diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp index 0509c08de..8efb5240a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp @@ -77,9 +77,9 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, port_coord.set_x(unique_mirror.get_cb_x(cb_type)); port_coord.set_y(unique_mirror.get_cb_y(cb_type)); } - std::string port_name = generate_routing_track_port_name(cb_type, - port_coord, itrack, - IN_PORT); + std::string port_name = generate_cb_module_track_port_name(cb_type, + itrack, + IN_PORT); /* Ensure we have this port in the module! */ ModulePortId module_port = module_manager.find_module_port(cb_module, port_name); @@ -108,9 +108,9 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, port_coord.set_x(unique_mirror.get_cb_x(cb_type)); port_coord.set_y(unique_mirror.get_cb_y(cb_type)); } - std::string port_name = generate_routing_track_port_name(cb_type, - port_coord, itrack, - OUT_PORT); + std::string port_name = generate_cb_module_track_port_name(cb_type, + itrack, + OUT_PORT); /* Ensure we have this port in the module! */ ModulePortId module_port = module_manager.find_module_port(cb_module, port_name); @@ -145,10 +145,8 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, } vtr::Point port_coord(ipin_node->xlow, ipin_node->ylow); - std::string port_name = generate_grid_side_port_name(grids, - port_coord, - rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), - ipin_node->ptc_num); + std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side, + ipin_node->ptc_num); /* Find the port in unique mirror! */ if (true == compact_routing_hierarchy) { @@ -158,10 +156,8 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, t_rr_node* unique_mirror_ipin_node = unique_mirror.get_ipin_node(cb_ipin_side, inode); port_coord.set_x(unique_mirror_ipin_node->xlow); port_coord.set_y(unique_mirror_ipin_node->ylow); - port_name = generate_grid_side_port_name(grids, - port_coord, - unique_mirror.get_ipin_node_grid_side(cb_ipin_side, inode), - unique_mirror_ipin_node->ptc_num); + port_name = generate_cb_module_grid_port_name(cb_ipin_side, + unique_mirror_ipin_node->ptc_num); } /* Ensure we have this port in the module! */ @@ -204,9 +200,9 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, port_coord.set_x(unique_mirror.get_cb_x(cb_type)); port_coord.set_y(unique_mirror.get_cb_y(cb_type)); } - std::string port_name = generate_routing_track_port_name(cb_type, - port_coord, itrack, - OUT_PORT); + std::string port_name = generate_cb_module_track_port_name(cb_type, + itrack, + OUT_PORT); /* Ensure we have this port in the module! */ ModulePortId module_port = module_manager.find_module_port(cb_module, port_name); @@ -327,9 +323,9 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, t_rr_node* chan_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack); vtr::Point port_coord(port_coordinate.get_x(), port_coordinate.get_y()); - std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, - port_coord, itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); + std::string port_name = generate_sb_module_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, + side_manager.get_side(), itrack, + rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); if (true == compact_routing_hierarchy) { /* Note: use GSB coordinate when inquire for unique modules!!! */ @@ -338,9 +334,9 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, DeviceCoordinator unique_port_coordinate = unique_mirror.get_side_block_coordinator(side_manager.get_side()); port_coord.set_x(unique_port_coordinate.get_x()); port_coord.set_y(unique_port_coordinate.get_y()); - port_name = generate_routing_track_port_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack)->type, - port_coord, itrack, - unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack)); + port_name = generate_sb_module_track_port_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack)->type, + side_manager.get_side(), itrack, + unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack)); } /* Ensure we have this port in the module! */ @@ -375,9 +371,9 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); - std::string port_name = generate_grid_side_port_name(grids, port_coord, - rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), - opin_node->ptc_num); + std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(), + rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), + opin_node->ptc_num); if (true == compact_routing_hierarchy) { /* Note: use GSB coordinate when inquire for unique modules!!! */ @@ -386,9 +382,9 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, port_coord.set_x(unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow); port_coord.set_y(unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow); - port_name = generate_grid_side_port_name(grids, port_coord, - unique_mirror.get_opin_node_grid_side(side_manager.get_side(), inode), - unique_mirror.get_opin_node(side_manager.get_side(), inode)->ptc_num); + port_name = generate_sb_module_grid_port_name(side_manager.get_side(), + unique_mirror.get_opin_node_grid_side(side_manager.get_side(), inode), + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ptc_num); } @@ -440,9 +436,9 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); - std::string port_name = generate_grid_side_port_name(grids, port_coord, - rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), - opin_node->ptc_num); + std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(), + rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), + opin_node->ptc_num); if (true == compact_routing_hierarchy) { /* Note: use GSB coordinate when inquire for unique modules!!! */ @@ -451,9 +447,9 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, port_coord.set_x(unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow); port_coord.set_y(unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow); - port_name = generate_grid_side_port_name(grids, port_coord, - unique_mirror.get_opin_node_grid_side(side_manager.get_side(), inode), - unique_mirror.get_opin_node(side_manager.get_side(), inode)->ptc_num); + port_name = generate_sb_module_grid_port_name(side_manager.get_side(), + unique_mirror.get_opin_node_grid_side(side_manager.get_side(), inode), + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ptc_num); } @@ -484,9 +480,9 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, t_rr_node* chan_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack); vtr::Point port_coord(port_coordinate.get_x(), port_coordinate.get_y()); - std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, - port_coord, itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); + std::string port_name = generate_sb_module_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, + side_manager.get_side(), itrack, + rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); if (true == compact_routing_hierarchy) { /* Note: use GSB coordinate when inquire for unique modules!!! */ @@ -496,9 +492,9 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, port_coord.set_x(unique_port_coordinate.get_x()); port_coord.set_y(unique_port_coordinate.get_y()); - port_name = generate_routing_track_port_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack)->type, - port_coord, itrack, - unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack)); + port_name = generate_sb_module_track_port_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack)->type, + side_manager.get_side(), itrack, + unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack)); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp index 8b3577ba1..5cac746ae 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp @@ -284,16 +284,66 @@ std::string generate_routing_track_port_name(const t_rr_type& chan_type, } /********************************************************************* - * Generate the port name for a routing track in a module + * Generate the port name for a routing track in a Switch Block module * This function is created to ease the PnR for each unique routing module * So it is mainly used when creating non-top-level modules! * Note that this function does not include any port coordinate + * Instead, we use the relative location of the pins in the context of routing modules * so that each module can be instanciated across the fabric * Even though, port direction must be provided! *********************************************************************/ -std::string generate_routing_module_track_port_name(const t_rr_type& chan_type, - const size_t& track_id, - const PORTS& port_direction) { +std::string generate_sb_module_track_port_name(const t_rr_type& chan_type, + const e_side& module_side, + const size_t& track_id, + const PORTS& port_direction) { + /* Channel must be either CHANX or CHANY */ + VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) ); + + /* Create a map between chan_type and module_prefix */ + std::map module_prefix_map; + /* TODO: use a constexpr string to replace the fixed name? */ + module_prefix_map[CHANX] = std::string("chanx"); + module_prefix_map[CHANY] = std::string("chany"); + + std::string port_name = module_prefix_map[chan_type]; + port_name += std::string("_"); + + Side side_manager(module_side); + port_name += std::string(side_manager.to_string()); + port_name += std::string("_"); + + switch (port_direction) { + case OUT_PORT: + port_name += std::string("out_"); + break; + case IN_PORT: + port_name += std::string("in_"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of chan_rr_node!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Add the track id to the port name */ + port_name += std::to_string(track_id) + std::string("_"); + + return port_name; +} + +/********************************************************************* + * Generate the port name for a routing track in a Connection Block module + * This function is created to ease the PnR for each unique routing module + * So it is mainly used when creating non-top-level modules! + * Note that this function does not include any port coordinate + * Instead, we use the relative location of the pins in the context of routing modules + * so that each module can be instanciated across the fabric + * Even though, port direction must be provided! + *********************************************************************/ +std::string generate_cb_module_track_port_name(const t_rr_type& chan_type, + const size_t& track_id, + const PORTS& port_direction) { /* Channel must be either CHANX or CHANY */ VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) ); @@ -424,16 +474,10 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, * To keep a short and simple name, this function will not * include any grid coorindate information! *********************************************************************/ -std::string generate_grid_module_port_name(const size_t& height, - const e_side& side, - const size_t& pin_id) { +std::string generate_grid_module_port_name(const size_t& pin_id) { /* For non-top netlist */ - Side side_manager(side); std::string port_name = std::string("grid_"); - port_name += std::string(side_manager.to_string()); - port_name += std::string("_height_"); - port_name += std::to_string(height); - port_name += std::string("__pin_"); + port_name += std::string("pin_"); port_name += std::to_string(pin_id); port_name += std::string("_"); return port_name; @@ -464,22 +508,67 @@ std::string generate_grid_side_port_name(const std::vector>& grids, - const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id) { - /* Output the pins on the side*/ - size_t height = find_grid_pin_height(grids, coordinate, pin_id); - if (1 != grids[coordinate.x()][coordinate.y()].type->pinloc[height][side][pin_id]) { - Side side_manager(side); - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Fail to generate a grid pin (x=%lu, y=%lu, height=%lu, side=%s, index=%d)\n", - __FILE__, __LINE__, - coordinate.x(), coordinate.y(), height, side_manager.c_str(), pin_id); - exit(1); - } - return generate_grid_module_port_name(height, side, pin_id); +std::string generate_sb_module_grid_port_name(const e_side& sb_side, + const e_side& grid_side, + const size_t& pin_id) { + Side sb_side_manager(sb_side); + Side grid_side_manager(grid_side); + /* Relative location is opposite to the side in grid context */ + grid_side_manager.set_opposite(); + std::string prefix = sb_side_manager.to_string() + std::string("_") + grid_side_manager.to_string(); + return prefix + std::string("_") + generate_grid_module_port_name(pin_id); +} + +/********************************************************************* + * Generate the port name of a grid pin for a routing module, + * which could be a switch block or a connection block + * Note that to ensure unique grid port name in the context of a routing module, + * we need a prefix which denotes the relative location of the port in the routing module + *********************************************************************/ +std::string generate_cb_module_grid_port_name(const e_side& cb_side, + const size_t& pin_id) { + Side side_manager(cb_side); + std::string prefix = side_manager.to_string(); + return prefix + std::string("_") + generate_grid_module_port_name(pin_id); } /********************************************************************* diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h index d83efcad2..d9df02e07 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h @@ -69,9 +69,14 @@ std::string generate_routing_track_port_name(const t_rr_type& chan_type, const size_t& track_id, const PORTS& port_direction); -std::string generate_routing_module_track_port_name(const t_rr_type& chan_type, - const size_t& track_id, - const PORTS& port_direction); +std::string generate_sb_module_track_port_name(const t_rr_type& chan_type, + const e_side& module_side, + const size_t& track_id, + const PORTS& port_direction); + +std::string generate_cb_module_track_port_name(const t_rr_type& chan_type, + const size_t& track_id, + const PORTS& port_direction); std::string generate_routing_track_middle_output_port_name(const t_rr_type& chan_type, const vtr::Point& coordinate, @@ -116,19 +121,14 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, const size_t& pin_id, const bool& for_top_netlist); -std::string generate_grid_module_port_name(const size_t& height, - const e_side& side, - const size_t& pin_id); +std::string generate_grid_module_port_name(const size_t& pin_id); -std::string generate_grid_side_port_name(const std::vector>& grids, - const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id); +std::string generate_sb_module_grid_port_name(const e_side& sb_side, + const e_side& grid_side, + const size_t& pin_id); -std::string generate_routing_module_grid_port_name(const std::vector>& grids, - const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id); +std::string generate_cb_module_grid_port_name(const e_side& cb_side, + const size_t& pin_id); std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index bd06d87d1..e9ca6f818 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -843,6 +843,7 @@ int RRGSB::get_node_index(t_rr_node* node, &&(node_direction == chan_node_direction_[side_manager.to_size_t()][inode])) { cnt++; ret = inode; + break; } } break; @@ -851,6 +852,7 @@ int RRGSB::get_node_index(t_rr_node* node, if (node == ipin_node_[side_manager.to_size_t()][inode]) { cnt++; ret = inode; + break; } } break; @@ -859,11 +861,14 @@ int RRGSB::get_node_index(t_rr_node* node, if (node == opin_node_[side_manager.to_size_t()][inode]) { cnt++; ret = inode; + break; } } break; default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid cur_rr_node type! Should be [CHANX|CHANY|IPIN|OPIN]\n", __FILE__, __LINE__); + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid cur_rr_node type! Should be [CHANX|CHANY|IPIN|OPIN]\n", + __FILE__, __LINE__); exit(1); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.cpp index a81eb567f..15d7ea872 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.cpp @@ -30,9 +30,9 @@ ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_mana DeviceCoordinator chan_rr_node_coordinator = rr_gsb.get_side_block_coordinator(chan_side); vtr::Point chan_port_coord(chan_rr_node_coordinator.get_x(), chan_rr_node_coordinator.get_y()); - std::string chan_port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(chan_side, index)->type, - chan_port_coord, index, - rr_gsb.get_chan_node_direction(chan_side, index)); + std::string chan_port_name = generate_sb_module_track_port_name(rr_gsb.get_chan_node(chan_side, index)->type, + chan_side, index, + rr_gsb.get_chan_node_direction(chan_side, index)); /* Must find a valid port id in the Switch Block module */ ModulePortId chan_port_id = module_manager.find_module_port(sb_module, chan_port_name); @@ -73,10 +73,14 @@ ModulePortId find_switch_block_module_input_port(const ModuleManager& module_man case OPIN: { /* Find the coordinator (grid_x and grid_y) for the input port */ vtr::Point input_port_coord(input_rr_node->xlow, input_rr_node->ylow); - std::string input_port_name = generate_grid_side_port_name(grids, - input_port_coord, - input_side, - input_rr_node->ptc_num); + + /* Find the side where the grid pin locates in the grid */ + enum e_side grid_pin_side = rr_gsb.get_opin_node_grid_side(input_rr_node); + VTR_ASSERT(NUM_SIDES != grid_pin_side); + + std::string input_port_name = generate_sb_module_grid_port_name(input_side, + grid_pin_side, + input_rr_node->ptc_num); /* Must find a valid port id in the Switch Block module */ input_port_id = module_manager.find_module_port(sb_module, input_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, input_port_id)); @@ -109,25 +113,14 @@ std::vector find_switch_block_module_input_ports(const ModuleManag std::vector input_ports; for (auto input_rr_node : input_rr_nodes) { + /* Find the side where the input locates in the Switch Block */ enum e_side input_pin_side = NUM_SIDES; - switch (input_rr_node->type) { - case OPIN: - input_pin_side = rr_gsb.get_opin_node_grid_side(input_rr_node); - break; - case CHANX: - case CHANY: { - /* The input could be at any side of the switch block, find it */ - int index = -1; - rr_gsb.get_node_side_and_index(input_rr_node, IN_PORT, &input_pin_side, &index); - VTR_ASSERT(NUM_SIDES != input_pin_side); - break; - } - default: /* SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } + /* The input could be at any side of the switch block, find it */ + int index = -1; + rr_gsb.get_node_side_and_index(input_rr_node, IN_PORT, &input_pin_side, &index); + VTR_ASSERT(NUM_SIDES != input_pin_side); + VTR_ASSERT(-1 != index); + input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, rr_gsb, grids, input_pin_side, input_rr_node)); } @@ -152,9 +145,9 @@ ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_ vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); int chan_node_track_id = rr_gsb.get_cb_chan_node_index(cb_type, chan_rr_node); /* Create a port description for the middle output */ - std::string input_port_name = generate_routing_track_port_name(cb_type, - port_coord, chan_node_track_id, - IN_PORT); + std::string input_port_name = generate_cb_module_track_port_name(cb_type, + chan_node_track_id, + IN_PORT); /* Must find a valid port id in the Switch Block module */ input_port_id = module_manager.find_module_port(cb_module, input_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, input_port_id)); @@ -189,10 +182,8 @@ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_ rr_gsb.get_node_side_and_index(src_rr_node, OUT_PORT, &cb_ipin_side, &cb_ipin_index); /* We need to be sure that drive_rr_node is part of the CB */ VTR_ASSERT((-1 != cb_ipin_index)&&(NUM_SIDES != cb_ipin_side)); - std::string port_name = generate_grid_side_port_name(grids, - port_coord, - rr_gsb.get_ipin_node_grid_side(cb_ipin_side, cb_ipin_index), - rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)->ptc_num); + std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side, + rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)->ptc_num); /* Must find a valid port id in the Switch Block module */ ModulePortId ipin_port_id = module_manager.find_module_port(cb_module, port_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index fcd0f93d2..642f23638 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -47,12 +47,14 @@ void build_switch_block_module_short_interc(ModuleManager& module_manager, /* Find the name of output port */ ModulePortId output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_gsb, chan_side, cur_rr_node, OUT_PORT); enum e_side input_pin_side = chan_side; + int index = -1; /* Generate the input port object */ switch (drive_rr_node->type) { - case OPIN: - input_pin_side = rr_gsb.get_opin_node_grid_side(drive_rr_node); + case OPIN: { + rr_gsb.get_node_side_and_index(drive_rr_node, IN_PORT, &input_pin_side, &index); break; + } case CHANX: case CHANY: { /* This should be an input in the data structure of RRGSB */ @@ -64,7 +66,6 @@ void build_switch_block_module_short_interc(ModuleManager& module_manager, input_pin_side = side_manager.get_opposite(); } else { /* The input could be at any side of the switch block, find it */ - int index = -1; rr_gsb.get_node_side_and_index(drive_rr_node, IN_PORT, &input_pin_side, &index); } break; @@ -341,9 +342,9 @@ void build_switch_block_module(ModuleManager& module_manager, for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { vtr::Point port_coord(port_coordinator.get_x(), port_coordinator.get_y()); - std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, - port_coord, itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); + std::string port_name = generate_sb_module_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, + side_manager.get_side(), itrack, + rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { @@ -369,9 +370,9 @@ void build_switch_block_module(ModuleManager& module_manager, for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); - std::string port_name = generate_grid_side_port_name(grids, port_coord, - rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num); + std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(), + rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), + rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num); BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ /* Grid outputs are inputs of switch blocks */ ModulePortId input_port_id = module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_INPUT_PORT); @@ -702,17 +703,17 @@ void build_connection_block_module(ModuleManager& module_manager, */ for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - std::string port_name = generate_routing_track_port_name(cb_type, - port_coord, itrack, - IN_PORT); + std::string port_name = generate_cb_module_track_port_name(cb_type, + itrack, + IN_PORT); BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_INPUT_PORT); } for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - std::string port_name = generate_routing_track_port_name(cb_type, - port_coord, itrack, - OUT_PORT); + std::string port_name = generate_cb_module_track_port_name(cb_type, + itrack, + OUT_PORT); BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); } @@ -724,10 +725,8 @@ void build_connection_block_module(ModuleManager& module_manager, for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { t_rr_node* ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); vtr::Point port_coord(ipin_node->xlow, ipin_node->ylow); - std::string port_name = generate_grid_side_port_name(grids, - port_coord, - rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), - ipin_node->ptc_num); + std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side, + ipin_node->ptc_num); BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ /* Grid outputs are inputs of switch blocks */ module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); @@ -747,16 +746,16 @@ void build_connection_block_module(ModuleManager& module_manager, for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); /* Create a port description for the input */ - std::string input_port_name = generate_routing_track_port_name(cb_type, - port_coord, itrack, - IN_PORT); + std::string input_port_name = generate_cb_module_track_port_name(cb_type, + itrack, + IN_PORT); ModulePortId input_port_id = module_manager.find_module_port(cb_module, input_port_name); BasicPort input_port = module_manager.module_port(cb_module, input_port_id); /* Create a port description for the output */ - std::string output_port_name = generate_routing_track_port_name(cb_type, - port_coord, itrack, - OUT_PORT); + std::string output_port_name = generate_cb_module_track_port_name(cb_type, + itrack, + OUT_PORT); ModulePortId output_port_id = module_manager.find_module_port(cb_module, output_port_name); BasicPort output_port = module_manager.module_port(cb_module, output_port_id); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp index a8e3543e5..6011dd94f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -428,9 +428,9 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, /* Collect sink-related information */ vtr::Point sink_sb_port_coord(module_sb.get_opin_node(side_manager.get_side(), inode)->xlow, module_sb.get_opin_node(side_manager.get_side(), inode)->ylow); - std::string sink_sb_port_name = generate_grid_side_port_name(grids, sink_sb_port_coord, - module_sb.get_opin_node_grid_side(side_manager.get_side(), inode), - src_grid_pin_index); + std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(), + module_sb.get_opin_node_grid_side(side_manager.get_side(), inode), + src_grid_pin_index); ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id)); BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id); @@ -557,9 +557,8 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, /* Collect source-related information */ t_rr_node* module_ipin_node = module_cb.get_ipin_node(cb_ipin_side, inode); vtr::Point cb_src_port_coord(module_ipin_node->xlow, module_ipin_node->ylow); - std::string src_cb_port_name = generate_grid_side_port_name(grids, cb_src_port_coord, - module_cb.get_ipin_node_grid_side(cb_ipin_side, inode), - module_ipin_node->ptc_num); + std::string src_cb_port_name = generate_cb_module_grid_port_name(cb_ipin_side, + module_ipin_node->ptc_num); ModulePortId src_cb_port_id = module_manager.find_module_port(src_cb_module, src_cb_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, src_cb_port_id)); BasicPort src_cb_port = module_manager.module_port(src_cb_module, src_cb_port_id); @@ -716,10 +715,9 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, size_t cb_instance = cb_instance_ids.at(cb_type)[instance_cb_coordinate.x()][instance_cb_coordinate.y()]; for (size_t itrack = 0; itrack < module_sb.get_chan_width(side_manager.get_side()); ++itrack) { - vtr::Point sb_port_coord(port_coordinator.get_x(), port_coordinator.get_y()); - std::string sb_port_name = generate_routing_track_port_name(module_sb.get_chan_node(side_manager.get_side(), itrack)->type, - sb_port_coord, itrack, - module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); + std::string sb_port_name = generate_sb_module_track_port_name(module_sb.get_chan_node(side_manager.get_side(), itrack)->type, + side_manager.get_side(), itrack, + module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); /* Prepare SB-related port information */ ModulePortId sb_port_id = module_manager.find_module_port(sb_module_id, sb_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module_id, sb_port_id)); @@ -733,10 +731,9 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, } else { VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); } - vtr::Point cb_port_coord(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type)); - std::string cb_port_name = generate_routing_track_port_name(cb_type, - cb_port_coord, itrack, - cb_port_direction); + std::string cb_port_name = generate_cb_module_track_port_name(cb_type, + itrack, + cb_port_direction); ModulePortId cb_port_id = module_manager.find_module_port(cb_module_id, cb_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module_id, cb_port_id)); BasicPort cb_port = module_manager.module_port(cb_module_id, cb_port_id);