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[Tool] Add signal_init option to preconfigured fabric wrapper writer

This commit is contained in:
tangxifan 2021-06-24 17:07:41 -06:00
parent 779437cd37
commit 5364d8104f
2 changed files with 5 additions and 0 deletions
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2
openfpga/src/base/openfpga_verilog.cpp
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@ -128,6 +128,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type"); CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator"); CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
CommandOptionId opt_verbose = cmd.option("verbose"); CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -139,6 +140,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator)); options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
options.set_print_formal_verification_top_netlist(true); options.set_print_formal_verification_top_netlist(true);
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) { if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));

3
openfpga/src/base/openfpga_verilog_command.cpp
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@ -149,6 +149,9 @@ ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga:
/* Add an option '--support_icarus_simulator' */ /* Add an option '--support_icarus_simulator' */
shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator"); shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator");
/* add an option '--include_signal_init' */
shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
/* add an option '--verbose' */ /* add an option '--verbose' */
shell_cmd.add_option("verbose", false, "enable verbose output"); shell_cmd.add_option("verbose", false, "enable verbose output");