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Added 'spice_simulator_path' in fpga_flow 

added vpr_fpga_spice_simulator_path in fpga-flow script
This commit is contained in:
Ganesh Gore 2019-07-03 12:30:56 -06:00
parent 54f6ca2687
commit 53486b8a89
1 changed files with 9 additions and 9 deletions
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18
fpga_flow/scripts/fpga_flow.pl
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@ -168,6 +168,7 @@ sub print_usage()
print " \t-vpr_fpga_spice_leakage_only : turn on leakage_only mode in VPR FPGA SPICE\n"; print " \t-vpr_fpga_spice_leakage_only : turn on leakage_only mode in VPR FPGA SPICE\n";
print " \t-vpr_fpga_spice_parasitic_net_estimation_off : turn off parasitic_net_estimation in VPR FPGA SPICE\n"; print " \t-vpr_fpga_spice_parasitic_net_estimation_off : turn off parasitic_net_estimation in VPR FPGA SPICE\n";
print " \t-vpr_fpga_spice_testbench_load_extraction_off : turn off testbench_load_extraction in VPR FPGA SPICE\n"; print " \t-vpr_fpga_spice_testbench_load_extraction_off : turn off testbench_load_extraction in VPR FPGA SPICE\n";
print " \t-vpr_fpga_spice_simulator_path <string> : Specify simulator path\n";
print " [ VPR - FPGA-Verilog Extension ] \n"; print " [ VPR - FPGA-Verilog Extension ] \n";
print " \t-vpr_fpga_verilog : turn on Verilog Generator of VPR FPGA SPICE\n"; print " \t-vpr_fpga_verilog : turn on Verilog Generator of VPR FPGA SPICE\n";
print " \t-vpr_fpga_verilog_dir <verilog_path>: provide the path where generated verilog files will be written\n"; print " \t-vpr_fpga_verilog_dir <verilog_path>: provide the path where generated verilog files will be written\n";
@ -274,8 +275,7 @@ sub read_opt_into_hash($ $ $)
sub opts_read() sub opts_read()
{ {
# if no arguments detected, print the usage. # if no arguments detected, print the usage.
if (-1 == $#ARGV) if (-1 == $#ARGV) {
{
print "Error : No input arguments!\n"; print "Error : No input arguments!\n";
print "Help desk:\n"; print "Help desk:\n";
&print_usage(); &print_usage();
@ -289,19 +289,15 @@ sub opts_read()
my $argfd; my $argfd;
# Check help fist # Check help fist
$argfd = &spot_option($cur_arg,"-help"); $argfd = &spot_option($cur_arg,"-help");
if (-1 != $argfd) if (-1 != $argfd) {
{
print "Help desk:\n"; print "Help desk:\n";
&print_usage(); &print_usage();
} }
# Then Check the debug with highest priority # Then Check the debug with highest priority
$argfd = &spot_option($cur_arg,"-debug"); $argfd = &spot_option($cur_arg,"-debug");
if (-1 != $argfd) if (-1 != $argfd) {
{
$opt_ptr->{"debug"} = "on"; $opt_ptr->{"debug"} = "on";
} } else {
else
{
$opt_ptr->{"debug"} = "off"; $opt_ptr->{"debug"} = "off";
} }
# Check mandatory options # Check mandatory options
@ -350,6 +346,7 @@ sub opts_read()
&read_opt_into_hash("vpr_fpga_spice_leakage_only","off","off"); &read_opt_into_hash("vpr_fpga_spice_leakage_only","off","off");
&read_opt_into_hash("vpr_fpga_spice_parasitic_net_estimation_off","off","off"); &read_opt_into_hash("vpr_fpga_spice_parasitic_net_estimation_off","off","off");
&read_opt_into_hash("vpr_fpga_spice_testbench_load_extraction_off","off","off"); &read_opt_into_hash("vpr_fpga_spice_testbench_load_extraction_off","off","off");
&read_opt_into_hash("vpr_fpga_spice_simulator_path","on","off");
# FPGA-Verilog options # FPGA-Verilog options
# Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory"
@ -1331,6 +1328,9 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) { if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}"; $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}";
} }
if ("on" eq $opt_ptr->{vpr_fpga_spice_simulator_path}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_spice_simulator_path $opt_ptr->{vpr_fpga_spice_simulator_path_val}";
}
if ("on" eq $opt_ptr->{vpr_fpga_spice_print_component_tb}) { if ("on" eq $opt_ptr->{vpr_fpga_spice_print_component_tb}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_lut_testbench"; $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_lut_testbench";
$vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_hardlogic_testbench"; $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_hardlogic_testbench";