From 51f54bbf20fe40b3e0e154e38b7d5d1a1a1a5140 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 27 Sep 2022 16:54:48 -0700
Subject: [PATCH] [engine] developing the steps to annotate clustering results

---
 .../src/annotation/annotate_clustering.cpp    | 44 +++++++++++++++++++
 openfpga/src/annotation/annotate_clustering.h | 23 ++++++++++
 openfpga/src/base/openfpga_link_arch.cpp      |  6 +++
 openfpga/src/base/openfpga_pb_pin_fixup.cpp   |  2 +
 4 files changed, 75 insertions(+)
 create mode 100644 openfpga/src/annotation/annotate_clustering.cpp
 create mode 100644 openfpga/src/annotation/annotate_clustering.h

diff --git a/openfpga/src/annotation/annotate_clustering.cpp b/openfpga/src/annotation/annotate_clustering.cpp
new file mode 100644
index 000000000..c806a03d3
--- /dev/null
+++ b/openfpga/src/annotation/annotate_clustering.cpp
@@ -0,0 +1,44 @@
+/********************************************************************
+ * This file includes functions that are used to annotate clustering results
+ * from VPR to OpenFPGA
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_geometry.h"
+
+#include "annotate_clustering.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/* @brief Record the net remapping and local routing trace changes in annotation 
+ * This is to ensure that the clustering annotation data structure is always up-to-date
+ */
+void annotate_post_routing_cluster_sync_results(const DeviceContext& device_ctx, 
+                                                const ClusteringContext& cluster_ctx, 
+                                                VprClusteringAnnotation& cluster_annotation) {
+  VTR_LOG("Building annotation for post-routing and clustering synchornization results...");
+
+  for (const ClusterBlockId& cluster_blk_id : cluster_ctx.clb_nlist.blocks()) {
+    /* Skip invalid ids */
+    if (!cluster_blk_id) {
+      continue;
+    }
+    auto logical_block = clustering_ctx.clb_nlist.block_type(cluster_blk_id);
+    for (int ipin = 0; ipin < logical_block->pb_type->num_pins; ++ipin) {
+      ClusterNetId pre_routing_net_id = clustering_ctx.clb_nlist.block_net(cluster_blk_id, ipin);
+      ClusterNetId post_routing_net_id = ClusterNetId::INVALID();
+      auto search_result = clustering_ctx.post_routing_clb_pin_nets[cluster_blk_id].find(ipin);
+      if (search_result != clustering_ctx.post_routing_clb_pin_nets[cluster_blk_id].end()) {
+        post_routing_net_id = search_result->second;
+      }
+      if (post_routing_net_id) {
+        vpr_clustering_annotation.rename_net(cluster_blk_id, ipin, post_routing_net_id);
+      }
+    }
+  } 
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/annotation/annotate_clustering.h b/openfpga/src/annotation/annotate_clustering.h
new file mode 100644
index 000000000..f9229ce4e
--- /dev/null
+++ b/openfpga/src/annotation/annotate_clustering.h
@@ -0,0 +1,23 @@
+#ifndef ANNOTATE_CLUSTERING_H
+#define ANNOTATE_CLUSTERING_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "vpr_clustering_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void annotate_post_routing_cluster_sync_results(const DeviceContext& device_ctx, 
+                                                const ClusteringContext& cluster_ctx, 
+                                                VprClusteringAnnotation& cluster_annotation);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp
index 14991adec..b45ed1533 100644
--- a/openfpga/src/base/openfpga_link_arch.cpp
+++ b/openfpga/src/base/openfpga_link_arch.cpp
@@ -25,6 +25,7 @@
 #include "annotate_bitstream_setting.h"
 #include "mux_library_builder.h"
 #include "build_tile_direct.h"
+#include "annotate_clustering.h"
 #include "annotate_placement.h"
 #include "openfpga_link_arch.h"
 
@@ -155,6 +156,11 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
                                                                 openfpga_ctx.arch().arch_direct,
                                                                 cmd_context.option_enable(cmd, opt_verbose));
 
+  /* Annotate clustering results */
+  annotate_post_routing_cluster_sync_results(g_vpr_ctx.device(),
+                                             g_vpr_ctx.clustering(),
+                                             openfpga_ctx.mutable_vpr_clustering_annotation());
+
   /* Annotate placement results */
   annotate_mapped_blocks(g_vpr_ctx.device(), 
                          g_vpr_ctx.clustering(),
diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
index 8a0278266..cdd1073be 100644
--- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
@@ -101,6 +101,7 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
      * This is important because we cannot bypass when router forces a valid net to be mapped
      * and the net remapping has to be considered
      */
+    /*
     if ( (ClusterNetId::INVALID() != cluster_net_id)
       && (ClusterNetId::INVALID() == routing_net_id)
       && (true == clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id))) {
@@ -114,6 +115,7 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
                );
       continue;
     }
+    */
 
     /* Ignore used in local cluster only, reserved one CLB pin */
     if ( (ClusterNetId::INVALID() != cluster_net_id)