diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index d8069f903..55dfe8130 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -942,11 +942,6 @@ bool CircuitLibrary::port_is_config_enable(const CircuitPortId& circuit_port_id) return port_is_config_enable_[circuit_port_id]; } -bool CircuitLibrary::port_is_edge_triggered(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_is_edge_triggered_[circuit_port_id]; -} /* Return a flag if the port is used during programming a FPGA in a circuit model */ bool CircuitLibrary::port_is_prog(const CircuitPortId& circuit_port_id) const { @@ -1380,7 +1375,6 @@ CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id, port_is_reset_.push_back(false); port_is_set_.push_back(false); port_is_config_enable_.push_back(false); - port_is_edge_triggered_.push_back(false); port_is_prog_.push_back(false); port_tri_state_model_names_.emplace_back(); port_tri_state_model_ids_.push_back(CircuitModelId::INVALID()); @@ -1500,15 +1494,6 @@ void CircuitLibrary::set_port_is_config_enable(const CircuitPortId& circuit_port return; } -/* Set the is_edge_triggered for a port of a circuit model */ -void CircuitLibrary::set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, - const bool& is_edge_triggered) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_is_edge_triggered_[circuit_port_id] = is_edge_triggered; - return; -} - /* Set the is_prog for a port of a circuit model */ void CircuitLibrary::set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog) { diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h index f4b742a27..bd082f738 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.h +++ b/libopenfpga/libarchopenfpga/src/circuit_library.h @@ -91,16 +91,15 @@ * 9. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches - * 12. port_is_edge_triggered: specify if this port is triggerd by edges like the clock signal of a D-type flip-flop - * 13. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches - * 14. port_tri_state_model_name: the name of circuit model linked to tri-state the port - * 15. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port - * 16. port_inv_model_names_: the name of inverter circuit model linked to the port - * 17. port_inv_model_ids_: the Id of inverter circuit model linked to the port - * 18. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port - * 19. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used - * 20. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used - * 21. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains + * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches + * 13. port_tri_state_model_name: the name of circuit model linked to tri-state the port + * 14. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port + * 15. port_inv_model_names_: the name of inverter circuit model linked to the port + * 16. port_inv_model_ids_: the Id of inverter circuit model linked to the port + * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port + * 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used + * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used + * 20. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains * * ------ Delay information ------ * 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge @@ -285,7 +284,6 @@ class CircuitLibrary { bool port_is_reset(const CircuitPortId& circuit_port_id) const; bool port_is_set(const CircuitPortId& circuit_port_id) const; bool port_is_config_enable(const CircuitPortId& circuit_port_id) const; - bool port_is_edge_triggered(const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitPortId& circuit_port_id) const; size_t port_lut_frac_level(const CircuitPortId& circuit_port_id) const; std::vector port_lut_output_mask(const CircuitPortId& circuit_port_id) const; @@ -366,8 +364,6 @@ class CircuitLibrary { const bool& is_set); void set_port_is_config_enable(const CircuitPortId& circuit_port_id, const bool& is_config_enable); - void set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, - const bool& is_edge_triggered); void set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog); void set_port_tri_state_model_name(const CircuitPortId& circuit_port_id, @@ -554,7 +550,6 @@ class CircuitLibrary { vtr::vector port_is_reset_; vtr::vector port_is_set_; vtr::vector port_is_config_enable_; - vtr::vector port_is_edge_triggered_; vtr::vector port_is_prog_; vtr::vector port_tri_state_model_names_; vtr::vector port_tri_state_model_ids_; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index 4136b0463..36e837814 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -564,9 +564,6 @@ void read_xml_circuit_port(pugi::xml_node& xml_port, /* Identify if the port is to enable programming for FPGAs, by default it is NOT */ circuit_lib.set_port_is_config_enable(port, get_attribute(xml_port, "is_config_enable", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); - /* Identify if the port is to triggered by edges, by default it is NOT */ - circuit_lib.set_port_is_edge_triggered(port, get_attribute(xml_port, "is_edge_triggered", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); - /* Find the name of circuit model that this port is linked to */ circuit_lib.set_port_tri_state_model_name(port, get_attribute(xml_port, "circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string()); diff --git a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp index 9165725e2..b141b0fe2 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp @@ -207,10 +207,6 @@ void write_xml_circuit_port(std::fstream& fp, write_xml_attribute(fp, "is_config_enable", "true"); } - if (true == circuit_lib.port_is_edge_triggered(port)) { - write_xml_attribute(fp, "is_edge_triggered", "true"); - } - /* Output the name of circuit model that this port is linked to */ if (!circuit_lib.port_tri_state_model_name(port).empty()) { write_xml_attribute(fp, "circuit_model_name", circuit_lib.port_tri_state_model_name(port).c_str());