From 9c19e2b365dcbb32baecf4f789fdc1296190d860 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Feb 2021 11:55:47 -0700 Subject: [PATCH 1/3] [Test] Move regression test scripts from workflow to openfpga_flow --- .github/workflows/build.yml | 4 ++-- .../regression_test_scripts}/basic_reg_test.sh | 0 .../regression_test_scripts}/fpga_bitstream_reg_test.sh | 0 .../regression_test_scripts}/fpga_sdc_reg_test.sh | 0 .../regression_test_scripts}/fpga_spice_reg_test.sh | 0 .../regression_test_scripts}/fpga_verilog_reg_test.sh | 0 .../regression_test_scripts}/quicklogic_reg_test.sh | 0 7 files changed, 2 insertions(+), 2 deletions(-) rename {.github/workflows => openfpga_flow/regression_test_scripts}/basic_reg_test.sh (100%) rename {.github/workflows => openfpga_flow/regression_test_scripts}/fpga_bitstream_reg_test.sh (100%) rename {.github/workflows => openfpga_flow/regression_test_scripts}/fpga_sdc_reg_test.sh (100%) rename {.github/workflows => openfpga_flow/regression_test_scripts}/fpga_spice_reg_test.sh (100%) rename {.github/workflows => openfpga_flow/regression_test_scripts}/fpga_verilog_reg_test.sh (100%) rename {.github/workflows => openfpga_flow/regression_test_scripts}/quicklogic_reg_test.sh (100%) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 11616f4f0..d8e42b28b 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -230,7 +230,7 @@ jobs: chmod +x yosys/yosys-smtbmc - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 18.04) shell: bash - run: source openfpga.sh && source .github/workflows/${{matrix.config.name}}.sh + run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh - name: Upload artifact uses: actions/upload-artifact@v2 if: ${{ failure() }} @@ -266,7 +266,7 @@ jobs: bash .github/workflows/install_dependencies_run.sh ${PYTHON_EXEC} -m pip install -r requirements.txt rsync -am --exclude='openfpga_flow/**' /opt/openfpga/. . - source openfpga.sh && source .github/workflows/${{matrix.config.name}}.sh + source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh - name: Upload artifact uses: actions/upload-artifact@v2 if: ${{ failure() }} diff --git a/.github/workflows/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh similarity index 100% rename from .github/workflows/basic_reg_test.sh rename to openfpga_flow/regression_test_scripts/basic_reg_test.sh diff --git a/.github/workflows/fpga_bitstream_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh similarity index 100% rename from .github/workflows/fpga_bitstream_reg_test.sh rename to openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh diff --git a/.github/workflows/fpga_sdc_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh similarity index 100% rename from .github/workflows/fpga_sdc_reg_test.sh rename to openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh diff --git a/.github/workflows/fpga_spice_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_spice_reg_test.sh similarity index 100% rename from .github/workflows/fpga_spice_reg_test.sh rename to openfpga_flow/regression_test_scripts/fpga_spice_reg_test.sh diff --git a/.github/workflows/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh similarity index 100% rename from .github/workflows/fpga_verilog_reg_test.sh rename to openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh diff --git a/.github/workflows/quicklogic_reg_test.sh b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh similarity index 100% rename from .github/workflows/quicklogic_reg_test.sh rename to openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh From 2c2e49373936d2270fd265a03b79f20723d901ab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Feb 2021 12:29:10 -0700 Subject: [PATCH 2/3] [Test] Remove quicklogic test from basic tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 2f1c7b5b7..591883df0 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -114,9 +114,6 @@ run-task basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_l run-task basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs run-task basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_logs -echo -e "Testing yosys flow using custom ys script for running quicklogic device"; -run-task quicklogic_tests/flow_test --debug --show_thread_logs - # Repgression test to test multi-user enviroment cp -r */*/basic_tests/full_testbench/configuration_chain /tmp/ -cd /tmp/ && run-task configuration_chain --debug --show_thread_logs \ No newline at end of file +cd /tmp/ && run-task configuration_chain --debug --show_thread_logs From a819375f697312cf04aac5a698792ac209f6bcba Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Feb 2021 16:53:13 -0700 Subject: [PATCH 3/3] [Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled --- openfpga_flow/scripts/run_fpga_flow.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 26116f0ec..66472e3c8 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -260,9 +260,13 @@ def main(): if args.power: run_ace2() run_pro_blif_3arg() - run_rewrite_verilog() else: + # Make a copy of the blif file to be compatible with vpr flow shutil.copy(args.top_module+'_yosys_out.blif', args.top_module+".blif") + + # Always Generate the post-synthesis verilog files + run_rewrite_verilog() + if (args.fpga_flow == "vpr_blif"): collect_files_for_vpr() logger.info("Runing OpenFPGA Shell Engine ")