diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 11616f4f0..d8e42b28b 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -230,7 +230,7 @@ jobs:
           chmod +x yosys/yosys-smtbmc
       - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 18.04)
         shell: bash
-        run: source openfpga.sh && source .github/workflows/${{matrix.config.name}}.sh
+        run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh
       - name: Upload artifact
         uses: actions/upload-artifact@v2
         if: ${{ failure() }}
@@ -266,7 +266,7 @@ jobs:
           bash .github/workflows/install_dependencies_run.sh
           ${PYTHON_EXEC} -m pip install -r requirements.txt
           rsync -am --exclude='openfpga_flow/**' /opt/openfpga/. .
-          source openfpga.sh && source .github/workflows/${{matrix.config.name}}.sh
+          source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh
       - name: Upload artifact
         uses: actions/upload-artifact@v2
         if: ${{ failure() }}
diff --git a/.github/workflows/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
similarity index 98%
rename from .github/workflows/basic_reg_test.sh
rename to openfpga_flow/regression_test_scripts/basic_reg_test.sh
index 2f1c7b5b7..591883df0 100755
--- a/.github/workflows/basic_reg_test.sh
+++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
@@ -114,9 +114,6 @@ run-task basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_l
 run-task basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs
 run-task basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_logs
 
-echo -e "Testing yosys flow using custom ys script for running quicklogic device";
-run-task quicklogic_tests/flow_test --debug --show_thread_logs
-
 # Repgression test to test multi-user enviroment
 cp -r */*/basic_tests/full_testbench/configuration_chain /tmp/
-cd /tmp/ && run-task configuration_chain --debug --show_thread_logs
\ No newline at end of file
+cd /tmp/ && run-task configuration_chain --debug --show_thread_logs
diff --git a/.github/workflows/fpga_bitstream_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh
similarity index 100%
rename from .github/workflows/fpga_bitstream_reg_test.sh
rename to openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh
diff --git a/.github/workflows/fpga_sdc_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh
similarity index 100%
rename from .github/workflows/fpga_sdc_reg_test.sh
rename to openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh
diff --git a/.github/workflows/fpga_spice_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_spice_reg_test.sh
similarity index 100%
rename from .github/workflows/fpga_spice_reg_test.sh
rename to openfpga_flow/regression_test_scripts/fpga_spice_reg_test.sh
diff --git a/.github/workflows/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
similarity index 100%
rename from .github/workflows/fpga_verilog_reg_test.sh
rename to openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
diff --git a/.github/workflows/quicklogic_reg_test.sh b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh
similarity index 100%
rename from .github/workflows/quicklogic_reg_test.sh
rename to openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh
diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index 26116f0ec..66472e3c8 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -260,9 +260,13 @@ def main():
         if args.power:
             run_ace2()
             run_pro_blif_3arg()
-            run_rewrite_verilog()
         else: 
+            # Make a copy of the blif file to be compatible with vpr flow
             shutil.copy(args.top_module+'_yosys_out.blif', args.top_module+".blif")
+
+        # Always Generate the post-synthesis verilog files
+        run_rewrite_verilog()
+
     if (args.fpga_flow == "vpr_blif"):
         collect_files_for_vpr()
     logger.info("Runing OpenFPGA Shell Engine ")