From 50cc4dfba3d6a835800538dc0ae65877af42346f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 27 Jul 2020 17:18:59 -0600 Subject: [PATCH] classify regression test to dedicated categories --- .travis/basic_reg_test.sh | 28 +++++----- .travis/fpga_sdc_reg_test.sh | 2 +- .travis/fpga_verilog_reg_test.sh | 52 +++++++++---------- .../config/task.conf | 0 .../configuration_chain/config/task.conf | 0 .../configuration_frame/config/task.conf | 0 .../fast_configuration_chain/config/task.conf | 0 .../fast_configuration_frame/config/task.conf | 0 .../fast_memory_bank/config/task.conf | 0 .../flatten_memory/config/task.conf | 0 .../memory_bank/config/task.conf | 0 .../generate_fabric/config/task.conf | 0 .../generate_testbench/config/task.conf | 0 .../configuration_chain/config/task.conf | 0 .../configuration_frame/config/task.conf | 0 .../flatten_memory/config/task.conf | 0 .../memory_bank/config/task.conf | 0 .../sdc_time_unit/config/task.conf | 0 .../behavioral_verilog/config/task.conf | 0 .../bram/dpram16k/config/task.conf | 0 .../bram/wide_dpram16k/config/task.conf | 0 .../depopulate_crossbar/config/task.conf | 0 .../duplicated_grid_pin/config/task.conf | 0 .../fabric_chain/adder_chain/config/task.conf | 0 .../register_chain/config/task.conf | 0 .../fabric_chain/scan_chain/config/task.conf | 0 .../generate_random_key/config/task.conf | 0 .../generate_vanilla_key/config/task.conf | 0 .../load_external_key/config/task.conf | 0 .../config/task.conf | 19 +++---- .../flatten_routing/config/task.conf | 0 .../hard_adder/config/task.conf | 0 .../implicit_verilog/config/task.conf | 0 .../io/aib/config/task.conf | 0 .../io/multi_io_capacity/config/task.conf | 0 .../io/reduced_io/config/task.conf | 0 .../lut_design/frac_lut/config/task.conf | 0 .../intermediate_buffer/config/task.conf | 0 .../lut_design/single_mode/config/task.conf | 0 .../mux_design/local_encoder/config/task.conf | 0 .../mux_design/stdcell_mux2/config/task.conf | 0 .../tree_structure/config/task.conf | 0 .../power_gated_inverter/config/task.conf | 0 .../spypad/config/task.conf | 0 .../untileable/config/task.conf | 0 45 files changed, 51 insertions(+), 50 deletions(-) rename openfpga_flow/tasks/{ => basic_tests}/fixed_simulation_settings/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/configuration_chain/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/configuration_frame/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/fast_configuration_chain/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/fast_configuration_frame/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/fast_memory_bank/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/flatten_memory/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/memory_bank/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/generate_fabric/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/generate_testbench/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/preconfig_testbench/configuration_chain/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/preconfig_testbench/configuration_frame/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/preconfig_testbench/flatten_memory/config/task.conf (100%) rename openfpga_flow/tasks/{ => basic_tests}/preconfig_testbench/memory_bank/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_sdc}/sdc_time_unit/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/behavioral_verilog/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/bram/dpram16k/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/bram/wide_dpram16k/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/depopulate_crossbar/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/duplicated_grid_pin/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/fabric_chain/adder_chain/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/fabric_chain/register_chain/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/fabric_chain/scan_chain/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/fabric_key/generate_random_key/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/fabric_key/generate_vanilla_key/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/fabric_key/load_external_key/config/task.conf (100%) rename openfpga_flow/tasks/{ncounter => fpga_verilog/fabric_key/load_external_key_cc_fpga}/config/task.conf (57%) rename openfpga_flow/tasks/{ => fpga_verilog}/flatten_routing/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/hard_adder/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/implicit_verilog/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/io/aib/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/io/multi_io_capacity/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/io/reduced_io/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/lut_design/frac_lut/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/lut_design/intermediate_buffer/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/lut_design/single_mode/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/mux_design/local_encoder/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/mux_design/stdcell_mux2/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/mux_design/tree_structure/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/power_gated_design/power_gated_inverter/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/spypad/config/task.conf (100%) rename openfpga_flow/tasks/{ => fpga_verilog}/untileable/config/task.conf (100%) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index b8f6e2efd..ff29f7b71 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -11,31 +11,31 @@ cd ${TRAVIS_BUILD_DIR} echo -e "Basic regression tests"; echo -e "Testing configuration chain of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/fast_configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py preconfig_testbench/configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/fast_configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py preconfig_testbench/configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/fast_memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py preconfig_testbench/memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/flatten_memory --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py preconfig_testbench/flatten_memory --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs echo -e "Testing fabric Verilog generation only"; -python3 openfpga_flow/scripts/run_fpga_task.py generate_fabric --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs echo -e "Testing Verilog testbench generation only"; -python3 openfpga_flow/scripts/run_fpga_task.py generate_testbench --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; -python3 openfpga_flow/scripts/run_fpga_task.py fixed_simulation_settings --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs end_section "OpenFPGA.TaskTun" diff --git a/.travis/fpga_sdc_reg_test.sh b/.travis/fpga_sdc_reg_test.sh index 984199312..70dd34809 100755 --- a/.travis/fpga_sdc_reg_test.sh +++ b/.travis/fpga_sdc_reg_test.sh @@ -11,6 +11,6 @@ cd ${TRAVIS_BUILD_DIR} echo -e "FPGA-SDC regression tests"; echo -e "Testing SDC generation with time units"; -python3 openfpga_flow/scripts/run_fpga_task.py sdc_time_unit --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_sdc/sdc_time_unit --debug --show_thread_logs end_section "OpenFPGA.TaskTun" diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index c9cab90f7..7ee1a5095 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -11,80 +11,80 @@ cd ${TRAVIS_BUILD_DIR} echo -e "FPGA-Verilog Feature Tests"; echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks"; -python3 openfpga_flow/scripts/run_fpga_task.py lut_design/single_mode --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 "; -python3 openfpga_flow/scripts/run_fpga_task.py lut_design/frac_lut --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut --debug --show_thread_logs echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers"; -python3 openfpga_flow/scripts/run_fpga_task.py lut_design/intermediate_buffer --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs echo -e "Testing Verilog generation with VPR's untileable routing architecture "; -python3 openfpga_flow/scripts/run_fpga_task.py untileable --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/untileable --debug --show_thread_logs echo -e "Testing Verilog generation with hard adder chain in CLBs "; -python3 openfpga_flow/scripts/run_fpga_task.py hard_adder --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/hard_adder --debug --show_thread_logs echo -e "Testing Verilog generation with 16k block RAMs "; -python3 openfpga_flow/scripts/run_fpga_task.py bram/dpram16k --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/dpram16k --debug --show_thread_logs echo -e "Testing Verilog generation with 16k block RAMs spanning two columns "; -python3 openfpga_flow/scripts/run_fpga_task.py bram/wide_dpram16k --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA "; -python3 openfpga_flow/scripts/run_fpga_task.py io/multi_io_capacity --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity --debug --show_thread_logs echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA "; -python3 openfpga_flow/scripts/run_fpga_task.py io/reduced_io --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs echo -e "Testing Verilog generation with adder chain across an FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py fabric_chain/adder_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs echo -e "Testing Verilog generation with shift register chain across an FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py fabric_chain/register_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs echo -e "Testing Verilog generation with scan chain across an FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py fabric_chain/scan_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure"; -python3 openfpga_flow/scripts/run_fpga_task.py mux_design/tree_structure --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/tree_structure --debug --show_thread_logs echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2"; -python3 openfpga_flow/scripts/run_fpga_task.py mux_design/stdcell_mux2 --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders"; -python3 openfpga_flow/scripts/run_fpga_task.py mux_design/local_encoder --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs echo -e "Testing Verilog generation with behavioral description"; -python3 openfpga_flow/scripts/run_fpga_task.py behavioral_verilog --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs echo -e "Testing implicit Verilog generation"; -python3 openfpga_flow/scripts/run_fpga_task.py implicit_verilog --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/implicit_verilog --debug --show_thread_logs echo -e "Testing Verilog generation with flatten routing modules"; -python3 openfpga_flow/scripts/run_fpga_task.py flatten_routing --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/flatten_routing --debug --show_thread_logs echo -e "Testing Verilog generation with duplicated grid output pins"; -python3 openfpga_flow/scripts/run_fpga_task.py duplicated_grid_pin --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin --debug --show_thread_logs echo -e "Testing Verilog generation with spy output pads"; -python3 openfpga_flow/scripts/run_fpga_task.py spypad --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs echo -e "Testing Secured FPGA fabrics"; -python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/generate_vanilla_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/generate_random_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/load_external_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_vanilla_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_random_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key --debug --show_thread_logs echo -e "Testing Power-gating designs"; -python3 openfpga_flow/scripts/run_fpga_task.py power_gated_design/power_gated_inverter --show_thread_logs --debug +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug echo -e "Testing Depopulated crossbar in local routing"; -python3 openfpga_flow/scripts/run_fpga_task.py depopulate_crossbar --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs # Verify MCNC big20 benchmark suite with ModelSim # Please make sure you have ModelSim installed in the environment # Otherwise, it will fail -#python3 openfpga_flow/scripts/run_fpga_task.py mcnc_big20 --debug --show_thread_logs --maxthreads 20 +#python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20 #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim end_section "OpenFPGA.TaskTun" diff --git a/openfpga_flow/tasks/fixed_simulation_settings/config/task.conf b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fixed_simulation_settings/config/task.conf rename to openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf diff --git a/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf similarity index 100% rename from openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf rename to openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf diff --git a/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf similarity index 100% rename from openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf rename to openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf diff --git a/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf similarity index 100% rename from openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf rename to openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf diff --git a/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf similarity index 100% rename from openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf rename to openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf diff --git a/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf similarity index 100% rename from openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf rename to openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf diff --git a/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf similarity index 100% rename from openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf rename to openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf diff --git a/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf similarity index 100% rename from openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf rename to openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf diff --git a/openfpga_flow/tasks/generate_fabric/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf similarity index 100% rename from openfpga_flow/tasks/generate_fabric/config/task.conf rename to openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf diff --git a/openfpga_flow/tasks/generate_testbench/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf similarity index 100% rename from openfpga_flow/tasks/generate_testbench/config/task.conf rename to openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf similarity index 100% rename from openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf rename to openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf similarity index 100% rename from openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf rename to openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf diff --git a/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf similarity index 100% rename from openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf rename to openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf diff --git a/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf similarity index 100% rename from openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf rename to openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf diff --git a/openfpga_flow/tasks/sdc_time_unit/config/task.conf b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/config/task.conf similarity index 100% rename from openfpga_flow/tasks/sdc_time_unit/config/task.conf rename to openfpga_flow/tasks/fpga_sdc/sdc_time_unit/config/task.conf diff --git a/openfpga_flow/tasks/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf similarity index 100% rename from openfpga_flow/tasks/behavioral_verilog/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf diff --git a/openfpga_flow/tasks/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf similarity index 100% rename from openfpga_flow/tasks/bram/dpram16k/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf diff --git a/openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf similarity index 100% rename from openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf diff --git a/openfpga_flow/tasks/depopulate_crossbar/config/task.conf b/openfpga_flow/tasks/fpga_verilog/depopulate_crossbar/config/task.conf similarity index 100% rename from openfpga_flow/tasks/depopulate_crossbar/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/depopulate_crossbar/config/task.conf diff --git a/openfpga_flow/tasks/duplicated_grid_pin/config/task.conf b/openfpga_flow/tasks/fpga_verilog/duplicated_grid_pin/config/task.conf similarity index 100% rename from openfpga_flow/tasks/duplicated_grid_pin/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/duplicated_grid_pin/config/task.conf diff --git a/openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf diff --git a/openfpga_flow/tasks/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fabric_chain/register_chain/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf diff --git a/openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf diff --git a/openfpga_flow/tasks/fabric_key/generate_random_key/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_random_key/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fabric_key/generate_random_key/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/fabric_key/generate_random_key/config/task.conf diff --git a/openfpga_flow/tasks/fabric_key/generate_vanilla_key/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_vanilla_key/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fabric_key/generate_vanilla_key/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/fabric_key/generate_vanilla_key/config/task.conf diff --git a/openfpga_flow/tasks/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fabric_key/load_external_key/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf diff --git a/openfpga_flow/tasks/ncounter/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf similarity index 57% rename from openfpga_flow/tasks/ncounter/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf index 75af20185..5931a4a13 100644 --- a/openfpga_flow/tasks/ncounter/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf @@ -16,22 +16,23 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml -external_fabric_key_file= +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=/var/tmp/AA_SC/ncounter_task/Ncounter.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif [SYNTHESIS_PARAM] -bench0_top = Ncounter -bench0_act = /var/tmp/AA_SC/ncounter_task/Ncounter.act -bench0_verilog = /var/tmp/AA_SC/ncounter_task/Ncounter_output_verilog.v +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -vpr_fpga_verilog_formal_verification_top_netlist= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/flatten_routing/config/task.conf b/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf similarity index 100% rename from openfpga_flow/tasks/flatten_routing/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf diff --git a/openfpga_flow/tasks/hard_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf similarity index 100% rename from openfpga_flow/tasks/hard_adder/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf diff --git a/openfpga_flow/tasks/implicit_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/implicit_verilog/config/task.conf similarity index 100% rename from openfpga_flow/tasks/implicit_verilog/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/implicit_verilog/config/task.conf diff --git a/openfpga_flow/tasks/io/aib/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf similarity index 100% rename from openfpga_flow/tasks/io/aib/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf diff --git a/openfpga_flow/tasks/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf similarity index 100% rename from openfpga_flow/tasks/io/multi_io_capacity/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf diff --git a/openfpga_flow/tasks/io/reduced_io/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf similarity index 100% rename from openfpga_flow/tasks/io/reduced_io/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf diff --git a/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf similarity index 100% rename from openfpga_flow/tasks/lut_design/frac_lut/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf diff --git a/openfpga_flow/tasks/lut_design/intermediate_buffer/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/intermediate_buffer/config/task.conf similarity index 100% rename from openfpga_flow/tasks/lut_design/intermediate_buffer/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/lut_design/intermediate_buffer/config/task.conf diff --git a/openfpga_flow/tasks/lut_design/single_mode/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf similarity index 100% rename from openfpga_flow/tasks/lut_design/single_mode/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf diff --git a/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/local_encoder/config/task.conf similarity index 100% rename from openfpga_flow/tasks/mux_design/local_encoder/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/mux_design/local_encoder/config/task.conf diff --git a/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2/config/task.conf similarity index 100% rename from openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2/config/task.conf diff --git a/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/tree_structure/config/task.conf similarity index 100% rename from openfpga_flow/tasks/mux_design/tree_structure/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/mux_design/tree_structure/config/task.conf diff --git a/openfpga_flow/tasks/power_gated_design/power_gated_inverter/config/task.conf b/openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf similarity index 100% rename from openfpga_flow/tasks/power_gated_design/power_gated_inverter/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf diff --git a/openfpga_flow/tasks/spypad/config/task.conf b/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf similarity index 100% rename from openfpga_flow/tasks/spypad/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf diff --git a/openfpga_flow/tasks/untileable/config/task.conf b/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf similarity index 100% rename from openfpga_flow/tasks/untileable/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf