[Tool] Remove duplicated codes on fast configuration
This commit is contained in:
tangxifan
parent
4aef9d5c96
commit
5075c68418
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@ -1461,102 +1461,6 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
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print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
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print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
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}
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}
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/********************************************************************
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* Decide if we should use reset or set signal to acheive fast configuration
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* - If only one type signal is specified, we use that type
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* For example, only reset signal is defined, we will use reset
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* - If both are defined, pick the one that will bring bigger reduction
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* i.e., larger number of configuration bits can be skipped
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*******************************************************************/
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static
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bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& config_protocol_type,
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const bool& fast_configuration,
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const std::vector<FabricGlobalPortId>& global_prog_reset_ports,
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const std::vector<FabricGlobalPortId>& global_prog_set_ports,
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const BitstreamManager& bitstream_manager,
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const FabricBitstream& fabric_bitstream) {
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/* Early exit conditions */
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if (!global_prog_reset_ports.empty() && global_prog_set_ports.empty()) {
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return false;
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} else if (!global_prog_set_ports.empty() && global_prog_reset_ports.empty()) {
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return true;
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} else if (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) {
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/* If both types of ports are not defined, the fast configuration should be turned off */
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VTR_ASSERT(false == fast_configuration);
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return false;
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}
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VTR_ASSERT(!global_prog_set_ports.empty() && !global_prog_reset_ports.empty());
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bool bit_value_to_skip = false;
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VTR_LOG("Both reset and set ports are defined for programming controls, selecting the best-fit one...\n");
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size_t num_ones_to_skip = 0;
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size_t num_zeros_to_skip = 0;
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/* Branch on the type of configuration protocol */
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switch (config_protocol_type) {
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case CONFIG_MEM_STANDALONE:
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break;
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case CONFIG_MEM_SCAN_CHAIN: {
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/* We can only skip the ones/zeros at the beginning of the bitstream */
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/* Count how many logic '1' bits we can skip */
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for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
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if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) {
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break;
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}
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VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)));
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num_ones_to_skip++;
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}
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/* Count how many logic '0' bits we can skip */
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for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
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if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) {
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break;
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}
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VTR_ASSERT(false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)));
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num_zeros_to_skip++;
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}
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break;
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}
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case CONFIG_MEM_MEMORY_BANK:
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case CONFIG_MEM_FRAME_BASED: {
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/* Count how many logic '1' and logic '0' bits we can skip */
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for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
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if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) {
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num_zeros_to_skip++;
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} else {
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VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)));
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num_ones_to_skip++;
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}
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}
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break;
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}
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid SRAM organization type!\n");
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exit(1);
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}
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VTR_LOG("Using reset will skip %g% (%lu/%lu) of configuration bitstream.\n",
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100. * (float) num_zeros_to_skip / (float) fabric_bitstream.num_bits(),
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num_zeros_to_skip, fabric_bitstream.num_bits());
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VTR_LOG("Using set will skip %g% (%lu/%lu) of configuration bitstream.\n",
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100. * (float) num_ones_to_skip / (float) fabric_bitstream.num_bits(),
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num_ones_to_skip, fabric_bitstream.num_bits());
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/* By default, we prefer to skip zeros (when the numbers are the same */
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if (num_ones_to_skip > num_zeros_to_skip) {
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VTR_LOG("Will use set signal in fast configuration\n");
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bit_value_to_skip = true;
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} else {
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VTR_LOG("Will use reset signal in fast configuration\n");
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}
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return bit_value_to_skip;
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}
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/********************************************************************
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/********************************************************************
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* Print stimulus for a FPGA fabric with a configuration chain protocol
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* Print stimulus for a FPGA fabric with a configuration chain protocol
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* where configuration bits are programming in serial (one by one)
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* where configuration bits are programming in serial (one by one)
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@ -2699,17 +2603,11 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
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std::vector<FabricGlobalPortId> global_prog_set_ports = find_fabric_global_programming_set_ports(global_ports);
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std::vector<FabricGlobalPortId> global_prog_set_ports = find_fabric_global_programming_set_ports(global_ports);
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/* Identify if we can apply fast configuration */
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/* Identify if we can apply fast configuration */
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bool apply_fast_configuration = fast_configuration;
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bool apply_fast_configuration = fast_configuration && is_fast_configuration_applicable(global_ports);
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if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty())
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&& (true == fast_configuration)) {
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VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off\n");
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apply_fast_configuration = false;
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}
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bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(),
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bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(),
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apply_fast_configuration,
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global_ports,
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global_prog_reset_ports,
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bitstream_manager,
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global_prog_set_ports,
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fabric_bitstream);
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bitstream_manager, fabric_bitstream);
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/* Start of testbench */
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/* Start of testbench */
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print_verilog_top_testbench_ports(fp, module_manager, top_module,
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print_verilog_top_testbench_ports(fp, module_manager, top_module,
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@ -2958,17 +2856,11 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
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std::vector<FabricGlobalPortId> global_prog_set_ports = find_fabric_global_programming_set_ports(global_ports);
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std::vector<FabricGlobalPortId> global_prog_set_ports = find_fabric_global_programming_set_ports(global_ports);
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/* Identify if we can apply fast configuration */
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/* Identify if we can apply fast configuration */
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bool apply_fast_configuration = fast_configuration;
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bool apply_fast_configuration = fast_configuration && is_fast_configuration_applicable(global_ports);
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if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty())
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&& (true == fast_configuration)) {
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VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off\n");
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apply_fast_configuration = false;
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}
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bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(),
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bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(),
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apply_fast_configuration,
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global_ports,
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global_prog_reset_ports,
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bitstream_manager,
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global_prog_set_ports,
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fabric_bitstream);
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bitstream_manager, fabric_bitstream);
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/* Start of testbench */
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/* Start of testbench */
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print_verilog_top_testbench_ports(fp, module_manager, top_module,
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print_verilog_top_testbench_ports(fp, module_manager, top_module,
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