From 4f8260a7ba0ecb3405483d16676a7fb2b8301128 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 4 Jul 2020 17:31:34 -0600 Subject: [PATCH] remove obselete codes and update regression tests --- .travis.yml | 8 +- .travis/basic_reg_test.sh | 46 + .travis/openfpga_vpr7_reg_test.sh | 30 - ...a_vpr8_reg_test.sh => verilog_reg_test.sh} | 37 +- CMakeLists.txt | 31 - ERI_demo/ERI.sh | 49 - ERI_demo/eri_demo.sh | 46 - OpenSTA | 1 - .../fpga_spice/k6_N10_sram_tsmc40nm_FF.xml | 1427 -- .../fpga_spice/k6_N10_sram_tsmc40nm_MC.xml | 1428 -- .../fpga_spice/k6_N10_sram_tsmc40nm_SS.xml | 1427 -- .../fpga_spice/k6_N10_sram_tsmc40nm_TT.xml | 1433 -- .../k6_N10_sram_chain_HC_DPRAM_template.xml | 1155 - .../k6_N10_sram_chain_HC_template.xml | 1040 - .../k8_N10_sram_chain_FC_template.xml | 1139 - .../Blif/FPGA_SPICE_bench/C1355.blif | 1102 - .../Blif/FPGA_SPICE_bench/alu2.blif | 263 - .../Blif/FPGA_SPICE_bench/alu4.blif | 502 - .../Blif/FPGA_SPICE_bench/apex7.blif | 220 - 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vpr7_x2p/vpr/regression_verilog.sh diff --git a/.travis.yml b/.travis.yml index 13b89c162..ca370367a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -87,16 +87,16 @@ stages: jobs: include: - stage: Test - name: "OpenFPGA + VPR7 regression tests" + name: "Basic regression tests" script: - source .travis/build.sh - - source .travis/openfpga_vpr7_reg_test.sh + - source .travis/basic_reg_test.sh - stage: Test - name: "OpenFPGA + VPR8 regression tests" + name: "FPGA-Verilog regression tests" script: - source .travis/build.sh - - source .travis/openfpga_vpr8_reg_test.sh + - source .travis/verilog_reg_test.sh #after_failure: # - .travis/after_failure.sh diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh new file mode 100755 index 000000000..4767ba217 --- /dev/null +++ b/.travis/basic_reg_test.sh @@ -0,0 +1,46 @@ +#!/bin/bash + +set -e + +start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" +cd ${TRAVIS_BUILD_DIR} + +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "Basic regression tests"; + +echo -e "Testing configuration chain of a K4N4 FPGA"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_chain --debug --show_thread_logs + +echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_frame --debug --show_thread_logs + +echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/memory_bank --debug --show_thread_logs + +echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/flatten_memory --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/flatten_memory --debug --show_thread_logs + +echo -e "Testing fabric Verilog generation only"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_fabric --debug --show_thread_logs + +echo -e "Testing Verilog testbench generation only"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_testbench --debug --show_thread_logs + +echo -e "Testing bitstream generation only"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_bitstream --debug --show_thread_logs + +echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fixed_simulation_settings --debug --show_thread_logs + +echo -e "Testing SDC generation with time units"; +python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/sdc_time_unit --debug --show_thread_logs + +end_section "OpenFPGA.TaskTun" diff --git a/.travis/openfpga_vpr7_reg_test.sh b/.travis/openfpga_vpr7_reg_test.sh deleted file mode 100755 index c04d202a4..000000000 --- a/.travis/openfpga_vpr7_reg_test.sh +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/bash -set -e - -start_section "OpenFPGA+VPR7.TaskTun" "${GREEN}..Running_Regression..${NC}" -cd ${TRAVIS_BUILD_DIR} - -############################################### -# OpenFPGA with VPR7 -# TO BE DEPRECATED -############################################## -echo -e "Testing single-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs -#python3 openfpga_flow/scripts/run_fpga_task.py s298 - -echo -e "Testing multi-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py multi_mode --maxthreads 4 --debug --show_thread_logs - -echo -e "Testing compact routing techniques"; -python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs - -echo -e "Testing tileable architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --debug --show_thread_logs - -echo -e "Testing Verilog generation with explicit port mapping "; -python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_thread_logs - -echo -e "Testing Verilog generation with grid pin duplication "; -python3 openfpga_flow/scripts/run_fpga_task.py duplicate_grid_pin --debug --show_thread_logs - -end_section "OpenFPGA+VPR7.TaskTun" diff --git a/.travis/openfpga_vpr8_reg_test.sh b/.travis/verilog_reg_test.sh similarity index 66% rename from .travis/openfpga_vpr8_reg_test.sh rename to .travis/verilog_reg_test.sh index c48959e58..7a4899041 100755 --- a/.travis/openfpga_vpr8_reg_test.sh +++ b/.travis/verilog_reg_test.sh @@ -7,31 +7,8 @@ cd ${TRAVIS_BUILD_DIR} ############################################### # OpenFPGA Shell with VPR8 -# (Will replace all the old tests) ############################################## -echo -e "Testing OpenFPGA Shell"; - -echo -e "Testing configuration chain of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_chain --debug --show_thread_logs - -echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/configuration_frame --debug --show_thread_logs - -echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/fast_memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/memory_bank --debug --show_thread_logs - - -echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/flatten_memory --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/preconfig_testbench/flatten_memory --debug --show_thread_logs - -echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fixed_simulation_settings --debug --show_thread_logs +echo -e "OpenFPGA Feature Testing for Verilog-to-Verification"; echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks"; python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/lut_design/single_mode --debug --show_thread_logs @@ -93,18 +70,6 @@ python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/duplicated_grid_pi echo -e "Testing Verilog generation with spy output pads"; python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/spypad --debug --show_thread_logs -echo -e "Testing fabric Verilog generation only"; -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_fabric --debug --show_thread_logs - -echo -e "Testing Verilog testbench generation only"; -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_testbench --debug --show_thread_logs - -echo -e "Testing bitstream generation only"; -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/generate_bitstream --debug --show_thread_logs - -echo -e "Testing SDC generation with time units"; -python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/sdc_time_unit --debug --show_thread_logs - echo -e "Testing Secured FPGA fabrics"; python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_key/generate_vanilla_key --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/fabric_key/generate_random_key --debug --show_thread_logs diff --git a/CMakeLists.txt b/CMakeLists.txt index 6aa930b94..de41f3ca2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -188,7 +188,6 @@ add_subdirectory(libopenfpga) add_subdirectory(yosys) add_subdirectory(abc) add_subdirectory(ace2) -add_subdirectory(vpr7_x2p) add_subdirectory(vpr) add_subdirectory(openfpga) @@ -228,37 +227,7 @@ set_target_properties(libace ace LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/ace2" RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/ace2") -set_target_properties(libarchfpgavpr7 read_arch_vpr7 - PROPERTIES - ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/libarchfpgavpr7" - LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/libarchfpgavpr7" - RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/libarchfpgavpr7") - -set_target_properties(libpcre pcredemo - PROPERTIES - ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/libpcre" - LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/libpcre" - RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/libpcre") - -set_target_properties(libprinthandler printhandlerdemo - PROPERTIES - ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/libprinthandler" - LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/libprinthandler" - RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/libprinthandler") - set_target_properties(libvpr vpr - PROPERTIES - ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/vpr" - LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/vpr" - RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/vpr") - -set_target_properties(libvpr vpr_shell - PROPERTIES - ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/vpr" - LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/vpr" - RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr7_x2p/vpr") - -set_target_properties(libvpr8 vpr8 PROPERTIES ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr" LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/vpr" diff --git a/ERI_demo/ERI.sh b/ERI_demo/ERI.sh deleted file mode 100755 index f585d90b2..000000000 --- a/ERI_demo/ERI.sh +++ /dev/null @@ -1,49 +0,0 @@ -#!/bin/bash -# Regression test version 1.0 - -# Set variables -my_pwd=$PWD -fpga_flow_scripts="${my_pwd}/fpga_flow/scripts" -vpr_path="${my_pwd}/vpr7_x2p/vpr" -benchmark="test_modes" -include_netlists="_include_netlists.v" -compiled_file="compiled_$benchmark" -tb_formal_postfix="_top_formal_verification_random_tb" -verilog_dirname="${vpr_path}/${benchmark}_Verilog" -log_file="${benchmark}_sim.log" -new_reg_sh="${PWD}/ERI_demo/my_eri_demo.sh" -template_sh="${PWD}/ERI_demo/eri_demo.sh" - - -# Remove former log file -rm -f $log_file -rm -f $compiled_file - -# Rewite script -cd $fpga_flow_scripts - -perl rewrite_path_in_file.pl -i $template_sh -o $new_reg_sh - -cd $my_pwd - -# Start the script -> run the fpga generation -> run the simulation -> check the log file -source $new_reg_sh # Leave us in vpr folder -cd $my_pwd -iverilog -o $compiled_file ${verilog_dirname}/SRC/${benchmark}${include_netlists} -s ${benchmark}${tb_formal_postfix} -vvp $compiled_file -j 64 >> $log_file - -result=`grep "Succeed" $log_file` -if ["$result" = ""]; then - result=`grep "Failed" $log_file` - if ["$result" = ""]; then - echo "Unexpected error, Verification didn't run" - exit 1 - else - echo "Verification failed" - exit 2 - fi -else - echo "Verification succeed" - gtkwave ${benchmark}_formal.vcd & -fi - diff --git a/ERI_demo/eri_demo.sh b/ERI_demo/eri_demo.sh deleted file mode 100644 index 6974366a7..000000000 --- a/ERI_demo/eri_demo.sh +++ /dev/null @@ -1,46 +0,0 @@ -#!/bin/bash -# Example of how to run vpr - -# Set variables -# For FPGA-Verilog ONLY -benchmark="test_modes" -OpenFPGA_path="OPENFPGAPATHKEYWORD" -verilog_output_dirname="${benchmark}_Verilog" -verilog_output_dirpath="$vpr_path" -tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" -# VPR critical inputs -template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml" -arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml" -blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif" -act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act " -verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v" -vpr_route_chan_width="200" -fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts" -ff_path="$vpr_path/VerilogNetlists/ff.v" -new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v" -ff_keyword="GENERATED_DIR_KEYWORD" -ff_include_path="$verilog_output_dirpath/$verilog_output_dirname" -arch_ff_keyword="FFPATHKEYWORD" -tb_formal_ext="_formal_random_top_tb.v" -formal_postfix="_top_formal_verification" - -# Remove previous designs -rm -rf $verilog_output_dirpath/$verilog_output_dirname - -mkdir ${OpenFPGA_path}/fpga_flow/arch/generated - -cd $fpga_flow_scripts -perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file -perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path - -# Move to vpr folder -cd $vpr_path - -# Run VPR -./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping --nodisp - -cd $fpga_flow_scripts -perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path -cd - - - diff --git a/OpenSTA b/OpenSTA deleted file mode 160000 index 7592f12e5..000000000 --- a/OpenSTA +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 7592f12e54daf5c91c106e82650bc35a6586aafb diff --git a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_FF.xml b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_FF.xml deleted file mode 100755 index 4a87b8588..000000000 --- a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_FF.xml +++ /dev/null @@ -1,1427 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.I[19:0] clb.O[4:0] - clb.I[39:20] clb.O[9:5] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_MC.xml b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_MC.xml deleted file mode 100755 index 8190908f5..000000000 --- a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_MC.xml +++ /dev/null @@ -1,1428 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.I[19:0] clb.O[4:0] - clb.I[39:20] clb.O[9:5] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_SS.xml b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_SS.xml deleted file mode 100755 index 80b3ad009..000000000 --- a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_SS.xml +++ /dev/null @@ -1,1427 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.I[19:0] clb.O[4:0] - clb.I[39:20] clb.O[9:5] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml deleted file mode 100755 index 5b0b85ae7..000000000 --- a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml +++ /dev/null @@ -1,1433 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.I[19:0] clb.O[4:0] - clb.I[39:20] clb.O[9:5] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml deleted file mode 100644 index c03b83855..000000000 --- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml +++ /dev/null @@ -1,1155 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255e-12 - 255e-12 - 255e-12 - 255e-12 - 255e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml deleted file mode 100644 index ba9ba3a04..000000000 --- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +++ /dev/null @@ -1,1040 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255e-12 - 255e-12 - 255e-12 - 255e-12 - 255e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/fpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml b/fpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml deleted file mode 100644 index 84d2c3ab3..000000000 --- a/fpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml +++ /dev/null @@ -1,1139 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - - - - - - - - - - - 10e-12 0e-12 0e-12 - - - 10e-12 0e-12 0e-12 - - - - - - - - - - - 10e-12 - - - 10e-12 - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/C1355.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/C1355.blif deleted file mode 100644 index 7f43f6af0..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/C1355.blif +++ /dev/null @@ -1,1102 +0,0 @@ - - -# ATPG -- Automatic Test Pattern Generation for -# Combinational Circuits -# ATPG, Version 1.0, 4/29/86, Author: Ruey-sing Wei and Tony Ma - -.model C1355.iscas -.inputs 1GAT(0) 8GAT(1) 15GAT(2) 22GAT(3) 29GAT(4) 36GAT(5) 43GAT(6) 50GAT(7) 57GAT(8) 64GAT(9) 71GAT(10) 78GAT(11) 85GAT(12) 92GAT(13) 99GAT(14) 106GAT(15) 113GAT(16) 120GAT(17) 127GAT(18) 134GAT(19) 141GAT(20) 148GAT(21) 155GAT(22) 162GAT(23) 169GAT(24) 176GAT(25) 183GAT(26) 190GAT(27) 197GAT(28) 204GAT(29) 211GAT(30) 218GAT(31) 225GAT(32) 226GAT(33) 227GAT(34) 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169GAT(24) 341GAT(55) 412GAT(95) -11 0 -.names 169GAT(24) 302GAT(56) 386GAT(96) -11 0 -.names 162GAT(23) 356GAT(59) 423GAT(97) -11 0 -.names 162GAT(23) 299GAT(57) 385GAT(98) -11 0 -.names 155GAT(22) 350GAT(60) 419GAT(99) -11 0 -.names 155GAT(22) 299GAT(57) 384GAT(100) -11 0 -.names 148GAT(21) 344GAT(62) 415GAT(101) -11 0 -.names 148GAT(21) 296GAT(58) 383GAT(102) -11 0 -.names 141GAT(20) 338GAT(63) 411GAT(103) -11 0 -.names 141GAT(20) 296GAT(58) 382GAT(104) -11 0 -.names 134GAT(19) 356GAT(59) 422GAT(105) -11 0 -.names 134GAT(19) 293GAT(61) 381GAT(106) -11 0 -.names 127GAT(18) 350GAT(60) 418GAT(107) -11 0 -.names 127GAT(18) 293GAT(61) 380GAT(108) -11 0 -.names 120GAT(17) 344GAT(62) 414GAT(109) -11 0 -.names 120GAT(17) 290GAT(64) 379GAT(110) -11 0 -.names 113GAT(16) 338GAT(63) 410GAT(111) -11 0 -.names 113GAT(16) 290GAT(64) 378GAT(112) -11 0 -.names 106GAT(15) 335GAT(67) 409GAT(113) -11 0 -.names 106GAT(15) 287GAT(65) 377GAT(114) -11 0 -.names 99GAT(14) 329GAT(68) 405GAT(115) -11 0 -.names 99GAT(14) 287GAT(65) 376GAT(116) -11 0 -.names 92GAT(13) 323GAT(70) 401GAT(117) -11 0 -.names 92GAT(13) 284GAT(66) 375GAT(118) -11 0 -.names 85GAT(12) 317GAT(71) 397GAT(119) -11 0 -.names 85GAT(12) 284GAT(66) 374GAT(120) -11 0 -.names 78GAT(11) 335GAT(67) 408GAT(121) -11 0 -.names 78GAT(11) 281GAT(69) 373GAT(122) -11 0 -.names 71GAT(10) 329GAT(68) 404GAT(123) -11 0 -.names 71GAT(10) 281GAT(69) 372GAT(124) -11 0 -.names 64GAT(9) 323GAT(70) 400GAT(125) -11 0 -.names 64GAT(9) 278GAT(72) 371GAT(126) -11 0 -.names 57GAT(8) 317GAT(71) 396GAT(127) -11 0 -.names 57GAT(8) 278GAT(72) 370GAT(128) -11 0 -.names 50GAT(7) 332GAT(75) 407GAT(129) -11 0 -.names 50GAT(7) 275GAT(73) 369GAT(130) -11 0 -.names 43GAT(6) 326GAT(76) 403GAT(131) -11 0 -.names 43GAT(6) 275GAT(73) 368GAT(132) -11 0 -.names 36GAT(5) 320GAT(78) 399GAT(133) -11 0 -.names 36GAT(5) 272GAT(74) 367GAT(134) -11 0 -.names 29GAT(4) 314GAT(79) 395GAT(135) -11 0 -.names 29GAT(4) 272GAT(74) 366GAT(136) -11 0 -.names 22GAT(3) 332GAT(75) 406GAT(137) -11 0 -.names 22GAT(3) 269GAT(77) 365GAT(138) -11 0 -.names 15GAT(2) 326GAT(76) 402GAT(139) -11 0 -.names 15GAT(2) 269GAT(77) 364GAT(140) -11 0 -.names 8GAT(1) 320GAT(78) 398GAT(141) -11 0 -.names 8GAT(1) 266GAT(80) 363GAT(142) -11 0 -.names 1GAT(0) 314GAT(79) 394GAT(143) -11 0 -.names 1GAT(0) 266GAT(80) 362GAT(144) -11 0 -.names 424GAT(89) 425GAT(81) 519GAT(145) -11 0 -.names 392GAT(84) 393GAT(82) 471GAT(146) -11 0 -.names 420GAT(91) 421GAT(83) 513GAT(147) -11 0 -.names 416GAT(93) 417GAT(85) 507GAT(148) -11 0 -.names 390GAT(88) 391GAT(86) 468GAT(149) -11 0 -.names 412GAT(95) 413GAT(87) 501GAT(150) -11 0 -.names 388GAT(92) 389GAT(90) 465GAT(151) -11 0 -.names 386GAT(96) 387GAT(94) 462GAT(152) -11 0 -.names 422GAT(105) 423GAT(97) 516GAT(153) -11 0 -.names 384GAT(100) 385GAT(98) 459GAT(154) -11 0 -.names 418GAT(107) 419GAT(99) 510GAT(155) -11 0 -.names 414GAT(109) 415GAT(101) 504GAT(156) -11 0 -.names 382GAT(104) 383GAT(102) 456GAT(157) -11 0 -.names 410GAT(111) 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558GAT(181) 595GAT(198) -11 0 -.names 465GAT(151) 540GAT(182) 583GAT(199) -11 0 -.names 462GAT(152) 540GAT(182) 582GAT(200) -11 0 -.names 516GAT(153) 567GAT(177) 600GAT(201) -11 0 -.names 459GAT(154) 537GAT(183) 581GAT(202) -11 0 -.names 510GAT(155) 564GAT(179) 598GAT(203) -11 0 -.names 504GAT(156) 561GAT(180) 596GAT(204) -11 0 -.names 456GAT(157) 537GAT(183) 580GAT(205) -11 0 -.names 498GAT(158) 558GAT(181) 594GAT(206) -11 0 -.names 453GAT(159) 534GAT(184) 579GAT(207) -11 0 -.names 450GAT(160) 534GAT(184) 578GAT(208) -11 0 -.names 495GAT(161) 555GAT(185) 593GAT(209) -11 0 -.names 447GAT(162) 531GAT(186) 577GAT(210) -11 0 -.names 489GAT(163) 552GAT(187) 591GAT(211) -11 0 -.names 483GAT(164) 549GAT(188) 589GAT(212) -11 0 -.names 444GAT(165) 531GAT(186) 576GAT(213) -11 0 -.names 477GAT(166) 546GAT(189) 587GAT(214) -11 0 -.names 441GAT(167) 528GAT(190) 575GAT(215) -11 0 -.names 438GAT(168) 528GAT(190) 574GAT(216) -11 0 -.names 492GAT(169) 555GAT(185) 592GAT(217) -11 0 -.names 435GAT(170) 525GAT(191) 573GAT(218) -11 0 -.names 486GAT(171) 552GAT(187) 590GAT(219) -11 0 -.names 480GAT(172) 549GAT(188) 588GAT(220) -11 0 -.names 432GAT(173) 525GAT(191) 572GAT(221) -11 0 -.names 474GAT(174) 546GAT(189) 586GAT(222) -11 0 -.names 429GAT(175) 522GAT(192) 571GAT(223) -11 0 -.names 426GAT(176) 522GAT(192) 570GAT(224) -11 0 -.names 600GAT(201) 601GAT(193) 663GAT(225) -11 0 -.names 584GAT(197) 585GAT(194) 637GAT(226) -11 0 -.names 598GAT(203) 599GAT(195) 660GAT(227) -11 0 -.names 596GAT(204) 597GAT(196) 657GAT(228) -11 0 -.names 594GAT(206) 595GAT(198) 654GAT(229) -11 0 -.names 582GAT(200) 583GAT(199) 632GAT(230) -11 0 -.names 580GAT(205) 581GAT(202) 627GAT(231) -11 0 -.names 578GAT(208) 579GAT(207) 622GAT(232) -11 0 -.names 592GAT(217) 593GAT(209) 651GAT(233) -11 0 -.names 576GAT(213) 577GAT(210) 617GAT(234) -11 0 -.names 590GAT(219) 591GAT(211) 648GAT(235) -11 0 -.names 588GAT(220) 589GAT(212) 645GAT(236) -11 0 -.names 586GAT(222) 587GAT(214) 642GAT(237) -11 0 -.names 574GAT(216) 575GAT(215) 612GAT(238) -11 0 -.names 572GAT(221) 573GAT(218) 607GAT(239) -11 0 -.names 570GAT(224) 571GAT(223) 602GAT(240) -11 0 -.names 632GAT(230) 637GAT(226) 681GAT(241) -11 0 -.names 627GAT(231) 637GAT(226) 687GAT(242) -11 0 -.names 622GAT(232) 632GAT(230) 684GAT(243) -11 0 -.names 622GAT(232) 627GAT(231) 678GAT(244) -11 0 -.names 612GAT(238) 617GAT(234) 669GAT(245) -11 0 -.names 607GAT(239) 617GAT(234) 675GAT(246) -11 0 -.names 602GAT(240) 612GAT(238) 672GAT(247) -11 0 -.names 602GAT(240) 607GAT(239) 666GAT(248) -11 0 -.names 637GAT(226) 681GAT(241) 701GAT(249) -11 0 -.names 637GAT(226) 687GAT(242) 705GAT(250) -11 0 -.names 632GAT(230) 681GAT(241) 700GAT(251) -11 0 -.names 632GAT(230) 684GAT(243) 703GAT(252) -11 0 -.names 627GAT(231) 678GAT(244) 699GAT(253) -11 0 -.names 627GAT(231) 687GAT(242) 704GAT(254) -11 0 -.names 622GAT(232) 678GAT(244) 698GAT(255) -11 0 -.names 622GAT(232) 684GAT(243) 702GAT(256) -11 0 -.names 617GAT(234) 669GAT(245) 693GAT(257) -11 0 -.names 617GAT(234) 675GAT(246) 697GAT(258) -11 0 -.names 612GAT(238) 669GAT(245) 692GAT(259) -11 0 -.names 612GAT(238) 672GAT(247) 695GAT(260) -11 0 -.names 607GAT(239) 666GAT(248) 691GAT(261) -11 0 -.names 607GAT(239) 675GAT(246) 696GAT(262) -11 0 -.names 602GAT(240) 666GAT(248) 690GAT(263) -11 0 -.names 602GAT(240) 672GAT(247) 694GAT(264) -11 0 -.names 700GAT(251) 701GAT(249) 721GAT(265) -11 0 -.names 704GAT(254) 705GAT(250) 727GAT(266) -11 0 -.names 702GAT(256) 703GAT(252) 724GAT(267) -11 0 -.names 698GAT(255) 699GAT(253) 718GAT(268) -11 0 -.names 692GAT(259) 693GAT(257) 709GAT(269) -11 0 -.names 696GAT(262) 697GAT(258) 715GAT(270) -11 0 -.names 694GAT(264) 695GAT(260) 712GAT(271) -11 0 -.names 690GAT(263) 691GAT(261) 706GAT(272) -11 0 -.names 263GAT(41) 715GAT(270) 751GAT(273) -11 0 -.names 260GAT(42) 712GAT(271) 748GAT(274) -11 0 -.names 257GAT(43) 709GAT(269) 745GAT(275) -11 0 -.names 254GAT(44) 706GAT(272) 742GAT(276) -11 0 -.names 251GAT(45) 727GAT(266) 739GAT(277) -11 0 -.names 248GAT(46) 724GAT(267) 736GAT(278) -11 0 -.names 245GAT(47) 721GAT(265) 733GAT(279) -11 0 -.names 242GAT(48) 718GAT(268) 730GAT(280) -11 0 -.names 263GAT(41) 751GAT(273) 768GAT(281) -11 0 -.names 260GAT(42) 748GAT(274) 766GAT(282) -11 0 -.names 257GAT(43) 745GAT(275) 764GAT(283) -11 0 -.names 254GAT(44) 742GAT(276) 762GAT(284) -11 0 -.names 251GAT(45) 739GAT(277) 760GAT(285) -11 0 -.names 248GAT(46) 736GAT(278) 758GAT(286) -11 0 -.names 245GAT(47) 733GAT(279) 756GAT(287) -11 0 -.names 242GAT(48) 730GAT(280) 754GAT(288) -11 0 -.names 721GAT(265) 733GAT(279) 757GAT(289) -11 0 -.names 727GAT(266) 739GAT(277) 761GAT(290) -11 0 -.names 724GAT(267) 736GAT(278) 759GAT(291) -11 0 -.names 718GAT(268) 730GAT(280) 755GAT(292) -11 0 -.names 709GAT(269) 745GAT(275) 765GAT(293) -11 0 -.names 715GAT(270) 751GAT(273) 769GAT(294) -11 0 -.names 712GAT(271) 748GAT(274) 767GAT(295) -11 0 -.names 706GAT(272) 742GAT(276) 763GAT(296) -11 0 -.names 768GAT(281) 769GAT(294) 791GAT(297) -11 0 -.names 766GAT(282) 767GAT(295) 788GAT(298) -11 0 -.names 764GAT(283) 765GAT(293) 785GAT(299) -11 0 -.names 762GAT(284) 763GAT(296) 782GAT(300) -11 0 -.names 760GAT(285) 761GAT(290) 779GAT(301) -11 0 -.names 758GAT(286) 759GAT(291) 776GAT(302) -11 0 -.names 756GAT(287) 757GAT(289) 773GAT(303) -11 0 -.names 754GAT(288) 755GAT(292) 770GAT(304) -11 0 -.names 663GAT(225) 791GAT(297) 815GAT(305) -11 0 -.names 660GAT(227) 788GAT(298) 812GAT(306) -11 0 -.names 657GAT(228) 785GAT(299) 809GAT(307) -11 0 -.names 654GAT(229) 782GAT(300) 806GAT(308) -11 0 -.names 651GAT(233) 779GAT(301) 803GAT(309) -11 0 -.names 648GAT(235) 776GAT(302) 800GAT(310) -11 0 -.names 645GAT(236) 773GAT(303) 797GAT(311) -11 0 -.names 642GAT(237) 770GAT(304) 794GAT(312) -11 0 -.names 791GAT(297) 815GAT(305) 833GAT(313) -11 0 -.names 788GAT(298) 812GAT(306) 831GAT(314) -11 0 -.names 785GAT(299) 809GAT(307) 829GAT(315) -11 0 -.names 782GAT(300) 806GAT(308) 827GAT(316) -11 0 -.names 779GAT(301) 803GAT(309) 825GAT(317) -11 0 -.names 776GAT(302) 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981GAT(384) -1111 1 -.names 982GAT(377) 983GAT(378) 984GAT(379) 985GAT(380) 991GAT(385) -0000 0 -.names 978GAT(381) 979GAT(382) 980GAT(383) 981GAT(384) 986GAT(386) -0000 0 -.names 925GAT(332) 952GAT(348) 953GAT(342) 899GAT(329) 986GAT(386) 1001GAT(387) -11111 1 -.names 956GAT(353) 886GAT(331) 957GAT(343) 899GAT(329) 986GAT(386) 1011GAT(388) -11111 1 -.names 925GAT(332) 950GAT(347) 912GAT(330) 951GAT(337) 986GAT(386) 996GAT(389) -11111 1 -.names 954GAT(352) 886GAT(331) 912GAT(330) 955GAT(338) 986GAT(386) 1006GAT(390) -11111 1 -.names 834GAT(336) 972GAT(371) 973GAT(365) 873GAT(333) 991GAT(385) 1021GAT(391) -11111 1 -.names 976GAT(376) 847GAT(335) 977GAT(366) 873GAT(333) 991GAT(385) 1031GAT(392) -11111 1 -.names 834GAT(336) 970GAT(370) 860GAT(334) 971GAT(360) 991GAT(385) 1016GAT(393) -11111 1 -.names 974GAT(375) 847GAT(335) 860GAT(334) 975GAT(361) 991GAT(385) 1026GAT(394) -11111 1 -.names 899GAT(329) 1016GAT(393) 1093GAT(395) -11 1 -.names 899GAT(329) 1021GAT(391) 1105GAT(396) -11 1 -.names 899GAT(329) 1026GAT(394) 1117GAT(397) -11 1 -.names 899GAT(329) 1031GAT(392) 1129GAT(398) -11 1 -.names 912GAT(330) 1016GAT(393) 1090GAT(399) -11 1 -.names 912GAT(330) 1021GAT(391) 1102GAT(400) -11 1 -.names 912GAT(330) 1026GAT(394) 1114GAT(401) -11 1 -.names 912GAT(330) 1031GAT(392) 1126GAT(402) -11 1 -.names 886GAT(331) 1016GAT(393) 1087GAT(403) -11 1 -.names 886GAT(331) 1021GAT(391) 1099GAT(404) -11 1 -.names 886GAT(331) 1026GAT(394) 1111GAT(405) -11 1 -.names 886GAT(331) 1031GAT(392) 1123GAT(406) -11 1 -.names 925GAT(332) 1016GAT(393) 1084GAT(407) -11 1 -.names 925GAT(332) 1021GAT(391) 1096GAT(408) -11 1 -.names 925GAT(332) 1026GAT(394) 1108GAT(409) -11 1 -.names 925GAT(332) 1031GAT(392) 1120GAT(410) -11 1 -.names 873GAT(333) 996GAT(389) 1045GAT(411) -11 1 -.names 873GAT(333) 1001GAT(387) 1057GAT(412) -11 1 -.names 873GAT(333) 1006GAT(390) 1069GAT(413) -11 1 -.names 873GAT(333) 1011GAT(388) 1081GAT(414) -11 1 -.names 860GAT(334) 996GAT(389) 1042GAT(415) -11 1 -.names 860GAT(334) 1001GAT(387) 1054GAT(416) -11 1 -.names 860GAT(334) 1006GAT(390) 1066GAT(417) -11 1 -.names 860GAT(334) 1011GAT(388) 1078GAT(418) -11 1 -.names 847GAT(335) 996GAT(389) 1039GAT(419) -11 1 -.names 847GAT(335) 1001GAT(387) 1051GAT(420) -11 1 -.names 847GAT(335) 1006GAT(390) 1063GAT(421) -11 1 -.names 847GAT(335) 1011GAT(388) 1075GAT(422) -11 1 -.names 834GAT(336) 996GAT(389) 1036GAT(423) -11 1 -.names 834GAT(336) 1001GAT(387) 1048GAT(424) -11 1 -.names 834GAT(336) 1006GAT(390) 1060GAT(425) -11 1 -.names 834GAT(336) 1011GAT(388) 1072GAT(426) -11 1 -.names 218GAT(31) 1129GAT(398) 1225GAT(427) -11 0 -.names 211GAT(30) 1126GAT(402) 1222GAT(428) -11 0 -.names 204GAT(29) 1123GAT(406) 1219GAT(429) -11 0 -.names 197GAT(28) 1120GAT(410) 1216GAT(430) -11 0 -.names 190GAT(27) 1117GAT(397) 1213GAT(431) -11 0 -.names 183GAT(26) 1114GAT(401) 1210GAT(432) -11 0 -.names 176GAT(25) 1111GAT(405) 1207GAT(433) -11 0 -.names 169GAT(24) 1108GAT(409) 1204GAT(434) -11 0 -.names 162GAT(23) 1105GAT(396) 1201GAT(435) -11 0 -.names 155GAT(22) 1102GAT(400) 1198GAT(436) -11 0 -.names 148GAT(21) 1099GAT(404) 1195GAT(437) -11 0 -.names 141GAT(20) 1096GAT(408) 1192GAT(438) -11 0 -.names 134GAT(19) 1093GAT(395) 1189GAT(439) -11 0 -.names 127GAT(18) 1090GAT(399) 1186GAT(440) -11 0 -.names 120GAT(17) 1087GAT(403) 1183GAT(441) -11 0 -.names 113GAT(16) 1084GAT(407) 1180GAT(442) -11 0 -.names 106GAT(15) 1081GAT(414) 1177GAT(443) -11 0 -.names 99GAT(14) 1078GAT(418) 1174GAT(444) -11 0 -.names 92GAT(13) 1075GAT(422) 1171GAT(445) -11 0 -.names 85GAT(12) 1072GAT(426) 1168GAT(446) -11 0 -.names 78GAT(11) 1069GAT(413) 1165GAT(447) -11 0 -.names 71GAT(10) 1066GAT(417) 1162GAT(448) -11 0 -.names 64GAT(9) 1063GAT(421) 1159GAT(449) -11 0 -.names 57GAT(8) 1060GAT(425) 1156GAT(450) -11 0 -.names 50GAT(7) 1057GAT(412) 1153GAT(451) -11 0 -.names 43GAT(6) 1054GAT(416) 1150GAT(452) -11 0 -.names 36GAT(5) 1051GAT(420) 1147GAT(453) -11 0 -.names 29GAT(4) 1048GAT(424) 1144GAT(454) -11 0 -.names 22GAT(3) 1045GAT(411) 1141GAT(455) -11 0 -.names 15GAT(2) 1042GAT(415) 1138GAT(456) -11 0 -.names 8GAT(1) 1039GAT(419) 1135GAT(457) -11 0 -.names 1GAT(0) 1036GAT(423) 1132GAT(458) -11 0 -.names 1093GAT(395) 1189GAT(439) 1267GAT(459) -11 0 -.names 1105GAT(396) 1201GAT(435) 1275GAT(460) -11 0 -.names 1117GAT(397) 1213GAT(431) 1283GAT(461) -11 0 -.names 1129GAT(398) 1225GAT(427) 1291GAT(462) -11 0 -.names 1090GAT(399) 1186GAT(440) 1265GAT(463) -11 0 -.names 1102GAT(400) 1198GAT(436) 1273GAT(464) -11 0 -.names 1114GAT(401) 1210GAT(432) 1281GAT(465) -11 0 -.names 1126GAT(402) 1222GAT(428) 1289GAT(466) -11 0 -.names 1087GAT(403) 1183GAT(441) 1263GAT(467) -11 0 -.names 1099GAT(404) 1195GAT(437) 1271GAT(468) -11 0 -.names 1111GAT(405) 1207GAT(433) 1279GAT(469) -11 0 -.names 1123GAT(406) 1219GAT(429) 1287GAT(470) -11 0 -.names 1084GAT(407) 1180GAT(442) 1261GAT(471) -11 0 -.names 1096GAT(408) 1192GAT(438) 1269GAT(472) -11 0 -.names 1108GAT(409) 1204GAT(434) 1277GAT(473) -11 0 -.names 1120GAT(410) 1216GAT(430) 1285GAT(474) -11 0 -.names 1045GAT(411) 1141GAT(455) 1235GAT(475) -11 0 -.names 1057GAT(412) 1153GAT(451) 1243GAT(476) -11 0 -.names 1069GAT(413) 1165GAT(447) 1251GAT(477) -11 0 -.names 1081GAT(414) 1177GAT(443) 1259GAT(478) -11 0 -.names 1042GAT(415) 1138GAT(456) 1233GAT(479) -11 0 -.names 1054GAT(416) 1150GAT(452) 1241GAT(480) -11 0 -.names 1066GAT(417) 1162GAT(448) 1249GAT(481) -11 0 -.names 1078GAT(418) 1174GAT(444) 1257GAT(482) -11 0 -.names 1039GAT(419) 1135GAT(457) 1231GAT(483) -11 0 -.names 1051GAT(420) 1147GAT(453) 1239GAT(484) -11 0 -.names 1063GAT(421) 1159GAT(449) 1247GAT(485) -11 0 -.names 1075GAT(422) 1171GAT(445) 1255GAT(486) -11 0 -.names 1036GAT(423) 1132GAT(458) 1229GAT(487) -11 0 -.names 1048GAT(424) 1144GAT(454) 1237GAT(488) -11 0 -.names 1060GAT(425) 1156GAT(450) 1245GAT(489) -11 0 -.names 1072GAT(426) 1168GAT(446) 1253GAT(490) -11 0 -.names 218GAT(31) 1225GAT(427) 1290GAT(491) -11 0 -.names 211GAT(30) 1222GAT(428) 1288GAT(492) -11 0 -.names 204GAT(29) 1219GAT(429) 1286GAT(493) -11 0 -.names 197GAT(28) 1216GAT(430) 1284GAT(494) -11 0 -.names 190GAT(27) 1213GAT(431) 1282GAT(495) -11 0 -.names 183GAT(26) 1210GAT(432) 1280GAT(496) -11 0 -.names 176GAT(25) 1207GAT(433) 1278GAT(497) -11 0 -.names 169GAT(24) 1204GAT(434) 1276GAT(498) -11 0 -.names 162GAT(23) 1201GAT(435) 1274GAT(499) -11 0 -.names 155GAT(22) 1198GAT(436) 1272GAT(500) -11 0 -.names 148GAT(21) 1195GAT(437) 1270GAT(501) -11 0 -.names 141GAT(20) 1192GAT(438) 1268GAT(502) -11 0 -.names 134GAT(19) 1189GAT(439) 1266GAT(503) -11 0 -.names 127GAT(18) 1186GAT(440) 1264GAT(504) -11 0 -.names 120GAT(17) 1183GAT(441) 1262GAT(505) -11 0 -.names 113GAT(16) 1180GAT(442) 1260GAT(506) -11 0 -.names 106GAT(15) 1177GAT(443) 1258GAT(507) -11 0 -.names 99GAT(14) 1174GAT(444) 1256GAT(508) -11 0 -.names 92GAT(13) 1171GAT(445) 1254GAT(509) -11 0 -.names 85GAT(12) 1168GAT(446) 1252GAT(510) -11 0 -.names 78GAT(11) 1165GAT(447) 1250GAT(511) -11 0 -.names 71GAT(10) 1162GAT(448) 1248GAT(512) -11 0 -.names 64GAT(9) 1159GAT(449) 1246GAT(513) -11 0 -.names 57GAT(8) 1156GAT(450) 1244GAT(514) -11 0 -.names 50GAT(7) 1153GAT(451) 1242GAT(515) -11 0 -.names 43GAT(6) 1150GAT(452) 1240GAT(516) -11 0 -.names 36GAT(5) 1147GAT(453) 1238GAT(517) -11 0 -.names 29GAT(4) 1144GAT(454) 1236GAT(518) -11 0 -.names 22GAT(3) 1141GAT(455) 1234GAT(519) -11 0 -.names 15GAT(2) 1138GAT(456) 1232GAT(520) -11 0 -.names 8GAT(1) 1135GAT(457) 1230GAT(521) -11 0 -.names 1GAT(0) 1132GAT(458) 1228GAT(522) -11 0 -.names 1266GAT(503) 1267GAT(459) 1311GAT(523) -11 0 -.names 1274GAT(499) 1275GAT(460) 1315GAT(524) -11 0 -.names 1282GAT(495) 1283GAT(461) 1319GAT(525) -11 0 -.names 1290GAT(491) 1291GAT(462) 1323GAT(526) -11 0 -.names 1264GAT(504) 1265GAT(463) 1310GAT(527) -11 0 -.names 1272GAT(500) 1273GAT(464) 1314GAT(528) -11 0 -.names 1280GAT(496) 1281GAT(465) 1318GAT(529) -11 0 -.names 1288GAT(492) 1289GAT(466) 1322GAT(530) -11 0 -.names 1262GAT(505) 1263GAT(467) 1309GAT(531) -11 0 -.names 1270GAT(501) 1271GAT(468) 1313GAT(532) -11 0 -.names 1278GAT(497) 1279GAT(469) 1317GAT(533) -11 0 -.names 1286GAT(493) 1287GAT(470) 1321GAT(534) -11 0 -.names 1260GAT(506) 1261GAT(471) 1308GAT(535) -11 0 -.names 1268GAT(502) 1269GAT(472) 1312GAT(536) -11 0 -.names 1276GAT(498) 1277GAT(473) 1316GAT(537) -11 0 -.names 1284GAT(494) 1285GAT(474) 1320GAT(538) -11 0 -.names 1234GAT(519) 1235GAT(475) 1295GAT(539) -11 0 -.names 1242GAT(515) 1243GAT(476) 1299GAT(540) -11 0 -.names 1250GAT(511) 1251GAT(477) 1303GAT(541) -11 0 -.names 1258GAT(507) 1259GAT(478) 1307GAT(542) -11 0 -.names 1232GAT(520) 1233GAT(479) 1294GAT(543) -11 0 -.names 1240GAT(516) 1241GAT(480) 1298GAT(544) -11 0 -.names 1248GAT(512) 1249GAT(481) 1302GAT(545) -11 0 -.names 1256GAT(508) 1257GAT(482) 1306GAT(546) -11 0 -.names 1230GAT(521) 1231GAT(483) 1293GAT(547) -11 0 -.names 1238GAT(517) 1239GAT(484) 1297GAT(548) -11 0 -.names 1246GAT(513) 1247GAT(485) 1301GAT(549) -11 0 -.names 1254GAT(509) 1255GAT(486) 1305GAT(550) -11 0 -.names 1228GAT(522) 1229GAT(487) 1292GAT(551) -11 0 -.names 1236GAT(518) 1237GAT(488) 1296GAT(552) -11 0 -.names 1244GAT(514) 1245GAT(489) 1300GAT(553) -11 0 -.names 1252GAT(510) 1253GAT(490) 1304GAT(554) -11 0 -.names 1311GAT(523) 1343GAT(555) -1 1 -.names 1315GAT(524) 1347GAT(556) -1 1 -.names 1319GAT(525) 1351GAT(557) -1 1 -.names 1323GAT(526) 1355GAT(558) -1 1 -.names 1310GAT(527) 1342GAT(559) -1 1 -.names 1314GAT(528) 1346GAT(560) -1 1 -.names 1318GAT(529) 1350GAT(561) -1 1 -.names 1322GAT(530) 1354GAT(562) -1 1 -.names 1309GAT(531) 1341GAT(563) -1 1 -.names 1313GAT(532) 1345GAT(564) -1 1 -.names 1317GAT(533) 1349GAT(565) -1 1 -.names 1321GAT(534) 1353GAT(566) -1 1 -.names 1308GAT(535) 1340GAT(567) -1 1 -.names 1312GAT(536) 1344GAT(568) -1 1 -.names 1316GAT(537) 1348GAT(569) -1 1 -.names 1320GAT(538) 1352GAT(570) -1 1 -.names 1295GAT(539) 1327GAT(571) -1 1 -.names 1299GAT(540) 1331GAT(572) -1 1 -.names 1303GAT(541) 1335GAT(573) -1 1 -.names 1307GAT(542) 1339GAT(574) -1 1 -.names 1294GAT(543) 1326GAT(575) -1 1 -.names 1298GAT(544) 1330GAT(576) -1 1 -.names 1302GAT(545) 1334GAT(577) -1 1 -.names 1306GAT(546) 1338GAT(578) -1 1 -.names 1293GAT(547) 1325GAT(579) -1 1 -.names 1297GAT(548) 1329GAT(580) -1 1 -.names 1301GAT(549) 1333GAT(581) -1 1 -.names 1305GAT(550) 1337GAT(582) -1 1 -.names 1292GAT(551) 1324GAT(583) -1 1 -.names 1296GAT(552) 1328GAT(584) -1 1 -.names 1300GAT(553) 1332GAT(585) -1 1 -.names 1304GAT(554) 1336GAT(586) -1 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/alu2.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/alu2.blif deleted file mode 100644 index f3a83d3fe..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/alu2.blif +++ /dev/null @@ -1,263 +0,0 @@ -.model alu4_cl -.inputs a b c d e f g h i j -.outputs k l m n o p -.names j d0 f0 i h m1 n1 c e f o1 l1 g z0 p1 q1 h0 r1 s1 c1 d1 f1 v0 k -1-11------------------- 1 -1-00------------------- 1 -11--0------------------ 1 -0---1-1---------------- 1 -0----1-10-------------- 1 -0-------001------------ 1 -0---1----0-----1------- 1 -0---1----0------1------ 1 -0---1----0-------1----- 1 -0------1-1----------1-- 1 -0---1----1-----------1- 1 -0--------1------1----1- 1 -0---1----0-11---------- 1 -0---1----0---11-------- 1 -0-------01--------01--- 1 -0-------11--1---------1 1 -0---0--010--1---------- 1 -0---0---10-00---------- 1 -.names j d0 e0 f0 i h y0 b d f g h0 w0 z0 a1 b1 j0 e u0 c1 p0 d1 n l -1-10------------------- 1 -1-1-1------------------ 1 -11---0----------------- 1 -0-----1-1-------------- 1 -0-----1--0------------- 1 -1-010------------------ 1 -0----1-1--1------------ 1 -0----1---0-1----------- 1 -0--------0-10---------- 1 -0----1---0----1-------- 1 -0----1---0------1------ 1 -0-------11-----------1- 1 -0----1---1------------1 1 -0--------1-1----------1 1 -0----1---01-1---------- 1 -0----1---0---1-1------- 1 -0--------11------11---- 1 -0--------1-------0-10-- 1 -0----0--001------1----- 1 -0----0---00-0----1----- 1 -.names p0 n m -0- 1 --1 1 -.names b d n -11 1 -.names j c0 d0 e0 f0 i h g0 h0 i0 f j0 k0 l0 e m0 n0 o0 p0 q0 r0 n a b g s0 t0 \ -u0 v0 w0 x0 o -111---------------------------- 1 -1-1---0------------------------ 1 -1-----0--1--------------------- 1 -1--110------------------------- 1 -1-----1--------1--1------------ 1 -1-----1-------------11--------- 1 -1-----1----------1---------1--- 1 -11----0-1-1-------------------- 1 -1-----01---1-1----------------- 1 -1-----1------------1--00------- 1 -1-----1----------1-----1----1-- 1 -1-----1----------1----------11- 1 -1-----01----110---------------- 1 -1-----01----1-0--------1------- 1 -1-----1-----1---1-------01----- 1 -1-----1-----1---1-------0-1---- 1 -1-----1---------1-------011---- 1 -1-----01------1----------1---1- 1 -1-----01------1----------1----1 1 -1-----01------1--------------11 1 -.names m f1 s1 p -11- 1 -1-0 1 -.names w0 l1 c0 -00 1 -.names g h1 d0 -01 1 -.names j m0 e1 j0 r0 n f1 f g h n0 g1 h1 w0 b d i1 c0 i0 j1 k1 k0 l1 o0 p0 s0 \ -m1 n1 a b1 a1 x0 t0 e0 -11---1--------------------------- 1 -1---1----0-----1----------------- 1 -1-------10--------1-------------- 1 -11-------1--------------0-------- 1 -1---1-0----------------------1--- 1 -1---1-0-----------------------1-- 1 -1-11---00------------------------ 1 -1--1---0-0-0--------------------- 1 -1-------001--1------------------- 1 -1-------00--0-1------------------ 1 -1-------101------1--------------- 1 -1-------01--1----1--------------- 1 -1--------01--1--------1---------- 1 -1-1------1----1--------1--------- 1 -1-0------1----0--------1--------- 1 -1--------1--11------------1------ 1 -1--------1--1-1------------1----- 1 -1-------10-1--0-1---------------- 1 -1-------10--1-------11----------- 1 -1-------11--1-0-------------0---- 1 -1-------10---1-----1-----1-----1- 1 -1-------10---0-----1-----0-----1- 1 -1-------10---0-----1-----1-----0- 1 -1-------10---1-----1-----0-----0- 1 -1-------011----------1---1------1 1 -1-------011----------0---0------1 1 -1-------011----------0---1------0 1 -1-------011----------1---0------0 1 -.names j f g h n1 h1 l1 a n0 q0 g0 o1 k1 e r1 q1 p1 t1 i1 f0 -1--1---0-1--------- 1 -1--0----1--1------- 1 -1--0-----1--0------ 1 -1-01-10------------ 1 -1--1100------------ 1 -1-00-0-1----------- 1 -1-11--10----------- 1 -100---0-------1---- 1 -10-0--------0-1---- 1 -100----------1-1--- 1 -100----------1--1-- 1 -1--1--10----------1 1 -1--0---0--1-10----- 1 -1-01----1---0----1- 1 -1--0--0---1--1---1- 1 -1-01----1---1----0- 1 -1--0--1---1--1---0- 1 -.names f g g0 -01 1 -.names e g h0 -01 1 -.names k0 k1 h1 i0 -001 1 -.names b e j0 -10 1 -.names u1 w1 u0 w0 h1 j1 i1 n b k0 -1--1----- 1 -1-------1 1 --11-1---- 1 --1-0--1-- 1 --1---1-1- 1 -.names a k1 l0 -11 1 -.names r0 f1 m0 -11 1 -.names e f n0 -01 1 -.names g0 h0 i1 o0 -1-- 1 --1- 1 ---1 1 -.names b d p0 -1- 1 --1 1 -.names g h1 q0 -11 1 -.names f z0 r0 -01 1 -.names k0 u1 v1 w1 j1 s0 --11-- 1 -0--11 1 -.names t1 k1 t0 -11 1 -.names b w0 u0 -11 1 -.names a l1 v0 -11 1 -.names x1 y1 z1 p0 v1 a2 j1 d j e h b2 b c2 p1 n f n1 a1 b1 w0 ---1----0------------ 1 -1-------1----------- 1 -1--------0---------- 1 --1-1--1------------- 1 ----------0-10------- 1 -----11---11--------- 1 ---------10---111---- 1 ----0----10----1-1--- 1 -----1---101-----0--- 1 ---------101-----01-- 1 ---------10----0-1-1- 1 ---------10---10-1--1 1 -.names t1 l1 x0 -11 1 -.names e g w0 y0 -001 1 -.names e g z0 -10 1 -.names b d a1 -10 1 -.names b d b1 -01 1 -.names g h c1 -10 1 -.names e h d1 -01 1 -.names w0 v0 e1 -11 1 -00 1 -.names a c f1 -11 1 -.names k0 l0 g1 -01 1 -10 1 -.names e f h1 -11 1 -.names e f i1 -00 1 -.names e f j1 -10 1 -.names u1 w1 l1 v0 h1 j1 f1 i1 a k1 -1-1------ 1 -1-------1 1 --1-11---- 1 --1---11-- 1 --10----1- 1 -.names s1 y1 z1 j1 f1 c j e g h b2 c1 a2 q1 a h1 i1 p1 f l1 ---1--0------------- 1 -11-1--------------- 1 --------0----11----- 1 --------0--1---0---- 1 --------0---11----1- 1 -----1--0---1------0 1 -----1-1-01-----1--- 1 -----1-1-01------1-- 1 -.names g l1 m1 -01 1 -.names a g n1 -11 1 -.names g m1 l1 o1 --1- 1 -1-0 1 -.names a c p1 -01 1 -.names a c q1 -10 1 -.names a e r1 -10 1 -.names a c s1 -1- 1 --1 1 -.names k1 u1 w1 j1 g f1 t1 -0-11-- 1 --1--01 1 -.names a2 d1 u1 -11 1 -.names g n v1 -01 1 -.names j c1 w1 -11 1 -.names n f c2 x1 -101 1 -.names g h j y1 -1-1 1 -000 1 -.names e j h1 g0 a2 c1 h z1 ---1--1- 1 -0---10- 1 -10-1--1 1 -.names f j a2 -11 1 -.names j g f h b2 -000- 1 -00-0 1 -.names g h c2 -10 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/alu4.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/alu4.blif deleted file mode 100644 index f20f491ba..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/alu4.blif +++ /dev/null @@ -1,502 +0,0 @@ -.model alu4_cl -.inputs a b c d e f g h i j k l m n -.outputs o p q r s t u v -.names j1 n g3 m k1 h3 m1 i3 e j n1 j3 o1 p1 q1 k3 l3 l s1 t1 r1 u1 m3 n3 o -1----------------------- 1 --111-------------------- 1 --100-------------------- 1 --0--11------------------ 1 --0----111--------------- 1 --0------11---1---------- 1 --0-------1-1--1--------- 1 --0-------11----1-------- 1 --0-------1--1---1------- 1 --0-----0-0--------1----- 1 --0-----1-0----------1--- 1 --0------00-----------1-- 1 --0-------0-------1----1- 1 --0-------0---------1---1 1 -.names j1 n k2 l2 k1 m1 m2 b f j l s1 t1 r1 u1 n2 o2 n1 o1 p1 q1 p2 q2 p -1---------------------- 1 --111------------------- 1 --100------------------- 1 --0---11-1-------------- 1 --0--1--1--1------------ 1 --0----0--0-1----------- 1 --0----1--0---1--------- 1 --0------00----1-------- 1 --0-------01----1------- 1 --0-------0--1---1------ 1 --0------11---------1--- 1 --0-------1----------11- 1 --0-------1-------1----1 1 --0----11-1--------1---- 1 -.names j1 n v1 w1 k1 x1 m1 y1 g j n1 z1 a2 o1 p1 q1 c r1 s1 t1 u1 q -1-------------------- 1 --111----------------- 1 --100----------------- 1 --0--11--------------- 1 --0----111------------ 1 --0---1--00----------- 1 --0-------11-1-------- 1 --0------11----1------ 1 --0-------1-0---1----- 1 --0-----1-0-------1--- 1 --0-----0-0--------1-- 1 --0------00----------1 1 --0-----1-1---1--1---- 1 --0------10------0--1- 1 -.names j1 n m0 p0 k1 l1 m1 h1 h j n1 o1 p1 q1 b1 d1 t r1 s1 t1 d u1 r -1--------------------- 1 --111------------------ 1 --100------------------ 1 --0--11---------------- 1 --0----111------------- 1 --0---1--00------------ 1 --0------11--1--------- 1 --0-------1-1--1------- 1 --0-------1---1-1------ 1 --0-------11-----1----- 1 --0-----1-0-------1---- 1 --0-----0-0--------1--- 1 --0------00-----------1 1 --0------10---------10- 1 -.names t d1 s -1- 1 --1 1 -.names d h t -11 1 -.names n m0 n0 o0 p0 l q0 r0 s0 t0 u0 k i v0 w0 x0 y0 d z0 a1 b1 c1 d1 t e1 f1 \ -g1 h1 i1 u -1-11------------------------- 1 -10--1------------------------ 1 -1--1-0----------------------- 1 -1----1--------1--------1----- 1 -1----1--------------1----1--- 1 -1----01--01------------------ 1 -1-1--0-1---1----------------- 1 -1----1-------1--10----------- 1 -1----1---1-----1--1---------- 1 -1----1---1-----1---1--------- 1 -1----1---------1--11--------- 1 -1----10----1--------1-------- 1 -1----1--------1-------0-1---- 1 -1----1-----------1---1---1--- 1 -1----1---------------1---1-1- 1 -1----0--11--0----1----------- 1 -1----10----1-----1---1------- 1 -1----0--11--0-------------1-- 1 -1----0--1---0----1--------1-- 1 -1----0--1---1-----1--------1- 1 -1----10----1---------1-----1- 1 -1----0--1---1-----1---------1 1 -1----0--1---1--------------11 1 -.names s e f a2 d3 y0 g j3 q2 k3 p2 z1 v -1--1---11--- 1 -1--1----11-- 1 -1--1-----11- 1 -1------11--0 1 -1-------11-0 1 -1--------110 1 -10011------- 1 -100--10----- 1 -.names v1 w1 m0 -1- 1 --0 1 -.names h1 e2 n0 -01 1 -.names k q0 o0 -01 1 -.names n b2 c2 v0 n0 l1 d2 w0 x0 h1 e2 y0 d i l z0 t0 a1 f2 g2 e1 h g1 f1 u0 \ -h2 i1 i2 j2 d1 t p0 -11--1-------------------------- 1 -1-----------1---------------1-- 1 -1-1------10-------------------- 1 -1--1-1-----0------------------- 1 -1-------11----0---------------- 1 -1-----------0-----11----------- 1 -1------1------0------1--------- 1 -1-----------1-----0--------1--- 1 -1------1------------1---------1 1 -1--1-------10-1---------------- 1 -1------1----0-------01--------- 1 -1------1----1-------00--------- 1 -1--1----------0-0-------1------ 1 -1--1----------0-1-------0------ 1 -1-----1------1-----------01---- 1 -1-----1------1-----------10---- 1 -1------1------1-----1--------1- 1 -1-------1-----1111------------- 1 -1-------1-----1001------------- 1 -1-------1-----1010------------- 1 -1-------1-----1100------------- 1 -1-----1-----00--0-----1-------- 1 -1-----1-----00--1-----0-------- 1 -1-----------1-0-1-----11------- 1 -1-----------1-0-0-----01------- 1 -.names i j q0 -11 1 -.names i j r0 -01 1 -.names j k s0 -01 1 -.names b4 c4 b1 h1 t f1 q0 v3 d t0 --1-1----- 1 --1------1 1 -1--0-1--- 1 -1-1---1-- 1 -1---1--1- 1 -.names e3 v2 u0 -10 1 -.names k q0 v0 -11 1 -.names j x2 w0 -01 1 -.names j m1 x0 -11 1 -.names c d3 y0 -01 1 -.names t0 y3 z3 t z0 -0-1- 1 --1-1 1 -.names v2 u2 w2 a1 -11- 1 -1-1 1 --11 1 -.names d h1 b1 -11 1 -.names y1 b3 c c1 -11- 1 -1-1 1 --11 1 -.names d h d1 -00 1 -.names t2 z1 a2 e1 ---1 1 -11- 1 -.names i j f1 -00 1 -.names v2 x3 c g1 -11- 1 -1-1 1 --11 1 -.names d4 d1 e4 t h n i d2 d k f4 g4 u3 x1 s0 j l h1 --01-------------- 1 -1---0------------ 1 ----1-1-1--------- 1 ----1--01--------- 1 ----1-1----1------ 1 ------10------11-- 1 ----1-10----01---- 1 --1---10----0---1- 1 ------00-00-----0- 1 ------00-00------0 1 -----010-1--1---1- 1 -----110-0--11--1- 1 -.names y1 u2 z2 i1 -11- 1 -1-1 1 --11 1 -.names n p1 s0 l4 q0 j1 -011-- 1 -1--11 1 -.names k f1 k1 -1- 1 --1 1 -.names d l l1 -11 1 -.names i k m1 -00 1 -.names l c3 n1 -1- 1 --1 1 -.names i k o1 -11 1 -.names i l p1 -01 1 -.names i u3 q1 -01 1 -.names k l m1 r1 ---1 1 -11- 1 -.names i c3 l4 s1 --1- 1 -1-1 1 -.names l x2 t1 -11 1 -.names i u3 u1 -11 1 -.names k2 l2 v1 -1- 1 --0 1 -.names n b2 v0 r2 w0 s2 y1 t2 e2 c u2 v2 w2 o1 x2 g y2 z2 i2 a3 j2 i b3 g2 c3 \ -x1 d3 y0 l e3 u0 c2 x0 f3 z1 a2 w1 -11------1--------------------------- 1 -1--------1----------1--------------- 1 -1--1----------11-------------------- 1 -1-1----------------------10--------- 1 -1-1------------------------11------- 1 -1-1-------------------------0-1----- 1 -1-----1---------------------0---1--- 1 -1-----1------------------------1-0-- 1 -1---1--1---------------------------1 1 -1----1----111----------------------- 1 -1----1----001----------------------- 1 -1----1----010----------------------- 1 -1----1----100----------------------- 1 -1---1--0-0-----1-------------------- 1 -1---1--0-1-----0-------------------- 1 -1--1---------1--11------------------ 1 -1--1---------1--00------------------ 1 -1--1-----1---------0-0-------------- 1 -1-----1--1--------1---1------------- 1 -1-----0--1--------1---0------------- 1 -1-----0--0------------11------------ 1 -1-----1--0------------01------------ 1 -1--1-----0---------1----1----------- 1 -1-1--------1----------------00------ 1 -1---1--1--------------------1-----0- 1 -.names c l x1 -11 1 -.names d4 h4 z1 a2 e4 i4 c g n i u3 s0 j4 b j l y1 --1-1------------ 1 ---1-1----------- 1 ------10--------- 1 -1------0-------- 1 ---------10-1-1-1 1 -------11101-1--- 1 -------0010--1-1- 1 -------1010--0-1- 1 -------01101-0-1- 1 -.names c g z1 -1- 1 --1 1 -.names c g a2 -11 1 -.names j q1 l o0 b2 -11-- 1 ---11 1 -.names l r0 o0 c2 -01- 1 -1-1 1 -.names j u3 d2 -01 1 -.names f3 y1 e2 -10 1 -.names c1 h1 f2 -01 1 -10 1 -.names l f1 k q0 g2 -11-- 1 -1-10 1 -.names z0 h1 h2 -01 1 -10 1 -.names k g2 f1 i2 --1- 1 -0-1 1 -.names l4 q0 j2 -10 1 -.names m g3 k2 -1- 1 --0 1 -.names n b2 v0 g2 r2 w0 s2 m2 l3 f3 b o3 o1 x2 c3 f i p3 d3 l q3 r3 e3 s3 t3 \ -i2 j2 h3 k3 c2 x0 i3 o2 p2 q2 l2 -11-------1------------------------- 1 -1---------1---------------1-------- 1 -1---1--------1-1------------------- 1 -1-1---------------11--------------- 1 -1-1----------------0--1------------ 1 -1-1-------1----------------1------- 1 -1------1-----------0----------1---- 1 -1------1---------------------1-1--- 1 -1----1----------------------0---1-- 1 -1----1----------------------1-----1 1 -1--1---01-0------------------------ 1 -1--1---10-0------------------------ 1 -1---1-----01--1-------------------- 1 -1---1-----10----0------------------ 1 -1-1----------------011------------- 1 -1-----1--------------1-11---------- 1 -1-----1--------------0-01---------- 1 -1-----1--------------0-10---------- 1 -1-----1--------------1-00---------- 1 -1------11-1--------------1--------- 1 -1------00-1--------------1--------- 1 -1----1----1----0------------0------ 1 -1----1-------------1--------1----1- 1 -1---1--1----1----1-----1----------- 1 -1---1--0----1----0-----1----------- 1 -1---1--0----1----1-----0----------- 1 -1---1--1----1----0-----0----------- 1 -.names d4 h4 p2 e4 q2 i4 b f n i u3 s0 h3 n3 j n2 o2 m2 ---01------------- 1 --1--1------------ 1 ------10---------- 1 -1------0--------- 1 ---------10-11---- 1 -----1---101--1--- 1 ---1-----10---11-- 1 ---------10---011- 1 ---------101--01-1 1 -.names b f n2 -10 1 -.names b f o2 -01 1 -.names b f p2 -00 1 -.names b f q2 -11 1 -.names j l r2 -00 1 -.names k j p1 s2 -011 1 -.names q2 k3 p2 t2 -1-- 1 --10 1 -.names v2 y3 z3 a2 u2 -0-1- 1 --1-1 1 -.names b4 c4 f1 y1 c i g j v2 --1-1---- 1 --1--1--- 1 -1-10---- 1 -1--111-1 1 -1---1110 1 -.names r3 s3 t3 w2 -11- 1 -1-1 1 --11 1 -.names i k x2 -10 1 -.names u2 y1 y2 -11 1 -00 1 -.names m2 s3 p3 z2 -11- 1 -1-1 1 --11 1 -.names x3 v2 a3 -01 1 -10 1 -.names m2 l3 b b3 -11- 1 -1-1 1 --11 1 -.names i k c3 -01 1 -.names a b d3 -00 1 -.names r3 q3 e3 -00 1 -.names m2 i3 f3 -00 1 -.names n b2 u3 q0 v3 r2 m1 i3 q3 k l x2 a e i x0 w3 k1 v0 j m3 n3 g3 -11-----0-------------- 1 -1-11----0------------- 1 -1-----1---0-1--------- 1 -1----1-----1-1-------- 1 -1---------1-0-----1--- 1 -1---1----0----------1- 1 -1---1----0-----------1 1 -1----1--0---1-0------- 1 -1-------0-1----11----- 1 -1-------1-1----10----- 1 -1------1--1-0----1---- 1 -1-----11--0--------1-- 1 -1-----10----1------0-- 1 -1--0---0-11-1--------- 1 -1----1--11--0-0------- 1 -1----1-0-1----1-1----- 1 -1----1-1-1----1-0----- 1 -.names a l h3 -11 1 -.names d4 k4 j3 r0 e4 i4 k3 a e n m3 u3 n3 i3 ---0-1-------- 1 --1----1------ 1 ------1-0----- 1 -1-------0---- 1 ----1-----11-- 1 ----1-----1-11 1 -.names a e j3 -00 1 -.names a e k3 -11 1 -.names a i3 l3 -11 1 -.names a e m3 -10 1 -.names a e n3 -01 1 -.names r3 a4 o3 -01 1 -10 1 -.names w3 i3 p3 -11 1 -.names b4 c4 i3 l3 k3 f1 q0 v3 a q3 --11------ 1 --1------1 1 -1-0--1--- 1 -1--1--1-- 1 -1---1--1- 1 -.names b4 c4 f1 m2 b i f j r3 --1-1---- 1 --1--1--- 1 -1-10---- 1 -1--111-1 1 -1---1110 1 -.names r3 y3 z3 q2 s3 -0-1- 1 --1-1 1 -.names w3 q3 t3 -11 1 -.names k l u3 -10 1 -.names i j v3 -10 1 -.names q3 y3 z3 k3 w3 -0-1- 1 --1-1 1 -.names r3 a4 b x3 -11- 1 -1-1 1 --11 1 -.names k c4 y3 -01 1 -.names j n u1 z3 -011 1 -.names a q3 a4 -11 1 -.names n u3 b4 -11 1 -.names n j p1 c4 -111 1 -.names j l n u3 o1 q0 r0 d4 ----1-1- 1 ---10--1 1 -010-1-- 1 -.names v3 k n l4 e4 -111- 1 -1-01 1 -.names k l f1 q0 f4 -011- 1 -01-1 1 -.names j4 c g g4 -01- 1 -0-0 1 --10 1 -.names n k4 d2 h4 --1- 1 -1-1 1 -.names m1 n j l i4 -100- 1 -10-0 1 -.names n2 o2 n3 j4 --1- 1 -0-1 1 -.names j n f4 q1 k4 --11- 1 -0--1 1 -.names k l l4 -00 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/apex7.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/apex7.blif deleted file mode 100644 index db4f107dc..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/apex7.blif +++ /dev/null @@ -1,220 +0,0 @@ -.model apex7 -.inputs CAPSD CAT0 CAT1 CAT2 CAT3 CAT4 CAT5 VACC MMERR IBT0 IBT1 IBT2 \ -ICLR LSD ACCRPY VERR_N RATR MARSSR VLENESR VSUMESR PLUTO0 PLUTO1 PLUTO2 \ -PLUTO3 PLUTO4 PLUTO5 ORWD_N OWL_N PY END FBI WATCH OVACC KBG_N DEL1 \ -COMPPAR VST0 VST1 STAR0 STAR1 STAR2 STAR3 BULL0 BULL1 BULL2 BULL3 \ -BULL4 BULL5 BULL6 -.outputs SDO LSD_P ACCRPY_P VERR_F RATR_P MARSSR_P VLENESR_P VSUMESR_P \ -PLUTO0_P PLUTO1_P PLUTO2_P PLUTO3_P PLUTO4_P PLUTO5_P ORWD_F OWL_F PY_P \ -END_P FBI_P WATCH_P OVACC_P KBG_F DEL1_P COMPPAR_P VST0_P VST1_P \ -STAR0_P STAR1_P STAR2_P STAR3_P BULL0_P BULL1_P BULL2_P BULL3_P \ -BULL4_P BULL5_P BULL6_P -.names FBI STAR3 C2G5 _260_m_ LSD OWL_N LSD_P -0---11 1 --0--11 1 ---1-11 1 -1000-- 1 -.names ACCRPY OWL_N _199_m__inv _219_m_ ACCRPY_P -11-- 1 ---00 1 -.names VERR_N WATCH _199_m__inv _42_m_ TIMOT OWL_N _219_m_ VERR_F ------01 1 -100---- 1 -1-0-0-- 1 -1--10-- 1 -.names RATR OWL_N _886_m_ COMPPAR _58_m__inv RATR_P ---1-- 1 -11--- 1 ----00 1 -.names MARSSR OWL_N C29G7 TIMOT MARSSR_P -11-- 1 ---01 1 -.names VLENESR OWL_N KBG_N VLENESR_P -11- 1 --10 1 -.names VSUMESR OWL_N VST1 _58_m__inv VSUMESR_P -11-- 1 ---10 1 -.names IBT0 PLUTO0 OWL_N _1015_m_ _894_m_ PLUTO0_P --11-- 1 -0--11 1 -.names IBT0 PLUTO1 OWL_N _1015_m_ _894_m_ PLUTO1_P --11-- 1 -1--11 1 -.names IBT1 PLUTO2 OWL_N IBT0 IBT2 _1015_m_ PLUTO2_P --11--- 1 -0--011 1 -.names IBT1 PLUTO3 OWL_N IBT0 IBT2 _1015_m_ PLUTO3_P --11--- 1 -0--111 1 -.names IBT1 PLUTO4 OWL_N IBT0 IBT2 _1015_m_ PLUTO4_P --11--- 1 -1--011 1 -.names IBT1 PLUTO5 OWL_N IBT0 IBT2 _1015_m_ PLUTO5_P --11--- 1 -1--111 1 -.names WATCH C1G3 ORWD_F -0- 1 --0 1 -.names WATCH TIMOT ICLR END KBG_N OWL_F -0-001 1 --0001 1 -.names PY DEL1 _89_m_ _90_m_ PY_P -1-1- 1 --1-1 1 -.names _58_m__inv _199_m__inv _219_m_ END_P -0-- 1 --00 1 -.names ORWD_N FBI _99_m_ _80_m_ _254_m__inv _260_m_ C2G5 _219_m_ STAR2 \ -_2087_m_ FBI_P --1---0---- 1 -0---00---- 1 ----000---- 1 -0-----10-- 1 --1----10-- 1 ----0--10-- 1 --1----1-11 1 ---1---1-11 1 -.names VACC OWL_N OVACC C29G7 WATCH_P ----0 1 -011- 1 -.names VACC ICLR OVACC_P -10 1 -.names KBG_N _199_m__inv _42_m_ OWL_N _219_m_ KBG_F -10--- 1 -1-1-- 1 ----01 1 -.names CAPSD ICLR DEL1_P -10 1 -.names FBI DEL1 COMPPAR _219_m_ OWL_N COMPPAR_P --100- 1 -0-1-1 1 --01-1 1 -.names VST0 VST1 _89_m_ _90_m_ VST0_P -1-1- 1 --1-1 1 -.names PY VST1 _89_m_ _90_m_ VST1_P --11- 1 -1--1 1 -.names STAR0 _254_m__inv _44_m__inv STAR0_P -00- 1 -1-0 1 -.names STAR0 STAR1 _99_m_ _44_m__inv _2087_m_ _80_m_ _219_m_ STAR1_P --1-0--- 1 -101---- 1 -01--1-- 1 -1----00 1 -.names STAR2 _99_m_ _44_m__inv C2G5 _80_m_ _219_m_ _2087_m_ STAR2_P -1-0---- 1 --1-0--- 1 -1-----1 1 -0---10- 1 -.names OWL_N STAR2 STAR3 _254_m__inv _44_m__inv _2087_m_ _80_m_ \ -STAR3_P ---1-0-- 1 ---1--1- 1 -101---- 1 --100--1 1 -.names BULL0 C29G7 OWL_N WATCH BULL0_P -00-- 1 -1-10 1 -.names BULL1 _1214_m_ BULL0 C29G7 BULL1_P -11-- 1 -0-10 1 -.names BULL1 BULL2 _1214_m_ BULL0 C29G7 BULL2_P --11-- 1 -10-10 1 -.names OWL_N BULL3 _226_m_ BULL3_P -111 1 -100 1 -.names BULL4 OWL_N BULL3 _226_m_ _873_m_ BULL4_P -0---1 1 -110-- 1 -11-1- 1 -.names BULL5 BULL4_P BULL4 _873_m_ OWL_N BULL3 _226_m_ BULL5_P -11----- 1 -0-11--- 1 -1---10- 1 -1---1-1 1 -.names BULL2 BULL3 BULL4 BULL5 BULL6 _1214_m_ _873_m_ _226_m_ OWL_N \ -BULL6_P -----11--- 1 -0---1---1 1 --0--1---1 1 ---0-1---1 1 ----01---1 1 ---110-1-- 1 --111-1-0- 1 -.names STAR2 _80_m_ C2G5 -1- 1 --0 1 -.names C1G3 C29G7 _260_m_ -0- 1 --1 1 -.names ORWD_F _219_m_ C2G5 _199_m__inv -00- 1 --01 1 -.names OWL_N FBI _219_m_ -0- 1 --0 1 -.names STAR3 ORWD_F C2G5 CAT1 WATCH CAT0 _894_m_ _42_m_ -00----- 1 --01---- 1 -0--0101 1 ---10101 1 -.names BULL0 BULL3 BULL4 BULL5 BULL6 BULL1 BULL2 TIMOT -0010110 1 -.names MMERR VST0 _58_m__inv _886_m_ -000 1 -.names OWL_N END _58_m__inv -0- 1 --0 1 -.names OWL_N WATCH C29G7 -0- 1 --0 1 -.names _886_m_ C29G7 TIMOT COMPPAR _58_m__inv VST1 OWL_N KBG_N _1015_m_ -1------- 1 --01----- 1 ----00--- 1 -----01-- 1 -------10 1 -.names IBT1 IBT2 _894_m_ -10 1 -.names CAT1 CAT2 CAT3 CAT4 CAT5 IBT0 _894_m_ CAT0 IBT1 IBT2 C1G3 -0----11--- 1 ------010-- 1 -----01--11 1 ----0-0--11 1 ---0--1--01 1 --0---0--01 1 -.names ICLR FBI _89_m_ -00 1 -.names ICLR FBI _90_m_ -01 1 -.names ORWD_N _260_m_ _99_m_ -00 1 -.names STAR0 STAR1 _80_m_ -11 1 -.names _99_m_ _219_m_ _254_m__inv -01 1 -.names OWL_N _80_m_ _2087_m_ -10 1 -.names ORWD_N OWL_N FBI ORWD_F _44_m__inv --0-- 1 ---1- 1 -0--0 1 -.names OWL_N BULL0 BULL1 WATCH _1214_m_ -10-- 1 -1-0- 1 -1--0 1 -.names WATCH BULL0 BULL1 BULL2 _226_m_ -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names OWL_N BULL3 _226_m_ _873_m_ -110 1 -.names VST0 SDO -1 1 -.end - diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/cavlc.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/cavlc.blif deleted file mode 100644 index 6ea1b8515..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/cavlc.blif +++ /dev/null @@ -1,1394 +0,0 @@ -.model top -.inputs totalcoeffs[0] totalcoeffs[1] totalcoeffs[2] totalcoeffs[3] \ - totalcoeffs[4] ctable[0] ctable[1] ctable[2] trailingones[0] \ - trailingones[1] -.outputs coeff_token[0] coeff_token[1] coeff_token[2] coeff_token[3] \ - coeff_token[4] coeff_token[5] ctoken_len[0] ctoken_len[1] ctoken_len[2] \ - ctoken_len[3] ctoken_len[4] -.names totalcoeffs[3] ctable[0] n22 -00 1 -.names totalcoeffs[1] trailingones[1] n23 -01 1 -.names totalcoeffs[0] trailingones[1] n24 -01 1 -.names totalcoeffs[1] n24 n25 -10 1 -.names n23 n25 n26 -00 1 -.names n22 n26 n27 -11 1 -.names totalcoeffs[0] trailingones[1] n28 -10 1 -.names totalcoeffs[1] n28 n29 -00 1 -.names totalcoeffs[1] trailingones[1] n30 -10 1 -.names ctable[2] n30 n31 -00 1 -.names n29 n31 n32 -01 1 -.names n27 n32 n33 -00 1 -.names totalcoeffs[2] n33 n34 -00 1 -.names totalcoeffs[2] ctable[0] n35 -00 1 -.names totalcoeffs[0] n35 n36 -00 1 -.names totalcoeffs[1] totalcoeffs[2] n37 -11 1 -.names n36 n37 n38 -00 1 -.names trailingones[1] n38 n39 -00 1 -.names totalcoeffs[2] totalcoeffs[3] n40 -00 1 -.names trailingones[1] n40 n41 -10 1 -.names totalcoeffs[0] totalcoeffs[3] n42 -11 1 -.names n41 n42 n43 -00 1 -.names totalcoeffs[1] n43 n44 -00 1 -.names totalcoeffs[1] totalcoeffs[3] n45 -10 1 -.names n44 n45 n46 -00 1 -.names n39 n46 n47 -01 1 -.names ctable[2] n47 n48 -00 1 -.names n34 n48 n49 -00 1 -.names trailingones[0] n49 n50 -00 1 -.names ctable[2] trailingones[0] n51 -11 1 -.names ctable[0] n51 n52 -01 1 -.names ctable[2] trailingones[1] n53 -01 1 -.names n52 n53 n54 -00 1 -.names totalcoeffs[1] n54 n55 -10 1 -.names totalcoeffs[1] ctable[2] n56 -10 1 -.names ctable[0] trailingones[1] n57 -00 1 -.names n56 n57 n58 -01 1 -.names n55 n58 n59 -00 1 -.names totalcoeffs[0] totalcoeffs[2] n60 -10 1 -.names n59 n60 n61 -01 1 -.names totalcoeffs[2] trailingones[1] n62 -10 1 -.names totalcoeffs[0] totalcoeffs[1] n63 -00 1 -.names n62 n63 n64 -11 1 -.names n52 n64 n65 -11 1 -.names n61 n65 n66 -00 1 -.names totalcoeffs[3] n66 n67 -00 1 -.names n50 n67 n68 -00 1 -.names ctable[1] n68 n69 -00 1 -.names totalcoeffs[0] totalcoeffs[2] n70 -00 1 -.names n23 n70 n71 -11 1 -.names ctable[0] n71 n72 -00 1 -.names ctable[1] n72 n73 -10 1 -.names totalcoeffs[0] trailingones[1] n74 -00 1 -.names totalcoeffs[0] trailingones[1] n75 -11 1 -.names n74 n75 n76 -00 1 -.names totalcoeffs[1] n76 n77 -10 1 -.names totalcoeffs[2] n77 n78 -11 1 -.names ctable[0] n78 n79 -11 1 -.names n73 n79 n80 -00 1 -.names trailingones[0] n80 n81 -10 1 -.names totalcoeffs[1] n24 n82 -00 1 -.names trailingones[0] n82 n83 -00 1 -.names totalcoeffs[1] totalcoeffs[2] n84 -01 1 -.names n28 n84 n85 -11 1 -.names n83 n85 n86 -00 1 -.names ctable[0] n86 n87 -00 1 -.names n81 n87 n88 -00 1 -.names totalcoeffs[3] n88 n89 -10 1 -.names totalcoeffs[2] n28 n90 -00 1 -.names ctable[1] n90 n91 -10 1 -.names n40 n77 n92 -11 1 -.names n91 n92 n93 -00 1 -.names ctable[0] n93 n94 -10 1 -.names totalcoeffs[2] trailingones[1] n95 -11 1 -.names totalcoeffs[2] n30 n96 -01 1 -.names n95 n96 n97 -00 1 -.names totalcoeffs[0] totalcoeffs[3] n98 -00 1 -.names n97 n98 n99 -01 1 -.names ctable[1] n99 n100 -11 1 -.names n94 n100 n101 -00 1 -.names trailingones[0] n101 n102 -10 1 -.names totalcoeffs[2] totalcoeffs[3] n103 -10 1 -.names n23 n103 n104 -11 1 -.names totalcoeffs[1] trailingones[0] n105 -10 1 -.names n104 n105 n106 -00 1 -.names totalcoeffs[0] n106 n107 -00 1 -.names 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n245 -00 1 -.names trailingones[0] n245 n246 -01 1 -.names n30 n201 n247 -11 1 -.names n246 n247 n248 -00 1 -.names ctable[2] n248 n249 -10 1 -.names n64 n249 n250 -00 1 -.names totalcoeffs[4] n250 n251 -00 1 -.names ctable[1] n251 n252 -01 1 -.names n22 n252 n253 -11 1 -.names n242 n253 coeff_token[1] -00 0 -.names totalcoeffs[3] trailingones[1] n255 -01 1 -.names n45 n174 n256 -00 1 -.names n255 n256 n257 -00 1 -.names ctable[1] n257 n258 -01 1 -.names totalcoeffs[3] n201 n259 -10 1 -.names ctable[0] n259 n260 -10 1 -.names totalcoeffs[2] ctable[0] n261 -10 1 -.names totalcoeffs[3] n261 n262 -10 1 -.names trailingones[0] n262 n263 -10 1 -.names n260 n263 n264 -00 1 -.names totalcoeffs[1] n264 n265 -10 1 -.names ctable[0] ctable[1] n266 -01 1 -.names trailingones[0] n266 n267 -01 1 -.names n139 n267 n268 -11 1 -.names n265 n268 n269 -00 1 -.names trailingones[1] n269 n270 -00 1 -.names totalcoeffs[1] n199 n271 -00 1 -.names totalcoeffs[2] n186 n272 -10 1 -.names n271 n272 n273 -00 1 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trailingones[1] n561 -10 1 -.names totalcoeffs[0] n561 n562 -01 1 -.names n560 n562 n563 -00 1 -.names trailingones[0] n563 n564 -10 1 -.names n95 n162 n565 -11 1 -.names n564 n565 n566 -00 1 -.names totalcoeffs[3] n566 n567 -00 1 -.names totalcoeffs[3] ctable[0] n568 -11 1 -.names n62 n568 n569 -00 1 -.names totalcoeffs[0] n569 n570 -00 1 -.names totalcoeffs[3] n491 n571 -11 1 -.names n570 n571 n572 -00 1 -.names trailingones[0] n572 n573 -00 1 -.names n554 n561 n574 -11 1 -.names n573 n574 n575 -00 1 -.names n567 n575 n576 -01 1 -.names totalcoeffs[1] n576 n577 -10 1 -.names totalcoeffs[2] totalcoeffs[3] n578 -11 1 -.names totalcoeffs[2] n42 n579 -00 1 -.names n450 n579 n580 -00 1 -.names n578 n580 n581 -00 1 -.names ctable[0] n581 n582 -10 1 -.names n42 n325 n583 -11 1 -.names n582 n583 n584 -00 1 -.names totalcoeffs[1] n584 n585 -00 1 -.names trailingones[0] n381 n586 -11 1 -.names n578 n586 n587 -11 1 -.names n585 n587 n588 -00 1 -.names n577 n588 n589 -01 1 -.names ctable[1] n589 n590 -00 1 -.names n559 n590 n591 -00 1 -.names ctable[2] n591 n592 -00 1 -.names totalcoeffs[2] n305 n593 -10 1 -.names totalcoeffs[0] n593 n594 -01 1 -.names trailingones[1] n51 n595 -01 1 -.names n60 n595 n596 -11 1 -.names n594 n596 n597 -00 1 -.names n216 n597 n598 -10 1 -.names n22 n598 n599 -11 1 -.names n592 n599 n600 -00 1 -.names totalcoeffs[4] n600 n601 -00 1 -.names n35 n98 n602 -11 1 -.names totalcoeffs[4] ctable[2] n603 -10 1 -.names n216 n603 n604 -11 1 -.names n602 n604 n605 -11 1 -.names n601 n605 ctoken_len[1] -00 1 -.names n227 n561 n607 -11 1 -.names n283 n607 n608 -00 1 -.names totalcoeffs[0] n608 n609 -00 1 -.names totalcoeffs[1] ctable[0] n610 -01 1 -.names n22 n610 n611 -00 1 -.names n108 n255 n612 -00 1 -.names n611 n612 n613 -01 1 -.names totalcoeffs[2] n613 n614 -01 1 -.names n332 n435 n615 -10 1 -.names n103 n615 n616 -10 1 -.names n614 n616 n617 -00 1 -.names n609 n617 n618 -01 1 -.names trailingones[0] n618 n619 -00 1 -.names n98 n611 n620 -00 1 -.names totalcoeffs[2] n620 n621 -01 1 -.names n139 n203 n622 -11 1 -.names n621 n622 n623 -00 1 -.names trailingones[0] n623 n624 -10 1 -.names ctable[0] n215 n625 -00 1 -.names n568 n625 n626 -00 1 -.names n37 n626 n627 -11 1 -.names n624 n627 n628 -00 1 -.names trailingones[1] n628 n629 -00 1 -.names n261 n568 n630 -00 1 -.names n259 n630 n631 -00 1 -.names totalcoeffs[1] n631 n632 -11 1 -.names n173 n310 n633 -01 1 -.names n201 n633 n634 -11 1 -.names n632 n634 n635 -00 1 -.names trailingones[1] n635 n636 -10 1 -.names n629 n636 n637 -00 1 -.names n619 n637 n638 -01 1 -.names ctable[1] n638 n639 -00 1 -.names totalcoeffs[1] n125 n640 -00 1 -.names totalcoeffs[2] n640 n641 -10 1 -.names n329 n641 n642 -00 1 -.names totalcoeffs[0] n642 n643 -10 1 -.names ctable[1] n105 n644 -00 1 -.names totalcoeffs[2] n644 n645 -10 1 -.names trailingones[0] n30 n646 -10 1 -.names n329 n646 n647 -10 1 -.names n645 n647 n648 -00 1 -.names n643 n648 n649 -01 1 -.names n386 n649 n650 -10 1 -.names n639 n650 n651 -00 1 -.names ctable[2] n651 n652 -00 1 -.names n146 n506 n653 -00 1 -.names totalcoeffs[0] n653 n654 -00 1 -.names n202 n654 n655 -00 1 -.names trailingones[1] n655 n656 -00 1 -.names n95 n485 n657 -11 1 -.names n656 n657 n658 -00 1 -.names totalcoeffs[1] n658 n659 -00 1 -.names n320 n546 n660 -11 1 -.names n659 n660 n661 -00 1 -.names n22 n661 n662 -10 1 -.names ctable[1] n662 n663 -01 1 -.names n652 n663 n664 -00 1 -.names totalcoeffs[4] n664 n665 -00 1 -.names n22 n603 n666 -11 1 -.names n425 n666 n667 -11 1 -.names n665 n667 ctoken_len[2] -00 1 -.names totalcoeffs[4] n140 n669 -10 1 -.names n203 n399 n670 -11 1 -.names ctable[2] n670 n671 -00 1 -.names n640 n671 n672 -00 1 -.names ctable[2] n140 n673 -00 1 -.names totalcoeffs[0] n673 n674 -10 1 -.names ctable[2] n103 n675 -10 1 -.names totalcoeffs[3] n57 n676 -00 1 -.names totalcoeffs[3] n151 n677 -10 1 -.names n215 n677 n678 -10 1 -.names n676 n678 n679 -00 1 -.names totalcoeffs[2] n679 n680 -00 1 -.names n356 n399 n681 -01 1 -.names ctable[0] n681 n682 -01 1 -.names ctable[1] n586 n683 -00 1 -.names totalcoeffs[3] n683 n684 -00 1 -.names n682 n684 n685 -00 1 -.names n680 n685 n686 -01 1 -.names totalcoeffs[1] n686 n687 -10 1 -.names n215 n409 n688 -10 1 -.names n151 n688 n689 -00 1 -.names totalcoeffs[3] n689 n690 -10 1 -.names totalcoeffs[4] n342 n691 -10 1 -.names totalcoeffs[3] n691 n692 -00 1 -.names n690 n692 n693 -00 1 -.names totalcoeffs[2] n693 n694 -00 1 -.names trailingones[0] n381 n695 -00 1 -.names n676 n695 n696 -10 1 -.names totalcoeffs[2] n696 n697 -11 1 -.names n694 n697 n698 -00 1 -.names totalcoeffs[1] n698 n699 -00 1 -.names ctable[0] n103 n700 -00 1 -.names ctable[1] n700 n701 -10 1 -.names n699 n701 n702 -00 1 -.names n687 n702 n703 -01 1 -.names n675 n703 n704 -01 1 -.names n674 n704 n705 -01 1 -.names n672 n705 n706 -01 1 -.names n669 n706 ctoken_len[3] -01 1 -.names trailingones[0] n29 n708 -00 1 -.names n25 n708 n709 -00 1 -.names n423 n709 n710 -10 1 -.names totalcoeffs[2] n710 n711 -11 1 -.names n430 n711 n712 -00 1 -.names ctable[2] n712 n713 -00 1 -.names n342 n713 ctoken_len[4] -11 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/ctrl.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/ctrl.blif deleted file mode 100644 index 560ceda29..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/ctrl.blif +++ /dev/null @@ -1,358 +0,0 @@ -.model top -.inputs opcode[0] opcode[1] opcode[2] opcode[3] opcode[4] op_ext[0] \ - op_ext[1] -.outputs sel_reg_dst[0] sel_reg_dst[1] sel_alu_opB[0] sel_alu_opB[1] \ - alu_op[0] alu_op[1] alu_op[2] alu_op_ext[0] alu_op_ext[1] alu_op_ext[2] \ - alu_op_ext[3] halt reg_write sel_pc_opA sel_pc_opB beqz bnez bgez bltz \ - jump Cin invA invB sign mem_write sel_wb -.names opcode[0] opcode[1] n35 -10 1 -.names opcode[3] opcode[4] n36 -11 1 -.names n35 n36 n37 -11 1 -.names opcode[1] opcode[3] n38 -11 1 -.names opcode[4] n38 n39 -11 1 -.names n37 n39 n40 -00 1 -.names opcode[2] n40 n41 -00 1 -.names opcode[1] opcode[3] n42 -01 1 -.names opcode[4] n42 n43 -11 1 -.names opcode[3] opcode[4] n44 -00 1 -.names n36 n44 n45 -00 1 -.names opcode[1] n45 n46 -10 1 -.names n43 n46 n47 -00 1 -.names opcode[2] n47 n48 -10 1 -.names n41 n48 sel_reg_dst[0] -00 0 -.names opcode[0] n36 n50 -00 1 -.names opcode[0] n50 n51 -00 1 -.names opcode[1] n51 n52 -00 1 -.names opcode[3] n44 n53 -00 1 -.names opcode[1] n53 n54 -10 1 -.names n52 n54 n55 -00 1 -.names opcode[2] n55 n56 -00 1 -.names opcode[3] opcode[4] n57 -01 1 -.names opcode[3] n57 n58 -00 1 -.names opcode[1] n58 n59 -10 1 -.names opcode[1] n59 n60 -10 1 -.names opcode[2] n60 n61 -10 1 -.names n56 n61 sel_reg_dst[1] -00 1 -.names opcode[0] n45 n63 -00 1 -.names opcode[3] n36 n64 -10 1 -.names opcode[0] n64 n65 -10 1 -.names n63 n65 n66 -00 1 -.names opcode[1] n66 n67 -10 1 -.names n52 n67 n68 -00 1 -.names opcode[2] n68 n69 -00 1 -.names opcode[2] n69 sel_alu_opB[0] -00 1 -.names opcode[0] opcode[3] n71 -00 1 -.names n57 n71 n72 -01 1 -.names opcode[0] n45 n73 -10 1 -.names n72 n73 n74 -00 1 -.names opcode[1] n74 n75 -00 1 -.names n54 n75 n76 -00 1 -.names opcode[2] n76 n77 -00 1 -.names opcode[2] n53 n78 -10 1 -.names n77 n78 sel_alu_opB[1] -00 1 -.names opcode[0] opcode[3] n80 -01 1 -.names opcode[4] op_ext[0] n81 -11 1 -.names n80 n81 n82 -11 1 -.names opcode[3] op_ext[1] n83 -10 1 -.names n36 n83 n84 -01 1 -.names opcode[3] op_ext[0] n85 -10 1 -.names n36 n85 n86 -01 1 -.names opcode[3] op_ext[0] n87 -11 1 -.names n86 n87 n88 -00 1 -.names op_ext[1] n88 n89 -10 1 -.names n84 n89 n90 -00 1 -.names opcode[0] n90 n91 -10 1 -.names n82 n91 n92 -00 1 -.names opcode[1] n92 n93 -10 1 -.names opcode[2] n93 n94 -00 1 -.names opcode[0] n53 n95 -10 1 -.names opcode[0] n95 n96 -10 1 -.names opcode[2] n96 n97 -10 1 -.names n94 n97 alu_op[0] -00 1 -.names opcode[3] op_ext[1] n99 -11 1 -.names n84 n99 n100 -00 1 -.names opcode[1] n100 n101 -10 1 -.names opcode[2] n101 n102 -00 1 -.names opcode[1] n54 n103 -10 1 -.names opcode[2] n103 n104 -10 1 -.names n102 n104 alu_op[1] -00 1 -.names opcode[1] n36 n106 -00 1 -.names n44 n106 n107 -01 1 -.names n44 n50 n108 -01 1 -.names opcode[0] n58 n109 -10 1 -.names n108 n109 n110 -00 1 -.names opcode[1] n110 n111 -10 1 -.names n107 n111 n112 -00 1 -.names opcode[2] n112 n113 -00 1 -.names opcode[2] opcode[3] n114 -11 1 -.names opcode[4] n114 n115 -11 1 -.names n113 n115 alu_op[2] -00 0 -.names opcode[1] opcode[2] n117 -00 1 -.names n52 n117 n118 -01 1 -.names opcode[1] n74 n119 -10 1 -.names n37 n119 n120 -00 1 -.names opcode[2] n120 n121 -10 1 -.names n118 n121 alu_op_ext[0] -00 0 -.names opcode[0] n53 n123 -00 1 -.names opcode[0] n123 n124 -00 1 -.names opcode[1] n124 n125 -10 1 -.names opcode[1] opcode[2] n126 -10 1 -.names n125 n126 n127 -01 1 -.names opcode[1] opcode[2] n128 -11 1 -.names n45 n128 n129 -01 1 -.names n127 n129 alu_op_ext[1] -00 0 -.names n106 n125 n131 -00 1 -.names opcode[2] n131 n132 -00 1 -.names n61 n132 alu_op_ext[2] -00 1 -.names n80 n109 n134 -00 1 -.names opcode[1] n134 n135 -10 1 -.names opcode[2] n107 n136 -00 1 -.names n135 n136 n137 -01 1 -.names n78 n137 alu_op_ext[3] -00 1 -.names opcode[0] n58 n139 -00 1 -.names opcode[0] n139 n140 -00 1 -.names opcode[1] n140 n141 -00 1 -.names opcode[1] n141 n142 -00 1 -.names opcode[2] n142 n143 -00 1 -.names opcode[2] n143 halt -00 1 -.names opcode[1] n134 n145 -00 1 -.names n59 n145 n146 -00 1 -.names opcode[2] n146 n147 -00 1 -.names opcode[1] opcode[4] n148 -01 1 -.names opcode[1] n64 n149 -10 1 -.names n148 n149 n150 -00 1 -.names opcode[2] n150 n151 -10 1 -.names n147 n151 reg_write -00 0 -.names opcode[0] n109 n153 -10 1 -.names opcode[2] n153 n154 -10 1 -.names opcode[2] n154 sel_pc_opA -10 1 -.names opcode[2] n140 n156 -10 1 -.names opcode[2] n156 sel_pc_opB -10 1 -.names opcode[0] n64 n158 -00 1 -.names opcode[0] n158 n159 -00 1 -.names opcode[1] n159 n160 -00 1 -.names opcode[1] n160 n161 -00 1 -.names opcode[2] n161 n162 -10 1 -.names opcode[2] n162 beqz -10 1 -.names opcode[0] n65 n164 -10 1 -.names opcode[1] n164 n165 -00 1 -.names opcode[1] n165 n166 -00 1 -.names opcode[2] n166 n167 -10 1 -.names opcode[2] n167 bnez -10 1 -.names opcode[1] n164 n169 -10 1 -.names opcode[1] n169 n170 -10 1 -.names opcode[2] n170 n171 -10 1 -.names opcode[2] n171 bgez -10 1 -.names opcode[1] n159 n173 -10 1 -.names opcode[1] n173 n174 -10 1 -.names opcode[2] n174 n175 -10 1 -.names opcode[2] n175 bltz -10 1 -.names opcode[2] n58 n177 -10 1 -.names opcode[2] n177 jump -10 1 -.names opcode[0] opcode[1] n179 -11 1 -.names n88 n179 n180 -01 1 -.names n35 n65 n181 -10 1 -.names opcode[2] n181 n182 -00 1 -.names n180 n182 n183 -01 1 -.names opcode[1] n51 n184 -10 1 -.names n106 n184 n185 -00 1 -.names opcode[2] n185 n186 -10 1 -.names n183 n186 Cin -00 1 -.names op_ext[0] n36 n188 -11 1 -.names op_ext[1] n188 n189 -00 1 -.names op_ext[1] n189 n190 -00 1 -.names opcode[0] n190 n191 -10 1 -.names opcode[0] n191 n192 -10 1 -.names opcode[1] n192 n193 -10 1 -.names n165 n193 n194 -00 1 -.names opcode[2] n194 n195 -00 1 -.names opcode[2] n195 invA -00 1 -.names n90 n179 n197 -01 1 -.names opcode[2] n197 n198 -00 1 -.names n186 n198 invB -00 1 -.names opcode[1] n124 n200 -00 1 -.names opcode[1] n96 n201 -10 1 -.names n200 n201 n202 -00 1 -.names opcode[2] n202 n203 -00 1 -.names opcode[2] n203 mem_write -00 1 -.names opcode[1] n96 n205 -00 1 -.names opcode[1] n205 n206 -00 1 -.names opcode[2] n206 n207 -00 1 -.names opcode[2] n207 sel_wb -00 1 -.names sign - 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/dalu.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/dalu.blif deleted file mode 100644 index b3b0547e4..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/dalu.blif +++ /dev/null @@ -1,1103 +0,0 @@ -.model TOP -.inputs Psh2 Psh1 Psh0 Popsel3 Popsel2 Popsel1 Popsel0 Pmusel4 Pmusel3 Pmusel2 \ -Pmusel1 PinD15 PinD14 PinD13 PinD12 PinD11 PinD10 PinD9 PinD8 PinD7 PinD6 \ -PinD5 PinD4 PinD3 PinD2 PinD1 PinD0 PinC15 PinC14 PinC13 PinC12 PinC11 PinC10 \ -PinC9 PinC8 PinC7 PinC6 PinC5 PinC4 PinC3 PinC2 PinC1 PinC0 PinB15 PinB14 \ -PinB13 PinB12 PinB11 PinB10 PinB9 PinB8 PinB7 PinB6 PinB5 PinB4 PinB3 PinB2 \ -PinB1 PinB0 PinA15 PinA14 PinA13 PinA12 PinA11 PinA10 PinA9 PinA8 PinA7 PinA6 \ -PinA5 PinA4 PinA3 PinA2 PinA1 PinA0 -.outputs PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 -.names n1 PO15 -0 1 -.names n2 PO14 -0 1 -.names n3 PO13 -0 1 -.names n4 PO12 -0 1 -.names n5 PO11 -0 1 -.names n6 PO10 -0 1 -.names n7 PO9 -0 1 -.names n8 PO8 -0 1 -.names n9 PO7 -0 1 -.names n10 PO6 -0 1 -.names n11 PO5 -0 1 -.names n12 PO4 -0 1 -.names n13 PO3 -0 1 -.names n14 PO2 -0 1 -.names n15 PO1 -0 1 -.names n16 PO0 -0 1 -.names n184 n185 n36 n120 n1 -111- 1 -11-1 1 -.names n194 n193 n120 n2 -11- 1 -1-1 1 -.names n205 n199 n120 n3 -11- 1 -1-1 1 -.names n212 n96 n209 n4 -11- 1 -1-1 1 -.names n109 n218 n217 n344 n5 -11-- 1 --11- 1 --1-0 1 -.names n222 n224 n225 n354 n6 -111- 1 --110 1 -.names n81 n86 n87 n354 n7 -111- 1 --110 1 -.names n97 n91 n96 n8 -11- 1 -1-1 1 -.names n110 n108 n109 n9 -11- 1 -1-1 1 -.names n121 n114 n120 n10 -11- 1 -1-1 1 -.names n131 n125 n120 n11 -11- 1 -1-1 1 -.names n139 n96 n135 n12 -11- 1 -1-1 1 -.names n152 n143 n120 n13 -11- 1 -1-1 1 -.names n160 n96 n156 n14 -11- 1 -1-1 1 -.names n233 n229 n96 n15 -11- 1 -1-1 1 -.names n241 n237 n96 n16 -11- 1 -1-1 1 -.names n164 n309 n18 -11 1 -.names n34 n35 n20 -1- 1 --1 1 -.names PinD12 PinB12 n18 n20 n17 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PinD9 PinB9 n18 n20 n22 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PinD14 PinB14 n18 n20 n25 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PinD10 PinB10 n18 n20 n28 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PinD11 PinB11 n18 n20 n31 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pmusel2 Pmusel1 n34 -11 1 -00 1 -.names Pmusel4 Pmusel3 n35 -1- 1 --0 1 -.names PinD15 PinB15 n18 n20 n36 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Psh2 n36 n40 -0- 1 --1 1 -.names n40 Psh2 n31 n39 -11- 1 -1-1 1 -.names PinD13 PinB13 n18 n20 n41 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n22 n208 n92 n207 n46 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n378 n93 n39 n353 n47 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names Psh2 n351 n45 -1- 1 --1 1 -.names n46 n47 n17 n45 n44 -111- 1 -11-1 1 -.names Pmusel2 PinC7 PinA7 n49 -11- 1 -0-1 1 --11 1 -.names Pmusel4 n49 n76 n384 n48 -0--0 1 -010- 1 -.names Pmusel2 PinC6 PinA6 n54 -11- 1 -0-1 1 --11 1 -.names Pmusel4 n54 n76 n386 n53 -0--0 1 -010- 1 -.names Pmusel2 PinC5 PinA5 n57 -11- 1 -0-1 1 --11 1 -.names Pmusel4 n57 n76 n389 n56 -0--0 1 -010- 1 -.names Pmusel2 PinC3 PinA3 n60 -11- 1 -0-1 1 --11 1 -.names Pmusel4 n60 n76 n394 n59 -0--0 1 -010- 1 -.names Pmusel2 PinC2 PinA2 n63 -11- 1 -0-1 1 --11 1 -.names Pmusel4 n63 n76 n396 n62 -0--0 1 -010- 1 -.names Pmusel2 PinC1 PinA1 n66 -11- 1 -0-1 1 --11 1 -.names Pmusel4 n66 n76 n409 n65 -0--0 1 -010- 1 -.names Pmusel2 PinC0 PinA0 n69 -11- 1 -0-1 1 --11 1 -.names Pmusel4 n69 n76 n413 n68 -0--0 1 -010- 1 -.names Pmusel2 PinC4 PinA4 n72 -11- 1 -0-1 1 --11 1 -.names Pmusel4 n72 n76 n392 n71 -0--0 1 -010- 1 -.names PinD8 PinB8 n348 n349 n77 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pmusel3 Pmusel1 n76 -1- 1 --0 1 -.names n77 n76 n376 n74 -11- 1 -1-0 1 -.names Pmusel2 PinC9 PinA9 n79 -11- 1 -0-1 1 --11 1 -.names Pmusel4 n76 n79 n377 n78 -0--0 1 -001- 1 -.names Popsel1 Popsel0 n82 -11 1 -00 1 -.names PinA9 n20 n78 n261 n83 -0-01 1 --101 1 -.names Popsel0 Popsel1 n84 -1- 1 --1 1 -.names n82 n83 n44 n84 n81 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n109 n242 n344 n86 -1-- 1 --1- 1 ---0 1 -.names n44 n120 n87 -1- 1 --1 1 -.names PinD8 PinB8 n18 n20 n88 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n102 n207 n31 n45 n94 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n381 n382 n28 n360 n95 -111- 1 -11-1 1 -.names Psh2 n22 n41 n92 -01- 1 -1-1 1 --11 1 -.names Psh1 Psh0 n93 -1- 1 --0 1 -.names n94 n95 n92 n93 n91 -111- 1 -11-1 1 -.names n383 n359 n380 n379 n97 -11-- 1 -1-11 1 -.names n84 n120 n354 n96 -11- 1 --10 1 -.names PinD7 PinB7 n18 n20 n98 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n115 n207 n28 n45 n103 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n385 n382 n22 n360 n104 -111- 1 -11-1 1 -.names Psh2 n17 n88 n102 -11- 1 -0-1 1 --11 1 -.names n103 n104 n102 n93 n101 -111- 1 -11-1 1 -.names n264 n279 n106 -1- 1 --1 1 -.names n253 n266 n107 -11 1 -00 1 -.names n106 n107 n105 -1- 1 --1 1 -.names n270 n359 n101 n96 n110 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n105 n267 n108 -11 1 -00 1 -.names Popsel3 n345 n109 -1- 1 --1 1 -.names PinD6 PinB6 n18 n20 n111 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n126 n207 n22 n45 n116 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n387 n88 n360 n117 -11- 1 -1-1 1 -.names Psh2 n31 n98 n115 -11- 1 -0-1 1 --11 1 -.names n116 n117 n115 n93 n114 -111- 1 -11-1 1 -.names PinA6 n20 n53 n277 n119 -0-01 1 --101 1 -.names n82 n119 n114 n84 n118 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n109 n118 n274 n354 n121 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names Popsel3 Popsel2 n84 n120 -1-- 1 --0- 1 ---0 1 -.names PinD5 PinB5 n18 n20 n122 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n136 n207 n88 n45 n127 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n390 n98 n360 n128 -11- 1 -1-1 1 -.names Psh2 n28 n111 n126 -11- 1 -0-1 1 --11 1 -.names n127 n128 n126 n93 n125 -111- 1 -11-1 1 -.names PinA5 n20 n56 n282 n130 -0-01 1 --101 1 -.names n82 n130 n125 n84 n129 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n109 n129 n278 n354 n131 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names PinD4 PinB4 n18 n20 n132 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n144 n207 n98 n45 n137 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n393 n111 n360 n138 -11- 1 -1-1 1 -.names Psh2 n22 n122 n136 -11- 1 -0-1 1 --11 1 -.names n137 n138 n136 n93 n135 -111- 1 -11-1 1 -.names n283 n109 n285 n359 n139 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names PinD3 PinB3 n18 n20 n140 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n157 n207 n111 n45 n145 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n395 n122 n360 n146 -11- 1 -1-1 1 -.names Psh2 n88 n132 n144 -11- 1 -0-1 1 --11 1 -.names n145 n146 n144 n93 n143 -111- 1 -11-1 1 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n326 -0-- 1 --11 1 -.names PinA11 n20 n176 n326 n323 -0-01 1 --101 1 -.names PinC10 n164 n309 n329 -0-- 1 --11 1 -.names PinC1 n164 n309 n333 -0-- 1 --11 1 -.names PinA1 n20 n65 n333 n330 -0-01 1 --101 1 -.names n250 n253 n335 -1- 1 --0 1 -.names n335 n248 n334 -01 1 -10 1 -.names PinC0 n164 n309 n339 -0-- 1 --11 1 -.names PinA0 n20 n68 n339 n336 -0-01 1 --101 1 -.names n250 n253 n340 -01 1 -10 1 -.names Pmusel4 Pmusel3 n34 n341 -0-- 1 --1- 1 ---1 1 -.names n149 n246 n248 n250 n253 n343 -1---- 1 --1--- 1 ---1-- 1 ----1- 1 -----0 1 -.names n242 n252 n255 n217 n343 n344 -1---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names Popsel2 n84 n345 -11 1 -00 1 -.names Pmusel3 Pmusel2 Pmusel1 n348 -0-- 1 --1- 1 ---1 1 -.names Pmusel3 Pmusel2 Pmusel1 n349 -1-- 1 --0- 1 ---1 1 -.names Psh1 Psh0 n351 -0- 1 --0 1 -.names Psh1 Psh0 n353 -0- 1 --1 1 -.names Popsel3 Popsel2 n354 -10 1 -.names n82 n354 n359 -1- 1 --0 1 -.names Psh2 n353 n360 -1- 1 --1 1 -.names Psh2 n353 n363 -0- 1 --1 1 -.names Pmusel2 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-----1- 1 ------1 1 -.names i_15_ n222 n35 -1- 1 --1 1 -.names i_5_ n65 i_2_ i_1_ n36 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names i_9_ n61 n37 -1- 1 --1 1 -.names i_14_ i_50_ n190 n38 -1-- 1 --1- 1 ---1 1 -.names i_12_ n31 n32 n33 n35 n36 n37 n38 n30 -0------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names n52 n89 n54 n45 -1-- 1 --1- 1 ---1 1 -.names i_42_ n180 n179 n46 -1-- 1 --1- 1 ---1 1 -.names i_59_ n98 n203 n48 -1-- 1 --1- 1 ---1 1 -.names i_53_ i_54_ i_55_ n45 n46 n48 n44 -0----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names i_51_ n202 n50 -1- 1 --1 1 -.names n78 n185 n51 -1- 1 --0 1 -.names i_35_ i_34_ i_33_ n52 -1-- 1 --1- 1 ---1 1 -.names i_41_ n175 n53 -1- 1 --1 1 -.names n65 n37 n64 n54 -1-- 1 --1- 1 ---1 1 -.names i_62_ n108 n204 n55 -1-- 1 --0- 1 ---1 1 -.names i_31_ n50 n51 n52 n53 n54 n55 n49 -0------ 1 --1----- 1 ---1---- 1 ----1--- 1 -----1-- 1 ------1- 1 -------1 1 -.names i_11_ i_10_ n61 -1- 1 --1 1 -.names n198 n104 i_17_ n106 n64 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n196 n197 n65 -1- 1 --1 1 -.names i_56_ i_55_ n66 -1- 1 --1 1 -.names i_51_ i_35_ n53 n67 -1-- 1 --1- 1 ---1 1 -.names i_9_ n51 n61 n64 n65 n66 n67 n91 n60 -0------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------0 1 -.names i_35_ n163 n70 -1- 1 --1 1 -.names i_47_ n180 n71 -1- 1 --1 1 -.names i_40_ i_42_ i_41_ n72 -1-- 1 --1- 1 ---1 1 -.names i_51_ i_50_ n73 -1- 1 --1 1 -.names i_34_ i_55_ n48 n54 n70 n71 n72 n73 n68 -0------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names n65 n208 i_15_ i_30_ n55 n89 n125 n76 -1------ 1 --1----- 1 ---1---- 1 ----1--- 1 -----1-- 1 ------1- 1 -------1 1 -.names i_45_ n175 n77 -1- 1 --1 1 -.names i_50_ n184 n78 -1- 1 --1 1 -.names i_31_ n52 n79 -1- 1 --1 1 -.names i_9_ i_17_ n80 -1- 1 --1 1 -.names i_2_ i_5_ n50 n76 n77 n78 n79 n80 n74 -0------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names n53 n174 n185 n82 -1-- 1 --1- 1 ---0 1 -.names i_53_ n73 n91 n189 n83 -1--- 1 --1-- 1 ---0- 1 ----1 1 -.names i_1_ i_2_ i_5_ n54 n79 n82 n83 n81 -0------ 1 --1----- 1 ---1---- 1 ----1--- 1 -----1-- 1 ------1- 1 -------1 1 -.names n36 n64 n79 n37 n86 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names i_55_ n202 n87 -1- 1 --1 1 -.names i_49_ n48 n73 n82 n86 n87 n85 -0----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names i_37_ n224 n89 -1- 1 --1 1 -.names i_33_ i_34_ i_35_ n46 n54 n55 n89 n88 -0------ 1 --1----- 1 ---1---- 1 ----1--- 1 -----1-- 1 ------1- 1 -------1 1 -.names i_58_ i_59_ i_60_ n187 n91 -0000 1 -.names i_60_ n187 n98 -1- 1 --1 1 -.names i_50_ n203 n99 -1- 1 --1 1 -.names n71 n231 n196 n208 n101 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names i_59_ n72 n98 n99 n101 n97 -0---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names n225 n143 n104 -1- 1 --1 1 -.names i_16_ n199 n36 i_20_ i_21_ i_13_ n105 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names i_29_ i_30_ n106 -0- 1 --1 1 -.names i_19_ i_32_ n20 n77 n79 n104 n105 n106 n102 -0------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names i_58_ n66 n108 -00 1 -.names i_40_ i_43_ n14 n78 n214 n110 -00100 1 -.names i_43_ n129 n112 -01 1 -.names n82 n135 n125 i_30_ i_36_ n191 n117 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names n91 n188 n223 n118 -0-- 1 --1- 1 ---1 1 -.names i_21_ n50 n117 n118 n115 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names i_10_ n198 n121 -00 1 -.names i_18_ n219 n221 n125 -1-- 1 --1- 1 ---1 1 -.names i_36_ n165 n212 n127 -1-- 1 --1- 1 ---1 1 -.names i_32_ n79 n105 n125 n127 n124 -0---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names i_37_ n205 n129 -00 1 -.names i_15_ n192 n132 -01 1 -.names n79 n199 n36 n135 -1-- 1 --1- 1 ---1 1 -.names i_16_ i_21_ i_29_ n104 n127 n135 n133 -0----- 1 --1---- 1 ---0--- 1 ----1-- 1 -----1- 1 ------1 1 -.names i_48_ n184 n137 -1- 1 --1 1 -.names i_49_ n73 n138 -1- 1 --1 1 -.names i_57_ i_62_ n188 n203 n204 n139 -1---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names i_36_ n22 n87 n89 n137 n138 n139 n136 -0------ 1 --1----- 1 ---1---- 1 ----1--- 1 -----1-- 1 ------1- 1 -------1 1 -.names i_10_ n197 n215 n142 -1-- 1 --1- 1 ---1 1 -.names i_22_ i_18_ i_24_ n143 -1-- 1 --1- 1 ---1 1 -.names i_62_ n16 n89 n106 n225 n144 -1---- 1 --0--- 1 ---1-- 1 ----1- 1 -----1 1 -.names i_0_ i_3_ n142 n143 n144 n141 -0---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names i_28_ i_43_ n51 n106 n192 n214 n215 n216 n149 -1------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----0--- 1 ------1-- 1 -------1- 1 --------1 1 -.names i_7_ i_62_ n149 n148 -1-- 1 --0- 1 ---1 1 -.names i_62_ n195 n151 -00 1 -.names i_58_ n112 n121 n154 -011 1 -.names n164 n191 i_52_ n190 n160 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names i_19_ n105 n200 n161 -1-- 1 --1- 1 ---1 1 -.names i_23_ n82 n160 n161 n158 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names i_37_ i_39_ n163 -1- 1 --1 1 -.names n79 n186 i_32_ i_36_ n164 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n139 n87 i_52_ n73 n32 n31 n72 n165 -1------ 1 --1----- 1 ---1---- 1 ----1--- 1 -----1-- 1 ------1- 1 -------1 1 -.names i_23_ n161 n167 -1- 1 --1 1 -.names i_38_ n163 n164 n165 n167 n162 -0---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names n118 n138 n137 i_37_ i_52_ n202 n170 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names i_38_ i_39_ n171 -1- 1 --1 1 -.names i_43_ i_44_ i_45_ n72 n164 n167 n170 n171 n168 -1------- 1 --0------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names i_45_ n184 n174 -1- 1 --1 1 -.names i_42_ i_43_ n175 -1- 1 --1 1 -.names i_27_ i_38_ i_44_ n89 n160 n167 n174 n175 n172 -0------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names i_47_ n73 n179 -1- 1 --1 1 -.names i_46_ i_43_ n180 -1- 1 --1 1 -.names i_9_ n196 n222 n142 n33 n181 -1---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names i_5_ i_45_ n48 n87 n179 n180 n181 n178 -1------ 1 --0----- 1 ---1---- 1 ----1--- 1 -----1-- 1 ------1- 1 -------1 1 -.names i_40_ i_39_ n183 -1- 1 --1 1 -.names i_47_ i_46_ n184 -1- 1 --1 1 -.names i_37_ n183 n185 -00 1 -.names i_28_ n106 n186 -1- 1 --1 1 -.names i_61_ i_62_ n187 -1- 1 --1 1 -.names i_63_ i_64_ n188 -1- 1 --1 1 -.names i_54_ n66 n189 -1- 1 --1 1 -.names n98 n189 i_51_ n188 i_59_ i_58_ i_57_ i_53_ n190 -1------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names i_48_ i_49_ i_50_ n191 -1-- 1 --1- 1 ---1 1 -.names i_24_ i_25_ n192 -00 1 -.names i_26_ n192 n193 -1- 1 --0 1 -.names i_8_ i_7_ n195 -1- 1 --1 1 -.names i_4_ i_0_ i_3_ n196 -1-- 1 --1- 1 ---1 1 -.names i_6_ n195 n197 -1- 1 --1 1 -.names i_15_ i_14_ n198 -1- 1 --1 1 -.names n198 n37 i_12_ i_17_ n199 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names i_22_ i_18_ n193 n200 -1-- 1 --1- 1 ---1 1 -.names i_53_ i_54_ n202 -1- 1 --1 1 -.names i_56_ i_58_ n203 -1- 1 --1 1 -.names i_59_ i_61_ i_60_ n204 -1-- 1 --1- 1 ---1 1 -.names i_28_ i_29_ n205 -1- 1 --0 1 -.names i_14_ n61 n208 -1- 1 --1 1 -.names i_30_ n163 n212 -1- 1 --1 1 -.names i_60_ n203 n214 -1- 1 --1 1 -.names i_11_ n198 n215 -1- 1 --1 1 -.names i_8_ i_10_ n216 -1- 1 --1 1 -.names i_26_ n205 n219 -1- 1 --1 1 -.names i_22_ n192 n221 -1- 1 --0 1 -.names n186 n200 n222 -1- 1 --1 1 -.names i_57_ n66 n223 -1- 1 --1 1 -.names i_41_ n183 n224 -1- 1 --1 1 -.names i_25_ i_26_ i_28_ n225 -1-- 1 --1- 1 ---1 1 -.names i_0_ i_3_ n142 n226 -1-- 1 --1- 1 ---1 1 -.names i_41_ n104 n106 n179 n180 n185 n226 n227 -1------ 1 --1----- 1 ---1---- 1 ----1--- 1 -----1-- 1 ------0- 1 -------1 1 -.names n82 n86 n50 n228 -1-- 1 --1- 1 ---1 1 -.names n91 n191 n228 n229 -0-- 1 --1- 1 ---1 1 -.names i_55_ i_51_ n197 n70 n35 n231 -1---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names i_21_ n190 n117 n232 -1-- 1 --1- 1 ---1 1 -.names i_29_ o_5_ -1 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/elliptic.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/elliptic.blif deleted file mode 100644 index d395d2dc4..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/elliptic.blif +++ /dev/null @@ -1,1479 +0,0 @@ -.model TOP -.inputs PCLK PRESET Preset_0_0_ Pinp_0_0_ Pinp_1_1_ Pinp_2_2_ Pinp_3_3_ \ -Pinp_4_4_ Pinp_5_5_ Pinp_6_6_ Pinp_7_7_ Pinp_8_8_ Pinp_9_9_ Pinp_10_10_ \ -Pinp_11_11_ Pinp_12_12_ Pinp_13_13_ Pinp_14_14_ Pinp_15_15_ -.outputs PDN Pover_0_0_ -.latch N_N8025 N_N8199 re PCLK 2 -.latch N_N9279 N_N9280 re PCLK 2 -.latch N_N8802 N_N8803 re PCLK 2 -.latch N_N7548 N_N8240 re PCLK 2 -.latch N_N6924 N_N8274 re PCLK 2 -.latch N_N7048 N_N8198 re PCLK 2 -.latch N_N7371 N_N8239 re PCLK 2 -.latch N_N8614 N_N8615 re PCLK 2 -.latch N_N7294 N_N7703 re PCLK 2 -.latch N_N7007 N_N8273 re PCLK 2 -.latch N_N8365 N_N8366 re PCLK 2 -.latch N_N7894 N_N8272 re PCLK 2 -.latch N_N6941 N_N8238 re PCLK 2 -.latch N_N7547 N_N8531 re PCLK 2 -.latch N_N7982 N_N7983 re PCLK 2 -.latch N_N7131 N_N8575 re PCLK 2 -.latch N_N7000 N_N7854 re PCLK 2 -.latch N_N7633 N_N8237 re PCLK 2 -.latch N_N7447 N_N8197 re PCLK 2 -.latch N_N7047 N_N8271 re PCLK 2 -.latch N_N6982 N_N8530 re PCLK 2 -.latch N_N7785 N_N8650 re PCLK 2 -.latch N_N7984 N_N7985 re PCLK 2 -.latch N_N8709 N_N8710 re PCLK 2 -.latch N_N7006 N_N8574 re PCLK 2 -.latch N_N8311 N_N8312 re PCLK 2 -.latch N_N8190 N_N8270 re PCLK 2 -.latch N_N7063 N_N8573 re PCLK 2 -.latch N_N8934 N_N8935 re PCLK 2 -.latch N_N7280 N_N8649 re PCLK 2 -.latch N_N7893 N_N8196 re PCLK 2 -.latch N_N8137 N_N8236 re PCLK 2 -.latch N_N9243 N_N9244 re PCLK 2 -.latch N_N8347 N_N8348 re PCLK 2 -.latch N_N9149 N_N9150 re PCLK 2 -.latch N_N7194 N_N8648 re PCLK 2 -.latch N_N7313 N_N8269 re PCLK 2 -.latch N_N7465 N_N8235 re PCLK 2 -.latch N_N9274 N_N9275 re PCLK 2 -.latch N_N8969 N_N8970 re PCLK 2 -.latch N_N7266 N_N9554 re PCLK 2 -.latch N_N9012 N_N9013 re PCLK 2 -.latch N_N8507 N_N8508 re PCLK 2 -.latch N_N8136 N_N8529 re PCLK 2 -.latch N_N9241 N_N9242 re PCLK 2 -.latch N_N8169 N_N8572 re PCLK 2 -.latch N_N7312 N_N8571 re PCLK 2 -.latch N_N8363 N_N9436 re PCLK 2 -.latch N_N7377 N_N8528 re PCLK 2 -.latch N_N8795 N_N8796 re PCLK 2 -.latch N_N7001 N_N7770 re PCLK 2 -.latch N_N8364 N_N9357 re PCLK 2 -.latch N_N8684 N_N8685 re PCLK 2 -.latch N_N9295 N_N9296 re PCLK 2 -.latch N_N6995 N_N9555 re PCLK 2 -.latch N_N6971 N_N7628 re PCLK 2 -.latch N_N9509 N_N9510 re PCLK 2 -.latch N_N9577 N_N9578 re PCLK 2 -.latch N_N8446 N_N8447 re PCLK 2 -.latch N_N7137 N_N9437 re PCLK 2 -.latch N_N7042 N_N7771 re PCLK 2 -.latch N_N7305 N_N8570 re PCLK 2 -.latch N_N8527 N_N8647 re PCLK 2 -.latch N_N6957 N_N7704 re PCLK 2 -.latch N_N6926 N_N8646 re PCLK 2 -.latch N_N6958 N_N7629 re PCLK 2 -.latch N_N7096 NDN3_11 re PCLK 2 -.latch N_N7460 NDN3_12 re PCLK 2 -.latch N_N8036 N_N8037 re PCLK 2 -.latch N_N8540 NDN3_16 re PCLK 2 -.latch N_N7087 NDN3_17 re PCLK 2 -.latch N_N9543 NDN3_19 re PCLK 2 -.latch N_N7883 NDN3_22 re PCLK 2 -.latch N_N8293 NDN3_25 re PCLK 2 -.latch N_N9328 NDN3_26 re PCLK 2 -.latch N_N7301 N_N7584 re PCLK 2 -.latch N_N9620 NDN3_28 re PCLK 2 -.latch N_N8217 NDN3_29 re PCLK 2 -.latch N_N7158 NDN3_40 re PCLK 2 -.latch N_N9425 NDN3_39 re PCLK 2 -.latch N_N7690 NDN3_42 re PCLK 2 -.latch N_N7232 NDN3_44 re PCLK 2 -.latch N_N7574 NDN3_46 re PCLK 2 -.latch N_N7608 N_N9358 re PCLK 2 -.latch N_N9538 N_N9539 re PCLK 2 -.latch N_N7795 N_N9556 re PCLK 2 -.latch N_N8147 N_N7306 re PCLK 2 -.latch N_N7038 NEN3_16 re PCLK 2 -.latch N_N9111 N_N9160 re PCLK 2 -.latch N_N7477 NEN3_19 re PCLK 2 -.latch N_N8299 NEN3_22 re PCLK 2 -.latch N_N7077 N_N8930 re PCLK 2 -.latch N_N7529 NEN3_28 re PCLK 2 -.latch N_N7796 N_N9438 re PCLK 2 -.latch N_N8825 NEN3_34 re PCLK 2 -.latch N_N7891 NEN3_36 re PCLK 2 -.latch N_N8317 NEN3_39 re PCLK 2 -.latch N_N7960 N_N7961 re PCLK 2 -.latch N_N8814 NLC1_2 re PCLK 2 -.latch N_N7126 N_N9359 re PCLK 2 -.latch N_N7475 N_N7476 re PCLK 2 -.latch N_N8576 N_N8577 re PCLK 2 -.latch N_N8178 N_N9289 re PCLK 2 -.latch N_N7397 N_N9557 re PCLK 2 -.latch N_N7238 N_N7630 re PCLK 2 -.latch N_N8829 N_N9161 re PCLK 2 -.latch N_N8690 N_N8691 re PCLK 2 -.latch N_N7449 N_N9439 re PCLK 2 -.latch N_N7747 N_N8798 re PCLK 2 -.latch N_N7750 N_N8869 re PCLK 2 -.latch N_N7450 N_N9360 re PCLK 2 -.latch N_N7535 N_N8911 re PCLK 2 -.latch N_N7451 N_N9290 re PCLK 2 -.latch N_N6942 N_N9558 re PCLK 2 -.latch N_N8181 N_N8993 re PCLK 2 -.latch N_N9039 N_N9162 re PCLK 2 -.latch N_N7538 N_N9034 re PCLK 2 -.latch N_N7998 N_N9440 re PCLK 2 -.latch N_N7799 N_N9361 re PCLK 2 -.latch N_N9297 N_N9298 re PCLK 2 -.latch N_N8737 N_N9559 re PCLK 2 -.latch N_N7193 N_N9163 re PCLK 2 -.latch N_N9549 N_N9550 re PCLK 2 -.latch N_N7729 PDN re PCLK 2 -.latch N_N8170 N_N8171 re PCLK 2 -.latch N_N8172 N_N8173 re PCLK 2 -.latch N_N8385 N_N9011 re PCLK 2 -.latch N_N9551 N_N9552 re PCLK 2 -.latch N_N7515 N_N7701 re PCLK 2 -.latch N_N8286 N_N8964 re PCLK 2 -.latch N_N7957 N_N9291 re PCLK 2 -.latch N_N8345 N_N9560 re PCLK 2 -.latch N_N6917 N_N7627 re PCLK 2 -.latch N_N7095 N_N8913 re PCLK 2 -.latch N_N8755 N_N8756 re PCLK 2 -.latch N_N7059 N_N9164 re PCLK 2 -.latch N_N8015 N_N8016 re PCLK 2 -.latch N_N8952 N_N9441 re PCLK 2 -.latch N_N8283 N_N8847 re PCLK 2 -.latch N_N7094 N_N8631 re PCLK 2 -.latch N_N7870 N_N9362 re PCLK 2 -.latch N_N7199 Pover_0_0_ re PCLK 2 -.latch N_N7015 NDN1_4 re PCLK 2 -.latch N_N7439 N_N8561 re PCLK 2 -.latch N_N6927 N_N9292 re PCLK 2 -.latch N_N7470 N_N9561 re PCLK 2 -.latch N_N7098 NGFDN_3 re PCLK 2 -.latch N_N6928 N_N9165 re PCLK 2 -.latch N_N7382 N_N9442 re PCLK 2 -.latch N_N7528 N_N7768 re PCLK 2 -.latch N_N8117 N_N8118 re PCLK 2 -.latch N_N8122 NDN2_2 re PCLK 2 -.latch N_N8874 N_N8875 re PCLK 2 -.latch N_N7448 N_N7852 re PCLK 2 -.latch N_N7318 N_N7582 re PCLK 2 -.latch N_N9330 N_N9331 re PCLK 2 -.latch N_N7981 N_N9363 re PCLK 2 -.latch N_N9293 N_N9294 re PCLK 2 -.latch N_N9443 NDN3_2 re PCLK 2 -.latch N_N8565 NDN3_4 re PCLK 2 -.latch N_N8399 NDN3_7 re PCLK 2 -.latch N_N7188 NDN3_9 re PCLK 2 -.latch N_N9409 N_N9410 re PCLK 2 -.latch N_N8612 N_N8613 re PCLK 2 -.latch N_N8971 N_N8972 re PCLK 2 -.latch N_N9461 N_N9247 re PCLK 2 -.latch N_N7030 N_N9166 re PCLK 2 -.latch N_N8967 N_N8968 re PCLK 2 -.latch N_N8478 NAK3_13 re PCLK 2 -.latch N_N8451 N_N8668 re PCLK 2 -.latch N_N8922 N_N8923 re PCLK 2 -.latch N_N7162 N_N7769 re PCLK 2 -.latch N_N8926 N_N8933 re PCLK 2 -.latch N_N7163 N_N7702 re PCLK 2 -.latch N_N7828 N_N8978 re PCLK 2 -.latch N_N8140 N_N8141 re PCLK 2 -.latch N_N7132 N_N8200 re PCLK 2 -.latch N_N8722 N_N8929 re PCLK 2 -.latch N_N7446 N_N7853 re PCLK 2 -.latch N_N8356 N_N9031 re PCLK 2 -.latch N_N7379 N_N8241 re PCLK 2 -.latch N_N7357 N_N7583 re PCLK 2 -.latch N_N11 NSr3_13 re PCLK 2 -.latch N_N10 N_N9248 re PCLK 2 -.latch N_N9 NSr3_14 re PCLK 2 -.latch N_N8 NSr3_20 re PCLK 2 -.latch N_N7 N_N9198 re PCLK 2 -.latch N_N6 NSr3_23 re PCLK 2 -.latch N_N5 NSr3_30 re PCLK 2 -.latch N_N4 NSr3_35 re PCLK 2 -.latch N_N3 NSr3_37 re PCLK 2 -.latch N_N2 NSr3_38 re PCLK 2 -.latch N_N1 NSr1_2 re PCLK 2 -.latch N_N0 N_N8603 re PCLK 2 -.names NEN3_28 NDN3_28 n1826 N_N9620 -1-0 1 --10 1 -.names PRESET n1323 N_N9578 n16 -11- 1 --10 1 -.names n16 N_N9577 -0 1 -.names PRESET n2838 n22 -01 1 -.names N_N9552 n22 N_N9551 -11 1 -.names N_N9550 n22 N_N9549 -11 1 -.names NDN3_19 NEN3_19 n1826 N_N9543 -1-0 1 --10 1 -.names N_N9539 n22 N_N9538 -11 1 -.names N_N9510 n22 N_N9509 -11 1 -.names PRESET n413 n3115 N_N9247 n41 -0-1- 1 -00-1 1 -.names n41 N_N9248 N_N9461 -11 1 -.names NDN3_2 n1607 n1826 N_N9443 -1-0 1 --00 1 -.names NDN3_39 NEN3_39 n1826 N_N9425 -1-0 1 --10 1 -.names N_N9410 n22 N_N9409 -11 1 -.names N_N9331 n22 N_N9330 -11 1 -.names NDN3_26 NDN3_25 n1826 N_N9328 -1-0 1 --10 1 -.names N_N9298 n22 N_N9297 -11 1 -.names N_N9296 n22 N_N9295 -11 1 -.names N_N9294 n22 N_N9293 -11 1 -.names N_N9280 n22 N_N9279 -11 1 -.names N_N9275 n22 N_N9274 -11 1 -.names N_N9244 n22 N_N9243 -11 1 -.names N_N9242 n22 N_N9241 -11 1 -.names N_N9150 n22 N_N9149 -11 1 -.names PRESET n1323 N_N9160 n103 -11- 1 --10 1 -.names n103 N_N9111 -0 1 -.names PRESET n1323 N_N9162 n126 -11- 1 --10 1 -.names n126 N_N9039 -0 1 -.names N_N9013 n22 N_N9012 -11 1 -.names N_N8972 n22 N_N8971 -11 1 -.names N_N8970 n22 N_N8969 -11 1 -.names N_N8968 n22 N_N8967 -11 1 -.names N_N9441 n22 N_N8952 -11 1 -.names N_N8935 n22 N_N8934 -11 1 -.names PRESET n1804 n1807 N_N8933 n156 -1-1- 1 --11- 1 -1--0 1 --1-0 1 -.names n156 N_N8926 -0 1 -.names PRESET n1807 n1808 N_N8923 n157 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n157 N_N8922 -0 1 -.names N_N8875 n22 N_N8874 -11 1 -.names PRESET n1323 N_N9161 n191 -11- 1 --10 1 -.names n191 N_N8829 -0 1 -.names NEN3_34 n1826 NGFDN_3 n1855 n193 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n193 N_N8825 -0 1 -.names PRESET PDN n196 -00 1 -.names n196 NLC1_2 NSr1_2 N_N8814 -11- 1 -1-1 1 -.names N_N8803 n22 N_N8802 -11 1 -.names N_N8796 n22 N_N8795 -11 1 -.names N_N8756 n22 N_N8755 -11 1 -.names N_N9559 n22 N_N8737 -11 1 -.names N_N9198 n1799 n1800 n227 -101 1 -.names PRESET N_N8929 n227 N_N8722 -01- 1 -0-1 1 -.names N_N8710 n22 N_N8709 -11 1 -.names N_N8691 n22 N_N8690 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1 -.names i5 i6 net_64 net_263 -11- 1 -1-1 1 --01 1 -.names i3 i4 net_121 net_125 net_264 -0-11 1 --111 1 -.names net_115 net_101 net_45 net_267 -11- 1 -1-1 1 -.names i0 net_249 net_269 -1- 1 --1 1 -.names i4 net_44 net_240 net_269 net_268 -01-1 1 --111 1 -.names i2 net_65 net_128 net_271 -11- 1 -0-1 1 --11 1 -.names i1 i3 net_62 net_271 net_270 -0-11 1 --011 1 -.names i0 net_254 net_272 -1- 1 --1 1 -.names i1 i7 net_222 net_274 -1-- 1 --1- 1 ---1 1 -.names i3 i5 net_206 net_274 net_273 --0-1 1 -0-11 1 -.names i0 i4 i7 S7_q net_255 net_275 -0---- 1 --1--- 1 ---1-- 1 ----0- 1 -----1 1 -.names i2 net_222 net_277 -01 1 -.names i0 S5_q net_98 net_235 net_278 -1--- 1 --0-- 1 ---1- 1 ----1 1 -.names i5 net_182 net_222 net_255 net_279 -0--1 1 --111 1 -.names S3_q net_125 net_247 net_280 -0-- 1 --1- 1 ---1 1 -.names i0 i1 i5 i6 net_281 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names i1 i3 i4 net_98 net_282 -10-- 1 --00- 1 -1--1 1 ---01 1 -.names i2 net_107 net_259 net_285 -01- 1 -1-1 1 --11 1 -.names i2 net_191 net_222 net_284 -11- 1 -0-1 1 --11 1 -.names i4 i7 net_208 net_255 net_286 -0-0- 1 -00-0 1 -.names i2 S4_q S5_q net_51 net_290 --00- 1 -00-1 1 -.names i6 net_95 net_292 -0- 1 --1 1 -.names i2 i7 net_293 -0- 1 --0 1 -.names i5 net_121 net_143 net_153 net_294 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names S7_q net_243 net_260 net_295 -00- 1 --01 1 -.names i0 i4 i6 net_45 net_297 --0-0 1 -000- 1 -.names i2 i6 net_299 -0- 1 --0 1 -.names i2 i3 i4 i5 net_300 -010- 1 -0-00 1 -.names i1 net_245 net_249 net_303 -11- 1 -0-0 1 --10 1 -.names i3 i4 i6 net_306 -0-- 1 --1- 1 ---1 1 -.names i4 net_125 net_306 net_305 -0-1 1 --11 1 -.names i0 i2 net_51 net_244 net_309 -0011 1 -.names net_7 net_324 -0 1 -.names net_21 net_318 -0 1 -.names net_12 net_322 -0 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/i2c.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/i2c.blif deleted file mode 100644 index e7cbdfcf8..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/i2c.blif +++ /dev/null @@ -1,2669 +0,0 @@ -# Benchmark "i2c" written by ABC on Mon Aug 29 15:33:09 2005 -.model i2c -.inputs wb_clk_i wb_rst_i arst_i wb_we_i wb_stb_i wb_cyc_i scl_pad_i \ - sda_pad_i wb_adr_i[0] wb_adr_i[1] wb_adr_i[2] wb_dat_i[0] wb_dat_i[1] \ - wb_dat_i[2] wb_dat_i[3] wb_dat_i[4] wb_dat_i[5] wb_dat_i[6] wb_dat_i[7] -.outputs wb_dat_o[0] wb_dat_o[1] wb_dat_o[2] wb_dat_o[3] wb_dat_o[4] \ - wb_dat_o[5] wb_dat_o[6] wb_dat_o[7] wb_ack_o wb_inta_o scl_pad_o \ - scl_padoen_o sda_pad_o sda_padoen_o - -.latch byte_controller_bit_controller_sda_oen_reg_in byte_controller_bit_controller_sda_oen_reg 1 -.latch byte_controller_bit_controller_scl_oen_reg_in byte_controller_bit_controller_scl_oen_reg 1 -.latch \byte_controller_bit_controller_cnt_reg[15]_in \byte_controller_bit_controller_cnt_reg[15] 0 -.latch byte_controller_bit_controller_al_reg_in byte_controller_bit_controller_al_reg 0 -.latch \byte_controller_bit_controller_c_state_reg[8]_in \byte_controller_bit_controller_c_state_reg[8] 0 -.latch \byte_controller_bit_controller_c_state_reg[13]_in \byte_controller_bit_controller_c_state_reg[13] 0 -.latch \byte_controller_bit_controller_c_state_reg[9]_in \byte_controller_bit_controller_c_state_reg[9] 0 -.latch \byte_controller_bit_controller_c_state_reg[4]_in \byte_controller_bit_controller_c_state_reg[4] 0 -.latch \byte_controller_bit_controller_c_state_reg[3]_in \byte_controller_bit_controller_c_state_reg[3] 0 -.latch \byte_controller_bit_controller_c_state_reg[16]_in \byte_controller_bit_controller_c_state_reg[16] 0 -.latch \byte_controller_bit_controller_c_state_reg[7]_in \byte_controller_bit_controller_c_state_reg[7] 0 -.latch \byte_controller_bit_controller_c_state_reg[15]_in \byte_controller_bit_controller_c_state_reg[15] 0 -.latch \byte_controller_bit_controller_c_state_reg[12]_in \byte_controller_bit_controller_c_state_reg[12] 0 -.latch \byte_controller_bit_controller_c_state_reg[5]_in \byte_controller_bit_controller_c_state_reg[5] 0 -.latch \byte_controller_bit_controller_c_state_reg[6]_in \byte_controller_bit_controller_c_state_reg[6] 0 -.latch \byte_controller_bit_controller_cnt_reg[13]_in \byte_controller_bit_controller_cnt_reg[13] 0 -.latch \byte_controller_bit_controller_c_state_reg[10]_in \byte_controller_bit_controller_c_state_reg[10] 0 -.latch \byte_controller_bit_controller_c_state_reg[0]_in \byte_controller_bit_controller_c_state_reg[0] 0 -.latch \byte_controller_bit_controller_c_state_reg[11]_in \byte_controller_bit_controller_c_state_reg[11] 0 -.latch \byte_controller_bit_controller_c_state_reg[1]_in \byte_controller_bit_controller_c_state_reg[1] 0 -.latch \byte_controller_bit_controller_cnt_reg[14]_in \byte_controller_bit_controller_cnt_reg[14] 0 -.latch \byte_controller_bit_controller_c_state_reg[2]_in \byte_controller_bit_controller_c_state_reg[2] 0 -.latch \byte_controller_bit_controller_c_state_reg[14]_in \byte_controller_bit_controller_c_state_reg[14] 0 -.latch byte_controller_bit_controller_busy_reg_in byte_controller_bit_controller_busy_reg 0 -.latch \byte_controller_bit_controller_cnt_reg[11]_in \byte_controller_bit_controller_cnt_reg[11] 0 -.latch \byte_controller_core_cmd_reg[3]_in \byte_controller_core_cmd_reg[3] 0 -.latch \byte_controller_c_state_reg[1]_in \byte_controller_c_state_reg[1] 0 -.latch \byte_controller_c_state_reg[2]_in \byte_controller_c_state_reg[2] 0 -.latch \byte_controller_core_cmd_reg[2]_in \byte_controller_core_cmd_reg[2] 0 -.latch \byte_controller_core_cmd_reg[1]_in \byte_controller_core_cmd_reg[1] 0 -.latch \byte_controller_sr_reg[0]_in \byte_controller_sr_reg[0] 0 -.latch \byte_controller_sr_reg[1]_in \byte_controller_sr_reg[1] 0 -.latch \byte_controller_sr_reg[2]_in \byte_controller_sr_reg[2] 0 -.latch \byte_controller_sr_reg[3]_in \byte_controller_sr_reg[3] 0 -.latch \byte_controller_sr_reg[4]_in \byte_controller_sr_reg[4] 0 -.latch \byte_controller_sr_reg[5]_in \byte_controller_sr_reg[5] 0 -.latch \byte_controller_sr_reg[6]_in \byte_controller_sr_reg[6] 0 -.latch \byte_controller_sr_reg[7]_in \byte_controller_sr_reg[7] 0 -.latch \byte_controller_bit_controller_cnt_reg[3]_in \byte_controller_bit_controller_cnt_reg[3] 0 -.latch \byte_controller_dcnt_reg[2]_in \byte_controller_dcnt_reg[2] 0 -.latch \byte_controller_bit_controller_cnt_reg[2]_in \byte_controller_bit_controller_cnt_reg[2] 0 -.latch \byte_controller_bit_controller_cnt_reg[6]_in \byte_controller_bit_controller_cnt_reg[6] 0 -.latch \byte_controller_bit_controller_cnt_reg[1]_in \byte_controller_bit_controller_cnt_reg[1] 0 -.latch \byte_controller_bit_controller_cnt_reg[7]_in \byte_controller_bit_controller_cnt_reg[7] 0 -.latch \byte_controller_bit_controller_cnt_reg[0]_in \byte_controller_bit_controller_cnt_reg[0] 0 -.latch \byte_controller_bit_controller_cnt_reg[10]_in \byte_controller_bit_controller_cnt_reg[10] 0 -.latch \byte_controller_bit_controller_cnt_reg[5]_in \byte_controller_bit_controller_cnt_reg[5] 0 -.latch \byte_controller_bit_controller_cnt_reg[8]_in \byte_controller_bit_controller_cnt_reg[8] 0 -.latch \byte_controller_bit_controller_cnt_reg[9]_in \byte_controller_bit_controller_cnt_reg[9] 0 -.latch \byte_controller_bit_controller_cnt_reg[12]_in \byte_controller_bit_controller_cnt_reg[12] 0 -.latch \byte_controller_bit_controller_cnt_reg[4]_in \byte_controller_bit_controller_cnt_reg[4] 0 -.latch \byte_controller_dcnt_reg[0]_in \byte_controller_dcnt_reg[0] 0 -.latch \byte_controller_dcnt_reg[1]_in \byte_controller_dcnt_reg[1] 0 -.latch \byte_controller_c_state_reg[4]_in \byte_controller_c_state_reg[4] 0 -.latch byte_controller_bit_controller_clk_en_reg_in byte_controller_bit_controller_clk_en_reg 1 -.latch byte_controller_bit_controller_sta_condition_reg_in byte_controller_bit_controller_sta_condition_reg 0 -.latch byte_controller_core_txd_reg_in byte_controller_core_txd_reg 0 -.latch byte_controller_ack_out_reg_in byte_controller_ack_out_reg 0 -.latch \byte_controller_c_state_reg[3]_in \byte_controller_c_state_reg[3] 0 -.latch \byte_controller_core_cmd_reg[0]_in \byte_controller_core_cmd_reg[0] 0 -.latch byte_controller_bit_controller_dout_reg_in byte_controller_bit_controller_dout_reg 2 -.latch byte_controller_bit_controller_sto_condition_reg_in byte_controller_bit_controller_sto_condition_reg 0 -.latch \prer_reg[9]_in \prer_reg[9] 1 -.latch \prer_reg[11]_in \prer_reg[11] 1 -.latch \prer_reg[8]_in \prer_reg[8] 1 -.latch \prer_reg[15]_in \prer_reg[15] 1 -.latch \prer_reg[4]_in \prer_reg[4] 1 -.latch \prer_reg[0]_in \prer_reg[0] 1 -.latch \prer_reg[10]_in \prer_reg[10] 1 -.latch \prer_reg[12]_in \prer_reg[12] 1 -.latch \prer_reg[13]_in \prer_reg[13] 1 -.latch \prer_reg[14]_in \prer_reg[14] 1 -.latch \prer_reg[1]_in \prer_reg[1] 1 -.latch \prer_reg[2]_in \prer_reg[2] 1 -.latch \prer_reg[3]_in \prer_reg[3] 1 -.latch \prer_reg[5]_in \prer_reg[5] 1 -.latch \prer_reg[6]_in \prer_reg[6] 1 -.latch \prer_reg[7]_in \prer_reg[7] 1 -.latch \ctr_reg[3]_in \ctr_reg[3] 0 -.latch \ctr_reg[4]_in \ctr_reg[4] 0 -.latch \ctr_reg[5]_in \ctr_reg[5] 0 -.latch \ctr_reg[6]_in \ctr_reg[6] 0 -.latch \ctr_reg[7]_in \ctr_reg[7] 0 -.latch \wb_dat_o_reg[1]_in \wb_dat_o_reg[1] 2 -.latch \ctr_reg[2]_in \ctr_reg[2] 0 -.latch \byte_controller_c_state_reg[0]_in \byte_controller_c_state_reg[0] 0 -.latch \ctr_reg[0]_in \ctr_reg[0] 0 -.latch \ctr_reg[1]_in \ctr_reg[1] 0 -.latch \txr_reg[0]_in \txr_reg[0] 0 -.latch \txr_reg[1]_in \txr_reg[1] 0 -.latch \txr_reg[3]_in \txr_reg[3] 0 -.latch \txr_reg[4]_in \txr_reg[4] 0 -.latch \txr_reg[5]_in \txr_reg[5] 0 -.latch \txr_reg[7]_in \txr_reg[7] 0 -.latch \cr_reg[3]_in \cr_reg[3] 0 -.latch \cr_reg[4]_in \cr_reg[4] 0 -.latch \cr_reg[7]_in \cr_reg[7] 0 -.latch \cr_reg[6]_in \cr_reg[6] 0 -.latch \txr_reg[6]_in \txr_reg[6] 0 -.latch \txr_reg[2]_in \txr_reg[2] 0 -.latch \cr_reg[5]_in \cr_reg[5] 0 -.latch \wb_dat_o_reg[7]_in \wb_dat_o_reg[7] 2 -.latch \wb_dat_o_reg[4]_in \wb_dat_o_reg[4] 2 -.latch \wb_dat_o_reg[3]_in \wb_dat_o_reg[3] 2 -.latch \wb_dat_o_reg[2]_in \wb_dat_o_reg[2] 2 -.latch \wb_dat_o_reg[5]_in \wb_dat_o_reg[5] 2 -.latch byte_controller_ld_reg_in byte_controller_ld_reg 0 -.latch \wb_dat_o_reg[6]_in \wb_dat_o_reg[6] 2 -.latch \wb_dat_o_reg[0]_in \wb_dat_o_reg[0] 2 -.latch byte_controller_shift_reg_in byte_controller_shift_reg 0 -.latch byte_controller_cmd_ack_reg_in byte_controller_cmd_ack_reg 0 -.latch \cr_reg[0]_in \cr_reg[0] 0 -.latch \cr_reg[2]_in \cr_reg[2] 0 -.latch byte_controller_bit_controller_sda_chk_reg_in byte_controller_bit_controller_sda_chk_reg 0 -.latch byte_controller_bit_controller_dSDA_reg_in byte_controller_bit_controller_dSDA_reg 1 -.latch \cr_reg[1]_in \cr_reg[1] 0 -.latch byte_controller_bit_controller_cmd_ack_reg_in byte_controller_bit_controller_cmd_ack_reg 0 -.latch byte_controller_bit_controller_dSCL_reg_in byte_controller_bit_controller_dSCL_reg 1 -.latch byte_controller_bit_controller_cmd_stop_reg_in byte_controller_bit_controller_cmd_stop_reg 0 -.latch tip_reg_in tip_reg 0 -.latch irq_flag_reg_in irq_flag_reg 0 -.latch wb_inta_o_reg_in wb_inta_o_reg 0 -.latch byte_controller_bit_controller_sSCL_reg_in byte_controller_bit_controller_sSCL_reg 1 -.latch byte_controller_bit_controller_sSDA_reg_in byte_controller_bit_controller_sSDA_reg 1 -.latch rxack_reg_in rxack_reg 0 -.latch al_reg_in al_reg 0 -.latch wb_ack_o_reg_in wb_ack_o_reg 2 -.latch byte_controller_bit_controller_dscl_oen_reg_in byte_controller_bit_controller_dscl_oen_reg 2 - -.names [161] - 0 -.names [162] - 1 -.names [161] sda_pad_o -1 1 -.names [161] scl_pad_o -1 1 -.names byte_controller_bit_controller_sda_oen_reg sda_padoen_o -1 1 -.names byte_controller_bit_controller_scl_oen_reg \ - byte_controller_bit_controller_dscl_oen_reg_in -1 1 -.names [957] [777] byte_controller_bit_controller_sda_oen_reg_in -11 0 -.names [963] [777] byte_controller_bit_controller_scl_oen_reg_in -11 0 -.names \byte_controller_bit_controller_cnt_reg[15] [169] -1 1 -.names byte_controller_bit_controller_al_reg [170] -1 1 -.names \byte_controller_bit_controller_c_state_reg[8] [171] -1 1 -.names [555] [200] [865] byte_controller_bit_controller_al_reg_in -11- 0 ---1 0 -.names \byte_controller_bit_controller_c_state_reg[13] [173] -1 1 -.names \byte_controller_bit_controller_c_state_reg[9] [174] -1 1 -.names \byte_controller_bit_controller_c_state_reg[4] [175] -1 1 -.names \byte_controller_bit_controller_c_state_reg[3] [176] -1 1 -.names \byte_controller_bit_controller_c_state_reg[16] [177] -1 1 -.names \byte_controller_bit_controller_c_state_reg[7] [178] -1 1 -.names \byte_controller_bit_controller_c_state_reg[15] [179] -1 1 -.names \byte_controller_bit_controller_c_state_reg[12] [180] -1 1 -.names \byte_controller_bit_controller_c_state_reg[5] [181] -1 1 -.names \byte_controller_bit_controller_c_state_reg[6] [182] -1 1 -.names \byte_controller_bit_controller_cnt_reg[13] [183] -1 1 -.names \byte_controller_bit_controller_c_state_reg[10] [184] -1 1 -.names \byte_controller_bit_controller_c_state_reg[0] [185] -1 1 -.names \byte_controller_bit_controller_c_state_reg[11] [186] -1 1 -.names [239] [814] [1047] \byte_controller_bit_controller_c_state_reg[3]_in -11- 0 ---1 0 -.names [1120] sda_padoen_o [215] [188] -11- 0 ---1 0 -.names [231] [810] [1047] \byte_controller_bit_controller_c_state_reg[9]_in -11- 0 ---1 0 -.names [230] [809] [1047] \byte_controller_bit_controller_c_state_reg[7]_in -11- 0 ---1 0 -.names [229] [706] [790] \byte_controller_bit_controller_c_state_reg[16]_in -00- 1 ---0 1 -.names \byte_controller_bit_controller_c_state_reg[1] [192] -1 1 -.names \byte_controller_bit_controller_cnt_reg[14] [193] -1 1 -.names \byte_controller_bit_controller_c_state_reg[2] [194] -1 1 -.names \byte_controller_bit_controller_c_state_reg[14] [195] -1 1 -.names byte_controller_bit_controller_busy_reg [196] -1 1 -.names [210] [197] -0 1 -.names [269] [697] [819] \byte_controller_bit_controller_c_state_reg[5]_in -11- 0 ---1 0 -.names [268] [502] [733] \byte_controller_bit_controller_c_state_reg[10]_in -00- 1 ---0 1 -.names [576] [262] [722] [262] [200] -11-- 0 ---11 0 -.names [268] [605] [792] \byte_controller_bit_controller_c_state_reg[11]_in -00- 1 ---0 1 -.names [266] [812] [1047] \byte_controller_bit_controller_c_state_reg[6]_in -11- 0 ---1 0 -.names [265] [696] [1047] \byte_controller_bit_controller_c_state_reg[0]_in -11- 0 ---1 0 -.names [786] [233] \byte_controller_bit_controller_c_state_reg[12]_in -11 0 -.names [788] [235] \byte_controller_bit_controller_c_state_reg[15]_in -11 0 -.names \byte_controller_bit_controller_cnt_reg[11] [206] -1 1 -.names \byte_controller_core_cmd_reg[3] [207] -1 1 -.names \byte_controller_c_state_reg[1] [208] -1 1 -.names \byte_controller_c_state_reg[2] [209] -1 1 -.names [1120] [1023] [276] [210] -111 0 -.names [785] [263] \byte_controller_bit_controller_c_state_reg[14]_in -11 0 -.names [967] \byte_controller_bit_controller_c_state_reg[1]_in -0 1 -.names [238] \byte_controller_bit_controller_c_state_reg[2]_in -0 1 -.names [275] [916] [264] byte_controller_bit_controller_busy_reg_in -11- 0 ---1 0 -.names [267] [1120] [215] -00 1 -.names \byte_controller_core_cmd_reg[2] [216] -1 1 -.names \byte_controller_core_cmd_reg[1] [217] -1 1 -.names \byte_controller_sr_reg[0] [218] -1 1 -.names \byte_controller_sr_reg[1] [219] -1 1 -.names \byte_controller_sr_reg[2] [220] -1 1 -.names \byte_controller_sr_reg[3] [221] -1 1 -.names \byte_controller_sr_reg[4] [222] -1 1 -.names \byte_controller_sr_reg[5] [223] -1 1 -.names \byte_controller_sr_reg[6] [224] -1 1 -.names \byte_controller_sr_reg[7] [225] -1 1 -.names \byte_controller_bit_controller_cnt_reg[3] [226] -1 1 -.names [1122] [841] \byte_controller_core_cmd_reg[3]_in -11 1 -.names \byte_controller_dcnt_reg[2] [228] -1 1 -.names [277] [821] [990] [995] [229] -1111 0 -.names [507] [1183] [879] [745] [230] -1111 0 -.names [976] [1074] [874] [868] [231] -1111 0 -.names [290] [525] [1047] \byte_controller_c_state_reg[2]_in -11- 0 ---1 0 -.names [684] [627] [982] [335] [233] -1111 0 -.names \byte_controller_bit_controller_cnt_reg[2] [234] -1 1 -.names [772] [736] [335] [591] [235] -1111 0 -.names [289] [1296] [1047] \byte_controller_c_state_reg[1]_in -11- 0 ---1 0 -.names \byte_controller_bit_controller_cnt_reg[6] [237] -1 1 -.names [688] [992] [1046] [1209] [238] -11-- 0 ---11 0 -.names [1178] [838] [988] [239] -111 0 -.names \byte_controller_bit_controller_cnt_reg[1] [240] -1 1 -.names \byte_controller_bit_controller_cnt_reg[7] [241] -1 1 -.names \byte_controller_bit_controller_cnt_reg[0] [242] -1 1 -.names \byte_controller_bit_controller_cnt_reg[10] [243] -1 1 -.names \byte_controller_bit_controller_cnt_reg[5] [244] -1 1 -.names \byte_controller_bit_controller_cnt_reg[8] [245] -1 1 -.names \byte_controller_bit_controller_cnt_reg[9] [246] -1 1 -.names \byte_controller_bit_controller_cnt_reg[12] [247] -1 1 -.names \byte_controller_bit_controller_cnt_reg[4] [248] -1 1 -.names \byte_controller_dcnt_reg[0] [249] -1 1 -.names \byte_controller_dcnt_reg[1] [250] -1 1 -.names [297] [841] \byte_controller_core_cmd_reg[2]_in -11 1 -.names [337] [321] [1279] \byte_controller_sr_reg[0]_in -11- 0 ---1 0 -.names [338] [322] [1279] \byte_controller_sr_reg[1]_in -11- 0 ---1 0 -.names [339] [323] [865] \byte_controller_sr_reg[2]_in -11- 0 ---1 0 -.names [340] [324] [865] \byte_controller_sr_reg[3]_in -11- 0 ---1 0 -.names [341] [325] [865] \byte_controller_sr_reg[4]_in -11- 0 ---1 0 -.names [342] [326] [1279] \byte_controller_sr_reg[5]_in -11- 0 ---1 0 -.names [343] [327] [1279] \byte_controller_sr_reg[6]_in -11- 0 ---1 0 -.names [344] [328] [1279] \byte_controller_sr_reg[7]_in -11- 0 ---1 0 -.names wb_rst_i [299] \byte_controller_bit_controller_cnt_reg[3]_in -00 1 -.names [1085] [169] [300] [261] -11- 0 ---1 0 -.names [291] [611] [262] -00 1 -.names [545] [335] [988] [772] [263] -1111 0 -.names [291] [880] [264] -11 0 -.names [292] [271] [1074] [287] [265] -1111 0 -.names [504] [335] [1207] [807] [266] -1111 0 -.names [276] [267] -0 1 -.names [277] [268] -0 1 -.names [850] [976] [874] [269] -111 0 -.names \byte_controller_c_state_reg[4] [270] -1 1 -.names byte_controller_bit_controller_clk_en_reg [271] -1 1 -.names [360] [391] [1279] \byte_controller_bit_controller_cnt_reg[1]_in -11- 0 ---1 0 -.names [361] [393] wb_rst_i \byte_controller_bit_controller_cnt_reg[2]_in -11- 0 ---1 0 -.names [386] [362] [1279] \byte_controller_bit_controller_cnt_reg[5]_in -11- 0 ---1 0 -.names byte_controller_bit_controller_sta_condition_reg [275] -0 1 -.names byte_controller_core_txd_reg [276] -1 1 -.names [293] [277] -0 1 -.names [699] [865] [336] \byte_controller_dcnt_reg[1]_in -00- 1 ---0 1 -.names [650] [865] [336] \byte_controller_dcnt_reg[2]_in -00- 1 ---0 1 -.names [390] [392] [1279] \byte_controller_bit_controller_cnt_reg[7]_in -11- 0 ---1 0 -.names [848] [865] [336] \byte_controller_dcnt_reg[0]_in -00- 1 ---0 1 -.names [363] [388] wb_rst_i \byte_controller_bit_controller_cnt_reg[8]_in -11- 0 ---1 0 -.names [397] [387] wb_rst_i \byte_controller_bit_controller_cnt_reg[6]_in -11- 0 ---1 0 -.names [398] [389] wb_rst_i \byte_controller_bit_controller_cnt_reg[9]_in -11- 0 ---1 0 -.names byte_controller_ack_out_reg [285] -1 1 -.names \byte_controller_c_state_reg[3] [286] -1 1 -.names \byte_controller_core_cmd_reg[0] [287] -1 1 -.names byte_controller_bit_controller_dout_reg [288] -1 1 -.names [595] [787] [366] [289] -11- 0 ---1 0 -.names [597] [787] [367] [290] -11- 0 ---1 0 -.names byte_controller_bit_controller_sto_condition_reg [291] -0 1 -.names [892] [1005] [292] -00 1 -.names [1005] [825] [293] -11 0 -.names [357] [841] \byte_controller_c_state_reg[4]_in -11 1 -.names [331] byte_controller_bit_controller_clk_en_reg_in -0 1 -.names \prer_reg[9] [296] -0 1 -.names [365] [421] [525] [549] [297] -1111 0 -.names \prer_reg[11] [298] -0 1 -.names [1235] [464] [394] [299] -11- 0 ---1 0 -.names [169] [1085] [300] -00 1 -.names \prer_reg[8] [301] -0 1 -.names \prer_reg[15] [302] -0 1 -.names \prer_reg[4] [303] -0 1 -.names \prer_reg[0] [304] -0 1 -.names \prer_reg[10] [305] -0 1 -.names \prer_reg[12] [306] -0 1 -.names \prer_reg[13] [307] -0 1 -.names \prer_reg[14] [308] -0 1 -.names \prer_reg[1] [309] -0 1 -.names \prer_reg[2] [310] -0 1 -.names \prer_reg[3] [311] -0 1 -.names \prer_reg[5] [312] -0 1 -.names \prer_reg[6] [313] -0 1 -.names \prer_reg[7] [314] -0 1 -.names \ctr_reg[3] [315] -1 1 -.names \ctr_reg[4] [316] -1 1 -.names \ctr_reg[5] [317] -1 1 -.names \ctr_reg[6] [318] -1 1 -.names \ctr_reg[7] [319] -1 1 -.names \wb_dat_o_reg[1] wb_dat_o[1] -1 1 -.names [856] [405] [321] -00 0 -.names [857] [405] [322] -00 0 -.names [859] [405] [323] -00 0 -.names [858] [405] [324] -00 0 -.names [845] [405] [325] -00 0 -.names [855] [405] [326] -00 0 -.names [854] [405] [327] -00 0 -.names [847] [405] [328] -00 0 -.names [453] [660] [819] \byte_controller_c_state_reg[3]_in -11- 0 ---1 0 -.names \ctr_reg[2] [330] -1 1 -.names [1235] [1056] [865] [331] -11- 0 ---1 0 -.names [404] [648] byte_controller_bit_controller_sta_condition_reg_in -11 1 -.names [471] [455] [1047] byte_controller_ack_out_reg_in -11- 0 ---1 0 -.names [407] [1047] byte_controller_core_txd_reg_in -00 1 -.names [969] [335] -0 1 -.names [405] [1280] [336] -11 0 -.names [405] [349] [337] -11 0 -.names [405] [350] [338] -11 0 -.names [405] [395] [339] -11 0 -.names [405] [351] [340] -11 0 -.names [405] [352] [341] -11 0 -.names [405] [353] [342] -11 0 -.names [405] [364] [343] -11 0 -.names [405] [354] [344] -11 0 -.names [472] [452] [1047] \byte_controller_core_cmd_reg[0]_in -11- 0 ---1 0 -.names \byte_controller_c_state_reg[0] [346] -1 1 -.names \ctr_reg[0] [347] -1 1 -.names \ctr_reg[1] [348] -1 1 -.names \txr_reg[0] [349] -1 1 -.names \txr_reg[1] [350] -1 1 -.names \txr_reg[3] [351] -1 1 -.names \txr_reg[4] [352] -1 1 -.names \txr_reg[5] [353] -1 1 -.names \txr_reg[7] [354] -1 1 -.names \cr_reg[3] [355] -1 1 -.names \cr_reg[4] [356] -1 1 -.names [547] [530] [527] [1134] [357] -1111 0 -.names \cr_reg[7] [358] -1 1 -.names \cr_reg[6] [359] -1 1 -.names [1264] [498] [360] -11 0 -.names [1264] [499] [361] -11 0 -.names [1264] [500] [362] -11 0 -.names [1264] [490] [363] -11 0 -.names \txr_reg[6] [364] -1 1 -.names [1079] [660] [365] -11 1 -.names [596] [457] [599] [366] -111 0 -.names [630] [458] [1082] [367] -111 0 -.names [288] [741] [461] byte_controller_bit_controller_dout_reg_in -01- 1 -1-1 1 -.names [422] [880] \prer_reg[0]_in -11 0 -.names [423] [1280] \prer_reg[10]_in -11 0 -.names [424] [1280] \prer_reg[11]_in -11 0 -.names [425] [1280] \prer_reg[12]_in -11 0 -.names [426] [1280] \prer_reg[13]_in -11 0 -.names [427] [1280] \prer_reg[14]_in -11 0 -.names [428] [1280] \prer_reg[15]_in -11 0 -.names [429] [1280] \prer_reg[1]_in -11 0 -.names [430] [1280] \prer_reg[2]_in -11 0 -.names [420] [603] byte_controller_bit_controller_sto_condition_reg_in -11 1 -.names [431] [1280] \prer_reg[3]_in -11 0 -.names [432] [1280] \prer_reg[4]_in -11 0 -.names [433] [880] \prer_reg[5]_in -11 0 -.names [434] [1280] \prer_reg[6]_in -11 0 -.names [435] [880] \prer_reg[7]_in -11 0 -.names [436] [880] \prer_reg[8]_in -11 0 -.names [437] [1280] \prer_reg[9]_in -11 0 -.names [1235] [624] [386] -00 0 -.names [1275] [569] [387] -00 0 -.names [570] [1275] [388] -00 0 -.names [466] [1275] [389] -00 0 -.names [1264] [489] [390] -11 0 -.names [805] [1275] [391] -00 0 -.names [568] [1275] [392] -00 0 -.names [656] [1275] [393] -00 0 -.names [704] [679] [1235] [394] -11- 0 ---1 0 -.names \txr_reg[2] [395] -1 1 -.names \cr_reg[5] [396] -1 1 -.names [1264] [463] [397] -11 0 -.names [1264] [491] [398] -11 0 -.names \wb_dat_o_reg[7] wb_dat_o[7] -1 1 -.names \wb_dat_o_reg[4] wb_dat_o[4] -1 1 -.names \wb_dat_o_reg[3] wb_dat_o[3] -1 1 -.names \wb_dat_o_reg[2] wb_dat_o[2] -1 1 -.names \wb_dat_o_reg[5] wb_dat_o[5] -1 1 -.names [465] [740] [404] -00 1 -.names byte_controller_ld_reg [405] -1 1 -.names [503] [523] [1047] \byte_controller_c_state_reg[0]_in -11- 0 ---1 0 -.names [529] [225] [476] [407] -11- 0 ---1 0 -.names [477] [1279] \ctr_reg[1]_in -00 1 -.names [478] [865] \ctr_reg[2]_in -00 1 -.names [479] [1279] \ctr_reg[3]_in -00 1 -.names [480] [1279] \ctr_reg[4]_in -00 1 -.names [481] [865] \ctr_reg[5]_in -00 1 -.names [482] [865] \ctr_reg[6]_in -00 1 -.names [483] [865] \ctr_reg[7]_in -00 1 -.names [484] [1279] \ctr_reg[0]_in -00 1 -.names [663] [488] [735] [637] \wb_dat_o_reg[1]_in -1111 0 -.names [459] [599] [417] -11 0 -.names \wb_dat_o_reg[6] wb_dat_o[6] -1 1 -.names [936] [1226] [419] -00 1 -.names [501] [740] [420] -00 1 -.names [572] [1084] [658] [421] -11- 0 ---1 0 -.names [833] [927] [505] [422] -11- 0 ---1 0 -.names [833] [906] [506] [423] -11- 0 ---1 0 -.names [833] [903] [508] [424] -11- 0 ---1 0 -.names [833] [925] [509] [425] -11- 0 ---1 0 -.names [833] [910] [510] [426] -11- 0 ---1 0 -.names [833] [924] [511] [427] -11- 0 ---1 0 -.names [833] [911] [512] [428] -11- 0 ---1 0 -.names [870] [914] [513] [429] -11- 0 ---1 0 -.names [870] [930] [514] [430] -11- 0 ---1 0 -.names [870] [922] [515] [431] -11- 0 ---1 0 -.names [870] [904] [516] [432] -11- 0 ---1 0 -.names [833] [900] [517] [433] -11- 0 ---1 0 -.names [833] [928] [518] [434] -11- 0 ---1 0 -.names [833] [915] [519] [435] -11- 0 ---1 0 -.names [833] [918] [520] [436] -11- 0 ---1 0 -.names [833] [902] [521] [437] -11- 0 ---1 0 -.names [766] [546] [865] \cr_reg[4]_in -11- 0 ---1 0 -.names [765] [574] [865] \cr_reg[5]_in -11- 0 ---1 0 -.names [753] [575] [865] \cr_reg[6]_in -11- 0 ---1 0 -.names [767] [573] [865] \cr_reg[7]_in -11- 0 ---1 0 -.names [531] [1279] \txr_reg[0]_in -00 1 -.names [532] [1279] \txr_reg[1]_in -00 1 -.names [533] [865] \txr_reg[2]_in -00 1 -.names [534] [865] \txr_reg[3]_in -00 1 -.names [535] [865] \txr_reg[4]_in -00 1 -.names [536] [865] \txr_reg[5]_in -00 1 -.names [537] [865] \txr_reg[6]_in -00 1 -.names [538] [1279] \txr_reg[7]_in -00 1 -.names [539] [865] \cr_reg[3]_in -00 1 -.names \wb_dat_o_reg[0] wb_dat_o[0] -1 1 -.names [1100] [808] [571] [452] -11- 0 ---1 0 -.names [729] [813] [526] [453] -11- 0 ---1 0 -.names byte_controller_shift_reg [454] -1 1 -.names [554] [285] [560] [455] -11- 0 ---1 0 -.names byte_controller_cmd_ack_reg [456] -1 1 -.names [1080] [1216] [1139] [457] -111 0 -.names [1100] [1244] [1139] [458] -111 0 -.names [1100] [1126] [459] -11 0 -.names [884] [1204] [1197] [460] -01- 1 -1-1 1 -.names [553] [740] [461] -00 1 -.names [557] [1001] [462] -11 0 -.names [951] [1053] [556] [463] -00- 1 ---0 1 -.names [1242] [1053] [559] [464] -00- 1 ---0 1 -.names [501] [465] -0 1 -.names [1106] [1225] [564] [466] -11- 0 ---1 0 -.names [598] [587] [1047] byte_controller_ld_reg_in -11- 0 ---1 0 -.names [666] [721] [737] [638] \wb_dat_o_reg[2]_in -1111 0 -.names [667] [725] [731] [643] \wb_dat_o_reg[3]_in -1111 0 -.names [668] [724] [728] [639] \wb_dat_o_reg[4]_in -1111 0 -.names [1000] [285] [471] -11 0 -.names [1125] [808] [472] -11 0 -.names [670] [669] [734] [640] \wb_dat_o_reg[5]_in -1111 0 -.names [672] [662] [691] [642] \wb_dat_o_reg[6]_in -1111 0 -.names [671] [601] [738] [641] \wb_dat_o_reg[7]_in -1111 0 -.names [776] [1136] [551] [476] -00- 1 ---0 1 -.names [833] [348] [563] [477] -11- 0 ---1 0 -.names [833] [330] [567] [478] -11- 0 ---1 0 -.names [833] [315] [552] [479] -11- 0 ---1 0 -.names [833] [316] [543] [480] -11- 0 ---1 0 -.names [833] [317] [540] [481] -11- 0 ---1 0 -.names [870] [318] [541] [482] -11- 0 ---1 0 -.names [833] [319] [542] [483] -11- 0 ---1 0 -.names [870] [347] [544] [484] -11- 0 ---1 0 -.names \cr_reg[0] [485] -1 1 -.names \cr_reg[2] [486] -0 1 -.names byte_controller_bit_controller_sda_chk_reg [487] -0 1 -.names [644] [801] [219] [800] [488] -11-- 0 ---11 0 -.names [241] [915] [1053] [489] -01- 1 -1-1 1 -.names [1213] [918] [1056] [490] -01- 1 -1-1 1 -.names [1225] [902] [1056] [491] -01- 1 -1-1 1 -.names [1010] [927] [1056] [492] -01- 1 -1-1 1 -.names [1241] [906] [1056] [493] -01- 1 -1-1 1 -.names [1226] [903] [1056] [494] -01- 1 -1-1 1 -.names [1217] [925] [1054] [495] -01- 1 -1-1 1 -.names [193] [924] [1056] [496] -01- 1 -1-1 1 -.names [1172] [497] -0 1 -.names [1131] [914] [1056] [498] -01- 1 -1-1 1 -.names [1007] [930] [1056] [499] -01- 1 -1-1 1 -.names [1110] [900] [1053] [500] -01- 1 -1-1 1 -.names byte_controller_bit_controller_dSDA_reg [501] -1 1 -.names [695] [743] [1254] [651] [502] -1111 0 -.names [602] [895] [1139] [503] -111 0 -.names [1240] [995] [504] -11 1 -.names [621] [833] [505] -00 1 -.names [609] [833] [506] -00 1 -.names [1240] [988] [507] -11 1 -.names [623] [833] [508] -00 1 -.names [610] [833] [509] -00 1 -.names [612] [833] [510] -00 1 -.names [617] [833] [511] -00 1 -.names [614] [833] [512] -00 1 -.names [615] [833] [513] -00 1 -.names [616] [833] [514] -00 1 -.names [607] [833] [515] -00 1 -.names [622] [833] [516] -00 1 -.names [608] [833] [517] -00 1 -.names [619] [833] [518] -00 1 -.names [620] [833] [519] -00 1 -.names [618] [833] [520] -00 1 -.names [613] [833] [521] -00 1 -.names [636] [732] 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n122 -01 1 -.names B[10] n122 n123 -00 1 -.names B[6] B[9] n124 -10 1 -.names B[4] n124 n125 -01 1 -.names B[5] B[6] n126 -10 1 -.names B[3] n126 n127 -01 1 -.names n125 n127 n128 -00 1 -.names B[2] n128 n129 -00 1 -.names B[1] n126 n130 -01 1 -.names n125 n130 n131 -00 1 -.names B[3] n131 n132 -00 1 -.names B[2] B[3] n133 -11 1 -.names B[4] n124 n134 -11 1 -.names n133 n134 n135 -11 1 -.names B[10] n135 n136 -00 1 -.names n132 n136 n137 -01 1 -.names n129 n137 n138 -01 1 -.names B[7] n138 n139 -00 1 -.names n75 n139 n140 -00 1 -.names B[8] n140 n141 -00 1 -.names B[6] B[10] n142 -11 1 -.names B[7] n142 n143 -11 1 -.names n89 n143 n144 -11 1 -.names n141 n144 n145 -00 1 -.names n123 n145 M[1] -01 1 -.names B[4] B[6] n147 -10 1 -.names B[0] B[3] n148 -10 1 -.names n147 n148 n149 -11 1 -.names B[4] B[5] n150 -01 1 -.names B[3] n150 n151 -11 1 -.names n149 n151 n152 -00 1 -.names B[1] n152 n153 -10 1 -.names B[4] B[6] n154 -00 1 -.names B[0] B[1] n155 -11 1 -.names B[4] n155 n156 -10 1 -.names B[3] n156 n157 -11 1 -.names n154 n157 n158 -00 1 -.names B[5] n158 n159 -00 1 -.names n153 n159 n160 -00 1 -.names B[2] n160 n161 -10 1 -.names B[3] B[6] n162 -10 1 -.names B[2] n162 n163 -01 1 -.names B[3] B[5] n164 -01 1 -.names n163 n164 n165 -00 1 -.names B[4] n165 n166 -10 1 -.names n161 n166 n167 -00 1 -.names B[7] n167 n168 -00 1 -.names B[5] B[6] n169 -01 1 -.names B[2] n169 n170 -11 1 -.names n130 n170 n171 -00 1 -.names B[4] n171 n172 -10 1 -.names B[3] n172 n173 -11 1 -.names B[5] n93 n174 -10 1 -.names B[6] n174 n175 -11 1 -.names n173 n175 n176 -00 1 -.names n168 n176 n177 -01 1 -.names B[8] n177 n178 -00 1 -.names B[6] B[7] n179 -01 1 -.names B[3] n179 n180 -11 1 -.names B[6] B[7] n181 -10 1 -.names B[2] n181 n182 -01 1 -.names n180 n182 n183 -00 1 -.names B[5] n183 n184 -10 1 -.names B[4] n184 n185 -11 1 -.names B[4] B[5] n186 -11 1 -.names B[7] n186 n187 -10 1 -.names B[6] n187 n188 -11 1 -.names n185 n188 n189 -00 1 -.names n178 n189 n190 -01 1 -.names B[9] n190 n191 -00 1 -.names B[4] B[6] n192 -11 1 -.names n33 n192 n193 -11 1 -.names n179 n193 n194 -00 1 -.names B[8] n194 n195 -10 1 -.names n191 n195 n196 -00 1 -.names B[10] n196 n197 -00 1 -.names B[8] B[10] n198 -11 1 -.names B[8] B[9] n199 -01 1 -.names B[5] n199 n200 -11 1 -.names n198 n200 n201 -00 1 -.names B[7] n201 n202 -10 1 -.names B[6] n202 n203 -11 1 -.names B[5] B[7] n204 -11 1 -.names B[8] n204 n205 -10 1 -.names B[10] n205 n206 -00 1 -.names B[9] n206 n207 -10 1 -.names n203 n207 n208 -00 1 -.names n197 n208 M[2] -01 0 -.names B[6] B[7] n210 -11 1 -.names B[2] n210 n211 -01 1 -.names B[5] n28 n212 -11 1 -.names n211 n212 n213 -11 1 -.names B[5] n20 n214 -01 1 -.names n103 n214 n215 -11 1 -.names n213 n215 n216 -00 1 -.names B[9] n216 n217 -00 1 -.names B[10] n217 n218 -01 1 -.names B[3] n218 M[3] -01 0 -.names B[5] B[6] n220 -11 1 -.names B[4] B[7] n221 -10 1 -.names n220 n221 n222 -11 1 -.names B[5] B[6] n223 -00 1 -.names n155 n223 n224 -11 1 -.names n222 n224 n225 -00 1 -.names B[3] n225 n226 -10 1 -.names B[2] n226 n227 -11 1 -.names B[4] n181 n228 -00 1 -.names B[7] n126 n229 -00 1 -.names B[3] n229 n230 -00 1 -.names B[7] n220 n231 -10 1 -.names B[6] n83 n232 -00 1 -.names B[5] n232 n233 -11 1 -.names B[9] n233 n234 -00 1 -.names n231 n234 n235 -01 1 -.names n230 n235 n236 -01 1 -.names n228 n236 n237 -01 1 -.names n227 n237 n238 -01 1 -.names B[8] n238 n239 -00 1 -.names B[3] B[8] n240 -11 1 -.names n65 n240 n241 -00 1 -.names B[6] n241 n242 -10 1 -.names B[5] n242 n243 -11 1 -.names B[7] n243 n244 -11 1 -.names B[9] n244 n245 -01 1 -.names B[4] n245 n246 -11 1 -.names B[7] n220 n247 -11 1 -.names B[9] n247 n248 -10 1 -.names n246 n248 n249 -00 1 -.names n239 n249 n250 -01 1 -.names B[10] n250 E[0] -00 0 -.names B[6] B[8] n252 -11 1 -.names n204 n252 n253 -11 1 -.names B[1] B[3] n254 -11 1 -.names B[0] n254 n255 -11 1 -.names B[5] B[7] n256 -00 1 -.names B[8] n256 n257 -01 1 -.names n255 n257 n258 -11 1 -.names n253 n258 n259 -00 1 -.names B[2] n259 n260 -10 1 -.names B[8] n204 n261 -11 1 -.names B[3] B[6] n262 -11 1 -.names n261 n262 n263 -11 1 -.names n260 n263 n264 -00 1 -.names B[4] n264 n265 -10 1 -.names n133 n192 n266 -11 1 -.names B[5] n266 n267 -10 1 -.names n169 n267 n268 -00 1 -.names B[7] n268 n269 -00 1 -.names B[8] n269 n270 -01 1 -.names B[9] B[10] n271 -00 1 -.names n270 n271 n272 -01 1 -.names n265 n272 E[1] -01 0 -.names B[2] n93 n274 -11 1 -.names n220 n274 n275 -11 1 -.names B[9] n275 n276 -00 1 -.names B[10] n276 n277 -01 1 -.names n53 n277 E[2] -11 0 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/mult32a.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/mult32a.blif deleted file mode 100644 index 8c2c27cce..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/mult32a.blif +++ /dev/null @@ -1,1033 +0,0 @@ -## inputs 33 -## outputs 1 -## latches 32 -## initial 00000000000000000000000000000000 -# - - - -.model MultiplierA_32 -.inputs 1 3 4 5 6 7 8 9 10 11 -.inputs 12 13 14 15 16 17 18 19 20 21 -.inputs 22 23 24 25 26 27 28 29 30 31 -.inputs 32 33 34 - -.outputs 68 -.latch 67 2 0 -.latch 69 36 0 -.latch 70 37 0 -.latch 71 38 0 -.latch 72 39 0 -.latch 73 40 0 -.latch 74 41 0 -.latch 75 42 0 -.latch 76 43 0 -.latch 77 44 0 -.latch 78 45 0 -.latch 79 46 0 -.latch 80 47 0 -.latch 81 48 0 -.latch 82 49 0 -.latch 83 50 0 -.latch 84 51 0 -.latch 85 52 0 -.latch 86 53 0 -.latch 87 54 0 -.latch 88 55 0 -.latch 89 56 0 -.latch 90 57 0 -.latch 91 58 0 -.latch 92 59 0 -.latch 93 60 0 -.latch 94 61 0 -.latch 95 62 0 -.latch 96 63 0 -.latch 97 64 0 -.latch 98 65 0 -.latch 99 66 0 - -.names 101 100 -0 1 - -.names 1 204 101 -00 1 -11 1 - -.names 3 102 -1 1 - -.names 4 103 -1 1 - -.names 5 104 -1 1 - -.names 6 105 -1 1 - -.names 7 106 -1 1 - -.names 8 107 -1 1 - -.names 9 108 -1 1 - -.names 10 109 -1 1 - -.names 11 110 -1 1 - -.names 12 111 -1 1 - -.names 13 112 -1 1 - -.names 14 113 -1 1 - -.names 15 114 -1 1 - -.names 16 115 -1 1 - -.names 17 116 -1 1 - -.names 18 117 -1 1 - -.names 19 118 -1 1 - -.names 20 119 -1 1 - -.names 21 120 -1 1 - -.names 22 121 -1 1 - -.names 23 122 -1 1 - -.names 24 123 -1 1 - -.names 25 124 -1 1 - -.names 26 125 -1 1 - -.names 27 126 -1 1 - -.names 28 127 -1 1 - -.names 29 128 -1 1 - -.names 30 129 -1 1 - -.names 31 130 -1 1 - -.names 32 131 -1 1 - -.names 33 132 -1 1 - -.names 34 133 -1 1 - -.names 134 - -.names 135 - -.names 136 - -.names 137 - -.names 138 - -.names 139 - -.names 140 - -.names 141 - -.names 142 - -.names 143 - -.names 144 - -.names 145 - -.names 146 - -.names 147 - -.names 148 - -.names 149 - -.names 150 - -.names 151 - -.names 152 - -.names 153 - -.names 154 - -.names 155 - -.names 156 - -.names 157 - -.names 158 - -.names 159 - -.names 160 - -.names 161 - -.names 162 - -.names 163 - -.names 164 - -.names 165 - -.names 66 265 266 166 --11 1 -1-1 1 -11- 1 - -.names 36 205 206 167 -010 1 -001 1 -100 1 -111 1 - -.names 37 207 208 168 -010 1 -001 1 -100 1 -111 1 - -.names 38 209 210 169 -010 1 -001 1 -100 1 -111 1 - -.names 39 211 212 170 -010 1 -001 1 -100 1 -111 1 - -.names 40 213 214 171 -010 1 -001 1 -100 1 -111 1 - -.names 41 215 216 172 -010 1 -001 1 -100 1 -111 1 - -.names 42 217 218 173 -010 1 -001 1 -100 1 -111 1 - -.names 43 219 220 174 -010 1 -001 1 -100 1 -111 1 - -.names 44 221 222 175 -010 1 -001 1 -100 1 -111 1 - -.names 45 223 224 176 -010 1 -001 1 -100 1 -111 1 - -.names 46 225 226 177 -010 1 -001 1 -100 1 -111 1 - -.names 47 227 228 178 -010 1 -001 1 -100 1 -111 1 - -.names 48 229 230 179 -010 1 -001 1 -100 1 -111 1 - -.names 49 231 232 180 -010 1 -001 1 -100 1 -111 1 - -.names 50 233 234 181 -010 1 -001 1 -100 1 -111 1 - -.names 51 235 236 182 -010 1 -001 1 -100 1 -111 1 - -.names 52 237 238 183 -010 1 -001 1 -100 1 -111 1 - -.names 53 239 240 184 -010 1 -001 1 -100 1 -111 1 - -.names 54 241 242 185 -010 1 -001 1 -100 1 -111 1 - -.names 55 243 244 186 -010 1 -001 1 -100 1 -111 1 - -.names 56 245 246 187 -010 1 -001 1 -100 1 -111 1 - -.names 57 247 248 188 -010 1 -001 1 -100 1 -111 1 - -.names 58 249 250 189 -010 1 -001 1 -100 1 -111 1 - -.names 59 251 252 190 -010 1 -001 1 -100 1 -111 1 - -.names 60 253 254 191 -010 1 -001 1 -100 1 -111 1 - -.names 61 255 256 192 -010 1 -001 1 -100 1 -111 1 - -.names 62 257 258 193 -010 1 -001 1 -100 1 -111 1 - -.names 63 259 260 194 -010 1 -001 1 -100 1 -111 1 - -.names 64 261 262 195 -010 1 -001 1 -100 1 -111 1 - -.names 65 263 264 196 -010 1 -001 1 -100 1 -111 1 - -.names 66 265 266 197 -010 1 -001 1 -100 1 -111 1 - -.names 2 268 198 -10 1 -01 1 - -.names 269 270 199 -11 1 - -.names 166 272 200 -11 1 - -.names 166 274 201 -11 1 - -.names 166 275 202 -11 1 - -.names 276 277 203 --1 1 -1- 1 - -.names 204 - -.names 205 - -.names 340 341 206 --1 1 -1- 1 - -.names 36 205 206 207 --11 1 -1-1 1 -11- 1 - -.names 338 339 208 --1 1 -1- 1 - -.names 37 207 208 209 --11 1 -1-1 1 -11- 1 - -.names 336 337 210 --1 1 -1- 1 - -.names 38 209 210 211 --11 1 -1-1 1 -11- 1 - -.names 334 335 212 --1 1 -1- 1 - -.names 39 211 212 213 --11 1 -1-1 1 -11- 1 - -.names 332 333 214 --1 1 -1- 1 - -.names 40 213 214 215 --11 1 -1-1 1 -11- 1 - -.names 330 331 216 --1 1 -1- 1 - -.names 41 215 216 217 --11 1 -1-1 1 -11- 1 - -.names 328 329 218 --1 1 -1- 1 - -.names 42 217 218 219 --11 1 -1-1 1 -11- 1 - -.names 326 327 220 --1 1 -1- 1 - -.names 43 219 220 221 --11 1 -1-1 1 -11- 1 - -.names 324 325 222 --1 1 -1- 1 - -.names 44 221 222 223 --11 1 -1-1 1 -11- 1 - -.names 322 323 224 --1 1 -1- 1 - -.names 45 223 224 225 --11 1 -1-1 1 -11- 1 - -.names 320 321 226 --1 1 -1- 1 - -.names 46 225 226 227 --11 1 -1-1 1 -11- 1 - -.names 318 319 228 --1 1 -1- 1 - -.names 47 227 228 229 --11 1 -1-1 1 -11- 1 - -.names 316 317 230 --1 1 -1- 1 - -.names 48 229 230 231 --11 1 -1-1 1 -11- 1 - -.names 314 315 232 --1 1 -1- 1 - -.names 49 231 232 233 --11 1 -1-1 1 -11- 1 - -.names 312 313 234 --1 1 -1- 1 - -.names 50 233 234 235 --11 1 -1-1 1 -11- 1 - -.names 310 311 236 --1 1 -1- 1 - -.names 51 235 236 237 --11 1 -1-1 1 -11- 1 - -.names 308 309 238 --1 1 -1- 1 - -.names 52 237 238 239 --11 1 -1-1 1 -11- 1 - -.names 306 307 240 --1 1 -1- 1 - -.names 53 239 240 241 --11 1 -1-1 1 -11- 1 - -.names 304 305 242 --1 1 -1- 1 - -.names 54 241 242 243 --11 1 -1-1 1 -11- 1 - -.names 302 303 244 --1 1 -1- 1 - -.names 55 243 244 245 --11 1 -1-1 1 -11- 1 - -.names 300 301 246 --1 1 -1- 1 - -.names 56 245 246 247 --11 1 -1-1 1 -11- 1 - -.names 298 299 248 --1 1 -1- 1 - -.names 57 247 248 249 --11 1 -1-1 1 -11- 1 - -.names 296 297 250 --1 1 -1- 1 - -.names 58 249 250 251 --11 1 -1-1 1 -11- 1 - -.names 294 295 252 --1 1 -1- 1 - -.names 59 251 252 253 --11 1 -1-1 1 -11- 1 - -.names 292 293 254 --1 1 -1- 1 - -.names 60 253 254 255 --11 1 -1-1 1 -11- 1 - -.names 290 291 256 --1 1 -1- 1 - -.names 61 255 256 257 --11 1 -1-1 1 -11- 1 - -.names 288 289 258 --1 1 -1- 1 - -.names 62 257 258 259 --11 1 -1-1 1 -11- 1 - -.names 286 287 260 --1 1 -1- 1 - -.names 63 259 260 261 --11 1 -1-1 1 -11- 1 - -.names 284 285 262 --1 1 -1- 1 - -.names 64 261 262 263 --11 1 -1-1 1 -11- 1 - -.names 282 283 264 --1 1 -1- 1 - -.names 65 263 264 265 --11 1 -1-1 1 -11- 1 - -.names 280 281 266 --1 1 -1- 1 - -.names 278 279 267 --1 1 -1- 1 - -.names 166 267 268 -01 1 -10 1 - -.names 2 267 269 -11 1 - -.names 166 270 -0 1 - -.names 267 271 -0 1 - -.names 2 271 272 -11 1 - -.names 2 273 -0 1 - -.names 267 273 274 -11 1 - -.names 2 267 275 -11 1 - -.names 199 200 276 --1 1 -1- 1 - -.names 201 202 277 --1 1 -1- 1 - -.names 203 67 -1 1 - -.names 167 68 -1 1 - -.names 168 69 -1 1 - -.names 169 70 -1 1 - -.names 170 71 -1 1 - -.names 171 72 -1 1 - -.names 172 73 -1 1 - -.names 173 74 -1 1 - -.names 174 75 -1 1 - -.names 175 76 -1 1 - -.names 176 77 -1 1 - -.names 177 78 -1 1 - -.names 178 79 -1 1 - -.names 179 80 -1 1 - -.names 180 81 -1 1 - -.names 181 82 -1 1 - -.names 182 83 -1 1 - -.names 183 84 -1 1 - -.names 184 85 -1 1 - -.names 185 86 -1 1 - -.names 186 87 -1 1 - -.names 187 88 -1 1 - -.names 188 89 -1 1 - -.names 189 90 -1 1 - -.names 190 91 -1 1 - -.names 191 92 -1 1 - -.names 192 93 -1 1 - -.names 193 94 -1 1 - -.names 194 95 -1 1 - -.names 195 96 -1 1 - -.names 196 97 -1 1 - -.names 197 98 -1 1 - -.names 198 99 -1 1 - -.names 100 133 278 -11 1 - -.names 101 165 279 -11 1 - -.names 100 132 280 -11 1 - -.names 101 164 281 -11 1 - -.names 100 131 282 -11 1 - -.names 101 163 283 -11 1 - -.names 100 130 284 -11 1 - -.names 101 162 285 -11 1 - -.names 100 129 286 -11 1 - -.names 101 161 287 -11 1 - -.names 100 128 288 -11 1 - -.names 101 160 289 -11 1 - -.names 100 127 290 -11 1 - -.names 101 159 291 -11 1 - -.names 100 126 292 -11 1 - -.names 101 158 293 -11 1 - -.names 100 125 294 -11 1 - -.names 101 157 295 -11 1 - -.names 100 124 296 -11 1 - -.names 101 156 297 -11 1 - -.names 100 123 298 -11 1 - -.names 101 155 299 -11 1 - -.names 100 122 300 -11 1 - -.names 101 154 301 -11 1 - -.names 100 121 302 -11 1 - -.names 101 153 303 -11 1 - -.names 100 120 304 -11 1 - -.names 101 152 305 -11 1 - -.names 100 119 306 -11 1 - -.names 101 151 307 -11 1 - -.names 100 118 308 -11 1 - -.names 101 150 309 -11 1 - -.names 100 117 310 -11 1 - -.names 101 149 311 -11 1 - -.names 100 116 312 -11 1 - -.names 101 148 313 -11 1 - -.names 100 115 314 -11 1 - -.names 101 147 315 -11 1 - -.names 100 114 316 -11 1 - -.names 101 146 317 -11 1 - -.names 100 113 318 -11 1 - -.names 101 145 319 -11 1 - -.names 100 112 320 -11 1 - -.names 101 144 321 -11 1 - -.names 100 111 322 -11 1 - -.names 101 143 323 -11 1 - -.names 100 110 324 -11 1 - -.names 101 142 325 -11 1 - -.names 100 109 326 -11 1 - -.names 101 141 327 -11 1 - -.names 100 108 328 -11 1 - -.names 101 140 329 -11 1 - -.names 100 107 330 -11 1 - -.names 101 139 331 -11 1 - -.names 100 106 332 -11 1 - -.names 101 138 333 -11 1 - -.names 100 105 334 -11 1 - -.names 101 137 335 -11 1 - -.names 100 104 336 -11 1 - -.names 101 136 337 -11 1 - -.names 100 103 338 -11 1 - -.names 101 135 339 -11 1 - -.names 100 102 340 -11 1 - -.names 101 134 341 -11 1 - -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/pci_conf_cyc_addr_dec.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/pci_conf_cyc_addr_dec.blif deleted file mode 100644 index a0588d70f..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/pci_conf_cyc_addr_dec.blif +++ /dev/null @@ -1,259 +0,0 @@ -# Benchmark "pci_conf_cyc_addr_dec" written by ABC on Mon Aug 29 15:33:11 2005 -.model pci_conf_cyc_addr_dec -.inputs ccyc_addr_in[0] ccyc_addr_in[1] ccyc_addr_in[2] ccyc_addr_in[3] \ - ccyc_addr_in[4] ccyc_addr_in[5] ccyc_addr_in[6] ccyc_addr_in[7] \ - ccyc_addr_in[8] ccyc_addr_in[9] ccyc_addr_in[10] ccyc_addr_in[11] \ - ccyc_addr_in[12] ccyc_addr_in[13] ccyc_addr_in[14] ccyc_addr_in[15] \ - ccyc_addr_in[16] ccyc_addr_in[17] ccyc_addr_in[18] ccyc_addr_in[19] \ - ccyc_addr_in[20] ccyc_addr_in[21] ccyc_addr_in[22] ccyc_addr_in[23] \ - ccyc_addr_in[24] ccyc_addr_in[25] ccyc_addr_in[26] ccyc_addr_in[27] \ - ccyc_addr_in[28] ccyc_addr_in[29] ccyc_addr_in[30] ccyc_addr_in[31] -.outputs ccyc_addr_out[0] ccyc_addr_out[1] ccyc_addr_out[2] \ - ccyc_addr_out[3] ccyc_addr_out[4] ccyc_addr_out[5] ccyc_addr_out[6] \ - ccyc_addr_out[7] ccyc_addr_out[8] ccyc_addr_out[9] ccyc_addr_out[10] \ - ccyc_addr_out[11] ccyc_addr_out[12] ccyc_addr_out[13] ccyc_addr_out[14] \ - ccyc_addr_out[15] ccyc_addr_out[16] ccyc_addr_out[17] ccyc_addr_out[18] \ - ccyc_addr_out[19] ccyc_addr_out[20] ccyc_addr_out[21] ccyc_addr_out[22] \ - ccyc_addr_out[23] ccyc_addr_out[24] ccyc_addr_out[25] ccyc_addr_out[26] \ - ccyc_addr_out[27] ccyc_addr_out[28] ccyc_addr_out[29] ccyc_addr_out[30] \ - ccyc_addr_out[31] -.names [64] - 0 -.names [65] - 1 -.names ccyc_addr_in[1] ccyc_addr_out[1] -1 1 -.names ccyc_addr_in[2] ccyc_addr_out[2] -1 1 -.names ccyc_addr_in[3] ccyc_addr_out[3] -1 1 -.names ccyc_addr_in[4] ccyc_addr_out[4] -1 1 -.names ccyc_addr_in[5] ccyc_addr_out[5] -1 1 -.names ccyc_addr_in[6] ccyc_addr_out[6] -1 1 -.names ccyc_addr_in[7] ccyc_addr_out[7] -1 1 -.names ccyc_addr_in[8] ccyc_addr_out[8] -1 1 -.names ccyc_addr_in[9] ccyc_addr_out[9] -1 1 -.names ccyc_addr_in[10] ccyc_addr_out[10] -1 1 -.names [126] [98] [115] ccyc_addr_out[30] -00- 1 ---0 1 -.names [147] [98] [151] ccyc_addr_out[29] -00- 1 ---0 1 -.names [131] [97] [123] ccyc_addr_out[28] -00- 1 ---0 1 -.names [120] [97] [116] ccyc_addr_out[27] -00- 1 ---0 1 -.names [105] ccyc_addr_out[0] [143] ccyc_addr_out[31] -00- 1 ---0 1 -.names [134] [99] [118] ccyc_addr_out[26] -00- 1 ---0 1 -.names [142] [99] [138] ccyc_addr_out[25] -00- 1 ---0 1 -.names [145] [104] [144] ccyc_addr_out[24] -00- 1 ---0 1 -.names [122] [104] [148] ccyc_addr_out[23] -00- 1 ---0 1 -.names [121] [106] [152] ccyc_addr_out[22] -00- 1 ---0 1 -.names [119] [106] [117] ccyc_addr_out[21] -00- 1 ---0 1 -.names [128] [107] [133] ccyc_addr_out[20] -00- 1 ---0 1 -.names [130] [107] [125] ccyc_addr_out[19] -00- 1 ---0 1 -.names [137] [102] [132] ccyc_addr_out[18] -00- 1 ---0 1 -.names [139] [102] [135] ccyc_addr_out[17] -00- 1 ---0 1 -.names [140] [100] [141] ccyc_addr_out[16] -00- 1 ---0 1 -.names [129] [100] [158] ccyc_addr_out[15] -00- 1 ---0 1 -.names [146] [101] [153] ccyc_addr_out[14] -00- 1 ---0 1 -.names [149] [101] [154] ccyc_addr_out[13] -00- 1 ---0 1 -.names [150] [103] [157] ccyc_addr_out[12] -00- 1 ---0 1 -.names [124] [103] [136] ccyc_addr_out[11] -00- 1 ---0 1 -.names [108] [168] [97] -11 0 -.names [109] ccyc_addr_in[12] [98] -11 0 -.names [111] ccyc_addr_in[12] [99] -11 0 -.names [112] [168] [100] -11 0 -.names [113] ccyc_addr_in[12] [101] -11 0 -.names [112] ccyc_addr_in[12] [102] -11 0 -.names [113] [168] [103] -11 0 -.names [111] [168] [104] -11 0 -.names [155] [127] ccyc_addr_in[13] [105] -111 0 -.names [114] ccyc_addr_in[12] [106] -11 0 -.names [114] [168] [107] -11 0 -.names [110] [108] -0 1 -.names [110] [109] -0 1 -.names [171] [165] [167] [110] -111 0 -.names [156] [167] [111] -00 1 -.names [159] [167] [112] -00 1 -.names [159] ccyc_addr_in[13] [113] -00 1 -.names [156] ccyc_addr_in[13] [114] -00 1 -.names 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a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/router.blif +++ /dev/null @@ -1,585 +0,0 @@ -.model top -.inputs dest_x[0] dest_x[1] dest_x[2] dest_x[3] dest_x[4] dest_x[5] \ - dest_x[6] dest_x[7] dest_x[8] dest_x[9] dest_x[10] dest_x[11] dest_x[12] \ - dest_x[13] dest_x[14] dest_x[15] dest_x[16] dest_x[17] dest_x[18] \ - dest_x[19] dest_x[20] dest_x[21] dest_x[22] dest_x[23] dest_x[24] \ - dest_x[25] dest_x[26] dest_x[27] dest_x[28] dest_x[29] dest_y[0] dest_y[1] \ - dest_y[2] dest_y[3] dest_y[4] dest_y[5] dest_y[6] dest_y[7] dest_y[8] \ - dest_y[9] dest_y[10] dest_y[11] dest_y[12] dest_y[13] dest_y[14] \ - dest_y[15] dest_y[16] dest_y[17] dest_y[18] dest_y[19] dest_y[20] \ - dest_y[21] dest_y[22] dest_y[23] dest_y[24] dest_y[25] dest_y[26] \ - dest_y[27] dest_y[28] dest_y[29] -.outputs outport[0] outport[1] outport[2] outport[3] outport[4] outport[5] \ - outport[6] outport[7] outport[8] outport[9] outport[10] outport[11] \ - outport[12] outport[13] outport[14] outport[15] outport[16] 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1 -.names n217 n240 n241 -00 1 -.names dest_y[11] n217 n242 -01 1 -.names n218 n242 n243 -00 1 -.names dest_y[12] n218 n244 -11 1 -.names n219 n244 n245 -00 1 -.names dest_y[13] n219 n246 -10 1 -.names n220 n246 n247 -00 1 -.names dest_y[14] n220 n248 -01 1 -.names n221 n248 n249 -00 1 -.names dest_y[15] n221 n250 -10 1 -.names dest_y[15] n221 n251 -01 1 -.names n250 n251 n252 -00 1 -.names dest_y[16] n222 n253 -11 1 -.names n223 n253 n254 -00 1 -.names dest_y[17] n223 n255 -01 1 -.names n224 n255 n256 -00 1 -.names dest_y[18] n224 n257 -11 1 -.names n225 n257 n258 -00 1 -.names dest_y[19] n225 n259 -01 1 -.names n226 n259 n260 -00 1 -.names dest_y[20] n226 n261 -10 1 -.names dest_y[20] n226 n262 -01 1 -.names n261 n262 n263 -00 1 -.names dest_y[21] n227 n264 -11 1 -.names n228 n264 n265 -00 1 -.names dest_y[22] n228 n266 -10 1 -.names n229 n266 n267 -00 1 -.names dest_y[23] n229 n268 -01 1 -.names n230 n268 n269 -00 1 -.names dest_y[24] n230 n270 -10 1 -.names dest_y[24] n230 n271 -01 1 -.names n270 n271 n272 -00 1 -.names dest_y[25] n231 n273 -10 1 -.names dest_y[25] n231 n274 -01 1 -.names n273 n274 n275 -00 1 -.names dest_y[26] n232 n276 -11 1 -.names n233 n276 n277 -00 1 -.names dest_y[27] n233 n278 -01 1 -.names n234 n278 n279 -00 1 -.names dest_y[28] n234 n280 -10 1 -.names dest_y[28] n234 n281 -01 1 -.names n280 n281 n282 -00 1 -.names dest_y[0] dest_y[9] n283 -10 1 -.names dest_y[29] n283 n284 -11 1 -.names n282 n284 n285 -01 1 -.names n279 n285 n286 -11 1 -.names n277 n286 n287 -01 1 -.names n275 n287 n288 -01 1 -.names n272 n288 n289 -01 1 -.names n269 n289 n290 -11 1 -.names n267 n290 n291 -01 1 -.names n265 n291 n292 -01 1 -.names n263 n292 n293 -01 1 -.names n260 n293 n294 -11 1 -.names n258 n294 n295 -01 1 -.names n256 n295 n296 -11 1 -.names n254 n296 n297 -01 1 -.names n252 n297 n298 -01 1 -.names n249 n298 n299 -11 1 -.names n247 n299 n300 -01 1 -.names n245 n300 n301 -01 1 -.names n243 n301 n302 -11 1 -.names n241 n302 n303 -01 1 -.names dest_y[8] n303 n304 -11 1 -.names dest_y[7] n304 n305 -11 1 -.names dest_y[6] n305 n306 -11 1 -.names dest_y[5] n306 n307 -11 1 -.names dest_y[4] n307 n308 -11 1 -.names dest_y[3] n308 n309 -11 1 -.names dest_y[2] n309 n310 -11 1 -.names dest_y[1] n310 n311 -11 1 -.names dest_y[1] dest_y[2] n312 -00 1 -.names dest_y[3] n312 n313 -01 1 -.names dest_y[4] n313 n314 -01 1 -.names dest_y[5] n314 n315 -01 1 -.names dest_y[6] n315 n316 -01 1 -.names dest_y[7] n316 n317 -01 1 -.names dest_y[8] n317 n318 -01 1 -.names n241 n318 n319 -11 1 -.names n243 n319 n320 -01 1 -.names n245 n320 n321 -11 1 -.names n247 n321 n322 -11 1 -.names n249 n322 n323 -01 1 -.names n252 n323 n324 -11 1 -.names n254 n324 n325 -11 1 -.names n256 n325 n326 -01 1 -.names n258 n326 n327 -11 1 -.names n260 n327 n328 -01 1 -.names n263 n328 n329 -11 1 -.names n265 n329 n330 -11 1 -.names n267 n330 n331 -11 1 -.names n269 n331 n332 -01 1 -.names n272 n332 n333 -11 1 -.names n275 n333 n334 -11 1 -.names n277 n334 n335 -11 1 -.names n279 n335 n336 -01 1 -.names n282 n336 n337 -11 1 -.names dest_y[9] n337 n338 -11 1 -.names n236 n338 n339 -10 1 -.names n311 n339 n340 -00 1 -.names n239 n340 n341 -01 1 -.names n187 n341 n342 -00 1 -.names n237 n342 n343 -01 1 -.names n215 n343 outport[1] -00 1 -.names dest_x[0] n236 n345 -11 1 -.names dest_y[0] n345 n346 -11 1 -.names n339 n346 n347 -00 1 -.names outport[0] n347 outport[2] -00 1 -.names outport[3] - 0 -.names outport[4] - 0 -.names outport[5] - 0 -.names outport[6] - 0 -.names outport[7] - 0 -.names outport[8] - 0 -.names outport[9] - 0 -.names outport[10] - 0 -.names outport[11] - 0 -.names outport[12] - 0 -.names outport[13] - 0 -.names outport[14] - 0 -.names outport[15] - 0 -.names outport[16] - 0 -.names outport[17] - 0 -.names outport[18] - 0 -.names outport[19] - 0 -.names outport[20] - 0 -.names outport[21] - 0 -.names outport[22] - 0 -.names outport[23] - 0 -.names outport[24] - 0 -.names outport[25] - 0 -.names outport[26] - 0 -.names outport[27] - 0 -.names outport[28] - 0 -.names outport[29] - 0 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/s1488.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/s1488.blif deleted file mode 100644 index c3dfdc8a5..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/s1488.blif +++ /dev/null @@ -1,796 +0,0 @@ -.model TOP -.inputs s1488_in_7_ s1488_in_6_ s1488_in_5_ s1488_in_4_ s1488_in_3_ \ -s1488_in_2_ s1488_in_1_ s1488_in_0_ clock -.outputs s1488_out_18_ s1488_out_17_ s1488_out_16_ s1488_out_15_ s1488_out_14_ \ -s1488_out_13_ s1488_out_12_ s1488_out_11_ s1488_out_10_ s1488_out_9_ \ -s1488_out_8_ s1488_out_7_ s1488_out_6_ s1488_out_5_ s1488_out_4_ s1488_out_3_ \ -s1488_out_2_ s1488_out_1_ s1488_out_0_ -.latch N_N33 N_N356 re clock 2 -.latch N_N34 N_N357 re clock 2 -.latch N_N35 N_N358 re clock 2 -.latch N_N36 N_N359 re clock 2 -.latch N_N37 N_N360 re clock 2 -.latch N_N38 N_N361 re clock 2 -.names s1488_in_3_ n1 n3 n244 s1488_out_18_ -1110 1 -.names n4 s1488_out_17_ -0 1 -.names n5 s1488_out_16_ -0 1 -.names n6 s1488_out_15_ -0 1 -.names n7 s1488_out_14_ -0 1 -.names n10 n8 N_N361 n173 s1488_out_13_ -1-0- 1 --100 1 -.names n30 s1488_out_12_ -0 1 -.names n12 s1488_out_11_ -0 1 -.names n39 s1488_out_10_ -0 1 -.names s1488_in_4_ n14 n173 n210 s1488_out_9_ -110- 1 -11-0 1 -.names n15 n16 n17 n18 s1488_out_8_ -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n40 n42 n192 n290 s1488_out_7_ -1--- 1 --1-- 1 ---0- 1 ----0 1 -.names n44 s1488_out_6_ -0 1 -.names n52 s1488_out_5_ -0 1 -.names n53 s1488_out_4_ -0 1 -.names n54 s1488_out_3_ -0 1 -.names n55 s1488_out_2_ -0 1 -.names n233 s1488_out_1_ -0 1 -.names n56 s1488_out_0_ -0 1 -.names n114 N_N360 n1 -10 1 -.names s1488_in_6_ s1488_in_1_ n3 -0- 1 --1 1 -.names n10 N_N361 n164 n165 n4 -0-11 1 --111 1 -.names n166 N_N360 n151 n5 -11- 1 -1-1 1 -.names n103 n114 n167 n187 n6 -0-0- 1 --00- 1 ---00 1 -.names s1488_in_6_ s1488_in_3_ n5 n172 n7 -1-1- 1 --01- 1 ---11 1 -.names n115 n210 n10 -10 1 -.names s1488_in_4_ s1488_in_5_ n8 -1- 1 --1 1 -.names n35 n179 n180 n187 n12 -111- 1 --110 1 -.names s1488_in_5_ N_N361 n14 -00 1 -.names N_N359 n116 n168 n226 n15 ---10 1 -101- 1 -.names n188 N_N360 n16 -11 1 -.names n206 n114 n17 -11 1 -.names s1488_in_0_ N_N359 n103 n187 n18 -1011 1 -.names n68 n76 n77 n107 n19 -111- 1 --110 1 -.names n19 N_N38 -0 1 -.names n91 n92 N_N356 n90 n20 -111- 1 -11-1 1 -.names n20 N_N37 -0 1 -.names n97 n110 n111 n122 n21 -111- 1 --110 1 -.names n21 N_N36 -0 1 -.names s1488_in_7_ N_N359 n119 n118 n22 -1-1- 1 -10-1 1 -.names n112 n122 n249 n262 n23 -11-- 1 --10- 1 --1-0 1 -.names n123 N_N359 n24 -11 1 -.names s1488_in_2_ n107 n116 n115 n26 --11- 1 -01-1 1 -.names n104 n113 n256 n27 -11- 1 -1-0 1 -.names n22 n23 n24 n26 n27 n90 N_N35 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------0 1 -.names n104 n131 n138 n278 n28 -001- 1 --010 1 -.names n28 N_N34 -0 1 -.names n122 n139 n161 n162 n29 -0-11 1 --111 1 -.names n29 N_N33 -0 1 -.names N_N361 n174 n31 -0- 1 --1 1 -.names N_N356 N_N360 n252 n305 n32 -0--1 1 --1-1 1 ---11 1 -.names n103 N_N360 n33 -0- 1 --0 1 -.names n221 n250 n34 -0- 1 --0 1 -.names s1488_in_0_ n119 n35 -0- 1 --0 1 -.names n31 n32 n33 n34 n35 N_N359 n118 n199 n30 -11111000 1 -.names N_N358 N_N359 n185 n186 n39 -0-11 1 --011 1 -.names n17 N_N360 n255 n40 -11- 1 --10 1 -.names n200 n199 n103 n42 -11- 1 -1-1 1 -.names N_N361 n199 n46 -1- 1 --0 1 -.names N_N356 n221 n47 -1- 1 --0 1 -.names n1 N_N358 n50 -0- 1 --0 1 -.names N_N361 n243 n51 -0- 1 --1 1 -.names n33 n46 n47 n50 n51 n203 n205 n309 n44 -11111000 1 -.names N_N358 n119 n214 n215 n52 -0-11 1 --011 1 -.names n70 N_N361 n115 n216 n217 n218 n53 -100111 1 -.names n184 n219 n220 n224 n54 -0-01 1 --101 1 -.names s1488_in_2_ n10 N_N361 n229 n55 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N358 n221 n250 n58 -1-- 1 --0- 1 ---0 1 -.names n1 n103 n238 n59 -0-0 1 --00 1 -.names N_N361 n115 n253 n60 -1-- 1 --0- 1 ---1 1 -.names N_N359 N_N360 n174 n61 -0-- 1 --0- 1 ---1 1 -.names n58 n59 n60 n61 n237 n312 n56 -111100 1 -.names s1488_in_3_ N_N358 N_N359 n63 -11- 1 --10 1 -.names s1488_in_6_ s1488_in_3_ s1488_in_2_ s1488_in_1_ n64 -11-1 1 -1-01 1 -.names N_N358 n103 n67 -01 1 -.names N_N359 n67 N_N361 n66 -11- 1 -1-0 1 -.names s1488_in_2_ N_N356 n70 -0- 1 --0 1 -.names s1488_in_2_ N_N358 n70 n103 n68 -1-10 1 --010 1 -.names s1488_in_7_ n66 n266 n268 n72 -11-- 1 -1-0- 1 -1--0 1 -.names N_N359 n104 n123 n206 n76 -0-0- 1 --00- 1 ---00 1 -.names n72 n122 n264 n265 n77 -00-- 1 -0-11 1 -.names s1488_in_7_ s1488_in_6_ N_N358 n82 -0-- 1 --1- 1 ---0 1 -.names s1488_in_1_ n82 n104 N_N357 n78 -01-- 1 --10- 1 --1-0 1 -.names N_N358 N_N356 n84 -0- 1 --0 1 -.names s1488_in_2_ N_N357 n115 n144 n85 --0-1 1 -0-11 1 -.names n84 n85 n103 n83 -110 1 -.names s1488_in_6_ n84 n88 -1- 1 --1 1 -.names s1488_in_2_ N_N356 n114 n89 -0-- 1 --1- 1 ---0 1 -.names n63 n88 n89 N_N357 n86 -011- 1 --110 1 -.names N_N361 n273 n274 n314 n91 -0--0 1 --110 1 -.names n83 n86 n107 n122 n92 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names s1488_in_7_ N_N359 N_N361 n90 -0-- 1 --0- 1 ---1 1 -.names s1488_in_3_ s1488_in_0_ n3 n93 -101 1 -.names s1488_in_2_ N_N358 n67 n226 n95 -0-1- 1 -01-0 1 -.names N_N361 n159 n243 n246 n100 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n95 N_N357 n245 n247 n101 -011- 1 -0-11 1 -.names s1488_in_6_ n132 n99 -0- 1 --0 1 -.names N_N356 n100 n101 n99 n97 -011- 1 --111 1 -.names s1488_in_7_ N_N360 n104 -10 1 -.names N_N356 N_N357 n103 -01 1 -.names s1488_in_2_ n104 n103 n244 n102 --1-0 1 -011- 1 -.names N_N361 n122 n107 -01 1 -.names s1488_in_2_ n103 n107 n116 n105 --11- 1 -1-10 1 -.names N_N359 n102 n67 s1488_in_7_ n108 -11-- 1 -1-11 1 -.names N_N361 n123 n301 n110 -1-1 1 --01 1 -.names N_N356 n90 n105 n108 n111 -0-00 1 --100 1 -.names s1488_in_2_ N_N361 n116 n112 -010 1 -.names N_N359 N_N361 n114 -01 1 -.names N_N358 N_N356 n114 N_N357 n113 --01- 1 -1-11 1 -.names N_N357 n174 n116 -1- 1 --1 1 -.names s1488_in_4_ s1488_in_5_ n115 -11 1 -.names n103 N_N361 n119 -10 1 -.names N_N358 N_N356 n118 -10 1 -.names s1488_in_7_ N_N360 n122 -11 1 -.names n199 n104 N_N356 n123 -111 1 -.names s1488_in_2_ N_N358 N_N359 N_N361 n124 -00-- 1 -0-1- 1 --0-0 1 ---10 1 -.names s1488_in_3_ s1488_in_0_ n3 n114 N_N357 n125 -0---- 1 --1--- 1 ---1-- 1 ----0- 1 -----0 1 -.names N_N359 n118 n198 n280 n128 -11-- 1 -1-0- 1 -1--0 1 -.names n199 N_N361 n132 -11 1 -.names s1488_in_2_ n122 n128 n132 n131 --11- 1 -01-1 1 -.names s1488_in_7_ n103 n124 n282 n133 --1-0 1 -110- 1 -.names N_N357 n133 n283 n285 n138 -10-- 1 --011 1 -.names s1488_in_3_ s1488_in_2_ n132 n241 n141 -10-- 1 --00- 1 -1--1 1 ---01 1 -.names n99 n114 n160 n307 n142 -10-0 1 -1-10 1 -.names N_N357 n141 n142 n206 n139 -111- 1 --110 1 -.names s1488_in_2_ N_N358 n144 -0- 1 --0 1 -.names s1488_in_6_ s1488_in_1_ N_N361 n144 n143 -0--- 1 --0-- 1 ---1- 1 ----1 1 -.names s1488_in_0_ n114 N_N356 n3 n146 -1111 1 -.names s1488_in_2_ n63 n114 n147 -00- 1 --00 1 -.names s1488_in_3_ N_N357 n143 n146 n148 -110- 1 -11-1 1 -.names N_N359 N_N361 n174 n252 n151 -1--- 1 --1-- 1 ---1- 1 ----0 1 -.names n103 n147 n199 n261 n153 -0-0- 1 --10- 1 -0--1 1 --1-1 1 -.names n60 n148 n151 n153 n150 -1011 1 -.names N_N359 n228 n157 -0- 1 --1 1 -.names s1488_in_0_ n103 n156 -1- 1 --0 1 -.names n51 n115 n157 n156 n154 -101- 1 -1-11 1 -.names s1488_in_2_ n115 n159 -00 1 -.names N_N356 N_N357 n160 -0- 1 --0 1 -.names n159 n160 N_N358 N_N357 n158 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names s1488_in_7_ n150 n161 -0- 1 --1 1 -.names n104 n107 n154 n158 n162 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names s1488_in_2_ n116 n221 n164 -0-- 1 --1- 1 ---0 1 -.names n33 N_N359 n144 n165 -1-- 1 --0- 1 ---1 1 -.names n103 n144 n200 n166 -0-- 1 --1- 1 ---0 1 -.names s1488_in_2_ N_N360 n168 -01 1 -.names N_N359 n118 n168 n263 n167 -1--0 1 -111- 1 -.names N_N356 n114 N_N360 n199 n172 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names n156 n187 n176 -1- 1 --0 1 -.names N_N358 N_N356 n174 -1- 1 --0 1 -.names n168 n176 n174 n173 -01- 1 --11 1 -.names s1488_in_6_ n172 n179 -0- 1 --1 1 -.names N_N361 n116 n200 n180 -0-- 1 --1- 1 ---0 1 -.names N_N361 N_N357 N_N360 n181 -1-0 1 --00 1 -.names s1488_in_5_ s1488_in_4_ n184 -0- 1 --1 1 -.names N_N358 N_N357 N_N360 n184 n183 -1-0- 1 --001 1 -.names N_N356 N_N360 n259 n306 n185 -1--0 1 --0-0 1 ---10 1 -.names N_N359 N_N361 n183 n288 n186 --1-1 1 -0-01 1 -.names N_N358 N_N360 n187 -00 1 -.names N_N359 n244 n188 -00 1 -.names N_N361 N_N360 n246 n315 n189 -10-0 1 --000 1 -.names s1488_in_2_ n226 n194 -0- 1 --1 1 -.names n84 n189 n194 n221 n192 -101- 1 --010 1 -.names N_N356 N_N359 n196 -1- 1 --1 1 -.names s1488_in_0_ N_N357 n115 n196 n195 -0-0- 1 --00- 1 -0--1 1 --0-1 1 -.names s1488_in_2_ n174 n198 -0- 1 --1 1 -.names N_N359 n198 n197 -0- 1 --1 1 -.names N_N359 N_N360 n200 -10 1 -.names N_N358 N_N357 n199 -10 1 -.names N_N360 N_N358 s1488_in_2_ n202 -11- 1 -1-1 1 -.names N_N357 n187 s1488_in_0_ n184 n203 -111- 1 -11-1 1 -.names N_N358 N_N356 n206 -00 1 -.names N_N359 n187 n206 n202 n205 -11-- 1 -1-1- 1 -1--1 1 -.names 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G40 G39 G38 G316 G320 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names G40 G280 G50 -00 1 -.names G328 G313 G39 G50 G52 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names G42 G41 G280 G137 -000 1 -.names G317 G137 G139 -1- 1 --1 1 -.names G42 G41 G280 G253 -000 1 -.names G317 G253 G255 -1- 1 --1 1 -.names G9 G8 G204 -0- 1 --0 1 -.names G228 G229 G205 -0- 1 --0 1 -.names G202 G203 G204 G205 G207 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names G141 G142 G143 G305 -000 1 -.names G39 G38 G305 G309 -1-- 1 --1- 1 ---1 1 -.names G41 G40 G318 G16 G57 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G132 G133 G134 G58 -0-- 1 --0- 1 ---0 1 -.names G267 G4 G57 G58 G62 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names G135 G136 G303 -0- 1 --0 1 -.names G328 G313 G39 G303 G307 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names G246 G247 G248 G81 -0-- 1 --0- 1 ---0 1 -.names G328 G313 G317 G81 G85 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names G195 G280 G177 -00 1 -.names G174 G175 G177 G67 -1-- 1 --1- 1 ---1 1 -.names G42 G41 G317 G65 -0-- 1 --0- 1 ---0 1 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----0 1 -.names G313 G40 G39 G280 G289 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G41 G40 G39 G280 G297 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G313 G40 G39 G280 G311 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G40 G39 G280 G16 G314 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G313 G40 G39 G280 G326 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G39 G38 G119 -00 1 -.names G281 G3 G323 G119 G301 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G317 G318 G280 G15 G44 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G41 G317 G318 G280 G54 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G318 G280 G281 G156 -0-- 1 --0- 1 ---0 1 -.names G318 G280 G15 G14 G299 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G182 G183 G179 -0- 1 --0 1 -.names G238 G239 G240 G241 G224 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G242 G243 G244 G40 G227 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G280 G267 G198 G131 -000 1 -.names G114 G115 G116 G317 G269 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G267 G123 G122 -00 1 -.names G318 G280 G16 G122 G46 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G180 G328 G317 G179 G69 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G318 G256 G138 -00 1 -.names G139 G138 G306 -0- 1 --0 1 -.names G318 G256 G254 -00 1 -.names G255 G254 G84 -0- 1 --0 1 -.names G127 G128 G129 G51 -000 1 -.names G3 G181 G1 G156 G146 -0000 1 -.names G328 G313 G317 G146 G61 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G231 G232 G233 G206 -000 1 -.names G210 G211 G77 -00 1 -.names G166 G167 G165 -00 1 -.names G199 G200 G192 -00 1 -.names G117 G118 G104 -00 1 -.names G120 G121 G324 -00 1 -.names G164 G165 G159 -00 1 -.names G191 G192 G186 -00 1 -.names G226 G227 G221 -00 1 -.names G268 G269 G261 -00 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/sasc.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/sasc.blif deleted file mode 100644 index 5c44ee382..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/sasc.blif +++ /dev/null @@ -1,1446 +0,0 @@ -# Benchmark "sasc" written by ABC on Mon Aug 29 15:33:11 2005 -.model sasc -.inputs clk rst rxd_i cts_i sio_ce sio_ce_x4 re_i we_i din_i[0] din_i[1] \ - din_i[2] din_i[3] din_i[4] din_i[5] din_i[6] din_i[7] -.outputs txd_o rts_o full_o empty_o dout_o[0] dout_o[1] dout_o[2] dout_o[3] \ - dout_o[4] dout_o[5] dout_o[6] dout_o[7] - -.latch rx_fifo_gb_reg_in rx_fifo_gb_reg 2 -.latch \rx_fifo_wp_reg[0]_in \rx_fifo_wp_reg[0] 0 -.latch \rx_fifo_mem_reg[1][6]_in \rx_fifo_mem_reg[1][6] 2 -.latch \rx_fifo_mem_reg[1][7]_in \rx_fifo_mem_reg[1][7] 2 -.latch \rx_fifo_mem_reg[2][0]_in \rx_fifo_mem_reg[2][0] 2 -.latch \rx_fifo_mem_reg[2][1]_in \rx_fifo_mem_reg[2][1] 2 -.latch \rx_fifo_mem_reg[2][2]_in \rx_fifo_mem_reg[2][2] 2 -.latch \rx_fifo_mem_reg[2][3]_in \rx_fifo_mem_reg[2][3] 2 -.latch \rx_fifo_mem_reg[2][4]_in \rx_fifo_mem_reg[2][4] 2 -.latch \rx_fifo_mem_reg[2][5]_in \rx_fifo_mem_reg[2][5] 2 -.latch \rx_fifo_mem_reg[2][6]_in \rx_fifo_mem_reg[2][6] 2 -.latch \rx_fifo_mem_reg[2][7]_in \rx_fifo_mem_reg[2][7] 2 -.latch \rx_fifo_mem_reg[1][0]_in \rx_fifo_mem_reg[1][0] 2 -.latch \rx_fifo_mem_reg[1][1]_in \rx_fifo_mem_reg[1][1] 2 -.latch \rx_fifo_mem_reg[1][2]_in \rx_fifo_mem_reg[1][2] 2 -.latch \rx_fifo_mem_reg[1][3]_in \rx_fifo_mem_reg[1][3] 2 -.latch \rx_fifo_mem_reg[1][4]_in \rx_fifo_mem_reg[1][4] 2 -.latch \rx_fifo_mem_reg[1][5]_in \rx_fifo_mem_reg[1][5] 2 -.latch \rx_fifo_mem_reg[3][0]_in \rx_fifo_mem_reg[3][0] 2 -.latch \rx_fifo_mem_reg[3][1]_in \rx_fifo_mem_reg[3][1] 2 -.latch \rx_fifo_mem_reg[3][2]_in \rx_fifo_mem_reg[3][2] 2 -.latch \rx_fifo_mem_reg[3][3]_in \rx_fifo_mem_reg[3][3] 2 -.latch \rx_fifo_mem_reg[3][4]_in \rx_fifo_mem_reg[3][4] 2 -.latch \rx_fifo_mem_reg[3][5]_in \rx_fifo_mem_reg[3][5] 2 -.latch \rx_fifo_mem_reg[3][6]_in \rx_fifo_mem_reg[3][6] 2 -.latch \rx_fifo_mem_reg[3][7]_in \rx_fifo_mem_reg[3][7] 2 -.latch \rx_fifo_mem_reg[0][0]_in \rx_fifo_mem_reg[0][0] 2 -.latch \rx_fifo_mem_reg[0][1]_in \rx_fifo_mem_reg[0][1] 2 -.latch \rx_fifo_mem_reg[0][2]_in \rx_fifo_mem_reg[0][2] 2 -.latch \rx_fifo_mem_reg[0][3]_in \rx_fifo_mem_reg[0][3] 2 -.latch \rx_fifo_mem_reg[0][4]_in \rx_fifo_mem_reg[0][4] 2 -.latch \rx_fifo_mem_reg[0][5]_in \rx_fifo_mem_reg[0][5] 2 -.latch \rx_fifo_mem_reg[0][6]_in \rx_fifo_mem_reg[0][6] 2 -.latch \rx_fifo_mem_reg[0][7]_in \rx_fifo_mem_reg[0][7] 2 -.latch \rx_bit_cnt_reg[1]_in \rx_bit_cnt_reg[1] 2 -.latch \rx_fifo_wp_reg[1]_in \rx_fifo_wp_reg[1] 0 -.latch \rx_bit_cnt_reg[3]_in \rx_bit_cnt_reg[3] 2 -.latch \rx_bit_cnt_reg[0]_in \rx_bit_cnt_reg[0] 2 -.latch \rx_bit_cnt_reg[2]_in \rx_bit_cnt_reg[2] 2 -.latch \rxr_reg[3]_in \rxr_reg[3] 2 -.latch \rxr_reg[9]_in \rxr_reg[9] 2 -.latch \rxr_reg[2]_in \rxr_reg[2] 2 -.latch \rxr_reg[4]_in \rxr_reg[4] 2 -.latch \rxr_reg[5]_in \rxr_reg[5] 2 -.latch \rxr_reg[6]_in \rxr_reg[6] 2 -.latch \rxr_reg[8]_in \rxr_reg[8] 2 -.latch \rxr_reg[7]_in \rxr_reg[7] 2 -.latch \tx_bit_cnt_reg[3]_in \tx_bit_cnt_reg[3] 2 -.latch tx_fifo_gb_reg_in tx_fifo_gb_reg 2 -.latch \hold_reg_reg[6]_in \hold_reg_reg[6] 2 -.latch \hold_reg_reg[7]_in \hold_reg_reg[7] 2 -.latch \hold_reg_reg[8]_in \hold_reg_reg[8] 2 -.latch \hold_reg_reg[1]_in \hold_reg_reg[1] 2 -.latch \hold_reg_reg[2]_in \hold_reg_reg[2] 2 -.latch \hold_reg_reg[3]_in \hold_reg_reg[3] 2 -.latch \hold_reg_reg[4]_in \hold_reg_reg[4] 2 -.latch \tx_bit_cnt_reg[2]_in \tx_bit_cnt_reg[2] 2 -.latch \hold_reg_reg[5]_in \hold_reg_reg[5] 2 -.latch txf_empty_r_reg_in txf_empty_r_reg 2 -.latch \tx_fifo_mem_reg[2][1]_in \tx_fifo_mem_reg[2][1] 2 -.latch \dpll_state_reg[0]_in \dpll_state_reg[0] 1 -.latch rts_o_reg_in rts_o_reg 2 -.latch \tx_bit_cnt_reg[0]_in \tx_bit_cnt_reg[0] 2 -.latch \tx_fifo_mem_reg[1][0]_in \tx_fifo_mem_reg[1][0] 2 -.latch \tx_fifo_mem_reg[1][1]_in \tx_fifo_mem_reg[1][1] 2 -.latch \tx_fifo_mem_reg[1][2]_in \tx_fifo_mem_reg[1][2] 2 -.latch \tx_fifo_mem_reg[1][3]_in \tx_fifo_mem_reg[1][3] 2 -.latch \tx_fifo_mem_reg[1][4]_in \tx_fifo_mem_reg[1][4] 2 -.latch \tx_fifo_mem_reg[1][6]_in \tx_fifo_mem_reg[1][6] 2 -.latch \tx_fifo_mem_reg[1][7]_in \tx_fifo_mem_reg[1][7] 2 -.latch \tx_fifo_mem_reg[2][0]_in \tx_fifo_mem_reg[2][0] 2 -.latch \tx_fifo_mem_reg[2][2]_in \tx_fifo_mem_reg[2][2] 2 -.latch \tx_fifo_mem_reg[2][3]_in \tx_fifo_mem_reg[2][3] 2 -.latch \tx_fifo_mem_reg[2][4]_in \tx_fifo_mem_reg[2][4] 2 -.latch \tx_fifo_mem_reg[2][6]_in \tx_fifo_mem_reg[2][6] 2 -.latch \tx_fifo_mem_reg[2][7]_in \tx_fifo_mem_reg[2][7] 2 -.latch txd_o_reg_in txd_o_reg 2 -.latch \tx_fifo_rp_reg[1]_in \tx_fifo_rp_reg[1] 0 -.latch \hold_reg_reg[0]_in \hold_reg_reg[0] 2 -.latch \tx_fifo_mem_reg[1][5]_in \tx_fifo_mem_reg[1][5] 2 -.latch \tx_fifo_mem_reg[2][5]_in \tx_fifo_mem_reg[2][5] 2 -.latch \tx_fifo_mem_reg[3][1]_in \tx_fifo_mem_reg[3][1] 2 -.latch \tx_fifo_mem_reg[3][6]_in \tx_fifo_mem_reg[3][6] 2 -.latch rx_valid_r_reg_in rx_valid_r_reg 2 -.latch \tx_fifo_mem_reg[3][5]_in \tx_fifo_mem_reg[3][5] 2 -.latch change_reg_in change_reg 2 -.latch \tx_fifo_mem_reg[0][0]_in \tx_fifo_mem_reg[0][0] 2 -.latch \tx_fifo_mem_reg[0][3]_in \tx_fifo_mem_reg[0][3] 2 -.latch \tx_fifo_mem_reg[0][4]_in \tx_fifo_mem_reg[0][4] 2 -.latch \tx_fifo_mem_reg[0][7]_in \tx_fifo_mem_reg[0][7] 2 -.latch \tx_fifo_mem_reg[0][2]_in \tx_fifo_mem_reg[0][2] 2 -.latch \tx_fifo_mem_reg[3][0]_in \tx_fifo_mem_reg[3][0] 2 -.latch \tx_fifo_mem_reg[3][2]_in \tx_fifo_mem_reg[3][2] 2 -.latch \tx_fifo_mem_reg[3][3]_in \tx_fifo_mem_reg[3][3] 2 -.latch \tx_fifo_mem_reg[3][4]_in \tx_fifo_mem_reg[3][4] 2 -.latch \tx_fifo_mem_reg[3][7]_in \tx_fifo_mem_reg[3][7] 2 -.latch \rx_fifo_rp_reg[1]_in \rx_fifo_rp_reg[1] 0 -.latch \hold_reg_reg[9]_in \hold_reg_reg[9] 2 -.latch \tx_fifo_mem_reg[0][6]_in \tx_fifo_mem_reg[0][6] 2 -.latch \tx_fifo_mem_reg[0][5]_in \tx_fifo_mem_reg[0][5] 2 -.latch \tx_fifo_mem_reg[0][1]_in \tx_fifo_mem_reg[0][1] 2 -.latch \tx_bit_cnt_reg[1]_in \tx_bit_cnt_reg[1] 2 -.latch rx_sio_ce_reg_in rx_sio_ce_reg 2 -.latch shift_en_r_reg_in shift_en_r_reg 2 -.latch \tx_fifo_wp_reg[1]_in \tx_fifo_wp_reg[1] 0 -.latch \dpll_state_reg[1]_in \dpll_state_reg[1] 0 -.latch rx_valid_reg_in rx_valid_reg 2 -.latch \rx_fifo_rp_reg[0]_in \rx_fifo_rp_reg[0] 0 -.latch rx_go_reg_in rx_go_reg 2 -.latch \tx_fifo_rp_reg[0]_in \tx_fifo_rp_reg[0] 0 -.latch load_reg_in load_reg 2 -.latch rx_sio_ce_r2_reg_in rx_sio_ce_r2_reg 2 -.latch \tx_fifo_wp_reg[0]_in \tx_fifo_wp_reg[0] 0 -.latch shift_en_reg_in shift_en_reg 2 -.latch rx_sio_ce_r1_reg_in rx_sio_ce_r1_reg 2 -.latch rxd_r_reg_in rxd_r_reg 2 -.latch rxd_s_reg_in rxd_s_reg 2 - -.names [145] - 0 -.names [146] - 1 -.names rx_fifo_gb_reg [147] -1 1 -.names \rx_fifo_wp_reg[0] [148] -1 1 -.names \rx_fifo_mem_reg[1][6] [149] -1 1 -.names \rx_fifo_mem_reg[1][7] [150] -1 1 -.names \rx_fifo_mem_reg[2][0] [151] -1 1 -.names \rx_fifo_mem_reg[2][1] [152] -1 1 -.names \rx_fifo_mem_reg[2][2] [153] -1 1 -.names \rx_fifo_mem_reg[2][3] [154] -1 1 -.names \rx_fifo_mem_reg[2][4] [155] -1 1 -.names \rx_fifo_mem_reg[2][5] [156] -1 1 -.names \rx_fifo_mem_reg[2][6] [157] -1 1 -.names \rx_fifo_mem_reg[2][7] [158] -1 1 -.names \rx_fifo_mem_reg[1][0] [159] -1 1 -.names \rx_fifo_mem_reg[1][1] [160] -1 1 -.names \rx_fifo_mem_reg[1][2] [161] -1 1 -.names \rx_fifo_mem_reg[1][3] [162] -1 1 -.names \rx_fifo_mem_reg[1][4] [163] -1 1 -.names \rx_fifo_mem_reg[1][5] [164] -1 1 -.names \rx_fifo_mem_reg[3][0] [165] -1 1 -.names \rx_fifo_mem_reg[3][1] [166] -1 1 -.names \rx_fifo_mem_reg[3][2] [167] -1 1 -.names \rx_fifo_mem_reg[3][3] [168] -1 1 -.names \rx_fifo_mem_reg[3][4] [169] -1 1 -.names \rx_fifo_mem_reg[3][5] [170] -1 1 -.names \rx_fifo_mem_reg[3][6] [171] -1 1 -.names \rx_fifo_mem_reg[3][7] [172] -1 1 -.names \rx_fifo_mem_reg[0][0] [173] -1 1 -.names \rx_fifo_mem_reg[0][1] [174] -1 1 -.names \rx_fifo_mem_reg[0][2] [175] -1 1 -.names \rx_fifo_mem_reg[0][3] [176] -1 1 -.names \rx_fifo_mem_reg[0][4] [177] -1 1 -.names \rx_fifo_mem_reg[0][5] [178] -1 1 -.names \rx_fifo_mem_reg[0][6] [179] -1 1 -.names \rx_fifo_mem_reg[0][7] [180] -1 1 -.names [230] [607] [648] rx_fifo_gb_reg_in -11- 0 ---1 0 -.names \rx_bit_cnt_reg[1] [182] -1 1 -.names \rx_fifo_wp_reg[1] [183] -1 1 -.names \rx_bit_cnt_reg[3] [184] -1 1 -.names [672] [625] [232] \rx_fifo_wp_reg[0]_in -00- 1 ---0 1 -.names [414] [150] [242] \rx_fifo_mem_reg[1][7]_in -01- 1 -1-1 1 -.names [352] [151] [242] \rx_fifo_mem_reg[2][0]_in -01- 1 -1-1 1 -.names [353] [152] [245] \rx_fifo_mem_reg[2][1]_in -01- 1 -1-1 1 -.names [413] [149] [244] \rx_fifo_mem_reg[1][6]_in -01- 1 -1-1 1 -.names \rx_bit_cnt_reg[0] [190] -1 1 -.names \rx_bit_cnt_reg[2] [191] -1 1 -.names [355] [154] [243] \rx_fifo_mem_reg[2][3]_in -01- 1 -1-1 1 -.names [354] [153] [245] \rx_fifo_mem_reg[2][2]_in -01- 1 -1-1 1 -.names [356] [155] [242] \rx_fifo_mem_reg[2][4]_in -01- 1 -1-1 1 -.names [357] [156] [243] \rx_fifo_mem_reg[2][5]_in -01- 1 -1-1 1 -.names [358] [157] [245] \rx_fifo_mem_reg[2][6]_in -01- 1 -1-1 1 -.names [359] [158] [244] \rx_fifo_mem_reg[2][7]_in -01- 1 -1-1 1 -.names [417] [160] [242] \rx_fifo_mem_reg[1][1]_in -01- 1 -1-1 1 -.names [415] [159] [245] \rx_fifo_mem_reg[1][0]_in -01- 1 -1-1 1 -.names [416] [161] [242] \rx_fifo_mem_reg[1][2]_in -01- 1 -1-1 1 -.names [418] [162] [243] \rx_fifo_mem_reg[1][3]_in -01- 1 -1-1 1 -.names [419] [163] [242] \rx_fifo_mem_reg[1][4]_in -01- 1 -1-1 1 -.names [420] [164] [244] \rx_fifo_mem_reg[1][5]_in -01- 1 -1-1 1 -.names [360] [165] [244] \rx_fifo_mem_reg[3][0]_in -01- 1 -1-1 1 -.names [361] [166] [245] \rx_fifo_mem_reg[3][1]_in -01- 1 -1-1 1 -.names [362] [167] [243] \rx_fifo_mem_reg[3][2]_in -01- 1 -1-1 1 -.names [363] [168] [244] \rx_fifo_mem_reg[3][3]_in -01- 1 -1-1 1 -.names [364] [169] [244] \rx_fifo_mem_reg[3][4]_in -01- 1 -1-1 1 -.names [366] [170] [243] \rx_fifo_mem_reg[3][5]_in -01- 1 -1-1 1 -.names [367] [171] [245] \rx_fifo_mem_reg[3][6]_in -01- 1 -1-1 1 -.names [368] [172] [245] \rx_fifo_mem_reg[3][7]_in -01- 1 -1-1 1 -.names [373] [173] [244] \rx_fifo_mem_reg[0][0]_in -01- 1 -1-1 1 -.names [369] [174] [243] \rx_fifo_mem_reg[0][1]_in -01- 1 -1-1 1 -.names [374] [175] [245] \rx_fifo_mem_reg[0][2]_in -01- 1 -1-1 1 -.names [375] [176] [244] \rx_fifo_mem_reg[0][3]_in -01- 1 -1-1 1 -.names [378] [177] [242] \rx_fifo_mem_reg[0][4]_in -01- 1 -1-1 1 -.names [376] [178] [242] \rx_fifo_mem_reg[0][5]_in -01- 1 -1-1 1 -.names [372] [179] [243] \rx_fifo_mem_reg[0][6]_in -01- 1 -1-1 1 -.names [377] [180] [243] \rx_fifo_mem_reg[0][7]_in -01- 1 -1-1 1 -.names \rxr_reg[3] [220] -1 1 -.names \rxr_reg[9] [221] -1 1 -.names \rxr_reg[2] [222] -1 1 -.names \rxr_reg[4] [223] -1 1 -.names \rxr_reg[5] [224] -1 1 -.names \rxr_reg[6] [225] -1 1 -.names \rxr_reg[8] [226] -1 1 -.names \rxr_reg[7] [227] -1 1 -.names [543] [246] rst \rx_bit_cnt_reg[1]_in -00- 1 ---0 1 -.names [251] [543] rst \rx_bit_cnt_reg[3]_in -00- 1 ---0 1 -.names [322] [247] [500] [230] -111 0 -.names [253] [467] \rx_bit_cnt_reg[0]_in -00 1 -.names [672] [625] [232] -11 0 -.names [252] [467] \rx_bit_cnt_reg[2]_in -00 1 -.names rxd_r_reg_in [221] [280] \rxr_reg[9]_in -01- 1 -1-1 1 -.names [220] [222] [280] \rxr_reg[2]_in -01- 1 -1-1 1 -.names [223] [220] [280] \rxr_reg[3]_in -01- 1 -1-1 1 -.names [224] [223] [280] \rxr_reg[4]_in -01- 1 -1-1 1 -.names [225] [224] [280] \rxr_reg[5]_in -01- 1 -1-1 1 -.names [227] [225] [280] \rxr_reg[6]_in -01- 1 -1-1 1 -.names [226] [227] [280] \rxr_reg[7]_in -01- 1 -1-1 1 -.names [221] [226] [280] \rxr_reg[8]_in -01- 1 -1-1 1 -.names [247] [242] -0 1 -.names [248] [243] -0 1 -.names [249] [244] -0 1 -.names [250] [245] -0 1 -.names [575] [270] [182] [280] [246] -11-- 0 ---11 0 -.names [673] [247] -0 1 -.names [673] [248] -0 1 -.names [673] [249] -0 1 -.names [673] [250] -0 1 -.names [184] [280] [267] [251] -11- 0 ---1 0 -.names [191] [280] [263] [252] -11- 0 ---1 0 -.names [629] [280] [262] [253] -11- 0 ---1 0 -.names \tx_bit_cnt_reg[3] [254] -1 1 -.names tx_fifo_gb_reg [255] -0 1 -.names \hold_reg_reg[6] [256] -0 1 -.names \hold_reg_reg[7] [257] -0 1 -.names \hold_reg_reg[8] [258] -0 1 -.names \hold_reg_reg[1] [259] -0 1 -.names \hold_reg_reg[2] [260] -0 1 -.names \hold_reg_reg[3] [261] -0 1 -.names [629] [280] [262] -00 1 -.names [501] [280] [263] -00 1 -.names \hold_reg_reg[4] [264] -0 1 -.names \tx_bit_cnt_reg[2] [265] -1 1 -.names \hold_reg_reg[5] [266] -0 1 -.names [453] [280] [267] -00 1 -.names txf_empty_r_reg [268] -0 1 -.names [329] [598] rst \tx_bit_cnt_reg[3]_in -00- 1 ---0 1 -.names [280] [270] -0 1 -.names [327] [591] \tx_bit_cnt_reg[2]_in -00 1 -.names [513] [383] [598] \hold_reg_reg[6]_in -01- 1 -1-1 1 -.names [511] [382] [598] \hold_reg_reg[5]_in -01- 1 -1-1 1 -.names [514] [384] [598] \hold_reg_reg[7]_in -01- 1 -1-1 1 -.names [516] [385] [598] \hold_reg_reg[8]_in -01- 1 -1-1 1 -.names [521] [386] [598] \hold_reg_reg[1]_in -01- 1 -1-1 1 -.names [517] [387] [632] \hold_reg_reg[2]_in -01- 1 -1-1 1 -.names [515] [388] [632] \hold_reg_reg[3]_in -01- 1 -1-1 1 -.names [533] [389] [632] \hold_reg_reg[4]_in -01- 1 -1-1 1 -.names [433] [328] [280] -11 0 -.names [572] [371] [648] tx_fifo_gb_reg_in -11- 0 ---1 0 -.names \tx_fifo_mem_reg[2][1] [282] -1 1 -.names \dpll_state_reg[0] [283] -1 1 -.names rts_o_reg rts_o -1 1 -.names \tx_bit_cnt_reg[0] [285] -1 1 -.names \tx_fifo_mem_reg[1][0] [286] -1 1 -.names \tx_fifo_mem_reg[1][1] [287] -1 1 -.names \tx_fifo_mem_reg[1][2] [288] -1 1 -.names \tx_fifo_mem_reg[1][3] [289] -1 1 -.names \tx_fifo_mem_reg[1][4] [290] -1 1 -.names \tx_fifo_mem_reg[1][6] [291] -1 1 -.names \tx_fifo_mem_reg[1][7] [292] -1 1 -.names \tx_fifo_mem_reg[2][0] [293] -1 1 -.names \tx_fifo_mem_reg[2][2] [294] -1 1 -.names \tx_fifo_mem_reg[2][3] [295] -1 1 -.names \tx_fifo_mem_reg[2][4] [296] -1 1 -.names \tx_fifo_mem_reg[2][6] [297] -1 1 -.names \tx_fifo_mem_reg[2][7] [298] -1 1 -.names txd_o_reg txd_o -1 1 -.names \tx_fifo_rp_reg[1] [300] -1 1 -.names \hold_reg_reg[0] [301] -1 1 -.names \tx_fifo_mem_reg[1][5] [302] -1 1 -.names \tx_fifo_mem_reg[2][5] [303] -1 1 -.names [381] rst txf_empty_r_reg_in -11 0 -.names \tx_fifo_mem_reg[3][1] [305] -1 1 -.names \tx_fifo_mem_reg[3][6] [306] -1 1 -.names rx_valid_r_reg [307] -0 1 -.names \tx_fifo_mem_reg[3][5] [308] -1 1 -.names change_reg [309] -1 1 -.names \tx_fifo_mem_reg[0][0] [310] -1 1 -.names \tx_fifo_mem_reg[0][3] [311] -1 1 -.names \tx_fifo_mem_reg[0][4] [312] -1 1 -.names \tx_fifo_mem_reg[0][7] [313] -1 1 -.names \tx_fifo_mem_reg[0][2] [314] -1 1 -.names \tx_fifo_mem_reg[3][0] [315] -1 1 -.names \tx_fifo_mem_reg[3][2] [316] -1 1 -.names \tx_fifo_mem_reg[3][3] [317] -1 1 -.names \tx_fifo_mem_reg[3][4] [318] -1 1 -.names \tx_fifo_mem_reg[3][7] [319] -1 1 -.names \rx_fifo_rp_reg[1] [320] -1 1 -.names \hold_reg_reg[9] [321] -1 1 -.names [671] [631] [412] [322] -00- 1 ---0 1 -.names \tx_fifo_mem_reg[0][6] [323] -1 1 -.names \tx_fifo_mem_reg[0][5] [324] -1 1 -.names \tx_fifo_mem_reg[0][1] [325] -1 1 -.names \tx_bit_cnt_reg[1] [326] -1 1 -.names [265] [595] [423] [327] -11- 0 ---1 0 -.names rx_sio_ce_reg [328] -1 1 -.names [583] [254] [405] [329] -11- 0 ---1 0 -.names [291] [478] we_i \tx_fifo_mem_reg[1][6]_in -01- 1 -1-1 1 -.names [292] [479] we_i \tx_fifo_mem_reg[1][7]_in -01- 1 -1-1 1 -.names [293] [480] we_i \tx_fifo_mem_reg[2][0]_in -01- 1 -1-1 1 -.names [282] [486] we_i \tx_fifo_mem_reg[2][1]_in -01- 1 -1-1 1 -.names [294] [481] we_i \tx_fifo_mem_reg[2][2]_in -01- 1 -1-1 1 -.names [295] [482] we_i \tx_fifo_mem_reg[2][3]_in -01- 1 -1-1 1 -.names [296] [483] we_i \tx_fifo_mem_reg[2][4]_in -01- 1 -1-1 1 -.names [303] [471] we_i \tx_fifo_mem_reg[2][5]_in -01- 1 -1-1 1 -.names [297] [484] we_i \tx_fifo_mem_reg[2][6]_in -01- 1 -1-1 1 -.names [298] [485] we_i \tx_fifo_mem_reg[2][7]_in -01- 1 -1-1 1 -.names [445] [448] dout_o[4] -11 0 -.names [446] [447] dout_o[0] -11 0 -.names shift_en_r_reg [342] -1 1 -.names [444] [449] dout_o[6] -11 0 -.names [687] [499] [632] \tx_fifo_rp_reg[1]_in -01- 1 -1-1 1 -.names [495] [490] [598] \hold_reg_reg[0]_in -11- 0 ---1 0 -.names [443] [450] dout_o[7] -11 0 -.names [439] [440] dout_o[5] -11 0 -.names [437] [451] dout_o[3] -11 0 -.names [436] [438] dout_o[2] -11 0 -.names [441] [442] dout_o[1] -11 0 -.names [452] [626] empty_o -00 1 -.names [222] [151] [502] [352] -01- 1 -1-1 1 -.names [220] [152] [502] [353] -01- 1 -1-1 1 -.names [223] [153] [502] [354] -01- 1 -1-1 1 -.names [224] [154] [502] [355] -01- 1 -1-1 1 -.names [225] [155] [502] [356] -01- 1 -1-1 1 -.names [227] [156] [502] [357] -01- 1 -1-1 1 -.names [226] [157] [502] [358] -01- 1 -1-1 1 -.names [221] [158] [502] [359] -01- 1 -1-1 1 -.names [222] [165] [689] [360] -01- 1 -1-1 1 -.names [220] [166] [689] [361] -01- 1 -1-1 1 -.names [223] [167] [689] [362] -01- 1 -1-1 1 -.names [224] [168] [689] [363] -01- 1 -1-1 1 -.names [225] [169] [689] [364] -01- 1 -1-1 1 -.names [573] [590] [457] \dpll_state_reg[0]_in -111 0 -.names [227] [170] [689] [366] -01- 1 -1-1 1 -.names [226] [171] [689] [367] -01- 1 -1-1 1 -.names [221] [172] [689] [368] -01- 1 -1-1 1 -.names [174] [220] [504] [369] -01- 1 -1-1 1 -.names [678] rts_o_reg_in -0 1 -.names [458] [555] we_i [371] -111 0 -.names [179] [226] [504] [372] -01- 1 -1-1 1 -.names [173] [222] [504] [373] -01- 1 -1-1 1 -.names [175] [223] [504] [374] -01- 1 -1-1 1 -.names [176] [224] [504] [375] -01- 1 -1-1 1 -.names [178] [227] [504] [376] -01- 1 -1-1 1 -.names [180] [221] [504] [377] -01- 1 -1-1 1 -.names [177] [225] [504] [378] -01- 1 -1-1 1 -.names [434] rst txd_o_reg_in -11 0 -.names [487] [632] rst \tx_bit_cnt_reg[0]_in -00- 1 ---0 1 -.names [617] [461] [639] [655] [381] -11-- 0 ---11 0 -.names [544] [535] [462] [382] -111 0 -.names [567] [548] [464] [383] -111 0 -.names [561] [498] [465] [384] -111 0 -.names [549] [494] [466] [385] -111 0 -.names [570] [537] [468] [386] -111 0 -.names [571] [536] [469] [387] -111 0 -.names [569] [493] [470] [388] -111 0 -.names [547] [496] [463] [389] -111 0 -.names [286] [472] we_i \tx_fifo_mem_reg[1][0]_in -01- 1 -1-1 1 -.names [287] [473] we_i \tx_fifo_mem_reg[1][1]_in -01- 1 -1-1 1 -.names [288] [474] we_i \tx_fifo_mem_reg[1][2]_in -01- 1 -1-1 1 -.names [289] [476] we_i \tx_fifo_mem_reg[1][3]_in -01- 1 -1-1 1 -.names [290] [477] we_i \tx_fifo_mem_reg[1][4]_in -01- 1 -1-1 1 -.names [302] [475] we_i \tx_fifo_mem_reg[1][5]_in -01- 1 -1-1 1 -.names [315] [529] we_i \tx_fifo_mem_reg[3][0]_in -01- 1 -1-1 1 -.names [305] [530] we_i \tx_fifo_mem_reg[3][1]_in -01- 1 -1-1 1 -.names [316] [512] we_i \tx_fifo_mem_reg[3][2]_in -01- 1 -1-1 1 -.names [319] [534] we_i \tx_fifo_mem_reg[3][7]_in -01- 1 -1-1 1 -.names [317] [531] we_i \tx_fifo_mem_reg[3][3]_in -01- 1 -1-1 1 -.names [318] [520] we_i \tx_fifo_mem_reg[3][4]_in -01- 1 -1-1 1 -.names [308] [532] we_i \tx_fifo_mem_reg[3][5]_in -01- 1 -1-1 1 -.names [563] [460] rx_sio_ce_reg_in -00 1 -.names [306] [522] we_i \tx_fifo_mem_reg[3][6]_in -01- 1 -1-1 1 -.names [489] [583] [405] -00 1 -.names \tx_fifo_wp_reg[1] [406] -1 1 -.names \dpll_state_reg[1] [407] -1 1 -.names [461] [653] full_o -11 1 -.names [631] [538] re_i \rx_fifo_rp_reg[1]_in -01- 1 -1-1 1 -.names rx_valid_reg rx_valid_r_reg_in -1 1 -.names [497] [321] \hold_reg_reg[9]_in -00 0 -.names [631] [671] [412] -11 0 -.names [226] [149] [540] [413] -01- 1 -1-1 1 -.names [221] [150] [540] [414] -01- 1 -1-1 1 -.names [222] [159] [540] [415] -01- 1 -1-1 1 -.names [223] [161] [540] [416] -01- 1 -1-1 1 -.names [220] [160] [540] [417] -01- 1 -1-1 1 -.names [224] [162] [540] [418] -01- 1 -1-1 1 -.names [225] [163] [540] [419] -01- 1 -1-1 1 -.names [227] [164] [540] [420] -01- 1 -1-1 1 -.names [491] [591] \tx_bit_cnt_reg[1]_in -00 1 -.names [508] [648] [589] change_reg_in -00- 1 ---0 1 -.names [488] [595] [423] -00 1 -.names [310] [523] we_i \tx_fifo_mem_reg[0][0]_in -01- 1 -1-1 1 -.names [325] [528] we_i \tx_fifo_mem_reg[0][1]_in -01- 1 -1-1 1 -.names [314] [524] we_i \tx_fifo_mem_reg[0][2]_in -01- 1 -1-1 1 -.names [311] [525] we_i \tx_fifo_mem_reg[0][3]_in -01- 1 -1-1 1 -.names [312] [526] we_i \tx_fifo_mem_reg[0][4]_in -01- 1 -1-1 1 -.names [324] [519] we_i \tx_fifo_mem_reg[0][5]_in -01- 1 -1-1 1 -.names [323] [527] we_i \tx_fifo_mem_reg[0][6]_in -01- 1 -1-1 1 -.names [313] [518] we_i \tx_fifo_mem_reg[0][7]_in -01- 1 -1-1 1 -.names \rx_fifo_rp_reg[0] [432] -1 1 -.names rx_go_reg [433] -1 1 -.names [551] sio_ce [639] txd_o [434] -11-- 0 ---11 0 -.names [610] [596] [648] shift_en_r_reg_in -11- 0 ---1 0 -.names [153] [559] [167] [581] [436] -11-- 0 ---11 0 -.names [154] [559] [168] [581] [437] -11-- 0 ---11 0 -.names [161] [557] [175] [582] [438] -11-- 0 ---11 0 -.names [156] [559] [170] [581] [439] -11-- 0 ---11 0 -.names [164] [557] [178] [582] [440] -11-- 0 ---11 0 -.names [152] [559] [166] [581] [441] -11-- 0 ---11 0 -.names [160] [557] [174] [582] [442] -11-- 0 ---11 0 -.names [557] [150] [582] [180] [443] -11-- 0 ---11 0 -.names [149] [557] [179] [582] [444] -11-- 0 ---11 0 -.names [155] [559] [169] [581] [445] -11-- 0 ---11 0 -.names [151] [559] [165] [581] [446] -11-- 0 ---11 0 -.names [159] [557] [173] [582] [447] -11-- 0 ---11 0 -.names [163] [557] [177] [582] [448] -11-- 0 ---11 0 -.names [157] [559] [171] [581] [449] -11-- 0 ---11 0 -.names [559] [158] [581] [172] [450] -11-- 0 ---11 0 -.names [162] [557] [176] [582] [451] -11-- 0 ---11 0 -.names [657] [452] -0 1 -.names [184] [565] [453] -01 1 -10 1 -.names \tx_fifo_rp_reg[0] [454] -1 1 -.names load_reg [455] -1 1 -.names [554] [615] [573] \dpll_state_reg[1]_in -111 0 -.names [627] [613] [309] [576] [457] -11-- 0 ---11 0 -.names [688] [564] [458] -01 1 -10 1 -.names [662] [564] we_i \tx_fifo_wp_reg[1]_in -01- 1 -1-1 1 -.names rx_sio_ce_r2_reg [460] -1 1 -.names [556] [555] [461] -00 1 -.names [619] [312] [296] [578] [462] -11-- 0 ---11 0 -.names [619] [311] [289] [694] [463] -11-- 0 ---11 0 -.names [302] [694] [303] [578] [464] -11-- 0 ---11 0 -.names [601] [306] [291] [694] [465] -11-- 0 ---11 0 -.names [619] [313] [292] [694] [466] -11-- 0 ---11 0 -.names [543] [648] [467] -00 0 -.names [601] [315] [293] [578] [468] -11-- 0 ---11 0 -.names [601] [305] [282] [578] [469] -11-- 0 ---11 0 -.names [601] [316] [288] [694] [470] -11-- 0 ---11 0 -.names din_i[5] [303] [579] [471] -01- 1 -1-1 1 -.names din_i[0] [286] [695] [472] -01- 1 -1-1 1 -.names din_i[1] [287] [695] [473] -01- 1 -1-1 1 -.names din_i[2] [288] [695] [474] -01- 1 -1-1 1 -.names din_i[5] [302] [695] [475] -01- 1 -1-1 1 -.names din_i[3] [289] [695] [476] -01- 1 -1-1 1 -.names din_i[4] [290] [695] [477] -01- 1 -1-1 1 -.names din_i[6] [291] [695] [478] -01- 1 -1-1 1 -.names din_i[7] [292] [695] [479] -01- 1 -1-1 1 -.names din_i[0] [293] [579] [480] -01- 1 -1-1 1 -.names din_i[2] [294] [618] [481] -01- 1 -1-1 1 -.names din_i[3] [295] [618] [482] -01- 1 -1-1 1 -.names din_i[4] [296] [579] [483] -01- 1 -1-1 1 -.names din_i[6] [297] [618] [484] -01- 1 -1-1 1 -.names din_i[7] [298] [579] [485] -01- 1 -1-1 1 -.names din_i[1] [282] [618] [486] -01- 1 -1-1 1 -.names [285] [596] [552] [487] -11- 0 ---1 0 -.names [585] [265] [553] [488] -11- 0 ---1 0 -.names [254] [568] [489] -01 1 -10 1 -.names [259] [596] [490] -00 0 -.names [326] [595] [541] [491] -11- 0 ---1 0 -.names [599] [560] rx_valid_reg_in -00 1 -.names [294] [578] [493] -11 0 -.names [298] [578] [494] -11 0 -.names [596] [301] [495] -11 0 -.names [295] [578] [496] -11 0 -.names [596] [612] [497] -11 0 -.names [297] [578] [498] -11 0 -.names [694] [578] [499] -00 0 -.names [692] [603] [500] -01 1 -10 1 -.names [588] [191] [542] [501] -11- 0 ---1 0 -.names [507] [502] -0 1 -.names [625] [682] [503] -11 0 -.names [505] [504] -0 1 -.names [603] [685] [505] -11 0 -.names \tx_fifo_wp_reg[0] [506] -1 1 -.names [679] [507] -0 1 -.names rxd_r_reg_in [587] [508] -01 1 -10 1 -.names [644] [182] [184] [643] rx_go_reg_in -1111 0 -.names shift_en_reg [510] -1 1 -.names [646] [637] [583] [511] -01- 1 -1-1 1 -.names din_i[2] [316] [661] [512] -01- 1 -1-1 1 -.names [635] [646] [595] [513] -01- 1 -1-1 1 -.names [649] [635] [595] [514] -01- 1 -1-1 1 -.names [641] [640] [595] [515] -01- 1 -1-1 1 -.names [321] [649] [595] [516] -01- 1 -1-1 1 -.names [640] [642] [583] [517] -01- 1 -1-1 1 -.names [313] din_i[7] [600] [518] -01- 1 -1-1 1 -.names [324] din_i[5] [600] [519] -01- 1 -1-1 1 -.names din_i[4] [318] [661] [520] -01- 1 -1-1 1 -.names [642] [634] [583] [521] -01- 1 -1-1 1 -.names din_i[6] [306] [661] [522] -01- 1 -1-1 1 -.names [310] din_i[0] [600] [523] -01- 1 -1-1 1 -.names [314] din_i[2] [600] [524] -01- 1 -1-1 1 -.names [311] din_i[3] [600] [525] -01- 1 -1-1 1 -.names [312] din_i[4] [600] [526] -01- 1 -1-1 1 -.names [323] din_i[6] [600] [527] -01- 1 -1-1 1 -.names [325] din_i[1] [600] [528] -01- 1 -1-1 1 -.names din_i[0] [315] [661] [529] -01- 1 -1-1 1 -.names din_i[1] [305] [661] [530] -01- 1 -1-1 1 -.names din_i[3] [317] [661] [531] -01- 1 -1-1 1 -.names din_i[5] [308] [661] [532] -01- 1 -1-1 1 -.names [637] [641] [583] [533] -01- 1 -1-1 1 -.names din_i[7] [319] [661] [534] -01- 1 -1-1 1 -.names [290] [694] [535] -11 0 -.names [287] [694] [536] -11 0 -.names [286] [694] [537] -11 0 -.names [577] [562] [538] -00 0 -.names re_i [691] \rx_fifo_rp_reg[0]_in -01 1 -10 1 -.names [558] [540] -0 1 -.names [616] [614] [595] [541] -11- 0 ---1 0 -.names [588] [191] [542] -00 1 -.names [602] [587] [543] -00 1 -.names [601] [318] [544] -11 0 -.names [628] [632] \tx_fifo_rp_reg[0]_in -01 1 -10 1 -.names [563] rx_sio_ce_r2_reg_in -0 1 -.names [601] [317] [547] -11 0 -.names [601] [308] [548] -11 0 -.names [601] [319] [549] -11 0 -.names [594] cts_i load_reg_in -00 1 -.names [593] [301] [551] -00 0 -.names [285] [596] [552] -00 1 -.names [585] [265] [553] -00 1 -.names [576] [554] -0 1 -.names [628] [630] [597] [555] -11- 0 ---1 0 -.names [662] [687] [556] -01 1 -10 1 -.names [562] [557] -1 1 -.names [566] [558] -0 1 -.names [577] [559] -1 1 -.names [629] [184] [560] -11 0 -.names [619] [323] [561] -11 0 -.names [692] [631] [562] -00 1 -.names rx_sio_ce_r1_reg [563] -0 1 -.names [609] [618] [564] -11 0 -.names [611] [191] [565] -11 0 -.names [625] [685] [566] -11 0 -.names [619] [324] [567] -11 0 -.names [621] [265] [568] -11 0 -.names [619] [314] [569] -11 0 -.names [619] [310] [570] -11 0 -.names [619] [325] [571] -11 0 -.names [612] [653] [572] -11 0 -.names [613] [407] [652] [573] -111 0 -.names [630] we_i \tx_fifo_wp_reg[0]_in -01 1 -10 1 -.names [629] [182] [575] -01 1 -10 1 -.names sio_ce_x4 rx_sio_ce_r1_reg_in [576] -11 1 -.names [691] [665] [577] -00 1 -.names [592] [578] -0 1 -.names [586] [579] -0 1 -.names [604] [616] shift_en_reg_in -00 0 -.names [692] [665] [581] -00 1 -.names [692] [665] [582] -11 1 -.names [620] [583] -0 1 -.names [454] [688] [584] -11 0 -.names [621] [585] -0 1 -.names [618] [586] -0 1 -.names rxd_r_reg [587] -0 1 -.names [611] [588] -0 1 -.names [309] [647] rst [589] -111 0 -.names [647] [283] [590] -11 0 -.names [632] [648] [591] -00 0 -.names [650] [300] [592] -11 0 -.names [510] [342] [593] -00 1 -.names [510] [655] [594] -00 0 -.names [620] [595] -0 1 -.names [620] [596] -0 1 -.names [628] [630] [597] -00 1 -.names [612] [598] -0 1 -.names [191] [182] [599] -00 0 -.names [608] [600] -0 1 -.names [622] [601] -0 1 -.names rxd_r_reg_in [433] [602] -00 0 -.names [625] [603] -0 1 -.names [656] [254] [604] -11 0 -.names [407] [652] rx_sio_ce_r1_reg_in -00 1 -.names [651] [693] [606] -00 0 -.names re_i [645] [607] -00 0 -.names [664] [663] [608] -11 0 -.names [506] [663] [609] -11 0 -.names [342] [639] [610] -11 0 -.names [643] [636] [611] -00 1 -.names [632] [612] -0 1 -.names [309] [647] [613] -00 1 -.names [633] [326] [614] -11 0 -.names [647] [407] [615] -11 0 -.names [633] [326] [616] -00 0 -.names [639] [653] [617] -00 1 -.names [664] [406] [618] -11 0 -.names [650] [688] [619] -11 1 -.names [654] [639] [620] -00 1 -.names [633] [638] [621] -00 1 -.names [650] [688] [622] -00 0 -.names [680] [693] [623] -11 0 -.names rxd_s_reg rxd_r_reg_in -1 1 -.names [680] [625] -0 1 -.names [645] [626] -0 1 -.names [407] [283] [627] -00 1 -.names [650] [628] -0 1 -.names [643] [629] -0 1 -.names [664] [630] -0 1 -.names [665] [631] -0 1 -.names [455] sio_ce [632] -11 1 -.names [285] [633] -0 1 -.names [259] [634] -0 1 -.names [257] [635] -0 1 -.names [182] [636] -0 1 -.names [266] [637] -0 1 -.names [326] [638] -0 1 -.names sio_ce [639] -0 1 -.names [261] [640] -0 1 -.names [264] [641] -0 1 -.names [260] [642] -0 1 -.names [190] [643] -0 1 -.names [191] [644] -0 1 -.names [147] [645] -0 1 -.names [256] [646] -0 1 -.names sio_ce_x4 [647] -0 1 -.names rst [648] -0 1 -.names [258] [649] -0 1 -.names [454] [650] -0 1 -.names [148] [651] -0 1 -.names [283] [652] -0 1 -.names [255] [653] -0 1 -.names [510] [654] -0 1 -.names [268] [655] -0 1 -.names [265] [656] -0 1 -.names [659] [658] [657] -00 1 -.names [676] [658] -0 1 -.names [660] [666] [659] -11 0 -.names [683] [665] [660] -11 0 -.names [662] [630] [661] -11 0 -.names [663] [662] -0 1 -.names [406] [663] -0 1 -.names [506] [664] -0 1 -.names [320] [665] -0 1 -.names [684] [320] [666] -11 0 -.names [681] [320] [147] [667] -111 0 -.names [669] [686] [147] [668] -111 0 -.names [320] [669] -0 1 -.names [671] [683] [672] \rx_fifo_wp_reg[1]_in -01- 1 -1-1 1 -.names [679] [566] [671] -11 0 -.names [678] [677] [672] -11 0 -.names [674] [677] [673] -11 0 -.names [675] [676] [674] -11 0 -.names [668] [667] [675] -11 0 -.names [606] [623] [676] -11 0 -.names [307] rx_valid_r_reg_in [677] -11 1 -.names [674] [678] -1 1 -.names [682] [680] [679] -11 0 -.names [148] [680] -0 1 -.names [686] [681] -0 1 -.names [685] [682] -0 1 -.names [684] [683] -0 1 -.names [685] [684] -1 1 -.names [686] [685] -1 1 -.names [183] [686] -0 1 -.names [688] [687] -0 1 -.names [300] [688] -0 1 -.names [690] [689] -0 1 -.names [503] [690] -0 1 -.names [692] [691] -0 1 -.names [693] [692] -1 1 -.names [432] [693] -0 1 -.names [584] [694] -0 1 -.names [609] [695] -1 1 -.names rxd_i rxd_s_reg_in -1 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/scf.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/scf.blif deleted file mode 100644 index 3e75ec395..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/scf.blif +++ /dev/null @@ -1,1187 +0,0 @@ -.model TOP -.inputs scf_in_26_ scf_in_25_ scf_in_24_ scf_in_23_ scf_in_22_ scf_in_21_ \ -scf_in_20_ scf_in_19_ scf_in_18_ scf_in_17_ scf_in_16_ scf_in_15_ scf_in_14_ \ -scf_in_13_ scf_in_12_ scf_in_11_ scf_in_10_ scf_in_9_ scf_in_8_ scf_in_7_ \ -scf_in_6_ scf_in_5_ scf_in_4_ scf_in_3_ scf_in_2_ scf_in_1_ scf_in_0_ clock -.outputs scf_out_55_ scf_out_54_ scf_out_53_ scf_out_52_ scf_out_51_ \ -scf_out_50_ scf_out_49_ scf_out_48_ scf_out_47_ scf_out_46_ scf_out_45_ \ -scf_out_44_ scf_out_43_ scf_out_42_ scf_out_41_ scf_out_40_ scf_out_39_ \ -scf_out_38_ scf_out_37_ scf_out_36_ scf_out_35_ scf_out_34_ scf_out_33_ \ -scf_out_32_ scf_out_31_ scf_out_30_ scf_out_29_ scf_out_28_ scf_out_27_ \ -scf_out_26_ scf_out_25_ scf_out_24_ scf_out_23_ scf_out_22_ scf_out_21_ \ -scf_out_20_ scf_out_19_ scf_out_18_ scf_out_17_ scf_out_16_ scf_out_15_ \ -scf_out_14_ scf_out_13_ scf_out_12_ scf_out_11_ scf_out_10_ scf_out_9_ \ -scf_out_8_ scf_out_7_ scf_out_6_ scf_out_5_ scf_out_4_ scf_out_3_ scf_out_2_ \ -scf_out_1_ scf_out_0_ -.latch N_N89 N_N575 re clock 2 -.latch N_N90 N_N576 re clock 2 -.latch N_N91 [36] re clock 2 -.latch N_N92 scf_out_13_ re clock 2 -.latch N_N93 N_N579 re clock 2 -.latch N_N94 N_N580 re clock 2 -.latch N_N95 N_N581 re clock 2 -.names n182 n348 scf_out_55_ -01 1 -.names n417 scf_out_54_ -0 1 -.names n22 scf_out_53_ -0 1 -.names n23 scf_out_5_ scf_out_52_ -1- 1 --1 1 -.names n179 n183 n387 scf_out_51_ -00- 1 -0-0 1 -.names n27 scf_out_50_ -0 1 -.names n32 scf_out_49_ -0 1 -.names n33 scf_out_48_ -0 1 -.names scf_out_0_ n327 scf_out_47_ -00 1 -.names n40 scf_out_46_ -0 1 -.names n58 scf_out_45_ -0 1 -.names n61 scf_out_44_ -0 1 -.names n43 scf_out_43_ -0 1 -.names n85 scf_out_42_ -0 1 -.names scf_out_41_ -.names n46 scf_out_40_ -0 1 -.names n50 scf_out_39_ -0 1 -.names n123 scf_out_38_ -0 1 -.names n315 scf_out_37_ -0 1 -.names scf_out_36_ -.names n55 scf_out_35_ -0 1 -.names n58 scf_out_34_ -0 1 -.names n59 scf_out_33_ -0 1 -.names n60 scf_out_32_ -0 1 -.names n123 n327 scf_out_31_ -00 1 -.names N_N576 scf_out_30_ -0 1 -.names n61 scf_out_29_ -0 1 -.names n62 scf_out_28_ -0 1 -.names n417 scf_out_26_ -0 1 -.names n48 scf_out_25_ -0 1 -.names n64 scf_out_24_ -0 1 -.names scf_out_55_ n41 n409 scf_out_23_ -1-- 1 --0- 1 ---0 1 -.names n66 scf_out_22_ -0 1 -.names n19 scf_out_21_ -0 1 -.names n41 scf_out_20_ -0 1 -.names n67 scf_out_19_ -0 1 -.names n68 scf_out_18_ -0 1 -.names n69 scf_out_17_ -0 1 -.names n70 scf_out_16_ -0 1 -.names n41 scf_out_15_ -0 1 -.names scf_out_31_ n59 n324 scf_out_14_ -1-- 1 --0- 1 ---0 1 -.names n30 n309 n330 scf_out_12_ -0-- 1 --0- 1 ---0 1 -.names n75 scf_out_11_ -0 1 -.names n139 scf_out_10_ -0 1 -.names n355 scf_out_9_ -0 1 -.names n151 scf_out_7_ -0 1 -.names scf_out_3_ n44 n330 scf_out_6_ -1-- 1 --0- 1 ---0 1 -.names n298 n338 scf_out_5_ -01 1 -.names N_N576 scf_out_4_ -0 1 -.names n30 n417 scf_out_3_ -0- 1 --0 1 -.names N_N579 [36] scf_out_2_ -1- 1 --1 1 -.names n104 scf_out_1_ -0 1 -.names [36] N_N579 scf_out_0_ -1- 1 --0 1 -.names n150 n123 n20 -1- 1 --1 1 -.names N_N576 n339 n21 -0- 1 --1 1 -.names n20 n21 n19 -1- 1 --1 1 -.names n57 n296 n297 n22 -11- 1 -1-1 1 -.names n148 n348 n23 -01 1 -.names n128 n304 n28 -1- 1 --0 1 -.names n298 n193 n29 -1- 1 --1 1 -.names n175 n234 n30 -1- 1 --1 1 -.names scf_out_0_ n175 n182 n31 -1-- 1 --1- 1 ---1 1 -.names n28 n29 n30 n31 n27 -1111 1 -.names n300 n301 n182 n299 n32 -111- 1 -11-1 1 -.names n305 n149 n35 -1- 1 --1 1 -.names n298 n217 n36 -1- 1 --1 1 -.names N_N580 n150 n102 n37 -1-- 1 --1- 1 ---1 1 -.names scf_out_2_ n175 n251 n38 -1-- 1 --1- 1 ---1 1 -.names scf_out_0_ n148 n320 n39 -1-- 1 --1- 1 ---1 1 -.names n35 n36 n37 n38 n39 n302 n33 -111110 1 -.names n297 n325 n41 -1- 1 --1 1 -.names n306 n307 n21 n298 n42 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n41 n42 n40 -11 1 -.names n128 n350 n44 -1- 1 --1 1 -.names n254 n150 n45 -1- 1 --1 1 -.names n44 n45 n43 -11 1 -.names scf_out_2_ n179 n222 n47 -1-- 1 --1- 1 ---1 1 -.names n23 n56 n57 n48 -011 1 -.names n335 n320 n49 -1- 1 --1 1 -.names n47 n42 n48 n49 n46 -1111 1 -.names n298 n195 n51 -1- 1 --1 1 -.names n28 n148 n299 n52 -11- 1 -1-1 1 -.names n41 N_N580 n217 n296 n54 -10-- 1 -1-0- 1 -1--1 1 -.names n51 n52 n54 n312 n50 -1110 1 -.names scf_out_0_ n151 n320 n56 -1-- 1 --1- 1 ---1 1 -.names n222 n304 n57 -1- 1 --0 1 -.names n56 n57 n44 n55 -111 1 -.names n60 n195 n298 n58 -11- 1 -1-1 1 -.names n39 n57 n151 n348 n59 -111- 1 -11-0 1 -.names n308 n251 n20 n60 -11- 1 -1-1 1 -.names n309 n296 n127 n61 -11- 1 -1-1 1 -.names n57 n254 n320 n62 -11- 1 -1-1 1 -.names scf_out_0_ n321 n296 n21 n64 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n322 n323 scf_out_0_ n321 n66 -111- 1 -11-1 1 -.names n324 n298 n297 n67 -11- 1 -1-1 1 -.names n326 n38 n127 n325 n68 -111- 1 -11-1 1 -.names n328 n329 scf_out_2_ n327 n69 -111- 1 -11-1 1 -.names n250 n324 n348 n70 -11- 1 --10 1 -.names [36] scf_out_13_ N_N581 n251 n75 --0-1 1 -1-01 1 -.names n116 n117 n118 n119 n31 n45 n120 n121 n78 -11111111 1 -.names n78 N_N95 -0 1 -.names n184 n185 n181 n175 n79 -111- 1 -11-1 1 -.names n79 N_N93 -0 1 -.names scf_in_26_ n231 n240 n241 n80 -0-11 1 --111 1 -.names n80 N_N91 -0 1 -.names N_N581 n264 n386 n388 n81 -11-- 1 -1-0- 1 -1--0 1 -.names scf_in_26_ n81 n351 n396 N_N90 -11-- 1 -1-0- 1 -1--0 1 -.names n195 n294 n295 n304 n84 -111- 1 --110 1 -.names n84 N_N89 -0 1 -.names n310 n311 n296 n250 n85 -111- 1 -11-1 1 -.names N_N575 N_N579 n89 -1- 1 --1 1 -.names scf_in_24_ [36] n89 n333 n86 -0-10 1 --010 1 -.names [36] scf_out_2_ n341 n91 -11- 1 --10 1 -.names N_N575 n333 n410 n95 -1-1 1 --01 1 -.names scf_out_13_ n86 n91 n96 -11- 1 -0-1 1 --11 1 -.names N_N576 n95 n96 n263 n93 -111- 1 --110 1 -.names scf_in_17_ scf_in_16_ n161 n97 -0-0 1 --00 1 -.names scf_out_13_ n123 n102 -1- 1 --1 1 -.names N_N581 n102 N_N576 [36] n101 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n101 N_N575 n331 n105 -10- 1 -1-1 1 --11 1 -.names scf_out_13_ n93 N_N581 n356 n106 -01-- 1 -0-0- 1 --1-0 1 ---00 1 -.names N_N581 N_N576 n104 -1- 1 --1 1 -.names n105 n106 scf_out_0_ n104 n103 -111- 1 -11-1 1 -.names scf_in_25_ n127 n144 n320 n107 --0-0 1 -100- 1 -.names n193 n144 N_N576 n150 n115 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names scf_in_26_ N_N575 n112 -0- 1 --0 1 -.names scf_out_13_ n104 n113 -1- 1 --1 1 -.names n107 n115 n112 n113 n111 -011- 1 -01-1 1 -.names scf_in_26_ n103 N_N580 n116 -0-- 1 --1- 1 ---1 1 -.names N_N576 n175 n253 n117 -1-- 1 --1- 1 ---1 1 -.names n144 n335 n118 -1- 1 --1 1 -.names n296 n127 n111 n123 n119 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n112 n104 scf_in_9_ n143 n120 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names scf_in_0_ n306 n331 n359 n121 -0--1 1 --1-1 1 ---11 1 -.names scf_in_11_ scf_out_0_ n124 -1- 1 --1 1 -.names [36] N_N579 n123 -0- 1 --1 1 -.names scf_in_24_ n124 N_N580 n123 n122 -01-- 1 --11- 1 --1-1 1 -.names N_N580 n127 n128 -0- 1 --1 1 -.names scf_out_13_ N_N576 n127 -1- 1 --0 1 -.names n128 n127 n198 n125 -11- 1 -1-0 1 -.names N_N576 n122 n333 n130 -11- 1 -0-0 1 --10 1 -.names N_N579 n217 n341 n360 n131 -0--1 1 --1-1 1 ---01 1 -.names [36] n125 n130 n131 n129 -0-11 1 --111 1 -.names scf_out_0_ n104 n128 n339 n132 -0-0- 1 -00-0 1 -.names [36] n132 N_N575 n182 n135 --11- 1 -1-10 1 -.names scf_in_11_ n21 n333 n140 -1-- 1 --1- 1 ---0 1 -.names N_N579 N_N580 n138 -0- 1 --0 1 -.names [36] scf_out_13_ N_N581 n139 -0-- 1 --0- 1 ---1 1 -.names n135 n140 n138 n139 n137 -011- 1 -01-1 1 -.names scf_out_13_ scf_out_2_ n179 n145 -0-- 1 --1- 1 ---1 1 -.names N_N580 n306 n333 n146 -1-- 1 --1- 1 ---0 1 -.names N_N579 N_N580 n143 -1- 1 --0 1 -.names scf_in_26_ N_N581 n144 -0- 1 --1 1 -.names n145 n146 n143 n144 n142 -111- 1 -11-1 1 -.names scf_out_13_ n193 n148 -0- 1 --1 1 -.names scf_in_26_ N_N575 n149 -0- 1 --1 1 -.names N_N575 n175 n150 -1- 1 --1 1 -.names N_N576 N_N580 n151 -1- 1 --0 1 -.names n148 n149 n150 n151 n147 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n123 n338 n153 -01 1 -.names N_N579 n151 n153 n175 n152 ---10 1 -10-0 1 -.names scf_in_26_ n129 n137 n320 n156 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names N_N576 n138 n142 n150 n157 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names [36] N_N580 n147 n299 n158 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n149 n152 n333 n337 n159 -10-- 1 --00- 1 --0-1 1 -.names n156 n157 n158 n159 n155 -1111 1 -.names scf_in_18_ scf_in_19_ n161 -1- 1 --1 1 -.names n161 scf_in_17_ scf_in_19_ n160 -11- 1 -1-1 1 -.names [36] n127 n160 n344 n162 --0-0 1 -100- 1 -.names scf_out_13_ scf_out_2_ N_N576 n365 n168 -0--1 1 --0-1 1 ---11 1 -.names scf_out_0_ N_N580 n162 n168 n165 -1-01 1 --001 1 -.names scf_out_13_ scf_out_2_ N_N580 n144 n169 -10-0 1 -1-10 1 -.names scf_in_26_ n183 n366 n368 n171 -10-- 1 -1-0- 1 -1--0 1 -.names scf_in_26_ N_N581 n175 -0- 1 --0 1 -.names n165 n169 n171 n175 n174 -100- 1 --001 1 -.names n149 n250 n338 n364 n180 -1--1 1 --101 1 -.names N_N575 n144 n179 -1- 1 --1 1 -.names n180 scf_out_13_ n179 n178 -11- 1 -1-1 1 -.names scf_out_13_ n151 n182 -0- 1 --1 1 -.names N_N579 n128 n183 -1- 1 --1 1 -.names n182 n183 scf_out_2_ n21 n181 -111- 1 -11-1 1 -.names n369 n144 n361 n368 n184 -11-- 1 -1-11 1 -.names N_N579 N_N575 n174 n178 n185 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names scf_in_16_ n161 n195 n186 -000 1 -.names scf_in_21_ scf_out_2_ n127 n186 n188 --0-1 1 -100- 1 -.names n123 n251 n189 -10 1 -.names [36] n127 n192 -1- 1 --1 1 -.names N_N576 N_N580 n193 -0- 1 --0 1 -.names N_N576 n123 n192 n193 n191 -0-11 1 --111 1 -.names N_N576 n339 n195 -1- 1 --1 1 -.names scf_in_17_ n161 n196 -1- 1 --1 1 -.names n148 n195 n196 n194 -11- 1 -1-1 1 -.names scf_in_19_ scf_in_18_ scf_in_17_ n198 -1-- 1 --0- 1 ---1 1 -.names n127 n198 scf_in_11_ n21 n197 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n112 n188 n189 n400 n199 -01-- 1 -0-1- 1 -0--0 1 -.names scf_out_13_ n123 n144 n370 n202 --0-0 1 -000- 1 -.names N_N576 n296 n298 n206 -01- 1 -1-1 1 --11 1 -.names scf_in_26_ scf_out_0_ N_N580 n411 n207 -0--1 1 --1-1 1 ---01 1 -.names n202 n320 n371 n373 n208 -01-- 1 -0-11 1 -.names n144 n251 n209 -1- 1 --1 1 -.names n191 n197 n304 n306 n210 -11-- 1 -1-0- 1 --1-1 1 ---01 1 -.names n327 [36] n194 n175 n212 -11-- 1 -1-1- 1 -1--1 1 -.names scf_out_13_ N_N579 n150 n213 -0-- 1 --0- 1 ---1 1 -.names n199 n206 n207 n208 n209 n210 n212 n213 n205 -01111111 1 -.names scf_in_22_ n123 n263 n214 -0-0 1 --10 1 -.names N_N579 n127 n161 n218 -0-- 1 --1- 1 ---0 1 -.names scf_out_0_ n196 n339 n378 n219 -1--1 1 --0-1 1 ---11 1 -.names scf_out_13_ N_N576 n217 -1- 1 --1 1 -.names n218 n219 n214 n217 n216 -111- 1 -11-1 1 -.names scf_in_11_ n21 N_N579 n221 -0-- 1 --1- 1 ---0 1 -.names scf_out_13_ n151 n222 -1- 1 --1 1 -.names scf_out_13_ N_N579 n104 n223 -0-- 1 --1- 1 ---1 1 -.names scf_in_11_ n195 n333 n224 -1-- 1 --1- 1 ---0 1 -.names scf_in_24_ N_N576 n253 n225 -1-- 1 --0- 1 ---1 1 -.names N_N581 n151 n216 n226 -01- 1 -1-1 1 --11 1 -.names N_N580 n139 n227 -1- 1 --1 1 -.names scf_out_0_ N_N579 N_N576 n251 n228 -10-- 1 --00- 1 -1--1 1 ---01 1 -.names n221 n222 n223 n224 n225 n226 n227 n228 n220 -11111111 1 -.names scf_in_23_ N_N576 n139 n253 n229 --00- 1 -10-0 1 -.names n151 n253 n234 -1- 1 --1 1 -.names N_N575 n220 n229 n234 n231 -0-01 1 --101 1 -.names [36] N_N580 n127 n333 n235 -0-1- 1 --01- 1 -0--0 1 --0-0 1 -.names [36] n150 n151 n375 n236 -0--0 1 -000- 1 -.names n149 n236 n376 n377 n240 -10-- 1 --011 1 -.names n382 n380 n144 n183 n241 -111- 1 -11-1 1 -.names scf_out_13_ n333 n243 -0- 1 --0 1 -.names N_N579 n102 N_N580 n243 n242 -01-1 1 --111 1 -.names n242 n104 N_N580 n276 n245 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names N_N581 n390 n391 n412 n246 -1--0 1 --110 1 -.names n21 n124 n263 n339 n247 -1-0- 1 --10- 1 -1--1 1 --1-1 1 -.names scf_in_23_ N_N579 n193 n395 n248 -0--1 1 --1-1 1 ---11 1 -.names n245 n246 n247 n248 n244 -1111 1 -.names scf_out_13_ N_N580 n250 -0- 1 --0 1 -.names scf_out_13_ N_N580 n251 -1- 1 --0 1 -.names N_N579 n250 n251 n333 n249 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names N_N579 n148 n254 -0- 1 --1 1 -.names scf_out_13_ n123 n253 -0- 1 --1 1 -.names N_N580 n254 n253 n252 -01- 1 --11 1 -.names N_N581 n249 n252 n256 -11- 1 -0-1 1 --11 1 -.names n153 n297 n333 n335 n257 -01-1 1 -0-01 1 -.names n256 n257 scf_out_0_ n127 n255 -111- 1 -11-1 1 -.names scf_in_23_ [36] N_N575 n259 -1-1 1 --01 1 -.names scf_out_2_ n196 n259 n333 n258 -1-10 1 --110 1 -.names scf_in_20_ scf_out_13_ scf_out_2_ N_N575 n260 ---00 1 -000- 1 -.names n333 scf_in_11_ n263 -11 1 -.names N_N580 n260 n263 n262 -01- 1 -0-1 1 -.names N_N576 n258 n262 n339 n264 -0-1- 1 -00-0 1 -.names scf_out_0_ N_N581 n339 n385 n266 -0--0 1 -000- 1 -.names scf_in_16_ n124 n160 n333 n271 -11-- 1 --11- 1 --1-0 1 -.names scf_in_16_ [36] n195 n196 n272 -000- 1 --001 1 -.names scf_in_20_ scf_out_2_ n217 n274 -1-- 1 --1- 1 ---1 1 -.names scf_in_22_ n123 n217 n276 -1-- 1 --1- 1 ---1 1 -.names n127 n153 n271 n346 n277 -10-- 1 --01- 1 -1--0 1 ---10 1 -.names N_N579 n128 n222 n278 -11- 1 -0-1 1 --11 1 -.names n221 n272 n274 n276 n277 n278 n273 -101111 1 -.names N_N575 n253 n368 n403 n280 -0-1- 1 --111 1 -.names scf_out_2_ scf_out_0_ n21 n338 n281 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names [36] n193 n280 n281 n279 -0-11 1 --111 1 -.names n138 n148 scf_out_13_ scf_out_0_ n282 -111- 1 -11-1 1 -.names scf_in_21_ scf_out_13_ N_N580 n331 n283 --1-0 1 -0-00 1 -.names scf_out_0_ n104 n151 n420 n286 -00-- 1 -0-0- 1 -0--0 1 -.names [36] n104 N_N580 n148 n288 -1--0 1 -100- 1 -.names scf_in_26_ N_N575 n352 n415 n290 -10-0 1 -1-00 1 -.names n279 n144 n273 n320 n294 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n179 n282 n290 n405 n295 -1-01 1 --101 1 -.names scf_out_0_ n150 n296 -1- 1 --1 1 -.names N_N580 n217 n297 -1- 1 --1 1 -.names N_N575 n304 n298 -1- 1 --0 1 -.names scf_out_13_ n23 N_N580 n325 n300 -10-- 1 --01- 1 --0-1 1 -.names n193 n349 N_N579 n327 n301 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names scf_out_2_ n144 n299 -1- 1 --1 1 -.names n175 n333 n304 -01 1 -.names n151 n304 n350 n302 -01- 1 -0-0 1 -.names scf_out_2_ n128 n305 -1- 1 --1 1 -.names N_N575 n144 n306 -0- 1 --1 1 -.names n123 n127 n307 -1- 1 --1 1 -.names n112 n123 n222 n308 -1-- 1 --1- 1 ---1 1 -.names n21 n325 n309 -1- 1 --1 1 -.names n30 N_N579 n128 n320 n310 -10-- 1 -1-1- 1 -1--1 1 -.names n52 n317 n21 n298 n311 -111- 1 -11-1 1 -.names n123 n128 n149 n321 n312 -0--0 1 -000- 1 -.names [36] n298 n321 n340 n316 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names n56 n47 n309 n317 -111 1 -.names n49 n45 n251 n20 n318 -111- 1 -11-1 1 -.names n316 n317 n318 n315 -111 1 -.names N_N575 n175 n320 -0- 1 --1 1 -.names n175 n222 n321 -1- 1 --1 1 -.names n151 n349 n322 -1- 1 --1 1 -.names n381 N_N579 n175 n148 n323 -11-- 1 -1-1- 1 -1--1 1 -.names n325 n338 n324 -1- 1 --0 1 -.names n222 n350 n326 -1- 1 --1 1 -.names scf_out_2_ n150 n325 -1- 1 --1 1 -.names n144 n182 n234 n304 n328 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n409 n37 n28 n329 -111 1 -.names n150 n195 n327 -1- 1 --1 1 -.names n56 n148 n298 n330 -11- 1 -1-1 1 -.names scf_out_2_ N_N576 n331 -1- 1 --0 1 -.names N_N579 [36] n333 -11 1 -.names scf_out_0_ n251 n335 -1- 1 --1 1 -.names scf_out_13_ n104 n337 -0- 1 --0 1 -.names N_N580 n127 n338 -00 1 -.names scf_out_13_ N_N580 n339 -0- 1 --1 1 -.names scf_out_13_ N_N576 n340 -0- 1 --0 1 -.names scf_in_15_ scf_in_14_ scf_in_13_ n341 -1-- 1 --1- 1 ---1 1 -.names scf_in_11_ scf_out_0_ n344 -0- 1 --1 1 -.names scf_in_8_ scf_in_7_ scf_in_6_ scf_in_5_ scf_in_4_ scf_in_3_ scf_in_2_ \ -scf_in_1_ n346 -1------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------0 1 -.names N_N575 n304 n348 -11 1 -.names scf_in_26_ N_N579 n139 n349 -0-- 1 --1- 1 ---1 1 -.names n144 n123 n350 -1- 1 --1 1 -.names N_N575 n244 n255 n351 -11- 1 -0-1 1 --11 1 -.names scf_in_24_ n21 N_N579 n283 n354 -1--0 1 --1-0 1 ---10 1 -.names n123 n151 n286 n354 n352 -1-01 1 --101 1 -.names [36] scf_out_13_ N_N581 n416 n355 -0--1 1 --0-1 1 ---01 1 -.names [36] N_N576 n97 N_N581 n356 -0--0 1 -000- 1 -.names [36] n113 n149 n359 -1-- 1 --1- 1 ---1 1 -.names scf_out_0_ n340 n361 -1- 1 --1 1 -.names n361 scf_out_2_ n97 n195 n360 -11-- 1 -1-1- 1 -1--1 1 -.names scf_in_26_ n113 n364 -0- 1 --1 1 -.names scf_in_11_ N_N579 n307 n339 n365 -1-1- 1 --01- 1 ---11 1 -.names scf_out_0_ n217 n341 n367 -1-- 1 --1- 1 ---1 1 -.names scf_in_25_ n307 n367 n366 -0-1 1 --11 1 -.names n149 n333 n337 n369 -1-- 1 --0- 1 ---0 1 -.names [36] n251 n368 -0- 1 --1 1 -.names scf_in_26_ n149 n222 n338 n370 -01-- 1 -0-1- 1 --1-0 1 ---10 1 -.names scf_in_20_ scf_out_2_ n217 n372 -0-- 1 --1- 1 ---1 1 -.names scf_in_10_ scf_out_13_ n331 n372 n371 -0--1 1 --0-1 1 ---11 1 -.names N_N579 N_N576 n151 n344 n373 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n21 n175 n179 n338 n375 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names [36] N_N580 n128 n333 n376 -00-- 1 --01- 1 -0--0 1 ---10 1 -.names n123 n339 N_N576 scf_out_0_ n377 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n148 [36] scf_in_10_ n340 n378 -11-- 1 -1-1- 1 -1--1 1 -.names scf_out_2_ n175 n250 n381 -1-- 1 --1- 1 ---1 1 -.names N_N579 n175 n251 n381 n380 -0--1 1 --1-1 1 ---11 1 -.names n235 n179 n382 -1- 1 --1 1 -.names N_N575 n341 n384 -0- 1 --0 1 -.names scf_in_17_ n195 n297 n384 n385 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names scf_out_2_ n193 n387 -1- 1 --1 1 -.names N_N579 n161 n195 n387 n386 -0--1 1 --0-1 1 ---11 1 -.names n153 n338 n344 n346 n388 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names scf_in_25_ scf_in_9_ n102 n143 n390 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names scf_out_2_ N_N580 n127 n333 n391 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names scf_in_10_ scf_out_13_ n392 -1- 1 --0 1 -.names n331 n392 [36] n250 n393 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names scf_in_19_ scf_in_17_ n333 n338 n395 -1--- 1 --1-- 1 ---0- 1 ----0 1 -.names N_N580 n223 n266 n305 n396 -0-01 1 --101 1 -.names scf_out_13_ scf_out_2_ n104 n400 -0-- 1 --1- 1 ---1 1 -.names n123 n288 n297 n400 n398 -10-1 1 --011 1 -.names scf_out_2_ N_N576 n151 n253 n401 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names scf_in_0_ n331 n403 -1- 1 --1 1 -.names [36] n150 n128 n406 -1-- 1 --1- 1 ---1 1 -.names n406 N_N576 N_N580 n296 n405 -11-- 1 -1-1- 1 -1--1 1 -.names n179 n305 n409 -1- 1 --1 1 -.names [36] N_N576 N_N575 n410 -1-- 1 --0- 1 ---0 1 -.names n149 n139 N_N580 n411 -1-- 1 --1- 1 ---1 1 -.names N_N581 n148 n225 n393 n412 -10-- 1 -1-0- 1 -1--0 1 -.names N_N575 n398 n401 n415 -011 1 -.names scf_out_13_ N_N579 n416 -1- 1 --1 1 -.names n296 n338 n417 -1- 1 --0 1 -.names scf_in_12_ n217 n341 n420 -1-- 1 --1- 1 ---1 1 -.names n155 N_N94 -0 1 -.names n205 N_N92 -0 1 -.names [36] scf_out_27_ -1 1 -.names [36] scf_out_8_ -1 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/simple_spi.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/simple_spi.blif deleted file mode 100644 index d2c545b2a..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/simple_spi.blif +++ /dev/null @@ -1,2055 +0,0 @@ -# Benchmark "simple_spi" written by ABC on Mon Aug 29 15:33:11 2005 -.model simple_spi -.inputs clk_i rst_i cyc_i stb_i we_i miso_i adr_i[0] adr_i[1] dat_i[0] \ - dat_i[1] dat_i[2] dat_i[3] dat_i[4] dat_i[5] dat_i[6] dat_i[7] -.outputs dat_o[0] dat_o[1] dat_o[2] dat_o[3] dat_o[4] dat_o[5] dat_o[6] \ - dat_o[7] ack_o inta_o sck_o mosi_o - -.latch \tcnt_reg[1]_in \tcnt_reg[1] 2 -.latch rfifo_gb_reg_in rfifo_gb_reg 2 -.latch \tcnt_reg[0]_in \tcnt_reg[0] 2 -.latch spif_reg_in spif_reg 2 -.latch \rfifo_wp_reg[1]_in \rfifo_wp_reg[1] 0 -.latch \rfifo_wp_reg[0]_in \rfifo_wp_reg[0] 0 -.latch \rfifo_mem_reg[1][4]_in \rfifo_mem_reg[1][4] 2 -.latch \rfifo_mem_reg[1][5]_in \rfifo_mem_reg[1][5] 2 -.latch \rfifo_mem_reg[1][6]_in \rfifo_mem_reg[1][6] 2 -.latch \rfifo_mem_reg[1][7]_in \rfifo_mem_reg[1][7] 2 -.latch \rfifo_mem_reg[1][8]_in \rfifo_mem_reg[1][8] 2 -.latch \rfifo_mem_reg[2][1]_in \rfifo_mem_reg[2][1] 2 -.latch \rfifo_mem_reg[2][2]_in \rfifo_mem_reg[2][2] 2 -.latch \rfifo_mem_reg[2][3]_in \rfifo_mem_reg[2][3] 2 -.latch \rfifo_mem_reg[2][4]_in \rfifo_mem_reg[2][4] 2 -.latch \rfifo_mem_reg[2][5]_in \rfifo_mem_reg[2][5] 2 -.latch \rfifo_mem_reg[2][6]_in \rfifo_mem_reg[2][6] 2 -.latch \rfifo_mem_reg[2][7]_in \rfifo_mem_reg[2][7] 2 -.latch \rfifo_mem_reg[2][8]_in \rfifo_mem_reg[2][8] 2 -.latch \rfifo_mem_reg[1][1]_in \rfifo_mem_reg[1][1] 2 -.latch \rfifo_mem_reg[1][2]_in \rfifo_mem_reg[1][2] 2 -.latch \rfifo_mem_reg[1][3]_in \rfifo_mem_reg[1][3] 2 -.latch \rfifo_mem_reg[3][1]_in \rfifo_mem_reg[3][1] 2 -.latch \rfifo_mem_reg[3][2]_in \rfifo_mem_reg[3][2] 2 -.latch \rfifo_mem_reg[3][3]_in \rfifo_mem_reg[3][3] 2 -.latch \rfifo_mem_reg[3][4]_in \rfifo_mem_reg[3][4] 2 -.latch \rfifo_mem_reg[3][5]_in \rfifo_mem_reg[3][5] 2 -.latch \rfifo_mem_reg[3][6]_in \rfifo_mem_reg[3][6] 2 -.latch \rfifo_mem_reg[3][7]_in \rfifo_mem_reg[3][7] 2 -.latch \rfifo_mem_reg[3][8]_in \rfifo_mem_reg[3][8] 2 -.latch \rfifo_mem_reg[0][1]_in \rfifo_mem_reg[0][1] 2 -.latch \rfifo_mem_reg[0][2]_in \rfifo_mem_reg[0][2] 2 -.latch \rfifo_mem_reg[0][4]_in \rfifo_mem_reg[0][4] 2 -.latch \rfifo_mem_reg[0][5]_in \rfifo_mem_reg[0][5] 2 -.latch \rfifo_mem_reg[0][6]_in \rfifo_mem_reg[0][6] 2 -.latch \rfifo_mem_reg[0][8]_in \rfifo_mem_reg[0][8] 2 -.latch \rfifo_mem_reg[0][3]_in \rfifo_mem_reg[0][3] 2 -.latch \rfifo_mem_reg[0][7]_in \rfifo_mem_reg[0][7] 2 -.latch sck_o_reg_in sck_o_reg 2 -.latch \state_reg[0]_in \state_reg[0] 2 -.latch \bcnt_reg[0]_in \bcnt_reg[0] 2 -.latch \bcnt_reg[2]_in \bcnt_reg[2] 2 -.latch \clkcnt_reg[8]_in \clkcnt_reg[8] 2 -.latch \treg_reg[7]_in \treg_reg[7] 2 -.latch \bcnt_reg[1]_in \bcnt_reg[1] 2 -.latch \treg_reg[2]_in \treg_reg[2] 2 -.latch \treg_reg[3]_in \treg_reg[3] 2 -.latch \treg_reg[4]_in \treg_reg[4] 2 -.latch \treg_reg[5]_in \treg_reg[5] 2 -.latch \treg_reg[6]_in \treg_reg[6] 2 -.latch \treg_reg[0]_in \treg_reg[0] 2 -.latch \treg_reg[1]_in \treg_reg[1] 2 -.latch \clkcnt_reg[10]_in \clkcnt_reg[10] 2 -.latch \clkcnt_reg[7]_in \clkcnt_reg[7] 2 -.latch \clkcnt_reg[4]_in \clkcnt_reg[4] 2 -.latch \clkcnt_reg[3]_in \clkcnt_reg[3] 2 -.latch \clkcnt_reg[6]_in \clkcnt_reg[6] 2 -.latch \clkcnt_reg[9]_in \clkcnt_reg[9] 2 -.latch \clkcnt_reg[2]_in \clkcnt_reg[2] 2 -.latch \clkcnt_reg[0]_in \clkcnt_reg[0] 2 -.latch \clkcnt_reg[1]_in \clkcnt_reg[1] 2 -.latch \clkcnt_reg[5]_in \clkcnt_reg[5] 2 -.latch \state_reg[1]_in \state_reg[1] 2 -.latch rfwe_reg_in rfwe_reg 2 -.latch \clkcnt_reg[11]_in \clkcnt_reg[11] 2 -.latch \dat_o_reg[6]_in \dat_o_reg[6] 2 -.latch wfifo_gb_reg_in wfifo_gb_reg 2 -.latch \dat_o_reg[3]_in \dat_o_reg[3] 2 -.latch \dat_o_reg[2]_in \dat_o_reg[2] 2 -.latch \dat_o_reg[1]_in \dat_o_reg[1] 2 -.latch \dat_o_reg[5]_in \dat_o_reg[5] 2 -.latch \dat_o_reg[0]_in \dat_o_reg[0] 2 -.latch wcol_reg_in wcol_reg 2 -.latch \dat_o_reg[7]_in \dat_o_reg[7] 2 -.latch \dat_o_reg[4]_in \dat_o_reg[4] 2 -.latch \rfifo_rp_reg[1]_in \rfifo_rp_reg[1] 0 -.latch \wfifo_rp_reg[1]_in \wfifo_rp_reg[1] 0 -.latch \rfifo_rp_reg[0]_in \rfifo_rp_reg[0] 0 -.latch \wfifo_mem_reg[2][5]_in \wfifo_mem_reg[2][5] 2 -.latch \wfifo_mem_reg[1][7]_in \wfifo_mem_reg[1][7] 2 -.latch \wfifo_mem_reg[2][1]_in \wfifo_mem_reg[2][1] 2 -.latch \wfifo_mem_reg[1][5]_in \wfifo_mem_reg[1][5] 2 -.latch \wfifo_wp_reg[1]_in \wfifo_wp_reg[1] 0 -.latch \wfifo_wp_reg[0]_in \wfifo_wp_reg[0] 0 -.latch \wfifo_mem_reg[1][1]_in \wfifo_mem_reg[1][1] 2 -.latch \wfifo_mem_reg[1][2]_in \wfifo_mem_reg[1][2] 2 -.latch \wfifo_mem_reg[1][3]_in \wfifo_mem_reg[1][3] 2 -.latch \wfifo_mem_reg[1][4]_in \wfifo_mem_reg[1][4] 2 -.latch \wfifo_mem_reg[1][6]_in \wfifo_mem_reg[1][6] 2 -.latch \wfifo_mem_reg[1][8]_in \wfifo_mem_reg[1][8] 2 -.latch \wfifo_mem_reg[2][2]_in \wfifo_mem_reg[2][2] 2 -.latch \wfifo_mem_reg[2][3]_in \wfifo_mem_reg[2][3] 2 -.latch \wfifo_mem_reg[2][4]_in \wfifo_mem_reg[2][4] 2 -.latch \wfifo_mem_reg[2][6]_in \wfifo_mem_reg[2][6] 2 -.latch \wfifo_mem_reg[2][7]_in \wfifo_mem_reg[2][7] 2 -.latch \wfifo_mem_reg[2][8]_in \wfifo_mem_reg[2][8] 2 -.latch \wfifo_mem_reg[0][5]_in \wfifo_mem_reg[0][5] 2 -.latch \wfifo_mem_reg[3][5]_in \wfifo_mem_reg[3][5] 2 -.latch \wfifo_mem_reg[3][1]_in \wfifo_mem_reg[3][1] 2 -.latch \wfifo_mem_reg[0][8]_in \wfifo_mem_reg[0][8] 2 -.latch \wfifo_mem_reg[0][1]_in \wfifo_mem_reg[0][1] 2 -.latch \wfifo_mem_reg[0][2]_in \wfifo_mem_reg[0][2] 2 -.latch \wfifo_mem_reg[0][3]_in \wfifo_mem_reg[0][3] 2 -.latch \wfifo_mem_reg[0][4]_in \wfifo_mem_reg[0][4] 2 -.latch \wfifo_mem_reg[0][7]_in \wfifo_mem_reg[0][7] 2 -.latch \wfifo_mem_reg[0][6]_in \wfifo_mem_reg[0][6] 2 -.latch \wfifo_mem_reg[3][2]_in \wfifo_mem_reg[3][2] 2 -.latch \wfifo_mem_reg[3][3]_in \wfifo_mem_reg[3][3] 2 -.latch \wfifo_mem_reg[3][4]_in \wfifo_mem_reg[3][4] 2 -.latch \wfifo_mem_reg[3][6]_in \wfifo_mem_reg[3][6] 2 -.latch \wfifo_mem_reg[3][7]_in \wfifo_mem_reg[3][7] 2 -.latch \wfifo_mem_reg[3][8]_in \wfifo_mem_reg[3][8] 2 -.latch \sper_reg[5]_in \sper_reg[5] 0 -.latch wfre_reg_in wfre_reg 2 -.latch \sper_reg[0]_in \sper_reg[0] 0 -.latch \sper_reg[1]_in \sper_reg[1] 0 -.latch \sper_reg[2]_in \sper_reg[2] 0 -.latch \sper_reg[3]_in \sper_reg[3] 0 -.latch \sper_reg[4]_in \sper_reg[4] 0 -.latch \sper_reg[6]_in \sper_reg[6] 0 -.latch \sper_reg[7]_in \sper_reg[7] 0 -.latch \spcr_reg[7]_in \spcr_reg[7] 0 -.latch \spcr_reg[5]_in \spcr_reg[5] 0 -.latch \spcr_reg[0]_in \spcr_reg[0] 0 -.latch \spcr_reg[2]_in \spcr_reg[2] 0 -.latch \spcr_reg[4]_in \spcr_reg[4] 1 -.latch \spcr_reg[1]_in \spcr_reg[1] 0 -.latch \spcr_reg[3]_in \spcr_reg[3] 0 -.latch \spcr_reg[6]_in \spcr_reg[6] 0 -.latch \wfifo_rp_reg[0]_in \wfifo_rp_reg[0] 0 -.latch ack_o_reg_in ack_o_reg 0 -.latch inta_o_reg_in inta_o_reg 2 - -.names [160] - 0 -.names [161] - 1 -.names \tcnt_reg[1] [162] -1 1 -.names rfifo_gb_reg [163] -1 1 -.names [243] [203] \tcnt_reg[1]_in -11 0 -.names \tcnt_reg[0] [165] -1 1 -.names spif_reg [166] -1 1 -.names [574] [241] [767] rfifo_gb_reg_in -11- 0 ---1 0 -.names \rfifo_wp_reg[1] [168] -1 1 -.names \rfifo_wp_reg[0] [169] -1 1 -.names \rfifo_mem_reg[1][4] [170] -1 1 -.names \rfifo_mem_reg[1][5] [171] -1 1 -.names \rfifo_mem_reg[1][6] [172] -1 1 -.names \rfifo_mem_reg[1][7] [173] -1 1 -.names \rfifo_mem_reg[1][8] [174] -1 1 -.names \rfifo_mem_reg[2][1] [175] -1 1 -.names \rfifo_mem_reg[2][2] [176] -1 1 -.names \rfifo_mem_reg[2][3] [177] -1 1 -.names \rfifo_mem_reg[2][4] [178] -1 1 -.names \rfifo_mem_reg[2][5] [179] -1 1 -.names \rfifo_mem_reg[2][6] [180] -1 1 -.names \rfifo_mem_reg[2][7] [181] -1 1 -.names \rfifo_mem_reg[2][8] [182] -1 1 -.names \rfifo_mem_reg[1][1] [183] -1 1 -.names \rfifo_mem_reg[1][2] [184] -1 1 -.names \rfifo_mem_reg[1][3] [185] -1 1 -.names \rfifo_mem_reg[3][1] [186] -1 1 -.names \rfifo_mem_reg[3][2] [187] -1 1 -.names \rfifo_mem_reg[3][3] [188] -1 1 -.names \rfifo_mem_reg[3][4] [189] -1 1 -.names \rfifo_mem_reg[3][5] [190] -1 1 -.names \rfifo_mem_reg[3][6] [191] -1 1 -.names \rfifo_mem_reg[3][7] [192] -1 1 -.names \rfifo_mem_reg[3][8] [193] -1 1 -.names \rfifo_mem_reg[0][1] [194] -1 1 -.names \rfifo_mem_reg[0][2] [195] -1 1 -.names \rfifo_mem_reg[0][4] [196] -1 1 -.names \rfifo_mem_reg[0][5] [197] -1 1 -.names \rfifo_mem_reg[0][6] [198] -1 1 -.names \rfifo_mem_reg[0][8] [199] -1 1 -.names \rfifo_mem_reg[0][3] [200] -1 1 -.names \rfifo_mem_reg[0][7] [201] -1 1 -.names [531] [239] spif_reg_in -11 0 -.names [240] [836] [203] -11 0 -.names [465] [244] [831] \tcnt_reg[0]_in -01- 1 -1-1 1 -.names [640] [172] [272] \rfifo_mem_reg[1][6]_in -01- 1 -1-1 1 -.names [641] [173] [272] \rfifo_mem_reg[1][7]_in -01- 1 -1-1 1 -.names [650] [174] [272] \rfifo_mem_reg[1][8]_in -01- 1 -1-1 1 -.names [648] [175] [272] \rfifo_mem_reg[2][1]_in -01- 1 -1-1 1 -.names [644] [176] [272] \rfifo_mem_reg[2][2]_in -01- 1 -1-1 1 -.names [647] [178] [272] \rfifo_mem_reg[2][4]_in -01- 1 -1-1 1 -.names [646] [177] [272] \rfifo_mem_reg[2][3]_in -01- 1 -1-1 1 -.names [645] [179] [272] \rfifo_mem_reg[2][5]_in -01- 1 -1-1 1 -.names [654] [180] [272] \rfifo_mem_reg[2][6]_in -01- 1 -1-1 1 -.names [643] [181] [272] \rfifo_mem_reg[2][7]_in -01- 1 -1-1 1 -.names [651] [182] [272] \rfifo_mem_reg[2][8]_in -01- 1 -1-1 1 -.names [649] [183] [272] \rfifo_mem_reg[1][1]_in -01- 1 -1-1 1 -.names [653] [184] [272] \rfifo_mem_reg[1][2]_in -01- 1 -1-1 1 -.names [655] [185] [272] \rfifo_mem_reg[1][3]_in -01- 1 -1-1 1 -.names [705] [186] [272] \rfifo_mem_reg[3][1]_in -01- 1 -1-1 1 -.names [698] [187] [272] \rfifo_mem_reg[3][2]_in -01- 1 -1-1 1 -.names [706] [188] [272] \rfifo_mem_reg[3][3]_in -01- 1 -1-1 1 -.names [697] [189] [272] \rfifo_mem_reg[3][4]_in -01- 1 -1-1 1 -.names [701] [190] [272] \rfifo_mem_reg[3][5]_in -01- 1 -1-1 1 -.names [699] [191] [272] \rfifo_mem_reg[3][6]_in -01- 1 -1-1 1 -.names [700] [192] [272] \rfifo_mem_reg[3][7]_in -01- 1 -1-1 1 -.names [702] [193] [272] \rfifo_mem_reg[3][8]_in -01- 1 -1-1 1 -.names [743] [194] [272] \rfifo_mem_reg[0][1]_in -01- 1 -1-1 1 -.names [744] [195] [272] \rfifo_mem_reg[0][2]_in -01- 1 -1-1 1 -.names [745] [200] [272] \rfifo_mem_reg[0][3]_in -01- 1 -1-1 1 -.names [746] [196] [272] \rfifo_mem_reg[0][4]_in -01- 1 -1-1 1 -.names [736] [197] [272] \rfifo_mem_reg[0][5]_in -01- 1 -1-1 1 -.names [737] [198] [272] \rfifo_mem_reg[0][6]_in -01- 1 -1-1 1 -.names [747] [201] [272] \rfifo_mem_reg[0][7]_in -01- 1 -1-1 1 -.names [748] [199] [272] \rfifo_mem_reg[0][8]_in -01- 1 -1-1 1 -.names [248] [252] [971] \rfifo_wp_reg[1]_in -11- 0 ---1 0 -.names [246] [247] [971] \rfifo_wp_reg[0]_in -11- 0 ---1 0 -.names [652] [170] [272] \rfifo_mem_reg[1][4]_in -01- 1 -1-1 1 -.names [642] [171] [272] \rfifo_mem_reg[1][5]_in -01- 1 -1-1 1 -.names [249] [627] [876] [239] -111 0 -.names [253] [245] [240] -11 0 -.names [250] [722] [241] -11 0 -.names sck_o_reg sck_o -1 1 -.names [809] [272] [473] [844] [243] -11-- 0 ---11 0 -.names [776] [272] [268] [244] -00- 1 ---0 1 -.names [270] [853] [165] [245] -111 0 -.names [882] [272] [246] -11 0 -.names [882] [272] [247] -00 0 -.names [168] [272] [248] -11 0 -.names [272] [859] [249] -00 1 -.names [685] [272] [250] -00 1 -.names \state_reg[0] [251] -1 1 -.names [760] [272] [252] -00 0 -.names [269] [876] [253] -11 0 -.names \bcnt_reg[0] [254] -1 1 -.names [267] sck_o_reg_in -0 1 -.names \bcnt_reg[2] [256] -1 1 -.names \clkcnt_reg[8] [257] -1 1 -.names \treg_reg[7] mosi_o -1 1 -.names \bcnt_reg[1] [259] -1 1 -.names \treg_reg[2] [260] -1 1 -.names \treg_reg[3] [261] -1 1 -.names \treg_reg[4] [262] -1 1 -.names \treg_reg[5] [263] -1 1 -.names \treg_reg[6] [264] -1 1 -.names \treg_reg[0] [265] -1 1 -.names \treg_reg[1] [266] -1 1 -.names [932] [771] [267] -11 0 -.names [165] [297] [268] -11 0 -.names [297] [903] [269] -00 1 -.names [297] [902] [270] -00 1 -.names [279] \state_reg[0]_in -0 1 -.names [285] [272] -0 1 -.names [298] [333] \clkcnt_reg[8]_in -11 0 -.names [414] [300] [814] \treg_reg[0]_in -11- 0 ---1 0 -.names [322] [975] [971] \bcnt_reg[2]_in -11- 0 ---1 0 -.names [415] [308] [859] \treg_reg[1]_in -11- 0 ---1 0 -.names [416] [309] [859] \treg_reg[2]_in -11- 0 ---1 0 -.names [417] [311] [859] \treg_reg[3]_in -11- 0 ---1 0 -.names [299] [771] [279] -11 0 -.names [418] [312] [814] \treg_reg[4]_in -11- 0 ---1 0 -.names [419] [313] [814] \treg_reg[5]_in -11- 0 ---1 0 -.names [420] [314] [859] \treg_reg[6]_in -11- 0 ---1 0 -.names [315] [411] [814] \treg_reg[7]_in -11- 0 ---1 0 -.names [305] [975] [971] \bcnt_reg[1]_in -11- 0 ---1 0 -.names [297] [285] -0 1 -.names \clkcnt_reg[10] [286] -1 1 -.names \clkcnt_reg[7] [287] -1 1 -.names \clkcnt_reg[4] [288] -1 1 -.names \clkcnt_reg[3] [289] -1 1 -.names \clkcnt_reg[6] [290] -1 1 -.names \clkcnt_reg[9] [291] -1 1 -.names \clkcnt_reg[2] [292] -1 1 -.names \clkcnt_reg[0] [293] -1 1 -.names \clkcnt_reg[1] [294] -1 1 -.names \clkcnt_reg[5] [295] -1 1 -.names \state_reg[1] [296] -1 1 -.names rfwe_reg [297] -0 1 -.names [537] [388] [324] [298] -11- 0 ---1 0 -.names [365] [528] [372] [758] [299] -1111 0 -.names [358] [977] [265] [973] [300] -11-- 0 ---11 0 -.names [325] rfwe_reg_in -0 1 -.names [348] [332] \clkcnt_reg[4]_in -11 0 -.names [351] [334] \clkcnt_reg[0]_in -11 0 -.names [350] [337] \clkcnt_reg[2]_in -11 0 -.names [356] [977] [873] [973] [305] -11-- 0 ---11 0 -.names \clkcnt_reg[11] [306] -1 1 -.names [340] [338] \clkcnt_reg[3]_in -11 0 -.names [359] [977] [266] [973] [308] -11-- 0 ---11 0 -.names [360] [977] [260] [973] [309] -11-- 0 ---11 0 -.names \dat_o_reg[6] dat_o[6] -1 1 -.names [361] [977] [261] [973] [311] -11-- 0 ---11 0 -.names [362] [977] [262] [973] [312] -11-- 0 ---11 0 -.names [363] [977] [263] [973] [313] -11-- 0 ---11 0 -.names [364] [977] [264] [973] [314] -11-- 0 ---11 0 -.names [357] [977] [973] mosi_o [315] -11-- 0 ---11 0 -.names [353] [334] \clkcnt_reg[1]_in -11 0 -.names [349] [336] \clkcnt_reg[10]_in -11 0 -.names [354] [332] \clkcnt_reg[5]_in -11 0 -.names [335] [343] \clkcnt_reg[7]_in -11 0 -.names [365] [830] [339] \state_reg[1]_in -00- 1 ---0 1 -.names [370] [333] \clkcnt_reg[9]_in -11 0 -.names [373] [977] [869] [973] [322] -11-- 0 ---11 0 -.names [341] [331] \clkcnt_reg[6]_in -11 0 -.names [753] [382] [838] [324] -11- 0 ---1 0 -.names [371] [778] [512] [977] [325] -1111 0 -.names wfifo_gb_reg [326] -1 1 -.names \dat_o_reg[3] dat_o[3] -1 1 -.names \dat_o_reg[2] dat_o[2] -1 1 -.names \dat_o_reg[1] dat_o[1] -1 1 -.names \dat_o_reg[5] dat_o[5] -1 1 -.names [735] [374] [331] -11 0 -.names [806] [375] [332] -11 0 -.names [374] [828] [333] -11 0 -.names [805] [375] [334] -11 0 -.names [375] [461] [335] -11 0 -.names [375] [828] [486] [336] -111 0 -.names [772] [374] [337] -11 0 -.names [733] [424] [338] -11 0 -.names [382] [977] [296] [512] [339] -1111 0 -.names [624] [388] [340] -11 0 -.names [551] [388] [341] -11 0 -.names [384] [694] \dat_o_reg[6]_in -11 0 -.names [577] [388] [343] -11 0 -.names \dat_o_reg[0] dat_o[0] -1 1 -.names wcol_reg [345] -0 1 -.names \dat_o_reg[7] dat_o[7] -1 1 -.names \dat_o_reg[4] dat_o[4] -1 1 -.names [818] [570] [388] [348] -01- 1 -1-1 1 -.names [514] [388] [349] -11 0 -.names [678] [388] [350] -11 0 -.names [894] [877] [388] [351] -01- 1 -1-1 1 -.names [494] [533] [375] \clkcnt_reg[11]_in -11- 0 ---1 0 -.names [749] [388] [353] -11 0 -.names [536] [388] [354] -11 0 -.names [387] [423] [355] -11 0 -.names [707] [873] [442] [356] -01- 1 -1-1 1 -.names [264] mosi_o [441] [357] -01- 1 -1-1 1 -.names miso_i [265] [445] [358] -01- 1 -1-1 1 -.names [265] [266] [447] [359] -01- 1 -1-1 1 -.names [266] [260] [445] [360] -01- 1 -1-1 1 -.names [260] [261] [447] [361] -01- 1 -1-1 1 -.names [261] [262] [446] [362] -01- 1 -1-1 1 -.names [262] [263] [445] [363] -01- 1 -1-1 1 -.names [263] [264] [446] [364] -01- 1 -1-1 1 -.names [407] [794] [365] -11 0 -.names [690] [547] [413] \dat_o_reg[1]_in -111 0 -.names [817] [412] [767] wfifo_gb_reg_in -11- 0 ---1 0 -.names [408] [691] \dat_o_reg[2]_in -11 0 -.names [409] [638] \dat_o_reg[3]_in -11 0 -.names [449] [388] [370] -11 0 -.names [382] [371] -0 1 -.names [386] [978] [372] -11 0 -.names [679] [869] [444] [373] -01- 1 -1-1 1 -.names [388] [374] -0 1 -.names [388] [375] -0 1 -.names [448] [637] \dat_o_reg[7]_in -11 0 -.names [639] [450] \dat_o_reg[0]_in -11 0 -.names [686] [798] [439] wcol_reg_in -11- 0 ---1 0 -.names \rfifo_rp_reg[1] [379] -1 1 -.names \wfifo_rp_reg[1] [380] -1 1 -.names [454] [860] [692] \dat_o_reg[4]_in -00- 1 ---0 1 -.names [407] [382] -0 1 -.names [455] [860] [693] \dat_o_reg[5]_in -00- 1 ---0 1 -.names [456] [795] [849] [512] [384] -11-- 0 ---11 0 -.names \rfifo_rp_reg[0] [385] -1 1 -.names [832] [866] [525] [386] -01- 1 -1-1 1 -.names [482] [897] [387] -11 0 -.names [424] [388] -0 1 -.names \wfifo_mem_reg[2][5] [389] -1 1 -.names \wfifo_mem_reg[1][7] [390] -1 1 -.names \wfifo_mem_reg[2][1] [391] -1 1 -.names \wfifo_mem_reg[1][5] [392] -1 1 -.names \wfifo_wp_reg[1] [393] -1 1 -.names \wfifo_wp_reg[0] [394] -1 1 -.names \wfifo_mem_reg[1][1] [395] -1 1 -.names \wfifo_mem_reg[1][2] [396] -1 1 -.names \wfifo_mem_reg[1][3] [397] -1 1 -.names \wfifo_mem_reg[1][4] [398] -1 1 -.names \wfifo_mem_reg[1][6] [399] -1 1 -.names \wfifo_mem_reg[1][8] [400] -1 1 -.names \wfifo_mem_reg[2][2] [401] -1 1 -.names \wfifo_mem_reg[2][3] [402] -1 1 -.names \wfifo_mem_reg[2][4] [403] -1 1 -.names \wfifo_mem_reg[2][6] [404] -1 1 -.names \wfifo_mem_reg[2][7] [405] -1 1 -.names \wfifo_mem_reg[2][8] [406] -1 1 -.names [441] [407] -0 1 -.names [498] [795] [625] [798] [408] -11-- 0 ---11 0 -.names [499] [795] [626] [798] [409] -11-- 0 ---11 0 -.names \wfifo_mem_reg[0][5] [410] -1 1 -.names [496] [976] [411] -11 0 -.names [773] [552] [732] [412] -111 0 -.names [497] [795] [413] -11 0 -.names [501] [976] [414] -11 0 -.names [502] [976] [415] -11 0 -.names [503] [976] [416] -11 0 -.names [504] [976] [417] -11 0 -.names [505] [976] [418] -11 0 -.names [506] [976] [419] -11 0 -.names [507] [976] [420] -11 0 -.names \wfifo_mem_reg[3][5] [421] -1 1 -.names [526] [830] \wfifo_rp_reg[1]_in -00 1 -.names [524] sck_o [423] -11 0 -.names [753] [525] [424] -11 0 -.names \wfifo_mem_reg[3][1] [425] -1 1 -.names \wfifo_mem_reg[0][8] [426] -1 1 -.names \wfifo_mem_reg[0][1] [427] -1 1 -.names \wfifo_mem_reg[0][2] [428] -1 1 -.names \wfifo_mem_reg[0][3] [429] -1 1 -.names \wfifo_mem_reg[0][4] [430] -1 1 -.names \wfifo_mem_reg[0][7] [431] -1 1 -.names \wfifo_mem_reg[0][6] [432] -1 1 -.names \wfifo_mem_reg[3][2] [433] -1 1 -.names \wfifo_mem_reg[3][3] [434] -1 1 -.names \wfifo_mem_reg[3][4] [435] -1 1 -.names \wfifo_mem_reg[3][6] [436] -1 1 -.names \wfifo_mem_reg[3][7] [437] -1 1 -.names \wfifo_mem_reg[3][8] [438] -1 1 -.names [529] [891] [831] [439] -00- 1 ---0 1 -.names [491] [830] \rfifo_rp_reg[1]_in -00 1 -.names [482] [441] -0 1 -.names [482] [442] -0 1 -.names [482] [443] -0 1 -.names [482] [444] -0 1 -.names [483] [445] -0 1 -.names [483] [446] -0 1 -.names [483] [447] -0 1 -.names [534] [795] [826] [473] [448] -11-- 0 ---11 0 -.names [575] [917] [489] [449] -00- 1 ---0 1 -.names [535] [795] [757] [630] [450] -11-- 0 ---11 0 -.names [395] [557] [628] \wfifo_mem_reg[1][1]_in -01- 1 -1-1 1 -.names [546] [512] \wfifo_wp_reg[0]_in -11 1 -.names [585] [586] [971] \wfifo_wp_reg[1]_in -11- 0 ---1 0 -.names [864] [197] [549] [454] -11- 0 ---1 0 -.names [864] [198] [550] [455] -11- 0 ---1 0 -.names [785] [710] [589] [456] -111 0 -.names [400] [558] [628] \wfifo_mem_reg[1][8]_in -01- 1 -1-1 1 -.names \sper_reg[5] [458] -1 1 -.names wfre_reg [459] -1 1 -.names \sper_reg[0] [460] -1 1 -.names \sper_reg[1] [461] -1 1 -.names \sper_reg[2] [462] -1 1 -.names \sper_reg[3] [463] -1 1 -.names \sper_reg[4] [464] -1 1 -.names \sper_reg[6] [465] -1 1 -.names [397] [568] [628] \wfifo_mem_reg[1][3]_in -01- 1 -1-1 1 -.names [398] [555] [628] \wfifo_mem_reg[1][4]_in -01- 1 -1-1 1 -.names [392] [567] [628] \wfifo_mem_reg[1][5]_in -01- 1 -1-1 1 -.names [399] [556] [628] \wfifo_mem_reg[1][6]_in -01- 1 -1-1 1 -.names [390] [554] [628] \wfifo_mem_reg[1][7]_in -01- 1 -1-1 1 -.names [402] [564] [628] \wfifo_mem_reg[2][3]_in -01- 1 -1-1 1 -.names [403] [560] [628] \wfifo_mem_reg[2][4]_in -01- 1 -1-1 1 -.names \sper_reg[7] [473] -1 1 -.names [389] [566] [628] \wfifo_mem_reg[2][5]_in -01- 1 -1-1 1 -.names [405] [565] [628] \wfifo_mem_reg[2][7]_in -01- 1 -1-1 1 -.names [396] [553] [628] \wfifo_mem_reg[1][2]_in -01- 1 -1-1 1 -.names [406] [562] [628] \wfifo_mem_reg[2][8]_in -01- 1 -1-1 1 -.names [401] [559] [628] \wfifo_mem_reg[2][2]_in -01- 1 -1-1 1 -.names [404] [561] [628] \wfifo_mem_reg[2][6]_in -01- 1 -1-1 1 -.names [391] [563] [628] \wfifo_mem_reg[2][1]_in -01- 1 -1-1 1 -.names [571] [572] [830] \rfifo_rp_reg[0]_in -11- 0 ---1 0 -.names [524] [482] -0 1 -.names [525] [483] -0 1 -.names \spcr_reg[7] [484] -1 1 -.names \spcr_reg[5] [485] -1 1 -.names \spcr_reg[0] [486] -1 1 -.names [427] [611] [628] \wfifo_mem_reg[0][1]_in -01- 1 -1-1 1 -.names \spcr_reg[2] [488] -1 1 -.names [575] [917] [489] -11 0 -.names [432] [600] [628] \wfifo_mem_reg[0][6]_in -01- 1 -1-1 1 -.names [682] [880] [576] [491] -11- 0 ---1 0 -.names [573] [623] [492] -11 0 -.names [429] [606] [628] \wfifo_mem_reg[0][3]_in -01- 1 -1-1 1 -.names [569] [870] [494] -11 0 -.names [410] [607] [628] \wfifo_mem_reg[0][5]_in -01- 1 -1-1 1 -.names [670] [616] [631] [496] -111 0 -.names [783] [668] [632] [497] -111 0 -.names [755] [673] [633] [498] -111 0 -.names [808] [754] [634] [499] -111 0 -.names \spcr_reg[4] [500] -1 1 -.names [671] [719] [590] [501] -111 0 -.names [674] [618] [591] [502] -111 0 -.names [669] [734] [592] [503] -111 0 -.names [667] [619] [593] [504] -111 0 -.names [683] [620] [594] [505] -111 0 -.names [675] [614] [595] [506] -111 0 -.names [665] [621] [596] [507] -111 0 -.names [435] [598] [628] \wfifo_mem_reg[3][4]_in -01- 1 -1-1 1 -.names [426] [603] [628] \wfifo_mem_reg[0][8]_in -01- 1 -1-1 1 -.names \spcr_reg[1] [510] -1 1 -.names \spcr_reg[3] [511] -1 1 -.names \spcr_reg[6] [512] -1 1 -.names \wfifo_rp_reg[0] [513] -1 1 -.names [871] [615] [514] -01 1 -10 1 -.names [434] [602] [628] \wfifo_mem_reg[3][3]_in -01- 1 -1-1 1 -.names [430] [599] [628] \wfifo_mem_reg[0][4]_in -01- 1 -1-1 1 -.names [431] [601] [628] \wfifo_mem_reg[0][7]_in -01- 1 -1-1 1 -.names [425] [608] [628] \wfifo_mem_reg[3][1]_in -01- 1 -1-1 1 -.names [433] [612] [628] \wfifo_mem_reg[3][2]_in -01- 1 -1-1 1 -.names [436] [610] [628] \wfifo_mem_reg[3][6]_in -01- 1 -1-1 1 -.names [437] [604] [628] \wfifo_mem_reg[3][7]_in -01- 1 -1-1 1 -.names [438] [609] [628] \wfifo_mem_reg[3][8]_in -01- 1 -1-1 1 -.names [421] [605] [628] \wfifo_mem_reg[3][5]_in -01- 1 -1-1 1 -.names [548] [524] -0 1 -.names [548] [525] -0 1 -.names [622] [459] [907] [879] [526] -11-- 0 ---11 0 -.names [428] [597] [628] \wfifo_mem_reg[0][2]_in -01- 1 -1-1 1 -.names [949] [866] [765] [528] -00- 1 ---0 1 -.names [626] [732] [529] -11 1 -.names [731] [927] [928] [530] -111 0 -.names [801] [627] [531] -11 0 -.names [617] [625] wfre_reg_in -00 1 -.names [948] [766] [727] [823] [533] -1111 0 -.names [786] [666] [696] [534] -111 0 -.names [784] [672] [695] [535] -111 0 -.names [867] [688] [536] -01 1 -10 1 -.names [922] [916] [680] [537] -01- 1 -1-1 1 -.names [656] [460] [708] \sper_reg[0]_in -01- 1 -1-1 1 -.names [657] [461] [708] \sper_reg[1]_in -01- 1 -1-1 1 -.names [658] [462] [708] \sper_reg[2]_in -01- 1 -1-1 1 -.names [659] [463] [708] \sper_reg[3]_in -01- 1 -1-1 1 -.names [660] [464] [708] \sper_reg[4]_in -01- 1 -1-1 1 -.names [661] [458] [708] \sper_reg[5]_in -01- 1 -1-1 1 -.names [662] [465] [708] \sper_reg[6]_in -01- 1 -1-1 1 -.names [663] [473] [708] \sper_reg[7]_in -01- 1 -1-1 1 -.names [881] [732] [546] -01 1 -10 1 -.names [630] [163] [798] [547] -111 0 -.names [939] [548] -0 1 -.names [751] [635] [549] -11 0 -.names [750] [636] [550] -11 0 -.names [725] [854] [613] [551] -00- 1 ---0 1 -.names [721] [879] [629] [552] -00- 1 ---0 1 -.names dat_i[1] [396] [723] [553] -01- 1 -1-1 1 -.names dat_i[6] [390] [723] [554] -01- 1 -1-1 1 -.names dat_i[3] [398] [790] [555] -01- 1 -1-1 1 -.names dat_i[5] [399] [790] [556] -01- 1 -1-1 1 -.names dat_i[0] [395] [723] [557] -01- 1 -1-1 1 -.names dat_i[7] [400] [790] [558] -01- 1 -1-1 1 -.names dat_i[1] [401] [724] [559] -01- 1 -1-1 1 -.names dat_i[3] [403] [724] [560] -01- 1 -1-1 1 -.names dat_i[5] [404] [793] [561] -01- 1 -1-1 1 -.names dat_i[7] [406] [793] [562] -01- 1 -1-1 1 -.names dat_i[0] [391] [724] [563] -01- 1 -1-1 1 -.names dat_i[2] [402] [793] [564] -01- 1 -1-1 1 -.names dat_i[6] [405] [724] [565] -01- 1 -1-1 1 -.names dat_i[4] [389] [793] [566] -01- 1 -1-1 1 -.names dat_i[4] [392] [723] [567] -01- 1 -1-1 1 -.names dat_i[2] [397] [790] [568] -01- 1 -1-1 1 -.names [766] [823] [727] [569] -111 0 -.names [874] [811] [570] -01 1 -10 1 -.names [682] [884] [571] -11 0 -.names [682] [884] [572] -00 0 -.names [949] [788] [573] -11 0 -.names [682] [163] [574] -11 0 -.names [688] [862] [868] [863] [575] -1111 0 -.names [822] [820] [682] [576] -11- 0 ---1 0 -.names [878] [727] [577] -01 1 -10 1 -.names [703] [486] [708] \spcr_reg[0]_in -01- 1 -1-1 1 -.names [738] [510] [708] \spcr_reg[1]_in -01- 1 -1-1 1 -.names [739] [488] [708] \spcr_reg[2]_in -01- 1 -1-1 1 -.names [740] [511] [708] \spcr_reg[3]_in -01- 1 -1-1 1 -.names [741] [485] [708] \spcr_reg[5]_in -01- 1 -1-1 1 -.names [704] [836] [708] \spcr_reg[6]_in -01- 1 -1-1 1 -.names [742] [484] [708] \spcr_reg[7]_in -01- 1 -1-1 1 -.names [687] [872] [585] -11 0 -.names [721] [732] [586] -11 0 -.names [689] [500] \spcr_reg[4]_in -00 0 -.names [677] [831] \wfifo_rp_reg[0]_in -11 1 -.names [827] [192] [664] [589] -11- 0 ---1 0 -.names [764] [425] [395] [763] [590] -11-- 0 ---11 0 -.names [764] [433] [718] [591] -11- 0 ---1 0 -.names [764] [434] [397] [763] [592] -11-- 0 ---11 0 -.names [764] [435] [712] [593] -11- 0 ---1 0 -.names [764] [421] [716] [594] -11- 0 ---1 0 -.names [764] [436] [709] [595] -11- 0 ---1 0 -.names [764] [437] [720] [596] -11- 0 ---1 0 -.names [428] dat_i[1] [769] [597] -01- 1 -1-1 1 -.names dat_i[3] [435] [768] [598] -01- 1 -1-1 1 -.names [430] dat_i[3] [769] [599] -01- 1 -1-1 1 -.names [432] dat_i[5] [769] [600] -01- 1 -1-1 1 -.names [431] dat_i[6] [769] [601] -01- 1 -1-1 1 -.names dat_i[2] [434] [768] [602] -01- 1 -1-1 1 -.names [426] dat_i[7] [769] [603] -01- 1 -1-1 1 -.names dat_i[6] [437] [768] [604] -01- 1 -1-1 1 -.names dat_i[4] [421] [768] [605] -01- 1 -1-1 1 -.names [429] dat_i[2] [769] [606] -01- 1 -1-1 1 -.names [410] dat_i[4] [769] [607] -01- 1 -1-1 1 -.names dat_i[0] [425] [768] [608] -01- 1 -1-1 1 -.names dat_i[7] [438] [768] [609] -01- 1 -1-1 1 -.names dat_i[5] [436] [768] [610] -01- 1 -1-1 1 -.names [427] dat_i[0] [769] [611] -01- 1 -1-1 1 -.names dat_i[1] [433] [768] [612] -01- 1 -1-1 1 -.names [725] [854] [613] -11 0 -.names [399] [763] [614] -11 0 -.names [713] [725] [615] -00 1 -.names [400] [763] [616] -11 0 -.names [859] [975] [617] -00 0 -.names [396] [763] [618] -11 0 -.names [398] [763] [619] -11 0 -.names [392] [763] [620] -11 0 -.names [390] [763] [621] -11 0 -.names [789] [763] [622] -00 0 -.names [511] [950] [953] [954] [623] -1111 0 -.names [681] [624] -0 1 -.names [949] [625] -0 1 -.names [684] [626] -0 1 -.names [798] dat_i[7] [752] [627] -111 0 -.names [687] [628] -0 1 -.names [721] [879] [629] -11 0 -.names [803] [722] [630] -00 1 -.names [764] [438] [730] [631] -11- 0 ---1 0 -.names [827] [187] [717] [632] -11- 0 ---1 0 -.names [864] [200] [729] [633] -11- 0 ---1 0 -.names [178] [792] [714] [634] -11- 0 ---1 0 -.names [179] [792] [715] [635] -11- 0 ---1 0 -.names [180] [792] [711] [636] -11- 0 ---1 0 -.names [849] [484] [166] [798] [637] -11-- 0 ---11 0 -.names [511] [849] [463] [826] [638] -11-- 0 ---11 0 -.names [486] [849] [460] [826] [639] -11-- 0 ---11 0 -.names [263] [172] [845] [640] -01- 1 -1-1 1 -.names [264] [173] [845] [641] -01- 1 -1-1 1 -.names [262] [171] [791] [642] -01- 1 -1-1 1 -.names [264] [181] [841] [643] -01- 1 -1-1 1 -.names [266] [176] [841] [644] -01- 1 -1-1 1 -.names [262] [179] [841] [645] -01- 1 -1-1 1 -.names [260] [177] [841] [646] -01- 1 -1-1 1 -.names [261] [178] [841] [647] -01- 1 -1-1 1 -.names [265] [175] [841] [648] -01- 1 -1-1 1 -.names [265] [183] [791] [649] -01- 1 -1-1 1 -.names mosi_o [174] [845] [650] -01- 1 -1-1 1 -.names mosi_o [182] [841] [651] -01- 1 -1-1 1 -.names [261] [170] [791] [652] -01- 1 -1-1 1 -.names [266] [184] [845] [653] -01- 1 -1-1 1 -.names [263] [180] [841] [654] -01- 1 -1-1 1 -.names [260] [185] [791] [655] -01- 1 -1-1 1 -.names [460] dat_i[0] [826] [656] -01- 1 -1-1 1 -.names [461] dat_i[1] [826] [657] -01- 1 -1-1 1 -.names [462] dat_i[2] [826] [658] -01- 1 -1-1 1 -.names [463] dat_i[3] [826] [659] -01- 1 -1-1 1 -.names [464] dat_i[4] [826] [660] -01- 1 -1-1 1 -.names [458] dat_i[5] [826] [661] -01- 1 -1-1 1 -.names [465] dat_i[6] [826] [662] -01- 1 -1-1 1 -.names [473] dat_i[7] [826] [663] -01- 1 -1-1 1 -.names [899] [822] [664] -00 1 -.names [770] [431] [665] -11 0 -.names [174] [797] [666] -11 0 -.names [770] [430] [667] -11 0 -.names [184] [797] [668] -11 0 -.names [770] [429] [669] -11 0 -.names [770] [426] [670] -11 0 -.names [770] [427] [671] -11 0 -.names [183] [797] [672] -11 0 -.names [185] [797] [673] -11 0 -.names [770] [428] [674] -11 0 -.names [770] [432] [675] -11 0 -.names ack_o_reg ack_o -1 1 -.names [459] [855] [677] -01 1 -10 1 -.names [726] [678] -0 1 -.names [728] [679] -0 1 -.names [942] [774] [680] -11 0 -.names [812] [915] [774] [681] -11- 0 ---1 0 -.names [858] [901] [804] [682] -111 0 -.names [770] [410] [683] -11 0 -.names [950] [954] [326] [684] -111 0 -.names [880] [913] [787] [685] -01- 1 -1-1 1 -.names dat_i[6] [752] [686] -11 1 -.names [732] [687] -0 1 -.names [847] [918] [688] -00 1 -.names [849] [752] [689] -11 1 -.names [510] [849] [461] [826] [690] -11-- 0 ---11 0 -.names [488] [849] [462] [826] [691] -11-- 0 ---11 0 -.names [500] [849] [464] [826] [692] -11-- 0 ---11 0 -.names [485] [849] [458] [826] [693] -11-- 0 ---11 0 -.names [826] [465] [891] [798] [694] -11-- 0 ---11 0 -.names [827] [186] [175] [792] [695] -11-- 0 ---11 0 -.names [827] [193] [182] [792] [696] -11-- 0 ---11 0 -.names [261] [189] [825] [697] -01- 1 -1-1 1 -.names [266] [187] [825] [698] -01- 1 -1-1 1 -.names [263] [191] [825] [699] -01- 1 -1-1 1 -.names [264] [192] [825] [700] -01- 1 -1-1 1 -.names [262] [190] [825] [701] -01- 1 -1-1 1 -.names mosi_o [193] [825] [702] -01- 1 -1-1 1 -.names [894] [849] [782] [703] -00- 1 ---0 1 -.names [849] [844] [780] [704] -00- 1 ---0 1 -.names [265] [186] [825] [705] -01- 1 -1-1 1 -.names [260] [188] [825] [706] -01- 1 -1-1 1 -.names [759] [707] -0 1 -.names [752] [708] -0 1 -.names [404] [789] [709] -11 1 -.names [181] [792] [710] -11 0 -.names [172] [797] [711] -11 1 -.names [403] [789] [712] -11 1 -.names [823] [802] [713] -11 0 -.names [170] [797] [714] -11 1 -.names [171] [797] [715] -11 1 -.names [389] [789] [716] -11 1 -.names [176] [792] [717] -11 1 -.names [401] [789] [718] -11 1 -.names [391] [789] [719] -11 0 -.names [405] [789] [720] -11 1 -.names [793] [790] [721] -11 0 -.names [884] [882] [807] [722] -11- 0 ---1 0 -.names [761] [723] -0 1 -.names [762] [724] -0 1 -.names [848] [846] [919] [725] -111 0 -.names [813] [812] [726] -11 1 -.names [779] [811] [727] -00 1 -.names [839] [869] [778] [728] -11- 0 ---1 0 -.names [177] [792] [729] -11 1 -.names [406] [789] [730] -11 1 -.names [511] [897] [832] [731] -01- 1 -1-1 1 -.names [777] [804] [732] -11 1 -.names [781] [824] [733] -11 0 -.names [402] [789] [734] -11 0 -.names [775] [735] -0 1 -.names [197] [262] [856] [736] -01- 1 -1-1 1 -.names [198] [263] [856] [737] -01- 1 -1-1 1 -.names [510] dat_i[1] [849] [738] -01- 1 -1-1 1 -.names [488] dat_i[2] [849] [739] -01- 1 -1-1 1 -.names [511] dat_i[3] [849] [740] -01- 1 -1-1 1 -.names [485] dat_i[5] [849] [741] -01- 1 -1-1 1 -.names [484] dat_i[7] [849] [742] -01- 1 -1-1 1 -.names [194] [265] [856] [743] -01- 1 -1-1 1 -.names [195] [266] [856] [744] -01- 1 -1-1 1 -.names [200] [260] [856] [745] -01- 1 -1-1 1 -.names [196] [261] [856] [746] -01- 1 -1-1 1 -.names [201] [264] [856] [747] -01- 1 -1-1 1 -.names [199] mosi_o [856] [748] -01- 1 -1-1 1 -.names [810] [749] -0 1 -.names [827] [191] [750] -11 0 -.names [827] [190] [751] -11 0 -.names [777] [752] -1 1 -.names [844] [765] [753] -00 1 -.names [827] [189] [754] -11 0 -.names [827] [188] [755] -11 0 -.names [865] ack_o ack_o_reg_in -00 1 -.names [163] [816] [757] -00 1 -.names [821] [885] [758] -00 0 -.names [254] [873] [829] [759] -11- 0 ---1 0 -.names [787] [760] -0 1 -.names [790] [761] -0 1 -.names [793] [762] -0 1 -.names [796] [763] -0 1 -.names [799] [764] -1 1 -.names [974] [765] -0 1 -.names [878] [871] [766] -00 1 -.names rst_i [512] [767] -11 0 -.names [881] [872] [768] -11 0 -.names [800] [769] -0 1 -.names [890] [893] [770] -11 1 -.names [814] [771] -0 1 -.names [837] [824] [772] -11 0 -.names [954] [773] -0 1 -.names [811] [774] -0 1 -.names [852] [486] [461] [775] -11- 0 ---1 0 -.names [465] [876] [834] [776] -11- 0 ---1 0 -.names [858] we_i [777] -11 1 -.names [832] [778] -0 1 -.names [848] [868] [779] -11 0 -.names [849] dat_i[6] [780] -11 0 -.names [843] [461] [781] -00 1 -.names [849] dat_i[0] [782] -11 0 -.names [864] [195] [783] -11 0 -.names [864] [194] [784] -11 0 -.names [864] [201] [785] -11 0 -.names [864] [199] [786] -11 0 -.names [841] [845] [787] -11 0 -.names [861] [842] [788] -11 0 -.names [819] [789] -0 1 -.names [881] [908] [790] -11 0 -.names [835] [791] -0 1 -.names [820] [792] -0 1 -.names [912] [872] [793] -11 0 -.names [821] [794] -0 1 -.names [860] [795] -0 1 -.names [855] [893] [796] -11 0 -.names [822] [797] -0 1 -.names [816] [798] -0 1 -.names [890] [893] [799] -00 1 -.names [912] [908] [800] -11 0 -.names [906] [859] [801] -00 1 -.names [878] [854] [802] -00 1 -.names [880] [168] [803] -01 1 -10 1 -.names [860] [892] [804] -00 1 -.names [857] [510] [805] -00 0 -.names [852] [461] [806] -00 0 -.names [904] [895] [807] -11 1 -.names [864] [196] [808] -11 0 -.names [902] [844] [809] -00 1 -.names [883] [877] [846] [810] -11- 0 ---1 0 -.names [965] [957] [886] [958] [811] -1111 0 -.names [846] [957] [812] -11 0 -.names [846] [957] [813] -00 0 -.names [836] [814] -0 1 -.names [885] [296] [815] -11 0 -.names [910] adr_i[1] [816] -00 0 -.names [907] [326] [817] -11 0 -.names [843] [818] -0 1 -.names [890] [879] [819] -11 0 -.names [904] [379] [820] -11 0 -.names [251] [914] [821] -11 0 -.names [884] [913] [822] -11 0 -.names [920] [823] -0 1 -.names [486] [510] [824] -11 0 -.names [882] [168] [825] -11 0 -.names adr_i[0] adr_i[1] [826] -11 1 -.names [850] [827] -0 1 -.names [510] [461] [828] -11 1 -.names [839] [829] -0 1 -.names [512] [830] -0 1 -.names [844] [831] -0 1 -.names [979] [909] [911] [832] -111 0 -.names inta_o_reg inta_o -1 1 -.names [876] [165] [834] -00 1 -.names [845] [835] -0 1 -.names [971] [836] -0 1 -.names [857] [837] -0 1 -.names [894] [888] [838] -00 0 -.names [979] [909] [839] -11 0 -.names [893] [908] [840] -11 0 -.names [895] [168] [841] -11 0 -.names [898] [511] [842] -11 0 -.names [894] [460] [843] -11 1 -.names [512] [844] -0 1 -.names [169] [889] [845] -11 0 -.names [958] [886] [846] -11 1 -.names [925] [886] [847] -11 0 -.names [926] [925] [848] -11 1 -.names [910] [887] [849] -11 1 -.names [904] [913] [850] -00 0 -.names [893] [908] [851] -00 0 -.names [905] [900] [852] -00 1 -.names [876] [853] -0 1 -.names [868] [854] -0 1 -.names [890] [855] -0 1 -.names [895] [889] [856] -11 1 -.names [900] [888] [857] -11 0 -.names [865] [858] -0 1 -.names [512] [859] -0 1 -.names [910] adr_i[1] [860] -11 0 -.names [488] [897] [861] -11 0 -.names [878] [862] -0 1 -.names [926] [922] [863] -11 1 -.names [904] [913] [864] -11 1 -.names cyc_i stb_i [865] -11 0 -.names [885] [866] -0 1 -.names [926] [867] -0 1 -.names [924] [868] -1 1 -.names [911] [869] -0 1 -.names [948] [870] -0 1 -.names [947] [871] -0 1 -.names [908] [872] -0 1 -.names [909] [873] -0 1 -.names [925] [874] -0 1 -.names [484] [166] inta_o_reg_in -11 1 -.names [165] [162] [876] -00 1 -.names [886] [877] -0 1 -.names [959] [878] -0 1 -.names [893] [879] -0 1 -.names [913] [880] -0 1 -.names [912] [881] -0 1 -.names [895] [882] -0 1 -.names [958] [883] -0 1 -.names [904] [884] -0 1 -.names [251] [885] -0 1 -.names [293] [886] -0 1 -.names adr_i[1] [887] -0 1 -.names [461] [888] -0 1 -.names [168] [889] -0 1 -.names [513] [890] -0 1 -.names [345] [891] -0 1 -.names ack_o [892] -0 1 -.names [380] [893] -0 1 -.names [486] [894] -0 1 -.names [169] [895] -0 1 -.names [296] [896] -0 1 -.names sck_o [897] -0 1 -.names [488] [898] -0 1 -.names [173] [899] -0 1 -.names [460] [900] -0 1 -.names we_i [901] -0 1 -.names [162] [902] -0 1 -.names [473] [903] -0 1 -.names [385] [904] -0 1 -.names [510] [905] -0 1 -.names [166] [906] -0 1 -.names [459] [907] -0 1 -.names [393] [908] -0 1 -.names [259] [909] -0 1 -.names adr_i[0] [910] -0 1 -.names [256] [911] -0 1 -.names [394] [912] -0 1 -.names [379] [913] -0 1 -.names [296] [914] -0 1 -.names [965] [915] -0 1 -.names [922] [916] -0 1 -.names [921] [917] -0 1 -.names [919] [958] [918] -11 0 -.names [943] [919] -0 1 -.names [921] [922] [920] -11 0 -.names [291] [921] -0 1 -.names [257] [922] -0 1 -.names [295] [923] -0 1 -.names [290] [924] -0 1 -.names [960] [925] -1 1 -.names [923] [926] -1 1 -.names [929] [930] [927] -00 1 -.names [944] [943] [928] -00 1 -.names [940] [929] -0 1 -.names [942] [930] -0 1 -.names [257] [291] [931] -00 1 -.names [933] [934] [938] [932] -111 0 -.names [355] [794] [933] -11 0 -.names [935] [936] [934] -00 1 -.names [897] [815] [935] -00 1 -.names [423] [530] [937] [936] -11- 0 ---1 0 -.names [978] [937] -0 1 -.names [492] [976] [938] -11 0 -.names [940] [961] [955] [939] -111 0 -.names [945] [941] [940] -00 1 -.names [931] [941] -0 1 -.names [956] [966] [942] -00 1 -.names [965] [957] [943] -11 0 -.names [964] [958] [944] -11 0 -.names [946] [947] [945] -11 0 -.names [306] [946] -0 1 -.names [286] [947] -0 1 -.names [946] [948] -1 1 -.names [950] [951] [953] [949] -111 0 -.names [851] [840] [950] -11 0 -.names [912] [890] [952] [951] -00- 1 ---0 1 -.names [912] [890] [952] -11 0 -.names [326] [953] -0 1 -.names [951] [954] -1 1 -.names [980] [956] [955] -00 1 -.names [924] [923] [956] -11 0 -.names [292] [957] -0 1 -.names [294] [958] -0 1 -.names [287] [959] -0 1 -.names [288] [960] -0 1 -.names [962] [963] [961] -00 1 -.names [960] [959] [962] -11 0 -.names [964] [965] [963] -11 0 -.names [293] [964] -0 1 -.names [289] [965] -0 1 -.names [960] [959] [966] -11 0 -.names [968] [969] [970] \bcnt_reg[0]_in -00- 1 ---0 1 -.names [254] [979] [443] [968] -01- 1 -1-1 1 -.names [296] [512] [251] [969] -111 0 -.names [971] [972] [970] -00 0 -.names [512] [971] -0 1 -.names [973] [254] [765] [972] -11- 0 ---1 0 -.names [821] [815] [973] -11 0 -.names [896] [885] [974] -11 0 -.names [765] [975] -0 1 -.names [974] [976] -0 1 -.names [978] [977] -1 1 -.names [885] [914] [978] -00 1 -.names [254] [979] -0 1 -.names [981] [982] [980] -11 0 -.names [292] [981] -0 1 -.names [294] [982] -0 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/sqrt8ml.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/sqrt8ml.blif deleted file mode 100644 index 8ed9ca00c..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/sqrt8ml.blif +++ /dev/null @@ -1,637 +0,0 @@ -# -# Written by e2fmt Tue Mar 31 16:20:04 1998 -############################################ -.model top -.inputs v_6_ v_7_ v_4_ v_5_ v_2_ v_3_ v_0_ v_1_ -.outputs sqrt_3_ sqrt_2_ sqrt_1_ sqrt_0_ -# connect ports to nets with different names -.names v_6_ n_n74 -1 1 -.names n_n81 sqrt_3_ -1 1 -.names v_7_ n_n75 -1 1 -.names n_n79 sqrt_2_ -1 1 -.names v_4_ n_n83 -1 1 -.names n_n77 sqrt_1_ -1 1 -.names v_5_ n_n73 -1 1 -.names n_n72 sqrt_0_ -1 1 -.names v_2_ n_n80 -1 1 -.names v_3_ n_n82 -1 1 -.names v_0_ n_n76 -1 1 -.names v_1_ n_n78 -1 1 -# instance g_g159 -.names n_n146 n_n21 n_n149 n_n145 -1-0 1 --11 1 -# instance g_g148 -.names n_n120 n_n93 n_n147 -10 1 -01 1 -# instance g_g137 -.names n_n20 n_n20 n_n21 n_n95 -1-0 1 --11 1 -# instance g_g126 -.names n_n32 n_n6 n_tmp34 -10 1 -01 1 -# instance g_g115 -.names n_n78 n_n66 n_n15 -1- 1 --1 1 -# instance g_g104 -.names n_n21 n_n21 n_n72 n_n77 -1-0 1 --11 1 -# instance g_g158 -.names n_n29 n_n1 n_tmp74 -10 1 -01 1 -# instance g_g149 -.names n_n114 n_n21 n_n149 -10 1 -01 1 -# instance g_g136 -.names n_n124 n_tmp70 n_n20 n_n126 -1-0 1 --11 1 -# instance g_g127 -.names n_n4 n_n5 n_tmp36 -10 1 -01 1 -# instance g_g114 -.names n_n92 n_n26 n_n99 -11 1 -# instance g_g105 -.names n_n140 n_n94 n_n142 n_n132 -1-0 1 --11 1 -# instance g_g168 -.names n_n76 n_n76 n_n49 n_n86 -1-0 1 --11 1 -# instance g_g135 -.names n_n117 n_tmp71 n_n20 n_n116 -1-0 1 --11 1 -# instance g_g124 -.names n_n34 n_n8 n_tmp32 -10 1 -01 1 -# instance g_g117 -.names n_n73 n_n64 n_n13 -1- 1 --1 1 -# instance g_g106 -.names n_n141 n_n20 n_n143 n_n140 -1-0 1 --11 1 -# instance g_g169 -.names n_n78 n_tmp36 n_n49 n_n88 -1-0 1 --11 1 -# instance g_g134 -.names n_n123 n_tmp69 n_n20 n_n122 -1-0 1 --11 1 -# instance g_g125 -.names n_n33 n_n7 n_tmp35 -10 1 -01 1 -# instance g_g116 -.names n_n83 n_n65 n_n14 -1- 1 --1 1 -# instance g_g107 -.names n_n116 n_n94 n_n142 -10 1 -01 1 -# instance g_g133 -.names n_n119 n_tmp72 n_n20 n_n121 -1-0 1 --11 1 -# instance g_g122 -.names n_n109 n_n10 n_tmp30 -10 1 -01 1 -# instance g_g111 -.names n_n111 n_n59 n_n17 -1- 1 --1 1 -# instance g_g100 -.names n_n37 n_n52 n_tmp108 -10 1 -01 1 -# instance g_g9 -.names n_n83 n_n9 -0 1 -# instance g_g132 -.names n_n111 n_tmp73 n_n20 n_n110 -1-0 1 --11 1 -# instance g_g123 -.names n_n35 n_n9 n_tmp33 -10 1 -01 1 -# instance g_g110 -.names n_n113 n_n60 n_n18 -1- 1 --1 1 -# instance g_g101 -.names n_n124 n_n49 n_n135 -10 1 -01 1 -# instance g_g131 -.names n_n113 n_tmp74 n_n20 n_n115 -1-0 1 --11 1 -# instance g_g120 -.names n_n74 n_n31 n_n109 -11 1 -# instance g_g113 -.names n_n16 n_n100 n_n101 -11 1 -# instance g_g102 -.names n_n134 n_n49 n_n135 n_n133 -1-0 1 --11 1 -# instance g_g130 -.names n_n88 n_tmp75 n_n20 n_n87 -1-0 1 --11 1 -# instance g_g121 -.names n_n31 n_n74 n_tmp31 -10 1 -01 1 -# instance g_g112 -.names n_n119 n_n27 n_n100 -11 1 -# instance g_g103 -.names n_n95 n_n95 n_n72 n_n79 -1-0 1 --11 1 -# instance g_g162 -.names n_n74 n_tmp31 n_n49 n_n124 -1-0 1 --11 1 -# instance g_g151 -.names n_n129 n_n124 n_n156 -11 1 -# instance g_g140 -.names n_n87 n_tmp114 n_n21 n_n89 -1-0 1 --11 1 -# instance g_g5 -.names n_n78 n_n5 -0 1 -# instance g_g163 -.names n_n75 n_tmp30 n_n49 n_n123 -1-0 1 --11 1 -# instance g_g150 -.names n_n129 n_n124 n_n92 -10 1 -01 1 -# instance g_g141 -.names n_n122 n_tmp108 n_n21 n_n127 -1-0 1 --11 1 -# instance g_g6 -.names n_n82 n_n6 -0 1 -# instance g_g160 -.names n_n28 n_n0 n_tmp73 -10 1 -01 1 -# instance g_g153 -.names n_n27 n_n119 n_tmp72 -10 1 -01 1 -# instance g_g142 -.names n_n126 n_tmp109 n_n21 n_n125 -1-0 1 --11 1 -# instance g_g7 -.names n_n80 n_n7 -0 1 -# instance g_g161 -.names n_n145 n_n95 n_n148 n_n139 -1-0 1 --11 1 -# instance g_g152 -.names n_n139 n_n93 n_n147 n_n138 -1-0 1 --11 1 -# instance g_g143 -.names n_n115 n_tmp113 n_n21 n_n114 -1-0 1 --11 1 -# instance g_g8 -.names n_n73 n_n8 -0 1 -# instance g_g166 -.names n_n80 n_tmp35 n_n49 n_n113 -1-0 1 --11 1 -# instance g_g155 -.names n_n26 n_n92 n_tmp70 -10 1 -01 1 -# instance g_g144 -.names n_n116 n_tmp110 n_n21 n_n118 -1-0 1 --11 1 -# instance g_g119 -.names n_n82 n_n62 n_n11 -1- 1 --1 1 -# instance g_g108 -.names n_n121 n_n20 n_n143 -10 1 -01 1 -# instance g_g1 -.names n_n113 n_n1 -0 1 -# instance g_g167 -.names n_n82 n_tmp34 n_n49 n_n111 -1-0 1 --11 1 -# instance g_g154 -.names n_n100 n_n16 n_tmp71 -10 1 -01 1 -# instance g_g145 -.names n_n110 n_tmp112 n_n21 n_n112 -1-0 1 --11 1 -# instance g_g118 -.names n_n80 n_n63 n_n12 -1- 1 --1 1 -# instance g_g109 -.names n_n88 n_n61 n_n19 -1- 1 --1 1 -# instance g_g2 -.names n_n61 n_n2 -0 1 -# instance g_g164 -.names n_n83 n_tmp33 n_n49 n_n119 -1-0 1 --11 1 -# instance g_g157 -.names n_n2 n_n3 n_tmp75 -10 1 -01 1 -# instance g_g146 -.names n_n121 n_tmp111 n_n21 n_n120 -1-0 1 --11 1 -# instance g_g139 -.names n_n91 n_n91 n_n21 n_n90 -1-0 1 --11 1 -# instance g_g128 -.names n_n49 n_n49 n_n20 n_n94 -1-0 1 --11 1 -# instance g_g3 -.names n_n88 n_n3 -0 1 -# instance g_g165 -.names n_n73 n_tmp32 n_n49 n_n117 -1-0 1 --11 1 -# instance g_g156 -.names n_n25 n_n51 n_tmp69 -10 1 -01 1 -# instance g_g147 -.names n_n112 n_n95 n_n148 -10 1 -01 1 -# instance g_g138 -.names n_n94 n_n94 n_n21 n_n93 -1-0 1 --11 1 -# instance g_g129 -.names n_n86 n_n86 n_n20 n_n91 -1-0 1 --11 1 -# instance g_g4 -.names n_n66 n_n4 -0 1 -# instance g_g94 -.names n_n22 n_n23 n_tmp114 -10 1 -01 1 -# instance g_g83 -.names n_n86 n_n30 n_n61 -11 1 -# instance g_g72 -.names n_n153 n_n102 n_n41 -1- 1 --1 1 -# instance g_g61 -.names n_n52 n_n131 n_n130 -11 1 -# instance g_g50 -.names n_n126 n_n55 -0 1 -# instance g_g95 -.names n_n42 n_n85 n_tmp111 -10 1 -01 1 -# instance g_g82 -.names n_n108 n_n73 n_n31 -1- 1 --1 1 -# instance g_g73 -.names n_n155 n_n87 n_n40 -1- 1 --1 1 -# instance g_g60 -.names n_n53 n_n136 n_n144 -11 1 -# instance g_g51 -.names n_n125 n_n56 -0 1 -# instance g_g96 -.names n_n41 n_n84 n_tmp110 -10 1 -01 1 -# instance g_g81 -.names n_n105 n_n80 n_n32 -1- 1 --1 1 -# instance g_g70 -.names n_n87 n_n68 n_n43 -1- 1 --1 1 -# instance g_g63 -.names n_n117 n_n119 n_n50 -1- 1 --1 1 -# instance g_g52 -.names n_n118 n_n57 -0 1 -# instance g_g97 -.names n_n40 n_n115 n_tmp113 -10 1 -01 1 -# instance g_g80 -.names n_n104 n_n78 n_n33 -1- 1 --1 1 -# instance g_g71 -.names n_n152 n_n110 n_n42 -1- 1 --1 1 -# instance g_g62 -.names n_n51 n_n133 n_n128 -11 1 -# instance g_g53 -.names n_n58 n_n146 -0 1 -# instance g_g0 -.names n_n111 n_n0 -0 1 -# instance g_g98 -.names n_n151 n_n44 n_tmp112 -10 1 -01 1 -# instance g_g43 -.names n_n48 n_n150 -0 1 -# instance g_g32 -.names n_n76 n_n36 -0 1 -# instance g_g21 -.names n_n130 n_n21 -0 1 -# instance g_g10 -.names n_n75 n_n10 -0 1 -# instance g_g99 -.names n_n38 n_n55 n_tmp109 -10 1 -01 1 -# instance g_g42 -.names n_n71 n_n47 -0 1 -# instance g_g33 -.names n_n38 n_n67 -0 1 -# instance g_g20 -.names n_n128 n_n20 -0 1 -# instance g_g11 -.names n_n11 n_n106 -0 1 -# instance g_g41 -.names n_n70 n_n46 -0 1 -# instance g_g30 -.names n_n34 n_n64 -0 1 -# instance g_g23 -.names n_n87 n_n23 -0 1 -# instance g_g12 -.names n_n12 n_n105 -0 1 -# instance g_g40 -.names n_n69 n_n45 -0 1 -# instance g_g31 -.names n_n35 n_n65 -0 1 -# instance g_g22 -.names n_n68 n_n22 -0 1 -# instance g_g13 -.names n_n13 n_n108 -0 1 -# instance g_g69 -.names n_n44 n_n151 n_n152 -11 1 -# instance g_g58 -.names n_n55 n_n132 n_n131 -11 1 -# instance g_g47 -.names n_n122 n_n52 -0 1 -# instance g_g36 -.names n_n41 n_n70 -0 1 -# instance g_g25 -.names n_n28 n_n59 -0 1 -# instance g_g14 -.names n_n14 n_n107 -0 1 -# instance g_g68 -.names n_n115 n_n45 n_n151 -11 1 -# instance g_g59 -.names n_n110 n_n115 n_n54 -1- 1 --1 1 -# instance g_g46 -.names n_n123 n_n51 -0 1 -# instance g_g37 -.names n_n42 n_n71 -0 1 -# instance g_g24 -.names n_n94 n_n24 -0 1 -# instance g_g15 -.names n_n15 n_n104 -0 1 -# instance g_g89 -.names n_n93 n_n93 n_n72 n_n81 -1-0 1 --11 1 -# instance g_g78 -.names n_n106 n_n82 n_n35 -1- 1 --1 1 -# instance g_g45 -.names n_n50 n_n134 -0 1 -# instance g_g34 -.names n_n91 n_n39 -0 1 -# instance g_g27 -.names n_n86 n_n30 -0 1 -# instance g_g16 -.names n_n117 n_n16 -0 1 -# instance g_g88 -.names n_n99 n_n156 n_n25 -1- 1 --1 1 -# instance g_g79 -.names n_n107 n_n83 n_n34 -1- 1 --1 1 -# instance g_g44 -.names n_n49 n_n129 -0 1 -# instance g_g35 -.names n_n40 n_n69 -0 1 -# instance g_g26 -.names n_n29 n_n60 -0 1 -# instance g_g17 -.names n_n17 n_n97 -0 1 -# instance g_g90 -.names n_n24 n_n116 n_n84 -10 1 -01 1 -# instance g_g87 -.names n_n101 n_n117 n_n26 -1- 1 --1 1 -# instance g_g76 -.names n_n150 n_n126 n_n37 -1- 1 --1 1 -# instance g_g65 -.names n_n126 n_n67 n_n48 -1- 1 --1 1 -# instance g_g54 -.names n_n144 n_n72 -0 1 -# instance g_g29 -.names n_n33 n_n63 -0 1 -# instance g_g18 -.names n_n18 n_n96 -0 1 -# instance g_g91 -.names n_n128 n_n121 n_n85 -10 1 -01 1 -# instance g_g86 -.names n_n97 n_n111 n_n27 -1- 1 --1 1 -# instance g_g77 -.names n_n76 n_n36 n_n66 -11 1 -# instance g_g64 -.names n_n75 n_n74 n_n49 -1- 1 --1 1 -# instance g_g55 -.names n_n89 n_n90 n_n58 -1- 1 --1 1 -# instance g_g28 -.names n_n32 n_n62 -0 1 -# instance g_g19 -.names n_n19 n_n98 -0 1 -# instance g_g92 -.names n_n128 n_n121 n_n102 -11 1 -# instance g_g85 -.names n_n96 n_n113 n_n28 -1- 1 --1 1 -# instance g_g74 -.names n_n91 n_n39 n_n68 -11 1 -# instance g_g67 -.names n_n84 n_n46 n_n154 -11 1 -# instance g_g56 -.names n_n57 n_n138 n_n137 -11 1 -# instance g_g49 -.names n_n54 n_n141 -0 1 -# instance g_g38 -.names n_n43 n_n155 -0 1 -# instance g_g93 -.names n_n24 n_n116 n_n103 -11 1 -# instance g_g84 -.names n_n98 n_n88 n_n29 -1- 1 --1 1 -# instance g_g75 -.names n_n154 n_n103 n_n38 -1- 1 --1 1 -# instance g_g66 -.names n_n85 n_n47 n_n153 -11 1 -# instance g_g57 -.names n_n56 n_n137 n_n136 -11 1 -# instance g_g48 -.names n_n127 n_n53 -0 1 -# instance g_g39 -.names n_n110 n_n44 -0 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/ss_pcm.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/ss_pcm.blif deleted file mode 100644 index 81899599d..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/ss_pcm.blif +++ /dev/null @@ -1,1142 +0,0 @@ -# Benchmark "ss_pcm" written by ABC on Mon Aug 29 15:33:12 2005 -.model ss_pcm -.inputs clk rst pcm_clk_i pcm_sync_i pcm_din_i re_i ssel[0] ssel[1] ssel[2] \ - din_i[0] din_i[1] din_i[2] din_i[3] din_i[4] din_i[5] din_i[6] din_i[7] \ - we_i[0] we_i[1] -.outputs pcm_dout_o dout_o[0] dout_o[1] dout_o[2] dout_o[3] dout_o[4] \ - dout_o[5] dout_o[6] dout_o[7] - -.latch \tx_hold_reg_reg[15]_in \tx_hold_reg_reg[15] 2 -.latch \tx_hold_reg_reg[1]_in \tx_hold_reg_reg[1] 2 -.latch \tx_hold_reg_reg[2]_in \tx_hold_reg_reg[2] 2 -.latch \tx_hold_reg_reg[3]_in \tx_hold_reg_reg[3] 2 -.latch \tx_hold_reg_reg[4]_in \tx_hold_reg_reg[4] 2 -.latch \tx_hold_reg_reg[5]_in \tx_hold_reg_reg[5] 2 -.latch \tx_hold_reg_reg[6]_in \tx_hold_reg_reg[6] 2 -.latch \tx_hold_reg_reg[7]_in \tx_hold_reg_reg[7] 2 -.latch \tx_hold_reg_reg[8]_in \tx_hold_reg_reg[8] 2 -.latch \tx_hold_reg_reg[9]_in \tx_hold_reg_reg[9] 2 -.latch \tx_hold_reg_reg[11]_in \tx_hold_reg_reg[11] 2 -.latch \tx_hold_reg_reg[12]_in \tx_hold_reg_reg[12] 2 -.latch \tx_hold_reg_reg[13]_in \tx_hold_reg_reg[13] 2 -.latch \tx_hold_reg_reg[14]_in \tx_hold_reg_reg[14] 2 -.latch \tx_hold_reg_reg[0]_in \tx_hold_reg_reg[0] 2 -.latch tx_go_reg_in tx_go_reg 2 -.latch \tx_hold_reg_reg[10]_in \tx_hold_reg_reg[10] 2 -.latch \rx_reg_reg[13]_in \rx_reg_reg[13] 2 -.latch \rx_reg_reg[14]_in \rx_reg_reg[14] 2 -.latch \rx_reg_reg[15]_in \rx_reg_reg[15] 2 -.latch \rx_reg_reg[1]_in \rx_reg_reg[1] 2 -.latch \rx_reg_reg[2]_in \rx_reg_reg[2] 2 -.latch \rx_reg_reg[3]_in \rx_reg_reg[3] 2 -.latch \rx_reg_reg[4]_in \rx_reg_reg[4] 2 -.latch \rx_reg_reg[5]_in \rx_reg_reg[5] 2 -.latch \rx_reg_reg[6]_in \rx_reg_reg[6] 2 -.latch \rx_reg_reg[7]_in \rx_reg_reg[7] 2 -.latch \rx_reg_reg[8]_in \rx_reg_reg[8] 2 -.latch \rx_reg_reg[9]_in \rx_reg_reg[9] 2 -.latch \rx_reg_reg[0]_in \rx_reg_reg[0] 2 -.latch \rx_reg_reg[12]_in \rx_reg_reg[12] 2 -.latch \rx_reg_reg[10]_in \rx_reg_reg[10] 2 -.latch \rx_reg_reg[11]_in \rx_reg_reg[11] 2 -.latch \tx_cnt_reg[3]_in \tx_cnt_reg[3] 2 -.latch \tx_cnt_reg[2]_in \tx_cnt_reg[2] 2 -.latch \tx_cnt_reg[0]_in \tx_cnt_reg[0] 2 -.latch \tx_cnt_reg[1]_in \tx_cnt_reg[1] 2 -.latch \rx_hold_reg_reg[8]_in \rx_hold_reg_reg[8] 2 -.latch \rx_hold_reg_reg[10]_in \rx_hold_reg_reg[10] 2 -.latch \rx_hold_reg_reg[0]_in \rx_hold_reg_reg[0] 2 -.latch \rx_hold_reg_reg[11]_in \rx_hold_reg_reg[11] 2 -.latch \rx_hold_reg_reg[12]_in \rx_hold_reg_reg[12] 2 -.latch \rx_hold_reg_reg[14]_in \rx_hold_reg_reg[14] 2 -.latch \rx_hold_reg_reg[15]_in \rx_hold_reg_reg[15] 2 -.latch \rx_hold_reg_reg[1]_in \rx_hold_reg_reg[1] 2 -.latch \rx_hold_reg_reg[4]_in \rx_hold_reg_reg[4] 2 -.latch \rx_hold_reg_reg[5]_in \rx_hold_reg_reg[5] 2 -.latch \rx_hold_reg_reg[6]_in \rx_hold_reg_reg[6] 2 -.latch \rx_hold_reg_reg[9]_in \rx_hold_reg_reg[9] 2 -.latch \rx_hold_reg_reg[2]_in \rx_hold_reg_reg[2] 2 -.latch \rx_hold_reg_reg[7]_in \rx_hold_reg_reg[7] 2 -.latch \rx_hold_reg_reg[13]_in \rx_hold_reg_reg[13] 2 -.latch \rx_hold_reg_reg[3]_in \rx_hold_reg_reg[3] 2 -.latch tx_go_r1_reg_in tx_go_r1_reg 2 -.latch \psa_reg[2]_in \psa_reg[2] 2 -.latch \psa_reg[5]_in \psa_reg[5] 2 -.latch \psa_reg[1]_in \psa_reg[1] 2 -.latch \psa_reg[7]_in \psa_reg[7] 2 -.latch \psa_reg[6]_in \psa_reg[6] 2 -.latch \psa_reg[0]_in \psa_reg[0] 2 -.latch \psa_reg[3]_in \psa_reg[3] 2 -.latch \psa_reg[4]_in \psa_reg[4] 2 -.latch psync_reg_in psync_reg 2 -.latch pcm_sync_r1_reg_in pcm_sync_r1_reg 2 -.latch rxd_t_reg_in rxd_t_reg 2 -.latch pcm_sync_r3_reg_in pcm_sync_r3_reg 2 -.latch pcm_sync_r2_reg_in pcm_sync_r2_reg 2 -.latch pclk_r_reg_in pclk_r_reg 2 -.latch \tx_hold_byte_l_reg[5]_in \tx_hold_byte_l_reg[5] 2 -.latch \tx_hold_byte_h_reg[7]_in \tx_hold_byte_h_reg[7] 2 -.latch \tx_hold_byte_h_reg[4]_in \tx_hold_byte_h_reg[4] 2 -.latch \tx_hold_byte_h_reg[6]_in \tx_hold_byte_h_reg[6] 2 -.latch \tx_hold_byte_h_reg[1]_in \tx_hold_byte_h_reg[1] 2 -.latch \tx_hold_byte_h_reg[2]_in \tx_hold_byte_h_reg[2] 2 -.latch \tx_hold_byte_h_reg[3]_in \tx_hold_byte_h_reg[3] 2 -.latch \tx_hold_byte_h_reg[5]_in \tx_hold_byte_h_reg[5] 2 -.latch \tx_hold_byte_l_reg[1]_in \tx_hold_byte_l_reg[1] 2 -.latch \tx_hold_byte_l_reg[2]_in \tx_hold_byte_l_reg[2] 2 -.latch \tx_hold_byte_l_reg[4]_in \tx_hold_byte_l_reg[4] 2 -.latch \tx_hold_byte_l_reg[7]_in \tx_hold_byte_l_reg[7] 2 -.latch \tx_hold_byte_h_reg[0]_in \tx_hold_byte_h_reg[0] 2 -.latch \tx_hold_byte_l_reg[6]_in \tx_hold_byte_l_reg[6] 2 -.latch \tx_hold_byte_l_reg[3]_in \tx_hold_byte_l_reg[3] 2 -.latch \tx_hold_byte_l_reg[0]_in \tx_hold_byte_l_reg[0] 2 -.latch pclk_s_reg_in pclk_s_reg 2 -.latch rxd_reg_in rxd_reg 2 -.latch pclk_t_reg_in pclk_t_reg 2 - -.names [115] - 0 -.names [116] - 1 -.names \tx_hold_reg_reg[15] pcm_dout_o -1 1 -.names \tx_hold_reg_reg[1] [118] -0 1 -.names \tx_hold_reg_reg[2] [119] -0 1 -.names \tx_hold_reg_reg[3] [120] -0 1 -.names \tx_hold_reg_reg[4] [121] -0 1 -.names \tx_hold_reg_reg[5] [122] -0 1 -.names \tx_hold_reg_reg[6] [123] -0 1 -.names \tx_hold_reg_reg[7] [124] -0 1 -.names \tx_hold_reg_reg[8] [125] -0 1 -.names \tx_hold_reg_reg[9] [126] -0 1 -.names \tx_hold_reg_reg[11] [127] -0 1 -.names \tx_hold_reg_reg[12] [128] -0 1 -.names \tx_hold_reg_reg[13] [129] -0 1 -.names \tx_hold_reg_reg[14] [130] -0 1 -.names \tx_hold_reg_reg[0] [131] -1 1 -.names tx_go_reg [132] -1 1 -.names \tx_hold_reg_reg[10] [133] -1 1 -.names [221] [207] [480] \tx_hold_reg_reg[1]_in -11- 0 ---1 0 -.names [236] [190] [481] \tx_hold_reg_reg[14]_in -11- 0 ---1 0 -.names [237] [191] [481] \tx_hold_reg_reg[15]_in -11- 0 ---1 0 -.names [168] [169] \tx_hold_reg_reg[0]_in -11 0 -.names [224] [210] [481] \tx_hold_reg_reg[4]_in -11- 0 ---1 0 -.names [225] [212] [480] \tx_hold_reg_reg[5]_in -11- 0 ---1 0 -.names [226] [213] [476] \tx_hold_reg_reg[6]_in -11- 0 ---1 0 -.names [227] [215] [478] \tx_hold_reg_reg[7]_in -11- 0 ---1 0 -.names \rx_reg_reg[13] [142] -0 1 -.names \rx_reg_reg[14] [143] -0 1 -.names \rx_reg_reg[15] [144] -0 1 -.names \rx_reg_reg[1] [145] -0 1 -.names \rx_reg_reg[2] [146] -0 1 -.names \rx_reg_reg[3] [147] -0 1 -.names \rx_reg_reg[4] [148] -0 1 -.names \rx_reg_reg[5] [149] -0 1 -.names \rx_reg_reg[6] [150] -0 1 -.names \rx_reg_reg[7] [151] -0 1 -.names \rx_reg_reg[8] [152] -0 1 -.names \rx_reg_reg[9] [153] -0 1 -.names \rx_reg_reg[0] [154] -0 1 -.names \rx_reg_reg[12] [155] -0 1 -.names \rx_reg_reg[10] [156] -0 1 -.names [228] [216] [480] \tx_hold_reg_reg[8]_in -11- 0 ---1 0 -.names \rx_reg_reg[11] [158] -0 1 -.names [229] [217] [574] \tx_hold_reg_reg[9]_in -11- 0 ---1 0 -.names [222] [208] [481] \tx_hold_reg_reg[2]_in -11- 0 ---1 0 -.names [223] [209] [480] \tx_hold_reg_reg[3]_in -11- 0 ---1 0 -.names [233] [218] [478] \tx_hold_reg_reg[11]_in -11- 0 ---1 0 -.names [234] [219] [476] \tx_hold_reg_reg[12]_in -11- 0 ---1 0 -.names [235] [189] [478] \tx_hold_reg_reg[13]_in -11- 0 ---1 0 -.names [414] [193] tx_go_reg_in -00 0 -.names \tx_cnt_reg[3] [166] -1 1 -.names [232] [238] [478] \tx_hold_reg_reg[10]_in -11- 0 ---1 0 -.names [230] [441] [168] -11 0 -.names [131] rst [303] [576] [169] -1111 0 -.names \tx_cnt_reg[2] [170] -1 1 -.names \tx_cnt_reg[0] [171] -1 1 -.names \tx_cnt_reg[1] [172] -1 1 -.names [273] [257] [477] \rx_reg_reg[14]_in -11- 0 ---1 0 -.names [277] [261] [475] \rx_reg_reg[3]_in -11- 0 ---1 0 -.names [272] [256] [475] \rx_reg_reg[13]_in -11- 0 ---1 0 -.names [274] [258] [574] \rx_reg_reg[15]_in -11- 0 ---1 0 -.names [275] [259] [574] \rx_reg_reg[1]_in -11- 0 ---1 0 -.names [276] [260] [474] \rx_reg_reg[2]_in -11- 0 ---1 0 -.names [279] [263] [474] \rx_reg_reg[5]_in -11- 0 ---1 0 -.names [280] [264] [477] \rx_reg_reg[6]_in -11- 0 ---1 0 -.names [281] [265] [474] \rx_reg_reg[7]_in -11- 0 ---1 0 -.names [282] [266] [474] \rx_reg_reg[8]_in -11- 0 ---1 0 -.names [283] [267] [476] \rx_reg_reg[9]_in -11- 0 ---1 0 -.names [284] [268] [476] \rx_reg_reg[0]_in -11- 0 ---1 0 -.names [278] [262] [477] \rx_reg_reg[4]_in -11- 0 ---1 0 -.names [285] [269] [475] \rx_reg_reg[10]_in -11- 0 ---1 0 -.names [286] [270] [475] \rx_reg_reg[11]_in -11- 0 ---1 0 -.names [271] [255] [477] \rx_reg_reg[12]_in -11- 0 ---1 0 -.names [298] [303] [189] -11 0 -.names [300] [303] [190] -11 0 -.names [293] [303] [191] -11 0 -.names \rx_hold_reg_reg[8] [192] -0 1 -.names [327] [303] [544] [193] -11- 0 ---1 0 -.names \rx_hold_reg_reg[10] [194] -0 1 -.names \rx_hold_reg_reg[0] [195] -0 1 -.names \rx_hold_reg_reg[11] [196] -0 1 -.names \rx_hold_reg_reg[12] [197] -0 1 -.names \rx_hold_reg_reg[14] [198] -0 1 -.names \rx_hold_reg_reg[15] [199] -0 1 -.names \rx_hold_reg_reg[1] [200] -0 1 -.names \rx_hold_reg_reg[4] [201] -0 1 -.names \rx_hold_reg_reg[5] [202] -0 1 -.names \rx_hold_reg_reg[6] [203] -0 1 -.names \rx_hold_reg_reg[9] [204] -0 1 -.names \rx_hold_reg_reg[2] [205] -0 1 -.names \rx_hold_reg_reg[7] [206] -0 1 -.names [287] [303] [207] -11 0 -.names [299] [303] [208] -11 0 -.names [289] [303] [209] -11 0 -.names [301] [303] [210] -11 0 -.names \rx_hold_reg_reg[13] [211] -0 1 -.names [290] [303] [212] -11 0 -.names [294] [303] [213] -11 0 -.names \rx_hold_reg_reg[3] [214] -0 1 -.names [291] [303] [215] -11 0 -.names [297] [303] [216] -11 0 -.names [288] [303] [217] -11 0 -.names [295] [303] [218] -11 0 -.names [296] [303] [219] -11 0 -.names [324] [365] [544] \tx_cnt_reg[1]_in -11- 0 ---1 0 -.names [499] [303] [221] -00 0 -.names [527] [303] [222] -00 0 -.names [500] [303] [223] -00 0 -.names [510] [303] [224] -00 0 -.names [511] [303] [225] -00 0 -.names [534] [303] [226] -00 0 -.names [529] [303] [227] -00 0 -.names [501] [303] [228] -00 0 -.names [303] [518] [229] -00 0 -.names [574] [303] [230] -00 1 -.names [325] [340] [544] \tx_cnt_reg[2]_in -11- 0 ---1 0 -.names [528] [303] [232] -00 0 -.names [509] [303] [233] -00 0 -.names [557] [303] [234] -00 0 -.names [539] [303] [235] -00 0 -.names [553] [303] [236] -00 0 -.names [562] [303] [237] -00 0 -.names [313] [388] [303] [238] -00- 1 ---0 1 -.names [323] [376] [544] \tx_cnt_reg[0]_in -11- 0 ---1 0 -.names [373] [342] [478] \rx_hold_reg_reg[10]_in -11- 0 ---1 0 -.names [374] [343] [479] \rx_hold_reg_reg[11]_in -11- 0 ---1 0 -.names [375] [344] [479] \rx_hold_reg_reg[12]_in -11- 0 ---1 0 -.names [377] [345] [479] \rx_hold_reg_reg[13]_in -11- 0 ---1 0 -.names [378] [346] [479] \rx_hold_reg_reg[14]_in -11- 0 ---1 0 -.names [379] [347] [476] \rx_hold_reg_reg[15]_in -11- 0 ---1 0 -.names [380] [348] [478] \rx_hold_reg_reg[1]_in -11- 0 ---1 0 -.names [381] [349] [479] \rx_hold_reg_reg[2]_in -11- 0 ---1 0 -.names [382] [350] [479] \rx_hold_reg_reg[3]_in -11- 0 ---1 0 -.names [383] [351] [479] \rx_hold_reg_reg[4]_in -11- 0 ---1 0 -.names [384] [352] [476] \rx_hold_reg_reg[5]_in -11- 0 ---1 0 -.names [385] [353] [476] \rx_hold_reg_reg[6]_in -11- 0 ---1 0 -.names [386] [354] [476] \rx_hold_reg_reg[7]_in -11- 0 ---1 0 -.names [389] [356] [479] \rx_hold_reg_reg[9]_in -11- 0 ---1 0 -.names [387] [355] [478] \rx_hold_reg_reg[8]_in -11- 0 ---1 0 -.names [331] [564] [255] -11 0 -.names [331] [550] [256] -11 0 -.names [331] [555] [257] -11 0 -.names [331] [558] [258] -11 0 -.names [331] [552] [259] -11 0 -.names [331] [551] [260] -11 0 -.names [331] [522] [261] -11 0 -.names [331] [521] [262] -11 0 -.names [331] [535] [263] -11 0 -.names [331] [547] [264] -11 0 -.names [331] [563] [265] -11 0 -.names [331] [559] [266] -11 0 -.names [331] [546] [267] -11 0 -.names [331] [560] [268] -11 0 -.names [331] [543] [269] -11 0 -.names [331] [536] [270] -11 0 -.names [332] [155] [271] -00 0 -.names [332] [142] [272] -00 0 -.names [332] [143] [273] -00 0 -.names [332] [144] [274] -00 0 -.names [332] [145] [275] -00 0 -.names [332] [146] [276] -00 0 -.names [332] [147] [277] -00 0 -.names [332] [148] [278] -00 0 -.names [332] [149] [279] -00 0 -.names [332] [150] [280] -00 0 -.names [332] [151] [281] -00 0 -.names [332] [152] [282] -00 0 -.names [332] [153] [283] -00 0 -.names [332] [154] [284] -00 0 -.names [332] [156] [285] -00 0 -.names [332] [158] [286] -00 0 -.names [314] [359] [287] -11 0 -.names [322] [364] [288] -11 0 -.names [318] [361] [289] -11 0 -.names [315] [362] [290] -11 0 -.names [319] [358] [291] -11 0 -.names tx_go_r1_reg [292] -1 1 -.names [329] [357] [293] -11 0 -.names [320] [371] [294] -11 0 -.names [328] [367] [295] -11 0 -.names [330] [368] [296] -11 0 -.names [333] [369] [297] -11 0 -.names [326] [366] [298] -11 0 -.names [316] [360] [299] -11 0 -.names [321] [370] [300] -11 0 -.names [317] [363] [301] -11 0 -.names [390] [372] [478] \rx_hold_reg_reg[0]_in -11- 0 ---1 0 -.names [312] [303] -0 1 -.names \psa_reg[2] [304] -1 1 -.names \psa_reg[5] [305] -1 1 -.names \psa_reg[1] [306] -1 1 -.names \psa_reg[7] [307] -1 1 -.names \psa_reg[6] [308] -1 1 -.names \psa_reg[0] [309] -1 1 -.names \psa_reg[3] [310] -1 1 -.names \psa_reg[4] [311] -1 1 -.names psync_reg [312] -1 1 -.names [578] [126] [313] -00 1 -.names [548] [399] [314] -11 0 -.names [519] [399] [315] -11 0 -.names [541] [399] [316] -11 0 -.names [513] [398] [317] -11 0 -.names [549] [398] [318] -11 0 -.names [505] [398] [319] -11 0 -.names [503] [399] [320] -11 0 -.names [506] [398] [321] -11 0 -.names [399] [565] [322] -11 0 -.names [171] [397] [323] -11 0 -.names [172] [397] [324] -11 0 -.names [170] [397] [325] -11 0 -.names [545] [398] [326] -11 0 -.names [397] [132] [327] -11 0 -.names [523] [398] [328] -11 0 -.names [399] pcm_dout_o [329] -11 0 -.names [515] [398] [330] -11 0 -.names [391] [331] -0 1 -.names [392] [332] -0 1 -.names [507] [399] [333] -11 0 -.names [403] [576] tx_go_r1_reg_in -11 0 -.names [306] [309] [567] \psa_reg[1]_in -01- 1 -1-1 1 -.names [304] [306] [567] \psa_reg[2]_in -01- 1 -1-1 1 -.names [310] [304] [567] \psa_reg[3]_in -01- 1 -1-1 1 -.names [305] [311] [567] \psa_reg[5]_in -01- 1 -1-1 1 -.names pcm_sync_r1_reg [339] -0 1 -.names [419] [570] [340] -11 0 -.names rxd_t_reg [341] -0 1 -.names [404] [546] [342] -11 0 -.names [404] [543] [343] -11 0 -.names [404] [536] [344] -11 0 -.names [404] [564] [345] -11 0 -.names [404] [550] [346] -11 0 -.names [404] [555] [347] -11 0 -.names [404] [560] [348] -11 0 -.names [404] [552] [349] -11 0 -.names [404] [551] [350] -11 0 -.names [404] [522] [351] -11 0 -.names [404] [521] [352] -11 0 -.names [404] [535] [353] -11 0 -.names [404] [547] [354] -11 0 -.names [404] [563] [355] -11 0 -.names [404] [559] [356] -11 0 -.names [506] [571] [357] -11 0 -.names [503] [571] [358] -11 0 -.names [131] [571] [359] -11 0 -.names [548] [571] [360] -11 0 -.names [541] [570] [361] -11 0 -.names [513] [571] [362] -11 0 -.names [549] [570] [363] -11 0 -.names [507] [570] [364] -11 0 -.names [440] [570] [365] -11 0 -.names [515] [571] [366] -11 0 -.names [133] [571] [367] -11 0 -.names [523] [570] [368] -11 0 -.names [505] [571] [369] -11 0 -.names [545] [570] [370] -11 0 -.names [519] [570] [371] -11 0 -.names [404] [472] [372] -11 0 -.names [405] [194] [373] -00 0 -.names [405] [196] [374] -00 0 -.names [405] [197] [375] -00 0 -.names [542] [570] [376] -11 0 -.names [405] [211] [377] -00 0 -.names [405] [198] [378] -00 0 -.names [405] [199] [379] -00 0 -.names [405] [200] [380] -00 0 -.names [405] [205] [381] -00 0 -.names [405] [214] [382] -00 0 -.names [405] [201] [383] -00 0 -.names [405] [202] [384] -00 0 -.names [405] [203] [385] -00 0 -.names [405] [206] [386] -00 0 -.names [405] [192] [387] -00 0 -.names [530] [570] [388] -00 1 -.names [405] [204] [389] -00 0 -.names [405] [195] [390] -00 0 -.names [400] [391] -0 1 -.names [400] [392] -0 1 -.names [307] [308] [567] \psa_reg[7]_in -01- 1 -1-1 1 -.names [308] [305] [567] \psa_reg[6]_in -01- 1 -1-1 1 -.names [309] [524] [567] \psa_reg[0]_in -01- 1 -1-1 1 -.names [311] [310] [567] \psa_reg[4]_in -01- 1 -1-1 1 -.names [577] [397] -0 1 -.names [402] [398] -0 1 -.names [402] [399] -0 1 -.names [582] [400] -0 1 -.names [412] [409] psync_reg_in -00 1 -.names [580] [402] -0 1 -.names [292] [566] [403] -11 0 -.names [408] [404] -1 1 -.names [408] [405] -1 1 -.names pcm_sync_i [524] [410] pcm_sync_r1_reg_in -01- 1 -1-1 1 -.names pcm_din_i rxd_reg_in [410] rxd_t_reg_in -01- 1 -1-1 1 -.names [512] [586] [410] [408] -11- 0 ---1 0 -.names pcm_sync_r3_reg [409] -1 1 -.names [439] [413] [410] -11 0 -.names [412] pcm_sync_r3_reg_in -0 1 -.names pcm_sync_r2_reg [412] -0 1 -.names [585] [413] -0 1 -.names [418] [166] [456] [414] -11- 0 ---1 0 -.names [420] [422] ssel[2] pcm_sync_r2_reg_in -01- 1 -1-1 1 -.names pclk_r_reg [416] -1 1 -.names [166] [438] [417] -01 1 -10 1 -.names [438] [418] -0 1 -.names [170] [473] [419] -01 1 -10 1 -.names [469] [470] ssel[1] [420] -01- 1 -1-1 1 -.names \tx_hold_byte_l_reg[5] [421] -1 1 -.names [467] [468] ssel[1] [422] -01- 1 -1-1 1 -.names [439] pclk_r_reg_in -0 1 -.names \tx_hold_byte_h_reg[7] [424] -1 1 -.names \tx_hold_byte_h_reg[4] [425] -1 1 -.names \tx_hold_byte_h_reg[6] [426] -1 1 -.names \tx_hold_byte_h_reg[1] [427] -1 1 -.names \tx_hold_byte_h_reg[2] [428] -1 1 -.names \tx_hold_byte_h_reg[3] [429] -1 1 -.names \tx_hold_byte_h_reg[5] [430] -1 1 -.names \tx_hold_byte_l_reg[1] [431] -1 1 -.names \tx_hold_byte_l_reg[2] [432] -1 1 -.names \tx_hold_byte_l_reg[4] [433] -1 1 -.names \tx_hold_byte_l_reg[7] [434] -1 1 -.names \tx_hold_byte_h_reg[0] [435] -1 1 -.names \tx_hold_byte_l_reg[6] [436] -1 1 -.names \tx_hold_byte_l_reg[3] [437] -1 1 -.names [473] [170] [438] -11 0 -.names [443] [439] -0 1 -.names [172] [171] [440] -01 1 -10 1 -.names \tx_hold_byte_l_reg[0] [441] -1 1 -.names [532] [517] re_i dout_o[4] -01- 1 -1-1 1 -.names pclk_s_reg [443] -1 1 -.names we_i[0] [529] [484] \tx_hold_byte_l_reg[7]_in -00- 1 ---0 1 -.names we_i[0] [500] [482] \tx_hold_byte_l_reg[3]_in -00- 1 ---0 1 -.names we_i[1] [528] [487] \tx_hold_byte_h_reg[2]_in -00- 1 ---0 1 -.names we_i[1] [518] [488] \tx_hold_byte_h_reg[1]_in -00- 1 ---0 1 -.names we_i[0] [499] [492] \tx_hold_byte_l_reg[1]_in -00- 1 ---0 1 -.names we_i[1] [501] [494] \tx_hold_byte_h_reg[0]_in -00- 1 ---0 1 -.names we_i[1] [509] [489] \tx_hold_byte_h_reg[3]_in -00- 1 ---0 1 -.names we_i[1] [553] [495] \tx_hold_byte_h_reg[6]_in -00- 1 ---0 1 -.names we_i[0] [510] [497] \tx_hold_byte_l_reg[4]_in -00- 1 ---0 1 -.names we_i[0] [534] [491] \tx_hold_byte_l_reg[6]_in -00- 1 ---0 1 -.names we_i[0] [511] [490] \tx_hold_byte_l_reg[5]_in -00- 1 ---0 1 -.names we_i[1] [539] [483] \tx_hold_byte_h_reg[5]_in -00- 1 ---0 1 -.names rst [132] [456] -11 0 -.names we_i[0] [527] [493] \tx_hold_byte_l_reg[2]_in -00- 1 ---0 1 -.names [540] [537] re_i dout_o[0] -01- 1 -1-1 1 -.names [533] [514] re_i dout_o[7] -01- 1 -1-1 1 -.names [525] [516] re_i dout_o[6] -01- 1 -1-1 1 -.names [520] [504] re_i dout_o[5] -01- 1 -1-1 1 -.names [538] [554] re_i dout_o[3] -01- 1 -1-1 1 -.names [526] [502] re_i dout_o[2] -01- 1 -1-1 1 -.names [531] [508] re_i dout_o[1] -01- 1 -1-1 1 -.names we_i[1] [562] [485] \tx_hold_byte_h_reg[7]_in -00- 1 ---0 1 -.names we_i[1] [557] [486] \tx_hold_byte_h_reg[4]_in -00- 1 ---0 1 -.names [311] [305] ssel[0] [467] -01- 1 -1-1 1 -.names [308] [307] ssel[0] [468] -01- 1 -1-1 1 -.names [309] [306] ssel[0] [469] -01- 1 -1-1 1 -.names [304] [310] ssel[0] [470] -01- 1 -1-1 1 -.names [441] din_i[0] we_i[0] \tx_hold_byte_l_reg[0]_in -01- 1 -1-1 1 -.names rxd_reg [472] -1 1 -.names [542] [561] [473] -00 1 -.names rst [474] -0 1 -.names rst [475] -0 1 -.names rst [476] -0 1 -.names rst [477] -0 1 -.names rst [478] -0 1 -.names rst [479] -0 1 -.names rst [480] -0 1 -.names rst [481] -0 1 -.names din_i[3] we_i[0] [482] -11 0 -.names we_i[1] din_i[5] [483] -11 0 -.names din_i[7] we_i[0] [484] -11 0 -.names we_i[1] din_i[7] [485] -11 0 -.names we_i[1] din_i[4] [486] -11 0 -.names we_i[1] din_i[2] [487] -11 0 -.names we_i[1] din_i[1] [488] -11 0 -.names we_i[1] din_i[3] [489] -11 0 -.names din_i[5] we_i[0] [490] -11 0 -.names din_i[6] we_i[0] [491] -11 0 -.names din_i[1] we_i[0] [492] -11 0 -.names din_i[2] we_i[0] [493] -11 0 -.names we_i[1] din_i[0] [494] -11 0 -.names we_i[1] din_i[6] [495] -11 0 -.names [586] [496] -0 1 -.names din_i[4] we_i[0] [497] -11 0 -.names pclk_t_reg pclk_s_reg_in -1 1 -.names [431] [499] -0 1 -.names [437] [500] -0 1 -.names [435] [501] -0 1 -.names [156] [502] -0 1 -.names [123] [503] -0 1 -.names [142] [504] -0 1 -.names [124] [505] -0 1 -.names [130] [506] -0 1 -.names [125] [507] -0 1 -.names [153] [508] -0 1 -.names [429] [509] -0 1 -.names [433] [510] -0 1 -.names [421] [511] -0 1 -.names [292] [512] -0 1 -.names [121] [513] -0 1 -.names [144] [514] -0 1 -.names [128] [515] -0 1 -.names [143] [516] -0 1 -.names [155] [517] -0 1 -.names [427] [518] -0 1 -.names [122] [519] -0 1 -.names [149] [520] -0 1 -.names [201] [521] -0 1 -.names [214] [522] -0 1 -.names [127] [523] -0 1 -.names [339] [524] -0 1 -.names [150] [525] -0 1 -.names [146] [526] -0 1 -.names [432] [527] -0 1 -.names [428] [528] -0 1 -.names [434] [529] -0 1 -.names [133] [530] -0 1 -.names [145] [531] -0 1 -.names [148] [532] -0 1 -.names [151] [533] -0 1 -.names [436] [534] -0 1 -.names [202] [535] -0 1 -.names [196] [536] -0 1 -.names [152] [537] -0 1 -.names [147] [538] -0 1 -.names [430] [539] -0 1 -.names [154] [540] -0 1 -.names [119] [541] -0 1 -.names [171] [542] -0 1 -.names [194] [543] -0 1 -.names rst [544] -0 1 -.names [129] [545] -0 1 -.names [204] [546] -0 1 -.names [203] [547] -0 1 -.names [118] [548] -0 1 -.names [120] [549] -0 1 -.names [211] [550] -0 1 -.names [205] [551] -0 1 -.names [200] [552] -0 1 -.names [426] [553] -0 1 -.names [158] [554] -0 1 -.names [198] [555] -0 1 -.names [341] rxd_reg_in -0 1 -.names [425] [557] -0 1 -.names [199] [558] -0 1 -.names [192] [559] -0 1 -.names [195] [560] -0 1 -.names [172] [561] -0 1 -.names [424] [562] -0 1 -.names [206] [563] -0 1 -.names [197] [564] -0 1 -.names [126] [565] -0 1 -.names [567] [566] -0 1 -.names [568] [567] -1 1 -.names [569] [568] -0 1 -.names [585] [443] [569] -11 0 -.names [572] [570] -0 1 -.names [572] [571] -0 1 -.names [581] [572] -0 1 -.names [574] [575] \tx_cnt_reg[3]_in -00 1 -.names rst [574] -0 1 -.names [166] [576] [579] [575] -11- 0 ---1 0 -.names [577] [576] -0 1 -.names [578] [577] -0 1 -.names [496] [568] [578] -11 0 -.names [417] [576] [579] -00 1 -.names [568] [496] [580] -11 0 -.names [586] [584] [581] -00 1 -.names [583] [586] [292] [582] -111 0 -.names [584] [583] -0 1 -.names [585] [443] [584] -11 0 -.names [416] [585] -0 1 -.names [132] [586] -0 1 -.names pcm_clk_i pclk_t_reg_in -1 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/steppermotordrive.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/steppermotordrive.blif deleted file mode 100644 index 655eb5c3d..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/steppermotordrive.blif +++ /dev/null @@ -1,515 +0,0 @@ -# Benchmark "steppermotordrive" written by ABC on Mon Aug 29 15:33:12 2005 -.model steppermotordrive -.inputs clock Direction StepEnable ProvideStaticHolding -.outputs StepDrive[0] StepDrive[1] StepDrive[2] StepDrive[3] - -.latch \StepCounter_reg[16]_in \StepCounter_reg[16] 2 -.latch \StepCounter_reg[15]_in \StepCounter_reg[15] 2 -.latch \StepCounter_reg[11]_in \StepCounter_reg[11] 2 -.latch \StepDrive_reg[0]_in \StepDrive_reg[0] 2 -.latch \StepDrive_reg[1]_in \StepDrive_reg[1] 2 -.latch \StepCounter_reg[17]_in \StepCounter_reg[17] 2 -.latch \StepCounter_reg[12]_in \StepCounter_reg[12] 2 -.latch \StepCounter_reg[14]_in \StepCounter_reg[14] 2 -.latch \state_reg[1]_in \state_reg[1] 2 -.latch \StepDrive_reg[2]_in \StepDrive_reg[2] 2 -.latch \StepCounter_reg[8]_in \StepCounter_reg[8] 2 -.latch \StepCounter_reg[10]_in \StepCounter_reg[10] 2 -.latch \StepDrive_reg[3]_in \StepDrive_reg[3] 2 -.latch InternalStepEnable_reg_in InternalStepEnable_reg 2 -.latch \StepCounter_reg[13]_in \StepCounter_reg[13] 2 -.latch \StepCounter_reg[7]_in \StepCounter_reg[7] 2 -.latch \StepCounter_reg[3]_in \StepCounter_reg[3] 2 -.latch \StepCounter_reg[6]_in \StepCounter_reg[6] 2 -.latch \state_reg[0]_in \state_reg[0] 2 -.latch \StepCounter_reg[2]_in \StepCounter_reg[2] 2 -.latch \StepCounter_reg[9]_in \StepCounter_reg[9] 2 -.latch \StepCounter_reg[0]_in \StepCounter_reg[0] 2 -.latch \StepCounter_reg[4]_in \StepCounter_reg[4] 2 -.latch \StepCounter_reg[5]_in \StepCounter_reg[5] 2 -.latch \StepCounter_reg[1]_in \StepCounter_reg[1] 2 - -.names [33] - 0 -.names [34] - 1 -.names \StepCounter_reg[16] [35] -1 1 -.names \StepCounter_reg[15] [36] -1 1 -.names \StepCounter_reg[11] [37] -1 1 -.names \StepDrive_reg[0] StepDrive[0] -1 1 -.names \StepDrive_reg[1] StepDrive[1] -1 1 -.names [42] \StepCounter_reg[16]_in -0 1 -.names \StepCounter_reg[17] [41] -1 1 -.names [54] [100] [42] -11 0 -.names [65] [95] \StepDrive_reg[0]_in -11 0 -.names [63] [95] \StepDrive_reg[1]_in -11 0 -.names \StepCounter_reg[12] [45] -1 1 -.names \StepCounter_reg[14] [46] -1 1 -.names \state_reg[1] [47] -1 1 -.names \StepDrive_reg[2] StepDrive[2] -1 1 -.names \StepCounter_reg[8] [49] -1 1 -.names \StepCounter_reg[10] [50] -1 1 -.names \StepDrive_reg[3] StepDrive[3] -1 1 -.names InternalStepEnable_reg [52] -1 1 -.names \StepCounter_reg[13] [53] -1 1 -.names [143] [35] [241] [54] -01- 1 -1-1 1 -.names \StepCounter_reg[7] [55] -1 1 -.names \StepCounter_reg[3] [56] -1 1 -.names \StepCounter_reg[6] [57] -1 1 -.names \state_reg[0] [58] -1 1 -.names \StepCounter_reg[2] [59] -1 1 -.names \StepCounter_reg[9] [60] -1 1 -.names \StepCounter_reg[0] [61] -1 1 -.names [78] [95] \StepDrive_reg[2]_in -11 0 -.names [100] StepDrive[1] [75] [63] -11- 0 ---1 0 -.names [109] [146] [76] \state_reg[1]_in -00- 1 ---0 1 -.names [100] StepDrive[0] [87] [65] -11- 0 ---1 0 -.names [84] [100] \StepCounter_reg[14]_in -11 1 -.names [169] [100] \StepCounter_reg[13]_in -11 1 -.names [77] InternalStepEnable_reg_in -0 1 -.names [93] [98] \StepCounter_reg[10]_in -00 1 -.names \StepCounter_reg[4] [70] -1 1 -.names \StepCounter_reg[5] [71] -1 1 -.names \StepCounter_reg[1] [72] -1 1 -.names [89] [95] \StepDrive_reg[3]_in -11 0 -.names [92] [100] \StepCounter_reg[8]_in -11 1 -.names [119] [146] [75] -00 1 -.names [146] [47] [76] -11 0 -.names [100] [133] StepEnable [77] -11- 0 ---1 0 -.names [131] [178] [179] StepDrive[2] [78] -11-- 0 ---11 0 -.names [125] [58] [259] \state_reg[0]_in -01- 1 -1-1 1 -.names [107] [97] \StepCounter_reg[3]_in -00 1 -.names [97] [230] \StepCounter_reg[0]_in -00 1 -.names [108] [98] \StepCounter_reg[2]_in -00 1 -.names [101] [97] \StepCounter_reg[9]_in -00 1 -.names [132] [103] [84] -01 1 -10 1 -.names [96] [97] \StepCounter_reg[7]_in -00 1 -.names [106] [97] \StepCounter_reg[6]_in -00 1 -.names [118] [146] [87] -00 1 -.names [105] [178] \StepCounter_reg[4]_in -00 1 -.names [126] [223] [179] StepDrive[3] [89] -11-- 0 ---11 0 -.names [114] [100] \StepCounter_reg[1]_in -11 1 -.names [104] [178] \StepCounter_reg[5]_in -00 1 -.names [151] [117] [102] [92] -00- 1 ---0 1 -.names [204] [236] [99] [93] -11- 0 ---1 0 -.names [161] [94] -0 1 -.names [136] [223] [95] -11 0 -.names [148] [234] [96] -01 1 -10 1 -.names [100] [97] -0 1 -.names [259] [98] -0 1 -.names [204] [236] [99] -00 1 -.names [223] [100] -0 1 -.names [60] [157] [101] -01 1 -10 1 -.names [151] [117] [102] -11 0 -.names [111] [204] [103] -00 1 -.names [71] [229] [104] -01 1 -10 1 -.names [70] [153] [105] -01 1 -10 1 -.names [135] [210] [106] -01 1 -10 1 -.names [122] [233] [107] -01 1 -10 1 -.names [113] [128] [110] [108] -11- 0 ---1 0 -.names [124] Direction [112] [109] -11- 0 ---1 0 -.names [113] [128] [110] -00 1 -.names [244] [186] [111] -11 0 -.names [119] Direction [112] -00 1 -.names [196] [113] -0 1 -.names [130] [230] [114] -01 1 -10 1 -.names [71] [55] [115] -11 0 -.names [217] [116] -0 1 -.names [194] [117] -0 1 -.names [124] [118] -0 1 -.names [58] [47] [134] [119] -11- 0 ---1 0 -.names [140] [215] [120] -00 1 -.names [138] [170] [121] -00 1 -.names [202] [122] -0 1 -.names [140] [123] -0 1 -.names [47] [58] [124] -01 1 -10 1 -.names [52] [58] [125] -01 1 -10 1 -.names [47] [142] [126] -00 1 -.names [139] [140] [127] -11 0 -.names [253] [128] -0 1 -.names [215] [129] -0 1 -.names [190] [130] -0 1 -.names [47] [52] [131] -11 1 -.names [138] [132] -0 1 -.names [142] [133] -0 1 -.names [58] [47] [134] -00 1 -.names [228] [135] -0 1 -.names ProvideStaticHolding [52] [136] -00 1 -.names [37] [137] -0 1 -.names [46] [138] -0 1 -.names [53] [139] -0 1 -.names [45] [140] -0 1 -.names [55] [141] -0 1 -.names [52] [142] -0 1 -.names [35] [143] -0 1 -.names [60] [144] -0 1 -.names [60] [236] [145] -11 0 -.names [147] [52] [146] -11 0 -.names [180] [147] -0 1 -.names [227] [148] -0 1 -.names [248] [197] [150] [149] -111 0 -.names [228] [202] [150] -00 1 -.names [152] [153] [151] -00 0 -.names [191] [232] [152] -00 0 -.names [201] [154] [153] -11 0 -.names [192] [154] -0 1 -.names [115] [155] -0 1 -.names [140] [144] [156] -00 0 -.names [158] [157] -0 1 -.names [229] [182] [158] -00 1 -.names [145] [160] [159] -00 1 -.names [227] [194] [160] -00 0 -.names [168] [161] -0 1 -.names [137] [162] -0 1 -.names [36] [163] -0 1 -.names [165] \StepCounter_reg[11]_in -0 1 -.names [166] [259] [165] -11 0 -.names [94] [129] [167] [166] -00- 1 ---0 1 -.names [168] [37] [167] -11 0 -.names [235] [159] [168] -11 0 -.names [170] [171] [169] -01 1 -10 1 -.names [53] [170] -0 1 -.names [172] [181] [189] [171] -111 0 -.names [229] [172] -0 1 -.names [174] [177] [178] \StepCounter_reg[15]_in -11- 0 ---1 0 -.names [175] [36] [174] -11 0 -.names [161] [176] [175] -11 0 -.names [120] [121] [176] -11 1 -.names [121] [120] [161] [163] [177] -1111 0 -.names [179] [178] -0 1 -.names [180] [179] -1 1 -.names [225] [224] [180] -11 0 -.names [182] [181] -0 1 -.names [193] [155] [182] -11 0 -.names [184] [185] [183] -00 1 -.names [231] [35] [184] -11 0 -.names [186] [187] [188] [185] -111 0 -.names [116] [186] -0 1 -.names [156] [187] -0 1 -.names [121] [36] [188] -11 1 -.names [156] [116] [189] -00 1 -.names [252] [190] -1 1 -.names [70] [71] [191] -11 0 -.names [59] [56] [192] -11 0 -.names [194] [228] [193] -00 1 -.names [49] [194] -0 1 -.names [46] [36] [195] -00 0 -.names [252] [250] [196] -00 1 -.names [237] [203] [197] -00 1 -.names [191] [192] [198] -00 1 -.names [228] [141] [199] -00 1 -.names [194] [250] [200] -00 0 -.names [250] [190] [201] -00 1 -.names [56] [202] -0 1 -.names [70] [203] -0 1 -.names [205] [207] [148] [193] [204] -1111 0 -.names [202] [206] [205] -00 1 -.names [59] [71] [70] [206] -111 0 -.names [208] [250] [207] -00 1 -.names [209] [60] [208] -11 0 -.names [252] [209] -0 1 -.names [211] [61] [213] [210] -111 0 -.names [212] [202] [211] -00 1 -.names [209] [212] -0 1 -.names [206] [213] -0 1 -.names [200] [214] -0 1 -.names [37] [215] -0 1 -.names [226] [217] [49] [216] -111 0 -.names [37] [50] [217] -11 1 -.names [127] [195] [218] -00 1 -.names [220] \StepCounter_reg[12]_in -0 1 -.names [221] [222] [100] [220] -111 0 -.names [123] [246] [221] -00 0 -.names [246] [123] [222] -11 0 -.names [260] [223] -0 1 -.names [216] [218] [239] [224] -111 0 -.names [41] [35] [225] -11 1 -.names [228] [227] [226] -11 0 -.names [55] [227] -0 1 -.names [57] [228] -0 1 -.names [250] [251] [229] -00 0 -.names [250] [230] -0 1 -.names [251] [231] -0 1 -.names [199] [232] -0 1 -.names [248] [233] -0 1 -.names [235] [234] -0 1 -.names [149] [235] -0 1 -.names [50] [236] -1 1 -.names [71] [237] -0 1 -.names [239] [238] -0 1 -.names [162] [236] [60] [239] -111 0 -.names [190] [232] [240] -00 1 -.names [242] [240] [238] [214] [241] -1111 0 -.names [243] [242] -0 1 -.names [198] [244] [245] [243] -111 0 -.names [170] [140] [244] -00 1 -.names [138] [163] [245] -00 1 -.names [247] [246] -0 1 -.names [240] [238] [214] [198] [247] -1111 0 -.names [249] [248] -0 1 -.names [61] [72] [59] [249] -111 0 -.names [61] [250] -0 1 -.names [209] [59] [56] [70] [251] -1111 0 -.names [72] [252] -0 1 -.names [59] [253] -0 1 -.names [255] [257] [98] \StepCounter_reg[17]_in -11- 0 ---1 0 -.names [256] [41] [255] -11 0 -.names [183] [181] [230] [256] -111 0 -.names [183] [181] [230] [258] [257] -1111 0 -.names [41] [258] -0 1 -.names [260] [259] -1 1 -.names [224] [225] [260] -11 0 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/stereovision3.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/stereovision3.blif deleted file mode 100644 index 604b91293..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/stereovision3.blif +++ /dev/null @@ -1,881 +0,0 @@ -# Benchmark "sv_chip3_hierarchy_no_mem" written by ABC on Tue Apr 9 16:48:04 2013 -.model sv_chip3_hierarchy_no_mem -.inputs top^tm3_clk_v0 top^tm3_clk_v2 top^tm3_vidin_llc top^tm3_vidin_vs \ - top^tm3_vidin_href top^tm3_vidin_cref top^tm3_vidin_rts0 \ - top^tm3_vidin_vpo~0 top^tm3_vidin_vpo~1 top^tm3_vidin_vpo~2 \ - top^tm3_vidin_vpo~3 top^tm3_vidin_vpo~4 top^tm3_vidin_vpo~5 \ - top^tm3_vidin_vpo~6 top^tm3_vidin_vpo~7 top^tm3_vidin_vpo~8 \ - top^tm3_vidin_vpo~9 top^tm3_vidin_vpo~10 top^tm3_vidin_vpo~11 \ - top^tm3_vidin_vpo~12 top^tm3_vidin_vpo~13 top^tm3_vidin_vpo~14 \ - top^tm3_vidin_vpo~15 -.outputs top^tm3_vidin_sda top^tm3_vidin_scl top^vidin_new_data \ - top^vidin_rgb_reg~0 top^vidin_rgb_reg~1 top^vidin_rgb_reg~2 \ - top^vidin_rgb_reg~3 top^vidin_rgb_reg~4 top^vidin_rgb_reg~5 \ - top^vidin_rgb_reg~6 top^vidin_rgb_reg~7 top^vidin_addr_reg~0 \ - top^vidin_addr_reg~1 top^vidin_addr_reg~2 top^vidin_addr_reg~3 \ - top^vidin_addr_reg~4 top^vidin_addr_reg~5 top^vidin_addr_reg~6 \ - top^vidin_addr_reg~7 top^vidin_addr_reg~8 top^vidin_addr_reg~9 \ - top^vidin_addr_reg~10 top^vidin_addr_reg~11 top^vidin_addr_reg~12 \ - top^vidin_addr_reg~13 top^vidin_addr_reg~14 top^vidin_addr_reg~15 \ - top^vidin_addr_reg~16 top^vidin_addr_reg~17 top^vidin_addr_reg~18 - -.latch n107 top^FF_NODE~20 re top^tm3_clk_v0 0 -.latch n112 top^FF_NODE~30 re top^tm3_clk_v0 0 -.latch n117 top^FF_NODE~41 re top^tm3_clk_v0 0 -.latch n122 top^FF_NODE~135 re top^tm3_clk_v0 0 -.latch n127 top^FF_NODE~31 re top^tm3_clk_v0 0 -.latch n132 top^FF_NODE~42 re top^tm3_clk_v0 0 -.latch n137 top^FF_NODE~119 re top^tm3_clk_v0 0 -.latch n142 top^FF_NODE~32 re top^tm3_clk_v0 0 -.latch n147 top^FF_NODE~43 re top^tm3_clk_v0 0 -.latch n152 top^FF_NODE~120 re top^tm3_clk_v0 0 -.latch n157 top^FF_NODE~33 re top^tm3_clk_v0 0 -.latch n162 top^FF_NODE~44 re top^tm3_clk_v0 0 -.latch n167 top^FF_NODE~121 re top^tm3_clk_v0 0 -.latch n172 top^FF_NODE~34 re top^tm3_clk_v0 0 -.latch n177 top^FF_NODE~45 re top^tm3_clk_v0 0 -.latch n182 top^FF_NODE~122 re top^tm3_clk_v0 0 -.latch n187 top^FF_NODE~35 re top^tm3_clk_v0 0 -.latch n192 top^FF_NODE~46 re top^tm3_clk_v0 0 -.latch n197 top^FF_NODE~123 re top^tm3_clk_v0 0 -.latch n202 top^FF_NODE~36 re top^tm3_clk_v0 0 -.latch n207 top^FF_NODE~47 re top^tm3_clk_v0 0 -.latch n212 top^FF_NODE~124 re top^tm3_clk_v0 0 -.latch n217 top^FF_NODE~37 re top^tm3_clk_v0 0 -.latch n222 top^FF_NODE~48 re top^tm3_clk_v0 0 -.latch n227 top^FF_NODE~125 re top^tm3_clk_v0 0 -.latch n232 top^FF_NODE~38 re top^tm3_clk_v0 0 -.latch n237 top^FF_NODE~117 re top^tm3_clk_v0 0 -.latch n242 top^FF_NODE~118 re top^tm3_clk_v0 0 -.latch n247 top^FF_NODE~126 re top^tm3_clk_v0 0 -.latch n252 top^FF_NODE~127 re top^tm3_clk_v0 0 -.latch n257 top^FF_NODE~128 re top^tm3_clk_v0 0 -.latch n262 top^FF_NODE~129 re top^tm3_clk_v0 0 -.latch n267 top^FF_NODE~130 re top^tm3_clk_v0 0 -.latch n272 top^FF_NODE~131 re top^tm3_clk_v0 0 -.latch n277 top^FF_NODE~132 re top^tm3_clk_v0 0 -.latch n282 top^FF_NODE~133 re top^tm3_clk_v0 0 -.latch n287 top^FF_NODE~134 re top^tm3_clk_v0 0 -.latch n292 top^FF_NODE~136 re top^tm3_clk_v0 0 -.latch n297 top^FF_NODE~137 re top^tm3_clk_v0 0 -.latch n302 top^FF_NODE~138 re top^tm3_clk_v0 0 -.latch n307 top^FF_NODE~139 re top^tm3_clk_v0 0 -.latch n312 top^FF_NODE~140 re top^tm3_clk_v0 0 -.latch n317 top^FF_NODE~141 re top^tm3_clk_v0 0 -.latch n322 top^FF_NODE~142 re top^tm3_clk_v0 0 -.latch n327 top^FF_NODE~143 re top^tm3_clk_v0 0 -.latch n332 top^FF_NODE~144 re top^tm3_clk_v0 0 -.latch n337 top^FF_NODE~21 re top^tm3_clk_v0 0 -.latch n342 top^FF_NODE~39 re top^tm3_clk_v0 0 -.latch n347 top^FF_NODE~22 re top^tm3_clk_v0 0 -.latch n352 top^FF_NODE~49 re top^tm3_clk_v0 0 -.latch n357 top^FF_NODE~23 re top^tm3_clk_v0 0 -.latch n362 top^FF_NODE~50 re top^tm3_clk_v0 0 -.latch n367 top^FF_NODE~24 re top^tm3_clk_v0 0 -.latch n372 top^FF_NODE~51 re top^tm3_clk_v0 0 -.latch n377 top^FF_NODE~25 re top^tm3_clk_v0 0 -.latch n382 top^FF_NODE~52 re top^tm3_clk_v0 0 -.latch n387 top^FF_NODE~26 re top^tm3_clk_v0 0 -.latch n392 top^FF_NODE~53 re top^tm3_clk_v0 0 -.latch n397 top^FF_NODE~27 re top^tm3_clk_v0 0 -.latch n402 top^FF_NODE~54 re top^tm3_clk_v0 0 -.latch n407 top^FF_NODE~28 re top^tm3_clk_v0 0 -.latch n412 top^FF_NODE~55 re top^tm3_clk_v0 0 -.latch n417 top^FF_NODE~29 re top^tm3_clk_v0 0 -.latch n422 top^FF_NODE~56 re top^tm3_clk_v0 0 -.latch n427 top^FF_NODE~228 re top^tm3_clk_v2 0 -.latch n432 top^FF_NODE~381 re top^tm3_clk_v2 0 -.latch n437 top^FF_NODE~386 re top^tm3_clk_v2 0 -.latch n442 top^FF_NODE~229 re top^tm3_clk_v2 0 -.latch n447 top^FF_NODE~230 re top^tm3_clk_v2 0 -.latch n452 top^FF_NODE~387 re top^tm3_clk_v2 0 -.latch n457 top^FF_NODE~388 re top^tm3_clk_v2 0 -.latch n462 top^FF_NODE~389 re top^tm3_clk_v2 0 -.latch n467 top^FF_NODE~390 re top^tm3_clk_v2 0 -.latch n472 top^FF_NODE~391 re top^tm3_clk_v2 0 -.latch n477 top^FF_NODE~392 re top^tm3_clk_v2 0 -.latch n482 top^FF_NODE~382 re top^tm3_clk_v2 0 -.latch n487 top^FF_NODE~383 re top^tm3_clk_v2 0 -.latch n492 top^FF_NODE~384 re top^tm3_clk_v2 0 -.latch n497 top^FF_NODE~385 re top^tm3_clk_v2 0 -.latch n502 top^FF_NODE~378 re top^tm3_clk_v2 0 -.latch n507 top^FF_NODE~40 re top^tm3_clk_v0 0 -.latch n512 top^FF_NODE~57 re top^tm3_clk_v0 0 -.latch n517 top^FF_NODE~81 re top^tm3_clk_v0 0 -.latch n522 top^FF_NODE~58 re top^tm3_clk_v0 0 -.latch n527 top^FF_NODE~82 re top^tm3_clk_v0 0 -.latch n632 top^FF_NODE~69 re top^tm3_clk_v0 0 -.latch n637 top^FF_NODE~93 re top^tm3_clk_v0 0 -.latch n682 top^FF_NODE~74 re top^tm3_clk_v0 0 -.latch n687 top^FF_NODE~98 re top^tm3_clk_v0 0 -.latch n692 top^FF_NODE~75 re top^tm3_clk_v0 0 -.latch n697 top^FF_NODE~99 re top^tm3_clk_v0 0 -.latch n702 top^FF_NODE~76 re top^tm3_clk_v0 0 -.latch n707 top^FF_NODE~100 re top^tm3_clk_v0 0 -.latch n712 top^FF_NODE~77 re top^tm3_clk_v0 0 -.latch n717 top^FF_NODE~101 re top^tm3_clk_v0 0 -.latch n722 top^FF_NODE~78 re top^tm3_clk_v0 0 -.latch n727 top^FF_NODE~102 re top^tm3_clk_v0 0 -.latch n751 top^FF_NODE~114 re top^tm3_clk_v0 0 -.latch n755 top^FF_NODE~115 re top^tm3_clk_v0 0 -.latch n759 top^FF_NODE~116 re top^tm3_clk_v0 0 -.latch n763 top^FF_NODE~379 re top^tm3_clk_v2 0 -.latch n767 top^FF_NODE~380 re top^tm3_clk_v2 0 - -.names top^tm3_vidin_href top^tm3_vidin_cref top^FF_NODE~20 n107 -100 1 -111 1 -.names top^tm3_vidin_vs top^FF_NODE~30 n458 n112 -001 1 -010 1 -.names top^tm3_vidin_href top^FF_NODE~20 top^FF_NODE~22 top^FF_NODE~28 \ - top^FF_NODE~29 n459 n458 -1----- 0 --00001 0 -.names top^FF_NODE~21 top^FF_NODE~23 top^FF_NODE~24 top^FF_NODE~25 \ - top^FF_NODE~26 top^FF_NODE~27 n459 -000000 1 -.names top^tm3_vidin_cref top^FF_NODE~30 top^FF_NODE~41 n117 -01- 1 -1-1 1 -.names top^FF_NODE~38 top^FF_NODE~40 top^FF_NODE~115 top^FF_NODE~116 n292 -0001 1 -.names top^tm3_vidin_vs top^FF_NODE~31 top^FF_NODE~30 n458 n127 -0011 1 -010- 1 -01-0 1 -.names top^tm3_vidin_cref top^FF_NODE~31 top^FF_NODE~42 n132 -01- 1 -1-1 1 -.names top^tm3_vidin_vs top^FF_NODE~31 top^FF_NODE~32 top^FF_NODE~30 n458 \ - n142 -001-- 1 -01011 1 -0-10- 1 -0-1-0 1 -.names top^tm3_vidin_cref top^FF_NODE~32 top^FF_NODE~43 n147 -01- 1 -1-1 1 -.names top^tm3_vidin_vs top^FF_NODE~33 top^FF_NODE~30 n458 top^FF_NODE~31 \ - top^FF_NODE~32 n157 -001111 1 -010--- 1 -01-0-- 1 -01--0- 1 -01---0 1 -.names top^tm3_vidin_cref top^FF_NODE~33 top^FF_NODE~44 n162 -01- 1 -1-1 1 -.names top^tm3_vidin_vs top^FF_NODE~33 top^FF_NODE~34 n473 top^FF_NODE~30 \ - n458 n172 -001--- 1 -010111 1 -0-10-- 1 -0-1-0- 1 -0-1--0 1 -.names top^FF_NODE~31 top^FF_NODE~32 n473 -11 1 -.names top^tm3_vidin_cref top^FF_NODE~34 top^FF_NODE~45 n177 -01- 1 -1-1 1 -.names top^tm3_vidin_vs top^FF_NODE~33 top^FF_NODE~34 top^FF_NODE~35 n477_1 \ - n473 n187 -00-1-- 1 -011011 1 -0-01-- 1 -0--10- 1 -0--1-0 1 -.names top^FF_NODE~30 n458 n477_1 -11 1 -.names top^tm3_vidin_cref top^FF_NODE~35 top^FF_NODE~46 n192 -01- 1 -1-1 1 -.names top^tm3_vidin_vs top^FF_NODE~36 n481 n202 -001 1 -010 1 -.names top^FF_NODE~33 top^FF_NODE~34 top^FF_NODE~35 n473 top^FF_NODE~30 \ - n458 n481 -111111 1 -.names top^tm3_vidin_cref top^FF_NODE~36 top^FF_NODE~47 n207 -01- 1 -1-1 1 -.names top^tm3_vidin_vs top^FF_NODE~36 top^FF_NODE~37 n481 n217 -001- 1 -0101 1 -0-10 1 -.names top^tm3_vidin_cref top^FF_NODE~37 top^FF_NODE~48 n222 -01- 1 -1-1 1 -.names top^FF_NODE~126 n292 n247 -10 1 -.names top^FF_NODE~127 n292 n252 -10 1 -.names top^tm3_vidin_href top^FF_NODE~21 top^tm3_vidin_cref top^FF_NODE~20 \ - n337 -1001 1 -111- 1 -11-0 1 -.names top^tm3_vidin_cref top^FF_NODE~21 top^FF_NODE~39 n342 -01- 1 -1-1 1 -.names top^tm3_vidin_href top^FF_NODE~21 top^FF_NODE~22 top^tm3_vidin_cref \ - top^FF_NODE~20 n347 -101-- 1 -11001 1 -1-11- 1 -1-1-0 1 -.names top^tm3_vidin_href top^FF_NODE~21 top^FF_NODE~22 top^FF_NODE~23 \ - top^tm3_vidin_cref top^FF_NODE~20 n357 -10-1-- 1 -111001 1 -1-01-- 1 -1--11- 1 -1--1-0 1 -.names top^tm3_vidin_href top^FF_NODE~21 top^FF_NODE~22 top^FF_NODE~23 \ - top^FF_NODE~24 n514 n367 -10--1- 1 -111101 1 -1-0-1- 1 -1--01- 1 -1---10 1 -.names top^tm3_vidin_cref top^FF_NODE~20 n514 -01 1 -.names top^tm3_vidin_cref top^FF_NODE~24 top^FF_NODE~51 n372 -01- 1 -1-1 1 -.names top^tm3_vidin_href top^FF_NODE~25 n517_1 n377 -101 1 -110 1 -.names top^tm3_vidin_cref top^FF_NODE~20 top^FF_NODE~21 top^FF_NODE~22 \ - top^FF_NODE~23 top^FF_NODE~24 n517_1 -011111 1 -.names top^tm3_vidin_cref top^FF_NODE~25 top^FF_NODE~52 n382 -01- 1 -1-1 1 -.names top^tm3_vidin_href top^FF_NODE~25 top^FF_NODE~26 n517_1 n387 -101- 1 -1101 1 -1-10 1 -.names top^tm3_vidin_cref top^FF_NODE~26 top^FF_NODE~53 n392 -01- 1 -1-1 1 -.names top^tm3_vidin_href top^FF_NODE~27 n522_1 n397 -101 1 -110 1 -.names top^FF_NODE~25 top^FF_NODE~26 n517_1 n522_1 -111 1 -.names top^tm3_vidin_cref top^FF_NODE~27 top^FF_NODE~54 n402 -01- 1 -1-1 1 -.names top^tm3_vidin_href top^FF_NODE~27 top^FF_NODE~28 n522_1 n407 -101- 1 -1101 1 -1-10 1 -.names top^tm3_vidin_cref top^FF_NODE~28 top^FF_NODE~55 n412 -01- 1 -1-1 1 -.names top^tm3_vidin_href top^FF_NODE~27 top^FF_NODE~28 top^FF_NODE~29 \ - n522_1 n417 -10-1- 1 -11101 1 -1-01- 1 -1--10 1 -.names top^tm3_vidin_cref top^FF_NODE~29 top^FF_NODE~56 n422 -01- 1 -1-1 1 -.names n529 n531 n533 n539 n543 n546 n528 -1----- 0 --01111 0 -.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ - top^FF_NODE~390 n530 n529 -100011 1 -.names top^FF_NODE~391 top^FF_NODE~392 n530 -01 1 -.names top^FF_NODE~392 n532 n531 -00 1 -.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ - top^FF_NODE~390 top^FF_NODE~391 n532 -00010- 0 -10-010 0 -11100- 0 -1111-0 0 -11-100 0 -1-0010 0 --00010 0 ---1100 0 -.names top^FF_NODE~391 top^FF_NODE~392 n534 n535 n536 n538 n533 -1---1- 1 --1--10 1 ---1110 1 -.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ - top^FF_NODE~390 n534 --0-11 0 --1101 0 ---011 0 -.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ - top^FF_NODE~390 n535 -01001 0 -01111 0 -10010 0 -10100 0 -.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ - top^FF_NODE~390 n537 n536 -001011 0 -11-111 0 -1-1111 0 --11111 0 -.names top^FF_NODE~391 top^FF_NODE~392 n537 -10 1 -.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ - top^FF_NODE~390 n538 -0-000 1 --0000 1 -.names top^FF_NODE~390 top^FF_NODE~391 top^FF_NODE~392 n540 n541 n542 n539 -0101-- 0 --00--0 0 --10-0- 0 -.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 n540 -0110 1 -.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ - top^FF_NODE~390 n541 -1-010 0 --1010 0 -.names top^FF_NODE~386 top^FF_NODE~387 top^FF_NODE~388 top^FF_NODE~389 \ - top^FF_NODE~390 n542 -01010 0 -0-100 0 -11000 0 -.names top^FF_NODE~391 top^FF_NODE~392 n538 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[59] [68] [188] -00000000000000000000000000 1 -.names [0] [1] [2] [7] [25] [26] [190] -000000 1 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/traffic.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/traffic.blif deleted file mode 100644 index 0167de3c7..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/traffic.blif +++ /dev/null @@ -1,172 +0,0 @@ -.model tlc.sim -.inputs in1 -.inputs in2 -.inputs in3 -.outputs out11 -.outputs out12 -.outputs out13 -.outputs out14 -.outputs out15 -.latch out1 in4 0 -.latch out2 in5 0 -.latch out3 in6 0 -.latch out4 in7 0 -.latch out5 in8 0 -.latch out6 in9 0 -.latch out7 in10 0 -.latch out8 in11 0 -.latch out9 in12 0 -.latch out10 in13 0 -.names in1 in1* -0 1 -.names in3 in3* -0 1 -.names in4 in4* -0 1 -.names in5 in5* -0 1 -.names in6 in6* -0 1 -.names in7 in7* -0 1 -.names in8 in8* -0 1 -.names in1* in4* in5* in6* in7 g_1and1 -11111 1 -.names in1* in4 in5 in6* in7* g_1and2 -11111 1 -.names in1* in4 in5 in6 in7* g_1and3 -11111 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gin10* in12 gin13* g_2and21 -1111 1 -.names gin1* in6 in7 gin10* gin13* g_2and22 -11111 1 -.names gin1* in5 in7 gin10* gin13* g_2and23 -11111 1 -.names gin1* in4 in7 gin10* gin13* g_2and24 -11111 1 -.names gin1* gin7* gin9* in12 g_2and25 -1111 1 -.names gin1* gin7* gin9* in11 g_2and26 -1111 1 -.names gin1* gin7* gin9* in13 g_2and27 -1111 1 -.names gin1* gin2* in9 g_2and28 -111 1 -.names gin1* in2 gin9* g_2and29 -111 1 -.names gin1* gin7* gin9* in10 g_2and30 -1111 1 -.names gin1* gin11* in12 gin13* g_2and31 -1111 1 -.names gin1* in9 gin10* gin13* g_2and32 -1111 1 -.names gin1* gin10* in11 gin13* g_2and33 -1111 1 -.names g_2and28 g_2and29 out6 -00 0 -.names g_2and4 g_2and11 g_2and12 g_2and13 g_2and19 g_2and22 g_2and23 g_2and24 g_2and30 g_2and32 out7 -0000000000 0 -.names g_2and2 g_2and15 g_2and16 g_2and17 g_2and20 g_2and26 g_2and33 out8 -0000000 0 -.names g_2and1 g_2and5 g_2and6 g_2and7 g_2and14 g_2and21 g_2and25 g_2and31 out9 -00000000 0 -.names g_2and3 g_2and8 g_2and9 g_2and10 g_2and11 g_2and12 g_2and13 g_2and18 g_2and19 g_2and27 out10 -0000000000 0 -.names g_2and28 g_2and29 out11 -00 0 -.names g_2and4 g_2and11 g_2and12 g_2and13 g_2and19 g_2and22 g_2and23 g_2and24 g_2and30 g_2and32 out12 -0000000000 0 -.names g_2and2 g_2and15 g_2and16 g_2and17 g_2and20 g_2and26 g_2and33 out13 -0000000 0 -.names g_2and1 g_2and5 g_2and6 g_2and7 g_2and14 g_2and21 g_2and25 g_2and31 out14 -00000000 0 -.names g_2and3 g_2and8 g_2and9 g_2and10 g_2and11 g_2and12 g_2and13 g_2and18 g_2and19 g_2and27 out15 -0000000000 0 -.end diff --git a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/usb_phy.blif b/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/usb_phy.blif deleted file mode 100644 index 8b8f164ad..000000000 --- a/fpga_flow/benchmarks/Blif/FPGA_SPICE_bench/usb_phy.blif +++ /dev/null @@ -1,1308 +0,0 @@ -# Benchmark "usb_phy" written by ABC on Mon Aug 29 15:33:14 2005 -.model usb_phy -.inputs clk rst phy_tx_mode rxd rxdp rxdn TxValid_i DataOut_i[0] \ - DataOut_i[1] DataOut_i[2] DataOut_i[3] DataOut_i[4] DataOut_i[5] \ - DataOut_i[6] DataOut_i[7] -.outputs usb_rst txdp txdn txoe TxReady_o RxValid_o RxActive_o RxError_o \ - DataIn_o[0] DataIn_o[1] DataIn_o[2] DataIn_o[3] DataIn_o[4] DataIn_o[5] \ - DataIn_o[6] DataIn_o[7] LineState_o[0] LineState_o[1] - -.latch i_rx_phy_shift_en_reg_in i_rx_phy_shift_en_reg 2 -.latch \i_rx_phy_fs_state_reg[0]_in \i_rx_phy_fs_state_reg[0] 2 -.latch i_rx_phy_rx_active_reg_in i_rx_phy_rx_active_reg 2 -.latch i_rx_phy_sync_err_reg_in i_rx_phy_sync_err_reg 2 -.latch \i_rx_phy_fs_state_reg[1]_in \i_rx_phy_fs_state_reg[1] 2 -.latch \i_rx_phy_fs_state_reg[2]_in \i_rx_phy_fs_state_reg[2] 2 -.latch i_rx_phy_byte_err_reg_in i_rx_phy_byte_err_reg 2 -.latch \i_tx_phy_hold_reg_reg[7]_in \i_tx_phy_hold_reg_reg[7] 2 -.latch i_rx_phy_bit_stuff_err_reg_in i_rx_phy_bit_stuff_err_reg 2 -.latch \i_tx_phy_hold_reg_reg[0]_in \i_tx_phy_hold_reg_reg[0] 2 -.latch \i_tx_phy_hold_reg_reg[1]_in \i_tx_phy_hold_reg_reg[1] 2 -.latch \i_tx_phy_hold_reg_reg[2]_in \i_tx_phy_hold_reg_reg[2] 2 -.latch \i_tx_phy_hold_reg_reg[3]_in \i_tx_phy_hold_reg_reg[3] 2 -.latch \i_tx_phy_hold_reg_reg[4]_in \i_tx_phy_hold_reg_reg[4] 2 -.latch \i_tx_phy_hold_reg_reg[5]_in \i_tx_phy_hold_reg_reg[5] 2 -.latch \i_tx_phy_hold_reg_reg[6]_in \i_tx_phy_hold_reg_reg[6] 2 -.latch i_rx_phy_se0_s_reg_in i_rx_phy_se0_s_reg 2 -.latch \i_tx_phy_state_reg[0]_in \i_tx_phy_state_reg[0] 2 -.latch \i_rx_phy_dpll_state_reg[0]_in \i_rx_phy_dpll_state_reg[0] 2 -.latch \i_tx_phy_state_reg[2]_in \i_tx_phy_state_reg[2] 2 -.latch i_rx_phy_rx_valid1_reg_in i_rx_phy_rx_valid1_reg 2 -.latch \i_rx_phy_dpll_state_reg[1]_in \i_rx_phy_dpll_state_reg[1] 2 -.latch i_rx_phy_rx_valid_r_reg_in i_rx_phy_rx_valid_r_reg 2 -.latch i_rx_phy_se0_r_reg_in i_rx_phy_se0_r_reg 2 -.latch \rst_cnt_reg[3]_in \rst_cnt_reg[3] 2 -.latch \rst_cnt_reg[4]_in \rst_cnt_reg[4] 2 -.latch \rst_cnt_reg[2]_in \rst_cnt_reg[2] 2 -.latch \i_tx_phy_state_reg[1]_in \i_tx_phy_state_reg[1] 2 -.latch \i_rx_phy_one_cnt_reg[2]_in \i_rx_phy_one_cnt_reg[2] 2 -.latch \i_rx_phy_one_cnt_reg[1]_in \i_rx_phy_one_cnt_reg[1] 2 -.latch i_tx_phy_sd_raw_o_reg_in i_tx_phy_sd_raw_o_reg 2 -.latch \i_rx_phy_bit_cnt_reg[2]_in \i_rx_phy_bit_cnt_reg[2] 2 -.latch \i_tx_phy_bit_cnt_reg[2]_in \i_tx_phy_bit_cnt_reg[2] 2 -.latch i_tx_phy_append_eop_reg_in i_tx_phy_append_eop_reg 2 -.latch \i_rx_phy_one_cnt_reg[0]_in \i_rx_phy_one_cnt_reg[0] 2 -.latch \i_rx_phy_bit_cnt_reg[0]_in \i_rx_phy_bit_cnt_reg[0] 2 -.latch \i_rx_phy_bit_cnt_reg[1]_in \i_rx_phy_bit_cnt_reg[1] 2 -.latch i_tx_phy_ld_data_reg_in i_tx_phy_ld_data_reg 2 -.latch \i_tx_phy_one_cnt_reg[1]_in \i_tx_phy_one_cnt_reg[1] 2 -.latch \i_tx_phy_one_cnt_reg[2]_in \i_tx_phy_one_cnt_reg[2] 2 -.latch i_tx_phy_TxReady_o_reg_in i_tx_phy_TxReady_o_reg 2 -.latch \i_tx_phy_bit_cnt_reg[0]_in \i_tx_phy_bit_cnt_reg[0] 2 -.latch \i_tx_phy_bit_cnt_reg[1]_in \i_tx_phy_bit_cnt_reg[1] 2 -.latch \i_tx_phy_one_cnt_reg[0]_in \i_tx_phy_one_cnt_reg[0] 2 -.latch i_rx_phy_rx_valid_reg_in i_rx_phy_rx_valid_reg 2 -.latch \i_rx_phy_hold_reg_reg[6]_in \i_rx_phy_hold_reg_reg[6] 2 -.latch \i_rx_phy_hold_reg_reg[4]_in \i_rx_phy_hold_reg_reg[4] 2 -.latch \i_rx_phy_hold_reg_reg[0]_in \i_rx_phy_hold_reg_reg[0] 2 -.latch \i_rx_phy_hold_reg_reg[1]_in \i_rx_phy_hold_reg_reg[1] 2 -.latch \i_rx_phy_hold_reg_reg[2]_in \i_rx_phy_hold_reg_reg[2] 2 -.latch \i_rx_phy_hold_reg_reg[3]_in \i_rx_phy_hold_reg_reg[3] 2 -.latch \i_rx_phy_hold_reg_reg[5]_in \i_rx_phy_hold_reg_reg[5] 2 -.latch \i_rx_phy_hold_reg_reg[7]_in \i_rx_phy_hold_reg_reg[7] 2 -.latch i_tx_phy_tx_ip_reg_in i_tx_phy_tx_ip_reg 2 -.latch \rst_cnt_reg[1]_in \rst_cnt_reg[1] 2 -.latch i_tx_phy_txdp_reg_in i_tx_phy_txdp_reg 2 -.latch i_rx_phy_sd_nrzi_reg_in i_rx_phy_sd_nrzi_reg 2 -.latch i_tx_phy_sd_bs_o_reg_in i_tx_phy_sd_bs_o_reg 2 -.latch \rst_cnt_reg[0]_in \rst_cnt_reg[0] 2 -.latch i_tx_phy_txdn_reg_in i_tx_phy_txdn_reg 2 -.latch i_tx_phy_append_eop_sync3_reg_in i_tx_phy_append_eop_sync3_reg 2 -.latch i_tx_phy_txoe_reg_in i_tx_phy_txoe_reg 2 -.latch i_rx_phy_rxdn_s_reg_in i_rx_phy_rxdn_s_reg 2 -.latch i_rx_phy_rxdp_s_reg_in i_rx_phy_rxdp_s_reg 2 -.latch i_tx_phy_sft_done_reg_in i_tx_phy_sft_done_reg 2 -.latch i_tx_phy_tx_ip_sync_reg_in i_tx_phy_tx_ip_sync_reg 2 -.latch i_tx_phy_txoe_r1_reg_in i_tx_phy_txoe_r1_reg 2 -.latch i_tx_phy_append_eop_sync1_reg_in i_tx_phy_append_eop_sync1_reg 2 -.latch i_tx_phy_append_eop_sync2_reg_in i_tx_phy_append_eop_sync2_reg 2 -.latch i_tx_phy_txoe_r2_reg_in i_tx_phy_txoe_r2_reg 2 -.latch usb_rst_reg_in usb_rst_reg 2 -.latch i_tx_phy_sd_nrzi_o_reg_in i_tx_phy_sd_nrzi_o_reg 2 -.latch i_tx_phy_append_eop_sync4_reg_in i_tx_phy_append_eop_sync4_reg 2 -.latch i_rx_phy_fs_ce_reg_in i_rx_phy_fs_ce_reg 2 -.latch i_rx_phy_rxd_s_reg_in i_rx_phy_rxd_s_reg 2 -.latch i_rx_phy_sd_r_reg_in i_rx_phy_sd_r_reg 2 -.latch i_rx_phy_fs_ce_r2_reg_in i_rx_phy_fs_ce_r2_reg 2 -.latch i_tx_phy_data_done_reg_in i_tx_phy_data_done_reg 2 -.latch i_rx_phy_rxdn_s_r_reg_in i_rx_phy_rxdn_s_r_reg 2 -.latch i_rx_phy_rxdp_s_r_reg_in i_rx_phy_rxdp_s_r_reg 2 -.latch i_rx_phy_fs_ce_r1_reg_in i_rx_phy_fs_ce_r1_reg 2 -.latch i_rx_phy_rxd_r_reg_in i_rx_phy_rxd_r_reg 2 -.latch i_rx_phy_rxdn_s1_reg_in i_rx_phy_rxdn_s1_reg 2 -.latch i_rx_phy_rxd_s1_reg_in i_rx_phy_rxd_s1_reg 2 -.latch i_rx_phy_rxdp_s1_reg_in i_rx_phy_rxdp_s1_reg 2 -.latch \i_tx_phy_hold_reg_d_reg[1]_in \i_tx_phy_hold_reg_d_reg[1] 2 -.latch \i_tx_phy_hold_reg_d_reg[5]_in \i_tx_phy_hold_reg_d_reg[5] 2 -.latch i_rx_phy_rxd_s0_reg_in i_rx_phy_rxd_s0_reg 2 -.latch \i_tx_phy_hold_reg_d_reg[3]_in \i_tx_phy_hold_reg_d_reg[3] 2 -.latch i_rx_phy_rxdn_s0_reg_in i_rx_phy_rxdn_s0_reg 2 -.latch \i_tx_phy_hold_reg_d_reg[6]_in \i_tx_phy_hold_reg_d_reg[6] 2 -.latch i_tx_phy_sft_done_r_reg_in i_tx_phy_sft_done_r_reg 2 -.latch \i_tx_phy_hold_reg_d_reg[0]_in \i_tx_phy_hold_reg_d_reg[0] 2 -.latch i_rx_phy_rxdp_s0_reg_in i_rx_phy_rxdp_s0_reg 2 -.latch \i_tx_phy_hold_reg_d_reg[2]_in \i_tx_phy_hold_reg_d_reg[2] 2 -.latch i_rx_phy_rx_en_reg_in i_rx_phy_rx_en_reg 2 -.latch \i_tx_phy_hold_reg_d_reg[7]_in \i_tx_phy_hold_reg_d_reg[7] 2 -.latch \i_tx_phy_hold_reg_d_reg[4]_in \i_tx_phy_hold_reg_d_reg[4] 2 - -.names [131] - 0 -.names [132] - 1 -.names [142] [137] [145] RxError_o -111 0 -.names i_rx_phy_shift_en_reg [134] -1 1 -.names \i_rx_phy_fs_state_reg[0] [135] -1 1 -.names i_rx_phy_rx_active_reg RxActive_o -1 1 -.names i_rx_phy_sync_err_reg [137] -0 1 -.names [547] \i_rx_phy_fs_state_reg[0]_in -0 1 -.names \i_rx_phy_fs_state_reg[1] [139] -1 1 -.names \i_rx_phy_fs_state_reg[2] [140] -1 1 -.names [154] [551] [403] \i_rx_phy_fs_state_reg[1]_in -11- 0 ---1 0 -.names i_rx_phy_byte_err_reg [142] -0 1 -.names [157] [198] [143] -11 0 -.names \i_tx_phy_hold_reg_reg[7] \i_tx_phy_hold_reg_d_reg[7]_in -1 1 -.names i_rx_phy_bit_stuff_err_reg [145] -0 1 -.names \i_tx_phy_hold_reg_reg[0] \i_tx_phy_hold_reg_d_reg[0]_in -1 1 -.names \i_tx_phy_hold_reg_reg[1] \i_tx_phy_hold_reg_d_reg[1]_in -1 1 -.names \i_tx_phy_hold_reg_reg[2] \i_tx_phy_hold_reg_d_reg[2]_in -1 1 -.names \i_tx_phy_hold_reg_reg[3] \i_tx_phy_hold_reg_d_reg[3]_in -1 1 -.names \i_tx_phy_hold_reg_reg[4] \i_tx_phy_hold_reg_d_reg[4]_in -1 1 -.names \i_tx_phy_hold_reg_reg[5] \i_tx_phy_hold_reg_d_reg[5]_in -1 1 -.names \i_tx_phy_hold_reg_reg[6] \i_tx_phy_hold_reg_d_reg[6]_in -1 1 -.names [661] [175] [191] \i_tx_phy_hold_reg_reg[7]_in -111 0 -.names [170] [589] [154] -11 0 -.names [168] i_rx_phy_bit_stuff_err_reg_in -0 1 -.names [171] [195] i_rx_phy_byte_err_reg_in -00 1 -.names [393] [415] [174] [157] -111 0 -.names i_rx_phy_se0_s_reg [158] -1 1 -.names [615] [606] [159] -11 0 -.names [179] [661] \i_tx_phy_hold_reg_reg[0]_in -11 1 -.names [180] [661] \i_tx_phy_hold_reg_reg[1]_in -11 1 -.names [181] [661] \i_tx_phy_hold_reg_reg[2]_in -11 1 -.names [182] [661] \i_tx_phy_hold_reg_reg[3]_in -11 1 -.names [183] [661] \i_tx_phy_hold_reg_reg[4]_in -11 1 -.names [184] [661] \i_tx_phy_hold_reg_reg[5]_in -11 1 -.names [185] [661] \i_tx_phy_hold_reg_reg[6]_in -11 1 -.names [629] [190] [167] -11 0 -.names [374] [431] [236] \i_rx_phy_hold_reg_reg[7]_in [168] -1111 0 -.names \i_tx_phy_state_reg[0] [169] -1 1 -.names [582] [170] -0 1 -.names [217] [212] [193] [171] -00- 1 ---0 1 -.names [519] [602] [194] i_rx_phy_se0_s_reg_in -00- 1 ---0 1 -.names \i_rx_phy_dpll_state_reg[0] [173] -1 1 -.names [612] [197] [174] -00 1 -.names [207] DataOut_i[7] [175] -11 0 -.names [583] [176] -0 1 -.names [583] [177] -0 1 -.names [556] [619] [414] \i_tx_phy_state_reg[0]_in -11- 0 ---1 0 -.names DataOut_i[0] \i_tx_phy_hold_reg_d_reg[0]_in [222] [179] -01- 1 -1-1 1 -.names DataOut_i[1] \i_tx_phy_hold_reg_d_reg[1]_in [222] [180] -01- 1 -1-1 1 -.names DataOut_i[2] \i_tx_phy_hold_reg_d_reg[2]_in [222] [181] -01- 1 -1-1 1 -.names DataOut_i[3] \i_tx_phy_hold_reg_d_reg[3]_in [222] [182] -01- 1 -1-1 1 -.names DataOut_i[4] \i_tx_phy_hold_reg_d_reg[4]_in [222] [183] -01- 1 -1-1 1 -.names DataOut_i[5] \i_tx_phy_hold_reg_d_reg[5]_in [222] [184] -01- 1 -1-1 1 -.names DataOut_i[6] \i_tx_phy_hold_reg_d_reg[6]_in [222] [185] -01- 1 -1-1 1 -.names \i_tx_phy_state_reg[2] [186] -1 1 -.names i_rx_phy_rx_valid1_reg [187] -1 1 -.names \i_rx_phy_dpll_state_reg[1] [188] -1 1 -.names i_rx_phy_rx_valid_r_reg [189] -1 1 -.names [618] [666] [190] -11 0 -.names \i_tx_phy_hold_reg_d_reg[7]_in [222] [191] -11 0 -.names [225] [261] rst \i_rx_phy_dpll_state_reg[0]_in -111 0 -.names i_rx_phy_se0_r_reg [193] -0 1 -.names i_rx_phy_se0_r_reg_in [674] [194] -11 0 -.names i_rx_phy_se0_r_reg_in RxActive_o [195] -11 0 -.names [189] i_rx_phy_se0_r_reg_in [196] -11 0 -.names [634] [197] -0 1 -.names [221] [443] [636] [198] -111 0 -.names \rst_cnt_reg[3] [199] -1 1 -.names \rst_cnt_reg[4] [200] -1 1 -.names \rst_cnt_reg[2] [201] -1 1 -.names \i_tx_phy_state_reg[1] [202] -1 1 -.names \i_rx_phy_one_cnt_reg[2] [203] -1 1 -.names \i_rx_phy_one_cnt_reg[1] [204] -1 1 -.names [612] [471] [205] -11 0 -.names [261] [479] [414] \i_rx_phy_dpll_state_reg[1]_in -11- 0 ---1 0 -.names [222] [207] -0 1 -.names [427] RxValid_o i_rx_phy_rx_valid_r_reg_in -00 0 -.names [255] [348] [404] \i_tx_phy_state_reg[2]_in -11- 0 ---1 0 -.names [585] [238] i_rx_phy_rx_valid1_reg_in -11 0 -.names i_tx_phy_sd_raw_o_reg [211] -1 1 -.names \i_rx_phy_bit_cnt_reg[2] [212] -1 1 -.names \i_tx_phy_bit_cnt_reg[2] [213] -1 1 -.names i_tx_phy_append_eop_reg [214] -1 1 -.names \i_rx_phy_one_cnt_reg[0] [215] -1 1 -.names \i_rx_phy_bit_cnt_reg[0] [216] -1 1 -.names \i_rx_phy_bit_cnt_reg[1] [217] -1 1 -.names [265] [385] \rst_cnt_reg[2]_in -00 1 -.names [430] [276] [651] \i_rx_phy_one_cnt_reg[1]_in -11- 0 ---1 0 -.names [236] i_rx_phy_se0_r_reg_in -0 1 -.names [272] [552] [221] -00 1 -.names i_tx_phy_ld_data_reg [222] -0 1 -.names \i_tx_phy_one_cnt_reg[1] [223] -1 1 -.names [243] \rst_cnt_reg[4]_in -0 1 -.names [465] [299] [260] [225] -11- 0 ---1 0 -.names [652] rst \i_tx_phy_state_reg[1]_in -11 1 -.names [264] [385] \rst_cnt_reg[3]_in -00 1 -.names \i_tx_phy_one_cnt_reg[2] [228] -1 1 -.names i_tx_phy_TxReady_o_reg TxReady_o -1 1 -.names \i_tx_phy_bit_cnt_reg[0] [230] -1 1 -.names \i_tx_phy_bit_cnt_reg[1] [231] -1 1 -.names \i_tx_phy_one_cnt_reg[0] [232] -1 1 -.names [275] [475] \i_tx_phy_bit_cnt_reg[2]_in -00 1 -.names [291] [302] [651] \i_rx_phy_bit_cnt_reg[2]_in -11- 0 ---1 0 -.names [554] [537] [235] -00 1 -.names [272] [553] [236] -11 0 -.names [280] [310] [496] i_tx_phy_sd_raw_o_reg_in -11- 0 ---1 0 -.names [586] [212] rst [473] [238] -1111 0 -.names [477] [658] [414] i_tx_phy_append_eop_reg_in -11- 0 ---1 0 -.names [292] [315] [651] \i_rx_phy_bit_cnt_reg[0]_in -11- 0 ---1 0 -.names [426] [300] [651] \i_rx_phy_one_cnt_reg[0]_in -11- 0 ---1 0 -.names [293] [312] [651] \i_rx_phy_bit_cnt_reg[1]_in -11- 0 ---1 0 -.names [273] [356] [243] -11 0 -.names i_rx_phy_rx_valid_reg RxValid_o -1 1 -.names \i_rx_phy_hold_reg_reg[6] \i_rx_phy_hold_reg_reg[5]_in -1 1 -.names \i_rx_phy_hold_reg_reg[4] \i_rx_phy_hold_reg_reg[3]_in -1 1 -.names \i_rx_phy_hold_reg_reg[0] DataIn_o[0] -1 1 -.names \i_rx_phy_hold_reg_reg[1] \i_rx_phy_hold_reg_reg[0]_in -1 1 -.names \i_rx_phy_hold_reg_reg[2] \i_rx_phy_hold_reg_reg[1]_in -1 1 -.names \i_rx_phy_hold_reg_reg[3] \i_rx_phy_hold_reg_reg[2]_in -1 1 -.names \i_rx_phy_hold_reg_reg[5] \i_rx_phy_hold_reg_reg[4]_in -1 1 -.names \i_rx_phy_hold_reg_reg[7] \i_rx_phy_hold_reg_reg[6]_in -1 1 -.names i_tx_phy_tx_ip_reg [253] -1 1 -.names [428] [307] [475] \i_tx_phy_one_cnt_reg[1]_in -11- 0 ---1 0 -.names [318] [641] [321] [255] -11- 0 ---1 0 -.names [314] [336] [475] \i_tx_phy_bit_cnt_reg[0]_in -11- 0 ---1 0 -.names [305] [340] [475] \i_tx_phy_bit_cnt_reg[1]_in -11- 0 ---1 0 -.names \rst_cnt_reg[1] [258] -1 1 -.names [334] [290] i_tx_phy_TxReady_o_reg_in -11 0 -.names [299] [479] [260] -00 1 -.names [299] [188] [530] [261] -111 0 -.names [423] [306] [475] \i_tx_phy_one_cnt_reg[2]_in -11- 0 ---1 0 -.names [346] [541] [301] i_tx_phy_ld_data_reg_in -00- 1 ---0 1 -.names [425] [199] [279] [264] -11- 0 ---1 0 -.names [425] [201] [281] [265] -11- 0 ---1 0 -.names i_tx_phy_txdp_reg txdp -1 1 -.names i_rx_phy_sd_nrzi_reg \i_rx_phy_hold_reg_reg[7]_in -1 1 -.names i_tx_phy_sd_bs_o_reg [268] -1 1 -.names \rst_cnt_reg[0] [269] -1 1 -.names i_tx_phy_txdn_reg txdn -1 1 -.names i_tx_phy_append_eop_sync3_reg [271] -1 1 -.names [282] [272] -0 1 -.names [328] [425] [371] [273] -00- 1 ---0 1 -.names [424] [338] [475] \i_tx_phy_one_cnt_reg[0]_in -11- 0 ---1 0 -.names [342] [213] [308] [275] -11- 0 ---1 0 -.names [446] [649] [276] -11 0 -.names [586] [187] i_rx_phy_rx_valid_reg_in -11 1 -.names i_tx_phy_txoe_reg i_rx_phy_rx_en_reg_in -1 1 -.names [344] [367] [425] [279] -11- 0 ---1 0 -.names [382] [337] [280] -00 1 -.names [332] [425] [281] -00 1 -.names i_rx_phy_rxdn_s_reg [282] -1 1 -.names i_rx_phy_rxdp_s_reg [283] -1 1 -.names [373] [357] [385] \rst_cnt_reg[1]_in -11- 0 ---1 0 -.names [331] rst i_tx_phy_txdp_reg_in -11 0 -.names [359] RxActive_o [414] i_rx_phy_sd_nrzi_reg_in -11- 0 ---1 0 -.names [429] [360] [403] i_tx_phy_txdn_reg_in -11- 0 ---1 0 -.names [326] [385] \rst_cnt_reg[0]_in -00 1 -.names [351] [339] i_tx_phy_sd_bs_o_reg_in -11 0 -.names [320] [363] [572] [451] [290] -1111 0 -.names [212] [587] [291] -11 0 -.names [216] [587] [292] -11 0 -.names [217] [587] [293] -11 0 -.names i_tx_phy_sft_done_reg i_tx_phy_sft_done_r_reg_in -1 1 -.names i_tx_phy_tx_ip_sync_reg [295] -1 1 -.names i_tx_phy_txoe_r1_reg [296] -1 1 -.names i_tx_phy_append_eop_sync1_reg [297] -1 1 -.names i_tx_phy_append_eop_sync2_reg [298] -1 1 -.names [327] [534] [299] -00 0 -.names [319] [528] [674] [300] -111 0 -.names [363] [541] [592] [301] -111 0 -.names [432] [586] [302] -11 0 -.names i_tx_phy_txoe_r2_reg [303] -1 1 -.names usb_rst_reg usb_rst -1 1 -.names [342] [508] [305] -11 0 -.names [433] [355] [306] -11 0 -.names [448] [355] [307] -11 0 -.names [441] [442] [342] [308] -11- 0 ---1 0 -.names [350] [354] i_tx_phy_append_eop_sync3_reg_in -11 0 -.names [370] [213] [388] [310] -11- 0 ---1 0 -.names [586] [134] [311] -11 0 -.names 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--1 1 -.names n542 n201 n619 -1- 1 --1 1 -.names n138 n276 n621 -1- 1 --1 1 -.names n442 n567 n622 -1- 1 --1 1 -.names n621 n226 n238 n196 n172 n239 n7 n622 n620 -11111111 1 -.names n531 n538 n623 -1- 1 --1 1 -.names n179 n560 n624 -1- 1 --1 1 -.names n534 n166 n625 -1- 1 --1 1 -.names n407 n541 n626 -1- 1 --1 1 -.names n139 n575 n627 -1- 1 --1 1 -.names n138 n429 n628 -1- 1 --1 1 -.names n139 n455 n629 -1- 1 --1 1 -.names n139 n154 n630 -1- 1 --1 1 -.names n568 n150 n631 -1- 1 --1 1 -.names n39 n305 n310 n314 n316 n382 n632 -100111 1 -.names n411 n575 n633 -1- 1 --1 1 -.names n323 n248 n634 -1- 1 --1 1 -.names n194 n323 n453 n635 -1-- 1 --1- 1 ---0 1 -.names n536 n399 n636 -1- 1 --1 1 -.names n190 n127 n637 -1- 1 --1 1 -.names n194 n542 n638 -1- 1 --1 1 -.names n323 n191 n639 -1- 1 --1 1 -.names n214 n306 n531 n680 n641 -1--1 1 --0-1 1 ---11 1 -.names n549 n442 n642 -1- 1 --1 1 -.names n190 n116 n643 -1- 1 --1 1 -.names n139 n400 n645 -1- 1 --1 1 -.names n416 n560 n646 -1- 1 --1 1 -.names n407 n543 n647 -1- 1 --1 1 -.names i_2_ n532 n649 -1- 1 --1 1 -.names n387 n628 n649 n379 n648 -1111 1 -.names n411 n195 n650 -1- 1 --1 1 -.names n195 n166 n651 -1- 1 --1 1 -.names n399 n567 n652 -1- 1 --1 1 -.names n399 n580 n653 -1- 1 --1 1 -.names n97 n233 n704 n616 n499 n685 n271 n654 -1111111 1 -.names n429 n580 n656 -1- 1 --1 1 -.names n429 n277 n657 -1- 1 --1 1 -.names n16 n14 n656 n657 n591 n655 -11111 1 -.names n319 n595 n658 -1- 1 --1 1 -.names i_5_ n194 n512 n659 -1-- 1 --1- 1 ---1 1 -.names n529 n407 n660 -1- 1 --1 1 -.names n277 n153 n661 -1- 1 --1 1 -.names n756 n12 n141 n662 -111 1 -.names n138 n442 n663 -1- 1 --1 1 -.names n194 n438 n664 -1- 1 --1 1 -.names n156 n139 n665 -1- 1 --1 1 -.names n172 n197 n679 n15 n659 n96 n666 -111111 1 -.names n529 n411 n667 -1- 1 --1 1 -.names n429 n576 n668 -1- 1 --1 1 -.names n740 n637 n586 n192 n385 n709 n588 n669 -1111111 1 -.names n106 n104 n651 n395 n270 n160 n342 n757 n670 -11111111 1 -.names n658 n435 n633 n672 -111 1 -.names n678 n725 n676 n638 n603 n605 n673 -111111 1 -.names n141 n227 n110 n6 n704 n756 n674 -111111 1 -.names n388 n177 n558 n377 n352 n634 n675 -111111 1 -.names n399 n438 n676 -1- 1 --1 1 -.names n166 n552 n677 -1- 1 --1 1 -.names n442 n430 n678 -1- 1 --1 1 -.names n429 n457 n679 -1- 1 --1 1 -.names n429 n154 n680 -1- 1 --1 1 -.names n407 n167 n681 -1- 1 --1 1 -.names n194 n441 n682 -1- 1 --1 1 -.names n156 n411 n683 -1- 1 --1 1 -.names n194 n488 n684 -1- 1 --1 1 -.names n429 n541 n685 -1- 1 --1 1 -.names n275 n564 n433 n686 -1-- 1 --1- 1 ---1 1 -.names n166 n277 n687 -1- 1 --1 1 -.names n233 n616 n13 n688 -111 1 -.names n166 n457 n689 -1- 1 --1 1 -.names n542 n439 n690 -1- 1 --1 1 -.names i_3_ n442 n453 n691 -0-- 1 --1- 1 ---0 1 -.names n665 n262 n628 n660 n636 n635 n600 n692 -1111111 1 -.names n275 n408 n693 -1- 1 --1 1 -.names n275 n538 n694 -1- 1 --1 1 -.names n539 n189 n695 -1- 1 --1 1 -.names n166 n579 n698 -1- 1 --1 1 -.names n407 n533 n337 n699 -1-- 1 --1- 1 ---1 1 -.names n200 n364 n700 -1- 1 --1 1 -.names n275 n200 n467 n701 -1-- 1 --1- 1 ---1 1 -.names n541 n442 n702 -1- 1 --1 1 -.names n288 n547 n703 -1- 1 --1 1 -.names n429 n542 n704 -1- 1 --1 1 -.names n149 n551 n705 -1- 1 --1 1 -.names n151 n373 n706 -1- 1 --1 1 -.names n166 n438 n707 -1- 1 --1 1 -.names n194 n315 n708 -1- 1 --1 1 -.names n323 n594 n709 -1- 1 --1 1 -.names n112 n429 n179 n280 n710 -11-- 1 -1-1- 1 -1--1 1 -.names n429 n552 n711 -1- 1 --1 1 -.names i_7_ n204 n279 n712 -0-- 1 --1- 1 ---1 1 -.names n528 n139 n354 n713 -1-- 1 --1- 1 ---1 1 -.names n645 n197 n95 n685 n677 n572 n175 n716 -1111111 1 -.names n543 n578 n717 -1- 1 --1 1 -.names n411 n200 n550 n718 -1-- 1 --1- 1 ---1 1 -.names n119 n295 n399 n546 n719 -11-- 1 -1-1- 1 -1--1 1 -.names n138 n275 n720 -1- 1 --1 1 -.names i_7_ n179 n208 n682 n721 -0--1 1 --1-1 1 ---11 1 -.names n323 n544 n722 -1- 1 --1 1 -.names n115 n317 n723 -1- 1 --1 1 -.names i_3_ i_5_ n279 n399 n724 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names n407 n156 n725 -1- 1 --1 1 -.names n335 n453 n531 n724 n728 -1--1 1 --0-1 1 ---11 1 -.names n127 n297 n729 -1- 1 --1 1 -.names i_7_ n204 n453 n730 -1-- 1 --1- 1 ---0 1 -.names n275 n184 n186 n732 -1-- 1 --1- 1 ---1 1 -.names n732 n403 n326 n731 -11- 1 -1-1 1 -.names n139 n441 n733 -1- 1 --1 1 -.names n531 n184 n483 n734 -1-- 1 --1- 1 ---1 1 -.names n687 n186 n427 n735 -11- 1 -1-1 1 -.names n439 n154 n179 n180 n736 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n528 n153 n275 n190 n737 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n531 n433 n149 n125 n738 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n319 n191 n740 -1- 1 --1 1 -.names n552 n153 n741 -1- 1 --1 1 -.names n514 n108 n740 n741 n739 -1111 1 -.names i_8_ n214 n483 n743 -1-- 1 --1- 1 ---1 1 -.names n743 n199 n354 n399 n742 -11-- 1 -1-1- 1 -1--1 1 -.names i_3_ n442 n453 n742 n744 -1--1 1 --1-1 1 ---01 1 -.names n194 n306 n535 n745 -1-- 1 --0- 1 ---1 1 -.names n468 n411 n466 n200 n746 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n153 n510 n531 n543 n747 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n747 n416 n738 n737 n748 -11-- 1 -1-11 1 -.names i_0_ i_2_ i_7_ n323 n750 -0--- 1 --0-- 1 ---0- 1 ----1 1 -.names n254 n46 n750 n366 n129 n40 n749 -111111 1 -.names n190 n306 n478 n595 n751 -10-- 1 -1-1- 1 --0-1 1 ---11 1 -.names n481 n149 n752 -1- 1 --1 1 -.names n354 n166 n550 n753 -1-- 1 --1- 1 ---1 1 -.names n535 n399 n407 n190 n754 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n369 n269 n683 n755 -111 1 -.names i_4_ i_6_ n512 n756 -1-- 1 --1- 1 ---1 1 -.names n173 n163 n700 n121 n741 n228 n757 -111111 1 -.names n142 n536 n194 n758 -11- 1 -1-1 1 -.names i_2_ i_5_ n762 n763 n759 -0--- 1 --0-- 1 ---1- 1 ----1 1 -.names i_3_ n416 n578 n760 -1-- 1 --1- 1 ---1 1 -.names n482 n568 n761 -1- 1 --1 1 -.names i_1_ i_4_ n189 n762 -11- 1 -1-1 1 -.names i_1_ i_4_ n166 n763 -00- 1 -0-1 1 -.end diff --git a/fpga_flow/benchmarks/Blif/MCNC_big20/bigkey.blif b/fpga_flow/benchmarks/Blif/MCNC_big20/bigkey.blif deleted file mode 100644 index aeae8a903..000000000 --- a/fpga_flow/benchmarks/Blif/MCNC_big20/bigkey.blif +++ /dev/null @@ -1,5474 +0,0 @@ -.model TOP -.inputs Pstart_0_ Pkey_255_ Pkey_254_ Pkey_253_ Pkey_252_ Pkey_251_ Pkey_250_ \ -Pkey_249_ Pkey_248_ Pkey_247_ Pkey_246_ Pkey_245_ Pkey_244_ Pkey_243_ \ -Pkey_242_ Pkey_241_ Pkey_240_ Pkey_239_ Pkey_238_ Pkey_237_ Pkey_236_ \ -Pkey_235_ Pkey_234_ Pkey_233_ Pkey_232_ Pkey_231_ Pkey_230_ Pkey_229_ \ -Pkey_228_ Pkey_227_ Pkey_226_ Pkey_225_ Pkey_224_ Pkey_223_ Pkey_222_ \ -Pkey_221_ Pkey_220_ Pkey_219_ Pkey_218_ Pkey_217_ Pkey_216_ Pkey_215_ \ -Pkey_214_ Pkey_213_ Pkey_212_ Pkey_211_ Pkey_210_ Pkey_209_ Pkey_208_ \ -Pkey_207_ Pkey_206_ Pkey_205_ Pkey_204_ Pkey_203_ Pkey_202_ Pkey_201_ \ -Pkey_200_ Pkey_199_ Pkey_198_ Pkey_197_ Pkey_196_ Pkey_195_ Pkey_194_ \ -Pkey_193_ Pkey_192_ Pkey_191_ Pkey_190_ Pkey_189_ Pkey_188_ Pkey_187_ \ -Pkey_186_ Pkey_185_ Pkey_184_ Pkey_183_ Pkey_182_ Pkey_181_ Pkey_180_ \ -Pkey_179_ Pkey_178_ Pkey_177_ Pkey_176_ Pkey_175_ Pkey_174_ Pkey_173_ \ -Pkey_172_ Pkey_171_ Pkey_170_ Pkey_169_ Pkey_168_ Pkey_167_ Pkey_166_ \ -Pkey_165_ Pkey_164_ Pkey_163_ Pkey_162_ Pkey_161_ Pkey_160_ Pkey_159_ \ -Pkey_158_ Pkey_157_ Pkey_156_ Pkey_155_ Pkey_154_ Pkey_153_ Pkey_152_ \ -Pkey_151_ Pkey_150_ Pkey_149_ Pkey_148_ Pkey_147_ Pkey_146_ Pkey_145_ \ -Pkey_144_ Pkey_143_ Pkey_142_ Pkey_141_ Pkey_140_ Pkey_139_ Pkey_138_ \ -Pkey_137_ Pkey_136_ Pkey_135_ Pkey_134_ Pkey_133_ Pkey_132_ Pkey_131_ \ -Pkey_130_ Pkey_129_ Pkey_128_ Pkey_127_ Pkey_126_ Pkey_125_ Pkey_124_ \ -Pkey_123_ Pkey_122_ Pkey_121_ Pkey_120_ Pkey_119_ Pkey_118_ Pkey_117_ \ -Pkey_116_ Pkey_115_ Pkey_114_ Pkey_113_ Pkey_112_ Pkey_111_ Pkey_110_ \ -Pkey_109_ Pkey_108_ Pkey_107_ Pkey_106_ Pkey_105_ Pkey_104_ Pkey_103_ \ -Pkey_102_ Pkey_101_ Pkey_100_ Pkey_99_ Pkey_98_ Pkey_97_ Pkey_96_ Pkey_95_ \ -Pkey_94_ Pkey_93_ Pkey_92_ Pkey_91_ Pkey_90_ Pkey_89_ Pkey_88_ Pkey_87_ \ -Pkey_86_ Pkey_85_ Pkey_84_ Pkey_83_ Pkey_82_ Pkey_81_ Pkey_80_ Pkey_79_ \ -Pkey_78_ Pkey_77_ Pkey_76_ Pkey_75_ Pkey_74_ Pkey_73_ Pkey_72_ Pkey_71_ \ -Pkey_70_ Pkey_69_ Pkey_68_ Pkey_67_ Pkey_66_ Pkey_65_ Pkey_64_ Pkey_63_ \ -Pkey_62_ Pkey_61_ Pkey_60_ Pkey_59_ Pkey_58_ Pkey_57_ Pkey_56_ Pkey_55_ \ -Pkey_54_ Pkey_53_ Pkey_52_ Pkey_51_ Pkey_50_ Pkey_49_ Pkey_48_ Pkey_47_ \ -Pkey_46_ Pkey_45_ Pkey_44_ Pkey_43_ Pkey_42_ Pkey_41_ Pkey_40_ Pkey_39_ \ -Pkey_38_ Pkey_37_ Pkey_36_ Pkey_35_ Pkey_34_ Pkey_33_ Pkey_32_ Pkey_31_ \ -Pkey_30_ Pkey_29_ Pkey_28_ Pkey_27_ Pkey_26_ Pkey_25_ Pkey_24_ Pkey_23_ \ -Pkey_22_ Pkey_21_ Pkey_20_ Pkey_19_ Pkey_18_ Pkey_17_ Pkey_16_ Pkey_15_ \ -Pkey_14_ Pkey_13_ Pkey_12_ Pkey_11_ Pkey_10_ Pkey_9_ Pkey_8_ Pkey_7_ Pkey_6_ \ -Pkey_5_ Pkey_4_ Pkey_3_ Pkey_2_ Pkey_1_ Pkey_0_ Pencrypt_0_ Pcount_3_ \ -Pcount_2_ Pcount_1_ Pcount_0_ PCLK -.outputs Pnew_count_3_ Pnew_count_2_ Pnew_count_1_ Pnew_count_0_ \ -Pdata_ready_0_ PKSi_191_ PKSi_190_ PKSi_189_ PKSi_188_ PKSi_187_ PKSi_186_ \ -PKSi_185_ PKSi_184_ PKSi_183_ PKSi_182_ PKSi_181_ PKSi_180_ PKSi_179_ \ -PKSi_178_ PKSi_177_ PKSi_176_ PKSi_175_ PKSi_174_ PKSi_173_ PKSi_172_ \ -PKSi_171_ PKSi_170_ PKSi_169_ PKSi_168_ PKSi_167_ PKSi_166_ PKSi_165_ \ -PKSi_164_ PKSi_163_ PKSi_162_ PKSi_161_ PKSi_160_ PKSi_159_ PKSi_158_ \ -PKSi_157_ PKSi_156_ PKSi_155_ PKSi_154_ PKSi_153_ PKSi_152_ PKSi_151_ \ -PKSi_150_ PKSi_149_ PKSi_148_ PKSi_147_ PKSi_146_ PKSi_145_ PKSi_144_ \ -PKSi_143_ PKSi_142_ PKSi_141_ PKSi_140_ PKSi_139_ PKSi_138_ PKSi_137_ \ -PKSi_136_ PKSi_135_ PKSi_134_ PKSi_133_ PKSi_132_ PKSi_131_ PKSi_130_ \ -PKSi_129_ PKSi_128_ PKSi_127_ PKSi_126_ PKSi_125_ PKSi_124_ PKSi_123_ \ -PKSi_122_ PKSi_121_ PKSi_120_ PKSi_119_ PKSi_118_ PKSi_117_ PKSi_116_ \ -PKSi_115_ PKSi_114_ PKSi_113_ PKSi_112_ PKSi_111_ PKSi_110_ PKSi_109_ \ -PKSi_108_ PKSi_107_ PKSi_106_ PKSi_105_ PKSi_104_ PKSi_103_ PKSi_102_ \ -PKSi_101_ PKSi_100_ PKSi_99_ PKSi_98_ PKSi_97_ PKSi_96_ PKSi_95_ PKSi_94_ \ -PKSi_93_ PKSi_92_ PKSi_91_ PKSi_90_ PKSi_89_ PKSi_88_ PKSi_87_ PKSi_86_ \ -PKSi_85_ PKSi_84_ PKSi_83_ PKSi_82_ PKSi_81_ PKSi_80_ PKSi_79_ PKSi_78_ \ -PKSi_77_ PKSi_76_ PKSi_75_ PKSi_74_ PKSi_73_ PKSi_72_ PKSi_71_ PKSi_70_ \ -PKSi_69_ PKSi_68_ PKSi_67_ PKSi_66_ PKSi_65_ PKSi_64_ PKSi_63_ PKSi_62_ \ -PKSi_61_ PKSi_60_ PKSi_59_ PKSi_58_ PKSi_57_ PKSi_56_ PKSi_55_ PKSi_54_ \ -PKSi_53_ PKSi_52_ PKSi_51_ PKSi_50_ PKSi_49_ PKSi_48_ PKSi_47_ PKSi_46_ \ -PKSi_45_ PKSi_44_ PKSi_43_ PKSi_42_ PKSi_41_ PKSi_40_ PKSi_39_ PKSi_38_ \ -PKSi_37_ PKSi_36_ PKSi_35_ PKSi_34_ PKSi_33_ PKSi_32_ PKSi_31_ PKSi_30_ \ -PKSi_29_ PKSi_28_ PKSi_27_ PKSi_26_ PKSi_25_ PKSi_24_ PKSi_23_ PKSi_22_ \ -PKSi_21_ PKSi_20_ PKSi_19_ PKSi_18_ PKSi_17_ PKSi_16_ PKSi_15_ PKSi_14_ \ -PKSi_13_ PKSi_12_ PKSi_11_ PKSi_10_ PKSi_9_ PKSi_8_ PKSi_7_ PKSi_6_ PKSi_5_ \ -PKSi_4_ PKSi_3_ PKSi_2_ PKSi_1_ PKSi_0_ -.latch N_N2733 PKSi_79_ re PCLK 2 -.latch N_N2734 PKSi_92_ re PCLK 2 -.latch N_N2735 [333] re PCLK 2 -.latch N_N2736 N_N2737 re PCLK 2 -.latch N_N2738 PKSi_75_ re PCLK 2 -.latch N_N2739 PKSi_84_ re PCLK 2 -.latch N_N2740 N_N2741 re PCLK 2 -.latch N_N2742 PKSi_82_ re PCLK 2 -.latch N_N2743 PKSi_93_ re PCLK 2 -.latch N_N2744 PKSi_85_ re PCLK 2 -.latch N_N2745 N_N2746 re PCLK 2 -.latch N_N2747 PKSi_73_ re PCLK 2 -.latch N_N2748 N_N2749 re PCLK 2 -.latch N_N2750 PKSi_80_ re PCLK 2 -.latch N_N2751 PKSi_72_ re PCLK 2 -.latch N_N2752 PKSi_94_ re PCLK 2 -.latch N_N2753 PKSi_86_ re PCLK 2 -.latch N_N2754 PKSi_74_ re PCLK 2 -.latch N_N2755 PKSi_83_ re PCLK 2 -.latch N_N2756 N_N2757 re PCLK 2 -.latch N_N2758 PKSi_89_ re PCLK 2 -.latch N_N2759 PKSi_91_ re PCLK 2 -.latch N_N2760 PKSi_81_ re PCLK 2 -.latch N_N2761 PKSi_77_ re PCLK 2 -.latch N_N2762 PKSi_87_ re PCLK 2 -.latch N_N2763 PKSi_78_ re PCLK 2 -.latch N_N2764 PKSi_95_ re PCLK 2 -.latch N_N2765 PKSi_76_ re PCLK 2 -.latch N_N2766 PKSi_55_ re PCLK 2 -.latch N_N2767 PKSi_68_ re PCLK 2 -.latch N_N2768 PKSi_64_ re PCLK 2 -.latch N_N2769 N_N2770 re PCLK 2 -.latch N_N2771 PKSi_51_ re PCLK 2 -.latch N_N2772 PKSi_60_ re PCLK 2 -.latch N_N2773 N_N2774 re PCLK 2 -.latch N_N2775 PKSi_58_ re PCLK 2 -.latch N_N2776 PKSi_69_ re PCLK 2 -.latch N_N2777 PKSi_61_ re PCLK 2 -.latch N_N2778 N_N2779 re PCLK 2 -.latch N_N2780 PKSi_49_ re PCLK 2 -.latch N_N2781 PKSi_66_ re PCLK 2 -.latch N_N2782 PKSi_56_ re PCLK 2 -.latch N_N2783 PKSi_48_ re PCLK 2 -.latch N_N2784 PKSi_70_ re PCLK 2 -.latch N_N2785 PKSi_62_ re PCLK 2 -.latch N_N2786 PKSi_50_ re PCLK 2 -.latch N_N2787 PKSi_59_ re PCLK 2 -.latch N_N2788 N_N2789 re PCLK 2 -.latch N_N2790 PKSi_65_ re PCLK 2 -.latch N_N2791 PKSi_67_ re PCLK 2 -.latch N_N2792 PKSi_57_ re PCLK 2 -.latch N_N2793 PKSi_53_ re PCLK 2 -.latch N_N2794 PKSi_63_ re PCLK 2 -.latch N_N2795 PKSi_54_ re PCLK 2 -.latch N_N2796 PKSi_71_ re PCLK 2 -.latch N_N2797 PKSi_52_ re PCLK 2 -.latch N_N2798 PKSi_31_ re PCLK 2 -.latch N_N2799 PKSi_44_ re PCLK 2 -.latch N_N2800 PKSi_40_ re PCLK 2 -.latch N_N2801 N_N2802 re PCLK 2 -.latch N_N2803 PKSi_27_ re PCLK 2 -.latch N_N2804 PKSi_36_ re PCLK 2 -.latch N_N2805 N_N2806 re PCLK 2 -.latch N_N2807 PKSi_34_ re PCLK 2 -.latch N_N2808 PKSi_45_ re PCLK 2 -.latch N_N2809 PKSi_37_ re PCLK 2 -.latch N_N2810 N_N2811 re PCLK 2 -.latch N_N2812 PKSi_25_ re PCLK 2 -.latch N_N2813 PKSi_42_ re PCLK 2 -.latch N_N2814 PKSi_32_ re PCLK 2 -.latch N_N2815 PKSi_24_ re PCLK 2 -.latch N_N2816 PKSi_46_ re PCLK 2 -.latch N_N2817 PKSi_38_ re PCLK 2 -.latch N_N2818 PKSi_26_ re PCLK 2 -.latch N_N2819 PKSi_35_ re PCLK 2 -.latch N_N2820 N_N2821 re PCLK 2 -.latch N_N2822 PKSi_41_ re PCLK 2 -.latch N_N2823 PKSi_43_ re PCLK 2 -.latch N_N2824 PKSi_33_ re PCLK 2 -.latch N_N2825 PKSi_29_ re PCLK 2 -.latch N_N2826 PKSi_39_ re PCLK 2 -.latch N_N2827 PKSi_30_ re PCLK 2 -.latch N_N2828 PKSi_47_ re PCLK 2 -.latch N_N2829 PKSi_28_ re PCLK 2 -.latch N_N2830 PKSi_7_ re PCLK 2 -.latch N_N2831 PKSi_20_ re PCLK 2 -.latch N_N2832 PKSi_16_ re PCLK 2 -.latch N_N2833 N_N2834 re PCLK 2 -.latch N_N2835 PKSi_3_ re PCLK 2 -.latch N_N2836 PKSi_12_ re PCLK 2 -.latch N_N2837 N_N2838 re PCLK 2 -.latch N_N2839 PKSi_10_ re PCLK 2 -.latch N_N2840 PKSi_21_ re PCLK 2 -.latch N_N2841 PKSi_13_ re PCLK 2 -.latch N_N2842 N_N2843 re PCLK 2 -.latch N_N2844 PKSi_1_ re PCLK 2 -.latch N_N2845 PKSi_18_ re PCLK 2 -.latch N_N2846 PKSi_8_ re PCLK 2 -.latch N_N2847 PKSi_0_ re PCLK 2 -.latch N_N2848 PKSi_22_ re PCLK 2 -.latch N_N2849 PKSi_14_ re PCLK 2 -.latch N_N2850 PKSi_2_ re PCLK 2 -.latch N_N2851 PKSi_11_ re PCLK 2 -.latch N_N2852 N_N2853 re PCLK 2 -.latch N_N2854 PKSi_17_ re PCLK 2 -.latch N_N2855 PKSi_19_ re PCLK 2 -.latch N_N2856 PKSi_9_ re PCLK 2 -.latch N_N2857 PKSi_5_ re PCLK 2 -.latch N_N2858 PKSi_15_ re PCLK 2 -.latch N_N2859 PKSi_6_ re PCLK 2 -.latch N_N2860 PKSi_23_ re PCLK 2 -.latch N_N2861 PKSi_4_ re PCLK 2 -.latch N_N2862 PKSi_183_ re PCLK 2 -.latch N_N2863 PKSi_173_ re PCLK 2 -.latch N_N2864 N_N2865 re PCLK 2 -.latch N_N2866 PKSi_185_ re PCLK 2 -.latch N_N2867 PKSi_169_ re PCLK 2 -.latch N_N2868 PKSi_176_ re PCLK 2 -.latch N_N2869 PKSi_188_ re PCLK 2 -.latch N_N2870 [253] re PCLK 2 -.latch N_N2871 PKSi_179_ re PCLK 2 -.latch N_N2872 PKSi_172_ re PCLK 2 -.latch N_N2873 PKSi_186_ re PCLK 2 -.latch N_N2874 PKSi_177_ re PCLK 2 -.latch N_N2875 PKSi_180_ re PCLK 2 -.latch N_N2876 N_N2877 re PCLK 2 -.latch N_N2878 N_N2879 re PCLK 2 -.latch N_N2880 N_N2881 re PCLK 2 -.latch N_N2882 PKSi_175_ re PCLK 2 -.latch N_N2883 PKSi_182_ re PCLK 2 -.latch N_N2884 N_N2885 re PCLK 2 -.latch N_N2886 PKSi_171_ re PCLK 2 -.latch N_N2887 PKSi_189_ re PCLK 2 -.latch N_N2888 N_N2889 re PCLK 2 -.latch N_N2890 PKSi_184_ re PCLK 2 -.latch N_N2891 PKSi_178_ re PCLK 2 -.latch N_N2892 [234] re PCLK 2 -.latch N_N2893 PKSi_170_ re PCLK 2 -.latch N_N2894 PKSi_174_ re PCLK 2 -.latch N_N2895 PKSi_190_ re PCLK 2 -.latch N_N2896 PKSi_159_ re PCLK 2 -.latch N_N2897 PKSi_149_ re PCLK 2 -.latch N_N2898 N_N2899 re PCLK 2 -.latch N_N2900 PKSi_161_ re PCLK 2 -.latch N_N2901 PKSi_145_ re PCLK 2 -.latch N_N2902 PKSi_152_ re PCLK 2 -.latch N_N2903 PKSi_164_ re PCLK 2 -.latch N_N2904 PKSi_157_ re PCLK 2 -.latch N_N2905 PKSi_155_ re PCLK 2 -.latch N_N2906 PKSi_148_ re PCLK 2 -.latch N_N2907 PKSi_162_ re PCLK 2 -.latch N_N2908 N_N2909 re PCLK 2 -.latch N_N2910 PKSi_156_ re PCLK 2 -.latch N_N2911 PKSi_153_ re PCLK 2 -.latch N_N2912 PKSi_163_ re PCLK 2 -.latch N_N2913 PKSi_144_ re PCLK 2 -.latch N_N2914 PKSi_151_ re PCLK 2 -.latch N_N2915 PKSi_158_ re PCLK 2 -.latch N_N2916 N_N2917 re PCLK 2 -.latch N_N2918 PKSi_147_ re PCLK 2 -.latch N_N2919 PKSi_165_ re PCLK 2 -.latch N_N2920 N_N2921 re PCLK 2 -.latch N_N2922 PKSi_160_ re PCLK 2 -.latch N_N2923 PKSi_154_ re PCLK 2 -.latch N_N2924 PKSi_167_ re PCLK 2 -.latch N_N2925 PKSi_146_ re PCLK 2 -.latch N_N2926 PKSi_150_ re PCLK 2 -.latch N_N2927 PKSi_166_ re PCLK 2 -.latch N_N2928 PKSi_135_ re PCLK 2 -.latch N_N2929 PKSi_125_ re PCLK 2 -.latch N_N2930 N_N2931 re PCLK 2 -.latch N_N2932 PKSi_137_ re PCLK 2 -.latch N_N2933 PKSi_121_ re PCLK 2 -.latch N_N2934 PKSi_128_ re PCLK 2 -.latch N_N2935 PKSi_140_ re PCLK 2 -.latch N_N2936 PKSi_133_ re PCLK 2 -.latch N_N2937 PKSi_131_ re PCLK 2 -.latch N_N2938 PKSi_124_ re PCLK 2 -.latch N_N2939 PKSi_138_ re PCLK 2 -.latch N_N2940 PKSi_129_ re PCLK 2 -.latch N_N2941 PKSi_132_ re PCLK 2 -.latch N_N2942 N_N2943 re PCLK 2 -.latch N_N2944 N_N2945 re PCLK 2 -.latch N_N2946 PKSi_120_ re PCLK 2 -.latch N_N2947 PKSi_127_ re PCLK 2 -.latch N_N2948 PKSi_134_ re PCLK 2 -.latch N_N2949 N_N2950 re PCLK 2 -.latch N_N2951 PKSi_123_ re PCLK 2 -.latch N_N2952 PKSi_141_ re PCLK 2 -.latch N_N2953 N_N2954 re PCLK 2 -.latch N_N2955 PKSi_136_ re PCLK 2 -.latch N_N2956 PKSi_130_ re PCLK 2 -.latch N_N2957 [282] re PCLK 2 -.latch N_N2958 PKSi_122_ re PCLK 2 -.latch N_N2959 PKSi_126_ re PCLK 2 -.latch N_N2960 PKSi_142_ re PCLK 2 -.latch N_N2961 PKSi_111_ re PCLK 2 -.latch N_N2962 PKSi_101_ re PCLK 2 -.latch N_N2963 N_N2964 re PCLK 2 -.latch N_N2965 PKSi_113_ re PCLK 2 -.latch N_N2966 PKSi_97_ re PCLK 2 -.latch N_N2967 PKSi_104_ re PCLK 2 -.latch N_N2968 PKSi_116_ re PCLK 2 -.latch N_N2969 PKSi_109_ re PCLK 2 -.latch N_N2970 PKSi_107_ re PCLK 2 -.latch N_N2971 PKSi_100_ re PCLK 2 -.latch N_N2972 PKSi_114_ re PCLK 2 -.latch N_N2973 PKSi_105_ re PCLK 2 -.latch N_N2974 PKSi_108_ re PCLK 2 -.latch N_N2975 N_N2976 re PCLK 2 -.latch N_N2977 PKSi_115_ re PCLK 2 -.latch N_N2978 PKSi_96_ re PCLK 2 -.latch N_N2979 PKSi_103_ re PCLK 2 -.latch N_N2980 PKSi_110_ re PCLK 2 -.latch N_N2981 N_N2982 re PCLK 2 -.latch N_N2983 PKSi_99_ re PCLK 2 -.latch N_N2984 PKSi_117_ re PCLK 2 -.latch N_N2985 N_N2986 re PCLK 2 -.latch N_N2987 PKSi_112_ re PCLK 2 -.latch N_N2988 PKSi_106_ re PCLK 2 -.latch N_N2989 PKSi_119_ re PCLK 2 -.latch N_N2990 PKSi_98_ re PCLK 2 -.latch N_N2991 PKSi_102_ re PCLK 2 -.latch N_N2992 PKSi_118_ re PCLK 2 -.names n17 Pnew_count_3_ -0 1 -.names n18 Pnew_count_2_ -0 1 -.names n19 Pnew_count_1_ -0 1 -.names n20 Pnew_count_0_ -0 1 -.names n16 Pdata_ready_0_ -0 1 -.names Pstart_0_ Pencrypt_0_ n15 -0- 1 --1 1 -.names Pstart_0_ Pencrypt_0_ n13 -0- 1 --0 1 -.names Pstart_0_ Pencrypt_0_ n245 n11 -1-- 1 --1- 1 ---1 1 -.names Pstart_0_ Pencrypt_0_ n245 n1741 -001 1 -.names n925 Pstart_0_ n924 n16 -11- 1 -1-1 1 -.names Pstart_0_ n15 n937 n17 -11- 1 --11 1 -.names Pencrypt_0_ n249 n930 n934 n18 -1-01 1 --101 1 -.names Pcount_0_ n15 n929 n928 n19 -011- 1 --111 1 -.names Pstart_0_ Pcount_0_ n15 n20 -1-1 1 --11 1 -.names Pkey_62_ n13 n586 n587 n21 -0-11 1 --111 1 -.names n21 N_N2862 -0 1 -.names Pkey_195_ n13 n583 n584 n22 -0-11 1 --111 1 -.names n22 N_N2863 -0 1 -.names Pkey_203_ n13 n580 n581 n23 -0-11 1 --111 1 -.names n23 N_N2864 -0 1 -.names Pkey_211_ n13 n577 n578 n24 -0-11 1 --111 1 -.names n24 N_N2866 -0 1 -.names Pkey_219_ n13 n574 n575 n25 -0-11 1 --111 1 -.names n25 N_N2867 -0 1 -.names Pkey_196_ n13 n571 n572 n26 -0-11 1 --111 1 -.names n26 N_N2868 -0 1 -.names Pkey_204_ n13 n568 n569 n27 -0-11 1 --111 1 -.names n27 N_N2869 -0 1 -.names Pkey_212_ n13 n565 n566 n28 -0-11 1 --111 1 -.names n28 N_N2870 -0 1 -.names Pkey_220_ n13 n562 n563 n29 -0-11 1 --111 1 -.names n29 N_N2871 -0 1 -.names Pkey_228_ n13 n559 n560 n30 -0-11 1 --111 1 -.names n30 N_N2872 -0 1 -.names Pkey_172_ n13 n556 n557 n31 -0-11 1 --111 1 -.names n31 N_N2873 -0 1 -.names Pkey_244_ n13 n554 n555 n32 -0-11 1 --111 1 -.names n32 N_N2874 -0 1 -.names Pkey_252_ n13 n551 n552 n33 -0-11 1 --111 1 -.names n33 N_N2875 -0 1 -.names Pkey_197_ n13 n548 n549 n34 -0-11 1 --111 1 -.names n34 N_N2876 -0 1 -.names Pkey_205_ n13 n545 n546 n35 -0-11 1 --111 1 -.names n35 N_N2878 -0 1 -.names Pkey_213_ n13 n542 n543 n36 -0-11 1 --111 1 -.names n36 N_N2880 -0 1 -.names Pkey_221_ n13 n539 n540 n37 -0-11 1 --111 1 -.names n37 N_N2882 -0 1 -.names Pkey_229_ n13 n536 n537 n38 -0-11 1 --111 1 -.names n38 N_N2883 -0 1 -.names Pkey_237_ n13 n533 n534 n39 -0-11 1 --111 1 -.names n39 N_N2884 -0 1 -.names Pkey_245_ n13 n530 n531 n40 -0-11 1 --111 1 -.names n40 N_N2886 -0 1 -.names Pkey_253_ n13 n527 n528 n41 -0-11 1 --111 1 -.names n41 N_N2887 -0 1 -.names Pkey_198_ n13 n524 n525 n42 -0-11 1 --111 1 -.names n42 N_N2888 -0 1 -.names Pkey_206_ n13 n521 n522 n43 -0-11 1 --111 1 -.names n43 N_N2890 -0 1 -.names Pkey_214_ n13 n518 n519 n44 -0-11 1 --111 1 -.names n44 N_N2891 -0 1 -.names Pkey_222_ n13 n515 n516 n45 -0-11 1 --111 1 -.names n45 N_N2892 -0 1 -.names Pkey_230_ n13 n512 n513 n46 -0-11 1 --111 1 -.names n46 N_N2893 -0 1 -.names Pkey_238_ n13 n509 n510 n47 -0-11 1 --111 1 -.names n47 N_N2894 -0 1 -.names Pkey_246_ n13 n506 n507 n48 -0-11 1 --111 1 -.names n48 N_N2895 -0 1 -.names Pkey_254_ n13 n503 n504 n49 -0-11 1 --111 1 -.names n49 N_N2896 -0 1 -.names Pkey_131_ n13 n500 n501 n50 -0-11 1 --111 1 -.names n50 N_N2897 -0 1 -.names Pkey_139_ n13 n497 n498 n51 -0-11 1 --111 1 -.names n51 N_N2898 -0 1 -.names Pkey_147_ n13 n494 n495 n52 -0-11 1 --111 1 -.names n52 N_N2900 -0 1 -.names Pkey_155_ n13 n491 n492 n53 -0-11 1 --111 1 -.names n53 N_N2901 -0 1 -.names Pkey_132_ n13 n488 n489 n54 -0-11 1 --111 1 -.names n54 N_N2902 -0 1 -.names Pkey_140_ n13 n485 n486 n55 -0-11 1 --111 1 -.names n55 N_N2903 -0 1 -.names Pkey_148_ n13 n482 n483 n56 -0-11 1 --111 1 -.names n56 N_N2904 -0 1 -.names Pkey_156_ n13 n479 n480 n57 -0-11 1 --111 1 -.names n57 N_N2905 -0 1 -.names Pkey_164_ n13 n476 n477 n58 -0-11 1 --111 1 -.names n58 N_N2906 -0 1 -.names Pkey_172_ n13 n473 n474 n59 -0-11 1 --111 1 -.names n59 N_N2907 -0 1 -.names Pkey_180_ n13 n470 n471 n60 -0-11 1 --111 1 -.names n60 N_N2908 -0 1 -.names Pkey_188_ n13 n467 n468 n61 -0-11 1 --111 1 -.names n61 N_N2910 -0 1 -.names Pkey_133_ n13 n464 n465 n62 -0-11 1 --111 1 -.names n62 N_N2911 -0 1 -.names Pkey_141_ n13 n461 n462 n63 -0-11 1 --111 1 -.names n63 N_N2912 -0 1 -.names Pkey_149_ n13 n458 n459 n64 -0-11 1 --111 1 -.names n64 N_N2913 -0 1 -.names Pkey_157_ n13 n455 n456 n65 -0-11 1 --111 1 -.names n65 N_N2914 -0 1 -.names Pkey_165_ n13 n452 n453 n66 -0-11 1 --111 1 -.names n66 N_N2915 -0 1 -.names Pkey_173_ n13 n449 n450 n67 -0-11 1 --111 1 -.names n67 N_N2916 -0 1 -.names Pkey_181_ n13 n446 n447 n68 -0-11 1 --111 1 -.names n68 N_N2918 -0 1 -.names Pkey_189_ n13 n443 n444 n69 -0-11 1 --111 1 -.names n69 N_N2919 -0 1 -.names Pkey_134_ n13 n440 n441 n70 -0-11 1 --111 1 -.names n70 N_N2920 -0 1 -.names Pkey_142_ n13 n437 n438 n71 -0-11 1 --111 1 -.names n71 N_N2922 -0 1 -.names Pkey_150_ n13 n434 n435 n72 -0-11 1 --111 1 -.names n72 N_N2923 -0 1 -.names Pkey_158_ n13 n431 n432 n73 -0-11 1 --111 1 -.names n73 N_N2924 -0 1 -.names Pkey_166_ n13 n428 n429 n74 -0-11 1 --111 1 -.names n74 N_N2925 -0 1 -.names Pkey_174_ n13 n425 n426 n75 -0-11 1 --111 1 -.names n75 N_N2926 -0 1 -.names Pkey_182_ n13 n422 n423 n76 -0-11 1 --111 1 -.names n76 N_N2927 -0 1 -.names Pkey_190_ n13 n419 n420 n77 -0-11 1 --111 1 -.names n77 N_N2928 -0 1 -.names Pkey_67_ n13 n416 n417 n78 -0-11 1 --111 1 -.names n78 N_N2929 -0 1 -.names Pkey_75_ n13 n413 n414 n79 -0-11 1 --111 1 -.names n79 N_N2930 -0 1 -.names Pkey_83_ n13 n410 n411 n80 -0-11 1 --111 1 -.names n80 N_N2932 -0 1 -.names Pkey_91_ n13 n407 n408 n81 -0-11 1 --111 1 -.names n81 N_N2933 -0 1 -.names Pkey_68_ n13 n404 n405 n82 -0-11 1 --111 1 -.names n82 N_N2934 -0 1 -.names Pkey_76_ n13 n401 n402 n83 -0-11 1 --111 1 -.names n83 N_N2935 -0 1 -.names Pkey_84_ n13 n398 n399 n84 -0-11 1 --111 1 -.names n84 N_N2936 -0 1 -.names Pkey_92_ n13 n395 n396 n85 -0-11 1 --111 1 -.names n85 N_N2937 -0 1 -.names Pkey_100_ n13 n392 n393 n86 -0-11 1 --111 1 -.names n86 N_N2938 -0 1 -.names Pkey_44_ n13 n389 n390 n87 -0-11 1 --111 1 -.names n87 N_N2939 -0 1 -.names Pkey_116_ n13 n387 n388 n88 -0-11 1 --111 1 -.names n88 N_N2940 -0 1 -.names Pkey_124_ n13 n384 n385 n89 -0-11 1 --111 1 -.names n89 N_N2941 -0 1 -.names Pkey_69_ n13 n381 n382 n90 -0-11 1 --111 1 -.names n90 N_N2942 -0 1 -.names Pkey_77_ n13 n378 n379 n91 -0-11 1 --111 1 -.names n91 N_N2944 -0 1 -.names Pkey_85_ n13 n375 n376 n92 -0-11 1 --111 1 -.names n92 N_N2946 -0 1 -.names Pkey_93_ n13 n372 n373 n93 -0-11 1 --111 1 -.names n93 N_N2947 -0 1 -.names Pkey_101_ n13 n369 n370 n94 -0-11 1 --111 1 -.names n94 N_N2948 -0 1 -.names Pkey_109_ n13 n366 n367 n95 -0-11 1 --111 1 -.names n95 N_N2949 -0 1 -.names Pkey_117_ n13 n363 n364 n96 -0-11 1 --111 1 -.names n96 N_N2951 -0 1 -.names Pkey_125_ n13 n360 n361 n97 -0-11 1 --111 1 -.names n97 N_N2952 -0 1 -.names Pkey_70_ n13 n357 n358 n98 -0-11 1 --111 1 -.names n98 N_N2953 -0 1 -.names Pkey_78_ n13 n354 n355 n99 -0-11 1 --111 1 -.names n99 N_N2955 -0 1 -.names Pkey_86_ n13 n351 n352 n100 -0-11 1 --111 1 -.names n100 N_N2956 -0 1 -.names Pkey_94_ n13 n348 n349 n101 -0-11 1 --111 1 -.names n101 N_N2957 -0 1 -.names Pkey_102_ n13 n345 n346 n102 -0-11 1 --111 1 -.names n102 N_N2958 -0 1 -.names Pkey_110_ n13 n342 n343 n103 -0-11 1 --111 1 -.names n103 N_N2959 -0 1 -.names Pkey_118_ n13 n339 n340 n104 -0-11 1 --111 1 -.names n104 N_N2960 -0 1 -.names Pkey_126_ n13 n336 n337 n105 -0-11 1 --111 1 -.names n105 N_N2961 -0 1 -.names Pkey_3_ n13 n333 n334 n106 -0-11 1 --111 1 -.names n106 N_N2962 -0 1 -.names Pkey_11_ n13 n330 n331 n107 -0-11 1 --111 1 -.names n107 N_N2963 -0 1 -.names Pkey_19_ n13 n327 n328 n108 -0-11 1 --111 1 -.names n108 N_N2965 -0 1 -.names Pkey_27_ n13 n324 n325 n109 -0-11 1 --111 1 -.names n109 N_N2966 -0 1 -.names Pkey_4_ n13 n321 n322 n110 -0-11 1 --111 1 -.names n110 N_N2967 -0 1 -.names Pkey_12_ n13 n318 n319 n111 -0-11 1 --111 1 -.names n111 N_N2968 -0 1 -.names Pkey_20_ n13 n315 n316 n112 -0-11 1 --111 1 -.names n112 N_N2969 -0 1 -.names Pkey_28_ n13 n312 n313 n113 -0-11 1 --111 1 -.names n113 N_N2970 -0 1 -.names Pkey_36_ n13 n309 n310 n114 -0-11 1 --111 1 -.names n114 N_N2971 -0 1 -.names Pkey_44_ n13 n306 n307 n115 -0-11 1 --111 1 -.names n115 N_N2972 -0 1 -.names Pkey_52_ n13 n303 n304 n116 -0-11 1 --111 1 -.names n116 N_N2973 -0 1 -.names Pkey_60_ n13 n300 n301 n117 -0-11 1 --111 1 -.names n117 N_N2974 -0 1 -.names Pkey_5_ n13 n297 n298 n118 -0-11 1 --111 1 -.names n118 N_N2975 -0 1 -.names Pkey_13_ n13 n294 n295 n119 -0-11 1 --111 1 -.names n119 N_N2977 -0 1 -.names Pkey_21_ n13 n291 n292 n120 -0-11 1 --111 1 -.names n120 N_N2978 -0 1 -.names Pkey_29_ n13 n288 n289 n121 -0-11 1 --111 1 -.names n121 N_N2979 -0 1 -.names Pkey_37_ n13 n285 n286 n122 -0-11 1 --111 1 -.names n122 N_N2980 -0 1 -.names Pkey_45_ n13 n282 n283 n123 -0-11 1 --111 1 -.names n123 N_N2981 -0 1 -.names Pkey_53_ n13 n279 n280 n124 -0-11 1 --111 1 -.names n124 N_N2983 -0 1 -.names Pkey_61_ n13 n276 n277 n125 -0-11 1 --111 1 -.names n125 N_N2984 -0 1 -.names Pkey_6_ n13 n273 n274 n126 -0-11 1 --111 1 -.names n126 N_N2985 -0 1 -.names Pkey_14_ n13 n270 n271 n127 -0-11 1 --111 1 -.names n127 N_N2987 -0 1 -.names Pkey_22_ n13 n267 n268 n128 -0-11 1 --111 1 -.names n128 N_N2988 -0 1 -.names Pkey_30_ n13 n264 n265 n129 -0-11 1 --111 1 -.names n129 N_N2989 -0 1 -.names Pkey_38_ n13 n261 n262 n130 -0-11 1 --111 1 -.names n130 N_N2990 -0 1 -.names Pkey_46_ n13 n258 n259 n131 -0-11 1 --111 1 -.names n131 N_N2991 -0 1 -.names Pkey_54_ n13 n255 n256 n132 -0-11 1 --111 1 -.names n132 N_N2992 -0 1 -.names Pkey_56_ n13 n922 n923 n133 -0-11 1 --111 1 -.names n133 N_N2733 -0 1 -.names Pkey_227_ n13 n919 n920 n134 -0-11 1 --111 1 -.names n134 N_N2734 -0 1 -.names Pkey_235_ n13 n916 n917 n135 -0-11 1 --111 1 -.names n135 N_N2735 -0 1 -.names Pkey_243_ n13 n913 n914 n136 -0-11 1 --111 1 -.names n136 N_N2736 -0 1 -.names Pkey_251_ n13 n910 n911 n137 -0-11 1 --111 1 -.names n137 N_N2738 -0 1 -.names Pkey_194_ n13 n907 n908 n138 -0-11 1 --111 1 -.names n138 N_N2739 -0 1 -.names Pkey_202_ n13 n904 n905 n139 -0-11 1 --111 1 -.names n139 N_N2740 -0 1 -.names Pkey_210_ n13 n901 n902 n140 -0-11 1 --111 1 -.names n140 N_N2742 -0 1 -.names Pkey_218_ n13 n898 n899 n141 -0-11 1 --111 1 -.names n141 N_N2743 -0 1 -.names Pkey_226_ n13 n895 n896 n142 -0-11 1 --111 1 -.names n142 N_N2744 -0 1 -.names Pkey_234_ n13 n892 n893 n143 -0-11 1 --111 1 -.names n143 N_N2745 -0 1 -.names Pkey_242_ n13 n889 n890 n144 -0-11 1 --111 1 -.names n144 N_N2747 -0 1 -.names Pkey_250_ n13 n886 n887 n145 -0-11 1 --111 1 -.names n145 N_N2748 -0 1 -.names Pkey_193_ n13 n883 n884 n146 -0-11 1 --111 1 -.names n146 N_N2750 -0 1 -.names Pkey_201_ n13 n880 n881 n147 -0-11 1 --111 1 -.names n147 N_N2751 -0 1 -.names Pkey_209_ n13 n877 n878 n148 -0-11 1 --111 1 -.names n148 N_N2752 -0 1 -.names Pkey_217_ n13 n874 n875 n149 -0-11 1 --111 1 -.names n149 N_N2753 -0 1 -.names Pkey_225_ n13 n871 n872 n150 -0-11 1 --111 1 -.names n150 N_N2754 -0 1 -.names Pkey_233_ n13 n868 n869 n151 -0-11 1 --111 1 -.names n151 N_N2755 -0 1 -.names Pkey_241_ n13 n865 n866 n152 -0-11 1 --111 1 -.names n152 N_N2756 -0 1 -.names Pkey_249_ n13 n862 n863 n153 -0-11 1 --111 1 -.names n153 N_N2758 -0 1 -.names Pkey_192_ n13 n859 n860 n154 -0-11 1 --111 1 -.names n154 N_N2759 -0 1 -.names Pkey_200_ n13 n856 n857 n155 -0-11 1 --111 1 -.names n155 N_N2760 -0 1 -.names Pkey_208_ n13 n853 n854 n156 -0-11 1 --111 1 -.names n156 N_N2761 -0 1 -.names Pkey_216_ n13 n850 n851 n157 -0-11 1 --111 1 -.names n157 N_N2762 -0 1 -.names Pkey_224_ n13 n847 n848 n158 -0-11 1 --111 1 -.names n158 N_N2763 -0 1 -.names Pkey_232_ n13 n844 n845 n159 -0-11 1 --111 1 -.names n159 N_N2764 -0 1 -.names Pkey_240_ n13 n841 n842 n160 -0-11 1 --111 1 -.names n160 N_N2765 -0 1 -.names Pkey_248_ n13 n838 n839 n161 -0-11 1 --111 1 -.names n161 N_N2766 -0 1 -.names Pkey_163_ n13 n835 n836 n162 -0-11 1 --111 1 -.names n162 N_N2767 -0 1 -.names Pkey_171_ n13 n832 n833 n163 -0-11 1 --111 1 -.names n163 N_N2768 -0 1 -.names Pkey_179_ n13 n829 n830 n164 -0-11 1 --111 1 -.names n164 N_N2769 -0 1 -.names Pkey_187_ n13 n826 n827 n165 -0-11 1 --111 1 -.names n165 N_N2771 -0 1 -.names Pkey_130_ n13 n823 n824 n166 -0-11 1 --111 1 -.names n166 N_N2772 -0 1 -.names Pkey_138_ n13 n820 n821 n167 -0-11 1 --111 1 -.names n167 N_N2773 -0 1 -.names Pkey_146_ n13 n817 n818 n168 -0-11 1 --111 1 -.names n168 N_N2775 -0 1 -.names Pkey_154_ n13 n814 n815 n169 -0-11 1 --111 1 -.names n169 N_N2776 -0 1 -.names Pkey_162_ n13 n811 n812 n170 -0-11 1 --111 1 -.names n170 N_N2777 -0 1 -.names Pkey_170_ n13 n808 n809 n171 -0-11 1 --111 1 -.names n171 N_N2778 -0 1 -.names Pkey_178_ n13 n805 n806 n172 -0-11 1 --111 1 -.names n172 N_N2780 -0 1 -.names Pkey_186_ n13 n802 n803 n173 -0-11 1 --111 1 -.names n173 N_N2781 -0 1 -.names Pkey_129_ n13 n799 n800 n174 -0-11 1 --111 1 -.names n174 N_N2782 -0 1 -.names Pkey_137_ n13 n796 n797 n175 -0-11 1 --111 1 -.names n175 N_N2783 -0 1 -.names Pkey_145_ n13 n793 n794 n176 -0-11 1 --111 1 -.names n176 N_N2784 -0 1 -.names Pkey_153_ n13 n790 n791 n177 -0-11 1 --111 1 -.names n177 N_N2785 -0 1 -.names Pkey_161_ n13 n787 n788 n178 -0-11 1 --111 1 -.names n178 N_N2786 -0 1 -.names Pkey_169_ n13 n784 n785 n179 -0-11 1 --111 1 -.names n179 N_N2787 -0 1 -.names Pkey_177_ n13 n781 n782 n180 -0-11 1 --111 1 -.names n180 N_N2788 -0 1 -.names Pkey_185_ n13 n778 n779 n181 -0-11 1 --111 1 -.names n181 N_N2790 -0 1 -.names Pkey_128_ n13 n775 n776 n182 -0-11 1 --111 1 -.names n182 N_N2791 -0 1 -.names Pkey_136_ n13 n772 n773 n183 -0-11 1 --111 1 -.names n183 N_N2792 -0 1 -.names Pkey_144_ n13 n769 n770 n184 -0-11 1 --111 1 -.names n184 N_N2793 -0 1 -.names Pkey_152_ n13 n766 n767 n185 -0-11 1 --111 1 -.names n185 N_N2794 -0 1 -.names Pkey_160_ n13 n763 n764 n186 -0-11 1 --111 1 -.names n186 N_N2795 -0 1 -.names Pkey_168_ n13 n760 n761 n187 -0-11 1 --111 1 -.names n187 N_N2796 -0 1 -.names Pkey_176_ n13 n757 n758 n188 -0-11 1 --111 1 -.names n188 N_N2797 -0 1 -.names Pkey_184_ n13 n754 n755 n189 -0-11 1 --111 1 -.names n189 N_N2798 -0 1 -.names Pkey_99_ n13 n751 n752 n190 -0-11 1 --111 1 -.names n190 N_N2799 -0 1 -.names Pkey_107_ n13 n748 n749 n191 -0-11 1 --111 1 -.names n191 N_N2800 -0 1 -.names Pkey_115_ n13 n745 n746 n192 -0-11 1 --111 1 -.names n192 N_N2801 -0 1 -.names Pkey_123_ n13 n742 n743 n193 -0-11 1 --111 1 -.names n193 N_N2803 -0 1 -.names Pkey_66_ n13 n739 n740 n194 -0-11 1 --111 1 -.names n194 N_N2804 -0 1 -.names Pkey_74_ n13 n736 n737 n195 -0-11 1 --111 1 -.names n195 N_N2805 -0 1 -.names Pkey_82_ n13 n733 n734 n196 -0-11 1 --111 1 -.names n196 N_N2807 -0 1 -.names Pkey_90_ n13 n730 n731 n197 -0-11 1 --111 1 -.names n197 N_N2808 -0 1 -.names Pkey_98_ n13 n727 n728 n198 -0-11 1 --111 1 -.names n198 N_N2809 -0 1 -.names Pkey_106_ n13 n724 n725 n199 -0-11 1 --111 1 -.names n199 N_N2810 -0 1 -.names Pkey_114_ n13 n721 n722 n200 -0-11 1 --111 1 -.names n200 N_N2812 -0 1 -.names Pkey_122_ n13 n718 n719 n201 -0-11 1 --111 1 -.names n201 N_N2813 -0 1 -.names Pkey_65_ n13 n715 n716 n202 -0-11 1 --111 1 -.names n202 N_N2814 -0 1 -.names Pkey_73_ n13 n712 n713 n203 -0-11 1 --111 1 -.names n203 N_N2815 -0 1 -.names Pkey_81_ n13 n709 n710 n204 -0-11 1 --111 1 -.names n204 N_N2816 -0 1 -.names Pkey_89_ n13 n706 n707 n205 -0-11 1 --111 1 -.names n205 N_N2817 -0 1 -.names Pkey_97_ n13 n703 n704 n206 -0-11 1 --111 1 -.names n206 N_N2818 -0 1 -.names Pkey_105_ n13 n700 n701 n207 -0-11 1 --111 1 -.names n207 N_N2819 -0 1 -.names Pkey_113_ n13 n697 n698 n208 -0-11 1 --111 1 -.names n208 N_N2820 -0 1 -.names Pkey_121_ n13 n694 n695 n209 -0-11 1 --111 1 -.names n209 N_N2822 -0 1 -.names Pkey_64_ n13 n691 n692 n210 -0-11 1 --111 1 -.names n210 N_N2823 -0 1 -.names Pkey_72_ n13 n688 n689 n211 -0-11 1 --111 1 -.names n211 N_N2824 -0 1 -.names Pkey_80_ n13 n685 n686 n212 -0-11 1 --111 1 -.names n212 N_N2825 -0 1 -.names Pkey_88_ n13 n682 n683 n213 -0-11 1 --111 1 -.names n213 N_N2826 -0 1 -.names Pkey_96_ n13 n679 n680 n214 -0-11 1 --111 1 -.names n214 N_N2827 -0 1 -.names Pkey_104_ n13 n676 n677 n215 -0-11 1 --111 1 -.names n215 N_N2828 -0 1 -.names Pkey_112_ n13 n673 n674 n216 -0-11 1 --111 1 -.names n216 N_N2829 -0 1 -.names Pkey_120_ n13 n670 n671 n217 -0-11 1 --111 1 -.names n217 N_N2830 -0 1 -.names Pkey_35_ n13 n667 n668 n218 -0-11 1 --111 1 -.names n218 N_N2831 -0 1 -.names Pkey_43_ n13 n664 n665 n219 -0-11 1 --111 1 -.names n219 N_N2832 -0 1 -.names Pkey_51_ n13 n661 n662 n220 -0-11 1 --111 1 -.names n220 N_N2833 -0 1 -.names Pkey_59_ n13 n658 n659 n221 -0-11 1 --111 1 -.names n221 N_N2835 -0 1 -.names Pkey_2_ n13 n655 n656 n222 -0-11 1 --111 1 -.names n222 N_N2836 -0 1 -.names Pkey_10_ n13 n652 n653 n223 -0-11 1 --111 1 -.names n223 N_N2837 -0 1 -.names Pkey_18_ n13 n649 n650 n224 -0-11 1 --111 1 -.names n224 N_N2839 -0 1 -.names Pkey_26_ n13 n646 n647 n225 -0-11 1 --111 1 -.names n225 N_N2840 -0 1 -.names Pkey_34_ n13 n643 n644 n226 -0-11 1 --111 1 -.names n226 N_N2841 -0 1 -.names Pkey_42_ n13 n640 n641 n227 -0-11 1 --111 1 -.names n227 N_N2842 -0 1 -.names Pkey_50_ n13 n637 n638 n228 -0-11 1 --111 1 -.names n228 N_N2844 -0 1 -.names Pkey_58_ n13 n634 n635 n229 -0-11 1 --111 1 -.names n229 N_N2845 -0 1 -.names Pkey_1_ n13 n631 n632 n230 -0-11 1 --111 1 -.names n230 N_N2846 -0 1 -.names Pkey_9_ n13 n628 n629 n231 -0-11 1 --111 1 -.names n231 N_N2847 -0 1 -.names Pkey_17_ n13 n625 n626 n232 -0-11 1 --111 1 -.names n232 N_N2848 -0 1 -.names Pkey_25_ n13 n622 n623 n233 -0-11 1 --111 1 -.names n233 N_N2849 -0 1 -.names Pkey_33_ n13 n619 n620 n234 -0-11 1 --111 1 -.names n234 N_N2850 -0 1 -.names Pkey_41_ n13 n616 n617 n235 -0-11 1 --111 1 -.names n235 N_N2851 -0 1 -.names Pkey_49_ n13 n613 n614 n236 -0-11 1 --111 1 -.names n236 N_N2852 -0 1 -.names Pkey_57_ n13 n610 n611 n237 -0-11 1 --111 1 -.names n237 N_N2854 -0 1 -.names Pkey_0_ n13 n607 n608 n238 -0-11 1 --111 1 -.names n238 N_N2855 -0 1 -.names Pkey_8_ n13 n604 n605 n239 -0-11 1 --111 1 -.names n239 N_N2856 -0 1 -.names Pkey_16_ n13 n601 n602 n240 -0-11 1 --111 1 -.names n240 N_N2857 -0 1 -.names Pkey_24_ n13 n598 n599 n241 -0-11 1 --111 1 -.names n241 N_N2858 -0 1 -.names Pkey_32_ n13 n595 n596 n242 -0-11 1 --111 1 -.names n242 N_N2859 -0 1 -.names Pkey_40_ n13 n592 n593 n243 -0-11 1 --111 1 -.names n243 N_N2860 -0 1 -.names Pkey_48_ n13 n589 n590 n244 -0-11 1 --111 1 -.names n244 N_N2861 -0 1 -.names Pcount_1_ Pcount_2_ Pcount_3_ n248 -1-- 1 --1- 1 ---1 1 -.names Pcount_1_ Pcount_2_ Pcount_0_ n249 -1-- 1 --1- 1 ---1 1 -.names Pcount_2_ Pcount_1_ Pcount_0_ n246 -0-- 1 --0- 1 ---0 1 -.names Pcount_3_ n248 n249 n246 n245 -011- 1 --111 1 -.names Pcount_3_ Pcount_2_ Pcount_1_ Pcount_0_ n251 -0--- 1 --0-- 1 ---0- 1 ----1 1 -.names Pcount_3_ n246 n252 -1- 1 --1 1 -.names n251 n252 Pcount_3_ n249 n250 -111- 1 -11-1 1 -.names PKSi_118_ PKSi_4_ n1166 n1290 n255 -0--1 1 --0-1 1 ---11 1 -.names Pkey_62_ n15 n1291 n256 -0-1 1 --11 1 -.names PKSi_102_ PKSi_23_ n1166 n1292 n258 -0--1 1 --0-1 1 ---11 1 -.names Pkey_54_ n15 n1293 n259 -0-1 1 --11 1 -.names PKSi_98_ PKSi_6_ n1166 n1294 n261 -0--1 1 --0-1 1 ---11 1 -.names Pkey_46_ n15 n1295 n262 -0-1 1 --11 1 -.names PKSi_119_ PKSi_15_ n1166 n1296 n264 -0--1 1 --0-1 1 ---11 1 -.names Pkey_38_ n15 n1297 n265 -0-1 1 --11 1 -.names PKSi_106_ PKSi_5_ n1166 n1298 n267 -0--1 1 --0-1 1 ---11 1 -.names Pkey_30_ n15 n1299 n268 -0-1 1 --11 1 -.names PKSi_112_ PKSi_9_ n1166 n1300 n270 -0--1 1 --0-1 1 ---11 1 -.names Pkey_22_ n15 n1301 n271 -0-1 1 --11 1 -.names PKSi_19_ N_N2986 n1166 n1302 n273 -0--1 1 --0-1 1 ---11 1 -.names Pkey_14_ n15 n1303 n274 -0-1 1 --11 1 -.names PKSi_117_ PKSi_17_ n1166 n1304 n276 -0--1 1 --0-1 1 ---11 1 -.names Pkey_6_ n15 n1305 n277 -0-1 1 --11 1 -.names PKSi_99_ n1166 N_N2853 n1306 n279 -0--1 1 --1-1 1 ---01 1 -.names Pkey_61_ n15 n1307 n280 -0-1 1 --11 1 -.names PKSi_11_ N_N2982 n1166 n1308 n282 -0--1 1 --0-1 1 ---11 1 -.names Pkey_53_ n15 n1309 n283 -0-1 1 --11 1 -.names PKSi_110_ PKSi_2_ n1166 n1310 n285 -0--1 1 --0-1 1 ---11 1 -.names Pkey_45_ n15 n1311 n286 -0-1 1 --11 1 -.names PKSi_103_ PKSi_14_ n1166 n1312 n288 -0--1 1 --0-1 1 ---11 1 -.names Pkey_37_ n15 n1313 n289 -0-1 1 --11 1 -.names PKSi_96_ PKSi_22_ n1166 n1314 n291 -0--1 1 --0-1 1 ---11 1 -.names Pkey_29_ n15 n1315 n292 -0-1 1 --11 1 -.names PKSi_115_ PKSi_0_ n1166 n1316 n294 -0--1 1 --0-1 1 ---11 1 -.names Pkey_21_ n15 n1317 n295 -0-1 1 --11 1 -.names PKSi_8_ N_N2976 n1166 n1318 n297 -0--1 1 --0-1 1 ---11 1 -.names Pkey_13_ n15 n1319 n298 -0-1 1 --11 1 -.names PKSi_108_ PKSi_18_ n1166 n1320 n300 -0--1 1 --0-1 1 ---11 1 -.names Pkey_5_ n15 n1321 n301 -0-1 1 --11 1 -.names PKSi_105_ PKSi_1_ n1166 n1322 n303 -0--1 1 --0-1 1 ---11 1 -.names Pkey_60_ n15 n1323 n304 -0-1 1 --11 1 -.names PKSi_114_ n1166 N_N2843 n1324 n306 -0--1 1 --1-1 1 ---01 1 -.names Pkey_52_ n15 n1325 n307 -0-1 1 --11 1 -.names PKSi_100_ PKSi_13_ n1166 n1326 n309 -0--1 1 --0-1 1 ---11 1 -.names Pkey_44_ n15 n1327 n310 -0-1 1 --11 1 -.names PKSi_107_ PKSi_21_ n1166 n1328 n312 -0--1 1 --0-1 1 ---11 1 -.names Pkey_36_ n15 n1329 n313 -0-1 1 --11 1 -.names PKSi_109_ PKSi_10_ n1166 n1330 n315 -0--1 1 --0-1 1 ---11 1 -.names Pkey_28_ n15 n1331 n316 -0-1 1 --11 1 -.names PKSi_116_ n1166 N_N2838 n1332 n318 -0--1 1 --1-1 1 ---01 1 -.names Pkey_20_ n15 n1333 n319 -0-1 1 --11 1 -.names PKSi_104_ PKSi_12_ n1166 n1334 n321 -0--1 1 --0-1 1 ---11 1 -.names Pkey_12_ n15 n1335 n322 -0-1 1 --11 1 -.names PKSi_97_ PKSi_3_ n1166 n1336 n324 -0--1 1 --0-1 1 ---11 1 -.names Pkey_4_ n15 n1337 n325 -0-1 1 --11 1 -.names PKSi_113_ n1166 N_N2834 n1338 n327 -0--1 1 --1-1 1 ---01 1 -.names Pkey_27_ n15 n1339 n328 -0-1 1 --11 1 -.names PKSi_16_ N_N2964 n1166 n1340 n330 -0--1 1 --0-1 1 ---11 1 -.names Pkey_19_ n15 n1341 n331 -0-1 1 --11 1 -.names PKSi_101_ PKSi_20_ n1166 n1342 n333 -0--1 1 --0-1 1 ---11 1 -.names Pkey_11_ n15 n1343 n334 -0-1 1 --11 1 -.names PKSi_111_ PKSi_7_ n1166 n1344 n336 -0--1 1 --0-1 1 ---11 1 -.names Pkey_3_ n15 n1345 n337 -0-1 1 --11 1 -.names PKSi_142_ PKSi_28_ n1166 n1346 n339 -0--1 1 --0-1 1 ---11 1 -.names Pkey_126_ n15 n1347 n340 -0-1 1 --11 1 -.names PKSi_126_ PKSi_47_ n1166 n1348 n342 -0--1 1 --0-1 1 ---11 1 -.names Pkey_118_ n15 n1349 n343 -0-1 1 --11 1 -.names PKSi_122_ PKSi_30_ n1166 n1350 n345 -0--1 1 --0-1 1 ---11 1 -.names Pkey_110_ n15 n1351 n346 -0-1 1 --11 1 -.names [282] PKSi_39_ n1166 n1352 n348 -0--1 1 --0-1 1 ---11 1 -.names Pkey_102_ n15 n1353 n349 -0-1 1 --11 1 -.names PKSi_130_ PKSi_29_ n1166 n1354 n351 -0--1 1 --0-1 1 ---11 1 -.names Pkey_94_ n15 n1355 n352 -0-1 1 --11 1 -.names PKSi_136_ PKSi_33_ n1166 n1356 n354 -0--1 1 --0-1 1 ---11 1 -.names Pkey_86_ n15 n1357 n355 -0-1 1 --11 1 -.names PKSi_43_ N_N2954 n1166 n1358 n357 -0--1 1 --0-1 1 ---11 1 -.names Pkey_78_ n15 n1359 n358 -0-1 1 --11 1 -.names PKSi_141_ PKSi_41_ n1166 n1360 n360 -0--1 1 --0-1 1 ---11 1 -.names Pkey_70_ n15 n1361 n361 -0-1 1 --11 1 -.names PKSi_123_ n1166 N_N2821 n1362 n363 -0--1 1 --1-1 1 ---01 1 -.names Pkey_125_ n15 n1363 n364 -0-1 1 --11 1 -.names PKSi_35_ N_N2950 n1166 n1364 n366 -0--1 1 --0-1 1 ---11 1 -.names Pkey_117_ n15 n1365 n367 -0-1 1 --11 1 -.names PKSi_134_ PKSi_26_ n1166 n1366 n369 -0--1 1 --0-1 1 ---11 1 -.names Pkey_109_ n15 n1367 n370 -0-1 1 --11 1 -.names PKSi_127_ PKSi_38_ n1166 n1368 n372 -0--1 1 --0-1 1 ---11 1 -.names Pkey_101_ n15 n1369 n373 -0-1 1 --11 1 -.names PKSi_120_ PKSi_46_ n1166 n1370 n375 -0--1 1 --0-1 1 ---11 1 -.names Pkey_93_ n15 n1371 n376 -0-1 1 --11 1 -.names PKSi_24_ N_N2945 n1166 n1372 n378 -0--1 1 --0-1 1 ---11 1 -.names Pkey_85_ n15 n1373 n379 -0-1 1 --11 1 -.names PKSi_32_ N_N2943 n1166 n1374 n381 -0--1 1 --0-1 1 ---11 1 -.names Pkey_77_ n15 n1375 n382 -0-1 1 --11 1 -.names PKSi_132_ PKSi_42_ n1166 n1376 n384 -0--1 1 --0-1 1 ---11 1 -.names Pkey_69_ n15 n1377 n385 -0-1 1 --11 1 -.names PKSi_129_ PKSi_25_ n1166 n1378 n387 -0--1 1 --0-1 1 ---11 1 -.names Pkey_124_ n15 n1379 n388 -0-1 1 --11 1 -.names PKSi_138_ n1166 N_N2811 n1380 n389 -0--1 1 --1-1 1 ---01 1 -.names Pkey_116_ n15 n1381 n390 -0-1 1 --11 1 -.names PKSi_124_ PKSi_37_ n1166 n1382 n392 -0--1 1 --0-1 1 ---11 1 -.names Pkey_44_ n15 n1383 n393 -0-1 1 --11 1 -.names PKSi_131_ PKSi_45_ n1166 n1384 n395 -0--1 1 --0-1 1 ---11 1 -.names Pkey_100_ n15 n1385 n396 -0-1 1 --11 1 -.names PKSi_133_ PKSi_34_ n1166 n1386 n398 -0--1 1 --0-1 1 ---11 1 -.names Pkey_92_ n15 n1387 n399 -0-1 1 --11 1 -.names PKSi_140_ n1166 N_N2806 n1388 n401 -0--1 1 --1-1 1 ---01 1 -.names Pkey_84_ n15 n1389 n402 -0-1 1 --11 1 -.names PKSi_128_ PKSi_36_ n1166 n1390 n404 -0--1 1 --0-1 1 ---11 1 -.names Pkey_76_ n15 n1391 n405 -0-1 1 --11 1 -.names PKSi_121_ PKSi_27_ n1166 n1392 n407 -0--1 1 --0-1 1 ---11 1 -.names Pkey_68_ n15 n1393 n408 -0-1 1 --11 1 -.names PKSi_137_ n1166 N_N2802 n1394 n410 -0--1 1 --1-1 1 ---01 1 -.names Pkey_91_ n15 n1395 n411 -0-1 1 --11 1 -.names PKSi_40_ N_N2931 n1166 n1396 n413 -0--1 1 --0-1 1 ---11 1 -.names Pkey_83_ n15 n1397 n414 -0-1 1 --11 1 -.names PKSi_125_ PKSi_44_ n1166 n1398 n416 -0--1 1 --0-1 1 ---11 1 -.names Pkey_75_ n15 n1399 n417 -0-1 1 --11 1 -.names PKSi_135_ PKSi_31_ n1166 n1400 n419 -0--1 1 --0-1 1 ---11 1 -.names Pkey_67_ n15 n1401 n420 -0-1 1 --11 1 -.names PKSi_166_ PKSi_52_ n1166 n1402 n422 -0--1 1 --0-1 1 ---11 1 -.names Pkey_190_ n15 n1403 n423 -0-1 1 --11 1 -.names PKSi_150_ PKSi_71_ n1166 n1404 n425 -0--1 1 --0-1 1 ---11 1 -.names Pkey_182_ n15 n1405 n426 -0-1 1 --11 1 -.names PKSi_146_ PKSi_54_ n1166 n1406 n428 -0--1 1 --0-1 1 ---11 1 -.names Pkey_174_ n15 n1407 n429 -0-1 1 --11 1 -.names PKSi_167_ PKSi_63_ n1166 n1408 n431 -0--1 1 --0-1 1 ---11 1 -.names Pkey_166_ n15 n1409 n432 -0-1 1 --11 1 -.names PKSi_154_ PKSi_53_ n1166 n1410 n434 -0--1 1 --0-1 1 ---11 1 -.names Pkey_158_ n15 n1411 n435 -0-1 1 --11 1 -.names PKSi_160_ PKSi_57_ n1166 n1412 n437 -0--1 1 --0-1 1 ---11 1 -.names Pkey_150_ n15 n1413 n438 -0-1 1 --11 1 -.names PKSi_67_ N_N2921 n1166 n1414 n440 -0--1 1 --0-1 1 ---11 1 -.names Pkey_142_ n15 n1415 n441 -0-1 1 --11 1 -.names PKSi_165_ PKSi_65_ n1166 n1416 n443 -0--1 1 --0-1 1 ---11 1 -.names Pkey_134_ n15 n1417 n444 -0-1 1 --11 1 -.names PKSi_147_ n1166 N_N2789 n1418 n446 -0--1 1 --1-1 1 ---01 1 -.names Pkey_189_ n15 n1419 n447 -0-1 1 --11 1 -.names PKSi_59_ N_N2917 n1166 n1420 n449 -0--1 1 --0-1 1 ---11 1 -.names Pkey_181_ n15 n1421 n450 -0-1 1 --11 1 -.names PKSi_158_ PKSi_50_ n1166 n1422 n452 -0--1 1 --0-1 1 ---11 1 -.names Pkey_173_ n15 n1423 n453 -0-1 1 --11 1 -.names PKSi_151_ PKSi_62_ n1166 n1424 n455 -0--1 1 --0-1 1 ---11 1 -.names Pkey_165_ n15 n1425 n456 -0-1 1 --11 1 -.names PKSi_144_ PKSi_70_ n1166 n1426 n458 -0--1 1 --0-1 1 ---11 1 -.names Pkey_157_ n15 n1427 n459 -0-1 1 --11 1 -.names PKSi_163_ PKSi_48_ n1166 n1428 n461 -0--1 1 --0-1 1 ---11 1 -.names Pkey_149_ n15 n1429 n462 -0-1 1 --11 1 -.names PKSi_153_ PKSi_56_ n1166 n1430 n464 -0--1 1 --0-1 1 ---11 1 -.names Pkey_141_ n15 n1431 n465 -0-1 1 --11 1 -.names PKSi_156_ PKSi_66_ n1166 n1432 n467 -0--1 1 --0-1 1 ---11 1 -.names Pkey_133_ n15 n1433 n468 -0-1 1 --11 1 -.names PKSi_49_ N_N2909 n1166 n1434 n470 -0--1 1 --0-1 1 ---11 1 -.names Pkey_188_ n15 n1435 n471 -0-1 1 --11 1 -.names PKSi_162_ n1166 N_N2779 n1436 n473 -0--1 1 --1-1 1 ---01 1 -.names Pkey_180_ n15 n1437 n474 -0-1 1 --11 1 -.names PKSi_148_ PKSi_61_ n1166 n1438 n476 -0--1 1 --0-1 1 ---11 1 -.names Pkey_172_ n15 n1439 n477 -0-1 1 --11 1 -.names PKSi_155_ PKSi_69_ n1166 n1440 n479 -0--1 1 --0-1 1 ---11 1 -.names Pkey_164_ n15 n1441 n480 -0-1 1 --11 1 -.names PKSi_157_ PKSi_58_ n1166 n1442 n482 -0--1 1 --0-1 1 ---11 1 -.names Pkey_156_ n15 n1443 n483 -0-1 1 --11 1 -.names PKSi_164_ n1166 N_N2774 n1444 n485 -0--1 1 --1-1 1 ---01 1 -.names Pkey_148_ n15 n1445 n486 -0-1 1 --11 1 -.names PKSi_152_ PKSi_60_ n1166 n1446 n488 -0--1 1 --0-1 1 ---11 1 -.names Pkey_140_ n15 n1447 n489 -0-1 1 --11 1 -.names PKSi_145_ PKSi_51_ n1166 n1448 n491 -0--1 1 --0-1 1 ---11 1 -.names Pkey_132_ n15 n1449 n492 -0-1 1 --11 1 -.names PKSi_161_ n1166 N_N2770 n1450 n494 -0--1 1 --1-1 1 ---01 1 -.names Pkey_155_ n15 n1451 n495 -0-1 1 --11 1 -.names PKSi_64_ N_N2899 n1166 n1452 n497 -0--1 1 --0-1 1 ---11 1 -.names Pkey_147_ n15 n1453 n498 -0-1 1 --11 1 -.names PKSi_149_ PKSi_68_ n1166 n1454 n500 -0--1 1 --0-1 1 ---11 1 -.names Pkey_139_ n15 n1455 n501 -0-1 1 --11 1 -.names PKSi_159_ PKSi_55_ n1166 n1456 n503 -0--1 1 --0-1 1 ---11 1 -.names Pkey_131_ n15 n1457 n504 -0-1 1 --11 1 -.names PKSi_190_ PKSi_76_ n1166 n1458 n506 -0--1 1 --0-1 1 ---11 1 -.names Pkey_254_ n15 n1459 n507 -0-1 1 --11 1 -.names PKSi_174_ PKSi_95_ n1166 n1460 n509 -0--1 1 --0-1 1 ---11 1 -.names Pkey_246_ n15 n1461 n510 -0-1 1 --11 1 -.names PKSi_170_ PKSi_78_ n1166 n1462 n512 -0--1 1 --0-1 1 ---11 1 -.names Pkey_238_ n15 n1463 n513 -0-1 1 --11 1 -.names [234] PKSi_87_ n1166 n1464 n515 -0--1 1 --0-1 1 ---11 1 -.names Pkey_230_ n15 n1465 n516 -0-1 1 --11 1 -.names PKSi_178_ PKSi_77_ n1166 n1466 n518 -0--1 1 --0-1 1 ---11 1 -.names Pkey_222_ n15 n1467 n519 -0-1 1 --11 1 -.names PKSi_184_ PKSi_81_ n1166 n1468 n521 -0--1 1 --0-1 1 ---11 1 -.names Pkey_214_ n15 n1469 n522 -0-1 1 --11 1 -.names PKSi_91_ N_N2889 n1166 n1470 n524 -0--1 1 --0-1 1 ---11 1 -.names Pkey_206_ n15 n1471 n525 -0-1 1 --11 1 -.names PKSi_189_ PKSi_89_ n1166 n1472 n527 -0--1 1 --0-1 1 ---11 1 -.names Pkey_198_ n15 n1473 n528 -0-1 1 --11 1 -.names PKSi_171_ n1166 N_N2757 n1474 n530 -0--1 1 --1-1 1 ---01 1 -.names Pkey_253_ n15 n1475 n531 -0-1 1 --11 1 -.names PKSi_83_ N_N2885 n1166 n1476 n533 -0--1 1 --0-1 1 ---11 1 -.names Pkey_245_ n15 n1477 n534 -0-1 1 --11 1 -.names PKSi_182_ PKSi_74_ n1166 n1478 n536 -0--1 1 --0-1 1 ---11 1 -.names Pkey_237_ n15 n1479 n537 -0-1 1 --11 1 -.names PKSi_175_ PKSi_86_ n1166 n1480 n539 -0--1 1 --0-1 1 ---11 1 -.names Pkey_229_ n15 n1481 n540 -0-1 1 --11 1 -.names PKSi_94_ N_N2881 n1166 n1482 n542 -0--1 1 --0-1 1 ---11 1 -.names Pkey_221_ n15 n1483 n543 -0-1 1 --11 1 -.names PKSi_72_ N_N2879 n1166 n1484 n545 -0--1 1 --0-1 1 ---11 1 -.names Pkey_213_ n15 n1485 n546 -0-1 1 --11 1 -.names PKSi_80_ N_N2877 n1166 n1486 n548 -0--1 1 --0-1 1 ---11 1 -.names Pkey_205_ n15 n1487 n549 -0-1 1 --11 1 -.names PKSi_180_ n1166 N_N2749 n1488 n551 -0--1 1 --1-1 1 ---01 1 -.names Pkey_197_ n15 n1489 n552 -0-1 1 --11 1 -.names PKSi_177_ PKSi_73_ n1166 n1490 n554 -0--1 1 --0-1 1 ---11 1 -.names Pkey_252_ n15 n1491 n555 -0-1 1 --11 1 -.names PKSi_186_ n1166 N_N2746 n1492 n556 -0--1 1 --1-1 1 ---01 1 -.names Pkey_244_ n15 n1493 n557 -0-1 1 --11 1 -.names PKSi_172_ PKSi_85_ n1166 n1494 n559 -0--1 1 --0-1 1 ---11 1 -.names Pkey_172_ n15 n1495 n560 -0-1 1 --11 1 -.names PKSi_179_ PKSi_93_ n1166 n1496 n562 -0--1 1 --0-1 1 ---11 1 -.names Pkey_228_ n15 n1497 n563 -0-1 1 --11 1 -.names [253] PKSi_82_ n1166 n1498 n565 -0--1 1 --0-1 1 ---11 1 -.names Pkey_220_ n15 n1499 n566 -0-1 1 --11 1 -.names PKSi_188_ n1166 N_N2741 n1500 n568 -0--1 1 --1-1 1 ---01 1 -.names Pkey_212_ n15 n1501 n569 -0-1 1 --11 1 -.names PKSi_176_ PKSi_84_ n1166 n1502 n571 -0--1 1 --0-1 1 ---11 1 -.names Pkey_204_ n15 n1503 n572 -0-1 1 --11 1 -.names PKSi_169_ PKSi_75_ n1166 n1504 n574 -0--1 1 --0-1 1 ---11 1 -.names Pkey_196_ n15 n1505 n575 -0-1 1 --11 1 -.names PKSi_185_ n1166 N_N2737 n1506 n577 -0--1 1 --1-1 1 ---01 1 -.names Pkey_219_ n15 n1507 n578 -0-1 1 --11 1 -.names [333] N_N2865 n1166 n1508 n580 -0--1 1 --0-1 1 ---11 1 -.names Pkey_211_ n15 n1509 n581 -0-1 1 --11 1 -.names PKSi_173_ PKSi_92_ n1166 n1510 n583 -0--1 1 --0-1 1 ---11 1 -.names Pkey_203_ n15 n1511 n584 -0-1 1 --11 1 -.names PKSi_183_ PKSi_79_ n1166 n1512 n586 -0--1 1 --0-1 1 ---11 1 -.names Pkey_195_ n15 n1513 n587 -0-1 1 --11 1 -.names n940 n1284 n1286 n1514 n589 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_56_ n15 n1516 n590 -0-1 1 --11 1 -.names n942 n1284 n1286 n1517 n592 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_48_ n15 n1518 n593 -0-1 1 --11 1 -.names n944 n1284 n1286 n1519 n595 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_40_ n15 n1520 n596 -0-1 1 --11 1 -.names n946 n1284 n1286 n1521 n598 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_32_ n15 n1522 n599 -0-1 1 --11 1 -.names n948 n1284 n1286 n1523 n601 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_24_ n15 n1524 n602 -0-1 1 --11 1 -.names n950 n1284 n1286 n1525 n604 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_16_ n15 n1526 n605 -0-1 1 --11 1 -.names n952 n1284 n1286 n1527 n607 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_8_ n15 n1528 n608 -0-1 1 --11 1 -.names n954 n1284 n1286 n1529 n610 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_0_ n15 n1530 n611 -0-1 1 --11 1 -.names n956 n1284 n1286 n1531 n613 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_57_ n15 n1532 n614 -0-1 1 --11 1 -.names n958 n1284 n1286 n1533 n616 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_49_ n15 n1534 n617 -0-1 1 --11 1 -.names n960 n1284 n1286 n1535 n619 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_41_ n15 n1536 n620 -0-1 1 --11 1 -.names n962 n1284 n1286 n1537 n622 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_33_ n15 n1538 n623 -0-1 1 --11 1 -.names n964 n1284 n1286 n1539 n625 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_25_ n15 n1540 n626 -0-1 1 --11 1 -.names n966 n1284 n1286 n1541 n628 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_17_ n15 n1542 n629 -0-1 1 --11 1 -.names n968 n1284 n1286 n1543 n631 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_9_ n15 n1544 n632 -0-1 1 --11 1 -.names n970 n1284 n1286 n1545 n634 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_1_ n15 n1546 n635 -0-1 1 --11 1 -.names n972 n1284 n1286 n1547 n637 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_58_ n15 n1548 n638 -0-1 1 --11 1 -.names n974 n1284 n1286 n1549 n640 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_50_ n15 n1550 n641 -0-1 1 --11 1 -.names n976 n1284 n1286 n1551 n643 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_42_ n15 n1552 n644 -0-1 1 --11 1 -.names n978 n1284 n1286 n1553 n646 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_34_ n15 n1554 n647 -0-1 1 --11 1 -.names n980 n1284 n1286 n1555 n649 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_26_ n15 n1556 n650 -0-1 1 --11 1 -.names n982 n1284 n1286 n1557 n652 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_18_ n15 n1558 n653 -0-1 1 --11 1 -.names n984 n1284 n1286 n1559 n655 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_10_ n15 n1560 n656 -0-1 1 --11 1 -.names n986 n1284 n1286 n1561 n658 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_2_ n15 n1562 n659 -0-1 1 --11 1 -.names n988 n1284 n1286 n1563 n661 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_59_ n15 n1564 n662 -0-1 1 --11 1 -.names n990 n1284 n1286 n1565 n664 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_51_ n15 n1566 n665 -0-1 1 --11 1 -.names n992 n1284 n1286 n1567 n667 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_43_ n15 n1568 n668 -0-1 1 --11 1 -.names n994 n1284 n1286 n1569 n670 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_35_ n15 n1570 n671 -0-1 1 --11 1 -.names n996 n1284 n1286 n1571 n673 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_120_ n15 n1572 n674 -0-1 1 --11 1 -.names n998 n1284 n1286 n1573 n676 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_112_ n15 n1574 n677 -0-1 1 --11 1 -.names n1000 n1284 n1286 n1575 n679 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_104_ n15 n1576 n680 -0-1 1 --11 1 -.names n1002 n1284 n1286 n1577 n682 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_96_ n15 n1578 n683 -0-1 1 --11 1 -.names n1004 n1284 n1286 n1579 n685 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_88_ n15 n1580 n686 -0-1 1 --11 1 -.names n1006 n1284 n1286 n1581 n688 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_80_ n15 n1582 n689 -0-1 1 --11 1 -.names n1008 n1284 n1286 n1583 n691 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_72_ n15 n1584 n692 -0-1 1 --11 1 -.names n1010 n1284 n1286 n1585 n694 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_64_ n15 n1586 n695 -0-1 1 --11 1 -.names n1012 n1284 n1286 n1587 n697 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_121_ n15 n1588 n698 -0-1 1 --11 1 -.names n1014 n1284 n1286 n1589 n700 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_113_ n15 n1590 n701 -0-1 1 --11 1 -.names n1016 n1284 n1286 n1591 n703 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_105_ n15 n1592 n704 -0-1 1 --11 1 -.names n1018 n1284 n1286 n1593 n706 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_97_ n15 n1594 n707 -0-1 1 --11 1 -.names n1020 n1284 n1286 n1595 n709 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_89_ n15 n1596 n710 -0-1 1 --11 1 -.names n1022 n1284 n1286 n1597 n712 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_81_ n15 n1598 n713 -0-1 1 --11 1 -.names n1024 n1284 n1286 n1599 n715 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_73_ n15 n1600 n716 -0-1 1 --11 1 -.names n1026 n1284 n1286 n1601 n718 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_65_ n15 n1602 n719 -0-1 1 --11 1 -.names n1028 n1284 n1286 n1603 n721 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_122_ n15 n1604 n722 -0-1 1 --11 1 -.names n1030 n1284 n1286 n1605 n724 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_114_ n15 n1606 n725 -0-1 1 --11 1 -.names n1032 n1284 n1286 n1607 n727 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_106_ n15 n1608 n728 -0-1 1 --11 1 -.names n1034 n1284 n1286 n1609 n730 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_98_ n15 n1610 n731 -0-1 1 --11 1 -.names n1036 n1284 n1286 n1611 n733 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_90_ n15 n1612 n734 -0-1 1 --11 1 -.names n1038 n1284 n1286 n1613 n736 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_82_ n15 n1614 n737 -0-1 1 --11 1 -.names n1040 n1284 n1286 n1615 n739 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_74_ n15 n1616 n740 -0-1 1 --11 1 -.names n1042 n1284 n1286 n1617 n742 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_66_ n15 n1618 n743 -0-1 1 --11 1 -.names n1044 n1284 n1286 n1619 n745 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_123_ n15 n1620 n746 -0-1 1 --11 1 -.names n1046 n1284 n1286 n1621 n748 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_115_ n15 n1622 n749 -0-1 1 --11 1 -.names n1048 n1284 n1286 n1623 n751 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_107_ n15 n1624 n752 -0-1 1 --11 1 -.names n1050 n1284 n1286 n1625 n754 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_99_ n15 n1626 n755 -0-1 1 --11 1 -.names n1052 n1284 n1286 n1627 n757 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_184_ n15 n1628 n758 -0-1 1 --11 1 -.names n1054 n1284 n1286 n1629 n760 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_176_ n15 n1630 n761 -0-1 1 --11 1 -.names n1056 n1284 n1286 n1631 n763 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_168_ n15 n1632 n764 -0-1 1 --11 1 -.names n1058 n1284 n1286 n1633 n766 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_160_ n15 n1634 n767 -0-1 1 --11 1 -.names n1060 n1284 n1286 n1635 n769 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_152_ n15 n1636 n770 -0-1 1 --11 1 -.names n1062 n1284 n1286 n1637 n772 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_144_ n15 n1638 n773 -0-1 1 --11 1 -.names n1064 n1284 n1286 n1639 n775 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_136_ n15 n1640 n776 -0-1 1 --11 1 -.names n1066 n1284 n1286 n1641 n778 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_128_ n15 n1642 n779 -0-1 1 --11 1 -.names n1068 n1284 n1286 n1643 n781 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_185_ n15 n1644 n782 -0-1 1 --11 1 -.names n1070 n1284 n1286 n1645 n784 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_177_ n15 n1646 n785 -0-1 1 --11 1 -.names n1072 n1284 n1286 n1647 n787 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_169_ n15 n1648 n788 -0-1 1 --11 1 -.names n1074 n1284 n1286 n1649 n790 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_161_ n15 n1650 n791 -0-1 1 --11 1 -.names n1076 n1284 n1286 n1651 n793 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_153_ n15 n1652 n794 -0-1 1 --11 1 -.names n1078 n1284 n1286 n1653 n796 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_145_ n15 n1654 n797 -0-1 1 --11 1 -.names n1080 n1284 n1286 n1655 n799 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_137_ n15 n1656 n800 -0-1 1 --11 1 -.names n1082 n1284 n1286 n1657 n802 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_129_ n15 n1658 n803 -0-1 1 --11 1 -.names n1084 n1284 n1286 n1659 n805 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_186_ n15 n1660 n806 -0-1 1 --11 1 -.names n1086 n1284 n1286 n1661 n808 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_178_ n15 n1662 n809 -0-1 1 --11 1 -.names n1088 n1284 n1286 n1663 n811 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_170_ n15 n1664 n812 -0-1 1 --11 1 -.names n1090 n1284 n1286 n1665 n814 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_162_ n15 n1666 n815 -0-1 1 --11 1 -.names n1092 n1284 n1286 n1667 n817 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_154_ n15 n1668 n818 -0-1 1 --11 1 -.names n1094 n1284 n1286 n1669 n820 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_146_ n15 n1670 n821 -0-1 1 --11 1 -.names n1096 n1284 n1286 n1671 n823 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_138_ n15 n1672 n824 -0-1 1 --11 1 -.names n1098 n1284 n1286 n1673 n826 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_130_ n15 n1674 n827 -0-1 1 --11 1 -.names n1100 n1284 n1286 n1675 n829 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_187_ n15 n1676 n830 -0-1 1 --11 1 -.names n1102 n1284 n1286 n1677 n832 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_179_ n15 n1678 n833 -0-1 1 --11 1 -.names n1104 n1284 n1286 n1679 n835 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_171_ n15 n1680 n836 -0-1 1 --11 1 -.names n1106 n1284 n1286 n1681 n838 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_163_ n15 n1682 n839 -0-1 1 --11 1 -.names n1108 n1284 n1286 n1683 n841 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_248_ n15 n1684 n842 -0-1 1 --11 1 -.names n1110 n1284 n1286 n1685 n844 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_240_ n15 n1686 n845 -0-1 1 --11 1 -.names n1112 n1284 n1286 n1687 n847 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_232_ n15 n1688 n848 -0-1 1 --11 1 -.names n1114 n1284 n1286 n1689 n850 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_224_ n15 n1690 n851 -0-1 1 --11 1 -.names n1116 n1284 n1286 n1691 n853 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_216_ n15 n1692 n854 -0-1 1 --11 1 -.names n1118 n1284 n1286 n1693 n856 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_208_ n15 n1694 n857 -0-1 1 --11 1 -.names n1120 n1284 n1286 n1695 n859 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_200_ n15 n1696 n860 -0-1 1 --11 1 -.names n1122 n1284 n1286 n1697 n862 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_192_ n15 n1698 n863 -0-1 1 --11 1 -.names n1124 n1284 n1286 n1699 n865 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_249_ n15 n1700 n866 -0-1 1 --11 1 -.names n1126 n1284 n1286 n1701 n868 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_241_ n15 n1702 n869 -0-1 1 --11 1 -.names n1128 n1284 n1286 n1703 n871 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_233_ n15 n1704 n872 -0-1 1 --11 1 -.names n1130 n1284 n1286 n1705 n874 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_225_ n15 n1706 n875 -0-1 1 --11 1 -.names n1132 n1284 n1286 n1707 n877 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_217_ n15 n1708 n878 -0-1 1 --11 1 -.names n1134 n1284 n1286 n1709 n880 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_209_ n15 n1710 n881 -0-1 1 --11 1 -.names n1136 n1284 n1286 n1711 n883 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_201_ n15 n1712 n884 -0-1 1 --11 1 -.names n1138 n1284 n1286 n1713 n886 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_193_ n15 n1714 n887 -0-1 1 --11 1 -.names n1140 n1284 n1286 n1715 n889 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_250_ n15 n1716 n890 -0-1 1 --11 1 -.names n1142 n1284 n1286 n1717 n892 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_242_ n15 n1718 n893 -0-1 1 --11 1 -.names n1144 n1284 n1286 n1719 n895 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_234_ n15 n1720 n896 -0-1 1 --11 1 -.names n1146 n1284 n1286 n1721 n898 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_226_ n15 n1722 n899 -0-1 1 --11 1 -.names n1148 n1284 n1286 n1723 n901 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_218_ n15 n1724 n902 -0-1 1 --11 1 -.names n1150 n1284 n1286 n1725 n904 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_210_ n15 n1726 n905 -0-1 1 --11 1 -.names n1152 n1284 n1286 n1727 n907 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_202_ n15 n1728 n908 -0-1 1 --11 1 -.names n1154 n1284 n1286 n1729 n910 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_194_ n15 n1730 n911 -0-1 1 --11 1 -.names n1156 n1284 n1286 n1731 n913 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_251_ n15 n1732 n914 -0-1 1 --11 1 -.names n1158 n1284 n1286 n1733 n916 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_243_ n15 n1734 n917 -0-1 1 --11 1 -.names n1160 n1284 n1286 n1735 n919 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_235_ n15 n1736 n920 -0-1 1 --11 1 -.names n1162 n1284 n1286 n1737 n922 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names Pkey_227_ n15 n1738 n923 -0-1 1 --11 1 -.names Pcount_3_ n246 n1287 n925 -0-- 1 --1- 1 ---1 1 -.names Pcount_3_ Pencrypt_0_ n249 n924 -1-- 1 --1- 1 ---1 1 -.names Pcount_1_ n1966 n1967 n929 -01- 1 -1-1 1 --11 1 -.names Pencrypt_0_ Pcount_1_ n928 -1- 1 --0 1 -.names Pcount_2_ n928 n1967 n930 -10- 1 -1-0 1 -.names Pstart_0_ Pcount_0_ n15 n1289 n934 -1-1- 1 --01- 1 ---10 1 -.names Pcount_2_ Pcount_0_ n935 -00 1 -.names Pencrypt_0_ n252 n924 n939 -0-1 1 --11 1 -.names Pencrypt_0_ n246 n935 n938 -10- 1 -0-1 1 --01 1 -.names Pcount_3_ n928 n939 n938 n937 -0-1- 1 --111 1 -.names PKSi_118_ PKSi_4_ n940 -11 1 -00 1 -.names PKSi_102_ PKSi_23_ n942 -11 1 -00 1 -.names PKSi_98_ PKSi_6_ n944 -11 1 -00 1 -.names PKSi_119_ PKSi_15_ n946 -11 1 -00 1 -.names PKSi_106_ PKSi_5_ n948 -11 1 -00 1 -.names PKSi_112_ PKSi_9_ n950 -11 1 -00 1 -.names PKSi_19_ N_N2986 n952 -11 1 -00 1 -.names PKSi_117_ PKSi_17_ n954 -11 1 -00 1 -.names PKSi_99_ N_N2853 n956 -11 1 -00 1 -.names PKSi_11_ N_N2982 n958 -11 1 -00 1 -.names PKSi_110_ PKSi_2_ n960 -11 1 -00 1 -.names PKSi_103_ PKSi_14_ n962 -11 1 -00 1 -.names PKSi_96_ PKSi_22_ n964 -11 1 -00 1 -.names PKSi_115_ PKSi_0_ n966 -11 1 -00 1 -.names PKSi_8_ N_N2976 n968 -11 1 -00 1 -.names PKSi_108_ PKSi_18_ n970 -11 1 -00 1 -.names PKSi_105_ PKSi_1_ n972 -11 1 -00 1 -.names PKSi_114_ N_N2843 n974 -11 1 -00 1 -.names PKSi_100_ PKSi_13_ n976 -11 1 -00 1 -.names PKSi_107_ PKSi_21_ n978 -11 1 -00 1 -.names PKSi_109_ PKSi_10_ n980 -11 1 -00 1 -.names PKSi_116_ N_N2838 n982 -11 1 -00 1 -.names PKSi_104_ PKSi_12_ n984 -11 1 -00 1 -.names PKSi_97_ PKSi_3_ n986 -11 1 -00 1 -.names PKSi_113_ N_N2834 n988 -11 1 -00 1 -.names PKSi_16_ N_N2964 n990 -11 1 -00 1 -.names PKSi_101_ PKSi_20_ n992 -11 1 -00 1 -.names PKSi_111_ PKSi_7_ n994 -11 1 -00 1 -.names PKSi_142_ PKSi_28_ n996 -11 1 -00 1 -.names PKSi_126_ PKSi_47_ n998 -11 1 -00 1 -.names PKSi_122_ PKSi_30_ n1000 -11 1 -00 1 -.names [282] PKSi_39_ n1002 -11 1 -00 1 -.names PKSi_130_ PKSi_29_ n1004 -11 1 -00 1 -.names PKSi_136_ PKSi_33_ n1006 -11 1 -00 1 -.names PKSi_43_ N_N2954 n1008 -11 1 -00 1 -.names PKSi_141_ PKSi_41_ n1010 -11 1 -00 1 -.names PKSi_123_ N_N2821 n1012 -11 1 -00 1 -.names PKSi_35_ N_N2950 n1014 -11 1 -00 1 -.names PKSi_134_ PKSi_26_ n1016 -11 1 -00 1 -.names PKSi_127_ PKSi_38_ n1018 -11 1 -00 1 -.names PKSi_120_ PKSi_46_ n1020 -11 1 -00 1 -.names PKSi_24_ N_N2945 n1022 -11 1 -00 1 -.names PKSi_32_ N_N2943 n1024 -11 1 -00 1 -.names PKSi_132_ PKSi_42_ n1026 -11 1 -00 1 -.names PKSi_129_ PKSi_25_ n1028 -11 1 -00 1 -.names PKSi_138_ N_N2811 n1030 -11 1 -00 1 -.names PKSi_124_ PKSi_37_ n1032 -11 1 -00 1 -.names PKSi_131_ PKSi_45_ n1034 -11 1 -00 1 -.names PKSi_133_ PKSi_34_ n1036 -11 1 -00 1 -.names PKSi_140_ N_N2806 n1038 -11 1 -00 1 -.names PKSi_128_ PKSi_36_ n1040 -11 1 -00 1 -.names PKSi_121_ PKSi_27_ n1042 -11 1 -00 1 -.names PKSi_137_ N_N2802 n1044 -11 1 -00 1 -.names PKSi_40_ N_N2931 n1046 -11 1 -00 1 -.names PKSi_125_ PKSi_44_ n1048 -11 1 -00 1 -.names PKSi_135_ PKSi_31_ n1050 -11 1 -00 1 -.names PKSi_166_ PKSi_52_ n1052 -11 1 -00 1 -.names PKSi_150_ PKSi_71_ n1054 -11 1 -00 1 -.names PKSi_146_ PKSi_54_ n1056 -11 1 -00 1 -.names PKSi_167_ PKSi_63_ n1058 -11 1 -00 1 -.names PKSi_154_ PKSi_53_ n1060 -11 1 -00 1 -.names PKSi_160_ PKSi_57_ n1062 -11 1 -00 1 -.names PKSi_67_ N_N2921 n1064 -11 1 -00 1 -.names PKSi_165_ PKSi_65_ n1066 -11 1 -00 1 -.names PKSi_147_ N_N2789 n1068 -11 1 -00 1 -.names PKSi_59_ N_N2917 n1070 -11 1 -00 1 -.names PKSi_158_ PKSi_50_ n1072 -11 1 -00 1 -.names PKSi_151_ PKSi_62_ n1074 -11 1 -00 1 -.names PKSi_144_ PKSi_70_ n1076 -11 1 -00 1 -.names PKSi_163_ PKSi_48_ n1078 -11 1 -00 1 -.names PKSi_153_ PKSi_56_ n1080 -11 1 -00 1 -.names PKSi_156_ PKSi_66_ n1082 -11 1 -00 1 -.names PKSi_49_ N_N2909 n1084 -11 1 -00 1 -.names PKSi_162_ N_N2779 n1086 -11 1 -00 1 -.names PKSi_148_ PKSi_61_ n1088 -11 1 -00 1 -.names PKSi_155_ PKSi_69_ n1090 -11 1 -00 1 -.names PKSi_157_ PKSi_58_ n1092 -11 1 -00 1 -.names PKSi_164_ N_N2774 n1094 -11 1 -00 1 -.names PKSi_152_ PKSi_60_ n1096 -11 1 -00 1 -.names PKSi_145_ PKSi_51_ n1098 -11 1 -00 1 -.names PKSi_161_ N_N2770 n1100 -11 1 -00 1 -.names PKSi_64_ N_N2899 n1102 -11 1 -00 1 -.names PKSi_149_ PKSi_68_ n1104 -11 1 -00 1 -.names PKSi_159_ PKSi_55_ n1106 -11 1 -00 1 -.names PKSi_190_ PKSi_76_ n1108 -11 1 -00 1 -.names PKSi_174_ PKSi_95_ n1110 -11 1 -00 1 -.names PKSi_170_ PKSi_78_ n1112 -11 1 -00 1 -.names [234] PKSi_87_ n1114 -11 1 -00 1 -.names PKSi_178_ PKSi_77_ n1116 -11 1 -00 1 -.names PKSi_184_ PKSi_81_ n1118 -11 1 -00 1 -.names PKSi_91_ N_N2889 n1120 -11 1 -00 1 -.names PKSi_189_ PKSi_89_ n1122 -11 1 -00 1 -.names PKSi_171_ N_N2757 n1124 -11 1 -00 1 -.names PKSi_83_ N_N2885 n1126 -11 1 -00 1 -.names PKSi_182_ PKSi_74_ n1128 -11 1 -00 1 -.names PKSi_175_ PKSi_86_ n1130 -11 1 -00 1 -.names PKSi_94_ N_N2881 n1132 -11 1 -00 1 -.names PKSi_72_ N_N2879 n1134 -11 1 -00 1 -.names PKSi_80_ N_N2877 n1136 -11 1 -00 1 -.names PKSi_180_ N_N2749 n1138 -11 1 -00 1 -.names PKSi_177_ PKSi_73_ n1140 -11 1 -00 1 -.names PKSi_186_ N_N2746 n1142 -11 1 -00 1 -.names PKSi_172_ PKSi_85_ n1144 -11 1 -00 1 -.names PKSi_179_ PKSi_93_ n1146 -11 1 -00 1 -.names [253] PKSi_82_ n1148 -11 1 -00 1 -.names PKSi_188_ N_N2741 n1150 -11 1 -00 1 -.names PKSi_176_ PKSi_84_ n1152 -11 1 -00 1 -.names PKSi_169_ PKSi_75_ n1154 -11 1 -00 1 -.names PKSi_185_ N_N2737 n1156 -11 1 -00 1 -.names [333] N_N2865 n1158 -11 1 -00 1 -.names PKSi_173_ PKSi_92_ n1160 -11 1 -00 1 -.names PKSi_183_ PKSi_79_ n1162 -11 1 -00 1 -.names Pencrypt_0_ n250 n1167 -10 1 -.names Pstart_0_ n1167 n1166 -1- 1 --1 1 -.names Pstart_0_ n1167 n1170 -1- 1 --0 1 -.names Pencrypt_0_ n250 n1285 -0- 1 --0 1 -.names Pstart_0_ n1285 n1284 -01 1 -.names Pstart_0_ n1285 n1286 -1- 1 --1 1 -.names Pstart_0_ Pencrypt_0_ n1287 -1- 1 --0 1 -.names Pencrypt_0_ Pcount_2_ Pcount_1_ n1968 n1289 ---01 1 -10-1 1 -.names n940 n1170 n1290 -1- 1 --1 1 -.names n11 n1741 n1740 n1291 -10- 1 -1-1 1 --00 1 -.names n942 n1170 n1292 -1- 1 --1 1 -.names n11 n1741 n1744 n1293 -10- 1 -1-1 1 --00 1 -.names n944 n1170 n1294 -1- 1 --1 1 -.names n11 n1741 n1746 n1295 -10- 1 -1-1 1 --00 1 -.names n946 n1170 n1296 -1- 1 --1 1 -.names n11 n1741 n1748 n1297 -10- 1 -1-1 1 --00 1 -.names n948 n1170 n1298 -1- 1 --1 1 -.names n11 n1741 n1750 n1299 -10- 1 -1-1 1 --00 1 -.names n950 n1170 n1300 -1- 1 --1 1 -.names n11 n1741 n1752 n1301 -10- 1 -1-1 1 --00 1 -.names n952 n1170 n1302 -1- 1 --1 1 -.names n11 n1741 n1754 n1303 -10- 1 -1-1 1 --00 1 -.names n954 n1170 n1304 -1- 1 --1 1 -.names n11 n1741 n1756 n1305 -10- 1 -1-1 1 --00 1 -.names n956 n1170 n1306 -1- 1 --1 1 -.names n11 n1741 n1758 n1307 -10- 1 -1-1 1 --00 1 -.names n958 n1170 n1308 -1- 1 --1 1 -.names n11 n1741 n1760 n1309 -10- 1 -1-1 1 --00 1 -.names n960 n1170 n1310 -1- 1 --1 1 -.names n11 n1741 n1762 n1311 -10- 1 -1-1 1 --00 1 -.names n962 n1170 n1312 -1- 1 --1 1 -.names n11 n1741 n1764 n1313 -10- 1 -1-1 1 --00 1 -.names n964 n1170 n1314 -1- 1 --1 1 -.names n11 n1741 n1766 n1315 -10- 1 -1-1 1 --00 1 -.names n966 n1170 n1316 -1- 1 --1 1 -.names n11 n1741 n1768 n1317 -10- 1 -1-1 1 --00 1 -.names n968 n1170 n1318 -1- 1 --1 1 -.names n11 n1741 n1770 n1319 -10- 1 -1-1 1 --00 1 -.names n970 n1170 n1320 -1- 1 --1 1 -.names n11 n1741 n1772 n1321 -10- 1 -1-1 1 --00 1 -.names n972 n1170 n1322 -1- 1 --1 1 -.names n11 n1741 n1774 n1323 -10- 1 -1-1 1 --00 1 -.names n974 n1170 n1324 -1- 1 --1 1 -.names n11 n1741 n1776 n1325 -10- 1 -1-1 1 --00 1 -.names n976 n1170 n1326 -1- 1 --1 1 -.names n11 n1741 n1778 n1327 -10- 1 -1-1 1 --00 1 -.names n978 n1170 n1328 -1- 1 --1 1 -.names n11 n1741 n1780 n1329 -10- 1 -1-1 1 --00 1 -.names n980 n1170 n1330 -1- 1 --1 1 -.names n11 n1741 n1782 n1331 -10- 1 -1-1 1 --00 1 -.names n982 n1170 n1332 -1- 1 --1 1 -.names n11 n1741 n1784 n1333 -10- 1 -1-1 1 --00 1 -.names n984 n1170 n1334 -1- 1 --1 1 -.names n11 n1741 n1786 n1335 -10- 1 -1-1 1 --00 1 -.names n986 n1170 n1336 -1- 1 --1 1 -.names n11 n1741 n1788 n1337 -10- 1 -1-1 1 --00 1 -.names n988 n1170 n1338 -1- 1 --1 1 -.names n11 n1741 n1790 n1339 -10- 1 -1-1 1 --00 1 -.names n990 n1170 n1340 -1- 1 --1 1 -.names n11 n1741 n1792 n1341 -10- 1 -1-1 1 --00 1 -.names n992 n1170 n1342 -1- 1 --1 1 -.names n11 n1741 n1794 n1343 -10- 1 -1-1 1 --00 1 -.names n994 n1170 n1344 -1- 1 --1 1 -.names n11 n1741 n1796 n1345 -10- 1 -1-1 1 --00 1 -.names n996 n1170 n1346 -1- 1 --1 1 -.names n11 n1741 n1798 n1347 -10- 1 -1-1 1 --00 1 -.names n998 n1170 n1348 -1- 1 --1 1 -.names n11 n1741 n1800 n1349 -10- 1 -1-1 1 --00 1 -.names n1000 n1170 n1350 -1- 1 --1 1 -.names n11 n1741 n1802 n1351 -10- 1 -1-1 1 --00 1 -.names n1002 n1170 n1352 -1- 1 --1 1 -.names n11 n1741 n1804 n1353 -10- 1 -1-1 1 --00 1 -.names n1004 n1170 n1354 -1- 1 --1 1 -.names n11 n1741 n1806 n1355 -10- 1 -1-1 1 --00 1 -.names n1006 n1170 n1356 -1- 1 --1 1 -.names n11 n1741 n1808 n1357 -10- 1 -1-1 1 --00 1 -.names n1008 n1170 n1358 -1- 1 --1 1 -.names n11 n1741 n1810 n1359 -10- 1 -1-1 1 --00 1 -.names n1010 n1170 n1360 -1- 1 --1 1 -.names n11 n1741 n1812 n1361 -10- 1 -1-1 1 --00 1 -.names n1012 n1170 n1362 -1- 1 --1 1 -.names n11 n1741 n1814 n1363 -10- 1 -1-1 1 --00 1 -.names n1014 n1170 n1364 -1- 1 --1 1 -.names n11 n1741 n1816 n1365 -10- 1 -1-1 1 --00 1 -.names n1016 n1170 n1366 -1- 1 --1 1 -.names n11 n1741 n1818 n1367 -10- 1 -1-1 1 --00 1 -.names n1018 n1170 n1368 -1- 1 --1 1 -.names n11 n1741 n1820 n1369 -10- 1 -1-1 1 --00 1 -.names n1020 n1170 n1370 -1- 1 --1 1 -.names n11 n1741 n1822 n1371 -10- 1 -1-1 1 --00 1 -.names n1022 n1170 n1372 -1- 1 --1 1 -.names n11 n1741 n1824 n1373 -10- 1 -1-1 1 --00 1 -.names n1024 n1170 n1374 -1- 1 --1 1 -.names n11 n1741 n1826 n1375 -10- 1 -1-1 1 --00 1 -.names n1026 n1170 n1376 -1- 1 --1 1 -.names n11 n1741 n1828 n1377 -10- 1 -1-1 1 --00 1 -.names n1028 n1170 n1378 -1- 1 --1 1 -.names n11 n1741 n1830 n1379 -10- 1 -1-1 1 --00 1 -.names n1030 n1170 n1380 -1- 1 --1 1 -.names n11 n1741 n1832 n1381 -10- 1 -1-1 1 --00 1 -.names n1032 n1170 n1382 -1- 1 --1 1 -.names n11 n1741 n1834 n1383 -10- 1 -1-1 1 --00 1 -.names n1034 n1170 n1384 -1- 1 --1 1 -.names n11 n1741 n1836 n1385 -10- 1 -1-1 1 --00 1 -.names n1036 n1170 n1386 -1- 1 --1 1 -.names n11 n1741 n1838 n1387 -10- 1 -1-1 1 --00 1 -.names n1038 n1170 n1388 -1- 1 --1 1 -.names n11 n1741 n1840 n1389 -10- 1 -1-1 1 --00 1 -.names n1040 n1170 n1390 -1- 1 --1 1 -.names n11 n1741 n1842 n1391 -10- 1 -1-1 1 --00 1 -.names n1042 n1170 n1392 -1- 1 --1 1 -.names n11 n1741 n1844 n1393 -10- 1 -1-1 1 --00 1 -.names n1044 n1170 n1394 -1- 1 --1 1 -.names n11 n1741 n1846 n1395 -10- 1 -1-1 1 --00 1 -.names n1046 n1170 n1396 -1- 1 --1 1 -.names n11 n1741 n1848 n1397 -10- 1 -1-1 1 --00 1 -.names n1048 n1170 n1398 -1- 1 --1 1 -.names n11 n1741 n1850 n1399 -10- 1 -1-1 1 --00 1 -.names n1050 n1170 n1400 -1- 1 --1 1 -.names n11 n1741 n1852 n1401 -10- 1 -1-1 1 --00 1 -.names n1052 n1170 n1402 -1- 1 --1 1 -.names n11 n1741 n1854 n1403 -10- 1 -1-1 1 --00 1 -.names n1054 n1170 n1404 -1- 1 --1 1 -.names n11 n1741 n1856 n1405 -10- 1 -1-1 1 --00 1 -.names n1056 n1170 n1406 -1- 1 --1 1 -.names n11 n1741 n1858 n1407 -10- 1 -1-1 1 --00 1 -.names n1058 n1170 n1408 -1- 1 --1 1 -.names n11 n1741 n1860 n1409 -10- 1 -1-1 1 --00 1 -.names n1060 n1170 n1410 -1- 1 --1 1 -.names n11 n1741 n1862 n1411 -10- 1 -1-1 1 --00 1 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n1930 n1479 -10- 1 -1-1 1 --00 1 -.names n1130 n1170 n1480 -1- 1 --1 1 -.names n11 n1741 n1932 n1481 -10- 1 -1-1 1 --00 1 -.names n1132 n1170 n1482 -1- 1 --1 1 -.names n11 n1741 n1934 n1483 -10- 1 -1-1 1 --00 1 -.names n1134 n1170 n1484 -1- 1 --1 1 -.names n11 n1741 n1936 n1485 -10- 1 -1-1 1 --00 1 -.names n1136 n1170 n1486 -1- 1 --1 1 -.names n11 n1741 n1938 n1487 -10- 1 -1-1 1 --00 1 -.names n1138 n1170 n1488 -1- 1 --1 1 -.names n11 n1741 n1940 n1489 -10- 1 -1-1 1 --00 1 -.names n1140 n1170 n1490 -1- 1 --1 1 -.names n11 n1741 n1942 n1491 -10- 1 -1-1 1 --00 1 -.names n1142 n1170 n1492 -1- 1 --1 1 -.names n11 n1741 n1944 n1493 -10- 1 -1-1 1 --00 1 -.names n1144 n1170 n1494 -1- 1 --1 1 -.names n11 n1741 n1946 n1495 -10- 1 -1-1 1 --00 1 -.names n1146 n1170 n1496 -1- 1 --1 1 -.names n11 n1741 n1948 n1497 -10- 1 -1-1 1 --00 1 -.names n1148 n1170 n1498 -1- 1 --1 1 -.names n11 n1741 n1950 n1499 -10- 1 -1-1 1 --00 1 -.names n1150 n1170 n1500 -1- 1 --1 1 -.names n11 n1741 n1952 n1501 -10- 1 -1-1 1 --00 1 -.names n1152 n1170 n1502 -1- 1 --1 1 -.names n11 n1741 n1954 n1503 -10- 1 -1-1 1 --00 1 -.names n1154 n1170 n1504 -1- 1 --1 1 -.names n11 n1741 n1956 n1505 -10- 1 -1-1 1 --00 1 -.names n1156 n1170 n1506 -1- 1 --1 1 -.names n11 n1741 n1958 n1507 -10- 1 -1-1 1 --00 1 -.names n1158 n1170 n1508 -1- 1 --1 1 -.names n11 n1741 n1960 n1509 -10- 1 -1-1 1 --00 1 -.names n1160 n1170 n1510 -1- 1 --1 1 -.names n11 n1741 n1962 n1511 -10- 1 -1-1 1 --00 1 -.names n1162 n1170 n1512 -1- 1 --1 1 -.names n11 n1741 n1964 n1513 -10- 1 -1-1 1 --00 1 -.names PKSi_118_ PKSi_4_ n1514 -0- 1 --0 1 -.names n11 n1741 n1740 n1516 -10- 1 --01 1 -1-0 1 -.names PKSi_102_ PKSi_23_ n1517 -0- 1 --0 1 -.names n11 n1741 n1744 n1518 -10- 1 --01 1 -1-0 1 -.names PKSi_98_ PKSi_6_ n1519 -0- 1 --0 1 -.names n11 n1741 n1746 n1520 -10- 1 --01 1 -1-0 1 -.names PKSi_119_ PKSi_15_ n1521 -0- 1 --0 1 -.names n11 n1741 n1748 n1522 -10- 1 --01 1 -1-0 1 -.names PKSi_106_ PKSi_5_ n1523 -0- 1 --0 1 -.names n11 n1741 n1750 n1524 -10- 1 --01 1 -1-0 1 -.names PKSi_112_ PKSi_9_ n1525 -0- 1 --0 1 -.names n11 n1741 n1752 n1526 -10- 1 --01 1 -1-0 1 -.names PKSi_19_ N_N2986 n1527 -0- 1 --0 1 -.names n11 n1741 n1754 n1528 -10- 1 --01 1 -1-0 1 -.names PKSi_117_ PKSi_17_ n1529 -0- 1 --0 1 -.names n11 n1741 n1756 n1530 -10- 1 --01 1 -1-0 1 -.names PKSi_99_ N_N2853 n1531 -0- 1 --0 1 -.names n11 n1741 n1758 n1532 -10- 1 --01 1 -1-0 1 -.names PKSi_11_ N_N2982 n1533 -0- 1 --0 1 -.names n11 n1741 n1760 n1534 -10- 1 --01 1 -1-0 1 -.names PKSi_110_ PKSi_2_ n1535 -0- 1 --0 1 -.names n11 n1741 n1762 n1536 -10- 1 --01 1 -1-0 1 -.names PKSi_103_ PKSi_14_ n1537 -0- 1 --0 1 -.names n11 n1741 n1764 n1538 -10- 1 --01 1 -1-0 1 -.names PKSi_96_ PKSi_22_ n1539 -0- 1 --0 1 -.names n11 n1741 n1766 n1540 -10- 1 --01 1 -1-0 1 -.names PKSi_115_ PKSi_0_ n1541 -0- 1 --0 1 -.names n11 n1741 n1768 n1542 -10- 1 --01 1 -1-0 1 -.names PKSi_8_ N_N2976 n1543 -0- 1 --0 1 -.names n11 n1741 n1770 n1544 -10- 1 --01 1 -1-0 1 -.names PKSi_108_ PKSi_18_ n1545 -0- 1 --0 1 -.names n11 n1741 n1772 n1546 -10- 1 --01 1 -1-0 1 -.names PKSi_105_ PKSi_1_ n1547 -0- 1 --0 1 -.names n11 n1741 n1774 n1548 -10- 1 --01 1 -1-0 1 -.names PKSi_114_ N_N2843 n1549 -0- 1 --0 1 -.names n11 n1741 n1776 n1550 -10- 1 --01 1 -1-0 1 -.names PKSi_100_ PKSi_13_ n1551 -0- 1 --0 1 -.names n11 n1741 n1778 n1552 -10- 1 --01 1 -1-0 1 -.names PKSi_107_ PKSi_21_ n1553 -0- 1 --0 1 -.names n11 n1741 n1780 n1554 -10- 1 --01 1 -1-0 1 -.names PKSi_109_ PKSi_10_ n1555 -0- 1 --0 1 -.names n11 n1741 n1782 n1556 -10- 1 --01 1 -1-0 1 -.names PKSi_116_ N_N2838 n1557 -0- 1 --0 1 -.names n11 n1741 n1784 n1558 -10- 1 --01 1 -1-0 1 -.names PKSi_104_ PKSi_12_ n1559 -0- 1 --0 1 -.names n11 n1741 n1786 n1560 -10- 1 --01 1 -1-0 1 -.names PKSi_97_ PKSi_3_ n1561 -0- 1 --0 1 -.names n11 n1741 n1788 n1562 -10- 1 --01 1 -1-0 1 -.names PKSi_113_ N_N2834 n1563 -0- 1 --0 1 -.names n11 n1741 n1790 n1564 -10- 1 --01 1 -1-0 1 -.names PKSi_16_ N_N2964 n1565 -0- 1 --0 1 -.names n11 n1741 n1792 n1566 -10- 1 --01 1 -1-0 1 -.names PKSi_101_ PKSi_20_ n1567 -0- 1 --0 1 -.names n11 n1741 n1794 n1568 -10- 1 --01 1 -1-0 1 -.names PKSi_111_ PKSi_7_ n1569 -0- 1 --0 1 -.names n11 n1741 n1796 n1570 -10- 1 --01 1 -1-0 1 -.names PKSi_142_ PKSi_28_ n1571 -0- 1 --0 1 -.names n11 n1741 n1798 n1572 -10- 1 --01 1 -1-0 1 -.names PKSi_126_ PKSi_47_ n1573 -0- 1 --0 1 -.names n11 n1741 n1800 n1574 -10- 1 --01 1 -1-0 1 -.names PKSi_122_ PKSi_30_ n1575 -0- 1 --0 1 -.names n11 n1741 n1802 n1576 -10- 1 --01 1 -1-0 1 -.names [282] PKSi_39_ n1577 -0- 1 --0 1 -.names n11 n1741 n1804 n1578 -10- 1 --01 1 -1-0 1 -.names PKSi_130_ PKSi_29_ n1579 -0- 1 --0 1 -.names n11 n1741 n1806 n1580 -10- 1 --01 1 -1-0 1 -.names PKSi_136_ PKSi_33_ n1581 -0- 1 --0 1 -.names n11 n1741 n1808 n1582 -10- 1 --01 1 -1-0 1 -.names PKSi_43_ N_N2954 n1583 -0- 1 --0 1 -.names n11 n1741 n1810 n1584 -10- 1 --01 1 -1-0 1 -.names PKSi_141_ PKSi_41_ n1585 -0- 1 --0 1 -.names n11 n1741 n1812 n1586 -10- 1 --01 1 -1-0 1 -.names PKSi_123_ N_N2821 n1587 -0- 1 --0 1 -.names n11 n1741 n1814 n1588 -10- 1 --01 1 -1-0 1 -.names PKSi_35_ N_N2950 n1589 -0- 1 --0 1 -.names n11 n1741 n1816 n1590 -10- 1 --01 1 -1-0 1 -.names PKSi_134_ PKSi_26_ n1591 -0- 1 --0 1 -.names n11 n1741 n1818 n1592 -10- 1 --01 1 -1-0 1 -.names PKSi_127_ PKSi_38_ n1593 -0- 1 --0 1 -.names n11 n1741 n1820 n1594 -10- 1 --01 1 -1-0 1 -.names PKSi_120_ PKSi_46_ n1595 -0- 1 --0 1 -.names n11 n1741 n1822 n1596 -10- 1 --01 1 -1-0 1 -.names PKSi_24_ N_N2945 n1597 -0- 1 --0 1 -.names n11 n1741 n1824 n1598 -10- 1 --01 1 -1-0 1 -.names PKSi_32_ N_N2943 n1599 -0- 1 --0 1 -.names n11 n1741 n1826 n1600 -10- 1 --01 1 -1-0 1 -.names PKSi_132_ PKSi_42_ n1601 -0- 1 --0 1 -.names n11 n1741 n1828 n1602 -10- 1 --01 1 -1-0 1 -.names PKSi_129_ PKSi_25_ n1603 -0- 1 --0 1 -.names n11 n1741 n1830 n1604 -10- 1 --01 1 -1-0 1 -.names PKSi_138_ N_N2811 n1605 -0- 1 --0 1 -.names n11 n1741 n1832 n1606 -10- 1 --01 1 -1-0 1 -.names PKSi_124_ PKSi_37_ n1607 -0- 1 --0 1 -.names n11 n1741 n1834 n1608 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PKSi_71_ n1629 -0- 1 --0 1 -.names n11 n1741 n1856 n1630 -10- 1 --01 1 -1-0 1 -.names PKSi_146_ PKSi_54_ n1631 -0- 1 --0 1 -.names n11 n1741 n1858 n1632 -10- 1 --01 1 -1-0 1 -.names PKSi_167_ PKSi_63_ n1633 -0- 1 --0 1 -.names n11 n1741 n1860 n1634 -10- 1 --01 1 -1-0 1 -.names PKSi_154_ PKSi_53_ n1635 -0- 1 --0 1 -.names n11 n1741 n1862 n1636 -10- 1 --01 1 -1-0 1 -.names PKSi_160_ PKSi_57_ n1637 -0- 1 --0 1 -.names n11 n1741 n1864 n1638 -10- 1 --01 1 -1-0 1 -.names PKSi_67_ N_N2921 n1639 -0- 1 --0 1 -.names n11 n1741 n1866 n1640 -10- 1 --01 1 -1-0 1 -.names PKSi_165_ PKSi_65_ n1641 -0- 1 --0 1 -.names n11 n1741 n1868 n1642 -10- 1 --01 1 -1-0 1 -.names PKSi_147_ N_N2789 n1643 -0- 1 --0 1 -.names n11 n1741 n1870 n1644 -10- 1 --01 1 -1-0 1 -.names PKSi_59_ N_N2917 n1645 -0- 1 --0 1 -.names n11 n1741 n1872 n1646 -10- 1 --01 1 -1-0 1 -.names PKSi_158_ PKSi_50_ n1647 -0- 1 --0 1 -.names n11 n1741 n1874 n1648 -10- 1 --01 1 -1-0 1 -.names PKSi_151_ PKSi_62_ n1649 -0- 1 --0 1 -.names n11 n1741 n1876 n1650 -10- 1 --01 1 -1-0 1 -.names PKSi_144_ PKSi_70_ n1651 -0- 1 --0 1 -.names n11 n1741 n1878 n1652 -10- 1 --01 1 -1-0 1 -.names PKSi_163_ PKSi_48_ n1653 -0- 1 --0 1 -.names n11 n1741 n1880 n1654 -10- 1 --01 1 -1-0 1 -.names PKSi_153_ PKSi_56_ n1655 -0- 1 --0 1 -.names n11 n1741 n1882 n1656 -10- 1 --01 1 -1-0 1 -.names PKSi_156_ PKSi_66_ n1657 -0- 1 --0 1 -.names n11 n1741 n1884 n1658 -10- 1 --01 1 -1-0 1 -.names PKSi_49_ N_N2909 n1659 -0- 1 --0 1 -.names n11 n1741 n1886 n1660 -10- 1 --01 1 -1-0 1 -.names PKSi_162_ N_N2779 n1661 -0- 1 --0 1 -.names n11 n1741 n1888 n1662 -10- 1 --01 1 -1-0 1 -.names PKSi_148_ PKSi_61_ n1663 -0- 1 --0 1 -.names n11 n1741 n1890 n1664 -10- 1 --01 1 -1-0 1 -.names PKSi_155_ PKSi_69_ n1665 -0- 1 --0 1 -.names n11 n1741 n1892 n1666 -10- 1 --01 1 -1-0 1 -.names PKSi_157_ PKSi_58_ n1667 -0- 1 --0 1 -.names n11 n1741 n1894 n1668 -10- 1 --01 1 -1-0 1 -.names PKSi_164_ N_N2774 n1669 -0- 1 --0 1 -.names n11 n1741 n1896 n1670 -10- 1 --01 1 -1-0 1 -.names PKSi_152_ PKSi_60_ n1671 -0- 1 --0 1 -.names n11 n1741 n1898 n1672 -10- 1 --01 1 -1-0 1 -.names PKSi_145_ PKSi_51_ n1673 -0- 1 --0 1 -.names n11 n1741 n1900 n1674 -10- 1 --01 1 -1-0 1 -.names PKSi_161_ N_N2770 n1675 -0- 1 --0 1 -.names n11 n1741 n1902 n1676 -10- 1 --01 1 -1-0 1 -.names PKSi_64_ N_N2899 n1677 -0- 1 --0 1 -.names n11 n1741 n1904 n1678 -10- 1 --01 1 -1-0 1 -.names PKSi_149_ PKSi_68_ n1679 -0- 1 --0 1 -.names n11 n1741 n1906 n1680 -10- 1 --01 1 -1-0 1 -.names PKSi_159_ PKSi_55_ n1681 -0- 1 --0 1 -.names n11 n1741 n1908 n1682 -10- 1 --01 1 -1-0 1 -.names PKSi_190_ PKSi_76_ n1683 -0- 1 --0 1 -.names n11 n1741 n1910 n1684 -10- 1 --01 1 -1-0 1 -.names PKSi_174_ PKSi_95_ n1685 -0- 1 --0 1 -.names n11 n1741 n1912 n1686 -10- 1 --01 1 -1-0 1 -.names PKSi_170_ PKSi_78_ n1687 -0- 1 --0 1 -.names n11 n1741 n1914 n1688 -10- 1 --01 1 -1-0 1 -.names [234] PKSi_87_ n1689 -0- 1 --0 1 -.names n11 n1741 n1916 n1690 -10- 1 --01 1 -1-0 1 -.names PKSi_178_ PKSi_77_ n1691 -0- 1 --0 1 -.names n11 n1741 n1918 n1692 -10- 1 --01 1 -1-0 1 -.names PKSi_184_ PKSi_81_ n1693 -0- 1 --0 1 -.names n11 n1741 n1920 n1694 -10- 1 --01 1 -1-0 1 -.names PKSi_91_ N_N2889 n1695 -0- 1 --0 1 -.names n11 n1741 n1922 n1696 -10- 1 --01 1 -1-0 1 -.names PKSi_189_ PKSi_89_ n1697 -0- 1 --0 1 -.names n11 n1741 n1924 n1698 -10- 1 --01 1 -1-0 1 -.names PKSi_171_ N_N2757 n1699 -0- 1 --0 1 -.names n11 n1741 n1926 n1700 -10- 1 --01 1 -1-0 1 -.names PKSi_83_ N_N2885 n1701 -0- 1 --0 1 -.names n11 n1741 n1928 n1702 -10- 1 --01 1 -1-0 1 -.names PKSi_182_ PKSi_74_ n1703 -0- 1 --0 1 -.names n11 n1741 n1930 n1704 -10- 1 --01 1 -1-0 1 -.names PKSi_175_ PKSi_86_ n1705 -0- 1 --0 1 -.names n11 n1741 n1932 n1706 -10- 1 --01 1 -1-0 1 -.names PKSi_94_ N_N2881 n1707 -0- 1 --0 1 -.names n11 n1741 n1934 n1708 -10- 1 --01 1 -1-0 1 -.names PKSi_72_ N_N2879 n1709 -0- 1 --0 1 -.names n11 n1741 n1936 n1710 -10- 1 --01 1 -1-0 1 -.names PKSi_80_ N_N2877 n1711 -0- 1 --0 1 -.names n11 n1741 n1938 n1712 -10- 1 --01 1 -1-0 1 -.names PKSi_180_ N_N2749 n1713 -0- 1 --0 1 -.names n11 n1741 n1940 n1714 -10- 1 --01 1 -1-0 1 -.names PKSi_177_ PKSi_73_ n1715 -0- 1 --0 1 -.names n11 n1741 n1942 n1716 -10- 1 --01 1 -1-0 1 -.names PKSi_186_ N_N2746 n1717 -0- 1 --0 1 -.names n11 n1741 n1944 n1718 -10- 1 --01 1 -1-0 1 -.names PKSi_172_ PKSi_85_ n1719 -0- 1 --0 1 -.names n11 n1741 n1946 n1720 -10- 1 --01 1 -1-0 1 -.names PKSi_179_ PKSi_93_ n1721 -0- 1 --0 1 -.names n11 n1741 n1948 n1722 -10- 1 --01 1 -1-0 1 -.names [253] PKSi_82_ n1723 -0- 1 --0 1 -.names n11 n1741 n1950 n1724 -10- 1 --01 1 -1-0 1 -.names PKSi_188_ N_N2741 n1725 -0- 1 --0 1 -.names n11 n1741 n1952 n1726 -10- 1 --01 1 -1-0 1 -.names PKSi_176_ PKSi_84_ n1727 -0- 1 --0 1 -.names n11 n1741 n1954 n1728 -10- 1 --01 1 -1-0 1 -.names PKSi_169_ PKSi_75_ n1729 -0- 1 --0 1 -.names n11 n1741 n1956 n1730 -10- 1 --01 1 -1-0 1 -.names PKSi_185_ N_N2737 n1731 -0- 1 --0 1 -.names n11 n1741 n1958 n1732 -10- 1 --01 1 -1-0 1 -.names [333] N_N2865 n1733 -0- 1 --0 1 -.names n11 n1741 n1960 n1734 -10- 1 --01 1 -1-0 1 -.names PKSi_173_ PKSi_92_ n1735 -0- 1 --0 1 -.names n11 n1741 n1962 n1736 -10- 1 --01 1 -1-0 1 -.names PKSi_183_ PKSi_79_ n1737 -0- 1 --0 1 -.names n11 n1741 n1964 n1738 -10- 1 --01 1 -1-0 1 -.names PKSi_4_ PKSi_118_ n1740 -1- 1 --1 1 -.names PKSi_23_ PKSi_102_ n1744 -1- 1 --1 1 -.names PKSi_6_ PKSi_98_ n1746 -1- 1 --1 1 -.names PKSi_15_ PKSi_119_ n1748 -1- 1 --1 1 -.names PKSi_5_ PKSi_106_ n1750 -1- 1 --1 1 -.names PKSi_9_ PKSi_112_ n1752 -1- 1 --1 1 -.names PKSi_19_ N_N2986 n1754 -1- 1 --1 1 -.names PKSi_17_ PKSi_117_ n1756 -1- 1 --1 1 -.names N_N2853 PKSi_99_ n1758 -1- 1 --1 1 -.names PKSi_11_ N_N2982 n1760 -1- 1 --1 1 -.names PKSi_2_ PKSi_110_ n1762 -1- 1 --1 1 -.names PKSi_14_ PKSi_103_ n1764 -1- 1 --1 1 -.names PKSi_22_ PKSi_96_ n1766 -1- 1 --1 1 -.names PKSi_0_ PKSi_115_ n1768 -1- 1 --1 1 -.names PKSi_8_ N_N2976 n1770 -1- 1 --1 1 -.names PKSi_18_ PKSi_108_ n1772 -1- 1 --1 1 -.names PKSi_1_ PKSi_105_ n1774 -1- 1 --1 1 -.names N_N2843 PKSi_114_ n1776 -1- 1 --1 1 -.names PKSi_13_ PKSi_100_ n1778 -1- 1 --1 1 -.names PKSi_21_ PKSi_107_ n1780 -1- 1 --1 1 -.names PKSi_10_ PKSi_109_ n1782 -1- 1 --1 1 -.names N_N2838 PKSi_116_ n1784 -1- 1 --1 1 -.names PKSi_12_ PKSi_104_ n1786 -1- 1 --1 1 -.names PKSi_3_ PKSi_97_ n1788 -1- 1 --1 1 -.names N_N2834 PKSi_113_ n1790 -1- 1 --1 1 -.names PKSi_16_ N_N2964 n1792 -1- 1 --1 1 -.names PKSi_20_ PKSi_101_ n1794 -1- 1 --1 1 -.names PKSi_7_ PKSi_111_ n1796 -1- 1 --1 1 -.names PKSi_28_ PKSi_142_ n1798 -1- 1 --1 1 -.names PKSi_47_ PKSi_126_ n1800 -1- 1 --1 1 -.names PKSi_30_ PKSi_122_ n1802 -1- 1 --1 1 -.names PKSi_39_ [282] n1804 -1- 1 --1 1 -.names PKSi_29_ PKSi_130_ n1806 -1- 1 --1 1 -.names PKSi_33_ PKSi_136_ n1808 -1- 1 --1 1 -.names PKSi_43_ N_N2954 n1810 -1- 1 --1 1 -.names PKSi_41_ PKSi_141_ n1812 -1- 1 --1 1 -.names N_N2821 PKSi_123_ n1814 -1- 1 --1 1 -.names PKSi_35_ N_N2950 n1816 -1- 1 --1 1 -.names PKSi_26_ PKSi_134_ n1818 -1- 1 --1 1 -.names PKSi_38_ PKSi_127_ n1820 -1- 1 --1 1 -.names PKSi_46_ PKSi_120_ n1822 -1- 1 --1 1 -.names PKSi_24_ N_N2945 n1824 -1- 1 --1 1 -.names PKSi_32_ N_N2943 n1826 -1- 1 --1 1 -.names PKSi_42_ PKSi_132_ n1828 -1- 1 --1 1 -.names PKSi_25_ PKSi_129_ n1830 -1- 1 --1 1 -.names N_N2811 PKSi_138_ n1832 -1- 1 --1 1 -.names PKSi_37_ PKSi_124_ n1834 -1- 1 --1 1 -.names PKSi_45_ PKSi_131_ n1836 -1- 1 --1 1 -.names PKSi_34_ PKSi_133_ n1838 -1- 1 --1 1 -.names N_N2806 PKSi_140_ n1840 -1- 1 --1 1 -.names PKSi_36_ PKSi_128_ n1842 -1- 1 --1 1 -.names PKSi_27_ PKSi_121_ n1844 -1- 1 --1 1 -.names N_N2802 PKSi_137_ n1846 -1- 1 --1 1 -.names PKSi_40_ N_N2931 n1848 -1- 1 --1 1 -.names PKSi_44_ PKSi_125_ n1850 -1- 1 --1 1 -.names PKSi_31_ PKSi_135_ n1852 -1- 1 --1 1 -.names PKSi_52_ PKSi_166_ n1854 -1- 1 --1 1 -.names PKSi_71_ PKSi_150_ n1856 -1- 1 --1 1 -.names PKSi_54_ PKSi_146_ n1858 -1- 1 --1 1 -.names PKSi_63_ PKSi_167_ n1860 -1- 1 --1 1 -.names PKSi_53_ PKSi_154_ n1862 -1- 1 --1 1 -.names PKSi_57_ PKSi_160_ n1864 -1- 1 --1 1 -.names PKSi_67_ N_N2921 n1866 -1- 1 --1 1 -.names PKSi_65_ PKSi_165_ n1868 -1- 1 --1 1 -.names N_N2789 PKSi_147_ n1870 -1- 1 --1 1 -.names PKSi_59_ N_N2917 n1872 -1- 1 --1 1 -.names PKSi_50_ PKSi_158_ n1874 -1- 1 --1 1 -.names PKSi_62_ PKSi_151_ n1876 -1- 1 --1 1 -.names PKSi_70_ PKSi_144_ n1878 -1- 1 --1 1 -.names PKSi_48_ PKSi_163_ n1880 -1- 1 --1 1 -.names PKSi_56_ PKSi_153_ n1882 -1- 1 --1 1 -.names PKSi_66_ PKSi_156_ n1884 -1- 1 --1 1 -.names PKSi_49_ N_N2909 n1886 -1- 1 --1 1 -.names N_N2779 PKSi_162_ n1888 -1- 1 --1 1 -.names PKSi_61_ PKSi_148_ n1890 -1- 1 --1 1 -.names PKSi_69_ PKSi_155_ n1892 -1- 1 --1 1 -.names PKSi_58_ PKSi_157_ n1894 -1- 1 --1 1 -.names N_N2774 PKSi_164_ n1896 -1- 1 --1 1 -.names PKSi_60_ PKSi_152_ n1898 -1- 1 --1 1 -.names PKSi_51_ PKSi_145_ n1900 -1- 1 --1 1 -.names N_N2770 PKSi_161_ n1902 -1- 1 --1 1 -.names PKSi_64_ N_N2899 n1904 -1- 1 --1 1 -.names PKSi_68_ PKSi_149_ n1906 -1- 1 --1 1 -.names PKSi_55_ PKSi_159_ n1908 -1- 1 --1 1 -.names PKSi_76_ PKSi_190_ n1910 -1- 1 --1 1 -.names PKSi_95_ PKSi_174_ n1912 -1- 1 --1 1 -.names PKSi_78_ PKSi_170_ n1914 -1- 1 --1 1 -.names PKSi_87_ [234] n1916 -1- 1 --1 1 -.names PKSi_77_ PKSi_178_ n1918 -1- 1 --1 1 -.names PKSi_81_ PKSi_184_ n1920 -1- 1 --1 1 -.names PKSi_91_ N_N2889 n1922 -1- 1 --1 1 -.names PKSi_89_ PKSi_189_ n1924 -1- 1 --1 1 -.names N_N2757 PKSi_171_ n1926 -1- 1 --1 1 -.names PKSi_83_ N_N2885 n1928 -1- 1 --1 1 -.names PKSi_74_ PKSi_182_ n1930 -1- 1 --1 1 -.names PKSi_86_ PKSi_175_ n1932 -1- 1 --1 1 -.names PKSi_94_ N_N2881 n1934 -1- 1 --1 1 -.names PKSi_72_ N_N2879 n1936 -1- 1 --1 1 -.names PKSi_80_ N_N2877 n1938 -1- 1 --1 1 -.names N_N2749 PKSi_180_ n1940 -1- 1 --1 1 -.names PKSi_73_ PKSi_177_ n1942 -1- 1 --1 1 -.names N_N2746 PKSi_186_ n1944 -1- 1 --1 1 -.names PKSi_85_ PKSi_172_ n1946 -1- 1 --1 1 -.names PKSi_93_ PKSi_179_ n1948 -1- 1 --1 1 -.names PKSi_82_ [253] n1950 -1- 1 --1 1 -.names N_N2741 PKSi_188_ n1952 -1- 1 --1 1 -.names PKSi_84_ PKSi_176_ n1954 -1- 1 --1 1 -.names PKSi_75_ PKSi_169_ n1956 -1- 1 --1 1 -.names N_N2737 PKSi_185_ n1958 -1- 1 --1 1 -.names [333] N_N2865 n1960 -1- 1 --1 1 -.names PKSi_92_ PKSi_173_ n1962 -1- 1 --1 1 -.names PKSi_79_ PKSi_183_ n1964 -1- 1 --1 1 -.names Pencrypt_0_ Pcount_0_ n1287 n1966 -10- 1 -1-1 1 --11 1 -.names Pcount_0_ n1287 n1967 -1- 1 --1 1 -.names Pcount_1_ Pcount_2_ n1968 -1- 1 --1 1 -.names [234] PKSi_191_ -1 1 -.names [234] PKSi_187_ -1 1 -.names [253] PKSi_181_ -1 1 -.names [253] PKSi_168_ -1 1 -.names [282] PKSi_143_ -1 1 -.names [282] PKSi_139_ -1 1 -.names [333] PKSi_90_ -1 1 -.names [333] PKSi_88_ -1 1 -.end diff --git a/fpga_flow/benchmarks/Blif/MCNC_big20/clma.blif b/fpga_flow/benchmarks/Blif/MCNC_big20/clma.blif deleted file mode 100644 index 6c51691e9..000000000 --- a/fpga_flow/benchmarks/Blif/MCNC_big20/clma.blif +++ /dev/null @@ -1,14167 +0,0 @@ -.model TOP -.inputs Pi416 Pi415 Pi414 Pi413 Pi412 Pi411 Pi410 Pi409 Pi408 Pi407 Pi406 \ -Pi405 Pi404 Pi403 Pi402 Pi401 Pi400 Pi399 Pi398 Pi397 Pi396 Pi395 Pi394 Pi393 \ -Pi392 Pi391 Pi390 Pi389 Pi388 Pi387 Pi386 Pi385 Pi384 Pi383 Pi382 Pi381 Pi380 \ -Pi379 Pi378 Pi377 Pi376 Pi375 Pi374 Pi373 Pi372 Pi371 Pi370 Pi369 Pi368 Pi367 \ -Pi366 Pi365 Pi364 Pi363 Pi362 Pi361 Pi360 Pi359 Pi358 Pi357 Pi356 Pi355 Pi354 \ -Pi353 Pi352 Pi351 Pi350 Pi349 Pi348 Pi347 Pi346 Pi345 Pi344 Pi343 Pi342 Pi341 \ -Pi340 Pi339 Pi338 Pi337 Pi336 Pi335 Pi334 Pi333 Pi332 Pi331 Pi330 Pi329 Pi328 \ -Pi327 Pi326 Pi325 Pi324 Pi323 Pi322 Pi321 Pi320 Pi319 Pi318 Pi317 Pi316 Pi315 \ -Pi314 Pi313 Pi312 Pi311 Pi310 Pi309 Pi308 Pi307 Pi306 Pi305 Pi304 Pi303 Pi302 \ -Pi301 Pi300 Pi299 Pi298 Pi297 Pi296 Pi295 Pi294 Pi293 Pi292 Pi291 Pi290 Pi289 \ -Pi288 Pi287 Pi286 Pi285 Pi284 Pi283 Pi282 Pi281 Pi280 Pi279 Pi278 Pi277 Pi276 \ -Pi275 Pi274 Pi273 Pi272 Pi271 Pi270 Pi269 Pi268 Pi267 Pi266 Pi265 Pi264 Pi263 \ -Pi262 Pi261 Pi260 Pi259 Pi258 Pi257 Pi256 Pi255 Pi254 Pi253 Pi252 Pi251 Pi250 \ -Pi249 Pi248 Pi247 Pi246 Pi245 Pi244 Pi243 Pi242 Pi241 Pi240 Pi239 Pi238 Pi237 \ -Pi236 Pi235 Pi234 Pi233 Pi232 Pi231 Pi230 Pi229 Pi228 Pi227 Pi226 Pi225 Pi224 \ -Pi223 Pi222 Pi221 Pi220 Pi219 Pi218 Pi217 Pi216 Pi215 Pi214 Pi213 Pi212 Pi211 \ -Pi210 Pi209 Pi208 Pi207 Pi206 Pi205 Pi204 Pi203 Pi202 Pi201 Pi200 Pi199 Pi198 \ -Pi197 Pi196 Pi195 Pi194 Pi193 Pi192 Pi191 Pi190 Pi189 Pi188 Pi187 Pi186 Pi185 \ -Pi184 Pi183 Pi182 Pi181 Pi180 Pi179 Pi178 Pi177 Pi176 Pi175 Pi174 Pi173 Pi172 \ -Pi171 Pi170 Pi169 Pi168 Pi167 Pi166 Pi165 Pi164 Pi163 Pi162 Pi161 Pi160 Pi159 \ -Pi158 Pi157 Pi156 Pi155 Pi154 Pi153 Pi152 Pi151 Pi150 Pi149 Pi148 Pi147 Pi146 \ -Pi145 Pi144 Pi143 Pi142 Pi141 Pi140 Pi139 Pi138 Pi137 Pi136 Pi135 Pi134 Pi133 \ -Pi132 Pi131 Pi130 Pi129 Pi128 Pi127 Pi126 Pi125 Pi124 Pi123 Pi122 Pi121 Pi120 \ -Pi119 Pi118 Pi117 Pi116 Pi115 Pi114 Pi113 Pi112 Pi111 Pi110 Pi109 Pi108 Pi107 \ -Pi106 Pi105 Pi104 Pi103 Pi102 Pi101 Pi100 Pi99 Pi98 Pi97 Pi96 Pi95 Pi94 Pi93 \ -Pi92 Pi91 Pi90 Pi89 Pi88 Pi87 Pi86 Pi85 Pi84 Pi83 Pi82 Pi81 Pi80 Pi79 Pi78 \ -Pi77 Pi76 Pi75 Pi74 Pi73 Pi72 Pi71 Pi70 Pi69 Pi68 Pi67 Pi66 Pi65 Pi64 Pi63 \ -Pi62 Pi61 Pi60 Pi59 Pi58 Pi57 Pi56 Pi55 Pi54 Pi53 Pi52 Pi51 Pi50 Pi49 Pi28 \ -Pi27 Pi26 Pi25 Pi24 Pi23 Pi22 Pi21 Pi20 Pi19 Pi18 Pi17 Pi16 Pi15 PCLK -.outputs P__cmxir_1 P__cmxir_0 P__cmxig_1 P__cmxig_0 P__cmxcl_1 P__cmxcl_0 \ -P__cmx1ad_35 P__cmx1ad_34 P__cmx1ad_33 P__cmx1ad_32 P__cmx1ad_31 P__cmx1ad_30 \ -P__cmx1ad_29 P__cmx1ad_28 P__cmx1ad_27 P__cmx1ad_26 P__cmx1ad_25 P__cmx1ad_24 \ -P__cmx1ad_23 P__cmx1ad_22 P__cmx1ad_21 P__cmx1ad_20 P__cmx1ad_19 P__cmx1ad_18 \ -P__cmx1ad_17 P__cmx1ad_16 P__cmx1ad_15 P__cmx1ad_14 P__cmx1ad_13 P__cmx1ad_12 \ -P__cmx1ad_11 P__cmx1ad_10 P__cmx1ad_9 P__cmx1ad_8 P__cmx1ad_7 P__cmx1ad_6 \ -P__cmx1ad_5 P__cmx1ad_4 P__cmx1ad_3 P__cmx1ad_2 P__cmx1ad_1 P__cmx1ad_0 \ -P__cmx0ad_35 P__cmx0ad_34 P__cmx0ad_33 P__cmx0ad_32 P__cmx0ad_31 P__cmx0ad_30 \ -P__cmx0ad_29 P__cmx0ad_28 P__cmx0ad_27 P__cmx0ad_26 P__cmx0ad_25 P__cmx0ad_24 \ -P__cmx0ad_23 P__cmx0ad_22 P__cmx0ad_21 P__cmx0ad_20 P__cmx0ad_19 P__cmx0ad_18 \ -P__cmx0ad_17 P__cmx0ad_16 P__cmx0ad_15 P__cmx0ad_14 P__cmx0ad_13 P__cmx0ad_12 \ -P__cmx0ad_11 P__cmx0ad_10 P__cmx0ad_9 P__cmx0ad_8 P__cmx0ad_7 P__cmx0ad_6 \ -P__cmx0ad_5 P__cmx0ad_4 P__cmx0ad_3 P__cmx0ad_2 P__cmx0ad_1 P__cmx0ad_0 \ -P__cmnxcp_1 P__cmnxcp_0 P__cmndst1p0 P__cmndst0p0 -.latch Nv2 Ni48 re PCLK 2 -.latch Nv14 Ni47 re PCLK 2 -.latch Nv31 Ni46 re PCLK 2 -.latch Nv43 Ni45 re PCLK 2 -.latch Nv59 Ni44 re PCLK 2 -.latch N_N13960 Ni43 re PCLK 2 -.latch N_N13959 Ni42 re PCLK 2 -.latch Nv243 Ni41 re PCLK 2 -.latch Nv294 Ni40 re PCLK 2 -.latch Nv345 Ni39 re PCLK 2 -.latch Nv349 Ni38 re PCLK 2 -.latch Nv437 Ni37 re PCLK 2 -.latch Nv499 Ni36 re PCLK 2 -.latch Nv550 Ni35 re PCLK 2 -.latch Nv601 Ni34 re PCLK 2 -.latch Nv2153 Ni33 re PCLK 2 -.latch Nv3888 Ni32 re PCLK 2 -.latch Nv6425 Ni31 re PCLK 2 -.latch Nv6437 Ni30 re PCLK 2 -.latch Nv8909 n18 re PCLK 2 -.latch Nv10056 Ni14 re PCLK 2 -.latch Nv10068 Ni13 re PCLK 2 -.latch Nv10082 Ni12 re PCLK 2 -.latch Nv10091 Ni11 re PCLK 2 -.latch Nv10099 Ni10 re PCLK 2 -.latch Nv10112 Ni9 re PCLK 2 -.latch Nv10126 Ni8 re PCLK 2 -.latch Nv10135 Ni7 re PCLK 2 -.latch Nv10143 Ni6 re PCLK 2 -.latch Nv10247 Ni5 re PCLK 2 -.latch Nv10316 Ni4 re PCLK 2 -.latch P__cmxcl_0 Ni3 re PCLK 2 -.latch N_N13958 Ni2 re PCLK 2 -.names n157 n3113 n3540 P__cmxir_1 -100 1 -.names n138 n3476 P__cmxir_0 -00 1 -.names n157 P__cmxig_1 -0 1 -.names n3837 P__cmxig_0 -0 1 -.names n3540 P__cmxcl_1 -0 1 -.names n3540 P__cmxcl_0 -0 1 -.names P__cmx1ad_35 -.names P__cmx1ad_34 -.names P__cmx1ad_33 -.names P__cmx1ad_32 -.names Pi255 n3880 P__cmx1ad_31 -10 1 -.names Pi254 n3880 P__cmx1ad_30 -10 1 -.names Pi253 n3880 P__cmx1ad_29 -10 1 -.names Pi252 n3880 P__cmx1ad_28 -10 1 -.names Pi251 n3880 P__cmx1ad_27 -10 1 -.names Pi250 n3880 P__cmx1ad_26 -10 1 -.names Pi249 n3880 P__cmx1ad_25 -10 1 -.names Pi248 n3880 P__cmx1ad_24 -10 1 -.names Pi247 n3880 P__cmx1ad_23 -10 1 -.names Pi246 n3880 P__cmx1ad_22 -10 1 -.names Pi245 n3880 P__cmx1ad_21 -10 1 -.names Pi244 n3880 P__cmx1ad_20 -10 1 -.names Pi243 n3880 P__cmx1ad_19 -10 1 -.names Pi242 n3880 P__cmx1ad_18 -10 1 -.names Pi241 n3880 P__cmx1ad_17 -10 1 -.names Pi240 n3880 P__cmx1ad_16 -10 1 -.names Pi27 Pi26 n3880 P__cmx1ad_15 -110 1 -.names n3966 P__cmx1ad_14 -0 1 -.names n161 n3880 P__cmx1ad_13 -10 1 -.names n4813 P__cmx1ad_12 -0 1 -.names P__cmx1ad_11 -.names P__cmx1ad_10 -.names n3880 P__cmx1ad_9 -0 1 -.names P__cmx1ad_8 -.names Pi239 n3880 P__cmx1ad_7 -10 1 -.names Pi238 n3880 P__cmx1ad_6 -10 1 -.names Pi237 n3880 P__cmx1ad_5 -10 1 -.names Pi236 n3880 P__cmx1ad_4 -10 1 -.names Pi235 n3880 P__cmx1ad_3 -10 1 -.names Pi234 n3880 P__cmx1ad_2 -10 1 -.names Pi233 n3880 P__cmx1ad_1 -10 1 -.names Pi232 n3880 P__cmx1ad_0 -10 1 -.names P__cmx0ad_35 -.names P__cmx0ad_34 -.names P__cmx0ad_33 -.names P__cmx0ad_32 -.names Pi72 n3881 P__cmx0ad_31 -10 1 -.names Pi71 n3881 P__cmx0ad_30 -10 1 -.names Pi70 n3881 P__cmx0ad_29 -10 1 -.names Pi69 n3881 P__cmx0ad_28 -10 1 -.names Pi68 n3881 P__cmx0ad_27 -10 1 -.names Pi67 n3881 P__cmx0ad_26 -10 1 -.names Pi66 n3881 P__cmx0ad_25 -10 1 -.names Pi65 n3881 P__cmx0ad_24 -10 1 -.names Pi64 n3881 P__cmx0ad_23 -10 1 -.names Pi63 n3881 P__cmx0ad_22 -10 1 -.names Pi62 n3881 P__cmx0ad_21 -10 1 -.names Pi61 n3881 P__cmx0ad_20 -10 1 -.names Pi60 n3881 P__cmx0ad_19 -10 1 -.names Pi59 n3881 P__cmx0ad_18 -10 1 -.names Pi58 n3881 P__cmx0ad_17 -10 1 -.names Pi57 n3881 P__cmx0ad_16 -10 1 -.names Pi24 Pi23 n3881 P__cmx0ad_15 -110 1 -.names n3967 P__cmx0ad_14 -0 1 -.names n160 n3881 P__cmx0ad_13 -10 1 -.names n4815 P__cmx0ad_12 -0 1 -.names P__cmx0ad_11 -.names P__cmx0ad_10 -.names n3881 P__cmx0ad_9 -0 1 -.names P__cmx0ad_8 -.names Pi56 n3881 P__cmx0ad_7 -10 1 -.names Pi55 n3881 P__cmx0ad_6 -10 1 -.names Pi54 n3881 P__cmx0ad_5 -10 1 -.names Pi53 n3881 P__cmx0ad_4 -10 1 -.names Pi52 n3881 P__cmx0ad_3 -10 1 -.names Pi51 n3881 P__cmx0ad_2 -10 1 -.names Pi50 n3881 P__cmx0ad_1 -10 1 -.names Pi49 n3881 P__cmx0ad_0 -10 1 -.names n159 P__cmnxcp_1 -0 1 -.names n158 P__cmnxcp_0 -0 1 -.names n153 n3593 P__cmndst1p0 -10 1 -.names n150 n3879 P__cmndst0p0 -10 1 -.names Pi22 n3478 n3482 Ni48 n19 --0-0 1 -001- 1 -.names n19 Nv2 -0 1 -.names Pi20 n299 n2947 n2946 n20 -101- 1 --011 1 -.names Pi21 Ni32 n2065 Ni46 n21 -1--1 1 --001 1 -.names n20 n21 Nv31 -1- 1 --1 1 -.names Ni44 n3592 n3687 n22 -0-0 1 --00 1 -.names n22 Nv59 -0 1 -.names Ni44 Ni39 n25 -11 1 -00 1 -.names n25 Ni38 n24 -11 1 -.names n25 Ni32 Ni37 n24 n23 -111- 1 -11-1 1 -.names n2040 n2954 Ni41 n26 -11- 1 --10 1 -.names n26 Nv243 -0 1 -.names n2040 n2952 Ni40 n27 -11- 1 --10 1 -.names n27 Nv294 -0 1 -.names n32 n2028 Ni39 n28 -11- 1 --10 1 -.names n28 Nv345 -0 1 -.names n694 n2025 n2937 n3735 n29 -0-00 1 --000 1 -.names n190 n400 n796 n2937 n30 -1-00 1 --000 1 -.names Pi15 n107 n3879 n31 -100 1 -.names Ni32 n2055 n32 -01 1 -.names n2937 n2939 n3879 n34 -010 1 -.names n29 n30 n31 n32 n34 n4835 Nv349 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------0 1 -.names Ni36 n2040 n2048 n2052 n35 -0-01 1 --101 1 -.names n35 Nv499 -0 1 -.names Ni35 n2036 n2042 n2040 n36 -001- 1 --011 1 -.names n36 Nv550 -0 1 -.names Ni34 n2016 n3540 n3657 n37 -00-0 1 --000 1 -.names n37 Nv601 -0 1 -.names Ni44 n104 Ni42 n38 -0-0 1 --00 1 -.names Ni44 n104 Ni42 n42 -1-0 1 --00 1 -.names Ni47 Ni45 n44 -00 1 -.names Ni42 Ni43 n45 -0- 1 --1 1 -.names n44 n45 n43 -11 1 -.names n3471 n3477 n3476 n3474 n46 --11- 1 -01-1 1 -.names n46 Nv2153 -0 1 -.names n1653 n2932 n2936 n4391 n47 -001- 1 --010 1 -.names n47 Nv3888 -0 1 -.names n43 n200 n1660 n3540 n48 -0-10 1 --010 1 -.names Ni32 Ni30 n1866 n3540 n49 -0010 1 -.names n48 n49 Ni31 Nv6425 -1-- 1 --1- 1 ---1 1 -.names Ni30 n1657 n1658 n3540 n50 -011- 1 --110 1 -.names n50 Nv6437 -0 1 -.names n878 n879 n52 n877 n55 -111- 1 -11-1 1 -.names n4823 n79 n52 -11 1 -.names n200 Ni36 n53 -0- 1 --0 1 -.names n55 n52 n53 n1063 n51 -11-0 1 -1-10 1 -.names n878 n879 n59 n882 n60 -111- 1 -11-1 1 -.names n4825 n79 n59 -11 1 -.names n53 n60 n59 n1063 n58 -11-0 1 --110 1 -.names n62 n390 Ni38 n64 -11- 1 --10 1 -.names n111 Ni35 n1063 n65 -1-0 1 --00 1 -.names n52 n79 Ni40 n62 -11- 1 --10 1 -.names Ni37 Ni36 n63 -1- 1 --0 1 -.names n64 n65 n62 n63 n61 -111- 1 -11-1 1 -.names n67 n390 Ni38 n68 -11- 1 --10 1 -.names n114 Ni35 n1063 n69 -1-0 1 --00 1 -.names n59 n79 Ni40 n67 -11- 1 --10 1 -.names n68 n69 n67 n63 n66 -111- 1 -11-1 1 -.names n71 n390 Ni38 n72 -11- 1 --10 1 -.names Ni35 n116 n1063 n73 -1-0 1 --10 1 -.names n79 Ni40 n52 n71 -11- 1 -1-1 1 -.names n72 n73 n71 n63 n70 -111- 1 -11-1 1 -.names n75 n390 Ni38 n76 -11- 1 --10 1 -.names Ni35 n118 n1063 n77 -1-0 1 --10 1 -.names n79 Ni40 n59 n75 -11- 1 -1-1 1 -.names n76 n77 n75 n63 n74 -111- 1 -11-1 1 -.names n79 n390 Ni38 n80 -11- 1 --10 1 -.names n104 n835 Ni41 n79 -11- 1 -1-0 1 -.names n63 n80 n79 n1063 n78 -11-0 1 --110 1 -.names n878 n879 n82 n877 n83 -111- 1 -11-1 1 -.names n104 n4823 n82 -11 1 -.names n53 n83 n82 n1063 n81 -11-0 1 --110 1 -.names n878 n879 n85 n882 n86 -111- 1 -11-1 1 -.names n104 n4825 n85 -11 1 -.names n53 n86 n85 n1063 n84 -11-0 1 --110 1 -.names n88 n390 Ni38 n89 -11- 1 --10 1 -.names Ni35 n122 n1063 n90 -0-0 1 --10 1 -.names n82 n104 Ni40 n88 -11- 1 --10 1 -.names n89 n90 n88 n63 n87 -111- 1 -11-1 1 -.names n92 n390 Ni38 n93 -11- 1 --10 1 -.names Ni35 n124 n1063 n94 -0-0 1 --10 1 -.names n85 n104 Ni40 n92 -11- 1 --10 1 -.names n93 n94 n92 n63 n91 -111- 1 -11-1 1 -.names n96 n390 Ni38 n97 -11- 1 --10 1 -.names Ni35 n126 n1063 n98 -1-0 1 --10 1 -.names n104 Ni40 n82 n96 -11- 1 -1-1 1 -.names n97 n98 n96 n63 n95 -111- 1 -11-1 1 -.names n100 n390 Ni38 n101 -11- 1 --10 1 -.names Ni35 n128 n1063 n102 -1-0 1 --10 1 -.names n104 Ni40 n85 n100 -11- 1 -1-1 1 -.names n101 n102 n100 n63 n99 -111- 1 -11-1 1 -.names n104 n390 Ni38 n105 -11- 1 --10 1 -.names n44 Ni43 n104 -10 1 -.names n63 n105 n104 n1063 n103 -11-0 1 --110 1 -.names n390 n1063 n108 -10 1 -.names Ni36 Ni38 n107 -0- 1 --0 1 -.names n55 n108 n52 n107 n106 -111- 1 -11-1 1 -.names n60 n108 n59 n107 n109 -111- 1 -11-1 1 -.names n62 n202 n111 -1- 1 --1 1 -.names n64 n111 Ni35 n1063 n110 -11-0 1 -1-00 1 -.names n67 n240 n114 -1- 1 --1 1 -.names n68 n114 Ni35 n1063 n113 -11-0 1 -1-00 1 -.names n71 n202 n116 -1- 1 --1 1 -.names n72 Ni35 n116 n1063 n115 -11-0 1 -1-10 1 -.names n75 n240 n118 -1- 1 --1 1 -.names n76 Ni35 n118 n1063 n117 -11-0 1 -1-10 1 -.names n108 n83 n82 n107 n119 -111- 1 -11-1 1 -.names n108 n86 n85 n107 n120 -111- 1 -11-1 1 -.names n88 n202 n122 -1- 1 --1 1 -.names n89 Ni35 n122 n1063 n121 -10-0 1 -1-10 1 -.names n92 n240 n124 -1- 1 --1 1 -.names n93 Ni35 n124 n1063 n123 -10-0 1 -1-10 1 -.names n96 n202 n126 -1- 1 --1 1 -.names n97 Ni35 n126 n1063 n125 -11-0 1 -1-10 1 -.names n100 n240 n128 -1- 1 --1 1 -.names n101 Ni35 n128 n1063 n127 -11-0 1 -1-10 1 -.names Ni47 n320 n130 -1- 1 --1 1 -.names Ni44 n130 Ni41 n129 -0-0 1 --10 1 -.names Ni45 n320 n133 -1- 1 --1 1 -.names Ni44 n133 Ni41 n132 -0-0 1 --10 1 -.names Ni44 n130 Ni41 n134 -1-0 1 --10 1 -.names Ni44 n133 Ni41 n135 -1-0 1 --10 1 -.names Ni14 n3545 n3569 Ni2 n136 -0-0- 1 --100 1 -.names n136 Nv10056 -0 1 -.names Ni13 n3540 n3564 n3568 n137 -0-1- 1 --010 1 -.names n137 Nv10068 -0 1 -.names Pi25 Ni10 n140 -0- 1 --1 1 -.names n140 Ni10 Ni9 n3837 n138 -100- 1 -1-00 1 -.names n3540 n3555 Ni9 n3844 n142 --10- 1 -01-0 1 -.names n142 Nv10112 -0 1 -.names n2049 Ni8 n3540 n3549 n143 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names n143 Nv10126 -0 1 -.names Ni6 n3544 n3548 n4805 n144 -1-10 1 --110 1 -.names n144 Nv10143 -0 1 -.names Ni6 n3488 n3705 n3876 n145 -100- 1 -1-00 1 -.names n3542 n3543 n2066 n3539 n149 -111- 1 -11-1 1 -.names n149 Nv10247 -0 1 -.names Ni37 Ni38 n150 -01 1 -.names Ni32 Ni30 n153 -0- 1 --0 1 -.names n18 Ni33 n157 -0- 1 --0 1 -.names n3615 n3616 n3611 n3540 n158 -111- 1 -11-1 1 -.names n3540 n3601 n3604 n3608 n159 -1-01 1 --101 1 -.names Pi23 Pi24 n160 -1- 1 --1 1 -.names Pi26 Pi27 n161 -1- 1 --1 1 -.names n153 n3592 n3590 n3591 n162 -01-- 1 --111 1 -.names n162 N_N13960 -0 1 -.names Ni34 Ni30 Ni32 Ni31 n163 -11-- 1 -1-1- 1 -1--1 1 -.names Pi21 n2328 n166 -0- 1 --0 1 -.names n160 Ni30 n166 n953 n164 -111- 1 --110 1 -.names Pi24 Pi23 n168 -1- 1 --0 1 -.names Ni30 n166 n168 n953 n167 -111- 1 -11-0 1 -.names n3640 n3843 n3863 n171 -0-- 1 --1- 1 ---1 1 -.names n171 n1471 n4827 n169 -10- 1 --00 1 -.names n171 n1866 n3342 n4827 n173 -10-- 1 --00- 1 --0-0 1 -.names n3843 n3592 n177 -1- 1 --1 1 -.names Ni32 Ni31 n178 -0- 1 --0 1 -.names n177 n178 n176 -11 1 -.names n3666 n2083 n180 -11 1 -.names n180 Ni33 n2068 n179 -1-0 1 --00 1 -.names n180 Ni33 n2068 n183 -1-0 1 --10 1 -.names n23 Ni31 n153 n184 -0-0 1 --10 1 -.names Pi20 n3060 n3869 n188 -01- 1 --10 1 -.names Ni35 Ni30 n190 -00 1 -.names n171 n4827 n193 -1- 1 --0 1 -.names Pi22 n193 n3342 n192 -11- 1 -1-0 1 -.names n2069 Ni45 n2068 n195 -11- 1 -1-1 1 -.names n178 n3687 n196 -10 1 -.names n195 n196 n194 -11 1 -.names Ni37 Ni38 n200 -0- 1 --1 1 -.names n269 Ni40 n457 n198 -11- 1 -1-1 1 -.names Ni37 n200 n198 n197 -01- 1 --11 1 -.names n2961 n3722 n202 -0- 1 --1 1 -.names n43 n198 n202 n201 -11- 1 -1-1 1 -.names n43 n150 n198 n197 n203 -10-1 1 -1-11 1 -.names n198 n63 n203 n2087 n206 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n197 n206 Ni35 n201 n205 -111- 1 -11-1 1 -.names Ni37 n44 Ni36 n2961 n207 -0-1- 1 -01-0 1 -.names n510 n511 n212 -1- 1 --1 1 -.names Ni36 n207 n210 -01 1 -.names Ni35 n2094 n211 -1- 1 --1 1 -.names n212 n210 n211 n209 -11- 1 -1-1 1 -.names n272 Ni40 n463 n214 -11- 1 -1-1 1 -.names Ni37 n200 n214 n213 -01- 1 --11 1 -.names n3718 n3724 n216 -1- 1 --1 1 -.names n216 n213 n214 n202 n215 -111- 1 -11-1 1 -.names Ni38 n3718 n218 -1- 1 --1 1 -.names n150 n214 n213 n218 n217 -0-11 1 --111 1 -.names n214 n464 n213 n275 n220 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n217 n3726 n215 n397 n221 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n220 n221 n219 -11 1 -.names n278 Ni40 n470 n223 -11- 1 -1-1 1 -.names Ni37 n200 n223 n222 -01- 1 --11 1 -.names n3749 n3724 n225 -1- 1 --1 1 -.names n225 n222 n223 n202 n224 -111- 1 -11-1 1 -.names Ni38 n3749 n227 -1- 1 --1 1 -.names n150 n223 n222 n227 n226 -0-11 1 --111 1 -.names n224 n400 n222 n281 n229 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n226 n3721 n223 n471 n230 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n229 n230 n228 -11 1 -.names n219 n228 n231 -11 1 -.names n231 n3719 n205 n288 n234 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names Ni32 n841 n233 -1- 1 --1 1 -.names n209 n234 n198 n233 n232 -111- 1 -11-1 1 -.names n18 n1063 n236 -1- 1 --0 1 -.names n236 n232 n18 n205 n235 -111- 1 -11-1 1 -.names n269 Ni40 n483 n238 -11- 1 -1-1 1 -.names Ni37 n200 n238 n237 -01- 1 --11 1 -.names n2962 n3722 n240 -0- 1 --1 1 -.names n43 n238 n240 n239 -11- 1 -1-1 1 -.names n43 n150 n238 n237 n241 -10-1 1 -1-11 1 -.names n238 n63 n241 n2087 n243 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n237 n243 Ni35 n239 n242 -111- 1 -11-1 1 -.names Ni37 n44 Ni36 n2962 n244 -0-1- 1 -01-0 1 -.names Ni36 n244 n247 -01 1 -.names n212 n247 n211 n246 -11- 1 -1-1 1 -.names n272 Ni40 n488 n249 -11- 1 -1-1 1 -.names Ni37 n200 n249 n248 -01- 1 --11 1 -.names n3718 n3725 n251 -1- 1 --1 1 -.names n251 n248 n249 n240 n250 -111- 1 -11-1 1 -.names n150 n218 n249 n248 n252 -01-1 1 --111 1 -.names n249 n464 n248 n275 n254 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n252 n3726 n250 n397 n255 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n254 n255 n253 -11 1 -.names n278 Ni40 n494 n257 -11- 1 -1-1 1 -.names Ni37 n200 n257 n256 -01- 1 --11 1 -.names n3749 n3725 n259 -1- 1 --1 1 -.names n259 n256 n257 n240 n258 -111- 1 -11-1 1 -.names n150 n227 n257 n256 n260 -01-1 1 --111 1 -.names n258 n400 n256 n281 n262 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n260 n3721 n257 n471 n263 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n262 n263 n261 -11 1 -.names n253 n261 n264 -11 1 -.names n264 n3719 n242 n288 n266 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n246 n266 n238 n233 n265 -111- 1 -11-1 1 -.names n236 n265 n18 n242 n267 -111- 1 -11-1 1 -.names n313 Ni41 n269 -10 1 -.names n43 n200 n269 Ni38 n268 -111- 1 -11-0 1 -.names n130 Ni41 n272 -00 1 -.names n200 n218 n272 Ni38 n271 -111- 1 -11-0 1 -.names n272 n200 n273 -11 1 -.names Ni32 Ni36 n275 -1- 1 --0 1 -.names Ni32 Ni36 n276 -1- 1 --1 1 -.names n273 n275 n271 n276 n274 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n133 Ni41 n278 -00 1 -.names n200 n227 n278 Ni38 n277 -111- 1 -11-0 1 -.names Ni32 Ni36 n281 -0- 1 --0 1 -.names Ni32 n278 n277 n281 n279 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names n274 n279 n3719 n282 -0-0 1 --00 1 -.names n269 n233 n510 n2094 n290 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names Ni36 n269 n268 n287 -0-1 1 --11 1 -.names n18 n2068 n288 -0- 1 --1 1 -.names n282 n290 n287 n288 n286 -011- 1 -01-1 1 -.names n236 n286 n18 n287 n291 -111- 1 -11-1 1 -.names Pi22 Ni30 n294 -1- 1 --0 1 -.names Pi22 n178 n294 n292 -1-1 1 --01 1 -.names n292 Pi22 n18 n295 -11- 1 -1-1 1 -.names Pi21 Ni30 n297 -1- 1 --0 1 -.names n297 Ni31 Pi21 n296 -11- 1 -1-1 1 -.names n2073 n296 n299 -11 1 -.names n299 Pi21 n18 n298 -11- 1 -1-1 1 -.names Pi21 Pi20 n301 -10 1 -.names n228 n301 n300 -01 1 -.names Pi20 Pi21 n304 -11 1 -.names Pi22 n261 n300 n304 n303 -0-1- 1 -00-1 1 -.names n295 Pi22 n279 n308 -11- 1 -1-1 1 -.names n298 n308 Pi21 n274 n307 -111- 1 -11-1 1 -.names Pi19 n307 n3732 n311 -11- 1 -0-0 1 --10 1 -.names n291 n1250 n235 n891 n312 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names Pi19 n3729 n310 -1- 1 --1 1 -.names n311 n312 n267 n310 n309 -111- 1 -11-1 1 -.names n104 Ni42 n313 -10 1 -.names n313 Ni40 n564 n315 -11- 1 -1-1 1 -.names Ni37 n200 n315 n314 -01- 1 --11 1 -.names n43 n315 n202 n316 -11- 1 -1-1 1 -.names n43 n150 n315 n314 n317 -10-1 1 -1-11 1 -.names n315 n63 n317 n2087 n319 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n314 n319 Ni35 n316 n318 -111- 1 -11-1 1 -.names Ni43 Ni42 n320 -1- 1 --1 1 -.names n130 n568 Ni40 n322 -01- 1 -0-1 1 -.names Ni37 n200 n322 n321 -01- 1 --11 1 -.names n216 n321 n322 n202 n323 -111- 1 -11-1 1 -.names n150 n218 n322 n321 n324 -01-1 1 --111 1 -.names n322 n464 n321 n275 n326 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n324 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--11- 1 -1--1 1 --1-1 1 -.names n2101 n2104 n2115 -11 1 -.names n2070 n2116 n2115 n310 n2114 -111- 1 -11-1 1 -.names n2076 Ni40 n2118 -1- 1 --1 1 -.names n2079 n2118 n2083 n2084 n2117 -1111 1 -.names n2117 n2086 n2087 n2119 -11- 1 -1-1 1 -.names n179 n2069 n2119 n2120 -01- 1 --10 1 -.names n2069 n2068 n2119 n2122 -11- 1 -1-0 1 -.names n153 n2122 n2124 -11 1 -.names n18 n2094 n2124 n2123 -11- 1 --11 1 -.names n2095 Ni40 n2126 -1- 1 --1 1 -.names n2079 n2126 n2083 n2099 n2125 -1111 1 -.names n2125 n2086 n2087 n2127 -11- 1 -1-1 1 -.names n179 n2069 n2127 n2128 -01- 1 --10 1 -.names n2069 n2068 n2127 n2130 -11- 1 -1-0 1 -.names n153 n2130 n2132 -11 1 -.names n18 n2094 n2132 n2131 -11- 1 --11 1 -.names n2086 n2083 n2079 n2134 -111 1 -.names n2079 n2083 Ni36 n2134 n2133 -111- 1 -11-1 1 -.names n179 n2069 n2133 n2135 -01- 1 --10 1 -.names n2069 n2068 n2133 n2137 -11- 1 -1-0 1 -.names n153 n2137 n2139 -11 1 -.names n18 n2094 n2139 n2138 -11- 1 --11 1 -.names n2379 n1250 n4365 n891 n2142 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n2128 n2131 n2141 -11 1 -.names n2070 n2142 n2141 n310 n2140 -111- 1 -11-1 1 -.names n2080 n2086 n2199 n2143 -11- 1 -1-0 1 -.names n179 n2069 n2143 n2145 -01- 1 --10 1 -.names n2069 n2068 n2143 n2147 -11- 1 -1-0 1 -.names n153 n2147 n2149 -11 1 -.names n18 n2094 n2149 n2148 -11- 1 --11 1 -.names n2086 n2097 n2199 n2150 -11- 1 --10 1 -.names n179 n2069 n2150 n2151 -01- 1 --10 1 -.names n2069 n2068 n2150 n2153 -11- 1 -1-0 1 -.names n153 n2153 n2155 -11 1 -.names n18 n2094 n2155 n2154 -11- 1 --11 1 -.names n179 n2069 n2108 n2156 -01- 1 --10 1 -.names n2069 n2068 n2108 n2158 -11- 1 -1-0 1 -.names n153 n2158 n2160 -11 1 -.names n18 n2094 n2160 n2159 -11- 1 --11 1 -.names n2351 n1250 n4373 n891 n2163 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n2151 n2154 n2162 -11 1 -.names n2070 n2163 n2162 n310 n2161 -111- 1 -11-1 1 -.names n2086 n2117 n2199 n2164 -11- 1 --10 1 -.names n179 n2069 n2164 n2165 -01- 1 --10 1 -.names n2069 n2068 n2164 n2167 -11- 1 -1-0 1 -.names n153 n2167 n2169 -11 1 -.names n18 n2094 n2169 n2168 -11- 1 --11 1 -.names n2086 n2125 n2199 n2170 -11- 1 --10 1 -.names n179 n2069 n2170 n2171 -01- 1 --10 1 -.names n2069 n2068 n2170 n2173 -11- 1 -1-0 1 -.names n153 n2173 n2175 -11 1 -.names n18 n2094 n2175 n2174 -11- 1 --11 1 -.names n179 n2069 n2134 n2176 -01- 1 --10 1 -.names n2069 n2068 n2134 n2178 -11- 1 -1-0 1 -.names n153 n2178 n2180 -11 1 -.names n18 n2094 n2180 n2179 -11- 1 --11 1 -.names n2352 n1250 n4375 n891 n2183 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n2171 n2174 n2182 -11 1 -.names n2070 n2183 n2182 n310 n2181 -111- 1 -11-1 1 -.names n2106 n2076 n2184 -11 1 -.names n179 n2069 n3851 n2185 -01- 1 --10 1 -.names n2069 n2068 n3851 n2187 -11- 1 -1-0 1 -.names n153 n2187 n2189 -11 1 -.names n18 n2094 n2189 n2188 -11- 1 --11 1 -.names n2106 n2095 n2190 -11 1 -.names n179 n2069 n3852 n2191 -01- 1 --10 1 -.names n2069 n2068 n3852 n2193 -11- 1 -1-0 1 -.names n153 n2193 n2195 -11 1 -.names n18 n2094 n2195 n2194 -11- 1 --11 1 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n2069 n2248 n2247 -01- 1 --11 1 -.names n2069 n2068 n2248 n2249 -11- 1 -1-1 1 -.names n153 n2249 n2251 -11 1 -.names n18 n2094 n2251 n2250 -11- 1 --11 1 -.names n3852 n4822 n2253 -0- 1 --0 1 -.names n179 n2069 n2253 n2252 -01- 1 --11 1 -.names n2069 n2068 n2253 n2254 -11- 1 -1-1 1 -.names n153 n2254 n2256 -11 1 -.names n18 n2094 n2256 n2255 -11- 1 --11 1 -.names n2086 n2087 n2196 n2257 -1-1 1 --01 1 -.names n179 n2069 n2257 n2259 -01- 1 --10 1 -.names n2069 n2068 n2257 n2261 -11- 1 -1-0 1 -.names n153 n2261 n2263 -11 1 -.names n18 n2094 n2263 n2262 -11- 1 --11 1 -.names n2086 n2087 n2205 n2264 -1-1 1 --01 1 -.names n179 n2069 n2264 n2265 -01- 1 --10 1 -.names n2069 n2068 n2264 n2267 -11- 1 -1-0 1 -.names n153 n2267 n2269 -11 1 -.names n18 n2094 n2269 n2268 -11- 1 --11 1 -.names n4378 n3776 n2444 n1692 n2272 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n2070 n2447 n310 n2273 -11- 1 -1-1 1 -.names n2247 n2250 n2271 -11 1 -.names n2272 n2273 n2271 n891 n2270 -111- 1 -11-1 1 -.names n3854 n4822 n2275 -0- 1 --0 1 -.names n179 n2069 n2275 n2274 -01- 1 --11 1 -.names n2069 n2068 n2275 n2276 -11- 1 -1-1 1 -.names n153 n2276 n2278 -11 1 -.names n18 n2094 n2278 n2277 -11- 1 --11 1 -.names n3855 n4822 n2280 -0- 1 --0 1 -.names n179 n2069 n2280 n2279 -01- 1 --11 1 -.names n2069 n2068 n2280 n2281 -11- 1 -1-1 1 -.names n153 n2281 n2283 -11 1 -.names n18 n2094 n2283 n2282 -11- 1 --11 1 -.names n2086 n2087 n2227 n2284 -1-1 1 --01 1 -.names n179 n2069 n2284 n2285 -01- 1 --10 1 -.names n2069 n2068 n2284 n2287 -11- 1 -1-0 1 -.names n153 n2287 n2289 -11 1 -.names n18 n2094 n2289 n2288 -11- 1 --11 1 -.names n2086 n2087 n2235 n2290 -1-1 1 --01 1 -.names n179 n2069 n2290 n2291 -01- 1 --10 1 -.names n2069 n2068 n2290 n2293 -11- 1 -1-0 1 -.names n153 n2293 n2295 -11 1 -.names n18 n2094 n2295 n2294 -11- 1 --11 1 -.names n4381 n3776 n2433 n1692 n2298 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n2070 n2436 n310 n2299 -11- 1 -1-1 1 -.names n2274 n2277 n2297 -11 1 -.names n2298 n2299 n2297 n891 n2296 -111- 1 -11-1 1 -.names n2325 n2070 n2302 -11 1 -.names n931 n934 n2302 n3900 n2300 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names Pi27 Ni32 n176 n2069 n2303 -0-11 1 --011 1 -.names Pi22 Pi21 n3677 n4730 n2306 -1--1 1 --0-1 1 ---11 1 -.names Pi26 n2754 n3672 n2305 -0-1 1 --11 1 -.names n2306 n2305 n1866 n2304 -11- 1 -1-1 1 -.names Pi27 Ni32 n176 n2069 n2307 -1-11 1 --011 1 -.names Pi21 n2307 n3901 n2310 -01- 1 -1-0 1 --10 1 -.names n3668 Pi27 n2754 n2309 -11- 1 -1-1 1 -.names n2310 n2309 n1866 n2308 -11- 1 -1-1 1 -.names n2302 n940 n2308 n3525 n2313 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names Ni12 n3798 n2312 -0- 1 --1 1 -.names n2300 n2313 n2304 n2312 n2311 -111- 1 -11-1 1 -.names Pi22 Pi21 n3682 n4735 n2316 -1--0 1 --0-0 1 ---10 1 -.names n3672 Pi26 n2754 n2315 -11- 1 -1-1 1 -.names n2316 n2315 n1866 n2314 -11- 1 -1-1 1 -.names Pi24 Pi21 n194 n2071 n2317 -01-0 1 --100 1 -.names Pi21 n3678 n2323 -1- 1 --1 1 -.names Pi24 n2073 n2317 n2323 n2321 -1-01 1 --101 1 -.names n3681 n1866 n2326 -1- 1 --1 1 -.names n2754 n1866 n2325 -1- 1 --1 1 -.names n2326 n2321 Pi24 n2325 n2324 -111- 1 -11-1 1 -.names Pi22 Pi21 n2328 -1- 1 --0 1 -.names n2326 n2323 n194 n2328 n2327 -111- 1 -11-1 1 -.names n3679 n2328 n2331 -1- 1 --1 1 -.names Pi27 n2333 n3678 n2332 -01- 1 --11 1 -.names Pi27 n3680 n3681 n2330 -01- 1 --11 1 -.names n2331 n2332 n2330 n1866 n2329 -111- 1 -11-1 1 -.names n2069 n178 n2333 -11 1 -.names n2456 n3798 n3914 n3916 n2335 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n2324 n2335 Ni13 n2334 -11- 1 --10 1 -.names n18 n196 n2156 n2158 n2336 -111- 1 --111 1 -.names n18 n196 n2176 n2178 n2337 -111- 1 --111 1 -.names n18 n196 n2259 n2261 n2338 -111- 1 --111 1 -.names n18 n196 n2265 n2267 n2339 -111- 1 --111 1 -.names n18 n196 n2247 n2249 n2340 -111- 1 --111 1 -.names n18 n196 n2252 n2254 n2341 -111- 1 --111 1 -.names n18 n196 n2145 n2147 n2342 -111- 1 --111 1 -.names n18 n196 n2151 n2153 n2343 -111- 1 --111 1 -.names n18 n196 n2285 n2287 n2344 -111- 1 --111 1 -.names n18 n196 n2291 n2293 n2345 -111- 1 --111 1 -.names n18 n196 n2274 n2276 n2346 -111- 1 --111 1 -.names n18 n196 n2279 n2281 n2347 -111- 1 --111 1 -.names n18 n196 n2165 n2167 n2348 -111- 1 --111 1 -.names n18 n196 n2171 n2173 n2349 -111- 1 --111 1 -.names n2156 n2159 n2351 -11 1 -.names n2176 n2179 n2352 -11 1 -.names n2351 n996 n2352 n998 n2350 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n3579 n4523 n4524 n2353 -00- 1 -0-0 1 -.names n1884 n4525 n4526 n2356 -00- 1 -0-0 1 -.names n2321 n3576 n4532 n4531 n2360 -11-- 1 -1-11 1 -.names n4536 n3582 n4530 n4529 n2361 -11-- 1 -1-11 1 -.names n4533 n4534 Pi24 n2350 n2362 -111- 1 -11-1 1 -.names n2360 n2361 n2362 n2359 -111 1 -.names n18 n196 n2109 n2111 n2363 -111- 1 --111 1 -.names n18 n196 n2135 n2137 n2364 -111- 1 --111 1 -.names n18 n196 n2200 n2202 n2365 -111- 1 --111 1 -.names n18 n196 n2208 n2210 n2366 -111- 1 --111 1 -.names n18 n196 n2185 n2187 n2367 -111- 1 --111 1 -.names n18 n196 n2191 n2193 n2368 -111- 1 --111 1 -.names n18 n196 n2088 n2091 n2369 -111- 1 --111 1 -.names n18 n196 n2101 n2103 n2370 -111- 1 --111 1 -.names n18 n196 n2230 n2232 n2371 -111- 1 --111 1 -.names n18 n196 n2238 n2240 n2372 -111- 1 --111 1 -.names n18 n196 n2217 n2219 n2373 -111- 1 --111 1 -.names n18 n196 n2222 n2224 n2374 -111- 1 --111 1 -.names n18 n196 n2120 n2122 n2375 -111- 1 --111 1 -.names n18 n196 n2128 n2130 n2376 -111- 1 --111 1 -.names n2109 n2112 n2378 -11 1 -.names n2135 n2138 n2379 -11 1 -.names n2378 n996 n2379 n998 n2377 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n3579 n4503 n4504 n2380 -00- 1 -0-0 1 -.names n1884 n4505 n4506 n2383 -00- 1 -0-0 1 -.names n3831 n4516 n4519 n4520 n2386 -00-- 1 -0-0- 1 -0--0 1 -.names n934 n1069 n2324 n2386 n2391 ---10 1 -11-0 1 -.names n2334 n3499 n3805 n3918 n2392 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n2391 n2392 n2359 n1993 n2390 -111- 1 -11-1 1 -.names Pi21 n160 n194 n2071 n2393 -11-0 1 -1-00 1 -.names n160 n2073 n2323 n2393 n2394 -0-10 1 --110 1 -.names n160 n2326 n2325 n2394 n2396 -01-1 1 --111 1 -.names Pi24 n2328 n3677 n4476 n2397 --0-0 1 -100- 1 -.names Pi24 n1866 n2305 n4477 n2401 --0-0 1 -100- 1 -.names Pi24 Pi21 n3674 n4478 n2404 --0-0 1 -100- 1 -.names n1069 n1068 n2456 n2407 -11- 1 -1-0 1 -.names n4491 n4371 n3823 n2412 -11- 1 -1-1 1 -.names n2238 n2241 n2410 -11 1 -.names n160 n3729 n2411 -0- 1 --1 1 -.names n2394 n2412 n2410 n2411 n2409 -111- 1 -11-1 1 -.names n4490 n2244 n3823 n2415 -11- 1 -1-1 1 -.names n2222 n2225 n2414 -11 1 -.names n2394 n2415 n2414 n2411 n2413 -111- 1 -11-1 1 -.names n4489 n4365 n3823 n2417 -11- 1 -1-1 1 -.names n2394 n2417 n2141 n2411 n2416 -111- 1 -11-1 1 -.names n2416 n3735 n2413 n3738 n2419 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n4492 n2379 n3821 n2420 -11- 1 -1-1 1 -.names n2419 n2420 n2409 n796 n2418 -111- 1 -11-1 1 -.names n4482 n4368 n3823 n2423 -11- 1 -1-1 1 -.names n2208 n2211 n2422 -11 1 -.names n2394 n2423 n2422 n2411 n2421 -111- 1 -11-1 1 -.names n4481 n2214 n3823 n2426 -11- 1 -1-1 1 -.names n2191 n2194 n2425 -11 1 -.names n2394 n2426 n2425 n2411 n2424 -111- 1 -11-1 1 -.names n4480 n4363 n3823 n2428 -11- 1 -1-1 1 -.names n2394 n2428 n2115 n2411 n2427 -111- 1 -11-1 1 -.names n2427 n3735 n2424 n3738 n2430 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n4483 n2378 n3821 n2431 -11- 1 -1-1 1 -.names n2430 n2431 n2421 n796 n2429 -111- 1 -11-1 1 -.names n4495 n4381 n3823 n2434 -11- 1 -1-1 1 -.names n2291 n2294 n2433 -11 1 -.names n2394 n2434 n2433 n2411 n2432 -111- 1 -11-1 1 -.names n4494 n2297 n3823 n2437 -11- 1 -1-1 1 -.names n2279 n2282 n2436 -11 1 -.names n2394 n2437 n2436 n2411 n2435 -111- 1 -11-1 1 -.names n4493 n4375 n3823 n2439 -11- 1 -1-1 1 -.names n2394 n2439 n2182 n2411 n2438 -111- 1 -11-1 1 -.names n2438 n3735 n2435 n3738 n2441 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n4496 n4484 n2352 n3821 n2442 -111- 1 -11-1 1 -.names n2441 n2442 n2432 n796 n2440 -111- 1 -11-1 1 -.names n4487 n4378 n3823 n2445 -11- 1 -1-1 1 -.names n2265 n2268 n2444 -11 1 -.names n2394 n2445 n2444 n2411 n2443 -111- 1 -11-1 1 -.names n4486 n2271 n3823 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1 -.names Pi26 Ni32 n2303 n3674 -0-1 1 --01 1 -.names n176 n195 n3675 -11 1 -.names Pi27 n3667 n3675 n3676 -0-1 1 --11 1 -.names Pi26 n3667 n3676 n3677 -0-1 1 --11 1 -.names n2069 n196 n3678 -11 1 -.names Pi27 n194 n3670 n3679 -0-1 1 --11 1 -.names n178 n2074 n3680 -11 1 -.names n2074 n196 n3681 -11 1 -.names n3676 Pi26 n3667 n3682 -11- 1 -1-1 1 -.names n3859 n2950 n3685 -11 1 -.names Pi26 n177 n3592 n3685 n3684 -01-1 1 --111 1 -.names n2055 n3843 n3687 -11 1 -.names Pi23 n3685 n3684 n3687 n3686 -1-0- 1 --00- 1 ---01 1 -.names n3862 n2953 n3691 -11 1 -.names Pi27 n177 n3592 n3691 n3690 -01-1 1 --111 1 -.names Pi24 n3687 n3691 n3690 n3692 -1--0 1 --1-0 1 ---00 1 -.names Pi22 n171 n1063 n2955 n3695 -01-- 1 -0-00 1 -.names Pi21 n171 n1063 n2947 n3696 -01-- 1 -0-01 1 -.names n2967 Ni41 n3697 -1- 1 --0 1 -.names Ni47 n2066 n3486 Ni4 n3698 -0-0- 1 --000 1 -.names Pi26 n3489 n3524 n3699 -0-1 1 --11 1 -.names n3699 n2312 n3498 n3499 n3701 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names Pi24 n3502 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--0 1 -.names Pi21 Pi20 n298 n487 n3736 --10- 1 -01-0 1 -.names Pi21 Pi20 n298 n462 n3737 --00- 1 -00-0 1 -.names Pi17 Pi19 n3738 -1- 1 --1 1 -.names Ni32 n2199 n3739 -0- 1 --1 1 -.names Ni32 n2199 n3740 -1- 1 --1 1 -.names Pi16 Pi15 n3742 -1- 1 --1 1 -.names Pi21 Pi20 n298 n408 n3747 --10- 1 -01-0 1 -.names Pi21 Pi20 n298 n395 n3748 --00- 1 -00-0 1 -.names n295 n420 n3747 n3748 n3746 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names n45 Ni45 n3749 -10 1 -.names Pi21 Pi20 n298 n678 n3750 --10- 1 -01-0 1 -.names Pi21 Pi20 n298 n664 n3751 --00- 1 -00-0 1 -.names Pi16 Pi15 n3754 -1- 1 --0 1 -.names Pi21 Pi20 n298 n349 n3757 --10- 1 -01-0 1 -.names Pi21 Pi20 n298 n325 n3758 --00- 1 -00-0 1 -.names n295 n381 n3757 n3758 n3756 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names Pi21 Pi20 n298 n588 n3760 --10- 1 -01-0 1 -.names Pi21 Pi20 n298 n567 n3761 --00- 1 -00-0 1 -.names n295 n656 n3760 n3761 n3759 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names Pi16 Pi15 n3763 -0- 1 --1 1 -.names Pi21 Pi20 n298 n435 n3767 --10- 1 -01-0 1 -.names Pi21 Pi20 n298 n428 n3768 --00- 1 -00-0 1 -.names n295 n447 n3767 n3768 n3766 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names Pi21 Pi20 n298 n724 n3770 --10- 1 -01-0 1 -.names Pi21 Pi20 n298 n714 n3771 --00- 1 -00-0 1 -.names n295 n752 n3770 n3771 n3769 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names Pi16 Pi15 n3774 -0- 1 --0 1 -.names Ni10 n3113 n3775 -1- 1 --0 1 -.names Pi19 n3727 n3776 -0- 1 --1 1 -.names Pi16 n3735 n3777 -1- 1 --1 1 -.names Pi16 n796 n3778 -1- 1 --1 1 -.names Ni4 Ni5 Ni6 n3779 -1-- 1 --1- 1 ---1 1 -.names Ni11 Ni10 n3783 -1- 1 --1 1 -.names n931 Ni11 n3784 -11 1 -.names n3716 n3603 n3785 -1- 1 --1 1 -.names n3603 n3716 n3786 -0- 1 --1 1 -.names n3727 n3603 n3787 -1- 1 --1 1 -.names n3729 n3603 n3788 -1- 1 --1 1 -.names n3603 n3729 n3789 -0- 1 --1 1 -.names Pi27 n996 n3790 -1- 1 --1 1 -.names Pi27 n998 n3791 -1- 1 --1 1 -.names Pi27 n996 n3792 -0- 1 --1 1 -.names Pi27 n998 n3793 -0- 1 --1 1 -.names Pi27 n3727 n3794 -1- 1 --1 1 -.names Pi27 n3729 n3795 -1- 1 --1 1 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n3754 n4650 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n3358 n3763 n3374 n3774 n4652 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n3798 n1068 n4785 n4786 n4654 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n168 Ni10 n1654 n3492 n4657 -1--- 1 --0-- 1 ---1- 1 ----1 1 -.names n3492 n3613 n3614 n4658 -1-- 1 --1- 1 ---1 1 -.names Ni31 Ni30 Ni5 Ni4 n4659 -10-- 1 -1-0- 1 -1--1 1 -.names Pi15 n773 n781 n4665 -11- 1 -0-1 1 --11 1 -.names Pi17 n758 n763 n4006 n4666 -01-- 1 -0-1- 1 -0--0 1 -.names Pi17 n4008 n4009 n4666 n4667 -0--0 1 --110 1 -.names n3113 n4665 n4667 n4669 -11- 1 -0-1 1 --11 1 -.names n3775 n4027 n4028 n4670 -011 1 -.names n1654 n3775 n4667 n4670 n4671 -0--1 1 -011- 1 -.names n1654 Ni7 n4669 n4671 n4672 --0-1 1 -101- 1 -.names n3540 Ni7 n4669 n4672 n4673 -0--1 1 -011- 1 -.names n4186 n3650 Ni14 n4675 -111 1 -.names Ni14 n4100 n4101 n4676 -011 1 -.names n4108 n4107 Ni14 n4677 -111 1 -.names n848 n1053 n1505 n1508 n1511 n1514 n1517 n4068 n4678 -0------- 1 --0------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------0 1 -.names n848 n994 n1482 n1487 n1490 n1494 n1498 n4082 n4682 -0------- 1 --0------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------0 1 -.names n1332 n3792 n4686 -1- 1 --1 1 -.names Pi15 n4139 n4142 n4145 n4146 n4686 n4685 -011111 1 -.names n1402 n3792 n4688 -1- 1 --1 1 -.names n4159 n4688 n4162 n4166 n4165 Pi15 n4687 -111111 1 -.names Pi17 n4051 n4053 n4689 -10- 1 -1-0 1 -.names Pi17 n848 n4084 n4085 n4691 -0111 1 -.names n4088 n848 n4087 Pi17 n4692 -1111 1 -.names n4174 Ni10 Ni11 n1414 n4693 -111- 1 -11-1 1 -.names Pi17 n4089 n4090 n4696 -011 1 -.names n2010 n3576 n4699 -1- 1 --1 1 -.names Pi15 n1995 n4236 n4238 n4239 n4699 n4698 -011111 1 -.names n18 Ni34 n4701 -1- 1 --0 1 -.names Ni34 n18 n1063 n4702 -1-- 1 --1- 1 ---1 1 -.names Pi17 n4255 n4256 n4703 -011 1 -.names n4258 n4257 Pi17 n4704 -111 1 -.names Pi20 n4281 n4285 n4705 -10- 1 -1-0 1 -.names Pi20 n4269 n4272 n4705 n4706 -1--0 1 --110 1 -.names Pi20 n4311 n4315 n4708 -10- 1 -1-0 1 -.names Pi20 n4299 n4302 n4708 n4709 -1--0 1 --110 1 -.names Pi15 n4287 n4706 n4711 -011 1 -.names n4317 n4709 Pi15 n4712 -111 1 -.names n4703 n4704 n3113 Ni10 n4713 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names Pi17 n4326 n4328 n4714 -00- 1 -0-0 1 -.names n4332 n2024 n2031 n4716 -111 1 -.names Pi23 n2026 n2031 n3660 n4717 ---01 1 -010- 1 -.names n4333 n2043 n2031 n4718 -111 1 -.names Pi24 n2031 n2046 n3663 n4719 --0-1 1 -001- 1 -.names Ni33 n275 n2031 n2046 n4720 -1-01 1 --101 1 -.names Ni44 n3572 Ni42 Ni39 n4722 -00-0 1 -0-10 1 -.names Ni44 n320 Ni39 n4722 n4724 -0--0 1 --0-0 1 ---00 1 -.names Pi21 n3674 n4730 -1- 1 --1 1 -.names Pi26 n2327 n2329 n4733 -10- 1 -0-0 1 --00 1 -.names Pi26 Pi21 Ni32 n2303 n4735 --0-0 1 -001- 1 -.names Pi26 n2327 n2329 n4737 -00- 1 -1-0 1 --00 1 -.names Ni14 n4405 n4406 n4738 -011 1 -.names n2070 n2377 n2782 n2785 n2788 n2791 n2794 n4372 n4740 -0------- 1 --0------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------0 1 -.names n2070 n2350 n2764 n2767 n2770 n2773 n2776 n4382 n4743 -0------- 1 --0------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------0 1 -.names n2632 n3792 n4747 -1- 1 --1 1 -.names Pi15 n4440 n4443 n4446 n4447 n4747 n4746 -011111 1 -.names n2688 n3792 n4749 -1- 1 --1 1 -.names n4460 n4749 n4463 n4467 n4466 Pi15 n4748 -111111 1 -.names Pi17 n4359 n4361 n4750 -10- 1 -1-0 1 -.names Pi17 n2070 n4384 n4385 n4752 -0111 1 -.names n4388 n2070 n4387 Pi17 n4753 -1111 1 -.names n4475 Ni10 Ni11 n2699 n4754 -111- 1 -11-1 1 -.names n2397 n2401 n2404 n4755 -1-- 1 --1- 1 ---1 1 -.names Pi17 n4394 n4395 n4756 -011 1 -.names Pi20 n2937 Ni39 n3858 n4759 -01-1 1 -0-01 1 -.names n3858 Pi20 Ni39 n2937 n4760 -111- 1 -11-1 1 -.names n2031 Ni40 n4761 -0- 1 --0 1 -.names n2031 n3686 n3925 n4763 -01- 1 -1-0 1 --10 1 -.names n2031 Ni41 n4764 -0- 1 --0 1 -.names n2031 n3692 n3931 n4766 -01- 1 -1-0 1 --10 1 -.names Pi21 n171 n1063 n2946 n4767 -01-- 1 -0-01 1 -.names Pi20 n3463 n3465 n4629 n4769 -11-- 1 -1-1- 1 -1--0 1 -.names Pi20 n4623 n4625 n4769 n4770 -1--0 1 --110 1 -.names Pi20 n3441 n3444 n4645 n4772 -11-- 1 -1-1- 1 -1--0 1 -.names Pi20 n4639 n4641 n4772 n4773 -1--0 1 --110 1 -.names Pi15 n4631 n4770 n4775 -011 1 -.names n4647 n4773 Pi15 n4776 -111 1 -.names Pi17 n4648 n4649 n4777 -011 1 -.names Ni10 n4775 n4776 n4779 -01- 1 -0-1 1 -.names Pi15 n3271 n3273 n4573 n4575 n4577 n4780 -000111 1 -.names Pi17 n4588 n4589 n4783 -011 1 -.names n4591 n4590 Pi17 n4784 -111 1 -.names Pi15 Ni10 n3937 n4780 n4785 --0-1 1 -101- 1 -.names Ni10 n4783 n4784 n4786 -11- 1 -1-1 1 -.names Pi15 n3335 n3337 n4598 n4600 n4602 n4787 -000111 1 -.names Pi17 n4612 n4613 n4790 -011 1 -.names n4615 n4614 Pi17 n4791 -111 1 -.names Pi15 Ni10 n3942 n4787 n4792 --0-1 1 -101- 1 -.names Ni14 Ni12 n4836 n4797 -0-- 1 --0- 1 ---1 1 -.names Ni6 Ni5 n3527 Ni4 n4798 -0--0 1 --0-0 1 ---00 1 -.names Ni31 Ni6 Ni5 n4799 -0-- 1 --0- 1 ---0 1 -.names n4799 Ni4 n2066 n3874 n4800 -111- 1 -11-1 1 -.names Ni4 Ni3 n4799 n4800 n4801 --1-1 1 -010- 1 -.names Ni2 Ni3 n3952 n4801 n4803 -0--1 1 -001- 1 -.names Ni31 Ni6 Ni2 Ni3 n4805 --11- 1 -01-1 1 -.names Ni12 n3540 n3559 n3568 n4808 -11-- 1 -1-01 1 -.names Pi20 n184 n3585 n3595 n4810 -11-- 1 -1-1- 1 -1--1 1 -.names Ni44 n3573 Ni42 Ni39 n4811 -0-10 1 --110 1 -.names Pi27 n3880 n4813 -1- 1 --1 1 -.names Pi27 Pi26 n3880 n4814 -0-- 1 --1- 1 ---1 1 -.names Pi24 n3881 n4815 -1- 1 --1 1 -.names Pi24 Pi23 n3881 n4816 -0-- 1 --1- 1 ---1 1 -.names n2065 Ni4 n3863 n4817 -10- 1 --01 1 -.names Ni4 Ni33 n3874 n4818 -11- 1 -1-1 1 -.names Ni33 n834 n4819 -10 1 -.names Ni33 n834 n4820 -00 1 -.names n63 n2086 n4822 -1- 1 --1 1 -.names n38 Ni41 n4823 -0- 1 --1 1 -.names n42 Ni41 n4825 -0- 1 --1 1 -.names Ni33 n2966 n4827 -0- 1 --1 1 -.names n1062 n953 n4832 -11 1 -.names n1071 n1075 n1079 n4223 n4833 -1--- 1 --1-- 1 ---1- 1 ----0 1 -.names n4759 n4760 n3879 n4835 -1-- 1 --1- 1 ---1 1 -.names n3492 Pi27 n4836 -11 1 -.end diff --git a/fpga_flow/benchmarks/Blif/MCNC_big20/des.blif b/fpga_flow/benchmarks/Blif/MCNC_big20/des.blif deleted file mode 100644 index 2e5b6489d..000000000 --- a/fpga_flow/benchmarks/Blif/MCNC_big20/des.blif +++ /dev/null @@ -1,5078 +0,0 @@ -.model TOP -.inputs Preset_0_ Poutreg_63_ Poutreg_62_ Poutreg_61_ Poutreg_60_ Poutreg_59_ \ -Poutreg_58_ Poutreg_57_ Poutreg_56_ Poutreg_55_ Poutreg_54_ Poutreg_53_ \ -Poutreg_52_ Poutreg_51_ Poutreg_50_ Poutreg_49_ Poutreg_48_ Poutreg_47_ \ -Poutreg_46_ Poutreg_45_ Poutreg_44_ Poutreg_43_ Poutreg_42_ Poutreg_41_ \ -Poutreg_40_ Poutreg_39_ Poutreg_38_ Poutreg_37_ Poutreg_36_ Poutreg_35_ \ -Poutreg_34_ Poutreg_33_ Poutreg_32_ Poutreg_31_ Poutreg_30_ Poutreg_29_ \ -Poutreg_28_ Poutreg_27_ Poutreg_26_ Poutreg_25_ Poutreg_24_ Poutreg_23_ \ -Poutreg_22_ Poutreg_21_ Poutreg_20_ Poutreg_19_ Poutreg_18_ Poutreg_17_ \ -Poutreg_16_ Poutreg_15_ Poutreg_14_ Poutreg_13_ Poutreg_12_ Poutreg_11_ \ -Poutreg_10_ Poutreg_9_ Poutreg_8_ Poutreg_7_ Poutreg_6_ Poutreg_5_ Poutreg_4_ \ -Poutreg_3_ Poutreg_2_ Poutreg_1_ Poutreg_0_ Pload_key_0_ Pinreg_55_ Pinreg_54_ \ -Pinreg_53_ Pinreg_52_ Pinreg_51_ Pinreg_50_ Pinreg_49_ Pinreg_48_ Pinreg_47_ \ -Pinreg_46_ Pinreg_45_ Pinreg_44_ Pinreg_43_ Pinreg_42_ Pinreg_41_ Pinreg_40_ \ -Pinreg_39_ Pinreg_38_ Pinreg_37_ Pinreg_36_ Pinreg_35_ Pinreg_34_ Pinreg_33_ \ -Pinreg_32_ Pinreg_31_ Pinreg_30_ Pinreg_29_ Pinreg_28_ Pinreg_27_ Pinreg_26_ \ -Pinreg_25_ Pinreg_24_ Pinreg_23_ Pinreg_22_ Pinreg_21_ Pinreg_20_ Pinreg_19_ \ -Pinreg_18_ Pinreg_17_ Pinreg_16_ Pinreg_15_ Pinreg_14_ Pinreg_13_ Pinreg_12_ \ -Pinreg_11_ Pinreg_10_ Pinreg_9_ Pinreg_8_ Pinreg_7_ Pinreg_6_ Pinreg_5_ \ -Pinreg_4_ Pinreg_3_ Pinreg_2_ Pinreg_1_ Pinreg_0_ Pencrypt_mode_0_ Pencrypt_0_ \ -Pdata_in_7_ Pdata_in_6_ Pdata_in_5_ Pdata_in_4_ Pdata_in_3_ Pdata_in_2_ \ -Pdata_in_1_ Pdata_in_0_ Pdata_63_ Pdata_62_ Pdata_61_ Pdata_60_ Pdata_59_ \ -Pdata_58_ Pdata_57_ Pdata_56_ Pdata_55_ Pdata_54_ Pdata_53_ Pdata_52_ \ -Pdata_51_ Pdata_50_ Pdata_49_ Pdata_48_ Pdata_47_ Pdata_46_ Pdata_45_ \ -Pdata_44_ Pdata_43_ Pdata_42_ Pdata_41_ Pdata_40_ Pdata_39_ Pdata_38_ \ -Pdata_37_ Pdata_36_ Pdata_35_ Pdata_34_ Pdata_33_ Pdata_32_ Pdata_31_ \ -Pdata_30_ Pdata_29_ Pdata_28_ Pdata_27_ Pdata_26_ Pdata_25_ Pdata_24_ \ -Pdata_23_ Pdata_22_ Pdata_21_ Pdata_20_ Pdata_19_ Pdata_18_ Pdata_17_ \ -Pdata_16_ Pdata_15_ Pdata_14_ Pdata_13_ Pdata_12_ Pdata_11_ Pdata_10_ Pdata_9_ \ -Pdata_8_ Pdata_7_ Pdata_6_ Pdata_5_ Pdata_4_ Pdata_3_ Pdata_2_ Pdata_1_ \ -Pdata_0_ Pcount_3_ Pcount_2_ Pcount_1_ Pcount_0_ PD_27_ PD_26_ PD_25_ PD_24_ \ -PD_23_ PD_22_ PD_21_ PD_20_ PD_19_ PD_18_ PD_17_ PD_16_ PD_15_ PD_14_ PD_13_ \ -PD_12_ PD_11_ PD_10_ PD_9_ PD_8_ PD_7_ PD_6_ PD_5_ PD_4_ PD_3_ PD_2_ PD_1_ \ -PD_0_ PC_27_ PC_26_ PC_25_ PC_24_ PC_23_ PC_22_ PC_21_ PC_20_ PC_19_ PC_18_ \ -PC_17_ PC_16_ PC_15_ PC_14_ PC_13_ PC_12_ PC_11_ PC_10_ PC_9_ PC_8_ PC_7_ \ -PC_6_ PC_5_ PC_4_ PC_3_ PC_2_ PC_1_ PC_0_ -.outputs Poutreg_new_63_ Poutreg_new_62_ Poutreg_new_61_ Poutreg_new_60_ \ -Poutreg_new_59_ Poutreg_new_58_ Poutreg_new_57_ Poutreg_new_56_ \ -Poutreg_new_55_ Poutreg_new_54_ Poutreg_new_53_ Poutreg_new_52_ \ -Poutreg_new_51_ Poutreg_new_50_ Poutreg_new_49_ Poutreg_new_48_ \ -Poutreg_new_47_ Poutreg_new_46_ Poutreg_new_45_ Poutreg_new_44_ \ -Poutreg_new_43_ Poutreg_new_42_ Poutreg_new_41_ Poutreg_new_40_ \ -Poutreg_new_39_ Poutreg_new_38_ Poutreg_new_37_ Poutreg_new_36_ \ -Poutreg_new_35_ Poutreg_new_34_ Poutreg_new_33_ Poutreg_new_32_ \ -Poutreg_new_31_ Poutreg_new_30_ Poutreg_new_29_ Poutreg_new_28_ \ -Poutreg_new_27_ Poutreg_new_26_ Poutreg_new_25_ Poutreg_new_24_ \ -Poutreg_new_23_ Poutreg_new_22_ Poutreg_new_21_ Poutreg_new_20_ \ -Poutreg_new_19_ Poutreg_new_18_ Poutreg_new_17_ Poutreg_new_16_ \ -Poutreg_new_15_ Poutreg_new_14_ Poutreg_new_13_ Poutreg_new_12_ \ -Poutreg_new_11_ Poutreg_new_10_ Poutreg_new_9_ Poutreg_new_8_ Poutreg_new_7_ \ -Poutreg_new_6_ Poutreg_new_5_ Poutreg_new_4_ Poutreg_new_3_ Poutreg_new_2_ \ -Poutreg_new_1_ Poutreg_new_0_ Pinreg_new_55_ Pinreg_new_54_ Pinreg_new_53_ \ -Pinreg_new_52_ Pinreg_new_51_ Pinreg_new_50_ Pinreg_new_49_ Pinreg_new_48_ \ -Pinreg_new_47_ Pinreg_new_46_ Pinreg_new_45_ Pinreg_new_44_ Pinreg_new_43_ \ -Pinreg_new_42_ Pinreg_new_41_ Pinreg_new_40_ Pinreg_new_39_ Pinreg_new_38_ \ -Pinreg_new_37_ Pinreg_new_36_ Pinreg_new_35_ Pinreg_new_34_ Pinreg_new_33_ \ -Pinreg_new_32_ Pinreg_new_31_ Pinreg_new_30_ Pinreg_new_29_ Pinreg_new_28_ \ -Pinreg_new_27_ Pinreg_new_26_ Pinreg_new_25_ Pinreg_new_24_ Pinreg_new_23_ \ -Pinreg_new_22_ Pinreg_new_21_ Pinreg_new_20_ Pinreg_new_19_ Pinreg_new_18_ \ -Pinreg_new_17_ Pinreg_new_16_ Pinreg_new_15_ Pinreg_new_14_ Pinreg_new_13_ \ -Pinreg_new_12_ Pinreg_new_11_ Pinreg_new_10_ Pinreg_new_9_ Pinreg_new_8_ \ -Pinreg_new_7_ Pinreg_new_6_ Pinreg_new_5_ Pinreg_new_4_ Pinreg_new_3_ \ -Pinreg_new_2_ Pinreg_new_1_ Pinreg_new_0_ Pencrypt_mode_new_0_ Pdata_new_63_ \ -Pdata_new_62_ Pdata_new_61_ Pdata_new_60_ Pdata_new_59_ Pdata_new_58_ \ -Pdata_new_57_ Pdata_new_56_ Pdata_new_55_ Pdata_new_54_ Pdata_new_53_ \ -Pdata_new_52_ Pdata_new_51_ Pdata_new_50_ Pdata_new_49_ Pdata_new_48_ \ -Pdata_new_47_ Pdata_new_46_ Pdata_new_45_ Pdata_new_44_ Pdata_new_43_ \ -Pdata_new_42_ Pdata_new_41_ Pdata_new_40_ Pdata_new_39_ Pdata_new_38_ \ -Pdata_new_37_ Pdata_new_36_ Pdata_new_35_ Pdata_new_34_ Pdata_new_33_ \ -Pdata_new_32_ Pdata_new_31_ Pdata_new_30_ Pdata_new_29_ Pdata_new_28_ \ -Pdata_new_27_ Pdata_new_26_ Pdata_new_25_ Pdata_new_24_ Pdata_new_23_ \ -Pdata_new_22_ Pdata_new_21_ Pdata_new_20_ Pdata_new_19_ Pdata_new_18_ \ -Pdata_new_17_ Pdata_new_16_ Pdata_new_15_ Pdata_new_14_ Pdata_new_13_ \ -Pdata_new_12_ Pdata_new_11_ Pdata_new_10_ Pdata_new_9_ Pdata_new_8_ \ -Pdata_new_7_ Pdata_new_6_ Pdata_new_5_ Pdata_new_4_ Pdata_new_3_ Pdata_new_2_ \ -Pdata_new_1_ Pdata_new_0_ Pcount_new_3_ Pcount_new_2_ Pcount_new_1_ \ -Pcount_new_0_ PD_new_27_ PD_new_26_ PD_new_25_ PD_new_24_ PD_new_23_ \ -PD_new_22_ PD_new_21_ PD_new_20_ PD_new_19_ PD_new_18_ PD_new_17_ PD_new_16_ \ -PD_new_15_ PD_new_14_ PD_new_13_ PD_new_12_ PD_new_11_ PD_new_10_ PD_new_9_ \ -PD_new_8_ PD_new_7_ PD_new_6_ PD_new_5_ PD_new_4_ PD_new_3_ PD_new_2_ \ -PD_new_1_ PD_new_0_ PC_new_27_ PC_new_26_ PC_new_25_ PC_new_24_ PC_new_23_ \ -PC_new_22_ PC_new_21_ PC_new_20_ PC_new_19_ PC_new_18_ PC_new_17_ PC_new_16_ \ -PC_new_15_ PC_new_14_ PC_new_13_ PC_new_12_ PC_new_11_ PC_new_10_ PC_new_9_ \ -PC_new_8_ PC_new_7_ PC_new_6_ PC_new_5_ PC_new_4_ PC_new_3_ PC_new_2_ \ -PC_new_1_ PC_new_0_ -.names n2 Poutreg_new_63_ -0 1 -.names n105 Poutreg_new_62_ -0 1 -.names n3 Poutreg_new_61_ -0 1 -.names n101 Poutreg_new_60_ -0 1 -.names n4 Poutreg_new_59_ -0 1 -.names n97 Poutreg_new_58_ -0 1 -.names n5 Poutreg_new_57_ -0 1 -.names n91 Poutreg_new_56_ -0 1 -.names n6 Poutreg_new_55_ -0 1 -.names n124 Poutreg_new_54_ -0 1 -.names n7 Poutreg_new_53_ -0 1 -.names n94 Poutreg_new_52_ -0 1 -.names n8 Poutreg_new_51_ -0 1 -.names n123 Poutreg_new_50_ -0 1 -.names n9 Poutreg_new_49_ -0 1 -.names n122 Poutreg_new_48_ -0 1 -.names n10 Poutreg_new_47_ -0 1 -.names n121 Poutreg_new_46_ -0 1 -.names n11 Poutreg_new_45_ -0 1 -.names n120 Poutreg_new_44_ -0 1 -.names n12 Poutreg_new_43_ -0 1 -.names n119 Poutreg_new_42_ -0 1 -.names n13 Poutreg_new_41_ -0 1 -.names n118 Poutreg_new_40_ -0 1 -.names n14 Poutreg_new_39_ -0 1 -.names n117 Poutreg_new_38_ -0 1 -.names n15 Poutreg_new_37_ -0 1 -.names n116 Poutreg_new_36_ -0 1 -.names n16 Poutreg_new_35_ -0 1 -.names n115 Poutreg_new_34_ -0 1 -.names n17 Poutreg_new_33_ -0 1 -.names n114 Poutreg_new_32_ -0 1 -.names n18 Poutreg_new_31_ -0 1 -.names n113 Poutreg_new_30_ -0 1 -.names n19 Poutreg_new_29_ -0 1 -.names n112 Poutreg_new_28_ -0 1 -.names n20 Poutreg_new_27_ -0 1 -.names n111 Poutreg_new_26_ -0 1 -.names n21 Poutreg_new_25_ -0 1 -.names n110 Poutreg_new_24_ -0 1 -.names n22 Poutreg_new_23_ -0 1 -.names n109 Poutreg_new_22_ -0 1 -.names n23 Poutreg_new_21_ -0 1 -.names n108 Poutreg_new_20_ -0 1 -.names n24 Poutreg_new_19_ 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-011- 1 -01-0 1 -.names n201 n914 n1187 n217 -1-- 1 --1- 1 ---0 1 -.names n207 n795 n1185 n1189 n218 -01-- 1 -0-0- 1 --1-1 1 ---01 1 -.names n201 n230 n216 -0- 1 --0 1 -.names n217 n218 n216 n559 n215 -111- 1 -11-0 1 -.names Pdata_50_ PD_8_ n220 -01 1 -10 1 -.names n914 n1156 n222 -01 1 -10 1 -.names n220 n222 n1186 n219 -1-- 1 --1- 1 ---0 1 -.names n201 n914 n224 -0- 1 --1 1 -.names n224 n1186 n223 -1- 1 --0 1 -.names n915 n1155 n228 -11 1 -.names n914 n1185 n227 -01 1 -.names n1185 n1184 n226 -1- 1 --1 1 -.names n228 n227 n201 n226 n225 -11-- 1 -1-11 1 -.names n911 n914 n230 -10 1 -.names n559 n209 n231 -1- 1 --1 1 -.names n201 n219 n230 n231 n229 -00-- 1 -0-11 1 -.names Pdata_24_ n1669 n234 -01 1 -10 1 -.names n266 n275 n243 -10 1 -.names n262 n269 n835 n240 -000 1 -.names n243 n240 n254 n1602 n239 -11-0 1 -1-00 1 -.names n239 n262 n272 n1372 n244 -00-- 1 -0-0- 1 -0--0 1 -.names n294 n297 n835 n1371 n252 -0-0- 1 --10- 1 -0--0 1 --1-0 1 -.names n244 n252 n281 n1199 n249 -110- 1 -11-0 1 -.names Pdata_36_ PC_4_ n254 -01 1 -10 1 -.names n254 n281 n835 n1200 n253 -10-- 1 -1-0- 1 --0-0 1 ---00 1 -.names n266 n292 n1198 n259 -0-- 1 --0- 1 ---1 1 -.names n294 n1199 n260 -0- 1 --0 1 -.names n253 n259 n260 n295 n257 -111- 1 --110 1 -.names n254 n262 n263 -1- 1 --0 1 -.names Pdata_35_ PC_0_ n262 -01 1 -10 1 -.names n254 n263 n262 n261 -01- 1 --11 1 -.names Pdata_63_ PC_13_ n266 -01 1 -10 1 -.names n243 n266 n275 n264 -01- 1 -0-0 1 -.names Pdata_32_ PC_16_ n269 -01 1 -10 1 -.names n254 n269 n268 -01 1 -.names n269 n275 n272 -00 1 -.names n254 n262 n266 n272 n270 -00-1 1 -0-01 1 -.names Pdata_34_ PC_23_ n275 -01 1 -10 1 -.names n262 n269 n274 -01 1 -.names n266 n268 n275 n274 n273 -011- 1 -0-11 1 -.names n261 n272 n275 n274 n276 -1-0- 1 --00- 1 -1--0 1 --0-0 1 -.names n835 n294 n279 -11 1 -.names n262 n272 n279 n278 -011 1 -.names n254 n266 n281 -00 1 -.names n240 n275 n281 n280 -101 1 -.names n266 n276 n835 n283 -0-- 1 --1- 1 ---0 1 -.names n281 n292 n1201 n1202 n285 -00-- 1 -0-0- 1 --0-1 1 ---01 1 -.names n249 n257 n283 n285 n1203 n1599 n282 -111100 1 -.names n282 Pdata_16_ n287 -01 1 -10 1 -.names n262 n254 n292 -11 1 -.names n243 n269 n292 n291 -111 1 -.names n254 n266 n294 -10 1 -.names n269 n262 n275 n295 -111 1 -.names n291 n294 n295 n835 n293 -1--0 1 --110 1 -.names n263 n266 n1198 n299 -1-- 1 --0- 1 ---1 1 -.names n262 n1198 n297 -1- 1 --1 1 -.names n281 n293 n299 n297 n296 -001- 1 --011 1 -.names n254 n261 n269 n274 n300 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n243 n254 n269 n304 -0-- 1 --0- 1 ---1 1 -.names n281 n1198 n305 -0- 1 --1 1 -.names n254 n275 n279 n303 -10- 1 -1-0 1 --10 1 -.names n269 n304 n305 n303 n301 -011- 1 --111 1 -.names n275 n300 n1200 n1464 n307 -0--1 1 --1-1 1 ---01 1 -.names n249 n254 n838 n1202 n308 -101- 1 -1-11 1 -.names n262 n301 n307 n308 n306 -0-11 1 --111 1 -.names n306 Pdata_8_ n309 -01 1 -10 1 -.names n357 n1158 n314 -1- 1 --1 1 -.names n323 n420 n315 -0- 1 --1 1 -.names n325 n357 n317 -1- 1 --0 1 -.names n314 n315 n317 n591 n313 -1-1- 1 --11- 1 -1--0 1 --1-0 1 -.names n313 n326 n359 n1215 n321 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n314 n355 n319 -1- 1 --1 1 -.names n321 n319 n588 n318 -11- 1 -1-0 1 -.names Pdata_43_ PC_15_ n323 -01 1 -10 1 -.names n323 n585 n325 -1- 1 --0 1 -.names Pdata_48_ PC_1_ n326 -01 1 -10 1 -.names n323 n325 n326 n328 n322 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n323 n326 n585 n329 -101 1 -.names n326 n585 n328 -10 1 -.names n323 n329 n328 n1216 n327 --1-0 1 -1-10 1 -.names n319 n318 n322 n327 n331 -11-0 1 --110 1 -.names n329 n328 n1215 n1219 n334 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n326 n1158 n1218 n1466 n335 -1--1 1 --0-1 1 ---11 1 -.names n334 n335 n333 -11 1 -.names n314 n355 n359 n1465 n339 -1--1 1 --0-1 1 ---11 1 -.names n585 n326 n337 -1- 1 --1 1 -.names n339 n337 n1376 n336 -11- 1 -1-0 1 -.names n323 n1158 n341 -01 1 -10 1 -.names n420 n326 n342 -1- 1 --1 1 -.names n355 n1158 n343 -1- 1 --0 1 -.names n341 n342 n343 n588 n340 -1-1- 1 --11- 1 -1--0 1 --1-0 1 -.names n323 n337 n345 -0- 1 --1 1 -.names n345 n315 n325 n326 n344 -111- 1 -11-1 1 -.names Pdata_0_ n1672 n346 -01 1 -10 1 -.names n326 n337 n1219 n1221 n351 -01-- 1 -0-1- 1 --1-1 1 ---11 1 -.names n329 n355 n1217 n1471 n352 -0--1 1 --0-1 1 ---11 1 -.names n351 n352 n350 -11 1 -.names Pdata_46_ PC_19_ n357 -01 1 -10 1 -.names Pdata_44_ PC_6_ n355 -01 1 -10 1 -.names n340 n357 n355 n359 n353 -01-- 1 --110 1 -.names n325 n326 n359 -1- 1 --0 1 -.names n319 n359 n358 -1- 1 --1 1 -.names n323 n585 n1215 n1469 n360 -1--0 1 -100- 1 -.names Poutreg_63_ n1 n126 n1472 n365 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_62_ Poutreg_54_ Pcount_0_ n126 n367 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n382 n380 n403 n692 n371 -0-1- 1 --01- 1 -0--1 1 --0-1 1 -.names n403 n572 n369 -0- 1 --1 1 -.names n371 n369 n432 n368 -11- 1 -1-0 1 -.names n375 n570 n373 -0- 1 --0 1 -.names n369 n373 n432 n372 -1-- 1 --1- 1 ---0 1 -.names Pdata_36_ PC_27_ n375 -01 1 -10 1 -.names n389 n570 n377 -1- 1 --0 1 -.names n375 n377 n380 n374 -1-- 1 --1- 1 ---0 1 -.names n450 n1159 n382 -00 1 -.names n403 n572 n380 -11 1 -.names n382 n380 n408 n1232 n378 -1-0- 1 -11-0 1 -.names n372 n374 n378 n386 -110 1 -.names n444 n570 n1234 n1474 n387 -0--1 1 --0-1 1 ---11 1 -.names n1232 n403 n384 -1- 1 --1 1 -.names n389 n572 n385 -1- 1 --0 1 -.names n386 n387 n384 n385 n383 -111- 1 -11-1 1 -.names n450 n1159 n389 -0- 1 --1 1 -.names n375 n570 n392 -1- 1 --0 1 -.names n389 n392 n447 n444 n388 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n375 n404 n452 n395 -0-- 1 --1- 1 ---1 1 -.names n384 n692 n396 -1- 1 --1 1 -.names n388 n395 n396 n445 n393 -111- 1 --110 1 -.names n389 n434 n447 n449 n398 -11-- 1 -1-0- 1 --1-1 1 ---01 1 -.names n375 n401 n452 n1473 n399 -0--1 1 --1-1 1 ---11 1 -.names n398 n399 n397 -11 1 -.names n382 n572 n401 -0- 1 --0 1 -.names n397 n393 n384 n401 n400 -111- 1 -11-1 1 -.names n369 n570 n1159 n405 -1-- 1 --0- 1 ---1 1 -.names n382 n380 n445 n450 n406 -00-- 1 --00- 1 -0--0 1 ---00 1 -.names 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-111111 1 -.names Poutreg_59_ n1 n126 n1478 n428 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_58_ Poutreg_50_ Pcount_0_ n126 n430 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n450 n1159 n432 -11 1 -.names n380 n408 n432 n1232 n431 --01- 1 -1-10 1 -.names n375 n377 n445 n436 -1-- 1 --1- 1 ---0 1 -.names n403 n404 n434 -0- 1 --1 1 -.names n373 n431 n436 n434 n433 -101- 1 --011 1 -.names n389 n444 n438 -10 1 -.names n373 n438 n369 n437 -1-- 1 --1- 1 ---1 1 -.names n382 n570 n692 n441 -011 1 -.names n385 n570 n442 -10 1 -.names n375 n403 n441 n442 n439 -1--- 1 --0-- 1 ---1- 1 ----1 1 -.names n375 n570 n447 -10 1 -.names n450 n1159 n444 -01 1 -.names n403 n572 n445 -00 1 -.names n368 n447 n444 n445 n443 -01-- 1 --111 1 -.names n570 n1234 n449 -1- 1 --1 1 -.names Pdata_39_ PC_20_ n450 -01 1 -10 1 -.names n449 n450 n448 -1- 1 --1 1 -.names n403 n570 n452 -1- 1 --0 1 -.names n404 n1160 n453 -10 1 -.names n452 n453 n451 -1- 1 --1 1 -.names Poutreg_57_ n1 n126 n1479 n455 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_56_ Poutreg_48_ Pcount_0_ n126 n457 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pdata_63_ PD_0_ n459 -01 1 -10 1 -.names Pdata_61_ PD_21_ n460 -01 1 -10 1 -.names n491 n1246 n461 -0- 1 --0 1 -.names n459 n460 n461 n458 -1-- 1 --1- 1 ---1 1 -.names n475 n1248 n477 n464 -1-- 1 --1- 1 ---1 1 -.names n459 n460 n477 n463 -1-- 1 --0- 1 ---1 1 -.names n461 n464 n463 n1607 n462 -11-0 1 --110 1 -.names n477 n483 n852 n1609 n467 -1--1 1 --1-1 1 ---01 1 -.names n472 n849 n1251 n1480 n468 -10-- 1 -1-1- 1 --0-1 1 ---11 1 -.names n467 n462 n468 n466 -111 1 -.names n460 n491 n675 n470 -0-- 1 --1- 1 ---1 1 -.names n459 n477 n471 -1- 1 --0 1 -.names n460 n483 n472 -1- 1 --1 1 -.names n477 n675 n473 -1- 1 --0 1 -.names n470 n471 n472 n473 n469 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names Pdata_59_ PD_17_ n475 -01 1 -10 1 -.names n477 n675 n476 -0- 1 --0 1 -.names Pdata_32_ PD_3_ n477 -01 1 -10 1 -.names n475 n476 n477 n851 n474 -1-1- 1 --11- 1 -1--0 1 --1-0 1 -.names n459 n473 n475 n849 n480 -0--- 1 --1-- 1 ---0- 1 ----0 1 -.names n1249 n670 n481 -1- 1 --1 1 -.names n480 n481 n474 n472 n479 -111- 1 -11-1 1 -.names n459 n491 n483 -1- 1 --1 1 -.names n475 n483 n476 n482 -1-- 1 --1- 1 ---1 1 -.names n475 n476 n1250 n484 -0-- 1 --1- 1 ---0 1 -.names n472 n477 n1246 n487 -1-- 1 --1- 1 ---0 1 -.names Pdata_60_ PD_13_ n491 -01 1 -10 1 -.names n460 n482 n491 n1251 n489 -10-- 1 -1-10 1 -.names n459 n475 n849 n495 -1-- 1 --1- 1 ---0 1 -.names n459 n461 n495 n493 -0-1 1 --11 1 -.names n459 n491 n852 n497 -1-- 1 --0- 1 ---0 1 -.names n463 n851 n498 -1- 1 --0 1 -.names n459 n460 n461 n499 -0-- 1 --1- 1 ---1 1 -.names n477 n493 n1482 n1633 n500 -0-1- 1 --110 1 -.names n460 n1251 n1258 n501 -01- 1 -1-1 1 --11 1 -.names n463 n469 n475 n491 n502 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n1254 n479 n503 -11 1 -.names n497 n498 n499 n500 n501 n466 n502 n503 n496 -11111111 1 -.names Poutreg_55_ n1 n126 n1483 n505 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_54_ Poutreg_46_ Pcount_0_ n126 n507 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n510 n531 n511 -0- 1 --1 1 -.names Pdata_55_ PD_4_ n510 -01 1 -10 1 -.names n511 n510 n531 n508 -11- 1 -1-0 1 -.names n1163 n1164 n515 -00 1 -.names n510 n1270 n513 -01 1 -.names n515 n513 n1484 n512 -11- 1 -1-0 1 -.names n513 n549 n647 n1611 n519 -0--0 1 --0-0 1 ---00 1 -.names n1487 n1488 n543 n526 n520 -111- 1 -11-1 1 -.names n647 n654 n517 -1- 1 --1 1 -.names n519 n520 n517 n1272 n516 -111- 1 -11-0 1 -.names n513 n543 n1486 n1484 n523 --11- 1 -0-11 1 -.names n510 n532 n522 -1- 1 --1 1 -.names n523 n522 n517 n521 -11- 1 -1-1 1 -.names n647 n654 n1272 n527 -0-- 1 --1- 1 ---0 1 -.names n543 n1273 n517 n1274 n528 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n647 n658 n525 -1- 1 --1 1 -.names n546 n511 n526 -1- 1 --1 1 -.names n527 n528 n525 n526 n524 -111- 1 -11-1 1 -.names n531 n546 n532 -0- 1 --1 1 -.names Pdata_51_ PD_1_ n531 -01 1 -10 1 -.names n532 n531 n546 n529 -11- 1 -1-0 1 -.names n524 n521 n534 -11 1 -.names n647 n1489 n1490 n1610 n535 -0--1 1 --111 1 -.names n1492 n658 n1274 n536 -11- 1 -1-1 1 -.names n516 n534 n535 n536 n533 -1111 1 -.names Poutreg_53_ n1 n126 n1494 n538 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_52_ Poutreg_44_ Pcount_0_ n126 n540 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n1495 n517 n1484 n1273 n544 -11-- 1 -1-11 1 -.names n546 n1265 n542 -1- 1 --0 1 -.names n647 n658 n543 -0- 1 --1 1 -.names n544 n542 n543 n541 -11- 1 -1-1 1 -.names n1163 n1164 n549 -01 1 -.names Pdata_54_ PD_16_ n546 -01 1 -10 1 -.names n508 n549 n546 n1273 n545 --1-0 1 -011- 1 -.names Poutreg_51_ n1 n126 n1500 n551 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_50_ Poutreg_42_ Pcount_0_ n126 n553 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n224 n559 n1184 n556 -1-- 1 --0- 1 ---0 1 -.names n207 n212 n1185 n1189 n557 -0-0- 1 --10- 1 -0--1 1 --1-1 1 -.names n209 n216 n556 n557 n554 -0-11 1 --111 1 -.names n915 n1155 n559 -01 1 -.names n559 n224 n207 n558 -111 1 -.names n1184 n228 n561 -11 1 -.names n561 n914 n560 -10 1 -.names Poutreg_49_ n1 n126 n1717 n564 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names Poutreg_48_ Poutreg_40_ Pcount_0_ n126 n566 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pdata_35_ PC_2_ n570 -01 1 -10 1 -.names n403 n432 n569 -0- 1 --0 1 -.names n377 n382 n570 n569 n567 -1-1- 1 -10-1 1 -.names Pdata_40_ PC_9_ n572 -01 1 -10 1 -.names n572 n452 n369 n570 n571 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n450 n567 n572 n571 n574 -11-- 1 -1-0- 1 --1-1 1 ---01 1 -.names n432 n452 n574 n573 -0-1 1 --11 1 -.names n384 n404 n576 -1- 1 --1 1 -.names n375 n570 n573 n1281 n577 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names n1502 n377 n1234 n578 -11- 1 -1-1 1 -.names n433 n383 n393 n576 n577 n578 n575 -111111 1 -.names Poutreg_47_ n1 n126 n1503 n580 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_46_ Poutreg_38_ Pcount_0_ n126 n582 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pdata_47_ PC_12_ n585 -01 1 -10 1 -.names n315 n357 n355 n585 n583 -01-- 1 --101 1 -.names n323 n326 n585 n588 -111 1 -.names n317 n357 n355 n588 n587 -0-1- 1 --011 1 -.names n355 n1158 n591 -11 1 -.names n319 n329 n357 n591 n590 -01-- 1 --111 1 -.names n328 n1215 n594 -0- 1 --1 1 -.names n594 n323 n593 -1- 1 --1 1 -.names Poutreg_45_ n1 n126 n1504 n596 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_44_ Poutreg_36_ Pcount_0_ n126 n598 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n609 n766 n862 n1380 n602 -10-- 1 --00- 1 -1--0 1 ---00 1 -.names n873 n1167 n600 -1- 1 --0 1 -.names n602 n600 n781 n599 -11- 1 -1-0 1 -.names n629 n1166 n607 -01 1 -.names n775 n1167 n604 -00 1 -.names n766 n776 n605 -00 1 -.names n600 n607 n604 n605 n603 -01-- 1 --111 1 -.names n772 n781 n1292 n612 -0-- 1 --0- 1 ---1 1 -.names n1292 n1293 n609 -1- 1 --0 1 -.names n603 n612 n609 n773 n608 -011- 1 -01-0 1 -.names n766 n776 n615 -1- 1 --0 1 -.names n607 n605 n615 n862 n613 -0-1- 1 --01- 1 -0--0 1 --0-0 1 -.names n766 n1166 n1295 n620 -0-- 1 --1- 1 ---0 1 -.names n609 n781 n621 -1- 1 --0 1 -.names n613 n620 n621 n777 n618 -111- 1 --110 1 -.names n773 n772 n862 n1293 n622 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names n607 n780 n1293 n626 -0-- 1 --0- 1 ---0 1 -.names n604 n1297 n627 -0- 1 --1 1 -.names n622 n626 n627 n777 n625 -111- 1 --110 1 -.names n780 n862 n631 -0- 1 --0 1 -.names n777 n776 n1300 n632 -0-- 1 --0- 1 ---1 1 -.names Pdata_57_ PD_10_ n629 -01 1 -10 1 -.names n631 n632 n629 n866 n628 -111- 1 -11-0 1 -.names n1624 n1300 n1301 n634 -11- 1 -1-1 1 -.names n608 n599 n635 -11 1 -.names n628 n766 n775 n1297 n636 -1-0- 1 --00- 1 -1--1 1 --0-1 1 -.names n773 n878 n1166 n1298 n637 -01-- 1 -0-0- 1 --1-1 1 ---01 1 -.names n634 n635 n618 n625 n636 n637 n633 -111111 1 -.names Poutreg_43_ n1 n126 n1505 n639 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_42_ Poutreg_34_ Pcount_0_ n126 n641 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n508 n1165 n1265 n1303 n642 -1-0- 1 --00- 1 -1--0 1 --0-0 1 -.names n510 n531 n648 -0- 1 --0 1 -.names Pdata_53_ PD_22_ n647 -01 1 -10 1 -.names n510 n648 n647 n1265 n646 -11-0 1 --110 1 -.names Poutreg_41_ n1 n126 n1507 n650 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_40_ Poutreg_32_ Pcount_0_ n126 n652 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n1164 n1274 n655 -1- 1 --1 1 -.names n658 n1272 n1508 n1509 n656 -1-11 1 --011 1 -.names n1163 n1164 n654 -0- 1 --0 1 -.names n655 n656 n522 n654 n653 -111- 1 -11-1 1 -.names n510 n529 n549 n659 -1-- 1 --1- 1 ---0 1 -.names n1163 n1265 n1272 n1275 n660 -10-- 1 --00- 1 -1--1 1 ---01 1 -.names n1163 n1164 n658 -0- 1 --1 1 -.names n659 n660 n508 n658 n657 -111- 1 -11-1 1 -.names n647 n653 n657 n662 -11- 1 -0-1 1 --11 1 -.names n524 n542 n517 n663 -11- 1 -1-1 1 -.names n662 n541 n663 n516 n661 -1111 1 -.names Poutreg_39_ n1 n126 n1510 n665 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_38_ Poutreg_30_ Pcount_0_ n126 n667 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n463 n475 n491 n675 n671 -1--- 1 --1-- 1 ---1- 1 ----0 1 -.names n477 n1246 n1250 n1628 n672 -1--1 1 --0-1 1 ---01 1 -.names n477 n852 n670 -0- 1 --0 1 -.names n671 n672 n670 n1252 n668 -111- 1 -11-0 1 -.names Pdata_62_ PD_7_ n675 -01 1 -10 1 -.names n473 n477 n675 n673 -10- 1 -1-1 1 -.names n472 n851 n678 -1- 1 --0 1 -.names n459 n491 n675 n1168 n679 -1--- 1 --0-- 1 ---0- 1 ----1 1 -.names n460 n461 n678 n679 n676 -0-11 1 --111 1 -.names n673 n1249 n1168 n681 -1-- 1 --1- 1 ---1 1 -.names n675 n1168 n1252 n682 -1-- 1 --0- 1 ---0 1 -.names n477 n497 n676 n683 -01- 1 -1-1 1 --11 1 -.names n459 n1257 n684 -1- 1 --1 1 -.names n473 n491 n495 n498 n685 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names n681 n682 n683 n668 n503 n462 n684 n685 n680 -11111111 1 -.names Poutreg_37_ n1 n126 n1511 n687 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_36_ Poutreg_28_ Pcount_0_ n126 n689 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n438 n570 n572 n691 -1-- 1 --0- 1 ---1 1 -.names n432 n572 n692 -0- 1 --0 1 -.names n382 n570 n691 n692 n690 -0-11 1 --111 1 -.names n403 n453 n570 n1631 n694 -0--1 1 --1-1 1 ---11 1 -.names n375 n403 n690 n695 -0-- 1 --1- 1 ---1 1 -.names n408 n444 n1232 n1281 n696 -1-0- 1 --00- 1 -1--1 1 --0-1 1 -.names n433 n383 n694 n397 n695 n696 n693 -111111 1 -.names Poutreg_35_ n1 n126 n1512 n698 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_34_ Poutreg_26_ Pcount_0_ n126 n700 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n477 n499 n1514 n1632 n702 -0-10 1 --110 1 -.names n460 n1258 n675 n495 n703 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n679 n1257 n483 n670 n704 -111- 1 -11-1 1 -.names n466 n479 n668 n702 n703 n704 n701 -111111 1 -.names Poutreg_33_ n1 n126 n1515 n706 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_32_ Poutreg_24_ Pcount_0_ n126 n708 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n742 n895 n710 -1- 1 --1 1 -.names n751 n756 n711 -0- 1 --0 1 -.names n710 n711 n719 n720 n709 -1-0- 1 --10- 1 -1--0 1 --1-0 1 -.names n711 n742 n1318 n716 -1-- 1 --0- 1 ---1 1 -.names n729 n898 n742 n717 -1-- 1 --1- 1 ---1 1 -.names n709 n716 n717 n801 n714 -111- 1 --110 1 -.names n1169 n738 n722 -11 1 -.names n719 n742 n895 n721 -101 1 -.names n751 n756 n719 -01 1 -.names n742 n895 n720 -10 1 -.names n722 n721 n719 n720 n718 -11-- 1 -1-11 1 -.names n711 n720 n732 n727 -1-- 1 --0- 1 ---1 1 -.names n814 n895 n724 -0- 1 --0 1 -.names n751 n732 n725 -1- 1 --1 1 -.names n718 n727 n724 n725 n723 -011- 1 -01-1 1 -.names n738 n1169 n729 -0- 1 --1 1 -.names n742 n895 n730 -0- 1 --0 1 -.names n719 n729 n730 n728 -0-- 1 --1- 1 ---1 1 -.names n738 n1169 n732 -1- 1 --0 1 -.names n732 n814 n888 n731 -1-- 1 --0- 1 ---0 1 -.names n710 n711 n722 n735 -1-- 1 --1- 1 ---0 1 -.names Pdata_44_ PC_7_ n738 -01 1 -10 1 -.names n802 n895 n1169 n740 -0-- 1 --0- 1 ---1 1 -.names n738 n740 n751 n737 -1-- 1 --1- 1 ---0 1 -.names n732 n742 n898 n744 -1-- 1 --0- 1 ---1 1 -.names n1635 n729 n724 n751 n745 -11-- 1 -1-1- 1 -1--1 1 -.names Pdata_39_ PC_22_ n742 -01 1 -10 1 -.names n725 n756 n895 n743 -1-- 1 --0- 1 ---0 1 -.names n744 n745 n742 n743 n741 -111- 1 -11-1 1 -.names n711 n719 n742 n748 -10- 1 --01 1 -1-0 1 -.names n748 n751 n802 n746 -10- 1 -1-0 1 -.names Pdata_41_ PC_11_ n751 -01 1 -10 1 -.names n751 n888 n895 n749 -10- 1 --00 1 -.names n801 n898 n754 -0- 1 --1 1 -.names n722 n749 n754 n756 n752 -0-1- 1 --11- 1 ---10 1 -.names Pdata_40_ PC_18_ n756 -01 1 -10 1 -.names n719 n742 n751 n756 n755 -0-0- 1 --10- 1 -0--1 1 --1-1 1 -.names n746 n814 n1169 n759 -01- 1 -0-1 1 --10 1 -.names n738 n759 n895 n757 -010 1 -.names n740 n751 n760 -1- 1 --1 1 -.names Poutreg_31_ n1 n126 n1517 n762 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_30_ Poutreg_22_ Pcount_0_ n126 n764 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pdata_59_ PD_5_ n766 -01 1 -10 1 -.names n766 n1166 n1295 n765 -1-- 1 --0- 1 ---0 1 -.names n607 n604 n1293 n769 -0-- 1 --0- 1 ---0 1 -.names n629 n1166 n773 -00 1 -.names n766 n776 n772 -10 1 -.names n600 n604 n773 n772 n771 -0-1- 1 --111 1 -.names n775 n1167 n777 -10 1 -.names Pdata_56_ PD_20_ n775 -01 1 -10 1 -.names Pdata_55_ PD_15_ n776 -01 1 -10 1 -.names n629 n777 n775 n776 n774 -01-- 1 -0-11 1 -.names n775 n1167 n780 -11 1 -.names n629 n1166 n781 -10 1 -.names n780 n781 n779 -11 1 -.names Poutreg_29_ n1 n126 n1521 n783 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_28_ Poutreg_20_ Pcount_0_ n126 n785 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n207 n789 n914 n786 -00- 1 --00 1 -.names n220 n222 n789 -11 1 -.names n789 n209 n788 -11 1 -.names n230 n915 n1155 n1383 n790 --0-0 1 -100- 1 -.names n1155 n1188 n795 -0- 1 --1 1 -.names n795 n1184 n794 -1- 1 --0 1 -.names Poutreg_27_ n1 n126 n1524 n797 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_26_ Poutreg_18_ Pcount_0_ n126 n799 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n742 n756 n802 -10 1 -.names n751 n895 n803 -00 1 -.names n738 n1169 n801 -00 1 -.names n802 n803 n801 n722 n800 -111- 1 -11-1 1 -.names n751 n814 n1318 n806 -1-- 1 --0- 1 ---1 1 -.names n721 n801 n800 n806 n804 -0-01 1 --001 1 -.names n711 n720 n801 n808 -1-- 1 --0- 1 ---0 1 -.names n732 n749 n802 n809 -1-- 1 --1- 1 ---0 1 -.names n730 n710 n811 -11 1 -.names n719 n811 n1340 n810 -0-- 1 --1- 1 ---0 1 -.names n742 n756 n814 -00 1 -.names n725 n814 n895 n813 -010 1 -.names n742 n898 n1169 n817 -001 1 -.names n817 n738 n816 -11 1 -.names Poutreg_25_ n1 n126 n1718 n819 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names Poutreg_24_ Poutreg_16_ Pcount_0_ n126 n821 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n266 n1172 n824 -0- 1 --1 1 -.names n254 n264 n279 n824 n822 -1-01 1 --001 1 -.names n254 n297 n827 -0- 1 --1 1 -.names n274 n822 n835 n1201 n829 -0-0- 1 --10- 1 -0--0 1 --1-0 1 -.names n249 n257 n296 n827 n829 n1702 n826 -111110 1 -.names Poutreg_23_ n1 n126 n1528 n831 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_22_ Poutreg_14_ Pcount_0_ n126 n833 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pdata_33_ PC_10_ n835 -01 1 -10 1 -.names n274 n266 n835 n834 -11- 1 -1-1 1 -.names n254 n297 n1384 n837 -01- 1 -1-0 1 --10 1 -.names n296 n1203 n838 -10 1 -.names n275 n835 n1647 n1648 n839 -1--- 1 --0-- 1 ---1- 1 ----1 1 -.names n244 n266 n1202 n841 -10- 1 -1-1 1 -.names n257 n837 n838 n839 n841 n1649 n836 -111110 1 -.names Poutreg_21_ n1 n126 n1529 n843 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_20_ Poutreg_12_ Pcount_0_ n126 n845 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n459 n475 n675 n847 -0-- 1 --1- 1 ---0 1 -.names n459 n475 n847 n846 -1-1 1 --01 1 -.names n460 n491 n849 -01 1 -.names n459 n675 n849 n848 -011 1 -.names n475 n675 n851 -00 1 -.names n460 n675 n475 n852 -111 1 -.names n851 n852 n1249 n850 -1-0 1 --10 1 -.names Poutreg_19_ n1 n126 n1533 n855 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_18_ Poutreg_10_ Pcount_0_ n126 n857 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n772 n781 n780 n858 -111 1 -.names n607 n605 n777 n859 -101 1 -.names n1166 n629 n862 -11 1 -.names n605 n1167 n1325 n863 -11- 1 -1-1 1 --01 1 -.names n775 n862 n863 n860 -011 1 -.names n777 n776 n1166 n866 -100 1 -.names n766 n866 n878 n864 -01- 1 -0-0 1 -.names Poutreg_17_ n1 n126 n1719 n869 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names Poutreg_16_ Poutreg_8_ Pcount_0_ n126 n871 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n775 n1300 n1325 n874 -0-- 1 --0- 1 ---1 1 -.names n1297 n775 n875 -1- 1 --1 1 -.names n775 n615 n873 -1- 1 --1 1 -.names n862 n874 n875 n873 n872 -011- 1 --111 1 -.names n629 n776 n1292 n1654 n877 -1--1 1 --0-1 1 ---11 1 -.names n775 n1289 n878 -0- 1 --1 1 -.names n866 n877 n878 n1166 n876 -0--0 1 -011- 1 -.names n615 n629 n777 n879 -1-- 1 --1- 1 ---0 1 -.names n781 n1298 n1301 n880 -10- 1 -1-0 1 -.names Poutreg_15_ n1 n126 n1538 n884 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_14_ Poutreg_6_ Pcount_0_ n126 n886 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n751 n895 n888 -10 1 -.names n756 n888 n887 -01 1 -.names n725 n811 n889 -1- 1 --1 1 -.names Poutreg_13_ n1 n126 n1539 n891 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_12_ Poutreg_4_ Pcount_0_ n126 n893 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n801 n895 n896 -1- 1 --0 1 -.names Pdata_43_ PC_25_ n895 -01 1 -10 1 -.names n725 n756 n896 n895 n894 -001- 1 --011 1 -.names n711 n895 n898 -1- 1 --0 1 -.names n738 n743 n894 n898 n897 -010- 1 --101 1 -.names n741 n804 n808 n1319 n901 -1111 1 -.names n742 n754 n897 n902 -01- 1 -1-1 1 --11 1 -.names n724 n751 n1340 n903 -1-- 1 --0- 1 ---1 1 -.names n710 n719 n1169 n904 -1-- 1 --0- 1 ---0 1 -.names n895 n1341 n746 n1318 n905 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n901 n723 n902 n903 n904 n905 n900 -111111 1 -.names Poutreg_11_ n1 n126 n1540 n907 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_10_ Poutreg_2_ Pcount_0_ n126 n909 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n201 n914 n912 -01 1 -.names n220 n1156 n911 -10 1 -.names n231 n912 n911 n207 n910 -111- 1 -11-1 1 -.names Pdata_47_ PD_12_ n914 -01 1 -10 1 -.names Pdata_52_ PD_26_ n915 -01 1 -10 1 -.names n914 n915 n1660 n913 -1-- 1 --1- 1 ---0 1 -.names n212 n226 n917 -1- 1 --0 1 -.names Poutreg_9_ n1 n126 n1541 n920 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Poutreg_8_ Poutreg_0_ Pcount_0_ n126 n922 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pcount_0_ n924 n925 -1- 1 --1 1 -.names n92 Preset_0_ n924 -1- 1 --1 1 -.names n925 Pcount_1_ n924 n923 -11- 1 -1-1 1 -.names n923 Pcount_2_ n924 n926 -11- 1 -1-1 1 -.names Pcount_3_ n1177 n928 -1- 1 --1 1 -.names Pcount_0_ n1 n928 n1453 n929 -111- 1 --110 1 -.names PC_26_ PC_0_ n1352 n1353 n932 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PC_25_ PC_1_ n1348 n1351 n933 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PC_27_ n1359 n1542 n934 -0-1 1 --11 1 -.names n932 n933 n934 n931 -111 1 -.names PC_27_ PC_25_ n1352 n1353 n936 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_24_ PC_0_ n1348 n1351 n937 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PC_26_ n1359 n1543 n938 -0-1 1 --11 1 -.names n936 n937 n938 n935 -111 1 -.names PC_26_ PC_24_ n1352 n1353 n940 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_27_ PC_23_ n1348 n1351 n941 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_25_ n1359 n1544 n942 -0-1 1 --11 1 -.names n940 n941 n942 n939 -111 1 -.names PC_25_ PC_23_ n1352 n1353 n944 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_26_ PC_22_ n1348 n1351 n945 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_24_ n1359 n1545 n946 -0-1 1 --11 1 -.names n944 n945 n946 n943 -111 1 -.names PC_24_ PC_22_ n1352 n1353 n948 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_25_ PC_21_ n1348 n1351 n949 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_23_ n1359 n1546 n950 -0-1 1 --11 1 -.names n948 n949 n950 n947 -111 1 -.names PC_23_ PC_21_ n1352 n1353 n952 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_24_ PC_20_ n1348 n1351 n953 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_22_ n1359 n1547 n954 -0-1 1 --11 1 -.names n952 n953 n954 n951 -111 1 -.names PC_22_ PC_20_ n1352 n1353 n956 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_23_ PC_19_ n1348 n1351 n957 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_21_ n1359 n1548 n958 -0-1 1 --11 1 -.names n956 n957 n958 n955 -111 1 -.names PC_21_ PC_19_ n1352 n1353 n960 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_22_ PC_18_ n1348 n1351 n961 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_20_ n1359 n1549 n962 -0-1 1 --11 1 -.names n960 n961 n962 n959 -111 1 -.names PC_20_ PC_18_ n1352 n1353 n964 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_21_ PC_17_ n1348 n1351 n965 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_19_ n1359 n1550 n966 -0-1 1 --11 1 -.names n964 n965 n966 n963 -111 1 -.names PC_19_ PC_17_ n1352 n1353 n968 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_20_ PC_16_ n1348 n1351 n969 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_18_ n1359 n1551 n970 -0-1 1 --11 1 -.names n968 n969 n970 n967 -111 1 -.names PC_18_ PC_16_ n1352 n1353 n972 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_19_ PC_15_ n1348 n1351 n973 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_17_ n1359 n1552 n974 -0-1 1 --11 1 -.names n972 n973 n974 n971 -111 1 -.names PC_17_ PC_15_ n1352 n1353 n976 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_18_ PC_14_ n1348 n1351 n977 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_16_ n1359 n1553 n978 -0-1 1 --11 1 -.names n976 n977 n978 n975 -111 1 -.names PC_16_ PC_14_ n1352 n1353 n980 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_17_ PC_13_ n1348 n1351 n981 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_15_ n1359 n1554 n982 -0-1 1 --11 1 -.names n980 n981 n982 n979 -111 1 -.names PC_15_ PC_13_ n1352 n1353 n984 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_16_ PC_12_ n1348 n1351 n985 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_14_ n1359 n1555 n986 -0-1 1 --11 1 -.names n984 n985 n986 n983 -111 1 -.names PC_14_ PC_12_ n1352 n1353 n988 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_15_ PC_11_ n1348 n1351 n989 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_13_ n1359 n1556 n990 -0-1 1 --11 1 -.names n988 n989 n990 n987 -111 1 -.names PC_13_ PC_11_ n1352 n1353 n992 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_14_ PC_10_ n1348 n1351 n993 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_12_ n1359 n1557 n994 -0-1 1 --11 1 -.names n992 n993 n994 n991 -111 1 -.names PC_12_ PC_10_ n1352 n1353 n996 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_13_ PC_9_ n1348 n1351 n997 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_11_ n1359 n1558 n998 -0-1 1 --11 1 -.names n996 n997 n998 n995 -111 1 -.names PC_11_ PC_9_ n1352 n1353 n1000 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_12_ PC_8_ n1348 n1351 n1001 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_10_ n1359 n1559 n1002 -0-1 1 --11 1 -.names n1000 n1001 n1002 n999 -111 1 -.names PC_10_ PC_8_ n1352 n1353 n1004 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_11_ PC_7_ n1348 n1351 n1005 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_9_ n1359 n1560 n1006 -0-1 1 --11 1 -.names n1004 n1005 n1006 n1003 -111 1 -.names PC_9_ PC_7_ n1352 n1353 n1008 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_10_ PC_6_ n1348 n1351 n1009 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_8_ n1359 n1561 n1010 -0-1 1 --11 1 -.names n1008 n1009 n1010 n1007 -111 1 -.names PC_8_ PC_6_ n1352 n1353 n1012 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_9_ PC_5_ n1348 n1351 n1013 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_7_ n1359 n1562 n1014 -0-1 1 --11 1 -.names n1012 n1013 n1014 n1011 -111 1 -.names PC_7_ PC_5_ n1352 n1353 n1016 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_8_ PC_4_ n1348 n1351 n1017 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_6_ n1359 n1563 n1018 -0-1 1 --11 1 -.names n1016 n1017 n1018 n1015 -111 1 -.names PC_6_ PC_4_ n1352 n1353 n1020 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_7_ PC_3_ n1348 n1351 n1021 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_5_ n1359 n1564 n1022 -0-1 1 --11 1 -.names n1020 n1021 n1022 n1019 -111 1 -.names PC_5_ PC_3_ n1352 n1353 n1024 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_6_ PC_2_ n1348 n1351 n1025 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_4_ n1359 n1565 n1026 -0-1 1 --11 1 -.names n1024 n1025 n1026 n1023 -111 1 -.names PC_4_ PC_2_ n1352 n1353 n1028 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_5_ PC_1_ n1348 n1351 n1029 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_3_ n1359 n1566 n1030 -0-1 1 --11 1 -.names n1028 n1029 n1030 n1027 -111 1 -.names PC_3_ PC_1_ n1352 n1353 n1032 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_4_ PC_0_ n1348 n1351 n1033 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_2_ n1359 n1567 n1034 -0-1 1 --11 1 -.names n1032 n1033 n1034 n1031 -111 1 -.names PC_2_ PC_0_ n1352 n1353 n1036 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PC_27_ PC_3_ n1348 n1351 n1037 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PC_1_ n1359 n1568 n1038 -0-1 1 --11 1 -.names n1036 n1037 n1038 n1035 -111 1 -.names PC_27_ PC_1_ n1352 n1353 n1040 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PC_26_ PC_2_ n1348 n1351 n1041 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PC_0_ n1359 n1569 n1042 -0-1 1 --11 1 -.names n1040 n1041 n1042 n1039 -111 1 -.names PD_26_ PD_0_ n1352 n1353 n1044 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PD_25_ PD_1_ n1348 n1351 n1045 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PD_27_ n1359 n1570 n1046 -0-1 1 --11 1 -.names n1044 n1045 n1046 n1043 -111 1 -.names PD_27_ PD_25_ n1352 n1353 n1048 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_24_ PD_0_ n1348 n1351 n1049 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PD_26_ n1359 n1571 n1050 -0-1 1 --11 1 -.names n1048 n1049 n1050 n1047 -111 1 -.names PD_26_ PD_24_ n1352 n1353 n1052 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_27_ PD_23_ n1348 n1351 n1053 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_25_ n1359 n1572 n1054 -0-1 1 --11 1 -.names n1052 n1053 n1054 n1051 -111 1 -.names PD_25_ PD_23_ n1352 n1353 n1056 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_26_ PD_22_ n1348 n1351 n1057 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_24_ n1359 n1573 n1058 -0-1 1 --11 1 -.names n1056 n1057 n1058 n1055 -111 1 -.names PD_24_ PD_22_ n1352 n1353 n1060 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_25_ PD_21_ n1348 n1351 n1061 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_23_ n1359 n1574 n1062 -0-1 1 --11 1 -.names n1060 n1061 n1062 n1059 -111 1 -.names PD_23_ PD_21_ n1352 n1353 n1064 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_24_ PD_20_ n1348 n1351 n1065 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_22_ n1359 n1575 n1066 -0-1 1 --11 1 -.names n1064 n1065 n1066 n1063 -111 1 -.names PD_22_ PD_20_ n1352 n1353 n1068 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_23_ PD_19_ n1348 n1351 n1069 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_21_ n1359 n1576 n1070 -0-1 1 --11 1 -.names n1068 n1069 n1070 n1067 -111 1 -.names PD_21_ PD_19_ n1352 n1353 n1072 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_22_ PD_18_ n1348 n1351 n1073 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_20_ n1359 n1577 n1074 -0-1 1 --11 1 -.names n1072 n1073 n1074 n1071 -111 1 -.names PD_20_ PD_18_ n1352 n1353 n1076 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_21_ PD_17_ n1348 n1351 n1077 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_19_ n1359 n1578 n1078 -0-1 1 --11 1 -.names n1076 n1077 n1078 n1075 -111 1 -.names PD_19_ PD_17_ n1352 n1353 n1080 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_20_ PD_16_ n1348 n1351 n1081 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_18_ n1359 n1579 n1082 -0-1 1 --11 1 -.names n1080 n1081 n1082 n1079 -111 1 -.names PD_18_ PD_16_ n1352 n1353 n1084 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_19_ PD_15_ n1348 n1351 n1085 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_17_ n1359 n1580 n1086 -0-1 1 --11 1 -.names n1084 n1085 n1086 n1083 -111 1 -.names PD_17_ PD_15_ n1352 n1353 n1088 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_18_ PD_14_ n1348 n1351 n1089 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_16_ n1359 n1581 n1090 -0-1 1 --11 1 -.names n1088 n1089 n1090 n1087 -111 1 -.names PD_16_ PD_14_ n1352 n1353 n1092 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_17_ PD_13_ n1348 n1351 n1093 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_15_ n1359 n1582 n1094 -0-1 1 --11 1 -.names n1092 n1093 n1094 n1091 -111 1 -.names PD_15_ PD_13_ n1352 n1353 n1096 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_16_ PD_12_ n1348 n1351 n1097 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_14_ n1359 n1583 n1098 -0-1 1 --11 1 -.names n1096 n1097 n1098 n1095 -111 1 -.names PD_14_ PD_12_ n1352 n1353 n1100 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_15_ PD_11_ n1348 n1351 n1101 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_13_ n1359 n1584 n1102 -0-1 1 --11 1 -.names n1100 n1101 n1102 n1099 -111 1 -.names PD_13_ PD_11_ n1352 n1353 n1104 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_14_ PD_10_ n1348 n1351 n1105 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_12_ n1359 n1585 n1106 -0-1 1 --11 1 -.names n1104 n1105 n1106 n1103 -111 1 -.names PD_12_ PD_10_ n1352 n1353 n1108 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_13_ PD_9_ n1348 n1351 n1109 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_11_ n1359 n1586 n1110 -0-1 1 --11 1 -.names n1108 n1109 n1110 n1107 -111 1 -.names PD_11_ PD_9_ n1352 n1353 n1112 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_12_ PD_8_ n1348 n1351 n1113 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_10_ n1359 n1587 n1114 -0-1 1 --11 1 -.names n1112 n1113 n1114 n1111 -111 1 -.names PD_10_ PD_8_ n1352 n1353 n1116 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_11_ PD_7_ n1348 n1351 n1117 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_9_ n1359 n1588 n1118 -0-1 1 --11 1 -.names n1116 n1117 n1118 n1115 -111 1 -.names PD_9_ PD_7_ n1352 n1353 n1120 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_10_ PD_6_ n1348 n1351 n1121 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_8_ n1359 n1589 n1122 -0-1 1 --11 1 -.names n1120 n1121 n1122 n1119 -111 1 -.names PD_8_ PD_6_ n1352 n1353 n1124 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_9_ PD_5_ n1348 n1351 n1125 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_7_ n1359 n1590 n1126 -0-1 1 --11 1 -.names n1124 n1125 n1126 n1123 -111 1 -.names PD_7_ PD_5_ n1352 n1353 n1128 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_8_ PD_4_ n1348 n1351 n1129 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_6_ n1359 n1591 n1130 -0-1 1 --11 1 -.names n1128 n1129 n1130 n1127 -111 1 -.names PD_6_ PD_4_ n1352 n1353 n1132 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_7_ PD_3_ n1348 n1351 n1133 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_5_ n1359 n1592 n1134 -0-1 1 --11 1 -.names n1132 n1133 n1134 n1131 -111 1 -.names PD_5_ PD_3_ n1352 n1353 n1136 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_6_ PD_2_ n1348 n1351 n1137 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_4_ n1359 n1593 n1138 -0-1 1 --11 1 -.names n1136 n1137 n1138 n1135 -111 1 -.names PD_4_ PD_2_ n1352 n1353 n1140 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_5_ PD_1_ n1348 n1351 n1141 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_3_ n1359 n1594 n1142 -0-1 1 --11 1 -.names n1140 n1141 n1142 n1139 -111 1 -.names PD_3_ PD_1_ n1352 n1353 n1144 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_4_ PD_0_ n1348 n1351 n1145 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_2_ n1359 n1595 n1146 -0-1 1 --11 1 -.names n1144 n1145 n1146 n1143 -111 1 -.names PD_2_ PD_0_ n1352 n1353 n1148 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names PD_27_ PD_3_ n1348 n1351 n1149 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PD_1_ n1359 n1596 n1150 -0-1 1 --11 1 -.names n1148 n1149 n1150 n1147 -111 1 -.names PD_27_ PD_1_ n1352 n1353 n1152 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PD_26_ PD_2_ n1348 n1351 n1153 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names PD_0_ n1359 n1597 n1154 -0-1 1 --11 1 -.names n1152 n1153 n1154 n1151 -111 1 -.names Pdata_48_ PD_23_ n1155 -01 1 -10 1 -.names Pdata_51_ PD_18_ n1156 -01 1 -10 1 -.names Pdata_45_ PC_26_ n1158 -01 1 -10 1 -.names Pdata_38_ PC_5_ n1159 -01 1 -10 1 -.names n375 n385 n432 n572 n1160 -10-- 1 -1-10 1 -.names Pdata_52_ PD_11_ n1163 -01 1 -10 1 -.names Pdata_56_ PD_19_ n1164 -01 1 -10 1 -.names n1164 n546 n1165 -01 1 -10 1 -.names Pdata_60_ PD_24_ n1166 -01 1 -10 1 -.names Pdata_58_ PD_27_ n1167 -01 1 -10 1 -.names n460 n475 n1168 -11 1 -00 1 -.names Pdata_42_ PC_3_ n1169 -01 1 -10 1 -.names n220 n1155 n1184 n1170 -0-0 1 --00 1 -.names n254 n835 n1172 -11 1 -00 1 -.names Pencrypt_mode_0_ Pencrypt_0_ n1173 -11 1 -00 1 -.names Pcount_2_ Pcount_1_ Pcount_0_ n1177 -0-- 1 --0- 1 ---0 1 -.names n220 n1156 n1184 -00 1 -.names n220 n1156 n1185 -11 1 -.names n915 n1155 n1186 -00 1 -.names n1184 n209 n1187 -11 1 -.names n201 n914 n915 n1188 -0-- 1 --0- 1 ---1 1 -.names n201 n209 n914 n1189 -0-- 1 --0- 1 ---0 1 -.names n269 n275 n835 n1198 -1-- 1 --0- 1 ---0 1 -.names n275 n240 n1199 -11 1 -.names n266 n835 n1200 -10 1 -.names n266 n269 n275 n1201 -010 1 -.names n275 n274 n835 n1202 -1-- 1 --0- 1 ---0 1 -.names n254 n266 n1199 n1204 -011 1 -.names n1200 n295 n254 n1205 -111 1 -.names n278 n280 n1204 n1205 n1203 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n357 n343 n1215 -1- 1 --1 1 -.names n343 n357 n1216 -1- 1 --0 1 -.names n357 n1158 n1217 -0- 1 --1 1 -.names n420 n357 n323 n1218 -1-- 1 --1- 1 ---1 1 -.names n323 n355 n1217 n1219 -1-- 1 --1- 1 ---1 1 -.names n323 n326 n1216 n1220 -1-- 1 --1- 1 ---1 1 -.names n323 n357 n420 n1158 n1221 -1--- 1 --0-- 1 ---1- 1 ----0 1 -.names n375 n570 n1232 -1- 1 --1 1 -.names n369 n375 n1234 -1- 1 --1 1 -.names n475 n675 n1246 -10 1 -.names n459 n470 n1248 -0- 1 --1 1 -.names n459 n491 n1249 -0- 1 --1 1 -.names n460 n1249 n1250 -00 1 -.names n477 n847 n1251 -1- 1 --1 1 -.names n459 n491 n1252 -11 1 -.names n484 n487 n489 n1254 -110 1 -.names n470 n475 n477 n1257 -1-- 1 --0- 1 ---1 1 -.names n477 n491 n847 n1258 -0-- 1 --1- 1 ---1 1 -.names n510 n531 n1265 -00 1 -.names n531 n546 n1270 -11 1 -.names n510 n1270 n1272 -11 1 -.names n510 n532 n1273 -0- 1 --1 1 -.names n546 n1265 n1274 -0- 1 --0 1 -.names n515 n546 n1275 -0- 1 --1 1 -.names n369 n382 n1281 -1- 1 --0 1 -.names n629 n776 n1167 n1289 -1-- 1 --1- 1 ---0 1 -.names n775 n1167 n1292 -1- 1 --0 1 -.names n776 n766 n1293 -11 1 -.names n775 n1289 n1295 -00 1 -.names n605 n781 n1297 -0- 1 --0 1 -.names n615 n780 n1298 -1- 1 --0 1 -.names n607 n781 n1300 -00 1 -.names n873 n1167 n1301 -1- 1 --1 1 -.names n1164 n546 n1303 -11 1 -.names n895 n729 n1318 -1- 1 --1 1 -.names n735 n737 n728 n731 n1319 -1111 1 -.names n1319 n723 n714 n1321 -111 1 -.names n781 n1167 n1293 n1323 -101 1 -.names n629 n1301 n1324 -1- 1 --1 1 -.names n605 n1293 n1325 -00 1 -.names n625 n765 n769 n771 n1326 -1110 1 -.names n215 n554 n1329 -11 1 -.names n801 n722 n1340 -1- 1 --1 1 -.names n751 n814 n1340 n1341 -0-- 1 --0- 1 ---0 1 -.names n924 n1358 n1345 -1- 1 --0 1 -.names Pencrypt_mode_0_ n1345 n1347 -1- 1 --1 1 -.names n929 n1347 n1348 -0- 1 --1 1 -.names Pencrypt_mode_0_ n1345 n1350 -0- 1 --1 1 -.names n929 n1350 n1351 -0- 1 --1 1 -.names n929 n1347 n1352 -1- 1 --1 1 -.names n929 n1350 n1353 -1- 1 --1 1 -.names Preset_0_ n92 n1354 -1- 1 --0 1 -.names Pencrypt_0_ n1354 n1356 -1- 1 --1 1 -.names Pencrypt_0_ n1354 n1357 -0- 1 --1 1 -.names n1173 n1 n1358 -1- 1 --1 1 -.names n924 n1358 n1359 -1- 1 --1 1 -.names n243 n261 n269 n1598 n1369 -0--1 1 --1-1 1 ---01 1 -.names n254 n266 n295 n1600 n1371 -0--0 1 --110 1 -.names n281 n294 n835 n1372 -11- 1 -1-1 1 --10 1 -.names n323 n326 n328 n355 n1373 -1-1- 1 -10-1 1 -.names n344 n357 n1373 n1375 -11- 1 -1-0 1 --00 1 -.names n319 n323 n1216 n1376 -00- 1 -0-0 1 --10 1 -.names n220 n228 n914 n1617 n1378 -1--0 1 --0-0 1 ---10 1 -.names n878 n1166 n1295 n1380 -00- 1 -0-1 1 --11 1 -.names n642 n647 n1625 n1382 -1-1 1 --01 1 -.names n207 n914 n1170 n1383 -00- 1 -0-1 1 --11 1 -.names n275 n834 n1200 n262 n1384 -11-- 1 -1-11 1 -.names n220 n222 n228 n230 n1385 ---11 1 -011- 1 -.names n228 n914 n915 n1185 n1386 -1--1 1 --011 1 -.names Pdata_in_6_ n1 n1538 n1387 -00- 1 -0-1 1 --11 1 -.names Pinreg_6_ n1 n1528 n1388 -00- 1 -0-1 1 --11 1 -.names Pinreg_14_ n1 n1517 n1389 -00- 1 -0-1 1 --11 1 -.names Pinreg_22_ n1 n1510 n1390 -00- 1 -0-1 1 --11 1 -.names Pinreg_30_ n1 n1503 n1391 -00- 1 -0-1 1 --11 1 -.names Pinreg_38_ n1 n1483 n1392 -00- 1 -0-1 1 --11 1 -.names Pinreg_46_ n1 n1472 n1393 -00- 1 -0-1 1 --11 1 -.names Pinreg_54_ n1 n234 n1394 -00- 1 -0-1 1 --11 1 -.names Pdata_in_4_ n1 n1539 n1395 -00- 1 -0-1 1 --11 1 -.names Pinreg_4_ n1 n1529 n1396 -00- 1 -0-1 1 --11 1 -.names Pinreg_12_ n1 n1521 n1397 -00- 1 -0-1 1 --11 1 -.names Pinreg_20_ n1 n1511 n1398 -00- 1 -0-1 1 --11 1 -.names Pinreg_28_ n1 n1504 n1399 -00- 1 -0-1 1 --11 1 -.names Pinreg_36_ n1 n1494 n1400 -00- 1 -0-1 1 --11 1 -.names Pinreg_44_ n1 n1477 n1401 -00- 1 -0-1 1 --11 1 -.names Pinreg_52_ n1 n287 n1402 -00- 1 -0-1 1 --11 1 -.names Pdata_in_2_ n1 n1540 n1403 -00- 1 -0-1 1 --11 1 -.names Pinreg_2_ n1 n1533 n1404 -00- 1 -0-1 1 --11 1 -.names Pinreg_10_ n1 n1524 n1405 -00- 1 -0-1 1 --11 1 -.names Pinreg_18_ n1 n1512 n1406 -00- 1 -0-1 1 --11 1 -.names Pinreg_26_ n1 n1505 n1407 -00- 1 -0-1 1 --11 1 -.names Pinreg_34_ n1 n1500 n1408 -00- 1 -0-1 1 --11 1 -.names Pinreg_42_ n1 n1478 n1409 -00- 1 -0-1 1 --11 1 -.names Pinreg_50_ n1 n309 n1410 -00- 1 -0-1 1 --11 1 -.names Pdata_in_0_ n1 n1541 n1411 -00- 1 -0-1 1 --11 1 -.names Pinreg_0_ n1 n1719 n1412 -00- 1 -0-0 1 --10 1 -.names Pinreg_8_ n1 n1718 n1413 -00- 1 -0-0 1 --10 1 -.names Pinreg_16_ n1 n1515 n1414 -00- 1 -0-1 1 --11 1 -.names Pinreg_24_ n1 n1507 n1415 -00- 1 -0-1 1 --11 1 -.names Pinreg_32_ n1 n1717 n1416 -00- 1 -0-0 1 --10 1 -.names Pinreg_40_ n1 n1479 n1417 -00- 1 -0-1 1 --11 1 -.names Pinreg_48_ n1 n346 n1418 -00- 1 -0-1 1 --11 1 -.names Pdata_in_7_ Pdata_63_ n1 n1419 -00- 1 --01 1 -0-0 1 -.names Pinreg_7_ Pdata_62_ n1 n1420 -00- 1 --01 1 -0-0 1 -.names Pinreg_15_ Pdata_61_ n1 n1421 -00- 1 --01 1 -0-0 1 -.names Pinreg_23_ Pdata_60_ n1 n1422 -00- 1 --01 1 -0-0 1 -.names Pinreg_31_ Pdata_59_ n1 n1423 -00- 1 --01 1 -0-0 1 -.names Pinreg_39_ Pdata_58_ n1 n1424 -00- 1 --01 1 -0-0 1 -.names Pinreg_47_ Pdata_57_ n1 n1425 -00- 1 --01 1 -0-0 1 -.names Pinreg_55_ Pdata_56_ n1 n1426 -00- 1 --01 1 -0-0 1 -.names Pdata_in_5_ Pdata_55_ n1 n1427 -00- 1 --01 1 -0-0 1 -.names Pinreg_5_ Pdata_54_ n1 n1428 -00- 1 --01 1 -0-0 1 -.names Pinreg_13_ Pdata_53_ n1 n1429 -00- 1 --01 1 -0-0 1 -.names Pinreg_21_ Pdata_52_ n1 n1430 -00- 1 --01 1 -0-0 1 -.names Pinreg_29_ Pdata_51_ n1 n1431 -00- 1 --01 1 -0-0 1 -.names Pinreg_37_ Pdata_50_ n1 n1432 -00- 1 --01 1 -0-0 1 -.names Pinreg_45_ Pdata_49_ n1 n1433 -00- 1 --01 1 -0-0 1 -.names Pinreg_53_ Pdata_48_ n1 n1434 -00- 1 --01 1 -0-0 1 -.names Pdata_in_3_ Pdata_47_ n1 n1435 -00- 1 --01 1 -0-0 1 -.names Pinreg_3_ Pdata_46_ n1 n1436 -00- 1 --01 1 -0-0 1 -.names Pinreg_11_ Pdata_45_ n1 n1437 -00- 1 --01 1 -0-0 1 -.names Pinreg_19_ Pdata_44_ n1 n1438 -00- 1 --01 1 -0-0 1 -.names Pinreg_27_ Pdata_43_ n1 n1439 -00- 1 --01 1 -0-0 1 -.names Pinreg_35_ Pdata_42_ n1 n1440 -00- 1 --01 1 -0-0 1 -.names Pinreg_43_ Pdata_41_ n1 n1441 -00- 1 --01 1 -0-0 1 -.names Pinreg_51_ Pdata_40_ n1 n1442 -00- 1 --01 1 -0-0 1 -.names Pdata_in_1_ Pdata_39_ n1 n1443 -00- 1 --01 1 -0-0 1 -.names Pinreg_1_ Pdata_38_ n1 n1444 -00- 1 --01 1 -0-0 1 -.names Pinreg_9_ Pdata_37_ n1 n1445 -00- 1 --01 1 -0-0 1 -.names Pinreg_17_ Pdata_36_ n1 n1446 -00- 1 --01 1 -0-0 1 -.names Pinreg_25_ Pdata_35_ n1 n1447 -00- 1 --01 1 -0-0 1 -.names Pinreg_33_ Pdata_34_ n1 n1448 -00- 1 --01 1 -0-0 1 -.names Pinreg_41_ Pdata_33_ n1 n1449 -00- 1 --01 1 -0-0 1 -.names Pinreg_49_ Pdata_32_ n1 n1450 -00- 1 --01 1 -0-0 1 -.names Pcount_2_ n923 n1664 n1451 -0-1 1 --11 1 -.names Pcount_1_ n925 n1665 n1452 -0-1 1 --11 1 -.names Pcount_3_ Pcount_2_ Pcount_1_ n1666 n1453 ---00 1 -11-0 1 -.names Pencrypt_mode_0_ Pencrypt_0_ n1 n1454 -00- 1 -0-1 1 --00 1 -.names n201 n209 n207 n914 n1457 -1--- 1 --0-- 1 ---0- 1 ----1 1 -.names n220 n795 n911 n1189 n1458 -1-0- 1 --10- 1 -1--1 1 --1-1 1 -.names n561 n914 n1184 n1188 n1459 -0-0- 1 --00- 1 -0--1 1 --0-1 1 -.names n261 n266 n269 n835 n1464 -1--- 1 --1-- 1 ---0- 1 ----1 1 -.names n357 n588 n591 n1465 -1-- 1 --0- 1 ---0 1 -.names n355 n588 n1217 n1466 -0-- 1 --0- 1 ---1 1 -.names n585 n1220 n340 n357 n1468 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n1158 n355 n337 n1470 -1-- 1 --1- 1 ---1 1 -.names n326 n357 n420 n1470 n1469 -0--1 1 --1-1 1 ---11 1 -.names n357 n588 n591 n1471 -0-- 1 --0- 1 ---0 1 -.names Pdata_25_ n1675 n1472 -01 1 -10 1 -.names n392 n432 n445 n1473 -1-- 1 --0- 1 ---0 1 -.names n432 n447 n445 n1475 -0-- 1 --0- 1 ---0 1 -.names n1475 n401 n375 n452 n1474 -11-- 1 -1-1- 1 -1--1 1 -.names n369 n444 n570 n1476 -1-- 1 --0- 1 ---1 1 -.names n407 Pdata_17_ n1477 -01 1 -10 1 -.names n422 Pdata_9_ n1478 -01 1 -10 1 -.names Pdata_1_ n1678 n1479 -01 1 -10 1 -.names n475 n476 n1480 -0- 1 --1 1 -.names n459 n1257 n1482 -0- 1 --1 1 -.names n496 Pdata_26_ n1483 -01 1 -10 1 -.names n526 n647 n654 n1486 -1-- 1 --0- 1 ---1 1 -.names n511 n546 n1484 -1- 1 --0 1 -.names n525 n522 n1487 -1- 1 --1 1 -.names n542 n549 n647 n1488 -1-- 1 --0- 1 ---0 1 -.names n522 n658 n1163 n1274 n1489 -1-0- 1 --10- 1 -1--1 1 --1-1 1 -.names n529 n549 n1265 n1275 n1490 -1-0- 1 --00- 1 -1--1 1 --0-1 1 -.names n648 n1163 n1165 n1493 -1-- 1 --1- 1 ---0 1 -.names n513 n517 n526 n1493 n1492 --1-1 1 -0-11 1 -.names n533 Pdata_18_ n1494 -01 1 -10 1 -.names n648 n647 n1275 n1495 -1-- 1 --1- 1 ---1 1 -.names n529 n510 n654 n1497 -1-- 1 --1- 1 ---1 1 -.names n1497 n508 n1275 n1496 -11- 1 -1-1 1 -.names n655 n658 n1163 n1272 n1499 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names Pdata_10_ n1680 n1500 -01 1 -10 1 -.names n392 n432 n434 n449 n1502 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names n575 Pdata_27_ n1503 -01 1 -10 1 -.names Pdata_19_ n1684 n1504 -01 1 -10 1 -.names n633 Pdata_11_ n1505 -01 1 -10 1 -.names n525 n646 n1272 n1275 n1506 -11-- 1 --10- 1 -1--1 1 ---01 1 -.names Pdata_3_ n1688 n1507 -01 1 -10 1 -.names n510 n549 n1270 n1508 -0-- 1 --0- 1 ---1 1 -.names n510 n515 n546 n1509 -1-- 1 --0- 1 ---0 1 -.names n661 Pdata_28_ n1510 -01 1 -10 1 -.names n680 Pdata_20_ n1511 -01 1 -10 1 -.names n693 Pdata_12_ n1512 -01 1 -10 1 -.names n469 n475 n1248 n1514 -10- 1 -1-1 1 --11 1 -.names n701 Pdata_4_ n1515 -01 1 -10 1 -.names n742 n752 n755 n1318 n1516 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names Pdata_29_ n1690 n1517 -01 1 -10 1 -.names n772 n777 n1300 n1520 -0-- 1 --0- 1 ---1 1 -.names n775 n1323 n1520 n1518 -1-1 1 --01 1 -.names Pdata_21_ n1692 n1521 -01 1 -10 1 -.names n228 n786 n914 n1187 n1522 -0-1- 1 --11- 1 -0--0 1 --1-0 1 -.names Pdata_13_ n1695 n1524 -01 1 -10 1 -.names n729 n730 n738 n724 n1525 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n826 Pdata_30_ n1528 -01 1 -10 1 -.names n836 Pdata_22_ n1529 -01 1 -10 1 -.names n460 n491 n846 n1248 n1530 -0--1 1 --0-1 1 ---11 1 -.names n470 n475 n495 n675 n1532 -1-1- 1 --11- 1 -1--0 1 --1-0 1 -.names Pdata_14_ n1703 n1533 -01 1 -10 1 -.names n629 n1166 n1298 n1324 n1534 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names n766 n872 n876 n1167 n1537 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names Pdata_31_ n1709 n1538 -01 1 -10 1 -.names Pdata_23_ n1711 n1539 -01 1 -10 1 -.names n900 Pdata_15_ n1540 -01 1 -10 1 -.names Pdata_7_ n1714 n1541 -01 1 -10 1 -.names Pinreg_48_ Pinreg_27_ n1356 n1357 n1542 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pinreg_35_ Pinreg_27_ n1356 n1357 n1543 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_43_ Pinreg_35_ n1356 n1357 n1544 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_51_ Pinreg_43_ n1356 n1357 n1545 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_51_ Pdata_in_2_ n1356 n1357 n1546 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pinreg_2_ Pdata_in_2_ n1356 n1357 n1547 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_10_ Pinreg_2_ n1356 n1357 n1548 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_18_ Pinreg_10_ n1356 n1357 n1549 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_26_ Pinreg_18_ n1356 n1357 n1550 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_34_ Pinreg_26_ n1356 n1357 n1551 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_42_ Pinreg_34_ n1356 n1357 n1552 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_50_ Pinreg_42_ n1356 n1357 n1553 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_50_ Pdata_in_1_ n1356 n1357 n1554 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pinreg_1_ Pdata_in_1_ n1356 n1357 n1555 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_9_ Pinreg_1_ n1356 n1357 n1556 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_17_ Pinreg_9_ n1356 n1357 n1557 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_25_ Pinreg_17_ n1356 n1357 n1558 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_33_ Pinreg_25_ n1356 n1357 n1559 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_41_ Pinreg_33_ n1356 n1357 n1560 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_49_ Pinreg_41_ n1356 n1357 n1561 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_49_ Pdata_in_0_ n1356 n1357 n1562 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pinreg_0_ Pdata_in_0_ n1356 n1357 n1563 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_8_ Pinreg_0_ n1356 n1357 n1564 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_16_ Pinreg_8_ n1356 n1357 n1565 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_24_ Pinreg_16_ n1356 n1357 n1566 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_32_ Pinreg_24_ n1356 n1357 n1567 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_40_ Pinreg_32_ n1356 n1357 n1568 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_48_ Pinreg_40_ n1356 n1357 n1569 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_54_ Pdata_in_3_ n1356 n1357 n1570 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pinreg_3_ Pdata_in_3_ n1356 n1357 n1571 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_11_ Pinreg_3_ n1356 n1357 n1572 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_19_ Pinreg_11_ n1356 n1357 n1573 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_19_ Pdata_in_4_ n1356 n1357 n1574 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pinreg_4_ Pdata_in_4_ n1356 n1357 n1575 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_12_ Pinreg_4_ n1356 n1357 n1576 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_20_ Pinreg_12_ n1356 n1357 n1577 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_28_ Pinreg_20_ n1356 n1357 n1578 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_36_ Pinreg_28_ n1356 n1357 n1579 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_44_ Pinreg_36_ n1356 n1357 n1580 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_52_ Pinreg_44_ n1356 n1357 n1581 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_52_ Pdata_in_5_ n1356 n1357 n1582 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pinreg_5_ Pdata_in_5_ n1356 n1357 n1583 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_13_ Pinreg_5_ n1356 n1357 n1584 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_21_ Pinreg_13_ n1356 n1357 n1585 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_29_ Pinreg_21_ n1356 n1357 n1586 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_37_ Pinreg_29_ n1356 n1357 n1587 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_45_ Pinreg_37_ n1356 n1357 n1588 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_53_ Pinreg_45_ n1356 n1357 n1589 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_53_ Pdata_in_6_ n1356 n1357 n1590 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pinreg_6_ Pdata_in_6_ n1356 n1357 n1591 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_14_ Pinreg_6_ n1356 n1357 n1592 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_22_ Pinreg_14_ n1356 n1357 n1593 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_30_ Pinreg_22_ n1356 n1357 n1594 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_38_ Pinreg_30_ n1356 n1357 n1595 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_46_ Pinreg_38_ n1356 n1357 n1596 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names Pinreg_54_ Pinreg_46_ n1356 n1357 n1597 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n264 n269 n292 n1598 -1-- 1 --1- 1 ---0 1 -.names n270 n273 n835 n1369 n1599 -1-0- 1 --10- 1 ---00 1 -.names n243 n254 n262 n269 n1600 -00-- 1 --01- 1 --0-1 1 -.names n254 n274 n835 n1602 -00- 1 -0-1 1 -.names n317 n355 n1158 n1375 n1604 ---00 1 -000- 1 -.names n317 n326 n1158 n1218 n1605 -011- 1 --110 1 -.names n458 n477 n851 n1250 n1607 -01-- 1 --111 1 -.names n460 n477 n851 n1252 n1609 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names n508 n1275 n647 n1610 -1-- 1 --1- 1 ---1 1 -.names n512 n526 n549 n647 n1611 -1--0 1 --010 1 -.names n647 n1163 n1272 n1496 n1614 -1--0 1 -101- 1 -.names n545 n647 n1165 n1265 n1615 -10-- 1 --011 1 -.names n230 n789 n1155 n1616 -11- 1 -1-1 1 --10 1 -.names n914 n1187 n228 n220 n1617 -11-- 1 -1-11 1 -.names n201 n227 n231 n1378 n1619 -1--0 1 -111- 1 -.names n201 n915 n1616 n1620 -001 1 -.names n583 n1218 n1622 -1- 1 --0 1 -.names n326 n587 n1158 n1622 n1621 --10- 1 -1-01 1 -.names n344 n357 n1158 n1623 -1-- 1 --1- 1 ---0 1 -.names n604 n1300 n1325 n1624 -0-- 1 --0- 1 ---1 1 -.names n647 n1265 n1303 n1625 -1-- 1 --0- 1 ---1 1 -.names n1163 n1164 n1272 n1382 n1626 -0--0 1 -011- 1 -.names n508 n647 n1163 n1303 n1627 -1--- 1 --0-- 1 ---0- 1 ----0 1 -.names n477 n847 n849 n1628 -0-- 1 --1- 1 ---0 1 -.names n375 n432 n1629 -10 1 -.names n375 n403 n438 n1630 -01- 1 -0-1 1 -.names n570 n572 n1629 n1630 n1631 -0--- 1 --0-- 1 ---1- 1 ----1 1 -.names n851 n849 n1633 -11 1 -.names n477 n852 n1252 n1633 n1632 -0--1 1 -011- 1 -.names n722 n751 n802 n895 n1635 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names n777 n779 n862 n1325 n1636 --1-0 1 -1-10 1 -.names n862 n1167 n1325 n1638 -0-- 1 --0- 1 ---0 1 -.names n766 n774 n1166 n1295 n1639 -010- 1 -0-01 1 -.names n1166 n1324 n1640 -0- 1 --1 1 -.names n201 n227 n1186 n1522 n1641 -1--0 1 -111- 1 -.names n201 n561 n788 n790 n1642 -01-- 1 -0-1- 1 -0--1 1 -.names n751 n814 n1318 n1525 n1643 -1--0 1 -110- 1 -.names n751 n802 n1318 n1668 n1645 -0--0 1 -010- 1 -.names n266 n263 n1647 -11 1 -.names n261 n266 n269 n1648 -00- 1 --01 1 -.names n274 n281 n835 n1201 n1649 ---01 1 -110- 1 -.names n472 n477 n1246 n1530 n1651 --1-0 1 -011- 1 -.names n477 n493 n848 n850 n1653 -00-- 1 -0-1- 1 -0--1 1 -.names n629 n775 n776 n1654 -0-- 1 --1- 1 ---1 1 -.names n729 n742 n749 n756 n1655 -1--- 1 --1-- 1 ---1- 1 ----0 1 -.names n742 n887 n898 n1340 n1656 -11-1 1 -1-01 1 -.names n738 n740 n1657 -0- 1 --1 1 -.names n738 n803 n814 n817 n1658 -0--1 1 -011- 1 -.names n201 n1184 n1185 n1659 -01- 1 -1-1 1 --11 1 -.names n207 n1155 n1659 n1660 -10- 1 -1-1 1 --11 1 -.names n201 n1385 n1386 n1663 -10- 1 -0-0 1 --00 1 -.names Pcount_2_ Pcount_1_ Pcount_0_ n924 n1664 -1--- 1 --0-- 1 ---0- 1 ----1 1 -.names Pcount_1_ Pcount_0_ n924 n1665 -1-- 1 --0- 1 ---1 1 -.names Pcount_3_ Pcount_2_ Pcount_1_ n1666 -1-0 1 --10 1 -.names n722 n724 n1668 -0- 1 --1 1 -.names n202 n210 n215 n223 n225 n229 n1458 n1459 n1669 -11110011 1 -.names n331 n424 n1468 n1604 n1605 n1672 -11100 1 -.names n331 n333 n350 n353 n358 n360 n421 n1220 n1675 -11101011 1 -.names n386 n400 n433 n437 n439 n443 n448 n451 n1678 -11111011 1 -.names n516 n521 n541 n1499 n1614 n1615 n1680 -111100 1 -.names n202 n208 n210 n554 n558 n560 n1619 n1620 n1683 -0------- 1 --1------ 1 ---0----- 1 ----0---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names n331 n336 n350 n590 n593 n1221 n1621 n1623 n1684 -11101101 1 -.names n519 n534 n541 n1506 n1626 n1627 n1688 -111101 1 -.names n741 n757 n760 n1321 n1341 n1516 n1690 -101111 1 -.names n599 n618 n1326 n1518 n1636 n1638 n1639 n1640 n1692 -11110101 1 -.names n199 n210 n794 n1329 n1641 n1642 n1695 -111100 1 -.names n714 n809 n810 n813 n816 n901 n1643 n1645 n1698 -0------- 1 --0------ 1 ---0----- 1 ----1---- 1 -----1--- 1 ------0-- 1 -------1- 1 --------1 1 -.names n262 n264 n269 n1172 n1702 -1001 1 -.names n466 n668 n1254 n1532 n1651 n1653 n1703 -111100 1 -.names n635 n858 n859 n860 n864 n1323 n1326 n1534 n1706 -0------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------0- 1 --------0 1 -.names n608 n618 n879 n880 n1326 n1537 n1709 -111011 1 -.names n804 n889 n1321 n1655 n1656 n1657 n1658 n1668 n1711 -11110101 1 -.names n202 n910 n913 n917 n1329 n1663 n1714 -101111 1 -.names Pdata_2_ n1683 n1717 -01 1 -10 1 -.names Pdata_5_ n1698 n1718 -01 1 -10 1 -.names Pdata_6_ n1706 n1719 -01 1 -10 1 -.end diff --git a/fpga_flow/benchmarks/Blif/MCNC_big20/diffeq.blif b/fpga_flow/benchmarks/Blif/MCNC_big20/diffeq.blif deleted file mode 100644 index da068664d..000000000 --- a/fpga_flow/benchmarks/Blif/MCNC_big20/diffeq.blif +++ /dev/null @@ -1,3834 +0,0 @@ -.model TOP -.inputs PCLK PRESET Pdxport_0_0_ Pdxport_1_1_ Pdxport_2_2_ Pdxport_3_3_ \ -Pdxport_4_4_ Pdxport_5_5_ Pdxport_6_6_ Pdxport_7_7_ Pdxport_8_8_ Pdxport_9_9_ \ -Pdxport_10_10_ Pdxport_11_11_ Paport_0_0_ Paport_1_1_ Paport_2_2_ Paport_3_3_ \ -Paport_4_4_ Paport_5_5_ Paport_6_6_ Paport_7_7_ Paport_8_8_ Paport_9_9_ \ -Paport_10_10_ Paport_11_11_ Preset_0_0_ Pready_0_0_ -.outputs PDN Pnext_0_0_ Pover_0_0_ -.latch N_N4053 N_N4054 re PCLK 2 -.latch N_N3744 N_N3745 re PCLK 2 -.latch N_N3406 N_N4119 re PCLK 2 -.latch N_N3825 N_N3826 re PCLK 2 -.latch N_N3817 N_N3818 re PCLK 2 -.latch N_N3078 N_N3345 re PCLK 2 -.latch N_N3409 N_N3924 re PCLK 2 -.latch N_N3814 N_N3815 re PCLK 2 -.latch N_N3690 N_N3691 re PCLK 2 -.latch N_N2972 N_N3157 re PCLK 2 -.latch N_N3123 N_N3872 re PCLK 2 -.latch N_N3787 N_N3788 re PCLK 2 -.latch N_N3374 N_N3375 re PCLK 2 -.latch N_N3136 N_N3143 re PCLK 2 -.latch N_N3847 N_N4197 re PCLK 2 -.latch N_N3668 N_N3843 re PCLK 2 -.latch N_N3425 N_N3426 re PCLK 2 -.latch N_N3506 N_N4118 re PCLK 2 -.latch N_N3579 N_N3580 re PCLK 2 -.latch N_N3174 N_N3175 re PCLK 2 -.latch N_N3070 N_N3071 re PCLK 2 -.latch N_N3349 N_N3808 re PCLK 2 -.latch N_N3227 N_N3923 re PCLK 2 -.latch N_N3249 N_N3250 re PCLK 2 -.latch N_N3486 N_N4221 re PCLK 2 -.latch N_N3068 N_N3069 re PCLK 2 -.latch N_N3216 N_N3464 re PCLK 2 -.latch N_N3454 N_N3535 re PCLK 2 -.latch N_N2952 N_N3871 re PCLK 2 -.latch N_N3247 N_N3248 re PCLK 2 -.latch N_N3334 N_N4180 re PCLK 2 -.latch N_N3310 N_N3311 re PCLK 2 -.latch N_N3215 N_N3442 re PCLK 2 -.latch N_N3980 N_N3981 re PCLK 2 -.latch N_N3413 N_N3842 re PCLK 2 -.latch N_N3104 N_N3105 re PCLK 2 -.latch N_N2997 N_N4133 re PCLK 2 -.latch N_N3661 N_N4117 re PCLK 2 -.latch N_N2973 N_N3420 re PCLK 2 -.latch N_N3640 N_N3761 re PCLK 2 -.latch N_N3009 N_N3062 re PCLK 2 -.latch N_N3615 N_N4071 re PCLK 2 -.latch N_N3859 N_N4227 re PCLK 2 -.latch N_N3129 N_N3807 re PCLK 2 -.latch N_N3222 N_N4145 re PCLK 2 -.latch N_N3652 N_N3922 re PCLK 2 -.latch N_N2992 N_N3516 re PCLK 2 -.latch N_N3488 N_N3489 re PCLK 2 -.latch N_N4029 N_N4030 re PCLK 2 -.latch N_N3050 N_N3540 re PCLK 2 -.latch N_N3487 N_N3513 re PCLK 2 -.latch N_N2963 N_N4083 re PCLK 2 -.latch N_N3431 N_N3841 re PCLK 2 -.latch N_N3717 N_N4018 re PCLK 2 -.latch N_N3801 N_N3971 re PCLK 2 -.latch N_N4231 N_N4232 re PCLK 2 -.latch N_N3276 N_N4246 re PCLK 2 -.latch N_N3173 N_N3806 re PCLK 2 -.latch N_N3723 N_N3992 re PCLK 2 -.latch N_N4085 N_N4086 re PCLK 2 -.latch N_N4229 N_N4230 re PCLK 2 -.latch N_N3599 N_N4212 re PCLK 2 -.latch N_N3005 Pnext_0_0_ re PCLK 2 -.latch N_N3162 N_N3626 re PCLK 2 -.latch N_N3106 N_N3965 re PCLK 2 -.latch N_N3570 N_N3890 re PCLK 2 -.latch N_N3287 NDN3_11 re PCLK 2 -.latch N_N3231 NDN5_10 re PCLK 2 -.latch N_N3785 N_N3786 re PCLK 2 -.latch N_N3596 N_N4171 re PCLK 2 -.latch N_N3063 NDN5_16 re PCLK 2 -.latch N_N3798 N_N3799 re PCLK 2 -.latch N_N3315 N_N3844 re PCLK 2 -.latch N_N3152 N_N3196 re PCLK 2 -.latch N_N3277 N_N4126 re PCLK 2 -.latch N_N3400 N_N3681 re PCLK 2 -.latch N_N3049 N_N3679 re PCLK 2 -.latch N_N3339 N_N3340 re PCLK 2 -.latch N_N3969 N_N4116 re PCLK 2 -.latch N_N3316 N_N3810 re PCLK 2 -.latch N_N2974 N_N3235 re PCLK 2 -.latch N_N3053 N_N3283 re PCLK 2 -.latch N_N3399 N_N3716 re PCLK 2 -.latch N_N3048 N_N3701 re PCLK 2 -.latch N_N3524 N_N3921 re PCLK 2 -.latch N_N3558 N_N3625 re PCLK 2 -.latch N_N3115 N_N3751 re PCLK 2 -.latch N_N3456 N_N3736 re PCLK 2 -.latch N_N3772 N_N3870 re PCLK 2 -.latch N_N4023 N_N4024 re PCLK 2 -.latch N_N3804 N_N3876 re PCLK 2 -.latch N_N3133 N_N3840 re PCLK 2 -.latch N_N4020 N_N4021 re PCLK 2 -.latch N_N3189 N_N3932 re PCLK 2 -.latch N_N3811 NLC1_2 re PCLK 2 -.latch N_N3132 N_N3805 re PCLK 2 -.latch N_N3259 N_N3700 re PCLK 2 -.latch N_N3015 N_N3735 re PCLK 2 -.latch N_N2987 NLak3_2 re PCLK 2 -.latch N_N3465 NLak3_9 re PCLK 2 -.latch N_N3003 N_N3906 re PCLK 2 -.latch N_N2953 N_N3388 re PCLK 2 -.latch N_N4007 N_N4057 re PCLK 2 -.latch N_N2969 N_N3011 re PCLK 2 -.latch N_N3037 N_N3346 re PCLK 2 -.latch N_N2998 N_N3677 re PCLK 2 -.latch N_N3146 N_N4165 re PCLK 2 -.latch N_N3010 N_N4080 re PCLK 2 -.latch N_N3372 N_N3373 re PCLK 2 -.latch N_N3616 N_N3709 re PCLK 2 -.latch N_N3483 N_N4206 re PCLK 2 -.latch N_N3119 N_N3324 re PCLK 2 -.latch N_N3325 N_N3575 re PCLK 2 -.latch N_N3058 N_N4159 re PCLK 2 -.latch N_N3638 NAK5_2 re PCLK 2 -.latch N_N3915 N_N3916 re PCLK 2 -.latch N_N3666 N_N3743 re PCLK 2 -.latch N_N3052 N_N4242 re PCLK 2 -.latch N_N2966 N_N3312 re PCLK 2 -.latch N_N3595 N_N3733 re PCLK 2 -.latch N_N3664 N_N3774 re PCLK 2 -.latch N_N3332 N_N4214 re PCLK 2 -.latch N_N2965 N_N3294 re PCLK 2 -.latch N_N3795 N_N3796 re PCLK 2 -.latch N_N3523 N_N3574 re PCLK 2 -.latch N_N3653 N_N3791 re PCLK 2 -.latch N_N3266 N_N3480 re PCLK 2 -.latch N_N3914 N_N4243 re PCLK 2 -.latch N_N3263 N_N3940 re PCLK 2 -.latch N_N3241 N_N3509 re PCLK 2 -.latch N_N3913 N_N4015 re PCLK 2 -.latch N_N2988 N_N2989 re PCLK 2 -.latch N_N2955 N_N3919 re PCLK 2 -.latch N_N3389 N_N3578 re PCLK 2 -.latch N_N3240 N_N3529 re PCLK 2 -.latch N_N4174 N_N4222 re PCLK 2 -.latch N_N3909 N_N3910 re PCLK 2 -.latch N_N2956 N_N3868 re PCLK 2 -.latch N_N3946 N_N3947 re PCLK 2 -.latch N_N3390 N_N4181 re PCLK 2 -.latch N_N3695 N_N3793 re PCLK 2 -.latch N_N3004 N_N3822 re PCLK 2 -.latch N_N3153 N_N3813 re PCLK 2 -.latch N_N4113 N_N4114 re PCLK 2 -.latch N_N3156 N_N4134 re PCLK 2 -.latch N_N2961 N_N3866 re PCLK 2 -.latch N_N4217 N_N4218 re PCLK 2 -.latch N_N3589 N_N3939 re PCLK 2 -.latch N_N3614 N_N3776 re PCLK 2 -.latch N_N3145 N_N3387 re PCLK 2 -.latch N_N3051 N_N4194 re PCLK 2 -.latch N_N3014 N_N3821 re PCLK 2 -.latch N_N3705 N_N3882 re PCLK 2 -.latch N_N4166 N_N4167 re PCLK 2 -.latch N_N3201 N_N3800 re PCLK 2 -.latch N_N3192 N_N4237 re PCLK 2 -.latch N_N3416 N_N3417 re PCLK 2 -.latch N_N3592 N_N3918 re PCLK 2 -.latch N_N3437 N_N4158 re PCLK 2 -.latch N_N2976 N_N3630 re PCLK 2 -.latch N_N3103 N_N3344 re PCLK 2 -.latch N_N3206 N_N4072 re PCLK 2 -.latch N_N3273 N_N3274 re PCLK 2 -.latch N_N3472 N_N3473 re PCLK 2 -.latch N_N3511 N_N4205 re PCLK 2 -.latch N_N4110 N_N4111 re PCLK 2 -.latch N_N3008 N_N3680 re PCLK 2 -.latch N_N3432 N_N3838 re PCLK 2 -.latch N_N2984 N_N3262 re PCLK 2 -.latch N_N4098 N_N4099 re PCLK 2 -.latch N_N2975 N_N3607 re PCLK 2 -.latch N_N3320 N_N3323 re PCLK 2 -.latch N_N3611 N_N3612 re PCLK 2 -.latch N_N4032 N_N4079 re PCLK 2 -.latch N_N3620 PDN re PCLK 2 -.latch N_N3102 N_N3457 re PCLK 2 -.latch N_N3155 N_N3445 re PCLK 2 -.latch N_N3559 N_N3794 re PCLK 2 -.latch N_N3662 N_N3663 re PCLK 2 -.latch N_N3007 N_N3715 re PCLK 2 -.latch N_N4038 N_N4039 re PCLK 2 -.latch N_N2983 N_N3280 re PCLK 2 -.latch N_N4238 N_N4239 re PCLK 2 -.latch N_N3987 N_N3988 re PCLK 2 -.latch N_N3172 N_N3433 re PCLK 2 -.latch N_N4074 N_N4075 re PCLK 2 -.latch N_N3038 N_N3468 re PCLK 2 -.latch N_N4044 N_N4045 re PCLK 2 -.latch N_N3481 N_N3482 re PCLK 2 -.latch N_N3086 N_N3832 re PCLK 2 -.latch N_N3210 N_N3304 re PCLK 2 -.latch N_N3040 N_N3750 re PCLK 2 -.latch N_N3633 N_N3634 re PCLK 2 -.latch N_N3177 N_N3293 re PCLK 2 -.latch N_N3658 N_N3659 re PCLK 2 -.latch N_N3671 N_N4252 re PCLK 2 -.latch N_N3449 N_N3912 re PCLK 2 -.latch N_N3117 N_N3862 re PCLK 2 -.latch N_N3209 N_N3221 re PCLK 2 -.latch N_N3113 N_N3875 re PCLK 2 -.latch N_N3602 N_N3949 re PCLK 2 -.latch N_N3322 N_N3908 re PCLK 2 -.latch N_N3710 N_N3711 re PCLK 2 -.latch N_N3244 N_N3931 re PCLK 2 -.latch N_N2996 N_N3469 re PCLK 2 -.latch N_N3435 N_N3436 re PCLK 2 -.latch N_N3027 N_N3974 re PCLK 2 -.latch N_N3904 N_N3905 re PCLK 2 -.latch N_N3740 N_N3741 re PCLK 2 -.latch N_N3165 N_N3369 re PCLK 2 -.latch N_N3144 N_N3164 re PCLK 2 -.latch N_N3499 N_N3500 re PCLK 2 -.latch N_N3200 N_N3996 re PCLK 2 -.latch N_N2979 N_N3356 re PCLK 2 -.latch N_N3147 N_N4093 re PCLK 2 -.latch N_N3061 Pover_0_0_ re PCLK 2 -.latch N_N3586 N_N4224 re PCLK 2 -.latch N_N2980 N_N4027 re PCLK 2 -.latch N_N3305 NDN1_4 re PCLK 2 -.latch N_N2978 N_N3384 re PCLK 2 -.latch N_N3093 N_N4036 re PCLK 2 -.latch N_N3967 N_N3968 re PCLK 2 -.latch N_N3190 N_N4183 re PCLK 2 -.latch N_N3542 NGFDN_3 re PCLK 2 -.latch N_N4089 N_N4090 re PCLK 2 -.latch N_N3091 N_N4004 re PCLK 2 -.latch N_N3204 N_N3205 re PCLK 2 -.latch N_N3191 N_N4136 re PCLK 2 -.latch N_N3101 N_N3303 re PCLK 2 -.latch N_N3352 N_N3533 re PCLK 2 -.latch N_N3335 N_N3336 re PCLK 2 -.latch N_N2964 N_N3961 re PCLK 2 -.latch N_N3057 N_N3331 re PCLK 2 -.latch N_N3202 N_N3203 re PCLK 2 -.latch N_N4028 N_N4236 re PCLK 2 -.latch N_N3321 N_N3884 re PCLK 2 -.latch N_N3366 N_N3367 re PCLK 2 -.latch N_N4139 N_N4140 re PCLK 2 -.latch N_N3476 NDN2_2 re PCLK 2 -.latch N_N4105 N_N4106 re PCLK 2 -.latch N_N3028 N_N3100 re PCLK 2 -.latch N_N3720 N_N4193 re PCLK 2 -.latch N_N3034 N_N3470 re PCLK 2 -.latch N_N3423 N_N3424 re PCLK 2 -.latch N_N3958 N_N3959 re PCLK 2 -.latch N_N3318 N_N3393 re PCLK 2 -.latch N_N4041 N_N4042 re PCLK 2 -.latch N_N3075 N_N3188 re PCLK 2 -.latch N_N4094 N_N4095 re PCLK 2 -.latch N_N3956 N_N3957 re PCLK 2 -.latch N_N3401 N_N3517 re PCLK 2 -.latch N_N4046 N_N4047 re PCLK 2 -.latch N_N2977 N_N3081 re PCLK 2 -.latch N_N2962 N_N3541 re PCLK 2 -.latch N_N3087 N_N4177 re PCLK 2 -.latch N_N3530 NDN3_3 re PCLK 2 -.latch N_N3479 N_N4176 re PCLK 2 -.latch N_N3584 N_N3585 re PCLK 2 -.latch N_N3752 NDN3_8 re PCLK 2 -.latch N_N3503 N_N4209 re PCLK 2 -.latch N_N3823 N_N3824 re PCLK 2 -.latch N_N3130 N_N4208 re PCLK 2 -.latch N_N3895 N_N4120 re PCLK 2 -.latch N_N3707 N_N3708 re PCLK 2 -.latch N_N3941 N_N4220 re PCLK 2 -.latch N_N4254 N_N3999 re PCLK 2 -.latch N_N3314 N_N4223 re PCLK 2 -.latch N_N3178 N_N3179 re PCLK 2 -.latch N_N3963 N_N4179 re PCLK 2 -.latch N_N3474 N_N3475 re PCLK 2 -.latch N_N3194 N_N4132 re PCLK 2 -.latch N_N2958 N_N4182 re PCLK 2 -.latch N_N3163 N_N3797 re PCLK 2 -.latch N_N3213 N_N3214 re PCLK 2 -.latch N_N3193 N_N4070 re PCLK 2 -.latch N_N2957 N_N4135 re PCLK 2 -.latch N_N3042 NLD3_9 re PCLK 2 -.latch N_N3160 NDN5_2 re PCLK 2 -.latch N_N3041 NDN5_3 re PCLK 2 -.latch N_N3284 N_N3778 re PCLK 2 -.latch N_N3739 NDN5_4 re PCLK 2 -.latch N_N3211 N_N3212 re PCLK 2 -.latch N_N3348 NDN5_5 re PCLK 2 -.latch N_N3016 NDN5_6 re PCLK 2 -.latch N_N3538 NDN5_7 re PCLK 2 -.latch N_N3029 NDN5_8 re PCLK 2 -.latch N_N3338 N_N4073 re PCLK 2 -.latch N_N3458 NDN5_9 re PCLK 2 -.latch N_N3618 NEN5_9 re PCLK 2 -.latch N_N3683 N_N3684 re PCLK 2 -.latch N_N4055 N_N4056 re PCLK 2 -.latch N_N3712 N_N3713 re PCLK 2 -.latch N_N3828 N_N3829 re PCLK 2 -.latch N_N47 N_N4060 re PCLK 2 -.latch N_N46 NSr3_2 re PCLK 2 -.latch N_N45 NSr5_2 re PCLK 2 -.latch N_N44 NSr5_3 re PCLK 2 -.latch N_N43 N_N3462 re PCLK 2 -.latch N_N42 N_N3460 re PCLK 2 -.latch N_N41 NSr5_4 re PCLK 2 -.latch N_N40 NSr3_9 re PCLK 2 -.latch N_N39 NSr5_5 re PCLK 2 -.latch N_N38 NSr5_7 re PCLK 2 -.latch N_N37 NSr5_8 re PCLK 2 -.latch N_N36 N_N3998 re PCLK 2 -.names PRESET n410 n3 -01 1 -.names N_N3460 n411 n412 n2 -101 1 -.names n3 n2 N_N3999 N_N4254 -11- 1 -1-1 1 -.names PRESET n458 n463 N_N4239 n4 -1-1- 1 --11- 1 -1--0 1 --1-0 1 -.names n4 N_N4238 -0 1 -.names n464 N_N4232 n5 -1- 1 --0 1 -.names n5 N_N4231 -0 1 -.names n464 N_N4230 n6 -1- 1 --0 1 -.names n6 N_N4229 -0 1 -.names n464 N_N4218 n7 -1- 1 --0 1 -.names n7 N_N4217 -0 1 -.names PRESET n1235 n8 -01 1 -.names N_N4222 n8 N_N4174 -11 1 -.names n591 n1194 n1237 N_N4167 n9 -1-0- 1 --00- 1 -1--0 1 --0-0 1 -.names n9 N_N4166 -0 1 -.names PRESET n463 n594 N_N4140 n11 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n11 N_N4139 -0 1 -.names n597 n599 n1194 N_N4114 n12 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n12 N_N4113 -0 1 -.names n607 n609 n610 N_N4111 n13 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n13 N_N4110 -0 1 -.names n464 N_N4106 n14 -1- 1 --0 1 -.names n14 N_N4105 -0 1 -.names PRESET n463 n613 N_N4099 n15 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n15 N_N4098 -0 1 -.names PRESET n463 n618 N_N4095 n16 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n16 N_N4094 -0 1 -.names n464 N_N4090 n17 -1- 1 --0 1 -.names n17 N_N4089 -0 1 -.names PRESET n463 n621 N_N4086 n18 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n18 N_N4085 -0 1 -.names n624 n625 n626 N_N4075 n19 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n19 N_N4074 -0 1 -.names Paport_5_5_ n464 n466 N_N4056 n22 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n22 N_N4055 -0 1 -.names Paport_7_7_ n464 n466 N_N4054 n23 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n23 N_N4053 -0 1 -.names n635 n636 n637 N_N4047 n24 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n24 N_N4046 -0 1 -.names n626 n635 n636 N_N4045 n25 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n25 N_N4044 -0 1 -.names n638 n639 n640 N_N4042 n26 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n26 N_N4041 -0 1 -.names n638 n639 n641 N_N4039 n27 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n27 N_N4038 -0 1 -.names n597 n599 n722 N_N4079 n28 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n28 N_N4032 -0 1 -.names n724 n725 n726 N_N4030 n29 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n29 N_N4029 -0 1 -.names n641 n727 n729 N_N4236 n30 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n30 N_N4028 -0 1 -.names n624 n625 n730 N_N4024 n31 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n31 N_N4023 -0 1 -.names n624 n625 n731 N_N4021 n32 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n32 N_N4020 -0 1 -.names Pdxport_2_2_ n464 n466 N_N4057 n34 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n34 N_N4007 -0 1 -.names n773 n775 n776 N_N3988 n35 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n35 N_N3987 -0 1 -.names n607 n610 N_N3981 n778 n36 -11-- 1 --10- 1 -1--1 1 ---01 1 -.names n36 N_N3980 -0 1 -.names n635 n636 n781 N_N4116 n38 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n38 N_N3969 -0 1 -.names n638 n639 n781 N_N3968 n39 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n39 N_N3967 -0 1 -.names Pdxport_5_5_ n464 n466 N_N4179 n40 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n40 N_N3963 -0 1 -.names n624 n625 n781 N_N3959 n41 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n41 N_N3958 -0 1 -.names n624 n625 n783 N_N3957 n42 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n42 N_N3956 -0 1 -.names n591 n784 n1237 N_N3947 n43 -1-0- 1 --10- 1 -1--0 1 --1-0 1 -.names n43 N_N3946 -0 1 -.names Pdxport_3_3_ n464 n466 N_N4220 n44 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n44 N_N3941 -0 1 -.names Paport_0_0_ n464 n466 N_N3916 n46 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n46 N_N3915 -0 1 -.names Paport_6_6_ n464 n466 N_N4243 n47 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n47 N_N3914 -0 1 -.names Paport_8_8_ n464 n466 N_N4015 n48 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n48 N_N3913 -0 1 -.names n727 n729 n793 N_N3910 n49 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n49 N_N3909 -0 1 -.names N_N3905 n8 N_N3904 -11 1 -.names Pdxport_1_1_ n464 n466 N_N4120 n51 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n51 N_N3895 -0 1 -.names n885 n886 n887 N_N4197 n56 -1-1- 1 --11- 1 -1--0 1 --1-0 1 -.names n56 N_N3847 -0 1 -.names n591 n888 n1237 N_N3829 n57 -1-0- 1 --10- 1 -1--0 1 --1-0 1 -.names n57 N_N3828 -0 1 -.names n591 n889 n1237 N_N3826 n58 -1-0- 1 --10- 1 -1--0 1 --1-0 1 -.names n58 N_N3825 -0 1 -.names n624 n625 n640 N_N3824 n59 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n59 N_N3823 -0 1 -.names Paport_9_9_ n464 n466 N_N3818 n60 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n60 N_N3817 -0 1 -.names n591 n892 n1237 N_N3815 n61 -1-0- 1 --10- 1 -1--0 1 --1-0 1 -.names n61 N_N3814 -0 1 -.names n464 N_N3876 n62 -1- 1 --0 1 -.names n62 N_N3804 -0 1 -.names PRESET n463 n895 N_N3971 n63 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n63 N_N3801 -0 1 -.names n638 n639 n730 N_N3799 n64 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n64 N_N3798 -0 1 -.names n591 n899 n1237 N_N3796 n65 -1-0- 1 --10- 1 -1--0 1 --1-0 1 -.names n65 N_N3795 -0 1 -.names n591 n900 n1237 N_N3788 n66 -1-0- 1 --10- 1 -1--0 1 --1-0 1 -.names n66 N_N3787 -0 1 -.names n464 N_N3786 n67 -1- 1 --0 1 -.names n67 N_N3785 -0 1 -.names n635 n636 n726 N_N3870 n68 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n68 N_N3772 -0 1 -.names PRESET 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--1-0 1 ---10 1 -.names n752 N_N3862 n754 -01 1 -.names n752 N_N3862 n754 N_N4243 n756 -0-1- 1 --11- 1 -0--0 1 --1-0 1 -.names n756 N_N3489 n759 -11 1 -.names n756 N_N3489 n759 N_N4054 n760 -1-1- 1 --11- 1 -1--0 1 --1-0 1 -.names n760 N_N3908 n761 -00 1 -.names n760 n761 N_N4015 N_N3908 n764 -01-- 1 -0-1- 1 --1-0 1 ---10 1 -.names n764 N_N3513 n765 -10 1 -.names n764 n765 N_N3818 N_N3513 n767 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n767 N_N3882 N_N3884 n769 -0-1 1 --01 1 -.names n767 N_N3882 n771 -00 1 -.names PRESET n1254 n773 -1- 1 --0 1 -.names PRESET n1254 n775 -1- 1 --1 1 -.names n412 N_N4083 n776 -0- 1 --0 1 -.names n679 n1287 n778 -01 1 -10 1 -.names n412 N_N4027 n781 -0- 1 --0 1 -.names n412 N_N3996 n783 -0- 1 --0 1 -.names n575 n1197 n784 -01 1 -10 1 -.names n412 N_N3965 n793 -0- 1 --0 1 -.names N_N3445 n356 n385 N_N4095 n802 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names N_N3905 n372 n390 N_N4237 n803 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n360 n802 n803 N_N3663 n800 -111- 1 --110 1 -.names N_N3468 n356 n385 N_N3470 n806 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n360 n372 N_N4194 N_N3473 n807 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names N_N3469 n390 n806 n807 n804 -0-11 1 --111 1 -.names n356 n372 N_N4070 N_N4140 n810 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names N_N4073 N_N4072 n385 n390 n811 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n360 n810 n811 N_N4071 n808 -111- 1 --110 1 -.names n356 n360 N_N3810 N_N3293 n814 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names N_N3426 n372 n385 N_N4242 n815 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names N_N3294 n390 n814 n815 n812 -0-11 1 --111 1 -.names n356 n372 N_N4132 N_N4136 n818 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names N_N4134 N_N4135 n385 n390 n819 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n360 n818 n819 N_N4133 n816 -111- 1 --110 1 -.names N_N3312 n356 n390 N_N3844 n822 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n360 n372 N_N4206 N_N3988 n823 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names N_N3375 n385 n822 n823 n820 -0-11 1 --111 1 -.names n356 n372 N_N4179 N_N4183 n826 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names N_N4181 N_N4182 n385 n390 n827 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n360 n826 n827 N_N4180 n824 -111- 1 --110 1 -.names n356 n360 N_N3890 N_N3323 n830 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names N_N3691 n372 n385 N_N4165 n831 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names N_N3324 n390 n830 n831 n828 -0-11 1 --111 1 -.names n356 n372 N_N4220 N_N4224 n834 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names N_N4222 N_N4223 n385 n390 n835 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n360 n834 n835 N_N4221 n832 -111- 1 --110 1 -.names n356 n360 N_N4086 N_N3344 n838 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n372 n390 N_N4057 N_N3346 n839 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names N_N3345 n385 n838 n839 n836 -0-11 1 --111 1 -.names n356 n385 N_N3500 N_N2989 n842 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names N_N3708 n372 n390 N_N4120 n843 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n360 n842 n843 N_N3175 n840 -111- 1 --110 1 -.names n356 n360 N_N3971 N_N3387 n846 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n372 n385 N_N3906 N_N3745 n847 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n390 n846 n847 N_N3388 n844 -111- 1 --110 1 -.names n844 N_N3965 n849 -1- 1 --0 1 -.names n840 n849 n848 -11 1 -.names n840 n849 n848 N_N4027 n850 -1-1- 1 --11- 1 -1--0 1 --1-0 1 -.names n850 N_N3992 n852 -10 1 -.names n836 n850 n852 N_N3992 n854 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n854 N_N3996 n855 -10 1 -.names n832 n854 n855 N_N3996 n857 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n857 N_N4018 n858 -10 1 -.names n828 n857 n858 N_N4018 n860 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n860 N_N3974 n861 -10 1 -.names n824 n860 n861 N_N3974 n863 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n863 N_N4083 n864 -10 1 -.names n820 n863 n864 N_N4083 n866 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n866 N_N3949 n867 -10 1 -.names n816 n866 n867 N_N3949 n869 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n869 N_N4145 n870 -10 1 -.names n812 n869 n870 N_N4145 n872 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n872 N_N3912 n873 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---00 1 -.names NLD3_9 n929 N_N3791 n927 -01- 1 --10 1 -.names n351 n460 N_N3843 N_N3105 n931 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names NLD3_9 N_N3489 n931 n930 -0-1 1 --01 1 -.names n684 n1290 n932 -01 1 -10 1 -.names n698 n1291 n934 -01 1 -10 1 -.names n710 n1292 n935 -01 1 -10 1 -.names n691 n1293 n939 -01 1 -10 1 -.names PRESET NLD3_9 n944 -1- 1 --1 1 -.names NSr5_8 PRESET n946 -1- 1 --1 1 -.names n676 n1294 n947 -01 1 -10 1 -.names n866 n1205 n950 -01 1 -10 1 -.names PDN NLC1_2 n951 -00 1 -.names n363 n413 N_N4212 n1271 n955 -1-0- 1 --10- 1 -1--1 1 --1-1 1 -.names n955 n429 n880 n954 -11- 1 -1-1 1 -.names PRESET n355 n956 -1- 1 --0 1 -.names n367 n413 N_N4171 n1271 n958 -1-0- 1 --10- 1 -1--1 1 --1-1 1 -.names n958 n437 n880 n957 -11- 1 -1-1 1 -.names n351 n460 N_N3918 N_N3356 n961 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names NLD3_9 n961 N_N3709 n960 -01- 1 --10 1 -.names NLD3_9 n351 N_N3939 N_N3677 n963 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names n460 n963 N_N3741 n962 -11- 1 --10 1 -.names NLD3_9 n351 N_N4224 N_N3442 n965 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names n460 n965 N_N4106 n964 -11- 1 --10 1 -.names n412 N_N3949 n966 -0- 1 --0 1 -.names n350 N_N3890 n1273 N_N3750 n971 -0-1- 1 --01- 1 -0--0 1 --0-0 1 -.names PRESET n460 n969 -1- 1 --1 1 -.names NLD3_9 n351 N_N4118 N_N3179 n980 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names n460 n980 N_N4232 n979 -11- 1 --10 1 -.names NLD3_9 N_N3336 n351 N_N4209 n983 -0-0- 1 --00- 1 -0--0 1 --0-0 1 -.names n460 n983 N_N3373 n981 -11- 1 --10 1 -.names n351 n460 N_N3500 N_N3331 n987 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names NLD3_9 n987 N_N3464 n985 -01- 1 --10 1 -.names n706 n1295 n991 -01 1 -10 1 -.names n350 N_N4176 N_N4079 n1273 n994 -0-0- 1 --00- 1 -0--1 1 --0-1 1 -.names n1206 n1207 n997 -01 1 -10 1 -.names n872 n1208 n999 -01 1 -10 1 -.names n475 n602 N_N4237 N_N4236 n1001 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n475 n602 N_N4208 N_N4209 n1003 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n720 n645 n1005 -11 1 -.names n642 n1005 n645 n720 n1006 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n585 n1209 n1049 -01 1 -10 1 -.names n1184 n1210 n1050 -11 1 -00 1 -.names NLD3_9 n351 N_N3940 N_N4111 n1052 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names n460 n1052 N_N4218 n1051 -11- 1 --10 1 -.names n1186 n1211 n1058 -11 1 -00 1 -.names n1188 n1212 n1059 -11 1 -00 1 -.names NSr5_7 PRESET n1061 -1- 1 --1 1 -.names NLD3_9 n351 N_N3923 N_N3475 n1063 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names n460 n1063 N_N4230 n1062 -11- 1 --10 1 -.names n869 n1213 n1064 -01 1 -10 1 -.names n350 N_N3800 N_N3908 n1273 n1066 -0-0- 1 --00- 1 -0--1 1 --0-1 1 -.names n854 n1214 n1067 -01 1 -10 1 -.names n350 N_N4136 n1273 N_N3516 n1072 -0-1- 1 --01- 1 -0--0 1 --0-0 1 -.names n350 N_N4183 n1273 N_N3420 n1073 -0-1- 1 --01- 1 -0--0 1 --0-0 1 -.names n394 n413 N_N3369 n1271 n1082 -1-0- 1 --10- 1 -1--1 1 --1-1 1 -.names n1082 n418 n880 n1081 -11- 1 -1-1 1 -.names n350 N_N3862 N_N3813 n1273 n1086 -00-- 1 --00- 1 -0--1 1 ---01 1 -.names n398 n413 N_N4093 n1271 n1091 -1-0- 1 --10- 1 -1--1 1 --1-1 1 -.names n1091 n425 n880 n1090 -11- 1 -1-1 1 -.names n350 N_N4208 N_N4158 n1273 n1100 -0-0- 1 --00- 1 -0--1 1 --0-1 1 -.names n350 N_N3807 N_N3713 n1273 n1102 -0-0- 1 --00- 1 -0--1 1 --0-1 1 -.names n351 n460 N_N3872 N_N3248 n1105 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names NLD3_9 n1105 N_N3761 n1104 -01- 1 --10 1 -.names N_N3965 n844 n1108 -01 1 -10 1 -.names n353 n384 n416 N_N4036 n1115 -01-- 1 -0-1- 1 --1-0 1 ---10 1 -.names n353 n380 n416 N_N4004 n1116 -01-- 1 -0-1- 1 --1-0 1 ---10 1 -.names n351 n460 N_N4177 N_N3011 n1118 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names NLD3_9 N_N3884 n1118 n1117 -0-1 1 --01 1 -.names n406 n413 N_N3283 n1271 n1129 -1-0- 1 --10- 1 -1--1 1 --1-1 1 -.names N_N3283 n421 n1128 -01 1 -10 1 -.names n1129 n1128 n880 n1127 -11- 1 -1-1 1 -.names n350 N_N3470 N_N3821 n1273 n1138 -0-0- 1 --00- 1 -0--1 1 --0-1 1 -.names n860 n1216 n1141 -01 1 -10 1 -.names n840 n1275 n1162 -01 1 -10 1 -.names n353 n376 n416 N_N3961 n1172 -01-- 1 -0-1- 1 --1-0 1 ---10 1 -.names n863 n1217 n1173 -01 1 -10 1 -.names n350 N_N3868 N_N3832 n1273 n1178 -0-0- 1 --00- 1 -0--1 1 --0-1 1 -.names n350 N_N3794 N_N3919 n1273 n1179 -00-- 1 --00- 1 -0--1 1 ---01 1 -.names n350 N_N3871 N_N3214 n1273 n1180 -0-0- 1 --00- 1 -0--1 1 --0-1 1 -.names n72 NSr3_9 N_N3542 -10 1 -.names PRESET Pover_0_0_ NGFDN_3 NDN3_11 n1181 -010- 1 -01-1 1 -.names N_N3542 n1181 N_N3061 -1- 1 --1 1 -.names PRESET Pnext_0_0_ NLD3_9 NDN5_16 n1182 -010- 1 -01-1 1 -.names PRESET n1227 N_N3042 -01 1 -.names n1182 N_N3042 N_N3005 -1- 1 --1 1 -.names N_N3283 n421 n1183 -1- 1 --1 1 -.names n536 n493 n1184 -01 1 -10 1 -.names n550 n499 n1185 -01 1 -10 1 -.names n549 n487 n1186 -01 1 -10 1 -.names n564 n502 n1187 -01 1 -10 1 -.names n563 n484 n1188 -01 1 -10 1 -.names n518 n505 n1189 -01 1 -10 1 -.names n505 n481 n518 n1192 -111 1 -.names n1192 n508 n1191 -01 1 -10 1 -.names n584 n586 n1195 -01 1 -10 1 -.names n473 n1284 n1196 -01 1 -10 1 -.names n1195 n1196 n1194 -01 1 -10 1 -.names n573 n514 n1197 -01 1 -10 1 -.names n804 N_N4197 n1198 -11 1 -00 1 -.names n542 n519 n1199 -01 1 -10 1 -.names n553 n554 n1200 -01 1 -10 1 -.names n567 n568 n1201 -01 1 -10 1 -.names n576 n577 n1202 -01 1 -10 1 -.names n836 N_N3992 n1203 -11 1 -00 1 -.names n828 N_N4018 n1204 -11 1 -00 1 -.names n816 N_N3949 n1205 -11 1 -00 1 -.names n665 n668 n1206 -01 1 -10 1 -.names n604 n600 n1207 -1- 1 --1 1 -.names n808 N_N3912 n1208 -11 1 -00 1 -.names n581 n511 n1209 -01 1 -10 1 -.names n533 n537 n1210 -01 1 -10 1 -.names n544 n546 n1211 -01 1 -10 1 -.names n559 n560 n1212 -01 1 -10 1 -.names n812 N_N4145 n1213 -11 1 -00 1 -.names n832 N_N3996 n1214 -11 1 -00 1 -.names n824 N_N3974 n1216 -11 1 -00 1 -.names n820 N_N4083 n1217 -11 1 -00 1 -.names n2 N_N4214 n1221 -10 1 -.names n425 n422 n418 n437 n433 n429 n1226 -111111 1 -.names NLD3_9 NDN5_9 n1227 -01 1 -.names PDN NDN1_4 n1228 -0- 1 --1 1 -.names Preset_0_0_ NLC1_2 N_N3998 n1230 -00- 1 -0-1 1 --11 1 -.names NDN3_3 NSr3_2 n1233 -00 1 -.names NDN2_2 n149 n1235 -1- 1 --1 1 -.names PRESET n476 n1237 -01 1 -.names n508 n1192 n1238 -11 1 -.names NSr5_8 NDN5_8 n1242 -1- 1 --1 1 -.names NSr5_4 NDN5_4 n1245 -1- 1 --1 1 -.names NSr5_7 NDN5_7 n1247 -1- 1 --1 1 -.names NSr5_3 NDN5_3 n1250 -1- 1 --1 1 -.names NSr5_5 NDN5_5 n1252 -1- 1 --1 1 -.names NSr5_2 NDN5_2 n1254 -1- 1 --1 1 -.names n412 n414 n1271 -0- 1 --1 1 -.names PRESET NLD3_9 n1273 -1- 1 --0 1 -.names n849 N_N4027 n1275 -11 1 -00 1 -.names PRESET n879 N_N4227 n1283 n1276 -1--1 1 --1-1 1 ---01 1 -.names n1276 N_N3859 -0 1 -.names n371 n367 n363 n384 n380 n376 n1277 -111111 1 -.names n881 n886 N_N4227 n1283 -0-- 1 --1- 1 ---1 1 -.names n1061 N_N3538 -0 1 -.names n946 N_N3029 -0 1 -.names n1238 n478 n1284 -11 1 -.names n490 n522 n1285 -1- 1 --1 1 -.names n642 n645 n1286 -01 1 -10 1 -.names n653 n656 n1287 -01 1 -10 1 -.names n712 n713 n1288 -01 1 -10 1 -.names n525 n1285 n1289 -01 1 -10 1 -.names n681 n682 n1290 -01 1 -10 1 -.names n695 n696 n1291 -01 1 -10 1 -.names n648 n650 n1292 -01 1 -10 1 -.names n688 n689 n1293 -01 1 -10 1 -.names n659 n662 n1294 -01 1 -10 1 -.names n702 n703 n1295 -01 1 -10 1 -.names n1001 n1003 n1296 -01 1 -10 1 -.names N_N3999 n358 n389 n394 n398 n402 n406 n1277 n1297 -01111111 1 -.names Preset_0_0_ n951 n1299 -01 1 -.end diff --git a/fpga_flow/benchmarks/Blif/MCNC_big20/dsip.blif b/fpga_flow/benchmarks/Blif/MCNC_big20/dsip.blif deleted file mode 100644 index e930b183b..000000000 --- a/fpga_flow/benchmarks/Blif/MCNC_big20/dsip.blif +++ /dev/null @@ -1,8753 +0,0 @@ -## inputs 228 -## outputs 197 -## latches 224 -## initial 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -.model dsip.sim -.inputs key[254] key[253] key[252] key[251] key[250] key[249] key[248] key[246] key[245] key[244] -.inputs key[243] key[242] key[241] key[240] key[238] key[237] key[235] key[234] key[233] key[232] -.inputs key[230] key[229] key[228] key[227] key[226] key[225] key[224] key[222] key[221] key[220] -.inputs key[219] key[218] key[217] key[216] key[214] key[213] key[212] key[211] key[210] key[209] -.inputs key[208] key[206] key[205] key[204] key[203] key[202] key[201] key[200] key[198] key[197] -.inputs key[196] key[195] key[194] key[193] key[192] key[190] key[189] key[188] key[187] key[186] -.inputs key[185] key[184] key[182] key[181] key[180] key[179] key[178] key[177] key[176] key[174] -.inputs key[173] key[172] key[171] key[170] key[169] key[168] key[166] key[165] key[164] key[163] -.inputs key[162] key[161] key[160] key[158] key[157] key[156] key[155] key[154] key[153] key[152] -.inputs key[150] key[149] key[148] key[147] key[146] key[145] key[144] key[142] key[141] key[140] -.inputs key[139] key[138] key[137] key[136] key[134] key[133] key[132] key[131] key[130] key[129] -.inputs key[128] key[126] key[125] key[124] key[123] key[122] key[121] key[120] key[118] key[117] -.inputs key[116] key[115] key[114] key[113] key[112] key[110] key[109] key[107] key[106] key[105] -.inputs key[104] key[102] key[101] key[100] key[99] key[98] key[97] key[96] key[94] key[93] -.inputs key[92] key[91] key[90] key[89] key[88] key[86] key[85] key[84] key[83] key[82] -.inputs key[81] key[80] key[78] key[77] key[76] key[75] key[74] key[73] key[72] key[70] -.inputs key[69] key[68] key[67] key[66] key[65] key[64] key[62] key[61] key[60] key[59] -.inputs key[58] key[57] key[56] key[54] key[53] key[52] key[51] key[50] key[49] key[48] -.inputs key[46] key[45] key[44] key[43] key[42] key[41] key[40] key[38] key[37] key[36] -.inputs key[35] key[34] key[33] key[32] key[30] key[29] key[28] key[27] key[26] key[25] -.inputs key[24] key[22] key[21] key[20] key[19] key[18] key[17] key[16] key[14] key[13] -.inputs key[12] key[11] key[10] key[9] key[8] key[6] key[5] key[4] key[3] key[2] -.inputs key[1] key[0] count[3] count[2] count[1] count[0] encrypt[0] start[0] -.outputs KSi[191] KSi[190] KSi[189] KSi[188] KSi[187] KSi[186] KSi[185] KSi[184] KSi[183] KSi[182] -.outputs KSi[181] KSi[180] KSi[179] KSi[178] KSi[177] KSi[176] KSi[175] KSi[174] KSi[173] KSi[172] -.outputs KSi[171] KSi[170] KSi[169] KSi[168] KSi[167] KSi[166] KSi[165] KSi[164] KSi[163] KSi[162] -.outputs KSi[161] KSi[160] KSi[159] KSi[158] KSi[157] KSi[156] KSi[155] KSi[154] KSi[153] KSi[152] -.outputs KSi[151] KSi[150] KSi[149] KSi[148] KSi[147] KSi[146] KSi[145] KSi[144] KSi[143] KSi[142] -.outputs KSi[141] KSi[140] KSi[139] KSi[138] KSi[137] KSi[136] KSi[135] KSi[134] KSi[133] KSi[132] -.outputs KSi[131] KSi[130] KSi[129] KSi[128] KSi[127] KSi[126] KSi[125] KSi[124] KSi[123] KSi[122] -.outputs KSi[121] KSi[120] KSi[119] KSi[118] KSi[117] KSi[116] KSi[115] KSi[114] KSi[113] KSi[112] -.outputs KSi[111] KSi[110] KSi[109] KSi[108] KSi[107] KSi[106] KSi[105] KSi[104] KSi[103] KSi[102] -.outputs KSi[101] KSi[100] KSi[99] KSi[98] KSi[97] KSi[96] KSi[95] KSi[94] KSi[93] KSi[92] -.outputs KSi[91] KSi[90] KSi[89] KSi[88] KSi[87] KSi[86] KSi[85] KSi[84] KSi[83] KSi[82] -.outputs KSi[81] KSi[80] KSi[79] KSi[78] KSi[77] KSi[76] KSi[75] KSi[74] KSi[73] KSi[72] -.outputs KSi[71] KSi[70] KSi[69] KSi[68] KSi[67] KSi[66] KSi[65] KSi[64] KSi[63] KSi[62] -.outputs KSi[61] KSi[60] KSi[59] KSi[58] KSi[57] KSi[56] KSi[55] KSi[54] KSi[53] KSi[52] -.outputs KSi[51] KSi[50] KSi[49] KSi[48] KSi[47] KSi[46] KSi[45] KSi[44] KSi[43] KSi[42] -.outputs KSi[41] KSi[40] KSi[39] KSi[38] KSi[37] KSi[36] KSi[35] KSi[34] KSi[33] KSi[32] -.outputs KSi[31] KSi[30] KSi[29] KSi[28] KSi[27] KSi[26] KSi[25] KSi[24] KSi[23] KSi[22] -.outputs KSi[21] KSi[20] KSi[19] KSi[18] KSi[17] KSi[16] KSi[15] KSi[14] KSi[13] KSi[12] -.outputs KSi[11] KSi[10] KSi[9] KSi[8] KSi[7] KSi[6] KSi[5] KSi[4] KSi[3] KSi[2] -.outputs KSi[1] KSi[0] new_count[3] new_count[2] new_count[1] new_count[0] data_ready[0] -.latch new_C[111] C[111] 0 -.latch new_C[110] C[110] 0 -.latch new_C[109] C[109] 0 -.latch new_C[108] C[108] 0 -.latch new_C[107] C[107] 0 -.latch new_C[106] C[106] 0 -.latch new_C[105] C[105] 0 -.latch new_C[104] C[104] 0 -.latch new_C[103] C[103] 0 -.latch new_C[102] C[102] 0 -.latch new_C[101] C[101] 0 -.latch new_C[100] C[100] 0 -.latch new_C[99] C[99] 0 -.latch new_C[98] C[98] 0 -.latch new_C[97] C[97] 0 -.latch new_C[96] C[96] 0 -.latch new_C[95] C[95] 0 -.latch new_C[94] C[94] 0 -.latch new_C[93] C[93] 0 -.latch new_C[92] C[92] 0 -.latch new_C[91] C[91] 0 -.latch new_C[90] C[90] 0 -.latch new_C[89] C[89] 0 -.latch new_C[88] C[88] 0 -.latch new_C[87] C[87] 0 -.latch new_C[86] C[86] 0 -.latch new_C[85] C[85] 0 -.latch new_C[84] C[84] 0 -.latch new_C[83] C[83] 0 -.latch new_C[82] C[82] 0 -.latch new_C[81] C[81] 0 -.latch new_C[80] C[80] 0 -.latch new_C[79] C[79] 0 -.latch new_C[78] C[78] 0 -.latch new_C[77] C[77] 0 -.latch new_C[76] C[76] 0 -.latch new_C[75] C[75] 0 -.latch new_C[74] C[74] 0 -.latch new_C[73] C[73] 0 -.latch new_C[72] C[72] 0 -.latch new_C[71] C[71] 0 -.latch new_C[70] C[70] 0 -.latch new_C[69] C[69] 0 -.latch new_C[68] C[68] 0 -.latch new_C[67] C[67] 0 -.latch new_C[66] C[66] 0 -.latch new_C[65] C[65] 0 -.latch new_C[64] C[64] 0 -.latch new_C[63] C[63] 0 -.latch new_C[62] C[62] 0 -.latch new_C[61] C[61] 0 -.latch new_C[60] C[60] 0 -.latch new_C[59] C[59] 0 -.latch new_C[58] C[58] 0 -.latch new_C[57] C[57] 0 -.latch new_C[56] C[56] 0 -.latch new_C[55] C[55] 0 -.latch new_C[54] C[54] 0 -.latch new_C[53] C[53] 0 -.latch new_C[52] C[52] 0 -.latch new_C[51] C[51] 0 -.latch new_C[50] C[50] 0 -.latch new_C[49] C[49] 0 -.latch new_C[48] C[48] 0 -.latch new_C[47] C[47] 0 -.latch new_C[46] C[46] 0 -.latch new_C[45] C[45] 0 -.latch new_C[44] C[44] 0 -.latch new_C[43] C[43] 0 -.latch new_C[42] C[42] 0 -.latch new_C[41] C[41] 0 -.latch new_C[40] C[40] 0 -.latch new_C[39] C[39] 0 -.latch new_C[38] C[38] 0 -.latch new_C[37] C[37] 0 -.latch new_C[36] C[36] 0 -.latch new_C[35] C[35] 0 -.latch new_C[34] C[34] 0 -.latch new_C[33] C[33] 0 -.latch new_C[32] C[32] 0 -.latch new_C[31] C[31] 0 -.latch new_C[30] C[30] 0 -.latch new_C[29] C[29] 0 -.latch new_C[28] C[28] 0 -.latch new_C[27] C[27] 0 -.latch new_C[26] C[26] 0 -.latch new_C[25] C[25] 0 -.latch new_C[24] C[24] 0 -.latch new_C[23] C[23] 0 -.latch new_C[22] C[22] 0 -.latch new_C[21] C[21] 0 -.latch new_C[20] C[20] 0 -.latch new_C[19] C[19] 0 -.latch new_C[18] C[18] 0 -.latch new_C[17] C[17] 0 -.latch new_C[16] C[16] 0 -.latch new_C[15] C[15] 0 -.latch new_C[14] C[14] 0 -.latch new_C[13] C[13] 0 -.latch new_C[12] C[12] 0 -.latch new_C[11] C[11] 0 -.latch new_C[10] C[10] 0 -.latch new_C[9] C[9] 0 -.latch new_C[8] C[8] 0 -.latch new_C[7] C[7] 0 -.latch new_C[6] C[6] 0 -.latch new_C[5] C[5] 0 -.latch new_C[4] C[4] 0 -.latch new_C[3] C[3] 0 -.latch new_C[2] C[2] 0 -.latch new_C[1] C[1] 0 -.latch new_C[0] C[0] 0 -.latch new_D[111] D[111] 0 -.latch new_D[110] D[110] 0 -.latch new_D[109] D[109] 0 -.latch new_D[108] D[108] 0 -.latch new_D[107] D[107] 0 -.latch new_D[106] D[106] 0 -.latch new_D[105] D[105] 0 -.latch new_D[104] D[104] 0 -.latch new_D[103] D[103] 0 -.latch new_D[102] D[102] 0 -.latch new_D[101] D[101] 0 -.latch new_D[100] D[100] 0 -.latch new_D[99] D[99] 0 -.latch new_D[98] D[98] 0 -.latch new_D[97] D[97] 0 -.latch new_D[96] D[96] 0 -.latch new_D[95] D[95] 0 -.latch new_D[94] D[94] 0 -.latch new_D[93] D[93] 0 -.latch new_D[92] D[92] 0 -.latch new_D[91] D[91] 0 -.latch new_D[90] D[90] 0 -.latch new_D[89] D[89] 0 -.latch new_D[88] D[88] 0 -.latch new_D[87] D[87] 0 -.latch new_D[86] D[86] 0 -.latch new_D[85] D[85] 0 -.latch new_D[84] D[84] 0 -.latch new_D[83] D[83] 0 -.latch new_D[82] D[82] 0 -.latch new_D[81] D[81] 0 -.latch new_D[80] D[80] 0 -.latch new_D[79] D[79] 0 -.latch new_D[78] D[78] 0 -.latch new_D[77] D[77] 0 -.latch new_D[76] D[76] 0 -.latch new_D[75] D[75] 0 -.latch new_D[74] D[74] 0 -.latch new_D[73] D[73] 0 -.latch new_D[72] D[72] 0 -.latch new_D[71] D[71] 0 -.latch new_D[70] D[70] 0 -.latch new_D[69] D[69] 0 -.latch new_D[68] D[68] 0 -.latch new_D[67] D[67] 0 -.latch new_D[66] D[66] 0 -.latch new_D[65] D[65] 0 -.latch new_D[64] D[64] 0 -.latch new_D[63] D[63] 0 -.latch new_D[62] D[62] 0 -.latch new_D[61] D[61] 0 -.latch new_D[60] D[60] 0 -.latch new_D[59] D[59] 0 -.latch new_D[58] D[58] 0 -.latch new_D[57] D[57] 0 -.latch new_D[56] D[56] 0 -.latch new_D[55] D[55] 0 -.latch new_D[54] D[54] 0 -.latch new_D[53] D[53] 0 -.latch new_D[52] D[52] 0 -.latch new_D[51] D[51] 0 -.latch new_D[50] D[50] 0 -.latch new_D[49] D[49] 0 -.latch new_D[48] D[48] 0 -.latch new_D[47] D[47] 0 -.latch new_D[46] D[46] 0 -.latch new_D[45] D[45] 0 -.latch new_D[44] D[44] 0 -.latch new_D[43] D[43] 0 -.latch new_D[42] D[42] 0 -.latch new_D[41] D[41] 0 -.latch new_D[40] D[40] 0 -.latch new_D[39] D[39] 0 -.latch new_D[38] D[38] 0 -.latch new_D[37] D[37] 0 -.latch new_D[36] D[36] 0 -.latch new_D[35] D[35] 0 -.latch new_D[34] D[34] 0 -.latch new_D[33] D[33] 0 -.latch new_D[32] D[32] 0 -.latch new_D[31] D[31] 0 -.latch new_D[30] D[30] 0 -.latch new_D[29] D[29] 0 -.latch new_D[28] D[28] 0 -.latch new_D[27] D[27] 0 -.latch new_D[26] D[26] 0 -.latch new_D[25] D[25] 0 -.latch new_D[24] D[24] 0 -.latch new_D[23] D[23] 0 -.latch new_D[22] D[22] 0 -.latch new_D[21] D[21] 0 -.latch new_D[20] D[20] 0 -.latch new_D[19] D[19] 0 -.latch new_D[18] D[18] 0 -.latch new_D[17] D[17] 0 -.latch new_D[16] D[16] 0 -.latch new_D[15] D[15] 0 -.latch new_D[14] D[14] 0 -.latch new_D[13] D[13] 0 -.latch new_D[12] D[12] 0 -.latch new_D[11] D[11] 0 -.latch new_D[10] D[10] 0 -.latch new_D[9] D[9] 0 -.latch new_D[8] D[8] 0 -.latch new_D[7] D[7] 0 -.latch new_D[6] D[6] 0 -.latch new_D[5] D[5] 0 -.latch new_D[4] D[4] 0 -.latch new_D[3] D[3] 0 -.latch new_D[2] D[2] 0 -.latch new_D[1] D[1] 0 -.latch new_D[0] D[0] 0 - - -.names D[87] KSi[191] -1 1 -.names D[84] KSi[190] -1 1 -.names D[91] KSi[189] -1 1 -.names D[105] KSi[188] -1 1 -.names D[87] KSi[187] -1 1 -.names D[101] KSi[186] -1 1 -.names D[108] KSi[185] -1 1 -.names D[89] KSi[184] -1 1 -.names D[111] KSi[183] -1 1 -.names D[94] KSi[182] -1 1 -.names D[104] KSi[181] -1 1 -.names D[99] KSi[180] -1 1 -.names D[103] KSi[179] -1 1 -.names D[88] KSi[178] -1 1 -.names D[100] KSi[177] -1 1 -.names D[106] KSi[176] -1 1 -.names D[95] KSi[175] -1 1 -.names D[85] KSi[174] -1 1 -.names D[110] KSi[173] -1 1 -.names D[102] KSi[172] -1 1 -.names D[92] KSi[171] -1 1 -.names D[86] KSi[170] -1 1 -.names D[107] KSi[169] -1 1 -.names D[104] KSi[168] -1 1 -.names D[59] KSi[167] -1 1 -.names D[56] KSi[166] -1 1 -.names D[63] KSi[165] -1 1 -.names D[77] KSi[164] -1 1 -.names D[69] KSi[163] -1 1 -.names D[73] KSi[162] -1 1 -.names D[80] KSi[161] -1 1 -.names D[61] KSi[160] -1 1 -.names D[83] KSi[159] -1 1 -.names D[66] KSi[158] -1 1 -.names D[76] KSi[157] -1 1 -.names D[71] KSi[156] -1 1 -.names D[75] KSi[155] -1 1 -.names D[60] KSi[154] -1 1 -.names D[70] KSi[153] -1 1 -.names D[78] KSi[152] -1 1 -.names D[67] KSi[151] -1 1 -.names D[57] KSi[150] -1 1 -.names D[82] KSi[149] -1 1 -.names D[74] KSi[148] -1 1 -.names D[64] KSi[147] -1 1 -.names D[58] KSi[146] -1 1 -.names D[79] KSi[145] -1 1 -.names D[68] KSi[144] -1 1 -.names D[31] KSi[143] -1 1 -.names D[28] KSi[142] -1 1 -.names D[35] KSi[141] -1 1 -.names D[49] KSi[140] -1 1 -.names D[31] KSi[139] -1 1 -.names D[45] KSi[138] -1 1 -.names D[52] KSi[137] -1 1 -.names D[33] KSi[136] -1 1 -.names D[55] KSi[135] -1 1 -.names D[38] KSi[134] -1 1 -.names D[48] KSi[133] -1 1 -.names D[43] KSi[132] -1 1 -.names D[47] KSi[131] -1 1 -.names D[32] KSi[130] -1 1 -.names D[44] KSi[129] -1 1 -.names D[50] KSi[128] -1 1 -.names D[39] KSi[127] -1 1 -.names D[29] KSi[126] -1 1 -.names D[54] KSi[125] -1 1 -.names D[46] KSi[124] -1 1 -.names D[36] KSi[123] -1 1 -.names D[30] KSi[122] -1 1 -.names D[51] KSi[121] -1 1 -.names D[40] KSi[120] -1 1 -.names D[3] KSi[119] -1 1 -.names D[0] KSi[118] -1 1 -.names D[7] KSi[117] -1 1 -.names D[21] KSi[116] -1 1 -.names D[13] KSi[115] -1 1 -.names D[17] KSi[114] -1 1 -.names D[24] KSi[113] -1 1 -.names D[5] KSi[112] -1 1 -.names D[27] KSi[111] -1 1 -.names D[10] KSi[110] -1 1 -.names D[20] KSi[109] -1 1 -.names D[15] KSi[108] -1 1 -.names D[19] KSi[107] -1 1 -.names D[4] KSi[106] -1 1 -.names D[16] KSi[105] -1 1 -.names D[22] KSi[104] -1 1 -.names D[11] KSi[103] -1 1 -.names D[1] KSi[102] -1 1 -.names D[26] KSi[101] -1 1 -.names D[18] KSi[100] -1 1 -.names D[8] KSi[99] -1 1 -.names D[2] KSi[98] -1 1 -.names D[23] KSi[97] -1 1 -.names D[12] KSi[96] -1 1 -.names C[85] KSi[95] -1 1 -.names C[96] KSi[94] -1 1 -.names C[103] KSi[93] -1 1 -.names C[110] KSi[92] -1 1 -.names C[90] KSi[91] -1 1 -.names C[109] KSi[90] -1 1 -.names C[91] KSi[89] -1 1 -.names C[109] KSi[88] -1 1 -.names C[87] KSi[87] -1 1 -.names C[95] KSi[86] -1 1 -.names C[102] KSi[85] -1 1 -.names C[106] KSi[84] -1 1 -.names C[93] KSi[83] -1 1 -.names C[104] KSi[82] -1 1 -.names C[89] KSi[81] -1 1 -.names C[98] KSi[80] -1 1 -.names C[111] KSi[79] -1 1 -.names C[86] KSi[78] -1 1 -.names C[88] KSi[77] -1 1 -.names C[84] KSi[76] -1 1 -.names C[107] KSi[75] -1 1 -.names C[94] KSi[74] -1 1 -.names C[100] KSi[73] -1 1 -.names C[97] KSi[72] -1 1 -.names C[57] KSi[71] -1 1 -.names C[68] KSi[70] -1 1 -.names C[75] KSi[69] -1 1 -.names C[82] KSi[68] -1 1 -.names C[62] KSi[67] -1 1 -.names C[71] KSi[66] -1 1 -.names C[63] KSi[65] -1 1 -.names C[81] KSi[64] -1 1 -.names C[59] KSi[63] -1 1 -.names C[67] KSi[62] -1 1 -.names C[74] KSi[61] -1 1 -.names C[78] KSi[60] -1 1 -.names C[65] KSi[59] -1 1 -.names C[76] KSi[58] -1 1 -.names C[61] KSi[57] -1 1 -.names C[70] KSi[56] -1 1 -.names C[83] KSi[55] -1 1 -.names C[58] KSi[54] -1 1 -.names C[60] KSi[53] -1 1 -.names C[56] KSi[52] -1 1 -.names C[79] KSi[51] -1 1 -.names C[66] KSi[50] -1 1 -.names C[72] KSi[49] -1 1 -.names C[69] KSi[48] -1 1 -.names C[29] KSi[47] -1 1 -.names C[40] KSi[46] -1 1 -.names C[47] KSi[45] -1 1 -.names C[54] KSi[44] -1 1 -.names C[34] KSi[43] -1 1 -.names C[43] KSi[42] -1 1 -.names C[35] KSi[41] -1 1 -.names C[53] KSi[40] -1 1 -.names C[31] KSi[39] -1 1 -.names C[39] KSi[38] -1 1 -.names C[46] KSi[37] -1 1 -.names C[50] KSi[36] -1 1 -.names C[37] KSi[35] -1 1 -.names C[48] KSi[34] -1 1 -.names C[33] KSi[33] -1 1 -.names C[42] KSi[32] -1 1 -.names C[55] KSi[31] -1 1 -.names C[30] KSi[30] -1 1 -.names C[32] KSi[29] -1 1 -.names C[28] KSi[28] -1 1 -.names C[51] KSi[27] -1 1 -.names C[38] KSi[26] -1 1 -.names C[44] KSi[25] -1 1 -.names C[41] KSi[24] -1 1 -.names C[1] KSi[23] -1 1 -.names C[12] KSi[22] -1 1 -.names C[19] KSi[21] -1 1 -.names C[26] KSi[20] -1 1 -.names C[6] KSi[19] -1 1 -.names C[15] KSi[18] -1 1 -.names C[7] KSi[17] -1 1 -.names C[25] KSi[16] -1 1 -.names C[3] KSi[15] -1 1 -.names C[11] KSi[14] -1 1 -.names C[18] KSi[13] -1 1 -.names C[22] KSi[12] -1 1 -.names C[9] KSi[11] -1 1 -.names C[20] KSi[10] -1 1 -.names C[5] KSi[9] -1 1 -.names C[14] KSi[8] -1 1 -.names C[27] KSi[7] -1 1 -.names C[2] KSi[6] -1 1 -.names C[4] KSi[5] -1 1 -.names C[0] KSi[4] -1 1 -.names C[23] KSi[3] -1 1 -.names C[10] KSi[2] -1 1 -.names C[16] KSi[1] -1 1 -.names C[13] KSi[0] -1 1 -.names count[1] count[0] count[2] [7572] -1-- 1 --1- 1 ---1 1 -.names encrypt[0] count[3] [7572] [17163] -1-- 1 --1- 1 ---1 1 -.names start[0]* [7573] -1 1 -.names encrypt[0]* [7573]* [7574] -1- 1 --1 1 -.names count[2]* [7568] -1 1 -.names I200 I199 [7575] -1- 1 --1 1 -.names [7574]* count[2]* I199 -11 1 -.names [7568]* encrypt[0]* I200 -11 1 -.names count[1]* count[0]* [7576] -1- 1 --1 1 -.names [7576]* [11699] -1 1 -.names count[1]* count[0]* main/$MINUS_4_1/c[0]8.3 -11 1 -.names I206 I205 [7577] -1- 1 --1 1 -.names [7574]* [11699]* I205 -11 1 -.names main/$MINUS_4_1/c[0]8.3* encrypt[0]* I206 -11 1 -.names I208 count[3]* [17165] -1- 1 --1 1 -.names [7577]* [7575]* I208 -11 1 -.names count[3]* [7565] -1 1 -.names count[2]* [7565]* [11699]* [7580] -1-- 1 --1- 1 ---1 1 -.names [7580] [7574] [17167] -1- 1 --1 1 -.names encrypt[0]* [7566] -1 1 -.names start[0]* [7566]* [7581] -1- 1 --1 1 -.names [7581]* [17167]* [17165]* [17163]* new_count[3] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [11699]* [7568]* encrypt[0]* [7573]* [17157] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7572] encrypt[0] [17159] -1- 1 --1 1 -.names count[2]* [7577]* [17161] -1- 1 --1 1 -.names [7581]* [17161]* [17159]* [17157]* new_count[2] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names count[1] count[0] [7571] -1- 1 --1 1 -.names [7571]* [7576]* [7586] -1- 1 --1 1 -.names [7586]* [14444] -1 1 -.names I224 I223 [7587] -1- 1 --1 1 -.names [7586]* [7574]* I223 -11 1 -.names [14444]* encrypt[0]* I224 -11 1 -.names I226 [7581]* new_count[0] -1- 1 --1 1 -.names start[0]* count[0]* I226 -11 1 -.names I229 I228 [194] -1- 1 --1 1 -.names new_count[0]* [7587]* I228 -11 1 -.names start[0]* [7587]* I229 -11 1 -.names [194]* new_count[1] -1 1 -.names C[1]* [7541] -1 1 -.names count[0]* [7569] -1 1 -.names count[1]* [7569]* count[2]* count[3]* [17145] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7572] count[3] [17147] -1- 1 --1 1 -.names [17147]* [17145]* [7580]* [7591] -1-- 1 --1- 1 ---1 1 -.names [7591] [7574] [7600] -1- 1 --1 1 -.names [7600]* [7541]* [2074] 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C[108]* [7608] -1 1 -.names I265 I264 [7609] -1- 1 --1 1 -.names [7608]* [7597]* I264 -11 1 -.names [7598]* [7475]* I265 -11 1 -.names key[235]* [7612] -1 1 -.names [7612]* [7581]* [2071] -11 1 -.names C[111]* [7485] -1 1 -.names I271 I270 [7611] -1- 1 --1 1 -.names [7602]* [7485]* I270 -11 1 -.names [7606]* [7604]* I271 -11 1 -.names [7611] [2071] [7609] [2068] new_C[110] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7485]* [2062] -11 1 -.names C[107]* [7489] -1 1 -.names I277 I276 [7614] -1- 1 --1 1 -.names [7597]* [7489]* I276 -11 1 -.names [7608]* [7598]* I277 -11 1 -.names key[243]* [7617] -1 1 -.names [7617]* [7581]* [2065] -11 1 -.names I282 I281 [7616] -1- 1 --1 1 -.names [7602]* [7473]* I281 -11 1 -.names [7612]* [7604]* I282 -11 1 -.names [7616] [2065] [7614] [2062] new_C[109] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7473]* [2056] -11 1 -.names C[106]* [7480] -1 1 -.names I288 I287 [7619] -1- 1 --1 1 -.names [7597]* [7480]* I287 -11 1 -.names [7598]* [7489]* I288 -11 1 -.names key[251]* [7622] -1 1 -.names [7622]* [7581]* [2059] -11 1 -.names I293 I292 [7621] -1- 1 --1 1 -.names [7602]* [7475]* I292 -11 1 -.names [7617]* [7604]* I293 -11 1 -.names [7621] [2059] [7619] [2056] new_C[108] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7475]* [2050] -11 1 -.names C[105]* [7624] -1 1 -.names I299 I298 [7625] -1- 1 --1 1 -.names [7624]* [7597]* I298 -11 1 -.names [7598]* [7480]* I299 -11 1 -.names key[194]* [7628] -1 1 -.names [7628]* [7581]* [2053] -11 1 -.names I304 I303 [7627] -1- 1 --1 1 -.names [7608]* [7602]* I303 -11 1 -.names [7622]* [7604]* I304 -11 1 -.names [7627] [2053] [7625] [2050] new_C[107] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7608]* [7600]* [2044] -11 1 -.names C[104]* [7482] -1 1 -.names I310 I309 [7630] -1- 1 --1 1 -.names [7597]* [7482]* I309 -11 1 -.names [7624]* [7598]* I310 -11 1 -.names key[202]* [7633] -1 1 -.names [7633]* [7581]* [2047] -11 1 -.names I315 I314 [7632] -1- 1 --1 1 -.names [7602]* [7489]* I314 -11 1 -.names [7628]* [7604]* I315 -11 1 -.names [7632] [2047] [7630] [2044] new_C[106] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7489]* [2038] -11 1 -.names C[103]* [7472] -1 1 -.names I321 I320 [7635] -1- 1 --1 1 -.names [7597]* [7472]* I320 -11 1 -.names [7598]* [7482]* I321 -11 1 -.names key[210]* [7638] -1 1 -.names [7638]* [7581]* [2041] -11 1 -.names I326 I325 [7637] -1- 1 --1 1 -.names [7602]* [7480]* I325 -11 1 -.names [7633]* [7604]* I326 -11 1 -.names [7637] [2041] [7635] [2038] new_C[105] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7480]* [2032] -11 1 -.names C[102]* [7479] -1 1 -.names I332 I331 [7640] -1- 1 --1 1 -.names [7597]* [7479]* I331 -11 1 -.names [7598]* [7472]* I332 -11 1 -.names key[218]* [7643] -1 1 -.names [7643]* [7581]* [2035] -11 1 -.names I337 I336 [7642] -1- 1 --1 1 -.names [7624]* [7602]* I336 -11 1 -.names [7638]* [7604]* I337 -11 1 -.names [7642] [2035] [7640] [2032] new_C[104] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7624]* [7600]* [2026] -11 1 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key[242]* [7660] -1 1 -.names [7660]* [7581]* [2017] -11 1 -.names I370 I369 [7659] -1- 1 --1 1 -.names [7602]* [7479]* I369 -11 1 -.names [7654]* [7604]* I370 -11 1 -.names [7659] [2017] [7657] [2014] new_C[101] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7479]* [2008] -11 1 -.names C[98]* [7484] -1 1 -.names I376 I375 [7662] -1- 1 --1 1 -.names [7597]* [7484]* I375 -11 1 -.names [7656]* [7598]* I376 -11 1 -.names key[250]* [7665] -1 1 -.names [7665]* [7581]* [2011] -11 1 -.names I381 I380 [7664] -1- 1 --1 1 -.names [7645]* [7602]* I380 -11 1 -.names [7660]* [7604]* I381 -11 1 -.names [7664] [2011] [7662] [2008] new_C[100] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7645]* [7600]* [2002] -11 1 -.names C[97]* [7492] -1 1 -.names I387 I386 [7667] -1- 1 --1 1 -.names [7597]* [7492]* I386 -11 1 -.names [7598]* [7484]* I387 -11 1 -.names key[193]* [7670] -1 1 -.names [7670]* [7581]* [2005] -11 1 -.names I392 I391 [7669] -1- 1 --1 1 -.names [7602]* [7491]* I391 -11 1 -.names [7665]* [7604]* I392 -11 1 -.names [7669] [2005] [7667] [2002] new_C[99] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7491]* [1996] -11 1 -.names C[96]* [7471] -1 1 -.names I398 I397 [7672] -1- 1 --1 1 -.names [7597]* [7471]* I397 -11 1 -.names [7598]* [7492]* I398 -11 1 -.names key[201]* [7675] -1 1 -.names [7675]* [7581]* [1999] -11 1 -.names I403 I402 [7674] -1- 1 --1 1 -.names [7656]* [7602]* I402 -11 1 -.names [7670]* [7604]* I403 -11 1 -.names [7674] [1999] [7672] [1996] new_C[98] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7656]* [7600]* [1990] -11 1 -.names C[95]* [7478] -1 1 -.names I409 I408 [7677] -1- 1 --1 1 -.names [7597]* [7478]* I408 -11 1 -.names [7598]* [7471]* I409 -11 1 -.names key[209]* [7680] -1 1 -.names [7680]* [7581]* [1993] -11 1 -.names I414 I413 [7679] -1- 1 --1 1 -.names [7602]* [7484]* I413 -11 1 -.names [7675]* [7604]* I414 -11 1 -.names [7679] [1993] [7677] [1990] new_C[97] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7484]* [1984] -11 1 -.names C[94]* [7490] -1 1 -.names I420 I419 [7682] -1- 1 --1 1 -.names [7597]* [7490]* I419 -11 1 -.names [7598]* [7478]* I420 -11 1 -.names key[217]* [7685] -1 1 -.names [7685]* [7581]* [1987] -11 1 -.names I425 I424 [7684] -1- 1 --1 1 -.names [7602]* [7492]* I424 -11 1 -.names [7680]* [7604]* I425 -11 1 -.names [7684] [1987] [7682] [1984] new_C[96] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7492]* [1978] -11 1 -.names C[93]* [7481] -1 1 -.names I431 I430 [7687] -1- 1 --1 1 -.names [7597]* [7481]* I430 -11 1 -.names [7598]* [7490]* I431 -11 1 -.names key[225]* [7690] -1 1 -.names [7690]* [7581]* [1981] -11 1 -.names I436 I435 [7689] -1- 1 --1 1 -.names [7602]* [7471]* I435 -11 1 -.names [7685]* [7604]* I436 -11 1 -.names [7689] [1981] [7687] [1978] new_C[95] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7471]* [1972] -11 1 -.names C[92]* [7692] -1 1 -.names I442 I441 [7693] -1- 1 --1 1 -.names [7692]* [7597]* I441 -11 1 -.names [7598]* [7481]* I442 -11 1 -.names key[233]* [7696] -1 1 -.names [7696]* [7581]* [1975] -11 1 -.names I447 I446 [7695] -1- 1 --1 1 -.names [7602]* [7478]* I446 -11 1 -.names [7690]* [7604]* I447 -11 1 -.names [7695] [1975] [7693] [1972] new_C[94] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7478]* [1966] -11 1 -.names C[91]* [7476] -1 1 -.names I453 I452 [7698] -1- 1 --1 1 -.names [7597]* [7476]* I452 -11 1 -.names [7692]* [7598]* I453 -11 1 -.names key[241]* [7701] -1 1 -.names [7701]* [7581]* [1969] -11 1 -.names I458 I457 [7700] -1- 1 --1 1 -.names [7602]* [7490]* I457 -11 1 -.names [7696]* [7604]* I458 -11 1 -.names [7700] [1969] [7698] [1966] new_C[93] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7490]* [1960] -11 1 -.names C[90]* [7474] -1 1 -.names I464 I463 [7703] -1- 1 --1 1 -.names [7597]* [7474]* I463 -11 1 -.names [7598]* [7476]* I464 -11 1 -.names key[249]* [7706] -1 1 -.names [7706]* [7581]* [1963] -11 1 -.names I469 I468 [7705] -1- 1 --1 1 -.names [7602]* [7481]* I468 -11 1 -.names [7701]* [7604]* I469 -11 1 -.names [7705] [1963] [7703] [1960] new_C[92] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7481]* [1954] -11 1 -.names C[89]* [7483] -1 1 -.names I475 I474 [7708] -1- 1 --1 1 -.names [7597]* [7483]* I474 -11 1 -.names [7598]* [7474]* I475 -11 1 -.names key[192]* [7711] -1 1 -.names [7711]* [7581]* [1957] -11 1 -.names I480 I479 [7710] -1- 1 --1 1 -.names [7692]* [7602]* I479 -11 1 -.names [7706]* [7604]* I480 -11 1 -.names [7710] [1957] [7708] [1954] new_C[91] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7692]* [7600]* [1948] -11 1 -.names C[88]* [7487] -1 1 -.names I486 I485 [7713] -1- 1 --1 1 -.names [7597]* [7487]* I485 -11 1 -.names [7598]* [7483]* I486 -11 1 -.names key[200]* [7716] -1 1 -.names [7716]* [7581]* [1951] -11 1 -.names I491 I490 [7715] -1- 1 --1 1 -.names [7602]* [7476]* I490 -11 1 -.names [7711]* [7604]* I491 -11 1 -.names [7715] [1951] [7713] [1948] new_C[90] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7476]* [1942] -11 1 -.names C[87]* [7477] -1 1 -.names I497 I496 [7718] -1- 1 --1 1 -.names [7597]* [7477]* I496 -11 1 -.names [7598]* [7487]* I497 -11 1 -.names key[208]* [7721] -1 1 -.names [7721]* [7581]* [1945] -11 1 -.names I502 I501 [7720] -1- 1 --1 1 -.names [7602]* [7474]* I501 -11 1 -.names [7716]* [7604]* I502 -11 1 -.names [7720] [1945] [7718] [1942] new_C[89] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7474]* [1936] -11 1 -.names C[86]* [7486] -1 1 -.names I508 I507 [7723] -1- 1 --1 1 -.names [7597]* [7486]* I507 -11 1 -.names [7598]* [7477]* I508 -11 1 -.names key[216]* [7726] -1 1 -.names [7726]* [7581]* [1939] -11 1 -.names I513 I512 [7725] -1- 1 --1 1 -.names [7602]* [7483]* I512 -11 1 -.names [7721]* [7604]* I513 -11 1 -.names [7725] [1939] [7723] [1936] new_C[88] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7483]* [1930] -11 1 -.names C[85]* [7470] -1 1 -.names I519 I518 [7728] -1- 1 --1 1 -.names [7597]* [7470]* I518 -11 1 -.names [7598]* [7486]* I519 -11 1 -.names key[224]* [7731] -1 1 -.names [7731]* [7581]* [1933] -11 1 -.names I524 I523 [7730] -1- 1 --1 1 -.names [7602]* [7487]* I523 -11 1 -.names [7726]* [7604]* I524 -11 1 -.names [7730] [1933] [7728] [1930] new_C[87] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7487]* [1924] -11 1 -.names C[84]* [7488] -1 1 -.names I530 I529 [7733] -1- 1 --1 1 -.names [7597]* [7488]* I529 -11 1 -.names [7598]* [7470]* I530 -11 1 -.names key[232]* [7736] -1 1 -.names [7736]* [7581]* [1927] -11 1 -.names I535 I534 [7735] -1- 1 --1 1 -.names [7602]* [7477]* I534 -11 1 -.names [7731]* [7604]* I535 -11 1 -.names [7735] [1927] [7733] [1924] new_C[86] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7477]* [1918] -11 1 -.names C[83]* [7509] -1 1 -.names I541 I540 [7738] -1- 1 --1 1 -.names [7597]* [7509]* I540 -11 1 -.names [7598]* [7488]* I541 -11 1 -.names key[240]* [7741] -1 1 -.names [7741]* [7581]* [1921] -11 1 -.names I546 I545 [7740] -1- 1 --1 1 -.names [7602]* [7486]* I545 -11 1 -.names [7736]* [7604]* I546 -11 1 -.names [7740] [1921] [7738] [1918] new_C[85] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7486]* [1912] -11 1 -.names C[82]* [7496] -1 1 -.names I552 I551 [7743] -1- 1 --1 1 -.names [7597]* [7496]* I551 -11 1 -.names [7598]* [7509]* I552 -11 1 -.names key[248]* [7746] -1 1 -.names [7746]* [7581]* [1915] -11 1 -.names I557 I556 [7745] -1- 1 --1 1 -.names [7602]* [7470]* I556 -11 1 -.names [7741]* [7604]* I557 -11 1 -.names [7745] [1915] [7743] [1912] new_C[84] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7470]* [1906] -11 1 -.names C[81]* [7500] -1 1 -.names I563 I562 [7748] -1- 1 --1 1 -.names [7597]* [7500]* I562 -11 1 -.names [7598]* [7496]* I563 -11 1 -.names key[163]* [7751] -1 1 -.names [7751]* [7581]* [1909] -11 1 -.names I568 I567 [7750] -1- 1 --1 1 -.names [7602]* [7488]* I567 -11 1 -.names [7746]* [7604]* I568 -11 1 -.names [7750] [1909] [7748] [1906] new_C[83] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7488]* [1900] -11 1 -.names C[80]* [7753] -1 1 -.names I574 I573 [7754] -1- 1 --1 1 -.names [7753]* [7597]* I573 -11 1 -.names [7598]* [7500]* I574 -11 1 -.names key[171]* [7757] -1 1 -.names [7757]* [7581]* [1903] -11 1 -.names I579 I578 [7756] -1- 1 --1 1 -.names [7602]* [7509]* I578 -11 1 -.names [7751]* [7604]* I579 -11 1 -.names [7756] [1903] [7754] [1900] new_C[82] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7509]* [1894] -11 1 -.names C[79]* [7513] -1 1 -.names I585 I584 [7759] -1- 1 --1 1 -.names [7597]* [7513]* I584 -11 1 -.names [7753]* [7598]* I585 -11 1 -.names key[179]* [7762] -1 1 -.names [7762]* [7581]* [1897] -11 1 -.names I590 I589 [7761] -1- 1 --1 1 -.names [7602]* [7496]* I589 -11 1 -.names [7757]* [7604]* I590 -11 1 -.names [7761] [1897] [7759] [1894] new_C[81] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7496]* [1888] -11 1 -.names C[78]* [7504] -1 1 -.names I596 I595 [7764] -1- 1 --1 1 -.names [7597]* [7504]* I595 -11 1 -.names [7598]* [7513]* I596 -11 1 -.names key[187]* [7767] -1 1 -.names [7767]* [7581]* [1891] -11 1 -.names I601 I600 [7766] -1- 1 --1 1 -.names [7602]* [7500]* I600 -11 1 -.names [7762]* [7604]* I601 -11 1 -.names [7766] [1891] [7764] [1888] new_C[80] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7500]* [1882] -11 1 -.names C[77]* [7769] -1 1 -.names I607 I606 [7770] -1- 1 --1 1 -.names [7769]* [7597]* I606 -11 1 -.names [7598]* [7504]* I607 -11 1 -.names key[130]* [7773] -1 1 -.names [7773]* [7581]* [1885] -11 1 -.names I612 I611 [7772] -1- 1 --1 1 -.names [7753]* [7602]* I611 -11 1 -.names [7767]* [7604]* I612 -11 1 -.names [7772] [1885] [7770] [1882] new_C[79] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7753]* [7600]* [1876] -11 1 -.names C[76]* [7506] -1 1 -.names I618 I617 [7775] -1- 1 --1 1 -.names [7597]* [7506]* I617 -11 1 -.names [7769]* [7598]* I618 -11 1 -.names key[138]* [7778] -1 1 -.names [7778]* [7581]* [1879] -11 1 -.names I623 I622 [7777] -1- 1 --1 1 -.names [7602]* [7513]* I622 -11 1 -.names [7773]* [7604]* I623 -11 1 -.names [7777] [1879] [7775] [1876] new_C[78] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7513]* [1870] -11 1 -.names C[75]* [7495] -1 1 -.names I629 I628 [7780] -1- 1 --1 1 -.names [7597]* [7495]* I628 -11 1 -.names [7598]* [7506]* I629 -11 1 -.names key[146]* [7783] -1 1 -.names [7783]* [7581]* [1873] -11 1 -.names I634 I633 [7782] -1- 1 --1 1 -.names [7602]* [7504]* I633 -11 1 -.names [7778]* [7604]* I634 -11 1 -.names [7782] [1873] [7780] [1870] new_C[77] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7504]* [1864] -11 1 -.names C[74]* [7503] -1 1 -.names I640 I639 [7785] -1- 1 --1 1 -.names [7597]* [7503]* I639 -11 1 -.names [7598]* [7495]* I640 -11 1 -.names key[154]* [7788] -1 1 -.names [7788]* [7581]* [1867] -11 1 -.names I645 I644 [7787] -1- 1 --1 1 -.names [7769]* [7602]* I644 -11 1 -.names [7783]* [7604]* I645 -11 1 -.names [7787] [1867] [7785] [1864] new_C[76] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7769]* [7600]* [1858] -11 1 -.names C[73]* [7790] -1 1 -.names I651 I650 [7791] -1- 1 --1 1 -.names [7790]* [7597]* I650 -11 1 -.names [7598]* [7503]* I651 -11 1 -.names key[162]* [7794] -1 1 -.names [7794]* [7581]* [1861] -11 1 -.names I656 I655 [7793] -1- 1 --1 1 -.names [7602]* [7506]* I655 -11 1 -.names [7788]* [7604]* I656 -11 1 -.names [7793] [1861] [7791] [1858] new_C[75] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7506]* [1852] -11 1 -.names C[72]* [7515] -1 1 -.names I662 I661 [7796] -1- 1 --1 1 -.names [7597]* [7515]* I661 -11 1 -.names [7790]* [7598]* I662 -11 1 -.names key[170]* [7799] -1 1 -.names [7799]* [7581]* [1855] -11 1 -.names I667 I666 [7798] -1- 1 --1 1 -.names [7602]* [7495]* I666 -11 1 -.names [7794]* [7604]* I667 -11 1 -.names [7798] [1855] [7796] [1852] new_C[74] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7495]* [1846] -11 1 -.names C[71]* [7498] -1 1 -.names I673 I672 [7801] -1- 1 --1 1 -.names [7597]* [7498]* I672 -11 1 -.names [7598]* [7515]* I673 -11 1 -.names key[178]* [7804] -1 1 -.names [7804]* [7581]* [1849] -11 1 -.names I678 I677 [7803] -1- 1 --1 1 -.names [7602]* [7503]* I677 -11 1 -.names [7799]* [7604]* I678 -11 1 -.names [7803] [1849] [7801] [1846] new_C[73] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7503]* [1840] -11 1 -.names C[70]* [7508] -1 1 -.names I684 I683 [7806] -1- 1 --1 1 -.names [7597]* [7508]* I683 -11 1 -.names [7598]* [7498]* I684 -11 1 -.names key[186]* [7809] -1 1 -.names [7809]* [7581]* [1843] -11 1 -.names I689 I688 [7808] -1- 1 --1 1 -.names [7790]* [7602]* I688 -11 1 -.names [7804]* [7604]* I689 -11 1 -.names [7808] [1843] [7806] [1840] new_C[72] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7790]* [7600]* [1834] -11 1 -.names C[69]* [7516] -1 1 -.names I695 I694 [7811] -1- 1 --1 1 -.names [7597]* [7516]* I694 -11 1 -.names [7598]* [7508]* I695 -11 1 -.names key[129]* [7814] -1 1 -.names [7814]* [7581]* [1837] -11 1 -.names I700 I699 [7813] -1- 1 --1 1 -.names [7602]* [7515]* I699 -11 1 -.names [7809]* [7604]* I700 -11 1 -.names [7813] [1837] [7811] [1834] new_C[71] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7515]* [1828] -11 1 -.names C[68]* [7494] -1 1 -.names I706 I705 [7816] -1- 1 --1 1 -.names [7597]* [7494]* I705 -11 1 -.names [7598]* [7516]* I706 -11 1 -.names key[137]* [7819] -1 1 -.names [7819]* [7581]* [1831] -11 1 -.names I711 I710 [7818] -1- 1 --1 1 -.names [7602]* [7498]* I710 -11 1 -.names [7814]* [7604]* I711 -11 1 -.names [7818] [1831] [7816] [1828] new_C[70] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7498]* [1822] -11 1 -.names C[67]* [7502] -1 1 -.names I717 I716 [7821] -1- 1 --1 1 -.names [7597]* [7502]* I716 -11 1 -.names [7598]* [7494]* I717 -11 1 -.names key[145]* [7824] -1 1 -.names [7824]* [7581]* [1825] -11 1 -.names I722 I721 [7823] -1- 1 --1 1 -.names [7602]* [7508]* I721 -11 1 -.names [7819]* [7604]* I722 -11 1 -.names [7823] [1825] [7821] [1822] new_C[69] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7508]* [1816] -11 1 -.names C[66]* [7514] -1 1 -.names I728 I727 [7826] -1- 1 --1 1 -.names [7597]* [7514]* I727 -11 1 -.names [7598]* [7502]* I728 -11 1 -.names key[153]* [7829] -1 1 -.names [7829]* [7581]* [1819] -11 1 -.names I733 I732 [7828] -1- 1 --1 1 -.names [7602]* [7516]* I732 -11 1 -.names [7824]* [7604]* I733 -11 1 -.names [7828] [1819] [7826] [1816] new_C[68] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7516]* [1810] -11 1 -.names C[65]* [7505] -1 1 -.names I739 I738 [7831] -1- 1 --1 1 -.names [7597]* [7505]* I738 -11 1 -.names [7598]* [7514]* I739 -11 1 -.names key[161]* [7834] -1 1 -.names [7834]* [7581]* [1813] -11 1 -.names I744 I743 [7833] -1- 1 --1 1 -.names [7602]* [7494]* I743 -11 1 -.names [7829]* [7604]* I744 -11 1 -.names [7833] [1813] [7831] [1810] new_C[67] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7494]* [1804] -11 1 -.names C[64]* [7836] -1 1 -.names I750 I749 [7837] -1- 1 --1 1 -.names [7836]* [7597]* I749 -11 1 -.names [7598]* [7505]* I750 -11 1 -.names key[169]* [7840] -1 1 -.names [7840]* [7581]* [1807] -11 1 -.names I755 I754 [7839] -1- 1 --1 1 -.names [7602]* [7502]* I754 -11 1 -.names [7834]* [7604]* I755 -11 1 -.names [7839] [1807] [7837] [1804] new_C[66] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7502]* [1798] -11 1 -.names C[63]* [7499] -1 1 -.names I761 I760 [7842] -1- 1 --1 1 -.names [7597]* [7499]* I760 -11 1 -.names [7836]* [7598]* I761 -11 1 -.names key[177]* [7845] -1 1 -.names [7845]* [7581]* [1801] -11 1 -.names I766 I765 [7844] -1- 1 --1 1 -.names [7602]* [7514]* I765 -11 1 -.names [7840]* [7604]* I766 -11 1 -.names [7844] [1801] [7842] [1798] new_C[65] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7514]* [1792] -11 1 -.names C[62]* [7497] -1 1 -.names I772 I771 [7847] -1- 1 --1 1 -.names [7597]* [7497]* I771 -11 1 -.names [7598]* [7499]* I772 -11 1 -.names key[185]* [7850] -1 1 -.names [7850]* [7581]* [1795] -11 1 -.names I777 I776 [7849] -1- 1 --1 1 -.names [7602]* [7505]* I776 -11 1 -.names [7845]* [7604]* I777 -11 1 -.names [7849] [1795] [7847] [1792] new_C[64] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7505]* [1786] -11 1 -.names C[61]* [7507] -1 1 -.names I783 I782 [7852] -1- 1 --1 1 -.names [7597]* [7507]* I782 -11 1 -.names [7598]* [7497]* I783 -11 1 -.names key[128]* [7855] -1 1 -.names [7855]* [7581]* [1789] -11 1 -.names I788 I787 [7854] -1- 1 --1 1 -.names [7836]* [7602]* I787 -11 1 -.names [7850]* [7604]* I788 -11 1 -.names [7854] [1789] [7852] [1786] new_C[63] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7836]* [7600]* [1780] -11 1 -.names C[60]* [7511] -1 1 -.names I794 I793 [7857] -1- 1 --1 1 -.names [7597]* [7511]* I793 -11 1 -.names [7598]* [7507]* I794 -11 1 -.names key[136]* [7860] -1 1 -.names [7860]* [7581]* [1783] -11 1 -.names I799 I798 [7859] -1- 1 --1 1 -.names [7602]* [7499]* I798 -11 1 -.names [7855]* [7604]* I799 -11 1 -.names [7859] [1783] [7857] [1780] new_C[62] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7499]* [1774] -11 1 -.names C[59]* [7501] -1 1 -.names I805 I804 [7862] -1- 1 --1 1 -.names [7597]* [7501]* I804 -11 1 -.names [7598]* [7511]* I805 -11 1 -.names key[144]* [7865] -1 1 -.names [7865]* [7581]* [1777] -11 1 -.names I810 I809 [7864] -1- 1 --1 1 -.names [7602]* [7497]* I809 -11 1 -.names [7860]* [7604]* I810 -11 1 -.names [7864] [1777] [7862] [1774] new_C[61] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7497]* [1768] -11 1 -.names C[58]* [7510] -1 1 -.names I816 I815 [7867] -1- 1 --1 1 -.names [7597]* [7510]* I815 -11 1 -.names [7598]* [7501]* I816 -11 1 -.names key[152]* [7870] -1 1 -.names [7870]* [7581]* [1771] -11 1 -.names I821 I820 [7869] -1- 1 --1 1 -.names [7602]* [7507]* I820 -11 1 -.names [7865]* [7604]* I821 -11 1 -.names [7869] [1771] [7867] [1768] new_C[60] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7507]* [1762] -11 1 -.names C[57]* [7493] -1 1 -.names I827 I826 [7872] -1- 1 --1 1 -.names [7597]* [7493]* I826 -11 1 -.names [7598]* [7510]* I827 -11 1 -.names key[160]* [7875] -1 1 -.names [7875]* [7581]* [1765] -11 1 -.names I832 I831 [7874] -1- 1 --1 1 -.names [7602]* [7511]* I831 -11 1 -.names [7870]* [7604]* I832 -11 1 -.names [7874] [1765] [7872] [1762] new_C[59] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7511]* [1756] -11 1 -.names C[56]* [7512] -1 1 -.names I838 I837 [7877] -1- 1 --1 1 -.names [7597]* [7512]* I837 -11 1 -.names [7598]* [7493]* I838 -11 1 -.names key[168]* [7880] -1 1 -.names [7880]* [7581]* [1759] -11 1 -.names I843 I842 [7879] -1- 1 --1 1 -.names [7602]* [7501]* I842 -11 1 -.names [7875]* [7604]* I843 -11 1 -.names [7879] [1759] [7877] [1756] new_C[58] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7501]* [1750] -11 1 -.names C[55]* [7533] -1 1 -.names I849 I848 [7882] -1- 1 --1 1 -.names [7597]* [7533]* I848 -11 1 -.names [7598]* [7512]* I849 -11 1 -.names key[176]* [7885] -1 1 -.names [7885]* [7581]* [1753] -11 1 -.names I854 I853 [7884] -1- 1 --1 1 -.names [7602]* [7510]* I853 -11 1 -.names [7880]* [7604]* I854 -11 1 -.names [7884] [1753] [7882] [1750] new_C[57] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7510]* [1744] -11 1 -.names C[54]* [7520] -1 1 -.names I860 I859 [7887] -1- 1 --1 1 -.names [7597]* [7520]* I859 -11 1 -.names [7598]* [7533]* I860 -11 1 -.names key[184]* [7890] -1 1 -.names [7890]* [7581]* [1747] -11 1 -.names I865 I864 [7889] -1- 1 --1 1 -.names [7602]* [7493]* I864 -11 1 -.names [7885]* [7604]* I865 -11 1 -.names [7889] [1747] [7887] [1744] new_C[56] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7493]* [1738] -11 1 -.names C[53]* [7524] -1 1 -.names I871 I870 [7892] -1- 1 --1 1 -.names [7597]* [7524]* I870 -11 1 -.names [7598]* [7520]* I871 -11 1 -.names key[99]* [7895] -1 1 -.names [7895]* [7581]* [1741] -11 1 -.names I876 I875 [7894] -1- 1 --1 1 -.names [7602]* [7512]* I875 -11 1 -.names [7890]* [7604]* I876 -11 1 -.names [7894] [1741] [7892] [1738] new_C[55] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7512]* [1732] -11 1 -.names C[52]* [7897] -1 1 -.names I882 I881 [7898] -1- 1 --1 1 -.names [7897]* [7597]* I881 -11 1 -.names [7598]* [7524]* I882 -11 1 -.names key[107]* [7901] -1 1 -.names [7901]* [7581]* [1735] -11 1 -.names I887 I886 [7900] -1- 1 --1 1 -.names [7602]* [7533]* I886 -11 1 -.names [7895]* [7604]* I887 -11 1 -.names [7900] [1735] [7898] [1732] new_C[54] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7533]* [1726] -11 1 -.names C[51]* [7537] -1 1 -.names I893 I892 [7903] -1- 1 --1 1 -.names [7597]* [7537]* I892 -11 1 -.names [7897]* [7598]* I893 -11 1 -.names key[115]* [7906] -1 1 -.names [7906]* [7581]* [1729] -11 1 -.names I898 I897 [7905] -1- 1 --1 1 -.names [7602]* [7520]* I897 -11 1 -.names [7901]* [7604]* I898 -11 1 -.names [7905] [1729] [7903] [1726] new_C[53] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7520]* [1720] -11 1 -.names C[50]* [7528] -1 1 -.names I904 I903 [7908] -1- 1 --1 1 -.names [7597]* [7528]* I903 -11 1 -.names [7598]* [7537]* I904 -11 1 -.names key[123]* [7911] -1 1 -.names [7911]* [7581]* [1723] -11 1 -.names I909 I908 [7910] -1- 1 --1 1 -.names [7602]* [7524]* I908 -11 1 -.names [7906]* [7604]* I909 -11 1 -.names [7910] [1723] [7908] [1720] new_C[52] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7524]* [1714] -11 1 -.names C[49]* [7913] -1 1 -.names I915 I914 [7914] -1- 1 --1 1 -.names [7913]* [7597]* I914 -11 1 -.names [7598]* [7528]* I915 -11 1 -.names key[66]* [7917] -1 1 -.names [7917]* [7581]* [1717] -11 1 -.names I920 I919 [7916] -1- 1 --1 1 -.names [7897]* [7602]* I919 -11 1 -.names [7911]* [7604]* I920 -11 1 -.names [7916] [1717] [7914] [1714] new_C[51] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7897]* [7600]* [1708] -11 1 -.names C[48]* [7530] -1 1 -.names I926 I925 [7919] -1- 1 --1 1 -.names [7597]* [7530]* I925 -11 1 -.names [7913]* [7598]* I926 -11 1 -.names key[74]* [7922] -1 1 -.names [7922]* [7581]* [1711] -11 1 -.names I931 I930 [7921] -1- 1 --1 1 -.names [7602]* [7537]* I930 -11 1 -.names [7917]* [7604]* I931 -11 1 -.names [7921] [1711] [7919] [1708] new_C[50] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7537]* [1702] -11 1 -.names C[47]* [7519] -1 1 -.names I937 I936 [7924] -1- 1 --1 1 -.names [7597]* [7519]* I936 -11 1 -.names [7598]* [7530]* I937 -11 1 -.names key[82]* [7927] -1 1 -.names [7927]* [7581]* [1705] -11 1 -.names I942 I941 [7926] -1- 1 --1 1 -.names [7602]* [7528]* I941 -11 1 -.names [7922]* [7604]* I942 -11 1 -.names [7926] [1705] [7924] [1702] new_C[49] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7528]* [1696] -11 1 -.names C[46]* [7527] -1 1 -.names I948 I947 [7929] -1- 1 --1 1 -.names [7597]* [7527]* I947 -11 1 -.names [7598]* [7519]* I948 -11 1 -.names key[90]* [7932] -1 1 -.names [7932]* [7581]* [1699] -11 1 -.names I953 I952 [7931] -1- 1 --1 1 -.names [7913]* [7602]* I952 -11 1 -.names [7927]* [7604]* I953 -11 1 -.names [7931] [1699] [7929] [1696] new_C[48] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7913]* [7600]* [1690] -11 1 -.names C[45]* [7934] -1 1 -.names I959 I958 [7935] -1- 1 --1 1 -.names [7934]* [7597]* I958 -11 1 -.names [7598]* [7527]* I959 -11 1 -.names key[98]* [7938] -1 1 -.names [7938]* [7581]* [1693] -11 1 -.names I964 I963 [7937] -1- 1 --1 1 -.names [7602]* [7530]* I963 -11 1 -.names [7932]* [7604]* I964 -11 1 -.names [7937] [1693] [7935] [1690] new_C[47] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7530]* [1684] -11 1 -.names C[44]* [7539] -1 1 -.names I970 I969 [7940] -1- 1 --1 1 -.names [7597]* [7539]* I969 -11 1 -.names [7934]* [7598]* I970 -11 1 -.names key[106]* [7943] -1 1 -.names [7943]* [7581]* [1687] -11 1 -.names I975 I974 [7942] -1- 1 --1 1 -.names [7602]* [7519]* I974 -11 1 -.names [7938]* [7604]* I975 -11 1 -.names [7942] [1687] [7940] [1684] new_C[46] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7519]* [1678] -11 1 -.names C[43]* [7522] -1 1 -.names I981 I980 [7945] -1- 1 --1 1 -.names [7597]* [7522]* I980 -11 1 -.names [7598]* [7539]* I981 -11 1 -.names key[114]* [7948] -1 1 -.names [7948]* [7581]* [1681] -11 1 -.names I986 I985 [7947] -1- 1 --1 1 -.names [7602]* [7527]* I985 -11 1 -.names [7943]* [7604]* I986 -11 1 -.names [7947] [1681] [7945] [1678] new_C[45] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7527]* [1672] -11 1 -.names C[42]* [7532] -1 1 -.names I992 I991 [7950] -1- 1 --1 1 -.names [7597]* [7532]* I991 -11 1 -.names [7598]* [7522]* I992 -11 1 -.names key[122]* [7953] -1 1 -.names [7953]* [7581]* [1675] -11 1 -.names I997 I996 [7952] -1- 1 --1 1 -.names [7934]* [7602]* I996 -11 1 -.names [7948]* [7604]* I997 -11 1 -.names [7952] [1675] [7950] [1672] new_C[44] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7934]* [7600]* [1666] -11 1 -.names C[41]* [7540] -1 1 -.names I1003 I1002 [7955] -1- 1 --1 1 -.names [7597]* [7540]* I1002 -11 1 -.names [7598]* [7532]* I1003 -11 1 -.names key[65]* [7958] -1 1 -.names [7958]* [7581]* [1669] -11 1 -.names I1008 I1007 [7957] -1- 1 --1 1 -.names [7602]* [7539]* I1007 -11 1 -.names [7953]* [7604]* I1008 -11 1 -.names [7957] [1669] [7955] [1666] new_C[43] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7539]* [1660] -11 1 -.names C[40]* [7518] -1 1 -.names I1014 I1013 [7960] -1- 1 --1 1 -.names [7597]* [7518]* I1013 -11 1 -.names [7598]* [7540]* I1014 -11 1 -.names key[73]* [7963] -1 1 -.names [7963]* [7581]* [1663] -11 1 -.names I1019 I1018 [7962] -1- 1 --1 1 -.names [7602]* [7522]* I1018 -11 1 -.names [7958]* [7604]* I1019 -11 1 -.names [7962] [1663] [7960] [1660] new_C[42] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7522]* [1654] -11 1 -.names C[39]* [7526] -1 1 -.names I1025 I1024 [7965] -1- 1 --1 1 -.names [7597]* [7526]* I1024 -11 1 -.names [7598]* [7518]* I1025 -11 1 -.names key[81]* [7968] -1 1 -.names [7968]* [7581]* [1657] -11 1 -.names I1030 I1029 [7967] -1- 1 --1 1 -.names [7602]* [7532]* I1029 -11 1 -.names [7963]* [7604]* I1030 -11 1 -.names [7967] [1657] [7965] [1654] new_C[41] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7532]* [1648] -11 1 -.names C[38]* [7538] -1 1 -.names I1036 I1035 [7970] -1- 1 --1 1 -.names [7597]* [7538]* I1035 -11 1 -.names [7598]* [7526]* I1036 -11 1 -.names key[89]* [7973] -1 1 -.names [7973]* [7581]* [1651] -11 1 -.names I1041 I1040 [7972] -1- 1 --1 1 -.names [7602]* [7540]* I1040 -11 1 -.names [7968]* [7604]* I1041 -11 1 -.names [7972] [1651] [7970] [1648] new_C[40] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7540]* [1642] -11 1 -.names C[37]* [7529] -1 1 -.names I1047 I1046 [7975] -1- 1 --1 1 -.names [7597]* [7529]* I1046 -11 1 -.names [7598]* [7538]* I1047 -11 1 -.names key[97]* [7978] -1 1 -.names [7978]* [7581]* [1645] -11 1 -.names I1052 I1051 [7977] -1- 1 --1 1 -.names [7602]* [7518]* I1051 -11 1 -.names [7973]* [7604]* I1052 -11 1 -.names [7977] [1645] [7975] [1642] new_C[39] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7518]* [1636] -11 1 -.names C[36]* [7980] -1 1 -.names I1058 I1057 [7981] -1- 1 --1 1 -.names [7980]* [7597]* I1057 -11 1 -.names [7598]* [7529]* I1058 -11 1 -.names key[105]* [7984] -1 1 -.names [7984]* [7581]* [1639] -11 1 -.names I1063 I1062 [7983] -1- 1 --1 1 -.names [7602]* [7526]* I1062 -11 1 -.names [7978]* [7604]* I1063 -11 1 -.names [7983] [1639] [7981] [1636] new_C[38] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7526]* [1630] -11 1 -.names C[35]* [7523] -1 1 -.names I1069 I1068 [7986] -1- 1 --1 1 -.names [7597]* [7523]* I1068 -11 1 -.names [7980]* [7598]* I1069 -11 1 -.names key[113]* [7989] -1 1 -.names [7989]* [7581]* [1633] -11 1 -.names I1074 I1073 [7988] -1- 1 --1 1 -.names [7602]* [7538]* I1073 -11 1 -.names [7984]* [7604]* I1074 -11 1 -.names [7988] [1633] [7986] [1630] new_C[37] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7538]* [1624] -11 1 -.names C[34]* [7521] -1 1 -.names I1080 I1079 [7991] -1- 1 --1 1 -.names [7597]* [7521]* I1079 -11 1 -.names [7598]* [7523]* I1080 -11 1 -.names key[121]* [7994] -1 1 -.names [7994]* [7581]* [1627] -11 1 -.names I1085 I1084 [7993] -1- 1 --1 1 -.names [7602]* [7529]* I1084 -11 1 -.names [7989]* [7604]* I1085 -11 1 -.names [7993] [1627] [7991] [1624] new_C[36] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7529]* [1618] -11 1 -.names C[33]* [7531] -1 1 -.names I1091 I1090 [7996] -1- 1 --1 1 -.names [7597]* [7531]* I1090 -11 1 -.names [7598]* [7521]* I1091 -11 1 -.names key[64]* [7999] -1 1 -.names [7999]* [7581]* [1621] -11 1 -.names I1096 I1095 [7998] -1- 1 --1 1 -.names [7980]* [7602]* I1095 -11 1 -.names [7994]* [7604]* I1096 -11 1 -.names [7998] [1621] [7996] [1618] new_C[35] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7980]* [7600]* [1612] -11 1 -.names C[32]* [7535] -1 1 -.names I1102 I1101 [8001] -1- 1 --1 1 -.names [7597]* [7535]* I1101 -11 1 -.names [7598]* [7531]* I1102 -11 1 -.names key[72]* [8004] -1 1 -.names [8004]* [7581]* [1615] -11 1 -.names I1107 I1106 [8003] -1- 1 --1 1 -.names [7602]* [7523]* I1106 -11 1 -.names [7999]* [7604]* I1107 -11 1 -.names [8003] [1615] [8001] [1612] new_C[34] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7523]* [1606] -11 1 -.names C[31]* [7525] -1 1 -.names I1113 I1112 [8006] -1- 1 --1 1 -.names [7597]* [7525]* I1112 -11 1 -.names [7598]* [7535]* I1113 -11 1 -.names key[80]* [8009] -1 1 -.names [8009]* [7581]* [1609] -11 1 -.names I1118 I1117 [8008] -1- 1 --1 1 -.names [7602]* [7521]* I1117 -11 1 -.names [8004]* [7604]* I1118 -11 1 -.names [8008] [1609] [8006] [1606] new_C[33] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7521]* [1600] -11 1 -.names C[30]* [7534] -1 1 -.names I1124 I1123 [8011] -1- 1 --1 1 -.names [7597]* [7534]* I1123 -11 1 -.names [7598]* [7525]* I1124 -11 1 -.names key[88]* [8014] -1 1 -.names [8014]* [7581]* [1603] -11 1 -.names I1129 I1128 [8013] -1- 1 --1 1 -.names [7602]* [7531]* I1128 -11 1 -.names [8009]* [7604]* I1129 -11 1 -.names [8013] [1603] [8011] [1600] new_C[32] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7531]* [1594] -11 1 -.names C[29]* [7517] -1 1 -.names I1135 I1134 [8016] -1- 1 --1 1 -.names [7597]* [7517]* I1134 -11 1 -.names [7598]* [7534]* I1135 -11 1 -.names key[96]* [8019] -1 1 -.names [8019]* [7581]* [1597] -11 1 -.names I1140 I1139 [8018] -1- 1 --1 1 -.names [7602]* [7535]* I1139 -11 1 -.names [8014]* [7604]* I1140 -11 1 -.names [8018] [1597] [8016] [1594] new_C[31] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7535]* [1588] -11 1 -.names C[28]* [7536] -1 1 -.names I1146 I1145 [8021] -1- 1 --1 1 -.names [7597]* [7536]* I1145 -11 1 -.names [7598]* [7517]* I1146 -11 1 -.names key[104]* [8024] -1 1 -.names [8024]* [7581]* [1591] -11 1 -.names I1151 I1150 [8023] -1- 1 --1 1 -.names [7602]* [7525]* I1150 -11 1 -.names [8019]* [7604]* I1151 -11 1 -.names [8023] [1591] [8021] [1588] new_C[30] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7525]* [1582] -11 1 -.names C[27]* [7557] -1 1 -.names I1157 I1156 [8026] -1- 1 --1 1 -.names [7597]* [7557]* I1156 -11 1 -.names [7598]* [7536]* I1157 -11 1 -.names key[112]* [8029] -1 1 -.names [8029]* [7581]* [1585] -11 1 -.names I1162 I1161 [8028] -1- 1 --1 1 -.names [7602]* [7534]* I1161 -11 1 -.names [8024]* [7604]* I1162 -11 1 -.names [8028] [1585] [8026] [1582] new_C[29] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7534]* [1576] -11 1 -.names C[26]* [7544] -1 1 -.names I1168 I1167 [8031] -1- 1 --1 1 -.names [7597]* [7544]* I1167 -11 1 -.names [7598]* [7557]* I1168 -11 1 -.names key[120]* [8034] -1 1 -.names [8034]* [7581]* [1579] -11 1 -.names I1173 I1172 [8033] -1- 1 --1 1 -.names [7602]* [7517]* I1172 -11 1 -.names [8029]* [7604]* I1173 -11 1 -.names [8033] [1579] [8031] [1576] new_C[28] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7517]* [1570] -11 1 -.names C[25]* [7548] -1 1 -.names I1179 I1178 [8036] -1- 1 --1 1 -.names [7597]* [7548]* I1178 -11 1 -.names [7598]* [7544]* I1179 -11 1 -.names key[35]* [8039] -1 1 -.names [8039]* [7581]* [1573] -11 1 -.names I1184 I1183 [8038] -1- 1 --1 1 -.names [7602]* [7536]* I1183 -11 1 -.names [8034]* [7604]* I1184 -11 1 -.names [8038] [1573] [8036] [1570] new_C[27] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7536]* [1564] -11 1 -.names C[24]* [8041] -1 1 -.names I1190 I1189 [8042] -1- 1 --1 1 -.names [8041]* [7597]* I1189 -11 1 -.names [7598]* [7548]* I1190 -11 1 -.names key[43]* [8045] -1 1 -.names [8045]* [7581]* [1567] -11 1 -.names I1195 I1194 [8044] -1- 1 --1 1 -.names [7602]* [7557]* I1194 -11 1 -.names [8039]* [7604]* I1195 -11 1 -.names [8044] [1567] [8042] [1564] new_C[26] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7557]* [1558] -11 1 -.names C[23]* [7561] -1 1 -.names I1201 I1200 [8047] -1- 1 --1 1 -.names [7597]* [7561]* I1200 -11 1 -.names [8041]* [7598]* I1201 -11 1 -.names key[51]* [8050] -1 1 -.names [8050]* [7581]* [1561] -11 1 -.names I1206 I1205 [8049] -1- 1 --1 1 -.names [7602]* [7544]* I1205 -11 1 -.names [8045]* [7604]* I1206 -11 1 -.names [8049] [1561] [8047] [1558] new_C[25] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7544]* [1552] -11 1 -.names C[22]* [7552] -1 1 -.names I1212 I1211 [8052] -1- 1 --1 1 -.names [7597]* [7552]* I1211 -11 1 -.names [7598]* [7561]* I1212 -11 1 -.names key[59]* [8055] -1 1 -.names [8055]* [7581]* [1555] -11 1 -.names I1217 I1216 [8054] -1- 1 --1 1 -.names [7602]* [7548]* I1216 -11 1 -.names [8050]* [7604]* I1217 -11 1 -.names [8054] [1555] [8052] [1552] new_C[24] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7548]* [1546] -11 1 -.names C[21]* [8057] -1 1 -.names I1223 I1222 [8058] -1- 1 --1 1 -.names [8057]* [7597]* I1222 -11 1 -.names [7598]* [7552]* I1223 -11 1 -.names key[2]* [8061] -1 1 -.names [8061]* [7581]* [1549] -11 1 -.names I1228 I1227 [8060] -1- 1 --1 1 -.names [8041]* [7602]* I1227 -11 1 -.names [8055]* [7604]* I1228 -11 1 -.names [8060] [1549] [8058] [1546] new_C[23] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8041]* [7600]* [1540] -11 1 -.names C[20]* [7554] -1 1 -.names I1234 I1233 [8063] -1- 1 --1 1 -.names [7597]* [7554]* I1233 -11 1 -.names [8057]* [7598]* I1234 -11 1 -.names key[10]* [8066] -1 1 -.names [8066]* [7581]* [1543] -11 1 -.names I1239 I1238 [8065] -1- 1 --1 1 -.names [7602]* [7561]* I1238 -11 1 -.names [8061]* [7604]* I1239 -11 1 -.names [8065] [1543] [8063] [1540] new_C[22] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7561]* [1534] -11 1 -.names C[19]* [7543] -1 1 -.names I1245 I1244 [8068] -1- 1 --1 1 -.names [7597]* [7543]* I1244 -11 1 -.names [7598]* [7554]* I1245 -11 1 -.names key[18]* [8071] -1 1 -.names [8071]* [7581]* [1537] -11 1 -.names I1250 I1249 [8070] -1- 1 --1 1 -.names [7602]* [7552]* I1249 -11 1 -.names [8066]* [7604]* I1250 -11 1 -.names [8070] [1537] [8068] [1534] new_C[21] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7552]* [1528] -11 1 -.names C[18]* [7551] -1 1 -.names I1256 I1255 [8073] -1- 1 --1 1 -.names [7597]* [7551]* I1255 -11 1 -.names [7598]* [7543]* I1256 -11 1 -.names key[26]* [8076] -1 1 -.names [8076]* [7581]* [1531] -11 1 -.names I1261 I1260 [8075] -1- 1 --1 1 -.names [8057]* [7602]* I1260 -11 1 -.names [8071]* [7604]* I1261 -11 1 -.names [8075] [1531] [8073] [1528] new_C[20] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8057]* [7600]* [1522] -11 1 -.names C[17]* [8078] -1 1 -.names I1267 I1266 [8079] -1- 1 --1 1 -.names [8078]* [7597]* I1266 -11 1 -.names [7598]* [7551]* I1267 -11 1 -.names key[34]* [8082] -1 1 -.names [8082]* [7581]* [1525] -11 1 -.names I1272 I1271 [8081] -1- 1 --1 1 -.names [7602]* [7554]* I1271 -11 1 -.names [8076]* [7604]* I1272 -11 1 -.names [8081] [1525] [8079] [1522] new_C[19] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7554]* [1516] -11 1 -.names C[16]* [7563] -1 1 -.names I1278 I1277 [8084] -1- 1 --1 1 -.names [7597]* [7563]* I1277 -11 1 -.names [8078]* [7598]* I1278 -11 1 -.names key[42]* [8087] -1 1 -.names [8087]* [7581]* [1519] -11 1 -.names I1283 I1282 [8086] -1- 1 --1 1 -.names [7602]* [7543]* I1282 -11 1 -.names [8082]* [7604]* I1283 -11 1 -.names [8086] [1519] [8084] [1516] new_C[18] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7543]* [1510] -11 1 -.names C[15]* [7546] -1 1 -.names I1289 I1288 [8089] -1- 1 --1 1 -.names [7597]* [7546]* I1288 -11 1 -.names [7598]* [7563]* I1289 -11 1 -.names key[50]* [8092] -1 1 -.names [8092]* [7581]* [1513] -11 1 -.names I1294 I1293 [8091] -1- 1 --1 1 -.names [7602]* [7551]* I1293 -11 1 -.names [8087]* [7604]* I1294 -11 1 -.names [8091] [1513] [8089] [1510] new_C[17] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7551]* [1504] -11 1 -.names C[14]* [7556] -1 1 -.names I1300 I1299 [8094] -1- 1 --1 1 -.names [7597]* [7556]* I1299 -11 1 -.names [7598]* [7546]* I1300 -11 1 -.names key[58]* [8097] -1 1 -.names [8097]* [7581]* [1507] -11 1 -.names I1305 I1304 [8096] -1- 1 --1 1 -.names [8078]* [7602]* I1304 -11 1 -.names [8092]* [7604]* I1305 -11 1 -.names [8096] [1507] [8094] [1504] new_C[16] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8078]* [7600]* [1498] -11 1 -.names C[13]* [7564] -1 1 -.names I1311 I1310 [8099] -1- 1 --1 1 -.names [7597]* [7564]* I1310 -11 1 -.names [7598]* [7556]* I1311 -11 1 -.names key[1]* [8102] -1 1 -.names [8102]* [7581]* [1501] -11 1 -.names I1316 I1315 [8101] -1- 1 --1 1 -.names [7602]* [7563]* I1315 -11 1 -.names [8097]* [7604]* I1316 -11 1 -.names [8101] [1501] [8099] [1498] new_C[15] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7563]* [1492] -11 1 -.names C[12]* [7542] -1 1 -.names I1322 I1321 [8104] -1- 1 --1 1 -.names [7597]* [7542]* I1321 -11 1 -.names [7598]* [7564]* I1322 -11 1 -.names key[9]* [8107] -1 1 -.names [8107]* [7581]* [1495] -11 1 -.names I1327 I1326 [8106] -1- 1 --1 1 -.names [7602]* [7546]* I1326 -11 1 -.names [8102]* [7604]* I1327 -11 1 -.names [8106] [1495] [8104] [1492] new_C[14] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7546]* [1486] -11 1 -.names C[11]* [7550] -1 1 -.names I1333 I1332 [8109] -1- 1 --1 1 -.names [7597]* [7550]* I1332 -11 1 -.names [7598]* [7542]* I1333 -11 1 -.names key[17]* [8112] -1 1 -.names [8112]* [7581]* [1489] -11 1 -.names I1338 I1337 [8111] -1- 1 --1 1 -.names [7602]* [7556]* I1337 -11 1 -.names [8107]* [7604]* I1338 -11 1 -.names [8111] [1489] [8109] [1486] new_C[13] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7556]* [1480] -11 1 -.names C[10]* [7562] -1 1 -.names I1344 I1343 [8114] -1- 1 --1 1 -.names [7597]* [7562]* I1343 -11 1 -.names [7598]* [7550]* I1344 -11 1 -.names key[25]* [8117] -1 1 -.names [8117]* [7581]* [1483] -11 1 -.names I1349 I1348 [8116] -1- 1 --1 1 -.names [7602]* [7564]* I1348 -11 1 -.names [8112]* [7604]* I1349 -11 1 -.names [8116] [1483] [8114] [1480] new_C[12] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7564]* [1474] -11 1 -.names C[9]* [7553] -1 1 -.names I1355 I1354 [8119] -1- 1 --1 1 -.names [7597]* [7553]* I1354 -11 1 -.names [7598]* [7562]* I1355 -11 1 -.names key[33]* [8122] -1 1 -.names [8122]* [7581]* [1477] -11 1 -.names I1360 I1359 [8121] -1- 1 --1 1 -.names [7602]* [7542]* I1359 -11 1 -.names [8117]* [7604]* I1360 -11 1 -.names [8121] [1477] [8119] [1474] new_C[11] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7542]* [1468] -11 1 -.names C[8]* [8124] -1 1 -.names I1366 I1365 [8125] -1- 1 --1 1 -.names [8124]* [7597]* I1365 -11 1 -.names [7598]* [7553]* I1366 -11 1 -.names key[41]* [8128] -1 1 -.names [8128]* [7581]* [1471] -11 1 -.names I1371 I1370 [8127] -1- 1 --1 1 -.names [7602]* [7550]* I1370 -11 1 -.names [8122]* [7604]* I1371 -11 1 -.names [8127] [1471] [8125] [1468] new_C[10] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7550]* [1462] -11 1 -.names C[7]* [7547] -1 1 -.names I1377 I1376 [8130] -1- 1 --1 1 -.names [7597]* [7547]* I1376 -11 1 -.names [8124]* [7598]* I1377 -11 1 -.names key[49]* [8133] -1 1 -.names [8133]* [7581]* [1465] -11 1 -.names I1382 I1381 [8132] -1- 1 --1 1 -.names [7602]* [7562]* I1381 -11 1 -.names [8128]* [7604]* I1382 -11 1 -.names [8132] [1465] [8130] [1462] new_C[9] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7562]* [1456] -11 1 -.names C[6]* [7545] -1 1 -.names I1388 I1387 [8135] -1- 1 --1 1 -.names [7597]* [7545]* I1387 -11 1 -.names [7598]* [7547]* I1388 -11 1 -.names key[57]* [8138] -1 1 -.names [8138]* [7581]* [1459] -11 1 -.names I1393 I1392 [8137] -1- 1 --1 1 -.names [7602]* [7553]* I1392 -11 1 -.names [8133]* [7604]* I1393 -11 1 -.names [8137] [1459] [8135] [1456] new_C[8] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7553]* [1450] -11 1 -.names C[5]* [7555] -1 1 -.names I1399 I1398 [8140] -1- 1 --1 1 -.names [7597]* [7555]* I1398 -11 1 -.names [7598]* [7545]* I1399 -11 1 -.names key[0]* [8143] -1 1 -.names [8143]* [7581]* [1453] -11 1 -.names I1404 I1403 [8142] -1- 1 --1 1 -.names [8124]* [7602]* I1403 -11 1 -.names [8138]* [7604]* I1404 -11 1 -.names [8142] [1453] [8140] [1450] new_C[7] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8124]* [7600]* [1444] -11 1 -.names C[4]* [7559] -1 1 -.names I1410 I1409 [8145] -1- 1 --1 1 -.names [7597]* [7559]* I1409 -11 1 -.names [7598]* [7555]* I1410 -11 1 -.names key[8]* [8148] -1 1 -.names [8148]* [7581]* [1447] -11 1 -.names I1415 I1414 [8147] -1- 1 --1 1 -.names [7602]* [7547]* I1414 -11 1 -.names [8143]* [7604]* I1415 -11 1 -.names [8147] [1447] [8145] [1444] new_C[6] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7547]* [1438] -11 1 -.names C[3]* [7549] -1 1 -.names I1421 I1420 [8150] -1- 1 --1 1 -.names [7597]* [7549]* I1420 -11 1 -.names [7598]* [7559]* I1421 -11 1 -.names key[16]* [8153] -1 1 -.names [8153]* [7581]* [1441] -11 1 -.names I1426 I1425 [8152] -1- 1 --1 1 -.names [7602]* [7545]* I1425 -11 1 -.names [8148]* [7604]* I1426 -11 1 -.names [8152] [1441] [8150] [1438] new_C[5] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7545]* [1432] -11 1 -.names C[2]* [7558] -1 1 -.names I1432 I1431 [8155] -1- 1 --1 1 -.names [7597]* [7558]* I1431 -11 1 -.names [7598]* [7549]* I1432 -11 1 -.names key[24]* [8158] -1 1 -.names [8158]* [7581]* [1435] -11 1 -.names I1437 I1436 [8157] -1- 1 --1 1 -.names [7602]* [7555]* I1436 -11 1 -.names [8153]* [7604]* I1437 -11 1 -.names [8157] [1435] [8155] [1432] new_C[4] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7555]* [1426] -11 1 -.names I1442 I1441 [8160] -1- 1 --1 1 -.names [7597]* [7541]* I1441 -11 1 -.names [7598]* [7558]* I1442 -11 1 -.names key[32]* [8163] -1 1 -.names [8163]* [7581]* [1429] -11 1 -.names I1447 I1446 [8162] -1- 1 --1 1 -.names [7602]* [7559]* I1446 -11 1 -.names [8158]* [7604]* I1447 -11 1 -.names [8162] [1429] [8160] [1426] new_C[3] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7559]* [1420] -11 1 -.names I1452 I1451 [8165] -1- 1 --1 1 -.names [7597]* [7560]* I1451 -11 1 -.names [7598]* [7541]* I1452 -11 1 -.names key[40]* [8168] -1 1 -.names [8168]* [7581]* [1423] -11 1 -.names I1457 I1456 [8167] -1- 1 --1 1 -.names [7602]* [7549]* I1456 -11 1 -.names [8163]* [7604]* I1457 -11 1 -.names [8167] [1423] [8165] [1420] new_C[2] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7549]* [1414] -11 1 -.names I1462 I1461 [8170] -1- 1 --1 1 -.names [7597]* [7485]* I1461 -11 1 -.names [7598]* [7560]* I1462 -11 1 -.names key[48]* [8173] -1 1 -.names [8173]* [7581]* [1417] -11 1 -.names I1467 I1466 [8172] -1- 1 --1 1 -.names [7602]* [7558]* I1466 -11 1 -.names [8168]* [7604]* I1467 -11 1 -.names [8172] [1417] [8170] [1414] new_C[1] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7558]* [1408] -11 1 -.names I1472 I1471 [8175] -1- 1 --1 1 -.names [7597]* [7473]* I1471 -11 1 -.names [7598]* [7485]* I1472 -11 1 -.names [7603]* [7581]* [1411] -11 1 -.names I1476 I1475 [8177] -1- 1 --1 1 -.names [7602]* [7541]* I1475 -11 1 -.names [8173]* [7604]* I1476 -11 1 -.names [8177] [1411] [8175] [1408] new_C[0] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names D[1]* [7463] -1 1 -.names [7600]* [7463]* [1402] -11 1 -.names D[109]* [8179] -1 1 -.names D[110]* [7394] -1 1 -.names I1484 I1483 [8180] -1- 1 --1 1 -.names [8179]* [7597]* I1483 -11 1 -.names [7598]* [7394]* I1484 -11 1 -.names key[195]* [8184] -1 1 -.names [8184]* [7581]* [1405] -11 1 -.names D[0]* [7447] -1 1 -.names key[62]* [8182] -1 1 -.names I1491 I1490 [8183] -1- 1 --1 1 -.names [7602]* [7447]* I1490 -11 1 -.names [8182]* [7604]* I1491 -11 1 -.names [8183] [1405] [8180] [1402] new_D[111] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7447]* [1396] -11 1 -.names D[108]* [7382] -1 1 -.names I1497 I1496 [8186] -1- 1 --1 1 -.names [7597]* [7382]* I1496 -11 1 -.names [8179]* [7598]* I1497 -11 1 -.names key[203]* [8189] -1 1 -.names [8189]* [7581]* [1399] -11 1 -.names D[111]* [7384] -1 1 -.names I1503 I1502 [8188] -1- 1 --1 1 -.names [7602]* [7384]* I1502 -11 1 -.names [8184]* [7604]* I1503 -11 1 -.names [8188] [1399] [8186] [1396] new_D[110] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7384]* [1390] -11 1 -.names D[107]* [7398] -1 1 -.names I1509 I1508 [8191] -1- 1 --1 1 -.names [7597]* [7398]* I1508 -11 1 -.names [7598]* [7382]* I1509 -11 1 -.names key[211]* [8194] -1 1 -.names [8194]* [7581]* [1393] -11 1 -.names I1514 I1513 [8193] -1- 1 --1 1 -.names [7602]* [7394]* I1513 -11 1 -.names [8189]* [7604]* I1514 -11 1 -.names [8193] [1393] [8191] [1390] new_D[109] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7394]* [1384] -11 1 -.names D[106]* [7391] -1 1 -.names I1520 I1519 [8196] -1- 1 --1 1 -.names [7597]* [7391]* I1519 -11 1 -.names [7598]* [7398]* I1520 -11 1 -.names key[219]* [8199] -1 1 -.names [8199]* [7581]* [1387] -11 1 -.names I1525 I1524 [8198] -1- 1 --1 1 -.names [8179]* [7602]* I1524 -11 1 -.names [8194]* [7604]* I1525 -11 1 -.names [8198] [1387] [8196] [1384] new_D[108] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8179]* [7600]* [1378] -11 1 -.names D[105]* [7380] -1 1 -.names I1531 I1530 [8201] -1- 1 --1 1 -.names [7597]* [7380]* I1530 -11 1 -.names [7598]* [7391]* I1531 -11 1 -.names key[196]* [8204] -1 1 -.names [8204]* [7581]* [1381] -11 1 -.names I1536 I1535 [8203] -1- 1 --1 1 -.names [7602]* [7382]* I1535 -11 1 -.names [8199]* [7604]* I1536 -11 1 -.names [8203] [1381] [8201] [1378] new_D[107] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7382]* [1372] -11 1 -.names D[104]* [7386] -1 1 -.names I1542 I1541 [8206] -1- 1 --1 1 -.names [7597]* [7386]* I1541 -11 1 -.names [7598]* [7380]* I1542 -11 1 -.names key[204]* [8209] -1 1 -.names [8209]* [7581]* [1375] -11 1 -.names I1547 I1546 [8208] -1- 1 --1 1 -.names [7602]* [7398]* I1546 -11 1 -.names [8204]* [7604]* I1547 -11 1 -.names [8208] [1375] [8206] [1372] new_D[106] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7398]* [1366] -11 1 -.names D[103]* [7388] -1 1 -.names I1553 I1552 [8211] -1- 1 --1 1 -.names [7597]* [7388]* I1552 -11 1 -.names [7598]* [7386]* I1553 -11 1 -.names key[212]* [8214] -1 1 -.names [8214]* [7581]* [1369] -11 1 -.names I1558 I1557 [8213] -1- 1 --1 1 -.names [7602]* [7391]* I1557 -11 1 -.names [8209]* [7604]* I1558 -11 1 -.names [8213] [1369] [8211] [1366] new_D[105] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7391]* [1360] -11 1 -.names D[102]* [7395] -1 1 -.names I1564 I1563 [8216] -1- 1 --1 1 -.names [7597]* [7395]* I1563 -11 1 -.names [7598]* [7388]* I1564 -11 1 -.names key[220]* [8219] -1 1 -.names [8219]* [7581]* [1363] -11 1 -.names I1569 I1568 [8218] -1- 1 --1 1 -.names [7602]* [7380]* I1568 -11 1 -.names [8214]* [7604]* I1569 -11 1 -.names [8218] [1363] [8216] [1360] new_D[104] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7380]* [1354] -11 1 -.names D[101]* [7381] -1 1 -.names I1575 I1574 [8221] -1- 1 --1 1 -.names [7597]* [7381]* I1574 -11 1 -.names [7598]* [7395]* I1575 -11 1 -.names key[228]* [8224] -1 1 -.names [8224]* [7581]* [1357] -11 1 -.names I1580 I1579 [8223] -1- 1 --1 1 -.names [7602]* [7386]* I1579 -11 1 -.names [8219]* [7604]* I1580 -11 1 -.names [8223] [1357] [8221] [1354] new_D[103] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7386]* [1348] -11 1 -.names D[100]* [7390] -1 1 -.names I1586 I1585 [8226] -1- 1 --1 1 -.names [7597]* [7390]* I1585 -11 1 -.names [7598]* [7381]* I1586 -11 1 -.names key[172]* [8229] -1 1 -.names [8229]* [7581]* [1351] -11 1 -.names I1591 I1590 [8228] -1- 1 --1 1 -.names [7602]* [7388]* I1590 -11 1 -.names [8224]* [7604]* I1591 -11 1 -.names [8228] [1351] [8226] [1348] new_D[102] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7388]* [1342] -11 1 -.names D[99]* [7387] -1 1 -.names I1597 I1596 [8231] -1- 1 --1 1 -.names [7597]* [7387]* I1596 -11 1 -.names [7598]* [7390]* I1597 -11 1 -.names key[244]* [8234] -1 1 -.names [8234]* [7581]* [1345] -11 1 -.names I1602 I1601 [8233] -1- 1 --1 1 -.names [7602]* [7395]* I1601 -11 1 -.names [8229]* [7604]* I1602 -11 1 -.names [8233] [1345] [8231] [1342] new_D[101] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7395]* [1336] -11 1 -.names D[98]* [8236] -1 1 -.names I1608 I1607 [8237] -1- 1 --1 1 -.names [8236]* [7597]* I1607 -11 1 -.names [7598]* [7387]* I1608 -11 1 -.names key[252]* [8240] -1 1 -.names [8240]* [7581]* [1339] -11 1 -.names I1613 I1612 [8239] -1- 1 --1 1 -.names [7602]* [7381]* I1612 -11 1 -.names [8234]* [7604]* I1613 -11 1 -.names [8239] [1339] [8237] [1336] new_D[100] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7381]* [1330] -11 1 -.names D[97]* [8242] -1 1 -.names I1619 I1618 [8243] -1- 1 --1 1 -.names [8242]* [7597]* I1618 -11 1 -.names [8236]* [7598]* I1619 -11 1 -.names key[197]* [8246] -1 1 -.names [8246]* [7581]* [1333] -11 1 -.names I1624 I1623 [8245] -1- 1 --1 1 -.names [7602]* [7390]* I1623 -11 1 -.names [8240]* [7604]* I1624 -11 1 -.names [8245] [1333] [8243] [1330] new_D[99] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7390]* [1324] -11 1 -.names D[96]* [8248] -1 1 -.names I1630 I1629 [8249] -1- 1 --1 1 -.names [8248]* [7597]* I1629 -11 1 -.names [8242]* [7598]* I1630 -11 1 -.names key[205]* [8252] -1 1 -.names [8252]* [7581]* [1327] -11 1 -.names I1635 I1634 [8251] -1- 1 --1 1 -.names [7602]* [7387]* I1634 -11 1 -.names [8246]* [7604]* I1635 -11 1 -.names [8251] [1327] [8249] [1324] new_D[98] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7387]* [1318] -11 1 -.names D[95]* [7392] -1 1 -.names I1641 I1640 [8254] -1- 1 --1 1 -.names [7597]* [7392]* I1640 -11 1 -.names [8248]* [7598]* I1641 -11 1 -.names key[213]* [8257] -1 1 -.names [8257]* [7581]* [1321] -11 1 -.names I1646 I1645 [8256] -1- 1 --1 1 -.names [8236]* [7602]* I1645 -11 1 -.names [8252]* [7604]* I1646 -11 1 -.names [8256] [1321] [8254] [1318] new_D[97] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8236]* [7600]* [1312] -11 1 -.names D[94]* [7385] -1 1 -.names I1652 I1651 [8259] -1- 1 --1 1 -.names [7597]* [7385]* I1651 -11 1 -.names [7598]* [7392]* I1652 -11 1 -.names key[221]* [8262] -1 1 -.names [8262]* [7581]* [1315] -11 1 -.names I1657 I1656 [8261] -1- 1 --1 1 -.names [8242]* [7602]* I1656 -11 1 -.names [8257]* [7604]* I1657 -11 1 -.names [8261] [1315] [8259] [1312] new_D[96] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8242]* [7600]* [1306] -11 1 -.names D[93]* [8264] -1 1 -.names I1663 I1662 [8265] -1- 1 --1 1 -.names [8264]* [7597]* I1662 -11 1 -.names [7598]* [7385]* I1663 -11 1 -.names key[229]* [8268] -1 1 -.names [8268]* [7581]* [1309] -11 1 -.names I1668 I1667 [8267] -1- 1 --1 1 -.names [8248]* [7602]* I1667 -11 1 -.names [8262]* [7604]* I1668 -11 1 -.names [8267] [1309] [8265] [1306] new_D[95] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8248]* [7600]* [1300] -11 1 -.names D[92]* [7396] -1 1 -.names I1674 I1673 [8270] -1- 1 --1 1 -.names [7597]* [7396]* I1673 -11 1 -.names [8264]* [7598]* I1674 -11 1 -.names key[237]* [8273] -1 1 -.names [8273]* [7581]* [1303] -11 1 -.names I1679 I1678 [8272] -1- 1 --1 1 -.names [7602]* [7392]* I1678 -11 1 -.names [8268]* [7604]* I1679 -11 1 -.names [8272] [1303] [8270] [1300] new_D[94] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7392]* [1294] -11 1 -.names D[91]* [7379] -1 1 -.names I1685 I1684 [8275] -1- 1 --1 1 -.names [7597]* [7379]* I1684 -11 1 -.names [7598]* [7396]* I1685 -11 1 -.names key[245]* [8278] -1 1 -.names [8278]* [7581]* [1297] -11 1 -.names I1690 I1689 [8277] -1- 1 --1 1 -.names [7602]* [7385]* I1689 -11 1 -.names [8273]* [7604]* I1690 -11 1 -.names [8277] [1297] [8275] [1294] new_D[93] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7385]* [1288] -11 1 -.names D[90]* [8280] -1 1 -.names I1696 I1695 [8281] -1- 1 --1 1 -.names [8280]* [7597]* I1695 -11 1 -.names [7598]* [7379]* I1696 -11 1 -.names key[253]* [8284] -1 1 -.names [8284]* [7581]* [1291] -11 1 -.names I1701 I1700 [8283] -1- 1 --1 1 -.names [8264]* [7602]* I1700 -11 1 -.names [8278]* [7604]* I1701 -11 1 -.names [8283] [1291] [8281] [1288] new_D[92] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8264]* [7600]* [1282] -11 1 -.names D[89]* [7383] -1 1 -.names I1707 I1706 [8286] -1- 1 --1 1 -.names [7597]* [7383]* I1706 -11 1 -.names [8280]* [7598]* I1707 -11 1 -.names key[198]* [8289] -1 1 -.names [8289]* [7581]* [1285] -11 1 -.names I1712 I1711 [8288] -1- 1 --1 1 -.names [7602]* [7396]* I1711 -11 1 -.names [8284]* [7604]* I1712 -11 1 -.names [8288] [1285] [8286] [1282] new_D[91] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7396]* [1276] -11 1 -.names D[88]* [7389] -1 1 -.names I1718 I1717 [8291] -1- 1 --1 1 -.names [7597]* [7389]* I1717 -11 1 -.names [7598]* [7383]* I1718 -11 1 -.names key[206]* [8294] -1 1 -.names [8294]* [7581]* [1279] -11 1 -.names I1723 I1722 [8293] -1- 1 --1 1 -.names [7602]* [7379]* I1722 -11 1 -.names [8289]* [7604]* I1723 -11 1 -.names [8293] [1279] [8291] [1276] new_D[90] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7379]* [1270] -11 1 -.names D[87]* [7377] -1 1 -.names I1729 I1728 [8296] -1- 1 --1 1 -.names [7597]* [7377]* I1728 -11 1 -.names [7598]* [7389]* I1729 -11 1 -.names key[214]* [8299] -1 1 -.names [8299]* [7581]* [1273] -11 1 -.names I1734 I1733 [8298] -1- 1 --1 1 -.names [8280]* [7602]* I1733 -11 1 -.names [8294]* [7604]* I1734 -11 1 -.names [8298] [1273] [8296] [1270] new_D[89] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8280]* [7600]* [1264] -11 1 -.names D[86]* [7397] -1 1 -.names I1740 I1739 [8301] -1- 1 --1 1 -.names [7597]* [7397]* I1739 -11 1 -.names [7598]* [7377]* I1740 -11 1 -.names key[222]* [8304] -1 1 -.names [8304]* [7581]* [1267] -11 1 -.names I1745 I1744 [8303] -1- 1 --1 1 -.names [7602]* [7383]* I1744 -11 1 -.names [8299]* [7604]* I1745 -11 1 -.names [8303] [1267] [8301] [1264] new_D[88] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7383]* [1258] -11 1 -.names D[85]* [7393] -1 1 -.names I1751 I1750 [8306] -1- 1 --1 1 -.names [7597]* [7393]* I1750 -11 1 -.names [7598]* [7397]* I1751 -11 1 -.names key[230]* [8309] -1 1 -.names [8309]* [7581]* [1261] -11 1 -.names I1756 I1755 [8308] -1- 1 --1 1 -.names [7602]* [7389]* I1755 -11 1 -.names [8304]* [7604]* I1756 -11 1 -.names [8308] [1261] [8306] [1258] new_D[87] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7389]* [1252] -11 1 -.names D[84]* [7378] -1 1 -.names I1762 I1761 [8311] -1- 1 --1 1 -.names [7597]* [7378]* I1761 -11 1 -.names [7598]* [7393]* I1762 -11 1 -.names key[238]* [8314] -1 1 -.names [8314]* [7581]* [1255] -11 1 -.names I1767 I1766 [8313] -1- 1 --1 1 -.names [7602]* [7377]* I1766 -11 1 -.names [8309]* [7604]* I1767 -11 1 -.names [8313] [1255] [8311] [1252] new_D[86] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7377]* [1246] -11 1 -.names D[83]* [7407] -1 1 -.names I1773 I1772 [8316] -1- 1 --1 1 -.names [7597]* [7407]* I1772 -11 1 -.names [7598]* [7378]* I1773 -11 1 -.names key[246]* [8319] -1 1 -.names [8319]* [7581]* [1249] -11 1 -.names I1778 I1777 [8318] -1- 1 --1 1 -.names [7602]* [7397]* I1777 -11 1 -.names [8314]* [7604]* I1778 -11 1 -.names [8318] [1249] [8316] [1246] new_D[85] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7397]* [1240] -11 1 -.names D[82]* [7417] -1 1 -.names I1784 I1783 [8321] -1- 1 --1 1 -.names [7597]* [7417]* I1783 -11 1 -.names [7598]* [7407]* I1784 -11 1 -.names key[254]* [8324] -1 1 -.names [8324]* [7581]* [1243] -11 1 -.names I1789 I1788 [8323] -1- 1 --1 1 -.names [7602]* [7393]* I1788 -11 1 -.names [8319]* [7604]* I1789 -11 1 -.names [8323] [1243] [8321] [1240] new_D[84] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7393]* [1234] -11 1 -.names D[81]* [8326] -1 1 -.names I1795 I1794 [8327] -1- 1 --1 1 -.names [8326]* [7597]* I1794 -11 1 -.names [7598]* [7417]* I1795 -11 1 -.names key[131]* [8330] -1 1 -.names [8330]* [7581]* [1237] -11 1 -.names I1800 I1799 [8329] -1- 1 --1 1 -.names [7602]* [7378]* I1799 -11 1 -.names [8324]* [7604]* I1800 -11 1 -.names [8329] [1237] [8327] [1234] new_D[83] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7378]* [1228] -11 1 -.names D[80]* [7405] -1 1 -.names I1806 I1805 [8332] -1- 1 --1 1 -.names [7597]* [7405]* I1805 -11 1 -.names [8326]* [7598]* I1806 -11 1 -.names key[139]* [8335] -1 1 -.names [8335]* [7581]* [1231] -11 1 -.names I1811 I1810 [8334] -1- 1 --1 1 -.names [7602]* [7407]* I1810 -11 1 -.names [8330]* [7604]* I1811 -11 1 -.names [8334] [1231] [8332] [1228] new_D[82] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7407]* [1222] -11 1 -.names D[79]* [7421] -1 1 -.names I1817 I1816 [8337] -1- 1 --1 1 -.names [7597]* [7421]* I1816 -11 1 -.names [7598]* [7405]* I1817 -11 1 -.names key[147]* [8340] -1 1 -.names [8340]* [7581]* [1225] -11 1 -.names I1822 I1821 [8339] -1- 1 --1 1 -.names [7602]* [7417]* I1821 -11 1 -.names [8335]* [7604]* I1822 -11 1 -.names [8339] [1225] [8337] [1222] new_D[81] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7417]* [1216] -11 1 -.names D[78]* [7414] -1 1 -.names I1828 I1827 [8342] -1- 1 --1 1 -.names [7597]* [7414]* I1827 -11 1 -.names [7598]* [7421]* I1828 -11 1 -.names key[155]* [8345] -1 1 -.names [8345]* [7581]* [1219] -11 1 -.names I1833 I1832 [8344] -1- 1 --1 1 -.names [8326]* [7602]* I1832 -11 1 -.names [8340]* [7604]* I1833 -11 1 -.names [8344] [1219] [8342] [1216] new_D[80] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8326]* [7600]* [1210] -11 1 -.names D[77]* [7402] -1 1 -.names I1839 I1838 [8347] -1- 1 --1 1 -.names [7597]* [7402]* I1838 -11 1 -.names [7598]* [7414]* I1839 -11 1 -.names key[132]* [8350] -1 1 -.names [8350]* [7581]* [1213] -11 1 -.names I1844 I1843 [8349] -1- 1 --1 1 -.names [7602]* [7405]* I1843 -11 1 -.names [8345]* [7604]* I1844 -11 1 -.names [8349] [1213] [8347] [1210] new_D[79] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7405]* [1204] -11 1 -.names D[76]* [7409] -1 1 -.names I1850 I1849 [8352] -1- 1 --1 1 -.names [7597]* [7409]* I1849 -11 1 -.names [7598]* [7402]* I1850 -11 1 -.names key[140]* [8355] -1 1 -.names [8355]* [7581]* [1207] -11 1 -.names I1855 I1854 [8354] -1- 1 --1 1 -.names [7602]* [7421]* I1854 -11 1 -.names [8350]* [7604]* I1855 -11 1 -.names [8354] [1207] [8352] [1204] new_D[78] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7421]* [1198] -11 1 -.names D[75]* [7411] -1 1 -.names I1861 I1860 [8357] -1- 1 --1 1 -.names [7597]* [7411]* I1860 -11 1 -.names [7598]* [7409]* I1861 -11 1 -.names key[148]* [8360] -1 1 -.names [8360]* [7581]* [1201] -11 1 -.names I1866 I1865 [8359] -1- 1 --1 1 -.names [7602]* [7414]* I1865 -11 1 -.names [8355]* [7604]* I1866 -11 1 -.names [8359] [1201] [8357] [1198] new_D[77] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7414]* [1192] -11 1 -.names D[74]* [7418] -1 1 -.names I1872 I1871 [8362] -1- 1 --1 1 -.names [7597]* [7418]* I1871 -11 1 -.names [7598]* [7411]* I1872 -11 1 -.names key[156]* [8365] -1 1 -.names [8365]* [7581]* [1195] -11 1 -.names I1877 I1876 [8364] -1- 1 --1 1 -.names [7602]* [7402]* I1876 -11 1 -.names [8360]* [7604]* I1877 -11 1 -.names [8364] [1195] [8362] [1192] new_D[76] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7402]* [1186] -11 1 -.names D[73]* [7404] -1 1 -.names I1883 I1882 [8367] -1- 1 --1 1 -.names [7597]* [7404]* I1882 -11 1 -.names [7598]* [7418]* I1883 -11 1 -.names key[164]* [8370] -1 1 -.names [8370]* [7581]* [1189] -11 1 -.names I1888 I1887 [8369] -1- 1 --1 1 -.names [7602]* [7409]* I1887 -11 1 -.names [8365]* [7604]* I1888 -11 1 -.names [8369] [1189] [8367] [1186] new_D[75] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7409]* [1180] -11 1 -.names D[72]* [8372] -1 1 -.names I1894 I1893 [8373] -1- 1 --1 1 -.names [8372]* [7597]* I1893 -11 1 -.names [7598]* [7404]* I1894 -11 1 -.names [8229]* [7581]* [1183] -11 1 -.names I1898 I1897 [8375] -1- 1 --1 1 -.names [7602]* [7411]* I1897 -11 1 -.names [8370]* [7604]* I1898 -11 1 -.names [8375] [1183] [8373] [1180] new_D[74] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7411]* [1174] -11 1 -.names D[71]* [7410] -1 1 -.names I1904 I1903 [8377] -1- 1 --1 1 -.names [7597]* [7410]* I1903 -11 1 -.names [8372]* [7598]* I1904 -11 1 -.names key[180]* [8380] -1 1 -.names [8380]* [7581]* [1177] -11 1 -.names I1909 I1908 [8379] -1- 1 --1 1 -.names [7602]* [7418]* I1908 -11 1 -.names [8229]* [7604]* I1909 -11 1 -.names [8379] [1177] [8377] [1174] new_D[73] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7418]* [1168] -11 1 -.names D[70]* [7413] -1 1 -.names I1915 I1914 [8382] -1- 1 --1 1 -.names [7597]* [7413]* I1914 -11 1 -.names [7598]* [7410]* I1915 -11 1 -.names key[188]* [8385] -1 1 -.names [8385]* [7581]* [1171] -11 1 -.names I1920 I1919 [8384] -1- 1 --1 1 -.names [7602]* [7404]* I1919 -11 1 -.names [8380]* [7604]* I1920 -11 1 -.names [8384] [1171] [8382] [1168] new_D[72] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7404]* [1162] -11 1 -.names D[69]* [7403] -1 1 -.names I1926 I1925 [8387] -1- 1 --1 1 -.names [7597]* [7403]* I1925 -11 1 -.names [7598]* [7413]* I1926 -11 1 -.names key[133]* [8390] -1 1 -.names [8390]* [7581]* [1165] -11 1 -.names I1931 I1930 [8389] -1- 1 --1 1 -.names [8372]* [7602]* I1930 -11 1 -.names [8385]* [7604]* I1931 -11 1 -.names [8389] [1165] [8387] [1162] new_D[71] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8372]* [7600]* [1156] -11 1 -.names D[68]* [7422] -1 1 -.names I1937 I1936 [8392] -1- 1 --1 1 -.names [7597]* [7422]* I1936 -11 1 -.names [7598]* [7403]* I1937 -11 1 -.names key[141]* [8395] -1 1 -.names [8395]* [7581]* [1159] -11 1 -.names I1942 I1941 [8394] -1- 1 --1 1 -.names [7602]* [7410]* I1941 -11 1 -.names [8390]* [7604]* I1942 -11 1 -.names [8394] [1159] [8392] [1156] new_D[70] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7410]* [1150] -11 1 -.names D[67]* [7415] -1 1 -.names I1948 I1947 [8397] -1- 1 --1 1 -.names [7597]* [7415]* I1947 -11 1 -.names [7598]* [7422]* I1948 -11 1 -.names key[149]* [8400] -1 1 -.names [8400]* [7581]* [1153] -11 1 -.names I1953 I1952 [8399] -1- 1 --1 1 -.names [7602]* [7413]* I1952 -11 1 -.names [8395]* [7604]* I1953 -11 1 -.names [8399] [1153] [8397] [1150] new_D[69] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7413]* [1144] -11 1 -.names D[66]* [7408] -1 1 -.names I1959 I1958 [8402] -1- 1 --1 1 -.names [7597]* [7408]* I1958 -11 1 -.names [7598]* [7415]* I1959 -11 1 -.names key[157]* [8405] -1 1 -.names [8405]* [7581]* [1147] -11 1 -.names I1964 I1963 [8404] -1- 1 --1 1 -.names [7602]* [7403]* I1963 -11 1 -.names [8400]* [7604]* I1964 -11 1 -.names [8404] [1147] [8402] [1144] new_D[68] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7403]* [1138] -11 1 -.names D[65]* [8407] -1 1 -.names I1970 I1969 [8408] -1- 1 --1 1 -.names [8407]* [7597]* I1969 -11 1 -.names [7598]* [7408]* I1970 -11 1 -.names key[165]* [8411] -1 1 -.names [8411]* [7581]* [1141] -11 1 -.names I1975 I1974 [8410] -1- 1 --1 1 -.names [7602]* [7422]* I1974 -11 1 -.names [8405]* [7604]* I1975 -11 1 -.names [8410] [1141] [8408] [1138] new_D[67] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7422]* [1132] -11 1 -.names D[64]* [7419] -1 1 -.names I1981 I1980 [8413] -1- 1 --1 1 -.names [7597]* [7419]* I1980 -11 1 -.names [8407]* [7598]* I1981 -11 1 -.names key[173]* [8416] -1 1 -.names [8416]* [7581]* [1135] -11 1 -.names I1986 I1985 [8415] -1- 1 --1 1 -.names [7602]* [7415]* I1985 -11 1 -.names [8411]* [7604]* I1986 -11 1 -.names [8415] [1135] [8413] [1132] new_D[66] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7415]* [1126] -11 1 -.names D[63]* [7401] -1 1 -.names I1992 I1991 [8418] -1- 1 --1 1 -.names [7597]* [7401]* I1991 -11 1 -.names [7598]* [7419]* I1992 -11 1 -.names key[181]* [8421] -1 1 -.names [8421]* [7581]* [1129] -11 1 -.names I1997 I1996 [8420] -1- 1 --1 1 -.names [7602]* [7408]* I1996 -11 1 -.names [8416]* [7604]* I1997 -11 1 -.names [8420] [1129] [8418] [1126] new_D[65] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7408]* [1120] -11 1 -.names D[62]* [8423] -1 1 -.names I2003 I2002 [8424] -1- 1 --1 1 -.names [8423]* [7597]* I2002 -11 1 -.names [7598]* [7401]* I2003 -11 1 -.names key[189]* [8427] -1 1 -.names [8427]* [7581]* [1123] -11 1 -.names I2008 I2007 [8426] -1- 1 --1 1 -.names [8407]* [7602]* I2007 -11 1 -.names [8421]* [7604]* I2008 -11 1 -.names [8426] [1123] [8424] [1120] new_D[64] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8407]* [7600]* [1114] -11 1 -.names D[61]* [7406] -1 1 -.names I2014 I2013 [8429] -1- 1 --1 1 -.names [7597]* [7406]* I2013 -11 1 -.names [8423]* [7598]* I2014 -11 1 -.names key[134]* [8432] -1 1 -.names [8432]* [7581]* [1117] -11 1 -.names I2019 I2018 [8431] -1- 1 --1 1 -.names [7602]* [7419]* I2018 -11 1 -.names [8427]* [7604]* I2019 -11 1 -.names [8431] [1117] [8429] [1114] new_D[63] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7419]* [1108] -11 1 -.names D[60]* [7412] -1 1 -.names I2025 I2024 [8434] -1- 1 --1 1 -.names [7597]* [7412]* I2024 -11 1 -.names [7598]* [7406]* I2025 -11 1 -.names key[142]* [8437] -1 1 -.names [8437]* [7581]* [1111] -11 1 -.names I2030 I2029 [8436] -1- 1 --1 1 -.names [7602]* [7401]* I2029 -11 1 -.names [8432]* [7604]* I2030 -11 1 -.names [8436] [1111] [8434] [1108] new_D[62] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7401]* [1102] -11 1 -.names D[59]* [7399] -1 1 -.names I2036 I2035 [8439] -1- 1 --1 1 -.names [7597]* [7399]* I2035 -11 1 -.names [7598]* [7412]* I2036 -11 1 -.names key[150]* [8442] -1 1 -.names [8442]* [7581]* [1105] -11 1 -.names I2041 I2040 [8441] -1- 1 --1 1 -.names [8423]* [7602]* I2040 -11 1 -.names [8437]* [7604]* I2041 -11 1 -.names [8441] [1105] [8439] [1102] new_D[61] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8423]* [7600]* [1096] -11 1 -.names D[58]* [7420] -1 1 -.names I2047 I2046 [8444] -1- 1 --1 1 -.names [7597]* [7420]* I2046 -11 1 -.names [7598]* [7399]* I2047 -11 1 -.names key[158]* [8447] -1 1 -.names [8447]* [7581]* [1099] -11 1 -.names I2052 I2051 [8446] -1- 1 --1 1 -.names [7602]* [7406]* I2051 -11 1 -.names [8442]* [7604]* I2052 -11 1 -.names [8446] [1099] [8444] [1096] new_D[60] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7406]* [1090] -11 1 -.names D[57]* [7416] -1 1 -.names I2058 I2057 [8449] -1- 1 --1 1 -.names [7597]* [7416]* I2057 -11 1 -.names [7598]* [7420]* I2058 -11 1 -.names key[166]* [8452] -1 1 -.names [8452]* [7581]* [1093] -11 1 -.names I2063 I2062 [8451] -1- 1 --1 1 -.names [7602]* [7412]* I2062 -11 1 -.names [8447]* [7604]* I2063 -11 1 -.names [8451] [1093] [8449] [1090] new_D[59] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7412]* [1084] -11 1 -.names D[56]* [7400] -1 1 -.names I2069 I2068 [8454] -1- 1 --1 1 -.names [7597]* [7400]* I2068 -11 1 -.names [7598]* [7416]* I2069 -11 1 -.names key[174]* [8457] -1 1 -.names [8457]* [7581]* [1087] -11 1 -.names I2074 I2073 [8456] -1- 1 --1 1 -.names [7602]* [7399]* I2073 -11 1 -.names [8452]* [7604]* I2074 -11 1 -.names [8456] [1087] [8454] [1084] new_D[58] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7399]* [1078] -11 1 -.names D[55]* [7430] -1 1 -.names I2080 I2079 [8459] -1- 1 --1 1 -.names [7597]* [7430]* I2079 -11 1 -.names [7598]* [7400]* I2080 -11 1 -.names key[182]* [8462] -1 1 -.names [8462]* [7581]* [1081] -11 1 -.names I2085 I2084 [8461] -1- 1 --1 1 -.names [7602]* [7420]* I2084 -11 1 -.names [8457]* [7604]* I2085 -11 1 -.names [8461] [1081] [8459] [1078] new_D[57] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7420]* [1072] -11 1 -.names D[54]* [7440] -1 1 -.names I2091 I2090 [8464] -1- 1 --1 1 -.names [7597]* [7440]* I2090 -11 1 -.names [7598]* [7430]* I2091 -11 1 -.names key[190]* [8467] -1 1 -.names [8467]* [7581]* [1075] -11 1 -.names I2096 I2095 [8466] -1- 1 --1 1 -.names [7602]* [7416]* I2095 -11 1 -.names [8462]* [7604]* I2096 -11 1 -.names [8466] [1075] [8464] [1072] new_D[56] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7416]* [1066] -11 1 -.names D[53]* [8469] -1 1 -.names I2102 I2101 [8470] -1- 1 --1 1 -.names [8469]* [7597]* I2101 -11 1 -.names [7598]* [7440]* I2102 -11 1 -.names key[67]* [8473] -1 1 -.names [8473]* [7581]* [1069] -11 1 -.names I2107 I2106 [8472] -1- 1 --1 1 -.names [7602]* [7400]* I2106 -11 1 -.names [8467]* [7604]* I2107 -11 1 -.names [8472] [1069] [8470] [1066] new_D[55] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7400]* [1060] -11 1 -.names D[52]* [7428] -1 1 -.names I2113 I2112 [8475] -1- 1 --1 1 -.names [7597]* [7428]* I2112 -11 1 -.names [8469]* [7598]* I2113 -11 1 -.names key[75]* [8478] -1 1 -.names [8478]* [7581]* [1063] -11 1 -.names I2118 I2117 [8477] -1- 1 --1 1 -.names [7602]* [7430]* I2117 -11 1 -.names [8473]* [7604]* I2118 -11 1 -.names [8477] [1063] [8475] [1060] new_D[54] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7430]* [1054] -11 1 -.names D[51]* [7444] -1 1 -.names I2124 I2123 [8480] -1- 1 --1 1 -.names [7597]* [7444]* I2123 -11 1 -.names [7598]* [7428]* I2124 -11 1 -.names key[83]* [8483] -1 1 -.names [8483]* [7581]* [1057] -11 1 -.names I2129 I2128 [8482] -1- 1 --1 1 -.names [7602]* [7440]* I2128 -11 1 -.names [8478]* [7604]* I2129 -11 1 -.names [8482] [1057] [8480] [1054] new_D[53] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7440]* [1048] -11 1 -.names D[50]* [7437] -1 1 -.names I2135 I2134 [8485] -1- 1 --1 1 -.names [7597]* [7437]* I2134 -11 1 -.names [7598]* [7444]* I2135 -11 1 -.names key[91]* [8488] -1 1 -.names [8488]* [7581]* [1051] -11 1 -.names I2140 I2139 [8487] -1- 1 --1 1 -.names [8469]* [7602]* I2139 -11 1 -.names [8483]* [7604]* I2140 -11 1 -.names [8487] [1051] [8485] [1048] new_D[52] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8469]* [7600]* [1042] -11 1 -.names D[49]* [7426] -1 1 -.names I2146 I2145 [8490] -1- 1 --1 1 -.names [7597]* [7426]* I2145 -11 1 -.names [7598]* [7437]* I2146 -11 1 -.names key[68]* [8493] -1 1 -.names [8493]* [7581]* [1045] -11 1 -.names I2151 I2150 [8492] -1- 1 --1 1 -.names [7602]* [7428]* I2150 -11 1 -.names [8488]* [7604]* I2151 -11 1 -.names [8492] [1045] [8490] [1042] new_D[51] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7428]* [1036] -11 1 -.names D[48]* [7432] -1 1 -.names I2157 I2156 [8495] -1- 1 --1 1 -.names [7597]* [7432]* I2156 -11 1 -.names [7598]* [7426]* I2157 -11 1 -.names key[76]* [8498] -1 1 -.names [8498]* [7581]* [1039] -11 1 -.names I2162 I2161 [8497] -1- 1 --1 1 -.names [7602]* [7444]* I2161 -11 1 -.names [8493]* [7604]* I2162 -11 1 -.names [8497] [1039] [8495] [1036] new_D[50] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7444]* [1030] -11 1 -.names D[47]* [7434] -1 1 -.names I2168 I2167 [8500] -1- 1 --1 1 -.names [7597]* [7434]* I2167 -11 1 -.names [7598]* [7432]* I2168 -11 1 -.names key[84]* [8503] -1 1 -.names [8503]* [7581]* [1033] -11 1 -.names I2173 I2172 [8502] -1- 1 --1 1 -.names [7602]* [7437]* I2172 -11 1 -.names [8498]* [7604]* I2173 -11 1 -.names [8502] [1033] [8500] [1030] new_D[49] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7437]* [1024] -11 1 -.names D[46]* [7441] -1 1 -.names I2179 I2178 [8505] -1- 1 --1 1 -.names [7597]* [7441]* I2178 -11 1 -.names [7598]* [7434]* I2179 -11 1 -.names key[92]* [8508] -1 1 -.names [8508]* [7581]* [1027] -11 1 -.names I2184 I2183 [8507] -1- 1 --1 1 -.names [7602]* [7426]* I2183 -11 1 -.names [8503]* [7604]* I2184 -11 1 -.names [8507] [1027] [8505] [1024] new_D[48] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7426]* [1018] -11 1 -.names D[45]* [7427] -1 1 -.names I2190 I2189 [8510] -1- 1 --1 1 -.names [7597]* [7427]* I2189 -11 1 -.names [7598]* [7441]* I2190 -11 1 -.names key[100]* [8513] -1 1 -.names [8513]* [7581]* [1021] -11 1 -.names I2195 I2194 [8512] -1- 1 --1 1 -.names [7602]* [7432]* I2194 -11 1 -.names [8508]* [7604]* I2195 -11 1 -.names [8512] [1021] [8510] [1018] new_D[47] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7432]* [1012] -11 1 -.names D[44]* [7436] -1 1 -.names I2201 I2200 [8515] -1- 1 --1 1 -.names [7597]* [7436]* I2200 -11 1 -.names [7598]* [7427]* I2201 -11 1 -.names key[44]* [8518] -1 1 -.names [8518]* [7581]* [1015] -11 1 -.names I2206 I2205 [8517] -1- 1 --1 1 -.names [7602]* [7434]* I2205 -11 1 -.names [8513]* [7604]* I2206 -11 1 -.names [8517] [1015] [8515] [1012] new_D[46] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7434]* [1006] -11 1 -.names D[43]* [7433] -1 1 -.names I2212 I2211 [8520] -1- 1 --1 1 -.names [7597]* [7433]* I2211 -11 1 -.names [7598]* [7436]* I2212 -11 1 -.names key[116]* [8523] -1 1 -.names [8523]* [7581]* [1009] -11 1 -.names I2217 I2216 [8522] -1- 1 --1 1 -.names [7602]* [7441]* I2216 -11 1 -.names [8518]* [7604]* I2217 -11 1 -.names [8522] [1009] [8520] [1006] new_D[45] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7441]* [1000] -11 1 -.names D[42]* [8525] -1 1 -.names I2223 I2222 [8526] -1- 1 --1 1 -.names [8525]* [7597]* I2222 -11 1 -.names [7598]* [7433]* I2223 -11 1 -.names key[124]* [8529] -1 1 -.names [8529]* [7581]* [1003] -11 1 -.names I2228 I2227 [8528] -1- 1 --1 1 -.names [7602]* [7427]* I2227 -11 1 -.names [8523]* [7604]* I2228 -11 1 -.names [8528] [1003] [8526] [1000] new_D[44] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7427]* [994] -11 1 -.names D[41]* [8531] -1 1 -.names I2234 I2233 [8532] -1- 1 --1 1 -.names [8531]* [7597]* I2233 -11 1 -.names [8525]* [7598]* I2234 -11 1 -.names key[69]* [8535] -1 1 -.names [8535]* [7581]* [997] -11 1 -.names I2239 I2238 [8534] -1- 1 --1 1 -.names [7602]* [7436]* I2238 -11 1 -.names [8529]* [7604]* I2239 -11 1 -.names [8534] [997] [8532] [994] new_D[43] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7436]* [988] -11 1 -.names D[40]* [7445] -1 1 -.names I2245 I2244 [8537] -1- 1 --1 1 -.names [7597]* [7445]* I2244 -11 1 -.names [8531]* [7598]* I2245 -11 1 -.names key[77]* [8540] -1 1 -.names [8540]* [7581]* [991] -11 1 -.names I2250 I2249 [8539] -1- 1 --1 1 -.names [7602]* [7433]* I2249 -11 1 -.names [8535]* [7604]* I2250 -11 1 -.names [8539] [991] [8537] [988] new_D[42] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7433]* [982] -11 1 -.names D[39]* [7438] -1 1 -.names I2256 I2255 [8542] -1- 1 --1 1 -.names [7597]* [7438]* I2255 -11 1 -.names [7598]* [7445]* I2256 -11 1 -.names key[85]* [8545] -1 1 -.names [8545]* [7581]* [985] -11 1 -.names I2261 I2260 [8544] -1- 1 --1 1 -.names [8525]* [7602]* I2260 -11 1 -.names [8540]* [7604]* I2261 -11 1 -.names [8544] [985] [8542] [982] new_D[41] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8525]* [7600]* [976] -11 1 -.names D[38]* [7431] -1 1 -.names I2267 I2266 [8547] -1- 1 --1 1 -.names [7597]* [7431]* I2266 -11 1 -.names [7598]* [7438]* I2267 -11 1 -.names key[93]* [8550] -1 1 -.names [8550]* [7581]* [979] -11 1 -.names I2272 I2271 [8549] -1- 1 --1 1 -.names [8531]* [7602]* I2271 -11 1 -.names [8545]* [7604]* I2272 -11 1 -.names [8549] [979] [8547] [976] new_D[40] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8531]* [7600]* [970] -11 1 -.names D[37]* [8552] -1 1 -.names I2278 I2277 [8553] -1- 1 --1 1 -.names [8552]* [7597]* I2277 -11 1 -.names [7598]* [7431]* I2278 -11 1 -.names key[101]* [8556] -1 1 -.names [8556]* [7581]* [973] -11 1 -.names I2283 I2282 [8555] -1- 1 --1 1 -.names [7602]* [7445]* I2282 -11 1 -.names [8550]* [7604]* I2283 -11 1 -.names [8555] [973] [8553] [970] new_D[39] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7445]* [964] -11 1 -.names D[36]* [7442] -1 1 -.names I2289 I2288 [8558] -1- 1 --1 1 -.names [7597]* [7442]* I2288 -11 1 -.names [8552]* [7598]* I2289 -11 1 -.names key[109]* [8561] -1 1 -.names [8561]* [7581]* [967] -11 1 -.names I2294 I2293 [8560] -1- 1 --1 1 -.names [7602]* [7438]* I2293 -11 1 -.names [8556]* [7604]* I2294 -11 1 -.names [8560] [967] [8558] [964] new_D[38] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7438]* [958] -11 1 -.names D[35]* [7425] -1 1 -.names I2300 I2299 [8563] -1- 1 --1 1 -.names [7597]* [7425]* I2299 -11 1 -.names [7598]* [7442]* I2300 -11 1 -.names key[117]* [8566] -1 1 -.names [8566]* [7581]* [961] -11 1 -.names I2305 I2304 [8565] -1- 1 --1 1 -.names [7602]* [7431]* I2304 -11 1 -.names [8561]* [7604]* I2305 -11 1 -.names [8565] [961] [8563] [958] new_D[37] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7431]* [952] -11 1 -.names D[34]* [8568] -1 1 -.names I2311 I2310 [8569] -1- 1 --1 1 -.names [8568]* [7597]* I2310 -11 1 -.names [7598]* [7425]* I2311 -11 1 -.names key[125]* [8572] -1 1 -.names [8572]* [7581]* [955] -11 1 -.names I2316 I2315 [8571] -1- 1 --1 1 -.names [8552]* [7602]* I2315 -11 1 -.names [8566]* [7604]* I2316 -11 1 -.names [8571] [955] [8569] [952] new_D[36] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8552]* [7600]* [946] -11 1 -.names D[33]* [7429] -1 1 -.names I2322 I2321 [8574] -1- 1 --1 1 -.names [7597]* [7429]* I2321 -11 1 -.names [8568]* [7598]* I2322 -11 1 -.names key[70]* [8577] -1 1 -.names [8577]* [7581]* [949] -11 1 -.names I2327 I2326 [8576] -1- 1 --1 1 -.names [7602]* [7442]* I2326 -11 1 -.names [8572]* [7604]* I2327 -11 1 -.names [8576] [949] [8574] [946] new_D[35] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7442]* [940] -11 1 -.names D[32]* [7435] -1 1 -.names I2333 I2332 [8579] -1- 1 --1 1 -.names [7597]* [7435]* I2332 -11 1 -.names [7598]* [7429]* I2333 -11 1 -.names key[78]* [8582] -1 1 -.names [8582]* [7581]* [943] -11 1 -.names I2338 I2337 [8581] -1- 1 --1 1 -.names [7602]* [7425]* I2337 -11 1 -.names [8577]* [7604]* I2338 -11 1 -.names [8581] [943] [8579] [940] new_D[34] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7425]* [934] -11 1 -.names D[31]* [7423] -1 1 -.names I2344 I2343 [8584] -1- 1 --1 1 -.names [7597]* [7423]* I2343 -11 1 -.names [7598]* [7435]* I2344 -11 1 -.names key[86]* [8587] -1 1 -.names [8587]* [7581]* [937] -11 1 -.names I2349 I2348 [8586] -1- 1 --1 1 -.names [8568]* [7602]* I2348 -11 1 -.names [8582]* [7604]* I2349 -11 1 -.names [8586] [937] [8584] [934] new_D[33] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8568]* [7600]* [928] -11 1 -.names D[30]* [7443] -1 1 -.names I2355 I2354 [8589] -1- 1 --1 1 -.names [7597]* [7443]* I2354 -11 1 -.names [7598]* [7423]* I2355 -11 1 -.names key[94]* [8592] -1 1 -.names [8592]* [7581]* [931] -11 1 -.names I2360 I2359 [8591] -1- 1 --1 1 -.names [7602]* [7429]* I2359 -11 1 -.names [8587]* [7604]* I2360 -11 1 -.names [8591] [931] [8589] [928] new_D[32] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7429]* [922] -11 1 -.names D[29]* [7439] -1 1 -.names I2366 I2365 [8594] -1- 1 --1 1 -.names [7597]* [7439]* I2365 -11 1 -.names [7598]* [7443]* I2366 -11 1 -.names key[102]* [8597] -1 1 -.names [8597]* [7581]* [925] -11 1 -.names I2371 I2370 [8596] -1- 1 --1 1 -.names [7602]* [7435]* I2370 -11 1 -.names [8592]* [7604]* I2371 -11 1 -.names [8596] [925] [8594] [922] new_D[31] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7435]* [916] -11 1 -.names D[28]* [7424] -1 1 -.names I2377 I2376 [8599] -1- 1 --1 1 -.names [7597]* [7424]* I2376 -11 1 -.names [7598]* [7439]* I2377 -11 1 -.names key[110]* [8602] -1 1 -.names [8602]* [7581]* [919] -11 1 -.names I2382 I2381 [8601] -1- 1 --1 1 -.names [7602]* [7423]* I2381 -11 1 -.names [8597]* [7604]* I2382 -11 1 -.names [8601] [919] [8599] [916] new_D[30] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7423]* [910] -11 1 -.names D[27]* [7454] -1 1 -.names I2388 I2387 [8604] -1- 1 --1 1 -.names [7597]* [7454]* I2387 -11 1 -.names [7598]* [7424]* I2388 -11 1 -.names key[118]* [8607] -1 1 -.names [8607]* [7581]* [913] -11 1 -.names I2393 I2392 [8606] -1- 1 --1 1 -.names [7602]* [7443]* I2392 -11 1 -.names [8602]* [7604]* I2393 -11 1 -.names [8606] [913] [8604] [910] new_D[29] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7443]* [904] -11 1 -.names D[26]* [7464] -1 1 -.names I2399 I2398 [8609] -1- 1 --1 1 -.names [7597]* [7464]* I2398 -11 1 -.names [7598]* [7454]* I2399 -11 1 -.names key[126]* [8612] -1 1 -.names [8612]* [7581]* [907] -11 1 -.names I2404 I2403 [8611] -1- 1 --1 1 -.names [7602]* [7439]* I2403 -11 1 -.names [8607]* [7604]* I2404 -11 1 -.names [8611] [907] [8609] [904] new_D[28] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7439]* [898] -11 1 -.names D[25]* [8614] -1 1 -.names I2410 I2409 [8615] -1- 1 --1 1 -.names [8614]* [7597]* I2409 -11 1 -.names [7598]* [7464]* I2410 -11 1 -.names key[3]* [8618] -1 1 -.names [8618]* [7581]* [901] -11 1 -.names I2415 I2414 [8617] -1- 1 --1 1 -.names [7602]* [7424]* I2414 -11 1 -.names [8612]* [7604]* I2415 -11 1 -.names [8617] [901] [8615] [898] new_D[27] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7424]* [892] -11 1 -.names D[24]* [7452] -1 1 -.names I2421 I2420 [8620] -1- 1 --1 1 -.names [7597]* [7452]* I2420 -11 1 -.names [8614]* [7598]* I2421 -11 1 -.names key[11]* [8623] -1 1 -.names [8623]* [7581]* [895] -11 1 -.names I2426 I2425 [8622] -1- 1 --1 1 -.names [7602]* [7454]* I2425 -11 1 -.names [8618]* [7604]* I2426 -11 1 -.names [8622] [895] [8620] [892] new_D[26] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7454]* [886] -11 1 -.names D[23]* [7468] -1 1 -.names I2432 I2431 [8625] -1- 1 --1 1 -.names [7597]* [7468]* I2431 -11 1 -.names [7598]* [7452]* I2432 -11 1 -.names key[19]* [8628] -1 1 -.names [8628]* [7581]* [889] -11 1 -.names I2437 I2436 [8627] -1- 1 --1 1 -.names [7602]* [7464]* I2436 -11 1 -.names [8623]* [7604]* I2437 -11 1 -.names [8627] [889] [8625] [886] new_D[25] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7464]* [880] -11 1 -.names D[22]* [7461] -1 1 -.names I2443 I2442 [8630] -1- 1 --1 1 -.names [7597]* [7461]* I2442 -11 1 -.names [7598]* [7468]* I2443 -11 1 -.names key[27]* [8633] -1 1 -.names [8633]* [7581]* [883] -11 1 -.names I2448 I2447 [8632] -1- 1 --1 1 -.names [8614]* [7602]* I2447 -11 1 -.names [8628]* [7604]* I2448 -11 1 -.names [8632] [883] [8630] [880] new_D[24] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8614]* [7600]* [874] -11 1 -.names D[21]* [7449] -1 1 -.names I2454 I2453 [8635] -1- 1 --1 1 -.names [7597]* [7449]* I2453 -11 1 -.names [7598]* [7461]* I2454 -11 1 -.names key[4]* [8638] -1 1 -.names [8638]* [7581]* [877] -11 1 -.names I2459 I2458 [8637] -1- 1 --1 1 -.names [7602]* [7452]* I2458 -11 1 -.names [8633]* [7604]* I2459 -11 1 -.names [8637] [877] [8635] [874] new_D[23] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7600]* [7452]* [868] -11 1 -.names D[20]* [7456] -1 1 -.names I2465 I2464 [8640] -1- 1 --1 1 -.names [7597]* [7456]* I2464 -11 1 -.names [7598]* [7449]* I2465 -11 1 -.names key[12]* [8643] -1 1 -.names [8643]* [7581]* [871] -11 1 -.names I2470 I2469 [8642] -1- 1 --1 1 -.names [7602]* [7468]* I2469 -11 1 -.names [8638]* [7604]* I2470 -11 1 -.names [8642] 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[8597] [8597]* -0 1 -.names D[28] D[28]* -0 1 -.names [7424] [7424]* -0 1 -.names key[110] key[110]* -0 1 -.names [8602] [8602]* -0 1 -.names D[27] D[27]* -0 1 -.names [7454] [7454]* -0 1 -.names key[118] key[118]* -0 1 -.names [8607] [8607]* -0 1 -.names D[26] D[26]* -0 1 -.names [7464] [7464]* -0 1 -.names key[126] key[126]* -0 1 -.names [8612] [8612]* -0 1 -.names D[25] D[25]* -0 1 -.names [8614] [8614]* -0 1 -.names key[3] key[3]* -0 1 -.names [8618] [8618]* -0 1 -.names D[24] D[24]* -0 1 -.names [7452] [7452]* -0 1 -.names key[11] key[11]* -0 1 -.names [8623] [8623]* -0 1 -.names D[23] D[23]* -0 1 -.names [7468] [7468]* -0 1 -.names key[19] key[19]* -0 1 -.names [8628] [8628]* -0 1 -.names D[22] D[22]* -0 1 -.names [7461] [7461]* -0 1 -.names key[27] key[27]* -0 1 -.names [8633] [8633]* -0 1 -.names D[21] D[21]* -0 1 -.names [7449] [7449]* -0 1 -.names key[4] key[4]* -0 1 -.names [8638] [8638]* -0 1 -.names D[20] D[20]* -0 1 -.names [7456] [7456]* -0 1 -.names key[12] key[12]* -0 1 -.names [8643] [8643]* -0 1 -.names D[19] D[19]* -0 1 -.names [7458] [7458]* -0 1 -.names key[20] key[20]* -0 1 -.names [8648] [8648]* -0 1 -.names D[18] D[18]* -0 1 -.names [7465] [7465]* -0 1 -.names key[28] key[28]* -0 1 -.names [8653] [8653]* -0 1 -.names D[17] D[17]* -0 1 -.names [7451] [7451]* -0 1 -.names key[36] key[36]* -0 1 -.names [8658] [8658]* -0 1 -.names D[16] D[16]* -0 1 -.names [7460] [7460]* -0 1 -.names D[15] D[15]* -0 1 -.names [7457] [7457]* -0 1 -.names key[52] key[52]* -0 1 -.names [8667] [8667]* -0 1 -.names D[14] D[14]* -0 1 -.names [8669] [8669]* -0 1 -.names key[60] key[60]* -0 1 -.names [8673] [8673]* -0 1 -.names D[13] D[13]* -0 1 -.names [7450] [7450]* -0 1 -.names key[5] key[5]* -0 1 -.names [8678] [8678]* -0 1 -.names D[12] D[12]* -0 1 -.names [7469] [7469]* -0 1 -.names key[13] key[13]* -0 1 -.names [8683] [8683]* -0 1 -.names D[11] D[11]* -0 1 -.names [7462] [7462]* -0 1 -.names key[21] key[21]* -0 1 -.names [8688] [8688]* -0 1 -.names D[10] D[10]* -0 1 -.names [7455] [7455]* -0 1 -.names key[29] key[29]* -0 1 -.names [8693] [8693]* -0 1 -.names D[9] D[9]* -0 1 -.names [8695] [8695]* -0 1 -.names key[37] key[37]* -0 1 -.names [8699] [8699]* -0 1 -.names D[8] D[8]* -0 1 -.names [7466] [7466]* -0 1 -.names key[45] key[45]* -0 1 -.names [8704] [8704]* -0 1 -.names D[7] D[7]* -0 1 -.names [7448] [7448]* -0 1 -.names key[53] key[53]* -0 1 -.names [8709] [8709]* -0 1 -.names D[6] D[6]* -0 1 -.names [8711] [8711]* -0 1 -.names key[61] key[61]* -0 1 -.names [8715] [8715]* -0 1 -.names D[5] D[5]* -0 1 -.names [7453] [7453]* -0 1 -.names key[6] key[6]* -0 1 -.names [8720] [8720]* -0 1 -.names D[4] D[4]* -0 1 -.names [7459] [7459]* -0 1 -.names key[14] key[14]* -0 1 -.names [8725] [8725]* -0 1 -.names D[3] D[3]* -0 1 -.names [7446] [7446]* -0 1 -.names key[22] key[22]* -0 1 -.names [8730] [8730]* -0 1 -.names D[2] D[2]* -0 1 -.names [7467] [7467]* -0 1 -.names key[30] key[30]* -0 1 -.names [8735] [8735]* -0 1 -.names key[38] key[38]* -0 1 -.names [8740] [8740]* -0 1 -.names key[46] key[46]* -0 1 -.names [8745] [8745]* -0 1 -.names key[54] key[54]* -0 1 -.names [8750] [8750]* -0 1 -.names [7570] [7570]* -0 1 -.names [7596] [7596]* -0 1 -.names [8756] [8756]* -0 1 -.names [8757] [8757]* -0 1 -.end diff --git a/fpga_flow/benchmarks/Blif/MCNC_big20/elliptic.blif b/fpga_flow/benchmarks/Blif/MCNC_big20/elliptic.blif deleted file mode 100644 index d395d2dc4..000000000 --- a/fpga_flow/benchmarks/Blif/MCNC_big20/elliptic.blif +++ /dev/null @@ -1,1479 +0,0 @@ -.model TOP -.inputs PCLK PRESET Preset_0_0_ Pinp_0_0_ Pinp_1_1_ Pinp_2_2_ Pinp_3_3_ \ -Pinp_4_4_ Pinp_5_5_ Pinp_6_6_ Pinp_7_7_ Pinp_8_8_ Pinp_9_9_ Pinp_10_10_ \ -Pinp_11_11_ Pinp_12_12_ Pinp_13_13_ Pinp_14_14_ Pinp_15_15_ -.outputs PDN Pover_0_0_ -.latch N_N8025 N_N8199 re PCLK 2 -.latch N_N9279 N_N9280 re PCLK 2 -.latch N_N8802 N_N8803 re PCLK 2 -.latch N_N7548 N_N8240 re PCLK 2 -.latch N_N6924 N_N8274 re PCLK 2 -.latch N_N7048 N_N8198 re PCLK 2 -.latch N_N7371 N_N8239 re PCLK 2 -.latch N_N8614 N_N8615 re PCLK 2 -.latch N_N7294 N_N7703 re PCLK 2 -.latch N_N7007 N_N8273 re PCLK 2 -.latch N_N8365 N_N8366 re PCLK 2 -.latch N_N7894 N_N8272 re PCLK 2 -.latch N_N6941 N_N8238 re PCLK 2 -.latch N_N7547 N_N8531 re PCLK 2 -.latch N_N7982 N_N7983 re PCLK 2 -.latch N_N7131 N_N8575 re PCLK 2 -.latch N_N7000 N_N7854 re PCLK 2 -.latch N_N7633 N_N8237 re PCLK 2 -.latch N_N7447 N_N8197 re PCLK 2 -.latch N_N7047 N_N8271 re PCLK 2 -.latch N_N6982 N_N8530 re PCLK 2 -.latch N_N7785 N_N8650 re PCLK 2 -.latch N_N7984 N_N7985 re PCLK 2 -.latch N_N8709 N_N8710 re PCLK 2 -.latch N_N7006 N_N8574 re PCLK 2 -.latch N_N8311 N_N8312 re PCLK 2 -.latch N_N8190 N_N8270 re PCLK 2 -.latch N_N7063 N_N8573 re PCLK 2 -.latch N_N8934 N_N8935 re PCLK 2 -.latch N_N7280 N_N8649 re PCLK 2 -.latch N_N7893 N_N8196 re PCLK 2 -.latch N_N8137 N_N8236 re PCLK 2 -.latch N_N9243 N_N9244 re PCLK 2 -.latch N_N8347 N_N8348 re PCLK 2 -.latch N_N9149 N_N9150 re PCLK 2 -.latch N_N7194 N_N8648 re PCLK 2 -.latch N_N7313 N_N8269 re PCLK 2 -.latch N_N7465 N_N8235 re PCLK 2 -.latch N_N9274 N_N9275 re PCLK 2 -.latch N_N8969 N_N8970 re PCLK 2 -.latch N_N7266 N_N9554 re PCLK 2 -.latch N_N9012 N_N9013 re PCLK 2 -.latch N_N8507 N_N8508 re PCLK 2 -.latch N_N8136 N_N8529 re PCLK 2 -.latch N_N9241 N_N9242 re PCLK 2 -.latch N_N8169 N_N8572 re PCLK 2 -.latch N_N7312 N_N8571 re PCLK 2 -.latch N_N8363 N_N9436 re PCLK 2 -.latch N_N7377 N_N8528 re PCLK 2 -.latch N_N8795 N_N8796 re PCLK 2 -.latch N_N7001 N_N7770 re PCLK 2 -.latch N_N8364 N_N9357 re PCLK 2 -.latch N_N8684 N_N8685 re PCLK 2 -.latch N_N9295 N_N9296 re PCLK 2 -.latch N_N6995 N_N9555 re PCLK 2 -.latch N_N6971 N_N7628 re PCLK 2 -.latch N_N9509 N_N9510 re PCLK 2 -.latch N_N9577 N_N9578 re PCLK 2 -.latch N_N8446 N_N8447 re PCLK 2 -.latch N_N7137 N_N9437 re PCLK 2 -.latch N_N7042 N_N7771 re PCLK 2 -.latch N_N7305 N_N8570 re PCLK 2 -.latch N_N8527 N_N8647 re PCLK 2 -.latch N_N6957 N_N7704 re PCLK 2 -.latch N_N6926 N_N8646 re PCLK 2 -.latch N_N6958 N_N7629 re PCLK 2 -.latch N_N7096 NDN3_11 re PCLK 2 -.latch N_N7460 NDN3_12 re PCLK 2 -.latch N_N8036 N_N8037 re PCLK 2 -.latch N_N8540 NDN3_16 re PCLK 2 -.latch N_N7087 NDN3_17 re PCLK 2 -.latch N_N9543 NDN3_19 re PCLK 2 -.latch N_N7883 NDN3_22 re PCLK 2 -.latch N_N8293 NDN3_25 re PCLK 2 -.latch N_N9328 NDN3_26 re PCLK 2 -.latch N_N7301 N_N7584 re PCLK 2 -.latch N_N9620 NDN3_28 re PCLK 2 -.latch N_N8217 NDN3_29 re PCLK 2 -.latch N_N7158 NDN3_40 re PCLK 2 -.latch N_N9425 NDN3_39 re PCLK 2 -.latch N_N7690 NDN3_42 re PCLK 2 -.latch N_N7232 NDN3_44 re PCLK 2 -.latch N_N7574 NDN3_46 re PCLK 2 -.latch N_N7608 N_N9358 re PCLK 2 -.latch N_N9538 N_N9539 re PCLK 2 -.latch N_N7795 N_N9556 re PCLK 2 -.latch N_N8147 N_N7306 re PCLK 2 -.latch N_N7038 NEN3_16 re PCLK 2 -.latch N_N9111 N_N9160 re PCLK 2 -.latch N_N7477 NEN3_19 re PCLK 2 -.latch N_N8299 NEN3_22 re PCLK 2 -.latch N_N7077 N_N8930 re PCLK 2 -.latch N_N7529 NEN3_28 re PCLK 2 -.latch N_N7796 N_N9438 re PCLK 2 -.latch N_N8825 NEN3_34 re PCLK 2 -.latch N_N7891 NEN3_36 re PCLK 2 -.latch N_N8317 NEN3_39 re PCLK 2 -.latch N_N7960 N_N7961 re PCLK 2 -.latch N_N8814 NLC1_2 re PCLK 2 -.latch N_N7126 N_N9359 re PCLK 2 -.latch N_N7475 N_N7476 re PCLK 2 -.latch N_N8576 N_N8577 re PCLK 2 -.latch N_N8178 N_N9289 re PCLK 2 -.latch N_N7397 N_N9557 re PCLK 2 -.latch N_N7238 N_N7630 re PCLK 2 -.latch N_N8829 N_N9161 re PCLK 2 -.latch N_N8690 N_N8691 re PCLK 2 -.latch N_N7449 N_N9439 re PCLK 2 -.latch N_N7747 N_N8798 re PCLK 2 -.latch N_N7750 N_N8869 re PCLK 2 -.latch N_N7450 N_N9360 re PCLK 2 -.latch N_N7535 N_N8911 re PCLK 2 -.latch N_N7451 N_N9290 re PCLK 2 -.latch N_N6942 N_N9558 re PCLK 2 -.latch N_N8181 N_N8993 re PCLK 2 -.latch N_N9039 N_N9162 re PCLK 2 -.latch N_N7538 N_N9034 re PCLK 2 -.latch N_N7998 N_N9440 re PCLK 2 -.latch N_N7799 N_N9361 re PCLK 2 -.latch N_N9297 N_N9298 re PCLK 2 -.latch N_N8737 N_N9559 re PCLK 2 -.latch N_N7193 N_N9163 re PCLK 2 -.latch N_N9549 N_N9550 re PCLK 2 -.latch N_N7729 PDN re PCLK 2 -.latch N_N8170 N_N8171 re PCLK 2 -.latch N_N8172 N_N8173 re PCLK 2 -.latch N_N8385 N_N9011 re PCLK 2 -.latch N_N9551 N_N9552 re PCLK 2 -.latch N_N7515 N_N7701 re PCLK 2 -.latch N_N8286 N_N8964 re PCLK 2 -.latch N_N7957 N_N9291 re PCLK 2 -.latch N_N8345 N_N9560 re PCLK 2 -.latch N_N6917 N_N7627 re PCLK 2 -.latch N_N7095 N_N8913 re PCLK 2 -.latch N_N8755 N_N8756 re PCLK 2 -.latch N_N7059 N_N9164 re PCLK 2 -.latch N_N8015 N_N8016 re PCLK 2 -.latch N_N8952 N_N9441 re PCLK 2 -.latch N_N8283 N_N8847 re PCLK 2 -.latch N_N7094 N_N8631 re PCLK 2 -.latch N_N7870 N_N9362 re PCLK 2 -.latch N_N7199 Pover_0_0_ re PCLK 2 -.latch N_N7015 NDN1_4 re PCLK 2 -.latch N_N7439 N_N8561 re PCLK 2 -.latch N_N6927 N_N9292 re PCLK 2 -.latch N_N7470 N_N9561 re PCLK 2 -.latch N_N7098 NGFDN_3 re PCLK 2 -.latch N_N6928 N_N9165 re PCLK 2 -.latch N_N7382 N_N9442 re PCLK 2 -.latch N_N7528 N_N7768 re PCLK 2 -.latch N_N8117 N_N8118 re PCLK 2 -.latch N_N8122 NDN2_2 re PCLK 2 -.latch N_N8874 N_N8875 re PCLK 2 -.latch N_N7448 N_N7852 re PCLK 2 -.latch N_N7318 N_N7582 re PCLK 2 -.latch N_N9330 N_N9331 re PCLK 2 -.latch N_N7981 N_N9363 re PCLK 2 -.latch N_N9293 N_N9294 re PCLK 2 -.latch N_N9443 NDN3_2 re PCLK 2 -.latch N_N8565 NDN3_4 re PCLK 2 -.latch N_N8399 NDN3_7 re PCLK 2 -.latch N_N7188 NDN3_9 re PCLK 2 -.latch N_N9409 N_N9410 re PCLK 2 -.latch N_N8612 N_N8613 re PCLK 2 -.latch N_N8971 N_N8972 re PCLK 2 -.latch N_N9461 N_N9247 re PCLK 2 -.latch N_N7030 N_N9166 re PCLK 2 -.latch N_N8967 N_N8968 re PCLK 2 -.latch N_N8478 NAK3_13 re PCLK 2 -.latch N_N8451 N_N8668 re PCLK 2 -.latch N_N8922 N_N8923 re PCLK 2 -.latch N_N7162 N_N7769 re PCLK 2 -.latch N_N8926 N_N8933 re PCLK 2 -.latch N_N7163 N_N7702 re PCLK 2 -.latch N_N7828 N_N8978 re PCLK 2 -.latch N_N8140 N_N8141 re PCLK 2 -.latch N_N7132 N_N8200 re PCLK 2 -.latch N_N8722 N_N8929 re PCLK 2 -.latch N_N7446 N_N7853 re PCLK 2 -.latch N_N8356 N_N9031 re PCLK 2 -.latch N_N7379 N_N8241 re PCLK 2 -.latch N_N7357 N_N7583 re PCLK 2 -.latch N_N11 NSr3_13 re PCLK 2 -.latch N_N10 N_N9248 re PCLK 2 -.latch N_N9 NSr3_14 re PCLK 2 -.latch N_N8 NSr3_20 re PCLK 2 -.latch N_N7 N_N9198 re PCLK 2 -.latch N_N6 NSr3_23 re PCLK 2 -.latch N_N5 NSr3_30 re PCLK 2 -.latch N_N4 NSr3_35 re PCLK 2 -.latch N_N3 NSr3_37 re PCLK 2 -.latch N_N2 NSr3_38 re PCLK 2 -.latch N_N1 NSr1_2 re PCLK 2 -.latch N_N0 N_N8603 re PCLK 2 -.names NEN3_28 NDN3_28 n1826 N_N9620 -1-0 1 --10 1 -.names PRESET n1323 N_N9578 n16 -11- 1 --10 1 -.names n16 N_N9577 -0 1 -.names PRESET n2838 n22 -01 1 -.names N_N9552 n22 N_N9551 -11 1 -.names N_N9550 n22 N_N9549 -11 1 -.names NDN3_19 NEN3_19 n1826 N_N9543 -1-0 1 --10 1 -.names N_N9539 n22 N_N9538 -11 1 -.names N_N9510 n22 N_N9509 -11 1 -.names PRESET n413 n3115 N_N9247 n41 -0-1- 1 -00-1 1 -.names n41 N_N9248 N_N9461 -11 1 -.names NDN3_2 n1607 n1826 N_N9443 -1-0 1 --00 1 -.names NDN3_39 NEN3_39 n1826 N_N9425 -1-0 1 --10 1 -.names N_N9410 n22 N_N9409 -11 1 -.names N_N9331 n22 N_N9330 -11 1 -.names NDN3_26 NDN3_25 n1826 N_N9328 -1-0 1 --10 1 -.names N_N9298 n22 N_N9297 -11 1 -.names N_N9296 n22 N_N9295 -11 1 -.names N_N9294 n22 N_N9293 -11 1 -.names N_N9280 n22 N_N9279 -11 1 -.names N_N9275 n22 N_N9274 -11 1 -.names N_N9244 n22 N_N9243 -11 1 -.names N_N9242 n22 N_N9241 -11 1 -.names N_N9150 n22 N_N9149 -11 1 -.names PRESET n1323 N_N9160 n103 -11- 1 --10 1 -.names n103 N_N9111 -0 1 -.names PRESET n1323 N_N9162 n126 -11- 1 --10 1 -.names n126 N_N9039 -0 1 -.names N_N9013 n22 N_N9012 -11 1 -.names N_N8972 n22 N_N8971 -11 1 -.names N_N8970 n22 N_N8969 -11 1 -.names N_N8968 n22 N_N8967 -11 1 -.names N_N9441 n22 N_N8952 -11 1 -.names N_N8935 n22 N_N8934 -11 1 -.names PRESET n1804 n1807 N_N8933 n156 -1-1- 1 --11- 1 -1--0 1 --1-0 1 -.names n156 N_N8926 -0 1 -.names PRESET n1807 n1808 N_N8923 n157 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n157 N_N8922 -0 1 -.names N_N8875 n22 N_N8874 -11 1 -.names PRESET n1323 N_N9161 n191 -11- 1 --10 1 -.names n191 N_N8829 -0 1 -.names NEN3_34 n1826 NGFDN_3 n1855 n193 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n193 N_N8825 -0 1 -.names PRESET PDN n196 -00 1 -.names n196 NLC1_2 NSr1_2 N_N8814 -11- 1 -1-1 1 -.names N_N8803 n22 N_N8802 -11 1 -.names N_N8796 n22 N_N8795 -11 1 -.names N_N8756 n22 N_N8755 -11 1 -.names N_N9559 n22 N_N8737 -11 1 -.names N_N9198 n1799 n1800 n227 -101 1 -.names PRESET N_N8929 n227 N_N8722 -01- 1 -0-1 1 -.names N_N8710 n22 N_N8709 -11 1 -.names N_N8691 n22 N_N8690 -11 1 -.names N_N8685 n22 N_N8684 -11 1 -.names N_N8615 n22 N_N8614 -11 1 -.names N_N8613 n22 N_N8612 -11 1 -.names N_N8577 n22 N_N8576 -11 1 -.names NDN3_2 NDN3_4 n1826 N_N8565 -1-0 1 --10 1 -.names NDN3_16 NEN3_16 n1826 N_N8540 -1-0 1 --10 1 -.names N_N8647 n22 N_N8527 -11 1 -.names N_N8508 n22 N_N8507 -11 1 -.names PRESET n1798 N_N8478 -00 1 -.names PRESET n1798 n315 -01 1 -.names N_N8668 n315 N_N8451 -11 1 -.names N_N8447 n22 N_N8446 -11 1 -.names NDN3_4 NDN3_7 n1826 N_N8399 -1-0 1 --10 1 -.names PRESET n1807 n2064 N_N9011 n338 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n338 N_N8385 -0 1 -.names N_N8366 n22 N_N8365 -11 1 -.names N_N9357 n22 N_N8364 -11 1 -.names N_N9436 n22 N_N8363 -11 1 -.names PRESET n1807 n2079 N_N9031 n349 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n349 N_N8356 -0 1 -.names N_N8348 n22 N_N8347 -11 1 -.names N_N9560 n22 N_N8345 -11 1 -.names NEN3_39 n1826 NGFDN_3 n2093 n360 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n360 N_N8317 -0 1 -.names N_N8312 n22 N_N8311 -11 1 -.names NEN3_22 n1826 NGFDN_3 n2099 n365 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n365 N_N8299 -0 1 -.names NDN3_25 NDN3_22 n1826 N_N8293 -1-0 1 --10 1 -.names PRESET n1807 n2104 N_N8964 n370 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n370 N_N8286 -0 1 -.names PRESET n1807 n2108 N_N8847 n371 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n371 N_N8283 -0 1 -.names NDN3_28 NDN3_29 n1826 N_N8217 -1-0 1 --10 1 -.names N_N8270 n22 N_N8190 -11 1 -.names PRESET n1807 n2142 N_N8993 n404 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n404 N_N8181 -0 1 -.names N_N9289 n22 N_N8178 -11 1 -.names N_N8173 n22 N_N8172 -11 1 -.names N_N8171 n22 N_N8170 -11 1 -.names N_N8572 n22 N_N8169 -11 1 -.names n1500 n2105 n1508 n1504 n1516 n1512 n3010 n3011 n413 -11111111 1 -.names PRESET n413 N_N8147 -01 1 -.names N_N8141 n22 N_N8140 -11 1 -.names N_N8236 n22 N_N8137 -11 1 -.names N_N8529 n22 N_N8136 -11 1 -.names PRESET NDN2_2 n2782 N_N8122 -010 1 -.names N_N8118 n22 N_N8117 -11 1 -.names N_N8037 n22 N_N8036 -11 1 -.names N_N8199 n22 N_N8025 -11 1 -.names N_N8016 n22 N_N8015 -11 1 -.names N_N9440 n22 N_N7998 -11 1 -.names N_N7985 n22 N_N7984 -11 1 -.names N_N7983 n22 N_N7982 -11 1 -.names N_N9363 n22 N_N7981 -11 1 -.names N_N7961 n22 N_N7960 -11 1 -.names N_N9291 n22 N_N7957 -11 1 -.names N_N8272 n22 N_N7894 -11 1 -.names N_N8196 n22 N_N7893 -11 1 -.names NEN3_36 n1826 NGFDN_3 n2247 n486 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n486 N_N7891 -0 1 -.names NDN3_22 NEN3_22 n1826 N_N7883 -1-0 1 --10 1 -.names N_N9362 n22 N_N7870 -11 1 -.names PRESET n1807 n2268 N_N8978 n501 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n501 N_N7828 -0 1 -.names N_N9361 n22 N_N7799 -11 1 -.names N_N9438 n22 N_N7796 -11 1 -.names N_N9556 n22 N_N7795 -11 1 -.names N_N8650 n22 N_N7785 -11 1 -.names PRESET n1807 n2282 N_N8869 n515 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n515 N_N7750 -0 1 -.names PRESET n1807 n2284 N_N8798 n516 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n516 N_N7747 -0 1 -.names NDN3_42 NDN3_40 n1826 N_N7690 -1-0 1 --10 1 -.names N_N8237 n22 N_N7633 -11 1 -.names N_N9358 n22 N_N7608 -11 1 -.names NDN3_44 n1826 N_N7098 n571 -0-0 1 --10 1 -.names n571 N_N7574 -0 1 -.names N_N8240 n22 N_N7548 -11 1 -.names N_N8531 n22 N_N7547 -11 1 -.names PRESET n1807 n2363 N_N9034 n584 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n584 N_N7538 -0 1 -.names PRESET n1807 n2365 N_N8911 n585 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n585 N_N7535 -0 1 -.names NEN3_28 n1826 NGFDN_3 n2373 n590 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n590 N_N7529 -0 1 -.names N_N7768 n22 N_N7528 -11 1 -.names N_N7701 n22 N_N7515 -11 1 -.names NEN3_19 n1826 NGFDN_3 n2419 n625 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n625 N_N7477 -0 1 -.names Preset_0_0_ n1608 N_N7476 n626 -00- 1 -0-1 1 --11 1 -.names PRESET n626 N_N7475 -01 1 -.names N_N9561 n22 N_N7470 -11 1 -.names N_N8235 n22 N_N7465 -11 1 -.names NDN3_11 NDN3_12 n1826 N_N7460 -1-0 1 --10 1 -.names N_N9290 n22 N_N7451 -11 1 -.names N_N9360 n22 N_N7450 -11 1 -.names N_N9439 n22 N_N7449 -11 1 -.names N_N7852 n22 N_N7448 -11 1 -.names N_N8197 n22 N_N7447 -11 1 -.names N_N7853 n22 N_N7446 -11 1 -.names PRESET n1807 n2433 N_N8561 n640 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n640 N_N7439 -0 1 -.names N_N9557 n22 N_N7397 -11 1 -.names N_N9442 n22 N_N7382 -11 1 -.names N_N8241 n22 N_N7379 -11 1 -.names N_N8528 n22 N_N7377 -11 1 -.names N_N8239 n22 N_N7371 -11 1 -.names N_N7583 n22 N_N7357 -11 1 -.names N_N7582 n22 N_N7318 -11 1 -.names N_N8269 n22 N_N7313 -11 1 -.names N_N8571 n22 N_N7312 -11 1 -.names N_N8570 n22 N_N7305 -11 1 -.names N_N7584 n22 N_N7301 -11 1 -.names N_N7703 n22 N_N7294 -11 1 -.names N_N8649 n22 N_N7280 -11 1 -.names N_N9554 n22 N_N7266 -11 1 -.names N_N7630 n22 N_N7238 -11 1 -.names NDN3_42 NDN3_44 n1826 N_N7232 -1-0 1 --10 1 -.names N_N8648 n22 N_N7194 -11 1 -.names PRESET n1323 N_N9163 n778 -11- 1 --10 1 -.names n778 N_N7193 -0 1 -.names NDN3_7 NDN3_9 n1826 N_N7188 -1-0 1 --10 1 -.names N_N7702 n22 N_N7163 -11 1 -.names N_N7769 n22 N_N7162 -11 1 -.names NDN3_39 NDN3_40 n1826 N_N7158 -1-0 1 --10 1 -.names N_N9437 n22 N_N7137 -11 1 -.names N_N8200 n22 N_N7132 -11 1 -.names N_N8575 n22 N_N7131 -11 1 -.names N_N9359 n22 N_N7126 -11 1 -.names NDN3_11 NDN3_9 n1826 N_N7096 -1-0 1 --10 1 -.names PRESET n1807 n2648 N_N8913 n834 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n834 N_N7095 -0 1 -.names PRESET n1807 n2650 N_N8631 n835 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names n835 N_N7094 -0 1 -.names NDN3_16 NDN3_17 n1826 N_N7087 -1-0 1 --10 1 -.names n315 n227 N_N8930 N_N7077 -11- 1 -1-1 1 -.names N_N8573 n22 N_N7063 -11 1 -.names PRESET n1323 N_N9164 n861 -11- 1 --10 1 -.names n861 N_N7059 -0 1 -.names N_N8198 n22 N_N7048 -11 1 -.names N_N8271 n22 N_N7047 -11 1 -.names N_N7771 n22 N_N7042 -11 1 -.names NEN3_16 n1826 NGFDN_3 n2693 n874 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n874 N_N7038 -0 1 -.names PRESET n1323 N_N9166 n880 -11- 1 --10 1 -.names n880 N_N7030 -0 1 -.names NDN1_4 n196 N_N7015 -11 1 -.names N_N8273 n22 N_N7007 -11 1 -.names N_N8574 n22 N_N7006 -11 1 -.names N_N7770 n22 N_N7001 -11 1 -.names N_N7854 n22 N_N7000 -11 1 -.names N_N9555 n22 N_N6995 -11 1 -.names N_N8530 n22 N_N6982 -11 1 -.names N_N7628 n22 N_N6971 -11 1 -.names N_N7629 n22 N_N6958 -11 1 -.names N_N7704 n22 N_N6957 -11 1 -.names N_N9558 n22 N_N6942 -11 1 -.names N_N8238 n22 N_N6941 -11 1 -.names PRESET n1323 N_N9165 n942 -11- 1 --10 1 -.names n942 N_N6928 -0 1 -.names N_N9292 n22 N_N6927 -11 1 -.names N_N8646 n22 N_N6926 -11 1 -.names N_N8274 n22 N_N6924 -11 1 -.names N_N7627 n22 N_N6917 -11 1 -.names n196 NDN3_12 NAK3_13 NSr3_13 n955 -1--0 1 -111- 1 -.names n955 N_N11 -0 1 -.names N_N9248 n315 n413 n956 -01- 1 --11 1 -.names n956 N_N10 -0 1 -.names n196 NAK3_13 NSr3_13 NSr3_14 n957 -1--0 1 -110- 1 -.names n957 N_N9 -0 1 -.names n196 NDN3_17 NAK3_13 NSr3_20 n958 -1--0 1 -111- 1 -.names n958 N_N8 -0 1 -.names N_N9248 n315 n413 n1799 n959 -01-0 1 --110 1 -.names n959 N_N7 -0 1 -.names NDN3_19 n196 NAK3_13 NSr3_23 n960 --1-0 1 -111- 1 -.names n960 N_N6 -0 1 -.names NDN3_26 n196 NAK3_13 NSr3_30 n961 --1-0 1 -111- 1 -.names n961 N_N5 -0 1 -.names n196 NDN3_29 NAK3_13 NSr3_35 n962 -1--0 1 -111- 1 -.names n962 N_N4 -0 1 -.names NEN3_34 n196 NAK3_13 NSr3_37 n963 --1-0 1 -111- 1 -.names n963 N_N3 -0 1 -.names NEN3_36 n196 NAK3_13 NSr3_38 n964 --1-0 1 -111- 1 -.names n964 N_N2 -0 1 -.names n196 NSr1_2 NGFDN_3 n2782 n965 -10-- 1 -1-1- 1 -1--1 1 -.names n965 N_N1 -0 1 -.names PRESET N_N8603 n3007 n3133 n966 -00-0 1 -0-00 1 -.names n966 N_N0 -0 1 -.names PRESET n2838 n1323 -1- 1 --1 1 -.names N_N9552 N_N9363 n2857 n2858 n1347 -00-- 1 -0-0- 1 --0-1 1 ---01 1 -.names N_N9362 N_N9361 n2853 n2855 n1348 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N9360 N_N9359 n2849 n2851 n1349 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N9357 N_N9358 n2845 n2847 n1350 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n1347 n1348 n1349 n1350 n1346 -1111 1 -.names N_N9539 N_N9410 n2847 n2857 n1352 -00-- 1 --01- 1 -0--0 1 ---10 1 -.names N_N9298 N_N9296 n2845 n2853 n1353 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N9291 N_N9292 n2855 n2858 n1354 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N9289 N_N9290 n2849 n2851 n1355 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n1352 n1353 n1354 n1355 n1351 -1111 1 -.names N_N9578 n2845 n2857 N_N9166 n1357 -0-0- 1 --10- 1 -0--0 1 --1-0 1 -.names n2855 n2858 N_N9164 N_N9165 n1358 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n2851 n2853 N_N9162 N_N9163 n1359 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n2847 n2849 N_N9160 N_N9161 n1360 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n1357 n1358 n1359 n1360 n1356 -1111 1 -.names N_N8875 N_N8613 n2847 n2849 n1362 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N8141 N_N7983 n2851 n2853 n1363 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N7630 N_N7629 n2855 n2857 n1364 -00-- 1 -0-1- 1 --0-0 1 ---10 1 -.names N_N7628 N_N7627 n2845 n2858 n1365 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n1362 n1363 n1364 n1365 n1361 -1111 1 -.names N_N8968 N_N8691 n2849 n2857 n1367 -00-- 1 --01- 1 -0--0 1 ---10 1 -.names N_N8447 N_N8016 n2845 n2858 n1368 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N7985 N_N7584 n2853 n2855 n1369 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N7583 N_N7582 n2847 n2851 n1370 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n1367 n1368 n1369 n1370 n1366 -1111 1 -.names N_N9294 N_N8685 n2849 n2858 n1372 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N8577 N_N8118 n2847 n2857 n1373 -00-- 1 -0-1- 1 --0-0 1 ---10 1 -.names N_N7703 N_N7704 n2853 n2855 n1374 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N7701 N_N7702 n2845 n2851 n1375 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n1372 n1373 n1374 n1375 n1371 -1111 1 -.names N_N9331 N_N8803 n2849 n2853 n1377 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N8173 N_N7961 n2845 n2857 n1378 -00-- 1 --01- 1 -0--0 1 ---10 1 -.names N_N7771 N_N7770 n2855 n2858 n1379 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N7768 N_N7769 n2847 n2851 n1380 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n1377 n1378 n1379 n1380 n1376 -1111 1 -.names N_N9560 N_N9561 n2855 n2857 n1382 -00-- 1 --01- 1 -0--0 1 ---10 1 -.names N_N9559 N_N9558 n2853 n2858 n1383 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N9556 N_N9557 n2849 n2851 n1384 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N9554 N_N9555 n2845 n2847 n1385 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n1382 n1383 n1384 n1385 n1381 -1111 1 -.names N_N9550 N_N9442 n2857 n2858 n1387 -00-- 1 -0-0- 1 --0-1 1 ---01 1 -.names N_N9441 N_N9440 n2853 n2855 n1388 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N9438 N_N9439 n2849 n2851 n1389 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N9436 N_N9437 n2845 n2847 n1390 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n1387 n1388 n1389 n1390 n1386 -1111 1 -.names N_N8508 N_N8348 n2845 n2849 n1392 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N8273 N_N8274 n2855 n2857 n1393 -00-- 1 --01- 1 -0--0 1 ---10 1 -.names N_N8272 N_N8271 n2853 n2858 n1394 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N8270 N_N8269 n2847 n2851 n1395 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n1392 n1393 n1394 n1395 n1391 -1111 1 -.names N_N9280 N_N8710 n2847 n2858 n1397 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N8366 N_N8200 n2851 n2857 n1398 -00-- 1 --01- 1 -0--0 1 ---10 1 -.names N_N8199 N_N8198 n2853 n2855 n1399 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N8196 N_N8197 n2845 n2849 n1400 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n1397 n1398 n1399 n1400 n1396 -1111 1 -.names N_N8312 N_N8241 n2849 n2857 n1402 -00-- 1 --01- 1 -0--0 1 ---10 1 -.names N_N8240 N_N8239 n2855 n2858 n1403 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N8237 N_N8238 n2851 n2853 n1404 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N8236 N_N8235 n2845 n2847 n1405 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n1402 n1403 n1404 n1405 n1401 -1111 1 -.names N_N9510 N_N8972 n2851 n2855 n1407 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N8756 N_N8171 n2845 n2847 n1408 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N8037 N_N7854 n2857 n2858 n1409 -00-- 1 --00- 1 -0--1 1 ---01 1 -.names N_N7852 N_N7853 n2849 n2853 n1410 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n1407 n1408 n1409 n1410 n1406 -1111 1 -.names N_N9242 N_N9013 n2851 n2853 n1412 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N8796 N_N8650 n2849 n2857 n1413 -00-- 1 --01- 1 -0--0 1 ---10 1 -.names N_N8649 N_N8648 n2855 n2858 n1414 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N8647 N_N8646 n2845 n2847 n1415 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n1412 n1413 n1414 n1415 n1411 -1111 1 -.names N_N9150 N_N8970 n2851 n2853 n1417 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names N_N8575 N_N8574 n2855 n2857 n1418 -00-- 1 -0-1- 1 --0-0 1 ---10 1 -.names N_N8572 N_N8573 n2849 n2858 n1419 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names N_N8571 N_N8570 n2845 n2847 n1420 -00-- 1 -0-1- 1 --0-1 1 ---11 1 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n330 n336 n276 n239 n424 -11111 1 -.names n284 n339 n426 -11 1 -.names n237 n283 n428 -0- 1 --1 1 -.names n283 n241 n429 -1- 1 --1 1 -.names n428 n285 n426 n340 n429 n342 n427 -111111 1 -.names n335 n424 n430 -11 1 -.names n240 n278 n432 -1- 1 --1 1 -.names n23 n283 n433 -1- 1 --1 1 -.names n432 n433 n69 n431 -111 1 -.names n398 n397 n434 -11 1 -.names n23 n20 n436 -1- 1 --1 1 -.names n195 n434 n223 n436 n435 -1111 1 -.names n15 n250 n241 n437 -111 1 -.names n20 n254 n438 -1- 1 --0 1 -.names n283 n346 n440 -1- 1 --1 1 -.names n109 n283 n441 -1- 1 --1 1 -.names n430 n431 n345 n427 n440 n441 n49 n232 n439 -11111111 1 -.names n244 n254 n442 -1- 1 --0 1 -.names n329 n244 n443 -1- 1 --1 1 -.names n226 n244 n445 -1- 1 --1 1 -.names n250 n244 n446 -1- 1 --1 1 -.names n244 n241 n447 -1- 1 --1 1 -.names n394 n39 n281 n445 n446 n447 n444 -111111 1 -.names n1 n252 n448 -10 1 -.names n400 n399 n287 n449 -111 1 -.names n388 n38 n450 -11 1 -.names n392 n223 n451 -11 1 -.names n209 n241 n452 -1- 1 --1 1 -.names n226 n209 n454 -1- 1 --1 1 -.names n6 n454 n453 -11 1 -.names n417 n413 n414 n455 -111 1 -.names n19 n203 n457 -11 1 -.names n12 n169 n458 -11 1 -.names n17 n294 n459 -11 1 -.names n232 n440 n345 n460 -111 1 -.names n196 n459 n410 n38 n461 -1111 1 -.names n335 n425 n276 n462 -111 1 -.names n402 n69 n463 -11 1 -.names n432 n462 n464 -11 1 -.names n19 n203 n12 n15 n465 -1111 1 -.names n446 n299 n245 n445 n466 -1111 1 -.names n395 n396 n442 n467 -111 1 -.names n220 n374 n468 -11 1 -.names n39 n467 n469 -11 1 -.names n354 n423 n457 n18 n341 n141 n470 -111111 1 -.names n140 n253 n471 -1- 1 --0 1 -.names n24 n278 n472 -1- 1 --1 1 -.names n351 n291 n365 n364 n473 -1111 1 -.names n302 n151 n133 n474 -111 1 -.names n422 n380 n475 -11 1 -.names n342 n131 n355 n476 -111 1 -.names n468 n475 n455 n462 n423 n47 n259 n275 n477 -11111111 1 -.names n7 n416 n478 -11 1 -.names n330 n285 n243 n479 -111 1 -.names n10 n209 n359 n480 -111 1 -.names n396 n411 n348 n481 -111 1 -.names n109 n140 n482 -1- 1 --1 1 -.names n433 n130 n483 -11 1 -.names n16 n279 n303 n484 -111 1 -.names n293 n358 n406 n422 n218 n274 n485 -111111 1 -.end diff --git a/fpga_flow/benchmarks/Blif/MCNC_big20/frisc.blif b/fpga_flow/benchmarks/Blif/MCNC_big20/frisc.blif deleted file mode 100644 index 46c12dc3e..000000000 --- a/fpga_flow/benchmarks/Blif/MCNC_big20/frisc.blif +++ /dev/null @@ -1,11610 +0,0 @@ -.model top -.inputs tin_pdata_8_8_ tin_pdata_0_0_ tin_pdata_7_7_ preset_0_0_ \ -tin_pdata_2_2_ tin_pdata_9_9_ tin_pdata_1_1_ tin_pdata_4_4_ pclk pirq_0_0_ \ -tin_pdata_10_10_ tin_pdata_3_3_ tin_pdata_6_6_ tin_pdata_15_15_ \ -tin_pdata_11_11_ tin_pdata_14_14_ tin_pdata_12_12_ tin_pdata_5_5_ preset \ -tin_pdata_13_13_ -.outputs ppeakb_7_7_ ppeakp_12_12_ ppeakp_0_0_ ppeaka_7_7_ ppeaki_15_15_ \ -ppeaki_11_11_ ppeaki_3_3_ paddress_3_3_ pdata_8_8_ pdata_0_0_ ppeakb_14_14_ \ -ppeakb_10_10_ ppeakb_8_8_ ppeakp_1_1_ ppeaka_14_14_ ppeaka_10_10_ ppeaka_8_8_ \ -ppeaki_4_4_ paddress_15_15_ paddress_11_11_ paddress_2_2_ ppeakb_9_9_ \ -ppeakp_2_2_ ppeaka_9_9_ ppeaks_12_12_ ppeaks_0_0_ ppeaki_5_5_ paddress_5_5_ \ -pdata_7_7_ ppeakb_15_15_ ppeakp_3_3_ pwr_0_0_ ppeaks_1_1_ ppeaki_6_6_ \ -paddress_4_4_ piack_0_0_ ppeakp_13_13_ ppeakp_4_4_ ppeaka_15_15_ ppeaka_11_11_ \ -ppeaks_2_2_ ppeaki_7_7_ paddress_10_10_ paddress_7_7_ pdata_2_2_ ppeakp_5_5_ \ -ppeaks_13_13_ ppeaks_3_3_ ppeaki_14_14_ ppeaki_10_10_ ppeaki_8_8_ \ -paddress_6_6_ ppeakp_6_6_ ppeaks_4_4_ ppeaki_9_9_ paddress_9_9_ pdata_9_9_ \ -pdata_1_1_ ppeakb_11_11_ ppeakp_7_7_ ppeaks_5_5_ paddress_13_13_ paddress_8_8_ \ -ppeakp_14_14_ ppeakp_10_10_ ppeakp_8_8_ ppeaks_6_6_ ppeaki_13_13_ pdata_4_4_ \ -ppeakb_0_0_ ppeakp_9_9_ ppeaka_0_0_ ppeaks_7_7_ ppeakb_1_1_ ppeaka_1_1_ \ -ppeaks_10_10_ ppeaks_8_8_ pdata_10_10_ pdata_3_3_ ppeakb_12_12_ ppeakb_2_2_ \ -ppeaka_12_12_ ppeaka_2_2_ ppeaks_15_15_ ppeaks_9_9_ ppeakb_3_3_ ppeakp_15_15_ \ -ppeakp_11_11_ ppeaka_13_13_ ppeaka_3_3_ paddress_14_14_ paddress_12_12_ \ -pdata_6_6_ ppeakb_13_13_ ppeakb_4_4_ pdn ppeaka_4_4_ ppeaki_0_0_ prd_0_0_ \ -pdata_15_15_ pdata_11_11_ ppeakb_5_5_ ppeaka_5_5_ ppeaks_14_14_ ppeaki_1_1_ \ -paddress_1_1_ pdata_14_14_ pdata_12_12_ pdata_5_5_ ppeakb_6_6_ ppeaka_6_6_ \ -ppeaks_11_11_ ppeaki_12_12_ ppeaki_2_2_ paddress_0_0_ pdata_13_13_ -.latch [4244] ndout re pclk 2 -.latch [4259] ppeakb_12_12_ re pclk 2 -.latch [4274] ppeakb_1_1_ re pclk 2 -.latch [4289] ppeaka_6_6_ re pclk 2 -.latch [4304] [4295] re pclk 2 -.latch [4319] [4310] re pclk 2 -.latch [4334] ppeaks_5_5_ re pclk 2 -.latch [4349] ppeakp_10_10_ re pclk 2 -.latch [4364] [4355] re pclk 2 -.latch [4379] [4370] re pclk 2 -.latch [4394] [4385] re pclk 2 -.latch [4409] [4400] re pclk 2 -.latch [4424] [4415] re pclk 2 -.latch [4439] [4430] re pclk 2 -.latch [4454] [4445] re pclk 2 -.latch [4469] [4460] re pclk 2 -.latch [4484] [4475] re pclk 2 -.latch [4499] [4490] re pclk 2 -.latch [4514] [4505] re pclk 2 -.latch [4529] [4520] re pclk 2 -.latch [4544] [4535] re pclk 2 -.latch [4559] [4550] re pclk 2 -.latch [4574] [4565] re pclk 2 -.latch [4589] [4580] re pclk 2 -.latch [4604] [4595] re pclk 2 -.latch [4619] [4610] re pclk 2 -.latch [4634] [4625] re pclk 2 -.latch [4649] [4640] re pclk 2 -.latch [4664] [4655] re pclk 2 -.latch [4679] [4670] re pclk 2 -.latch [4709] [4700] re pclk 2 -.latch [4724] [4715] re pclk 2 -.latch [4739] [4730] re pclk 2 -.latch [4754] [4745] re pclk 2 -.latch [4769] [4760] re pclk 2 -.latch [4784] [4775] re pclk 2 -.latch [4799] [4790] re pclk 2 -.latch [4814] [4805] re pclk 2 -.latch [4829] [4820] re pclk 2 -.latch [4844] [4835] re pclk 2 -.latch [4859] [4850] re pclk 2 -.latch [4874] [4865] re pclk 2 -.latch [4889] [4880] re pclk 2 -.latch [4904] [4895] re pclk 2 -.latch [4919] [4910] re pclk 2 -.latch [4934] [4925] re pclk 2 -.latch [4949] [4940] re pclk 2 -.latch [4964] [4955] re pclk 2 -.latch [4979] [4970] re pclk 2 -.latch [4994] ppeakb_0_0_ re pclk 2 -.latch [5009] ppeaka_7_7_ re pclk 2 -.latch [5024] [5015] re pclk 2 -.latch [5039] [5030] re pclk 2 -.latch [5054] ppeaks_4_4_ re pclk 2 -.latch [5069] ppeakp_11_11_ re pclk 2 -.latch [5084] [5075] re pclk 2 -.latch [5099] [5090] re pclk 2 -.latch [5114] [5105] re pclk 2 -.latch [5129] [5120] re pclk 2 -.latch [5144] [5135] re pclk 2 -.latch [5159] [5150] re pclk 2 -.latch [5174] [5165] re pclk 2 -.latch [5189] [5180] re pclk 2 -.latch [5204] [5195] re pclk 2 -.latch [5219] [5210] re pclk 2 -.latch [5234] [5225] re pclk 2 -.latch [5249] [5240] re pclk 2 -.latch [5264] [5255] re pclk 2 -.latch [5279] [5270] re pclk 2 -.latch [5294] [5285] re pclk 2 -.latch [5309] [5300] re pclk 2 -.latch [5324] [5315] re pclk 2 -.latch [5339] [5330] re pclk 2 -.latch [5354] [5345] re pclk 2 -.latch [5369] [5360] re pclk 2 -.latch [5384] [5375] re pclk 2 -.latch [5399] [5390] re pclk 2 -.latch [5414] [5405] re pclk 2 -.latch [5429] [5420] re pclk 2 -.latch [5444] [5435] re pclk 2 -.latch [5459] [5450] re pclk 2 -.latch [5474] [5465] re pclk 2 -.latch [5489] [5480] re pclk 2 -.latch [5504] [5495] re pclk 2 -.latch [5519] [5510] re pclk 2 -.latch [5534] [5525] re pclk 2 -.latch [5549] [5540] re pclk 2 -.latch [5564] [5555] re pclk 2 -.latch [5579] [5570] re pclk 2 -.latch [5609] [5600] re pclk 2 -.latch [5624] [5615] re pclk 2 -.latch [5639] [5630] re pclk 2 -.latch [5654] [5645] re pclk 2 -.latch [5669] [5660] re pclk 2 -.latch [5684] [5675] re pclk 2 -.latch [5699] ppeakb_10_10_ re pclk 2 -.latch [5714] ppeaka_8_8_ re pclk 2 -.latch [5729] [5720] re pclk 2 -.latch [5744] ppeaks_14_14_ re pclk 2 -.latch [5759] ppeaks_7_7_ re pclk 2 -.latch [5774] ppeakp_12_12_ re pclk 2 -.latch [5789] [5780] re pclk 2 -.latch [5804] [5795] re pclk 2 -.latch [5819] [5810] re pclk 2 -.latch [5834] [5825] re pclk 2 -.latch [5849] [5840] re pclk 2 -.latch [5864] [5855] re pclk 2 -.latch [5879] [5870] re pclk 2 -.latch [5894] [5885] re pclk 2 -.latch [5909] [5900] re pclk 2 -.latch [5924] [5915] re pclk 2 -.latch [5939] [5930] re pclk 2 -.latch [5954] [5945] re pclk 2 -.latch [5969] [5960] re pclk 2 -.latch [5984] [5975] re pclk 2 -.latch [5999] [5990] re pclk 2 -.latch [6014] [6005] re pclk 2 -.latch [6029] [6020] re pclk 2 -.latch [6044] [6035] re pclk 2 -.latch [6059] [6050] re pclk 2 -.latch [6074] [6065] re pclk 2 -.latch [6089] [6080] re pclk 2 -.latch [6104] [6095] re pclk 2 -.latch [6119] [6110] re pclk 2 -.latch [6134] [6125] re pclk 2 -.latch [6149] [6140] re pclk 2 -.latch [6164] [6155] re pclk 2 -.latch [6179] [6170] re pclk 2 -.latch [6194] [6185] re pclk 2 -.latch [6209] [6200] re pclk 2 -.latch [6224] [6215] re pclk 2 -.latch [6239] [6230] re pclk 2 -.latch [6254] [6245] re pclk 2 -.latch [6269] [6260] re pclk 2 -.latch [6284] [6275] re pclk 2 -.latch [6299] [6290] re pclk 2 -.latch [6314] [6305] re pclk 2 -.latch [6329] [6320] re pclk 2 -.latch [6344] [6335] re pclk 2 -.latch [6359] [6350] re pclk 2 -.latch [6374] [6365] re pclk 2 -.latch [6389] ppeakb_11_11_ re pclk 2 -.latch [6404] ppeakb_2_2_ re pclk 2 -.latch [6419] [6410] re pclk 2 -.latch [6434] ppeaks_15_15_ re pclk 2 -.latch [6449] ppeaks_6_6_ re pclk 2 -.latch [6464] ppeakp_13_13_ re pclk 2 -.latch [6479] [6470] re pclk 2 -.latch [6494] [6485] re pclk 2 -.latch [6509] [6500] re pclk 2 -.latch [6524] [6515] re pclk 2 -.latch [6539] [6530] re pclk 2 -.latch [6554] [6545] re pclk 2 -.latch [6569] [6560] re pclk 2 -.latch [6584] [6575] re pclk 2 -.latch [6599] [6590] re pclk 2 -.latch [6614] [6605] re pclk 2 -.latch [6629] [6620] re pclk 2 -.latch [6644] [6635] re pclk 2 -.latch [6659] [6650] re pclk 2 -.latch [6674] [6665] re pclk 2 -.latch [6689] [6680] re pclk 2 -.latch [6704] [6695] re pclk 2 -.latch [6719] [6710] re pclk 2 -.latch [6734] [6725] re pclk 2 -.latch [6749] [6740] re pclk 2 -.latch [6764] [6755] re pclk 2 -.latch [6779] [6770] re pclk 2 -.latch [6794] [6785] re pclk 2 -.latch [6824] [6815] re pclk 2 -.latch [6839] [6830] re pclk 2 -.latch [6854] [6845] re pclk 2 -.latch [6869] [6860] re pclk 2 -.latch [6884] [6875] re pclk 2 -.latch [6899] [6890] re pclk 2 -.latch [6914] [6905] re pclk 2 -.latch [6929] [6920] re pclk 2 -.latch [6944] [6935] re pclk 2 -.latch [6959] [6950] re pclk 2 -.latch [6974] [6965] re pclk 2 -.latch [6989] [6980] re pclk 2 -.latch [7004] [6995] re pclk 2 -.latch [7019] [7010] re pclk 2 -.latch [7034] [7025] re pclk 2 -.latch [7064] [7055] re pclk 2 -.latch [7079] ppeaks_12_12_ re pclk 2 -.latch [7094] ppeaks_1_1_ re pclk 2 -.latch [7109] ppeakp_3_3_ re pclk 2 -.latch [7124] [7115] re pclk 2 -.latch [7139] [7130] re pclk 2 -.latch [7154] [7145] re pclk 2 -.latch [7169] [7160] re pclk 2 -.latch [7184] [7175] re pclk 2 -.latch [7199] [7190] re pclk 2 -.latch [7214] [7205] re pclk 2 -.latch [7229] [7220] re pclk 2 -.latch [7244] [7235] re pclk 2 -.latch [7259] [7250] re pclk 2 -.latch [7274] [7265] re pclk 2 -.latch [7289] [7280] re pclk 2 -.latch [7304] [7295] re pclk 2 -.latch [7319] [7310] re pclk 2 -.latch [7334] [7325] re pclk 2 -.latch [7349] [7340] re pclk 2 -.latch [7364] [7355] re pclk 2 -.latch [7379] [7370] re pclk 2 -.latch [7394] [7385] re pclk 2 -.latch [7409] [7400] re pclk 2 -.latch [7424] [7415] re pclk 2 -.latch [7439] [7430] re pclk 2 -.latch [7454] [7445] re pclk 2 -.latch [7469] [7460] re pclk 2 -.latch [7484] [7475] re pclk 2 -.latch [7499] [7490] re pclk 2 -.latch [7514] [7505] re pclk 2 -.latch [7529] [7520] re pclk 2 -.latch [7544] [7535] re pclk 2 -.latch [7559] [7550] re pclk 2 -.latch [7574] [7565] re pclk 2 -.latch [7589] [7580] re pclk 2 -.latch [7604] [7595] re pclk 2 -.latch [7634] [7625] re pclk 2 -.latch [7649] [7640] re pclk 2 -.latch [7664] [7655] re pclk 2 -.latch [7679] [7670] re pclk 2 -.latch [7694] [7685] re pclk 2 -.latch [7709] ppeaks_13_13_ re pclk 2 -.latch [7724] ppeakp_7_7_ re pclk 2 -.latch [7739] ppeakp_2_2_ re pclk 2 -.latch [7754] [7745] re pclk 2 -.latch [7769] [7760] re pclk 2 -.latch [7784] [7775] re pclk 2 -.latch [7799] [7790] re pclk 2 -.latch [7814] [7805] re pclk 2 -.latch [7829] [7820] re pclk 2 -.latch [7844] [7835] re pclk 2 -.latch [7859] [7850] re pclk 2 -.latch [7874] [7865] re pclk 2 -.latch [7889] [7880] re pclk 2 -.latch [7904] [7895] re pclk 2 -.latch [7919] [7910] re pclk 2 -.latch [7934] [7925] re pclk 2 -.latch [7949] [7940] re pclk 2 -.latch [7964] [7955] re pclk 2 -.latch [7979] [7970] re pclk 2 -.latch [8009] [8000] re pclk 2 -.latch [8024] [8015] re pclk 2 -.latch [8039] [8030] re pclk 2 -.latch [8054] [8045] re pclk 2 -.latch [8069] [8060] re pclk 2 -.latch [8084] [8075] re pclk 2 -.latch [8099] [8090] re pclk 2 -.latch [8114] [8105] re pclk 2 -.latch [8129] [8120] re pclk 2 -.latch [8144] [8135] re pclk 2 -.latch [8159] [8150] re pclk 2 -.latch [8174] [8165] re pclk 2 -.latch [8189] [8180] re pclk 2 -.latch [8204] [8195] re pclk 2 -.latch [8219] [8210] re pclk 2 -.latch [8234] [8225] re pclk 2 -.latch [8249] [8240] re pclk 2 -.latch [8264] [8255] re pclk 2 -.latch [8294] [8285] re pclk 2 -.latch [8309] [8300] re pclk 2 -.latch [8324] [8315] re pclk 2 -.latch [8339] [8330] re pclk 2 -.latch [8354] ppeaks_3_3_ re pclk 2 -.latch [8369] ppeakp_8_8_ re pclk 2 -.latch [8384] ppeakp_1_1_ re pclk 2 -.latch [8399] [8390] re pclk 2 -.latch [8414] [8405] re pclk 2 -.latch [8429] [8420] re pclk 2 -.latch [8444] [8435] re pclk 2 -.latch [8459] [8450] re pclk 2 -.latch [8474] [8465] re pclk 2 -.latch [8489] [8480] re pclk 2 -.latch [8504] [8495] re pclk 2 -.latch [8519] [8510] re pclk 2 -.latch [8534] [8525] re pclk 2 -.latch [8549] [8540] re pclk 2 -.latch [8564] [8555] re pclk 2 -.latch [8579] [8570] re pclk 2 -.latch [8594] [8585] re pclk 2 -.latch [8609] [8600] re pclk 2 -.latch [8624] [8615] re pclk 2 -.latch [8639] [8630] re pclk 2 -.latch [8654] [8645] re pclk 2 -.latch [8669] [8660] re pclk 2 -.latch [8684] [8675] re pclk 2 -.latch [8699] [8690] re pclk 2 -.latch [8714] [8705] re pclk 2 -.latch [8729] [8720] re pclk 2 -.latch [8744] [8735] re pclk 2 -.latch [8759] [8750] re pclk 2 -.latch [8774] [8765] re pclk 2 -.latch [8789] [8780] re pclk 2 -.latch [8819] [8810] re pclk 2 -.latch [8834] [8825] re pclk 2 -.latch [8849] [8840] re pclk 2 -.latch [8864] [8855] re pclk 2 -.latch [8879] [8870] re pclk 2 -.latch [8894] [8885] re pclk 2 -.latch [8909] [8900] re pclk 2 -.latch [8924] [8915] re pclk 2 -.latch [8939] [8930] re pclk 2 -.latch [8954] [8945] re pclk 2 -.latch [8969] [8960] re pclk 2 -.latch [8984] [8975] re pclk 2 -.latch [8999] ppeaks_11_11_ re pclk 2 -.latch [9014] ppeaks_2_2_ re pclk 2 -.latch [9029] ppeakp_9_9_ re pclk 2 -.latch [9044] ppeakp_0_0_ re pclk 2 -.latch [9059] [9050] re pclk 2 -.latch [9074] [9065] re pclk 2 -.latch [9089] [9080] re pclk 2 -.latch [9104] [9095] re pclk 2 -.latch [9119] [9110] re pclk 2 -.latch [9134] [9125] re pclk 2 -.latch [9149] [9140] re pclk 2 -.latch [9164] [9155] re pclk 2 -.latch [9179] [9170] re pclk 2 -.latch [9194] [9185] re pclk 2 -.latch [9209] [9200] re pclk 2 -.latch [9224] [9215] re pclk 2 -.latch [9239] [9230] re pclk 2 -.latch [9254] [9245] re pclk 2 -.latch [9269] [9260] re pclk 2 -.latch [9284] [9275] re pclk 2 -.latch [9299] [9290] re pclk 2 -.latch [9314] [9305] re pclk 2 -.latch [9329] [9320] re pclk 2 -.latch [9344] [9335] re pclk 2 -.latch [9359] [9350] re pclk 2 -.latch [9374] [9365] re pclk 2 -.latch [9389] [9380] re pclk 2 -.latch [9404] [9395] re pclk 2 -.latch [9419] [9410] re pclk 2 -.latch [9449] [9440] re pclk 2 -.latch [9464] [9455] re pclk 2 -.latch [9479] [9470] re pclk 2 -.latch [9494] [9485] re pclk 2 -.latch [9509] [9500] re pclk 2 -.latch [9524] [9515] re pclk 2 -.latch [9539] [9530] re pclk 2 -.latch [9554] [9545] re pclk 2 -.latch [9569] [9560] re pclk 2 -.latch [9584] [9575] re pclk 2 -.latch [9599] [9590] re pclk 2 -.latch [9614] [9605] re pclk 2 -.latch [9629] [9620] re pclk 2 -.latch [9644] [9635] re pclk 2 -.latch [9659] [9650] re pclk 2 -.latch [9674] [9665] re pclk 2 -.latch [9689] [9680] re pclk 2 -.latch [9704] ppeaki_6_6_ re pclk 2 -.latch [9719] [9710] re pclk 2 -.latch [9734] [9725] re pclk 2 -.latch [9749] [9740] re pclk 2 -.latch [9779] [9770] re pclk 2 -.latch [9794] [9785] re pclk 2 -.latch [9809] [9800] re pclk 2 -.latch [9824] [9815] re pclk 2 -.latch [9839] [9830] re pclk 2 -.latch [9854] [9845] re pclk 2 -.latch [9869] [9860] re pclk 2 -.latch [9884] [9875] re pclk 2 -.latch [9899] [9890] re pclk 2 -.latch [9914] [9905] re pclk 2 -.latch [9929] [9920] re pclk 2 -.latch [9944] [9935] re pclk 2 -.latch [9959] [9950] re pclk 2 -.latch [9989] [9980] re pclk 2 -.latch [10004] [9995] re pclk 2 -.latch [10019] [10010] re pclk 2 -.latch [10034] [10025] re pclk 2 -.latch [10049] [10040] re pclk 2 -.latch [10064] [10055] re pclk 2 -.latch [10079] [10070] re pclk 2 -.latch [10094] [10085] re pclk 2 -.latch [10109] [10100] re pclk 2 -.latch [10124] [10115] re pclk 2 -.latch [10139] [10130] re pclk 2 -.latch [10154] [10145] re pclk 2 -.latch [10184] [10175] re pclk 2 -.latch [10199] [10190] re pclk 2 -.latch [10214] [10205] re pclk 2 -.latch [10229] [10220] re pclk 2 -.latch [10244] ppeaki_15_15_ re pclk 2 -.latch [10259] ppeaki_4_4_ re pclk 2 -.latch [10274] [10265] re pclk 2 -.latch [10289] [10280] re pclk 2 -.latch [10319] [10310] re pclk 2 -.latch [10334] [10325] re pclk 2 -.latch [10349] [10340] re pclk 2 -.latch [10364] [10355] re pclk 2 -.latch [10379] [10370] re pclk 2 -.latch [10409] [10400] re pclk 2 -.latch [10424] [10415] re pclk 2 -.latch [10439] [10430] re pclk 2 -.latch [10454] [10445] re pclk 2 -.latch [10469] [10460] re pclk 2 -.latch [10484] [10475] re pclk 2 -.latch [10499] [10490] re pclk 2 -.latch [10514] [10505] re pclk 2 -.latch [10529] ppeaki_14_14_ re pclk 2 -.latch [10544] ppeaki_5_5_ re pclk 2 -.latch [10559] [10550] re pclk 2 -.latch [10574] [10565] re pclk 2 -.latch [10589] [10580] re pclk 2 -.latch [10604] [10595] re pclk 2 -.latch [10619] [10610] re pclk 2 -.latch [10634] [10625] re pclk 2 -.latch [10664] [10655] re pclk 2 -.latch [10679] [10670] re pclk 2 -.latch [10694] [10685] re pclk 2 -.latch [10709] [10700] re pclk 2 -.latch [10724] [10715] re pclk 2 -.latch [10739] [10730] re pclk 2 -.latch [10754] [10745] re pclk 2 -.latch [10769] [10760] re pclk 2 -.latch [10784] [10775] re pclk 2 -.latch [10799] [10790] re pclk 2 -.latch [10814] [10805] re pclk 2 -.latch [10829] [10820] re pclk 2 -.latch [10859] [10850] re pclk 2 -.latch [10874] [10865] re pclk 2 -.latch [10889] [10880] re pclk 2 -.latch [10904] [10895] re pclk 2 -.latch [10934] [10925] re pclk 2 -.latch [10949] [10940] re pclk 2 -.latch [10964] [10955] re pclk 2 -.latch [10979] [10970] re pclk 2 -.latch [10994] [10985] re pclk 2 -.latch [11024] [11015] re pclk 2 -.latch [11039] [11030] re pclk 2 -.latch [11054] [11045] re pclk 2 -.latch [11069] [11060] re pclk 2 -.latch [11084] [11075] re pclk 2 -.latch [11099] [11090] re pclk 2 -.latch [11129] [11120] re pclk 2 -.latch [11144] [11135] re pclk 2 -.latch [11159] [11150] re pclk 2 -.latch [11174] [11165] re pclk 2 -.latch [11189] [11180] re pclk 2 -.latch [11204] [11195] re pclk 2 -.latch [11219] [11210] re pclk 2 -.latch [11234] [11225] re pclk 2 -.latch [11249] [11240] re pclk 2 -.latch [11264] [11255] re pclk 2 -.latch [11279] [11270] re pclk 2 -.latch [11294] [11285] re pclk 2 -.latch [11309] [11300] re pclk 2 -.latch [11324] [11315] re pclk 2 -.latch [11339] [11330] re pclk 2 -.latch [11354] [11345] re pclk 2 -.latch [11384] [11375] re pclk 2 -.latch [11399] [11390] re pclk 2 -.latch [11414] [11405] re pclk 2 -.latch [11429] [11420] re pclk 2 -.latch [11444] [11435] re pclk 2 -.latch [11459] [11450] re pclk 2 -.latch [11474] [11465] re pclk 2 -.latch [11489] [11480] re pclk 2 -.latch [11504] [11495] re pclk 2 -.latch [11519] [11510] re pclk 2 -.latch [11534] [11525] re pclk 2 -.latch [11549] [11540] re pclk 2 -.latch [11564] [11555] re pclk 2 -.latch [11579] [11570] re pclk 2 -.latch [11594] [11585] re pclk 2 -.latch [11609] [11600] re pclk 2 -.latch [11624] [11615] re pclk 2 -.latch [11639] [11630] re pclk 2 -.latch [11654] [11645] re pclk 2 -.latch [11669] [11660] re pclk 2 -.latch [11684] [11675] re pclk 2 -.latch [11699] [11690] re pclk 2 -.latch [11714] [11705] re pclk 2 -.latch [11729] [11720] re pclk 2 -.latch [11744] [11735] re pclk 2 -.latch [11759] [11750] re pclk 2 -.latch [11774] [11765] re pclk 2 -.latch [11789] [11780] re pclk 2 -.latch [11804] [11795] re pclk 2 -.latch [11819] [11810] re pclk 2 -.latch [11864] ppeaki_9_9_ re pclk 2 -.latch [11879] ppeakb_14_14_ re pclk 2 -.latch [11894] [11885] re pclk 2 -.latch [11909] [11900] re pclk 2 -.latch [11924] [11915] re pclk 2 -.latch [11939] [11930] re pclk 2 -.latch [11984] ppeaki_8_8_ re pclk 2 -.latch [11999] ppeakb_15_15_ re pclk 2 -.latch [12014] [12005] re pclk 2 -.latch [12029] [12020] re pclk 2 -.latch [12044] [12035] re pclk 2 -.latch [12059] [12050] re pclk 2 -.latch [12074] [12065] re pclk 2 -.latch [12089] [12080] re pclk 2 -.latch [12119] ppeaki_7_7_ re pclk 2 -.latch [12134] [12125] re pclk 2 -.latch [12149] [12140] re pclk 2 -.latch [12164] [12155] re pclk 2 -.latch [12179] [12170] re pclk 2 -.latch [12194] [12185] re pclk 2 -.latch [12209] [12200] re pclk 2 -.latch [12239] ppeakb_13_13_ re pclk 2 -.latch [12254] [12245] re pclk 2 -.latch [12269] [12260] re pclk 2 -.latch [12284] [12275] re pclk 2 -.latch [12314] ppeaki_13_13_ re pclk 2 -.latch [12329] ppeaki_2_2_ re pclk 2 -.latch [12344] [12335] re pclk 2 -.latch [12359] [12350] re pclk 2 -.latch [12374] [12365] re pclk 2 -.latch [12389] [12380] re pclk 2 -.latch [12404] [12395] re pclk 2 -.latch [12419] [12410] re pclk 2 -.latch [12434] [12425] re pclk 2 -.latch [12449] [12440] re pclk 2 -.latch [12464] [12455] re pclk 2 -.latch [12479] [12470] re pclk 2 -.latch [12494] [12485] re pclk 2 -.latch [12524] ppeaki_12_12_ re pclk 2 -.latch [12539] ppeaki_3_3_ re pclk 2 -.latch [12554] [12545] re pclk 2 -.latch [12569] [12560] re pclk 2 -.latch [12584] [12575] re pclk 2 -.latch [12599] [12590] re pclk 2 -.latch [12614] [12605] re pclk 2 -.latch [12629] [12620] re pclk 2 -.latch [12644] [12635] re pclk 2 -.latch [12659] [12650] re pclk 2 -.latch [12674] [12665] re pclk 2 -.latch [12689] [12680] re pclk 2 -.latch [12704] [12695] re pclk 2 -.latch [12749] ppeaki_11_11_ re pclk 2 -.latch [12764] ppeaki_0_0_ re pclk 2 -.latch [12779] [12770] re pclk 2 -.latch [12809] [12800] re pclk 2 -.latch [12824] [12815] re pclk 2 -.latch [12839] [12830] re pclk 2 -.latch [12854] [12845] re pclk 2 -.latch [12869] [12860] re pclk 2 -.latch [12884] [12875] re pclk 2 -.latch [12899] [12890] re pclk 2 -.latch [12914] [12905] re pclk 2 -.latch [12929] [12920] re pclk 2 -.latch [12944] [12935] re pclk 2 -.latch [12989] ppeaki_10_10_ re pclk 2 -.latch [13004] ppeaki_1_1_ re pclk 2 -.latch [13019] [13010] re pclk 2 -.latch [13034] [13025] re pclk 2 -.latch [13049] [13040] re pclk 2 -.latch [13064] [13055] re pclk 2 -.latch [13079] [13070] re pclk 2 -.latch [13094] [13085] re pclk 2 -.latch [13109] [13100] re pclk 2 -.latch [13124] [13115] re pclk 2 -.latch [13139] [13130] re pclk 2 -.latch [13169] [13160] re pclk 2 -.latch [13184] [13175] re pclk 2 -.latch [13199] ppeakb_4_4_ re pclk 2 -.latch [13214] ppeaka_9_9_ re pclk 2 -.latch [13229] [13220] re pclk 2 -.latch [13244] [13235] re pclk 2 -.latch [13259] [13250] re pclk 2 -.latch [13274] [13265] re pclk 2 -.latch [13289] [13280] re pclk 2 -.latch [13304] [13295] re pclk 2 -.latch [13319] [13310] re pclk 2 -.latch [13334] [13325] re pclk 2 -.latch [13349] [13340] re pclk 2 -.latch [13364] [13355] re pclk 2 -.latch [13379] [13370] re pclk 2 -.latch [13394] [13385] re pclk 2 -.latch [13409] [13400] re pclk 2 -.latch [13424] [13415] re pclk 2 -.latch [13439] [13430] re pclk 2 -.latch [13454] [13445] re pclk 2 -.latch [13469] [13460] re pclk 2 -.latch [13484] [13475] re pclk 2 -.latch [13499] [13490] re pclk 2 -.latch [13514] [13505] re pclk 2 -.latch [13544] ppeakb_5_5_ re pclk 2 -.latch [13559] [13550] re pclk 2 -.latch [13574] ppeakp_6_6_ re pclk 2 -.latch [13589] [13580] re pclk 2 -.latch [13604] [13595] re pclk 2 -.latch [13619] [13610] re pclk 2 -.latch [13634] [13625] re pclk 2 -.latch [13649] [13640] re pclk 2 -.latch [13664] [13655] re pclk 2 -.latch [13679] [13670] re pclk 2 -.latch [13694] [13685] re pclk 2 -.latch [13709] [13700] re pclk 2 -.latch [13724] [13715] re pclk 2 -.latch [13739] [13730] re pclk 2 -.latch [13754] [13745] re pclk 2 -.latch [13784] [13775] re pclk 2 -.latch [13799] [13790] re pclk 2 -.latch [13814] [13805] re pclk 2 -.latch [13829] [13820] re pclk 2 -.latch [13844] [13835] re pclk 2 -.latch [13859] [13850] re pclk 2 -.latch [13874] [13865] re pclk 2 -.latch [13889] [13880] re pclk 2 -.latch [13904] [13895] re pclk 2 -.latch [13919] ppeaka_11_11_ re pclk 2 -.latch [13934] ppeaka_0_0_ re pclk 2 -.latch [13949] ppeakp_5_5_ re pclk 2 -.latch [13964] [13955] re pclk 2 -.latch [13979] [13970] re pclk 2 -.latch [13994] [13985] re pclk 2 -.latch [14009] [14000] re pclk 2 -.latch [14024] [14015] re pclk 2 -.latch [14039] [14030] re pclk 2 -.latch [14054] [14045] re pclk 2 -.latch [14069] [14060] re pclk 2 -.latch [14084] [14075] re pclk 2 -.latch [14099] [14090] re pclk 2 -.latch [14114] [14105] re pclk 2 -.latch [14129] [14120] re pclk 2 -.latch [14144] [14135] re pclk 2 -.latch [14159] [14150] re pclk 2 -.latch [14174] [14165] re pclk 2 -.latch [14189] [14180] re pclk 2 -.latch [14219] [14210] re pclk 2 -.latch [14234] [14225] re pclk 2 -.latch [14249] [14240] re pclk 2 -.latch [14264] [14255] re pclk 2 -.latch [14279] [14270] re pclk 2 -.latch [14294] [14285] re pclk 2 -.latch [14309] ppeakb_3_3_ re pclk 2 -.latch [14324] ppeaka_10_10_ re pclk 2 -.latch [14339] ppeaka_1_1_ re pclk 2 -.latch [14354] ppeakp_4_4_ re pclk 2 -.latch [14369] [14360] re pclk 2 -.latch [14384] [14375] re pclk 2 -.latch [14399] [14390] re pclk 2 -.latch [14414] [14405] re pclk 2 -.latch [14429] [14420] re pclk 2 -.latch [14444] [14435] re pclk 2 -.latch [14459] [14450] re pclk 2 -.latch [14474] [14465] re pclk 2 -.latch [14489] [14480] re pclk 2 -.latch [14504] [14495] re pclk 2 -.latch [14519] [14510] re pclk 2 -.latch [14534] [14525] re pclk 2 -.latch [14549] [14540] re pclk 2 -.latch [14564] [14555] re pclk 2 -.latch [14579] [14570] re pclk 2 -.latch [14594] [14585] re pclk 2 -.latch [14609] [14600] re pclk 2 -.latch [14624] [14615] re pclk 2 -.latch [14639] [14630] re pclk 2 -.latch [14669] [14660] re pclk 2 -.latch [14684] [14675] re pclk 2 -.latch [14699] [14690] re pclk 2 -.latch [14714] [14705] re pclk 2 -.latch [14729] ppeakb_8_8_ re pclk 2 -.latch [14744] ppeaka_13_13_ re pclk 2 -.latch [14759] ppeaka_2_2_ re pclk 2 -.latch [14774] [14765] re pclk 2 -.latch [14789] ppeaks_9_9_ re pclk 2 -.latch [14804] ppeakp_14_14_ re pclk 2 -.latch [14819] [14810] re pclk 2 -.latch [14834] [14825] re pclk 2 -.latch [14849] [14840] re pclk 2 -.latch [14864] [14855] re pclk 2 -.latch [14879] [14870] re pclk 2 -.latch [14894] [14885] re pclk 2 -.latch [14909] [14900] re pclk 2 -.latch [14924] [14915] re pclk 2 -.latch [14939] [14930] re pclk 2 -.latch [14969] [14960] re pclk 2 -.latch [14984] [14975] re pclk 2 -.latch [14999] [14990] re pclk 2 -.latch [15014] [15005] re pclk 2 -.latch [15029] [15020] re pclk 2 -.latch [15044] [15035] re pclk 2 -.latch [15059] [15050] re pclk 2 -.latch [15074] [15065] re pclk 2 -.latch [15089] [15080] re pclk 2 -.latch [15104] ppeakb_9_9_ re pclk 2 -.latch [15119] ppeaka_12_12_ re pclk 2 -.latch [15134] ppeaka_3_3_ re pclk 2 -.latch [15149] [15140] re pclk 2 -.latch [15164] ppeaks_8_8_ re pclk 2 -.latch [15179] ppeakp_15_15_ re pclk 2 -.latch [15194] [15185] re pclk 2 -.latch [15209] [15200] re pclk 2 -.latch [15224] [15215] re pclk 2 -.latch [15239] [15230] re pclk 2 -.latch [15254] [15245] re pclk 2 -.latch [15269] [15260] re pclk 2 -.latch [15284] [15275] re pclk 2 -.latch [15299] [15290] re pclk 2 -.latch [15314] [15305] re pclk 2 -.latch [15329] [15320] re pclk 2 -.latch [15344] [15335] re pclk 2 -.latch [15359] [15350] re pclk 2 -.latch [15374] [15365] re pclk 2 -.latch [15389] [15380] re pclk 2 -.latch [15404] [15395] re pclk 2 -.latch [15419] [15410] re pclk 2 -.latch [15434] [15425] re pclk 2 -.latch [15449] [15440] re pclk 2 -.latch [15464] ppeakb_6_6_ re pclk 2 -.latch [15479] ppeaka_15_15_ re pclk 2 -.latch [15494] ppeaka_4_4_ re pclk 2 -.latch [15509] [15500] re pclk 2 -.latch [15524] [15515] re pclk 2 -.latch [15539] ppeaks_0_0_ re pclk 2 -.latch [15554] [15545] re pclk 2 -.latch [15569] [15560] re pclk 2 -.latch [15584] [15575] re pclk 2 -.latch [15599] [15590] re pclk 2 -.latch [15614] [15605] re pclk 2 -.latch [15629] [15620] re pclk 2 -.latch [15644] [15635] re pclk 2 -.latch [15659] [15650] re pclk 2 -.latch [15674] [15665] re pclk 2 -.latch [15689] [15680] re pclk 2 -.latch [15704] [15695] re pclk 2 -.latch [15719] [15710] re pclk 2 -.latch [15734] [15725] re pclk 2 -.latch [15764] [15755] re pclk 2 -.latch [15779] [15770] re pclk 2 -.latch [15794] [15785] re pclk 2 -.latch [15809] ppeakb_7_7_ re pclk 2 -.latch [15824] ppeaka_14_14_ re pclk 2 -.latch [15839] ppeaka_5_5_ re pclk 2 -.latch [15854] [15845] re pclk 2 -.latch [15869] [15860] re pclk 2 -.latch [15884] ppeaks_10_10_ re pclk 2 -.latch [15899] [15890] re pclk 2 -.latch [15914] [15905] re pclk 2 -.latch [15929] [15920] re pclk 2 -.latch [15944] [15935] re pclk 2 -.latch [15959] [15950] re pclk 2 -.latch [15974] [15965] re pclk 2 -.latch [15989] [15980] re pclk 2 -.latch [16004] [15995] re pclk 2 -.latch [16019] [16010] re pclk 2 -.latch [16034] [16025] re pclk 2 -.latch [16049] [16040] re pclk 2 -.latch [16064] [16055] re pclk 2 -.latch [16079] [16070] re pclk 2 -.latch [16094] [16085] re pclk 2 -.latch [16109] [16100] re pclk 2 -.latch [16904] paddress_8_8_ re pclk 2 -.latch [16917] [16907] re pclk 2 -.latch [16928] [16920] re pclk 2 -.latch [16941] [16933] re pclk 2 -.latch [16956] paddress_9_9_ re pclk 2 -.latch [16969] [16959] re pclk 2 -.latch [16980] [16972] re pclk 2 -.latch [16993] [16985] re pclk 2 -.latch [17008] [16998] re pclk 2 -.latch [17021] [17011] re pclk 2 -.latch [17032] [17024] re pclk 2 -.latch [17045] [17037] re pclk 2 -.latch [17058] [17050] re pclk 2 -.latch [17073] [17063] re pclk 2 -.latch [17086] [17076] re pclk 2 -.latch [17097] [17089] re pclk 2 -.latch [17110] [17102] re pclk 2 -.latch [17123] [17115] re pclk 2 -.latch [17138] [17128] re pclk 2 -.latch [17151] [17141] re pclk 2 -.latch [17162] [17154] re pclk 2 -.latch [17175] [17167] re pclk 2 -.latch [17188] [17180] re pclk 2 -.latch [17203] [17193] re pclk 2 -.latch [17214] [17206] re pclk 2 -.latch [17227] [17219] re pclk 2 -.latch [17240] [17232] re pclk 2 -.latch [17253] [17245] re pclk 2 -.latch [17268] [17258] re pclk 2 -.latch [17279] [17271] re pclk 2 -.latch [17292] [17284] re pclk 2 -.latch [17305] [17297] re pclk 2 -.latch [17318] [17310] re pclk 2 -.latch [17333] [17323] re pclk 2 -.latch [17346] [17336] re pclk 2 -.latch [17357] [17349] re pclk 2 -.latch [17370] [17362] re pclk 2 -.latch [17383] [17375] re pclk 2 -.latch [17396] [17388] re pclk 2 -.latch [17411] paddress_11_11_ re pclk 2 -.latch [17422] [17414] re pclk 2 -.latch [17435] [17427] re pclk 2 -.latch [17461] [17453] re pclk 2 -.latch [17476] paddress_10_10_ re pclk 2 -.latch [17489] [17479] re pclk 2 -.latch [17502] [17492] re pclk 2 -.latch [17513] [17505] re pclk 2 -.latch [17526] [17518] re pclk 2 -.latch [17539] [17531] re pclk 2 -.latch [17554] [17544] re pclk 2 -.latch [17567] paddress_13_13_ re pclk 2 -.latch [17578] [17570] re pclk 2 -.latch [17591] [17583] re pclk 2 -.latch [17604] [17596] re pclk 2 -.latch [17619] [17609] re pclk 2 -.latch [17632] paddress_12_12_ re pclk 2 -.latch [17643] [17635] re pclk 2 -.latch [17656] [17648] re pclk 2 -.latch [17669] [17661] re pclk 2 -.latch [17684] [17674] re pclk 2 -.latch [17697] paddress_15_15_ re pclk 2 -.latch [17708] [17700] re pclk 2 -.latch [17723] [17713] re pclk 2 -.latch [17736] paddress_14_14_ re pclk 2 -.latch [17747] [17739] re pclk 2 -.latch [17760] [17752] re pclk 2 -.latch [17775] [17765] re pclk 2 -.latch [17788] [17778] re pclk 2 -.latch [17799] [17791] re pclk 2 -.latch [17812] [17804] re pclk 2 -.latch [17825] [17817] re pclk 2 -.latch [17840] pwr_0_0_ re pclk 2 -.latch [17851] [17843] re pclk 2 -.latch [17866] [17856] re pclk 2 -.latch [17879] [17869] re pclk 2 -.latch [17892] [17882] re pclk 2 -.latch [17905] prd_0_0_ re pclk 2 -.latch [17918] [17908] re pclk 2 -.latch [17931] [17921] re pclk 2 -.latch [17944] [17934] re pclk 2 -.latch [17957] [17947] re pclk 2 -.latch [17970] [17960] re pclk 2 -.latch [17983] [17973] re pclk 2 -.latch [17994] [17986] re pclk 2 -.latch [18007] [17999] re pclk 2 -.latch [18022] [18012] re pclk 2 -.latch [18033] [18025] re pclk 2 -.latch [18048] [18038] re pclk 2 -.latch [18059] pdn re pclk 2 -.latch [18072] [18064] re pclk 2 -.latch [18085] [18077] re pclk 2 -.latch [18100] [18090] re pclk 2 -.latch [18111] [18103] re pclk 2 -.latch [18126] [18116] re pclk 2 -.latch [18139] [18129] re pclk 2 -.latch [18150] [18142] re pclk 2 -.latch [18165] [18155] re pclk 2 -.latch [18176] [18168] re pclk 2 -.latch [18191] [18181] re pclk 2 -.latch [18204] [18194] re pclk 2 -.latch [18215] [18207] re pclk 2 -.latch [18228] [18220] re pclk 2 -.latch [18243] [18233] re pclk 2 -.latch [18254] [18246] re pclk 2 -.latch [18269] paddress_0_0_ re pclk 2 -.latch [18282] piack_0_0_ re pclk 2 -.latch [18293] [18285] re pclk 2 -.latch [18306] [18298] re pclk 2 -.latch [18319] [18311] re pclk 2 -.latch [18334] paddress_1_1_ re pclk 2 -.latch [18347] [18337] re pclk 2 -.latch [18360] [18350] re pclk 2 -.latch [18371] [18363] re pclk 2 -.latch [18384] [18376] re pclk 2 -.latch [18397] [18389] re pclk 2 -.latch [18412] paddress_2_2_ re pclk 2 -.latch [18423] [18415] re pclk 2 -.latch [18436] [18428] re pclk 2 -.latch [18449] [18441] re pclk 2 -.latch [18464] paddress_3_3_ re pclk 2 -.latch [18475] [18467] re pclk 2 -.latch [18488] [18480] re pclk 2 -.latch [18501] [18493] re pclk 2 -.latch [18514] [18506] re pclk 2 -.latch [18529] paddress_4_4_ re pclk 2 -.latch [18542] paddress_5_5_ re pclk 2 -.latch [18555] [18545] re pclk 2 -.latch [18568] paddress_6_6_ re pclk 2 -.latch [18581] [18571] re pclk 2 -.latch [18594] [18584] re pclk 2 -.latch [18605] [18597] re pclk 2 -.latch [18618] [18610] re pclk 2 -.latch [18633] paddress_7_7_ re pclk 2 -.latch [18644] [18636] re pclk 2 -.names tin_pdata_8_8_ [16959] [17882] pdata_8_8_ --11 1 -1-0 1 -.names tin_pdata_0_0_ [17479] [18337] pdata_0_0_ -10- 1 --11 1 -.names tin_pdata_7_7_ [16907] [17869] pdata_7_7_ --11 1 -1-0 1 -.names tin_pdata_2_2_ [17323] [18181] pdata_2_2_ --11 1 -1-0 1 -.names tin_pdata_9_9_ [17765] [18571] pdata_9_9_ --11 1 -1-0 1 -.names tin_pdata_1_1_ [17258] [18116] pdata_1_1_ --11 1 -1-0 1 -.names tin_pdata_4_4_ [17193] [18038] pdata_4_4_ --11 1 -1-0 1 -.names tin_pdata_10_10_ [17011] [17921] pdata_10_10_ -10- 1 --11 1 -.names tin_pdata_3_3_ [17128] [17960] pdata_3_3_ --11 1 -1-0 1 -.names tin_pdata_6_6_ [17063] [17934] pdata_6_6_ --11 1 -1-0 1 -.names tin_pdata_15_15_ [17076] [17947] pdata_15_15_ --11 1 -1-0 1 -.names tin_pdata_11_11_ [17336] [18194] pdata_11_11_ -10- 1 --11 1 -.names tin_pdata_14_14_ [17778] [18584] pdata_14_14_ --11 1 -1-0 1 -.names tin_pdata_12_12_ [17141] [17973] pdata_12_12_ -10- 1 --11 1 -.names tin_pdata_5_5_ [16998] [17908] pdata_5_5_ --11 1 -1-0 1 -.names tin_pdata_13_13_ [17492] [18350] pdata_13_13_ --11 1 -1-0 1 -.names pdata_2_2_ [4305] [5582] [4244] ---1 1 -11- 1 -.names [17615] [17616] [17621] [4259] -1-- 1 --1- 1 ---1 1 -.names [17626] [17627] [17631] [4274] -1-- 1 --1- 1 ---1 1 -.names [17641] [17642] [17647] [4289] -1-- 1 --1- 1 ---1 1 -.names [5455] [5456] [17652] [4304] -1-- 1 --1- 1 ---1 1 -.names [5451] [5452] [17654] [4319] -1-- 1 --1- 1 ---1 1 -.names [17672] [17673] [17678] [4334] -1-- 1 --1- 1 ---1 1 -.names [5407] [5410] [5411] [17705] [4349] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names pdata_0_0_ [4352] [5403] [4364] ---1 1 -11- 1 -.names pdata_11_11_ [4352] [5398] [4379] ---1 1 -11- 1 -.names preset pdata_6_6_ [4385] nrq10_4 [4394] -01-1 1 -0-10 1 -.names pdata_1_1_ [4353] [5389] [4409] ---1 1 -11- 1 -.names pdata_12_12_ [4353] [5385] [4424] ---1 1 -11- 1 -.names preset pdata_7_7_ [4430] nrq14_3 [4439] -01-1 1 -0-10 1 -.names preset pdata_2_2_ [4445] nrq14_3 [4454] -01-1 1 -0-10 1 -.names preset pdata_13_13_ [4460] nrq14_3 [4469] -01-1 1 -0-10 1 -.names pdata_8_8_ [4354] [5368] [4484] ---1 1 -11- 1 -.names pdata_3_3_ [18384] [5363] [4499] ---1 1 -11- 1 -.names pdata_14_14_ [18384] [5358] [4514] ---1 1 -11- 1 -.names [5353] [5355] [4529] -1- 1 --1 1 -.names [5349] [5350] [4544] -1- 1 --1 1 -.names [5344] [5346] [4559] -1- 1 --1 1 -.names preset pdata_5_5_ [4565] nrq23_3 [4574] -01-1 1 -0-10 1 -.names preset pdata_0_0_ [4580] nrq23_3 [4589] -01-1 1 -0-10 1 -.names preset pdata_11_11_ [4595] nrq23_3 [4604] -01-1 1 -0-10 1 -.names pdata_6_6_ [4375] [5334] [4619] ---1 1 -11- 1 -.names [4625] [17461] [19360] [4340] [4634] --11- 1 -1--1 1 -.names [4640] [17461] [4340] [19390] [4649] -1-1- 1 --1-1 1 -.names [5143] [5145] [4664] -1- 1 --1 1 -.names [4670] [4253] [5139] [4679] ---1 1 -11- 1 -.names [5132] [5133] [4709] -1- 1 --1 1 -.names [4715] [4317] [5126] [4724] ---1 1 -11- 1 -.names [4730] [4317] [4381] [19368] [4739] -11-- 1 ---11 1 -.names [18501] [19359] [5073] [4754] ---1 1 -11- 1 -.names [4760] [4252] [5068] [4769] ---1 1 -11- 1 -.names [4775] [4252] [5063] [4784] ---1 1 -11- 1 -.names [5057] [5058] [4799] -1- 1 --1 1 -.names [4805] [19360] [4277] [4278] [4814] -1-1- 1 --1-1 1 -.names [4820] [19390] [4277] [4278] [4829] -1-1- 1 --1-1 1 -.names preset [4835] [19088] nrq4_2 [4844] -0-11 1 -01-0 1 -.names [19092] [4345] [4902] [4859] ---1 1 -11- 1 -.names [4865] [19103] [4330] [4374] [4874] -1-1- 1 --1-1 1 -.names [4374] [4388] [4511] [4834] [4889] ----1 1 -111- 1 -100- 1 -.names [19060] [4360] [4828] [4904] ---1 1 -11- 1 -.names [4910] [19097] [4331] [4332] [4919] -1-1- 1 --1-1 1 -.names [4925] [4277] [4278] [19061] [4934] -11-- 1 ---11 1 -.names [4940] [4277] [4278] [19091] [4949] -11-- 1 ---11 1 -.names [4955] [19088] [4336] [4365] [4964] -1-1- 1 --1-1 1 -.names pdata_1_1_ [4305] [4807] [4979] ---1 1 -11- 1 -.names [18037] [18039] [18043] [4994] -1-- 1 --1- 1 ---1 1 -.names [18051] [18052] [18056] [5009] -1-- 1 --1- 1 ---1 1 -.names [4773] [4774] [18057] [5024] -1-- 1 --1- 1 ---1 1 -.names [4768] [4770] [18060] [5039] -1-- 1 --1- 1 ---1 1 -.names [18071] [18073] [18078] [5054] -1-- 1 --1- 1 ---1 1 -.names [4742] [4746] [4747] [18080] [5069] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names pdata_1_1_ [4352] [4741] [5084] ---1 1 -11- 1 -.names pdata_10_10_ [4352] [4738] [5099] ---1 1 -11- 1 -.names pdata_2_2_ [4353] [4736] [5114] ---1 1 -11- 1 -.names pdata_11_11_ [4353] [4734] [5129] ---1 1 -11- 1 -.names preset pdata_8_8_ [5135] nrq14_3 [5144] -01-1 1 -0-10 1 -.names preset pdata_1_1_ [5150] nrq14_3 [5159] -01-1 1 -0-10 1 -.names preset pdata_14_14_ [5165] nrq14_3 [5174] -01-1 1 -0-10 1 -.names pdata_7_7_ [4354] [4725] [5189] ---1 1 -11- 1 -.names pdata_4_4_ [18384] [4719] [5204] ---1 1 -11- 1 -.names pdata_13_13_ [18384] [4717] [5219] ---1 1 -11- 1 -.names [4714] [4716] [5234] -1- 1 --1 1 -.names [4712] [4713] [5249] -1- 1 --1 1 -.names [4710] [4711] [5264] -1- 1 --1 1 -.names preset pdata_4_4_ [5270] nrq23_3 [5279] -01-1 1 -0-10 1 -.names preset pdata_1_1_ [5285] nrq23_3 [5294] -01-1 1 -0-10 1 -.names preset pdata_10_10_ [5300] nrq23_3 [5309] -01-1 1 -0-10 1 -.names pdata_7_7_ [4375] [4702] [5324] ---1 1 -11- 1 -.names [17461] n_n2471 n_n2487 [4698] [5339] ----1 1 -101- 1 -110- 1 -.names [5345] [4340] [4697] [5354] ---1 1 -11- 1 -.names [19390] [4308] [4694] [5369] ---1 1 -11- 1 -.names [5375] [4253] [4693] [5384] ---1 1 -11- 1 -.names [4306] n_n2471 n_n2487 [4690] [5399] ----1 1 -101- 1 -110- 1 -.names [4306] [19359] [4688] [5414] ---1 1 -11- 1 -.names [5420] [4317] [4686] [5429] ---1 1 -11- 1 -.names [5435] [4317] [4381] [19367] [5444] -11-- 1 ---11 1 -.names [4682] [4683] [5459] -1- 1 --1 1 -.names [17305] [19359] [4680] [5474] ---1 1 -11- 1 -.names [5480] [4245] [4252] [19367] [5489] -1-1- 1 --1-1 1 -.names [4377] [19387] [4673] [5504] ---1 1 -11- 1 -.names [5510] [4277] [4669] [5519] ---1 1 -11- 1 -.names [5525] [4277] [4667] [5534] ---1 1 -11- 1 -.names preset [5540] [19070] nrq4_2 [5549] -0-11 1 -01-0 1 -.names [4345] [19096] [4657] [5564] ---1 1 -11- 1 -.names [5570] [4330] [4374] [19097] [5579] -11-- 1 ---11 1 -.names [4360] [19072] [4648] [5609] ---1 1 -11- 1 -.names [5615] [19103] [4331] [4332] [5624] -1-1- 1 --1-1 1 -.names [17240] [19072] [4643] [5639] ---1 1 -11- 1 -.names [5645] [4277] [4278] [19087] [5654] -11-- 1 ---11 1 -.names [5660] [4336] [4365] [19082] [5669] -11-- 1 ---11 1 -.names pdata_0_0_ [4305] [4629] [5684] ---1 1 -11- 1 -.names [18114] [18115] [18120] [5699] -1-- 1 --1- 1 ---1 1 -.names [18128] [18130] [18134] [5714] -1-- 1 --1- 1 ---1 1 -.names [4596] [4597] [18135] [5729] -1-- 1 --1- 1 ---1 1 -.names [18147] [18148] [18153] [5744] -1-- 1 --1- 1 ---1 1 -.names [18163] [18164] [18170] [5759] -1-- 1 --1- 1 ---1 1 -.names [4551] [4554] [4555] [18172] [5774] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names pdata_2_2_ [4352] [4549] [5789] ---1 1 -11- 1 -.names preset pdata_4_4_ [5795] nrq10_4 [5804] -01-1 1 -0-10 1 -.names preset pdata_8_8_ [5810] nrq10_4 [5819] -01-1 1 -0-10 1 -.names preset pdata_9_9_ [5825] nrq14_3 [5834] -01-1 1 -0-10 1 -.names preset pdata_4_4_ [5840] nrq14_3 [5849] -01-1 1 -0-10 1 -.names preset pdata_11_11_ [5855] nrq14_3 [5864] -01-1 1 -0-10 1 -.names pdata_6_6_ [4354] [4536] [5879] ---1 1 -11- 1 -.names pdata_5_5_ [18384] [4532] [5894] ---1 1 -11- 1 -.names [4530] [4531] [5909] -1- 1 --1 1 -.names [4527] [4528] [5924] -1- 1 --1 1 -.names [4525] [4526] [5939] -1- 1 --1 1 -.names [4523] [4524] [5954] -1- 1 --1 1 -.names preset pdata_7_7_ [5960] nrq23_3 [5969] -01-1 1 -0-10 1 -.names preset pdata_14_14_ [5975] nrq23_3 [5984] -01-1 1 -0-10 1 -.names preset pdata_9_9_ [5990] nrq23_3 [5999] -01-1 1 -0-10 1 -.names pdata_8_8_ [4375] [4506] [6014] ---1 1 -11- 1 -.names [6020] [17461] [4340] [19396] [6029] -1-1- 1 --1-1 1 -.names [6035] [4340] [4497] [6044] ---1 1 -11- 1 -.names [4493] [4494] [6059] -1- 1 --1 1 -.names [6065] [4253] [4492] [6074] ---1 1 -11- 1 -.names [6080] [4243] [4253] [19367] [6089] -1-1- 1 --1-1 1 -.names [4291] [4406] [6104] -1- 1 --1 1 -.names [6110] [4317] [4381] [19387] [6119] -11-- 1 ---11 1 -.names [18501] n_n2471 n_n2487 [4263] [6134] ----1 1 -101- 1 -110- 1 -.names [4257] [4262] [6149] -1- 1 --1 1 -.names [4250] [4251] [6164] -1- 1 --1 1 -.names [6170] [4252] [4249] [6179] ---1 1 -11- 1 -.names [4246] [4247] [6194] -1- 1 --1 1 -.names [6200] [4277] [4278] [19396] [6209] -11-- 1 ---11 1 -.names [6215] [4277] [4278] [19367] [6224] -11-- 1 ---11 1 -.names preset [6230] [19103] nrq4_2 [6239] -0-11 1 -01-0 1 -.names [19070] [4383] [4230] [6254] ---1 1 -11- 1 -.names [4345] [19061] [4227] [6269] ---1 1 -11- 1 -.names [4360] [19073] [4218] [6284] ---1 1 -11- 1 -.names [4360] [19096] [4213] [6299] ---1 1 -11- 1 -.names [6305] [4331] [4332] [19061] [6314] -11-- 1 ---11 1 -.names [4307] [4388] [4511] [4196] [6329] ----1 1 -111- 1 -100- 1 -.names [6335] [4277] [4278] [19068] [6344] -11-- 1 ---11 1 -.names [6350] [4336] [4365] [19072] [6359] -11-- 1 ---11 1 -.names [4365] [4388] [4511] [4188] [6374] ----1 1 -111- 1 -100- 1 -.names [18189] [18190] [18196] [6389] -1-- 1 --1- 1 ---1 1 -.names [18201] [18202] [18208] [6404] -1-- 1 --1- 1 ---1 1 -.names [4160] [4161] [18209] [6419] -1-- 1 --1- 1 ---1 1 -.names [18221] [18222] [18226] [6434] -1-- 1 --1- 1 ---1 1 -.names [18237] [18238] [18242] [6449] -1-- 1 --1- 1 ---1 1 -.names [4121] [4124] [4125] [18245] [6464] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names pdata_12_12_ [4352] [4120] [6479] ---1 1 -11- 1 -.names preset pdata_5_5_ [6485] nrq10_4 [6494] -01-1 1 -0-10 1 -.names preset pdata_7_7_ [6500] nrq10_4 [6509] -01-1 1 -0-10 1 -.names preset pdata_10_10_ [6515] nrq14_3 [6524] -01-1 1 -0-10 1 -.names preset pdata_3_3_ [6530] nrq14_3 [6539] -01-1 1 -0-10 1 -.names preset pdata_12_12_ [6545] nrq14_3 [6554] -01-1 1 -0-10 1 -.names pdata_5_5_ [4354] [4108] [6569] ---1 1 -11- 1 -.names pdata_6_6_ [18384] [4105] [6584] ---1 1 -11- 1 -.names pdata_15_15_ [18384] [4103] [6599] ---1 1 -11- 1 -.names [4101] [4102] [6614] -1- 1 --1 1 -.names [4099] [4100] [6629] -1- 1 --1 1 -.names preset pdata_6_6_ [6635] nrq23_3 [6644] -01-1 1 -0-10 1 -.names preset pdata_15_15_ [6650] nrq23_3 [6659] -01-1 1 -0-10 1 -.names preset pdata_8_8_ [6665] nrq23_3 [6674] -01-1 1 -0-10 1 -.names pdata_9_9_ [4375] [4092] [6689] ---1 1 -11- 1 -.names [6695] [4340] [4090] [6704] ---1 1 -11- 1 -.names [6710] [4340] [4088] [6719] ---1 1 -11- 1 -.names [4308] [19367] [4085] [6734] ---1 1 -11- 1 -.names [6740] [4243] [4253] [19387] [6749] -1-1- 1 --1-1 1 -.names [6755] [4243] [4253] [19368] [6764] -1-1- 1 --1-1 1 -.names [4079] [4080] [6779] -1- 1 --1 1 -.names [6785] [4317] [4077] [6794] ---1 1 -11- 1 -.names [4075] [4076] [6824] -1- 1 --1 1 -.names [4073] [4074] [6839] -1- 1 --1 1 -.names [6845] [4245] [4252] [19396] [6854] -1-1- 1 --1-1 1 -.names [6860] [4245] [4252] [19390] [6869] -1-1- 1 --1-1 1 -.names [6875] [4277] [4067] [6884] ---1 1 -11- 1 -.names [6890] [4277] [4065] [6899] ---1 1 -11- 1 -.names preset [6905] [19082] nrq4_2 [6914] -0-11 1 -01-0 1 -.names [19072] [4383] [4062] [6929] ---1 1 -11- 1 -.names [4345] [19073] [4060] [6944] ---1 1 -11- 1 -.names [4360] [19061] [4058] [6959] ---1 1 -11- 1 -.names [19092] [4360] [4056] [6974] ---1 1 -11- 1 -.names [6980] [4331] [4332] [19065] [6989] -11-- 1 ---11 1 -.names [6995] [19082] [4307] [4325] [7004] --11- 1 -1--1 1 -.names [4278] [4388] [4511] [4047] [7019] ----1 1 -111- 1 -100- 1 -.names [7025] [4336] [4365] [19070] [7034] -11-- 1 ---11 1 -.names [4041] [4042] [18253] [7064] -1-- 1 --1- 1 ---1 1 -.names [18264] [18265] [18270] [7079] -1-- 1 --1- 1 ---1 1 -.names [18279] [18280] [18286] [7094] -1-- 1 --1- 1 ---1 1 -.names [4001] [4004] [4005] [18288] [7109] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names pdata_7_7_ [4352] [4000] [7124] ---1 1 -11- 1 -.names preset pdata_2_2_ [7130] nrq10_4 [7139] -01-1 1 -0-10 1 -.names preset pdata_11_11_ [7145] nrq14_3 [7154] -01-1 1 -0-10 1 -.names preset pdata_6_6_ [7160] nrq14_3 [7169] -01-1 1 -0-10 1 -.names pdata_1_1_ [4354] [3992] [7184] ---1 1 -11- 1 -.names pdata_12_12_ [4354] [3990] [7199] ---1 1 -11- 1 -.names pdata_15_15_ [4354] [3988] [7214] ---1 1 -11- 1 -.names pdata_10_10_ [18384] [3985] [7229] ---1 1 -11- 1 -.names [3983] [3984] [7244] -1- 1 --1 1 -.names [3981] [3982] [7259] -1- 1 --1 1 -.names preset pdata_9_9_ [7265] nrq23_3 [7274] -01-1 1 -0-10 1 -.names preset pdata_4_4_ [7280] nrq23_3 [7289] -01-1 1 -0-10 1 -.names preset pdata_15_15_ [7295] nrq23_3 [7304] -01-1 1 -0-10 1 -.names pdata_2_2_ [4375] [3974] [7319] ---1 1 -11- 1 -.names pdata_13_13_ [4375] [3972] [7334] ---1 1 -11- 1 -.names [7340] [4340] [3970] [7349] ---1 1 -11- 1 -.names [4308] [19368] [3967] [7364] ---1 1 -11- 1 -.names [7370] [4243] [4253] [19359] [7379] -1-1- 1 --1-1 1 -.names [4306] [19396] [3963] [7394] ---1 1 -11- 1 -.names [4306] [19367] [3961] [7409] ---1 1 -11- 1 -.names [4381] n_n2471 n_n2487 [3960] [7424] ----1 1 -101- 1 -110- 1 -.names [7430] [4317] [3957] [7439] ---1 1 -11- 1 -.names [3955] [3956] [7454] -1- 1 --1 1 -.names [17305] [19390] [3953] [7469] ---1 1 -11- 1 -.names [7475] [4245] [4252] [19387] [7484] -1-1- 1 --1-1 1 -.names [4377] n_n2471 n_n2487 [3950] [7499] ----1 1 -101- 1 -110- 1 -.names [3947] [3948] [7514] -1- 1 --1 1 -.names [7520] [4277] [3945] [7529] ---1 1 -11- 1 -.names preset [7535] [19065] nrq4_2 [7544] -0-11 1 -01-0 1 -.names [19060] [4383] [3942] [7559] ---1 1 -11- 1 -.names [4345] [19097] [3940] [7574] ---1 1 -11- 1 -.names [4345] [19068] [3938] [7589] ---1 1 -11- 1 -.names [7595] [4330] [4374] [19072] [7604] -11-- 1 ---11 1 -.names [7625] [19088] [4307] [4325] [7634] --11- 1 -1--1 1 -.names [17240] [19073] [3931] [7649] ---1 1 -11- 1 -.names [17240] [19096] [3929] [7664] ---1 1 -11- 1 -.names [7670] [4277] [4278] [19082] [7679] -11-- 1 ---11 1 -.names [3924] [3925] [18291] [7694] -1-- 1 --1- 1 ---1 1 -.names [18303] [18304] [18309] [7709] -1-- 1 --1- 1 ---1 1 -.names [3901] [3904] [3905] [18312] [7724] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3895] [3898] [3899] [18316] [7739] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names pdata_6_6_ [4352] [3894] [7754] ---1 1 -11- 1 -.names preset pdata_3_3_ [7760] nrq10_4 [7769] -01-1 1 -0-10 1 -.names preset pdata_12_12_ [7775] nrq14_3 [7784] -01-1 1 -0-10 1 -.names preset pdata_5_5_ [7790] nrq14_3 [7799] -01-1 1 -0-10 1 -.names pdata_2_2_ [4354] [3886] [7814] ---1 1 -11- 1 -.names pdata_11_11_ [4354] [3884] [7829] ---1 1 -11- 1 -.names pdata_0_0_ [18384] [3881] [7844] ---1 1 -11- 1 -.names pdata_9_9_ [18384] [3879] [7859] ---1 1 -11- 1 -.names [3877] [3878] [7874] -1- 1 --1 1 -.names [3875] [3876] [7889] -1- 1 --1 1 -.names preset pdata_8_8_ [7895] nrq23_3 [7904] -01-1 1 -0-10 1 -.names preset pdata_5_5_ [7910] nrq23_3 [7919] -01-1 1 -0-10 1 -.names preset pdata_14_14_ [7925] nrq23_3 [7934] -01-1 1 -0-10 1 -.names pdata_3_3_ [4375] [3868] [7949] ---1 1 -11- 1 -.names pdata_12_12_ [4375] [3866] [7964] ---1 1 -11- 1 -.names [7970] [17461] [4340] [19359] [7979] -1-1- 1 --1-1 1 -.names [8000] [4253] [3862] [8009] ---1 1 -11- 1 -.names [3859] [3860] [8024] -1- 1 --1 1 -.names [3857] [3858] [8039] -1- 1 --1 1 -.names [8045] [19360] [4317] [4381] [8054] -1-1- 1 --1-1 1 -.names [8060] [4317] [3853] [8069] ---1 1 -11- 1 -.names [18501] [19387] [3851] [8084] ---1 1 -11- 1 -.names [3849] [3850] [8099] -1- 1 --1 1 -.names [8105] [4252] [3848] [8114] ---1 1 -11- 1 -.names [19360] [4377] [3846] [8129] ---1 1 -11- 1 -.names [3843] [3844] [8144] -1- 1 --1 1 -.names [19368] [4377] [3842] [8159] ---1 1 -11- 1 -.names preset [8165] [19097] nrq4_2 [8174] -0-11 1 -01-0 1 -.names [19092] [4383] [3838] [8189] ---1 1 -11- 1 -.names [4345] [19065] [3836] [8204] ---1 1 -11- 1 -.names [4345] [4388] [4511] [3834] [8219] ----1 1 -111- 1 -100- 1 -.names [8225] [4330] [4374] [19070] [8234] -11-- 1 ---11 1 -.names [8240] [4331] [4332] [19073] [8249] -11-- 1 ---11 1 -.names [8255] [19070] [4307] [4325] [8264] --11- 1 -1--1 1 -.names [17240] [19091] [3825] [8294] ---1 1 -11- 1 -.names [8300] [4277] [4278] [19103] [8309] -11-- 1 ---11 1 -.names [8315] [4336] [4365] [19068] [8324] -11-- 1 ---11 1 -.names [3818] [3819] [18320] [8339] -1-- 1 --1- 1 ---1 1 -.names [18330] [18331] [18336] [8354] -1-- 1 --1- 1 ---1 1 -.names [3795] [3798] [3799] [18339] [8369] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3789] [3792] [3793] [18343] [8384] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names pdata_9_9_ [4352] [3788] [8399] ---1 1 -11- 1 -.names preset pdata_0_0_ [8405] nrq10_4 [8414] -01-1 1 -0-10 1 -.names preset pdata_13_13_ [8420] nrq14_3 [8429] -01-1 1 -0-10 1 -.names preset pdata_8_8_ [8435] nrq14_3 [8444] -01-1 1 -0-10 1 -.names preset pdata_15_15_ [8450] nrq14_3 [8459] -01-1 1 -0-10 1 -.names pdata_10_10_ [4354] [3777] [8474] ---1 1 -11- 1 -.names pdata_1_1_ [18384] [3773] [8489] ---1 1 -11- 1 -.names pdata_12_12_ [18384] [3771] [8504] ---1 1 -11- 1 -.names [3768] [3769] [8519] -1- 1 --1 1 -.names preset pdata_0_0_ [8525] nrq23_3 [8534] -01-1 1 -0-10 1 -.names preset pdata_11_11_ [8540] nrq23_3 [8549] -01-1 1 -0-10 1 -.names preset pdata_2_2_ [8555] nrq23_3 [8564] -01-1 1 -0-10 1 -.names preset pdata_13_13_ [8570] nrq23_3 [8579] -01-1 1 -0-10 1 -.names pdata_4_4_ [4375] [3759] [8594] ---1 1 -11- 1 -.names pdata_15_15_ [4375] [3757] [8609] ---1 1 -11- 1 -.names [8615] [17461] [4340] [19387] [8624] -1-1- 1 --1-1 1 -.names [4243] n_n2471 n_n2487 [3751] [8639] ----1 1 -101- 1 -110- 1 -.names [8645] [4253] [3749] [8654] ---1 1 -11- 1 -.names [19360] [4306] [3743] [8669] ---1 1 -11- 1 -.names [19390] [4306] [3741] [8684] ---1 1 -11- 1 -.names [8690] [4317] [3737] [8699] ---1 1 -11- 1 -.names [8705] [4317] [3735] [8714] ---1 1 -11- 1 -.names [18501] [19396] [3733] [8729] ---1 1 -11- 1 -.names [17305] [19367] [3731] [8744] ---1 1 -11- 1 -.names [8750] [4252] [3730] [8759] ---1 1 -11- 1 -.names [8765] [4245] [4252] [19368] [8774] -1-1- 1 --1-1 1 -.names [19359] [4377] [3725] [8789] ---1 1 -11- 1 -.names [8810] [4277] [3721] [8819] ---1 1 -11- 1 -.names [19096] [4383] [3719] [8834] ---1 1 -11- 1 -.names [4345] [19082] [3716] [8849] ---1 1 -11- 1 -.names [4345] [19091] [3713] [8864] ---1 1 -11- 1 -.names [8870] [19088] [4330] [4374] [8879] -1-1- 1 --1-1 1 -.names [8885] [4330] [4374] [19087] [8894] -11-- 1 ---11 1 -.names [4360] [19070] [3706] [8909] ---1 1 -11- 1 -.names [8915] [19072] [4307] [4325] [8924] --11- 1 -1--1 1 -.names [17240] [19065] [3701] [8939] ---1 1 -11- 1 -.names [17240] [19060] [3699] [8954] ---1 1 -11- 1 -.names [8960] [4277] [4278] [19097] [8969] -11-- 1 ---11 1 -.names [8975] [19103] [4336] [4365] [8984] -1-1- 1 --1-1 1 -.names [18356] [18357] [18362] [8999] -1-- 1 --1- 1 ---1 1 -.names [18373] [18374] [18379] [9014] -1-- 1 --1- 1 ---1 1 -.names [3657] [3660] [3661] [18381] [9029] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3651] [3654] [3655] [18386] [9044] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names pdata_8_8_ [4352] [3650] [9059] ---1 1 -11- 1 -.names preset pdata_1_1_ [9065] nrq10_4 [9074] -01-1 1 -0-10 1 -.names preset pdata_14_14_ [9080] nrq14_3 [9089] -01-1 1 -0-10 1 -.names preset pdata_7_7_ [9095] nrq14_3 [9104] -01-1 1 -0-10 1 -.names pdata_0_0_ [4354] [3642] [9119] ---1 1 -11- 1 -.names pdata_9_9_ [4354] [3640] [9134] ---1 1 -11- 1 -.names pdata_2_2_ [18384] [3637] [9149] ---1 1 -11- 1 -.names pdata_11_11_ [18384] [3635] [9164] ---1 1 -11- 1 -.names [3633] [3634] [9179] -1- 1 --1 1 -.names preset pdata_1_1_ [9185] nrq23_3 [9194] -01-1 1 -0-10 1 -.names preset pdata_10_10_ [9200] nrq23_3 [9209] -01-1 1 -0-10 1 -.names preset pdata_3_3_ [9215] nrq23_3 [9224] -01-1 1 -0-10 1 -.names preset pdata_12_12_ [9230] nrq23_3 [9239] -01-1 1 -0-10 1 -.names pdata_5_5_ [4375] [3624] [9254] ---1 1 -11- 1 -.names pdata_14_14_ [4375] [3622] [9269] ---1 1 -11- 1 -.names [9275] [4340] [3620] [9284] ---1 1 -11- 1 -.names [9290] [4243] [4253] [19360] [9299] -1-1- 1 --1-1 1 -.names [9305] [4253] [3616] [9314] ---1 1 -11- 1 -.names [3613] [3614] [9329] -1- 1 --1 1 -.names [3611] [3612] [9344] -1- 1 --1 1 -.names [9350] [4317] [4381] [19396] [9359] -11-- 1 ---11 1 -.names [9365] [19390] [4317] [4381] [9374] -1-1- 1 --1-1 1 -.names [3605] [3606] [9389] -1- 1 --1 1 -.names [17305] [19368] [3603] [9404] ---1 1 -11- 1 -.names [9410] [4252] [3602] [9419] ---1 1 -11- 1 -.names [3599] [3600] [9449] -1- 1 --1 1 -.names [4278] n_n2471 n_n2487 [3598] [9464] ----1 1 -101- 1 -110- 1 -.names [9470] [19359] [4277] [4278] [9479] -1-1- 1 --1-1 1 -.names preset [9485] [19061] nrq4_2 [9494] -0-11 1 -01-0 1 -.names [19091] [4383] [3592] [9509] ---1 1 -11- 1 -.names [4345] [19103] [3590] [9524] ---1 1 -11- 1 -.names [4345] [19087] [3588] [9539] ---1 1 -11- 1 -.names [9545] [4330] [4374] [19082] [9554] -11-- 1 ---11 1 -.names [9560] [4330] [4374] [19068] [9569] -11-- 1 ---11 1 -.names [19088] [4360] [3582] [9584] ---1 1 -11- 1 -.names [9590] [19060] [4307] [4325] [9599] --11- 1 -1--1 1 -.names [17240] [19061] [3577] [9614] ---1 1 -11- 1 -.names [17240] [19092] [3575] [9629] ---1 1 -11- 1 -.names [9635] [4277] [4278] [19065] [9644] -11-- 1 ---11 1 -.names [9650] [4277] [4278] [19096] [9659] -11-- 1 ---11 1 -.names pdata_1_1_ [4357] [3570] [9674] ---1 1 -11- 1 -.names pdata_12_12_ [4357] [3568] [9689] ---1 1 -11- 1 -.names [1427] [4199] [3562] [3563] [9704] ---1- 1 ----1 1 -11-- 1 -.names preset pdata_2_2_ [9710] nrq23_3 [9719] -01-1 1 -0-10 1 -.names [9725] [4253] [3559] [9734] ---1 1 -11- 1 -.names [9740] [4253] [3557] [9749] ---1 1 -11- 1 -.names [9770] [4252] [3555] [9779] ---1 1 -11- 1 -.names [3552] [3553] [9794] -1- 1 --1 1 -.names [19087] [4383] [3551] [9809] ---1 1 -11- 1 -.names [4345] [19070] [3549] [9824] ---1 1 -11- 1 -.names [9830] [4330] [4374] [19061] [9839] -11-- 1 ---11 1 -.names [9845] [4330] [4374] [19091] [9854] -11-- 1 ---11 1 -.names [9860] [19092] [4307] [4325] [9869] --11- 1 -1--1 1 -.names [17240] [19103] [3540] [9884] ---1 1 -11- 1 -.names [17240] [4388] [4511] [3538] [9899] ----1 1 -111- 1 -100- 1 -.names [9905] [4277] [4278] [19060] [9914] -11-- 1 ---11 1 -.names [9920] [19097] [4336] [4365] [9929] -1-1- 1 --1-1 1 -.names pdata_0_0_ [4357] [3533] [9944] ---1 1 -11- 1 -.names pdata_6_6_ [4358] [3531] [9959] ---1 1 -11- 1 -.names preset pdata_12_12_ [9980] nrq23_3 [9989] -01-1 1 -0-10 1 -.names [9995] [4243] [4253] [19396] [10004] -1-1- 1 --1-1 1 -.names [10010] [4243] [4253] [19390] [10019] -1-1- 1 --1-1 1 -.names [4245] n_n2471 n_n2487 [3522] [10034] ----1 1 -101- 1 -110- 1 -.names [10040] [4245] [4252] [19359] [10049] -1-1- 1 --1-1 1 -.names [4377] [19367] [3519] [10064] ---1 1 -11- 1 -.names [4383] [19068] [3517] [10079] ---1 1 -11- 1 -.names [19088] [4345] [3515] [10094] ---1 1 -11- 1 -.names [10100] [4330] [4374] [19065] [10109] -11-- 1 ---11 1 -.names [10115] [4330] [4374] [19096] [10124] -11-- 1 ---11 1 -.names [10130] [19096] [4307] [4325] [10139] --11- 1 -1--1 1 -.names [17240] [19097] [3506] [10154] ---1 1 -11- 1 -.names [10175] [4277] [4278] [19072] [10184] -11-- 1 ---11 1 -.names [10190] [4336] [4365] [19087] [10199] -11-- 1 ---11 1 -.names pdata_10_10_ [4357] [3501] [10214] ---1 1 -11- 1 -.names pdata_5_5_ [4358] [3499] [10229] ---1 1 -11- 1 -.names [12200] [3496] [5513] [5514] [10244] --1-- 1 -1-1- 1 -1--1 1 -.names [4199] [1342] [3491] [3492] [10259] ---1- 1 ----1 1 -11-- 1 -.names preset pdata_6_6_ [10265] nrq23_3 [10274] -01-1 1 -0-10 1 -.names [3487] [3488] [10289] -1- 1 --1 1 -.names [10310] [4245] [4252] [19360] [10319] -1-1- 1 --1-1 1 -.names [3483] [3484] [10334] -1- 1 --1 1 -.names [3481] [3482] [10349] -1- 1 --1 1 -.names [4383] [4388] [4511] [3480] [10364] ----1 1 -111- 1 -100- 1 -.names [4345] [19060] [3478] [10379] ---1 1 -11- 1 -.names [10400] [19092] [4330] [4374] [10409] -1-1- 1 --1-1 1 -.names [10415] [19091] [4307] [4325] [10424] --11- 1 -1--1 1 -.names [17240] [19088] [3471] [10439] ---1 1 -11- 1 -.names [17240] [19087] [3469] [10454] ---1 1 -11- 1 -.names [10460] [4277] [4278] [19070] [10469] -11-- 1 ---11 1 -.names pdata_2_2_ [4357] [3466] [10484] ---1 1 -11- 1 -.names pdata_11_11_ [4357] [3464] [10499] ---1 1 -11- 1 -.names pdata_4_4_ [4358] [3462] [10514] ---1 1 -11- 1 -.names [12080] [3459] [5513] [5514] [10529] --1-- 1 -1-1- 1 -1--1 1 -.names [4199] [1353] [3454] [3455] [10544] ---1- 1 ----1 1 -11-- 1 -.names pdata_0_0_ [4375] [3453] [10559] ---1 1 -11- 1 -.names [4306] [19387] [3450] [10574] ---1 1 -11- 1 -.names [4306] [19368] [3448] [10589] ---1 1 -11- 1 -.names [10595] [4252] [3447] [10604] ---1 1 -11- 1 -.names [4377] [19396] [3445] [10619] ---1 1 -11- 1 -.names [19390] [4377] [3443] [10634] ---1 1 -11- 1 -.names [4345] [19072] [3441] [10664] ---1 1 -11- 1 -.names [10670] [4330] [4374] [19073] [10679] -11-- 1 ---11 1 -.names [10685] [4330] [4374] [19060] [10694] -11-- 1 ---11 1 -.names [10700] [19087] [4307] [4325] [10709] --11- 1 -1--1 1 -.names [17240] [19082] [3432] [10724] ---1 1 -11- 1 -.names [17240] [19068] [3430] [10739] ---1 1 -11- 1 -.names [10745] [4277] [4278] [19088] [10754] -11-- 1 ---11 1 -.names pdata_13_13_ [4305] [3426] [10769] ---1 1 -11- 1 -.names pdata_8_8_ [4357] [3425] [10784] ---1 1 -11- 1 -.names pdata_3_3_ [4358] [3423] [10799] ---1 1 -11- 1 -.names pdata_1_1_ [4359] [3421] [10814] ---1 1 -11- 1 -.names pdata_12_12_ [4359] [3419] [10829] ---1 1 -11- 1 -.names pdata_10_10_ [4375] [3417] [10859] ---1 1 -11- 1 -.names [10865] [4317] [3414] [10874] ---1 1 -11- 1 -.names [3412] [3413] [10889] -1- 1 --1 1 -.names [10895] [4277] [3410] [10904] ---1 1 -11- 1 -.names preset [10925] [19092] nrq4_2 [10934] -0-11 1 -01-0 1 -.names [4360] [19065] [3407] [10949] ---1 1 -11- 1 -.names [4360] [19087] [3405] [10964] ---1 1 -11- 1 -.names [10970] [4331] [4332] [19070] [10979] -11-- 1 ---11 1 -.names [10985] [4307] [4325] [19068] [10994] -1-1- 1 --1-1 1 -.names [11015] [19092] [4336] [4365] [11024] -1-1- 1 --1-1 1 -.names pdata_12_12_ [4305] [3396] [11039] ---1 1 -11- 1 -.names pdata_9_9_ [4357] [3395] [11054] ---1 1 -11- 1 -.names pdata_2_2_ [4358] [3393] [11069] ---1 1 -11- 1 -.names pdata_7_7_ [4358] [3391] [11084] ---1 1 -11- 1 -.names pdata_13_13_ [4359] [3389] [11099] ---1 1 -11- 1 -.names [11120] [4340] [3387] [11129] ---1 1 -11- 1 -.names [11135] [4317] [4381] [19359] [11144] -11-- 1 ---11 1 -.names [18501] [19360] [3382] [11159] ---1 1 -11- 1 -.names [11165] [4277] [4278] [19387] [11174] -11-- 1 ---11 1 -.names [11180] [19368] [4277] [4278] [11189] -1-1- 1 --1-1 1 -.names [4360] [19097] [3377] [11204] ---1 1 -11- 1 -.names [4360] [19091] [3375] [11219] ---1 1 -11- 1 -.names [11225] [4331] [4332] [19072] [11234] -11-- 1 ---11 1 -.names [17240] [19070] [3370] [11249] ---1 1 -11- 1 -.names [11255] [4336] [4365] [19073] [11264] -11-- 1 ---11 1 -.names [11270] [19060] [4336] [4365] [11279] -1-1- 1 --1-1 1 -.names pdata_15_15_ [4305] [3364] [11294] ---1 1 -11- 1 -.names pdata_6_6_ [4357] [3363] [11309] ---1 1 -11- 1 -.names pdata_1_1_ [4358] [3361] [11324] ---1 1 -11- 1 -.names pdata_8_8_ [4358] [3359] [11339] ---1 1 -11- 1 -.names pdata_3_3_ [4359] [3357] [11354] ---1 1 -11- 1 -.names [11375] [17461] [4340] [19367] [11384] -1-1- 1 --1-1 1 -.names [3352] [3353] [11399] -1- 1 --1 1 -.names [11405] [4277] [3350] [11414] ---1 1 -11- 1 -.names preset [11420] [19072] nrq4_2 [11429] -0-11 1 -01-0 1 -.names [19103] [4360] [3347] [11444] ---1 1 -11- 1 -.names [4360] [4388] [4511] [3345] [11459] ----1 1 -111- 1 -100- 1 -.names [11465] [4331] [4332] [19082] [11474] -11-- 1 ---11 1 -.names [11480] [4277] [4278] [19073] [11489] -11-- 1 ---11 1 -.names [11495] [19061] [4336] [4365] [11504] -1-1- 1 --1-1 1 -.names [11510] [19091] [4336] [4365] [11519] -1-1- 1 --1-1 1 -.names pdata_14_14_ [4305] [3334] [11534] ---1 1 -11- 1 -.names pdata_7_7_ [4357] [3333] [11549] ---1 1 -11- 1 -.names pdata_0_0_ [4358] [3331] [11564] ---1 1 -11- 1 -.names pdata_9_9_ [4358] [3329] [11579] ---1 1 -11- 1 -.names pdata_2_2_ [4359] [3327] [11594] ---1 1 -11- 1 -.names pdata_11_11_ [4359] [3325] [11609] ---1 1 -11- 1 -.names [18501] [19390] [3322] [11624] ---1 1 -11- 1 -.names preset [11630] [19073] nrq4_2 [11639] -0-11 1 -01-0 1 -.names preset [11645] [19060] nrq4_2 [11654] -0-11 1 -01-0 1 -.names [4360] [19082] [3317] [11669] ---1 1 -11- 1 -.names [4360] [19068] [3315] [11684] ---1 1 -11- 1 -.names [11690] [19088] [4331] [4332] [11699] -1-1- 1 --1-1 1 -.names [11705] [4277] [4278] [19092] [11714] -11-- 1 ---11 1 -.names [11720] [4336] [4365] [19065] [11729] -11-- 1 ---11 1 -.names [11735] [4336] [4365] [19096] [11744] -11-- 1 ---11 1 -.names pdata_9_9_ [4305] [3304] [11759] ---1 1 -11- 1 -.names pdata_4_4_ [4357] [3303] [11774] ---1 1 -11- 1 -.names pdata_15_15_ [4357] [3301] [11789] ---1 1 -11- 1 -.names pdata_10_10_ [4358] [3299] [11804] ---1 1 -11- 1 -.names pdata_5_5_ [4359] [3297] [11819] ---1 1 -11- 1 -.names [4199] [1412] [3293] [3294] [11864] ---1- 1 ----1 1 -11-- 1 -.names [18401] [18402] [18406] [11879] -1-- 1 --1- 1 ---1 1 -.names pdata_5_5_ [4357] [3280] [11894] ---1 1 -11- 1 -.names pdata_14_14_ [4357] [3278] [11909] ---1 1 -11- 1 -.names pdata_11_11_ [4358] [3276] [11924] ---1 1 -11- 1 -.names pdata_4_4_ [4359] [3274] [11939] ---1 1 -11- 1 -.names [4199] [1397] [3270] [3271] [11984] ---1- 1 ----1 1 -11-- 1 -.names [3268] [18414] [18416] [18417] [11999] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [12005] [19061] [4316] [4327] [12014] -1-1- 1 --1-1 1 -.names pdata_11_11_ [4305] [3254] [12029] ---1 1 -11- 1 -.names pdata_13_13_ [4357] [3253] [12044] ---1 1 -11- 1 -.names pdata_12_12_ [4358] [3251] [12059] ---1 1 -11- 1 -.names pdata_7_7_ [4359] [3249] [12074] ---1 1 -11- 1 -.names pdata_14_14_ [4359] [3247] [12089] ---1 1 -11- 1 -.names [4199] [1439] [3241] [3242] [12119] ---1- 1 ----1 1 -11-- 1 -.names [12125] [19096] [4316] [4327] [12134] -1-1- 1 --1-1 1 -.names pdata_10_10_ [4305] [3237] [12149] ---1 1 -11- 1 -.names pdata_3_3_ [4357] [3236] [12164] ---1 1 -11- 1 -.names pdata_13_13_ [4358] [3234] [12179] ---1 1 -11- 1 -.names pdata_6_6_ [4359] [3232] [12194] ---1 1 -11- 1 -.names pdata_15_15_ [4359] [3230] [12209] ---1 1 -11- 1 -.names [3227] [18427] [18429] [18430] [12239] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [12245] [19103] [4307] [4325] [12254] --11- 1 -1--1 1 -.names pdata_14_14_ [4358] [3214] [12269] ---1 1 -11- 1 -.names pdata_9_9_ [4359] [3212] [12284] ---1 1 -11- 1 -.names [11090] [3209] [5513] [5514] [12314] --1-- 1 -1-1- 1 -1--1 1 -.names [4199] [1368] [3204] [3205] [12329] ---1- 1 ----1 1 -11-- 1 -.names [12335] [4280] [3203] [12344] ---1 1 -11- 1 -.names [3200] [3201] [12359] -1- 1 --1 1 -.names [16928] [19368] [3198] [12374] ---1 1 -11- 1 -.names [19061] [4368] [3197] [12389] ---1 1 -11- 1 -.names [19091] [4368] [3195] [12404] ---1 1 -11- 1 -.names [19088] [4383] [3193] [12419] ---1 1 -11- 1 -.names [4332] [4388] [4511] [3191] [12434] ----1 1 -111- 1 -100- 1 -.names [12440] [19060] [4316] [4327] [12449] -1-1- 1 --1-1 1 -.names [12455] [19097] [4307] [4325] [12464] --11- 1 -1--1 1 -.names pdata_15_15_ [4358] [3185] [12479] ---1 1 -11- 1 -.names pdata_8_8_ [4359] [3183] [12494] ---1 1 -11- 1 -.names [10820] [3180] [5513] [5514] [12524] --1-- 1 -1-1- 1 -1--1 1 -.names [4199] [1386] [3175] [3176] [12539] ---1- 1 ----1 1 -11-- 1 -.names [3173] [3174] [12554] -1- 1 --1 1 -.names [12560] [18176] [4280] [19387] [12569] -1-1- 1 --1-1 1 -.names [16928] [19396] [3169] [12584] ---1 1 -11- 1 -.names [3167] [3168] [12599] -1- 1 --1 1 -.names [19073] [4368] [3166] [12614] ---1 1 -11- 1 -.names [19087] [4368] [3164] [12629] ---1 1 -11- 1 -.names [19082] [4383] [3162] [12644] ---1 1 -11- 1 -.names [12650] [4331] [4332] [19068] [12659] -11-- 1 ---11 1 -.names [12665] [19092] [4316] [4327] [12674] -1-1- 1 --1-1 1 -.names [12680] [4307] [4325] [19065] [12689] -1-1- 1 --1-1 1 -.names pdata_0_0_ [4359] [3154] [12704] ---1 1 -11- 1 -.names [4199] [1411] [3150] [3151] [12749] ---1- 1 ----1 1 -11-- 1 -.names [4199] [1398] [3145] [3146] [12764] ---1- 1 ----1 1 -11-- 1 -.names [3143] [3144] [12779] -1- 1 --1 1 -.names [3141] [3142] [12809] -1- 1 --1 1 -.names [3139] [3140] [12824] -1- 1 --1 1 -.names [3137] [3138] [12839] -1- 1 --1 1 -.names [19097] [4368] [3136] [12854] ---1 1 -11- 1 -.names [19092] [4368] [3134] [12869] ---1 1 -11- 1 -.names [19103] [4383] [3132] [12884] ---1 1 -11- 1 -.names [12890] [19073] [4316] [4327] [12899] -1-1- 1 --1-1 1 -.names [12905] [19070] [4316] [4327] [12914] -1-1- 1 --1-1 1 -.names [12920] [19061] [4307] [4325] [12929] --11- 1 -1--1 1 -.names pdata_10_10_ [4359] [3124] [12944] ---1 1 -11- 1 -.names [4199] [1434] [3120] [3121] [12989] ---1- 1 ----1 1 -11-- 1 -.names [4199] [1413] [3115] [3116] [13004] ---1- 1 ----1 1 -11-- 1 -.names [3113] [3114] [13019] -1- 1 --1 1 -.names [4308] n_n2471 n_n2487 [3111] [13034] ----1 1 -101- 1 -110- 1 -.names [4308] [19359] [3109] [13049] ---1 1 -11- 1 -.names [3107] [3108] [13064] -1- 1 --1 1 -.names [16928] [19367] [3105] [13079] ---1 1 -11- 1 -.names [17305] [19387] [3103] [13094] ---1 1 -11- 1 -.names [19065] [4368] [3102] [13109] ---1 1 -11- 1 -.names [19096] [4368] [3100] [13124] ---1 1 -11- 1 -.names [19097] [4383] [3098] [13139] ---1 1 -11- 1 -.names [13160] [19072] [4316] [4327] [13169] -1-1- 1 --1-1 1 -.names [13175] [19073] [4307] [4325] [13184] --11- 1 -1--1 1 -.names [18445] [18446] [18451] [13199] -1-- 1 --1- 1 ---1 1 -.names [18458] [18459] [18463] [13214] -1-- 1 --1- 1 ---1 1 -.names pdata_3_3_ [4352] [3066] [13229] ---1 1 -11- 1 -.names pdata_14_14_ [4352] [3064] [13244] ---1 1 -11- 1 -.names preset pdata_14_14_ [13250] nrq10_4 [13259] -01-1 1 -0-10 1 -.names pdata_9_9_ [4353] [3060] [13274] ---1 1 -11- 1 -.names preset pdata_4_4_ [13280] nrq14_3 [13289] -01-1 1 -0-10 1 -.names [3055] [3056] [13304] -1- 1 --1 1 -.names [3053] [3054] [13319] -1- 1 --1 1 -.names [3051] [3052] [13334] -1- 1 --1 1 -.names [3049] [3050] [13349] -1- 1 --1 1 -.names [13355] [18176] [4280] [19396] [13364] -1-1- 1 --1-1 1 -.names [13370] [18176] [4280] [19367] [13379] -1-1- 1 --1-1 1 -.names [3043] [3044] [13394] -1- 1 --1 1 -.names [16928] n_n2471 n_n2487 [3041] [13409] ----1 1 -101- 1 -110- 1 -.names [3039] [3040] [13424] -1- 1 --1 1 -.names [3037] [3038] [13439] -1- 1 --1 1 -.names preset [13445] [19068] nrq4_2 [13454] -0-11 1 -01-0 1 -.names [19072] [4368] [3034] [13469] ---1 1 -11- 1 -.names [4383] [19065] [3032] [13484] ---1 1 -11- 1 -.names [13490] [4331] [4332] [19096] [13499] -11-- 1 ---11 1 -.names [13505] [19082] [4316] [4327] [13514] -1-1- 1 --1-1 1 -.names [18470] [18471] [18476] [13544] -1-- 1 --1- 1 ---1 1 -.names [3012] [3013] [18477] [13559] -1-- 1 --1- 1 ---1 1 -.names [3005] [3008] [3009] [18481] [13574] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names pdata_15_15_ [4352] [3004] [13589] ---1 1 -11- 1 -.names preset pdata_13_13_ [13595] nrq10_4 [13604] -01-1 1 -0-10 1 -.names pdata_10_10_ [4353] [3000] [13619] ---1 1 -11- 1 -.names preset pdata_3_3_ [13625] nrq14_3 [13634] -01-1 1 -0-10 1 -.names [2995] [2996] [13649] -1- 1 --1 1 -.names [2993] [2994] [13664] -1- 1 --1 1 -.names [2991] [2992] [13679] -1- 1 --1 1 -.names [2989] [2990] [13694] -1- 1 --1 1 -.names [13700] [4340] [2988] [13709] ---1 1 -11- 1 -.names [13715] [4280] [2986] [13724] ---1 1 -11- 1 -.names [13730] [18176] [4280] [19368] [13739] -1-1- 1 --1-1 1 -.names [2981] [2982] [13754] -1- 1 --1 1 -.names [16928] [19390] [2979] [13784] ---1 1 -11- 1 -.names [2977] [2978] [13799] -1- 1 --1 1 -.names preset [13805] [19087] nrq4_2 [13814] -0-11 1 -01-0 1 -.names [19060] [4368] [2974] [13829] ---1 1 -11- 1 -.names [19061] [4383] [2972] [13844] ---1 1 -11- 1 -.names [13850] [19092] [4331] [4332] [13859] -1-1- 1 --1-1 1 -.names [13865] [19088] [4316] [4327] [13874] -1-1- 1 --1-1 1 -.names [4327] [4388] [4511] [2966] [13889] ----1 1 -111- 1 -100- 1 -.names pdata_8_8_ [4305] [2963] [13904] ---1 1 -11- 1 -.names [18491] [18492] [18497] [13919] -1-- 1 --1- 1 ---1 1 -.names [2946] [18507] [18511] [13934] -1-- 1 --1- 1 ---1 1 -.names [2927] [2930] [2931] [18513] [13949] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names pdata_5_5_ [4352] [2926] [13964] ---1 1 -11- 1 -.names pdata_0_0_ [4353] [2924] [13979] ---1 1 -11- 1 -.names pdata_7_7_ [4353] [2922] [13994] ---1 1 -11- 1 -.names preset pdata_2_2_ [14000] nrq14_3 [14009] -01-1 1 -0-10 1 -.names pdata_13_13_ [4354] [2918] [14024] ---1 1 -11- 1 -.names pdata_8_8_ [18384] [2915] [14039] ---1 1 -11- 1 -.names [2913] [2914] [14054] -1- 1 --1 1 -.names [2911] [2912] [14069] -1- 1 --1 1 -.names [2909] [2910] [14084] -1- 1 --1 1 -.names pdata_11_11_ [4375] [2908] [14099] ---1 1 -11- 1 -.names [14105] [4280] [2906] [14114] ---1 1 -11- 1 -.names [14120] [18176] [4280] [19390] [14129] -1-1- 1 --1-1 1 -.names [4308] [19387] [2901] [14144] ---1 1 -11- 1 -.names [2899] [2900] [14159] -1- 1 --1 1 -.names [16928] [19359] [2897] [14174] ---1 1 -11- 1 -.names [17305] [19396] [2895] [14189] ---1 1 -11- 1 -.names [19088] [4368] [2894] [14219] ---1 1 -11- 1 -.names [4383] [19073] [2892] [14234] ---1 1 -11- 1 -.names [14240] [4331] [4332] [19087] [14249] -11-- 1 ---11 1 -.names [14255] [19097] [4316] [4327] [14264] -1-1- 1 --1-1 1 -.names [14270] [19068] [4316] [4327] [14279] -1-1- 1 --1-1 1 -.names pdata_7_7_ [4305] [2883] [14294] ---1 1 -11- 1 -.names [2881] [18522] [18523] [18524] [14309] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2870] [18535] [18539] [14324] -1-- 1 --1- 1 ---1 1 -.names [2856] [18549] [18553] [14339] -1-- 1 --1- 1 ---1 1 -.names [2837] [2840] [2841] [18556] [14354] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names pdata_4_4_ [4352] [2836] [14369] ---1 1 -11- 1 -.names pdata_13_13_ [4352] [2834] [14384] ---1 1 -11- 1 -.names preset pdata_15_15_ [14390] nrq10_4 [14399] -01-1 1 -0-10 1 -.names pdata_8_8_ [4353] [2830] [14414] ---1 1 -11- 1 -.names preset pdata_1_1_ [14420] nrq14_3 [14429] -01-1 1 -0-10 1 -.names pdata_14_14_ [4354] [2826] [14444] ---1 1 -11- 1 -.names pdata_7_7_ [18384] [2823] [14459] ---1 1 -11- 1 -.names [2821] [2822] [14474] -1- 1 --1 1 -.names [2819] [2820] [14489] -1- 1 --1 1 -.names [2817] [2818] [14504] -1- 1 --1 1 -.names pdata_1_1_ [4375] [2816] [14519] ---1 1 -11- 1 -.names [14525] [4280] [2814] [14534] ---1 1 -11- 1 -.names [14540] [4280] [2812] [14549] ---1 1 -11- 1 -.names [2809] [2810] [14564] -1- 1 --1 1 -.names [16928] [19360] [2807] [14579] ---1 1 -11- 1 -.names [2805] [2806] [14594] -1- 1 --1 1 -.names [2803] [2804] [14609] -1- 1 --1 1 -.names [4350] [4388] [4511] [2802] [14624] ----1 1 -111- 1 -100- 1 -.names [19070] [4368] [2800] [14639] ---1 1 -11- 1 -.names [14660] [4331] [4332] [19091] [14669] -11-- 1 ---11 1 -.names [14675] [19103] [4316] [4327] [14684] -1-1- 1 --1-1 1 -.names [14690] [19087] [4316] [4327] [14699] -1-1- 1 --1-1 1 -.names pdata_6_6_ [4305] [2791] [14714] ---1 1 -11- 1 -.names [2789] [18564] [18565] [18566] [14729] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [18577] [18578] [18583] [14744] -1-- 1 --1- 1 ---1 1 -.names [2764] [18592] [18598] [14759] -1-- 1 --1- 1 ---1 1 -.names [2748] [2749] [18599] [14774] -1-- 1 --1- 1 ---1 1 -.names [18611] [18612] [18616] [14789] -1-- 1 --1- 1 ---1 1 -.names [2725] [2728] [2729] [18619] [14804] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names preset pdata_10_10_ [14810] nrq10_4 [14819] -01-1 1 -0-10 1 -.names pdata_5_5_ [4353] [2722] [14834] ---1 1 -11- 1 -.names preset pdata_0_0_ [14840] nrq14_3 [14849] -01-1 1 -0-10 1 -.names preset pdata_9_9_ [14855] nrq14_3 [14864] -01-1 1 -0-10 1 -.names pdata_4_4_ [4354] [2716] [14879] ---1 1 -11- 1 -.names [2713] [2714] [14894] -1- 1 --1 1 -.names [2711] [2712] [14909] -1- 1 --1 1 -.names [2709] [2710] [14924] -1- 1 --1 1 -.names preset pdata_7_7_ [14930] nrq23_3 [14939] -01-1 1 -0-10 1 -.names [14960] [4280] [2706] [14969] ---1 1 -11- 1 -.names [2703] [2704] [14984] -1- 1 --1 1 -.names [2701] [2702] [14999] -1- 1 --1 1 -.names [2699] [2700] [15014] -1- 1 --1 1 -.names [17305] [19360] [2697] [15029] ---1 1 -11- 1 -.names [19103] [4368] [2696] [15044] ---1 1 -11- 1 -.names [4368] [4388] [4511] [2694] [15059] ----1 1 -111- 1 -100- 1 -.names [15065] [19091] [4316] [4327] [15074] -1-1- 1 --1-1 1 -.names pdata_5_5_ [4305] [2689] [15089] ---1 1 -11- 1 -.names [2687] [18627] [18628] [18629] [15104] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [18640] [18641] [18646] [15119] -1-- 1 --1- 1 ---1 1 -.names [2662] [18654] [18658] [15134] -1-- 1 --1- 1 ---1 1 -.names [2646] [2647] [18659] [15149] -1-- 1 --1- 1 ---1 1 -.names [18669] [18670] [18674] [15164] -1-- 1 --1- 1 ---1 1 -.names [2623] [2626] [2627] [18676] [15179] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names preset pdata_9_9_ [15185] nrq10_4 [15194] -01-1 1 -0-10 1 -.names pdata_6_6_ [4353] [2620] [15209] ---1 1 -11- 1 -.names pdata_15_15_ [4353] [2618] [15224] ---1 1 -11- 1 -.names preset pdata_10_10_ [15230] nrq14_3 [15239] -01-1 1 -0-10 1 -.names pdata_3_3_ [4354] [2614] [15254] ---1 1 -11- 1 -.names [2611] [2612] [15269] -1- 1 --1 1 -.names [2609] [2610] [15284] -1- 1 --1 1 -.names [2607] [2608] [15299] -1- 1 --1 1 -.names preset pdata_13_13_ [15305] nrq23_3 [15314] -01-1 1 -0-10 1 -.names [15320] [17461] [4340] [19368] [15329] -1-1- 1 --1-1 1 -.names [15335] [4280] [2602] [15344] ---1 1 -11- 1 -.names [4308] [19396] [2599] [15359] ---1 1 -11- 1 -.names [2597] [2598] [15374] -1- 1 --1 1 -.names [17305] n_n2471 n_n2487 [2595] [15389] ----1 1 -101- 1 -110- 1 -.names [19082] [4368] [2594] [15404] ---1 1 -11- 1 -.names [19068] [4368] [2592] [15419] ---1 1 -11- 1 -.names [15425] [19065] [4316] [4327] [15434] -1-1- 1 --1-1 1 -.names pdata_4_4_ [4305] [2587] [15449] ---1 1 -11- 1 -.names [2585] [18684] [18685] [18686] [15464] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2574] [18695] [18696] [18697] [15479] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2561] [18707] [18711] [15494] -1-- 1 --1- 1 ---1 1 -.names [2545] [2546] [18712] [15509] -1-- 1 --1- 1 ---1 1 -.names [2541] [2542] [18714] [15524] -1-- 1 --1- 1 ---1 1 -.names [18724] [18725] [18729] [15539] -1-- 1 --1- 1 ---1 1 -.names preset pdata_12_12_ [15545] nrq10_4 [15554] -01-1 1 -0-10 1 -.names pdata_3_3_ [4353] [2521] [15569] ---1 1 -11- 1 -.names pdata_14_14_ [4353] [2519] [15584] ---1 1 -11- 1 -.names preset pdata_5_5_ [15590] nrq14_3 [15599] -01-1 1 -0-10 1 -.names preset pdata_0_0_ [15605] nrq14_3 [15614] -01-1 1 -0-10 1 -.names [2512] [2513] [15629] -1- 1 --1 1 -.names [2510] [2511] [15644] -1- 1 --1 1 -.names [2508] [2509] [15659] -1- 1 --1 1 -.names preset pdata_3_3_ [15665] nrq23_3 [15674] -01-1 1 -0-10 1 -.names [15680] [18176] [4280] [19360] [15689] -1-1- 1 --1-1 1 -.names [15695] [4280] [2503] [15704] ---1 1 -11- 1 -.names [2500] [2501] [15719] -1- 1 --1 1 -.names [18501] [19368] [2498] [15734] ---1 1 -11- 1 -.names preset [15755] [19091] nrq4_2 [15764] -0-11 1 -01-0 1 -.names [15770] [19060] [4331] [4332] [15779] -1-1- 1 --1-1 1 -.names pdata_3_3_ [4305] [2492] [15794] ---1 1 -11- 1 -.names [18734] [18735] [18739] [15809] -1-- 1 --1- 1 ---1 1 -.names [18746] [18747] [18751] [15824] -1-- 1 --1- 1 ---1 1 -.names [2465] [18759] [18763] [15839] -1-- 1 --1- 1 ---1 1 -.names [2449] [2450] [18764] [15854] -1-- 1 --1- 1 ---1 1 -.names [2445] [2446] [18766] [15869] -1-- 1 --1- 1 ---1 1 -.names [18776] [18777] [18781] [15884] -1-- 1 --1- 1 ---1 1 -.names preset pdata_11_11_ [15890] nrq10_4 [15899] -01-1 1 -0-10 1 -.names pdata_4_4_ [4353] [2425] [15914] ---1 1 -11- 1 -.names pdata_13_13_ [4353] [2423] [15929] ---1 1 -11- 1 -.names preset pdata_6_6_ [15935] nrq14_3 [15944] -01-1 1 -0-10 1 -.names preset pdata_15_15_ [15950] nrq14_3 [15959] -01-1 1 -0-10 1 -.names [2416] [2417] [15974] -1- 1 --1 1 -.names [2414] [2415] [15989] -1- 1 --1 1 -.names [2412] [2413] [16004] -1- 1 --1 1 -.names [2410] [2411] [16019] -1- 1 --1 1 -.names [18176] n_n2471 n_n2487 [2408] [16034] ----1 1 -101- 1 -110- 1 -.names [16040] [18176] [4280] [19359] [16049] -1-1- 1 --1-1 1 -.names [19360] [4308] [2404] [16064] ---1 1 -11- 1 -.names [18501] [19367] [2402] [16079] ---1 1 -11- 1 -.names [16928] [19387] [2400] [16094] ---1 1 -11- 1 -.names preset [16100] [19096] nrq4_2 [16109] -0-11 1 -01-0 1 -.names [18813] [18814] [16904] -1- 1 --1 1 -.names [2374] [18815] [16917] -1- 1 --1 1 -.names preset [16920] nrq7_2 [3720] [16928] -0011 1 -.names [17396] nrq7_2 [3718] [18816] [16941] -1--- 1 --111 1 -.names [18828] [18829] [16956] -1- 1 --1 1 -.names [2354] [18830] [16969] -1- 1 --1 1 -.names preset [16920] [16972] [16980] -001 1 -.names preset [16985] [18389] [16993] -010 1 -.names [2351] [18832] [17008] -1- 1 --1 1 -.names preset [17011] [4234] [4242] [17021] -01-- 1 -0-1- 1 -0--1 1 -.names preset pdn [17032] -00 1 -.names preset [17037] [17102] [18025] [17045] -010- 1 -0-01 1 -.names preset [17050] [17115] [17058] -001 1 -.names [2344] [18833] [17073] -1- 1 --1 1 -.names [2341] [18834] [17086] -1- 1 --1 1 -.names preset pdn [17089] [17097] -001 1 -.names preset [17037] [17102] [17110] -010 1 -.names [17058] nrq7_2 [3750] [18835] [17123] -1--- 1 --111 1 -.names [2336] [18836] [17138] -1- 1 --1 1 -.names preset [17141] [4234] [4242] [17151] -01-- 1 -0-1- 1 -0--1 1 -.names preset [17102] [17154] [17162] -001 1 -.names preset [17167] nrq7_2 [3727] [17175] -0011 1 -.names [17240] nrq7_2 [3754] [18837] [17188] -1--- 1 --111 1 -.names [2329] [18838] [17203] -1- 1 --1 1 -.names [17279] nrq7_2 [3715] [18839] [17214] -1--- 1 --111 1 -.names preset [17050] [17219] [17227] -001 1 -.names preset [17180] [17232] [17240] -010 1 -.names preset [17245] nrq7_2 [3746] [17253] -010- 1 -01-0 1 -.names [2324] [18842] [17268] -1- 1 --1 1 -.names preset [17206] [17271] [17279] -010 1 -.names [18384] nrq7_2 [3738] [18843] [17292] -1--- 1 --111 1 -.names preset [17297] nrq7_2 [3747] [17305] -0011 1 -.names preset [17310] [17388] [17318] -010 1 -.names [2319] [18845] [17333] -1- 1 --1 1 -.names preset [17336] [4234] [4242] [17346] -01-- 1 -0-1- 1 -0--1 1 -.names preset [17271] [17349] [17357] -001 1 -.names preset [17167] [17362] [17370] -001 1 -.names preset [17297] [17375] [17383] -001 1 -.names preset [16933] [17388] [17396] -010 1 -.names [18860] [18862] [17411] -1- 1 --1 1 -.names preset [17414] [17843] [17422] -001 1 -.names preset [17427] [17518] [17700] [17435] -01-0 1 -0-10 1 -.names preset nrq7_2 [17710] [17716] [17461] -0111 1 -.names [18874] [18875] [17476] -1- 1 --1 1 -.names preset [17479] [4234] [4242] [17489] -01-- 1 -0-1- 1 -0--1 1 -.names [2280] [18876] [17502] -1- 1 --1 1 -.names preset [17414] [17505] [17513] -001 1 -.names preset [17518] [17700] [17817] [17526] -010- 1 -0-01 1 -.names [17531] [4466] [2276] [17539] ---1 1 -11- 1 -.names preset ppeaki_7_7_ [17544] nlbr8_2_e [17554] -01-1 1 -0-10 1 -.names [18889] [18890] [17567] -1- 1 --1 1 -.names preset [17570] nen3_5 nrq3_11 [17578] -01-0 1 -0-10 1 -.names preset [17583] [17648] [17700] [17591] -01-0 1 -0-10 1 -.names nrq3_11 [2246] [18906] [17604] --1- 1 -0-1 1 -.names preset ppeaki_6_6_ [17609] nlbr8_2_e [17619] -01-1 1 -0-10 1 -.names [18919] [18920] [17632] -1- 1 --1 1 -.names preset [17570] [17635] nrq3_11 [17643] -01-0 1 -0-10 1 -.names preset [17427] [17648] [17700] [17656] -01-0 1 -0-10 1 -.names preset [18897] [18898] [18901] [17669] -0111 1 -.names preset ppeaki_5_5_ [17674] nlbr8_2_e [17684] -01-1 1 -0-10 1 -.names [18932] [18933] [17697] -1- 1 --1 1 -.names preset [17700] [18142] [17708] -001 1 -.names preset ppeaki_4_4_ [17713] nlbr8_2_e [17723] -01-1 1 -0-10 1 -.names [18945] [18946] [17736] -1- 1 --1 1 -.names preset [17700] [17739] [17747] -001 1 -.names [17752] [4466] nrq7_2 [17710] [17760] -11-- 1 --111 1 -.names [2187] [18947] [17775] -1- 1 --1 1 -.names [2184] [18948] [17788] -1- 1 --1 1 -.names preset [17414] [17791] nen2_3 [17799] -001- 1 -00-1 1 -.names preset pdn nrq3_11 [17812] -001 1 -.names preset [17700] [17817] [2179] [17825] ----1 1 -001- 1 -.names [18962] [18963] [18964] [17840] -1-- 1 --1- 1 ---1 1 -.names preset [17414] [17791] [17843] [17851] -00-1 1 -0010 1 -.names preset [17856] [4513] [17866] -01- 1 -0-1 1 -.names preset [17869] [4234] [4242] [17879] -01-- 1 -0-1- 1 -0--1 1 -.names preset [17882] [4234] [4242] [17892] -01-- 1 -0-1- 1 -0--1 1 -.names [18994] [18995] [18999] [17905] -1-- 1 --1- 1 ---1 1 -.names preset [17908] [4234] [4242] [17918] -01-- 1 -0-1- 1 -0--1 1 -.names [2116] [19000] [17931] -1- 1 --1 1 -.names preset [17934] [4234] [4242] [17944] -01-- 1 -0-1- 1 -0--1 1 -.names preset [17947] [4234] [4242] [17957] -01-- 1 -0-1- 1 -0--1 1 -.names preset [17960] [4234] [4242] [17970] -01-- 1 -0-1- 1 -0--1 1 -.names [2107] [19001] [17983] -1- 1 --1 1 -.names preset [17635] [17986] nrq3_11 [17994] -01-0 1 -0-10 1 -.names preset [17700] [17999] [18077] [18007] -001- 1 -00-1 1 -.names [2100] [2101] [18022] -1- 1 --1 1 -.names [18025] [4458] nrq7_2 [3740] [18033] -11-- 1 --111 1 -.names preset [18038] [4234] [4242] [18048] -01-- 1 -0-1- 1 -0--1 1 -.names preset pdn [17414] nrq3_11 [18059] -001- 1 -00-1 1 -.names preset pdn [18064] [2092] [18072] ----1 1 -001- 1 -.names preset [17583] [17700] [18077] [18085] -010- 1 -0-01 1 -.names [2088] [2089] [18100] -1- 1 --1 1 -.names preset [18103] [18168] [18111] -010 1 -.names preset [18116] [4234] [4242] [18126] -01-- 1 -0-1- 1 -0--1 1 -.names [2084] [2085] [18139] -1- 1 --1 1 -.names preset [17700] [18142] [18220] [18150] -001- 1 -00-1 1 -.names [2080] [2081] [18165] -1- 1 --1 1 -.names preset nrq7_2 [17710] [17711] [18176] -0111 1 -.names preset [18181] [4234] [4242] [18191] -01-- 1 -0-1- 1 -0--1 1 -.names [2076] [19004] [18204] -1- 1 --1 1 -.names preset pdn [18207] [4513] [18215] -001- 1 -00-1 1 -.names preset [17700] [17999] [18220] [18228] -001- 1 -00-1 1 -.names [2069] [2070] [18243] -1- 1 --1 1 -.names preset [17453] [18246] [18254] -001 1 -.names [19018] [19019] [18269] -1- 1 --1 1 -.names [17708] [2050] [2051] [18282] -1-- 1 --1- 1 ---1 1 -.names nrq7_2 [3723] [2049] [19022] [18293] ---1- 1 -11-1 1 -.names preset [18298] [18376] [18306] -010 1 -.names preset [18311] [18389] [18506] [18319] -010- 1 -0-01 1 -.names [19037] [19038] [18334] -1- 1 --1 1 -.names [2028] [19039] [18347] -1- 1 --1 1 -.names preset [18350] [4234] [4242] [18360] -01-- 1 -0-1- 1 -0--1 1 -.names preset [18285] [18363] [18415] [18371] -0-10 1 -0100 1 -.names preset [17284] [18376] [18384] -010 1 -.names preset [18311] [18389] [18397] -010 1 -.names [19051] [19052] [18412] -1- 1 --1 1 -.names preset [18363] [18415] [18423] -010 1 -.names preset [18428] [18493] [18436] -010 1 -.names preset [17232] [18441] [18449] -001 1 -.names [19074] [19075] [18464] -1- 1 --1 1 -.names [1991] [1992] [18475] -1- 1 --1 1 -.names preset [18415] [18480] [18488] -001 1 -.names preset [18493] nrq7_2 [3711] [18501] -0011 1 -.names [18506] [4467] nrq7_2 [3744] [18514] -11-- 1 --111 1 -.names [19094] [19095] [18529] -1- 1 --1 1 -.names [19110] [19111] [18542] -1- 1 --1 1 -.names preset pdn [18545] n_n3081 [18555] -011- 1 -00-1 1 -0-11 1 -.names [19124] [19125] [18568] -1- 1 --1 1 -.names preset [18571] [4234] [4242] [18581] -01-- 1 -0-1- 1 -0--1 1 -.names preset [18584] [4234] [4242] [18594] -01-- 1 -0-1- 1 -0--1 1 -.names preset pdn [18597] [1936] [18605] ----1 1 -001- 1 -.names [18610] [4466] [19135] [19136] [18618] ---1- 1 ----1 1 -11-- 1 -.names [19150] [19151] [18633] -1- 1 --1 1 -.names [1915] [19163] [19164] [18644] -1-- 1 --1- 1 ---1 1 -.names preset [17791] [17843] [4305] -010 1 -.names [4199] n_n2344 [3775] n_n2772 [4260] -1111 1 -.names [4199] n_n2344 [3770] n_n2772 [4269] -1111 1 -.names [4226] [4199] n_n2333 n_n2772 [4298] -1--1 1 --111 1 -.names [4199] n_n2344 [3784] n_n2772 [4392] -1111 1 -.names [4199] n_n2772 [4215] [4397] -111 1 -.names n_n3925 [4202] [4266] [5514] [4226] -1--1 1 -101- 1 -.names preset [17453] [18246] [4352] -010 1 -.names preset nrq7_2 [17710] [17711] [4280] -00-- 1 -0-0- 1 -0--0 1 -.names preset [17102] [17154] [4353] -010 1 -.names preset [18285] nrq7_2 [3723] [4243] -0011 1 -.names preset [18285] nrq7_2 [3723] [4253] -01-- 1 -0-0- 1 -0--0 1 -.names preset [17167] [17362] [4354] -010 1 -.names preset [18506] nrq7_2 [3744] [4245] -0011 1 -.names preset [18506] nrq7_2 [3744] [4252] -01-- 1 -0-0- 1 -0--0 1 -.names preset [17310] [17388] [4375] -001 1 -.names n_n2486 n_n2471 n_n2487 [4457] [19360] -10-1 1 -00-0 1 -1111 1 -0101 1 -0110 1 -1100 1 -.names preset nrq7_2 [17710] [17716] [4340] -00-- 1 -0-0- 1 -0--0 1 -.names n_n2475 [19739] [5157] [5158] [19390] -111- 1 -001- 1 -11-1 1 -00-1 1 -0100 1 -1000 1 -.names preset [18103] [18168] [4308] -001 1 -.names preset [18285] [18363] [4306] -010 1 -.names preset [17284] nrq7_2 [3738] [4317] -01-- 1 -0-0- 1 -0--0 1 -.names preset [17284] nrq7_2 [3738] [4381] -0011 1 -.names n_n2473 [19731] [19474] [4301] [19368] --111 1 -00-0 1 -1011 1 -1101 1 -0100 1 -1000 1 -.names n_n2478 [19747] [5164] [5166] [19359] -111- 1 -001- 1 -11-1 1 -00-1 1 -0100 1 -1000 1 -.names preset [18311] [18506] [4377] -001 1 -.names preset [16933] nrq7_2 [3718] [4277] -01-- 1 -0-0- 1 -0--0 1 -.names preset [16933] nrq7_2 [3718] [4278] -0011 1 -.names ppeaka_6_6_ ndn_latch24_2 n_n2449 [19171] [19088] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names preset nrq4_2 [4350] -01 1 -.names ppeaka_10_10_ ndn_latch24_2 n_n2445 [19205] [19092] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names preset [17635] [17986] [4345] -010 1 -.names ppeaka_4_4_ ndn_latch24_2 n_n2451 [19180] [19103] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names preset [18025] nrq7_2 [3740] [4330] -01-- 1 -0-0- 1 -0--0 1 -.names preset [18025] nrq7_2 [3740] [4374] -0011 1 -.names ppeaka_9_9_ ndn_latch24_2 n_n2446 [19227] [19060] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names preset [17037] [18025] [4360] -001 1 -.names ppeaka_3_3_ ndn_latch24_2 n_n2452 [19153] [19097] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names preset [17206] nrq7_2 [3715] [4331] -01-- 1 -0-0- 1 -0--0 1 -.names preset [17206] nrq7_2 [3715] [4332] -0011 1 -.names nrq21_7 n_n2454 [4496] [4451] [19061] -101- 1 -110- 1 --010 1 --100 1 -0111 1 -0001 1 -.names ppeaka_12_12_ ndn_latch24_2 n_n2443 [19191] [19091] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names preset [17245] nrq7_2 [3746] [4336] -01-- 1 -0-0- 1 -0--0 1 -.names preset [17245] nrq7_2 [3746] [4365] -0011 1 -.names n_n2474 [19514] [19733] [4410] [19367] -11-1 1 -1-11 1 --111 1 -00-0 1 -0-00 1 --000 1 -.names n_n2481 [19729] [5171] [5172] [19387] -111- 1 -001- 1 -11-1 1 -00-1 1 -0100 1 -1000 1 -.names ppeaka_7_7_ ndn_latch24_2 n_n2448 [19221] [19070] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names ppeaka_11_11_ ndn_latch24_2 n_n2444 [19232] [19096] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names ppeaka_8_8_ ndn_latch24_2 n_n2447 [19196] [19072] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names ppeaka_13_13_ ndn_latch24_2 n_n2442 [19215] [19087] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names ppeaka_5_5_ ndn_latch24_2 n_n2450 [19157] [19082] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names n_n2484 [19452] [5190] [17770] [19396] -111- 1 -001- 1 -11-1 1 -00-1 1 -0100 1 -1000 1 -.names preset [17999] [18077] [4383] -001 1 -.names ppeaks_0_0_ [4273] [17906] [17913] [19073] --001 1 -01-0 1 -0-10 1 --010 1 -.names preset [17180] nrq7_2 [3754] [4307] -0011 1 -.names preset [17180] nrq7_2 [3754] [4325] -01-- 1 -0-0- 1 -0--0 1 -.names ppeaka_14_14_ ndn_latch24_2 n_n2441 [19175] [19068] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names ppeaka_2_2_ ndn_latch24_2 n_n2453 [19167] [19065] -0-01 1 --001 1 -0-10 1 --010 1 -1111 1 -1100 1 -.names preset [17414] [17505] [4357] -010 1 -.names ppeaki_14_14_ ppeaki_10_10_ n_n2344 [4292] [1427] -1-1- 1 --1-1 1 -.names preset [18636] nrq7_2 [17582] [4199] -01-- 1 -0-01 1 -.names preset [18142] [18220] [4358] -001 1 -.names ppeaki_8_8_ ppeaki_12_12_ n_n2344 [4292] [1342] --11- 1 -1--1 1 -.names ppeaki_9_9_ ppeaki_13_13_ n_n2344 [4292] [1353] --11- 1 -1--1 1 -.names preset [17570] [17635] [4359] -010 1 -.names ppeaki_13_13_ [4292] [1412] -11 1 -.names ppeaki_12_12_ [4292] [1397] -11 1 -.names preset [17115] nrq7_2 [3750] [4316] -01-- 1 -0-0- 1 -0--0 1 -.names preset [17115] nrq7_2 [3750] [4327] -0011 1 -.names ppeaki_15_15_ ppeaki_11_11_ n_n2344 [4292] [1439] -1-1- 1 --1-1 1 -.names ppeaki_6_6_ ppeaki_10_10_ n_n2344 [4292] [1368] --11- 1 -1--1 1 -.names preset [17427] [17648] [4368] -010 1 -.names ppeaki_11_11_ ppeaki_7_7_ n_n2344 [4292] [1386] -1-1- 1 --1-1 1 -.names ppeaki_15_15_ [4292] [1411] -11 1 -.names ppeaki_4_4_ ppeaki_8_8_ n_n2344 [4292] [1398] --11- 1 -1--1 1 -.names ppeaki_14_14_ [4292] [1434] -11 1 -.names ppeaki_5_5_ ppeaki_9_9_ n_n2344 [4292] [1413] --11- 1 -1--1 1 -.names preset nrq4_5 [18795] [18796] [4341] -011- 1 -01-1 1 -.names preset nrq23_3 [18795] [18796] [4351] -011- 1 -01-1 1 -.names preset nrq4_9 [18795] [18796] [4369] -011- 1 -01-1 1 -.names preset ndn_latch12_11 [18795] [18796] [4378] -011- 1 -01-1 1 -.names preset nrq17_3 [18795] [18796] [4382] -011- 1 -01-1 1 -.names preset [18389] [4467] -00 1 -.names preset [17102] [4458] -00 1 -.names [17180] [17232] nrq21_7 -10 1 -.names [17206] [17271] nrq13_4 -10 1 -.names preset [17700] [4300] -00 1 -.names [18636] nrq7_2 [17582] ndn7_2 -1-- 1 --01 1 -.names preset [18636] nrq7_2 [17582] [4466] -001- 1 -00-0 1 -.names [18467] nen3_2 n_n3925 nen3_5 -1-- 1 --10 1 -.names [18900] [18901] [18902] [18904] nrq3_11 ----1 1 -111- 1 -.names [18610] n_n2344 nsl8_2 nrq7_2 nrq8_2 -0101 1 -.names preset_0_0_ pdn [17024] [18545] nen2_3 -100- 1 --011 1 -.names [17037] [17518] [17817] [18025] [4235] --01- 1 -0--1 1 -.names [5528] [17599] [17600] [17601] [4513] -00-1 1 -0-01 1 -.names [17461] [18176] [18798] [18799] [4241] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [18168] nrq7_2 [3770] [17710] nrq10_4 -0111 1 -.names [17999] [18220] nrq4_14 -10 1 -.names [18363] [18415] nrq14_8 -10 1 -.names preset_0_0_ pdn [17024] [18545] nen3_2 -000- 1 -00-0 1 --010 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 n_n2344 -0010 1 -.names [17555] [17556] [17557] [17558] nsl8_2 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names nsl8_2 [17564] [17574] [17580] nrq7_2 ----1 1 -01-- 1 -0-1- 1 -.names pdn [17089] nrq1_4 -10 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3723] -1000 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3744] -1110 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3738] -1011 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3718] -1101 1 -.names pirq_0_0_ [18064] [18129] n_n3925 -10- 1 --11 1 -.names [17635] [17986] ndn_latch3_9 -10 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3740] -0001 1 -.names [17037] [18025] ndn_latch12_11 -01 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3715] -0011 1 -.names [17206] nrq7_2 [3715] ndn_latch13_2 -011 1 -.names [16933] nrq7_2 [3718] ndn_latch24_2 -011 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3746] -1111 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3747] -0101 1 -.names [18506] nrq7_2 [3744] nrq23_3 -011 1 -.names [4471] [17602] [17603] [17605] [3770] --11- 1 -1--1 1 -.names [4471] [17606] [17607] [17608] [3775] --11- 1 -1--1 1 -.names [17570] [18467] nen3_2 n_n3925 nrq3_5 -01-- 1 -0-10 1 -.names [18285] nrq7_2 [3723] nrq14_3 -011 1 -.names [17583] [17648] nrq4_9 -01 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3727] -1001 1 -.names [17284] nrq7_2 [3738] nrq17_3 -011 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3711] -0100 1 -.names [17115] nrq7_2 [3750] nrq15_5 -011 1 -.names [17180] nrq7_2 [3754] nrq21_5 -011 1 -.names [17518] [17817] nrq4_5 -01 1 -.names [17817] [18467] nen3_2 n_n3925 nrq4_2 -0011 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3750] -1010 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3754] -0111 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 n_n2333 -1100 1 -.names ppeaki_2_2_ [17531] [18012] n_n3712 -10- 1 --11 1 -.names [4468] [4470] [17517] [17519] n_n2326 --11- 1 -1--1 1 -.names [4470] [4483] [17520] [17521] n_n2314 -11-- 1 ---11 1 -.names [4465] [4471] [17522] [17523] n_n2325 --11- 1 -1--1 1 -.names [4483] [4459] [17524] [17525] n_n2316 -1-1- 1 --1-1 1 -.names [4470] [4391] [4480] [17527] n_n2318 -1-1- 1 --1-1 1 -.names [4465] [4472] [17528] [17529] n_n2323 --11- 1 -1--1 1 -.names [4483] [4459] [17530] [17532] n_n2317 -1-1- 1 --1-1 1 -.names [4483] [4472] [17533] [17534] n_n2315 -11-- 1 ---11 1 -.names [4459] [4480] [17535] [17536] n_n2321 --11- 1 -1--1 1 -.names [4465] [4471] [17537] [17538] n_n2324 --11- 1 -1--1 1 -.names [4459] [4480] [17540] [17541] n_n2320 --11- 1 -1--1 1 -.names [4470] [4465] [17542] [17543] n_n2322 -1-1- 1 --1-1 1 -.names [4391] [4480] [4472] [17545] n_n2319 --11- 1 -1--1 1 -.names [4468] [4472] [17546] [17547] [3784] --11- 1 -1--1 1 -.names [17609] [17674] [4468] -01 1 -.names ppeaki_4_4_ ppeaki_5_5_ [4470] -11 1 -.names [17544] [17752] [4391] -11 1 -.names ppeaki_6_6_ ppeaki_7_7_ [17752] [4483] -110 1 -.names ndn_latch13_2 nrq15_5 nrq21_5 [17865] [4273] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names ppeaks_2_2_ [4273] [17900] n_n2453 ---1 1 -11- 1 -.names ppeaks_3_3_ [4273] [17894] n_n2452 ---1 1 -11- 1 -.names [17544] [17609] [17752] [4465] -011 1 -.names ppeaki_5_5_ ppeaki_7_7_ [17752] [4471] -000 1 -.names [17544] [17674] [17752] [4459] -101 1 -.names ppeaki_6_6_ ppeaki_7_7_ [17752] [4480] -010 1 -.names ppeaki_4_4_ ppeaki_5_5_ [4472] -01 1 -.names pdn [17089] [17596] [4513] [4205] -10-- 1 ---01 1 -.names [18636] nrq7_2 [4205] [17582] n_n2772 -1--- 1 ---1- 1 --0-1 1 -.names [17284] nrq7_2 [3738] nrq4_9 [4234] ----1 1 -011- 1 -.names [4235] ndn_latch13_2 nrq15_5 nrq21_5 [4242] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names ppeaks_12_12_ [4273] [18005] n_n2443 ---1 1 -11- 1 -.names ppeaks_6_6_ [4273] [17873] n_n2449 ---1 1 -11- 1 -.names ppeaki_3_3_ [17531] [18090] n_n3711 -10- 1 --11 1 -.names ppeaks_13_13_ [4273] [17998] n_n2442 ---1 1 -11- 1 -.names ppeaks_9_9_ [4273] [17949] n_n2446 ---1 1 -11- 1 -.names ppeaks_8_8_ [4273] [17955] n_n2447 ---1 1 -11- 1 -.names ppeaks_10_10_ [4273] [17941] n_n2445 ---1 1 -11- 1 -.names ppeaks_14_14_ [4273] [17991] n_n2441 ---1 1 -11- 1 -.names ppeaks_15_15_ [4273] [17984] n_n2440 ---1 1 -11- 1 -.names ppeaks_11_11_ [4273] [18013] n_n2444 ---1 1 -11- 1 -.names ppeaks_1_1_ [4273] [17920] n_n2454 ---1 1 -11- 1 -.names ppeaks_5_5_ [4273] [17880] n_n2450 ---1 1 -11- 1 -.names ppeaks_4_4_ [4273] [17887] n_n2451 ---1 1 -11- 1 -.names ppeaks_7_7_ [4273] [17963] n_n2448 ---1 1 -11- 1 -.names preset_0_0_ [17024] [18545] n_n3081 -10- 1 --11 1 -.names ppeaki_0_0_ [17531] [18155] n_n3714 -10- 1 --11 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [3720] -0110 1 -.names [17752] nsl8_2 nrq7_2 [17709] nlbr8_2_e -0011 1 -.names [18103] [18168] [17717] [17718] [4265] ---1- 1 ----1 1 -01-- 1 -.names [17037] [17102] [17284] [18376] [4488] -10-- 1 ---10 1 -.names ppeaks_12_12_ [4265] [17719] [17742] n_n2475 ----1 1 -11-- 1 -1-1- 1 -.names ppeaki_1_1_ [17531] [18233] n_n3713 -10- 1 --11 1 -.names ppeaks_15_15_ [4265] [17719] [17841] n_n2472 ----1 1 -11-- 1 -1-1- 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [4292] -1111 1 -0111 1 -1011 1 -0011 1 -1101 1 -0101 1 -1001 1 -0001 1 -1110 1 -0110 1 -1010 1 -1100 1 -0100 1 -1000 1 -.names ppeaks_3_3_ [4265] [17719] [17768] n_n2484 ----1 1 -11-- 1 -1-1- 1 -.names ppeaks_13_13_ [4265] [17719] [17829] n_n2474 ----1 1 -11-- 1 -1-1- 1 -.names ppeaks_8_8_ [4265] [17719] [17796] n_n2479 ----1 1 -11-- 1 -1-1- 1 -.names ppeaks_4_4_ [4265] [17719] [17774] n_n2483 ----1 1 -11-- 1 -1-1- 1 -.names ppeaks_2_2_ [4265] [17719] [17763] n_n2485 ----1 1 -11-- 1 -1-1- 1 -.names ppeaks_5_5_ [4265] [17719] [17780] n_n2482 ----1 1 -11-- 1 -1-1- 1 -.names ppeaks_7_7_ [4265] [17719] [17792] n_n2480 ----1 1 -11-- 1 -1-1- 1 -.names ppeaks_1_1_ [4265] [17719] [17731] n_n2486 ----1 1 -11-- 1 -1-1- 1 -.names ppeaks_14_14_ [4265] [17719] [17833] n_n2473 ----1 1 -11-- 1 -1-1- 1 -.names ndn_latch24_2 nrq17_3 [4265] [17722] n_n2471 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names ppeaks_0_0_ [4265] [17719] [17727] n_n2487 ----1 1 -11-- 1 -1-1- 1 -.names ppeaks_11_11_ [4265] [17719] [17813] n_n2476 ----1 1 -11-- 1 -1-1- 1 -.names ppeaks_9_9_ [4265] [17719] [17801] n_n2478 ----1 1 -11-- 1 -1-1- 1 -.names ppeaks_10_10_ [4265] [17719] [17808] n_n2477 ----1 1 -11-- 1 -1-1- 1 -.names ppeaks_6_6_ [4265] [17719] [17784] n_n2481 ----1 1 -11-- 1 -1-1- 1 -.names [17688] [17689] [17690] [17691] [4024] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4265] [4457] [17719] [17722] [19749] -11-- 1 --11- 1 --1-1 1 -0000 1 -.names n_n2486 n_n2471 n_n2487 [4457] [19466] -111- 1 -11-1 1 --111 1 -10-0 1 -.names ppeaka_12_12_ [5271] [5272] [17758] [19739] ----1 1 -000- 1 -.names n_n2475 [19739] [5157] [5158] [19514] -11-- 1 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names ppeaka_11_11_ [4455] [5273] [5274] [19741] ---1- 1 ----1 1 -00-- 1 -.names n_n2477 [19735] [19504] [19531] -11- 1 -1-1 1 --11 1 -.names n_n2476 [5273] [5274] [5275] [4438] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4508] [5288] [5289] [17748] [19727] ----1 1 -100- 1 -.names n_n2483 [19725] [19479] [19456] -11- 1 -1-1 1 --11 1 -.names n_n2482 [5286] [17748] [4440] -1-- 1 --1- 1 ---1 1 -.names [19743] [4455] [5277] [17753] [19735] --01- 1 -110- 1 -00-1 1 --100 1 -.names n_n2478 [19747] [5164] [5166] [19504] -11-- 1 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names nrq10_4 [19749] [4452] [5288] [19725] ---01 1 -000- 1 -1-10 1 --110 1 -.names n_n2484 [19452] [5190] [17770] [19479] -11-- 1 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names [5106] [17836] [19731] -1- 1 --1 1 -.names n_n2474 [19514] [19733] [19474] -11- 1 -1-1 1 --11 1 -.names n_n2472 [5088] [5091] [17846] [4301] -11-- 1 -1-1- 1 -1--1 1 -0000 1 -.names nrq10_4 [19989] [5241] [5243] [19747] ---1- 1 ----1 1 -00-- 1 -.names ppeaka_2_2_ [4457] [5290] [5291] [19721] ---1- 1 ----1 1 -00-- 1 -.names n_n2485 [19466] [19721] [19452] -11- 1 -1-1 1 --11 1 -.names [4453] [5271] [5272] [19733] -01- 1 -0-1 1 -100 1 -.names [19989] [4456] [19737] -01 1 -10 1 -.names n_n2481 [19729] [5171] [5172] [19520] -11-- 1 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n_n2480 [19520] [19989] [4456] [19495] -11-- 1 -1-01 1 --101 1 -1-10 1 --110 1 -.names n_n2450 [19157] [17928] [19171] -11- 1 -1-1 1 --11 1 -.names n_n2449 [19171] [17932] [19221] -11- 1 -1-1 1 --11 1 -.names n_n2446 [19227] [17966] [19205] -11- 1 -1-1 1 --11 1 -.names n_n2445 [19205] [17969] [19232] -11- 1 -1-1 1 --11 1 -.names n_n2451 [19180] [17927] [19157] -11- 1 -1-1 1 --11 1 -.names n_n2452 [19153] [17926] [19180] -11- 1 -1-1 1 --11 1 -.names n_n2441 n_n2440 [19175] [18017] [4388] -101- 1 -010- 1 -10-1 1 --011 1 -01-0 1 --100 1 -.names ppeaka_15_15_ [16933] nrq7_2 [3718] [4511] -0--- 1 --1-- 1 ---0- 1 ----0 1 -.names n_n2447 [19196] [17965] [19227] -11- 1 -1-1 1 --11 1 -.names n_n2453 [19167] [17925] [19153] -11- 1 -1-1 1 --11 1 -.names ppeaks_0_0_ [4273] [17906] [17913] [4496] --00- 1 -0--0 1 --0-0 1 -.names n_n2444 [19232] [18014] [19191] -11- 1 -1-1 1 --11 1 -.names n_n2443 [19191] [18015] [19215] -11- 1 -1-1 1 --11 1 -.names n_n2473 [5106] [17836] [4410] -11- 1 -1-1 1 -000 1 -.names ppeaka_6_6_ nrq10_4 [19989] [17785] [19729] -0-0- 1 --00- 1 ---01 1 -.names n_n2448 [19221] [17964] [19196] -11- 1 -1-1 1 --11 1 -.names n_n2442 [19215] [18016] [19175] -11- 1 -1-1 1 --11 1 -.names ppeaka_7_7_ ppeaka_8_8_ nrq10_4 [19989] [19743] --0-0 1 ---00 1 -101- 1 -0111 1 -.names n_n2479 [19743] [4450] -1- 1 --1 1 -.names nrq21_7 n_n2454 [4451] [17924] [19167] -11-- 1 --10- 1 -10-1 1 --001 1 -0111 1 -.names ppeaka_1_1_ [16933] nrq7_2 [3718] [4451] -0--- 1 --1-- 1 ---0- 1 ----0 1 -.names ppeaka_1_1_ nrq7_2 [17710] [17711] [4457] -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names ppeaka_2_2_ nrq7_2 [17710] [17711] [4507] -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names ppeaka_4_4_ nrq7_2 [17710] [17711] [4452] -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names ppeaka_5_5_ nrq7_2 [17710] [17711] [4508] -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names [5283] [5286] [17748] [17749] [19989] -1--- 1 --001 1 -.names ppeaka_13_13_ nrq7_2 [17710] [17711] [4453] -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names ppeaka_8_8_ ppeaka_9_9_ [19743] [5277] [18861] ----1 1 -000- 1 -.names ppeaka_10_10_ nrq7_2 [17710] [17711] [4455] -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names ppeaka_7_7_ nrq7_2 [17710] [17711] [4456] -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names ppeaka_11_11_ nrq7_2 [17710] [17711] [4509] -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names n_n3081 [5528] [17599] [17600] [4202] -1--- 1 --00- 1 --0-0 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [4204] -1111 1 -1001 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [4207] -0111 1 -1010 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [4208] -1011 1 -0101 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [4209] -1111 1 -1001 1 -1100 1 -.names n_n2344 [3784] [4209] [4211] ---1 1 -11- 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [4212] -0011 1 -0001 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [4215] -1011 1 -0101 1 -0110 1 -0100 1 -.names preset pdn [17089] [4266] -010 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [4219] -1101 1 -0010 1 -1000 1 -.names preset nrq3_5 [18795] [18796] [4303] -011- 1 -01-1 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [4224] -0111 1 -0011 1 -0001 1 -1010 1 -.names n_n3712 n_n3711 n_n3714 n_n3713 [4225] -1111 1 -1011 1 -0101 1 -1001 1 -0110 1 -1100 1 -0100 1 -.names preset n_n2772 [5520] [5522] [4515] ---1- 1 -00-- 1 -0--1 1 -.names preset [16920] nrq7_2 [1914] -011 1 -.names nrq7_2 [1935] [19135] [19136] [1915] -11-- 1 -1-1- 1 -1--1 1 -.names [8255] [17240] [18795] [18796] [1918] -111- 1 -11-1 1 -.names [6065] [18423] [18795] [18796] [1920] -111- 1 -11-1 1 -.names [9410] [18397] [18795] [18796] [1921] -111- 1 -11-1 1 -.names [10970] [17279] [18795] [18796] [1922] -111- 1 -11-1 1 -.names ppeaks_7_7_ [4241] [18795] [18796] [1923] -111- 1 -11-1 1 -.names preset paddress_7_7_ [18795] [18796] [1926] -0100 1 -.names [12905] [17058] [18795] [18796] [1927] -111- 1 -11-1 1 -.names [11075] n_n3925 [4303] [1928] -111 1 -.names ppeaka_7_7_ [2391] [2392] [1929] -11- 1 -1-1 1 -.names ppeakp_7_7_ n_n3925 [4303] [2394] [1930] -1--1 1 -101- 1 -.names [18610] [4466] [1935] -11 1 -.names preset [18900] [18901] [19126] [1936] -0111 1 -.names [7625] [17240] [18795] [18796] [1944] -111- 1 -11-1 1 -.names [6740] [18423] [18795] [18796] [1946] -111- 1 -11-1 1 -.names [7475] [18397] [18795] [18796] [1947] -111- 1 -11-1 1 -.names [11690] [17279] [18795] [18796] [1948] -111- 1 -11-1 1 -.names ppeaks_6_6_ [4241] [18795] [18796] [1949] -111- 1 -11-1 1 -.names preset paddress_6_6_ [18795] [18796] [1952] -0100 1 -.names [13865] [17058] [18795] [18796] [1953] -111- 1 -11-1 1 -.names [9950] n_n3925 [4303] [1954] -111 1 -.names ppeaka_6_6_ [2391] [2392] [1955] -11- 1 -1-1 1 -.names ppeakp_6_6_ n_n3925 [4303] [2394] [1956] -1--1 1 -101- 1 -.names [6995] [17240] [18795] [18796] [1961] -111- 1 -11-1 1 -.names [4670] [18423] [18795] [18796] [1963] -111- 1 -11-1 1 -.names [8105] [18397] [18795] [18796] [1964] -111- 1 -11-1 1 -.names [11465] [17279] [18795] [18796] [1965] -111- 1 -11-1 1 -.names ppeaks_5_5_ [4241] [18795] [18796] [1966] -111- 1 -11-1 1 -.names preset paddress_5_5_ [18795] [18796] [1969] -0100 1 -.names [13505] [17058] [18795] [18796] [1970] -111- 1 -11-1 1 -.names [10220] n_n3925 [4303] [1971] -111 1 -.names ppeaka_5_5_ [2391] [2392] [1972] -11- 1 -1-1 1 -.names ppeakp_5_5_ n_n3925 [4303] [2394] [1973] -1--1 1 -101- 1 -.names [12245] [17240] [18795] [18796] [1976] -111- 1 -11-1 1 -.names [5375] [18423] [18795] [18796] [1978] -111- 1 -11-1 1 -.names [6170] [18397] [18795] [18796] [1979] -111- 1 -11-1 1 -.names [5615] [17279] [18795] [18796] [1980] -111- 1 -11-1 1 -.names ppeaks_4_4_ [4241] [18795] [18796] [1981] -111- 1 -11-1 1 -.names preset paddress_4_4_ [18795] [18796] [1984] -0100 1 -.names [14675] [17058] [18795] [18796] [1985] -111- 1 -11-1 1 -.names [10505] n_n3925 [4303] [1986] -111 1 -.names ppeaka_4_4_ [2391] [2392] [1987] -11- 1 -1-1 1 -.names ppeakp_4_4_ n_n3925 [4303] [2394] [1988] -1--1 1 -101- 1 -.names [18467] nen3_2 n_n3925 [19076] [1991] -0111 1 -.names [17032] [18467] nen3_2 n_n3925 [1992] -11-- 1 -1-10 1 -.names [12455] [17240] [18795] [18796] [1995] -111- 1 -11-1 1 -.names [9995] [18423] [18795] [18796] [1997] -111- 1 -11-1 1 -.names [6845] [18397] [18795] [18796] [1998] -111- 1 -11-1 1 -.names [4910] [17279] [18795] [18796] [1999] -111- 1 -11-1 1 -.names ppeaks_3_3_ [4241] [18795] [18796] [2000] -111- 1 -11-1 1 -.names preset paddress_3_3_ [18795] [18796] [2003] -0100 1 -.names [14255] [17058] [18795] [18796] [2004] -111- 1 -11-1 1 -.names [10790] n_n3925 [4303] [2005] -111 1 -.names ppeaka_3_3_ [2391] [2392] [2006] -11- 1 -1-1 1 -.names ppeakp_3_3_ n_n3925 [4303] [2394] [2007] -1--1 1 -101- 1 -.names [12680] [17240] [18795] [18796] [2010] -111- 1 -11-1 1 -.names [9725] [18423] [18795] [18796] [2012] -111- 1 -11-1 1 -.names [4760] [18397] [18795] [18796] [2013] -111- 1 -11-1 1 -.names [6980] [17279] [18795] [18796] [2014] -111- 1 -11-1 1 -.names ppeaks_2_2_ [4241] [18795] [18796] [2015] -111- 1 -11-1 1 -.names preset paddress_2_2_ [18795] [18796] [2018] -0100 1 -.names [15425] [17058] [18795] [18796] [2019] -111- 1 -11-1 1 -.names [11060] n_n3925 [4303] [2020] -111 1 -.names ppeaka_2_2_ [2391] [2392] [2021] -11- 1 -1-1 1 -.names ppeakp_2_2_ n_n3925 [4303] [2394] [2022] -1--1 1 -101- 1 -.names preset [18337] [4234] [4242] [2028] -0100 1 -.names preset ppeaka_0_0_ [4234] [2029] -011 1 -.names [12920] [17240] [18795] [18796] [2032] -111- 1 -11-1 1 -.names [9290] [18423] [18795] [18796] [2034] -111- 1 -11-1 1 -.names [10310] [18397] [18795] [18796] [2035] -111- 1 -11-1 1 -.names [6305] [17279] [18795] [18796] [2036] -111- 1 -11-1 1 -.names ppeaks_1_1_ [4241] [18795] [18796] [2037] -111- 1 -11-1 1 -.names preset paddress_1_1_ [18795] [18796] [2040] -0100 1 -.names [12005] [17058] [18795] [18796] [2041] -111- 1 -11-1 1 -.names [11315] n_n3925 [4303] [2042] -111 1 -.names ppeaka_1_1_ [2391] [2392] [2043] -11- 1 -1-1 1 -.names ppeakp_1_1_ n_n3925 [4303] [2394] [2044] -1--1 1 -101- 1 -.names preset nrq4_14 [18795] [18796] [2045] -011- 1 -01-1 1 -.names preset [18285] [18415] [2049] -010 1 -.names preset piack_0_0_ [17739] [2050] -011 1 -.names preset piack_0_0_ [17700] [2051] -010 1 -.names [13175] [17240] [18795] [18796] [2055] -111- 1 -11-1 1 -.names [8630] [18423] [18795] [18796] [2057] -111- 1 -11-1 1 -.names [10025] [18397] [18795] [18796] [2058] -111- 1 -11-1 1 -.names [8240] [17279] [18795] [18796] [2059] -111- 1 -11-1 1 -.names ppeaks_0_0_ [4241] [18795] [18796] [2060] -111- 1 -11-1 1 -.names preset paddress_0_0_ [18795] [18796] [2063] -0100 1 -.names [12890] [17058] [18795] [18796] [2064] -111- 1 -11-1 1 -.names [11555] n_n3925 [4303] [2065] -111 1 -.names ppeaka_0_0_ [2391] [2392] [2066] -11- 1 -1-1 1 -.names ppeakp_0_0_ n_n3925 [4303] [2394] [2067] -1--1 1 -101- 1 -.names [17422] [18795] [18796] [2068] -11- 1 -1-1 1 -.names preset [17531] [18233] nrq7_2 [2069] -011- 1 -0-10 1 -.names preset ppeaki_1_1_ [17531] nrq7_2 [2070] -0101 1 -.names preset [18194] [4234] [4242] [2076] -0100 1 -.names preset ppeaka_11_11_ [4234] [2077] -011 1 -.names preset [17531] [18155] nrq7_2 [2080] -011- 1 -0-10 1 -.names preset ppeaki_0_0_ [17531] nrq7_2 [2081] -0101 1 -.names [18467] nen3_2 n_n3925 [19003] [2084] -1--1 1 --0-1 1 --101 1 -.names preset [18467] nen3_2 n_n3925 [2085] -0011 1 -.names preset [17531] [18090] nrq7_2 [2088] -011- 1 -0-10 1 -.names preset ppeaki_3_3_ [17531] nrq7_2 [2089] -0101 1 -.names [17032] [18467] nen3_2 n_n3925 [2092] -1011 1 -.names preset [17531] [18012] nrq7_2 [2100] -011- 1 -0-10 1 -.names preset ppeaki_2_2_ [17531] nrq7_2 [2101] -0101 1 -.names preset [17973] [4234] [4242] [2107] -0100 1 -.names preset ppeaka_12_12_ [4234] [2108] -011 1 -.names preset [17921] [4234] [4242] [2116] -0100 1 -.names preset ppeaka_10_10_ [4234] [2117] -011 1 -.names [18467] [4300] nen3_2 n_n3925 [2179] -0111 1 -.names preset [17778] [4234] [4242] [2184] -0100 1 -.names preset ppeaka_14_14_ [4234] [2185] -011 1 -.names preset [17765] [4234] [4242] [2187] -0100 1 -.names preset ppeaka_9_9_ [4234] [2188] -011 1 -.names [10985] [17240] [18795] [18796] [2193] -111- 1 -11-1 1 -.names [6080] [18423] [18795] [18796] [2195] -111- 1 -11-1 1 -.names [5480] [18397] [18795] [18796] [2196] -111- 1 -11-1 1 -.names [12650] [17279] [18795] [18796] [2197] -111- 1 -11-1 1 -.names ppeaks_14_14_ [4241] [18795] [18796] [2198] -111- 1 -11-1 1 -.names preset paddress_14_14_ [18795] [18796] [2201] -0100 1 -.names [14270] [17058] [18795] [18796] [2202] -111- 1 -11-1 1 -.names [12260] n_n3925 [4303] [2203] -111 1 -.names ppeaka_14_14_ [2391] [2392] [2204] -11- 1 -1-1 1 -.names ppeakp_14_14_ n_n3925 [4303] [2394] [2205] -1--1 1 -101- 1 -.names [6320] [17240] [18795] [18796] [2210] -111- 1 -11-1 1 -.names [6755] [18423] [18795] [18796] [2212] -111- 1 -11-1 1 -.names [8765] [18397] [18795] [18796] [2213] -111- 1 -11-1 1 -.names [12425] [17279] [18795] [18796] [2214] -111- 1 -11-1 1 -.names ppeaks_15_15_ [4241] [18795] [18796] [2215] -111- 1 -11-1 1 -.names preset paddress_15_15_ [18795] [18796] [2218] -0100 1 -.names [13880] [17058] [18795] [18796] [2219] -111- 1 -11-1 1 -.names [12470] n_n3925 [4303] [2220] -111 1 -.names ppeaka_15_15_ [2391] [2392] [2221] -11- 1 -1-1 1 -.names ppeakp_15_15_ n_n3925 [4303] [2394] [2222] -1--1 1 -101- 1 -.names [10415] [17240] [18795] [18796] [2231] -111- 1 -11-1 1 -.names [10010] [18423] [18795] [18796] [2233] -111- 1 -11-1 1 -.names [6860] [18397] [18795] [18796] [2234] -111- 1 -11-1 1 -.names [14660] [17279] [18795] [18796] [2235] -111- 1 -11-1 1 -.names ppeaks_12_12_ [4241] [18795] [18796] [2236] -111- 1 -11-1 1 -.names preset paddress_12_12_ [18795] [18796] [2239] -0100 1 -.names [15065] [17058] [18795] [18796] [2240] -111- 1 -11-1 1 -.names [12050] n_n3925 [4303] [2241] -111 1 -.names ppeaka_12_12_ [2391] [2392] [2242] -11- 1 -1-1 1 -.names ppeakp_12_12_ n_n3925 [4303] [2394] [2243] -1--1 1 -101- 1 -.names [18897] [18898] [18901] [18905] [2246] -0--1 1 --0-1 1 ---01 1 -.names [17986] [5528] [17599] [17600] [2255] -11-- 1 -1-11 1 -.names [10700] [17240] [18795] [18796] [2260] -111- 1 -11-1 1 -.names [9740] [18423] [18795] [18796] [2262] -111- 1 -11-1 1 -.names [4775] [18397] [18795] [18796] [2263] -111- 1 -11-1 1 -.names [14240] [17279] [18795] [18796] [2264] -111- 1 -11-1 1 -.names ppeaks_13_13_ [4241] [18795] [18796] [2265] -111- 1 -11-1 1 -.names preset paddress_13_13_ [18795] [18796] [2268] -0100 1 -.names [14690] [17058] [18795] [18796] [2269] -111- 1 -11-1 1 -.names [12170] n_n3925 [4303] [2270] -111 1 -.names ppeaka_13_13_ [2391] [2392] [2271] -11- 1 -1-1 1 -.names ppeakp_13_13_ n_n3925 [4303] [2394] [2272] -1--1 1 -101- 1 -.names preset [18636] nrq7_2 [2276] -001 1 -.names preset [17492] [4234] [4242] [2280] -0100 1 -.names preset ppeaka_13_13_ [4234] [2281] -011 1 -.names [9860] [17240] [18795] [18796] [2286] -111- 1 -11-1 1 -.names [9305] [18423] [18795] [18796] [2288] -111- 1 -11-1 1 -.names [9770] [18397] [18795] [18796] [2289] -111- 1 -11-1 1 -.names [13850] [17279] [18795] [18796] [2290] -111- 1 -11-1 1 -.names ppeaks_10_10_ [4241] [18795] [18796] [2291] -111- 1 -11-1 1 -.names preset paddress_10_10_ [18795] [18796] [2294] -0100 1 -.names [12665] [17058] [18795] [18796] [2295] -111- 1 -11-1 1 -.names [11795] n_n3925 [4303] [2296] -111 1 -.names ppeaka_10_10_ [2391] [2392] [2297] -11- 1 -1-1 1 -.names ppeakp_10_10_ n_n3925 [4303] [2394] [2298] -1--1 1 -101- 1 -.names [10130] [17240] [18795] [18796] [2303] -111- 1 -11-1 1 -.names [8645] [18423] [18795] [18796] [2305] -111- 1 -11-1 1 -.names [10595] [18397] [18795] [18796] [2306] -111- 1 -11-1 1 -.names [13490] [17279] [18795] [18796] [2307] -111- 1 -11-1 1 -.names ppeaks_11_11_ [4241] [18795] [18796] [2308] -111- 1 -11-1 1 -.names preset paddress_11_11_ [18795] [18796] [2311] -0100 1 -.names [12125] [17058] [18795] [18796] [2312] -111- 1 -11-1 1 -.names [11915] n_n3925 [4303] [2313] -111 1 -.names ppeaka_11_11_ [2391] [2392] [2314] -11- 1 -1-1 1 -.names ppeakp_11_11_ n_n3925 [4303] [2394] [2315] -1--1 1 -101- 1 -.names preset [17323] [4234] [4242] [2319] -0100 1 -.names preset ppeaka_2_2_ [4234] [2320] -011 1 -.names preset [17258] [4234] [4242] [2324] -0100 1 -.names preset ppeaka_1_1_ [4234] [2325] -011 1 -.names preset [17193] [4234] [4242] [2329] -0100 1 -.names preset ppeaka_4_4_ [4234] [2330] -011 1 -.names preset [17128] [4234] [4242] [2336] -0100 1 -.names preset ppeaka_3_3_ [4234] [2337] -011 1 -.names preset [17076] [4234] [4242] [2341] -0100 1 -.names preset ppeaka_15_15_ [4234] [2342] -011 1 -.names preset [17063] [4234] [4242] [2344] -0100 1 -.names preset ppeaka_6_6_ [4234] [2345] -011 1 -.names preset [16998] [4234] [4242] [2351] -0100 1 -.names preset ppeaka_5_5_ [4234] [2352] -011 1 -.names preset [16959] [4234] [4242] [2354] -0100 1 -.names preset ppeaka_8_8_ [4234] [2355] -011 1 -.names [9590] [17240] [18795] [18796] [2358] -111- 1 -11-1 1 -.names [7370] [18423] [18795] [18796] [2360] -111- 1 -11-1 1 -.names [10040] [18397] [18795] [18796] [2361] -111- 1 -11-1 1 -.names [15770] [17279] [18795] [18796] [2362] -111- 1 -11-1 1 -.names ppeaks_9_9_ [4241] [18795] [18796] [2363] -111- 1 -11-1 1 -.names preset paddress_9_9_ [18795] [18796] [2366] -0100 1 -.names [12440] [17058] [18795] [18796] [2367] -111- 1 -11-1 1 -.names [11570] n_n3925 [4303] [2368] -111 1 -.names ppeaka_9_9_ [2391] [2392] [2369] -11- 1 -1-1 1 -.names ppeakp_9_9_ n_n3925 [4303] [2394] [2370] -1--1 1 -101- 1 -.names preset [16907] [4234] [4242] [2374] -0100 1 -.names preset ppeaka_7_7_ [4234] [2375] -011 1 -.names [8915] [17240] [18795] [18796] [2378] -111- 1 -11-1 1 -.names [8000] [18423] [18795] [18796] [2380] -111- 1 -11-1 1 -.names [8750] [18397] [18795] [18796] [2381] -111- 1 -11-1 1 -.names [11225] [17279] [18795] [18796] [2382] -111- 1 -11-1 1 -.names ppeaks_8_8_ [4241] [18795] [18796] [2383] -111- 1 -11-1 1 -.names preset paddress_8_8_ [18795] [18796] [2386] -0100 1 -.names [13160] [17058] [18795] [18796] [2387] -111- 1 -11-1 1 -.names [11330] n_n3925 [4303] [2388] -111 1 -.names ppeaka_8_8_ [2391] [2392] [2389] -11- 1 -1-1 1 -.names ppeakp_8_8_ n_n3925 [4303] [2394] [2390] -1--1 1 -101- 1 -.names preset nrq14_3 [18795] [18796] [2391] -011- 1 -01-1 1 -.names [17175] [18795] [18796] [2392] -11- 1 -1-1 1 -.names [17110] [18795] [18796] [2394] -11- 1 -1-1 1 -.names preset [16085] nrq7_2 [17714] [2400] -010- 1 -01-0 1 -.names preset [16070] nrq7_2 [17712] [2402] -010- 1 -01-0 1 -.names preset [16055] [18103] [18168] [2404] -011- 1 -01-0 1 -.names [16025] [4280] [2408] -11 1 -.names preset [16010] nrq7_2 [17715] [2410] -010- 1 -01-0 1 -.names preset pdata_9_9_ nrq7_2 [17715] [2411] -0111 1 -.names preset [15995] nrq7_2 [17715] [2412] -010- 1 -01-0 1 -.names preset pdata_0_0_ nrq7_2 [17715] [2413] -0111 1 -.names preset [15980] nrq7_2 [17714] [2414] -010- 1 -01-0 1 -.names preset pdata_7_7_ nrq7_2 [17714] [2415] -0111 1 -.names preset [15965] nrq7_2 [17712] [2416] -010- 1 -01-0 1 -.names preset pdata_14_14_ nrq7_2 [17712] [2417] -0111 1 -.names preset [15920] [17102] [17154] [2423] -010- 1 -01-1 1 -.names preset [15905] [17102] [17154] [2425] -010- 1 -01-1 1 -.names [9860] [4199] [3754] n_n2772 [2428] -1111 1 -.names [10205] n_n2772 n_n3081 [4266] [2429] -1111 1 -.names [12665] [4199] [3750] n_n2772 [2430] -1111 1 -.names [13850] [4199] [3715] n_n2772 [2431] -1111 1 -.names [10400] [4199] [3740] n_n2772 [2432] -1111 1 -.names [6155] [4199] [3747] n_n2772 [2433] -1111 1 -.names [8135] [4199] [3744] n_n2772 [2434] -1111 1 -.names [14585] [4199] n_n2772 [3720] [2435] -1111 1 -.names [5450] [4199] [3711] n_n2772 [2436] -1111 1 -.names [8060] [4199] [3738] n_n2772 [2437] -1111 1 -.names [8810] [4199] [3718] n_n2772 [2438] -1111 1 -.names [12860] [4226] n_n2772 [2440] -111 1 -.names [4700] [4199] [3723] n_n2772 [2441] -1111 1 -.names ppeaks_10_10_ [17660] [17662] [2443] -11- 1 -1-1 1 -.names [15665] [4199] [3744] [2445] -111 1 -.names [15860] [4515] [17649] [17650] [2446] -11-- 1 -1-1- 1 -1--1 1 -.names [13130] n_n3925 [5513] [5514] [2447] -111- 1 -11-1 1 -.names [9980] [4199] [3744] [2449] -111 1 -.names [15845] [4515] [17649] [17650] [2450] -11-- 1 -1-1- 1 -1--1 1 -.names [9500] n_n3925 [5513] [5514] [2451] -111- 1 -11-1 1 -.names ppeaka_6_6_ [4199] n_n2344 [3784] [2452] -1111 1 -.names [8330] [4199] [4207] [2453] -111 1 -.names [5660] [4199] [3746] [2454] -111 1 -.names ppeakb_5_5_ [4199] [4215] [2455] -111 1 -.names [6560] [4199] [3727] [2456] -111 1 -.names [11465] [4199] [3715] [2457] -111 1 -.names [15590] [4199] [3723] [2458] -111 1 -.names [14105] [4199] n_n2344 [3770] [2459] -1111 1 -.names [7670] [4199] [3718] [2460] -111 1 -.names ppeaka_5_5_ [4199] n_n2344 [3775] [2461] -0111 1 -.names ppeakb_5_5_ [4199] n_n2344 [3775] [2462] -0111 1 -.names ppeakp_5_5_ [4226] [4199] n_n2333 [2463] -11-- 1 -1-11 1 -.names [14825] [4199] [3740] [2464] -111 1 -.names ppeaka_5_5_ [4199] [3744] [4515] [2465] -1--1 1 -111- 1 -.names [8315] [4199] [3746] n_n2772 [2466] -1111 1 -.names [14435] [4199] [3727] n_n2772 [2468] -1111 1 -.names [15140] [4199] n_n2772 [4207] [2469] -1111 1 -.names [12650] [4199] [3715] n_n2772 [2472] -1111 1 -.names [15575] [4199] [3740] n_n2772 [2473] -1111 1 -.names [6335] [4199] [3718] n_n2772 [2474] -1111 1 -.names [9080] [4199] [3723] n_n2772 [2476] -1111 1 -.names ppeaka_14_14_ [4199] [3744] [4515] [2479] -1--1 1 -111- 1 -.names ppeaka_7_7_ [4199] n_n2772 [4224] [2480] -1111 1 -.names [13340] [4199] [3747] n_n2772 [2481] -1111 1 -.names [14930] [4199] [3744] n_n2772 [2482] -1111 1 -.names [15980] [4199] n_n2772 [3720] [2483] -1111 1 -.names [5915] [4199] [3711] n_n2772 [2484] -1111 1 -.names [14450] [4199] [3738] n_n2772 [2485] -1111 1 -.names [5315] [4199] [3718] n_n2772 [2486] -1111 1 -.names [7055] [4226] n_n2772 [2488] -111 1 -.names [9095] [4199] [3723] n_n2772 [2489] -1111 1 -.names ppeakb_7_7_ [4199] [4211] [4515] [2491] -1--1 1 -111- 1 -.names preset [15785] [17791] [17843] [2492] -010- 1 -01-1 1 -.names preset [15725] nrq7_2 [17712] [2498] -010- 1 -01-0 1 -.names preset [15710] [18103] [18168] [2500] -011- 1 -01-0 1 -.names [4308] n_n2485 [19466] [19721] [2501] -1111 1 -1001 1 -1010 1 -1100 1 -.names [18176] n_n2479 [19495] [19743] [2503] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [15650] nrq7_2 [17715] [2508] -010- 1 -01-0 1 -.names preset pdata_1_1_ nrq7_2 [17715] [2509] -0111 1 -.names preset [15635] nrq7_2 [17714] [2510] -010- 1 -01-0 1 -.names preset pdata_6_6_ nrq7_2 [17714] [2511] -0111 1 -.names preset [15620] nrq7_2 [17712] [2512] -010- 1 -01-0 1 -.names preset pdata_15_15_ nrq7_2 [17712] [2513] -0111 1 -.names preset [15575] [17102] [17154] [2519] -010- 1 -01-1 1 -.names preset [15560] [17102] [17154] [2521] -010- 1 -01-1 1 -.names [13175] [4199] [3754] n_n2772 [2524] -1111 1 -.names [9935] n_n2772 n_n3081 [4266] [2525] -1111 1 -.names [12890] [4199] [3750] n_n2772 [2526] -1111 1 -.names [8240] [4199] [3715] n_n2772 [2527] -1111 1 -.names [10670] [4199] [3740] n_n2772 [2528] -1111 1 -.names [15380] [4199] [3747] n_n2772 [2529] -1111 1 -.names [7490] [4199] [3744] n_n2772 [2530] -1111 1 -.names [13400] [4199] n_n2772 [3720] [2531] -1111 1 -.names [6125] [4199] [3711] n_n2772 [2532] -1111 1 -.names [7415] [4199] [3738] n_n2772 [2533] -1111 1 -.names [9455] [4199] [3718] n_n2772 [2534] -1111 1 -.names [12605] [4226] n_n2772 [2536] -111 1 -.names [5390] [4199] [3723] n_n2772 [2537] -1111 1 -.names ppeaks_0_0_ [17660] [17662] [2539] -11- 1 -1-1 1 -.names [9710] [4199] [3744] [2541] -111 1 -.names [15515] [4515] [17649] [17650] [2542] -11-- 1 -1-1- 1 -1--1 1 -.names [13475] n_n3925 [5513] [5514] [2543] -111- 1 -11-1 1 -.names [15305] [4199] [3744] [2545] -111 1 -.names [15500] [4515] [17649] [17650] [2546] -11-- 1 -1-1- 1 -1--1 1 -.names [9800] n_n3925 [5513] [5514] [2547] -111- 1 -11-1 1 -.names ppeaka_5_5_ [4199] n_n2344 [3784] [2548] -1111 1 -.names [14765] [4199] [4207] [2549] -111 1 -.names [8975] [4199] [3746] [2550] -111 1 -.names ppeakb_4_4_ [4199] [4215] [2551] -111 1 -.names [14870] [4199] [3727] [2552] -111 1 -.names [5615] [4199] [3715] [2553] -111 1 -.names [13280] [4199] [3723] [2554] -111 1 -.names [14525] [4199] n_n2344 [3770] [2555] -1111 1 -.names [8300] [4199] [3718] [2556] -111 1 -.names ppeaka_4_4_ [4199] n_n2344 [3775] [2557] -0111 1 -.names ppeakb_4_4_ [4199] n_n2344 [3775] [2558] -0111 1 -.names ppeakp_4_4_ [4226] [4199] n_n2333 [2559] -11-- 1 -1-11 1 -.names [15905] [4199] [3740] [2560] -111 1 -.names ppeaka_4_4_ [4199] [3744] [4515] [2561] -1--1 1 -111- 1 -.names [13550] [4199] [4207] [2562] -111 1 -.names [6365] [4199] [3746] [2563] -111 1 -.names ppeakb_15_15_ [4199] [4215] [2564] -111 1 -.names [7205] [4199] [3727] [2565] -111 1 -.names [12425] [4199] [3715] [2566] -111 1 -.names [15950] [4199] [3723] [2567] -111 1 -.names [13730] [4199] n_n2344 [3770] [2568] -1111 1 -.names [7010] [4199] [3718] [2569] -111 1 -.names ppeaka_15_15_ [4199] n_n2344 [3775] [2570] -0111 1 -.names ppeakb_15_15_ [4199] n_n2344 [3775] [2571] -0111 1 -.names ppeakp_15_15_ [4226] [4199] n_n2333 [2572] -11-- 1 -1-11 1 -.names [15215] [4199] [3740] [2573] -111 1 -.names ppeaka_15_15_ [4199] [3744] [4515] [2574] -1--1 1 -111- 1 -.names ppeaka_6_6_ [4199] [4224] [2576] -111 1 -.names [7865] [4199] [3711] [2577] -111 1 -.names [6575] [4199] [3738] [2578] -111 1 -.names [15635] [4199] [3720] [2579] -111 1 -.names [7160] [4199] [3723] [2580] -111 1 -.names [4385] [4199] n_n2344 [3770] [2581] -1111 1 -.names [4610] [4199] [3718] [2582] -111 1 -.names [7745] [4199] n_n2344 [3775] [2583] -1111 1 -.names [10265] [4199] [3744] [2584] -111 1 -.names ppeakb_6_6_ [4199] [4211] [4515] [2585] -1--1 1 -111- 1 -.names [7685] n_n3925 [5513] [5514] [2586] -111- 1 -11-1 1 -.names preset [15440] [17791] [17843] [2587] -010- 1 -01-1 1 -.names preset [15410] [17427] [17648] [2592] -010- 1 -01-1 1 -.names preset [15395] [17427] [17648] [2594] -010- 1 -01-1 1 -.names preset [15380] nrq7_2 [17715] [2595] -010- 1 -01-0 1 -.names preset [15365] nrq7_2 [17714] [2597] -010- 1 -01-0 1 -.names [16928] n_n2479 [19495] [19743] [2598] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [15350] [18103] [18168] [2599] -011- 1 -01-0 1 -.names [18176] n_n2476 [19741] [19531] [2602] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [15290] nrq7_2 [17715] [2607] -010- 1 -01-0 1 -.names preset pdata_2_2_ nrq7_2 [17715] [2608] -0111 1 -.names preset [15275] nrq7_2 [17714] [2609] -010- 1 -01-0 1 -.names preset pdata_9_9_ nrq7_2 [17714] [2610] -0111 1 -.names preset [15260] nrq7_2 [17712] [2611] -010- 1 -01-0 1 -.names preset pdata_12_12_ nrq7_2 [17712] [2612] -0111 1 -.names preset [15245] [17167] [17362] [2614] -010- 1 -01-1 1 -.names preset [15215] [17102] [17154] [2618] -010- 1 -01-1 1 -.names preset [15200] [17102] [17154] [2620] -010- 1 -01-1 1 -.names ppeaka_15_15_ [5413] [17694] [2623] -11- 1 -1-1 1 -.names [11285] n_n3081 [4266] [2625] -111 1 -.names ppeakp_15_15_ [17696] [17698] [17703] [2626] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_15_15_ [4199] [3744] [2627] -111 1 -.names [8915] [4199] [3754] n_n2772 [2629] -1111 1 -.names [10775] n_n2772 n_n3081 [4266] [2630] -1111 1 -.names [13160] [4199] [3750] n_n2772 [2631] -1111 1 -.names [11225] [4199] [3715] n_n2772 [2632] -1111 1 -.names [7595] [4199] [3740] n_n2772 [2633] -1111 1 -.names [12590] [4199] [3747] n_n2772 [2634] -1111 1 -.names [9440] [4199] [3744] n_n2772 [2635] -1111 1 -.names [15365] [4199] n_n2772 [3720] [2636] -1111 1 -.names [6815] [4199] [3711] n_n2772 [2637] -1111 1 -.names [10865] [4199] [3738] n_n2772 [2638] -1111 1 -.names [7520] [4199] [3718] n_n2772 [2639] -1111 1 -.names [13460] [4226] n_n2772 [2641] -111 1 -.names [6095] [4199] [3723] n_n2772 [2642] -1111 1 -.names ppeaks_8_8_ [17660] [17662] [2644] -11- 1 -1-1 1 -.names [5975] [4199] [3744] [2646] -111 1 -.names [15140] [4515] [17649] [17650] [2647] -11-- 1 -1-1- 1 -1--1 1 -.names [10070] n_n3925 [5513] [5514] [2648] -111- 1 -11-1 1 -.names ppeaka_4_4_ [4199] n_n2344 [3784] [2649] -1111 1 -.names [15860] [4199] [4207] [2650] -111 1 -.names [9920] [4199] [3746] [2651] -111 1 -.names ppeakb_3_3_ [4199] [4215] [2652] -111 1 -.names [15245] [4199] [3727] [2653] -111 1 -.names [4910] [4199] [3715] [2654] -111 1 -.names [13625] [4199] [3723] [2655] -111 1 -.names [13355] [4199] n_n2344 [3770] [2656] -1111 1 -.names [8960] [4199] [3718] [2657] -111 1 -.names ppeaka_3_3_ [4199] n_n2344 [3775] [2658] -0111 1 -.names ppeakb_3_3_ [4199] n_n2344 [3775] [2659] -0111 1 -.names ppeakp_3_3_ [4226] [4199] n_n2333 [2660] -11-- 1 -1-11 1 -.names [15560] [4199] [3740] [2661] -111 1 -.names ppeaka_3_3_ [4199] [3744] [4515] [2662] -1--1 1 -111- 1 -.names [11510] [4199] [3746] n_n2772 [2663] -1111 1 -.names [7190] [4199] [3727] n_n2772 [2665] -1111 1 -.names [15845] [4199] n_n2772 [4207] [2666] -1111 1 -.names [14660] [4199] [3715] n_n2772 [2669] -1111 1 -.names [4415] [4199] [3740] n_n2772 [2670] -1111 1 -.names [4940] [4199] [3718] n_n2772 [2671] -1111 1 -.names [7775] [4199] [3723] n_n2772 [2673] -1111 1 -.names ppeaka_12_12_ [4199] [3744] [4515] [2676] -1--1 1 -111- 1 -.names ppeaka_9_9_ [4199] [4224] [2678] -111 1 -.names [4520] [4199] [3711] [2679] -111 1 -.names [7850] [4199] [3738] [2680] -111 1 -.names [15275] [4199] [3720] [2681] -111 1 -.names [14855] [4199] [3723] [2682] -111 1 -.names [15185] [4199] n_n2344 [3770] [2683] -1111 1 -.names [6680] [4199] [3718] [2684] -111 1 -.names [8390] [4199] n_n2344 [3775] [2685] -1111 1 -.names [5990] [4199] [3744] [2686] -111 1 -.names ppeakb_9_9_ [4199] [4211] [4515] [2687] -1--1 1 -111- 1 -.names [5720] n_n3925 [5513] [5514] [2688] -111- 1 -11-1 1 -.names preset [15080] [17791] [17843] [2689] -010- 1 -01-1 1 -.names preset [15050] [17427] [17648] [2694] -010- 1 -01-1 1 -.names preset [15035] [17427] [17648] [2696] -010- 1 -01-1 1 -.names preset [15020] nrq7_2 [17715] [2697] -010- 1 -01-0 1 -.names preset [15005] nrq7_2 [17714] [2699] -010- 1 -01-0 1 -.names [16928] n_n2480 [19737] [19520] [2700] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [14990] nrq7_2 [17712] [2701] -010- 1 -01-0 1 -.names [18501] n_n2474 [19514] [19733] [2702] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [14975] [18103] [18168] [2703] -011- 1 -01-0 1 -.names [4308] n_n2483 [19725] [19479] [2704] -1111 1 -1001 1 -1010 1 -1100 1 -.names [18176] n_n2477 [19735] [19504] [2706] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [14915] nrq7_2 [17715] [2709] -010- 1 -01-0 1 -.names preset pdata_3_3_ nrq7_2 [17715] [2710] -0111 1 -.names preset [14900] nrq7_2 [17714] [2711] -010- 1 -01-0 1 -.names preset pdata_8_8_ nrq7_2 [17714] [2712] -0111 1 -.names preset [14885] nrq7_2 [17712] [2713] -010- 1 -01-0 1 -.names preset pdata_13_13_ nrq7_2 [17712] [2714] -0111 1 -.names preset [14870] [17167] [17362] [2716] -010- 1 -01-1 1 -.names preset [14825] [17102] [17154] [2722] -010- 1 -01-1 1 -.names ppeaka_14_14_ [5413] [17694] [2725] -11- 1 -1-1 1 -.names [11525] n_n3081 [4266] [2727] -111 1 -.names ppeakp_14_14_ [17696] [17698] [17703] [2728] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_14_14_ [4199] [3744] [2729] -111 1 -.names [9590] [4199] [3754] n_n2772 [2731] -1111 1 -.names [11045] n_n2772 n_n3081 [4266] [2732] -1111 1 -.names [12440] [4199] [3750] n_n2772 [2733] -1111 1 -.names [15770] [4199] [3715] n_n2772 [2734] -1111 1 -.names [10685] [4199] [3740] n_n2772 [2735] -1111 1 -.names [5465] [4199] [3747] n_n2772 [2736] -1111 1 -.names [8780] [4199] [3744] n_n2772 [2737] -1111 1 -.names [14165] [4199] n_n2772 [3720] [2738] -1111 1 -.names [4745] [4199] [3711] n_n2772 [2739] -1111 1 -.names [11135] [4199] [3738] n_n2772 [2740] -1111 1 -.names [9470] [4199] [3718] n_n2772 [2741] -1111 1 -.names [13820] [4226] n_n2772 [2743] -111 1 -.names [5405] [4199] [3723] n_n2772 [2744] -1111 1 -.names ppeaks_9_9_ [17660] [17662] [2746] -11- 1 -1-1 1 -.names [5270] [4199] [3744] [2748] -111 1 -.names [14765] [4515] [17649] [17650] [2749] -11-- 1 -1-1- 1 -1--1 1 -.names [12875] n_n3925 [5513] [5514] [2750] -111- 1 -11-1 1 -.names ppeaka_3_3_ [4199] n_n2344 [3784] [2751] -1111 1 -.names [15515] [4199] [4207] [2752] -111 1 -.names [11720] [4199] [3746] [2753] -111 1 -.names ppeakb_2_2_ [4199] [4215] [2754] -111 1 -.names [7805] [4199] [3727] [2755] -111 1 -.names [6980] [4199] [3715] [2756] -111 1 -.names [14000] [4199] [3723] [2757] -111 1 -.names [13715] [4199] n_n2344 [3770] [2758] -1111 1 -.names [9635] [4199] [3718] [2759] -111 1 -.names ppeaka_2_2_ [4199] n_n2344 [3775] [2760] -0111 1 -.names ppeakb_2_2_ [4199] n_n2344 [3775] [2761] -0111 1 -.names ppeakp_2_2_ [4226] [4199] n_n2333 [2762] -11-- 1 -1-11 1 -.names [5105] [4199] [3740] [2763] -111 1 -.names ppeaka_2_2_ [4199] [3744] [4515] [2764] -1--1 1 -111- 1 -.names [10190] [4199] [3746] n_n2772 [2765] -1111 1 -.names ppeakb_13_13_ [4199] n_n2772 [4215] [2766] -1111 1 -.names [14015] [4199] [3727] n_n2772 [2767] -1111 1 -.names [15500] [4199] n_n2772 [4207] [2768] -1111 1 -.names [14240] [4199] [3715] n_n2772 [2771] -1111 1 -.names [15920] [4199] [3740] n_n2772 [2772] -1111 1 -.names [5645] [4199] [3718] n_n2772 [2773] -1111 1 -.names [8420] [4199] [3723] n_n2772 [2775] -1111 1 -.names ppeaka_13_13_ [4199] [3744] [4515] [2778] -1--1 1 -111- 1 -.names ppeaka_8_8_ [4199] [4224] [2780] -111 1 -.names [6605] [4199] [3711] [2781] -111 1 -.names [14030] [4199] [3738] [2782] -111 1 -.names [14900] [4199] [3720] [2783] -111 1 -.names [8435] [4199] [3723] [2784] -111 1 -.names [5810] [4199] n_n2344 [3770] [2785] -1111 1 -.names [6005] [4199] [3718] [2786] -111 1 -.names [9050] [4199] n_n2344 [3775] [2787] -1111 1 -.names [6665] [4199] [3744] [2788] -111 1 -.names ppeakb_8_8_ [4199] [4211] [4515] [2789] -1--1 1 -111- 1 -.names [6410] n_n3925 [5513] [5514] [2790] -111- 1 -11-1 1 -.names preset [14705] [17791] [17843] [2791] -010- 1 -01-1 1 -.names preset [14630] [17427] [17648] [2800] -010- 1 -01-1 1 -.names preset [14615] nrq4_2 [2802] -010 1 -.names preset [14600] nrq7_2 [17715] [2803] -010- 1 -01-0 1 -.names [17305] n_n2485 [19466] [19721] [2804] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [14585] nrq7_2 [17714] [2805] -010- 1 -01-0 1 -.names [16928] n_n2477 [19735] [19504] [2806] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [14570] nrq7_2 [17714] [2807] -010- 1 -01-0 1 -.names preset [14555] [18103] [18168] [2809] -011- 1 -01-0 1 -.names [4308] n_n2482 [19727] [19456] [2810] -1111 1 -1001 1 -1010 1 -1100 1 -.names [18176] n_n2474 [19514] [19733] [2812] -1111 1 -1001 1 -1010 1 -1100 1 -.names [18176] n_n2483 [19725] [19479] [2814] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [14510] [17310] [17388] [2816] -011- 1 -01-0 1 -.names preset [14495] nrq7_2 [17715] [2817] -010- 1 -01-0 1 -.names preset pdata_4_4_ nrq7_2 [17715] [2818] -0111 1 -.names preset [14480] nrq7_2 [17714] [2819] -010- 1 -01-0 1 -.names preset pdata_11_11_ nrq7_2 [17714] [2820] -0111 1 -.names preset [14465] nrq7_2 [17714] [2821] -010- 1 -01-0 1 -.names preset pdata_2_2_ nrq7_2 [17714] [2822] -0111 1 -.names preset [14450] [17284] [18376] [2823] -010- 1 -01-1 1 -.names preset [14435] [17167] [17362] [2826] -010- 1 -01-1 1 -.names preset [14405] [17102] [17154] [2830] -010- 1 -01-1 1 -.names preset [14375] [17453] [18246] [2834] -010- 1 -01-1 1 -.names preset [14360] [17453] [18246] [2836] -010- 1 -01-1 1 -.names ppeaka_4_4_ [5413] [17694] [2837] -11- 1 -1-1 1 -.names [15440] n_n3081 [4266] [2839] -111 1 -.names ppeakp_4_4_ [17696] [17698] [17703] [2840] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_4_4_ [4199] [3744] [2841] -111 1 -.names ppeaka_2_2_ [4199] n_n2344 [3784] [2843] -1111 1 -.names [5030] [4199] [4207] [2844] -111 1 -.names [11495] [4199] [3746] [2845] -111 1 -.names ppeakb_1_1_ [4199] [4215] [2846] -111 1 -.names [7175] [4199] [3727] [2847] -111 1 -.names [6305] [4199] [3715] [2848] -111 1 -.names [14420] [4199] [3723] [2849] -111 1 -.names [15680] [4199] n_n2344 [3770] [2850] -1111 1 -.names [4925] [4199] [3718] [2851] -111 1 -.names ppeaka_1_1_ [4199] n_n2344 [3775] [2852] -0111 1 -.names ppeakb_1_1_ [4199] n_n2344 [3775] [2853] -0111 1 -.names ppeakp_1_1_ [4226] [4199] n_n2333 [2854] -11-- 1 -1-11 1 -.names [4400] [4199] [3740] [2855] -111 1 -.names ppeaka_1_1_ [4199] [3744] [4515] [2856] -1--1 1 -111- 1 -.names ppeaka_11_11_ [4199] n_n2344 [3784] [2857] -1111 1 -.names [5015] [4199] [4207] [2858] -111 1 -.names [11015] [4199] [3746] [2859] -111 1 -.names ppeakb_10_10_ [4199] [4215] [2860] -111 1 -.names [8465] [4199] [3727] [2861] -111 1 -.names [13850] [4199] [3715] [2862] -111 1 -.names [6515] [4199] [3723] [2863] -111 1 -.names [14960] [4199] n_n2344 [3770] [2864] -1111 1 -.names [11705] [4199] [3718] [2865] -111 1 -.names ppeaka_10_10_ [4199] n_n2344 [3775] [2866] -0111 1 -.names ppeakb_10_10_ [4199] n_n2344 [3775] [2867] -0111 1 -.names ppeakp_10_10_ [4226] [4199] n_n2333 [2868] -11-- 1 -1-11 1 -.names [13610] [4199] [3740] [2869] -111 1 -.names ppeaka_10_10_ [4199] [3744] [4515] [2870] -1--1 1 -111- 1 -.names ppeaka_3_3_ [4199] [4224] [2872] -111 1 -.names [8510] [4199] [3711] [2873] -111 1 -.names [4490] [4199] [3738] [2874] -111 1 -.names [14045] [4199] [3720] [2875] -111 1 -.names [6530] [4199] [3723] [2876] -111 1 -.names [7760] [4199] n_n2344 [3770] [2877] -1111 1 -.names [7940] [4199] [3718] [2878] -111 1 -.names [13220] [4199] n_n2344 [3775] [2879] -1111 1 -.names [9215] [4199] [3744] [2880] -111 1 -.names ppeakb_3_3_ [4199] [4211] [4515] [2881] -1--1 1 -111- 1 -.names [15860] n_n3925 [5513] [5514] [2882] -111- 1 -11-1 1 -.names preset [14285] [17791] [17843] [2883] -010- 1 -01-1 1 -.names preset [14225] [17999] [18077] [2892] -011- 1 -01-0 1 -.names preset [14210] [17427] [17648] [2894] -010- 1 -01-1 1 -.names preset [14180] nrq7_2 [17715] [2895] -010- 1 -01-0 1 -.names preset [14165] nrq7_2 [17714] [2897] -010- 1 -01-0 1 -.names preset [14150] nrq7_2 [17714] [2899] -010- 1 -01-0 1 -.names [16928] n_n2485 [19466] [19721] [2900] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [14135] [18103] [18168] [2901] -011- 1 -01-0 1 -.names [18176] n_n2482 [19727] [19456] [2906] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [14090] [17310] [17388] [2908] -011- 1 -01-0 1 -.names preset [14075] nrq7_2 [17715] [2909] -010- 1 -01-0 1 -.names preset pdata_5_5_ nrq7_2 [17715] [2910] -0111 1 -.names preset [14060] nrq7_2 [17714] [2911] -010- 1 -01-0 1 -.names preset pdata_10_10_ nrq7_2 [17714] [2912] -0111 1 -.names preset [14045] nrq7_2 [17714] [2913] -010- 1 -01-0 1 -.names preset pdata_3_3_ nrq7_2 [17714] [2914] -0111 1 -.names preset [14030] [17284] [18376] [2915] -010- 1 -01-1 1 -.names preset [14015] [17167] [17362] [2918] -010- 1 -01-1 1 -.names preset [13985] [17102] [17154] [2922] -010- 1 -01-1 1 -.names preset [13970] [17102] [17154] [2924] -010- 1 -01-1 1 -.names preset [13955] [17453] [18246] [2926] -010- 1 -01-1 1 -.names ppeaka_5_5_ [5413] [17694] [2927] -11- 1 -1-1 1 -.names [15080] n_n3081 [4266] [2929] -111 1 -.names ppeakp_5_5_ [17696] [17698] [17703] [2930] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_5_5_ [4199] [3744] [2931] -111 1 -.names ppeaka_1_1_ [4199] n_n2344 [3784] [2933] -1111 1 -.names [4310] [4199] [4207] [2934] -111 1 -.names [11255] [4199] [3746] [2935] -111 1 -.names ppeakb_0_0_ [4199] [4215] [2936] -111 1 -.names [9110] [4199] [3727] [2937] -111 1 -.names [8240] [4199] [3715] [2938] -111 1 -.names [14840] [4199] [3723] [2939] -111 1 -.names [16025] [4199] n_n2344 [3770] [2940] -1111 1 -.names [11480] [4199] [3718] [2941] -111 1 -.names ppeaka_0_0_ [4199] n_n2344 [3775] [2942] -0111 1 -.names ppeakb_0_0_ [4199] n_n2344 [3775] [2943] -0111 1 -.names ppeakp_0_0_ [4226] [4199] n_n2333 [2944] -11-- 1 -1-11 1 -.names [13970] [4199] [3740] [2945] -111 1 -.names ppeaka_0_0_ [4199] [3744] [4515] [2946] -1--1 1 -111- 1 -.names [11735] [4199] [3746] n_n2772 [2949] -1111 1 -.names ppeakb_11_11_ [4199] n_n2772 [4215] [2950] -1111 1 -.names [7820] [4199] [3727] n_n2772 [2951] -1111 1 -.names [4295] [4199] n_n2772 [4207] [2952] -1111 1 -.names [13490] [4199] [3715] n_n2772 [2955] -1111 1 -.names [5120] [4199] [3740] n_n2772 [2956] -1111 1 -.names [9650] [4199] [3718] n_n2772 [2957] -1111 1 -.names [7145] [4199] [3723] n_n2772 [2959] -1111 1 -.names ppeaka_11_11_ [4199] [3744] [4515] [2962] -1--1 1 -111- 1 -.names preset [13895] [17791] [17843] [2963] -010- 1 -01-1 1 -.names [13880] [4316] [2966] -11 1 -.names preset [13835] [17999] [18077] [2972] -011- 1 -01-0 1 -.names preset [13820] [17427] [17648] [2974] -010- 1 -01-1 1 -.names preset [13790] nrq7_2 [17715] [2977] -010- 1 -01-0 1 -.names [17305] n_n2483 [19725] [19479] [2978] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [13775] nrq7_2 [17714] [2979] -010- 1 -01-0 1 -.names preset [13745] [18103] [18168] [2981] -011- 1 -01-0 1 -.names [4308] n_n2480 [19737] [19520] [2982] -1111 1 -1001 1 -1010 1 -1100 1 -.names [18176] n_n2485 [19466] [19721] [2986] -1111 1 -1001 1 -1010 1 -1100 1 -.names [17461] n_n2482 [19727] [19456] [2988] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [13685] nrq7_2 [17715] [2989] -010- 1 -01-0 1 -.names preset pdata_6_6_ nrq7_2 [17715] [2990] -0111 1 -.names preset [13670] nrq7_2 [17714] [2991] -010- 1 -01-0 1 -.names preset pdata_13_13_ nrq7_2 [17714] [2992] -0111 1 -.names preset [13655] nrq7_2 [17714] [2993] -010- 1 -01-0 1 -.names preset pdata_0_0_ nrq7_2 [17714] [2994] -0111 1 -.names preset [13640] nrq7_2 [17712] [2995] -010- 1 -01-0 1 -.names preset pdata_2_2_ nrq7_2 [17712] [2996] -0111 1 -.names preset [13610] [17102] [17154] [3000] -010- 1 -01-1 1 -.names preset [13580] [17453] [18246] [3004] -010- 1 -01-1 1 -.names ppeaka_6_6_ [5413] [17694] [3005] -11- 1 -1-1 1 -.names [14705] n_n3081 [4266] [3007] -111 1 -.names ppeakp_6_6_ [17696] [17698] [17703] [3008] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_6_6_ [4199] [3744] [3009] -111 1 -.names [6650] [4199] [3744] [3012] -111 1 -.names [13550] [4515] [17649] [17650] [3013] -11-- 1 -1-1- 1 -1--1 1 -.names [10355] n_n3925 [5513] [5514] [3014] -111- 1 -11-1 1 -.names ppeaka_5_5_ [4199] n_n2772 [4224] [3015] -1111 1 -.names [14075] [4199] [3747] n_n2772 [3016] -1111 1 -.names [7910] [4199] [3744] n_n2772 [3017] -1111 1 -.names [5240] [4199] n_n2772 [3720] [3018] -1111 1 -.names [7235] [4199] [3711] n_n2772 [3019] -1111 1 -.names [5885] [4199] [3738] n_n2772 [3020] -1111 1 -.names [9245] [4199] [3718] n_n2772 [3021] -1111 1 -.names [8330] [4226] n_n2772 [3023] -111 1 -.names [7790] [4199] [3723] n_n2772 [3024] -1111 1 -.names ppeakb_5_5_ [4199] [4211] [4515] [3026] -1--1 1 -111- 1 -.names preset [13475] [17999] [18077] [3032] -011- 1 -01-0 1 -.names preset [13460] [17427] [17648] [3034] -010- 1 -01-1 1 -.names preset [13430] nrq7_2 [17715] [3037] -010- 1 -01-0 1 -.names [17305] n_n2482 [19727] [19456] [3038] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [13415] nrq7_2 [17714] [3039] -010- 1 -01-0 1 -.names [16928] n_n2476 [19741] [19531] [3040] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [13400] nrq7_2 [17714] [3041] -010- 1 -01-0 1 -.names preset [13385] [18103] [18168] [3043] -011- 1 -01-0 1 -.names [4308] n_n2479 [19495] [19743] [3044] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [13340] nrq7_2 [17715] [3049] -010- 1 -01-0 1 -.names preset pdata_7_7_ nrq7_2 [17715] [3050] -0111 1 -.names preset [13325] nrq7_2 [17714] [3051] -010- 1 -01-0 1 -.names preset pdata_12_12_ nrq7_2 [17714] [3052] -0111 1 -.names preset [13310] nrq7_2 [17714] [3053] -010- 1 -01-0 1 -.names preset pdata_1_1_ nrq7_2 [17714] [3054] -0111 1 -.names preset [13295] nrq7_2 [17712] [3055] -010- 1 -01-0 1 -.names preset pdata_1_1_ nrq7_2 [17712] [3056] -0111 1 -.names preset [13265] [17102] [17154] [3060] -010- 1 -01-1 1 -.names preset [13235] [17453] [18246] [3064] -010- 1 -01-1 1 -.names preset [13220] [17453] [18246] [3066] -010- 1 -01-1 1 -.names [11270] [4199] [3746] n_n2772 [3067] -1111 1 -.names [9125] [4199] [3727] n_n2772 [3069] -1111 1 -.names [5720] [4199] n_n2772 [4207] [3070] -1111 1 -.names [15770] [4199] [3715] n_n2772 [3073] -1111 1 -.names [13265] [4199] [3740] n_n2772 [3074] -1111 1 -.names [9905] [4199] [3718] n_n2772 [3075] -1111 1 -.names [5825] [4199] [3723] n_n2772 [3077] -1111 1 -.names ppeaka_9_9_ [4199] [3744] [4515] [3080] -1--1 1 -111- 1 -.names ppeaka_4_4_ [4199] n_n2772 [4224] [3081] -1111 1 -.names [14495] [4199] [3747] n_n2772 [3082] -1111 1 -.names [7280] [4199] [3744] n_n2772 [3083] -1111 1 -.names [12545] [4199] n_n2772 [3720] [3084] -1111 1 -.names [9170] [4199] [3711] n_n2772 [3085] -1111 1 -.names [5195] [4199] [3738] n_n2772 [3086] -1111 1 -.names [8585] [4199] [3718] n_n2772 [3087] -1111 1 -.names [14765] [4226] n_n2772 [3089] -111 1 -.names [5840] [4199] [3723] n_n2772 [3090] -1111 1 -.names ppeakb_4_4_ [4199] [4211] [4515] [3092] -1--1 1 -111- 1 -.names preset [13130] [17999] [18077] [3098] -011- 1 -01-0 1 -.names preset [13115] [17427] [17648] [3100] -010- 1 -01-1 1 -.names preset [13100] [17427] [17648] [3102] -010- 1 -01-1 1 -.names preset [13085] nrq7_2 [17715] [3103] -010- 1 -01-0 1 -.names preset [13070] nrq7_2 [17714] [3105] -010- 1 -01-0 1 -.names preset [13055] nrq7_2 [17714] [3107] -010- 1 -01-0 1 -.names [16928] n_n2482 [19727] [19456] [3108] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [13040] [18103] [18168] [3109] -011- 1 -01-0 1 -.names preset [13025] [18103] [18168] [3111] -011- 1 -01-0 1 -.names preset [13010] nrq7_2 [17715] [3113] -010- 1 -01-0 1 -.names preset pdata_8_8_ nrq7_2 [17715] [3114] -0111 1 -.names preset ppeaki_1_1_ n_n2772 [5522] [3115] -010- 1 -01-1 1 -.names [10805] [4202] [4266] [5514] [3116] -1--1 1 -101- 1 -.names preset ppeaki_10_10_ n_n2772 [5522] [3120] -010- 1 -01-1 1 -.names [12935] [4202] [4266] [5514] [3121] -1--1 1 -101- 1 -.names preset [12935] [17570] [17635] [3124] -010- 1 -01-1 1 -.names preset [12875] [17999] [18077] [3132] -011- 1 -01-0 1 -.names preset [12860] [17427] [17648] [3134] -010- 1 -01-1 1 -.names preset [12845] [17427] [17648] [3136] -010- 1 -01-1 1 -.names preset [12830] nrq7_2 [17715] [3137] -010- 1 -01-0 1 -.names [17305] n_n2480 [19737] [19520] [3138] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [12815] nrq7_2 [17714] [3139] -010- 1 -01-0 1 -.names [16928] n_n2474 [19514] [19733] [3140] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [12800] [18103] [18168] [3141] -011- 1 -01-0 1 -.names [4308] n_n2477 [19735] [19504] [3142] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [12770] nrq7_2 [17714] [3143] -010- 1 -01-0 1 -.names preset pdata_14_14_ nrq7_2 [17714] [3144] -0111 1 -.names preset ppeaki_0_0_ n_n2772 [5522] [3145] -010- 1 -01-1 1 -.names [12695] [4202] [4266] [5514] [3146] -1--1 1 -101- 1 -.names preset ppeaki_11_11_ n_n2772 [5522] [3150] -010- 1 -01-1 1 -.names [11600] [4202] [4266] [5514] [3151] -1--1 1 -101- 1 -.names preset [12695] [17570] [17635] [3154] -010- 1 -01-1 1 -.names preset [12635] [17999] [18077] [3162] -011- 1 -01-0 1 -.names preset [12620] [17427] [17648] [3164] -010- 1 -01-1 1 -.names preset [12605] [17427] [17648] [3166] -010- 1 -01-1 1 -.names preset [12590] nrq7_2 [17715] [3167] -010- 1 -01-0 1 -.names [17305] n_n2479 [19495] [19743] [3168] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [12575] nrq7_2 [17714] [3169] -010- 1 -01-0 1 -.names preset [12545] nrq7_2 [17714] [3173] -010- 1 -01-0 1 -.names preset pdata_4_4_ nrq7_2 [17714] [3174] -0111 1 -.names preset ppeaki_3_3_ n_n2772 [5522] [3175] -010- 1 -01-1 1 -.names [11345] [4202] [4266] [5514] [3176] -1--1 1 -101- 1 -.names preset ppeaki_12_12_ n_n2772 [5522] [3180] -010- 1 -01-1 1 -.names preset [12485] [17570] [17635] [3183] -010- 1 -01-1 1 -.names preset [12470] [18142] [18220] [3185] -011- 1 -01-0 1 -.names [12425] [4331] [3191] -11 1 -.names preset [12410] [17999] [18077] [3193] -011- 1 -01-0 1 -.names preset [12395] [17427] [17648] [3195] -010- 1 -01-1 1 -.names preset [12380] [17427] [17648] [3197] -010- 1 -01-1 1 -.names preset [12365] nrq7_2 [17714] [3198] -010- 1 -01-0 1 -.names preset [12350] nrq7_2 [17714] [3200] -010- 1 -01-0 1 -.names [16928] n_n2483 [19725] [19479] [3201] -1111 1 -1001 1 -1010 1 -1100 1 -.names [18176] n_n2480 [19737] [19520] [3203] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset ppeaki_2_2_ n_n2772 [5522] [3204] -010- 1 -01-1 1 -.names [11585] [4202] [4266] [5514] [3205] -1--1 1 -101- 1 -.names preset ppeaki_13_13_ n_n2772 [5522] [3209] -010- 1 -01-1 1 -.names preset [12275] [17570] [17635] [3212] -010- 1 -01-1 1 -.names preset [12260] [18142] [18220] [3214] -011- 1 -01-0 1 -.names ppeaka_13_13_ [4199] [4224] [3218] -111 1 -.names [14885] [4199] [3711] [3219] -111 1 -.names [5210] [4199] [3738] [3220] -111 1 -.names [13670] [4199] [3720] [3221] -111 1 -.names [4460] [4199] [3723] [3222] -111 1 -.names [13595] [4199] n_n2344 [3770] [3223] -1111 1 -.names [7325] [4199] [3718] [3224] -111 1 -.names [14375] [4199] n_n2344 [3775] [3225] -1111 1 -.names [8570] [4199] [3744] [3226] -111 1 -.names ppeakb_13_13_ [4199] [4211] [4515] [3227] -1--1 1 -111- 1 -.names [15500] n_n3925 [5513] [5514] [3228] -111- 1 -11-1 1 -.names preset [12200] [17570] [17635] [3230] -010- 1 -01-1 1 -.names preset [12185] [17570] [17635] [3232] -010- 1 -01-1 1 -.names preset [12170] [18142] [18220] [3234] -011- 1 -01-0 1 -.names preset [12155] [17414] [17505] [3236] -010- 1 -01-1 1 -.names preset [12140] [17791] [17843] [3237] -010- 1 -01-1 1 -.names preset ppeaki_7_7_ n_n2772 [5522] [3241] -010- 1 -01-1 1 -.names [12065] [4202] [4266] [5514] [3242] -1--1 1 -101- 1 -.names preset [12080] [17570] [17635] [3247] -010- 1 -01-1 1 -.names preset [12065] [17570] [17635] [3249] -010- 1 -01-1 1 -.names preset [12050] [18142] [18220] [3251] -011- 1 -01-0 1 -.names preset [12035] [17414] [17505] [3253] -010- 1 -01-1 1 -.names preset [12020] [17791] [17843] [3254] -010- 1 -01-1 1 -.names ppeaka_15_15_ [4199] [4224] [3259] -111 1 -.names [15620] [4199] [3711] [3260] -111 1 -.names [6590] [4199] [3738] [3261] -111 1 -.names [4535] [4199] [3720] [3262] -111 1 -.names [8450] [4199] [3723] [3263] -111 1 -.names [14390] [4199] n_n2344 [3770] [3264] -1111 1 -.names [8600] [4199] [3718] [3265] -111 1 -.names [13580] [4199] n_n2344 [3775] [3266] -1111 1 -.names [7295] [4199] [3744] [3267] -111 1 -.names ppeakb_15_15_ [4199] [4211] [4515] [3268] -1--1 1 -111- 1 -.names [13550] n_n3925 [5513] [5514] [3269] -111- 1 -11-1 1 -.names preset ppeaki_8_8_ n_n2772 [5522] [3270] -010- 1 -01-1 1 -.names [12485] [4202] [4266] [5514] [3271] -1--1 1 -101- 1 -.names preset [11930] [17570] [17635] [3274] -010- 1 -01-1 1 -.names preset [11915] [18142] [18220] [3276] -011- 1 -01-0 1 -.names preset [11900] [17414] [17505] [3278] -010- 1 -01-1 1 -.names preset [11885] [17414] [17505] [3280] -010- 1 -01-1 1 -.names ppeaka_14_14_ [4199] n_n2772 [4224] [3281] -1111 1 -.names [7250] [4199] [3747] n_n2772 [3282] -1111 1 -.names [7925] [4199] [3744] n_n2772 [3283] -1111 1 -.names [12770] [4199] n_n2772 [3720] [3284] -1111 1 -.names [15965] [4199] [3711] n_n2772 [3285] -1111 1 -.names [4505] [4199] [3738] n_n2772 [3286] -1111 1 -.names [9260] [4199] [3718] n_n2772 [3287] -1111 1 -.names [15140] [4226] n_n2772 [3289] -111 1 -.names [5165] [4199] [3723] n_n2772 [3290] -1111 1 -.names ppeakb_14_14_ [4199] [4211] [4515] [3292] -1--1 1 -111- 1 -.names preset ppeaki_9_9_ n_n2772 [5522] [3293] -010- 1 -01-1 1 -.names [12275] [4202] [4266] [5514] [3294] -1--1 1 -101- 1 -.names preset [11810] [17570] [17635] [3297] -010- 1 -01-1 1 -.names preset [11795] [18142] [18220] [3299] -011- 1 -01-0 1 -.names preset [11780] [17414] [17505] [3301] -010- 1 -01-1 1 -.names preset [11765] [17414] [17505] [3303] -010- 1 -01-1 1 -.names preset [11750] [17791] [17843] [3304] -010- 1 -01-1 1 -.names preset [11675] [17037] [18025] [3315] -011- 1 -01-0 1 -.names preset [11660] [17037] [18025] [3317] -011- 1 -01-0 1 -.names preset [11615] nrq7_2 [17712] [3322] -010- 1 -01-0 1 -.names preset [11600] [17570] [17635] [3325] -010- 1 -01-1 1 -.names preset [11585] [17570] [17635] [3327] -010- 1 -01-1 1 -.names preset [11570] [18142] [18220] [3329] -011- 1 -01-0 1 -.names preset [11555] [18142] [18220] [3331] -011- 1 -01-0 1 -.names preset [11540] [17414] [17505] [3333] -010- 1 -01-1 1 -.names preset [11525] [17791] [17843] [3334] -010- 1 -01-1 1 -.names preset [11450] [17037] [18025] [3345] -011- 1 -01-0 1 -.names preset [11435] [17037] [18025] [3347] -011- 1 -01-0 1 -.names [4278] n_n2480 [19737] [19520] [3350] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [11390] nrq7_2 [17712] [3352] -010- 1 -01-0 1 -.names [18501] n_n2476 [19741] [19531] [3353] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [11345] [17570] [17635] [3357] -010- 1 -01-1 1 -.names preset [11330] [18142] [18220] [3359] -011- 1 -01-0 1 -.names preset [11315] [18142] [18220] [3361] -011- 1 -01-0 1 -.names preset [11300] [17414] [17505] [3363] -010- 1 -01-1 1 -.names preset [11285] [17791] [17843] [3364] -010- 1 -01-1 1 -.names preset [11240] [17180] [17232] [3370] -010- 1 -01-1 1 -.names preset [11210] [17037] [18025] [3375] -011- 1 -01-0 1 -.names preset [11195] [17037] [18025] [3377] -011- 1 -01-0 1 -.names preset [11150] nrq7_2 [17712] [3382] -010- 1 -01-0 1 -.names [17461] n_n2483 [19725] [19479] [3387] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [11090] [17570] [17635] [3389] -010- 1 -01-1 1 -.names preset [11075] [18142] [18220] [3391] -011- 1 -01-0 1 -.names preset [11060] [18142] [18220] [3393] -011- 1 -01-0 1 -.names preset [11045] [17414] [17505] [3395] -010- 1 -01-1 1 -.names preset [11030] [17791] [17843] [3396] -010- 1 -01-1 1 -.names preset [10955] [17037] [18025] [3405] -011- 1 -01-0 1 -.names preset [10940] [17037] [18025] [3407] -011- 1 -01-0 1 -.names [4278] n_n2482 [19727] [19456] [3410] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [10880] nrq7_2 [17712] [3412] -010- 1 -01-0 1 -.names [18501] n_n2485 [19466] [19721] [3413] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4381] n_n2479 [19495] [19743] [3414] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [10850] [17310] [17388] [3417] -011- 1 -01-0 1 -.names preset [10820] [17570] [17635] [3419] -010- 1 -01-1 1 -.names preset [10805] [17570] [17635] [3421] -010- 1 -01-1 1 -.names preset [10790] [18142] [18220] [3423] -011- 1 -01-0 1 -.names preset [10775] [17414] [17505] [3425] -010- 1 -01-1 1 -.names preset [10760] [17791] [17843] [3426] -010- 1 -01-1 1 -.names preset [10730] [17180] [17232] [3430] -010- 1 -01-1 1 -.names preset [10715] [17180] [17232] [3432] -010- 1 -01-1 1 -.names preset [10655] [17635] [17986] [3441] -010- 1 -01-1 1 -.names preset [10625] [18311] [18506] [3443] -011- 1 -01-0 1 -.names preset [10610] [18311] [18506] [3445] -011- 1 -01-0 1 -.names [4245] n_n2476 [19741] [19531] [3447] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [10580] [18285] [18363] [3448] -010- 1 -01-1 1 -.names preset [10565] [18285] [18363] [3450] -010- 1 -01-1 1 -.names preset [10550] [17310] [17388] [3453] -011- 1 -01-0 1 -.names preset ppeaki_5_5_ n_n2772 [5522] [3454] -010- 1 -01-1 1 -.names [11810] [4202] [4266] [5514] [3455] -1--1 1 -101- 1 -.names preset ppeaki_14_14_ n_n2772 [5522] [3459] -010- 1 -01-1 1 -.names preset [10505] [18142] [18220] [3462] -011- 1 -01-0 1 -.names preset [10490] [17414] [17505] [3464] -010- 1 -01-1 1 -.names preset [10475] [17414] [17505] [3466] -010- 1 -01-1 1 -.names preset [10445] [17180] [17232] [3469] -010- 1 -01-1 1 -.names preset [10430] [17180] [17232] [3471] -010- 1 -01-1 1 -.names preset [10370] [17635] [17986] [3478] -010- 1 -01-1 1 -.names preset [10355] [17999] [18077] [3480] -011- 1 -01-0 1 -.names [4377] n_n2474 [19514] [19733] [3481] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [10340] [18311] [18506] [3482] -011- 1 -01-0 1 -.names [4377] n_n2485 [19466] [19721] [3483] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [10325] [18311] [18506] [3484] -011- 1 -01-0 1 -.names preset [10280] [18285] [18363] [3487] -010- 1 -01-1 1 -.names [4306] n_n2482 [19727] [19456] [3488] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset ppeaki_4_4_ n_n2772 [5522] [3491] -010- 1 -01-1 1 -.names [11930] [4202] [4266] [5514] [3492] -1--1 1 -101- 1 -.names preset ppeaki_15_15_ n_n2772 [5522] [3496] -010- 1 -01-1 1 -.names preset [10220] [18142] [18220] [3499] -011- 1 -01-0 1 -.names preset [10205] [17414] [17505] [3501] -010- 1 -01-1 1 -.names preset [10145] [17180] [17232] [3506] -010- 1 -01-1 1 -.names preset [10085] [17635] [17986] [3515] -010- 1 -01-1 1 -.names preset [10070] [17999] [18077] [3517] -011- 1 -01-0 1 -.names preset [10055] [18311] [18506] [3519] -011- 1 -01-0 1 -.names [10025] [4252] [3522] -11 1 -.names preset [9950] [18142] [18220] [3531] -011- 1 -01-0 1 -.names preset [9935] [17414] [17505] [3533] -010- 1 -01-1 1 -.names preset [9890] [17180] [17232] [3538] -010- 1 -01-1 1 -.names preset [9875] [17180] [17232] [3540] -010- 1 -01-1 1 -.names preset [9815] [17635] [17986] [3549] -010- 1 -01-1 1 -.names preset [9800] [17999] [18077] [3551] -011- 1 -01-0 1 -.names [4377] n_n2483 [19725] [19479] [3552] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [9785] [18311] [18506] [3553] -011- 1 -01-0 1 -.names [4245] n_n2477 [19735] [19504] [3555] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4243] n_n2474 [19514] [19733] [3557] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4243] n_n2485 [19466] [19721] [3559] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset ppeaki_6_6_ n_n2772 [5522] [3562] -010- 1 -01-1 1 -.names [12185] [4202] [4266] [5514] [3563] -1--1 1 -101- 1 -.names preset [9680] [17414] [17505] [3568] -010- 1 -01-1 1 -.names preset [9665] [17414] [17505] [3570] -010- 1 -01-1 1 -.names preset [9620] [17180] [17232] [3575] -010- 1 -01-1 1 -.names preset [9605] [17180] [17232] [3577] -010- 1 -01-1 1 -.names preset [9575] [17037] [18025] [3582] -011- 1 -01-0 1 -.names preset [9530] [17635] [17986] [3588] -010- 1 -01-1 1 -.names preset [9515] [17635] [17986] [3590] -010- 1 -01-1 1 -.names preset [9500] [17999] [18077] [3592] -011- 1 -01-0 1 -.names [9455] [4277] [3598] -11 1 -.names [4377] n_n2479 [19495] [19743] [3599] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [9440] [18311] [18506] [3600] -011- 1 -01-0 1 -.names [4245] n_n2480 [19737] [19520] [3602] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [9395] nrq7_2 [17715] [3603] -010- 1 -01-0 1 -.names preset [9380] nrq7_2 [17712] [3605] -010- 1 -01-0 1 -.names [18501] n_n2483 [19725] [19479] [3606] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [9335] [18285] [18363] [3611] -010- 1 -01-1 1 -.names [4306] n_n2476 [19741] [19531] [3612] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [9320] [18285] [18363] [3613] -010- 1 -01-1 1 -.names [4306] n_n2485 [19466] [19721] [3614] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4243] n_n2477 [19735] [19504] [3616] -1111 1 -1001 1 -1010 1 -1100 1 -.names [17461] n_n2480 [19737] [19520] [3620] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [9260] [17310] [17388] [3622] -011- 1 -01-0 1 -.names preset [9245] [17310] [17388] [3624] -011- 1 -01-0 1 -.names preset [9170] nrq7_2 [17712] [3633] -010- 1 -01-0 1 -.names preset pdata_4_4_ nrq7_2 [17712] [3634] -0111 1 -.names preset [9155] [17284] [18376] [3635] -010- 1 -01-1 1 -.names preset [9140] [17284] [18376] [3637] -010- 1 -01-1 1 -.names preset [9125] [17167] [17362] [3640] -010- 1 -01-1 1 -.names preset [9110] [17167] [17362] [3642] -010- 1 -01-1 1 -.names preset [9050] [17453] [18246] [3650] -010- 1 -01-1 1 -.names ppeaka_0_0_ [5413] [17694] [3651] -11- 1 -1-1 1 -.names [5675] n_n3081 [4266] [3653] -111 1 -.names ppeakp_0_0_ [17696] [17698] [17703] [3654] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_0_0_ [4199] [3744] [3655] -111 1 -.names ppeaka_9_9_ [5413] [17694] [3657] -11- 1 -1-1 1 -.names [11750] n_n3081 [4266] [3659] -111 1 -.names ppeakp_9_9_ [17696] [17698] [17703] [3660] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_9_9_ [4199] [3744] [3661] -111 1 -.names [12680] [4199] [3754] n_n2772 [3663] -1111 1 -.names [10475] n_n2772 n_n3081 [4266] [3664] -1111 1 -.names [15425] [4199] [3750] n_n2772 [3665] -1111 1 -.names [6980] [4199] [3715] n_n2772 [3666] -1111 1 -.names [10100] [4199] [3740] n_n2772 [3667] -1111 1 -.names [14600] [4199] [3747] n_n2772 [3668] -1111 1 -.names [10325] [4199] [3744] n_n2772 [3669] -1111 1 -.names [14150] [4199] n_n2772 [3720] [3670] -1111 1 -.names [10880] [4199] [3711] n_n2772 [3671] -1111 1 -.names [8690] [4199] [3738] n_n2772 [3672] -1111 1 -.names [5510] [4199] [3718] n_n2772 [3673] -1111 1 -.names [13100] [4226] n_n2772 [3675] -111 1 -.names [9320] [4199] [3723] n_n2772 [3676] -1111 1 -.names ppeaks_2_2_ [17660] [17662] [3678] -11- 1 -1-1 1 -.names [10130] [4199] [3754] n_n2772 [3679] -1111 1 -.names [10490] n_n2772 n_n3081 [4266] [3680] -1111 1 -.names [12125] [4199] [3750] n_n2772 [3681] -1111 1 -.names [13490] [4199] [3715] n_n2772 [3682] -1111 1 -.names [10115] [4199] [3740] n_n2772 [3683] -1111 1 -.names [6830] [4199] [3747] n_n2772 [3684] -1111 1 -.names [7505] [4199] [3744] n_n2772 [3685] -1111 1 -.names [13415] [4199] n_n2772 [3720] [3686] -1111 1 -.names [11390] [4199] [3711] n_n2772 [3687] -1111 1 -.names [7430] [4199] [3738] n_n2772 [3688] -1111 1 -.names [5525] [4199] [3718] n_n2772 [3689] -1111 1 -.names [13115] [4226] n_n2772 [3691] -111 1 -.names [9335] [4199] [3723] n_n2772 [3692] -1111 1 -.names ppeaks_11_11_ [17660] [17662] [3694] -11- 1 -1-1 1 -.names preset [8945] [17180] [17232] [3699] -010- 1 -01-1 1 -.names preset [8930] [17180] [17232] [3701] -010- 1 -01-1 1 -.names preset [8900] [17037] [18025] [3706] -011- 1 -01-0 1 -.names preset [8855] [17635] [17986] [3713] -010- 1 -01-1 1 -.names preset [8840] [17635] [17986] [3716] -010- 1 -01-1 1 -.names preset [8825] [17999] [18077] [3719] -011- 1 -01-0 1 -.names [4278] n_n2477 [19735] [19504] [3721] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [8780] [18311] [18506] [3725] -011- 1 -01-0 1 -.names [4245] n_n2479 [19495] [19743] [3730] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [8735] nrq7_2 [17715] [3731] -010- 1 -01-0 1 -.names preset [8720] nrq7_2 [17712] [3733] -010- 1 -01-0 1 -.names [4381] n_n2474 [19514] [19733] [3735] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4381] n_n2485 [19466] [19721] [3737] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [8675] [18285] [18363] [3741] -010- 1 -01-1 1 -.names preset [8660] [18285] [18363] [3743] -010- 1 -01-1 1 -.names [4243] n_n2476 [19741] [19531] [3749] -1111 1 -1001 1 -1010 1 -1100 1 -.names [8630] [4253] [3751] -11 1 -.names preset [8600] [17310] [17388] [3757] -011- 1 -01-0 1 -.names preset [8585] [17310] [17388] [3759] -011- 1 -01-0 1 -.names preset [8510] nrq7_2 [17712] [3768] -010- 1 -01-0 1 -.names preset pdata_3_3_ nrq7_2 [17712] [3769] -0111 1 -.names preset [8495] [17284] [18376] [3771] -010- 1 -01-1 1 -.names preset [8480] [17284] [18376] [3773] -010- 1 -01-1 1 -.names preset [8465] [17167] [17362] [3777] -010- 1 -01-1 1 -.names preset [8390] [17453] [18246] [3788] -010- 1 -01-1 1 -.names ppeaka_1_1_ [5413] [17694] [3789] -11- 1 -1-1 1 -.names [4970] n_n3081 [4266] [3791] -111 1 -.names ppeakp_1_1_ [17696] [17698] [17703] [3792] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_1_1_ [4199] [3744] [3793] -111 1 -.names ppeaka_8_8_ [5413] [17694] [3795] -11- 1 -1-1 1 -.names [13895] n_n3081 [4266] [3797] -111 1 -.names ppeakp_8_8_ [17696] [17698] [17703] [3798] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_8_8_ [4199] [3744] [3799] -111 1 -.names [12455] [4199] [3754] n_n2772 [3801] -1111 1 -.names [12155] n_n2772 n_n3081 [4266] [3802] -1111 1 -.names [14255] [4199] [3750] n_n2772 [3803] -1111 1 -.names [4910] [4199] [3715] n_n2772 [3804] -1111 1 -.names [5570] [4199] [3740] n_n2772 [3805] -1111 1 -.names [14180] [4199] [3747] n_n2772 [3806] -1111 1 -.names [10610] [4199] [3744] n_n2772 [3807] -1111 1 -.names [12575] [4199] n_n2772 [3720] [3808] -1111 1 -.names [8720] [4199] [3711] n_n2772 [3809] -1111 1 -.names [9350] [4199] [3738] n_n2772 [3810] -1111 1 -.names [6200] [4199] [3718] n_n2772 [3811] -1111 1 -.names [12845] [4226] n_n2772 [3813] -111 1 -.names [7385] [4199] [3723] n_n2772 [3814] -1111 1 -.names ppeaks_3_3_ [17660] [17662] [3816] -11- 1 -1-1 1 -.names [4565] [4199] [3744] [3818] -111 1 -.names [8330] [4515] [17649] [17650] [3819] -11-- 1 -1-1- 1 -1--1 1 -.names [12635] n_n3925 [5513] [5514] [3820] -111- 1 -11-1 1 -.names preset [8285] [17180] [17232] [3825] -010- 1 -01-1 1 -.names preset [8210] [17635] [17986] [3834] -010- 1 -01-1 1 -.names preset [8195] [17635] [17986] [3836] -010- 1 -01-1 1 -.names preset [8180] [17999] [18077] [3838] -011- 1 -01-0 1 -.names preset [8150] [18311] [18506] [3842] -011- 1 -01-0 1 -.names [4377] n_n2477 [19735] [19504] [3843] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [8135] [18311] [18506] [3844] -011- 1 -01-0 1 -.names preset [8120] [18311] [18506] [3846] -011- 1 -01-0 1 -.names [4245] n_n2482 [19727] [19456] [3848] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [8090] nrq7_2 [17715] [3849] -010- 1 -01-0 1 -.names [17305] n_n2474 [19514] [19733] [3850] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [8075] nrq7_2 [17712] [3851] -010- 1 -01-0 1 -.names [4381] n_n2477 [19735] [19504] [3853] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [8030] [18285] [18363] [3857] -010- 1 -01-1 1 -.names [4306] n_n2474 [19514] [19733] [3858] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [8015] [18285] [18363] [3859] -010- 1 -01-1 1 -.names [4306] n_n2483 [19725] [19479] [3860] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4243] n_n2479 [19495] [19743] [3862] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [7955] [17310] [17388] [3866] -011- 1 -01-0 1 -.names preset [7940] [17310] [17388] [3868] -011- 1 -01-0 1 -.names preset [7880] nrq7_2 [17715] [3875] -010- 1 -01-0 1 -.names preset pdata_15_15_ nrq7_2 [17715] [3876] -0111 1 -.names preset [7865] nrq7_2 [17712] [3877] -010- 1 -01-0 1 -.names preset pdata_6_6_ nrq7_2 [17712] [3878] -0111 1 -.names preset [7850] [17284] [18376] [3879] -010- 1 -01-1 1 -.names preset [7835] [17284] [18376] [3881] -010- 1 -01-1 1 -.names preset [7820] [17167] [17362] [3884] -010- 1 -01-1 1 -.names preset [7805] [17167] [17362] [3886] -010- 1 -01-1 1 -.names preset [7745] [17453] [18246] [3894] -010- 1 -01-1 1 -.names ppeaka_2_2_ [5413] [17694] [3895] -11- 1 -1-1 1 -.names ndout n_n3081 [4266] [3897] -111 1 -.names ppeakp_2_2_ [17696] [17698] [17703] [3898] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_2_2_ [4199] [3744] [3899] -111 1 -.names ppeaka_7_7_ [5413] [17694] [3901] -11- 1 -1-1 1 -.names [14285] n_n3081 [4266] [3903] -111 1 -.names ppeakp_7_7_ [17696] [17698] [17703] [3904] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_7_7_ [4199] [3744] [3905] -111 1 -.names [10700] [4199] [3754] n_n2772 [3907] -1111 1 -.names [12035] n_n2772 n_n3081 [4266] [3908] -1111 1 -.names [14690] [4199] [3750] n_n2772 [3909] -1111 1 -.names [14240] [4199] [3715] n_n2772 [3910] -1111 1 -.names [8885] [4199] [3740] n_n2772 [3911] -1111 1 -.names [8090] [4199] [3747] n_n2772 [3912] -1111 1 -.names [10340] [4199] [3744] n_n2772 [3913] -1111 1 -.names [12815] [4199] n_n2772 [3720] [3914] -1111 1 -.names [14990] [4199] [3711] n_n2772 [3915] -1111 1 -.names [8705] [4199] [3738] n_n2772 [3916] -1111 1 -.names [6890] [4199] [3718] n_n2772 [3917] -1111 1 -.names [12620] [4226] n_n2772 [3919] -111 1 -.names [8030] [4199] [3723] n_n2772 [3920] -1111 1 -.names ppeaks_13_13_ [17660] [17662] [3922] -11- 1 -1-1 1 -.names [6635] [4199] [3744] [3924] -111 1 -.names [7685] [4515] [17649] [17650] [3925] -11-- 1 -1-1- 1 -1--1 1 -.names [12410] n_n3925 [5513] [5514] [3926] -111- 1 -11-1 1 -.names preset [7655] [17180] [17232] [3929] -010- 1 -01-1 1 -.names preset [7640] [17180] [17232] [3931] -010- 1 -01-1 1 -.names preset [7580] [17635] [17986] [3938] -010- 1 -01-1 1 -.names preset [7565] [17635] [17986] [3940] -010- 1 -01-1 1 -.names preset [7550] [17999] [18077] [3942] -011- 1 -01-0 1 -.names [4278] n_n2479 [19495] [19743] [3945] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4377] n_n2476 [19741] [19531] [3947] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [7505] [18311] [18506] [3948] -011- 1 -01-0 1 -.names preset [7490] [18311] [18506] [3950] -011- 1 -01-0 1 -.names preset [7460] nrq7_2 [17715] [3953] -010- 1 -01-0 1 -.names preset [7445] nrq7_2 [17712] [3955] -010- 1 -01-0 1 -.names [18501] n_n2482 [19727] [19456] [3956] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4381] n_n2476 [19741] [19531] [3957] -1111 1 -1001 1 -1010 1 -1100 1 -.names [7415] [4317] [3960] -11 1 -.names preset [7400] [18285] [18363] [3961] -010- 1 -01-1 1 -.names preset [7385] [18285] [18363] [3963] -010- 1 -01-1 1 -.names preset [7355] [18103] [18168] [3967] -011- 1 -01-0 1 -.names [17461] n_n2479 [19495] [19743] [3970] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [7325] [17310] [17388] [3972] -011- 1 -01-0 1 -.names preset [7310] [17310] [17388] [3974] -011- 1 -01-0 1 -.names preset [7250] nrq7_2 [17715] [3981] -010- 1 -01-0 1 -.names preset pdata_14_14_ nrq7_2 [17715] [3982] -0111 1 -.names preset [7235] nrq7_2 [17712] [3983] -010- 1 -01-0 1 -.names preset pdata_5_5_ nrq7_2 [17712] [3984] -0111 1 -.names preset [7220] [17284] [18376] [3985] -010- 1 -01-1 1 -.names preset [7205] [17167] [17362] [3988] -010- 1 -01-1 1 -.names preset [7190] [17167] [17362] [3990] -010- 1 -01-1 1 -.names preset [7175] [17167] [17362] [3992] -010- 1 -01-1 1 -.names preset [7115] [17453] [18246] [4000] -010- 1 -01-1 1 -.names ppeaka_3_3_ [5413] [17694] [4001] -11- 1 -1-1 1 -.names [15785] n_n3081 [4266] [4003] -111 1 -.names ppeakp_3_3_ [17696] [17698] [17703] [4004] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_3_3_ [4199] [3744] [4005] -111 1 -.names [12920] [4199] [3754] n_n2772 [4007] -1111 1 -.names [9665] n_n2772 n_n3081 [4266] [4008] -1111 1 -.names [12005] [4199] [3750] n_n2772 [4009] -1111 1 -.names [6305] [4199] [3715] n_n2772 [4010] -1111 1 -.names [9830] [4199] [3740] n_n2772 [4011] -1111 1 -.names [15020] [4199] [3747] n_n2772 [4012] -1111 1 -.names [8120] [4199] [3744] n_n2772 [4013] -1111 1 -.names [14570] [4199] n_n2772 [3720] [4014] -1111 1 -.names [11150] [4199] [3711] n_n2772 [4015] -1111 1 -.names [8045] [4199] [3738] n_n2772 [4016] -1111 1 -.names [4805] [4199] [3718] n_n2772 [4017] -1111 1 -.names [12380] [4226] n_n2772 [4019] -111 1 -.names [8660] [4199] [3723] n_n2772 [4020] -1111 1 -.names ppeaks_1_1_ [17660] [17662] [4022] -11- 1 -1-1 1 -.names [10415] [4199] [3754] n_n2772 [4023] -1111 1 -.names [9680] n_n2772 n_n3081 [4266] [4025] -1111 1 -.names [15065] [4199] [3750] n_n2772 [4026] -1111 1 -.names [14660] [4199] [3715] n_n2772 [4027] -1111 1 -.names [9845] [4199] [3740] n_n2772 [4028] -1111 1 -.names [7460] [4199] [3747] n_n2772 [4029] -1111 1 -.names [10625] [4199] [3744] n_n2772 [4030] -1111 1 -.names [13775] [4199] n_n2772 [3720] [4031] -1111 1 -.names [11615] [4199] [3711] n_n2772 [4032] -1111 1 -.names [9365] [4199] [3738] n_n2772 [4033] -1111 1 -.names [4820] [4199] [3718] n_n2772 [4034] -1111 1 -.names [12395] [4226] n_n2772 [4036] -111 1 -.names [8675] [4199] [3723] n_n2772 [4037] -1111 1 -.names ppeaks_12_12_ [17660] [17662] [4039] -11- 1 -1-1 1 -.names [5960] [4199] [3744] [4041] -111 1 -.names [7055] [4515] [17649] [17650] [4042] -11-- 1 -1-1- 1 -1--1 1 -.names [6245] n_n3925 [5513] [5514] [4043] -111- 1 -11-1 1 -.names [7010] [4277] [4047] -11 1 -.names preset [6965] [17037] [18025] [4056] -011- 1 -01-0 1 -.names preset [6950] [17037] [18025] [4058] -011- 1 -01-0 1 -.names preset [6935] [17635] [17986] [4060] -010- 1 -01-1 1 -.names preset [6920] [17999] [18077] [4062] -011- 1 -01-0 1 -.names [4278] n_n2474 [19514] [19733] [4065] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4278] n_n2483 [19725] [19479] [4067] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [6830] nrq7_2 [17715] [4073] -010- 1 -01-0 1 -.names [17305] n_n2476 [19741] [19531] [4074] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [6815] nrq7_2 [17712] [4075] -010- 1 -01-0 1 -.names [18501] n_n2479 [19495] [19743] [4076] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4381] n_n2480 [19737] [19520] [4077] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [6770] [18285] [18363] [4079] -010- 1 -01-1 1 -.names [4306] n_n2480 [19737] [19520] [4080] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [6725] [18103] [18168] [4085] -011- 1 -01-0 1 -.names [17461] n_n2476 [19741] [19531] [4088] -1111 1 -1001 1 -1010 1 -1100 1 -.names [17461] n_n2485 [19466] [19721] [4090] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [6680] [17310] [17388] [4092] -011- 1 -01-0 1 -.names preset [6620] nrq7_2 [17715] [4099] -010- 1 -01-0 1 -.names preset pdata_13_13_ nrq7_2 [17715] [4100] -0111 1 -.names preset [6605] nrq7_2 [17712] [4101] -010- 1 -01-0 1 -.names preset pdata_8_8_ nrq7_2 [17712] [4102] -0111 1 -.names preset [6590] [17284] [18376] [4103] -010- 1 -01-1 1 -.names preset [6575] [17284] [18376] [4105] -010- 1 -01-1 1 -.names preset [6560] [17167] [17362] [4108] -010- 1 -01-1 1 -.names preset [6470] [17453] [18246] [4120] -010- 1 -01-1 1 -.names ppeaka_13_13_ [5413] [17694] [4121] -11- 1 -1-1 1 -.names [10760] n_n3081 [4266] [4123] -111 1 -.names ppeakp_13_13_ [17696] [17698] [17703] [4124] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_13_13_ [4199] [3744] [4125] -111 1 -.names [7625] [4199] [3754] n_n2772 [4127] -1111 1 -.names [11300] n_n2772 n_n3081 [4266] [4128] -1111 1 -.names [13865] [4199] [3750] n_n2772 [4129] -1111 1 -.names [11690] [4199] [3715] n_n2772 [4130] -1111 1 -.names [8870] [4199] [3740] n_n2772 [4131] -1111 1 -.names [13085] [4199] [3747] n_n2772 [4132] -1111 1 -.names [5495] [4199] [3744] n_n2772 [4133] -1111 1 -.names [16085] [4199] n_n2772 [3720] [4134] -1111 1 -.names [8075] [4199] [3711] n_n2772 [4135] -1111 1 -.names [6110] [4199] [3738] n_n2772 [4136] -1111 1 -.names [11165] [4199] [3718] n_n2772 [4137] -1111 1 -.names [14210] [4226] n_n2772 [4139] -111 1 -.names [10565] [4199] [3723] n_n2772 [4140] -1111 1 -.names ppeaks_6_6_ [17660] [17662] [4142] -11- 1 -1-1 1 -.names [6320] [4199] [3754] n_n2772 [4143] -1111 1 -.names [11780] n_n2772 n_n3081 [4266] [4144] -1111 1 -.names [13880] [4199] [3750] n_n2772 [4145] -1111 1 -.names [12425] [4199] [3715] n_n2772 [4146] -1111 1 -.names [4880] [4199] [3740] n_n2772 [4147] -1111 1 -.names [9395] [4199] [3747] n_n2772 [4148] -1111 1 -.names [8150] [4199] [3744] n_n2772 [4149] -1111 1 -.names [12365] [4199] n_n2772 [3720] [4150] -1111 1 -.names [15725] [4199] [3711] n_n2772 [4151] -1111 1 -.names [4730] [4199] [3738] n_n2772 [4152] -1111 1 -.names [11180] [4199] [3718] n_n2772 [4153] -1111 1 -.names [15050] [4226] n_n2772 [4155] -111 1 -.names [10580] [4199] [3723] n_n2772 [4156] -1111 1 -.names ppeaks_15_15_ [17660] [17662] [4158] -11- 1 -1-1 1 -.names [7895] [4199] [3744] [4160] -111 1 -.names [6410] [4515] [17649] [17650] [4161] -11-- 1 -1-1- 1 -1--1 1 -.names [6920] n_n3925 [5513] [5514] [4162] -111- 1 -11-1 1 -.names ppeaka_2_2_ [4199] n_n2772 [4224] [4163] -1111 1 -.names [15290] [4199] [3747] n_n2772 [4164] -1111 1 -.names [8555] [4199] [3744] n_n2772 [4165] -1111 1 -.names [14465] [4199] n_n2772 [3720] [4166] -1111 1 -.names [13640] [4199] [3711] n_n2772 [4167] -1111 1 -.names [9140] [4199] [3738] n_n2772 [4168] -1111 1 -.names [7310] [4199] [3718] n_n2772 [4169] -1111 1 -.names [15515] [4226] n_n2772 [4171] -111 1 -.names [4445] [4199] [3723] n_n2772 [4172] -1111 1 -.names ppeakb_2_2_ [4199] [4211] [4515] [4174] -1--1 1 -111- 1 -.names ppeaka_11_11_ [4199] n_n2772 [4224] [4175] -1111 1 -.names [5255] [4199] [3747] n_n2772 [4176] -1111 1 -.names [4595] [4199] [3744] n_n2772 [4177] -1111 1 -.names [14480] [4199] n_n2772 [3720] [4178] -1111 1 -.names [5930] [4199] [3711] n_n2772 [4179] -1111 1 -.names [9155] [4199] [3738] n_n2772 [4180] -1111 1 -.names [14090] [4199] [3718] n_n2772 [4181] -1111 1 -.names [4295] [4226] n_n2772 [4183] -111 1 -.names [5855] [4199] [3723] n_n2772 [4184] -1111 1 -.names ppeakb_11_11_ [4199] [4211] [4515] [4186] -1--1 1 -111- 1 -.names [6365] [4336] [4188] -11 1 -.names [6320] [4325] [4196] -11 1 -.names preset [6290] [17037] [18025] [4213] -011- 1 -01-0 1 -.names preset [6275] [17037] [18025] [4218] -011- 1 -01-0 1 -.names preset [6260] [17635] [17986] [4227] -010- 1 -01-1 1 -.names preset [6245] [17999] [18077] [4230] -011- 1 -01-0 1 -.names [4377] n_n2482 [19727] [19456] [4246] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [6185] [18311] [18506] [4247] -011- 1 -01-0 1 -.names [4245] n_n2483 [19725] [19479] [4249] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [6155] nrq7_2 [17715] [4250] -010- 1 -01-0 1 -.names [17305] n_n2477 [19735] [19504] [4251] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [6140] nrq7_2 [17712] [4257] -010- 1 -01-0 1 -.names [18501] n_n2480 [19737] [19520] [4262] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [6125] nrq7_2 [17712] [4263] -010- 1 -01-0 1 -.names preset [6095] [18285] [18363] [4291] -010- 1 -01-1 1 -.names [4306] n_n2479 [19495] [19743] [4406] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4243] n_n2480 [19737] [19520] [4492] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [6050] [18103] [18168] [4493] -011- 1 -01-0 1 -.names [4308] n_n2474 [19514] [19733] [4494] -1111 1 -1001 1 -1010 1 -1100 1 -.names [17461] n_n2477 [19735] [19504] [4497] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [6005] [17310] [17388] [4506] -011- 1 -01-0 1 -.names preset [5945] nrq7_2 [17715] [4523] -010- 1 -01-0 1 -.names preset pdata_12_12_ nrq7_2 [17715] [4524] -0111 1 -.names preset [5930] nrq7_2 [17712] [4525] -010- 1 -01-0 1 -.names preset pdata_11_11_ nrq7_2 [17712] [4526] -0111 1 -.names preset [5915] nrq7_2 [17712] [4527] -010- 1 -01-0 1 -.names preset pdata_7_7_ nrq7_2 [17712] [4528] -0111 1 -.names preset [5900] nrq7_2 [17712] [4530] -010- 1 -01-0 1 -.names preset pdata_0_0_ nrq7_2 [17712] [4531] -0111 1 -.names preset [5885] [17284] [18376] [4532] -010- 1 -01-1 1 -.names preset [5870] [17167] [17362] [4536] -010- 1 -01-1 1 -.names preset [5780] [17453] [18246] [4549] -010- 1 -01-1 1 -.names ppeaka_12_12_ [5413] [17694] [4551] -11- 1 -1-1 1 -.names [11030] n_n3081 [4266] [4553] -111 1 -.names ppeakp_12_12_ [17696] [17698] [17703] [4554] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_12_12_ [4199] [3744] [4555] -111 1 -.names [8255] [4199] [3754] n_n2772 [4557] -1111 1 -.names [11540] n_n2772 n_n3081 [4266] [4558] -1111 1 -.names [12905] [4199] [3750] n_n2772 [4560] -1111 1 -.names [10970] [4199] [3715] n_n2772 [4561] -1111 1 -.names [8225] [4199] [3740] n_n2772 [4562] -1111 1 -.names [12830] [4199] [3747] n_n2772 [4563] -1111 1 -.names [4790] [4199] [3744] n_n2772 [4564] -1111 1 -.names [15005] [4199] n_n2772 [3720] [4566] -1111 1 -.names [6140] [4199] [3711] n_n2772 [4567] -1111 1 -.names [6785] [4199] [3738] n_n2772 [4568] -1111 1 -.names [11405] [4199] [3718] n_n2772 [4569] -1111 1 -.names [14630] [4226] n_n2772 [4571] -111 1 -.names [6770] [4199] [3723] n_n2772 [4572] -1111 1 -.names ppeaks_7_7_ [17660] [17662] [4575] -11- 1 -1-1 1 -.names [10985] [4199] [3754] n_n2772 [4576] -1111 1 -.names [11900] n_n2772 n_n3081 [4266] [4577] -1111 1 -.names [14270] [4199] [3750] n_n2772 [4578] -1111 1 -.names [12650] [4199] [3715] n_n2772 [4579] -1111 1 -.names [9560] [4199] [3740] n_n2772 [4581] -1111 1 -.names [8735] [4199] [3747] n_n2772 [4582] -1111 1 -.names [10055] [4199] [3744] n_n2772 [4583] -1111 1 -.names [13070] [4199] n_n2772 [3720] [4584] -1111 1 -.names [16070] [4199] [3711] n_n2772 [4585] -1111 1 -.names [5435] [4199] [3738] n_n2772 [4586] -1111 1 -.names [6215] [4199] [3718] n_n2772 [4587] -1111 1 -.names [15410] [4226] n_n2772 [4590] -111 1 -.names [7400] [4199] [3723] n_n2772 [4591] -1111 1 -.names ppeaks_14_14_ [17660] [17662] [4593] -11- 1 -1-1 1 -.names [7265] [4199] [3744] [4596] -111 1 -.names [5720] [4515] [17649] [17650] [4597] -11-- 1 -1-1- 1 -1--1 1 -.names [7550] n_n3925 [5513] [5514] [4598] -111- 1 -11-1 1 -.names [6350] [4199] [3746] n_n2772 [4599] -1111 1 -.names [4475] [4199] [3727] n_n2772 [4601] -1111 1 -.names [6410] [4199] n_n2772 [4207] [4602] -1111 1 -.names [11225] [4199] [3715] n_n2772 [4606] -1111 1 -.names [14405] [4199] [3740] n_n2772 [4607] -1111 1 -.names [10175] [4199] [3718] n_n2772 [4608] -1111 1 -.names [5135] [4199] [3723] n_n2772 [4611] -1111 1 -.names ppeaka_8_8_ [4199] [3744] [4515] [4614] -1--1 1 -111- 1 -.names ppeaka_10_10_ [4199] n_n2772 [4224] [4615] -1111 1 -.names [4550] [4199] [3747] n_n2772 [4616] -1111 1 -.names [5300] [4199] [3744] n_n2772 [4617] -1111 1 -.names [14060] [4199] n_n2772 [3720] [4618] -1111 1 -.names [5225] [4199] [3711] n_n2772 [4620] -1111 1 -.names [7220] [4199] [3738] n_n2772 [4621] -1111 1 -.names [10850] [4199] [3718] n_n2772 [4622] -1111 1 -.names [5015] [4226] n_n2772 [4624] -111 1 -.names [15230] [4199] [3723] n_n2772 [4626] -1111 1 -.names ppeakb_10_10_ [4199] [4211] [4515] [4628] -1--1 1 -111- 1 -.names preset [5675] [17791] [17843] [4629] -010- 1 -01-1 1 -.names preset [5630] [17180] [17232] [4643] -010- 1 -01-1 1 -.names preset [5600] [17037] [18025] [4648] -011- 1 -01-0 1 -.names preset [5555] [17635] [17986] [4657] -010- 1 -01-1 1 -.names [4278] n_n2476 [19741] [19531] [4667] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4278] n_n2485 [19466] [19721] [4669] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [5495] [18311] [18506] [4673] -011- 1 -01-0 1 -.names preset [5465] nrq7_2 [17715] [4680] -010- 1 -01-0 1 -.names preset [5450] nrq7_2 [17712] [4682] -010- 1 -01-0 1 -.names [18501] n_n2477 [19735] [19504] [4683] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4381] n_n2482 [19727] [19456] [4686] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [5405] [18285] [18363] [4688] -010- 1 -01-1 1 -.names preset [5390] [18285] [18363] [4690] -010- 1 -01-1 1 -.names [4243] n_n2483 [19725] [19479] [4693] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [5360] [18103] [18168] [4694] -011- 1 -01-0 1 -.names [17461] n_n2474 [19514] [19733] [4697] -1111 1 -1001 1 -1010 1 -1100 1 -.names [5330] [4340] [4698] -11 1 -.names preset [5315] [17310] [17388] [4702] -011- 1 -01-0 1 -.names preset [5255] nrq7_2 [17715] [4710] -010- 1 -01-0 1 -.names preset pdata_11_11_ nrq7_2 [17715] [4711] -0111 1 -.names preset [5240] nrq7_2 [17714] [4712] -010- 1 -01-0 1 -.names preset pdata_5_5_ nrq7_2 [17714] [4713] -0111 1 -.names preset [5225] nrq7_2 [17712] [4714] -010- 1 -01-0 1 -.names preset pdata_10_10_ nrq7_2 [17712] [4716] -0111 1 -.names preset [5210] [17284] [18376] [4717] -010- 1 -01-1 1 -.names preset [5195] [17284] [18376] [4719] -010- 1 -01-1 1 -.names preset [5180] [17167] [17362] [4725] -010- 1 -01-1 1 -.names preset [5120] [17102] [17154] [4734] -010- 1 -01-1 1 -.names preset [5105] [17102] [17154] [4736] -010- 1 -01-1 1 -.names preset [5090] [17453] [18246] [4738] -010- 1 -01-1 1 -.names preset [5075] [17453] [18246] [4741] -010- 1 -01-1 1 -.names ppeaka_11_11_ [5413] [17694] [4742] -11- 1 -1-1 1 -.names [12020] n_n3081 [4266] [4744] -111 1 -.names ppeakp_11_11_ [17696] [17698] [17703] [4746] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_11_11_ [4199] [3744] [4747] -111 1 -.names [12245] [4199] [3754] n_n2772 [4749] -1111 1 -.names [11765] n_n2772 n_n3081 [4266] [4750] -1111 1 -.names [14675] [4199] [3750] n_n2772 [4751] -1111 1 -.names [5615] [4199] [3715] n_n2772 [4752] -1111 1 -.names [4865] [4199] [3740] n_n2772 [4753] -1111 1 -.names [13790] [4199] [3747] n_n2772 [4755] -1111 1 -.names [9785] [4199] [3744] n_n2772 [4756] -1111 1 -.names [12350] [4199] n_n2772 [3720] [4757] -1111 1 -.names [9380] [4199] [3711] n_n2772 [4758] -1111 1 -.names [4715] [4199] [3738] n_n2772 [4759] -1111 1 -.names [6875] [4199] [3718] n_n2772 [4761] -1111 1 -.names [15035] [4226] n_n2772 [4763] -111 1 -.names [8015] [4199] [3723] n_n2772 [4764] -1111 1 -.names ppeaks_4_4_ [17660] [17662] [4766] -11- 1 -1-1 1 -.names [9185] [4199] [3744] [4768] -111 1 -.names [5030] [4515] [17649] [17650] [4770] -11-- 1 -1-1- 1 -1--1 1 -.names [13835] n_n3925 [5513] [5514] [4771] -111- 1 -11-1 1 -.names [9200] [4199] [3744] [4773] -111 1 -.names [5015] [4515] [17649] [17650] [4774] -11-- 1 -1-1- 1 -1--1 1 -.names [8180] n_n3925 [5513] [5514] [4776] -111- 1 -11-1 1 -.names [7025] [4199] [3746] n_n2772 [4777] -1111 1 -.names [5180] [4199] [3727] n_n2772 [4779] -1111 1 -.names [7055] [4199] n_n2772 [4207] [4780] -1111 1 -.names [10970] [4199] [3715] n_n2772 [4783] -1111 1 -.names [13985] [4199] [3740] n_n2772 [4785] -1111 1 -.names [10460] [4199] [3718] n_n2772 [4786] -1111 1 -.names [4430] [4199] [3723] n_n2772 [4788] -1111 1 -.names ppeaka_7_7_ [4199] [3744] [4515] [4792] -1--1 1 -111- 1 -.names ppeaka_0_0_ [4199] n_n2772 [4224] [4793] -1111 1 -.names [15995] [4199] [3747] n_n2772 [4794] -1111 1 -.names [4580] [4199] [3744] n_n2772 [4795] -1111 1 -.names [13655] [4199] n_n2772 [3720] [4796] -1111 1 -.names [5900] [4199] [3711] n_n2772 [4797] -1111 1 -.names [7835] [4199] [3738] n_n2772 [4798] -1111 1 -.names [10550] [4199] [3718] n_n2772 [4800] -1111 1 -.names [4310] [4226] n_n2772 [4802] -111 1 -.names [15605] [4199] [3723] n_n2772 [4803] -1111 1 -.names ppeakb_0_0_ [4199] [4211] [4515] [4806] -1--1 1 -111- 1 -.names preset [4970] [17791] [17843] [4807] -010- 1 -01-1 1 -.names preset [4895] [17037] [18025] [4828] -011- 1 -01-0 1 -.names [4880] [4330] [4834] -11 1 -.names [11915] [17635] [17986] n_n3925 [4849] -1101 1 -.names ppeakp_11_11_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4852] -1--1 1 -101- 1 -.names [16100] [17427] [17648] [4853] -110 1 -.names [10130] [17180] [17232] [4854] -110 1 -.names ppeaka_11_11_ [17245] nrq7_2 [3746] [4855] -1011 1 -.names [13115] [17999] [18077] [4856] -101 1 -.names ppeakb_11_11_ [16933] nrq7_2 [3718] [4857] -1011 1 -.names [12050] [17635] [17986] n_n3925 [4858] -1101 1 -.names ppeakp_12_12_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4861] -1--1 1 -101- 1 -.names [15755] [17427] [17648] [4862] -110 1 -.names [10415] [17180] [17232] [4863] -110 1 -.names ppeaka_12_12_ [17245] nrq7_2 [3746] [4864] -1011 1 -.names [12395] [17999] [18077] [4866] -101 1 -.names ppeakb_12_12_ [16933] nrq7_2 [3718] [4867] -1011 1 -.names [12170] [17635] [17986] n_n3925 [4868] -1101 1 -.names ppeakp_13_13_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4870] -1--1 1 -101- 1 -.names [13805] [17427] [17648] [4871] -110 1 -.names [10700] [17180] [17232] [4872] -110 1 -.names ppeaka_13_13_ [17245] nrq7_2 [3746] [4873] -1011 1 -.names [12620] [17999] [18077] [4875] -101 1 -.names ppeakb_13_13_ [16933] nrq7_2 [3718] [4876] -1011 1 -.names [12260] [17635] [17986] n_n3925 [4877] -1101 1 -.names ppeakp_14_14_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4879] -1--1 1 -101- 1 -.names [13445] [17427] [17648] [4881] -110 1 -.names [10985] [17180] [17232] [4882] -110 1 -.names ppeaka_14_14_ [17245] nrq7_2 [3746] [4883] -1011 1 -.names [15410] [17999] [18077] [4884] -101 1 -.names ppeakb_14_14_ [16933] nrq7_2 [3718] [4885] -1011 1 -.names [12470] [17635] [17986] n_n3925 [4886] -1101 1 -.names ppeakp_15_15_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4888] -1--1 1 -101- 1 -.names [14615] [17427] [17648] [4890] -110 1 -.names [6320] [17180] [17232] [4891] -110 1 -.names ppeaka_15_15_ [17245] nrq7_2 [3746] [4892] -1011 1 -.names [15050] [17999] [18077] [4893] -101 1 -.names ppeakb_15_15_ [16933] nrq7_2 [3718] [4894] -1011 1 -.names preset [4850] [17635] [17986] [4902] -010- 1 -01-1 1 -.names [11075] [17635] [17986] n_n3925 [4916] -1101 1 -.names ppeakp_7_7_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4918] -1--1 1 -101- 1 -.names [5540] [17427] [17648] [4920] -110 1 -.names [8255] [17180] [17232] [4921] -110 1 -.names ppeaka_7_7_ [17245] nrq7_2 [3746] [4922] -1011 1 -.names [14630] [17999] [18077] [4923] -101 1 -.names ppeakb_7_7_ [16933] nrq7_2 [3718] [4924] -1011 1 -.names [11330] [17635] [17986] n_n3925 [4926] -1101 1 -.names ppeakp_8_8_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4928] -1--1 1 -101- 1 -.names [11420] [17427] [17648] [4929] -110 1 -.names [8915] [17180] [17232] [4930] -110 1 -.names ppeaka_8_8_ [17245] nrq7_2 [3746] [4931] -1011 1 -.names [13460] [17999] [18077] [4932] -101 1 -.names ppeakb_8_8_ [16933] nrq7_2 [3718] [4933] -1011 1 -.names [11570] [17635] [17986] n_n3925 [4935] -1101 1 -.names ppeakp_9_9_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4937] -1--1 1 -101- 1 -.names [11645] [17427] [17648] [4938] -110 1 -.names [9590] [17180] [17232] [4939] -110 1 -.names ppeaka_9_9_ [17245] nrq7_2 [3746] [4941] -1011 1 -.names [13820] [17999] [18077] [4942] -101 1 -.names ppeakb_9_9_ [16933] nrq7_2 [3718] [4943] -1011 1 -.names [11795] [17635] [17986] n_n3925 [4944] -1101 1 -.names ppeakp_10_10_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4946] -1--1 1 -101- 1 -.names [10925] [17427] [17648] [4947] -110 1 -.names [9860] [17180] [17232] [4948] -110 1 -.names ppeaka_10_10_ [17245] nrq7_2 [3746] [4950] -1011 1 -.names [12860] [17999] [18077] [4951] -101 1 -.names ppeakb_10_10_ [16933] nrq7_2 [3718] [4952] -1011 1 -.names ppeaka_0_0_ [16933] nrq7_2 [3718] [4978] -1011 1 -.names [11555] [17635] [17986] n_n3925 [4986] -1101 1 -.names ppeakp_0_0_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4988] -1--1 1 -101- 1 -.names [11630] [17427] [17648] [4989] -110 1 -.names [13175] [17180] [17232] [4990] -110 1 -.names ppeaka_0_0_ [17245] nrq7_2 [3746] [4991] -1011 1 -.names [12605] [17999] [18077] [4992] -101 1 -.names ppeakb_0_0_ [16933] nrq7_2 [3718] [4993] -1011 1 -.names [11315] [17635] [17986] n_n3925 [4995] -1101 1 -.names ppeakp_1_1_ n_n3925 ndn_latch3_9 ndn_latch12_11 [4997] -1--1 1 -101- 1 -.names [9485] [17427] [17648] [4998] -110 1 -.names [12920] [17180] [17232] [4999] -110 1 -.names ppeaka_1_1_ [17245] nrq7_2 [3746] [5000] -1011 1 -.names [12380] [17999] [18077] [5001] -101 1 -.names ppeakb_1_1_ [16933] nrq7_2 [3718] [5002] -1011 1 -.names [11060] [17635] [17986] n_n3925 [5003] -1101 1 -.names ppeakp_2_2_ n_n3925 ndn_latch3_9 ndn_latch12_11 [5005] -1--1 1 -101- 1 -.names [7535] [17427] [17648] [5006] -110 1 -.names [12680] [17180] [17232] [5007] -110 1 -.names ppeaka_2_2_ [17245] nrq7_2 [3746] [5008] -1011 1 -.names [13100] [17999] [18077] [5010] -101 1 -.names ppeakb_2_2_ [16933] nrq7_2 [3718] [5011] -1011 1 -.names [10790] [17635] [17986] n_n3925 [5012] -1101 1 -.names ppeakp_3_3_ n_n3925 ndn_latch3_9 ndn_latch12_11 [5014] -1--1 1 -101- 1 -.names [8165] [17427] [17648] [5016] -110 1 -.names [12455] [17180] [17232] [5017] -110 1 -.names ppeaka_3_3_ [17245] nrq7_2 [3746] [5018] -1011 1 -.names [12845] [17999] [18077] [5019] -101 1 -.names ppeakb_3_3_ [16933] nrq7_2 [3718] [5020] -1011 1 -.names [10505] [17635] [17986] n_n3925 [5021] -1101 1 -.names ppeakp_4_4_ n_n3925 ndn_latch3_9 ndn_latch12_11 [5023] -1--1 1 -101- 1 -.names [6230] [17427] [17648] [5025] -110 1 -.names [12245] [17180] [17232] [5026] -110 1 -.names ppeaka_4_4_ [17245] nrq7_2 [3746] [5027] -1011 1 -.names [15035] [17999] [18077] [5028] -101 1 -.names ppeakb_4_4_ [16933] nrq7_2 [3718] [5029] -1011 1 -.names [10220] [17635] [17986] n_n3925 [5031] -1101 1 -.names ppeakp_5_5_ n_n3925 ndn_latch3_9 ndn_latch12_11 [5033] -1--1 1 -101- 1 -.names [6905] [17427] [17648] [5034] -110 1 -.names [6995] [17180] [17232] [5035] -110 1 -.names ppeaka_5_5_ [17245] nrq7_2 [3746] [5036] -1011 1 -.names [15395] [17999] [18077] [5037] -101 1 -.names ppeakb_5_5_ [16933] nrq7_2 [3718] [5038] -1011 1 -.names [9950] [17635] [17986] n_n3925 [5040] -1101 1 -.names ppeakp_6_6_ n_n3925 ndn_latch3_9 ndn_latch12_11 [5042] -1--1 1 -101- 1 -.names [4835] [17427] [17648] [5043] -110 1 -.names [7625] [17180] [17232] [5044] -110 1 -.names ppeaka_6_6_ [17245] nrq7_2 [3746] [5045] -1011 1 -.names [14210] [17999] [18077] [5046] -101 1 -.names ppeakb_6_6_ [16933] nrq7_2 [3718] [5047] -1011 1 -.names [4377] n_n2480 [19737] [19520] [5057] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [4790] [18311] [18506] [5058] -011- 1 -01-0 1 -.names [4245] n_n2474 [19514] [19733] [5063] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4245] n_n2485 [19466] [19721] [5068] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [4745] nrq7_2 [17712] [5073] -010- 1 -01-0 1 -.names [5106] [17836] [17844] [5088] -001 1 -.names ppeaka_15_15_ [4453] [5271] [5272] [5091] -00-- 1 -0-00 1 -.names [6755] [18285] [18363] [5094] -110 1 -.names ppeaka_15_15_ [18285] nrq7_2 [3723] [5096] -1011 1 -.names ppeakb_15_15_ nrq7_2 [17710] [17711] [5097] -1111 1 -.names [13550] [18506] nrq7_2 [3744] [5098] -1011 1 -.names ppeaka_14_14_ [4453] [5271] [5272] [5106] -00-- 1 -0-00 1 -.names [9740] [18285] [18363] [5113] -110 1 -.names ppeaka_13_13_ [18285] nrq7_2 [3723] [5116] -1011 1 -.names ppeakb_13_13_ nrq7_2 [17710] [17711] [5117] -1111 1 -.names [15500] [18506] nrq7_2 [3744] [5118] -1011 1 -.names [6080] [18285] [18363] [5121] -110 1 -.names ppeaka_14_14_ [18285] nrq7_2 [3723] [5123] -1011 1 -.names ppeakb_14_14_ nrq7_2 [17710] [17711] [5124] -1111 1 -.names [15140] [18506] nrq7_2 [3744] [5125] -1011 1 -.names [4381] n_n2483 [19725] [19479] [5126] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [4700] [18285] [18363] [5132] -010- 1 -01-1 1 -.names [4306] n_n2477 [19735] [19504] [5133] -1111 1 -1001 1 -1010 1 -1100 1 -.names [4243] n_n2482 [19727] [19456] [5139] -1111 1 -1001 1 -1010 1 -1100 1 -.names preset [4655] [18103] [18168] [5143] -011- 1 -01-0 1 -.names [4308] n_n2476 [19741] [19531] [5145] -1111 1 -1001 1 -1010 1 -1100 1 -.names n_n2477 [4438] [19735] [19504] [5157] -111- 1 -11-1 1 --111 1 -.names n_n2476 [5273] [5274] [5275] [5158] -11-- 1 -1-1- 1 -1--1 1 -.names n_n2480 [19737] [19520] [4450] [5164] -11-1 1 -1-11 1 --111 1 -.names n_n2479 [19743] [5166] -11 1 -.names n_n2483 [4440] [19725] [19479] [5171] -111- 1 -11-1 1 --111 1 -.names n_n2482 [5286] [17748] [5172] -11- 1 -1-1 1 -.names [9725] [18285] [18363] [5182] -110 1 -.names ppeaka_2_2_ [18285] nrq7_2 [3723] [5184] -1011 1 -.names ppeakb_2_2_ nrq7_2 [17710] [17711] [5185] -1111 1 -.names [15515] [18506] nrq7_2 [3744] [5186] -1011 1 -.names ppeaka_3_3_ nrq10_4 [19749] [5288] [5190] -01-0 1 -0-10 1 -.names [9995] [18285] [18363] [5192] -110 1 -.names ppeaka_3_3_ [18285] nrq7_2 [3723] [5194] -1011 1 -.names ppeakb_3_3_ nrq7_2 [17710] [17711] [5196] -1111 1 -.names [15860] [18506] nrq7_2 [3744] [5197] -1011 1 -.names [5375] [18285] [18363] [5201] -110 1 -.names ppeaka_4_4_ [18285] nrq7_2 [3723] [5203] -1011 1 -.names ppeakb_4_4_ nrq7_2 [17710] [17711] [5205] -1111 1 -.names [14765] [18506] nrq7_2 [3744] [5206] -1011 1 -.names [4670] [18285] [18363] [5208] -110 1 -.names ppeaka_5_5_ [18285] nrq7_2 [3723] [5211] -1011 1 -.names ppeakb_5_5_ nrq7_2 [17710] [17711] [5212] -1111 1 -.names [8330] [18506] nrq7_2 [3744] [5213] -1011 1 -.names [6740] [18285] [18363] [5218] -110 1 -.names ppeaka_6_6_ [18285] nrq7_2 [3723] [5221] -1011 1 -.names ppeakb_6_6_ nrq7_2 [17710] [17711] [5222] -1111 1 -.names [7685] [18506] nrq7_2 [3744] [5223] -1011 1 -.names [6065] [18285] [18363] [5228] -110 1 -.names ppeaka_7_7_ [18285] nrq7_2 [3723] [5230] -1011 1 -.names ppeakb_7_7_ nrq7_2 [17710] [17711] [5231] -1111 1 -.names [7055] [18506] nrq7_2 [3744] [5232] -1011 1 -.names [8000] [18285] [18363] [5235] -110 1 -.names ppeaka_8_8_ [18285] nrq7_2 [3723] [5237] -1011 1 -.names ppeakb_8_8_ nrq7_2 [17710] [17711] [5238] -1111 1 -.names [6410] [18506] nrq7_2 [3744] [5239] -1011 1 -.names ppeaka_8_8_ ppeaka_9_9_ [19743] [5277] [5241] -0100 1 -.names ppeaka_8_8_ ppeaka_9_9_ [19743] [5277] [5243] -10-0 1 --010 1 -.names [7370] [18285] [18363] [5245] -110 1 -.names ppeaka_9_9_ [18285] nrq7_2 [3723] [5247] -1011 1 -.names ppeakb_9_9_ nrq7_2 [17710] [17711] [5248] -1111 1 -.names [5720] [18506] nrq7_2 [3744] [5250] -1011 1 -.names [9305] [18285] [18363] [5254] -110 1 -.names ppeaka_10_10_ [18285] nrq7_2 [3723] [5257] -1011 1 -.names ppeakb_10_10_ nrq7_2 [17710] [17711] [5258] -1111 1 -.names [5015] [18506] nrq7_2 [3744] [5259] -1011 1 -.names [8645] [18285] [18363] [5261] -110 1 -.names ppeaka_11_11_ [18285] nrq7_2 [3723] [5263] -1011 1 -.names ppeakb_11_11_ nrq7_2 [17710] [17711] [5265] -1111 1 -.names [4295] [18506] nrq7_2 [3744] [5266] -1011 1 -.names [5273] [5274] [5275] [17756] [5271] -0001 1 -.names nrq10_4 [19743] [19989] [17753] [5272] -0-1- 1 -00-1 1 -.names [19743] [5277] [17753] [17754] [5273] --1-1 1 -0-11 1 -.names [19743] [4509] [5277] [17753] [5274] -110- 1 --100 1 -.names ppeaka_11_11_ [4455] [5275] -00 1 -.names nrq7_2 [19989] [17710] [17711] [5277] -01-- 1 --10- 1 --1-0 1 -.names nrq10_4 [19749] [5288] [5283] -00- 1 -0-1 1 -.names nrq10_4 [19749] [4508] [5288] [5286] -1-10 1 --110 1 -.names ppeaka_5_5_ [4452] [5287] -00 1 -.names [5290] [5291] [5292] [17745] [5288] -0001 1 -.names nrq7_2 [19749] [17710] [17711] [5289] -00-- 1 --00- 1 --0-0 1 -.names [4265] [17719] [17722] [17743] [5290] -0001 1 -.names [4265] [4507] [17719] [17722] [5291] -11-- 1 --11- 1 --1-1 1 -.names ppeaka_2_2_ [4457] [5292] -00 1 -.names [10010] [18285] [18363] [5295] -110 1 -.names ppeaka_12_12_ [18285] nrq7_2 [3723] [5297] -1011 1 -.names ppeakb_12_12_ nrq7_2 [17710] [17711] [5298] -1111 1 -.names [15845] [18506] nrq7_2 [3744] [5299] -1011 1 -.names ppeaka_0_0_ nrq7_2 [17710] [17711] [5313] -1111 1 -.names [8630] [18285] [18363] [5320] -110 1 -.names ppeaka_0_0_ [18285] nrq7_2 [3723] [5322] -1011 1 -.names ppeakb_0_0_ nrq7_2 [17710] [17711] [5323] -1111 1 -.names [4310] [18506] nrq7_2 [3744] [5325] -1011 1 -.names [9290] [18285] [18363] [5327] -110 1 -.names ppeaka_1_1_ [18285] nrq7_2 [3723] [5329] -1011 1 -.names ppeakb_1_1_ nrq7_2 [17710] [17711] [5331] -1111 1 -.names [5030] [18506] nrq7_2 [3744] [5332] -1011 1 -.names preset [4610] [17310] [17388] [5334] -011- 1 -01-0 1 -.names preset [4550] nrq7_2 [17715] [5344] -010- 1 -01-0 1 -.names preset pdata_10_10_ nrq7_2 [17715] [5346] -0111 1 -.names preset [4535] nrq7_2 [17714] [5349] -010- 1 -01-0 1 -.names preset pdata_15_15_ nrq7_2 [17714] [5350] -0111 1 -.names preset [4520] nrq7_2 [17712] [5353] -010- 1 -01-0 1 -.names preset pdata_9_9_ nrq7_2 [17712] [5355] -0111 1 -.names preset [4505] [17284] [18376] [5358] -010- 1 -01-1 1 -.names preset [4490] [17284] [18376] [5363] -010- 1 -01-1 1 -.names preset [4475] [17167] [17362] [5368] -010- 1 -01-1 1 -.names preset [4415] [17102] [17154] [5385] -010- 1 -01-1 1 -.names preset [4400] [17102] [17154] [5389] -010- 1 -01-1 1 -.names preset [4370] [17453] [18246] [5398] -010- 1 -01-1 1 -.names preset [4355] [17453] [18246] [5403] -010- 1 -01-1 1 -.names ppeaka_10_10_ [5413] [17694] [5407] -11- 1 -1-1 1 -.names [12140] n_n3081 [4266] [5409] -111 1 -.names ppeakp_10_10_ [17696] [17698] [17703] [5410] -11-- 1 -1-1- 1 -1--1 1 -.names ppeakb_10_10_ [4199] [3744] [5411] -111 1 -.names [4199] [3720] [4024] [5413] -111 1 -.names [4199] [3720] [4024] [5418] -110 1 -.names [6995] [4199] [3754] n_n2772 [5426] -1111 1 -.names [11885] n_n2772 n_n3081 [4266] [5427] -1111 1 -.names [13505] [4199] [3750] n_n2772 [5428] -1111 1 -.names [11465] [4199] [3715] n_n2772 [5430] -1111 1 -.names [9545] [4199] [3740] n_n2772 [5431] -1111 1 -.names [13430] [4199] [3747] n_n2772 [5432] -1111 1 -.names [6185] [4199] [3744] n_n2772 [5433] -1111 1 -.names [13055] [4199] n_n2772 [3720] [5434] -1111 1 -.names [7445] [4199] [3711] n_n2772 [5436] -1111 1 -.names [5420] [4199] [3738] n_n2772 [5437] -1111 1 -.names [10895] [4199] [3718] n_n2772 [5438] -1111 1 -.names [15395] [4226] n_n2772 [5440] -111 1 -.names [10280] [4199] [3723] n_n2772 [5441] -1111 1 -.names ppeaks_5_5_ [17660] [17662] [5443] -11- 1 -1-1 1 -.names [8525] [4199] [3744] [5451] -111 1 -.names [4310] [4515] [17649] [17650] [5452] -11-- 1 -1-1- 1 -1--1 1 -.names [14225] n_n3925 [5513] [5514] [5453] -111- 1 -11-1 1 -.names [8540] [4199] [3744] [5455] -111 1 -.names [4295] [4515] [17649] [17650] [5456] -11-- 1 -1-1- 1 -1--1 1 -.names [8825] n_n3925 [5513] [5514] [5457] -111- 1 -11-1 1 -.names [4955] [4199] [3746] n_n2772 [5464] -1111 1 -.names [5870] [4199] [3727] n_n2772 [5467] -1111 1 -.names [7685] [4199] n_n2772 [4207] [5468] -1111 1 -.names [11690] [4199] [3715] n_n2772 [5471] -1111 1 -.names [15200] [4199] [3740] n_n2772 [5472] -1111 1 -.names [10745] [4199] [3718] n_n2772 [5473] -1111 1 -.names [15935] [4199] [3723] n_n2772 [5476] -1111 1 -.names ppeaka_6_6_ [4199] [3744] [4515] [5479] -1--1 1 -111- 1 -.names ppeaka_1_1_ [4199] n_n2772 [4224] [5483] -1111 1 -.names [15650] [4199] [3747] n_n2772 [5484] -1111 1 -.names [5285] [4199] [3744] n_n2772 [5485] -1111 1 -.names [13310] [4199] n_n2772 [3720] [5486] -1111 1 -.names [13295] [4199] [3711] n_n2772 [5487] -1111 1 -.names [8480] [4199] [3738] n_n2772 [5488] -1111 1 -.names [14510] [4199] [3718] n_n2772 [5490] -1111 1 -.names [5030] [4226] n_n2772 [5492] -111 1 -.names [5150] [4199] [3723] n_n2772 [5493] -1111 1 -.names ppeakb_1_1_ [4199] [4211] [4515] [5496] -1--1 1 -111- 1 -.names ppeaka_12_12_ [4199] n_n2772 [4224] [5497] -1111 1 -.names [5945] [4199] [3747] n_n2772 [5498] -1111 1 -.names [9230] [4199] [3744] n_n2772 [5499] -1111 1 -.names [13325] [4199] n_n2772 [3720] [5500] -1111 1 -.names [15260] [4199] [3711] n_n2772 [5501] -1111 1 -.names [8495] [4199] [3738] n_n2772 [5502] -1111 1 -.names [7955] [4199] [3718] n_n2772 [5503] -1111 1 -.names [15845] [4226] n_n2772 [5506] -111 1 -.names [6545] [4199] [3723] n_n2772 [5507] -1111 1 -.names ppeakb_12_12_ [4199] [4211] [4515] [5509] -1--1 1 -111- 1 -.names preset pdn [17089] [4202] [5513] -0100 1 -.names preset [17596] [4513] [5514] -001 1 -.names [17596] [4513] nrq1_4 [17610] [5520] ---11 1 -01-1 1 -.names pdn [17089] [4202] [5522] -101 1 -.names [17856] [18207] [5528] -01 1 -.names preset ndout [17791] [17843] [5582] -010- 1 -01-1 1 -.names ppeaki_6_6_ ppeaki_7_7_ [17752] [17517] -000 1 -.names [17544] [17713] [17752] [17519] -011 1 -.names [17674] [17609] [17520] -11 1 -.names [17544] [17713] [17752] [17521] -111 1 -.names ppeaki_6_6_ ppeaki_4_4_ [17522] -10 1 -.names [17713] [17674] [17523] -00 1 -.names ppeaki_5_5_ ppeaki_4_4_ [17524] -01 1 -.names [17713] [17609] [17525] -11 1 -.names [17609] [17674] [17713] [17527] -011 1 -.names ppeaki_6_6_ ppeaki_7_7_ [17752] [17528] -100 1 -.names [17713] [17674] [17529] -01 1 -.names ppeaki_5_5_ ppeaki_4_4_ [17530] -00 1 -.names [17713] [17609] [17532] -01 1 -.names [17674] [17609] [17533] -11 1 -.names [17544] [17713] [17752] [17534] -101 1 -.names ppeaki_5_5_ ppeaki_4_4_ [17535] -00 1 -.names [17713] [17609] [17536] -00 1 -.names ppeaki_6_6_ ppeaki_4_4_ [17537] -11 1 -.names [17713] [17674] [17538] -10 1 -.names ppeaki_5_5_ ppeaki_4_4_ [17540] -01 1 -.names [17713] [17609] [17541] -10 1 -.names ppeaki_6_6_ ppeaki_7_7_ [17752] [17542] -100 1 -.names [17713] [17674] [17543] -11 1 -.names [17609] [17674] [17713] [17545] -010 1 -.names ppeaki_6_6_ ppeaki_7_7_ [17752] [17546] -000 1 -.names [17544] [17713] [17752] [17547] -001 1 -.names [3784] n_n2319 [17555] -1- 1 --1 1 -.names n_n2326 n_n2314 n_n2325 n_n2316 [17556] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n_n2318 n_n2323 n_n2317 n_n2315 [17557] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n_n2321 n_n2324 n_n2320 n_n2322 [17558] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [17596] [17661] [18597] [18636] [17562] -1000 1 -.names n_n2333 n_n3714 n_n3713 [17562] [17564] -01-1 1 -0-11 1 -.names [17596] [17661] [18597] [18636] [17566] -1000 1 -.names n_n3714 n_n3713 [17566] [17568] -1-1 1 --11 1 -.names [17596] [17661] [18597] [18636] [17572] -1000 1 -.names n_n2333 n_n3712 n_n3711 [17572] [17574] -01-1 1 -0-11 1 -.names [17596] [17661] [18597] [18636] [17576] -1000 1 -.names n_n3712 n_n3711 [17576] [17577] -1-1 1 --11 1 -.names n_n2344 n_n2333 [17568] [17577] [17580] -001- 1 -00-1 1 -.names [17596] [17661] [18597] [17582] -100 1 -.names [10805] [10820] [18207] [17593] -000 1 -.names [11090] [11345] [11585] [11600] [17594] -0000 1 -.names [11810] [11930] [12065] [12080] [17595] -0000 1 -.names [12185] [12200] [12275] [12485] [17597] -0000 1 -.names [17595] [17594] [17599] -11 1 -.names [12695] [12935] [17593] [17597] [17600] -0011 1 -.names [17986] [17804] [17601] -10 1 -.names [17674] [17609] [17602] -00 1 -.names [17544] [17713] [17752] [17603] -011 1 -.names ppeaki_6_6_ ppeaki_4_4_ [17605] -01 1 -.names [17674] [17609] [17606] -00 1 -.names [17544] [17713] [17752] [17607] -001 1 -.names ppeaki_6_6_ ppeaki_4_4_ [17608] -00 1 -.names pirq_0_0_ preset [18064] [18129] [17610] -000- 1 -00-0 1 --010 1 -.names [15545] [4269] [5507] [17615] ---1 1 -11- 1 -.names [6470] [4260] [5497] [5506] [17616] ---1- 1 ----1 1 -11-- 1 -.names [5498] [5499] [5500] [5501] [17617] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [5502] [5503] [5509] [17617] [17621] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [9065] [4269] [5493] [17626] ---1 1 -11- 1 -.names [5075] [4260] [5483] [5492] [17627] ---1- 1 ----1 1 -11-- 1 -.names [5484] [5485] [5486] [5487] [17628] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [5488] [5490] [5496] [17628] [17631] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [5476] [5473] [17638] -1- 1 --1 1 -.names ppeaka_7_7_ ppeakp_6_6_ [4298] [4392] [17639] --11- 1 -1--1 1 -.names ppeaka_6_6_ [12560] [4260] [4269] [17640] -0-1- 1 --1-1 1 -.names ppeakb_6_6_ [4260] [4397] [5464] [17641] ----1 1 -01-- 1 -1-1- 1 -.names [5467] [5468] [5471] [5472] [17642] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [5479] [17638] [17639] [17640] [17647] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4199] [4219] [4225] [17649] -11- 1 -1-1 1 -.names [4199] [3750] [4212] [17650] -11- 1 -1-1 1 -.names [7655] [4199] [3754] [5457] [17652] ----1 1 -111- 1 -.names [7640] [4199] [3754] [5453] [17654] ----1 1 -111- 1 -.names preset pdn [17089] n_n3081 [17657] -0100 1 -.names [5528] [17599] [17600] [17657] [17658] -00-1 1 -0-01 1 -.names n_n3925 [4202] [4266] [5514] [17659] -0--1 1 -001- 1 -.names n_n2772 [17658] [17659] [17660] -11- 1 -1-1 1 -.names preset ndn7_2 [4205] [4211] [17662] -000- 1 -01-1 1 -.names [5438] [5437] [17668] -1- 1 --1 1 -.names [5427] [5440] [5441] [17670] -1-- 1 --1- 1 ---1 1 -.names [13700] [14555] [4260] [4269] [17671] -1-1- 1 --1-1 1 -.names [5426] [5428] [5430] [5431] [17672] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [5432] [5433] [5434] [5436] [17673] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [5443] [17668] [17670] [17671] [17678] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names ppeakb_7_7_ ppeakb_14_14_ ppeakb_10_10_ ppeakb_8_8_ [17688] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names ppeakb_9_9_ ppeakb_15_15_ ppeakb_11_11_ ppeakb_0_0_ [17689] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names ppeakb_1_1_ ppeakb_12_12_ ppeakb_2_2_ ppeakb_3_3_ [17690] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names ppeakb_13_13_ ppeakb_4_4_ ppeakb_5_5_ ppeakb_6_6_ [17691] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4199] [3711] n_n2333 [17694] -11- 1 -1-1 1 -.names preset_0_0_ [17024] [18545] [4266] [17695] -00-1 1 --101 1 -.names [4199] [3715] [4202] [17695] [17696] -11-- 1 ---11 1 -.names [4199] [4207] [4219] [17698] -11- 1 -1-1 1 -.names [4199] [4204] [4208] [17699] -11- 1 -1-1 1 -.names preset n_n2772 [5418] [17699] [17703] ---1- 1 ----1 1 -00-- 1 -.names [4850] [5409] [5513] [5514] [17704] --1-- 1 -1-1- 1 -1--1 1 -.names [6965] [4199] [3740] [17704] [17705] ----1 1 -111- 1 -.names n_n2344 [18610] [17709] -10 1 -.names [18610] n_n2344 nsl8_2 [17710] -010 1 -.names [3770] [18168] [17711] -10 1 -.names [3711] [18493] [17712] -10 1 -.names [3720] [16920] [17714] -10 1 -.names [3747] [17297] [17715] -10 1 -.names [3775] [17453] [17716] -10 1 -.names [16920] nrq7_2 [3720] [17715] [17717] --1-1 1 -011- 1 -.names nrq7_2 [17710] [17712] [17716] [17718] -1-1- 1 -11-1 1 -.names [17284] nrq7_2 [3738] ndn_latch24_2 [17719] ----1 1 -011- 1 -.names [18285] [18311] [18363] [18506] [17720] -1-0- 1 --0-1 1 -.names nrq23_3 nrq14_3 [5313] [17720] [17722] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [10025] [18311] [18506] [5320] [17724] ----1 1 -101- 1 -.names [5322] [5323] [5325] [17724] [17727] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [10310] [18311] [18506] [5327] [17728] ----1 1 -101- 1 -.names [5329] [5331] [5332] [17728] [17731] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [6860] [18311] [18506] [5295] [17738] ----1 1 -101- 1 -.names [5297] [5298] [5299] [17738] [17742] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4507] ppeaka_1_1_ [17743] -00 1 -.names ppeaka_3_3_ ppeaka_2_2_ [17745] -00 1 -.names [4508] ppeaka_4_4_ [17746] -00 1 -.names [5287] [5288] [5289] [17746] [17748] -1--- 1 --1-1 1 ---11 1 -.names ppeaka_6_6_ ppeaka_5_5_ [17749] -00 1 -.names ppeaka_9_9_ ppeaka_8_8_ [17753] -00 1 -.names [4509] ppeaka_10_10_ [17754] -00 1 -.names ppeaka_12_12_ ppeaka_11_11_ [17756] -00 1 -.names ppeaka_10_10_ ppeaka_11_11_ nrq10_4 [18861] [17757] -00-1 1 --001 1 -.names nrq10_4 [18861] [5271] [17757] [17758] -00-- 1 -1-01 1 --001 1 -.names [4760] [18311] [18506] [5182] [17759] ----1 1 -101- 1 -.names [5184] [5185] [5186] [17759] [17763] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [6845] [18311] [18506] [5192] [17764] ----1 1 -101- 1 -.names [5194] [5196] [5197] [17764] [17768] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names ppeaka_1_1_ ppeaka_2_2_ nrq10_4 n_n2471 [17769] -00-0 1 --000 1 -.names nrq10_4 [19749] [5288] [17769] [17770] -010- 1 -1-01 1 --101 1 -.names [6170] [18311] [18506] [5201] [17771] ----1 1 -101- 1 -.names [5203] [5205] [5206] [17771] [17774] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8105] [18311] [18506] [5208] [17776] ----1 1 -101- 1 -.names [5211] [5212] [5213] [17776] [17780] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7475] [18311] [18506] [5218] [17781] ----1 1 -101- 1 -.names [5221] [5222] [5223] [17781] [17784] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names ppeaka_5_5_ [5286] [17748] [17785] -000 1 -.names [9410] [18311] [18506] [5228] [17787] ----1 1 -101- 1 -.names [5230] [5231] [5232] [17787] [17792] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8750] [18311] [18506] [5235] [17793] ----1 1 -101- 1 -.names [5237] [5238] [5239] [17793] [17796] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [10040] [18311] [18506] [5245] [17797] ----1 1 -101- 1 -.names [5247] [5248] [5250] [17797] [17801] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [9770] [18311] [18506] [5254] [17805] ----1 1 -101- 1 -.names [5257] [5258] [5259] [17805] [17808] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [10595] [18311] [18506] [5261] [17809] ----1 1 -101- 1 -.names [5263] [5265] [5266] [17809] [17813] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4775] [18311] [18506] [5113] [17826] ----1 1 -101- 1 -.names [5116] [5117] [5118] [17826] [17829] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [5480] [18311] [18506] [5121] [17830] ----1 1 -101- 1 -.names [5123] [5124] [5125] [17830] [17833] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names ppeaka_13_13_ ppeaka_14_14_ [17834] -01 1 -.names nrq10_4 [18861] [5271] [17834] [17836] -000- 1 -1-11 1 -.names [8765] [18311] [18506] [5094] [17837] ----1 1 -101- 1 -.names [5096] [5097] [5098] [17837] [17841] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names ppeaka_15_15_ ppeaka_14_14_ [17842] -10 1 -.names nrq7_2 [17710] [17711] [17842] [17844] -1111 1 -.names ppeaka_15_15_ ppeaka_14_14_ [17845] -01 1 -.names nrq10_4 [18861] [5271] [17845] [17846] -1--1 1 -000- 1 -.names [18025] nrq7_2 [3740] nrq4_2 [17865] ----1 1 -011- 1 -.names [5043] [5044] [5046] [17868] -1-- 1 --1- 1 ---1 1 -.names [5040] [5042] [17868] [17871] -1-- 1 --1- 1 ---1 1 -.names [5045] [5047] [17871] [17873] -1-- 1 --1- 1 ---1 1 -.names [5034] [5035] [5037] [17875] -1-- 1 --1- 1 ---1 1 -.names [5031] [5033] [17875] [17877] -1-- 1 --1- 1 ---1 1 -.names [5036] [5038] [17877] [17880] -1-- 1 --1- 1 ---1 1 -.names [5025] [5026] [5028] [17883] -1-- 1 --1- 1 ---1 1 -.names [5021] [5023] [17883] [17885] -1-- 1 --1- 1 ---1 1 -.names [5027] [5029] [17885] [17887] -1-- 1 --1- 1 ---1 1 -.names [5016] [5017] [5019] [17889] -1-- 1 --1- 1 ---1 1 -.names [5012] [5014] [17889] [17891] -1-- 1 --1- 1 ---1 1 -.names [5018] [5020] [17891] [17894] -1-- 1 --1- 1 ---1 1 -.names [5006] [5007] [5010] [17896] -1-- 1 --1- 1 ---1 1 -.names [5003] [5005] [17896] [17898] -1-- 1 --1- 1 ---1 1 -.names [5008] [5011] [17898] [17900] -1-- 1 --1- 1 ---1 1 -.names [17037] [17635] [17986] [18025] [17901] --10- 1 -0--1 1 -.names [17427] [17648] [17999] [18077] [17902] -10-- 1 ---01 1 -.names [17902] [17901] [17903] -1- 1 --1 1 -.names [17245] nrq7_2 [3746] [17903] [17904] ----1 1 -011- 1 -.names [17904] [4978] [17906] -1- 1 --1 1 -.names [4989] [4990] [4992] [17909] -1-- 1 --1- 1 ---1 1 -.names [4986] [4988] [17909] [17911] -1-- 1 --1- 1 ---1 1 -.names [4991] [4993] [17911] [17913] -1-- 1 --1- 1 ---1 1 -.names [4998] [4999] [5001] [17915] -1-- 1 --1- 1 ---1 1 -.names [4995] [4997] [17915] [17917] -1-- 1 --1- 1 ---1 1 -.names [5000] [5002] [17917] [17920] -1-- 1 --1- 1 ---1 1 -.names ppeaks_0_0_ [4273] [17906] [17913] [17924] -11-- 1 --1-1 1 ---11 1 -.names ppeaka_2_2_ [16933] nrq7_2 [3718] [17925] -1011 1 -.names ppeaka_3_3_ [16933] nrq7_2 [3718] [17926] -1011 1 -.names ppeaka_4_4_ [16933] nrq7_2 [3718] [17927] -1011 1 -.names ppeaka_5_5_ [16933] nrq7_2 [3718] [17928] -1011 1 -.names ppeaka_6_6_ [16933] nrq7_2 [3718] [17932] -1011 1 -.names [4947] [4948] [4951] [17937] -1-- 1 --1- 1 ---1 1 -.names [4944] [4946] [17937] [17939] -1-- 1 --1- 1 ---1 1 -.names [4950] [4952] [17939] [17941] -1-- 1 --1- 1 ---1 1 -.names [4938] [4939] [4942] [17943] -1-- 1 --1- 1 ---1 1 -.names [4935] [4937] [17943] [17946] -1-- 1 --1- 1 ---1 1 -.names [4941] [4943] [17946] [17949] -1-- 1 --1- 1 ---1 1 -.names [4929] [4930] [4932] [17951] -1-- 1 --1- 1 ---1 1 -.names [4926] [4928] [17951] [17953] -1-- 1 --1- 1 ---1 1 -.names [4931] [4933] [17953] [17955] -1-- 1 --1- 1 ---1 1 -.names [4920] [4921] [4923] [17958] -1-- 1 --1- 1 ---1 1 -.names [4916] [4918] [17958] [17961] -1-- 1 --1- 1 ---1 1 -.names [4922] [4924] [17961] [17963] -1-- 1 --1- 1 ---1 1 -.names ppeaka_7_7_ [16933] nrq7_2 [3718] [17964] -1011 1 -.names ppeaka_8_8_ [16933] nrq7_2 [3718] [17965] -1011 1 -.names ppeaka_9_9_ [16933] nrq7_2 [3718] [17966] -1011 1 -.names ppeaka_10_10_ [16933] nrq7_2 [3718] [17969] -1011 1 -.names [4890] [4891] [4893] [17979] -1-- 1 --1- 1 ---1 1 -.names [4886] [4888] [17979] [17981] -1-- 1 --1- 1 ---1 1 -.names [4892] [4894] [17981] [17984] -1-- 1 --1- 1 ---1 1 -.names [4881] [4882] [4884] [17987] -1-- 1 --1- 1 ---1 1 -.names [4877] [4879] [17987] [17989] -1-- 1 --1- 1 ---1 1 -.names [4883] [4885] [17989] [17991] -1-- 1 --1- 1 ---1 1 -.names [4871] [4872] [4875] [17993] -1-- 1 --1- 1 ---1 1 -.names [4868] [4870] [17993] [17996] -1-- 1 --1- 1 ---1 1 -.names [4873] [4876] [17996] [17998] -1-- 1 --1- 1 ---1 1 -.names [4862] [4863] [4866] [18001] -1-- 1 --1- 1 ---1 1 -.names [4858] [4861] [18001] [18003] -1-- 1 --1- 1 ---1 1 -.names [4864] [4867] [18003] [18005] -1-- 1 --1- 1 ---1 1 -.names [4853] [4854] [4856] [18008] -1-- 1 --1- 1 ---1 1 -.names [4849] [4852] [18008] [18010] -1-- 1 --1- 1 ---1 1 -.names [4855] [4857] [18010] [18013] -1-- 1 --1- 1 ---1 1 -.names ppeaka_11_11_ [16933] nrq7_2 [3718] [18014] -1011 1 -.names ppeaka_12_12_ [16933] nrq7_2 [3718] [18015] -1011 1 -.names ppeaka_13_13_ [16933] nrq7_2 [3718] [18016] -1011 1 -.names ppeaka_14_14_ [16933] nrq7_2 [3718] [18017] -1011 1 -.names [8405] [4269] [4803] [18037] ---1 1 -11- 1 -.names [4355] [4260] [4793] [4802] [18039] ---1- 1 ----1 1 -11-- 1 -.names [4794] [4795] [4796] [4797] [18040] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4798] [4800] [4806] [18040] [18043] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4788] [4786] [18047] -1- 1 --1 1 -.names ppeaka_8_8_ ppeakp_7_7_ [4298] [4392] [18049] --11- 1 -1--1 1 -.names ppeaka_7_7_ [12335] [4260] [4269] [18050] -0-1- 1 --1-1 1 -.names ppeakb_7_7_ [4260] [4397] [4777] [18051] ----1 1 -01-- 1 -1-1- 1 -.names [4779] [4780] [4783] [4785] [18052] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4792] [18047] [18049] [18050] [18056] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [9620] [4199] [3754] [4776] [18057] ----1 1 -111- 1 -.names [9605] [4199] [3754] [4771] [18060] ----1 1 -111- 1 -.names [4761] [4759] [18068] -1- 1 --1 1 -.names [4750] [4763] [4764] [18069] -1-- 1 --1- 1 ---1 1 -.names [11120] [14975] [4260] [4269] [18070] -1-1- 1 --1-1 1 -.names [4749] [4751] [4752] [4753] [18071] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4755] [4756] [4757] [4758] [18073] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4766] [18068] [18069] [18070] [18078] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [5555] [4744] [5513] [5514] [18079] --1-- 1 -1-1- 1 -1--1 1 -.names [6290] [4199] [3740] [18079] [18080] ----1 1 -111- 1 -.names [14810] [4269] [4626] [18114] ---1 1 -11- 1 -.names [5090] [4260] [4615] [4624] [18115] ---1- 1 ----1 1 -11-- 1 -.names [4616] [4617] [4618] [4620] [18117] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4621] [4622] [4628] [18117] [18120] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4611] [4608] [18124] -1- 1 --1 1 -.names ppeaka_9_9_ ppeakp_8_8_ [4298] [4392] [18125] --11- 1 -1--1 1 -.names ppeaka_8_8_ [15695] [4260] [4269] [18127] -0-1- 1 --1-1 1 -.names ppeakb_8_8_ [4260] [4397] [4599] [18128] ----1 1 -01-- 1 -1-1- 1 -.names [4601] [4602] [4606] [4607] [18130] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4614] [18124] [18125] [18127] [18134] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8945] [4199] [3754] [4598] [18135] ----1 1 -111- 1 -.names [4587] [4586] [18144] -1- 1 --1 1 -.names [4577] [4590] [4591] [18145] -1-- 1 --1- 1 ---1 1 -.names [6725] [11375] [4260] [4269] [18146] --11- 1 -1--1 1 -.names [4576] [4578] [4579] [4581] [18147] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4582] [4583] [4584] [4585] [18148] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4593] [18144] [18145] [18146] [18153] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4569] [4568] [18160] -1- 1 --1 1 -.names [4558] [4571] [4572] [18161] -1-- 1 --1- 1 ---1 1 -.names [9275] [13745] [4260] [4269] [18162] -1-1- 1 --1-1 1 -.names [4557] [4560] [4561] [4562] [18163] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4563] [4564] [4566] [4567] [18164] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4575] [18160] [18161] [18162] [18170] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8855] [4553] [5513] [5514] [18171] --1-- 1 -1-1- 1 -1--1 1 -.names [11210] [4199] [3740] [18171] [18172] ----1 1 -111- 1 -.names [15890] [4269] [4184] [18189] ---1 1 -11- 1 -.names [4370] [4260] [4175] [4183] [18190] ---1- 1 ----1 1 -11-- 1 -.names [4176] [4177] [4178] [4179] [18192] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4180] [4181] [4186] [18192] [18196] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7130] [4269] [4172] [18201] ---1 1 -11- 1 -.names [5780] [4260] [4163] [4171] [18202] ---1- 1 ----1 1 -11-- 1 -.names [4164] [4165] [4166] [4167] [18203] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4168] [4169] [4174] [18203] [18208] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [5630] [4199] [3754] [4162] [18209] ----1 1 -111- 1 -.names [4153] [4152] [18217] -1- 1 --1 1 -.names [4144] [4155] [4156] [18218] -1-- 1 --1- 1 ---1 1 -.names [7355] [15320] [4260] [4269] [18219] --11- 1 -1--1 1 -.names [4143] [4145] [4146] [4147] [18221] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4148] [4149] [4150] [4151] [18222] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4158] [18217] [18218] [18219] [18226] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4137] [4136] [18234] -1- 1 --1 1 -.names [4128] [4139] [4140] [18235] -1-- 1 --1- 1 ---1 1 -.names [8615] [14135] [4260] [4269] [18236] -1-1- 1 --1-1 1 -.names [4127] [4129] [4130] [4131] [18237] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4132] [4133] [4134] [4135] [18238] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4142] [18234] [18235] [18236] [18242] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [9530] [4123] [5513] [5514] [18244] --1-- 1 -1-1- 1 -1--1 1 -.names [10955] [4199] [3740] [18244] [18245] ----1 1 -111- 1 -.names [11240] [4199] [3754] [4043] [18253] ----1 1 -111- 1 -.names [4034] [4033] [18261] -1- 1 --1 1 -.names [4025] [4036] [4037] [18262] -1-- 1 --1- 1 ---1 1 -.names [4640] [5360] [4260] [4269] [18263] -1-1- 1 --1-1 1 -.names [4023] [4026] [4027] [4028] [18264] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4029] [4030] [4031] [4032] [18265] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4039] [18261] [18262] [18263] [18270] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4017] [4016] [18276] -1- 1 --1 1 -.names [4008] [4019] [4020] [18277] -1-- 1 --1- 1 ---1 1 -.names [4625] [16055] [4260] [4269] [18278] -1-1- 1 --1-1 1 -.names [4007] [4009] [4010] [4011] [18279] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4012] [4013] [4014] [4015] [18280] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [4022] [18276] [18277] [18278] [18286] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7565] [4003] [5513] [5514] [18287] --1-- 1 -1-1- 1 -1--1 1 -.names [11195] [4199] [3740] [18287] [18288] ----1 1 -111- 1 -.names [10430] [4199] [3754] [3926] [18291] ----1 1 -111- 1 -.names [3917] [3916] [18300] -1- 1 --1 1 -.names [3908] [3919] [3920] [18301] -1-- 1 --1- 1 ---1 1 -.names [5345] [6050] [4260] [4269] [18302] -1-1- 1 --1-1 1 -.names [3907] [3909] [3910] [3911] [18303] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3912] [3913] [3914] [3915] [18304] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3922] [18300] [18301] [18302] [18309] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [9815] [3903] [5513] [5514] [18310] --1-- 1 -1-1- 1 -1--1 1 -.names [8900] [4199] [3740] [18310] [18312] ----1 1 -111- 1 -.names [8195] [3897] [5513] [5514] [18315] --1-- 1 -1-1- 1 -1--1 1 -.names [10940] [4199] [3740] [18315] [18316] ----1 1 -111- 1 -.names [10715] [4199] [3754] [3820] [18320] ----1 1 -111- 1 -.names [3811] [3810] [18327] -1- 1 --1 1 -.names [3802] [3813] [3814] [18328] -1-- 1 --1- 1 ---1 1 -.names [6020] [15350] [4260] [4269] [18329] -1-1- 1 --1-1 1 -.names [3801] [3803] [3804] [3805] [18330] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3806] [3807] [3808] [3809] [18331] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3816] [18327] [18328] [18329] [18336] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [10655] [3797] [5513] [5514] [18338] --1-- 1 -1-1- 1 -1--1 1 -.names [5600] [4199] [3740] [18338] [18339] ----1 1 -111- 1 -.names [6260] [3791] [5513] [5514] [18342] --1-- 1 -1-1- 1 -1--1 1 -.names [6950] [4199] [3740] [18342] [18343] ----1 1 -111- 1 -.names [3689] [3688] [18353] -1- 1 --1 1 -.names [3680] [3691] [3692] [18354] -1-- 1 --1- 1 ---1 1 -.names [4655] [6710] [4260] [4269] [18355] --11- 1 -1--1 1 -.names [3679] [3681] [3682] [3683] [18356] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3684] [3685] [3686] [3687] [18357] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3694] [18353] [18354] [18355] [18362] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3673] [3672] [18369] -1- 1 --1 1 -.names [3664] [3675] [3676] [18370] -1-- 1 --1- 1 ---1 1 -.names [6695] [15710] [4260] [4269] [18372] -1-1- 1 --1-1 1 -.names [3663] [3665] [3666] [3667] [18373] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3668] [3669] [3670] [3671] [18374] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3678] [18369] [18370] [18372] [18379] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [10370] [3659] [5513] [5514] [18380] --1-- 1 -1-1- 1 -1--1 1 -.names [4895] [4199] [3740] [18380] [18381] ----1 1 -111- 1 -.names [6935] [3653] [5513] [5514] [18385] --1-- 1 -1-1- 1 -1--1 1 -.names [6275] [4199] [3740] [18385] [18386] ----1 1 -111- 1 -.names [13250] [4269] [3290] [18401] ---1 1 -11- 1 -.names [13235] [4260] [3281] [3289] [18402] ---1- 1 ----1 1 -11-- 1 -.names [3282] [3283] [3284] [3285] [18403] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3286] [3287] [3292] [18403] [18406] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7880] [4199] [3747] [3269] [18408] ----1 1 -111- 1 -.names [18408] [3266] [18414] -1- 1 --1 1 -.names [3259] [3260] [3261] [3262] [18416] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3263] [3264] [3265] [3267] [18417] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [6620] [4199] [3747] [3228] [18421] ----1 1 -111- 1 -.names [18421] [3225] [18427] -1- 1 --1 1 -.names [3218] [3219] [3220] [3221] [18429] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3222] [3223] [3224] [3226] [18430] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [5795] [4269] [3090] [18445] ---1 1 -11- 1 -.names [14360] [4260] [3081] [3089] [18446] ---1- 1 ----1 1 -11-- 1 -.names [3082] [3083] [3084] [3085] [18447] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3086] [3087] [3092] [18447] [18451] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3077] [3075] [18455] -1- 1 --1 1 -.names ppeaka_10_10_ ppeakp_9_9_ [4298] [4392] [18456] --11- 1 -1--1 1 -.names ppeaka_9_9_ [16040] [4260] [4269] [18457] -0-1- 1 --1-1 1 -.names ppeakb_9_9_ [4260] [4397] [3067] [18458] ----1 1 -01-- 1 -1-1- 1 -.names [3069] [3070] [3073] [3074] [18459] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3080] [18455] [18456] [18457] [18463] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [6485] [4269] [3024] [18470] ---1 1 -11- 1 -.names [13955] [4260] [3015] [3023] [18471] ---1- 1 ----1 1 -11-- 1 -.names [3016] [3017] [3018] [3019] [18472] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [3020] [3021] [3026] [18472] [18476] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [9890] [4199] [3754] [3014] [18477] ----1 1 -111- 1 -.names [10085] [3007] [5513] [5514] [18479] --1-- 1 -1-1- 1 -1--1 1 -.names [9575] [4199] [3740] [18479] [18481] ----1 1 -111- 1 -.names [2959] [2957] [18487] -1- 1 --1 1 -.names ppeaka_12_12_ ppeakp_11_11_ [4298] [4392] [18489] --11- 1 -1--1 1 -.names ppeakb_11_11_ [15335] [4260] [4269] [18490] -0-1- 1 --1-1 1 -.names ppeaka_11_11_ [4260] [2949] [2950] [18491] ---1- 1 ----1 1 -01-- 1 -.names [2951] [2952] [2955] [2956] [18492] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2962] [18487] [18489] [18490] [18497] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2934] [2935] [2944] [18505] -1-- 1 --1- 1 ---1 1 -.names [2936] [2937] [2938] [2939] [18507] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2933] [2940] [2941] [2945] [18508] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2942] [2943] [18505] [18508] [18511] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8840] [2929] [5513] [5514] [18512] --1-- 1 -1-1- 1 -1--1 1 -.names [11660] [4199] [3740] [18512] [18513] ----1 1 -111- 1 -.names [14915] [4199] [3747] [2882] [18517] ----1 1 -111- 1 -.names [18517] [2879] [18522] -1- 1 --1 1 -.names [2872] [2873] [2874] [2875] [18523] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2876] [2877] [2878] [2880] [18524] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2858] [2859] [2868] [18534] -1-- 1 --1- 1 ---1 1 -.names [2860] [2861] [2862] [2863] [18535] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2857] [2864] [2865] [2869] [18536] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2866] [2867] [18534] [18536] [18539] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2844] [2845] [2854] [18548] -1-- 1 --1- 1 ---1 1 -.names [2846] [2847] [2848] [2849] [18549] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2843] [2850] [2851] [2855] [18550] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2852] [2853] [18548] [18550] [18553] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [9515] [2839] [5513] [5514] [18554] --1-- 1 -1-1- 1 -1--1 1 -.names [11435] [4199] [3740] [18554] [18556] ----1 1 -111- 1 -.names [13010] [4199] [3747] [2790] [18559] ----1 1 -111- 1 -.names [18559] [2787] [18564] -1- 1 --1 1 -.names [2780] [2781] [2782] [2783] [18565] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2784] [2785] [2786] [2788] [18566] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2775] [2773] [18574] -1- 1 --1 1 -.names ppeaka_14_14_ ppeakp_13_13_ [4298] [4392] [18575] --11- 1 -1--1 1 -.names ppeakb_13_13_ [14540] [4260] [4269] [18576] -0-1- 1 --1-1 1 -.names ppeaka_13_13_ [4260] [2765] [2766] [18577] ---1- 1 ----1 1 -01-- 1 -.names [2767] [2768] [2771] [2772] [18578] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2778] [18574] [18575] [18576] [18583] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2752] [2753] [2762] [18591] -1-- 1 --1- 1 ---1 1 -.names [2754] [2755] [2756] [2757] [18592] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2751] [2758] [2759] [2763] [18593] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2760] [2761] [18591] [18593] [18598] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [9875] [4199] [3754] [2750] [18599] ----1 1 -111- 1 -.names [2741] [2740] [18607] -1- 1 --1 1 -.names [2732] [2743] [2744] [18608] -1-- 1 --1- 1 ---1 1 -.names [7970] [13040] [4260] [4269] [18609] -1-1- 1 --1-1 1 -.names [2731] [2733] [2734] [2735] [18611] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2736] [2737] [2738] [2739] [18612] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2746] [18607] [18608] [18609] [18616] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [7580] [2727] [5513] [5514] [18617] --1-- 1 -1-1- 1 -1--1 1 -.names [11675] [4199] [3740] [18617] [18619] ----1 1 -111- 1 -.names [16010] [4199] [3747] [2688] [18622] ----1 1 -111- 1 -.names [18622] [2685] [18627] -1- 1 --1 1 -.names [2678] [2679] [2680] [2681] [18628] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2682] [2683] [2684] [2686] [18629] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2673] [2671] [18637] -1- 1 --1 1 -.names ppeakp_12_12_ ppeaka_13_13_ [4298] [4392] [18638] -1-1- 1 --1-1 1 -.names ppeaka_12_12_ [14120] [4260] [4269] [18639] -0-1- 1 --1-1 1 -.names ppeakb_12_12_ [4260] [4397] [2663] [18640] ----1 1 -01-- 1 -1-1- 1 -.names [2665] [2666] [2669] [2670] [18641] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2676] [18637] [18638] [18639] [18646] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2650] [2651] [2660] [18653] -1-- 1 --1- 1 ---1 1 -.names [2652] [2653] [2654] [2655] [18654] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2649] [2656] [2657] [2661] [18655] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2658] [2659] [18653] [18655] [18658] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [10730] [4199] [3754] [2648] [18659] ----1 1 -111- 1 -.names [2639] [2638] [18666] -1- 1 --1 1 -.names [2630] [2641] [2642] [18667] -1-- 1 --1- 1 ---1 1 -.names [7340] [13385] [4260] [4269] [18668] -1-1- 1 --1-1 1 -.names [2629] [2631] [2632] [2633] [18669] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2634] [2635] [2636] [2637] [18670] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2644] [18666] [18667] [18668] [18674] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8210] [2625] [5513] [5514] [18675] --1-- 1 -1-1- 1 -1--1 1 -.names [11450] [4199] [3740] [18675] [18676] ----1 1 -111- 1 -.names [13685] [4199] [3747] [2586] [18679] ----1 1 -111- 1 -.names [18679] [2583] [18684] -1- 1 --1 1 -.names [2576] [2577] [2578] [2579] [18685] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2580] [2581] [2582] [2584] [18686] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2562] [2563] [2564] [2565] [18695] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2566] [2567] [2569] [2573] [18696] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2568] [2570] [2571] [2572] [18697] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2549] [2550] [2559] [18706] -1-- 1 --1- 1 ---1 1 -.names [2551] [2552] [2553] [2554] [18707] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2548] [2555] [2556] [2560] [18708] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2557] [2558] [18706] [18708] [18711] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [10445] [4199] [3754] [2547] [18712] ----1 1 -111- 1 -.names [8930] [4199] [3754] [2543] [18714] ----1 1 -111- 1 -.names [2534] [2533] [18721] -1- 1 --1 1 -.names [2525] [2536] [2537] [18722] -1-- 1 --1- 1 ---1 1 -.names [5330] [13025] [4260] [4269] [18723] -1-1- 1 --1-1 1 -.names [2524] [2526] [2527] [2528] [18724] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2529] [2530] [2531] [2532] [18725] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2539] [18721] [18722] [18723] [18729] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [6500] [4269] [2489] [18734] ---1 1 -11- 1 -.names [7115] [4260] [2480] [2488] [18735] ---1- 1 ----1 1 -11-- 1 -.names [2481] [2482] [2483] [2484] [18736] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2485] [2486] [2491] [18736] [18739] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2476] [2474] [18743] -1- 1 --1 1 -.names ppeaka_15_15_ ppeakp_14_14_ [4298] [4392] [18744] --11- 1 -1--1 1 -.names ppeaka_14_14_ [13370] [4260] [4269] [18745] -0-1- 1 --1-1 1 -.names ppeakb_14_14_ [4260] [4397] [2466] [18746] ----1 1 -01-- 1 -1-1- 1 -.names [2468] [2469] [2472] [2473] [18747] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2479] [18743] [18744] [18745] [18751] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2453] [2454] [2463] [18758] -1-- 1 --1- 1 ---1 1 -.names [2455] [2456] [2457] [2458] [18759] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2452] [2459] [2460] [2464] [18760] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2461] [2462] [18758] [18760] [18763] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [8285] [4199] [3754] [2451] [18764] ----1 1 -111- 1 -.names [10145] [4199] [3754] [2447] [18766] ----1 1 -111- 1 -.names [2438] [2437] [18773] -1- 1 --1 1 -.names [2429] [2440] [2441] [18774] -1-- 1 --1- 1 ---1 1 -.names [6035] [12800] [4260] [4269] [18775] -1-1- 1 --1-1 1 -.names [2428] [2430] [2431] [2432] [18776] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2433] [2434] [2435] [2436] [18777] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2443] [18773] [18774] [18775] [18781] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [17791] [17999] [18220] nen2_3 [18783] --10- 1 -0--1 1 -.names [17050] [17115] [17180] [17232] [18784] -01-- 1 ---10 1 -.names [16933] [17206] [17271] [17388] [18785] --10- 1 -1--0 1 -.names [17414] [17843] [18311] [18389] [18786] -01-- 1 ---10 1 -.names [18786] [18785] [18789] -1- 1 --1 1 -.names [4235] nrq14_8 [4488] [18784] [18790] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names nrq3_5 [18783] [18789] [18790] [18792] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [17167] nrq7_2 [3727] [18792] [18793] ----1 1 -011- 1 -.names nrq23_3 nrq14_3 [4234] [18795] -1-- 1 --1- 1 ---1 1 -.names nrq10_4 [17717] [17718] [18793] [18796] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names preset [17284] [17396] [18376] [18797] ---1- 1 -01-0 1 -.names preset nrq7_2 [17714] [18797] [18798] ----1 1 -011- 1 -.names preset nrq7_2 [17712] [17715] [18799] -011- 1 -01-1 1 -.names [2386] [2383] [18804] -1- 1 --1 1 -.names ppeakb_8_8_ [4382] [2387] [18805] ---1 1 -11- 1 -.names [7595] [13460] [4369] [4378] [18806] --11- 1 -1--1 1 -.names [6410] [11420] [4341] [4351] [18807] --11- 1 -1--1 1 -.names [2378] [2380] [2381] [2382] [18808] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2388] [2389] [18804] [18805] [18813] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2390] [18806] [18807] [18808] [18814] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names preset ppeakb_7_7_ [4242] [2375] [18815] ----1 1 -011- 1 -.names [17388] preset [18816] -00 1 -.names [2366] [2363] [18819] -1- 1 --1 1 -.names ppeakb_9_9_ [4382] [2367] [18820] ---1 1 -11- 1 -.names [10685] [13820] [4369] [4378] [18821] --11- 1 -1--1 1 -.names [5720] [11645] [4341] [4351] [18822] --11- 1 -1--1 1 -.names [2358] [2360] [2361] [2362] [18823] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2368] [2369] [18819] [18820] [18828] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2370] [18821] [18822] [18823] [18829] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names preset ppeakb_8_8_ [4242] [2355] [18830] ----1 1 -011- 1 -.names preset ppeakb_5_5_ [4242] [2352] [18832] ----1 1 -011- 1 -.names preset ppeakb_6_6_ [4242] [2345] [18833] ----1 1 -011- 1 -.names preset ppeakb_15_15_ [4242] [2342] [18834] ----1 1 -011- 1 -.names [17050] preset [18835] -00 1 -.names preset ppeakb_3_3_ [4242] [2337] [18836] ----1 1 -011- 1 -.names [17232] preset [18837] -00 1 -.names preset ppeakb_4_4_ [4242] [2330] [18838] ----1 1 -011- 1 -.names [17271] preset [18839] -00 1 -.names preset ppeakb_1_1_ [4242] [2325] [18842] ----1 1 -011- 1 -.names [18376] preset [18843] -00 1 -.names preset ppeakb_2_2_ [4242] [2320] [18845] ----1 1 -011- 1 -.names [2311] [2308] [18851] -1- 1 --1 1 -.names ppeakb_11_11_ [4382] [2312] [18852] ---1 1 -11- 1 -.names [10115] [13115] [4369] [4378] [18853] --11- 1 -1--1 1 -.names [4295] [16100] [4341] [4351] [18854] --11- 1 -1--1 1 -.names [2303] [2305] [2306] [2307] [18855] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2313] [2314] [18851] [18852] [18860] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2315] [18853] [18854] [18855] [18862] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2294] [2291] [18865] -1- 1 --1 1 -.names ppeakb_10_10_ [4382] [2295] [18866] ---1 1 -11- 1 -.names [10400] [12860] [4369] [4378] [18867] --11- 1 -1--1 1 -.names [5015] [10925] [4341] [4351] [18868] --11- 1 -1--1 1 -.names [2286] [2288] [2289] [2290] [18869] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2296] [2297] [18865] [18866] [18874] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2298] [18867] [18868] [18869] [18875] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names preset ppeakb_13_13_ [4242] [2281] [18876] ----1 1 -011- 1 -.names [2268] [2265] [18880] -1- 1 --1 1 -.names ppeakb_13_13_ [4382] [2269] [18881] ---1 1 -11- 1 -.names [8885] [12620] [4369] [4378] [18882] --11- 1 -1--1 1 -.names [13805] [15500] [4341] [4351] [18883] -1-1- 1 --1-1 1 -.names [2260] [2262] [2263] [2264] [18884] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2270] [2271] [18880] [18881] [18889] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2272] [18882] [18883] [18884] [18890] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names ppeaki_13_13_ ppeaki_12_12_ [4292] [18891] ---0 1 -00- 1 -.names ppeaki_15_15_ ppeaki_14_14_ [4292] [18892] ---0 1 -00- 1 -.names ppeaki_15_15_ ppeaki_14_14_ [4292] [18891] [18897] ---01 1 -00-1 1 -.names [1427] [1342] [1353] [1439] [18898] -0000 1 -.names [1368] [1386] [1398] [1413] [18899] -0000 1 -.names [18891] [18892] [18898] [18900] -111 1 -.names [18636] nrq7_2 [17582] [18899] [18901] -1--1 1 --011 1 -.names [17986] [17596] [18902] -11 1 -.names [17804] [17986] [18597] [2255] [18904] -1--- 1 ----1 1 --11- 1 -.names preset [17596] [18597] [18905] -010 1 -.names preset [17596] [4513] [18906] -001 1 -.names [2239] [2236] [18909] -1- 1 --1 1 -.names ppeakb_12_12_ [4382] [2240] [18910] ---1 1 -11- 1 -.names [9845] [12395] [4369] [4378] [18911] --11- 1 -1--1 1 -.names [15755] [15845] [4341] [4351] [18912] -1-1- 1 --1-1 1 -.names [2231] [2233] [2234] [2235] [18914] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2241] [2242] [18909] [18910] [18919] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2243] [18911] [18912] [18914] [18920] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2218] [2215] [18923] -1- 1 --1 1 -.names ppeakb_15_15_ [4382] [2219] [18924] ---1 1 -11- 1 -.names [4880] [15050] [4369] [4378] [18925] --11- 1 -1--1 1 -.names [13550] [14615] [4341] [4351] [18926] --11- 1 -1--1 1 -.names [2210] [2212] [2213] [2214] [18927] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2220] [2221] [18923] [18924] [18932] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2222] [18925] [18926] [18927] [18933] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2201] [2198] [18936] -1- 1 --1 1 -.names ppeakb_14_14_ [4382] [2202] [18937] ---1 1 -11- 1 -.names [9560] [15410] [4369] [4378] [18938] --11- 1 -1--1 1 -.names [13445] [15140] [4341] [4351] [18939] -1-1- 1 --1-1 1 -.names [2193] [2195] [2196] [2197] [18940] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2203] [2204] [18936] [18937] [18945] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2205] [18938] [18939] [18940] [18946] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names preset ppeakb_9_9_ [4242] [2188] [18947] ----1 1 -011- 1 -.names preset ppeakb_14_14_ [4242] [2185] [18948] ----1 1 -011- 1 -.names [17050] [17115] [17180] [17232] [18951] -01-- 1 ---10 1 -.names [17206] [17232] [17271] [18441] [18952] -1-0- 1 --1-0 1 -.names [17427] [17518] [17583] [18077] [18953] -01-- 1 ---10 1 -.names [17050] [17219] [17271] [17349] [18954] -10-- 1 ---10 1 -.names [4235] [4488] [18951] [18952] [18958] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [18953] [18954] [18958] [18959] -1-- 1 --1- 1 ---1 1 -.names [4235] preset [18960] -10 1 -.names pwr_0_0_ preset [18961] -10 1 -.names [4234] [18959] [18960] [18961] [18962] -1-1- 1 --11- 1 -00-1 1 -.names preset nrq13_4 [4234] [18959] [18963] -0-1- 1 -01-1 1 -.names [17058] [17240] [4234] [18959] [18964] -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names [16933] [17388] [17414] [17843] [18966] -10-- 1 ---01 1 -.names [18311] [18363] [18389] [18415] [18967] -1-0- 1 --1-0 1 -.names [17453] [17791] [17843] [18246] [18968] --10- 1 -1--0 1 -.names [17102] [17154] [17167] [17362] [18969] -10-- 1 ---10 1 -.names [17310] [17388] [17414] [17505] [18970] -01-- 1 ---10 1 -.names [18142] [18220] [18311] [18506] [18971] -01-- 1 ---01 1 -.names [17570] [17635] [18285] [18363] [18972] -10-- 1 ---10 1 -.names [18415] [18428] [18480] [18493] [18973] -1-0- 1 --0-1 1 -.names [16985] [18298] [18376] [18389] [18974] --01- 1 -0--1 1 -.names [16920] [16972] [17297] [17375] [18975] -10-- 1 ---10 1 -.names [4488] [18966] [18975] [18981] -1-- 1 --1- 1 ---1 1 -.names [18967] [18968] [18969] [18970] [18982] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [18971] [18972] [18973] [18974] [18983] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [18981] [18982] [18983] [18985] -1-- 1 --1- 1 ---1 1 -.names nrq3_5 [18783] [18985] [18986] -1-- 1 --1- 1 ---1 1 -.names [17167] nrq7_2 [3727] [18986] [18987] ----1 1 -011- 1 -.names nrq10_4 nrq23_3 nrq14_3 [18987] [18989] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names preset nrq3_5 [18783] [18990] -01- 1 -0-1 1 -.names prd_0_0_ preset [18991] -10 1 -.names [4265] [18989] [18990] [18991] [18992] -1-1- 1 --11- 1 -00-1 1 -.names [4243] [4245] [4265] [18989] [18993] -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names [18423] [4241] [4265] [18989] [18994] -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names [17422] [18397] [4265] [18989] [18995] -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names [17110] [17175] [4265] [18989] [18996] -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names [18992] [18993] [18996] [18999] -1-- 1 --1- 1 ---1 1 -.names preset ppeakb_10_10_ [4242] [2117] [19000] ----1 1 -011- 1 -.names preset ppeakb_12_12_ [4242] [2108] [19001] ----1 1 -011- 1 -.names [18129] preset [19003] -10 1 -.names preset ppeakb_11_11_ [4242] [2077] [19004] ----1 1 -011- 1 -.names [2064] [2063] [19009] -1- 1 --1 1 -.names ppeakb_0_0_ [10670] [4378] [4382] [19010] --11- 1 -1--1 1 -.names [4310] [12605] [4351] [4369] [19011] -1-1- 1 --1-1 1 -.names [11630] [4341] [2055] [2068] [19012] ---1- 1 ----1 1 -11-- 1 -.names [2057] [2058] [2059] [2060] [19013] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2065] [2066] [19009] [19010] [19018] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2067] [19011] [19012] [19013] [19019] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [18415] preset [19022] -00 1 -.names [2045] [2041] [19028] -1- 1 --1 1 -.names ppeakb_1_1_ [9830] [4378] [4382] [19029] --11- 1 -1--1 1 -.names [5030] [12380] [4351] [4369] [19030] -1-1- 1 --1-1 1 -.names [9485] [4341] [2032] [2034] [19031] ---1- 1 ----1 1 -11-- 1 -.names [2035] [2036] [2037] [2040] [19032] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2042] [2043] [19028] [19029] [19037] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2044] [19030] [19031] [19032] [19038] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names preset ppeakb_0_0_ [4242] [2029] [19039] ----1 1 -011- 1 -.names [2018] [2015] [19042] -1- 1 --1 1 -.names ppeakb_2_2_ [4382] [2019] [19043] ---1 1 -11- 1 -.names [10100] [13100] [4369] [4378] [19044] --11- 1 -1--1 1 -.names [7535] [15515] [4341] [4351] [19045] -1-1- 1 --1-1 1 -.names [2010] [2012] [2013] [2014] [19046] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2020] [2021] [19042] [19043] [19051] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2022] [19044] [19045] [19046] [19052] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2003] [2000] [19057] -1- 1 --1 1 -.names ppeakb_3_3_ [4382] [2004] [19058] ---1 1 -11- 1 -.names [5570] [12845] [4369] [4378] [19059] --11- 1 -1--1 1 -.names [8165] [15860] [4341] [4351] [19062] -1-1- 1 --1-1 1 -.names [1995] [1997] [1998] [1999] [19063] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2005] [2006] [19057] [19058] [19074] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [2007] [19059] [19062] [19063] [19075] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names preset pdn [17700] [19076] -001 1 -.names [1984] [1981] [19080] -1- 1 --1 1 -.names ppeakb_4_4_ [4382] [1985] [19081] ---1 1 -11- 1 -.names [4865] [15035] [4369] [4378] [19083] --11- 1 -1--1 1 -.names [6230] [14765] [4341] [4351] [19084] -1-1- 1 --1-1 1 -.names [1976] [1978] [1979] [1980] [19085] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [1986] [1987] [19080] [19081] [19094] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [1988] [19083] [19084] [19085] [19095] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [1969] [1966] [19100] -1- 1 --1 1 -.names ppeakb_5_5_ [4382] [1970] [19101] ---1 1 -11- 1 -.names [9545] [15395] [4369] [4378] [19102] --11- 1 -1--1 1 -.names [6905] [8330] [4341] [4351] [19104] -1-1- 1 --1-1 1 -.names [1961] [1963] [1964] [1965] [19105] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [1971] [1972] [19100] [19101] [19110] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names [1973] 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b/fpga_flow/benchmarks/Blif/MCNC_big20/s298.blif deleted file mode 100644 index 8acf0c347..000000000 --- a/fpga_flow/benchmarks/Blif/MCNC_big20/s298.blif +++ /dev/null @@ -1,308 +0,0 @@ -.model s298.bench -.inputs G0 G1 G2 -.outputs G117 G132 G66 G118 G133 G67 -.wire_load_slope 0.00 -.latch G29 G10 0 -.latch G30 G11 0 -.latch G34 G12 0 -.latch G39 G13 0 -.latch G44 G14 0 -.latch G56 G15 0 -.latch G86 G16 0 -.latch G92 G17 0 -.latch G98 G18 0 -.latch G102 G19 0 -.latch G107 G20 0 -.latch G113 G21 0 -.latch G119 G22 0 -.latch G125 G23 0 -.names II210 G117 -0 1 -.names II235 G132 -0 1 -.names II155 G66 -0 1 -.names II213 G118 -0 1 -.names II238 G133 -0 1 -.names II158 G67 -0 1 -.names G10 G130 G29 -00 1 -.names G31 G32 G33 G130 G30 -0000 1 -.names G35 G36 G37 G130 G34 -0000 1 -.names G42 G43 G39 -00 1 -.names G48 G49 G53 G44 -000 1 -.names G57 G58 G130 G56 -000 1 -.names G88 G89 G90 G112 G86 -0000 1 -.names G94 G95 G97 G92 -000 1 -.names G100 G101 G98 -00 1 -.names G105 G106 G102 -00 1 -.names G110 G111 G107 -00 1 -.names G115 G116 G113 -00 1 -.names G122 G123 G130 G119 -000 1 -.names G128 G129 G130 G125 -000 1 -.names II229 G130 -0 1 -.names G130 G28 -0 1 -.names G10 G38 -0 1 -.names G13 G40 -0 1 -.names G12 G45 -0 1 -.names G11 G46 -0 1 -.names G14 G50 -0 1 -.names G23 G51 -0 1 -.names G11 G54 -0 1 -.names G13 G55 -0 1 -.names G12 G59 -0 1 -.names G22 G60 -0 1 -.names G15 G64 -0 1 -.names G16 II155 -0 1 -.names G17 II158 -0 1 -.names G10 G76 -0 1 -.names G11 G82 -0 1 -.names G16 G87 -0 1 -.names G12 G91 -0 1 -.names G17 G93 -0 1 -.names G14 G96 -0 1 -.names G18 G99 -0 1 -.names G13 G103 -0 1 -.names G62 G63 G112 -00 1 -.names G112 G108 -0 1 -.names G21 G114 -0 1 -.names G18 II210 -0 1 -.names G19 II213 -0 1 -.names II221 G124 -0 1 -.names G124 G120 -0 1 -.names G22 G121 -0 1 -.names G2 II221 -0 1 -.names II232 G131 -0 1 -.names G131 G126 -0 1 -.names G23 G127 -0 1 -.names G0 II229 -0 1 -.names G1 II232 -0 1 -.names G20 II235 -0 1 -.names G21 II238 -0 1 -.names G28 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G108 G109 G110 -11 1 -.names G10 G112 G111 -11 1 -.names G114 G14 G115 -11 1 -.names G120 G121 G122 -11 1 -.names G124 G22 G123 -11 1 -.names G126 G127 G128 -11 1 -.names G131 G23 G129 -11 1 -.names G38 G46 G45 G40 G24 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names G38 G11 G12 G25 -1-- 1 --1- 1 ---1 1 -.names G11 G12 G13 G96 G68 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names G103 G18 G69 -1- 1 --1 1 -.names G103 G14 G70 -1- 1 --1 1 -.names G82 G12 G13 G71 -1-- 1 --1- 1 ---1 1 -.names G91 G20 G72 -1- 1 --1 1 -.names G103 G20 G73 -1- 1 --1 1 -.names G112 G103 G96 G19 G77 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names G108 G76 G78 -1- 1 --1 1 -.names G103 G14 G79 -1- 1 --1 1 -.names G11 G14 G80 -1- 1 --1 1 -.names G12 G13 G81 -1- 1 --1 1 -.names G11 G12 G13 G96 G83 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names G82 G91 G14 G84 -1-- 1 --1- 1 ---1 1 -.names G91 G96 G17 G85 -1-- 1 --1- 1 ---1 1 -.names G24 G25 G28 G43 -0-- 1 --0- 1 ---0 1 -.names G83 G84 G85 G108 G97 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G68 G69 G70 G108 G101 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G77 G78 G106 -0- 1 --0 1 -.names G79 G80 G81 G108 G116 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names G26 G27 G53 -00 1 -.end diff --git a/fpga_flow/benchmarks/Blif/MCNC_big20/s38417.blif b/fpga_flow/benchmarks/Blif/MCNC_big20/s38417.blif deleted file mode 100644 index 40f97eab7..000000000 --- a/fpga_flow/benchmarks/Blif/MCNC_big20/s38417.blif +++ /dev/null @@ -1,15102 +0,0 @@ -.model TOP -.inputs Pg3234 Pg3233 Pg3232 Pg3231 Pg3230 Pg3229 Pg3228 Pg3227 Pg3226 Pg3225 \ -Pg3224 Pg3223 Pg3222 Pg3221 Pg3220 Pg3219 Pg3218 Pg3217 Pg3216 Pg3215 Pg3214 \ -Pg3213 Pg3212 Pg2637 Pg1943 Pg1249 Pg563 Pg51 PCLK -.outputs Pg27380 Pg26149 Pg26135 Pg26104 Pg25489 Pg25442 Pg25435 Pg25420 \ -Pg24734 Pg16496 Pg16437 Pg16399 Pg16355 Pg16297 Pg8275 Pg8274 Pg8273 Pg8272 \ -Pg8271 Pg8270 Pg8269 Pg8268 Pg8267 Pg8266 Pg8265 Pg8264 Pg8263 Pg8262 Pg8261 \ -Pg8260 Pg8259 Pg8258 Pg8251 Pg8249 Pg8175 Pg8167 Pg8106 Pg8096 Pg8087 Pg8082 \ -Pg8030 Pg8023 Pg8021 Pg8012 Pg8007 Pg7961 Pg7956 Pg7909 Pg7519 Pg7487 Pg7425 \ -Pg7390 Pg7357 Pg7334 Pg7302 Pg7264 Pg7229 Pg7194 Pg7161 Pg7084 Pg7052 Pg7014 \ -Pg6979 Pg6944 Pg6911 Pg6895 Pg6837 Pg6782 Pg6750 Pg6712 Pg6677 Pg6642 Pg6573 \ -Pg6518 Pg6485 Pg6447 Pg6442 Pg6368 Pg6313 Pg6231 Pg6225 Pg5796 Pg5747 Pg5738 \ -Pg5695 Pg5686 Pg5657 Pg5648 Pg5637 Pg5629 Pg5612 Pg5595 Pg5555 Pg5549 Pg5511 \ -Pg5472 Pg5437 Pg5388 Pg4590 Pg4450 Pg4323 Pg4321 Pg4200 Pg4090 Pg4088 Pg3993 -.latch Pg51 Pg8021 re PCLK 2 -.latch Ng20571 Ng2817 re PCLK 2 -.latch Ng20588 Ng2933 re PCLK 2 -.latch Ng21951 Ng13457 re PCLK 2 -.latch Ng23315 Ng2883 re PCLK 2 -.latch Ng24423 Ng2888 re PCLK 2 -.latch Ng25175 Ng2896 re PCLK 2 -.latch Ng26019 Ng2892 re PCLK 2 -.latch Ng26747 Ng2903 re PCLK 2 -.latch Ng27237 Ng2900 re PCLK 2 -.latch Ng27715 Ng2908 re PCLK 2 -.latch Ng24424 Ng2912 re PCLK 2 -.latch Ng25174 Ng2917 re PCLK 2 -.latch Ng26020 Ng2924 re PCLK 2 -.latch Ng26746 Ng2920 re PCLK 2 -.latch Ng19061 Ng2984 re PCLK 2 -.latch Ng19060 Ng2985 re PCLK 2 -.latch Pg8021 Ng2929 re PCLK 2 -.latch Ng16494 Ng2879 re PCLK 2 -.latch Pg3212 Ng2934 re PCLK 2 -.latch Pg3228 Ng2935 re PCLK 2 -.latch Pg3227 Ng2938 re PCLK 2 -.latch Pg3226 Ng2941 re PCLK 2 -.latch Pg3225 Ng2944 re PCLK 2 -.latch Pg3224 Ng2947 re PCLK 2 -.latch Pg3223 Ng2953 re PCLK 2 -.latch Pg3222 Ng2956 re PCLK 2 -.latch Pg3221 Ng2959 re PCLK 2 -.latch Pg3232 Ng2962 re PCLK 2 -.latch Pg3220 Ng2963 re PCLK 2 -.latch Pg3219 Ng2966 re PCLK 2 -.latch Pg3218 Ng2969 re PCLK 2 -.latch Pg3217 Ng2972 re PCLK 2 -.latch Pg3216 Ng2975 re PCLK 2 -.latch Pg3215 Ng2978 re PCLK 2 -.latch Pg3214 Ng2981 re PCLK 2 -.latch Pg3213 Ng2874 re PCLK 2 -.latch Ng20572 Ng1506 re PCLK 2 -.latch Ng20573 Ng1501 re PCLK 2 -.latch Ng20574 Ng1496 re PCLK 2 -.latch Ng20575 Ng1491 re PCLK 2 -.latch Ng20576 Ng1486 re PCLK 2 -.latch Ng20577 Ng1481 re PCLK 2 -.latch Ng20578 Ng1476 re PCLK 2 -.latch Ng20579 Ng1471 re PCLK 2 -.latch Ng23313 Ng13439 re PCLK 2 -.latch Ng21960 Pg8251 re PCLK 2 -.latch Pg8251 Ng813 re PCLK 2 -.latch Ng21961 Pg4090 re PCLK 2 -.latch Pg4090 Ng809 re PCLK 2 -.latch Ng21962 Pg4323 re PCLK 2 -.latch Pg4323 Ng805 re PCLK 2 -.latch Ng21963 Pg4590 re PCLK 2 -.latch Pg4590 Ng801 re PCLK 2 -.latch Ng21947 Pg6225 re PCLK 2 -.latch Pg6225 Ng797 re PCLK 2 -.latch Ng21948 Pg6442 re PCLK 2 -.latch Pg6442 Ng793 re PCLK 2 -.latch Ng21949 Pg6895 re PCLK 2 -.latch Pg6895 Ng789 re PCLK 2 -.latch Ng21950 Pg7334 re PCLK 2 -.latch Pg7334 Ng785 re PCLK 2 -.latch Ng23312 Pg7519 re PCLK 2 -.latch Pg7519 Ng13423 re PCLK 2 -.latch Ng21952 Pg8249 re PCLK 2 -.latch Pg8249 Ng125 re PCLK 2 -.latch Ng21953 Pg4088 re PCLK 2 -.latch Pg4088 Ng121 re PCLK 2 -.latch Ng21954 Pg4321 re PCLK 2 -.latch Pg4321 Ng117 re PCLK 2 -.latch Ng21955 Pg8023 re PCLK 2 -.latch Pg8023 Ng113 re PCLK 2 -.latch Ng21956 Pg8175 re PCLK 2 -.latch Pg8175 Ng109 re PCLK 2 -.latch Ng21957 Pg3993 re PCLK 2 -.latch Pg3993 Ng105 re PCLK 2 -.latch Ng21958 Pg4200 re PCLK 2 -.latch Pg4200 Ng101 re PCLK 2 -.latch Ng21959 Pg4450 re PCLK 2 -.latch Pg4450 Ng97 re PCLK 2 -.latch Ng23316 Pg8096 re PCLK 2 -.latch Pg8096 Ng13407 re PCLK 2 -.latch Ng20587 Ng2200 re PCLK 2 -.latch Ng20585 Ng2195 re PCLK 2 -.latch Ng20586 Ng2190 re PCLK 2 -.latch Ng20584 Ng2185 re PCLK 2 -.latch Ng20583 Ng2180 re PCLK 2 -.latch Ng20582 Ng2175 re PCLK 2 -.latch Ng20581 Ng2170 re PCLK 2 -.latch Ng20580 Ng2165 re PCLK 2 -.latch Ng23314 Ng13455 re PCLK 2 -.latch Ng20630 Ng3210 re PCLK 2 -.latch Ng20631 Ng3211 re PCLK 2 -.latch Ng20632 Ng3084 re PCLK 2 -.latch Ng20609 Ng3085 re PCLK 2 -.latch Ng20610 Ng3086 re PCLK 2 -.latch Ng20611 Ng3087 re PCLK 2 -.latch Ng20612 Ng3091 re PCLK 2 -.latch Ng20613 Ng3092 re PCLK 2 -.latch Ng20614 Ng3093 re PCLK 2 -.latch Ng20615 Ng3094 re PCLK 2 -.latch Ng20616 Ng3095 re PCLK 2 -.latch Ng20617 Ng3096 re PCLK 2 -.latch Ng26751 Ng3097 re PCLK 2 -.latch Ng26752 Ng3098 re PCLK 2 -.latch Ng26753 Ng3099 re PCLK 2 -.latch Ng29163 Ng3100 re PCLK 2 -.latch Ng29164 Ng3101 re PCLK 2 -.latch Ng29165 Ng3102 re PCLK 2 -.latch Ng30120 Ng3103 re PCLK 2 -.latch Ng30121 Ng3104 re PCLK 2 -.latch Ng30122 Ng3105 re PCLK 2 -.latch Ng30941 Ng3106 re PCLK 2 -.latch Ng30942 Ng3107 re PCLK 2 -.latch Ng30943 Ng3108 re PCLK 2 -.latch Ng20618 Ng3155 re PCLK 2 -.latch Ng20619 Ng3158 re PCLK 2 -.latch Ng20620 Ng3161 re PCLK 2 -.latch Ng20621 Ng3164 re PCLK 2 -.latch Ng20622 Ng3167 re PCLK 2 -.latch Ng20623 Ng3170 re PCLK 2 -.latch Ng20624 Ng3173 re PCLK 2 -.latch Ng20625 Ng3176 re PCLK 2 -.latch Ng20626 Ng3179 re PCLK 2 -.latch Ng20627 Ng3182 re PCLK 2 -.latch Ng20628 Ng3185 re PCLK 2 -.latch Ng20629 Ng3088 re PCLK 2 -.latch Pg24734 Ng3191 re PCLK 2 -.latch Ng29166 Ng3128 re PCLK 2 -.latch [1521] Ng3126 re PCLK 2 -.latch Ng28696 Ng3125 re PCLK 2 -.latch Ng28313 Ng3123 re PCLK 2 -.latch Pg26104 Ng3120 re PCLK 2 -.latch Pg25435 Ng3110 re PCLK 2 -.latch Pg27380 Ng3139 re PCLK 2 -.latch Pg26149 Ng3135 re PCLK 2 -.latch Pg26135 Ng3147 re PCLK 2 -.latch Ng29656 Ng185 re PCLK 2 -.latch Ng24259 Ng130 re PCLK 2 -.latch Ng24260 Ng131 re PCLK 2 -.latch Ng24261 Ng129 re PCLK 2 -.latch Ng24262 Ng133 re PCLK 2 -.latch Ng24263 Ng134 re PCLK 2 -.latch Ng24264 Ng132 re PCLK 2 -.latch Ng24265 Ng142 re PCLK 2 -.latch Ng24266 Ng143 re PCLK 2 -.latch Ng24267 Ng141 re PCLK 2 -.latch Ng24268 Ng145 re PCLK 2 -.latch Ng24269 Ng146 re PCLK 2 -.latch Ng24270 Ng144 re PCLK 2 -.latch Ng24271 Ng148 re PCLK 2 -.latch Ng24272 Ng149 re PCLK 2 -.latch Ng24273 Ng147 re PCLK 2 -.latch Ng24274 Ng151 re PCLK 2 -.latch Ng24275 Ng152 re PCLK 2 -.latch Ng24276 Ng150 re PCLK 2 -.latch Ng24277 Ng154 re PCLK 2 -.latch Ng24278 Ng155 re PCLK 2 -.latch Ng24279 Ng153 re PCLK 2 -.latch Ng24280 Ng157 re PCLK 2 -.latch Ng24281 Ng158 re PCLK 2 -.latch Ng24282 Ng156 re PCLK 2 -.latch Ng24283 Ng160 re PCLK 2 -.latch Ng24284 Ng161 re PCLK 2 -.latch Ng24285 Ng159 re PCLK 2 -.latch Ng24286 Ng163 re PCLK 2 -.latch Ng24287 Ng164 re PCLK 2 -.latch Ng24288 Ng162 re PCLK 2 -.latch Ng26679 Ng169 re PCLK 2 -.latch Ng26680 Ng170 re PCLK 2 -.latch Ng26681 Ng168 re PCLK 2 -.latch Ng26682 Ng172 re PCLK 2 -.latch Ng26683 Ng173 re PCLK 2 -.latch Ng26684 Ng171 re PCLK 2 -.latch Ng26685 Ng175 re PCLK 2 -.latch Ng26686 Ng176 re PCLK 2 -.latch Ng26687 Ng174 re PCLK 2 -.latch Ng26688 Ng178 re PCLK 2 -.latch Ng26689 Ng179 re PCLK 2 -.latch Ng26690 Ng177 re PCLK 2 -.latch Ng30506 Ng186 re PCLK 2 -.latch Ng30507 Ng189 re PCLK 2 -.latch Ng30508 Ng192 re PCLK 2 -.latch Ng30842 Ng231 re PCLK 2 -.latch Ng30843 Ng234 re PCLK 2 -.latch Ng30844 Ng237 re PCLK 2 -.latch Ng30836 Ng195 re PCLK 2 -.latch Ng30837 Ng198 re PCLK 2 -.latch Ng30838 Ng201 re PCLK 2 -.latch Ng30845 Ng240 re PCLK 2 -.latch Ng30846 Ng243 re PCLK 2 -.latch Ng30847 Ng246 re PCLK 2 -.latch Ng30509 Ng204 re PCLK 2 -.latch Ng30510 Ng207 re PCLK 2 -.latch Ng30511 Ng210 re PCLK 2 -.latch Ng30515 Ng249 re PCLK 2 -.latch Ng30516 Ng252 re PCLK 2 -.latch Ng30517 Ng255 re PCLK 2 -.latch Ng30512 Ng213 re PCLK 2 -.latch Ng30513 Ng216 re PCLK 2 -.latch Ng30514 Ng219 re PCLK 2 -.latch Ng30518 Ng258 re PCLK 2 -.latch Ng30519 Ng261 re PCLK 2 -.latch Ng30520 Ng264 re PCLK 2 -.latch Ng30839 Ng222 re PCLK 2 -.latch Ng30840 Ng225 re PCLK 2 -.latch Ng30841 Ng228 re PCLK 2 -.latch Ng30848 Ng267 re PCLK 2 -.latch Ng30849 Ng270 re PCLK 2 -.latch Ng30850 Ng273 re PCLK 2 -.latch Ng25983 Ng92 re PCLK 2 -.latch Ng26678 Ng88 re PCLK 2 -.latch Ng27189 Ng83 re PCLK 2 -.latch Ng27683 Ng79 re PCLK 2 -.latch Ng28206 Ng74 re PCLK 2 -.latch Ng28673 Ng70 re PCLK 2 -.latch Ng29131 Ng65 re PCLK 2 -.latch Ng29413 Ng61 re PCLK 2 -.latch Ng29627 Ng56 re PCLK 2 -.latch Ng29794 Ng52 re PCLK 2 -.latch Ng28207 Ng11497 re PCLK 2 -.latch Ng28208 Ng11498 re PCLK 2 -.latch Ng28209 Ng11499 re PCLK 2 -.latch Ng28210 Ng11500 re PCLK 2 -.latch Ng28211 Ng11501 re PCLK 2 -.latch Ng28212 Ng11502 re PCLK 2 -.latch Ng28213 Ng11503 re PCLK 2 -.latch Ng28214 Ng11504 re PCLK 2 -.latch Ng28215 Ng11505 re PCLK 2 -.latch Ng28216 Ng11506 re PCLK 2 -.latch Ng28217 Ng11507 re PCLK 2 -.latch Ng28218 Ng11508 re PCLK 2 -.latch Ng29414 Ng408 re PCLK 2 -.latch Ng29415 Ng411 re PCLK 2 -.latch Ng29416 Ng414 re PCLK 2 -.latch Ng29631 Ng417 re PCLK 2 -.latch Ng29632 Ng420 re PCLK 2 -.latch Ng29633 Ng423 re PCLK 2 -.latch Ng29417 Ng427 re PCLK 2 -.latch Ng29418 Ng428 re PCLK 2 -.latch Ng29419 Ng426 re PCLK 2 -.latch Ng27684 Ng429 re PCLK 2 -.latch Ng27685 Ng432 re PCLK 2 -.latch Ng27686 Ng435 re PCLK 2 -.latch Ng27687 Ng438 re PCLK 2 -.latch Ng27688 Ng441 re PCLK 2 -.latch Ng27689 Ng444 re PCLK 2 -.latch Ng28674 Ng448 re PCLK 2 -.latch Ng28675 Ng449 re PCLK 2 -.latch Ng28676 Ng447 re PCLK 2 -.latch Ng29795 Ng312 re PCLK 2 -.latch Ng29796 Ng313 re PCLK 2 -.latch Ng29797 Ng314 re PCLK 2 -.latch Ng30851 Ng315 re PCLK 2 -.latch Ng30852 Ng316 re PCLK 2 -.latch Ng30853 Ng317 re PCLK 2 -.latch Ng30710 Ng318 re PCLK 2 -.latch Ng30711 Ng319 re PCLK 2 -.latch Ng30712 Ng320 re PCLK 2 -.latch Ng29628 Ng322 re PCLK 2 -.latch Ng29629 Ng323 re PCLK 2 -.latch Ng29630 Ng321 re PCLK 2 -.latch Ng27191 Ng403 re PCLK 2 -.latch Ng27192 Ng404 re PCLK 2 -.latch Ng27193 Ng402 re PCLK 2 -.latch Ng11509 Ng450 re PCLK 2 -.latch Ng450 Ng451 re PCLK 2 -.latch Ng11510 Ng452 re PCLK 2 -.latch Ng452 Ng453 re PCLK 2 -.latch Ng11511 Ng454 re PCLK 2 -.latch Ng454 Ng279 re PCLK 2 -.latch Ng11491 Ng280 re PCLK 2 -.latch Ng280 Ng281 re PCLK 2 -.latch Ng11492 Ng282 re PCLK 2 -.latch Ng282 Ng283 re PCLK 2 -.latch Ng11493 Ng284 re PCLK 2 -.latch Ng284 Ng285 re PCLK 2 -.latch Ng11494 Ng286 re PCLK 2 -.latch Ng286 Ng287 re PCLK 2 -.latch Ng11495 Ng288 re PCLK 2 -.latch Ng288 Ng289 re PCLK 2 -.latch Ng13407 Ng290 re PCLK 2 -.latch Ng290 Ng291 re PCLK 2 -.latch Ng19012 Ng299 re PCLK 2 -.latch Ng23148 Ng305 re PCLK 2 -.latch Ng27190 Ng298 re PCLK 2 -.latch Ng11497 Ng342 re PCLK 2 -.latch Ng342 Ng349 re PCLK 2 -.latch Ng11498 Ng350 re PCLK 2 -.latch Ng350 Ng351 re PCLK 2 -.latch Ng11499 Ng352 re PCLK 2 -.latch Ng352 Ng353 re PCLK 2 -.latch Ng11500 Ng357 re PCLK 2 -.latch Ng357 Ng364 re PCLK 2 -.latch Ng11501 Ng365 re PCLK 2 -.latch Ng365 Ng366 re PCLK 2 -.latch Ng11502 Ng367 re PCLK 2 -.latch Ng367 Ng368 re PCLK 2 -.latch Ng11503 Ng372 re PCLK 2 -.latch Ng372 Ng379 re PCLK 2 -.latch Ng11504 Ng380 re PCLK 2 -.latch Ng380 Ng381 re PCLK 2 -.latch Ng11505 Ng382 re PCLK 2 -.latch Ng382 Ng383 re PCLK 2 -.latch Ng11506 Ng387 re PCLK 2 -.latch Ng387 Ng394 re PCLK 2 -.latch Ng11507 Ng395 re PCLK 2 -.latch Ng395 Ng396 re PCLK 2 -.latch Ng11508 Ng397 re PCLK 2 -.latch Ng397 Ng324 re PCLK 2 -.latch Ng23160 Ng554 re PCLK 2 -.latch Ng20556 Ng557 re PCLK 2 -.latch Ng20557 Ng510 re PCLK 2 -.latch Ng16467 Ng513 re PCLK 2 -.latch Ng513 Ng523 re PCLK 2 -.latch Ng523 Ng524 re PCLK 2 -.latch Ng11512 Ng564 re PCLK 2 -.latch Ng564 Ng569 re PCLK 2 -.latch Ng11515 Ng570 re PCLK 2 -.latch Ng570 Ng571 re PCLK 2 -.latch Ng11516 Ng572 re PCLK 2 -.latch Ng572 Ng573 re PCLK 2 -.latch Ng11517 Ng574 re PCLK 2 -.latch Ng574 Ng565 re PCLK 2 -.latch Ng11513 Ng566 re PCLK 2 -.latch Ng566 Ng567 re PCLK 2 -.latch Ng11514 Ng568 re PCLK 2 -.latch Ng568 Ng489 re PCLK 2 -.latch Ng24292 Ng486 re PCLK 2 -.latch Ng24293 Ng487 re PCLK 2 -.latch Ng24294 Ng488 re PCLK 2 -.latch Ng25139 Ng11512 re PCLK 2 -.latch Ng25131 Ng11515 re PCLK 2 -.latch Ng25132 Ng11516 re PCLK 2 -.latch Ng25136 Ng477 re PCLK 2 -.latch Ng25137 Ng478 re PCLK 2 -.latch Ng25138 Ng479 re PCLK 2 -.latch Ng24289 Ng480 re PCLK 2 -.latch Ng24290 Ng484 re PCLK 2 -.latch Ng24291 Ng464 re PCLK 2 -.latch Ng25133 Ng11517 re PCLK 2 -.latch Ng25134 Ng11513 re PCLK 2 -.latch Ng25135 Ng11514 re PCLK 2 -.latch Ng16468 Ng528 re PCLK 2 -.latch Ng528 Ng535 re PCLK 2 -.latch Ng535 Ng542 re PCLK 2 -.latch Ng19021 Ng543 re PCLK 2 -.latch Ng543 Ng544 re PCLK 2 -.latch Ng23159 Ng548 re PCLK 2 -.latch Ng19022 Ng549 re PCLK 2 -.latch Ng549 Ng8284 re PCLK 2 -.latch Ng19023 Ng558 re PCLK 2 -.latch Ng558 Ng559 re PCLK 2 -.latch Ng28219 Ng576 re PCLK 2 -.latch Ng28220 Ng577 re PCLK 2 -.latch Ng28221 Ng575 re PCLK 2 -.latch Ng28222 Ng579 re PCLK 2 -.latch Ng28223 Ng580 re PCLK 2 -.latch Ng28224 Ng578 re PCLK 2 -.latch Ng28225 Ng582 re PCLK 2 -.latch Ng28226 Ng583 re PCLK 2 -.latch Ng28227 Ng581 re PCLK 2 -.latch Ng28228 Ng585 re PCLK 2 -.latch Ng28229 Ng586 re PCLK 2 -.latch Ng28230 Ng584 re PCLK 2 -.latch Ng25985 Ng587 re PCLK 2 -.latch Ng25986 Ng590 re PCLK 2 -.latch Ng25987 Ng593 re PCLK 2 -.latch Ng25988 Ng596 re PCLK 2 -.latch Ng25989 Ng599 re PCLK 2 -.latch Ng25990 Ng602 re PCLK 2 -.latch Ng29135 Ng614 re PCLK 2 -.latch Ng29136 Ng617 re PCLK 2 -.latch Ng29137 Ng620 re PCLK 2 -.latch Ng29132 Ng605 re PCLK 2 -.latch Ng29133 Ng608 re PCLK 2 -.latch Ng29134 Ng611 re PCLK 2 -.latch Ng27194 Ng490 re PCLK 2 -.latch Ng27195 Ng493 re PCLK 2 -.latch Ng27196 Ng496 re PCLK 2 -.latch Ng8284 Ng506 re PCLK 2 -.latch Ng24295 Ng507 re PCLK 2 -.latch Ng23154 Pg16297 re PCLK 2 -.latch Pg16297 Ng525 re PCLK 2 -.latch Ng13410 Ng529 re PCLK 2 -.latch Ng13411 Ng530 re PCLK 2 -.latch Ng13412 Ng531 re PCLK 2 -.latch Ng13413 Ng532 re PCLK 2 -.latch Ng13414 Ng533 re PCLK 2 -.latch Ng13415 Ng534 re PCLK 2 -.latch Ng13416 Ng536 re PCLK 2 -.latch Ng13417 Ng537 re PCLK 2 -.latch Ng25984 Ng538 re PCLK 2 -.latch Ng13418 Ng541 re PCLK 2 -.latch Ng20558 Ng630 re PCLK 2 -.latch Ng21943 Ng659 re PCLK 2 -.latch Ng23161 Ng640 re PCLK 2 -.latch Ng24296 Ng633 re PCLK 2 -.latch Ng25140 Ng653 re PCLK 2 -.latch Ng25991 Ng646 re PCLK 2 -.latch Ng26691 Ng660 re PCLK 2 -.latch Ng27197 Ng672 re PCLK 2 -.latch Ng27690 Ng666 re PCLK 2 -.latch Ng28231 Ng679 re PCLK 2 -.latch Ng28677 Ng686 re PCLK 2 -.latch Ng29138 Ng692 re PCLK 2 -.latch Ng23162 Ng699 re PCLK 2 -.latch Ng23163 Ng700 re PCLK 2 -.latch Ng23164 Ng698 re PCLK 2 -.latch Ng23165 Ng702 re PCLK 2 -.latch Ng23166 Ng703 re PCLK 2 -.latch Ng23167 Ng701 re PCLK 2 -.latch Ng23168 Ng705 re PCLK 2 -.latch Ng23169 Ng706 re PCLK 2 -.latch Ng23170 Ng704 re PCLK 2 -.latch Ng23171 Ng708 re PCLK 2 -.latch Ng23172 Ng709 re PCLK 2 -.latch Ng23173 Ng707 re PCLK 2 -.latch Ng23174 Ng711 re PCLK 2 -.latch Ng23175 Ng712 re PCLK 2 -.latch Ng23176 Ng710 re PCLK 2 -.latch Ng23177 Ng714 re PCLK 2 -.latch Ng23178 Ng715 re PCLK 2 -.latch Ng23179 Ng713 re PCLK 2 -.latch Ng23180 Ng717 re PCLK 2 -.latch Ng23181 Ng718 re PCLK 2 -.latch Ng23182 Ng716 re PCLK 2 -.latch Ng23183 Ng720 re PCLK 2 -.latch Ng23184 Ng721 re PCLK 2 -.latch Ng23185 Ng719 re PCLK 2 -.latch Ng23186 Ng723 re PCLK 2 -.latch Ng23187 Ng724 re PCLK 2 -.latch Ng23188 Ng722 re PCLK 2 -.latch Ng23189 Ng726 re PCLK 2 -.latch Ng23190 Ng727 re PCLK 2 -.latch Ng23191 Ng725 re PCLK 2 -.latch Ng23192 Ng729 re PCLK 2 -.latch Ng23193 Ng730 re PCLK 2 -.latch Ng23194 Ng728 re PCLK 2 -.latch Ng23195 Ng732 re PCLK 2 -.latch Ng23196 Ng733 re PCLK 2 -.latch Ng23197 Ng731 re PCLK 2 -.latch Ng26692 Ng735 re PCLK 2 -.latch Ng26693 Ng736 re PCLK 2 -.latch Ng26694 Ng734 re PCLK 2 -.latch Ng24297 Ng738 re PCLK 2 -.latch Ng24298 Ng739 re PCLK 2 -.latch Ng24299 Ng737 re PCLK 2 -.latch Ng13457 [1612] re PCLK 2 -.latch [1612] [1594] re PCLK 2 -.latch [1594] Ng853 re PCLK 2 -.latch Ng24300 Ng818 re PCLK 2 -.latch Ng24301 Ng819 re PCLK 2 -.latch Ng24302 Ng817 re PCLK 2 -.latch Ng24303 Ng821 re PCLK 2 -.latch Ng24304 Ng822 re PCLK 2 -.latch Ng24305 Ng820 re PCLK 2 -.latch Ng24306 Ng830 re PCLK 2 -.latch Ng24307 Ng831 re PCLK 2 -.latch Ng24308 Ng829 re PCLK 2 -.latch Ng24309 Ng833 re PCLK 2 -.latch Ng24310 Ng834 re PCLK 2 -.latch Ng24311 Ng832 re PCLK 2 -.latch Ng24312 Ng836 re PCLK 2 -.latch Ng24313 Ng837 re PCLK 2 -.latch Ng24314 Ng835 re PCLK 2 -.latch Ng24315 Ng839 re PCLK 2 -.latch Ng24316 Ng840 re PCLK 2 -.latch Ng24317 Ng838 re PCLK 2 -.latch Ng24318 Ng842 re PCLK 2 -.latch Ng24319 Ng843 re PCLK 2 -.latch Ng24320 Ng841 re PCLK 2 -.latch Ng24321 Ng845 re PCLK 2 -.latch Ng24322 Ng846 re PCLK 2 -.latch Ng24323 Ng844 re PCLK 2 -.latch Ng24324 Ng848 re PCLK 2 -.latch Ng24325 Ng849 re PCLK 2 -.latch Ng24326 Ng847 re PCLK 2 -.latch Ng24327 Ng851 re PCLK 2 -.latch Ng24328 Ng852 re PCLK 2 -.latch Ng24329 Ng850 re PCLK 2 -.latch Ng26696 Ng857 re PCLK 2 -.latch Ng26697 Ng858 re PCLK 2 -.latch Ng26698 Ng856 re PCLK 2 -.latch Ng26699 Ng860 re PCLK 2 -.latch Ng26700 Ng861 re PCLK 2 -.latch Ng26701 Ng859 re PCLK 2 -.latch Ng26702 Ng863 re PCLK 2 -.latch Ng26703 Ng864 re PCLK 2 -.latch Ng26704 Ng862 re PCLK 2 -.latch Ng26705 Ng866 re PCLK 2 -.latch Ng26706 Ng867 re PCLK 2 -.latch Ng26707 Ng865 re PCLK 2 -.latch Ng30521 Ng873 re PCLK 2 -.latch Ng30522 Ng876 re PCLK 2 -.latch Ng30523 Ng879 re PCLK 2 -.latch Ng30860 Ng918 re PCLK 2 -.latch Ng30861 Ng921 re PCLK 2 -.latch Ng30862 Ng924 re PCLK 2 -.latch Ng30854 Ng882 re PCLK 2 -.latch Ng30855 Ng885 re PCLK 2 -.latch Ng30856 Ng888 re PCLK 2 -.latch Ng30863 Ng927 re PCLK 2 -.latch Ng30864 Ng930 re PCLK 2 -.latch Ng30865 Ng933 re PCLK 2 -.latch Ng30524 Ng891 re PCLK 2 -.latch Ng30525 Ng894 re PCLK 2 -.latch Ng30526 Ng897 re PCLK 2 -.latch Ng30530 Ng936 re PCLK 2 -.latch Ng30531 Ng939 re PCLK 2 -.latch Ng30532 Ng942 re PCLK 2 -.latch Ng30527 Ng900 re PCLK 2 -.latch Ng30528 Ng903 re PCLK 2 -.latch Ng30529 Ng906 re PCLK 2 -.latch Ng30533 Ng945 re PCLK 2 -.latch Ng30534 Ng948 re PCLK 2 -.latch Ng30535 Ng951 re PCLK 2 -.latch Ng30857 Ng909 re PCLK 2 -.latch Ng30858 Ng912 re PCLK 2 -.latch Ng30859 Ng915 re PCLK 2 -.latch Ng30866 Ng954 re PCLK 2 -.latch Ng30867 Ng957 re PCLK 2 -.latch Ng30868 Ng960 re PCLK 2 -.latch Ng25992 Ng780 re PCLK 2 -.latch Ng26695 Ng776 re PCLK 2 -.latch Ng27198 Ng771 re PCLK 2 -.latch Ng27691 Ng767 re PCLK 2 -.latch Ng28232 Ng762 re PCLK 2 -.latch Ng28678 Ng758 re PCLK 2 -.latch Ng29139 Ng753 re PCLK 2 -.latch Ng29420 Ng749 re PCLK 2 -.latch Ng29634 Ng744 re PCLK 2 -.latch Ng29798 Ng740 re PCLK 2 -.latch Ng28233 Ng11524 re PCLK 2 -.latch Ng28234 Ng11525 re PCLK 2 -.latch Ng28235 Ng11526 re PCLK 2 -.latch Ng28236 Ng11527 re PCLK 2 -.latch Ng28237 Ng11528 re PCLK 2 -.latch Ng28238 Ng11529 re PCLK 2 -.latch Ng28239 Ng11530 re PCLK 2 -.latch Ng28240 Ng11531 re PCLK 2 -.latch Ng28241 Ng11532 re PCLK 2 -.latch Ng28242 Ng11533 re PCLK 2 -.latch Ng28243 Ng11534 re PCLK 2 -.latch Ng28244 Ng11535 re PCLK 2 -.latch Ng29421 Ng1095 re PCLK 2 -.latch Ng29422 Ng1098 re PCLK 2 -.latch Ng29423 Ng1101 re PCLK 2 -.latch Ng29638 Ng1104 re PCLK 2 -.latch Ng29639 Ng1107 re PCLK 2 -.latch Ng29640 Ng1110 re PCLK 2 -.latch Ng29424 Ng1114 re PCLK 2 -.latch Ng29425 Ng1115 re PCLK 2 -.latch Ng29426 Ng1113 re PCLK 2 -.latch Ng27692 Ng1116 re PCLK 2 -.latch Ng27693 Ng1119 re PCLK 2 -.latch Ng27694 Ng1122 re PCLK 2 -.latch Ng27695 Ng1125 re PCLK 2 -.latch Ng27696 Ng1128 re PCLK 2 -.latch Ng27697 Ng1131 re PCLK 2 -.latch Ng28679 Ng1135 re PCLK 2 -.latch Ng28680 Ng1136 re PCLK 2 -.latch Ng28681 Ng1134 re PCLK 2 -.latch Ng29799 Ng999 re PCLK 2 -.latch Ng29800 Ng1000 re PCLK 2 -.latch Ng29801 Ng1001 re PCLK 2 -.latch Ng30869 Ng1002 re PCLK 2 -.latch Ng30870 Ng1003 re PCLK 2 -.latch Ng30871 Ng1004 re PCLK 2 -.latch Ng30713 Ng1005 re PCLK 2 -.latch Ng30714 Ng1006 re PCLK 2 -.latch Ng30715 Ng1007 re PCLK 2 -.latch Ng29635 Ng1009 re PCLK 2 -.latch Ng29636 Ng1010 re PCLK 2 -.latch Ng29637 Ng1008 re PCLK 2 -.latch Ng27206 Ng1090 re PCLK 2 -.latch Ng27207 Ng1091 re PCLK 2 -.latch Ng27208 Ng1089 re PCLK 2 -.latch Ng11536 Ng1137 re PCLK 2 -.latch Ng1137 Ng1138 re PCLK 2 -.latch Ng11537 Ng1139 re PCLK 2 -.latch Ng1139 Ng1140 re PCLK 2 -.latch Ng11538 Ng1141 re PCLK 2 -.latch Ng1141 Ng966 re PCLK 2 -.latch Ng11518 Ng967 re PCLK 2 -.latch Ng967 Ng968 re PCLK 2 -.latch Ng11519 Ng969 re PCLK 2 -.latch Ng969 Ng970 re PCLK 2 -.latch Ng11520 Ng971 re PCLK 2 -.latch Ng971 Ng972 re PCLK 2 -.latch Ng11521 Ng973 re PCLK 2 -.latch Ng973 Ng974 re PCLK 2 -.latch Ng11522 Ng975 re PCLK 2 -.latch Ng975 Ng976 re PCLK 2 -.latch Ng13423 Ng977 re PCLK 2 -.latch Ng977 Ng978 re PCLK 2 -.latch Ng19024 Ng986 re PCLK 2 -.latch Ng27200 Ng992 re PCLK 2 -.latch Ng27199 Ng985 re PCLK 2 -.latch Ng11524 Ng1029 re PCLK 2 -.latch Ng1029 Ng1036 re PCLK 2 -.latch Ng11525 Ng1037 re PCLK 2 -.latch Ng1037 Ng1038 re PCLK 2 -.latch Ng11526 Ng1039 re PCLK 2 -.latch Ng1039 Ng1040 re PCLK 2 -.latch Ng11527 Ng1044 re PCLK 2 -.latch Ng1044 Ng1051 re PCLK 2 -.latch Ng11528 Ng1052 re PCLK 2 -.latch Ng1052 Ng1053 re PCLK 2 -.latch Ng11529 Ng1054 re PCLK 2 -.latch Ng1054 Ng1055 re PCLK 2 -.latch Ng11530 Ng1059 re PCLK 2 -.latch Ng1059 Ng1066 re PCLK 2 -.latch Ng11531 Ng1067 re PCLK 2 -.latch Ng1067 Ng1068 re PCLK 2 -.latch Ng11532 Ng1069 re PCLK 2 -.latch Ng1069 Ng1070 re PCLK 2 -.latch Ng11533 Ng1074 re PCLK 2 -.latch Ng1074 Ng1081 re PCLK 2 -.latch Ng11534 Ng1082 re PCLK 2 -.latch Ng1082 Ng1083 re PCLK 2 -.latch Ng11535 Ng1084 re PCLK 2 -.latch Ng1084 Ng1011 re PCLK 2 -.latch Ng23198 Ng1240 re PCLK 2 -.latch Ng20560 Ng1243 re PCLK 2 -.latch Ng20561 Ng1196 re PCLK 2 -.latch Ng16469 Ng1199 re PCLK 2 -.latch Ng1199 Ng1209 re PCLK 2 -.latch Ng1209 Ng1210 re PCLK 2 -.latch Ng11539 Ng1250 re PCLK 2 -.latch Ng1250 Ng1255 re PCLK 2 -.latch Ng11542 Ng1256 re PCLK 2 -.latch Ng1256 Ng1257 re PCLK 2 -.latch Ng11543 Ng1258 re PCLK 2 -.latch Ng1258 Ng1259 re PCLK 2 -.latch Ng11544 Ng1260 re PCLK 2 -.latch Ng1260 Ng1251 re PCLK 2 -.latch Ng11540 Ng1252 re PCLK 2 -.latch Ng1252 Ng1253 re PCLK 2 -.latch Ng11541 Ng1254 re PCLK 2 -.latch Ng1254 Ng1176 re PCLK 2 -.latch Ng24333 Ng1173 re PCLK 2 -.latch Ng24334 Ng1174 re PCLK 2 -.latch Ng24335 Ng1175 re PCLK 2 -.latch Ng25150 Ng11539 re PCLK 2 -.latch Ng25142 Ng11542 re PCLK 2 -.latch Ng25143 Ng11543 re PCLK 2 -.latch Ng25147 Ng1164 re PCLK 2 -.latch Ng25148 Ng1165 re PCLK 2 -.latch Ng25149 Ng1166 re PCLK 2 -.latch Ng24330 Ng1167 re PCLK 2 -.latch Ng24331 Ng1171 re PCLK 2 -.latch Ng24332 Ng1151 re PCLK 2 -.latch Ng25144 Ng11544 re PCLK 2 -.latch Ng25145 Ng11540 re PCLK 2 -.latch Ng25146 Ng11541 re PCLK 2 -.latch Ng16470 Ng1214 re PCLK 2 -.latch Ng1214 Ng1221 re PCLK 2 -.latch Ng1221 Ng1228 re PCLK 2 -.latch Ng19033 Ng1229 re PCLK 2 -.latch Ng1229 Ng1230 re PCLK 2 -.latch Ng27217 Ng1234 re PCLK 2 -.latch Ng19034 Ng1235 re PCLK 2 -.latch Ng1235 Ng8293 re PCLK 2 -.latch Ng19035 Ng1244 re PCLK 2 -.latch Ng1244 Ng1245 re PCLK 2 -.latch Ng28245 Ng1262 re PCLK 2 -.latch Ng28246 Ng1263 re PCLK 2 -.latch Ng28247 Ng1261 re PCLK 2 -.latch Ng28248 Ng1265 re PCLK 2 -.latch Ng28249 Ng1266 re PCLK 2 -.latch Ng28250 Ng1264 re PCLK 2 -.latch Ng28251 Ng1268 re PCLK 2 -.latch Ng28252 Ng1269 re PCLK 2 -.latch Ng28253 Ng1267 re PCLK 2 -.latch Ng28254 Ng1271 re PCLK 2 -.latch Ng28255 Ng1272 re PCLK 2 -.latch Ng28256 Ng1270 re PCLK 2 -.latch Ng25994 Ng1273 re PCLK 2 -.latch Ng25995 Ng1276 re PCLK 2 -.latch Ng25996 Ng1279 re PCLK 2 -.latch Ng25997 Ng1282 re PCLK 2 -.latch Ng25998 Ng1285 re PCLK 2 -.latch Ng25999 Ng1288 re PCLK 2 -.latch Ng29143 Ng1300 re PCLK 2 -.latch Ng29144 Ng1303 re PCLK 2 -.latch Ng29145 Ng1306 re PCLK 2 -.latch Ng29140 Ng1291 re PCLK 2 -.latch Ng29141 Ng1294 re PCLK 2 -.latch Ng29142 Ng1297 re PCLK 2 -.latch Ng27209 Ng1177 re PCLK 2 -.latch Ng27210 Ng1180 re PCLK 2 -.latch Ng27211 Ng1183 re PCLK 2 -.latch Ng8293 Ng1192 re PCLK 2 -.latch Ng24336 Ng1193 re PCLK 2 -.latch Ng27212 Pg16355 re PCLK 2 -.latch Pg16355 Ng1211 re PCLK 2 -.latch Ng13426 Ng1215 re PCLK 2 -.latch Ng13427 Ng1216 re PCLK 2 -.latch Ng13428 Ng1217 re PCLK 2 -.latch Ng13429 Ng1218 re PCLK 2 -.latch Ng13430 Ng1219 re PCLK 2 -.latch Ng13431 Ng1220 re PCLK 2 -.latch Ng13432 Ng1222 re PCLK 2 -.latch Ng13433 Ng1223 re PCLK 2 -.latch Ng25993 Ng1224 re PCLK 2 -.latch Ng13434 Ng1227 re PCLK 2 -.latch Ng13475 [1605] re PCLK 2 -.latch [1605] [1603] re PCLK 2 -.latch [1603] Ng1315 re PCLK 2 -.latch Ng20562 Ng1316 re PCLK 2 -.latch Ng21944 Ng1345 re PCLK 2 -.latch Ng23199 Ng1326 re PCLK 2 -.latch Ng24337 Ng1319 re PCLK 2 -.latch Ng25151 Ng1339 re PCLK 2 -.latch Ng26000 Ng1332 re PCLK 2 -.latch Ng26708 Ng1346 re PCLK 2 -.latch Ng27218 Ng1358 re PCLK 2 -.latch Ng27698 Ng1352 re PCLK 2 -.latch Ng28257 Ng1365 re PCLK 2 -.latch Ng28682 Ng1372 re PCLK 2 -.latch Ng29146 Ng1378 re PCLK 2 -.latch Ng23200 Ng1385 re PCLK 2 -.latch Ng23201 Ng1386 re PCLK 2 -.latch Ng23202 Ng1384 re PCLK 2 -.latch Ng23203 Ng1388 re PCLK 2 -.latch Ng23204 Ng1389 re PCLK 2 -.latch Ng23205 Ng1387 re PCLK 2 -.latch Ng23206 Ng1391 re PCLK 2 -.latch Ng23207 Ng1392 re PCLK 2 -.latch Ng23208 Ng1390 re PCLK 2 -.latch Ng23209 Ng1394 re PCLK 2 -.latch Ng23210 Ng1395 re PCLK 2 -.latch Ng23211 Ng1393 re PCLK 2 -.latch Ng23212 Ng1397 re PCLK 2 -.latch Ng23213 Ng1398 re PCLK 2 -.latch Ng23214 Ng1396 re PCLK 2 -.latch Ng23215 Ng1400 re PCLK 2 -.latch Ng23216 Ng1401 re PCLK 2 -.latch Ng23217 Ng1399 re PCLK 2 -.latch Ng23218 Ng1403 re PCLK 2 -.latch Ng23219 Ng1404 re PCLK 2 -.latch Ng23220 Ng1402 re PCLK 2 -.latch Ng23221 Ng1406 re PCLK 2 -.latch Ng23222 Ng1407 re PCLK 2 -.latch Ng23223 Ng1405 re PCLK 2 -.latch Ng23224 Ng1409 re PCLK 2 -.latch Ng23225 Ng1410 re PCLK 2 -.latch Ng23226 Ng1408 re PCLK 2 -.latch Ng23227 Ng1412 re PCLK 2 -.latch Ng23228 Ng1413 re PCLK 2 -.latch Ng23229 Ng1411 re PCLK 2 -.latch Ng23230 Ng1415 re PCLK 2 -.latch Ng23231 Ng1416 re PCLK 2 -.latch Ng23232 Ng1414 re PCLK 2 -.latch Ng23233 Ng1418 re PCLK 2 -.latch Ng23234 Ng1419 re PCLK 2 -.latch Ng23235 Ng1417 re PCLK 2 -.latch Ng26709 Ng1421 re PCLK 2 -.latch Ng26710 Ng1422 re PCLK 2 -.latch Ng26711 Ng1420 re PCLK 2 -.latch Ng24338 Ng1424 re PCLK 2 -.latch Ng24339 Ng1425 re PCLK 2 -.latch Ng24340 Ng1423 re PCLK 2 -.latch Ng24341 Ng1512 re PCLK 2 -.latch Ng24342 Ng1513 re PCLK 2 -.latch Ng24343 Ng1511 re PCLK 2 -.latch Ng24344 Ng1515 re PCLK 2 -.latch Ng24345 Ng1516 re PCLK 2 -.latch Ng24346 Ng1514 re PCLK 2 -.latch Ng24347 Ng1524 re PCLK 2 -.latch Ng24348 Ng1525 re PCLK 2 -.latch Ng24349 Ng1523 re PCLK 2 -.latch Ng24350 Ng1527 re PCLK 2 -.latch Ng24351 Ng1528 re PCLK 2 -.latch Ng24352 Ng1526 re PCLK 2 -.latch Ng24353 Ng1530 re PCLK 2 -.latch Ng24354 Ng1531 re PCLK 2 -.latch Ng24355 Ng1529 re PCLK 2 -.latch Ng24356 Ng1533 re PCLK 2 -.latch Ng24357 Ng1534 re PCLK 2 -.latch Ng24358 Ng1532 re PCLK 2 -.latch Ng24359 Ng1536 re PCLK 2 -.latch Ng24360 Ng1537 re PCLK 2 -.latch Ng24361 Ng1535 re PCLK 2 -.latch Ng24362 Ng1539 re PCLK 2 -.latch Ng24363 Ng1540 re PCLK 2 -.latch Ng24364 Ng1538 re PCLK 2 -.latch Ng24365 Ng1542 re PCLK 2 -.latch Ng24366 Ng1543 re PCLK 2 -.latch Ng24367 Ng1541 re PCLK 2 -.latch Ng24368 Ng1545 re PCLK 2 -.latch Ng24369 Ng1546 re PCLK 2 -.latch Ng24370 Ng1544 re PCLK 2 -.latch Ng26713 Ng1551 re PCLK 2 -.latch Ng26714 Ng1552 re PCLK 2 -.latch Ng26715 Ng1550 re PCLK 2 -.latch Ng26716 Ng1554 re PCLK 2 -.latch Ng26717 Ng1555 re PCLK 2 -.latch Ng26718 Ng1553 re PCLK 2 -.latch Ng26719 Ng1557 re PCLK 2 -.latch Ng26720 Ng1558 re PCLK 2 -.latch Ng26721 Ng1556 re PCLK 2 -.latch Ng26722 Ng1560 re PCLK 2 -.latch Ng26723 Ng1561 re PCLK 2 -.latch Ng26724 Ng1559 re PCLK 2 -.latch Ng30536 Ng1567 re PCLK 2 -.latch Ng30537 Ng1570 re PCLK 2 -.latch Ng30538 Ng1573 re PCLK 2 -.latch Ng30878 Ng1612 re PCLK 2 -.latch Ng30879 Ng1615 re PCLK 2 -.latch Ng30880 Ng1618 re PCLK 2 -.latch Ng30872 Ng1576 re PCLK 2 -.latch Ng30873 Ng1579 re PCLK 2 -.latch Ng30874 Ng1582 re PCLK 2 -.latch Ng30881 Ng1621 re PCLK 2 -.latch Ng30882 Ng1624 re PCLK 2 -.latch Ng30883 Ng1627 re PCLK 2 -.latch Ng30539 Ng1585 re PCLK 2 -.latch Ng30540 Ng1588 re PCLK 2 -.latch Ng30541 Ng1591 re PCLK 2 -.latch Ng30545 Ng1630 re PCLK 2 -.latch Ng30546 Ng1633 re PCLK 2 -.latch Ng30547 Ng1636 re PCLK 2 -.latch Ng30542 Ng1594 re PCLK 2 -.latch Ng30543 Ng1597 re PCLK 2 -.latch Ng30544 Ng1600 re PCLK 2 -.latch Ng30548 Ng1639 re PCLK 2 -.latch Ng30549 Ng1642 re PCLK 2 -.latch Ng30550 Ng1645 re PCLK 2 -.latch Ng30875 Ng1603 re PCLK 2 -.latch Ng30876 Ng1606 re PCLK 2 -.latch Ng30877 Ng1609 re PCLK 2 -.latch Ng30884 Ng1648 re PCLK 2 -.latch Ng30885 Ng1651 re PCLK 2 -.latch Ng30886 Ng1654 re PCLK 2 -.latch Ng26001 Ng1466 re PCLK 2 -.latch Ng26712 Ng1462 re PCLK 2 -.latch Ng27219 Ng1457 re PCLK 2 -.latch Ng27699 Ng1453 re PCLK 2 -.latch Ng28258 Ng1448 re PCLK 2 -.latch Ng28683 Ng1444 re PCLK 2 -.latch Ng29147 Ng1439 re PCLK 2 -.latch Ng29427 Ng1435 re PCLK 2 -.latch Ng29641 Ng1430 re PCLK 2 -.latch Ng29802 Ng1426 re PCLK 2 -.latch Ng28259 Ng11551 re PCLK 2 -.latch Ng28260 Ng11552 re PCLK 2 -.latch Ng28261 Ng11553 re PCLK 2 -.latch Ng28262 Ng11554 re PCLK 2 -.latch Ng28263 Ng11555 re PCLK 2 -.latch Ng28264 Ng11556 re PCLK 2 -.latch Ng28265 Ng11557 re PCLK 2 -.latch Ng28266 Ng11558 re PCLK 2 -.latch Ng28267 Ng11559 re PCLK 2 -.latch Ng28268 Ng11560 re PCLK 2 -.latch Ng28269 Ng11561 re PCLK 2 -.latch Ng28270 Ng11562 re PCLK 2 -.latch Ng29434 Ng1789 re PCLK 2 -.latch Ng29435 Ng1792 re PCLK 2 -.latch Ng29436 Ng1795 re PCLK 2 -.latch Ng29645 Ng1798 re PCLK 2 -.latch Ng29646 Ng1801 re PCLK 2 -.latch Ng29647 Ng1804 re PCLK 2 -.latch Ng29437 Ng1808 re PCLK 2 -.latch Ng29438 Ng1809 re PCLK 2 -.latch Ng29439 Ng1807 re PCLK 2 -.latch Ng27700 Ng1810 re PCLK 2 -.latch Ng27701 Ng1813 re PCLK 2 -.latch Ng27702 Ng1816 re PCLK 2 -.latch Ng27703 Ng1819 re PCLK 2 -.latch Ng27704 Ng1822 re PCLK 2 -.latch Ng27705 Ng1825 re PCLK 2 -.latch Ng28684 Ng1829 re PCLK 2 -.latch Ng28685 Ng1830 re PCLK 2 -.latch Ng28686 Ng1828 re PCLK 2 -.latch Ng29803 Ng1693 re PCLK 2 -.latch Ng29804 Ng1694 re PCLK 2 -.latch Ng29805 Ng1695 re PCLK 2 -.latch Ng30887 Ng1696 re PCLK 2 -.latch Ng30888 Ng1697 re PCLK 2 -.latch Ng30889 Ng1698 re PCLK 2 -.latch Ng30716 Ng1699 re PCLK 2 -.latch Ng30717 Ng1700 re PCLK 2 -.latch Ng30718 Ng1701 re PCLK 2 -.latch Ng29642 Ng1703 re PCLK 2 -.latch Ng29643 Ng1704 re PCLK 2 -.latch Ng29644 Ng1702 re PCLK 2 -.latch Ng27221 Ng1784 re PCLK 2 -.latch Ng27222 Ng1785 re PCLK 2 -.latch Ng27223 Ng1783 re PCLK 2 -.latch Ng11563 Ng1831 re PCLK 2 -.latch Ng1831 Ng1832 re PCLK 2 -.latch Ng11564 Ng1833 re PCLK 2 -.latch Ng1833 Ng1834 re PCLK 2 -.latch Ng11565 Ng1835 re PCLK 2 -.latch Ng1835 Ng1660 re PCLK 2 -.latch Ng11545 Ng1661 re PCLK 2 -.latch Ng1661 Ng1662 re PCLK 2 -.latch Ng11546 Ng1663 re PCLK 2 -.latch Ng1663 Ng1664 re PCLK 2 -.latch Ng11547 Ng1665 re PCLK 2 -.latch Ng1665 Ng1666 re PCLK 2 -.latch Ng11548 Ng1667 re PCLK 2 -.latch Ng1667 Ng1668 re PCLK 2 -.latch Ng11549 Ng1669 re PCLK 2 -.latch Ng1669 Ng1670 re PCLK 2 -.latch Ng13439 Ng1671 re PCLK 2 -.latch Ng1671 Ng1672 re PCLK 2 -.latch Ng19036 Ng1680 re PCLK 2 -.latch Ng29428 Ng1686 re PCLK 2 -.latch Ng27220 Ng1679 re PCLK 2 -.latch Ng11551 Ng1723 re PCLK 2 -.latch Ng1723 Ng1730 re PCLK 2 -.latch Ng11552 Ng1731 re PCLK 2 -.latch Ng1731 Ng1732 re PCLK 2 -.latch Ng11553 Ng1733 re PCLK 2 -.latch Ng1733 Ng1734 re PCLK 2 -.latch Ng11554 Ng1738 re PCLK 2 -.latch Ng1738 Ng1745 re PCLK 2 -.latch Ng11555 Ng1746 re PCLK 2 -.latch Ng1746 Ng1747 re PCLK 2 -.latch Ng11556 Ng1748 re PCLK 2 -.latch Ng1748 Ng1749 re PCLK 2 -.latch Ng11557 Ng1753 re PCLK 2 -.latch Ng1753 Ng1760 re PCLK 2 -.latch Ng11558 Ng1761 re PCLK 2 -.latch Ng1761 Ng1762 re PCLK 2 -.latch Ng11559 Ng1763 re PCLK 2 -.latch Ng1763 Ng1764 re PCLK 2 -.latch Ng11560 Ng1768 re PCLK 2 -.latch Ng1768 Ng1775 re PCLK 2 -.latch Ng11561 Ng1776 re PCLK 2 -.latch Ng1776 Ng1777 re PCLK 2 -.latch Ng11562 Ng1778 re PCLK 2 -.latch Ng1778 Ng1705 re PCLK 2 -.latch Ng23236 Ng1934 re PCLK 2 -.latch Ng20564 Ng1937 re PCLK 2 -.latch Ng20565 Ng1890 re PCLK 2 -.latch Ng16471 Ng1893 re PCLK 2 -.latch Ng1893 Ng1903 re PCLK 2 -.latch Ng1903 Ng1904 re PCLK 2 -.latch Ng11566 Ng1944 re PCLK 2 -.latch Ng1944 Ng1949 re PCLK 2 -.latch Ng11569 Ng1950 re PCLK 2 -.latch Ng1950 Ng1951 re PCLK 2 -.latch Ng11570 Ng1952 re PCLK 2 -.latch Ng1952 Ng1953 re PCLK 2 -.latch Ng11571 Ng1954 re PCLK 2 -.latch Ng1954 Ng1945 re PCLK 2 -.latch Ng11567 Ng1946 re PCLK 2 -.latch Ng1946 Ng1947 re PCLK 2 -.latch Ng11568 Ng1948 re PCLK 2 -.latch Ng1948 Ng1870 re PCLK 2 -.latch Ng24374 Ng1867 re PCLK 2 -.latch Ng24375 Ng1868 re PCLK 2 -.latch Ng24376 Ng1869 re PCLK 2 -.latch Ng25161 Ng11566 re PCLK 2 -.latch Ng25153 Ng11569 re PCLK 2 -.latch Ng25154 Ng11570 re PCLK 2 -.latch Ng25158 Ng1858 re PCLK 2 -.latch Ng25159 Ng1859 re PCLK 2 -.latch Ng25160 Ng1860 re PCLK 2 -.latch Ng24371 Ng1861 re PCLK 2 -.latch Ng24372 Ng1865 re PCLK 2 -.latch Ng24373 Ng1845 re PCLK 2 -.latch Ng25155 Ng11571 re PCLK 2 -.latch Ng25156 Ng11567 re PCLK 2 -.latch Ng25157 Ng11568 re PCLK 2 -.latch Ng16472 Ng1908 re PCLK 2 -.latch Ng1908 Ng1915 re PCLK 2 -.latch Ng1915 Ng1922 re PCLK 2 -.latch Ng19045 Ng1923 re PCLK 2 -.latch Ng1923 Ng1924 re PCLK 2 -.latch Ng29445 Ng1928 re PCLK 2 -.latch Ng19046 Ng1929 re PCLK 2 -.latch Ng1929 Ng8302 re PCLK 2 -.latch Ng19047 Ng1938 re PCLK 2 -.latch Ng1938 Ng1939 re PCLK 2 -.latch Ng28271 Ng1956 re PCLK 2 -.latch Ng28272 Ng1957 re PCLK 2 -.latch Ng28273 Ng1955 re PCLK 2 -.latch Ng28274 Ng1959 re PCLK 2 -.latch Ng28275 Ng1960 re PCLK 2 -.latch Ng28276 Ng1958 re PCLK 2 -.latch Ng28277 Ng1962 re PCLK 2 -.latch Ng28278 Ng1963 re PCLK 2 -.latch Ng28279 Ng1961 re PCLK 2 -.latch Ng28280 Ng1965 re PCLK 2 -.latch Ng28281 Ng1966 re PCLK 2 -.latch Ng28282 Ng1964 re PCLK 2 -.latch Ng26003 Ng1967 re PCLK 2 -.latch Ng26004 Ng1970 re PCLK 2 -.latch Ng26005 Ng1973 re PCLK 2 -.latch Ng26006 Ng1976 re PCLK 2 -.latch Ng26007 Ng1979 re PCLK 2 -.latch Ng26008 Ng1982 re PCLK 2 -.latch Ng29151 Ng1994 re PCLK 2 -.latch Ng29152 Ng1997 re PCLK 2 -.latch Ng29153 Ng2000 re PCLK 2 -.latch Ng29148 Ng1985 re PCLK 2 -.latch Ng29149 Ng1988 re PCLK 2 -.latch Ng29150 Ng1991 re PCLK 2 -.latch Ng27224 Ng1871 re PCLK 2 -.latch Ng27225 Ng1874 re PCLK 2 -.latch Ng27226 Ng1877 re PCLK 2 -.latch Ng8302 Ng1886 re PCLK 2 -.latch Ng24377 Ng1887 re PCLK 2 -.latch Ng29440 Pg16399 re PCLK 2 -.latch Pg16399 Ng1905 re PCLK 2 -.latch Ng13442 Ng1909 re PCLK 2 -.latch Ng13443 Ng1910 re PCLK 2 -.latch Ng13444 Ng1911 re PCLK 2 -.latch Ng13445 Ng1912 re PCLK 2 -.latch Ng13446 Ng1913 re PCLK 2 -.latch Ng13447 Ng1914 re PCLK 2 -.latch Ng13448 Ng1916 re PCLK 2 -.latch Ng13449 Ng1917 re PCLK 2 -.latch Ng26002 Ng1918 re PCLK 2 -.latch Ng13450 Ng1921 re PCLK 2 -.latch Ng20566 Ng2010 re PCLK 2 -.latch Ng21945 Ng2039 re PCLK 2 -.latch Ng23237 Ng2020 re PCLK 2 -.latch Ng24378 Ng2013 re PCLK 2 -.latch Ng25162 Ng2033 re PCLK 2 -.latch Ng26009 Ng2026 re PCLK 2 -.latch Ng26725 Ng2040 re PCLK 2 -.latch Ng27227 Ng2052 re PCLK 2 -.latch Ng27706 Ng2046 re PCLK 2 -.latch Ng28283 Ng2059 re PCLK 2 -.latch Ng28687 Ng2066 re PCLK 2 -.latch Ng29154 Ng2072 re PCLK 2 -.latch Ng23238 Ng2079 re PCLK 2 -.latch Ng23239 Ng2080 re PCLK 2 -.latch Ng23240 Ng2078 re PCLK 2 -.latch Ng23241 Ng2082 re PCLK 2 -.latch Ng23242 Ng2083 re PCLK 2 -.latch Ng23243 Ng2081 re PCLK 2 -.latch Ng23244 Ng2085 re PCLK 2 -.latch Ng23245 Ng2086 re PCLK 2 -.latch Ng23246 Ng2084 re PCLK 2 -.latch Ng23247 Ng2088 re PCLK 2 -.latch Ng23248 Ng2089 re PCLK 2 -.latch Ng23249 Ng2087 re PCLK 2 -.latch Ng23250 Ng2091 re PCLK 2 -.latch Ng23251 Ng2092 re PCLK 2 -.latch Ng23252 Ng2090 re PCLK 2 -.latch Ng23253 Ng2094 re PCLK 2 -.latch Ng23254 Ng2095 re PCLK 2 -.latch Ng23255 Ng2093 re PCLK 2 -.latch Ng23256 Ng2097 re PCLK 2 -.latch Ng23257 Ng2098 re PCLK 2 -.latch Ng23258 Ng2096 re PCLK 2 -.latch Ng23259 Ng2100 re PCLK 2 -.latch Ng23260 Ng2101 re PCLK 2 -.latch Ng23261 Ng2099 re PCLK 2 -.latch Ng23262 Ng2103 re PCLK 2 -.latch Ng23263 Ng2104 re PCLK 2 -.latch Ng23264 Ng2102 re PCLK 2 -.latch Ng23265 Ng2106 re PCLK 2 -.latch Ng23266 Ng2107 re PCLK 2 -.latch Ng23267 Ng2105 re PCLK 2 -.latch Ng23268 Ng2109 re PCLK 2 -.latch Ng23269 Ng2110 re PCLK 2 -.latch Ng23270 Ng2108 re PCLK 2 -.latch Ng23271 Ng2112 re PCLK 2 -.latch Ng23272 Ng2113 re PCLK 2 -.latch Ng23273 Ng2111 re PCLK 2 -.latch Ng26726 Ng2115 re PCLK 2 -.latch Ng26727 Ng2116 re PCLK 2 -.latch Ng26728 Ng2114 re PCLK 2 -.latch Ng24379 Ng2118 re PCLK 2 -.latch Ng24380 Ng2119 re PCLK 2 -.latch Ng24381 Ng2117 re PCLK 2 -.latch Ng24382 Ng2206 re PCLK 2 -.latch Ng24383 Ng2207 re PCLK 2 -.latch Ng24384 Ng2205 re PCLK 2 -.latch Ng24385 Ng2209 re PCLK 2 -.latch Ng24386 Ng2210 re PCLK 2 -.latch Ng24387 Ng2208 re PCLK 2 -.latch Ng24388 Ng2218 re PCLK 2 -.latch Ng24389 Ng2219 re PCLK 2 -.latch Ng24390 Ng2217 re PCLK 2 -.latch Ng24391 Ng2221 re PCLK 2 -.latch Ng24392 Ng2222 re PCLK 2 -.latch Ng24393 Ng2220 re PCLK 2 -.latch Ng24394 Ng2224 re PCLK 2 -.latch Ng24395 Ng2225 re PCLK 2 -.latch Ng24396 Ng2223 re PCLK 2 -.latch Ng24397 Ng2227 re PCLK 2 -.latch Ng24398 Ng2228 re PCLK 2 -.latch Ng24399 Ng2226 re PCLK 2 -.latch Ng24400 Ng2230 re PCLK 2 -.latch Ng24401 Ng2231 re PCLK 2 -.latch Ng24402 Ng2229 re PCLK 2 -.latch Ng24403 Ng2233 re PCLK 2 -.latch Ng24404 Ng2234 re PCLK 2 -.latch Ng24405 Ng2232 re PCLK 2 -.latch Ng24406 Ng2236 re PCLK 2 -.latch Ng24407 Ng2237 re PCLK 2 -.latch Ng24408 Ng2235 re PCLK 2 -.latch Ng24409 Ng2239 re PCLK 2 -.latch Ng24410 Ng2240 re PCLK 2 -.latch Ng24411 Ng2238 re PCLK 2 -.latch Ng26730 Ng2245 re PCLK 2 -.latch Ng26731 Ng2246 re PCLK 2 -.latch Ng26732 Ng2244 re PCLK 2 -.latch Ng26733 Ng2248 re PCLK 2 -.latch Ng26734 Ng2249 re PCLK 2 -.latch Ng26735 Ng2247 re PCLK 2 -.latch Ng26736 Ng2251 re PCLK 2 -.latch Ng26737 Ng2252 re PCLK 2 -.latch Ng26738 Ng2250 re PCLK 2 -.latch Ng26739 Ng2254 re PCLK 2 -.latch Ng26740 Ng2255 re PCLK 2 -.latch Ng26741 Ng2253 re PCLK 2 -.latch Ng30551 Ng2261 re PCLK 2 -.latch Ng30552 Ng2264 re PCLK 2 -.latch Ng30553 Ng2267 re PCLK 2 -.latch Ng30896 Ng2306 re PCLK 2 -.latch Ng30897 Ng2309 re PCLK 2 -.latch Ng30898 Ng2312 re PCLK 2 -.latch Ng30890 Ng2270 re PCLK 2 -.latch Ng30891 Ng2273 re PCLK 2 -.latch Ng30892 Ng2276 re PCLK 2 -.latch Ng30899 Ng2315 re PCLK 2 -.latch Ng30900 Ng2318 re PCLK 2 -.latch Ng30901 Ng2321 re PCLK 2 -.latch Ng30554 Ng2279 re PCLK 2 -.latch Ng30555 Ng2282 re PCLK 2 -.latch Ng30556 Ng2285 re PCLK 2 -.latch Ng30560 Ng2324 re PCLK 2 -.latch Ng30561 Ng2327 re PCLK 2 -.latch Ng30562 Ng2330 re PCLK 2 -.latch Ng30557 Ng2288 re PCLK 2 -.latch Ng30558 Ng2291 re PCLK 2 -.latch Ng30559 Ng2294 re PCLK 2 -.latch Ng30563 Ng2333 re PCLK 2 -.latch Ng30564 Ng2336 re PCLK 2 -.latch Ng30565 Ng2339 re PCLK 2 -.latch Ng30893 Ng2297 re PCLK 2 -.latch Ng30894 Ng2300 re PCLK 2 -.latch Ng30895 Ng2303 re PCLK 2 -.latch Ng30902 Ng2342 re PCLK 2 -.latch Ng30903 Ng2345 re PCLK 2 -.latch Ng30904 Ng2348 re PCLK 2 -.latch Ng26010 Ng2160 re PCLK 2 -.latch Ng26729 Ng2156 re PCLK 2 -.latch Ng27228 Ng2151 re PCLK 2 -.latch Ng27707 Ng2147 re PCLK 2 -.latch Ng28284 Ng2142 re PCLK 2 -.latch Ng28688 Ng2138 re PCLK 2 -.latch Ng29155 Ng2133 re PCLK 2 -.latch Ng29446 Ng2129 re PCLK 2 -.latch Ng29648 Ng2124 re PCLK 2 -.latch Ng29806 Ng2120 re PCLK 2 -.latch Ng20567 Ng2256 re PCLK 2 -.latch Ng2256 [1609] re PCLK 2 -.latch [1609] Ng2257 re PCLK 2 -.latch Ng28285 Ng11578 re PCLK 2 -.latch Ng28286 Ng11579 re PCLK 2 -.latch Ng28287 Ng11580 re PCLK 2 -.latch Ng28288 Ng11581 re PCLK 2 -.latch Ng28289 Ng11582 re PCLK 2 -.latch Ng28290 Ng11583 re PCLK 2 -.latch Ng28291 Ng11584 re PCLK 2 -.latch Ng28292 Ng11585 re PCLK 2 -.latch Ng28293 Ng11586 re PCLK 2 -.latch Ng28294 Ng11587 re PCLK 2 -.latch Ng28295 Ng11588 re PCLK 2 -.latch Ng28296 Ng11589 re PCLK 2 -.latch Ng29447 Ng2483 re PCLK 2 -.latch Ng29448 Ng2486 re PCLK 2 -.latch Ng29449 Ng2489 re PCLK 2 -.latch Ng29652 Ng2492 re PCLK 2 -.latch Ng29653 Ng2495 re PCLK 2 -.latch Ng29654 Ng2498 re PCLK 2 -.latch Ng29450 Ng2502 re PCLK 2 -.latch Ng29451 Ng2503 re PCLK 2 -.latch Ng29452 Ng2501 re PCLK 2 -.latch Ng27708 Ng2504 re PCLK 2 -.latch Ng27709 Ng2507 re PCLK 2 -.latch Ng27710 Ng2510 re PCLK 2 -.latch Ng27711 Ng2513 re PCLK 2 -.latch Ng27712 Ng2516 re PCLK 2 -.latch Ng27713 Ng2519 re PCLK 2 -.latch Ng28689 Ng2523 re PCLK 2 -.latch Ng28690 Ng2524 re PCLK 2 -.latch Ng28691 Ng2522 re PCLK 2 -.latch Ng29807 Ng2387 re PCLK 2 -.latch Ng29808 Ng2388 re PCLK 2 -.latch Ng29809 Ng2389 re PCLK 2 -.latch Ng30905 Ng2390 re PCLK 2 -.latch Ng30906 Ng2391 re PCLK 2 -.latch Ng30907 Ng2392 re PCLK 2 -.latch Ng30719 Ng2393 re PCLK 2 -.latch Ng30720 Ng2394 re PCLK 2 -.latch Ng30721 Ng2395 re PCLK 2 -.latch Ng29649 Ng2397 re PCLK 2 -.latch Ng29650 Ng2398 re PCLK 2 -.latch Ng29651 Ng2396 re PCLK 2 -.latch Ng27230 Ng2478 re PCLK 2 -.latch Ng27231 Ng2479 re PCLK 2 -.latch Ng27232 Ng2477 re PCLK 2 -.latch Ng11590 Ng2525 re PCLK 2 -.latch Ng2525 Ng2526 re PCLK 2 -.latch Ng11591 Ng2527 re PCLK 2 -.latch Ng2527 Ng2528 re PCLK 2 -.latch Ng11592 Ng2529 re PCLK 2 -.latch Ng2529 Ng2354 re PCLK 2 -.latch Ng11572 Ng2355 re PCLK 2 -.latch Ng2355 Ng2356 re PCLK 2 -.latch Ng11573 Ng2357 re PCLK 2 -.latch Ng2357 Ng2358 re PCLK 2 -.latch Ng11574 Ng2359 re PCLK 2 -.latch Ng2359 Ng2360 re PCLK 2 -.latch Ng11575 Ng2361 re PCLK 2 -.latch Ng2361 Ng2362 re PCLK 2 -.latch Ng11576 Ng2363 re PCLK 2 -.latch Ng2363 Ng2364 re PCLK 2 -.latch Ng13455 Ng2365 re PCLK 2 -.latch Ng2365 Ng2366 re PCLK 2 -.latch Ng19048 Ng2374 re PCLK 2 -.latch Ng30314 Ng2380 re PCLK 2 -.latch Ng27229 Ng2373 re PCLK 2 -.latch Ng11578 Ng2417 re PCLK 2 -.latch Ng2417 Ng2424 re PCLK 2 -.latch Ng11579 Ng2425 re PCLK 2 -.latch Ng2425 Ng2426 re PCLK 2 -.latch Ng11580 Ng2427 re PCLK 2 -.latch Ng2427 Ng2428 re PCLK 2 -.latch Ng11581 Ng2432 re PCLK 2 -.latch Ng2432 Ng2439 re PCLK 2 -.latch Ng11582 Ng2440 re PCLK 2 -.latch Ng2440 Ng2441 re PCLK 2 -.latch Ng11583 Ng2442 re PCLK 2 -.latch Ng2442 Ng2443 re PCLK 2 -.latch Ng11584 Ng2447 re PCLK 2 -.latch Ng2447 Ng2454 re PCLK 2 -.latch Ng11585 Ng2455 re PCLK 2 -.latch Ng2455 Ng2456 re PCLK 2 -.latch Ng11586 Ng2457 re PCLK 2 -.latch Ng2457 Ng2458 re PCLK 2 -.latch Ng11587 Ng2462 re PCLK 2 -.latch Ng2462 Ng2469 re PCLK 2 -.latch Ng11588 Ng2470 re PCLK 2 -.latch Ng2470 Ng2471 re PCLK 2 -.latch Ng11589 Ng2472 re PCLK 2 -.latch Ng2472 Ng2399 re PCLK 2 -.latch Ng23274 Ng2628 re PCLK 2 -.latch Ng20568 Ng2631 re PCLK 2 -.latch Ng20569 Ng2584 re PCLK 2 -.latch Ng16473 Ng2587 re PCLK 2 -.latch Ng2587 Ng2597 re PCLK 2 -.latch Ng2597 Ng2598 re PCLK 2 -.latch Ng11593 Ng2638 re PCLK 2 -.latch Ng2638 Ng2643 re PCLK 2 -.latch Ng11596 Ng2644 re PCLK 2 -.latch Ng2644 Ng2645 re PCLK 2 -.latch Ng11597 Ng2646 re PCLK 2 -.latch Ng2646 Ng2647 re PCLK 2 -.latch Ng11598 Ng2648 re PCLK 2 -.latch Ng2648 Ng2639 re PCLK 2 -.latch Ng11594 Ng2640 re PCLK 2 -.latch Ng2640 Ng2641 re PCLK 2 -.latch Ng11595 Ng2642 re PCLK 2 -.latch Ng2642 Ng2564 re PCLK 2 -.latch Ng24415 Ng2561 re PCLK 2 -.latch Ng24416 Ng2562 re PCLK 2 -.latch Ng24417 Ng2563 re PCLK 2 -.latch Ng25172 Ng11593 re PCLK 2 -.latch Ng25164 Ng11596 re PCLK 2 -.latch Ng25165 Ng11597 re PCLK 2 -.latch Ng25169 Ng2552 re PCLK 2 -.latch Ng25170 Ng2553 re PCLK 2 -.latch Ng25171 Ng2554 re PCLK 2 -.latch Ng24412 Ng2555 re PCLK 2 -.latch Ng24413 Ng2559 re PCLK 2 -.latch Ng24414 Ng2539 re PCLK 2 -.latch Ng25166 Ng11598 re PCLK 2 -.latch Ng25167 Ng11594 re PCLK 2 -.latch Ng25168 Ng11595 re PCLK 2 -.latch Ng16474 Ng2602 re PCLK 2 -.latch Ng2602 Ng2609 re PCLK 2 -.latch Ng2609 Ng2616 re PCLK 2 -.latch Ng19057 Ng2617 re PCLK 2 -.latch Ng2617 Ng2618 re PCLK 2 -.latch Ng30325 Ng2622 re PCLK 2 -.latch Ng19058 Ng2623 re PCLK 2 -.latch Ng2623 Ng8311 re PCLK 2 -.latch Ng19059 Ng2632 re PCLK 2 -.latch Ng2632 Ng2633 re PCLK 2 -.latch Ng28297 Ng2650 re PCLK 2 -.latch Ng28298 Ng2651 re PCLK 2 -.latch Ng28299 Ng2649 re PCLK 2 -.latch Ng28300 Ng2653 re PCLK 2 -.latch Ng28301 Ng2654 re PCLK 2 -.latch Ng28302 Ng2652 re PCLK 2 -.latch Ng28303 Ng2656 re PCLK 2 -.latch Ng28304 Ng2657 re PCLK 2 -.latch Ng28305 Ng2655 re PCLK 2 -.latch Ng28306 Ng2659 re PCLK 2 -.latch Ng28307 Ng2660 re PCLK 2 -.latch Ng28308 Ng2658 re PCLK 2 -.latch Ng26012 Ng2661 re PCLK 2 -.latch Ng26013 Ng2664 re PCLK 2 -.latch Ng26014 Ng2667 re PCLK 2 -.latch Ng26015 Ng2670 re PCLK 2 -.latch Ng26016 Ng2673 re PCLK 2 -.latch Ng26017 Ng2676 re PCLK 2 -.latch Ng29159 Ng2688 re PCLK 2 -.latch Ng29160 Ng2691 re PCLK 2 -.latch Ng29161 Ng2694 re PCLK 2 -.latch Ng29156 Ng2679 re PCLK 2 -.latch Ng29157 Ng2682 re PCLK 2 -.latch Ng29158 Ng2685 re PCLK 2 -.latch Ng27233 Ng2565 re PCLK 2 -.latch Ng27234 Ng2568 re PCLK 2 -.latch Ng27235 Ng2571 re PCLK 2 -.latch Ng8311 Ng2580 re PCLK 2 -.latch Ng24418 Ng2581 re PCLK 2 -.latch Ng30320 Pg16437 re PCLK 2 -.latch Pg16437 Ng2599 re PCLK 2 -.latch Ng13458 Ng2603 re PCLK 2 -.latch Ng13459 Ng2604 re PCLK 2 -.latch Ng13460 Ng2605 re PCLK 2 -.latch Ng13461 Ng2606 re PCLK 2 -.latch Ng13462 Ng2607 re PCLK 2 -.latch Ng13463 Ng2608 re PCLK 2 -.latch Ng13464 Ng2610 re PCLK 2 -.latch Ng13465 Ng2611 re PCLK 2 -.latch Ng26011 Ng2612 re PCLK 2 -.latch Ng13466 Ng2615 re PCLK 2 -.latch Ng20570 Ng2704 re PCLK 2 -.latch Ng21946 Ng2733 re PCLK 2 -.latch Ng23275 Ng2714 re PCLK 2 -.latch Ng24419 Ng2707 re PCLK 2 -.latch Ng25173 Ng2727 re PCLK 2 -.latch Ng26018 Ng2720 re PCLK 2 -.latch Ng26742 Ng2734 re PCLK 2 -.latch Ng27236 Ng2746 re PCLK 2 -.latch Ng27714 Ng2740 re PCLK 2 -.latch Ng28309 Ng2753 re PCLK 2 -.latch Ng28692 Ng2760 re PCLK 2 -.latch Ng29162 Ng2766 re PCLK 2 -.latch Ng23276 Ng2773 re PCLK 2 -.latch Ng23277 Ng2774 re PCLK 2 -.latch Ng23278 Ng2772 re PCLK 2 -.latch Ng23279 Ng2776 re PCLK 2 -.latch Ng23280 Ng2777 re PCLK 2 -.latch Ng23281 Ng2775 re PCLK 2 -.latch Ng23282 Ng2779 re PCLK 2 -.latch Ng23283 Ng2780 re PCLK 2 -.latch Ng23284 Ng2778 re PCLK 2 -.latch Ng23285 Ng2782 re PCLK 2 -.latch Ng23286 Ng2783 re PCLK 2 -.latch Ng23287 Ng2781 re PCLK 2 -.latch Ng23288 Ng2785 re PCLK 2 -.latch Ng23289 Ng2786 re PCLK 2 -.latch Ng23290 Ng2784 re PCLK 2 -.latch Ng23291 Ng2788 re PCLK 2 -.latch Ng23292 Ng2789 re PCLK 2 -.latch Ng23293 Ng2787 re PCLK 2 -.latch Ng23294 Ng2791 re PCLK 2 -.latch Ng23295 Ng2792 re PCLK 2 -.latch Ng23296 Ng2790 re PCLK 2 -.latch Ng23297 Ng2794 re PCLK 2 -.latch Ng23298 Ng2795 re PCLK 2 -.latch Ng23299 Ng2793 re PCLK 2 -.latch Ng23300 Ng2797 re PCLK 2 -.latch Ng23301 Ng2798 re PCLK 2 -.latch Ng23302 Ng2796 re PCLK 2 -.latch Ng23303 Ng2800 re PCLK 2 -.latch Ng23304 Ng2801 re PCLK 2 -.latch Ng23305 Ng2799 re PCLK 2 -.latch Ng23306 Ng2803 re PCLK 2 -.latch Ng23307 Ng2804 re PCLK 2 -.latch Ng23308 Ng2802 re PCLK 2 -.latch Ng23309 Ng2806 re PCLK 2 -.latch Ng23310 Ng2807 re PCLK 2 -.latch Ng23311 Ng2805 re PCLK 2 -.latch Ng26743 Ng2809 re PCLK 2 -.latch Ng26744 Ng2810 re PCLK 2 -.latch Ng26745 Ng2808 re PCLK 2 -.latch Ng24420 Ng2812 re PCLK 2 -.latch Ng24421 Ng2813 re PCLK 2 -.latch Ng24422 Ng2811 re PCLK 2 -.latch Ng23317 Ng3054 re PCLK 2 -.latch Ng23318 Ng3079 re PCLK 2 -.latch Ng21965 Ng13475 re PCLK 2 -.latch Ng29453 Ng3043 re PCLK 2 -.latch Ng29454 Ng3044 re PCLK 2 -.latch Ng29455 Ng3045 re PCLK 2 -.latch Ng29456 Ng3046 re PCLK 2 -.latch Ng29457 Ng3047 re PCLK 2 -.latch Ng29458 Ng3048 re PCLK 2 -.latch Ng29459 Ng3049 re PCLK 2 -.latch Ng29460 Ng3050 re PCLK 2 -.latch Ng29655 Ng3051 re PCLK 2 -.latch Ng29972 Ng3052 re PCLK 2 -.latch Ng29973 Ng3053 re PCLK 2 -.latch Ng29974 Ng3055 re PCLK 2 -.latch Ng29975 Ng3056 re PCLK 2 -.latch Ng29976 Ng3057 re PCLK 2 -.latch Ng29977 Ng3058 re PCLK 2 -.latch Ng29978 Ng3059 re PCLK 2 -.latch Ng29979 Ng3060 re PCLK 2 -.latch Ng30119 Ng3061 re PCLK 2 -.latch Ng30908 Ng3062 re PCLK 2 -.latch Ng30909 Ng3063 re PCLK 2 -.latch Ng30910 Ng3064 re PCLK 2 -.latch Ng30911 Ng3065 re PCLK 2 -.latch Ng30912 Ng3066 re PCLK 2 -.latch Ng30913 Ng3067 re PCLK 2 -.latch Ng30914 Ng3068 re PCLK 2 -.latch Ng30915 Ng3069 re PCLK 2 -.latch Ng30940 Ng3070 re PCLK 2 -.latch Ng30980 Ng3071 re PCLK 2 -.latch Ng30981 Ng3072 re PCLK 2 -.latch Ng30982 Ng3073 re PCLK 2 -.latch Ng30983 Ng3074 re PCLK 2 -.latch Ng30984 Ng3075 re PCLK 2 -.latch Ng30985 Ng3076 re PCLK 2 -.latch Ng30986 Ng3077 re PCLK 2 -.latch Ng30987 Ng3078 re PCLK 2 -.latch Ng30989 Ng2997 re PCLK 2 -.latch Ng26748 Ng2993 re PCLK 2 -.latch Ng27238 Ng2998 re PCLK 2 -.latch Ng25177 Ng3006 re PCLK 2 -.latch Ng26021 Ng3002 re PCLK 2 -.latch Ng26750 Ng3013 re PCLK 2 -.latch Ng27239 Ng3010 re PCLK 2 -.latch Ng27716 Ng3024 re PCLK 2 -.latch Ng24425 Ng3018 re PCLK 2 -.latch Ng25176 Ng3028 re PCLK 2 -.latch Ng26022 Ng3036 re PCLK 2 -.latch Ng26749 Ng3032 re PCLK 2 -.latch Pg3234 Pg5388 re PCLK 2 -.latch Pg5388 Ng2986 re PCLK 2 -.latch Pg16496 Ng2987 re PCLK 2 -.latch Ng20595 Pg8275 re PCLK 2 -.latch Ng20596 Pg8274 re PCLK 2 -.latch Ng20597 Pg8273 re PCLK 2 -.latch Ng20598 Pg8272 re PCLK 2 -.latch Ng20599 Pg8268 re PCLK 2 -.latch Ng20600 Pg8269 re PCLK 2 -.latch Ng20601 Pg8270 re PCLK 2 -.latch Ng20602 Pg8271 re PCLK 2 -.latch Ng20603 Ng3083 re PCLK 2 -.latch Ng20604 Pg8267 re PCLK 2 -.latch Ng21966 Ng2992 re PCLK 2 -.latch Ng20605 Pg8266 re PCLK 2 -.latch Ng20606 Pg8265 re PCLK 2 -.latch Ng20607 Pg8264 re PCLK 2 -.latch Ng20608 Pg8262 re PCLK 2 -.latch Ng20589 Pg8263 re PCLK 2 -.latch Ng20590 Pg8260 re PCLK 2 -.latch Ng20591 Pg8261 re PCLK 2 -.latch Ng20592 Pg8259 re PCLK 2 -.latch Ng20593 Ng2990 re PCLK 2 -.latch Ng21964 Ng2991 re PCLK 2 -.latch Ng20594 Pg8258 re PCLK 2 -.names Ng29656 Pg27380 -0 1 -.names n1770 Pg26149 -0 1 -.names Ng29166 Pg26135 -0 1 -.names n1778 Pg26104 -0 1 -.names n3323 Pg25489 -0 1 -.names Pg3233 Pg3230 [1521] -0- 1 --1 1 -.names Ng28696 Pg25435 -0 1 -.names Ng28313 Pg24734 -0 1 -.names n188 Pg16496 -0 1 -.names Pg8269 Pg8268 n1139 -01 1 -10 1 -.names Pg8271 Pg8270 n1138 -01 1 -10 1 -.names n1139 n1138 n1137 -01 1 -10 1 -.names Pg8262 Pg8264 n1142 -01 1 -10 1 -.names Pg8265 Pg8266 n1141 -01 1 -10 1 -.names n1142 n1141 n1140 -01 1 -10 1 -.names Pg8259 Pg8261 n1145 -01 1 -10 1 -.names Pg8260 Pg8263 n1144 -01 1 -10 1 -.names n1145 n1144 n1143 -01 1 -10 1 -.names Pg8272 Pg8273 n1148 -01 1 -10 1 -.names Pg8275 Pg8274 n1147 -01 1 -10 1 -.names n1148 n1147 n1146 -01 1 -10 1 -.names [1605] Ng1315 Ng324 Ng394 n69 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n69 Ng396 n66 -01- 1 --10 1 -.names [1605] Ng1315 Ng383 Ng379 n72 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n72 Ng381 n70 -01- 1 --10 1 -.names [1605] Ng1315 Ng1011 Ng1081 n75 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n75 Ng1083 n73 -01- 1 --10 1 -.names [1605] Ng1315 Ng368 Ng364 n78 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n78 Ng366 n76 -01- 1 --10 1 -.names [1605] Ng1315 Ng1070 Ng1066 n81 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n81 Ng1068 n79 -01- 1 --10 1 -.names [1605] Ng1315 Ng1705 Ng1775 n84 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n84 Ng1777 n82 -01- 1 --10 1 -.names [1605] Ng1315 Ng353 Ng349 n87 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n87 Ng351 n85 -01- 1 --10 1 -.names [1605] Ng1315 Ng1055 Ng1051 n90 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n90 Ng1053 n88 -01- 1 --10 1 -.names [1605] Ng1315 Ng1764 Ng1760 n93 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n93 Ng1762 n91 -01- 1 --10 1 -.names [1605] Ng1315 Ng2399 Ng2469 n96 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n96 Ng2471 n94 -01- 1 --10 1 -.names [1605] Ng1315 Ng1040 Ng1036 n99 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n99 Ng1038 n97 -01- 1 --10 1 -.names [1605] Ng1315 Ng1749 Ng1745 n102 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n102 Ng1747 n100 -01- 1 --10 1 -.names [1605] Ng1315 Ng2458 Ng2454 n105 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n105 Ng2456 n103 -01- 1 --10 1 -.names [1605] Ng1315 Ng1734 Ng1730 n108 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n108 Ng1732 n106 -01- 1 --10 1 -.names [1605] Ng1315 Ng2443 Ng2439 n111 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n111 Ng2441 n109 -01- 1 --10 1 -.names [1605] Ng1315 Ng2428 Ng2424 n114 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n114 Ng2426 n112 -01- 1 --10 1 -.names [1605] Ng1315 Ng496 Ng490 n117 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n117 Ng493 n115 -01- 1 --10 1 -.names [1605] Ng1315 Ng1183 Ng1177 n120 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n120 Ng1180 n118 -01- 1 --10 1 -.names [1605] Ng1315 Ng1877 Ng1871 n123 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n123 Ng1874 n121 -01- 1 --10 1 -.names [1605] Ng1315 Ng2571 Ng2565 n126 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n126 Ng2568 n124 -01- 1 --10 1 -.names [1612] Ng853 Ng448 Ng447 n129 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names [1594] n129 Ng449 n127 -01- 1 --11 1 -.names [1612] Ng853 Ng402 Ng403 n131 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n131 Ng404 n130 -01- 1 --11 1 -.names [1603] [1605] Ng479 Ng477 n133 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng1315 n133 Ng478 Ng19021 -01- 1 --11 1 -.names [1603] [1605] Ng464 Ng480 n134 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng1315 n134 Ng484 Ng19022 -01- 1 --11 1 -.names [1612] Ng853 Ng1135 Ng1134 n136 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names [1594] n136 Ng1136 n135 -01- 1 --11 1 -.names [1612] Ng853 Ng1089 Ng1090 n138 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n138 Ng1091 n137 -01- 1 --11 1 -.names [1603] [1605] Ng1166 Ng1164 n139 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng1315 n139 Ng1165 Ng19033 -01- 1 --11 1 -.names [1603] [1605] Ng488 Ng486 n140 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng1315 n140 Ng487 Ng19023 -01- 1 --11 1 -.names [1603] [1605] Ng1151 Ng1167 n141 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng1315 n141 Ng1171 Ng19034 -01- 1 --11 1 -.names [1612] Ng853 Ng1829 Ng1828 n143 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names [1594] n143 Ng1830 n142 -01- 1 --11 1 -.names [1612] Ng853 Ng1783 Ng1784 n145 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n145 Ng1785 n144 -01- 1 --11 1 -.names [1603] [1605] Ng1860 Ng1858 n146 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng1315 n146 Ng1859 Ng19045 -01- 1 --11 1 -.names [1605] Ng1315 Ng573 Ng569 n148 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n148 Ng571 Ng16467 -01- 1 --10 1 -.names [1603] [1605] Ng1175 Ng1173 n149 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng1315 n149 Ng1174 Ng19035 -01- 1 --11 1 -.names [1603] [1605] Ng1845 Ng1861 n150 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng1315 n150 Ng1865 Ng19046 -01- 1 --11 1 -.names [1612] Ng853 Ng2523 Ng2522 n152 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names [1594] n152 Ng2524 n151 -01- 1 --11 1 -.names [1612] Ng853 Ng2477 Ng2478 n154 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n154 Ng2479 n153 -01- 1 --11 1 -.names [1603] [1605] Ng2554 Ng2552 n155 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng1315 n155 Ng2553 Ng19057 -01- 1 --11 1 -.names [1605] Ng1315 Ng1259 Ng1255 n157 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n157 Ng1257 Ng16469 -01- 1 --10 1 -.names [1603] [1605] Ng1869 Ng1867 n158 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng1315 n158 Ng1868 Ng19047 -01- 1 --11 1 -.names [1603] [1605] Ng2539 Ng2555 n159 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng1315 n159 Ng2559 Ng19058 -01- 1 --11 1 -.names [1612] Ng853 Ng321 Ng322 n161 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n161 Ng323 n160 -01- 1 --11 1 -.names [1605] Ng1315 Ng1953 Ng1949 n163 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n163 Ng1951 Ng16471 -01- 1 --10 1 -.names [1603] [1605] Ng2563 Ng2561 n164 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng1315 n164 Ng2562 Ng19059 -01- 1 --11 1 -.names [1605] Ng1315 Ng489 Ng565 n166 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n166 Ng567 Ng16468 -01- 1 --10 1 -.names [1612] Ng853 Ng1008 Ng1009 n168 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n168 Ng1010 n167 -01- 1 --11 1 -.names [1605] Ng1315 Ng2647 Ng2643 n170 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n170 Ng2645 Ng16473 -01- 1 --10 1 -.names [1605] Ng1315 Ng1176 Ng1251 n172 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n172 Ng1253 Ng16470 -01- 1 --10 1 -.names [1612] Ng853 Ng1702 Ng1703 n174 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n174 Ng1704 n173 -01- 1 --11 1 -.names [1605] Ng1315 Ng1870 Ng1945 n176 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n176 Ng1947 Ng16472 -01- 1 --10 1 -.names [1612] Ng853 Ng2396 Ng2397 n178 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n178 Ng2398 n177 -01- 1 --11 1 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Ng1531 n217 -01- 1 --11 1 -.names [1612] Ng853 Ng2220 Ng2221 n220 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n220 Ng2222 n219 -01- 1 --11 1 -.names [1612] Ng853 Ng156 Ng157 n222 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n222 Ng158 n221 -01- 1 --11 1 -.names [1612] Ng853 Ng237 Ng231 n225 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n225 Ng234 n223 -01- 1 --10 1 -.names [1605] Ng1315 Ng698 Ng699 n227 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n227 Ng700 n226 -01- 1 --11 1 -.names [1605] Ng1315 Ng725 Ng726 n229 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n229 Ng727 n228 -01- 1 --11 1 -.names [1612] Ng853 Ng841 Ng842 n231 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n231 Ng843 n230 -01- 1 --11 1 -.names [1612] Ng853 Ng915 Ng909 n234 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n234 Ng912 n232 -01- 1 --10 1 -.names [1612] Ng853 Ng1532 Ng1533 n236 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n236 Ng1534 n235 -01- 1 --11 1 -.names [1612] Ng853 Ng1600 Ng1594 n239 -00-- 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--11 1 -.names [1612] Ng853 Ng1535 Ng1536 n259 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n259 Ng1537 n258 -01- 1 --11 1 -.names [1612] Ng853 Ng1609 Ng1603 n262 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n262 Ng1606 n260 -01- 1 --10 1 -.names [1612] Ng853 Ng2226 Ng2227 n264 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n264 Ng2228 n263 -01- 1 --11 1 -.names [1612] Ng853 Ng2294 Ng2288 n267 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n267 Ng2291 n265 -01- 1 --10 1 -.names [1612] Ng853 Ng129 Ng130 n269 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n269 Ng131 n268 -01- 1 --11 1 -.names [1612] Ng853 Ng162 Ng163 n271 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n271 Ng164 n270 -01- 1 --11 1 -.names [1612] Ng853 Ng255 Ng249 n274 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n274 Ng252 n272 -01- 1 --10 1 -.names [1605] Ng1315 Ng704 Ng705 n276 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n276 Ng706 n275 -01- 1 --11 1 -.names [1612] Ng853 Ng847 Ng848 n278 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n278 Ng849 n277 -01- 1 --11 1 -.names [1612] Ng853 Ng933 Ng927 n281 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n281 Ng930 n279 -01- 1 --10 1 -.names [1605] Ng1315 Ng1387 Ng1388 n283 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n283 Ng1389 n282 -01- 1 --11 1 -.names [1612] Ng853 Ng1538 Ng1539 n285 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n285 Ng1540 n284 -01- 1 --11 1 -.names [1612] Ng853 Ng1618 Ng1612 n288 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n288 Ng1615 n286 -01- 1 --10 1 -.names [1605] Ng1315 Ng2078 Ng2079 n290 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n290 Ng2080 n289 -01- 1 --11 1 -.names [1605] Ng1315 Ng2105 Ng2106 n292 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n292 Ng2107 n291 -01- 1 --11 1 -.names [1612] Ng853 Ng2229 Ng2230 n294 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n294 Ng2231 n293 -01- 1 --11 1 -.names [1612] Ng853 Ng2303 Ng2297 n297 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n297 Ng2300 n295 -01- 1 --10 1 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[1612] Ng853 Ng273 Ng267 n340 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n340 Ng270 n338 -01- 1 --10 1 -.names [1612] Ng853 Ng11502 Ng11500 n342 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n342 Ng11501 n341 -01- 1 --11 1 -.names [1612] Ng853 Ng444 Ng438 n345 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n345 Ng441 n343 -01- 1 --10 1 -.names [1605] Ng1315 Ng710 Ng711 n347 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n347 Ng712 n346 -01- 1 --11 1 -.names [1612] Ng853 Ng820 Ng821 n349 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n349 Ng822 n348 -01- 1 --11 1 -.names [1612] Ng853 Ng951 Ng945 n352 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n352 Ng948 n350 -01- 1 --10 1 -.names [1612] Ng853 Ng11526 Ng11524 n354 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n354 Ng11525 n353 -01- 1 --11 1 -.names [1612] Ng853 Ng1122 Ng1116 n357 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n357 Ng1119 n355 -01- 1 --10 1 -.names [1605] Ng1315 Ng1393 Ng1394 n359 -00-- 1 -0-1- 1 --0-1 1 ---11 1 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[1612] Ng853 Ng11505 Ng11503 n380 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n380 Ng11504 n379 -01- 1 --11 1 -.names [1605] Ng1315 Ng713 Ng714 n382 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n382 Ng715 n381 -01- 1 --11 1 -.names [1605] Ng1315 Ng731 Ng732 n384 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n384 Ng733 n383 -01- 1 --11 1 -.names [1612] Ng853 Ng879 Ng873 n387 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n387 Ng876 n385 -01- 1 --10 1 -.names [1612] Ng853 Ng960 Ng954 n390 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n390 Ng957 n388 -01- 1 --10 1 -.names [1612] Ng853 Ng11529 Ng11527 n392 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n392 Ng11528 n391 -01- 1 --11 1 -.names [1612] Ng853 Ng1131 Ng1125 n395 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n395 Ng1128 n393 -01- 1 --10 1 -.names [1605] Ng1315 Ng1396 Ng1397 n397 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n397 Ng1398 n396 -01- 1 --11 1 -.names [1612] Ng853 Ng1514 Ng1515 n399 -00-- 1 -0-1- 1 --0-1 1 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1 --0-0 1 ---00 1 -.names [1594] n440 Ng1651 n438 -01- 1 --10 1 -.names [1612] Ng853 Ng11556 Ng11554 n442 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n442 Ng11555 n441 -01- 1 --11 1 -.names [1612] Ng853 Ng1825 Ng1819 n445 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n445 Ng1822 n443 -01- 1 --10 1 -.names [1605] Ng1315 Ng2090 Ng2091 n447 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n447 Ng2092 n446 -01- 1 --11 1 -.names [1612] Ng853 Ng2208 Ng2209 n449 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n449 Ng2210 n448 -01- 1 --11 1 -.names [1612] Ng853 Ng2339 Ng2333 n452 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n452 Ng2336 n450 -01- 1 --10 1 -.names [1612] Ng853 Ng11580 Ng11578 n454 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n454 Ng11579 n453 -01- 1 --11 1 -.names [1612] Ng853 Ng2510 Ng2504 n457 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n457 Ng2507 n455 -01- 1 --10 1 -.names [1605] Ng1315 Ng2781 Ng2782 n459 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n459 Ng2783 n458 -01- 1 --11 1 -.names [1594] Ng853 Ng168 Ng170 n461 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1612] n461 Ng169 n460 -01- 1 --11 1 -.names [1605] Ng1315 Ng719 Ng720 n463 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n463 Ng721 n462 -01- 1 --11 1 -.names [1612] Ng853 Ng897 Ng891 n466 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n466 Ng894 n464 -01- 1 --10 1 -.names [1612] Ng853 Ng11535 Ng11533 n468 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n468 Ng11534 n467 -01- 1 --11 1 -.names [1605] Ng1315 Ng1402 Ng1403 n470 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n470 Ng1404 n469 -01- 1 --11 1 -.names [1612] Ng853 Ng1582 Ng1576 n473 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n473 Ng1579 n471 -01- 1 --10 1 -.names [1612] Ng853 Ng11559 Ng11557 n475 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n475 Ng11558 n474 -01- 1 --11 1 -.names [1605] Ng1315 Ng2093 Ng2094 n477 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n477 Ng2095 n476 -01- 1 --11 1 -.names [1605] Ng1315 Ng2111 Ng2112 n479 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n479 Ng2113 n478 -01- 1 --11 1 -.names [1612] Ng853 Ng2267 Ng2261 n482 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n482 Ng2264 n480 -01- 1 --10 1 -.names [1612] Ng853 Ng2348 Ng2342 n485 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n485 Ng2345 n483 -01- 1 --10 1 -.names [1612] Ng853 Ng11583 Ng11581 n487 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n487 Ng11582 n486 -01- 1 --11 1 -.names [1612] Ng853 Ng2519 Ng2513 n490 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n490 Ng2516 n488 -01- 1 --10 1 -.names [1605] Ng1315 Ng2784 Ng2785 n492 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n492 Ng2786 n491 -01- 1 --11 1 -.names [1605] Ng1315 Ng722 Ng723 n494 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n494 Ng724 n493 -01- 1 --11 1 -.names [1594] Ng853 Ng856 Ng858 n496 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1612] n496 Ng857 n495 -01- 1 --11 1 -.names [1605] Ng1315 Ng1405 Ng1406 n498 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n498 Ng1407 n497 -01- 1 --11 1 -.names [1612] Ng853 Ng1591 Ng1585 n501 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n501 Ng1588 n499 -01- 1 --10 1 -.names [1612] Ng853 Ng11562 Ng11560 n503 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n503 Ng11561 n502 -01- 1 --11 1 -.names [1605] Ng1315 Ng2096 Ng2097 n505 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n505 Ng2098 n504 -01- 1 --11 1 -.names [1612] Ng853 Ng2276 Ng2270 n508 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n508 Ng2273 n506 -01- 1 --10 1 -.names [1612] Ng853 Ng11586 Ng11584 n510 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n510 Ng11585 n509 -01- 1 --11 1 -.names [1605] Ng1315 Ng2787 Ng2788 n512 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n512 Ng2789 n511 -01- 1 --11 1 -.names [1605] Ng1315 Ng2805 Ng2806 n514 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n514 Ng2807 n513 -01- 1 --11 1 -.names [1605] Ng1315 Ng1408 Ng1409 n516 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n516 Ng1410 n515 -01- 1 --11 1 -.names [1612] Ng853 Ng1550 Ng1551 n518 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n518 Ng1552 n517 -01- 1 --11 1 -.names [1605] Ng1315 Ng2099 Ng2100 n520 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n520 Ng2101 n519 -01- 1 --11 1 -.names [1612] Ng853 Ng2285 Ng2279 n523 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n523 Ng2282 n521 -01- 1 --10 1 -.names [1612] Ng853 Ng11589 Ng11587 n525 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n525 Ng11588 n524 -01- 1 --11 1 -.names [1605] Ng1315 Ng2790 Ng2791 n527 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n527 Ng2792 n526 -01- 1 --11 1 -.names [1605] Ng1315 Ng2102 Ng2103 n529 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n529 Ng2104 n528 -01- 1 --11 1 -.names [1612] Ng853 Ng2244 Ng2245 n531 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n531 Ng2246 n530 -01- 1 --11 1 -.names [1605] Ng1315 Ng2793 Ng2794 n533 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n533 Ng2795 n532 -01- 1 --11 1 -.names [1612] Ng853 Ng314 Ng312 n535 -00-- 1 -0-1- 1 --0-1 1 ---11 1 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Ng853 Ng1698 Ng1696 n554 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n554 Ng1697 n553 -01- 1 --11 1 -.names [1612] Ng853 Ng2389 Ng2387 n556 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n556 Ng2388 n555 -01- 1 --11 1 -.names [1605] Ng1315 Ng1306 Ng1300 n559 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n559 Ng1303 n557 -01- 1 --10 1 -.names [1612] Ng853 Ng1701 Ng1699 n561 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n561 Ng1700 n560 -01- 1 --11 1 -.names [1612] Ng853 Ng2392 Ng2390 n563 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n563 Ng2391 n562 -01- 1 --11 1 -.names [1605] Ng1315 Ng2000 Ng1994 n566 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n566 Ng1997 n564 -01- 1 --10 1 -.names [1612] Ng853 Ng2395 Ng2393 n568 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1594] n568 Ng2394 n567 -01- 1 --11 1 -.names [1605] Ng1315 Ng2694 Ng2688 n571 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1603] n571 Ng2691 n569 -01- 1 --10 1 -.names [1605] Ng1315 Ng575 Ng576 n573 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n573 Ng577 n572 -01- 1 --11 1 -.names [1605] Ng1315 Ng578 Ng579 n575 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n575 Ng580 n574 -01- 1 --11 1 -.names [1605] Ng1315 Ng1261 Ng1262 n577 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n577 Ng1263 n576 -01- 1 --11 1 -.names [1612] Ng853 Ng414 Ng408 n580 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n580 Ng411 n578 -01- 1 --10 1 -.names [1605] Ng1315 Ng581 Ng582 n582 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n582 Ng583 n581 -01- 1 --11 1 -.names [1605] Ng1315 Ng1264 Ng1265 n584 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n584 Ng1266 n583 -01- 1 --11 1 -.names [1605] Ng1315 Ng1955 Ng1956 n586 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n586 Ng1957 n585 -01- 1 --11 1 -.names [1612] Ng853 Ng423 Ng417 n589 -00-- 1 -0-0- 1 --0-0 1 ---00 1 -.names [1594] n589 Ng420 n587 -01- 1 --10 1 -.names [1605] Ng1315 Ng584 Ng585 n591 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1603] n591 Ng586 n590 -01- 1 --11 1 -.names [1612] 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n2706 n751 -11 1 -.names n752 Ng737 n751 Ng24299 -11- 1 -1-1 1 -.names [1603] n2705 n753 -11 1 -.names n709 Ng1425 n753 Ng24339 -11- 1 -1-1 1 -.names [1605] Ng2010 n755 -0- 1 --0 1 -.names [1605] n2704 n754 -11 1 -.names n755 Ng2118 n754 Ng24379 -11- 1 -1-1 1 -.names [1605] n3876 n3877 Ng1415 n757 -011- 1 --111 1 -.names [1603] n433 n757 Ng1416 n756 -011- 1 --111 1 -.names Ng1315 Ng1316 n759 -0- 1 --0 1 -.names Ng1315 n2705 n758 -11 1 -.names n759 Ng1423 n758 Ng24340 -11- 1 -1-1 1 -.names [1603] n2704 n760 -11 1 -.names n711 Ng2119 n760 Ng24380 -11- 1 -1-1 1 -.names [1605] Ng2704 n762 -0- 1 --0 1 -.names [1605] n2702 n761 -11 1 -.names n762 Ng2812 n761 Ng24420 -11- 1 -1-1 1 -.names [1605] n3873 n3874 Ng2109 n764 -011- 1 --111 1 -.names [1603] n478 n764 Ng2110 n763 -011- 1 --111 1 -.names Ng1315 Ng2010 n766 -0- 1 --0 1 -.names Ng1315 n2704 n765 -11 1 -.names n766 Ng2117 n765 Ng24381 -11- 1 -1-1 1 -.names [1603] n2702 n767 -11 1 -.names n713 Ng2813 n767 Ng24421 -11- 1 -1-1 1 -.names [1605] n3870 n3871 Ng2803 n769 -011- 1 --111 1 -.names [1603] n513 n769 Ng2804 n768 -011- 1 --111 1 -.names Ng1315 Ng2704 n771 -0- 1 --0 1 -.names Ng1315 n2702 n770 -11 1 -.names n771 Ng2811 n770 Ng24422 -11- 1 -1-1 1 -.names [1521] n1527 Ng3123 Ng28313 -01- 1 -0-1 1 -.names Ng653 n1945 n772 -01 1 -10 1 -.names n772 n707 Ng25140 -11 1 -.names Ng1339 n1943 n773 -01 1 -10 1 -.names n773 n709 Ng25151 -11 1 -.names n2694 Ng3006 n775 -01 1 -10 1 -.names n775 n1905 Ng25177 -10 1 -.names Ng2033 n1941 n776 -01 1 -10 1 -.names n776 n711 Ng25162 -11 1 -.names Ng2727 n1939 n777 -01 1 -10 1 -.names n777 n713 Ng25173 -11 1 -.names Ng2917 n1937 n778 -01 1 -10 1 -.names n734 n778 Ng25174 -01 1 -.names n1934 Ng2896 n780 -01 1 -10 1 -.names n714 n780 Ng25175 -01 1 -.names Ng3028 n1935 n781 -01 1 -10 1 -.names n737 n781 Ng25176 -01 1 -.names [1521] n1527 Ng3125 Ng28696 -01- 1 -0-1 1 -.names n1927 Ng646 n783 -01 1 -10 1 -.names n783 n707 Ng25991 -11 1 -.names n1923 Ng1332 n784 -01 1 -10 1 -.names n784 n709 Ng26000 -11 1 -.names n1919 Ng2026 n785 -01 1 -10 1 -.names n785 n711 Ng26009 -11 1 -.names n1914 Ng2720 n786 -01 1 -10 1 -.names n786 n713 Ng26018 -11 1 -.names n1930 Ng3002 n787 -11 1 -00 1 -.names n787 n1905 Ng26021 -10 1 -.names n1907 Ng3036 n788 -01 1 -10 1 -.names n737 n788 Ng26022 -01 1 -.names Ng2892 n1933 n789 -01 1 -10 1 -.names n714 n789 Ng26019 -01 1 -.names n1912 Ng2924 n790 -01 1 -10 1 -.names n734 n790 Ng26020 -01 1 -.names n1928 Ng88 n791 -11 1 -00 1 -.names n2450 n721 n792 -1- 1 --1 1 -.names n791 n792 Ng26678 -11 1 -.names n1924 Ng776 n793 -11 1 -00 1 -.names n793 n792 Ng26695 -11 1 -.names n1920 Ng1462 n794 -11 1 -00 1 -.names n794 n792 Ng26712 -11 1 -.names n1915 Ng2156 n795 -11 1 -00 1 -.names n795 n792 Ng26729 -11 1 -.names n1620 n1621 n1622 n1623 n1624 n1625 n1626 n1627 Ng29166 -11111111 1 -.names Ng660 n1926 n796 -01 1 -10 1 -.names n796 n707 Ng26691 -11 1 -.names Ng1346 n1922 n797 -01 1 -10 1 -.names n797 n709 Ng26708 -11 1 -.names Ng3013 n2695 n798 -11 1 -00 1 -.names n798 n1905 Ng26750 -10 1 -.names Ng2040 n1918 n799 -01 1 -10 1 -.names n799 n711 Ng26725 -11 1 -.names Ng2734 n1913 n800 -01 1 -10 1 -.names n800 n713 Ng26742 -11 1 -.names Ng2920 n1911 n801 -01 1 -10 1 -.names n734 n801 Ng26746 -01 1 -.names n2699 Ng2903 n802 -01 1 -10 1 -.names n714 n802 Ng26747 -01 1 -.names Ng3032 n1906 n803 -01 1 -10 1 -.names n737 n803 Ng26749 -01 1 -.names n1885 Ng83 n804 -01 1 -10 1 -.names n804 n792 Ng27189 -11 1 -.names n1881 Ng771 n805 -01 1 -10 1 -.names n805 n792 Ng27198 -11 1 -.names n1877 Ng1457 n806 -01 1 -10 1 -.names n806 n792 Ng27219 -11 1 -.names n1873 Ng2151 n807 -01 1 -10 1 -.names n807 n792 Ng27228 -11 1 -.names n1883 Ng672 n808 -01 1 -10 1 -.names n808 n707 Ng27197 -11 1 -.names n1879 Ng1358 n809 -01 1 -10 1 -.names n809 n709 Ng27218 -11 1 -.names n1875 Ng2052 n810 -01 1 -10 1 -.names n810 n711 Ng27227 -11 1 -.names n1871 Ng2746 n811 -01 1 -10 1 -.names n811 n713 Ng27236 -11 1 -.names n1867 Ng3010 n812 -11 1 -00 1 -.names n812 n1905 Ng27239 -10 1 -.names Ng2900 n1869 n813 -01 1 -10 1 -.names n714 n813 Ng27237 -01 1 -.names Ng79 n1884 n814 -01 1 -10 1 -.names n814 n792 Ng27683 -11 1 -.names Ng767 n1880 n815 -01 1 -10 1 -.names n815 n792 Ng27691 -11 1 -.names Ng1453 n1876 n816 -01 1 -10 1 -.names n816 n792 Ng27699 -11 1 -.names Ng2147 n1872 n817 -01 1 -10 1 -.names n817 n792 Ng27707 -11 1 -.names [1521] n1529 Ng185 n1527 Ng29656 -011- 1 -01-1 1 -.names Ng666 n1882 n818 -01 1 -10 1 -.names n818 n707 Ng27690 -11 1 -.names Ng1352 n1878 n819 -01 1 -10 1 -.names n819 n709 Ng27698 -11 1 -.names n1905 n2714 Ng27716 -00 1 -.names Ng2046 n1874 n821 -01 1 -10 1 -.names n821 n711 Ng27706 -11 1 -.names Ng2740 n1870 n822 -01 1 -10 1 -.names n822 n713 Ng27714 -11 1 -.names Ng2908 n1868 n823 -01 1 -10 1 -.names n714 n823 Ng27715 -01 1 -.names n1826 Ng74 n824 -01 1 -10 1 -.names n824 n792 Ng28206 -11 1 -.names n1816 Ng762 n825 -01 1 -10 1 -.names n825 n792 Ng28232 -11 1 -.names n1806 Ng1448 n826 -01 1 -10 1 -.names n826 n792 Ng28258 -11 1 -.names n1796 Ng2142 n827 -01 1 -10 1 -.names n827 n792 Ng28284 -11 1 -.names n2599 Ng679 n828 -01 1 -10 1 -.names n828 n707 Ng28231 -11 1 -.names n2575 Ng1365 n829 -01 1 -10 1 -.names n829 n709 Ng28257 -11 1 -.names n2551 Ng2059 n830 -01 1 -10 1 -.names n830 n711 Ng28283 -11 1 -.names n2523 Ng2753 n831 -01 1 -10 1 -.names n831 n713 Ng28309 -11 1 -.names n1437 n1439 n1440 n833 -111 1 -.names n208 n1481 n834 -11 1 -00 1 -.names n833 n834 n832 -11 1 -.names n1404 n1406 n1407 n836 -111 1 -.names n232 n1473 n837 -11 1 -00 1 -.names n836 n837 n835 -11 1 -.names n1371 n1373 n1374 n839 -111 1 -.names n260 n1465 n840 -11 1 -00 1 -.names n839 n840 n838 -11 1 -.names n1338 n1340 n1341 n842 -111 1 -.names n295 n1457 n843 -11 1 -00 1 -.names n842 n843 n841 -11 1 -.names Ng70 n1825 n844 -01 1 -10 1 -.names n844 n792 Ng28673 -11 1 -.names Ng758 n1815 n845 -01 1 -10 1 -.names n845 n792 Ng28678 -11 1 -.names Ng1444 n1805 n846 -01 1 -10 1 -.names n846 n792 Ng28683 -11 1 -.names Ng2138 n1795 n847 -01 1 -10 1 -.names n847 n792 Ng28688 -11 1 -.names Ng686 n1734 n848 -01 1 -10 1 -.names n848 n707 Ng28677 -11 1 -.names Ng1372 n1699 n849 -01 1 -10 1 -.names n849 n709 Ng28682 -11 1 -.names Ng2066 n1664 n850 -01 1 -10 1 -.names n850 n711 Ng28687 -11 1 -.names Ng2760 n1629 n851 -01 1 -10 1 -.names n851 n713 Ng28692 -11 1 -.names n127 Ng2257 n2680 n852 -0-- 1 --0- 1 ---1 1 -.names [1612] n1821 n853 -10 1 -.names [1612] n852 n853 Ng448 Ng28674 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names [1594] n1821 n854 -10 1 -.names [1594] Ng449 n852 n854 Ng28675 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names n135 Ng2257 n2671 n855 -0-- 1 --0- 1 ---1 1 -.names [1612] n1811 n856 -10 1 -.names [1612] n855 n856 Ng1135 Ng28679 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names Ng853 n1821 n857 -10 1 -.names Ng853 n852 n857 Ng447 Ng28676 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names [1594] n1811 n858 -10 1 -.names [1594] Ng1136 n855 n858 Ng28680 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names n142 Ng2257 n2662 n859 -0-- 1 --0- 1 ---1 1 -.names [1612] n1801 n860 -10 1 -.names [1612] n859 n860 Ng1829 Ng28684 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names Ng853 n1811 n861 -10 1 -.names Ng853 n855 n861 Ng1134 Ng28681 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names [1594] n1801 n862 -10 1 -.names [1594] Ng1830 n859 n862 Ng28685 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names n151 Ng2257 n2653 n863 -0-- 1 --0- 1 ---1 1 -.names [1612] n1790 n864 -10 1 -.names [1612] n863 n864 Ng2523 Ng28689 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names Ng853 n1801 n865 -10 1 -.names Ng853 n859 n865 Ng1828 Ng28686 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names [1594] n1790 n866 -10 1 -.names [1594] Ng2524 n863 n866 Ng28690 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names Ng853 n1790 n867 -10 1 -.names Ng853 n863 n867 Ng2522 Ng28691 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n1619 Ng65 n868 -01 1 -10 1 -.names n868 n792 Ng29131 -11 1 -.names n1612 Ng753 n869 -01 1 -10 1 -.names n869 n792 Ng29139 -11 1 -.names n1605 Ng1439 n870 -01 1 -10 1 -.names n870 n792 Ng29147 -11 1 -.names n1598 Ng2133 n871 -01 1 -10 1 -.names n871 n792 Ng29155 -11 1 -.names Ng692 n1733 n872 -01 1 -10 1 -.names n872 n707 Ng29138 -11 1 -.names Ng1378 n1698 n873 -01 1 -10 1 -.names n873 n709 Ng29146 -11 1 -.names Ng2072 n1663 n874 -01 1 -10 1 -.names n874 n711 Ng29154 -11 1 -.names Ng2766 n1628 n875 -01 1 -10 1 -.names n875 n713 Ng29162 -11 1 -.names Ng61 n1618 n876 -01 1 -10 1 -.names n876 n792 Ng29413 -11 1 -.names Ng749 n1611 n877 -01 1 -10 1 -.names n877 n792 Ng29420 -11 1 -.names Ng1435 n1604 n878 -01 1 -10 1 -.names n878 n792 Ng29427 -11 1 -.names Ng2129 n1597 n879 -01 1 -10 1 -.names n879 n792 Ng29446 -11 1 -.names [1612] n2495 n881 -0- 1 --1 1 -.names n578 n1205 Ng2257 n880 -101 1 -.names n881 Ng427 [1612] n880 Ng29417 -11-- 1 -1-11 1 -.names [1594] n2495 n882 -0- 1 --1 1 -.names n882 Ng428 [1594] n880 Ng29418 -11-- 1 -1-11 1 -.names [1612] n2493 n884 -0- 1 --1 1 -.names n592 n1208 Ng2257 n883 -101 1 -.names n884 Ng1114 [1612] n883 Ng29424 -11-- 1 -1-11 1 -.names Ng853 n2495 n885 -0- 1 --1 1 -.names n885 Ng426 Ng853 n880 Ng29419 -11-- 1 -1-11 1 -.names [1594] n2493 n886 -0- 1 --1 1 -.names n886 Ng1115 [1594] n883 Ng29425 -11-- 1 -1-11 1 -.names [1612] n2491 n888 -0- 1 --1 1 -.names n606 n1211 Ng2257 n887 -101 1 -.names n888 Ng1808 [1612] n887 Ng29437 -11-- 1 -1-11 1 -.names Ng853 n2493 n889 -0- 1 --1 1 -.names n889 Ng1113 Ng853 n883 Ng29426 -11-- 1 -1-11 1 -.names [1594] n2491 n890 -0- 1 --1 1 -.names n890 Ng1809 [1594] n887 Ng29438 -11-- 1 -1-11 1 -.names [1612] n2489 n892 -0- 1 --1 1 -.names n620 n1214 Ng2257 n891 -101 1 -.names n892 Ng2502 [1612] n891 Ng29450 -11-- 1 -1-11 1 -.names Ng853 n2491 n893 -0- 1 --1 1 -.names n893 Ng1807 Ng853 n887 Ng29439 -11-- 1 -1-11 1 -.names [1594] n2489 n894 -0- 1 --1 1 -.names n894 Ng2503 [1594] n891 Ng29451 -11-- 1 -1-11 1 -.names Ng853 n2489 n895 -0- 1 --1 1 -.names n895 Ng2501 Ng853 n891 Ng29452 -11-- 1 -1-11 1 -.names n1522 Ng56 n896 -01 1 -10 1 -.names n896 n792 Ng29627 -11 1 -.names n1518 Ng744 n897 -01 1 -10 1 -.names n897 n792 Ng29634 -11 1 -.names n1514 Ng1430 n898 -01 1 -10 1 -.names n898 n792 Ng29641 -11 1 -.names n1510 Ng2124 n899 -01 1 -10 1 -.names n899 n792 Ng29648 -11 1 -.names Ng52 n1521 n900 -01 1 -10 1 -.names n900 n792 Ng29794 -11 1 -.names Ng740 n1517 n901 -01 1 -10 1 -.names n901 n792 Ng29798 -11 1 -.names Ng1426 n1513 n902 -01 1 -10 1 -.names n902 n792 Ng29802 -11 1 -.names Ng2120 n1509 n903 -01 1 -10 1 -.names n903 n792 Ng29806 -11 1 -.names n1038 n1443 n907 -1- 1 --1 1 -.names n130 n1575 n908 -1- 1 --1 1 -.names n542 n907 n908 n1038 n904 -011- 1 --110 1 -.names n1042 n1410 n912 -1- 1 --1 1 -.names n137 n1565 n913 -1- 1 --1 1 -.names n551 n912 n913 n1042 n909 -011- 1 --110 1 -.names n1046 n1377 n917 -1- 1 --1 1 -.names n144 n1555 n918 -1- 1 --1 1 -.names n560 n917 n918 n1046 n914 -011- 1 --110 1 -.names n1050 n1344 n922 -1- 1 --1 1 -.names n153 n1545 n923 -1- 1 --1 1 -.names n567 n922 n923 n1050 n919 -011- 1 --110 1 -.names n208 n833 n925 -11 1 -00 1 -.names n625 n1448 n927 -00 1 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1 -.names n295 n842 n955 -11 1 -00 1 -.names n642 n1349 n957 -00 1 -.names n955 n957 n1273 n1351 n954 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n321 n2050 n960 -01 1 -10 1 -.names Ng1486 n1382 n961 -10 1 -.names n960 n961 n1270 n1384 n959 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n328 n2018 n963 -01 1 -10 1 -.names Ng2170 n1349 n964 -10 1 -.names n963 n964 n1273 n1351 n962 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n338 n832 n966 -11 1 -00 1 -.names n613 n1448 n967 -00 1 -.names n966 n967 n1264 n1450 n965 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n371 n2017 n969 -01 1 -10 1 -.names Ng2180 n1349 n970 -10 1 -.names n969 n970 n1273 n1351 n968 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n376 n2119 n972 -01 1 -10 1 -.names Ng105 n1448 n973 -10 1 -.names n972 n973 n1264 n1450 n971 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n388 n835 n975 -11 1 -00 1 -.names n627 n1415 n976 -00 1 -.names n975 n976 n1267 n1417 n974 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n426 n2086 n978 -01 1 -10 1 -.names Ng793 n1415 n979 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--00 1 -.names n226 n548 n1008 -0- 1 --1 1 -.names n226 n993 n1008 n1263 n1007 -1-10 1 --110 1 -.names n346 n548 n1010 -0- 1 --1 1 -.names n346 n993 n1010 n1263 n1009 -1-10 1 --110 1 -.names n462 n649 n1012 -0- 1 --1 1 -.names n462 n1012 n1263 n3738 n1011 -110- 1 --100 1 -.names Pg563 n1530 Ng559 n2727 n1015 -1--- 1 --1-- 1 ---1- 1 ----0 1 -.names n1015 Ng8284 n1262 n1579 n1013 -1--0 1 --100 1 -.names n497 n654 n1019 -0- 1 --1 1 -.names n497 n1019 n1260 n3739 n1017 -110- 1 --100 1 -.names n469 n557 n1023 -0- 1 --1 1 -.names n557 n1487 n1022 -00 1 -.names n469 n1023 n1022 n1260 n1021 -11-0 1 --110 1 -.names n1487 n654 n1025 -11 1 -.names n1025 n1260 n2939 n1024 -10- 1 --00 1 -.names n1487 n557 n1028 -11 1 -.names n1028 n1260 n2940 n1027 -10- 1 --00 1 -.names n431 n654 n1031 -0- 1 --1 1 -.names n431 n1031 n1260 n3739 n1030 -110- 1 --100 1 -.names n1025 n1260 n2938 n1032 -10- 1 --00 1 -.names n254 n557 n1035 -0- 1 --1 1 -.names n254 n1022 n1035 n1260 n1034 -1-10 1 --110 1 -.names n396 n557 n1037 -0- 1 --1 1 -.names n396 n1022 n1037 n1260 n1036 -1-10 1 --110 1 -.names n542 n1427 n2428 n1039 -10- 1 -0-1 1 --01 1 -.names n534 n538 n1039 n3988 n1038 -01-0 1 -0-10 1 -.names n551 n1394 n2393 n1043 -10- 1 -0-1 1 --01 1 -.names n540 n544 n1043 n3983 n1042 -01-0 1 -0-10 1 -.names n560 n1361 n2358 n1047 -10- 1 -0-1 1 --01 1 -.names n546 n553 n1047 n3978 n1046 -01-0 1 -0-10 1 -.names n567 n1328 n2323 n1051 -10- 1 -0-1 1 --01 1 -.names n555 n562 n1051 n3973 n1050 -01-0 1 -0-10 1 -.names Pg1249 Ng1245 n2728 n1056 -1-- 1 --1- 1 ---0 1 -.names n1056 Ng8293 n1259 n1494 n1054 -1--0 1 --100 1 -.names n542 n1422 n1431 n2428 n1059 -0-0- 1 --10- 1 ---00 1 -.names n534 n538 n1059 n3958 n1058 -01-0 1 -0-10 1 -.names n551 n1389 n1398 n2393 n1062 -0-0- 1 --10- 1 ---00 1 -.names n540 n544 n1062 n3942 n1061 -01-0 1 -0-10 1 -.names n560 n1356 n1365 n2358 n1065 -0-0- 1 --10- 1 ---00 1 -.names n546 n553 n1065 n3926 n1064 -01-0 1 -0-10 1 -.names n567 n1323 n1332 n2323 n1068 -0-0- 1 --10- 1 ---00 1 -.names n555 n562 n1068 n3910 n1067 -01-0 1 -0-10 1 -.names n446 n564 n3740 n1072 -11- 1 -0-1 1 --11 1 -.names n1072 n1257 n1070 -10 1 -.names n519 n659 n3741 n1074 -11- 1 -0-0 1 --10 1 -.names n1074 n1257 n1073 -10 1 -.names n504 n564 n3740 n1076 -11- 1 -0-1 1 --11 1 -.names n1076 n1257 n1075 -10 1 -.names n659 n1300 n1078 -10 1 -.names n1078 n1257 n2741 n1077 -10- 1 --00 1 -.names n564 n1300 n1081 -10 1 -.names n1081 n1257 n2742 n1080 -10- 1 --00 1 -.names n476 n659 n3741 n1084 -11- 1 -0-0 1 --10 1 -.names n1084 n1257 n1083 -10 1 -.names n1078 n1257 n2740 n1085 -10- 1 --00 1 -.names n289 n564 n3740 n1088 -11- 1 -0-1 1 --11 1 -.names n1088 n1257 n1087 -10 1 -.names Pg1943 Ng1939 n2729 n1091 -1-- 1 --1- 1 ---0 1 -.names n1091 Ng8302 n1256 n1311 n1089 -1--0 1 --100 1 -.names n1115 Ng8311 n1094 -1- 1 --0 1 -.names n1094 n3895 n1093 -1- 1 --0 1 -.names n491 n569 n3742 n1098 -11- 1 -0-1 1 --11 1 -.names n1094 n1098 n1096 -01 1 -.names n532 n662 n3743 n1100 -11- 1 -0-0 1 --10 1 -.names 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1 --11- 1 -1--1 1 --1-1 1 -.names n1094 n1107 n2726 n1191 -01- 1 -0-0 1 -.names n1094 n1104 n2731 n1193 -01- 1 -0-0 1 -.names n1096 n1109 n1196 -11 1 -00 1 -.names n1099 n1101 n1197 -11 1 -00 1 -.names n1096 n1109 n1198 -01 1 -10 1 -.names n1099 n1101 n1199 -01 1 -10 1 -.names n1196 n1197 n1198 n1199 n1195 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n1111 n1093 n1201 -01 1 -10 1 -.names n1103 n1106 n1202 -11 1 -00 1 -.names n1093 n1111 n1203 -11 1 -00 1 -.names n1103 n1106 n1204 -01 1 -10 1 -.names n1201 n1202 n1203 n1204 n1200 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n587 n1206 n2429 n1207 -0-- 1 --0- 1 ---1 1 -.names n613 n625 n1820 n1206 -001 1 -.names n1207 n1206 n587 n1205 -11- 1 -1-1 1 -.names n601 n1209 n2394 n1210 -0-- 1 --0- 1 ---1 1 -.names n627 n634 n1810 n1209 -001 1 -.names n1210 n1209 n601 n1208 -11- 1 -1-1 1 -.names n615 n1212 n2359 n1213 -0-- 1 --0- 1 ---1 1 -.names n636 n638 n1800 n1212 -001 1 -.names n1213 n1212 n615 n1211 -11- 1 -1-1 1 -.names n629 n1215 n2324 n1216 -0-- 1 --0- 1 ---1 1 -.names n640 n642 n1789 n1215 -001 1 -.names n1216 n1215 n629 n1214 -11- 1 -1-1 1 -.names n629 Ng19048 -0 1 -.names n615 Ng19036 -0 1 -.names n601 Ng19024 -0 1 -.names n587 Ng19012 -0 1 -.names Ng2584 n1284 n1283 n1217 -01- 1 --11 1 -.names n1217 Ng30989 -0 1 -.names n677 n1191 n1287 n3748 n1218 -01-- 1 -0-1- 1 --1-0 1 ---10 1 -.names n1218 Ng30987 -0 1 -.names n677 n1193 n1287 n3749 n1219 -01-- 1 -0-1- 1 --1-0 1 ---10 1 -.names n1219 Ng30986 -0 1 -.names n677 n1290 n3750 n1220 -01- 1 --10 1 -.names n1220 Ng30985 -0 1 -.names n677 n1290 n3751 n1221 -01- 1 --10 1 -.names n1221 Ng30984 -0 1 -.names n677 n1253 n3752 n1222 -00- 1 --00 1 -.names n1222 Ng30983 -0 1 -.names n677 n1113 n3754 n1223 -00- 1 --00 1 -.names n1223 Ng30982 -0 1 -.names n677 n1113 n3755 n1224 -00- 1 --00 1 -.names n1224 Ng30981 -0 1 -.names n677 n1253 n3756 n1225 -00- 1 --00 1 -.names n1225 Ng30980 -0 1 -.names Ng1890 n1308 n1307 n1226 -01- 1 --11 1 -.names n1226 Ng30940 -0 1 -.names n673 n1177 n1311 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-.names Ng1491 n1382 n1469 -10 1 -.names Ng1471 n1382 n1470 -10 1 -.names n540 n544 n551 n1473 -0-- 1 --1- 1 ---0 1 -.names n314 n1404 n1473 n1471 -01- 1 --11 1 -.names n1471 n1406 n1474 -11 1 -.names Ng813 n1415 n1475 -10 1 -.names Ng809 n1415 n1476 -10 1 -.names Ng801 n1415 n1477 -10 1 -.names Ng785 n1415 n1478 -10 1 -.names n534 n538 n542 n1481 -0-- 1 --1- 1 ---0 1 -.names n272 n1437 n1481 n1479 -01- 1 --11 1 -.names n1479 n1439 n1482 -11 1 -.names Ng125 n1448 n1483 -10 1 -.names Ng121 n1448 n1484 -10 1 -.names Ng113 n1448 n1485 -10 1 -.names Ng97 n1448 n1486 -10 1 -.names [1603] n497 Ng1425 n3824 n1488 --1-0 1 -110- 1 -.names n254 n396 n431 n469 n1488 n3826 n1487 -111110 1 -.names Ng1243 n4032 n4034 n1491 -0-1 1 --11 1 -.names n1167 n1172 n1490 -11 1 -00 1 -.names n669 n671 n1494 -1- 1 --0 1 -.names n1056 n1494 n1497 -0- 1 --1 1 -.names [1603] Ng1315 Ng1422 Ng1420 n1500 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n555 n1457 n1546 n2320 n1507 -11-- 1 --10- 1 --1-0 1 -.names Ng2133 Ng2129 n1598 n1510 -111 1 -.names n1510 Ng2124 n1509 -11 1 -.names n546 n1465 n1556 n2355 n1511 -11-- 1 --10- 1 --1-0 1 -.names Ng1439 Ng1435 n1605 n1514 -111 1 -.names n1514 Ng1430 n1513 -11 1 -.names n540 n1473 n1566 n2390 n1515 -11-- 1 --10- 1 --1-0 1 -.names Ng753 Ng749 n1612 n1518 -111 1 -.names n1518 Ng744 n1517 -11 1 -.names n534 n1481 n1576 n2425 n1519 -11-- 1 --10- 1 --1-0 1 -.names Ng65 Ng61 n1619 n1522 -111 1 -.names n1522 Ng56 n1521 -11 1 -.names n2453 n1525 n1526 -1- 1 --1 1 -.names Ng3135 n2460 n1524 -0- 1 --1 1 -.names Ng3147 n1768 n1525 -0- 1 --1 1 -.names n1526 n1524 n1525 n1523 -11- 1 -1-1 1 -.names Ng3120 Ng3135 n2497 n2954 n1529 -1-1- 1 --01- 1 ---10 1 -.names Ng3147 n1768 n1524 n1527 -1-- 1 --1- 1 ---1 1 -.names [1605] Ng8284 n1530 -10 1 -.names [1603] n462 Ng739 n3836 n1533 --1-0 1 -110- 1 -.names n226 n346 n381 n424 n1533 n3838 n1532 -111110 1 -.names Ng557 n4055 n4057 n1536 -0-1 1 --11 1 -.names n1153 n1158 n1535 -11 1 -00 1 -.names n629 n1215 Ng2257 n2324 n1541 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names n629 n657 n1215 n1538 -11- 1 -1-0 1 -.names n629 n657 n1215 n1539 -01- 1 -0-1 1 -.names n620 Ng2257 n1540 -1- 1 --0 1 -.names n1541 n1538 n1539 n1540 n1537 -11-- 1 -1-1- 1 -1--1 1 -.names n1994 n1995 n1329 n2295 n2296 n2297 n1545 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names n555 n562 n567 n1546 -1-- 1 --0- 1 ---1 1 -.names n1343 n1344 n1545 n1546 n1542 -0-1- 1 --01- 1 -0--1 1 --0-1 1 -.names n615 n1212 Ng2257 n2359 n1551 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names n615 n652 n1212 n1548 -11- 1 -1-0 1 -.names n615 n652 n1212 n1549 -01- 1 -0-1 1 -.names n606 Ng2257 n1550 -1- 1 --0 1 -.names n1551 n1548 n1549 n1550 n1547 -11-- 1 -1-1- 1 -1--1 1 -.names n2027 n2028 n1362 n2330 n2331 n2332 n1555 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names n546 n553 n560 n1556 -1-- 1 --0- 1 ---1 1 -.names n1376 n1377 n1555 n1556 n1552 -0-1- 1 --01- 1 -0--1 1 --0-1 1 -.names n601 n1209 Ng2257 n2394 n1561 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names n601 n647 n1209 n1558 -11- 1 -1-0 1 -.names n601 n647 n1209 n1559 -01- 1 -0-1 1 -.names n592 Ng2257 n1560 -1- 1 --0 1 -.names n1561 n1558 n1559 n1560 n1557 -11-- 1 -1-1- 1 -1--1 1 -.names n2060 n2061 n1395 n2365 n2366 n2367 n1565 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names n540 n544 n551 n1566 -1-- 1 --0- 1 ---1 1 -.names n1409 n1410 n1565 n1566 n1562 -0-1- 1 --01- 1 -0--1 1 --0-1 1 -.names n587 n1206 Ng2257 n2429 n1571 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names n587 n645 n1206 n1568 -11- 1 -1-0 1 -.names n587 n645 n1206 n1569 -01- 1 -0-1 1 -.names n578 Ng2257 n1570 -1- 1 --0 1 -.names n1571 n1568 n1569 n1570 n1567 -11-- 1 -1-1- 1 -1--1 1 -.names n2093 n2094 n1428 n2400 n2401 n2402 n1575 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names n534 n538 n542 n1576 -1-- 1 --0- 1 ---1 1 -.names n1442 n1443 n1575 n1576 n1572 -0-1- 1 --01- 1 -0--1 1 --0-1 1 -.names n665 n667 n1579 -1- 1 --0 1 -.names n1015 n1579 n1582 -0- 1 --1 1 -.names [1603] Ng1315 Ng736 Ng734 n1585 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n629 n657 n1215 n1595 -1-- 1 --0- 1 ---1 1 -.names n657 n1216 n1540 n1595 n1593 -0-01 1 --101 1 -.names Ng2142 Ng2138 n1796 n1598 -111 1 -.names n1598 Ng2133 n1597 -11 1 -.names n615 n652 n1212 n1602 -1-- 1 --0- 1 ---1 1 -.names n652 n1213 n1550 n1602 n1600 -0-01 1 --101 1 -.names Ng1448 Ng1444 n1806 n1605 -111 1 -.names n1605 Ng1439 n1604 -11 1 -.names n601 n647 n1209 n1609 -1-- 1 --0- 1 ---1 1 -.names n647 n1210 n1560 n1609 n1607 -0-01 1 --101 1 -.names Ng762 Ng758 n1816 n1612 -111 1 -.names n1612 Ng753 n1611 -11 1 -.names n587 n645 n1206 n1616 -1-- 1 --0- 1 ---1 1 -.names n645 n1207 n1570 n1616 n1614 -0-01 1 --101 1 -.names Ng74 Ng70 n1826 n1619 -111 1 -.names n1619 Ng65 n1618 -11 1 -.names [1521] n1523 n1620 -01 1 -.names n1527 Ng3105 n2521 Ng3128 n1621 -10-- 1 -1-1- 1 --0-1 1 ---11 1 -.names Ng3104 Ng3103 n2519 n2520 n1622 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n2515 Ng3101 n2517 Ng3102 n1623 -1-1- 1 --01- 1 -1--0 1 --0-0 1 -.names n2510 Ng3099 n2512 Ng3100 n1624 -1-1- 1 --01- 1 -1--0 1 --0-0 1 -.names n2506 Ng3097 n2508 Ng3098 n1625 -1-1- 1 --01- 1 -1--0 1 --0-0 1 -.names Ng3108 Ng3107 n2502 n2504 n1626 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Ng3106 n2497 n2501 n4878 n1627 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names Ng2753 n2523 n1629 -11 1 -.names Ng2760 n1629 n1628 -11 1 -.names n103 n112 n599 n623 n1630 -10-- 1 --00- 1 -1--0 1 ---00 1 -.names n109 n599 n623 n3850 n1634 --1-0 1 -110- 1 -.names n103 n112 n611 n3848 n1636 --1-0 1 -110- 1 -.names n623 n611 n1640 -11 1 -.names n94 n599 n1636 n1640 n1639 --01- 1 -10-1 1 -.names n112 n632 n1634 n1654 n1641 -0-1- 1 -00-0 1 -.names n94 n109 n623 n1646 -1-- 1 --1- 1 ---0 1 -.names n103 n109 n623 n1646 n1644 -0--1 1 --101 1 -.names n112 n623 n632 n1647 -11- 1 --10 1 -.names n103 n109 n632 n1640 n1648 -1-0- 1 -10-1 1 -.names n94 n599 n632 n1648 n1650 -1--0 1 --1-0 1 ---10 1 -.names n112 n611 n623 n1653 -10- 1 -0-1 1 --01 1 -.names n103 n109 n1654 -1- 1 --1 1 -.names n94 n1647 n1653 n1654 n1652 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n611 n1644 n112 n1657 -1-- 1 --1- 1 ---1 1 -.names n599 n1652 n3000 n1658 -11- 1 -0-0 1 --10 1 -.names n112 n1650 n1657 n1658 n1656 -0-11 1 --111 1 -.names Ng16474 Ng185 Ng2616 n1661 -1-- 1 --0- 1 ---0 1 -.names [1603] [1605] Ng2673 Ng2670 n1662 -00-- 1 --00- 1 -0--0 1 ---00 1 -.names Ng1315 n1661 n1662 Ng2676 n1659 -011- 1 --110 1 -.names Ng2059 n2551 n1664 -11 1 -.names Ng2066 n1664 n1663 -11 1 -.names n91 n106 n585 n609 n1665 -10-- 1 --00- 1 -1--0 1 ---00 1 -.names n100 n585 n609 n3853 n1669 --1-0 1 -110- 1 -.names n91 n106 n597 n3851 n1671 --1-0 1 -110- 1 -.names n609 n597 n1675 -11 1 -.names n82 n585 n1671 n1675 n1674 --01- 1 -10-1 1 -.names n106 n618 n1669 n1689 n1676 -0-1- 1 -00-0 1 -.names n82 n100 n609 n1681 -1-- 1 --1- 1 ---0 1 -.names n91 n100 n609 n1681 n1679 -0--1 1 --101 1 -.names n106 n609 n618 n1682 -11- 1 --10 1 -.names n91 n100 n618 n1675 n1683 -1-0- 1 -10-1 1 -.names n82 n585 n618 n1683 n1685 -1--0 1 --1-0 1 ---10 1 -.names n106 n597 n609 n1688 -10- 1 -0-1 1 --01 1 -.names n91 n100 n1689 -1- 1 --1 1 -.names n82 n1682 n1688 n1689 n1687 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n597 n1679 n106 n1692 -1-- 1 --1- 1 ---1 1 -.names n585 n1687 n3013 n1693 -11- 1 -0-0 1 --10 1 -.names n106 n1685 n1692 n1693 n1691 -0-11 1 --111 1 -.names Ng16472 Ng185 Ng1922 n1696 -1-- 1 --0- 1 ---0 1 -.names [1603] [1605] Ng1979 Ng1976 n1697 -00-- 1 --00- 1 -0--0 1 ---00 1 -.names Ng1315 n1696 n1697 Ng1982 n1694 -011- 1 --110 1 -.names Ng1365 n2575 n1699 -11 1 -.names Ng1372 n1699 n1698 -11 1 -.names n79 n97 n576 n595 n1700 -10-- 1 --00- 1 -1--0 1 ---00 1 -.names n88 n576 n595 n3856 n1704 --1-0 1 -110- 1 -.names n79 n97 n583 n3854 n1706 --1-0 1 -110- 1 -.names n595 n583 n1710 -11 1 -.names n73 n576 n1706 n1710 n1709 --01- 1 -10-1 1 -.names n97 n604 n1704 n1724 n1711 -0-1- 1 -00-0 1 -.names n73 n88 n595 n1716 -1-- 1 --1- 1 ---0 1 -.names n79 n88 n595 n1716 n1714 -0--1 1 --101 1 -.names n97 n595 n604 n1717 -11- 1 --10 1 -.names n79 n88 n604 n1710 n1718 -1-0- 1 -10-1 1 -.names n73 n576 n604 n1718 n1720 -1--0 1 --1-0 1 ---10 1 -.names n97 n583 n595 n1723 -10- 1 -0-1 1 --01 1 -.names n79 n88 n1724 -1- 1 --1 1 -.names n73 n1717 n1723 n1724 n1722 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n583 n1714 n97 n1727 -1-- 1 --1- 1 ---1 1 -.names n576 n1722 n3026 n1728 -11- 1 -0-0 1 --10 1 -.names n97 n1720 n1727 n1728 n1726 -0-11 1 --111 1 -.names Ng16470 Ng185 Ng1228 n1731 -1-- 1 --0- 1 ---0 1 -.names [1603] [1605] Ng1285 Ng1282 n1732 -00-- 1 --00- 1 -0--0 1 ---00 1 -.names Ng1315 n1731 n1732 Ng1288 n1729 -011- 1 --110 1 -.names Ng679 n2599 n1734 -11 1 -.names Ng686 n1734 n1733 -11 1 -.names n70 n85 n572 n581 n1735 -10-- 1 --00- 1 -1--0 1 ---00 1 -.names n76 n572 n581 n3859 n1739 --1-0 1 -110- 1 -.names n70 n85 n574 n3857 n1741 --1-0 1 -110- 1 -.names n581 n574 n1745 -11 1 -.names n66 n572 n1741 n1745 n1744 --01- 1 -10-1 1 -.names n85 n590 n1739 n1759 n1746 -0-1- 1 -00-0 1 -.names n66 n76 n581 n1751 -1-- 1 --1- 1 ---0 1 -.names n70 n76 n581 n1751 n1749 -0--1 1 --101 1 -.names n85 n581 n590 n1752 -11- 1 --10 1 -.names n70 n76 n590 n1745 n1753 -1-0- 1 -10-1 1 -.names n66 n572 n590 n1753 n1755 -1--0 1 --1-0 1 ---10 1 -.names n85 n574 n581 n1758 -10- 1 -0-1 1 --01 1 -.names n70 n76 n1759 -1- 1 --1 1 -.names n66 n1752 n1758 n1759 n1757 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n574 n1749 n85 n1762 -1-- 1 --1- 1 ---1 1 -.names n572 n1757 n3039 n1763 -11- 1 -0-0 1 --10 1 -.names n85 n1755 n1762 n1763 n1761 -0-11 1 --111 1 -.names Ng16468 Ng185 Ng542 n1766 -1-- 1 --0- 1 ---0 1 -.names [1603] [1605] Ng599 Ng596 n1767 -00-- 1 --00- 1 -0--0 1 ---00 1 -.names Ng1315 n1766 n1767 Ng602 n1764 -011- 1 --110 1 -.names Ng3126 Ng3191 Ng3126 Ng3110 n1768 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n1526 n1527 n1769 -11 1 -.names n2506 n2510 Ng3161 Ng3155 n1771 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n2508 n2512 Ng3164 Ng3158 n1772 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n2515 n2517 Ng3167 Ng3170 n1773 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n2520 n2521 Ng3176 Ng3179 n1774 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n2519 Ng3173 n1775 -1- 1 --0 1 -.names n2501 n2502 Ng3185 Ng3182 n1776 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n1769 Ng3135 n2504 Ng3088 n1777 -1-1- 1 --01- 1 -1--0 1 --0-0 1 -.names [1521] n1771 n1772 n1773 n1774 n1775 n1776 n1777 n1770 -01111111 1 -.names n2502 n2504 Ng3095 Ng3096 n1779 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n2501 n2521 Ng3093 Ng3094 n1780 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n2519 n2520 Ng3091 Ng3092 n1781 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n2515 n2517 Ng3086 Ng3087 n1782 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n2510 n2512 Ng3084 Ng3085 n1783 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n2506 n2508 Ng3210 Ng3211 n1784 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n1523 n1527 Ng3120 n3860 n1785 ---01 1 -11-1 1 -.names [1521] n1779 n1780 n1781 n1782 n1783 n1784 n1785 n1778 -01111111 1 -.names Ng2195 Ng2200 Ng2185 Ng2190 Ng2175 Ng2180 Ng2165 Ng2170 n1789 -11111111 1 -.names [1594] n1789 n3861 Ng2255 n1786 --10- 1 -11-0 1 -.names n455 n488 n1786 n1791 -10- 1 -1-0 1 -.names n455 n488 n1786 n1792 -01- 1 -0-1 1 -.names Ng2257 n1791 n1792 n1790 -0-- 1 --1- 1 ---1 1 -.names Ng2151 Ng2147 n1873 n1796 -111 1 -.names n1796 Ng2142 n1795 -11 1 -.names Ng1501 Ng1506 Ng1491 Ng1496 Ng1481 Ng1486 Ng1471 Ng1476 n1800 -11111111 1 -.names [1594] n1800 n3862 Ng1561 n1797 --10- 1 -11-0 1 -.names n405 n443 n1797 n1802 -10- 1 -1-0 1 -.names n405 n443 n1797 n1803 -01- 1 -0-1 1 -.names Ng2257 n1802 n1803 n1801 -0-- 1 --1- 1 ---1 1 -.names Ng1457 Ng1453 n1877 n1806 -111 1 -.names n1806 Ng1448 n1805 -11 1 -.names Ng809 Ng813 Ng801 Ng805 Ng793 Ng797 Ng785 Ng789 n1810 -11111111 1 -.names [1594] n1810 n3863 Ng867 n1807 --10- 1 -11-0 1 -.names n355 n393 n1807 n1812 -10- 1 -1-0 1 -.names n355 n393 n1807 n1813 -01- 1 -0-1 1 -.names Ng2257 n1812 n1813 n1811 -0-- 1 --1- 1 ---1 1 -.names Ng771 Ng767 n1881 n1816 -111 1 -.names n1816 Ng762 n1815 -11 1 -.names Ng121 Ng125 Ng113 Ng117 Ng105 Ng109 Ng97 Ng101 n1820 -11111111 1 -.names [1594] n1820 n3864 Ng179 n1817 --10- 1 -11-0 1 -.names n305 n343 n1817 n1822 -10- 1 -1-0 1 -.names n305 n343 n1817 n1823 -01- 1 -0-1 1 -.names Ng2257 n1822 n1823 n1821 -0-- 1 --1- 1 ---1 1 -.names Ng83 Ng79 n1885 n1826 -111 1 -.names n1826 Ng74 n1825 -11 1 -.names n124 n569 Ng2584 n1830 -0-- 1 --1- 1 ---0 1 -.names Pg3229 n611 n623 n1834 -1-- 1 --1- 1 ---0 1 -.names Pg3229 n632 n1834 n4158 n1831 -0-10 1 --110 1 -.names Pg3229 n486 n509 n1837 -1-- 1 --1- 1 ---0 1 -.names Pg3229 n524 n1837 n4181 n1835 -0-10 1 --110 1 -.names n121 n564 Ng1890 n1840 -0-- 1 --1- 1 ---0 1 -.names Pg3229 n597 n609 n1843 -1-- 1 --1- 1 ---0 1 -.names Pg3229 n618 n1843 n4205 n1841 -0-10 1 --110 1 -.names Pg3229 n441 n474 n1846 -1-- 1 --1- 1 ---0 1 -.names Pg3229 n502 n1846 n4228 n1844 -0-10 1 --110 1 -.names n118 n557 Ng1196 n1849 -0-- 1 --1- 1 ---0 1 -.names Pg3229 n583 n595 n1852 -1-- 1 --1- 1 ---0 1 -.names Pg3229 n604 n1852 n4252 n1850 -0-10 1 --110 1 -.names Pg3229 n391 n429 n1855 -1-- 1 --1- 1 ---0 1 -.names Pg3229 n467 n1855 n4275 n1853 -0-10 1 --110 1 -.names n115 n548 Ng510 n1858 -0-- 1 --1- 1 ---0 1 -.names Pg3229 n574 n581 n1861 -1-- 1 --1- 1 ---0 1 -.names Pg3229 n590 n1861 n4299 n1859 -0-10 1 --110 1 -.names Pg3229 n341 n379 n1864 -1-- 1 --1- 1 ---0 1 -.names Pg3229 n422 n1864 n4322 n1862 -0-10 1 --110 1 -.names Ng3013 n2695 n1867 -0- 1 --1 1 -.names n1867 Ng3010 n1865 -1- 1 --0 1 -.names Ng2903 n2699 n1869 -11 1 -.names Ng2900 n1869 n1868 -11 1 -.names Ng2734 Ng2720 n1914 n1871 -111 1 -.names n1871 Ng2746 n1870 -11 1 -.names n1916 Ng2160 Ng2156 n1873 -011 1 -.names n1873 Ng2151 n1872 -11 1 -.names Ng2040 Ng2026 n1919 n1875 -111 1 -.names n1875 Ng2052 n1874 -11 1 -.names n1916 Ng1466 Ng1462 n1877 -011 1 -.names n1877 Ng1457 n1876 -11 1 -.names Ng1346 Ng1332 n1923 n1879 -111 1 -.names n1879 Ng1358 n1878 -11 1 -.names n1916 Ng780 Ng776 n1881 -011 1 -.names n1881 Ng771 n1880 -11 1 -.names Ng660 Ng646 n1927 n1883 -111 1 -.names n1883 Ng672 n1882 -11 1 -.names n1916 Ng92 Ng88 n1885 -011 1 -.names n1885 Ng83 n1884 -11 1 -.names n721 n733 n2145 n2146 n2147 n2148 n1886 -0----- 1 --0---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names n2152 n2153 n2154 n2149 n2150 n2151 n1887 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names n555 n562 n567 n1889 -0-- 1 --0- 1 ---0 1 -.names n1886 n1887 n1889 n2326 Ng27229 -1-1- 1 --11- 1 -1--0 1 --1-0 1 -.names n721 n730 n2156 n2157 n2158 n2159 n1890 -0----- 1 --0---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names n2163 n2164 n2165 n2160 n2161 n2162 n1891 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names n546 n553 n560 n1893 -0-- 1 --0- 1 ---0 1 -.names n1890 n1891 n1893 n2361 Ng27220 -1-1- 1 --11- 1 -1--0 1 --1-0 1 -.names n721 n726 n2167 n2168 n2169 n2170 n1894 -0----- 1 --0---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names n2174 n2175 n2176 n2171 n2172 n2173 n1895 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 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-1- 1 --0 1 -.names Ng1339 Ng1319 n1944 n1923 -111 1 -.names n1923 Ng1332 n1922 -11 1 -.names n1916 Ng780 n1924 -1- 1 --0 1 -.names Ng653 Ng633 n1946 n1927 -111 1 -.names n1927 Ng646 n1926 -11 1 -.names n1916 Ng92 n1928 -1- 1 --0 1 -.names n2694 Ng3006 n1930 -0- 1 --0 1 -.names Ng13457 Ng2888 Ng2883 n1934 -111 1 -.names n1934 Ng2896 n1933 -11 1 -.names n2524 Ng13475 n1936 -11 1 -.names n1936 Ng3018 n1935 -11 1 -.names Ng13457 Ng2900 Ng2896 Ng2883 Ng2892 Ng2903 Ng2908 Ng2888 n1938 -10001111 1 -.names n1938 Ng2912 n1937 -11 1 -.names Ng1315 Ng2733 Ng2714 n1940 -101 1 -.names n1940 Ng2707 n1939 -11 1 -.names Ng1315 Ng2039 Ng2020 n1942 -101 1 -.names n1942 Ng2013 n1941 -11 1 -.names Ng1315 Ng1345 Ng1326 n1944 -101 1 -.names n1944 Ng1319 n1943 -11 1 -.names Ng1315 Ng659 Ng640 n1946 -101 1 -.names n1946 Ng633 n1945 -11 1 -.names Ng2883 Ng13457 n1947 -11 1 -.names Ng1315 Ng2733 n1948 -0- 1 --1 1 -.names Ng1315 n1949 n1951 -0- 1 --1 1 -.names Ng1315 n2547 n1949 -11 1 -.names Ng1315 Ng2039 n1952 -0- 1 --1 1 -.names Ng1315 Ng1345 n1954 -0- 1 --1 1 -.names Ng1315 Ng659 n1956 -0- 1 --1 1 -.names Ng1315 n1958 n1960 -0- 1 --1 1 -.names n4869 Ng1315 n1958 -11 1 -.names n177 n1323 n1328 n1343 n1966 -101- 1 --010 1 -.names n173 n1356 n1361 n1376 n1968 -101- 1 --010 1 -.names n167 n1389 n1394 n1409 n1970 -101- 1 --010 1 -.names n160 n1422 n1427 n1442 n1972 -101- 1 --010 1 -.names Ng185 Ng3139 n1976 -0- 1 --0 1 -.names n1976 Ng3139 n2455 n4878 n1974 -110- 1 -1-00 1 -.names Pg3234 n1905 n2142 n1978 -01- 1 -0-0 1 -.names n1978 Ng27238 -0 1 -.names n293 Ng2195 n1988 -11 1 -00 1 -.names n448 Ng2170 n1989 -11 1 -00 1 -.names n219 Ng2180 n1990 -11 1 -00 1 -.names n204 Ng2175 n1991 -11 1 -00 1 -.names n326 Ng2200 n1992 -11 1 -00 1 -.names n263 Ng2190 n1993 -11 1 -00 1 -.names n240 Ng2185 n1994 -11 1 -00 1 -.names n410 Ng2165 n1995 -11 1 -00 1 -.names n506 Ng2175 n1996 -11 1 -00 1 -.names n480 Ng2165 n1998 -11 1 -00 1 -.names n265 Ng2195 n2000 -11 1 -00 1 -.names n521 Ng2185 n2002 -11 1 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n244 n1481 n2114 -01 1 -10 1 -.names n2113 n2119 n2116 -1- 1 --1 1 -.names n1451 n2110 n2117 -1- 1 --1 1 -.names n2111 n2117 n2119 -1- 1 --1 1 -.names n414 n1339 n2121 -01 1 -10 1 -.names Ng2190 n1349 n1351 n2121 n2120 -0-0- 1 --10- 1 -0--1 1 --1-1 1 -.names n364 n1372 n2123 -01 1 -10 1 -.names Ng1496 n1382 n1384 n2123 n2122 -0-0- 1 --10- 1 -0--1 1 --1-1 1 -.names n314 n1405 n2125 -01 1 -10 1 -.names Ng805 n1415 n1417 n2125 n2124 -0-0- 1 --10- 1 -0--1 1 --1-1 1 -.names n272 n1438 n2127 -01 1 -10 1 -.names Ng117 n1448 n1450 n2127 n2126 -0-0- 1 --10- 1 -0--1 1 --1-1 1 -.names Pg3229 n453 n2138 -11 1 -00 1 -.names Pg3229 n403 n2139 -11 1 -00 1 -.names Pg3229 n353 n2140 -11 1 -00 1 -.names Pg3229 n303 n2141 -11 1 -00 1 -.names Ng13475 Ng2993 n2143 -11 1 -.names n2143 Ng2998 n2142 -01 1 -10 1 -.names n483 Ng2120 n2145 -11 1 -00 1 -.names n450 Ng2129 n2146 -11 1 -00 1 -.names n295 Ng2124 n2147 -11 1 -00 1 -.names n265 Ng2133 n2148 -11 1 -00 1 -.names n506 Ng2151 n2149 -11 1 -00 1 -.names n521 Ng2142 n2150 -11 1 -00 1 -.names n414 Ng2138 n2151 -11 1 -00 1 -.names n480 Ng2160 n2152 -11 1 -00 1 -.names n371 Ng2147 n2153 -11 1 -00 1 -.names n328 Ng2156 n2154 -11 1 -00 1 -.names n438 Ng1426 n2156 -11 1 -00 1 -.names n400 Ng1435 n2157 -11 1 -00 1 -.names n260 Ng1430 n2158 -11 1 -00 1 -.names n237 Ng1439 n2159 -11 1 -00 1 -.names n471 Ng1457 n2160 -11 1 -00 1 -.names n499 Ng1448 n2161 -11 1 -00 1 -.names n364 Ng1444 n2162 -11 1 -00 1 -.names n435 Ng1466 n2163 -11 1 -00 1 -.names n321 Ng1453 n2164 -11 1 -00 1 -.names n286 Ng1462 n2165 -11 1 -00 1 -.names n388 Ng740 n2167 -11 1 -00 1 -.names n350 Ng749 n2168 -11 1 -00 1 -.names n232 Ng744 n2169 -11 1 -00 1 -.names n214 Ng753 n2170 -11 1 -00 1 -.names n426 Ng771 n2171 -11 1 -00 1 -.names n464 Ng762 n2172 -11 1 -00 1 -.names n314 Ng758 n2173 -11 1 -00 1 -.names n385 Ng780 n2174 -11 1 -00 1 -.names n279 Ng767 n2175 -11 1 -00 1 -.names n251 Ng776 n2176 -11 1 -00 1 -.names n338 Ng52 n2178 -11 1 -00 1 -.names n300 Ng61 n2179 -11 1 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n2219 -11 1 -00 1 -.names n289 Ng2020 n2220 -11 1 -00 1 -.names n515 Ng1372 n2221 -11 1 -00 1 -.names n469 Ng1352 n2223 -11 1 -00 1 -.names n497 Ng1365 n2225 -11 1 -00 1 -.names n256 Ng1378 n2227 -11 1 -00 1 -.names n282 Ng1319 n2229 -11 1 -00 1 -.names n396 Ng1346 n2231 -11 1 -00 1 -.names n317 Ng1339 n2233 -11 1 -00 1 -.names n358 Ng1332 n2235 -11 1 -00 1 -.names n431 Ng1358 n2237 -11 1 -00 1 -.names n254 Ng1326 n2239 -11 1 -00 1 -.names n493 Ng686 n2241 -11 1 -00 1 -.names n424 Ng666 n2243 -11 1 -00 1 -.names n462 Ng679 n2245 -11 1 -00 1 -.names n228 Ng692 n2247 -11 1 -00 1 -.names n247 Ng633 n2249 -11 1 -00 1 -.names n346 Ng660 n2251 -11 1 -00 1 -.names n275 Ng653 n2253 -11 1 -00 1 -.names n308 Ng646 n2255 -11 1 -00 1 -.names n381 Ng672 n2257 -11 1 -00 1 -.names n226 Ng640 n2259 -11 1 -00 1 -.names n2730 Ng30325 -0 1 -.names n679 n1115 n2278 -0- 1 --1 1 -.names n2729 Ng29445 -0 1 -.names n675 n1091 n2291 -0- 1 --1 1 -.names n369 n642 n2295 -01 1 -10 1 -.names n412 n640 n2296 -01 1 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[1605] Ng3106 n2730 n2737 -00- 1 -1-1 1 --01 1 -.names n2737 Ng30941 -0 1 -.names n528 n564 n3740 n2738 -10- 1 -0-0 1 --00 1 -.names n291 n659 n3741 n2739 -10- 1 -0-1 1 --01 1 -.names n324 n659 n3741 n2740 -10- 1 -0-1 1 --01 1 -.names n408 n659 n3741 n2741 -10- 1 -0-1 1 --01 1 -.names n367 n564 n3740 n2742 -10- 1 -0-0 1 --00 1 -.names Ng853 Ng2392 n3916 n2743 -00- 1 -1-1 1 --01 1 -.names n2743 Ng30907 -0 1 -.names [1594] Ng2391 n3916 n2744 -00- 1 -1-1 1 --01 1 -.names n2744 Ng30906 -0 1 -.names [1612] Ng2390 n3916 n2745 -00- 1 -1-1 1 --01 1 -.names n2745 Ng30905 -0 1 -.names n295 n328 n371 n483 n506 n2325 n2746 -000001 1 -.names n1457 n2326 n2746 n2747 -11- 1 -0-1 1 --11 1 -.names Ng853 n986 Ng2348 n2748 -10- 1 -0-0 1 --00 1 -.names n2748 Ng30904 -0 1 -.names [1594] n986 Ng2345 n2749 -10- 1 -0-0 1 --00 1 -.names n2749 Ng30903 -0 1 -.names [1612] n986 Ng2342 n2750 -10- 1 -0-0 1 --00 1 -.names n2750 Ng30902 -0 1 -.names Ng853 n968 Ng2321 n2751 -10- 1 -0-0 1 --00 1 -.names n2751 Ng30901 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n3932 n2764 -00- 1 -1-1 1 --01 1 -.names n2764 Ng30888 -0 1 -.names [1612] Ng1696 n3932 n2765 -00- 1 -1-1 1 --01 1 -.names n2765 Ng30887 -0 1 -.names n260 n286 n321 n438 n471 n2360 n2766 -000001 1 -.names n1465 n2361 n2766 n2767 -11- 1 -0-1 1 --11 1 -.names Ng853 n980 Ng1654 n2768 -10- 1 -0-0 1 --00 1 -.names n2768 Ng30886 -0 1 -.names [1594] n980 Ng1651 n2769 -10- 1 -0-0 1 --00 1 -.names n2769 Ng30885 -0 1 -.names [1612] n980 Ng1648 n2770 -10- 1 -0-0 1 --00 1 -.names n2770 Ng30884 -0 1 -.names Ng853 n959 Ng1627 n2771 -10- 1 -0-0 1 --00 1 -.names n2771 Ng30883 -0 1 -.names [1594] n959 Ng1624 n2772 -10- 1 -0-0 1 --00 1 -.names n2772 Ng30882 -0 1 -.names [1612] n959 Ng1621 n2773 -10- 1 -0-0 1 --00 1 -.names n2773 Ng30881 -0 1 -.names Ng853 n951 Ng1618 n2774 -10- 1 -0-0 1 --00 1 -.names n2774 Ng30880 -0 1 -.names [1594] n951 Ng1615 n2775 -10- 1 -0-0 1 --00 1 -.names n2775 Ng30879 -0 1 -.names [1612] n951 Ng1612 n2776 -10- 1 -0-0 1 --00 1 -.names n2776 Ng30878 -0 1 -.names Ng853 n943 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n3845 -1-1- 1 --01- 1 -1--1 1 --0-1 1 -.names n667 n992 n2467 Ng530 n3846 -1-1- 1 --01- 1 -1--1 1 --0-1 1 -.names n667 n1011 n2467 Ng529 n3847 -1-1- 1 --01- 1 -1--1 1 --0-1 1 -.names n94 n109 n623 n3849 -1-- 1 --1- 1 ---1 1 -.names n3849 n2534 n1654 n3848 -11- 1 -1-1 1 -.names n103 n611 n1646 n2534 n3850 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n82 n100 n609 n3852 -1-- 1 --1- 1 ---1 1 -.names n3852 n2560 n1689 n3851 -11- 1 -1-1 1 -.names n91 n597 n1681 n2560 n3853 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n73 n88 n595 n3855 -1-- 1 --1- 1 ---1 1 -.names n3855 n2584 n1724 n3854 -11- 1 -1-1 1 -.names n79 n583 n1716 n2584 n3856 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n66 n76 n581 n3858 -1-- 1 --1- 1 ---1 1 -.names n3858 n2608 n1759 n3857 -11- 1 -1-1 1 -.names n70 n574 n1751 n2608 n3859 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n2497 n4456 n3860 -1- 1 --0 1 -.names [1612] Ng853 Ng2253 Ng2254 n3861 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1612] Ng853 Ng1559 Ng1560 n3862 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1612] Ng853 Ng865 Ng866 n3863 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names [1612] Ng853 Ng177 Ng178 n3864 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n2189 n2191 n2192 n3869 -1-- 1 --1- 1 ---1 1 -.names n2198 n2199 n2201 n2203 n2204 n2194 n2196 n3869 n3870 -1------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names Ng1315 Ng2802 n3871 -0- 1 --1 1 -.names n2205 n2207 n2208 n3872 -1-- 1 --1- 1 ---1 1 -.names n2214 n2215 n2217 n2219 n2220 n2210 n2212 n3872 n3873 -1------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names Ng1315 Ng2108 n3874 -0- 1 --1 1 -.names n2221 n2223 n2225 n3875 -1-- 1 --1- 1 ---1 1 -.names n2231 n2233 n2235 n2237 n2239 n2227 n2229 n3875 n3876 -1------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names Ng1315 Ng1414 n3877 -0- 1 --1 1 -.names n2241 n2243 n2245 n3878 -1-- 1 --1- 1 ---1 1 -.names n2251 n2253 n2255 n2257 n2259 n2247 n2249 n3878 n3879 -1------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names Ng1315 Ng728 n3880 -0- 1 --1 1 -.names Ng3139 n2453 n4878 n3881 -11- 1 --10 1 -.names [1605] Ng8284 Ng548 n3884 -1-- 1 --1- 1 ---0 1 -.names [1605] n2727 Ng1234 n3886 -11- 1 -0-0 1 --10 1 -.names [1605] n2728 Ng1928 n3889 -11- 1 -0-0 1 --10 1 -.names [1605] n2729 Ng2622 n3892 -11- 1 -0-0 1 --10 1 -.names n331 n569 n3742 n3895 -11- 1 -0-1 1 --11 1 -.names Pg3229 Ng2612 Ng2615 n3897 -11- 1 -0-1 1 --11 1 -.names n1191 n1193 n3898 -11 1 -00 1 -.names Ng2631 n2278 n3897 n3900 -1-- 1 --1- 1 ---0 1 -.names Pg3229 Ng1918 Ng1921 n3904 -11- 1 -0-1 1 --11 1 -.names n1177 n1179 n3905 -11 1 -00 1 -.names Ng1937 n2291 n3904 n3907 -1-- 1 --1- 1 ---0 1 -.names n177 n567 n1545 n2324 n3909 --0-1 1 -000- 1 -.names n562 n567 n1966 n3909 n3910 -1--1 1 -110- 1 -.names n555 n562 n1067 n3912 -10- 1 --01 1 -.names n555 n562 n567 n1067 n3913 -01-0 1 --110 1 -.names n923 n3912 n3913 n3916 -0-- 1 --1- 1 ---1 1 -.names n173 n560 n1555 n2359 n3925 --0-1 1 -000- 1 -.names n553 n560 n1968 n3925 n3926 -1--1 1 -110- 1 -.names n546 n553 n1064 n3928 -10- 1 --01 1 -.names n546 n553 n560 n1064 n3929 -01-0 1 --110 1 -.names n918 n3928 n3929 n3932 -0-- 1 --1- 1 ---1 1 -.names n167 n551 n1565 n2394 n3941 --0-1 1 -000- 1 -.names n544 n551 n1970 n3941 n3942 -1--1 1 -110- 1 -.names n540 n544 n1061 n3944 -10- 1 --01 1 -.names n540 n544 n551 n1061 n3945 -01-0 1 --110 1 -.names n913 n3944 n3945 n3948 -0-- 1 --1- 1 ---1 1 -.names n160 n542 n1575 n2429 n3957 --0-1 1 -000- 1 -.names n538 n542 n1972 n3957 n3958 -1--1 1 -110- 1 -.names n534 n538 n1058 n3960 -10- 1 --01 1 -.names n534 n538 n542 n1058 n3961 -01-0 1 --110 1 -.names n908 n3960 n3961 n3964 -0-- 1 --1- 1 ---1 1 -.names n562 n567 Ng2257 n2320 n3973 -10-- 1 -1-0- 1 -1--1 1 -.names n553 n560 Ng2257 n2355 n3978 -10-- 1 -1-0- 1 -1--1 1 -.names n544 n551 Ng2257 n2390 n3983 -10-- 1 -1-0- 1 -1--1 1 -.names n538 n542 Ng2257 n2425 n3988 -10-- 1 -1-0- 1 -1--1 1 -.names n450 n1458 n3993 -11 1 -00 1 -.names n265 n1455 n3994 -11 1 -00 1 -.names n2327 n2020 n521 n3996 -1-- 1 --1- 1 ---1 1 -.names n521 n2020 n2327 n3996 n3995 -0--1 1 --001 1 -.names n400 n1466 n3997 -11 1 -00 1 -.names n237 n1463 n3998 -11 1 -00 1 -.names n2362 n2053 n499 n4000 -1-- 1 --1- 1 ---1 1 -.names n499 n2053 n2362 n4000 n3999 -0--1 1 --001 1 -.names n350 n1474 n4001 -11 1 -00 1 -.names n214 n1471 n4002 -11 1 -00 1 -.names n2397 n2086 n464 n4004 -1-- 1 --1- 1 ---1 1 -.names n464 n2086 n2397 n4004 n4003 -0--1 1 --001 1 -.names n300 n1482 n4005 -11 1 -00 1 -.names n197 n1479 n4006 -11 1 -00 1 -.names n2432 n2119 n419 n4008 -1-- 1 --1- 1 ---1 1 -.names n419 n2119 n2432 n4008 n4007 -0--1 1 --001 1 -.names [1603] Pg16297 Ng506 n4010 -1-- 1 --1- 1 ---1 1 -.names Ng506 n4010 Ng507 Ng23154 -01- 1 --11 1 -.names Pg16355 [1603] Ng23154 n4011 -10- 1 -1-1 1 --11 1 -.names n4011 Ng1192 Ng1193 Ng27212 -10- 1 -1-1 1 --11 1 -.names Pg16399 [1603] Ng27212 n4013 -10- 1 -1-1 1 --11 1 -.names Pg16437 [1603] Ng29440 n4016 -00- 1 -0-0 1 --10 1 -.names Ng298 Ng299 n4020 -1- 1 --1 1 -.names [1594] n2929 Ng992 n4022 -11- 1 -0-0 1 --10 1 -.names [1594] n2930 Ng1686 n4025 -11- 1 -0-0 1 --10 1 -.names [1594] n2931 Ng2380 n4028 -11- 1 -0-0 1 --10 1 -.names Pg3229 Ng1224 Ng1227 n4031 -11- 1 -0-1 1 --11 1 -.names n1163 n1165 n4032 -11 1 -00 1 -.names Ng1243 n2444 n4031 n4034 -1-- 1 --1- 1 ---0 1 -.names n923 n1507 n4037 -0- 1 --1 1 -.names n918 n1511 n4041 -0- 1 --1 1 -.names n913 n1515 n4045 -0- 1 --1 1 -.names n908 n1519 n4049 -0- 1 --1 1 -.names Pg3229 Ng538 Ng541 n4054 -11- 1 -0-1 1 --11 1 -.names n1149 n1151 n4055 -11 1 -00 1 -.names Ng557 n2467 n4054 n4057 -1-- 1 --1- 1 ---0 1 -.names n629 n1537 n4059 -11 1 -00 1 -.names n1546 Ng2257 n2323 n4060 -01- 1 -1-1 1 --11 1 -.names Ng853 n4060 n4062 -11 1 -.names [1594] n4060 n4066 -11 1 -.names [1612] n4060 n4069 -11 1 -.names n615 n1547 n4071 -11 1 -00 1 -.names n1556 Ng2257 n2358 n4072 -01- 1 -1-1 1 --11 1 -.names Ng853 n4072 n4074 -11 1 -.names [1594] n4072 n4078 -11 1 -.names [1612] n4072 n4081 -11 1 -.names n601 n1557 n4083 -11 1 -00 1 -.names n1566 Ng2257 n2393 n4084 -01- 1 -1-1 1 --11 1 -.names Ng853 n4084 n4086 -11 1 -.names [1594] n4084 n4090 -11 1 -.names [1612] n4084 n4093 -11 1 -.names n587 n1567 n4095 -11 1 -00 1 -.names n1576 Ng2257 n2428 n4096 -01- 1 -1-1 1 --11 1 -.names Ng853 n4096 n4098 -11 1 -.names [1594] n4096 n4102 -11 1 -.names [1612] n4096 n4105 -11 1 -.names n1593 n891 n4108 -1- 1 --1 1 -.names n620 n4108 n4107 -01 1 -10 1 -.names n1600 n887 n4110 -1- 1 --1 1 -.names n606 n4110 n4109 -01 1 -10 1 -.names n1607 n883 n4112 -1- 1 --1 1 -.names n592 n4112 n4111 -01 1 -10 1 -.names n1614 n880 n4114 -1- 1 --1 1 -.names n578 n4114 n4113 -01 1 -10 1 -.names n2547 n569 n4118 -1- 1 --1 1 -.names n2545 n2547 n3003 n4118 n4116 -1--1 1 --0-1 1 ---01 1 -.names n662 n2547 n3007 n4120 -10- 1 -1-0 1 --10 1 -.names n2547 n564 n4123 -1- 1 --1 1 -.names n2547 n2571 n3016 n4123 n4122 -0--1 1 --1-1 1 ---01 1 -.names n659 n2547 n3020 n4125 -10- 1 -1-0 1 --10 1 -.names n2547 n557 n4128 -1- 1 --1 1 -.names n2547 n2595 n3029 n4128 n4127 -0--1 1 --1-1 1 ---01 1 -.names n654 n2547 n3033 n4130 -10- 1 -1-0 1 --10 1 -.names n2547 n548 n4133 -1- 1 --1 1 -.names n2547 n2619 n3042 n4133 n4132 -0--1 1 --1-1 1 ---01 1 -.names n649 n2547 n3046 n4135 -10- 1 -1-0 1 --10 1 -.names n455 n488 n1786 n4136 -0-- 1 --1- 1 ---1 1 -.names n405 n443 n1797 n4137 -0-- 1 --1- 1 ---1 1 -.names n355 n393 n1807 n4138 -0-- 1 --1- 1 ---1 1 -.names n305 n343 n1817 n4139 -0-- 1 --1- 1 ---1 1 -.names Ng1315 n745 n4140 -0- 1 --1 1 -.names n1640 n4150 n4142 -11 1 -.names [1603] n745 n4144 -0- 1 --1 1 -.names [1605] n745 n4147 -0- 1 --1 1 -.names Pg3229 n599 n4150 -11 1 -00 1 -.names n599 n611 n623 n632 n4158 -01-1 1 -0-01 1 -.names Ng853 n731 n4163 -11 1 -.names n509 n2138 n486 n4165 -111 1 -.names [1594] n731 n4167 -11 1 -.names [1612] n731 n4170 -11 1 -.names n453 n486 n509 n524 n4181 -01-1 1 -0-01 1 -.names Ng1315 n740 n4187 -0- 1 --1 1 -.names n1675 n4197 n4189 -11 1 -.names [1603] n740 n4191 -0- 1 --1 1 -.names [1605] n740 n4194 -0- 1 --1 1 -.names Pg3229 n585 n4197 -11 1 -00 1 -.names n585 n597 n609 n618 n4205 -01-1 1 -0-01 1 -.names Ng853 n728 n4210 -11 1 -.names n474 n2139 n441 n4212 -111 1 -.names [1594] n728 n4214 -11 1 -.names [1612] n728 n4217 -11 1 -.names n403 n441 n474 n502 n4228 -01-1 1 -0-01 1 -.names Ng1315 n739 n4234 -0- 1 --1 1 -.names n1710 n4244 n4236 -11 1 -.names [1603] n739 n4238 -0- 1 --1 1 -.names [1605] n739 n4241 -0- 1 --1 1 -.names Pg3229 n576 n4244 -11 1 -00 1 -.names n576 n583 n595 n604 n4252 -01-1 1 -0-01 1 -.names Ng853 n724 n4257 -11 1 -.names n429 n2140 n391 n4259 -111 1 -.names [1594] n724 n4261 -11 1 -.names [1612] n724 n4264 -11 1 -.names n353 n391 n429 n467 n4275 -01-1 1 -0-01 1 -.names Ng1315 n736 n4281 -0- 1 --1 1 -.names n1745 n4291 n4283 -11 1 -.names [1603] n736 n4285 -0- 1 --1 1 -.names [1605] n736 n4288 -0- 1 --1 1 -.names Pg3229 n572 n4291 -11 1 -00 1 -.names n572 n574 n581 n590 n4299 -01-1 1 -0-01 1 -.names Ng853 n719 n4304 -11 1 -.names n379 n2141 n341 n4306 -111 1 -.names [1594] n719 n4308 -11 1 -.names [1612] n719 n4311 -11 1 -.names n303 n341 n379 n422 n4322 -01-1 1 -0-01 1 -.names n488 n4873 n4328 -11 1 -00 1 -.names n455 n4893 n4329 -11 1 -00 1 -.names n443 n4872 n4330 -11 1 -00 1 -.names n405 n4894 n4331 -11 1 -00 1 -.names n393 n4871 n4332 -11 1 -00 1 -.names n355 n4895 n4333 -11 1 -00 1 -.names n343 n4870 n4334 -11 1 -00 1 -.names n305 n4896 n4335 -11 1 -00 1 -.names n124 n569 Ng2584 n4336 -0-- 1 --0- 1 ---0 1 -.names Ng853 Ng2257 n4337 -0- 1 --0 1 -.names n153 n1545 n4339 -10 1 -.names [1594] Ng2257 n4341 -0- 1 --0 1 -.names [1612] Ng2257 n4344 -0- 1 --0 1 -.names n121 n564 Ng1890 n4347 -0-- 1 --0- 1 ---0 1 -.names n144 n1555 n4349 -10 1 -.names n118 n557 Ng1196 n4352 -0-- 1 --0- 1 ---0 1 -.names n137 n1565 n4354 -10 1 -.names n115 n548 Ng510 n4357 -0-- 1 --0- 1 ---0 1 -.names n130 n1575 n4359 -10 1 -.names Ng13475 Ng2993 n4362 -11 1 -00 1 -.names Ng853 n2703 n4370 -0- 1 --1 1 -.names [1594] n2703 n4373 -0- 1 --1 1 -.names [1612] n2703 n4375 -0- 1 --1 1 -.names Ng2185 Ng2190 Ng2195 Ng2200 n4385 -0--- 1 --1-- 1 ---1- 1 ----0 1 -.names Ng1491 Ng1496 Ng1501 Ng1506 n4404 -0--- 1 --1-- 1 ---1- 1 ----0 1 -.names Ng801 Ng805 Ng809 Ng813 n4423 -0--- 1 --1-- 1 ---1- 1 ----0 1 -.names Ng113 Ng117 Ng121 Ng125 n4442 -0--- 1 --1-- 1 ---1- 1 ----0 1 -.names n2547 n1659 n4445 -1- 1 --1 1 -.names n2547 n693 n4446 -1- 1 --1 1 -.names n1916 n792 n4447 -11 1 -.names n2547 n1694 n4449 -1- 1 --1 1 -.names n2547 n689 n4450 -1- 1 --1 1 -.names n2547 n1729 n4451 -1- 1 --1 1 -.names n2547 n685 n4452 -1- 1 --1 1 -.names n2547 n1764 n4453 -1- 1 --1 1 -.names n2547 n681 n4454 -1- 1 --1 1 -.names Ng2985 Ng2984 n4456 -1- 1 --1 1 -.names Ng3147 Ng3120 n3881 n4456 n4455 -0-0- 1 -00-1 1 -.names [1594] Ng2257 n4503 -0- 1 --0 1 -.names [1612] Ng2257 n4506 -0- 1 --0 1 -.names n2724 n4897 n4644 -11 1 -00 1 -.names Ng3002 Ng3013 Ng3024 Ng3006 Ng3010 n4869 -1---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names n2703 Ng20567 -0 1 -.names n127 Ng2257 n2680 n4870 -1-- 1 --0- 1 ---1 1 -.names n135 Ng2257 n2671 n4871 -1-- 1 --0- 1 ---1 1 -.names n142 Ng2257 n2662 n4872 -1-- 1 --0- 1 ---1 1 -.names n151 Ng2257 n2653 n4873 -1-- 1 --0- 1 ---1 1 -.names Ng2991 Ng2992 n4878 -1- 1 --1 1 -.names Ng2257 n2715 n4893 -0- 1 --1 1 -.names Ng2257 n2716 n4894 -0- 1 --1 1 -.names Ng2257 n2717 n4895 -0- 1 --1 1 -.names Ng2257 n2718 n4896 -0- 1 --1 1 -.names Pg3231 Ng3139 n4897 -1- 1 --0 1 -.names Pg3231 Ng3120 n4898 -1- 1 --0 1 -.names n2725 n4897 n4900 -01 1 -10 1 -.names n486 n524 n2138 n4904 -110 1 -.names n441 n502 n2139 n4905 -110 1 -.names n391 n467 n2140 n4906 -110 1 -.names n341 n422 n2141 n4907 -110 1 -.names [1521] Pg25442 -1 1 -.names [1521] Pg25420 -1 1 -.names [1594] Pg8167 -1 1 -.names [1605] Pg8106 -1 1 -.names [1612] Pg8087 -1 1 -.names [1594] Pg8082 -1 1 -.names [1603] Pg8030 -1 1 -.names [1612] Pg8012 -1 1 -.names [1594] Pg8007 -1 1 -.names [1612] Pg7961 -1 1 -.names [1594] Pg7956 -1 1 -.names [1612] Pg7909 -1 1 -.names [1603] Pg7487 -1 1 -.names [1605] Pg7425 -1 1 -.names [1603] Pg7390 -1 1 -.names [1603] Pg7357 -1 1 -.names [1605] Pg7302 -1 1 -.names [1594] Pg7264 -1 1 -.names [1605] Pg7229 -1 1 -.names [1603] Pg7194 -1 1 -.names [1603] Pg7161 -1 1 -.names [1594] Pg7084 -1 1 -.names [1605] Pg7052 -1 1 -.names [1594] Pg7014 -1 1 -.names [1605] Pg6979 -1 1 -.names [1603] Pg6944 -1 1 -.names [1603] Pg6911 -1 1 -.names [1612] Pg6837 -1 1 -.names [1594] Pg6782 -1 1 -.names [1605] Pg6750 -1 1 -.names [1594] Pg6712 -1 1 -.names [1605] Pg6677 -1 1 -.names [1603] Pg6642 -1 1 -.names [1612] Pg6573 -1 1 -.names [1594] Pg6518 -1 1 -.names [1605] Pg6485 -1 1 -.names [1594] Pg6447 -1 1 -.names [1612] Pg6368 -1 1 -.names [1594] Pg6313 -1 1 -.names [1612] Pg6231 -1 1 -.names [1603] Pg5796 -1 1 -.names [1605] Pg5747 -1 1 -.names [1603] Pg5738 -1 1 -.names [1605] Pg5695 -1 1 -.names [1603] Pg5686 -1 1 -.names [1605] Pg5657 -1 1 -.names [1603] Pg5648 -1 1 -.names [1609] Pg5637 -1 1 -.names [1605] Pg5629 -1 1 -.names [1609] Pg5612 -1 1 -.names [1609] Pg5595 -1 1 -.names [1612] Pg5555 -1 1 -.names [1609] Pg5549 -1 1 -.names [1612] Pg5511 -1 1 -.names [1612] Pg5472 -1 1 -.names [1612] Pg5437 -1 1 -.end diff --git a/fpga_flow/benchmarks/Blif/MCNC_big20/s38584.1.blif b/fpga_flow/benchmarks/Blif/MCNC_big20/s38584.1.blif deleted file mode 100644 index a06e70db9..000000000 --- a/fpga_flow/benchmarks/Blif/MCNC_big20/s38584.1.blif +++ /dev/null @@ -1,18005 +0,0 @@ -.model TOP -.inputs Pg6753 Pg6752 Pg6751 Pg6750 Pg6749 Pg6748 Pg6747 Pg6746 Pg6745 Pg6744 \ -Pg135 Pg134 Pg127 Pg126 Pg125 Pg124 Pg120 Pg116 Pg115 Pg114 Pg113 Pg100 Pg99 \ -Pg92 Pg91 Pg90 Pg84 Pg73 Pg72 Pg64 Pg57 Pg56 Pg54 Pg53 Pg44 Pg36 Pg35 Pg5 PCLK -.outputs Pg34972 Pg34956 Pg34927 Pg34925 Pg34923 Pg34921 Pg34919 Pg34917 \ -Pg34915 Pg34913 Pg34839 Pg34788 Pg34597 Pg34437 Pg34436 Pg34435 Pg34425 \ -Pg34383 Pg34240 Pg34239 Pg34238 Pg34237 Pg34236 Pg34235 Pg34234 Pg34233 \ -Pg34232 Pg34221 Pg34201 Pg33959 Pg33950 Pg33949 Pg33948 Pg33947 Pg33946 \ -Pg33945 Pg33935 Pg33894 Pg33874 Pg33659 Pg33636 Pg33533 Pg33435 Pg33079 \ -Pg32975 Pg32454 Pg32429 Pg32185 Pg31863 Pg31862 Pg31861 Pg31860 Pg31793 \ -Pg31665 Pg31656 Pg31521 Pg30332 Pg30331 Pg30330 Pg30329 Pg30327 Pg29221 \ -Pg29220 Pg29219 Pg29218 Pg29217 Pg29216 Pg29215 Pg29214 Pg29213 Pg29212 \ -Pg29211 Pg29210 Pg28753 Pg28042 Pg28041 Pg28030 Pg27831 Pg26877 Pg26876 \ -Pg26875 Pg26801 Pg25590 Pg25589 Pg25588 Pg25587 Pg25586 Pg25585 Pg25584 \ -Pg25583 Pg25582 Pg25259 Pg25219 Pg25167 Pg25114 Pg24185 Pg24184 Pg24183 \ -Pg24182 Pg24181 Pg24180 Pg24179 Pg24178 Pg24177 Pg24176 Pg24175 Pg24174 \ -Pg24173 Pg24172 Pg24171 Pg24170 Pg24169 Pg24168 Pg24167 Pg24166 Pg24165 \ -Pg24164 Pg24163 Pg24162 Pg24161 Pg24151 Pg23759 Pg23683 Pg23652 Pg23612 \ -Pg23190 Pg23002 Pg21727 Pg21698 Pg21292 Pg21270 Pg21245 Pg21176 Pg20901 \ -Pg20899 Pg20763 Pg20654 Pg20652 Pg20557 Pg20049 Pg19357 Pg19334 Pg18881 \ -Pg18101 Pg18100 Pg18099 Pg18098 Pg18097 Pg18096 Pg18095 Pg18094 Pg18092 \ -Pg17871 Pg17845 Pg17819 Pg17813 Pg17787 Pg17778 Pg17764 Pg17760 Pg17743 \ -Pg17739 Pg17722 Pg17715 Pg17711 Pg17688 Pg17685 Pg17678 Pg17674 Pg17649 \ -Pg17646 Pg17639 Pg17607 Pg17604 Pg17580 Pg17577 Pg17519 Pg17423 Pg17404 \ -Pg17400 Pg17320 Pg17316 Pg17291 Pg16955 Pg16924 Pg16874 Pg16775 Pg16748 \ -Pg16744 Pg16722 Pg16718 Pg16693 Pg16686 Pg16659 Pg16656 Pg16627 Pg16624 \ -Pg16603 Pg14828 Pg14779 Pg14749 Pg14738 Pg14705 Pg14694 Pg14673 Pg14662 \ -Pg14635 Pg14597 Pg14518 Pg14451 Pg14421 Pg14217 Pg14201 Pg14189 Pg14167 \ -Pg14147 Pg14125 Pg14096 Pg13966 Pg13926 Pg13906 Pg13895 Pg13881 Pg13865 \ -Pg13272 Pg13259 Pg13099 Pg13085 Pg13068 Pg13049 Pg13039 Pg12923 Pg12919 \ -Pg12833 Pg12832 Pg12470 Pg12422 Pg12368 Pg12350 Pg12300 Pg12238 Pg12184 \ -Pg11770 Pg11678 Pg11447 Pg11418 Pg11388 Pg11349 Pg10527 Pg10500 Pg10306 \ -Pg10122 Pg9817 Pg9743 Pg9741 Pg9682 Pg9680 Pg9617 Pg9615 Pg9555 Pg9553 Pg9497 \ -Pg9251 Pg9048 Pg9019 Pg8920 Pg8919 Pg8918 Pg8917 Pg8916 Pg8915 Pg8870 Pg8839 \ -Pg8789 Pg8788 Pg8787 Pg8786 Pg8785 Pg8784 Pg8783 Pg8719 Pg8475 Pg8416 Pg8403 \ -Pg8398 Pg8358 Pg8353 Pg8344 Pg8342 Pg8291 Pg8283 Pg8279 Pg8277 Pg8235 Pg8215 \ -Pg8178 Pg8132 Pg7946 Pg7916 Pg7540 Pg7260 Pg7257 Pg7245 Pg7243 -.latch Ng33046 Ng5057 re PCLK 2 -.latch Ng34441 Ng2771 re PCLK 2 -.latch Ng33982 Ng1882 re PCLK 2 -.latch Ng34007 Ng2299 re PCLK 2 -.latch Ng24276 Ng4040 re PCLK 2 -.latch Ng30381 Ng2547 re PCLK 2 -.latch Pg9048 Ng559 re PCLK 2 -.latch Ng30405 Ng3243 re PCLK 2 -.latch Ng25604 Ng452 re PCLK 2 -.latch Ng30416 Ng3542 re PCLK 2 -.latch Ng30466 Ng5232 re PCLK 2 -.latch Ng25736 Ng5813 re PCLK 2 -.latch Ng34617 Ng2907 re PCLK 2 -.latch Ng33974 Ng1744 re PCLK 2 -.latch Ng30505 Ng5909 re PCLK 2 -.latch Ng33554 Ng1802 re PCLK 2 -.latch Ng30432 Ng3554 re PCLK 2 -.latch Ng33064 Ng6219 re PCLK 2 -.latch Ng34881 Ng807 re PCLK 2 -.latch Pg17715 Ng6031 re PCLK 2 -.latch Ng24216 Ng847 re PCLK 2 -.latch Ng24232 Ng976 re PCLK 2 -.latch Ng34733 Ng4172 re PCLK 2 -.latch Ng34882 Ng4372 re PCLK 2 -.latch Ng33026 Ng3512 re PCLK 2 -.latch Ng31867 Ng749 re PCLK 2 -.latch Ng25668 Ng3490 re PCLK 2 -.latch Ng24344 Pg12350 re PCLK 2 -.latch Pg8920 Ng4235 re PCLK 2 -.latch Ng33966 Ng1600 re PCLK 2 -.latch Ng33550 Ng1714 re PCLK 2 -.latch Pg16656 Pg14451 re PCLK 2 -.latch Ng30393 Ng3155 re PCLK 2 -.latch Ng29248 Ng2236 re PCLK 2 -.latch Ng4571 Ng4555 re PCLK 2 -.latch Ng24274 Ng3698 re PCLK 2 -.latch Ng33973 Ng1736 re PCLK 2 -.latch Ng30360 Ng1968 re PCLK 2 -.latch Ng34460 Ng4621 re PCLK 2 -.latch Ng30494 Ng5607 re PCLK 2 -.latch Ng30384 Ng2657 re PCLK 2 -.latch Ng24340 Pg12300 re PCLK 2 -.latch Ng29223 Ng490 re PCLK 2 -.latch Ng26881 Ng311 re PCLK 2 -.latch Ng34252 Ng772 re PCLK 2 -.latch Ng30489 Ng5587 re PCLK 2 -.latch Ng29301 Ng6177 re PCLK 2 -.latch Pg17743 Ng6377 re PCLK 2 -.latch Ng33022 Ng3167 re PCLK 2 -.latch Ng30496 Ng5615 re PCLK 2 -.latch Ng33043 Ng4567 re PCLK 2 -.latch Ng29263 Ng3457 re PCLK 2 -.latch Ng30533 Ng6287 re PCLK 2 -.latch Ng24256 Pg7946 re PCLK 2 -.latch Ng34015 Ng2563 re PCLK 2 -.latch Ng34031 Ng4776 re PCLK 2 -.latch Ng34452 Ng4593 re PCLK 2 -.latch Ng34646 Ng6199 re PCLK 2 -.latch Ng34001 Ng2295 re PCLK 2 -.latch Ng25633 Ng1384 re PCLK 2 -.latch Ng24259 Ng1339 re PCLK 2 -.latch Ng33049 Ng5180 re PCLK 2 -.latch Ng34609 Ng2844 re PCLK 2 -.latch Ng31869 Ng1024 re PCLK 2 -.latch Ng30490 Ng5591 re PCLK 2 -.latch Ng30427 Ng3598 re PCLK 2 -.latch Ng21894 Ng4264 re PCLK 2 -.latch Ng33965 Ng767 re PCLK 2 -.latch Ng34645 Ng5853 re PCLK 2 -.latch Pg16874 Pg13865 re PCLK 2 -.latch Ng33571 Ng2089 re PCLK 2 -.latch Ng34267 Ng4933 re PCLK 2 -.latch Ng26971 Ng4521 re PCLK 2 -.latch Ng34644 Ng5507 re PCLK 2 -.latch Pg16627 Pg16656 re PCLK 2 -.latch Ng30534 Ng6291 re PCLK 2 -.latch Ng33535 Ng294 re PCLK 2 -.latch Ng30498 Ng5559 re PCLK 2 -.latch Ng25728 Pg9617 re PCLK 2 -.latch Ng25743 Pg9741 re PCLK 2 -.latch Ng25684 Ng3813 re PCLK 2 -.latch Ng25613 Ng562 re PCLK 2 -.latch Ng34438 Ng608 re PCLK 2 -.latch Ng24244 Ng1205 re PCLK 2 -.latch Ng30439 Ng3909 re PCLK 2 -.latch Ng30541 Ng6259 re PCLK 2 -.latch Ng30519 Ng5905 re PCLK 2 -.latch Ng25621 Ng921 re PCLK 2 -.latch Ng34807 Ng2955 re PCLK 2 -.latch Ng25599 Ng203 re PCLK 2 -.latch Ng24235 Ng1099 re PCLK 2 -.latch Ng34036 Ng4878 re PCLK 2 -.latch Ng30476 Ng5204 re PCLK 2 -.latch Pg17580 Pg17604 re PCLK 2 -.latch Ng30429 Ng3606 re PCLK 2 -.latch Ng32997 Ng1926 re PCLK 2 -.latch Ng33063 Ng6215 re PCLK 2 -.latch Ng30424 Ng3586 re PCLK 2 -.latch Ng32977 Ng291 re PCLK 2 -.latch Ng34026 Ng4674 re PCLK 2 -.latch Ng30420 Ng3570 re PCLK 2 -.latch Pg12368 Pg9048 re PCLK 2 -.latch Pg17739 Pg17607 re PCLK 2 -.latch Ng33560 Ng1862 re PCLK 2 -.latch Ng29226 Ng676 re PCLK 2 -.latch Ng25619 Ng843 re PCLK 2 -.latch Ng34455 Ng4332 re PCLK 2 -.latch Ng30457 Ng4153 re PCLK 2 -.latch Pg14694 Pg17711 re PCLK 2 -.latch Ng33625 Ng6336 re PCLK 2 -.latch Ng34790 Ng622 re PCLK 2 -.latch Ng30414 Ng3506 re PCLK 2 -.latch Ng26966 Ng4558 re PCLK 2 -.latch Pg17649 Pg17685 re PCLK 2 -.latch Ng25656 Ng3111 re PCLK 2 -.latch Ng30390 [4430] re PCLK 2 -.latch Ng28079 Ng26936 re PCLK 2 -.latch Ng34727 Ng939 re PCLK 2 -.latch Ng25594 Ng278 re PCLK 2 -.latch Ng26963 Ng4492 re PCLK 2 -.latch Ng34034 Ng4864 re PCLK 2 -.latch Ng33541 Ng1036 re PCLK 2 -.latch Ng28093 [4427] re PCLK 2 -.latch Ng24236 Ng1178 re PCLK 2 -.latch Ng30404 Ng3239 re PCLK 2 -.latch Ng28051 Ng718 re PCLK 2 -.latch Ng29303 Ng6195 re PCLK 2 -.latch Ng26917 Ng1135 re PCLK 2 -.latch Ng33624 Ng6395 re PCLK 2 -.latch Ng24337 [4415] re PCLK 2 -.latch Ng34911 Ng554 re PCLK 2 -.latch Ng33963 Ng496 re PCLK 2 -.latch Ng34627 Ng3853 re PCLK 2 -.latch Ng29282 Ng5134 re PCLK 2 -.latch Pg17320 Pg17404 re PCLK 2 -.latch Ng25676 Pg8344 re PCLK 2 -.latch Ng33013 Ng2485 re PCLK 2 -.latch Ng32981 Ng925 re PCLK 2 -.latch Ng34993 Ng48 re PCLK 2 -.latch Ng30483 Ng5555 re PCLK 2 -.latch Pg14217 Pg14096 re PCLK 2 -.latch Ng32994 Ng1798 re PCLK 2 -.latch Ng28070 Ng4076 re PCLK 2 -.latch Ng34806 Ng2941 re PCLK 2 -.latch Ng30453 Ng3905 re PCLK 2 -.latch Ng33539 Ng763 re PCLK 2 -.latch Ng30526 Ng6255 re PCLK 2 -.latch Ng26951 Ng4375 re PCLK 2 -.latch Ng34035 Ng4871 re PCLK 2 -.latch Ng34636 Ng4722 re PCLK 2 -.latch Ng32978 Ng590 re PCLK 2 -.latch Pg17722 Pg13099 re PCLK 2 -.latch Ng30348 Ng1632 re PCLK 2 -.latch Ng24336 Pg12238 re PCLK 2 -.latch Pg8215 Ng3100 re PCLK 2 -.latch Ng24250 Ng1495 re PCLK 2 -.latch Ng29236 Ng1437 re PCLK 2 -.latch Ng29298 Ng6154 re PCLK 2 -.latch Pg10527 Ng1579 re PCLK 2 -.latch Ng30499 Ng5567 re PCLK 2 -.latch Ng33976 Ng1752 re PCLK 2 -.latch Ng32996 Ng1917 re PCLK 2 -.latch Ng30335 Ng744 re PCLK 2 -.latch Ng34637 Ng4737 re PCLK 2 -.latch Ng25694 [4661] re PCLK 2 -.latch Ng30528 Ng6267 re PCLK 2 -.latch Pg16775 Pg16659 re PCLK 2 -.latch Ng24251 Ng1442 re PCLK 2 -.latch Ng30521 Ng5965 re PCLK 2 -.latch Ng26960 Ng4477 re PCLK 2 -.latch Ng24239 Pg10500 re PCLK 2 -.latch Ng34259 Ng4643 re PCLK 2 -.latch Ng30474 Ng5264 re PCLK 2 -.latch Pg12422 Pg14779 re PCLK 2 -.latch Ng33016 Ng2610 re PCLK 2 -.latch Ng34643 Ng5160 re PCLK 2 -.latch Ng30510 Ng5933 re PCLK 2 -.latch Ng29239 Ng1454 re PCLK 2 -.latch Ng26897 Ng753 re PCLK 2 -.latch Ng34729 Ng1296 re PCLK 2 -.latch Ng34625 Ng3151 re PCLK 2 -.latch Ng34800 Ng2980 re PCLK 2 -.latch Ng24353 Ng6727 re PCLK 2 -.latch Ng33029 Ng3530 re PCLK 2 -.latch Ng33615 Ng4104 re PCLK 2 -.latch Ng24253 Ng1532 re PCLK 2 -.latch Ng24281 Pg9251 re PCLK 2 -.latch Ng33997 Ng2177 re PCLK 2 -.latch Ng34997 Ng52 re PCLK 2 -.latch Ng34263 Ng4754 re PCLK 2 -.latch Ng24237 Ng1189 re PCLK 2 -.latch Ng33584 Ng2287 re PCLK 2 -.latch Ng24280 Ng4273 re PCLK 2 -.latch Ng26920 Ng1389 re PCLK 2 -.latch Ng33548 Ng1706 re PCLK 2 -.latch Ng29296 Ng5835 re PCLK 2 -.latch Ng30338 Ng1171 re PCLK 2 -.latch Ng21895 Ng4269 re PCLK 2 -.latch Ng33588 Ng2399 re PCLK 2 -.latch Ng34041 Ng4983 re PCLK 2 -.latch Ng30495 Ng5611 re PCLK 2 -.latch Pg16744 Pg16627 re PCLK 2 -.latch Ng29279 Ng4572 re PCLK 2 -.latch Ng25655 Ng3143 re PCLK 2 -.latch Ng34795 Ng2898 re PCLK 2 -.latch Ng24269 Ng3343 re PCLK 2 -.latch Ng30403 Ng3235 re PCLK 2 -.latch Ng33042 Ng4543 re PCLK 2 -.latch Ng30419 Ng3566 re PCLK 2 -.latch Ng34023 Ng4534 re PCLK 2 -.latch Ng28090 Ng4961 re PCLK 2 -.latch Ng34642 Ng4927 re PCLK 2 -.latch Ng30370 Ng2259 re PCLK 2 -.latch Ng34448 Ng2819 re PCLK 2 -.latch Ng26946 Pg7257 re PCLK 2 -.latch Pg9617 Ng5802 re PCLK 2 -.latch Ng34610 Ng2852 re PCLK 2 -.latch Ng24209 Ng417 re PCLK 2 -.latch Ng28047 Ng681 re PCLK 2 -.latch Ng24206 Ng437 re PCLK 2 -.latch Ng26891 Ng351 re PCLK 2 -.latch Ng30504 Ng5901 re PCLK 2 -.latch Ng34798 Ng2886 re PCLK 2 -.latch Ng25669 Ng3494 re PCLK 2 -.latch Ng30480 Ng5511 re PCLK 2 -.latch Ng33027 Ng3518 re PCLK 2 -.latch Ng33972 Ng1604 re PCLK 2 -.latch Ng25697 Ng5092 re PCLK 2 -.latch Ng28099 Ng4831 re PCLK 2 -.latch Ng26947 Ng4382 re PCLK 2 -.latch Ng24350 Ng6386 re PCLK 2 -.latch Ng24210 Ng479 re PCLK 2 -.latch Ng30455 Ng3965 re PCLK 2 -.latch Ng28084 Ng4749 re PCLK 2 -.latch Ng33993 Ng2008 re PCLK 2 -.latch Pg11678 Ng736 re PCLK 2 -.latch Ng30444 Ng3933 re PCLK 2 -.latch Ng33537 Ng222 re PCLK 2 -.latch Ng25650 Ng3050 re PCLK 2 -.latch Ng25625 Ng1052 re PCLK 2 -.latch Pg17711 Pg17580 re PCLK 2 -.latch Ng30366 Ng2122 re PCLK 2 -.latch Ng33593 Ng2465 re PCLK 2 -.latch Ng30502 Ng5889 re PCLK 2 -.latch Ng33036 Ng4495 re PCLK 2 -.latch Ng25595 Pg8719 re PCLK 2 -.latch Ng34462 Ng4653 re PCLK 2 -.latch Ng33024 Ng3179 re PCLK 2 -.latch Ng33552 Ng1728 re PCLK 2 -.latch Ng34014 Ng2433 re PCLK 2 -.latch Ng29273 Ng3835 re PCLK 2 -.latch Ng25748 Ng6187 re PCLK 2 -.latch Ng34638 Ng4917 re PCLK 2 -.latch Ng30341 Ng1070 re PCLK 2 -.latch Ng26899 Ng822 re PCLK 2 -.latch Pg14673 Pg17715 re PCLK 2 -.latch Ng30336 Ng914 re PCLK 2 -.latch Pg17639 Ng5339 re PCLK 2 -.latch Ng26940 Ng4164 re PCLK 2 -.latch Ng25622 Ng969 re PCLK 2 -.latch Ng34447 Ng2807 re PCLK 2 -.latch Ng33613 Ng4054 re PCLK 2 -.latch Ng25749 Ng6191 re PCLK 2 -.latch Ng25704 Ng5077 re PCLK 2 -.latch Ng33053 Ng5523 re PCLK 2 -.latch Pg16722 Ng3680 re PCLK 2 -.latch Ng30555 Ng6637 re PCLK 2 -.latch Ng25601 Ng174 re PCLK 2 -.latch Ng33971 Ng1682 re PCLK 2 -.latch Ng26892 Ng355 re PCLK 2 -.latch Pg17400 Ng1087 re PCLK 2 -.latch Ng26915 Ng1105 re PCLK 2 -.latch Ng33008 Ng2342 re PCLK 2 -.latch Ng30538 Ng6307 re PCLK 2 -.latch Pg8344 Ng3802 re PCLK 2 -.latch Ng25750 Ng6159 re PCLK 2 -.latch Ng30369 Ng2255 re PCLK 2 -.latch Ng34446 Ng2815 re PCLK 2 -.latch Ng29230 Ng911 re PCLK 2 -.latch Ng34789 Ng43 re PCLK 2 -.latch Pg13966 Pg16775 re PCLK 2 -.latch Ng33975 Ng1748 re PCLK 2 -.latch Ng30497 Ng5551 re PCLK 2 -.latch Ng30418 Ng3558 re PCLK 2 -.latch Ng25721 Ng5499 re PCLK 2 -.latch Ng34622 Ng2960 re PCLK 2 -.latch Ng30438 Ng3901 re PCLK 2 -.latch Ng34266 Ng4888 re PCLK 2 -.latch Ng30540 Ng6251 re PCLK 2 -.latch Pg17760 Pg17649 re PCLK 2 -.latch Ng32986 Ng1373 re PCLK 2 -.latch Ng25648 Pg8215 re PCLK 2 -.latch Ng33960 Ng157 re PCLK 2 -.latch Ng34442 Ng2783 re PCLK 2 -.latch Pg8839 Ng4281 re PCLK 2 -.latch Ng30421 Ng3574 re PCLK 2 -.latch Ng33573 Ng2112 re PCLK 2 -.latch Ng34730 Ng1283 re PCLK 2 -.latch Ng24205 Ng433 re PCLK 2 -.latch Pg10122 Ng4297 re PCLK 2 -.latch Pg12350 Pg14738 re PCLK 2 -.latch Pg19357 Pg13272 re PCLK 2 -.latch Ng32979 Ng758 re PCLK 2 -.latch Ng34025 Ng4639 re PCLK 2 -.latch Ng25763 Ng6537 re PCLK 2 -.latch Ng30481 Ng5543 re PCLK 2 -.latch Pg7946 Pg8475 re PCLK 2 -.latch Ng30517 Ng5961 re PCLK 2 -.latch Ng30539 Ng6243 re PCLK 2 -.latch Ng34880 Ng632 re PCLK 2 -.latch Ng24242 Pg12919 re PCLK 2 -.latch Ng30436 Ng3889 re PCLK 2 -.latch Ng29265 Ng3476 re PCLK 2 -.latch Ng32990 Ng1664 re PCLK 2 -.latch Ng24245 Ng1246 re PCLK 2 -.latch Ng30553 Ng6629 re PCLK 2 -.latch Ng26907 Ng246 re PCLK 2 -.latch Ng24278 Ng4049 re PCLK 2 -.latch Ng26955 Pg7260 re PCLK 2 -.latch Ng24282 Ng2932 re PCLK 2 -.latch Ng29276 Ng4575 re PCLK 2 -.latch Ng31894 Ng4098 re PCLK 2 -.latch Ng33037 Ng4498 re PCLK 2 -.latch Ng26894 Ng528 re PCLK 2 -.latch Ng34994 Ng16 re PCLK 2 -.latch Ng25654 Ng3139 re PCLK 2 -.latch Ng33962 [4432] re PCLK 2 -.latch Ng34451 Ng4584 re PCLK 2 -.latch Ng34250 Ng142 re PCLK 2 -.latch Pg14597 Pg17639 re PCLK 2 -.latch Ng29295 Ng5831 re PCLK 2 -.latch Ng26905 Ng239 re PCLK 2 -.latch Ng25629 Ng1216 re PCLK 2 -.latch Ng34792 Ng2848 re PCLK 2 -.latch Ng25703 Ng5022 re PCLK 2 -.latch Pg14518 Pg16955 re PCLK 2 -.latch Ng32983 Ng1030 re PCLK 2 -.latch Pg16924 Pg13881 re PCLK 2 -.latch Ng30402 Ng3231 re PCLK 2 -.latch Ng25757 Pg9817 re PCLK 2 -.latch Pg17423 Ng1430 re PCLK 2 -.latch Pg7245 Ng4452 re PCLK 2 -.latch Ng33999 Ng2241 re PCLK 2 -.latch Ng24262 Ng1564 re PCLK 2 -.latch Ng25729 Pg9680 re PCLK 2 -.latch Pg9682 Ng6148 re PCLK 2 -.latch Ng30558 Ng6649 re PCLK 2 -.latch Ng34848 Ng110 re PCLK 2 -.latch Pg14125 Pg14147 re PCLK 2 -.latch Ng26901 Ng225 re PCLK 2 -.latch Ng26961 Ng4486 re PCLK 2 -.latch Ng33039 Ng4504 re PCLK 2 -.latch Ng33059 Ng5873 re PCLK 2 -.latch Ng31899 Ng5037 re PCLK 2 -.latch Ng33007 Ng2319 re PCLK 2 -.latch Ng25720 Ng5495 re PCLK 2 -.latch Ng21891 Pg11770 re PCLK 2 -.latch Ng30462 Ng5208 re PCLK 2 -.latch Ng30487 Ng5579 re PCLK 2 -.latch Ng33058 Ng5869 re PCLK 2 -.latch Ng24261 Ng1589 re PCLK 2 -.latch Ng25730 Ng5752 re PCLK 2 -.latch Ng30531 Ng6279 re PCLK 2 -.latch Ng30506 Ng5917 re PCLK 2 -.latch Ng34804 Ng2975 re PCLK 2 -.latch Ng25747 Ng6167 re PCLK 2 -.latch Pg11418 Pg13966 re PCLK 2 -.latch Ng33601 Ng2599 re PCLK 2 -.latch Ng26922 Ng1448 re PCLK 2 -.latch Pg14096 Pg14125 re PCLK 2 -.latch Ng29250 Ng2370 re PCLK 2 -.latch Ng30459 Ng5164 re PCLK 2 -.latch Pg8475 Ng1333 re PCLK 2 -.latch Ng33534 Ng153 re PCLK 2 -.latch Ng30543 Ng6549 re PCLK 2 -.latch Ng29275 Ng4087 re PCLK 2 -.latch Ng34030 Ng4801 re PCLK 2 -.latch Ng34980 Ng2984 re PCLK 2 -.latch Ng30451 Ng3961 re PCLK 2 -.latch Ng25627 Ng962 re PCLK 2 -.latch Ng34787 Ng101 re PCLK 2 -.latch Pg8870 Pg8918 re PCLK 2 -.latch Ng30552 Ng6625 re PCLK 2 -.latch Ng34996 Ng51 re PCLK 2 -.latch Ng30337 Ng1018 re PCLK 2 -.latch Ng24254 Pg17320 re PCLK 2 -.latch Ng24277 Ng4045 re PCLK 2 -.latch Ng29237 Ng1467 re PCLK 2 -.latch Ng30378 Ng2461 re PCLK 2 -.latch Ng33019 Ng2756 re PCLK 2 -.latch Ng33623 Ng5990 re PCLK 2 -.latch Ng29235 Ng1256 re PCLK 2 -.latch Ng31902 Ng5029 re PCLK 2 -.latch Ng29306 Ng6519 re PCLK 2 -.latch Ng33978 Ng1816 re PCLK 2 -.latch Ng26970 Ng4369 re PCLK 2 -.latch Ng29278 Ng4578 re PCLK 2 -.latch Ng34253 Ng4459 re PCLK 2 -.latch Ng29272 Ng3831 re PCLK 2 -.latch Ng33595 Ng2514 re PCLK 2 -.latch Ng33610 Ng3288 re PCLK 2 -.latch Ng33589 Ng2403 re PCLK 2 -.latch Ng34605 Ng2145 re PCLK 2 -.latch Ng30350 Ng1700 re PCLK 2 -.latch Ng25611 Ng513 re PCLK 2 -.latch Ng26936 Ng2841 re PCLK 2 -.latch Ng33619 Ng5297 re PCLK 2 -.latch Ng34022 Ng2763 re PCLK 2 -.latch Ng34033 Ng4793 re PCLK 2 -.latch Ng34726 Ng952 re PCLK 2 -.latch Ng31870 Ng1263 re PCLK 2 -.latch Ng33985 Ng1950 re PCLK 2 -.latch Ng29283 Ng5138 re PCLK 2 -.latch Ng34003 Ng2307 re PCLK 2 -.latch Pg9497 Ng5109 re PCLK 2 -.latch Ng25677 Pg8398 re PCLK 2 -.latch Ng34463 Ng4664 re PCLK 2 -.latch Ng33006 Ng2223 re PCLK 2 -.latch Ng29292 Ng5808 re PCLK 2 -.latch Ng30557 Ng6645 re PCLK 2 -.latch Ng33989 Ng2016 re PCLK 2 -.latch Ng33033 Ng3873 re PCLK 2 -.latch Pg11388 Pg13926 re PCLK 2 -.latch Ng34005 Ng2315 re PCLK 2 -.latch Ng26932 Ng2811 re PCLK 2 -.latch Ng30516 Ng5957 re PCLK 2 -.latch Ng33575 Ng2047 re PCLK 2 -.latch Ng33032 Ng3869 re PCLK 2 -.latch Pg14779 Pg17760 re PCLK 2 -.latch Ng30486 Ng5575 re PCLK 2 -.latch Ng34991 Ng46 re PCLK 2 -.latch Ng25678 Ng3752 re PCLK 2 -.latch Ng30440 Ng3917 re PCLK 2 -.latch Pg11447 Pg8783 re PCLK 2 -.latch Pg12923 Ng1585 re PCLK 2 -.latch Ng26949 Ng4388 re PCLK 2 -.latch Ng30530 Ng6275 re PCLK 2 -.latch Ng30542 Ng6311 re PCLK 2 -.latch Pg8915 Pg8916 re PCLK 2 -.latch Ng25624 Ng1041 re PCLK 2 -.latch Ng30383 Ng2595 re PCLK 2 -.latch Ng33597 Ng2537 re PCLK 2 -.latch Ng34598 [4426] re PCLK 2 -.latch Ng26957 Ng4430 re PCLK 2 -.latch Ng26967 Ng4564 re PCLK 2 -.latch Ng28102 Ng4826 re PCLK 2 -.latch Ng30524 Ng6239 re PCLK 2 -.latch Ng26903 Ng232 re PCLK 2 -.latch Ng30475 Ng5268 re PCLK 2 -.latch Ng34647 Ng6545 re PCLK 2 -.latch Ng30377 Ng2417 re PCLK 2 -.latch Ng33553 Ng1772 re PCLK 2 -.latch Ng31903 Ng5052 re PCLK 2 -.latch Ng25715 Pg9615 re PCLK 2 -.latch Ng33984 Ng1890 re PCLK 2 -.latch Ng33602 Ng2629 re PCLK 2 -.latch Ng28045 Ng572 re PCLK 2 -.latch Ng34603 Ng2130 re PCLK 2 -.latch Ng33035 Ng4108 re PCLK 2 -.latch Pg9251 Ng4308 re PCLK 2 -.latch Ng24208 Ng475 re PCLK 2 -.latch Pg8416 Ng990 re PCLK 2 -.latch Ng34990 Ng45 re PCLK 2 -.latch Ng24213 Pg12184 re PCLK 2 -.latch Ng33614 Ng3990 re PCLK 2 -.latch Ng33060 Ng5881 re PCLK 2 -.latch Ng30362 Ng1992 re PCLK 2 -.latch Ng33023 Ng3171 re PCLK 2 -.latch Ng26898 Ng812 re PCLK 2 -.latch Ng25618 Ng832 re PCLK 2 -.latch Ng30518 Ng5897 re PCLK 2 -.latch Ng6974 Ng4571 re PCLK 2 -.latch Pg11349 Pg13895 re PCLK 2 -.latch Ng26959 Ng4455 re PCLK 2 -.latch Ng34801 Ng2902 re PCLK 2 -.latch Ng26884 Ng333 re PCLK 2 -.latch Ng25600 Ng168 re PCLK 2 -.latch Ng26933 Ng2823 re PCLK 2 -.latch Ng28066 Ng3684 re PCLK 2 -.latch Ng33612 Ng3639 re PCLK 2 -.latch Pg17787 Pg14597 re PCLK 2 -.latch Ng24268 Ng3338 re PCLK 2 -.latch Ng25716 Ng5406 re PCLK 2 -.latch Ng26906 Ng269 re PCLK 2 -.latch Ng24203 Ng401 re PCLK 2 -.latch Ng24346 Ng6040 re PCLK 2 -.latch Ng24207 Ng441 re PCLK 2 -.latch Ng25701 Pg9553 re PCLK 2 -.latch Ng29269 Ng3808 re PCLK 2 -.latch Ng34255 Ng10384 re PCLK 2 -.latch Ng30450 Ng3957 re PCLK 2 -.latch Ng30456 Ng4093 re PCLK 2 -.latch Ng32991 Ng1760 re PCLK 2 -.latch Ng24348 Pg12422 re PCLK 2 -.latch Ng34249 Ng160 re PCLK 2 -.latch Ng30371 Ng2279 re PCLK 2 -.latch Ng29268 Ng3498 re PCLK 2 -.latch Ng29224 Ng586 re PCLK 2 -.latch Pg14189 Pg14201 re PCLK 2 -.latch Ng33017 Ng2619 re PCLK 2 -.latch Ng30339 Ng1183 re PCLK 2 -.latch Ng33967 Ng1608 re PCLK 2 -.latch Pg8784 Pg8785 re PCLK 2 -.latch Pg17519 Pg17577 re PCLK 2 -.latch Ng33559 Ng1779 re PCLK 2 -.latch Ng29255 Ng2652 re PCLK 2 -.latch Ng30368 Ng2193 re PCLK 2 -.latch Ng30375 Ng2393 re PCLK 2 -.latch Ng28052 Ng661 re PCLK 2 -.latch Ng28089 Ng4950 re PCLK 2 -.latch Ng33055 Ng5535 re PCLK 2 -.latch Ng30392 Ng2834 re PCLK 2 -.latch Ng30343 Ng1361 re PCLK 2 -.latch Ng30523 Ng6235 re PCLK 2 -.latch Ng24233 Ng1146 re PCLK 2 -.latch Ng33018 Ng2625 re PCLK 2 -.latch Ng32976 Ng150 re PCLK 2 -.latch Ng30349 Ng1696 re PCLK 2 -.latch Ng33067 Ng6555 re PCLK 2 -.latch Ng26900 Pg14189 re PCLK 2 -.latch Ng33034 Ng3881 re PCLK 2 -.latch Ng30551 Ng6621 re PCLK 2 -.latch Ng25667 Ng3470 re PCLK 2 -.latch Ng30452 Ng3897 re PCLK 2 -.latch Ng25612 Ng518 re PCLK 2 -.latch Ng34719 Ng538 re PCLK 2 -.latch Ng33607 Ng2606 re PCLK 2 -.latch Ng26923 Ng1472 re PCLK 2 -.latch Ng24211 Ng542 re PCLK 2 -.latch Ng33050 Ng5188 re PCLK 2 -.latch Ng24341 Ng5689 re PCLK 2 -.latch Pg19334 Pg13259 re PCLK 2 -.latch Ng24201 Ng405 re PCLK 2 -.latch Ng30463 Ng5216 re PCLK 2 -.latch Pg9743 Ng6494 re PCLK 2 -.latch Ng34464 Ng4669 re PCLK 2 -.latch Ng24243 Ng996 re PCLK 2 -.latch Ng24335 Ng4531 re PCLK 2 -.latch Ng34611 Ng2860 re PCLK 2 -.latch Ng34262 Ng4743 re PCLK 2 -.latch Ng30546 Ng6593 re PCLK 2 -.latch Ng25591 Pg8291 re PCLK 2 -.latch Pg7257 Ng4411 re PCLK 2 -.latch Ng30347 Ng1413 re PCLK 2 -.latch Ng10384 Ng26960 re PCLK 2 -.latch Pg17577 Pg13039 re PCLK 2 -.latch Ng30556 Ng6641 re PCLK 2 -.latch Ng33562 Ng1936 re PCLK 2 -.latch Ng35002 Ng55 re PCLK 2 -.latch Ng25610 Ng504 re PCLK 2 -.latch Ng33015 Ng2587 re PCLK 2 -.latch Ng31896 Ng4480 re PCLK 2 -.latch Ng34004 Ng2311 re PCLK 2 -.latch Ng30428 Ng3602 re PCLK 2 -.latch Ng30485 Ng5571 re PCLK 2 -.latch Ng30422 Ng3578 re PCLK 2 -.latch Ng25714 Pg9555 re PCLK 2 -.latch Ng29294 Ng5827 re PCLK 2 -.latch Ng30423 Ng3582 re PCLK 2 -.latch Ng30529 Ng6271 re PCLK 2 -.latch Ng34028 Ng4688 re PCLK 2 -.latch Ng33587 Ng2380 re PCLK 2 -.latch Ng30460 Ng5196 re PCLK 2 -.latch Ng30401 Ng3227 re PCLK 2 -.latch Ng33990 Ng2020 re PCLK 2 -.latch Pg16693 Pg14518 re PCLK 2 -.latch Pg17291 Pg17316 re PCLK 2 -.latch Ng29309 Ng6541 re PCLK 2 -.latch Ng30411 Ng3203 re PCLK 2 -.latch Ng33546 Ng1668 re PCLK 2 -.latch Ng28085 Ng4760 re PCLK 2 -.latch Ng26904 Ng262 re PCLK 2 -.latch Ng33556 Ng1840 re PCLK 2 -.latch Ng25722 Ng5467 re PCLK 2 -.latch Ng25605 Ng460 re PCLK 2 -.latch Ng33062 Ng6209 re PCLK 2 -.latch Ng26893 [4436] re PCLK 2 -.latch Pg12238 Pg14662 re PCLK 2 -.latch Ng28050 Ng655 re PCLK 2 -.latch Ng34626 Ng3502 re PCLK 2 -.latch Ng33583 Ng2204 re PCLK 2 -.latch Ng30472 Ng5256 re PCLK 2 -.latch Ng34454 Ng4608 re PCLK 2 -.latch Ng34850 Ng794 re PCLK 2 -.latch Pg16955 Pg13906 re PCLK 2 -.latch Pg10306 Ng4423 re PCLK 2 -.latch Ng24272 Ng3689 re PCLK 2 -.latch Pg17678 Ng5685 re PCLK 2 -.latch Ng24214 Ng703 re PCLK 2 -.latch Ng26909 Ng862 re PCLK 2 -.latch Ng30406 Ng3247 re PCLK 2 -.latch Ng33569 Ng2040 re PCLK 2 -.latch Ng34628 Ng4146 re PCLK 2 -.latch Ng34458 Ng4633 re PCLK 2 -.latch Ng24240 Pg7916 re PCLK 2 -.latch Ng34634 Ng4732 re PCLK 2 -.latch Ng25700 Pg9497 re PCLK 2 -.latch Ng29293 Ng5817 re PCLK 2 -.latch Ng33009 Ng2351 re PCLK 2 -.latch Ng33603 Ng2648 re PCLK 2 -.latch Ng24355 Ng6736 re PCLK 2 -.latch Ng34268 Ng4944 re PCLK 2 -.latch Ng25691 Ng4072 re PCLK 2 -.latch Ng26890 Pg7540 re PCLK 2 -.latch Pg7260 Ng4443 re PCLK 2 -.latch Ng29264 Ng3466 re PCLK 2 -.latch Ng28072 Ng4116 re PCLK 2 -.latch Ng31900 Ng5041 re PCLK 2 -.latch Ng26956 Ng4434 re PCLK 2 -.latch Ng29271 Ng3827 re PCLK 2 -.latch Ng29304 Ng6500 re PCLK 2 -.latch Pg13049 Pg17813 re PCLK 2 -.latch Ng29261 Ng3133 re PCLK 2 -.latch Ng28063 Ng3333 re PCLK 2 -.latch Pg13259 Ng979 re PCLK 2 -.latch Ng34027 Ng4681 re PCLK 2 -.latch Ng33961 Ng298 re PCLK 2 -.latch Ng33604 Ng2667 re PCLK 2 -.latch Pg8788 Pg8789 re PCLK 2 -.latch Ng32995 Ng1894 re PCLK 2 -.latch Ng34624 Ng2988 re PCLK 2 -.latch Ng30415 Ng3538 re PCLK 2 -.latch Ng33536 Ng301 re PCLK 2 -.latch Ng26888 Ng341 re PCLK 2 -.latch Ng28055 Ng827 re PCLK 2 -.latch Ng24238 Pg17291 re PCLK 2 -.latch Ng33600 Ng2555 re PCLK 2 -.latch Ng28105 Ng5011 re PCLK 2 -.latch Ng34721 Ng199 re PCLK 2 -.latch Ng29307 Ng6523 re PCLK 2 -.latch Ng30345 Ng1526 re PCLK 2 -.latch Ng34453 Ng4601 re PCLK 2 -.latch Ng32980 Ng854 re PCLK 2 -.latch Ng29238 Ng1484 re PCLK 2 -.latch Ng34639 Ng4922 re PCLK 2 -.latch Ng25695 Ng5080 re PCLK 2 -.latch Ng33057 Ng5863 re PCLK 2 -.latch Ng26969 Ng4581 re PCLK 2 -.latch Ng29253 Ng2518 re PCLK 2 -.latch Ng34021 Ng2567 re PCLK 2 -.latch Ng26895 Ng568 re PCLK 2 -.latch Ng30413 Ng3263 re PCLK 2 -.latch Ng30549 Ng6613 re PCLK 2 -.latch Ng24347 Ng6044 re PCLK 2 -.latch Ng25758 Ng6444 re PCLK 2 -.latch Ng34808 Ng2965 re PCLK 2 -.latch Ng30501 Ng5857 re PCLK 2 -.latch Ng33969 Ng1616 re PCLK 2 -.latch Ng34440 Ng890 re PCLK 2 -.latch Pg17607 Pg17646 re PCLK 2 -.latch Ng30433 Ng3562 re PCLK 2 -.latch Ng21900 Pg10122 re PCLK 2 -.latch Ng26921 Ng1404 re PCLK 2 -.latch Ng29270 Ng3817 re PCLK 2 -.latch Ng34878 Ng93 re PCLK 2 -.latch Ng33038 Ng4501 re PCLK 2 -.latch Ng31865 Ng287 re PCLK 2 -.latch Ng26926 Ng2724 re PCLK 2 -.latch Ng28083 Ng4704 re PCLK 2 -.latch Ng29209 Ng22 re PCLK 2 -.latch Ng34797 Ng2878 re PCLK 2 -.latch Ng30478 Ng5220 re PCLK 2 -.latch Ng34724 Ng617 re PCLK 2 -.latch Ng24212 Pg12368 re PCLK 2 -.latch Ng26883 Ng316 re PCLK 2 -.latch Ng32985 Ng1277 re PCLK 2 -.latch Ng25761 Ng6513 re PCLK 2 -.latch Ng26886 Ng336 re PCLK 2 -.latch Ng34796 Ng2882 re PCLK 2 -.latch Ng32982 Ng933 re PCLK 2 -.latch Ng33561 Ng1906 re PCLK 2 -.latch Ng26880 Ng305 re PCLK 2 -.latch Ng34992 Ng8 re PCLK 2 -.latch Ng26931 Ng2799 re PCLK 2 -.latch Pg14147 Pg14167 re PCLK 2 -.latch Pg13039 Pg17787 re PCLK 2 -.latch Ng34641 Ng4912 re PCLK 2 -.latch Ng34629 Ng4157 re PCLK 2 -.latch Ng33598 Ng2541 re PCLK 2 -.latch Ng33576 Ng2153 re PCLK 2 -.latch Ng34720 Ng550 re PCLK 2 -.latch Ng26902 Ng255 re PCLK 2 -.latch Ng29244 Ng1945 re PCLK 2 -.latch Ng30468 Ng5240 re PCLK 2 -.latch Ng26924 Ng1478 re PCLK 2 -.latch Ng33031 Ng3863 re PCLK 2 -.latch Ng29245 Ng1959 re PCLK 2 -.latch Ng29266 Ng3480 re PCLK 2 -.latch Ng30559 Ng6653 re PCLK 2 -.latch Pg14749 Pg17764 re PCLK 2 -.latch Ng34794 Ng2864 re PCLK 2 -.latch Ng28087 Ng4894 re PCLK 2 -.latch Pg14635 Pg17678 re PCLK 2 -.latch Ng30435 Ng3857 re PCLK 2 -.latch Pg16659 Pg16693 re PCLK 2 -.latch Ng25609 Ng499 re PCLK 2 -.latch Ng28057 Ng1002 re PCLK 2 -.latch Ng34439 Ng776 re PCLK 2 -.latch Pg10500 Ng1236 re PCLK 2 -.latch Ng34260 Ng4646 re PCLK 2 -.latch Ng33012 Ng2476 re PCLK 2 -.latch Ng32989 Ng1657 re PCLK 2 -.latch Ng34006 Ng2375 re PCLK 2 -.latch Ng34847 Ng63 re PCLK 2 -.latch Pg14738 Pg17739 re PCLK 2 -.latch Pg8719 Ng358 re PCLK 2 -.latch Ng26910 Ng896 re PCLK 2 -.latch Ng28043 Ng283 re PCLK 2 -.latch Ng33021 Ng3161 re PCLK 2 -.latch Ng29251 Ng2384 re PCLK 2 -.latch Pg12470 Pg14828 re PCLK 2 -.latch Ng34456 Ng4616 re PCLK 2 -.latch Ng26968 Ng4561 re PCLK 2 -.latch Ng33991 Ng2024 re PCLK 2 -.latch Pg8279 Ng3451 re PCLK 2 -.latch Ng26930 Ng2795 re PCLK 2 -.latch Ng34599 Ng613 re PCLK 2 -.latch Ng28082 Ng4527 re PCLK 2 -.latch Ng33557 Ng1844 re PCLK 2 -.latch Ng30511 Ng5937 re PCLK 2 -.latch Ng33045 Ng4546 re PCLK 2 -.latch Ng30379 Ng2523 re PCLK 2 -.latch Ng24267 Pg11349 re PCLK 2 -.latch Ng34020 Ng2643 re PCLK 2 -.latch Ng24249 Ng1489 re PCLK 2 -.latch Ng25592 Pg8358 re PCLK 2 -.latch Ng30382 Ng2551 re PCLK 2 -.latch Ng29285 Ng5156 re PCLK 2 -.latch Pg12919 [4421] re PCLK 2 -.latch Ng25662 Pg8279 re PCLK 2 -.latch Ng21896 Pg8839 re PCLK 2 -.latch Ng33563 Ng1955 re PCLK 2 -.latch Ng33622 Ng6049 re PCLK 2 -.latch Ng33582 Ng2273 re PCLK 2 -.latch Pg17871 Pg14749 re PCLK 2 -.latch Ng28086 Ng4771 re PCLK 2 -.latch Ng25744 Ng6098 re PCLK 2 -.latch Ng29262 Ng3147 re PCLK 2 -.latch Ng24270 Ng3347 re PCLK 2 -.latch Ng33581 Ng2269 re PCLK 2 -.latch Pg8358 Ng191 re PCLK 2 -.latch Ng26937 Ng2712 re PCLK 2 -.latch Ng34849 Ng626 re PCLK 2 -.latch Ng28060 Ng2729 re PCLK 2 -.latch Ng33618 Ng5357 re PCLK 2 -.latch Ng34038 Ng4991 re PCLK 2 -.latch Pg13068 Pg17819 re PCLK 2 -.latch Ng34032 Ng4709 re PCLK 2 -.latch Ng34803 Ng2927 re PCLK 2 -.latch Ng34459 Ng4340 re PCLK 2 -.latch Ng30509 Ng5929 re PCLK 2 -.latch Ng34640 Ng4907 re PCLK 2 -.latch Pg14421 Pg16874 re PCLK 2 -.latch Ng28069 Ng4035 re PCLK 2 -.latch Ng21899 Ng2946 re PCLK 2 -.latch Ng31868 Ng918 re PCLK 2 -.latch Ng26938 Ng4082 re PCLK 2 -.latch Ng25756 Pg9743 re PCLK 2 -.latch Ng30363 Ng2036 re PCLK 2 -.latch Ng30334 Ng577 re PCLK 2 -.latch Ng33970 Ng1620 re PCLK 2 -.latch Ng30391 Ng2831 re PCLK 2 -.latch Ng25615 Ng667 re PCLK 2 -.latch Ng33540 Ng930 re PCLK 2 -.latch Ng30445 Ng3937 re PCLK 2 -.latch Ng25617 Ng817 re PCLK 2 -.latch Ng24247 Ng1249 re PCLK 2 -.latch Ng24215 Ng837 re PCLK 2 -.latch Pg14451 Pg16924 re PCLK 2 -.latch Ng33964 Ng599 re PCLK 2 -.latch Ng25719 Ng5475 re PCLK 2 -.latch Ng29228 Ng739 re PCLK 2 -.latch Ng30514 Ng5949 re PCLK 2 -.latch Ng33627 Ng6682 re PCLK 2 -.latch Ng24231 Ng904 re PCLK 2 -.latch Ng34615 Ng2873 re PCLK 2 -.latch Ng30356 Ng1854 re PCLK 2 -.latch Ng25696 Ng5084 re PCLK 2 -.latch Ng30493 Ng5603 re PCLK 2 -.latch Pg8917 Pg8870 re PCLK 2 -.latch Ng33594 Ng2495 re PCLK 2 -.latch Ng34009 Ng2437 re PCLK 2 -.latch Ng30365 Ng2102 re PCLK 2 -.latch Ng33004 Ng2208 re PCLK 2 -.latch Ng34018 Ng2579 re PCLK 2 -.latch Ng25685 Ng4064 re PCLK 2 -.latch Ng34040 Ng4899 re PCLK 2 -.latch Ng25639 Ng2719 re PCLK 2 -.latch Ng34029 Ng4785 re PCLK 2 -.latch Ng30488 Ng5583 re PCLK 2 -.latch Ng34600 Ng781 re PCLK 2 -.latch Ng29300 Ng6173 re PCLK 2 -.latch Pg14705 Pg17743 re PCLK 2 -.latch Ng34802 Ng2917 re PCLK 2 -.latch Ng25614 Ng686 re PCLK 2 -.latch Ng28058 Ng1252 re PCLK 2 -.latch Ng29225 Ng671 re PCLK 2 -.latch Ng33580 Ng2265 re PCLK 2 -.latch Ng30532 Ng6283 re PCLK 2 -.latch Pg17845 Pg14705 re PCLK 2 -.latch Pg17674 Pg17519 re PCLK 2 -.latch Pg8783 Pg8784 re PCLK 2 -.latch Ng33054 Ng5527 re PCLK 2 -.latch Ng26962 Ng4489 re PCLK 2 -.latch Ng33564 Ng1974 re PCLK 2 -.latch Ng32984 Ng1270 re PCLK 2 -.latch Ng34039 Ng4966 re PCLK 2 -.latch Ng33065 Ng6227 re PCLK 2 -.latch Ng30443 Ng3929 re PCLK 2 -.latch Ng29291 Ng5503 re PCLK 2 -.latch Ng24279 Ng4242 re PCLK 2 -.latch Ng30508 Ng5925 re PCLK 2 -.latch Ng29232 Ng1124 re PCLK 2 -.latch Ng34269 Ng4955 re PCLK 2 -.latch Ng30464 Ng5224 re PCLK 2 -.latch Ng33988 Ng2012 re PCLK 2 -.latch Ng30522 Ng6203 re PCLK 2 -.latch Ng25708 Ng5120 re PCLK 2 -.latch Pg14662 Pg17674 re PCLK 2 -.latch Ng30374 Ng2389 re PCLK 2 -.latch Ng26953 Ng4438 re PCLK 2 -.latch Ng34008 Ng2429 re PCLK 2 -.latch Ng34444 Ng2787 re PCLK 2 -.latch Ng34731 Ng1287 re PCLK 2 -.latch Ng33606 Ng2675 re PCLK 2 -.latch Ng24334 [4507] re PCLK 2 -.latch Ng34265 Ng4836 re PCLK 2 -.latch Ng30340 Ng1199 re PCLK 2 -.latch Ng24257 Pg19357 re PCLK 2 -.latch Ng30482 Ng5547 re PCLK 2 -.latch Ng34604 Ng2138 re PCLK 2 -.latch Pg13926 Pg16744 re PCLK 2 -.latch Ng33591 Ng2338 re PCLK 2 -.latch Pg8918 Pg8919 re PCLK 2 -.latch Ng30525 Ng6247 re PCLK 2 -.latch Ng26929 Ng2791 re PCLK 2 -.latch Ng30448 Ng3949 re PCLK 2 -.latch Ng34602 Ng1291 re PCLK 2 -.latch Ng30513 Ng5945 re PCLK 2 -.latch Ng30469 Ng5244 re PCLK 2 -.latch Ng33608 Ng2759 re PCLK 2 -.latch Ng33626 Ng6741 re PCLK 2 -.latch Ng34725 Ng785 re PCLK 2 -.latch Ng30342 Ng1259 re PCLK 2 -.latch Ng29267 Ng3484 re PCLK 2 -.latch Ng25593 Ng209 re PCLK 2 -.latch Ng30548 Ng6609 re PCLK 2 -.latch Ng33052 Ng5517 re PCLK 2 -.latch Ng34012 Ng2449 re PCLK 2 -.latch Ng34017 Ng2575 re PCLK 2 -.latch [4507] Ng65 re PCLK 2 -.latch Ng24263 Ng2715 re PCLK 2 -.latch Ng26912 Ng936 re PCLK 2 -.latch Ng30364 Ng2098 re PCLK 2 -.latch Ng34254 Ng4462 re PCLK 2 -.latch Ng34251 Ng604 re PCLK 2 -.latch Ng30560 Ng6589 re PCLK 2 -.latch Ng33983 Ng1886 re PCLK 2 -.latch Pg13085 Pg17845 re PCLK 2 -.latch Pg13099 Pg17871 re PCLK 2 -.latch Ng24204 Ng429 re PCLK 2 -.latch Ng33980 Ng1870 re PCLK 2 -.latch Ng34631 Ng4249 re PCLK 2 -.latch Ng29243 Ng1825 re PCLK 2 -.latch Ng25623 Ng1008 re PCLK 2 -.latch Ng26950 Ng4392 re PCLK 2 -.latch Ng30431 Ng3546 re PCLK 2 -.latch Ng30467 Ng5236 re PCLK 2 -.latch Ng30353 Ng1768 re PCLK 2 -.latch Ng34467 Ng4854 re PCLK 2 -.latch Ng30442 Ng3925 re PCLK 2 -.latch Ng29305 Ng6509 re PCLK 2 -.latch Ng25616 Ng732 re PCLK 2 -.latch Ng29252 Ng2504 re PCLK 2 -.latch Pg13272 Ng1322 re PCLK 2 -.latch Ng6972 Ng4520 re PCLK 2 -.latch Pg8916 Pg8917 re PCLK 2 -.latch Ng33003 Ng2185 re PCLK 2 -.latch Ng34613 Ng37 re PCLK 2 -.latch Pg16748 Ng4031 re PCLK 2 -.latch Ng33570 Ng2070 re PCLK 2 -.latch [4661] [4658] re PCLK 2 -.latch Ng34734 Ng4176 re PCLK 2 -.latch Ng24275 Pg11418 re PCLK 2 -.latch Pg7243 Ng4405 re PCLK 2 -.latch Pg14167 Ng872 re PCLK 2 -.latch Ng29302 Ng6181 re PCLK 2 -.latch Ng24349 Ng6381 re PCLK 2 -.latch Ng34264 Ng4765 re PCLK 2 -.latch Ng30484 Ng5563 re PCLK 2 -.latch Ng25634 Ng1395 re PCLK 2 -.latch Ng33567 Ng1913 re PCLK 2 -.latch Ng33585 Ng2331 re PCLK 2 -.latch Ng30527 Ng6263 re PCLK 2 -.latch Ng34995 Ng50 re PCLK 2 -.latch Ng30447 Ng3945 re PCLK 2 -.latch Pg7540 Ng347 re PCLK 2 -.latch Ng34256 Ng4473 re PCLK 2 -.latch Ng25630 Ng1266 re PCLK 2 -.latch Ng29290 Ng5489 re PCLK 2 -.latch Ng29227 Ng714 re PCLK 2 -.latch Ng31872 Ng2748 re PCLK 2 -.latch Ng29287 Ng5471 re PCLK 2 -.latch Ng31897 Ng4540 re PCLK 2 -.latch Pg17764 Ng6723 re PCLK 2 -.latch Ng30562 Ng6605 re PCLK 2 -.latch Ng34011 Ng2445 re PCLK 2 -.latch Ng33996 Ng2173 re PCLK 2 -.latch Ng21898 Pg9019 re PCLK 2 -.latch Ng33014 Ng2491 re PCLK 2 -.latch Ng34465 Ng4849 re PCLK 2 -.latch Ng33995 Ng2169 re PCLK 2 -.latch Ng30372 Ng2283 re PCLK 2 -.latch Ng30545 Ng6585 re PCLK 2 -.latch Ng30389 [4428] re PCLK 2 -.latch Ng33590 Ng2407 re PCLK 2 -.latch Ng34616 Ng2868 re PCLK 2 -.latch Ng26927 Ng2767 re PCLK 2 -.latch Ng32992 Ng1783 re PCLK 2 -.latch Pg13895 Pg16718 re PCLK 2 -.latch Ng25631 Ng1312 re PCLK 2 -.latch Ng30477 Ng5212 re PCLK 2 -.latch Ng34632 Ng4245 re PCLK 2 -.latch Ng28046 Ng645 re PCLK 2 -.latch Pg9019 Ng4291 re PCLK 2 -.latch Ng26896 [4435] re PCLK 2 -.latch Ng25602 Ng182 re PCLK 2 -.latch Ng26916 Ng1129 re PCLK 2 -.latch Ng33578 Ng2227 re PCLK 2 -.latch Pg8787 Pg8788 re PCLK 2 -.latch Ng33579 Ng2246 re PCLK 2 -.latch Ng30354 Ng1830 re PCLK 2 -.latch Ng30425 Ng3590 re PCLK 2 -.latch Ng24200 Ng392 re PCLK 2 -.latch Ng33544 Ng1592 re PCLK 2 -.latch Ng25764 Ng6505 re PCLK 2 -.latch Ng24246 Ng1221 re PCLK 2 -.latch Ng30507 Ng5921 re PCLK 2 -.latch Ng26889 [4431] re PCLK 2 -.latch Ng30333 Ng146 re PCLK 2 -.latch Pg8291 Ng218 re PCLK 2 -.latch Ng32998 Ng1932 re PCLK 2 -.latch Ng32987 Ng1624 re PCLK 2 -.latch Ng25702 Ng5062 re PCLK 2 -.latch Ng29286 Ng5462 re PCLK 2 -.latch Ng34606 Ng2689 re PCLK 2 -.latch Ng33070 Ng6573 re PCLK 2 -.latch Ng29240 Ng1677 re PCLK 2 -.latch Ng32999 Ng2028 re PCLK 2 -.latch Ng33605 Ng2671 re PCLK 2 -.latch Ng24255 Pg10527 re PCLK 2 -.latch Ng26945 Pg7243 re PCLK 2 -.latch Ng33558 Ng1848 re PCLK 2 -.latch Ng25699 [4434] re PCLK 2 -.latch Ng29289 Ng5485 re PCLK 2 -.latch Ng30388 Ng2741 re PCLK 2 -.latch Pg12184 Pg11678 re PCLK 2 -.latch Ng29254 Ng2638 re PCLK 2 -.latch Ng28074 Ng4122 re PCLK 2 -.latch Ng34450 Ng4322 re PCLK 2 -.latch Ng30512 Ng5941 re PCLK 2 -.latch Ng33572 Ng2108 re PCLK 2 -.latch Pg17646 Pg13068 re PCLK 2 -.latch Ng25 Ng25 re PCLK 2 -.latch Ng33551 Ng1644 re PCLK 2 -.latch Ng33538 Ng595 re PCLK 2 -.latch Ng33005 Ng2217 re PCLK 2 -.latch Ng24248 Ng1319 re PCLK 2 -.latch Ng33002 Ng2066 re PCLK 2 -.latch Ng24234 Ng1152 re PCLK 2 -.latch Ng30471 Ng5252 re PCLK 2 -.latch Ng34000 Ng2165 re PCLK 2 -.latch Ng34016 Ng2571 re PCLK 2 -.latch Ng33048 Ng5176 re PCLK 2 -.latch Pg17819 Pg14673 re PCLK 2 -.latch Ng25628 Ng1211 re PCLK 2 -.latch Ng26934 Ng2827 re PCLK 2 -.latch Pg14201 Pg14217 re PCLK 2 -.latch Ng34468 Ng4859 re PCLK 2 -.latch Ng24202 Ng424 re PCLK 2 -.latch Ng33542 Ng1274 re PCLK 2 -.latch Pg17404 Pg17423 re PCLK 2 -.latch Pg33435 Ng85 re PCLK 2 -.latch Ng34445 Ng2803 re PCLK 2 -.latch Ng33555 Ng1821 re PCLK 2 -.latch Ng34013 Ng2509 re PCLK 2 -.latch Ng28091 Ng5073 re PCLK 2 -.latch Ng26919 Ng1280 re PCLK 2 -.latch [4658] [4651] re PCLK 2 -.latch Pg17685 Pg13085 re PCLK 2 -.latch Ng30554 Ng6633 re PCLK 2 -.latch Ng29281 Ng5124 re PCLK 2 -.latch Pg17316 Pg17400 re PCLK 2 -.latch Ng30537 Ng6303 re PCLK 2 -.latch Ng28092 Ng5069 re PCLK 2 -.latch Ng34732 Ng2994 re PCLK 2 -.latch Ng28049 Ng650 re PCLK 2 -.latch Ng33545 Ng1636 re PCLK 2 -.latch Ng30441 Ng3921 re PCLK 2 -.latch Ng29247 Ng2093 re PCLK 2 -.latch Ng24354 Ng6732 re PCLK 2 -.latch Ng25636 Ng1306 re PCLK 2 -.latch Ng26914 Ng1061 re PCLK 2 -.latch Ng25670 Ng3462 re PCLK 2 -.latch Ng33998 Ng2181 re PCLK 2 -.latch Ng25626 Ng956 re PCLK 2 -.latch Ng33977 Ng1756 re PCLK 2 -.latch Ng29297 Ng5849 re PCLK 2 -.latch Ng28071 Ng4112 re PCLK 2 -.latch Ng30387 Ng2685 re PCLK 2 -.latch Ng33577 Ng2197 re PCLK 2 -.latch Ng33592 Ng2421 re PCLK 2 -.latch Ng26913 Ng1046 re PCLK 2 -.latch Ng28044 Ng482 re PCLK 2 -.latch Ng26948 Ng4401 re PCLK 2 -.latch Ng30344 Ng1514 re PCLK 2 -.latch Ng26885 Ng329 re PCLK 2 -.latch Ng33069 Ng6565 re PCLK 2 -.latch Ng34621 Ng2950 re PCLK 2 -.latch Ng28059 Ng1345 re PCLK 2 -.latch Ng25762 Ng6533 re PCLK 2 -.latch Pg16624 Pg14421 re PCLK 2 -.latch Ng34633 Ng4727 re PCLK 2 -.latch Ng24352 Pg12470 re PCLK 2 -.latch Ng26925 Ng1536 re PCLK 2 -.latch Ng30446 Ng3941 re PCLK 2 -.latch Ng25597 Ng370 re PCLK 2 -.latch Ng24342 Ng5694 re PCLK 2 -.latch Ng30357 Ng1858 re PCLK 2 -.latch Ng26908 Ng446 re PCLK 2 -.latch Ng30399 Ng3219 re PCLK 2 -.latch Ng29242 Ng1811 re PCLK 2 -.latch Ng30547 Ng6601 re PCLK 2 -.latch Ng34010 Ng2441 re PCLK 2 -.latch Ng33986 Ng1874 re PCLK 2 -.latch Ng34257 Ng4349 re PCLK 2 -.latch Ng30544 Ng6581 re PCLK 2 -.latch Ng30561 Ng6597 re PCLK 2 -.latch Ng30430 Ng3610 re PCLK 2 -.latch Ng34799 Ng2890 re PCLK 2 -.latch Ng33565 Ng1978 re PCLK 2 -.latch Ng33968 Ng1612 re PCLK 2 -.latch Ng34879 Ng112 re PCLK 2 -.latch Ng34793 Ng2856 re PCLK 2 -.latch Ng33566 Ng1982 re PCLK 2 -.latch Pg17688 Pg17722 re PCLK 2 -.latch Ng30465 Ng5228 re PCLK 2 -.latch Ng28073 Ng4119 re PCLK 2 -.latch Ng24351 Ng6390 re PCLK 2 -.latch Ng30346 Ng1542 re PCLK 2 -.latch Ng21893 Ng4258 re PCLK 2 -.latch [4651] Ng4818 re PCLK 2 -.latch Ng31904 Ng5033 re PCLK 2 -.latch Ng34635 Ng4717 re PCLK 2 -.latch Ng25637 Ng1554 re PCLK 2 -.latch Ng29274 Ng3849 re PCLK 2 -.latch Pg14828 Pg17778 re PCLK 2 -.latch Ng30396 Ng3199 re PCLK 2 -.latch Ng25735 Ng5845 re PCLK 2 -.latch Ng34037 Ng4975 re PCLK 2 -.latch Ng34791 Ng790 re PCLK 2 -.latch Ng30520 Ng5913 re PCLK 2 -.latch Ng30358 Ng1902 re PCLK 2 -.latch Ng29299 Ng6163 re PCLK 2 -.latch Ng28081 Ng4125 re PCLK 2 -.latch Ng28096 Ng4821 re PCLK 2 -.latch Ng28088 Ng4939 re PCLK 2 -.latch Ng24241 Pg19334 re PCLK 2 -.latch Ng30397 Ng3207 re PCLK 2 -.latch Ng4520 Ng4483 re PCLK 2 -.latch Ng30409 Ng3259 re PCLK 2 -.latch Ng29284 Ng5142 re PCLK 2 -.latch Ng30470 Ng5248 re PCLK 2 -.latch Ng30367 Ng2126 re PCLK 2 -.latch Ng24273 Ng3694 re PCLK 2 -.latch Ng29288 Ng5481 re PCLK 2 -.latch Ng30359 Ng1964 re PCLK 2 -.latch Ng25698 Ng5097 re PCLK 2 -.latch Ng30398 Ng3215 re PCLK 2 -.latch Pg13906 Pg16748 re PCLK 2 -.latch Pg33079 Ng111 re PCLK 2 -.latch Ng26952 Ng4427 re PCLK 2 -.latch Ng26928 Ng2779 re PCLK 2 -.latch Pg8785 Pg8786 re PCLK 2 -.latch Ng26954 Pg7245 re PCLK 2 -.latch Ng30351 Ng1720 re PCLK 2 -.latch Ng31871 Ng1367 re PCLK 2 -.latch Pg9553 Ng5112 re PCLK 2 -.latch Ng26939 Ng4145 re PCLK 2 -.latch Ng33994 Ng2161 re PCLK 2 -.latch Ng25596 Ng376 re PCLK 2 -.latch Ng33586 Ng2361 re PCLK 2 -.latch Ng21901 Pg11447 re PCLK 2 -.latch Ng31866 Ng582 re PCLK 2 -.latch Ng33000 Ng2051 re PCLK 2 -.latch Ng26918 Ng1193 re PCLK 2 -.latch Ng30373 Ng2327 re PCLK 2 -.latch Ng28056 Ng907 re PCLK 2 -.latch Ng34601 Ng947 re PCLK 2 -.latch Ng30355 Ng1834 re PCLK 2 -.latch Ng30426 Ng3594 re PCLK 2 -.latch Ng34805 Ng2999 re PCLK 2 -.latch Ng34002 Ng2303 re PCLK 2 -.latch Pg17778 Pg17688 re PCLK 2 -.latch Ng28053 Ng699 re PCLK 2 -.latch Ng29229 Ng723 re PCLK 2 -.latch Ng33620 Ng5703 re PCLK 2 -.latch Ng34722 Ng546 re PCLK 2 -.latch Ng33599 Ng2472 re PCLK 2 -.latch Ng30515 Ng5953 re PCLK 2 -.latch Ng25649 Pg8277 re PCLK 2 -.latch Ng33979 Ng1740 re PCLK 2 -.latch Ng30417 Ng3550 re PCLK 2 -.latch Ng25683 Ng3845 re PCLK 2 -.latch Ng33574 Ng2116 re PCLK 2 -.latch Pg17813 Pg14635 re PCLK 2 -.latch Ng30410 Ng3195 re PCLK 2 -.latch Ng30454 Ng3913 re PCLK 2 -.latch Ng34024 Pg10306 re PCLK 2 -.latch Ng33547 Ng1687 re PCLK 2 -.latch Ng30386 Ng2681 re PCLK 2 -.latch Ng33596 Ng2533 re PCLK 2 -.latch Ng26887 Ng324 re PCLK 2 -.latch Ng34607 Ng2697 re PCLK 2 -.latch Ng31895 Ng4417 re PCLK 2 -.latch Ng33068 Ng6561 re PCLK 2 -.latch Ng29233 Ng1141 re PCLK 2 -.latch Ng24258 Pg12923 re PCLK 2 -.latch Ng30376 Ng2413 re PCLK 2 -.latch Ng33549 Ng1710 re PCLK 2 -.latch Ng29308 Ng6527 re PCLK 2 -.latch Ng30408 Ng3255 re PCLK 2 -.latch Ng29241 Ng1691 re PCLK 2 -.latch Ng34620 Ng2936 re PCLK 2 -.latch Ng33621 Ng5644 re PCLK 2 -.latch Ng25707 Ng5152 re PCLK 2 -.latch Ng24339 Ng5352 re PCLK 2 -.latch Pg11770 Pg8915 re PCLK 2 -.latch Ng34443 Ng2775 re PCLK 2 -.latch Ng34619 Ng2922 re PCLK 2 -.latch Ng29234 Ng1111 re PCLK 2 -.latch Ng30503 Ng5893 re PCLK 2 -.latch Pg16718 Pg16603 re PCLK 2 -.latch Ng30550 Ng6617 re PCLK 2 -.latch Ng33001 Ng2060 re PCLK 2 -.latch Ng33040 Ng4512 re PCLK 2 -.latch Ng30492 Ng5599 re PCLK 2 -.latch Ng25664 Ng3401 re PCLK 2 -.latch Ng26944 Ng4366 re PCLK 2 -.latch Pg13881 Pg16722 re PCLK 2 -.latch Ng34614 [4433] re PCLK 2 -.latch Ng29260 Ng3129 re PCLK 2 -.latch Pg16686 Ng3329 re PCLK 2 -.latch Ng33047 Ng5170 re PCLK 2 -.latch Ng25692 Ng26959 re PCLK 2 -.latch Ng25733 Ng5821 re PCLK 2 -.latch Ng30536 Ng6299 re PCLK 2 -.latch Pg7916 Pg8416 re PCLK 2 -.latch Ng29246 Ng2079 re PCLK 2 -.latch Ng34261 Ng4698 re PCLK 2 -.latch Ng33611 Ng3703 re PCLK 2 -.latch Ng25638 Ng1559 re PCLK 2 -.latch Ng34728 Ng943 re PCLK 2 -.latch Ng29222 Ng411 re PCLK 2 -.latch Ng25742 Pg9682 re PCLK 2 -.latch Ng30449 Ng3953 re PCLK 2 -.latch Ng34608 Ng2704 re PCLK 2 -.latch Ng24345 Ng6035 re PCLK 2 -.latch Ng25635 Ng1300 re PCLK 2 -.latch Ng25686 Ng4057 re PCLK 2 -.latch Ng30461 Ng5200 re PCLK 2 -.latch Ng34466 Ng4843 re PCLK 2 -.latch Ng31901 Ng5046 re PCLK 2 -.latch Ng29249 Ng2250 re PCLK 2 -.latch Ng26882 Ng26885 re PCLK 2 -.latch Ng33041 Ng4549 re PCLK 2 -.latch Ng33011 Ng2453 re PCLK 2 -.latch Ng25734 Ng5841 re PCLK 2 -.latch Pg12300 Pg14694 re PCLK 2 -.latch Ng34618 Ng2912 re PCLK 2 -.latch Ng33010 Ng2357 re PCLK 2 -.latch Pg8919 Pg8920 re PCLK 2 -.latch Ng31864 Ng164 re PCLK 2 -.latch Ng34630 Ng4253 re PCLK 2 -.latch Ng31898 Ng5016 re PCLK 2 -.latch Ng25653 Ng3119 re PCLK 2 -.latch Ng25632 Ng1351 re PCLK 2 -.latch Ng32988 Ng1648 re PCLK 2 -.latch Ng33616 Ng6972 re PCLK 2 -.latch Ng29280 Ng5115 re PCLK 2 -.latch Ng33609 Ng3352 re PCLK 2 -.latch Ng30563 Ng6657 re PCLK 2 -.latch Ng33044 Ng4552 re PCLK 2 -.latch Ng30437 Ng3893 re PCLK 2 -.latch Ng30412 Ng3211 re PCLK 2 -.latch Pg17604 Pg13049 re PCLK 2 -.latch Pg16603 Pg16624 re PCLK 2 -.latch Ng30491 Ng5595 re PCLK 2 -.latch Ng30434 Ng3614 re PCLK 2 -.latch Ng34612 Ng2894 re PCLK 2 -.latch Ng29259 Ng3125 re PCLK 2 -.latch Pg13865 Pg16686 re PCLK 2 -.latch Ng25681 Ng3821 re PCLK 2 -.latch Ng25687 Ng4141 re PCLK 2 -.latch Ng33617 Ng6974 re PCLK 2 -.latch Ng30479 Ng5272 re PCLK 2 -.latch Ng29256 Ng2735 re PCLK 2 -.latch Ng28054 Ng728 re PCLK 2 -.latch Ng30535 Ng6295 re PCLK 2 -.latch Ng30385 Ng2661 re PCLK 2 -.latch Ng30361 Ng1988 re PCLK 2 -.latch Ng25705 Ng5128 re PCLK 2 -.latch Ng24260 Ng1548 re PCLK 2 -.latch Ng29257 Ng3106 re PCLK 2 -.latch Ng34461 Ng4659 re PCLK 2 -.latch Ng34258 Ng4358 re PCLK 2 -.latch Ng32993 Ng1792 re PCLK 2 -.latch Ng33992 Ng2084 re PCLK 2 -.latch Ng30394 Ng3187 re PCLK 2 -.latch Ng34449 Ng4311 re PCLK 2 -.latch Ng34019 Ng2583 re PCLK 2 -.latch Ng21726 Ng3003 re PCLK 2 -.latch Ng29231 Ng1094 re PCLK 2 -.latch Ng25682 Ng3841 re PCLK 2 -.latch Ng21897 Ng4284 re PCLK 2 -.latch Ng30395 Ng3191 re PCLK 2 -.latch Ng21892 Ng4239 re PCLK 2 -.latch Pg8789 Ng4180 re PCLK 2 -.latch Ng28048 Ng691 re PCLK 2 -.latch Ng34723 Ng534 re PCLK 2 -.latch Ng25598 Ng385 re PCLK 2 -.latch Ng33987 Ng2004 re PCLK 2 -.latch Ng30380 Ng2527 re PCLK 2 -.latch Pg9555 Ng5456 re PCLK 2 -.latch Ng26965 Ng4420 re PCLK 2 -.latch Ng25706 Ng5148 re PCLK 2 -.latch Ng30458 Ng4507 re PCLK 2 -.latch Ng24338 Ng5348 re PCLK 2 -.latch Ng30400 Ng3223 re PCLK 2 -.latch Ng34623 Ng2970 re PCLK 2 -.latch Ng24343 Ng5698 re PCLK 2 -.latch Ng30473 Ng5260 re PCLK 2 -.latch Ng24252 Ng1521 re PCLK 2 -.latch Ng33028 Ng3522 re PCLK 2 -.latch Ng29258 Ng3115 re PCLK 2 -.latch Ng30407 Ng3251 re PCLK 2 -.latch Ng26958 Pg12832 re PCLK 2 -.latch Ng34457 Ng4628 re PCLK 2 -.latch Ng33568 Ng1996 re PCLK 2 -.latch Ng25663 Pg8342 re PCLK 2 -.latch Ng26964 Ng4515 re PCLK 2 -.latch Pg8786 Pg8787 re PCLK 2 -.latch Ng34735 Ng4300 re PCLK 2 -.latch Ng30352 Ng1724 re PCLK 2 -.latch Ng33543 Ng1379 re PCLK 2 -.latch Ng24271 Pg11388 re PCLK 2 -.latch Ng33981 Ng1878 re PCLK 2 -.latch Ng30500 Ng5619 re PCLK 2 -.latch Ng34786 Ng71 re PCLK 2 -.latch Ng29277 [4437] re PCLK 2 -.names n4486 Ng22 Pg34972 -0- 1 --0 1 -.names Ng4369 Ng4366 n1368 [4366] -11- 1 -1-1 1 -.names n1121 Ng22 Pg34927 -0- 1 --0 1 -.names n1141 Ng22 Pg34925 -0- 1 --0 1 -.names n204 Ng22 Pg34923 -0- 1 --0 1 -.names n1119 Ng22 Pg34921 -0- 1 --0 1 -.names n1092 Ng22 Pg34919 -0- 1 --0 1 -.names n981 Ng22 Pg34917 -0- 1 --0 1 -.names n1132 Ng22 Pg34915 -0- 1 --0 1 -.names n569 Ng22 Pg34913 -0- 1 --0 1 -.names Ng890 Ng528 n1170 Ng479 [4376] -11-- 1 -1-1- 1 -1--0 1 -.names Pg34597 -.names Pg113 Ng2868 [4378] -0- 1 --0 1 -.names Pg113 Ng2873 [4379] -0- 1 --0 1 -.names n6112 Pg34435 -0 1 -.names n1189 n1636 Pg34425 -0- 1 --0 1 -.names n1129 n1169 n1638 Pg34383 -1-- 1 --0- 1 ---0 1 -.names Pg34240 -.names Pg34239 -.names Pg34238 -.names Pg34237 -.names Pg34236 -.names Pg34235 -.names Pg34234 -.names Pg34233 -.names Pg34232 -.names n1168 n1636 Pg34221 -0- 1 --0 1 -.names n1178 n1401 n1638 Pg34201 -1-- 1 --0- 1 ---0 1 -.names Ng4646 n1100 n1145 [4394] -11- 1 -1-1 1 -.names Pg33950 -.names Pg33949 -.names Pg33948 -.names Pg33947 -.names Pg33946 -.names Pg33945 -.names n1175 Pg33935 -0 1 -.names [4507] n1160 Ng4507 Pg33874 -1-- 1 --1- 1 ---0 1 -.names n1191 n1638 n6113 Pg33659 -1-- 1 --0- 1 ---0 1 -.names n1194 Pg33636 -0 1 -.names Pg17291 Ng1171 n1142 [4406] -10- 1 -1-1 1 -.names Ng2729 n5700 n5701 Pg33435 -01- 1 -1-1 1 --11 1 -.names Ng2729 n5698 n5699 Pg33079 -01- 1 -1-1 1 --11 1 -.names n3401 Pg32975 -0 1 -.names Pg32454 -.names Pg32429 -.names n2489 n2490 n2491 n2492 Pg32185 -1111 1 -.names n4553 Pg31863 -0 1 -.names n4321 Pg31862 -0 1 -.names n4527 Pg31860 -0 1 -.names n186 Pg31793 -0 1 -.names n6112 Pg31521 -0 1 -.names Ng2831 Pg30331 -0 1 -.names Ng2834 Pg30330 -0 1 -.names [4426] Pg30329 -0 1 -.names Ng37 Pg30327 -0 1 -.names n184 n185 Pg28042 -1- 1 --1 1 -.names n182 n5079 Pg28041 -1- 1 --0 1 -.names n180 n181 Pg28030 -1- 1 --1 1 -.names n177 Pg26877 -0 1 -.names n174 Pg26876 -0 1 -.names n171 Pg26875 -0 1 -.names n3401 Pg26801 -0 1 -.names Pg25590 -.names Pg25589 -.names Pg25588 -.names Pg25587 -.names Pg25586 -.names Pg25585 -.names Pg25584 -.names Pg25583 -.names Pg25582 -.names n4321 Pg25259 -0 1 -.names n4553 Pg25167 -0 1 -.names n4527 Pg25114 -0 1 -.names Pg24151 -.names Ng2831 Pg23759 -0 1 -.names Ng2834 Pg23652 -0 1 -.names [4426] Pg23612 -0 1 -.names Ng25 Ng22 Pg23190 -00 1 -.names Ng37 Pg23002 -0 1 -.names Pg35 Ng3003 Pg21727 -01 1 -.names Pg5 Pg12833 -0 1 -.names Pg35 n4887 n160 -0- 1 --1 1 -.names Ng1830 Ng2098 Ng1696 Ng1964 n172 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n1410 Pg35 n173 -11 1 -.names n172 n173 n171 -11 1 -.names Ng1710 Ng1858 Ng1844 Ng2126 Ng1992 Ng1978 Ng1724 Ng2112 n175 -1------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names n1243 Pg35 n176 -11 1 -.names n175 n176 n174 -11 1 -.names Ng1913 Ng2047 Ng1932 Ng1798 Ng1644 Ng2066 Ng1664 Ng1779 n178 -1------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names n1242 Pg35 n179 -11 1 -.names n178 n179 n177 -11 1 -.names n1134 n3911 n4366 n4567 n180 -010- 1 --100 1 -.names n1131 n1133 n1134 n3914 n181 -0-01 1 --001 1 -.names Pg35 n1411 n182 -0- 1 --1 1 -.names Pg35 Ng962 n184 -0- 1 --1 1 -.names Pg35 Ng1306 n185 -0- 1 --1 1 -.names n2567 n2564 n2565 n5591 n186 -11-- 1 -1-1- 1 -1--0 1 -.names Pg35 n2296 n2297 Ng5052 n188 -111- 1 --110 1 -.names n188 Ng33046 -0 1 -.names n1611 n1604 n1610 n1601 n189 -11-- 1 -1-1- 1 -1--1 1 -.names n189 Ng34441 -0 1 -.names n1267 n1884 n1885 n1883 n190 -011- 1 --111 1 -.names n190 Ng33982 -0 1 -.names Pg35 n1793 Ng2380 n191 -11- 1 --10 1 -.names n191 Ng34007 -0 1 -.names n3008 n3009 n160 n3007 n192 -111- 1 -11-1 1 -.names n192 Ng30405 -0 1 -.names n2980 n2981 n160 n2979 n193 -111- 1 -11-1 1 -.names n193 Ng30416 -0 1 -.names n2839 n2840 n160 n2838 n194 -111- 1 -11-1 1 -.names n194 Ng30466 -0 1 -.names Pg35 n1499 Ng2984 n195 -11- 1 --10 1 -.names n195 Ng34617 -0 1 -.names n1257 n1912 n1913 n1911 n196 -011- 1 --111 1 -.names n196 Ng33974 -0 1 -.names n160 n2732 n2733 n2731 n197 -111- 1 --111 1 -.names n197 Ng30505 -0 1 -.names n1898 n2163 Ng1772 Ng1802 n198 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n198 Ng33554 -0 1 -.names n2932 n2933 n160 n2333 n199 -111- 1 -11-1 1 -.names n199 Ng30432 -0 1 -.names Ng6215 Ng6219 n2248 n2250 n200 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n200 Ng33064 -0 1 -.names n1377 n1378 Ng807 n1371 n201 -111- 1 -11-1 1 -.names n201 Ng34881 -0 1 -.names Ng1061 n4245 n202 -01 1 -10 1 -.names n202 n5636 Ng24232 -1- 1 --0 1 -.names Ng4172 Ng4153 n206 -1- 1 --1 1 -.names n1284 n1285 n1286 n1287 n204 -1111 1 -.names n206 Pg35 Ng34733 -11 1 -.names Pg35 n2334 n2341 Ng3506 n207 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n207 Ng33026 -0 1 -.names n2547 n2548 Ng749 n2546 n208 -111- 1 -11-1 1 -.names n208 Ng31867 -0 1 -.names Pg17739 Pg14738 Pg12350 n212 -00- 1 -0-1 1 --11 1 -.names Pg35 Pg17646 Pg17607 Pg13068 n212 Ng24344 -10001 1 -.names n1271 n1940 n1941 n1939 n213 -011- 1 --111 1 -.names n213 Ng33966 -0 1 -.names n2180 n2181 n4770 Ng1714 n214 -110- 1 -11-0 1 -.names n214 Ng33550 -0 1 -.names n2351 Ng3155 Ng30393 -00 1 -.names n3702 n3703 Ng2165 n4956 n217 -110- 1 -11-0 1 -.names n217 Ng29248 -0 1 -.names Ng3689 n5150 n218 -0- 1 --1 1 -.names Pg35 Ng3694 n218 Ng24274 -01- 1 --11 1 -.names n1257 n1915 n1916 n1914 n219 -011- 1 --111 1 -.names n219 Ng33973 -0 1 -.names Pg35 Ng1964 n3113 n220 -1-1 1 --01 1 -.names n220 Ng30360 -0 1 -.names Ng4621 n1548 n1551 Ng4639 n221 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n221 Ng34460 -0 1 -.names n160 n2760 n2761 n2759 n222 -111- 1 --111 1 -.names n222 Ng30494 -0 1 -.names Pg35 n3056 Ng2652 n5842 n223 -11-0 1 --100 1 -.names n223 Ng30384 -0 1 -.names Pg17711 Pg14694 Pg12300 n227 -00- 1 -0-1 1 --11 1 -.names Pg35 Pg17604 Pg17580 Pg13049 n227 Ng24340 -10001 1 -.names n3809 n3810 Ng490 n5058 n228 -111- 1 -11-0 1 -.names n228 Ng29223 -0 1 -.names n1683 n1684 Ng772 n1682 n229 -111- 1 -11-1 1 -.names n229 Ng34252 -0 1 -.names n160 n2775 n2776 n2774 n230 -111- 1 --111 1 -.names n230 Ng30489 -0 1 -.names Ng6177 n3243 n3242 n5891 n231 -01-0 1 --110 1 -.names n231 Ng29301 -0 1 -.names Pg35 n2351 n2352 Ng3161 n232 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n232 Ng33022 -0 1 -.names n160 n2754 n2755 n2753 n233 -111- 1 --111 1 -.names n233 Ng30496 -0 1 -.names n1245 n2304 n2521 Ng4543 n234 -010- 1 -01-0 1 -.names n234 Ng33043 -0 1 -.names n3581 Ng3457 n3580 n5941 n235 -11-0 1 -1-10 1 -.names n235 Ng29263 -0 1 -.names n160 n2653 n2652 n6287 n236 -11-0 1 --110 1 -.names n236 Ng30533 -0 1 -.names n1260 n1762 n1763 n1761 n237 -011- 1 --111 1 -.names n237 Ng34015 -0 1 -.names n1729 n1726 n1727 Ng4801 n238 -11-- 1 -1-1- 1 -1--0 1 -.names n238 Ng34031 -0 1 -.names Pg35 n1582 n1583 Ng4584 n239 -111- 1 --110 1 -.names n239 Ng34452 -0 1 -.names Pg35 Ng6199 n240 -0- 1 --0 1 -.names n240 Ng34646 -0 1 -.names n1273 n1813 n1814 n1812 n241 -011- 1 --111 1 -.names n241 Ng34001 -0 1 -.names Pg35 Ng1379 n4140 n4141 n242 -1-11 1 --011 1 -.names n242 Ng25633 -0 1 -.names Pg35 n4222 Ng1579 n243 -11- 1 --10 1 -.names n243 Ng24259 -0 1 -.names Ng5176 Ng5180 n2287 n2289 n244 -00-- 1 --01- 1 -0--1 1 ---11 1 -.names n244 Ng33049 -0 1 -.names Pg35 n1512 Ng2890 n245 -11- 1 --10 1 -.names n245 Ng34609 -0 1 -.names Pg35 Ng1018 n2541 n2542 n246 -1-11 1 --011 1 -.names n246 Ng31869 -0 1 -.names n160 n2772 n2773 n2771 n247 -111- 1 --111 1 -.names n247 Ng30490 -0 1 -.names n2947 n2948 n160 n2946 n248 -111- 1 -11-1 1 -.names n248 Ng30427 -0 1 -.names n4210 Ng4264 n4268 Ng4258 n249 -1-1- 1 --01- 1 -1--0 1 --0-0 1 -.names n249 Ng21894 -0 1 -.names n1943 n1944 Ng767 n1942 n250 -111- 1 -11-1 1 -.names n250 Ng33965 -0 1 -.names Pg35 Ng5853 n251 -0- 1 --0 1 -.names n251 Ng34645 -0 1 -.names n1656 n1657 n1655 n1653 n252 -111- 1 -11-1 1 -.names n252 Ng34267 -0 1 -.names Pg35 Ng5507 n253 -0- 1 --0 1 -.names n253 Ng34644 -0 1 -.names n160 n2650 n2651 n2649 n254 -111- 1 --111 1 -.names n254 Ng30534 -0 1 -.names Pg35 n2225 n2226 Ng291 n255 -111- 1 --110 1 -.names n255 Ng33535 -0 1 -.names n160 n2271 n2748 n6318 n256 -1-10 1 --110 1 -.names n256 Ng30498 -0 1 -.names Pg35 n4184 Ng559 n257 -10- 1 --00 1 -.names n257 Ng25613 -0 1 -.names n1631 Ng608 n1629 n6203 n258 -11-0 1 -1-10 1 -.names n258 Ng34438 -0 1 -.names n2916 n2917 n160 n2915 n259 -111- 1 -11-1 1 -.names n259 Ng30439 -0 1 -.names n160 n2630 n2631 n2629 n260 -111- 1 --111 1 -.names n260 Ng30541 -0 1 -.names n160 n2258 n2690 n6299 n261 -1-10 1 --110 1 -.names n261 Ng30519 -0 1 -.names Ng921 n4165 n4168 Ng904 n262 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names n262 Ng25621 -0 1 -.names Pg35 n4673 n263 -0- 1 --0 1 -.names Ng4871 n263 Ng34036 -11 1 -.names n160 n2809 n2810 n2808 n264 -111- 1 --111 1 -.names n264 Ng30476 -0 1 -.names n2941 n2942 n160 n2940 n265 -111- 1 -11-1 1 -.names n265 Ng30429 -0 1 -.names n2428 n2433 n2434 Ng1926 n266 -111- 1 --110 1 -.names n266 Ng32997 -0 1 -.names Pg35 n2250 n2251 Ng6209 n267 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n267 Ng33063 -0 1 -.names n2956 n2957 n160 n2955 n268 -111- 1 -11-1 1 -.names n268 Ng30424 -0 1 -.names Pg35 n2484 n2485 Ng287 n269 -111- 1 --110 1 -.names n269 Ng32977 -0 1 -.names Pg35 n4676 n270 -0- 1 --0 1 -.names Ng4646 n270 Ng34026 -11 1 -.names n2968 n2969 n160 n2967 n271 -111- 1 -11-1 1 -.names n271 Ng30420 -0 1 -.names n1873 n2151 Ng1862 n272 -11- 1 --10 1 -.names n272 Ng33560 -0 1 -.names Pg35 n3800 n3801 Ng671 n273 -111- 1 --110 1 -.names n273 Ng29226 -0 1 -.names Ng843 n4248 n274 -01 1 -10 1 -.names Pg35 Ng837 n274 Ng25619 -01- 1 --11 1 -.names n1574 n1572 Ng4322 n4642 n275 -11-- 1 -1-0- 1 -1--0 1 -.names n275 Ng34455 -0 1 -.names Pg35 n1963 Ng6395 n6116 n276 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n276 Ng33625 -0 1 -.names n1416 n1417 Ng622 n1415 n277 -111- 1 -11-1 1 -.names n277 Ng34790 -0 1 -.names n2338 Ng3506 Ng30414 -00 1 -.names Pg35 Ng2834 n3043 n280 -1-1 1 --01 1 -.names n280 Ng30390 -0 1 -.names Ng246 Ng239 Ng232 Ng225 Ng269 Ng262 Ng255 n282 -0------ 1 --0----- 1 ---0---- 1 ----0--- 1 -----1-- 1 ------1- 1 -------1 1 -.names Ng246 Ng239 Ng232 Ng225 Ng269 Ng262 Ng255 n281 -0000111 1 -.names n282 Pg35 Ng278 n281 Ng25594 -111- 1 -11-1 1 -.names Ng4836 n263 Ng34034 -11 1 -.names Ng1036 n2210 Ng1030 n5590 n283 -01-- 1 -0-0- 1 --1-0 1 ---00 1 -.names n283 Ng33541 -0 1 -.names Pg35 n3452 n3819 Ng5272 n284 -111- 1 --110 1 -.names n284 Ng28093 -0 1 -.names n160 n3011 n3010 n6405 n285 -11-0 1 --110 1 -.names n285 Ng30404 -0 1 -.names n3239 n160 Ng6195 n3238 n286 -11-- 1 -1-11 1 -.names n286 Ng29303 -0 1 -.names Ng1135 n3996 n3997 n5090 n287 -111- 1 --110 1 -.names n287 Ng26917 -0 1 -.names n1970 n1971 n1969 Ng6395 n288 -111- 1 -11-0 1 -.names n288 Ng33624 -0 1 -.names n1372 n1371 Ng807 n289 -11- 1 -1-0 1 -.names n289 Ng34911 -0 1 -.names Pg35 Ng3853 n290 -0- 1 --0 1 -.names n290 Ng34627 -0 1 -.names n2374 n2379 n2380 Ng2485 n291 -111- 1 --110 1 -.names n291 Ng33013 -0 1 -.names n2475 n2476 Ng925 n2474 n292 -111- 1 -11-1 1 -.names n292 Ng32981 -0 1 -.names n160 n2793 n2794 n2792 n293 -111- 1 --111 1 -.names n293 Ng30483 -0 1 -.names Ng1798 n2439 n2443 n2444 n294 -0-11 1 --111 1 -.names n294 Ng32994 -0 1 -.names n1994 n3868 Ng4076 n3867 n295 -111- 1 -11-1 1 -.names n295 Ng28070 -0 1 -.names n2874 n2875 n160 n2320 n296 -111- 1 -11-1 1 -.names n296 Ng30453 -0 1 -.names n2219 n2220 Ng763 n2218 n297 -111- 1 -11-1 1 -.names n297 Ng33539 -0 1 -.names n160 n2674 n2675 n2673 n298 -111- 1 --111 1 -.names n298 Ng30526 -0 1 -.names Pg35 Ng4427 n3940 n299 -1-1 1 --01 1 -.names n299 Ng26951 -0 1 -.names Ng4864 n263 Ng34035 -11 1 -.names Pg35 n1464 Ng4717 n300 -11- 1 --10 1 -.names n300 Ng34636 -0 1 -.names n2482 Ng590 n2480 n6256 n301 -11-0 1 -1-10 1 -.names n301 Ng32978 -0 1 -.names Pg35 n3141 Ng1612 n5878 n302 -10-0 1 --000 1 -.names n302 Ng30348 -0 1 -.names Pg17674 Pg14662 Pg12238 n306 -00- 1 -0-1 1 --11 1 -.names Pg35 Pg17577 Pg17519 Pg13039 n306 Ng24336 -10001 1 -.names n3289 Ng6154 n3288 n5896 n307 -11-0 1 -1-10 1 -.names n307 Ng29298 -0 1 -.names n160 n2746 n2747 n2745 n308 -111- 1 --111 1 -.names n308 Ng30499 -0 1 -.names n1257 n1906 n1907 n4764 n309 -011- 1 --110 1 -.names n309 Ng33976 -0 1 -.names n3176 n3177 Ng744 n3175 n310 -111- 1 -11-1 1 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n325 -011- 1 --110 1 -.names n325 Ng33997 -0 1 -.names n1796 n2088 Ng2287 n326 -11- 1 --10 1 -.names n326 Ng33584 -0 1 -.names Ng4269 n4211 Ng4273 n4212 n327 -01-- 1 -0-0- 1 --1-1 1 ---01 1 -.names n327 Ng24280 -0 1 -.names Pg35 Ng1384 n3990 n6186 n328 -1-10 1 --010 1 -.names n328 Ng26920 -0 1 -.names Pg35 Ng5831 n3294 n329 -1-1 1 --01 1 -.names n329 Ng29296 -0 1 -.names Ng1171 n1211 Ng1183 Ng1193 n330 --1-0 1 -011- 1 -.names Pg7916 Ng1171 n331 -01 1 -10 1 -.names Pg35 n330 n331 Ng30338 -11- 1 -1-1 1 -.names Ng4264 n4209 Ng4269 n4267 n332 -01-- 1 -0-0- 1 --1-1 1 ---01 1 -.names n332 Ng21895 -0 1 -.names Pg35 n1703 n1704 Ng4818 n333 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n333 Ng34041 -0 1 -.names n160 n2757 n2758 n2756 n334 -111- 1 --111 1 -.names n334 Ng30495 -0 1 -.names Ng4864 Ng4878 Ng4836 Ng4871 n335 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names Pg35 n335 n5348 n5923 Ng29279 -11-0 1 -1-00 1 -.names Pg35 n4129 Ng3139 n338 -11- 1 --10 1 -.names n338 Ng25655 -0 1 -.names n160 n3014 n3013 n6406 n339 -11-0 1 --110 1 -.names n339 Ng30403 -0 1 -.names n1245 n1253 n2521 Ng4540 n340 -000- 1 -00-0 1 -.names n340 Ng33042 -0 1 -.names n2971 n2972 n160 n2970 n341 -111- 1 -11-1 1 -.names n341 Ng30419 -0 1 -.names Pg35 n3820 n3824 n3823 n342 -0-1- 1 --11- 1 ---11 1 -.names n342 Ng28090 -0 1 -.names Pg35 n1452 Ng4912 n343 -11- 1 --10 1 -.names n343 Ng34642 -0 1 -.names Pg35 Ng2255 n3089 n344 -1-1 1 --01 1 -.names n344 Ng30370 -0 1 -.names n1593 n1591 n1589 n1592 n345 -11-- 1 -1-1- 1 -1--1 1 -.names n345 Ng34448 -0 1 -.names Pg35 n3952 Ng4382 Ng4375 n346 --1-0 1 -110- 1 -.names n346 Ng26946 -0 1 -.names Pg35 n1510 Ng2844 n347 -11- 1 --10 1 -.names n347 Ng34610 -0 1 -.names n3812 n4259 Ng417 Ng446 n348 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n348 Ng24209 -0 1 -.names n160 n2735 n2736 n2734 n349 -111- 1 --111 1 -.names n349 Ng30504 -0 1 -.names Pg35 n4123 Ng3490 n350 -11- 1 --10 1 -.names n350 Ng25669 -0 1 -.names n2276 Ng5511 Ng30480 -00 1 -.names Pg35 n2338 n2339 Ng3512 n353 -11-- 1 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n2521 Ng4480 n368 -010- 1 -01-0 1 -.names n368 Ng33036 -0 1 -.names Pg35 Pg8719 Ng358 Ng25595 -100 1 -.names Pg35 Ng3171 n2344 n2347 n371 -1-1- 1 --01- 1 -1--1 1 --0-1 1 -.names n371 Ng33024 -0 1 -.names n1898 n2172 Ng1728 n372 -11- 1 --10 1 -.names n372 Ng33552 -0 1 -.names Pg35 n1767 Ng2514 n373 -11- 1 --10 1 -.names n373 Ng34014 -0 1 -.names Pg35 Ng3831 n3479 n374 -1-1 1 --01 1 -.names n374 Ng29273 -0 1 -.names Pg35 Ng4917 n375 -0- 1 --0 1 -.names n375 Ng34638 -0 1 -.names Pg35 n330 Ng1199 n5341 n376 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n376 Ng30341 -0 1 -.names Pg35 n4036 n4037 Ng832 n377 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n377 Ng26899 -0 1 -.names n3173 n3174 Ng914 n3172 n378 -111- 1 -11-1 1 -.names n378 Ng30336 -0 1 -.names Ng1008 n2207 n3160 n6043 n380 -11-0 1 --110 1 -.names n2207 n4323 n379 -0- 1 --1 1 -.names Pg35 n380 Ng969 n379 Ng25622 -11-- 1 -1-11 1 -.names n1596 n1591 n1594 n1595 n381 -11-- 1 -1-1- 1 -1--1 1 -.names n381 Ng34447 -0 1 -.names n2003 n2004 n2002 Ng4054 n382 -111- 1 -11-0 1 -.names n382 Ng33613 -0 1 -.names Pg35 n4073 Ng6187 n383 -11- 1 --10 1 -.names n383 Ng25749 -0 1 -.names Pg35 Ng5073 Ng5069 Ng25704 -01- 1 --11 1 -.names Pg35 n2276 n2277 Ng5517 n384 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n384 Ng33053 -0 1 -.names n160 n2592 n2593 n2591 n385 -111- 1 --111 1 -.names n385 Ng30555 -0 1 -.names n1925 n1923 Ng1682 n386 -11- 1 -1-0 1 -.names n386 Ng33971 -0 1 -.names Ng1105 n4003 n5092 n6435 n387 -11-0 1 --100 1 -.names n387 Ng26915 -0 1 -.names n160 n2638 n2639 n2637 n388 -111- 1 --111 1 -.names n388 Ng30538 -0 1 -.names Pg35 n3092 Ng2250 n5857 n389 -11-0 1 --100 1 -.names n389 Ng30369 -0 1 -.names n1599 n1591 n1597 n1598 n390 -11-- 1 -1-1- 1 -1--1 1 -.names n390 Ng34446 -0 1 -.names n3782 n3783 Ng911 n4823 n391 -111- 1 -11-0 1 -.names n391 Ng29230 -0 1 -.names n1257 n1909 n1910 n1908 n392 -011- 1 --111 1 -.names n392 Ng33975 -0 1 -.names n160 n2751 n2752 n2750 n393 -111- 1 --111 1 -.names n393 Ng30497 -0 1 -.names n2974 n2975 n160 n2973 n394 -111- 1 -11-1 1 -.names n394 Ng30418 -0 1 -.names Pg35 n4085 Ng5495 n395 -11- 1 --10 1 -.names n395 Ng25721 -0 1 -.names Pg35 n1489 Ng2950 n396 -11- 1 --10 1 -.names n396 Ng34622 -0 1 -.names n2919 n2920 n160 n2918 n397 -111- 1 -11-1 1 -.names n397 Ng30438 -0 1 -.names n160 n2245 n2632 n2633 n398 -1-11 1 --111 1 -.names n398 Ng30540 -0 1 -.names Pg35 Ng1367 n2466 n2467 n399 -1-11 1 --011 1 -.names n399 Ng32986 -0 1 -.names Pg35 n1952 n1953 Ng153 n400 -111- 1 --110 1 -.names n400 Ng33960 -0 1 -.names n1609 n1604 n1608 n1598 n401 -11-- 1 -1-1- 1 -1--1 1 -.names n401 Ng34442 -0 1 -.names n2965 n2966 n160 n2964 n402 -111- 1 -11-1 1 -.names n402 Ng30421 -0 1 -.names Pg35 n2120 Ng2108 n403 -11- 1 --10 1 -.names n403 Ng33573 -0 1 -.names Pg35 n4263 Ng437 n404 -11- 1 --10 1 -.names n404 Ng24205 -0 1 -.names n2478 n2479 Ng758 n2477 n405 -111- 1 -11-1 1 -.names n405 Ng32979 -0 1 -.names Pg35 n4067 Ng6533 n406 -11- 1 --10 1 -.names n406 Ng25763 -0 1 -.names n160 n2799 n2800 n2798 n407 -111- 1 --111 1 -.names n407 Ng30481 -0 1 -.names n160 n2696 n2695 n6301 n408 -11-0 1 --110 1 -.names n408 Ng30517 -0 1 -.names n160 n2635 n2636 n2634 n409 -111- 1 --111 1 -.names n409 Ng30539 -0 1 -.names n1380 n1381 Ng632 n1379 n410 -111- 1 -11-1 1 -.names n410 Ng34880 -0 1 -.names n2925 n2926 n160 n2924 n411 -111- 1 -11-1 1 -.names n411 Ng30436 -0 1 -.names Ng1664 n2452 n2456 n2457 n412 -0-11 1 --111 1 -.names n412 Ng32990 -0 1 -.names Pg35 [4421] n4235 n413 -1-1 1 --01 1 -.names n413 Ng24245 -0 1 -.names n160 n2598 n2599 n2597 n414 -111- 1 --111 1 -.names n414 Ng30553 -0 1 -.names Pg35 n4023 Ng269 n415 -11- 1 --10 1 -.names n415 Ng26907 -0 1 -.names Ng4040 n5149 n416 -0- 1 --1 1 -.names Pg35 Ng4045 n416 Ng24278 -01- 1 --11 1 -.names Pg35 n3933 Ng4382 Ng4438 n417 --1-0 1 -110- 1 -.names n417 Ng26955 -0 1 -.names Pg35 [4437] Ng29277 n418 -1-0 1 --00 1 -.names n418 Ng29276 -0 1 -.names Ng4681 Ng4688 Ng4674 Ng4646 n419 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names Pg35 n419 n5350 n5925 Ng29277 -11-0 1 -1-00 1 -.names Pg35 n1994 n2527 n2526 n422 -011- 1 --111 1 -.names n422 Ng31894 -0 1 -.names n1245 n2312 n2521 Ng4495 n423 -010- 1 -01-0 1 -.names n423 Ng33037 -0 1 -.names Pg35 n1579 n1584 Ng4332 n424 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n424 Ng34451 -0 1 -.names Pg35 n1689 n1690 Ng298 n425 -111- 1 --110 1 -.names n425 Ng34250 -0 1 -.names Ng5831 n3296 n3295 n5900 n426 -01-0 1 --110 1 -.names n426 Ng29295 -0 1 -.names Pg35 n4027 Ng262 n427 -11- 1 --10 1 -.names n427 Ng26905 -0 1 -.names Pg35 Ng1024 n2472 n2473 n428 -1-11 1 --011 1 -.names n428 Ng32983 -0 1 -.names n3017 n3018 n160 n3016 n429 -111- 1 -11-1 1 -.names n429 Ng30402 -0 1 -.names n1823 n1821 Ng2241 n430 -11- 1 -1-0 1 -.names n430 Ng33999 -0 1 -.names n4220 n4221 Ng1564 n5130 n431 -111- 1 -11-0 1 -.names n431 Ng24262 -0 1 -.names n160 n2583 n2584 n2582 n432 -111- 1 --111 1 -.names n432 Ng30558 -0 1 -.names Pg35 n4035 Ng872 n433 -11- 1 --10 1 -.names n433 Ng26901 -0 1 -.names n1248 n2312 n2521 Ng4501 n434 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Ng26922 -0 1 -.names n3685 n3686 Ng2299 n4953 n447 -110- 1 -11-0 1 -.names n447 Ng29250 -0 1 -.names n2289 Ng5164 Ng30459 -00 1 -.names Pg35 n2228 n2229 Ng150 n450 -111- 1 --110 1 -.names n450 Ng33534 -0 1 -.names n2237 Ng6549 Ng30543 -00 1 -.names Pg35 n3473 n3474 Ng4076 n453 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n453 Ng29275 -0 1 -.names Pg35 n1731 n1732 Ng4793 n454 -111- 1 --110 1 -.names n454 Ng34030 -0 1 -.names n2880 n2881 n160 n2879 n455 -111- 1 -11-1 1 -.names n455 Ng30451 -0 1 -.names n160 n2601 n2602 n2600 n456 -111- 1 --111 1 -.names n456 Ng30552 -0 1 -.names Pg35 Ng1002 n3170 n3171 n457 -1-11 1 --011 1 -.names n457 Ng30337 -0 1 -.names Pg35 n854 n1218 n5152 n461 -1--0 1 -100- 1 -.names Pg17423 Pg17404 Pg17320 n461 Ng24254 -0001 1 -.names Pg35 n3071 Ng2441 n5848 n462 -11-0 1 --100 1 -.names n462 Ng30378 -0 1 -.names Pg35 n1736 n2358 n2357 n463 -011- 1 --111 1 -.names n463 Ng33019 -0 1 -.names Pg35 n1972 Ng6049 n6118 n464 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n464 Ng33623 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1 --111 1 -.names n556 Ng30523 -0 1 -.names n557 Ng1146 Ng1152 n559 -01- 1 --10 1 -.names Pg13259 Ng1171 Ng1183 n557 -100 1 -.names Pg35 n559 n557 Ng1099 Ng24233 -11-- 1 -1-10 1 -.names Ng2625 n2359 n2363 n2364 n560 -0-11 1 --111 1 -.names n560 Ng33018 -0 1 -.names Pg35 n2487 n2488 Ng164 n561 -111- 1 --110 1 -.names n561 Ng32976 -0 1 -.names Pg35 n3140 Ng1691 n5877 n562 -11-0 1 --100 1 -.names n562 Ng30349 -0 1 -.names Pg35 n2233 n2240 Ng6549 n563 -11-- 1 -1-1- 1 --1-0 1 ---10 1 -.names n563 Ng33067 -0 1 -.names [4431] Pg35 Ng26900 -11 1 -.names Pg35 Ng3873 n2318 n2321 n564 -1-1- 1 --01- 1 -1--1 1 --0-1 1 -.names n564 Ng33034 -0 1 -.names n160 n2604 n2605 n2603 n565 -111- 1 --111 1 -.names n565 Ng30551 -0 1 -.names n4126 n4127 n4928 Ng3470 n566 -110- 1 -11-0 1 -.names n566 Ng25667 -0 1 -.names n2877 n2878 n160 n2876 n567 -111- 1 -11-1 1 -.names n567 Ng30452 -0 1 -.names n4180 n4190 Ng518 Ng513 n568 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n568 Ng25612 -0 1 -.names Ng538 Ng209 n571 -1- 1 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n4431 n4442 Ng4245 Ng2145 n1306 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n4416 n4444 Ng4157 Ng2704 n1307 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n5557 n4394 n5556 n5553 n1308 -11-- 1 -1-11 1 -.names n1294 n1323 Ng2965 Ng2960 n1312 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names [4433] n1281 n4406 Ng2873 n1313 -0-1- 1 --11- 1 -0--0 1 --1-0 1 -.names Ng48 n4402 n4407 n1310 -0-- 1 --1- 1 ---1 1 -.names n1312 n1313 n1310 Ng2878 n1309 -111- 1 -11-0 1 -.names n4428 Ng2689 n4444 Ng952 n1314 -10-- 1 -1-1- 1 --0-1 1 ---11 1 -.names n4416 Ng4176 Ng2130 n4442 n1315 -1-0- 1 --00- 1 -1--1 1 --0-1 1 -.names n4426 n4431 Ng4253 Ng1296 n1316 -11-- 1 -1-0- 1 --1-1 1 ---01 1 -.names n5548 n4394 n5547 n5544 n1317 -11-- 1 -1-11 1 -.names Ng582 n4419 n4421 Ng546 n1320 -0-1- 1 --11- 1 -0--0 1 --1-0 1 -.names n1250 n1331 Ng622 n5564 n1321 -01-1 1 -0-01 1 -.names n1289 n1320 n1321 Ng767 n1318 -111- 1 --110 1 -.names n1310 n1351 Ng2864 Ng2860 n1325 -11-- 1 --10- 1 -1--0 1 ---00 1 -.names n1294 n4406 Ng2922 Ng2994 n1326 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1 ---0 1 -.names n1564 n1569 Ng4608 n1577 -0-- 1 --1- 1 ---1 1 -.names Ng4601 n4300 n1578 -01 1 -10 1 -.names Pg35 n1564 n1579 -0- 1 --0 1 -.names n1579 Ng4593 n4640 n1582 -1-- 1 --0- 1 ---1 1 -.names n1564 Ng4593 n4640 n1583 -0-- 1 --1- 1 ---0 1 -.names n4301 Ng4584 n1584 -11 1 -00 1 -.names Ng4322 n4641 n4642 n1587 -0-- 1 --1- 1 ---1 1 -.names n1572 Ng4322 n4642 n1588 -1-- 1 --1- 1 ---0 1 -.names Pg35 Ng2827 n4794 n1589 -0-0 1 --10 1 -.names Pg35 n1592 Ng2819 n5717 n1593 -0--1 1 --0-1 1 ---01 1 -.names n1221 Ng111 n1591 -11 1 -.names n1255 Ng2724 Ng2729 n1592 -1-- 1 --0- 1 ---0 1 -.names Pg35 Ng2811 n4794 n1594 -0-0 1 --10 1 -.names Pg35 n1595 Ng2807 n5719 n1596 -0--1 1 --0-1 1 ---01 1 -.names n1255 Ng2724 Ng2729 n1595 -1-- 1 --0- 1 ---1 1 -.names Pg35 Ng2823 n4794 n1597 -0-0 1 --10 1 -.names Pg35 n1598 Ng2815 n5721 n1599 -0--1 1 --0-1 1 ---01 1 -.names n1255 Ng2724 Ng2729 n1598 -1-- 1 --1- 1 ---0 1 -.names Pg35 Ng2799 n4794 n1600 -0-0 1 --10 1 -.names Pg35 n1601 Ng2803 n5723 n1602 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n1779 -1- 1 --0 1 -.names Pg35 Ng2445 n4713 n1780 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng2445 n1782 -1- 1 --0 1 -.names Pg35 n1781 Ng2441 n1783 -0-- 1 --0- 1 ---0 1 -.names Ng2495 n4714 n1781 -0- 1 --1 1 -.names Pg35 Ng2429 n1785 -1- 1 --0 1 -.names Pg35 n1784 Ng2437 n1786 -0-- 1 --0- 1 ---0 1 -.names Ng2465 Ng2495 n4710 n1784 -0-- 1 --1- 1 ---0 1 -.names Pg35 Ng2433 n1788 -1- 1 --0 1 -.names Pg35 n1787 Ng2429 n1789 -0-- 1 --0- 1 ---0 1 -.names Ng2465 n4714 n1787 -1- 1 --1 1 -.names Ng2689 Ng2697 Ng2704 n1791 -0-- 1 --1- 1 ---0 1 -.names n1273 n4717 n4719 Ng2299 n1793 -0-0- 1 --10- 1 -0--0 1 --1-0 1 -.names n1203 n1274 Ng1589 n1794 -00- 1 -0-1 1 -.names Pg35 Ng2361 n5263 n1798 -00- 1 -1-0 1 --00 1 -.names Pg35 n4720 n1796 -0- 1 --1 1 -.names Pg35 Ng2303 n1801 -1- 1 --0 1 -.names n4311 n4720 n1800 -1- 1 --0 1 -.names Pg35 Ng2315 n1804 -1- 1 --0 1 -.names Pg35 Ng2311 n4723 n1805 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng2311 n1807 -1- 1 --0 1 -.names Pg35 n1806 Ng2307 n1808 -0-- 1 --0- 1 ---0 1 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n4720 n2079 -11- 1 -1-0 1 -.names Pg35 n2080 n4724 n2084 -0-- 1 --1- 1 ---1 1 -.names Pg35 Ng2338 n2085 -1- 1 --0 1 -.names Ng2331 n4720 Ng2287 n2086 -1-0 1 --00 1 -.names Pg35 n2080 n2086 Ng2361 n2088 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names Pg35 n1096 n1644 n2027 n2089 -0--1 1 --101 1 -.names Pg35 Ng2153 n2093 -1- 1 --0 1 -.names Pg35 Ng2269 n2096 -1- 1 --0 1 -.names Pg35 n4727 Ng2273 n2097 -0-- 1 --1- 1 ---1 1 -.names Ng2269 n4727 n4729 n5307 n2099 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names n1644 n4796 n2101 -01 1 -.names Pg35 n2101 n4730 n2100 -11- 1 -1-0 1 -.names Pg35 n2101 n4730 Ng2153 n2105 -0--- 1 --1-- 1 ---0- 1 ----0 1 -.names Pg35 Ng2204 n2106 -1- 1 --0 1 -.names Ng2197 n4730 Ng2153 n2107 -1-0 1 --00 1 -.names Pg35 n2101 n2107 Ng2227 n2109 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names Pg35 n1155 n1640 n2027 n2110 -0--1 1 --101 1 -.names Pg35 Ng1996 n2114 -1- 1 --0 1 -.names Pg35 Ng2112 n2117 -1- 1 --0 1 -.names Pg35 n4738 Ng2116 n2118 -0-- 1 --1- 1 ---1 1 -.names Ng2112 n4738 n4740 n5311 n2120 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names n1640 n4796 n2122 -01 1 -.names Pg35 n2122 n4741 n2121 -11- 1 -1-0 1 -.names Pg35 n2122 n4741 Ng1996 n2126 -0--- 1 --1-- 1 ---0- 1 ----0 1 -.names Pg35 Ng2047 n2127 -1- 1 --0 1 -.names Ng2040 n4741 Ng1996 n2128 -1-0 1 --00 1 -.names Pg35 n2122 n2128 Ng2070 n2130 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names Pg35 n1113 n1645 n2027 n2131 -0--1 1 --101 1 -.names Pg35 Ng1862 n2135 -1- 1 --0 1 -.names Pg35 Ng1978 n2138 -1- 1 --0 1 -.names Pg35 n4748 Ng1982 n2139 -0-- 1 --1- 1 ---1 1 -.names Ng1978 n4748 n4750 n5315 n2141 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names n1645 n4796 n2143 -01 1 -.names Pg35 n2143 n4751 n2142 -11- 1 -1-0 1 -.names Pg35 n2143 n4751 Ng1862 n2147 -0--- 1 --1-- 1 ---0- 1 ----0 1 -.names Pg35 Ng1913 n2148 -1- 1 --0 1 -.names Ng1906 n4751 Ng1862 n2149 -1-0 1 --00 1 -.names Pg35 n2143 n2149 Ng1936 n2151 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names Pg35 n1120 n1639 n2027 n2152 -0--1 1 --101 1 -.names Pg35 Ng1728 n2156 -1- 1 --0 1 -.names Pg35 Ng1844 n2159 -1- 1 --0 1 -.names Pg35 n4758 Ng1848 n2160 -0-- 1 --1- 1 ---1 1 -.names Ng1844 n4758 n4760 n5319 n2162 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names n1639 n4796 n2164 -01 1 -.names Pg35 n2164 n4761 n2163 -11- 1 -1-0 1 -.names Pg35 n2164 n4765 n2168 -0-- 1 --1- 1 ---1 1 -.names Pg35 Ng1779 n2169 -1- 1 --0 1 -.names Ng1772 n4761 Ng1728 n2170 -1-0 1 --00 1 -.names Pg35 n2164 n2170 Ng1802 n2172 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names Pg35 [4406] n1641 n2027 n2173 -0--1 1 --101 1 -.names Pg35 Ng1592 n2177 -1- 1 --0 1 -.names Pg35 Ng1710 n2180 -1- 1 --0 1 -.names Pg35 n4768 Ng1714 n2181 -0-- 1 --1- 1 ---1 1 -.names Ng1710 n4768 n4770 n5323 n2183 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names n1923 Ng1668 n4773 n5588 n2185 -1-1- 1 --01- 1 -1--1 1 --0-1 1 -.names Pg35 n4774 n5588 n2186 -0-- 1 --1- 1 ---1 1 -.names Pg35 Ng1644 n2187 -1- 1 --0 1 -.names Ng1636 Ng1592 n4771 n2188 -10- 1 --00 1 -.names Pg35 n2188 Ng1668 n5588 n2191 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names Ng1333 Ng1322 n2194 -1- 1 --1 1 -.names n2194 Ng1345 n4805 n2192 -11- 1 -1-0 1 -.names n2192 Ng1361 n4805 n2195 -11- 1 -1-0 1 -.names n2195 Ng1367 n4805 n2196 -11- 1 -1-0 1 -.names Pg35 n2196 Ng1379 n4805 n2197 -10-- 1 -1-1- 1 -1--0 1 -.names Ng1274 n666 n4222 n2203 -0-- 1 --1- 1 ---1 1 -.names Pg35 Ng1270 n2204 -1- 1 --0 1 -.names Ng990 Ng979 n2207 -1- 1 --1 1 -.names n2207 Ng1002 n4818 n2205 -11- 1 -1-0 1 -.names n2205 Ng1018 n4818 n2208 -11- 1 -1-0 1 -.names n2208 Ng1024 n4818 n2209 -11- 1 -1-0 1 -.names Pg35 n2209 Ng1036 n4818 n2210 -10-- 1 -1-1- 1 -1--0 1 -.names Ng930 n670 n4235 n2216 -0-- 1 --1- 1 ---1 1 -.names Pg35 Ng925 n2217 -1- 1 --0 1 -.names Ng763 n2218 n3791 n2219 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng758 n2220 -1- 1 --0 1 -.names Ng758 n2477 n2218 -0- 1 --1 1 -.names Pg35 Ng590 n2223 -1- 1 --0 1 -.names Ng590 n2480 n2221 -0- 1 --1 1 -.names Ng294 n4661 n2225 -1- 1 --1 1 -.names n3904 Ng294 n4661 n2226 -1-- 1 --0- 1 ---0 1 -.names Ng153 n4670 n2228 -1- 1 --1 1 -.names n3182 Ng153 n4670 n2229 -1-- 1 --0- 1 ---0 1 -.names Ng6561 n4833 n2232 -0- 1 --1 1 -.names n2232 Ng6561 Ng6565 Ng25756 n2230 -1--0 1 -111- 1 -.names n4110 n4832 n2233 -11 1 -.names Pg35 Ng6565 n2233 n2235 -11- 1 -1-1 1 -.names Pg35 Ng6561 n2233 n2237 -0-- 1 --1- 1 ---1 1 -.names Ng6555 Ng6549 n2238 -0- 1 --0 1 -.names Ng6555 Ng6549 n2242 -1- 1 --0 1 -.names Ng6555 Ng6549 n2241 -0- 1 --1 1 -.names Pg35 n2242 n2241 n2240 -01- 1 --11 1 -.names Ng6215 n4836 n2245 -0- 1 --1 1 -.names Pg35 Ng6227 n2244 -0- 1 --0 1 -.names n2245 n2244 Ng6215 Ng6219 n2243 -11-- 1 -1-11 1 -.names n4582 n4835 n2246 -11 1 -.names Pg35 Ng6219 n2246 n2248 -11- 1 -1-1 1 -.names Pg35 Ng6215 n2246 n2250 -0-- 1 --1- 1 ---1 1 -.names Ng6203 Ng6209 n2251 -0- 1 --0 1 -.names Ng6203 Ng6209 n2255 -0- 1 --1 1 -.names Ng6203 Ng6209 n2254 -1- 1 --0 1 -.names Pg35 n2255 n2254 n2253 -01- 1 --11 1 -.names Ng5869 n4837 n2258 -0- 1 --1 1 -.names n2258 Ng5869 Ng5873 Ng25728 n2256 -1--0 1 -111- 1 -.names n4582 n4832 n2259 -11 1 -.names Pg35 Ng5873 n2259 n2261 -11- 1 -1-1 1 -.names Pg35 Ng5869 n2259 n2263 -0-- 1 --1- 1 ---1 1 -.names Ng5863 Ng5857 n2264 -0- 1 --0 1 -.names Ng5863 Ng5857 n2268 -1- 1 --0 1 -.names Ng5863 Ng5857 n2267 -0- 1 --1 1 -.names Pg35 n2268 n2267 n2266 -01- 1 --11 1 -.names Ng5523 n4838 n2271 -0- 1 --1 1 -.names Pg35 Ng5535 n2270 -0- 1 --0 1 -.names n2271 n2270 Ng5523 Ng5527 n2269 -11-- 1 -1-11 1 -.names n1633 n4835 n2272 -01 1 -.names Pg35 Ng5527 n2272 n2274 -11- 1 -1-1 1 -.names Pg35 Ng5523 n2272 n2276 -0-- 1 --1- 1 ---1 1 -.names Ng5517 Ng5511 n2277 -0- 1 --0 1 -.names Ng5517 Ng5511 n2281 -1- 1 --0 1 -.names Ng5517 Ng5511 n2280 -0- 1 --1 1 -.names Pg35 n2281 n2280 n2279 -01- 1 --11 1 -.names Ng5176 n4839 n2284 -0- 1 --1 1 -.names Pg35 Ng5188 n2283 -0- 1 --0 1 -.names n2284 n2283 Ng5176 Ng5180 n2282 -11-- 1 -1-11 1 -.names n1633 n4832 n2285 -01 1 -.names Pg35 Ng5180 n2285 n2287 -11- 1 -1-1 1 -.names Pg35 Ng5176 n2285 n2289 -0-- 1 --1- 1 ---1 1 -.names Ng5170 Ng5164 n2290 -0- 1 --0 1 -.names Ng5170 Ng5164 n2294 -1- 1 --0 1 -.names Ng5170 Ng5164 n2293 -0- 1 --1 1 -.names Pg35 n2294 n2293 n2292 -01- 1 --11 1 -.names Pg35 Ng5057 n5795 n2296 -0-- 1 --1- 1 ---1 1 -.names n2509 Ng5057 n5795 n2297 -1-- 1 --0- 1 ---0 1 -.names n1222 n2521 Ng4549 n2302 -00- 1 -0-0 1 --10 1 -.names n1253 n2302 n2301 -01 1 -.names n2521 Ng4575 n2304 -1- 1 --0 1 -.names n1222 n2521 Ng4504 n2309 -00- 1 -0-0 1 --10 1 -.names n2521 Ng4572 n2310 -1- 1 --0 1 -.names n2309 n2310 n2308 -11 1 -.names [4437] n2521 n2312 -0- 1 --1 1 -.names Pg35 Ng4108 n2316 n5799 n2317 -0--1 1 --0-1 1 ---01 1 -.names Ng4098 n4791 n2316 -0- 1 --1 1 -.names Ng3869 n4855 n2320 -0- 1 --1 1 -.names Pg35 Ng3881 n2319 -0- 1 --0 1 -.names n2320 n2319 Ng3869 Ng3873 n2318 -11-- 1 -1-11 1 -.names n4585 n4835 n2321 -11 1 -.names Pg35 Ng3873 n2321 n2323 -11- 1 -1-1 1 -.names Pg35 Ng3869 n2321 n2325 -0-- 1 --1- 1 ---1 1 -.names Ng3857 Ng3863 n2326 -0- 1 --0 1 -.names Ng3857 Ng3863 n2330 -0- 1 --1 1 -.names Ng3857 Ng3863 n2329 -1- 1 --0 1 -.names Pg35 n2330 n2329 n2328 -01- 1 --11 1 -.names Ng3518 n4856 n2333 -0- 1 --1 1 -.names Pg35 Ng3530 n2332 -0- 1 --0 1 -.names n2333 n2332 Ng3518 Ng3522 n2331 -11-- 1 -1-11 1 -.names n4585 n4832 n2334 -11 1 -.names Pg35 Ng3522 n2334 n2336 -11- 1 -1-1 1 -.names Pg35 Ng3518 n2334 n2338 -0-- 1 --1- 1 ---1 1 -.names Ng3512 Ng3506 n2339 -0- 1 --0 1 -.names Ng3512 Ng3506 n2343 -1- 1 --0 1 -.names Ng3512 Ng3506 n2342 -0- 1 --1 1 -.names Pg35 n2343 n2342 n2341 -01- 1 --11 1 -.names Ng3167 n4857 n2346 -0- 1 --1 1 -.names Pg35 Ng3179 n2345 -0- 1 --0 1 -.names n2346 n2345 Ng3167 Ng3171 n2344 -11-- 1 -1-11 1 -.names n4110 n4835 n2347 -11 1 -.names Pg35 Ng3171 n2347 n2349 -11- 1 -1-1 1 -.names Pg35 Ng3167 n2347 n2351 -0-- 1 --1- 1 ---1 1 -.names Ng3161 Ng3155 n2352 -0- 1 --0 1 -.names Ng3161 Ng3155 n2356 -1- 1 --0 1 -.names Ng3161 Ng3155 n2355 -0- 1 --1 1 -.names Pg35 n2356 n2355 n2354 -01- 1 --11 1 -.names Pg35 Ng2748 n2358 -1- 1 --0 1 -.names n4692 Ng2756 n2357 -01 1 -10 1 -.names Pg35 n1153 n2361 -0- 1 --1 1 -.names Pg35 n1698 n2027 n2361 n2359 -0-11 1 --011 1 -.names n1153 n1698 n4324 n4794 n2363 -0--- 1 --1-- 1 ---1- 1 ----0 1 -.names Pg35 Ng2610 n2364 -1- 1 --0 1 -.names n1698 n4859 n4860 n2366 -1-- 1 --0- 1 ---1 1 -.names Pg35 Ng2625 Ng2610 n4860 n2367 -1-0- 1 --00- 1 -1--1 1 --0-1 1 -.names n2361 Ng2610 Ng2587 n2369 -00- 1 -1-0 1 --00 1 -.names n2369 n2366 n2368 -11 1 -.names Ng2619 n4860 n4947 n2370 -1-- 1 --1- 1 ---0 1 -.names Pg35 n2361 Ng2587 Ng2595 n2371 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names Pg35 n1151 n2374 -0- 1 --1 1 -.names Pg35 n1695 n2027 n2374 n2372 -0-11 1 --011 1 -.names n1151 n1695 n4326 n4794 n2376 -0--- 1 --1-- 1 ---1- 1 ----0 1 -.names Pg35 Ng2476 n2377 -1- 1 --0 1 -.names n1695 n4859 n4864 n2379 -1-- 1 --0- 1 ---1 1 -.names Pg35 Ng2491 Ng2476 n4864 n2380 -1-0- 1 --00- 1 -1--1 1 --0-1 1 -.names n2374 Ng2476 Ng2453 n2382 -00- 1 -1-0 1 --00 1 -.names n2382 n2379 n2381 -11 1 -.names Pg35 Ng2453 n4948 n2384 -0-- 1 --0- 1 ---1 1 -.names n2379 Ng2485 Ng2476 n4864 n2385 -11-- 1 -1-1- 1 -1--1 1 -.names Pg35 n1162 n2388 -0- 1 --1 1 -.names Pg35 n1697 n2027 n2388 n2386 -0-11 1 --011 1 -.names n1162 n1697 n4328 n4794 n2390 -0--- 1 --1-- 1 ---1- 1 ----0 1 -.names Pg35 Ng2342 n2391 -1- 1 --0 1 -.names n1697 n4859 n4866 n2393 -1-- 1 --0- 1 ---1 1 -.names Pg35 Ng2357 Ng2342 n4866 n2394 -1-0- 1 --00- 1 -1--1 1 --0-1 1 -.names n2388 Ng2342 Ng2319 n2396 -00- 1 -1-0 1 --00 1 -.names n2396 n2393 n2395 -11 1 -.names Ng2351 n4866 n4954 n2397 -1-- 1 --1- 1 ---0 1 -.names Pg35 n2388 Ng2319 Ng2327 n2398 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names Pg35 n1104 n2401 -0- 1 --1 1 -.names Pg35 n1699 n2027 n2401 n2399 -0-11 1 --011 1 -.names n1104 n1699 n4330 n4794 n2403 -0--- 1 --1-- 1 ---1- 1 ----0 1 -.names Pg35 Ng2208 n2404 -1- 1 --0 1 -.names n1699 n4859 n4870 n2406 -1-- 1 --0- 1 ---1 1 -.names Pg35 Ng2223 Ng2208 n4870 n2407 -1-0- 1 --00- 1 -1--1 1 --0-1 1 -.names n2401 Ng2208 Ng2185 n2409 -00- 1 -1-0 1 --00 1 -.names n2409 n2406 n2408 -11 1 -.names Ng2217 n4870 n4957 n2410 -1-- 1 --1- 1 ---0 1 -.names Pg35 n2401 Ng2185 Ng2193 n2411 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names Pg35 n1146 n2414 -0- 1 --1 1 -.names Pg35 n1701 n2027 n2414 n2412 -0-11 1 --011 1 -.names n1146 n1701 n4332 n4794 n2416 -0--- 1 --1-- 1 ---1- 1 ----0 1 -.names Pg35 Ng2051 n2417 -1- 1 --0 1 -.names n1701 n4859 n4873 n2419 -1-- 1 --0- 1 ---1 1 -.names Pg35 Ng2066 Ng2051 n4873 n2420 -1-0- 1 --00- 1 -1--1 1 --0-1 1 -.names n2414 Ng2051 Ng2028 n2422 -00- 1 -1-0 1 --00 1 -.names n2422 n2419 n2421 -11 1 -.names Pg35 Ng2028 n4958 n2424 -0-- 1 --0- 1 ---1 1 -.names n2419 Ng2051 Ng2060 n4873 n2425 -11-- 1 -1-1- 1 -1--1 1 -.names Pg35 n1126 n2428 -0- 1 --1 1 -.names Pg35 n1700 n2027 n2428 n2426 -0-11 1 --011 1 -.names n1126 n1700 n4334 n4794 n2430 -0--- 1 --1-- 1 ---1- 1 ----0 1 -.names Pg35 Ng1917 n2431 -1- 1 --0 1 -.names n1700 n4859 n4875 n2433 -1-- 1 --0- 1 ---1 1 -.names Pg35 Ng1932 Ng1917 n4875 n2434 -1-0- 1 --00- 1 -1--1 1 --0-1 1 -.names n2428 Ng1917 Ng1894 n2436 -00- 1 -1-0 1 --00 1 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-1--1 1 --0-1 1 -.names n2454 Ng1648 Ng1624 n2462 -00- 1 -1-0 1 --00 1 -.names n2462 n2459 n2461 -11 1 -.names Ng1657 n4881 n4970 n2463 -1-- 1 --1- 1 ---0 1 -.names Pg35 n2454 Ng1624 Ng1632 n2464 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names Pg35 n2196 Ng1373 n2466 -0-- 1 --1- 1 ---0 1 -.names n2196 n3875 Ng1373 n2467 -0-- 1 --1- 1 ---1 1 -.names Ng1270 n2468 n4222 n2469 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng1263 n2470 -1- 1 --0 1 -.names Ng1263 n4813 n2468 -0- 1 --0 1 -.names Pg35 n2209 Ng1030 n2472 -0-- 1 --1- 1 ---0 1 -.names n2209 n3881 Ng1030 n2473 -0-- 1 --1- 1 ---1 1 -.names Ng925 n2474 n4235 n2475 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng918 n2476 -1- 1 --0 1 -.names Ng918 n4826 n2474 -0- 1 --0 1 -.names Ng758 n2477 n3791 n2478 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng749 n2479 -1- 1 --0 1 -.names Ng749 n2546 n2477 -0- 1 --1 1 -.names Pg35 Ng582 n2482 -1- 1 --0 1 -.names Ng582 n2549 n2480 -0- 1 --1 1 -.names n4660 Ng291 n2484 -0- 1 --1 1 -.names n3904 n4660 Ng291 n2485 -1-- 1 --1- 1 ---0 1 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--0-1 1 ---11 1 -.names n5984 n4259 Ng417 n3813 -1-- 1 --1- 1 ---1 1 -.names Pg35 n4170 n3812 -0- 1 --0 1 -.names n1960 Ng5011 n3815 -1- 1 --0 1 -.names n1969 Ng4826 n3816 -1- 1 --0 1 -.names n1978 Ng4831 n3817 -1- 1 --0 1 -.names n3393 n3849 n4784 Ng4821 n3818 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names [4427] n1990 n3819 -0- 1 --1 1 -.names n1998 n3501 Ng4049 n3821 -11- 1 --11 1 -1-0 1 -.names Ng4045 n3516 n3520 n3822 -01- 1 -1-1 1 --11 1 -.names n1165 n3821 n3822 Ng4961 n3820 -0--0 1 --110 1 -.names n2002 Ng4961 n3824 -1- 1 --0 1 -.names n4564 n1118 n3823 -1- 1 --1 1 -.names Ng3694 n4792 n5034 n3826 -11- 1 -0-1 1 --11 1 -.names n2007 n3572 Ng3698 n3827 -11- 1 --11 1 -1-0 1 -.names n1116 n3826 n3827 Ng4950 n3825 -0--0 1 --110 1 -.names n2011 Ng4950 n3829 -1- 1 --0 1 -.names n4564 n1136 n3828 -1- 1 --1 1 -.names Ng4975 Ng4899 n4564 n3830 -1-- 1 --1- 1 ---1 1 -.names Pg35 n1135 n3832 -0- 1 --1 1 -.names Ng6732 n3223 n3227 n3834 -01- 1 -1-1 1 --11 1 -.names n1956 n3208 Ng6736 n3835 -11- 1 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Ng4119 n3861 -1- 1 --0 1 -.names Pg35 n3855 Ng4122 n3862 -0-- 1 --0- 1 ---0 1 -.names n4786 n5068 n3855 -1- 1 --0 1 -.names Pg35 Ng4145 n3860 -0- 1 --0 1 -.names Pg35 Ng4116 n3863 -1- 1 --0 1 -.names Pg35 n5070 Ng4119 n3864 -0-- 1 --1- 1 ---0 1 -.names Pg35 Ng4112 n3865 -1- 1 --0 1 -.names Pg35 n5071 Ng4116 n3866 -0-- 1 --1- 1 ---0 1 -.names Pg35 Ng4076 n3867 n5992 n3868 -0--1 1 --0-1 1 ---01 1 -.names n4787 Ng4082 n3867 -0- 1 --0 1 -.names n2002 Ng4035 n3869 -1- 1 --0 1 -.names n2011 Ng3684 n3870 -1- 1 --0 1 -.names n3626 n3832 n4793 Ng3333 n3871 -11-- 1 --11- 1 -1--0 1 ---10 1 -.names Pg35 Ng2724 n3873 -1- 1 --0 1 -.names n4690 Ng2729 n3872 -01 1 -10 1 -.names Pg35 n2194 Ng1345 n5993 n3876 -0--1 1 --1-1 1 ---01 1 -.names Pg35 n4805 n3875 -0- 1 --0 1 -.names Ng1252 n3877 n4222 n3878 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng1280 n3879 -1- 1 --0 1 -.names n4808 Ng1280 n3877 -1- 1 --0 1 -.names Pg35 n2207 Ng1002 n5994 n3882 -0--1 1 --1-1 1 ---01 1 -.names Pg35 n4818 n3881 -0- 1 --0 1 -.names Ng907 n3883 n4235 n3884 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng936 n3885 -1- 1 --0 1 -.names n4821 Ng936 n3883 -1- 1 --0 1 -.names n3784 Ng827 n5049 n3887 -0-- 1 --1- 1 ---1 1 -.names n4037 Ng827 n5049 n3888 -1-- 1 --0- 1 ---0 1 -.names n3812 Ng699 n3890 -1- 1 --0 1 -.names Pg35 n5075 n3891 -0- 1 --1 1 -.names n3891 Ng681 Ng650 n5074 n3893 -1-0- 1 --00- 1 -1--0 1 --0-0 1 -.names Ng703 Ng714 n4192 n3894 -0-0 1 --10 1 -.names Ng572 n3899 n4508 n3900 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng568 n3901 -1- 1 --0 1 -.names Ng568 n4046 n3899 -0- 1 --1 1 -.names Pg35 Ng528 n3903 -1- 1 --0 1 -.names n1172 Ng482 n3902 -11 1 -00 1 -.names Pg35 n4657 n3904 -0- 1 --0 1 -.names n1108 n1112 n3907 -1- 1 --1 1 -.names n3907 n1150 n1108 n1112 n3906 -11-- 1 -1-11 1 -.names n1101 n1131 n1133 n3911 -100 1 -.names n1101 n1131 n1133 n4567 n3914 -1--0 1 --000 1 -.names Ng4531 Ng4581 n3915 -11 1 -.names Pg10306 Pg35 n3916 -11 1 -.names Pg35 Ng4515 Ng4521 n3918 -0-- 1 --0- 1 ---0 1 -.names Ng4392 Ng4417 n3943 n3923 -1-- 1 --1- 1 ---1 1 -.names Pg35 Ng4392 n3923 n5081 n3920 -00-- 1 --01- 1 -0--0 1 ---10 1 -.names Ng4438 Ng4443 Ng4452 Pg7245 Pg7260 n3926 -1---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names Pg35 Ng4392 n3926 n3925 -10- 1 -1-1 1 -.names Pg35 Ng4392 n3929 -0- 1 --1 1 -.names Pg35 Ng4392 n3926 n3933 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng4443 n3934 -1- 1 --0 1 -.names Pg35 Ng4382 Ng4438 n3935 -0-- 1 --1- 1 ---0 1 -.names Ng4401 Ng4434 n3937 -01 1 -10 1 -.names Pg35 n3937 Ng4388 Ng4430 n3936 -11-- 1 -1-10 1 -.names Pg35 Ng4423 n3940 -0- 1 --0 1 -.names Ng4405 Ng4375 Ng4411 Pg7257 Pg7243 n3943 -1---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names Pg35 Ng4392 n3943 n3942 -10- 1 -1-1 1 -.names Ng4382 n5081 Ng4375 n3948 -0-- 1 --0- 1 ---1 1 -.names Ng4382 n5081 Ng4375 n3949 -1-- 1 --0- 1 ---0 1 -.names Pg35 n3923 Ng4388 n3950 -11- 1 -0-0 1 --10 1 -.names Pg35 Ng4392 n3943 n3952 -0-- 1 --0- 1 ---1 1 -.names n3943 n3929 n3953 -1- 1 --1 1 -.names Pg35 Ng4141 n3955 -1- 1 --0 1 -.names n4787 Ng4082 n3954 -11 1 -00 1 -.names n1256 n1254 Ng2827 Ng2595 n3957 -00-- 1 --00- 1 -0--1 1 ---01 1 -.names n1256 n1254 Ng2823 Ng2461 n3959 -00-- 1 --00- 1 -0--1 1 ---01 1 -.names n1256 n1254 Ng2811 Ng2327 n3961 -00-- 1 --00- 1 -0--1 1 ---01 1 -.names n1256 n1254 Ng2799 Ng2193 n3963 -00-- 1 --00- 1 -0--1 1 ---01 1 -.names n1256 n1254 Ng2795 Ng2036 n3965 -00-- 1 --00- 1 -0--1 1 ---01 1 -.names n1256 n1254 Ng2791 Ng1902 n3967 -00-- 1 --00- 1 -0--1 1 ---01 1 -.names n1256 n1254 Ng2779 Ng1768 n3969 -00-- 1 --00- 1 -0--1 1 ---01 1 -.names n1256 n1254 Ng2767 Ng1632 n3971 -00-- 1 --00- 1 -0--1 1 ---01 1 -.names n3046 Ng2724 n4689 n3973 -1-- 1 --0- 1 ---0 1 -.names Ng2724 n4689 Ng2841 n3974 -1-- 1 --1- 1 ---0 1 -.names Pg35 Ng1437 n3976 -1- 1 --0 1 -.names Pg35 Ng1478 n5084 n3977 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng1467 n3979 -1- 1 --0 1 -.names Pg35 Ng1472 n5085 n3980 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng1448 n5086 n3983 -0-- 1 --0- 1 ---1 1 -.names Pg12923 Pg7946 Pg19357 Ng1333 n3984 -11-- 1 -1-1- 1 -1--1 1 -.names Ng1395 n3984 n3985 -11 1 -.names n854 Ng1384 Ng1351 n3986 -01- 1 -0-0 1 -.names Pg35 n3986 Ng1389 n3990 -0-- 1 --1- 1 ---0 1 -.names Ng1280 n4808 n3993 -1- 1 --1 1 -.names n4222 n4808 Ng1280 n3994 -1-- 1 --0- 1 ---0 1 -.names Pg35 Ng1094 n3996 -1- 1 --0 1 -.names Pg35 Ng1135 n5090 n3997 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng1124 n3999 -1- 1 --0 1 -.names Pg35 Ng1129 n5091 n4000 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng1105 n5092 n4003 -0-- 1 --0- 1 ---1 1 -.names Pg12919 Pg7916 Pg19334 Ng990 n4004 -11-- 1 -1-1- 1 -1--1 1 -.names Pg35 n4004 Ng1061 Ng1052 n4005 -00-- 1 --00- 1 -0--0 1 ---00 1 -.names n379 Ng1008 Ng1041 n4010 -00- 1 -0-1 1 -.names Pg35 n4010 Ng1046 n4014 -0-- 1 --1- 1 ---0 1 -.names Ng936 n4821 n4017 -1- 1 --1 1 -.names n4235 n4821 Ng936 n4018 -1-- 1 --0- 1 ---0 1 -.names Pg35 Ng890 n4019 -10 1 -.names Ng446 n5094 n5096 Ng872 n4021 -0-1- 1 --11- 1 -0--0 1 --1-0 1 -.names Pg14167 Ng246 n5094 n5096 n4023 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pg14147 Ng269 n5094 n5096 n4025 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pg14125 Ng239 n5094 n5096 n4027 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pg14096 Ng262 n5094 n5096 n4029 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pg14217 Ng232 n5094 n5096 n4031 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pg14201 Ng255 n5094 n5096 n4033 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names Pg14189 Ng225 n5094 n5096 n4035 -00-- 1 -0-1- 1 --0-1 1 ---11 1 -.names n4379 Ng822 n4036 -01 1 -10 1 -.names Pg35 n3784 n4037 -0- 1 --0 1 -.names Pg35 Ng847 Ng843 n4039 -10- 1 -1-0 1 -.names Pg35 [4435] n4363 n4044 -0-- 1 --0- 1 ---1 1 -.names Ng568 n4046 n4508 n4047 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng562 n4048 -1- 1 --0 1 -.names n1205 Ng562 n4503 n4046 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng351 Ng355 Ng333 n4049 -0-0- 1 --100 1 -.names [4436] Ng351 n4052 -00 1 -.names Ng311 Ng324 Ng305 n4055 -1-0 1 --00 1 -.names Pg35 Ng336 n5109 n4059 -0-- 1 --0- 1 ---0 1 -.names Pg35 Ng311 n4060 -1- 1 --0 1 -.names Pg35 n5109 n4058 -0- 1 --1 1 -.names Pg35 Ng329 n6013 n4063 -11- 1 -1-1 1 --01 1 -.names Ng311 Ng305 Ng336 n4061 -00- 1 --01 1 -0-0 1 -.names Ng311 Ng305 n4064 -00 1 -.names Ng6537 n3184 n4886 n5409 n4067 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names Pg35 Ng6509 n4070 -1- 1 --0 1 -.names Pg35 n3184 Ng6513 n4071 -0-- 1 --1- 1 ---1 1 -.names Ng6191 n3238 n4894 n5417 n4073 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names Pg35 Ng6163 n4076 -1- 1 --0 1 -.names Pg35 n3238 Ng6167 n4077 -0-- 1 --1- 1 ---1 1 -.names Ng5845 n3291 n4901 n5425 n4079 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names Pg35 Ng5817 n4082 -1- 1 --0 1 -.names Pg35 n3291 Ng5821 n4083 -0-- 1 --1- 1 ---1 1 -.names Ng5499 n3346 n4908 n5433 n4085 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names Pg35 Ng5471 n4088 -1- 1 --0 1 -.names Pg35 n3346 Ng5475 n4089 -0-- 1 --1- 1 ---1 1 -.names Ng5152 n3401 n4092 n5441 n4091 -01-- 1 --11- 1 -0--0 1 ---10 1 -.names Pg35 Ng5124 n4094 -1- 1 --0 1 -.names Pg35 n3401 Ng5128 n4095 -0-- 1 --1- 1 ---1 1 -.names Pg35 n3401 n4092 -0- 1 --0 1 -.names Pg35 Ng5097 n4097 -1- 1 --0 1 -.names Ng5097 n5122 n4096 -0- 1 --0 1 -.names Pg35 Ng5092 n4100 -1- 1 --0 1 -.names Pg35 Ng5097 n5122 n4101 -0-- 1 --0- 1 ---1 1 -.names Ng5092 Pg35 n4102 -11 1 -.names Pg35 Ng5073 Ng5077 n4106 -0-- 1 --1- 1 ---0 1 -.names Pg35 Ng5084 n4103 -10 1 -.names Ng4098 Ng4093 n4110 -10 1 -.names n1635 Ng4087 Ng4057 Ng4064 Ng4076 n4110 n4107 -110011 1 -.names n4786 Ng4141 Ng2841 n4112 -1-- 1 --1- 1 ---0 1 -.names n3474 n4786 Ng4141 n4113 -1-- 1 --0- 1 ---0 1 -.names Pg35 Ng4064 Ng4072 n4115 -11- 1 -0-0 1 --10 1 -.names n4115 n1994 n4114 -11 1 -.names Ng3845 n3476 n4922 n5454 n4117 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names Pg35 Ng3817 n4120 -1- 1 --0 1 -.names Pg35 n3476 Ng3821 n4121 -0-- 1 --1- 1 ---1 1 -.names Ng3494 n3531 n4928 n5462 n4123 -01-- 1 --10- 1 -0--0 1 ---00 1 -.names Pg35 Ng3466 n4126 -1- 1 --0 1 -.names Pg35 n3531 Ng3470 n4127 -0-- 1 --1- 1 ---1 1 -.names n3583 n4934 Ng3143 n5470 n4129 -10-- 1 -1-0- 1 --0-0 1 ---00 1 -.names Pg35 Ng3115 n4132 -1- 1 --0 1 -.names Pg35 n3583 Ng3119 n4133 -0-- 1 --1- 1 ---1 1 -.names Ng2715 Ng2719 n4135 -0- 1 --1 1 -.names Pg35 Ng2715 n4862 n4136 -00- 1 -1-1 1 --01 1 -.names n4135 n1736 n4136 n4134 -111 1 -.names Pg35 Ng1484 n4138 -1- 1 --0 1 -.names Pg35 Ng1300 n5132 n4139 -0-- 1 --0- 1 ---1 1 -.names Pg35 n854 Ng1384 n4140 -0-- 1 --0- 1 ---0 1 -.names Ng1384 n854 n5088 n4141 -1-- 1 --1- 1 ---1 1 -.names Ng1361 Ng1373 n4144 -0- 1 --0 1 -.names n2194 n4144 n5088 n6036 n4142 -0-0- 1 --100 1 -.names Pg35 Pg12923 Ng1266 n4149 -10- 1 -1-1 1 -.names Ng1249 n4222 n4152 -1- 1 --1 1 -.names Pg35 Ng1141 n4154 -1- 1 --0 1 -.names Pg35 Ng956 n5135 n4155 -0-- 1 --0- 1 ---1 1 -.names Pg35 n379 Ng1041 n4156 -0-- 1 --0- 1 ---0 1 -.names Ng1041 n379 n5093 n4157 -1-- 1 --1- 1 ---1 1 -.names Ng1018 Ng1030 n4160 -0- 1 --0 1 -.names n2207 n4160 n5093 n6044 n4158 -0-0- 1 --100 1 -.names Pg35 Pg12919 Ng921 n4165 -10- 1 -1-1 1 -.names Ng904 n4235 n4168 -1- 1 --1 1 -.names Ng385 n4201 Ng370 n4170 -0-- 1 --1- 1 ---0 1 -.names Pg35 n3784 Ng832 n4170 n4169 -10-- 1 -1-1- 1 -1--1 1 -.names n5184 n5185 n4176 -1- 1 --1 1 -.names n4388 n4389 n4177 -1- 1 --1 1 -.names n1215 Ng732 n4178 -1- 1 --0 1 -.names Pg35 n4192 n4365 n4182 -0-- 1 --1- 1 ---0 1 -.names Pg35 Ng691 n4183 -1- 1 --0 1 -.names Pg35 n4192 n4180 -0- 1 --0 1 -.names n1205 Ng562 n4186 -01 1 -10 1 -.names Ng632 Ng626 n4186 n4508 n4184 -0-10 1 --010 1 -.names Ng385 Ng376 Ng358 n4192 -0-- 1 --1- 1 ---0 1 -.names Pg35 n4192 n5056 n4190 -11- 1 -1-0 1 -.names n4180 Ng499 Ng504 n4196 -10- 1 -0-0 1 --00 1 -.names Ng246 n5136 n5137 Ng460 n4198 -0-0- 1 --10- 1 -0--0 1 --1-0 1 -.names Ng182 Ng446 n5136 n5137 n4200 -00-- 1 -0-1- 1 --0-0 1 ---10 1 -.names Pg35 Ng376 n4202 -1- 1 --0 1 -.names Pg35 Ng385 n4201 n4203 -0-- 1 --0- 1 ---0 1 -.names Ng376 Ng358 n4201 -0- 1 --0 1 -.names Pg35 Ng4332 Ng4322 Ng4311 n4521 n4204 -0---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names Ng4340 Ng4643 n4205 -1- 1 --0 1 -.names Ng4633 Ng4616 n4204 Ng4601 Ng4584 Ng4608 Ng4593 n4637 n4208 -0------- 1 --1------ 1 ---1----- 1 ----1---- 1 -----1--- 1 ------1-- 1 -------1- 1 --------1 1 -.names Pg35 Ng4258 n4210 -0- 1 --1 1 -.names Pg35 n4210 Ng4264 n4209 -01- 1 --11 1 -.names Pg35 n4209 Ng4269 n4211 -01- 1 --11 1 -.names Pg35 Ng4264 Ng4273 Ng4258 n4212 -10-- 1 -1-1- 1 -1--0 1 -.names Pg35 Ng2715 Ng2712 n4218 -11- 1 -0-0 1 --10 1 -.names n4218 n1736 n4217 -11 1 -.names Pg35 Ng1548 n4220 -1- 1 --0 1 -.names Pg35 Ng1564 n5130 n4221 -0-- 1 --0- 1 ---1 1 -.names Pg35 Pg12923 n4222 -0- 1 --0 1 -.names Ng1548 Pg35 n4223 -11 1 -.names n854 n1218 n4392 n4226 -001 1 -.names n4226 Pg35 n4225 -11 1 -.names Pg35 Ng1589 n4227 -1- 1 --0 1 -.names Pg35 Pg17423 Pg10527 n4228 -0-- 1 --1- 1 ---0 1 -.names Pg35 Pg12923 n4231 -10 1 -.names Pg35 Ng1205 n4233 -1- 1 --0 1 -.names Pg35 Ng1221 n5133 n4234 -0-- 1 --0- 1 ---1 1 -.names Pg35 Pg12919 n4235 -0- 1 --0 1 -.names Ng1205 Pg35 n4236 -11 1 -.names n4393 n634 n4239 -11 1 -.names n4239 Pg35 n4238 -11 1 -.names Pg35 Ng1246 n4241 -1- 1 --0 1 -.names Pg35 Pg17400 Pg10500 n4242 -0-- 1 --1- 1 ---0 1 -.names Pg35 Pg12919 n4245 -10 1 -.names Pg35 n3786 Ng832 Ng827 n4246 -110- 1 -11-0 1 -.names n4170 Ng847 n4248 -01 1 -.names Pg35 Ng837 Ng703 n4248 n4247 -0-1- 1 --011 1 -.names Pg35 Ng837 n3786 n3812 n4251 -0--1 1 --101 1 -.names Pg35 Ng847 n6102 n4253 -11- 1 -1-1 1 --01 1 -.names Ng691 Ng542 n4256 -10 1 -.names Pg35 n4170 n4259 -0- 1 --1 1 -.names n3812 n4259 Ng246 Ng475 n4261 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n3812 n4259 Ng269 Ng433 n4263 -11-- 1 -1-0- 1 --1-0 1 ---00 1 -.names n3812 Ng392 n4265 -1- 1 --0 1 -.names Ng703 n4259 Ng854 n4266 -1-- 1 --1- 1 ---0 1 -.names Pg35 Ng4269 Ng4258 n4267 -11- 1 -1-0 1 -.names Ng4264 Pg35 n4268 -11 1 -.names Ng4349 n4303 n4271 -0- 1 --1 1 -.names Pg35 n4271 n4270 -11 1 -.names n4368 Ng2988 n4272 -00 1 -.names Ng4564 Ng4555 Ng4561 Ng4558 n4275 -0--- 1 --0-- 1 ---0- 1 ----0 1 -.names n4275 Ng2988 n4274 -10 1 -.names Pg35 Ng2667 n4276 -10 1 -.names Pg35 Ng2527 n4277 -10 1 -.names Pg35 Ng2399 n4279 -10 1 -.names Pg35 Ng2265 n4280 -10 1 -.names Pg35 Ng2102 n4281 -10 1 -.names Pg35 Ng1968 n4283 -10 1 -.names Pg35 Ng1840 n4285 -10 1 -.names Pg35 Ng1706 n4286 -10 1 -.names n4356 Ng1542 n4288 -1- 1 --0 1 -.names Pg35 n4288 n4287 -11 1 -.names n4358 Ng1199 n4290 -1- 1 --0 1 -.names Pg35 n4290 n4289 -11 1 -.names Pg35 Ng6533 n4291 -10 1 -.names Pg35 Ng6187 n4292 -10 1 -.names Pg35 Ng5841 n4293 -10 1 -.names Pg35 Ng5495 n4294 -10 1 -.names Pg35 Ng5148 n4295 -10 1 -.names Pg35 Ng3841 n4296 -10 1 -.names Pg35 Ng3490 n4297 -10 1 -.names Pg35 Ng3139 n4298 -10 1 -.names Pg35 n1621 Ng385 n4299 -10- 1 --00 1 -.names n4299 Ng25599 -0 1 -.names Ng4593 n4640 n4300 -0- 1 --0 1 -.names Ng4332 Ng4322 n4638 n4301 -111 1 -.names Ng4628 n4637 n4303 -0- 1 --1 1 -.names Ng4349 n4303 n4302 -01 1 -10 1 -.names Ng4688 n4556 n4304 -0- 1 --1 1 -.names Ng2599 Ng2629 n4307 -1- 1 --0 1 -.names n4307 Ng112 n4305 -11 1 -00 1 -.names Ng2465 Ng2495 n4309 -1- 1 --0 1 -.names n4309 Ng112 n4308 -11 1 -00 1 -.names Ng2331 Ng2361 n4311 -1- 1 --0 1 -.names n4311 Ng112 n4310 -11 1 -00 1 -.names Ng2197 Ng2227 n4313 -1- 1 --0 1 -.names n4313 Ng112 n4312 -11 1 -00 1 -.names Ng2040 Ng2070 n4315 -1- 1 --0 1 -.names n4315 Ng112 n4314 -11 1 -00 1 -.names Ng1906 Ng1936 n4317 -1- 1 --0 1 -.names n4317 Ng112 n4316 -11 1 -00 1 -.names Ng1772 Ng1802 n4319 -1- 1 --0 1 -.names n4319 Ng112 n4318 -11 1 -00 1 -.names Ng1636 Ng1668 n4321 -1- 1 --0 1 -.names n4321 Ng112 n4320 -11 1 -00 1 -.names Ng1339 Ng1322 n4322 -11 1 -00 1 -.names Ng996 Ng979 n4323 -11 1 -00 1 -.names Ng2610 Ng2619 n4325 -1- 1 --0 1 -.names Ng110 n4325 n4324 -01 1 -10 1 -.names Ng2476 Ng2485 n4327 -1- 1 --0 1 -.names Ng110 n4327 n4326 -01 1 -10 1 -.names Ng2342 Ng2351 n4329 -1- 1 --0 1 -.names Ng110 n4329 n4328 -01 1 -10 1 -.names Ng2208 Ng2217 n4331 -1- 1 --0 1 -.names Ng110 n4331 n4330 -01 1 -10 1 -.names Ng2051 Ng2060 n4333 -1- 1 --0 1 -.names Ng110 n4333 n4332 -01 1 -10 1 -.names Ng1917 Ng1926 n4335 -1- 1 --0 1 -.names Ng110 n4335 n4334 -01 1 -10 1 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Ng4349 Ng4358 n4515 -0- 1 --1 1 -.names Ng3352 Ng3288 n4516 -0- 1 --0 1 -.names Ng4349 Ng4358 n4518 -1- 1 --0 1 -.names Ng4358 Ng4349 n4521 -1- 1 --1 1 -.names Ng5357 Ng5297 n4527 -0- 1 --0 1 -.names Ng2759 Pg72 n4531 -01 1 -10 1 -.names Ng2763 Pg73 n4532 -01 1 -10 1 -.names n4531 n4532 n4530 -1- 1 --1 1 -.names Ng2756 Ng2748 n4530 n4533 -0-- 1 --1- 1 ---1 1 -.names Ng2208 Ng2217 n4535 -0- 1 --1 1 -.names Ng2756 Ng2748 Ng2741 n4536 -1-- 1 --1- 1 ---0 1 -.names Ng1783 Ng1792 n4538 -0- 1 --1 1 -.names Ng2748 n4530 n4540 -0- 1 --1 1 -.names Ng2051 Ng2060 n4542 -0- 1 --1 1 -.names Ng1917 Ng1926 n4544 -0- 1 --1 1 -.names Ng2476 Ng2485 n4546 -0- 1 --1 1 -.names Ng2342 Ng2351 n4548 -0- 1 --1 1 -.names Ng2610 Ng2619 n4550 -0- 1 --1 1 -.names Ng2756 Ng2748 Ng2741 n4551 -000 1 -.names Ng1648 Ng1657 n4553 -0- 1 --1 1 -.names Ng4669 Ng4659 Ng4653 n4556 -0-- 1 --0- 1 ---0 1 -.names Ng4793 Ng4776 Ng4801 n4559 -0-- 1 --0- 1 ---1 1 -.names Ng4859 Ng4843 Ng4849 n4561 -0-- 1 --0- 1 ---0 1 -.names Ng4983 Ng4966 Ng4991 n4564 -0-- 1 --0- 1 ---1 1 -.names n1086 n1150 n3907 n4567 -1-- 1 --1- 1 ---1 1 -.names Pg35 Ng6509 n4569 -11 1 -.names n1107 n2565 n4343 n2564 n4569 n4345 n4568 -1----- 1 --1---- 1 ---1--- 1 ----1-- 1 -----1- 1 ------1 1 -.names n1101 n1131 n1133 n1134 n4567 n4570 -10000 1 -.names Ng3171 Ng3179 n4577 -0- 1 --0 1 -.names Ng6219 Ng6227 n4581 -0- 1 --0 1 -.names Ng4098 Ng4093 n4582 -01 1 -.names Ng3873 Ng3881 n4584 -0- 1 --0 1 -.names Ng4098 Ng4093 n4585 -11 1 -.names Ng5527 Ng5535 n4587 -0- 1 --0 1 -.names Ng6565 Ng6573 n4588 -0- 1 --0 1 -.names Ng5873 Ng5881 n4590 -0- 1 --0 1 -.names Ng3522 Ng3530 n4593 -0- 1 --0 1 -.names Ng5180 Ng5188 n4595 -0- 1 --0 1 -.names Ng4108 Pg72 n4596 -01 1 -10 1 -.names Ng4104 Pg73 n4597 -01 1 -10 1 -.names n1408 n4673 n4630 -10 1 -.names Ng4878 Ng4843 n4632 -0- 1 --0 1 -.names n4304 n4676 n4633 -10 1 -.names Ng4688 Ng4653 n4635 -0- 1 --0 1 -.names Ng4621 Ng4639 Ng4340 n4637 -0-- 1 --1- 1 ---0 1 -.names n4271 Ng4358 n4638 -01 1 -.names Ng4584 n4301 n4640 -11 1 -.names Pg35 n1572 n4641 -0- 1 --1 1 -.names Ng4311 n4638 n4642 -11 1 -.names Ng4818 [4661] n1160 n4652 -1-- 1 --1- 1 ---1 1 -.names n4652 Ng71 n4653 -01 1 -.names Ng4818 [4661] n1160 n4654 -1-- 1 --1- 1 ---1 1 -.names n282 Ng278 n281 n4659 -01- 1 -0-1 1 --01 1 -.names n1212 Ng691 n4659 n4657 -011 1 -.names Ng287 Ng283 n4657 n4660 -111 1 -.names n4660 Ng291 n4661 -0- 1 --0 1 -.names Ng294 n4661 n4663 -0- 1 --1 1 -.names Ng298 n4663 n4664 -0- 1 --1 1 -.names n1212 n1691 Ng691 n4666 -1-- 1 --1- 1 ---0 1 -.names n359 Ng146 n4666 n4667 -110 1 -.names Ng164 n4667 n4669 -11 1 -.names n4669 Ng150 n4670 -0- 1 --0 1 -.names Ng153 n4670 n4672 -0- 1 --1 1 -.names n1221 n1406 Ng63 n4673 -101 1 -.names n1710 Ng4966 n4674 -01 1 -.names n1221 n1368 Ng63 n4676 -101 1 -.names n1726 Ng4776 n4677 -01 1 -.names Ng2715 Ng2719 n4689 -0- 1 --0 1 -.names Ng2724 n4689 n4690 -0- 1 --1 1 -.names n4346 Ng2741 n4691 -1- 1 --0 1 -.names Ng2748 n4691 n4692 -0- 1 --1 1 -.names Ng1564 Ng1548 Ng1322 Ng1559 Ng1554 Ng1404 n4695 -1----- 1 --1---- 1 ---0--- 1 ----1-- 1 -----1- 1 ------0 1 -.names Ng2629 Ng2555 n4696 -00 1 -.names n4696 n4700 n4697 -0- 1 --0 1 -.names n4697 Pg35 n4699 -11 1 -.names n1140 n1261 n4700 -1- 1 --0 1 -.names Ng2599 Ng2555 n4702 -10 1 -.names n4700 n4702 n4703 -11 1 -.names n4700 Ng2555 n4704 -0- 1 --0 1 -.names Ng2495 Ng2421 n4706 -00 1 -.names n4706 n4710 n4707 -0- 1 --0 1 -.names n4707 Pg35 n4709 -11 1 -.names n1093 n1264 n4710 -1- 1 --0 1 -.names Ng2465 Ng2421 n4712 -10 1 -.names n4710 n4712 n4713 -11 1 -.names n4710 Ng2421 n4714 -0- 1 --0 1 -.names Ng2361 Ng2287 n4716 -00 1 -.names n4716 n4720 n4717 -0- 1 --0 1 -.names n4717 Pg35 n4719 -11 1 -.names n1138 n1274 n4720 -1- 1 --0 1 -.names Ng2331 Ng2287 n4722 -10 1 -.names n4720 n4722 n4723 -11 1 -.names n4720 Ng2287 n4724 -0- 1 --0 1 -.names Ng2227 Ng2153 n4726 -00 1 -.names n4726 n4730 n4727 -0- 1 --0 1 -.names n4727 Pg35 n4729 -11 1 -.names n1096 n1270 n4730 -1- 1 --0 1 -.names Ng2227 n4730 n4731 -0- 1 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n5576 n5687 -011 1 -.names n5579 n5578 Ng4087 n5688 -111 1 -.names Ng2724 Ng2807 Ng2803 n5698 -10- 1 -0-0 1 --00 1 -.names Ng2724 Ng2819 Ng2815 n5699 -10- 1 -0-0 1 --00 1 -.names Ng2724 Ng2775 Ng2771 n5700 -10- 1 -0-0 1 --00 1 -.names Ng2724 Ng2787 Ng2783 n5701 -10- 1 -0-0 1 --00 1 -.names Pg35 Ng2894 n5704 -1- 1 --0 1 -.names Pg35 Ng1291 n5705 -0- 1 --0 1 -.names Pg35 Ng947 n5706 -0- 1 --0 1 -.names Pg35 Ng4878 Ng4843 n4630 n5710 -01-- 1 --101 1 -.names Pg35 Ng4688 Ng4653 n4633 n5712 -01-- 1 --101 1 -.names n1552 Ng4340 n1555 n5715 -10- 1 -0-1 1 --01 1 -.names Pg35 Ng2827 n5717 -1- 1 --0 1 -.names Pg35 Ng2815 n5719 -1- 1 --0 1 -.names Pg35 Ng2819 n5721 -1- 1 --0 1 -.names Pg35 Ng2807 n5723 -1- 1 --0 1 -.names Pg35 Ng2795 n5724 -1- 1 --0 1 -.names Pg35 Ng2783 n5725 -1- 1 --0 1 -.names Pg35 Ng2787 n5726 -1- 1 --0 1 -.names Pg35 Ng2775 n5727 -1- 1 --0 1 -.names Ng174 Ng392 Ng452 n5730 -00- 1 -0-0 1 --10 1 -.names Ng405 Ng437 Ng424 n5731 -10- 1 -0-0 1 --00 1 -.names Ng401 Ng405 Ng437 n5732 -01- 1 -0-0 1 --00 1 -.names Ng392 n5731 n5732 n5733 -01- 1 -1-1 1 --11 1 -.names n3823 n4652 n5734 -11 1 -.names n1647 Ng4955 n5734 n5735 -10- 1 --01 1 -1-0 1 -.names n3828 n4652 n5737 -11 1 -.names n1651 Ng4944 n5737 n5738 -10- 1 --01 1 -1-0 1 -.names n1407 n4652 n5740 -11 1 -.names n1658 Ng4888 n5740 n5741 -10- 1 --01 1 -1-0 1 -.names n3840 n4654 n5743 -11 1 -.names n1660 Ng4765 n5743 n5744 -10- 1 --01 1 -1-0 1 -.names n3845 n4654 n5746 -11 1 -.names n1664 Ng4754 n5746 n5747 -10- 1 --01 1 -1-0 1 -.names n3853 n4654 n5749 -11 1 -.names n1671 Ng4698 n5749 n5750 -10- 1 --01 1 -1-0 1 -.names Pg35 Ng4340 n5752 -1- 1 --0 1 -.names Ng157 n4672 n5754 -0- 1 --1 1 -.names Ng4512 Ng4581 n5755 -1- 1 --1 1 -.names n1222 n4272 n5252 n5756 -01- 1 -1-0 1 --10 1 -.names Ng4552 Ng4581 n5757 -1- 1 --1 1 -.names n1222 n4274 n5255 n5758 -01- 1 -1-0 1 --10 1 -.names Pg35 Ng2759 n5760 -1- 1 --0 1 -.names n1097 n4515 n4781 n5777 -0-- 1 --1- 1 ---1 1 -.names Pg35 n3391 n5290 n5777 n5775 -10-1 1 -1-01 1 -.names Pg35 Ng4108 n5781 -1- 1 --0 1 -.names Pg35 Ng2756 n5785 -1- 1 --0 1 -.names Pg35 Ng301 n5793 -1- 1 --0 1 -.names n4842 Ng5041 Ng5046 n5794 -1-- 1 --0- 1 ---0 1 -.names Ng5052 n4846 n5794 n5795 -01- 1 -1-1 1 --11 1 -.names Pg35 Ng4098 n5799 -1- 1 --0 1 -.names Pg35 n4840 Ng5033 n4844 n5809 --00- 1 -1-00 1 -.names Pg35 Ng5052 n4846 n5794 n5812 --0-0 1 -100- 1 -.names Pg35 Ng5041 n5815 -1- 1 --0 1 -.names Pg35 Ng5037 n5816 -1- 1 --0 1 -.names Pg35 Ng5033 n5817 -1- 1 --0 1 -.names Pg35 Ng5022 n5818 -1- 1 --0 1 -.names Pg35 Ng283 Ng287 n4657 n5819 -01-- 1 --101 1 -.names Ng4473 Ng4459 n5821 -0- 1 --1 1 -.names Pg124 Pg120 Ng4146 n5825 -00- 1 -0-1 1 --00 1 -.names Pg116 Pg114 Ng4157 n5828 -00- 1 -0-1 1 --00 1 -.names Ng2638 Ng2504 Ng2715 n5829 -00- 1 -0-1 1 --00 1 -.names Ng2819 Ng2815 Ng2715 n5830 -11- 1 -1-1 1 --10 1 -.names n1090 Ng2735 n4551 n5831 -1-- 1 --1- 1 ---0 1 -.names Ng2719 n5593 n5829 n5831 n5832 --0-1 1 -1-11 1 -.names Ng2719 n5595 n5830 n5831 n5833 --0-0 1 -1-10 1 -.names Ng1811 Ng1677 Ng2715 n5835 -00- 1 -0-1 1 --00 1 -.names Ng2787 Ng2783 Ng2715 n5836 -11- 1 -1-1 1 --10 1 -.names Ng2719 n5597 n5831 n5835 n5837 --01- 1 -0-11 1 -.names Ng2719 n5599 n5831 n5836 n5838 --00- 1 -1-01 1 -.names Pg35 Ng2675 n4945 Ng2681 n5840 -0--1 1 --111 1 -.names Pg35 n1153 Ng2657 n4947 n5842 -101- 1 -1-11 1 -.names Pg35 n1153 n4550 Ng2595 n5843 -10-1 1 -1-11 1 -.names Pg35 Ng2541 n4949 Ng2547 n5845 -0--1 1 --111 1 -.names Pg35 n1151 Ng2523 n4951 n5847 -101- 1 -1-11 1 -.names Pg35 n1151 n4546 Ng2461 n5848 -10-1 1 -1-11 1 -.names Pg35 Ng2407 n4952 Ng2413 n5850 -0--1 1 --111 1 -.names Pg35 n1162 Ng2389 n4954 n5852 -101- 1 -1-11 1 -.names Pg35 n1162 n4548 Ng2327 n5853 -10-1 1 -1-11 1 -.names Pg35 Ng2273 n4955 Ng2279 n5855 -0--1 1 --111 1 -.names Pg35 n1104 Ng2255 n4957 n5857 -101- 1 -1-11 1 -.names Pg35 n1104 n4535 Ng2193 n5858 -10-1 1 -1-11 1 -.names Pg35 Ng2116 n4959 Ng2122 n5860 -0--1 1 --111 1 -.names Pg35 n1146 Ng2098 n4961 n5862 -101- 1 -1-11 1 -.names Pg35 n1146 n4542 Ng2036 n5863 -10-1 1 -1-11 1 -.names Pg35 Ng1982 n4962 Ng1988 n5865 -0--1 1 --111 1 -.names Pg35 n1126 Ng1964 n4964 n5867 -101- 1 -1-11 1 -.names Pg35 n1126 n4544 Ng1902 n5868 -10-1 1 -1-11 1 -.names Pg35 Ng1848 n4965 Ng1854 n5870 -0--1 1 --111 1 -.names Pg35 n1182 Ng1830 n4967 n5872 -101- 1 -1-11 1 -.names Pg35 n1182 n4538 Ng1768 n5873 -10-1 1 -1-11 1 -.names Pg35 Ng1714 n4968 Ng1720 n5875 -0--1 1 --111 1 -.names Pg35 n1087 Ng1696 n4970 n5877 -101- 1 -1-11 1 -.names Pg35 n1087 n4553 Ng1632 n5878 -10-1 1 -1-11 1 -.names Pg35 Ng1536 n5879 -1- 1 --0 1 -.names Pg35 Ng1193 n5880 -1- 1 --0 1 -.names Pg35 n4983 Ng6513 Ng6519 n5883 -0--1 1 --011 1 -.names Pg35 Ng6500 n4983 Ng6505 n5885 -01-- 1 --100 1 -.names Pg12470 Ng6727 n5886 -11 1 -00 1 -.names Pg35 n1109 Ng6500 n5160 n5888 -101- 1 -1-11 1 -.names Pg35 n4990 Ng6167 Ng6173 n5891 -0--1 1 --011 1 -.names Pg35 Ng6154 n4990 Ng6159 n5893 -01-- 1 --100 1 -.names Pg12422 Ng6381 n5894 -11 1 -00 1 -.names Pg35 n1196 Ng6154 n5162 n5896 -101- 1 -1-10 1 -.names Pg35 n4998 Ng5821 Ng5827 n5900 -0--1 1 --011 1 -.names Pg35 Ng5808 n4998 Ng5813 n5902 -01-- 1 --100 1 -.names Pg12350 Ng6035 n5903 -11 1 -00 1 -.names Pg35 n1179 Ng5808 n5163 n5905 -101- 1 -1-11 1 -.names Pg35 n5005 Ng5475 Ng5481 n5908 -0--1 1 --011 1 -.names Pg35 n5005 Ng5467 Ng5462 n5910 -0--1 1 --001 1 -.names Pg12300 Ng5689 n5911 -11 1 -00 1 -.names Pg35 n1097 n5165 Ng5462 n5913 -10-1 1 -1-11 1 -.names Pg35 n5012 Ng5128 Ng5134 n5916 -0--1 1 --011 1 -.names Pg35 Ng5115 n5012 Ng5120 n5918 -01-- 1 --100 1 -.names [4415] Pg12238 n5919 -11 1 -00 1 -.names Pg35 [4394] Ng5115 n5167 n5921 -101- 1 -1-11 1 -.names n3455 Ng4983 Ng4991 n5922 -10- 1 --01 1 -.names n5612 n5611 n335 n5923 -111 1 -.names n3464 Ng4793 Ng4801 n5924 -10- 1 --01 1 -.names n5614 n5613 n419 n5925 -111 1 -.names Pg35 n5023 Ng3821 Ng3827 n5928 -0--1 1 --011 1 -.names Pg35 Ng3808 n5023 Ng3813 n5930 -01-- 1 --100 1 -.names Pg11418 Ng4040 n5931 -11 1 -00 1 -.names Pg35 n1165 Ng3808 n5168 n5933 -101- 1 -1-11 1 -.names Pg35 n5030 Ng3470 Ng3476 n5936 -0--1 1 --011 1 -.names Pg35 Ng3457 n5030 Ng3462 n5938 -01-- 1 --100 1 -.names Pg11388 Ng3689 n5939 -11 1 -00 1 -.names Pg35 n1116 Ng3457 n5170 n5941 -101- 1 -1-11 1 -.names Pg35 n5038 Ng3119 Ng3125 n5944 -0--1 1 --011 1 -.names Pg35 n5038 Ng3111 Ng3106 n5946 -0--1 1 --001 1 -.names Pg11349 Ng3338 n5947 -11 1 -00 1 -.names Pg35 n1135 n5172 Ng3106 n5949 -10-1 1 -1-11 1 -.names Pg35 Ng2729 n5951 -1- 1 --0 1 -.names n5174 n5043 Ng1454 n5357 n5952 -111- 1 -11-1 1 -.names Pg35 n5043 Ng1454 n5952 n5953 -1--1 1 -101- 1 -.names n5177 n5044 Ng1467 n5357 n5957 -111- 1 -11-1 1 -.names Pg35 n5044 Ng1467 n5957 n5958 -1--1 1 -101- 1 -.names n5178 n5045 Ng1437 n5357 n5961 -111- 1 -11-1 1 -.names Pg35 n5045 Ng1437 n5961 n5962 -1--1 1 -101- 1 -.names n5179 n5046 Ng1111 n5362 n5965 -111- 1 -11-1 1 -.names Pg35 n5046 Ng1111 n5965 n5966 -1--1 1 -101- 1 -.names n5182 n5047 Ng1124 n5362 n5970 -111- 1 -11-1 1 -.names Pg35 n5047 Ng1124 n5970 n5971 -1--1 1 -101- 1 -.names n5183 n5048 Ng1094 n5362 n5974 -111- 1 -11-1 1 -.names Pg35 n5048 Ng1094 n5974 n5975 -1--1 1 -101- 1 -.names Ng827 n5049 n5978 -10 1 -.names Ng676 n5054 n5980 -0- 1 --0 1 -.names Pg35 Ng482 n5982 -1- 1 --0 1 -.names Ng417 n5733 n5984 -11 1 -00 1 -.names Pg35 n4170 Ng417 n5984 n5983 -0-1- 1 --011 1 -.names Pg35 Ng5057 n5985 -1- 1 --0 1 -.names Pg35 Ng5069 n5986 -1- 1 --0 1 -.names Pg35 n1013 Ng4521 n5988 -0-- 1 --1- 1 ---1 1 -.names n4368 Ng4527 n5987 -11 1 -00 1 -.names Pg35 Ng4125 Ng26936 n5989 -0-- 1 --1- 1 ---0 1 -.names Pg35 Ng4082 n5992 -1- 1 --0 1 -.names Pg35 Ng1351 n5993 -1- 1 --0 1 -.names Pg35 Ng1008 n5994 -1- 1 --0 1 -.names Ng10384 Ng4473 n5995 -1- 1 --1 1 -.names Pg35 n4368 Ng4527 n5999 -01- 1 --11 1 -.names Pg35 Ng2712 Ng26936 n6001 -0-- 1 --1- 1 ---0 1 -.names Pg35 Ng1395 n6002 -1- 1 --0 1 -.names Ng890 Ng896 Ng862 n6003 -11- 1 -1-0 1 --00 1 -.names n3812 n4039 Ng812 n6004 -0-- 1 --1- 1 ---0 1 -.names Pg35 n1215 n6005 -0- 1 --1 1 -.names Ng528 n1173 n5057 n6007 -01- 1 -0-1 1 -.names Pg35 Pg7540 Ng347 n6010 -0-- 1 --0- 1 ---1 1 -.names Pg35 Ng329 n5109 Ng341 n6011 -0--- 1 --0-- 1 ---0- 1 ----1 1 -.names Pg35 Ng311 Ng305 Ng26885 n6013 -0--- 1 --1-- 1 ---1- 1 ----1 1 -.names Ng5069 Ng5077 n4103 Ng5080 n6022 -1-10 1 --010 1 -.names Pg35 Ng4057 Ng4064 Ng2841 n6023 -0-1- 1 --011 1 -.names Pg35 Ng1564 n6029 -1- 1 --0 1 -.names Ng1526 n3151 n6032 -0- 1 --1 1 -.names Ng1339 Ng1306 n6032 n6033 -00- 1 --01 1 -0-0 1 -.names n4322 Ng1389 n6036 -01 1 -.names Ng1351 n6036 n4144 n6035 -11- 1 -1-1 1 -.names Pg35 Ng1221 n6037 -1- 1 --0 1 -.names Ng1183 n3167 n6040 -0- 1 --1 1 -.names Ng996 Ng962 n6040 n6041 -00- 1 --01 1 -0-0 1 -.names n4323 Ng1046 n6044 -01 1 -.names Ng1008 n6044 n4160 n6043 -11- 1 -1-1 1 -.names n1621 Ng370 n6047 -11 1 -00 1 -.names Ng376 Ng358 n6048 -11 1 -00 1 -.names Pg8358 Ng191 n6050 -11 1 -00 1 -.names Ng209 n5139 n6050 n6052 -00- 1 -0-1 1 --11 1 -.names n5139 n6050 n6057 -11 1 -.names Pg8358 n6057 n6055 -11 1 -00 1 -.names Pg35 Ng6727 n6059 -1- 1 --0 1 -.names Ng6727 n5140 n6060 -11 1 -00 1 -.names Pg35 Ng6381 n6062 -1- 1 --0 1 -.names n5142 Ng6381 n6063 -01 1 -10 1 -.names Pg35 Ng6035 n6065 -1- 1 --0 1 -.names Ng6035 n5143 n6066 -11 1 -00 1 -.names Pg35 Ng5689 n6068 -1- 1 --0 1 -.names Ng5689 n5145 n6069 -11 1 -00 1 -.names Pg35 [4415] n6071 -1- 1 --0 1 -.names n5147 [4415] n6072 -01 1 -10 1 -.names Pg9251 Ng4308 n6074 -11 1 -00 1 -.names Ng4253 Ng4145 Ng4164 n6075 -01- 1 -1-1 1 --11 1 -.names Pg8870 Ng4235 n6078 -0- 1 --1 1 -.names Pg8918 Pg8917 Pg8920 Pg8919 Pg8916 Pg8915 Pg11770 n6077 -1------ 1 --1----- 1 ---1---- 1 ----1--- 1 -----1-- 1 ------1- 1 -------1 1 -.names Pg8870 Ng4235 n6078 n6077 n6076 -1-1- 1 --011 1 -.names n6076 n6075 n6079 -01 1 -10 1 -.names Pg35 Ng4040 n6082 -1- 1 --0 1 -.names n5149 Ng4040 n6083 -01 1 -10 1 -.names Pg35 Ng3689 n6085 -1- 1 --0 1 -.names n5150 Ng3689 n6086 -01 1 -10 1 -.names Pg35 Ng3338 n6088 -1- 1 --0 1 -.names n5151 Ng3338 n6089 -01 1 -10 1 -.names Pg7946 Pg19357 Pg13272 Ng1333 Pg8475 n6093 -1---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names n4226 n6093 n6092 -01 1 -10 1 -.names Pg7946 Ng1521 Ng1532 n6094 -10- 1 -0-0 1 --00 1 -.names Pg7946 Ng1339 Ng1521 n6095 -10- 1 -0-0 1 --00 1 -.names Pg7916 Pg19334 Pg13259 Ng990 Pg8416 n6098 -1---- 1 --1--- 1 ---1-- 1 ----1- 1 -----1 1 -.names n4239 n6098 n6097 -01 1 -10 1 -.names Pg7916 Ng1178 Ng1189 n6099 -10- 1 -0-0 1 --00 1 -.names Pg7916 Ng996 Ng1178 n6100 -10- 1 -0-0 1 --00 1 -.names n4259 Ng822 Ng817 Ng723 n6102 -1--- 1 --0-- 1 ---0- 1 ----0 1 -.names Pg8786 Ng4180 n6107 -0- 1 --1 1 -.names Pg8785 Pg8787 Pg8783 Pg8784 Pg8788 Pg8789 Pg11447 n6106 -1------ 1 --1----- 1 ---1---- 1 ----1--- 1 -----1-- 1 ------1- 1 -------1 1 -.names Pg8786 Ng4180 n6107 n6106 n6105 -1-1- 1 --011 1 -.names Ng4297 Pg10122 n6109 -1- 1 --1 1 -.names n2319 Ng25676 -0 1 -.names Pg35 Pg113 Ng25694 -11 1 -.names n2345 Ng25648 -0 1 -.names n1551 Ng34025 -0 1 -.names n2270 Ng25714 -0 1 -.names n2283 Ng25700 -0 1 -.names Pg35 Pg64 Ng24212 -11 1 -.names n2332 Ng25662 -0 1 -.names n4152 Ng24247 -0 1 -.names n4168 Ng24231 -0 1 -.names n3940 Ng26953 -0 1 -.names n4210 Ng21893 -0 1 -.names n2244 Ng25742 -0 1 -.names Pg35 Pg125 Ng28079 -11 1 -.names Ng4125 n1632 Ng4057 Ng4064 n6112 -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n5687 n5688 n1191 n6113 -1-- 1 --1- 1 ---1 1 -.names n1014 n1165 n4779 n6114 -1-- 1 --0- 1 ---1 1 -.names n1109 n4521 n4779 n6115 -0-- 1 --1- 1 ---1 1 -.names n1014 n1196 n4781 n6116 -1-- 1 --0- 1 ---1 1 -.names [4394] n4521 n4781 n6117 -0-- 1 --1- 1 ---1 1 -.names n1179 n4518 n4781 n6118 -0-- 1 --1- 1 ---1 1 -.names n1116 n4518 n4779 n6119 -0-- 1 --1- 1 ---1 1 -.names n1135 n4515 n4779 n6120 -0-- 1 --1- 1 ---1 1 -.names n184 n185 Ng2975 n6123 -110 1 -.names n182 Ng2917 n5079 n6124 -100 1 -.names n1140 n1646 n4305 n4794 n6128 -1011 1 -.names n1093 n1642 n4308 n4794 n6129 -1011 1 -.names n1138 n1643 n4310 n4794 n6130 -1011 1 -.names n1096 n1644 n4312 n4794 n6131 -1011 1 -.names n1155 n1640 n4314 n4794 n6132 -1011 1 -.names n1113 n1645 n4316 n4794 n6133 -1011 1 -.names n1120 n1639 n4318 n4794 n6134 -1011 1 -.names [4406] n1641 n4320 n4794 n6135 -1011 1 -.names n1238 n4176 n1239 n4177 n6174 -1111 1 -.names n3986 n5088 Ng1389 n6186 -100 1 -.names n4010 n5093 Ng1046 n6188 -100 1 -.names n1533 Ng4849 n4632 n6200 -011 1 -.names n1543 Ng4659 n4635 n6201 -011 1 -.names Ng608 n1629 n4508 n6203 -110 1 -.names Ng604 n1685 n4508 n6207 -110 1 -.names n1775 Ng2449 Pg35 n6214 -111 1 -.names n1800 Ng2315 Pg35 n6218 -111 1 -.names n1902 Ng1756 Pg35 n6234 -111 1 -.names Ng599 n1945 n4508 n6244 -110 1 -.names Ng595 n2221 n4508 n6251 -110 1 -.names Ng590 n2480 n4508 n6256 -110 1 -.names n2232 Ng6597 Pg35 n6261 -111 1 -.names n2579 Ng6653 Pg35 n6263 -111 1 -.names n2594 Ng6633 Pg35 n6268 -111 1 -.names n2652 Ng6287 Pg35 n6287 -111 1 -.names n2655 Ng6283 Pg35 n6288 -111 1 -.names n2661 Ng6275 Pg35 n6290 -111 1 -.names n2258 Ng5905 Pg35 n6299 -111 1 -.names n2695 Ng5961 Pg35 n6301 -111 1 -.names n2710 Ng5941 Pg35 n6306 -111 1 -.names n2271 Ng5559 Pg35 n6318 -111 1 -.names n2768 Ng5595 Pg35 n6325 -111 1 -.names n2817 Ng5260 Pg35 n6341 -111 1 -.names n2823 Ng5252 Pg35 n6343 -111 1 -.names n2826 Ng5248 Pg35 n6344 -111 1 -.names n2885 Ng3953 Pg35 n6364 -111 1 -.names n2891 Ng3945 Pg35 n6366 -111 1 -.names n2894 Ng3941 Pg35 n6367 -111 1 -.names n2943 Ng3602 Pg35 n6383 -111 1 -.names n2952 Ng3590 Pg35 n6386 -111 1 -.names n2961 Ng3578 Pg35 n6389 -111 1 -.names n3010 Ng3239 Pg35 n6405 -111 1 -.names n3013 Ng3235 Pg35 n6406 -111 1 -.names n3019 Ng3227 Pg35 n6408 -111 1 -.names Pg35 Ng1454 n6431 -01 1 -.names Pg35 Ng1111 n6435 -01 1 -.names n4096 [4434] Pg35 n6444 -111 1 -.names n2435 Ng32996 -0 1 -.names n2448 Ng32992 -0 1 -.names n2461 Ng32988 -0 1 -.names n4217 Ng24263 -0 1 -.names n2308 Ng33040 -0 1 -.names n2368 Ng33016 -0 1 -.names n2381 Ng33012 -0 1 -.names n2395 Ng33008 -0 1 -.names n2408 Ng33004 -0 1 -.names n2421 Ng33000 -0 1 -.names n4114 Ng25685 -0 1 -.names n4134 Ng25639 -0 1 -.names n2301 Ng33044 -0 1 -.names n2859 Ng30458 -0 1 -.names [4366] Pg34956 -1 1 -.names [4366] Pg34839 -1 1 -.names [4376] Pg34788 -1 1 -.names [4378] Pg34437 -1 1 -.names [4379] Pg34436 -1 1 -.names [4394] Pg33959 -1 1 -.names [4376] Pg33894 -1 1 -.names [4406] Pg33533 -1 1 -.names [4415] Pg31861 -1 1 -.names [4378] Pg31665 -1 1 -.names [4379] Pg31656 -1 1 -.names [4421] Pg30332 -1 1 -.names [4426] Pg29221 -1 1 -.names [4427] Pg29220 -1 1 -.names [4428] Pg29219 -1 1 -.names [4507] Pg29218 -1 1 -.names [4430] Pg29217 -1 1 -.names [4431] Pg29216 -1 1 -.names [4432] Pg29215 -1 1 -.names [4433] Pg29214 -1 1 -.names [4434] Pg29213 -1 1 -.names [4435] Pg29212 -1 1 -.names [4436] Pg29211 -1 1 -.names [4437] Pg29210 -1 1 -.names [4394] Pg28753 -1 1 -.names [4406] Pg27831 -1 1 -.names [4415] Pg25219 -1 1 -.names Pg44 Pg24185 -1 1 -.names Pg135 Pg24184 -1 1 -.names Pg134 Pg24183 -1 1 -.names Pg127 Pg24182 -1 1 -.names Pg126 Pg24181 -1 1 -.names Pg125 Pg24180 -1 1 -.names Pg124 Pg24179 -1 1 -.names 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-.names Pg6750 Pg18096 -1 1 -.names Pg6749 Pg18095 -1 1 -.names Pg6748 Pg18094 -1 1 -.names Pg6753 Pg18092 -1 1 -.names [4651] Pg8403 -1 1 -.names [4651] Pg8353 -1 1 -.names [4658] Pg8283 -1 1 -.names [4658] Pg8235 -1 1 -.names [4661] Pg8178 -1 1 -.names [4661] Pg8132 -1 1 -.end diff --git a/fpga_flow/benchmarks/Blif/MCNC_big20/seq.blif b/fpga_flow/benchmarks/Blif/MCNC_big20/seq.blif deleted file mode 100644 index 586efcbf7..000000000 --- a/fpga_flow/benchmarks/Blif/MCNC_big20/seq.blif +++ /dev/null @@ -1,3422 +0,0 @@ -.model TOP -.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_ i_8_ i_9_ i_10_ i_11_ i_12_ \ -i_13_ i_14_ i_15_ i_16_ i_17_ i_18_ i_19_ i_20_ i_21_ i_22_ i_23_ i_24_ i_25_ \ -i_26_ i_27_ i_28_ i_29_ i_30_ i_31_ i_32_ i_33_ i_34_ i_35_ i_36_ i_37_ i_38_ \ -i_39_ i_40_ -.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ o_8_ o_9_ o_10_ o_11_ o_12_ \ -o_13_ o_14_ o_15_ o_16_ o_17_ o_18_ o_19_ o_20_ o_21_ o_22_ o_23_ o_24_ o_25_ \ -o_26_ o_27_ o_28_ o_29_ o_30_ o_31_ o_32_ o_33_ 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n1710 n621 n1762 n1667 n423 n2436 n2438 -111111 1 -.names n2040 n1681 n1982 n2028 n2029 n1633 n2439 -111111 1 -.names n827 n1105 n2441 -1- 1 --0 1 -.names n1541 n2326 n870 n1978 n1450 n1703 n2441 n2439 n2440 -11111111 1 -.names n1573 n1497 n1306 n1567 n1999 n1590 n2442 -111111 1 -.names n996 n441 n702 n701 n2446 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n793 n997 n1937 n2448 -011 1 -.names n2448 n1277 n462 n989 n2447 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n1291 n1357 n1068 n827 n2449 -111- 1 -11-1 1 -.names n1051 n1054 n2450 -0- 1 --1 1 -.names n90 n1230 n1636 n1950 n2452 -0-1- 1 --01- 1 -0--1 1 --0-1 1 -.names n500 n1032 n2454 -11 1 -.names n1178 n37 n2454 n1066 n2453 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n37 n265 n1230 n2454 n2455 -11-- 1 --10- 1 -1--1 1 ---01 1 -.names n37 n91 n1346 n2454 n2456 -1-1- 1 --01- 1 -1--1 1 --0-1 1 -.names n1178 n1950 n2458 -11 1 -.names n76 n161 n1635 n2458 n2457 -00-- 1 -0-1- 1 -0--1 1 -.names n2080 n2406 n2098 n2460 -111 1 -.names n325 n2128 n1067 n164 n2461 -111- 1 -11-1 1 -.names n614 n848 n855 n1061 n2462 -1-0- 1 --00- 1 -1--1 1 --0-1 1 -.names n356 n482 n1103 n1936 n2463 --00- 1 -0-01 1 -.names n2463 n1100 n891 n2465 -11- 1 -1-1 1 -.names n2242 n1346 n192 n657 n2467 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n537 n1131 n1456 n2272 n2468 --0-1 1 -101- 1 -.names n350 n1066 n1143 n1510 n2472 --10- 1 -0-01 1 -.names n1275 n998 n2283 n1058 n2474 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n486 n1125 n1599 n1602 n2475 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n240 n619 n1124 n1585 n2476 -01-- 1 -0-1- 1 --1-1 1 ---11 1 -.names n649 n848 n1269 n1601 n2478 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names n1105 n1454 n1598 n2285 n2479 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names n508 n692 n749 n1280 n2480 -1-1- 1 --01- 1 -1--1 1 --0-1 1 -.names n1923 n608 n2287 n1346 n2481 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n2290 n265 n2242 n807 n2482 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n192 n1586 n626 n388 n2483 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n350 n370 n392 n630 n2484 -0-0- 1 --10- 1 -0--1 1 --1-1 1 -.names n462 n1587 n1279 n1220 n2485 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n1516 n657 n1270 n1245 n2486 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n14 n427 n434 n634 n2487 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names n827 n1127 n2489 -1- 1 --1 1 -.names n543 n510 n414 n2489 n2487 n2486 n2488 -111111 1 -.names n1260 n1270 n1966 n1246 n2490 -11-- 1 -1-11 1 -.names n164 n392 n458 n2490 n2491 ---11 1 -10-1 1 -.names n185 n1154 n1510 n1967 n2492 -10-- 1 --011 1 -.names n14 n169 n809 n2237 n2494 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names n2494 n1511 n2235 n2495 -11- 1 -1-1 1 -.names n2308 n307 n2228 n1332 n2496 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n1155 n1157 n1219 n2285 n2497 -001- 1 -00-1 1 -.names n2314 n1424 n1643 n1323 n2500 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n2239 n1331 n2290 n1264 n2501 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n2240 n220 n192 n172 n2502 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n2319 n1314 n1325 n184 n2503 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n486 n1206 n1470 n2272 n2504 -0-1- 1 --11- 1 -0--1 1 --1-1 1 -.names n350 n1247 n1318 n2292 n2505 -01-- 1 --11- 1 -0--1 1 ---11 1 -.names n374 n401 n657 n1127 n2506 -10-- 1 --01- 1 -1--1 1 ---11 1 -.names i_0_ i_1_ i_2_ n2507 -0-- 1 --1- 1 ---1 1 -.names n614 n1666 n2508 -11 1 -.names n1219 n1220 n165 n2509 -111 1 -.names n178 n1319 n370 n2511 -111 1 -.names n645 n316 n2512 -11 1 -.names n370 n1236 n165 n2513 -111 1 -.names n1235 n1205 n2514 -11 1 -.names n1334 n1326 n2515 -11 1 -.names n1313 n431 n2516 -11 1 -.names n638 n312 n2517 -11 1 -.names n922 n1423 n2518 -01 1 -.end diff --git a/fpga_flow/benchmarks/Blif/MCNC_big20/tseng.blif b/fpga_flow/benchmarks/Blif/MCNC_big20/tseng.blif deleted file mode 100644 index ce29cffa7..000000000 --- a/fpga_flow/benchmarks/Blif/MCNC_big20/tseng.blif +++ /dev/null @@ -1,3696 +0,0 @@ -.model top -.inputs tin_pv10_4_4_ tin_pv11_4_4_ tin_pv6_7_7_ tin_pv2_0_0_ tin_pv10_3_3_ \ -tin_pv1_2_2_ tin_pv11_3_3_ tin_pv4_3_3_ tin_pv10_2_2_ tin_pv11_2_2_ \ -tin_pv6_0_0_ tin_pv2_1_1_ tin_pv10_1_1_ tin_pv1_3_3_ preset_0_0_ tin_pv11_1_1_ \ -tin_pv4_4_4_ tin_pready_0_0_ tin_pv10_0_0_ tin_pv11_0_0_ tin_pv6_1_1_ \ -tin_pv2_2_2_ tin_pv1_4_4_ tin_pv4_5_5_ tin_pv6_2_2_ tin_pv2_3_3_ tin_pv1_5_5_ \ -tin_pv4_6_6_ tin_pv6_3_3_ tin_pv2_4_4_ tin_pv1_6_6_ pclk tin_pv4_7_7_ \ -tin_pv6_4_4_ tin_pv2_5_5_ tin_pv1_7_7_ tin_pv4_0_0_ tin_pv6_5_5_ tin_pv2_6_6_ \ -tin_pv10_7_7_ tin_pv1_0_0_ tin_pv11_7_7_ tin_pv4_1_1_ tin_pv10_6_6_ \ -tin_pv11_6_6_ tin_pv6_6_6_ tin_pv2_7_7_ preset tin_pv10_5_5_ tin_pv1_1_1_ \ -tin_pv11_5_5_ tin_pv4_2_2_ -.outputs pv14_2_2_ pv12_3_3_ pv10_4_4_ pv7_5_5_ pv3_6_6_ pv15_2_2_ pv13_3_3_ \ -pv11_4_4_ pv6_7_7_ pv2_0_0_ pv14_1_1_ pv12_2_2_ pv10_3_3_ pv9_0_0_ pv5_1_1_ \ -pv1_2_2_ pv15_1_1_ pv13_2_2_ pv11_3_3_ pv8_2_2_ pv4_3_3_ pv14_0_0_ pv12_1_1_ \ -pv10_2_2_ pv7_6_6_ pv3_7_7_ pv15_0_0_ pv13_1_1_ pv11_2_2_ pv6_0_0_ pv2_1_1_ \ -pv12_0_0_ pv10_1_1_ pv9_1_1_ pv5_2_2_ pv1_3_3_ pv13_0_0_ pv11_1_1_ pv8_3_3_ \ -pv4_4_4_ pready_0_0_ pv10_0_0_ pv7_7_7_ pv3_0_0_ pv11_0_0_ pv6_1_1_ pv2_2_2_ \ -pv9_2_2_ pv5_3_3_ pv1_4_4_ pv8_4_4_ pv4_5_5_ pv7_0_0_ pv3_1_1_ pv6_2_2_ \ -pv2_3_3_ pv9_3_3_ pv5_4_4_ pv1_5_5_ pv8_5_5_ pv4_6_6_ pv7_1_1_ pv3_2_2_ \ -pv6_3_3_ pv2_4_4_ pv9_4_4_ pv5_5_5_ pv1_6_6_ pv8_6_6_ pv4_7_7_ pv7_2_2_ \ -pv3_3_3_ pv6_4_4_ pv2_5_5_ pv14_7_7_ pv9_5_5_ pv5_6_6_ pv1_7_7_ pv15_7_7_ \ -pv8_7_7_ pv4_0_0_ pv14_6_6_ pv12_7_7_ pv7_3_3_ pv3_4_4_ pv15_6_6_ pv13_7_7_ \ -pv6_5_5_ pv2_6_6_ pdn pv14_5_5_ pv12_6_6_ pv10_7_7_ pv9_6_6_ pv5_7_7_ pv1_0_0_ \ -pv15_5_5_ pv13_6_6_ pv11_7_7_ pv8_0_0_ pv4_1_1_ pv14_4_4_ pv12_5_5_ pv10_6_6_ \ -pv7_4_4_ pv3_5_5_ pv15_4_4_ pv13_5_5_ pv11_6_6_ pv6_6_6_ pv2_7_7_ pv14_3_3_ \ -pv12_4_4_ pv10_5_5_ pv9_7_7_ pv5_0_0_ pv1_1_1_ pv15_3_3_ pv13_4_4_ pv11_5_5_ \ -pv8_1_1_ pv4_2_2_ -.latch n_n4140 n_n4142 re pclk 2 -.latch n_n3935 n_n3936 re pclk 2 -.latch n_n3444 n_n3574 re pclk 2 -.latch n_n3007 n_n3008 re pclk 2 -.latch n_n3725 n_n3726 re pclk 2 -.latch n_n3399 n_n3604 re pclk 2 -.latch n_n3143 n_n3144 re pclk 2 -.latch n_n3781 n_n3782 re pclk 2 -.latch n_n3066 n_n3067 re pclk 2 -.latch n_n3507 n_n4258 re pclk 2 -.latch n_n3224 n_n3225 re pclk 2 -.latch n_n3179 n_n3180 re pclk 2 -.latch n_n3273 n_n3274 re pclk 2 -.latch n_n3166 n_n3475 re pclk 2 -.latch n_n3686 n_n3687 re pclk 2 -.latch n_n3380 n_n3381 re pclk 2 -.latch n_n3096 n_n3098 re pclk 2 -.latch n_n4106 n_n4108 re pclk 2 -.latch n_n3496 n_n3497 re pclk 2 -.latch n_n3791 n_n3793 re pclk 2 -.latch n_n3518 n_n4316 re pclk 2 -.latch n_n4348 n_n4349 re pclk 2 -.latch n_n3028 n_n3029 re pclk 2 -.latch n_n3618 n_n3619 re pclk 2 -.latch n_n3263 n_n3264 re pclk 2 -.latch n_n3778 n_n3780 re pclk 2 -.latch n_n3227 ndn3_4 re pclk 2 -.latch n_n4113 n_n4114 re pclk 2 -.latch n_n3145 n_n3146 re pclk 2 -.latch n_n3510 n_n3511 re pclk 2 -.latch n_n3151 n_n3152 re pclk 2 -.latch n_n129 n_n3833 re pclk 2 -.latch n_n4280 n_n4282 re pclk 2 -.latch n_n3304 n_n3305 re pclk 2 -.latch n_n3309 n_n4392 re pclk 2 -.latch n_n3490 n_n4224 re pclk 2 -.latch n_n3377 n_n3198 re pclk 2 -.latch n_n3203 n_n3204 re pclk 2 -.latch n_n3023 n_n3024 re pclk 2 -.latch n_n4137 n_n4139 re pclk 2 -.latch n_n3084 ndn3_15 re pclk 2 -.latch n_n3131 n_n3133 re pclk 2 -.latch n_n4073 n_n4074 re pclk 2 -.latch n_n3269 n_n3270 re pclk 2 -.latch n_n3181 n_n3858 re pclk 2 -.latch n_n3455 n_n3456 re pclk 2 -.latch n_n3520 n_n3521 re pclk 2 -.latch n_n3080 n_n3081 re pclk 2 -.latch n_n3296 n_n4381 re pclk 2 -.latch n_n3668 n_n3670 re pclk 2 -.latch n_n4210 n_n4211 re pclk 2 -.latch n_n3076 n_n3493 re pclk 2 -.latch n_n3148 n_n3495 re pclk 2 -.latch n_n3226 n_n3916 re pclk 2 -.latch n_n3194 n_n3195 re pclk 2 -.latch n_n3523 n_n3525 re pclk 2 -.latch n_n3727 n_n3729 re pclk 2 -.latch n_n3875 n_n3876 re pclk 2 -.latch n_n3614 ndn3_5 re pclk 2 -.latch n_n3547 n_n3549 re pclk 2 -.latch n_n3488 n_n3489 re pclk 2 -.latch n_n3762 n_n3764 re pclk 2 -.latch n_n3256 n_n3281 re pclk 2 -.latch n_n124 n_n3707 re pclk 2 -.latch n_n3515 n_n3517 re pclk 2 -.latch n_n3016 n_n4160 re pclk 2 -.latch n_n3168 n_n4222 re pclk 2 -.latch n_n3011 n_n3012 re pclk 2 -.latch n_n3373 n_n4071 re pclk 2 -.latch n_n3371 n_n3372 re pclk 2 -.latch n_n3343 n_n3344 re pclk 2 -.latch n_n3018 n_n3688 re pclk 2 -.latch n_n3077 n_n3079 re pclk 2 -.latch n_n3312 n_n3313 re pclk 2 -.latch n_n3410 n_n3411 re pclk 2 -.latch n_n3230 n_n3231 re pclk 2 -.latch n_n3395 n_n3396 re pclk 2 -.latch n_n3431 n_n3432 re pclk 2 -.latch n_n3605 n_n3606 re pclk 2 -.latch n_n3732 n_n3733 re pclk 2 -.latch n_n3063 n_n3556 re pclk 2 -.latch n_n3913 n_n4040 re pclk 2 -.latch n_n3119 n_n3120 re pclk 2 -.latch n_n3220 n_n3221 re pclk 2 -.latch n_n3172 n_n3173 re pclk 2 -.latch n_n3070 n_n3851 re pclk 2 -.latch n_n3112 n_n3113 re pclk 2 -.latch n_n3241 n_n3242 re pclk 2 -.latch n_n3117 n_n3118 re pclk 2 -.latch n_n3375 n_n3376 re pclk 2 -.latch n_n4088 n_n4089 re pclk 2 -.latch n_n3043 n_n3044 re pclk 2 -.latch n_n3625 n_n3627 re pclk 2 -.latch n_n3027 n_n3035 re pclk 2 -.latch n_n3110 n_n3111 re pclk 2 -.latch n_n3320 n_n3321 re pclk 2 -.latch n_n3442 n_n3443 re pclk 2 -.latch n_n3214 n_n3215 re pclk 2 -.latch n_n3751 ndn3_10 re pclk 2 -.latch n_n4170 n_n4172 re pclk 2 -.latch n_n3982 nlc1_2 re pclk 2 -.latch n_n3589 n_n3590 re pclk 2 -.latch n_n4109 n_n4110 re pclk 2 -.latch n_n3941 nlc3_3 re pclk 2 -.latch n_n3575 n_n3576 re pclk 2 -.latch n_n4128 n_n4129 re pclk 2 -.latch n_n4186 n_n4189 re pclk 2 -.latch n_n4283 n_n4286 re pclk 2 -.latch n_n3022 n_n4383 re pclk 2 -.latch n_n3437 pdn re pclk 2 -.latch n_n3566 n_n3567 re pclk 2 -.latch n_n3032 n_n3892 re pclk 2 -.latch n_n3074 n_n3075 re pclk 2 -.latch n_n3353 n_n3354 re pclk 2 -.latch n_n3464 n_n3465 re pclk 2 -.latch n_n4321 ndn3_6 re pclk 2 -.latch n_n3616 n_n3617 re pclk 2 -.latch n_n4161 n_n4162 re pclk 2 -.latch n_n3206 n_n3207 re pclk 2 -.latch n_n4119 n_n4120 re pclk 2 -.latch n_n3064 n_n3065 re pclk 2 -.latch n_n4004 n_n4005 re pclk 2 -.latch n_n3265 n_n3266 re pclk 2 -.latch n_n3216 n_n4337 re pclk 2 -.latch n_n3599 n_n3600 re pclk 2 -.latch n_n3414 n_n3415 re pclk 2 -.latch n_n4242 n_n4243 re pclk 2 -.latch n_n3871 n_n3872 re pclk 2 -.latch n_n3647 n_n3648 re pclk 2 -.latch n_n3357 n_n3358 re pclk 2 -.latch n_n3349 n_n3350 re pclk 2 -.latch n_n3675 ndn3_7 re pclk 2 -.latch n_n3115 n_n3116 re pclk 2 -.latch n_n3582 n_n3583 re pclk 2 -.latch n_n3904 n_n3906 re pclk 2 -.latch n_n4130 n_n4131 re pclk 2 -.latch n_n3314 n_n3316 re pclk 2 -.latch n_n3060 n_n3061 re pclk 2 -.latch n_n3047 n_n3048 re pclk 2 -.latch n_n3837 n_n3886 re pclk 2 -.latch n_n3508 n_n3919 re pclk 2 -.latch n_n3127 n_n3128 re pclk 2 -.latch n_n3235 n_n3995 re pclk 2 -.latch n_n4212 n_n4213 re pclk 2 -.latch n_n3759 n_n3761 re pclk 2 -.latch n_n4218 ndn3_8 re pclk 2 -.latch n_n3251 n_n3252 re pclk 2 -.latch n_n3382 n_n4366 re pclk 2 -.latch n_n3327 n_n3328 re pclk 2 -.latch n_n3987 n_n3988 re pclk 2 -.latch n_n3347 n_n3348 re pclk 2 -.latch n_n3543 n_n3544 re pclk 2 -.latch n_n3100 n_n3101 re pclk 2 -.latch n_n4276 n_n4279 re pclk 2 -.latch n_n3895 n_n3896 re pclk 2 -.latch n_n3735 n_n3736 re pclk 2 -.latch n_n3049 n_n4251 re pclk 2 -.latch n_n3649 n_n3650 re pclk 2 -.latch n_n3306 n_n3307 re pclk 2 -.latch n_n4293 n_n4294 re pclk 2 -.latch n_n3907 n_n4334 re pclk 2 -.latch n_n3579 n_n3955 re pclk 2 -.latch n_n4163 n_n4164 re pclk 2 -.latch n_n3154 n_n3155 re pclk 2 -.latch n_n3748 n_n3749 re pclk 2 -.latch n_n3271 n_n4233 re pclk 2 -.latch n_n4346 n_n4347 re pclk 2 -.latch n_n3825 n_n3826 re pclk 2 -.latch n_n3359 n_n3360 re pclk 2 -.latch n_n3147 n_n3458 re pclk 2 -.latch n_n3092 n_n3093 re pclk 2 -.latch n_n3156 n_n3157 re pclk 2 -.latch n_n3505 n_n3506 re pclk 2 -.latch n_n3160 n_n3161 re pclk 2 -.latch n_n3318 n_n3319 re pclk 2 -.latch n_n3428 n_n3429 re pclk 2 -.latch n_n3969 n_n3971 re pclk 2 -.latch n_n3447 n_n3449 re pclk 2 -.latch n_n4081 n_n4270 re pclk 2 -.latch n_n3302 n_n4288 re pclk 2 -.latch n_n3182 n_n3183 re pclk 2 -.latch n_n3129 n_n3130 re pclk 2 -.latch n_n3430 nlak4_2 re pclk 2 -.latch n_n4046 n_n4047 re pclk 2 -.latch n_n3123 n_n3978 re pclk 2 -.latch n_n3238 n_n3239 re pclk 2 -.latch n_n3972 n_n4145 re pclk 2 -.latch n_n3889 n_n3890 re pclk 2 -.latch n_n4001 n_n4003 re pclk 2 -.latch n_n3090 n_n3091 re pclk 2 -.latch n_n3983 n_n3985 re pclk 2 -.latch n_n3325 n_n3326 re pclk 2 -.latch n_n3540 n_n4052 re pclk 2 -.latch n_n125 nsr4_2 re pclk 2 -.latch n_n3693 n_n4099 re pclk 2 -.latch n_n4373 n_n4375 re pclk 2 -.latch n_n3866 n_n4067 re pclk 2 -.latch n_n4289 n_n4290 re pclk 2 -.latch n_n3459 n_n3898 re pclk 2 -.latch n_n4121 n_n4122 re pclk 2 -.latch n_n3773 n_n3774 re pclk 2 -.latch n_n3013 n_n3014 re pclk 2 -.latch n_n4239 n_n4241 re pclk 2 -.latch n_n3950 n_n3952 re pclk 2 -.latch n_n3236 n_n3237 re pclk 2 -.latch n_n3530 n_n3968 re pclk 2 -.latch n_n3033 n_n3922 re pclk 2 -.latch n_n3550 n_n3551 re pclk 2 -.latch n_n3378 n_n3379 re pclk 2 -.latch n_n3009 n_n4275 re pclk 2 -.latch n_n3569 n_n3570 re pclk 2 -.latch n_n3853 n_n3854 re pclk 2 -.latch n_n131 n_n4057 re pclk 2 -.latch n_n3450 n_n3451 re pclk 2 -.latch n_n4036 n_n4037 re pclk 2 -.latch n_n3406 n_n3408 re pclk 2 -.latch n_n4228 n_n4229 re pclk 2 -.latch n_n3701 n_n4201 re pclk 2 -.latch n_n3338 n_n3339 re pclk 2 -.latch n_n4361 n_n4362 re pclk 2 -.latch n_n3466 n_n3483 re pclk 2 -.latch n_n3355 n_n3557 re pclk 2 -.latch n_n4184 n_n4185 re pclk 2 -.latch n_n3068 n_n3069 re pclk 2 -.latch n_n3642 n_n3643 re pclk 2 -.latch n_n3402 n_n3404 re pclk 2 -.latch n_n3056 n_n3057 re pclk 2 -.latch n_n3019 n_n3020 re pclk 2 -.latch n_n3827 n_n3828 re pclk 2 -.latch n_n3629 n_n3631 re pclk 2 -.latch n_n3137 n_n3138 re pclk 2 -.latch n_n126 nsr1_2 re pclk 2 -.latch n_n4063 n_n4065 re pclk 2 -.latch n_n3677 n_n3679 re pclk 2 -.latch n_n3285 n_n3287 re pclk 2 -.latch n_n3308 n_n4351 re pclk 2 -.latch n_n4058 n_n4059 re pclk 2 -.latch n_n3435 n_n3436 re pclk 2 -.latch n_n3635 nen3_10 re pclk 2 -.latch n_n3460 n_n3461 re pclk 2 -.latch n_n4011 n_n4012 re pclk 2 -.latch n_n3050 n_n3051 re pclk 2 -.latch n_n3072 n_n3073 re pclk 2 -.latch n_n3775 n_n3777 re pclk 2 -.latch n_n3199 n_n3709 re pclk 2 -.latch n_n3025 n_n3946 re pclk 2 -.latch n_n3058 n_n3085 re pclk 2 -.latch n_n3258 n_n3259 re pclk 2 -.latch n_n3503 n_n3504 re pclk 2 -.latch n_n130 n_n4045 re pclk 2 -.latch n_n121 n_n3954 re pclk 2 -.latch n_n3134 n_n3136 re pclk 2 -.latch n_n4370 n_n4372 re pclk 2 -.latch n_n4234 n_n4236 re pclk 2 -.latch n_n3039 n_n3040 re pclk 2 -.latch n_n3873 n_n3874 re pclk 2 -.latch n_n3998 n_n3999 re pclk 2 -.latch n_n3222 n_n3223 re pclk 2 -.latch n_n3036 ndn1_34 re pclk 2 -.latch n_n3062 n_n3743 re pclk 2 -.latch n_n3017 n_n3657 re pclk 2 -.latch n_n3212 n_n3213 re pclk 2 -.latch n_n3094 n_n3095 re pclk 2 -.latch n_n3662 n_n3663 re pclk 2 -.latch n_n3217 n_n3724 re pclk 2 -.latch n_n3037 n_n3038 re pclk 2 -.latch n_n3368 n_n3370 re pclk 2 -.latch n_n3030 n_n3624 re pclk 2 -.latch n_n3494 n_n3578 re pclk 2 -.latch n_n3711 n_n3713 re pclk 2 -.latch n_n3088 n_n3089 re pclk 2 -.latch n_n3210 n_n3211 re pclk 2 -.latch n_n3366 n_n3367 re pclk 2 -.latch n_n3433 n_n3434 re pclk 2 -.latch n_n3125 n_n3126 re pclk 2 -.latch n_n4190 n_n4192 re pclk 2 -.latch n_n4134 n_n4136 re pclk 2 -.latch n_n3052 n_n3053 re pclk 2 -.latch n_n3937 n_n3938 re pclk 2 -.latch n_n3632 n_n3769 re pclk 2 -.latch n_n4387 n_n4390 re pclk 2 -.latch n_n127 nsr3_17 re pclk 2 -.latch n_n3902 n_n3903 re pclk 2 -.latch n_n3684 n_n3658 re pclk 2 -.latch n_n3046 nrq3_11 re pclk 2 -.latch n_n3817 n_n3818 re pclk 2 -.latch n_n3374 n_n3533 re pclk 2 -.latch n_n3462 n_n3463 re pclk 2 -.latch n_n3174 n_n3175 re pclk 2 -.latch n_n3054 n_n3055 re pclk 2 -.latch n_n3200 n_n3202 re pclk 2 -.latch n_n3383 n_n3385 re pclk 2 -.latch n_n4076 n_n4077 re pclk 2 -.latch n_n3141 n_n3142 re pclk 2 -.latch n_n3289 n_n3901 re pclk 2 -.latch n_n3552 n_n3934 re pclk 2 -.latch n_n3821 n_n3823 re pclk 2 -.latch n_n3721 n_n3722 re pclk 2 -.latch n_n4307 n_n4309 re pclk 2 -.latch n_n3229 n_n4159 re pclk 2 -.latch n_n3021 n_n4330 re pclk 2 -.latch n_n3835 n_n3836 re pclk 2 -.latch n_n3469 n_n3470 re pclk 2 -.latch n_n3329 n_n3331 re pclk 2 -.latch n_n3881 n_n3883 re pclk 2 -.latch n_n3031 n_n4299 re pclk 2 -.latch n_n4156 n_n4157 re pclk 2 -.latch n_n4086 ndn3_9 re pclk 2 -.latch n_n3045 n_n3208 re pclk 2 -.latch n_n3189 n_n3190 re pclk 2 -.latch n_n4028 n_n4029 re pclk 2 -.latch n_n3041 n_n3042 re pclk 2 -.latch n_n133 nsr3_14 re pclk 2 -.latch n_n122 n_n4151 re pclk 2 -.latch n_n3187 n_n3188 re pclk 2 -.latch n_n4300 n_n4303 re pclk 2 -.latch n_n3249 n_n3250 re pclk 2 -.latch n_n3169 n_n3170 re pclk 2 -.latch n_n3757 n_n3758 re pclk 2 -.latch n_n3908 n_n3910 re pclk 2 -.latch n_n3106 n_n3108 re pclk 2 -.latch n_n3149 n_n3150 re pclk 2 -.latch n_n4317 n_n4320 re pclk 2 -.latch n_n4359 n_n4360 re pclk 2 -.latch n_n4245 n_n4247 re pclk 2 -.latch n_n4196 n_n4199 re pclk 2 -.latch n_n3964 n_n3966 re pclk 2 -.latch n_n3184 n_n3766 re pclk 2 -.latch n_n3010 n_n4021 re pclk 2 -.latch n_n3122 n_n4062 re pclk 2 -.latch n_n3512 n_n3514 re pclk 2 -.latch n_n3571 n_n3572 re pclk 2 -.latch n_n4165 n_n4166 re pclk 2 -.latch n_n3519 n_n3976 re pclk 2 -.latch n_n3392 n_n3394 re pclk 2 -.latch n_n4094 n_n4095 re pclk 2 -.latch n_n3862 n_n3863 re pclk 2 -.latch n_n3719 n_n3720 re pclk 2 -.latch n_n3810 ngfdn_3 re pclk 2 -.latch n_n3755 n_n3756 re pclk 2 -.latch n_n3665 n_n3667 re pclk 2 -.latch n_n3340 n_n3342 re pclk 2 -.latch n_n3528 n_n3529 re pclk 2 -.latch n_n4207 n_n4209 re pclk 2 -.latch n_n3585 n_n4324 re pclk 2 -.latch n_n3336 n_n3337 re pclk 2 -.latch n_n3026 n_n4227 re pclk 2 -.latch n_n4152 n_n4153 re pclk 2 -.latch n_n128 n_n3831 re pclk 2 -.latch n_n3232 n_n3233 re pclk 2 -.latch n_n4262 n_n4263 re pclk 2 -.latch n_n3412 n_n3413 re pclk 2 -.latch n_n3015 n_n4182 re pclk 2 -.latch n_n3526 n_n3841 re pclk 2 -.latch n_n3440 n_n3441 re pclk 2 -.latch n_n3140 n_n4026 re pclk 2 -.latch n_n4339 n_n4342 re pclk 2 -.latch n_n4100 n_n4102 re pclk 2 -.latch n_n3275 n_n3277 re pclk 2 -.latch n_n4178 n_n4180 re pclk 2 -.latch n_n3877 n_n3878 re pclk 2 -.latch n_n3538 n_n3931 re pclk 2 -.latch n_n3680 n_n3845 re pclk 2 -.latch n_n3104 n_n3865 re pclk 2 -.latch n_n3484 n_n3486 re pclk 2 -.latch n_n3473 n_n4056 re pclk 2 -.latch n_n3673 n_n3674 re pclk 2 -.latch n_n3592 n_n3959 re pclk 2 -.latch n_n3607 n_n3608 re pclk 2 -.latch n_n3292 n_n4080 re pclk 2 -.latch n_n4017 n_n4018 re pclk 2 -.latch n_n4352 n_n4354 re pclk 2 -.latch n_n3796 n_n3797 re pclk 2 -.latch n_n3737 n_n3739 re pclk 2 -.latch n_n3644 n_n3646 re pclk 2 -.latch n_n3059 n_n3099 re pclk 2 -.latch n_n3535 n_n3537 re pclk 2 -.latch n_n3804 n_n3806 re pclk 2 -.latch n_n3086 n_n3087 re pclk 2 -.latch n_n4104 n_n4105 re pclk 2 -.latch n_n3261 n_n3262 re pclk 2 -.latch n_n4124 n_n4125 re pclk 2 -.latch n_n3813 n_n3814 re pclk 2 -.latch n_n132 n_n4093 re pclk 2 -.latch n_n123 nsr3_3 re pclk 2 -.names n_n3358 n_n4153 pv14_2_2_ -11 1 -.names n_n3631 n_n3367 pv12_3_3_ -11 1 -.names tin_pv10_4_4_ n_n4136 n_n3042 pv10_4_4_ --11 1 -1-0 1 -.names n_n3130 n_n3679 pv7_5_5_ -11 1 -.names n_n3252 n_n3057 pv3_6_6_ -11 1 -.names n_n3113 n_n4037 pv15_2_2_ -11 1 -.names n_n3600 n_n3404 pv13_3_3_ -11 1 -.names tin_pv11_4_4_ n_n4120 n_n3966 pv11_4_4_ -10- 1 --11 1 -.names tin_pv6_7_7_ n_n4164 n_n3370 pv6_7_7_ -10- 1 --11 1 -.names tin_pv2_0_0_ n_n3211 n_n3910 pv2_0_0_ -10- 1 --11 1 -.names n_n3012 n_n3038 pv14_1_1_ -11 1 -.names n_n3067 n_n3576 pv12_2_2_ -11 1 -.names tin_pv10_3_3_ n_n4129 n_n3213 pv10_3_3_ -10- 1 --11 1 -.names n_n3128 n_n3890 pv9_0_0_ -11 1 -.names n_n3443 n_n3287 pv5_1_1_ -11 1 -.names tin_pv1_2_2_ n_n3470 n_n3537 pv1_2_2_ -10- 1 --11 1 -.names n_n3606 n_n3108 pv15_1_1_ -11 1 -.names n_n3379 n_n3463 pv13_2_2_ -11 1 -.names tin_pv11_3_3_ n_n3432 n_n3583 pv11_3_3_ -10- 1 --11 1 -.names n_n3456 n_n3055 pv8_2_2_ -11 1 -.names tin_pv4_3_3_ n_n3489 n_n4309 pv4_3_3_ -10- 1 --11 1 -.names n_n3761 n_n3903 pv14_0_0_ -11 1 -.names n_n3264 n_n4390 pv12_1_1_ -11 1 -.names tin_pv10_2_2_ n_n3549 n_n3065 pv10_2_2_ --11 1 -1-0 1 -.names n_n3670 n_n3617 pv7_6_6_ -11 1 -.names n_n3590 n_n4102 pv3_7_7_ -11 1 -.names n_n4003 n_n3188 pv15_0_0_ -11 1 -.names n_n3221 n_n3150 pv13_1_1_ -11 1 -.names tin_pv11_2_2_ n_n3152 n_n3823 pv11_2_2_ -10- 1 --11 1 -.names tin_pv6_0_0_ n_n3029 n_n3506 pv6_0_0_ -10- 1 --11 1 -.names tin_pv2_1_1_ n_n3999 n_n3646 pv2_1_1_ -10- 1 --11 1 -.names n_n3098 n_n3339 pv12_0_0_ -11 1 -.names tin_pv10_1_1_ n_n3270 n_n3872 pv10_1_1_ --11 1 -1-0 1 -.names n_n3024 n_n3044 pv9_1_1_ -11 1 -.names n_n4286 n_n3350 pv5_2_2_ -11 1 -.names tin_pv1_3_3_ n_n3441 n_n4180 pv1_3_3_ -10- 1 --11 1 -.names n_n3061 n_n3434 pv13_0_0_ -11 1 -.names tin_pv11_1_1_ n_n4142 n_n4185 pv11_1_1_ --11 1 -1-0 1 -.names n_n3146 n_n3091 pv8_3_3_ -11 1 -.names tin_pv4_4_4_ n_n3627 n_n4110 pv4_4_4_ --11 1 -1-0 1 -.names tin_pready_0_0_ n_n4108 n_n3354 pready_0_0_ -10- 1 --11 1 -.names tin_pv10_0_0_ n_n4282 n_n4209 pv10_0_0_ -10- 1 --11 1 -.names n_n3136 n_n4077 pv7_7_7_ -11 1 -.names n_n3173 n_n3828 pv3_0_0_ -11 1 -.names tin_pv11_0_0_ n_n3514 n_n3233 pv11_0_0_ --11 1 -1-0 1 -.names tin_pv6_1_1_ n_n3144 n_n3952 pv6_1_1_ -10- 1 --11 1 -.names tin_pv2_2_2_ n_n3202 n_n4354 pv2_2_2_ --11 1 -1-0 1 -.names n_n3736 n_n3157 pv9_2_2_ -11 1 -.names n_n3321 n_n4236 pv5_3_3_ -11 1 -.names tin_pv1_4_4_ n_n3863 n_n3806 pv1_4_4_ -10- 1 --11 1 -.names n_n3344 n_n3095 pv8_4_4_ -11 1 -.names tin_pv4_5_5_ n_n3733 n_n3087 pv4_5_5_ --11 1 -1-0 1 -.names n_n3161 n_n3069 pv7_0_0_ -11 1 -.names n_n3048 n_n3461 pv3_1_1_ -11 1 -.names tin_pv6_2_2_ n_n3307 n_n3138 pv6_2_2_ -10- 1 --11 1 -.names tin_pv2_3_3_ n_n3465 n_n3874 pv2_3_3_ --11 1 -1-0 1 -.names n_n3906 n_n3749 pv9_3_3_ -11 1 -.names n_n3793 n_n4213 pv5_4_4_ -11 1 -.names tin_pv1_5_5_ n_n3313 n_n3101 pv1_5_5_ --11 1 -1-0 1 -.names n_n3116 n_n3331 pv8_5_5_ -11 1 -.names tin_pv4_6_6_ n_n3774 n_n3413 pv4_6_6_ -10- 1 --11 1 -.names n_n3415 n_n3971 pv7_1_1_ -11 1 -.names n_n3190 n_n3739 pv3_2_2_ -11 1 -.names tin_pv6_3_3_ n_n3204 n_n3486 pv6_3_3_ -10- 1 --11 1 -.names tin_pv2_4_4_ n_n3133 n_n3643 pv2_4_4_ --11 1 -1-0 1 -.names n_n3687 n_n3650 pv9_4_4_ -11 1 -.names n_n3266 n_n3408 pv5_5_5_ -11 1 -.names tin_pv1_6_6_ n_n3118 n_n4018 pv1_6_6_ --11 1 -1-0 1 -.names n_n3180 n_n3223 pv8_6_6_ -11 1 -.names tin_pv4_7_7_ n_n4114 n_n4166 pv4_7_7_ -10- 1 --11 1 -.names n_n3497 n_n4105 pv7_2_2_ -11 1 -.names n_n3274 n_n4342 pv3_3_3_ -11 1 -.names tin_pv6_4_4_ n_n3093 n_n4065 pv6_4_4_ -10- 1 --11 1 -.names tin_pv2_5_5_ n_n3780 n_n4059 pv2_5_5_ --11 1 -1-0 1 -.names n_n3449 n_n4241 pv14_7_7_ -11 1 -.names n_n3985 n_n4290 pv9_5_5_ -11 1 -.names n_n3567 n_n3237 pv5_6_6_ -11 1 -.names tin_pv1_7_7_ n_n3544 n_n4199 pv1_7_7_ -10- 1 --11 1 -.names n_n3079 n_n3648 pv15_7_7_ -11 1 -.names n_n3525 n_n3529 pv8_7_7_ -11 1 -.names tin_pv4_0_0_ n_n3517 n_n3826 pv4_0_0_ --11 1 -1-0 1 -.names n_n3713 n_n3262 pv14_6_6_ -11 1 -.names n_n3764 n_n3720 pv12_7_7_ -11 1 -.names n_n3411 n_n4303 pv7_3_3_ -11 1 -.names n_n3729 n_n4162 pv3_4_4_ -11 1 -.names n_n4375 n_n3020 pv15_6_6_ -11 1 -.names n_n3372 n_n3394 pv13_7_7_ -11 1 -.names tin_pv6_5_5_ n_n4189 n_n3348 pv6_5_5_ --11 1 -1-0 1 -.names tin_pv2_6_6_ n_n3120 n_n3385 pv2_6_6_ -10- 1 --11 1 -.names n_n3008 n_n3663 pv14_5_5_ -11 1 -.names n_n3782 n_n3896 pv12_6_6_ -11 1 -.names tin_pv10_7_7_ n_n3225 n_n3521 pv10_7_7_ --11 1 -1-0 1 -.names n_n4243 n_n3239 pv9_6_6_ -11 1 -.names n_n3111 n_n4005 pv5_7_7_ -11 1 -.names tin_pv1_0_0_ n_n3551 n_n4192 pv1_0_0_ -10- 1 --11 1 -.names n_n3277 n_n3674 pv15_5_5_ -11 1 -.names n_n3155 n_n3797 pv13_6_6_ -11 1 -.names tin_pv11_7_7_ n_n3376 n_n3360 pv11_7_7_ --11 1 -1-0 1 -.names n_n3014 n_n4320 pv8_0_0_ -11 1 -.names tin_pv4_1_1_ n_n4089 n_n3722 pv4_1_1_ -10- 1 --11 1 -.names n_n3326 n_n3089 pv14_4_4_ -11 1 -.names n_n3619 n_n3337 pv12_5_5_ -11 1 -.names tin_pv10_6_6_ n_n3570 n_n3342 pv10_6_6_ -10- 1 --11 1 -.names n_n3073 n_n3053 pv7_4_4_ -11 1 -.names n_n3436 n_n3142 pv3_5_5_ -11 1 -.names n_n3305 n_n3667 pv15_4_4_ -11 1 -.names n_n4139 n_n3777 pv13_5_5_ -11 1 -.names tin_pv11_6_6_ n_n4279 n_n3504 pv11_6_6_ --11 1 -1-0 1 -.names tin_pv6_6_6_ n_n3429 n_n3836 pv6_6_6_ --11 1 -1-0 1 -.names tin_pv2_7_7_ n_n4131 n_n3126 pv2_7_7_ -10- 1 --11 1 -.names n_n3396 n_n3316 pv14_3_3_ -11 1 -.names n_n3231 n_n3175 pv12_4_4_ -11 1 -.names tin_pv10_5_5_ n_n3381 n_n4247 pv10_5_5_ -10- 1 --11 1 -.names n_n3319 n_n3040 pv9_7_7_ -11 1 -.names n_n3195 n_n3572 pv5_0_0_ -11 1 -.names tin_pv1_1_1_ n_n3215 n_n3183 pv1_1_1_ -10- 1 --11 1 -.names n_n4172 n_n3051 pv15_3_3_ -11 1 -.names n_n3075 n_n3758 pv13_4_4_ -11 1 -.names tin_pv11_5_5_ n_n3081 n_n3207 pv11_5_5_ -10- 1 --11 1 -.names n_n3938 n_n3883 pv8_1_1_ -11 1 -.names tin_pv4_2_2_ n_n4347 n_n4372 pv4_2_2_ -10- 1 --11 1 -.names n_n3724 n_n3830 [2275] [6252] n_n4140 ---1- 1 -10-1 1 -.names pv11_1_1_ [988] [2270] n_n3935 ---1 1 -11- 1 -.names [2261] [2262] [2263] n_n3444 -1-- 1 --1- 1 ---1 1 -.names n_n3035 n_n4157 [894] [2259] n_n3007 ----1 1 -111- 1 -.names [2240] [2241] [2242] n_n3725 -1-- 1 --1- 1 ---1 1 -.names preset [1016] n_n3399 -01 1 -.names preset pdn n_n3144 nrq1_3 n_n3143 -0-1- 1 -00-1 1 -.names preset pdn n_n3782 nrq1_3 n_n3781 -0-1- 1 -00-1 1 -.names preset pdn n_n3067 nrq1_3 n_n3066 -0-1- 1 -00-1 1 -.names pv10_3_3_ [992] [2226] n_n3507 ---1 1 -11- 1 -.names n_n4360 [894] [2224] n_n3224 ---1 1 -11- 1 -.names preset pdn n_n3180 nrq1_3 n_n3179 -0-1- 1 -00-1 1 -.names preset pdn n_n3274 nrq1_3 n_n3273 -0-1- 1 -00-1 1 -.names n_n3475 [916] [934] [1019] n_n3166 -1-1- 1 -11-1 1 -01-0 1 -.names n_n3458 [894] [2202] n_n3686 ---1 1 -11- 1 -.names preset pdn n_n3381 nrq1_3 n_n3380 -0-1- 1 -00-1 1 -.names n_n3688 n_n3624 [894] [2198] n_n3096 ----1 1 -111- 1 -.names preset [1020] n_n4106 -01 1 -.names n_n3901 [894] n_n4367 [2195] n_n3496 ----1 1 -111- 1 -.names n_n3916 [894] [1096] [2192] n_n3791 ----1 1 -111- 1 -010- 1 -.names n_n4015 [1004] [2166] n_n3518 ---1 1 -11- 1 -.names pv6_0_0_ [990] [2162] n_n4348 ---1 1 -11- 1 -.names preset pdn n_n3029 nrq1_3 n_n3028 -0-1- 1 -00-1 1 -.names preset pdn n_n3619 nrq1_3 n_n3618 -0-1- 1 -00-1 1 -.names preset pdn n_n3264 nrq1_3 n_n3263 -0-1- 1 -00-1 1 -.names n_n4288 [894] [2153] [6259] n_n3778 ---1- 1 -11-- 1 --1-1 1 -.names preset ngfdn_3 [1021] n_n3227 -001 1 -.names preset pdn n_n4114 nrq1_3 n_n4113 -0-1- 1 -00-1 1 -.names preset pdn n_n3146 nrq1_3 n_n3145 -0-1- 1 -00-1 1 -.names pv1_5_5_ [994] [2141] n_n3510 ---1 1 -11- 1 -.names preset pdn n_n3152 nrq1_3 n_n3151 -0-1- 1 -00-1 1 -.names preset n_n3833 n_n3563 [1022] n_n129 -1--- 1 --1-1 1 ---00 1 -.names preset pdn n_n4282 nrq1_3 n_n4280 -0-1- 1 -00-1 1 -.names preset pdn n_n3305 nrq1_3 n_n3304 -0-1- 1 -00-1 1 -.names [1002] n_n3363 [1128] [2126] n_n3309 ----1 1 -111- 1 -100- 1 -.names pv4_5_5_ [997] [2122] n_n3490 ---1 1 -11- 1 -.names preset [1137] [1136] [6290] n_n3377 -00-1 1 -0-01 1 -.names preset pdn n_n3204 nrq1_3 n_n3203 -0-1- 1 -00-1 1 -.names preset pdn n_n3024 nrq1_3 n_n3023 -0-1- 1 -00-1 1 -.names preset pdn n_n4139 nrq1_3 n_n4137 -0-1- 1 -00-1 1 -.names preset ndn3_15 ngfdn_3 n_n3084 -010 1 -.names n_n3458 [894] [2051] [6291] n_n3131 ---1- 1 -11-- 1 --1-1 1 -.names n_n3810 n_n4345 [1122] [2029] n_n4073 ----1 1 -111- 1 -100- 1 -.names n_n3743 [894] [2027] n_n3269 ---1 1 -11- 1 -.names pv1_2_2_ [994] [2023] n_n3181 ---1 1 -11- 1 -.names preset pdn n_n3456 nrq1_3 n_n3455 -0-1- 1 -00-1 1 -.names preset pdn n_n3521 nrq1_3 n_n3520 -0-1- 1 -00-1 1 -.names preset pdn n_n3081 nrq1_3 n_n3080 -0-1- 1 -00-1 1 -.names [1006] [2007] [2009] [6300] n_n3296 --1-- 1 -1-1- 1 -1--1 1 -.names n_n3475 [894] n_n4367 [2005] n_n3668 ----1 1 -111- 1 -.names pv11_2_2_ [988] [2000] n_n4210 ---1 1 -11- 1 -.names n_n4045 n_n4367 [6299] [6302] n_n3076 -11-1 1 -1-01 1 -.names n_n4015 [1002] [1998] n_n3148 ---1 1 -11- 1 -.names [1004] n_n4345 [1122] [1996] n_n3226 ----1 1 -111- 1 -100- 1 -.names preset pdn n_n3195 nrq1_3 n_n3194 -0-1- 1 -00-1 1 -.names n_n3242 [894] [1992] n_n3523 ---1 1 -11- 1 -.names n_n3916 [894] [1990] n_n3727 ---1 1 -11- 1 -.names pv10_4_4_ [992] [1986] n_n3875 ---1 1 -11- 1 -.names preset ndn3_4 ndn3_5 ngfdn_3 n_n3614 -01-0 1 -0-10 1 -.names n_n3946 [894] [1984] n_n3547 ---1 1 -11- 1 -.names preset pdn n_n3489 nrq1_3 n_n3488 -0-1- 1 -00-1 1 -.names n_n3242 n_n3170 [894] [1980] n_n3762 ----1 1 -111- 1 -.names pv2_3_3_ [999] [1976] n_n3256 ---1 1 -11- 1 -.names preset nak3_17 [1971] n_n124 -1-- 1 --1- 1 ---1 1 -.names n_n4159 [894] [1969] n_n3515 ---1 1 -11- 1 -.names pv4_1_1_ [997] [1965] n_n3016 ---1 1 -11- 1 -.names [1004] n_n3363 [1128] [1963] n_n3168 ----1 1 -111- 1 -100- 1 -.names n_n3936 n_n3099 [894] [1961] n_n3011 ----1 1 -111- 1 -.names pv6_5_5_ [990] [1957] n_n3373 ---1 1 -11- 1 -.names preset pdn n_n3372 nrq1_3 n_n3371 -0-1- 1 -00-1 1 -.names n_n4074 [894] [1953] n_n3343 ---1 1 -11- 1 -.names n_n3810 n_n3975 n_n3974 [1949] n_n3018 ----1 1 -101- 1 -110- 1 -.names n_n4233 [894] [1946] [6303] n_n3077 ---1- 1 -11-- 1 --1-1 1 -.names n_n3035 n_n4157 [894] [1944] n_n3312 ----1 1 -111- 1 -.names preset pdn n_n3411 nrq1_3 n_n3410 -0-1- 1 -00-1 1 -.names n_n4074 n_n3578 [894] [1940] n_n3230 ----1 1 -111- 1 -.names preset pdn n_n3396 nrq1_3 n_n3395 -0-1- 1 -00-1 1 -.names preset pdn n_n3432 nrq1_3 n_n3431 -0-1- 1 -00-1 1 -.names preset pdn n_n3606 nrq1_3 n_n3605 -0-1- 1 -00-1 1 -.names n_n4224 [894] [1932] n_n3732 ---1 1 -11- 1 -.names pv11_6_6_ [988] [1928] n_n3063 ---1 1 -11- 1 -.names [1925] [1926] [1927] n_n3913 -1-- 1 --1- 1 ---1 1 -.names preset pdn n_n3120 nrq1_3 n_n3119 -0-1- 1 -00-1 1 -.names n_n4222 [894] [1921] n_n3220 ---1 1 -11- 1 -.names n_n3976 [894] [1919] n_n3172 ---1 1 -11- 1 -.names preset n_n3851 n_n3852 [936] n_n3070 -01-1 1 -0-10 1 -.names n_n3495 [894] [1914] [6310] n_n3112 ---1- 1 -11-- 1 --1-1 1 -.names [1884] [1885] n_n3241 -1- 1 --1 1 -.names n_n3556 n_n4122 [894] [1882] n_n3117 ----1 1 -111- 1 -.names n_n3483 n_n3830 [1881] [6252] n_n3375 ---1- 1 -10-1 1 -.names preset pdn n_n4089 nrq1_3 n_n4088 -0-1- 1 -00-1 1 -.names n_n4392 [894] [1876] n_n3043 ---1 1 -11- 1 -.names n_n4330 [894] [1874] n_n3625 ---1 1 -11- 1 -.names pv11_5_5_ [988] [1870] n_n3027 ---1 1 -11- 1 -.names n_n3841 [894] [1078] [1868] n_n3110 ----1 1 -111- 1 -010- 1 -.names preset pdn n_n3321 nrq1_3 n_n3320 -0-1- 1 -00-1 1 -.names preset pdn n_n3443 nrq1_3 n_n3442 -0-1- 1 -00-1 1 -.names preset pdn n_n3215 nrq1_3 n_n3214 -0-1- 1 -00-1 1 -.names preset ndn3_10 nen3_10 ngfdn_3 n_n3751 -01-0 1 -0-10 1 -.names n_n4351 [894] [1859] [6322] n_n4170 ---1- 1 -11-- 1 --1-1 1 -.names preset pdn [1028] n_n3982 -001 1 -.names preset pdn n_n3590 nrq1_3 n_n3589 -0-1- 1 -00-1 1 -.names preset pdn n_n4110 nrq1_3 n_n4109 -0-1- 1 -00-1 1 -.names nlc3_3 [944] nrq3_2 [6324] n_n3941 -10-- 1 --011 1 -.names n_n4211 n_n3657 [894] [1853] n_n3575 ----1 1 -111- 1 -.names preset pdn n_n4129 nrq1_3 n_n4128 -0-1- 1 -00-1 1 -.names n_n4071 [894] [1849] n_n4186 ---1 1 -11- 1 -.names [894] n_n4116 [1847] n_n4283 ---1 1 -11- 1 -.names pv4_2_2_ [997] [1843] n_n3022 ---1 1 -11- 1 -.names preset pdn nrq1_3 n_n3437 -001 1 -.names preset pdn n_n3567 nrq1_3 n_n3566 -0-1- 1 -00-1 1 -.names pv6_6_6_ [990] [1837] n_n3032 ---1 1 -11- 1 -.names preset pdn n_n3075 nrq1_3 n_n3074 -0-1- 1 -00-1 1 -.names preset pdn nrq1_3 [1833] n_n3353 ----1 1 -001- 1 -.names n_n4351 [894] [1830] [6322] n_n3464 ---1- 1 -11-- 1 --1-1 1 -.names preset ndn3_5 ndn3_6 ngfdn_3 n_n4321 -01-0 1 -0-10 1 -.names preset pdn n_n3617 nrq1_3 n_n3616 -0-1- 1 -00-1 1 -.names preset pdn n_n4162 nrq1_3 n_n4161 -0-1- 1 -00-1 1 -.names n_n4012 n_n3830 [1825] [6252] n_n3206 ---1- 1 -10-1 1 -.names preset pdn n_n4120 nrq1_3 n_n4119 -0-1- 1 -00-1 1 -.names preset pdn n_n3065 nrq1_3 n_n3064 -0-1- 1 -00-1 1 -.names preset pdn n_n4005 nrq1_3 n_n4004 -0-1- 1 -00-1 1 -.names preset pdn n_n3266 nrq1_3 n_n3265 -0-1- 1 -00-1 1 -.names pv6_7_7_ [990] [1812] n_n3216 ---1 1 -11- 1 -.names preset pdn n_n3600 nrq1_3 n_n3599 -0-1- 1 -00-1 1 -.names preset pdn n_n3415 nrq1_3 n_n3414 -0-1- 1 -00-1 1 -.names n_n4095 [894] [1806] n_n4242 ---1 1 -11- 1 -.names preset pdn n_n3872 nrq1_3 n_n3871 -0-1- 1 -00-1 1 -.names preset pdn n_n3648 nrq1_3 n_n3647 -0-1- 1 -00-1 1 -.names n_n4211 n_n3657 [894] [1800] n_n3357 ----1 1 -111- 1 -.names preset pdn n_n3350 nrq1_3 n_n3349 -0-1- 1 -00-1 1 -.names preset ndn3_6 ndn3_7 ngfdn_3 n_n3675 -01-0 1 -0-10 1 -.names preset pdn n_n3116 nrq1_3 n_n3115 -0-1- 1 -00-1 1 -.names n_n3766 n_n3830 [1795] [6252] n_n3582 ---1- 1 -10-1 1 -.names n_n4351 [894] [1792] n_n3904 ---1 1 -11- 1 -.names preset pdn n_n4131 nrq1_3 n_n4130 -0-1- 1 -00-1 1 -.names n_n3085 n_n3250 [894] [1788] n_n3314 ----1 1 -111- 1 -.names n_n3976 [894] [1786] n_n3060 ---1 1 -11- 1 -.names n_n4222 [894] [1784] n_n3047 ---1 1 -11- 1 -.names pv1_4_4_ [994] [1780] n_n3837 ---1 1 -11- 1 -.names pv1_6_6_ [994] [1776] n_n3508 ---1 1 -11- 1 -.names n_n3608 [894] [1774] n_n3127 ---1 1 -11- 1 -.names [1771] [1772] [1773] n_n3235 -1-- 1 --1- 1 ---1 1 -.names preset pdn n_n4213 nrq1_3 n_n4212 -0-1- 1 -00-1 1 -.names n_n3688 n_n3624 [894] [1767] n_n3759 ----1 1 -111- 1 -.names preset ndn3_7 ndn3_8 ngfdn_3 n_n4218 -01-0 1 -0-10 1 -.names preset pdn n_n3252 nrq1_3 n_n3251 -0-1- 1 -00-1 1 -.names n_n4366 [916] [934] [1034] n_n3382 -1-1- 1 -11-1 1 -01-0 1 -.names pv2_1_1_ [999] [1755] n_n3327 ---1 1 -11- 1 -.names [1752] [1753] [1754] n_n3987 -1-- 1 --1- 1 ---1 1 -.names preset pdn n_n3348 nrq1_3 n_n3347 -0-1- 1 -00-1 1 -.names preset pdn n_n3544 nrq1_3 n_n3543 -0-1- 1 -00-1 1 -.names preset pdn n_n3101 nrq1_3 n_n3100 -0-1- 1 -00-1 1 -.names n_n4334 n_n3830 [1745] [6252] n_n4276 ---1- 1 -10-1 1 -.names n_n3556 n_n4122 [894] [1742] n_n3895 ----1 1 -111- 1 -.names n_n3495 [894] [1740] n_n3735 ---1 1 -11- 1 -.names pv4_6_6_ [997] [1736] n_n3049 ---1 1 -11- 1 -.names preset pdn n_n3650 nrq1_3 n_n3649 -0-1- 1 -00-1 1 -.names preset pdn n_n3307 nrq1_3 n_n3306 -0-1- 1 -00-1 1 -.names pv1_3_3_ [994] [1728] n_n4293 ---1 1 -11- 1 -.names n_n4334 [1014] [982] [1724] n_n3907 -01-- 1 -1-1- 1 -1--1 1 -.names [1006] [1716] [1719] [6332] n_n3579 --1-- 1 -1-1- 1 -1--1 1 -.names preset pdn n_n4164 nrq1_3 n_n4163 -0-1- 1 -00-1 1 -.names n_n4145 [894] [1711] n_n3154 ---1 1 -11- 1 -.names preset pdn n_n3749 nrq1_3 n_n3748 -0-1- 1 -00-1 1 -.names [1707] [1708] n_n3271 -1- 1 --1 1 -.names preset pdn n_n4347 nrq1_3 n_n4346 -0-1- 1 -00-1 1 -.names preset pdn n_n3826 nrq1_3 n_n3825 -0-1- 1 -00-1 1 -.names preset pdn n_n3360 nrq1_3 n_n3359 -0-1- 1 -00-1 1 -.names [1002] n_n4345 [1122] [1699] n_n3147 ----1 1 -111- 1 -100- 1 -.names preset pdn n_n3093 nrq1_3 n_n3092 -0-1- 1 -00-1 1 -.names preset pdn n_n3157 nrq1_3 n_n3156 -0-1- 1 -00-1 1 -.names n_n4349 [894] [1693] n_n3505 ---1 1 -11- 1 -.names preset pdn n_n3161 nrq1_3 n_n3160 -0-1- 1 -00-1 1 -.names n_n4233 [894] [1689] n_n3318 ---1 1 -11- 1 -.names n_n3892 [894] [1687] n_n3428 ---1 1 -11- 1 -.names n_n4125 [894] n_n4367 [1686] n_n3969 ----1 1 -111- 1 -.names n_n3242 n_n3170 [894] [1683] n_n3447 ----1 1 -111- 1 -.names pv4_7_7_ [997] [1679] n_n4081 ---1 1 -11- 1 -.names [1002] n_n4158 [1673] n_n3302 ---1 1 -11- 1 -.names n_n3936 n_n3099 [894] [1671] n_n3182 ----1 1 -111- 1 -.names preset pdn n_n3130 nrq1_3 n_n3129 -0-1- 1 -00-1 1 -.names preset nsr4_2 [973] n_n3430 -010 1 -.names preset n_n4047 n_n4126 [1659] n_n4046 ----1 1 -010- 1 -.names pv2_2_2_ [999] [1655] n_n3123 ---1 1 -11- 1 -.names preset pdn n_n3239 nrq1_3 n_n3238 -0-1- 1 -00-1 1 -.names [1647] [1648] n_n3972 -1- 1 --1 1 -.names preset pdn n_n3890 nrq1_3 n_n3889 -0-1- 1 -00-1 1 -.names n_n3608 [894] [1642] [6272] n_n4001 ---1- 1 -11-- 1 --1-1 1 -.names n_n3085 [894] [1640] n_n3090 ---1 1 -11- 1 -.names n_n4288 [894] [1638] n_n3983 ---1 1 -11- 1 -.names preset pdn n_n3326 nrq1_3 n_n3325 -0-1- 1 -00-1 1 -.names [1006] [1630] [1633] [6337] n_n3540 --1-- 1 -1-1- 1 -1--1 1 -.names preset pdn nsr4_2 [973] n_n125 -1--- 1 --1-- 1 ---11 1 -.names [1006] [1621] [1623] [6338] n_n3693 --1-- 1 -1-1- 1 -1--1 1 -.names preset pdn n_n4375 nrq1_3 n_n4373 -0-1- 1 -00-1 1 -.names preset nak3_17 [1041] n_n3866 -001 1 -.names preset pdn n_n4290 nrq1_3 n_n4289 -0-1- 1 -00-1 1 -.names [1004] n_n4158 [1614] n_n3459 ---1 1 -11- 1 -.names [1612] [1613] n_n4121 -1- 1 --1 1 -.names preset pdn n_n3774 nrq1_3 n_n3773 -0-1- 1 -00-1 1 -.names preset pdn n_n3014 nrq1_3 n_n3013 -0-1- 1 -00-1 1 -.names preset pdn n_n4241 nrq1_3 n_n4239 -0-1- 1 -00-1 1 -.names n_n4201 [894] [1604] n_n3950 ---1 1 -11- 1 -.names n_n4145 [894] [1075] [1602] n_n3236 ----1 1 -111- 1 -010- 1 -.names pv6_2_2_ [990] [1598] n_n3530 ---1 1 -11- 1 -.names pv6_4_4_ [990] [1594] n_n3033 ---1 1 -11- 1 -.names preset pdn n_n3551 nrq1_3 n_n3550 -0-1- 1 -00-1 1 -.names preset pdn n_n3379 nrq1_3 n_n3378 -0-1- 1 -00-1 1 -.names n_n4275 [1042] [1580] n_n3009 ---1 1 -11- 1 -.names preset pdn n_n3570 nrq1_3 n_n3569 -0-1- 1 -00-1 1 -.names pv2_5_5_ [999] [1574] n_n3853 ---1 1 -11- 1 -.names [1565] [6350] n_n131 -1- 1 --1 1 -.names pv2_7_7_ [999] [1561] n_n3450 ---1 1 -11- 1 -.names preset pdn n_n4037 nrq1_3 n_n4036 -0-1- 1 -00-1 1 -.names n_n3898 [894] [1076] [1557] n_n3406 ----1 1 -111- 1 -010- 1 -.names [1551] [1552] n_n4228 -1- 1 --1 1 -.names pv6_1_1_ [990] [1547] n_n3701 ---1 1 -11- 1 -.names preset pdn n_n3339 nrq1_3 n_n3338 -0-1- 1 -00-1 1 -.names pv10_5_5_ [992] [1541] n_n4361 ---1 1 -11- 1 -.names n_n4334 n_n3483 [1014] [1538] n_n3466 ----1 1 -101- 1 -.names preset n_n4099 [1119] [6349] n_n3355 -0011 1 -0101 1 -.names preset pdn n_n4185 nrq1_3 n_n4184 -0-1- 1 -00-1 1 -.names n_n3934 [894] n_n4367 [1534] n_n3068 ----1 1 -111- 1 -.names preset pdn n_n3643 nrq1_3 n_n3642 -0-1- 1 -00-1 1 -.names n_n4229 [894] [1529] n_n3402 ---1 1 -11- 1 -.names n_n4145 [894] [1527] n_n3056 ---1 1 -11- 1 -.names n_n4095 [894] [1524] [6321] n_n3019 ---1- 1 -11-- 1 --1-1 1 -.names preset pdn n_n3828 nrq1_3 n_n3827 -0-1- 1 -00-1 1 -.names n_n3085 n_n3250 [894] [1520] n_n3629 ----1 1 -111- 1 -.names n_n3968 [894] [1518] n_n3137 ---1 1 -11- 1 -.names preset pdn ngfdn_3 nrq1_3 n_n126 -1--- 1 --1-- 1 ---00 1 -.names n_n3922 [894] [1514] n_n4063 ---1 1 -11- 1 -.names n_n4366 [894] n_n4367 [1513] n_n3677 ----1 1 -111- 1 -.names [894] n_n3741 [1510] n_n3285 ---1 1 -11- 1 -.names [1508] [1509] n_n3308 -1- 1 --1 1 -.names preset pdn n_n4059 nrq1_3 n_n4058 -0-1- 1 -00-1 1 -.names n_n3898 [894] [1504] n_n3435 ---1 1 -11- 1 -.names preset nen3_10 ndn3_9 ngfdn_3 n_n3635 -01-0 1 -0-10 1 -.names preset pdn n_n3461 nrq1_3 n_n3460 -0-1- 1 -00-1 1 -.names n_n4012 [982] [1500] n_n4011 ---1 1 -11- 1 -.names preset pdn n_n3051 nrq1_3 n_n3050 -0-1- 1 -00-1 1 -.names n_n4047 [894] n_n4367 [1497] n_n3072 ----1 1 -111- 1 -.names n_n3898 [894] [1494] n_n3775 ---1 1 -11- 1 -.names n_n3832 [1492] [6255] [6354] n_n3199 --1-1 1 -1-11 1 -.names pv10_2_2_ [992] [1488] n_n3025 ---1 1 -11- 1 -.names [1486] [1487] n_n3058 -1- 1 --1 1 -.names pv1_7_7_ [994] [1482] n_n3258 ---1 1 -11- 1 -.names preset pdn n_n3504 nrq1_3 n_n3503 -0-1- 1 -00-1 1 -.names n_n4045 [1477] [6356] [6357] n_n130 ----1 1 -11-- 1 -1-1- 1 -.names [1006] [1470] [1472] [6358] n_n121 -00-- 1 --000 1 -.names n_n4324 [894] n_n4367 [1468] n_n3134 ----1 1 -111- 1 -.names n_n4383 [894] [1465] n_n4370 ---1 1 -11- 1 -.names n_n4229 [894] [1079] [1463] n_n4234 ----1 1 -111- 1 -010- 1 -.names preset pdn n_n3040 nrq1_3 n_n3039 -0-1- 1 -00-1 1 -.names preset pdn n_n3874 nrq1_3 n_n3873 -0-1- 1 -00-1 1 -.names preset pdn n_n3999 nrq1_3 n_n3998 -0-1- 1 -00-1 1 -.names n_n4122 [894] [1455] n_n3222 ---1 1 -11- 1 -.names preset pdn ndn1_34 n_n3036 -001 1 -.names pv10_1_1_ [992] [1451] n_n3062 ---1 1 -11- 1 -.names n_n3810 n_n4015 [1449] n_n3017 ---1 1 -11- 1 -.names n_n4258 [894] [1447] n_n3212 ---1 1 -11- 1 -.names preset pdn n_n3095 nrq1_3 n_n3094 -0-1- 1 -00-1 1 -.names preset pdn n_n3663 nrq1_3 n_n3662 -0-1- 1 -00-1 1 -.names n_n3724 n_n3814 [896] [947] n_n3217 -1--1 1 -011- 1 -.names preset pdn n_n3038 nrq1_3 n_n3037 -0-1- 1 -00-1 1 -.names n_n4337 [894] [1437] n_n3368 ---1 1 -11- 1 -.names pv11_0_0_ [988] [1433] n_n3030 ---1 1 -11- 1 -.names pv11_4_4_ [988] [1429] n_n3494 ---1 1 -11- 1 -.names n_n3556 n_n4122 [894] [1427] n_n3711 ----1 1 -111- 1 -.names n_n4074 n_n3578 [894] [1425] n_n3088 ----1 1 -111- 1 -.names preset pdn n_n3211 nrq1_3 n_n3210 -0-1- 1 -00-1 1 -.names preset pdn n_n3367 nrq1_3 n_n3366 -0-1- 1 -00-1 1 -.names preset pdn n_n3434 nrq1_3 n_n3433 -0-1- 1 -00-1 1 -.names n_n4233 [894] [1416] [6303] n_n3125 ---1- 1 -11-- 1 --1-1 1 -.names n_n3688 n_n3624 [894] [1414] n_n4190 ----1 1 -111- 1 -.names n_n3876 [894] [1412] n_n4134 ---1 1 -11- 1 -.names preset pdn n_n3053 nrq1_3 n_n3052 -0-1- 1 -00-1 1 -.names preset pdn n_n3938 nrq1_3 n_n3937 -0-1- 1 -00-1 1 -.names preset n_n3769 n_n4126 [1402] n_n3632 ----1 1 -010- 1 -.names n_n3936 n_n3099 [894] [1400] n_n4387 ----1 1 -111- 1 -.names nen3_10 nsr3_17 nak3_17 [944] n_n127 ----1 1 -01-- 1 --10- 1 -.names preset pdn n_n3903 nrq1_3 n_n3902 -0-1- 1 -00-1 1 -.names n_n3658 n_n4367 [6268] [6361] n_n3684 -1--1 1 --111 1 -.names preset nrq3_11 nsr3_14 ngfdn_3 n_n3046 -01-0 1 -0-00 1 -.names [1391] [1392] [1393] n_n3817 -1-- 1 --1- 1 ---1 1 -.names pv6_3_3_ [990] [1387] n_n3374 ---1 1 -11- 1 -.names n_n4316 [894] [1385] n_n3462 ---1 1 -11- 1 -.names preset pdn n_n3175 nrq1_3 n_n3174 -0-1- 1 -00-1 1 -.names n_n3657 [894] [1381] n_n3054 ---1 1 -11- 1 -.names n_n3495 [894] [1378] [6310] n_n3200 ---1- 1 -11-- 1 --1-1 1 -.names n_n4095 [894] [1375] [6321] n_n3383 ---1- 1 -11-- 1 --1-1 1 -.names preset pdn n_n4077 nrq1_3 n_n4076 -0-1- 1 -00-1 1 -.names preset pdn n_n3142 nrq1_3 n_n3141 -0-1- 1 -00-1 1 -.names preset n_n3901 n_n4126 [1365] n_n3289 ----1 1 -010- 1 -.names n_n3934 n_n3976 [916] [1362] n_n3552 ----1 1 -011- 1 -.names n_n4227 n_n3830 [1360] [6252] n_n3821 ---1- 1 -10-1 1 -.names n_n4160 [894] [1357] n_n3721 ---1 1 -11- 1 -.names n_n4182 [894] [1355] n_n4307 ---1 1 -11- 1 -.names pv4_0_0_ [997] [1351] n_n3229 ---1 1 -11- 1 -.names pv4_4_4_ [997] [1347] n_n3021 ---1 1 -11- 1 -.names preset pdn n_n3836 nrq1_3 n_n3835 -0-1- 1 -00-1 1 -.names preset pdn n_n3470 nrq1_3 n_n3469 -0-1- 1 -00-1 1 -.names n_n4157 [894] [1341] n_n3329 ---1 1 -11- 1 -.names n_n3099 [894] [1339] n_n3881 ---1 1 -11- 1 -.names pv10_6_6_ [992] [1335] n_n3031 ---1 1 -11- 1 -.names n_n3810 n_n4158 [1333] n_n4156 ---1 1 -11- 1 -.names preset ndn3_8 ndn3_9 ngfdn_3 n_n4086 -01-0 1 -0-10 1 -.names pv1_1_1_ [994] [1329] n_n3045 ---1 1 -11- 1 -.names preset pdn n_n3190 nrq1_3 n_n3189 -0-1- 1 -00-1 1 -.names [1006] [1323] [1325] [6366] n_n4028 --1-- 1 -1-1- 1 -1--1 1 -.names preset pdn n_n3042 nrq1_3 n_n3041 -0-1- 1 -00-1 1 -.names preset pdn [1318] n_n133 -1-- 1 --1- 1 ---1 1 -.names preset [1315] [1316] n_n122 -1-- 1 --1- 1 ---1 1 -.names preset pdn n_n3188 nrq1_3 n_n3187 -0-1- 1 -00-1 1 -.names n_n3769 [894] n_n4367 [1312] n_n4300 ----1 1 -111- 1 -.names pv11_3_3_ [988] [1307] n_n3249 ---1 1 -11- 1 -.names pv11_7_7_ [988] [1303] n_n3169 ---1 1 -11- 1 -.names n_n3916 [894] [1301] n_n3757 ---1 1 -11- 1 -.names n_n3608 [894] [1298] [6272] n_n3908 ---1- 1 -11-- 1 --1-1 1 -.names n_n4392 [894] [1295] [6306] n_n3106 ---1- 1 -11-- 1 --1-1 1 -.names preset pdn n_n3150 nrq1_3 n_n3149 -0-1- 1 -00-1 1 -.names n_n3688 [894] [1291] n_n4317 ---1 1 -11- 1 -.names pv10_7_7_ [992] [1287] n_n4359 ---1 1 -11- 1 -.names n_n4362 [894] [1285] n_n4245 ---1 1 -11- 1 -.names n_n3242 n_n3170 [894] [1283] n_n4196 ----1 1 -111- 1 -.names n_n4275 n_n3830 [1282] [6252] n_n3964 ---1- 1 -10-1 1 -.names [896] [1280] [6370] n_n3184 --1- 1 -1-1 1 -.names pv2_4_4_ [999] [1275] n_n3010 ---1 1 -11- 1 -.names pv2_6_6_ [999] [1271] n_n3122 ---1 1 -11- 1 -.names n_n3814 n_n3830 [1270] [6252] n_n3512 ---1- 1 -10-1 1 -.names n_n4159 n_n3976 [894] [1267] n_n3571 ----1 1 -011- 1 -101- 1 -.names n_n4270 [894] [1265] n_n4165 ---1 1 -11- 1 -.names [1004] n_n3975 n_n3974 [1263] n_n3519 ----1 1 -101- 1 -110- 1 -.names n_n3841 [894] [1261] n_n3392 ---1 1 -11- 1 -.names [1259] [1260] n_n4094 -1- 1 --1 1 -.names preset pdn n_n3863 nrq1_3 n_n3862 -0-1- 1 -00-1 1 -.names preset pdn n_n3720 nrq1_3 n_n3719 -0-1- 1 -00-1 1 -.names preset nrq3_11 ngfdn_3 n_n3810 -010 1 -.names pv10_0_0_ [992] [1251] n_n3755 ---1 1 -11- 1 -.names n_n3458 [894] [1248] [6291] n_n3665 ---1- 1 -11-- 1 --1-1 1 -.names n_n4299 [894] [1246] n_n3340 ---1 1 -11- 1 -.names preset pdn n_n3529 nrq1_3 n_n3528 -0-1- 1 -00-1 1 -.names n_n3756 [894] [1242] n_n4207 ---1 1 -11- 1 -.names n_n4324 [916] [934] [1062] n_n3585 -1-1- 1 -11-1 1 -01-0 1 -.names n_n3035 n_n4157 [894] [1232] n_n3336 ----1 1 -111- 1 -.names n_n4227 [947] [1230] [1586] n_n3026 ---1- 1 -11-- 1 -1--1 1 -.names preset pdn n_n4153 nrq1_3 n_n4152 -0-1- 1 -00-1 1 -.names [1225] [6376] n_n128 -1- 1 --1 1 -.names preset pdn n_n3233 nrq1_3 n_n3232 -0-1- 1 -00-1 1 -.names preset [1064] n_n4262 -01 1 -.names n_n4251 [894] [1218] n_n3412 ---1 1 -11- 1 -.names pv4_3_3_ [997] [1214] n_n3015 ---1 1 -11- 1 -.names [1212] [1213] n_n3526 -1- 1 --1 1 -.names preset pdn n_n3441 nrq1_3 n_n3440 -0-1- 1 -00-1 1 -.names preset n_n4026 nak3_17 [1208] n_n3140 -010- 1 -0-01 1 -.names n_n4229 [894] [1206] n_n4339 ---1 1 -11- 1 -.names n_n3841 [894] [1204] n_n4100 ---1 1 -11- 1 -.names n_n4288 [894] [1201] [6259] n_n3275 ---1- 1 -11-- 1 --1-1 1 -.names n_n3085 n_n3250 [894] [1199] n_n4178 ----1 1 -111- 1 -.names pv1_0_0_ [994] [1195] n_n3877 ---1 1 -11- 1 -.names pv2_0_0_ [999] [1191] n_n3538 ---1 1 -11- 1 -.names [1006] [1187] [1189] [6379] n_n3680 --1-- 1 -1-1- 1 -1--1 1 -.names [1006] [1182] [1184] [6380] n_n3104 --1-- 1 -1-1- 1 -1--1 1 -.names n_n3533 [894] [1179] n_n3484 ---1 1 -11- 1 -.names preset n_n4057 [1068] n_n3473 -011 1 -.names preset pdn n_n3674 nrq1_3 n_n3673 -0-1- 1 -00-1 1 -.names n_n3959 [1069] [1171] [1172] n_n3592 ---1- 1 ----1 1 -11-- 1 -.names [1002] n_n3975 n_n3974 [1168] n_n3607 ----1 1 -101- 1 -110- 1 -.names [1165] [1166] [1167] n_n3292 -1-- 1 --1- 1 ---1 1 -.names preset pdn n_n4018 nrq1_3 n_n4017 -0-1- 1 -00-1 1 -.names preset pdn n_n4354 nrq1_3 n_n4352 -0-1- 1 -00-1 1 -.names preset pdn n_n3797 nrq1_3 n_n3796 -0-1- 1 -00-1 1 -.names n_n4316 [894] [983] n_n3737 ---1 1 -11- 1 -.names n_n4392 [894] [978] [6306] n_n3644 ---1- 1 -11-- 1 --1-1 1 -.names n_n3810 n_n3363 [1128] [976] n_n3059 ----1 1 -111- 1 -100- 1 -.names n_n4211 n_n3657 [894] [974] n_n3535 ----1 1 -111- 1 -.names n_n4074 n_n3578 [894] [971] n_n3804 ----1 1 -111- 1 -.names preset pdn n_n3087 nrq1_3 n_n3086 -0-1- 1 -00-1 1 -.names preset pdn n_n4105 nrq1_3 n_n4104 -0-1- 1 -00-1 1 -.names preset pdn n_n3262 nrq1_3 n_n3261 -0-1- 1 -00-1 1 -.names preset n_n4125 n_n4126 [6385] n_n4124 ---11 1 -010- 1 -.names n_n3814 [896] [946] n_n3813 ---1 1 -01- 1 -.names n_n3832 [921] [6386] [6389] n_n132 ----0 1 -00-- 1 --00- 1 -.names nsr3_3 [944] nrq3_2 [911] n_n123 --1-- 1 -1-0- 1 -1--1 1 -.names preset ndn3_8 ndn3_9 [988] -010 1 -.names preset n_n3198 n_n3707 n_n3709 [896] -0011 1 -.names n_n3604 n_n3658 n_n4335 [6268] [1016] -11-- 1 -1--0 1 -100- 1 --011 1 -.names preset ndn3_7 ndn3_8 [992] -010 1 -.names preset pdn nsr1_2 n_n3765 [894] -0000 1 -.names preset n_n4057 n_n3557 n_n4056 [916] -0101 1 -.names preset n_n4126 [934] -00 1 -.names pdn n_n4108 ndn1_34 nrq1_3 [1020] --1-- 1 -1-0- 1 -0--1 1 -.names n_n3916 [1096] n_n4069 -11 1 -00 1 -.names n_n3363 n_n3362 [941] [1129] n_n4015 -11-1 1 -1-01 1 --101 1 -00-0 1 -0-10 1 --010 1 -.names preset ndn3_10 nen3_10 [1004] -001 1 -.names preset ndn3_6 ndn3_7 [990] -010 1 -.names pready_0_0_ ndn3_4 nsr3_3 nrq3_2 [1021] --1-- 1 ---0- 1 -1--1 1 -.names pready_0_0_ nsr3_3 nrq3_2 [6284] [994] --0-1 1 -1-11 1 -.names n_n4360 n_n3653 [905] [906] n_n3563 -0--1 1 --1-1 1 -011- 1 -.names n_n4067 n_n3788 n_n3830 [6254] [1022] -1--- 1 --1-- 1 ----0 1 -0-1- 1 -.names preset ndn3_15 ngfdn_3 [1002] -001 1 -.names preset ndn3_5 ndn3_6 [997] -010 1 -.names preset n_n4126 n_n3500 [1006] -01- 1 -0-1 1 -.names preset ndn3_4 ndn3_5 [999] -010 1 -.names n_n4093 n_n3788 [1013] [2264] nak3_17 -0--- 1 --11- 1 ---11 1 -.names n_n3916 n_n4040 n_n4039 [1096] n_n4038 -0111 1 -1011 1 -1101 1 -0001 1 -1110 1 -0010 1 -0100 1 -1000 1 -.names n_n3841 [1078] n_n3653 -11 1 -00 1 -.names preset pdn [944] -1- 1 --1 1 -.names preset_0_0_ nlc1_2 nsr1_2 n_n4151 [1028] --1-- 1 -001- 1 -0-11 1 -.names n_n4316 n_n4315 n_n4155 n_n4116 -111 1 -001 1 -010 1 -100 1 -.names n_n3988 n_n3898 [1076] n_n3622 n_n3689 -0111 1 -1011 1 -1101 1 -0001 1 -1110 1 -0010 1 -0100 1 -1000 1 -.names n_n4012 [896] [1012] [6330] [1014] -1111 1 -.names n_n4345 n_n4019 n_n3884 [1086] n_n4158 -11-1 1 -1-11 1 --111 1 -00-0 1 -0-00 1 --000 1 -.names pready_0_0_ nsr3_3 nrq3_2 [6333] [973] -1--- 1 -0--- 1 --0-- 1 ---0- 1 ----1 1 -.names n_n4067 n_n3788 n_n3830 [6254] [1041] -1--- 1 --001 1 -.names n_n4145 [1075] n_n4079 -11 1 -00 1 -.names n_n3724 n_n4227 n_n3814 [1012] -111 1 -.names [947] [1582] [1584] [1586] [1042] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n_n3898 [1076] n_n3745 -11 1 -00 1 -.names preset_0_0_ nlc1_2 nsr1_2 n_n4151 nrq1_3 ---0- 1 -10-- 1 --1-0 1 -.names n_n4160 n_n4222 n_n4159 n_n3976 n_n3741 -010- 1 -100- 1 -0111 1 -1011 1 -1110 1 -0010 1 -.names n_n3832 [1726] [6255] [6257] [982] --1-- 1 -0--1 1 ---01 1 -.names n_n4229 [1079] n_n4256 -11 1 -00 1 -.names n_n3832 [1588] [6255] [6257] [947] --1-- 1 -0--1 1 ---01 1 -.names n_n4229 n_n3818 [1079] n_n3595 n_n4084 -0111 1 -1011 1 -1101 1 -0001 1 -1110 1 -0010 1 -0100 1 -1000 1 -.names n_n4159 n_n3976 n_n4133 -01 1 -10 1 -.names nrq3_11 ngfdn_3 nrq3_12 -10 1 -.names n_n3788 [2264] [6254] n_n3832 -001 1 -.names n_n3851 n_n3831 n_n4026 n_n3852 [1015] -111- 1 -11-1 1 --101 1 -.names n_n3709 [1137] [1136] [6290] [1063] -0--- 1 ----0 1 --11- 1 -.names nlc3_3 n_n4263 nrq3_2 [6324] [1064] --1-- 1 -0-11 1 -.names n_n4056 n_n3656 n_n4098 [6349] [1068] --1-- 1 -1-1- 1 -1--0 1 -.names n_n4159 n_n3976 n_n3959 [923] ---1 1 -11- 1 -00- 1 -.names n_n3832 [1173] [6255] [6257] [1069] --1-- 1 -0--1 1 ---01 1 -.names n_n4145 n_n4080 [1075] n_n4078 n_n4297 -0111 1 -1011 1 -1101 1 -0001 1 -1110 1 -0010 1 -0100 1 -1000 1 -.names n_n4056 n_n4367 [6268] [6270] n_n4126 -1--1 1 -011- 1 -.names n_n4222 n_n3934 n_n3976 n_n4125 [1070] -00-1 1 -0-01 1 -10-0 1 -1-00 1 -1111 1 -0110 1 -.names n_n4160 n_n4383 n_n4159 [935] -1-- 1 --1- 1 ---1 1 -.names preset_0_0_ nlc1_2 n_n4151 n_n3765 -10- 1 --10 1 -.names n_n3604 n_n3658 [6265] [6266] n_n4367 -11-- 1 --01- 1 --0-1 1 -.names n_n3955 n_n3954 n_n4029 n_n3845 [984] -1--- 1 --0-- 1 ---1- 1 ----1 1 -.names [6265] [6266] n_n4335 -1- 1 --1 1 -.names n_n4069 n_n4038 n_n3986 n_n4082 [899] -1--1 1 --0-1 1 -101- 1 -.names n_n3689 n_n3745 [899] [900] n_n3786 -0-1- 1 --11- 1 -01-1 1 -.names n_n3898 n_n4144 n_n4223 n_n4034 [1075] -111- 1 -000- 1 -11-1 1 --111 1 -00-0 1 --000 1 -.names n_n3916 n_n4223 n_n3420 n_n4267 [1076] -111- 1 -000- 1 -11-1 1 --111 1 -00-0 1 --000 1 -.names n_n3833 n_n4067 n_n3563 n_n3788 -01- 1 --01 1 -.names n_n4057 n_n3557 n_n4056 n_n4305 -101 1 -.names n_n4056 n_n4367 [6268] n_n3656 -011 1 -.names n_n3493 n_n4045 n_n4367 [6299] n_n3500 -00-- 1 -0-01 1 -.names n_n4145 n_n4144 n_n4259 n_n4268 [1078] -11-1 1 -1-11 1 --111 1 -00-0 1 -0-00 1 --000 1 -.names n_n4316 n_n4181 n_n4315 n_n4155 [1079] -111- 1 -000- 1 -11-1 1 --111 1 -00-0 1 --000 1 -.names nen3_10 nsr3_17 [1013] -11 1 -.names ndn3_15 ngfdn_3 nrq3_15 -01 1 -.names [2189] [2190] [2191] n_n3363 -1-- 1 --1- 1 ---1 1 -.names nrq3_11 ngfdn_3 n_n3741 [6275] n_n3362 ----1 1 -101- 1 -.names n_n3988 n_n3898 [1076] n_n3622 n_n4078 -1--1 1 -101- 1 -110- 1 --011 1 --101 1 -.names n_n4145 n_n4080 [1075] n_n4078 n_n3888 --1-1 1 -011- 1 -110- 1 -0-11 1 -1-01 1 -.names n_n4169 n_n4168 [2049] [2050] n_n4345 -11-- 1 -1-1- 1 --11- 1 -1--1 1 --1-1 1 -.names n_n3916 nrq3_12 [1096] [6296] n_n4019 ----1 1 -111- 1 -010- 1 -.names [2035] [2036] [2037] n_n3884 -1-- 1 --1- 1 ---1 1 -.names n_n3334 [1903] [1904] [1905] [1086] -11-- 1 -1-1- 1 -1--1 1 -0000 1 -.names n_n4229 n_n3818 [1079] n_n3595 n_n4039 --1-1 1 -011- 1 -110- 1 -0-11 1 -1-01 1 -.names n_n3916 n_n4040 n_n4039 [1096] n_n3622 --11- 1 -01-1 1 -0-11 1 -11-0 1 -1-10 1 -.names [2175] [2176] [2177] n_n3981 -1-- 1 --1- 1 ---1 1 -.names n_n3981 [2174] [6281] [1088] -1-- 1 --1- 1 ---1 1 -.names n_n3865 [984] n_n3294 -11 1 -00 1 -.names n_n3898 nrq3_12 [1076] [6317] n_n3334 ----1 1 -111- 1 -010- 1 -.names n_n3198 n_n3707 n_n3709 n_n4296 -011 1 -.names n_n3841 nrq3_12 [1078] [6312] n_n3324 ----1 1 -111- 1 -010- 1 -.names [1908] [1909] [1910] n_n3243 -1-- 1 --1- 1 ---1 1 -.names n_n3851 n_n4026 n_n3852 n_n3830 -01- 1 --00 1 -.names n_n3916 n_n4047 n_n3870 n_n3869 -11- 1 -1-1 1 --11 1 -.names n_n4366 n_n3898 n_n3869 n_n3205 -11- 1 -1-1 1 --11 1 -.names n_n3876 n_n4069 n_n4231 n_n4254 [901] -0-1- 1 --11- 1 -01-1 1 -.names n_n4362 n_n3745 [901] [907] n_n3240 -0-1- 1 --11- 1 -01-1 1 -.names n_n4160 n_n4383 n_n4159 n_n4182 n_n4181 -1--0 1 --1-0 1 ---10 1 -0001 1 -.names n_n4096 [1892] [1893] [1894] [1094] -11-- 1 -1-1- 1 -1--1 1 -0000 1 -.names n_n4229 n_n3769 n_n3899 n_n3870 -11- 1 -1-1 1 --11 1 -.names n_n4229 n_n4181 n_n3420 n_n3923 [1096] -111- 1 -000- 1 -1-11 1 --111 1 -0-00 1 --000 1 -.names n_n4224 n_n4251 [935] [6251] n_n4144 -10-- 1 --01- 1 --0-0 1 -0101 1 -.names n_n4224 n_n4330 n_n4182 [935] n_n4223 -01-- 1 -0-1- 1 -0--1 1 -1000 1 -.names n_n3916 n_n4330 [1116] n_n4267 n_n4034 -1--1 1 -101- 1 -110- 1 --011 1 --101 1 -.names n_n3898 n_n4223 n_n4034 n_n4259 -11- 1 -1-1 1 --11 1 -.names n_n4222 n_n3934 n_n3976 n_n4125 n_n3900 -1--1 1 -111- 1 --111 1 -.names n_n3574 n_n3959 n_n3741 n_n4133 n_n3124 --00- 1 ---00 1 -110- 1 -0-10 1 -1011 1 -.names n_n3726 n_n3653 n_n3888 [1137] n_n135 --0-1 1 -0111 1 -1101 1 -.names n_n4160 n_n4383 n_n4159 n_n4315 -10- 1 --01 1 -010 1 -.names n_n3334 [1903] [1904] [1905] [1104] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n_n4145 nrq3_12 [1075] [6318] n_n4096 ----1 1 -111- 1 -010- 1 -.names n_n3995 n_n4116 n_n3124 n_n3994 [904] --01- 1 -0111 1 -1001 1 -1110 1 -0000 1 -.names n_n4256 n_n4084 [904] [903] n_n3986 -0-1- 1 --11- 1 -01-1 1 -.names n_n3574 n_n3741 [923] n_n3994 -10- 1 -1-1 1 --01 1 -.names n_n3995 n_n4116 n_n3994 n_n3595 -10- 1 -1-1 1 --01 1 -.names n_n4381 n_n4052 n_n3865 [984] n_n4357 -11-- 1 -1-1- 1 -1--1 1 -0000 1 -.names n_n4224 n_n4251 [935] [6251] [1109] -1--- 1 --1-- 1 ---1- 1 ----0 1 -.names n_n4270 [1109] n_n4268 -01 1 -10 1 -.names n_n3955 n_n3954 n_n4029 n_n3845 n_n4006 -1-1- 1 --01- 1 ---11 1 -0100 1 -.names n_n3955 n_n3954 n_n3845 n_n3848 -1-1 1 --01 1 -010 1 -.names n_n4099 [1119] n_n4098 -11 1 -00 1 -.names n_n4052 n_n3865 [984] [942] -01- 1 -0-1 1 -100 1 -.names n_n4169 [2045] [6295] [1110] -11- 1 -1-1 1 -000 1 -.names n_n4360 n_n3653 [905] [906] n_n3852 -1-1- 1 --01- 1 -10-1 1 -.names n_n3995 n_n4116 n_n3124 n_n3994 [903] --10- 1 -1111 1 -0001 1 -0110 1 -1000 1 -.names n_n4256 n_n4084 [904] [903] n_n4082 -1--1 1 --0-1 1 -101- 1 -.names preset_0_0_ nlc1_2 nsr1_2 n_n4151 nrq3_2 -001- 1 -0-11 1 --111 1 -.names [2046] [2047] [2048] n_n4169 -1-- 1 --1- 1 ---1 1 -.names n_n4229 nrq3_12 [1079] [6295] n_n4168 ----1 1 -111- 1 -010- 1 -.names n_n4160 n_n4222 n_n4159 n_n3976 n_n4155 -011- 1 -110- 1 -0-11 1 --111 1 -.names n_n4299 n_n4079 n_n3240 n_n3253 [905] -1--1 1 --0-1 1 -101- 1 -.names n_n4160 n_n4383 n_n4159 n_n4182 [1116] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n_n4330 [1116] n_n3420 -01 1 -10 1 -.names n_n3946 n_n4116 n_n3927 [902] -0-1 1 --11 1 -010 1 -.names n_n4258 n_n4256 [902] [908] n_n4231 -0-1- 1 --11- 1 -01-1 1 -.names n_n3876 n_n4069 n_n4231 n_n4254 [907] -1--1 1 --0-1 1 -101- 1 -.names n_n4362 n_n3745 [901] [907] n_n3253 -1--1 1 --0-1 1 -101- 1 -.names n_n4381 n_n4052 n_n3865 [984] [1119] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n_n4069 n_n4038 n_n3986 n_n4082 [900] -0-1- 1 --11- 1 -01-1 1 -.names n_n3689 n_n3745 [899] [900] n_n3785 -1--1 1 --0-1 1 -101- 1 -.names [1892] [1893] [1894] n_n4097 -1-- 1 --1- 1 ---1 1 -.names n_n3974 [2183] [2184] [2185] [941] -0--- 1 --000 1 -.names [2183] [2184] [2185] n_n3975 -1-- 1 --1- 1 ---1 1 -.names n_n3934 n_n4367 nrq3_15 [6278] n_n3974 ----1 1 -111- 1 -.names n_n4019 [2035] [2036] [2037] [1122] -11-- 1 -1-1- 1 -1--1 1 -0000 1 -.names n_n4229 n_n4181 n_n3923 n_n4267 -11- 1 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-111- 1 -000- 1 -11-1 1 --111 1 -00-0 1 --000 1 -.names n_n3916 n_n4047 n_n3898 n_n3870 [1034] -111- 1 -000- 1 -1-11 1 --111 1 -0-00 1 --000 1 -.names n_n4047 n_n4229 n_n3769 n_n3899 [1038] -111- 1 -000- 1 -11-1 1 -1-11 1 -00-0 1 -0-00 1 -.names n_n4316 n_n3769 n_n3901 n_n3900 [1051] -111- 1 -000- 1 -11-1 1 --111 1 -00-0 1 --000 1 -.names n_n3475 n_n4145 n_n3841 n_n3205 [1062] -111- 1 -000- 1 -1-11 1 --111 1 -0-00 1 --000 1 -.names n_n3707 n_n3851 n_n4026 n_n3852 [1082] -0--- 1 --01- 1 ---00 1 -.names tin_pready_0_0_ n_n4108 n_n3354 nsr4_2 [911] -00-1 1 -0-01 1 --101 1 -.names preset n_n3831 [922] [937] [921] -00-- 1 -0-1- 1 -0--1 1 -.names n_n3788 [2264] [6254] [6387] [922] -0011 1 -.names n_n3788 [1082] [2264] [6254] [937] -0101 1 -.names n_n3814 n_n3832 [6255] [6257] [946] -10-1 1 -1-01 1 -.names preset pdn n_n3806 nrq1_3 [971] -011- 1 -0-10 1 -.names preset pdn n_n3537 nrq1_3 [974] -011- 1 -0-10 1 -.names preset nrq3_11 ngfdn_3 n_n3099 [976] -00-1 1 -0-11 1 -.names preset pdn n_n3646 nrq1_3 [978] -011- 1 -0-10 1 -.names preset pdn n_n3739 nrq1_3 [983] -011- 1 -0-10 1 -.names preset n_n4299 n_n3832 [6255] [1165] -0111 1 -.names n_n4080 n_n3832 [6255] [6257] [1166] -10-1 1 -1-01 1 -.names n_n4080 [896] n_n4079 n_n4078 [1167] -0111 1 -1101 1 -1110 1 -0100 1 -.names preset ndn3_15 ngfdn_3 n_n3608 [1168] -01-1 1 -0-01 1 -.names preset n_n3756 n_n3832 [6255] [1171] -0111 1 -.names n_n4159 n_n3976 n_n3959 [896] [1172] -0101 1 -1001 1 -.names n_n4159 n_n3976 [896] [1173] -111 1 -001 1 -.names preset pdn n_n3486 nrq1_3 [1179] -011- 1 -0-10 1 -.names preset n_n3865 n_n4126 n_n3500 [1182] -0100 1 -.names n_n3922 n_n3656 [2011] [1184] -11- 1 -1-1 1 -.names preset n_n3845 n_n4126 n_n3500 [1187] -0100 1 -.names n_n3968 n_n3656 [2011] [1189] -11- 1 -1-1 1 -.names preset ndn3_4 ndn3_5 n_n3931 [1191] -00-1 1 -0-11 1 -.names preset n_n3878 [1155] [1195] -011 1 -.names preset pdn n_n4180 nrq1_3 [1199] -011- 1 -0-10 1 -.names preset pdn n_n3277 nrq1_3 [1201] -011- 1 -0-10 1 -.names preset pdn n_n4102 nrq1_3 [1204] -011- 1 -0-10 1 -.names preset pdn n_n4342 nrq1_3 [1206] -011- 1 -0-10 1 -.names [1015] n_n3788 [2264] [6254] [1208] -1001 1 -.names preset ndn3_10 nen3_10 n_n3841 [1212] -01-1 1 -0-01 1 -.names [1004] n_n3324 n_n3243 [914] [1213] -1011 1 -1101 1 -1110 1 -1000 1 -.names preset ndn3_5 ndn3_6 n_n4182 [1214] -00-1 1 -0-11 1 -.names preset pdn n_n3413 nrq1_3 [1218] -011- 1 -0-10 1 -.names n_n3831 n_n3788 [2264] [6254] [1225] -11-- 1 -1-1- 1 -1--0 1 -.names n_n3724 n_n4227 n_n3814 [896] [1230] -1011 1 -.names preset pdn n_n3337 nrq1_3 [1232] -011- 1 -0-10 1 -.names preset pdn n_n4209 nrq1_3 [1242] -011- 1 -0-10 1 -.names preset pdn n_n3342 nrq1_3 [1246] -011- 1 -0-10 1 -.names preset pdn n_n3667 nrq1_3 [1248] -011- 1 -0-10 1 -.names preset ndn3_7 ndn3_8 n_n3756 [1251] -00-1 1 -0-11 1 -.names preset ndn3_15 n_n4095 ngfdn_3 [1259] -011- 1 -0-10 1 -.names [1002] [1094] [1898] [1899] [1260] -111- 1 -11-1 1 -1000 1 -.names preset pdn n_n3394 nrq1_3 [1261] -011- 1 -0-10 1 -.names preset ndn3_10 nen3_10 n_n3976 [1263] -01-1 1 -0-01 1 -.names preset pdn n_n4166 nrq1_3 [1265] -011- 1 -0-10 1 -.names preset pdn n_n3572 nrq1_3 [1267] -011- 1 -0-10 1 -.names preset pdn n_n3514 nrq1_3 [1270] -011- 1 -0-10 1 -.names preset ndn3_4 ndn3_5 n_n4062 [1271] -00-1 1 -0-11 1 -.names preset ndn3_4 ndn3_5 n_n4021 [1275] -00-1 1 -0-11 1 -.names n_n3766 [947] [1584] [1586] [1280] -11-- 1 -1-1- 1 -1--1 1 -.names preset pdn n_n3966 nrq1_3 [1282] -011- 1 -0-10 1 -.names preset pdn n_n4199 nrq1_3 [1283] -011- 1 -0-10 1 -.names preset pdn n_n4247 nrq1_3 [1285] -011- 1 -0-10 1 -.names preset ndn3_7 ndn3_8 n_n4360 [1287] -00-1 1 -0-11 1 -.names preset pdn n_n4320 nrq1_3 [1291] -011- 1 -0-10 1 -.names preset pdn n_n3108 nrq1_3 [1295] -011- 1 -0-10 1 -.names preset pdn n_n3910 nrq1_3 [1298] -011- 1 -0-10 1 -.names preset pdn n_n3758 nrq1_3 [1301] -011- 1 -0-10 1 -.names preset ndn3_8 ndn3_9 n_n3170 [1303] -00-1 1 -0-11 1 -.names preset ndn3_8 ndn3_9 n_n3250 [1307] -00-1 1 -0-11 1 -.names preset pdn n_n4303 nrq1_3 [1312] -011- 1 -0-10 1 -.names preset_0_0_ nlc1_2 nsr1_2 [1315] -001 1 -.names preset_0_0_ nlc1_2 nsr1_2 n_n4151 [1316] --1-1 1 ---01 1 -10-1 1 -.names n_n4045 nsr3_17 nsr3_14 n_n4367 [1318] --11- 1 -1-11 1 -.names preset n_n4029 n_n4126 n_n3500 [1323] -0100 1 -.names n_n3533 n_n3656 [2011] [1325] -11- 1 -1-1 1 -.names preset n_n3208 [1155] [1329] -011 1 -.names preset nrq3_11 n_n4157 ngfdn_3 [1333] -001- 1 -0-11 1 -.names preset ndn3_7 ndn3_8 n_n4299 [1335] -00-1 1 -0-11 1 -.names preset pdn n_n3883 nrq1_3 [1339] -011- 1 -0-10 1 -.names preset pdn n_n3331 nrq1_3 [1341] -011- 1 -0-10 1 -.names preset ndn3_5 ndn3_6 n_n4330 [1347] -00-1 1 -0-11 1 -.names preset ndn3_5 ndn3_6 n_n4159 [1351] -00-1 1 -0-11 1 -.names preset pdn n_n4309 nrq1_3 [1355] -011- 1 -0-10 1 -.names preset pdn n_n3722 nrq1_3 [1357] -011- 1 -0-10 1 -.names preset pdn n_n3823 nrq1_3 [1360] -011- 1 -0-10 1 -.names preset n_n3934 n_n4126 [1363] [1362] --1-1 1 -010- 1 -.names n_n3976 [916] [1363] -01 1 -.names n_n4316 n_n3901 [916] n_n3900 [1365] -1111 1 -0011 1 -0110 1 -1010 1 -.names preset pdn n_n3385 nrq1_3 [1375] -011- 1 -0-10 1 -.names preset pdn n_n3202 nrq1_3 [1378] -011- 1 -0-10 1 -.names preset pdn n_n3055 nrq1_3 [1381] -011- 1 -0-10 1 -.names preset pdn n_n3463 nrq1_3 [1385] -011- 1 -0-10 1 -.names preset ndn3_6 ndn3_7 n_n3533 [1387] -00-1 1 -0-11 1 -.names preset n_n4258 n_n3832 [6255] [1391] -0111 1 -.names n_n3818 n_n3832 [6255] [6257] [1392] -10-1 1 -1-01 1 -.names n_n3818 [896] n_n4256 n_n3595 [1393] -0111 1 -1101 1 -1110 1 -0100 1 -.names preset pdn n_n4390 nrq1_3 [1400] -011- 1 -0-10 1 -.names n_n4229 [916] [1051] [1402] -111 1 -010 1 -.names preset pdn n_n4136 nrq1_3 [1412] -011- 1 -0-10 1 -.names preset pdn n_n4192 nrq1_3 [1414] -011- 1 -0-10 1 -.names preset pdn n_n3126 nrq1_3 [1416] -011- 1 -0-10 1 -.names preset pdn n_n3089 nrq1_3 [1425] -011- 1 -0-10 1 -.names preset pdn n_n3713 nrq1_3 [1427] -011- 1 -0-10 1 -.names preset ndn3_8 n_n3578 ndn3_9 [1429] -001- 1 -0-11 1 -.names preset ndn3_8 n_n3624 ndn3_9 [1433] -001- 1 -0-11 1 -.names preset pdn n_n3370 nrq1_3 [1437] -011- 1 -0-10 1 -.names preset pdn n_n3213 nrq1_3 [1447] -011- 1 -0-10 1 -.names preset n_n3657 nrq3_11 ngfdn_3 [1449] -010- 1 -01-1 1 -.names preset ndn3_7 ndn3_8 n_n3743 [1451] -00-1 1 -0-11 1 -.names preset pdn n_n3223 nrq1_3 [1455] -011- 1 -0-10 1 -.names preset pdn n_n4236 nrq1_3 [1463] -011- 1 -0-10 1 -.names preset pdn n_n4372 nrq1_3 [1465] -011- 1 -0-10 1 -.names preset pdn n_n3136 nrq1_3 [1468] -011- 1 -0-10 1 -.names preset n_n3954 n_n4126 n_n3500 [1470] -0000 1 -.names n_n4349 n_n3656 [2011] [1472] -11- 1 -1-1 1 -.names n_n4056 n_n4098 [6349] [6355] [1477] -0--1 1 --1-1 1 ---01 1 -.names preset n_n3259 [1155] [1482] -011 1 -.names preset n_n3085 nrq3_11 ngfdn_3 [1486] -010- 1 -01-1 1 -.names n_n3810 [1110] [2049] [2050] [1487] -111- 1 -11-1 1 -1000 1 -.names preset ndn3_7 ndn3_8 n_n3946 [1488] -00-1 1 -0-11 1 -.names n_n3709 [1137] [1136] [6290] [1492] -1--0 1 -111- 1 -.names preset pdn n_n3777 nrq1_3 [1494] -011- 1 -0-10 1 -.names preset pdn n_n3073 nrq1_3 [1497] -011- 1 -0-10 1 -.names n_n4012 [896] [1012] [6330] [1500] -0111 1 -.names preset pdn n_n3436 nrq1_3 [1504] -011- 1 -0-10 1 -.names preset ndn3_15 n_n4351 ngfdn_3 [1508] -011- 1 -0-10 1 -.names [1002] [1110] [2049] [2050] [1509] -111- 1 -11-1 1 -1000 1 -.names preset pdn n_n3287 nrq1_3 [1510] -011- 1 -0-10 1 -.names preset pdn n_n3679 nrq1_3 [1513] -011- 1 -0-10 1 -.names preset pdn n_n4065 nrq1_3 [1514] -011- 1 -0-10 1 -.names preset pdn n_n3138 nrq1_3 [1518] -011- 1 -0-10 1 -.names preset pdn n_n3631 nrq1_3 [1520] -011- 1 -0-10 1 -.names preset pdn n_n3020 nrq1_3 [1524] -011- 1 -0-10 1 -.names preset pdn n_n3057 nrq1_3 [1527] -011- 1 -0-10 1 -.names preset pdn n_n3404 nrq1_3 [1529] -011- 1 -0-10 1 -.names preset pdn n_n3069 nrq1_3 [1534] -011- 1 -0-10 1 -.names n_n3483 [982] [1539] [1724] [1538] -11-- 1 -1-1- 1 -1--1 1 -.names n_n4334 [896] [1539] -01 1 -.names preset ndn3_7 ndn3_8 n_n4362 [1541] -00-1 1 -0-11 1 -.names preset ndn3_6 ndn3_7 n_n4201 [1547] -00-1 1 -0-11 1 -.names preset ndn3_10 n_n4229 nen3_10 [1551] -011- 1 -0-10 1 -.names [1004] [1110] [2049] [2050] [1552] -111- 1 -11-1 1 -1000 1 -.names preset pdn n_n3408 nrq1_3 [1557] -011- 1 -0-10 1 -.names preset ndn3_4 ndn3_5 n_n3451 [1561] -00-1 1 -0-11 1 -.names n_n4057 n_n4056 n_n4098 [6349] [1565] -10-- 1 -1-1- 1 -1--0 1 -.names preset ndn3_4 ndn3_5 n_n3854 [1574] -00-1 1 -0-11 1 -.names n_n3832 n_n4296 [6255] [6342] [1580] --1-1 1 -1-11 1 -.names n_n3766 [896] [1582] -01 1 -.names n_n4227 [896] [1584] -01 1 -.names n_n3724 [896] [1586] -01 1 -.names n_n3814 [896] [1588] -01 1 -.names preset ndn3_6 ndn3_7 n_n3922 [1594] -00-1 1 -0-11 1 -.names preset ndn3_6 ndn3_7 n_n3968 [1598] -00-1 1 -0-11 1 -.names preset pdn n_n3237 nrq1_3 [1602] -011- 1 -0-10 1 -.names preset pdn n_n3952 nrq1_3 [1604] -011- 1 -0-10 1 -.names preset n_n4122 nrq3_11 ngfdn_3 [1612] -010- 1 -01-1 1 -.names n_n3810 [1094] [1898] [1899] [1613] -111- 1 -11-1 1 -1000 1 -.names preset ndn3_10 n_n3898 nen3_10 [1614] -011- 1 -0-10 1 -.names preset n_n4099 n_n4126 n_n3500 [1621] -0100 1 -.names n_n4337 n_n3656 [2011] [1623] -11- 1 -1-1 1 -.names preset n_n4052 n_n4126 n_n3500 [1630] -0100 1 -.names n_n4052 n_n3865 [984] n_n4305 [1632] -11-1 1 -1-11 1 -0001 1 -.names n_n4071 n_n3656 [2011] [1633] -11- 1 -1-1 1 -.names preset pdn n_n3985 nrq1_3 [1638] -011- 1 -0-10 1 -.names preset pdn n_n3091 nrq1_3 [1640] -011- 1 -0-10 1 -.names preset pdn n_n4003 nrq1_3 [1642] -011- 1 -0-10 1 -.names preset ndn3_10 n_n4145 nen3_10 [1647] -011- 1 -0-10 1 -.names [1004] [1094] [1898] [1899] [1648] -111- 1 -11-1 1 -1000 1 -.names preset ndn3_4 ndn3_5 n_n3978 [1655] -00-1 1 -0-11 1 -.names n_n3916 [916] [1038] [1659] -111 1 -010 1 -.names preset pdn n_n3183 nrq1_3 [1671] -011- 1 -0-10 1 -.names preset ndn3_15 n_n4288 ngfdn_3 [1673] -011- 1 -0-10 1 -.names preset ndn3_5 ndn3_6 n_n4270 [1679] -00-1 1 -0-11 1 -.names preset pdn n_n3449 nrq1_3 [1683] -011- 1 -0-10 1 -.names preset pdn n_n3971 nrq1_3 [1686] -011- 1 -0-10 1 -.names preset pdn n_n3429 nrq1_3 [1687] -011- 1 -0-10 1 -.names preset pdn n_n3319 nrq1_3 [1689] -011- 1 -0-10 1 -.names preset pdn n_n3506 nrq1_3 [1693] -011- 1 -0-10 1 -.names preset ndn3_15 n_n3458 ngfdn_3 [1699] -011- 1 -0-10 1 -.names preset ndn3_15 n_n4233 ngfdn_3 [1707] -011- 1 -0-10 1 -.names [1002] n_n3324 n_n3243 [914] [1708] -1011 1 -1101 1 -1110 1 -1000 1 -.names preset pdn n_n3155 nrq1_3 [1711] -011- 1 -0-10 1 -.names preset n_n3955 n_n4126 n_n3500 [1716] -0100 1 -.names n_n4201 n_n3656 [2011] [1719] -11- 1 -1-1 1 -.names n_n4012 [896] [1724] -01 1 -.names n_n4275 n_n3766 [896] [1012] [1726] -0-1- 1 --01- 1 ---10 1 -.names preset n_n4294 [1155] [1728] -011 1 -.names preset ndn3_5 ndn3_6 n_n4251 [1736] -00-1 1 -0-11 1 -.names preset pdn n_n3736 nrq1_3 [1740] -011- 1 -0-10 1 -.names preset pdn n_n3896 nrq1_3 [1742] -011- 1 -0-10 1 -.names preset pdn n_n4279 nrq1_3 [1745] -011- 1 -0-10 1 -.names preset n_n4362 n_n3832 [6255] [1752] -0111 1 -.names n_n3988 n_n3832 [6255] [6257] [1753] -10-1 1 -1-01 1 -.names n_n3988 [896] n_n3745 n_n3622 [1754] -0111 1 -1101 1 -1110 1 -0100 1 -.names preset ndn3_4 ndn3_5 n_n3328 [1755] -00-1 1 -0-11 1 -.names preset pdn n_n3761 nrq1_3 [1767] -011- 1 -0-10 1 -.names preset n_n3946 n_n3832 [6255] [1771] -0111 1 -.names n_n3995 n_n3832 [6255] [6257] [1772] -10-1 1 -1-01 1 -.names n_n3995 [896] n_n4116 n_n3994 [1773] -0111 1 -1101 1 -1110 1 -0100 1 -.names preset pdn n_n3128 nrq1_3 [1774] -011- 1 -0-10 1 -.names preset n_n3919 [1155] [1776] -011 1 -.names preset n_n3886 [1155] [1780] -011 1 -.names preset pdn n_n3048 nrq1_3 [1784] -011- 1 -0-10 1 -.names preset pdn n_n3061 nrq1_3 [1786] -011- 1 -0-10 1 -.names preset pdn n_n3316 nrq1_3 [1788] -011- 1 -0-10 1 -.names preset pdn n_n3906 nrq1_3 [1792] -011- 1 -0-10 1 -.names preset pdn n_n3583 nrq1_3 [1795] -011- 1 -0-10 1 -.names preset pdn n_n3358 nrq1_3 [1800] -011- 1 -0-10 1 -.names preset pdn n_n4243 nrq1_3 [1806] -011- 1 -0-10 1 -.names preset ndn3_6 n_n4337 ndn3_7 [1812] -001- 1 -0-11 1 -.names preset pdn n_n3207 nrq1_3 [1825] -011- 1 -0-10 1 -.names preset pdn n_n3465 nrq1_3 [1830] -011- 1 -0-10 1 -.names pdn ndn1_34 nrq1_3 [6325] [1833] -11-1 1 -0-01 1 --101 1 -.names preset n_n3892 ndn3_6 ndn3_7 [1837] -010- 1 -01-1 1 -.names preset ndn3_5 n_n4383 ndn3_6 [1843] -001- 1 -0-11 1 -.names preset pdn n_n4286 nrq1_3 [1847] -011- 1 -0-10 1 -.names preset pdn n_n4189 nrq1_3 [1849] -011- 1 -0-10 1 -.names preset pdn n_n3576 nrq1_3 [1853] -011- 1 -0-10 1 -.names preset pdn n_n4172 nrq1_3 [1859] -011- 1 -0-10 1 -.names preset pdn n_n3111 nrq1_3 [1868] -011- 1 -0-10 1 -.names preset n_n3035 ndn3_8 ndn3_9 [1870] -010- 1 -01-1 1 -.names preset pdn n_n3627 nrq1_3 [1874] -011- 1 -0-10 1 -.names preset pdn n_n3044 nrq1_3 [1876] -011- 1 -0-10 1 -.names preset pdn n_n3376 nrq1_3 [1881] -011- 1 -0-10 1 -.names preset pdn n_n3118 nrq1_3 [1882] -011- 1 -0-10 1 -.names preset n_n3242 nrq3_11 ngfdn_3 [1884] -010- 1 -01-1 1 -.names n_n3810 n_n3324 n_n3243 [914] [1885] -1011 1 -1101 1 -1110 1 -1000 1 -.names ndn3_15 n_n3556 n_n4122 ngfdn_3 [1892] -0111 1 -.names ndn3_10 n_n3919 nen3_10 [1893] -011 1 -.names n_n4145 nrq3_11 ngfdn_3 [1894] -110 1 -.names ndn3_10 nen3_10 n_n4062 [1896] -011 1 -.names n_n4345 n_n4019 n_n3884 [1104] [1898] -11-1 1 -1-11 1 --111 1 -.names n_n3334 [1903] [1904] [1905] [1899] -11-- 1 -1-1- 1 -1--1 1 -.names ndn3_10 n_n3854 nen3_10 [1901] -011 1 -.names ndn3_15 n_n3035 n_n4157 ngfdn_3 [1903] -0111 1 -.names n_n3511 ndn3_10 nen3_10 [1904] -101 1 -.names n_n3898 nrq3_11 ngfdn_3 [1905] -110 1 -.names ndn3_15 n_n3242 n_n3170 ngfdn_3 [1908] -0111 1 -.names ndn3_10 nen3_10 n_n3259 [1909] -011 1 -.names nrq3_11 ngfdn_3 n_n3841 [1910] -101 1 -.names ndn3_10 n_n3451 nen3_10 [1912] -011 1 -.names preset pdn n_n3113 nrq1_3 [1914] -011- 1 -0-10 1 -.names preset pdn n_n3173 nrq1_3 [1919] -011- 1 -0-10 1 -.names preset pdn n_n3221 nrq1_3 [1921] -011- 1 -0-10 1 -.names preset n_n3876 n_n3832 [6255] [1925] -0111 1 -.names n_n4040 n_n3832 [6255] [6257] [1926] -10-1 1 -1-01 1 -.names n_n4040 [896] n_n4069 n_n4039 [1927] -0111 1 -1101 1 -1110 1 -0100 1 -.names preset n_n3556 ndn3_8 ndn3_9 [1928] -010- 1 -01-1 1 -.names preset pdn n_n3733 nrq1_3 [1932] -011- 1 -0-10 1 -.names preset pdn n_n3231 nrq1_3 [1940] -011- 1 -0-10 1 -.names preset pdn n_n3313 nrq1_3 [1944] -011- 1 -0-10 1 -.names preset pdn n_n3079 nrq1_3 [1946] -011- 1 -0-10 1 -.names preset n_n3688 nrq3_11 ngfdn_3 [1949] -010- 1 -01-1 1 -.names preset pdn n_n3344 nrq1_3 [1953] -011- 1 -0-10 1 -.names preset n_n4071 ndn3_6 ndn3_7 [1957] -010- 1 -01-1 1 -.names preset pdn n_n3012 nrq1_3 [1961] -011- 1 -0-10 1 -.names preset n_n4222 ndn3_10 nen3_10 [1963] -011- 1 -01-0 1 -.names preset ndn3_5 n_n4160 ndn3_6 [1965] -001- 1 -0-11 1 -.names preset pdn n_n3517 nrq1_3 [1969] -011- 1 -0-10 1 -.names n_n3707 n_n3709 n_n135 [6290] [1971] -10-- 1 -1-1- 1 -1--0 1 -.names preset ndn3_4 ndn3_5 n_n3281 [1976] -00-1 1 -0-11 1 -.names preset pdn n_n3764 nrq1_3 [1980] -011- 1 -0-10 1 -.names preset pdn n_n3549 nrq1_3 [1984] -011- 1 -0-10 1 -.names preset n_n3876 ndn3_7 ndn3_8 [1986] -010- 1 -01-1 1 -.names preset pdn n_n3729 nrq1_3 [1990] -011- 1 -0-10 1 -.names preset pdn n_n3525 nrq1_3 [1992] -011- 1 -0-10 1 -.names preset n_n3916 ndn3_10 nen3_10 [1996] -011- 1 -01-0 1 -.names preset ndn3_15 n_n3495 ngfdn_3 [1998] -011- 1 -0-10 1 -.names preset n_n4211 ndn3_8 ndn3_9 [2000] -010- 1 -01-1 1 -.names preset pdn n_n3670 nrq1_3 [2005] -011- 1 -0-10 1 -.names preset n_n4381 n_n4126 n_n3500 [2007] -0100 1 -.names n_n3892 n_n3656 [2011] [2009] -11- 1 -1-1 1 -.names n_n3493 n_n4045 n_n4367 [6299] [2011] -000- 1 -0-01 1 -.names preset n_n3858 [1155] [2023] -011 1 -.names preset pdn n_n3270 nrq1_3 [2027] -011- 1 -0-10 1 -.names preset n_n4074 nrq3_11 ngfdn_3 [2029] -010- 1 -01-1 1 -.names ndn3_15 n_n4074 n_n3578 ngfdn_3 [2035] -0111 1 -.names ndn3_10 n_n3886 nen3_10 [2036] -011 1 -.names n_n3916 nrq3_11 ngfdn_3 [2037] -110 1 -.names ndn3_10 nen3_10 n_n4021 [2039] -011 1 -.names n_n3281 ndn3_10 nen3_10 [2044] -101 1 -.names n_n4229 nrq3_11 ngfdn_3 [1079] [2045] -1101 1 -0100 1 -.names ndn3_15 n_n3085 n_n3250 ngfdn_3 [2046] -0111 1 -.names ndn3_10 n_n4294 nen3_10 [2047] -011 1 -.names n_n4229 nrq3_11 ngfdn_3 [2048] -110 1 -.names n_n3363 n_n3362 [1088] [941] [2049] -111- 1 -1-10 1 --110 1 -.names n_n3981 [2174] [6281] [2050] -11- 1 -1-1 1 -.names preset pdn n_n3133 nrq1_3 [2051] -011- 1 -0-10 1 -.names n_n3786 n_n3785 [6287] [2060] -00- 1 -0-1 1 -.names n_n4145 n_n4080 [1075] n_n4078 [2061] -0111 1 -1101 1 -0010 1 -1000 1 -.names preset n_n4224 ndn3_5 ndn3_6 [2122] -010- 1 -01-1 1 -.names preset n_n4392 ndn3_15 ngfdn_3 [2126] -011- 1 -01-0 1 -.names preset n_n3511 [1155] [2141] -011 1 -.names preset pdn n_n3780 nrq1_3 [2153] -011- 1 -0-10 1 -.names preset n_n4349 ndn3_6 ndn3_7 [2162] -010- 1 -01-1 1 -.names preset n_n4316 ndn3_10 nen3_10 [2166] -011- 1 -01-0 1 -.names ndn3_10 n_n3978 nen3_10 [2173] -011 1 -.names n_n4316 nrq3_12 n_n4315 n_n4155 [2174] -1111 1 -0101 1 -0110 1 -1100 1 -.names ndn3_15 n_n4211 n_n3657 ngfdn_3 [2175] -0111 1 -.names n_n3858 ndn3_10 nen3_10 [2176] -101 1 -.names n_n4316 nrq3_11 ngfdn_3 [2177] -110 1 -.names nrq3_11 n_n4159 n_n3976 ngfdn_3 [2182] -1010 1 -1100 1 -.names ndn3_15 n_n3688 n_n3624 ngfdn_3 [2183] -0111 1 -.names ndn3_10 nen3_10 n_n3878 [2184] -011 1 -.names nrq3_11 n_n3976 ngfdn_3 [2185] -110 1 -.names ndn3_10 n_n3328 nen3_10 [2187] -011 1 -.names nrq3_11 ngfdn_3 n_n3741 [2188] -101 1 -.names n_n3936 ndn3_15 ngfdn_3 n_n3099 [2189] -1011 1 -.names ndn3_10 nen3_10 n_n3208 [2190] -011 1 -.names n_n4222 nrq3_11 ngfdn_3 [2191] -110 1 -.names preset pdn n_n3793 nrq1_3 [2192] -011- 1 -0-10 1 -.names preset pdn n_n3497 nrq1_3 [2195] -011- 1 -0-10 1 -.names preset pdn n_n3098 nrq1_3 [2198] -011- 1 -0-10 1 -.names preset pdn n_n3687 nrq1_3 [2202] -011- 1 -0-10 1 -.names preset pdn n_n3225 nrq1_3 [2224] -011- 1 -0-10 1 -.names preset n_n4258 ndn3_7 ndn3_8 [2226] -010- 1 -01-1 1 -.names preset n_n4360 n_n3832 [6255] [2240] -0111 1 -.names n_n3726 n_n3832 [6255] [6257] [2241] -10-1 1 -1-01 1 -.names n_n3726 [896] n_n3653 n_n3888 [2242] -0111 1 -1101 1 -1110 1 -0100 1 -.names preset pdn n_n3008 nrq1_3 [2259] -011- 1 -0-10 1 -.names preset n_n3743 n_n3832 [6255] [2261] -0111 1 -.names n_n3574 n_n3832 [6255] [6257] [2262] -10-1 1 -1-01 1 -.names n_n3574 [896] n_n3741 [923] [2263] -0111 1 -1101 1 -1110 1 -0100 1 -.names n_n3851 n_n4067 n_n4026 n_n3852 [2264] -001- 1 --000 1 -.names preset n_n3936 ndn3_8 ndn3_9 [2270] -010- 1 -01-1 1 -.names preset pdn n_n4142 nrq1_3 [2275] -011- 1 -0-10 1 -.names n_n4159 n_n3976 n_n3756 [6250] -010 1 -100 1 -.names n_n4182 n_n4330 [6251] -00 1 -.names n_n3833 n_n4067 [894] n_n3563 [6252] -111- 1 -1-10 1 --010 1 -.names nen3_10 nsr3_17 n_n4093 [6254] -111 1 -.names [1015] n_n3709 [6255] -10 1 -.names preset n_n3198 n_n3707 n_n3709 [6257] -01-- 1 -0-0- 1 -0--0 1 -.names n_n4157 n_n3035 [6259] -11 1 -.names n_n4349 n_n4071 n_n3892 n_n4337 [6265] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n_n3968 n_n3922 n_n4201 n_n3533 [6266] -1--- 1 --1-- 1 ---1- 1 ----1 1 -.names n_n4045 nsr3_17 nsr3_14 [6268] -101 1 -.names n_n3557 n_n4057 [6270] -01 1 -.names n_n3624 n_n3688 [6272] -11 1 -.names n_n4125 n_n4367 nrq3_15 [2187] [6275] ----1 1 -111- 1 -.names ndn3_10 nen3_10 n_n3931 [2182] [6278] ----1 1 -011- 1 -.names n_n3901 n_n4367 nrq3_15 [2173] [6281] ----1 1 -111- 1 -.names ndn3_4 preset [6284] -00 1 -.names n_n4145 n_n4080 [1075] n_n4078 [6287] -0-1- 1 -1-0- 1 -1011 1 -0001 1 -1110 1 -0100 1 -.names n_n3726 n_n3653 n_n3888 [2061] [6289] --1-- 1 ----1 1 -001- 1 -100- 1 -.names n_n4296 [2060] [6289] [6290] -11- 1 -1-1 1 -.names n_n3578 n_n4074 [6291] -11 1 -.names n_n3769 n_n4367 nrq3_15 [2044] [6295] ----1 1 -111- 1 -.names n_n4047 n_n4367 nrq3_15 [2039] [6296] ----1 1 -111- 1 -.names nsr3_14 nsr3_17 [6299] -10 1 -.names n_n4381 n_n4305 n_n4357 [1008] [6300] --11- 1 -1--1 1 -.names n_n3493 preset [6302] -10 1 -.names n_n3170 n_n3242 [6303] -11 1 -.names n_n3099 n_n3936 [6306] -11 1 -.names n_n3831 n_n4026 n_n3852 [6309] -0-- 1 --1- 1 --00 1 -.names n_n3657 n_n4211 [6310] -11 1 -.names n_n4324 n_n4367 nrq3_15 [1912] [6312] ----1 1 -111- 1 -.names n_n4366 n_n4367 nrq3_15 [1901] [6317] ----1 1 -111- 1 -.names n_n3475 n_n4367 nrq3_15 [1896] [6318] ----1 1 -111- 1 -.names n_n4122 n_n3556 [6321] -11 1 -.names n_n3250 n_n3085 [6322] -11 1 -.names tin_pready_0_0_ n_n4108 n_n3354 nsr3_3 [6324] -00-1 1 -0-01 1 --101 1 -.names n_n3354 preset [6325] -10 1 -.names n_n3766 n_n4275 [6330] -11 1 -.names n_n3955 n_n3954 n_n4305 [1008] [6332] -1--1 1 -011- 1 -101- 1 -.names nlc3_3 nlak4_2 n_n4263 [6333] --1- 1 -1-0 1 -.names n_n4052 [1008] [1632] [6337] ---1 1 -11- 1 -.names n_n4099 n_n4305 [1119] [1008] [6338] -1--1 1 -111- 1 -010- 1 -.names n_n4275 n_n3766 [896] [1012] [6342] -0111 1 -.names n_n3954 n_n3955 [6343] -00 1 -.names n_n4305 n_n4006 n_n3848 [6343] [6346] -1001 1 -.names n_n3294 n_n4357 [942] [6346] [6349] -0011 1 -.names preset n_n4045 n_n4367 [6299] [6350] -1--- 1 --0-- 1 ---01 1 -.names n_n3707 preset [6354] -10 1 -.names n_n4367 n_n4057 [6355] -11 1 -.names nsr3_14 nsr3_17 [6356] -0- 1 --1 1 -.names preset n_n4045 n_n4367 [6299] [6357] -1--- 1 --0-- 1 ---01 1 -.names n_n3954 n_n4305 [1008] [6358] -11- 1 -0-1 1 -.names preset n_n4045 n_n4367 [6299] [6361] -011- 1 -01-0 1 -.names n_n4029 n_n4305 n_n4006 [1008] [6366] --11- 1 -1--1 1 -.names n_n3724 n_n3766 n_n4227 n_n3814 [6370] -1011 1 -.names [1015] n_n3707 [6374] -11 1 -.names preset nak3_17 [1063] [6374] [6376] -1--- 1 --1-- 1 ---11 1 -.names n_n3845 n_n4305 n_n3848 [1008] [6379] --11- 1 -1--1 1 -.names n_n3865 [984] n_n4305 [1008] [6380] -1--1 1 -111- 1 -001- 1 -.names [1070] [916] [6385] -11 1 -.names preset n_n3709 n_n135 [6290] [6386] -0101 1 -.names n_n3563 n_n4067 [6387] -10 1 -.names n_n4093 n_n3788 [1013] [2264] [6389] -1010 1 -.end diff --git a/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.act b/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.act deleted file mode 100644 index a58956a8e..000000000 --- a/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.act +++ /dev/null @@ -1,67 +0,0 @@ -cint01 0.485400 0.188600 -n01 0.489000 0.213200 -cint02 0.502400 0.203200 -n02 0.509200 0.195200 -cint03 0.507200 0.192200 -n03 0.502400 0.201600 -cint04 0.463200 0.199400 -n04 0.522000 0.191000 -n05 0.486800 0.204800 -reg0 0.463000 0.195400 -reg1 0.487400 0.196600 -reg2 0.506200 0.195000 -reg3 0.492200 0.208200 -reg4 0.507200 0.204800 -reg5 0.500400 0.200600 -reg6 0.500800 0.203400 -reg7 0.509600 0.198800 -reg8 0.492200 0.188000 -reg9 0.504800 0.204400 -reg10 0.507600 0.203200 -reg11 0.494200 0.203600 -clk 0.534600 0.203800 -a_0 0.478200 0.203800 -a_1 0.514800 0.208600 -a_2 0.505800 0.204600 -a_3 0.500000 0.195200 -b_0 0.530800 0.192800 -b_1 0.495800 0.195400 -b_2 0.496600 0.201200 -b_3 0.492000 0.200200 -cin 0.502600 0.202200 -e 0.495200 0.201000 -f 0.504000 0.203400 -g 0.498200 0.202000 -reg_a_0 0.478200 0.203800 -reg_a_1 0.514800 0.208600 -reg_a_2 0.505800 0.204600 -reg_a_3 0.500000 0.195200 -reg_b_0 0.530800 0.192800 -reg_b_1 0.495800 0.195400 -reg_b_2 0.496600 0.201200 -reg_b_3 0.492000 0.200200 -reg_cin 0.502600 0.202200 -sum_0 0.489000 0.213200 -sum_1 0.509200 0.195200 -sum_2 0.502400 0.201600 -sum_3 0.522000 0.191000 -cout 0.486800 0.204800 -ref0 0.000000 0.000000 -n57 0.478200 0.097457 -n62 0.514800 0.107387 -n67 0.505800 0.103487 -n72 0.500000 0.097600 -n77 0.530800 0.102338 -n82 0.495800 0.096879 -n87 0.496600 0.099916 -n92 0.492000 0.098498 -n97 0.502600 0.101626 -d0 0.617800 0.046719 -x 0.492200 0.102476 -y 0.509600 0.101308 -z 0.494200 0.100619 -n102 0.489000 0.104255 -n106 0.509200 0.099396 -n110 0.502400 0.101284 -n114 0.522000 0.099702 -n118 0.486800 0.099697 diff --git a/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif b/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif deleted file mode 100644 index f7ed4cb33..000000000 --- a/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif +++ /dev/null @@ -1,94 +0,0 @@ -# Benchmark "test" written by ABC on Tue Apr 30 17:17:10 2019 -.model test_modes -.inputs clk a_0 a_1 a_2 a_3 b_0 b_1 b_2 b_3 cin e f g -.outputs sum_0 sum_1 sum_2 sum_3 cout x y z - -.latch n57 reg_a_0 re clk 0 -.latch n62 reg_a_1 re clk 0 -.latch n67 reg_a_2 re clk 0 -.latch n72 reg_a_3 re clk 0 -.latch n77 reg_b_0 re clk 0 -.latch n82 reg_b_1 re clk 0 -.latch n87 reg_b_2 re clk 0 -.latch n92 reg_b_3 re clk 0 -.latch n97 reg_cin re clk 0 -.latch n102 sum_0 re clk 0 -.latch n106 sum_1 re clk 0 -.latch n110 sum_2 re clk 0 -.latch n114 sum_3 re clk 0 -.latch n118 cout re clk 0 - - -.subckt adder a=reg_a_0 b=reg_b_0 cin=reg_cin cout=cint01 sumout=n01 -.subckt adder a=reg_a_1 b=reg_b_1 cin=cint01 cout=cint02 sumout=n02 -.subckt adder a=reg_a_2 b=reg_b_2 cin=cint02 cout=cint03 sumout=n03 -.subckt adder a=reg_a_3 b=reg_b_3 cin=cint03 cout=cint04 sumout=n04 -.subckt adder a=ref0 b=ref0 cin=cint04 cout=unconn sumout=n05 - -.subckt shift D=d0 clk=clk Q=reg0 -.subckt shift D=reg0 clk=clk Q=reg1 -.subckt shift D=reg1 clk=clk Q=reg2 -.subckt shift D=reg2 clk=clk Q=reg3 -.subckt shift D=reg3 clk=clk Q=reg4 -.subckt shift D=reg4 clk=clk Q=reg5 -.subckt shift D=reg5 clk=clk Q=reg6 -.subckt shift D=reg6 clk=clk Q=reg7 -.subckt shift D=reg7 clk=clk Q=reg8 -.subckt shift D=reg8 clk=clk Q=reg9 -.subckt shift D=reg9 clk=clk Q=reg10 -.subckt shift D=reg10 clk=clk Q=reg11 - -.names ref0 - 0 -.names a_0 n57 -1 1 -.names a_1 n62 -1 1 -.names a_2 n67 -1 1 -.names a_3 n72 -1 1 -.names b_0 n77 -1 1 -.names b_1 n82 -1 1 -.names b_2 n87 -1 1 -.names b_3 n92 -1 1 -.names cin n97 -1 1 -.names e f g d0 -1-1 1 --0- 1 -.names reg3 x -1 1 -.names reg7 y -1 1 -.names reg11 z -1 1 -.names n01 n102 -1 1 -.names n02 n106 -1 1 -.names n03 n110 -1 1 -.names n04 n114 -1 1 -.names n05 n118 -1 1 -.end - - -.model adder -.inputs a b cin -.outputs cout sumout -.blackbox -.end - - -.model shift -.inputs D clk -.outputs Q -.blackbox -.end diff --git a/fpga_flow/benchmarks/List/fpga_spice_bench.txt b/fpga_flow/benchmarks/List/fpga_spice_bench.txt deleted file mode 100644 index 9457c6ff3..000000000 --- a/fpga_flow/benchmarks/List/fpga_spice_bench.txt +++ /dev/null @@ -1,32 +0,0 @@ -## Circuit Names, fixed routing channel width, -#### One # worked, ## did not -s298.blif, 60 -#elliptic.blif, 60 -#simple_spi.blif, 60 -#i2c.blif, 60 -#pci_conf_cyc_addr_dec.blif, 60 -#sasc.blif, 60 -#usb_phy.blif, 60 -#steppermotordrive.blif, 60 -#stereovision3.blif, 60 -#dalu.blif, 60 -#C1355.blif, 60 -#alu4.blif, 60 -#priority.blif, 60 -apex7.blif, 60 -#int2float.blif, 60 -#planet.blif, 60 -#alu2.blif, 60 -#mult32a.blif, 60 -#tbk.blif, 60 -#sqrt8ml.blif, 60 -#ss_pcm.blif, 60 -#scf.blif, 60 -#s820.blif, 60 -#ctrl.blif, 60 -#cavlc.blif, 60 -#router.blif, 60 -traffic.blif, 60 -#e64.blif, 60 -#s1488.blif, 60 -#fsm8_8_13.blif, 60 diff --git a/fpga_flow/benchmarks/List/mcnc_benchmark.txt b/fpga_flow/benchmarks/List/mcnc_benchmark.txt deleted file mode 100644 index 799289cea..000000000 --- a/fpga_flow/benchmarks/List/mcnc_benchmark.txt +++ /dev/null @@ -1,21 +0,0 @@ -# Circuit Names, fixed routing channel width, -alu4/*.v, 300 -apex2/*.v, 300 -apex4/*.v, 300 -bigkey/*.v, 300 -clma/*.v, 300 -des/*.v, 300 -diffeq/*.v, 300 -dsip/*.v, 300 -elliptic/*.v, 300 -ex1010/*.v, 300 -ex5p/*.v, 300 -frisc/*.v, 300 -misex3/*.v, 300 -pdc/*.v, 300 -s298/*.v, 30 -s38417/*.v, 300 -s38584/*.v, 300 -seq/*.v, 300 -spla/*.v, 300 -tseng/*.v, 300 diff --git a/fpga_flow/benchmarks/List/mcnc_big20.txt b/fpga_flow/benchmarks/List/mcnc_big20.txt deleted file mode 100644 index c7ef1af76..000000000 --- a/fpga_flow/benchmarks/List/mcnc_big20.txt +++ /dev/null @@ -1,21 +0,0 @@ -# Circuit Names, fixed routing channel width, -alu4.blif, 120 -apex2.blif, 120 -apex4.blif, 120 -bigkey.blif, 120 -clma.blif, 120 -des.blif, 120 -diffeq.blif, 120 -dsip.blif, 120 -elliptic.blif, 120 -ex1010.blif, 120 -ex5p.blif, 120 -frisc.blif, 120 -misex3.blif, 120 -pdc.blif, 120 -s298.blif, 30 -s38417.blif, 120 -s38584.1.blif, 120 -seq.blif, 120 -spla.blif, 120 -tseng.blif, 120 diff --git a/fpga_flow/benchmarks/List/tuto_benchmark.txt b/fpga_flow/benchmarks/List/tuto_benchmark.txt deleted file mode 100644 index 8c59d3b57..000000000 --- a/fpga_flow/benchmarks/List/tuto_benchmark.txt +++ /dev/null @@ -1,2 +0,0 @@ -# Circuit Names, fixed routing channel width, -s298/*.v, 200 diff --git a/fpga_flow/benchmarks/Verilog/.gitignore b/fpga_flow/benchmarks/Verilog/.gitignore deleted file mode 100644 index 2e39c18d2..000000000 --- a/fpga_flow/benchmarks/Verilog/.gitignore +++ /dev/null @@ -1 +0,0 @@ -lattice_ultra_example_source/ diff --git a/fpga_flow/benchmarks/Verilog/MCNC/alu4/alu4.v b/fpga_flow/benchmarks/Verilog/MCNC/alu4/alu4.v deleted file mode 100644 index d5c9a0d0d..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/alu4/alu4.v +++ /dev/null @@ -1,802 +0,0 @@ -// Benchmark "TOP" written by ABC on Mon Feb 4 10:08:03 2019 - -module alu4 ( - i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, - i_11_, i_12_, i_13_, - o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_ ); - input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, - i_10_, i_11_, i_12_, i_13_; - output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_; - wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, - n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, - n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, - n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, - n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, - n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, - n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, - n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, - n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, - n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, - n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, - n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, - n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, - n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, - n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, - n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, - n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, - n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, - n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, - n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, - n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, - n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, - n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, - n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, - n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, - n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, - n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, - n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, - n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, - n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, - n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, - n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, - n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, - n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, - n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, - n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, - n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, - n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, - n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, - n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, - n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, - n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, - n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, - n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, - n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, - n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, - n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, - n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, - n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, - n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, - n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, - n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, - n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, - n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, - n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, - n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, - n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, - n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, - n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, - n748, n749, n750, n751; - assign o_0_ = ~n42; - assign o_1_ = ~n509; - assign o_2_ = ~n502; - assign o_3_ = ~n488; - assign o_4_ = ~n41; - assign o_5_ = ~n659 | ~n662 | n40 | ~n658 | n38 | n39 | n36 | n37; - assign o_6_ = ~n35; - assign o_7_ = ~n636 | ~n637 | n34 | ~n576 | n32 | n33 | n30 | n31; - assign n30 = ~i_9_ & (~n163 | n165 | n168); - assign n31 = i_9_ & n65 & n419; - assign n32 = ~i_5_ & (~n625 | (~n238 & n250)); - assign n33 = i_9_ & (n66 | ~n621 | ~n622); - assign n34 = n244 | n246 | n240 | n242 | ~n630 | ~n632 | n248 | n249; - assign n35 = n278 & n279 & (~i_2_ | n277); - assign n36 = i_11_ & (~n650 | (~n266 & n360)); - assign n37 = i_2_ & n361 & n272; - assign n38 = ~n71 & ~n532; - assign n39 = ~n562 & (~n648 | (~i_13_ & ~n532)); - assign n40 = ~i_4_ & (~n647 | (~n59 & ~n281)); - assign n41 = n473 & n472 & n471 & n470 & n469 & ~n465 & ~n459 & ~n461; - assign n42 = ~n46 & n510 & (~i_0_ | n511); - assign n43 = ~i_1_ | ~i_3_; - assign n44 = ~i_5_ | n43; - assign n45 = ~i_8_ & i_10_; - assign n46 = i_3_ & (n45 | ~n435); - assign n47 = ~n67 & (~i_6_ | ~i_10_); - assign n48 = (n521 | n52) & (n56 | n120); - assign n49 = i_1_ | n445; - assign n50 = i_11_ | n116; - assign n51 = n48 & (n49 | n50); - assign n52 = i_12_ | n116; - assign n53 = i_0_ | n225; - assign n54 = (i_11_ | n53) & (n49 | n52); - assign n55 = ~i_6_ | i_7_; - assign n56 = i_0_ | n212; - assign n57 = ~i_2_ | i_0_ | i_1_; - assign n58 = (i_6_ | n57) & (n55 | n56); - assign n59 = ~i_3_ | n225; - assign n60 = ~i_3_ | n445; - assign n61 = (~i_6_ | n60) & (~i_5_ | n59); - assign n62 = i_0_ | n63; - assign n63 = i_3_ | i_2_; - assign n64 = n62 & (~i_5_ | n63); - assign n65 = ~i_12_ & i_13_; - assign n66 = n65 & (~n613 | (i_8_ & ~n379)); - assign n67 = i_6_ & n519; - assign n68 = ~n158 & (~n615 | (n67 & ~n400)); - assign n69 = (i_7_ | n200) & (i_6_ | n62); - assign n70 = n69 & (i_8_ | n56); - assign n71 = ~i_12_ | n116; - assign n72 = (~i_1_ | n71) & (~i_6_ | ~n348); - assign n73 = ~i_1_ & i_6_; - assign n74 = (~i_0_ | n73) & (~i_1_ | i_5_); - assign n75 = ~n304 & ~i_9_ & ~n77; - assign n76 = i_3_ & (n75 | (~n71 & ~n98)); - assign n77 = ~i_11_ | n116; - assign n78 = i_8_ | i_6_; - assign n79 = n77 | n78 | ~i_2_ | i_9_; - assign n80 = ~i_0_ | n63; - assign n81 = ~i_0_ | n195; - assign n82 = (i_7_ | n81) & (i_6_ | n80); - assign n83 = i_0_ & (n76 | ~n79 | ~n627); - assign n84 = i_3_ | ~i_11_ | n56 | ~n348; - assign n85 = n116 | n400 | ~i_3_ | i_9_; - assign n86 = n178 | ~i_5_ | n72; - assign n87 = n516 | n177 | ~n338; - assign n88 = i_9_ | n74 | n522 | n77; - assign n89 = n88 & n87 & n86 & n85 & ~n83 & n84; - assign n90 = (n99 | n157) & (n134 | n521); - assign n91 = ~i_6_ | n522; - assign n92 = n90 & (n91 | n49); - assign n93 = (~n102 | n521) & (~n67 | n157); - assign n94 = (n518 | n49) & (n520 | n400); - assign n95 = n93 & n94; - assign n96 = (~n103 | n134) & (n53 | n107); - assign n97 = n96 & (n57 | n91); - assign n98 = ~i_6_ | n272; - assign n99 = i_8_ | ~i_6_ | ~i_7_; - assign n100 = n98 & n97 & (n99 | n56); - assign n101 = i_5_ & n365; - assign n102 = ~i_6_ & n519; - assign n103 = ~i_2_ & ~i_0_ & i_1_; - assign n104 = n101 & (~n607 | (n102 & n103)); - assign n105 = i_11_ | ~n166; - assign n106 = i_10_ | n304; - assign n107 = i_6_ | n522; - assign n108 = (n107 | n50) & (n105 | n106); - assign n109 = i_12_ | n113; - assign n110 = i_11_ | n113; - assign n111 = (~n67 | n109) & (n99 | n110); - assign n112 = i_11_ | i_12_; - assign n113 = i_9_ | i_13_; - assign n114 = i_3_ | i_10_ | n112 | n113; - assign n115 = i_5_ | n312; - assign n116 = i_10_ | i_13_; - assign n117 = (~i_10_ | n115) & (n116 | ~n164); - assign n118 = i_13_ & (~n600 | (~n547 & ~n548)); - assign n119 = i_5_ | n515; - assign n120 = i_12_ | ~n338; - assign n121 = (n119 | n120) & (~n164 | ~n239); - assign n122 = n65 & (~n599 | (~i_3_ & ~i_11_)); - assign n123 = n555 | n518 | n554; - assign n124 = n553 | n134 | n552; - assign n125 = n522 | n198 | ~n247; - assign n126 = ~n348 | ~n67 | ~n101; - assign n127 = n449 | n107 | ~n338; - assign n128 = n524 | n99 | ~n319; - assign n129 = (n544 | n546) & (n121 | n520); - assign n130 = n129 & n128 & n127 & n126 & n125 & n124 & ~n122 & n123; - assign n131 = (n107 | ~n419) & (n91 | ~n402); - assign n132 = (n171 | n151) & (n150 | n551); - assign n133 = n597 & n598 & (n545 | n550); - assign n134 = ~i_7_ | n78; - assign n135 = ~n101 | ~n239; - assign n136 = n132 & n133 & (n134 | n135); - assign n137 = i_4_ | ~i_0_ | ~i_1_; - assign n138 = i_4_ | n445; - assign n139 = (~i_6_ | n138) & (~i_7_ | n137); - assign n140 = ~n524 & ~n220 & i_2_ & ~i_8_; - assign n141 = n546 | n549; - assign n142 = n162 | n107 | n158; - assign n143 = n555 | ~n102 | n554; - assign n144 = n553 | n91 | n552; - assign n145 = (n194 | n151) & (n198 | n551); - assign n146 = (n134 | n543) & (n547 | n550); - assign n147 = n146 & n145 & n144 & n143 & n141 & n142; - assign n148 = (n171 | n551) & (n99 | n543); - assign n149 = n595 & n596 & (n545 | n549); - assign n150 = ~i_5_ | n201; - assign n151 = ~n65 | ~n264; - assign n152 = n148 & n149 & (n150 | n151); - assign n153 = (n99 | ~n402) & (n91 | ~n419); - assign n154 = (n544 | n547) & (n172 | n198); - assign n155 = n593 & n594 & (n542 | n546); - assign n156 = n154 & n155 & (n91 | n135); - assign n157 = ~i_0_ | n212; - assign n158 = ~i_5_ | n312; - assign n159 = n158 | n157 | n134; - assign n160 = n115 | n99 | ~n103; - assign n161 = i_2_ | n312; - assign n162 = ~i_10_ | ~n319; - assign n163 = n161 | n162 | ~i_5_ | n91; - assign n164 = ~i_5_ & i_3_ & i_4_; - assign n165 = n164 & ~n77 & i_1_ & ~i_7_; - assign n166 = ~i_12_ & ~i_13_; - assign n167 = i_10_ & i_11_; - assign n168 = n166 & n167 & (~n159 | ~n160); - assign n169 = (n542 | n545) & (n541 | n150); - assign n170 = (n107 | n135) & (~n446 | n544); - assign n171 = i_3_ | n539; - assign n172 = ~n65 | ~n437; - assign n173 = n169 & n170 & (n171 | n172); - assign n174 = (~n446 | n542) & (n171 | n541); - assign n175 = (n544 | n545) & (n91 | n543); - assign n176 = n174 & n175 & (n172 | n150); - assign n177 = i_10_ | n522; - assign n178 = ~i_8_ | n272; - assign n179 = n177 & n178; - assign n180 = (~n460 | n591) & (n179 | ~n463); - assign n181 = n592 & (n533 | n56); - assign n182 = n106 & n98; - assign n183 = n180 & n181 & (n182 | ~n385); - assign n184 = (~n340 | n535) & (n106 | n449); - assign n185 = i_8_ | n534; - assign n186 = ~i_4_ | n212; - assign n187 = n184 & (n185 | n186); - assign n188 = (~n536 | n537) & (n335 | n538); - assign n189 = (n186 | n474) & (n98 | ~n101); - assign n190 = ~i_5_ | n272; - assign n191 = n188 & n189 & (n190 | ~n340); - assign n192 = (n518 | n521) & (n520 | n157); - assign n193 = n192 & (n49 | ~n102); - assign n194 = i_3_ | n214; - assign n195 = i_1_ | i_3_; - assign n196 = n194 & (~i_5_ | n195); - assign n197 = ~i_6_ | i_0_ | i_3_; - assign n198 = i_3_ | n516; - assign n199 = n198 & (i_5_ | n195); - assign n200 = i_0_ | n195; - assign n201 = i_3_ | i_6_; - assign n202 = n200 & n199 & (i_0_ | n201); - assign n203 = ~i_6_ | ~i_0_ | ~i_3_; - assign n204 = i_1_ & ~i_6_; - assign n205 = (i_2_ | ~i_6_) & (~i_7_ | n204); - assign n206 = n517 | i_6_ | n749; - assign n207 = n517 | i_1_ | i_7_; - assign n208 = i_11_ | n435; - assign n209 = n206 & n207 & (n205 | n208); - assign n210 = i_5_ | n63; - assign n211 = i_2_ | n516; - assign n212 = i_1_ | i_2_; - assign n213 = n211 & (i_5_ | n212); - assign n214 = ~i_5_ | ~i_6_; - assign n215 = (~i_5_ | n212) & (i_2_ | n214); - assign n216 = (~i_5_ | n225) & (~i_2_ | n214); - assign n217 = ~i_6_ | n445; - assign n218 = n216 & n217; - assign n219 = ~i_7_ | ~i_1_ | ~i_5_; - assign n220 = ~i_1_ & ~i_6_; - assign n221 = n219 & (~i_0_ | ~i_7_ | n220); - assign n222 = i_10_ & ~n435 & (~n218 | ~n221); - assign n223 = ~i_2_ | n516; - assign n224 = i_6_ | n445; - assign n225 = ~i_1_ | ~i_2_; - assign n226 = n223 & n224 & (i_5_ | n225); - assign n227 = n226 & (i_7_ | n74); - assign n228 = (~i_0_ | i_6_) & (~i_1_ | i_5_); - assign n229 = (i_6_ | n138) & (i_7_ | n137); - assign n230 = n73 | n119 | ~i_2_ | ~i_8_; - assign n231 = n230 & (n229 | ~n475); - assign n232 = (n53 | ~n67) & (~n103 | n518); - assign n233 = n232 & (n57 | ~n102); - assign n234 = ~i_4_ | n225; - assign n235 = ~i_4_ | n557; - assign n236 = (i_6_ | n235) & (i_8_ | n234); - assign n237 = i_4_ & (~n623 | (~i_1_ & ~n177)); - assign n238 = ~n237 & (i_6_ | i_10_ | ~n536); - assign n239 = ~i_9_ & n338; - assign n240 = n239 & n164 & ~n233; - assign n241 = n406 & ~i_10_ & ~i_13_; - assign n242 = ~n119 & (~n580 | (~n92 & n241)); - assign n243 = ~i_3_ & ~i_8_; - assign n244 = ~n525 & (n140 | (~n139 & n243)); - assign n245 = n383 & ~i_9_ & ~i_13_; - assign n246 = ~n524 & (~n582 | (~n193 & n245)); - assign n247 = ~i_11_ & i_13_; - assign n248 = n247 & (~n584 | (~n223 & ~n528)); - assign n249 = n65 & (~n586 | ~n588 | ~n590); - assign n250 = n338 & i_12_; - assign n251 = n250 & (~n183 | ~n187 | ~n191); - assign n252 = ~n71 & (~n609 | ~n610 | ~n611); - assign n253 = ~n247 & (i_4_ | ~i_8_ | ~n406); - assign n254 = (~i_3_ | n208) & (~n338 | n533); - assign n255 = n253 & n254 & (n120 | ~n475); - assign n256 = ~i_7_ | i_10_; - assign n257 = i_4_ | ~n383; - assign n258 = (~i_7_ | n257) & (n256 | ~n318); - assign n259 = i_7_ & n45; - assign n260 = (i_8_ | n258) & (~n259 | n559); - assign n261 = n260 & ~n731 & (i_7_ | n255); - assign n262 = ~i_7_ | ~i_9_; - assign n263 = n262 & (i_7_ | ~i_10_); - assign n264 = i_10_ & ~i_7_ & i_8_; - assign n265 = i_12_ & (n264 | ~n548); - assign n266 = ~i_10_ | n522; - assign n267 = i_8_ | n262; - assign n268 = ~n265 & (~i_11_ | (n266 & n267)); - assign n269 = (n110 | ~n243) & (n109 | ~n475); - assign n270 = ~i_4_ | n116; - assign n271 = n270 & (~i_8_ | n52); - assign n272 = ~i_7_ | i_9_; - assign n273 = ~i_4_ | n272; - assign n274 = (i_7_ | n271) & (i_13_ | n273); - assign n275 = n282 & (i_4_ | n268); - assign n276 = n556 & n638 & (i_3_ | n274); - assign n277 = n275 & n276 & (~i_13_ | n263); - assign n278 = ~n750 & (n548 | n559); - assign n279 = n644 & n645 & (i_2_ | n261); - assign n280 = ~i_6_ | ~i_9_; - assign n281 = n280 & (i_6_ | ~i_10_); - assign n282 = n332 | n116; - assign n283 = (n523 & (~i_7_ | n733)) | (i_7_ & n733); - assign n284 = i_2_ | i_13_; - assign n285 = n282 & (n283 | n284); - assign n286 = i_10_ | i_7_; - assign n287 = i_11_ | n286; - assign n288 = i_11_ | i_13_; - assign n289 = (~n166 | n287) & (n177 | n288); - assign n290 = i_8_ | n272; - assign n291 = (n288 | n290) & (~n166 | n178); - assign n292 = (n289 & (~i_6_ | n291)) | (i_6_ & n291); - assign n293 = (n523 & (~i_8_ | n733)) | (i_8_ & n733); - assign n294 = n292 & (i_13_ | n293); - assign n295 = (~i_7_ & n566) | (n565 & (i_7_ | n566)); - assign n296 = i_7_ | n435; - assign n297 = n295 & (~i_6_ | ~i_11_ | n296); - assign n298 = n287 & (i_12_ | n256); - assign n299 = ~i_2_ & ~n751 & (i_6_ | ~n298); - assign n300 = ~n299 & (~i_4_ | ~n578); - assign n301 = n591 | i_2_ | ~i_4_; - assign n302 = n300 & n301 & (n182 | ~n365); - assign n303 = ~i_7_ | n280; - assign n304 = i_6_ | i_7_; - assign n305 = n303 & (~i_10_ | (~i_9_ & n304)); - assign n306 = (i_6_ & ~n540) | (~n266 & (~i_6_ | ~n540)); - assign n307 = ~i_4_ & (~n577 | (i_11_ & n306)); - assign n308 = (n294 & (~i_3_ | n297)) | (i_3_ & n297); - assign n309 = (~i_13_ & n302) | (n281 & (i_13_ | n302)); - assign n310 = ~n307 & n656 & (~i_2_ | n305); - assign n311 = n310 & n309 & n308 & n285; - assign n312 = ~i_3_ | i_4_; - assign n313 = (n312 | ~n406) & (n284 | ~n383); - assign n314 = (~i_4_ | ~n338) & (i_3_ | n120); - assign n315 = ~n247 & (~i_3_ | ~n406 | n548); - assign n316 = (~i_2_ | n530) & (~i_7_ | n313); - assign n317 = n315 & n316 & (n314 | n178); - assign n318 = i_4_ & n348; - assign n319 = ~i_11_ & n348; - assign n320 = ~n177 & (n318 | (~i_3_ & n319)); - assign n321 = ~n402 | ~i_2_ | i_7_; - assign n322 = ~n319 | n563; - assign n323 = ~n383 | ~i_3_ | n266; - assign n324 = n257 | ~i_2_ | i_8_; - assign n325 = ~n65 & (i_7_ | n312 | ~n383); - assign n326 = n325 & n324 & n323 & n322 & ~n320 & n321; - assign n327 = i_11_ | ~n496 | n558 | ~n563; - assign n328 = (n317 & (~i_6_ | n326)) | (i_6_ & n326); - assign n329 = n327 & n328 & (n91 | n257); - assign n330 = ~i_11_ | n514; - assign n331 = ~n166 | ~n475; - assign n332 = ~i_4_ | i_9_; - assign n333 = (n332 | n77) & (n330 | n331); - assign n334 = ~n517 & i_3_ & i_12_; - assign n335 = i_1_ | n63; - assign n336 = ~i_11_ | ~n166; - assign n337 = (n335 | n336) & (n186 | ~n239); - assign n338 = i_11_ & ~i_13_; - assign n339 = i_4_ & (~n652 | (~n335 & n338)); - assign n340 = ~i_1_ & n365; - assign n341 = i_7_ & (n334 | (n340 & n239)); - assign n342 = n734 & (~i_8_ | n337); - assign n343 = (n208 | n561) & (n404 | n356); - assign n344 = (n517 | n557) & (~n45 | n59); - assign n345 = n344 & n343 & n342 & ~n341 & n333 & ~n339; - assign n346 = ~i_2_ | i_12_; - assign n347 = (~i_8_ | n59) & (n346 | ~n391); - assign n348 = i_12_ & ~i_13_; - assign n349 = n348 & (~n654 | (i_4_ & ~n335)); - assign n350 = n655 & (i_8_ | ~n402 | n561); - assign n351 = ~n349 & n350 & (~i_9_ | n347); - assign n352 = ~i_8_ | i_9_; - assign n353 = (~n263 | ~n340) & (n186 | n352); - assign n354 = i_10_ | n78; - assign n355 = ~i_6_ | n352; - assign n356 = ~i_1_ | n312; - assign n357 = (n303 | n356) & (~n259 | ~n360); - assign n358 = ~n573 & (~i_4_ | i_13_ | ~n496); - assign n359 = ~n512 & (i_6_ | i_11_); - assign n360 = i_3_ & n204; - assign n361 = ~i_6_ & n419; - assign n362 = ~i_9_ | ~i_11_; - assign n363 = ~i_12_ | n362; - assign n364 = ~i_4_ | n113; - assign n365 = ~i_3_ & i_4_; - assign n366 = ~i_9_ | ~i_12_; - assign n367 = n364 & (n365 | n366); - assign n368 = (~i_9_ & n572) | (~i_13_ & (i_9_ | n572)); - assign n369 = i_3_ | n111; - assign n370 = ~n166 | i_2_ | n98; - assign n371 = (~i_1_ | n280) & (n363 | ~n391); - assign n372 = (~n67 | n367) & (i_4_ | n363); - assign n373 = ~n737 & n372 & n371 & n370 & n368 & n369; - assign n374 = ~i_4_ & (~n564 | (~n107 & n167)); - assign n375 = ~n736 & (~i_10_ | (~i_13_ & ~n204)); - assign n376 = ~n374 & n687 & (n107 | n270); - assign n377 = n375 & n376 & (i_3_ | n108); - assign n378 = i_7_ | n516; - assign n379 = ~i_7_ | n214; - assign n380 = (n113 | n379) & (n378 | n116); - assign n381 = ~i_2_ & (~n686 | (~n270 & ~n440)); - assign n382 = ~n53 & i_3_ & ~i_8_; - assign n383 = i_11_ & ~i_12_; - assign n384 = n383 & i_10_ & ~i_0_ & i_2_; - assign n385 = ~i_0_ & n365; - assign n386 = ~i_6_ & (n384 | (~n71 & n385)); - assign n387 = (n56 | ~n319) & (n53 | ~n402); - assign n388 = i_0_ | n43; - assign n389 = ~n386 & n387 & (n257 | n388); - assign n390 = (~i_7_ | n81) & (~i_6_ | n80); - assign n391 = i_8_ & i_3_; - assign n392 = ~n400 & (i_7_ | n391); - assign n393 = (i_3_ & n553) | (~n241 & (~i_3_ | n553)); - assign n394 = n257 & n393 & (~i_4_ | n71); - assign n395 = ~i_12_ | n572; - assign n396 = ~n65 & (i_2_ | n106 | ~n319); - assign n397 = n395 & n396 & (n394 | n107); - assign n398 = ~i_7_ | n362; - assign n399 = (i_2_ | n355) & (n204 | n178); - assign n400 = ~i_1_ | n445; - assign n401 = (~i_8_ | n400) & (~i_6_ | n60); - assign n402 = i_10_ & ~i_12_; - assign n403 = n402 & (n382 | (~i_0_ & n204)); - assign n404 = i_7_ | ~n167; - assign n405 = n167 & (~n718 | (~i_8_ & ~n400)); - assign n406 = ~i_11_ & i_12_; - assign n407 = n406 & (~n674 | (i_8_ & ~n53)); - assign n408 = ~i_0_ | n43; - assign n409 = ~n405 & ~n407 & (n404 | n408); - assign n410 = ~n247 & (~i_1_ | i_11_ | n280); - assign n411 = n672 & (~n67 | (~n423 & n673)); - assign n412 = n410 & n411 & (~n73 | n336); - assign n413 = ~n385 | ~i_6_ | ~n239; - assign n414 = ~n166 | ~i_11_ | n56; - assign n415 = n413 & n414 & (n200 | ~n423); - assign n416 = n238 & (~i_4_ | i_6_ | n177); - assign n417 = ~i_7_ & n419; - assign n418 = n417 & i_2_ & i_12_; - assign n419 = i_10_ & ~i_11_; - assign n420 = n116 | ~i_4_ | i_8_; - assign n421 = n420 & (n50 | ~n243); - assign n422 = ~n53 & (~n530 | (i_3_ & ~n208)); - assign n423 = i_4_ & n239; - assign n424 = i_6_ & (n418 | (~n62 & n423)); - assign n425 = (n517 | n59) & (i_4_ | n409); - assign n426 = (~i_7_ | n415) & (i_0_ | n412); - assign n427 = (n82 | n271) & (~n338 | n416); - assign n428 = (~i_1_ | ~n361) & (~n423 | n671); - assign n429 = (n157 | n421) & (n400 | ~n670); - assign n430 = ~n422 & (n56 | n120 | ~n475); - assign n431 = n430 & n429 & n428 & n427 & n426 & n425 & n333 & ~n424; - assign n432 = n183 & (~i_4_ | i_10_ | n70); - assign n433 = i_7_ | i_9_ | i_11_; - assign n434 = n191 & (n215 | n433); - assign n435 = ~i_8_ | ~i_9_; - assign n436 = i_5_ & ~n558 & (~n540 | ~n568); - assign n437 = i_10_ & n519; - assign n438 = ~i_4_ & ~n539 & (n437 | ~n568); - assign n439 = ~i_8_ | n214; - assign n440 = i_8_ | n516; - assign n441 = (n366 | n439) & (~n167 | n440); - assign n442 = ~i_12_ & (~n158 | n417 | ~n530); - assign n443 = n435 | ~i_3_ | n112; - assign n444 = ~n442 & n443 & (i_11_ | n115); - assign n445 = ~i_0_ | ~i_2_; - assign n446 = ~i_6_ & i_3_ & i_5_; - assign n447 = n383 & (~n684 | (~i_7_ & n446)); - assign n448 = n406 & (~n685 | (i_7_ & ~n545)); - assign n449 = i_5_ | ~n365; - assign n450 = (~n338 | n449) & (~n101 | ~n348); - assign n451 = i_5_ | n522; - assign n452 = (n80 | n440) & (n81 | n451); - assign n453 = ~i_5_ | ~n519; - assign n454 = (n453 | n81) & (n439 | n80); - assign n455 = n137 & n408; - assign n456 = ~i_0_ | n312; - assign n457 = (n379 | n456) & (n455 | n453); - assign n458 = ~i_5_ & i_0_ & i_3_; - assign n459 = n167 & (~n663 | (~n107 & n458)); - assign n460 = i_4_ & ~i_0_ & ~i_2_; - assign n461 = ~n569 & (~n664 | (n239 & n460)); - assign n462 = ~i_5_ & n519; - assign n463 = i_4_ & ~i_0_ & ~i_1_; - assign n464 = n462 & (~n665 | (n239 & n463)); - assign n465 = ~n570 & (~n666 | (~n71 & n463)); - assign n466 = ~n571 & (~n667 | (~n71 & n460)); - assign n467 = n406 & (n438 | (n259 & ~n545)); - assign n468 = n383 & (n436 | (~n296 & n446)); - assign n469 = (n450 | n56) & (n441 | n60); - assign n470 = ~n464 & (~i_9_ | n158 | n400); - assign n471 = n702 & n701 & (n452 | n50); - assign n472 = n699 & n698 & (n457 | n366); - assign n473 = ~n740 & ~n739 & n709 & n707 & n706 & n705 & n703 & n704; - assign n474 = ~i_5_ | n352; - assign n475 = ~i_3_ & i_8_; - assign n476 = ~n56 & (i_7_ | n475); - assign n477 = (i_1_ | n537) & (n589 | n178); - assign n478 = ~n476 & n715 & (n335 | n474); - assign n479 = n477 & n478 & (i_0_ | ~i_5_); - assign n480 = ~n56 & (~i_7_ | n243); - assign n481 = n300 & (i_1_ | n359); - assign n482 = n746 & (i_5_ | n416); - assign n483 = n187 & (i_3_ | n293); - assign n484 = (n56 | ~n365) & (i_12_ | n479); - assign n485 = (n213 | n298) & (n215 | n574); - assign n486 = n716 & (i_1_ | n359 | n534); - assign n487 = n717 & (i_11_ | (n714 & n711)); - assign n488 = n487 & n486 & n485 & n484 & n483 & n482 & n432 & n434; - assign n489 = ~i_7_ | n366; - assign n490 = ~i_10_ | ~i_12_; - assign n491 = n489 & ~n496 & (i_7_ | n490); - assign n492 = (n747 & (~i_5_ | n748)) | (i_5_ & n748); - assign n493 = n492 & (~i_0_ | n281); - assign n494 = i_8_ | ~i_11_; - assign n495 = ~n496 & n494 & ~i_3_ & n263; - assign n496 = i_8_ & i_12_; - assign n497 = n496 & (~n221 | ~n379); - assign n498 = (n218 | n491) & (~i_1_ | n493); - assign n499 = n726 & (~i_12_ | (n61 & n723)); - assign n500 = n725 & (~i_11_ | (n719 & n722)); - assign n501 = n724 & (n494 | (n227 & n378)); - assign n502 = n501 & n500 & n498 & n499; - assign n503 = i_12_ | ~n475; - assign n504 = ~n46 & n503 & (i_11_ | ~n243); - assign n505 = (~n243 | ~n338) & (n113 | ~n391); - assign n506 = (~n243 | ~n247) & (~n65 | ~n475); - assign n507 = (n504 & (~i_4_ | n505)) | (i_4_ & n505); - assign n508 = n727 & n728 & (~i_13_ | ~n46); - assign n509 = n508 & n506 & n507; - assign n510 = (~i_1_ | n281) & (~i_2_ | n263); - assign n511 = (~i_5_ & ~i_10_) | (~i_9_ & (i_5_ | ~i_10_)); - assign n512 = i_6_ & ~i_12_; - assign n513 = i_9_ & (n392 | (n512 & i_1_)); - assign n514 = i_9_ | i_10_; - assign n515 = i_3_ | i_4_; - assign n516 = i_5_ | i_6_; - assign n517 = i_8_ | ~n419; - assign n518 = ~i_8_ | n55; - assign n519 = i_8_ & i_7_; - assign n520 = ~i_8_ | n304; - assign n521 = i_2_ | ~i_0_ | ~i_1_; - assign n522 = i_8_ | i_7_; - assign n523 = i_11_ | n514; - assign n524 = ~i_5_ | n515; - assign n525 = ~n348 | n523; - assign n526 = ~i_9_ | ~i_10_; - assign n527 = i_7_ | n526; - assign n528 = ~i_3_ | n526; - assign n529 = ~i_7_ | n526; - assign n530 = i_11_ | n262; - assign n531 = ~i_5_ | ~i_3_ | ~i_4_; - assign n532 = ~i_6_ | n332; - assign n533 = ~i_8_ | n332; - assign n534 = i_5_ | i_10_; - assign n535 = i_7_ | n534; - assign n536 = ~i_2_ & n365; - assign n537 = i_9_ | n214; - assign n538 = ~i_5_ | n332; - assign n539 = i_5_ | ~i_6_; - assign n540 = ~i_9_ | n522; - assign n541 = ~n247 | n540; - assign n542 = ~n65 | ~n259; - assign n543 = ~n239 | n449; - assign n544 = ~n247 | n296; - assign n545 = ~i_3_ | n539; - assign n546 = ~i_3_ | n516; - assign n547 = ~i_3_ | n214; - assign n548 = ~i_7_ | n435; - assign n549 = ~n247 | n548; - assign n550 = ~n65 | n266; - assign n551 = ~n247 | n267; - assign n552 = i_13_ | n115; - assign n553 = ~i_11_ | ~n402; - assign n554 = i_13_ | n158; - assign n555 = ~i_9_ | ~n406; - assign n556 = n114 & n528; - assign n557 = ~i_2_ | ~i_3_; - assign n558 = i_4_ | i_6_; - assign n559 = ~i_3_ | i_12_; - assign n560 = i_4_ | n225; - assign n561 = i_1_ | n557; - assign n562 = ~i_1_ | n63; - assign n563 = i_7_ | i_2_; - assign n564 = ~i_11_ | n490; - assign n565 = ~i_9_ | n490; - assign n566 = ~i_9_ | ~n167; - assign n567 = ~i_8_ | n286; - assign n568 = i_0_ | n557; - assign n569 = ~i_8_ | n539; - assign n570 = ~i_5_ | n522; - assign n571 = ~i_5_ | n78; - assign n572 = ~n220 | n288; - assign n573 = n243 & n319; - assign n574 = i_12_ | n272; - assign n575 = (~i_5_ & n419) | (n402 & (i_5_ | n419)); - assign n576 = (~i_4_ & n729) | (n89 & (i_4_ | n729)); - assign n577 = (~i_6_ & n564) | (n363 & (i_6_ | n564)); - assign n578 = (i_6_ & ~n178) | (~n177 & (~i_6_ | ~n178)); - assign n579 = i_10_ | i_13_ | ~n383 | n520; - assign n580 = n579 & (n233 | ~n245); - assign n581 = i_9_ | i_13_ | n99 | ~n406; - assign n582 = n581 & (n97 | ~n241); - assign n583 = n527 | ~i_3_ | n228; - assign n584 = n583 & (i_8_ | n227 | n526); - assign n585 = (n213 | n517) & (n210 | ~n361); - assign n586 = ~n222 & n585 & (n208 | n215); - assign n587 = n547 & n408 & n44 & n203; - assign n588 = (n587 | n529) & (i_0_ | n209); - assign n589 = n196 & n200 & n197; - assign n590 = (n530 | n589) & (n202 | ~n417); - assign n591 = n355 & n354; - assign n592 = (n273 | n200) & (n62 | n532); - assign n593 = n541 | n194; - assign n594 = n113 | n153 | n158; - assign n595 = ~n402 | n107 | n158; - assign n596 = ~n446 | n550; - assign n597 = ~n446 | n549; - assign n598 = n113 | n131 | n158; - assign n599 = (~n259 | n547) & (n194 | ~n519); - assign n600 = n528 & (n546 | n266); - assign n601 = n531 | ~n67 | n113; - assign n602 = n601 & (n117 | n107); - assign n603 = (n99 | n135) & (n198 | n151); - assign n604 = n602 & n603 & (n194 | n551); - assign n605 = (n108 | n119) & (n111 | n524); - assign n606 = ~n118 & n605 & (i_4_ | n556); - assign n607 = (n518 | n57) & (n53 | n520); - assign n608 = (n95 | n449) & (n92 | ~n164); - assign n609 = ~n104 & n608 & (n100 | n531); - assign n610 = (n537 | n235) & (n474 | n234); - assign n611 = (n273 | n408) & (n538 | n59); - assign n612 = n64 | ~i_6_ | i_11_; - assign n613 = n612 & (~i_10_ | n61); - assign n614 = i_10_ | ~n103 | ~n319 | n520; - assign n615 = n614 & (n58 | n162); - assign n616 = i_10_ | n157 | ~n319 | n518; - assign n617 = n616 & (n47 | n57 | n120); - assign n618 = n617 & (n520 | n521 | n50); - assign n619 = (n54 | ~n67) & (n51 | ~n102); - assign n620 = n161 | n534 | ~n102 | n120; - assign n621 = n620 & (i_4_ | n59 | ~n575); - assign n622 = ~n68 & (n115 | (n618 & n619)); - assign n623 = (i_2_ | n354) & (i_10_ | n335); - assign n624 = i_11_ | n266 | n59 | n558; - assign n625 = n624 & (i_9_ | n236 | n77); - assign n626 = n355 | ~i_2_ | n71; - assign n627 = n626 & (n220 | n71 | n178); - assign n628 = n332 | i_10_ | ~n250; - assign n629 = n628 & (~n166 | n231 | n330); - assign n630 = n629 & (~i_13_ | n378 | n517); - assign n631 = n531 | n193 | ~n239; - assign n632 = ~n251 & n631 & (~n103 | n176); - assign n633 = (n156 | n521) & (n173 | n157); - assign n634 = n633 & (n152 | n53); - assign n635 = (n136 | n49) & (n147 | n57); - assign n636 = n635 & n634 & (n130 | n56); - assign n637 = ~n252 & (n400 | (n604 & n606)); - assign n638 = n730 & (~i_7_ | n269); - assign n639 = ~n435 | ~i_4_ | n77; - assign n640 = n639 & (i_8_ | i_13_ | n235); - assign n641 = (i_11_ | n161) & (~n338 | ~n536); - assign n642 = n235 | ~i_8_ | i_13_; - assign n643 = n642 & (~n348 | (n533 & ~n536)); - assign n644 = n312 | ~i_2_ | n263; - assign n645 = ~n732 & (i_7_ | (n640 & n641)); - assign n646 = ~n563 | ~n361 | ~n496; - assign n647 = n646 & (n359 | n561); - assign n648 = (n288 | n354) & (~n166 | n355); - assign n649 = ~i_8_ | i_3_ | i_6_ | n749 | i_10_ | ~n166; - assign n650 = n649 & (~n348 | n353); - assign n651 = i_10_ | i_13_ | n749 | n494; - assign n652 = n651 & (n116 | n562); - assign n653 = i_10_ | i_8_; - assign n654 = (n286 | ~n340) & (n186 | n653); - assign n655 = n335 | i_8_ | ~n319; - assign n656 = n365 | n548 | ~i_6_ | ~i_12_; - assign n657 = ~i_3_ | ~i_9_ | ~n383 | n518; - assign n658 = n657 & (n281 | ~n496 | n560); - assign n659 = (n358 | n98) & (n346 | n303); - assign n660 = (n345 & (~i_6_ | n351)) | (i_6_ & n351); - assign n661 = (~i_1_ & n329) | (n311 & (i_1_ | n329)); - assign n662 = n660 & n661 & (~i_12_ | n357); - assign n663 = (n378 | n456) & (n455 | n451); - assign n664 = (n555 | n568) & (n62 | ~n245); - assign n665 = (n388 | n555) & (n200 | ~n245); - assign n666 = (n388 | n553) & (n200 | ~n241); - assign n667 = (n553 | n568) & (n62 | ~n241); - assign n668 = (n288 | n535) & (~n166 | n190); - assign n669 = (n116 | n449) & (~n101 | n113); - assign n670 = i_10_ & (~i_7_ | (i_3_ & ~i_8_)); - assign n671 = ~i_8_ | n56; - assign n672 = n741 & (~i_2_ | n303 | ~n406); - assign n673 = (i_3_ & n555) | (~n245 & (~i_3_ | n555)); - assign n674 = (~i_7_ | n388) & (i_0_ | ~n67); - assign n675 = ~n383 | i_8_ | n53; - assign n676 = n675 & (n401 | n366); - assign n677 = n157 | ~i_8_ | n113; - assign n678 = n677 & (~n348 | n399); - assign n679 = n346 | i_6_ | n398; - assign n680 = n679 & (n390 | n364); - assign n681 = (~n243 | n525) & (n157 | n269); - assign n682 = n680 & n681 & (n56 | ~n573); - assign n683 = (i_7_ | n389) & (i_0_ | n397); - assign n684 = (~i_2_ | n571) & (~i_1_ | n570); - assign n685 = (~i_2_ | n569) & (~i_1_ | ~n462); - assign n686 = (n364 | n439) & (n105 | n537); - assign n687 = n288 | i_2_ | n106; - assign n688 = (n451 | n270) & (n364 | n453); - assign n689 = n211 | i_10_ | n105; - assign n690 = n689 & (~i_9_ | n536 | n564); - assign n691 = ~n381 & n690 & (~n365 | n380); - assign n692 = i_3_ | i_13_ | n293; - assign n693 = n735 & (~i_6_ | ~i_12_ | n529); - assign n694 = n285 & n692 & (~i_3_ | n693); - assign n695 = (~i_5_ & n377) | (n373 & (i_5_ | n377)); - assign n696 = n695 & ~n738 & (~i_1_ | n526); - assign n697 = n564 | i_8_ | ~n458; - assign n698 = n697 & (n213 | n256 | n336); - assign n699 = n400 | ~i_10_ | n115; - assign n700 = n567 | n199 | n120; - assign n701 = n700 & (n454 | n109); - assign n702 = ~n319 | n196 | n290; - assign n703 = ~n466 & (n157 | (n668 & n669)); - assign n704 = (n444 | n53) & (n217 | n565); - assign n705 = ~n467 & ~n468 & (n138 | n441); - assign n706 = (~n348 | n434) & (~n250 | n432); - assign n707 = (n538 | n71) & (n566 | n224); - assign n708 = n445 | i_5_ | n512 | n404; - assign n709 = n708 & ~n745 & (i_5_ | n431); - assign n710 = (n589 | n290) & (n202 | n177); - assign n711 = ~n480 & n710 & (n62 | n354); - assign n712 = (n185 | n335) & (n210 | n354); - assign n713 = ~n220 | ~i_5_ | i_9_; - assign n714 = n713 & n712 & (i_0_ | i_5_); - assign n715 = (n202 | n567) & (n64 | n355); - assign n716 = i_10_ | n332; - assign n717 = (i_2_ | n283) & (i_0_ | n481); - assign n718 = i_6_ | n60; - assign n719 = ~i_12_ & n718 & (i_5_ | n59); - assign n720 = n228 | ~i_3_ | i_7_; - assign n721 = n720 & (i_7_ | n408); - assign n722 = n721 & (n546 | (~i_2_ & i_7_)); - assign n723 = (~i_7_ | n587) & (~i_2_ | n547); - assign n724 = ~n497 & (n226 | (n398 & n404)); - assign n725 = ~i_0_ | n511; - assign n726 = n495 | n400; - assign n727 = ~n435 | ~i_3_ | n270; - assign n728 = ~n365 | ~i_8_ | ~n348; - assign n729 = ~i_5_ | n59 | ~n512 | n548; - assign n730 = ~n243 | i_7_ | n50; - assign n731 = i_7_ & (n573 | n65); - assign n732 = i_7_ & (~n643 | (~i_12_ & ~n161)); - assign n733 = i_12_ | n514; - assign n734 = n560 | i_8_ | ~n167; - assign n735 = n527 | i_6_ | ~i_11_; - assign n736 = ~i_10_ & (~n572 | (n73 & n166)); - assign n737 = i_2_ & i_12_ & (~n303 | ~n398); - assign n738 = ~i_1_ & (~n688 | (n166 & ~n537)); - assign n739 = ~i_0_ & ~i_4_ & (n447 | n448); - assign n740 = i_0_ & (~n691 | ~n694 | ~n696); - assign n741 = i_2_ | n98 | n120; - assign n742 = i_4_ & (~n678 | (~n70 & ~n71)); - assign n743 = ~i_4_ & (~n676 | (~n408 & ~n489)); - assign n744 = ~n682 | n403 | n513 | n743 | ~n683 | n742; - assign n745 = i_5_ & n744; - assign n746 = n399 | ~i_4_ | ~i_5_; - assign n747 = (i_6_ & n362) | (~n167 & (~i_6_ | n362)); - assign n748 = (~i_6_ & n490) | (n366 & (i_6_ | n490)); - assign n749 = i_2_ & i_7_; - assign n750 = n417 & n533 & i_3_; - assign n751 = i_6_ & n574 & n433; -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/apex2/apex2.v b/fpga_flow/benchmarks/Verilog/MCNC/apex2/apex2.v deleted file mode 100644 index 357e6f846..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/apex2/apex2.v +++ /dev/null @@ -1,1036 +0,0 @@ -// Benchmark "TOP" written by ABC on Tue Mar 5 09:54:52 2019 - -module apex2 ( - i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, - i_11_, i_12_, i_13_, i_14_, i_16_, i_17_, i_18_, i_19_, i_20_, - i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, i_30_, - i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_, - o_0_, o_1_, o_2_ ); - input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, - i_10_, i_11_, i_12_, i_13_, i_14_, i_16_, i_17_, i_18_, i_19_, - i_20_, i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, - i_30_, i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_; - output o_0_, o_1_, o_2_; - wire n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, - n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, - n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, - n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, - n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, - n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, - n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, - n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, - n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, - n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, - n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, - n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, - n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, - n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, - n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, - n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244, - n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, - n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, - n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, - n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, - n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, - n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, - n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, - n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, - n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, - n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, - n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376, - n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, n388, - n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, - n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, - n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, - n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, - n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, - n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, - n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, - n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, - n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, - n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508, - n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520, - n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, - n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, - n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, - n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, - n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, - n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, - n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, - n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, - n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, - n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640, - n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, - n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, - n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, - n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, - n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, - n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, - n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, - n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, - n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, - n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, - n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772, - n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, - n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, - n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, - n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, - n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, - n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, - n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, - n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, - n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, - n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891, n892, - n893, n894, n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, - n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, n915, n916, - n917, n918, n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, - n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, - n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, - n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, - n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, - n977, n978, n979, n980, n981, n982, n983; - assign o_0_ = ~n965 | ~n966 | n49 | ~n964 | n47 | n48 | n45 | n46; - assign o_1_ = ~n603; - assign o_2_ = ~n350; - assign n45 = ~n798 & n686 & n229 & ~n379; - assign n46 = ~n684 & n528 & i_35_ & n526; - assign n47 = ~n693 & ~n805 & (~i_13_ | ~i_14_); - assign n48 = ~n524 & (~n939 | (~n205 & ~n473)); - assign n49 = n804 | ~n968 | n734 | n736 | n732 | n733 | ~n208 | n731; - assign n50 = ~i_27_ & ~n161; - assign n51 = ~i_30_ & n300; - assign n52 = i_36_ & (~n938 | (n50 & n51)); - assign n53 = ~i_12_ & ~i_13_; - assign n54 = ~i_7_ & (n53 | ~n803); - assign n55 = ~i_11_ & ~i_19_; - assign n56 = ~i_24_ & (~n80 | (n55 & ~n81)); - assign n57 = i_19_ & ~i_13_ & i_18_; - assign n58 = ~i_13_ & i_18_; - assign n59 = ~i_22_ & (n57 | (i_11_ & n58)); - assign n60 = ~i_24_ & (~n86 | (n55 & ~n87)); - assign n61 = i_17_ & i_12_; - assign n62 = i_14_ & i_13_; - assign n63 = i_22_ & (n61 | n62); - assign n64 = ~i_10_ & ~i_24_; - assign n65 = ~n90 & (n64 | (i_13_ & ~i_24_)); - assign n66 = ~i_24_ & (n61 | n62); - assign n67 = n610 | i_1_ | n746; - assign n68 = ~i_18_ | ~n237; - assign n69 = i_6_ | n113; - assign n70 = (n68 | n69) & (n67 | ~n237); - assign n71 = i_11_ & ~i_13_; - assign n72 = n71 & (~n773 | (i_18_ & ~n149)); - assign n73 = i_9_ & n71; - assign n74 = n73 & (~n67 | (i_18_ & ~n69)); - assign n75 = ~n635 | ~n280 | ~n324; - assign n76 = ~n324 | n747; - assign n77 = n75 & (n76 | ~n128); - assign n78 = ~n280 | n106 | n140; - assign n79 = n78 & (~n128 | ~n259 | ~n328); - assign n80 = n764 | i_9_ | i_18_; - assign n81 = n313 | n100; - assign n82 = n80 & (~n55 | n81); - assign n83 = n113 | i_6_ | n744; - assign n84 = n316 | n745; - assign n85 = n83 & (~i_9_ | n84); - assign n86 = i_18_ | n759; - assign n87 = n313 | n98; - assign n88 = n86 & (~n55 | n87); - assign n89 = i_10_ & ~i_13_; - assign n90 = i_9_ | n760; - assign n91 = (i_32_ | n88) & (n89 | n90); - assign n92 = n754 | ~i_9_ | n745; - assign n93 = ~i_11_ | i_12_; - assign n94 = ~i_11_ | n744; - assign n95 = (n67 | n94) & (n92 | n93); - assign n96 = (~n73 | n84) & (~n71 | n83); - assign n97 = (~i_18_ | n96) & (i_13_ | n95); - assign n98 = i_7_ | n763; - assign n99 = i_32_ | ~i_38_; - assign n100 = i_8_ | n763; - assign n101 = (n98 | n99) & (n100 | ~n262); - assign n102 = ~n278 | n98 | n107; - assign n103 = ~n328 | n100 | n116; - assign n104 = i_25_ | n743; - assign n105 = n102 & n103 & (n101 | n104); - assign n106 = i_32_ | ~n324; - assign n107 = i_32_ | n743; - assign n108 = (n104 | n106) & (n107 | ~n328); - assign n109 = n757 | n419; - assign n110 = n313 | n765; - assign n111 = (i_19_ | n110) & (i_18_ | n109); - assign n112 = n316 | n468; - assign n113 = i_12_ | n313; - assign n114 = i_6_ | ~n214; - assign n115 = (n113 | n114) & (i_8_ | n112); - assign n116 = i_31_ | n743; - assign n117 = i_35_ | n749; - assign n118 = n117 | n116 | n111; - assign n119 = ~n262 | i_32_ | n111; - assign n120 = n119 & (i_2_ | ~n259 | ~n324); - assign n121 = ~n104 | ~n971; - assign n122 = i_38_ & (~n118 | (~n115 & n121)); - assign n123 = n867 & (~n635 | n774); - assign n124 = (~i_38_ | n91) & (n82 | ~n262); - assign n125 = n866 & (i_10_ | n85 | ~n324); - assign n126 = n123 & (i_28_ | (n124 & n125)); - assign n127 = ~i_24_ & (~n869 | ~n871 | ~n873); - assign n128 = ~i_28_ & ~n161; - assign n129 = n128 & (~n876 | ~n878 | ~n880); - assign n130 = ~n271 | i_30_ | n160; - assign n131 = (n190 | ~n269) & (n104 | n768); - assign n132 = ~i_38_ | n762; - assign n133 = n130 & n131 & (~n51 | n132); - assign n134 = i_28_ | n175; - assign n135 = i_22_ | ~n257; - assign n136 = n143 | ~n324; - assign n137 = (n135 | n136) & (n134 | ~n269); - assign n138 = n135 | n143; - assign n139 = n175 | ~n328; - assign n140 = i_28_ | i_31_ | i_30_; - assign n141 = (n139 | n140) & (n138 | ~n262); - assign n142 = n104 | i_30_ | ~i_38_; - assign n143 = i_30_ | n743; - assign n144 = n142 & (n143 | ~n278); - assign n145 = (~n64 | n83) & (n84 | ~n272); - assign n146 = ~i_18_ | ~n257; - assign n147 = i_13_ | ~n257; - assign n148 = (n95 | n147) & (n96 | n146); - assign n149 = n742 | n316; - assign n150 = i_10_ | i_6_ | ~i_9_; - assign n151 = (n113 | n150) & (i_10_ | n149); - assign n152 = ~n262 | i_8_ | i_30_; - assign n153 = n119 & (n89 | n101 | n313); - assign n154 = n152 & n153 & (n151 | n106); - assign n155 = ~n65 & (i_32_ | ~n60); - assign n156 = n155 & (i_30_ | ~n336); - assign n157 = (n156 | ~n278) & (~n56 | n282); - assign n158 = n865 & (n76 | ~n272); - assign n159 = n157 & n158 & (n154 | ~n257); - assign n160 = ~i_34_ | ~n324; - assign n161 = i_24_ | i_26_; - assign n162 = (n161 | ~n328) & (n160 | ~n257); - assign n163 = n98 | n161 | ~n278 | ~n310; - assign n164 = n162 | n167; - assign n165 = i_31_ | i_33_ | n160 | ~n267; - assign n166 = n163 & (n100 | (n164 & n165)); - assign n167 = i_31_ | ~n300; - assign n168 = (n116 | n135) & (n167 | ~n280); - assign n169 = (n160 | ~n265) & (~n128 | ~n328); - assign n170 = n750 | n160 | ~n267; - assign n171 = (i_31_ | n199) & (n168 | n106); - assign n172 = i_29_ | n541; - assign n173 = n170 & n171 & (n169 | n172); - assign n174 = n135 | n143 | i_32_ | ~i_38_; - assign n175 = i_22_ | n161; - assign n176 = n174 & (n175 | ~n278 | ~n635); - assign n177 = n176 | n761; - assign n178 = i_3_ | i_8_ | ~i_10_ | n141; - assign n179 = i_3_ | n744; - assign n180 = n177 & n178 & (n137 | n179); - assign n181 = (i_29_ | ~n128) & (i_28_ | n175); - assign n182 = i_2_ | n744; - assign n183 = i_24_ | ~i_12_ | i_22_; - assign n184 = i_10_ | n744; - assign n185 = (n183 | n184) & (n182 | ~n342); - assign n186 = i_26_ | ~i_38_ | ~n51 | n117; - assign n187 = i_29_ | ~n219; - assign n188 = n186 & (i_28_ | n187 | n132); - assign n189 = ~n654 | ~i_38_ | ~n51; - assign n190 = i_26_ | ~n300; - assign n191 = i_30_ | n106; - assign n192 = n189 & (n190 | n191); - assign n193 = ~i_19_ | i_24_; - assign n194 = ~i_19_ | ~n257; - assign n195 = (n192 | n194) & (n188 | n193); - assign n196 = (n107 | n135) & (~n265 | n509); - assign n197 = (~n128 | n224) & (~n267 | n318); - assign n198 = n196 & n197 & (~n280 | ~n310); - assign n199 = n139 | i_32_ | i_28_; - assign n200 = n199 & (n198 | ~n324); - assign n201 = ~i_31_ | ~n235; - assign n202 = n201 & (~n235 | (~i_30_ & ~i_32_)); - assign n203 = i_23_ | ~n739; - assign n204 = i_27_ | n740; - assign n205 = ~i_14_ | n580; - assign n206 = (n204 | n205) & (n203 | ~n307); - assign n207 = n684 | n738 | ~i_20_ | ~n537; - assign n208 = n207 & (n206 | ~n235 | ~n531); - assign n209 = i_22_ | ~n237; - assign n210 = ~n59 & (i_3_ | n209); - assign n211 = (i_8_ | n141) & (i_7_ | n176); - assign n212 = (n79 | n210) & (n211 | n68); - assign n213 = ~i_22_ & ~n193; - assign n214 = ~i_7_ & ~i_8_; - assign n215 = n214 & ~n144 & n213; - assign n216 = i_12_ & n58; - assign n217 = n216 & (n215 | (i_11_ & ~n211)); - assign n218 = ~i_34_ | n769; - assign n219 = ~i_30_ & ~i_32_; - assign n220 = n218 & (i_28_ | ~i_34_ | n219); - assign n221 = (~i_22_ | n220) & (n219 | ~n303); - assign n222 = i_29_ | n572; - assign n223 = n221 & (i_28_ | n222); - assign n224 = i_29_ | n749; - assign n225 = (i_28_ | n224) & (i_25_ | ~n310); - assign n226 = i_31_ | n752; - assign n227 = (i_8_ | n226) & (n111 | n172); - assign n228 = i_33_ & n235; - assign n229 = i_33_ & i_34_; - assign n230 = i_14_ & (n228 | (~i_24_ & n229)); - assign n231 = n785 & n112; - assign n232 = i_2_ | ~n214; - assign n233 = (i_30_ | n232) & (i_32_ | n231); - assign n234 = i_22_ & (n230 | (~n202 & n203)); - assign n235 = ~i_34_ & i_35_; - assign n236 = ~n259 & (~n853 | (n63 & n235)); - assign n237 = ~i_13_ & i_19_; - assign n238 = ~n179 & (n71 | n237); - assign n239 = ~i_24_ & (n238 | (n58 & ~n94)); - assign n240 = i_13_ | n744; - assign n241 = ~n239 & (~i_18_ | n193 | n240); - assign n242 = n68 & (~i_18_ | ~n71); - assign n243 = (n94 | ~n216) & (n182 | n242); - assign n244 = ~i_12_ | n744; - assign n245 = n243 & (n68 | n244); - assign n246 = i_12_ & n71; - assign n247 = n246 & i_18_ & ~i_22_; - assign n248 = ~n761 & n213 & ~i_13_ & ~i_8_ & i_12_; - assign n249 = (n106 | n138) & (n139 | ~n635); - assign n250 = (n77 | n210) & (i_7_ | n176); - assign n251 = ~i_10_ & ~n249 & (~i_2_ | i_12_); - assign n252 = ~i_3_ & i_11_; - assign n253 = ~i_22_ & i_12_ & ~i_13_; - assign n254 = n252 & (~n847 | (~n77 & n253)); - assign n255 = (~n55 | n90) & (i_8_ | n86); - assign n256 = ~n225 & ~n89 & ~i_24_ & ~n87; - assign n257 = ~i_24_ & ~i_25_; - assign n258 = n257 & n51 & ~i_7_ & ~i_32_; - assign n259 = ~i_31_ & n219; - assign n260 = (~i_22_ | ~i_23_) & (~n63 | n259); - assign n261 = (~i_38_ | n155) & (~n56 | ~n262); - assign n262 = ~i_31_ & n324; - assign n263 = ~n823 & ~i_29_ & n262; - assign n264 = i_8_ | ~n51 | ~n257 | ~n262; - assign n265 = ~i_28_ & n257; - assign n266 = n265 & (n263 | (~n184 & ~n768)); - assign n267 = ~i_24_ & n300; - assign n268 = ~n823 & ~i_31_ & n328; - assign n269 = ~i_30_ & n328; - assign n270 = n267 & (n268 | (~n184 & n269)); - assign n271 = ~i_25_ & n300; - assign n272 = n64 & i_9_; - assign n273 = n271 & (~n261 | (~n191 & n272)); - assign n274 = i_29_ | n769; - assign n275 = ~n66 | n274; - assign n276 = i_38_ & (n256 | n258 | ~n842); - assign n277 = (n104 | n261) & (n142 | ~n336); - assign n278 = ~i_33_ & i_38_; - assign n279 = n278 & ~i_7_ & ~n161; - assign n280 = ~i_25_ & ~n161; - assign n281 = ~i_32_ & (n279 | (n262 & n280)); - assign n282 = i_33_ | ~n262; - assign n283 = ~n281 & (i_8_ | n161 | n282); - assign n284 = ~i_25_ & (~n770 | (n51 & n214)); - assign n285 = ~n89 & (~n90 | (~i_32_ & ~n87)); - assign n286 = n829 & (~n310 | (~n280 & ~n299)); - assign n287 = n830 & (~n267 | n318); - assign n288 = i_32_ | ~n235; - assign n289 = n286 & n287 & (~n271 | n288); - assign n290 = ~n190 & (~n115 | (~i_7_ & n219)); - assign n291 = n565 | n87 | ~n300; - assign n292 = i_29_ | i_34_ | i_33_; - assign n293 = n291 & (i_28_ | n90 | n292); - assign n294 = (n117 | ~n128) & (~n265 | ~n654); - assign n295 = i_33_ | n755; - assign n296 = i_24_ | i_28_; - assign n297 = i_33_ | ~n300; - assign n298 = (n161 | n297) & (n295 | n296); - assign n299 = ~i_33_ & n235; - assign n300 = ~i_28_ & ~i_29_; - assign n301 = ~n115 & (~n298 | (n299 & n300)); - assign n302 = ~n255 & (~n827 | (n280 & n300)); - assign n303 = n300 & i_34_; - assign n304 = n257 & (~n828 | (~n115 & n303)); - assign n305 = n235 & (n284 | ~n832 | ~n834); - assign n306 = ~i_27_ & n300; - assign n307 = n53 & i_14_; - assign n308 = ~i_16_ & n655; - assign n309 = n308 & n306 & n307; - assign n310 = ~i_32_ & n300; - assign n311 = n310 & ~n151 & ~n161; - assign n312 = (~n56 | n167) & (~n259 | ~n267); - assign n313 = i_5_ | n741; - assign n314 = i_12_ | i_6_; - assign n315 = i_5_ | i_6_; - assign n316 = i_1_ | n741; - assign n317 = (n315 | n316) & (n313 | n314); - assign n318 = ~i_34_ | n749; - assign n319 = (~n272 | n318) & (n184 | ~n280); - assign n320 = (i_29_ | n145) & (n187 | ~n272); - assign n321 = ~i_24_ & ~n317 & (~n814 | ~n815); - assign n322 = n213 & (~n104 | ~n971); - assign n323 = (~n816 | ~n817) & (~n819 | ~n820); - assign n324 = ~i_35_ & i_38_; - assign n325 = n324 & (~n821 | ~n822 | ~n825); - assign n326 = ~n181 & (n268 | (~n255 & n278)); - assign n327 = ~n180 & (n246 | (i_12_ & n237)); - assign n328 = ~i_33_ & n324; - assign n329 = n328 & (n311 | (~n143 & ~n185)); - assign n330 = n306 & ~n473; - assign n331 = n229 & (n309 | (~n205 & n330)); - assign n332 = n228 & n300 & n259; - assign n333 = i_14_ & (n332 | (n128 & i_33_)); - assign n334 = i_9_ & (~n848 | ~n850 | ~n852); - assign n335 = i_10_ & (n247 | (n252 & n253)); - assign n336 = ~i_24_ & n214; - assign n337 = ~n144 & (n248 | (n335 & n336)); - assign n338 = ~i_28_ & (n234 | n236 | ~n975); - assign n339 = i_10_ & (~n857 | (i_12_ & ~n212)); - assign n340 = n73 & (~n859 | (~n137 & ~n771)); - assign n341 = n203 & (~n860 | (n128 & ~n219)); - assign n342 = ~i_22_ & n64; - assign n343 = ~n313 & (~n864 | (~n105 & n342)); - assign n344 = ~n325 & (~i_27_ | n175 | ~n421); - assign n345 = n887 & (n77 | n209 | n748); - assign n346 = n886 & (~n66 | n219 | ~n303); - assign n347 = ~n333 & n890 & (~n51 | n283); - assign n348 = ~n329 & n888 & (n132 | n312); - assign n349 = n897 & n896 & n895 & n893 & n892 & n891 & ~n339 & ~n340; - assign n350 = n349 & n348 & n347 & n346 & n345 & n344 & ~n326 & ~n327; - assign n351 = ~i_34_ | ~i_37_; - assign n352 = i_29_ | n510; - assign n353 = ~i_37_ | ~n235; - assign n354 = (n351 | n352) & (~n306 | n353); - assign n355 = n523 | i_29_ | ~n427; - assign n356 = ~i_34_ | ~n427; - assign n357 = n355 & (~n306 | n356); - assign n358 = ~n654 | ~i_37_ | ~n306; - assign n359 = n358 & (i_32_ | n355); - assign n360 = n793 | n313 | n361; - assign n361 = i_17_ | n581; - assign n362 = i_10_ | n763; - assign n363 = n360 & (n313 | n361 | n362); - assign n364 = n413 | n397 | n788 | n362; - assign n365 = n488 | ~i_37_ | n468; - assign n366 = n863 | ~n427 | n788; - assign n367 = n364 & (n361 | (n365 & n366)); - assign n368 = n788 | ~n391 | n766; - assign n369 = n778 | i_7_ | i_0_; - assign n370 = n368 & (i_12_ | n369); - assign n371 = ~i_23_ & ~n161; - assign n372 = n371 & (~n921 | (~n370 & ~n493)); - assign n373 = n463 | n500 | n782; - assign n374 = i_11_ | n581; - assign n375 = n590 | n98 | n788; - assign n376 = ~n372 & n373 & (n374 | n375); - assign n377 = i_14_ | ~n427; - assign n378 = (~i_21_ | ~n546) & (~n51 | n377); - assign n379 = n737 & n361; - assign n380 = n379 & (i_33_ | ~n544); - assign n381 = n87 | n604; - assign n382 = i_10_ | n581; - assign n383 = n381 & (n87 | n382); - assign n384 = n380 | n450 | ~i_31_ | ~n51; - assign n385 = n384 & (~n330 | n383); - assign n386 = n523 | n800 | ~i_29_ | n367; - assign n387 = n796 | i_29_ | n690 | n444; - assign n388 = (~i_37_ | n376) & (n351 | n385); - assign n389 = n923 & (i_31_ | n378 | n540); - assign n390 = n389 & n388 & n386 & n387; - assign n391 = ~i_27_ & n421; - assign n392 = n655 & i_22_; - assign n393 = n391 & n392 & (~n379 | ~n784); - assign n394 = ~i_33_ | n541; - assign n395 = ~i_25_ | ~n655; - assign n396 = ~n393 & (~n51 | n394 | n395); - assign n397 = i_33_ | ~n427; - assign n398 = n377 & (i_13_ | n397); - assign n399 = n382 & n604; - assign n400 = i_10_ | n580; - assign n401 = (n397 | n400) & (n399 | ~n427); - assign n402 = ~n365 & (~n485 | (~i_33_ & ~n474)); - assign n403 = i_20_ | ~n776; - assign n404 = i_20_ | n740; - assign n405 = (i_16_ | n404) & (i_12_ | n403); - assign n406 = n900 & (n764 | n500 | n786); - assign n407 = i_19_ | n740; - assign n408 = n406 & (n81 | n407 | n374); - assign n409 = n786 | n764 | n501; - assign n410 = i_11_ | n580; - assign n411 = n409 & (n81 | n407 | n410); - assign n412 = n399 & (i_33_ | n400); - assign n413 = i_17_ | n580; - assign n414 = (n397 | n413) & (n361 | ~n427); - assign n415 = n918 & (i_19_ | n765 | n417); - assign n416 = n415 & (n398 | n314 | n403); - assign n417 = n414 | i_23_ | i_20_; - assign n418 = ~i_3_ | n780; - assign n419 = i_9_ | n315; - assign n420 = n419 | i_18_ | n417 | n418; - assign n421 = ~i_28_ & i_29_; - assign n422 = ~n404 & n421 & (n402 | ~n917); - assign n423 = n438 | i_13_ | n787; - assign n424 = n423 | ~n310 | n397; - assign n425 = ~i_32_ & n421; - assign n426 = n425 & (~n420 | (~n416 & ~n788)); - assign n427 = ~i_35_ & i_37_; - assign n428 = n427 & (~n919 | (n310 & ~n556)); - assign n429 = n898 & (n758 | n501 | n786); - assign n430 = n429 & (n87 | n407 | n410); - assign n431 = i_18_ | ~n655; - assign n432 = i_19_ | ~n655; - assign n433 = (n110 | n432) & (n109 | n431); - assign n434 = ~i_37_ | n749; - assign n435 = i_30_ | ~i_31_ | n434 | ~n544; - assign n436 = n362 | n313 | n413; - assign n437 = n436 | ~i_37_ | n117; - assign n438 = i_16_ | n740; - assign n439 = i_13_ | ~n214; - assign n440 = i_23_ | n580; - assign n441 = i_12_ | ~n214; - assign n442 = (n440 | n441) & (n438 | n439); - assign n443 = n397 | n472 | ~i_34_ | ~n308; - assign n444 = i_34_ | n566; - assign n445 = n443 & (i_33_ | n442 | n444); - assign n446 = n371 & (~n435 | ~n437 | ~n913); - assign n447 = n915 & (n430 | n565 | n566); - assign n448 = ~n446 & n447 & (i_30_ | n445); - assign n449 = ~n659 | n690; - assign n450 = i_27_ | ~n655; - assign n451 = n449 & (~n303 | n450); - assign n452 = n462 | i_8_ | n759; - assign n453 = i_11_ | n783; - assign n454 = n452 & (n90 | n453); - assign n455 = i_7_ | i_28_ | n226 | n288; - assign n456 = n495 | i_9_ | n89 | ~n537 | n789; - assign n457 = n455 & n456 & (n451 | n454); - assign n458 = (i_10_ | n90) & (i_30_ | ~n214); - assign n459 = n438 | n354 | n458; - assign n460 = n912 & (~n427 | n751 | n767); - assign n461 = n459 & n460 & (~i_37_ | n457); - assign n462 = i_18_ | n779; - assign n463 = n468 | n418; - assign n464 = n463 | n462 | i_8_; - assign n465 = ~i_9_ & (~n464 | (~n453 & ~n789)); - assign n466 = n465 & (~i_14_ | (~i_13_ & ~i_33_)); - assign n467 = ~n789 & (~n737 | (~i_33_ & ~n784)); - assign n468 = i_7_ | n315; - assign n469 = n434 | n413 | n468; - assign n470 = ~n488 & (~n469 | (~n414 & ~n745)); - assign n471 = ~n470 & (~i_37_ | (~n466 & ~n467)); - assign n472 = i_8_ | ~n53; - assign n473 = i_17_ | ~n655; - assign n474 = i_8_ | n580; - assign n475 = (n473 | n474) & (~n308 | n472); - assign n476 = i_33_ | n752; - assign n477 = n623 & n972; - assign n478 = (n477 | n224) & (n475 | n476); - assign n479 = ~n543 | n737; - assign n480 = n969 & (~i_29_ | n471 | n800); - assign n481 = n479 & n480 & (~n427 | n478); - assign n482 = n394 | n799 | ~i_25_ | i_28_; - assign n483 = n482 & (~n330 | n397 | n474); - assign n484 = i_8_ | n803; - assign n485 = i_8_ | n581; - assign n486 = (~n308 | n484) & (n473 | n485); - assign n487 = i_33_ | i_9_ | i_10_ | n789; - assign n488 = i_1_ | n780; - assign n489 = n487 & (n315 | n117 | n488); - assign n490 = n434 | n369 | ~n371; - assign n491 = n490 & (~i_37_ | n489 | ~n537); - assign n492 = i_20_ | n580; - assign n493 = i_20_ | n581; - assign n494 = (~n427 | n493) & (n397 | n492); - assign n495 = i_20_ | n779; - assign n496 = (n398 | n495) & (i_12_ | n494); - assign n497 = n299 & ~i_7_ & i_37_; - assign n498 = n300 & (n497 | (i_25_ & n228)); - assign n499 = ~n498 & (~n235 | ~n421 | ~n738); - assign n500 = i_9_ | n581; - assign n501 = i_9_ | n580; - assign n502 = (n397 | n501) & (~n427 | n500); - assign n503 = (n356 | n423) & (n430 | n351); - assign n504 = n760 | n784; - assign n505 = n783 | i_11_ | n90; - assign n506 = n504 & (i_13_ | (n505 & n452)); - assign n507 = n84 | n413; - assign n508 = (n356 | n507) & (n506 | n351); - assign n509 = i_32_ | n755; - assign n510 = i_24_ | n777; - assign n511 = (n509 | n510) & (n288 | ~n306); - assign n512 = n907 & (n758 | n500 | n786); - assign n513 = n512 & (n87 | n407 | n374); - assign n514 = ~n310 | n450; - assign n515 = n81 | n400; - assign n516 = (n436 | n514) & (~n330 | n515); - assign n517 = n204 | ~n310; - assign n518 = (n318 | ~n330) & (~n299 | n517); - assign n519 = (n511 | n513) & (n516 | n762); - assign n520 = n908 & n909 & (n518 | n802); - assign n521 = n760 | n737; - assign n522 = n519 & n520 & (n451 | n521); - assign n523 = i_26_ | n777; - assign n524 = (~n229 | ~n306) & (~i_33_ | n523); - assign n525 = ~n664 & i_25_ & i_20_ & ~i_23_; - assign n526 = ~i_34_ & n421; - assign n527 = ~i_27_ & n697; - assign n528 = i_22_ & n797; - assign n529 = i_35_ & n526 & (n527 | n528); - assign n530 = i_25_ & n797; - assign n531 = n300 & i_33_; - assign n532 = n235 & (n525 | (n530 & n531)); - assign n533 = n906 & (~i_34_ | ~n391 | ~n686); - assign n534 = ~n532 & n533 & (n395 | n524); - assign n535 = ~n413 & i_34_ & n391; - assign n536 = ~i_20_ & ~i_21_; - assign n537 = n371 & n391; - assign n538 = ~n737 | ~n784; - assign n539 = n538 & n537 & n536 & i_2_; - assign n540 = i_34_ | n161; - assign n541 = i_31_ | i_32_; - assign n542 = ~i_22_ | n540 | n541 | ~n546; - assign n543 = i_29_ & n392; - assign n544 = ~n413 | ~n784; - assign n545 = ~n523 & n543 & (~n361 | n544); - assign n546 = ~i_30_ & n421; - assign n547 = n392 & (n535 | (n546 & ~n751)); - assign n548 = n112 | n413; - assign n549 = n112 | n474; - assign n550 = (n514 | n548) & (~n330 | n549); - assign n551 = n905 & (n442 | n476 | n510); - assign n552 = (~n330 | n794) & (n514 | n796); - assign n553 = n551 & n552 & (i_33_ | n550); - assign n554 = ~n655 | i_28_ | n318; - assign n555 = n973 & n411; - assign n556 = n438 | i_14_ | n787; - assign n557 = (n509 | n556) & (n555 | n295); - assign n558 = ~n226 & (~n554 | (n128 & ~n565)); - assign n559 = n795 | ~n303 | n450; - assign n560 = ~n558 & n559 & (n510 | n557); - assign n561 = (n297 | n549) & (~n310 | n383); - assign n562 = n794 | ~n300 | n444; - assign n563 = n562 & (n561 | n353); - assign n564 = n379 | ~i_37_ | n288; - assign n565 = i_34_ | n749; - assign n566 = ~i_35_ | ~i_37_; - assign n567 = n564 & (~n544 | n565 | n566); - assign n568 = n492 | n370 | ~n371; - assign n569 = n463 | n501 | n782; - assign n570 = n568 & n569 & (n410 | n375); - assign n571 = i_27_ | n769; - assign n572 = ~i_31_ | ~i_34_; - assign n573 = (~n235 | n571) & (n510 | n572); - assign n574 = (~n306 | n572) & (~i_31_ | n523); - assign n575 = n274 | n204 | ~n235; - assign n576 = n740 | ~i_20_ | n573; - assign n577 = n575 & n576 & (n574 | n473); - assign n578 = n308 & ~n574; - assign n579 = (n578 | ~n902) & (n53 | ~n803); - assign n580 = i_16_ | i_13_; - assign n581 = i_16_ | i_14_; - assign n582 = ~n579 & (n577 | (n580 & n581)); - assign n583 = i_34_ | i_24_ | n143 | n394; - assign n584 = n583 & (i_28_ | ~n228 | ~n259); - assign n585 = ~n51 | n540; - assign n586 = (~i_20_ | n584) & (n394 | n585); - assign n587 = (n363 | n514) & (n408 | n352); - assign n588 = (n397 | n410) & (n374 | ~n427); - assign n589 = n753 | n494 | ~n537; - assign n590 = i_19_ | n781; - assign n591 = n589 & (n588 | n100 | n590); - assign n592 = ~n308 | i_14_ | n69; - assign n593 = n592 & (n433 | n361); - assign n594 = ~i_30_ & (~n911 | (i_34_ & ~n483)); - assign n595 = n502 | n745 | n782 | n418; - assign n596 = i_0_ | i_8_ | n496 | n709; - assign n597 = n924 & (n503 | n224 | n510); - assign n598 = n926 & n927 & (n473 | ~n899); - assign n599 = (~i_25_ | n586) & (n356 | n587); - assign n600 = (n591 | n788) & (n359 | n593); - assign n601 = n928 & (n690 | (n904 & n929)); - assign n602 = n936 & n935 & n933 & n932 & n931 & n930 & ~n594 & ~n804; - assign n603 = n602 & n601 & n600 & n599 & n598 & n597 & n595 & n596; - assign n604 = ~i_13_ | n581; - assign n605 = (i_12_ | n604) & (~i_13_ | n361); - assign n606 = n413 & n361; - assign n607 = (i_10_ | n413) & (~i_13_ | n361); - assign n608 = i_5_ | ~i_3_ | i_4_; - assign n609 = n608 | n462 | i_6_; - assign n610 = i_4_ | n315; - assign n611 = ~i_2_ & (i_8_ | n610 | ~n735); - assign n612 = ~n610 & i_36_ & ~i_7_ & ~i_32_; - assign n613 = ~n607 & (~n611 | n612); - assign n614 = ~i_13_ & (~n609 | (~n453 & ~n610)); - assign n615 = ~i_32_ & n735; - assign n616 = ~i_9_ & (n613 | (n614 & n615)); - assign n617 = n957 & (~n259 | ~n735 | n958); - assign n618 = i_31_ | n610 | ~n615 | n958; - assign n619 = n617 & (~i_29_ | (~n616 & n618)); - assign n620 = n974 & n515; - assign n621 = n794 & n549; - assign n622 = (~i_36_ | n621) & (n620 | ~n735); - assign n623 = n433 | n413; - assign n624 = (~n615 | n623) & (n473 | n622); - assign n625 = n485 & n474; - assign n626 = n472 & n484; - assign n627 = (n473 | n625) & (~n308 | n626); - assign n628 = n972 & n592; - assign n629 = (n627 | n226) & (n628 | n172); - assign n630 = n425 & ~n610; - assign n631 = i_9_ | n610; - assign n632 = n400 & n604; - assign n633 = n631 | n632 | ~n214 | ~n421; - assign n634 = ~i_21_ & n776; - assign n635 = ~i_28_ & n219; - assign n636 = n54 & n634 & (n630 | n635); - assign n637 = ~n809 & (~n633 | (~i_28_ & ~n621)); - assign n638 = n310 & (~n898 | ~n907); - assign n639 = n410 | n631 | i_19_ | ~n214; - assign n640 = n114 | i_18_ | n608 | n501; - assign n641 = ~n306 | ~n371; - assign n642 = i_21_ | ~n655; - assign n643 = n641 & (n523 | n642); - assign n644 = ~n648 & (~n449 | ~n643); - assign n645 = n371 & (~n504 | ~n521); - assign n646 = n330 & (~n621 | (~i_32_ & ~n978)); - assign n647 = n352 | n651 | n438; - assign n648 = n796 & n548; - assign n649 = ~n646 & n647 & (n514 | n648); - assign n650 = n978 | n204 | ~n310; - assign n651 = n790 & n801; - assign n652 = n650 & (~n306 | n438 | n651); - assign n653 = (i_7_ | ~n259) & (n204 | n621); - assign n654 = ~i_35_ & ~i_32_ & i_34_; - assign n655 = ~i_23_ & ~i_24_; - assign n656 = n655 & ~n226 & n654; - assign n657 = ~n511 & (~n430 | ~n907); - assign n658 = ~n451 & (~n506 | ~n521); - assign n659 = ~i_29_ & n235; - assign n660 = ~i_28_ & (n656 | (~n653 & n659)); - assign n661 = n306 & (n645 | (~n623 & n654)); - assign n662 = ~i_32_ & (n644 | (~i_7_ & ~n812)); - assign n663 = n50 & (n636 | n637 | n638); - assign n664 = ~i_33_ | n777; - assign n665 = (~n235 | n664) & (~n229 | n510); - assign n666 = n973 & n900; - assign n667 = n411 & (i_31_ | n666); - assign n668 = n951 & (n678 | n172 | n510); - assign n669 = (~n330 | n620) & (n514 | n947); - assign n670 = n668 & n669 & (n667 | n352); - assign n671 = n140 & (i_31_ | ~n421 | n610); - assign n672 = ~i_8_ & ~n812; - assign n673 = ~n751 & n306 & ~n628; - assign n674 = ~i_31_ & (n672 | (~n643 & ~n980)); - assign n675 = n50 & (~n950 | (n300 & ~n411)); - assign n676 = ~n371 | i_31_ | n62 | n777 | n787; - assign n677 = n676 & (~n537 | n631 | ~n813); - assign n678 = n423 & n556; - assign n679 = n678 | ~n50 | n167; - assign n680 = ~n226 & ~i_34_ & n128; - assign n681 = ~i_14_ & ~i_25_; - assign n682 = i_28_ | i_30_ | n394 | n681; - assign n683 = ~n421 | i_24_ | ~n259; - assign n684 = n379 & ~n544; - assign n685 = n683 & (~i_29_ | n510 | n684); - assign n686 = n655 & i_21_; - assign n687 = n686 & (~n682 | (~n571 & ~n807)); - assign n688 = (n222 | n510) & (~n50 | n769); - assign n689 = n688 & (n201 | ~n306); - assign n690 = i_23_ | n777; - assign n691 = (n450 | n218) & (n690 | n201); - assign n692 = n779 | ~i_21_ | n691; - assign n693 = n692 & (n689 | n438); - assign n694 = i_11_ | n806; - assign n695 = ~i_3_ | n806; - assign n696 = (i_18_ | n695) & (i_19_ | n694); - assign n697 = i_21_ & ~i_23_; - assign n698 = n697 & i_25_ & ~n664; - assign n699 = i_22_ & n259 & n421; - assign n700 = ~n379 & (n698 | (n530 & n531)); - assign n701 = n608 | i_18_ | n98; - assign n702 = n701 & (i_7_ | ~n55 | n631); - assign n703 = i_9_ | ~i_2_ | ~i_3_; - assign n704 = n703 & (n100 | n608 | ~n735); - assign n705 = ~n611 & ~i_9_ & n55; - assign n706 = n421 & (n705 | (~i_18_ & ~n704)); - assign n707 = ~n706 & (~i_36_ | ~n425 | n702); - assign n708 = ~n981 & (i_31_ | n288 | ~n546); - assign n709 = ~n371 | n778; - assign n710 = n709 & (~n537 | n610); - assign n711 = n523 | n187 | n473; - assign n712 = n711 & (~n51 | n204 | n288); - assign n713 = ~n219 | ~i_34_ | ~i_36_; - assign n714 = (~n330 | n713) & (~i_36_ | n712); - assign n715 = ~n615 | i_2_ | n140; - assign n716 = ~n983 & (~n52 | ~n214 | n438); - assign n717 = (i_7_ | n714) & (n809 | ~n940); - assign n718 = n970 & (~i_21_ | n691 | n729); - assign n719 = n716 & (i_16_ | (n717 & n718)); - assign n720 = (n431 | n695) & (n432 | n694); - assign n721 = ~n697 | n573 | n696; - assign n722 = n721 & (n574 | n720); - assign n723 = (i_17_ | n205) & (i_16_ | ~n307); - assign n724 = n394 | n585; - assign n725 = ~n332 & n724 & (~i_21_ | n584); - assign n726 = i_31_ | i_30_ | n627 | n808; - assign n727 = n726 & (~n54 | ~n308 | n713); - assign n728 = (~n371 | n571) & (~i_31_ | n449); - assign n729 = i_12_ | n805; - assign n730 = (n689 | n729) & (~n52 | n441); - assign n731 = ~i_21_ & (~n982 | (i_20_ & ~n708)); - assign n732 = n235 & (n699 | n700 | ~n943); - assign n733 = i_34_ & (~n396 | n687 | ~n946); - assign n734 = n615 & (~n679 | n680 | ~n948); - assign n735 = ~i_35_ & i_36_; - assign n736 = n735 & (n673 | n674 | n675); - assign n737 = i_12_ | n581; - assign n738 = i_21_ | i_22_; - assign n739 = ~i_16_ & ~i_27_; - assign n740 = i_23_ | i_17_; - assign n741 = i_2_ | i_4_; - assign n742 = ~i_9_ | n315; - assign n743 = i_28_ | i_26_; - assign n744 = i_8_ | ~i_9_; - assign n745 = i_8_ | n315; - assign n746 = i_2_ | i_3_; - assign n747 = i_33_ | ~n219; - assign n748 = ~i_9_ | n746; - assign n749 = i_33_ | i_32_; - assign n750 = i_31_ | n749; - assign n751 = ~i_34_ | n541; - assign n752 = i_30_ | i_29_; - assign n753 = i_8_ | n314; - assign n754 = i_4_ | n746; - assign n755 = i_29_ | ~i_34_; - assign n756 = ~i_9_ | ~n58; - assign n757 = ~i_3_ | n741; - assign n758 = n757 | n468; - assign n759 = i_9_ | n758; - assign n760 = n313 | n114; - assign n761 = ~i_10_ | i_3_ | i_7_; - assign n762 = i_35_ | i_33_ | ~i_34_; - assign n763 = i_9_ | i_6_; - assign n764 = n745 | n757; - assign n765 = i_11_ | n763; - assign n766 = i_7_ | n314; - assign n767 = ~n51 | ~n655; - assign n768 = ~n324 | n752; - assign n769 = i_28_ | ~i_31_; - assign n770 = n187 | i_7_ | i_28_; - assign n771 = i_8_ | n746; - assign n772 = i_22_ | ~n421 | n684 | ~n697; - assign n773 = n754 | i_12_ | n742; - assign n774 = ~i_38_ | i_2_ | i_7_; - assign n775 = n61 | n62; - assign n776 = ~i_16_ & ~i_23_; - assign n777 = i_27_ | i_28_; - assign n778 = i_30_ | n777; - assign n779 = i_16_ | i_17_; - assign n780 = i_0_ | i_4_; - assign n781 = ~n537 | i_17_ | i_20_; - assign n782 = i_18_ | n781; - assign n783 = i_19_ | n779; - assign n784 = i_12_ | n580; - assign n785 = n313 | n766; - assign n786 = i_18_ | n740; - assign n787 = n315 | n316; - assign n788 = i_5_ | n780; - assign n789 = n114 | n788; - assign n790 = n90 | ~i_13_ | i_14_; - assign n791 = n313 | n753; - assign n792 = i_23_ | n581; - assign n793 = ~i_13_ | n763; - assign n794 = n112 | n485; - assign n795 = n84 | n361; - assign n796 = n112 | n361; - assign n797 = ~i_23_ & ~i_27_; - assign n798 = ~i_25_ | n777; - assign n799 = ~i_20_ | ~n655; - assign n800 = i_20_ | ~n655; - assign n801 = n90 | i_13_ | i_10_; - assign n802 = n87 | n400; - assign n803 = i_14_ | i_12_; - assign n804 = n545 | n547 | n539 | ~n542; - assign n805 = ~i_7_ | i_9_; - assign n806 = ~i_7_ | ~i_10_; - assign n807 = n605 | n806; - assign n808 = ~i_34_ | ~n735; - assign n809 = i_21_ | n740; - assign n810 = i_23_ | ~i_20_ | i_21_; - assign n811 = i_21_ | n779; - assign n812 = i_2_ | n62 | n709 | n811; - assign n813 = (i_13_ & ~i_14_) | (~i_10_ & (~i_13_ | ~i_14_)); - assign n814 = (n104 | n172) & (n167 | n318); - assign n815 = (~n271 | n751) & (n190 | n750); - assign n816 = (~n53 | n92) & (n67 | n240); - assign n817 = (n84 | n756) & (~n58 | n83); - assign n818 = n297 | ~i_19_ | n161; - assign n819 = n818 & (i_28_ | n295 | n193); - assign n820 = ~n322 & (n194 | (n190 & ~n303)); - assign n821 = ~n321 & (~n128 | n184 | n476); - assign n822 = (~n51 | n319) & (n104 | n320); - assign n823 = n791 & n84; - assign n824 = (n148 | ~n303) & (n168 | n823); - assign n825 = ~n323 & n824 & (n97 | n298); - assign n826 = n659 & (~n115 | n285); - assign n827 = (~n265 | n755) & (n135 | n743); - assign n828 = ~n290 & (n111 | n167 | ~n654); - assign n829 = n107 | n135; - assign n830 = (~n128 | n224) & (~n265 | n509); - assign n831 = n476 | i_28_ | ~n214; - assign n832 = n831 & (i_7_ | ~n300 | n747); - assign n833 = ~n271 & n297; - assign n834 = (n88 | n225) & (n833 | n255); - assign n835 = n111 | n161 | n167 | n117; - assign n836 = n835 & (i_25_ | i_28_ | ~n826); - assign n837 = n836 & (~i_35_ | n89 | n293); - assign n838 = ~n301 & n837 & (n226 | n294); - assign n839 = ~n302 & ~n304 & (n138 | n232); - assign n840 = ~n305 & n839 & (n231 | n289); - assign n841 = ~n336 | i_30_ | ~n271; - assign n842 = n841 & (~n65 | n297); - assign n843 = (~n60 | ~n310) & (i_24_ | n770); - assign n844 = (n255 | ~n267) & (~n51 | ~n336); - assign n845 = ~n276 & (~n278 | (n843 & n844)); - assign n846 = i_13_ | i_24_; - assign n847 = (n192 | n147) & (n188 | n846); - assign n848 = ~n251 & (n137 | ~n237 | n771); - assign n849 = n77 | i_2_ | ~n59; - assign n850 = n849 & (i_13_ | i_3_ | n195); - assign n851 = ~n214 | n144 | n183; - assign n852 = ~n254 & n851 & (~i_12_ | n250); - assign n853 = (i_26_ | ~n66) & (~n659 | ~n775); - assign n854 = n160 | n151 | n225; - assign n855 = n854 & (i_28_ | n227 | n132); - assign n856 = (n223 | n739) & (~i_23_ | ~n303); - assign n857 = ~n217 & (n79 | ~n252 | ~n253); - assign n858 = n188 | ~i_18_ | i_24_; - assign n859 = n858 & (n192 | n146); - assign n860 = (n202 | ~n300) & (n161 | n769); - assign n861 = ~n72 & ~n74 & (~i_9_ | n70); - assign n862 = (n68 | n149) & (~n237 | n773); - assign n863 = n793 & n362; - assign n864 = (n89 | n166) & (n863 | n173); - assign n865 = (n148 | ~n324) & (n145 | ~n328); - assign n866 = n106 | i_31_ | n875; - assign n867 = i_2_ | i_8_ | n140 | ~n324; - assign n868 = n536 | ~i_34_ | ~n421; - assign n869 = n868 & (n97 | ~n121 | ~n324); - assign n870 = n150 | n108 | n113; - assign n871 = n870 & (~i_13_ | n105 | n313); - assign n872 = n136 | i_2_ | n750; - assign n873 = ~n122 & n872 & (n104 | n120); - assign n874 = i_2_ | i_8_ | i_31_ | ~n269; - assign n875 = n787 & n69; - assign n876 = n874 & (~n324 | n750 | n875); - assign n877 = ~n328 | i_10_ | n85; - assign n878 = n877 & (~i_29_ | (~n775 & n776)); - assign n879 = (n82 | n282) & (n747 | n774); - assign n880 = n879 & (n91 | ~n278); - assign n881 = n536 | ~n235 | ~n421; - assign n882 = n881 & (~n71 | n77 | n748); - assign n883 = n882 & (~i_9_ | ~i_12_ | n79); - assign n884 = ~n127 & ~n129 & (n126 | ~n280); - assign n885 = ~n342 | n108 | n149; - assign n886 = n885 & (n145 | n833 | n160); - assign n887 = n142 | i_35_ | n185; - assign n888 = ~n331 & (~i_38_ | (n838 & n840)); - assign n889 = n976 & n945 & n845 & n275 & ~n273 & ~n270 & n264 & ~n266; - assign n890 = (~i_34_ | n889) & (i_29_ | n277); - assign n891 = ~n334 & ~n337 & (~n50 | n772); - assign n892 = (n133 | n241) & (n137 | n245); - assign n893 = ~n338 & (i_24_ | (n855 & n856)); - assign n894 = ~n341 & (n200 | (n861 & n862)); - assign n895 = ~n343 & n894 & (n195 | n756); - assign n896 = (n141 | n244) & (n159 | n190); - assign n897 = n208 & (i_22_ | (n884 & n883)); - assign n898 = n785 | n440; - assign n899 = ~n357 & (~n974 | (~n81 & ~n382)); - assign n900 = n791 | n792; - assign n901 = n274 | n203 | ~n235; - assign n902 = n901 & (~i_20_ | n573 | ~n776); - assign n903 = n752 | ~i_31_ | n567; - assign n904 = n903 & (n506 | n292 | n566); - assign n905 = n767 | i_7_ | n750; - assign n906 = ~n529 & (~n229 | n798 | n799); - assign n907 = n785 | n792; - assign n908 = n295 | n438 | n510 | n801; - assign n909 = ~n214 | i_0_ | i_30_ | n800 | n380 | n523; - assign n910 = n441 | n354 | n792; - assign n911 = n910 & (n357 | n486); - assign n912 = ~n259 | i_7_ | i_23_ | ~n267 | n351; - assign n913 = (~n427 | n795) & (n397 | n507); - assign n914 = n438 | n801 | ~i_37_ | ~n299; - assign n915 = n914 & (n318 | ~n427 | n477); - assign n916 = n62 | ~i_2_ | i_16_; - assign n917 = n916 & (n401 | n100 | n788); - assign n918 = n404 | n412 | ~i_37_ | n98; - assign n919 = (n297 | n555) & (~n300 | n408); - assign n920 = i_30_ | ~i_31_ | ~n306 | n379; - assign n921 = n920 & (i_14_ | n495 | n369); - assign n922 = n488 | n315 | n377 | n495 | ~n537; - assign n923 = n922 & (n363 | ~n427 | n641); - assign n924 = n450 | n508 | n297; - assign n925 = n751 | ~n546 | ~n686; - assign n926 = n925 & (n354 | n438 | n790); - assign n927 = n495 | i_13_ | n491; - assign n928 = (n434 | n570) & (~i_7_ | n582); - assign n929 = n548 | n224 | n353; - assign n930 = (n204 | n563) & (~n427 | n560); - assign n931 = (n684 | n534) & (n553 | n351); - assign n932 = (~i_37_ | n522) & (~n259 | n499); - assign n933 = (i_14_ | n461) & (n481 | n523); - assign n934 = n977 & n772 & ~n428 & ~n426 & ~n422 & n424; - assign n935 = (~n50 | n934) & (~n306 | n448); - assign n936 = (~i_34_ | n396) & (i_32_ | n390); - assign n937 = n752 | ~i_34_ | n510; - assign n938 = n937 & (i_30_ | ~n235 | ~n306); - assign n939 = (n379 | n395) & (~n307 | ~n308); - assign n940 = n50 & (~n715 | (i_0_ & n421)); - assign n941 = n274 | ~n544 | n696 | ~n797; - assign n942 = n941 & (~n527 | n769 | n807); - assign n943 = n942 & (~n391 | n684 | n810); - assign n944 = n807 | n274 | n450; - assign n945 = n767 | ~i_14_ | n394; - assign n946 = n944 & n945 & (n685 | n810); - assign n947 = n360 & n436; - assign n948 = (n947 | n641) & (n677 | n811); - assign n949 = n671 | n626 | ~n634; - assign n950 = n949 & (n666 | n167); - assign n951 = n450 | n980 | n167; - assign n952 = n537 & (~n639 | ~n640); - assign n953 = n203 | n288 | ~n51 | ~n54; - assign n954 = n953 & (i_17_ | i_21_ | ~n952); - assign n955 = n954 & (i_7_ | n751 | n767); - assign n956 = (~n235 | n652) & (~i_34_ | n649); - assign n957 = n232 | n606 | i_30_ | ~i_36_; - assign n958 = n737 & n784; - assign n959 = ~i_36_ | ~n54 | n187 | ~n308; - assign n960 = n479 & n959 & (n629 | ~n735); - assign n961 = (n619 | n642) & (i_29_ | n624); - assign n962 = n723 | n665 | ~n697; - assign n963 = n962 & (n730 | (n440 & n792)); - assign n964 = n963 & (n728 | n807); - assign n965 = (n681 | n725) & (~n306 | n727); - assign n966 = (~n544 | n722) & (n62 | n719); - assign n967 = (~i_36_ | ~n979) & (n670 | n808); - assign n968 = n967 & (n523 | (n961 & n960)); - assign n969 = n515 | i_29_ | n473 | n397; - assign n970 = n441 | n710 | i_21_ | ~i_36_; - assign n971 = i_33_ | n743; - assign n972 = ~n308 | i_13_ | n69; - assign n973 = n440 | n791; - assign n974 = n81 | n604; - assign n975 = ~n278 | n175 | n233; - assign n976 = n260 | i_24_ | i_28_; - assign n977 = i_0_ | n398 | n405 | ~n635; - assign n978 = n381 & n802; - assign n979 = n660 | n661 | n657 | n658 | ~n955 | ~n956 | n662 | n663; - assign n980 = n507 & n795; - assign n981 = n526 & ~n161 & n259; - assign n982 = n413 | n707 | i_23_ | ~n50; - assign n983 = n634 & n421 & n50 & i_0_ & ~i_12_; -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/apex4/apex4.v b/fpga_flow/benchmarks/Verilog/MCNC/apex4/apex4.v deleted file mode 100644 index df98f3d1d..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/apex4/apex4.v +++ /dev/null @@ -1,792 +0,0 @@ -// Benchmark "TOP" written by ABC on Mon Feb 4 17:25:42 2019 - -module apex4 ( - i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, - o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, - o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_ ); - input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_; - output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, - o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_; - wire n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, - n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, - n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, - n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, - n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, - n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, - n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, - n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, - n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, - n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, - n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, - n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, - n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, - n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, - n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233, - n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244, n245, - n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, - n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269, - n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, - n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293, - n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, - n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, - n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, - n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, n341, - n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353, - n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, n365, - n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, - n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, - n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, - n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, - n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, - n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, - n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, - n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, n461, - n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, - n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, - n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, - n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508, n509, - n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, - n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, - n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, - n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, - n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569, - n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, n581, - n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, - n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, - n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, - n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629, - n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, - n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, - n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, - n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, - n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, - n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, - n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, - n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, - n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, - n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749; - assign o_0_ = 1'b0; - assign o_1_ = ~n134; - assign o_2_ = ~n492; - assign o_3_ = ~n129; - assign o_4_ = ~n128; - assign o_5_ = ~n119; - assign o_6_ = ~n110; - assign o_7_ = ~n101; - assign o_8_ = ~n313; - assign o_9_ = ~n100; - assign o_10_ = ~n526; - assign o_11_ = ~n91; - assign o_12_ = ~n87; - assign o_13_ = ~n80; - assign o_14_ = ~n72; - assign o_15_ = ~n64; - assign o_16_ = ~n63; - assign o_17_ = ~n61; - assign o_18_ = ~n53; - assign n47 = n440 | n512; - assign n48 = n539 | n454; - assign n49 = n425 | n540; - assign n50 = n305 | n557; - assign n51 = n643 & n644 & n409 & n616 & n645 & n646 & n642 & n647; - assign n52 = n65 & (n515 | n514); - assign n53 = n47 & n48 & n49 & n50 & n51 & n52; - assign n54 = n641 & n501 & n624 & n620 & n586; - assign n55 = n314 | n591; - assign n56 = n528 | n208; - assign n57 = n425 | n558; - assign n58 = n236 | n576; - assign n59 = n545 | ~i_6_ | n531; - assign n60 = n49 & n742; - assign n61 = n48 & n54 & n55 & n56 & n57 & n58 & n59 & n60; - assign n62 = n651 & n652 & n653 & n654 & n650 & n259 & n604 & n655; - assign n63 = n54 & n62 & n50 & n47; - assign n64 = n51 & n62 & n58 & n56; - assign n65 = n190 | n543 | n514; - assign n66 = n229 | n548; - assign n67 = n443 | ~i_0_ | n419; - assign n68 = n190 | n562; - assign n69 = n656 & n247 & n657 & n621 & n658 & n599 & n659; - assign n70 = n437 & n456 & n513 & n660 & n661 & n516 & n662 & n663; - assign n71 = n504 & n505 & n506 & n507 & n508 & n509 & n510 & n511; - assign n72 = n65 & n66 & n67 & n68 & n69 & n70 & n71; - assign n73 = n664 & n597 & n556 & n264 & n358 & n391 & n434 & ~n522; - assign n74 = n360 & n517 & n399 & n518 & n519 & n520 & n521; - assign n75 = n515 | n245; - assign n76 = n440 | n558; - assign n77 = ~i_0_ | n190 | n250 | n252; - assign n78 = n430 | n419; - assign n79 = ~n332 | n345; - assign n80 = n73 & n74 & n75 & n70 & n76 & n77 & n78 & n79; - assign n81 = n634 & n596 & n350 & n468 & n130 & n665 & n666 & n667; - assign n82 = n440 | n144; - assign n83 = i_3_ | n373 | n419; - assign n84 = n190 | n575; - assign n85 = n342 | n559; - assign n86 = n182 | n575; - assign n87 = n74 & n81 & n82 & n69 & n83 & n84 & n85 & n86; - assign n88 = n560 | n575; - assign n89 = ~i_3_ | i_5_ | n440 | ~n461; - assign n90 = n345 | ~i_0_ | n250; - assign n91 = n88 & n89 & n59 & n90 & n71 & n73 & n81; - assign n92 = n570 & n193 & n202 & n199 & n588 & n589; - assign n93 = n178 & n184 & n183 & n185 & n186 & n187 & n188 & n189; - assign n94 = n141 & n155 & n160 & n164 & n172 & n122 & n173 & n174; - assign n95 = n221 & n222 & (n223 | n224); - assign n96 = n213 & n214 & n215 & n216 & n217 & n218 & n219 & n220; - assign n97 = n210 & n206 & n583 & n212 & n584 & n585 & n586 & n587; - assign n98 = n582 & n580 & ~n255 & n123 & n238 & n249 & ~n254; - assign n99 = n660 & n685 & n615 & n686 & n687 & n325 & n253 & n684; - assign n100 = n92 & n93 & n94 & n95 & n96 & n97 & n98 & n99; - assign n101 = n102 & n348 & n349 & n347 & n350 & n351 & n352 & n353; - assign n102 = n325 & n326 & n152 & n327 & n328 & n329 & n330 & n331; - assign n103 = n371 & (i_5_ | n372); - assign n104 = n369 & (n190 | n223 | n370); - assign n105 = n630 & n366 & n368 & n149 & n216 & n631; - assign n106 = n151 & n358 & n359 & n360 & n361 & n362 & n363 & n364; - assign n107 = n580 & n379 & n210 & n267 & n285 & ~n377; - assign n108 = n90 & n417 & n712 & n148 & n568 & n713; - assign n109 = n646 & n66 & n75 & n86 & n374 & ~n376; - assign n110 = n102 & n103 & n104 & n105 & n106 & n107 & n108 & n109; - assign n111 = n414 & (n415 | n416); - assign n112 = n281 & n413 & (n224 | ~n332); - assign n113 = n407 & n79 & n408 & n409 & n49 & n410 & n411 & n412; - assign n114 = n399 & n400 & n401 & n402 & n403 & n404 & n405 & n406; - assign n115 = n391 & n392 & n393 & n394 & n395 & n396 & n397 & n398; - assign n116 = n349 & n424 & n420 & n431 & n94 & n307; - assign n117 = n638 & n656 & n713 & n694 & n57 & n651; - assign n118 = n427 & n428 & n429 & n614 & n86 & n696; - assign n119 = n111 & n112 & n113 & n114 & n115 & n116 & n117 & n118; - assign n120 = n262 & n266 & n267 & n268 & n269 & n270 & n271 & n272; - assign n121 = n315 & n202 & n613 & n614; - assign n122 = n168 & n169 & (n170 | n171); - assign n123 = n88 & n231 & (n232 | n233); - assign n124 = n240 | n415 | i_0_ | ~i_2_; - assign n125 = n443 | n190 | n444; - assign n126 = n500 & n719 & n720; - assign n127 = n435 & n457 & n442 & n437 & n386 & n111 & n348 & n106; - assign n128 = n120 & n121 & n122 & n123 & n124 & n125 & n126 & n127; - assign n129 = n447 & n456 & n455 & n457 & n115 & n347 & n458 & n459; - assign n130 = n382 & n496 & (n145 | n335); - assign n131 = n640 & n494 & n495 & n505 & n504 & n619; - assign n132 = n661 & n657 & n497; - assign n133 = n603 & n48 & n68 & n720 & n279 & n187 & n602 & n741; - assign n134 = ~n499 & n97 & n112 & n130 & n131 & n132 & n133 & ~n498; - assign n135 = n339 | n542; - assign n136 = n440 | n416; - assign n137 = n166 | n541; - assign n138 = n236 | n538; - assign n139 = (n440 | n237) & (n305 | n224); - assign n140 = n679 & (n301 | n226 | n515); - assign n141 = n135 & n136 & n137 & n138 & n139 & n140; - assign n142 = n301 | n354 | n474; - assign n143 = n166 | n341; - assign n144 = n430 | n158; - assign n145 = i_6_ | i_7_; - assign n146 = n142 & n143 & (n144 | n145); - assign n147 = n422 | n467; - assign n148 = n170 | n544; - assign n149 = n342 | n367; - assign n150 = n440 | n436; - assign n151 = n166 | n365; - assign n152 = ~i_6_ | ~i_8_ | n453; - assign n153 = n422 | n546; - assign n154 = n146 & (n440 | n232 | n430); - assign n155 = n147 & n148 & n149 & n150 & n151 & n152 & n153 & n154; - assign n156 = n425 | n448; - assign n157 = n229 | n252 | n226; - assign n158 = i_5_ | n533; - assign n159 = n182 | ~n332; - assign n160 = n156 & n157 & (n158 | n159); - assign n161 = n529 | n548; - assign n162 = n425 | n546; - assign n163 = (n440 | n534) & (n423 | n454); - assign n164 = n161 & n162 & n163; - assign n165 = n182 | n430; - assign n166 = i_5_ | n240; - assign n167 = n165 | n166; - assign n168 = n240 | n223 | n208; - assign n169 = n342 | n337; - assign n170 = ~i_5_ | n533; - assign n171 = n425 | n430; - assign n172 = n553 & n554 & n167 & n286 & n555 & n556; - assign n173 = n683 & n477 & (n425 | n195); - assign n174 = n633 & n482 & n637 & n609 & n681 & n682 & n621 & n680; - assign n175 = n454 | n463; - assign n176 = n236 | n209; - assign n177 = (n166 | n559) & (n158 | n341); - assign n178 = n175 & n176 & n177; - assign n179 = n560 | n441; - assign n180 = n531 | n224; - assign n181 = n166 | n305; - assign n182 = ~i_6_ | n529; - assign n183 = n179 & n180 & (n181 | n182); - assign n184 = n295 & n294 & n563; - assign n185 = n166 | n367; - assign n186 = n529 | n531 | n472; - assign n187 = n225 | n301 | ~n332; - assign n188 = n678 & (~i_8_ | n562); - assign n189 = n675 & n676 & n269 & n76 & n362 & n624 & n677 & n50; - assign n190 = i_7_ | i_8_; - assign n191 = ~i_6_ | n543; - assign n192 = ~i_0_ | ~n469; - assign n193 = n85 & (n190 | n191 | n192); - assign n194 = i_6_ | ~i_7_; - assign n195 = n166 | n223; - assign n196 = n194 | n195; - assign n197 = n416 | n454; - assign n198 = n232 | n223; - assign n199 = n197 & (n198 | n145); - assign n200 = n166 | n566; - assign n201 = n339 | n274; - assign n202 = n200 & n201 & (n182 | n144); - assign n203 = n166 | n337; - assign n204 = n425 | n209; - assign n205 = (n158 | n233) & (n198 | n454); - assign n206 = n203 & n204 & n205; - assign n207 = n145 | n170 | ~n461; - assign n208 = ~i_6_ | n229; - assign n209 = n241 | n545; - assign n210 = n207 & (n208 | n209); - assign n211 = n223 | n339; - assign n212 = n211 | n208; - assign n213 = n440 | n209; - assign n214 = n158 | n274; - assign n215 = n236 | n572; - assign n216 = n182 | n572; - assign n217 = n415 | n211; - assign n218 = n301 | n191 | n488; - assign n219 = n182 | n211; - assign n220 = (n166 | n573) & (n532 | n145); - assign n221 = n531 | n229 | n545; - assign n222 = n59 & (n232 | ~n332 | n574); - assign n223 = ~i_2_ | n321; - assign n224 = n425 | n339; - assign n225 = i_6_ | n487; - assign n226 = ~i_1_ | n443; - assign n227 = n226 | ~i_7_ | n225; - assign n228 = i_0_ | n191 | ~n469; - assign n229 = ~i_7_ | ~i_8_; - assign n230 = n228 | n229; - assign n231 = n422 | n195; - assign n232 = ~i_5_ | n240; - assign n233 = n182 | ~n461; - assign n234 = n190 | n515 | n488; - assign n235 = n342 | n372; - assign n236 = i_6_ | n529; - assign n237 = n531 | n158; - assign n238 = n234 & n235 & (n236 | n237); - assign n239 = n321 | n577; - assign n240 = ~i_3_ | i_4_; - assign n241 = ~i_2_ | n373; - assign n242 = ~i_6_ | i_8_; - assign n243 = n239 & (n240 | n241 | n242); - assign n244 = i_6_ | n323; - assign n245 = n190 | ~n461; - assign n246 = n244 | n245; - assign n247 = n339 | n573; - assign n248 = i_3_ | i_4_ | i_6_; - assign n249 = n247 & (n229 | n248 | ~n332); - assign n250 = i_2_ | ~i_3_; - assign n251 = n250 | ~i_0_ | n225; - assign n252 = i_6_ | ~i_4_ | i_5_; - assign n253 = ~i_1_ | ~i_7_ | n250 | n252; - assign n254 = i_8_ & (~n251 | (~n430 & ~n472)); - assign n255 = ~i_5_ & (~n591 | (~n422 & ~n561)); - assign n256 = n425 | n436; - assign n257 = n378 | ~n461; - assign n258 = n170 | n367; - assign n259 = n208 | n558; - assign n260 = n327 & (n166 | n229 | ~n461); - assign n261 = n301 | n144; - assign n262 = n256 & n257 & n258 & n259 & n260 & n261; - assign n263 = n415 | n538; - assign n264 = n181 | n208; - assign n265 = n578 & (n301 | n241 | n444); - assign n266 = n78 & n263 & n264 & n265; - assign n267 = n592 & n593; - assign n268 = n238 & n700 & (n537 | n191); - assign n269 = n339 | n440 | ~n461; - assign n270 = n342 | n365; - assign n271 = n232 | n241 | n242; - assign n272 = n669 & n699 & n656 & n410; - assign n273 = ~n415 & (~n237 | (~n305 & ~n533)); - assign n274 = n208 | ~n332; - assign n275 = n274 | n170; - assign n276 = n444 | n565; - assign n277 = n365 | ~i_4_ | i_5_; - assign n278 = n276 & n277 & (n225 | n245); - assign n279 = n232 | n372; - assign n280 = n529 | n571; - assign n281 = n342 | n159; - assign n282 = n182 | n539; - assign n283 = n691 & (n527 | n544); - assign n284 = n689 & n466 & n690 & n658 & n452 & n648 & n138 & n402; - assign n285 = n279 & n280 & n281 & n282 & n183 & n146 & n283 & n284; - assign n286 = n545 | n274; - assign n287 = n158 | n542; - assign n288 = n532 | n425; - assign n289 = n425 | n453; - assign n290 = n170 | n302 | n430; - assign n291 = n182 | n423; - assign n292 = (n532 | n454) & (n528 | n145); - assign n293 = n286 & n136 & n287 & n288 & n289 & n290 & n291 & n292; - assign n294 = n208 | n546; - assign n295 = n440 | n493; - assign n296 = n236 | n564; - assign n297 = n158 | n591; - assign n298 = n688 & (n158 | n236 | ~n332); - assign n299 = n305 | n229 | n354; - assign n300 = n294 & n295 & n296 & n297 & n298 & n299; - assign n301 = ~i_7_ | i_8_; - assign n302 = i_6_ | ~i_8_; - assign n303 = n531 | n339; - assign n304 = (n301 | n228) & (n302 | n303); - assign n305 = i_2_ | n321; - assign n306 = i_3_ | i_5_; - assign n307 = n239 & (n305 | n236 | n306); - assign n308 = n602 & n603 & n604 & n519; - assign n309 = n702 & (~i_1_ | n182 | n342); - assign n310 = n351 & n285 & n120 & n300 & n304 & n293; - assign n311 = n673 & n84 & n640 & n675 & n701 & n67; - assign n312 = n76 & n404 & n219 & n636 & n649 & n79; - assign n313 = n308 & n95 & n307 & n309 & n160 & n310 & n311 & n312; - assign n314 = i_3_ | n487; - assign n315 = n159 | n314; - assign n316 = n165 | n232; - assign n317 = n440 | n423; - assign n318 = n190 | n248 | ~n332; - assign n319 = (n236 | n536) & (n415 | n575); - assign n320 = n317 & n318 & n319; - assign n321 = i_0_ | ~i_1_; - assign n322 = n191 | n301 | n321 | i_3_; - assign n323 = i_3_ | ~i_5_; - assign n324 = n208 | n223 | n323; - assign n325 = n537 | n252; - assign n326 = n415 | n467; - assign n327 = n342 | n573; - assign n328 = n706 & (i_0_ | n443 | n419); - assign n329 = i_3_ | n566; - assign n330 = n320 & n478 & n300 & n172 & n121 & n612 & n617; - assign n331 = n705 & n218 & n403 & n257 & n150 & n187 & n583 & n704; - assign n332 = ~i_2_ & ~n426; - assign n333 = ~n170 & (~n233 | (~n301 & n332)); - assign n334 = ~n430 & (~n224 | (~n314 & ~n529)); - assign n335 = n342 | n241; - assign n336 = n335 | n190; - assign n337 = ~n332 | n422; - assign n338 = n337 | n232; - assign n339 = i_5_ | n527; - assign n340 = n242 | n339 | ~n461; - assign n341 = n415 | ~n461; - assign n342 = ~i_5_ | n527; - assign n343 = n341 | n342; - assign n344 = n681 & n563 & n703; - assign n345 = n229 | n444; - assign n346 = i_1_ | ~n469; - assign n347 = n243 & n344 & (n345 | n346); - assign n348 = n621 & n622 & n623 & n624 & n496 & n625 & n626 & n627; - assign n349 = n340 & n343 & n58 & n620; - assign n350 = n618 & n405 & n619; - assign n351 = n605 & n178 & n606 & n607 & n278 & n596 & n601 & n608; - assign n352 = n582 & n193 & n266; - assign n353 = n399 & n258 & n695 & n708 & n506 & n186 & n654 & n707; - assign n354 = ~i_6_ | n487; - assign n355 = n301 | n354 | ~n461; - assign n356 = ~i_4_ | ~i_5_; - assign n357 = n356 | n165; - assign n358 = n182 | n448; - assign n359 = n241 | n224; - assign n360 = n232 | n182 | n241; - assign n361 = n166 | n159; - assign n362 = n170 | n341; - assign n363 = n47 & n501 & n147; - assign n364 = n408 & n396 & n676 & n197 & n710 & n388 & n711 & n709; - assign n365 = n430 | n208; - assign n366 = n365 | n232; - assign n367 = ~n332 | n425; - assign n368 = n367 | n158; - assign n369 = n531 | n208 | n547; - assign n370 = i_6_ | n547; - assign n371 = n534 | n449; - assign n372 = n425 | ~n461; - assign n373 = ~i_0_ | ~i_1_; - assign n374 = n373 | n301 | n339; - assign n375 = (i_1_ & (~i_5_ | ~n426)) | (i_5_ & ~n426); - assign n376 = ~n454 & ~i_4_ & n375; - assign n377 = ~n195 & (~n425 | ~n449); - assign n378 = n232 | n236; - assign n379 = ~n332 | n378; - assign n380 = n241 | n557; - assign n381 = n423 | n208; - assign n382 = n166 | n590; - assign n383 = n232 | n542; - assign n384 = (n170 | n541) & (n422 | n453); - assign n385 = n716 & (~i_1_ | i_2_ | n577); - assign n386 = n380 & n381 & n382 & n383 & n384 & n385; - assign n387 = n422 | n549; - assign n388 = n355 & n357 & n628 & n629; - assign n389 = n529 | n515; - assign n390 = n387 & n388 & (n389 | n346); - assign n391 = n236 | n549; - assign n392 = n170 | n590; - assign n393 = n415 | n441; - assign n394 = n182 | n564; - assign n395 = n425 | n538; - assign n396 = n208 | n441; - assign n397 = n425 | n441; - assign n398 = n390 & n320 & n386 & n308 & n278 & n718; - assign n399 = n166 | n430 | n454; - assign n400 = n170 | n159; - assign n401 = n314 | n559; - assign n402 = n425 | n564; - assign n403 = n144 | n454; - assign n404 = n314 | n274; - assign n405 = n538 | n208; - assign n406 = n326 & n607 & n282 & n697 & n714 & n715; - assign n407 = n474 | n438; - assign n408 = n314 | n449 | ~n461; - assign n409 = n449 | n564; - assign n410 = n182 | n467; - assign n411 = n708 & n625 & (n537 | n248); - assign n412 = n613 & n698 & n710; - assign n413 = n594 & n693 & n90; - assign n414 = n301 | n430 | n252; - assign n415 = i_6_ | n301; - assign n416 = n305 | n170; - assign n417 = n415 | n453; - assign n418 = n425 | n576; - assign n419 = n225 | n229; - assign n420 = n417 & n418 & (n192 | n419); - assign n421 = n574 | ~n332 | n545; - assign n422 = ~i_6_ | n301; - assign n423 = n166 | n241; - assign n424 = n421 & (n422 | n423); - assign n425 = ~i_6_ | n190; - assign n426 = ~i_0_ | i_1_; - assign n427 = n425 | n240 | n426; - assign n428 = n354 | i_7_ | n192; - assign n429 = n229 | n241 | n244; - assign n430 = i_2_ | n373; - assign n431 = n224 | n430; - assign n432 = ~n454 & ((~n223 & ~n306) | ~n534); - assign n433 = n372 | n158; - assign n434 = n415 | n546; - assign n435 = n434 & (n229 | ~n332 | n370); - assign n436 = n223 | n545; - assign n437 = n401 & (n236 | n436); - assign n438 = n229 | n515; - assign n439 = ~i_0_ | ~i_2_; - assign n440 = i_6_ | n190; - assign n441 = n223 | n170; - assign n442 = (n438 | n439) & (n440 | n441); - assign n443 = ~i_2_ | i_3_; - assign n444 = i_6_ | n356; - assign n445 = n208 | n493; - assign n446 = (n422 | n575) & (n529 | n441); - assign n447 = n445 & n361 & n446; - assign n448 = n430 | n545; - assign n449 = ~i_6_ | ~i_7_; - assign n450 = n448 | n449; - assign n451 = n232 | n367; - assign n452 = n305 | n422 | n533; - assign n453 = n342 | n223; - assign n454 = i_6_ | n229; - assign n455 = n451 & n452 & (n453 | n454); - assign n456 = n636 & n450 & n622 & n579; - assign n457 = n635 & n634 & n633 & n632 & n553 & n552 & ~n432 & n433; - assign n458 = n601 & n249 & n617; - assign n459 = n294 & n297 & n701 & n721 & n206 & n199 & n722 & n155; - assign n460 = ~n252 & ~n529; - assign n461 = i_2_ & ~n426; - assign n462 = n461 & ((~n194 & ~n314) | n460); - assign n463 = n305 | n339; - assign n464 = n463 | n415; - assign n465 = n182 | n534; - assign n466 = n314 | n365; - assign n467 = n241 | n158; - assign n468 = n465 & n466 & (n236 | n467); - assign n469 = i_3_ & i_2_; - assign n470 = n469 & ((~n229 & ~n252) | ~n389); - assign n471 = ~n470 & (i_2_ | n306 | n440); - assign n472 = ~i_6_ | n527; - assign n473 = (n229 | n472) & (i_7_ | n370); - assign n474 = i_3_ | n426; - assign n475 = (n321 | n158) & (i_4_ | n474); - assign n476 = n639 & n638 & n637 & n464 & n148 & ~n462; - assign n477 = n550 & n551 & n552; - assign n478 = n291 & n322 & n324; - assign n479 = n732 & n734 & (~i_1_ | n471); - assign n480 = n554 & n701 & n731 & n730 & n396 & n161 & n688 & n727; - assign n481 = n468 & n420 & n476 & n96 & n477 & n478 & n479 & n480; - assign n482 = n440 | n540; - assign n483 = n482 & (n198 | n415); - assign n484 = n302 | n158; - assign n485 = n166 | n236; - assign n486 = n484 & n485 & (~i_5_ | n440); - assign n487 = i_4_ | ~i_5_; - assign n488 = i_3_ | ~i_0_ | i_2_; - assign n489 = (n487 | n488) & (n373 | n170); - assign n490 = n262 & n92 & n612 & n738 & n739 & n737; - assign n491 = n621 & n649 & n644 & n643 & n289 & n162 & n393 & n736; - assign n492 = n483 & n447 & n481 & n114 & n103 & n442 & n490 & n491; - assign n493 = n241 | n314; - assign n494 = n493 | n422; - assign n495 = n209 | n182; - assign n496 = n425 | n493; - assign n497 = n356 | n182 | n346; - assign n498 = ~n170 & ~n449 & (~n430 | n461); - assign n499 = n332 & (~n378 | ~n485 | ~n740); - assign n500 = n545 | n145 | ~n332; - assign n501 = n531 | n557; - assign n502 = (n342 | n171) & (n449 | n335); - assign n503 = n500 & n501 & n502; - assign n504 = n166 | n274; - assign n505 = n158 | n566; - assign n506 = n422 | n576; - assign n507 = n719 & (n190 | n354 | n561); - assign n508 = n430 | n345; - assign n509 = n476 & n455 & n503 & n293 & n570 & n424; - assign n510 = n611 & n383 & n203 & n213 & n682 & n361; - assign n511 = n317 & n176 & n175 & n643 & n641 & n318; - assign n512 = n166 | n531; - assign n513 = n270 & (n425 | n512); - assign n514 = i_3_ | n530; - assign n515 = i_6_ | n543; - assign n516 = n514 | n515; - assign n517 = n145 | n575; - assign n518 = n166 | n233; - assign n519 = n170 | n566; - assign n520 = n669 & n387 & n217 & n693 & n200; - assign n521 = n404 & n692 & n359 & n744 & n650 & n642 & n483 & n105; - assign n522 = ~n232 & (~n544 | ~n591); - assign n523 = n390 & n104 & n113 & n93 & n141 & n304; - assign n524 = n745 & n746 & n747 & n77 & n381 & n605; - assign n525 = n689 & n271 & n705 & n360 & n47 & n618; - assign n526 = n481 & n435 & n131 & n513 & n503 & n523 & n524 & n525; - assign n527 = i_3_ | ~i_4_; - assign n528 = n305 | n342; - assign n529 = i_7_ | ~i_8_; - assign n530 = i_1_ | i_0_; - assign n531 = ~i_2_ | n530; - assign n532 = n342 | n531; - assign n533 = ~i_3_ | ~i_4_; - assign n534 = n170 | n241; - assign n535 = i_0_ | n443 | n225; - assign n536 = n339 | n430; - assign n537 = n223 | n229; - assign n538 = n531 | n170; - assign n539 = n305 | n158; - assign n540 = n305 | n314; - assign n541 = n422 | n430; - assign n542 = n208 | ~n461; - assign n543 = i_4_ | i_5_; - assign n544 = n415 | n430; - assign n545 = i_4_ | n306; - assign n546 = n305 | n545; - assign n547 = ~i_3_ | ~i_5_; - assign n548 = n430 | n370; - assign n549 = n223 | n158; - assign n550 = n232 | n341; - assign n551 = n170 | n372; - assign n552 = n208 | n540; - assign n553 = n182 | n549; - assign n554 = n208 | n463; - assign n555 = n540 | n454; - assign n556 = n425 | n467; - assign n557 = n422 | n339; - assign n558 = n531 | n314; - assign n559 = ~n332 | n454; - assign n560 = ~i_6_ | i_7_; - assign n561 = i_1_ | n443; - assign n562 = n426 | ~i_3_ | n252; - assign n563 = n236 | n211; - assign n564 = n305 | n232; - assign n565 = n529 | n474; - assign n566 = n422 | ~n461; - assign n567 = n236 | n463; - assign n568 = n536 | n560; - assign n569 = n339 | n341; - assign n570 = n567 & n196 & n568 & n569; - assign n571 = n223 | n314; - assign n572 = n241 | n339; - assign n573 = ~n332 | n415; - assign n574 = i_6_ | i_8_; - assign n575 = ~n461 | n545; - assign n576 = n232 | n531; - assign n577 = i_3_ | n190 | n444; - assign n578 = n49 & n394 & n421 & n387 & n445; - assign n579 = n440 | n564; - assign n580 = n246 & n578 & n243 & n410 & n579 & n418; - assign n581 = ~n461 | n485; - assign n582 = n227 & n230 & n451 & n581; - assign n583 = n422 | n441; - assign n584 = n422 | n571; - assign n585 = n182 | n546; - assign n586 = n425 | n416; - assign n587 = n182 | n436; - assign n588 = n672 & n673 & n606 & n674; - assign n589 = n668 & n626 & n669 & n670 & n671 & n287 & n645 & n296; - assign n590 = ~n332 | n440; - assign n591 = n182 | n531; - assign n592 = n407 & n135 & n692 & n392 & n137 & n693 & n694 & n55; - assign n593 = n695 & n696 & n685 & n687 & n585 & n697 & n698 & n681; - assign n594 = n339 | n559; - assign n595 = n181 | n425; - assign n596 = n418 & n393 & n594 & n595 & n550; - assign n597 = ~n332 | n557; - assign n598 = n425 | n144; - assign n599 = n440 | n571; - assign n600 = n314 | n541; - assign n601 = n600 & n599 & n598 & n597 & n518 & ~n273 & n275; - assign n602 = n182 | n493; - assign n603 = n232 | n274; - assign n604 = n422 | n558; - assign n605 = n170 | n236 | ~n461; - assign n606 = n430 | n485; - assign n607 = n208 | n416; - assign n608 = n551 & n686 & n639 & n637 & n671 & n569 & n57 & n653; - assign n609 = n339 | n159; - assign n610 = n422 | n237; - assign n611 = n237 | n454; - assign n612 = n609 & n395 & n316 & n610 & n611 & n391; - assign n613 = n236 | n416; - assign n614 = n539 | n242; - assign n615 = n181 | n302; - assign n616 = n454 | n564; - assign n617 = n615 & n256 & n269 & n234 & n214 & n270 & n50 & n616; - assign n618 = n529 | n535; - assign n619 = n223 | n557; - assign n620 = n532 | n208; - assign n621 = n422 | n538; - assign n622 = n182 | n571; - assign n623 = n181 | n440; - assign n624 = n182 | n463; - assign n625 = n182 | n195; - assign n626 = n565 | n191; - assign n627 = n397 & n338 & n336 & ~n334 & n82 & ~n333; - assign n628 = n425 | n571; - assign n629 = n342 | n274; - assign n630 = n236 | n342 | ~n461; - assign n631 = n534 | n415; - assign n632 = n232 | n171; - assign n633 = n236 | n539; - assign n634 = n342 | n233; - assign n635 = n672 & (n252 | ~n332 | n529); - assign n636 = n546 | n454; - assign n637 = n232 | n159; - assign n638 = n182 | n416; - assign n639 = n430 | n557; - assign n640 = n422 | n540; - assign n641 = i_2_ | n530; - assign n642 = n402 & n623 & n641 & n394; - assign n643 = n425 | n237; - assign n644 = n237 | n208; - assign n645 = n415 | n564; - assign n646 = n415 | n576; - assign n647 = n138 & n263 & n694 & n610 & n501 & n677 & n297; - assign n648 = n440 | n576; - assign n649 = n440 | n303; - assign n650 = n59 & n57 & n648 & n649 & n587; - assign n651 = n339 | n591; - assign n652 = i_5_ | n236 | n514; - assign n653 = n528 | n422; - assign n654 = n303 | n194; - assign n655 = n742 & n55 & n180; - assign n656 = n181 | n454; - assign n657 = n236 | n448; - assign n658 = n198 | n182; - assign n659 = n214 & n235 & n671 & n58 & n652 & n137; - assign n660 = n528 | n425; - assign n661 = n440 | n572; - assign n662 = n725 & n632 & n581 & n231 & n400 & n699 & n584; - assign n663 = n147 & n143 & n644 & n410 & n296 & n201 & n362 & n743; - assign n664 = n651 & n445 & n628; - assign n665 = n670 & n713 & n668 & n633 & n598 & n600; - assign n666 = n180 & n257 & n151 & n49 & n694 & n742; - assign n667 = n403 & n219 & n555 & n392 & n371 & n629; - assign n668 = n415 | n448; - assign n669 = n208 | n549; - assign n670 = n454 | n441; - assign n671 = n440 | n467; - assign n672 = n440 | n195; - assign n673 = n422 | n209; - assign n674 = n236 | n453; - assign n675 = n198 | n425; - assign n676 = n236 | n493; - assign n677 = n440 | n538; - assign n678 = n301 | n561 | n444; - assign n679 = n208 | n303; - assign n680 = n263 & n610 & n56; - assign n681 = n208 | n467; - assign n682 = n539 | n449; - assign n683 = ~n461 | ~i_3_ | n454; - assign n684 = n658 & n288 & n623 & n653 & n631 & n630 & n595; - assign n685 = n301 | n423; - assign n686 = n301 | n535; - assign n687 = n536 | n229; - assign n688 = n208 | n575; - assign n689 = n422 | n531 | n356; - assign n690 = n241 | n378; - assign n691 = n301 | n241 | n472; - assign n692 = n538 | n454; - assign n693 = n314 | n544; - assign n694 = n440 | n539; - assign n695 = n190 | n548; - assign n696 = n192 | n389; - assign n697 = n208 | n448; - assign n698 = n236 | n335; - assign n699 = n342 | n590; - assign n700 = n153 & (n440 | n223 | n306); - assign n701 = n440 | n549; - assign n702 = n305 | ~i_7_ | n244; - assign n703 = n527 | n182 | n373; - assign n704 = n638 & n235 & n136 & n677 & n669 & n567 & n217; - assign n705 = n540 | n574; - assign n706 = n425 | n241 | n547; - assign n707 = n164 & (n321 | n415 | n543); - assign n708 = n181 | n301; - assign n709 = n674 & (~i_7_ | n223 | n248); - assign n710 = n342 | n541; - assign n711 = n158 | n337; - assign n712 = ~i_3_ | i_5_ | n305 | n415; - assign n713 = n422 | n198; - assign n714 = n712 & (n354 | ~n461 | n529); - assign n715 = n171 | n323; - assign n716 = i_7_ | n244 | ~n461; - assign n717 = n301 | n225 | n226; - assign n718 = n717 & (n419 | n346); - assign n719 = n182 | n453; - assign n720 = n529 | n225 | n488; - assign n721 = n679 & (n226 | n438); - assign n722 = (n449 | n195) & (n223 | n224); - assign n723 = (n527 | n194) & (n301 | n232); - assign n724 = (n529 | n444) & (n190 | n166); - assign n725 = n339 | n233; - assign n726 = n549 | n194; - assign n727 = n517 & n149 & n725 & n726; - assign n728 = i_8_ | n252 | n488; - assign n729 = n728 & (n240 | n373 | n415); - assign n730 = n729 & (i_3_ | n454 | ~n461); - assign n731 = n533 | n236 | ~n332; - assign n732 = (n475 | n425) & (n473 | n241); - assign n733 = (n194 | n512) & (n529 | n540); - assign n734 = n733 & (n430 | (n724 & n723)); - assign n735 = ~i_0_ | ~i_2_ | ~i_7_ | n342; - assign n736 = n280 & n89 & n735 & n380 & n169 & n83; - assign n737 = (~n332 | n486) & (n232 | n591); - assign n738 = n489 | n190; - assign n739 = n373 | n208 | n547; - assign n740 = (n533 | n415) & (n422 | n232); - assign n741 = n383 & n295 & n675; - assign n742 = i_4_ | i_6_ | n514; - assign n743 = n215 & n204 & n690 & n162 & n726 & n258; - assign n744 = n184 & (n534 | n236); - assign n745 = ~i_2_ | ~i_5_ | n748 | n749; - assign n746 = i_3_ | n430 | n574; - assign n747 = n487 | n565; - assign n748 = i_1_ & (i_4_ | n229); - assign n749 = ~i_1_ & (~i_4_ | n208); -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/bigkey/bigkey.v b/fpga_flow/benchmarks/Verilog/MCNC/bigkey/bigkey.v deleted file mode 100644 index e6cf05c69..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/bigkey/bigkey.v +++ /dev/null @@ -1,2197 +0,0 @@ -// Benchmark "TOP" written by ABC on Tue Mar 5 09:55:28 2019 - -module bigkey ( clock, - Pstart_0_, Pkey_255_, Pkey_254_, Pkey_253_, Pkey_252_, Pkey_251_, - Pkey_250_, Pkey_249_, Pkey_248_, Pkey_247_, Pkey_246_, Pkey_245_, - Pkey_244_, Pkey_243_, Pkey_242_, Pkey_241_, Pkey_240_, Pkey_239_, - Pkey_238_, Pkey_237_, Pkey_236_, Pkey_235_, Pkey_234_, Pkey_233_, - Pkey_232_, Pkey_231_, Pkey_230_, Pkey_229_, Pkey_228_, Pkey_227_, - Pkey_226_, Pkey_225_, Pkey_224_, Pkey_223_, Pkey_222_, Pkey_221_, - Pkey_220_, Pkey_219_, Pkey_218_, Pkey_217_, Pkey_216_, Pkey_215_, - Pkey_214_, Pkey_213_, Pkey_212_, Pkey_211_, Pkey_210_, Pkey_209_, - Pkey_208_, Pkey_207_, Pkey_206_, Pkey_205_, Pkey_204_, Pkey_203_, - Pkey_202_, Pkey_201_, Pkey_200_, Pkey_199_, Pkey_198_, Pkey_197_, - Pkey_196_, Pkey_195_, Pkey_194_, Pkey_193_, Pkey_192_, Pkey_191_, - Pkey_190_, Pkey_189_, Pkey_188_, Pkey_187_, Pkey_186_, Pkey_185_, - Pkey_184_, Pkey_183_, Pkey_182_, Pkey_181_, Pkey_180_, Pkey_179_, - Pkey_178_, Pkey_177_, Pkey_176_, Pkey_175_, Pkey_174_, Pkey_173_, - Pkey_172_, Pkey_171_, Pkey_170_, Pkey_169_, Pkey_168_, Pkey_167_, - Pkey_166_, Pkey_165_, Pkey_164_, Pkey_163_, Pkey_162_, Pkey_161_, - Pkey_160_, Pkey_159_, Pkey_158_, Pkey_157_, Pkey_156_, Pkey_155_, - Pkey_154_, Pkey_153_, Pkey_152_, Pkey_151_, Pkey_150_, Pkey_149_, - Pkey_148_, Pkey_147_, Pkey_146_, Pkey_145_, Pkey_144_, Pkey_143_, - Pkey_142_, Pkey_141_, Pkey_140_, Pkey_139_, Pkey_138_, Pkey_137_, - Pkey_136_, Pkey_135_, Pkey_134_, Pkey_133_, Pkey_132_, Pkey_131_, - Pkey_130_, Pkey_129_, Pkey_128_, Pkey_127_, Pkey_126_, Pkey_125_, - Pkey_124_, Pkey_123_, Pkey_122_, Pkey_121_, Pkey_120_, Pkey_119_, - Pkey_118_, Pkey_117_, Pkey_116_, Pkey_115_, Pkey_114_, Pkey_113_, - Pkey_112_, Pkey_111_, Pkey_110_, Pkey_109_, Pkey_108_, Pkey_107_, - Pkey_106_, Pkey_105_, Pkey_104_, Pkey_103_, Pkey_102_, Pkey_101_, - Pkey_100_, Pkey_99_, Pkey_98_, Pkey_97_, Pkey_96_, Pkey_95_, Pkey_94_, - Pkey_93_, Pkey_92_, Pkey_91_, Pkey_90_, Pkey_89_, Pkey_88_, Pkey_87_, - Pkey_86_, Pkey_85_, Pkey_84_, Pkey_83_, Pkey_82_, Pkey_81_, Pkey_80_, - Pkey_79_, Pkey_78_, Pkey_77_, Pkey_76_, Pkey_75_, Pkey_74_, Pkey_73_, - Pkey_72_, Pkey_71_, Pkey_70_, Pkey_69_, Pkey_68_, Pkey_67_, Pkey_66_, - Pkey_65_, Pkey_64_, Pkey_63_, Pkey_62_, Pkey_61_, Pkey_60_, Pkey_59_, - Pkey_58_, Pkey_57_, Pkey_56_, Pkey_55_, Pkey_54_, Pkey_53_, Pkey_52_, - Pkey_51_, Pkey_50_, Pkey_49_, Pkey_48_, Pkey_47_, Pkey_46_, Pkey_45_, - Pkey_44_, Pkey_43_, Pkey_42_, Pkey_41_, Pkey_40_, Pkey_39_, Pkey_38_, - Pkey_37_, Pkey_36_, Pkey_35_, Pkey_34_, Pkey_33_, Pkey_32_, Pkey_31_, - Pkey_30_, Pkey_29_, Pkey_28_, Pkey_27_, Pkey_26_, Pkey_25_, Pkey_24_, - Pkey_23_, Pkey_22_, Pkey_21_, Pkey_20_, Pkey_19_, Pkey_18_, Pkey_17_, - Pkey_16_, Pkey_15_, Pkey_14_, Pkey_13_, Pkey_12_, Pkey_11_, Pkey_10_, - Pkey_9_, Pkey_8_, Pkey_7_, Pkey_6_, Pkey_5_, Pkey_4_, Pkey_3_, Pkey_2_, - Pkey_1_, Pkey_0_, Pencrypt_0_, Pcount_3_, Pcount_2_, Pcount_1_, - Pcount_0_, - Pnew_count_3_, Pnew_count_2_, Pnew_count_1_, Pnew_count_0_, - Pdata_ready_0_, PKSi_191_, PKSi_190_, PKSi_189_, PKSi_188_, PKSi_187_, - PKSi_186_, PKSi_185_, PKSi_184_, PKSi_183_, PKSi_182_, PKSi_181_, - PKSi_180_, PKSi_179_, PKSi_178_, PKSi_177_, PKSi_176_, PKSi_175_, - PKSi_174_, PKSi_173_, PKSi_172_, PKSi_171_, PKSi_170_, PKSi_169_, - PKSi_168_, PKSi_167_, PKSi_166_, PKSi_165_, PKSi_164_, PKSi_163_, - PKSi_162_, PKSi_161_, PKSi_160_, PKSi_159_, PKSi_158_, PKSi_157_, - PKSi_156_, PKSi_155_, PKSi_154_, PKSi_153_, PKSi_152_, PKSi_151_, - PKSi_150_, PKSi_149_, PKSi_148_, PKSi_147_, PKSi_146_, PKSi_145_, - PKSi_144_, PKSi_143_, PKSi_142_, PKSi_141_, PKSi_140_, PKSi_139_, - PKSi_138_, PKSi_137_, PKSi_136_, PKSi_135_, PKSi_134_, PKSi_133_, - PKSi_132_, PKSi_131_, PKSi_130_, PKSi_129_, PKSi_128_, PKSi_127_, - PKSi_126_, PKSi_125_, PKSi_124_, PKSi_123_, PKSi_122_, PKSi_121_, - PKSi_120_, PKSi_119_, PKSi_118_, PKSi_117_, PKSi_116_, PKSi_115_, - PKSi_114_, PKSi_113_, PKSi_112_, PKSi_111_, PKSi_110_, PKSi_109_, - PKSi_108_, PKSi_107_, PKSi_106_, PKSi_105_, PKSi_104_, PKSi_103_, - PKSi_102_, PKSi_101_, PKSi_100_, PKSi_99_, PKSi_98_, PKSi_97_, - PKSi_96_, PKSi_95_, PKSi_94_, PKSi_93_, PKSi_92_, PKSi_91_, PKSi_90_, - PKSi_89_, PKSi_88_, PKSi_87_, PKSi_86_, PKSi_85_, PKSi_84_, PKSi_83_, - PKSi_82_, PKSi_81_, PKSi_80_, PKSi_79_, PKSi_78_, PKSi_77_, PKSi_76_, - PKSi_75_, PKSi_74_, PKSi_73_, PKSi_72_, PKSi_71_, PKSi_70_, PKSi_69_, - PKSi_68_, PKSi_67_, PKSi_66_, PKSi_65_, PKSi_64_, PKSi_63_, PKSi_62_, - PKSi_61_, PKSi_60_, PKSi_59_, PKSi_58_, PKSi_57_, PKSi_56_, PKSi_55_, - PKSi_54_, PKSi_53_, PKSi_52_, PKSi_51_, PKSi_50_, PKSi_49_, PKSi_48_, - PKSi_47_, PKSi_46_, PKSi_45_, PKSi_44_, PKSi_43_, PKSi_42_, PKSi_41_, - PKSi_40_, PKSi_39_, PKSi_38_, PKSi_37_, PKSi_36_, PKSi_35_, PKSi_34_, - PKSi_33_, PKSi_32_, PKSi_31_, PKSi_30_, PKSi_29_, PKSi_28_, PKSi_27_, - PKSi_26_, PKSi_25_, PKSi_24_, PKSi_23_, PKSi_22_, PKSi_21_, PKSi_20_, - PKSi_19_, PKSi_18_, PKSi_17_, PKSi_16_, PKSi_15_, PKSi_14_, PKSi_13_, - PKSi_12_, PKSi_11_, PKSi_10_, PKSi_9_, PKSi_8_, PKSi_7_, PKSi_6_, - PKSi_5_, PKSi_4_, PKSi_3_, PKSi_2_, PKSi_1_, PKSi_0_ ); - input Pstart_0_, Pkey_255_, Pkey_254_, Pkey_253_, Pkey_252_, - Pkey_251_, Pkey_250_, Pkey_249_, Pkey_248_, Pkey_247_, Pkey_246_, - Pkey_245_, Pkey_244_, Pkey_243_, Pkey_242_, Pkey_241_, Pkey_240_, - Pkey_239_, Pkey_238_, Pkey_237_, Pkey_236_, Pkey_235_, Pkey_234_, - Pkey_233_, Pkey_232_, Pkey_231_, Pkey_230_, Pkey_229_, Pkey_228_, - Pkey_227_, Pkey_226_, Pkey_225_, Pkey_224_, Pkey_223_, Pkey_222_, - Pkey_221_, Pkey_220_, Pkey_219_, Pkey_218_, Pkey_217_, Pkey_216_, - Pkey_215_, Pkey_214_, Pkey_213_, Pkey_212_, Pkey_211_, Pkey_210_, - Pkey_209_, Pkey_208_, Pkey_207_, Pkey_206_, Pkey_205_, Pkey_204_, - Pkey_203_, Pkey_202_, Pkey_201_, Pkey_200_, Pkey_199_, Pkey_198_, - Pkey_197_, Pkey_196_, Pkey_195_, Pkey_194_, Pkey_193_, Pkey_192_, - Pkey_191_, Pkey_190_, Pkey_189_, Pkey_188_, Pkey_187_, Pkey_186_, - Pkey_185_, Pkey_184_, Pkey_183_, Pkey_182_, Pkey_181_, Pkey_180_, - Pkey_179_, Pkey_178_, Pkey_177_, Pkey_176_, Pkey_175_, Pkey_174_, - Pkey_173_, Pkey_172_, Pkey_171_, Pkey_170_, Pkey_169_, Pkey_168_, - Pkey_167_, Pkey_166_, Pkey_165_, Pkey_164_, Pkey_163_, Pkey_162_, - Pkey_161_, Pkey_160_, Pkey_159_, Pkey_158_, Pkey_157_, Pkey_156_, - Pkey_155_, Pkey_154_, Pkey_153_, Pkey_152_, Pkey_151_, Pkey_150_, - Pkey_149_, Pkey_148_, Pkey_147_, Pkey_146_, Pkey_145_, Pkey_144_, - Pkey_143_, Pkey_142_, Pkey_141_, Pkey_140_, Pkey_139_, Pkey_138_, - Pkey_137_, Pkey_136_, Pkey_135_, Pkey_134_, Pkey_133_, Pkey_132_, - Pkey_131_, Pkey_130_, Pkey_129_, Pkey_128_, Pkey_127_, Pkey_126_, - Pkey_125_, Pkey_124_, Pkey_123_, Pkey_122_, Pkey_121_, Pkey_120_, - Pkey_119_, Pkey_118_, Pkey_117_, Pkey_116_, Pkey_115_, Pkey_114_, - Pkey_113_, Pkey_112_, Pkey_111_, Pkey_110_, Pkey_109_, Pkey_108_, - Pkey_107_, Pkey_106_, Pkey_105_, Pkey_104_, Pkey_103_, Pkey_102_, - Pkey_101_, Pkey_100_, Pkey_99_, Pkey_98_, Pkey_97_, Pkey_96_, Pkey_95_, - Pkey_94_, Pkey_93_, Pkey_92_, Pkey_91_, Pkey_90_, Pkey_89_, Pkey_88_, - Pkey_87_, Pkey_86_, Pkey_85_, Pkey_84_, Pkey_83_, Pkey_82_, Pkey_81_, - Pkey_80_, Pkey_79_, Pkey_78_, Pkey_77_, Pkey_76_, Pkey_75_, Pkey_74_, - Pkey_73_, Pkey_72_, Pkey_71_, Pkey_70_, Pkey_69_, Pkey_68_, Pkey_67_, - Pkey_66_, Pkey_65_, Pkey_64_, Pkey_63_, Pkey_62_, Pkey_61_, Pkey_60_, - Pkey_59_, Pkey_58_, Pkey_57_, Pkey_56_, Pkey_55_, Pkey_54_, Pkey_53_, - Pkey_52_, Pkey_51_, Pkey_50_, Pkey_49_, Pkey_48_, Pkey_47_, Pkey_46_, - Pkey_45_, Pkey_44_, Pkey_43_, Pkey_42_, Pkey_41_, Pkey_40_, Pkey_39_, - Pkey_38_, Pkey_37_, Pkey_36_, Pkey_35_, Pkey_34_, Pkey_33_, Pkey_32_, - Pkey_31_, Pkey_30_, Pkey_29_, Pkey_28_, Pkey_27_, Pkey_26_, Pkey_25_, - Pkey_24_, Pkey_23_, Pkey_22_, Pkey_21_, Pkey_20_, Pkey_19_, Pkey_18_, - Pkey_17_, Pkey_16_, Pkey_15_, Pkey_14_, Pkey_13_, Pkey_12_, Pkey_11_, - Pkey_10_, Pkey_9_, Pkey_8_, Pkey_7_, Pkey_6_, Pkey_5_, Pkey_4_, - Pkey_3_, Pkey_2_, Pkey_1_, Pkey_0_, Pencrypt_0_, Pcount_3_, Pcount_2_, - Pcount_1_, Pcount_0_, clock; - output Pnew_count_3_, Pnew_count_2_, Pnew_count_1_, Pnew_count_0_, - Pdata_ready_0_, PKSi_191_, PKSi_190_, PKSi_189_, PKSi_188_, PKSi_187_, - PKSi_186_, PKSi_185_, PKSi_184_, PKSi_183_, PKSi_182_, PKSi_181_, - PKSi_180_, PKSi_179_, PKSi_178_, PKSi_177_, PKSi_176_, PKSi_175_, - PKSi_174_, PKSi_173_, PKSi_172_, PKSi_171_, PKSi_170_, PKSi_169_, - PKSi_168_, PKSi_167_, PKSi_166_, PKSi_165_, PKSi_164_, PKSi_163_, - PKSi_162_, PKSi_161_, PKSi_160_, PKSi_159_, PKSi_158_, PKSi_157_, - PKSi_156_, PKSi_155_, PKSi_154_, PKSi_153_, PKSi_152_, PKSi_151_, - PKSi_150_, PKSi_149_, PKSi_148_, PKSi_147_, PKSi_146_, PKSi_145_, - PKSi_144_, PKSi_143_, PKSi_142_, PKSi_141_, PKSi_140_, PKSi_139_, - PKSi_138_, PKSi_137_, PKSi_136_, PKSi_135_, PKSi_134_, PKSi_133_, - PKSi_132_, PKSi_131_, PKSi_130_, PKSi_129_, PKSi_128_, PKSi_127_, - PKSi_126_, PKSi_125_, PKSi_124_, PKSi_123_, PKSi_122_, PKSi_121_, - PKSi_120_, PKSi_119_, PKSi_118_, PKSi_117_, PKSi_116_, PKSi_115_, - PKSi_114_, PKSi_113_, PKSi_112_, PKSi_111_, PKSi_110_, PKSi_109_, - PKSi_108_, PKSi_107_, PKSi_106_, PKSi_105_, PKSi_104_, PKSi_103_, - PKSi_102_, PKSi_101_, PKSi_100_, PKSi_99_, PKSi_98_, PKSi_97_, - PKSi_96_, PKSi_95_, PKSi_94_, PKSi_93_, PKSi_92_, PKSi_91_, PKSi_90_, - PKSi_89_, PKSi_88_, PKSi_87_, PKSi_86_, PKSi_85_, PKSi_84_, PKSi_83_, - PKSi_82_, PKSi_81_, PKSi_80_, PKSi_79_, PKSi_78_, PKSi_77_, PKSi_76_, - PKSi_75_, PKSi_74_, PKSi_73_, PKSi_72_, PKSi_71_, PKSi_70_, PKSi_69_, - PKSi_68_, PKSi_67_, PKSi_66_, PKSi_65_, PKSi_64_, PKSi_63_, PKSi_62_, - PKSi_61_, PKSi_60_, PKSi_59_, PKSi_58_, PKSi_57_, PKSi_56_, PKSi_55_, - PKSi_54_, PKSi_53_, PKSi_52_, PKSi_51_, PKSi_50_, PKSi_49_, PKSi_48_, - PKSi_47_, PKSi_46_, PKSi_45_, PKSi_44_, PKSi_43_, PKSi_42_, PKSi_41_, - PKSi_40_, PKSi_39_, PKSi_38_, PKSi_37_, PKSi_36_, PKSi_35_, PKSi_34_, - PKSi_33_, PKSi_32_, PKSi_31_, PKSi_30_, PKSi_29_, PKSi_28_, PKSi_27_, - PKSi_26_, PKSi_25_, PKSi_24_, PKSi_23_, PKSi_22_, PKSi_21_, PKSi_20_, - PKSi_19_, PKSi_18_, PKSi_17_, PKSi_16_, PKSi_15_, PKSi_14_, PKSi_13_, - PKSi_12_, PKSi_11_, PKSi_10_, PKSi_9_, PKSi_8_, PKSi_7_, PKSi_6_, - PKSi_5_, PKSi_4_, PKSi_3_, PKSi_2_, PKSi_1_, PKSi_0_; - reg PKSi_79_, PKSi_92_, \[333] , N_N2737, PKSi_75_, PKSi_84_, N_N2741, - PKSi_82_, PKSi_93_, PKSi_85_, N_N2746, PKSi_73_, N_N2749, PKSi_80_, - PKSi_72_, PKSi_94_, PKSi_86_, PKSi_74_, PKSi_83_, N_N2757, PKSi_89_, - PKSi_91_, PKSi_81_, PKSi_77_, PKSi_87_, PKSi_78_, PKSi_95_, PKSi_76_, - PKSi_55_, PKSi_68_, PKSi_64_, N_N2770, PKSi_51_, PKSi_60_, N_N2774, - PKSi_58_, PKSi_69_, PKSi_61_, N_N2779, PKSi_49_, PKSi_66_, PKSi_56_, - PKSi_48_, PKSi_70_, PKSi_62_, PKSi_50_, PKSi_59_, N_N2789, PKSi_65_, - PKSi_67_, PKSi_57_, PKSi_53_, PKSi_63_, PKSi_54_, PKSi_71_, PKSi_52_, - PKSi_31_, PKSi_44_, PKSi_40_, N_N2802, PKSi_27_, PKSi_36_, N_N2806, - PKSi_34_, PKSi_45_, PKSi_37_, N_N2811, PKSi_25_, PKSi_42_, PKSi_32_, - PKSi_24_, PKSi_46_, PKSi_38_, PKSi_26_, PKSi_35_, N_N2821, PKSi_41_, - PKSi_43_, PKSi_33_, PKSi_29_, PKSi_39_, PKSi_30_, PKSi_47_, PKSi_28_, - PKSi_7_, PKSi_20_, PKSi_16_, N_N2834, PKSi_3_, PKSi_12_, N_N2838, - PKSi_10_, PKSi_21_, PKSi_13_, N_N2843, PKSi_1_, PKSi_18_, PKSi_8_, - PKSi_0_, PKSi_22_, PKSi_14_, PKSi_2_, PKSi_11_, N_N2853, PKSi_17_, - PKSi_19_, PKSi_9_, PKSi_5_, PKSi_15_, PKSi_6_, PKSi_23_, PKSi_4_, - PKSi_183_, PKSi_173_, N_N2865, PKSi_185_, PKSi_169_, PKSi_176_, - PKSi_188_, \[253] , PKSi_179_, PKSi_172_, PKSi_186_, PKSi_177_, - PKSi_180_, N_N2877, N_N2879, N_N2881, PKSi_175_, PKSi_182_, N_N2885, - PKSi_171_, PKSi_189_, N_N2889, PKSi_184_, PKSi_178_, \[234] , - PKSi_170_, PKSi_174_, PKSi_190_, PKSi_159_, PKSi_149_, N_N2899, - PKSi_161_, PKSi_145_, PKSi_152_, PKSi_164_, PKSi_157_, PKSi_155_, - PKSi_148_, PKSi_162_, N_N2909, PKSi_156_, PKSi_153_, PKSi_163_, - PKSi_144_, PKSi_151_, PKSi_158_, N_N2917, PKSi_147_, PKSi_165_, - N_N2921, PKSi_160_, PKSi_154_, PKSi_167_, PKSi_146_, PKSi_150_, - PKSi_166_, PKSi_135_, PKSi_125_, N_N2931, PKSi_137_, PKSi_121_, - PKSi_128_, PKSi_140_, PKSi_133_, PKSi_131_, PKSi_124_, PKSi_138_, - PKSi_129_, PKSi_132_, N_N2943, N_N2945, PKSi_120_, PKSi_127_, - PKSi_134_, N_N2950, PKSi_123_, PKSi_141_, N_N2954, PKSi_136_, - PKSi_130_, \[282] , PKSi_122_, PKSi_126_, PKSi_142_, PKSi_111_, - PKSi_101_, N_N2964, PKSi_113_, PKSi_97_, PKSi_104_, PKSi_116_, - PKSi_109_, PKSi_107_, PKSi_100_, PKSi_114_, PKSi_105_, PKSi_108_, - N_N2976, PKSi_115_, PKSi_96_, PKSi_103_, PKSi_110_, N_N2982, PKSi_99_, - PKSi_117_, N_N2986, PKSi_112_, PKSi_106_, PKSi_119_, PKSi_98_, - PKSi_102_, PKSi_118_; - wire n1137, n1138, n1139_1, n1140, n1141, n1142, n1143_1, n1144, n1145, - n1146, n1148, n1150, n1152, n1154, n1156, n1158, n1160, n1162, n1164, - n1166, n1168, n1170, n1172_1, n1174, n1176_1, n1178, n1180_1, n1182, - n1184, n1186, n1188, n1190, n1192, n1194, n1196, n1198, n1200, n1202_1, - n1204, n1206_1, n1208, n1210_1, n1212, n1214_1, n1216, n1218_1, n1220, - n1222_1, n1224, n1226_1, n1228, n1230_1, n1232, n1234_1, n1236, n1238, - n1240, n1242, n1244, n1246, n1248, n1250, n1252, n1254, n1256, n1258, - n1260, n1262, n1264, n1266, n1268, n1270, n1272, n1274, n1276, n1278, - n1280, n1282, n1284, n1286, n1288_1, n1290, n1292, n1294, n1296, n1298, - n1300, n1302, n1304, n1306, n1308, n1310, n1312, n1314, n1316, n1318, - n1320, n1322, n1324, n1326, n1328, n1330, n1332, n1334, n1336, n1338, - n1340, n1342, n1344, n1346, n1348, n1350, n1352, n1354, n1356, n1358, - n1360, n1362, n1364, n1366, n1368, n1370, n1372, n1374, n1376, n1378, - n1380, n1382, n1384, n1386, n1388, n1390, n1392, n1394, n1396, n1398, - n1400, n1402, n1404, n1406, n1408, n1410, n1412, n1414, n1416, n1418, - n1420, n1422, n1424, n1426, n1428, n1430, n1432, n1434, n1436, n1438, - n1440, n1442, n1444, n1446, n1448, n1450, n1452, n1454, n1456, n1458, - n1460, n1462, n1464, n1466, n1468, n1470, n1472, n1474, n1476, n1478, - n1480, n1482, n1484, n1486, n1488, n1490, n1492, n1494, n1496, n1498, - n1500, n1502, n1504, n1506, n1508, n1510, n1512, n1514, n1516, n1518, - n1520, n1522, n1524, n1526, n1528, n1530, n1532, n1534, n1536, n1538, - n1540, n1542, n1544, n1546, n1548, n1550, n1552, n1554, n1556, n1558, - n1560, n1562, n1564, n1566, n1568, n1570, n1572, n1574, n1576, n1578, - n1580, n1582, n1584, n1586, n1588, n1590, n1592, n1594, n1595, n1596, - n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, - n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, - n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, - n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, - n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, - n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, - n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, - n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, - n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, - n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, - n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, - n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, - n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, - n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, - n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745_1, n1746, - n1747, n1748, n1749_1, n1750, n1751, n1752, n1753, n1754, n1755, n1756, - n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, - n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, - n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, - n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, - n1797, n1798, n1799_1, n1800, n1801, n1802, n1803_1, n1804, n1805, - n1806, n1807_1, n1808, n1809, n1810, n1811_1, n1812, n1813, n1814, - n1815_1, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, - n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833_1, n1834, - n1835, n1836, n1837_1, n1838, n1839, n1840, n1841_1, n1842, n1843, - n1844, n1845_1, n1846, n1847, n1848, n1849_1, n1850, n1851, n1852, - n1853_1, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, - n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, - n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, - n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, - n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, - n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, - n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, - n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, - n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, - n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, - n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, - n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, - n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, - n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, - n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, - n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, - n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, - n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, - n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, - n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, - n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, - n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, - n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, - n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, - n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, - n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, - n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, - n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, - n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, - n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, - n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, - n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, - n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, - n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, - n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, - n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, - n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, - n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, - n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, - n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, - n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, - n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, - n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, - n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, - n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, - n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, - n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, - n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, - n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, - n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, - n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, - n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, - n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, - n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, - n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, - n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, - n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, - n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, - n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, - n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, - n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, - n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, - n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, - n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, - n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, - n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, - n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, - n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, - n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, - n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, - n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, - n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, - n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, - n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, - n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, - n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, - n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, - n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, - n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, - n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, - n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, - n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, - n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, - n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, - n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, - n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, - n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, - n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, - n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n921, - n925_1, n929_1, n934_1, n939_1, n943, n947, n952_1, n956_1, n960_1, - n964_1, n969, n973, n978_1, n982_1, n986_1, n990_1, n994_1, n998_1, - n1002_1, n1007, n1011, n1015, n1019, n1023, n1027, n1031, n1035, n1039, - n1043, n1047, n1051, n1056_1, n1060_1, n1064_1, n1069, n1073, n1077, - n1081, n1086_1, n1090_1, n1094_1, n1098_1, n1102_1, n1106_1, n1110_1, - n1114_1, n1118_1, n1123, n1127, n1131, n1135, n1139, n1143, n1147, - n1151, n1155, n1159, n1163, n1167_1, n1172, n1176, n1180, n1185, n1189, - n1193, n1197, n1202, n1206, n1210, n1214, n1218, n1222, n1226, n1230, - n1234, n1239, n1243, n1247, n1251, n1255, n1259, n1263, n1267, n1271, - n1275, n1279, n1283, n1288, n1292_1, n1296_1, n1301_1, n1305_1, - n1309_1, n1313_1, n1318_1, n1322_1, n1326_1, n1330_1, n1334_1, n1338_1, - n1342_1, n1346_1, n1350_1, n1355_1, n1359_1, n1363_1, n1367_1, n1371_1, - n1375_1, n1379_1, n1383_1, n1387_1, n1391_1, n1395_1, n1400_1, n1404_1, - n1408_1, n1412_1, n1416_1, n1421_1, n1425_1, n1429_1, n1433_1, n1437_1, - n1441_1, n1446_1, n1451_1, n1456_1, n1460_1, n1464_1, n1469_1, n1473_1, - n1477_1, n1482_1, n1486_1, n1490_1, n1495_1, n1499_1, n1503_1, n1507_1, - n1511_1, n1515, n1520_1, n1524_1, n1528_1, n1532_1, n1536_1, n1540_1, - n1544_1, n1548_1, n1552_1, n1557_1, n1561_1, n1565_1, n1569_1, n1573_1, - n1577_1, n1581_1, n1586_1, n1590_1, n1594_1, n1599_1, n1603_1, n1607_1, - n1611_1, n1615_1, n1619_1, n1623_1, n1627_1, n1631_1, n1636_1, n1640_1, - n1644_1, n1648_1, n1652_1, n1656_1, n1660_1, n1664_1, n1668_1, n1672_1, - n1676_1, n1681_1, n1686_1, n1690_1, n1694_1, n1698_1, n1703_1, n1707_1, - n1711_1, n1716_1, n1720_1, n1724_1, n1729_1, n1733_1, n1737_1, n1741_1, - n1745, n1749, n1754_1, n1758_1, n1762_1, n1766_1, n1770_1, n1774_1, - n1778_1, n1782_1, n1786_1, n1790_1, n1794_1, n1799, n1803, n1807, - n1811, n1815, n1820_1, n1824_1, n1828_1, n1833, n1837, n1841, n1845, - n1849, n1853; - assign Pnew_count_3_ = ~n1142; - assign Pnew_count_2_ = ~n1143_1; - assign Pnew_count_1_ = ~n1144; - assign Pnew_count_0_ = ~n1145; - assign Pdata_ready_0_ = ~n1141; - assign n1137 = ~Pstart_0_ | Pencrypt_0_; - assign n1138 = ~Pstart_0_ | ~Pencrypt_0_; - assign n1139_1 = n1597 | Pstart_0_ | Pencrypt_0_; - assign n1140 = n1597 & ~Pstart_0_ & ~Pencrypt_0_; - assign n1141 = n2049 & (Pstart_0_ | n2050); - assign n1142 = n1137 & (Pstart_0_ | n2058); - assign n1143_1 = ~n2053 & (Pencrypt_0_ | n1595) & n2054; - assign n1144 = n1137 & n2051 & (~Pcount_0_ | n2052); - assign n1145 = n1137 & (Pstart_0_ | Pcount_0_); - assign n1146 = n1823 & (~Pkey_62_ | n1138) & n1824; - assign n1387_1 = ~n1146; - assign n1148 = n1821 & (~Pkey_195_ | n1138) & n1822; - assign n1391_1 = ~n1148; - assign n1150 = n1819 & (~Pkey_203_ | n1138) & n1820; - assign n1395_1 = ~n1150; - assign n1152 = n1817 & (~Pkey_211_ | n1138) & n1818; - assign n1400_1 = ~n1152; - assign n1154 = n1815_1 & (~Pkey_219_ | n1138) & n1816; - assign n1404_1 = ~n1154; - assign n1156 = n1813 & (~Pkey_196_ | n1138) & n1814; - assign n1408_1 = ~n1156; - assign n1158 = n1811_1 & (~Pkey_204_ | n1138) & n1812; - assign n1412_1 = ~n1158; - assign n1160 = n1809 & (~Pkey_212_ | n1138) & n1810; - assign n1416_1 = ~n1160; - assign n1162 = n1807_1 & (~Pkey_220_ | n1138) & n1808; - assign n1421_1 = ~n1162; - assign n1164 = n1805 & (~Pkey_228_ | n1138) & n1806; - assign n1425_1 = ~n1164; - assign n1166 = n1803_1 & (~Pkey_172_ | n1138) & n1804; - assign n1429_1 = ~n1166; - assign n1168 = n1801 & (~Pkey_244_ | n1138) & n1802; - assign n1433_1 = ~n1168; - assign n1170 = n1799_1 & (~Pkey_252_ | n1138) & n1800; - assign n1437_1 = ~n1170; - assign n1172_1 = n1797 & (~Pkey_197_ | n1138) & n1798; - assign n1441_1 = ~n1172_1; - assign n1174 = n1795 & (~Pkey_205_ | n1138) & n1796; - assign n1446_1 = ~n1174; - assign n1176_1 = n1793 & (~Pkey_213_ | n1138) & n1794; - assign n1451_1 = ~n1176_1; - assign n1178 = n1791 & (~Pkey_221_ | n1138) & n1792; - assign n1456_1 = ~n1178; - assign n1180_1 = n1789 & (~Pkey_229_ | n1138) & n1790; - assign n1460_1 = ~n1180_1; - assign n1182 = n1787 & (~Pkey_237_ | n1138) & n1788; - assign n1464_1 = ~n1182; - assign n1184 = n1785 & (~Pkey_245_ | n1138) & n1786; - assign n1469_1 = ~n1184; - assign n1186 = n1783 & (~Pkey_253_ | n1138) & n1784; - assign n1473_1 = ~n1186; - assign n1188 = n1781 & (~Pkey_198_ | n1138) & n1782; - assign n1477_1 = ~n1188; - assign n1190 = n1779 & (~Pkey_206_ | n1138) & n1780; - assign n1482_1 = ~n1190; - assign n1192 = n1777 & (~Pkey_214_ | n1138) & n1778; - assign n1486_1 = ~n1192; - assign n1194 = n1775 & (~Pkey_222_ | n1138) & n1776; - assign n1490_1 = ~n1194; - assign n1196 = n1773 & (~Pkey_230_ | n1138) & n1774; - assign n1495_1 = ~n1196; - assign n1198 = n1771 & (~Pkey_238_ | n1138) & n1772; - assign n1499_1 = ~n1198; - assign n1200 = n1769 & (~Pkey_246_ | n1138) & n1770; - assign n1503_1 = ~n1200; - assign n1202_1 = n1767 & (~Pkey_254_ | n1138) & n1768; - assign n1507_1 = ~n1202_1; - assign n1204 = n1765 & (~Pkey_131_ | n1138) & n1766; - assign n1511_1 = ~n1204; - assign n1206_1 = n1763 & (~Pkey_139_ | n1138) & n1764; - assign n1515 = ~n1206_1; - assign n1208 = n1761 & (~Pkey_147_ | n1138) & n1762; - assign n1520_1 = ~n1208; - assign n1210_1 = n1759 & (~Pkey_155_ | n1138) & n1760; - assign n1524_1 = ~n1210_1; - assign n1212 = n1757 & (~Pkey_132_ | n1138) & n1758; - assign n1528_1 = ~n1212; - assign n1214_1 = n1755 & (~Pkey_140_ | n1138) & n1756; - assign n1532_1 = ~n1214_1; - assign n1216 = n1753 & (~Pkey_148_ | n1138) & n1754; - assign n1536_1 = ~n1216; - assign n1218_1 = n1751 & (~Pkey_156_ | n1138) & n1752; - assign n1540_1 = ~n1218_1; - assign n1220 = n1749_1 & (~Pkey_164_ | n1138) & n1750; - assign n1544_1 = ~n1220; - assign n1222_1 = n1747 & (~Pkey_172_ | n1138) & n1748; - assign n1548_1 = ~n1222_1; - assign n1224 = n1745_1 & (~Pkey_180_ | n1138) & n1746; - assign n1552_1 = ~n1224; - assign n1226_1 = n1743 & (~Pkey_188_ | n1138) & n1744; - assign n1557_1 = ~n1226_1; - assign n1228 = n1741 & (~Pkey_133_ | n1138) & n1742; - assign n1561_1 = ~n1228; - assign n1230_1 = n1739 & (~Pkey_141_ | n1138) & n1740; - assign n1565_1 = ~n1230_1; - assign n1232 = n1737 & (~Pkey_149_ | n1138) & n1738; - assign n1569_1 = ~n1232; - assign n1234_1 = n1735 & (~Pkey_157_ | n1138) & n1736; - assign n1573_1 = ~n1234_1; - assign n1236 = n1733 & (~Pkey_165_ | n1138) & n1734; - assign n1577_1 = ~n1236; - assign n1238 = n1731 & (~Pkey_173_ | n1138) & n1732; - assign n1581_1 = ~n1238; - assign n1240 = n1729 & (~Pkey_181_ | n1138) & n1730; - assign n1586_1 = ~n1240; - assign n1242 = n1727 & (~Pkey_189_ | n1138) & n1728; - assign n1590_1 = ~n1242; - assign n1244 = n1725 & (~Pkey_134_ | n1138) & n1726; - assign n1594_1 = ~n1244; - assign n1246 = n1723 & (~Pkey_142_ | n1138) & n1724; - assign n1599_1 = ~n1246; - assign n1248 = n1721 & (~Pkey_150_ | n1138) & n1722; - assign n1603_1 = ~n1248; - assign n1250 = n1719 & (~Pkey_158_ | n1138) & n1720; - assign n1607_1 = ~n1250; - assign n1252 = n1717 & (~Pkey_166_ | n1138) & n1718; - assign n1611_1 = ~n1252; - assign n1254 = n1715 & (~Pkey_174_ | n1138) & n1716; - assign n1615_1 = ~n1254; - assign n1256 = n1713 & (~Pkey_182_ | n1138) & n1714; - assign n1619_1 = ~n1256; - assign n1258 = n1711 & (~Pkey_190_ | n1138) & n1712; - assign n1623_1 = ~n1258; - assign n1260 = n1709 & (~Pkey_67_ | n1138) & n1710; - assign n1627_1 = ~n1260; - assign n1262 = n1707 & (~Pkey_75_ | n1138) & n1708; - assign n1631_1 = ~n1262; - assign n1264 = n1705 & (~Pkey_83_ | n1138) & n1706; - assign n1636_1 = ~n1264; - assign n1266 = n1703 & (~Pkey_91_ | n1138) & n1704; - assign n1640_1 = ~n1266; - assign n1268 = n1701 & (~Pkey_68_ | n1138) & n1702; - assign n1644_1 = ~n1268; - assign n1270 = n1699 & (~Pkey_76_ | n1138) & n1700; - assign n1648_1 = ~n1270; - assign n1272 = n1697 & (~Pkey_84_ | n1138) & n1698; - assign n1652_1 = ~n1272; - assign n1274 = n1695 & (~Pkey_92_ | n1138) & n1696; - assign n1656_1 = ~n1274; - assign n1276 = n1693 & (~Pkey_100_ | n1138) & n1694; - assign n1660_1 = ~n1276; - assign n1278 = n1691 & (~Pkey_44_ | n1138) & n1692; - assign n1664_1 = ~n1278; - assign n1280 = n1689 & (~Pkey_116_ | n1138) & n1690; - assign n1668_1 = ~n1280; - assign n1282 = n1687 & (~Pkey_124_ | n1138) & n1688; - assign n1672_1 = ~n1282; - assign n1284 = n1685 & (~Pkey_69_ | n1138) & n1686; - assign n1676_1 = ~n1284; - assign n1286 = n1683 & (~Pkey_77_ | n1138) & n1684; - assign n1681_1 = ~n1286; - assign n1288_1 = n1681 & (~Pkey_85_ | n1138) & n1682; - assign n1686_1 = ~n1288_1; - assign n1290 = n1679 & (~Pkey_93_ | n1138) & n1680; - assign n1690_1 = ~n1290; - assign n1292 = n1677 & (~Pkey_101_ | n1138) & n1678; - assign n1694_1 = ~n1292; - assign n1294 = n1675 & (~Pkey_109_ | n1138) & n1676; - assign n1698_1 = ~n1294; - assign n1296 = n1673 & (~Pkey_117_ | n1138) & n1674; - assign n1703_1 = ~n1296; - assign n1298 = n1671 & (~Pkey_125_ | n1138) & n1672; - assign n1707_1 = ~n1298; - assign n1300 = n1669 & (~Pkey_70_ | n1138) & n1670; - assign n1711_1 = ~n1300; - assign n1302 = n1667 & (~Pkey_78_ | n1138) & n1668; - assign n1716_1 = ~n1302; - assign n1304 = n1665 & (~Pkey_86_ | n1138) & n1666; - assign n1720_1 = ~n1304; - assign n1306 = n1663 & (~Pkey_94_ | n1138) & n1664; - assign n1724_1 = ~n1306; - assign n1308 = n1661 & (~Pkey_102_ | n1138) & n1662; - assign n1729_1 = ~n1308; - assign n1310 = n1659 & (~Pkey_110_ | n1138) & n1660; - assign n1733_1 = ~n1310; - assign n1312 = n1657 & (~Pkey_118_ | n1138) & n1658; - assign n1737_1 = ~n1312; - assign n1314 = n1655 & (~Pkey_126_ | n1138) & n1656; - assign n1741_1 = ~n1314; - assign n1316 = n1653 & (~Pkey_3_ | n1138) & n1654; - assign n1745 = ~n1316; - assign n1318 = n1651 & (~Pkey_11_ | n1138) & n1652; - assign n1749 = ~n1318; - assign n1320 = n1649 & (~Pkey_19_ | n1138) & n1650; - assign n1754_1 = ~n1320; - assign n1322 = n1647 & (~Pkey_27_ | n1138) & n1648; - assign n1758_1 = ~n1322; - assign n1324 = n1645 & (~Pkey_4_ | n1138) & n1646; - assign n1762_1 = ~n1324; - assign n1326 = n1643 & (~Pkey_12_ | n1138) & n1644; - assign n1766_1 = ~n1326; - assign n1328 = n1641 & (~Pkey_20_ | n1138) & n1642; - assign n1770_1 = ~n1328; - assign n1330 = n1639 & (~Pkey_28_ | n1138) & n1640; - assign n1774_1 = ~n1330; - assign n1332 = n1637 & (~Pkey_36_ | n1138) & n1638; - assign n1778_1 = ~n1332; - assign n1334 = n1635 & (~Pkey_44_ | n1138) & n1636; - assign n1782_1 = ~n1334; - assign n1336 = n1633 & (~Pkey_52_ | n1138) & n1634; - assign n1786_1 = ~n1336; - assign n1338 = n1631 & (~Pkey_60_ | n1138) & n1632; - assign n1790_1 = ~n1338; - assign n1340 = n1629 & (~Pkey_5_ | n1138) & n1630; - assign n1794_1 = ~n1340; - assign n1342 = n1627 & (~Pkey_13_ | n1138) & n1628; - assign n1799 = ~n1342; - assign n1344 = n1625 & (~Pkey_21_ | n1138) & n1626; - assign n1803 = ~n1344; - assign n1346 = n1623 & (~Pkey_29_ | n1138) & n1624; - assign n1807 = ~n1346; - assign n1348 = n1621 & (~Pkey_37_ | n1138) & n1622; - assign n1811 = ~n1348; - assign n1350 = n1619 & (~Pkey_45_ | n1138) & n1620; - assign n1815 = ~n1350; - assign n1352 = n1617 & (~Pkey_53_ | n1138) & n1618; - assign n1820_1 = ~n1352; - assign n1354 = n1615 & (~Pkey_61_ | n1138) & n1616; - assign n1824_1 = ~n1354; - assign n1356 = n1613 & (~Pkey_6_ | n1138) & n1614; - assign n1828_1 = ~n1356; - assign n1358 = n1611 & (~Pkey_14_ | n1138) & n1612; - assign n1833 = ~n1358; - assign n1360 = n1609 & (~Pkey_22_ | n1138) & n1610; - assign n1837 = ~n1360; - assign n1362 = n1607 & (~Pkey_30_ | n1138) & n1608; - assign n1841 = ~n1362; - assign n1364 = n1605 & (~Pkey_38_ | n1138) & n1606; - assign n1845 = ~n1364; - assign n1366 = n1603 & (~Pkey_46_ | n1138) & n1604; - assign n1849 = ~n1366; - assign n1368 = n1601 & (~Pkey_54_ | n1138) & n1602; - assign n1853 = ~n1368; - assign n1370 = n2047 & (~Pkey_56_ | n1138) & n2048; - assign n921 = ~n1370; - assign n1372 = n2045 & (~Pkey_227_ | n1138) & n2046; - assign n925_1 = ~n1372; - assign n1374 = n2043 & (~Pkey_235_ | n1138) & n2044; - assign n929_1 = ~n1374; - assign n1376 = n2041 & (~Pkey_243_ | n1138) & n2042; - assign n934_1 = ~n1376; - assign n1378 = n2039 & (~Pkey_251_ | n1138) & n2040; - assign n939_1 = ~n1378; - assign n1380 = n2037 & (~Pkey_194_ | n1138) & n2038; - assign n943 = ~n1380; - assign n1382 = n2035 & (~Pkey_202_ | n1138) & n2036; - assign n947 = ~n1382; - assign n1384 = n2033 & (~Pkey_210_ | n1138) & n2034; - assign n952_1 = ~n1384; - assign n1386 = n2031 & (~Pkey_218_ | n1138) & n2032; - assign n956_1 = ~n1386; - assign n1388 = n2029 & (~Pkey_226_ | n1138) & n2030; - assign n960_1 = ~n1388; - assign n1390 = n2027 & (~Pkey_234_ | n1138) & n2028; - assign n964_1 = ~n1390; - assign n1392 = n2025 & (~Pkey_242_ | n1138) & n2026; - assign n969 = ~n1392; - assign n1394 = n2023 & (~Pkey_250_ | n1138) & n2024; - assign n973 = ~n1394; - assign n1396 = n2021 & (~Pkey_193_ | n1138) & n2022; - assign n978_1 = ~n1396; - assign n1398 = n2019 & (~Pkey_201_ | n1138) & n2020; - assign n982_1 = ~n1398; - assign n1400 = n2017 & (~Pkey_209_ | n1138) & n2018; - assign n986_1 = ~n1400; - assign n1402 = n2015 & (~Pkey_217_ | n1138) & n2016; - assign n990_1 = ~n1402; - assign n1404 = n2013 & (~Pkey_225_ | n1138) & n2014; - assign n994_1 = ~n1404; - assign n1406 = n2011 & (~Pkey_233_ | n1138) & n2012; - assign n998_1 = ~n1406; - assign n1408 = n2009 & (~Pkey_241_ | n1138) & n2010; - assign n1002_1 = ~n1408; - assign n1410 = n2007 & (~Pkey_249_ | n1138) & n2008; - assign n1007 = ~n1410; - assign n1412 = n2005 & (~Pkey_192_ | n1138) & n2006; - assign n1011 = ~n1412; - assign n1414 = n2003 & (~Pkey_200_ | n1138) & n2004; - assign n1015 = ~n1414; - assign n1416 = n2001 & (~Pkey_208_ | n1138) & n2002; - assign n1019 = ~n1416; - assign n1418 = n1999 & (~Pkey_216_ | n1138) & n2000; - assign n1023 = ~n1418; - assign n1420 = n1997 & (~Pkey_224_ | n1138) & n1998; - assign n1027 = ~n1420; - assign n1422 = n1995 & (~Pkey_232_ | n1138) & n1996; - assign n1031 = ~n1422; - assign n1424 = n1993 & (~Pkey_240_ | n1138) & n1994; - assign n1035 = ~n1424; - assign n1426 = n1991 & (~Pkey_248_ | n1138) & n1992; - assign n1039 = ~n1426; - assign n1428 = n1989 & (~Pkey_163_ | n1138) & n1990; - assign n1043 = ~n1428; - assign n1430 = n1987 & (~Pkey_171_ | n1138) & n1988; - assign n1047 = ~n1430; - assign n1432 = n1985 & (~Pkey_179_ | n1138) & n1986; - assign n1051 = ~n1432; - assign n1434 = n1983 & (~Pkey_187_ | n1138) & n1984; - assign n1056_1 = ~n1434; - assign n1436 = n1981 & (~Pkey_130_ | n1138) & n1982; - assign n1060_1 = ~n1436; - assign n1438 = n1979 & (~Pkey_138_ | n1138) & n1980; - assign n1064_1 = ~n1438; - assign n1440 = n1977 & (~Pkey_146_ | n1138) & n1978; - assign n1069 = ~n1440; - assign n1442 = n1975 & (~Pkey_154_ | n1138) & n1976; - assign n1073 = ~n1442; - assign n1444 = n1973 & (~Pkey_162_ | n1138) & n1974; - assign n1077 = ~n1444; - assign n1446 = n1971 & (~Pkey_170_ | n1138) & n1972; - assign n1081 = ~n1446; - assign n1448 = n1969 & (~Pkey_178_ | n1138) & n1970; - assign n1086_1 = ~n1448; - assign n1450 = n1967 & (~Pkey_186_ | n1138) & n1968; - assign n1090_1 = ~n1450; - assign n1452 = n1965 & (~Pkey_129_ | n1138) & n1966; - assign n1094_1 = ~n1452; - assign n1454 = n1963 & (~Pkey_137_ | n1138) & n1964; - assign n1098_1 = ~n1454; - assign n1456 = n1961 & (~Pkey_145_ | n1138) & n1962; - assign n1102_1 = ~n1456; - assign n1458 = n1959 & (~Pkey_153_ | n1138) & n1960; - assign n1106_1 = ~n1458; - assign n1460 = n1957 & (~Pkey_161_ | n1138) & n1958; - assign n1110_1 = ~n1460; - assign n1462 = n1955 & (~Pkey_169_ | n1138) & n1956; - assign n1114_1 = ~n1462; - assign n1464 = n1953 & (~Pkey_177_ | n1138) & n1954; - assign n1118_1 = ~n1464; - assign n1466 = n1951 & (~Pkey_185_ | n1138) & n1952; - assign n1123 = ~n1466; - assign n1468 = n1949 & (~Pkey_128_ | n1138) & n1950; - assign n1127 = ~n1468; - assign n1470 = n1947 & (~Pkey_136_ | n1138) & n1948; - assign n1131 = ~n1470; - assign n1472 = n1945 & (~Pkey_144_ | n1138) & n1946; - assign n1135 = ~n1472; - assign n1474 = n1943 & (~Pkey_152_ | n1138) & n1944; - assign n1139 = ~n1474; - assign n1476 = n1941 & (~Pkey_160_ | n1138) & n1942; - assign n1143 = ~n1476; - assign n1478 = n1939 & (~Pkey_168_ | n1138) & n1940; - assign n1147 = ~n1478; - assign n1480 = n1937 & (~Pkey_176_ | n1138) & n1938; - assign n1151 = ~n1480; - assign n1482 = n1935 & (~Pkey_184_ | n1138) & n1936; - assign n1155 = ~n1482; - assign n1484 = n1933 & (~Pkey_99_ | n1138) & n1934; - assign n1159 = ~n1484; - assign n1486 = n1931 & (~Pkey_107_ | n1138) & n1932; - assign n1163 = ~n1486; - assign n1488 = n1929 & (~Pkey_115_ | n1138) & n1930; - assign n1167_1 = ~n1488; - assign n1490 = n1927 & (~Pkey_123_ | n1138) & n1928; - assign n1172 = ~n1490; - assign n1492 = n1925 & (~Pkey_66_ | n1138) & n1926; - assign n1176 = ~n1492; - assign n1494 = n1923 & (~Pkey_74_ | n1138) & n1924; - assign n1180 = ~n1494; - assign n1496 = n1921 & (~Pkey_82_ | n1138) & n1922; - assign n1185 = ~n1496; - assign n1498 = n1919 & (~Pkey_90_ | n1138) & n1920; - assign n1189 = ~n1498; - assign n1500 = n1917 & (~Pkey_98_ | n1138) & n1918; - assign n1193 = ~n1500; - assign n1502 = n1915 & (~Pkey_106_ | n1138) & n1916; - assign n1197 = ~n1502; - assign n1504 = n1913 & (~Pkey_114_ | n1138) & n1914; - assign n1202 = ~n1504; - assign n1506 = n1911 & (~Pkey_122_ | n1138) & n1912; - assign n1206 = ~n1506; - assign n1508 = n1909 & (~Pkey_65_ | n1138) & n1910; - assign n1210 = ~n1508; - assign n1510 = n1907 & (~Pkey_73_ | n1138) & n1908; - assign n1214 = ~n1510; - assign n1512 = n1905 & (~Pkey_81_ | n1138) & n1906; - assign n1218 = ~n1512; - assign n1514 = n1903 & (~Pkey_89_ | n1138) & n1904; - assign n1222 = ~n1514; - assign n1516 = n1901 & (~Pkey_97_ | n1138) & n1902; - assign n1226 = ~n1516; - assign n1518 = n1899 & (~Pkey_105_ | n1138) & n1900; - assign n1230 = ~n1518; - assign n1520 = n1897 & (~Pkey_113_ | n1138) & n1898; - assign n1234 = ~n1520; - assign n1522 = n1895 & (~Pkey_121_ | n1138) & n1896; - assign n1239 = ~n1522; - assign n1524 = n1893 & (~Pkey_64_ | n1138) & n1894; - assign n1243 = ~n1524; - assign n1526 = n1891 & (~Pkey_72_ | n1138) & n1892; - assign n1247 = ~n1526; - assign n1528 = n1889 & (~Pkey_80_ | n1138) & n1890; - assign n1251 = ~n1528; - assign n1530 = n1887 & (~Pkey_88_ | n1138) & n1888; - assign n1255 = ~n1530; - assign n1532 = n1885 & (~Pkey_96_ | n1138) & n1886; - assign n1259 = ~n1532; - assign n1534 = n1883 & (~Pkey_104_ | n1138) & n1884; - assign n1263 = ~n1534; - assign n1536 = n1881 & (~Pkey_112_ | n1138) & n1882; - assign n1267 = ~n1536; - assign n1538 = n1879 & (~Pkey_120_ | n1138) & n1880; - assign n1271 = ~n1538; - assign n1540 = n1877 & (~Pkey_35_ | n1138) & n1878; - assign n1275 = ~n1540; - assign n1542 = n1875 & (~Pkey_43_ | n1138) & n1876; - assign n1279 = ~n1542; - assign n1544 = n1873 & (~Pkey_51_ | n1138) & n1874; - assign n1283 = ~n1544; - assign n1546 = n1871 & (~Pkey_59_ | n1138) & n1872; - assign n1288 = ~n1546; - assign n1548 = n1869 & (~Pkey_2_ | n1138) & n1870; - assign n1292_1 = ~n1548; - assign n1550 = n1867 & (~Pkey_10_ | n1138) & n1868; - assign n1296_1 = ~n1550; - assign n1552 = n1865 & (~Pkey_18_ | n1138) & n1866; - assign n1301_1 = ~n1552; - assign n1554 = n1863 & (~Pkey_26_ | n1138) & n1864; - assign n1305_1 = ~n1554; - assign n1556 = n1861 & (~Pkey_34_ | n1138) & n1862; - assign n1309_1 = ~n1556; - assign n1558 = n1859 & (~Pkey_42_ | n1138) & n1860; - assign n1313_1 = ~n1558; - assign n1560 = n1857 & (~Pkey_50_ | n1138) & n1858; - assign n1318_1 = ~n1560; - assign n1562 = n1855 & (~Pkey_58_ | n1138) & n1856; - assign n1322_1 = ~n1562; - assign n1564 = n1853_1 & (~Pkey_1_ | n1138) & n1854; - assign n1326_1 = ~n1564; - assign n1566 = n1851 & (~Pkey_9_ | n1138) & n1852; - assign n1330_1 = ~n1566; - assign n1568 = n1849_1 & (~Pkey_17_ | n1138) & n1850; - assign n1334_1 = ~n1568; - assign n1570 = n1847 & (~Pkey_25_ | n1138) & n1848; - assign n1338_1 = ~n1570; - assign n1572 = n1845_1 & (~Pkey_33_ | n1138) & n1846; - assign n1342_1 = ~n1572; - assign n1574 = n1843 & (~Pkey_41_ | n1138) & n1844; - assign n1346_1 = ~n1574; - assign n1576 = n1841_1 & (~Pkey_49_ | n1138) & n1842; - assign n1350_1 = ~n1576; - assign n1578 = n1839 & (~Pkey_57_ | n1138) & n1840; - assign n1355_1 = ~n1578; - assign n1580 = n1837_1 & (~Pkey_0_ | n1138) & n1838; - assign n1359_1 = ~n1580; - assign n1582 = n1835 & (~Pkey_8_ | n1138) & n1836; - assign n1363_1 = ~n1582; - assign n1584 = n1833_1 & (~Pkey_16_ | n1138) & n1834; - assign n1367_1 = ~n1584; - assign n1586 = n1831 & (~Pkey_24_ | n1138) & n1832; - assign n1371_1 = ~n1586; - assign n1588 = n1829 & (~Pkey_32_ | n1138) & n1830; - assign n1375_1 = ~n1588; - assign n1590 = n1827 & (~Pkey_40_ | n1138) & n1828; - assign n1379_1 = ~n1590; - assign n1592 = n1825 & (~Pkey_48_ | n1138) & n1826; - assign n1383_1 = ~n1592; - assign n1594 = Pcount_3_ | Pcount_1_ | Pcount_2_; - assign n1595 = Pcount_0_ | Pcount_1_ | Pcount_2_; - assign n1596 = ~Pcount_2_ | ~Pcount_1_ | ~Pcount_0_; - assign n1597 = n1594 & n1595 & (~Pcount_3_ | n1596); - assign n1598 = ~Pcount_3_ | ~Pcount_2_ | ~Pcount_1_ | Pcount_0_; - assign n1599 = Pcount_3_ | n1596; - assign n1600 = n1598 & n1599 & (Pcount_3_ | n1595); - assign n1601 = n2179 & (~PKSi_118_ | ~PKSi_4_ | n2172); - assign n1602 = (~Pkey_62_ | n1137) & n2180; - assign n1603 = n2181 & (~PKSi_102_ | ~PKSi_23_ | n2172); - assign n1604 = (~Pkey_54_ | n1137) & n2182; - assign n1605 = n2183 & (~PKSi_98_ | ~PKSi_6_ | n2172); - assign n1606 = (~Pkey_46_ | n1137) & n2184; - assign n1607 = n2185 & (~PKSi_119_ | ~PKSi_15_ | n2172); - assign n1608 = (~Pkey_38_ | n1137) & n2186; - assign n1609 = n2187 & (~PKSi_106_ | ~PKSi_5_ | n2172); - assign n1610 = (~Pkey_30_ | n1137) & n2188; - assign n1611 = n2189 & (~PKSi_112_ | ~PKSi_9_ | n2172); - assign n1612 = (~Pkey_22_ | n1137) & n2190; - assign n1613 = n2191 & (~PKSi_19_ | ~N_N2986 | n2172); - assign n1614 = (~Pkey_14_ | n1137) & n2192; - assign n1615 = n2193 & (~PKSi_117_ | ~PKSi_17_ | n2172); - assign n1616 = (~Pkey_6_ | n1137) & n2194; - assign n1617 = n2195 & (~PKSi_99_ | n2172 | ~N_N2853); - assign n1618 = (~Pkey_61_ | n1137) & n2196; - assign n1619 = n2197 & (~PKSi_11_ | ~N_N2982 | n2172); - assign n1620 = (~Pkey_53_ | n1137) & n2198; - assign n1621 = n2199 & (~PKSi_110_ | ~PKSi_2_ | n2172); - assign n1622 = (~Pkey_45_ | n1137) & n2200; - assign n1623 = n2201 & (~PKSi_103_ | ~PKSi_14_ | n2172); - assign n1624 = (~Pkey_37_ | n1137) & n2202; - assign n1625 = n2203 & (~PKSi_96_ | ~PKSi_22_ | n2172); - assign n1626 = (~Pkey_29_ | n1137) & n2204; - assign n1627 = n2205 & (~PKSi_115_ | ~PKSi_0_ | n2172); - assign n1628 = (~Pkey_21_ | n1137) & n2206; - assign n1629 = n2207 & (~PKSi_8_ | ~N_N2976 | n2172); - assign n1630 = (~Pkey_13_ | n1137) & n2208; - assign n1631 = n2209 & (~PKSi_108_ | ~PKSi_18_ | n2172); - assign n1632 = (~Pkey_5_ | n1137) & n2210; - assign n1633 = n2211 & (~PKSi_105_ | ~PKSi_1_ | n2172); - assign n1634 = (~Pkey_60_ | n1137) & n2212; - assign n1635 = n2213 & (~PKSi_114_ | n2172 | ~N_N2843); - assign n1636 = (~Pkey_52_ | n1137) & n2214; - assign n1637 = n2215 & (~PKSi_100_ | ~PKSi_13_ | n2172); - assign n1638 = (~Pkey_44_ | n1137) & n2216; - assign n1639 = n2217 & (~PKSi_107_ | ~PKSi_21_ | n2172); - assign n1640 = (~Pkey_36_ | n1137) & n2218; - assign n1641 = n2219 & (~PKSi_109_ | ~PKSi_10_ | n2172); - assign n1642 = (~Pkey_28_ | n1137) & n2220; - assign n1643 = n2221 & (~PKSi_116_ | n2172 | ~N_N2838); - assign n1644 = (~Pkey_20_ | n1137) & n2222; - assign n1645 = n2223 & (~PKSi_104_ | ~PKSi_12_ | n2172); - assign n1646 = (~Pkey_12_ | n1137) & n2224; - assign n1647 = n2225 & (~PKSi_97_ | ~PKSi_3_ | n2172); - assign n1648 = (~Pkey_4_ | n1137) & n2226; - assign n1649 = n2227 & (~PKSi_113_ | n2172 | ~N_N2834); - assign n1650 = (~Pkey_27_ | n1137) & n2228; - assign n1651 = n2229 & (~PKSi_16_ | ~N_N2964 | n2172); - assign n1652 = (~Pkey_19_ | n1137) & n2230; - assign n1653 = n2231 & (~PKSi_101_ | ~PKSi_20_ | n2172); - assign n1654 = (~Pkey_11_ | n1137) & n2232; - assign n1655 = n2233 & (~PKSi_111_ | ~PKSi_7_ | n2172); - assign n1656 = (~Pkey_3_ | n1137) & n2234; - assign n1657 = n2235 & (~PKSi_142_ | ~PKSi_28_ | n2172); - assign n1658 = (~Pkey_126_ | n1137) & n2236; - assign n1659 = n2237 & (~PKSi_126_ | ~PKSi_47_ | n2172); - assign n1660 = (~Pkey_118_ | n1137) & n2238; - assign n1661 = n2239 & (~PKSi_122_ | ~PKSi_30_ | n2172); - assign n1662 = (~Pkey_110_ | n1137) & n2240; - assign n1663 = n2241 & (~\[282] | ~PKSi_39_ | n2172); - assign n1664 = (~Pkey_102_ | n1137) & n2242; - assign n1665 = n2243 & (~PKSi_130_ | ~PKSi_29_ | n2172); - assign n1666 = (~Pkey_94_ | n1137) & n2244; - assign n1667 = n2245 & (~PKSi_136_ | ~PKSi_33_ | n2172); - assign n1668 = (~Pkey_86_ | n1137) & n2246; - assign n1669 = n2247 & (~PKSi_43_ | ~N_N2954 | n2172); - assign n1670 = (~Pkey_78_ | n1137) & n2248; - assign n1671 = n2249 & (~PKSi_141_ | ~PKSi_41_ | n2172); - assign n1672 = (~Pkey_70_ | n1137) & n2250; - assign n1673 = n2251 & (~PKSi_123_ | n2172 | ~N_N2821); - assign n1674 = (~Pkey_125_ | n1137) & n2252; - assign n1675 = n2253 & (~PKSi_35_ | ~N_N2950 | n2172); - assign n1676 = (~Pkey_117_ | n1137) & n2254; - assign n1677 = n2255 & (~PKSi_134_ | ~PKSi_26_ | n2172); - assign n1678 = (~Pkey_109_ | n1137) & n2256; - assign n1679 = n2257 & (~PKSi_127_ | ~PKSi_38_ | n2172); - assign n1680 = (~Pkey_101_ | n1137) & n2258; - assign n1681 = n2259 & (~PKSi_120_ | ~PKSi_46_ | n2172); - assign n1682 = (~Pkey_93_ | n1137) & n2260; - assign n1683 = n2261 & (~PKSi_24_ | ~N_N2945 | n2172); - assign n1684 = (~Pkey_85_ | n1137) & n2262; - assign n1685 = n2263 & (~PKSi_32_ | ~N_N2943 | n2172); - assign n1686 = (~Pkey_77_ | n1137) & n2264; - assign n1687 = n2265 & (~PKSi_132_ | ~PKSi_42_ | n2172); - assign n1688 = (~Pkey_69_ | n1137) & n2266; - assign n1689 = n2267 & (~PKSi_129_ | ~PKSi_25_ | n2172); - assign n1690 = (~Pkey_124_ | n1137) & n2268; - assign n1691 = n2269 & (~PKSi_138_ | n2172 | ~N_N2811); - assign n1692 = (~Pkey_116_ | n1137) & n2270; - assign n1693 = n2271 & (~PKSi_124_ | ~PKSi_37_ | n2172); - assign n1694 = (~Pkey_44_ | n1137) & n2272; - assign n1695 = n2273 & (~PKSi_131_ | ~PKSi_45_ | n2172); - assign n1696 = (~Pkey_100_ | n1137) & n2274; - assign n1697 = n2275 & (~PKSi_133_ | ~PKSi_34_ | n2172); - assign n1698 = (~Pkey_92_ | n1137) & n2276; - assign n1699 = n2277 & (~PKSi_140_ | n2172 | ~N_N2806); - assign n1700 = (~Pkey_84_ | n1137) & n2278; - assign n1701 = n2279 & (~PKSi_128_ | ~PKSi_36_ | n2172); - assign n1702 = (~Pkey_76_ | n1137) & n2280; - assign n1703 = n2281 & (~PKSi_121_ | ~PKSi_27_ | n2172); - assign n1704 = (~Pkey_68_ | n1137) & n2282; - assign n1705 = n2283 & (~PKSi_137_ | n2172 | ~N_N2802); - assign n1706 = (~Pkey_91_ | n1137) & n2284; - assign n1707 = n2285 & (~PKSi_40_ | ~N_N2931 | n2172); - assign n1708 = (~Pkey_83_ | n1137) & n2286; - assign n1709 = n2287 & (~PKSi_125_ | ~PKSi_44_ | n2172); - assign n1710 = (~Pkey_75_ | n1137) & n2288; - assign n1711 = n2289 & (~PKSi_135_ | ~PKSi_31_ | n2172); - assign n1712 = (~Pkey_67_ | n1137) & n2290; - assign n1713 = n2291 & (~PKSi_166_ | ~PKSi_52_ | n2172); - assign n1714 = (~Pkey_190_ | n1137) & n2292; - assign n1715 = n2293 & (~PKSi_150_ | ~PKSi_71_ | n2172); - assign n1716 = (~Pkey_182_ | n1137) & n2294; - assign n1717 = n2295 & (~PKSi_146_ | ~PKSi_54_ | n2172); - assign n1718 = (~Pkey_174_ | n1137) & n2296; - assign n1719 = n2297 & (~PKSi_167_ | ~PKSi_63_ | n2172); - assign n1720 = (~Pkey_166_ | n1137) & n2298; - assign n1721 = n2299 & (~PKSi_154_ | ~PKSi_53_ | n2172); - assign n1722 = (~Pkey_158_ | n1137) & n2300; - assign n1723 = n2301 & (~PKSi_160_ | ~PKSi_57_ | n2172); - assign n1724 = (~Pkey_150_ | n1137) & n2302; - assign n1725 = n2303 & (~PKSi_67_ | ~N_N2921 | n2172); - assign n1726 = (~Pkey_142_ | n1137) & n2304; - assign n1727 = n2305 & (~PKSi_165_ | ~PKSi_65_ | n2172); - assign n1728 = (~Pkey_134_ | n1137) & n2306; - assign n1729 = n2307 & (~PKSi_147_ | n2172 | ~N_N2789); - assign n1730 = (~Pkey_189_ | n1137) & n2308; - assign n1731 = n2309 & (~PKSi_59_ | ~N_N2917 | n2172); - assign n1732 = (~Pkey_181_ | n1137) & n2310; - assign n1733 = n2311 & (~PKSi_158_ | ~PKSi_50_ | n2172); - assign n1734 = (~Pkey_173_ | n1137) & n2312; - assign n1735 = n2313 & (~PKSi_151_ | ~PKSi_62_ | n2172); - assign n1736 = (~Pkey_165_ | n1137) & n2314; - assign n1737 = n2315 & (~PKSi_144_ | ~PKSi_70_ | n2172); - assign n1738 = (~Pkey_157_ | n1137) & n2316; - assign n1739 = n2317 & (~PKSi_163_ | ~PKSi_48_ | n2172); - assign n1740 = (~Pkey_149_ | n1137) & n2318; - assign n1741 = n2319 & (~PKSi_153_ | ~PKSi_56_ | n2172); - assign n1742 = (~Pkey_141_ | n1137) & n2320; - assign n1743 = n2321 & (~PKSi_156_ | ~PKSi_66_ | n2172); - assign n1744 = (~Pkey_133_ | n1137) & n2322; - assign n1745_1 = n2323 & (~PKSi_49_ | ~N_N2909 | n2172); - assign n1746 = (~Pkey_188_ | n1137) & n2324; - assign n1747 = n2325 & (~PKSi_162_ | n2172 | ~N_N2779); - assign n1748 = (~Pkey_180_ | n1137) & n2326; - assign n1749_1 = n2327 & (~PKSi_148_ | ~PKSi_61_ | n2172); - assign n1750 = (~Pkey_172_ | n1137) & n2328; - assign n1751 = n2329 & (~PKSi_155_ | ~PKSi_69_ | n2172); - assign n1752 = (~Pkey_164_ | n1137) & n2330; - assign n1753 = n2331 & (~PKSi_157_ | ~PKSi_58_ | n2172); - assign n1754 = (~Pkey_156_ | n1137) & n2332; - assign n1755 = n2333 & (~PKSi_164_ | n2172 | ~N_N2774); - assign n1756 = (~Pkey_148_ | n1137) & n2334; - assign n1757 = n2335 & (~PKSi_152_ | ~PKSi_60_ | n2172); - assign n1758 = (~Pkey_140_ | n1137) & n2336; - assign n1759 = n2337 & (~PKSi_145_ | ~PKSi_51_ | n2172); - assign n1760 = (~Pkey_132_ | n1137) & n2338; - assign n1761 = n2339 & (~PKSi_161_ | n2172 | ~N_N2770); - assign n1762 = (~Pkey_155_ | n1137) & n2340; - assign n1763 = n2341 & (~PKSi_64_ | ~N_N2899 | n2172); - assign n1764 = (~Pkey_147_ | n1137) & n2342; - assign n1765 = n2343 & (~PKSi_149_ | ~PKSi_68_ | n2172); - assign n1766 = (~Pkey_139_ | n1137) & n2344; - assign n1767 = n2345 & (~PKSi_159_ | ~PKSi_55_ | n2172); - assign n1768 = (~Pkey_131_ | n1137) & n2346; - assign n1769 = n2347 & (~PKSi_190_ | ~PKSi_76_ | n2172); - assign n1770 = (~Pkey_254_ | n1137) & n2348; - assign n1771 = n2349 & (~PKSi_174_ | ~PKSi_95_ | n2172); - assign n1772 = (~Pkey_246_ | n1137) & n2350; - assign n1773 = n2351 & (~PKSi_170_ | ~PKSi_78_ | n2172); - assign n1774 = (~Pkey_238_ | n1137) & n2352; - assign n1775 = n2353 & (~\[234] | ~PKSi_87_ | n2172); - assign n1776 = (~Pkey_230_ | n1137) & n2354; - assign n1777 = n2355 & (~PKSi_178_ | ~PKSi_77_ | n2172); - assign n1778 = (~Pkey_222_ | n1137) & n2356; - assign n1779 = n2357 & (~PKSi_184_ | ~PKSi_81_ | n2172); - assign n1780 = (~Pkey_214_ | n1137) & n2358; - assign n1781 = n2359 & (~PKSi_91_ | ~N_N2889 | n2172); - assign n1782 = (~Pkey_206_ | n1137) & n2360; - assign n1783 = n2361 & (~PKSi_189_ | ~PKSi_89_ | n2172); - assign n1784 = (~Pkey_198_ | n1137) & n2362; - assign n1785 = n2363 & (~PKSi_171_ | n2172 | ~N_N2757); - assign n1786 = (~Pkey_253_ | n1137) & n2364; - assign n1787 = n2365 & (~PKSi_83_ | ~N_N2885 | n2172); - assign n1788 = (~Pkey_245_ | n1137) & n2366; - assign n1789 = n2367 & (~PKSi_182_ | ~PKSi_74_ | n2172); - assign n1790 = (~Pkey_237_ | n1137) & n2368; - assign n1791 = n2369 & (~PKSi_175_ | ~PKSi_86_ | n2172); - assign n1792 = (~Pkey_229_ | n1137) & n2370; - assign n1793 = n2371 & (~PKSi_94_ | ~N_N2881 | n2172); - assign n1794 = (~Pkey_221_ | n1137) & n2372; - assign n1795 = n2373 & (~PKSi_72_ | ~N_N2879 | n2172); - assign n1796 = (~Pkey_213_ | n1137) & n2374; - assign n1797 = n2375 & (~PKSi_80_ | ~N_N2877 | n2172); - assign n1798 = (~Pkey_205_ | n1137) & n2376; - assign n1799_1 = n2377 & (~PKSi_180_ | n2172 | ~N_N2749); - assign n1800 = (~Pkey_197_ | n1137) & n2378; - assign n1801 = n2379 & (~PKSi_177_ | ~PKSi_73_ | n2172); - assign n1802 = (~Pkey_252_ | n1137) & n2380; - assign n1803_1 = n2381 & (~PKSi_186_ | n2172 | ~N_N2746); - assign n1804 = (~Pkey_244_ | n1137) & n2382; - assign n1805 = n2383 & (~PKSi_172_ | ~PKSi_85_ | n2172); - assign n1806 = (~Pkey_172_ | n1137) & n2384; - assign n1807_1 = n2385 & (~PKSi_179_ | ~PKSi_93_ | n2172); - assign n1808 = (~Pkey_228_ | n1137) & n2386; - assign n1809 = n2387 & (~\[253] | ~PKSi_82_ | n2172); - assign n1810 = (~Pkey_220_ | n1137) & n2388; - assign n1811_1 = n2389 & (~PKSi_188_ | n2172 | ~N_N2741); - assign n1812 = (~Pkey_212_ | n1137) & n2390; - assign n1813 = n2391 & (~PKSi_176_ | ~PKSi_84_ | n2172); - assign n1814 = (~Pkey_204_ | n1137) & n2392; - assign n1815_1 = n2393 & (~PKSi_169_ | ~PKSi_75_ | n2172); - assign n1816 = (~Pkey_196_ | n1137) & n2394; - assign n1817 = n2395 & (~PKSi_185_ | n2172 | ~N_N2737); - assign n1818 = (~Pkey_219_ | n1137) & n2396; - assign n1819 = n2397 & (~\[333] | ~N_N2865 | n2172); - assign n1820 = (~Pkey_211_ | n1137) & n2398; - assign n1821 = n2399 & (~PKSi_173_ | ~PKSi_92_ | n2172); - assign n1822 = (~Pkey_203_ | n1137) & n2400; - assign n1823 = n2401 & (~PKSi_183_ | ~PKSi_79_ | n2172); - assign n1824 = (~Pkey_195_ | n1137) & n2402; - assign n1825 = (n2059 | n2176) & (~n2175 | n2403); - assign n1826 = (~Pkey_56_ | n1137) & n2404; - assign n1827 = (n2060 | n2176) & (~n2175 | n2405); - assign n1828 = (~Pkey_48_ | n1137) & n2406; - assign n1829 = (n2061 | n2176) & (~n2175 | n2407); - assign n1830 = (~Pkey_40_ | n1137) & n2408; - assign n1831 = (n2062 | n2176) & (~n2175 | n2409); - assign n1832 = (~Pkey_32_ | n1137) & n2410; - assign n1833_1 = (n2063 | n2176) & (~n2175 | n2411); - assign n1834 = (~Pkey_24_ | n1137) & n2412; - assign n1835 = (n2064 | n2176) & (~n2175 | n2413); - assign n1836 = (~Pkey_16_ | n1137) & n2414; - assign n1837_1 = (n2065 | n2176) & (~n2175 | n2415); - assign n1838 = (~Pkey_8_ | n1137) & n2416; - assign n1839 = (n2066 | n2176) & (~n2175 | n2417); - assign n1840 = (~Pkey_0_ | n1137) & n2418; - assign n1841_1 = (n2067 | n2176) & (~n2175 | n2419); - assign n1842 = (~Pkey_57_ | n1137) & n2420; - assign n1843 = (n2068 | n2176) & (~n2175 | n2421); - assign n1844 = (~Pkey_49_ | n1137) & n2422; - assign n1845_1 = (n2069 | n2176) & (~n2175 | n2423); - assign n1846 = (~Pkey_41_ | n1137) & n2424; - assign n1847 = (n2070 | n2176) & (~n2175 | n2425); - assign n1848 = (~Pkey_33_ | n1137) & n2426; - assign n1849_1 = (n2071 | n2176) & (~n2175 | n2427); - assign n1850 = (~Pkey_25_ | n1137) & n2428; - assign n1851 = (n2072 | n2176) & (~n2175 | n2429); - assign n1852 = (~Pkey_17_ | n1137) & n2430; - assign n1853_1 = (n2073 | n2176) & (~n2175 | n2431); - assign n1854 = (~Pkey_9_ | n1137) & n2432; - assign n1855 = (n2074 | n2176) & (~n2175 | n2433); - assign n1856 = (~Pkey_1_ | n1137) & n2434; - assign n1857 = (n2075 | n2176) & (~n2175 | n2435); - assign n1858 = (~Pkey_58_ | n1137) & n2436; - assign n1859 = (n2076 | n2176) & (~n2175 | n2437); - assign n1860 = (~Pkey_50_ | n1137) & n2438; - assign n1861 = (n2077 | n2176) & (~n2175 | n2439); - assign n1862 = (~Pkey_42_ | n1137) & n2440; - assign n1863 = (n2078 | n2176) & (~n2175 | n2441); - assign n1864 = (~Pkey_34_ | n1137) & n2442; - assign n1865 = (n2079 | n2176) & (~n2175 | n2443); - assign n1866 = (~Pkey_26_ | n1137) & n2444; - assign n1867 = (n2080 | n2176) & (~n2175 | n2445); - assign n1868 = (~Pkey_18_ | n1137) & n2446; - assign n1869 = (n2081 | n2176) & (~n2175 | n2447); - assign n1870 = (~Pkey_10_ | n1137) & n2448; - assign n1871 = (n2082 | n2176) & (~n2175 | n2449); - assign n1872 = (~Pkey_2_ | n1137) & n2450; - assign n1873 = (n2083 | n2176) & (~n2175 | n2451); - assign n1874 = (~Pkey_59_ | n1137) & n2452; - assign n1875 = (n2084 | n2176) & (~n2175 | n2453); - assign n1876 = (~Pkey_51_ | n1137) & n2454; - assign n1877 = (n2085 | n2176) & (~n2175 | n2455); - assign n1878 = (~Pkey_43_ | n1137) & n2456; - assign n1879 = (n2086 | n2176) & (~n2175 | n2457); - assign n1880 = (~Pkey_35_ | n1137) & n2458; - assign n1881 = (n2087 | n2176) & (~n2175 | n2459); - assign n1882 = (~Pkey_120_ | n1137) & n2460; - assign n1883 = (n2088 | n2176) & (~n2175 | n2461); - assign n1884 = (~Pkey_112_ | n1137) & n2462; - assign n1885 = (n2089 | n2176) & (~n2175 | n2463); - assign n1886 = (~Pkey_104_ | n1137) & n2464; - assign n1887 = (n2090 | n2176) & (~n2175 | n2465); - assign n1888 = (~Pkey_96_ | n1137) & n2466; - assign n1889 = (n2091 | n2176) & (~n2175 | n2467); - assign n1890 = (~Pkey_88_ | n1137) & n2468; - assign n1891 = (n2092 | n2176) & (~n2175 | n2469); - assign n1892 = (~Pkey_80_ | n1137) & n2470; - assign n1893 = (n2093 | n2176) & (~n2175 | n2471); - assign n1894 = (~Pkey_72_ | n1137) & n2472; - assign n1895 = (n2094 | n2176) & (~n2175 | n2473); - assign n1896 = (~Pkey_64_ | n1137) & n2474; - assign n1897 = (n2095 | n2176) & (~n2175 | n2475); - assign n1898 = (~Pkey_121_ | n1137) & n2476; - assign n1899 = (n2096 | n2176) & (~n2175 | n2477); - assign n1900 = (~Pkey_113_ | n1137) & n2478; - assign n1901 = (n2097 | n2176) & (~n2175 | n2479); - assign n1902 = (~Pkey_105_ | n1137) & n2480; - assign n1903 = (n2098 | n2176) & (~n2175 | n2481); - assign n1904 = (~Pkey_97_ | n1137) & n2482; - assign n1905 = (n2099 | n2176) & (~n2175 | n2483); - assign n1906 = (~Pkey_89_ | n1137) & n2484; - assign n1907 = (n2100 | n2176) & (~n2175 | n2485); - assign n1908 = (~Pkey_81_ | n1137) & n2486; - assign n1909 = (n2101 | n2176) & (~n2175 | n2487); - assign n1910 = (~Pkey_73_ | n1137) & n2488; - assign n1911 = (n2102 | n2176) & (~n2175 | n2489); - assign n1912 = (~Pkey_65_ | n1137) & n2490; - assign n1913 = (n2103 | n2176) & (~n2175 | n2491); - assign n1914 = (~Pkey_122_ | n1137) & n2492; - assign n1915 = (n2104 | n2176) & (~n2175 | n2493); - assign n1916 = (~Pkey_114_ | n1137) & n2494; - assign n1917 = (n2105 | n2176) & (~n2175 | n2495); - assign n1918 = (~Pkey_106_ | n1137) & n2496; - assign n1919 = (n2106 | n2176) & (~n2175 | n2497); - assign n1920 = (~Pkey_98_ | n1137) & n2498; - assign n1921 = (n2107 | n2176) & (~n2175 | n2499); - assign n1922 = (~Pkey_90_ | n1137) & n2500; - assign n1923 = (n2108 | n2176) & (~n2175 | n2501); - assign n1924 = (~Pkey_82_ | n1137) & n2502; - assign n1925 = (n2109 | n2176) & (~n2175 | n2503); - assign n1926 = (~Pkey_74_ | n1137) & n2504; - assign n1927 = (n2110 | n2176) & (~n2175 | n2505); - assign n1928 = (~Pkey_66_ | n1137) & n2506; - assign n1929 = (n2111 | n2176) & (~n2175 | n2507); - assign n1930 = (~Pkey_123_ | n1137) & n2508; - assign n1931 = (n2112 | n2176) & (~n2175 | n2509); - assign n1932 = (~Pkey_115_ | n1137) & n2510; - assign n1933 = (n2113 | n2176) & (~n2175 | n2511); - assign n1934 = (~Pkey_107_ | n1137) & n2512; - assign n1935 = (n2114 | n2176) & (~n2175 | n2513); - assign n1936 = (~Pkey_99_ | n1137) & n2514; - assign n1937 = (n2115 | n2176) & (~n2175 | n2515); - assign n1938 = (~Pkey_184_ | n1137) & n2516; - assign n1939 = (n2116 | n2176) & (~n2175 | n2517); - assign n1940 = (~Pkey_176_ | n1137) & n2518; - assign n1941 = (n2117 | n2176) & (~n2175 | n2519); - assign n1942 = (~Pkey_168_ | n1137) & n2520; - assign n1943 = (n2118 | n2176) & (~n2175 | n2521); - assign n1944 = (~Pkey_160_ | n1137) & n2522; - assign n1945 = (n2119 | n2176) & (~n2175 | n2523); - assign n1946 = (~Pkey_152_ | n1137) & n2524; - assign n1947 = (n2120 | n2176) & (~n2175 | n2525); - assign n1948 = (~Pkey_144_ | n1137) & n2526; - assign n1949 = (n2121 | n2176) & (~n2175 | n2527); - assign n1950 = (~Pkey_136_ | n1137) & n2528; - assign n1951 = (n2122 | n2176) & (~n2175 | n2529); - assign n1952 = (~Pkey_128_ | n1137) & n2530; - assign n1953 = (n2123 | n2176) & (~n2175 | n2531); - assign n1954 = (~Pkey_185_ | n1137) & n2532; - assign n1955 = (n2124 | n2176) & (~n2175 | n2533); - assign n1956 = (~Pkey_177_ | n1137) & n2534; - assign n1957 = (n2125 | n2176) & (~n2175 | n2535); - assign n1958 = (~Pkey_169_ | n1137) & n2536; - assign n1959 = (n2126 | n2176) & (~n2175 | n2537); - assign n1960 = (~Pkey_161_ | n1137) & n2538; - assign n1961 = (n2127 | n2176) & (~n2175 | n2539); - assign n1962 = (~Pkey_153_ | n1137) & n2540; - assign n1963 = (n2128 | n2176) & (~n2175 | n2541); - assign n1964 = (~Pkey_145_ | n1137) & n2542; - assign n1965 = (n2129 | n2176) & (~n2175 | n2543); - assign n1966 = (~Pkey_137_ | n1137) & n2544; - assign n1967 = (n2130 | n2176) & (~n2175 | n2545); - assign n1968 = (~Pkey_129_ | n1137) & n2546; - assign n1969 = (n2131 | n2176) & (~n2175 | n2547); - assign n1970 = (~Pkey_186_ | n1137) & n2548; - assign n1971 = (n2132 | n2176) & (~n2175 | n2549); - assign n1972 = (~Pkey_178_ | n1137) & n2550; - assign n1973 = (n2133 | n2176) & (~n2175 | n2551); - assign n1974 = (~Pkey_170_ | n1137) & n2552; - assign n1975 = (n2134 | n2176) & (~n2175 | n2553); - assign n1976 = (~Pkey_162_ | n1137) & n2554; - assign n1977 = (n2135 | n2176) & (~n2175 | n2555); - assign n1978 = (~Pkey_154_ | n1137) & n2556; - assign n1979 = (n2136 | n2176) & (~n2175 | n2557); - assign n1980 = (~Pkey_146_ | n1137) & n2558; - assign n1981 = (n2137 | n2176) & (~n2175 | n2559); - assign n1982 = (~Pkey_138_ | n1137) & n2560; - assign n1983 = (n2138 | n2176) & (~n2175 | n2561); - assign n1984 = (~Pkey_130_ | n1137) & n2562; - assign n1985 = (n2139 | n2176) & (~n2175 | n2563); - assign n1986 = (~Pkey_187_ | n1137) & n2564; - assign n1987 = (n2140 | n2176) & (~n2175 | n2565); - assign n1988 = (~Pkey_179_ | n1137) & n2566; - assign n1989 = (n2141 | n2176) & (~n2175 | n2567); - assign n1990 = (~Pkey_171_ | n1137) & n2568; - assign n1991 = (n2142 | n2176) & (~n2175 | n2569); - assign n1992 = (~Pkey_163_ | n1137) & n2570; - assign n1993 = (n2143 | n2176) & (~n2175 | n2571); - assign n1994 = (~Pkey_248_ | n1137) & n2572; - assign n1995 = (n2144 | n2176) & (~n2175 | n2573); - assign n1996 = (~Pkey_240_ | n1137) & n2574; - assign n1997 = (n2145 | n2176) & (~n2175 | n2575); - assign n1998 = (~Pkey_232_ | n1137) & n2576; - assign n1999 = (n2146 | n2176) & (~n2175 | n2577); - assign n2000 = (~Pkey_224_ | n1137) & n2578; - assign n2001 = (n2147 | n2176) & (~n2175 | n2579); - assign n2002 = (~Pkey_216_ | n1137) & n2580; - assign n2003 = (n2148 | n2176) & (~n2175 | n2581); - assign n2004 = (~Pkey_208_ | n1137) & n2582; - assign n2005 = (n2149 | n2176) & (~n2175 | n2583); - assign n2006 = (~Pkey_200_ | n1137) & n2584; - assign n2007 = (n2150 | n2176) & (~n2175 | n2585); - assign n2008 = (~Pkey_192_ | n1137) & n2586; - assign n2009 = (n2151 | n2176) & (~n2175 | n2587); - assign n2010 = (~Pkey_249_ | n1137) & n2588; - assign n2011 = (n2152 | n2176) & (~n2175 | n2589); - assign n2012 = (~Pkey_241_ | n1137) & n2590; - assign n2013 = (n2153 | n2176) & (~n2175 | n2591); - assign n2014 = (~Pkey_233_ | n1137) & n2592; - assign n2015 = (n2154 | n2176) & (~n2175 | n2593); - assign n2016 = (~Pkey_225_ | n1137) & n2594; - assign n2017 = (n2155 | n2176) & (~n2175 | n2595); - assign n2018 = (~Pkey_217_ | n1137) & n2596; - assign n2019 = (n2156 | n2176) & (~n2175 | n2597); - assign n2020 = (~Pkey_209_ | n1137) & n2598; - assign n2021 = (n2157 | n2176) & (~n2175 | n2599); - assign n2022 = (~Pkey_201_ | n1137) & n2600; - assign n2023 = (n2158 | n2176) & (~n2175 | n2601); - assign n2024 = (~Pkey_193_ | n1137) & n2602; - assign n2025 = (n2159 | n2176) & (~n2175 | n2603); - assign n2026 = (~Pkey_250_ | n1137) & n2604; - assign n2027 = (n2160 | n2176) & (~n2175 | n2605); - assign n2028 = (~Pkey_242_ | n1137) & n2606; - assign n2029 = (n2161 | n2176) & (~n2175 | n2607); - assign n2030 = (~Pkey_234_ | n1137) & n2608; - assign n2031 = (n2162 | n2176) & (~n2175 | n2609); - assign n2032 = (~Pkey_226_ | n1137) & n2610; - assign n2033 = (n2163 | n2176) & (~n2175 | n2611); - assign n2034 = (~Pkey_218_ | n1137) & n2612; - assign n2035 = (n2164 | n2176) & (~n2175 | n2613); - assign n2036 = (~Pkey_210_ | n1137) & n2614; - assign n2037 = (n2165 | n2176) & (~n2175 | n2615); - assign n2038 = (~Pkey_202_ | n1137) & n2616; - assign n2039 = (n2166 | n2176) & (~n2175 | n2617); - assign n2040 = (~Pkey_194_ | n1137) & n2618; - assign n2041 = (n2167 | n2176) & (~n2175 | n2619); - assign n2042 = (~Pkey_251_ | n1137) & n2620; - assign n2043 = (n2168 | n2176) & (~n2175 | n2621); - assign n2044 = (~Pkey_243_ | n1137) & n2622; - assign n2045 = (n2169 | n2176) & (~n2175 | n2623); - assign n2046 = (~Pkey_235_ | n1137) & n2624; - assign n2047 = (n2170 | n2176) & (~n2175 | n2625); - assign n2048 = (~Pkey_227_ | n1137) & n2626; - assign n2049 = ~Pcount_3_ | n1596 | n2177; - assign n2050 = n1595 | Pcount_3_ | Pencrypt_0_; - assign n2051 = (n2739 & (~Pcount_1_ | n2740)) | (Pcount_1_ & n2740); - assign n2052 = Pencrypt_0_ | ~Pcount_1_; - assign n2053 = Pcount_2_ & (~n2052 | ~n2740); - assign n2054 = n1137 & (Pstart_0_ | ~Pcount_0_ | ~n2178); - assign n2055 = ~Pcount_2_ & ~Pcount_0_; - assign n2056 = (~Pencrypt_0_ | n1599) & n2050; - assign n2057 = (~n1596 & (Pencrypt_0_ | n2055)) | (~Pencrypt_0_ & n2055); - assign n2058 = n2056 & (~Pcount_3_ | (n2052 & n2057)); - assign n2059 = ~PKSi_118_ ^ PKSi_4_; - assign n2060 = ~PKSi_102_ ^ PKSi_23_; - assign n2061 = ~PKSi_98_ ^ PKSi_6_; - assign n2062 = ~PKSi_119_ ^ PKSi_15_; - assign n2063 = ~PKSi_106_ ^ PKSi_5_; - assign n2064 = ~PKSi_112_ ^ PKSi_9_; - assign n2065 = ~PKSi_19_ ^ N_N2986; - assign n2066 = ~PKSi_117_ ^ PKSi_17_; - assign n2067 = ~PKSi_99_ ^ N_N2853; - assign n2068 = ~PKSi_11_ ^ N_N2982; - assign n2069 = ~PKSi_110_ ^ PKSi_2_; - assign n2070 = ~PKSi_103_ ^ PKSi_14_; - assign n2071 = ~PKSi_96_ ^ PKSi_22_; - assign n2072 = ~PKSi_115_ ^ PKSi_0_; - assign n2073 = ~PKSi_8_ ^ N_N2976; - assign n2074 = ~PKSi_108_ ^ PKSi_18_; - assign n2075 = ~PKSi_105_ ^ PKSi_1_; - assign n2076 = ~PKSi_114_ ^ N_N2843; - assign n2077 = ~PKSi_100_ ^ PKSi_13_; - assign n2078 = ~PKSi_107_ ^ PKSi_21_; - assign n2079 = ~PKSi_109_ ^ PKSi_10_; - assign n2080 = ~PKSi_116_ ^ N_N2838; - assign n2081 = ~PKSi_104_ ^ PKSi_12_; - assign n2082 = ~PKSi_97_ ^ PKSi_3_; - assign n2083 = ~PKSi_113_ ^ N_N2834; - assign n2084 = ~PKSi_16_ ^ N_N2964; - assign n2085 = ~PKSi_101_ ^ PKSi_20_; - assign n2086 = ~PKSi_111_ ^ PKSi_7_; - assign n2087 = ~PKSi_142_ ^ PKSi_28_; - assign n2088 = ~PKSi_126_ ^ PKSi_47_; - assign n2089 = ~PKSi_122_ ^ PKSi_30_; - assign n2090 = ~\[282] ^ PKSi_39_; - assign n2091 = ~PKSi_130_ ^ PKSi_29_; - assign n2092 = ~PKSi_136_ ^ PKSi_33_; - assign n2093 = ~PKSi_43_ ^ N_N2954; - assign n2094 = ~PKSi_141_ ^ PKSi_41_; - assign n2095 = ~PKSi_123_ ^ N_N2821; - assign n2096 = ~PKSi_35_ ^ N_N2950; - assign n2097 = ~PKSi_134_ ^ PKSi_26_; - assign n2098 = ~PKSi_127_ ^ PKSi_38_; - assign n2099 = ~PKSi_120_ ^ PKSi_46_; - assign n2100 = ~PKSi_24_ ^ N_N2945; - assign n2101 = ~PKSi_32_ ^ N_N2943; - assign n2102 = ~PKSi_132_ ^ PKSi_42_; - assign n2103 = ~PKSi_129_ ^ PKSi_25_; - assign n2104 = ~PKSi_138_ ^ N_N2811; - assign n2105 = ~PKSi_124_ ^ PKSi_37_; - assign n2106 = ~PKSi_131_ ^ PKSi_45_; - assign n2107 = ~PKSi_133_ ^ PKSi_34_; - assign n2108 = ~PKSi_140_ ^ N_N2806; - assign n2109 = ~PKSi_128_ ^ PKSi_36_; - assign n2110 = ~PKSi_121_ ^ PKSi_27_; - assign n2111 = ~PKSi_137_ ^ N_N2802; - assign n2112 = ~PKSi_40_ ^ N_N2931; - assign n2113 = ~PKSi_125_ ^ PKSi_44_; - assign n2114 = ~PKSi_135_ ^ PKSi_31_; - assign n2115 = ~PKSi_166_ ^ PKSi_52_; - assign n2116 = ~PKSi_150_ ^ PKSi_71_; - assign n2117 = ~PKSi_146_ ^ PKSi_54_; - assign n2118 = ~PKSi_167_ ^ PKSi_63_; - assign n2119 = ~PKSi_154_ ^ PKSi_53_; - assign n2120 = ~PKSi_160_ ^ PKSi_57_; - assign n2121 = ~PKSi_67_ ^ N_N2921; - assign n2122 = ~PKSi_165_ ^ PKSi_65_; - assign n2123 = ~PKSi_147_ ^ N_N2789; - assign n2124 = ~PKSi_59_ ^ N_N2917; - assign n2125 = ~PKSi_158_ ^ PKSi_50_; - assign n2126 = ~PKSi_151_ ^ PKSi_62_; - assign n2127 = ~PKSi_144_ ^ PKSi_70_; - assign n2128 = ~PKSi_163_ ^ PKSi_48_; - assign n2129 = ~PKSi_153_ ^ PKSi_56_; - assign n2130 = ~PKSi_156_ ^ PKSi_66_; - assign n2131 = ~PKSi_49_ ^ N_N2909; - assign n2132 = ~PKSi_162_ ^ N_N2779; - assign n2133 = ~PKSi_148_ ^ PKSi_61_; - assign n2134 = ~PKSi_155_ ^ PKSi_69_; - assign n2135 = ~PKSi_157_ ^ PKSi_58_; - assign n2136 = ~PKSi_164_ ^ N_N2774; - assign n2137 = ~PKSi_152_ ^ PKSi_60_; - assign n2138 = ~PKSi_145_ ^ PKSi_51_; - assign n2139 = ~PKSi_161_ ^ N_N2770; - assign n2140 = ~PKSi_64_ ^ N_N2899; - assign n2141 = ~PKSi_149_ ^ PKSi_68_; - assign n2142 = ~PKSi_159_ ^ PKSi_55_; - assign n2143 = ~PKSi_190_ ^ PKSi_76_; - assign n2144 = ~PKSi_174_ ^ PKSi_95_; - assign n2145 = ~PKSi_170_ ^ PKSi_78_; - assign n2146 = ~\[234] ^ PKSi_87_; - assign n2147 = ~PKSi_178_ ^ PKSi_77_; - assign n2148 = ~PKSi_184_ ^ PKSi_81_; - assign n2149 = ~PKSi_91_ ^ N_N2889; - assign n2150 = ~PKSi_189_ ^ PKSi_89_; - assign n2151 = ~PKSi_171_ ^ N_N2757; - assign n2152 = ~PKSi_83_ ^ N_N2885; - assign n2153 = ~PKSi_182_ ^ PKSi_74_; - assign n2154 = ~PKSi_175_ ^ PKSi_86_; - assign n2155 = ~PKSi_94_ ^ N_N2881; - assign n2156 = ~PKSi_72_ ^ N_N2879; - assign n2157 = ~PKSi_80_ ^ N_N2877; - assign n2158 = ~PKSi_180_ ^ N_N2749; - assign n2159 = ~PKSi_177_ ^ PKSi_73_; - assign n2160 = ~PKSi_186_ ^ N_N2746; - assign n2161 = ~PKSi_172_ ^ PKSi_85_; - assign n2162 = ~PKSi_179_ ^ PKSi_93_; - assign n2163 = ~\[253] ^ PKSi_82_; - assign n2164 = ~PKSi_188_ ^ N_N2741; - assign n2165 = ~PKSi_176_ ^ PKSi_84_; - assign n2166 = ~PKSi_169_ ^ PKSi_75_; - assign n2167 = ~PKSi_185_ ^ N_N2737; - assign n2168 = ~\[333] ^ N_N2865; - assign n2169 = ~PKSi_173_ ^ PKSi_92_; - assign n2170 = ~PKSi_183_ ^ PKSi_79_; - assign n2171 = Pencrypt_0_ & ~n1600; - assign n2172 = Pstart_0_ | n2171; - assign n2173 = Pstart_0_ | ~n2171; - assign n2174 = ~Pencrypt_0_ | ~n1600; - assign n2175 = ~Pstart_0_ & n2174; - assign n2176 = Pstart_0_ | n2174; - assign n2177 = Pstart_0_ | ~Pencrypt_0_; - assign n2178 = n2741 & ((Pencrypt_0_ & ~Pcount_2_) | ~Pcount_1_); - assign n2179 = n2059 | n2173; - assign n2180 = (~n1140 & ~n2627) | (n1139_1 & (~n1140 | n2627)); - assign n2181 = n2060 | n2173; - assign n2182 = (~n1140 & ~n2628) | (n1139_1 & (~n1140 | n2628)); - assign n2183 = n2061 | n2173; - assign n2184 = (~n1140 & ~n2629) | (n1139_1 & (~n1140 | n2629)); - assign n2185 = n2062 | n2173; - assign n2186 = (~n1140 & ~n2630) | (n1139_1 & (~n1140 | n2630)); - assign n2187 = n2063 | n2173; - assign n2188 = (~n1140 & ~n2631) | (n1139_1 & (~n1140 | n2631)); - assign n2189 = n2064 | n2173; - assign n2190 = (~n1140 & ~n2632) | (n1139_1 & (~n1140 | n2632)); - assign n2191 = n2065 | n2173; - assign n2192 = (~n1140 & ~n2633) | (n1139_1 & (~n1140 | n2633)); - assign n2193 = n2066 | n2173; - assign n2194 = (~n1140 & ~n2634) | (n1139_1 & (~n1140 | n2634)); - assign n2195 = n2067 | n2173; - assign n2196 = (~n1140 & ~n2635) | (n1139_1 & (~n1140 | n2635)); - assign n2197 = n2068 | n2173; - assign n2198 = (~n1140 & ~n2636) | (n1139_1 & (~n1140 | n2636)); - assign n2199 = n2069 | n2173; - assign n2200 = (~n1140 & ~n2637) | (n1139_1 & (~n1140 | n2637)); - assign n2201 = n2070 | n2173; - assign n2202 = (~n1140 & ~n2638) | (n1139_1 & (~n1140 | n2638)); - assign n2203 = n2071 | n2173; - assign n2204 = (~n1140 & ~n2639) | (n1139_1 & (~n1140 | n2639)); - assign n2205 = n2072 | n2173; - assign n2206 = (~n1140 & ~n2640) | (n1139_1 & (~n1140 | n2640)); - assign n2207 = n2073 | n2173; - assign n2208 = (~n1140 & ~n2641) | (n1139_1 & (~n1140 | n2641)); - assign n2209 = n2074 | n2173; - assign n2210 = (~n1140 & ~n2642) | (n1139_1 & (~n1140 | n2642)); - assign n2211 = n2075 | n2173; - assign n2212 = (~n1140 & ~n2643) | (n1139_1 & (~n1140 | n2643)); - assign n2213 = n2076 | n2173; - assign n2214 = (~n1140 & ~n2644) | (n1139_1 & (~n1140 | n2644)); - assign n2215 = n2077 | n2173; - assign n2216 = (~n1140 & ~n2645) | (n1139_1 & (~n1140 | n2645)); - assign n2217 = n2078 | n2173; - assign n2218 = (~n1140 & ~n2646) | (n1139_1 & (~n1140 | n2646)); - assign n2219 = n2079 | n2173; - assign n2220 = (~n1140 & ~n2647) | (n1139_1 & (~n1140 | n2647)); - assign n2221 = n2080 | n2173; - assign n2222 = (~n1140 & ~n2648) | (n1139_1 & (~n1140 | n2648)); - assign n2223 = n2081 | n2173; - assign n2224 = (~n1140 & ~n2649) | (n1139_1 & (~n1140 | n2649)); - assign n2225 = n2082 | n2173; - assign n2226 = (~n1140 & ~n2650) | (n1139_1 & (~n1140 | n2650)); - assign n2227 = n2083 | n2173; - assign n2228 = (~n1140 & ~n2651) | (n1139_1 & (~n1140 | n2651)); - assign n2229 = n2084 | n2173; - assign n2230 = (~n1140 & ~n2652) | (n1139_1 & (~n1140 | n2652)); - assign n2231 = n2085 | n2173; - assign n2232 = (~n1140 & ~n2653) | (n1139_1 & (~n1140 | n2653)); - assign n2233 = n2086 | n2173; - assign n2234 = (~n1140 & ~n2654) | (n1139_1 & (~n1140 | n2654)); - assign n2235 = n2087 | n2173; - assign n2236 = (~n1140 & ~n2655) | (n1139_1 & (~n1140 | n2655)); - assign n2237 = n2088 | n2173; - assign n2238 = (~n1140 & ~n2656) | (n1139_1 & (~n1140 | n2656)); - assign n2239 = n2089 | n2173; - assign n2240 = (~n1140 & ~n2657) | (n1139_1 & (~n1140 | n2657)); - assign n2241 = n2090 | n2173; - assign n2242 = (~n1140 & ~n2658) | (n1139_1 & (~n1140 | n2658)); - assign n2243 = n2091 | n2173; - assign n2244 = (~n1140 & ~n2659) | (n1139_1 & (~n1140 | n2659)); - assign n2245 = n2092 | n2173; - assign n2246 = (~n1140 & ~n2660) | (n1139_1 & (~n1140 | n2660)); - assign n2247 = n2093 | n2173; - assign n2248 = (~n1140 & ~n2661) | (n1139_1 & (~n1140 | n2661)); - assign n2249 = n2094 | n2173; - assign n2250 = (~n1140 & ~n2662) | (n1139_1 & (~n1140 | n2662)); - assign n2251 = n2095 | n2173; - assign n2252 = (~n1140 & ~n2663) | (n1139_1 & (~n1140 | n2663)); - assign n2253 = n2096 | n2173; - assign n2254 = (~n1140 & ~n2664) | (n1139_1 & (~n1140 | n2664)); - assign n2255 = n2097 | n2173; - assign n2256 = (~n1140 & ~n2665) | (n1139_1 & (~n1140 | n2665)); - assign n2257 = n2098 | n2173; - assign n2258 = (~n1140 & ~n2666) | (n1139_1 & (~n1140 | n2666)); - assign n2259 = n2099 | n2173; - assign n2260 = (~n1140 & ~n2667) | (n1139_1 & (~n1140 | n2667)); - assign n2261 = n2100 | n2173; - assign n2262 = (~n1140 & ~n2668) | (n1139_1 & (~n1140 | n2668)); - assign n2263 = n2101 | n2173; - assign n2264 = (~n1140 & ~n2669) | (n1139_1 & (~n1140 | n2669)); - assign n2265 = n2102 | n2173; - assign n2266 = (~n1140 & ~n2670) | (n1139_1 & (~n1140 | n2670)); - assign n2267 = n2103 | n2173; - assign n2268 = (~n1140 & ~n2671) | (n1139_1 & (~n1140 | n2671)); - assign n2269 = n2104 | n2173; - assign n2270 = (~n1140 & ~n2672) | (n1139_1 & (~n1140 | n2672)); - assign n2271 = n2105 | n2173; - assign n2272 = (~n1140 & ~n2673) | (n1139_1 & (~n1140 | n2673)); - assign n2273 = n2106 | n2173; - assign n2274 = (~n1140 & ~n2674) | (n1139_1 & (~n1140 | n2674)); - assign n2275 = n2107 | n2173; - assign n2276 = (~n1140 & ~n2675) | (n1139_1 & (~n1140 | n2675)); - assign n2277 = n2108 | n2173; - assign n2278 = (~n1140 & ~n2676) | (n1139_1 & (~n1140 | n2676)); - assign n2279 = n2109 | n2173; - assign n2280 = (~n1140 & ~n2677) | (n1139_1 & (~n1140 | n2677)); - assign n2281 = n2110 | n2173; - assign n2282 = (~n1140 & ~n2678) | (n1139_1 & (~n1140 | n2678)); - assign n2283 = n2111 | n2173; - assign n2284 = (~n1140 & ~n2679) | (n1139_1 & (~n1140 | n2679)); - assign n2285 = n2112 | n2173; - assign n2286 = (~n1140 & ~n2680) | (n1139_1 & (~n1140 | n2680)); - assign n2287 = n2113 | n2173; - assign n2288 = (~n1140 & ~n2681) | (n1139_1 & (~n1140 | n2681)); - assign n2289 = n2114 | n2173; - assign n2290 = (~n1140 & ~n2682) | (n1139_1 & (~n1140 | n2682)); - assign n2291 = n2115 | n2173; - assign n2292 = (~n1140 & ~n2683) | (n1139_1 & (~n1140 | n2683)); - assign n2293 = n2116 | n2173; - assign n2294 = (~n1140 & ~n2684) | (n1139_1 & (~n1140 | n2684)); - assign n2295 = n2117 | n2173; - assign n2296 = (~n1140 & ~n2685) | (n1139_1 & (~n1140 | n2685)); - assign n2297 = n2118 | n2173; - assign n2298 = (~n1140 & ~n2686) | (n1139_1 & (~n1140 | n2686)); - assign n2299 = n2119 | n2173; - assign n2300 = (~n1140 & ~n2687) | (n1139_1 & (~n1140 | n2687)); - assign n2301 = n2120 | n2173; - assign n2302 = (~n1140 & ~n2688) | (n1139_1 & (~n1140 | n2688)); - assign n2303 = n2121 | n2173; - assign n2304 = (~n1140 & ~n2689) | (n1139_1 & (~n1140 | n2689)); - assign n2305 = n2122 | n2173; - assign n2306 = (~n1140 & ~n2690) | (n1139_1 & (~n1140 | n2690)); - assign n2307 = n2123 | n2173; - assign n2308 = (~n1140 & ~n2691) | (n1139_1 & (~n1140 | n2691)); - assign n2309 = n2124 | n2173; - assign n2310 = (~n1140 & ~n2692) | (n1139_1 & (~n1140 | n2692)); - assign n2311 = n2125 | n2173; - assign n2312 = (~n1140 & ~n2693) | (n1139_1 & (~n1140 | n2693)); - assign n2313 = n2126 | n2173; - assign n2314 = (~n1140 & ~n2694) | (n1139_1 & (~n1140 | n2694)); - assign n2315 = n2127 | n2173; - assign n2316 = (~n1140 & ~n2695) | (n1139_1 & (~n1140 | n2695)); - assign n2317 = n2128 | n2173; - assign n2318 = (~n1140 & ~n2696) | (n1139_1 & (~n1140 | n2696)); - assign n2319 = n2129 | n2173; - assign n2320 = (~n1140 & ~n2697) | (n1139_1 & (~n1140 | n2697)); - assign n2321 = n2130 | n2173; - assign n2322 = (~n1140 & ~n2698) | (n1139_1 & (~n1140 | n2698)); - assign n2323 = n2131 | n2173; - assign n2324 = (~n1140 & ~n2699) | (n1139_1 & (~n1140 | n2699)); - assign n2325 = n2132 | n2173; - assign n2326 = (~n1140 & ~n2700) | (n1139_1 & (~n1140 | n2700)); - assign n2327 = n2133 | n2173; - assign n2328 = (~n1140 & ~n2701) | (n1139_1 & (~n1140 | n2701)); - assign n2329 = n2134 | n2173; - assign n2330 = (~n1140 & ~n2702) | (n1139_1 & (~n1140 | n2702)); - assign n2331 = n2135 | n2173; - assign n2332 = (~n1140 & ~n2703) | (n1139_1 & (~n1140 | n2703)); - assign n2333 = n2136 | n2173; - assign n2334 = (~n1140 & ~n2704) | (n1139_1 & (~n1140 | n2704)); - assign n2335 = n2137 | n2173; - assign n2336 = (~n1140 & ~n2705) | (n1139_1 & (~n1140 | n2705)); - assign n2337 = n2138 | n2173; - assign n2338 = (~n1140 & ~n2706) | (n1139_1 & (~n1140 | n2706)); - assign n2339 = n2139 | n2173; - assign n2340 = (~n1140 & ~n2707) | (n1139_1 & (~n1140 | n2707)); - assign n2341 = n2140 | n2173; - assign n2342 = (~n1140 & ~n2708) | (n1139_1 & (~n1140 | n2708)); - assign n2343 = n2141 | n2173; - assign n2344 = (~n1140 & ~n2709) | (n1139_1 & (~n1140 | n2709)); - assign n2345 = n2142 | n2173; - assign n2346 = (~n1140 & ~n2710) | (n1139_1 & (~n1140 | n2710)); - assign n2347 = n2143 | n2173; - assign n2348 = (~n1140 & ~n2711) | (n1139_1 & (~n1140 | n2711)); - assign n2349 = n2144 | n2173; - assign n2350 = (~n1140 & ~n2712) | (n1139_1 & (~n1140 | n2712)); - assign n2351 = n2145 | n2173; - assign n2352 = (~n1140 & ~n2713) | (n1139_1 & (~n1140 | n2713)); - assign n2353 = n2146 | n2173; - assign n2354 = (~n1140 & ~n2714) | (n1139_1 & (~n1140 | n2714)); - assign n2355 = n2147 | n2173; - assign n2356 = (~n1140 & ~n2715) | (n1139_1 & (~n1140 | n2715)); - assign n2357 = n2148 | n2173; - assign n2358 = (~n1140 & ~n2716) | (n1139_1 & (~n1140 | n2716)); - assign n2359 = n2149 | n2173; - assign n2360 = (~n1140 & ~n2717) | (n1139_1 & (~n1140 | n2717)); - assign n2361 = n2150 | n2173; - assign n2362 = (~n1140 & ~n2718) | (n1139_1 & (~n1140 | n2718)); - assign n2363 = n2151 | n2173; - assign n2364 = (~n1140 & ~n2719) | (n1139_1 & (~n1140 | n2719)); - assign n2365 = n2152 | n2173; - assign n2366 = (~n1140 & ~n2720) | (n1139_1 & (~n1140 | n2720)); - assign n2367 = n2153 | n2173; - assign n2368 = (~n1140 & ~n2721) | (n1139_1 & (~n1140 | n2721)); - assign n2369 = n2154 | n2173; - assign n2370 = (~n1140 & ~n2722) | (n1139_1 & (~n1140 | n2722)); - assign n2371 = n2155 | n2173; - assign n2372 = (~n1140 & ~n2723) | (n1139_1 & (~n1140 | n2723)); - assign n2373 = n2156 | n2173; - assign n2374 = (~n1140 & ~n2724) | (n1139_1 & (~n1140 | n2724)); - assign n2375 = n2157 | n2173; - assign n2376 = (~n1140 & ~n2725) | (n1139_1 & (~n1140 | n2725)); - assign n2377 = n2158 | n2173; - assign n2378 = (~n1140 & ~n2726) | (n1139_1 & (~n1140 | n2726)); - assign n2379 = n2159 | n2173; - assign n2380 = (~n1140 & ~n2727) | (n1139_1 & (~n1140 | n2727)); - assign n2381 = n2160 | n2173; - assign n2382 = (~n1140 & ~n2728) | (n1139_1 & (~n1140 | n2728)); - assign n2383 = n2161 | n2173; - assign n2384 = (~n1140 & ~n2729) | (n1139_1 & (~n1140 | n2729)); - assign n2385 = n2162 | n2173; - assign n2386 = (~n1140 & ~n2730) | (n1139_1 & (~n1140 | n2730)); - assign n2387 = n2163 | n2173; - assign n2388 = (~n1140 & ~n2731) | (n1139_1 & (~n1140 | n2731)); - assign n2389 = n2164 | n2173; - assign n2390 = (~n1140 & ~n2732) | (n1139_1 & (~n1140 | n2732)); - assign n2391 = n2165 | n2173; - assign n2392 = (~n1140 & ~n2733) | (n1139_1 & (~n1140 | n2733)); - assign n2393 = n2166 | n2173; - assign n2394 = (~n1140 & ~n2734) | (n1139_1 & (~n1140 | n2734)); - assign n2395 = n2167 | n2173; - assign n2396 = (~n1140 & ~n2735) | (n1139_1 & (~n1140 | n2735)); - assign n2397 = n2168 | n2173; - assign n2398 = (~n1140 & ~n2736) | (n1139_1 & (~n1140 | n2736)); - assign n2399 = n2169 | n2173; - assign n2400 = (~n1140 & ~n2737) | (n1139_1 & (~n1140 | n2737)); - assign n2401 = n2170 | n2173; - assign n2402 = (~n1140 & ~n2738) | (n1139_1 & (~n1140 | n2738)); - assign n2403 = ~PKSi_118_ | ~PKSi_4_; - assign n2404 = (~n1140 & n2627) | (n1139_1 & (~n1140 | ~n2627)); - assign n2405 = ~PKSi_102_ | ~PKSi_23_; - assign n2406 = (~n1140 & n2628) | (n1139_1 & (~n1140 | ~n2628)); - assign n2407 = ~PKSi_98_ | ~PKSi_6_; - assign n2408 = (~n1140 & n2629) | (n1139_1 & (~n1140 | ~n2629)); - assign n2409 = ~PKSi_119_ | ~PKSi_15_; - assign n2410 = (~n1140 & n2630) | (n1139_1 & (~n1140 | ~n2630)); - assign n2411 = ~PKSi_106_ | ~PKSi_5_; - assign n2412 = (~n1140 & n2631) | (n1139_1 & (~n1140 | ~n2631)); - assign n2413 = ~PKSi_112_ | ~PKSi_9_; - assign n2414 = (~n1140 & n2632) | (n1139_1 & (~n1140 | ~n2632)); - assign n2415 = ~PKSi_19_ | ~N_N2986; - assign n2416 = (~n1140 & n2633) | (n1139_1 & (~n1140 | ~n2633)); - assign n2417 = ~PKSi_117_ | ~PKSi_17_; - assign n2418 = (~n1140 & n2634) | (n1139_1 & (~n1140 | ~n2634)); - assign n2419 = ~PKSi_99_ | ~N_N2853; - assign n2420 = (~n1140 & n2635) | (n1139_1 & (~n1140 | ~n2635)); - assign n2421 = ~PKSi_11_ | ~N_N2982; - assign n2422 = (~n1140 & n2636) | (n1139_1 & (~n1140 | ~n2636)); - assign n2423 = ~PKSi_110_ | ~PKSi_2_; - assign n2424 = (~n1140 & n2637) | (n1139_1 & (~n1140 | ~n2637)); - assign n2425 = ~PKSi_103_ | ~PKSi_14_; - assign n2426 = (~n1140 & n2638) | (n1139_1 & (~n1140 | ~n2638)); - assign n2427 = ~PKSi_96_ | ~PKSi_22_; - assign n2428 = (~n1140 & n2639) | (n1139_1 & (~n1140 | ~n2639)); - assign n2429 = ~PKSi_115_ | ~PKSi_0_; - assign n2430 = (~n1140 & n2640) | (n1139_1 & (~n1140 | ~n2640)); - assign n2431 = ~PKSi_8_ | ~N_N2976; - assign n2432 = (~n1140 & n2641) | (n1139_1 & (~n1140 | ~n2641)); - assign n2433 = ~PKSi_108_ | ~PKSi_18_; - assign n2434 = (~n1140 & n2642) | (n1139_1 & (~n1140 | ~n2642)); - assign n2435 = ~PKSi_105_ | ~PKSi_1_; - assign n2436 = (~n1140 & n2643) | (n1139_1 & (~n1140 | ~n2643)); - assign n2437 = ~PKSi_114_ | ~N_N2843; - assign n2438 = (~n1140 & n2644) | (n1139_1 & (~n1140 | ~n2644)); - assign n2439 = ~PKSi_100_ | ~PKSi_13_; - assign n2440 = (~n1140 & n2645) | (n1139_1 & (~n1140 | ~n2645)); - assign n2441 = ~PKSi_107_ | ~PKSi_21_; - assign n2442 = (~n1140 & n2646) | (n1139_1 & (~n1140 | ~n2646)); - assign n2443 = ~PKSi_109_ | ~PKSi_10_; - assign n2444 = (~n1140 & n2647) | (n1139_1 & (~n1140 | ~n2647)); - assign n2445 = ~PKSi_116_ | ~N_N2838; - assign n2446 = (~n1140 & n2648) | (n1139_1 & (~n1140 | ~n2648)); - assign n2447 = ~PKSi_104_ | ~PKSi_12_; - assign n2448 = (~n1140 & n2649) | (n1139_1 & (~n1140 | ~n2649)); - assign n2449 = ~PKSi_97_ | ~PKSi_3_; - assign n2450 = (~n1140 & n2650) | (n1139_1 & (~n1140 | ~n2650)); - assign n2451 = ~PKSi_113_ | ~N_N2834; - assign n2452 = (~n1140 & n2651) | (n1139_1 & (~n1140 | ~n2651)); - assign n2453 = ~PKSi_16_ | ~N_N2964; - assign n2454 = (~n1140 & n2652) | (n1139_1 & (~n1140 | ~n2652)); - assign n2455 = ~PKSi_101_ | ~PKSi_20_; - assign n2456 = (~n1140 & n2653) | (n1139_1 & (~n1140 | ~n2653)); - assign n2457 = ~PKSi_111_ | ~PKSi_7_; - assign n2458 = (~n1140 & n2654) | (n1139_1 & (~n1140 | ~n2654)); - assign n2459 = ~PKSi_142_ | ~PKSi_28_; - assign n2460 = (~n1140 & n2655) | (n1139_1 & (~n1140 | ~n2655)); - assign n2461 = ~PKSi_126_ | ~PKSi_47_; - assign n2462 = (~n1140 & n2656) | (n1139_1 & (~n1140 | ~n2656)); - assign n2463 = ~PKSi_122_ | ~PKSi_30_; - assign n2464 = (~n1140 & n2657) | (n1139_1 & (~n1140 | ~n2657)); - assign n2465 = ~\[282] | ~PKSi_39_; - assign n2466 = (~n1140 & n2658) | (n1139_1 & (~n1140 | ~n2658)); - assign n2467 = ~PKSi_130_ | ~PKSi_29_; - assign n2468 = (~n1140 & n2659) | (n1139_1 & (~n1140 | ~n2659)); - assign n2469 = ~PKSi_136_ | ~PKSi_33_; - assign n2470 = (~n1140 & n2660) | (n1139_1 & (~n1140 | ~n2660)); - assign n2471 = ~PKSi_43_ | ~N_N2954; - assign n2472 = (~n1140 & n2661) | (n1139_1 & (~n1140 | ~n2661)); - assign n2473 = ~PKSi_141_ | ~PKSi_41_; - assign n2474 = (~n1140 & n2662) | (n1139_1 & (~n1140 | ~n2662)); - assign n2475 = ~PKSi_123_ | ~N_N2821; - assign n2476 = (~n1140 & n2663) | (n1139_1 & (~n1140 | ~n2663)); - assign n2477 = ~PKSi_35_ | ~N_N2950; - assign n2478 = (~n1140 & n2664) | (n1139_1 & (~n1140 | ~n2664)); - assign n2479 = ~PKSi_134_ | ~PKSi_26_; - assign n2480 = (~n1140 & n2665) | (n1139_1 & (~n1140 | ~n2665)); - assign n2481 = ~PKSi_127_ | ~PKSi_38_; - assign n2482 = (~n1140 & n2666) | (n1139_1 & (~n1140 | ~n2666)); - assign n2483 = ~PKSi_120_ | ~PKSi_46_; - assign n2484 = (~n1140 & n2667) | (n1139_1 & (~n1140 | ~n2667)); - assign n2485 = ~PKSi_24_ | ~N_N2945; - assign n2486 = (~n1140 & n2668) | (n1139_1 & (~n1140 | ~n2668)); - assign n2487 = ~PKSi_32_ | ~N_N2943; - assign n2488 = (~n1140 & n2669) | (n1139_1 & (~n1140 | ~n2669)); - assign n2489 = ~PKSi_132_ | ~PKSi_42_; - assign n2490 = (~n1140 & n2670) | (n1139_1 & (~n1140 | ~n2670)); - assign n2491 = ~PKSi_129_ | ~PKSi_25_; - assign n2492 = (~n1140 & n2671) | (n1139_1 & (~n1140 | ~n2671)); - assign n2493 = ~PKSi_138_ | ~N_N2811; - assign n2494 = (~n1140 & n2672) | (n1139_1 & (~n1140 | ~n2672)); - assign n2495 = ~PKSi_124_ | ~PKSi_37_; - assign n2496 = (~n1140 & n2673) | (n1139_1 & (~n1140 | ~n2673)); - assign n2497 = ~PKSi_131_ | ~PKSi_45_; - assign n2498 = (~n1140 & n2674) | (n1139_1 & (~n1140 | ~n2674)); - assign n2499 = ~PKSi_133_ | ~PKSi_34_; - assign n2500 = (~n1140 & n2675) | (n1139_1 & (~n1140 | ~n2675)); - assign n2501 = ~PKSi_140_ | ~N_N2806; - assign n2502 = (~n1140 & n2676) | (n1139_1 & (~n1140 | ~n2676)); - assign n2503 = ~PKSi_128_ | ~PKSi_36_; - assign n2504 = (~n1140 & n2677) | (n1139_1 & (~n1140 | ~n2677)); - assign n2505 = ~PKSi_121_ | ~PKSi_27_; - assign n2506 = (~n1140 & n2678) | (n1139_1 & (~n1140 | ~n2678)); - assign n2507 = ~PKSi_137_ | ~N_N2802; - assign n2508 = (~n1140 & n2679) | (n1139_1 & (~n1140 | ~n2679)); - assign n2509 = ~PKSi_40_ | ~N_N2931; - assign n2510 = (~n1140 & n2680) | (n1139_1 & (~n1140 | ~n2680)); - assign n2511 = ~PKSi_125_ | ~PKSi_44_; - assign n2512 = (~n1140 & n2681) | (n1139_1 & (~n1140 | ~n2681)); - assign n2513 = ~PKSi_135_ | ~PKSi_31_; - assign n2514 = (~n1140 & n2682) | (n1139_1 & (~n1140 | ~n2682)); - assign n2515 = ~PKSi_166_ | ~PKSi_52_; - assign n2516 = (~n1140 & n2683) | (n1139_1 & (~n1140 | ~n2683)); - assign n2517 = ~PKSi_150_ | ~PKSi_71_; - assign n2518 = (~n1140 & n2684) | (n1139_1 & (~n1140 | ~n2684)); - assign n2519 = ~PKSi_146_ | ~PKSi_54_; - assign n2520 = (~n1140 & n2685) | (n1139_1 & (~n1140 | ~n2685)); - assign n2521 = ~PKSi_167_ | ~PKSi_63_; - assign n2522 = (~n1140 & n2686) | (n1139_1 & (~n1140 | ~n2686)); - assign n2523 = ~PKSi_154_ | ~PKSi_53_; - assign n2524 = (~n1140 & n2687) | (n1139_1 & (~n1140 | ~n2687)); - assign n2525 = ~PKSi_160_ | ~PKSi_57_; - assign n2526 = (~n1140 & n2688) | (n1139_1 & (~n1140 | ~n2688)); - assign n2527 = ~PKSi_67_ | ~N_N2921; - assign n2528 = (~n1140 & n2689) | (n1139_1 & (~n1140 | ~n2689)); - assign n2529 = ~PKSi_165_ | ~PKSi_65_; - assign n2530 = (~n1140 & n2690) | (n1139_1 & (~n1140 | ~n2690)); - assign n2531 = ~PKSi_147_ | ~N_N2789; - assign n2532 = (~n1140 & n2691) | (n1139_1 & (~n1140 | ~n2691)); - assign n2533 = ~PKSi_59_ | ~N_N2917; - assign n2534 = (~n1140 & n2692) | (n1139_1 & (~n1140 | ~n2692)); - assign n2535 = ~PKSi_158_ | ~PKSi_50_; - assign n2536 = (~n1140 & n2693) | (n1139_1 & (~n1140 | ~n2693)); - assign n2537 = ~PKSi_151_ | ~PKSi_62_; - assign n2538 = (~n1140 & n2694) | (n1139_1 & (~n1140 | ~n2694)); - assign n2539 = ~PKSi_144_ | ~PKSi_70_; - assign n2540 = (~n1140 & n2695) | (n1139_1 & (~n1140 | ~n2695)); - assign n2541 = ~PKSi_163_ | ~PKSi_48_; - assign n2542 = (~n1140 & n2696) | (n1139_1 & (~n1140 | ~n2696)); - assign n2543 = ~PKSi_153_ | ~PKSi_56_; - assign n2544 = (~n1140 & n2697) | (n1139_1 & (~n1140 | ~n2697)); - assign n2545 = ~PKSi_156_ | ~PKSi_66_; - assign n2546 = (~n1140 & n2698) | (n1139_1 & (~n1140 | ~n2698)); - assign n2547 = ~PKSi_49_ | ~N_N2909; - assign n2548 = (~n1140 & n2699) | (n1139_1 & (~n1140 | ~n2699)); - assign n2549 = ~PKSi_162_ | ~N_N2779; - assign n2550 = (~n1140 & n2700) | (n1139_1 & (~n1140 | ~n2700)); - assign n2551 = ~PKSi_148_ | ~PKSi_61_; - assign n2552 = (~n1140 & n2701) | (n1139_1 & (~n1140 | ~n2701)); - assign n2553 = ~PKSi_155_ | ~PKSi_69_; - assign n2554 = (~n1140 & n2702) | (n1139_1 & (~n1140 | ~n2702)); - assign n2555 = ~PKSi_157_ | ~PKSi_58_; - assign n2556 = (~n1140 & n2703) | (n1139_1 & (~n1140 | ~n2703)); - assign n2557 = ~PKSi_164_ | ~N_N2774; - assign n2558 = (~n1140 & n2704) | (n1139_1 & (~n1140 | ~n2704)); - assign n2559 = ~PKSi_152_ | ~PKSi_60_; - assign n2560 = (~n1140 & n2705) | (n1139_1 & (~n1140 | ~n2705)); - assign n2561 = ~PKSi_145_ | ~PKSi_51_; - assign n2562 = (~n1140 & n2706) | (n1139_1 & (~n1140 | ~n2706)); - assign n2563 = ~PKSi_161_ | ~N_N2770; - assign n2564 = (~n1140 & n2707) | (n1139_1 & (~n1140 | ~n2707)); - assign n2565 = ~PKSi_64_ | ~N_N2899; - assign n2566 = (~n1140 & n2708) | (n1139_1 & (~n1140 | ~n2708)); - assign n2567 = ~PKSi_149_ | ~PKSi_68_; - assign n2568 = (~n1140 & n2709) | (n1139_1 & (~n1140 | ~n2709)); - assign n2569 = ~PKSi_159_ | ~PKSi_55_; - assign n2570 = (~n1140 & n2710) | (n1139_1 & (~n1140 | ~n2710)); - assign n2571 = ~PKSi_190_ | ~PKSi_76_; - assign n2572 = (~n1140 & n2711) | (n1139_1 & (~n1140 | ~n2711)); - assign n2573 = ~PKSi_174_ | ~PKSi_95_; - assign n2574 = (~n1140 & n2712) | (n1139_1 & (~n1140 | ~n2712)); - assign n2575 = ~PKSi_170_ | ~PKSi_78_; - assign n2576 = (~n1140 & n2713) | (n1139_1 & (~n1140 | ~n2713)); - assign n2577 = ~\[234] | ~PKSi_87_; - assign n2578 = (~n1140 & n2714) | (n1139_1 & (~n1140 | ~n2714)); - assign n2579 = ~PKSi_178_ | ~PKSi_77_; - assign n2580 = (~n1140 & n2715) | (n1139_1 & (~n1140 | ~n2715)); - assign n2581 = ~PKSi_184_ | ~PKSi_81_; - assign n2582 = (~n1140 & n2716) | (n1139_1 & (~n1140 | ~n2716)); - assign n2583 = ~PKSi_91_ | ~N_N2889; - assign n2584 = (~n1140 & n2717) | (n1139_1 & (~n1140 | ~n2717)); - assign n2585 = ~PKSi_189_ | ~PKSi_89_; - assign n2586 = (~n1140 & n2718) | (n1139_1 & (~n1140 | ~n2718)); - assign n2587 = ~PKSi_171_ | ~N_N2757; - assign n2588 = (~n1140 & n2719) | (n1139_1 & (~n1140 | ~n2719)); - assign n2589 = ~PKSi_83_ | ~N_N2885; - assign n2590 = (~n1140 & n2720) | (n1139_1 & (~n1140 | ~n2720)); - assign n2591 = ~PKSi_182_ | ~PKSi_74_; - assign n2592 = (~n1140 & n2721) | (n1139_1 & (~n1140 | ~n2721)); - assign n2593 = ~PKSi_175_ | ~PKSi_86_; - assign n2594 = (~n1140 & n2722) | (n1139_1 & (~n1140 | ~n2722)); - assign n2595 = ~PKSi_94_ | ~N_N2881; - assign n2596 = (~n1140 & n2723) | (n1139_1 & (~n1140 | ~n2723)); - assign n2597 = ~PKSi_72_ | ~N_N2879; - assign n2598 = (~n1140 & n2724) | (n1139_1 & (~n1140 | ~n2724)); - assign n2599 = ~PKSi_80_ | ~N_N2877; - assign n2600 = (~n1140 & n2725) | (n1139_1 & (~n1140 | ~n2725)); - assign n2601 = ~PKSi_180_ | ~N_N2749; - assign n2602 = (~n1140 & n2726) | (n1139_1 & (~n1140 | ~n2726)); - assign n2603 = ~PKSi_177_ | ~PKSi_73_; - assign n2604 = (~n1140 & n2727) | (n1139_1 & (~n1140 | ~n2727)); - assign n2605 = ~PKSi_186_ | ~N_N2746; - assign n2606 = (~n1140 & n2728) | (n1139_1 & (~n1140 | ~n2728)); - assign n2607 = ~PKSi_172_ | ~PKSi_85_; - assign n2608 = (~n1140 & n2729) | (n1139_1 & (~n1140 | ~n2729)); - assign n2609 = ~PKSi_179_ | ~PKSi_93_; - assign n2610 = (~n1140 & n2730) | (n1139_1 & (~n1140 | ~n2730)); - assign n2611 = ~\[253] | ~PKSi_82_; - assign n2612 = (~n1140 & n2731) | (n1139_1 & (~n1140 | ~n2731)); - assign n2613 = ~PKSi_188_ | ~N_N2741; - assign n2614 = (~n1140 & n2732) | (n1139_1 & (~n1140 | ~n2732)); - assign n2615 = ~PKSi_176_ | ~PKSi_84_; - assign n2616 = (~n1140 & n2733) | (n1139_1 & (~n1140 | ~n2733)); - assign n2617 = ~PKSi_169_ | ~PKSi_75_; - assign n2618 = (~n1140 & n2734) | (n1139_1 & (~n1140 | ~n2734)); - assign n2619 = ~PKSi_185_ | ~N_N2737; - assign n2620 = (~n1140 & n2735) | (n1139_1 & (~n1140 | ~n2735)); - assign n2621 = ~\[333] | ~N_N2865; - assign n2622 = (~n1140 & n2736) | (n1139_1 & (~n1140 | ~n2736)); - assign n2623 = ~PKSi_173_ | ~PKSi_92_; - assign n2624 = (~n1140 & n2737) | (n1139_1 & (~n1140 | ~n2737)); - assign n2625 = ~PKSi_183_ | ~PKSi_79_; - assign n2626 = (~n1140 & n2738) | (n1139_1 & (~n1140 | ~n2738)); - assign n2627 = PKSi_4_ | PKSi_118_; - assign n2628 = PKSi_23_ | PKSi_102_; - assign n2629 = PKSi_6_ | PKSi_98_; - assign n2630 = PKSi_15_ | PKSi_119_; - assign n2631 = PKSi_5_ | PKSi_106_; - assign n2632 = PKSi_9_ | PKSi_112_; - assign n2633 = PKSi_19_ | N_N2986; - assign n2634 = PKSi_17_ | PKSi_117_; - assign n2635 = N_N2853 | PKSi_99_; - assign n2636 = PKSi_11_ | N_N2982; - assign n2637 = PKSi_2_ | PKSi_110_; - assign n2638 = PKSi_14_ | PKSi_103_; - assign n2639 = PKSi_22_ | PKSi_96_; - assign n2640 = PKSi_0_ | PKSi_115_; - assign n2641 = PKSi_8_ | N_N2976; - assign n2642 = PKSi_18_ | PKSi_108_; - assign n2643 = PKSi_1_ | PKSi_105_; - assign n2644 = N_N2843 | PKSi_114_; - assign n2645 = PKSi_13_ | PKSi_100_; - assign n2646 = PKSi_21_ | PKSi_107_; - assign n2647 = PKSi_10_ | PKSi_109_; - assign n2648 = N_N2838 | PKSi_116_; - assign n2649 = PKSi_12_ | PKSi_104_; - assign n2650 = PKSi_3_ | PKSi_97_; - assign n2651 = N_N2834 | PKSi_113_; - assign n2652 = PKSi_16_ | N_N2964; - assign n2653 = PKSi_20_ | PKSi_101_; - assign n2654 = PKSi_7_ | PKSi_111_; - assign n2655 = PKSi_28_ | PKSi_142_; - assign n2656 = PKSi_47_ | PKSi_126_; - assign n2657 = PKSi_30_ | PKSi_122_; - assign n2658 = PKSi_39_ | \[282] ; - assign n2659 = PKSi_29_ | PKSi_130_; - assign n2660 = PKSi_33_ | PKSi_136_; - assign n2661 = PKSi_43_ | N_N2954; - assign n2662 = PKSi_41_ | PKSi_141_; - assign n2663 = N_N2821 | PKSi_123_; - assign n2664 = PKSi_35_ | N_N2950; - assign n2665 = PKSi_26_ | PKSi_134_; - assign n2666 = PKSi_38_ | PKSi_127_; - assign n2667 = PKSi_46_ | PKSi_120_; - assign n2668 = PKSi_24_ | N_N2945; - assign n2669 = PKSi_32_ | N_N2943; - assign n2670 = PKSi_42_ | PKSi_132_; - assign n2671 = PKSi_25_ | PKSi_129_; - assign n2672 = N_N2811 | PKSi_138_; - assign n2673 = PKSi_37_ | PKSi_124_; - assign n2674 = PKSi_45_ | PKSi_131_; - assign n2675 = PKSi_34_ | PKSi_133_; - assign n2676 = N_N2806 | PKSi_140_; - assign n2677 = PKSi_36_ | PKSi_128_; - assign n2678 = PKSi_27_ | PKSi_121_; - assign n2679 = N_N2802 | PKSi_137_; - assign n2680 = PKSi_40_ | N_N2931; - assign n2681 = PKSi_44_ | PKSi_125_; - assign n2682 = PKSi_31_ | PKSi_135_; - assign n2683 = PKSi_52_ | PKSi_166_; - assign n2684 = PKSi_71_ | PKSi_150_; - assign n2685 = PKSi_54_ | PKSi_146_; - assign n2686 = PKSi_63_ | PKSi_167_; - assign n2687 = PKSi_53_ | PKSi_154_; - assign n2688 = PKSi_57_ | PKSi_160_; - assign n2689 = PKSi_67_ | N_N2921; - assign n2690 = PKSi_65_ | PKSi_165_; - assign n2691 = N_N2789 | PKSi_147_; - assign n2692 = PKSi_59_ | N_N2917; - assign n2693 = PKSi_50_ | PKSi_158_; - assign n2694 = PKSi_62_ | PKSi_151_; - assign n2695 = PKSi_70_ | PKSi_144_; - assign n2696 = PKSi_48_ | PKSi_163_; - assign n2697 = PKSi_56_ | PKSi_153_; - assign n2698 = PKSi_66_ | PKSi_156_; - assign n2699 = PKSi_49_ | N_N2909; - assign n2700 = N_N2779 | PKSi_162_; - assign n2701 = PKSi_61_ | PKSi_148_; - assign n2702 = PKSi_69_ | PKSi_155_; - assign n2703 = PKSi_58_ | PKSi_157_; - assign n2704 = N_N2774 | PKSi_164_; - assign n2705 = PKSi_60_ | PKSi_152_; - assign n2706 = PKSi_51_ | PKSi_145_; - assign n2707 = N_N2770 | PKSi_161_; - assign n2708 = PKSi_64_ | N_N2899; - assign n2709 = PKSi_68_ | PKSi_149_; - assign n2710 = PKSi_55_ | PKSi_159_; - assign n2711 = PKSi_76_ | PKSi_190_; - assign n2712 = PKSi_95_ | PKSi_174_; - assign n2713 = PKSi_78_ | PKSi_170_; - assign n2714 = PKSi_87_ | \[234] ; - assign n2715 = PKSi_77_ | PKSi_178_; - assign n2716 = PKSi_81_ | PKSi_184_; - assign n2717 = PKSi_91_ | N_N2889; - assign n2718 = PKSi_89_ | PKSi_189_; - assign n2719 = N_N2757 | PKSi_171_; - assign n2720 = PKSi_83_ | N_N2885; - assign n2721 = PKSi_74_ | PKSi_182_; - assign n2722 = PKSi_86_ | PKSi_175_; - assign n2723 = PKSi_94_ | N_N2881; - assign n2724 = PKSi_72_ | N_N2879; - assign n2725 = PKSi_80_ | N_N2877; - assign n2726 = N_N2749 | PKSi_180_; - assign n2727 = PKSi_73_ | PKSi_177_; - assign n2728 = N_N2746 | PKSi_186_; - assign n2729 = PKSi_85_ | PKSi_172_; - assign n2730 = PKSi_93_ | PKSi_179_; - assign n2731 = PKSi_82_ | \[253] ; - assign n2732 = N_N2741 | PKSi_188_; - assign n2733 = PKSi_84_ | PKSi_176_; - assign n2734 = PKSi_75_ | PKSi_169_; - assign n2735 = N_N2737 | PKSi_185_; - assign n2736 = \[333] | N_N2865; - assign n2737 = PKSi_92_ | PKSi_173_; - assign n2738 = PKSi_79_ | PKSi_183_; - assign n2739 = (Pcount_0_ & n2177) | (Pencrypt_0_ & (~Pcount_0_ | n2177)); - assign n2740 = Pcount_0_ | n2177; - assign n2741 = Pcount_1_ | Pcount_2_; - assign PKSi_191_ = \[234] ; - assign PKSi_187_ = \[234] ; - assign PKSi_181_ = \[253] ; - assign PKSi_168_ = \[253] ; - assign PKSi_143_ = \[282] ; - assign PKSi_139_ = \[282] ; - assign PKSi_90_ = \[333] ; - assign PKSi_88_ = \[333] ; - always @ (posedge clock) begin - PKSi_79_ <= n921; - PKSi_92_ <= n925_1; - \[333] <= n929_1; - N_N2737 <= n934_1; - PKSi_75_ <= n939_1; - PKSi_84_ <= n943; - N_N2741 <= n947; - PKSi_82_ <= n952_1; - PKSi_93_ <= n956_1; - PKSi_85_ <= n960_1; - N_N2746 <= n964_1; - PKSi_73_ <= n969; - N_N2749 <= n973; - PKSi_80_ <= n978_1; - PKSi_72_ <= n982_1; - PKSi_94_ <= n986_1; - PKSi_86_ <= n990_1; - PKSi_74_ <= n994_1; - PKSi_83_ <= n998_1; - N_N2757 <= n1002_1; - PKSi_89_ <= n1007; - PKSi_91_ <= n1011; - PKSi_81_ <= n1015; - PKSi_77_ <= n1019; - PKSi_87_ <= n1023; - PKSi_78_ <= n1027; - PKSi_95_ <= n1031; - PKSi_76_ <= n1035; - PKSi_55_ <= n1039; - PKSi_68_ <= n1043; - PKSi_64_ <= n1047; - N_N2770 <= n1051; - PKSi_51_ <= n1056_1; - PKSi_60_ <= n1060_1; - N_N2774 <= n1064_1; - PKSi_58_ <= n1069; - PKSi_69_ <= n1073; - PKSi_61_ <= n1077; - N_N2779 <= n1081; - PKSi_49_ <= n1086_1; - PKSi_66_ <= n1090_1; - PKSi_56_ <= n1094_1; - PKSi_48_ <= n1098_1; - PKSi_70_ <= n1102_1; - PKSi_62_ <= n1106_1; - PKSi_50_ <= n1110_1; - PKSi_59_ <= n1114_1; - N_N2789 <= n1118_1; - PKSi_65_ <= n1123; - PKSi_67_ <= n1127; - PKSi_57_ <= n1131; - PKSi_53_ <= n1135; - PKSi_63_ <= n1139; - PKSi_54_ <= n1143; - PKSi_71_ <= n1147; - PKSi_52_ <= n1151; - PKSi_31_ <= n1155; - PKSi_44_ <= n1159; - PKSi_40_ <= n1163; - N_N2802 <= n1167_1; - PKSi_27_ <= n1172; - PKSi_36_ <= n1176; - N_N2806 <= n1180; - PKSi_34_ <= n1185; - PKSi_45_ <= n1189; - PKSi_37_ <= n1193; - N_N2811 <= n1197; - PKSi_25_ <= n1202; - PKSi_42_ <= n1206; - PKSi_32_ <= n1210; - PKSi_24_ <= n1214; - PKSi_46_ <= n1218; - PKSi_38_ <= n1222; - PKSi_26_ <= n1226; - PKSi_35_ <= n1230; - N_N2821 <= n1234; - PKSi_41_ <= n1239; - PKSi_43_ <= n1243; - PKSi_33_ <= n1247; - PKSi_29_ <= n1251; - PKSi_39_ <= n1255; - PKSi_30_ <= n1259; - PKSi_47_ <= n1263; - PKSi_28_ <= n1267; - PKSi_7_ <= n1271; - PKSi_20_ <= n1275; - PKSi_16_ <= n1279; - N_N2834 <= n1283; - PKSi_3_ <= n1288; - PKSi_12_ <= n1292_1; - N_N2838 <= n1296_1; - PKSi_10_ <= n1301_1; - PKSi_21_ <= n1305_1; - PKSi_13_ <= n1309_1; - N_N2843 <= n1313_1; - PKSi_1_ <= n1318_1; - PKSi_18_ <= n1322_1; - PKSi_8_ <= n1326_1; - PKSi_0_ <= n1330_1; - PKSi_22_ <= n1334_1; - PKSi_14_ <= n1338_1; - PKSi_2_ <= n1342_1; - PKSi_11_ <= n1346_1; - N_N2853 <= n1350_1; - PKSi_17_ <= n1355_1; - PKSi_19_ <= n1359_1; - PKSi_9_ <= n1363_1; - PKSi_5_ <= n1367_1; - PKSi_15_ <= n1371_1; - PKSi_6_ <= n1375_1; - PKSi_23_ <= n1379_1; - PKSi_4_ <= n1383_1; - PKSi_183_ <= n1387_1; - PKSi_173_ <= n1391_1; - N_N2865 <= n1395_1; - PKSi_185_ <= n1400_1; - PKSi_169_ <= n1404_1; - PKSi_176_ <= n1408_1; - PKSi_188_ <= n1412_1; - \[253] <= n1416_1; - PKSi_179_ <= n1421_1; - PKSi_172_ <= n1425_1; - PKSi_186_ <= n1429_1; - PKSi_177_ <= n1433_1; - PKSi_180_ <= n1437_1; - N_N2877 <= n1441_1; - N_N2879 <= n1446_1; - N_N2881 <= n1451_1; - PKSi_175_ <= n1456_1; - PKSi_182_ <= n1460_1; - N_N2885 <= n1464_1; - PKSi_171_ <= n1469_1; - PKSi_189_ <= n1473_1; - N_N2889 <= n1477_1; - PKSi_184_ <= n1482_1; - PKSi_178_ <= n1486_1; - \[234] <= n1490_1; - PKSi_170_ <= n1495_1; - PKSi_174_ <= n1499_1; - PKSi_190_ <= n1503_1; - PKSi_159_ <= n1507_1; - PKSi_149_ <= n1511_1; - N_N2899 <= n1515; - PKSi_161_ <= n1520_1; - PKSi_145_ <= n1524_1; - PKSi_152_ <= n1528_1; - PKSi_164_ <= n1532_1; - PKSi_157_ <= n1536_1; - PKSi_155_ <= n1540_1; - PKSi_148_ <= n1544_1; - PKSi_162_ <= n1548_1; - N_N2909 <= n1552_1; - PKSi_156_ <= n1557_1; - PKSi_153_ <= n1561_1; - PKSi_163_ <= n1565_1; - PKSi_144_ <= n1569_1; - PKSi_151_ <= n1573_1; - PKSi_158_ <= n1577_1; - N_N2917 <= n1581_1; - PKSi_147_ <= n1586_1; - PKSi_165_ <= n1590_1; - N_N2921 <= n1594_1; - PKSi_160_ <= n1599_1; - PKSi_154_ <= n1603_1; - PKSi_167_ <= n1607_1; - PKSi_146_ <= n1611_1; - PKSi_150_ <= n1615_1; - PKSi_166_ <= n1619_1; - PKSi_135_ <= n1623_1; - PKSi_125_ <= n1627_1; - N_N2931 <= n1631_1; - PKSi_137_ <= n1636_1; - PKSi_121_ <= n1640_1; - PKSi_128_ <= n1644_1; - PKSi_140_ <= n1648_1; - PKSi_133_ <= n1652_1; - PKSi_131_ <= n1656_1; - PKSi_124_ <= n1660_1; - PKSi_138_ <= n1664_1; - PKSi_129_ <= n1668_1; - PKSi_132_ <= n1672_1; - N_N2943 <= n1676_1; - N_N2945 <= n1681_1; - PKSi_120_ <= n1686_1; - PKSi_127_ <= n1690_1; - PKSi_134_ <= n1694_1; - N_N2950 <= n1698_1; - PKSi_123_ <= n1703_1; - PKSi_141_ <= n1707_1; - N_N2954 <= n1711_1; - PKSi_136_ <= n1716_1; - PKSi_130_ <= n1720_1; - \[282] <= n1724_1; - PKSi_122_ <= n1729_1; - PKSi_126_ <= n1733_1; - PKSi_142_ <= n1737_1; - PKSi_111_ <= n1741_1; - PKSi_101_ <= n1745; - N_N2964 <= n1749; - PKSi_113_ <= n1754_1; - PKSi_97_ <= n1758_1; - PKSi_104_ <= n1762_1; - PKSi_116_ <= n1766_1; - PKSi_109_ <= n1770_1; - PKSi_107_ <= n1774_1; - PKSi_100_ <= n1778_1; - PKSi_114_ <= n1782_1; - PKSi_105_ <= n1786_1; - PKSi_108_ <= n1790_1; - N_N2976 <= n1794_1; - PKSi_115_ <= n1799; - PKSi_96_ <= n1803; - PKSi_103_ <= n1807; - PKSi_110_ <= n1811; - N_N2982 <= n1815; - PKSi_99_ <= n1820_1; - PKSi_117_ <= n1824_1; - N_N2986 <= n1828_1; - PKSi_112_ <= n1833; - PKSi_106_ <= n1837; - PKSi_119_ <= n1841; - PKSi_98_ <= n1845; - PKSi_102_ <= n1849; - PKSi_118_ <= n1853; - end -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/clma/clma.v b/fpga_flow/benchmarks/Verilog/MCNC/clma/clma.v deleted file mode 100644 index c73b12461..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/clma/clma.v +++ /dev/null @@ -1,4776 +0,0 @@ -// Benchmark "TOP" written by ABC on Tue Mar 5 09:55:52 2019 - -module clma ( clock, - Pi416, Pi415, Pi414, Pi413, Pi412, Pi411, Pi410, Pi409, Pi408, Pi407, - Pi406, Pi405, Pi404, Pi403, Pi402, Pi401, Pi400, Pi399, Pi398, Pi397, - Pi396, Pi395, Pi394, Pi393, Pi392, Pi391, Pi390, Pi389, Pi388, Pi387, - Pi386, Pi385, Pi384, Pi383, Pi382, Pi381, Pi380, Pi379, Pi378, Pi377, - Pi376, Pi375, Pi374, Pi373, Pi372, Pi371, Pi370, Pi369, Pi368, Pi367, - Pi366, Pi365, Pi364, Pi363, Pi362, Pi361, Pi360, Pi359, Pi358, Pi357, - Pi356, Pi355, Pi354, Pi353, Pi352, Pi351, Pi350, Pi349, Pi348, Pi347, - Pi346, Pi345, Pi344, Pi343, Pi342, Pi341, Pi340, Pi339, Pi338, Pi337, - Pi336, Pi335, Pi334, Pi333, Pi332, Pi331, Pi330, Pi329, Pi328, Pi327, - Pi326, Pi325, Pi324, Pi323, Pi322, Pi321, Pi320, Pi319, Pi318, Pi317, - Pi316, Pi315, Pi314, Pi313, Pi312, Pi311, Pi310, Pi309, Pi308, Pi307, - Pi306, Pi305, Pi304, Pi303, Pi302, Pi301, Pi300, Pi299, Pi298, Pi297, - Pi296, Pi295, Pi294, Pi293, Pi292, Pi291, Pi290, Pi289, Pi288, Pi287, - Pi286, Pi285, Pi284, Pi283, Pi282, Pi281, Pi280, Pi279, Pi278, Pi277, - Pi276, Pi275, Pi274, Pi273, Pi272, Pi271, Pi270, Pi269, Pi268, Pi267, - Pi266, Pi265, Pi264, Pi263, Pi262, Pi261, Pi260, Pi259, Pi258, Pi257, - Pi256, Pi255, Pi254, Pi253, Pi252, Pi251, Pi250, Pi249, Pi248, Pi247, - Pi246, Pi245, Pi244, Pi243, Pi242, Pi241, Pi240, Pi239, Pi238, Pi237, - Pi236, Pi235, Pi234, Pi233, Pi232, Pi231, Pi230, Pi229, Pi228, Pi227, - Pi226, Pi225, Pi224, Pi223, Pi222, Pi221, Pi220, Pi219, Pi218, Pi217, - Pi216, Pi215, Pi214, Pi213, Pi212, Pi211, Pi210, Pi209, Pi208, Pi207, - Pi206, Pi205, Pi204, Pi203, Pi202, Pi201, Pi200, Pi199, Pi198, Pi197, - Pi196, Pi195, Pi194, Pi193, Pi192, Pi191, Pi190, Pi189, Pi188, Pi187, - Pi186, Pi185, Pi184, Pi183, Pi182, Pi181, Pi180, Pi179, Pi178, Pi177, - Pi176, Pi175, Pi174, Pi173, Pi172, Pi171, Pi170, Pi169, Pi168, Pi167, - Pi166, Pi165, Pi164, Pi163, Pi162, Pi161, Pi160, Pi159, Pi158, Pi157, - Pi156, Pi155, Pi154, Pi153, Pi152, Pi151, Pi150, Pi149, Pi148, Pi147, - Pi146, Pi145, Pi144, Pi143, Pi142, Pi141, Pi140, Pi139, Pi138, Pi137, - Pi136, Pi135, Pi134, Pi133, Pi132, Pi131, Pi130, Pi129, Pi128, Pi127, - Pi126, Pi125, Pi124, Pi123, Pi122, Pi121, Pi120, Pi119, Pi118, Pi117, - Pi116, Pi115, Pi114, Pi113, Pi112, Pi111, Pi110, Pi109, Pi108, Pi107, - Pi106, Pi105, Pi104, Pi103, Pi102, Pi101, Pi100, Pi99, Pi98, Pi97, - Pi96, Pi95, Pi94, Pi93, Pi92, Pi91, Pi90, Pi89, Pi88, Pi87, Pi86, Pi85, - Pi84, Pi83, Pi82, Pi81, Pi80, Pi79, Pi78, Pi77, Pi76, Pi75, Pi74, Pi73, - Pi72, Pi71, Pi70, Pi69, Pi68, Pi67, Pi66, Pi65, Pi64, Pi63, Pi62, Pi61, - Pi60, Pi59, Pi58, Pi57, Pi56, Pi55, Pi54, Pi53, Pi52, Pi51, Pi50, Pi49, - Pi28, Pi27, Pi26, Pi25, Pi24, Pi23, Pi22, Pi21, Pi20, Pi19, Pi18, Pi17, - Pi16, Pi15, - P__cmxir_1, P__cmxir_0, P__cmxig_1, P__cmxig_0, P__cmxcl_1, P__cmxcl_0, - P__cmx1ad_35, P__cmx1ad_34, P__cmx1ad_33, P__cmx1ad_32, P__cmx1ad_31, - P__cmx1ad_30, P__cmx1ad_29, P__cmx1ad_28, P__cmx1ad_27, P__cmx1ad_26, - P__cmx1ad_25, P__cmx1ad_24, P__cmx1ad_23, P__cmx1ad_22, P__cmx1ad_21, - P__cmx1ad_20, P__cmx1ad_19, P__cmx1ad_18, P__cmx1ad_17, P__cmx1ad_16, - P__cmx1ad_15, P__cmx1ad_14, P__cmx1ad_13, P__cmx1ad_12, P__cmx1ad_11, - P__cmx1ad_10, P__cmx1ad_9, P__cmx1ad_8, P__cmx1ad_7, P__cmx1ad_6, - P__cmx1ad_5, P__cmx1ad_4, P__cmx1ad_3, P__cmx1ad_2, P__cmx1ad_1, - P__cmx1ad_0, P__cmx0ad_35, P__cmx0ad_34, P__cmx0ad_33, P__cmx0ad_32, - P__cmx0ad_31, P__cmx0ad_30, P__cmx0ad_29, P__cmx0ad_28, P__cmx0ad_27, - P__cmx0ad_26, P__cmx0ad_25, P__cmx0ad_24, P__cmx0ad_23, P__cmx0ad_22, - P__cmx0ad_21, P__cmx0ad_20, P__cmx0ad_19, P__cmx0ad_18, P__cmx0ad_17, - P__cmx0ad_16, P__cmx0ad_15, P__cmx0ad_14, P__cmx0ad_13, P__cmx0ad_12, - P__cmx0ad_11, P__cmx0ad_10, P__cmx0ad_9, P__cmx0ad_8, P__cmx0ad_7, - P__cmx0ad_6, P__cmx0ad_5, P__cmx0ad_4, P__cmx0ad_3, P__cmx0ad_2, - P__cmx0ad_1, P__cmx0ad_0, P__cmnxcp_1, P__cmnxcp_0, P__cmndst1p0, - P__cmndst0p0 ); - input Pi416, Pi415, Pi414, Pi413, Pi412, Pi411, Pi410, Pi409, Pi408, - Pi407, Pi406, Pi405, Pi404, Pi403, Pi402, Pi401, Pi400, Pi399, Pi398, - Pi397, Pi396, Pi395, Pi394, Pi393, Pi392, Pi391, Pi390, Pi389, Pi388, - Pi387, Pi386, Pi385, Pi384, Pi383, Pi382, Pi381, Pi380, Pi379, Pi378, - Pi377, Pi376, Pi375, Pi374, Pi373, Pi372, Pi371, Pi370, Pi369, Pi368, - Pi367, Pi366, Pi365, Pi364, Pi363, Pi362, Pi361, Pi360, Pi359, Pi358, - Pi357, Pi356, Pi355, Pi354, Pi353, Pi352, Pi351, Pi350, Pi349, Pi348, - Pi347, Pi346, Pi345, Pi344, Pi343, Pi342, Pi341, Pi340, Pi339, Pi338, - Pi337, Pi336, Pi335, Pi334, Pi333, Pi332, Pi331, Pi330, Pi329, Pi328, - Pi327, Pi326, Pi325, Pi324, Pi323, Pi322, Pi321, Pi320, Pi319, Pi318, - Pi317, Pi316, Pi315, Pi314, Pi313, Pi312, Pi311, Pi310, Pi309, Pi308, - Pi307, Pi306, Pi305, Pi304, Pi303, Pi302, Pi301, Pi300, Pi299, Pi298, - Pi297, Pi296, Pi295, Pi294, Pi293, Pi292, Pi291, Pi290, Pi289, Pi288, - Pi287, Pi286, Pi285, Pi284, Pi283, Pi282, Pi281, Pi280, Pi279, Pi278, - Pi277, Pi276, Pi275, Pi274, Pi273, Pi272, Pi271, Pi270, Pi269, Pi268, - Pi267, Pi266, Pi265, Pi264, Pi263, Pi262, Pi261, Pi260, Pi259, Pi258, - Pi257, Pi256, Pi255, Pi254, Pi253, Pi252, Pi251, Pi250, Pi249, Pi248, - Pi247, Pi246, Pi245, Pi244, Pi243, Pi242, Pi241, Pi240, Pi239, Pi238, - Pi237, Pi236, Pi235, Pi234, Pi233, Pi232, Pi231, Pi230, Pi229, Pi228, - Pi227, Pi226, Pi225, Pi224, Pi223, Pi222, Pi221, Pi220, Pi219, Pi218, - Pi217, Pi216, Pi215, Pi214, Pi213, Pi212, Pi211, Pi210, Pi209, Pi208, - Pi207, Pi206, Pi205, Pi204, Pi203, Pi202, Pi201, Pi200, Pi199, Pi198, - Pi197, Pi196, Pi195, Pi194, Pi193, Pi192, Pi191, Pi190, Pi189, Pi188, - Pi187, Pi186, Pi185, Pi184, Pi183, Pi182, Pi181, Pi180, Pi179, Pi178, - Pi177, Pi176, Pi175, Pi174, Pi173, Pi172, Pi171, Pi170, Pi169, Pi168, - Pi167, Pi166, Pi165, Pi164, Pi163, Pi162, Pi161, Pi160, Pi159, Pi158, - Pi157, Pi156, Pi155, Pi154, Pi153, Pi152, Pi151, Pi150, Pi149, Pi148, - Pi147, Pi146, Pi145, Pi144, Pi143, Pi142, Pi141, Pi140, Pi139, Pi138, - Pi137, Pi136, Pi135, Pi134, Pi133, Pi132, Pi131, Pi130, Pi129, Pi128, - Pi127, Pi126, Pi125, Pi124, Pi123, Pi122, Pi121, Pi120, Pi119, Pi118, - Pi117, Pi116, Pi115, Pi114, Pi113, Pi112, Pi111, Pi110, Pi109, Pi108, - Pi107, Pi106, Pi105, Pi104, Pi103, Pi102, Pi101, Pi100, Pi99, Pi98, - Pi97, Pi96, Pi95, Pi94, Pi93, Pi92, Pi91, Pi90, Pi89, Pi88, Pi87, Pi86, - Pi85, Pi84, Pi83, Pi82, Pi81, Pi80, Pi79, Pi78, Pi77, Pi76, Pi75, Pi74, - Pi73, Pi72, Pi71, Pi70, Pi69, Pi68, Pi67, Pi66, Pi65, Pi64, Pi63, Pi62, - Pi61, Pi60, Pi59, Pi58, Pi57, Pi56, Pi55, Pi54, Pi53, Pi52, Pi51, Pi50, - Pi49, Pi28, Pi27, Pi26, Pi25, Pi24, Pi23, Pi22, Pi21, Pi20, Pi19, Pi18, - Pi17, Pi16, Pi15, clock; - output P__cmxir_1, P__cmxir_0, P__cmxig_1, P__cmxig_0, P__cmxcl_1, - P__cmxcl_0, P__cmx1ad_35, P__cmx1ad_34, P__cmx1ad_33, P__cmx1ad_32, - P__cmx1ad_31, P__cmx1ad_30, P__cmx1ad_29, P__cmx1ad_28, P__cmx1ad_27, - P__cmx1ad_26, P__cmx1ad_25, P__cmx1ad_24, P__cmx1ad_23, P__cmx1ad_22, - P__cmx1ad_21, P__cmx1ad_20, P__cmx1ad_19, P__cmx1ad_18, P__cmx1ad_17, - P__cmx1ad_16, P__cmx1ad_15, P__cmx1ad_14, P__cmx1ad_13, P__cmx1ad_12, - P__cmx1ad_11, P__cmx1ad_10, P__cmx1ad_9, P__cmx1ad_8, P__cmx1ad_7, - P__cmx1ad_6, P__cmx1ad_5, P__cmx1ad_4, P__cmx1ad_3, P__cmx1ad_2, - P__cmx1ad_1, P__cmx1ad_0, P__cmx0ad_35, P__cmx0ad_34, P__cmx0ad_33, - P__cmx0ad_32, P__cmx0ad_31, P__cmx0ad_30, P__cmx0ad_29, P__cmx0ad_28, - P__cmx0ad_27, P__cmx0ad_26, P__cmx0ad_25, P__cmx0ad_24, P__cmx0ad_23, - P__cmx0ad_22, P__cmx0ad_21, P__cmx0ad_20, P__cmx0ad_19, P__cmx0ad_18, - P__cmx0ad_17, P__cmx0ad_16, P__cmx0ad_15, P__cmx0ad_14, P__cmx0ad_13, - P__cmx0ad_12, P__cmx0ad_11, P__cmx0ad_10, P__cmx0ad_9, P__cmx0ad_8, - P__cmx0ad_7, P__cmx0ad_6, P__cmx0ad_5, P__cmx0ad_4, P__cmx0ad_3, - P__cmx0ad_2, P__cmx0ad_1, P__cmx0ad_0, P__cmnxcp_1, P__cmnxcp_0, - P__cmndst1p0, P__cmndst0p0; - reg Ni48, Ni47, Ni46, Ni45, Ni44, Ni43, Ni42, Ni41, Ni40, Ni39, Ni38, - Ni37, Ni36, Ni35, Ni34, Ni33, Ni32, Ni31, Ni30, n18, Ni14, Ni13, Ni12, - Ni11, Ni10, Ni9, Ni8, Ni7, Ni6, Ni5, Ni4, Ni3, Ni2; - wire n646, n648, n649, n651, n653, n654, n655, n656, n658, n660, n662, - n663, n664, n665, n666, n668, n670, n672, n674, n675, n676, n677, n678, - n679, n681, n683, n684, n686, n688, n689, n690, n691, n692, n693, n694, - n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, - n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, - n719, n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, - n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, - n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, - n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, - n767, n768, n770, n772, n773, n774, n776, n778, n780, n781, n783, n784, - n785, n786, n787, n788, n789, n790, n792, n793, n794, n795, n796, n797, - n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, - n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, - n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, - n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, - n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, - n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, - n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, n881, - n882, n883, n884, n885, n886, n887, n888, n889, n890, n891, n892, n893, - n894, n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, - n906, n907, n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, - n918, n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, - n930, n931, n932, n933, n934, n935, n936_1, n937, n938, n939, n940, - n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, - n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, - n965, n966, n967, n968, n969, n970, n971_1, n972, n973, n974, n975, - n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986_1, - n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, - n999, n1000, n1001_1, n1002, n1003, n1004, n1005, n1006, n1007, n1008, - n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, - n1019, n1020, n1021_1, n1022, n1023, n1024, n1025, n1026, n1027, n1028, - n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036_1, n1037, n1038, - n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, - n1049, n1050, n1051_1, n1052, n1053, n1054, n1055, n1056, n1057, n1058, - n1059, n1060, n1061_1, n1062, n1063, n1064, n1065, n1066, n1067, n1068, - n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076_1, n1077, n1078, - n1079, n1080, n1081_1, n1082, n1083, n1084, n1085_1, n1086, n1087, - n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, - n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, - n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, - n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, - n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, - n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, - n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, - n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, - n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, - n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, - n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, - n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, - n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, - n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, - n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, - n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, - n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, - n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, - n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, - n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, - n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, - n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, - n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, - n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, - n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, - n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, - n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, - n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, - n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, - n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, - n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, - n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, - n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, - n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, - n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, - n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, - n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, - n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, - n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, - n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, - n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, - n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, - n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, - n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, - n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, - n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, - n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, - n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, - n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, - n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, - n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, - n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, - n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, - n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, - n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, - n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, - n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, - n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, - n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, - n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, - n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, - n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, - n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, - n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, - n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, - n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, - n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, - n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, - n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, - n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, - n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, - n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, - n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, - n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, - n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, - n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, - n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, - n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, - n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, - n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, - n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, - n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, - n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, - n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, - n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, - n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, - n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, - n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, - n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, - n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, - n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, - n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, - n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, - n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, - n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, - n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, - n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, - n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, - n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, - n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, - n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, - n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, - n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, - n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, - n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, - n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, - n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, - n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, - n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, - n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, - n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, - n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, - n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, - n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, - n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, - n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, - n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, - n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, - n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, - n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, - n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, - n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, - n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, - n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, - n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, - n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, - n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, - n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, - n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, - n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, - n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, - n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, - n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, - n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, - n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, - n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, - n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, - n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, - n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, - n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, - n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, - n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, - n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, - n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, - n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, - n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, - n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, - n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, - n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, - n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, - n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, - n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, - n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, - n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, - n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, - n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, - n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, - n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, - n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, - n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, - n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, - n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, - n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, - n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, - n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, - n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, - n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, - n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, - n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, - n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, - n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, - n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, - n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, - n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, - n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, - n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, - n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, - n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, - n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, - n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, - n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, - n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, - n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, - n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, - n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, - n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, - n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, - n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, - n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, - n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, - n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, - n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, - n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, - n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, - n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, - n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, - n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, - n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, - n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, - n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, - n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, - n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, - n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, - n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, - n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, - n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, - n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, - n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, - n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, - n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, - n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, - n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, - n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, - n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, - n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, - n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, - n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, - n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, - n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, - n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, - n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, - n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, - n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, - n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, - n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, - n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, - n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357, - n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367, - n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377, - n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387, - n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397, - n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407, - n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417, - n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427, - n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437, - n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, - n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, - n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, - n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, - n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, - n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, - n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507, - n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3517, - n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525, n3526, n3527, - n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535, n3536, n3537, - n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545, n3546, n3547, - n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555, n3556, n3557, - n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565, n3566, n3567, - n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575, n3576, n3577, - n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585, n3586, n3587, - n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597, - n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607, - n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615, n3616, n3617, - n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625, n3626, n3627, - n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635, n3636, n3637, - n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645, n3646, n3647, - n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655, n3656, n3657, - n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665, n3666, n3667, - n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675, n3676, n3677, - n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685, n3686, n3687, - n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695, n3696, n3697, - n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705, n3706, n3707, - n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715, n3716, n3717, - n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725, n3726, n3727, - n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735, n3736, n3737, - n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745, n3746, n3747, - n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755, n3756, n3757, - n3758, n3760, n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, - n3769, n3770, n3771, n3772, n3773, n3775, n3777, n3779, n3780, n3781, - n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, - n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, - n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, - n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, - n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, - n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, - n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, - n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, - n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, - n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, - n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, - n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, - n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, - n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, - n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, - n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, - n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, - n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, - n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, - n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, - n3983, n3984, n3985, n3986, n3987, n3989, n3990, n3991, n3992, n3993, - n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, - n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, - n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, - n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, - n4034, n4035, n4037, n4038, n4039, n4040, n4042, n4044, n4045, n4046, - n4048, n4050, n4051, n4052, n4053, n4054, n4055, n4056, n4057, n4058, - n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066, n4067, n4068, - n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076, n4077, n4078, - n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086, n4087, n4088, - n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096, n4097, n4098, - n4099, n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107, n4108, - n4109, n4110, n4111, n4112, n4113, n4114, n4115, n4116, n4117, n4118, - n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4127, n4128, - n4129, n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137, n4138, - n4139, n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147, n4148, - n4149, n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157, n4158, - n4159, n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167, n4168, - n4169, n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177, n4178, - n4179, n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187, n4188, - n4189, n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197, n4198, - n4199, n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207, n4208, - n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217, n4218, - n4219, n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227, n4228, - n4229, n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237, n4238, - n4239, n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247, n4248, - n4249, n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257, n4258, - n4259, n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4268, - n4269, n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278, - n4279, n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4287, n4288, - n4289, n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298, - n4299, n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308, - n4309, n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318, - n4319, n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328, - n4329, n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338, - n4339, n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347, n4348, - n4349, n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358, - n4359, n4360, n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368, - n4369, n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378, - n4379, n4380, n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388, - n4389, n4390, n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398, - n4399, n4400, n4401, n4402, n4403, n4404, n4405, n4406, n4407, n4408, - n4409, n4410, n4411, n4412, n4413, n4414, n4415, n4416, n4417, n4418, - n4419, n4420, n4421, n4422, n4423, n4424, n4425, n4426, n4427, n4428, - n4429, n4430, n4431, n4432, n4433, n4434, n4435, n4436, n4437, n4438, - n4439, n4440, n4441, n4442, n4443, n4444, n4445, n4446, n4447, n4448, - n4449, n4450, n4451, n4452, n4453, n4454, n4455, n4456, n4457, n4458, - n4459, n4460, n4461, n4462, n4463, n4464, n4465, n4466, n4467, n4468, - n4469, n4470, n4471, n4472, n4473, n4474, n4475, n4476, n4477, n4478, - n4479, n4480, n4481, n4482, n4483, n4484, n4485, n4486, n4487, n4488, - n4489, n4490, n4491, n4492, n4493, n4494, n4495, n4496, n4497, n4498, - n4499, n4500, n4501, n4502, n4503, n4504, n4505, n4506, n4507, n4508, - n4509, n4510, n4511, n4512, n4513, n4514, n4515, n4516, n4517, n4518, - n4519, n4520, n4521, n4522, n4523, n4524, n4525, n4526, n4527, n4528, - n4529, n4530, n4531, n4532, n4533, n4534, n4535, n4536, n4537, n4538, - n4539, n4540, n4541, n4542, n4543, n4544, n4545, n4546, n4547, n4548, - n4549, n4550, n4551, n4552, n4553, n4554, n4555, n4556, n4557, n4558, - n4559, n4560, n4561, n4562, n4563, n4564, n4565, n4566, n4567, n4568, - n4569, n4570, n4571, n4572, n4573, n4574, n4575, n4576, n4577, n4578, - n4579, n4580, n4581, n4582, n4583, n4584, n4585, n4586, n4587, n4588, - n4589, n4590, n4591, n4592, n4593, n4594, n4595, n4596, n4597, n4598, - n4599, n4600, n4601, n4602, n4603, n4604, n4605, n4606, n4607, n4608, - n4609, n4610, n4611, n4612, n4613, n4614, n4615, n4616, n4617, n4618, - n4619, n4620, n4621, n4622, n4623, n4624, n4625, n4626, n4627, n4628, - n4629, n4630, n4631, n4632, n4633, n4634, n4635, n4636, n4637, n4638, - n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4646, n4647, n4648, - n4649, n4650, n4651, n4652, n4653, n4654, n4655, n4656, n4657, n4658, - n4659, n4660, n4661, n4662, n4663, n4664, n4665, n4666, n4667, n4668, - n4669, n4670, n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678, - n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4686, n4687, n4688, - n4689, n4690, n4691, n4692, n4693, n4694, n4695, n4696, n4697, n4698, - n4699, n4700, n4701, n4702, n4703, n4704, n4705, n4706, n4707, n4708, - n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716, n4717, n4718, - n4719, n4720, n4721, n4722, n4723, n4724, n4725, n4726, n4727, n4728, - n4729, n4730, n4731, n4732, n4733, n4734, n4735, n4736, n4737, n4738, - n4739, n4740, n4741, n4742, n4743, n4744, n4745, n4746, n4747, n4748, - n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756, n4757, n4758, - n4759, n4760, n4761, n4762, n4763, n4764, n4765, n4766, n4767, n4768, - n4769, n4770, n4771, n4772, n4773, n4774, n4775, n931_1, n936, n941_1, - n946_1, n951_1, n956_1, n961_1, n966_1, n971, n976_1, n981_1, n986, - n991_1, n996_1, n1001, n1006_1, n1011_1, n1016_1, n1021, n1026_1, - n1031_1, n1036, n1041_1, n1046_1, n1051, n1056_1, n1061, n1066_1, - n1071_1, n1076, n1081, n1085, n1090_1; - assign P__cmxir_1 = n785 & ~n3327 & ~n3707; - assign P__cmxir_0 = ~n773 & ~n3659; - assign P__cmxig_1 = ~n785; - assign P__cmxig_0 = ~n3950; - assign P__cmxcl_1 = ~n3707; - assign P__cmxcl_0 = ~n3707; - assign P__cmx1ad_35 = 1'b0; - assign P__cmx1ad_34 = 1'b0; - assign P__cmx1ad_33 = 1'b0; - assign P__cmx1ad_32 = 1'b0; - assign P__cmx1ad_31 = Pi255 & ~n3985; - assign P__cmx1ad_30 = Pi254 & ~n3985; - assign P__cmx1ad_29 = Pi253 & ~n3985; - assign P__cmx1ad_28 = Pi252 & ~n3985; - assign P__cmx1ad_27 = Pi251 & ~n3985; - assign P__cmx1ad_26 = Pi250 & ~n3985; - assign P__cmx1ad_25 = Pi249 & ~n3985; - assign P__cmx1ad_24 = Pi248 & ~n3985; - assign P__cmx1ad_23 = Pi247 & ~n3985; - assign P__cmx1ad_22 = Pi246 & ~n3985; - assign P__cmx1ad_21 = Pi245 & ~n3985; - assign P__cmx1ad_20 = Pi244 & ~n3985; - assign P__cmx1ad_19 = Pi243 & ~n3985; - assign P__cmx1ad_18 = Pi242 & ~n3985; - assign P__cmx1ad_17 = Pi241 & ~n3985; - assign P__cmx1ad_16 = Pi240 & ~n3985; - assign P__cmx1ad_15 = ~n3985 & Pi27 & Pi26; - assign P__cmx1ad_14 = ~n4051; - assign P__cmx1ad_13 = n789 & ~n3985; - assign P__cmx1ad_12 = ~n4760; - assign P__cmx1ad_11 = 1'b0; - assign P__cmx1ad_10 = 1'b0; - assign P__cmx1ad_9 = ~n3985; - assign P__cmx1ad_8 = 1'b0; - assign P__cmx1ad_7 = Pi239 & ~n3985; - assign P__cmx1ad_6 = Pi238 & ~n3985; - assign P__cmx1ad_5 = Pi237 & ~n3985; - assign P__cmx1ad_4 = Pi236 & ~n3985; - assign P__cmx1ad_3 = Pi235 & ~n3985; - assign P__cmx1ad_2 = Pi234 & ~n3985; - assign P__cmx1ad_1 = Pi233 & ~n3985; - assign P__cmx1ad_0 = Pi232 & ~n3985; - assign P__cmx0ad_35 = 1'b0; - assign P__cmx0ad_34 = 1'b0; - assign P__cmx0ad_33 = 1'b0; - assign P__cmx0ad_32 = 1'b0; - assign P__cmx0ad_31 = Pi72 & ~n3986; - assign P__cmx0ad_30 = Pi71 & ~n3986; - assign P__cmx0ad_29 = Pi70 & ~n3986; - assign P__cmx0ad_28 = Pi69 & ~n3986; - assign P__cmx0ad_27 = Pi68 & ~n3986; - assign P__cmx0ad_26 = Pi67 & ~n3986; - assign P__cmx0ad_25 = Pi66 & ~n3986; - assign P__cmx0ad_24 = Pi65 & ~n3986; - assign P__cmx0ad_23 = Pi64 & ~n3986; - assign P__cmx0ad_22 = Pi63 & ~n3986; - assign P__cmx0ad_21 = Pi62 & ~n3986; - assign P__cmx0ad_20 = Pi61 & ~n3986; - assign P__cmx0ad_19 = Pi60 & ~n3986; - assign P__cmx0ad_18 = Pi59 & ~n3986; - assign P__cmx0ad_17 = Pi58 & ~n3986; - assign P__cmx0ad_16 = Pi57 & ~n3986; - assign P__cmx0ad_15 = ~n3986 & Pi24 & Pi23; - assign P__cmx0ad_14 = ~n4052; - assign P__cmx0ad_13 = n788 & ~n3986; - assign P__cmx0ad_12 = ~n4762; - assign P__cmx0ad_11 = 1'b0; - assign P__cmx0ad_10 = 1'b0; - assign P__cmx0ad_9 = ~n3986; - assign P__cmx0ad_8 = 1'b0; - assign P__cmx0ad_7 = Pi56 & ~n3986; - assign P__cmx0ad_6 = Pi55 & ~n3986; - assign P__cmx0ad_5 = Pi54 & ~n3986; - assign P__cmx0ad_4 = Pi53 & ~n3986; - assign P__cmx0ad_3 = Pi52 & ~n3986; - assign P__cmx0ad_2 = Pi51 & ~n3986; - assign P__cmx0ad_1 = Pi50 & ~n3986; - assign P__cmx0ad_0 = Pi49 & ~n3986; - assign P__cmnxcp_1 = ~n787; - assign P__cmnxcp_0 = ~n786; - assign P__cmndst1p0 = n784 & ~n3754; - assign P__cmndst0p0 = n783 & ~n3984; - assign n646 = ~n3662 & (~Ni48 | (~Pi22 & n3663)); - assign n931_1 = ~n646; - assign n648 = ~n904 & n3185 & (Pi20 | n3186); - assign n649 = Ni46 & (Pi21 | (~Ni32 & ~n2416)); - assign n941_1 = n648 | n649; - assign n651 = ~n3829 & (~Ni44 | ~n3751); - assign n951_1 = ~n651; - assign n653 = Ni44 ^ ~Ni39; - assign n654 = n653 & Ni38; - assign n655 = n653 & Ni32 & (Ni37 | n654); - assign n656 = n3190 & (n2398 | ~Ni41); - assign n966_1 = ~n656; - assign n658 = n3188 & (n2398 | ~Ni40); - assign n971 = ~n658; - assign n660 = n2391 & (n665 | ~Ni39); - assign n976_1 = ~n660; - assign n662 = ~n3183 & (~n1241 | ~n2389) & ~n3864; - assign n663 = ~n1322 & ~n3183 & (n808 | ~n995); - assign n664 = Pi15 & ~n741 & ~n3984; - assign n665 = ~Ni32 & n2406; - assign n666 = ~n3984 & ~n3183 & n3184; - assign n981_1 = ~n4774 | n665 | n666 | n664 | n662 | n663; - assign n668 = ~n2404 & (~Ni36 | n2398) & n2405; - assign n991_1 = ~n668; - assign n670 = ~n2396 & n2397 & (~Ni35 | n2398); - assign n996_1 = ~n670; - assign n672 = ~n2388 & ~n3806 & (~Ni34 | ~n3707); - assign n1001 = ~n672; - assign n674 = ~Ni42 & (~Ni44 | ~n738); - assign n675 = ~Ni42 & (Ni44 | ~n738); - assign n676 = ~Ni47 & ~Ni45; - assign n677 = ~Ni42 | Ni43; - assign n678 = n676 & n677; - assign n679 = n3658 & (n3659 | (~n3657 & n3660)); - assign n1006_1 = ~n679; - assign n681 = ~n3181 & n3182 & (~n2073 | ~n4431); - assign n1011_1 = ~n681; - assign n683 = n2078 & (~n678 | ~n814) & ~n3707; - assign n684 = ~n3707 & n2254 & ~Ni32 & ~Ni30; - assign n1016_1 = Ni31 | n683 | n684; - assign n686 = n2076 & n2077 & (~Ni30 | ~n3707); - assign n1021 = ~n686; - assign n688 = n1393 & n1394 & (n689 | n1395); - assign n689 = n4769 & n713; - assign n690 = ~n814 | ~Ni36; - assign n691 = n688 & ~n1539 & (n689 | n690); - assign n692 = n1393 & n1394 & (n693 | n1398); - assign n693 = n4770 & n713; - assign n694 = n692 & ~n1539 & (n690 | n693); - assign n695 = n985 & (n697 | ~Ni38); - assign n696 = ~n1539 & (n744 | ~Ni35); - assign n697 = n713 & (n689 | ~Ni40); - assign n698 = Ni37 | ~Ni36; - assign n699 = n695 & n696 & (n697 | n698); - assign n700 = n985 & (n702 | ~Ni38); - assign n701 = ~n1539 & (n746 | ~Ni35); - assign n702 = n713 & (n693 | ~Ni40); - assign n703 = n700 & n701 & (n702 | n698); - assign n704 = n985 & (n706 | ~Ni38); - assign n705 = ~n1539 & (Ni35 | n748); - assign n706 = n713 & (Ni40 | n689); - assign n707 = n704 & n705 & (n706 | n698); - assign n708 = n985 & (n710 | ~Ni38); - assign n709 = ~n1539 & (Ni35 | n750); - assign n710 = n713 & (Ni40 | n693); - assign n711 = n708 & n709 & (n710 | n698); - assign n712 = n985 & (n713 | ~Ni38); - assign n713 = n738 & (n1351 | ~Ni41); - assign n714 = n712 & ~n1539 & (n698 | n713); - assign n715 = n1393 & n1394 & (n716 | n1395); - assign n716 = n738 & n4769; - assign n717 = n715 & ~n1539 & (n690 | n716); - assign n718 = n1393 & n1394 & (n719 | n1398); - assign n719 = n738 & n4770; - assign n720 = n718 & ~n1539 & (n690 | n719); - assign n721 = n985 & (n723 | ~Ni38); - assign n722 = (~Ni35 | n754) & ~n1539; - assign n723 = n738 & (n716 | ~Ni40); - assign n724 = n721 & n722 & (n723 | n698); - assign n725 = n985 & (n727 | ~Ni38); - assign n726 = (~Ni35 | n756) & ~n1539; - assign n727 = n738 & (n719 | ~Ni40); - assign n728 = n725 & n726 & (n727 | n698); - assign n729 = n985 & (n731 | ~Ni38); - assign n730 = ~n1539 & (Ni35 | n758); - assign n731 = n738 & (Ni40 | n716); - assign n732 = n729 & n730 & (n731 | n698); - assign n733 = n985 & (n735 | ~Ni38); - assign n734 = ~n1539 & (Ni35 | n760); - assign n735 = n738 & (Ni40 | n719); - assign n736 = n733 & n734 & (n735 | n698); - assign n737 = n985 & (n738 | ~Ni38); - assign n738 = n676 & ~Ni43; - assign n739 = n737 & ~n1539 & (n698 | n738); - assign n740 = n985 & ~n1539; - assign n741 = ~Ni36 | ~Ni38; - assign n742 = n688 & n740 & (n689 | n741); - assign n743 = n692 & n740 & (n693 | n741); - assign n744 = n697 | n817; - assign n745 = n695 & ~n1539 & (n744 | ~Ni35); - assign n746 = n702 | n853; - assign n747 = n700 & ~n1539 & (n746 | ~Ni35); - assign n748 = n706 | n817; - assign n749 = n704 & ~n1539 & (Ni35 | n748); - assign n750 = n710 | n853; - assign n751 = n708 & ~n1539 & (Ni35 | n750); - assign n752 = n740 & n715 & (n716 | n741); - assign n753 = n740 & n718 & (n719 | n741); - assign n754 = n723 | n817; - assign n755 = n721 & ~n1539 & (~Ni35 | n754); - assign n756 = n727 | n853; - assign n757 = n725 & ~n1539 & (~Ni35 | n756); - assign n758 = n731 | n817; - assign n759 = n729 & ~n1539 & (Ni35 | n758); - assign n760 = n735 | n853; - assign n761 = n733 & ~n1539 & (Ni35 | n760); - assign n762 = Ni47 | n923; - assign n763 = (~Ni44 | n762) & ~Ni41; - assign n764 = Ni45 | n923; - assign n765 = (~Ni44 | n764) & ~Ni41; - assign n766 = ~Ni41 & (Ni44 | n762); - assign n767 = ~Ni41 & (Ni44 | n764); - assign n768 = ~n3731 & (~Ni14 | (n3711 & ~Ni2)); - assign n1031_1 = ~n768; - assign n770 = n3726 & (~Ni13 | (~n3707 & ~n3727)); - assign n1036 = ~n770; - assign n772 = ~Pi25 | Ni10; - assign n773 = n772 & ~Ni9 & (~Ni10 | ~n3950); - assign n774 = n3718 & (~Ni9 | (~n3707 & ~n3957)); - assign n1056_1 = ~n774; - assign n776 = (n2403 | n3707) & (~Ni8 | n3715); - assign n1061 = ~n776; - assign n778 = n3713 & (Ni6 | n3712) & ~n4756; - assign n1071_1 = ~n778; - assign n780 = Ni6 & ~n3843 & (~n3668 | ~n3982); - assign n781 = n3709 & n3710 & (n2418 | n3708); - assign n1076 = ~n781; - assign n783 = ~Ni37 & Ni38; - assign n784 = ~Ni32 | ~Ni30; - assign n785 = ~n18 | ~Ni33; - assign n786 = n3770 & n3771 & (n3769 | n3707); - assign n787 = ~n3763 & (n3707 | n3762) & n3764; - assign n788 = Pi23 | Pi24; - assign n789 = Pi26 | Pi27; - assign n790 = n3751 & (~n784 | (n3752 & n3753)); - assign n956_1 = ~n790; - assign n792 = Ni34 & (Ni30 | Ni32 | Ni31); - assign n793 = ~Pi21 | ~n2643; - assign n794 = Ni30 & n793 & (n788 | ~n1463); - assign n795 = Pi24 | ~Pi23; - assign n796 = Ni30 & n793 & (n795 | ~n1463); - assign n797 = ~n3795 | n3956 | n3973; - assign n798 = ~n1919 & (n797 | ~n4771); - assign n799 = ~n2254 & (n797 | ~n3539 | ~n4771); - assign n800 = n3956 | n3751; - assign n801 = ~Ni32 | ~Ni31; - assign n802 = n800 & n801; - assign n803 = n3811 & n2430; - assign n804 = ~n2420 & (n803 | ~Ni33); - assign n805 = ~n2420 & (n803 | Ni33); - assign n806 = (~n655 | Ni31) & ~n784; - assign n807 = n3283 & (~Pi20 | ~n3977); - assign n808 = ~Ni35 & ~Ni30; - assign n809 = n797 | ~n4771; - assign n810 = Pi22 & (n809 | ~n3539); - assign n811 = n2419 & (Ni45 | n2420); - assign n812 = n801 & ~n3829; - assign n813 = n811 & n812; - assign n814 = ~Ni37 | Ni38; - assign n815 = n881 & (Ni40 | n1048); - assign n816 = n814 & (~Ni37 | n815); - assign n817 = ~n3194 | n3852; - assign n818 = n678 & (n815 | n817); - assign n819 = n678 & n816 & (~n783 | n815); - assign n820 = (n815 | n698) & (n819 | n2434); - assign n821 = n816 & n820 & (Ni35 | n818); - assign n822 = ~Ni37 & (Ni36 | (n676 & ~n3194)); - assign n823 = n1082 | n1083; - assign n824 = ~Ni36 & n822; - assign n825 = Ni35 | n2438; - assign n826 = n823 & (n824 | n825); - assign n827 = n883 & (Ni40 | n1051_1); - assign n828 = n814 & (~Ni37 | n827); - assign n829 = n3849 | n3854; - assign n830 = n829 & n828 & (n827 | n817); - assign n831 = Ni38 | n3849; - assign n832 = n828 & (~n783 | n827) & n831; - assign n833 = (n827 | n1052) & (n828 | n886); - assign n834 = (n832 | n3856) & (n830 | n992); - assign n835 = n833 & n834; - assign n836 = n889 & (Ni40 | n1055); - assign n837 = n814 & (~Ni37 | n836); - assign n838 = n3874 | n3854; - assign n839 = n838 & n837 & (n836 | n817); - assign n840 = Ni38 | n3874; - assign n841 = n837 & (~n783 | n836) & n840; - assign n842 = (n839 | n995) & (n837 | n891); - assign n843 = (n841 | n3851) & (n836 | n1056); - assign n844 = n842 & n843; - assign n845 = n835 & n844; - assign n846 = (n845 | n3850) & (n821 | n896); - assign n847 = Ni32 | n1355; - assign n848 = n826 & n846 & (n815 | n847); - assign n849 = n18 | ~n1539; - assign n850 = n849 & n848 & (n18 | n821); - assign n851 = n881 & (Ni40 | n1064); - assign n852 = n814 & (~Ni37 | n851); - assign n853 = ~n3195 | n3852; - assign n854 = n678 & (n851 | n853); - assign n855 = n678 & n852 & (~n783 | n851); - assign n856 = (n851 | n698) & (n855 | n2434); - assign n857 = n852 & n856 & (Ni35 | n854); - assign n858 = ~Ni37 & (Ni36 | (n676 & ~n3195)); - assign n859 = ~Ni36 & n858; - assign n860 = n823 & (n859 | n825); - assign n861 = n883 & (Ni40 | n1067); - assign n862 = n814 & (~Ni37 | n861); - assign n863 = n3849 | n3855; - assign n864 = n863 & n862 & (n861 | n853); - assign n865 = n831 & n862 & (~n783 | n861); - assign n866 = (n861 | n1052) & (n862 | n886); - assign n867 = (n865 | n3856) & (n864 | n992); - assign n868 = n866 & n867; - assign n869 = n889 & (Ni40 | n1070); - assign n870 = n814 & (~Ni37 | n869); - assign n871 = n3874 | n3855; - assign n872 = n871 & n870 & (n869 | n853); - assign n873 = n840 & n870 & (~n783 | n869); - assign n874 = (n872 | n995) & (n870 | n891); - assign n875 = (n873 | n3851) & (n869 | n1056); - assign n876 = n874 & n875; - assign n877 = n868 & n876; - assign n878 = (n877 | n3850) & (n857 | n896); - assign n879 = n860 & n878 & (n851 | n847); - assign n880 = n849 & n879 & (n18 | n857); - assign n881 = n916 & ~Ni41; - assign n882 = n678 & n814 & (n881 | ~Ni38); - assign n883 = ~n762 & ~Ni41; - assign n884 = n814 & n831 & (n883 | ~Ni38); - assign n885 = n883 & n814; - assign n886 = Ni32 | ~Ni36; - assign n887 = Ni32 | Ni36; - assign n888 = (n885 | n886) & (n884 | n887); - assign n889 = ~n764 & ~Ni41; - assign n890 = n814 & n840 & (n889 | ~Ni38); - assign n891 = ~Ni32 | ~Ni36; - assign n892 = (n889 | n891) & (~Ni32 | n890); - assign n893 = ~n3850 & (~n888 | ~n892); - assign n894 = (n881 | n847) & (n1082 | n2438); - assign n895 = (~Ni36 | n881) & n882; - assign n896 = ~n18 | n2420; - assign n897 = ~n893 & n894 & (n895 | n896); - assign n898 = n849 & n897 & (n18 | n895); - assign n899 = Pi22 | ~Ni30; - assign n900 = n899 & (Pi22 | ~n801); - assign n901 = n900 & (Pi22 | n18); - assign n902 = Pi21 | ~Ni30; - assign n903 = n902 & (Ni31 | Pi21); - assign n904 = n2421 & n903; - assign n905 = n904 & (Pi21 | n18); - assign n906 = Pi21 & ~Pi20; - assign n907 = ~n844 & n906; - assign n908 = Pi20 & Pi21; - assign n909 = ~Pi22 & (n907 | (~n876 & n908)); - assign n910 = n901 & (Pi22 | n892); - assign n911 = n905 & n910 & (Pi21 | n888); - assign n912 = (n911 & (Pi19 | ~n3863)) | (~Pi19 & ~n3863); - assign n913 = (n898 | n1702) & (n850 | n1408); - assign n914 = Pi19 | n3859; - assign n915 = n912 & n913 & (n880 | n914); - assign n916 = n738 & ~Ni42; - assign n917 = n916 & (Ni40 | n1134); - assign n918 = n814 & (~Ni37 | n917); - assign n919 = n678 & (n917 | n817); - assign n920 = n678 & n918 & (~n783 | n917); - assign n921 = (n917 | n698) & (n920 | n2434); - assign n922 = n918 & n921 & (Ni35 | n919); - assign n923 = Ni43 | Ni42; - assign n924 = ~n762 & (n1137 | Ni40); - assign n925 = n814 & (~Ni37 | n924); - assign n926 = n829 & n925 & (n924 | n817); - assign n927 = n831 & n925 & (~n783 | n924); - assign n928 = (n924 | n1052) & (n925 | n886); - assign n929 = (n927 | n3856) & (n926 | n992); - assign n930 = n928 & n929; - assign n931 = ~n764 & (n1140 | Ni40); - assign n932 = n814 & (~Ni37 | n931); - assign n933 = n838 & n932 & (n931 | n817); - assign n934 = n840 & n932 & (~n783 | n931); - assign n935 = (n933 | n995) & (n932 | n891); - assign n936_1 = (n934 | n3851) & (n931 | n1056); - assign n937 = n935 & n936_1; - assign n938 = n930 & n937; - assign n939 = (n938 | n3850) & (n922 | n896); - assign n940 = n826 & n939 & (n917 | n847); - assign n941 = n849 & n940 & (n18 | n922); - assign n942 = n916 & (Ni40 | n1148); - assign n943 = n814 & (~Ni37 | n942); - assign n944 = n678 & (n942 | n853); - assign n945 = n678 & n943 & (~n783 | n942); - assign n946 = (n942 | n698) & (n945 | n2434); - assign n947 = n943 & n946 & (Ni35 | n944); - assign n948 = ~n762 & (n1151 | Ni40); - assign n949 = n814 & (~Ni37 | n948); - assign n950 = n863 & n949 & (n948 | n853); - assign n951 = n831 & n949 & (~n783 | n948); - assign n952 = (n948 | n1052) & (n949 | n886); - assign n953 = (n951 | n3856) & (n950 | n992); - assign n954 = n952 & n953; - assign n955 = ~n764 & (n1154 | Ni40); - assign n956 = n814 & (~Ni37 | n955); - assign n957 = n871 & n956 & (n955 | n853); - assign n958 = n840 & n956 & (~n783 | n955); - assign n959 = (n957 | n995) & (n956 | n891); - assign n960 = (n958 | n3851) & (n955 | n1056); - assign n961 = n959 & n960; - assign n962 = n954 & n961; - assign n963 = (n962 | n3850) & (n947 | n896); - assign n964 = n860 & n963 & (n942 | n847); - assign n965 = n849 & n964 & (n18 | n947); - assign n966 = n678 & n814 & (n916 | ~Ni38); - assign n967 = n814 & n831 & (~n762 | ~Ni38); - assign n968 = ~n762 & n814; - assign n969 = (n968 | n886) & (n967 | n887); - assign n970 = n814 & n840 & (~n764 | ~Ni38); - assign n971_1 = (~Ni32 | n970) & (~n764 | n891); - assign n972 = ~n3850 & (~n969 | ~n971_1); - assign n973 = (n916 | n847) & (n1082 | n2438); - assign n974 = (~Ni36 | n916) & n966; - assign n975 = ~n972 & n973 & (n896 | n974); - assign n976 = n849 & n975 & (n18 | n974); - assign n977 = n906 & ~n937; - assign n978 = ~Pi22 & (n977 | (n908 & ~n961)); - assign n979 = n901 & (Pi22 | n971_1); - assign n980 = n905 & n979 & (Pi21 | n969); - assign n981 = (n980 & (Pi19 | ~n3880)) | (~Pi19 & ~n3880); - assign n982 = (n976 | n1702) & (n941 | n1408); - assign n983 = n981 & n982 & (n965 | n914); - assign n984 = n819 & (Ni35 | n818); - assign n985 = Ni38 | n676; - assign n986_1 = ~Ni37 & ~Ni38; - assign n987 = n985 & n986_1; - assign n988 = n987 | n1083; - assign n989 = n987 & n822; - assign n990 = n988 & (n989 | n825); - assign n991 = Ni32 | ~n2530; - assign n992 = Ni32 | Ni35; - assign n993 = (n832 | n991) & (n830 | n992); - assign n994 = n1241 & n891; - assign n995 = ~Ni32 | Ni35; - assign n996 = (n841 | n994) & (n839 | n995); - assign n997 = n993 & n996; - assign n998 = (n997 | n3850) & (n984 | n896); - assign n999 = n990 & n998 & (n815 | n847); - assign n1000 = n849 & n999 & (n18 | n984); - assign n1001_1 = n855 & (Ni35 | n854); - assign n1002 = n987 & n858; - assign n1003 = n988 & (n1002 | n825); - assign n1004 = (n865 | n991) & (n864 | n992); - assign n1005 = (n873 | n994) & (n872 | n995); - assign n1006 = n1004 & n1005; - assign n1007 = (n1006 | n3850) & (n1001_1 | n896); - assign n1008 = n1003 & n1007 & (n851 | n847); - assign n1009 = n849 & n1008 & (n18 | n1001_1); - assign n1010 = n4071 & (n890 | n3663); - assign n1011 = (n881 | n847) & (n987 | n2438); - assign n1012 = n1010 & n1011 & (n882 | n896); - assign n1013 = n849 & n1012 & (n18 | n882); - assign n1014 = n906 & ~n996; - assign n1015 = ~Pi22 & (n1014 | (n908 & ~n1005)); - assign n1016 = n901 & (Pi22 | n890); - assign n1017 = n905 & n1016 & (Pi21 | n884); - assign n1018 = (n1017 & (Pi19 | ~n3873)) | (~Pi19 & ~n3873); - assign n1019 = (n1013 | n1702) & (n1000 | n1408); - assign n1020 = n1018 & n1019 & (n1009 | n914); - assign n1021_1 = n920 & (Ni35 | n919); - assign n1022 = (n927 | n991) & (n926 | n992); - assign n1023 = (n934 | n994) & (n933 | n995); - assign n1024 = n1022 & n1023; - assign n1025 = (n1024 | n3850) & (n1021_1 | n896); - assign n1026 = n990 & n1025 & (n917 | n847); - assign n1027 = n849 & n1026 & (n18 | n1021_1); - assign n1028 = n945 & (Ni35 | n944); - assign n1029 = (n951 | n991) & (n950 | n992); - assign n1030 = (n958 | n994) & (n957 | n995); - assign n1031 = n1029 & n1030; - assign n1032 = (n1031 | n3850) & (n1028 | n896); - assign n1033 = n1003 & n1032 & (n942 | n847); - assign n1034 = n849 & n1033 & (n18 | n1028); - assign n1035 = n4072 & (n970 | n3663); - assign n1036_1 = (n916 | n847) & (n987 | n2438); - assign n1037 = n1035 & n1036_1 & (n966 | n896); - assign n1038 = n849 & n1037 & (n18 | n966); - assign n1039 = n906 & ~n1023; - assign n1040 = ~Pi22 & (n1039 | (n908 & ~n1030)); - assign n1041 = n901 & (Pi22 | n970); - assign n1042 = n905 & n1041 & (Pi21 | n967); - assign n1043 = (n1042 & (Pi19 | ~n3887)) | (~Pi19 & ~n3887); - assign n1044 = (n1038 | n1702) & (n1027 | n1408); - assign n1045 = n1043 & n1044 & (n1034 | n914); - assign n1046 = n1048 | (~Ni37 & n817); - assign n1047 = n1046 & n814 & n678; - assign n1048 = ~n674 & ~n2426; - assign n1049 = n1047 & (n1048 | n698); - assign n1050 = ~Ni32 & (~n814 | ~n829 | ~n4056); - assign n1051_1 = ~n763 & ~Ni41; - assign n1052 = Ni32 | n698; - assign n1053 = ~n1050 & (n1051_1 | n1052); - assign n1054 = Ni32 & (~n814 | ~n838 | ~n4055); - assign n1055 = ~n765 & ~Ni41; - assign n1056 = Ni37 | n891; - assign n1057 = ~n1054 & (n1055 | n1056); - assign n1058 = ~n3850 & (~n1053 | ~n1057); - assign n1059 = (n1048 | n847) & (n824 | n2438); - assign n1060 = ~n1058 & (n896 | n1049) & n1059; - assign n1061_1 = n849 & n1060 & (n18 | n1049); - assign n1062 = n1064 | (~Ni37 & n853); - assign n1063 = n1062 & n814 & n678; - assign n1064 = ~n675 & ~n2426; - assign n1065 = n1063 & (n1064 | n698); - assign n1066 = ~Ni32 & (~n814 | ~n863 | ~n4058); - assign n1067 = ~n766 & ~Ni41; - assign n1068 = ~n1066 & (n1052 | n1067); - assign n1069 = Ni32 & (~n814 | ~n871 | ~n4057); - assign n1070 = ~n767 & ~Ni41; - assign n1071 = ~n1069 & (n1056 | n1070); - assign n1072 = ~n3850 & (~n1068 | ~n1071); - assign n1073 = (n1064 | n847) & (n859 | n2438); - assign n1074 = ~n1072 & (n896 | n1065) & n1073; - assign n1075 = n849 & n1074 & (n18 | n1065); - assign n1076_1 = n881 & (n1048 | ~Ni40); - assign n1077 = n814 & (~Ni37 | n1076_1); - assign n1078 = n678 & n1077 & (~n783 | n1076_1); - assign n1079 = n678 & (n1076_1 | n817); - assign n1080 = (n1076_1 | n698) & (n1078 | n2530); - assign n1081_1 = n1077 & n1080 & (~Ni35 | n1079); - assign n1082 = ~Ni36 & n987; - assign n1083 = ~Ni35 | n2438; - assign n1084 = (n1082 | n825) & (n824 | n1083); - assign n1085_1 = n883 & (n1051_1 | ~Ni40); - assign n1086 = n814 & (~Ni37 | n1085_1); - assign n1087 = n831 & n1086 & (~n783 | n1085_1); - assign n1088 = n829 & n1086 & (n1085_1 | n817); - assign n1089 = (n1085_1 | n1052) & (n1086 | n886); - assign n1090 = (n1087 | n3869) & (n1088 | n1238); - assign n1091 = n1089 & n1090; - assign n1092 = n889 & (n1055 | ~Ni40); - assign n1093 = n814 & (~Ni37 | n1092); - assign n1094 = n840 & n1093 & (~n783 | n1092); - assign n1095 = n838 & n1093 & (n1092 | n817); - assign n1096 = (n1095 | n1241) & (n1093 | n891); - assign n1097 = (n1094 | n3868) & (n1092 | n1056); - assign n1098 = n1096 & n1097; - assign n1099 = n1091 & n1098; - assign n1100 = (n1099 | n3850) & (n1081_1 | n896); - assign n1101 = n1084 & n1100 & (n1076_1 | n847); - assign n1102 = n849 & n1101 & (n18 | n1081_1); - assign n1103 = n881 & (n1064 | ~Ni40); - assign n1104 = n814 & (~Ni37 | n1103); - assign n1105 = n678 & n1104 & (~n783 | n1103); - assign n1106 = n678 & (n1103 | n853); - assign n1107 = (n1103 | n698) & (n1105 | n2530); - assign n1108 = n1104 & n1107 & (~Ni35 | n1106); - assign n1109 = (n1082 | n825) & (n859 | n1083); - assign n1110 = n883 & (n1067 | ~Ni40); - assign n1111 = n814 & (~Ni37 | n1110); - assign n1112 = n831 & n1111 & (~n783 | n1110); - assign n1113 = n863 & n1111 & (n1110 | n853); - assign n1114 = (n1110 | n1052) & (n1111 | n886); - assign n1115 = (n1112 | n3869) & (n1113 | n1238); - assign n1116 = n1114 & n1115; - assign n1117 = n889 & (n1070 | ~Ni40); - assign n1118 = n814 & (~Ni37 | n1117); - assign n1119 = n840 & n1118 & (~n783 | n1117); - assign n1120 = n871 & n1118 & (n1117 | n853); - assign n1121 = (n1120 | n1241) & (n1118 | n891); - assign n1122 = (n1119 | n3868) & (n1117 | n1056); - assign n1123 = n1121 & n1122; - assign n1124 = n1116 & n1123; - assign n1125 = (n1124 | n3850) & (n1108 | n896); - assign n1126 = n1109 & n1125 & (n1103 | n847); - assign n1127 = n849 & n1126 & (n18 | n1108); - assign n1128 = n906 & ~n1098; - assign n1129 = ~Pi22 & (n1128 | (n908 & ~n1123)); - assign n1130 = n906 & ~n1057; - assign n1131 = ~Pi22 & (n1130 | (n908 & ~n1071)); - assign n1132 = n1134 | (~Ni37 & n817); - assign n1133 = n1132 & n814 & n678; - assign n1134 = n4769 & n916; - assign n1135 = n1133 & (n1134 | n698); - assign n1136 = ~Ni32 & (~n814 | ~n829 | ~n4062); - assign n1137 = ~n762 & ~n763; - assign n1138 = ~n1136 & (n1052 | n1137); - assign n1139 = Ni32 & (~n814 | ~n838 | ~n4061); - assign n1140 = ~n764 & ~n765; - assign n1141 = ~n1139 & (n1056 | n1140); - assign n1142 = ~n3850 & (~n1138 | ~n1141); - assign n1143 = (n1134 | n847) & (n824 | n2438); - assign n1144 = ~n1142 & (n896 | n1135) & n1143; - assign n1145 = n849 & n1144 & (n18 | n1135); - assign n1146 = n1148 | (~Ni37 & n853); - assign n1147 = n1146 & n814 & n678; - assign n1148 = n4770 & n916; - assign n1149 = n1147 & (n1148 | n698); - assign n1150 = ~Ni32 & (~n814 | ~n863 | ~n4064); - assign n1151 = ~n762 & ~n766; - assign n1152 = ~n1150 & (n1052 | n1151); - assign n1153 = Ni32 & (~n814 | ~n871 | ~n4063); - assign n1154 = ~n764 & ~n767; - assign n1155 = ~n1153 & (n1056 | n1154); - assign n1156 = ~n3850 & (~n1152 | ~n1155); - assign n1157 = (n1148 | n847) & (n859 | n2438); - assign n1158 = ~n1156 & (n896 | n1149) & n1157; - assign n1159 = n849 & n1158 & (n18 | n1149); - assign n1160 = n916 & (n1134 | ~Ni40); - assign n1161 = n814 & (~Ni37 | n1160); - assign n1162 = n678 & n1161 & (~n783 | n1160); - assign n1163 = n678 & (n1160 | n817); - assign n1164 = (n1160 | n698) & (n1162 | n2530); - assign n1165 = n1161 & n1164 & (~Ni35 | n1163); - assign n1166 = ~n762 & (n1137 | ~Ni40); - assign n1167 = n814 & (~Ni37 | n1166); - assign n1168 = n831 & n1167 & (~n783 | n1166); - assign n1169 = n829 & n1167 & (n1166 | n817); - assign n1170 = (n1166 | n1052) & (n1167 | n886); - assign n1171 = (n1168 | n3869) & (n1169 | n1238); - assign n1172 = n1170 & n1171; - assign n1173 = ~n764 & (n1140 | ~Ni40); - assign n1174 = n814 & (~Ni37 | n1173); - assign n1175 = n840 & n1174 & (~n783 | n1173); - assign n1176 = n838 & n1174 & (n1173 | n817); - assign n1177 = (n1176 | n1241) & (n1174 | n891); - assign n1178 = (n1175 | n3868) & (n1173 | n1056); - assign n1179 = n1177 & n1178; - assign n1180 = n1172 & n1179; - assign n1181 = (n1180 | n3850) & (n1165 | n896); - assign n1182 = n1084 & n1181 & (n1160 | n847); - assign n1183 = n849 & n1182 & (n18 | n1165); - assign n1184 = n916 & (n1148 | ~Ni40); - assign n1185 = n814 & (~Ni37 | n1184); - assign n1186 = n678 & n1185 & (~n783 | n1184); - assign n1187 = n678 & (n1184 | n853); - assign n1188 = (n1184 | n698) & (n1186 | n2530); - assign n1189 = n1185 & n1188 & (~Ni35 | n1187); - assign n1190 = ~n762 & (n1151 | ~Ni40); - assign n1191 = n814 & (~Ni37 | n1190); - assign n1192 = n831 & n1191 & (~n783 | n1190); - assign n1193 = n863 & n1191 & (n1190 | n853); - assign n1194 = (n1190 | n1052) & (n1191 | n886); - assign n1195 = (n1192 | n3869) & (n1193 | n1238); - assign n1196 = n1194 & n1195; - assign n1197 = ~n764 & (n1154 | ~Ni40); - assign n1198 = n814 & (~Ni37 | n1197); - assign n1199 = n840 & n1198 & (~n783 | n1197); - assign n1200 = n871 & n1198 & (n1197 | n853); - assign n1201 = (n1200 | n1241) & (n1198 | n891); - assign n1202 = (n1199 | n3868) & (n1197 | n1056); - assign n1203 = n1201 & n1202; - assign n1204 = n1196 & n1203; - assign n1205 = (n1204 | n3850) & (n1189 | n896); - assign n1206 = n1109 & n1205 & (n1184 | n847); - assign n1207 = n849 & n1206 & (n18 | n1189); - assign n1208 = n906 & ~n1179; - assign n1209 = ~Pi22 & (n1208 | (n908 & ~n1203)); - assign n1210 = n906 & ~n1141; - assign n1211 = ~Pi22 & (n1210 | (n908 & ~n1155)); - assign n1212 = (n914 | n1159) & (Pi19 | ~n3883); - assign n1213 = (n1183 | n3893) & (n1207 | n2109); - assign n1214 = n1145 | n1408; - assign n1215 = ~n3789 & n1214 & n1212 & n1213; - assign n1216 = n698 | ~Ni38; - assign n1217 = n1047 & (n1048 | n1216); - assign n1218 = n831 | n1052; - assign n1219 = Ni32 | n1216; - assign n1220 = ~n1050 & n1218 & (n1051_1 | n1219); - assign n1221 = n891 | n840; - assign n1222 = ~n783 | n891; - assign n1223 = ~n1054 & n1221 & (n1055 | n1222); - assign n1224 = ~n3850 & (~n1220 | ~n1223); - assign n1225 = (n1048 | n847) & (n989 | n2438); - assign n1226 = ~n1224 & (n896 | n1217) & n1225; - assign n1227 = n849 & n1226 & (n18 | n1217); - assign n1228 = n1063 & (n1064 | n1216); - assign n1229 = ~n1066 & n1218 & (n1067 | n1219); - assign n1230 = ~n1069 & n1221 & (n1070 | n1222); - assign n1231 = ~n3850 & (~n1229 | ~n1230); - assign n1232 = (n1064 | n847) & (n1002 | n2438); - assign n1233 = ~n1231 & (n896 | n1228) & n1232; - assign n1234 = n849 & n1233 & (n18 | n1228); - assign n1235 = n1078 & (~Ni35 | n1079); - assign n1236 = (n987 | n825) & (n989 | n1083); - assign n1237 = Ni32 | ~n2434; - assign n1238 = Ni32 | ~Ni35; - assign n1239 = (n1087 | n1237) & (n1088 | n1238); - assign n1240 = n995 & n891; - assign n1241 = ~Ni32 | ~Ni35; - assign n1242 = (n1094 | n1240) & (n1095 | n1241); - assign n1243 = n1239 & n1242; - assign n1244 = (n1243 | n3850) & (n1235 | n896); - assign n1245 = n1236 & n1244 & (n1076_1 | n847); - assign n1246 = n849 & n1245 & (n18 | n1235); - assign n1247 = n1105 & (~Ni35 | n1106); - assign n1248 = (n987 | n825) & (n1002 | n1083); - assign n1249 = (n1112 | n1237) & (n1113 | n1238); - assign n1250 = (n1119 | n1240) & (n1120 | n1241); - assign n1251 = n1249 & n1250; - assign n1252 = (n1251 | n3850) & (n1247 | n896); - assign n1253 = n1248 & n1252 & (n1103 | n847); - assign n1254 = n849 & n1253 & (n18 | n1247); - assign n1255 = n906 & ~n1242; - assign n1256 = ~Pi22 & (n1255 | (n908 & ~n1250)); - assign n1257 = n906 & ~n1223; - assign n1258 = ~Pi22 & (n1257 | (n908 & ~n1230)); - assign n1259 = n1133 & (n1134 | n1216); - assign n1260 = ~n1136 & n1218 & (n1137 | n1219); - assign n1261 = ~n1139 & n1221 & (n1140 | n1222); - assign n1262 = ~n3850 & (~n1260 | ~n1261); - assign n1263 = (n1134 | n847) & (n989 | n2438); - assign n1264 = ~n1262 & (n896 | n1259) & n1263; - assign n1265 = n849 & n1264 & (n18 | n1259); - assign n1266 = n1147 & (n1148 | n1216); - assign n1267 = ~n1150 & n1218 & (n1151 | n1219); - assign n1268 = ~n1153 & n1221 & (n1154 | n1222); - assign n1269 = ~n3850 & (~n1267 | ~n1268); - assign n1270 = (n1148 | n847) & (n1002 | n2438); - assign n1271 = ~n1269 & (n896 | n1266) & n1270; - assign n1272 = n849 & n1271 & (n18 | n1266); - assign n1273 = n1162 & (~Ni35 | n1163); - assign n1274 = (n1168 | n1237) & (n1169 | n1238); - assign n1275 = (n1175 | n1240) & (n1176 | n1241); - assign n1276 = n1274 & n1275; - assign n1277 = (n1276 | n3850) & (n1273 | n896); - assign n1278 = n1236 & n1277 & (n1160 | n847); - assign n1279 = n849 & n1278 & (n18 | n1273); - assign n1280 = n1186 & (~Ni35 | n1187); - assign n1281 = (n1192 | n1237) & (n1193 | n1238); - assign n1282 = (n1199 | n1240) & (n1200 | n1241); - assign n1283 = n1281 & n1282; - assign n1284 = (n1283 | n3850) & (n1280 | n896); - assign n1285 = n1248 & n1284 & (n1184 | n847); - assign n1286 = n849 & n1285 & (n18 | n1280); - assign n1287 = n906 & ~n1275; - assign n1288 = ~Pi22 & (n1287 | (n908 & ~n1282)); - assign n1289 = n906 & ~n1261; - assign n1290 = ~Pi22 & (n1289 | (n908 & ~n1268)); - assign n1291 = (n914 | n1272) & (Pi19 | ~n3890); - assign n1292 = (n1279 | n3893) & (n1286 | n2109); - assign n1293 = n1265 | n1408; - assign n1294 = ~n3792 & n1293 & n1291 & n1292; - assign n1295 = ~n901 | n1129 | n3783 | n3784; - assign n1296 = ~n3870 & (n1295 | ~n4084 | ~n4085); - assign n1297 = ~n901 | n1256 | n3785 | n3786; - assign n1298 = ~n3877 & (n1297 | ~n4087 | ~n4088); - assign n1299 = ~n901 | n1258 | n3875 | n3876; - assign n1300 = ~n2272 & (n1299 | ~n4075); - assign n1301 = n18 & (n3737 | (~n3792 & n4078)); - assign n1302 = n4082 & (n3743 | (~n3890 & n4077)); - assign n1303 = n4081 & (n3740 | (~n3887 & n4074)); - assign n1304 = n4079 & (n1012 | n1495); - assign n1305 = n1304 & n1303 & n1301 & n1302; - assign n1306 = ~n901 | n1131 | n3865 | n3866; - assign n1307 = ~n2272 & (n1306 | ~n4059); - assign n1308 = n18 & (n3737 | (~n3789 & n4066)); - assign n1309 = n4070 & (n3743 | (~n3883 & n4065)); - assign n1310 = n4069 & (n3740 | (~n3880 & n4054)); - assign n1311 = n4067 & (n897 | n1495); - assign n1312 = n1311 & n1310 & n1308 & n1309; - assign n1313 = n4103 & (n1183 | n2372); - assign n1314 = ~Pi25 | n3859; - assign n1315 = n1313 & ~n3789 & (n1207 | n1314); - assign n1316 = n4102 & (n1145 | n2372); - assign n1317 = n1316 & (n1159 | n1314) & ~n3883; - assign n1318 = n4101 & (n941 | n2372); - assign n1319 = n1318 & (n965 | n1314) & ~n3880; - assign n1320 = (n1319 | n3864) & (n1317 | n3867); - assign n1321 = n4096 & n4104 & (n975 | n3848); - assign n1322 = ~Pi19 | Pi17; - assign n1323 = n1320 & n1321 & (n1315 | n1322); - assign n1324 = n4094 & (n1102 | n2372); - assign n1325 = ~n1295 & n1324 & (n1127 | n1314); - assign n1326 = n4093 & (n1061_1 | n2372); - assign n1327 = ~n1306 & n1326 & (n1075 | n1314); - assign n1328 = n4092 & (n850 | n2372); - assign n1329 = n1328 & (n880 | n1314) & ~n3863; - assign n1330 = (n1329 | n3864) & (n1327 | n3867); - assign n1331 = n4096 & n4095 & (n897 | n3848); - assign n1332 = n1330 & n1331 & (n1325 | n1322); - assign n1333 = n4107 & (n1279 | n2372); - assign n1334 = n1333 & (n1286 | n1314) & ~n3792; - assign n1335 = n4106 & (n1265 | n2372); - assign n1336 = n1335 & (n1272 | n1314) & ~n3890; - assign n1337 = n4105 & (n1027 | n2372); - assign n1338 = n1337 & (n1034 | n1314) & ~n3887; - assign n1339 = (n1338 | n3864) & (n1336 | n3867); - assign n1340 = n4096 & n4108 & (n1037 | n3848); - assign n1341 = n1339 & n1340 & (n1334 | n1322); - assign n1342 = n4099 & (n1246 | n2372); - assign n1343 = ~n1297 & n1342 & (n1254 | n1314); - assign n1344 = n4098 & (n1227 | n2372); - assign n1345 = ~n1299 & n1344 & (n1234 | n1314); - assign n1346 = n4097 & (n1000 | n2372); - assign n1347 = n1346 & (n1009 | n1314) & ~n3873; - assign n1348 = (n1347 | n3864) & (n1345 | n3867); - assign n1349 = n4096 & n4100 & (n1012 | n3848); - assign n1350 = n1348 & n1349 & (n1343 | n1322); - assign n1351 = n738 & Ni42; - assign n1352 = n985 & (~n814 | n1351); - assign n1353 = ~Ni31 | ~Ni30; - assign n1354 = (~Ni30 | Ni33) & n1353; - assign n1355 = ~n18 | ~Ni30; - assign n1356 = ~n707 & ~Ni30; - assign n1357 = n1355 & (n18 | n1356); - assign n1358 = ~n711 & ~Ni30; - assign n1359 = n1355 & (n18 | n1358); - assign n1360 = ~n714 & ~Ni30; - assign n1361 = n1355 & (n18 | n1360); - assign n1362 = n899 & n902; - assign n1363 = (n1534 | n1702) & (n4135 | n1408); - assign n1364 = n1520 & n1359; - assign n1365 = n1362 & n1363 & (n1364 | n914); - assign n1366 = ~n732 & ~Ni30; - assign n1367 = n1355 & (n18 | n1366); - assign n1368 = ~n736 & ~Ni30; - assign n1369 = n1355 & (n18 | n1368); - assign n1370 = ~n739 & ~Ni30; - assign n1371 = n1355 & (n18 | n1370); - assign n1372 = (n1535 | n1702) & (n4136 | n1408); - assign n1373 = n1532 & n1369; - assign n1374 = n1362 & n1372 & (n1373 | n914); - assign n1375 = ~n749 & ~Ni30; - assign n1376 = n1355 & (n18 | n1375); - assign n1377 = ~n751 & ~Ni30; - assign n1378 = n1355 & (n18 | n1377); - assign n1379 = ~Ni30 & n1465; - assign n1380 = n1355 & (n18 | n1379); - assign n1381 = (n1494 | n1702) & (n4149 | n1408); - assign n1382 = n1480 & n1378; - assign n1383 = n1362 & n1381 & (n1382 | n914); - assign n1384 = ~n759 & ~Ni30; - assign n1385 = n1355 & (n18 | n1384); - assign n1386 = ~n761 & ~Ni30; - assign n1387 = n1355 & (n18 | n1386); - assign n1388 = ~Ni30 & n1468; - assign n1389 = n1355 & (n18 | n1388); - assign n1390 = (n1496 | n1702) & (n4150 | n1408); - assign n1391 = n1492 & n1387; - assign n1392 = n1362 & n1390 & (n1391 | n914); - assign n1393 = ~Ni37 | n985; - assign n1394 = n676 | n3853; - assign n1395 = n3959 & n3183; - assign n1396 = ~n691 & ~Ni30; - assign n1397 = n1355 & (n18 | n1396); - assign n1398 = n3961 & n3183; - assign n1399 = ~n694 & ~Ni30; - assign n1400 = n1355 & (n18 | n1399); - assign n1401 = ~n699 & ~Ni30; - assign n1402 = n1355 & (n18 | n1401); - assign n1403 = ~n703 & ~Ni30; - assign n1404 = n1355 & (n18 | n1403); - assign n1405 = (n4140 | n3893) & (n4141 | n2109); - assign n1406 = n1362 & (n4138 | n914); - assign n1407 = n1514 & n1397; - assign n1408 = Pi19 | n3857; - assign n1409 = n1405 & n1406 & (n1407 | n1408); - assign n1410 = ~n717 & ~Ni30; - assign n1411 = n1355 & (n18 | n1410); - assign n1412 = ~n720 & ~Ni30; - assign n1413 = n1355 & (n18 | n1412); - assign n1414 = ~n724 & ~Ni30; - assign n1415 = n1355 & (n18 | n1414); - assign n1416 = ~n728 & ~Ni30; - assign n1417 = n1355 & (n18 | n1416); - assign n1418 = (n4145 | n3893) & (n4146 | n2109); - assign n1419 = n1362 & (n4143 | n914); - assign n1420 = n1526 & n1411; - assign n1421 = n1418 & n1419 & (n1420 | n1408); - assign n1422 = ~n742 & ~Ni30; - assign n1423 = n1355 & (n18 | n1422); - assign n1424 = ~n743 & ~Ni30; - assign n1425 = n1355 & (n18 | n1424); - assign n1426 = ~n745 & ~Ni30; - assign n1427 = n1355 & (n18 | n1426); - assign n1428 = ~n747 & ~Ni30; - assign n1429 = n1355 & (n18 | n1428); - assign n1430 = (n4154 | n3893) & (n4155 | n2109); - assign n1431 = n1362 & (n4152 | n914); - assign n1432 = n1474 & n1423; - assign n1433 = n1430 & n1431 & (n1432 | n1408); - assign n1434 = ~n752 & ~Ni30; - assign n1435 = n1355 & (n18 | n1434); - assign n1436 = ~n753 & ~Ni30; - assign n1437 = n1355 & (n18 | n1436); - assign n1438 = ~n755 & ~Ni30; - assign n1439 = n1355 & (n18 | n1438); - assign n1440 = ~n757 & ~Ni30; - assign n1441 = n1355 & (n18 | n1440); - assign n1442 = (n4159 | n3893) & (n4160 | n2109); - assign n1443 = n1362 & (n4157 | n914); - assign n1444 = n1486 & n1435; - assign n1445 = n1442 & n1443 & (n1444 | n1408); - assign n1446 = Ni12 | n2750; - assign n1447 = n1461 & n1362; - assign n1448 = Ni12 | ~n2750; - assign n1449 = (n1447 | n1448) & (n1446 | ~n3991); - assign n1450 = ~n3696 & (~n1552 | (~n1986 & ~n2254)); - assign n1451 = ~n1450 & (n2632 | (~n3918 & n4300)); - assign n1452 = ~Ni12 | ~Ni13; - assign n1453 = n1449 & n1451 & (n1447 | n1452); - assign n1454 = n1354 & (~Ni30 | ~n3761); - assign n1455 = n1454 | (Pi22 & Pi21); - assign n1456 = n1455 | n3677; - assign n1457 = (n1541 | n1610) & (n1447 | ~n3898); - assign n1458 = n1456 & n1457 & (Ni11 | n1453); - assign n1459 = n4772 | n2254; - assign n1460 = (Pi24 | n1362) & (~n793 | n1463); - assign n1461 = n1918 | n2254; - assign n1462 = n1459 & n1460 & (Pi24 | n1461); - assign n1463 = n1353 & n3795; - assign n1464 = n4766 | n1465; - assign n1465 = ~n712 | n1539; - assign n1466 = n1463 & n1464 & (n18 | n1465); - assign n1467 = n4766 | n1468; - assign n1468 = ~n737 | n1539; - assign n1469 = n1463 & n1467 & (n18 | n1468); - assign n1470 = ~n745 | n4766; - assign n1471 = n1463 & n1470 & (n18 | ~n745); - assign n1472 = ~n747 | n4766; - assign n1473 = n1463 & n1472 & (n18 | ~n747); - assign n1474 = ~n742 | n4766; - assign n1475 = n1463 & n1474 & (n18 | ~n742); - assign n1476 = ~n743 | n4766; - assign n1477 = n1463 & n1476 & (n18 | ~n743); - assign n1478 = ~n749 | n4766; - assign n1479 = n1463 & n1478 & (n18 | ~n749); - assign n1480 = ~n751 | n4766; - assign n1481 = n1463 & n1480 & (n18 | ~n751); - assign n1482 = ~n755 | n4766; - assign n1483 = n1463 & n1482 & (n18 | ~n755); - assign n1484 = ~n757 | n4766; - assign n1485 = n1463 & n1484 & (n18 | ~n757); - assign n1486 = ~n752 | n4766; - assign n1487 = n1463 & n1486 & (n18 | ~n752); - assign n1488 = ~n753 | n4766; - assign n1489 = n1463 & n1488 & (n18 | ~n753); - assign n1490 = ~n759 | n4766; - assign n1491 = n1463 & n1490 & (n18 | ~n759); - assign n1492 = ~n761 | n4766; - assign n1493 = n1463 & n1492 & (n18 | ~n761); - assign n1494 = n1464 & n1380; - assign n1495 = Pi16 | n3848; - assign n1496 = n1467 & n1389; - assign n1497 = ~Pi16 | n3848; - assign n1498 = (n1494 | n1495) & (n1496 | n1497); - assign n1499 = ~n3894 & (~n4277 | ~n4278); - assign n1500 = ~n2272 & (~n4281 | ~n4282); - assign n1501 = n1460 & (n3737 | (n4288 & n4287)); - assign n1502 = n4290 & (n3743 | (n4286 & n4285)); - assign n1503 = ~n1499 & (n3740 | (n4279 & n4280)); - assign n1504 = n4289 & (Pi24 | n1498); - assign n1505 = n1504 & n1503 & n1501 & n1502; - assign n1506 = ~n714 | n4766; - assign n1507 = n1463 & n1506 & (n18 | ~n714); - assign n1508 = ~n739 | n4766; - assign n1509 = n1463 & n1508 & (n18 | ~n739); - assign n1510 = ~n699 | n4766; - assign n1511 = n1463 & n1510 & (n18 | ~n699); - assign n1512 = ~n703 | n4766; - assign n1513 = n1463 & n1512 & (n18 | ~n703); - assign n1514 = ~n691 | n4766; - assign n1515 = n1463 & n1514 & (n18 | ~n691); - assign n1516 = ~n694 | n4766; - assign n1517 = n1463 & n1516 & (n18 | ~n694); - assign n1518 = ~n707 | n4766; - assign n1519 = n1463 & n1518 & (n18 | ~n707); - assign n1520 = ~n711 | n4766; - assign n1521 = n1463 & n1520 & (n18 | ~n711); - assign n1522 = ~n724 | n4766; - assign n1523 = n1463 & n1522 & (n18 | ~n724); - assign n1524 = ~n728 | n4766; - assign n1525 = n1463 & n1524 & (n18 | ~n728); - assign n1526 = ~n717 | n4766; - assign n1527 = n1463 & n1526 & (n18 | ~n717); - assign n1528 = ~n720 | n4766; - assign n1529 = n1463 & n1528 & (n18 | ~n720); - assign n1530 = ~n732 | n4766; - assign n1531 = n1463 & n1530 & (n18 | ~n732); - assign n1532 = ~n736 | n4766; - assign n1533 = n1463 & n1532 & (n18 | ~n736); - assign n1534 = n1506 & n1361; - assign n1535 = n1508 & n1371; - assign n1536 = (n1534 | n1495) & (n1535 | n1497); - assign n1537 = ~n3894 & (~n4259 | ~n4260); - assign n1538 = ~n2272 & (~n4263 | ~n4264); - assign n1539 = Ni32 | n2420; - assign n1540 = ~n1352 | n1539; - assign n1541 = n3794 & (Pi26 | n1918); - assign n1542 = ~Ni11 | ~Ni12; - assign n1543 = Ni12 | Ni11; - assign n1544 = n1542 & ~Ni13 & (Ni14 | n1543); - assign n1545 = Ni11 & ~Ni12; - assign n1546 = ~n1462 & n1545 & (~n1541 | ~Ni14); - assign n1547 = ~n3928 & ~n4674 & (Ni14 | ~n3993); - assign n1548 = ~n3944 & (~n4273 | ~n4275 | ~n4276); - assign n1549 = ~n794 & n1459 & (~n788 | n1461); - assign n1550 = Pi21 | n3801; - assign n1551 = Pi22 | n3801; - assign n1552 = n1550 & n1551; - assign n1553 = ~Ni13 & (Ni14 | Ni12); - assign n1554 = ~n794 & (n1523 | n3935); - assign n1555 = (n4145 | n3936) & (n4146 | n2707); - assign n1556 = n3859 | n788; - assign n1557 = n1554 & n1555 & (n1525 | n1556); - assign n1558 = ~n794 & (n1527 | n3935); - assign n1559 = (n1420 | n3936) & (n4143 | n2707); - assign n1560 = n1558 & n1559 & (n1529 | n1556); - assign n1561 = ~n794 & (n1531 | n3935); - assign n1562 = (n4136 | n3936) & (n1373 | n2707); - assign n1563 = n1561 & n1562 & (n1533 | n1556); - assign n1564 = (n1563 | n3864) & (n1560 | n3867); - assign n1565 = n4254 & n4252 & (n1535 | n3934); - assign n1566 = n1564 & n1565 & (n1557 | n1322); - assign n1567 = ~n794 & (n1511 | n3935); - assign n1568 = (n4140 | n3936) & (n4141 | n2707); - assign n1569 = n1567 & n1568 & (n1513 | n1556); - assign n1570 = ~n794 & (n1515 | n3935); - assign n1571 = (n1407 | n3936) & (n4138 | n2707); - assign n1572 = n1570 & n1571 & (n1517 | n1556); - assign n1573 = ~n794 & (n1519 | n3935); - assign n1574 = (n4135 | n3936) & (n1364 | n2707); - assign n1575 = n1573 & n1574 & (n1521 | n1556); - assign n1576 = (n1575 | n3864) & (n1572 | n3867); - assign n1577 = n4251 & n4252 & (n1534 | n3934); - assign n1578 = n1576 & n1577 & (n1569 | n1322); - assign n1579 = ~n794 & (n1483 | n3935); - assign n1580 = (n4159 | n3936) & (n4160 | n2707); - assign n1581 = n1579 & n1580 & (n1485 | n1556); - assign n1582 = ~n794 & (n1487 | n3935); - assign n1583 = (n1444 | n3936) & (n4157 | n2707); - assign n1584 = n1582 & n1583 & (n1489 | n1556); - assign n1585 = ~n794 & (n1491 | n3935); - assign n1586 = (n4150 | n3936) & (n1391 | n2707); - assign n1587 = n1585 & n1586 & (n1493 | n1556); - assign n1588 = (n1587 | n3864) & (n1584 | n3867); - assign n1589 = n4255 & n4252 & (n1496 | n3934); - assign n1590 = n1588 & n1589 & (n1581 | n1322); - assign n1591 = ~n794 & (n1471 | n3935); - assign n1592 = (n4154 | n3936) & (n4155 | n2707); - assign n1593 = n1591 & n1592 & (n1473 | n1556); - assign n1594 = ~n794 & (n1475 | n3935); - assign n1595 = (n1432 | n3936) & (n4152 | n2707); - assign n1596 = n1594 & n1595 & (n1477 | n1556); - assign n1597 = ~n794 & (n1479 | n3935); - assign n1598 = (n4149 | n3936) & (n1382 | n2707); - assign n1599 = n1597 & n1598 & (n1481 | n1556); - assign n1600 = (n1599 | n3864) & (n1596 | n3867); - assign n1601 = n4253 & n4252 & (n1494 | n3934); - assign n1602 = n1600 & n1601 & (n1593 | n1322); - assign n1603 = ~Ni14 & ~n3796 & (n788 | ~n3797); - assign n1604 = ~n1986 & n788 & Ni14 & ~n2254; - assign n1605 = Ni12 & (n1603 | n1604 | ~n4250); - assign n1606 = ~n1605 & (n1446 | (n4256 & n4257)); - assign n1607 = n1606 & (n1549 | n1553); - assign n1608 = ~n1454 & ~n3677 & (n788 | ~n1463); - assign n1609 = (Ni11 | n1607) & (n1549 | ~n3898); - assign n1610 = n2254 | n3677; - assign n1611 = ~n1608 & n1609 & (n1540 | n1610); - assign n1612 = ~n796 & n1459 & (~n795 | n1461); - assign n1613 = ~n796 & (n1523 | n3947); - assign n1614 = (n4145 | n3948) & (n4146 | n2757); - assign n1615 = n3859 | n795; - assign n1616 = n1613 & n1614 & (n1525 | n1615); - assign n1617 = ~n796 & (n1527 | n3947); - assign n1618 = (n1420 | n3948) & (n4143 | n2757); - assign n1619 = n1617 & n1618 & (n1529 | n1615); - assign n1620 = ~n796 & (n1531 | n3947); - assign n1621 = (n4136 | n3948) & (n1373 | n2757); - assign n1622 = n1620 & n1621 & (n1533 | n1615); - assign n1623 = (n1622 | n3864) & (n1619 | n3867); - assign n1624 = n4296 & n4294 & (n1535 | n3946); - assign n1625 = n1623 & n1624 & (n1616 | n1322); - assign n1626 = ~n796 & (n1511 | n3947); - assign n1627 = (n4140 | n3948) & (n4141 | n2757); - assign n1628 = n1626 & n1627 & (n1513 | n1615); - assign n1629 = ~n796 & (n1515 | n3947); - assign n1630 = (n1407 | n3948) & (n4138 | n2757); - assign n1631 = n1629 & n1630 & (n1517 | n1615); - assign n1632 = ~n796 & (n1519 | n3947); - assign n1633 = (n4135 | n3948) & (n1364 | n2757); - assign n1634 = n1632 & n1633 & (n1521 | n1615); - assign n1635 = (n1634 | n3864) & (n1631 | n3867); - assign n1636 = n4293 & n4294 & (n1534 | n3946); - assign n1637 = n1635 & n1636 & (n1628 | n1322); - assign n1638 = ~n796 & (n1483 | n3947); - assign n1639 = (n4159 | n3948) & (n4160 | n2757); - assign n1640 = n1638 & n1639 & (n1485 | n1615); - assign n1641 = ~n796 & (n1487 | n3947); - assign n1642 = (n1444 | n3948) & (n4157 | n2757); - assign n1643 = n1641 & n1642 & (n1489 | n1615); - assign n1644 = ~n796 & (n1491 | n3947); - assign n1645 = (n4150 | n3948) & (n1391 | n2757); - assign n1646 = n1644 & n1645 & (n1493 | n1615); - assign n1647 = (n1646 | n3864) & (n1643 | n3867); - assign n1648 = n4297 & n4294 & (n1496 | n3946); - assign n1649 = n1647 & n1648 & (n1640 | n1322); - assign n1650 = ~n796 & (n1471 | n3947); - assign n1651 = (n4154 | n3948) & (n4155 | n2757); - assign n1652 = n1650 & n1651 & (n1473 | n1615); - assign n1653 = ~n796 & (n1475 | n3947); - assign n1654 = (n1432 | n3948) & (n4152 | n2757); - assign n1655 = n1653 & n1654 & (n1477 | n1615); - assign n1656 = ~n796 & (n1479 | n3947); - assign n1657 = (n4149 | n3948) & (n1382 | n2757); - assign n1658 = n1656 & n1657 & (n1481 | n1615); - assign n1659 = (n1658 | n3864) & (n1655 | n3867); - assign n1660 = n4295 & n4294 & (n1494 | n3946); - assign n1661 = n1659 & n1660 & (n1652 | n1322); - assign n1662 = ~Ni14 & ~n3796 & (n795 | ~n3797); - assign n1663 = ~n1986 & n795 & Ni14 & ~n2254; - assign n1664 = Ni12 & (n1662 | n1663 | ~n4292); - assign n1665 = ~n1664 & (n1446 | (n4298 & n4299)); - assign n1666 = n1665 & (n1553 | n1612); - assign n1667 = ~n1454 & ~n3677 & (n795 | ~n1463); - assign n1668 = (Ni11 | n1666) & (n1612 | ~n3898); - assign n1669 = ~n1667 & (n1540 | n1610) & n1668; - assign n1670 = ~Ni9 & (~Ni8 | ~Ni7); - assign n1671 = n1670 & (Ni10 | ~Ni7); - assign n1672 = (n4129 | n1702) & (n1783 | n1408); - assign n1673 = n1778 & n1359; - assign n1674 = n1362 & n1672 & (n1673 | n914); - assign n1675 = (n4131 | n1702) & (n1748 | n1408); - assign n1676 = n1743 & n1369; - assign n1677 = n1362 & n1675 & (n1676 | n914); - assign n1678 = (n4130 | n1702) & (n1853 | n1408); - assign n1679 = n1848 & n1378; - assign n1680 = n1362 & n1678 & (n1679 | n914); - assign n1681 = (n4132 | n1702) & (n1818 | n1408); - assign n1682 = n1813 & n1387; - assign n1683 = n1362 & n1681 & (n1682 | n914); - assign n1684 = (n1764 | n3893) & (n4119 | n2109); - assign n1685 = n1362 & (n4120 | n914); - assign n1686 = n1766 & n1397; - assign n1687 = n1684 & n1685 & (n1686 | n1408); - assign n1688 = (n1728 | n3893) & (n4123 | n2109); - assign n1689 = n1362 & (n4124 | n914); - assign n1690 = n1731 & n1411; - assign n1691 = n1688 & n1689 & (n1690 | n1408); - assign n1692 = (n1834 | n3893) & (n4121 | n2109); - assign n1693 = n1362 & (n4122 | n914); - assign n1694 = n1836 & n1423; - assign n1695 = n1692 & n1693 & (n1694 | n1408); - assign n1696 = (n1799 | n3893) & (n4125 | n2109); - assign n1697 = n1362 & (n4126 | n914); - assign n1698 = n1801 & n1435; - assign n1699 = n1696 & n1697 & (n1698 | n1408); - assign n1700 = (Pi20 & n1368) | (n1366 & (~Pi20 | n1368)); - assign n1701 = Pi19 | n2254; - assign n1702 = ~Pi19 | n2254; - assign n1703 = (n1700 | n1701) & (n1370 | n1702); - assign n1704 = (Pi20 & n1377) | (n1375 & (~Pi20 | n1377)); - assign n1705 = (n1704 | n1701) & (n1379 | n1702); - assign n1706 = (Pi20 & n1386) | (n1384 & (~Pi20 | n1386)); - assign n1707 = (n1706 | n1701) & (n1388 | n1702); - assign n1708 = (Pi20 & n1412) | (n1410 & (~Pi20 | n1412)); - assign n1709 = (Pi20 & n1416) | (n1414 & (~Pi20 | n1416)); - assign n1710 = (n1708 | n1701) & (n1709 | n1702); - assign n1711 = (Pi20 & n1424) | (n1422 & (~Pi20 | n1424)); - assign n1712 = (Pi20 & n1428) | (n1426 & (~Pi20 | n1428)); - assign n1713 = (n1711 | n1701) & (n1712 | n1702); - assign n1714 = (Pi20 & n1436) | (n1434 & (~Pi20 | n1436)); - assign n1715 = (Pi20 & n1440) | (n1438 & (~Pi20 | n1440)); - assign n1716 = (n1714 | n1701) & (n1715 | n1702); - assign n1717 = n1446 | n4684 | n4685; - assign n1718 = ~n4683 & (Pi17 | (n4127 & n4128)); - assign n1719 = n1717 & (n1718 | n1448); - assign n1720 = ~n724 | n4767; - assign n1721 = ~n724 & n1354; - assign n1722 = n1354 & n1720 & (n18 | n1721); - assign n1723 = ~n728 | n4767; - assign n1724 = ~n728 & n1354; - assign n1725 = n1354 & n1723 & (n18 | n1724); - assign n1726 = (n1722 | n3915) & (n1725 | n3916); - assign n1727 = ~n3918 & (n3917 | n4123); - assign n1728 = n1720 & n1415; - assign n1729 = ~n789 | n3857; - assign n1730 = n1726 & n1727 & (n1728 | n1729); - assign n1731 = ~n717 | n4767; - assign n1732 = ~n717 & n1354; - assign n1733 = n1354 & n1731 & (n18 | n1732); - assign n1734 = ~n720 | n4767; - assign n1735 = ~n720 & n1354; - assign n1736 = n1354 & n1734 & (n18 | n1735); - assign n1737 = (n1733 | n3915) & (n1736 | n3916); - assign n1738 = ~n3918 & (n3917 | n4124); - assign n1739 = n1737 & n1738 & (n1690 | n1729); - assign n1740 = ~n732 | n4767; - assign n1741 = ~n732 & n1354; - assign n1742 = n1354 & n1740 & (n18 | n1741); - assign n1743 = ~n736 | n4767; - assign n1744 = ~n736 & n1354; - assign n1745 = n1354 & n1743 & (n18 | n1744); - assign n1746 = (n1742 | n3915) & (n1745 | n3916); - assign n1747 = ~n3918 & (n1676 | n3917); - assign n1748 = n1740 & n1367; - assign n1749 = n1746 & n1747 & (n1748 | n1729); - assign n1750 = ~n739 | n4767; - assign n1751 = ~n739 & n1354; - assign n1752 = n1354 & n1750 & (n18 | n1751); - assign n1753 = (n1749 | n3864) & (n1739 | n3867); - assign n1754 = n4244 & n4242 & (n4131 | n3914); - assign n1755 = n1753 & n1754 & (n1730 | n1322); - assign n1756 = ~n699 | n4767; - assign n1757 = ~n699 & n1354; - assign n1758 = n1354 & n1756 & (n18 | n1757); - assign n1759 = ~n703 | n4767; - assign n1760 = ~n703 & n1354; - assign n1761 = n1354 & n1759 & (n18 | n1760); - assign n1762 = (n1758 | n3915) & (n1761 | n3916); - assign n1763 = ~n3918 & (n3917 | n4119); - assign n1764 = n1756 & n1402; - assign n1765 = n1762 & n1763 & (n1764 | n1729); - assign n1766 = ~n691 | n4767; - assign n1767 = ~n691 & n1354; - assign n1768 = n1354 & n1766 & (n18 | n1767); - assign n1769 = ~n694 | n4767; - assign n1770 = ~n694 & n1354; - assign n1771 = n1354 & n1769 & (n18 | n1770); - assign n1772 = (n1768 | n3915) & (n1771 | n3916); - assign n1773 = ~n3918 & (n3917 | n4120); - assign n1774 = n1772 & n1773 & (n1686 | n1729); - assign n1775 = ~n707 | n4767; - assign n1776 = ~n707 & n1354; - assign n1777 = n1354 & n1775 & (n18 | n1776); - assign n1778 = ~n711 | n4767; - assign n1779 = ~n711 & n1354; - assign n1780 = n1354 & n1778 & (n18 | n1779); - assign n1781 = (n1777 | n3915) & (n1780 | n3916); - assign n1782 = ~n3918 & (n1673 | n3917); - assign n1783 = n1775 & n1357; - assign n1784 = n1781 & n1782 & (n1783 | n1729); - assign n1785 = ~n714 | n4767; - assign n1786 = ~n714 & n1354; - assign n1787 = n1354 & n1785 & (n18 | n1786); - assign n1788 = (n1784 | n3864) & (n1774 | n3867); - assign n1789 = n4241 & n4242 & (n4129 | n3914); - assign n1790 = n1788 & n1789 & (n1765 | n1322); - assign n1791 = ~n755 | n4767; - assign n1792 = ~n755 & n1354; - assign n1793 = n1354 & n1791 & (n18 | n1792); - assign n1794 = ~n757 | n4767; - assign n1795 = ~n757 & n1354; - assign n1796 = n1354 & n1794 & (n18 | n1795); - assign n1797 = (n1793 | n3915) & (n1796 | n3916); - assign n1798 = ~n3918 & (n3917 | n4125); - assign n1799 = n1791 & n1439; - assign n1800 = n1797 & n1798 & (n1799 | n1729); - assign n1801 = ~n752 | n4767; - assign n1802 = ~n752 & n1354; - assign n1803 = n1354 & n1801 & (n18 | n1802); - assign n1804 = ~n753 | n4767; - assign n1805 = ~n753 & n1354; - assign n1806 = n1354 & n1804 & (n18 | n1805); - assign n1807 = (n1803 | n3915) & (n1806 | n3916); - assign n1808 = ~n3918 & (n3917 | n4126); - assign n1809 = n1807 & n1808 & (n1698 | n1729); - assign n1810 = ~n759 | n4767; - assign n1811 = ~n759 & n1354; - assign n1812 = n1354 & n1810 & (n18 | n1811); - assign n1813 = ~n761 | n4767; - assign n1814 = ~n761 & n1354; - assign n1815 = n1354 & n1813 & (n18 | n1814); - assign n1816 = (n1812 | n3915) & (n1815 | n3916); - assign n1817 = ~n3918 & (n1682 | n3917); - assign n1818 = n1810 & n1385; - assign n1819 = n1816 & n1817 & (n1818 | n1729); - assign n1820 = n4767 | n1468; - assign n1821 = n1468 & n1354; - assign n1822 = n1354 & n1820 & (n18 | n1821); - assign n1823 = (n1819 | n3864) & (n1809 | n3867); - assign n1824 = n4245 & n4242 & (n4132 | n3914); - assign n1825 = n1823 & n1824 & (n1800 | n1322); - assign n1826 = ~n745 | n4767; - assign n1827 = ~n745 & n1354; - assign n1828 = n1354 & n1826 & (n18 | n1827); - assign n1829 = ~n747 | n4767; - assign n1830 = ~n747 & n1354; - assign n1831 = n1354 & n1829 & (n18 | n1830); - assign n1832 = (n1828 | n3915) & (n1831 | n3916); - assign n1833 = ~n3918 & (n3917 | n4121); - assign n1834 = n1826 & n1427; - assign n1835 = n1832 & n1833 & (n1834 | n1729); - assign n1836 = ~n742 | n4767; - assign n1837 = ~n742 & n1354; - assign n1838 = n1354 & n1836 & (n18 | n1837); - assign n1839 = ~n743 | n4767; - assign n1840 = ~n743 & n1354; - assign n1841 = n1354 & n1839 & (n18 | n1840); - assign n1842 = (n1838 | n3915) & (n1841 | n3916); - assign n1843 = ~n3918 & (n3917 | n4122); - assign n1844 = n1842 & n1843 & (n1694 | n1729); - assign n1845 = ~n749 | n4767; - assign n1846 = ~n749 & n1354; - assign n1847 = n1354 & n1845 & (n18 | n1846); - assign n1848 = ~n751 | n4767; - assign n1849 = ~n751 & n1354; - assign n1850 = n1354 & n1848 & (n18 | n1849); - assign n1851 = (n1847 | n3915) & (n1850 | n3916); - assign n1852 = ~n3918 & (n1679 | n3917); - assign n1853 = n1845 & n1376; - assign n1854 = n1851 & n1852 & (n1853 | n1729); - assign n1855 = n4767 | n1465; - assign n1856 = n1465 & n1354; - assign n1857 = n1354 & n1855 & (n18 | n1856); - assign n1858 = (n1854 | n3864) & (n1844 | n3867); - assign n1859 = n4243 & n4242 & (n4130 | n3914); - assign n1860 = n1858 & n1859 & (n1835 | n1322); - assign n1861 = ~n2272 & (~n4226 | ~n4227); - assign n1862 = ~n2272 & (~n4207 | ~n4208); - assign n1863 = n3696 | n4680 | n4682; - assign n1864 = n1719 & (n2632 | (n4247 & n4246)); - assign n1865 = n1863 & n1864 & (n1718 | n1452); - assign n1866 = (n1722 | n3901) & (n1725 | n3902); - assign n1867 = n1455 & (n4123 | n3903); - assign n1868 = ~n3761 | n3857; - assign n1869 = n1866 & n1867 & (n1728 | n1868); - assign n1870 = (n1733 | n3901) & (n1736 | n3902); - assign n1871 = n1455 & (n4124 | n3903); - assign n1872 = n1870 & n1871 & (n1690 | n1868); - assign n1873 = (n1742 | n3901) & (n1745 | n3902); - assign n1874 = n1455 & (n1676 | n3903); - assign n1875 = n1873 & n1874 & (n1748 | n1868); - assign n1876 = (n1875 | n3864) & (n1872 | n3867); - assign n1877 = n4201 & n4199 & (n4131 | n3900); - assign n1878 = n1876 & n1877 & (n1869 | n1322); - assign n1879 = (n1758 | n3901) & (n1761 | n3902); - assign n1880 = n1455 & (n4119 | n3903); - assign n1881 = n1879 & n1880 & (n1764 | n1868); - assign n1882 = (n1768 | n3901) & (n1771 | n3902); - assign n1883 = n1455 & (n4120 | n3903); - assign n1884 = n1882 & n1883 & (n1686 | n1868); - assign n1885 = (n1777 | n3901) & (n1780 | n3902); - assign n1886 = n1455 & (n1673 | n3903); - assign n1887 = n1885 & n1886 & (n1783 | n1868); - assign n1888 = (n1887 | n3864) & (n1884 | n3867); - assign n1889 = n4198 & n4199 & (n4129 | n3900); - assign n1890 = n1888 & n1889 & (n1881 | n1322); - assign n1891 = (n1793 | n3901) & (n1796 | n3902); - assign n1892 = n1455 & (n4125 | n3903); - assign n1893 = n1891 & n1892 & (n1799 | n1868); - assign n1894 = (n1803 | n3901) & (n1806 | n3902); - assign n1895 = n1455 & (n4126 | n3903); - assign n1896 = n1894 & n1895 & (n1698 | n1868); - assign n1897 = (n1812 | n3901) & (n1815 | n3902); - assign n1898 = n1455 & (n1682 | n3903); - assign n1899 = n1897 & n1898 & (n1818 | n1868); - assign n1900 = (n1899 | n3864) & (n1896 | n3867); - assign n1901 = n4202 & n4199 & (n4132 | n3900); - assign n1902 = n1900 & n1901 & (n1893 | n1322); - assign n1903 = (n1828 | n3901) & (n1831 | n3902); - assign n1904 = n1455 & (n4121 | n3903); - assign n1905 = n1903 & n1904 & (n1834 | n1868); - assign n1906 = (n1838 | n3901) & (n1841 | n3902); - assign n1907 = n1455 & (n4122 | n3903); - assign n1908 = n1906 & n1907 & (n1694 | n1868); - assign n1909 = (n1847 | n3901) & (n1850 | n3902); - assign n1910 = n1455 & (n1679 | n3903); - assign n1911 = n1909 & n1910 & (n1853 | n1868); - assign n1912 = (n1911 | n3864) & (n1908 | n3867); - assign n1913 = n4200 & n4199 & (n4130 | n3900); - assign n1914 = n1912 & n1913 & (n1905 | n1322); - assign n1915 = (n1878 | n3884) & (n1902 | n3891); - assign n1916 = (n1890 | n3870) & (n1914 | n3877); - assign n1917 = n1915 & n1916; - assign n1918 = ~Ni30 & n1540; - assign n1919 = Pi25 | n2254; - assign n1920 = n1362 & (n1918 | n1919); - assign n1921 = n1920 & (n1929 | (n4118 & n4116)); - assign n1922 = n1379 & (~Pi16 | n1388); - assign n1923 = ~Pi25 | n3848; - assign n1924 = n1921 & (n1922 | n1923); - assign n1925 = n1920 & (n1929 | (n4114 & n4112)); - assign n1926 = n1360 & (~Pi16 | n1370); - assign n1927 = n1925 & (n1926 | n1923); - assign n1928 = (n4149 | n3858) & (n1382 | n3860); - assign n1929 = ~Pi25 | n2254; - assign n1930 = n1928 & (n1704 | n1929); - assign n1931 = ~n3740 & ((~n1706 & ~n1929) | ~n4151); - assign n1932 = ~n2272 & ((~n1711 & ~n1929) | ~n4153); - assign n1933 = ~n3895 & ((~n1712 & ~n1929) | ~n4156); - assign n1934 = ~n3743 & ((~n1714 & ~n1929) | ~n4158); - assign n1935 = ~n3737 & ((~n1715 & ~n1929) | ~n4161); - assign n1936 = (n4135 | n3858) & (n1364 | n3860); - assign n1937 = (Pi20 & n1358) | (n1356 & (~Pi20 | n1358)); - assign n1938 = n1936 & (n1937 | n1929); - assign n1939 = ~n3740 & ((~n1700 & ~n1929) | ~n4137); - assign n1940 = ~n2272 & ((~n1929 & ~n1961) | ~n4139); - assign n1941 = ~n3895 & ((~n1929 & ~n1958) | ~n4142); - assign n1942 = ~n3743 & ((~n1708 & ~n1929) | ~n4144); - assign n1943 = ~n3737 & ((~n1709 & ~n1929) | ~n4147); - assign n1944 = (~Pi15 & n1927) | (n1924 & (Pi15 | n1927)); - assign n1945 = (n1448 | n1944) & (n1446 | ~n3990); - assign n1946 = n1455 & (n1541 | n1919); - assign n1947 = (n1721 | n3931) & (n1724 | n3932); - assign n1948 = n1929 | ~n3761; - assign n1949 = n1946 & n1947 & (n1709 | n1948); - assign n1950 = (n1732 | n3931) & (n1735 | n3932); - assign n1951 = n1946 & n1950 & (n1708 | n1948); - assign n1952 = (n1741 | n3931) & (n1744 | n3932); - assign n1953 = n1946 & n1952 & (n1700 | n1948); - assign n1954 = (n1953 | n3864) & (n1951 | n3867); - assign n1955 = n4190 & n4188 & (n1370 | n3930); - assign n1956 = n1954 & n1955 & (n1949 | n1322); - assign n1957 = (n1757 | n3931) & (n1760 | n3932); - assign n1958 = (Pi20 & n1403) | (n1401 & (~Pi20 | n1403)); - assign n1959 = n1946 & n1957 & (n1958 | n1948); - assign n1960 = (n1767 | n3931) & (n1770 | n3932); - assign n1961 = (Pi20 & n1399) | (n1396 & (~Pi20 | n1399)); - assign n1962 = n1946 & n1960 & (n1961 | n1948); - assign n1963 = (n1776 | n3931) & (n1779 | n3932); - assign n1964 = n1946 & n1963 & (n1937 | n1948); - assign n1965 = (n1964 | n3864) & (n1962 | n3867); - assign n1966 = n4187 & n4188 & (n1360 | n3930); - assign n1967 = n1965 & n1966 & (n1959 | n1322); - assign n1968 = (n1792 | n3931) & (n1795 | n3932); - assign n1969 = n1946 & n1968 & (n1715 | n1948); - assign n1970 = (n1802 | n3931) & (n1805 | n3932); - assign n1971 = n1946 & n1970 & (n1714 | n1948); - assign n1972 = (n1811 | n3931) & (n1814 | n3932); - assign n1973 = n1946 & n1972 & (n1706 | n1948); - assign n1974 = (n1973 | n3864) & (n1971 | n3867); - assign n1975 = n4191 & n4188 & (n1388 | n3930); - assign n1976 = n1974 & n1975 & (n1969 | n1322); - assign n1977 = (n1827 | n3931) & (n1830 | n3932); - assign n1978 = n1946 & n1977 & (n1712 | n1948); - assign n1979 = (n1837 | n3931) & (n1840 | n3932); - assign n1980 = n1946 & n1979 & (n1711 | n1948); - assign n1981 = (n1846 | n3931) & (n1849 | n3932); - assign n1982 = n1946 & n1981 & (n1704 | n1948); - assign n1983 = (n1982 | n3864) & (n1980 | n3867); - assign n1984 = n4189 & n4188 & (n1379 | n3930); - assign n1985 = n1983 & n1984 & (n1978 | n1322); - assign n1986 = n3793 & (Pi27 | n1918); - assign n1987 = n1552 & (n1986 | n1919); - assign n1988 = (n1709 | n3922) & (n1721 | n3923); - assign n1989 = ~Pi27 | n1314; - assign n1990 = n1987 & n1988 & (n1724 | n1989); - assign n1991 = (n1708 | n3922) & (n1732 | n3923); - assign n1992 = n1987 & n1991 & (n1735 | n1989); - assign n1993 = (n1700 | n3922) & (n1741 | n3923); - assign n1994 = n1987 & n1993 & (n1744 | n1989); - assign n1995 = (n1994 | n3864) & (n1992 | n3867); - assign n1996 = n4183 & n4181 & (n1751 | n3921); - assign n1997 = n1995 & n1996 & (n1990 | n1322); - assign n1998 = (n1958 | n3922) & (n1757 | n3923); - assign n1999 = n1987 & n1998 & (n1760 | n1989); - assign n2000 = (n1961 | n3922) & (n1767 | n3923); - assign n2001 = n1987 & n2000 & (n1770 | n1989); - assign n2002 = (n1937 | n3922) & (n1776 | n3923); - assign n2003 = n1987 & n2002 & (n1779 | n1989); - assign n2004 = (n2003 | n3864) & (n2001 | n3867); - assign n2005 = n4180 & n4181 & (n1786 | n3921); - assign n2006 = n2004 & n2005 & (n1999 | n1322); - assign n2007 = (n1715 | n3922) & (n1792 | n3923); - assign n2008 = n1987 & n2007 & (n1795 | n1989); - assign n2009 = (n1714 | n3922) & (n1802 | n3923); - assign n2010 = n1987 & n2009 & (n1805 | n1989); - assign n2011 = (n1706 | n3922) & (n1811 | n3923); - assign n2012 = n1987 & n2011 & (n1814 | n1989); - assign n2013 = (n2012 | n3864) & (n2010 | n3867); - assign n2014 = n4184 & n4181 & (n1821 | n3921); - assign n2015 = n2013 & n2014 & (n2008 | n1322); - assign n2016 = (n1712 | n3922) & (n1827 | n3923); - assign n2017 = n1987 & n2016 & (n1830 | n1989); - assign n2018 = (n1711 | n3922) & (n1837 | n3923); - assign n2019 = n1987 & n2018 & (n1840 | n1989); - assign n2020 = (n1704 | n3922) & (n1846 | n3923); - assign n2021 = n1987 & n2020 & (n1849 | n1989); - assign n2022 = (n2021 | n3864) & (n2019 | n3867); - assign n2023 = n4182 & n4181 & (n1856 | n3921); - assign n2024 = n2022 & n2023 & (n2017 | n1322); - assign n2025 = (~Pi26 | n1918) & n3794; - assign n2026 = ~n3918 & (n1919 | n2025); - assign n2027 = (n1721 | n3926) & (n1724 | n3927); - assign n2028 = ~n789 | n1929; - assign n2029 = n2026 & n2027 & (n1709 | n2028); - assign n2030 = (n1732 | n3926) & (n1735 | n3927); - assign n2031 = n2026 & n2030 & (n1708 | n2028); - assign n2032 = (n1741 | n3926) & (n1744 | n3927); - assign n2033 = n2026 & n2032 & (n1700 | n2028); - assign n2034 = (n2033 | n3864) & (n2031 | n3867); - assign n2035 = n4176 & n4174 & (n1370 | n3925); - assign n2036 = n2034 & n2035 & (n2029 | n1322); - assign n2037 = (n1757 | n3926) & (n1760 | n3927); - assign n2038 = n2026 & n2037 & (n1958 | n2028); - assign n2039 = (n1767 | n3926) & (n1770 | n3927); - assign n2040 = n2026 & n2039 & (n1961 | n2028); - assign n2041 = (n1776 | n3926) & (n1779 | n3927); - assign n2042 = n2026 & n2041 & (n1937 | n2028); - assign n2043 = (n2042 | n3864) & (n2040 | n3867); - assign n2044 = n4173 & n4174 & (n1360 | n3925); - assign n2045 = n2043 & n2044 & (n2038 | n1322); - assign n2046 = (n1792 | n3926) & (n1795 | n3927); - assign n2047 = n2026 & n2046 & (n1715 | n2028); - assign n2048 = (n1802 | n3926) & (n1805 | n3927); - assign n2049 = n2026 & n2048 & (n1714 | n2028); - assign n2050 = (n1811 | n3926) & (n1814 | n3927); - assign n2051 = n2026 & n2050 & (n1706 | n2028); - assign n2052 = (n2051 | n3864) & (n2049 | n3867); - assign n2053 = n4177 & n4174 & (n1388 | n3925); - assign n2054 = n2052 & n2053 & (n2047 | n1322); - assign n2055 = (n1827 | n3926) & (n1830 | n3927); - assign n2056 = n2026 & n2055 & (n1712 | n2028); - assign n2057 = (n1837 | n3926) & (n1840 | n3927); - assign n2058 = n2026 & n2057 & (n1711 | n2028); - assign n2059 = (n1846 | n3926) & (n1849 | n3927); - assign n2060 = n2026 & n2059 & (n1704 | n2028); - assign n2061 = (n2060 | n3864) & (n2058 | n3867); - assign n2062 = n4175 & n4174 & (n1379 | n3925); - assign n2063 = n2061 & n2062 & (n2056 | n1322); - assign n2064 = (n1611 | n3937) & (n3805 | ~n3992); - assign n2065 = (n1669 | n3766) & (n1458 | n1671); - assign n2066 = ~Ni10 | n3768; - assign n2067 = n2064 & n2065 & (n2066 | ~n4773); - assign n2068 = (n1449 | Ni11) & (n1447 | ~n1543); - assign n2069 = (n1945 | n3897) & (~n1543 | ~n3989); - assign n2070 = Ni11 | ~Ni10; - assign n2071 = n2069 & (n1719 | n2070); - assign n2072 = Ni7 & n2398; - assign n2073 = n2398 & ~Ni7; - assign n2074 = Ni9 | Ni8; - assign n2075 = ~n2068 & (n2072 | (n2073 & n2074)); - assign n2076 = ~n3896 | n2067 | n3707; - assign n2077 = ~n2075 & (n2071 | ~n2073 | n2074); - assign n2078 = ~Ni32 & ~Ni30; - assign n2079 = ~n18 | n1539; - assign n2080 = ~Ni34 | ~Ni33; - assign n2081 = ~n792 & (n2079 | n2080); - assign n2082 = (~Ni34 | n821) & n2081; - assign n2083 = (~Ni34 | n857) & n2081; - assign n2084 = (~Ni34 | n895) & n2081; - assign n2085 = ~Ni34 | ~n793; - assign n2086 = (n2082 | n1408) & (n2083 | n914); - assign n2087 = n2085 & n2086 & (n2084 | n1702); - assign n2088 = (~Ni34 | n922) & n2081; - assign n2089 = (~Ni34 | n947) & n2081; - assign n2090 = (~Ni34 | n974) & n2081; - assign n2091 = (n2088 | n1408) & (n2089 | n914); - assign n2092 = n2085 & n2091 & (n2090 | n1702); - assign n2093 = (~Ni34 | n984) & n2081; - assign n2094 = (~Ni34 | n1001_1) & n2081; - assign n2095 = (~Ni34 | n882) & n2081; - assign n2096 = (n2093 | n1408) & (n2094 | n914); - assign n2097 = n2085 & n2096 & (n2095 | n1702); - assign n2098 = (~Ni34 | n1021_1) & n2081; - assign n2099 = (~Ni34 | n1028) & n2081; - assign n2100 = (~Ni34 | n966) & n2081; - assign n2101 = (n2098 | n1408) & (n2099 | n914); - assign n2102 = n2085 & n2101 & (n2100 | n1702); - assign n2103 = (~Ni34 | n1049) & n2081; - assign n2104 = (~Ni34 | n1065) & n2081; - assign n2105 = (~Ni34 | n1081_1) & n2081; - assign n2106 = (~Ni34 | n1108) & n2081; - assign n2107 = n2085 & (n2105 | n3893); - assign n2108 = (n2103 | n1408) & (n2104 | n914); - assign n2109 = ~Pi19 | n3859; - assign n2110 = n2107 & n2108 & (n2106 | n2109); - assign n2111 = (~Ni34 | n1135) & n2081; - assign n2112 = (~Ni34 | n1149) & n2081; - assign n2113 = (~Ni34 | n1165) & n2081; - assign n2114 = (~Ni34 | n1189) & n2081; - assign n2115 = n2085 & (n2113 | n3893); - assign n2116 = (n2111 | n1408) & (n2112 | n914); - assign n2117 = n2115 & n2116 & (n2114 | n2109); - assign n2118 = (~Ni34 | n1217) & n2081; - assign n2119 = (~Ni34 | n1228) & n2081; - assign n2120 = (~Ni34 | n1235) & n2081; - assign n2121 = (~Ni34 | n1247) & n2081; - assign n2122 = n2085 & (n2120 | n3893); - assign n2123 = (n2118 | n1408) & (n2119 | n914); - assign n2124 = n2122 & n2123 & (n2121 | n2109); - assign n2125 = (~Ni34 | n1259) & n2081; - assign n2126 = (~Ni34 | n1266) & n2081; - assign n2127 = (~Ni34 | n1273) & n2081; - assign n2128 = (~Ni34 | n1280) & n2081; - assign n2129 = n2085 & (n2127 | n3893); - assign n2130 = (n2125 | n1408) & (n2126 | n914); - assign n2131 = n2129 & n2130 & (n2128 | n2109); - assign n2132 = n2080 & (~Ni33 | ~n821); - assign n2133 = (n2132 | n3949) & (~n821 | n3951); - assign n2134 = (n821 & n4691) | (n4690 & (~n821 | n4691)); - assign n2135 = n2082 & n2133 & (~Pi25 | n2134); - assign n2136 = n2080 & (~Ni33 | ~n857); - assign n2137 = (n2136 | n3949) & (~n857 | n3951); - assign n2138 = (n857 & n4691) | (n4690 & (~n857 | n4691)); - assign n2139 = n2083 & n2137 & (~Pi25 | n2138); - assign n2140 = n2080 & (~Ni33 | ~n895); - assign n2141 = (n2140 | n3949) & (~n895 | n3951); - assign n2142 = (n895 & n4691) | (n4690 & (~n895 | n4691)); - assign n2143 = n2084 & n2141 & (~Pi25 | n2142); - assign n2144 = (n2135 | n1408) & (n2139 | n914); - assign n2145 = n2085 & n2144 & (n2143 | n1702); - assign n2146 = n2080 & (~Ni33 | ~n922); - assign n2147 = (n2146 | n3949) & (~n922 | n3951); - assign n2148 = (n922 & n4691) | (n4690 & (~n922 | n4691)); - assign n2149 = n2088 & n2147 & (~Pi25 | n2148); - assign n2150 = n2080 & (~Ni33 | ~n947); - assign n2151 = (n2150 | n3949) & (~n947 | n3951); - assign n2152 = (n947 & n4691) | (n4690 & (~n947 | n4691)); - assign n2153 = n2089 & n2151 & (~Pi25 | n2152); - assign n2154 = n2080 & (~Ni33 | ~n974); - assign n2155 = (n2154 | n3949) & (~n974 | n3951); - assign n2156 = (n974 & n4691) | (n4690 & (~n974 | n4691)); - assign n2157 = n2090 & n2155 & (~Pi25 | n2156); - assign n2158 = (n2149 | n1408) & (n2153 | n914); - assign n2159 = n2085 & n2158 & (n2157 | n1702); - assign n2160 = n2080 & (~Ni33 | ~n984); - assign n2161 = (n2160 | n3949) & (~n984 | n3951); - assign n2162 = (n984 & n4691) | (n4690 & (~n984 | n4691)); - assign n2163 = n2093 & n2161 & (~Pi25 | n2162); - assign n2164 = n2080 & (~Ni33 | ~n1001_1); - assign n2165 = (n2164 | n3949) & (~n1001_1 | n3951); - assign n2166 = (n1001_1 & n4691) | (n4690 & (~n1001_1 | n4691)); - assign n2167 = n2094 & n2165 & (~Pi25 | n2166); - assign n2168 = n2080 & (~Ni33 | ~n882); - assign n2169 = (n2168 | n3949) & (~n882 | n3951); - assign n2170 = (n882 & n4691) | (n4690 & (~n882 | n4691)); - assign n2171 = n2095 & n2169 & (~Pi25 | n2170); - assign n2172 = (n2163 | n1408) & (n2167 | n914); - assign n2173 = n2085 & n2172 & (n2171 | n1702); - assign n2174 = n2080 & (~Ni33 | ~n1021_1); - assign n2175 = (n2174 | n3949) & (~n1021_1 | n3951); - assign n2176 = (n1021_1 & n4691) | (n4690 & (~n1021_1 | n4691)); - assign n2177 = n2098 & n2175 & (~Pi25 | n2176); - assign n2178 = n2080 & (~Ni33 | ~n1028); - assign n2179 = (n2178 | n3949) & (~n1028 | n3951); - assign n2180 = (n1028 & n4691) | (n4690 & (~n1028 | n4691)); - assign n2181 = n2099 & n2179 & (~Pi25 | n2180); - assign n2182 = n2080 & (~Ni33 | ~n966); - assign n2183 = (n2182 | n3949) & (~n966 | n3951); - assign n2184 = (n966 & n4691) | (n4690 & (~n966 | n4691)); - assign n2185 = n2100 & n2183 & (~Pi25 | n2184); - assign n2186 = (n2177 | n1408) & (n2181 | n914); - assign n2187 = n2085 & n2186 & (n2185 | n1702); - assign n2188 = n2080 & (~Ni33 | ~n1049); - assign n2189 = (n2188 | n3949) & (~n1049 | n3951); - assign n2190 = (n1049 & n4691) | (n4690 & (~n1049 | n4691)); - assign n2191 = n2103 & n2189 & (~Pi25 | n2190); - assign n2192 = n2080 & (~Ni33 | ~n1065); - assign n2193 = (n2192 | n3949) & (~n1065 | n3951); - assign n2194 = (n1065 & n4691) | (n4690 & (~n1065 | n4691)); - assign n2195 = n2104 & n2193 & (~Pi25 | n2194); - assign n2196 = n2080 & (~Ni33 | ~n1081_1); - assign n2197 = n2080 & (~Ni33 | ~n1108); - assign n2198 = (n2197 | n3949) & (~n1108 | n3951); - assign n2199 = (n1108 & n4691) | (n4690 & (~n1108 | n4691)); - assign n2200 = n2106 & n2198 & (~Pi25 | n2199); - assign n2201 = n2085 & (n3893 | (n4309 & n4308)); - assign n2202 = (n2191 | n1408) & (n2195 | n914); - assign n2203 = n2201 & n2202 & (n2200 | n2109); - assign n2204 = n2080 & (~Ni33 | ~n1135); - assign n2205 = (n2204 | n3949) & (~n1135 | n3951); - assign n2206 = (n1135 & n4691) | (n4690 & (~n1135 | n4691)); - assign n2207 = n2111 & n2205 & (~Pi25 | n2206); - assign n2208 = n2080 & (~Ni33 | ~n1149); - assign n2209 = (n2208 | n3949) & (~n1149 | n3951); - assign n2210 = (n1149 & n4691) | (n4690 & (~n1149 | n4691)); - assign n2211 = n2112 & n2209 & (~Pi25 | n2210); - assign n2212 = n2080 & (~Ni33 | ~n1165); - assign n2213 = n2080 & (~Ni33 | ~n1189); - assign n2214 = (n2213 | n3949) & (~n1189 | n3951); - assign n2215 = (n1189 & n4691) | (n4690 & (~n1189 | n4691)); - assign n2216 = n2114 & n2214 & (~Pi25 | n2215); - assign n2217 = n2085 & (n3893 | (n4313 & n4312)); - assign n2218 = (n2207 | n1408) & (n2211 | n914); - assign n2219 = n2217 & n2218 & (n2216 | n2109); - assign n2220 = n2080 & (~Ni33 | ~n1217); - assign n2221 = (n2220 | n3949) & (~n1217 | n3951); - assign n2222 = (n1217 & n4691) | (n4690 & (~n1217 | n4691)); - assign n2223 = n2118 & n2221 & (~Pi25 | n2222); - assign n2224 = n2080 & (~Ni33 | ~n1228); - assign n2225 = (n2224 | n3949) & (~n1228 | n3951); - assign n2226 = (n1228 & n4691) | (n4690 & (~n1228 | n4691)); - assign n2227 = n2119 & n2225 & (~Pi25 | n2226); - assign n2228 = n2080 & (~Ni33 | ~n1235); - assign n2229 = n2080 & (~Ni33 | ~n1247); - assign n2230 = (n2229 | n3949) & (~n1247 | n3951); - assign n2231 = (n1247 & n4691) | (n4690 & (~n1247 | n4691)); - assign n2232 = n2121 & n2230 & (~Pi25 | n2231); - assign n2233 = n2085 & (n3893 | (n4311 & n4310)); - assign n2234 = (n2223 | n1408) & (n2227 | n914); - assign n2235 = n2233 & n2234 & (n2232 | n2109); - assign n2236 = n2080 & (~Ni33 | ~n1259); - assign n2237 = (n2236 | n3949) & (~n1259 | n3951); - assign n2238 = (n1259 & n4691) | (n4690 & (~n1259 | n4691)); - assign n2239 = n2125 & n2237 & (~Pi25 | n2238); - assign n2240 = n2080 & (~Ni33 | ~n1266); - assign n2241 = (n2240 | n3949) & (~n1266 | n3951); - assign n2242 = (n1266 & n4691) | (n4690 & (~n1266 | n4691)); - assign n2243 = n2126 & n2241 & (~Pi25 | n2242); - assign n2244 = n2080 & (~Ni33 | ~n1273); - assign n2245 = n2080 & (~Ni33 | ~n1280); - assign n2246 = (n2245 | n3949) & (~n1280 | n3951); - assign n2247 = (n1280 & n4691) | (n4690 & (~n1280 | n4691)); - assign n2248 = n2128 & n2246 & (~Pi25 | n2247); - assign n2249 = n2085 & (n3893 | (n4315 & n4314)); - assign n2250 = (n2239 | n1408) & (n2243 | n914); - assign n2251 = n2249 & n2250 & (n2248 | n2109); - assign n2252 = ~n792 & n2085; - assign n2253 = (n882 | n3954) & (n2168 | n3952); - assign n2254 = ~Pi22 | ~Pi21; - assign n2255 = n2252 & n2253 & (n2170 | n2254); - assign n2256 = (n966 | n3954) & (n2182 | n3952); - assign n2257 = n2252 & n2256 & (n2184 | n2254); - assign n2258 = (n1228 | n3954) & (n2224 | n3952); - assign n2259 = n2252 & n2258 & (n2226 | n2254); - assign n2260 = (n1247 | n3954) & (n2229 | n3952); - assign n2261 = n2252 & n2260 & (n2231 | n2254); - assign n2262 = (n1001_1 | n3954) & (n2164 | n3952); - assign n2263 = n2252 & n2262 & (n2166 | n2254); - assign n2264 = (n1266 | n3954) & (n2240 | n3952); - assign n2265 = n2252 & n2264 & (n2242 | n2254); - assign n2266 = (n1280 | n3954) & (n2245 | n3952); - assign n2267 = n2252 & n2266 & (n2247 | n2254); - assign n2268 = (n1028 | n3954) & (n2178 | n3952); - assign n2269 = n2252 & n2268 & (n2180 | n2254); - assign n2270 = (n2263 | n3894) & (n2269 | n3740); - assign n2271 = n4370 & (n2267 | n3737); - assign n2272 = Pi16 | n3867; - assign n2273 = n2270 & n2271 & (n2259 | n2272); - assign n2274 = (n1217 | n3954) & (n2220 | n3952); - assign n2275 = n2252 & n2274 & (n2222 | n2254); - assign n2276 = (n1235 | n3954) & (n2228 | n3952); - assign n2277 = (n1235 & n4691) | (n4690 & (~n1235 | n4691)); - assign n2278 = n2252 & n2276 & (n2277 | n2254); - assign n2279 = (n984 | n3954) & (n2160 | n3952); - assign n2280 = n2252 & n2279 & (n2162 | n2254); - assign n2281 = (n1259 | n3954) & (n2236 | n3952); - assign n2282 = n2252 & n2281 & (n2238 | n2254); - assign n2283 = (n1273 | n3954) & (n2244 | n3952); - assign n2284 = (n1273 & n4691) | (n4690 & (~n1273 | n4691)); - assign n2285 = n2252 & n2283 & (n2284 | n2254); - assign n2286 = (n1021_1 | n3954) & (n2174 | n3952); - assign n2287 = n2252 & n2286 & (n2176 | n2254); - assign n2288 = (n2280 | n3894) & (n2287 | n3740); - assign n2289 = n4369 & (n2285 | n3737); - assign n2290 = n2288 & n2289 & (n2275 | n2272); - assign n2291 = (n895 | n3954) & (n2140 | n3952); - assign n2292 = n2252 & n2291 & (n2142 | n2254); - assign n2293 = (n974 | n3954) & (n2154 | n3952); - assign n2294 = n2252 & n2293 & (n2156 | n2254); - assign n2295 = (n1065 | n3954) & (n2192 | n3952); - assign n2296 = n2252 & n2295 & (n2194 | n2254); - assign n2297 = (n1108 | n3954) & (n2197 | n3952); - assign n2298 = n2252 & n2297 & (n2199 | n2254); - assign n2299 = (n857 | n3954) & (n2136 | n3952); - assign n2300 = n2252 & n2299 & (n2138 | n2254); - assign n2301 = (n1149 | n3954) & (n2208 | n3952); - assign n2302 = n2252 & n2301 & (n2210 | n2254); - assign n2303 = (n1189 | n3954) & (n2213 | n3952); - assign n2304 = n2252 & n2303 & (n2215 | n2254); - assign n2305 = (n947 | n3954) & (n2150 | n3952); - assign n2306 = n2252 & n2305 & (n2152 | n2254); - assign n2307 = (n2300 | n3894) & (n2306 | n3740); - assign n2308 = n4367 & (n2304 | n3737); - assign n2309 = n2307 & n2308 & (n2296 | n2272); - assign n2310 = (n1049 | n3954) & (n2188 | n3952); - assign n2311 = n2252 & n2310 & (n2190 | n2254); - assign n2312 = (n1081_1 | n3954) & (n2196 | n3952); - assign n2313 = (n1081_1 & n4691) | (n4690 & (~n1081_1 | n4691)); - assign n2314 = n2252 & n2312 & (n2313 | n2254); - assign n2315 = (n821 | n3954) & (n2132 | n3952); - assign n2316 = n2252 & n2315 & (n2134 | n2254); - assign n2317 = (n1135 | n3954) & (n2204 | n3952); - assign n2318 = n2252 & n2317 & (n2206 | n2254); - assign n2319 = (n1165 | n3954) & (n2212 | n3952); - assign n2320 = (n1165 & n4691) | (n4690 & (~n1165 | n4691)); - assign n2321 = n2252 & n2319 & (n2320 | n2254); - assign n2322 = (n922 | n3954) & (n2146 | n3952); - assign n2323 = n2252 & n2322 & (n2148 | n2254); - assign n2324 = (n2316 | n3894) & (n2323 | n3740); - assign n2325 = n4366 & (n2321 | n3737); - assign n2326 = n2324 & n2325 & (n2311 | n2272); - assign n2327 = ~Ni34 & (~n882 | n1539); - assign n2328 = ~Ni34 & (~n966 | n1539); - assign n2329 = ~Ni34 & (~n1228 | n1539); - assign n2330 = ~Ni34 & (~n1247 | n1539); - assign n2331 = ~Ni34 & (~n1001_1 | n1539); - assign n2332 = ~Ni34 & (~n1266 | n1539); - assign n2333 = ~Ni34 & (~n1280 | n1539); - assign n2334 = ~Ni34 & (~n1028 | n1539); - assign n2335 = ~n3894 & (~n3955 | ~n4355); - assign n2336 = ~n3743 & (~n3955 | ~n4359); - assign n2337 = ~Ni34 & (~n1217 | n1539); - assign n2338 = ~Ni34 & (~n1235 | n1539); - assign n2339 = ~Ni34 & (~n984 | n1539); - assign n2340 = ~Ni34 & (~n1259 | n1539); - assign n2341 = ~Ni34 & (~n1273 | n1539); - assign n2342 = ~Ni34 & (~n1021_1 | n1539); - assign n2343 = ~n3894 & (~n3955 | ~n4345); - assign n2344 = ~n3743 & (~n3955 | ~n4349); - assign n2345 = n3184 & Pi16; - assign n2346 = n2345 & (~n3955 | ~n4344); - assign n2347 = ~Ni34 & (~n895 | n1539); - assign n2348 = ~Ni34 & (~n974 | n1539); - assign n2349 = ~Ni34 & (~n1065 | n1539); - assign n2350 = ~Ni34 & (~n1108 | n1539); - assign n2351 = ~Ni34 & (~n857 | n1539); - assign n2352 = ~Ni34 & (~n1149 | n1539); - assign n2353 = ~Ni34 & (~n1189 | n1539); - assign n2354 = ~Ni34 & (~n947 | n1539); - assign n2355 = ~n3894 & (~n3955 | ~n4332); - assign n2356 = ~n3743 & (~n3955 | ~n4336); - assign n2357 = ~Ni34 & (~n1049 | n1539); - assign n2358 = ~Ni34 & (~n1081_1 | n1539); - assign n2359 = ~Ni34 & (~n821 | n1539); - assign n2360 = ~Ni34 & (~n1135 | n1539); - assign n2361 = ~Ni34 & (~n1165 | n1539); - assign n2362 = ~Ni34 & (~n922 | n1539); - assign n2363 = ~n3894 & (~n3955 | ~n4322); - assign n2364 = ~n3743 & (~n3955 | ~n4326); - assign n2365 = n2345 & (~n3955 | ~n4321); - assign n2366 = n4371 & (n3944 | (n4368 & n4372)); - assign n2367 = ~Pi15 | n3327; - assign n2368 = (n2255 | ~n3772) & (n2257 | ~n2345); - assign n2369 = (~Pi20 & n2290) | (n2273 & (Pi20 | n2290)); - assign n2370 = n2366 & (n2367 | (n2368 & n2369)); - assign n2371 = (~Ni34 | n1919) & n2085; - assign n2372 = ~Pi25 | n3857; - assign n2373 = (n2338 | n2372) & (n2330 | n1314); - assign n2374 = (n2337 | n2372) & (n2329 | n1314); - assign n2375 = (n2339 | n2372) & (n2331 | n1314); - assign n2376 = (n2341 | n2372) & (n2333 | n1314); - assign n2377 = (n2340 | n2372) & (n2332 | n1314); - assign n2378 = (n2342 | n2372) & (n2334 | n1314); - assign n2379 = ~n1923 & ~n2328 & (Pi16 | ~n2327); - assign n2380 = (n2358 | n2372) & (n2350 | n1314); - assign n2381 = (n2357 | n2372) & (n2349 | n1314); - assign n2382 = (n2359 | n2372) & (n2351 | n1314); - assign n2383 = (n2361 | n2372) & (n2353 | n1314); - assign n2384 = (n2360 | n2372) & (n2352 | n1314); - assign n2385 = (n2362 | n2372) & (n2354 | n1314); - assign n2386 = ~n1923 & ~n2348 & (Pi16 | ~n2347); - assign n2387 = ~n4689 & (~Pi15 | ~n4305 | ~n4307); - assign n2388 = ~n3659 & (~n3994 | (n2387 & ~n3892)); - assign n2389 = ~Ni35 | Ni30; - assign n2390 = n1241 & n2389 & (~Ni35 | n1353); - assign n2391 = Ni32 | n3958; - assign n2392 = n2390 & (~Pi26 | n2391); - assign n2393 = n1543 | n3727; - assign n2394 = Ni35 & (n2393 | ~n3807); - assign n2395 = ~n2072 & (~n2073 | ~n2403); - assign n2396 = ~n2395 & (n2394 | (~n2392 & ~n2393)); - assign n2397 = ~n2073 | n2403 | n4702 | n4703; - assign n2398 = ~n3707 & ~n3896; - assign n2399 = ~Ni31 | ~Ni36; - assign n2400 = n891 & n2399 & (Ni30 | ~Ni36); - assign n2401 = (~Pi27 | n2391) & n2400; - assign n2402 = ~n4706 & (Ni36 | ~n2393); - assign n2403 = Ni8 | n3957; - assign n2404 = n2402 & (n2072 | (n2073 & n2403)); - assign n2405 = ~n2073 | n2403 | n4704 | n4705; - assign n2406 = ~Ni31 & Ni30; - assign n2407 = ~n4708 & ~Ni32 & n2406; - assign n2408 = ~Ni30 & (~n814 | (Ni37 & ~n4708)); - assign n2409 = ~Pi20 | n3961 | n3962; - assign n2410 = Pi20 | n3959 | n3962; - assign n2411 = Pi20 | n3959 | n3960; - assign n2412 = ~Pi20 | n3960 | n3961; - assign n2413 = n2412 & n2411 & n2409 & n2410; - assign n2414 = n1216 | (n784 & Ni30); - assign n2415 = ~n784 & ((Ni37 & n654) | ~n814); - assign n2416 = ~Ni31 | Ni30; - assign n2417 = Ni45 & (Ni32 | n2416); - assign n2418 = ~Ni6 | Ni5; - assign n2419 = ~Ni32 | Ni30; - assign n2420 = Ni30 | Ni31; - assign n2421 = Pi21 | ~Ni32; - assign n2422 = Pi22 | n3812; - assign n2423 = n2421 & (~Pi21 | n2422); - assign n2424 = n2419 & (~n803 | n2420); - assign n2425 = ~Ni45 & (Ni47 | ~Ni43); - assign n2426 = Ni41 | Ni42; - assign n2427 = n2425 & (Ni47 | n2426 | ~n3331); - assign n2428 = n2425 & n2451; - assign n2429 = n2518 | Ni40; - assign n2430 = ~Ni37 | Ni47 | Ni38; - assign n2431 = n3811 | n3854; - assign n2432 = n2431 & n2430 & n2428 & n2429; - assign n2433 = Ni38 | n3811; - assign n2434 = ~Ni35 | Ni36; - assign n2435 = n2432 & (n2433 | n2434); - assign n2436 = n2419 & (~n804 | ~n2435); - assign n2437 = n2419 & (n2420 | ~n2435); - assign n2438 = ~n18 | n784; - assign n2439 = n784 & n2437; - assign n2440 = n2438 & (n18 | n2439); - assign n2441 = ~Ni44 & ~Ni43; - assign n2442 = n2425 & (Ni47 | n2441 | n2426); - assign n2443 = n2523 | Ni40; - assign n2444 = n3811 | n3855; - assign n2445 = n2444 & n2430 & n2428 & n2443; - assign n2446 = n2445 & (n2433 | n2434); - assign n2447 = n2419 & (~n804 | ~n2446); - assign n2448 = n2419 & (n2420 | ~n2446); - assign n2449 = n784 & n2448; - assign n2450 = n2438 & (n18 | n2449); - assign n2451 = ~Ni41 | n3811; - assign n2452 = n2428 & n2433 & n2430; - assign n2453 = n2428 & n2430 & (Ni36 | n2452); - assign n2454 = n2419 & (~n804 | ~n2453); - assign n2455 = n2419 & (n2420 | ~n2453); - assign n2456 = n784 & n2455; - assign n2457 = n2438 & (n18 | n2456); - assign n2458 = (n2689 | n1702) & (n4404 | n1408); - assign n2459 = n2447 & n2450; - assign n2460 = n2423 & n2458 & (n2459 | n914); - assign n2461 = n2427 | Ni40; - assign n2462 = n2431 & n2430 & n2425 & n2461; - assign n2463 = n2462 & (n2433 | n2434); - assign n2464 = n2419 & (~n804 | ~n2463); - assign n2465 = n2419 & (n2420 | ~n2463); - assign n2466 = n784 & n2465; - assign n2467 = n2438 & (n18 | n2466); - assign n2468 = n2442 | Ni40; - assign n2469 = n2444 & n2430 & n2425 & n2468; - assign n2470 = n2469 & (n2433 | n2434); - assign n2471 = n2419 & (~n804 | ~n2470); - assign n2472 = n2419 & (n2420 | ~n2470); - assign n2473 = n784 & n2472; - assign n2474 = n2438 & (n18 | n2473); - assign n2475 = n2425 & n2433 & n2430; - assign n2476 = n2425 & n2430 & (Ni36 | n2475); - assign n2477 = n2419 & (~n804 | ~n2476); - assign n2478 = n2419 & (n2420 | ~n2476); - assign n2479 = n784 & n2478; - assign n2480 = n2438 & (n18 | n2479); - assign n2481 = (n2690 | n1702) & (n4405 | n1408); - assign n2482 = n2471 & n2474; - assign n2483 = n2423 & n2481 & (n2482 | n914); - assign n2484 = n2432 & (n2433 | ~n2530); - assign n2485 = n2419 & (~n804 | ~n2484); - assign n2486 = n2419 & (n2420 | ~n2484); - assign n2487 = n784 & n2486; - assign n2488 = n2438 & (n18 | n2487); - assign n2489 = n2445 & (n2433 | ~n2530); - assign n2490 = n2419 & (~n804 | ~n2489); - assign n2491 = n2419 & (n2420 | ~n2489); - assign n2492 = n784 & n2491; - assign n2493 = n2438 & (n18 | n2492); - assign n2494 = n2419 & (~n804 | ~n2452); - assign n2495 = n2419 & (n2420 | ~n2452); - assign n2496 = n784 & n2495; - assign n2497 = n2438 & (n18 | n2496); - assign n2498 = (n2666 | n1702) & (n4414 | n1408); - assign n2499 = n2490 & n2493; - assign n2500 = n2423 & n2498 & (n2499 | n914); - assign n2501 = n2462 & (n2433 | ~n2530); - assign n2502 = n2419 & (~n804 | ~n2501); - assign n2503 = n2419 & (n2420 | ~n2501); - assign n2504 = n784 & n2503; - assign n2505 = n2438 & (n18 | n2504); - assign n2506 = n2469 & (n2433 | ~n2530); - assign n2507 = n2419 & (~n804 | ~n2506); - assign n2508 = n2419 & (n2420 | ~n2506); - assign n2509 = n784 & n2508; - assign n2510 = n2438 & (n18 | n2509); - assign n2511 = n2419 & (~n804 | ~n2475); - assign n2512 = n2419 & (n2420 | ~n2475); - assign n2513 = n784 & n2512; - assign n2514 = n2438 & (n18 | n2513); - assign n2515 = (n2667 | n1702) & (n4415 | n1408); - assign n2516 = n2507 & n2510; - assign n2517 = n2423 & n2515 & (n2516 | n914); - assign n2518 = n2451 & n2427; - assign n2519 = n2419 & (~n804 | ~n3963); - assign n2520 = n2419 & (n2420 | ~n3963); - assign n2521 = n784 & n2520; - assign n2522 = n2438 & (n18 | n2521); - assign n2523 = n2451 & n2442; - assign n2524 = n2419 & (~n804 | ~n3964); - assign n2525 = n2419 & (n2420 | ~n3964); - assign n2526 = n784 & n2525; - assign n2527 = n2438 & (n18 | n2526); - assign n2528 = n2518 | ~Ni40; - assign n2529 = n2431 & n2430 & n2428 & n2528; - assign n2530 = Ni35 | Ni36; - assign n2531 = n2529 & (n2433 | n2530); - assign n2532 = n2419 & (~n804 | ~n2531); - assign n2533 = n2419 & (n2420 | ~n2531); - assign n2534 = n784 & n2533; - assign n2535 = n2438 & (n18 | n2534); - assign n2536 = n2523 | ~Ni40; - assign n2537 = n2444 & n2430 & n2428 & n2536; - assign n2538 = n2537 & (n2433 | n2530); - assign n2539 = n2419 & (~n804 | ~n2538); - assign n2540 = n2419 & (n2420 | ~n2538); - assign n2541 = n784 & n2540; - assign n2542 = n2438 & (n18 | n2541); - assign n2543 = (n4408 | n3893) & (n2718 | n2109); - assign n2544 = n2423 & (n2721 | n914); - assign n2545 = n2519 & n2522; - assign n2546 = n2543 & n2544 & (n2545 | n1408); - assign n2547 = n2419 & (~n804 | ~n3965); - assign n2548 = n2419 & (n2420 | ~n3965); - assign n2549 = n784 & n2548; - assign n2550 = n2438 & (n18 | n2549); - assign n2551 = n2419 & (~n804 | ~n3966); - assign n2552 = n2419 & (n2420 | ~n3966); - assign n2553 = n784 & n2552; - assign n2554 = n2438 & (n18 | n2553); - assign n2555 = n2427 | ~Ni40; - assign n2556 = n2431 & n2430 & n2425 & n2555; - assign n2557 = n2556 & (n2433 | n2530); - assign n2558 = n2419 & (~n804 | ~n2557); - assign n2559 = n2419 & (n2420 | ~n2557); - assign n2560 = n784 & n2559; - assign n2561 = n2438 & (n18 | n2560); - assign n2562 = n2442 | ~Ni40; - assign n2563 = n2444 & n2430 & n2425 & n2562; - assign n2564 = n2563 & (n2433 | n2530); - assign n2565 = n2419 & (~n804 | ~n2564); - assign n2566 = n2419 & (n2420 | ~n2564); - assign n2567 = n784 & n2566; - assign n2568 = n2438 & (n18 | n2567); - assign n2569 = (n4411 | n3893) & (n2706 | n2109); - assign n2570 = n2423 & (n2710 | n914); - assign n2571 = n2547 & n2550; - assign n2572 = n2569 & n2570 & (n2571 | n1408); - assign n2573 = ~n3963 | ~n4768; - assign n2574 = n2419 & (~n804 | n2573); - assign n2575 = n2419 & (n2420 | n2573); - assign n2576 = n784 & n2575; - assign n2577 = n2438 & (n18 | n2576); - assign n2578 = ~n3964 | ~n4768; - assign n2579 = n2419 & (~n804 | n2578); - assign n2580 = n2419 & (n2420 | n2578); - assign n2581 = n784 & n2580; - assign n2582 = n2438 & (n18 | n2581); - assign n2583 = n2529 & (n2433 | ~n2434); - assign n2584 = n2419 & (~n804 | ~n2583); - assign n2585 = n2419 & (n2420 | ~n2583); - assign n2586 = n784 & n2585; - assign n2587 = n2438 & (n18 | n2586); - assign n2588 = n2537 & (n2433 | ~n2434); - assign n2589 = n2419 & (~n804 | ~n2588); - assign n2590 = n2419 & (n2420 | ~n2588); - assign n2591 = n784 & n2590; - assign n2592 = n2438 & (n18 | n2591); - assign n2593 = (n4418 | n3893) & (n2740 | n2109); - assign n2594 = n2423 & (n2743 | n914); - assign n2595 = n2574 & n2577; - assign n2596 = n2593 & n2594 & (n2595 | n1408); - assign n2597 = ~n3965 | ~n4768; - assign n2598 = n2419 & (~n804 | n2597); - assign n2599 = n2419 & (n2420 | n2597); - assign n2600 = n784 & n2599; - assign n2601 = n2438 & (n18 | n2600); - assign n2602 = ~n3966 | ~n4768; - assign n2603 = n2419 & (~n804 | n2602); - assign n2604 = n2419 & (n2420 | n2602); - assign n2605 = n784 & n2604; - assign n2606 = n2438 & (n18 | n2605); - assign n2607 = n2556 & (n2433 | ~n2434); - assign n2608 = n2419 & (~n804 | ~n2607); - assign n2609 = n2419 & (n2420 | ~n2607); - assign n2610 = n784 & n2609; - assign n2611 = n2438 & (n18 | n2610); - assign n2612 = n2563 & (n2433 | ~n2434); - assign n2613 = n2419 & (~n804 | ~n2612); - assign n2614 = n2419 & (n2420 | ~n2612); - assign n2615 = n784 & n2614; - assign n2616 = n2438 & (n18 | n2615); - assign n2617 = (n4421 | n3893) & (n2729 | n2109); - assign n2618 = n2423 & (n2732 | n914); - assign n2619 = n2598 & n2601; - assign n2620 = n2617 & n2618 & (n2619 | n1408); - assign n2621 = n2641 & n2423; - assign n2622 = (n1448 | n2621) & (n1446 | ~n3998); - assign n2623 = n802 & (~Pi27 | ~Ni32) & n2419; - assign n2624 = n4709 & (Pi22 | ~Pi21 | n3821); - assign n2625 = (~Pi26 | n3037) & n3817; - assign n2626 = n2624 & (n2625 | n2254); - assign n2627 = n802 & n2419 & (Pi27 | ~Ni32); - assign n2628 = (n2627 & (~Pi21 | ~n3999)) | (Pi21 & ~n3999); - assign n2629 = n3813 & (Pi27 | n3037); - assign n2630 = n2628 & (n2629 | n2254); - assign n2631 = (n2621 | n1452) & (n2630 | n3696); - assign n2632 = ~Ni12 | n3912; - assign n2633 = n2622 & n2631 & (n2626 | n2632); - assign n2634 = ~n4711 & (Pi22 | ~Pi21 | n3826); - assign n2635 = n3817 & (Pi26 | n3037); - assign n2636 = n2634 & (n2635 | n2254); - assign n2637 = Pi21 & ~n2422 & (~Pi24 | ~n813); - assign n2638 = Pi21 | n3822; - assign n2639 = ~n2637 & (Pi24 | n2421) & n2638; - assign n2640 = n3825 | n2254; - assign n2641 = n3037 | n2254; - assign n2642 = n2640 & n2639 & (Pi24 | n2641); - assign n2643 = Pi22 | ~Pi21; - assign n2644 = n2640 & n2638 & (n813 | n2643); - assign n2645 = n3823 | n2643; - assign n2646 = n2649 & (~Pi27 | n3822); - assign n2647 = n3824 & (~Pi27 | n3825); - assign n2648 = n2645 & n2646 & (n2647 | n2254); - assign n2649 = n2419 & n801; - assign n2650 = (n2750 | ~n4005) & (n3912 | ~n4006); - assign n2651 = n2650 & (n2642 | ~Ni13); - assign n2652 = n812 & n2494 & (n18 | n2495); - assign n2653 = n812 & n2511 & (n18 | n2512); - assign n2654 = n812 & n2584 & (n18 | n2585); - assign n2655 = n812 & n2589 & (n18 | n2590); - assign n2656 = n812 & n2574 & (n18 | n2575); - assign n2657 = n812 & n2579 & (n18 | n2580); - assign n2658 = n812 & n2485 & (n18 | n2486); - assign n2659 = n812 & n2490 & (n18 | n2491); - assign n2660 = n812 & n2608 & (n18 | n2609); - assign n2661 = n812 & n2613 & (n18 | n2614); - assign n2662 = n812 & n2598 & (n18 | n2599); - assign n2663 = n812 & n2603 & (n18 | n2604); - assign n2664 = n812 & n2502 & (n18 | n2503); - assign n2665 = n812 & n2507 & (n18 | n2508); - assign n2666 = n2494 & n2497; - assign n2667 = n2511 & n2514; - assign n2668 = (n2666 | n1495) & (n2667 | n1497); - assign n2669 = ~n3740 & (~n4553 | ~n4554); - assign n2670 = ~n2272 & (~n4555 | ~n4556); - assign n2671 = n2639 & (n3737 | (n4562 & n4561)); - assign n2672 = n4565 & (n3743 | (n4560 & n4559)); - assign n2673 = n4563 & n4564 & (Pi24 | n2668); - assign n2674 = n2673 & n2671 & n2672; - assign n2675 = n812 & n2454 & (n18 | n2455); - assign n2676 = n812 & n2477 & (n18 | n2478); - assign n2677 = n812 & n2532 & (n18 | n2533); - assign n2678 = n812 & n2539 & (n18 | n2540); - assign n2679 = n812 & n2519 & (n18 | n2520); - assign n2680 = n812 & n2524 & (n18 | n2525); - assign n2681 = n812 & n2436 & (n18 | n2437); - assign n2682 = n812 & n2447 & (n18 | n2448); - assign n2683 = n812 & n2558 & (n18 | n2559); - assign n2684 = n812 & n2565 & (n18 | n2566); - assign n2685 = n812 & n2547 & (n18 | n2548); - assign n2686 = n812 & n2551 & (n18 | n2552); - assign n2687 = n812 & n2464 & (n18 | n2465); - assign n2688 = n812 & n2471 & (n18 | n2472); - assign n2689 = n2454 & n2457; - assign n2690 = n2477 & n2480; - assign n2691 = (n2689 | n1495) & (n2690 | n1497); - assign n2692 = ~n3740 & (~n4535 | ~n4536); - assign n2693 = ~n2272 & (~n4537 | ~n4538); - assign n2694 = ~n3944 & (~n4547 | ~n4549 | ~n4550); - assign n2695 = ~n2694 & (n2642 | (n1448 & n1542)); - assign n2696 = (n2651 | n3919) & (n3677 | ~n4007); - assign n2697 = n2695 & n2696 & (n2674 | n2367); - assign n2698 = Pi21 & ~n2422 & (n788 | ~n813); - assign n2699 = n2638 & (~n788 | n2421) & ~n2698; - assign n2700 = n2640 & n2699 & (~n788 | n2641); - assign n2701 = ~n2643 & (~n4508 | (Pi24 & ~n3821)); - assign n2702 = ~n2254 & (~n4509 | (Pi24 & ~n2625)); - assign n2703 = ~Pi21 & (~n4510 | (Pi24 & ~n3818)); - assign n2704 = n1542 & (n1543 | ~n2750); - assign n2705 = n4523 & (n4411 | n3936); - assign n2706 = n2565 & n2568; - assign n2707 = ~n788 | n3859; - assign n2708 = n2699 & n2705 & (n2706 | n2707); - assign n2709 = n4522 & (n2571 | n3936); - assign n2710 = n2551 & n2554; - assign n2711 = n2699 & n2709 & (n2710 | n2707); - assign n2712 = n4521 & (n4405 | n3936); - assign n2713 = n2699 & n2712 & (n2482 | n2707); - assign n2714 = (n2713 | n3864) & (n2711 | n3867); - assign n2715 = n4524 & (n2690 | n3934); - assign n2716 = n2714 & n2715 & (n2708 | n1322); - assign n2717 = n4514 & (n4408 | n3936); - assign n2718 = n2539 & n2542; - assign n2719 = n2699 & n2717 & (n2718 | n2707); - assign n2720 = n4513 & (n2545 | n3936); - assign n2721 = n2524 & n2527; - assign n2722 = n2699 & n2720 & (n2721 | n2707); - assign n2723 = n4512 & (n4404 | n3936); - assign n2724 = n2699 & n2723 & (n2459 | n2707); - assign n2725 = (n2724 | n3864) & (n2722 | n3867); - assign n2726 = n4516 & (n2689 | n3934); - assign n2727 = n2725 & n2726 & (n2719 | n1322); - assign n2728 = n4527 & (n4421 | n3936); - assign n2729 = n2613 & n2616; - assign n2730 = n2699 & n2728 & (n2729 | n2707); - assign n2731 = n4526 & (n2619 | n3936); - assign n2732 = n2603 & n2606; - assign n2733 = n2699 & n2731 & (n2732 | n2707); - assign n2734 = n4525 & (n4415 | n3936); - assign n2735 = n2699 & n2734 & (n2516 | n2707); - assign n2736 = (n2735 | n3864) & (n2733 | n3867); - assign n2737 = n4528 & n4515 & (n2667 | n3934); - assign n2738 = n2736 & n2737 & (n2730 | n1322); - assign n2739 = n4519 & (n4418 | n3936); - assign n2740 = n2589 & n2592; - assign n2741 = n2699 & n2739 & (n2740 | n2707); - assign n2742 = n4518 & (n2595 | n3936); - assign n2743 = n2579 & n2582; - assign n2744 = n2699 & n2742 & (n2743 | n2707); - assign n2745 = n4517 & (n4414 | n3936); - assign n2746 = n2699 & n2745 & (n2499 | n2707); - assign n2747 = (n2746 | n3864) & (n2744 | n3867); - assign n2748 = n4520 & (n2666 | n3934); - assign n2749 = n2747 & n2748 & (n2741 | n1322); - assign n2750 = ~Ni14 | Ni13; - assign n2751 = n1545 & ~n2700 & (~n2636 | n2750); - assign n2752 = ~n3919 & (~n4511 | (~n2700 & Ni13)); - assign n2753 = Pi21 & ~n2422 & (n795 | ~n813); - assign n2754 = n2638 & (~n795 | n2421) & ~n2753; - assign n2755 = n2640 & n2754 & (~n795 | n2641); - assign n2756 = n4578 & (n4411 | n3948); - assign n2757 = ~n795 | n3859; - assign n2758 = n2754 & n2756 & (n2706 | n2757); - assign n2759 = n4577 & (n2571 | n3948); - assign n2760 = n2754 & n2759 & (n2710 | n2757); - assign n2761 = n4576 & (n4405 | n3948); - assign n2762 = n2754 & n2761 & (n2482 | n2757); - assign n2763 = (n2762 | n3864) & (n2760 | n3867); - assign n2764 = n4579 & (n2690 | n3946); - assign n2765 = n2763 & n2764 & (n2758 | n1322); - assign n2766 = n4569 & (n4408 | n3948); - assign n2767 = n2754 & n2766 & (n2718 | n2757); - assign n2768 = n4568 & (n2545 | n3948); - assign n2769 = n2754 & n2768 & (n2721 | n2757); - assign n2770 = n4567 & (n4404 | n3948); - assign n2771 = n2754 & n2770 & (n2459 | n2757); - assign n2772 = (n2771 | n3864) & (n2769 | n3867); - assign n2773 = n4571 & (n2689 | n3946); - assign n2774 = n2772 & n2773 & (n2767 | n1322); - assign n2775 = n4582 & (n4421 | n3948); - assign n2776 = n2754 & n2775 & (n2729 | n2757); - assign n2777 = n4581 & (n2619 | n3948); - assign n2778 = n2754 & n2777 & (n2732 | n2757); - assign n2779 = n4580 & (n4415 | n3948); - assign n2780 = n2754 & n2779 & (n2516 | n2757); - assign n2781 = (n2780 | n3864) & (n2778 | n3867); - assign n2782 = n4583 & n4570 & (n2667 | n3946); - assign n2783 = n2781 & n2782 & (n2776 | n1322); - assign n2784 = n4574 & (n4418 | n3948); - assign n2785 = n2754 & n2784 & (n2740 | n2757); - assign n2786 = n4573 & (n2595 | n3948); - assign n2787 = n2754 & n2786 & (n2743 | n2757); - assign n2788 = n4572 & (n4414 | n3948); - assign n2789 = n2754 & n2788 & (n2499 | n2757); - assign n2790 = (n2789 | n3864) & (n2787 | n3867); - assign n2791 = n4575 & (n2666 | n3946); - assign n2792 = n2790 & n2791 & (n2785 | n1322); - assign n2793 = n1545 & ~n2755 & (~n2636 | n2750); - assign n2794 = ~n3919 & ((Ni13 & ~n2755) | ~n4566); - assign n2795 = n2419 & (~n805 | ~n2435); - assign n2796 = n2419 & (~n805 | ~n2446); - assign n2797 = n2419 & (~n805 | ~n2453); - assign n2798 = (n4398 | n1702) & (n2918 | n1408); - assign n2799 = n2796 & n2450; - assign n2800 = n2423 & n2798 & (n2799 | n914); - assign n2801 = n2419 & (~n805 | ~n2463); - assign n2802 = n2419 & (~n805 | ~n2470); - assign n2803 = n2419 & (~n805 | ~n2476); - assign n2804 = (n4400 | n1702) & (n2890 | n1408); - assign n2805 = n2802 & n2474; - assign n2806 = n2423 & n2804 & (n2805 | n914); - assign n2807 = n2419 & (~n805 | ~n2484); - assign n2808 = n2419 & (~n805 | ~n2489); - assign n2809 = n2419 & (~n805 | ~n2452); - assign n2810 = (n4399 | n1702) & (n2974 | n1408); - assign n2811 = n2808 & n2493; - assign n2812 = n2423 & n2810 & (n2811 | n914); - assign n2813 = n2419 & (~n805 | ~n2501); - assign n2814 = n2419 & (~n805 | ~n2506); - assign n2815 = n2419 & (~n805 | ~n2475); - assign n2816 = (n4401 | n1702) & (n2946 | n1408); - assign n2817 = n2814 & n2510; - assign n2818 = n2423 & n2816 & (n2817 | n914); - assign n2819 = n2419 & (~n805 | ~n3963); - assign n2820 = n2419 & (~n805 | ~n3964); - assign n2821 = n2419 & (~n805 | ~n2531); - assign n2822 = n2419 & (~n805 | ~n2538); - assign n2823 = (n2903 | n3893) & (n4388 | n2109); - assign n2824 = n2423 & (n4389 | n914); - assign n2825 = n2819 & n2522; - assign n2826 = n2823 & n2824 & (n2825 | n1408); - assign n2827 = n2419 & (~n805 | ~n3965); - assign n2828 = n2419 & (~n805 | ~n3966); - assign n2829 = n2419 & (~n805 | ~n2557); - assign n2830 = n2419 & (~n805 | ~n2564); - assign n2831 = (n2875 | n3893) & (n4392 | n2109); - assign n2832 = n2423 & (n4393 | n914); - assign n2833 = n2827 & n2550; - assign n2834 = n2831 & n2832 & (n2833 | n1408); - assign n2835 = n2419 & (~n805 | n2573); - assign n2836 = n2419 & (~n805 | n2578); - assign n2837 = n2419 & (~n805 | ~n2583); - assign n2838 = n2419 & (~n805 | ~n2588); - assign n2839 = (n2959 | n3893) & (n4390 | n2109); - assign n2840 = n2423 & (n4391 | n914); - assign n2841 = n2835 & n2577; - assign n2842 = n2839 & n2840 & (n2841 | n1408); - assign n2843 = n2419 & (~n805 | n2597); - assign n2844 = n2419 & (~n805 | n2602); - assign n2845 = n2419 & (~n805 | ~n2607); - assign n2846 = n2419 & (~n805 | ~n2612); - assign n2847 = (n2931 | n3893) & (n4394 | n2109); - assign n2848 = n2423 & (n4395 | n914); - assign n2849 = n2843 & n2601; - assign n2850 = n2847 & n2848 & (n2849 | n1408); - assign n2851 = (Pi20 & n2449) | (n2439 & (~Pi20 | n2449)); - assign n2852 = (n2851 | n1701) & (n2456 | n1702); - assign n2853 = (Pi20 & n2473) | (n2466 & (~Pi20 | n2473)); - assign n2854 = (n2853 | n1701) & (n2479 | n1702); - assign n2855 = (Pi20 & n2509) | (n2504 & (~Pi20 | n2509)); - assign n2856 = (n2855 | n1701) & (n2513 | n1702); - assign n2857 = (Pi20 & n2526) | (n2521 & (~Pi20 | n2526)); - assign n2858 = (Pi20 & n2541) | (n2534 & (~Pi20 | n2541)); - assign n2859 = (n2857 | n1701) & (n2858 | n1702); - assign n2860 = (Pi20 & n2553) | (n2549 & (~Pi20 | n2553)); - assign n2861 = (Pi20 & n2567) | (n2560 & (~Pi20 | n2567)); - assign n2862 = (n2860 | n1701) & (n2861 | n1702); - assign n2863 = (Pi20 & n2605) | (n2600 & (~Pi20 | n2605)); - assign n2864 = (Pi20 & n2615) | (n2610 & (~Pi20 | n2615)); - assign n2865 = (n2863 | n1701) & (n2864 | n1702); - assign n2866 = n1446 | n4721 | n4722; - assign n2867 = ~n4720 & (Pi17 | (n4396 & n4397)); - assign n2868 = n2866 & (n2867 | n1448); - assign n2869 = n802 & n2559; - assign n2870 = n802 & n2829 & (n18 | n2869); - assign n2871 = n802 & n2566; - assign n2872 = n802 & n2830 & (n18 | n2871); - assign n2873 = (n2870 | n3915) & (n2872 | n3916); - assign n2874 = n2624 & (n4392 | n3917); - assign n2875 = n2829 & n2561; - assign n2876 = n2873 & n2874 & (n2875 | n1729); - assign n2877 = n802 & n2548; - assign n2878 = n802 & n2827 & (n18 | n2877); - assign n2879 = n802 & n2552; - assign n2880 = n802 & n2828 & (n18 | n2879); - assign n2881 = (n2878 | n3915) & (n2880 | n3916); - assign n2882 = n2624 & (n4393 | n3917); - assign n2883 = n2881 & n2882 & (n2833 | n1729); - assign n2884 = n802 & n2465; - assign n2885 = n802 & n2801 & (n18 | n2884); - assign n2886 = n802 & n2472; - assign n2887 = n802 & n2802 & (n18 | n2886); - assign n2888 = (n2885 | n3915) & (n2887 | n3916); - assign n2889 = n2624 & (n2805 | n3917); - assign n2890 = n2801 & n2467; - assign n2891 = n2888 & n2889 & (n2890 | n1729); - assign n2892 = n802 & n2478; - assign n2893 = n802 & n2803 & (n18 | n2892); - assign n2894 = (n2891 | n3864) & (n2883 | n3867); - assign n2895 = n4503 & n4501 & (n4400 | n3914); - assign n2896 = n2894 & n2895 & (n2876 | n1322); - assign n2897 = n802 & n2533; - assign n2898 = n802 & n2821 & (n18 | n2897); - assign n2899 = n802 & n2540; - assign n2900 = n802 & n2822 & (n18 | n2899); - assign n2901 = (n2898 | n3915) & (n2900 | n3916); - assign n2902 = n2624 & (n4388 | n3917); - assign n2903 = n2821 & n2535; - assign n2904 = n2901 & n2902 & (n2903 | n1729); - assign n2905 = n802 & n2520; - assign n2906 = n802 & n2819 & (n18 | n2905); - assign n2907 = n802 & n2525; - assign n2908 = n802 & n2820 & (n18 | n2907); - assign n2909 = (n2906 | n3915) & (n2908 | n3916); - assign n2910 = n2624 & (n4389 | n3917); - assign n2911 = n2909 & n2910 & (n2825 | n1729); - assign n2912 = n802 & n2437; - assign n2913 = n802 & n2795 & (n18 | n2912); - assign n2914 = n802 & n2448; - assign n2915 = n802 & n2796 & (n18 | n2914); - assign n2916 = (n2913 | n3915) & (n2915 | n3916); - assign n2917 = n2624 & (n2799 | n3917); - assign n2918 = n2795 & n2440; - assign n2919 = n2916 & n2917 & (n2918 | n1729); - assign n2920 = n802 & n2455; - assign n2921 = n802 & n2797 & (n18 | n2920); - assign n2922 = (n2919 | n3864) & (n2911 | n3867); - assign n2923 = n4500 & n4501 & (n4398 | n3914); - assign n2924 = n2922 & n2923 & (n2904 | n1322); - assign n2925 = n802 & n2609; - assign n2926 = n802 & n2845 & (n18 | n2925); - assign n2927 = n802 & n2614; - assign n2928 = n802 & n2846 & (n18 | n2927); - assign n2929 = (n2926 | n3915) & (n2928 | n3916); - assign n2930 = n2624 & (n4394 | n3917); - assign n2931 = n2845 & n2611; - assign n2932 = n2929 & n2930 & (n2931 | n1729); - assign n2933 = n802 & n2599; - assign n2934 = n802 & n2843 & (n18 | n2933); - assign n2935 = n802 & n2604; - assign n2936 = n802 & n2844 & (n18 | n2935); - assign n2937 = (n2934 | n3915) & (n2936 | n3916); - assign n2938 = n2624 & (n4395 | n3917); - assign n2939 = n2937 & n2938 & (n2849 | n1729); - assign n2940 = n802 & n2503; - assign n2941 = n802 & n2813 & (n18 | n2940); - assign n2942 = n802 & n2508; - assign n2943 = n802 & n2814 & (n18 | n2942); - assign n2944 = (n2941 | n3915) & (n2943 | n3916); - assign n2945 = n2624 & (n2817 | n3917); - assign n2946 = n2813 & n2505; - assign n2947 = n2944 & n2945 & (n2946 | n1729); - assign n2948 = n802 & n2512; - assign n2949 = n802 & n2815 & (n18 | n2948); - assign n2950 = (n2947 | n3864) & (n2939 | n3867); - assign n2951 = n4504 & n4501 & (n4401 | n3914); - assign n2952 = n2950 & n2951 & (n2932 | n1322); - assign n2953 = n802 & n2585; - assign n2954 = n802 & n2837 & (n18 | n2953); - assign n2955 = n802 & n2590; - assign n2956 = n802 & n2838 & (n18 | n2955); - assign n2957 = (n2954 | n3915) & (n2956 | n3916); - assign n2958 = n2624 & (n4390 | n3917); - assign n2959 = n2837 & n2587; - assign n2960 = n2957 & n2958 & (n2959 | n1729); - assign n2961 = n802 & n2575; - assign n2962 = n802 & n2835 & (n18 | n2961); - assign n2963 = n802 & n2580; - assign n2964 = n802 & n2836 & (n18 | n2963); - assign n2965 = (n2962 | n3915) & (n2964 | n3916); - assign n2966 = n2624 & (n4391 | n3917); - assign n2967 = n2965 & n2966 & (n2841 | n1729); - assign n2968 = n802 & n2486; - assign n2969 = n802 & n2807 & (n18 | n2968); - assign n2970 = n802 & n2491; - assign n2971 = n802 & n2808 & (n18 | n2970); - assign n2972 = (n2969 | n3915) & (n2971 | n3916); - assign n2973 = n2624 & (n2811 | n3917); - assign n2974 = n2807 & n2488; - assign n2975 = n2972 & n2973 & (n2974 | n1729); - assign n2976 = n802 & n2495; - assign n2977 = n802 & n2809 & (n18 | n2976); - assign n2978 = (n2975 | n3864) & (n2967 | n3867); - assign n2979 = n4502 & n4501 & (n4399 | n3914); - assign n2980 = n2978 & n2979 & (n2960 | n1322); - assign n2981 = ~n2272 & (~n4485 | ~n4486); - assign n2982 = ~n2272 & (~n4466 | ~n4467); - assign n2983 = n3696 | n4717 | n4719; - assign n2984 = n2868 & (n2632 | (n4506 & n4505)); - assign n2985 = n2983 & n2984 & (n2867 | n1452); - assign n2986 = (n2870 | n3901) & (n2872 | n3902); - assign n2987 = n2634 & (n4392 | n3903); - assign n2988 = n2986 & n2987 & (n2875 | n1868); - assign n2989 = (n2878 | n3901) & (n2880 | n3902); - assign n2990 = n2634 & (n4393 | n3903); - assign n2991 = n2989 & n2990 & (n2833 | n1868); - assign n2992 = (n2885 | n3901) & (n2887 | n3902); - assign n2993 = n2634 & (n2805 | n3903); - assign n2994 = n2992 & n2993 & (n2890 | n1868); - assign n2995 = (n2994 | n3864) & (n2991 | n3867); - assign n2996 = n4460 & n4458 & (n4400 | n3900); - assign n2997 = n2995 & n2996 & (n2988 | n1322); - assign n2998 = (n2898 | n3901) & (n2900 | n3902); - assign n2999 = n2634 & (n4388 | n3903); - assign n3000 = n2998 & n2999 & (n2903 | n1868); - assign n3001 = (n2906 | n3901) & (n2908 | n3902); - assign n3002 = n2634 & (n4389 | n3903); - assign n3003 = n3001 & n3002 & (n2825 | n1868); - assign n3004 = (n2913 | n3901) & (n2915 | n3902); - assign n3005 = n2634 & (n2799 | n3903); - assign n3006 = n3004 & n3005 & (n2918 | n1868); - assign n3007 = (n3006 | n3864) & (n3003 | n3867); - assign n3008 = n4457 & n4458 & (n4398 | n3900); - assign n3009 = n3007 & n3008 & (n3000 | n1322); - assign n3010 = (n2926 | n3901) & (n2928 | n3902); - assign n3011 = n2634 & (n4394 | n3903); - assign n3012 = n3010 & n3011 & (n2931 | n1868); - assign n3013 = (n2934 | n3901) & (n2936 | n3902); - assign n3014 = n2634 & (n4395 | n3903); - assign n3015 = n3013 & n3014 & (n2849 | n1868); - assign n3016 = (n2941 | n3901) & (n2943 | n3902); - assign n3017 = n2634 & (n2817 | n3903); - assign n3018 = n3016 & n3017 & (n2946 | n1868); - assign n3019 = (n3018 | n3864) & (n3015 | n3867); - assign n3020 = n4461 & n4458 & (n4401 | n3900); - assign n3021 = n3019 & n3020 & (n3012 | n1322); - assign n3022 = (n2954 | n3901) & (n2956 | n3902); - assign n3023 = n2634 & (n4390 | n3903); - assign n3024 = n3022 & n3023 & (n2959 | n1868); - assign n3025 = (n2962 | n3901) & (n2964 | n3902); - assign n3026 = n2634 & (n4391 | n3903); - assign n3027 = n3025 & n3026 & (n2841 | n1868); - assign n3028 = (n2969 | n3901) & (n2971 | n3902); - assign n3029 = n2634 & (n2811 | n3903); - assign n3030 = n3028 & n3029 & (n2974 | n1868); - assign n3031 = (n3030 | n3864) & (n3027 | n3867); - assign n3032 = n4459 & n4458 & (n4399 | n3900); - assign n3033 = n3031 & n3032 & (n3024 | n1322); - assign n3034 = (n2997 | n3884) & (n3021 | n3891); - assign n3035 = (n3009 | n3870) & (n3033 | n3877); - assign n3036 = n3034 & n3035; - assign n3037 = n784 & n2424; - assign n3038 = n2423 & (n3037 | n1919); - assign n3039 = n3038 & (n1929 | (n4387 & n4385)); - assign n3040 = n2496 & (~Pi16 | n2513); - assign n3041 = n3039 & (n3040 | n1923); - assign n3042 = n3038 & (n1929 | (n4383 & n4381)); - assign n3043 = n2456 & (~Pi16 | n2479); - assign n3044 = n3042 & (n3043 | n1923); - assign n3045 = (n4414 | n3858) & (n2499 | n3860); - assign n3046 = (Pi20 & n2492) | (n2487 & (~Pi20 | n2492)); - assign n3047 = n3045 & (n3046 | n1929); - assign n3048 = ~n3740 & ((~n1929 & ~n2855) | ~n4416); - assign n3049 = ~n2272 & (~n4417 | (~n1929 & ~n3094)); - assign n3050 = ~n3895 & ((~n1929 & ~n3091) | ~n4419); - assign n3051 = ~n3743 & ((~n1929 & ~n2863) | ~n4420); - assign n3052 = ~n3737 & ((~n1929 & ~n2864) | ~n4422); - assign n3053 = (n4404 | n3858) & (n2459 | n3860); - assign n3054 = n3053 & (n2851 | n1929); - assign n3055 = ~n3740 & ((~n1929 & ~n2853) | ~n4406); - assign n3056 = ~n2272 & (~n4407 | (~n1929 & ~n2857)); - assign n3057 = ~n3895 & ((~n1929 & ~n2858) | ~n4409); - assign n3058 = ~n3743 & ((~n1929 & ~n2860) | ~n4410); - assign n3059 = ~n3737 & ((~n1929 & ~n2861) | ~n4412); - assign n3060 = (~Pi15 & n3044) | (n3041 & (Pi15 | n3044)); - assign n3061 = (n1448 | n3060) & (n1446 | ~n3997); - assign n3062 = n2634 & (n2635 | n1919); - assign n3063 = (n2869 | n3931) & (n2871 | n3932); - assign n3064 = n3062 & n3063 & (n2861 | n1948); - assign n3065 = (n2877 | n3931) & (n2879 | n3932); - assign n3066 = n3062 & n3065 & (n2860 | n1948); - assign n3067 = (n2884 | n3931) & (n2886 | n3932); - assign n3068 = n3062 & n3067 & (n2853 | n1948); - assign n3069 = (n3068 | n3864) & (n3066 | n3867); - assign n3070 = n4453 & n4451 & (n2479 | n3930); - assign n3071 = n3069 & n3070 & (n3064 | n1322); - assign n3072 = (n2897 | n3931) & (n2899 | n3932); - assign n3073 = n3062 & n3072 & (n2858 | n1948); - assign n3074 = (n2905 | n3931) & (n2907 | n3932); - assign n3075 = n3062 & n3074 & (n2857 | n1948); - assign n3076 = (n2912 | n3931) & (n2914 | n3932); - assign n3077 = n3062 & n3076 & (n2851 | n1948); - assign n3078 = (n3077 | n3864) & (n3075 | n3867); - assign n3079 = n4450 & n4451 & (n2456 | n3930); - assign n3080 = n3078 & n3079 & (n3073 | n1322); - assign n3081 = (n2925 | n3931) & (n2927 | n3932); - assign n3082 = n3062 & n3081 & (n2864 | n1948); - assign n3083 = (n2933 | n3931) & (n2935 | n3932); - assign n3084 = n3062 & n3083 & (n2863 | n1948); - assign n3085 = (n2940 | n3931) & (n2942 | n3932); - assign n3086 = n3062 & n3085 & (n2855 | n1948); - assign n3087 = (n3086 | n3864) & (n3084 | n3867); - assign n3088 = n4454 & n4451 & (n2513 | n3930); - assign n3089 = n3087 & n3088 & (n3082 | n1322); - assign n3090 = (n2953 | n3931) & (n2955 | n3932); - assign n3091 = (Pi20 & n2591) | (n2586 & (~Pi20 | n2591)); - assign n3092 = n3062 & n3090 & (n3091 | n1948); - assign n3093 = (n2961 | n3931) & (n2963 | n3932); - assign n3094 = (Pi20 & n2581) | (n2576 & (~Pi20 | n2581)); - assign n3095 = n3062 & n3093 & (n3094 | n1948); - assign n3096 = (n2968 | n3931) & (n2970 | n3932); - assign n3097 = n3062 & n3096 & (n3046 | n1948); - assign n3098 = (n3097 | n3864) & (n3095 | n3867); - assign n3099 = n4452 & n4451 & (n2496 | n3930); - assign n3100 = n3098 & n3099 & (n3092 | n1322); - assign n3101 = n2628 & (n2629 | n1919); - assign n3102 = (n2861 | n3922) & (n2869 | n3923); - assign n3103 = n3101 & n3102 & (n2871 | n1989); - assign n3104 = (n2860 | n3922) & (n2877 | n3923); - assign n3105 = n3101 & n3104 & (n2879 | n1989); - assign n3106 = (n2853 | n3922) & (n2884 | n3923); - assign n3107 = n3101 & n3106 & (n2886 | n1989); - assign n3108 = (n3107 | n3864) & (n3105 | n3867); - assign n3109 = n4446 & n4444 & (n2892 | n3921); - assign n3110 = n3108 & n3109 & (n3103 | n1322); - assign n3111 = (n2858 | n3922) & (n2897 | n3923); - assign n3112 = n3101 & n3111 & (n2899 | n1989); - assign n3113 = (n2857 | n3922) & (n2905 | n3923); - assign n3114 = n3101 & n3113 & (n2907 | n1989); - assign n3115 = (n2851 | n3922) & (n2912 | n3923); - assign n3116 = n3101 & n3115 & (n2914 | n1989); - assign n3117 = (n3116 | n3864) & (n3114 | n3867); - assign n3118 = n4443 & n4444 & (n2920 | n3921); - assign n3119 = n3117 & n3118 & (n3112 | n1322); - assign n3120 = (n2864 | n3922) & (n2925 | n3923); - assign n3121 = n3101 & n3120 & (n2927 | n1989); - assign n3122 = (n2863 | n3922) & (n2933 | n3923); - assign n3123 = n3101 & n3122 & (n2935 | n1989); - assign n3124 = (n2855 | n3922) & (n2940 | n3923); - assign n3125 = n3101 & n3124 & (n2942 | n1989); - assign n3126 = (n3125 | n3864) & (n3123 | n3867); - assign n3127 = n4447 & n4444 & (n2948 | n3921); - assign n3128 = n3126 & n3127 & (n3121 | n1322); - assign n3129 = (n3091 | n3922) & (n2953 | n3923); - assign n3130 = n3101 & n3129 & (n2955 | n1989); - assign n3131 = (n3094 | n3922) & (n2961 | n3923); - assign n3132 = n3101 & n3131 & (n2963 | n1989); - assign n3133 = (n3046 | n3922) & (n2968 | n3923); - assign n3134 = n3101 & n3133 & (n2970 | n1989); - assign n3135 = (n3134 | n3864) & (n3132 | n3867); - assign n3136 = n4445 & n4444 & (n2976 | n3921); - assign n3137 = n3135 & n3136 & (n3130 | n1322); - assign n3138 = n2624 & (n2625 | n1919); - assign n3139 = (n2869 | n3926) & (n2871 | n3927); - assign n3140 = n3138 & n3139 & (n2861 | n2028); - assign n3141 = (n2877 | n3926) & (n2879 | n3927); - assign n3142 = n3138 & n3141 & (n2860 | n2028); - assign n3143 = (n2884 | n3926) & (n2886 | n3927); - assign n3144 = n3138 & n3143 & (n2853 | n2028); - assign n3145 = (n3144 | n3864) & (n3142 | n3867); - assign n3146 = n4439 & n4437 & (n2479 | n3925); - assign n3147 = n3145 & n3146 & (n3140 | n1322); - assign n3148 = (n2897 | n3926) & (n2899 | n3927); - assign n3149 = n3138 & n3148 & (n2858 | n2028); - assign n3150 = (n2905 | n3926) & (n2907 | n3927); - assign n3151 = n3138 & n3150 & (n2857 | n2028); - assign n3152 = (n2912 | n3926) & (n2914 | n3927); - assign n3153 = n3138 & n3152 & (n2851 | n2028); - assign n3154 = (n3153 | n3864) & (n3151 | n3867); - assign n3155 = n4436 & n4437 & (n2456 | n3925); - assign n3156 = n3154 & n3155 & (n3149 | n1322); - assign n3157 = (n2925 | n3926) & (n2927 | n3927); - assign n3158 = n3138 & n3157 & (n2864 | n2028); - assign n3159 = (n2933 | n3926) & (n2935 | n3927); - assign n3160 = n3138 & n3159 & (n2863 | n2028); - assign n3161 = (n2940 | n3926) & (n2942 | n3927); - assign n3162 = n3138 & n3161 & (n2855 | n2028); - assign n3163 = (n3162 | n3864) & (n3160 | n3867); - assign n3164 = n4440 & n4437 & (n2513 | n3925); - assign n3165 = n3163 & n3164 & (n3158 | n1322); - assign n3166 = (n2953 | n3926) & (n2955 | n3927); - assign n3167 = n3138 & n3166 & (n3091 | n2028); - assign n3168 = (n2961 | n3926) & (n2963 | n3927); - assign n3169 = n3138 & n3168 & (n3094 | n2028); - assign n3170 = (n2968 | n3926) & (n2970 | n3927); - assign n3171 = n3138 & n3170 & (n3046 | n2028); - assign n3172 = (n3171 | n3864) & (n3169 | n3867); - assign n3173 = n4438 & n4437 & (n2496 | n3925); - assign n3174 = n3172 & n3173 & (n3167 | n1322); - assign n3175 = ~n3677 & (~n4455 | ~n4456); - assign n3176 = ~n3805 & ~n4723 & (Ni10 | ~n4002); - assign n3177 = ~n3937 & (n2751 | n2752 | ~n4532); - assign n3178 = ~n3766 & (n2793 | n2794 | ~n4587); - assign n3179 = ~n1671 & (~n4588 | (~Ni11 & ~n2633)); - assign n3180 = (Ni11 | n2622) & (~n1543 | n2621); - assign n3181 = ~n3180 & (n2072 | (n2073 & n2074)); - assign n3182 = (~n3707 & ~n4010) | (~Ni32 & (n3707 | ~n4010)); - assign n3183 = Ni36 | ~Ni38; - assign n3184 = Pi19 & Pi17; - assign n3185 = ~Ni45 | n3186; - assign n3186 = Ni45 & Ni46; - assign n3187 = ~Ni40 | (Ni30 & n1353); - assign n3188 = (~n2073 | ~n4014) & (~n2072 | n4013); - assign n3189 = ~Ni41 | (Ni30 & n1353); - assign n3190 = (~n2073 | ~n4018) & (~n2072 | n4017); - assign n3191 = ~n3186 & (Ni45 | ~n3661); - assign n3192 = ~Ni47 | ~Ni48; - assign n3193 = ~n3186 & (Ni45 | n3192); - assign n3194 = Ni38 | ~Ni39; - assign n3195 = Ni39 | Ni38; - assign n3196 = (n3191 | n3194) & (n3193 | n3195); - assign n3197 = ~Ni37 | n3196; - assign n3198 = n3193 & (n3203 | ~Ni42); - assign n3199 = n3197 & (~n814 | n3198); - assign n3200 = n3333 & (Ni42 | n3191); - assign n3201 = n3197 & (~n814 | n3200); - assign n3202 = ~n797 & (n1539 | n3193); - assign n3203 = n3193 & (n3191 | n3331); - assign n3204 = n3198 & (Ni41 | n3203); - assign n3205 = n3203 & (n3191 | n923); - assign n3206 = n3198 & (Ni41 | n3205); - assign n3207 = n3200 | n3854; - assign n3208 = n3211 | (n817 & n3968); - assign n3209 = n3208 & n3207 & n3197; - assign n3210 = Ni37 | n3976; - assign n3211 = n3204 & (n3206 | ~Ni40); - assign n3212 = n3210 & (~n783 | n3211); - assign n3213 = n3209 & (~n2530 | n3212); - assign n3214 = ~n2426 & ~n3191 & (n2441 | ~n3193); - assign n3215 = Ni41 | ~Ni42; - assign n3216 = ~n3214 & (n3203 | n3215); - assign n3217 = n3200 | n3855; - assign n3218 = n3220 | (n853 & n3968); - assign n3219 = n3218 & n3217 & n3197; - assign n3220 = n3247 & (n3206 | ~Ni40); - assign n3221 = n3210 & (~n783 | n3220); - assign n3222 = n3219 & (~n2530 | n3221); - assign n3223 = Pi20 | Pi19; - assign n3224 = ~Pi20 | Pi19; - assign n3225 = (n3213 | n3223) & (n3222 | n3224); - assign n3226 = n3197 & n3210 & (n3206 | ~Ni38); - assign n3227 = Pi21 & Pi19; - assign n3228 = Pi22 & ~n3550; - assign n3229 = n3227 & (n810 | (~n3226 & n3228)); - assign n3230 = n3232 | (n817 & n3968); - assign n3231 = n3230 & n3207 & n3197; - assign n3232 = n3276 & (n3205 | ~Ni40); - assign n3233 = n3210 & (~n783 | n3232); - assign n3234 = n3231 & (~n2530 | n3233); - assign n3235 = (~Ni41 | n3205) & n3216; - assign n3236 = n3238 | (n853 & n3968); - assign n3237 = n3236 & n3217 & n3197; - assign n3238 = n3235 & (n3205 | ~Ni40); - assign n3239 = n3210 & (~n783 | n3238); - assign n3240 = n3237 & (~n2530 | n3239); - assign n3241 = (n3234 | n3223) & (n3240 | n3224); - assign n3242 = n3197 & n3210 & (n3205 | ~Ni38); - assign n3243 = n3227 & (n810 | (n3228 & ~n3242)); - assign n3244 = n3247 | (n853 & n3968); - assign n3245 = n3244 & n3217 & n3197; - assign n3246 = n698 | n3976; - assign n3247 = n3198 & n3216; - assign n3248 = n3246 & n3245 & (n1216 | n3247); - assign n3249 = n3247 & (Ni40 | n3206); - assign n3250 = n3210 & (~n783 | n3249); - assign n3251 = n3249 | (n853 & n3968); - assign n3252 = n3251 & n3217 & n3197; - assign n3253 = (~n2434 | n3250) & n3252; - assign n3254 = n3235 | (n853 & n3968); - assign n3255 = n3254 & n3217 & n3197; - assign n3256 = n3246 & n3255 & (n1216 | n3235); - assign n3257 = n3235 & (Ni40 | n3205); - assign n3258 = n3210 & (~n783 | n3257); - assign n3259 = n3257 | (n853 & n3968); - assign n3260 = n3259 & n3217 & n3197; - assign n3261 = (~n2434 | n3258) & n3260; - assign n3262 = ~n799 & ~n3977; - assign n3263 = (n3256 | n3743) & (n3261 | n3737); - assign n3264 = (n3248 | n2272) & (n3253 | n3895); - assign n3265 = n3262 & (~n3288 | (n3263 & n3264)); - assign n3266 = n3204 | (n817 & n3968); - assign n3267 = n3266 & n3207 & n3197; - assign n3268 = n3246 & n3267 & (n1216 | n3204); - assign n3269 = n3204 & (Ni40 | n3206); - assign n3270 = n3210 & (~n783 | n3269); - assign n3271 = n3269 | (n817 & n3968); - assign n3272 = n3271 & n3207 & n3197; - assign n3273 = (~n2434 | n3270) & n3272; - assign n3274 = n3276 | (n817 & n3968); - assign n3275 = n3274 & n3207 & n3197; - assign n3276 = n3203 & (~Ni41 | n3205); - assign n3277 = n3246 & n3275 & (n1216 | n3276); - assign n3278 = n3276 & (Ni40 | n3205); - assign n3279 = n3210 & (~n783 | n3278); - assign n3280 = n3278 | (n817 & n3968); - assign n3281 = n3280 & n3207 & n3197; - assign n3282 = (~n2434 | n3279) & n3281; - assign n3283 = ~n4732 & (Pi22 | ~Pi21 | n3202); - assign n3284 = ~n799 & n3283; - assign n3285 = (n3277 | n3743) & (n3282 | n3737); - assign n3286 = (n3268 | n2272) & (n3273 | n3895); - assign n3287 = n3284 & (~n3288 | (n3285 & n3286)); - assign n3288 = ~n2254 & ~n3550; - assign n3289 = ~n3978 & (n3229 | (~n3225 & n3288)); - assign n3290 = ~n3979 & (n3243 | (~n3241 & n3288)); - assign n3291 = (n3211 | n698) & (n3212 | n2434); - assign n3292 = n3291 & n3209; - assign n3293 = (n3220 | n698) & (n3221 | n2434); - assign n3294 = n3293 & n3219; - assign n3295 = (n3292 | n3223) & (n3294 | n3224); - assign n3296 = n3197 & (n3206 | n690); - assign n3297 = n3296 & (Ni36 | n3226); - assign n3298 = ~n3297 & n3227 & n3228; - assign n3299 = (n3232 | n698) & (n3233 | n2434); - assign n3300 = n3299 & n3231; - assign n3301 = (n3238 | n698) & (n3239 | n2434); - assign n3302 = n3301 & n3237; - assign n3303 = (n3300 | n3223) & (n3302 | n3224); - assign n3304 = n3197 & (n3205 | n690); - assign n3305 = n3304 & (Ni36 | n3242); - assign n3306 = n3227 & (n810 | (n3228 & ~n3305)); - assign n3307 = n3245 & (n3247 | n698); - assign n3308 = (n3249 | n698) & (n3250 | n2530); - assign n3309 = n3308 & n3252; - assign n3310 = n3255 & (n3235 | n698); - assign n3311 = (n3257 | n698) & (n3258 | n2530); - assign n3312 = n3311 & n3260; - assign n3313 = (n3310 | n3743) & (n3312 | n3737); - assign n3314 = (n3307 | n2272) & (n3309 | n3895); - assign n3315 = n3262 & (~n3288 | (n3313 & n3314)); - assign n3316 = n3267 & (n3204 | n698); - assign n3317 = (n3269 | n698) & (n3270 | n2530); - assign n3318 = n3317 & n3272; - assign n3319 = n3275 & (n3276 | n698); - assign n3320 = (n3278 | n698) & (n3279 | n2530); - assign n3321 = n3320 & n3281; - assign n3322 = (n3319 | n3743) & (n3321 | n3737); - assign n3323 = (n3316 | n2272) & (n3318 | n3895); - assign n3324 = n3284 & (~n3288 | (n3322 & n3323)); - assign n3325 = ~n3978 & ((n3288 & ~n3295) | n3298); - assign n3326 = ~n3979 & ((n3288 & ~n3303) | n3306); - assign n3327 = Ni11 | n1446; - assign n3328 = n3327 & (~n807 | (~n2254 & ~n3471)); - assign n3329 = ~n3944 & (n3325 | n3326 | ~n4030); - assign n3330 = ~n2367 & (n3289 | n3290 | ~n4031); - assign n3331 = ~Ni44 | Ni43; - assign n3332 = ~n2426 & ~n3191 & (~n3193 | n3331); - assign n3333 = n3193 & (n2441 | n3191); - assign n3334 = ~n3332 & (n3215 | n3333); - assign n3335 = n3193 & (n3191 | n3754); - assign n3336 = n3335 & (n3333 | ~Ni42); - assign n3337 = n3353 & (Ni40 | n3395); - assign n3338 = n3337 | n817; - assign n3339 = Ni37 | n3974; - assign n3340 = n3337 | (~n783 & n3968); - assign n3341 = n3340 & n3339 & n3197; - assign n3342 = n3337 | n698; - assign n3343 = n3341 & n3342 & (Ni35 | n3338); - assign n3344 = ~n797 & n3480; - assign n3345 = (~Ni33 | n3343) & n3344; - assign n3346 = n3353 & (Ni40 | n3401); - assign n3347 = n3346 | n853; - assign n3348 = n3346 | (~n783 & n3968); - assign n3349 = n3348 & n3339 & n3197; - assign n3350 = n3346 | n698; - assign n3351 = n3349 & n3350 & (Ni35 | n3347); - assign n3352 = n3344 & (~Ni33 | n3351); - assign n3353 = n3336 & n3836; - assign n3354 = n3197 & n3339 & (n3353 | ~Ni38); - assign n3355 = n3354 & (n3353 | n690); - assign n3356 = n3344 & (~Ni33 | n3355); - assign n3357 = (n3345 | n1408) & (n3352 | n914); - assign n3358 = n807 & n3357 & (n3356 | n1702); - assign n3359 = n3336 & (Ni40 | n3423); - assign n3360 = n3359 | n817; - assign n3361 = n3359 | (~n783 & n3968); - assign n3362 = n3361 & n3339 & n3197; - assign n3363 = n3359 | n698; - assign n3364 = n3362 & n3363 & (Ni35 | n3360); - assign n3365 = n3344 & (~Ni33 | n3364); - assign n3366 = n3336 & (Ni40 | n3428); - assign n3367 = n3366 | n853; - assign n3368 = n3366 | (~n783 & n3968); - assign n3369 = n3368 & n3339 & n3197; - assign n3370 = n3366 | n698; - assign n3371 = n3369 & n3370 & (Ni35 | n3367); - assign n3372 = n3344 & (~Ni33 | n3371); - assign n3373 = n3197 & n3339 & (n3336 | ~Ni38); - assign n3374 = n3373 & (n3336 | n690); - assign n3375 = n3344 & (~Ni33 | n3374); - assign n3376 = (n3365 | n1408) & (n3372 | n914); - assign n3377 = n807 & n3376 & (n3375 | n1702); - assign n3378 = n3341 & (Ni35 | n3338); - assign n3379 = n3344 & (~Ni33 | n3378); - assign n3380 = n3349 & (Ni35 | n3347); - assign n3381 = n3344 & (~Ni33 | n3380); - assign n3382 = n3344 & (~Ni33 | n3354); - assign n3383 = (n3379 | n1408) & (n3381 | n914); - assign n3384 = n807 & n3383 & (n3382 | n1702); - assign n3385 = n3362 & (Ni35 | n3360); - assign n3386 = n3344 & (~Ni33 | n3385); - assign n3387 = n3369 & (Ni35 | n3367); - assign n3388 = n3344 & (~Ni33 | n3387); - assign n3389 = n3344 & (~Ni33 | n3373); - assign n3390 = (n3386 | n1408) & (n3388 | n914); - assign n3391 = n807 & n3390 & (n3389 | n1702); - assign n3392 = n3198 | n3854; - assign n3393 = n3395 | (n817 & n3968); - assign n3394 = n3393 & n3392 & n3197; - assign n3395 = n3836 & n3334; - assign n3396 = n3394 & (n3395 | n698); - assign n3397 = n3344 & (~Ni33 | n3396); - assign n3398 = n3198 | n3855; - assign n3399 = n3401 | (n853 & n3968); - assign n3400 = n3399 & n3398 & n3197; - assign n3401 = n3333 & n3836; - assign n3402 = n3400 & (n3401 | n698); - assign n3403 = n3344 & (~Ni33 | n3402); - assign n3404 = n3406 | (~n783 & n3968); - assign n3405 = n3404 & n3339 & n3197; - assign n3406 = n3353 & (n3395 | ~Ni40); - assign n3407 = n3406 | n817; - assign n3408 = n3406 | n698; - assign n3409 = n3405 & n3408 & (~Ni35 | n3407); - assign n3410 = n3344 & (~Ni33 | n3409); - assign n3411 = n3413 | (~n783 & n3968); - assign n3412 = n3411 & n3339 & n3197; - assign n3413 = n3353 & (n3401 | ~Ni40); - assign n3414 = n3413 | n853; - assign n3415 = n3413 | n698; - assign n3416 = n3412 & n3415 & (~Ni35 | n3414); - assign n3417 = n3344 & (~Ni33 | n3416); - assign n3418 = n807 & (n3410 | n3893); - assign n3419 = (n3397 | n1408) & (n3403 | n914); - assign n3420 = n3418 & n3419 & (n3417 | n2109); - assign n3421 = n3423 | (n817 & n3968); - assign n3422 = n3421 & n3392 & n3197; - assign n3423 = n3336 & n3334; - assign n3424 = n3422 & (n3423 | n698); - assign n3425 = n3344 & (~Ni33 | n3424); - assign n3426 = n3428 | (n853 & n3968); - assign n3427 = n3426 & n3398 & n3197; - assign n3428 = n3336 & (Ni41 | n3333); - assign n3429 = n3427 & (n3428 | n698); - assign n3430 = n3344 & (~Ni33 | n3429); - assign n3431 = n3433 | (~n783 & n3968); - assign n3432 = n3431 & n3339 & n3197; - assign n3433 = n3336 & (n3423 | ~Ni40); - assign n3434 = n3433 | n817; - assign n3435 = n3433 | n698; - assign n3436 = n3432 & n3435 & (~Ni35 | n3434); - assign n3437 = n3344 & (~Ni33 | n3436); - assign n3438 = n3440 | (~n783 & n3968); - assign n3439 = n3438 & n3339 & n3197; - assign n3440 = n3336 & (n3428 | ~Ni40); - assign n3441 = n3440 | n853; - assign n3442 = n3440 | n698; - assign n3443 = n3439 & n3442 & (~Ni35 | n3441); - assign n3444 = n3344 & (~Ni33 | n3443); - assign n3445 = n807 & (n3437 | n3893); - assign n3446 = (n3425 | n1408) & (n3430 | n914); - assign n3447 = n3445 & n3446 & (n3444 | n2109); - assign n3448 = n698 | n3974; - assign n3449 = n3448 & n3394 & (n1216 | n3395); - assign n3450 = n3344 & (~Ni33 | n3449); - assign n3451 = n3448 & n3400 & (n1216 | n3401); - assign n3452 = n3344 & (~Ni33 | n3451); - assign n3453 = n3405 & (~Ni35 | n3407); - assign n3454 = n3344 & (~Ni33 | n3453); - assign n3455 = n3412 & (~Ni35 | n3414); - assign n3456 = n3344 & (~Ni33 | n3455); - assign n3457 = n807 & (n3454 | n3893); - assign n3458 = (n3450 | n1408) & (n3452 | n914); - assign n3459 = n3457 & n3458 & (n3456 | n2109); - assign n3460 = n3448 & n3422 & (n1216 | n3423); - assign n3461 = n3344 & (~Ni33 | n3460); - assign n3462 = n3448 & n3427 & (n1216 | n3428); - assign n3463 = n3344 & (~Ni33 | n3462); - assign n3464 = n3432 & (~Ni35 | n3434); - assign n3465 = n3344 & (~Ni33 | n3464); - assign n3466 = n3439 & (~Ni35 | n3441); - assign n3467 = n3344 & (~Ni33 | n3466); - assign n3468 = n807 & (n3465 | n3893); - assign n3469 = (n3461 | n1408) & (n3463 | n914); - assign n3470 = n3468 & n3469 & (n3467 | n2109); - assign n3471 = ~n809 & n3480; - assign n3472 = n807 & (n3471 | n1919); - assign n3473 = (~n2345 | n3389) & (n3382 | ~n3772); - assign n3474 = ~n2272 & (~n3472 | ~n4604); - assign n3475 = ~n3743 & (~n3472 | ~n4606); - assign n3476 = (~n2345 | n3375) & (n3356 | ~n3772); - assign n3477 = ~n3740 & (~n3472 | ~n4593); - assign n3478 = ~n2272 & (~n3472 | ~n4594); - assign n3479 = ~n3743 & (~n3472 | ~n4596); - assign n3480 = n1539 | Ni33 | n3199; - assign n3481 = ~Ni34 | n3201; - assign n3482 = ~n797 & n3480 & (~Ni33 | n3481); - assign n3483 = Ni34 | ~Ni33; - assign n3484 = n3482 & (n3343 | n3483); - assign n3485 = n3482 & (n3351 | n3483); - assign n3486 = n3482 & (n3355 | n3483); - assign n3487 = (n3484 | n1408) & (n3485 | n914); - assign n3488 = n807 & n3487 & (n3486 | n1702); - assign n3489 = n3482 & (n3364 | n3483); - assign n3490 = n3482 & (n3371 | n3483); - assign n3491 = n3482 & (n3374 | n3483); - assign n3492 = (n3489 | n1408) & (n3490 | n914); - assign n3493 = n807 & n3492 & (n3491 | n1702); - assign n3494 = n3482 & (n3378 | n3483); - assign n3495 = n3482 & (n3380 | n3483); - assign n3496 = n3482 & (n3354 | n3483); - assign n3497 = (n3494 | n1408) & (n3495 | n914); - assign n3498 = n807 & n3497 & (n3496 | n1702); - assign n3499 = n3482 & (n3385 | n3483); - assign n3500 = n3482 & (n3387 | n3483); - assign n3501 = n3482 & (n3373 | n3483); - assign n3502 = (n3499 | n1408) & (n3500 | n914); - assign n3503 = n807 & n3502 & (n3501 | n1702); - assign n3504 = n3482 & (n3396 | n3483); - assign n3505 = n3482 & (n3402 | n3483); - assign n3506 = n3482 & (n3409 | n3483); - assign n3507 = n3482 & (n3416 | n3483); - assign n3508 = n807 & (n3506 | n3893); - assign n3509 = (n3504 | n1408) & (n3505 | n914); - assign n3510 = n3508 & n3509 & (n3507 | n2109); - assign n3511 = n3482 & (n3424 | n3483); - assign n3512 = n3482 & (n3429 | n3483); - assign n3513 = n3482 & (n3436 | n3483); - assign n3514 = n3482 & (n3443 | n3483); - assign n3515 = n807 & (n3513 | n3893); - assign n3516 = (n3511 | n1408) & (n3512 | n914); - assign n3517 = n3515 & n3516 & (n3514 | n2109); - assign n3518 = n3482 & (n3449 | n3483); - assign n3519 = n3482 & (n3451 | n3483); - assign n3520 = n3482 & (n3453 | n3483); - assign n3521 = n3482 & (n3455 | n3483); - assign n3522 = n807 & (n3520 | n3893); - assign n3523 = (n3518 | n1408) & (n3519 | n914); - assign n3524 = n3522 & n3523 & (n3521 | n2109); - assign n3525 = n3482 & (n3460 | n3483); - assign n3526 = n3482 & (n3462 | n3483); - assign n3527 = n3482 & (n3464 | n3483); - assign n3528 = n3482 & (n3466 | n3483); - assign n3529 = n807 & (n3527 | n3893); - assign n3530 = (n3525 | n1408) & (n3526 | n914); - assign n3531 = n3529 & n3530 & (n3528 | n2109); - assign n3532 = (~n2345 | n3501) & (n3496 | ~n3772); - assign n3533 = ~n2272 & (~n3472 | ~n4625); - assign n3534 = ~n3743 & (~n3472 | ~n4627); - assign n3535 = (~n2345 | n3491) & (n3486 | ~n3772); - assign n3536 = ~n3740 & (~n3472 | ~n4614); - assign n3537 = ~n2272 & (~n3472 | ~n4615); - assign n3538 = ~n3743 & (~n3472 | ~n4617); - assign n3539 = n3975 | Ni34 | n3199; - assign n3540 = ~n797 & n3539 & (~Ni33 | n3481); - assign n3541 = n3292 | n3550; - assign n3542 = n3541 & n3540 & (n3343 | n3483); - assign n3543 = n3294 | n3550; - assign n3544 = n3543 & n3540 & (n3351 | n3483); - assign n3545 = (n3297 | n3550) & (n3355 | n3483); - assign n3546 = n3545 & n3540; - assign n3547 = (n3542 | n1408) & (n3544 | n914); - assign n3548 = n807 & n3547 & (n3546 | n1702); - assign n3549 = n3364 | n3483; - assign n3550 = n1539 | n3953; - assign n3551 = n3549 & n3540 & (n3300 | n3550); - assign n3552 = n3371 | n3483; - assign n3553 = n3552 & n3540 & (n3302 | n3550); - assign n3554 = (n3305 | n3550) & (n3374 | n3483); - assign n3555 = n3554 & n3540; - assign n3556 = (n3551 | n1408) & (n3553 | n914); - assign n3557 = n807 & n3556 & (n3555 | n1702); - assign n3558 = n3213 | n3550; - assign n3559 = n3558 & n3540 & (n3378 | n3483); - assign n3560 = n3222 | n3550; - assign n3561 = n3560 & n3540 & (n3380 | n3483); - assign n3562 = (n3226 | n3550) & (n3354 | n3483); - assign n3563 = n3562 & n3540; - assign n3564 = (n3559 | n1408) & (n3561 | n914); - assign n3565 = n807 & n3564 & (n3563 | n1702); - assign n3566 = n3385 | n3483; - assign n3567 = n3566 & n3540 & (n3234 | n3550); - assign n3568 = n3387 | n3483; - assign n3569 = n3568 & n3540 & (n3240 | n3550); - assign n3570 = (n3242 | n3550) & (n3373 | n3483); - assign n3571 = n3570 & n3540; - assign n3572 = (n3567 | n1408) & (n3569 | n914); - assign n3573 = n807 & n3572 & (n3571 | n1702); - assign n3574 = n3316 | n3550; - assign n3575 = n3574 & n3540 & (n3396 | n3483); - assign n3576 = n3307 | n3550; - assign n3577 = n3576 & n3540 & (n3402 | n3483); - assign n3578 = n3318 | n3550; - assign n3579 = n3578 & n3540 & (n3409 | n3483); - assign n3580 = n3309 | n3550; - assign n3581 = n3580 & n3540 & (n3416 | n3483); - assign n3582 = n807 & (n3579 | n3893); - assign n3583 = (n3575 | n1408) & (n3577 | n914); - assign n3584 = n3582 & n3583 & (n3581 | n2109); - assign n3585 = n3424 | n3483; - assign n3586 = n3585 & n3540 & (n3319 | n3550); - assign n3587 = n3429 | n3483; - assign n3588 = n3587 & n3540 & (n3310 | n3550); - assign n3589 = n3436 | n3483; - assign n3590 = n3589 & n3540 & (n3321 | n3550); - assign n3591 = n3443 | n3483; - assign n3592 = n3591 & n3540 & (n3312 | n3550); - assign n3593 = n807 & (n3590 | n3893); - assign n3594 = (n3586 | n1408) & (n3588 | n914); - assign n3595 = n3593 & n3594 & (n3592 | n2109); - assign n3596 = n3268 | n3550; - assign n3597 = n3596 & n3540 & (n3449 | n3483); - assign n3598 = n3248 | n3550; - assign n3599 = n3598 & n3540 & (n3451 | n3483); - assign n3600 = n3273 | n3550; - assign n3601 = n3600 & n3540 & (n3453 | n3483); - assign n3602 = n3253 | n3550; - assign n3603 = n3602 & n3540 & (n3455 | n3483); - assign n3604 = n807 & (n3601 | n3893); - assign n3605 = (n3597 | n1408) & (n3599 | n914); - assign n3606 = n3604 & n3605 & (n3603 | n2109); - assign n3607 = n3460 | n3483; - assign n3608 = n3607 & n3540 & (n3277 | n3550); - assign n3609 = n3462 | n3483; - assign n3610 = n3609 & n3540 & (n3256 | n3550); - assign n3611 = n3464 | n3483; - assign n3612 = n3611 & n3540 & (n3282 | n3550); - assign n3613 = n3466 | n3483; - assign n3614 = n3613 & n3540 & (n3261 | n3550); - assign n3615 = n807 & (n3612 | n3893); - assign n3616 = (n3608 | n1408) & (n3610 | n914); - assign n3617 = n3615 & n3616 & (n3614 | n2109); - assign n3618 = n2254 | n3624; - assign n3619 = n3561 & ~n3635 & (n3222 | n3618); - assign n3620 = n3213 | n3618; - assign n3621 = ~n798 & n3283; - assign n3622 = n3620 & n3621 & (n3559 | n1929); - assign n3623 = Pi25 | ~n809; - assign n3624 = Pi25 | n3975; - assign n3625 = n3623 & n3563 & (n3226 | n3624); - assign n3626 = (n3622 | n3223) & (n3619 | n3224); - assign n3627 = ~Pi22 | ~n3227; - assign n3628 = n807 & n3626 & (n3625 | n3627); - assign n3629 = n3623 & n3571 & (n3242 | n3624); - assign n3630 = ~n3223 & (~n3621 | ~n4646); - assign n3631 = ~n3630 & (n3224 | (~n3635 & n4647)); - assign n3632 = n807 & n3631 & (n3629 | n3627); - assign n3633 = n3599 & ~n3635 & (n3248 | n3618); - assign n3634 = n3603 & ~n3635 & (n3253 | n3618); - assign n3635 = n798 | n3977; - assign n3636 = ~n3743 & (n3635 | ~n4654); - assign n3637 = ~n3737 & (n3635 | ~n4655); - assign n3638 = ~n2272 & (~n3621 | ~n4648); - assign n3639 = ~n3743 & (~n3621 | ~n4650); - assign n3640 = n3544 & ~n3635 & (n3294 | n3618); - assign n3641 = n3292 | n3618; - assign n3642 = n3641 & n3621 & (n3542 | n1929); - assign n3643 = n3623 & n3546 & (n3297 | n3624); - assign n3644 = (n3642 | n3223) & (n3640 | n3224); - assign n3645 = n807 & n3644 & (n3643 | n3627); - assign n3646 = n3623 & n3555 & (n3305 | n3624); - assign n3647 = ~n3223 & (~n3621 | ~n4634); - assign n3648 = ~n3647 & (n3224 | (~n3635 & n4635)); - assign n3649 = n807 & n3648 & (n3646 | n3627); - assign n3650 = n3577 & ~n3635 & (n3307 | n3618); - assign n3651 = n3581 & ~n3635 & (n3309 | n3618); - assign n3652 = ~n3743 & (n3635 | ~n4642); - assign n3653 = ~n3737 & (n3635 | ~n4643); - assign n3654 = ~n2272 & (~n3621 | ~n4636); - assign n3655 = ~n3743 & (~n3621 | ~n4638); - assign n3656 = ~n4739 & (~Pi17 | ~n4660 | ~n4661); - assign n3657 = ~n3327 & ~n4740 & (~Ni10 | n3656); - assign n3658 = (~n3707 & ~n4032) | (~Ni33 & (n3707 | ~n4032)); - assign n3659 = n3707 | n3805; - assign n3660 = n4662 & (~n4029 | (~n1543 & ~Ni13)); - assign n3661 = ~Ni47 | ~n3192; - assign n3662 = ~n900 & n3661 & (Pi20 | ~n3192); - assign n3663 = Ni30 | n801; - assign n3664 = Ni47 & (n801 | Ni30); - assign n3665 = n1353 & Ni30; - assign n3666 = n1463 & Ni30; - assign n3667 = Ni12 | ~n3727; - assign n3668 = n3665 & (n3666 | n3667); - assign n3669 = n1354 & Ni30; - assign n3670 = n1553 & n1542 & n1543; - assign n3671 = n4750 & (Ni12 | n3679); - assign n3672 = ~Pi26 & n3981; - assign n3673 = n3670 & n3671 & (Ni14 | n3672); - assign n3674 = (n3841 | n3696) & (n3838 | n2632); - assign n3675 = ~n3842 & (n3670 | (Pi24 & n3666)); - assign n3676 = n3695 & (Pi26 | n3666); - assign n3677 = n1446 | ~Ni11; - assign n3678 = n3674 & n3675 & (n3676 | n3677); - assign n3679 = Pi26 & n3981; - assign n3680 = (n3672 | n2632) & (n3679 | n3677); - assign n3681 = ~n3696 & ~n4775 & (n788 | ~n3841); - assign n3682 = n3840 & (~Pi23 | (n3670 & n3680)); - assign n3683 = ~Pi24 & n3666; - assign n3684 = ~n3681 & n3682 & (n3670 | n3683); - assign n3685 = ~n3696 & ~n4775 & (n795 | ~n3841); - assign n3686 = n3840 & (Pi23 | (n3670 & n3680)); - assign n3687 = ~n3685 & (n3670 | n3683) & n3686; - assign n3688 = Ni7 | Ni8; - assign n3689 = n3688 & n1670 & (Ni8 | Ni10); - assign n3690 = (n3687 | n3766) & (n3673 | n3689); - assign n3691 = (n3684 | n3937) & (n3678 | n2066); - assign n3692 = n3690 & n3691; - assign n3693 = ~n3692 & (~Ni6 | ~Ni5); - assign n3694 = n2632 | Pi26 | n3841; - assign n3695 = n3665 & (~Pi27 | n3666); - assign n3696 = ~Ni12 | n2750; - assign n3697 = n3694 & n3668 & (n3695 | n3696); - assign n3698 = n3665 & (~Pi26 | n3677 | n3841); - assign n3699 = n4663 & n4664 & (n3669 | n3982); - assign n3700 = n3698 & n3699 & (Ni11 | n3697); - assign n3701 = (Ni32 | n2399) & (n801 | ~Ni41); - assign n3702 = ~Ni5 & (~Ni31 | ~Ni6 | ~n3980); - assign n3703 = ~n3707 & (n780 | (~Ni6 & ~n3692)); - assign n3704 = Ni4 | n3711; - assign n3705 = ~n3703 & ~Ni2 & (Ni31 | n3704); - assign n3706 = n3701 & Ni30; - assign n3707 = Ni2 | Ni3; - assign n3708 = (n1353 | n3704) & (~n3700 | n3707); - assign n3709 = n3702 | n3711 | ~Ni4 | ~n4752; - assign n3710 = (~Ni5 | n3705) & (n3706 | n3983); - assign n3711 = Ni2 | ~Ni3; - assign n3712 = (~n3700 | n3707) & (n3711 | ~n4665); - assign n3713 = (~n780 | n3707) & (n3980 | n3983); - assign n3714 = ~Ni9 & ~Ni7; - assign n3715 = ~n3707 & (~n3957 | (n3714 & ~n3767)); - assign n3716 = (~n795 | ~Ni7) & (n3688 | n3950); - assign n3717 = n3716 & (Pi24 | ~Ni8); - assign n3718 = ~Ni10 | n3707 | n3717 | ~n3957; - assign n3719 = (~n788 | Ni10) & ~Ni9; - assign n3720 = (n773 | n3688) & (~Ni8 | n3719); - assign n3721 = (Ni10 | ~Ni7) & (n3720 | ~n3957); - assign n3722 = (~n789 & ~Ni14) | (Pi27 & (~n789 | Ni14)); - assign n3723 = n3722 & ~Ni11 & ~Ni13; - assign n3724 = (n785 | n1543) & (~Ni11 | ~n3761); - assign n3725 = n3724 & (Pi27 | ~Ni12); - assign n3726 = ~Ni14 | n3707 | n3725 | ~n3727; - assign n3727 = ~Ni14 | ~Ni13; - assign n3728 = n789 & ~Ni14 & Ni12; - assign n3729 = ~n1543 & n785 & Ni14; - assign n3730 = n3727 & (n3728 | n3729 | Ni13); - assign n3731 = ~n3707 & ((Ni11 & ~Ni14) | n3730); - assign n3732 = ~Ni42 | ~Ni43; - assign n3733 = Ni44 | ~Ni43; - assign n3734 = n3732 & (n2426 | n3733); - assign n3735 = ~Ni41 | ~Ni43; - assign n3736 = (n3740 | ~Ni43) & (n3844 | n3894); - assign n3737 = ~Pi16 | n1322; - assign n3738 = n3734 & n3736 & (n3735 | n3737); - assign n3739 = (n3737 | ~Ni43) & (n3844 | n3895); - assign n3740 = ~Pi16 | n3864; - assign n3741 = n3734 & n3739 & (n3735 | n3740); - assign n3742 = (n3738 & (n3741 | Ni40)) | (n3741 & ~Ni40); - assign n3743 = ~Pi16 | n3867; - assign n3744 = n3742 & (n3735 | n3743); - assign n3745 = ~Ni44 | ~Ni43; - assign n3746 = n3732 & (n2426 | n3745); - assign n3747 = n3746 & n3736 & (n3735 | n3737); - assign n3748 = n3746 & n3739 & (n3735 | n3740); - assign n3749 = (n3747 & (n3748 | Ni40)) | (n3748 & ~Ni40); - assign n3750 = n3749 & (n3735 | n3743); - assign n3751 = Ni31 | n784; - assign n3752 = (~n2345 | ~Ni43) & (~n3772 | n3844); - assign n3753 = (~Pi20 & n3750) | (n3744 & (Pi20 | n3750)); - assign n3754 = Ni42 | ~Ni43; - assign n3755 = n2426 | ~Ni40; - assign n3756 = n3733 | n3755; - assign n3757 = n3756 | (Ni30 & ~n3984); - assign n3758 = (n801 | Ni41) & (~Ni31 | n887); - assign n1090_1 = ~n3711; - assign n3760 = Ni4 & ~n3711 & ~n2418 & ~n3701; - assign n3761 = Pi27 | ~Pi26; - assign n3762 = (~Ni12 | ~n3723) & (n3677 | n3761); - assign n3763 = ~n3795 & (n3760 | (~n3758 & ~n3983)); - assign n3764 = Ni30 | n2418 | n3704 | ~n3973; - assign n3765 = n887 & (~Ni32 | Ni41); - assign n3766 = ~Ni10 | n2074 | ~Ni7; - assign n3767 = (~Pi24 & (n788 | Ni10)) | (n788 & ~Ni10); - assign n3768 = ~Ni8 | Ni9 | Ni7; - assign n3769 = (n795 | n3766) & (n3767 | n3768); - assign n3770 = n2418 | n3711 | n4764 | n4765; - assign n3771 = n1353 | n3983 | Ni33 | n3765; - assign n3772 = ~Pi16 & n3184; - assign n3773 = ~n3472 & (n2345 | n3772); - assign n986 = n2407 | n2408 | n2415 | ~n4379; - assign n3775 = ~n2417 & (Pi21 | n801) & n3810; - assign n946_1 = ~n3775; - assign n3777 = n900 & n3837 & (~Ni47 | ~n3711); - assign n936 = ~n3777; - assign n3779 = n3845 & ((n655 & Ni30) | ~n4050); - assign n3780 = ~n3754 & Ni41 & ~Pi16 & ~n806; - assign n3781 = n3846 & ~n4758 & (Pi20 | ~n3757); - assign n961_1 = n3781 | n3779 | n3780; - assign n3783 = Pi20 & (~n905 | (~Pi21 & ~n1116)); - assign n3784 = ~Pi20 & (~n905 | (~Pi21 & ~n1091)); - assign n3785 = Pi20 & (~n905 | (~Pi21 & ~n1249)); - assign n3786 = ~Pi20 & (~n905 | (~Pi21 & ~n1239)); - assign n3787 = Pi20 & (~n905 | (~Pi21 & ~n1196)); - assign n3788 = ~Pi20 & (~n905 | (~Pi21 & ~n1172)); - assign n3789 = ~n901 | n1209 | n3787 | n3788; - assign n3790 = Pi20 & (~n905 | (~Pi21 & ~n1281)); - assign n3791 = ~Pi20 & (~n905 | (~Pi21 & ~n1274)); - assign n3792 = ~n901 | n1288 | n3790 | n3791; - assign n3793 = n1540 & n1354; - assign n3794 = (~Pi27 | n1918) & n3793; - assign n3795 = ~Ni30 | ~Ni33; - assign n3796 = n1354 & (~n789 | ~Ni30); - assign n3797 = n1353 & (~n789 | n1463); - assign n3798 = ~Pi21 & ~n3796; - assign n3799 = ~Pi22 & ~n3796; - assign n3800 = ~Pi24 & (n3798 | n3799 | ~n4300); - assign n3801 = n1354 & (Pi27 | ~Ni30); - assign n3802 = n1353 & (Pi27 | n1463); - assign n3803 = Ni14 & ~n3801 & (Pi24 | ~n3802); - assign n3804 = ~n3803 & (n1540 | n2254); - assign n3805 = Ni7 | n2074; - assign n3806 = Ni34 & n3805 & (n3327 | ~n3995); - assign n3807 = ~n665 | Ni33; - assign n3808 = n2390 & (~Pi26 | ~n665) & n3807; - assign n3809 = n2400 & (~Pi27 | ~n665) & n3807; - assign n3810 = n903 & (~Ni45 | (~n2418 & ~n3704)); - assign n3811 = n2425 & (Ni42 | Ni47); - assign n3812 = n784 & n811; - assign n3813 = n802 & n2424; - assign n3814 = (n3824 | n2254) & (Pi27 | n3822); - assign n3815 = n801 & n811; - assign n3816 = n2649 & n3814 & (n3815 | n2643); - assign n3817 = (~Pi27 | n3037) & n3813; - assign n3818 = n2623 & (~Pi26 | ~Ni32); - assign n3819 = n802 & n811; - assign n3820 = (~Pi27 | n3812) & n3819; - assign n3821 = (~Pi26 | n3812) & n3820; - assign n3822 = n2419 & n812; - assign n3823 = (~Pi27 | n813) & n3815; - assign n3824 = n801 & n2424; - assign n3825 = n2424 & n812; - assign n3826 = n3820 & (Pi26 | n3812); - assign n3827 = n3969 & n3187; - assign n3828 = n800 & n3827 & (~Pi26 | n3751); - assign n3829 = n2406 & n3956; - assign n3830 = ~n3828 & (Pi23 | ~n3827 | n3829); - assign n3831 = n3972 & n3189; - assign n3832 = n800 & n3831 & (~Pi27 | n3751); - assign n3833 = ~n3832 & (Pi24 | n3829 | ~n3831); - assign n3834 = ~Pi22 & (n797 | (~n1539 & ~n3191)); - assign n3835 = ~Pi21 & (n797 | (~n1539 & n3185)); - assign n3836 = n3200 | ~Ni41; - assign n3837 = ~n3664 & (~Ni47 | (~n2418 & ~Ni4)); - assign n3838 = (~Pi26 | n3666) & n3695; - assign n3839 = (n3838 | n2632) & (n3676 | n3677); - assign n3840 = (~Pi24 | n3680) & n3839; - assign n3841 = n3665 & (Pi27 | n3666); - assign n3842 = ~Pi24 & (~n3680 | (~n3696 & ~n4775)); - assign n3843 = n3669 & (Ni11 | n3667); - assign n3844 = Ni41 | ~Ni43; - assign n3845 = ~n806 & (Ni30 | ~n986_1 | n3732); - assign n3846 = Pi18 & ~Pi17; - assign n3847 = n18 | n2254; - assign n3848 = n2254 | ~n3184; - assign n3849 = n677 & ~Ni47; - assign n3850 = ~n18 | n2416; - assign n3851 = Ni36 | n1241; - assign n3852 = Ni37 | Ni36; - assign n3853 = Ni38 | n3852; - assign n3854 = n3853 | ~Ni39; - assign n3855 = Ni39 | n3853; - assign n3856 = Ni32 | n2434; - assign n3857 = Pi20 | n2254; - assign n3858 = Pi25 | n3857; - assign n3859 = ~Pi20 | n2254; - assign n3860 = Pi25 | n3859; - assign n3861 = Pi20 & (~n905 | (~Pi21 & ~n868)); - assign n3862 = ~Pi20 & (~n905 | (~Pi21 & ~n835)); - assign n3863 = ~n901 | n909 | n3861 | n3862; - assign n3864 = Pi19 | ~Pi17; - assign n3865 = Pi20 & (~n905 | (~Pi21 & ~n1068)); - assign n3866 = ~Pi20 & (~n905 | (~Pi21 & ~n1053)); - assign n3867 = Pi17 | Pi19; - assign n3868 = ~Ni32 | n2530; - assign n3869 = Ni32 | n2530; - assign n3870 = Pi16 | Pi15; - assign n3871 = Pi20 & (~n905 | (~Pi21 & ~n1004)); - assign n3872 = ~Pi20 & (~n905 | (~Pi21 & ~n993)); - assign n3873 = ~n901 | n1015 | n3871 | n3872; - assign n3874 = n677 & ~Ni45; - assign n3875 = Pi20 & (~n905 | (~Pi21 & ~n1229)); - assign n3876 = ~Pi20 & (~n905 | (~Pi21 & ~n1220)); - assign n3877 = Pi16 | ~Pi15; - assign n3878 = Pi20 & (~n905 | (~Pi21 & ~n954)); - assign n3879 = ~Pi20 & (~n905 | (~Pi21 & ~n930)); - assign n3880 = ~n901 | n978 | n3878 | n3879; - assign n3881 = Pi20 & (~n905 | (~Pi21 & ~n1152)); - assign n3882 = ~Pi20 & (~n905 | (~Pi21 & ~n1138)); - assign n3883 = ~n901 | n1211 | n3881 | n3882; - assign n3884 = ~Pi16 | Pi15; - assign n3885 = Pi20 & (~n905 | (~Pi21 & ~n1029)); - assign n3886 = ~Pi20 & (~n905 | (~Pi21 & ~n1022)); - assign n3887 = ~n901 | n1040 | n3885 | n3886; - assign n3888 = Pi20 & (~n905 | (~Pi21 & ~n1267)); - assign n3889 = ~Pi20 & (~n905 | (~Pi21 & ~n1260)); - assign n3890 = ~n901 | n1290 | n3888 | n3889; - assign n3891 = ~Pi16 | ~Pi15; - assign n3892 = Ni10 | ~n3327; - assign n3893 = ~Pi19 | n3857; - assign n3894 = Pi16 | n3864; - assign n3895 = Pi16 | n1322; - assign n3896 = Ni6 | Ni4 | Ni5; - assign n3897 = Ni11 | Ni10; - assign n3898 = n1446 & Ni11; - assign n3899 = n3848 | n3761; - assign n3900 = ~n3761 | n3848; - assign n3901 = n3857 | n3761; - assign n3902 = n3859 | n3761; - assign n3903 = ~n3761 | n3859; - assign n3904 = Pi27 | n1495; - assign n3905 = Pi27 | n1497; - assign n3906 = ~Pi27 | n1495; - assign n3907 = ~Pi27 | n1497; - assign n3908 = Pi27 | n3857; - assign n3909 = Pi27 | n3859; - assign n3910 = ~Pi27 | n3857; - assign n3911 = ~Pi27 | n3859; - assign n3912 = Ni13 | Ni14; - assign n3913 = n3848 | n789; - assign n3914 = ~n789 | n3848; - assign n3915 = n3857 | n789; - assign n3916 = n3859 | n789; - assign n3917 = ~n789 | n3859; - assign n3918 = n3799 | n3798; - assign n3919 = Ni11 | ~Ni12; - assign n3920 = Pi27 | n1923; - assign n3921 = ~Pi27 | n1923; - assign n3922 = Pi27 | n1929; - assign n3923 = ~Pi27 | n2372; - assign n3924 = n1923 | n789; - assign n3925 = ~n789 | n1923; - assign n3926 = n2372 | n789; - assign n3927 = n1314 | n789; - assign n3928 = Ni13 | n3919; - assign n3929 = n1923 | n3761; - assign n3930 = n1923 | ~n3761; - assign n3931 = n2372 | n3761; - assign n3932 = n1314 | n3761; - assign n3933 = n3848 | n788; - assign n3934 = ~n788 | n3848; - assign n3935 = n3857 | n788; - assign n3936 = ~n788 | n3857; - assign n3937 = Ni10 | n3768; - assign n3938 = ~Pi24 | n1495; - assign n3939 = ~Pi24 | n1497; - assign n3940 = Pi24 | n3857; - assign n3941 = Pi24 | n3859; - assign n3942 = ~Pi24 | n3857; - assign n3943 = ~Pi24 | n3859; - assign n3944 = Pi15 | n3327; - assign n3945 = n3848 | n795; - assign n3946 = ~n795 | n3848; - assign n3947 = n3857 | n795; - assign n3948 = ~n795 | n3857; - assign n3949 = ~Pi25 | n2079; - assign n3950 = ~n18 | Ni33; - assign n3951 = ~Pi25 | Ni34 | n1539 | n3950; - assign n3952 = n2254 | n2079; - assign n3953 = ~Ni34 | Ni33; - assign n3954 = n3952 | n3953; - assign n3955 = n3954 & ~n792 & n2085; - assign n3956 = Ni32 & Ni33; - assign n3957 = ~Ni10 | ~Ni9; - assign n3958 = Ni31 | n3795; - assign n3959 = Ni39 | n3852; - assign n3960 = n1241 | ~Ni38; - assign n3961 = n3852 | ~Ni39; - assign n3962 = n2389 | ~Ni38; - assign n3963 = n2518 & n2430 & n2431; - assign n3964 = n2523 & n2430 & n2444; - assign n3965 = n2427 & n2430 & n2431; - assign n3966 = n2442 & n2430 & n2444; - assign n3967 = ~Pi26 | Pi24; - assign n3968 = ~Ni37 | ~Ni38; - assign n3969 = Ni32 | ~Ni40; - assign n3970 = Ni33 | n3751; - assign n3971 = ~Ni33 | n3751; - assign n3972 = Ni32 | ~Ni41; - assign n3973 = Ni31 & Ni33; - assign n3974 = Ni38 | n3198; - assign n3975 = Ni33 | n1539; - assign n3976 = Ni38 | n3200; - assign n3977 = n3834 | n3835; - assign n3978 = ~Pi17 | Pi16; - assign n3979 = ~Pi17 | ~Pi16; - assign n3980 = ~Ni30 | n3701; - assign n3981 = ~Pi27 & n3669; - assign n3982 = n3688 | ~n3957; - assign n3983 = n3704 | Ni6 | ~Ni5; - assign n3984 = ~Ni32 & Ni30; - assign n3985 = n3707 | n2393; - assign n3986 = n2403 | Ni7 | n3707; - assign n3987 = ~n4673 & (~n18 | ~n3707); - assign n1026_1 = ~n3987; - assign n3989 = (~Ni10 & ~n1944) | (~n1718 & (Ni10 | ~n1944)); - assign n3990 = (Pi15 & n4678) | (n4677 & (~Pi15 | n4678)); - assign n3991 = ~n4687 & (~Pi17 | ~n4171 | ~n4172); - assign n3992 = ~n4686 & (Ni10 | ~n4195 | ~n4197); - assign n3993 = n3797 & (n1540 | n2254) & ~n3800; - assign n3994 = (~Ni10 | n2370) & n4700; - assign n3995 = ~n4701 & (~Pi17 | (n4375 & n4376)); - assign n3996 = (~Ni10 & ~n3060) | (~n2867 & (Ni10 | ~n3060)); - assign n3997 = (Pi15 & n4715) | (n4714 & (~Pi15 | n4715)); - assign n3998 = ~n4725 & (~Pi17 | ~n4434 | ~n4435); - assign n3999 = ~Pi22 & ~n3812 & (~Pi27 | ~n3819); - assign n4000 = ~n4713 & (~Ni14 | ~n4448 | ~n4449); - assign n4001 = (n4196 | n3060) & (Ni11 | n3061); - assign n4002 = ~n3175 & n4001 & (n3928 | ~n4000); - assign n4003 = (~Pi23 & n4724) | (~n2626 & (Pi23 | n4724)); - assign n4004 = (~n788 & ~n3816) | (~n2630 & (n788 | ~n3816)); - assign n4005 = (Pi24 & ~n3816) | (~n2630 & (~Pi24 | ~n3816)); - assign n4006 = (Pi24 & n4710) | (~n2626 & (~Pi24 | n4710)); - assign n4007 = (Pi24 & n4712) | (~n2636 & (~Pi24 | n4712)); - assign n4008 = (Pi23 & n4724) | (~n2626 & (~Pi23 | n4724)); - assign n4009 = (~n795 & ~n3816) | (~n2630 & (n795 | ~n3816)); - assign n4010 = n3896 & (n3178 | n3179 | ~n4589); - assign n4011 = n3969 & (~Pi23 | n3970); - assign n4012 = n3187 & n4011 & (~Ni40 | n3971); - assign n4013 = n4728 & (n2393 | (n4590 & n3827)); - assign n4014 = (~n2403 & n4729) | (~n4013 & (n2403 | n4729)); - assign n4015 = (~Pi24 | n3970) & n3972; - assign n4016 = n3189 & n4015 & (~Ni41 | n3971); - assign n4017 = n4730 & (n2393 | (n4591 & n3831)); - assign n4018 = (~n2403 & n4731) | (~n4017 & (n2403 | n4731)); - assign n4019 = ~n3773 & (n3737 | (n3472 & n4607)); - assign n4020 = ~n3475 & (n3895 | (n3472 & n4605)); - assign n4021 = ~n3474 & (n3740 | (n3472 & n4603)); - assign n4022 = n4608 & (n3894 | (n4602 & n3472)); - assign n4023 = n4022 & n4021 & n4019 & n4020; - assign n4024 = ~n3773 & (n3737 | (n3472 & n4628)); - assign n4025 = ~n3534 & (n3895 | (n3472 & n4626)); - assign n4026 = ~n3533 & (n3740 | (n3472 & n4624)); - assign n4027 = n4629 & (n3894 | (n4623 & n3472)); - assign n4028 = n4027 & n4026 & n4024 & n4025; - assign n4029 = ~n4749 & (~Ni10 | (~n4747 & ~n4748)); - assign n4030 = (~Pi20 & n3324) | (n3315 & (Pi20 | n3324)); - assign n4031 = (~Pi20 & n3287) | (n3265 & (Pi20 | n3287)); - assign n4032 = n3805 & (n3328 | n3329 | n3330); - assign n4033 = ~Ni4 | n780 | n3693; - assign n4034 = n4033 & ~n4751 & (Ni5 | ~n3692); - assign n4035 = ~n4755 & (~Ni4 | ~Ni2); - assign n1081 = ~n4035; - assign n4037 = n3957 | ~Ni8 | ~Ni7; - assign n4038 = n3688 & (n795 | ~Ni10 | n2074); - assign n4039 = n4037 & n4038 & (Ni7 | ~n3957); - assign n4040 = (~n3707 & ~n4039) | (~Ni7 & (n3707 | ~n4039)); - assign n1066_1 = ~n4040; - assign n4042 = (~Ni10 & (n3707 | n3721)) | (~n3707 & n3721); - assign n1051 = ~n4042; - assign n4044 = (Ni11 & (n1542 | n3727)) | (n1542 & ~n3727); - assign n4045 = n1543 & n4044 & (n1446 | n3761); - assign n4046 = (~n3707 & ~n4045) | (~Ni11 & (n3707 | ~n4045)); - assign n1046_1 = ~n4046; - assign n4048 = ~n4757 & (Ni12 | n3707 | n3727); - assign n1041_1 = ~n4048; - assign n4050 = ~n4759 & (~n3733 | ~Ni42 | ~Ni39); - assign n4051 = (~Pi26 | n4760) & n4761; - assign n4052 = (~Pi23 | n4762) & n4763; - assign n4053 = (n848 | n3857) & (n879 | n3859); - assign n4054 = (n940 | n3857) & (n964 | n3859); - assign n4055 = n1055 | (~Ni37 & n817); - assign n4056 = n1051_1 | (~Ni37 & n817); - assign n4057 = n1070 | (~Ni37 & n853); - assign n4058 = n1067 | (~Ni37 & n853); - assign n4059 = (n1060 | n3857) & (n1074 | n3859); - assign n4060 = (n1101 | n3857) & (n1126 | n3859); - assign n4061 = n1140 | (~Ni37 & n817); - assign n4062 = n1137 | (~Ni37 & n817); - assign n4063 = n1154 | (~Ni37 & n853); - assign n4064 = n1151 | (~Ni37 & n853); - assign n4065 = (n1144 | n3857) & (n1158 | n3859); - assign n4066 = (n1182 | n3857) & (n1206 | n3859); - assign n4067 = (n911 | ~n3772) & (n980 | ~n2345); - assign n4068 = n975 | n1497; - assign n4069 = n4068 & (n3894 | (~n3863 & n4053)); - assign n4070 = ~n1307 & (n3895 | (~n1295 & n4060)); - assign n4071 = n3850 | Ni32 | n884; - assign n4072 = n3850 | Ni32 | n967; - assign n4073 = (n999 | n3857) & (n1008 | n3859); - assign n4074 = (n1026 | n3857) & (n1033 | n3859); - assign n4075 = (n1226 | n3857) & (n1233 | n3859); - assign n4076 = (n1245 | n3857) & (n1253 | n3859); - assign n4077 = (n1264 | n3857) & (n1271 | n3859); - assign n4078 = (n1278 | n3857) & (n1285 | n3859); - assign n4079 = (n1017 | ~n3772) & (n1042 | ~n2345); - assign n4080 = n1037 | n1497; - assign n4081 = n4080 & (n3894 | (~n3873 & n4073)); - assign n4082 = ~n1300 & (n3895 | (~n1297 & n4076)); - assign n4083 = (n1102 | n3893) & (n1127 | n2109); - assign n4084 = n4083 & (n1061_1 | n1408); - assign n4085 = (n914 | n1075) & (Pi19 | ~n1306); - assign n4086 = (n1246 | n3893) & (n1254 | n2109); - assign n4087 = n4086 & (n1227 | n1408); - assign n4088 = (n914 | n1234) & (Pi19 | ~n1299); - assign n4089 = (n1215 | n3884) & (n1294 | n3891); - assign n4090 = (n915 | n3870) & (n1020 | n3877); - assign n4091 = (n983 | n3884) & (n1045 | n3891); - assign n4092 = (n848 | n3858) & (n879 | n3860); - assign n4093 = (n1060 | n3858) & (n1074 | n3860); - assign n4094 = (n1101 | n3858) & (n1126 | n3860); - assign n4095 = (n898 | n1923) & (n911 | ~n3184); - assign n4096 = Pi25 | n3847; - assign n4097 = (n999 | n3858) & (n1008 | n3860); - assign n4098 = (n1226 | n3858) & (n1233 | n3860); - assign n4099 = (n1245 | n3858) & (n1253 | n3860); - assign n4100 = (n1013 | n1923) & (n1017 | ~n3184); - assign n4101 = (n940 | n3858) & (n964 | n3860); - assign n4102 = (n1144 | n3858) & (n1158 | n3860); - assign n4103 = (n1182 | n3858) & (n1206 | n3860); - assign n4104 = (n976 | n1923) & (n980 | ~n3184); - assign n4105 = (n1026 | n3858) & (n1033 | n3860); - assign n4106 = (n1264 | n3858) & (n1271 | n3860); - assign n4107 = (n1278 | n3858) & (n1285 | n3860); - assign n4108 = (n1038 | n1923) & (n1042 | ~n3184); - assign n4109 = (n1332 | n3870) & (n1350 | n3877); - assign n4110 = (n1323 | n3884) & (n1341 | n3891); - assign n4111 = (n1937 | n3894) & (n1700 | n3740); - assign n4112 = n4111 & (n1961 | n2272); - assign n4113 = (n1958 | n3895) & (n1708 | n3743); - assign n4114 = n4113 & (n1709 | n3737); - assign n4115 = (n1704 | n3894) & (n1706 | n3740); - assign n4116 = n4115 & (n1711 | n2272); - assign n4117 = (n1712 | n3895) & (n1714 | n3743); - assign n4118 = n4117 & (n1715 | n3737); - assign n4119 = n1759 & n1404; - assign n4120 = n1769 & n1400; - assign n4121 = n1829 & n1429; - assign n4122 = n1839 & n1425; - assign n4123 = n1723 & n1417; - assign n4124 = n1734 & n1413; - assign n4125 = n1794 & n1441; - assign n4126 = n1804 & n1437; - assign n4127 = (n1687 | n3870) & (n1695 | n3877); - assign n4128 = (n1691 | n3884) & (n1699 | n3891); - assign n4129 = n1785 & n1361; - assign n4130 = n1855 & n1380; - assign n4131 = n1750 & n1371; - assign n4132 = n1820 & n1389; - assign n4133 = (n1674 | n3870) & (n1680 | n3877); - assign n4134 = (n1677 | n3884) & (n1683 | n3891); - assign n4135 = n1518 & n1357; - assign n4136 = n1530 & n1367; - assign n4137 = (n4136 | n3858) & (n1373 | n3860); - assign n4138 = n1516 & n1400; - assign n4139 = (n1407 | n3858) & (n4138 | n3860); - assign n4140 = n1510 & n1402; - assign n4141 = n1512 & n1404; - assign n4142 = (n4140 | n3858) & (n4141 | n3860); - assign n4143 = n1528 & n1413; - assign n4144 = (n1420 | n3858) & (n4143 | n3860); - assign n4145 = n1522 & n1415; - assign n4146 = n1524 & n1417; - assign n4147 = (n4145 | n3858) & (n4146 | n3860); - assign n4148 = (n1926 | n1923) & (n1938 | n3894); - assign n4149 = n1478 & n1376; - assign n4150 = n1490 & n1385; - assign n4151 = (n4150 | n3858) & (n1391 | n3860); - assign n4152 = n1476 & n1425; - assign n4153 = (n1432 | n3858) & (n4152 | n3860); - assign n4154 = n1470 & n1427; - assign n4155 = n1472 & n1429; - assign n4156 = (n4154 | n3858) & (n4155 | n3860); - assign n4157 = n1488 & n1437; - assign n4158 = (n1444 | n3858) & (n4157 | n3860); - assign n4159 = n1482 & n1439; - assign n4160 = n1484 & n1441; - assign n4161 = (n4159 | n3858) & (n4160 | n3860); - assign n4162 = (n1922 | n1923) & (n1930 | n3894); - assign n4163 = (n1961 | n1701) & (n1958 | n1702); - assign n4164 = n4163 & (n1713 | n3877); - assign n4165 = (n1710 | n3884) & (n1716 | n3891); - assign n4166 = (n1937 | n1701) & (n1360 | n1702); - assign n4167 = n4166 & (n1705 | n3877); - assign n4168 = (n1703 | n3884) & (n1707 | n3891); - assign n4169 = (n1409 | n3870) & (n1433 | n3877); - assign n4170 = (n1421 | n3884) & (n1445 | n3891); - assign n4171 = (n1365 | n3870) & (n1383 | n3877); - assign n4172 = (n1374 | n3884) & (n1392 | n3891); - assign n4173 = n1786 | n3924; - assign n4174 = n2026 | ~n3184; - assign n4175 = n1856 | n3924; - assign n4176 = n1751 | n3924; - assign n4177 = n1821 | n3924; - assign n4178 = (n2045 | n3870) & (n2063 | n3877); - assign n4179 = (n2036 | n3884) & (n2054 | n3891); - assign n4180 = n1360 | n3920; - assign n4181 = n1987 | ~n3184; - assign n4182 = n1379 | n3920; - assign n4183 = n1370 | n3920; - assign n4184 = n1388 | n3920; - assign n4185 = (n2006 | n3870) & (n2024 | n3877); - assign n4186 = (n1997 | n3884) & (n2015 | n3891); - assign n4187 = n1786 | n3929; - assign n4188 = n1946 | ~n3184; - assign n4189 = n1856 | n3929; - assign n4190 = n1751 | n3929; - assign n4191 = n1821 | n3929; - assign n4192 = (n1967 | n3870) & (n1985 | n3877); - assign n4193 = (n1956 | n3884) & (n1976 | n3891); - assign n4194 = n3928 | n4675 | n4676; - assign n4195 = n4194 & (n3677 | (n4193 & n4192)); - assign n4196 = n1452 & ~n3898; - assign n4197 = (n4196 | n1944) & (Ni11 | n1945); - assign n4198 = n1787 | n3899; - assign n4199 = n1455 | ~n3184; - assign n4200 = n1857 | n3899; - assign n4201 = n1752 | n3899; - assign n4202 = n1822 | n3899; - assign n4203 = (n1783 | n3908) & (n1673 | n3909); - assign n4204 = (n1777 | n3910) & (n1780 | n3911); - assign n4205 = (n1748 | n3908) & (n1676 | n3909); - assign n4206 = (n1742 | n3910) & (n1745 | n3911); - assign n4207 = (n1686 | n3908) & (n4120 | n3909); - assign n4208 = (n1768 | n3910) & (n1771 | n3911); - assign n4209 = (n1764 | n3908) & (n4119 | n3909); - assign n4210 = (n1758 | n3910) & (n1761 | n3911); - assign n4211 = (n1690 | n3908) & (n4124 | n3909); - assign n4212 = (n1733 | n3910) & (n1736 | n3911); - assign n4213 = (n1728 | n3908) & (n4123 | n3909); - assign n4214 = (n1722 | n3910) & (n1725 | n3911); - assign n4215 = (n4129 | n3904) & (n4131 | n3905); - assign n4216 = n1752 | n3907; - assign n4217 = n4216 & (n3894 | (n4204 & n4203)); - assign n4218 = n4217 & (n3740 | (n4206 & n4205)); - assign n4219 = ~n1862 & (n3895 | (n4209 & n4210)); - assign n4220 = n4219 & (n3743 | (n4212 & n4211)); - assign n4221 = n1552 & (n3737 | (n4214 & n4213)); - assign n4222 = (n1853 | n3908) & (n1679 | n3909); - assign n4223 = (n1847 | n3910) & (n1850 | n3911); - assign n4224 = (n1818 | n3908) & (n1682 | n3909); - assign n4225 = (n1812 | n3910) & (n1815 | n3911); - assign n4226 = (n1694 | n3908) & (n4122 | n3909); - assign n4227 = (n1838 | n3910) & (n1841 | n3911); - assign n4228 = (n1834 | n3908) & (n4121 | n3909); - assign n4229 = (n1828 | n3910) & (n1831 | n3911); - assign n4230 = (n1698 | n3908) & (n4126 | n3909); - assign n4231 = (n1803 | n3910) & (n1806 | n3911); - assign n4232 = (n1799 | n3908) & (n4125 | n3909); - assign n4233 = (n1793 | n3910) & (n1796 | n3911); - assign n4234 = (n4130 | n3904) & (n4132 | n3905); - assign n4235 = n1822 | n3907; - assign n4236 = n4235 & (n3894 | (n4223 & n4222)); - assign n4237 = n4236 & (n3740 | (n4225 & n4224)); - assign n4238 = ~n1861 & (n3895 | (n4228 & n4229)); - assign n4239 = n4238 & (n3743 | (n4231 & n4230)); - assign n4240 = n1552 & (n3737 | (n4233 & n4232)); - assign n4241 = n1787 | n3913; - assign n4242 = ~n3184 | ~n3918; - assign n4243 = n1857 | n3913; - assign n4244 = n1752 | n3913; - assign n4245 = n1822 | n3913; - assign n4246 = (n1790 | n3870) & (n1860 | n3877); - assign n4247 = (n1755 | n3884) & (n1825 | n3891); - assign n4248 = (n1917 | n3677) & (n1718 | ~n3898); - assign n4249 = (~Ni14 & n4300) | (n1552 & (Ni14 | n4300)); - assign n4250 = n3804 & (~Pi23 | n4249); - assign n4251 = n1507 | n3933; - assign n4252 = ~n794 | ~n3184; - assign n4253 = n1466 | n3933; - assign n4254 = n1509 | n3933; - assign n4255 = n1469 | n3933; - assign n4256 = (n1578 | n3870) & (n1602 | n3877); - assign n4257 = (n1566 | n3884) & (n1590 | n3891); - assign n4258 = (n1540 | n2254) & (Pi24 | n3801); - assign n4259 = (n4135 | n3940) & (n1364 | n3941); - assign n4260 = (n1519 | n3942) & (n1521 | n3943); - assign n4261 = (n4136 | n3940) & (n1373 | n3941); - assign n4262 = (n1531 | n3942) & (n1533 | n3943); - assign n4263 = (n1407 | n3940) & (n4138 | n3941); - assign n4264 = (n1515 | n3942) & (n1517 | n3943); - assign n4265 = (n4140 | n3940) & (n4141 | n3941); - assign n4266 = (n1511 | n3942) & (n1513 | n3943); - assign n4267 = (n1420 | n3940) & (n4143 | n3941); - assign n4268 = (n1527 | n3942) & (n1529 | n3943); - assign n4269 = (n4145 | n3940) & (n4146 | n3941); - assign n4270 = (n1523 | n3942) & (n1525 | n3943); - assign n4271 = (n1507 | n3938) & (n1509 | n3939); - assign n4272 = ~n1537 & (n3740 | (n4261 & n4262)); - assign n4273 = n4271 & n4272 & (Pi24 | n1536); - assign n4274 = ~n1538 & (n3895 | (n4265 & n4266)); - assign n4275 = n4274 & (n3743 | (n4268 & n4267)); - assign n4276 = n1460 & (n3737 | (n4270 & n4269)); - assign n4277 = (n4149 | n3940) & (n1382 | n3941); - assign n4278 = (n1479 | n3942) & (n1481 | n3943); - assign n4279 = (n4150 | n3940) & (n1391 | n3941); - assign n4280 = (n1491 | n3942) & (n1493 | n3943); - assign n4281 = (n1432 | n3940) & (n4152 | n3941); - assign n4282 = (n1475 | n3942) & (n1477 | n3943); - assign n4283 = (n4154 | n3940) & (n4155 | n3941); - assign n4284 = (n1471 | n3942) & (n1473 | n3943); - assign n4285 = (n1444 | n3940) & (n4157 | n3941); - assign n4286 = (n1487 | n3942) & (n1489 | n3943); - assign n4287 = (n4159 | n3940) & (n4160 | n3941); - assign n4288 = (n1483 | n3942) & (n1485 | n3943); - assign n4289 = (n1466 | n3938) & (n1469 | n3939); - assign n4290 = ~n1500 & (n3895 | (n4283 & n4284)); - assign n4291 = (n1505 | n2367) & (n1462 | n1544); - assign n4292 = n3804 & (Pi23 | n4249); - assign n4293 = n1507 | n3945; - assign n4294 = ~n796 | ~n3184; - assign n4295 = n1466 | n3945; - assign n4296 = n1509 | n3945; - assign n4297 = n1469 | n3945; - assign n4298 = (n1637 | n3870) & (n1661 | n3877); - assign n4299 = (n1625 | n3884) & (n1649 | n3891); - assign n4300 = n2025 | n2254; - assign n4301 = ~n2386 & (n2382 | n3894); - assign n4302 = (n2385 | n3740) & (n2381 | n2272); - assign n4303 = (n2380 | n3895) & (n2384 | n3743); - assign n4304 = (n2378 | n3740) & (n2374 | n2272); - assign n4305 = ~n2379 & n4304 & (n2375 | n3894); - assign n4306 = (n2373 | n3895) & (n2377 | n3743); - assign n4307 = n2371 & n4306 & (n2376 | n3737); - assign n4308 = (n2196 | n3949) & (~n1081_1 | n3951); - assign n4309 = n2105 & (~Pi25 | n2313); - assign n4310 = (n2228 | n3949) & (~n1235 | n3951); - assign n4311 = n2120 & (~Pi25 | n2277); - assign n4312 = (n2212 | n3949) & (~n1165 | n3951); - assign n4313 = n2113 & (~Pi25 | n2320); - assign n4314 = (n2244 | n3949) & (~n1273 | n3951); - assign n4315 = n2127 & (~Pi25 | n2284); - assign n4316 = (n2203 | n3870) & (n2235 | n3877); - assign n4317 = (n2219 | n3884) & (n2251 | n3891); - assign n4318 = (n2145 | n3870) & (n2173 | n3877); - assign n4319 = (n2159 | n3884) & (n2187 | n3891); - assign n4320 = (n2347 | n3847) & (n2140 | n3952); - assign n4321 = (n2348 | n3847) & (n2154 | n3952); - assign n4322 = (n2359 | n3847) & (n2132 | n3952); - assign n4323 = (n2362 | n3847) & (n2146 | n3952); - assign n4324 = (n2357 | n3847) & (n2188 | n3952); - assign n4325 = (n2358 | n3847) & (n2196 | n3952); - assign n4326 = (n2360 | n3847) & (n2204 | n3952); - assign n4327 = (n2361 | n3847) & (n2212 | n3952); - assign n4328 = ~n2363 & (n3740 | (n3955 & n4323)); - assign n4329 = n4328 & (n2272 | (n4324 & n3955)); - assign n4330 = ~n2364 & (n3895 | (n3955 & n4325)); - assign n4331 = n4330 & (n3737 | (n4327 & n3955)); - assign n4332 = (n2351 | n3847) & (n2136 | n3952); - assign n4333 = (n2354 | n3847) & (n2150 | n3952); - assign n4334 = (n2349 | n3847) & (n2192 | n3952); - assign n4335 = (n2350 | n3847) & (n2197 | n3952); - assign n4336 = (n2352 | n3847) & (n2208 | n3952); - assign n4337 = (n2353 | n3847) & (n2213 | n3952); - assign n4338 = ~n2355 & (n3740 | (n3955 & n4333)); - assign n4339 = n4338 & (n2272 | (n4334 & n3955)); - assign n4340 = ~n2356 & (n3895 | (n3955 & n4335)); - assign n4341 = n4340 & (n3737 | (n4337 & n3955)); - assign n4342 = ~n2365 & (~n3772 | (n3955 & n4320)); - assign n4343 = (n2327 | n3847) & (n2168 | n3952); - assign n4344 = (n2328 | n3847) & (n2182 | n3952); - assign n4345 = (n2339 | n3847) & (n2160 | n3952); - assign n4346 = (n2342 | n3847) & (n2174 | n3952); - assign n4347 = (n2337 | n3847) & (n2220 | n3952); - assign n4348 = (n2338 | n3847) & (n2228 | n3952); - assign n4349 = (n2340 | n3847) & (n2236 | n3952); - assign n4350 = (n2341 | n3847) & (n2244 | n3952); - assign n4351 = ~n2343 & (n3740 | (n3955 & n4346)); - assign n4352 = n4351 & (n2272 | (n4347 & n3955)); - assign n4353 = ~n2344 & (n3895 | (n3955 & n4348)); - assign n4354 = n4353 & (n3737 | (n4350 & n3955)); - assign n4355 = (n2331 | n3847) & (n2164 | n3952); - assign n4356 = (n2334 | n3847) & (n2178 | n3952); - assign n4357 = (n2329 | n3847) & (n2224 | n3952); - assign n4358 = (n2330 | n3847) & (n2229 | n3952); - assign n4359 = (n2332 | n3847) & (n2240 | n3952); - assign n4360 = (n2333 | n3847) & (n2245 | n3952); - assign n4361 = ~n2335 & (n3740 | (n3955 & n4356)); - assign n4362 = n4361 & (n2272 | (n4357 & n3955)); - assign n4363 = ~n2336 & (n3895 | (n3955 & n4358)); - assign n4364 = n4363 & (n3737 | (n4360 & n3955)); - assign n4365 = ~n2346 & (~n3772 | (n3955 & n4343)); - assign n4366 = (n2314 | n3895) & (n2318 | n3743); - assign n4367 = (n2298 | n3895) & (n2302 | n3743); - assign n4368 = (n2292 | ~n3772) & (n2294 | ~n2345); - assign n4369 = (n2278 | n3895) & (n2282 | n3743); - assign n4370 = (n2261 | n3895) & (n2265 | n3743); - assign n4371 = ~n3327 | n4698 | n4699; - assign n4372 = (~Pi20 & n2326) | (n2309 & (Pi20 | n2326)); - assign n4373 = (n2110 | n3870) & (n2124 | n3877); - assign n4374 = (n2117 | n3884) & (n2131 | n3891); - assign n4375 = (n2087 | n3870) & (n2097 | n3877); - assign n4376 = (n2092 | n3884) & (n2102 | n3891); - assign n4377 = (n1238 | n3958) & (~Pi23 | n3807); - assign n4378 = (n886 | n3958) & (~Pi24 | n3807); - assign n4379 = (Pi15 | n2414) & (n2413 | ~n3846); - assign n4380 = (n2851 | n3894) & (n2853 | n3740); - assign n4381 = n4380 & (n2857 | n2272); - assign n4382 = (n2858 | n3895) & (n2860 | n3743); - assign n4383 = n4382 & (n2861 | n3737); - assign n4384 = (n3046 | n3894) & (n2855 | n3740); - assign n4385 = n4384 & (n3094 | n2272); - assign n4386 = (n3091 | n3895) & (n2863 | n3743); - assign n4387 = n4386 & (n2864 | n3737); - assign n4388 = n2822 & n2542; - assign n4389 = n2820 & n2527; - assign n4390 = n2838 & n2592; - assign n4391 = n2836 & n2582; - assign n4392 = n2830 & n2568; - assign n4393 = n2828 & n2554; - assign n4394 = n2846 & n2616; - assign n4395 = n2844 & n2606; - assign n4396 = (n2826 | n3870) & (n2842 | n3877); - assign n4397 = (n2834 | n3884) & (n2850 | n3891); - assign n4398 = n2797 & n2457; - assign n4399 = n2809 & n2497; - assign n4400 = n2803 & n2480; - assign n4401 = n2815 & n2514; - assign n4402 = (n2800 | n3870) & (n2812 | n3877); - assign n4403 = (n2806 | n3884) & (n2818 | n3891); - assign n4404 = n2436 & n2440; - assign n4405 = n2464 & n2467; - assign n4406 = (n4405 | n3858) & (n2482 | n3860); - assign n4407 = (n2545 | n3858) & (n2721 | n3860); - assign n4408 = n2532 & n2535; - assign n4409 = (n4408 | n3858) & (n2718 | n3860); - assign n4410 = (n2571 | n3858) & (n2710 | n3860); - assign n4411 = n2558 & n2561; - assign n4412 = (n4411 | n3858) & (n2706 | n3860); - assign n4413 = (n3043 | n1923) & (n3054 | n3894); - assign n4414 = n2485 & n2488; - assign n4415 = n2502 & n2505; - assign n4416 = (n4415 | n3858) & (n2516 | n3860); - assign n4417 = (n2595 | n3858) & (n2743 | n3860); - assign n4418 = n2584 & n2587; - assign n4419 = (n4418 | n3858) & (n2740 | n3860); - assign n4420 = (n2619 | n3858) & (n2732 | n3860); - assign n4421 = n2608 & n2611; - assign n4422 = (n4421 | n3858) & (n2729 | n3860); - assign n4423 = (n3040 | n1923) & (n3047 | n3894); - assign n4424 = (n3094 | n1701) & (n3091 | n1702); - assign n4425 = n4424 & (n2859 | n3870); - assign n4426 = (n2862 | n3884) & (n2865 | n3891); - assign n4427 = (n3046 | n1701) & (n2496 | n1702); - assign n4428 = n4427 & (n2852 | n3870); - assign n4429 = (n2854 | n3884) & (n2856 | n3891); - assign n4430 = (n3061 | n3897) & (~n1543 | ~n3996); - assign n4431 = ~n2074 & (~n4430 | (~n2070 & ~n2868)); - assign n4432 = (n2546 | n3870) & (n2596 | n3877); - assign n4433 = (n2572 | n3884) & (n2620 | n3891); - assign n4434 = (n2460 | n3870) & (n2500 | n3877); - assign n4435 = (n2483 | n3884) & (n2517 | n3891); - assign n4436 = n2920 | n3924; - assign n4437 = n3138 | ~n3184; - assign n4438 = n2976 | n3924; - assign n4439 = n2892 | n3924; - assign n4440 = n2948 | n3924; - assign n4441 = (n3156 | n3870) & (n3174 | n3877); - assign n4442 = (n3147 | n3884) & (n3165 | n3891); - assign n4443 = n2456 | n3920; - assign n4444 = n3101 | ~n3184; - assign n4445 = n2496 | n3920; - assign n4446 = n2479 | n3920; - assign n4447 = n2513 | n3920; - assign n4448 = (n3119 | n3870) & (n3137 | n3877); - assign n4449 = (n3110 | n3884) & (n3128 | n3891); - assign n4450 = n2920 | n3929; - assign n4451 = n3062 | ~n3184; - assign n4452 = n2976 | n3929; - assign n4453 = n2892 | n3929; - assign n4454 = n2948 | n3929; - assign n4455 = (n3080 | n3870) & (n3100 | n3877); - assign n4456 = (n3071 | n3884) & (n3089 | n3891); - assign n4457 = n2921 | n3899; - assign n4458 = n2634 | ~n3184; - assign n4459 = n2977 | n3899; - assign n4460 = n2893 | n3899; - assign n4461 = n2949 | n3899; - assign n4462 = (n2918 | n3908) & (n2799 | n3909); - assign n4463 = (n2913 | n3910) & (n2915 | n3911); - assign n4464 = (n2890 | n3908) & (n2805 | n3909); - assign n4465 = (n2885 | n3910) & (n2887 | n3911); - assign n4466 = (n2825 | n3908) & (n4389 | n3909); - assign n4467 = (n2906 | n3910) & (n2908 | n3911); - assign n4468 = (n2903 | n3908) & (n4388 | n3909); - assign n4469 = (n2898 | n3910) & (n2900 | n3911); - assign n4470 = (n2833 | n3908) & (n4393 | n3909); - assign n4471 = (n2878 | n3910) & (n2880 | n3911); - assign n4472 = (n2875 | n3908) & (n4392 | n3909); - assign n4473 = (n2870 | n3910) & (n2872 | n3911); - assign n4474 = (n4398 | n3904) & (n4400 | n3905); - assign n4475 = n2893 | n3907; - assign n4476 = n4475 & (n3894 | (n4463 & n4462)); - assign n4477 = n4476 & (n3740 | (n4465 & n4464)); - assign n4478 = ~n2982 & (n3895 | (n4468 & n4469)); - assign n4479 = n4478 & (n3743 | (n4471 & n4470)); - assign n4480 = n2628 & (n3737 | (n4473 & n4472)); - assign n4481 = (n2974 | n3908) & (n2811 | n3909); - assign n4482 = (n2969 | n3910) & (n2971 | n3911); - assign n4483 = (n2946 | n3908) & (n2817 | n3909); - assign n4484 = (n2941 | n3910) & (n2943 | n3911); - assign n4485 = (n2841 | n3908) & (n4391 | n3909); - assign n4486 = (n2962 | n3910) & (n2964 | n3911); - assign n4487 = (n2959 | n3908) & (n4390 | n3909); - assign n4488 = (n2954 | n3910) & (n2956 | n3911); - assign n4489 = (n2849 | n3908) & (n4395 | n3909); - assign n4490 = (n2934 | n3910) & (n2936 | n3911); - assign n4491 = (n2931 | n3908) & (n4394 | n3909); - assign n4492 = (n2926 | n3910) & (n2928 | n3911); - assign n4493 = (n4399 | n3904) & (n4401 | n3905); - assign n4494 = n2949 | n3907; - assign n4495 = n4494 & (n3894 | (n4482 & n4481)); - assign n4496 = n4495 & (n3740 | (n4484 & n4483)); - assign n4497 = ~n2981 & (n3895 | (n4487 & n4488)); - assign n4498 = n4497 & (n3743 | (n4490 & n4489)); - assign n4499 = n2628 & (n3737 | (n4492 & n4491)); - assign n4500 = n2921 | n3913; - assign n4501 = n2624 | ~n3184; - assign n4502 = n2977 | n3913; - assign n4503 = n2893 | n3913; - assign n4504 = n2949 | n3913; - assign n4505 = (n2924 | n3870) & (n2980 | n3877); - assign n4506 = (n2896 | n3884) & (n2952 | n3891); - assign n4507 = (n3036 | n3677) & (n2867 | ~n3898); - assign n4508 = n3823 & (n813 | n3967); - assign n4509 = n2647 & (n3825 | n3967); - assign n4510 = n2646 & (n3822 | n3967); - assign n4511 = (n2750 | ~n4004) & (n3912 | ~n4003); - assign n4512 = (n2681 | n3935) & (n2682 | n1556); - assign n4513 = (n2679 | n3935) & (n2680 | n1556); - assign n4514 = (n2677 | n3935) & (n2678 | n1556); - assign n4515 = n2699 | ~n3184; - assign n4516 = n4515 & (n2675 | n3933); - assign n4517 = (n2658 | n3935) & (n2659 | n1556); - assign n4518 = (n2656 | n3935) & (n2657 | n1556); - assign n4519 = (n2654 | n3935) & (n2655 | n1556); - assign n4520 = n4515 & (n2652 | n3933); - assign n4521 = (n2687 | n3935) & (n2688 | n1556); - assign n4522 = (n2685 | n3935) & (n2686 | n1556); - assign n4523 = (n2683 | n3935) & (n2684 | n1556); - assign n4524 = n4515 & (n2676 | n3933); - assign n4525 = (n2664 | n3935) & (n2665 | n1556); - assign n4526 = (n2662 | n3935) & (n2663 | n1556); - assign n4527 = (n2660 | n3935) & (n2661 | n1556); - assign n4528 = n2653 | n3933; - assign n4529 = (n2727 | n3870) & (n2749 | n3877); - assign n4530 = (n2716 | n3884) & (n2738 | n3891); - assign n4531 = n2700 | n2704; - assign n4532 = n4531 & (n3327 | (n4530 & n4529)); - assign n4533 = (n4404 | n3940) & (n2459 | n3941); - assign n4534 = (n2681 | n3942) & (n2682 | n3943); - assign n4535 = (n4405 | n3940) & (n2482 | n3941); - assign n4536 = (n2687 | n3942) & (n2688 | n3943); - assign n4537 = (n2545 | n3940) & (n2721 | n3941); - assign n4538 = (n2679 | n3942) & (n2680 | n3943); - assign n4539 = (n4408 | n3940) & (n2718 | n3941); - assign n4540 = (n2677 | n3942) & (n2678 | n3943); - assign n4541 = (n2571 | n3940) & (n2710 | n3941); - assign n4542 = (n2685 | n3942) & (n2686 | n3943); - assign n4543 = (n4411 | n3940) & (n2706 | n3941); - assign n4544 = (n2683 | n3942) & (n2684 | n3943); - assign n4545 = (n2675 | n3938) & (n2676 | n3939); - assign n4546 = ~n2692 & (n3894 | (n4533 & n4534)); - assign n4547 = n4545 & n4546 & (Pi24 | n2691); - assign n4548 = ~n2693 & (n3895 | (n4539 & n4540)); - assign n4549 = n4548 & (n3743 | (n4542 & n4541)); - assign n4550 = n2639 & (n3737 | (n4544 & n4543)); - assign n4551 = (n4414 | n3940) & (n2499 | n3941); - assign n4552 = (n2658 | n3942) & (n2659 | n3943); - assign n4553 = (n4415 | n3940) & (n2516 | n3941); - assign n4554 = (n2664 | n3942) & (n2665 | n3943); - assign n4555 = (n2595 | n3940) & (n2743 | n3941); - assign n4556 = (n2656 | n3942) & (n2657 | n3943); - assign n4557 = (n4418 | n3940) & (n2740 | n3941); - assign n4558 = (n2654 | n3942) & (n2655 | n3943); - assign n4559 = (n2619 | n3940) & (n2732 | n3941); - assign n4560 = (n2662 | n3942) & (n2663 | n3943); - assign n4561 = (n4421 | n3940) & (n2729 | n3941); - assign n4562 = (n2660 | n3942) & (n2661 | n3943); - assign n4563 = (n2652 | n3938) & (n2653 | n3939); - assign n4564 = ~n2669 & (n3894 | (n4551 & n4552)); - assign n4565 = ~n2670 & (n3895 | (n4557 & n4558)); - assign n4566 = (n2750 | ~n4009) & (n3912 | ~n4008); - assign n4567 = (n2681 | n3947) & (n2682 | n1615); - assign n4568 = (n2679 | n3947) & (n2680 | n1615); - assign n4569 = (n2677 | n3947) & (n2678 | n1615); - assign n4570 = n2754 | ~n3184; - assign n4571 = n4570 & (n2675 | n3945); - assign n4572 = (n2658 | n3947) & (n2659 | n1615); - assign n4573 = (n2656 | n3947) & (n2657 | n1615); - assign n4574 = (n2654 | n3947) & (n2655 | n1615); - assign n4575 = n4570 & (n2652 | n3945); - assign n4576 = (n2687 | n3947) & (n2688 | n1615); - assign n4577 = (n2685 | n3947) & (n2686 | n1615); - assign n4578 = (n2683 | n3947) & (n2684 | n1615); - assign n4579 = n4570 & (n2676 | n3945); - assign n4580 = (n2664 | n3947) & (n2665 | n1615); - assign n4581 = (n2662 | n3947) & (n2663 | n1615); - assign n4582 = (n2660 | n3947) & (n2661 | n1615); - assign n4583 = n2653 | n3945; - assign n4584 = (n2774 | n3870) & (n2792 | n3877); - assign n4585 = (n2765 | n3884) & (n2783 | n3891); - assign n4586 = n2704 | n2755; - assign n4587 = n4586 & (n3327 | (n4585 & n4584)); - assign n4588 = (n2636 | n3677) & (n2621 | ~n3898); - assign n4589 = ~n3176 & (n2066 | n2697) & ~n3177; - assign n4590 = (~Pi26 | n3971) & (~Ni40 | n3970); - assign n4591 = (~Pi27 | n3971) & (~Ni41 | n3970); - assign n4592 = (n3345 | n2372) & (n3352 | n1314); - assign n4593 = (n3365 | n2372) & (n3372 | n1314); - assign n4594 = (n3397 | n2372) & (n3403 | n1314); - assign n4595 = (n3410 | n2372) & (n3417 | n1314); - assign n4596 = (n3425 | n2372) & (n3430 | n1314); - assign n4597 = (n3437 | n2372) & (n3444 | n1314); - assign n4598 = n3476 | n1929; - assign n4599 = n4598 & (n3894 | (n4592 & n3472)); - assign n4600 = ~n3479 & (n3895 | (n3472 & n4595)); - assign n4601 = ~n3773 & (n3737 | (n3472 & n4597)); - assign n4602 = (n3379 | n2372) & (n3381 | n1314); - assign n4603 = (n3386 | n2372) & (n3388 | n1314); - assign n4604 = (n3450 | n2372) & (n3452 | n1314); - assign n4605 = (n3454 | n2372) & (n3456 | n1314); - assign n4606 = (n3461 | n2372) & (n3463 | n1314); - assign n4607 = (n3465 | n2372) & (n3467 | n1314); - assign n4608 = n3473 | n1929; - assign n4609 = (n3420 | n3870) & (n3459 | n3877); - assign n4610 = (n3447 | n3884) & (n3470 | n3891); - assign n4611 = (n3358 | n3870) & (n3384 | n3877); - assign n4612 = (n3377 | n3884) & (n3391 | n3891); - assign n4613 = (n3484 | n2372) & (n3485 | n1314); - assign n4614 = (n3489 | n2372) & (n3490 | n1314); - assign n4615 = (n3504 | n2372) & (n3505 | n1314); - assign n4616 = (n3506 | n2372) & (n3507 | n1314); - assign n4617 = (n3511 | n2372) & (n3512 | n1314); - assign n4618 = (n3513 | n2372) & (n3514 | n1314); - assign n4619 = n3535 | n1929; - assign n4620 = n4619 & (n3894 | (n4613 & n3472)); - assign n4621 = ~n3538 & (n3895 | (n3472 & n4616)); - assign n4622 = ~n3773 & (n3737 | (n3472 & n4618)); - assign n4623 = (n3494 | n2372) & (n3495 | n1314); - assign n4624 = (n3499 | n2372) & (n3500 | n1314); - assign n4625 = (n3518 | n2372) & (n3519 | n1314); - assign n4626 = (n3520 | n2372) & (n3521 | n1314); - assign n4627 = (n3525 | n2372) & (n3526 | n1314); - assign n4628 = (n3527 | n2372) & (n3528 | n1314); - assign n4629 = n3532 | n1929; - assign n4630 = (n3510 | n3870) & (n3524 | n3877); - assign n4631 = (n3517 | n3884) & (n3531 | n3891); - assign n4632 = (n3488 | n3870) & (n3498 | n3877); - assign n4633 = (n3493 | n3884) & (n3503 | n3891); - assign n4634 = (n3300 | n3618) & (n3551 | n1929); - assign n4635 = (n3302 | n3618) & (n3553 | n1929); - assign n4636 = (n3316 | n3618) & (n3575 | n1929); - assign n4637 = (n3318 | n3618) & (n3579 | n1929); - assign n4638 = (n3319 | n3618) & (n3586 | n1929); - assign n4639 = (n3321 | n3618) & (n3590 | n1929); - assign n4640 = ~n3654 & (n3895 | (n3621 & n4637)); - assign n4641 = ~n3655 & (n3737 | (n3621 & n4639)); - assign n4642 = (n3310 | n3618) & (n3588 | n1929); - assign n4643 = (n3312 | n3618) & (n3592 | n1929); - assign n4644 = (n3650 | n2272) & (n3651 | n3895); - assign n4645 = (n3645 | n3978) & (n3649 | n3979); - assign n4646 = (n3234 | n3618) & (n3567 | n1929); - assign n4647 = (n3240 | n3618) & (n3569 | n1929); - assign n4648 = (n3268 | n3618) & (n3597 | n1929); - assign n4649 = (n3273 | n3618) & (n3601 | n1929); - assign n4650 = (n3277 | n3618) & (n3608 | n1929); - assign n4651 = (n3282 | n3618) & (n3612 | n1929); - assign n4652 = ~n3638 & (n3895 | (n3621 & n4649)); - assign n4653 = ~n3639 & (n3737 | (n3621 & n4651)); - assign n4654 = (n3256 | n3618) & (n3610 | n1929); - assign n4655 = (n3261 | n3618) & (n3614 | n1929); - assign n4656 = (n3633 | n2272) & (n3634 | n3895); - assign n4657 = (n3628 | n3978) & (n3632 | n3979); - assign n4658 = (n3584 | n3870) & (n3606 | n3877); - assign n4659 = (n3595 | n3884) & (n3617 | n3891); - assign n4660 = (n3548 | n3870) & (n3565 | n3877); - assign n4661 = (n3557 | n3884) & (n3573 | n3891); - assign n4662 = n3912 | n1543 | n4744 | n4745; - assign n4663 = n2074 | n3669 | n795 | ~Ni10; - assign n4664 = n3768 | n3669 | n3767; - assign n4665 = Ni31 & (~Ni30 | ~Ni5 | Ni4); - assign n4666 = (~Pi15 & n1312) | (n1305 & (Pi15 | n1312)); - assign n4667 = ~Pi17 & (n1296 | n1298 | ~n4089); - assign n4668 = ~n4667 & (~Pi17 | (n4090 & n4091)); - assign n4669 = (~n3327 & n4668) | (n4666 & (n3327 | n4668)); - assign n4670 = n4110 & ~n3892 & n4109; - assign n4671 = ~n2074 & (n4670 | (n3892 & n4668)); - assign n4672 = ~Ni7 & (n4671 | (n2074 & n4669)); - assign n4673 = ~n3707 & (n4672 | (Ni7 & n4669)); - assign n4674 = Ni14 & n4258 & n3802; - assign n4675 = n4179 & ~Ni14 & n4178; - assign n4676 = Ni14 & n4186 & n4185; - assign n4677 = n1943 | ~n4148 | n1941 | n1942 | ~n1362 | ~n1536 | n1939 | n1940; - assign n4678 = n1935 | ~n4162 | n1933 | n1934 | ~n1362 | ~n1498 | n1931 | n1932; - assign n4679 = n1787 | n3906; - assign n4680 = n4679 & n4221 & n4220 & n4218 & ~Pi15 & n4215; - assign n4681 = n1857 | n3906; - assign n4682 = Pi15 & n4239 & n4240 & n4237 & n4234 & n4681; - assign n4683 = Pi17 & (~n4133 | ~n4134); - assign n4684 = n4165 & n4164 & ~Pi17 & n1362; - assign n4685 = Pi17 & n4167 & n4168 & n1362; - assign n4686 = n4248 & Ni10 & (Ni11 | n1865); - assign n4687 = n4170 & ~Pi17 & n4169; - assign n4688 = n2383 | n3737; - assign n4689 = n4688 & n4303 & n4302 & n4301 & ~Pi15 & n2371; - assign n4690 = n18 | ~Ni34; - assign n4691 = n1539 | Ni34 | n18; - assign n4692 = n4317 & ~Pi17 & n4316; - assign n4693 = Pi17 & n4319 & n4318; - assign n4694 = Pi20 & (~n4339 | ~n4341); - assign n4695 = ~n4694 & (Pi20 | (n4329 & n4331)); - assign n4696 = Pi20 & (~n4362 | ~n4364); - assign n4697 = ~n4696 & (Pi20 | (n4352 & n4354)); - assign n4698 = n4695 & ~Pi15 & n4342; - assign n4699 = Pi15 & n4365 & n4697; - assign n4700 = n4692 | n4693 | n3327 | Ni10; - assign n4701 = ~Pi17 & (~n4373 | ~n4374); - assign n4702 = n2393 & n4377 & n2390; - assign n4703 = ~n2393 & (n3808 | (~Pi23 & n2392)); - assign n4704 = n2393 & n4378 & n2400; - assign n4705 = ~n2393 & (n3809 | (~Pi24 & n2401)); - assign n4706 = ~n2393 & (Ni33 | n886) & n2401; - assign n4707 = ~Ni44 & ~Ni39 & (~n3733 | Ni42); - assign n4708 = ~n4707 & (~Ni44 | ~n923 | ~Ni39); - assign n4709 = Pi21 | n3818; - assign n4710 = (~Pi26 & ~n2648) | (~n2644 & (Pi26 | ~n2648)); - assign n4711 = ~Pi21 & (~n2623 | (~Pi26 & Ni32)); - assign n4712 = (Pi26 & ~n2648) | (~n2644 & (~Pi26 | ~n2648)); - assign n4713 = n4442 & ~Ni14 & n4441; - assign n4714 = n3059 | ~n4413 | n3057 | n3058 | ~n2423 | ~n2691 | n3055 | n3056; - assign n4715 = n3052 | ~n4423 | n3050 | n3051 | ~n2423 | ~n2668 | n3048 | n3049; - assign n4716 = n2921 | n3906; - assign n4717 = n4716 & n4480 & n4479 & n4477 & ~Pi15 & n4474; - assign n4718 = n2977 | n3906; - assign n4719 = Pi15 & n4498 & n4499 & n4496 & n4493 & n4718; - assign n4720 = Pi17 & (~n4402 | ~n4403); - assign n4721 = n4426 & n4425 & ~Pi17 & n2423; - assign n4722 = Pi17 & n4428 & n4429 & n2423; - assign n4723 = n4507 & Ni10 & (Ni11 | n2985); - assign n4724 = n2703 | n2701 | n2702; - assign n4725 = n4433 & ~Pi17 & n4432; - assign n4726 = ~Pi20 & n3968 & (n3183 | ~Ni39); - assign n4727 = n3968 & Pi20 & (Ni39 | n3183); - assign n4728 = ~n2393 | ~Ni40; - assign n4729 = (n3830 & (~n2393 | ~n4012)) | (n2393 & ~n4012); - assign n4730 = ~n2393 | ~Ni41; - assign n4731 = (n3833 & (~n2393 | ~n4016)) | (n2393 & ~n4016); - assign n4732 = ~Pi21 & (n797 | (~n1539 & n3186)); - assign n4733 = Pi20 & (n3652 | n3653 | ~n4644); - assign n4734 = ~n4733 & (Pi20 | (n4640 & n4641)); - assign n4735 = Pi20 & (n3636 | n3637 | ~n4656); - assign n4736 = ~n4735 & (Pi20 | (n4652 & n4653)); - assign n4737 = n4734 & ~Pi15 & n4645; - assign n4738 = Pi15 & n4657 & n4736; - assign n4739 = n4659 & ~Pi17 & n4658; - assign n4740 = ~Ni10 & (n4737 | n4738); - assign n4741 = n4601 & n4600 & n4599 & ~n3478 & ~Pi15 & ~n3477; - assign n4742 = n4610 & ~Pi17 & n4609; - assign n4743 = Pi17 & n4612 & n4611; - assign n4744 = ~Ni10 & (n4741 | (Pi15 & n4023)); - assign n4745 = Ni10 & (n4742 | n4743); - assign n4746 = n4622 & n4621 & n4620 & ~n3537 & ~Pi15 & ~n3536; - assign n4747 = n4631 & ~Pi17 & n4630; - assign n4748 = Pi17 & n4633 & n4632; - assign n4749 = ~Ni10 & (n4746 | (Pi15 & n4028)); - assign n4750 = n4775 | ~Ni14 | ~Ni12; - assign n4751 = ~Ni4 & (~Ni6 | ~Ni5 | ~n3700); - assign n4752 = ~Ni5 | ~Ni31 | ~Ni6; - assign n4753 = n4752 & Ni4 & (n2418 | n3980); - assign n4754 = Ni3 & (n4753 | (~Ni4 & ~n4752)); - assign n4755 = ~Ni2 & (n4754 | (~Ni3 & n4034)); - assign n4756 = Ni6 & (Ni2 | (~Ni31 & Ni3)); - assign n4757 = Ni12 & (n3707 | (~n3723 & n3727)); - assign n4758 = Pi20 & (n806 | n3745 | n3755); - assign n4759 = Ni42 & (~Ni44 | n3732) & ~Ni39; - assign n4760 = Pi27 | n3985; - assign n4761 = ~Pi27 | Pi26 | n3985; - assign n4762 = Pi24 | n3986; - assign n4763 = ~Pi24 | Pi23 | n3986; - assign n4764 = ~Ni4 & (n2416 | n3973); - assign n4765 = Ni4 & (Ni33 | n3980); - assign n4766 = Ni33 & ~n1352; - assign n4767 = ~Ni33 & ~n1352; - assign n4768 = n698 | n2433; - assign n4769 = ~n674 | Ni41; - assign n4770 = ~n675 | Ni41; - assign n4771 = ~Ni33 | n3201; - assign n4772 = n1540 & n1463; - assign n4773 = n1546 | n1547 | n1548 | ~n4291; - assign n4774 = n3984 | n4726 | n4727; - assign n4775 = n3669 & Pi27; - assign n1085 = P__cmxcl_0; - always @ (posedge clock) begin - Ni48 <= n931_1; - Ni47 <= n936; - Ni46 <= n941_1; - Ni45 <= n946_1; - Ni44 <= n951_1; - Ni43 <= n956_1; - Ni42 <= n961_1; - Ni41 <= n966_1; - Ni40 <= n971; - Ni39 <= n976_1; - Ni38 <= n981_1; - Ni37 <= n986; - Ni36 <= n991_1; - Ni35 <= n996_1; - Ni34 <= n1001; - Ni33 <= n1006_1; - Ni32 <= n1011_1; - Ni31 <= n1016_1; - Ni30 <= n1021; - n18 <= n1026_1; - Ni14 <= n1031_1; - Ni13 <= n1036; - Ni12 <= n1041_1; - Ni11 <= n1046_1; - Ni10 <= n1051; - Ni9 <= n1056_1; - Ni8 <= n1061; - Ni7 <= n1066_1; - Ni6 <= n1071_1; - Ni5 <= n1076; - Ni4 <= n1081; - Ni3 <= n1085; - Ni2 <= n1090_1; - end -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/des/des.v b/fpga_flow/benchmarks/Verilog/MCNC/des/des.v deleted file mode 100644 index e4f2fab16..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/des/des.v +++ /dev/null @@ -1,1822 +0,0 @@ -// Benchmark "TOP" written by ABC on Tue Mar 5 09:56:12 2019 - -module des ( - Preset_0_, Poutreg_63_, Poutreg_62_, Poutreg_61_, Poutreg_60_, - Poutreg_59_, Poutreg_58_, Poutreg_57_, Poutreg_56_, Poutreg_55_, - Poutreg_54_, Poutreg_53_, Poutreg_52_, Poutreg_51_, Poutreg_50_, - Poutreg_49_, Poutreg_48_, Poutreg_47_, Poutreg_46_, Poutreg_45_, - Poutreg_44_, Poutreg_43_, Poutreg_42_, Poutreg_41_, Poutreg_40_, - Poutreg_39_, Poutreg_38_, Poutreg_37_, Poutreg_36_, Poutreg_35_, - Poutreg_34_, Poutreg_33_, Poutreg_32_, Poutreg_31_, Poutreg_30_, - Poutreg_29_, Poutreg_28_, Poutreg_27_, Poutreg_26_, Poutreg_25_, - Poutreg_24_, Poutreg_23_, Poutreg_22_, Poutreg_21_, Poutreg_20_, - Poutreg_19_, Poutreg_18_, Poutreg_17_, Poutreg_16_, Poutreg_15_, - Poutreg_14_, Poutreg_13_, Poutreg_12_, Poutreg_11_, Poutreg_10_, - Poutreg_9_, Poutreg_8_, Poutreg_7_, Poutreg_6_, Poutreg_5_, Poutreg_4_, - Poutreg_3_, Poutreg_2_, Poutreg_1_, Poutreg_0_, Pload_key_0_, - Pinreg_55_, Pinreg_54_, Pinreg_53_, Pinreg_52_, Pinreg_51_, Pinreg_50_, - Pinreg_49_, Pinreg_48_, Pinreg_47_, Pinreg_46_, Pinreg_45_, Pinreg_44_, - Pinreg_43_, Pinreg_42_, Pinreg_41_, Pinreg_40_, Pinreg_39_, Pinreg_38_, - Pinreg_37_, Pinreg_36_, Pinreg_35_, Pinreg_34_, Pinreg_33_, Pinreg_32_, - Pinreg_31_, Pinreg_30_, Pinreg_29_, Pinreg_28_, Pinreg_27_, Pinreg_26_, - Pinreg_25_, Pinreg_24_, Pinreg_23_, Pinreg_22_, Pinreg_21_, Pinreg_20_, - Pinreg_19_, Pinreg_18_, Pinreg_17_, Pinreg_16_, Pinreg_15_, Pinreg_14_, - Pinreg_13_, Pinreg_12_, Pinreg_11_, Pinreg_10_, Pinreg_9_, Pinreg_8_, - Pinreg_7_, Pinreg_6_, Pinreg_5_, Pinreg_4_, Pinreg_3_, Pinreg_2_, - Pinreg_1_, Pinreg_0_, Pencrypt_mode_0_, Pencrypt_0_, Pdata_in_7_, - Pdata_in_6_, Pdata_in_5_, Pdata_in_4_, Pdata_in_3_, Pdata_in_2_, - Pdata_in_1_, Pdata_in_0_, Pdata_63_, Pdata_62_, Pdata_61_, Pdata_60_, - Pdata_59_, Pdata_58_, Pdata_57_, Pdata_56_, Pdata_55_, Pdata_54_, - Pdata_53_, Pdata_52_, Pdata_51_, Pdata_50_, Pdata_49_, Pdata_48_, - Pdata_47_, Pdata_46_, Pdata_45_, Pdata_44_, Pdata_43_, Pdata_42_, - Pdata_41_, Pdata_40_, Pdata_39_, Pdata_38_, Pdata_37_, Pdata_36_, - Pdata_35_, Pdata_34_, Pdata_33_, Pdata_32_, Pdata_31_, Pdata_30_, - Pdata_29_, Pdata_28_, Pdata_27_, Pdata_26_, Pdata_25_, Pdata_24_, - Pdata_23_, Pdata_22_, Pdata_21_, Pdata_20_, Pdata_19_, Pdata_18_, - Pdata_17_, Pdata_16_, Pdata_15_, Pdata_14_, Pdata_13_, Pdata_12_, - Pdata_11_, Pdata_10_, Pdata_9_, Pdata_8_, Pdata_7_, Pdata_6_, Pdata_5_, - Pdata_4_, Pdata_3_, Pdata_2_, Pdata_1_, Pdata_0_, Pcount_3_, Pcount_2_, - Pcount_1_, Pcount_0_, PD_27_, PD_26_, PD_25_, PD_24_, PD_23_, PD_22_, - PD_21_, PD_20_, PD_19_, PD_18_, PD_17_, PD_16_, PD_15_, PD_14_, PD_13_, - PD_12_, PD_11_, PD_10_, PD_9_, PD_8_, PD_7_, PD_6_, PD_5_, PD_4_, - PD_3_, PD_2_, PD_1_, PD_0_, PC_27_, PC_26_, PC_25_, PC_24_, PC_23_, - PC_22_, PC_21_, PC_20_, PC_19_, PC_18_, PC_17_, PC_16_, PC_15_, PC_14_, - PC_13_, PC_12_, PC_11_, PC_10_, PC_9_, PC_8_, PC_7_, PC_6_, PC_5_, - PC_4_, PC_3_, PC_2_, PC_1_, PC_0_, - Poutreg_new_63_, Poutreg_new_62_, Poutreg_new_61_, Poutreg_new_60_, - Poutreg_new_59_, Poutreg_new_58_, Poutreg_new_57_, Poutreg_new_56_, - Poutreg_new_55_, Poutreg_new_54_, Poutreg_new_53_, Poutreg_new_52_, - Poutreg_new_51_, Poutreg_new_50_, Poutreg_new_49_, Poutreg_new_48_, - Poutreg_new_47_, Poutreg_new_46_, Poutreg_new_45_, Poutreg_new_44_, - Poutreg_new_43_, Poutreg_new_42_, Poutreg_new_41_, Poutreg_new_40_, - Poutreg_new_39_, Poutreg_new_38_, Poutreg_new_37_, Poutreg_new_36_, - Poutreg_new_35_, Poutreg_new_34_, Poutreg_new_33_, Poutreg_new_32_, - Poutreg_new_31_, Poutreg_new_30_, Poutreg_new_29_, Poutreg_new_28_, - Poutreg_new_27_, Poutreg_new_26_, Poutreg_new_25_, Poutreg_new_24_, - Poutreg_new_23_, Poutreg_new_22_, Poutreg_new_21_, Poutreg_new_20_, - Poutreg_new_19_, Poutreg_new_18_, Poutreg_new_17_, Poutreg_new_16_, - Poutreg_new_15_, Poutreg_new_14_, Poutreg_new_13_, Poutreg_new_12_, - Poutreg_new_11_, Poutreg_new_10_, Poutreg_new_9_, Poutreg_new_8_, - Poutreg_new_7_, Poutreg_new_6_, Poutreg_new_5_, Poutreg_new_4_, - Poutreg_new_3_, Poutreg_new_2_, Poutreg_new_1_, Poutreg_new_0_, - Pinreg_new_55_, Pinreg_new_54_, Pinreg_new_53_, Pinreg_new_52_, - Pinreg_new_51_, Pinreg_new_50_, Pinreg_new_49_, Pinreg_new_48_, - Pinreg_new_47_, Pinreg_new_46_, Pinreg_new_45_, Pinreg_new_44_, - Pinreg_new_43_, Pinreg_new_42_, Pinreg_new_41_, Pinreg_new_40_, - Pinreg_new_39_, Pinreg_new_38_, Pinreg_new_37_, Pinreg_new_36_, - Pinreg_new_35_, Pinreg_new_34_, Pinreg_new_33_, Pinreg_new_32_, - Pinreg_new_31_, Pinreg_new_30_, Pinreg_new_29_, Pinreg_new_28_, - Pinreg_new_27_, Pinreg_new_26_, Pinreg_new_25_, Pinreg_new_24_, - Pinreg_new_23_, Pinreg_new_22_, Pinreg_new_21_, Pinreg_new_20_, - Pinreg_new_19_, Pinreg_new_18_, Pinreg_new_17_, Pinreg_new_16_, - Pinreg_new_15_, Pinreg_new_14_, Pinreg_new_13_, Pinreg_new_12_, - Pinreg_new_11_, Pinreg_new_10_, Pinreg_new_9_, Pinreg_new_8_, - Pinreg_new_7_, Pinreg_new_6_, Pinreg_new_5_, Pinreg_new_4_, - Pinreg_new_3_, Pinreg_new_2_, Pinreg_new_1_, Pinreg_new_0_, - Pencrypt_mode_new_0_, Pdata_new_63_, Pdata_new_62_, Pdata_new_61_, - Pdata_new_60_, Pdata_new_59_, Pdata_new_58_, Pdata_new_57_, - Pdata_new_56_, Pdata_new_55_, Pdata_new_54_, Pdata_new_53_, - Pdata_new_52_, Pdata_new_51_, Pdata_new_50_, Pdata_new_49_, - Pdata_new_48_, Pdata_new_47_, Pdata_new_46_, Pdata_new_45_, - Pdata_new_44_, Pdata_new_43_, Pdata_new_42_, Pdata_new_41_, - Pdata_new_40_, Pdata_new_39_, Pdata_new_38_, Pdata_new_37_, - Pdata_new_36_, Pdata_new_35_, Pdata_new_34_, Pdata_new_33_, - Pdata_new_32_, Pdata_new_31_, Pdata_new_30_, Pdata_new_29_, - Pdata_new_28_, Pdata_new_27_, Pdata_new_26_, Pdata_new_25_, - Pdata_new_24_, Pdata_new_23_, Pdata_new_22_, Pdata_new_21_, - Pdata_new_20_, Pdata_new_19_, Pdata_new_18_, Pdata_new_17_, - Pdata_new_16_, Pdata_new_15_, Pdata_new_14_, Pdata_new_13_, - Pdata_new_12_, Pdata_new_11_, Pdata_new_10_, Pdata_new_9_, - Pdata_new_8_, Pdata_new_7_, Pdata_new_6_, Pdata_new_5_, Pdata_new_4_, - Pdata_new_3_, Pdata_new_2_, Pdata_new_1_, Pdata_new_0_, Pcount_new_3_, - Pcount_new_2_, Pcount_new_1_, Pcount_new_0_, PD_new_27_, PD_new_26_, - PD_new_25_, PD_new_24_, PD_new_23_, PD_new_22_, PD_new_21_, PD_new_20_, - PD_new_19_, PD_new_18_, PD_new_17_, PD_new_16_, PD_new_15_, PD_new_14_, - PD_new_13_, PD_new_12_, PD_new_11_, PD_new_10_, PD_new_9_, PD_new_8_, - PD_new_7_, PD_new_6_, PD_new_5_, PD_new_4_, PD_new_3_, PD_new_2_, - PD_new_1_, PD_new_0_, PC_new_27_, PC_new_26_, PC_new_25_, PC_new_24_, - PC_new_23_, PC_new_22_, PC_new_21_, PC_new_20_, PC_new_19_, PC_new_18_, - PC_new_17_, PC_new_16_, PC_new_15_, PC_new_14_, PC_new_13_, PC_new_12_, - PC_new_11_, PC_new_10_, PC_new_9_, PC_new_8_, PC_new_7_, PC_new_6_, - PC_new_5_, PC_new_4_, PC_new_3_, PC_new_2_, PC_new_1_, PC_new_0_ ); - input Preset_0_, Poutreg_63_, Poutreg_62_, Poutreg_61_, Poutreg_60_, - Poutreg_59_, Poutreg_58_, Poutreg_57_, Poutreg_56_, Poutreg_55_, - Poutreg_54_, Poutreg_53_, Poutreg_52_, Poutreg_51_, Poutreg_50_, - Poutreg_49_, Poutreg_48_, Poutreg_47_, Poutreg_46_, Poutreg_45_, - Poutreg_44_, Poutreg_43_, Poutreg_42_, Poutreg_41_, Poutreg_40_, - Poutreg_39_, Poutreg_38_, Poutreg_37_, Poutreg_36_, Poutreg_35_, - Poutreg_34_, Poutreg_33_, Poutreg_32_, Poutreg_31_, Poutreg_30_, - Poutreg_29_, Poutreg_28_, Poutreg_27_, Poutreg_26_, Poutreg_25_, - Poutreg_24_, Poutreg_23_, Poutreg_22_, Poutreg_21_, Poutreg_20_, - Poutreg_19_, Poutreg_18_, Poutreg_17_, Poutreg_16_, Poutreg_15_, - Poutreg_14_, Poutreg_13_, Poutreg_12_, Poutreg_11_, Poutreg_10_, - Poutreg_9_, Poutreg_8_, Poutreg_7_, Poutreg_6_, Poutreg_5_, Poutreg_4_, - Poutreg_3_, Poutreg_2_, Poutreg_1_, Poutreg_0_, Pload_key_0_, - Pinreg_55_, Pinreg_54_, Pinreg_53_, Pinreg_52_, Pinreg_51_, Pinreg_50_, - Pinreg_49_, Pinreg_48_, Pinreg_47_, Pinreg_46_, Pinreg_45_, Pinreg_44_, - Pinreg_43_, Pinreg_42_, Pinreg_41_, Pinreg_40_, Pinreg_39_, Pinreg_38_, - Pinreg_37_, Pinreg_36_, Pinreg_35_, Pinreg_34_, Pinreg_33_, Pinreg_32_, - Pinreg_31_, Pinreg_30_, Pinreg_29_, Pinreg_28_, Pinreg_27_, Pinreg_26_, - Pinreg_25_, Pinreg_24_, Pinreg_23_, Pinreg_22_, Pinreg_21_, Pinreg_20_, - Pinreg_19_, Pinreg_18_, Pinreg_17_, Pinreg_16_, Pinreg_15_, Pinreg_14_, - Pinreg_13_, Pinreg_12_, Pinreg_11_, Pinreg_10_, Pinreg_9_, Pinreg_8_, - Pinreg_7_, Pinreg_6_, Pinreg_5_, Pinreg_4_, Pinreg_3_, Pinreg_2_, - Pinreg_1_, Pinreg_0_, Pencrypt_mode_0_, Pencrypt_0_, Pdata_in_7_, - Pdata_in_6_, Pdata_in_5_, Pdata_in_4_, Pdata_in_3_, Pdata_in_2_, - Pdata_in_1_, Pdata_in_0_, Pdata_63_, Pdata_62_, Pdata_61_, Pdata_60_, - Pdata_59_, Pdata_58_, Pdata_57_, Pdata_56_, Pdata_55_, Pdata_54_, - Pdata_53_, Pdata_52_, Pdata_51_, Pdata_50_, Pdata_49_, Pdata_48_, - Pdata_47_, Pdata_46_, Pdata_45_, Pdata_44_, Pdata_43_, Pdata_42_, - Pdata_41_, Pdata_40_, Pdata_39_, Pdata_38_, Pdata_37_, Pdata_36_, - Pdata_35_, Pdata_34_, Pdata_33_, Pdata_32_, Pdata_31_, Pdata_30_, - Pdata_29_, Pdata_28_, Pdata_27_, Pdata_26_, Pdata_25_, Pdata_24_, - Pdata_23_, Pdata_22_, Pdata_21_, Pdata_20_, Pdata_19_, Pdata_18_, - Pdata_17_, Pdata_16_, Pdata_15_, Pdata_14_, Pdata_13_, Pdata_12_, - Pdata_11_, Pdata_10_, Pdata_9_, Pdata_8_, Pdata_7_, Pdata_6_, Pdata_5_, - Pdata_4_, Pdata_3_, Pdata_2_, Pdata_1_, Pdata_0_, Pcount_3_, Pcount_2_, - Pcount_1_, Pcount_0_, PD_27_, PD_26_, PD_25_, PD_24_, PD_23_, PD_22_, - PD_21_, PD_20_, PD_19_, PD_18_, PD_17_, PD_16_, PD_15_, PD_14_, PD_13_, - PD_12_, PD_11_, PD_10_, PD_9_, PD_8_, PD_7_, PD_6_, PD_5_, PD_4_, - PD_3_, PD_2_, PD_1_, PD_0_, PC_27_, PC_26_, PC_25_, PC_24_, PC_23_, - PC_22_, PC_21_, PC_20_, PC_19_, PC_18_, PC_17_, PC_16_, PC_15_, PC_14_, - PC_13_, PC_12_, PC_11_, PC_10_, PC_9_, PC_8_, PC_7_, PC_6_, PC_5_, - PC_4_, PC_3_, PC_2_, PC_1_, PC_0_; - output Poutreg_new_63_, Poutreg_new_62_, Poutreg_new_61_, Poutreg_new_60_, - Poutreg_new_59_, Poutreg_new_58_, Poutreg_new_57_, Poutreg_new_56_, - Poutreg_new_55_, Poutreg_new_54_, Poutreg_new_53_, Poutreg_new_52_, - Poutreg_new_51_, Poutreg_new_50_, Poutreg_new_49_, Poutreg_new_48_, - Poutreg_new_47_, Poutreg_new_46_, Poutreg_new_45_, Poutreg_new_44_, - Poutreg_new_43_, Poutreg_new_42_, Poutreg_new_41_, Poutreg_new_40_, - Poutreg_new_39_, Poutreg_new_38_, Poutreg_new_37_, Poutreg_new_36_, - Poutreg_new_35_, Poutreg_new_34_, Poutreg_new_33_, Poutreg_new_32_, - Poutreg_new_31_, Poutreg_new_30_, Poutreg_new_29_, Poutreg_new_28_, - Poutreg_new_27_, Poutreg_new_26_, Poutreg_new_25_, Poutreg_new_24_, - Poutreg_new_23_, Poutreg_new_22_, Poutreg_new_21_, Poutreg_new_20_, - Poutreg_new_19_, Poutreg_new_18_, Poutreg_new_17_, Poutreg_new_16_, - Poutreg_new_15_, Poutreg_new_14_, Poutreg_new_13_, Poutreg_new_12_, - Poutreg_new_11_, Poutreg_new_10_, Poutreg_new_9_, Poutreg_new_8_, - Poutreg_new_7_, Poutreg_new_6_, Poutreg_new_5_, Poutreg_new_4_, - Poutreg_new_3_, Poutreg_new_2_, Poutreg_new_1_, Poutreg_new_0_, - Pinreg_new_55_, Pinreg_new_54_, Pinreg_new_53_, Pinreg_new_52_, - Pinreg_new_51_, Pinreg_new_50_, Pinreg_new_49_, Pinreg_new_48_, - Pinreg_new_47_, Pinreg_new_46_, Pinreg_new_45_, Pinreg_new_44_, - Pinreg_new_43_, Pinreg_new_42_, Pinreg_new_41_, Pinreg_new_40_, - Pinreg_new_39_, Pinreg_new_38_, Pinreg_new_37_, Pinreg_new_36_, - Pinreg_new_35_, Pinreg_new_34_, Pinreg_new_33_, Pinreg_new_32_, - Pinreg_new_31_, Pinreg_new_30_, Pinreg_new_29_, Pinreg_new_28_, - Pinreg_new_27_, Pinreg_new_26_, Pinreg_new_25_, Pinreg_new_24_, - Pinreg_new_23_, Pinreg_new_22_, Pinreg_new_21_, Pinreg_new_20_, - Pinreg_new_19_, Pinreg_new_18_, Pinreg_new_17_, Pinreg_new_16_, - Pinreg_new_15_, Pinreg_new_14_, Pinreg_new_13_, Pinreg_new_12_, - Pinreg_new_11_, Pinreg_new_10_, Pinreg_new_9_, Pinreg_new_8_, - Pinreg_new_7_, Pinreg_new_6_, Pinreg_new_5_, Pinreg_new_4_, - Pinreg_new_3_, Pinreg_new_2_, Pinreg_new_1_, Pinreg_new_0_, - Pencrypt_mode_new_0_, Pdata_new_63_, Pdata_new_62_, Pdata_new_61_, - Pdata_new_60_, Pdata_new_59_, Pdata_new_58_, Pdata_new_57_, - Pdata_new_56_, Pdata_new_55_, Pdata_new_54_, Pdata_new_53_, - Pdata_new_52_, Pdata_new_51_, Pdata_new_50_, Pdata_new_49_, - Pdata_new_48_, Pdata_new_47_, Pdata_new_46_, Pdata_new_45_, - Pdata_new_44_, Pdata_new_43_, Pdata_new_42_, Pdata_new_41_, - Pdata_new_40_, Pdata_new_39_, Pdata_new_38_, Pdata_new_37_, - Pdata_new_36_, Pdata_new_35_, Pdata_new_34_, Pdata_new_33_, - Pdata_new_32_, Pdata_new_31_, Pdata_new_30_, Pdata_new_29_, - Pdata_new_28_, Pdata_new_27_, Pdata_new_26_, Pdata_new_25_, - Pdata_new_24_, Pdata_new_23_, Pdata_new_22_, Pdata_new_21_, - Pdata_new_20_, Pdata_new_19_, Pdata_new_18_, Pdata_new_17_, - Pdata_new_16_, Pdata_new_15_, Pdata_new_14_, Pdata_new_13_, - Pdata_new_12_, Pdata_new_11_, Pdata_new_10_, Pdata_new_9_, - Pdata_new_8_, Pdata_new_7_, Pdata_new_6_, Pdata_new_5_, Pdata_new_4_, - Pdata_new_3_, Pdata_new_2_, Pdata_new_1_, Pdata_new_0_, Pcount_new_3_, - Pcount_new_2_, Pcount_new_1_, Pcount_new_0_, PD_new_27_, PD_new_26_, - PD_new_25_, PD_new_24_, PD_new_23_, PD_new_22_, PD_new_21_, PD_new_20_, - PD_new_19_, PD_new_18_, PD_new_17_, PD_new_16_, PD_new_15_, PD_new_14_, - PD_new_13_, PD_new_12_, PD_new_11_, PD_new_10_, PD_new_9_, PD_new_8_, - PD_new_7_, PD_new_6_, PD_new_5_, PD_new_4_, PD_new_3_, PD_new_2_, - PD_new_1_, PD_new_0_, PC_new_27_, PC_new_26_, PC_new_25_, PC_new_24_, - PC_new_23_, PC_new_22_, PC_new_21_, PC_new_20_, PC_new_19_, PC_new_18_, - PC_new_17_, PC_new_16_, PC_new_15_, PC_new_14_, PC_new_13_, PC_new_12_, - PC_new_11_, PC_new_10_, PC_new_9_, PC_new_8_, PC_new_7_, PC_new_6_, - PC_new_5_, PC_new_4_, PC_new_3_, PC_new_2_, PC_new_1_, PC_new_0_; - wire n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, - n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, - n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, - n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, - n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, - n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816, - n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, - n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, - n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, - n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, - n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, - n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, - n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, - n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, - n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, - n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, - n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, n948, - n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, - n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, - n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, - n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, - n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, - n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, - n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, - n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, - n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, - n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, - n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, - n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, - n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, - n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, - n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, - n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, - n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, - n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, - n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, - n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, - n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, - n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, - n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, - n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, - n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, - n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, - n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, - n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, - n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, - n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, - n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, - n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, - n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, - n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, - n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, - n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, - n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, - n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, - n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, - n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, - n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, - n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, - n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, - n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, - n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, - n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, - n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, - n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, - n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, - n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, - n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, - n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, - n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, - n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, - n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, - n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, - n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, - n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, - n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, - n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, - n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, - n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, - n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, - n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, - n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, - n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, - n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, - n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, - n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, - n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, - n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, - n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, - n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, - n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, - n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, - n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, - n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, - n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, - n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, - n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, - n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, - n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, - n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, - n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, - n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, - n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, - n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, - n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, - n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, - n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, - n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, - n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, - n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, - n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, - n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, - n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, - n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, - n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, - n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, - n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, - n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, - n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, - n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, - n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, - n1997, n1998; - assign Poutreg_new_63_ = ~n747; - assign Poutreg_new_62_ = ~n849; - assign Poutreg_new_61_ = ~n748; - assign Poutreg_new_60_ = ~n845; - assign Poutreg_new_59_ = ~n749; - assign Poutreg_new_58_ = ~n841; - assign Poutreg_new_57_ = ~n750; - assign Poutreg_new_56_ = ~n836; - assign Poutreg_new_55_ = ~n751; - assign Poutreg_new_54_ = ~n868; - assign Poutreg_new_53_ = ~n752; - assign Poutreg_new_52_ = ~n838; - assign Poutreg_new_51_ = ~n753; - assign Poutreg_new_50_ = ~n867; - assign Poutreg_new_49_ = ~n754; - assign Poutreg_new_48_ = ~n866; - assign Poutreg_new_47_ = ~n755; - assign Poutreg_new_46_ = ~n865; - assign Poutreg_new_45_ = ~n756; - assign Poutreg_new_44_ = ~n864; - assign Poutreg_new_43_ = ~n757; - assign Poutreg_new_42_ = ~n863; - assign Poutreg_new_41_ = ~n758; - assign Poutreg_new_40_ = ~n862; - assign Poutreg_new_39_ = ~n759; - assign Poutreg_new_38_ = ~n861; - assign Poutreg_new_37_ = ~n760; - assign Poutreg_new_36_ = ~n860; - assign Poutreg_new_35_ = ~n761; - assign Poutreg_new_34_ = ~n859; - assign Poutreg_new_33_ = ~n762; - assign Poutreg_new_32_ = ~n858; - assign Poutreg_new_31_ = ~n763; - assign Poutreg_new_30_ = ~n857; - assign Poutreg_new_29_ = ~n764; - assign Poutreg_new_28_ = ~n856; - assign Poutreg_new_27_ = ~n765; - assign Poutreg_new_26_ = ~n855; - assign Poutreg_new_25_ = ~n766; - assign Poutreg_new_24_ = ~n854; - assign Poutreg_new_23_ = ~n767; - assign Poutreg_new_22_ = ~n853; - assign Poutreg_new_21_ = ~n768; - assign Poutreg_new_20_ = ~n852; - assign Poutreg_new_19_ = ~n769; - assign Poutreg_new_18_ = ~n851; - assign Poutreg_new_17_ = ~n770; - assign Poutreg_new_16_ = ~n850; - assign Poutreg_new_15_ = ~n771; - assign Poutreg_new_14_ = ~n848; - assign Poutreg_new_13_ = ~n772; - assign Poutreg_new_12_ = ~n847; - assign Poutreg_new_11_ = ~n773; - assign Poutreg_new_10_ = ~n846; - assign Poutreg_new_9_ = ~n774; - assign Poutreg_new_8_ = ~n844; - assign Poutreg_new_7_ = ~n775; - assign Poutreg_new_6_ = ~n843; - assign Poutreg_new_5_ = ~n776; - assign Poutreg_new_4_ = ~n842; - assign Poutreg_new_3_ = ~n777; - assign Poutreg_new_2_ = ~n840; - assign Poutreg_new_1_ = ~n778; - assign Poutreg_new_0_ = ~n839; - assign Pinreg_new_55_ = ~n780; - assign Pinreg_new_54_ = ~n781; - assign Pinreg_new_53_ = ~n782; - assign Pinreg_new_52_ = ~n783; - assign Pinreg_new_51_ = ~n784; - assign Pinreg_new_50_ = ~n785; - assign Pinreg_new_49_ = ~n786; - assign Pinreg_new_48_ = ~n787; - assign Pinreg_new_47_ = ~n788; - assign Pinreg_new_46_ = ~n789; - assign Pinreg_new_45_ = ~n790; - assign Pinreg_new_44_ = ~n791; - assign Pinreg_new_43_ = ~n792; - assign Pinreg_new_42_ = ~n793; - assign Pinreg_new_41_ = ~n794; - assign Pinreg_new_40_ = ~n795; - assign Pinreg_new_39_ = ~n796; - assign Pinreg_new_38_ = ~n797; - assign Pinreg_new_37_ = ~n798; - assign Pinreg_new_36_ = ~n799; - assign Pinreg_new_35_ = ~n800; - assign Pinreg_new_34_ = ~n801; - assign Pinreg_new_33_ = ~n802; - assign Pinreg_new_32_ = ~n803; - assign Pinreg_new_31_ = ~n804; - assign Pinreg_new_30_ = ~n805; - assign Pinreg_new_29_ = ~n806; - assign Pinreg_new_28_ = ~n807; - assign Pinreg_new_27_ = ~n808; - assign Pinreg_new_26_ = ~n809; - assign Pinreg_new_25_ = ~n810; - assign Pinreg_new_24_ = ~n811; - assign Pinreg_new_23_ = ~n812; - assign Pinreg_new_22_ = ~n813; - assign Pinreg_new_21_ = ~n814; - assign Pinreg_new_20_ = ~n815; - assign Pinreg_new_19_ = ~n816; - assign Pinreg_new_18_ = ~n817; - assign Pinreg_new_17_ = ~n818; - assign Pinreg_new_16_ = ~n819; - assign Pinreg_new_15_ = ~n820; - assign Pinreg_new_14_ = ~n821; - assign Pinreg_new_13_ = ~n822; - assign Pinreg_new_12_ = ~n823; - assign Pinreg_new_11_ = ~n824; - assign Pinreg_new_10_ = ~n825; - assign Pinreg_new_9_ = ~n826; - assign Pinreg_new_8_ = ~n827; - assign Pinreg_new_7_ = ~n828; - assign Pinreg_new_6_ = ~n829; - assign Pinreg_new_5_ = ~n830; - assign Pinreg_new_4_ = ~n831; - assign Pinreg_new_3_ = ~n832; - assign Pinreg_new_2_ = ~n833; - assign Pinreg_new_1_ = ~n834; - assign Pinreg_new_0_ = ~n835; - assign Pencrypt_mode_new_0_ = ~n1799; - assign Pdata_new_63_ = ~n1732; - assign Pdata_new_62_ = ~n1733; - assign Pdata_new_61_ = ~n1734; - assign Pdata_new_60_ = ~n1735; - assign Pdata_new_59_ = ~n1736; - assign Pdata_new_58_ = ~n1737; - assign Pdata_new_57_ = ~n1738; - assign Pdata_new_56_ = ~n1739; - assign Pdata_new_55_ = ~n1740; - assign Pdata_new_54_ = ~n1741; - assign Pdata_new_53_ = ~n1742; - assign Pdata_new_52_ = ~n1743; - assign Pdata_new_51_ = ~n1744; - assign Pdata_new_50_ = ~n1745; - assign Pdata_new_49_ = ~n1746; - assign Pdata_new_48_ = ~n1747; - assign Pdata_new_47_ = ~n1748; - assign Pdata_new_46_ = ~n1749; - assign Pdata_new_45_ = ~n1750; - assign Pdata_new_44_ = ~n1751; - assign Pdata_new_43_ = ~n1752; - assign Pdata_new_42_ = ~n1753; - assign Pdata_new_41_ = ~n1754; - assign Pdata_new_40_ = ~n1755; - assign Pdata_new_39_ = ~n1756; - assign Pdata_new_38_ = ~n1757; - assign Pdata_new_37_ = ~n1758; - assign Pdata_new_36_ = ~n1759; - assign Pdata_new_35_ = ~n1760; - assign Pdata_new_34_ = ~n1761; - assign Pdata_new_33_ = ~n1762; - assign Pdata_new_32_ = ~n1763; - assign Pdata_new_31_ = ~n1764; - assign Pdata_new_30_ = ~n1765; - assign Pdata_new_29_ = ~n1766; - assign Pdata_new_28_ = ~n1767; - assign Pdata_new_27_ = ~n1768; - assign Pdata_new_26_ = ~n1769; - assign Pdata_new_25_ = ~n1770; - assign Pdata_new_24_ = ~n1771; - assign Pdata_new_23_ = ~n1772; - assign Pdata_new_22_ = ~n1773; - assign Pdata_new_21_ = ~n1774; - assign Pdata_new_20_ = ~n1775; - assign Pdata_new_19_ = ~n1776; - assign Pdata_new_18_ = ~n1777; - assign Pdata_new_17_ = ~n1778; - assign Pdata_new_16_ = ~n1779; - assign Pdata_new_15_ = ~n1780; - assign Pdata_new_14_ = ~n1781; - assign Pdata_new_13_ = ~n1782; - assign Pdata_new_12_ = ~n1783; - assign Pdata_new_11_ = ~n1784; - assign Pdata_new_10_ = ~n1785; - assign Pdata_new_9_ = ~n1786; - assign Pdata_new_8_ = ~n1787; - assign Pdata_new_7_ = ~n1788; - assign Pdata_new_6_ = ~n1789; - assign Pdata_new_5_ = ~n1790; - assign Pdata_new_4_ = ~n1791; - assign Pdata_new_3_ = ~n1792; - assign Pdata_new_2_ = ~n1793; - assign Pdata_new_1_ = ~n1794; - assign Pdata_new_0_ = ~n1795; - assign Pcount_new_3_ = ~n779; - assign Pcount_new_2_ = ~n1796; - assign Pcount_new_1_ = ~n1797; - assign Pcount_new_0_ = ~n1403; - assign PD_new_27_ = ~n1524; - assign PD_new_26_ = ~n1528; - assign PD_new_25_ = ~n1532; - assign PD_new_24_ = ~n1536; - assign PD_new_23_ = ~n1540; - assign PD_new_22_ = ~n1544; - assign PD_new_21_ = ~n1548; - assign PD_new_20_ = ~n1552; - assign PD_new_19_ = ~n1556; - assign PD_new_18_ = ~n1560; - assign PD_new_17_ = ~n1564; - assign PD_new_16_ = ~n1568; - assign PD_new_15_ = ~n1572; - assign PD_new_14_ = ~n1576; - assign PD_new_13_ = ~n1580; - assign PD_new_12_ = ~n1584; - assign PD_new_11_ = ~n1588; - assign PD_new_10_ = ~n1592; - assign PD_new_9_ = ~n1596; - assign PD_new_8_ = ~n1600; - assign PD_new_7_ = ~n1604; - assign PD_new_6_ = ~n1608; - assign PD_new_5_ = ~n1612; - assign PD_new_4_ = ~n1616; - assign PD_new_3_ = ~n1620; - assign PD_new_2_ = ~n1624; - assign PD_new_1_ = ~n1628; - assign PD_new_0_ = ~n1632; - assign PC_new_27_ = ~n1412; - assign PC_new_26_ = ~n1416; - assign PC_new_25_ = ~n1420; - assign PC_new_24_ = ~n1424; - assign PC_new_23_ = ~n1428; - assign PC_new_22_ = ~n1432; - assign PC_new_21_ = ~n1436; - assign PC_new_20_ = ~n1440; - assign PC_new_19_ = ~n1444; - assign PC_new_18_ = ~n1448; - assign PC_new_17_ = ~n1452; - assign PC_new_16_ = ~n1456; - assign PC_new_15_ = ~n1460; - assign PC_new_14_ = ~n1464; - assign PC_new_13_ = ~n1468; - assign PC_new_12_ = ~n1472; - assign PC_new_11_ = ~n1476; - assign PC_new_10_ = ~n1480; - assign PC_new_9_ = ~n1484; - assign PC_new_8_ = ~n1488; - assign PC_new_7_ = ~n1492; - assign PC_new_6_ = ~n1496; - assign PC_new_5_ = ~n1500; - assign PC_new_4_ = ~n1504; - assign PC_new_3_ = ~n1508; - assign PC_new_2_ = ~n1512; - assign PC_new_1_ = ~n1516; - assign PC_new_0_ = ~n1520; - assign n746 = ~Pcount_3_ | n1648; - assign n747 = (~Poutreg_63_ | Pcount_0_) & (n746 | n899); - assign n748 = (~Poutreg_61_ | Pcount_0_) & (n746 | n931); - assign n749 = (~Poutreg_59_ | Pcount_0_) & (n746 | n948); - assign n750 = (~Poutreg_57_ | Pcount_0_) & (n746 | n976); - assign n751 = (~Poutreg_55_ | Pcount_0_) & n986; - assign n752 = (~Poutreg_53_ | Pcount_0_) & n1024; - assign n753 = (~Poutreg_51_ | Pcount_0_) & n1037; - assign n754 = (~Poutreg_49_ | Pcount_0_) & n1059; - assign n755 = (~Poutreg_47_ | Pcount_0_) & n1099; - assign n756 = (~Poutreg_45_ | Pcount_0_) & n1126; - assign n757 = (~Poutreg_43_ | Pcount_0_) & n1135; - assign n758 = (~Poutreg_41_ | Pcount_0_) & n1144; - assign n759 = (~Poutreg_39_ | Pcount_0_) & n1157; - assign n760 = (~Poutreg_37_ | Pcount_0_) & n1167; - assign n761 = (~Poutreg_35_ | Pcount_0_) & n1197; - assign n762 = (~Poutreg_33_ | Pcount_0_) & n1203; - assign n763 = (~Poutreg_31_ | Pcount_0_) & n1216; - assign n764 = (~Poutreg_29_ | Pcount_0_) & n1233; - assign n765 = (~Poutreg_27_ | Pcount_0_) & n1242; - assign n766 = (~Poutreg_25_ | Pcount_0_) & n1248; - assign n767 = (~Poutreg_23_ | Pcount_0_) & n1290; - assign n768 = (~Poutreg_21_ | Pcount_0_) & n1305; - assign n769 = (~Poutreg_19_ | Pcount_0_) & n1313; - assign n770 = (~Poutreg_17_ | Pcount_0_) & n1329; - assign n771 = (~Poutreg_15_ | Pcount_0_) & n1336; - assign n772 = (~Poutreg_13_ | Pcount_0_) & n1345; - assign n773 = (~Poutreg_11_ | Pcount_0_) & n1354; - assign n774 = (~Poutreg_9_ | Pcount_0_) & n1363; - assign n775 = (~Poutreg_7_ | Pcount_0_) & n1374; - assign n776 = (~Poutreg_5_ | Pcount_0_) & n1379; - assign n777 = (~Poutreg_3_ | Pcount_0_) & n1392; - assign n778 = (~Poutreg_1_ | Pcount_0_) & n1401; - assign n779 = (n1404 | n1407) & (~Pcount_3_ | n1406); - assign n780 = (~Pinreg_55_ | Pcount_0_) & (~Pinreg_47_ | n869); - assign n781 = (~Pinreg_54_ | Pcount_0_) & (~Pinreg_46_ | n869); - assign n782 = (~Pinreg_53_ | Pcount_0_) & (~Pinreg_45_ | n869); - assign n783 = (~Pinreg_52_ | Pcount_0_) & (~Pinreg_44_ | n869); - assign n784 = (~Pinreg_51_ | Pcount_0_) & (~Pinreg_43_ | n869); - assign n785 = (~Pinreg_50_ | Pcount_0_) & (~Pinreg_42_ | n869); - assign n786 = (~Pinreg_49_ | Pcount_0_) & (~Pinreg_41_ | n869); - assign n787 = (~Pinreg_48_ | Pcount_0_) & (~Pinreg_40_ | n869); - assign n788 = (~Pinreg_47_ | Pcount_0_) & (~Pinreg_39_ | n869); - assign n789 = (~Pinreg_46_ | Pcount_0_) & (~Pinreg_38_ | n869); - assign n790 = (~Pinreg_45_ | Pcount_0_) & (~Pinreg_37_ | n869); - assign n791 = (~Pinreg_44_ | Pcount_0_) & (~Pinreg_36_ | n869); - assign n792 = (~Pinreg_43_ | Pcount_0_) & (~Pinreg_35_ | n869); - assign n793 = (~Pinreg_42_ | Pcount_0_) & (~Pinreg_34_ | n869); - assign n794 = (~Pinreg_41_ | Pcount_0_) & (~Pinreg_33_ | n869); - assign n795 = (~Pinreg_40_ | Pcount_0_) & (~Pinreg_32_ | n869); - assign n796 = (~Pinreg_39_ | Pcount_0_) & (~Pinreg_31_ | n869); - assign n797 = (~Pinreg_38_ | Pcount_0_) & (~Pinreg_30_ | n869); - assign n798 = (~Pinreg_37_ | Pcount_0_) & (~Pinreg_29_ | n869); - assign n799 = (~Pinreg_36_ | Pcount_0_) & (~Pinreg_28_ | n869); - assign n800 = (~Pinreg_35_ | Pcount_0_) & (~Pinreg_27_ | n869); - assign n801 = (~Pinreg_34_ | Pcount_0_) & (~Pinreg_26_ | n869); - assign n802 = (~Pinreg_33_ | Pcount_0_) & (~Pinreg_25_ | n869); - assign n803 = (~Pinreg_32_ | Pcount_0_) & (~Pinreg_24_ | n869); - assign n804 = (~Pinreg_31_ | Pcount_0_) & (~Pinreg_23_ | n869); - assign n805 = (~Pinreg_30_ | Pcount_0_) & (~Pinreg_22_ | n869); - assign n806 = (~Pinreg_29_ | Pcount_0_) & (~Pinreg_21_ | n869); - assign n807 = (~Pinreg_28_ | Pcount_0_) & (~Pinreg_20_ | n869); - assign n808 = (~Pinreg_27_ | Pcount_0_) & (~Pinreg_19_ | n869); - assign n809 = (~Pinreg_26_ | Pcount_0_) & (~Pinreg_18_ | n869); - assign n810 = (~Pinreg_25_ | Pcount_0_) & (~Pinreg_17_ | n869); - assign n811 = (~Pinreg_24_ | Pcount_0_) & (~Pinreg_16_ | n869); - assign n812 = (~Pinreg_23_ | Pcount_0_) & (~Pinreg_15_ | n869); - assign n813 = (~Pinreg_22_ | Pcount_0_) & (~Pinreg_14_ | n869); - assign n814 = (~Pinreg_21_ | Pcount_0_) & (~Pinreg_13_ | n869); - assign n815 = (~Pinreg_20_ | Pcount_0_) & (~Pinreg_12_ | n869); - assign n816 = (~Pinreg_19_ | Pcount_0_) & (~Pinreg_11_ | n869); - assign n817 = (~Pinreg_18_ | Pcount_0_) & (~Pinreg_10_ | n869); - assign n818 = (~Pinreg_17_ | Pcount_0_) & (~Pinreg_9_ | n869); - assign n819 = (~Pinreg_16_ | Pcount_0_) & (~Pinreg_8_ | n869); - assign n820 = (~Pinreg_15_ | Pcount_0_) & (~Pinreg_7_ | n869); - assign n821 = (~Pinreg_14_ | Pcount_0_) & (~Pinreg_6_ | n869); - assign n822 = (~Pinreg_13_ | Pcount_0_) & (~Pinreg_5_ | n869); - assign n823 = (~Pinreg_12_ | Pcount_0_) & (~Pinreg_4_ | n869); - assign n824 = (~Pinreg_11_ | Pcount_0_) & (~Pinreg_3_ | n869); - assign n825 = (~Pinreg_10_ | Pcount_0_) & (~Pinreg_2_ | n869); - assign n826 = (~Pinreg_9_ | Pcount_0_) & (~Pinreg_1_ | n869); - assign n827 = (~Pinreg_8_ | Pcount_0_) & (~Pinreg_0_ | n869); - assign n828 = (~Pinreg_7_ | Pcount_0_) & (~Pdata_in_7_ | n869); - assign n829 = (~Pinreg_6_ | Pcount_0_) & (~Pdata_in_6_ | n869); - assign n830 = (~Pinreg_5_ | Pcount_0_) & (~Pdata_in_5_ | n869); - assign n831 = (~Pinreg_4_ | Pcount_0_) & (~Pdata_in_4_ | n869); - assign n832 = (~Pinreg_3_ | Pcount_0_) & (~Pdata_in_3_ | n869); - assign n833 = (~Pinreg_2_ | Pcount_0_) & (~Pdata_in_2_ | n869); - assign n834 = (~Pinreg_1_ | Pcount_0_) & (~Pdata_in_1_ | n869); - assign n835 = (~Pinreg_0_ | Pcount_0_) & (~Pdata_in_0_ | n869); - assign n836 = (~Poutreg_56_ | Pcount_0_) & (~Pdata_32_ | n746); - assign n837 = Pload_key_0_ & ~n746; - assign n838 = (~Pdata_49_ | n746) & n1025; - assign n839 = (~Pdata_39_ | n746) & n1402; - assign n840 = (~Pdata_47_ | n746) & n1393; - assign n841 = (~Poutreg_58_ | Pcount_0_) & (~Pdata_40_ | n746); - assign n842 = (~Pdata_55_ | n746) & n1380; - assign n843 = (~Pdata_63_ | n746) & n1375; - assign n844 = (~Pdata_38_ | n746) & n1364; - assign n845 = (~Poutreg_60_ | Pcount_0_) & (~Pdata_48_ | n746); - assign n846 = (~Pdata_46_ | n746) & n1355; - assign n847 = (~Pdata_54_ | n746) & n1346; - assign n848 = (~Pdata_62_ | n746) & n1337; - assign n849 = (~Poutreg_62_ | Pcount_0_) & (~Pdata_56_ | n746); - assign n850 = (~Pdata_37_ | n746) & n1330; - assign n851 = (~Pdata_45_ | n746) & n1314; - assign n852 = (~Pdata_53_ | n746) & n1306; - assign n853 = (~Pdata_61_ | n746) & n1291; - assign n854 = (~Pdata_36_ | n746) & n1249; - assign n855 = (~Pdata_44_ | n746) & n1243; - assign n856 = (~Pdata_52_ | n746) & n1234; - assign n857 = (~Pdata_60_ | n746) & n1217; - assign n858 = (~Pdata_35_ | n746) & n1204; - assign n859 = (~Pdata_43_ | n746) & n1198; - assign n860 = (~Pdata_51_ | n746) & n1168; - assign n861 = (~Pdata_59_ | n746) & n1158; - assign n862 = (~Pdata_34_ | n746) & n1145; - assign n863 = (~Pdata_42_ | n746) & n1136; - assign n864 = (~Pdata_50_ | n746) & n1127; - assign n865 = (~Pdata_58_ | n746) & n1100; - assign n866 = (~Pdata_33_ | n746) & n1060; - assign n867 = (~Pdata_41_ | n746) & n1038; - assign n868 = (~Pdata_57_ | n746) & n987; - assign n869 = ~Pcount_0_ | ~n746; - assign n870 = (~n893 | ~n1140) & (~n892 | ~n896); - assign n871 = (~n878 | ~n892) & (~n1140 | ~n1649); - assign n872 = ~Pdata_49_ ^ ~PD_2_; - assign n873 = (n871 | ~n1394) & (n870 | n872); - assign n874 = n1800 & (~n1651 | (~n877 & n885)); - assign n875 = n873 & n874 & (~n1394 | ~n1652); - assign n876 = n1398 & ~n1633; - assign n877 = n1394 & n1650; - assign n878 = ~n887 & n1634; - assign n879 = n876 & (n877 | (n878 & ~n890)); - assign n880 = ~n1651 | n890 | ~n1649; - assign n881 = n1633 | n1653; - assign n882 = ~n879 & n880 & (n881 | ~n1395); - assign n883 = ~n1652 | n872 | n1397; - assign n884 = (n1311 | ~n1650) & (~n878 | n1654); - assign n885 = ~n872 | ~n896; - assign n886 = n883 & n884 & (n885 | ~n1140); - assign n887 = ~Pdata_50_ ^ ~PD_8_; - assign n888 = ~n1397 ^ ~n1634; - assign n889 = ~n1651 | n887 | n888; - assign n890 = ~n872 | n1397; - assign n891 = n890 | ~n1651; - assign n892 = n1398 & n1633; - assign n893 = ~n1397 & n1650; - assign n894 = n1650 | n1649; - assign n895 = n892 & (n893 | (n872 & n894)); - assign n896 = n1395 & ~n1397; - assign n897 = n1140 | n876; - assign n898 = ~n872 & (~n889 | (n896 & n897)); - assign n899 = ~Pdata_24_ ^ ~n1978; - assign n900 = n914 & ~n920; - assign n901 = ~n1338 & ~n912 & ~n916; - assign n902 = n900 & ~n1926 & (n901 | ~n906); - assign n903 = ~n902 & (~n912 | ~n918 | ~n1721); - assign n904 = (~n934 | n938) & (~n1338 | ~n1720); - assign n905 = n903 & n904 & (~n926 | ~n1656); - assign n906 = ~Pdata_36_ ^ ~PC_4_; - assign n907 = (~n926 | ~n1338) & (n906 | ~n1657); - assign n908 = n1655 | ~n914 | ~n932; - assign n909 = ~n934 | ~n1656; - assign n910 = n908 & n909 & (n907 | ~n935); - assign n911 = n906 | ~n912; - assign n912 = ~Pdata_35_ ^ ~PC_0_; - assign n913 = n911 & (~n906 | n912); - assign n914 = ~Pdata_63_ ^ ~PC_13_; - assign n915 = ~n900 & (n914 | ~n920); - assign n916 = ~Pdata_32_ ^ ~PC_16_; - assign n917 = ~n906 & n916; - assign n918 = ~n916 & ~n920; - assign n919 = ~n906 & n918 & (~n912 | ~n914); - assign n920 = ~Pdata_34_ ^ ~PC_23_; - assign n921 = ~n912 & n916; - assign n922 = ~n914 & n920 & (n917 | n921); - assign n923 = (~n920 | ~n921) & (n913 | ~n918); - assign n924 = n1338 & n934; - assign n925 = n924 & ~n912 & n918; - assign n926 = ~n906 & ~n914; - assign n927 = n901 & ~n920 & n926; - assign n928 = ~n914 | n923 | ~n1338; - assign n929 = (~n926 | n1659) & (~n932 | ~n1658); - assign n930 = n929 & n928 & n905 & n910 & ~n1662 & ~n1924; - assign n931 = ~n930 ^ ~Pdata_16_; - assign n932 = n912 & n906; - assign n933 = n932 & n900 & n916; - assign n934 = n906 & ~n914; - assign n935 = n920 & n916 & n912; - assign n936 = ~n1338 & (n933 | (n934 & n935)); - assign n937 = n1655 | n911 | ~n914; - assign n938 = n912 | n1655; - assign n939 = ~n936 & n937 & (~n926 | n938); - assign n940 = (n906 | ~n921) & (n913 | n916); - assign n941 = n916 | ~n900 | ~n906; - assign n942 = ~n926 | n1655; - assign n943 = (n906 & (~n920 | ~n924)) | (n920 & ~n924); - assign n944 = n941 & n942 & (~n916 | n943); - assign n945 = n1803 & (~n920 | n940 | ~n1657); - assign n946 = n905 & n1341 & (~n906 | n1659); - assign n947 = n945 & (~n912 | n944) & n946; - assign n948 = ~n947 ^ ~Pdata_8_; - assign n949 = n980 | n1635; - assign n950 = ~n956 | n1030; - assign n951 = n957 | ~n980; - assign n952 = (n949 | n950) & (n951 | ~n1163); - assign n953 = (n983 | n1663) & (n952 | n958); - assign n954 = n949 | n981; - assign n955 = n953 & (n954 | ~n1161); - assign n956 = ~Pdata_43_ ^ ~PC_15_; - assign n957 = n956 | ~n1159; - assign n958 = ~Pdata_48_ ^ ~PC_1_; - assign n959 = (n956 | ~n961) & (n957 | n958); - assign n960 = n956 & ~n958 & n1159; - assign n961 = n958 & ~n1159; - assign n962 = ~n1664 & (n960 | (n956 & n961)); - assign n963 = n955 & ~n962 & (n954 | n959); - assign n964 = (~n960 | n1663) & (~n961 | n1667); - assign n965 = n1805 & (n958 | ~n1635 | n1666); - assign n966 = n964 & n965; - assign n967 = n1804 & (n949 | ~n981 | n983); - assign n968 = n1159 | n958; - assign n969 = n967 & (n968 | ~n1724); - assign n970 = ~n956 ^ ~n1635; - assign n971 = n1030 | n958; - assign n972 = n981 | ~n1635; - assign n973 = (n970 | n971) & (n972 | ~n1161); - assign n974 = ~n956 | n968; - assign n975 = n974 & n950 & (n957 | n958); - assign n976 = ~Pdata_0_ ^ ~n1979; - assign n977 = (~n958 | n1669) & (n968 | n1667); - assign n978 = n1809 & (~n960 | ~n981 | n1665); - assign n979 = n977 & n978; - assign n980 = ~Pdata_46_ ^ ~PC_19_; - assign n981 = ~Pdata_44_ ^ ~PC_6_; - assign n982 = n980 & (~n973 | (n981 & ~n983)); - assign n983 = n957 | ~n958; - assign n984 = n954 | n983; - assign n985 = n956 & (~n1808 | (~n1159 & ~n1663)); - assign n986 = (n746 | n1810) & (~Poutreg_63_ | n869); - assign n987 = (~Poutreg_62_ | n869) & (~Poutreg_54_ | Pcount_0_); - assign n988 = (n1017 | n1236) & (~n996 | ~n997); - assign n989 = ~n1017 | n1149; - assign n990 = n988 & (n989 | ~n1039); - assign n991 = ~n993 | ~n1146; - assign n992 = ~n1039 | n989 | n991; - assign n993 = ~Pdata_36_ ^ ~PC_27_; - assign n994 = n1004 | ~n1146; - assign n995 = ~n997 | n993 | n994; - assign n996 = ~n1054 & ~n1636; - assign n997 = n1017 & n1149; - assign n998 = n996 & (~n1022 | (n997 & ~n1670)); - assign n999 = ~n998 & n992 & n995; - assign n1000 = n1813 & (~n1050 | ~n1146 | n1671); - assign n1001 = n1670 | n1017; - assign n1002 = n1004 | ~n1149; - assign n1003 = n999 & n1000 & (n1001 | n1002); - assign n1004 = ~n1054 | n1636; - assign n1005 = n993 | ~n1146; - assign n1006 = (n1005 | ~n1050) & (n1004 | ~n1049); - assign n1007 = ~n993 | n1018 | n1056; - assign n1008 = n1001 | n1236; - assign n1009 = n1007 & n1008 & (n1006 | ~n1051); - assign n1010 = (n1042 | ~n1049) & (n1004 | n1053); - assign n1011 = n1811 & (~n993 | n1013 | n1056); - assign n1012 = n1010 & n1011; - assign n1013 = ~n996 | ~n1149; - assign n1014 = n1012 & n1009 & (n1001 | n1013); - assign n1015 = n1636 | n989 | ~n1146; - assign n1016 = (~n997 | ~n1054) & (~n996 | ~n1051); - assign n1017 = ~Pdata_37_ ^ ~PC_14_; - assign n1018 = ~n1050 | ~n1149; - assign n1019 = n1015 & n1016 & (n1017 | n1018); - assign n1020 = n1814 & (n990 | n1005); - assign n1021 = n1003 & n1014 & (~n993 | n1019); - assign n1022 = n1149 | n1001; - assign n1023 = n1020 & n1021 & (n1004 | n1022); - assign n1024 = (n746 | n1815) & (~Poutreg_61_ | n869); - assign n1025 = (~Poutreg_60_ | n869) & (~Poutreg_52_ | Pcount_0_); - assign n1026 = ~n981 | ~n1159 | n970 | n980; - assign n1027 = (n957 | n972) & (n950 | n1665); - assign n1028 = n1026 & n1027 & (n951 | n981); - assign n1029 = ~n1163 | n957 | n980; - assign n1030 = ~n981 | n1159; - assign n1031 = n1029 & (n970 | ~n980 | n1030); - assign n1032 = (n958 & n1031) | (n1028 & (~n958 | n1031)); - assign n1033 = n969 & n966; - assign n1034 = (n954 | ~n956) & (n951 | n972); - assign n1035 = n1165 & (~n1161 | n1665); - assign n1036 = n1035 & n955 & n1033 & n1032 & n979 & n1034; - assign n1037 = (n746 | n1816) & (~Poutreg_59_ | n869); - assign n1038 = (~Poutreg_58_ | n869) & (~Poutreg_50_ | Pcount_0_); - assign n1039 = n1054 & n1636; - assign n1040 = n1039 & (~n1022 | (n997 & ~n1670)); - assign n1041 = ~n1051 | n993 | n994; - assign n1042 = ~n1017 | n1018; - assign n1043 = ~n1040 & n1041 & (n991 | n1042); - assign n1044 = n1004 & ~n1050; - assign n1045 = n989 | n991 | n1044; - assign n1046 = n1236 & ~n996 & n1146; - assign n1047 = n1002 & ~n1146; - assign n1048 = n1046 | n1047 | n993 | ~n1017; - assign n1049 = n993 & ~n1146; - assign n1050 = ~n1054 & n1636; - assign n1051 = ~n1017 & ~n1149; - assign n1052 = n1049 & (~n990 | (n1050 & n1051)); - assign n1053 = n1146 | n1671; - assign n1054 = ~Pdata_39_ ^ ~PC_20_; - assign n1055 = n1053 | n1054; - assign n1056 = n1017 | ~n1146; - assign n1057 = n1018 & ~n1637; - assign n1058 = n1056 | n1057; - assign n1059 = (n746 | n1817) & (~Poutreg_57_ | n869); - assign n1060 = (~Poutreg_56_ | n869) & (~Poutreg_48_ | Pcount_0_); - assign n1061 = ~Pdata_63_ ^ ~PD_0_; - assign n1062 = ~Pdata_61_ ^ ~PD_21_; - assign n1063 = ~n1087 | ~n1672; - assign n1064 = n1063 | n1061 | n1062; - assign n1065 = n1078 | n1076 | n1673; - assign n1066 = n1078 | n1061 | ~n1062; - assign n1067 = n1065 & ~n1929 & (n1063 | n1066); - assign n1068 = n1930 & (n1078 | n1083 | ~n1352); - assign n1069 = (~n1349 | n1676) & (n1073 | n1818); - assign n1070 = n1069 & n1068 & n1067; - assign n1071 = ~n1062 | n1087 | n1222; - assign n1072 = n1061 | ~n1078; - assign n1073 = n1062 | n1083; - assign n1074 = n1078 | ~n1222; - assign n1075 = (n1073 | n1074) & (n1071 | n1072); - assign n1076 = ~Pdata_59_ ^ ~PD_17_; - assign n1077 = ~n1078 | ~n1222; - assign n1078 = ~Pdata_32_ ^ ~PD_3_; - assign n1079 = (n1076 | n1077) & (n1078 | ~n1351); - assign n1080 = ~n1061 | n1074 | ~n1076 | ~n1349; - assign n1081 = n1674 | n1220; - assign n1082 = n1080 & n1081 & (n1079 | n1073); - assign n1083 = n1061 | n1087; - assign n1084 = n1077 | n1076 | n1083; - assign n1085 = ~n1076 | n1077 | ~n1675; - assign n1086 = ~n1672 | n1073 | n1078; - assign n1087 = ~Pdata_60_ ^ ~PD_13_; - assign n1088 = n1062 & (~n1084 | (n1087 & ~n1676)); - assign n1089 = ~n1349 | n1061 | n1076; - assign n1090 = (~n1061 | n1063) & n1089; - assign n1091 = ~n1352 | n1061 | ~n1087; - assign n1092 = n1066 | ~n1351; - assign n1093 = ~n1061 | n1062 | n1063; - assign n1094 = n1819 & (~n1078 | (n1090 & ~n1950)); - assign n1095 = (n1062 & n1680) | (n1676 & (~n1062 | n1680)); - assign n1096 = (n1075 | ~n1076) & (n1066 | ~n1087); - assign n1097 = n1678 & n1082; - assign n1098 = n1070 & n1094 & n1093 & n1091 & n1092 & n1095 & n1096 & n1097; - assign n1099 = (n746 | n1820) & (~Poutreg_55_ | n869); - assign n1100 = (~Poutreg_54_ | n869) & (~Poutreg_46_ | Pcount_0_); - assign n1101 = ~n1102 | n1120; - assign n1102 = ~Pdata_55_ ^ ~PD_4_; - assign n1103 = n1101 & (n1102 | ~n1120); - assign n1104 = ~n1638 & ~n1639; - assign n1105 = ~n1102 & n1682; - assign n1106 = n1104 & (n1105 | ~n1822); - assign n1107 = ~n1932 & (~n1105 | ~n1132 | ~n1201); - assign n1108 = n1823 & n1824 & (n1130 | n1117); - assign n1109 = n1201 | n1207; - assign n1110 = n1107 & n1108 & (n1109 | ~n1683); - assign n1111 = n1821 & (n1130 | (~n1105 & n1822)); - assign n1112 = n1102 | n1119; - assign n1113 = n1111 & (n1112 | n1109); - assign n1114 = ~n1201 | n1207 | ~n1683; - assign n1115 = (n1109 | n1685) & (n1130 | n1684); - assign n1116 = n1201 | n1211; - assign n1117 = n1133 | n1101; - assign n1118 = n1114 & n1115 & (n1116 | n1117); - assign n1119 = ~n1120 | n1133; - assign n1120 = ~Pdata_51_ ^ ~PD_1_; - assign n1121 = n1119 & (n1120 | ~n1133); - assign n1122 = n1118 & n1113; - assign n1123 = n1931 & (~n1201 | (n1825 & n1826)); - assign n1124 = n1828 & (n1211 | n1685); - assign n1125 = n1124 & n1123 & n1110 & n1122; - assign n1126 = (n746 | n1829) & (~Poutreg_53_ | n869); - assign n1127 = (~Poutreg_52_ | n869) & (~Poutreg_44_ | Pcount_0_); - assign n1128 = n1830 & (n1109 | (n1822 & n1684)); - assign n1129 = n1133 | ~n1681; - assign n1130 = ~n1201 | n1211; - assign n1131 = n1128 & (n1129 | n1130); - assign n1132 = ~n1638 & n1639; - assign n1133 = ~Pdata_54_ ^ ~PD_16_; - assign n1134 = n1132 & (~n1684 | (~n1103 & n1133)); - assign n1135 = (n746 | n1834) & (~Poutreg_51_ | n869); - assign n1136 = (~Poutreg_50_ | n869) & (~Poutreg_42_ | Pcount_0_); - assign n1137 = ~n1649 | n890 | ~n1140; - assign n1138 = (~n878 | n881) & (~n1650 | n1654); - assign n1139 = n1137 & (~n876 | n885) & n1138; - assign n1140 = ~n1398 & n1633; - assign n1141 = n878 & n1140 & n890; - assign n1142 = n1649 & n892; - assign n1143 = n1142 & ~n1397; - assign n1144 = (~Poutreg_49_ | n869) & (n746 | ~n1996); - assign n1145 = (~Poutreg_48_ | n869) & (~Poutreg_40_ | Pcount_0_); - assign n1146 = ~Pdata_35_ ^ ~PC_2_; - assign n1147 = ~n1017 | ~n1039; - assign n1148 = n994 & (n1146 | (~n996 & n1147)); - assign n1149 = ~Pdata_40_ ^ ~PC_9_; - assign n1150 = (n989 | n1146) & (n1149 | n1056); - assign n1151 = (n1148 | ~n1149) & (n1054 | n1150); - assign n1152 = (~n1039 | n1056) & n1151; - assign n1153 = n1001 | n1018; - assign n1154 = (n1146 | n1687) & (~n993 | n1152); - assign n1155 = n1835 & (n994 | n1671); - assign n1156 = n1155 & n1153 & n1009 & n1043 & n1003 & n1154; - assign n1157 = (n746 | n1836) & (~Poutreg_47_ | n869); - assign n1158 = (~Poutreg_46_ | n869) & (~Poutreg_38_ | Pcount_0_); - assign n1159 = ~Pdata_47_ ^ ~PC_12_; - assign n1160 = n980 & (~n950 | (~n981 & n1159)); - assign n1161 = n1159 & n956 & n958; - assign n1162 = n981 & (~n951 | (~n980 & n1161)); - assign n1163 = n981 & n1635; - assign n1164 = n960 & (~n954 | (n980 & n1163)); - assign n1165 = ~n961 | n1663; - assign n1166 = n1165 | n956; - assign n1167 = (n746 | n1837) & (~Poutreg_45_ | n869); - assign n1168 = (~Poutreg_44_ | n869) & (~Poutreg_36_ | Pcount_0_); - assign n1169 = (~n1292 | ~n1726) & (n1177 | ~n1358); - assign n1170 = n1367 | ~n1642; - assign n1171 = n1169 & (n1170 | ~n1303); - assign n1172 = ~n1190 & n1641; - assign n1173 = ~n1299 & ~n1642; - assign n1174 = ~n1292 & ~n1300; - assign n1175 = n1172 & (~n1170 | (n1173 & n1174)); - assign n1176 = n1689 | ~n1296 | ~n1303; - assign n1177 = n1689 | ~n1690; - assign n1178 = ~n1175 & n1176 & (n1177 | ~n1295); - assign n1179 = n1292 | ~n1300; - assign n1180 = (~n1172 | ~n1174) & (n1179 | ~n1358); - assign n1181 = ~n1292 | n1641 | ~n1691; - assign n1182 = n1177 | ~n1303; - assign n1183 = n1181 & n1182 & (n1180 | ~n1298); - assign n1184 = (~n1296 | ~n1358) & (~n1295 | ~n1690); - assign n1185 = ~n1690 | ~n1172 | ~n1302; - assign n1186 = ~n1173 | n1692; - assign n1187 = n1185 & n1186 & (n1184 | ~n1298); - assign n1188 = ~n1302 | ~n1358; - assign n1189 = n1694 | ~n1298 | ~n1300; - assign n1190 = ~Pdata_57_ ^ ~PD_10_; - assign n1191 = n1188 & n1189 & (n1190 | ~n1361); - assign n1192 = n1942 & (n1694 | n1695); - assign n1193 = n1178 & n1171; - assign n1194 = (n1191 | ~n1292) & (~n1299 | n1692); - assign n1195 = (n1370 | ~n1641) & (~n1295 | n1693); - assign n1196 = n1195 & n1187 & n1183 & n1192 & n1193 & n1194; - assign n1197 = (n746 | n1838) & (~Poutreg_43_ | n869); - assign n1198 = (~Poutreg_42_ | n869) & (~Poutreg_34_ | Pcount_0_); - assign n1199 = (~n1681 | ~n1696) & (n1103 | ~n1640); - assign n1200 = ~n1102 | ~n1120; - assign n1201 = ~Pdata_53_ ^ ~PD_22_; - assign n1202 = n1200 & ~n1681 & (n1102 | n1201); - assign n1203 = (n746 | n1840) & (~Poutreg_41_ | n869); - assign n1204 = (~Poutreg_40_ | n869) & (~Poutreg_32_ | Pcount_0_); - assign n1205 = n1639 | n1685; - assign n1206 = n1841 & n1842 & (n1211 | ~n1683); - assign n1207 = ~n1638 | ~n1639; - assign n1208 = n1205 & n1206 & (n1112 | n1207); - assign n1209 = ~n1132 | n1102 | n1121; - assign n1210 = (~n1681 | n1686) & (n1638 | ~n1683); - assign n1211 = ~n1638 | n1639; - assign n1212 = n1209 & n1210 & (n1103 | n1211); - assign n1213 = (~n1201 & n1212) | (n1208 & (n1201 | n1212)); - assign n1214 = n1118 & (n1129 | n1109); - assign n1215 = n1110 & n1214 & n1213 & n1131; - assign n1216 = (n746 | n1843) & (~Poutreg_39_ | n869); - assign n1217 = (~Poutreg_38_ | n869) & (~Poutreg_30_ | Pcount_0_); - assign n1218 = n1066 | n1076 | n1087 | ~n1222; - assign n1219 = n1946 & (n1078 | ~n1672 | ~n1675); - assign n1220 = ~n1078 | ~n1352; - assign n1221 = n1218 & n1219 & (n1220 | ~n1677); - assign n1222 = ~Pdata_62_ ^ ~PD_7_; - assign n1223 = n1074 & (~n1078 | n1222); - assign n1224 = n1073 | ~n1351; - assign n1225 = n1061 | ~n1087 | ~n1222 | n1643; - assign n1226 = n1224 & (~n1062 | n1063) & n1225; - assign n1227 = n1643 | n1223 | n1674; - assign n1228 = ~n1677 | n1222 | ~n1643; - assign n1229 = (n1078 & n1226) | (n1091 & (~n1078 | n1226)); - assign n1230 = n1061 | n1679; - assign n1231 = (~n1087 | n1092) & (n1074 | n1089); - assign n1232 = n1067 & n1221 & n1229 & n1227 & n1228 & n1097 & n1230 & n1231; - assign n1233 = (n746 | n1844) & (~Poutreg_37_ | n869); - assign n1234 = (~Poutreg_36_ | n869) & (~Poutreg_28_ | Pcount_0_); - assign n1235 = n1149 | n1044 | ~n1146; - assign n1236 = ~n1039 | ~n1149; - assign n1237 = n1235 & (~n996 | n1146) & n1236; - assign n1238 = n1949 & (~n1017 | n1057 | n1146); - assign n1239 = ~n993 | n1017 | n1237; - assign n1240 = (n1022 | ~n1050) & (~n1670 | n1687); - assign n1241 = n1240 & n1012 & n1238 & n1043 & n1003 & n1239; - assign n1242 = (n746 | n1845) & (~Poutreg_35_ | n869); - assign n1243 = (~Poutreg_34_ | n869) & (~Poutreg_26_ | Pcount_0_); - assign n1244 = n1846 & (~n1078 | n1093) & ~n1951; - assign n1245 = (n1222 | n1089) & (n1062 | n1680); - assign n1246 = n1225 & n1679 & (n1083 | n1220); - assign n1247 = n1246 & n1244 & n1221 & n1070 & n1082 & n1245; - assign n1248 = (n746 | n1847) & (~Poutreg_33_ | n869); - assign n1249 = (~Poutreg_32_ | n869) & (~Poutreg_24_ | Pcount_0_); - assign n1250 = n1276 | n1382; - assign n1251 = ~n1281 | ~n1285; - assign n1252 = (~n1258 | ~n1259) & (n1250 | n1251); - assign n1253 = n1697 | n1251 | ~n1276; - assign n1254 = n1276 | n1265 | n1384; - assign n1255 = n1253 & n1254 & (n1252 | ~n1317); - assign n1256 = n1644 & n1271; - assign n1257 = n1258 & ~n1276 & n1382; - assign n1258 = ~n1281 & n1285; - assign n1259 = n1276 & ~n1382; - assign n1260 = n1256 & (n1257 | (n1258 & n1259)); - assign n1261 = n1268 | n1251 | ~n1259; - assign n1262 = ~n1325 | ~n1382; - assign n1263 = n1281 | n1268; - assign n1264 = ~n1260 & n1261 & (n1262 | n1263); - assign n1265 = ~n1271 | n1644; - assign n1266 = ~n1276 | ~n1382; - assign n1267 = ~n1258 | n1265 | n1266; - assign n1268 = n1271 | ~n1644; - assign n1269 = ~n1376 | n1268 | ~n1325; - assign n1270 = ~n1256 | n1250 | n1251; - assign n1271 = ~Pdata_44_ ^ ~PC_7_; - assign n1272 = n1644 | ~n1315 | ~n1382; - assign n1273 = ~n1281 | n1271 | n1272; - assign n1274 = n1384 | n1268 | ~n1276; - assign n1275 = n1952 & (n1265 | n1262 | n1281); - assign n1276 = ~Pdata_39_ ^ ~PC_22_; - assign n1277 = ~n1382 | n1263 | ~n1285; - assign n1278 = n1274 & n1275 & (n1276 | n1277); - assign n1279 = (~n1258 & n1276) | (n1251 & (~n1258 | ~n1276)); - assign n1280 = n1279 & (~n1281 | ~n1315); - assign n1281 = ~Pdata_41_ ^ ~PC_11_; - assign n1282 = ~n1376 & (n1281 | ~n1382); - assign n1283 = ~n1317 | n1384; - assign n1284 = n1283 & (~n1256 | n1282 | ~n1285); - assign n1285 = ~Pdata_40_ ^ ~PC_18_; - assign n1286 = (~n1258 | n1276) & (~n1281 | n1285); - assign n1287 = (n1325 & ~n1644) | (~n1280 & (n1325 | n1644)); - assign n1288 = ~n1382 & ~n1271 & n1287; - assign n1289 = n1272 | n1281; - assign n1290 = (n746 | n1849) & (~Poutreg_31_ | n869); - assign n1291 = (~Poutreg_30_ | n869) & (~Poutreg_22_ | Pcount_0_); - assign n1292 = ~Pdata_59_ ^ ~PD_5_; - assign n1293 = ~n1691 | n1292 | ~n1641; - assign n1294 = ~n1690 | ~n1172 | ~n1173; - assign n1295 = ~n1190 & ~n1641; - assign n1296 = n1292 & ~n1300; - assign n1297 = n1295 & (~n1170 | (n1173 & n1296)); - assign n1298 = n1299 & ~n1642; - assign n1299 = ~Pdata_56_ ^ ~PD_20_; - assign n1300 = ~Pdata_55_ ^ ~PD_15_; - assign n1301 = ~n1190 & (n1298 | (n1299 & n1300)); - assign n1302 = n1299 & n1642; - assign n1303 = n1190 & ~n1641; - assign n1304 = n1302 & n1303; - assign n1305 = (n746 | n1852) & (~Poutreg_29_ | n869); - assign n1306 = (~Poutreg_28_ | n869) & (~Poutreg_20_ | Pcount_0_); - assign n1307 = ~n1308 & (~n878 | ~n1397); - assign n1308 = n887 & n888; - assign n1309 = n1308 & n876; - assign n1310 = ~n1398 & (~n1728 | (n896 & ~n1633)); - assign n1311 = ~n1633 | n1653; - assign n1312 = n1311 | ~n1649; - assign n1313 = (n746 | n1854) & (~Poutreg_27_ | n869); - assign n1314 = (~Poutreg_26_ | n869) & (~Poutreg_18_ | Pcount_0_); - assign n1315 = n1276 & ~n1285; - assign n1316 = ~n1281 & ~n1382; - assign n1317 = ~n1271 & ~n1644; - assign n1318 = n1315 & n1316 & (n1317 | n1256); - assign n1319 = n1697 | n1281 | ~n1325; - assign n1320 = ~n1318 & n1319 & (~n1257 | ~n1317); - assign n1321 = ~n1317 | n1251 | ~n1259; - assign n1322 = ~n1315 | n1268 | n1282; - assign n1323 = n1266 & n1250; - assign n1324 = ~n1258 | n1323 | ~n1705; - assign n1325 = ~n1276 & ~n1285; - assign n1326 = ~n1382 & ~n1263 & n1325; - assign n1327 = n1644 & ~n1276 & ~n1384; - assign n1328 = n1327 & n1271; - assign n1329 = (~Poutreg_25_ | n869) & (n746 | ~n1997); - assign n1330 = (~Poutreg_24_ | n869) & (~Poutreg_16_ | Pcount_0_); - assign n1331 = ~n914 | n1646; - assign n1332 = ~n924 & n1331 & (n906 | ~n915); - assign n1333 = ~n906 | n938; - assign n1334 = (~n921 | n1332) & (~n1338 | ~n1658); - assign n1335 = ~n1990 & n1333 & n939 & n905 & n910 & n1334; - assign n1336 = (n746 | n1856) & (~Poutreg_23_ | n869); - assign n1337 = (~Poutreg_22_ | n869) & (~Poutreg_14_ | Pcount_0_); - assign n1338 = ~Pdata_33_ ^ ~PC_10_; - assign n1339 = n921 & (n914 | n1338); - assign n1340 = (n906 & ~n1729) | (n938 & (~n906 | ~n1729)); - assign n1341 = n939 & ~n1662; - assign n1342 = n1961 | n1962 | n920 | ~n1338; - assign n1343 = n903 & (~n914 | n1659); - assign n1344 = ~n1963 & n1342 & n1341 & n910 & n1340 & n1343; - assign n1345 = (n746 | n1857) & (~Poutreg_21_ | n869); - assign n1346 = (~Poutreg_20_ | n869) & (~Poutreg_12_ | Pcount_0_); - assign n1347 = ~n1061 | n1076 | ~n1222; - assign n1348 = n1347 & (n1061 | ~n1076); - assign n1349 = ~n1062 & n1087; - assign n1350 = n1349 & ~n1061 & n1222; - assign n1351 = ~n1076 & ~n1222; - assign n1352 = n1076 & n1062 & n1222; - assign n1353 = ~n1674 & (n1351 | n1352); - assign n1354 = (n746 | n1860) & (~Poutreg_19_ | n869); - assign n1355 = (~Poutreg_18_ | n869) & (~Poutreg_10_ | Pcount_0_); - assign n1356 = n1302 & n1296 & n1303; - assign n1357 = n1172 & ~n1174 & n1298; - assign n1358 = n1641 & n1190; - assign n1359 = (~n1642 & n1702) | (n1174 & (n1642 | n1702)); - assign n1360 = n1359 & ~n1299 & n1358; - assign n1361 = n1298 & ~n1300 & ~n1641; - assign n1362 = ~n1292 & (n1361 | ~n1370); - assign n1363 = (~Poutreg_17_ | n869) & (n746 | ~n1998); - assign n1364 = (~Poutreg_16_ | n869) & (~Poutreg_8_ | Pcount_0_); - assign n1365 = n1702 | ~n1299 | ~n1694; - assign n1366 = n1692 | n1299; - assign n1367 = n1299 | n1179; - assign n1368 = n1365 & n1366 & (~n1358 | n1367); - assign n1369 = n1966 & (n1190 | ~n1300 | n1689); - assign n1370 = ~n1299 | n1688; - assign n1371 = ~n1361 & (~n1641 | (n1369 & n1370)); - assign n1372 = ~n1298 | n1179 | n1190; - assign n1373 = n1303 & (~n1693 | ~n1695); - assign n1374 = (n746 | n1863) & (~Poutreg_15_ | n869); - assign n1375 = (~Poutreg_14_ | n869) & (~Poutreg_6_ | Pcount_0_); - assign n1376 = n1281 & ~n1382; - assign n1377 = ~n1285 & n1376; - assign n1378 = n1263 | n1323; - assign n1379 = (n746 | n1864) & (~Poutreg_13_ | n869); - assign n1380 = (~Poutreg_12_ | n869) & (~Poutreg_4_ | Pcount_0_); - assign n1381 = n1317 | ~n1382; - assign n1382 = ~Pdata_43_ ^ ~PC_25_; - assign n1383 = ~n1285 & n1381 & (~n1263 | n1382); - assign n1384 = n1251 | ~n1382; - assign n1385 = n1277 & ~n1383 & (~n1271 | n1384); - assign n1386 = n1698 & n1321 & n1278 & n1320; - assign n1387 = (n1276 & n1385) | (n1283 & (~n1276 | n1385)); - assign n1388 = n1705 | n1262 | ~n1281; - assign n1389 = ~n1644 | n1250 | ~n1258; - assign n1390 = (n1280 | n1697) & (n1382 | n1706); - assign n1391 = n1390 & n1388 & n1387 & n1386 & n1264 & n1389; - assign n1392 = (n746 | n1865) & (~Poutreg_11_ | n869); - assign n1393 = (~Poutreg_10_ | n869) & (~Poutreg_2_ | Pcount_0_); - assign n1394 = ~n872 & n1397; - assign n1395 = n887 & ~n1634; - assign n1396 = n897 & n1394 & (n1395 | n878); - assign n1397 = ~Pdata_47_ ^ ~PD_12_; - assign n1398 = ~Pdata_52_ ^ ~PD_26_; - assign n1399 = ~n1972 | n1397 | n1398; - assign n1400 = n881 | ~n894; - assign n1401 = (n746 | n1866) & (~Poutreg_9_ | n869); - assign n1402 = (~Poutreg_8_ | n869) & (~Poutreg_0_ | Pcount_0_); - assign n1403 = Pcount_0_ | n1404; - assign n1404 = n837 | Preset_0_; - assign n1405 = n1403 & (Pcount_1_ | n1404); - assign n1406 = n1405 & (Pcount_2_ | n1404); - assign n1407 = Pcount_3_ | n1648; - assign n1408 = n746 & n1407 & (Pcount_0_ | ~n1798); - assign n1409 = (~PC_26_ | n1712) & (~PC_0_ | n1713); - assign n1410 = (~PC_25_ | n1709) & (~PC_1_ | n1711); - assign n1411 = (~PC_27_ | n1718) & n1867; - assign n1412 = n1411 & n1409 & n1410; - assign n1413 = (~PC_27_ | n1713) & (~PC_25_ | n1712); - assign n1414 = (~PC_24_ | n1709) & (~PC_0_ | n1711); - assign n1415 = (~PC_26_ | n1718) & n1868; - assign n1416 = n1415 & n1413 & n1414; - assign n1417 = (~PC_26_ | n1713) & (~PC_24_ | n1712); - assign n1418 = (~PC_27_ | n1711) & (~PC_23_ | n1709); - assign n1419 = (~PC_25_ | n1718) & n1869; - assign n1420 = n1419 & n1417 & n1418; - assign n1421 = (~PC_25_ | n1713) & (~PC_23_ | n1712); - assign n1422 = (~PC_26_ | n1711) & (~PC_22_ | n1709); - assign n1423 = (~PC_24_ | n1718) & n1870; - assign n1424 = n1423 & n1421 & n1422; - assign n1425 = (~PC_24_ | n1713) & (~PC_22_ | n1712); - assign n1426 = (~PC_25_ | n1711) & (~PC_21_ | n1709); - assign n1427 = (~PC_23_ | n1718) & n1871; - assign n1428 = n1427 & n1425 & n1426; - assign n1429 = (~PC_23_ | n1713) & (~PC_21_ | n1712); - assign n1430 = (~PC_24_ | n1711) & (~PC_20_ | n1709); - assign n1431 = (~PC_22_ | n1718) & n1872; - assign n1432 = n1431 & n1429 & n1430; - assign n1433 = (~PC_22_ | n1713) & (~PC_20_ | n1712); - assign n1434 = (~PC_23_ | n1711) & (~PC_19_ | n1709); - assign n1435 = (~PC_21_ | n1718) & n1873; - assign n1436 = n1435 & n1433 & n1434; - assign n1437 = (~PC_21_ | n1713) & (~PC_19_ | n1712); - assign n1438 = (~PC_22_ | n1711) & (~PC_18_ | n1709); - assign n1439 = (~PC_20_ | n1718) & n1874; - assign n1440 = n1439 & n1437 & n1438; - assign n1441 = (~PC_20_ | n1713) & (~PC_18_ | n1712); - assign n1442 = (~PC_21_ | n1711) & (~PC_17_ | n1709); - assign n1443 = (~PC_19_ | n1718) & n1875; - assign n1444 = n1443 & n1441 & n1442; - assign n1445 = (~PC_19_ | n1713) & (~PC_17_ | n1712); - assign n1446 = (~PC_20_ | n1711) & (~PC_16_ | n1709); - assign n1447 = (~PC_18_ | n1718) & n1876; - assign n1448 = n1447 & n1445 & n1446; - assign n1449 = (~PC_18_ | n1713) & (~PC_16_ | n1712); - assign n1450 = (~PC_19_ | n1711) & (~PC_15_ | n1709); - assign n1451 = (~PC_17_ | n1718) & n1877; - assign n1452 = n1451 & n1449 & n1450; - assign n1453 = (~PC_17_ | n1713) & (~PC_15_ | n1712); - assign n1454 = (~PC_18_ | n1711) & (~PC_14_ | n1709); - assign n1455 = (~PC_16_ | n1718) & n1878; - assign n1456 = n1455 & n1453 & n1454; - assign n1457 = (~PC_16_ | n1713) & (~PC_14_ | n1712); - assign n1458 = (~PC_17_ | n1711) & (~PC_13_ | n1709); - assign n1459 = (~PC_15_ | n1718) & n1879; - assign n1460 = n1459 & n1457 & n1458; - assign n1461 = (~PC_15_ | n1713) & (~PC_13_ | n1712); - assign n1462 = (~PC_16_ | n1711) & (~PC_12_ | n1709); - assign n1463 = (~PC_14_ | n1718) & n1880; - assign n1464 = n1463 & n1461 & n1462; - assign n1465 = (~PC_14_ | n1713) & (~PC_12_ | n1712); - assign n1466 = (~PC_15_ | n1711) & (~PC_11_ | n1709); - assign n1467 = (~PC_13_ | n1718) & n1881; - assign n1468 = n1467 & n1465 & n1466; - assign n1469 = (~PC_13_ | n1713) & (~PC_11_ | n1712); - assign n1470 = (~PC_14_ | n1711) & (~PC_10_ | n1709); - assign n1471 = (~PC_12_ | n1718) & n1882; - assign n1472 = n1471 & n1469 & n1470; - assign n1473 = (~PC_12_ | n1713) & (~PC_10_ | n1712); - assign n1474 = (~PC_13_ | n1711) & (~PC_9_ | n1709); - assign n1475 = (~PC_11_ | n1718) & n1883; - assign n1476 = n1475 & n1473 & n1474; - assign n1477 = (~PC_11_ | n1713) & (~PC_9_ | n1712); - assign n1478 = (~PC_12_ | n1711) & (~PC_8_ | n1709); - assign n1479 = (~PC_10_ | n1718) & n1884; - assign n1480 = n1479 & n1477 & n1478; - assign n1481 = (~PC_10_ | n1713) & (~PC_8_ | n1712); - assign n1482 = (~PC_11_ | n1711) & (~PC_7_ | n1709); - assign n1483 = (~PC_9_ | n1718) & n1885; - assign n1484 = n1483 & n1481 & n1482; - assign n1485 = (~PC_9_ | n1713) & (~PC_7_ | n1712); - assign n1486 = (~PC_10_ | n1711) & (~PC_6_ | n1709); - assign n1487 = (~PC_8_ | n1718) & n1886; - assign n1488 = n1487 & n1485 & n1486; - assign n1489 = (~PC_8_ | n1713) & (~PC_6_ | n1712); - assign n1490 = (~PC_9_ | n1711) & (~PC_5_ | n1709); - assign n1491 = (~PC_7_ | n1718) & n1887; - assign n1492 = n1491 & n1489 & n1490; - assign n1493 = (~PC_7_ | n1713) & (~PC_5_ | n1712); - assign n1494 = (~PC_8_ | n1711) & (~PC_4_ | n1709); - assign n1495 = (~PC_6_ | n1718) & n1888; - assign n1496 = n1495 & n1493 & n1494; - assign n1497 = (~PC_6_ | n1713) & (~PC_4_ | n1712); - assign n1498 = (~PC_7_ | n1711) & (~PC_3_ | n1709); - assign n1499 = (~PC_5_ | n1718) & n1889; - assign n1500 = n1499 & n1497 & n1498; - assign n1501 = (~PC_5_ | n1713) & (~PC_3_ | n1712); - assign n1502 = (~PC_6_ | n1711) & (~PC_2_ | n1709); - assign n1503 = (~PC_4_ | n1718) & n1890; - assign n1504 = n1503 & n1501 & n1502; - assign n1505 = (~PC_4_ | n1713) & (~PC_2_ | n1712); - assign n1506 = (~PC_5_ | n1711) & (~PC_1_ | n1709); - assign n1507 = (~PC_3_ | n1718) & n1891; - assign n1508 = n1507 & n1505 & n1506; - assign n1509 = (~PC_3_ | n1713) & (~PC_1_ | n1712); - assign n1510 = (~PC_4_ | n1711) & (~PC_0_ | n1709); - assign n1511 = (~PC_2_ | n1718) & n1892; - assign n1512 = n1511 & n1509 & n1510; - assign n1513 = (~PC_2_ | n1713) & (~PC_0_ | n1712); - assign n1514 = (~PC_27_ | n1709) & (~PC_3_ | n1711); - assign n1515 = (~PC_1_ | n1718) & n1893; - assign n1516 = n1515 & n1513 & n1514; - assign n1517 = (~PC_27_ | n1712) & (~PC_1_ | n1713); - assign n1518 = (~PC_26_ | n1709) & (~PC_2_ | n1711); - assign n1519 = (~PC_0_ | n1718) & n1894; - assign n1520 = n1519 & n1517 & n1518; - assign n1521 = (~PD_26_ | n1712) & (~PD_0_ | n1713); - assign n1522 = (~PD_25_ | n1709) & (~PD_1_ | n1711); - assign n1523 = (~PD_27_ | n1718) & n1895; - assign n1524 = n1523 & n1521 & n1522; - assign n1525 = (~PD_27_ | n1713) & (~PD_25_ | n1712); - assign n1526 = (~PD_24_ | n1709) & (~PD_0_ | n1711); - assign n1527 = (~PD_26_ | n1718) & n1896; - assign n1528 = n1527 & n1525 & n1526; - assign n1529 = (~PD_26_ | n1713) & (~PD_24_ | n1712); - assign n1530 = (~PD_27_ | n1711) & (~PD_23_ | n1709); - assign n1531 = (~PD_25_ | n1718) & n1897; - assign n1532 = n1531 & n1529 & n1530; - assign n1533 = (~PD_25_ | n1713) & (~PD_23_ | n1712); - assign n1534 = (~PD_26_ | n1711) & (~PD_22_ | n1709); - assign n1535 = (~PD_24_ | n1718) & n1898; - assign n1536 = n1535 & n1533 & n1534; - assign n1537 = (~PD_24_ | n1713) & (~PD_22_ | n1712); - assign n1538 = (~PD_25_ | n1711) & (~PD_21_ | n1709); - assign n1539 = (~PD_23_ | n1718) & n1899; - assign n1540 = n1539 & n1537 & n1538; - assign n1541 = (~PD_23_ | n1713) & (~PD_21_ | n1712); - assign n1542 = (~PD_24_ | n1711) & (~PD_20_ | n1709); - assign n1543 = (~PD_22_ | n1718) & n1900; - assign n1544 = n1543 & n1541 & n1542; - assign n1545 = (~PD_22_ | n1713) & (~PD_20_ | n1712); - assign n1546 = (~PD_23_ | n1711) & (~PD_19_ | n1709); - assign n1547 = (~PD_21_ | n1718) & n1901; - assign n1548 = n1547 & n1545 & n1546; - assign n1549 = (~PD_21_ | n1713) & (~PD_19_ | n1712); - assign n1550 = (~PD_22_ | n1711) & (~PD_18_ | n1709); - assign n1551 = (~PD_20_ | n1718) & n1902; - assign n1552 = n1551 & n1549 & n1550; - assign n1553 = (~PD_20_ | n1713) & (~PD_18_ | n1712); - assign n1554 = (~PD_21_ | n1711) & (~PD_17_ | n1709); - assign n1555 = (~PD_19_ | n1718) & n1903; - assign n1556 = n1555 & n1553 & n1554; - assign n1557 = (~PD_19_ | n1713) & (~PD_17_ | n1712); - assign n1558 = (~PD_20_ | n1711) & (~PD_16_ | n1709); - assign n1559 = (~PD_18_ | n1718) & n1904; - assign n1560 = n1559 & n1557 & n1558; - assign n1561 = (~PD_18_ | n1713) & (~PD_16_ | n1712); - assign n1562 = (~PD_19_ | n1711) & (~PD_15_ | n1709); - assign n1563 = (~PD_17_ | n1718) & n1905; - assign n1564 = n1563 & n1561 & n1562; - assign n1565 = (~PD_17_ | n1713) & (~PD_15_ | n1712); - assign n1566 = (~PD_18_ | n1711) & (~PD_14_ | n1709); - assign n1567 = (~PD_16_ | n1718) & n1906; - assign n1568 = n1567 & n1565 & n1566; - assign n1569 = (~PD_16_ | n1713) & (~PD_14_ | n1712); - assign n1570 = (~PD_17_ | n1711) & (~PD_13_ | n1709); - assign n1571 = (~PD_15_ | n1718) & n1907; - assign n1572 = n1571 & n1569 & n1570; - assign n1573 = (~PD_15_ | n1713) & (~PD_13_ | n1712); - assign n1574 = (~PD_16_ | n1711) & (~PD_12_ | n1709); - assign n1575 = (~PD_14_ | n1718) & n1908; - assign n1576 = n1575 & n1573 & n1574; - assign n1577 = (~PD_14_ | n1713) & (~PD_12_ | n1712); - assign n1578 = (~PD_15_ | n1711) & (~PD_11_ | n1709); - assign n1579 = (~PD_13_ | n1718) & n1909; - assign n1580 = n1579 & n1577 & n1578; - assign n1581 = (~PD_13_ | n1713) & (~PD_11_ | n1712); - assign n1582 = (~PD_14_ | n1711) & (~PD_10_ | n1709); - assign n1583 = (~PD_12_ | n1718) & n1910; - assign n1584 = n1583 & n1581 & n1582; - assign n1585 = (~PD_12_ | n1713) & (~PD_10_ | n1712); - assign n1586 = (~PD_13_ | n1711) & (~PD_9_ | n1709); - assign n1587 = (~PD_11_ | n1718) & n1911; - assign n1588 = n1587 & n1585 & n1586; - assign n1589 = (~PD_11_ | n1713) & (~PD_9_ | n1712); - assign n1590 = (~PD_12_ | n1711) & (~PD_8_ | n1709); - assign n1591 = (~PD_10_ | n1718) & n1912; - assign n1592 = n1591 & n1589 & n1590; - assign n1593 = (~PD_10_ | n1713) & (~PD_8_ | n1712); - assign n1594 = (~PD_11_ | n1711) & (~PD_7_ | n1709); - assign n1595 = (~PD_9_ | n1718) & n1913; - assign n1596 = n1595 & n1593 & n1594; - assign n1597 = (~PD_9_ | n1713) & (~PD_7_ | n1712); - assign n1598 = (~PD_10_ | n1711) & (~PD_6_ | n1709); - assign n1599 = (~PD_8_ | n1718) & n1914; - assign n1600 = n1599 & n1597 & n1598; - assign n1601 = (~PD_8_ | n1713) & (~PD_6_ | n1712); - assign n1602 = (~PD_9_ | n1711) & (~PD_5_ | n1709); - assign n1603 = (~PD_7_ | n1718) & n1915; - assign n1604 = n1603 & n1601 & n1602; - assign n1605 = (~PD_7_ | n1713) & (~PD_5_ | n1712); - assign n1606 = (~PD_8_ | n1711) & (~PD_4_ | n1709); - assign n1607 = (~PD_6_ | n1718) & n1916; - assign n1608 = n1607 & n1605 & n1606; - assign n1609 = (~PD_6_ | n1713) & (~PD_4_ | n1712); - assign n1610 = (~PD_7_ | n1711) & (~PD_3_ | n1709); - assign n1611 = (~PD_5_ | n1718) & n1917; - assign n1612 = n1611 & n1609 & n1610; - assign n1613 = (~PD_5_ | n1713) & (~PD_3_ | n1712); - assign n1614 = (~PD_6_ | n1711) & (~PD_2_ | n1709); - assign n1615 = (~PD_4_ | n1718) & n1918; - assign n1616 = n1615 & n1613 & n1614; - assign n1617 = (~PD_4_ | n1713) & (~PD_2_ | n1712); - assign n1618 = (~PD_5_ | n1711) & (~PD_1_ | n1709); - assign n1619 = (~PD_3_ | n1718) & n1919; - assign n1620 = n1619 & n1617 & n1618; - assign n1621 = (~PD_3_ | n1713) & (~PD_1_ | n1712); - assign n1622 = (~PD_4_ | n1711) & (~PD_0_ | n1709); - assign n1623 = (~PD_2_ | n1718) & n1920; - assign n1624 = n1623 & n1621 & n1622; - assign n1625 = (~PD_2_ | n1713) & (~PD_0_ | n1712); - assign n1626 = (~PD_27_ | n1709) & (~PD_3_ | n1711); - assign n1627 = (~PD_1_ | n1718) & n1921; - assign n1628 = n1627 & n1625 & n1626; - assign n1629 = (~PD_27_ | n1712) & (~PD_1_ | n1713); - assign n1630 = (~PD_26_ | n1709) & (~PD_2_ | n1711); - assign n1631 = (~PD_0_ | n1718) & n1922; - assign n1632 = n1631 & n1629 & n1630; - assign n1633 = ~Pdata_48_ ^ ~PD_23_; - assign n1634 = ~Pdata_51_ ^ ~PD_18_; - assign n1635 = ~Pdata_45_ ^ ~PC_26_; - assign n1636 = ~Pdata_38_ ^ ~PC_5_; - assign n1637 = n993 & (~n1002 | (n1039 & ~n1149)); - assign n1638 = ~Pdata_52_ ^ ~PD_11_; - assign n1639 = ~Pdata_56_ ^ ~PD_19_; - assign n1640 = ~n1639 ^ ~n1133; - assign n1641 = ~Pdata_60_ ^ ~PD_24_; - assign n1642 = ~Pdata_58_ ^ ~PD_27_; - assign n1643 = ~n1062 ^ n1076; - assign n1644 = ~Pdata_42_ ^ ~PC_3_; - assign n1645 = ~n1649 & (~n887 | ~n1633); - assign n1646 = ~n906 ^ n1338; - assign n1647 = ~Pencrypt_mode_0_ ^ Pencrypt_0_; - assign n1648 = ~Pcount_0_ | ~Pcount_2_ | ~Pcount_1_; - assign n1649 = ~n887 & ~n1634; - assign n1650 = n887 & n1634; - assign n1651 = ~n1398 & ~n1633; - assign n1652 = n1649 & n876; - assign n1653 = n1398 | ~n872 | ~n1397; - assign n1654 = ~n1397 | ~n872 | ~n876; - assign n1655 = ~n1338 | n916 | ~n920; - assign n1656 = n920 & n901; - assign n1657 = n914 & ~n1338; - assign n1658 = ~n920 & ~n914 & n916; - assign n1659 = ~n1338 | n920 | ~n921; - assign n1660 = n1656 & ~n906 & n914; - assign n1661 = n906 & n1657 & n935; - assign n1662 = n1660 | n1661 | n925 | n927; - assign n1663 = n980 | n972; - assign n1664 = n972 | ~n980; - assign n1665 = ~n980 | n1635; - assign n1666 = n956 | n1030 | n980; - assign n1667 = n1665 | n956 | n981; - assign n1668 = n1664 | n956 | n958; - assign n1669 = n956 | ~n980 | n1030 | ~n1635; - assign n1670 = n993 | n1146; - assign n1671 = n989 | n993; - assign n1672 = n1076 & ~n1222; - assign n1673 = ~n1061 | n1071; - assign n1674 = ~n1061 | n1087; - assign n1675 = ~n1062 & ~n1674; - assign n1676 = n1078 | n1347; - assign n1677 = n1061 & n1087; - assign n1678 = ~n1088 & n1085 & n1086; - assign n1679 = n1078 | n1071 | ~n1076; - assign n1680 = ~n1078 | n1087 | n1347; - assign n1681 = ~n1102 & ~n1120; - assign n1682 = n1120 & n1133; - assign n1683 = n1102 & n1682; - assign n1684 = ~n1102 | n1119; - assign n1685 = ~n1133 | ~n1681; - assign n1686 = ~n1104 | n1133; - assign n1687 = n989 | ~n996; - assign n1688 = ~n1642 | n1190 | n1300; - assign n1689 = n1299 | ~n1642; - assign n1690 = n1300 & n1292; - assign n1691 = ~n1299 & ~n1688; - assign n1692 = ~n1174 | ~n1303; - assign n1693 = n1179 | ~n1302; - assign n1694 = ~n1172 & ~n1303; - assign n1695 = n1367 | n1642; - assign n1696 = n1639 & n1133; - assign n1697 = n1382 | n1265; - assign n1698 = n1269 & n1267 & n1270 & n1273; - assign n1699 = n1255 & n1698 & n1264; - assign n1700 = n1303 & ~n1642 & n1690; - assign n1701 = n1190 | n1695; - assign n1702 = ~n1174 & ~n1690; - assign n1703 = ~n1297 & n1294 & n1187 & n1293; - assign n1704 = n886 & n1139; - assign n1705 = n1317 | n1256; - assign n1706 = ~n1705 | ~n1281 | ~n1325; - assign n1707 = n1404 | ~n1717; - assign n1708 = Pencrypt_mode_0_ | n1707; - assign n1709 = ~n1408 | n1708; - assign n1710 = ~Pencrypt_mode_0_ | n1707; - assign n1711 = ~n1408 | n1710; - assign n1712 = n1408 | n1708; - assign n1713 = n1408 | n1710; - assign n1714 = Preset_0_ | ~n837; - assign n1715 = Pencrypt_0_ | n1714; - assign n1716 = ~Pencrypt_0_ | n1714; - assign n1717 = n1647 | n746; - assign n1718 = n1404 | n1717; - assign n1719 = n1923 & (~n900 | n913 | ~n916); - assign n1720 = ~n1925 & (~n906 | (n914 & n935)); - assign n1721 = (n934 & ~n1338) | (n926 & (n934 | n1338)); - assign n1722 = n956 & (n961 | (~n958 & n981)); - assign n1723 = (~n980 & ~n1722) | (n975 & (n980 | ~n1722)); - assign n1724 = (~n954 & (~n956 | ~n1664)) | (n956 & ~n1664); - assign n1725 = ~n1936 & (n887 | ~n892 | n1397); - assign n1726 = (n1641 & n1691) | (~n1370 & (~n1641 | n1691)); - assign n1727 = n1943 & (n1199 | ~n1201); - assign n1728 = (n1397 & n1645) | (~n878 & (~n1397 | n1645)); - assign n1729 = n920 & (n1339 | (n1657 & n912)); - assign n1730 = n892 & (n896 | (~n887 & n888)); - assign n1731 = n1650 & (n892 | (~n1397 & n1398)); - assign n1732 = (n746 & n1863) | (~Pdata_in_6_ & (~n746 | n1863)); - assign n1733 = (n746 & n1856) | (~Pinreg_6_ & (~n746 | n1856)); - assign n1734 = (n746 & n1849) | (~Pinreg_14_ & (~n746 | n1849)); - assign n1735 = (n746 & n1843) | (~Pinreg_22_ & (~n746 | n1843)); - assign n1736 = (n746 & n1836) | (~Pinreg_30_ & (~n746 | n1836)); - assign n1737 = (n746 & n1820) | (~Pinreg_38_ & (~n746 | n1820)); - assign n1738 = (n746 & n1810) | (~Pinreg_46_ & (~n746 | n1810)); - assign n1739 = (n746 & n899) | (~Pinreg_54_ & (~n746 | n899)); - assign n1740 = (n746 & n1864) | (~Pdata_in_4_ & (~n746 | n1864)); - assign n1741 = (n746 & n1857) | (~Pinreg_4_ & (~n746 | n1857)); - assign n1742 = (n746 & n1852) | (~Pinreg_12_ & (~n746 | n1852)); - assign n1743 = (n746 & n1844) | (~Pinreg_20_ & (~n746 | n1844)); - assign n1744 = (n746 & n1837) | (~Pinreg_28_ & (~n746 | n1837)); - assign n1745 = (n746 & n1829) | (~Pinreg_36_ & (~n746 | n1829)); - assign n1746 = (n746 & n1815) | (~Pinreg_44_ & (~n746 | n1815)); - assign n1747 = (n746 & n931) | (~Pinreg_52_ & (~n746 | n931)); - assign n1748 = (n746 & n1865) | (~Pdata_in_2_ & (~n746 | n1865)); - assign n1749 = (n746 & n1860) | (~Pinreg_2_ & (~n746 | n1860)); - assign n1750 = (n746 & n1854) | (~Pinreg_10_ & (~n746 | n1854)); - assign n1751 = (n746 & n1845) | (~Pinreg_18_ & (~n746 | n1845)); - assign n1752 = (n746 & n1838) | (~Pinreg_26_ & (~n746 | n1838)); - assign n1753 = (n746 & n1834) | (~Pinreg_34_ & (~n746 | n1834)); - assign n1754 = (n746 & n1816) | (~Pinreg_42_ & (~n746 | n1816)); - assign n1755 = (n746 & n948) | (~Pinreg_50_ & (~n746 | n948)); - assign n1756 = (n746 & n1866) | (~Pdata_in_0_ & (~n746 | n1866)); - assign n1757 = (~Pinreg_0_ & (~n746 | ~n1998)) | (n746 & ~n1998); - assign n1758 = (~Pinreg_8_ & (~n746 | ~n1997)) | (n746 & ~n1997); - assign n1759 = (n746 & n1847) | (~Pinreg_16_ & (~n746 | n1847)); - assign n1760 = (n746 & n1840) | (~Pinreg_24_ & (~n746 | n1840)); - assign n1761 = (~Pinreg_32_ & (~n746 | ~n1996)) | (n746 & ~n1996); - assign n1762 = (n746 & n1817) | (~Pinreg_40_ & (~n746 | n1817)); - assign n1763 = (n746 & n976) | (~Pinreg_48_ & (~n746 | n976)); - assign n1764 = (~Pdata_63_ & n746) | (~Pdata_in_7_ & (~Pdata_63_ | ~n746)); - assign n1765 = (~Pdata_62_ & n746) | (~Pinreg_7_ & (~Pdata_62_ | ~n746)); - assign n1766 = (~Pdata_61_ & n746) | (~Pinreg_15_ & (~Pdata_61_ | ~n746)); - assign n1767 = (~Pdata_60_ & n746) | (~Pinreg_23_ & (~Pdata_60_ | ~n746)); - assign n1768 = (~Pdata_59_ & n746) | (~Pinreg_31_ & (~Pdata_59_ | ~n746)); - assign n1769 = (~Pdata_58_ & n746) | (~Pinreg_39_ & (~Pdata_58_ | ~n746)); - assign n1770 = (~Pdata_57_ & n746) | (~Pinreg_47_ & (~Pdata_57_ | ~n746)); - assign n1771 = (~Pdata_56_ & n746) | (~Pinreg_55_ & (~Pdata_56_ | ~n746)); - assign n1772 = (~Pdata_55_ & n746) | (~Pdata_in_5_ & (~Pdata_55_ | ~n746)); - assign n1773 = (~Pdata_54_ & n746) | (~Pinreg_5_ & (~Pdata_54_ | ~n746)); - assign n1774 = (~Pdata_53_ & n746) | (~Pinreg_13_ & (~Pdata_53_ | ~n746)); - assign n1775 = (~Pdata_52_ & n746) | (~Pinreg_21_ & (~Pdata_52_ | ~n746)); - assign n1776 = (~Pdata_51_ & n746) | (~Pinreg_29_ & (~Pdata_51_ | ~n746)); - assign n1777 = (~Pdata_50_ & n746) | (~Pinreg_37_ & (~Pdata_50_ | ~n746)); - assign n1778 = (~Pdata_49_ & n746) | (~Pinreg_45_ & (~Pdata_49_ | ~n746)); - assign n1779 = (~Pdata_48_ & n746) | (~Pinreg_53_ & (~Pdata_48_ | ~n746)); - assign n1780 = (~Pdata_47_ & n746) | (~Pdata_in_3_ & (~Pdata_47_ | ~n746)); - assign n1781 = (~Pdata_46_ & n746) | (~Pinreg_3_ & (~Pdata_46_ | ~n746)); - assign n1782 = (~Pdata_45_ & n746) | (~Pinreg_11_ & (~Pdata_45_ | ~n746)); - assign n1783 = (~Pdata_44_ & n746) | (~Pinreg_19_ & (~Pdata_44_ | ~n746)); - assign n1784 = (~Pdata_43_ & n746) | (~Pinreg_27_ & (~Pdata_43_ | ~n746)); - assign n1785 = (~Pdata_42_ & n746) | (~Pinreg_35_ & (~Pdata_42_ | ~n746)); - assign n1786 = (~Pdata_41_ & n746) | (~Pinreg_43_ & (~Pdata_41_ | ~n746)); - assign n1787 = (~Pdata_40_ & n746) | (~Pinreg_51_ & (~Pdata_40_ | ~n746)); - assign n1788 = (~Pdata_39_ & n746) | (~Pdata_in_1_ & (~Pdata_39_ | ~n746)); - assign n1789 = (~Pdata_38_ & n746) | (~Pinreg_1_ & (~Pdata_38_ | ~n746)); - assign n1790 = (~Pdata_37_ & n746) | (~Pinreg_9_ & (~Pdata_37_ | ~n746)); - assign n1791 = (~Pdata_36_ & n746) | (~Pinreg_17_ & (~Pdata_36_ | ~n746)); - assign n1792 = (~Pdata_35_ & n746) | (~Pinreg_25_ & (~Pdata_35_ | ~n746)); - assign n1793 = (~Pdata_34_ & n746) | (~Pinreg_33_ & (~Pdata_34_ | ~n746)); - assign n1794 = (~Pdata_33_ & n746) | (~Pinreg_41_ & (~Pdata_33_ | ~n746)); - assign n1795 = (~Pdata_32_ & n746) | (~Pinreg_49_ & (~Pdata_32_ | ~n746)); - assign n1796 = (~Pcount_2_ | n1405) & n1974; - assign n1797 = (~Pcount_1_ | n1403) & n1975; - assign n1798 = ~n1976 & (~Pcount_1_ | (Pcount_3_ & Pcount_2_)); - assign n1799 = (~Pencrypt_0_ & ~n746) | (~Pencrypt_mode_0_ & (~Pencrypt_0_ | n746)); - assign n1800 = n872 | ~n876 | ~n878 | n1397; - assign n1801 = (~n1395 | n1654) & (n887 | n1311); - assign n1802 = (~n1142 | ~n1397) & (~n1649 | n1653); - assign n1803 = ~n916 | n1338 | n913 | n914; - assign n1804 = ~n1163 | n980 | ~n1161; - assign n1805 = n1665 | ~n981 | ~n1161; - assign n1806 = (n973 | n980) & (n1159 | n1668); - assign n1807 = n968 | n1635 | n981; - assign n1808 = n1807 & (~n958 | n980 | n1030); - assign n1809 = ~n1163 | ~n980 | ~n1161; - assign n1810 = ~Pdata_25_ ^ ~n1980; - assign n1811 = ~n1051 | n1005 | ~n1039; - assign n1812 = ~n1051 | ~n1039 | ~n1049; - assign n1813 = n1812 & (n1013 | n993 | n1056); - assign n1814 = n1146 | n989 | ~n1050; - assign n1815 = ~n1023 ^ ~Pdata_17_; - assign n1816 = ~n1036 ^ ~Pdata_9_; - assign n1817 = ~Pdata_1_ ^ ~n1981; - assign n1818 = ~n1076 | n1077; - assign n1819 = ~n1061 | n1679; - assign n1820 = ~n1098 ^ ~Pdata_26_; - assign n1821 = n1207 | n1117 | ~n1201; - assign n1822 = n1101 | ~n1133; - assign n1823 = n1116 | n1112; - assign n1824 = ~n1201 | n1129 | ~n1132; - assign n1825 = (~n1638 | n1685) & (n1112 | n1211); - assign n1826 = (n1121 | ~n1132) & (~n1681 | n1686); - assign n1827 = ~n1640 | n1200 | n1638; - assign n1828 = n1827 & (n1109 | (~n1105 & n1117)); - assign n1829 = ~n1125 ^ ~Pdata_18_; - assign n1830 = n1686 | n1200 | n1201; - assign n1831 = n1207 | n1121 | n1102; - assign n1832 = n1831 & (n1103 | n1686); - assign n1833 = (n1211 | ~n1683) & (n1205 | n1638); - assign n1834 = ~Pdata_10_ ^ ~n1982; - assign n1835 = (~n1039 | n1053) & (n1005 | n1042); - assign n1836 = ~n1156 ^ ~Pdata_27_; - assign n1837 = ~Pdata_19_ ^ ~n1984; - assign n1838 = ~n1196 ^ ~Pdata_11_; - assign n1839 = (n1202 | n1686) & (n1116 | ~n1683); - assign n1840 = ~Pdata_3_ ^ ~n1985; - assign n1841 = n1682 | ~n1102 | ~n1132; - assign n1842 = ~n1133 | n1102 | ~n1104; - assign n1843 = ~n1215 ^ ~Pdata_28_; - assign n1844 = ~n1232 ^ ~Pdata_20_; - assign n1845 = ~n1241 ^ ~Pdata_12_; - assign n1846 = (n1076 & n1673) | (n1075 & (~n1076 | n1673)); - assign n1847 = ~n1247 ^ ~Pdata_4_; - assign n1848 = (~n1276 | n1284) & (n1286 | n1697); - assign n1849 = ~Pdata_29_ ^ ~n1986; - assign n1850 = n1694 | ~n1296 | ~n1298; - assign n1851 = n1850 & (n1299 | ~n1700); - assign n1852 = ~Pdata_21_ ^ ~n1987; - assign n1853 = (~n892 | n1307) & (n1397 | ~n1652); - assign n1854 = ~Pdata_13_ ^ ~n1988; - assign n1855 = (n1271 | n1262) & (n1265 | n1266); - assign n1856 = ~n1335 ^ ~Pdata_30_; - assign n1857 = ~n1344 ^ ~Pdata_22_; - assign n1858 = n1673 & (~n1062 | ~n1087 | n1348); - assign n1859 = (n1071 | n1076) & (n1089 | ~n1222); - assign n1860 = ~Pdata_14_ ^ ~n1991; - assign n1861 = (n1641 | n1701) & (~n1190 | n1693); - assign n1862 = (~n1292 | n1371) & (n1368 | ~n1642); - assign n1863 = ~Pdata_31_ ^ ~n1993; - assign n1864 = ~Pdata_23_ ^ ~n1994; - assign n1865 = ~n1391 ^ ~Pdata_15_; - assign n1866 = ~Pdata_7_ ^ ~n1995; - assign n1867 = (~Pinreg_48_ | n1716) & (~Pinreg_27_ | n1715); - assign n1868 = (~Pinreg_35_ | n1715) & (~Pinreg_27_ | n1716); - assign n1869 = (~Pinreg_43_ | n1715) & (~Pinreg_35_ | n1716); - assign n1870 = (~Pinreg_51_ | n1715) & (~Pinreg_43_ | n1716); - assign n1871 = (~Pinreg_51_ | n1716) & (~Pdata_in_2_ | n1715); - assign n1872 = (~Pinreg_2_ | n1715) & (~Pdata_in_2_ | n1716); - assign n1873 = (~Pinreg_10_ | n1715) & (~Pinreg_2_ | n1716); - assign n1874 = (~Pinreg_18_ | n1715) & (~Pinreg_10_ | n1716); - assign n1875 = (~Pinreg_26_ | n1715) & (~Pinreg_18_ | n1716); - assign n1876 = (~Pinreg_34_ | n1715) & (~Pinreg_26_ | n1716); - assign n1877 = (~Pinreg_42_ | n1715) & (~Pinreg_34_ | n1716); - assign n1878 = (~Pinreg_50_ | n1715) & (~Pinreg_42_ | n1716); - assign n1879 = (~Pinreg_50_ | n1716) & (~Pdata_in_1_ | n1715); - assign n1880 = (~Pinreg_1_ | n1715) & (~Pdata_in_1_ | n1716); - assign n1881 = (~Pinreg_9_ | n1715) & (~Pinreg_1_ | n1716); - assign n1882 = (~Pinreg_17_ | n1715) & (~Pinreg_9_ | n1716); - assign n1883 = (~Pinreg_25_ | n1715) & (~Pinreg_17_ | n1716); - assign n1884 = (~Pinreg_33_ | n1715) & (~Pinreg_25_ | n1716); - assign n1885 = (~Pinreg_41_ | n1715) & (~Pinreg_33_ | n1716); - assign n1886 = (~Pinreg_49_ | n1715) & (~Pinreg_41_ | n1716); - assign n1887 = (~Pinreg_49_ | n1716) & (~Pdata_in_0_ | n1715); - assign n1888 = (~Pinreg_0_ | n1715) & (~Pdata_in_0_ | n1716); - assign n1889 = (~Pinreg_8_ | n1715) & (~Pinreg_0_ | n1716); - assign n1890 = (~Pinreg_16_ | n1715) & (~Pinreg_8_ | n1716); - assign n1891 = (~Pinreg_24_ | n1715) & (~Pinreg_16_ | n1716); - assign n1892 = (~Pinreg_32_ | n1715) & (~Pinreg_24_ | n1716); - assign n1893 = (~Pinreg_40_ | n1715) & (~Pinreg_32_ | n1716); - assign n1894 = (~Pinreg_48_ | n1715) & (~Pinreg_40_ | n1716); - assign n1895 = (~Pinreg_54_ | n1716) & (~Pdata_in_3_ | n1715); - assign n1896 = (~Pinreg_3_ | n1715) & (~Pdata_in_3_ | n1716); - assign n1897 = (~Pinreg_11_ | n1715) & (~Pinreg_3_ | n1716); - assign n1898 = (~Pinreg_19_ | n1715) & (~Pinreg_11_ | n1716); - assign n1899 = (~Pinreg_19_ | n1716) & (~Pdata_in_4_ | n1715); - assign n1900 = (~Pinreg_4_ | n1715) & (~Pdata_in_4_ | n1716); - assign n1901 = (~Pinreg_12_ | n1715) & (~Pinreg_4_ | n1716); - assign n1902 = (~Pinreg_20_ | n1715) & (~Pinreg_12_ | n1716); - assign n1903 = (~Pinreg_28_ | n1715) & (~Pinreg_20_ | n1716); - assign n1904 = (~Pinreg_36_ | n1715) & (~Pinreg_28_ | n1716); - assign n1905 = (~Pinreg_44_ | n1715) & (~Pinreg_36_ | n1716); - assign n1906 = (~Pinreg_52_ | n1715) & (~Pinreg_44_ | n1716); - assign n1907 = (~Pinreg_52_ | n1716) & (~Pdata_in_5_ | n1715); - assign n1908 = (~Pinreg_5_ | n1715) & (~Pdata_in_5_ | n1716); - assign n1909 = (~Pinreg_13_ | n1715) & (~Pinreg_5_ | n1716); - assign n1910 = (~Pinreg_21_ | n1715) & (~Pinreg_13_ | n1716); - assign n1911 = (~Pinreg_29_ | n1715) & (~Pinreg_21_ | n1716); - assign n1912 = (~Pinreg_37_ | n1715) & (~Pinreg_29_ | n1716); - assign n1913 = (~Pinreg_45_ | n1715) & (~Pinreg_37_ | n1716); - assign n1914 = (~Pinreg_53_ | n1715) & (~Pinreg_45_ | n1716); - assign n1915 = (~Pinreg_53_ | n1716) & (~Pdata_in_6_ | n1715); - assign n1916 = (~Pinreg_6_ | n1715) & (~Pdata_in_6_ | n1716); - assign n1917 = (~Pinreg_14_ | n1715) & (~Pinreg_6_ | n1716); - assign n1918 = (~Pinreg_22_ | n1715) & (~Pinreg_14_ | n1716); - assign n1919 = (~Pinreg_30_ | n1715) & (~Pinreg_22_ | n1716); - assign n1920 = (~Pinreg_38_ | n1715) & (~Pinreg_30_ | n1716); - assign n1921 = (~Pinreg_46_ | n1715) & (~Pinreg_38_ | n1716); - assign n1922 = (~Pinreg_54_ | n1715) & (~Pinreg_46_ | n1716); - assign n1923 = ~n932 | n915 | n916; - assign n1924 = ~n1338 & (n919 | n922 | ~n1719); - assign n1925 = ~n906 & (~n900 | n912 | n916); - assign n1926 = ~n906 & (~n921 | n1338); - assign n1927 = ~n1635 & (~n1723 | (~n951 & ~n981)); - assign n1928 = n958 & n1635 & (~n951 | ~n1666); - assign n1929 = n1078 & (~n1064 | (n1351 & n1675)); - assign n1930 = ~n1062 | ~n1078 | ~n1351 | ~n1677; - assign n1931 = n1201 | n1103 | n1686; - assign n1932 = ~n1201 & (n1106 | (~n1117 & n1132)); - assign n1933 = n1201 & (~n1832 | (~n1638 & n1683)); - assign n1934 = ~n1201 & (n1134 | (n1640 & n1681)); - assign n1935 = (n1308 & ~n1633) | (n896 & (n1308 | n1633)); - assign n1936 = n1397 & (n1652 | (n892 & n887)); - assign n1937 = n872 & (~n1725 | (n893 & n897)); - assign n1938 = n1935 & ~n872 & ~n1398; - assign n1939 = n1160 | ~n1666; - assign n1940 = ~n1635 & (n1162 | (n958 & n1939)); - assign n1941 = ~n1635 | n975 | n980; - assign n1942 = n1702 | ~n1173 | ~n1694; - assign n1943 = n1696 | n1201 | ~n1681; - assign n1944 = ~n1638 & (~n1727 | (n1639 & n1683)); - assign n1945 = ~n1638 | ~n1696 | n1103 | ~n1201; - assign n1946 = ~n1078 | n1347 | ~n1349; - assign n1947 = n993 & ~n1039; - assign n1948 = ~n993 & (n1017 | n1044); - assign n1949 = n1947 | n1948 | ~n1146 | ~n1149; - assign n1950 = n1351 & n1349; - assign n1951 = ~n1078 & (n1950 | (n1352 & n1677)); - assign n1952 = ~n1256 | ~n1281 | ~n1315 | ~n1382; - assign n1953 = ~n1702 & (n1304 | (n1298 & n1358)); - assign n1954 = ~n1702 | ~n1358 | ~n1642; - assign n1955 = ~n1292 & ~n1641 & (n1301 | n1691); - assign n1956 = ~n1641 | n1701; - assign n1957 = n872 & (~n1853 | (n893 & n1651)); - assign n1958 = ~n872 & (n1142 | n1309 | n1310); - assign n1959 = n1281 & (~n1855 | (n1325 & ~n1697)); - assign n1960 = ~n1281 & (~n1977 | (n1315 & ~n1697)); - assign n1961 = n914 & n911; - assign n1962 = ~n914 & (~n913 | n916); - assign n1963 = ~n1338 & (n1658 | (n921 & n926)); - assign n1964 = n1078 & (~n1858 | (~n1073 & n1672)); - assign n1965 = ~n1078 & (~n1090 | n1350 | n1353); - assign n1966 = ~n1190 | n1299 | n1300; - assign n1967 = n1265 | n1276 | n1282 | ~n1285; - assign n1968 = n1276 & n1705 & (n1377 | ~n1384); - assign n1969 = ~n1271 | n1272; - assign n1970 = ~n1271 & (n1327 | (n1316 & n1325)); - assign n1971 = (n872 & n1650) | (n1649 & (~n872 | n1650)); - assign n1972 = (n1633 & n1971) | (n878 & (~n1633 | n1971)); - assign n1973 = (~n872 & ~n1731) | (~n1730 & (n872 | ~n1731)); - assign n1974 = Pcount_2_ | ~Pcount_1_ | ~Pcount_0_ | n1404; - assign n1975 = n1404 | Pcount_1_ | ~Pcount_0_; - assign n1976 = ~Pcount_1_ & (Pcount_3_ | Pcount_2_); - assign n1977 = ~n1256 | n1262; - assign n1978 = n1802 & n891 & n886 & n875 & n882 & ~n895 & ~n898 & n1801; - assign n1979 = ~n1928 & ~n1927 & n1806 & n963 & n1033; - assign n1980 = n1668 & n1029 & ~n985 & n984 & ~n982 & n979 & n963 & n966; - assign n1981 = n1058 & n1055 & ~n1052 & n1045 & n1043 & n999 & n1014 & n1048; - assign n1982 = n1833 & n1131 & n1110 & n1113 & ~n1933 & ~n1934; - assign n1983 = ~n875 | n877 | ~n882 | ~n1139 | n1937 | n1938 | n1141 | n1143; - assign n1984 = n1941 & ~n1940 & n1669 & n1166 & ~n1164 & n979 & n963 & n969; - assign n1985 = n1839 & n1131 & n1107 & n1122 & ~n1944 & n1945; - assign n1986 = n1848 & n1706 & n1699 & n1278 & ~n1288 & n1289; - assign n1987 = n1956 & ~n1955 & n1851 & n1703 & n1171 & n1183 & ~n1953 & n1954; - assign n1988 = n1704 & n1312 & n873 & n882 & ~n1957 & ~n1958; - assign n1989 = n1959 | n1960 | n1328 | ~n1386 | ~n1255 | ~n1322 | ~n1324 | n1326; - assign n1990 = n1646 & n912 & ~n915 & ~n916; - assign n1991 = n1859 & n1678 & n1070 & n1221 & ~n1964 & ~n1965; - assign n1992 = n1362 | n1700 | ~n1703 | ~n1861 | ~n1193 | n1356 | n1357 | n1360; - assign n1993 = n1862 & n1703 & ~n1373 & n1372 & n1178 & n1183; - assign n1994 = n1977 & ~n1970 & n1967 & n1699 & n1320 & n1378 & ~n1968 & n1969; - assign n1995 = n1973 & n1704 & n1400 & n875 & ~n1396 & n1399; - assign n1996 = ~Pdata_2_ ^ ~n1983; - assign n1997 = ~Pdata_5_ ^ ~n1989; - assign n1998 = ~Pdata_6_ ^ ~n1992; -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/diffeq/diffeq.v b/fpga_flow/benchmarks/Verilog/MCNC/diffeq/diffeq.v deleted file mode 100644 index 419c09c79..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/diffeq/diffeq.v +++ /dev/null @@ -1,1523 +0,0 @@ -// Benchmark "TOP" written by ABC on Tue Mar 5 09:56:39 2019 - -module diffeq ( clock, - PRESET, Pdxport_0_0_, Pdxport_1_1_, Pdxport_2_2_, Pdxport_3_3_, - Pdxport_4_4_, Pdxport_5_5_, Pdxport_6_6_, Pdxport_7_7_, Pdxport_8_8_, - Pdxport_9_9_, Pdxport_10_10_, Pdxport_11_11_, Paport_0_0_, Paport_1_1_, - Paport_2_2_, Paport_3_3_, Paport_4_4_, Paport_5_5_, Paport_6_6_, - Paport_7_7_, Paport_8_8_, Paport_9_9_, Paport_10_10_, Paport_11_11_, - Preset_0_0_, Pready_0_0_, - PDN, Pnext_0_0_, Pover_0_0_ ); - input clock, PRESET, Pdxport_0_0_, Pdxport_1_1_, Pdxport_2_2_, - Pdxport_3_3_, Pdxport_4_4_, Pdxport_5_5_, Pdxport_6_6_, Pdxport_7_7_, - Pdxport_8_8_, Pdxport_9_9_, Pdxport_10_10_, Pdxport_11_11_, - Paport_0_0_, Paport_1_1_, Paport_2_2_, Paport_3_3_, Paport_4_4_, - Paport_5_5_, Paport_6_6_, Paport_7_7_, Paport_8_8_, Paport_9_9_, - Paport_10_10_, Paport_11_11_, Preset_0_0_, Pready_0_0_; - output PDN, Pnext_0_0_, Pover_0_0_; - reg N_N4054, N_N3745, N_N4119, N_N3826, N_N3818, N_N3345, N_N3924, - N_N3815, N_N3691, N_N3157, N_N3872, N_N3788, N_N3375, N_N3143, N_N4197, - N_N3843, N_N3426, N_N4118, N_N3580, N_N3175, N_N3071, N_N3808, N_N3923, - N_N3250, N_N4221, N_N3069, N_N3464, N_N3535, N_N3871, N_N3248, N_N4180, - N_N3311, N_N3442, N_N3981, N_N3842, N_N3105, N_N4133, N_N4117, N_N3420, - N_N3761, N_N3062, N_N4071, N_N4227, N_N3807, N_N4145, N_N3922, N_N3516, - N_N3489, N_N4030, N_N3540, N_N3513, N_N4083, N_N3841, N_N4018, N_N3971, - N_N4232, N_N4246, N_N3806, N_N3992, N_N4086, N_N4230, N_N4212, - Pnext_0_0_, N_N3626, N_N3965, N_N3890, NDN3_11, NDN5_10, N_N3786, - N_N4171, NDN5_16, N_N3799, N_N3844, N_N3196, N_N4126, N_N3681, N_N3679, - N_N3340, N_N4116, N_N3810, N_N3235, N_N3283, N_N3716, N_N3701, N_N3921, - N_N3625, N_N3751, N_N3736, N_N3870, N_N4024, N_N3876, N_N3840, N_N4021, - N_N3932, NLC1_2, N_N3805, N_N3700, N_N3735, NLak3_2, NLak3_9, N_N3906, - N_N3388, N_N4057, N_N3011, N_N3346, N_N3677, N_N4165, N_N4080, N_N3373, - N_N3709, N_N4206, N_N3324, N_N3575, N_N4159, NAK5_2, N_N3916, N_N3743, - N_N4242, N_N3312, N_N3733, N_N3774, N_N4214, N_N3294, N_N3796, N_N3574, - N_N3791, N_N3480, N_N4243, N_N3940, N_N3509, N_N4015, N_N2989, N_N3919, - N_N3578, N_N3529, N_N4222, N_N3910, N_N3868, N_N3947, N_N4181, N_N3793, - N_N3822, N_N3813, N_N4114, N_N4134, N_N3866, N_N4218, N_N3939, N_N3776, - N_N3387, N_N4194, N_N3821, N_N3882, N_N4167, N_N3800, N_N4237, N_N3417, - N_N3918, N_N4158, N_N3630, N_N3344, N_N4072, N_N3274, N_N3473, N_N4205, - N_N4111, N_N3680, N_N3838, N_N3262, N_N4099, N_N3607, N_N3323, N_N3612, - N_N4079, PDN, N_N3457, N_N3445, N_N3794, N_N3663, N_N3715, N_N4039, - N_N3280, N_N4239, N_N3988, N_N3433, N_N4075, N_N3468, N_N4045, N_N3482, - N_N3832, N_N3304, N_N3750, N_N3634, N_N3293, N_N3659, N_N4252, N_N3912, - N_N3862, N_N3221, N_N3875, N_N3949, N_N3908, N_N3711, N_N3931, N_N3469, - N_N3436, N_N3974, N_N3905, N_N3741, N_N3369, N_N3164, N_N3500, N_N3996, - N_N3356, N_N4093, Pover_0_0_, N_N4224, N_N4027, NDN1_4, N_N3384, - N_N4036, N_N3968, N_N4183, NGFDN_3, N_N4090, N_N4004, N_N3205, N_N4136, - N_N3303, N_N3533, N_N3336, N_N3961, N_N3331, N_N3203, N_N4236, N_N3884, - N_N3367, N_N4140, NDN2_2, N_N4106, N_N3100, N_N4193, N_N3470, N_N3424, - N_N3959, N_N3393, N_N4042, N_N3188, N_N4095, N_N3957, N_N3517, N_N4047, - N_N3081, N_N3541, N_N4177, NDN3_3, N_N4176, N_N3585, NDN3_8, N_N4209, - N_N3824, N_N4208, N_N4120, N_N3708, N_N4220, N_N3999, N_N4223, N_N3179, - N_N4179, N_N3475, N_N4132, N_N4182, N_N3797, N_N3214, N_N4070, N_N4135, - NLD3_9, NDN5_2, NDN5_3, N_N3778, NDN5_4, N_N3212, NDN5_5, NDN5_6, - NDN5_7, NDN5_8, N_N4073, NDN5_9, NEN5_9, N_N3684, N_N4056, N_N3713, - N_N3829, N_N4060, NSr3_2, NSr5_2, NSr5_3, N_N3462, N_N3460, NSr5_4, - NSr3_9, NSr5_5, NSr5_7, NSr5_8, N_N3998; - wire n946, n947, n949, n951, n953, n955, n957, n959, n961, n963, n965, - n967, n969, n971, n973, n975, n977, n979, n981, n983, n985, n987, n989, - n991, n993, n995, n997, n999, n1001, n1003, n1005, n1007, n1009, - n1011_1, n1013, n1015, n1017, n1019, n1021_1, n1023, n1025, n1027, - n1030, n1032, n1034, n1036_1, n1038, n1040, n1042, n1044, n1046_1, - n1048, n1050, n1052, n1054, n1056_1, n1058, n1060, n1062, n1065, n1067, - n1069, n1071_1, n1073, n1076_1, n1078, n1081, n1083, n1085, n1087, - n1089, n1091, n1093, n1095, n1097, n1099, n1101_1, n1104, n1106_1, - n1107, n1110, n1112, n1114, n1116, n1118, n1120, n1122, n1124, n1126_1, - n1128, n1130, n1132, n1134, n1136_1, n1138, n1140_1, n1142, n1145_1, - n1147, n1149, n1151, n1153, n1155_1, n1157, n1159, n1161, n1163, - n1165_1, n1167, n1169, n1171, n1173, n1176, n1178, n1180, n1182, n1184, - n1186, n1189, n1192, n1194, n1196, n1198, n1200, n1202, n1204, n1206, - n1211, n1213, n1215_1, n1217, n1220_1, n1223, n1225_1, n1227, n1229, - n1231, n1233, n1235, n1237, n1239, n1241, n1244, n1248, n1250, n1252, - n1254, n1256, n1258, n1260_1, n1262, n1264, n1266, n1268, n1270_1, - n1272, n1274, n1276, n1278, n1280_1, n1282, n1284, n1286, n1288, n1291, - n1293, n1295, n1297, n1299, n1301, n1303, n1305_1, n1307, n1309, n1311, - n1313, n1315_1, n1317, n1319, n1321, n1323, n1325_1, n1330_1, n1332, - n1334, n1336, n1338, n1340_1, n1342, n1344, n1346, n1348, n1350_1, - n1352, n1355_1, n1357, n1359, n1361, n1363, n1365_1, n1367, n1369, - n1371, n1373, n1375_1, n1377, n1380_1, n1382, n1384, n1387, n1389, - n1391, n1393, n1395_1, n1397, n1399, n1401, n1404, n1407, n1409, n1411, - n1413, n1416, n1418, n1420_1, n1422, n1424, n1426, n1428, n1430_1, - n1432, n1434, n1437, n1439, n1441, n1443, n1445_1, n1447, n1449, n1451, - n1453, n1455_1, n1457, n1459, n1461, n1463, n1465_1, n1469, n1471, - n1473, n1475_1, n1479, n1481, n1483, n1485_1, n1487, n1489, n1491, - n1493, n1495_1, n1497, n1499, n1501, n1503, n1505_1, n1507, n1509, - n1510_1, n1511, n1512, n1513, n1514, n1515_1, n1516, n1517, n1518, - n1519, n1520_1, n1521, n1522, n1523, n1524, n1525_1, n1526, n1527, - n1528, n1529, n1530_1, n1531, n1532, n1533, n1534, n1535_1, n1536, - n1537, n1538, n1539, n1540_1, n1541, n1542, n1543, n1544, n1545_1, - n1546, n1547, n1548, n1549, n1550_1, n1551, n1552, n1553, n1554, - n1555_1, n1556, n1557, n1558, n1559, n1560_1, n1561, n1562, n1564, - n1565_1, n1566, n1567, n1568, n1569, n1570_1, n1571, n1572, n1573, - n1574, n1575_1, n1576, n1577, n1578, n1579, n1580_1, n1581, n1582, - n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, - n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, - n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, - n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, - n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, - n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, - n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, - n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, - n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, - n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, - n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, - n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, - n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, - n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, - n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, - n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, - n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, - n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, - n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, - n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, - n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, - n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, - n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, - n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, - n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, - n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, - n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, - n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, - n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, - n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, - n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, - n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, - n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, - n1913, n1914, n1915, n1916, n1918, n1920, n1923, n1924, n1925, n1926, - n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, - n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, - n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, - n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, - n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1975, n1976, n1979, - n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, - n1990, n1991, n1992, n1993, n63_1, n68_1, n73_1, n78_1, n83_1, n88, - n93_1, n98_1, n103, n108_1, n113_1, n118_1, n123_1, n128, n133, n138_1, - n143_1, n148_1, n153_1, n158_1, n163_1, n168_1, n173_1, n178_1, n183_1, - n188_1, n193_1, n198_1, n203_1, n208_1, n213_1, n218_1, n223_1, n228_1, - n233, n238, n243_1, n248_1, n253_1, n258_1, n263_1, n268, n273, n278_1, - n283, n288_1, n293, n298, n303_1, n308_1, n313_1, n318_1, n323_1, - n328_1, n333_1, n338_1, n343_1, n348_1, n353_1, n358_1, n363_1, n368, - n373, n377, n382_1, n387_1, n392_1, n397_1, n402_1, n407, n412_1, - n417_1, n422_1, n427, n432_1, n437_1, n442, n447, n452_1, n457, n462, - n467, n472, n477, n482, n487_1, n492, n497, n502_1, n507, n512, n517_1, - n522_1, n527, n532, n537_1, n542_1, n547, n552, n557_1, n562, n567_1, - n572, n577_1, n582, n587, n592, n597_1, n602_1, n607_1, n612, n617, - n622, n627, n632, n637_1, n642_1, n647, n652, n657, n662_1, n667, n672, - n677, n682_1, n687_1, n692, n697, n702_1, n707, n712_1, n717, n722_1, - n727_1, n732, n737, n742_1, n747, n752_1, n757, n762, n767_1, n772, - n777, n782, n787, n792, n797, n802_1, n807_1, n812_1, n817, n822_1, - n827_1, n832_1, n837, n842_1, n847_1, n852_1, n857_1, n862, n867_1, - n872_1, n877, n882_1, n887_1, n892_1, n897_1, n902, n907, n912, n917, - n922, n927_1, n932_1, n936, n941, n946_1, n951_1, n956_1, n961_1, - n966_1, n971_1, n976, n981_1, n986, n991_1, n996, n1001_1, n1006_1, - n1011, n1016_1, n1021, n1026, n1031_1, n1036, n1041_1, n1046, n1051_1, - n1056, n1061_1, n1066_1, n1071, n1076, n1081_1, n1086_1, n1091_1, - n1096, n1101, n1106, n1111, n1116_1, n1121, n1126, n1131, n1136, n1140, - n1145, n1150, n1155, n1160, n1165, n1170, n1175, n1180_1, n1185_1, - n1190, n1195_1, n1200_1, n1205_1, n1210_1, n1215, n1220, n1225, - n1230_1, n1235_1, n1240, n1245_1, n1250_1, n1255, n1260, n1265, n1270, - n1275_1, n1280, n1285_1, n1290_1, n1295_1, n1300, n1305, n1310, n1315, - n1320, n1325, n1330, n1335, n1340, n1345, n1350, n1355, n1360, n1365, - n1370, n1375, n1380, n1385, n1390, n1395, n1400, n1405, n1410, n1415, - n1420, n1425, n1430, n1435, n1440, n1445, n1450, n1455, n1460, n1465, - n1470, n1475, n1480, n1485, n1490, n1495, n1500, n1505, n1510, n1515, - n1520, n1525, n1530, n1535, n1540, n1545, n1550, n1555, n1560, n1565, - n1570, n1575, n1580; - assign n946 = ~PRESET & n1558; - assign n947 = N_N3460 & ~n1556 & n1557; - assign n1385 = n946 & (n947 | N_N3999); - assign n949 = (n1585 | ~N_N4239) & (PRESET | n1584); - assign n971_1 = ~n949; - assign n951 = n1586 | ~N_N4232; - assign n338_1 = ~n951; - assign n953 = n1586 | ~N_N4230; - assign n363_1 = ~n953; - assign n955 = n1586 | ~N_N4218; - assign n792 = ~n955; - assign n957 = ~PRESET & n1961; - assign n737 = N_N4222 & n957; - assign n959 = (n1644 | ~n1934) & (~n1962 | ~N_N4167); - assign n827_1 = ~n959; - assign n961 = (n1585 | ~N_N4140) & (PRESET | n1646); - assign n1245_1 = ~n961; - assign n963 = (n1648 | ~n1934) & (n1647 | ~N_N4114); - assign n777 = ~n963; - assign n965 = (n1653 | n1654) & (n1652 | ~N_N4111); - assign n887_1 = ~n965; - assign n967 = n1586 | ~N_N4106; - assign n1255 = ~n967; - assign n969 = (n1585 | ~N_N4099) & (PRESET | n1656); - assign n907 = ~n969; - assign n971 = (n1585 | ~N_N4095) & (PRESET | n1658); - assign n1300 = ~n971; - assign n973 = n1586 | ~N_N4090; - assign n1180_1 = ~n973; - assign n975 = (n1585 | ~N_N4086) & (PRESET | n1660); - assign n358_1 = ~n975; - assign n977 = (n1662 | n1663) & (n1661 | ~N_N4075); - assign n986 = ~n977; - assign n979 = (n1586 | ~N_N4056) & (~Paport_5_5_ | n1587); - assign n1510 = ~n979; - assign n981 = (n1586 | ~N_N4054) & (~Paport_7_7_ | n1587); - assign n63_1 = ~n981; - assign n983 = (n1665 | n1666) & (n1664 | ~N_N4047); - assign n1315 = ~n983; - assign n985 = (n1664 | ~N_N4045) & (n1663 | n1665); - assign n996 = ~n985; - assign n987 = (n1668 | n1669) & (n1667 | ~N_N4042); - assign n1290_1 = ~n987; - assign n989 = (n1668 | n1670) & (n1667 | ~N_N4039); - assign n961_1 = ~n989; - assign n991 = (n1648 | n1709) & (n1647 | ~N_N4079); - assign n927_1 = ~n991; - assign n993 = (n1711 | n1712) & (n1710 | ~N_N4030); - assign n303_1 = ~n993; - assign n995 = (n1713 | ~N_N4236) & (n1670 | n1714); - assign n1230_1 = ~n995; - assign n997 = (n1662 | n1715) & (n1661 | ~N_N4024); - assign n507 = ~n997; - assign n999 = (n1662 | n1716) & (n1661 | ~N_N4021); - assign n522_1 = ~n999; - assign n1001 = (n1586 | ~N_N4057) & (~Pdxport_2_2_ | n1587); - assign n572 = ~n1001; - assign n1003 = (n1738 | n1739) & (n1737 | ~N_N3988); - assign n976 = ~n1003; - assign n1005 = (n1654 | n1740) & (n1652 | ~N_N3981); - assign n228_1 = ~n1005; - assign n1007 = (n1665 | n1741) & (n1664 | ~N_N4116); - assign n452_1 = ~n1007; - assign n1009 = (n1668 | n1741) & (n1667 | ~N_N3968); - assign n1165 = ~n1009; - assign n1011_1 = (n1586 | ~N_N4179) & (~Pdxport_5_5_ | n1587); - assign n1400 = ~n1011_1; - assign n1013 = (n1662 | n1741) & (n1661 | ~N_N3959); - assign n1280 = ~n1013; - assign n1015 = (n1662 | n1742) & (n1661 | ~N_N3957); - assign n1305 = ~n1015; - assign n1017 = (n1644 | n1743) & (~n1962 | ~N_N3947); - assign n752_1 = ~n1017; - assign n1019 = (n1586 | ~N_N4220) & (~Pdxport_3_3_ | n1587); - assign n1380 = ~n1019; - assign n1021_1 = (n1586 | ~N_N3916) & (~Paport_0_0_ | n1587); - assign n637_1 = ~n1021_1; - assign n1023 = (n1586 | ~N_N4243) & (~Paport_6_6_ | n1587); - assign n697 = ~n1023; - assign n1025 = (n1586 | ~N_N4015) & (~Paport_8_8_ | n1587); - assign n712_1 = ~n1025; - assign n1027 = (n1714 | n1744) & (n1713 | ~N_N3910); - assign n742_1 = ~n1027; - assign n1096 = N_N3905 & n957; - assign n1030 = (n1586 | ~N_N4120) & (~Pdxport_1_1_ | n1587); - assign n1370 = ~n1030; - assign n1032 = (n1808 | ~N_N4197) & (n1806 | n1807); - assign n133 = ~n1032; - assign n1034 = (n1644 | n1809) & (~n1962 | ~N_N3829); - assign n1520 = ~n1034; - assign n1036_1 = (n1644 | n1810) & (~n1962 | ~N_N3826); - assign n78_1 = ~n1036_1; - assign n1038 = (n1662 | n1669) & (n1661 | ~N_N3824); - assign n1360 = ~n1038; - assign n1040 = (n1586 | ~N_N3818) & (~Paport_9_9_ | n1587); - assign n83_1 = ~n1040; - assign n1042 = (n1644 | n1811) & (~n1962 | ~N_N3815); - assign n98_1 = ~n1042; - assign n1044 = n1586 | ~N_N3876; - assign n512 = ~n1044; - assign n1046_1 = (n1585 | ~N_N3971) & (PRESET | n1813); - assign n333_1 = ~n1046_1; - assign n1048 = (n1668 | n1715) & (n1667 | ~N_N3799); - assign n417_1 = ~n1048; - assign n1050 = (n1644 | n1814) & (~n1962 | ~N_N3796); - assign n677 = ~n1050; - assign n1052 = (n1644 | n1815) & (~n1962 | ~N_N3788); - assign n118_1 = ~n1052; - assign n1054 = n1586 | ~N_N3786; - assign n402_1 = ~n1054; - assign n1056_1 = (n1665 | n1712) & (n1664 | ~N_N3870); - assign n502_1 = ~n1056_1; - assign n1058 = ~PRESET & ~NGFDN_3; - assign n1350 = n1058 & (NDN3_8 | NDN3_3); - assign n1060 = n1816 & (PRESET | ~N_N3745); - assign n68_1 = ~n1060; - assign n1062 = n1586 | ~N_N3741; - assign n1101 = ~n1062; - assign n1460 = ~PRESET & ~NSr5_4; - assign n1065 = (n1808 | ~N_N3992) & (n1807 | n1817); - assign n353_1 = ~n1065; - assign n1067 = (n1713 | ~N_N4193) & (n1663 | n1714); - assign n1265 = ~n1067; - assign n1069 = (n1808 | ~N_N4018) & (n1807 | n1818); - assign n328_1 = ~n1069; - assign n1071_1 = (n1648 | n1819) & (n1647 | ~N_N3713); - assign n1515 = ~n1071_1; - assign n1073 = (n1711 | n1716) & (n1710 | ~N_N3711); - assign n1071 = ~n1073; - assign n1375 = N_N3708 & n957; - assign n1076_1 = (n1586 | ~N_N3882) & (~Paport_10_10_ | n1587); - assign n822_1 = ~n1076_1; - assign n1078 = (n1714 | n1715) & (n1713 | ~N_N3793); - assign n762 = ~n1078; - assign n103 = N_N3691 & n957; - assign n1081 = (n1644 | n1820) & (~n1962 | ~N_N3684); - assign n1505 = ~n1081; - assign n1083 = (n1585 | ~N_N4252) & (PRESET | n1822); - assign n1036 = ~n1083; - assign n1085 = (n1585 | ~N_N3843) & (PRESET | n1824); - assign n138_1 = ~n1085; - assign n1087 = (n1648 | n1825) & (n1647 | ~N_N3743); - assign n642_1 = ~n1087; - assign n1089 = (n1648 | n1826) & (n1647 | ~N_N3774); - assign n662_1 = ~n1089; - assign n1091 = (n1737 | ~N_N3663) & (n1670 | n1738); - assign n951_1 = ~n1091; - assign n1093 = (n1711 | n1741) & (n1710 | ~N_N4117); - assign n248_1 = ~n1093; - assign n1095 = (n1665 | n1670) & (n1664 | ~N_N3659); - assign n1031_1 = ~n1095; - assign n1097 = (n1648 | n1827) & (n1647 | ~N_N3791); - assign n687_1 = ~n1097; - assign n1099 = (n1711 | n1742) & (n1710 | ~N_N3922); - assign n288_1 = ~n1099; - assign n1101_1 = (n1654 | n1828) & (n1652 | ~N_N3761); - assign n258_1 = ~n1101_1; - assign n632 = ~PRESET & ~n1558; - assign n1104 = n1586 | ~N_N3634; - assign n1021 = ~n1104; - assign n1106_1 = (n1735 | n1736) & (N_N3336 | ~N_N4205); - assign n1107 = NLD3_9 & (n1106_1 | (N_N3336 & ~N_N4205)); - assign n532 = ~PRESET & ~PDN; - assign n932_1 = n532 & (NGFDN_3 | ~n1169); - assign n1110 = (n1829 | ~NEN5_9) & (NLD3_9 | n1830); - assign n1500 = ~n1110; - assign n1112 = (n1648 | n1831) & (n1647 | ~N_N3709); - assign n607_1 = ~n1112; - assign n1114 = (n1737 | ~N_N4071) & (n1669 | n1738); - assign n268 = ~n1114; - assign n1116 = (n1714 | n1716) & (n1713 | ~N_N3776); - assign n802_1 = ~n1116; - assign n1118 = (n1662 | n1670) & (n1661 | ~N_N3612); - assign n922 = ~n1118; - assign n1120 = (n1808 | ~N_N3949) & (n1807 | n1832); - assign n1061_1 = ~n1120; - assign n1122 = (n1836 | ~N_N4212) & (PRESET | n1835); - assign n368 = ~n1122; - assign n1124 = (n1836 | ~N_N4171) & (PRESET | n1838); - assign n407 = ~n1124; - assign n1126_1 = (n1586 | ~N_N3733) & (~Paport_2_2_ | n1587); - assign n657 = ~n1126_1; - assign n1128 = (n1585 | ~N_N3918) & (PRESET | n1840); - assign n847_1 = ~n1128; - assign n1130 = (n1585 | ~N_N3939) & (PRESET | n1842); - assign n797 = ~n1130; - assign n1132 = (n1585 | ~N_N4224) & (PRESET | n1844); - assign n1140 = ~n1132; - assign n1134 = (n1662 | n1845) & (n1661 | ~N_N3585); - assign n1345 = ~n1134; - assign n1136_1 = n1586 | ~N_N3580; - assign n153_1 = ~n1136_1; - assign n1138 = n1846 & (n1847 | ~N_N3751); - assign n387_1 = ~n1138; - assign n1140_1 = (n1654 | n1831) & (n1652 | ~N_N3794); - assign n946_1 = ~n1140_1; - assign n1142 = (n1662 | n1744) & (n1661 | ~N_N3625); - assign n487_1 = ~n1142; - assign n1335 = n1058 & (NDN3_3 | ~NSr3_2); - assign n1145_1 = (n1665 | n1742) & (n1664 | ~N_N3921); - assign n482 = ~n1145_1; - assign n1147 = (n1586 | ~N_N3574) & (~Paport_4_4_ | n1587); - assign n682_1 = ~n1147; - assign n1149 = (n1586 | ~N_N4205) & (~Paport_11_11_ | n1587); - assign n882_1 = ~n1149; - assign n1151 = (n1585 | ~N_N4118) & (PRESET | n1849); - assign n148_1 = ~n1151; - assign n1153 = (n1585 | ~N_N4209) & (PRESET | n1851); - assign n1355 = ~n1153; - assign n1155_1 = (n1585 | ~N_N3500) & (PRESET | n1853); - assign n1116_1 = ~n1155_1; - assign n1157 = (n1654 | n1854) & (n1652 | ~N_N3489); - assign n298 = ~n1157; - assign n1159 = (n1654 | n1819) & (n1652 | ~N_N3513); - assign n313_1 = ~n1159; - assign n1161 = (n1738 | n1742) & (n1737 | ~N_N4221); - assign n183_1 = ~n1161; - assign n1163 = (n1586 | ~N_N4206) & (~Pdxport_6_6_ | n1587); - assign n612 = ~n1163; - assign n1165_1 = (n1667 | ~N_N3482) & (n1663 | n1668); - assign n1001_1 = ~n1165_1; - assign n1167 = n1855 & (n1847 | ~N_N4080); - assign n1340 = ~n1167; - assign n1169 = ~Preset_0_0_ | PDN | NLC1_2; - assign n1250_1 = ~PRESET & n1169 & NDN2_2; - assign n1171 = (n1648 | n1740) & (n1647 | ~N_N3475); - assign n1405 = ~n1171; - assign n1173 = (n1737 | ~N_N3473) & (n1663 | n1738); - assign n877 = ~n1173; - assign n557_1 = ~PRESET & n1107; - assign n1176 = ~n1440 & (n1829 | ~NEN5_9); - assign n1495 = ~n1176; - assign n1178 = (n1667 | ~N_N3736) & (n1666 | n1668); - assign n497 = ~n1178; - assign n1180 = (n1654 | n1856) & (n1652 | ~N_N3535); - assign n198_1 = ~n1180; - assign n1182 = (n1808 | ~N_N3912) & (n1807 | n1857); - assign n1041_1 = ~n1182; - assign n1184 = (n1648 | n1862) & (n1647 | ~N_N4158); - assign n852_1 = ~n1184; - assign n1186 = (n1711 | n1739) & (n1710 | ~N_N3436); - assign n1086_1 = ~n1186; - assign n897_1 = ~PRESET & (n947 | N_N3838); - assign n1189 = (n1711 | n1845) & (n1710 | ~N_N3841); - assign n323_1 = ~n1189; - assign n143_1 = N_N3426 & n957; - assign n1192 = (n1665 | n1716) & (n1664 | ~N_N3424); - assign n1275_1 = ~n1192; - assign n1194 = n1586 | ~N_N3417; - assign n842_1 = ~n1194; - assign n1196 = (n1585 | ~N_N3842) & (PRESET | n1864); - assign n233 = ~n1196; - assign n1198 = (n1585 | ~N_N3924) & (PRESET | n1866); - assign n93_1 = ~n1198; - assign n1200 = (n1585 | ~N_N4119) & (PRESET | n1868); - assign n73_1 = ~n1200; - assign n1202 = n1586 | ~N_N3517; - assign n1310 = ~n1202; - assign n1204 = n1586 | ~N_N3681; - assign n437_1 = ~n1204; - assign n1206 = n1586 | ~N_N3716; - assign n472 = ~n1206; - assign n757 = N_N4181 & n957; - assign n727_1 = N_N3578 & n946; - assign n123_1 = N_N3375 & n957; - assign n1211 = n1586 | ~N_N3373; - assign n602_1 = ~n1211; - assign n1213 = (n1665 | n1715) & (n1664 | ~N_N3367); - assign n1240 = ~n1213; - assign n1215_1 = n1586 | ~N_N3533; - assign n1205_1 = ~n1215_1; - assign n1217 = (n1585 | ~N_N3808) & (PRESET | n1870); - assign n168_1 = ~n1217; - assign n1470 = ~PRESET & ~NSr5_5; - assign n1220_1 = (n1836 | ~N_N3340) & (PRESET | n1873); - assign n447 = ~n1220_1; - assign n1490 = N_N4073 & n957; - assign n1223 = (~N_N3336 | n1652) & (n1654 | n1862); - assign n1210_1 = ~n1223; - assign n1225_1 = (n1737 | ~N_N4180) & (n1712 | n1738); - assign n213_1 = ~n1225_1; - assign n1227 = ~PRESET & (n1955 | (~n1229 & N_N4214)); - assign n667 = n1227 & N_N3462; - assign n1229 = n1581 & ~N_N4060 & n1577 & n1579 & ~n1803 & n1872 & n1907 & n1956; - assign n622 = ~PRESET & n1229; - assign n1231 = (n1654 | n1827) & (n1652 | ~N_N3908); - assign n1066_1 = ~n1231; - assign n1233 = (n1654 | n1709) & (n1652 | ~N_N3884); - assign n1235_1 = ~n1233; - assign n1235 = (n1737 | ~N_N3323) & (n1716 | n1738); - assign n917 = ~n1235; - assign n1237 = n1586 | ~N_N3393; - assign n1285_1 = ~n1237; - assign n1239 = n1874 & (n1847 | ~N_N3932); - assign n457 = ~n1239; - assign n1241 = n1875 & (n1847 | ~N_N3876); - assign n422_1 = ~n1241; - assign n1390 = N_N4223 & n957; - assign n1244 = (n1713 | ~N_N3311) & (n1669 | n1714); - assign n218_1 = ~n1244; - assign n1150 = NDN1_4 & n532; - assign n392_1 = NDN3_11 & n1058; - assign n1248 = (n1586 | ~N_N3778) & (~Paport_3_3_ | n1587); - assign n1455 = ~n1248; - assign n1250 = n1876 & (n1577 | n1807); - assign n432_1 = ~n1250; - assign n1252 = n1877 & (n1573 | n1807); - assign n343_1 = ~n1252; - assign n1254 = (n1644 | n1878) & (~n1962 | ~N_N3274); - assign n872_1 = ~n1254; - assign n1256 = (n1644 | n1879) & (~n1962 | ~N_N3480); - assign n692 = ~n1256; - assign n1258 = (n1585 | ~N_N3940) & (PRESET | n1881); - assign n702_1 = ~n1258; - assign n1260_1 = (n1662 | n1739) & (n1661 | ~N_N3700); - assign n542_1 = ~n1260_1; - assign n1262 = n1586 | ~N_N3250; - assign n178_1 = ~n1262; - assign n1264 = n1586 | ~N_N3248; - assign n208_1 = ~n1264; - assign n1266 = (n1648 | n1743) & (n1647 | ~N_N3931); - assign n1076 = ~n1266; - assign n1268 = (n1644 | n1882) & (~n1962 | ~N_N3509); - assign n707 = ~n1268; - assign n1270_1 = (n1644 | n1883) & (~n1962 | ~N_N3529); - assign n732 = ~n1270_1; - assign n1272 = (n1829 | ~NDN5_10) & (NLD3_9 | n1884); - assign n397_1 = ~n1272; - assign n1274 = (n1585 | ~N_N3923) & (PRESET | n1886); - assign n173_1 = ~n1274; - assign n1276 = (n1808 | ~N_N4145) & (n1807 | n1887); - assign n283 = ~n1276; - assign n1278 = (n1648 | n1820) & (n1647 | ~N_N3464); - assign n193_1 = ~n1278; - assign n1280_1 = (n1648 | n1809) & (n1647 | ~N_N3442); - assign n223_1 = ~n1280_1; - assign n1282 = (n1648 | n1828) & (n1647 | ~N_N3214); - assign n1425 = ~n1282; - assign n1284 = (n1648 | n1854) & (n1647 | ~N_N3212); - assign n1465 = ~n1284; - assign n1286 = (n1711 | n1744) & (n1710 | ~N_N3304); - assign n1011 = ~n1286; - assign n1288 = (n1711 | n1715) & (n1710 | ~N_N3221); - assign n1051_1 = ~n1288; - assign n867_1 = N_N4072 & n957; - assign n1291 = (n1668 | n1742) & (n1667 | ~N_N3205); - assign n1190 = ~n1291; - assign n1293 = (n1668 | n1712) & (n1667 | ~N_N3203); - assign n1225 = ~n1293; - assign n1295 = n1888 & (n1847 | ~N_N3634); - assign n832_1 = ~n1295; - assign n1297 = (n1808 | ~N_N3996) & (n1807 | n1889); - assign n1121 = ~n1297; - assign n1299 = (n1586 | ~N_N4132) & (~Pdxport_7_7_ | n1587); - assign n1410 = ~n1299; - assign n1301 = (n1586 | ~N_N4070) & (~Pdxport_9_9_ | n1587); - assign n1430 = ~n1301; - assign n1303 = (n1586 | ~N_N4237) & (~Pdxport_11_11_ | n1587); - assign n837 = ~n1303; - assign n1305_1 = n1890 & (n1847 | ~N_N3517); - assign n1195_1 = ~n1305_1; - assign n1307 = n1891 & (n1847 | ~N_N3393); - assign n1170 = ~n1307; - assign n1309 = n1586 | ~N_N3932; - assign n527 = ~n1309; - assign n1311 = (n1648 | n1856) & (n1647 | ~N_N3179); - assign n1395 = ~n1311; - assign n1313 = (n1737 | ~N_N3293) & (n1666 | n1738); - assign n1026 = ~n1313; - assign n1315_1 = (n1738 | n1741) & (n1737 | ~N_N3175); - assign n158_1 = ~n1315_1; - assign n1317 = (n1710 | ~N_N3806) & (n1669 | n1711); - assign n348_1 = ~n1317; - assign n1319 = (n1710 | ~N_N3433) & (n1670 | n1711); - assign n981_1 = ~n1319; - assign n1321 = (n1836 | ~N_N3369) & (PRESET | n1893); - assign n1106 = ~n1321; - assign n1323 = (n1586 | ~N_N3797) & (~Paport_1_1_ | n1587); - assign n1420 = ~n1323; - assign n1325_1 = (n1668 | n1744) & (n1667 | ~N_N3626); - assign n377 = ~n1325_1; - assign n1445 = ~PRESET & ~NSr5_2; - assign n782 = N_N4134 & n957; - assign n941 = N_N3445 & n957; - assign n1330_1 = n1894 & (n1847 | ~N_N3280); - assign n772 = ~n1330_1; - assign n1332 = n1586 | ~N_N3196; - assign n427 = ~n1332; - assign n1334 = (n1836 | ~N_N4093) & (PRESET | n1896); - assign n1131 = ~n1334; - assign n1336 = (n1586 | ~N_N4165) & (~Pdxport_4_4_ | n1587); - assign n592 = ~n1336; - assign n1338 = (n1738 | n1744) & (n1737 | ~N_N3387); - assign n807_1 = ~n1338; - assign n1340_1 = (n1710 | ~N_N3164) & (n1666 | n1711); - assign n1111 = ~n1340_1; - assign n1342 = (n1714 | n1742) & (n1713 | ~N_N3143); - assign n128 = ~n1342; - assign n1344 = (n1665 | n1845) & (n1664 | ~N_N3840); - assign n517_1 = ~n1344; - assign n1346 = (n1665 | n1669) & (n1664 | ~N_N3805); - assign n537_1 = ~n1346; - assign n1348 = n1897 & (n1847 | ~N_N4159); - assign n1365 = ~n1348; - assign n1350_1 = n1898 & (n1847 | ~N_N3235); - assign n278_1 = ~n1350_1; - assign n1352 = (n1585 | ~N_N3872) & (PRESET | n1900); - assign n113_1 = ~n1352; - assign n617 = N_N3324 & n957; - assign n1355_1 = (n1654 | n1826) & (n1652 | ~N_N3862); - assign n1046 = ~n1355_1; - assign n1357 = n1586 | ~N_N3751; - assign n492 = ~n1357; - assign n1359 = (n1648 | n1883) & (n1647 | ~N_N3875); - assign n1056 = ~n1359; - assign n1361 = (n1808 | ~N_N3965) & (n1807 | n1901); - assign n382_1 = ~n1361; - assign n1363 = n1586 | ~N_N3105; - assign n238 = ~n1363; - assign n1365_1 = (n1737 | ~N_N3344) & (n1715 | n1738); - assign n862 = ~n1365_1; - assign n1367 = (n1710 | ~N_N3457) & (n1663 | n1711); - assign n936 = ~n1367; - assign n1369 = (n1665 | n1744) & (n1664 | ~N_N3303); - assign n1200_1 = ~n1369; - assign n1371 = n1902 & (n1579 | n1807); - assign n1160 = ~n1371; - assign n1373 = n1903 & (n1581 | n1807); - assign n1185_1 = ~n1373; - assign n1375_1 = (n1585 | ~N_N4177) & (PRESET | n1905); - assign n1330 = ~n1375_1; - assign n1377 = (n1654 | n1825) & (n1652 | ~N_N3832); - assign n1006_1 = ~n1377; - assign n88 = N_N3345 & n957; - assign n1380_1 = (n1665 | n1739) & (n1664 | ~N_N3188); - assign n1295_1 = ~n1380_1; - assign n1382 = (n1713 | ~N_N3071) & (n1712 | n1714); - assign n163_1 = ~n1382; - assign n1384 = (n1714 | n1845) & (n1713 | ~N_N3069); - assign n188_1 = ~n1384; - assign n412_1 = NDN5_16 & ~n1829; - assign n1387 = n1586 | ~N_N4159; - assign n627 = ~n1387; - assign n1389 = n1586 | ~N_N3331; - assign n1220 = ~n1389; - assign n1391 = (n1836 | ~N_N3283) & (PRESET | n1908); - assign n467 = ~n1391; - assign n1393 = (n1586 | ~N_N4242) & (~Pdxport_8_8_ | n1587); - assign n647 = ~n1393; - assign n1395_1 = (n1586 | ~N_N4194) & (~Pdxport_10_10_ | n1587); - assign n812_1 = ~n1395_1; - assign n1397 = (n1648 | n1815) & (n1647 | ~N_N3540); - assign n308_1 = ~n1397; - assign n1399 = (n1668 | n1716) & (n1667 | ~N_N3679); - assign n442 = ~n1399; - assign n1401 = (n1668 | n1739) & (n1667 | ~N_N3701); - assign n477 = ~n1401; - assign n1450 = ~PRESET & ~NSr5_3; - assign n1404 = (n1648 | n1882) & (n1647 | ~N_N3750); - assign n1016_1 = ~n1404; - assign n991_1 = N_N3468 & n957; - assign n1407 = n1816 & (PRESET | ~N_N3346); - assign n582 = ~n1407; - assign n1409 = n1909 & (n1847 | ~N_N3822); - assign n1270 = ~n1409; - assign n1411 = (n1668 | n1845) & (n1667 | ~N_N3100); - assign n1260 = ~n1411; - assign n1413 = (n1808 | ~N_N3974) & (n1807 | n1910); - assign n1091_1 = ~n1413; - assign n1475 = (NDN5_6 | ~n1514) & ~n1829; - assign n1416 = (n1662 | n1666) & (n1661 | ~N_N3735); - assign n547 = ~n1416; - assign n1418 = (n1648 | n1878) & (n1647 | ~N_N3821); - assign n817 = ~n1418; - assign n1420_1 = n1586 | ~N_N4080; - assign n597_1 = ~n1420_1; - assign n1422 = n1586 | ~N_N3062; - assign n263_1 = ~n1422; - assign n1424 = (n1648 | n1814) & (n1647 | ~N_N3680); - assign n892_1 = ~n1424; - assign n1426 = (n1648 | n1879) & (n1647 | ~N_N3715); - assign n956_1 = ~n1426; - assign n1428 = n1586 | ~N_N3822; - assign n767_1 = ~n1428; - assign n1430_1 = (n1586 | ~N_N3906) & (~Pdxport_0_0_ | n1587); - assign n562 = ~n1430_1; - assign n1432 = (n1648 | n1653) & (n1647 | ~N_N3677); - assign n587 = ~n1432; - assign n1434 = (n1738 | n1845) & (n1737 | ~N_N4133); - assign n243_1 = ~n1434; - assign n1081_1 = N_N3469 & n957; - assign n1437 = (n1648 | n1811) & (n1647 | ~N_N3516); - assign n293 = ~n1437; - assign n1439 = n1816 & (PRESET | ~N_N2989); - assign n717 = ~n1439; - assign n1441 = Pready_0_0_ & ~PDN & n1959 & ~NLak3_2; - assign n552 = ~PRESET & NSr3_2 & n1441; - assign n1443 = n1586 | ~N_N3262; - assign n902 = ~n1443; - assign n1445_1 = n1586 | ~N_N3280; - assign n966_1 = ~n1445_1; - assign n1447 = (n1808 | ~N_N4027) & (n1807 | n1911); - assign n1145 = ~n1447; - assign n1449 = n1586 | ~N_N3356; - assign n1126 = ~n1449; - assign n1451 = n1586 | ~N_N3384; - assign n1155 = ~n1451; - assign n1453 = (n1662 | n1712) & (n1661 | ~N_N3081); - assign n1320 = ~n1453; - assign n1455_1 = (n1714 | n1739) & (n1713 | ~N_N3630); - assign n857_1 = ~n1455_1; - assign n1457 = (n1713 | ~N_N3607) & (n1666 | n1714); - assign n912 = ~n1457; - assign n1459 = n1586 | ~N_N3235; - assign n462 = ~n1459; - assign n1461 = (n1648 | n1810) & (n1647 | ~N_N3420); - assign n253_1 = ~n1461; - assign n1463 = (n1714 | n1741) & (n1713 | ~N_N3157); - assign n108_1 = ~n1463; - assign n1465_1 = n1586 | ~N_N3011; - assign n577_1 = ~n1465_1; - assign n652 = N_N3312 & n957; - assign n672 = N_N3294 & n957; - assign n1469 = n1912 & (n1567 | n1807); - assign n1215 = ~n1469; - assign n1471 = (n1808 | ~N_N4083) & (n1807 | n1913); - assign n318_1 = ~n1471; - assign n1473 = n1586 | ~N_N3541; - assign n1325 = ~n1473; - assign n1475_1 = n1586 | ~N_N3866; - assign n787 = ~n1475_1; - assign n1415 = N_N4182 & n957; - assign n1435 = N_N4135 & n957; - assign n1479 = n1914 & (n1847 | ~N_N3262); - assign n747 = ~n1479; - assign n1481 = n1915 & (n1847 | ~N_N3417); - assign n722_1 = ~n1481; - assign n1483 = n1816 & (PRESET | ~N_N3388); - assign n567_1 = ~n1483; - assign n1485_1 = n1916 & (n1847 | ~N_N3786); - assign n203_1 = ~n1485_1; - assign n1487 = n532 & (~NSr3_2 | n1441); - assign n1530 = ~n1487; - assign n1489 = ~n1829 & ((~n1514 & NAK5_2) | ~NSr5_2); - assign n1535 = ~n1489; - assign n1491 = ~n1829 & (~NSr5_3 | (NAK5_2 & ~NSr5_2)); - assign n1540 = ~n1491; - assign n1493 = n946 & (~N_N3462 | n1229); - assign n1545 = ~n1493; - assign n1495_1 = n946 & ~n1556 & (~N_N3462 | n1229); - assign n1550 = ~n1495_1; - assign n1497 = ~n1829 & (~NSr5_4 | (NAK5_2 & ~NSr5_3)); - assign n1555 = ~n1497; - assign n1499 = n532 & (~NSr3_9 | (NDN3_8 & n1107)); - assign n1560 = ~n1499; - assign n1501 = ~n1829 & ((~NSr5_4 & NAK5_2) | ~NSr5_5); - assign n1565 = ~n1501; - assign n1503 = ~n1829 & (~NSr5_7 | (NAK5_2 & ~NSr5_5)); - assign n1570 = ~n1503; - assign n1505_1 = ~n1829 & (~NSr5_8 | (NAK5_2 & ~NSr5_7)); - assign n1575 = ~n1505_1; - assign n1507 = ~PRESET & ~n1993 & (n1833 | ~N_N3998); - assign n1580 = ~n1507; - assign n1509 = ~n1958 & n1959; - assign n1510_1 = ~NLD3_9 & n1583 & n1958; - assign n1511 = ~PRESET & (n1509 | n1510_1); - assign n1512 = n1559 & ~n1802; - assign n1513 = ~PRESET & (n1512 | ~n1970); - assign n1514 = NLak3_9 | ~NDN3_8 | ~NSr3_9; - assign n1515_1 = (n1514 | ~NSr5_2) & (NSr5_4 | ~NSr5_5); - assign n1516 = (n1528 | ~N_N3303) & (n1515_1 | ~N_N3906); - assign n1517 = (n1542 | ~N_N3940) & (n1538 | ~N_N3939); - assign n1518 = ~NSr5_7 | NSr5_5; - assign n1519 = n1516 & n1517 & (n1518 | ~N_N3304); - assign n1520_1 = (n1528 | ~N_N3188) & (n1515_1 | ~N_N4206); - assign n1521 = (n1542 | ~N_N3813) & (n1538 | ~N_N4239); - assign n1522 = n1520_1 & n1521 & (n1518 | ~N_N3436); - assign n1523 = (n1528 | ~N_N3424) & (n1515_1 | ~N_N4165); - assign n1524 = (n1542 | ~N_N3868) & (n1538 | ~N_N4099); - assign n1525_1 = n1523 & n1524 & (n1518 | ~N_N3711); - assign n1526 = (n1518 | ~N_N3221) & (n1515_1 | ~N_N4057); - assign n1527 = (n1542 | ~N_N3919) & (n1538 | ~N_N3918); - assign n1528 = NSr5_7 | ~NSr5_8; - assign n1529 = n1526 & n1527 & (n1528 | ~N_N3367); - assign n1530_1 = (n1528 | ~N_N4116) & (n1515_1 | ~N_N4120); - assign n1531 = (n1542 | ~N_N4119) & (n1538 | ~N_N4118); - assign n1532 = n1530_1 & n1531 & (n1518 | ~N_N4117); - assign n1533 = (n1528 | ~N_N3921) & (n1515_1 | ~N_N4220); - assign n1534 = (n1542 | ~N_N3924) & (n1538 | ~N_N3923); - assign n1535_1 = n1533 & n1534 & (n1518 | ~N_N3922); - assign n1536 = (n1528 | ~N_N3870) & (n1515_1 | ~N_N4179); - assign n1537 = (n1542 | ~N_N3872) & (n1518 | ~N_N4030); - assign n1538 = ~NSr5_4 | NSr5_3; - assign n1539 = n1536 & n1537 & (n1538 | ~N_N3871); - assign n1540_1 = (n1518 | ~N_N3164) & (n1515_1 | ~N_N4242); - assign n1541 = (n1538 | ~N_N4252) & (n1528 | ~N_N4047); - assign n1542 = ~NSr5_3 | NSr5_2; - assign n1543 = n1540_1 & n1541 & (n1542 | ~N_N3800); - assign n1544 = (n1528 | ~N_N3805) & (n1515_1 | ~N_N4070); - assign n1545_1 = (n1542 | ~N_N3808) & (n1538 | ~N_N3807); - assign n1546 = n1544 & n1545_1 & (n1518 | ~N_N3806); - assign n1547 = (n1528 | ~N_N3840) & (n1515_1 | ~N_N4132); - assign n1548 = (n1542 | ~N_N3843) & (n1538 | ~N_N3842); - assign n1549 = n1547 & n1548 & (n1518 | ~N_N3841); - assign n1550_1 = (n1518 | ~N_N3433) & (n1515_1 | ~N_N4237); - assign n1551 = (n1542 | ~N_N4209) & (n1538 | ~N_N4208); - assign n1552 = n1550_1 & n1551 & (n1528 | ~N_N3659); - assign n1553 = (n1518 | ~N_N3457) & (n1515_1 | ~N_N4194); - assign n1554 = (n1542 | ~N_N4177) & (n1538 | ~N_N4176); - assign n1555_1 = n1553 & n1554 & (n1528 | ~N_N4045); - assign n1556 = n1515_1 & n1528 & n1518 & n1542 & n1538; - assign n1557 = (~N_N3999 | N_N3838) & ~n1992; - assign n1558 = N_N3460 & (n1556 | n1557); - assign n1559 = N_N3578 | n1558; - assign n1560_1 = ~n1955 & (n1557 | n1559); - assign n1561 = (~n1513 & (~N_N4060 | n1807)) | (N_N4060 & n1807); - assign n1562 = PRESET | n1560_1; - assign n1525 = n1561 & (n1519 | n1562); - assign n1564 = N_N3369 | n1572; - assign n1565_1 = n1564 & (~n1572 | ~N_N3369); - assign n1566 = ~N_N4060 | N_N3961; - assign n1567 = n1566 & (N_N4060 | ~N_N3961); - assign n1568 = N_N4093 | n1570_1; - assign n1569 = n1568 & (~n1570_1 | ~N_N4093); - assign n1570_1 = N_N4212 | n1578; - assign n1571 = n1570_1 & (~n1578 | ~N_N4212); - assign n1572 = N_N4246 | n1568; - assign n1573 = n1572 & (~n1568 | ~N_N4246); - assign n1574 = N_N4171 | n1580_1; - assign n1575_1 = n1574 & (~n1580_1 | ~N_N4171); - assign n1576 = N_N4126 | n1566; - assign n1577 = n1576 & (~n1566 | ~N_N4126); - assign n1578 = N_N4036 | n1574; - assign n1579 = n1578 & (~n1574 | ~N_N4036); - assign n1580_1 = N_N4004 | n1576; - assign n1581 = n1580_1 & (~n1576 | ~N_N4004); - assign n1582 = (~n1509 | ~N_N4239) & (~NLD3_9 | ~N_N3774); - assign n1583 = NDN3_8 | ~NDN3_3; - assign n1584 = n1582 & (n1583 | ~N_N4090); - assign n1585 = PRESET | ~n1510_1; - assign n1586 = n1960 | PRESET; - assign n1587 = PRESET | ~n1960; - assign n1588 = NDN5_9 | ~NEN5_9; - assign n1589 = NDN5_10 | NSr5_7; - assign n1590 = (n1589 | ~N_N4039) & (n1588 | ~N_N3612); - assign n1591 = (n1589 | ~N_N3482) & (n1588 | ~N_N4075); - assign n1592 = (n1589 | ~N_N3736) & (n1588 | ~N_N3735); - assign n1593 = (n1589 | ~N_N3701) & (n1588 | ~N_N3700); - assign n1594 = (n1589 | ~N_N3679) & (n1588 | ~N_N4021); - assign n1595 = (n1589 | ~N_N3626) & (n1588 | ~N_N3625); - assign n1596 = (n1589 | ~N_N3799) & (n1588 | ~N_N4024); - assign n1597 = (n1589 | ~N_N3968) & (n1588 | ~N_N3959); - assign n1598 = (n1589 | ~N_N3205) & (n1588 | ~N_N3957); - assign n1599 = (n1589 | ~N_N3203) & (n1588 | ~N_N3081); - assign n1600 = (n1589 | ~N_N3100) & (n1588 | ~N_N3585); - assign n1601 = (n1589 | ~N_N4042) & (n1588 | ~N_N3824); - assign n1602 = (n1589 | ~N_N3470) & (n1588 | ~N_N3274); - assign n1603 = (n1589 | ~N_N3810) & (n1588 | ~N_N3947); - assign n1604 = n1627 & n1599 & n1593; - assign n1605 = n1604 & n1600; - assign n1606 = (n1589 | ~N_N4224) & (n1588 | ~N_N3829); - assign n1607 = (n1589 | ~N_N3971) & (n1588 | ~N_N3796); - assign n1608 = (n1589 | ~N_N3500) & (n1588 | ~N_N3684); - assign n1609 = ~n1595 & ~n1607 & (~n1608 | ~n1610); - assign n1610 = n1595 ^ ~n1597; - assign n1611 = ~n1609 & (n1608 | n1610); - assign n1612 = n1595 & n1597; - assign n1613 = (n1589 | ~N_N4086) & (n1588 | ~N_N3480); - assign n1614 = n1613 & ~n1924; - assign n1615 = (n1613 | ~n1924) & (n1611 | n1614); - assign n1616 = n1606 & n1615; - assign n1617 = (n1616 | ~n1925) & (n1606 | n1615); - assign n1618 = (n1589 | ~N_N3890) & (n1588 | ~N_N3509); - assign n1619 = n1595 & n1597 & n1596; - assign n1620 = n1619 & n1598; - assign n1621 = n1618 & ~n1926; - assign n1622 = (n1618 | ~n1926) & (n1617 | n1621); - assign n1623 = (n1589 | ~N_N4183) & (n1588 | ~N_N3826); - assign n1624 = n1623 & ~n1927; - assign n1625 = (n1623 | ~n1927) & (n1622 | n1624); - assign n1626 = (n1589 | ~N_N3844) & (n1588 | ~N_N3529); - assign n1627 = n1619 & n1598 & n1594; - assign n1628 = n1627 & n1599; - assign n1629 = n1626 & ~n1928; - assign n1630 = (n1626 | ~n1928) & (n1625 | n1629); - assign n1631 = (n1589 | ~N_N4136) & (n1588 | ~N_N3815); - assign n1632 = n1631 & ~n1929; - assign n1633 = (n1631 | ~n1929) & (n1630 | n1632); - assign n1634 = n1592 ^ ~n1605; - assign n1635 = n1633 & n1634; - assign n1636 = (n1603 | n1635) & (n1633 | n1634); - assign n1637 = (n1589 | ~N_N4140) & (n1588 | ~N_N3788); - assign n1638 = n1636 & n1637; - assign n1639 = (n1638 | ~n1931) & (n1636 | n1637); - assign n1640 = n1602 & n1639; - assign n1641 = n1591 ^ ~n1963; - assign n1642 = (n1640 | n1641) & (n1602 | n1639); - assign n1643 = (n1589 | ~N_N4095) & (n1588 | ~N_N4167); - assign n1644 = PRESET | n1589; - assign n1645 = (~n1509 | ~N_N4140) & (~NLD3_9 | ~N_N3540); - assign n1646 = n1645 & (n1583 | ~N_N3541); - assign n1647 = PRESET | ~n1588; - assign n1648 = PRESET | n1588; - assign n1649 = NDN5_6 | n1514; - assign n1650 = (n1649 | ~N_N3906) & (n1588 | ~N_N3910); - assign n1651 = (n1649 | ~N_N3940) & (n1588 | ~N_N3939); - assign n1652 = PRESET | ~n1649; - assign n1653 = n1650 ^ ~n1651; - assign n1654 = PRESET | n1649; - assign n1655 = (n1583 | ~N_N3384) & (~n1509 | ~N_N4099); - assign n1656 = n1655 & (~NLD3_9 | ~N_N3743); - assign n1657 = (n1583 | ~N_N3866) & (~n1509 | ~N_N4095); - assign n1658 = n1657 & (~NLD3_9 | ~N_N4114); - assign n1659 = (~n1509 | ~N_N4086) & (~NLD3_9 | ~N_N3715); - assign n1660 = n1659 & (n1583 | ~N_N3716); - assign n1661 = PRESET | ~n1964; - assign n1662 = PRESET | n1964; - assign n1663 = ~n1557 | ~N_N4197; - assign n1664 = PRESET | ~n1965; - assign n1665 = PRESET | n1965; - assign n1666 = ~n1557 | ~N_N4145; - assign n1667 = PRESET | ~n1966; - assign n1668 = PRESET | n1966; - assign n1669 = ~n1557 | ~N_N3912; - assign n1670 = ~n1557 | ~N_N4227; - assign n1671 = (n1649 | ~N_N4194) & (n1588 | ~N_N4193); - assign n1672 = (n1649 | ~N_N4177) & (n1588 | ~N_N4176); - assign n1673 = (n1649 | ~N_N3800) & (n1588 | ~N_N4252); - assign n1674 = (n1649 | ~N_N4242) & (n1588 | ~N_N3607); - assign n1675 = (n1649 | ~N_N4220) & (n1588 | ~N_N3143); - assign n1676 = (n1649 | ~N_N3924) & (n1588 | ~N_N3923); - assign n1677 = (n1649 | ~N_N3919) & (n1588 | ~N_N3918); - assign n1678 = (n1649 | ~N_N4057) & (n1588 | ~N_N3793); - assign n1679 = (n1649 | ~N_N4119) & (n1588 | ~N_N4118); - assign n1680 = (n1649 | ~N_N4120) & (n1588 | ~N_N3157); - assign n1681 = ~n1650 & ~n1651 & (~n1679 | ~n1680); - assign n1682 = ~n1681 & (n1679 | n1680); - assign n1683 = n1678 & n1682; - assign n1684 = (n1677 | n1683) & (n1678 | n1682); - assign n1685 = n1676 & n1684; - assign n1686 = (n1675 | n1685) & (n1676 | n1684); - assign n1687 = (n1649 | ~N_N3868) & (n1588 | ~N_N4099); - assign n1688 = (n1649 | ~N_N4165) & (n1588 | ~N_N3776); - assign n1689 = n1687 & n1688; - assign n1690 = (n1686 | n1689) & (n1687 | n1688); - assign n1691 = (n1649 | ~N_N3872) & (n1588 | ~N_N3871); - assign n1692 = (n1649 | ~N_N4179) & (n1588 | ~N_N3071); - assign n1693 = n1691 & n1692; - assign n1694 = (n1690 | n1693) & (n1691 | n1692); - assign n1695 = (n1649 | ~N_N3813) & (n1588 | ~N_N4239); - assign n1696 = (n1649 | ~N_N4206) & (n1588 | ~N_N3630); - assign n1697 = n1695 & n1696; - assign n1698 = (n1694 | n1697) & (n1695 | n1696); - assign n1699 = (n1649 | ~N_N3843) & (n1588 | ~N_N3842); - assign n1700 = (n1649 | ~N_N4132) & (n1588 | ~N_N3069); - assign n1701 = n1699 & n1700; - assign n1702 = (n1698 | n1701) & (n1699 | n1700); - assign n1703 = n1674 & n1702; - assign n1704 = (n1673 | n1703) & (n1674 | n1702); - assign n1705 = (n1649 | ~N_N3808) & (n1588 | ~N_N3807); - assign n1706 = (n1649 | ~N_N4070) & (n1588 | ~N_N3311); - assign n1707 = n1705 & n1706; - assign n1708 = (n1704 | n1707) & (n1705 | n1706); - assign n1709 = n1708 ^ n1981; - assign n1710 = PRESET | ~n1967; - assign n1711 = PRESET | n1967; - assign n1712 = ~n1557 | ~N_N3974; - assign n1713 = PRESET | ~n1968; - assign n1714 = PRESET | n1968; - assign n1715 = ~n1557 | ~N_N3992; - assign n1716 = ~n1557 | ~N_N4018; - assign n1717 = N_N3916 & ~N_N4111 & (N_N3797 | ~N_N3535); - assign n1718 = ~n1717 & (~N_N3797 | N_N3535); - assign n1719 = n1718 & ~N_N3733; - assign n1720 = (n1719 | N_N3794) & (n1718 | ~N_N3733); - assign n1721 = n1720 & ~N_N3778; - assign n1722 = (n1721 | N_N3981) & (n1720 | ~N_N3778); - assign n1723 = ~n1722 & N_N3574; - assign n1724 = (~n1722 | N_N3574) & (n1723 | ~N_N3832); - assign n1725 = n1724 & ~N_N3761; - assign n1726 = (n1725 | N_N4056) & (n1724 | ~N_N3761); - assign n1727 = ~n1726 & N_N3862; - assign n1728 = (~n1726 | N_N3862) & (n1727 | ~N_N4243); - assign n1729 = n1728 & N_N3489; - assign n1730 = (n1729 | ~N_N4054) & (n1728 | N_N3489); - assign n1731 = ~n1730 & ~N_N3908; - assign n1732 = (n1731 | N_N4015) & (~n1730 | ~N_N3908); - assign n1733 = n1732 & ~N_N3513; - assign n1734 = (n1733 | N_N3818) & (n1732 | ~N_N3513); - assign n1735 = N_N3884 & (~n1734 | ~N_N3882); - assign n1736 = ~n1734 & ~N_N3882; - assign n1737 = PRESET | ~n1969; - assign n1738 = PRESET | n1969; - assign n1739 = ~n1557 | ~N_N4083; - assign n1740 = n1684 ^ n1982; - assign n1741 = ~n1557 | ~N_N4027; - assign n1742 = ~n1557 | ~N_N3996; - assign n1743 = n1634 ^ n1935; - assign n1744 = ~n1557 | ~N_N3965; - assign n1745 = (n1515_1 | ~N_N4095) & (~N_N3445 | n1538); - assign n1746 = (n1528 | ~N_N4237) & (~N_N3905 | n1542); - assign n1747 = n1745 & n1746 & (n1518 | ~N_N3663); - assign n1748 = (n1515_1 | ~N_N3470) & (~N_N3468 | n1538); - assign n1749 = (n1528 | ~N_N4194) & (n1518 | ~N_N3473); - assign n1750 = n1748 & (~N_N3469 | n1542) & n1749; - assign n1751 = (n1528 | ~N_N4070) & (n1515_1 | ~N_N4140); - assign n1752 = (~N_N4072 | n1538) & (~N_N4073 | n1542); - assign n1753 = n1751 & n1752 & (n1518 | ~N_N4071); - assign n1754 = (n1518 | ~N_N3293) & (n1515_1 | ~N_N3810); - assign n1755 = (n1528 | ~N_N4242) & (~N_N3426 | n1538); - assign n1756 = n1754 & (~N_N3294 | n1542) & n1755; - assign n1757 = (n1528 | ~N_N4132) & (n1515_1 | ~N_N4136); - assign n1758 = (~N_N4134 | n1538) & (~N_N4135 | n1542); - assign n1759 = n1757 & n1758 & (n1518 | ~N_N4133); - assign n1760 = (n1515_1 | ~N_N3844) & (~N_N3312 | n1542); - assign n1761 = (n1528 | ~N_N4206) & (n1518 | ~N_N3988); - assign n1762 = n1760 & (~N_N3375 | n1538) & n1761; - assign n1763 = (n1528 | ~N_N4179) & (n1515_1 | ~N_N4183); - assign n1764 = (~N_N4181 | n1538) & (~N_N4182 | n1542); - assign n1765 = n1763 & n1764 & (n1518 | ~N_N4180); - assign n1766 = (n1518 | ~N_N3323) & (n1515_1 | ~N_N3890); - assign n1767 = (n1528 | ~N_N4165) & (~N_N3691 | n1538); - assign n1768 = n1766 & (~N_N3324 | n1542) & n1767; - assign n1769 = (n1528 | ~N_N4220) & (n1515_1 | ~N_N4224); - assign n1770 = (~N_N4222 | n1538) & (~N_N4223 | n1542); - assign n1771 = n1769 & n1770 & (n1518 | ~N_N4221); - assign n1772 = (n1518 | ~N_N3344) & (n1515_1 | ~N_N4086); - assign n1773 = (n1542 | ~N_N3346) & (n1528 | ~N_N4057); - assign n1774 = n1772 & (~N_N3345 | n1538) & n1773; - assign n1775 = (n1538 | ~N_N2989) & (n1515_1 | ~N_N3500); - assign n1776 = (n1528 | ~N_N4120) & (~N_N3708 | n1542); - assign n1777 = n1775 & n1776 & (n1518 | ~N_N3175); - assign n1778 = (n1518 | ~N_N3387) & (n1515_1 | ~N_N3971); - assign n1779 = (n1538 | ~N_N3745) & (n1528 | ~N_N3906); - assign n1780 = n1778 & n1779 & (n1542 | ~N_N3388); - assign n1781 = n1780 | ~N_N3965; - assign n1782 = n1777 & n1781; - assign n1783 = (n1782 | ~N_N4027) & (n1777 | n1781); - assign n1784 = n1783 & ~N_N3992; - assign n1785 = (n1783 | ~N_N3992) & (n1774 | n1784); - assign n1786 = n1785 & ~N_N3996; - assign n1787 = (n1785 | ~N_N3996) & (n1771 | n1786); - assign n1788 = n1787 & ~N_N4018; - assign n1789 = (n1787 | ~N_N4018) & (n1768 | n1788); - assign n1790 = n1789 & ~N_N3974; - assign n1791 = (n1789 | ~N_N3974) & (n1765 | n1790); - assign n1792 = n1791 & ~N_N4083; - assign n1793 = (n1791 | ~N_N4083) & (n1762 | n1792); - assign n1794 = n1793 & ~N_N3949; - assign n1795 = (n1793 | ~N_N3949) & (n1759 | n1794); - assign n1796 = n1795 & ~N_N4145; - assign n1797 = (n1795 | ~N_N4145) & (n1756 | n1796); - assign n1798 = n1797 & ~N_N3912; - assign n1799 = (n1797 | ~N_N3912) & (n1753 | n1798); - assign n1800 = n1799 & ~N_N4197; - assign n1801 = (n1799 | ~N_N4197) & (n1750 | n1800); - assign n1802 = ~n1803 | n1955; - assign n1803 = ~N_N3462 | N_N3575 | ~N_N4214; - assign n1804 = n1801 ^ n1747; - assign n1805 = n1802 & (n1803 | n1804); - assign n1806 = n1799 ^ n1936; - assign n1807 = PRESET | n1803; - assign n1808 = PRESET | n1802; - assign n1809 = n1925 ^ ~n1937; - assign n1810 = n1927 ^ ~n1938; - assign n1811 = n1929 ^ ~n1939; - assign n1812 = (~n1509 | ~N_N3971) & (~NLD3_9 | ~N_N3680); - assign n1813 = n1812 & (n1583 | ~N_N3681); - assign n1814 = n1595 ^ ~n1607; - assign n1815 = n1931 ^ ~n1940; - assign n1816 = PRESET | n1961; - assign n1817 = n1783 ^ n1941; - assign n1818 = n1787 ^ n1942; - assign n1819 = n1706 ^ n1983; - assign n1820 = n1610 ^ n1984; - assign n1821 = (n1583 | ~N_N3533) & (~n1509 | ~N_N4252); - assign n1822 = n1821 & (~NLD3_9 | ~N_N3791); - assign n1823 = (n1583 | ~N_N3105) & (~n1509 | ~N_N3843); - assign n1824 = n1823 & (~NLD3_9 | ~N_N3489); - assign n1825 = n1688 ^ n1985; - assign n1826 = n1696 ^ n1986; - assign n1827 = n1702 ^ n1987; - assign n1828 = n1692 ^ n1988; - assign n1829 = PRESET | NLD3_9; - assign n1830 = NSr5_8 | PRESET; - assign n1831 = n1682 ^ n1989; - assign n1832 = n1793 ^ n1943; - assign n1833 = ~PDN & ~NLC1_2; - assign n1834 = (n1522 | n1560_1) & (~N_N4212 | n1970); - assign n1835 = n1834 & (n1571 | n1803); - assign n1836 = PRESET | ~n1512; - assign n1837 = (n1525_1 | n1560_1) & (~N_N4171 | n1970); - assign n1838 = n1837 & (n1575_1 | n1803); - assign n1839 = (n1583 | ~N_N3356) & (~n1509 | ~N_N3918); - assign n1840 = n1839 & (~NLD3_9 | ~N_N3709); - assign n1841 = (~n1509 | ~N_N3939) & (~NLD3_9 | ~N_N3677); - assign n1842 = n1841 & (n1583 | ~N_N3741); - assign n1843 = (~n1509 | ~N_N4224) & (~NLD3_9 | ~N_N3442); - assign n1844 = n1843 & (n1583 | ~N_N4106); - assign n1845 = ~n1557 | ~N_N3949; - assign n1846 = (n1971 | ~N_N3750) & (~n1511 | ~N_N3890); - assign n1847 = PRESET | n1583; - assign n1848 = (~n1509 | ~N_N4118) & (~NLD3_9 | ~N_N3179); - assign n1849 = n1848 & (n1583 | ~N_N4232); - assign n1850 = (~NLD3_9 | ~N_N3336) & (~n1509 | ~N_N4209); - assign n1851 = n1850 & (n1583 | ~N_N3373); - assign n1852 = (n1583 | ~N_N3331) & (~n1509 | ~N_N3500); - assign n1853 = n1852 & (~NLD3_9 | ~N_N3464); - assign n1854 = n1700 ^ n1990; - assign n1855 = (~n1511 | ~N_N4176) & (~N_N4079 | n1971); - assign n1856 = n1944 ^ n1945; - assign n1857 = n1797 ^ n1946; - assign n1858 = (n1649 | ~N_N4237) & (n1588 | ~N_N4236); - assign n1859 = (n1649 | ~N_N4209) & (n1588 | ~N_N4208); - assign n1860 = n1708 & n1672; - assign n1861 = (n1671 | n1860) & (n1672 | n1708); - assign n1862 = n1861 ^ n1991; - assign n1863 = (n1583 | ~N_N3196) & (~n1509 | ~N_N3842); - assign n1864 = n1863 & (~NLD3_9 | ~N_N3212); - assign n1865 = (n1583 | ~N_N3250) & (~n1509 | ~N_N3924); - assign n1866 = n1865 & (~NLD3_9 | ~N_N3981); - assign n1867 = (~NLD3_9 | ~N_N3535) & (~n1509 | ~N_N4119); - assign n1868 = n1867 & (n1583 | ~N_N3580); - assign n1869 = (n1583 | ~N_N3062) & (~n1509 | ~N_N3808); - assign n1870 = n1869 & (~NLD3_9 | ~N_N3513); - assign n1871 = (n1552 | n1560_1) & (~N_N3340 | n1970); - assign n1872 = N_N3340 ^ n1923; - assign n1873 = n1871 & (n1872 | n1803); - assign n1874 = (~n1511 | ~N_N3810) & (~N_N3931 | n1971); - assign n1875 = (~n1511 | ~N_N3844) & (~N_N3875 | n1971); - assign n1876 = (n1529 | n1562) & (~n1513 | ~N_N4126); - assign n1877 = (n1543 | n1562) & (~n1513 | ~N_N4246); - assign n1878 = n1641 ^ n1947; - assign n1879 = n1924 ^ ~n1948; - assign n1880 = (~n1509 | ~N_N3940) & (~NLD3_9 | ~N_N4111); - assign n1881 = n1880 & (n1583 | ~N_N4218); - assign n1882 = n1926 ^ ~n1949; - assign n1883 = n1928 ^ ~n1950; - assign n1884 = NSr5_7 | PRESET; - assign n1885 = (~n1509 | ~N_N3923) & (~NLD3_9 | ~N_N3475); - assign n1886 = n1885 & (n1583 | ~N_N4230); - assign n1887 = n1795 ^ n1951; - assign n1888 = (~n1511 | ~N_N3800) & (~N_N3908 | n1971); - assign n1889 = n1785 ^ n1952; - assign n1890 = (n1971 | ~N_N3516) & (~n1511 | ~N_N4136); - assign n1891 = (n1971 | ~N_N3420) & (~n1511 | ~N_N4183); - assign n1892 = (n1546 | n1560_1) & (~N_N3369 | n1970); - assign n1893 = n1892 & (n1565_1 | n1803); - assign n1894 = (~N_N3862 | n1971) & (~n1511 | ~N_N3813); - assign n1895 = (n1549 | n1560_1) & (~N_N4093 | n1970); - assign n1896 = n1895 & (n1569 | n1803); - assign n1897 = (~n1511 | ~N_N4208) & (~N_N4158 | n1971); - assign n1898 = (~n1511 | ~N_N3807) & (~N_N3713 | n1971); - assign n1899 = (n1583 | ~N_N3248) & (~n1509 | ~N_N3872); - assign n1900 = n1899 & (~NLD3_9 | ~N_N3761); - assign n1901 = N_N3965 ^ n1780; - assign n1902 = (n1539 | n1562) & (~n1513 | ~N_N4036); - assign n1903 = (n1535_1 | n1562) & (~n1513 | ~N_N4004); - assign n1904 = (n1583 | ~N_N3011) & (~n1509 | ~N_N4177); - assign n1905 = n1904 & (~NLD3_9 | ~N_N3884); - assign n1906 = (n1555_1 | n1560_1) & (~N_N3283 | n1970); - assign n1907 = N_N3283 ^ n1564; - assign n1908 = n1906 & (n1907 | n1803); - assign n1909 = (~n1511 | ~N_N3470) & (~N_N3821 | n1971); - assign n1910 = n1789 ^ n1953; - assign n1911 = n1777 ^ n1972; - assign n1912 = (n1532 | n1562) & (~n1513 | ~N_N3961); - assign n1913 = n1791 ^ n1954; - assign n1914 = (~n1511 | ~N_N3868) & (~N_N3832 | n1971); - assign n1915 = (~N_N3794 | n1971) & (~n1511 | ~N_N3919); - assign n1916 = (~n1511 | ~N_N3871) & (~N_N3214 | n1971); - assign n1175 = n1058 & ~NSr3_9; - assign n1918 = ~PRESET & Pover_0_0_ & (~NGFDN_3 | NDN3_11); - assign n1136 = n1175 | n1918; - assign n1920 = ~PRESET & Pnext_0_0_ & (~NLD3_9 | NDN5_16); - assign n1440 = ~PRESET & n1957; - assign n373 = n1920 | n1440; - assign n1923 = N_N3283 | n1564; - assign n1924 = n1612 ^ n1596; - assign n1925 = n1619 ^ n1598; - assign n1926 = n1620 ^ n1594; - assign n1927 = n1627 ^ n1599; - assign n1928 = n1628 ^ n1593; - assign n1929 = n1604 ^ n1600; - assign n1930 = n1604 & n1600 & n1592; - assign n1931 = n1930 ^ n1601; - assign n1932 = n1642 ^ n1643; - assign n1933 = n1590 ^ n1979; - assign n1934 = n1932 ^ n1933; - assign n1935 = n1633 ^ n1603; - assign n1936 = n1750 ^ ~N_N4197; - assign n1937 = n1615 ^ n1606; - assign n1938 = n1622 ^ n1623; - assign n1939 = n1630 ^ n1631; - assign n1940 = n1636 ^ n1637; - assign n1941 = n1774 ^ ~N_N3992; - assign n1942 = n1768 ^ ~N_N4018; - assign n1943 = n1759 ^ ~N_N3949; - assign n1944 = n1679 ^ n1680; - assign n1945 = n1651 | n1650; - assign n1946 = n1753 ^ ~N_N3912; - assign n1947 = n1639 ^ n1602; - assign n1948 = n1611 ^ n1613; - assign n1949 = n1617 ^ n1618; - assign n1950 = n1625 ^ n1626; - assign n1951 = n1756 ^ ~N_N4145; - assign n1952 = n1771 ^ ~N_N3996; - assign n1953 = n1765 ^ ~N_N3974; - assign n1954 = n1762 ^ ~N_N4083; - assign n1955 = n947 & ~N_N4214; - assign n1956 = n1571 & n1573 & n1575_1 & n1565_1 & n1569 & n1567; - assign n1957 = ~NLD3_9 & NDN5_9; - assign n1958 = ~PDN | NDN1_4; - assign n1959 = (~Preset_0_0_ & (~NLC1_2 | N_N3998)) | (NLC1_2 & N_N3998); - assign n1960 = ~NDN3_3 & ~NSr3_2; - assign n1961 = NDN2_2 | n1169; - assign n1962 = ~PRESET & n1589; - assign n1963 = n1601 & n1930; - assign n1964 = NSr5_8 | NDN5_8; - assign n1965 = NSr5_4 | NDN5_4; - assign n1966 = NSr5_7 | NDN5_7; - assign n1967 = NSr5_3 | NDN5_3; - assign n1968 = NSr5_5 | NDN5_5; - assign n1969 = NSr5_2 | NDN5_2; - assign n1970 = ~n1557 | n1559; - assign n1971 = PRESET | ~NLD3_9; - assign n1972 = n1781 ^ ~N_N4027; - assign n1973 = n1976 & (PRESET | n1805 | ~N_N4227); - assign n273 = ~n1973; - assign n1975 = n1532 & n1535_1 & n1539 & n1522 & n1529 & n1525_1; - assign n1976 = ~n1804 | n1807 | N_N4227; - assign n1480 = ~n1884; - assign n1485 = ~n1830; - assign n1979 = n1963 & n1591; - assign n1980 = n1595 | n1607; - assign n1981 = n1671 ^ n1672; - assign n1982 = n1675 ^ n1676; - assign n1983 = n1704 ^ n1705; - assign n1984 = n1608 ^ n1980; - assign n1985 = n1686 ^ n1687; - assign n1986 = n1694 ^ n1695; - assign n1987 = n1673 ^ n1674; - assign n1988 = n1690 ^ n1691; - assign n1989 = n1677 ^ n1678; - assign n1990 = n1698 ^ n1699; - assign n1991 = n1858 ^ n1859; - assign n1992 = n1975 & n1555_1 & n1552 & n1546 & ~N_N3999 & n1519 & n1543 & n1549; - assign n1993 = ~Preset_0_0_ & n1833; - always @ (posedge clock) begin - N_N4054 <= n63_1; - N_N3745 <= n68_1; - N_N4119 <= n73_1; - N_N3826 <= n78_1; - N_N3818 <= n83_1; - N_N3345 <= n88; - N_N3924 <= n93_1; - N_N3815 <= n98_1; - N_N3691 <= n103; - N_N3157 <= n108_1; - N_N3872 <= n113_1; - N_N3788 <= n118_1; - N_N3375 <= n123_1; - N_N3143 <= n128; - N_N4197 <= n133; - N_N3843 <= n138_1; - N_N3426 <= n143_1; - N_N4118 <= n148_1; - N_N3580 <= n153_1; - N_N3175 <= n158_1; - N_N3071 <= n163_1; - N_N3808 <= n168_1; - N_N3923 <= n173_1; - N_N3250 <= n178_1; - N_N4221 <= n183_1; - N_N3069 <= n188_1; - N_N3464 <= n193_1; - N_N3535 <= n198_1; - N_N3871 <= n203_1; - N_N3248 <= n208_1; - N_N4180 <= n213_1; - N_N3311 <= n218_1; - N_N3442 <= n223_1; - N_N3981 <= n228_1; - N_N3842 <= n233; - N_N3105 <= n238; - N_N4133 <= n243_1; - N_N4117 <= n248_1; - N_N3420 <= n253_1; - N_N3761 <= n258_1; - N_N3062 <= n263_1; - N_N4071 <= n268; - N_N4227 <= n273; - N_N3807 <= n278_1; - N_N4145 <= n283; - N_N3922 <= n288_1; - N_N3516 <= n293; - N_N3489 <= n298; - N_N4030 <= n303_1; - N_N3540 <= n308_1; - N_N3513 <= n313_1; - N_N4083 <= n318_1; - N_N3841 <= n323_1; - N_N4018 <= n328_1; - N_N3971 <= n333_1; - N_N4232 <= n338_1; - N_N4246 <= n343_1; - N_N3806 <= n348_1; - N_N3992 <= n353_1; - N_N4086 <= n358_1; - N_N4230 <= n363_1; - N_N4212 <= n368; - Pnext_0_0_ <= n373; - N_N3626 <= n377; - N_N3965 <= n382_1; - N_N3890 <= n387_1; - NDN3_11 <= n392_1; - NDN5_10 <= n397_1; - N_N3786 <= n402_1; - N_N4171 <= n407; - NDN5_16 <= n412_1; - N_N3799 <= n417_1; - N_N3844 <= n422_1; - N_N3196 <= n427; - N_N4126 <= n432_1; - N_N3681 <= n437_1; - N_N3679 <= n442; - N_N3340 <= n447; - N_N4116 <= n452_1; - N_N3810 <= n457; - N_N3235 <= n462; - N_N3283 <= n467; - N_N3716 <= n472; - N_N3701 <= n477; - N_N3921 <= n482; - N_N3625 <= n487_1; - N_N3751 <= n492; - N_N3736 <= n497; - N_N3870 <= n502_1; - N_N4024 <= n507; - N_N3876 <= n512; - N_N3840 <= n517_1; - N_N4021 <= n522_1; - N_N3932 <= n527; - NLC1_2 <= n532; - N_N3805 <= n537_1; - N_N3700 <= n542_1; - N_N3735 <= n547; - NLak3_2 <= n552; - NLak3_9 <= n557_1; - N_N3906 <= n562; - N_N3388 <= n567_1; - N_N4057 <= n572; - N_N3011 <= n577_1; - N_N3346 <= n582; - N_N3677 <= n587; - N_N4165 <= n592; - N_N4080 <= n597_1; - N_N3373 <= n602_1; - N_N3709 <= n607_1; - N_N4206 <= n612; - N_N3324 <= n617; - N_N3575 <= n622; - N_N4159 <= n627; - NAK5_2 <= n632; - N_N3916 <= n637_1; - N_N3743 <= n642_1; - N_N4242 <= n647; - N_N3312 <= n652; - N_N3733 <= n657; - N_N3774 <= n662_1; - N_N4214 <= n667; - N_N3294 <= n672; - N_N3796 <= n677; - N_N3574 <= n682_1; - N_N3791 <= n687_1; - N_N3480 <= n692; - N_N4243 <= n697; - N_N3940 <= n702_1; - N_N3509 <= n707; - N_N4015 <= n712_1; - N_N2989 <= n717; - N_N3919 <= n722_1; - N_N3578 <= n727_1; - N_N3529 <= n732; - N_N4222 <= n737; - N_N3910 <= n742_1; - N_N3868 <= n747; - N_N3947 <= n752_1; - N_N4181 <= n757; - N_N3793 <= n762; - N_N3822 <= n767_1; - N_N3813 <= n772; - N_N4114 <= n777; - N_N4134 <= n782; - N_N3866 <= n787; - N_N4218 <= n792; - N_N3939 <= n797; - N_N3776 <= n802_1; - N_N3387 <= n807_1; - N_N4194 <= n812_1; - N_N3821 <= n817; - N_N3882 <= n822_1; - N_N4167 <= n827_1; - N_N3800 <= n832_1; - N_N4237 <= n837; - N_N3417 <= n842_1; - N_N3918 <= n847_1; - N_N4158 <= n852_1; - N_N3630 <= n857_1; - N_N3344 <= n862; - N_N4072 <= n867_1; - N_N3274 <= n872_1; - N_N3473 <= n877; - N_N4205 <= n882_1; - N_N4111 <= n887_1; - N_N3680 <= n892_1; - N_N3838 <= n897_1; - N_N3262 <= n902; - N_N4099 <= n907; - N_N3607 <= n912; - N_N3323 <= n917; - N_N3612 <= n922; - N_N4079 <= n927_1; - PDN <= n932_1; - N_N3457 <= n936; - N_N3445 <= n941; - N_N3794 <= n946_1; - N_N3663 <= n951_1; - N_N3715 <= n956_1; - N_N4039 <= n961_1; - N_N3280 <= n966_1; - N_N4239 <= n971_1; - N_N3988 <= n976; - N_N3433 <= n981_1; - N_N4075 <= n986; - N_N3468 <= n991_1; - N_N4045 <= n996; - N_N3482 <= n1001_1; - N_N3832 <= n1006_1; - N_N3304 <= n1011; - N_N3750 <= n1016_1; - N_N3634 <= n1021; - N_N3293 <= n1026; - N_N3659 <= n1031_1; - N_N4252 <= n1036; - N_N3912 <= n1041_1; - N_N3862 <= n1046; - N_N3221 <= n1051_1; - N_N3875 <= n1056; - N_N3949 <= n1061_1; - N_N3908 <= n1066_1; - N_N3711 <= n1071; - N_N3931 <= n1076; - N_N3469 <= n1081_1; - N_N3436 <= n1086_1; - N_N3974 <= n1091_1; - N_N3905 <= n1096; - N_N3741 <= n1101; - N_N3369 <= n1106; - N_N3164 <= n1111; - N_N3500 <= n1116_1; - N_N3996 <= n1121; - N_N3356 <= n1126; - N_N4093 <= n1131; - Pover_0_0_ <= n1136; - N_N4224 <= n1140; - N_N4027 <= n1145; - NDN1_4 <= n1150; - N_N3384 <= n1155; - N_N4036 <= n1160; - N_N3968 <= n1165; - N_N4183 <= n1170; - NGFDN_3 <= n1175; - N_N4090 <= n1180_1; - N_N4004 <= n1185_1; - N_N3205 <= n1190; - N_N4136 <= n1195_1; - N_N3303 <= n1200_1; - N_N3533 <= n1205_1; - N_N3336 <= n1210_1; - N_N3961 <= n1215; - N_N3331 <= n1220; - N_N3203 <= n1225; - N_N4236 <= n1230_1; - N_N3884 <= n1235_1; - N_N3367 <= n1240; - N_N4140 <= n1245_1; - NDN2_2 <= n1250_1; - N_N4106 <= n1255; - N_N3100 <= n1260; - N_N4193 <= n1265; - N_N3470 <= n1270; - N_N3424 <= n1275_1; - N_N3959 <= n1280; - N_N3393 <= n1285_1; - N_N4042 <= n1290_1; - N_N3188 <= n1295_1; - N_N4095 <= n1300; - N_N3957 <= n1305; - N_N3517 <= n1310; - N_N4047 <= n1315; - N_N3081 <= n1320; - N_N3541 <= n1325; - N_N4177 <= n1330; - NDN3_3 <= n1335; - N_N4176 <= n1340; - N_N3585 <= n1345; - NDN3_8 <= n1350; - N_N4209 <= n1355; - N_N3824 <= n1360; - N_N4208 <= n1365; - N_N4120 <= n1370; - N_N3708 <= n1375; - N_N4220 <= n1380; - N_N3999 <= n1385; - N_N4223 <= n1390; - N_N3179 <= n1395; - N_N4179 <= n1400; - N_N3475 <= n1405; - N_N4132 <= n1410; - N_N4182 <= n1415; - N_N3797 <= n1420; - N_N3214 <= n1425; - N_N4070 <= n1430; - N_N4135 <= n1435; - NLD3_9 <= n1440; - NDN5_2 <= n1445; - NDN5_3 <= n1450; - N_N3778 <= n1455; - NDN5_4 <= n1460; - N_N3212 <= n1465; - NDN5_5 <= n1470; - NDN5_6 <= n1475; - NDN5_7 <= n1480; - NDN5_8 <= n1485; - N_N4073 <= n1490; - NDN5_9 <= n1495; - NEN5_9 <= n1500; - N_N3684 <= n1505; - N_N4056 <= n1510; - N_N3713 <= n1515; - N_N3829 <= n1520; - N_N4060 <= n1525; - NSr3_2 <= n1530; - NSr5_2 <= n1535; - NSr5_3 <= n1540; - N_N3462 <= n1545; - N_N3460 <= n1550; - NSr5_4 <= n1555; - NSr3_9 <= n1560; - NSr5_5 <= n1565; - NSr5_7 <= n1570; - NSr5_8 <= n1575; - N_N3998 <= n1580; - end -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/dsip/dsip.v b/fpga_flow/benchmarks/Verilog/MCNC/dsip/dsip.v deleted file mode 100644 index a8275d9c1..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/dsip/dsip.v +++ /dev/null @@ -1,1917 +0,0 @@ -// Benchmark "top" written by ABC on Tue Mar 5 10:01:57 2019 - -module dsip ( clock, - pcount_3_, pkey_5_, pkey_131_, pkey_144_, pkey_157_, pkey_230_, - pkey_243_, pcount_2_, pkey_4_, pkey_132_, pkey_158_, pkey_169_, - pkey_242_, pcount_1_, pkey_146_, pkey_168_, pkey_245_, pcount_0_, - pkey_6_, pkey_130_, pkey_145_, pkey_244_, pkey_9_, pkey_16_, pkey_27_, - pkey_38_, pkey_49_, pkey_122_, pkey_148_, pkey_153_, pkey_166_, - pkey_221_, pkey_252_, pkey_8_, pkey_17_, pkey_26_, pkey_48_, pkey_110_, - pkey_121_, pkey_147_, pkey_154_, pkey_165_, pkey_220_, pkey_246_, - pkey_253_, pkey_18_, pkey_29_, pkey_36_, pkey_120_, pkey_155_, - pkey_164_, pkey_210_, pkey_249_, pkey_254_, pkey_19_, pkey_28_, - pkey_37_, pkey_46_, pkey_112_, pkey_149_, pkey_156_, pkey_163_, - pkey_211_, pkey_248_, pkey_56_, pkey_67_, pkey_78_, pkey_89_, - pkey_113_, pkey_126_, pkey_139_, pkey_162_, pkey_212_, pkey_225_, - pkey_238_, pkey_57_, pkey_66_, pkey_88_, pkey_114_, pkey_125_, - pkey_150_, pkey_161_, pkey_213_, pkey_224_, pkey_58_, pkey_69_, - pkey_76_, pkey_115_, pkey_124_, pkey_137_, pkey_160_, pkey_214_, - pkey_250_, pkey_59_, pkey_68_, pkey_77_, pkey_86_, pkey_116_, - pkey_123_, pkey_138_, pkey_152_, pkey_222_, pkey_237_, pkey_251_, - pkey_1_, pkey_96_, pkey_117_, pkey_140_, pkey_216_, pkey_229_, - pkey_234_, pkey_0_, pkey_97_, pkey_118_, pkey_129_, pkey_136_, - pkey_217_, pkey_228_, pkey_235_, pkey_3_, pkey_98_, pkey_128_, - pkey_133_, pkey_142_, pkey_218_, pkey_227_, pkey_232_, pkey_241_, - pkey_2_, pkey_99_, pkey_134_, pkey_141_, pkey_219_, pkey_226_, - pkey_233_, pkey_240_, pkey_70_, pkey_81_, pkey_92_, pkey_180_, - pkey_193_, pkey_80_, pkey_93_, pkey_107_, pkey_194_, pkey_206_, - pkey_50_, pkey_61_, pkey_94_, pkey_182_, pkey_195_, pkey_209_, - pstart_0_, pkey_51_, pkey_60_, pkey_109_, pkey_181_, pkey_196_, - pkey_208_, pkey_52_, pkey_74_, pkey_85_, pkey_104_, pkey_171_, - pkey_197_, pkey_203_, pencrypt_0_, pkey_53_, pkey_62_, pkey_75_, - pkey_84_, pkey_172_, pkey_198_, pkey_202_, pkey_54_, pkey_65_, - pkey_72_, pkey_83_, pkey_90_, pkey_106_, pkey_205_, pkey_64_, pkey_73_, - pkey_82_, pkey_91_, pkey_105_, pkey_170_, pkey_204_, pkey_12_, - pkey_34_, pkey_45_, pkey_100_, pkey_188_, pkey_13_, pkey_22_, pkey_35_, - pkey_44_, pkey_176_, pkey_187_, pkey_14_, pkey_25_, pkey_32_, pkey_43_, - pkey_102_, pkey_173_, pkey_201_, pkey_24_, pkey_33_, pkey_42_, - pkey_101_, pkey_174_, pkey_189_, pkey_200_, pkey_30_, pkey_41_, - pkey_179_, pkey_184_, pkey_40_, pkey_190_, pkey_10_, pkey_21_, - pkey_177_, pkey_186_, pkey_11_, pkey_20_, pkey_178_, pkey_185_, - pkey_192_, - pksi_50_, pksi_61_, pksi_72_, pksi_83_, pksi_94_, pksi_102_, pksi_115_, - pksi_128_, pdata_ready_0_, pksi_51_, pksi_60_, pksi_73_, pksi_82_, - pksi_95_, pksi_101_, pksi_116_, pksi_127_, pksi_52_, pksi_63_, - pksi_70_, pksi_81_, pksi_96_, pksi_100_, pksi_113_, pksi_53_, pksi_62_, - pksi_71_, pksi_80_, pksi_97_, pksi_114_, pksi_129_, pksi_54_, pksi_65_, - pksi_76_, pksi_87_, pksi_90_, pksi_119_, pksi_124_, pksi_191_, - pksi_55_, pksi_64_, pksi_77_, pksi_86_, pksi_91_, pksi_123_, pksi_56_, - pksi_67_, pksi_74_, pksi_85_, pksi_92_, pksi_117_, pksi_126_, pksi_57_, - pksi_66_, pksi_75_, pksi_84_, pksi_93_, pksi_118_, pksi_125_, - pksi_190_, pksi_14_, pksi_25_, pksi_36_, pksi_47_, pksi_120_, pksi_15_, - pksi_24_, pksi_37_, pksi_46_, pksi_109_, pnew_count_3_, pksi_16_, - pksi_27_, pksi_34_, pksi_45_, pksi_108_, pksi_122_, pksi_17_, pksi_26_, - pksi_35_, pksi_44_, pksi_107_, pksi_121_, pksi_10_, pksi_21_, pksi_32_, - pksi_43_, pksi_106_, pksi_111_, pnew_count_0_, pksi_11_, pksi_20_, - pksi_33_, pksi_42_, pksi_105_, pksi_112_, pksi_12_, pksi_23_, pksi_30_, - pksi_41_, pksi_104_, pnew_count_2_, pksi_13_, pksi_22_, pksi_31_, - pksi_40_, pksi_103_, pksi_110_, pnew_count_1_, pksi_3_, pksi_151_, - pksi_164_, pksi_177_, pksi_2_, pksi_152_, pksi_163_, pksi_178_, - pksi_189_, pksi_1_, pksi_166_, pksi_179_, pksi_188_, pksi_0_, - pksi_150_, pksi_165_, pksi_187_, pksi_18_, pksi_29_, pksi_142_, - pksi_168_, pksi_173_, pksi_186_, pksi_19_, pksi_28_, pksi_130_, - pksi_141_, pksi_167_, pksi_174_, pksi_185_, pksi_38_, pksi_49_, - pksi_131_, pksi_140_, pksi_175_, pksi_184_, pksi_39_, pksi_48_, - pksi_132_, pksi_169_, pksi_176_, pksi_183_, pksi_58_, pksi_69_, - pksi_133_, pksi_146_, pksi_159_, pksi_182_, pksi_59_, pksi_68_, - pksi_134_, pksi_145_, pksi_170_, pksi_181_, pksi_9_, pksi_78_, - pksi_89_, pksi_135_, pksi_144_, pksi_157_, pksi_171_, pksi_180_, - pksi_8_, pksi_79_, pksi_88_, pksi_136_, pksi_143_, pksi_158_, - pksi_172_, pksi_7_, pksi_98_, pksi_137_, pksi_155_, pksi_160_, pksi_6_, - pksi_99_, pksi_138_, pksi_149_, pksi_156_, pksi_5_, pksi_139_, - pksi_148_, pksi_153_, pksi_162_, pksi_4_, pksi_147_, pksi_154_, - pksi_161_ ); - input pcount_3_, pkey_5_, pkey_131_, pkey_144_, pkey_157_, pkey_230_, - pkey_243_, pcount_2_, pkey_4_, pkey_132_, pkey_158_, pkey_169_, - pkey_242_, pcount_1_, pkey_146_, pkey_168_, pkey_245_, pcount_0_, - pkey_6_, pkey_130_, pkey_145_, pkey_244_, pkey_9_, pkey_16_, pkey_27_, - pkey_38_, pkey_49_, pkey_122_, pkey_148_, pkey_153_, pkey_166_, - pkey_221_, pkey_252_, pkey_8_, pkey_17_, pkey_26_, pkey_48_, pkey_110_, - pkey_121_, pkey_147_, pkey_154_, pkey_165_, pkey_220_, pkey_246_, - pkey_253_, pkey_18_, pkey_29_, pkey_36_, pkey_120_, pkey_155_, - pkey_164_, pkey_210_, pkey_249_, pkey_254_, pkey_19_, pkey_28_, - pkey_37_, pkey_46_, pkey_112_, pkey_149_, pkey_156_, pkey_163_, - pkey_211_, pkey_248_, pkey_56_, pkey_67_, pkey_78_, pkey_89_, - pkey_113_, pkey_126_, pkey_139_, pkey_162_, pkey_212_, pkey_225_, - pkey_238_, pkey_57_, pkey_66_, pkey_88_, pkey_114_, pkey_125_, - pkey_150_, pkey_161_, pkey_213_, pkey_224_, pkey_58_, pkey_69_, - pkey_76_, pkey_115_, pkey_124_, pkey_137_, pkey_160_, pkey_214_, - pkey_250_, pkey_59_, pkey_68_, pkey_77_, pkey_86_, pkey_116_, - pkey_123_, pkey_138_, pkey_152_, pkey_222_, pkey_237_, pkey_251_, - pkey_1_, pkey_96_, pkey_117_, pkey_140_, pkey_216_, pkey_229_, - pkey_234_, pkey_0_, pkey_97_, pkey_118_, pkey_129_, pkey_136_, - pkey_217_, pkey_228_, pkey_235_, pkey_3_, pkey_98_, pkey_128_, - pkey_133_, pkey_142_, pkey_218_, pkey_227_, pkey_232_, pkey_241_, - pkey_2_, pkey_99_, pkey_134_, pkey_141_, pkey_219_, pkey_226_, - pkey_233_, pkey_240_, pkey_70_, pkey_81_, pkey_92_, pkey_180_, - pkey_193_, pkey_80_, pkey_93_, pkey_107_, pkey_194_, pkey_206_, clock, - pkey_50_, pkey_61_, pkey_94_, pkey_182_, pkey_195_, pkey_209_, - pstart_0_, pkey_51_, pkey_60_, pkey_109_, pkey_181_, pkey_196_, - pkey_208_, pkey_52_, pkey_74_, pkey_85_, pkey_104_, pkey_171_, - pkey_197_, pkey_203_, pencrypt_0_, pkey_53_, pkey_62_, pkey_75_, - pkey_84_, pkey_172_, pkey_198_, pkey_202_, pkey_54_, pkey_65_, - pkey_72_, pkey_83_, pkey_90_, pkey_106_, pkey_205_, pkey_64_, pkey_73_, - pkey_82_, pkey_91_, pkey_105_, pkey_170_, pkey_204_, pkey_12_, - pkey_34_, pkey_45_, pkey_100_, pkey_188_, pkey_13_, pkey_22_, pkey_35_, - pkey_44_, pkey_176_, pkey_187_, pkey_14_, pkey_25_, pkey_32_, pkey_43_, - pkey_102_, pkey_173_, pkey_201_, pkey_24_, pkey_33_, pkey_42_, - pkey_101_, pkey_174_, pkey_189_, pkey_200_, pkey_30_, pkey_41_, - pkey_179_, pkey_184_, pkey_40_, pkey_190_, pkey_10_, pkey_21_, - pkey_177_, pkey_186_, pkey_11_, pkey_20_, pkey_178_, pkey_185_, - pkey_192_; - output pksi_50_, pksi_61_, pksi_72_, pksi_83_, pksi_94_, pksi_102_, - pksi_115_, pksi_128_, pdata_ready_0_, pksi_51_, pksi_60_, pksi_73_, - pksi_82_, pksi_95_, pksi_101_, pksi_116_, pksi_127_, pksi_52_, - pksi_63_, pksi_70_, pksi_81_, pksi_96_, pksi_100_, pksi_113_, pksi_53_, - pksi_62_, pksi_71_, pksi_80_, pksi_97_, pksi_114_, pksi_129_, pksi_54_, - pksi_65_, pksi_76_, pksi_87_, pksi_90_, pksi_119_, pksi_124_, - pksi_191_, pksi_55_, pksi_64_, pksi_77_, pksi_86_, pksi_91_, pksi_123_, - pksi_56_, pksi_67_, pksi_74_, pksi_85_, pksi_92_, pksi_117_, pksi_126_, - pksi_57_, pksi_66_, pksi_75_, pksi_84_, pksi_93_, pksi_118_, pksi_125_, - pksi_190_, pksi_14_, pksi_25_, pksi_36_, pksi_47_, pksi_120_, pksi_15_, - pksi_24_, pksi_37_, pksi_46_, pksi_109_, pnew_count_3_, pksi_16_, - pksi_27_, pksi_34_, pksi_45_, pksi_108_, pksi_122_, pksi_17_, pksi_26_, - pksi_35_, pksi_44_, pksi_107_, pksi_121_, pksi_10_, pksi_21_, pksi_32_, - pksi_43_, pksi_106_, pksi_111_, pnew_count_0_, pksi_11_, pksi_20_, - pksi_33_, pksi_42_, pksi_105_, pksi_112_, pksi_12_, pksi_23_, pksi_30_, - pksi_41_, pksi_104_, pnew_count_2_, pksi_13_, pksi_22_, pksi_31_, - pksi_40_, pksi_103_, pksi_110_, pnew_count_1_, pksi_3_, pksi_151_, - pksi_164_, pksi_177_, pksi_2_, pksi_152_, pksi_163_, pksi_178_, - pksi_189_, pksi_1_, pksi_166_, pksi_179_, pksi_188_, pksi_0_, - pksi_150_, pksi_165_, pksi_187_, pksi_18_, pksi_29_, pksi_142_, - pksi_168_, pksi_173_, pksi_186_, pksi_19_, pksi_28_, pksi_130_, - pksi_141_, pksi_167_, pksi_174_, pksi_185_, pksi_38_, pksi_49_, - pksi_131_, pksi_140_, pksi_175_, pksi_184_, pksi_39_, pksi_48_, - pksi_132_, pksi_169_, pksi_176_, pksi_183_, pksi_58_, pksi_69_, - pksi_133_, pksi_146_, pksi_159_, pksi_182_, pksi_59_, pksi_68_, - pksi_134_, pksi_145_, pksi_170_, pksi_181_, pksi_9_, pksi_78_, - pksi_89_, pksi_135_, pksi_144_, pksi_157_, pksi_171_, pksi_180_, - pksi_8_, pksi_79_, pksi_88_, pksi_136_, pksi_143_, pksi_158_, - pksi_172_, pksi_7_, pksi_98_, pksi_137_, pksi_155_, pksi_160_, pksi_6_, - pksi_99_, pksi_138_, pksi_149_, pksi_156_, pksi_5_, pksi_139_, - pksi_148_, pksi_153_, pksi_162_, pksi_4_, pksi_147_, pksi_154_, - pksi_161_; - reg pksi_17_, pksi_185_, n_n2410, pksi_170_, pksi_155_, pksi_147_, - pksi_109_, n_n2513, pksi_19_, n_n2396, n_n2412, n_n121, pksi_148_, - n_n2448, pksi_107_, pksi_110_, pksi_9_, pksi_176_, pksi_180_, - pksi_178_, pksi_135_, pksi_129_, pksi_100_, pksi_117_, pksi_118_, - pksi_5_, pksi_169_, n_n2408, pksi_184_, pksi_125_, pksi_138_, - pksi_114_, pksi_99_, pksi_85_, pksi_14_, pksi_4_, pksi_186_, n_n2420, - pksi_141_, pksi_113_, pksi_115_, pksi_98_, pksi_2_, pksi_23_, - pksi_177_, pksi_189_, n_n2485, n_n2495, pksi_97_, pksi_102_, pksi_11_, - pksi_173_, pksi_179_, pksi_171_, pksi_104_, pksi_103_, n_n2384, - pksi_183_, pksi_172_, n_n2416, pksi_116_, pksi_96_, pksi_119_, - pksi_84_, pksi_159_, n_n2440, pksi_160_, pksi_128_, pksi_127_, - pksi_142_, n_n2272, pksi_149_, pksi_162_, pksi_154_, pksi_121_, - pksi_134_, pksi_126_, pksi_82_, n_n2430, pksi_153_, pksi_165_, - pksi_137_, n_n2481, pksi_101_, pksi_93_, pksi_161_, pksi_156_, n_n2452, - n_n2462, pksi_123_, pksi_111_, pksi_92_, pksi_15_, n_n109, pksi_145_, - pksi_144_, pksi_150_, pksi_124_, pksi_132_, pksi_130_, pksi_105_, - pksi_112_, n_n10, pksi_6_, pksi_188_, pksi_152_, pksi_163_, pksi_166_, - pksi_131_, n_n2474, pksi_136_, pksi_108_, n_n2517, n_n2268, pksi_175_, - pksi_190_, pksi_164_, pksi_158_, pksi_167_, pksi_133_, n_n2476, - pksi_122_, n_n2507, pksi_75_, pksi_182_, pksi_174_, pksi_157_, - pksi_151_, pksi_146_, pksi_140_, pksi_120_, n_n168, pksi_106_, - pksi_57_, pksi_36_, pksi_38_, pksi_28_, n_n2374, pksi_53_, pksi_27_, - pksi_26_, pksi_47_, pksi_1_, pksi_63_, pksi_34_, pksi_24_, pksi_30_, - pksi_18_, pksi_79_, pksi_54_, n_n2337, pksi_46_, pksi_39_, pksi_8_, - n_n2277, pksi_91_, pksi_51_, pksi_70_, pksi_0_, pksi_73_, pksi_89_, - pksi_60_, pksi_48_, pksi_22_, n_n2280, pksi_77_, pksi_64_, pksi_56_, - pksi_80_, pksi_81_, n_n2301, pksi_66_, pksi_72_, pksi_78_, pksi_69_, - n_n2320, pksi_40_, pksi_32_, pksi_94_, pksi_87_, pksi_61_, pksi_59_, - n_n2333, pksi_42_, pksi_86_, pksi_76_, n_n2305, pksi_50_, pksi_33_, - pksi_12_, pksi_74_, pksi_95_, pksi_58_, pksi_62_, pksi_29_, pksi_3_, - pksi_83_, pksi_68_, pksi_71_, pksi_37_, pksi_41_, n_n2365, n_n2369, - n_n2288, pksi_55_, pksi_52_, pksi_45_, pksi_43_, pksi_16_, pksi_10_, - n_n2310, pksi_67_, pksi_31_, pksi_25_, pksi_35_, pksi_20_, pksi_21_, - pksi_49_, pksi_65_, pksi_44_, n_n2342, n_n2352, pksi_7_, pksi_13_; - wire n1327_1, n1328, n1329, n1330, n1331, n1332_1, n1341, n1342, n1343, - n1344_1, n1345, n1346, n1347, n1348_1, n1349, n1350, n1351, n1352_1, - n1353, n1354, n1355, n1356_1, n1357, n1358, n1359, n1360, n1361_1, - n1362, n1363, n1364, n1365_1, n1366, n1367, n1368, n1369, n1370_1, - n1371, n1372, n1373, n1374_1, n1375, n1376, n1377, n1378_1, n1379, - n1380, n1381, n1382_1, n1383, n1384, n1385, n1386_1, n1387, n1388, - n1389, n1390_1, n1391, n1392, n1393, n1394_1, n1395, n1396, n1397, - n1398_1, n1399, n1400, n1401, n1402_1, n1403, n1404, n1405, n1406, - n1407_1, n1408, n1409, n1410, n1411_1, n1412, n1413, n1414, n1415_1, - n1416, n1417, n1418, n1419_1, n1420, n1421, n1422, n1423_1, n1424, - n1425, n1426, n1427_1, n1428, n1429, n1430, n1431, n1432_1, n1433, - n1434, n1435, n1436_1, n1437, n1438, n1439, n1440_1, n1441, n1442, - n1443, n1444_1, n1445, n1446, n1447, n1448_1, n1449, n1450, n1451, - n1452_1, n1453, n1454, n1455, n1456_1, n1457, n1458, n1459, n1460_1, - n1461, n1462, n1463, n1464_1, n1465, n1466, n1467, n1468_1, n1469, - n1470, n1471, n1472_1, n1473, n1474, n1475, n1476_1, n1477, n1478, - n1479, n1480_1, n1481, n1482, n1483, n1484, n1485_1, n1486, n1487, - n1488, n1489_1, n1490, n1491, n1492, n1493_1, n1494, n1495, n1496, - n1497_1, n1498, n1499, n1500, n1501, n1502_1, n1503, n1504, n1505, - n1506_1, n1507, n1508, n1509, n1510_1, n1511, n1512, n1513, n1514_1, - n1515, n1516, n1517, n1518_1, n1519, n1520, n1521, n1522_1, n1523, - n1524, n1525, n1526_1, n1527, n1528, n1529, n1530_1, n1531, n1532, - n1533, n1534_1, n1535, n1536, n1537, n1538_1, n1539, n1540, n1541, - n1542, n1543_1, n1544, n1545, n1546, n1547_1, n1548, n1549, n1550, - n1551_1, n1552, n1553, n1554, n1555_1, n1556, n1557, n1558, n1559_1, - n1560, n1561, n1562, n1563_1, n1564, n1565, n1566, n1567, n1568_1, - n1569, n1570, n1571, n1572_1, n1573, n1574, n1575, n1576_1, n1577, - n1578, n1579, n1580_1, n1581, n1582, n1583, n1584_1, n1585, n1586, - n1587, n1588, n1589_1, n1590, n1591, n1592, n1593_1, n1594, n1595, - n1596, n1597_1, n1598, n1599, n1600, n1601_1, n1602, n1603, n1604, - n1605_1, n1606, n1607, n1608, n1609_1, n1610, n1611, n1612, n1613_1, - n1614, n1615, n1616, n1617, n1618_1, n1619, n1620, n1621, n1622_1, - n1623, n1624, n1625, n1626_1, n1627, n1628, n1629, n1630_1, n1631, - n1632, n1633, n1634, n1635_1, n1636, n1637, n1638, n1639_1, n1640, - n1641, n1642, n1643_1, n1644, n1645, n1646, n1647_1, n1648, n1649, - n1650, n1651_1, n1652, n1653, n1654, n1655_1, n1656, n1657, n1658, - n1659_1, n1660, n1661, n1662, n1663_1, n1664, n1665, n1666, n1667_1, - n1668, n1669, n1670, n1671_1, n1672, n1673, n1674, n1675_1, n1676, - n1677, n1678, n1679_1, n1680, n1681, n1682, n1683_1, n1684, n1685, - n1686, n1687_1, n1688, n1689, n1690, n1691_1, n1692, n1693, n1694, - n1695, n1696_1, n1697, n1698, n1699, n1700, n1701_1, n1702, n1703, - n1704, n1705, n1706_1, n1707, n1708, n1709, n1710_1, n1711, n1712, - n1713, n1714_1, n1715, n1716, n1717, n1718_1, n1719, n1720, n1721, - n1722_1, n1723, n1724, n1725, n1726_1, n1727, n1728, n1729, n1730_1, - n1731, n1732, n1733, n1734, n1735_1, n1736, n1737, n1738, n1739_1, - n1740, n1741, n1742, n1743_1, n1744, n1745, n1746, n1747_1, n1748, - n1749, n1750, n1751_1, n1752, n1753, n1754, n1755_1, n1756, n1757, - n1758, n1759_1, n1760, n1761, n1762, n1763_1, n1764, n1765, n1766, - n1767_1, n1768, n1769, n1770, n1771_1, n1772, n1773, n1774, n1775, - n1776_1, n1777, n1778, n1779, n1780, n1781_1, n1782, n1783, n1784, - n1785_1, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, - n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, - n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, - n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, - n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, - n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, - n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, - n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, - n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, - n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, - n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, - n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, - n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, - n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, - n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, - n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, - n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, - n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, - n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, - n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, - n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, - n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, - n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, - n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, - n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, - n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, - n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, - n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, - n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, - n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, - n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, - n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, - n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, - n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, - n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, - n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, - n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, - n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, - n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, - n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, - n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, - n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, - n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, - n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, - n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, - n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, - n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, - n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, - n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, - n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, - n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, - n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, - n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, - n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, - n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, - n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, - n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, - n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, - n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, - n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, - n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, - n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, - n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, - n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, - n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, - n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, - n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, - n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, - n2465, n2466, n2467, n853, n857, n861, n866, n870, n874, n878, n882, - n887, n891, n896, n901, n906, n910, n915, n919, n923, n927, n931, n935, - n939, n943, n947, n951, n955, n959, n963, n967, n972, n976, n980, n984, - n988, n992, n996, n1000, n1004, n1008, n1013, n1017, n1021, n1025, - n1029, n1033, n1037, n1041, n1045, n1050, n1055, n1059, n1063, n1067, - n1071, n1075, n1079, n1083, n1087, n1092, n1096, n1100, n1105, n1109, - n1113, n1117, n1121, n1125, n1130, n1134, n1138, n1142, n1146, n1151, - n1155, n1159, n1163, n1167, n1171, n1175, n1179, n1184, n1188, n1192, - n1196, n1201, n1205, n1209, n1213, n1217, n1222, n1227, n1231, n1235, - n1239, n1243, n1248, n1252, n1256, n1260, n1264, n1268, n1272, n1276, - n1280, n1285, n1289, n1293, n1297, n1301, n1305, n1309, n1314, n1318, - n1322, n1327, n1332, n1336, n1340, n1344, n1348, n1352, n1356, n1361, - n1365, n1370, n1374, n1378, n1382, n1386, n1390, n1394, n1398, n1402, - n1407, n1411, n1415, n1419, n1423, n1427, n1432, n1436, n1440, n1444, - n1448, n1452, n1456, n1460, n1464, n1468, n1472, n1476, n1480, n1485, - n1489, n1493, n1497, n1502, n1506, n1510, n1514, n1518, n1522, n1526, - n1530, n1534, n1538, n1543, n1547, n1551, n1555, n1559, n1563, n1568, - n1572, n1576, n1580, n1584, n1589, n1593, n1597, n1601, n1605, n1609, - n1613, n1618, n1622, n1626, n1630, n1635, n1639, n1643, n1647, n1651, - n1655, n1659, n1663, n1667, n1671, n1675, n1679, n1683, n1687, n1691, - n1696, n1701, n1706, n1710, n1714, n1718, n1722, n1726, n1730, n1735, - n1739, n1743, n1747, n1751, n1755, n1759, n1763, n1767, n1771, n1776, - n1781, n1785; - assign pdata_ready_0_ = (n1327_1 & n2465) | (n1328 & n1329); - assign pnew_count_3_ = n1343 | n1342 | (pstart_0_ & ~pencrypt_0_); - assign pnew_count_0_ = pstart_0_ ? ~pencrypt_0_ : ~pcount_0_; - assign pnew_count_2_ = n2467 | (pcount_2_ & ~n1331); - assign pnew_count_1_ = (pcount_1_ & (pcount_0_ ? ~pencrypt_0_ : (~pstart_0_ & pencrypt_0_))) | (~pcount_1_ & (pcount_0_ ? (~pstart_0_ & pencrypt_0_) : ~pencrypt_0_)) | (pstart_0_ & ~pencrypt_0_); - assign n853 = n2014 | n2015 | n2016 | n2018; - assign n857 = n2011 | n2012 | n2013 | n2020; - assign n861 = n2008 | n2009 | n2010 | n2022; - assign n866 = n2005 | n2006 | n2007 | n2024; - assign n870 = n2002 | n2003 | n2004 | n2026; - assign n874 = n1999 | n2000 | n2001 | n2028; - assign n878 = n1996 | n1997 | n1998 | n2030; - assign n882 = n1993 | n1994 | n1995 | n2032; - assign n887 = n1990 | n1991 | n1992 | n2034; - assign n891 = n1987 | n1988 | n1989 | n2036; - assign n896 = n1984 | n1985 | n1986 | n2038; - assign n901 = n1981 | n1982 | n1983 | n2040; - assign n906 = n1978 | n1979 | n1980 | n2042; - assign n910 = n1975 | n1976 | n1977 | n2044; - assign n915 = n1972 | n1973 | n1974 | n2046; - assign n919 = n1969 | n1970 | n1971 | n2048; - assign n923 = n1966 | n1967 | n1968 | n2050; - assign n927 = n1963 | n1964 | n1965 | n2052; - assign n931 = n1960 | n1961 | n1962 | n2054; - assign n935 = n1957 | n1958 | n1959 | n2056; - assign n939 = n1954 | n1955 | n1956 | n2058; - assign n943 = n1951 | n1952 | n1953 | n2060; - assign n947 = n1948 | n1949 | n1950 | n2062; - assign n951 = n1945 | n1946 | n1947 | n2064; - assign n955 = n1942 | n1943 | n1944 | n2066; - assign n959 = n1939 | n1940 | n1941 | n2068; - assign n963 = n1936 | n1937 | n1938 | n2070; - assign n967 = n1933 | n1934 | n1935 | n2072; - assign n972 = n1930 | n1931 | n1932 | n2074; - assign n976 = n1927 | n1928 | n1929 | n2076; - assign n980 = n1924 | n1925 | n1926 | n2078; - assign n984 = n1921 | n1922 | n1923 | n2080; - assign n988 = n1918 | n1919 | n1920 | n2082; - assign n992 = n1915 | n1916 | n1917 | n2084; - assign n996 = n1912 | n1913 | n1914 | n2086; - assign n1000 = n1909 | n1910 | n1911 | n2088; - assign n1004 = n1906 | n1907 | n1908 | n2090; - assign n1008 = n1903 | n1904 | n1905 | n2092; - assign n1013 = n1900 | n1901 | n1902 | n2094; - assign n1017 = n1897 | n1898 | n1899 | n2096; - assign n1021 = n1894 | n1895 | n1896 | n2098; - assign n1025 = n1891 | n1892 | n1893 | n2100; - assign n1029 = n1888 | n1889 | n1890 | n2102; - assign n1033 = n1885 | n1886 | n1887 | n2104; - assign n1037 = n1882 | n1883 | n1884 | n2106; - assign n1041 = n1879 | n1880 | n1881 | n2108; - assign n1045 = n1876 | n1877 | n1878 | n2110; - assign n1050 = n1873 | n1874 | n1875 | n2112; - assign n1055 = n1870 | n1871 | n1872 | n2114; - assign n1059 = n1867 | n1868 | n1869 | n2116; - assign n1063 = n1864 | n1865 | n1866 | n2118; - assign n1067 = n1861 | n1862 | n1863 | n2120; - assign n1071 = n1858 | n1859 | n1860 | n2122; - assign n1075 = n1855 | n1856 | n1857 | n2124; - assign n1079 = n1852 | n1853 | n1854 | n2126; - assign n1083 = n1849 | n1850 | n1851 | n2128; - assign n1087 = n1846 | n1847 | n1848 | n2130; - assign n1092 = n1843 | n1844 | n1845 | n2132; - assign n1096 = n1840 | n1841 | n1842 | n2134; - assign n1100 = n1837 | n1838 | n1839 | n2136; - assign n1105 = n1834 | n1835 | n1836 | n2138; - assign n1109 = n1831 | n1832 | n1833 | n2140; - assign n1113 = n1828 | n1829 | n1830 | n2142; - assign n1117 = n1825 | n1826 | n1827 | n2144; - assign n1121 = n1822 | n1823 | n1824 | n2146; - assign n1125 = n1819 | n1820 | n1821 | n2148; - assign n1130 = n1816 | n1817 | n1818 | n2150; - assign n1134 = n1813 | n1814 | n1815 | n2152; - assign n1138 = n1810 | n1811 | n1812 | n2154; - assign n1142 = n1807 | n1808 | n1809 | n2156; - assign n1146 = n1804 | n1805 | n1806 | n2158; - assign n1151 = n1801 | n1802 | n1803 | n2160; - assign n1155 = n1798 | n1799 | n1800 | n2162; - assign n1159 = n1795 | n1796 | n1797 | n2164; - assign n1163 = n1792 | n1793 | n1794 | n2166; - assign n1167 = n1789 | n1790 | n1791 | n2168; - assign n1171 = n1786 | n1787 | n1788 | n2170; - assign n1175 = n1783 | n1784 | n1785_1 | n2172; - assign n1179 = n1780 | n1781_1 | n1782 | n2174; - assign n1184 = n1777 | n1778 | n1779 | n2176; - assign n1188 = n1774 | n1775 | n1776_1 | n2178; - assign n1192 = n1771_1 | n1772 | n1773 | n2180; - assign n1196 = n1768 | n1769 | n1770 | n2182; - assign n1201 = n1765 | n1766 | n1767_1 | n2184; - assign n1205 = n1762 | n1763_1 | n1764 | n2186; - assign n1209 = n1759_1 | n1760 | n1761 | n2188; - assign n1213 = n1756 | n1757 | n1758 | n2190; - assign n1217 = n1753 | n1754 | n1755_1 | n2192; - assign n1222 = n1750 | n1751_1 | n1752 | n2194; - assign n1227 = n1747_1 | n1748 | n1749 | n2196; - assign n1231 = n1744 | n1745 | n1746 | n2198; - assign n1235 = n1741 | n1742 | n1743_1 | n2200; - assign n1239 = n1738 | n1739_1 | n1740 | n2202; - assign n1243 = n1735_1 | n1736 | n1737 | n2204; - assign n1248 = n1732 | n1733 | n1734 | n2206; - assign n1252 = n1729 | n1730_1 | n1731 | n2208; - assign n1256 = n1726_1 | n1727 | n1728 | n2210; - assign n1260 = n1723 | n1724 | n1725 | n2212; - assign n1264 = n1720 | n1721 | n1722_1 | n2214; - assign n1268 = n1717 | n1718_1 | n1719 | n2216; - assign n1272 = n1714_1 | n1715 | n1716 | n2218; - assign n1276 = n1711 | n1712 | n1713 | n2220; - assign n1280 = n1708 | n1709 | n1710_1 | n2222; - assign n1285 = n1705 | n1706_1 | n1707 | n2224; - assign n1289 = n1702 | n1703 | n1704 | n2226; - assign n1293 = n1699 | n1700 | n1701_1 | n2228; - assign n1297 = n1696_1 | n1697 | n1698 | n2230; - assign n1301 = n1693 | n1694 | n1695 | n2232; - assign n1305 = n1690 | n1691_1 | n1692 | n2234; - assign n1309 = n1687_1 | n1688 | n1689 | n2236; - assign n1314 = n1684 | n1685 | n1686 | n2238; - assign n1318 = n1681 | n1682 | n1683_1 | n2240; - assign n1322 = n1678 | n1679_1 | n1680 | n2242; - assign n1327 = n1675_1 | n1676 | n1677 | n2244; - assign n1332 = n1672 | n1673 | n1674 | n2246; - assign n1336 = n1669 | n1670 | n1671_1 | n2248; - assign n1340 = n1666 | n1667_1 | n1668 | n2250; - assign n1344 = n1663_1 | n1664 | n1665 | n2252; - assign n1348 = n1660 | n1661 | n1662 | n2254; - assign n1352 = n1657 | n1658 | n1659_1 | n2256; - assign n1356 = n1654 | n1655_1 | n1656 | n2258; - assign n1361 = n1651_1 | n1652 | n1653 | n2260; - assign n1365 = n1648 | n1649 | n1650 | n2262; - assign n1370 = n1645 | n1646 | n1647_1 | n2264; - assign n1374 = n1642 | n1643_1 | n1644 | n2266; - assign n1378 = n1639_1 | n1640 | n1641 | n2268; - assign n1382 = n1636 | n1637 | n1638 | n2270; - assign n1386 = n1633 | n1634 | n1635_1 | n2272; - assign n1390 = n1630_1 | n1631 | n1632 | n2274; - assign n1394 = n1627 | n1628 | n1629 | n2276; - assign n1398 = n1624 | n1625 | n1626_1 | n2278; - assign n1402 = n1621 | n1622_1 | n1623 | n2280; - assign n1407 = n1618_1 | n1619 | n1620 | n2282; - assign n1411 = n1615 | n1616 | n1617 | n2284; - assign n1415 = n1612 | n1613_1 | n1614 | n2286; - assign n1419 = n1609_1 | n1610 | n1611 | n2288; - assign n1423 = n1606 | n1607 | n1608 | n2290; - assign n1427 = n1603 | n1604 | n1605_1 | n2292; - assign n1432 = n1600 | n1601_1 | n1602 | n2294; - assign n1436 = n1597_1 | n1598 | n1599 | n2296; - assign n1440 = n1594 | n1595 | n1596 | n2298; - assign n1444 = n1591 | n1592 | n1593_1 | n2300; - assign n1448 = n1588 | n1589_1 | n1590 | n2302; - assign n1452 = n1585 | n1586 | n1587 | n2304; - assign n1456 = n1582 | n1583 | n1584_1 | n2306; - assign n1460 = n1579 | n1580_1 | n1581 | n2308; - assign n1464 = n1576_1 | n1577 | n1578 | n2310; - assign n1468 = n1573 | n1574 | n1575 | n2312; - assign n1472 = n1570 | n1571 | n1572_1 | n2314; - assign n1476 = n1567 | n1568_1 | n1569 | n2316; - assign n1480 = n1564 | n1565 | n1566 | n2318; - assign n1485 = n1561 | n1562 | n1563_1 | n2320; - assign n1489 = n1558 | n1559_1 | n1560 | n2322; - assign n1493 = n1555_1 | n1556 | n1557 | n2324; - assign n1497 = n1552 | n1553 | n1554 | n2326; - assign n1502 = n1549 | n1550 | n1551_1 | n2328; - assign n1506 = n1546 | n1547_1 | n1548 | n2330; - assign n1510 = n1543_1 | n1544 | n1545 | n2332; - assign n1514 = n1540 | n1541 | n1542 | n2334; - assign n1518 = n1537 | n1538_1 | n1539 | n2336; - assign n1522 = n1534_1 | n1535 | n1536 | n2338; - assign n1526 = n1531 | n1532 | n1533 | n2340; - assign n1530 = n1528 | n1529 | n1530_1 | n2342; - assign n1534 = n1525 | n1526_1 | n1527 | n2344; - assign n1538 = n1522_1 | n1523 | n1524 | n2346; - assign n1543 = n1519 | n1520 | n1521 | n2348; - assign n1547 = n1516 | n1517 | n1518_1 | n2350; - assign n1551 = n1513 | n1514_1 | n1515 | n2352; - assign n1555 = n1510_1 | n1511 | n1512 | n2354; - assign n1559 = n1507 | n1508 | n1509 | n2356; - assign n1563 = n1504 | n1505 | n1506_1 | n2358; - assign n1568 = n1501 | n1502_1 | n1503 | n2360; - assign n1572 = n1498 | n1499 | n1500 | n2362; - assign n1576 = n1495 | n1496 | n1497_1 | n2364; - assign n1580 = n1492 | n1493_1 | n1494 | n2366; - assign n1584 = n1489_1 | n1490 | n1491 | n2368; - assign n1589 = n1486 | n1487 | n1488 | n2370; - assign n1593 = n1483 | n1484 | n1485_1 | n2372; - assign n1597 = n1480_1 | n1481 | n1482 | n2374; - assign n1601 = n1477 | n1478 | n1479 | n2376; - assign n1605 = n1474 | n1475 | n1476_1 | n2378; - assign n1609 = n1471 | n1472_1 | n1473 | n2380; - assign n1613 = n1468_1 | n1469 | n1470 | n2382; - assign n1618 = n1465 | n1466 | n1467 | n2384; - assign n1622 = n1462 | n1463 | n1464_1 | n2386; - assign n1626 = n1459 | n1460_1 | n1461 | n2388; - assign n1630 = n1456_1 | n1457 | n1458 | n2390; - assign n1635 = n1453 | n1454 | n1455 | n2392; - assign n1639 = n1450 | n1451 | n1452_1 | n2394; - assign n1643 = n1447 | n1448_1 | n1449 | n2396; - assign n1647 = n1444_1 | n1445 | n1446 | n2398; - assign n1651 = n1441 | n1442 | n1443 | n2400; - assign n1655 = n1438 | n1439 | n1440_1 | n2402; - assign n1659 = n1435 | n1436_1 | n1437 | n2404; - assign n1663 = n1432_1 | n1433 | n1434 | n2406; - assign n1667 = n1429 | n1430 | n1431 | n2408; - assign n1671 = n1426 | n1427_1 | n1428 | n2410; - assign n1675 = n1423_1 | n1424 | n1425 | n2412; - assign n1679 = n1420 | n1421 | n1422 | n2414; - assign n1683 = n1417 | n1418 | n1419_1 | n2416; - assign n1687 = n1414 | n1415_1 | n1416 | n2418; - assign n1691 = n1411_1 | n1412 | n1413 | n2420; - assign n1696 = n1408 | n1409 | n1410 | n2422; - assign n1701 = n1405 | n1406 | n1407_1 | n2424; - assign n1706 = n1402_1 | n1403 | n1404 | n2426; - assign n1710 = n1399 | n1400 | n1401 | n2428; - assign n1714 = n1396 | n1397 | n1398_1 | n2430; - assign n1718 = n1393 | n1394_1 | n1395 | n2432; - assign n1722 = n1390_1 | n1391 | n1392 | n2434; - assign n1726 = n1387 | n1388 | n1389 | n2436; - assign n1730 = n1384 | n1385 | n1386_1 | n2438; - assign n1735 = n1381 | n1382_1 | n1383 | n2440; - assign n1739 = n1378_1 | n1379 | n1380 | n2442; - assign n1743 = n1375 | n1376 | n1377 | n2444; - assign n1747 = n1372 | n1373 | n1374_1 | n2446; - assign n1751 = n1369 | n1370_1 | n1371 | n2448; - assign n1755 = n1366 | n1367 | n1368 | n2450; - assign n1759 = n1363 | n1364 | n1365_1 | n2452; - assign n1763 = n1360 | n1361_1 | n1362 | n2454; - assign n1767 = n1357 | n1358 | n1359 | n2456; - assign n1771 = n1354 | n1355 | n1356_1 | n2458; - assign n1776 = n1351 | n1352_1 | n1353 | n2460; - assign n1781 = n1348_1 | n1349 | n1350 | n2462; - assign n1785 = n1345 | n1346 | n1347 | n2464; - assign n1327_1 = (~pcount_3_ & (pcount_2_ ? (pcount_1_ & pcount_0_) : (~pcount_1_ & ~pcount_0_))) | (pcount_1_ & ~pcount_0_ & pcount_3_ & pcount_2_); - assign n1328 = (~pcount_2_ & ~pcount_1_ & (~pcount_3_ | ~pcount_0_)) | (pcount_1_ & pcount_0_ & pcount_3_ & pcount_2_); - assign n1329 = pencrypt_0_ & ~pstart_0_ & pcount_1_ & pcount_0_; - assign n1330 = ~pstart_0_ | pencrypt_0_; - assign n1331 = (pencrypt_0_ & (pstart_0_ | (pcount_1_ & pcount_0_))) | (~pcount_1_ & ~pcount_0_ & ~pencrypt_0_); - assign n1332_1 = ~pstart_0_ & pencrypt_0_; - assign pksi_90_ = n_n10; - assign pksi_191_ = n_n121; - assign pksi_187_ = n_n121; - assign pksi_168_ = n_n109; - assign pksi_181_ = n_n109; - assign pksi_88_ = n_n10; - assign pksi_143_ = n_n168; - assign pksi_139_ = n_n168; - assign n1341 = ~pencrypt_0_ & ~pcount_0_ & ~pcount_2_ & ~pcount_1_; - assign n1342 = ~pcount_3_ & (n1344_1 | (pcount_2_ & n1329)); - assign n1343 = pcount_3_ & (~n1331 | n2466); - assign n1344_1 = ~pencrypt_0_ & ~pcount_0_ & ~pcount_2_ & ~pcount_1_; - assign n1345 = n1328 & n_n2374 & ~pstart_0_ & ~pencrypt_0_; - assign n1346 = ~n1328 & pksi_1_ & ~pstart_0_ & ~pencrypt_0_; - assign n1347 = ~n1327_1 & pksi_10_ & ~pstart_0_ & pencrypt_0_; - assign n1348_1 = ~n1328 & pksi_16_ & ~pstart_0_ & ~pencrypt_0_; - assign n1349 = n1328 & pksi_20_ & ~pstart_0_ & ~pencrypt_0_; - assign n1350 = ~n1327_1 & pksi_47_ & ~pstart_0_ & pencrypt_0_; - assign n1351 = ~n1328 & pksi_43_ & ~pstart_0_ & ~pencrypt_0_; - assign n1352_1 = n1328 & pksi_41_ & ~pstart_0_ & ~pencrypt_0_; - assign n1353 = ~n1327_1 & pksi_26_ & ~pstart_0_ & pencrypt_0_; - assign n1354 = ~n1328 & pksi_42_ & ~pstart_0_ & ~pencrypt_0_; - assign n1355 = n1328 & pksi_25_ & ~pstart_0_ & ~pencrypt_0_; - assign n1356_1 = ~n1327_1 & pksi_45_ & ~pstart_0_ & pencrypt_0_; - assign n1357 = ~n1328 & n_n2333 & ~pstart_0_ & ~pencrypt_0_; - assign n1358 = n1328 & pksi_40_ & ~pstart_0_ & ~pencrypt_0_; - assign n1359 = ~n1327_1 & pksi_52_ & ~pstart_0_ & pencrypt_0_; - assign n1360 = ~n1328 & pksi_57_ & ~pstart_0_ & ~pencrypt_0_; - assign n1361_1 = n1328 & pksi_67_ & ~pstart_0_ & ~pencrypt_0_; - assign n1362 = ~n1327_1 & pksi_59_ & ~pstart_0_ & pencrypt_0_; - assign n1363 = ~n1328 & pksi_56_ & ~pstart_0_ & ~pencrypt_0_; - assign n1364 = n1328 & pksi_66_ & ~pstart_0_ & ~pencrypt_0_; - assign n1365_1 = ~n1327_1 & pksi_61_ & ~pstart_0_ & pencrypt_0_; - assign n1366 = ~n1328 & n_n2374 & ~pstart_0_ & ~pencrypt_0_; - assign n1367 = n1327_1 & pksi_10_ & ~pstart_0_ & pencrypt_0_; - assign n1368 = n1328 & pksi_13_ & ~pstart_0_ & ~pencrypt_0_; - assign n1369 = ~n1328 & n_n2365 & ~pstart_0_ & ~pencrypt_0_; - assign n1370_1 = n1328 & pksi_16_ & ~pstart_0_ & ~pencrypt_0_; - assign n1371 = ~n1327_1 & pksi_28_ & ~pstart_0_ & pencrypt_0_; - assign n1372 = n1328 & n_n2352 & ~pstart_0_ & ~pencrypt_0_; - assign n1373 = ~n1328 & pksi_41_ & ~pstart_0_ & ~pencrypt_0_; - assign n1374_1 = ~n1327_1 & pksi_38_ & ~pstart_0_ & pencrypt_0_; - assign n1375 = ~n1328 & pksi_32_ & ~pstart_0_ & ~pencrypt_0_; - assign n1376 = n1328 & pksi_42_ & ~pstart_0_ & ~pencrypt_0_; - assign n1377 = ~n1327_1 & pksi_37_ & ~pstart_0_ & pencrypt_0_; - assign n1378_1 = ~n1328 & pksi_40_ & ~pstart_0_ & ~pencrypt_0_; - assign n1379 = n1328 & pksi_44_ & ~pstart_0_ & ~pencrypt_0_; - assign n1380 = ~n1327_1 & pksi_71_ & ~pstart_0_ & pencrypt_0_; - assign n1381 = ~n1328 & pksi_53_ & ~pstart_0_ & ~pencrypt_0_; - assign n1382_1 = n1327_1 & pksi_65_ & ~pstart_0_ & pencrypt_0_; - assign n1383 = n1328 & pksi_57_ & ~pstart_0_ & ~pencrypt_0_; - assign n1384 = ~n1328 & pksi_66_ & ~pstart_0_ & ~pencrypt_0_; - assign n1385 = n1328 & pksi_49_ & ~pstart_0_ & ~pencrypt_0_; - assign n1386_1 = ~n1327_1 & pksi_69_ & ~pstart_0_ & pencrypt_0_; - assign n1387 = ~n1328 & pksi_13_ & ~pstart_0_ & ~pencrypt_0_; - assign n1388 = n1328 & pksi_21_ & ~pstart_0_ & ~pencrypt_0_; - assign n1389 = ~n1327_1 & pksi_12_ & ~pstart_0_ & pencrypt_0_; - assign n1390_1 = n1328 & n_n2365 & ~pstart_0_ & ~pencrypt_0_; - assign n1391 = ~n1328 & pksi_3_ & ~pstart_0_ & ~pencrypt_0_; - assign n1392 = ~n1327_1 & pksi_7_ & ~pstart_0_ & pencrypt_0_; - assign n1393 = ~n1328 & pksi_29_ & ~pstart_0_ & ~pencrypt_0_; - assign n1394_1 = n1327_1 & pksi_41_ & ~pstart_0_ & pencrypt_0_; - assign n1395 = n1328 & pksi_33_ & ~pstart_0_ & ~pencrypt_0_; - assign n1396 = ~n1328 & n_n2342 & ~pstart_0_ & ~pencrypt_0_; - assign n1397 = n1327_1 & pksi_34_ & ~pstart_0_ & pencrypt_0_; - assign n1398_1 = n1328 & pksi_37_ & ~pstart_0_ & ~pencrypt_0_; - assign n1399 = ~n1328 & pksi_44_ & ~pstart_0_ & ~pencrypt_0_; - assign n1400 = n1328 & pksi_31_ & ~pstart_0_ & ~pencrypt_0_; - assign n1401 = ~n1327_1 & pksi_54_ & ~pstart_0_ & pencrypt_0_; - assign n1402_1 = ~n1328 & pksi_64_ & ~pstart_0_ & ~pencrypt_0_; - assign n1403 = n1328 & pksi_68_ & ~pstart_0_ & ~pencrypt_0_; - assign n1404 = ~n1327_1 & pksi_95_ & ~pstart_0_ & pencrypt_0_; - assign n1405 = ~n1328 & pksi_91_ & ~pstart_0_ & ~pencrypt_0_; - assign n1406 = n1328 & pksi_89_ & ~pstart_0_ & ~pencrypt_0_; - assign n1407_1 = ~n1327_1 & pksi_74_ & ~pstart_0_ & pencrypt_0_; - assign n1408 = ~n1328 & pksi_21_ & ~pstart_0_ & ~pencrypt_0_; - assign n1409 = n1328 & pksi_10_ & ~pstart_0_ & ~pencrypt_0_; - assign n1410 = ~n1327_1 & pksi_3_ & ~pstart_0_ & pencrypt_0_; - assign n1411_1 = ~n1328 & pksi_12_ & ~pstart_0_ & ~pencrypt_0_; - assign n1412 = n1328 & pksi_3_ & ~pstart_0_ & ~pencrypt_0_; - assign n1413 = ~n1327_1 & pksi_20_ & ~pstart_0_ & pencrypt_0_; - assign n1414 = ~n1328 & pksi_33_ & ~pstart_0_ & ~pencrypt_0_; - assign n1415_1 = n1328 & pksi_43_ & ~pstart_0_ & ~pencrypt_0_; - assign n1416 = ~n1327_1 & pksi_35_ & ~pstart_0_ & pencrypt_0_; - assign n1417 = n1328 & n_n2342 & ~pstart_0_ & ~pencrypt_0_; - assign n1418 = ~n1328 & pksi_25_ & ~pstart_0_ & ~pencrypt_0_; - assign n1419_1 = ~n1327_1 & pksi_34_ & ~pstart_0_ & pencrypt_0_; - assign n1420 = ~n1328 & pksi_31_ & ~pstart_0_ & ~pencrypt_0_; - assign n1421 = n1328 & pksi_52_ & ~pstart_0_ & ~pencrypt_0_; - assign n1422 = ~n1327_1 & pksi_63_ & ~pstart_0_ & pencrypt_0_; - assign n1423_1 = ~n1328 & n_n2301 & ~pstart_0_ & ~pencrypt_0_; - assign n1424 = n1328 & pksi_64_ & ~pstart_0_ & ~pencrypt_0_; - assign n1425 = ~n1327_1 & pksi_76_ & ~pstart_0_ & pencrypt_0_; - assign n1426 = ~n1328 & pksi_89_ & ~pstart_0_ & ~pencrypt_0_; - assign n1427_1 = n1328 & n_n2288 & ~pstart_0_ & ~pencrypt_0_; - assign n1428 = ~n1327_1 & pksi_86_ & ~pstart_0_ & pencrypt_0_; - assign n1429 = ~n1328 & n_n2369 & ~pstart_0_ & ~pencrypt_0_; - assign n1430 = n1328 & pksi_12_ & ~pstart_0_ & ~pencrypt_0_; - assign n1431 = ~n1327_1 & pksi_16_ & ~pstart_0_ & pencrypt_0_; - assign n1432_1 = ~n1328 & pksi_30_ & ~pstart_0_ & ~pencrypt_0_; - assign n1433 = n1328 & pksi_39_ & ~pstart_0_ & ~pencrypt_0_; - assign n1434 = ~n1327_1 & pksi_43_ & ~pstart_0_ & pencrypt_0_; - assign n1435 = ~n1328 & pksi_59_ & ~pstart_0_ & ~pencrypt_0_; - assign n1436_1 = n1328 & pksi_50_ & ~pstart_0_ & ~pencrypt_0_; - assign n1437 = ~n1327_1 & pksi_48_ & ~pstart_0_ & pencrypt_0_; - assign n1438 = ~n1328 & pksi_61_ & ~pstart_0_ & ~pencrypt_0_; - assign n1439 = n1328 & pksi_69_ & ~pstart_0_ & ~pencrypt_0_; - assign n1440_1 = ~n1327_1 & pksi_60_ & ~pstart_0_ & pencrypt_0_; - assign n1441 = ~n1328 & pksi_55_ & ~pstart_0_ & ~pencrypt_0_; - assign n1442 = n1328 & pksi_76_ & ~pstart_0_ & ~pencrypt_0_; - assign n1443 = ~n1327_1 & pksi_87_ & ~pstart_0_ & pencrypt_0_; - assign n1444_1 = ~n1328 & n_n2288 & ~pstart_0_ & ~pencrypt_0_; - assign n1445 = n1328 & pksi_83_ & ~pstart_0_ & ~pencrypt_0_; - assign n1446 = ~n1327_1 & pksi_94_ & ~pstart_0_ & pencrypt_0_; - assign n1447 = n1328 & n_n2369 & ~pstart_0_ & ~pencrypt_0_; - assign n1448_1 = ~n1328 & pksi_10_ & ~pstart_0_ & ~pencrypt_0_; - assign n1449 = n1327_1 & pksi_3_ & ~pstart_0_ & pencrypt_0_; - assign n1450 = ~n1328 & pksi_39_ & ~pstart_0_ & ~pencrypt_0_; - assign n1451 = n1328 & pksi_29_ & ~pstart_0_ & ~pencrypt_0_; - assign n1452_1 = ~n1327_1 & pksi_41_ & ~pstart_0_ & pencrypt_0_; - assign n1453 = ~n1328 & n_n2320 & ~pstart_0_ & ~pencrypt_0_; - assign n1454 = n1328 & pksi_59_ & ~pstart_0_ & ~pencrypt_0_; - assign n1455 = ~n1327_1 & pksi_70_ & ~pstart_0_ & pencrypt_0_; - assign n1456_1 = ~n1328 & pksi_69_ & ~pstart_0_ & ~pencrypt_0_; - assign n1457 = n1328 & pksi_58_ & ~pstart_0_ & ~pencrypt_0_; - assign n1458 = ~n1327_1 & pksi_51_ & ~pstart_0_ & pencrypt_0_; - assign n1459 = ~n1328 & pksi_68_ & ~pstart_0_ & ~pencrypt_0_; - assign n1460_1 = n1328 & pksi_55_ & ~pstart_0_ & ~pencrypt_0_; - assign n1461 = ~n1327_1 & pksi_78_ & ~pstart_0_ & pencrypt_0_; - assign n1462 = ~n1328 & pksi_83_ & ~pstart_0_ & ~pencrypt_0_; - assign n1463 = n1328 & pksi_74_ & ~pstart_0_ & ~pencrypt_0_; - assign n1464_1 = ~n1327_1 & pksi_72_ & ~pstart_0_ & pencrypt_0_; - assign n1465 = ~n1328 & pksi_24_ & ~pstart_0_ & ~pencrypt_0_; - assign n1466 = n1327_1 & pksi_25_ & ~pstart_0_ & pencrypt_0_; - assign n1467 = n1328 & pksi_32_ & ~pstart_0_ & ~pencrypt_0_; - assign n1468_1 = ~n1328 & pksi_36_ & ~pstart_0_ & ~pencrypt_0_; - assign n1469 = n1328 & pksi_27_ & ~pstart_0_ & ~pencrypt_0_; - assign n1470 = ~n1327_1 & pksi_44_ & ~pstart_0_ & pencrypt_0_; - assign n1471 = n1328 & n_n2320 & ~pstart_0_ & ~pencrypt_0_; - assign n1472_1 = ~n1328 & pksi_65_ & ~pstart_0_ & ~pencrypt_0_; - assign n1473 = ~n1327_1 & pksi_62_ & ~pstart_0_ & pencrypt_0_; - assign n1474 = ~n1328 & pksi_49_ & ~pstart_0_ & ~pencrypt_0_; - assign n1475 = n1328 & n_n2310 & ~pstart_0_ & ~pencrypt_0_; - assign n1476_1 = ~n1327_1 & pksi_58_ & ~pstart_0_ & pencrypt_0_; - assign n1477 = ~n1328 & pksi_95_ & ~pstart_0_ & ~pencrypt_0_; - assign n1478 = n1328 & pksi_78_ & ~pstart_0_ & ~pencrypt_0_; - assign n1479 = ~n1327_1 & pksi_81_ & ~pstart_0_ & pencrypt_0_; - assign n1480_1 = ~n1328 & pksi_74_ & ~pstart_0_ & ~pencrypt_0_; - assign n1481 = n1328 & pksi_86_ & ~pstart_0_ & ~pencrypt_0_; - assign n1482 = ~n1327_1 & pksi_80_ & ~pstart_0_ & pencrypt_0_; - assign n1483 = ~n1328 & pksi_46_ & ~pstart_0_ & ~pencrypt_0_; - assign n1484 = n1328 & pksi_24_ & ~pstart_0_ & ~pencrypt_0_; - assign n1485_1 = ~n1327_1 & pksi_25_ & ~pstart_0_ & pencrypt_0_; - assign n1486 = n1328 & n_n2333 & ~pstart_0_ & ~pencrypt_0_; - assign n1487 = ~n1328 & pksi_27_ & ~pstart_0_ & ~pencrypt_0_; - assign n1488 = ~n1327_1 & pksi_31_ & ~pstart_0_ & pencrypt_0_; - assign n1489_1 = ~n1328 & pksi_67_ & ~pstart_0_ & ~pencrypt_0_; - assign n1490 = n1328 & pksi_65_ & ~pstart_0_ & ~pencrypt_0_; - assign n1491 = ~n1327_1 & pksi_50_ & ~pstart_0_ & pencrypt_0_; - assign n1492 = ~n1328 & n_n2310 & ~pstart_0_ & ~pencrypt_0_; - assign n1493_1 = ~n1327_1 & n_n2305 & ~pstart_0_ & pencrypt_0_; - assign n1494 = n1328 & pksi_61_ & ~pstart_0_ & ~pencrypt_0_; - assign n1495 = ~n1328 & pksi_76_ & ~pstart_0_ & ~pencrypt_0_; - assign n1496 = n1328 & pksi_95_ & ~pstart_0_ & ~pencrypt_0_; - assign n1497_1 = ~n1327_1 & pksi_77_ & ~pstart_0_ & pencrypt_0_; - assign n1498 = ~n1328 & pksi_86_ & ~pstart_0_ & ~pencrypt_0_; - assign n1499 = ~n1327_1 & n_n2280 & ~pstart_0_ & pencrypt_0_; - assign n1500 = n1328 & pksi_94_ & ~pstart_0_ & ~pencrypt_0_; - assign n1501 = ~n1328 & pksi_48_ & ~pstart_0_ & ~pencrypt_0_; - assign n1502_1 = n1328 & pksi_56_ & ~pstart_0_ & ~pencrypt_0_; - assign n1503 = ~n1327_1 & n_n2310 & ~pstart_0_ & pencrypt_0_; - assign n1504 = ~n1328 & pksi_60_ & ~pstart_0_ & ~pencrypt_0_; - assign n1505 = n1328 & pksi_51_ & ~pstart_0_ & ~pencrypt_0_; - assign n1506_1 = ~n1327_1 & pksi_68_ & ~pstart_0_ & pencrypt_0_; - assign n1507 = ~n1328 & pksi_87_ & ~pstart_0_ & ~pencrypt_0_; - assign n1508 = n1328 & pksi_77_ & ~pstart_0_ & ~pencrypt_0_; - assign n1509 = ~n1327_1 & pksi_89_ & ~pstart_0_ & pencrypt_0_; - assign n1510_1 = ~n1328 & pksi_94_ & ~pstart_0_ & ~pencrypt_0_; - assign n1511 = n1328 & pksi_72_ & ~pstart_0_ & ~pencrypt_0_; - assign n1512 = ~n1327_1 & pksi_73_ & ~pstart_0_ & pencrypt_0_; - assign n1513 = ~n1328 & pksi_70_ & ~pstart_0_ & ~pencrypt_0_; - assign n1514_1 = n1328 & pksi_48_ & ~pstart_0_ & ~pencrypt_0_; - assign n1515 = ~n1327_1 & pksi_49_ & ~pstart_0_ & pencrypt_0_; - assign n1516 = ~n1328 & pksi_51_ & ~pstart_0_ & ~pencrypt_0_; - assign n1517 = n1328 & n_n2301 & ~pstart_0_ & ~pencrypt_0_; - assign n1518_1 = ~n1327_1 & pksi_55_ & ~pstart_0_ & pencrypt_0_; - assign n1519 = ~n1328 & pksi_78_ & ~pstart_0_ & ~pencrypt_0_; - assign n1520 = n1328 & pksi_87_ & ~pstart_0_ & ~pencrypt_0_; - assign n1521 = ~n1327_1 & pksi_91_ & ~pstart_0_ & pencrypt_0_; - assign n1522_1 = ~n1328 & pksi_72_ & ~pstart_0_ & ~pencrypt_0_; - assign n1523 = n1327_1 & pksi_73_ & ~pstart_0_ & pencrypt_0_; - assign n1524 = n1328 & pksi_80_ & ~pstart_0_ & ~pencrypt_0_; - assign n1525 = ~n1328 & pksi_2_ & ~pstart_0_ & ~pencrypt_0_; - assign n1526_1 = n1328 & pksi_14_ & ~pstart_0_ & ~pencrypt_0_; - assign n1527 = ~n1327_1 & pksi_8_ & ~pstart_0_ & pencrypt_0_; - assign n1528 = ~n1328 & pksi_62_ & ~pstart_0_ & ~pencrypt_0_; - assign n1529 = n1328 & pksi_70_ & ~pstart_0_ & ~pencrypt_0_; - assign n1530_1 = ~n1327_1 & pksi_66_ & ~pstart_0_ & pencrypt_0_; - assign n1531 = ~n1328 & pksi_58_ & ~pstart_0_ & ~pencrypt_0_; - assign n1532 = n1328 & n_n2305 & ~pstart_0_ & ~pencrypt_0_; - assign n1533 = ~n1327_1 & n_n2301 & ~pstart_0_ & pencrypt_0_; - assign n1534_1 = ~n1328 & pksi_81_ & ~pstart_0_ & ~pencrypt_0_; - assign n1535 = n1328 & pksi_91_ & ~pstart_0_ & ~pencrypt_0_; - assign n1536 = ~n1327_1 & pksi_83_ & ~pstart_0_ & pencrypt_0_; - assign n1537 = ~n1328 & pksi_80_ & ~pstart_0_ & ~pencrypt_0_; - assign n1538_1 = n1328 & n_n2280 & ~pstart_0_ & ~pencrypt_0_; - assign n1539 = ~n1327_1 & pksi_85_ & ~pstart_0_ & pencrypt_0_; - assign n1540 = ~n1328 & pksi_14_ & ~pstart_0_ & ~pencrypt_0_; - assign n1541 = n1328 & pksi_22_ & ~pstart_0_ & ~pencrypt_0_; - assign n1542 = ~n1327_1 & pksi_18_ & ~pstart_0_ & pencrypt_0_; - assign n1543_1 = ~n1328 & pksi_50_ & ~pstart_0_ & ~pencrypt_0_; - assign n1544 = n1328 & pksi_62_ & ~pstart_0_ & ~pencrypt_0_; - assign n1545 = ~n1327_1 & pksi_56_ & ~pstart_0_ & pencrypt_0_; - assign n1546 = ~n1328 & n_n2305 & ~pstart_0_ & ~pencrypt_0_; - assign n1547_1 = n1328 & pksi_60_ & ~pstart_0_ & ~pencrypt_0_; - assign n1548 = ~n1327_1 & pksi_64_ & ~pstart_0_ & pencrypt_0_; - assign n1549 = ~n1328 & pksi_77_ & ~pstart_0_ & ~pencrypt_0_; - assign n1550 = n1328 & pksi_81_ & ~pstart_0_ & ~pencrypt_0_; - assign n1551_1 = ~n1327_1 & n_n2288 & ~pstart_0_ & pencrypt_0_; - assign n1552 = ~n1328 & n_n2280 & ~pstart_0_ & ~pencrypt_0_; - assign n1553 = n1328 & pksi_73_ & ~pstart_0_ & ~pencrypt_0_; - assign n1554 = ~n1327_1 & pksi_93_ & ~pstart_0_ & pencrypt_0_; - assign n1555_1 = ~n1328 & pksi_22_ & ~pstart_0_ & ~pencrypt_0_; - assign n1556 = n1328 & pksi_0_ & ~pstart_0_ & ~pencrypt_0_; - assign n1557 = ~n1327_1 & pksi_1_ & ~pstart_0_ & pencrypt_0_; - assign n1558 = ~n1328 & pksi_47_ & ~pstart_0_ & ~pencrypt_0_; - assign n1559_1 = n1328 & pksi_30_ & ~pstart_0_ & ~pencrypt_0_; - assign n1560 = ~n1327_1 & pksi_33_ & ~pstart_0_ & pencrypt_0_; - assign n1561 = ~n1328 & pksi_26_ & ~pstart_0_ & ~pencrypt_0_; - assign n1562 = n1328 & pksi_38_ & ~pstart_0_ & ~pencrypt_0_; - assign n1563_1 = ~n1327_1 & pksi_32_ & ~pstart_0_ & pencrypt_0_; - assign n1564 = ~n1328 & pksi_45_ & ~pstart_0_ & ~pencrypt_0_; - assign n1565 = n1328 & pksi_34_ & ~pstart_0_ & ~pencrypt_0_; - assign n1566 = ~n1327_1 & pksi_27_ & ~pstart_0_ & pencrypt_0_; - assign n1567 = ~n1328 & pksi_52_ & ~pstart_0_ & ~pencrypt_0_; - assign n1568_1 = n1328 & pksi_71_ & ~pstart_0_ & ~pencrypt_0_; - assign n1569 = ~n1327_1 & pksi_53_ & ~pstart_0_ & pencrypt_0_; - assign n1570 = ~n1328 & n_n10 & ~pstart_0_ & ~pencrypt_0_; - assign n1571 = n1328 & pksi_92_ & ~pstart_0_ & ~pencrypt_0_; - assign n1572_1 = ~n1327_1 & pksi_23_ & ~pstart_0_ & pencrypt_0_; - assign n1573 = ~n1328 & pksi_0_ & ~pstart_0_ & ~pencrypt_0_; - assign n1574 = n1327_1 & pksi_1_ & ~pstart_0_ & pencrypt_0_; - assign n1575 = n1328 & pksi_8_ & ~pstart_0_ & ~pencrypt_0_; - assign n1576_1 = ~n1328 & pksi_28_ & ~pstart_0_ & ~pencrypt_0_; - assign n1577 = n1328 & pksi_47_ & ~pstart_0_ & ~pencrypt_0_; - assign n1578 = ~n1327_1 & pksi_29_ & ~pstart_0_ & pencrypt_0_; - assign n1579 = ~n1328 & pksi_38_ & ~pstart_0_ & ~pencrypt_0_; - assign n1580_1 = n1328 & pksi_46_ & ~pstart_0_ & ~pencrypt_0_; - assign n1581 = ~n1327_1 & pksi_42_ & ~pstart_0_ & pencrypt_0_; - assign n1582 = ~n1328 & pksi_37_ & ~pstart_0_ & ~pencrypt_0_; - assign n1583 = n1328 & pksi_45_ & ~pstart_0_ & ~pencrypt_0_; - assign n1584_1 = ~n1327_1 & pksi_36_ & ~pstart_0_ & pencrypt_0_; - assign n1585 = ~n1328 & pksi_71_ & ~pstart_0_ & ~pencrypt_0_; - assign n1586 = n1328 & pksi_54_ & ~pstart_0_ & ~pencrypt_0_; - assign n1587 = ~n1327_1 & pksi_57_ & ~pstart_0_ & pencrypt_0_; - assign n1588 = ~n1328 & pksi_8_ & ~pstart_0_ & ~pencrypt_0_; - assign n1589_1 = n1328 & pksi_18_ & ~pstart_0_ & ~pencrypt_0_; - assign n1590 = ~n1327_1 & pksi_13_ & ~pstart_0_ & pencrypt_0_; - assign n1591 = ~n1328 & pksi_7_ & ~pstart_0_ & ~pencrypt_0_; - assign n1592 = n1328 & pksi_28_ & ~pstart_0_ & ~pencrypt_0_; - assign n1593_1 = ~n1327_1 & pksi_39_ & ~pstart_0_ & pencrypt_0_; - assign n1594 = ~n1328 & n_n2352 & ~pstart_0_ & ~pencrypt_0_; - assign n1595 = n1328 & pksi_35_ & ~pstart_0_ & ~pencrypt_0_; - assign n1596 = ~n1327_1 & pksi_46_ & ~pstart_0_ & pencrypt_0_; - assign n1597_1 = ~n1328 & n_n2337 & ~pstart_0_ & ~pencrypt_0_; - assign n1598 = n1328 & pksi_36_ & ~pstart_0_ & ~pencrypt_0_; - assign n1599 = ~n1327_1 & pksi_40_ & ~pstart_0_ & pencrypt_0_; - assign n1600 = ~n1328 & pksi_54_ & ~pstart_0_ & ~pencrypt_0_; - assign n1601_1 = n1328 & pksi_63_ & ~pstart_0_ & ~pencrypt_0_; - assign n1602 = ~n1327_1 & pksi_67_ & ~pstart_0_ & pencrypt_0_; - assign n1603 = ~n1328 & pksi_18_ & ~pstart_0_ & ~pencrypt_0_; - assign n1604 = n1328 & pksi_1_ & ~pstart_0_ & ~pencrypt_0_; - assign n1605_1 = ~n1327_1 & pksi_21_ & ~pstart_0_ & pencrypt_0_; - assign n1606 = ~n1328 & pksi_20_ & ~pstart_0_ & ~pencrypt_0_; - assign n1607 = n1328 & pksi_7_ & ~pstart_0_ & ~pencrypt_0_; - assign n1608 = ~n1327_1 & pksi_30_ & ~pstart_0_ & pencrypt_0_; - assign n1609_1 = ~n1328 & pksi_35_ & ~pstart_0_ & ~pencrypt_0_; - assign n1610 = n1328 & pksi_26_ & ~pstart_0_ & ~pencrypt_0_; - assign n1611 = ~n1327_1 & pksi_24_ & ~pstart_0_ & pencrypt_0_; - assign n1612 = n1328 & n_n2337 & ~pstart_0_ & ~pencrypt_0_; - assign n1613_1 = ~n1328 & pksi_34_ & ~pstart_0_ & ~pencrypt_0_; - assign n1614 = n1327_1 & pksi_27_ & ~pstart_0_ & pencrypt_0_; - assign n1615 = ~n1328 & pksi_63_ & ~pstart_0_ & ~pencrypt_0_; - assign n1616 = n1328 & pksi_53_ & ~pstart_0_ & ~pencrypt_0_; - assign n1617 = ~n1327_1 & pksi_65_ & ~pstart_0_ & pencrypt_0_; - assign n1618_1 = ~n1328 & pksi_98_ & ~pstart_0_ & ~pencrypt_0_; - assign n1619 = n1327_1 & pksi_112_ & ~pstart_0_ & pencrypt_0_; - assign n1620 = n1328 & pksi_119_ & ~pstart_0_ & ~pencrypt_0_; - assign n1621 = ~n1328 & pksi_126_ & ~pstart_0_ & ~pencrypt_0_; - assign n1622_1 = n1328 & pksi_122_ & ~pstart_0_ & ~pencrypt_0_; - assign n1623 = ~n1327_1 & pksi_136_ & ~pstart_0_ & pencrypt_0_; - assign n1624 = ~n1328 & pksi_134_ & ~pstart_0_ & ~pencrypt_0_; - assign n1625 = n1327_1 & n_n2476 & ~pstart_0_ & pencrypt_0_; - assign n1626_1 = n1328 & pksi_127_ & ~pstart_0_ & ~pencrypt_0_; - assign n1627 = ~n1328 & pksi_131_ & ~pstart_0_ & ~pencrypt_0_; - assign n1628 = n1328 & pksi_133_ & ~pstart_0_ & ~pencrypt_0_; - assign n1629 = ~n1327_1 & pksi_121_ & ~pstart_0_ & pencrypt_0_; - assign n1630_1 = ~n1328 & pksi_166_ & ~pstart_0_ & ~pencrypt_0_; - assign n1631 = n1328 & pksi_150_ & ~pstart_0_ & ~pencrypt_0_; - assign n1632 = ~n1327_1 & pksi_154_ & ~pstart_0_ & pencrypt_0_; - assign n1633 = ~n1328 & n_n2448 & ~pstart_0_ & ~pencrypt_0_; - assign n1634 = n1328 & pksi_158_ & ~pstart_0_ & ~pencrypt_0_; - assign n1635_1 = ~n1327_1 & pksi_163_ & ~pstart_0_ & pencrypt_0_; - assign n1636 = ~n1328 & pksi_148_ & ~pstart_0_ & ~pencrypt_0_; - assign n1637 = n1328 & pksi_155_ & ~pstart_0_ & ~pencrypt_0_; - assign n1638 = ~n1327_1 & pksi_152_ & ~pstart_0_ & pencrypt_0_; - assign n1639_1 = ~n1328 & pksi_159_ & ~pstart_0_ & ~pencrypt_0_; - assign n1640 = n1328 & pksi_190_ & ~pstart_0_ & ~pencrypt_0_; - assign n1641 = ~n1327_1 & n_n121 & ~pstart_0_ & pencrypt_0_; - assign n1642 = ~n1328 & pksi_171_ & ~pstart_0_ & ~pencrypt_0_; - assign n1643_1 = n1328 & n_n2416 & ~pstart_0_ & ~pencrypt_0_; - assign n1644 = ~n1327_1 & n_n2412 & ~pstart_0_ & pencrypt_0_; - assign n1645 = ~n1328 & n_n2272 & ~pstart_0_ & ~pencrypt_0_; - assign n1646 = n1328 & pksi_84_ & ~pstart_0_ & ~pencrypt_0_; - assign n1647_1 = ~n1327_1 & n_n10 & ~pstart_0_ & pencrypt_0_; - assign n1648 = ~n1328 & pksi_96_ & ~pstart_0_ & ~pencrypt_0_; - assign n1649 = n1328 & pksi_115_ & ~pstart_0_ & ~pencrypt_0_; - assign n1650 = ~n1327_1 & pksi_105_ & ~pstart_0_ & pencrypt_0_; - assign n1651_1 = ~n1328 & pksi_142_ & ~pstart_0_ & ~pencrypt_0_; - assign n1652 = n1328 & pksi_126_ & ~pstart_0_ & ~pencrypt_0_; - assign n1653 = ~n1327_1 & pksi_130_ & ~pstart_0_ & pencrypt_0_; - assign n1654 = ~n1328 & pksi_127_ & ~pstart_0_ & ~pencrypt_0_; - assign n1655_1 = n1328 & pksi_120_ & ~pstart_0_ & ~pencrypt_0_; - assign n1656 = ~n1327_1 & pksi_132_ & ~pstart_0_ & pencrypt_0_; - assign n1657 = ~n1328 & pksi_124_ & ~pstart_0_ & ~pencrypt_0_; - assign n1658 = n1328 & pksi_131_ & ~pstart_0_ & ~pencrypt_0_; - assign n1659_1 = ~n1327_1 & pksi_128_ & ~pstart_0_ & pencrypt_0_; - assign n1660 = ~n1328 & pksi_150_ & ~pstart_0_ & ~pencrypt_0_; - assign n1661 = n1328 & pksi_146_ & ~pstart_0_ & ~pencrypt_0_; - assign n1662 = ~n1327_1 & pksi_160_ & ~pstart_0_ & pencrypt_0_; - assign n1663_1 = ~n1328 & pksi_147_ & ~pstart_0_ & ~pencrypt_0_; - assign n1664 = n1328 & n_n2448 & ~pstart_0_ & ~pencrypt_0_; - assign n1665 = ~n1327_1 & pksi_144_ & ~pstart_0_ & pencrypt_0_; - assign n1666 = ~n1328 & pksi_155_ & ~pstart_0_ & ~pencrypt_0_; - assign n1667_1 = n1328 & pksi_157_ & ~pstart_0_ & ~pencrypt_0_; - assign n1668 = ~n1327_1 & pksi_145_ & ~pstart_0_ & pencrypt_0_; - assign n1669 = ~n1328 & pksi_149_ & ~pstart_0_ & ~pencrypt_0_; - assign n1670 = n1328 & pksi_159_ & ~pstart_0_ & ~pencrypt_0_; - assign n1671_1 = ~n1327_1 & pksi_170_ & ~pstart_0_ & pencrypt_0_; - assign n1672 = ~n1328 & n_n2416 & ~pstart_0_ & ~pencrypt_0_; - assign n1673 = n1328 & pksi_182_ & ~pstart_0_ & ~pencrypt_0_; - assign n1674 = ~n1327_1 & n_n2410 & ~pstart_0_ & pencrypt_0_; - assign n1675_1 = ~n1328 & pksi_84_ & ~pstart_0_ & ~pencrypt_0_; - assign n1676 = n1328 & pksi_75_ & ~pstart_0_ & ~pencrypt_0_; - assign n1677 = ~n1327_1 & pksi_92_ & ~pstart_0_ & pencrypt_0_; - assign n1678 = ~n1328 & pksi_106_ & ~pstart_0_ & ~pencrypt_0_; - assign n1679_1 = n1328 & pksi_112_ & ~pstart_0_ & ~pencrypt_0_; - assign n1680 = ~n1327_1 & pksi_99_ & ~pstart_0_ & pencrypt_0_; - assign n1681 = ~n1328 & pksi_115_ & ~pstart_0_ & ~pencrypt_0_; - assign n1682 = n1328 & n_n2507 & ~pstart_0_ & ~pencrypt_0_; - assign n1683_1 = ~n1327_1 & pksi_114_ & ~pstart_0_ & pencrypt_0_; - assign n1684 = ~n1328 & n_n168 & ~pstart_0_ & ~pencrypt_0_; - assign n1685 = n1328 & pksi_130_ & ~pstart_0_ & ~pencrypt_0_; - assign n1686 = ~n1327_1 & pksi_141_ & ~pstart_0_ & pencrypt_0_; - assign n1687_1 = ~n1328 & pksi_120_ & ~pstart_0_ & ~pencrypt_0_; - assign n1688 = n1328 & n_n2476 & ~pstart_0_ & ~pencrypt_0_; - assign n1689 = ~n1327_1 & pksi_129_ & ~pstart_0_ & pencrypt_0_; - assign n1690 = ~n1328 & pksi_138_ & ~pstart_0_ & ~pencrypt_0_; - assign n1691_1 = n1328 & pksi_124_ & ~pstart_0_ & ~pencrypt_0_; - assign n1692 = ~n1327_1 & pksi_140_ & ~pstart_0_ & pencrypt_0_; - assign n1693 = ~n1328 & pksi_125_ & ~pstart_0_ & ~pencrypt_0_; - assign n1694 = n1328 & pksi_135_ & ~pstart_0_ & ~pencrypt_0_; - assign n1695 = ~n1327_1 & pksi_146_ & ~pstart_0_ & pencrypt_0_; - assign n1696_1 = ~n1328 & pksi_151_ & ~pstart_0_ & ~pencrypt_0_; - assign n1697 = n1328 & pksi_144_ & ~pstart_0_ & ~pencrypt_0_; - assign n1698 = ~n1327_1 & pksi_156_ & ~pstart_0_ & pencrypt_0_; - assign n1699 = ~n1328 & pksi_157_ & ~pstart_0_ & ~pencrypt_0_; - assign n1700 = n1328 & pksi_164_ & ~pstart_0_ & ~pencrypt_0_; - assign n1701_1 = ~n1327_1 & pksi_161_ & ~pstart_0_ & pencrypt_0_; - assign n1702 = ~n1328 & pksi_179_ & ~pstart_0_ & ~pencrypt_0_; - assign n1703 = n1328 & n_n109 & ~pstart_0_ & ~pencrypt_0_; - assign n1704 = ~n1327_1 & pksi_169_ & ~pstart_0_ & pencrypt_0_; - assign n1705 = ~n1328 & pksi_4_ & ~pstart_0_ & ~pencrypt_0_; - assign n1706_1 = n1328 & pksi_23_ & ~pstart_0_ & ~pencrypt_0_; - assign n1707 = ~n1327_1 & pksi_5_ & ~pstart_0_ & pencrypt_0_; - assign n1708 = n1328 & n_n2268 & ~pstart_0_ & ~pencrypt_0_; - assign n1709 = ~n1328 & pksi_75_ & ~pstart_0_ & ~pencrypt_0_; - assign n1710_1 = ~n1327_1 & pksi_79_ & ~pstart_0_ & pencrypt_0_; - assign n1711 = ~n1328 & pksi_119_ & ~pstart_0_ & ~pencrypt_0_; - assign n1712 = n1328 & pksi_106_ & ~pstart_0_ & ~pencrypt_0_; - assign n1713 = ~n1327_1 & pksi_117_ & ~pstart_0_ & pencrypt_0_; - assign n1714_1 = ~n1328 & n_n2507 & ~pstart_0_ & ~pencrypt_0_; - assign n1715 = n1328 & pksi_108_ & ~pstart_0_ & ~pencrypt_0_; - assign n1716 = ~n1327_1 & pksi_100_ & ~pstart_0_ & pencrypt_0_; - assign n1717 = ~n1328 & pksi_122_ & ~pstart_0_ & ~pencrypt_0_; - assign n1718_1 = ~n1327_1 & n_n2485 & ~pstart_0_ & pencrypt_0_; - assign n1719 = n1328 & n_n168 & ~pstart_0_ & ~pencrypt_0_; - assign n1720 = n1328 & n_n2474 & ~pstart_0_ & ~pencrypt_0_; - assign n1721 = ~n1328 & n_n2476 & ~pstart_0_ & ~pencrypt_0_; - assign n1722_1 = ~n1327_1 & pksi_138_ & ~pstart_0_ & pencrypt_0_; - assign n1723 = ~n1328 & pksi_129_ & ~pstart_0_ & ~pencrypt_0_; - assign n1724 = n1328 & pksi_138_ & ~pstart_0_ & ~pencrypt_0_; - assign n1725 = ~n1327_1 & pksi_133_ & ~pstart_0_ & pencrypt_0_; - assign n1726_1 = ~n1328 & pksi_135_ & ~pstart_0_ & ~pencrypt_0_; - assign n1727 = n1328 & pksi_166_ & ~pstart_0_ & ~pencrypt_0_; - assign n1728 = ~n1327_1 & pksi_167_ & ~pstart_0_ & pencrypt_0_; - assign n1729 = ~n1328 & pksi_158_ & ~pstart_0_ & ~pencrypt_0_; - assign n1730_1 = n1328 & pksi_151_ & ~pstart_0_ & ~pencrypt_0_; - assign n1731 = ~n1327_1 & pksi_153_ & ~pstart_0_ & pencrypt_0_; - assign n1732 = ~n1328 & pksi_164_ & ~pstart_0_ & ~pencrypt_0_; - assign n1733 = n1327_1 & pksi_161_ & ~pstart_0_ & pencrypt_0_; - assign n1734 = n1328 & pksi_152_ & ~pstart_0_ & ~pencrypt_0_; - assign n1735_1 = ~n1328 & pksi_172_ & ~pstart_0_ & ~pencrypt_0_; - assign n1736 = n1328 & pksi_179_ & ~pstart_0_ & ~pencrypt_0_; - assign n1737 = ~n1327_1 & pksi_176_ & ~pstart_0_ & pencrypt_0_; - assign n1738 = ~n1328 & pksi_23_ & ~pstart_0_ & ~pencrypt_0_; - assign n1739_1 = n1328 & pksi_6_ & ~pstart_0_ & ~pencrypt_0_; - assign n1740 = ~n1327_1 & pksi_9_ & ~pstart_0_ & pencrypt_0_; - assign n1741 = ~n1328 & n_n2268 & ~pstart_0_ & ~pencrypt_0_; - assign n1742 = n1328 & n_n10 & ~pstart_0_ & ~pencrypt_0_; - assign n1743_1 = ~n1327_1 & pksi_4_ & ~pstart_0_ & pencrypt_0_; - assign n1744 = ~n1328 & n_n2495 & ~pstart_0_ & ~pencrypt_0_; - assign n1745 = n1328 & pksi_101_ & ~pstart_0_ & ~pencrypt_0_; - assign n1746 = ~n1327_1 & pksi_126_ & ~pstart_0_ & pencrypt_0_; - assign n1747_1 = ~n1328 & n_n2485 & ~pstart_0_ & ~pencrypt_0_; - assign n1748 = n1328 & pksi_141_ & ~pstart_0_ & ~pencrypt_0_; - assign n1749 = ~n1327_1 & pksi_134_ & ~pstart_0_ & pencrypt_0_; - assign n1750 = ~n1328 & pksi_121_ & ~pstart_0_ & ~pencrypt_0_; - assign n1751_1 = n1328 & pksi_137_ & ~pstart_0_ & ~pencrypt_0_; - assign n1752 = ~n1327_1 & pksi_135_ & ~pstart_0_ & pencrypt_0_; - assign n1753 = ~n1328 & pksi_154_ & ~pstart_0_ & ~pencrypt_0_; - assign n1754 = n1328 & pksi_160_ & ~pstart_0_ & ~pencrypt_0_; - assign n1755_1 = ~n1327_1 & pksi_147_ & ~pstart_0_ & pencrypt_0_; - assign n1756 = ~n1328 & pksi_163_ & ~pstart_0_ & ~pencrypt_0_; - assign n1757 = n1328 & pksi_153_ & ~pstart_0_ & ~pencrypt_0_; - assign n1758 = ~n1327_1 & pksi_162_ & ~pstart_0_ & pencrypt_0_; - assign n1759_1 = ~n1328 & pksi_152_ & ~pstart_0_ & ~pencrypt_0_; - assign n1760 = n1328 & pksi_145_ & ~pstart_0_ & ~pencrypt_0_; - assign n1761 = ~n1327_1 & pksi_149_ & ~pstart_0_ & pencrypt_0_; - assign n1762 = ~n1328 & n_n2277 & ~pstart_0_ & ~pencrypt_0_; - assign n1763_1 = ~n1327_1 & n_n2272 & ~pstart_0_ & pencrypt_0_; - assign n1764 = n1328 & pksi_85_ & ~pstart_0_ & ~pencrypt_0_; - assign n1765 = ~n1328 & pksi_113_ & ~pstart_0_ & ~pencrypt_0_; - assign n1766 = n1328 & n_n2495 & ~pstart_0_ & ~pencrypt_0_; - assign n1767_1 = ~n1327_1 & pksi_142_ & ~pstart_0_ & pencrypt_0_; - assign n1768 = ~n1328 & pksi_141_ & ~pstart_0_ & ~pencrypt_0_; - assign n1769 = n1328 & pksi_123_ & ~pstart_0_ & ~pencrypt_0_; - assign n1770 = ~n1327_1 & pksi_127_ & ~pstart_0_ & pencrypt_0_; - assign n1771_1 = ~n1328 & pksi_128_ & ~pstart_0_ & ~pencrypt_0_; - assign n1772 = n1328 & pksi_121_ & ~pstart_0_ & ~pencrypt_0_; - assign n1773 = ~n1327_1 & pksi_125_ & ~pstart_0_ & pencrypt_0_; - assign n1774 = n1328 & n_n2452 & ~pstart_0_ & ~pencrypt_0_; - assign n1775 = ~n1328 & pksi_160_ & ~pstart_0_ & ~pencrypt_0_; - assign n1776_1 = ~n1327_1 & n_n2448 & ~pstart_0_ & pencrypt_0_; - assign n1777 = ~n1328 & pksi_144_ & ~pstart_0_ & ~pencrypt_0_; - assign n1778 = ~n1327_1 & n_n2440 & ~pstart_0_ & pencrypt_0_; - assign n1779 = n1328 & pksi_163_ & ~pstart_0_ & ~pencrypt_0_; - assign n1780 = ~n1328 & pksi_145_ & ~pstart_0_ & ~pencrypt_0_; - assign n1781_1 = n1328 & pksi_161_ & ~pstart_0_ & ~pencrypt_0_; - assign n1782 = ~n1327_1 & pksi_159_ & ~pstart_0_ & pencrypt_0_; - assign n1783 = ~n1328 & pksi_85_ & ~pstart_0_ & ~pencrypt_0_; - assign n1784 = n1328 & pksi_93_ & ~pstart_0_ & ~pencrypt_0_; - assign n1785_1 = ~n1327_1 & pksi_84_ & ~pstart_0_ & pencrypt_0_; - assign n1786 = ~n1328 & pksi_111_ & ~pstart_0_ & ~pencrypt_0_; - assign n1787 = n1328 & pksi_142_ & ~pstart_0_ & ~pencrypt_0_; - assign n1788 = ~n1327_1 & n_n168 & ~pstart_0_ & pencrypt_0_; - assign n1789 = ~n1328 & pksi_123_ & ~pstart_0_ & ~pencrypt_0_; - assign n1790 = n1328 & n_n2481 & ~pstart_0_ & ~pencrypt_0_; - assign n1791 = ~n1327_1 & pksi_120_ & ~pstart_0_ & pencrypt_0_; - assign n1792 = ~n1328 & pksi_140_ & ~pstart_0_ & ~pencrypt_0_; - assign n1793 = n1327_1 & pksi_137_ & ~pstart_0_ & pencrypt_0_; - assign n1794 = n1328 & pksi_128_ & ~pstart_0_ & ~pencrypt_0_; - assign n1795 = ~n1328 & pksi_146_ & ~pstart_0_ & ~pencrypt_0_; - assign n1796 = n1327_1 & pksi_160_ & ~pstart_0_ & pencrypt_0_; - assign n1797 = n1328 & pksi_167_ & ~pstart_0_ & ~pencrypt_0_; - assign n1798 = ~n1328 & pksi_156_ & ~pstart_0_ & ~pencrypt_0_; - assign n1799 = n1328 & n_n2440 & ~pstart_0_ & ~pencrypt_0_; - assign n1800 = ~n1327_1 & pksi_155_ & ~pstart_0_ & pencrypt_0_; - assign n1801 = ~n1328 & pksi_161_ & ~pstart_0_ & ~pencrypt_0_; - assign n1802 = n1328 & n_n2430 & ~pstart_0_ & ~pencrypt_0_; - assign n1803 = ~n1327_1 & pksi_190_ & ~pstart_0_ & pencrypt_0_; - assign n1804 = ~n1328 & pksi_93_ & ~pstart_0_ & ~pencrypt_0_; - assign n1805 = n1328 & pksi_82_ & ~pstart_0_ & ~pencrypt_0_; - assign n1806 = ~n1327_1 & pksi_75_ & ~pstart_0_ & pencrypt_0_; - assign n1807 = ~n1328 & pksi_101_ & ~pstart_0_ & ~pencrypt_0_; - assign n1808 = n1328 & pksi_111_ & ~pstart_0_ & ~pencrypt_0_; - assign n1809 = ~n1327_1 & pksi_122_ & ~pstart_0_ & pencrypt_0_; - assign n1810 = ~n1328 & n_n2481 & ~pstart_0_ & ~pencrypt_0_; - assign n1811 = n1327_1 & pksi_120_ & ~pstart_0_ & pencrypt_0_; - assign n1812 = n1328 & pksi_134_ & ~pstart_0_ & ~pencrypt_0_; - assign n1813 = ~n1328 & pksi_133_ & ~pstart_0_ & ~pencrypt_0_; - assign n1814 = n1328 & pksi_140_ & ~pstart_0_ & ~pencrypt_0_; - assign n1815 = ~n1327_1 & pksi_137_ & ~pstart_0_ & pencrypt_0_; - assign n1816 = ~n1328 & pksi_167_ & ~pstart_0_ & ~pencrypt_0_; - assign n1817 = n1328 & pksi_154_ & ~pstart_0_ & ~pencrypt_0_; - assign n1818 = ~n1327_1 & pksi_165_ & ~pstart_0_ & pencrypt_0_; - assign n1819 = ~n1328 & pksi_153_ & ~pstart_0_ & ~pencrypt_0_; - assign n1820 = n1328 & pksi_156_ & ~pstart_0_ & ~pencrypt_0_; - assign n1821 = ~n1327_1 & pksi_148_ & ~pstart_0_ & pencrypt_0_; - assign n1822 = ~n1328 & n_n2430 & ~pstart_0_ & ~pencrypt_0_; - assign n1823 = n1328 & pksi_149_ & ~pstart_0_ & ~pencrypt_0_; - assign n1824 = ~n1327_1 & pksi_174_ & ~pstart_0_ & pencrypt_0_; - assign n1825 = ~n1328 & pksi_82_ & ~pstart_0_ & ~pencrypt_0_; - assign n1826 = n1327_1 & pksi_75_ & ~pstart_0_ & pencrypt_0_; - assign n1827 = n1328 & n_n2272 & ~pstart_0_ & ~pencrypt_0_; - assign n1828 = ~n1328 & pksi_102_ & ~pstart_0_ & ~pencrypt_0_; - assign n1829 = n1328 & pksi_98_ & ~pstart_0_ & ~pencrypt_0_; - assign n1830 = ~n1327_1 & pksi_112_ & ~pstart_0_ & pencrypt_0_; - assign n1831 = ~n1328 & pksi_110_ & ~pstart_0_ & ~pencrypt_0_; - assign n1832 = n1327_1 & pksi_115_ & ~pstart_0_ & pencrypt_0_; - assign n1833 = n1328 & pksi_103_ & ~pstart_0_ & ~pencrypt_0_; - assign n1834 = ~n1328 & pksi_107_ & ~pstart_0_ & ~pencrypt_0_; - assign n1835 = n1328 & pksi_109_ & ~pstart_0_ & ~pencrypt_0_; - assign n1836 = ~n1327_1 & pksi_97_ & ~pstart_0_ & pencrypt_0_; - assign n1837 = ~n1328 & pksi_189_ & ~pstart_0_ & ~pencrypt_0_; - assign n1838 = n1328 & pksi_171_ & ~pstart_0_ & ~pencrypt_0_; - assign n1839 = ~n1327_1 & pksi_175_ & ~pstart_0_ & pencrypt_0_; - assign n1840 = ~n1328 & pksi_177_ & ~pstart_0_ & ~pencrypt_0_; - assign n1841 = n1328 & pksi_186_ & ~pstart_0_ & ~pencrypt_0_; - assign n1842 = ~n1327_1 & n_n109 & ~pstart_0_ & pencrypt_0_; - assign n1843 = ~n1328 & n_n2396 & ~pstart_0_ & ~pencrypt_0_; - assign n1844 = n1328 & pksi_173_ & ~pstart_0_ & ~pencrypt_0_; - assign n1845 = ~n1327_1 & pksi_102_ & ~pstart_0_ & pencrypt_0_; - assign n1846 = ~n1328 & pksi_19_ & ~pstart_0_ & ~pencrypt_0_; - assign n1847 = n1328 & pksi_17_ & ~pstart_0_ & ~pencrypt_0_; - assign n1848 = ~n1327_1 & pksi_2_ & ~pstart_0_ & pencrypt_0_; - assign n1849 = ~n1328 & n_n2513 & ~pstart_0_ & ~pencrypt_0_; - assign n1850 = n1328 & pksi_110_ & ~pstart_0_ & ~pencrypt_0_; - assign n1851 = ~n1327_1 & pksi_115_ & ~pstart_0_ & pencrypt_0_; - assign n1852 = ~n1328 & pksi_109_ & ~pstart_0_ & ~pencrypt_0_; - assign n1853 = n1328 & pksi_116_ & ~pstart_0_ & ~pencrypt_0_; - assign n1854 = ~n1327_1 & pksi_113_ & ~pstart_0_ & pencrypt_0_; - assign n1855 = ~n1328 & n_n2420 & ~pstart_0_ & ~pencrypt_0_; - assign n1856 = n1328 & pksi_189_ & ~pstart_0_ & ~pencrypt_0_; - assign n1857 = ~n1327_1 & pksi_182_ & ~pstart_0_ & pencrypt_0_; - assign n1858 = ~n1328 & pksi_186_ & ~pstart_0_ & ~pencrypt_0_; - assign n1859 = n1328 & pksi_172_ & ~pstart_0_ & ~pencrypt_0_; - assign n1860 = ~n1327_1 & pksi_188_ & ~pstart_0_ & pencrypt_0_; - assign n1861 = ~n1328 & pksi_185_ & ~pstart_0_ & ~pencrypt_0_; - assign n1862 = n1328 & n_n2396 & ~pstart_0_ & ~pencrypt_0_; - assign n1863 = ~n1327_1 & pksi_118_ & ~pstart_0_ & pencrypt_0_; - assign n1864 = ~n1328 & pksi_17_ & ~pstart_0_ & ~pencrypt_0_; - assign n1865 = n1328 & n_n2384 & ~pstart_0_ & ~pencrypt_0_; - assign n1866 = ~n1327_1 & pksi_14_ & ~pstart_0_ & pencrypt_0_; - assign n1867 = ~n1328 & pksi_183_ & ~pstart_0_ & ~pencrypt_0_; - assign n1868 = n1328 & pksi_118_ & ~pstart_0_ & ~pencrypt_0_; - assign n1869 = ~n1327_1 & pksi_119_ & ~pstart_0_ & pencrypt_0_; - assign n1870 = ~n1328 & pksi_116_ & ~pstart_0_ & ~pencrypt_0_; - assign n1871 = ~n1327_1 & n_n2495 & ~pstart_0_ & pencrypt_0_; - assign n1872 = n1328 & pksi_104_ & ~pstart_0_ & ~pencrypt_0_; - assign n1873 = ~n1328 & pksi_97_ & ~pstart_0_ & ~pencrypt_0_; - assign n1874 = n1328 & pksi_113_ & ~pstart_0_ & ~pencrypt_0_; - assign n1875 = ~n1327_1 & pksi_111_ & ~pstart_0_ & pencrypt_0_; - assign n1876 = ~n1328 & pksi_130_ & ~pstart_0_ & ~pencrypt_0_; - assign n1877 = n1328 & pksi_136_ & ~pstart_0_ & ~pencrypt_0_; - assign n1878 = ~n1327_1 & pksi_123_ & ~pstart_0_ & pencrypt_0_; - assign n1879 = ~n1328 & pksi_184_ & ~pstart_0_ & ~pencrypt_0_; - assign n1880 = ~n1327_1 & n_n2416 & ~pstart_0_ & pencrypt_0_; - assign n1881 = n1328 & n_n2420 & ~pstart_0_ & ~pencrypt_0_; - assign n1882 = ~n1328 & n_n2408 & ~pstart_0_ & ~pencrypt_0_; - assign n1883 = n1328 & pksi_180_ & ~pstart_0_ & ~pencrypt_0_; - assign n1884 = ~n1327_1 & pksi_172_ & ~pstart_0_ & pencrypt_0_; - assign n1885 = ~n1328 & pksi_79_ & ~pstart_0_ & ~pencrypt_0_; - assign n1886 = n1328 & pksi_4_ & ~pstart_0_ & ~pencrypt_0_; - assign n1887 = ~n1327_1 & pksi_15_ & ~pstart_0_ & pencrypt_0_; - assign n1888 = ~n1328 & n_n2384 & ~pstart_0_ & ~pencrypt_0_; - assign n1889 = n1328 & pksi_11_ & ~pstart_0_ & ~pencrypt_0_; - assign n1890 = ~n1327_1 & pksi_22_ & ~pstart_0_ & pencrypt_0_; - assign n1891 = ~n1328 & pksi_118_ & ~pstart_0_ & ~pencrypt_0_; - assign n1892 = n1328 & pksi_102_ & ~pstart_0_ & ~pencrypt_0_; - assign n1893 = ~n1327_1 & pksi_106_ & ~pstart_0_ & pencrypt_0_; - assign n1894 = ~n1328 & pksi_103_ & ~pstart_0_ & ~pencrypt_0_; - assign n1895 = n1328 & pksi_96_ & ~pstart_0_ & ~pencrypt_0_; - assign n1896 = ~n1327_1 & pksi_108_ & ~pstart_0_ & pencrypt_0_; - assign n1897 = ~n1328 & pksi_104_ & ~pstart_0_ & ~pencrypt_0_; - assign n1898 = n1328 & pksi_97_ & ~pstart_0_ & ~pencrypt_0_; - assign n1899 = ~n1327_1 & pksi_101_ & ~pstart_0_ & pencrypt_0_; - assign n1900 = ~n1328 & pksi_136_ & ~pstart_0_ & ~pencrypt_0_; - assign n1901 = n1327_1 & pksi_123_ & ~pstart_0_ & pencrypt_0_; - assign n1902 = n1328 & n_n2485 & ~pstart_0_ & ~pencrypt_0_; - assign n1903 = ~n1328 & pksi_178_ & ~pstart_0_ & ~pencrypt_0_; - assign n1904 = n1328 & pksi_184_ & ~pstart_0_ & ~pencrypt_0_; - assign n1905 = ~n1327_1 & pksi_171_ & ~pstart_0_ & pencrypt_0_; - assign n1906 = ~n1328 & pksi_180_ & ~pstart_0_ & ~pencrypt_0_; - assign n1907 = n1328 & pksi_177_ & ~pstart_0_ & ~pencrypt_0_; - assign n1908 = ~n1327_1 & pksi_179_ & ~pstart_0_ & pencrypt_0_; - assign n1909 = ~n1328 & pksi_92_ & ~pstart_0_ & ~pencrypt_0_; - assign n1910 = n1328 & pksi_79_ & ~pstart_0_ & ~pencrypt_0_; - assign n1911 = ~n1327_1 & pksi_6_ & ~pstart_0_ & pencrypt_0_; - assign n1912 = ~n1328 & pksi_11_ & ~pstart_0_ & ~pencrypt_0_; - assign n1913 = n1328 & pksi_2_ & ~pstart_0_ & ~pencrypt_0_; - assign n1914 = ~n1327_1 & pksi_0_ & ~pstart_0_ & pencrypt_0_; - assign n1915 = n1328 & n_n2277 & ~pstart_0_ & ~pencrypt_0_; - assign n1916 = ~n1328 & pksi_73_ & ~pstart_0_ & ~pencrypt_0_; - assign n1917 = ~n1327_1 & pksi_82_ & ~pstart_0_ & pencrypt_0_; - assign n1918 = ~n1328 & n_n2517 & ~pstart_0_ & ~pencrypt_0_; - assign n1919 = n1328 & pksi_117_ & ~pstart_0_ & ~pencrypt_0_; - assign n1920 = ~n1327_1 & pksi_110_ & ~pstart_0_ & pencrypt_0_; - assign n1921 = ~n1328 & pksi_108_ & ~pstart_0_ & ~pencrypt_0_; - assign n1922 = n1328 & pksi_105_ & ~pstart_0_ & ~pencrypt_0_; - assign n1923 = ~n1327_1 & pksi_107_ & ~pstart_0_ & pencrypt_0_; - assign n1924 = ~n1328 & pksi_132_ & ~pstart_0_ & ~pencrypt_0_; - assign n1925 = n1328 & pksi_129_ & ~pstart_0_ & ~pencrypt_0_; - assign n1926 = ~n1327_1 & pksi_131_ & ~pstart_0_ & pencrypt_0_; - assign n1927 = n1328 & n_n2462 & ~pstart_0_ & ~pencrypt_0_; - assign n1928 = ~n1328 & pksi_137_ & ~pstart_0_ & ~pencrypt_0_; - assign n1929 = ~n1327_1 & pksi_166_ & ~pstart_0_ & pencrypt_0_; - assign n1930 = ~n1328 & n_n121 & ~pstart_0_ & ~pencrypt_0_; - assign n1931 = n1328 & pksi_178_ & ~pstart_0_ & ~pencrypt_0_; - assign n1932 = ~n1327_1 & pksi_189_ & ~pstart_0_ & pencrypt_0_; - assign n1933 = ~n1328 & n_n2412 & ~pstart_0_ & ~pencrypt_0_; - assign n1934 = n1328 & n_n2410 & ~pstart_0_ & ~pencrypt_0_; - assign n1935 = ~n1327_1 & pksi_177_ & ~pstart_0_ & pencrypt_0_; - assign n1936 = ~n1328 & pksi_188_ & ~pstart_0_ & ~pencrypt_0_; - assign n1937 = n1328 & pksi_176_ & ~pstart_0_ & ~pencrypt_0_; - assign n1938 = ~n1327_1 & n_n2396 & ~pstart_0_ & pencrypt_0_; - assign n1939 = ~n1328 & pksi_6_ & ~pstart_0_ & ~pencrypt_0_; - assign n1940 = n1328 & pksi_15_ & ~pstart_0_ & ~pencrypt_0_; - assign n1941 = ~n1327_1 & pksi_19_ & ~pstart_0_ & pencrypt_0_; - assign n1942 = ~n1328 & pksi_173_ & ~pstart_0_ & ~pencrypt_0_; - assign n1943 = n1328 & pksi_183_ & ~pstart_0_ & ~pencrypt_0_; - assign n1944 = ~n1327_1 & pksi_98_ & ~pstart_0_ & pencrypt_0_; - assign n1945 = ~n1328 & pksi_112_ & ~pstart_0_ & ~pencrypt_0_; - assign n1946 = n1328 & n_n2517 & ~pstart_0_ & ~pencrypt_0_; - assign n1947 = ~n1327_1 & n_n2513 & ~pstart_0_ & pencrypt_0_; - assign n1948 = ~n1328 & pksi_105_ & ~pstart_0_ & ~pencrypt_0_; - assign n1949 = n1328 & pksi_114_ & ~pstart_0_ & ~pencrypt_0_; - assign n1950 = ~n1327_1 & pksi_109_ & ~pstart_0_ & pencrypt_0_; - assign n1951 = ~n1328 & n_n2474 & ~pstart_0_ & ~pencrypt_0_; - assign n1952 = n1328 & pksi_132_ & ~pstart_0_ & ~pencrypt_0_; - assign n1953 = ~n1327_1 & pksi_124_ & ~pstart_0_ & pencrypt_0_; - assign n1954 = ~n1328 & n_n2462 & ~pstart_0_ & ~pencrypt_0_; - assign n1955 = n1328 & pksi_125_ & ~pstart_0_ & ~pencrypt_0_; - assign n1956 = ~n1327_1 & pksi_150_ & ~pstart_0_ & pencrypt_0_; - assign n1957 = ~n1328 & pksi_170_ & ~pstart_0_ & ~pencrypt_0_; - assign n1958 = ~n1327_1 & n_n2420 & ~pstart_0_ & pencrypt_0_; - assign n1959 = n1328 & n_n121 & ~pstart_0_ & ~pencrypt_0_; - assign n1960 = ~n1328 & n_n2410 & ~pstart_0_ & ~pencrypt_0_; - assign n1961 = n1328 & n_n2408 & ~pstart_0_ & ~pencrypt_0_; - assign n1962 = ~n1327_1 & pksi_186_ & ~pstart_0_ & pencrypt_0_; - assign n1963 = ~n1328 & n_n109 & ~pstart_0_ & ~pencrypt_0_; - assign n1964 = n1328 & pksi_188_ & ~pstart_0_ & ~pencrypt_0_; - assign n1965 = ~n1327_1 & pksi_185_ & ~pstart_0_ & pencrypt_0_; - assign n1966 = ~n1328 & pksi_15_ & ~pstart_0_ & ~pencrypt_0_; - assign n1967 = n1328 & pksi_5_ & ~pstart_0_ & ~pencrypt_0_; - assign n1968 = ~n1327_1 & pksi_17_ & ~pstart_0_ & pencrypt_0_; - assign n1969 = ~n1328 & pksi_99_ & ~pstart_0_ & ~pencrypt_0_; - assign n1970 = n1328 & n_n2513 & ~pstart_0_ & ~pencrypt_0_; - assign n1971 = ~n1327_1 & pksi_96_ & ~pstart_0_ & pencrypt_0_; - assign n1972 = ~n1328 & pksi_114_ & ~pstart_0_ & ~pencrypt_0_; - assign n1973 = n1328 & pksi_100_ & ~pstart_0_ & ~pencrypt_0_; - assign n1974 = ~n1327_1 & pksi_116_ & ~pstart_0_ & pencrypt_0_; - assign n1975 = ~n1328 & pksi_165_ & ~pstart_0_ & ~pencrypt_0_; - assign n1976 = n1328 & pksi_147_ & ~pstart_0_ & ~pencrypt_0_; - assign n1977 = ~n1327_1 & pksi_151_ & ~pstart_0_ & pencrypt_0_; - assign n1978 = ~n1328 & n_n2440 & ~pstart_0_ & ~pencrypt_0_; - assign n1979 = n1328 & pksi_162_ & ~pstart_0_ & ~pencrypt_0_; - assign n1980 = ~n1327_1 & pksi_157_ & ~pstart_0_ & pencrypt_0_; - assign n1981 = ~n1328 & pksi_174_ & ~pstart_0_ & ~pencrypt_0_; - assign n1982 = n1328 & pksi_170_ & ~pstart_0_ & ~pencrypt_0_; - assign n1983 = ~n1327_1 & pksi_184_ & ~pstart_0_ & pencrypt_0_; - assign n1984 = ~n1328 & pksi_182_ & ~pstart_0_ & ~pencrypt_0_; - assign n1985 = ~n1327_1 & n_n2408 & ~pstart_0_ & pencrypt_0_; - assign n1986 = n1328 & pksi_175_ & ~pstart_0_ & ~pencrypt_0_; - assign n1987 = ~n1328 & pksi_169_ & ~pstart_0_ & ~pencrypt_0_; - assign n1988 = n1328 & pksi_185_ & ~pstart_0_ & ~pencrypt_0_; - assign n1989 = ~n1327_1 & pksi_183_ & ~pstart_0_ & pencrypt_0_; - assign n1990 = ~n1328 & pksi_5_ & ~pstart_0_ & ~pencrypt_0_; - assign n1991 = ~n1327_1 & n_n2384 & ~pstart_0_ & pencrypt_0_; - assign n1992 = n1328 & pksi_9_ & ~pstart_0_ & ~pencrypt_0_; - assign n1993 = ~n1328 & pksi_117_ & ~pstart_0_ & ~pencrypt_0_; - assign n1994 = n1328 & pksi_99_ & ~pstart_0_ & ~pencrypt_0_; - assign n1995 = ~n1327_1 & pksi_103_ & ~pstart_0_ & pencrypt_0_; - assign n1996 = ~n1328 & pksi_100_ & ~pstart_0_ & ~pencrypt_0_; - assign n1997 = n1328 & pksi_107_ & ~pstart_0_ & ~pencrypt_0_; - assign n1998 = ~n1327_1 & pksi_104_ & ~pstart_0_ & pencrypt_0_; - assign n1999 = ~n1328 & n_n2452 & ~pstart_0_ & ~pencrypt_0_; - assign n2000 = n1328 & pksi_165_ & ~pstart_0_ & ~pencrypt_0_; - assign n2001 = ~n1327_1 & pksi_158_ & ~pstart_0_ & pencrypt_0_; - assign n2002 = ~n1328 & pksi_162_ & ~pstart_0_ & ~pencrypt_0_; - assign n2003 = n1328 & pksi_148_ & ~pstart_0_ & ~pencrypt_0_; - assign n2004 = ~n1327_1 & pksi_164_ & ~pstart_0_ & pencrypt_0_; - assign n2005 = ~n1328 & pksi_190_ & ~pstart_0_ & ~pencrypt_0_; - assign n2006 = n1328 & pksi_174_ & ~pstart_0_ & ~pencrypt_0_; - assign n2007 = ~n1327_1 & pksi_178_ & ~pstart_0_ & pencrypt_0_; - assign n2008 = ~n1328 & pksi_175_ & ~pstart_0_ & ~pencrypt_0_; - assign n2009 = n1328 & n_n2412 & ~pstart_0_ & ~pencrypt_0_; - assign n2010 = ~n1327_1 & pksi_180_ & ~pstart_0_ & pencrypt_0_; - assign n2011 = ~n1328 & pksi_176_ & ~pstart_0_ & ~pencrypt_0_; - assign n2012 = n1328 & pksi_169_ & ~pstart_0_ & ~pencrypt_0_; - assign n2013 = ~n1327_1 & pksi_173_ & ~pstart_0_ & pencrypt_0_; - assign n2014 = ~n1328 & pksi_9_ & ~pstart_0_ & ~pencrypt_0_; - assign n2015 = n1328 & pksi_19_ & ~pstart_0_ & ~pencrypt_0_; - assign n2016 = ~n1327_1 & pksi_11_ & ~pstart_0_ & pencrypt_0_; - assign n2017 = pstart_0_ & (pencrypt_0_ ? pkey_57_ : pkey_0_); - assign n2018 = n2017 | (n_n2384 & n1327_1 & n1332_1); - assign n2019 = pstart_0_ & (pencrypt_0_ ? pkey_211_ : pkey_219_); - assign n2020 = n2019 | (n_n2396 & n1327_1 & n1332_1); - assign n2021 = pstart_0_ & (pencrypt_0_ ? pkey_205_ : pkey_213_); - assign n2022 = n2021 | (n_n2408 & n1327_1 & n1332_1); - assign n2023 = pstart_0_ & (pencrypt_0_ ? pkey_230_ : pkey_238_); - assign n2024 = n2023 | (n_n121 & n1327_1 & n1332_1); - assign n2025 = pstart_0_ & (pencrypt_0_ ? pkey_156_ : pkey_164_); - assign n2026 = n2025 | (pksi_157_ & n1327_1 & n1332_1); - assign n2027 = pstart_0_ & (pencrypt_0_ ? pkey_181_ : pkey_189_); - assign n2028 = n2027 | (n_n2448 & n1327_1 & n1332_1); - assign n2029 = pstart_0_ & (pencrypt_0_ ? pkey_20_ : pkey_28_); - assign n2030 = n2029 | (pksi_116_ & n1327_1 & n1332_1); - assign n2031 = pstart_0_ & (pencrypt_0_ ? pkey_45_ : pkey_53_); - assign n2032 = n2031 | (pksi_110_ & n1327_1 & n1332_1); - assign n2033 = pstart_0_ & (pencrypt_0_ ? pkey_0_ : pkey_8_); - assign n2034 = n2033 | (pksi_17_ & n1327_1 & n1332_1); - assign n2035 = pstart_0_ & (pencrypt_0_ ? pkey_203_ : pkey_211_); - assign n2036 = n2035 | (pksi_173_ & n1327_1 & n1332_1); - assign n2037 = pstart_0_ & (pencrypt_0_ ? pkey_213_ : pkey_221_); - assign n2038 = n2037 | (n_n2410 & n1327_1 & n1332_1); - assign n2039 = pstart_0_ & (pencrypt_0_ ? pkey_222_ : pkey_230_); - assign n2040 = n2039 | (pksi_178_ & n1327_1 & n1332_1); - assign n2041 = pstart_0_ & (pencrypt_0_ ? pkey_164_ : pkey_172_); - assign n2042 = n2041 | (pksi_155_ & n1327_1 & n1332_1); - assign n2043 = pstart_0_ & (pencrypt_0_ ? pkey_173_ : pkey_181_); - assign n2044 = n2043 | (pksi_158_ & n1327_1 & n1332_1); - assign n2045 = pstart_0_ & (pencrypt_0_ ? pkey_28_ : pkey_36_); - assign n2046 = n2045 | (pksi_109_ & n1327_1 & n1332_1); - assign n2047 = pstart_0_ & (pencrypt_0_ ? pkey_37_ : pkey_45_); - assign n2048 = n2047 | (pksi_103_ & n1327_1 & n1332_1); - assign n2049 = pstart_0_ & (pencrypt_0_ ? pkey_8_ : pkey_16_); - assign n2050 = n2049 | (pksi_19_ & n1327_1 & n1332_1); - assign n2051 = pstart_0_ & (pencrypt_0_ ? pkey_196_ : pkey_204_); - assign n2052 = n2051 | (pksi_169_ & n1327_1 & n1332_1); - assign n2053 = pstart_0_ & (pencrypt_0_ ? pkey_252_ : pkey_197_); - assign n2054 = n2053 | (pksi_177_ & n1327_1 & n1332_1); - assign n2055 = pstart_0_ & (pencrypt_0_ ? pkey_214_ : pkey_222_); - assign n2056 = n2055 | (pksi_184_ & n1327_1 & n1332_1); - assign n2057 = pstart_0_ & (pencrypt_0_ ? pkey_190_ : pkey_67_); - assign n2058 = n2057 | (pksi_166_ & n1327_1 & n1332_1); - assign n2059 = pstart_0_ & (pencrypt_0_ ? pkey_116_ : pkey_124_); - assign n2060 = n2059 | (pksi_138_ & n1327_1 & n1332_1); - assign n2061 = pstart_0_ & (pencrypt_0_ ? pkey_36_ : pkey_44_); - assign n2062 = n2061 | (pksi_107_ & n1327_1 & n1332_1); - assign n2063 = pstart_0_ & (pencrypt_0_ ? pkey_61_ : pkey_6_); - assign n2064 = n2063 | (pksi_99_ & n1327_1 & n1332_1); - assign n2065 = pstart_0_ & (pencrypt_0_ ? pkey_54_ : pkey_62_); - assign n2066 = n2065 | (pksi_102_ & n1327_1 & n1332_1); - assign n2067 = pstart_0_ & (pencrypt_0_ ? pkey_16_ : pkey_24_); - assign n2068 = n2067 | (pksi_9_ & n1327_1 & n1332_1); - assign n2069 = pstart_0_ & (pencrypt_0_ ? pkey_219_ : pkey_196_); - assign n2070 = n2069 | (pksi_185_ & n1327_1 & n1332_1); - assign n2071 = pstart_0_ & (pencrypt_0_ ? pkey_197_ : pkey_205_); - assign n2072 = n2071 | (pksi_180_ & n1327_1 & n1332_1); - assign n2073 = pstart_0_ & (pencrypt_0_ ? pkey_206_ : pkey_214_); - assign n2074 = n2073 | (n_n2420 & n1327_1 & n1332_1); - assign n2075 = pstart_0_ & (pencrypt_0_ ? pkey_67_ : pkey_75_); - assign n2076 = n2075 | (pksi_135_ & n1327_1 & n1332_1); - assign n2077 = pstart_0_ & (pencrypt_0_ ? pkey_44_ : pkey_116_); - assign n2078 = n2077 | (pksi_124_ & n1327_1 & n1332_1); - assign n2079 = pstart_0_ & (pencrypt_0_ ? pkey_44_ : pkey_52_); - assign n2080 = n2079 | (pksi_100_ & n1327_1 & n1332_1); - assign n2081 = pstart_0_ & (pencrypt_0_ ? pkey_53_ : pkey_61_); - assign n2082 = n2081 | (n_n2513 & n1327_1 & n1332_1); - assign n2083 = pstart_0_ & (pencrypt_0_ ? pkey_226_ : pkey_234_); - assign n2084 = n2083 | (pksi_93_ & n1327_1 & n1332_1); - assign n2085 = pstart_0_ & (pencrypt_0_ ? pkey_25_ : pkey_33_); - assign n2086 = n2085 | (pksi_22_ & n1327_1 & n1332_1); - assign n2087 = pstart_0_ & (pencrypt_0_ ? pkey_48_ : pkey_56_); - assign n2088 = n2087 | (pksi_23_ & n1327_1 & n1332_1); - assign n2089 = pstart_0_ & (pencrypt_0_ ? pkey_172_ : pkey_244_); - assign n2090 = n2089 | (pksi_172_ & n1327_1 & n1332_1); - assign n2091 = pstart_0_ & (pencrypt_0_ ? pkey_198_ : pkey_206_); - assign n2092 = n2091 | (pksi_189_ & n1327_1 & n1332_1); - assign n2093 = pstart_0_ & (pencrypt_0_ ? pkey_125_ : pkey_70_); - assign n2094 = n2093 | (n_n2481 & ~n1327_1 & n1332_1); - assign n2095 = pstart_0_ & (pencrypt_0_ ? pkey_19_ : pkey_27_); - assign n2096 = n2095 | (n_n2495 & n1327_1 & n1332_1); - assign n2097 = pstart_0_ & (pencrypt_0_ ? pkey_13_ : pkey_21_); - assign n2098 = n2097 | (n_n2507 & n1327_1 & n1332_1); - assign n2099 = pstart_0_ & (pencrypt_0_ ? pkey_38_ : pkey_46_); - assign n2100 = n2099 | (pksi_119_ & n1327_1 & n1332_1); - assign n2101 = pstart_0_ & (pencrypt_0_ ? pkey_33_ : pkey_41_); - assign n2102 = n2101 | (pksi_14_ & n1327_1 & n1332_1); - assign n2103 = pstart_0_ & (pencrypt_0_ ? pkey_40_ : pkey_48_); - assign n2104 = n2103 | (pksi_6_ & n1327_1 & n1332_1); - assign n2105 = pstart_0_ & (pencrypt_0_ ? pkey_244_ : pkey_252_); - assign n2106 = n2105 | (pksi_186_ & n1327_1 & n1332_1); - assign n2107 = pstart_0_ & (pencrypt_0_ ? pkey_253_ : pkey_198_); - assign n2108 = n2107 | (pksi_171_ & n1327_1 & n1332_1); - assign n2109 = pstart_0_ & (pencrypt_0_ ? pkey_70_ : pkey_78_); - assign n2110 = n2109 | (pksi_141_ & n1327_1 & n1332_1); - assign n2111 = pstart_0_ & (pencrypt_0_ ? pkey_11_ : pkey_19_); - assign n2112 = n2111 | (pksi_101_ & n1327_1 & n1332_1); - assign n2113 = pstart_0_ & (pencrypt_0_ ? pkey_27_ : pkey_4_); - assign n2114 = n2113 | (pksi_113_ & n1327_1 & n1332_1); - assign n2115 = pstart_0_ & (pencrypt_0_ ? pkey_46_ : pkey_54_); - assign n2116 = n2115 | (pksi_98_ & n1327_1 & n1332_1); - assign n2117 = pstart_0_ & (pencrypt_0_ ? pkey_41_ : pkey_49_); - assign n2118 = n2117 | (pksi_2_ & n1327_1 & n1332_1); - assign n2119 = pstart_0_ & (pencrypt_0_ ? pkey_195_ : pkey_203_); - assign n2120 = n2119 | (pksi_183_ & n1327_1 & n1332_1); - assign n2121 = pstart_0_ & (pencrypt_0_ ? pkey_220_ : pkey_228_); - assign n2122 = n2121 | (n_n109 & n1327_1 & n1332_1); - assign n2123 = pstart_0_ & (pencrypt_0_ ? pkey_245_ : pkey_253_); - assign n2124 = n2123 | (n_n2416 & n1327_1 & n1332_1); - assign n2125 = pstart_0_ & (pencrypt_0_ ? pkey_4_ : pkey_12_); - assign n2126 = n2125 | (pksi_97_ & n1327_1 & n1332_1); - assign n2127 = pstart_0_ & (pencrypt_0_ ? pkey_29_ : pkey_37_); - assign n2128 = n2127 | (pksi_96_ & n1327_1 & n1332_1); - assign n2129 = pstart_0_ & (pencrypt_0_ ? pkey_49_ : pkey_57_); - assign n2130 = n2129 | (pksi_11_ & n1327_1 & n1332_1); - assign n2131 = pstart_0_ & (pencrypt_0_ ? pkey_62_ : pkey_195_); - assign n2132 = n2131 | (pksi_118_ & n1327_1 & n1332_1); - assign n2133 = pstart_0_ & (pencrypt_0_ ? pkey_228_ : pkey_172_); - assign n2134 = n2133 | (pksi_179_ & n1327_1 & n1332_1); - assign n2135 = pstart_0_ & (pencrypt_0_ ? pkey_237_ : pkey_245_); - assign n2136 = n2135 | (pksi_182_ & n1327_1 & n1332_1); - assign n2137 = pstart_0_ & (pencrypt_0_ ? pkey_12_ : pkey_20_); - assign n2138 = n2137 | (pksi_104_ & n1327_1 & n1332_1); - assign n2139 = pstart_0_ & (pencrypt_0_ ? pkey_21_ : pkey_29_); - assign n2140 = n2139 | (n_n2507 & ~n1327_1 & n1332_1); - assign n2141 = pstart_0_ & (pencrypt_0_ ? pkey_30_ : pkey_38_); - assign n2142 = n2141 | (pksi_106_ & n1327_1 & n1332_1); - assign n2143 = pstart_0_ & (pencrypt_0_ ? pkey_194_ : pkey_202_); - assign n2144 = n2143 | (n_n2268 & ~n1327_1 & n1332_1); - assign n2145 = pstart_0_ & (pencrypt_0_ ? pkey_254_ : pkey_131_); - assign n2146 = n2145 | (pksi_190_ & n1327_1 & n1332_1); - assign n2147 = pstart_0_ & (pencrypt_0_ ? pkey_180_ : pkey_188_); - assign n2148 = n2147 | (pksi_162_ & n1327_1 & n1332_1); - assign n2149 = pstart_0_ & (pencrypt_0_ ? pkey_142_ : pkey_150_); - assign n2150 = n2149 | (n_n2452 & n1327_1 & n1332_1); - assign n2151 = pstart_0_ & (pencrypt_0_ ? pkey_68_ : pkey_76_); - assign n2152 = n2151 | (pksi_121_ & n1327_1 & n1332_1); - assign n2153 = pstart_0_ & (pencrypt_0_ ? pkey_93_ : pkey_101_); - assign n2154 = n2153 | (n_n2476 & ~n1327_1 & n1332_1); - assign n2155 = pstart_0_ & (pencrypt_0_ ? pkey_118_ : pkey_126_); - assign n2156 = n2155 | (pksi_126_ & n1327_1 & n1332_1); - assign n2157 = pstart_0_ & (pencrypt_0_ ? pkey_202_ : pkey_210_); - assign n2158 = n2157 | (pksi_84_ & n1327_1 & n1332_1); - assign n2159 = pstart_0_ & (pencrypt_0_ ? pkey_131_ : pkey_139_); - assign n2160 = n2159 | (pksi_159_ & n1327_1 & n1332_1); - assign n2161 = pstart_0_ & (pencrypt_0_ ? pkey_172_ : pkey_180_); - assign n2162 = n2161 | (pksi_148_ & n1327_1 & n1332_1); - assign n2163 = pstart_0_ & (pencrypt_0_ ? pkey_150_ : pkey_158_); - assign n2164 = n2163 | (n_n2452 & ~n1327_1 & n1332_1); - assign n2165 = pstart_0_ & (pencrypt_0_ ? pkey_91_ : pkey_68_); - assign n2166 = n2165 | (n_n2462 & ~n1327_1 & n1332_1); - assign n2167 = pstart_0_ & (pencrypt_0_ ? pkey_101_ : pkey_109_); - assign n2168 = n2167 | (pksi_127_ & n1327_1 & n1332_1); - assign n2169 = pstart_0_ & (pencrypt_0_ ? pkey_110_ : pkey_118_); - assign n2170 = n2169 | (pksi_122_ & n1327_1 & n1332_1); - assign n2171 = pstart_0_ & (pencrypt_0_ ? pkey_210_ : pkey_218_); - assign n2172 = n2171 | (n_n2272 & n1327_1 & n1332_1); - assign n2173 = pstart_0_ & (pencrypt_0_ ? pkey_139_ : pkey_147_); - assign n2174 = n2173 | (pksi_149_ & n1327_1 & n1332_1); - assign n2175 = pstart_0_ & (pencrypt_0_ ? pkey_133_ : pkey_141_); - assign n2176 = n2175 | (pksi_156_ & n1327_1 & n1332_1); - assign n2177 = pstart_0_ & (pencrypt_0_ ? pkey_189_ : pkey_134_); - assign n2178 = n2177 | (pksi_147_ & n1327_1 & n1332_1); - assign n2179 = pstart_0_ & (pencrypt_0_ ? pkey_83_ : pkey_91_); - assign n2180 = n2179 | (n_n2462 & n1327_1 & n1332_1); - assign n2181 = pstart_0_ & (pencrypt_0_ ? pkey_109_ : pkey_117_); - assign n2182 = n2181 | (pksi_134_ & n1327_1 & n1332_1); - assign n2183 = pstart_0_ & (pencrypt_0_ ? pkey_3_ : pkey_11_); - assign n2184 = n2183 | (pksi_111_ & n1327_1 & n1332_1); - assign n2185 = pstart_0_ & (pencrypt_0_ ? pkey_218_ : pkey_226_); - assign n2186 = n2185 | (pksi_82_ & n1327_1 & n1332_1); - assign n2187 = pstart_0_ & (pencrypt_0_ ? pkey_147_ : pkey_155_); - assign n2188 = n2187 | (n_n2430 & n1327_1 & n1332_1); - assign n2189 = pstart_0_ & (pencrypt_0_ ? pkey_188_ : pkey_133_); - assign n2190 = n2189 | (n_n2440 & n1327_1 & n1332_1); - assign n2191 = pstart_0_ & (pencrypt_0_ ? pkey_134_ : pkey_142_); - assign n2192 = n2191 | (pksi_165_ & n1327_1 & n1332_1); - assign n2193 = pstart_0_ & (pencrypt_0_ ? pkey_75_ : pkey_83_); - assign n2194 = n2193 | (pksi_125_ & n1327_1 & n1332_1); - assign n2195 = pstart_0_ & (pencrypt_0_ ? pkey_117_ : pkey_125_); - assign n2196 = n2195 | (n_n2481 & n1327_1 & n1332_1); - assign n2197 = pstart_0_ & (pencrypt_0_ ? pkey_126_ : pkey_3_); - assign n2198 = n2197 | (pksi_142_ & n1327_1 & n1332_1); - assign n2199 = pstart_0_ & (pencrypt_0_ ? pkey_227_ : pkey_235_); - assign n2200 = n2199 | (pksi_79_ & n1327_1 & n1332_1); - assign n2201 = pstart_0_ & (pencrypt_0_ ? pkey_24_ : pkey_32_); - assign n2202 = n2201 | (pksi_5_ & n1327_1 & n1332_1); - assign n2203 = pstart_0_ & (pencrypt_0_ ? pkey_212_ : pkey_220_); - assign n2204 = n2203 | (pksi_188_ & n1327_1 & n1332_1); - assign n2205 = pstart_0_ & (pencrypt_0_ ? pkey_155_ : pkey_132_); - assign n2206 = n2205 | (n_n2430 & ~n1327_1 & n1332_1); - assign n2207 = pstart_0_ & (pencrypt_0_ ? pkey_149_ : pkey_157_); - assign n2208 = n2207 | (pksi_163_ & n1327_1 & n1332_1); - assign n2209 = pstart_0_ & (pencrypt_0_ ? pkey_174_ : pkey_182_); - assign n2210 = n2209 | (pksi_146_ & n1327_1 & n1332_1); - assign n2211 = pstart_0_ & (pencrypt_0_ ? pkey_100_ : pkey_44_); - assign n2212 = n2211 | (pksi_131_ & n1327_1 & n1332_1); - assign n2213 = pstart_0_ & (pencrypt_0_ ? pkey_124_ : pkey_69_); - assign n2214 = n2213 | (pksi_129_ & n1327_1 & n1332_1); - assign n2215 = pstart_0_ & (pencrypt_0_ ? pkey_86_ : pkey_94_); - assign n2216 = n2215 | (pksi_136_ & n1327_1 & n1332_1); - assign n2217 = pstart_0_ & (pencrypt_0_ ? pkey_52_ : pkey_60_); - assign n2218 = n2217 | (pksi_114_ & n1327_1 & n1332_1); - assign n2219 = pstart_0_ & (pencrypt_0_ ? pkey_14_ : pkey_22_); - assign n2220 = n2219 | (n_n2517 & n1327_1 & n1332_1); - assign n2221 = pstart_0_ & (pencrypt_0_ ? pkey_235_ : pkey_243_); - assign n2222 = n2221 | (pksi_92_ & n1327_1 & n1332_1); - assign n2223 = pstart_0_ & (pencrypt_0_ ? pkey_32_ : pkey_40_); - assign n2224 = n2223 | (pksi_15_ & n1327_1 & n1332_1); - assign n2225 = pstart_0_ & (pencrypt_0_ ? pkey_204_ : pkey_212_); - assign n2226 = n2225 | (pksi_176_ & n1327_1 & n1332_1); - assign n2227 = pstart_0_ & (pencrypt_0_ ? pkey_132_ : pkey_140_); - assign n2228 = n2227 | (pksi_145_ & n1327_1 & n1332_1); - assign n2229 = pstart_0_ & (pencrypt_0_ ? pkey_141_ : pkey_149_); - assign n2230 = n2229 | (pksi_153_ & n1327_1 & n1332_1); - assign n2231 = pstart_0_ & (pencrypt_0_ ? pkey_182_ : pkey_190_); - assign n2232 = n2231 | (pksi_150_ & n1327_1 & n1332_1); - assign n2233 = pstart_0_ & (pencrypt_0_ ? pkey_92_ : pkey_100_); - assign n2234 = n2233 | (pksi_133_ & n1327_1 & n1332_1); - assign n2235 = pstart_0_ & (pencrypt_0_ ? pkey_69_ : pkey_77_); - assign n2236 = n2235 | (pksi_132_ & n1327_1 & n1332_1); - assign n2237 = pstart_0_ & (pencrypt_0_ ? pkey_78_ : pkey_86_); - assign n2238 = n2237 | (n_n2485 & n1327_1 & n1332_1); - assign n2239 = pstart_0_ & (pencrypt_0_ ? pkey_60_ : pkey_5_); - assign n2240 = n2239 | (pksi_105_ & n1327_1 & n1332_1); - assign n2241 = pstart_0_ & (pencrypt_0_ ? pkey_6_ : pkey_14_); - assign n2242 = n2241 | (pksi_117_ & n1327_1 & n1332_1); - assign n2243 = pstart_0_ & (pencrypt_0_ ? pkey_243_ : pkey_251_); - assign n2244 = n2243 | (n_n10 & n1327_1 & n1332_1); - assign n2245 = pstart_0_ & (pencrypt_0_ ? pkey_221_ : pkey_229_); - assign n2246 = n2245 | (n_n2412 & n1327_1 & n1332_1); - assign n2247 = pstart_0_ & (pencrypt_0_ ? pkey_246_ : pkey_254_); - assign n2248 = n2247 | (pksi_174_ & n1327_1 & n1332_1); - assign n2249 = pstart_0_ & (pencrypt_0_ ? pkey_140_ : pkey_148_); - assign n2250 = n2249 | (pksi_152_ & n1327_1 & n1332_1); - assign n2251 = pstart_0_ & (pencrypt_0_ ? pkey_165_ : pkey_173_); - assign n2252 = n2251 | (pksi_151_ & n1327_1 & n1332_1); - assign n2253 = pstart_0_ & (pencrypt_0_ ? pkey_158_ : pkey_166_); - assign n2254 = n2253 | (pksi_154_ & n1327_1 & n1332_1); - assign n2255 = pstart_0_ & (pencrypt_0_ ? pkey_84_ : pkey_92_); - assign n2256 = n2255 | (pksi_140_ & n1327_1 & n1332_1); - assign n2257 = pstart_0_ & (pencrypt_0_ ? pkey_77_ : pkey_85_); - assign n2258 = n2257 | (n_n2474 & n1327_1 & n1332_1); - assign n2259 = pstart_0_ & (pencrypt_0_ ? pkey_102_ : pkey_110_); - assign n2260 = n2259 | (n_n168 & n1327_1 & n1332_1); - assign n2261 = pstart_0_ & (pencrypt_0_ ? pkey_5_ : pkey_13_); - assign n2262 = n2261 | (pksi_108_ & n1327_1 & n1332_1); - assign n2263 = pstart_0_ & (pencrypt_0_ ? pkey_251_ : pkey_194_); - assign n2264 = n2263 | (n_n2268 & n1327_1 & n1332_1); - assign n2265 = pstart_0_ & (pencrypt_0_ ? pkey_229_ : pkey_237_); - assign n2266 = n2265 | (pksi_175_ & n1327_1 & n1332_1); - assign n2267 = pstart_0_ & (pencrypt_0_ ? pkey_238_ : pkey_246_); - assign n2268 = n2267 | (pksi_170_ & n1327_1 & n1332_1); - assign n2269 = pstart_0_ & (pencrypt_0_ ? pkey_148_ : pkey_156_); - assign n2270 = n2269 | (pksi_164_ & n1327_1 & n1332_1); - assign n2271 = pstart_0_ & (pencrypt_0_ ? pkey_157_ : pkey_165_); - assign n2272 = n2271 | (pksi_144_ & n1327_1 & n1332_1); - assign n2273 = pstart_0_ & (pencrypt_0_ ? pkey_166_ : pkey_174_); - assign n2274 = n2273 | (pksi_167_ & n1327_1 & n1332_1); - assign n2275 = pstart_0_ & (pencrypt_0_ ? pkey_76_ : pkey_84_); - assign n2276 = n2275 | (pksi_128_ & n1327_1 & n1332_1); - assign n2277 = pstart_0_ & (pencrypt_0_ ? pkey_85_ : pkey_93_); - assign n2278 = n2277 | (n_n2474 & ~n1327_1 & n1332_1); - assign n2279 = pstart_0_ & (pencrypt_0_ ? pkey_94_ : pkey_102_); - assign n2280 = n2279 | (pksi_130_ & n1327_1 & n1332_1); - assign n2281 = pstart_0_ & (pencrypt_0_ ? pkey_22_ : pkey_30_); - assign n2282 = n2281 | (n_n2517 & ~n1327_1 & n1332_1); - assign n2283 = pstart_0_ & (pencrypt_0_ ? pkey_136_ : pkey_144_); - assign n2284 = n2283 | (pksi_67_ & n1327_1 & n1332_1); - assign n2285 = pstart_0_ & (pencrypt_0_ ? pkey_66_ : pkey_74_); - assign n2286 = n2285 | (n_n2333 & ~n1327_1 & n1332_1); - assign n2287 = pstart_0_ & (pencrypt_0_ ? pkey_89_ : pkey_97_); - assign n2288 = n2287 | (pksi_46_ & n1327_1 & n1332_1); - assign n2289 = pstart_0_ & (pencrypt_0_ ? pkey_112_ : pkey_120_); - assign n2290 = n2289 | (pksi_47_ & n1327_1 & n1332_1); - assign n2291 = pstart_0_ & (pencrypt_0_ ? pkey_42_ : pkey_50_); - assign n2292 = n2291 | (pksi_13_ & n1327_1 & n1332_1); - assign n2293 = pstart_0_ & (pencrypt_0_ ? pkey_144_ : pkey_152_); - assign n2294 = n2293 | (pksi_57_ & n1327_1 & n1332_1); - assign n2295 = pstart_0_ & (pencrypt_0_ ? pkey_123_ : pkey_66_); - assign n2296 = n2295 | (n_n2333 & n1327_1 & n1332_1); - assign n2297 = pstart_0_ & (pencrypt_0_ ? pkey_97_ : pkey_105_); - assign n2298 = n2297 | (pksi_38_ & n1327_1 & n1332_1); - assign n2299 = pstart_0_ & (pencrypt_0_ ? pkey_104_ : pkey_112_); - assign n2300 = n2299 | (pksi_30_ & n1327_1 & n1332_1); - assign n2301 = pstart_0_ & (pencrypt_0_ ? pkey_50_ : pkey_58_); - assign n2302 = n2301 | (n_n2374 & n1327_1 & n1332_1); - assign n2303 = pstart_0_ & (pencrypt_0_ ? pkey_152_ : pkey_160_); - assign n2304 = n2303 | (pksi_53_ & n1327_1 & n1332_1); - assign n2305 = pstart_0_ & (pencrypt_0_ ? pkey_82_ : pkey_90_); - assign n2306 = n2305 | (n_n2337 & n1327_1 & n1332_1); - assign n2307 = pstart_0_ & (pencrypt_0_ ? pkey_73_ : pkey_81_); - assign n2308 = n2307 | (pksi_32_ & n1327_1 & n1332_1); - assign n2309 = pstart_0_ & (pencrypt_0_ ? pkey_96_ : pkey_104_); - assign n2310 = n2309 | (pksi_39_ & n1327_1 & n1332_1); - assign n2311 = pstart_0_ & (pencrypt_0_ ? pkey_58_ : pkey_1_); - assign n2312 = n2311 | (n_n2374 & ~n1327_1 & n1332_1); - assign n2313 = pstart_0_ & (pencrypt_0_ ? pkey_56_ : pkey_227_); - assign n2314 = n2313 | (pksi_4_ & n1327_1 & n1332_1); - assign n2315 = pstart_0_ & (pencrypt_0_ ? pkey_160_ : pkey_168_); - assign n2316 = n2315 | (pksi_63_ & n1327_1 & n1332_1); - assign n2317 = pstart_0_ & (pencrypt_0_ ? pkey_74_ : pkey_82_); - assign n2318 = n2317 | (pksi_36_ & n1327_1 & n1332_1); - assign n2319 = pstart_0_ & (pencrypt_0_ ? pkey_81_ : pkey_89_); - assign n2320 = n2319 | (pksi_24_ & n1327_1 & n1332_1); - assign n2321 = pstart_0_ & (pencrypt_0_ ? pkey_88_ : pkey_96_); - assign n2322 = n2321 | (pksi_29_ & n1327_1 & n1332_1); - assign n2323 = pstart_0_ & (pencrypt_0_ ? pkey_1_ : pkey_9_); - assign n2324 = n2323 | (pksi_18_ & n1327_1 & n1332_1); - assign n2325 = pstart_0_ & (pencrypt_0_ ? pkey_234_ : pkey_242_); - assign n2326 = n2325 | (pksi_85_ & n1327_1 & n1332_1); - assign n2327 = pstart_0_ & (pencrypt_0_ ? pkey_192_ : pkey_200_); - assign n2328 = n2327 | (pksi_89_ & n1327_1 & n1332_1); - assign n2329 = pstart_0_ & (pencrypt_0_ ? pkey_187_ : pkey_130_); - assign n2330 = n2329 | (n_n2301 & n1327_1 & n1332_1); - assign n2331 = pstart_0_ & (pencrypt_0_ ? pkey_145_ : pkey_153_); - assign n2332 = n2331 | (pksi_48_ & n1327_1 & n1332_1); - assign n2333 = pstart_0_ & (pencrypt_0_ ? pkey_9_ : pkey_17_); - assign n2334 = n2333 | (pksi_8_ & n1327_1 & n1332_1); - assign n2335 = pstart_0_ & (pencrypt_0_ ? pkey_242_ : pkey_250_); - assign n2336 = n2335 | (n_n2277 & n1327_1 & n1332_1); - assign n2337 = pstart_0_ & (pencrypt_0_ ? pkey_249_ : pkey_192_); - assign n2338 = n2337 | (n_n2288 & n1327_1 & n1332_1); - assign n2339 = pstart_0_ & (pencrypt_0_ ? pkey_130_ : pkey_138_); - assign n2340 = n2339 | (pksi_51_ & n1327_1 & n1332_1); - assign n2341 = pstart_0_ & (pencrypt_0_ ? pkey_137_ : pkey_145_); - assign n2342 = n2341 | (pksi_56_ & n1327_1 & n1332_1); - assign n2343 = pstart_0_ & (pencrypt_0_ ? pkey_17_ : pkey_25_); - assign n2344 = n2343 | (pksi_0_ & n1327_1 & n1332_1); - assign n2345 = pstart_0_ & (pencrypt_0_ ? pkey_250_ : pkey_193_); - assign n2346 = n2345 | (n_n2277 & ~n1327_1 & n1332_1); - assign n2347 = pstart_0_ & (pencrypt_0_ ? pkey_208_ : pkey_216_); - assign n2348 = n2347 | (pksi_81_ & n1327_1 & n1332_1); - assign n2349 = pstart_0_ & (pencrypt_0_ ? pkey_171_ : pkey_179_); - assign n2350 = n2349 | (pksi_68_ & n1327_1 & n1332_1); - assign n2351 = pstart_0_ & (pencrypt_0_ ? pkey_129_ : pkey_137_); - assign n2352 = n2351 | (pksi_66_ & n1327_1 & n1332_1); - assign n2353 = pstart_0_ & (pencrypt_0_ ? pkey_193_ : pkey_201_); - assign n2354 = n2353 | (n_n2280 & n1327_1 & n1332_1); - assign n2355 = pstart_0_ & (pencrypt_0_ ? pkey_200_ : pkey_208_); - assign n2356 = n2355 | (pksi_91_ & n1327_1 & n1332_1); - assign n2357 = pstart_0_ & (pencrypt_0_ ? pkey_179_ : pkey_187_); - assign n2358 = n2357 | (pksi_64_ & n1327_1 & n1332_1); - assign n2359 = pstart_0_ & (pencrypt_0_ ? pkey_186_ : pkey_129_); - assign n2360 = n2359 | (pksi_49_ & n1327_1 & n1332_1); - assign n2361 = pstart_0_ & (pencrypt_0_ ? pkey_201_ : pkey_209_); - assign n2362 = n2361 | (pksi_80_ & n1327_1 & n1332_1); - assign n2363 = pstart_0_ & (pencrypt_0_ ? pkey_224_ : pkey_232_); - assign n2364 = n2363 | (pksi_87_ & n1327_1 & n1332_1); - assign n2365 = pstart_0_ & (pencrypt_0_ ? pkey_154_ : pkey_162_); - assign n2366 = n2365 | (pksi_58_ & n1327_1 & n1332_1); - assign n2367 = pstart_0_ & (pencrypt_0_ ? pkey_177_ : pkey_185_); - assign n2368 = n2367 | (pksi_59_ & n1327_1 & n1332_1); - assign n2369 = pstart_0_ & (pencrypt_0_ ? pkey_107_ : pkey_115_); - assign n2370 = n2369 | (pksi_44_ & n1327_1 & n1332_1); - assign n2371 = pstart_0_ & (pencrypt_0_ ? pkey_65_ : pkey_73_); - assign n2372 = n2371 | (pksi_42_ & n1327_1 & n1332_1); - assign n2373 = pstart_0_ & (pencrypt_0_ ? pkey_209_ : pkey_217_); - assign n2374 = n2373 | (pksi_72_ & n1327_1 & n1332_1); - assign n2375 = pstart_0_ & (pencrypt_0_ ? pkey_216_ : pkey_224_); - assign n2376 = n2375 | (pksi_77_ & n1327_1 & n1332_1); - assign n2377 = pstart_0_ & (pencrypt_0_ ? pkey_162_ : pkey_170_); - assign n2378 = n2377 | (pksi_69_ & n1327_1 & n1332_1); - assign n2379 = pstart_0_ & (pencrypt_0_ ? pkey_169_ : pkey_177_); - assign n2380 = n2379 | (pksi_50_ & n1327_1 & n1332_1); - assign n2381 = pstart_0_ & (pencrypt_0_ ? pkey_115_ : pkey_123_); - assign n2382 = n2381 | (pksi_40_ & n1327_1 & n1332_1); - assign n2383 = pstart_0_ & (pencrypt_0_ ? pkey_122_ : pkey_65_); - assign n2384 = n2383 | (n_n2342 & ~n1327_1 & n1332_1); - assign n2385 = pstart_0_ & (pencrypt_0_ ? pkey_217_ : pkey_225_); - assign n2386 = n2385 | (pksi_94_ & n1327_1 & n1332_1); - assign n2387 = pstart_0_ & (pencrypt_0_ ? pkey_240_ : pkey_248_); - assign n2388 = n2387 | (pksi_95_ & n1327_1 & n1332_1); - assign n2389 = pstart_0_ & (pencrypt_0_ ? pkey_138_ : pkey_146_); - assign n2390 = n2389 | (pksi_60_ & n1327_1 & n1332_1); - assign n2391 = pstart_0_ & (pencrypt_0_ ? pkey_161_ : pkey_169_); - assign n2392 = n2391 | (pksi_62_ & n1327_1 & n1332_1); - assign n2393 = pstart_0_ & (pencrypt_0_ ? pkey_72_ : pkey_80_); - assign n2394 = n2393 | (pksi_43_ & n1327_1 & n1332_1); - assign n2395 = pstart_0_ & (pencrypt_0_ ? pkey_2_ : pkey_10_); - assign n2396 = n2395 | (n_n2365 & ~n1327_1 & n1332_1); - assign n2397 = pstart_0_ & (pencrypt_0_ ? pkey_225_ : pkey_233_); - assign n2398 = n2397 | (pksi_86_ & n1327_1 & n1332_1); - assign n2399 = pstart_0_ & (pencrypt_0_ ? pkey_232_ : pkey_240_); - assign n2400 = n2399 | (pksi_78_ & n1327_1 & n1332_1); - assign n2401 = pstart_0_ & (pencrypt_0_ ? pkey_146_ : pkey_154_); - assign n2402 = n2401 | (n_n2305 & n1327_1 & n1332_1); - assign n2403 = pstart_0_ & (pencrypt_0_ ? pkey_153_ : pkey_161_); - assign n2404 = n2403 | (pksi_70_ & n1327_1 & n1332_1); - assign n2405 = pstart_0_ & (pencrypt_0_ ? pkey_80_ : pkey_88_); - assign n2406 = n2405 | (pksi_33_ & n1327_1 & n1332_1); - assign n2407 = pstart_0_ & (pencrypt_0_ ? pkey_59_ : pkey_2_); - assign n2408 = n2407 | (n_n2365 & n1327_1 & n1332_1); - assign n2409 = pstart_0_ & (pencrypt_0_ ? pkey_233_ : pkey_241_); - assign n2410 = n2409 | (pksi_74_ & n1327_1 & n1332_1); - assign n2411 = pstart_0_ & (pencrypt_0_ ? pkey_163_ : pkey_171_); - assign n2412 = n2411 | (pksi_55_ & n1327_1 & n1332_1); - assign n2413 = pstart_0_ & (pencrypt_0_ ? pkey_168_ : pkey_176_); - assign n2414 = n2413 | (pksi_54_ & n1327_1 & n1332_1); - assign n2415 = pstart_0_ & (pencrypt_0_ ? pkey_98_ : pkey_106_); - assign n2416 = n2415 | (pksi_45_ & n1327_1 & n1332_1); - assign n2417 = pstart_0_ & (pencrypt_0_ ? pkey_121_ : pkey_64_); - assign n2418 = n2417 | (n_n2352 & n1327_1 & n1332_1); - assign n2419 = pstart_0_ & (pencrypt_0_ ? pkey_51_ : pkey_59_); - assign n2420 = n2419 | (pksi_16_ & n1327_1 & n1332_1); - assign n2421 = pstart_0_ & (pencrypt_0_ ? pkey_10_ : pkey_18_); - assign n2422 = n2421 | (pksi_12_ & n1327_1 & n1332_1); - assign n2423 = pstart_0_ & (pencrypt_0_ ? pkey_241_ : pkey_249_); - assign n2424 = n2423 | (pksi_83_ & n1327_1 & n1332_1); - assign n2425 = pstart_0_ & (pencrypt_0_ ? pkey_248_ : pkey_163_); - assign n2426 = n2425 | (pksi_76_ & n1327_1 & n1332_1); - assign n2427 = pstart_0_ & (pencrypt_0_ ? pkey_176_ : pkey_184_); - assign n2428 = n2427 | (pksi_71_ & n1327_1 & n1332_1); - assign n2429 = pstart_0_ & (pencrypt_0_ ? pkey_90_ : pkey_98_); - assign n2430 = n2429 | (n_n2337 & ~n1327_1 & n1332_1); - assign n2431 = pstart_0_ & (pencrypt_0_ ? pkey_64_ : pkey_72_); - assign n2432 = n2431 | (n_n2352 & ~n1327_1 & n1332_1); - assign n2433 = pstart_0_ & (pencrypt_0_ ? pkey_43_ : pkey_51_); - assign n2434 = n2433 | (pksi_20_ & n1327_1 & n1332_1); - assign n2435 = pstart_0_ & (pencrypt_0_ ? pkey_18_ : pkey_26_); - assign n2436 = n2435 | (n_n2369 & n1327_1 & n1332_1); - assign n2437 = pstart_0_ & (pencrypt_0_ ? pkey_170_ : pkey_178_); - assign n2438 = n2437 | (pksi_61_ & n1327_1 & n1332_1); - assign n2439 = pstart_0_ & (pencrypt_0_ ? pkey_128_ : pkey_136_); - assign n2440 = n2439 | (n_n2320 & ~n1327_1 & n1332_1); - assign n2441 = pstart_0_ & (pencrypt_0_ ? pkey_184_ : pkey_99_); - assign n2442 = n2441 | (pksi_52_ & n1327_1 & n1332_1); - assign n2443 = pstart_0_ & (pencrypt_0_ ? pkey_114_ : pkey_122_); - assign n2444 = n2443 | (n_n2342 & n1327_1 & n1332_1); - assign n2445 = pstart_0_ & (pencrypt_0_ ? pkey_105_ : pkey_113_); - assign n2446 = n2445 | (pksi_26_ & n1327_1 & n1332_1); - assign n2447 = pstart_0_ & (pencrypt_0_ ? pkey_35_ : pkey_43_); - assign n2448 = n2447 | (pksi_7_ & n1327_1 & n1332_1); - assign n2449 = pstart_0_ & (pencrypt_0_ ? pkey_26_ : pkey_34_); - assign n2450 = n2449 | (n_n2369 & ~n1327_1 & n1332_1); - assign n2451 = pstart_0_ & (pencrypt_0_ ? pkey_178_ : pkey_186_); - assign n2452 = n2451 | (n_n2310 & n1327_1 & n1332_1); - assign n2453 = pstart_0_ & (pencrypt_0_ ? pkey_185_ : pkey_128_); - assign n2454 = n2453 | (n_n2320 & n1327_1 & n1332_1); - assign n2455 = pstart_0_ & (pencrypt_0_ ? pkey_99_ : pkey_107_); - assign n2456 = n2455 | (pksi_31_ & n1327_1 & n1332_1); - assign n2457 = pstart_0_ & (pencrypt_0_ ? pkey_106_ : pkey_114_); - assign n2458 = n2457 | (pksi_37_ & n1327_1 & n1332_1); - assign n2459 = pstart_0_ & (pencrypt_0_ ? pkey_113_ : pkey_121_); - assign n2460 = n2459 | (pksi_35_ & n1327_1 & n1332_1); - assign n2461 = pstart_0_ & (pencrypt_0_ ? pkey_120_ : pkey_35_); - assign n2462 = n2461 | (pksi_28_ & n1327_1 & n1332_1); - assign n2463 = pstart_0_ & (pencrypt_0_ ? pkey_34_ : pkey_42_); - assign n2464 = n2463 | (pksi_21_ & n1327_1 & n1332_1); - assign n2465 = ~pencrypt_0_ & ~pstart_0_ & ~pcount_1_ & ~pcount_0_; - assign n2466 = pcount_2_ ? ~pencrypt_0_ : (~pstart_0_ & pencrypt_0_); - assign n2467 = n1341 | ~n1330 | (~pcount_2_ & n1329); - always @ (posedge clock) begin - pksi_17_ <= n853; - pksi_185_ <= n857; - n_n2410 <= n861; - pksi_170_ <= n866; - pksi_155_ <= n870; - pksi_147_ <= n874; - pksi_109_ <= n878; - n_n2513 <= n882; - pksi_19_ <= n887; - n_n2396 <= n891; - n_n2412 <= n896; - n_n121 <= n901; - pksi_148_ <= n906; - n_n2448 <= n910; - pksi_107_ <= n915; - pksi_110_ <= n919; - pksi_9_ <= n923; - pksi_176_ <= n927; - pksi_180_ <= n931; - pksi_178_ <= n935; - pksi_135_ <= n939; - pksi_129_ <= n943; - pksi_100_ <= n947; - pksi_117_ <= n951; - pksi_118_ <= n955; - pksi_5_ <= n959; - pksi_169_ <= n963; - n_n2408 <= n967; - pksi_184_ <= n972; - pksi_125_ <= n976; - pksi_138_ <= n980; - pksi_114_ <= n984; - pksi_99_ <= n988; - pksi_85_ <= n992; - pksi_14_ <= n996; - pksi_4_ <= n1000; - pksi_186_ <= n1004; - n_n2420 <= n1008; - pksi_141_ <= n1013; - pksi_113_ <= n1017; - pksi_115_ <= n1021; - pksi_98_ <= n1025; - pksi_2_ <= n1029; - pksi_23_ <= n1033; - pksi_177_ <= n1037; - pksi_189_ <= n1041; - n_n2485 <= n1045; - n_n2495 <= n1050; - pksi_97_ <= n1055; - pksi_102_ <= n1059; - pksi_11_ <= n1063; - pksi_173_ <= n1067; - pksi_179_ <= n1071; - pksi_171_ <= n1075; - pksi_104_ <= n1079; - pksi_103_ <= n1083; - n_n2384 <= n1087; - pksi_183_ <= n1092; - pksi_172_ <= n1096; - n_n2416 <= n1100; - pksi_116_ <= n1105; - pksi_96_ <= n1109; - pksi_119_ <= n1113; - pksi_84_ <= n1117; - pksi_159_ <= n1121; - n_n2440 <= n1125; - pksi_160_ <= n1130; - pksi_128_ <= n1134; - pksi_127_ <= n1138; - pksi_142_ <= n1142; - n_n2272 <= n1146; - pksi_149_ <= n1151; - pksi_162_ <= n1155; - pksi_154_ <= n1159; - pksi_121_ <= n1163; - pksi_134_ <= n1167; - pksi_126_ <= n1171; - pksi_82_ <= n1175; - n_n2430 <= n1179; - pksi_153_ <= n1184; - pksi_165_ <= n1188; - pksi_137_ <= n1192; - n_n2481 <= n1196; - pksi_101_ <= n1201; - pksi_93_ <= n1205; - pksi_161_ <= n1209; - pksi_156_ <= n1213; - n_n2452 <= n1217; - n_n2462 <= n1222; - pksi_123_ <= n1227; - pksi_111_ <= n1231; - pksi_92_ <= n1235; - pksi_15_ <= n1239; - n_n109 <= n1243; - pksi_145_ <= n1248; - pksi_144_ <= n1252; - pksi_150_ <= n1256; - pksi_124_ <= n1260; - pksi_132_ <= n1264; - pksi_130_ <= n1268; - pksi_105_ <= n1272; - pksi_112_ <= n1276; - n_n10 <= n1280; - pksi_6_ <= n1285; - pksi_188_ <= n1289; - pksi_152_ <= n1293; - pksi_163_ <= n1297; - pksi_166_ <= n1301; - pksi_131_ <= n1305; - n_n2474 <= n1309; - pksi_136_ <= n1314; - pksi_108_ <= n1318; - n_n2517 <= n1322; - n_n2268 <= n1327; - pksi_175_ <= n1332; - pksi_190_ <= n1336; - pksi_164_ <= n1340; - pksi_158_ <= n1344; - pksi_167_ <= n1348; - pksi_133_ <= n1352; - n_n2476 <= n1356; - pksi_122_ <= n1361; - n_n2507 <= n1365; - pksi_75_ <= n1370; - pksi_182_ <= n1374; - pksi_174_ <= n1378; - pksi_157_ <= n1382; - pksi_151_ <= n1386; - pksi_146_ <= n1390; - pksi_140_ <= n1394; - pksi_120_ <= n1398; - n_n168 <= n1402; - pksi_106_ <= n1407; - pksi_57_ <= n1411; - pksi_36_ <= n1415; - pksi_38_ <= n1419; - pksi_28_ <= n1423; - n_n2374 <= n1427; - pksi_53_ <= n1432; - pksi_27_ <= n1436; - pksi_26_ <= n1440; - pksi_47_ <= n1444; - pksi_1_ <= n1448; - pksi_63_ <= n1452; - pksi_34_ <= n1456; - pksi_24_ <= n1460; - pksi_30_ <= n1464; - pksi_18_ <= n1468; - pksi_79_ <= n1472; - pksi_54_ <= n1476; - n_n2337 <= n1480; - pksi_46_ <= n1485; - pksi_39_ <= n1489; - pksi_8_ <= n1493; - n_n2277 <= n1497; - pksi_91_ <= n1502; - pksi_51_ <= n1506; - pksi_70_ <= n1510; - pksi_0_ <= n1514; - pksi_73_ <= n1518; - pksi_89_ <= n1522; - pksi_60_ <= n1526; - pksi_48_ <= n1530; - pksi_22_ <= n1534; - n_n2280 <= n1538; - pksi_77_ <= n1543; - pksi_64_ <= n1547; - pksi_56_ <= n1551; - pksi_80_ <= n1555; - pksi_81_ <= n1559; - n_n2301 <= n1563; - pksi_66_ <= n1568; - pksi_72_ <= n1572; - pksi_78_ <= n1576; - pksi_69_ <= n1580; - n_n2320 <= n1584; - pksi_40_ <= n1589; - pksi_32_ <= n1593; - pksi_94_ <= n1597; - pksi_87_ <= n1601; - pksi_61_ <= n1605; - pksi_59_ <= n1609; - n_n2333 <= n1613; - pksi_42_ <= n1618; - pksi_86_ <= n1622; - pksi_76_ <= n1626; - n_n2305 <= n1630; - pksi_50_ <= n1635; - pksi_33_ <= n1639; - pksi_12_ <= n1643; - pksi_74_ <= n1647; - pksi_95_ <= n1651; - pksi_58_ <= n1655; - pksi_62_ <= n1659; - pksi_29_ <= n1663; - pksi_3_ <= n1667; - pksi_83_ <= n1671; - pksi_68_ <= n1675; - pksi_71_ <= n1679; - pksi_37_ <= n1683; - pksi_41_ <= n1687; - n_n2365 <= n1691; - n_n2369 <= n1696; - n_n2288 <= n1701; - pksi_55_ <= n1706; - pksi_52_ <= n1710; - pksi_45_ <= n1714; - pksi_43_ <= n1718; - pksi_16_ <= n1722; - pksi_10_ <= n1726; - n_n2310 <= n1730; - pksi_67_ <= n1735; - pksi_31_ <= n1739; - pksi_25_ <= n1743; - pksi_35_ <= n1747; - pksi_20_ <= n1751; - pksi_21_ <= n1755; - pksi_49_ <= n1759; - pksi_65_ <= n1763; - pksi_44_ <= n1767; - n_n2342 <= n1771; - n_n2352 <= n1776; - pksi_7_ <= n1781; - pksi_13_ <= n1785; - end -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/elliptic/elliptic.v b/fpga_flow/benchmarks/Verilog/MCNC/elliptic/elliptic.v deleted file mode 100644 index 34435cafd..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/elliptic/elliptic.v +++ /dev/null @@ -1,5343 +0,0 @@ -// Benchmark "top" written by ABC on Thu Feb 21 17:22:32 2019 - -module elliptic ( clock, - tin_psv39_8_8_, tin_psv39_0_0_, tin_psv13_5_5_, tin_psv2_13_13_, - tin_psv2_8_8_, pinp_2_2_, tin_psv38_2_2_, tin_psv33_5_5_, - tin_psv26_6_6_, tin_psv2_9_9_, pinp_3_3_, tin_psv18_2_2_, - tin_psv39_9_9_, tin_psv39_1_1_, tin_psv13_6_6_, tin_psv2_6_6_, - pinp_0_0_, tin_psv38_3_3_, tin_psv33_6_6_, tin_psv26_13_13_, - tin_psv26_12_12_, tin_psv26_7_7_, tin_psv2_7_7_, pinp_1_1_, - preset_0_0_, tin_psv18_3_3_, tin_psv39_2_2_, tin_psv33_12_12_, - tin_psv33_11_11_, tin_psv33_10_10_, tin_psv13_7_7_, tin_psv2_10_10_, - tin_psv38_4_4_, tin_psv39_10_10_, tin_psv33_7_7_, tin_psv26_15_15_, - tin_psv26_14_14_, tin_psv26_8_8_, tin_psv26_0_0_, tin_psv13_12_12_, - tin_psv13_11_11_, tin_psv18_4_4_, tin_psv39_3_3_, tin_psv13_8_8_, - tin_psv13_0_0_, pinp_15_15_, pinp_12_12_, tin_psv38_5_5_, - tin_psv33_8_8_, tin_psv33_0_0_, tin_psv26_9_9_, tin_psv26_1_1_, - tin_psv13_10_10_, tin_psv18_5_5_, tin_psv39_4_4_, tin_psv13_9_9_, - tin_psv13_1_1_, tin_psv2_15_15_, tin_psv2_11_11_, tin_psv2_0_0_, - tin_psv38_14_14_, tin_psv38_12_12_, tin_psv38_10_10_, tin_psv38_6_6_, - tin_psv18_15_15_, tin_psv18_13_13_, tin_psv18_11_11_, tin_psv33_9_9_, - tin_psv33_1_1_, tin_psv26_2_2_, tin_psv2_1_1_, pclk, tin_psv38_15_15_, - tin_psv38_11_11_, tin_psv18_12_12_, tin_psv18_6_6_, tin_psv39_5_5_, - tin_psv13_2_2_, pinp_14_14_, pinp_11_11_, pinp_8_8_, tin_psv38_7_7_, - tin_psv39_12_12_, tin_psv39_11_11_, tin_psv33_2_2_, tin_psv26_3_3_, - tin_psv13_14_14_, tin_psv13_13_13_, pinp_9_9_, tin_psv18_10_10_, - tin_psv18_7_7_, tin_psv39_6_6_, tin_psv33_15_15_, tin_psv33_14_14_, - tin_psv33_13_13_, tin_psv13_3_3_, tin_psv2_14_14_, tin_psv2_12_12_, - tin_psv2_4_4_, pinp_6_6_, tin_psv38_8_8_, tin_psv38_0_0_, - tin_psv39_14_14_, tin_psv39_13_13_, tin_psv33_3_3_, tin_psv26_11_11_, - tin_psv26_10_10_, tin_psv26_4_4_, tin_psv13_15_15_, tin_psv2_5_5_, - pinp_7_7_, tin_psv18_8_8_, tin_psv18_0_0_, tin_psv39_7_7_, - tin_psv13_4_4_, tin_psv2_2_2_, pinp_13_13_, pinp_10_10_, pinp_4_4_, - tin_psv38_9_9_, tin_psv38_1_1_, preset, tin_psv39_15_15_, - tin_psv33_4_4_, tin_psv26_5_5_, tin_psv2_3_3_, pinp_5_5_, - tin_psv38_13_13_, tin_psv18_14_14_, tin_psv18_9_9_, tin_psv18_1_1_, - psv39_8_8_, psv39_0_0_, psv13_5_5_, psv2_13_13_, psv2_8_8_, psv38_2_2_, - psv33_5_5_, psv26_6_6_, psv2_9_9_, psv18_2_2_, psv39_9_9_, psv39_1_1_, - psv13_6_6_, psv2_6_6_, psv38_3_3_, psv33_6_6_, psv26_13_13_, - psv26_12_12_, psv26_7_7_, psv2_7_7_, psv18_3_3_, psv39_2_2_, - psv33_12_12_, psv33_11_11_, psv33_10_10_, psv13_7_7_, psv2_10_10_, - psv38_4_4_, psv39_10_10_, psv33_7_7_, psv26_15_15_, psv26_14_14_, - psv26_8_8_, psv26_0_0_, psv13_12_12_, psv13_11_11_, psv18_4_4_, - psv39_3_3_, psv13_8_8_, psv13_0_0_, psv38_5_5_, psv33_8_8_, psv33_0_0_, - psv26_9_9_, psv26_1_1_, psv13_10_10_, psv18_5_5_, psv39_4_4_, - psv13_9_9_, psv13_1_1_, psv2_15_15_, psv2_11_11_, psv2_0_0_, - psv38_14_14_, psv38_12_12_, psv38_10_10_, psv38_6_6_, psv18_15_15_, - psv18_13_13_, psv18_11_11_, psv33_9_9_, psv33_1_1_, psv26_2_2_, - psv2_1_1_, psv38_15_15_, psv38_11_11_, psv18_12_12_, psv18_6_6_, - psv39_5_5_, psv13_2_2_, pover_0_0_, psv38_7_7_, psv39_12_12_, - psv39_11_11_, psv33_2_2_, psv26_3_3_, psv13_14_14_, psv13_13_13_, - psv18_10_10_, psv18_7_7_, psv39_6_6_, psv33_15_15_, psv33_14_14_, - psv33_13_13_, psv13_3_3_, psv2_14_14_, psv2_12_12_, psv2_4_4_, - psv38_8_8_, psv38_0_0_, pdn, psv39_14_14_, psv39_13_13_, psv33_3_3_, - psv26_11_11_, psv26_10_10_, psv26_4_4_, psv13_15_15_, psv2_5_5_, - psv18_8_8_, psv18_0_0_, psv39_7_7_, psv13_4_4_, psv2_2_2_, psv38_9_9_, - psv38_1_1_, psv39_15_15_, psv33_4_4_, psv26_5_5_, psv2_3_3_, - psv38_13_13_, psv18_14_14_, psv18_9_9_, psv18_1_1_ ); - input clock, tin_psv39_8_8_, tin_psv39_0_0_, tin_psv13_5_5_, tin_psv2_13_13_, - tin_psv2_8_8_, pinp_2_2_, tin_psv38_2_2_, tin_psv33_5_5_, - tin_psv26_6_6_, tin_psv2_9_9_, pinp_3_3_, tin_psv18_2_2_, - tin_psv39_9_9_, tin_psv39_1_1_, tin_psv13_6_6_, tin_psv2_6_6_, - pinp_0_0_, tin_psv38_3_3_, tin_psv33_6_6_, tin_psv26_13_13_, - tin_psv26_12_12_, tin_psv26_7_7_, tin_psv2_7_7_, pinp_1_1_, - preset_0_0_, tin_psv18_3_3_, tin_psv39_2_2_, tin_psv33_12_12_, - tin_psv33_11_11_, tin_psv33_10_10_, tin_psv13_7_7_, tin_psv2_10_10_, - tin_psv38_4_4_, tin_psv39_10_10_, tin_psv33_7_7_, tin_psv26_15_15_, - tin_psv26_14_14_, tin_psv26_8_8_, tin_psv26_0_0_, tin_psv13_12_12_, - tin_psv13_11_11_, tin_psv18_4_4_, tin_psv39_3_3_, tin_psv13_8_8_, - tin_psv13_0_0_, pinp_15_15_, pinp_12_12_, tin_psv38_5_5_, - tin_psv33_8_8_, tin_psv33_0_0_, tin_psv26_9_9_, tin_psv26_1_1_, - tin_psv13_10_10_, tin_psv18_5_5_, tin_psv39_4_4_, tin_psv13_9_9_, - tin_psv13_1_1_, tin_psv2_15_15_, tin_psv2_11_11_, tin_psv2_0_0_, - tin_psv38_14_14_, tin_psv38_12_12_, tin_psv38_10_10_, tin_psv38_6_6_, - tin_psv18_15_15_, tin_psv18_13_13_, tin_psv18_11_11_, tin_psv33_9_9_, - tin_psv33_1_1_, tin_psv26_2_2_, tin_psv2_1_1_, pclk, tin_psv38_15_15_, - tin_psv38_11_11_, tin_psv18_12_12_, tin_psv18_6_6_, tin_psv39_5_5_, - tin_psv13_2_2_, pinp_14_14_, pinp_11_11_, pinp_8_8_, tin_psv38_7_7_, - tin_psv39_12_12_, tin_psv39_11_11_, tin_psv33_2_2_, tin_psv26_3_3_, - tin_psv13_14_14_, tin_psv13_13_13_, pinp_9_9_, tin_psv18_10_10_, - tin_psv18_7_7_, tin_psv39_6_6_, tin_psv33_15_15_, tin_psv33_14_14_, - tin_psv33_13_13_, tin_psv13_3_3_, tin_psv2_14_14_, tin_psv2_12_12_, - tin_psv2_4_4_, pinp_6_6_, tin_psv38_8_8_, tin_psv38_0_0_, - tin_psv39_14_14_, tin_psv39_13_13_, tin_psv33_3_3_, tin_psv26_11_11_, - tin_psv26_10_10_, tin_psv26_4_4_, tin_psv13_15_15_, tin_psv2_5_5_, - pinp_7_7_, tin_psv18_8_8_, tin_psv18_0_0_, tin_psv39_7_7_, - tin_psv13_4_4_, tin_psv2_2_2_, pinp_13_13_, pinp_10_10_, pinp_4_4_, - tin_psv38_9_9_, tin_psv38_1_1_, preset, tin_psv39_15_15_, - tin_psv33_4_4_, tin_psv26_5_5_, tin_psv2_3_3_, pinp_5_5_, - tin_psv38_13_13_, tin_psv18_14_14_, tin_psv18_9_9_, tin_psv18_1_1_; - output psv39_8_8_, psv39_0_0_, psv13_5_5_, psv2_13_13_, psv2_8_8_, - psv38_2_2_, psv33_5_5_, psv26_6_6_, psv2_9_9_, psv18_2_2_, psv39_9_9_, - psv39_1_1_, psv13_6_6_, psv2_6_6_, psv38_3_3_, psv33_6_6_, - psv26_13_13_, psv26_12_12_, psv26_7_7_, psv2_7_7_, psv18_3_3_, - psv39_2_2_, psv33_12_12_, psv33_11_11_, psv33_10_10_, psv13_7_7_, - psv2_10_10_, psv38_4_4_, psv39_10_10_, psv33_7_7_, psv26_15_15_, - psv26_14_14_, psv26_8_8_, psv26_0_0_, psv13_12_12_, psv13_11_11_, - psv18_4_4_, psv39_3_3_, psv13_8_8_, psv13_0_0_, psv38_5_5_, psv33_8_8_, - psv33_0_0_, psv26_9_9_, psv26_1_1_, psv13_10_10_, psv18_5_5_, - psv39_4_4_, psv13_9_9_, psv13_1_1_, psv2_15_15_, psv2_11_11_, - psv2_0_0_, psv38_14_14_, psv38_12_12_, psv38_10_10_, psv38_6_6_, - psv18_15_15_, psv18_13_13_, psv18_11_11_, psv33_9_9_, psv33_1_1_, - psv26_2_2_, psv2_1_1_, psv38_15_15_, psv38_11_11_, psv18_12_12_, - psv18_6_6_, psv39_5_5_, psv13_2_2_, pover_0_0_, psv38_7_7_, - psv39_12_12_, psv39_11_11_, psv33_2_2_, psv26_3_3_, psv13_14_14_, - psv13_13_13_, psv18_10_10_, psv18_7_7_, psv39_6_6_, psv33_15_15_, - psv33_14_14_, psv33_13_13_, psv13_3_3_, psv2_14_14_, psv2_12_12_, - psv2_4_4_, psv38_8_8_, psv38_0_0_, pdn, psv39_14_14_, psv39_13_13_, - psv33_3_3_, psv26_11_11_, psv26_10_10_, psv26_4_4_, psv13_15_15_, - psv2_5_5_, psv18_8_8_, psv18_0_0_, psv39_7_7_, psv13_4_4_, psv2_2_2_, - psv38_9_9_, psv38_1_1_, psv39_15_15_, psv33_4_4_, psv26_5_5_, - psv2_3_3_, psv38_13_13_, psv18_14_14_, psv18_9_9_, psv18_1_1_; - reg n_n9280, n_n9172, n_n9260, n_n7726, n_n8270, n_n8196, n_n9150, - n_n9267, n_n7779, n_n9503, n_n8150, n_n9401, n_n7341, n_n9180, n_n8592, - n_n8871, n_n7252, n_n7271, n_n6991, n_n8557, n_n7707, n_n7552, ndn3_23, - n_n9548, n_n9467, n_n8002, n_n6950, n_n8930, n_n7244, n_n7819, n_n8883, - n_n7709, n_n9580, n_n9130, n_n9486, n_n9235, n_n7522, n_n7373, n_n9085, - n_n9638, n_n7452, n_n8775, n_n7654, n_n8410, n_n8208, n_n8377, n_n7558, - n_n7599, n_n8225, n_n8202, n_n7670, n_n7888, n_n7889, n_n8597, n_n8152, - n_n8394, n_n7812, n_n7816, n_n9141, n_n7332, n_n8758, n_n7765, n_n7877, - n_n7814, n_n9008, n_n7581, n_n7376, n_n7970, pover_0_0_, n_n8599, - n_n8227, n_n9442, n_n9485, n_n7148, n_n9311, n_n9273, ndn3_9, n_n8613, - n_n8533, n_n8699, n_n8609, n_n8308, n_n8655, n_n8981, n_n7583, n_n9198, - n_n9602, n_n8786, n_n9598, n_n7738, n_n8573, n_n9473, n_n9000, n_n8001, - n_n9554, n_n8508, n_n9635, n_n7190, n_n8702, n_n9106, n_n7409, n_n9437, - n_n9052, n_n8647, n_n9265, n_n7179, ndn3_13, ndn3_17, ndn3_25, ndn3_29, - n_n9539, n_n7953, n_n8488, nen3_22, n_n9438, n_n8132, n_n8661, n_n7759, - n_n8333, n_n9399, n_n7798, n_n9434, n_n7910, n_n9528, n_n7850, n_n8251, - n_n7937, n_n8482, n_n9290, n_n8007, n_n7556, n_n9064, n_n9398, n_n9412, - n_n9361, n_n9304, n_n7651, n_n7712, n_n7735, n_n7934, n_n7811, n_n8053, - n_n9015, n_n8066, n_n9518, n_n8091, n_n9257, n_n8175, n_n8491, n_n8114, - n_n7951, n_n8913, n_n8035, n_n8631, n_n8243, n_n7857, ngfdn_3, n_n7791, - n_n9175, n_n9588, n_n9049, n_n9483, n_n9410, n_n7691, n_n7740, n_n7602, - n_n7783, n_n7948, n_n7054, n_n9343, n_n9400, nsr1_2, n_n9127, n_n8531, - n_n9335, n_n7324, n_n9611, n_n8112, n_n9406, n_n9618, n_n9613, n_n9242, - n_n7384, n_n8884, n_n7462, n_n7908, n_n8765, n_n7909, n_n7898, n_n9135, - n_n8862, n_n8037, ndn3_18, ndn3_22, n_n8974, n_n7286, n_n9223, n_n7306, - n_n9169, n_n9125, nen3_39, n_n8278, n_n9557, n_n7758, n_n9391, n_n8110, - n_n9597, n_n8568, n_n7428, n_n7931, n_n7742, n_n7236, n_n8219, n_n9568, - n_n9200, n_n8545, n_n7823, n_n8005, n_n8736, n_n9339, n_n8499, n_n8086, - n_n7803, n_n7640, n_n9098, n_n7160, n_n7713, n_n9566, n_n7955, n_n8414, - n_n8006, n_n9560, n_n8742, n_n7174, n_n8882, n_n7546, n_n8282, n_n8998, - n_n7656, n_n9465, n_n9601, n_n8875, n_n7954, n_n8959, n_n8957, n_n8247, - n_n8258, n_n7641, n_n8843, n_n9321, n_n7702, nsr3_23, n_n8199, n_n7983, - n_n7217, n_n7821, n_n9489, n_n8348, n_n9408, n_n8445, n_n9501, n_n7831, - n_n7757, n_n9174, n_n9432, n_n8678, n_n8024, n_n7806, n_n8996, n_n7918, - n_n8260, n_n9341, n_n9189, n_n9096, ndn3_30, n_n7775, n_n7693, nen3_16, - n_n7643, n_n8941, n_n8042, n_n8681, n_n8659, n_n9110, n_n9573, n_n8951, - n_n9589, n_n9387, n_n8279, n_n7790, n_n8406, n_n8582, n_n7911, n_n7474, - n_n8466, n_n6984, n_n7760, n_n7847, n_n9559, n_n7362, n_n9300, n_n9550, - n_n9492, n_n8777, n_n7764, n_n7826, n_n7777, n_n7824, n_n8173, n_n7498, - n_n9148, n_n8753, n_n8772, n_n8049, n_n9362, ndn1_4, n_n9561, n_n9004, - n_n8203, n_n8153, n_n9263, n_n8369, n_n9331, n_n7454, ndn3_7, n_n7527, - n_n9036, n_n7875, n_n8697, n_n9497, n_n7291, nsr3_13, nsr3_38, n_n8240, - n_n7703, n_n9282, n_n8237, n_n8935, n_n9244, n_n8648, n_n8235, n_n8611, - n_n9045, n_n9334, n_n8572, n_n9491, n_n9134, n_n9555, n_n9336, n_n7050, - n_n9346, n_n7140, n_n7681, n_n6948, n_n8549, ndn3_19, ndn3_28, n_n7102, - n_n8093, n_n9041, n_n8381, n_n8810, nen3_36, n_n9047, n_n9333, n_n7736, - n_n7820, n_n8986, n_n8891, n_n8000, n_n7968, n_n8750, n_n9558, n_n9368, - n_n8519, n_n6956, n_n8298, n_n9397, n_n7017, n_n8638, n_n9552, n_n8964, - n_n8016, n_n7603, n_n7696, n_n8589, n_n9337, n_n9132, n_n8652, n_n8707, - n_n9407, n_n9044, n_n8808, nsr3_30, n_n8274, n_n8615, n_n8238, n_n7854, - n_n8649, n_n8236, n_n8269, n_n9592, n_n8022, n_n8744, n_n8529, n_n7967, - n_n9487, n_n8685, n_n9531, n_n9510, n_n7771, n_n8480, n_n8543, n_n7789, - ndn3_11, ndn3_15, ndn3_21, n_n7584, n_n8354, n_n6952, n_n8864, n_n7930, - n_n7962, n_n7929, n_n9316, n_n9102, n_n7308, n_n7657, n_n9264, n_n8760, - n_n6912, n_n7887, n_n8911, n_n7952, n_n8704, n_n7876, n_n9596, n_n8430, - n_n9019, n_n7699, n_n7375, n_n7936, n_n8340, n_n8809, n_n6961, n_n9429, - n_n7743, n_n8980, n_n7582, n_n8968, n_n9371, n_n8741, n_n9502, n_n9373, - n_n9248, n_n7822, n_n9054, n_n8273, n_n6937, n_n9342, n_n9325, n_n9609, - n_n9623, n_n9470, n_n7570, n_n9310, n_n9366, n_n7181, n_n8739, n_n8939, - n_n7256, n_n8983, n_n7487, n_n9268, n_n8906, n_n7988, n_n9181, n_n8725, - n_n8626, ndn3_27, n_n8210, n_n7415, n_n8900, nen3_19, n_n8762, n_n8512, - n_n8095, n_n8982, n_n7387, n_n9494, n_n7689, n_n7835, n_n9157, n_n8552, - n_n7381, n_n9446, n_n8633, n_n7684, n_n7310, n_n8402, n_n9315, n_n7950, - n_n8504, n_n8456, n_n7514, n_n7315, n_n9476, n_n8276, n_n8833, n_n7923, - n_n9395, n_n9512, n_n9319, nsr3_35, n_n7154, n_n9495, n_n9137, n_n8854, - n_n9183, n_n9323, n_n9349, n_n7896, n_n8073, n_n8970, n_n9314, n_n8486, - n_n7246, n_n7866, n_n9599, n_n7635, n_n8984, n_n7360, n_n8794, n_n9108, - n_n9286, ndn3_12, ndn3_16, n_n7708, n_n7807, n_n7650, n_n7947, n_n9500, - n_n7734, n_n8464, n_n7659, n_n7630, n_n7756, n_n8691, n_n9176, n_n9327, - n_n7995, n_n7395, n_n7878, n_n7507, n_n7959, n_n7825, n_n8009, n_n8281, - n_n7685, n_n8106, n_n7687, n_n7766, n_n7880, n_n8961, n_n8014, n_n9278, - n_n9087, n_n9182, n_n7852, n_n9324, nak3_13, n_n9416, nsr3_14, n_n8603, - n_n7026, n_n8856, n_n8272, n_n9312, n_n7985, n_n8312, n_n7231, n_n9396, - n_n8801, n_n8683, ndn3_39, n_n8245, n_n9458, n_n9302, n_n7392, n_n6963, - n_n7808, n_n7225, n_n7817, n_n8201, n_n7793, n_n8177, n_n8389, n_n9440, - n_n7683, n_n7761, n_n7667, n_n7980, n_n7509, n_n7813, n_n8396, n_n9535, - n_n7209, n_n7003, n_n7695, n_n7624, n_n8791, n_n7374, n_n7429, n_n7944, - n_n9266, n_n8100, n_n6988, n_n6986, n_n8933, n_n7117, n_n9043, n_n8241, - n_n9219, n_n8198, n_n8081, n_n8575, n_n8710, n_n7622, n_n7966, n_n7885, - n_n7033, ndn3_34, n_n9186, ndn3_50, n_n7879, n_n7019, n_n9171, n_n7261, - n_n8223, n_n8989, n_n7993, n_n7845, n_n8253, n_n8889, n_n7809, n_n8918, - n_n8515, n_n7933, n_n8075, n_n7338, n_n8104, n_n8171, n_n9059, n_n9023, - n_n7692, n_n9441, n_n6920, n_n8831, n_n8441, n_n9576, n_n9252, n_n9363, - ndn3_4, n_n9247, n_n7561, n_n8923, n_n7978, n_n8978, n_n9499, n_n8713, - n_n8944, n_n8239, n_n7652, n_n9042, n_n8530, n_n9271, n_n9318, n_n7706, - n_n7964, n_n8222, n_n8898, n_n7976, n_n7649, n_n7604, n_n7961, n_n7424, - n_n7476, n_n9259, n_n9309, n_n9161, n_n8436, n_n9121, n_n8061, n_n8004, - n_n9360, n_n9205, n_n8392, n_n9034, n_n8375, n_n8328, n_n9298, n_n7598, - n_n8506, pdn, n_n7737, n_n7420, n_n9291, n_n7946, n_n8584, n_n9308, - n_n9403, n_n7284, n_n9270, n_n7390, n_n9351, n_n6968, n_n8668, n_n9605, - n_n7013, n_n9626, n_n8200, n_n9028, n_n8803, n_n9570, n_n8366, n_n9050, - n_n8650, n_n8574, n_n7276, n_n9212, n_n8384, ndn3_35, n_n8449, ndn3_46, - n_n7554, n_n8743, n_n8277, n_n9359, n_n8425, n_n9104, n_n9221, n_n9448, - n_n9537, n_n8003, n_n7467, n_n8233, n_n7932, n_n8064, n_n9162, n_n7971, - n_n8055, n_n7711, n_n8256, n_n7925, n_n7762, n_n7668, n_n7914, n_n7873, - n_n7849, n_n9421, n_n7626, n_n7848, n_n8263, n_n9100, n_n9393, n_n9591, - n_n7588, n_n9123, n_n9159, n_n9128, n_n8045, n_n7728, n_n8929, n_n7739, - n_n9355, n_n9394, n_n8470, n_n8571, n_n8796, ndn3_36, n_n7990, n_n8781, - n_n8817, n_n9160, n_n9092, n_n8513, n_n8213, n_n8581, n_n9284, n_n7837, - n_n8224, n_n9203, n_n7655, n_n8946, n_n7052, n_n9615, n_n8473, n_n7741, - n_n9460, n_n7912, n_n7606, n_n9021, n_n7781, n_n7810, n_n7108, n_n7697, - n_n7642, n_n9595, n_n7694, n_n8221, n_n7600, n_n7935, n_n9230, n_n7701, - n_n7510, n_n7627, n_n8502, n_n8516, n_n7913, n_n9320, n_n7411, n_n9129, - n_n9053, n_n7069, n_n8617, n_n7242, n_n8230, n_n9294, n_n8249, n_n8972, - n_n7074, n_n7493, n_n8290, n_n8821, n_n7769, n_n7491, n_n9600, n_n9317, - n_n8047, n_n9629, n_n9126, n_n9508, n_n9155, n_n8528, ndn3_37, ndn3_42, - n_n9358, n_n8185, nen3_28, n_n8839, n_n7903, n_n9139, n_n9075, n_n9439, - n_n9353, n_n7665, n_n8798, n_n7146, n_n7890, n_n7176, n_n8477, n_n8514, - n_n8636, n_n7183, n_n8657, n_n9493, n_n7969, n_n9255, n_n8535, n_n8619, - n_n8909, n_n7744, n_n9119, n_n7827, n_n8916, n_n8729, n_n9011, n_n8779, - n_n6980, n_n7715, n_n9067, n_n9164, n_n7402, n_n8938, n_n9046, n_n8789, - n_n9390, n_n7768, n_n9136, n_n8670, n_n8644, n_n9178, n_n8188, n_n7083, - n_n9344, n_n7366, n_n8361, n_n9228, n_n9402, n_n8510, n_n8881, n_n9404, - n_n9424, n_n9031, nsr3_37, n_n8197, n_n8468, n_n7121, n_n7511, ndn3_44, - n_n9322, n_n7682, n_n9603, nlc1_2, n_n8408, n_n8577, n_n7079, n_n8828, - n_n9340, n_n8586, n_n7901, n_n8628, n_n8869, n_n7710, n_n8993, n_n9586, - n_n8852, n_n8583, n_n8011, n_n7717, n_n8326, n_n9163, n_n8344, n_n8296, - n_n8116, n_n8267, n_n7686, n_n9061, n_n9338, n_n7688, n_n9081, n_n6910, - n_n8727, n_n7674, n_n7330, n_n8966, n_n7843, n_n8847, n_n9376, n_n7553, - n_n9292, n_n7464, n_n8146, n_n8439, n_n9498, n_n8118, n_n9452, n_n9239, - n_n9237, n_n9488, ndn3_2, n_n9522, n_n9313, n_n7435, n_n8665, n_n9593, - n_n8303, n_n7022, n_n9173, n_n9261, n_n7150, n_n9455, n_n8371, nsr3_20, - n_n8271, n_n9542, n_n7444, ndn3_40, n_n7130, n_n9347, n_n8102, n_n9225, - n_n8462, n_n8088, n_n9026, n_n9289, n_n7661, n_n8108, n_n8921, n_n7859, - n_n7732, n_n7956, n_n9520, n_n7666, n_n7678, n_n7846, n_n8280, n_n8841, - n_n7336, n_n8226, n_n8151, n_n7644, n_n8770, n_n8423, n_n7763, n_n9525, - n_n8033, n_n7881, n_n7815, n_n9232, n_n7792, n_n9563, n_n8672, n_n7346, - n_n7949, n_n8756, n_n8641, n_n8192, n_n8058, n_n8561, n_n9306, n_n9165, - n_n8850, n_n9210, ndn2_2, n_n7342, n_n8051, n_n7136, n_n9348, n_n9006, - n_n7653, n_n7905, n_n9166, n_n7065, n_n9490, n_n7024, n_n7586, n_n8416, - n_n8937, n_n8141, n_n7853, n_n8121, n_n9604, n_n9496, n_n8195, n_n9516, - n_n9077, n_n9436, n_n9051, n_n7664, n_n8419, n_n7874, n_n9133, n_n9392, - n_n7770, ndn3_32, n_n7601, n_n8206, n_n7927, n_n9606, n_n7111, n_n9269, - ndn3_38, n_n7886, n_n9179, n_n9357, n_n9594, n_n7628, n_n8454, ndn3_20, - n_n9505, nen3_34, n_n9632, n_n7076, n_n9262, n_n9048, n_n9578, n_n8135, - ndn3_26, n_n7500, n_n6974, n_n8605, n_n9296, n_n7156, n_n7920, n_n8895, - n_n8991, n_n8139, n_n9275, n_n7203, n_n9590, n_n7344, n_n6976, n_n7629, - ndn3_14, n_n7862, n_n9013, n_n7288, n_n8078, n_n7334, n_n7704, n_n7788, - n_n8526, n_n9556, n_n9345, n_n8447, n_n7485, n_n8570, n_n7453, n_n7928, - n_n8646, n_n9405, n_n8948, n_n9131, n_n8216, n_n9177, n_n7844, n_n8811, - n_n9145, n_n8428, n_n8858, n_n8580; - wire n4845, n4846, n4847, n4848, n4849_1, n4850, n4851, n4852, n4853, - n4854_1, n4855, n4856, n4857, n4858, n4859_1, n4860, n4861, n4862, - n4863, n4864_1, n4865, n4866, n4867, n4868, n4869_1, n4870, n4871, - n4872, n4873, n4874_1, n4875, n4876, n4877, n4878, n4879_1, n4880, - n4881, n4882, n4883, n4884_1, n4885, n4886, n4887, n4888, n4889_1, - n4890, n4891, n4892, n4893, n4894_1, n4895, n4896, n4897, n4898, - n4899_1, n4900, n4901, n4902, n4903, n4904_1, n4905, n4906, n4907, - n4908, n4909_1, n4910, n4911, n4912, n4913, n4914_1, n4915, n4916, - n4917, n4918, n4919_1, n4920, n4921, n4922, n4923, n4924_1, n4925, - n4926, n4927, n4928, n4929_1, n4930, n4931, n4932, n4933, n4934_1, - n4935, n4936, n4937, n4938, n4939_1, n4940, n4941, n4942, n4943, - n4944_1, n4945, n4946, n4947, n4948, n4949_1, n4950, n4951, n4952, - n4953, n4954_1, n4955, n4956, n4957, n4958, n4959_1, n4960, n4961, - n4962, n4963, n4964_1, n4965, n4966, n4967, n4968, n4969_1, n4970, - n4971, n4972, n4973, n4974_1, n4975, n4976, n4977, n4978, n4979_1, - n4980, n4981, n4982, n4983, n4984_1, n4985, n4986, n4987, n4988, - n4989_1, n4990, n4991, n4992, n4993, n4994_1, n4995, n4996, n4997, - n4998, n4999_1, n5000, n5001, n5002, n5003, n5004_1, n5005, n5006, - n5007, n5008, n5009_1, n5010, n5011, n5012, n5013, n5014_1, n5015, - n5016, n5017, n5018, n5019_1, n5020, n5021, n5022, n5023, n5024_1, - n5025, n5026, n5027, n5028, n5029_1, n5030, n5031, n5032, n5033, - n5034_1, n5035, n5036, n5037, n5038, n5039_1, n5040, n5041, n5042, - n5043, n5044_1, n5045, n5046, n5047, n5048, n5049_1, n5050, n5051, - n5052, n5053, n5054_1, n5055, n5056, n5057, n5058, n5059_1, n5060, - n5061, n5062, n5063, n5064_1, n5065, n5066, n5067, n5068, n5069_1, - n5070, n5071, n5072, n5073, n5074_1, n5075, n5076, n5077, n5078, - n5079_1, n5080, n5081, n5082, n5083, n5084_1, n5085, n5086, n5087, - n5088, n5089_1, n5090, n5091, n5092, n5093, n5094_1, n5095, n5096, - n5097, n5098, n5099_1, n5100, n5101, n5102, n5103, n5104_1, n5105, - n5106, n5107, n5108, n5109_1, n5110, n5111, n5112, n5113, n5114_1, - n5115, n5116, n5117, n5118, n5119_1, n5120, n5121, n5122, n5123, - n5124_1, n5125, n5126, n5127, n5128, n5129_1, n5130, n5131, n5132, - n5133, n5134_1, n5135, n5136, n5137, n5138, n5139_1, n5140, n5141, - n5142, n5143, n5144_1, n5145, n5146, n5147, n5148, n5149_1, n5150, - n5151, n5152, n5153, n5154_1, n5155, n5156, n5157, n5158, n5159_1, - n5160, n5161, n5162, n5163, n5164_1, n5165, n5166, n5167, n5168, - n5169_1, n5170, n5171, n5172, n5173, n5174_1, n5175, n5176, n5177, - n5178, n5179_1, n5180, n5181, n5182, n5183, n5184_1, n5185, n5186, - n5187, n5188, n5189_1, n5190, n5191, n5192, n5193, n5194_1, n5195, - n5196, n5197, n5198, n5199_1, n5200, n5201, n5202, n5203, n5204_1, - n5205, n5206, n5207, n5208, n5209_1, n5210, n5211, n5212, n5213, - n5214_1, n5215, n5216, n5217, n5218, n5219_1, n5220, n5221, n5222, - n5223, n5224_1, n5225, n5226, n5227, n5228, n5229_1, n5230, n5231, - n5232, n5233, n5234_1, n5235, n5236, n5237, n5238, n5239_1, n5240, - n5241, n5242, n5243, n5244_1, n5245, n5246, n5247, n5248, n5249_1, - n5250, n5251, n5252, n5253, n5254_1, n5255, n5256, n5257, n5258, - n5259_1, n5260, n5261, n5262, n5263, n5264_1, n5265, n5266, n5267, - n5268, n5269_1, n5270, n5271, n5272, n5273, n5274_1, n5275, n5276, - n5277, n5278, n5279_1, n5280, n5281, n5282, n5283, n5284_1, n5285, - n5286, n5287, n5288, n5289_1, n5290, n5291, n5292, n5293, n5294_1, - n5295, n5296, n5297, n5298, n5299_1, n5300, n5301, n5302, n5303, - n5304_1, n5305, n5306, n5307, n5308, n5309_1, n5310, n5311, n5312, - n5313, n5314_1, n5315, n5316, n5317, n5318, n5319_1, n5320, n5321, - n5322, n5323, n5324_1, n5325, n5326, n5327, n5328, n5329_1, n5330, - n5331, n5332, n5333, n5334_1, n5335, n5336, n5337, n5338, n5339_1, - n5340, n5341, n5342, n5343, n5344_1, n5345, n5346, n5347, n5348, - n5349_1, n5350, n5351, n5352, n5353, n5354_1, n5355, n5356, n5357, - n5358, n5359_1, n5360, n5361, n5362, n5363, n5364_1, n5365, n5366, - n5367, n5368, n5369_1, n5370, n5371, n5372, n5373, n5374_1, n5375, - n5376, n5377, n5378, n5379_1, n5380, n5381, n5382, n5383, n5384_1, - n5385, n5386, n5387, n5388, n5389_1, n5390, n5391, n5392, n5393, - n5394_1, n5395, n5396, n5397, n5398, n5399_1, n5400, n5401, n5402, - n5403, n5404_1, n5405, n5406, n5407, n5408, n5409_1, n5410, n5411, - n5412, n5413, n5414_1, n5415, n5416, n5417, n5418, n5419_1, n5420, - n5421, n5422, n5423, n5424_1, n5425, n5426, n5427, n5428, n5429_1, - n5430, n5431, n5432, n5433, n5434_1, n5435, n5436, n5437, n5438, - n5439_1, n5440, n5441, n5442, n5443, n5444_1, n5445, n5446, n5447, - n5448, n5449_1, n5450, n5451, n5452, n5453, n5454_1, n5455, n5456, - n5457, n5458, n5459_1, n5460, n5461, n5462, n5463, n5464_1, n5465, - n5466, n5467, n5468, n5469_1, n5470, n5471, n5472, n5473, n5474_1, - n5475, n5476, n5477, n5478, n5479_1, n5480, n5481, n5482, n5483, - n5484_1, n5485, n5486, n5487, n5488, n5489_1, n5490, n5491, n5492, - n5493, n5494_1, n5495, n5496, n5497, n5498, n5499_1, n5500, n5501, - n5502, n5503, n5504_1, n5505, n5506, n5507, n5508, n5509_1, n5510, - n5511, n5512, n5513, n5514_1, n5515, n5516, n5517, n5518, n5519_1, - n5520, n5521, n5522, n5523, n5524_1, n5525, n5526, n5527, n5528, - n5529_1, n5530, n5531, n5532, n5533, n5534_1, n5535, n5536, n5537, - n5538, n5539_1, n5540, n5541, n5542, n5543, n5544_1, n5545, n5546, - n5547, n5548, n5549_1, n5550, n5551, n5552, n5553, n5554_1, n5555, - n5556, n5557, n5558, n5559_1, n5560, n5561, n5562, n5563, n5564_1, - n5565, n5566, n5567, n5568, n5569_1, n5570, n5571, n5572, n5573, - n5574_1, n5575, n5576, n5577, n5578, n5579_1, n5580, n5581, n5582, - n5583, n5584_1, n5585, n5586, n5587, n5588, n5589_1, n5590, n5591, - n5592, n5593, n5594_1, n5595, n5596, n5597, n5598, n5599_1, n5600, - n5601, n5602, n5603, n5604_1, n5605, n5606, n5607, n5608, n5609_1, - n5610, n5611, n5612, n5613, n5614_1, n5615, n5616, n5617, n5618, - n5619_1, n5620, n5621, n5622, n5623, n5624_1, n5625, n5626, n5627, - n5628, n5629_1, n5630, n5631, n5632, n5633, n5634_1, n5635, n5636, - n5637, n5638, n5639_1, n5640, n5641, n5642, n5643, n5644_1, n5645, - n5646, n5647, n5648, n5649_1, n5650, n5651, n5652, n5653, n5654_1, - n5655, n5656, n5657, n5658, n5659_1, n5660, n5661, n5662, n5663, - n5664_1, n5665, n5666, n5667, n5668, n5669_1, n5670, n5671, n5672, - n5673, n5674_1, n5675, n5676, n5677, n5678, n5679_1, n5680, n5681, - n5682, n5683, n5684_1, n5685, n5686, n5687, n5688, n5689_1, n5690, - n5691, n5692, n5693, n5694_1, n5695, n5696, n5697, n5698, n5699_1, - n5700, n5701, n5702, n5703, n5704_1, n5705, n5706, n5707, n5708, - n5709_1, n5710, n5711, n5712, n5713, n5714_1, n5715, n5716, n5717, - n5718, n5719_1, n5720, n5721, n5722, n5723, n5724_1, n5725, n5726, - n5727, n5728, n5729_1, n5730, n5731, n5732, n5733, n5734_1, n5735, - n5736, n5737, n5738, n5739_1, n5740, n5741, n5742, n5743, n5744_1, - n5745, n5746, n5747, n5748, n5749_1, n5750, n5751, n5752, n5753, - n5754_1, n5755, n5756, n5757, n5758, n5759_1, n5760, n5761, n5762, - n5763, n5764_1, n5765, n5766, n5767, n5768, n5769_1, n5770, n5771, - n5772, n5773, n5774_1, n5775, n5776, n5777, n5778, n5779_1, n5780, - n5781, n5782, n5783, n5784_1, n5785, n5786, n5787, n5788, n5789_1, - n5790, n5791, n5792, n5793, n5794_1, n5795, n5796, n5797, n5798, - n5799_1, n5800, n5801, n5802, n5803, n5804_1, n5805, n5806, n5807, - n5808, n5809_1, n5810, n5811, n5812, n5813, n5814_1, n5815, n5816, - n5817, n5818, n5819_1, n5820, n5821, n5822, n5823, n5824_1, n5825, - n5826, n5827, n5828, n5829_1, n5830, n5831, n5832, n5833, n5834_1, - n5835, n5836, n5837, n5838, n5839_1, n5840, n5841, n5842, n5843, - n5844_1, n5845, n5846, n5847, n5848, n5849_1, n5850, n5851, n5852, - n5853, n5854_1, n5855, n5856, n5857, n5858, n5859_1, n5860, n5861, - n5862, n5863, n5864_1, n5865, n5866, n5867, n5868, n5869_1, n5870, - n5871, n5872, n5873, n5874_1, n5875, n5876, n5877, n5878, n5879_1, - n5880, n5881, n5882, n5883, n5884_1, n5885, n5886, n5887, n5888, - n5889_1, n5890, n5891, n5892, n5893, n5894_1, n5895, n5896, n5897, - n5898, n5899_1, n5900, n5901, n5902, n5903, n5904_1, n5905, n5906, - n5907, n5908, n5909_1, n5910, n5911, n5912, n5913, n5914_1, n5915, - n5916, n5917, n5918, n5919_1, n5920, n5921, n5922, n5923, n5924_1, - n5925, n5926, n5927, n5928, n5929_1, n5930, n5931, n5932, n5933, - n5934_1, n5935, n5936, n5937, n5938, n5939_1, n5940, n5941, n5942, - n5943, n5944_1, n5945, n5946, n5947, n5948, n5949_1, n5950, n5951, - n5952, n5953, n5954_1, n5955, n5956, n5957, n5958, n5959_1, n5960, - n5961, n5962, n5963, n5964_1, n5965, n5966, n5967, n5968, n5969_1, - n5970, n5971, n5972, n5973, n5974_1, n5975, n5976, n5977, n5978, - n5979_1, n5980, n5981, n5982, n5983, n5984_1, n5985, n5986, n5987, - n5988, n5989_1, n5990, n5991, n5992, n5993, n5994_1, n5995, n5996, - n5997, n5998, n5999_1, n6000, n6001, n6002, n6003, n6004_1, n6005, - n6006, n6007, n6008, n6009_1, n6010, n6011, n6012, n6013, n6014_1, - n6015, n6016, n6017, n6018, n6019_1, n6020, n6021, n6022, n6023, - n6024_1, n6025, n6026, n6027, n6028, n6029_1, n6030, n6031, n6032, - n6033, n6034_1, n6035, n6036, n6037, n6038, n6039_1, n6040, n6041, - n6042, n6043, n6044_1, n6045, n6046, n6047, n6048, n6049_1, n6050, - n6051, n6052, n6053, n6054_1, n6055, n6056, n6057, n6058, n6059_1, - n6060, n6061, n6062, n6063, n6064_1, n6065, n6066, n6067, n6068, - n6069_1, n6070, n6071, n6072, n6073, n6074_1, n6075, n6076, n6077, - n6078, n6079_1, n6080, n6081, n6082, n6083, n6084_1, n6085, n6086, - n6087, n6088, n6089_1, n6090, n6091, n6092, n6093, n6094_1, n6095, - n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105, - n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115, - n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125, - n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135, - n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145, - n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155, - n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165, - n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175, - n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185, - n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195, - n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205, - n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215, - n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225, - n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235, - n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245, - n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255, - n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265, - n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275, - n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285, - n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295, - n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305, - n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315, - n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325, - n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335, - n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345, - n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355, - n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365, - n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375, - n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385, - n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395, - n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405, - n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415, - n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425, - n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435, - n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445, - n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455, - n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465, - n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474, n6475, - n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484, n6485, - n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494, n6495, - n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504, n6505, - n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514, n6515, - n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524, n6525, - n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534, n6535, - n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544, n6545, - n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554, n6555, - n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564, n6565, - n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574, n6575, - n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584, n6585, - n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595, - n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605, - n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615, - n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625, - n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635, - n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644, n6645, - n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654, n6655, - n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664, n6665, - n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674, n6675, - n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684, n6685, - n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695, - n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705, - n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714, n6715, - n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725, - n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735, - n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6745, - n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755, - n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765, - n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775, - n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785, - n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795, - n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805, - n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815, - n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825, - n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835, - n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845, - n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855, - n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865, - n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875, - n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885, - n6886, n6887, n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895, - n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905, - n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915, - n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925, - n6926, n6927, n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935, - n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945, - n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955, - n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965, - n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975, - n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985, - n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995, - n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005, - n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015, - n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025, - n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035, - n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045, - n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055, - n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065, - n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075, - n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085, - n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095, - n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105, - n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115, - n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125, - n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135, - n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145, - n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155, - n7156, n7157, n7158, n7159, n7160, n7161, n7162, n7163, n7164, n7165, - n7166, n7167, n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175, - n7176, n7177, n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185, - n7186, n7187, n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195, - n7196, n7197, n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205, - n7206, n7207, n7208, n7209, n7210, n7211, n7212, n491, n496, n501, - n506, n511, n516, n521, n526, n531, n536, n541, n546, n551, n556, n561, - n566, n571, n576, n581, n586, n591, n596, n601, n606, n611, n616, n621, - n626, n631, n636, n641, n646, n651, n656, n661, n666, n671, n676, n681, - n686, n691, n696, n701, n706, n711, n716, n721, n726, n731, n736, n741, - n746, n751, n756, n761, n766, n771, n776, n781, n786, n791, n796, n801, - n806, n811, n816, n821, n826, n831, n835, n840, n845, n850, n855, n860, - n865, n870, n875, n880, n885, n890, n895, n900, n905, n910, n915, n920, - n925, n930, n935, n940, n945, n950, n955, n960, n965, n970, n975, n980, - n985, n990, n995, n1000, n1005, n1010, n1015, n1020, n1025, n1030, - n1035, n1040, n1045, n1050, n1055, n1060, n1065, n1070, n1075, n1080, - n1085, n1090, n1095, n1100, n1105, n1110, n1115, n1120, n1125, n1130, - n1135, n1140, n1145, n1150, n1155, n1160, n1165, n1170, n1175, n1180, - n1185, n1190, n1195, n1200, n1205, n1210, n1215, n1220, n1225, n1230, - n1235, n1240, n1245, n1250, n1255, n1260, n1265, n1270, n1275, n1280, - n1285, n1290, n1295, n1300, n1305, n1310, n1315, n1320, n1325, n1330, - n1335, n1340, n1345, n1350, n1355, n1360, n1365, n1370, n1375, n1380, - n1385, n1390, n1395, n1400, n1405, n1410, n1415, n1420, n1425, n1430, - n1435, n1440, n1445, n1450, n1455, n1460, n1465, n1470, n1475, n1480, - n1485, n1490, n1495, n1500, n1505, n1510, n1515, n1520, n1525, n1530, - n1535, n1540, n1545, n1550, n1555, n1560, n1565, n1570, n1575, n1580, - n1585, n1590, n1595, n1600, n1605, n1610, n1615, n1620, n1625, n1630, - n1635, n1640, n1645, n1650, n1655, n1660, n1665, n1670, n1675, n1680, - n1685, n1690, n1695, n1700, n1705, n1710, n1715, n1720, n1725, n1730, - n1735, n1740, n1745, n1750, n1755, n1760, n1765, n1770, n1775, n1780, - n1785, n1790, n1795, n1800, n1805, n1810, n1815, n1820, n1825, n1830, - n1835, n1840, n1845, n1850, n1855, n1860, n1865, n1870, n1875, n1880, - n1885, n1890, n1895, n1900, n1905, n1910, n1915, n1920, n1925, n1930, - n1935, n1940, n1945, n1950, n1955, n1960, n1965, n1970, n1975, n1980, - n1985, n1990, n1995, n2000, n2005, n2010, n2015, n2020, n2025, n2030, - n2035, n2040, n2045, n2050, n2055, n2060, n2065, n2070, n2075, n2080, - n2085, n2090, n2095, n2100, n2105, n2110, n2115, n2120, n2125, n2130, - n2135, n2140, n2145, n2150, n2155, n2160, n2165, n2170, n2175, n2180, - n2185, n2190, n2195, n2200, n2205, n2210, n2215, n2220, n2225, n2230, - n2235, n2240, n2245, n2250, n2255, n2260, n2265, n2270, n2275, n2280, - n2285, n2290, n2295, n2300, n2305, n2310, n2315, n2320, n2325, n2330, - n2335, n2340, n2345, n2350, n2355, n2360, n2365, n2370, n2375, n2380, - n2385, n2390, n2395, n2400, n2405, n2410, n2415, n2420, n2425, n2430, - n2435, n2440, n2445, n2450, n2455, n2460, n2465, n2470, n2475, n2480, - n2485, n2490, n2495, n2500, n2505, n2510, n2515, n2520, n2525, n2530, - n2535, n2540, n2545, n2550, n2555, n2560, n2565, n2570, n2575, n2580, - n2585, n2590, n2595, n2600, n2605, n2610, n2615, n2620, n2625, n2630, - n2635, n2640, n2645, n2650, n2655, n2660, n2665, n2670, n2675, n2680, - n2685, n2690, n2695, n2700, n2705, n2710, n2715, n2720, n2725, n2730, - n2735, n2740, n2745, n2750, n2755, n2760, n2765, n2770, n2775, n2780, - n2785, n2790, n2795, n2800, n2805, n2810, n2815, n2820, n2825, n2830, - n2835, n2840, n2845, n2850, n2855, n2860, n2865, n2870, n2875, n2880, - n2885, n2890, n2895, n2900, n2905, n2910, n2915, n2920, n2925, n2930, - n2935, n2940, n2945, n2950, n2955, n2960, n2965, n2970, n2975, n2980, - n2985, n2990, n2995, n3000, n3005, n3010, n3015, n3020, n3025, n3030, - n3035, n3040, n3045, n3050, n3055, n3060, n3065, n3070, n3075, n3080, - n3085, n3090, n3095, n3100, n3105, n3110, n3115, n3120, n3125, n3130, - n3135, n3140, n3145, n3150, n3155, n3160, n3165, n3170, n3175, n3180, - n3185, n3190, n3195, n3200, n3205, n3210, n3215, n3220, n3225, n3230, - n3235, n3240, n3245, n3250, n3255, n3260, n3265, n3270, n3275, n3280, - n3285, n3290, n3295, n3300, n3305, n3310, n3315, n3320, n3325, n3330, - n3335, n3340, n3345, n3350, n3355, n3360, n3365, n3370, n3375, n3380, - n3385, n3390, n3395, n3400, n3405, n3410, n3415, n3420, n3425, n3430, - n3435, n3440, n3445, n3450, n3455, n3460, n3465, n3470, n3475, n3480, - n3485, n3490, n3495, n3500, n3505, n3510, n3515, n3520, n3525, n3530, - n3535, n3540, n3545, n3550, n3555, n3560, n3565, n3570, n3575, n3580, - n3585, n3590, n3595, n3600, n3605, n3610, n3615, n3620, n3625, n3630, - n3635, n3640, n3645, n3650, n3655, n3660, n3665, n3670, n3675, n3680, - n3685, n3690, n3695, n3700, n3705, n3710, n3715, n3720, n3725, n3730, - n3735, n3740, n3745, n3750, n3755, n3760, n3765, n3770, n3775, n3780, - n3785, n3790, n3795, n3800, n3805, n3810, n3815, n3820, n3825, n3830, - n3835, n3840, n3845, n3850, n3855, n3860, n3865, n3870, n3875, n3880, - n3885, n3890, n3895, n3900, n3905, n3910, n3915, n3920, n3925, n3930, - n3935, n3940, n3945, n3950, n3955, n3960, n3965, n3970, n3975, n3980, - n3985, n3990, n3995, n4000, n4005, n4009, n4014, n4019, n4024, n4029, - n4034, n4039, n4044, n4049, n4054, n4059, n4064, n4069, n4074, n4079, - n4084, n4089, n4094, n4099, n4104, n4109, n4114, n4119, n4124, n4129, - n4134, n4139, n4144, n4149, n4154, n4159, n4164, n4169, n4174, n4179, - n4184, n4189, n4194, n4199, n4204, n4209, n4214, n4219, n4224, n4229, - n4234, n4239, n4244, n4249, n4254, n4259, n4264, n4269, n4274, n4279, - n4284, n4289, n4294, n4299, n4304, n4309, n4314, n4319, n4324, n4329, - n4334, n4339, n4344, n4349, n4354, n4359, n4364, n4369, n4374, n4379, - n4384, n4389, n4394, n4399, n4404, n4409, n4414, n4419, n4424, n4429, - n4434, n4439, n4444, n4449, n4454, n4459, n4464, n4469, n4474, n4479, - n4484, n4489, n4494, n4499, n4504, n4509, n4514, n4519, n4524, n4529, - n4534, n4539, n4544, n4549, n4554, n4559, n4564, n4569, n4574, n4579, - n4584, n4589, n4594, n4599, n4604, n4609, n4614, n4619, n4624, n4629, - n4634, n4639, n4644, n4649, n4654, n4659, n4664, n4669, n4674, n4679, - n4684, n4689, n4694, n4699, n4704, n4709, n4714, n4719, n4724, n4729, - n4734, n4739, n4744, n4749, n4754, n4759, n4764, n4769, n4774, n4779, - n4784, n4789, n4794, n4799, n4804, n4809, n4814, n4819, n4824, n4829, - n4834, n4839, n4844, n4849, n4854, n4859, n4864, n4869, n4874, n4879, - n4884, n4889, n4894, n4899, n4904, n4909, n4914, n4919, n4924, n4929, - n4934, n4939, n4944, n4949, n4954, n4959, n4964, n4969, n4974, n4979, - n4984, n4989, n4994, n4999, n5004, n5009, n5014, n5019, n5024, n5029, - n5034, n5039, n5044, n5049, n5054, n5059, n5064, n5069, n5074, n5079, - n5084, n5089, n5094, n5099, n5104, n5109, n5114, n5119, n5124, n5129, - n5134, n5139, n5144, n5149, n5154, n5159, n5164, n5169, n5174, n5179, - n5184, n5189, n5194, n5199, n5204, n5209, n5214, n5219, n5224, n5229, - n5234, n5239, n5244, n5249, n5254, n5259, n5264, n5269, n5274, n5279, - n5284, n5289, n5294, n5299, n5304, n5309, n5314, n5319, n5324, n5329, - n5334, n5339, n5344, n5349, n5354, n5359, n5364, n5369, n5374, n5379, - n5384, n5389, n5394, n5399, n5404, n5409, n5414, n5419, n5424, n5429, - n5434, n5439, n5444, n5449, n5454, n5459, n5464, n5469, n5474, n5479, - n5484, n5489, n5494, n5499, n5504, n5509, n5514, n5519, n5524, n5529, - n5534, n5539, n5544, n5549, n5554, n5559, n5564, n5569, n5574, n5579, - n5584, n5589, n5594, n5599, n5604, n5609, n5614, n5619, n5624, n5629, - n5634, n5639, n5644, n5649, n5654, n5659, n5664, n5669, n5674, n5679, - n5684, n5689, n5694, n5699, n5704, n5709, n5714, n5719, n5724, n5729, - n5734, n5739, n5744, n5749, n5754, n5759, n5764, n5769, n5774, n5779, - n5784, n5789, n5794, n5799, n5804, n5809, n5814, n5819, n5824, n5829, - n5834, n5839, n5844, n5849, n5854, n5859, n5864, n5869, n5874, n5879, - n5884, n5889, n5894, n5899, n5904, n5909, n5914, n5919, n5924, n5929, - n5934, n5939, n5944, n5949, n5954, n5959, n5964, n5969, n5974, n5979, - n5984, n5989, n5994, n5999, n6004, n6009, n6014, n6019, n6024, n6029, - n6034, n6039, n6044, n6049, n6054, n6059, n6064, n6069, n6074, n6079, - n6084, n6089, n6094; - assign psv39_8_8_ = n_n7154 ? n_n9366 : tin_psv39_8_8_; - assign psv39_0_0_ = n_n6986 ? n_n9424 : tin_psv39_0_0_; - assign psv13_5_5_ = n_n7561 ? n_n9004 : tin_psv13_5_5_; - assign psv2_13_13_ = n_n8245 ? n_n9169 : tin_psv2_13_13_; - assign psv2_8_8_ = n_n8121 ? n_n8303 : tin_psv2_8_8_; - assign psv38_2_2_ = n_n7146 ? n_n6910 : tin_psv38_2_2_; - assign psv33_5_5_ = n_n7050 ? n_n9148 : tin_psv33_5_5_; - assign psv26_6_6_ = n_n7622 ? n_n6980 : tin_psv26_6_6_; - assign psv2_9_9_ = n_n8918 ? n_n7522 : tin_psv2_9_9_; - assign psv18_2_2_ = n_n7905 ? n_n8801 : tin_psv18_2_2_; - assign psv39_9_9_ = n_n7717 ? n_n7332 : tin_psv39_9_9_; - assign psv39_1_1_ = n_n8946 ? n_n8430 : tin_psv39_1_1_; - assign psv13_6_6_ = n_n8568 ? n_n7179 : tin_psv13_6_6_; - assign psv2_6_6_ = n_n7150 ? n_n7022 : tin_psv2_6_6_; - assign psv38_3_3_ = n_n7491 ? n_n7203 : tin_psv38_3_3_; - assign psv33_6_6_ = n_n8243 ? n_n7344 : tin_psv33_6_6_; - assign psv26_13_13_ = n_n7381 ? n_n7500 : tin_psv26_13_13_; - assign psv26_12_12_ = n_n7798 ? n_n8488 : tin_psv26_12_12_; - assign psv26_7_7_ = n_n7362 ? n_n8702 : tin_psv26_7_7_; - assign psv2_7_7_ = n_n8392 ? n_n8061 : tin_psv2_7_7_; - assign psv18_3_3_ = n_n7079 ? n_n7498 : tin_psv18_3_3_; - assign psv39_2_2_ = n_n7978 ? n_n7726 : tin_psv39_2_2_; - assign psv33_12_12_ = n_n7493 ? n_n8369 : tin_psv33_12_12_; - assign psv33_11_11_ = n_n8665 ? n_n7923 : tin_psv33_11_11_; - assign psv33_10_10_ = n_n9123 ? n_n9483 : tin_psv33_10_10_; - assign psv13_7_7_ = n_n9228 ? n_n7546 : tin_psv13_7_7_; - assign psv2_10_10_ = n_n7244 ? n_n8681 : tin_psv2_10_10_; - assign psv38_4_4_ = n_n7052 ? n_n7674 : tin_psv38_4_4_; - assign psv39_10_10_ = n_n7330 ? n_n8644 : tin_psv39_10_10_; - assign psv33_7_7_ = n_n7140 ? n_n7843 : tin_psv33_7_7_; - assign psv26_15_15_ = n_n8389 ? n_n9026 : tin_psv26_15_15_; - assign psv26_14_14_ = n_n9200 ? n_n7392 : tin_psv26_14_14_; - assign psv26_8_8_ = n_n6937 ? n_n7581 : tin_psv26_8_8_; - assign psv26_0_0_ = n_n7246 ? n_n7017 : tin_psv26_0_0_; - assign psv13_12_12_ = n_n8055 ? n_n8895 : tin_psv13_12_12_; - assign psv13_11_11_ = n_n7336 ? n_n9548 : tin_psv13_11_11_; - assign psv18_4_4_ = n_n9006 ? n_n9432 : tin_psv18_4_4_; - assign psv39_3_3_ = n_n7507 ? n_n7108 : tin_psv39_3_3_; - assign psv13_8_8_ = n_n7261 ? n_n7271 : tin_psv13_8_8_; - assign psv13_0_0_ = n_n7176 ? n_n7775 : tin_psv13_0_0_; - assign psv38_5_5_ = n_n8655 ? n_n7256 : tin_psv38_5_5_; - assign psv33_8_8_ = n_n9306 ? n_n7288 : tin_psv33_8_8_; - assign psv33_0_0_ = n_n8672 ? n_n8486 : tin_psv33_0_0_; - assign psv26_9_9_ = n_n7310 ? n_n7360 : tin_psv26_9_9_; - assign psv26_1_1_ = n_n7699 ? n_n7231 : tin_psv26_1_1_; - assign psv13_10_10_ = n_n6956 ? n_n7976 : tin_psv13_10_10_; - assign psv18_5_5_ = n_n7903 ? n_n7715 : tin_psv18_5_5_; - assign psv39_4_4_ = n_n7117 ? n_n7121 : tin_psv39_4_4_; - assign psv13_9_9_ = n_n7944 ? n_n9376 : tin_psv13_9_9_; - assign psv13_1_1_ = n_n7013 ? n_n8589 : tin_psv13_1_1_; - assign psv2_15_15_ = n_n6948 ? n_n8102 : tin_psv2_15_15_; - assign psv2_11_11_ = n_n6952 ? n_n6963 : tin_psv2_11_11_; - assign psv2_0_0_ = n_n7024 ? n_n8371 : tin_psv2_0_0_; - assign psv38_14_14_ = n_n8454 ? n_n7174 : tin_psv38_14_14_; - assign psv38_12_12_ = n_n8605 ? n_n7402 : tin_psv38_12_12_; - assign psv38_10_10_ = n_n7181 ? n_n7284 : tin_psv38_10_10_; - assign psv38_6_6_ = n_n7556 ? n_n7514 : tin_psv38_6_6_; - assign psv18_15_15_ = n_n7019 ? n_n7074 : tin_psv18_15_15_; - assign psv18_13_13_ = n_n7415 ? n_n7148 : tin_psv18_13_13_; - assign psv18_11_11_ = n_n8195 ? n_n8439 : tin_psv18_11_11_; - assign psv33_9_9_ = n_n8725 ? n_n9278 : tin_psv33_9_9_; - assign psv33_1_1_ = n_n7635 ? n_n8091 : tin_psv33_1_1_; - assign psv26_2_2_ = n_n7276 ? n_n7777 : tin_psv26_2_2_; - assign psv2_1_1_ = n_n7467 ? n_n7678 : tin_psv2_1_1_; - assign psv38_15_15_ = n_n8216 ? n_n8340 : tin_psv38_15_15_; - assign psv38_11_11_ = n_n7033 ? n_n7857 : tin_psv38_11_11_; - assign psv18_12_12_ = n_n8817 ? n_n9465 : tin_psv18_12_12_; - assign psv18_6_6_ = n_n8230 ? n_n7156 : tin_psv18_6_6_; - assign psv39_5_5_ = n_n8633 ? n_n8777 : tin_psv39_5_5_; - assign psv13_2_2_ = n_n8251 ? n_n7130 : tin_psv13_2_2_; - assign psv38_7_7_ = n_n8713 ? n_n8592 : tin_psv38_7_7_; - assign psv39_12_12_ = n_n9476 ? n_n8100 : tin_psv39_12_12_; - assign psv39_11_11_ = n_n7315 ? n_n7390 : tin_psv39_11_11_; - assign psv33_2_2_ = n_n7209 ? n_n7111 : tin_psv33_2_2_; - assign psv26_3_3_ = n_n7338 ? n_n8384 : tin_psv26_3_3_; - assign psv13_14_14_ = n_n7959 ? n_n7252 : tin_psv13_14_14_; - assign psv13_13_13_ = n_n8704 ? n_n6991 : tin_psv13_13_13_; - assign psv18_10_10_ = n_n8974 ? n_n8146 : tin_psv18_10_10_; - assign psv18_7_7_ = n_n7659 ? n_n8049 : tin_psv18_7_7_; - assign psv39_6_6_ = n_n8047 ? n_n8073 : tin_psv39_6_6_; - assign psv33_15_15_ = n_n7026 ? n_n8263 : tin_psv33_15_15_; - assign psv33_14_14_ = n_n6988 ? n_n9429 : tin_psv33_14_14_; - assign psv33_13_13_ = n_n8290 ? n_n7069 : tin_psv33_13_13_; - assign psv13_3_3_ = n_n7586 ? n_n8850 : tin_psv13_3_3_; - assign psv2_14_14_ = n_n8683 ? n_n7102 : tin_psv2_14_14_; - assign psv2_12_12_ = n_n7286 ? n_n8132 : tin_psv2_12_12_; - assign psv2_4_4_ = n_n7291 ? n_n8045 : tin_psv2_4_4_; - assign psv38_8_8_ = n_n6984 ? n_n9421 : tin_psv38_8_8_; - assign psv38_0_0_ = n_n8921 ? n_n8916 : tin_psv38_0_0_; - assign psv39_14_14_ = n_n8441 ? n_n9371 : tin_psv39_14_14_; - assign psv39_13_13_ = n_n8831 ? n_n7366 : tin_psv39_13_13_; - assign psv33_3_3_ = n_n7409 ? n_n7420 : tin_psv33_3_3_; - assign psv26_11_11_ = n_n7308 ? n_n8185 : tin_psv26_11_11_; - assign psv26_10_10_ = n_n9580 ? n_n8781 : tin_psv26_10_10_; - assign psv26_4_4_ = n_n8112 ? n_n8175 : tin_psv26_4_4_; - assign psv13_15_15_ = n_n8406 ? n_n9145 : tin_psv13_15_15_; - assign psv2_5_5_ = n_n9446 ? n_n7395 : tin_psv2_5_5_; - assign psv18_8_8_ = n_n7242 ? n_n8678 : tin_psv18_8_8_; - assign psv18_0_0_ = n_n7065 ? n_n7190 : tin_psv18_0_0_; - assign psv39_7_7_ = n_n7183 ? n_n7160 : tin_psv39_7_7_; - assign psv13_4_4_ = n_n9085 ? n_n9096 : tin_psv13_4_4_; - assign psv2_2_2_ = n_n8510 ? n_n7054 : tin_psv2_2_2_; - assign psv38_9_9_ = n_n8944 ? n_n8428 : tin_psv38_9_9_; - assign psv38_1_1_ = n_n9373 ? n_n7964 : tin_psv38_1_1_; - assign psv39_15_15_ = n_n7411 ? n_n8361 : tin_psv39_15_15_; - assign psv33_4_4_ = n_n7003 ? n_n7462 : tin_psv33_4_4_; - assign psv26_5_5_ = n_n8423 ? n_n7076 : tin_psv26_5_5_; - assign psv2_3_3_ = n_n6912 ? n_n8750 : tin_psv2_3_3_; - assign psv38_13_13_ = n_n9531 ? n_n6920 : tin_psv38_13_13_; - assign psv18_14_14_ = n_n8762 ? n_n7435 : tin_psv18_14_14_; - assign psv18_9_9_ = n_n6950 ? n_n6961 : tin_psv18_9_9_; - assign psv18_1_1_ = n_n7387 ? n_n9535 : tin_psv18_1_1_; - assign n491 = ~n4956 & ~preset & n_n9280; - assign n496 = n6728 | (n_n9434 & n4845 & n4967); - assign n501 = n6727 | (n_n9537 & n4845 & n4967); - assign n506 = n6725 | n6726; - assign n511 = ~n4956 & ~preset & n_n8270; - assign n516 = ~n4956 & ~preset & n_n8196; - assign n521 = ~n4956 & ~preset & n_n9150; - assign n526 = n6479 | n6480; - assign n531 = n6356 | (n1270 & n4848); - assign n536 = n6354 | n6355; - assign n541 = n6320 | n6321; - assign n546 = n6319 | (ndn3_11 & ~ndn3_12 & n4850); - assign n551 = ~preset & (n4851 ? n4930 : n_n7341); - assign n556 = ~preset & (n4852 ? n4868 : n_n9180); - assign n561 = n6317 | n6318; - assign n566 = n6316 | (nen3_39 & ~ndn3_39 & n4855); - assign n571 = n6314 | n6315; - assign n576 = n6312 | n6313; - assign n581 = n6310 | n6311; - assign n586 = n6197 | (n4858 & n7122) | (~n4858 & n7121); - assign n591 = n6196 | (n_n8354 & n4845 & n4967); - assign n596 = ~preset & (n4859_1 ? n4903 : n_n7552); - assign n601 = ~preset & ~nsr3_23; - assign n606 = n6194 | n6195; - assign n611 = n6192 | n6193; - assign n616 = n6190 | n6191; - assign n621 = ~preset & (n_n6950 | (ndn3_42 & ~ndn3_44)); - assign n626 = ~n4862 & (n_n8930 | (n4967 & n7089)); - assign n631 = ~preset & (n_n7244 | (~ndn3_42 & ndn3_40)); - assign n636 = n6189 | (n_n9512 & n4864_1 & n4967); - assign n641 = ~preset & (n4865 ? n4868 : n_n8883); - assign n646 = n6187 | n6188; - assign n651 = ~preset & (n_n9580 | (nen3_22 & ~ndn3_22)); - assign n656 = n6186 | (n_n9353 & n4867 & n4967); - assign n661 = n6185 | (n4863 & n4868); - assign n666 = n6184 | (n4853 & (n4969_1 ^ n4970)); - assign n671 = n6182 | n6183; - assign n676 = ~preset & (n4869_1 ? n4903 : n_n7373); - assign n681 = ~preset & (n_n9085 | (~ngfdn_3 & ndn3_46)); - assign n686 = n6178 | n6179 | n6180 | n6181; - assign n691 = n6177 | (~ndn3_29 & ndn3_28 & n4873); - assign n696 = n6145 | n6146; - assign n701 = ~preset & (n4875 ? n4930 : n_n7654); - assign n706 = ~preset & (n4876 ? n4887 : n_n8410); - assign n711 = n6082 | (ndn3_17 & ~ndn3_18 & n4878); - assign n716 = n6081 | (~ndn3_7 & ndn3_4 & n4873); - assign n721 = n6079_1 | n6080; - assign n726 = n6078 | (n_n9512 & n4845 & n4967); - assign n731 = n6077 | (~ndn3_19 & nen3_19 & n4855); - assign n736 = ~preset & (n4865 ? n4848 : n_n8202); - assign n741 = ~preset & (n4880 ? n4930 : n_n7670); - assign n746 = n6075 | n6076; - assign n751 = n6073 | n6074_1; - assign n756 = n6071 | n6072; - assign n761 = n6069_1 | n6070; - assign n766 = n6068 | (n_n8449 & n4883 & n4967); - assign n771 = n6067 | (n_n8419 & n4883 & n4967); - assign n776 = n6065 | n6066; - assign n781 = ~preset & (n4849_1 ? n4903 : n_n9141); - assign n786 = n6063 | n6064_1; - assign n791 = n6061 | n6062; - assign n796 = n6059_1 | n6060; - assign n801 = n6058 | (ndn3_11 & ~ndn3_12 & n4873); - assign n806 = n6056 | n6057; - assign n811 = n6054_1 | n6055; - assign n816 = n6052 | n6053; - assign n821 = ~preset & (n4854_1 ? n4903 : n_n7376); - assign n826 = n6051 | (ndn3_9 & ~ndn3_11 & n4878); - assign n831 = (n4005 & n4884_1) | (~preset & pover_0_0_ & ~n4884_1); - assign n835 = ~preset & (n4877 ? n4887 : n_n8599); - assign n840 = n6050 | (ndn3_11 & ~ndn3_12 & n4855); - assign n845 = ~n4956 & ~preset & n_n9442; - assign n850 = ~preset & (n4860 ? n4868 : n_n9485); - assign n855 = n6048 | n6049_1; - assign n860 = n6047 | (n_n9284 & n4864_1 & n4967); - assign n865 = n6046 | (ndn3_19 & ~ndn3_21 & n4873); - assign n870 = ~preset & ~ngfdn_3 & (ndn3_9 | ndn3_7); - assign n875 = ~n4956 & ~preset & n_n8613; - assign n880 = n6045 | (n_n8707 & n4867 & n4967); - assign n885 = n6044_1 | (n_n9512 & n4886 & n4967); - assign n890 = n6042 | n6043; - assign n895 = n6041 | (n4853 & n4887); - assign n900 = ~preset & (n_n8655 | (~ndn3_46 & ndn3_44)); - assign n905 = n6040 | (~ndn3_29 & ndn3_28 & n4888); - assign n910 = ~n4956 & ~preset & n_n7583; - assign n915 = n7174 | (n_n9248 & (~n_n9247 | ~n4902)); - assign n920 = n6038 | n6039_1; - assign n925 = n6037 | (~ndn3_7 & ndn3_4 & n4888); - assign n930 = n6035 | n6036; - assign n935 = ~preset & (n4889_1 ? n4903 : n_n7738); - assign n940 = ~n4956 & ~preset & n_n8573; - assign n945 = ~preset & (n4880 ? n4868 : n_n9473); - assign n950 = n6034_1 | (~ndn3_25 & ndn3_22 & n4873); - assign n955 = n6033 | (n_n8557 & n4890 & n4967); - assign n960 = ~n4956 & ~preset & n_n9554; - assign n965 = ~n4956 & ~preset & n_n8508; - assign n970 = n6031 | n6032; - assign n975 = n6029_1 | n6030; - assign n980 = n6027 | n6028; - assign n985 = n6025 | n6026; - assign n990 = ~preset & (n_n7409 | (ngfdn_3 & ~ndn3_50)); - assign n995 = ~n4956 & ~preset & n_n9437; - assign n1000 = n6023 | n6024_1; - assign n1005 = ~n4956 & ~preset & n_n8647; - assign n1010 = n6021 | n6022; - assign n1015 = n6019_1 | n6020; - assign n1020 = ~preset & ~nsr3_13; - assign n1025 = ~preset & ~ngfdn_3 & (ndn3_17 | ndn3_16); - assign n1030 = ~preset & ~ngfdn_3 & (ndn3_25 | ndn3_22); - assign n1035 = ~preset & ~ngfdn_3 & (ndn3_29 | ndn3_28); - assign n1040 = ~n4956 & ~preset & n_n9539; - assign n1045 = n6018 | (n_n8821 & n4883 & n4967); - assign n1050 = n6016 | n6017; - assign n1055 = ~preset & ~ngfdn_3 & (nen3_22 | ~nsr3_23); - assign n1060 = ~n4956 & ~preset & n_n9438; - assign n1065 = n6014_1 | n6015; - assign n1070 = n6013 | (n_n9416 & n4891 & n4967); - assign n1075 = n6011 | n6012; - assign n1080 = n6009_1 | n6010; - assign n1085 = n6008 | (n_n9353 & n4886 & n4967); - assign n1090 = ~preset & (n_n7798 | (nen3_22 & ~ndn3_22)); - assign n1095 = n6004_1 | n6005 | n6006 | n6007; - assign n1100 = ~preset & (n4859_1 ? n4904_1 : n_n7910); - assign n1105 = ~preset & (n4881 ? n4903 : n_n9528); - assign n1110 = n6002 | n6003; - assign n1115 = ~preset & (n_n8251 | (~ngfdn_3 & ndn3_46)); - assign n1120 = n6000 | n6001; - assign n1125 = n5998 | n5999_1; - assign n1130 = ~n4956 & ~preset & n_n9290; - assign n1135 = n5996 | n5997; - assign n1140 = ~preset & (n_n7556 | (~ndn3_46 & ndn3_44)); - assign n1145 = n5995 | (n_n8449 & n4886 & n4967); - assign n1150 = n5993 | n5994_1; - assign n1155 = n5992 | (ndn3_19 & ~ndn3_21 & n4855); - assign n1160 = ~n4956 & ~preset & n_n9361; - assign n1165 = ~preset & (n4885 ? n4848 : n_n9304); - assign n1170 = n5991 | (n_n8652 & n4896 & n4967); - assign n1175 = ~preset & (n4877 ? n4848 : n_n7712); - assign n1180 = n5990 | (n_n8707 & n4896 & n4967); - assign n1185 = n5989_1 | (n_n8549 & n4883 & n4967); - assign n1190 = n5988 | (~nsr3_13 & ~ndn3_15 & n4855); - assign n1195 = n5986 | n5987; - assign n1200 = ~preset & (n4849_1 ? n4930 : n_n9015); - assign n1205 = n5985 | (n_n8354 & n4891 & n4967); - assign n1210 = ~preset & (n4880 ? n4887 : n_n9518); - assign n1215 = n5983 | n5984_1; - assign n1220 = n5982 | (n_n9448 & n4883 & n4967); - assign n1225 = n5980 | n5981; - assign n1230 = n5978 | n5979_1; - assign n1235 = n5976 | n5977; - assign n1240 = ~preset & (n4849_1 ? n4887 : n_n7951); - assign n1245 = n5974_1 | n5973 | (n_n8913 & n4898); - assign n1250 = ~preset & (n4877 ? n4903 : n_n8035); - assign n1255 = n5972 | n5971 | (n_n8631 & n4898); - assign n1260 = ~preset & (n_n8243 | (ngfdn_3 & ~ndn3_50)); - assign n1265 = n5969_1 | n5970; - assign n1270 = ndn3_46 & ~preset & ~ngfdn_3; - assign n1275 = n5968 | (ndn3_9 & ~ndn3_11 & n4855); - assign n1280 = ~preset & (n4859_1 ? n4868 : n_n9175); - assign n1285 = n5966 | n5967; - assign n1290 = n5965 | (n_n9284 & n4891 & n4967); - assign n1295 = n5963 | n5964_1; - assign n1300 = ~n4956 & ~preset & n_n9410; - assign n1305 = n5962 | (n4861 & n4887); - assign n1310 = n5961 | (n_n8707 & n4886 & n4967); - assign n1315 = n5960 | (n_n9512 & n4867 & n4967); - assign n1320 = n5958 | n5959_1; - assign n1325 = n5957 | (n4863 & n4887); - assign n1330 = n5955 | n5956; - assign n1335 = n5954_1 | (~nsr3_13 & ~ndn3_15 & n4888); - assign n1340 = n5953 | (nen3_16 & ~ndn3_16 & n4850); - assign n1345 = n5952 | preset | pdn; - assign n1350 = n5951 | (n_n9353 & n4845 & n4967); - assign n1355 = ~n4956 & ~preset & n_n8531; - assign n1360 = n5950 | (n_n9638 & n4845 & n4967); - assign n1365 = n5949_1 | (n1270 & (n4985 ^ n4986)); - assign n1370 = n5948 | (nen3_39 & ~ndn3_39 & n4878); - assign n1375 = ~preset & (n_n8112 | (nen3_22 & ~ndn3_22)); - assign n1380 = n5946 | n5947; - assign n1385 = ~preset & (n4889_1 ? n4887 : n_n9618); - assign n1390 = n5944_1 | n5945; - assign n1395 = ~n4956 & ~preset & n_n9242; - assign n1400 = n5943 | (n4848 & n4853); - assign n1405 = ~preset & (n4882 ? n4868 : n_n8884); - assign n1410 = n5941 | n5942; - assign n1415 = n5940 | (n_n8549 & n4845 & n4967); - assign n1420 = n5939_1 | (n4853 & (n4976 ^ n4977)); - assign n1425 = ~preset & (n4876 ? n4904_1 : n_n7909); - assign n1430 = n5938 | (n4861 & (n4976 ^ n4977)); - assign n1435 = n5937 | (~ndn3_4 & ndn3_2 & n4850); - assign n1440 = ~preset & (n4860 ? n4930 : n_n8862); - assign n1445 = ~n4956 & ~preset & n_n8037; - assign n1450 = ~preset & ~ngfdn_3 & (ndn3_17 | ndn3_18); - assign n1455 = ~preset & ~ngfdn_3 & (nen3_22 | ndn3_22); - assign n1460 = ~preset & (n_n8974 | (ndn3_42 & ~ndn3_44)); - assign n1465 = ~preset & (n_n7286 | (~ndn3_42 & ndn3_40)); - assign n1470 = n5935 | n5936; - assign n1475 = ~preset & n4902; - assign n1480 = n5933 | n5934_1; - assign n1485 = n5931 | n5932; - assign n1490 = ~preset & ~ngfdn_3 & (nen3_39 | ~nsr3_38); - assign n1495 = n5929_1 | n5930; - assign n1500 = ~n4956 & ~preset & n_n9557; - assign n1505 = n5928 | (n_n8354 & n4896 & n4967); - assign n1510 = n5926 | n5927; - assign n1515 = n5924_1 | n5925; - assign n1520 = n5923 | (n_n9537 & n4886 & n4967); - assign n1525 = ~preset & (n_n8568 | (~ngfdn_3 & ndn3_46)); - assign n1530 = n5921 | n5922; - assign n1535 = ~preset & (n4889_1 ? n4904_1 : n_n7931); - assign n1540 = ~preset & (n4879_1 ? n4903 : n_n7742); - assign n1545 = n5920 | (ndn3_19 & ~ndn3_21 & n4878); - assign n1550 = n5919_1 | (n_n8549 & n4886 & n4967); - assign n1555 = ~preset & (n4874_1 ? n4904_1 : n_n9568); - assign n1560 = ~preset & (n_n9200 | (nen3_22 & ~ndn3_22)); - assign n1565 = n5917 | n5918; - assign n1570 = n5915 | n5916; - assign n1575 = n5914_1 | (nen3_16 & ~ndn3_16 & n4878); - assign n1580 = n5912 | n5913; - assign n1585 = n5910 | n5911; - assign n1590 = ~preset & (n4880 ? n4903 : n_n8499); - assign n1595 = n5908 | n5909_1; - assign n1600 = n5906 | n5907; - assign n1605 = n5905 | (ndn3_29 & ~ndn3_32 & n4873); - assign n1610 = n5903 | n5904_1; - assign n1615 = n5901 | n5902; - assign n1620 = ~preset & (n4852 ? n4848 : n_n7713); - assign n1625 = ~preset & (n4852 ? n4930 : n_n9566); - assign n1630 = n5899_1 | n5900; - assign n1635 = n5897 | n5898; - assign n1640 = n5896 | (~ndn3_7 & ndn3_4 & n4878); - assign n1645 = ~n4956 & ~preset & n_n9560; - assign n1650 = n5894_1 | n5895; - assign n1655 = n5892 | n5893; - assign n1660 = ~preset & (n4851 ? n4868 : n_n8882); - assign n1665 = n5890 | n5891; - assign n1670 = n5888 | n5889_1; - assign n1675 = n5887 | (ndn3_25 & ~ndn3_26 & n4888); - assign n1680 = n5885 | n5886; - assign n1685 = n5883 | n5884_1; - assign n1690 = n5882 | (n_n9537 & n4883 & n4967); - assign n1695 = ~n4956 & ~preset & n_n8875; - assign n1700 = n5880 | n5881; - assign n1705 = n5878 | n5879_1; - assign n1710 = n5877 | (n4846 & n4887); - assign n1715 = n5876 | (n4863 & n4903); - assign n1720 = n5875 | (n4853 & (n4971 ^ n4972)); - assign n1725 = n5874_1 | (n_n9416 & n4867 & n4967); - assign n1730 = n5873 | (n_n8821 & n4886 & n4967); - assign n1735 = n5871 | n5872; - assign n1740 = ~n4956 & ~preset & n_n7702; - assign n1745 = n7177 | (nsr3_23 & ~ndn3_19); - assign n1750 = ~n4956 & ~preset & n_n8199; - assign n1755 = ~n4956 & ~preset & n_n7983; - assign n1760 = n5870 | (n1270 & n4904_1); - assign n1765 = n5868 | n5869_1; - assign n1770 = n5867 | (n_n9434 & n4896 & n4967); - assign n1775 = ~n4956 & ~preset & n_n8348; - assign n1780 = n5865 | n5866; - assign n1785 = n5864_1 | (n_n8549 & n4890 & n4967); - assign n1790 = n5862 | n5863; - assign n1795 = n5861 | (n_n9638 & n4896 & n4967); - assign n1800 = n5860 | (n4848 & n4863); - assign n1805 = n5858 | n5859_1; - assign n1810 = n5856 | n5857; - assign n1815 = n5854_1 | n5855; - assign n1820 = n5853 | (n4863 & (n4976 ^ n4977)); - assign n1825 = n5852 | (n_n8419 & n4890 & n4967); - assign n1830 = n5851 | (n4846 & (n4976 ^ n4977)); - assign n1835 = n5850 | (n_n8354 & n4890 & n4967); - assign n1840 = n5849_1 | (n_n8652 & n4883 & n4967); - assign n1845 = n5848 | (ndn3_17 & ~ndn3_18 & n4888); - assign n1850 = n5847 | (n_n8707 & n4883 & n4967); - assign n1855 = n5845 | n5846; - assign n1860 = ~preset & ~nsr3_30; - assign n1865 = n5843 | n5844_1; - assign n1870 = ~preset & (n4859_1 ? n4887 : n_n7693); - assign n1875 = ~preset & ~ngfdn_3 & (nen3_16 | ~nsr3_14); - assign n1880 = n5841 | n5842; - assign n1885 = n5840 | (~ndn3_29 & ndn3_28 & n4878); - assign n1890 = n5839_1 | (n_n9512 & n4891 & n4967); - assign n1895 = n5837 | n5838; - assign n1900 = n5836 | (n_n8821 & n4891 & n4967); - assign n1905 = ~preset & (n4880 ? n4848 : n_n9110); - assign n1910 = n5834_1 | n5835; - assign n1915 = n5833 | (n4853 & n4868); - assign n1920 = n5832 | (n4863 & (n4969_1 ^ n4970)); - assign n1925 = n5830 | n5831; - assign n1930 = n5828 | n5829_1; - assign n1935 = n5827 | (~ndn3_27 & ndn3_26 & n4855); - assign n1940 = ~preset & (n_n8406 | (~ngfdn_3 & ndn3_46)); - assign n1945 = n5826 | (~ndn3_19 & nen3_19 & n4878); - assign n1950 = n5825 | (n_n8549 & n4867 & n4967); - assign n1955 = ~preset & (n4869_1 ? n4887 : n_n7474); - assign n1960 = n5824_1 | (n1270 & (n4954_1 ^ n4955)); - assign n1965 = ~preset & (n_n6984 | (~ndn3_46 & ndn3_44)); - assign n1970 = n5823 | (n4848 & n4866); - assign n1975 = n5821 | n5822; - assign n1980 = ~n4956 & ~preset & n_n9559; - assign n1985 = ~preset & (n_n7362 | (nen3_22 & ~ndn3_22)); - assign n1990 = n5819_1 | n5820; - assign n1995 = ~n4956 & ~preset & n_n9550; - assign n2000 = ~preset & (n4889_1 ? n4868 : n_n9492); - assign n2005 = n5817 | n5818; - assign n2010 = ~preset & (n4879_1 ? n4848 : n_n7764); - assign n2015 = n5815 | n5816; - assign n2020 = n5813 | n5814_1; - assign n2025 = n5811 | n5812; - assign n2030 = ~n4956 & ~preset & n_n8173; - assign n2035 = n5809_1 | n5810; - assign n2040 = n5807 | n5808; - assign n2045 = ~preset & (n4882 ? n4887 : n_n8753); - assign n2050 = ~preset & (n4852 ? n4904_1 : n_n8772); - assign n2055 = n5805 | n5806; - assign n2060 = ~n4956 & ~preset & n_n9362; - assign n2065 = ndn1_4 & ~preset & ~pdn; - assign n2070 = ~n4956 & ~preset & n_n9561; - assign n2075 = n5803 | n5804_1; - assign n2080 = ~preset & (n4849_1 ? n4848 : n_n8203); - assign n2085 = n5801 | n5802; - assign n2090 = n5799_1 | n5800; - assign n2095 = n5797 | n5798; - assign n2100 = ~n4956 & ~preset & n_n9331; - assign n2105 = n5796 | (~ndn3_19 & nen3_19 & n4873); - assign n2110 = ~preset & ~ngfdn_3 & (ndn3_7 | ndn3_4); - assign n2115 = n5795 | (n4853 & n4903); - assign n2120 = n5794_1 | (n4863 & (n4971 ^ n4972)); - assign n2125 = n5793 | (n_n9416 & n4886 & n4967); - assign n2130 = n5792 | (n_n8821 & n4867 & n4967); - assign n2135 = ~preset & (n4881 ? n4868 : n_n9497); - assign n2140 = ~preset & (n_n7291 | (~ndn3_42 & ndn3_40)); - assign n2145 = n7178 | (nsr3_13 & ~ndn3_12); - assign n2150 = n7179 | (nsr3_38 & ~nen3_36); - assign n2155 = ~n4956 & ~preset & n_n8240; - assign n2160 = ~n4956 & ~preset & n_n7703; - assign n2165 = n5791 | (n1270 & n4887); - assign n2170 = ~n4956 & ~preset & n_n8237; - assign n2175 = ~n4956 & ~preset & n_n8935; - assign n2180 = ~n4956 & ~preset & n_n9244; - assign n2185 = ~n4956 & ~preset & n_n8648; - assign n2190 = ~n4956 & ~preset & n_n8235; - assign n2195 = ~preset & (n4854_1 ? n4904_1 : n_n8611); - assign n2200 = n5789_1 | n5790; - assign n2205 = n5788 | (ndn3_29 & ~ndn3_32 & n4888); - assign n2210 = ~n4956 & ~preset & n_n8572; - assign n2215 = n5786 | n5787; - assign n2220 = n5785 | (~ndn3_9 & ndn3_7 & n4850); - assign n2225 = ~n4956 & ~preset & n_n9555; - assign n2230 = n5783 | n5784_1; - assign n2235 = ~preset & (n_n7050 | (ngfdn_3 & ~ndn3_50)); - assign n2240 = n5782 | (~ndn3_9 & ndn3_7 & n4888); - assign n2245 = ~preset & (n_n7140 | (ngfdn_3 & ~ndn3_50)); - assign n2250 = n5781 | (n_n9448 & n4890 & n4967); - assign n2255 = ~preset & (n_n6948 | (~ndn3_42 & ndn3_40)); - assign n2260 = n5777 | n5778 | n5779_1 | n5780; - assign n2265 = ~preset & ~ngfdn_3 & (ndn3_19 | nen3_19); - assign n2270 = ~preset & ~ngfdn_3 & (ndn3_28 | nen3_28); - assign n2275 = n5775 | n5776; - assign n2280 = n5773 | n5774_1; - assign n2285 = n5772 | (n4861 & (n4954_1 ^ n4955)); - assign n2290 = n5771 | (n_n8707 & n4891 & n4967); - assign n2295 = n5770 | (~ndn3_19 & nen3_19 & n4850); - assign n2300 = ~preset & ~ngfdn_3 & (nen3_36 | ~nsr3_37); - assign n2305 = n5769_1 | (n_n9284 & n4867 & n4967); - assign n2310 = n5767 | n5768; - assign n2315 = ~preset & (n4892 ? n4903 : n_n7736); - assign n2320 = n5765 | n5766; - assign n2325 = n5763 | n5764_1; - assign n2330 = ~preset & (n4892 ? n4887 : n_n8891); - assign n2335 = n5761 | n5762; - assign n2340 = n5760 | (n_n8557 & n4867 & n4967); - assign n2345 = n5758 | n5759_1; - assign n2350 = ~n4956 & ~preset & n_n9558; - assign n2355 = n5757 | (n4866 & (n4954_1 ^ n4955)); - assign n2360 = n5756 | (~nsr3_13 & ~ndn3_15 & n4878); - assign n2365 = ~preset & (n_n6956 | (~ngfdn_3 & ndn3_46)); - assign n2370 = ~preset & (n4847 ? n4903 : n_n8298); - assign n2375 = n5755 | (~ndn3_25 & ndn3_22 & n4850); - assign n2380 = n5753 | n5754_1; - assign n2385 = n5751 | n5752; - assign n2390 = ~n4956 & ~preset & n_n9552; - assign n2395 = n5750 | n5749_1 | (n_n8964 & n4898); - assign n2400 = ~n4956 & ~preset & n_n8016; - assign n2405 = n5747 | n5748; - assign n2410 = ~preset & (n4874_1 ? n4887 : n_n7696); - assign n2415 = n5745 | n5746; - assign n2420 = n5744_1 | (~ndn3_27 & ndn3_26 & n4888); - assign n2425 = n5743 | (n_n9353 & n4891 & n4967); - assign n2430 = n7181 | (~preset & n_n8652 & ~n5001); - assign n2435 = n7184 | (~preset & n_n8707 & ~n5001); - assign n2440 = n5741 | n5742; - assign n2445 = n5739_1 | n5740; - assign n2450 = n5738 | (~ndn3_29 & ndn3_28 & n4850); - assign n2455 = n7185 | (nsr3_30 & ~nak3_13); - assign n2460 = ~n4956 & ~preset & n_n8274; - assign n2465 = ~n4956 & ~preset & n_n8615; - assign n2470 = ~n4956 & ~preset & n_n8238; - assign n2475 = ~n4956 & ~preset & n_n7854; - assign n2480 = ~n4956 & ~preset & n_n8649; - assign n2485 = ~n4956 & ~preset & n_n8236; - assign n2490 = ~n4956 & ~preset & n_n8269; - assign n2495 = n5737 | (n_n9537 & n4896 & n4967); - assign n2500 = n5735 | n5736; - assign n2505 = n5733 | n5734_1; - assign n2510 = ~n4956 & ~preset & n_n8529; - assign n2515 = n5732 | (nen3_36 & ~ndn3_36 & n4878); - assign n2520 = n5731 | (n_n9434 & n4890 & n4967); - assign n2525 = ~n4956 & ~preset & n_n8685; - assign n2530 = ~preset & (n_n9531 | (~ndn3_46 & ndn3_44)); - assign n2535 = ~n4956 & ~preset & n_n9510; - assign n2540 = ~n4956 & ~preset & n_n7771; - assign n2545 = n5730 | (n_n8449 & n4845 & n4967); - assign n2550 = n5728 | n5729_1; - assign n2555 = n5727 | (nen3_36 & ~ndn3_36 & n4855); - assign n2560 = ~preset & ~ngfdn_3 & (ndn3_9 | ndn3_11); - assign n2565 = ~preset & ~ngfdn_3 & (~nsr3_13 | ndn3_15); - assign n2570 = ~preset & ~ngfdn_3 & (ndn3_19 | ndn3_21); - assign n2575 = ~n4956 & ~preset & n_n7584; - assign n2580 = n5723 | n5724_1 | n5725 | n5726; - assign n2585 = ~preset & (n_n6952 | (~ndn3_42 & ndn3_40)); - assign n2590 = n5722 | (ndn3_29 & ~ndn3_32 & n4878); - assign n2595 = n5720 | n5721; - assign n2600 = n5718 | n5719_1; - assign n2605 = n5717 | (n_n8549 & n4896 & n4967); - assign n2610 = n5716 | (n_n9284 & n4886 & n4967); - assign n2615 = n5714_1 | n5715; - assign n2620 = ~preset & (n_n7308 | (nen3_22 & ~ndn3_22)); - assign n2625 = n5712 | n5713; - assign n2630 = n5711 | (n_n9537 & n4867 & n4967); - assign n2635 = n5709_1 | n5710; - assign n2640 = ~preset & (n_n6912 | (~ndn3_42 & ndn3_40)); - assign n2645 = n5707 | n5708; - assign n2650 = n5706 | n5705 | (n_n8911 & n4898); - assign n2655 = ~preset & (n4881 ? n4887 : n_n7952); - assign n2660 = ~preset & (n_n8704 | (~ngfdn_3 & ndn3_46)); - assign n2665 = n5704_1 | (nen3_16 & ~ndn3_16 & n4873); - assign n2670 = n5703 | (n4866 & (n4969_1 ^ n4970)); - assign n2675 = n5701 | n5702; - assign n2680 = ~preset & (n4882 ? n4848 : n_n9019); - assign n2685 = ~preset & (n_n7699 | (nen3_22 & ~ndn3_22)); - assign n2690 = ~preset & (n4882 ? n4903 : n_n7375); - assign n2695 = n5699_1 | n5700; - assign n2700 = n5697 | n5698; - assign n2705 = n5696 | (ndn3_25 & ~ndn3_26 & n4850); - assign n2710 = n5694_1 | n5695; - assign n2715 = n5692 | n5693; - assign n2720 = n5690 | n5691; - assign n2725 = n5689_1 | (~ndn3_34 & nen3_34 & n4888); - assign n2730 = ~n4956 & ~preset & n_n7582; - assign n2735 = ~n4956 & ~preset & n_n8968; - assign n2740 = n5687 | n5688; - assign n2745 = n5685 | n5686; - assign n2750 = n5683 | n5684_1; - assign n2755 = ~preset & (n_n9373 | (~ndn3_46 & ndn3_44)); - assign n2760 = n4862 | (n_n9248 & (~n_n9247 | ~n4902)); - assign n2765 = n5682 | (n4866 & (n4971 ^ n4972)); - assign n2770 = n5680 | n5681; - assign n2775 = ~n4956 & ~preset & n_n8273; - assign n2780 = ~preset & (n_n6937 | (nen3_22 & ~ndn3_22)); - assign n2785 = n5679_1 | (nen3_16 & ~ndn3_16 & n4888); - assign n2790 = n5677 | n5678; - assign n2795 = n5676 | (n4846 & n4904_1); - assign n2800 = n5675 | (n4863 & (n4985 ^ n4986)); - assign n2805 = n5673 | n5674_1; - assign n2810 = n5671 | n5672; - assign n2815 = n5670 | (n_n9284 & n4890 & n4967); - assign n2820 = n5668 | n5669_1; - assign n2825 = ~preset & (n_n7181 | (~ndn3_46 & ndn3_44)); - assign n2830 = n5666 | n5667; - assign n2835 = n5664_1 | n5665; - assign n2840 = n5662 | n5663; - assign n2845 = n5661 | (~ndn3_17 & ndn3_16 & n4888); - assign n2850 = ~preset & (n4851 ? n4903 : n_n7487); - assign n2855 = n5659_1 | n5660; - assign n2860 = n5657 | n5658; - assign n2865 = n5656 | (n_n8449 & n4864_1 & n4967); - assign n2870 = ~preset & (n4874_1 ? n4868 : n_n9181); - assign n2875 = ~preset & (n_n8725 | (ngfdn_3 & ~ndn3_50)); - assign n2880 = n5654_1 | n5655; - assign n2885 = ~preset & ~ngfdn_3 & (ndn3_27 | ndn3_26); - assign n2890 = n5653 | (n_n8652 & n4891 & n4967); - assign n2895 = ~preset & (n_n7415 | (ndn3_42 & ~ndn3_44)); - assign n2900 = n5652 | (n_n8557 & n4896 & n4967); - assign n2905 = ~preset & ~ngfdn_3 & (nen3_19 | ~nsr3_20); - assign n2910 = ~preset & (n_n8762 | (ndn3_42 & ~ndn3_44)); - assign n2915 = ~preset & (n4880 ? n4904_1 : n_n8512); - assign n2920 = n5651 | (n_n8821 & n4864_1 & n4967); - assign n2925 = n5650 | (~ndn3_19 & nen3_19 & n4888); - assign n2930 = ~preset & (n_n7387 | (ndn3_42 & ~ndn3_44)); - assign n2935 = n5649_1 | (n_n9434 & n4886 & n4967); - assign n2940 = n5647 | n5648; - assign n2945 = n5645 | n5646; - assign n2950 = ~preset & (n4892 ? n4848 : n_n9157); - assign n2955 = n5644_1 | (nen3_36 & ~ndn3_36 & n4873); - assign n2960 = ~preset & (n_n7381 | (nen3_22 & ~ndn3_22)); - assign n2965 = ~preset & (n_n9446 | (~ndn3_42 & ndn3_40)); - assign n2970 = ~preset & (n_n8633 | (ndn3_39 & ~ndn3_40)); - assign n2975 = n5643 | (n4866 & (n4976 ^ n4977)); - assign n2980 = ~preset & (n_n7310 | (nen3_22 & ~ndn3_22)); - assign n2985 = n5642 | (ndn3_17 & ~ndn3_18 & n4855); - assign n2990 = n5640 | n5641; - assign n2995 = n5639_1 | (n_n8821 & n4896 & n4967); - assign n3000 = n5637 | n5638; - assign n3005 = n5635 | n5636; - assign n3010 = n5633 | n5634_1; - assign n3015 = ~preset & (n_n7315 | (ndn3_39 & ~ndn3_40)); - assign n3020 = ~preset & (n_n9476 | (ndn3_39 & ~ndn3_40)); - assign n3025 = n5631 | n5632; - assign n3030 = n5630 | (n_n9638 & n4883 & n4967); - assign n3035 = n5628 | n5629_1; - assign n3040 = n5627 | (~ndn3_28 & nen3_28 & n4850); - assign n3045 = n7190 | (~n4894_1 & (n7188 | n7189)); - assign n3050 = n5624_1 | n5625; - assign n3055 = n7191 | (~ndn3_29 & nsr3_35); - assign n3060 = ~preset & (n_n7154 | (ndn3_39 & ~ndn3_40)); - assign n3065 = ~preset & (n4875 ? n4868 : n_n9495); - assign n3070 = n5622 | n5623; - assign n3075 = n5621 | (n4866 & n4887); - assign n3080 = n5619_1 | n5620; - assign n3085 = n5617 | n5618; - assign n3090 = n5615 | n5616; - assign n3095 = n5614_1 | (n4853 & (n4985 ^ n4986)); - assign n3100 = n5612 | n5613; - assign n3105 = ~n4956 & ~preset & n_n8970; - assign n3110 = n5610 | n5611; - assign n3115 = n5608 | n5609_1; - assign n3120 = ~preset & (n_n7246 | (nen3_22 & ~ndn3_22)); - assign n3125 = n5606 | n5607; - assign n3130 = n5604_1 | n5605; - assign n3135 = ~preset & (n_n7635 | (ngfdn_3 & ~ndn3_50)); - assign n3140 = n5603 | (ndn3_11 & ~ndn3_12 & n4888); - assign n3145 = n5601 | n5602; - assign n3150 = n5600 | (nen3_39 & ~ndn3_39 & n4850); - assign n3155 = ~preset & (n4860 ? n4904_1 : n_n9108); - assign n3160 = ~preset & (n4851 ? n4887 : n_n9286); - assign n3165 = ~preset & ~ngfdn_3 & (ndn3_11 | ndn3_12); - assign n3170 = ~preset & ~ngfdn_3 & (nen3_16 | ndn3_16); - assign n3175 = ~preset & (n4876 ? n4848 : n_n7708); - assign n3180 = n5599_1 | (n_n8419 & n4864_1 & n4967); - assign n3185 = n5598 | (n_n8652 & n4864_1 & n4967); - assign n3190 = ~preset & (n4860 ? n4887 : n_n7947); - assign n3195 = n5596 | n5597; - assign n3200 = n5595 | (n_n8707 & n4864_1 & n4967); - assign n3205 = n5594_1 | (ndn3_19 & ~ndn3_21 & n4850); - assign n3210 = ~preset & (n_n7659 | (ndn3_42 & ~ndn3_44)); - assign n3215 = ~n4956 & ~preset & n_n7630; - assign n3220 = n5593 | (ndn3_19 & ~ndn3_21 & n4888); - assign n3225 = ~n4956 & ~preset & n_n8691; - assign n3230 = n5592 | (n_n9434 & n4867 & n4967); - assign n3235 = n5591 | (~ndn3_28 & nen3_28 & n4873); - assign n3240 = ~preset & (n4876 ? n4930 : n_n7995); - assign n3245 = n5589_1 | n5590; - assign n3250 = n5588 | (~nsr3_13 & ~ndn3_15 & n4873); - assign n3255 = ~preset & (n_n7507 | (ndn3_39 & ~ndn3_40)); - assign n3260 = ~preset & (n_n7959 | (~ngfdn_3 & ndn3_46)); - assign n3265 = n5586 | n5587; - assign n3270 = n5584_1 | n5585; - assign n3275 = n5582 | n5583; - assign n3280 = n5581 | (n_n9448 & n4886 & n4967); - assign n3285 = ~preset & (n4881 ? n4904_1 : n_n8106); - assign n3290 = n5579_1 | n5580; - assign n3295 = n5577 | n5578; - assign n3300 = n5575 | n5576; - assign n3305 = n5574_1 | (~ndn3_9 & ndn3_7 & n4873); - assign n3310 = n5573 | (~ndn3_9 & ndn3_7 & n4878); - assign n3315 = n5571 | n5572; - assign n3320 = ~preset & (n4885 ? n4930 : n_n9087); - assign n3325 = n5569_1 | n5570; - assign n3330 = ~n4956 & ~preset & n_n7852; - assign n3335 = n5567 | n5568; - assign n3340 = ~preset & (~n_n9198 | (~n4967 & n4974_1)); - assign n3345 = n5563 | n5564_1 | n5565 | n5566; - assign n3350 = n7193 | preset | (nsr3_13 & nsr3_14); - assign n3355 = n7197 | n5561 | n5562; - assign n3360 = ~preset & (n_n7026 | (ngfdn_3 & ~ndn3_50)); - assign n3365 = n5559_1 | n5560; - assign n3370 = ~n4956 & ~preset & n_n8272; - assign n3375 = n5558 | (n_n9284 & n4896 & n4967); - assign n3380 = ~n4956 & ~preset & n_n7985; - assign n3385 = ~n4956 & ~preset & n_n8312; - assign n3390 = n5556 | n5557; - assign n3395 = n5554_1 | n5555; - assign n3400 = n5552 | n5553; - assign n3405 = ~preset & (n_n8683 | (~ndn3_42 & ndn3_40)); - assign n3410 = ~preset & ~ngfdn_3 & (nen3_39 | ndn3_39); - assign n3415 = ~preset & (n_n8245 | (~ndn3_42 & ndn3_40)); - assign n3420 = n5551 | (~ndn3_34 & nen3_34 & n4873); - assign n3425 = n5549_1 | n5550; - assign n3430 = n5547 | n5548; - assign n3435 = n5545 | n5546; - assign n3440 = n5544_1 | (n_n8419 & n4896 & n4967); - assign n3445 = n5543 | (n_n9638 & n4886 & n4967); - assign n3450 = n5541 | n5542; - assign n3455 = ~preset & (n4869_1 ? n4848 : n_n8201); - assign n3460 = n5540 | (~ndn3_4 & ndn3_2 & n4855); - assign n3465 = n5538 | n5539_1; - assign n3470 = ~preset & (n_n8389 | (nen3_22 & ~ndn3_22)); - assign n3475 = ~n4956 & ~preset & n_n9440; - assign n3480 = n5536 | n5537; - assign n3485 = n5535 | (n_n8354 & n4886 & n4967); - assign n3490 = n5534_1 | (n_n9448 & n4867 & n4967); - assign n3495 = n5533 | (n_n9416 & n4896 & n4967); - assign n3500 = n5531 | n5532; - assign n3505 = n5530 | (~ndn3_7 & ndn3_4 & n4855); - assign n3510 = n5529_1 | (n_n8354 & n4883 & n4967); - assign n3515 = n5527 | n5528; - assign n3520 = ~preset & (n_n7209 | (ngfdn_3 & ~ndn3_50)); - assign n3525 = ~preset & (n_n7003 | (ngfdn_3 & ~ndn3_50)); - assign n3530 = ~preset & (n4852 ? n4887 : n_n7695); - assign n3535 = n5526 | (nen3_39 & ~ndn3_39 & n4873); - assign n3540 = n5524_1 | n5525; - assign n3545 = ~preset & (n4865 ? n4903 : n_n7374); - assign n3550 = n5522 | n5523; - assign n3555 = ~preset & (n_n7944 | (~ngfdn_3 & ndn3_46)); - assign n3560 = n5521 | (n_n9537 & n4891 & n4967); - assign n3565 = n5519_1 | n5520; - assign n3570 = ~preset & (n_n6988 | (ngfdn_3 & ~ndn3_50)); - assign n3575 = ~preset & (n_n6986 | (ndn3_39 & ~ndn3_40)); - assign n3580 = n5518 | n5517 | (n_n8933 & n4898); - assign n3585 = ~preset & (n_n7117 | (ndn3_39 & ~ndn3_40)); - assign n3590 = n5516 | (n_n9284 & n4845 & n4967); - assign n3595 = ~n4956 & ~preset & n_n8241; - assign n3600 = n5515 | (n1270 & (n4971 ^ n4972)); - assign n3605 = ~n4956 & ~preset & n_n8198; - assign n3610 = n5513 | n5514_1; - assign n3615 = ~n4956 & ~preset & n_n8575; - assign n3620 = ~n4956 & ~preset & n_n8710; - assign n3625 = ~preset & (n_n7622 | (nen3_22 & ~ndn3_22)); - assign n3630 = n5512 | (n_n8557 & n4845 & n4967); - assign n3635 = n5511 | (n_n8449 & n4890 & n4967); - assign n3640 = ~preset & (n_n7033 | (~ndn3_46 & ndn3_44)); - assign n3645 = ~preset & ~ngfdn_3 & (ndn3_34 | nen3_34); - assign n3650 = n5510 | (n_n9512 & n4883 & n4967); - assign n3655 = ndn3_50 & ~preset & ~ngfdn_3; - assign n3660 = n5509_1 | (n_n9416 & n4883 & n4967); - assign n3665 = ~preset & (n_n7019 | (ndn3_42 & ~ndn3_44)); - assign n3670 = n5508 | (n4861 & n4868); - assign n3675 = ~preset & (n_n7261 | (~ngfdn_3 & ndn3_46)); - assign n3680 = n5507 | (ndn3_29 & ~ndn3_32 & n4855); - assign n3685 = n5505 | n5506; - assign n3690 = ~preset & (n4876 ? n4903 : n_n7993); - assign n3695 = n5503 | n5504_1; - assign n3700 = n5501 | n5502; - assign n3705 = n5499_1 | n5500; - assign n3710 = n5497 | n5498; - assign n3715 = ~preset & (n_n8918 | (~ndn3_42 & ndn3_40)); - assign n3720 = ~preset & (n4882 ? n4904_1 : n_n8515); - assign n3725 = ~preset & (n4875 ? n4904_1 : n_n7933); - assign n3730 = ~preset & (n4847 ? n4930 : n_n8075); - assign n3735 = ~preset & (n_n7338 | (nen3_22 & ~ndn3_22)); - assign n3740 = ~preset & (n4882 ? n4930 : n_n8104); - assign n3745 = ~n4956 & ~preset & n_n8171; - assign n3750 = n5496 | (n_n8707 & n4890 & n4967); - assign n3755 = n5494_1 | n5495; - assign n3760 = n5492 | n5493; - assign n3765 = ~n4956 & ~preset & n_n9441; - assign n3770 = n5490 | n5491; - assign n3775 = ~preset & (n_n8831 | (ndn3_39 & ~ndn3_40)); - assign n3780 = ~preset & (n_n8441 | (ndn3_39 & ~ndn3_40)); - assign n3785 = n5489_1 | (n4846 & n4903); - assign n3790 = n5487 | n5488; - assign n3795 = ~n4956 & ~preset & n_n9363; - assign n3800 = ~preset & ~ngfdn_3 & (ndn3_4 | ndn3_2); - assign n3805 = n5485 | n5486; - assign n3810 = ~preset & (n_n7561 | (~ngfdn_3 & ndn3_46)); - assign n3815 = n5484_1 | n5483 | (n_n8923 & n4898); - assign n3820 = ~preset & (n_n7978 | (ndn3_39 & ~ndn3_40)); - assign n3825 = n5482 | n5481 | (n_n8978 & n4898); - assign n3830 = ~preset & (n4879_1 ? n4868 : n_n9499); - assign n3835 = ~preset & (n_n8713 | (~ndn3_46 & ndn3_44)); - assign n3840 = ~preset & (n_n8944 | (~ndn3_46 & ndn3_44)); - assign n3845 = ~n4956 & ~preset & n_n8239; - assign n3850 = ~preset & (n4889_1 ? n4930 : n_n7652); - assign n3855 = n5479_1 | n5480; - assign n3860 = ~n4956 & ~preset & n_n8530; - assign n3865 = n5477 | n5478; - assign n3870 = n5475 | n5476; - assign n3875 = n5474_1 | (n4848 & n4861); - assign n3880 = n5472 | n5473; - assign n3885 = n5471 | (~ndn3_34 & nen3_34 & n4855); - assign n3890 = n5469_1 | n5470; - assign n3895 = n5467 | n5468; - assign n3900 = n5466 | (~ndn3_27 & ndn3_26 & n4873); - assign n3905 = n5464_1 | n5465; - assign n3910 = ~n4956 & ~preset & n_n7961; - assign n3915 = n5462 | n5463; - assign n3920 = n5460 | n5461; - assign n3925 = n5459_1 | (n4861 & (n4969_1 ^ n4970)); - assign n3930 = n5458 | (n4863 & (n4954_1 ^ n4955)); - assign n3935 = ~preset & (n_n9161 | n4956); - assign n3940 = n5456 | n5457; - assign n3945 = n5454_1 | n5455; - assign n3950 = n5452 | n5453; - assign n3955 = n5450 | n5451; - assign n3960 = ~n4956 & ~preset & n_n9360; - assign n3965 = n5449_1 | (ndn3_25 & ~ndn3_26 & n4855); - assign n3970 = ~preset & (n_n8392 | (~ndn3_42 & ndn3_40)); - assign n3975 = n5448 | n5447 | (n_n9034 & n4898); - assign n3980 = ~preset & (n4879_1 ? n4887 : n_n8375); - assign n3985 = n5446 | (n_n9416 & n4845 & n4967); - assign n3990 = ~n4956 & ~preset & n_n9298; - assign n3995 = n5444_1 | n5445; - assign n4000 = n5442 | n5443; - assign n4005 = ~nsr1_2 & ~preset & ~pdn; - assign n4009 = n5440 | n5441; - assign n4014 = n5438 | n5439_1; - assign n4019 = ~n4956 & ~preset & n_n9291; - assign n4024 = n5436 | n5437; - assign n4029 = n5435 | (ndn3_11 & ~ndn3_12 & n4878); - assign n4034 = n5433 | n5434_1; - assign n4039 = n5432 | (n_n9353 & n4883 & n4967); - assign n4044 = n5430 | n5431; - assign n4049 = n5428 | n5429_1; - assign n4054 = n5426 | n5427; - assign n4059 = ~preset & (n4885 ? n4887 : n_n9351); - assign n4064 = n5425 | (n_n9638 & n4864_1 & n4967); - assign n4069 = n_n8668 & ~n4862; - assign n4074 = n5423 | n5424_1; - assign n4079 = ~preset & (n_n7013 | (~ngfdn_3 & ndn3_46)); - assign n4084 = n5422 | (n1270 & n4930); - assign n4089 = ~n4956 & ~preset & n_n8200; - assign n4094 = n5421 | (n1270 & n4903); - assign n4099 = ~n4956 & ~preset & n_n8803; - assign n4104 = n5419_1 | n5420; - assign n4109 = ~n4956 & ~preset & n_n8366; - assign n4114 = n5417 | n5418; - assign n4119 = ~n4956 & ~preset & n_n8650; - assign n4124 = ~n4956 & ~preset & n_n8574; - assign n4129 = ~preset & (n_n7276 | (nen3_22 & ~ndn3_22)); - assign n4134 = n5415 | n5416; - assign n4139 = n5413 | n5414_1; - assign n4144 = ~preset & ~nsr3_35; - assign n4149 = n5409_1 | n5410 | n5411 | n5412; - assign n4154 = ~preset & ~ngfdn_3 & (ndn3_46 | ndn3_44); - assign n4159 = n5407 | n5408; - assign n4164 = n5405 | n5406; - assign n4169 = n5403 | n5404_1; - assign n4174 = ~n4956 & ~preset & n_n9359; - assign n4179 = ~preset & (n4892 ? n4904_1 : n_n8425); - assign n4184 = n5402 | (n4846 & (n4969_1 ^ n4970)); - assign n4189 = n5401 | (n4853 & (n4954_1 ^ n4955)); - assign n4194 = n5397 | n5398 | n5399_1 | n5400; - assign n4199 = n5393 | n5394_1 | n5395 | n5396; - assign n4204 = n5392 | (~ndn3_25 & ndn3_22 & n4878); - assign n4209 = ~preset & (n_n7467 | (~ndn3_42 & ndn3_40)); - assign n4214 = n5390 | n5391; - assign n4219 = n5389_1 | (n4866 & n4904_1); - assign n4224 = n5388 | (n_n8557 & n4886 & n4967); - assign n4229 = ~preset & (n_n9162 | n4956); - assign n4234 = n5387 | (~ndn3_4 & ndn3_2 & n4878); - assign n4239 = ~preset & (n_n8055 | (~ngfdn_3 & ndn3_46)); - assign n4244 = n5386 | (n_n8354 & n4867 & n4967); - assign n4249 = n5385 | (n1270 & (n4969_1 ^ n4970)); - assign n4254 = n5384_1 | (n_n9512 & n4896 & n4967); - assign n4259 = ~preset & (n4875 ? n4848 : n_n7762); - assign n4264 = n5382 | n5383; - assign n4269 = n5380 | n5381; - assign n4274 = n5379_1 | (n_n9416 & n4890 & n4967); - assign n4279 = n5377 | n5378; - assign n4284 = n5375 | n5376; - assign n4289 = n5373 | n5374_1; - assign n4294 = n5371 | n5372; - assign n4299 = n5369_1 | n5370; - assign n4304 = ~preset & (n4885 ? n4903 : n_n9100); - assign n4309 = n5368 | (n_n9353 & n4864_1 & n4967); - assign n4314 = n5367 | (n_n9537 & n4864_1 & n4967); - assign n4319 = ~preset & (n4865 ? n4887 : n_n7588); - assign n4324 = ~preset & (n_n9123 | (ngfdn_3 & ~ndn3_50)); - assign n4329 = n5366 | (~ndn3_28 & nen3_28 & n4888); - assign n4334 = n5365 | (nen3_36 & ~ndn3_36 & n4850); - assign n4339 = n5363 | n5364_1; - assign n4344 = n5362 | (n4866 & n4930); - assign n4349 = n5360 | n5361; - assign n4354 = n5359_1 | (n4866 & n4903); - assign n4359 = n5357 | n5358; - assign n4364 = n5356 | (n_n9353 & n4896 & n4967); - assign n4369 = n5355 | (n4861 & (n4985 ^ n4986)); - assign n4374 = ~n4956 & ~preset & n_n8571; - assign n4379 = ~n4956 & ~preset & n_n8796; - assign n4384 = ~preset & ~ngfdn_3 & (nen3_36 | ndn3_36); - assign n4389 = n5354_1 | (n_n8354 & n4864_1 & n4967); - assign n4394 = n5352 | n5353; - assign n4399 = ~preset & (n_n8817 | (ndn3_42 & ~ndn3_44)); - assign n4404 = ~preset & (n_n9160 | n4956); - assign n4409 = n5351 | (n_n8449 & n4896 & n4967); - assign n4414 = ~preset & (n4869_1 ? n4904_1 : n_n8513); - assign n4419 = n5349_1 | n5350; - assign n4424 = n5348 | (ndn3_25 & ~ndn3_26 & n4878); - assign n4429 = n7206 | (~preset & n_n9284 & ~n5001); - assign n4434 = n5346 | n5347; - assign n4439 = n5345 | (~ndn3_29 & ndn3_28 & n4855); - assign n4444 = ~preset & (n4851 ? n4904_1 : n_n9203); - assign n4449 = ~preset & (n4879_1 ? n4930 : n_n7655); - assign n4454 = ~preset & (n_n8946 | (ndn3_39 & ~ndn3_40)); - assign n4459 = ~preset & (n_n7052 | (~ndn3_46 & ndn3_44)); - assign n4464 = ~preset & (n4851 ? n4848 : n_n9615); - assign n4469 = n5344_1 | (~ndn3_25 & ndn3_22 & n4855); - assign n4474 = ~preset & (n4875 ? n4903 : n_n7741); - assign n4479 = n5342 | n5343; - assign n4484 = ~preset & (n4877 ? n4904_1 : n_n7912); - assign n4489 = n5341 | (n1270 & n4868); - assign n4494 = ~preset & (n4875 ? n4887 : n_n9021); - assign n4499 = n5339_1 | n5340; - assign n4504 = n5338 | (nen3_16 & ~ndn3_16 & n4855); - assign n4509 = n5336 | n5337; - assign n4514 = n5334_1 | n5335; - assign n4519 = n5333 | (ndn3_9 & ~ndn3_11 & n4873); - assign n4524 = n5331 | n5332; - assign n4529 = ~preset & (n4847 ? n4887 : n_n7694); - assign n4534 = n5330 | (n_n9448 & n4891 & n4967); - assign n4539 = n5328 | n5329_1; - assign n4544 = ~preset & (n4879_1 ? n4904_1 : n_n7935); - assign n4549 = n5326 | n5327; - assign n4554 = ~n4956 & ~preset & n_n7701; - assign n4559 = ~preset & (n4877 ? n4930 : n_n7510); - assign n4564 = ~n4956 & ~preset & n_n7627; - assign n4569 = n5324_1 | n5325; - assign n4574 = ~preset & (n4849_1 ? n4904_1 : n_n8516); - assign n4579 = ~preset & (n4847 ? n4904_1 : n_n7913); - assign n4584 = n5323 | (n_n9284 & n4883 & n4967); - assign n4589 = ~preset & (n_n7411 | (ndn3_39 & ~ndn3_40)); - assign n4594 = n5322 | (~ndn3_27 & ndn3_26 & n4850); - assign n4599 = n5320 | n5321; - assign n4604 = n5318 | n5319_1; - assign n4609 = n5316 | n5317; - assign n4614 = ~preset & (n_n7242 | (ndn3_42 & ~ndn3_44)); - assign n4619 = ~preset & (n_n8230 | (ndn3_42 & ~ndn3_44)); - assign n4624 = ~n4956 & ~preset & n_n9294; - assign n4629 = n5315 | (n4863 & n4930); - assign n4634 = ~n4956 & ~preset & n_n8972; - assign n4639 = n5313 | n5314_1; - assign n4644 = ~preset & (n_n7493 | (ngfdn_3 & ~ndn3_50)); - assign n4649 = ~preset & (n_n8290 | (ngfdn_3 & ~ndn3_50)); - assign n4654 = n5309_1 | n5310 | n5311 | n5312; - assign n4659 = ~n4956 & ~preset & n_n7769; - assign n4664 = ~preset & (n_n7491 | (~ndn3_46 & ndn3_44)); - assign n4669 = n5307 | n5308; - assign n4674 = n5305 | n5306; - assign n4679 = ~preset & (n_n8047 | (ndn3_39 & ~ndn3_40)); - assign n4684 = n5303 | n5304_1; - assign n4689 = n5302 | (ndn3_29 & ~ndn3_32 & n4850); - assign n4694 = n5300 | n5301; - assign n4699 = n5299_1 | (n4846 & n4848); - assign n4704 = ~n4956 & ~preset & n_n8528; - assign n4709 = ~preset & ~nsr3_37; - assign n4714 = ~preset & ~ngfdn_3 & (ndn3_42 | ndn3_40); - assign n4719 = ~n4956 & ~preset & n_n9358; - assign n4724 = n5297 | n5298; - assign n4729 = ~preset & ~ngfdn_3 & (~nsr3_30 | nen3_28); - assign n4734 = n5296 | (~ndn3_28 & nen3_28 & n4878); - assign n4739 = ~preset & (n_n7903 | (ndn3_42 & ~ndn3_44)); - assign n4744 = n5294_1 | n5295; - assign n4749 = ~preset & (n4892 ? n4930 : n_n9075); - assign n4754 = ~n4956 & ~preset & n_n9439; - assign n4759 = n7209 | n5292 | n5293; - assign n4764 = n5290 | n5291; - assign n4769 = n5289_1 | n5288 | (n_n8798 & n4898); - assign n4774 = ~preset & (n_n7146 | (~ndn3_46 & ndn3_44)); - assign n4779 = n5286 | n5287; - assign n4784 = ~preset & (n_n7176 | (~ngfdn_3 & ndn3_46)); - assign n4789 = n5285 | (n_n8652 & n4845 & n4967); - assign n4794 = ~preset & (n4865 ? n4904_1 : n_n8514); - assign n4799 = n5284_1 | (n_n8707 & n4845 & n4967); - assign n4804 = ~preset & (n_n7183 | (ndn3_39 & ~ndn3_40)); - assign n4809 = n5283 | (n_n8419 & n4886 & n4967); - assign n4814 = n5282 | (n4866 & n4868); - assign n4819 = n5281 | (n_n8557 & n4891 & n4967); - assign n4824 = n5279_1 | n5280; - assign n4829 = n5278 | (n_n8549 & n4891 & n4967); - assign n4834 = n5276 | n5277; - assign n4839 = n5275 | (n_n8449 & n4891 & n4967); - assign n4844 = n5273 | n5274_1; - assign n4849 = n5271 | n5272; - assign n4854 = n5269_1 | n5270; - assign n4859 = n5267 | n5268; - assign n4864 = n5265 | n5266; - assign n4869 = n5264_1 | n5263 | (n_n9011 & n4898); - assign n4874 = n5261 | n5262; - assign n4879 = n5259_1 | n5260; - assign n4884 = n5257 | n5258; - assign n4889 = n5255 | n5256; - assign n4894 = ~preset & (n_n9164 | n4956); - assign n4899 = n5253 | n5254_1; - assign n4904 = n5251 | n5252; - assign n4909 = n5249_1 | n5250; - assign n4914 = n5248 | (~ndn3_4 & ndn3_2 & n4873); - assign n4919 = n5247 | (~ndn3_34 & nen3_34 & n4850); - assign n4924 = ~n4956 & ~preset & n_n7768; - assign n4929 = n5245 | n5246; - assign n4934 = n5244_1 | (n4861 & n4930); - assign n4939 = n5242 | n5243; - assign n4944 = n5241 | (n_n9434 & n4891 & n4967); - assign n4949 = n5239_1 | n5240; - assign n4954 = n5238 | (n4853 & n4930); - assign n4959 = n5237 | (n_n9638 & n4891 & n4967); - assign n4964 = n5235 | n5236; - assign n4969 = n5233 | n5234_1; - assign n4974 = ~preset & (n_n9228 | (~ngfdn_3 & ndn3_46)); - assign n4979 = n5232 | (~nsr3_13 & ~ndn3_15 & n4850); - assign n4984 = ~preset & (n_n8510 | (~ndn3_42 & ndn3_40)); - assign n4989 = ~preset & (n4869_1 ? n4868 : n_n8881); - assign n4994 = n5231 | (~ndn3_7 & ndn3_4 & n4850); - assign n4999 = n5229_1 | n5230; - assign n5004 = n5228 | n5227 | (n_n9031 & n4898); - assign n5009 = n7210 | (~nak3_13 & nsr3_37); - assign n5014 = ~n4956 & ~preset & n_n8197; - assign n5019 = n5225 | n5226; - assign n5024 = n5223 | n5224_1; - assign n5029 = n5221 | n5222; - assign n5034 = ~preset & ~ngfdn_3 & (ndn3_42 | ndn3_44); - assign n5039 = n5219_1 | n5220; - assign n5044 = n5218 | (n_n9448 & n4864_1 & n4967); - assign n5049 = n5216 | n5217; - assign n5054 = ~preset & ~pdn & (nsr1_2 | nlc1_2); - assign n5059 = n5214_1 | n5215; - assign n5064 = ~n4956 & ~preset & n_n8577; - assign n5069 = ~preset & (n_n7079 | (ndn3_42 & ~ndn3_44)); - assign n5074 = ~preset & (n4869_1 ? n4930 : n_n8828); - assign n5079 = n5213 | (n_n9638 & n4867 & n4967); - assign n5084 = n5211 | n5212; - assign n5089 = ~preset & (n4874_1 ? n4848 : n_n7901); - assign n5094 = n5209_1 | n5210; - assign n5099 = n5208 | n5207 | (n_n8869 & n4898); - assign n5104 = ~preset & (n4859_1 ? n4848 : n_n7710); - assign n5109 = n5206 | n5205 | (n_n8993 & n4898); - assign n5114 = ~preset & (n4885 ? n4904_1 : n_n9586); - assign n5119 = ~preset & (n4889_1 ? n4848 : n_n8852); - assign n5124 = n5204_1 | (~ndn3_17 & ndn3_16 & n4878); - assign n5129 = n5202 | n5203; - assign n5134 = ~preset & (n_n7717 | (ndn3_39 & ~ndn3_40)); - assign n5139 = n5201 | (n_n8821 & n4845 & n4967); - assign n5144 = ~preset & (n_n9163 | n4956); - assign n5149 = n5200 | (n_n8557 & n4883 & n4967); - assign n5154 = n5198 | n5199_1; - assign n5159 = n5196 | n5197; - assign n5164 = n5194_1 | n5195; - assign n5169 = n5192 | n5193; - assign n5174 = n5191 | (n_n8652 & n4890 & n4967); - assign n5179 = n5190 | (~ndn3_25 & ndn3_22 & n4888); - assign n5184 = n5188 | n5189_1; - assign n5189 = n5187 | (n_n9512 & n4890 & n4967); - assign n5194 = n5185 | n5186; - assign n5199 = n5184_1 | (~ndn3_17 & ndn3_16 & n4873); - assign n5204 = n5182 | n5183; - assign n5209 = ~preset & (n_n7330 | (ndn3_39 & ~ndn3_40)); - assign n5214 = n5180 | n5181; - assign n5219 = n5178 | n5179_1; - assign n5224 = n5177 | n5176 | (n_n8847 & n4898); - assign n5229 = n5174_1 | n5175; - assign n5234 = ~preset & (n4874_1 ? n4903 : n_n7553); - assign n5239 = ~n4956 & ~preset & n_n9292; - assign n5244 = ~preset & (n4854_1 ? n4887 : n_n7464); - assign n5249 = n5172 | n5173; - assign n5254 = n5170 | n5171; - assign n5259 = n5169_1 | (n_n9434 & n4883 & n4967); - assign n5264 = ~n4956 & ~preset & n_n8118; - assign n5269 = n5168 | (n4846 & n4930); - assign n5274 = n5167 | (n4861 & n4903); - assign n5279 = n5166 | (n4861 & (n4971 ^ n4972)); - assign n5284 = n5165 | (n_n9434 & n4864_1 & n4967); - assign n5289 = ~preset & ~ngfdn_3 & (ndn3_2 | n4949_1); - assign n5294 = n5164_1 | (n_n8652 & n4867 & n4967); - assign n5299 = n5162 | n5163; - assign n5304 = n5160 | n5161; - assign n5309 = ~preset & (n_n8665 | (ngfdn_3 & ~ndn3_50)); - assign n5314 = n5158 | n5159_1; - assign n5319 = n5156 | n5157; - assign n5324 = n5154_1 | n5155; - assign n5329 = ~preset & (n4876 ? n4868 : n_n9173); - assign n5334 = n5152 | n5153; - assign n5339 = ~preset & (n_n7150 | (~ndn3_42 & ndn3_40)); - assign n5344 = n5151 | (nen3_36 & ~ndn3_36 & n4888); - assign n5349 = n5149_1 | n5150; - assign n5354 = n7211 | (~ndn3_17 & nsr3_20); - assign n5359 = ~n4956 & ~preset & n_n8271; - assign n5364 = n5147 | n5148; - assign n5369 = n5146 | (n4853 & n4904_1); - assign n5374 = ~preset & ~ngfdn_3 & (ndn3_39 | ndn3_40); - assign n5379 = n5144_1 | n5145; - assign n5384 = n5143 | (~ndn3_4 & ndn3_2 & n4888); - assign n5389 = n5141 | n5142; - assign n5394 = n5139_1 | n5140; - assign n5399 = ~preset & (n4885 ? n4868 : n_n8462); - assign n5404 = n5137 | n5138; - assign n5409 = n5135 | n5136; - assign n5414 = ~n4956 & ~preset & n_n9289; - assign n5419 = ~preset & (n4881 ? n4930 : n_n7661); - assign n5424 = n5133 | n5134_1; - assign n5429 = ~preset & (n_n8921 | (~ndn3_46 & ndn3_44)); - assign n5434 = n5132 | (~ndn3_28 & nen3_28 & n4855); - assign n5439 = n5131 | (n_n9448 & n4896 & n4967); - assign n5444 = n5129_1 | n5130; - assign n5449 = n5128 | (n4866 & (n4985 ^ n4986)); - assign n5454 = n5126 | n5127; - assign n5459 = n5124_1 | n5125; - assign n5464 = n5123 | (n_n8449 & n4867 & n4967); - assign n5469 = n5121 | n5122; - assign n5474 = n5120 | (n_n8419 & n4867 & n4967); - assign n5479 = ~preset & (n_n7336 | (~ngfdn_3 & ndn3_46)); - assign n5484 = n5119_1 | (~ndn3_17 & ndn3_16 & n4855); - assign n5489 = n5117 | n5118; - assign n5494 = n5115 | n5116; - assign n5499 = n5113 | n5114_1; - assign n5504 = ~preset & (n_n8423 | (nen3_22 & ~ndn3_22)); - assign n5509 = ~preset & (n4881 ? n4848 : n_n7763); - assign n5514 = n5112 | (n_n8419 & n4891 & n4967); - assign n5519 = n5110 | n5111; - assign n5524 = n5108 | n5109_1; - assign n5529 = n5106 | n5107; - assign n5534 = n5104_1 | n5105; - assign n5539 = n5103 | (~ndn3_9 & ndn3_7 & n4855); - assign n5544 = ~preset & (n4852 ? n4903 : n_n9563); - assign n5549 = ~preset & (n_n8672 | (ngfdn_3 & ~ndn3_50)); - assign n5554 = ~preset & (n4854_1 ? n4930 : n_n7346); - assign n5559 = n5102 | (n_n8821 & n4890 & n4967); - assign n5564 = ~n4956 & ~preset & n_n8756; - assign n5569 = ~preset & (n4874_1 ? n4930 : n_n8641); - assign n5574 = n5100 | n5101; - assign n5579 = n5099_1 | (ndn3_17 & ~ndn3_18 & n4873); - assign n5584 = n5098 | n5097 | (n_n8561 & n4898); - assign n5589 = ~preset & (n_n9306 | (ngfdn_3 & ~ndn3_50)); - assign n5594 = ~preset & (n_n9165 | n4956); - assign n5599 = n5095 | n5096; - assign n5604 = ~preset & (n4847 ? n4848 : n_n9210); - assign n5609 = ~n4901 & ~preset & ndn2_2; - assign n5614 = ~preset & (n4865 ? n4930 : n_n7342); - assign n5619 = n5093 | n5094_1; - assign n5624 = n5092 | (n4846 & (n4971 ^ n4972)); - assign n5629 = n5090 | n5091; - assign n5634 = ~preset & (n_n9006 | (ndn3_42 & ~ndn3_44)); - assign n5639 = n5089_1 | (n_n8652 & n4886 & n4967); - assign n5644 = ~preset & (n_n7905 | (ndn3_42 & ~ndn3_44)); - assign n5649 = ~preset & (n_n9166 | n4956); - assign n5654 = ~preset & (n_n7065 | (ndn3_42 & ~ndn3_44)); - assign n5659 = ~preset & (n4892 ? n4868 : n_n9490); - assign n5664 = ~preset & (n_n7024 | (~ndn3_42 & ndn3_40)); - assign n5669 = ~preset & (n_n7586 | (~ngfdn_3 & ndn3_46)); - assign n5674 = n5087 | n5088; - assign n5679 = n5085 | n5086; - assign n5684 = ~n4956 & ~preset & n_n8141; - assign n5689 = ~n4956 & ~preset & n_n7853; - assign n5694 = ~preset & (n_n8121 | (~ndn3_42 & ndn3_40)); - assign n5699 = n5083 | n5084_1; - assign n5704 = ~preset & (n4849_1 ? n4868 : n_n9496); - assign n5709 = ~preset & (n_n8195 | (ndn3_42 & ~ndn3_44)); - assign n5714 = ~preset & (n4860 ? n4848 : n_n9516); - assign n5719 = n5082 | (~ndn3_27 & ndn3_26 & n4878); - assign n5724 = ~n4956 & ~preset & n_n9436; - assign n5729 = n5080 | n5081; - assign n5734 = n5078 | n5079_1; - assign n5739 = n5074_1 | n5075 | n5076 | n5077; - assign n5744 = n5073 | (n_n9416 & n4864_1 & n4967); - assign n5749 = n5072 | (ndn3_9 & ~ndn3_11 & n4850); - assign n5754 = n5071 | (n_n9353 & n4890 & n4967); - assign n5759 = ~n4956 & ~preset & n_n7770; - assign n5764 = ~preset & ~ngfdn_3 & (ndn3_29 | ndn3_32); - assign n5769 = n5069_1 | n5070; - assign n5774 = n5068 | (n4846 & n4868); - assign n5779 = n5067 | (n4863 & n4904_1); - assign n5784 = n5065 | n5066; - assign n5789 = n5063 | n5064_1; - assign n5794 = n5061 | n5062; - assign n5799 = ~preset & ~nsr3_38; - assign n5804 = n5059_1 | n5060; - assign n5809 = ~preset & (n4847 ? n4868 : n_n9179); - assign n5814 = ~n4956 & ~preset & n_n9357; - assign n5819 = n5057 | n5058; - assign n5824 = ~n4956 & ~preset & n_n7628; - assign n5829 = ~preset & (n_n8454 | (~ndn3_46 & ndn3_44)); - assign n5834 = ~preset & ~nsr3_20; - assign n5839 = n5056 | (n_n9448 & n4845 & n4967); - assign n5844 = ~preset & ~ngfdn_3 & (~nsr3_35 | nen3_34); - assign n5849 = n5055 | (n4861 & n4904_1); - assign n5854 = n5053 | n5054_1; - assign n5859 = n5051 | n5052; - assign n5864 = n5049_1 | n5050; - assign n5869 = ~preset & (n_n9578 | n4956); - assign n5874 = ~preset & (n4860 ? n4903 : n_n8135); - assign n5879 = ~preset & ~ngfdn_3 & (ndn3_25 | ndn3_26); - assign n5884 = n5047 | n5048; - assign n5889 = n5046 | (n4846 & (n4985 ^ n4986)); - assign n5894 = ~preset & (n_n8605 | (~ndn3_46 & ndn3_44)); - assign n5899 = ~n4956 & ~preset & n_n9296; - assign n5904 = n5044_1 | n5045; - assign n5909 = n5043 | (n_n9638 & n4890 & n4967); - assign n5914 = n5041 | n5042; - assign n5919 = n5040 | (nen3_39 & ~ndn3_39 & n4888); - assign n5924 = n5038 | n5039_1; - assign n5929 = ~n4956 & ~preset & n_n9275; - assign n5934 = n5036 | n5037; - assign n5939 = n5035 | (n_n9537 & n4890 & n4967); - assign n5944 = n5033 | n5034_1; - assign n5949 = n5031 | n5032; - assign n5954 = ~n4956 & ~preset & n_n7629; - assign n5959 = ~preset & ~nsr3_14; - assign n5964 = n5030 | (n4846 & (n4954_1 ^ n4955)); - assign n5969 = ~n4956 & ~preset & n_n9013; - assign n5974 = n5028 | n5029_1; - assign n5979 = n5027 | (n_n8557 & n4864_1 & n4967); - assign n5984 = ~preset & (n4854_1 ? n4848 : n_n7334); - assign n5989 = ~n4956 & ~preset & n_n7704; - assign n5994 = n5026 | (n_n8419 & n4845 & n4967); - assign n5999 = ~preset & (n4859_1 ? n4930 : n_n8526); - assign n6004 = ~n4956 & ~preset & n_n9556; - assign n6009 = n5025 | (ndn3_9 & ~ndn3_11 & n4888); - assign n6014 = ~n4956 & ~preset & n_n8447; - assign n6019 = n5023 | n5024_1; - assign n6024 = ~n4956 & ~preset & n_n8570; - assign n6029 = n5022 | (ndn3_25 & ~ndn3_26 & n4873); - assign n6034 = n5021 | (n_n8549 & n4864_1 & n4967); - assign n6039 = ~n4956 & ~preset & n_n8646; - assign n6044 = n5019_1 | n5020; - assign n6049 = n5018 | (n1270 & (n4976 ^ n4977)); - assign n6054 = n5017 | (ndn3_17 & ~ndn3_18 & n4850); - assign n6059 = ~preset & (n_n8216 | (~ndn3_46 & ndn3_44)); - assign n6064 = ~preset & (n4877 ? n4868 : n_n9177); - assign n6069 = n5015 | n5016; - assign n6074 = n5014_1 | (~ndn3_17 & ndn3_16 & n4850); - assign n6079 = n5012 | n5013; - assign n6084 = n5010 | n5011; - assign n6089 = ~preset & (n4854_1 ? n4868 : n_n8858); - assign n6094 = n5009_1 | (~ndn3_34 & nen3_34 & n4878); - assign n4845 = ~nsr3_37 & ~preset & ~ndn3_37; - assign n4846 = ~ndn3_40 & ~preset & ndn3_39; - assign n4847 = ndn3_9 & ~ndn3_11; - assign n4848 = n5002 ? ((~n4988 & ~n4989_1) | (~n4976 & (~n4989_1 | (~n4988 & n4989_1)))) : ((n4988 & n4989_1) | (n4976 & (n4988 ^ n4989_1))); - assign n4849_1 = ndn3_11 & ~ndn3_12; - assign n4850 = ~preset & (n4996 ^ (n6545 | n6546)); - assign n4851 = ndn3_25 & ~ndn3_26; - assign n4852 = ~ndn3_9 & ndn3_7; - assign n4853 = ndn3_44 & ~preset & ~ndn3_46; - assign n4854_1 = nen3_39 & ~ndn3_39; - assign n4855 = ~preset & (n4980 ^ (n6352 | n6353)); - assign n4856 = n_n9247 & n_n9248 & ~preset & ~n_n7306; - assign n4857 = n4856 & n5001; - assign n4858 = n4998 ? ((n4905 & n4906) | (n_n8549 & (n4905 | n4906))) : ((~n4905 & ~n4906) | (~n_n8549 & (~n4905 | ~n4906))); - assign n4859_1 = ~ndn3_27 & ndn3_26; - assign n4860 = ~ndn3_34 & nen3_34; - assign n4861 = ~ndn3_44 & ~preset & ndn3_42; - assign n4862 = ~n_n9198 | preset | (~n4967 & n4974_1); - assign n4863 = ndn3_40 & ~preset & ~ndn3_42; - assign n4864_1 = ~ndn3_35 & ~preset & ~nsr3_35; - assign n4865 = ~ndn3_19 & nen3_19; - assign n4866 = ~ndn3_22 & ~preset & nen3_22; - assign n4867 = ~nsr3_23 & ~preset & ~ndn3_23; - assign n4868 = n4965 ? ((~n4978 & ~n4979_1) | (~n4972 & (~n4979_1 | (~n4978 & n4979_1)))) : ((n4978 & n4979_1) | (n4972 & (~n4978 ^ ~n4979_1))); - assign n4869_1 = ~ndn3_29 & ndn3_28; - assign n4870 = n6282 | n6283 | n6284 | n7095; - assign n4871 = (n_n8821 & n4934_1) | ((n_n8821 | n4934_1) & (n7112 | n7113)); - assign n4872 = (n_n9638 & n4871) | ((n_n9638 | n4871) & (n7094 | n7095)); - assign n4873 = ~preset & (n5004_1 ^ (n6527 | n6528)); - assign n4874_1 = ~ndn3_4 & ndn3_2; - assign n4875 = nen3_16 & ~ndn3_16; - assign n4876 = nen3_36 & ~ndn3_36; - assign n4877 = ndn3_17 & ~ndn3_18; - assign n4878 = ~preset & (n4997 ^ (n6083 | n6084_1)); - assign n4879_1 = ~ndn3_7 & ndn3_4; - assign n4880 = ndn3_29 & ~ndn3_32; - assign n4881 = ~nsr3_13 & ~ndn3_15; - assign n4882 = ~ndn3_17 & ndn3_16; - assign n4883 = ~nsr3_13 & ~preset & ~ndn3_13; - assign n4884_1 = pdn ? ~ndn1_4 : ~nsr1_2; - assign n4885 = ndn3_19 & ~ndn3_21; - assign n4886 = ~ndn3_20 & ~preset & ~nsr3_20; - assign n4887 = n4966 ? ((~n5007 & ~n5008) | (~n4969_1 & (~n5008 | (~n5007 & n5008)))) : ((n5007 & n5008) | (n4969_1 & (~n5007 ^ ~n5008))); - assign n4888 = ~preset & (n4987 ^ (n6433 | n6434)); - assign n4889_1 = ~ndn3_25 & ndn3_22; - assign n4890 = ~ndn3_38 & ~preset & ~nsr3_38; - assign n4891 = ~ndn3_14 & ~preset & ~nsr3_14; - assign n4892 = ~ndn3_28 & nen3_28; - assign n4893 = n6261 | n6262 | n6263 | n7097; - assign n4894_1 = (n_n9512 & n4919_1) | ((n_n9512 | n4919_1) & (n7098 | n7099)); - assign n4895 = (n_n9434 & n4894_1) | ((n_n9434 | n4894_1) & (n7096 | n7097)); - assign n4896 = ~nsr3_30 & ~preset & ~ndn3_30; - assign n4897 = n6857 | n6858; - assign n4898 = ~preset & (n4975 ? n4967 : ~n5001); - assign n4899_1 = ~n_n8631 ^ (n_n8561 | n4999_1); - assign n4900 = n6859 | n6860; - assign n4901 = ~nlc1_2 & preset_0_0_ & nsr1_2; - assign n4902 = n7173 & n7172 & ~n4907 & ~n4940; - assign n4903 = n4973 ? ((~n4981 & ~n4982) | (~n4955 & (~n4982 | (~n4981 & n4982)))) : ((n4981 & n4982) | (n4955 & (~n4981 ^ ~n4982))); - assign n4904_1 = n4952 ? ((~n4994_1 & ~n4995) | (~n4986 & (~n4995 | (~n4994_1 & n4995)))) : ((n4994_1 & n4995) | (n4986 & (~n4994_1 ^ ~n4995))); - assign n4905 = n6303 | n6304 | n6305 | n7091; - assign n4906 = (n_n8449 & n4932) | ((n_n8449 | n4932) & (n7092 | n7093)); - assign n4907 = (~n_n8913 & ~n_n8964 & ~n4968) | (n_n8964 & (n_n8913 | n4968)); - assign n4908 = n6861 | n6862; - assign n4909_1 = n_n8652 & (n7100 | n7101); - assign n4910 = n6233 | n6234 | n6235 | n7101; - assign n4911 = (n_n9284 & n4909_1) | ((n_n9284 | n4909_1) & (n7102 | n7103)); - assign n4912 = (n_n8707 & n4911) | ((n_n8707 | n4911) & (n7104 | n7105)); - assign n4913 = n6226 | n6227 | n6228 | n7105; - assign n4914_1 = (n_n8354 & n4915) | ((n_n8354 | n4915) & (n7116 | n7117)); - assign n4915 = (n_n9448 & n4872) | ((n_n9448 | n4872) & (n7114 | n7115)); - assign n4916 = n6212 | n6213 | n6214 | n7117; - assign n4917 = n6863 | n6864; - assign n4918 = n6254 | n6255 | n6256 | n7099; - assign n4919_1 = (n_n9353 & n4912) | ((n_n9353 | n4912) & (n7106 | n7107)); - assign n4920 = (n_n9353 & (n4912 | n4938)) | n4918 | (n4912 & n4938); - assign n4921 = n6268 | n6269 | n6270 | n7109; - assign n4922 = (n_n9416 & n4895) | ((n_n9416 | n4895) & (n7108 | n7109)); - assign n4923 = n6867 | n6868; - assign n4924_1 = (n_n8923 & (~n_n8603 | n_n8798)) | (n_n8603 & ~n_n8923 & ~n_n8798); - assign n4925 = n6869 | n6870; - assign n4926 = n6871 | n6872; - assign n4927 = (~n_n8911 & ~n_n8933 & ~n_n8978 & ~n5000) | (n_n8978 & (n_n8911 | n_n8933 | n5000)); - assign n4928 = (~n_n9034 & ~n_n9031 & ~n_n8993 & ~n5005) | (n_n9034 & (n_n9031 | n_n8993 | n5005)); - assign n4929_1 = n6873 | n6874; - assign n4930 = (~n6992 & ~n6993 & (n6999 | n7000)) | (~n6999 & ~n7000 & (n6992 | n6993)); - assign n4931 = n6296 | n6297 | n6298 | n7093; - assign n4932 = (n_n8419 & n4914_1) | ((n_n8419 | n4914_1) & (n7118 | n7119)); - assign n4933 = n6289 | n6290 | n6291 | n7115; - assign n4934_1 = (n_n9537 & n4922) | ((n_n9537 | n4922) & (n7110 | n7111)); - assign n4935 = n6275 | n6276 | n6277 | n7111; - assign n4936 = n6240 | n6241 | n6242 | n7103; - assign n4937 = n6219 | n6220 | n6221 | n7113; - assign n4938 = n6247 | n6248 | n6249 | n7107; - assign n4939_1 = n6875 | n6876; - assign n4940 = (~n_n8913 & ~n_n8964 & ~n_n9011 & ~n4968) | (n_n9011 & (n_n8913 | n_n8964 | n4968)); - assign n4941 = n6877 | n6878; - assign n4942 = n6879 | n6880; - assign n4943 = ~n_n9031 ^ (n_n8993 | n5005); - assign n4944_1 = n6881 | n6882; - assign n4945 = (n_n8869 & (~n_n8603 | n_n8923 | n_n8798)) | (n_n8603 & ~n_n8923 & ~n_n8798 & ~n_n8869); - assign n4946 = n6883 | n6884; - assign n4947 = (~n_n8631 & ~n_n8847 & ~n_n8561 & ~n4999_1) | (n_n8847 & (n_n8631 | n_n8561 | n4999_1)); - assign n4948 = n6885 | n6886; - assign n4949_1 = nsr1_2 & (nlc1_2 ? n_n7476 : ~preset_0_0_); - assign n4950 = n6887 | n6888; - assign n4951 = n6205 | n6206 | n6207 | n7119; - assign n4952 = (~n7157 & ~n7158 & (n7164 | n7165)) | (~n7164 & ~n7165 & (n7157 | n7158)); - assign n4953 = n_n9247 & ~n_n7306 & n_n9248; - assign n4954_1 = (~n6978 & ~n6979 & (n6985 | n6986)) | (~n6985 & ~n6986 & (n6978 | n6979)); - assign n4955 = (n6992 | n6993) & (n6999 | n7000); - assign n4956 = ~ndn2_2 & ~nlc1_2 & preset_0_0_ & nsr1_2; - assign n4957 = nsr3_13 ? ndn3_12 : nsr3_14; - assign n4958 = (nen3_36 & ~ndn3_36) | (~ndn3_4 & ndn3_2); - assign n4959_1 = (~ndn3_29 & ndn3_28) | (nen3_39 & ~ndn3_39); - assign n4960 = (ndn3_42 & ~ndn3_44) | (~ndn3_34 & nen3_34); - assign n4961 = (~ndn3_19 & nen3_19) | (~ndn3_28 & nen3_28); - assign n4962 = (ndn3_39 & ~ndn3_40) | (ndn3_25 & ~ndn3_26); - assign n4963 = (~ndn3_42 & ndn3_40) | (ndn3_29 & ~ndn3_32); - assign n4964_1 = (~ndn3_17 & ndn3_16) | (~ndn3_27 & ndn3_26); - assign n4965 = (~n6922 & ~n6923 & (n6929 | n6930)) | (~n6929 & ~n6930 & (n6922 | n6923)); - assign n4966 = (~n7048 & ~n7049 & (n7055 | n7056)) | (~n7055 & ~n7056 & (n7048 | n7049)); - assign n4967 = n_n8930 ? n_n8929 : (n6897 | n6898); - assign n4968 = n_n8631 | n_n8847 | n_n8561 | n4999_1; - assign n4969_1 = (n4992 & n4993) | ((n6527 | n6528) & (~n4992 ^ ~n4993)); - assign n4970 = (~n7006 & ~n7007 & (n7013 | n7014)) | (~n7013 & ~n7014 & (n7006 | n7007)); - assign n4971 = (~n6936 & ~n6937 & (n6943 | n6944)) | (~n6943 & ~n6944 & (n6936 | n6937)); - assign n4972 = (n4990 & n4991) | ((n6545 | n6546) & (~n4990 ^ ~n4991)); - assign n4973 = (~n6964 & ~n6965 & (n6971 | n6972)) | (~n6971 & ~n6972 & (n6964 | n6965)); - assign n4974_1 = n4957 | n7086 | n7087 | n7088; - assign n4975 = ~n_n8668 & (~n_n9198 | (~n4967 & n4974_1)); - assign n4976 = (n4983 & n4984_1) | ((n6433 | n6434) & (~n4983 ^ ~n4984_1)); - assign n4977 = (~n7020 & ~n7021 & (n7027 | n7028)) | (~n7027 & ~n7028 & (n7020 | n7021)); - assign n4978 = n6665 | n6666 | n6935 | n6937; - assign n4979_1 = n6651 | n6652 | n6942 | n6944; - assign n4980 = (~n7076 & ~n7077 & (n7083 | n7084)) | (~n7083 & ~n7084 & (n7076 | n7077)); - assign n4981 = n6593 | n6594 | n6977 | n6979; - assign n4982 = n6607 | n6608 | n6984 | n6986; - assign n4983 = n6465 | n6466 | n7033 | n7035; - assign n4984_1 = n6417 | n6418 | n7040 | n7042; - assign n4985 = (~n7129 & ~n7130 & (n7136 | n7137)) | (~n7136 & ~n7137 & (n7129 | n7130)); - assign n4986 = (n5003 & n5006) | ((n6352 | n6353) & (~n5003 ^ ~n5006)); - assign n4987 = (~n7034 & ~n7035 & (n7041 | n7042)) | (~n7041 & ~n7042 & (n7034 | n7035)); - assign n4988 = n6387 | n6388 | n7019 | n7021; - assign n4989_1 = n6401 | n6402 | n7026 | n7028; - assign n4990 = n6637 | n6638 | n6949 | n6951; - assign n4991 = n6529 | n6530 | n6956 | n6958; - assign n4992 = n6711 | n6712 | n6905 | n6907; - assign n4993 = n6511 | n6512 | n6914 | n6916; - assign n4994_1 = n6163 | n6164 | n7128 | n7130; - assign n4995 = n6147 | n6148 | n7135 | n7137; - assign n4996 = (~n6950 & ~n6951 & (n6957 | n6958)) | (~n6957 & ~n6958 & (n6950 | n6951)); - assign n4997 = (~n7143 & ~n7144 & (n7150 | n7151)) | (~n7150 & ~n7151 & (n7143 | n7144)); - assign n4998 = n6198 | n6199 | n6200 | n7120; - assign n4999_1 = n_n9034 | n_n9031 | n_n8993 | n5005; - assign n5000 = ~n_n8603 | n_n8923 | n_n8798 | n_n8869; - assign n5001 = n_n9247 ? n7085 : (n4967 & n7089); - assign n5002 = (~n7062 & ~n7063 & (n7069 | n7070)) | (~n7069 & ~n7070 & (n7062 | n7063)); - assign n5003 = n6322 | n6323 | n7075 | n7077; - assign n5004_1 = (~n6906 & ~n6907 & (n6915 | n6916)) | (~n6915 & ~n6916 & (n6906 | n6907)); - assign n5005 = n_n8911 | n_n8933 | n_n8978 | n5000; - assign n5006 = n6338 | n6339 | n7082 | n7084; - assign n5007 = n6497 | n6498 | n7005 | n7007; - assign n5008 = n6481 | n6482 | n7012 | n7014; - assign n5009_1 = ~preset & n_n8580 & (ndn3_34 | ~nen3_34); - assign n5010 = ~preset & n_n8428 & (ndn3_46 | ~ndn3_44); - assign n5011 = ~ndn3_46 & ~preset & n_n9333 & ndn3_44; - assign n5012 = ~preset & n_n9145 & (ngfdn_3 | ~ndn3_46); - assign n5013 = n_n9629 & ndn3_46 & ~preset & ~ngfdn_3; - assign n5014_1 = ~preset & n_n8811 & (ndn3_17 | ~ndn3_16); - assign n5015 = ~preset & n_n7844 & (~nen3_36 | ndn3_36); - assign n5016 = ~preset & n4876 & (~n4985 ^ ~n4986); - assign n5017 = ~preset & n_n9131 & (~ndn3_17 | ndn3_18); - assign n5018 = ~preset & n_n8948 & (ngfdn_3 | ~ndn3_46); - assign n5019_1 = ~ndn3_2 & ~preset & psv26_3_3_ & n4949_1; - assign n5020 = ~preset & n_n9405 & (ndn3_2 | ~n4949_1); - assign n5021 = ~preset & n_n7928 & (nsr3_35 | ndn3_35); - assign n5022 = ~preset & n_n7453 & (~ndn3_25 | ndn3_26); - assign n5023 = ~preset & n_n7485 & (~ndn3_25 | ndn3_26); - assign n5024_1 = ~preset & n4851 & (~n4971 ^ ~n4972); - assign n5025 = ~preset & n_n9345 & (~ndn3_9 | ndn3_11); - assign n5026 = ~preset & n_n7788 & (ndn3_37 | nsr3_37); - assign n5027 = ~preset & n_n8078 & (nsr3_35 | ndn3_35); - assign n5028 = ~preset & n_n7288 & (~ngfdn_3 | ndn3_50); - assign n5029_1 = ~ndn3_50 & n_n9282 & ~preset & ngfdn_3; - assign n5030 = ~preset & n_n7862 & (~ndn3_39 | ndn3_40); - assign n5031 = ~ndn3_2 & ~preset & psv18_9_9_ & n4949_1; - assign n5032 = ~preset & n_n6976 & (ndn3_2 | ~n4949_1); - assign n5033 = ~preset & n_n7344 & (~ngfdn_3 | ndn3_50); - assign n5034_1 = ~ndn3_50 & ~preset & ngfdn_3 & n_n9570; - assign n5035 = ~preset & n_n9590 & (nsr3_38 | ndn3_38); - assign n5036 = ~preset & n_n7203 & (ndn3_46 | ~ndn3_44); - assign n5037 = ~ndn3_46 & ~preset & n_n9125 & ndn3_44; - assign n5038 = ~ndn3_2 & ~preset & psv38_14_14_ & n4949_1; - assign n5039_1 = ~preset & n_n8139 & (ndn3_2 | ~n4949_1); - assign n5040 = ~preset & n_n8991 & (~nen3_39 | ndn3_39); - assign n5041 = ~preset & n_n8895 & (ngfdn_3 | ~ndn3_46); - assign n5042 = ndn3_46 & n_n7570 & ~preset & ~ngfdn_3; - assign n5043 = ~preset & n_n7920 & (nsr3_38 | ndn3_38); - assign n5044_1 = ~preset & n_n7156 & (~ndn3_42 | ndn3_44); - assign n5045 = ~ndn3_44 & ndn3_42 & ~preset & n_n8609; - assign n5046 = ~preset & n_n6974 & (~ndn3_39 | ndn3_40); - assign n5047 = ~preset & n_n7500 & (~nen3_22 | ndn3_22); - assign n5048 = ~ndn3_22 & ~preset & nen3_22 & n_n9460; - assign n5049_1 = ~preset & n_n9048 & (~ndn3_17 | ndn3_18); - assign n5050 = ~preset & n4877 & (~n4954_1 ^ ~n4955); - assign n5051 = ~ndn3_2 & ~preset & psv38_7_7_ & n4949_1; - assign n5052 = ~preset & n_n9262 & (ndn3_2 | ~n4949_1); - assign n5053 = ~preset & n_n7076 & (~nen3_22 | ndn3_22); - assign n5054_1 = ~ndn3_22 & ~preset & nen3_22 & n_n8462; - assign n5055 = ~preset & n_n9632 & (~ndn3_42 | ndn3_44); - assign n5056 = ~preset & n_n9505 & (ndn3_37 | nsr3_37); - assign n5057 = ~ndn3_2 & ~preset & psv18_7_7_ & n4949_1; - assign n5058 = ~preset & n_n9594 & (ndn3_2 | ~n4949_1); - assign n5059_1 = ~ndn3_2 & ~preset & psv18_13_13_ & n4949_1; - assign n5060 = ~preset & n_n7886 & (ndn3_2 | ~n4949_1); - assign n5061 = ~preset & n_n9269 & (ndn3_4 | ~ndn3_2); - assign n5062 = ~preset & n4874_1 & (~n4969_1 ^ ~n4970); - assign n5063 = ~preset & n_n7111 & (~ngfdn_3 | ndn3_50); - assign n5064_1 = ~ndn3_50 & ~preset & ngfdn_3 & n_n9028; - assign n5065 = ~ndn3_2 & ~preset & psv2_7_7_ & n4949_1; - assign n5066 = ~preset & n_n9606 & (ndn3_2 | ~n4949_1); - assign n5067 = ~preset & n_n7927 & (ndn3_42 | ~ndn3_40); - assign n5068 = ~preset & n_n8206 & (~ndn3_39 | ndn3_40); - assign n5069_1 = ~preset & n_n7601 & (ndn3_27 | ~ndn3_26); - assign n5070 = ~preset & n4859_1 & (~n4971 ^ ~n4972); - assign n5071 = ~preset & n_n9392 & (nsr3_38 | ndn3_38); - assign n5072 = ~preset & n_n9133 & (~ndn3_9 | ndn3_11); - assign n5073 = ~preset & n_n7874 & (nsr3_35 | ndn3_35); - assign n5074_1 = n7212 & ((n4915 & n4916) | (n_n8354 & (n4915 | n4916))); - assign n5075 = ~n_n8419 & n4857 & (~n4914_1 ^ ~n4951); - assign n5076 = ~n4951 & ~n4914_1 & n_n8419 & n4856; - assign n5077 = ~n5001 & ~preset & n_n8419; - assign n5078 = ~preset & n_n7664 & (~nen3_36 | ndn3_36); - assign n5079_1 = ~preset & n4876 & (~n4976 ^ ~n4977); - assign n5080 = ~preset & n_n9051 & (ndn3_9 | ~ndn3_7); - assign n5081 = ~preset & n4852 & (~n4954_1 ^ ~n4955); - assign n5082 = ~preset & n_n9077 & (ndn3_27 | ~ndn3_26); - assign n5083 = ~ndn3_2 & ~preset & psv13_7_7_ & n4949_1; - assign n5084_1 = ~preset & n_n9604 & (ndn3_2 | ~n4949_1); - assign n5085 = ~preset & n_n8937 & (ndn3_29 | ~ndn3_28); - assign n5086 = ~preset & n4869_1 & (~n4969_1 ^ ~n4970); - assign n5087 = ~ndn3_2 & ~preset & psv39_9_9_ & n4949_1; - assign n5088 = ~preset & n_n8416 & (ndn3_2 | ~n4949_1); - assign n5089_1 = ~preset & n_n7653 & (nsr3_20 | ndn3_20); - assign n5090 = ~ndn3_2 & ~preset & psv33_9_9_ & n4949_1; - assign n5091 = ~preset & n_n9348 & (ndn3_2 | ~n4949_1); - assign n5092 = ~preset & n_n7136 & (~ndn3_39 | ndn3_40); - assign n5093 = ~ndn3_2 & ~preset & psv26_6_6_ & n4949_1; - assign n5094_1 = ~preset & n_n8051 & (ndn3_2 | ~n4949_1); - assign n5095 = ~preset & n_n8850 & (ngfdn_3 | ~ndn3_46); - assign n5096 = ndn3_46 & n_n9573 & ~preset & ~ngfdn_3; - assign n5097 = n4950 & (n5975 | (n4975 & n7176)); - assign n5098 = n4856 & (n_n8561 ^ ~n4999_1); - assign n5099_1 = ~preset & n_n8058 & (~ndn3_17 | ndn3_18); - assign n5100 = ~ndn3_2 & ~preset & psv26_15_15_ & n4949_1; - assign n5101 = ~preset & n_n8192 & (ndn3_2 | ~n4949_1); - assign n5102 = ~preset & n_n7949 & (nsr3_38 | ndn3_38); - assign n5103 = ~preset & n_n7792 & (ndn3_9 | ~ndn3_7); - assign n5104_1 = ~ndn3_2 & ~preset & psv18_4_4_ & n4949_1; - assign n5105 = ~preset & n_n9232 & (ndn3_2 | ~n4949_1); - assign n5106 = ~ndn3_2 & ~preset & psv13_12_12_ & n4949_1; - assign n5107 = ~preset & n_n7815 & (ndn3_2 | ~n4949_1); - assign n5108 = ~ndn3_2 & ~preset & psv2_6_6_ & n4949_1; - assign n5109_1 = ~preset & n_n7881 & (ndn3_2 | ~n4949_1); - assign n5110 = ~ndn3_2 & ~preset & psv18_0_0_ & n4949_1; - assign n5111 = ~preset & n_n8033 & (ndn3_2 | ~n4949_1); - assign n5112 = ~preset & n_n9525 & (nsr3_14 | ndn3_14); - assign n5113 = ~ndn3_2 & ~preset & psv2_0_0_ & n4949_1; - assign n5114_1 = ~preset & n_n8770 & (ndn3_2 | ~n4949_1); - assign n5115 = n4949_1 & ~ndn3_2 & pinp_6_6_ & ~preset; - assign n5116 = ~preset & n_n7644 & (ndn3_2 | ~n4949_1); - assign n5117 = ~preset & n_n8151 & (ndn3_19 | ~nen3_19); - assign n5118 = ~preset & n4865 & (~n4976 ^ ~n4977); - assign n5119_1 = ~preset & n_n8226 & (ndn3_17 | ~ndn3_16); - assign n5120 = ~preset & n_n8841 & (ndn3_23 | nsr3_23); - assign n5121 = ~preset & n_n8280 & (ndn3_19 | ~nen3_19); - assign n5122 = ~preset & n4865 & (~n4985 ^ ~n4986); - assign n5123 = ~preset & n_n7846 & (ndn3_23 | nsr3_23); - assign n5124_1 = ~preset & n_n7678 & (ndn3_42 | ~ndn3_40); - assign n5125 = n_n7862 & ndn3_40 & ~preset & ~ndn3_42; - assign n5126 = ~preset & n_n7666 & (ndn3_27 | ~ndn3_26); - assign n5127 = ~preset & n4859_1 & (~n4976 ^ ~n4977); - assign n5128 = ~preset & n_n9520 & (~nen3_22 | ndn3_22); - assign n5129_1 = ~ndn3_2 & ~preset & psv39_8_8_ & n4949_1; - assign n5130 = ~preset & n_n7956 & (ndn3_2 | ~n4949_1); - assign n5131 = ~preset & n_n7732 & (ndn3_30 | nsr3_30); - assign n5132 = ~preset & n_n7859 & (ndn3_28 | ~nen3_28); - assign n5133 = n4949_1 & ~ndn3_2 & pinp_12_12_ & ~preset; - assign n5134_1 = ~preset & n_n8108 & (ndn3_2 | ~n4949_1); - assign n5135 = ~preset & n_n9026 & (~nen3_22 | ndn3_22); - assign n5136 = ~ndn3_22 & ~preset & nen3_22 & n_n7236; - assign n5137 = ~ndn3_2 & ~preset & psv38_12_12_ & n4949_1; - assign n5138 = ~preset & n_n8088 & (ndn3_2 | ~n4949_1); - assign n5139_1 = ~ndn3_2 & ~preset & psv38_13_13_ & n4949_1; - assign n5140 = ~preset & n_n9225 & (ndn3_2 | ~n4949_1); - assign n5141 = ~preset & n_n8102 & (ndn3_42 | ~ndn3_40); - assign n5142 = ndn3_40 & n_n9542 & ~preset & ~ndn3_42; - assign n5143 = ~preset & n_n9347 & (ndn3_4 | ~ndn3_2); - assign n5144_1 = ~preset & n_n7130 & (ngfdn_3 | ~ndn3_46); - assign n5145 = ndn3_46 & n_n7527 & ~preset & ~ngfdn_3; - assign n5146 = ~preset & n_n7444 & (ndn3_46 | ~ndn3_44); - assign n5147 = ~preset & n_n9542 & (~ndn3_39 | ndn3_40); - assign n5148 = n4846 & (n4997 ^ (n6083 | n6084_1)); - assign n5149_1 = ~preset & n_n8371 & (ndn3_42 | ~ndn3_40); - assign n5150 = ndn3_40 & n_n9452 & ~preset & ~ndn3_42; - assign n5151 = ~preset & n_n9455 & (~nen3_36 | ndn3_36); - assign n5152 = ~preset & n_n9261 & (~nen3_36 | ndn3_36); - assign n5153 = ~preset & n4876 & (~n4969_1 ^ ~n4970); - assign n5154_1 = ~preset & n_n7022 & (ndn3_42 | ~ndn3_40); - assign n5155 = ~ndn3_42 & ~preset & n_n8959 & ndn3_40; - assign n5156 = ~preset & n_n8303 & (ndn3_42 | ~ndn3_40); - assign n5157 = ~ndn3_42 & ~preset & n_n8957 & ndn3_40; - assign n5158 = ~preset & n_n9593 & (ndn3_28 | ~nen3_28); - assign n5159_1 = ~preset & n4892 & (~n4969_1 ^ ~n4970); - assign n5160 = ~preset & n_n7435 & (~ndn3_42 | ndn3_44); - assign n5161 = ~ndn3_44 & ~preset & ndn3_42 & n_n7927; - assign n5162 = ~preset & n_n9313 & (ndn3_28 | ~nen3_28); - assign n5163 = ~preset & n4892 & (~n4954_1 ^ ~n4955); - assign n5164_1 = ~preset & n_n9522 & (ndn3_23 | nsr3_23); - assign n5165 = ~preset & n_n9488 & (nsr3_35 | ndn3_35); - assign n5166 = ~preset & n_n9237 & (~ndn3_42 | ndn3_44); - assign n5167 = ~preset & n_n9239 & (~ndn3_42 | ndn3_44); - assign n5168 = ~preset & n_n9452 & (~ndn3_39 | ndn3_40); - assign n5169_1 = ~preset & n_n9498 & (ndn3_13 | nsr3_13); - assign n5170 = ~preset & n_n8439 & (~ndn3_42 | ndn3_44); - assign n5171 = ~ndn3_44 & ndn3_42 & ~preset & n_n7757; - assign n5172 = ~preset & n_n8146 & (~ndn3_42 | ndn3_44); - assign n5173 = ~ndn3_44 & ndn3_42 & ~preset & n_n8024; - assign n5174_1 = ~preset & n_n9376 & (ngfdn_3 | ~ndn3_46); - assign n5175 = ndn3_46 & n_n8436 & ~preset & ~ngfdn_3; - assign n5176 = n4948 & (n5975 | (n4975 & n7176)); - assign n5177 = n4856 & n4947; - assign n5178 = ~preset & n_n7843 & (~ngfdn_3 | ndn3_50); - assign n5179_1 = ~ndn3_50 & ~preset & ngfdn_3 & n_n8256; - assign n5180 = ~ndn3_2 & ~preset & psv18_8_8_ & n4949_1; - assign n5181 = ~preset & n_n8966 & (ndn3_2 | ~n4949_1); - assign n5182 = ~preset & n_n7674 & (ndn3_46 | ~ndn3_44); - assign n5183 = n_n9237 & ndn3_44 & ~preset & ~ndn3_46; - assign n5184_1 = ~preset & n_n8727 & (ndn3_17 | ~ndn3_16); - assign n5185 = ~preset & n_n6910 & (ndn3_46 | ~ndn3_44); - assign n5186 = n_n9239 & ndn3_44 & ~preset & ~ndn3_46; - assign n5187 = ~preset & n_n9081 & (nsr3_38 | ndn3_38); - assign n5188 = ~ndn3_2 & ~preset & psv26_10_10_ & n4949_1; - assign n5189_1 = ~preset & n_n7688 & (ndn3_2 | ~n4949_1); - assign n5190 = ~preset & n_n9338 & (ndn3_25 | ~ndn3_22); - assign n5191 = ~preset & n_n9061 & (nsr3_38 | ndn3_38); - assign n5192 = ~preset & n_n7686 & (~nen3_16 | ndn3_16); - assign n5193 = ~preset & n4875 & (~n4976 ^ ~n4977); - assign n5194_1 = ~ndn3_2 & ~preset & psv33_12_12_ & n4949_1; - assign n5195 = ~preset & n_n8267 & (ndn3_2 | ~n4949_1); - assign n5196 = ~ndn3_2 & ~preset & psv39_10_10_ & n4949_1; - assign n5197 = ~preset & n_n8116 & (ndn3_2 | ~n4949_1); - assign n5198 = ~preset & n_n8296 & (~ndn3_9 | ndn3_11); - assign n5199_1 = ~preset & n4847 & (~n4971 ^ ~n4972); - assign n5200 = ~preset & n_n8344 & (ndn3_13 | nsr3_13); - assign n5201 = ~preset & n_n8326 & (ndn3_37 | nsr3_37); - assign n5202 = n4949_1 & ~ndn3_2 & pinp_0_0_ & ~preset; - assign n5203 = ~preset & n_n8011 & (ndn3_2 | ~n4949_1); - assign n5204_1 = ~preset & n_n8583 & (ndn3_17 | ~ndn3_16); - assign n5205 = n4946 & (n5975 | (n4975 & n7176)); - assign n5206 = n4856 & (n_n8993 ^ ~n5005); - assign n5207 = n4944_1 & (n5975 | (n4975 & n7176)); - assign n5208 = n4856 & n4945; - assign n5209_1 = ~preset & n_n8628 & (~ndn3_29 | ndn3_32); - assign n5210 = ~preset & n4880 & (~n4976 ^ ~n4977); - assign n5211 = ~ndn3_2 & ~preset & psv18_10_10_ & n4949_1; - assign n5212 = ~preset & n_n8586 & (ndn3_2 | ~n4949_1); - assign n5213 = ~preset & n_n9340 & (ndn3_23 | nsr3_23); - assign n5214_1 = ~ndn3_2 & ~preset & psv18_12_12_ & n4949_1; - assign n5215 = ~preset & n_n8408 & (ndn3_2 | ~n4949_1); - assign n5216 = ~ndn3_2 & ~preset & psv26_7_7_ & n4949_1; - assign n5217 = ~preset & n_n9603 & (ndn3_2 | ~n4949_1); - assign n5218 = ~preset & n_n7682 & (nsr3_35 | ndn3_35); - assign n5219_1 = ~ndn3_2 & ~preset & psv26_1_1_ & n4949_1; - assign n5220 = ~preset & n_n9322 & (ndn3_2 | ~n4949_1); - assign n5221 = ~ndn3_2 & ~preset & psv33_0_0_ & n4949_1; - assign n5222 = ~preset & n_n7511 & (ndn3_2 | ~n4949_1); - assign n5223 = ~preset & n_n7121 & (~ndn3_39 | ndn3_40); - assign n5224_1 = ~ndn3_40 & n_n7626 & ~preset & ndn3_39; - assign n5225 = ~preset & n_n8468 & (~ndn3_42 | ndn3_44); - assign n5226 = n4861 & (n4997 ^ (n6083 | n6084_1)); - assign n5227 = n4942 & (n5975 | (n4975 & n7176)); - assign n5228 = n4856 & (~n_n9031 ^ (n_n8993 | n5005)); - assign n5229_1 = ~preset & n_n9424 & (~ndn3_39 | ndn3_40); - assign n5230 = ~ndn3_40 & ~preset & ndn3_39 & n_n7346; - assign n5231 = ~preset & n_n9404 & (ndn3_7 | ~ndn3_4); - assign n5232 = ~preset & n_n9402 & (nsr3_13 | ndn3_15); - assign n5233 = ~preset & n_n8361 & (~ndn3_39 | ndn3_40); - assign n5234_1 = ~ndn3_40 & ndn3_39 & ~preset & n_n9611; - assign n5235 = ~preset & n_n7366 & (~ndn3_39 | ndn3_40); - assign n5236 = ~ndn3_40 & ndn3_39 & ~preset & n_n9613; - assign n5237 = ~preset & n_n9344 & (nsr3_14 | ndn3_14); - assign n5238 = ~preset & n_n7083 & (ndn3_46 | ~ndn3_44); - assign n5239_1 = ~preset & n_n8188 & (~ndn3_42 | ndn3_44); - assign n5240 = n4861 & (n5004_1 ^ (n6527 | n6528)); - assign n5241 = ~preset & n_n9178 & (nsr3_14 | ndn3_14); - assign n5242 = ~preset & n_n8644 & (~ndn3_39 | ndn3_40); - assign n5243 = ~ndn3_40 & ndn3_39 & ~preset & n_n8543; - assign n5244_1 = ~preset & n_n8670 & (~ndn3_42 | ndn3_44); - assign n5245 = ~ndn3_2 & ~preset & psv33_3_3_ & n4949_1; - assign n5246 = ~preset & n_n9136 & (ndn3_2 | ~n4949_1); - assign n5247 = ~preset & n_n9390 & (ndn3_34 | ~nen3_34); - assign n5248 = ~preset & n_n8789 & (ndn3_4 | ~ndn3_2); - assign n5249_1 = ~preset & n_n9046 & (ndn3_27 | ~ndn3_26); - assign n5250 = ~preset & n4859_1 & (~n4954_1 ^ ~n4955); - assign n5251 = ~preset & n_n8938 & (~ndn3_25 | ndn3_26); - assign n5252 = ~preset & n4851 & (~n4969_1 ^ ~n4970); - assign n5253 = ~preset & n_n7402 & (ndn3_46 | ~ndn3_44); - assign n5254_1 = ~ndn3_46 & ~preset & n_n9635 & ndn3_44; - assign n5255 = ~ndn3_2 & ~preset & psv26_13_13_ & n4949_1; - assign n5256 = ~preset & n_n9067 & (ndn3_2 | ~n4949_1); - assign n5257 = ~preset & n_n7715 & (~ndn3_42 | ndn3_44); - assign n5258 = ~ndn3_44 & ndn3_42 & ~preset & n_n9486; - assign n5259_1 = ~preset & n_n6980 & (~nen3_22 | ndn3_22); - assign n5260 = ~ndn3_22 & nen3_22 & ~preset & n_n9273; - assign n5261 = ~ndn3_2 & ~preset & psv38_6_6_ & n4949_1; - assign n5262 = ~preset & n_n8779 & (ndn3_2 | ~n4949_1); - assign n5263 = n4941 & (n5975 | (n4975 & n7176)); - assign n5264_1 = n4856 & n4940; - assign n5265 = ~preset & n_n8729 & (ndn3_17 | ~ndn3_16); - assign n5266 = ~preset & n4882 & (~n4971 ^ ~n4972); - assign n5267 = ~preset & n_n8916 & (ndn3_46 | ~ndn3_44); - assign n5268 = ndn3_44 & n_n8670 & ~preset & ~ndn3_46; - assign n5269_1 = ~ndn3_2 & ~preset & psv2_4_4_ & n4949_1; - assign n5270 = ~preset & n_n7827 & (ndn3_2 | ~n4949_1); - assign n5271 = ~ndn3_2 & ~preset & psv13_10_10_ & n4949_1; - assign n5272 = ~preset & n_n9119 & (ndn3_2 | ~n4949_1); - assign n5273 = ~ndn3_2 & ~preset & psv2_2_2_ & n4949_1; - assign n5274_1 = ~preset & n_n7744 & (ndn3_2 | ~n4949_1); - assign n5275 = ~preset & n_n8909 & (nsr3_14 | ndn3_14); - assign n5276 = ~ndn3_2 & ~preset & psv13_0_0_ & n4949_1; - assign n5277 = ~preset & n_n8619 & (ndn3_2 | ~n4949_1); - assign n5278 = ~preset & n_n8535 & (nsr3_14 | ndn3_14); - assign n5279_1 = ~preset & n_n9255 & (~ndn3_19 | ndn3_21); - assign n5280 = ~preset & n4885 & (~n4976 ^ ~n4977); - assign n5281 = ~preset & n_n7969 & (nsr3_14 | ndn3_14); - assign n5282 = ~preset & n_n9493 & (~nen3_22 | ndn3_22); - assign n5283 = ~preset & n_n8657 & (nsr3_20 | ndn3_20); - assign n5284_1 = ~preset & n_n8636 & (ndn3_37 | nsr3_37); - assign n5285 = ~preset & n_n8477 & (ndn3_37 | nsr3_37); - assign n5286 = ~ndn3_2 & ~preset & psv2_13_13_ & n4949_1; - assign n5287 = ~preset & n_n7890 & (ndn3_2 | ~n4949_1); - assign n5288 = n4939_1 & (n5975 | (n4975 & n7176)); - assign n5289_1 = n4856 & (~n_n8603 ^ ~n_n8798); - assign n5290 = ~ndn3_2 & ~preset & psv38_10_10_ & n4949_1; - assign n5291 = ~preset & n_n7665 & (ndn3_2 | ~n4949_1); - assign n5292 = n7208 & n4856 & n5001; - assign n5293 = ~n5001 & ~preset & n_n9353; - assign n5294_1 = ~preset & n_n9139 & (ndn3_19 | ~nen3_19); - assign n5295 = ~preset & n4865 & (~n4969_1 ^ ~n4970); - assign n5296 = ~preset & n_n8839 & (ndn3_28 | ~nen3_28); - assign n5297 = ~preset & n_n8185 & (~nen3_22 | ndn3_22); - assign n5298 = ~ndn3_22 & n_n9304 & ~preset & nen3_22; - assign n5299_1 = ~preset & n_n9155 & (~ndn3_39 | ndn3_40); - assign n5300 = ~preset & n_n9508 & (ngfdn_3 | ~ndn3_46); - assign n5301 = n1270 & (n4980 ^ (n6352 | n6353)); - assign n5302 = ~preset & n_n9126 & (~ndn3_29 | ndn3_32); - assign n5303 = ~preset & n_n9629 & (ndn3_46 | ~ndn3_44); - assign n5304_1 = n4853 & (n4997 ^ (n6083 | n6084_1)); - assign n5305 = ~preset & n_n9317 & (~nen3_16 | ndn3_16); - assign n5306 = ~preset & n4875 & (~n4954_1 ^ ~n4955); - assign n5307 = ~preset & n_n9600 & (nsr3_13 | ndn3_15); - assign n5308 = ~preset & n4881 & (~n4969_1 ^ ~n4970); - assign n5309_1 = n7207 & ((n4922 & n4935) | (n_n9537 & (n4922 | n4935))); - assign n5310 = ~n_n8821 & n4857 & (~n4934_1 ^ ~n4937); - assign n5311 = ~n4937 & ~n4934_1 & n_n8821 & n4856; - assign n5312 = ~n5001 & ~preset & n_n8821; - assign n5313 = ~preset & n_n7074 & (~ndn3_42 | ndn3_44); - assign n5314_1 = ~ndn3_44 & ndn3_42 & ~preset & n_n9355; - assign n5315 = ~preset & n_n8249 & (ndn3_42 | ~ndn3_40); - assign n5316 = ~ndn3_2 & ~preset & psv26_4_4_ & n4949_1; - assign n5317 = ~preset & n_n8617 & (ndn3_2 | ~n4949_1); - assign n5318 = ~preset & n_n7069 & (~ngfdn_3 | ndn3_50); - assign n5319_1 = ~ndn3_50 & n_n7324 & ~preset & ngfdn_3; - assign n5320 = ~ndn3_2 & ~preset & psv33_1_1_ & n4949_1; - assign n5321 = ~preset & n_n9053 & (ndn3_2 | ~n4949_1); - assign n5322 = ~preset & n_n9129 & (ndn3_27 | ~ndn3_26); - assign n5323 = ~preset & n_n9320 & (ndn3_13 | nsr3_13); - assign n5324_1 = ~ndn3_2 & ~preset & psv13_15_15_ & n4949_1; - assign n5325 = ~preset & n_n8502 & (ndn3_2 | ~n4949_1); - assign n5326 = ~ndn3_2 & ~preset & psv18_6_6_ & n4949_1; - assign n5327 = ~preset & n_n9230 & (ndn3_2 | ~n4949_1); - assign n5328 = ~ndn3_2 & ~preset & psv38_4_4_ & n4949_1; - assign n5329_1 = ~preset & n_n7600 & (ndn3_2 | ~n4949_1); - assign n5330 = ~preset & n_n8221 & (nsr3_14 | ndn3_14); - assign n5331 = ~preset & n_n9595 & (ndn3_25 | ~ndn3_22); - assign n5332 = ~preset & n4889_1 & (~n4969_1 ^ ~n4970); - assign n5333 = ~preset & n_n7642 & (~ndn3_9 | ndn3_11); - assign n5334_1 = n4949_1 & ~ndn3_2 & pinp_8_8_ & ~preset; - assign n5335 = ~preset & n_n7697 & (ndn3_2 | ~n4949_1); - assign n5336 = ~preset & n_n7108 & (~ndn3_39 | ndn3_40); - assign n5337 = ~ndn3_40 & ndn3_39 & ~preset & n_n8794; - assign n5338 = ~preset & n_n7810 & (~nen3_16 | ndn3_16); - assign n5339_1 = ~preset & n_n7781 & (ngfdn_3 | ~ndn3_46); - assign n5340 = n1270 & (n4987 ^ (n6433 | n6434)); - assign n5341 = ~preset & n_n7606 & (ngfdn_3 | ~ndn3_46); - assign n5342 = ~preset & n_n9460 & (~ndn3_19 | ndn3_21); - assign n5343 = ~preset & n4885 & (~n4985 ^ ~n4986); - assign n5344_1 = ~preset & n_n8473 & (ndn3_25 | ~ndn3_22); - assign n5345 = ~preset & n_n8224 & (ndn3_29 | ~ndn3_28); - assign n5346 = ~ndn3_2 & ~preset & psv39_2_2_ & n4949_1; - assign n5347 = ~preset & n_n7837 & (ndn3_2 | ~n4949_1); - assign n5348 = ~preset & n_n8581 & (~ndn3_25 | ndn3_26); - assign n5349_1 = ~preset & n_n8213 & (~ndn3_19 | ndn3_21); - assign n5350 = ~preset & n4885 & (~n4969_1 ^ ~n4970); - assign n5351 = ~preset & n_n9092 & (ndn3_30 | nsr3_30); - assign n5352 = ~preset & n_n8781 & (~nen3_22 | ndn3_22); - assign n5353 = ~ndn3_22 & ~preset & nen3_22 & n_n9255; - assign n5354_1 = ~preset & n_n7990 & (nsr3_35 | ndn3_35); - assign n5355 = ~preset & n_n8470 & (~ndn3_42 | ndn3_44); - assign n5356 = ~preset & n_n9394 & (ndn3_30 | nsr3_30); - assign n5357 = ~preset & n_n9355 & (ndn3_42 | ~ndn3_40); - assign n5358 = n4863 & (n4997 ^ (n6083 | n6084_1)); - assign n5359_1 = ~preset & n_n7739 & (~nen3_22 | ndn3_22); - assign n5360 = n7202 & (n_n8930 | ~n4967 | ~n7089); - assign n5361 = n7203 & n7089 & ~n_n8930 & n4967; - assign n5362 = ~preset & n_n7728 & (~nen3_22 | ndn3_22); - assign n5363 = ~preset & n_n8045 & (ndn3_42 | ~ndn3_40); - assign n5364_1 = n_n7136 & ndn3_40 & ~preset & ~ndn3_42; - assign n5365 = ~preset & n_n9128 & (~nen3_36 | ndn3_36); - assign n5366 = ~preset & n_n9159 & (ndn3_28 | ~nen3_28); - assign n5367 = ~preset & n_n9591 & (nsr3_35 | ndn3_35); - assign n5368 = ~preset & n_n9393 & (nsr3_35 | ndn3_35); - assign n5369_1 = ~preset & n_n8263 & (~ngfdn_3 | ndn3_50); - assign n5370 = ~ndn3_50 & n_n8081 & ~preset & ngfdn_3; - assign n5371 = ~preset & n_n7848 & (~ndn3_9 | ndn3_11); - assign n5372 = ~preset & n4847 & (~n4985 ^ ~n4986); - assign n5373 = ~preset & n_n7626 & (~nen3_39 | ndn3_39); - assign n5374_1 = ~preset & n4854_1 & (~n4971 ^ ~n4972); - assign n5375 = ~preset & n_n9421 & (ndn3_46 | ~ndn3_44); - assign n5376 = ~ndn3_46 & ~preset & n_n7691 & ndn3_44; - assign n5377 = ~preset & n_n7849 & (ndn3_9 | ~ndn3_7); - assign n5378 = ~preset & n4852 & (~n4985 ^ ~n4986); - assign n5379_1 = ~preset & n_n7873 & (nsr3_38 | ndn3_38); - assign n5380 = ~ndn3_2 & ~preset & psv33_14_14_ & n4949_1; - assign n5381 = ~preset & n_n7914 & (ndn3_2 | ~n4949_1); - assign n5382 = ~preset & n_n7668 & (ndn3_9 | ~ndn3_7); - assign n5383 = ~preset & n4852 & (~n4976 ^ ~n4977); - assign n5384_1 = ~preset & n_n7925 & (ndn3_30 | nsr3_30); - assign n5385 = ~preset & n_n8256 & (ngfdn_3 | ~ndn3_46); - assign n5386 = ~preset & n_n7711 & (ndn3_23 | nsr3_23); - assign n5387 = ~preset & n_n7971 & (ndn3_4 | ~ndn3_2); - assign n5388 = ~preset & n_n8064 & (nsr3_20 | ndn3_20); - assign n5389_1 = ~preset & n_n7932 & (~nen3_22 | ndn3_22); - assign n5390 = ~preset & n_n8233 & (nsr3_13 | ndn3_15); - assign n5391 = ~preset & n4881 & (~n4971 ^ ~n4972); - assign n5392 = ~preset & n_n8003 & (ndn3_25 | ~ndn3_22); - assign n5393 = n7201 & ((n4895 & n4921) | (n_n9416 & (n4895 | n4921))); - assign n5394_1 = ~n_n9537 & n4857 & (~n4922 ^ ~n4935); - assign n5395 = ~n4935 & ~n4922 & n_n9537 & n4856; - assign n5396 = ~n5001 & ~preset & n_n9537; - assign n5397 = n7200 & ((n4870 & n4871) | (n_n9638 & (n4870 | n4871))); - assign n5398 = ~n_n9448 & n4857 & (~n4872 ^ ~n4933); - assign n5399_1 = ~n4933 & ~n4872 & n_n9448 & n4856; - assign n5400 = ~n5001 & ~preset & n_n9448; - assign n5401 = ~preset & n_n9221 & (ndn3_46 | ~ndn3_44); - assign n5402 = ~preset & n_n9104 & (~ndn3_39 | ndn3_40); - assign n5403 = ~preset & n_n8277 & (~ndn3_29 | ndn3_32); - assign n5404_1 = ~preset & n4880 & (~n4985 ^ ~n4986); - assign n5405 = ~preset & n_n8743 & (ndn3_19 | ~nen3_19); - assign n5406 = ~preset & n4865 & (~n4954_1 ^ ~n4955); - assign n5407 = ~ndn3_2 & ~preset & psv33_2_2_ & n4949_1; - assign n5408 = ~preset & n_n7554 & (ndn3_2 | ~n4949_1); - assign n5409_1 = n7199 & ((n4914_1 & n4951) | (n_n8419 & (n4914_1 | n4951))); - assign n5410 = ~n_n8449 & n4857 & (~n4931 ^ ~n4932); - assign n5411 = ~n4932 & ~n4931 & n_n8449 & n4856; - assign n5412 = ~n5001 & ~preset & n_n8449; - assign n5413 = ~preset & n_n8384 & (~nen3_22 | ndn3_22); - assign n5414_1 = ~ndn3_22 & ~preset & nen3_22 & n_n8464; - assign n5415 = ~ndn3_2 & ~preset & psv38_3_3_ & n4949_1; - assign n5416 = ~preset & n_n9212 & (ndn3_2 | ~n4949_1); - assign n5417 = ~preset & n_n9050 & (~ndn3_9 | ndn3_11); - assign n5418 = ~preset & n4847 & (~n4954_1 ^ ~n4955); - assign n5419_1 = ~preset & n_n9570 & (ngfdn_3 | ~ndn3_46); - assign n5420 = n1270 & (n5004_1 ^ (n6527 | n6528)); - assign n5421 = ~preset & n_n9028 & (ngfdn_3 | ~ndn3_46); - assign n5422 = ~preset & n_n9626 & (ngfdn_3 | ~ndn3_46); - assign n5423 = ~ndn3_2 & ~preset & psv39_7_7_ & n4949_1; - assign n5424_1 = ~preset & n_n9605 & (ndn3_2 | ~n4949_1); - assign n5425 = ~preset & n_n6968 & (nsr3_35 | ndn3_35); - assign n5426 = ~preset & n_n7390 & (~ndn3_39 | ndn3_40); - assign n5427 = ~ndn3_40 & ~preset & ndn3_39 & n_n7334; - assign n5428 = ~ndn3_2 & ~preset & psv33_7_7_ & n4949_1; - assign n5429_1 = ~preset & n_n9270 & (ndn3_2 | ~n4949_1); - assign n5430 = ~preset & n_n7284 & (ndn3_46 | ~ndn3_44); - assign n5431 = ~ndn3_46 & ~preset & n_n7898 & ndn3_44; - assign n5432 = ~preset & n_n9403 & (ndn3_13 | nsr3_13); - assign n5433 = ~preset & n_n9308 & (ndn3_34 | ~nen3_34); - assign n5434_1 = ~preset & n4860 & (~n4954_1 ^ ~n4955); - assign n5435 = ~preset & n_n8584 & (~ndn3_11 | ndn3_12); - assign n5436 = ~ndn3_2 & ~preset & psv26_14_14_ & n4949_1; - assign n5437 = ~preset & n_n7946 & (ndn3_2 | ~n4949_1); - assign n5438 = ~preset & n_n7420 & (~ngfdn_3 | ndn3_50); - assign n5439_1 = ~ndn3_50 & ngfdn_3 & ~preset & n_n7558; - assign n5440 = ~ndn3_2 & ~preset & psv18_2_2_ & n4949_1; - assign n5441 = ~preset & n_n7737 & (ndn3_2 | ~n4949_1); - assign n5442 = ~ndn3_2 & ~preset & psv39_11_11_ & n4949_1; - assign n5443 = ~preset & n_n8506 & (ndn3_2 | ~n4949_1); - assign n5444_1 = ~preset & n_n7598 & (~ndn3_29 | ndn3_32); - assign n5445 = ~preset & n4880 & (~n4971 ^ ~n4972); - assign n5446 = ~preset & n_n8328 & (ndn3_37 | nsr3_37); - assign n5447 = n4929_1 & (n5975 | (n4975 & n7176)); - assign n5448 = n4856 & n4928; - assign n5449_1 = ~preset & n_n9205 & (~ndn3_25 | ndn3_26); - assign n5450 = ~preset & n_n8004 & (~nen3_22 | ndn3_22); - assign n5451 = n4866 & (n4997 ^ (n6083 | n6084_1)); - assign n5452 = ~preset & n_n8061 & (ndn3_42 | ~ndn3_40); - assign n5453 = ~ndn3_42 & ~preset & n_n9104 & ndn3_40; - assign n5454_1 = ~ndn3_2 & ~preset & psv39_6_6_ & n4949_1; - assign n5455 = ~preset & n_n9121 & (ndn3_2 | ~n4949_1); - assign n5456 = ~preset & n_n8436 & (ndn3_46 | ~ndn3_44); - assign n5457 = n4853 & (n4987 ^ (n6433 | n6434)); - assign n5458 = ~preset & n_n9309 & (ndn3_42 | ~ndn3_40); - assign n5459_1 = ~preset & n_n9259 & (~ndn3_42 | ndn3_44); - assign n5460 = ~preset & n_n7476 & (~nsr1_2 | nlc1_2); - assign n5461 = ~nlc1_2 & nsr1_2 & ~preset_0_0_ & ~preset; - assign n5462 = ~ndn3_2 & ~preset & psv26_9_9_ & n4949_1; - assign n5463 = ~preset & n_n7424 & (ndn3_2 | ~n4949_1); - assign n5464_1 = ~ndn3_2 & ~preset & psv33_4_4_ & n4949_1; - assign n5465 = ~preset & n_n7604 & (ndn3_2 | ~n4949_1); - assign n5466 = ~preset & n_n7649 & (ndn3_27 | ~ndn3_26); - assign n5467 = ~preset & n_n7976 & (ngfdn_3 | ~ndn3_46); - assign n5468 = ndn3_46 & n_n8765 & ~preset & ~ngfdn_3; - assign n5469_1 = ~preset & n_n8898 & (ndn3_34 | ~nen3_34); - assign n5470 = ~preset & n4860 & (~n4971 ^ ~n4972); - assign n5471 = ~preset & n_n8222 & (ndn3_34 | ~nen3_34); - assign n5472 = ~preset & n_n7964 & (ndn3_46 | ~ndn3_44); - assign n5473 = ~ndn3_46 & ~preset & n_n9041 & ndn3_44; - assign n5474_1 = ~preset & n_n7706 & (~ndn3_42 | ndn3_44); - assign n5475 = ~preset & n_n9318 & (~ndn3_11 | ndn3_12); - assign n5476 = ~preset & n4849_1 & (~n4954_1 ^ ~n4955); - assign n5477 = n4949_1 & ~ndn3_2 & pinp_7_7_ & ~preset; - assign n5478 = ~preset & n_n9271 & (ndn3_2 | ~n4949_1); - assign n5479_1 = ~preset & n_n9042 & (~ndn3_29 | ndn3_32); - assign n5480 = ~preset & n4880 & (~n4954_1 ^ ~n4955); - assign n5481 = n4926 & (n5975 | (n4975 & n7176)); - assign n5482 = n4856 & n4927; - assign n5483 = n4925 & (n5975 | (n4975 & n7176)); - assign n5484_1 = n4856 & ((n_n8923 & (~n_n8603 | n_n8798)) | (n_n8603 & ~n_n8923 & ~n_n8798)); - assign n5485 = n_n9248 & (~n_n9247 | ~n4902) & n7198; - assign n5486 = ~n4902 & n_n9247 & ~preset & n_n9248; - assign n5487 = ~preset & n_n9252 & (~ndn3_19 | ndn3_21); - assign n5488 = ~preset & n4885 & (~n4971 ^ ~n4972); - assign n5489_1 = ~preset & n_n9576 & (~ndn3_39 | ndn3_40); - assign n5490 = ~preset & n_n6920 & (ndn3_46 | ~ndn3_44); - assign n5491 = ndn3_44 & n_n8470 & ~preset & ~ndn3_46; - assign n5492 = ~ndn3_2 & ~preset & psv38_8_8_ & n4949_1; - assign n5493 = ~preset & n_n7692 & (ndn3_2 | ~n4949_1); - assign n5494_1 = ~ndn3_2 & ~preset & psv2_8_8_ & n4949_1; - assign n5495 = ~preset & n_n9023 & (ndn3_2 | ~n4949_1); - assign n5496 = ~preset & n_n9059 & (nsr3_38 | ndn3_38); - assign n5497 = ~preset & n_n7809 & (~nen3_22 | ndn3_22); - assign n5498 = n4866 & (n4980 ^ (n6352 | n6353)); - assign n5499_1 = ~preset & n_n8889 & (ndn3_28 | ~nen3_28); - assign n5500 = ~preset & n4892 & (~n4976 ^ ~n4977); - assign n5501 = ~preset & n_n8253 & (~nen3_36 | ndn3_36); - assign n5502 = ~preset & n4876 & (~n4971 ^ ~n4972); - assign n5503 = ~preset & n_n7845 & (ndn3_27 | ~ndn3_26); - assign n5504_1 = ~preset & n4859_1 & (~n4985 ^ ~n4986); - assign n5505 = ~preset & n_n8989 & (ndn3_42 | ~ndn3_40); - assign n5506 = n4863 & (n4987 ^ (n6433 | n6434)); - assign n5507 = ~preset & n_n8223 & (~ndn3_29 | ndn3_32); - assign n5508 = ~preset & n_n9171 & (~ndn3_42 | ndn3_44); - assign n5509_1 = ~preset & n_n7879 & (ndn3_13 | nsr3_13); - assign n5510 = ~preset & n_n9186 & (ndn3_13 | nsr3_13); - assign n5511 = ~preset & n_n7885 & (nsr3_38 | ndn3_38); - assign n5512 = ~preset & n_n7966 & (ndn3_37 | nsr3_37); - assign n5513 = ~preset & n_n8081 & (ngfdn_3 | ~ndn3_46); - assign n5514_1 = n1270 & (n4997 ^ (n6083 | n6084_1)); - assign n5515 = ~preset & n_n9219 & (ngfdn_3 | ~ndn3_46); - assign n5516 = ~preset & n_n9043 & (ndn3_37 | nsr3_37); - assign n5517 = n4923 & (n5975 | (n4975 & n7176)); - assign n5518 = n4856 & (n_n8933 ^ ~n5000); - assign n5519_1 = ~preset & n_n8100 & (~ndn3_39 | ndn3_40); - assign n5520 = ~ndn3_40 & ndn3_39 & ~preset & n_n8871; - assign n5521 = ~preset & n_n9266 & (nsr3_14 | ndn3_14); - assign n5522 = ~preset & n_n7429 & (ndn3_19 | ~nen3_19); - assign n5523 = ~preset & n4865 & (~n4971 ^ ~n4972); - assign n5524_1 = ~preset & n_n8791 & (ndn3_4 | ~ndn3_2); - assign n5525 = ~preset & n4874_1 & (~n4971 ^ ~n4972); - assign n5526 = ~preset & n_n7624 & (~nen3_39 | ndn3_39); - assign n5527 = ~preset & n_n9535 & (~ndn3_42 | ndn3_44); - assign n5528 = ~ndn3_44 & ndn3_42 & ~preset & n_n9309; - assign n5529_1 = ~preset & n_n8396 & (ndn3_13 | nsr3_13); - assign n5530 = ~preset & n_n7813 & (ndn3_7 | ~ndn3_4); - assign n5531 = ~ndn3_2 & ~preset & psv38_0_0_ & n4949_1; - assign n5532 = ~preset & n_n7509 & (ndn3_2 | ~n4949_1); - assign n5533 = ~preset & n_n7980 & (ndn3_30 | nsr3_30); - assign n5534_1 = ~preset & n_n7667 & (ndn3_23 | nsr3_23); - assign n5535 = ~preset & n_n7761 & (nsr3_20 | ndn3_20); - assign n5536 = ~preset & n_n7683 & (ndn3_25 | ~ndn3_22); - assign n5537 = ~preset & n4889_1 & (~n4976 ^ ~n4977); - assign n5538 = ~preset & n_n8177 & (ndn3_29 | ~ndn3_28); - assign n5539_1 = ~preset & n4869_1 & (~n4976 ^ ~n4977); - assign n5540 = ~preset & n_n7793 & (ndn3_4 | ~ndn3_2); - assign n5541 = ~ndn3_2 & ~preset & psv2_12_12_ & n4949_1; - assign n5542 = ~preset & n_n7817 & (ndn3_2 | ~n4949_1); - assign n5543 = ~preset & n_n7225 & (nsr3_20 | ndn3_20); - assign n5544_1 = ~preset & n_n7808 & (ndn3_30 | nsr3_30); - assign n5545 = ~preset & n_n6963 & (ndn3_42 | ~ndn3_40); - assign n5546 = ~ndn3_42 & ~preset & n_n9155 & ndn3_40; - assign n5547 = ~preset & n_n7392 & (~nen3_22 | ndn3_22); - assign n5548 = ~ndn3_22 & ~preset & nen3_22 & n_n9586; - assign n5549_1 = ~ndn3_2 & ~preset & psv33_8_8_ & n4949_1; - assign n5550 = ~preset & n_n9302 & (ndn3_2 | ~n4949_1); - assign n5551 = ~preset & n_n9458 & (ndn3_34 | ~nen3_34); - assign n5552 = ~preset & n_n8801 & (~ndn3_42 | ndn3_44); - assign n5553 = ~ndn3_44 & ndn3_42 & ~preset & n_n8247; - assign n5554_1 = ~ndn3_2 & ~preset & psv18_3_3_ & n4949_1; - assign n5555 = ~preset & n_n9396 & (ndn3_2 | ~n4949_1); - assign n5556 = ~preset & n_n7231 & (~nen3_22 | ndn3_22); - assign n5557 = ~ndn3_22 & ~preset & nen3_22 & n_n8093; - assign n5558 = ~preset & n_n9312 & (ndn3_30 | nsr3_30); - assign n5559_1 = ~preset & n_n8856 & (~nen3_22 | ndn3_22); - assign n5560 = n4866 & (n5004_1 ^ (n6527 | n6528)); - assign n5561 = ~n5975 & n7196 & (~n4975 | ~n7176); - assign n5562 = ~n6866 & ~n6865 & n_n8603 & ~n4856; - assign n5563 = n7192 & ((n4893 & n4894_1) | (n_n9434 & (n4893 | n4894_1))); - assign n5564_1 = ~n_n9416 & n4857 & (~n4895 ^ ~n4921); - assign n5565 = ~n4921 & ~n4895 & n_n9416 & n4856; - assign n5566 = ~n5001 & ~preset & n_n9416; - assign n5567 = ~ndn3_2 & ~preset & psv39_1_1_ & n4949_1; - assign n5568 = ~preset & n_n9324 & (ndn3_2 | ~n4949_1); - assign n5569_1 = ~ndn3_2 & ~preset & psv33_5_5_ & n4949_1; - assign n5570 = ~preset & n_n9182 & (ndn3_2 | ~n4949_1); - assign n5571 = ~preset & n_n9278 & (~ngfdn_3 | ndn3_50); - assign n5572 = ~ndn3_50 & ~preset & ngfdn_3 & n_n7781; - assign n5573 = ~preset & n_n8014 & (ndn3_9 | ~ndn3_7); - assign n5574_1 = ~preset & n_n8961 & (ndn3_9 | ~ndn3_7); - assign n5575 = ~ndn3_2 & ~preset & psv13_6_6_ & n4949_1; - assign n5576 = ~preset & n_n7880 & (ndn3_2 | ~n4949_1); - assign n5577 = ~ndn3_2 & ~preset & psv13_11_11_ & n4949_1; - assign n5578 = ~preset & n_n7766 & (ndn3_2 | ~n4949_1); - assign n5579_1 = ~preset & n_n7687 & (nsr3_13 | ndn3_15); - assign n5580 = ~preset & n4881 & (~n4976 ^ ~n4977); - assign n5581 = ~preset & n_n7685 & (nsr3_20 | ndn3_20); - assign n5582 = ~preset & n_n8281 & (ndn3_17 | ~ndn3_16); - assign n5583 = ~preset & n4882 & (~n4985 ^ ~n4986); - assign n5584_1 = n4949_1 & ~ndn3_2 & pinp_2_2_ & ~preset; - assign n5585 = ~preset & n_n8009 & (ndn3_2 | ~n4949_1); - assign n5586 = ~preset & n_n7825 & (ndn3_7 | ~ndn3_4); - assign n5587 = ~preset & n4879_1 & (~n4971 ^ ~n4972); - assign n5588 = ~preset & n_n7878 & (nsr3_13 | ndn3_15); - assign n5589_1 = ~preset & n_n7395 & (ndn3_42 | ~ndn3_40); - assign n5590 = n_n8206 & ndn3_40 & ~preset & ~ndn3_42; - assign n5591 = ~preset & n_n9327 & (ndn3_28 | ~nen3_28); - assign n5592 = ~preset & n_n9176 & (ndn3_23 | nsr3_23); - assign n5593 = ~preset & n_n7756 & (~ndn3_19 | ndn3_21); - assign n5594_1 = ~preset & n_n8464 & (~ndn3_19 | ndn3_21); - assign n5595 = ~preset & n_n7734 & (nsr3_35 | ndn3_35); - assign n5596 = ~ndn3_2 & ~preset & psv26_5_5_ & n4949_1; - assign n5597 = ~preset & n_n9500 & (ndn3_2 | ~n4949_1); - assign n5598 = ~preset & n_n7650 & (nsr3_35 | ndn3_35); - assign n5599_1 = ~preset & n_n7807 & (nsr3_35 | ndn3_35); - assign n5600 = ~preset & n_n8794 & (~nen3_39 | ndn3_39); - assign n5601 = ~preset & n_n7360 & (~nen3_22 | ndn3_22); - assign n5602 = ~ndn3_22 & ~preset & nen3_22 & n_n7756; - assign n5603 = ~preset & n_n8984 & (~ndn3_11 | ndn3_12); - assign n5604_1 = ~preset & n_n9599 & (~ndn3_11 | ndn3_12); - assign n5605 = ~preset & n4849_1 & (~n4969_1 ^ ~n4970); - assign n5606 = ~ndn3_2 & ~preset & psv13_9_9_ & n4949_1; - assign n5607 = ~preset & n_n7866 & (ndn3_2 | ~n4949_1); - assign n5608 = ~preset & n_n8486 & (~ngfdn_3 | ndn3_50); - assign n5609_1 = ~ndn3_50 & ~preset & ngfdn_3 & n_n9626; - assign n5610 = ~ndn3_2 & ~preset & psv18_1_1_ & n4949_1; - assign n5611 = ~preset & n_n9314 & (ndn3_2 | ~n4949_1); - assign n5612 = ~preset & n_n8073 & (~ndn3_39 | ndn3_40); - assign n5613 = ~ndn3_40 & n_n7624 & ~preset & ndn3_39; - assign n5614_1 = ~preset & n_n7896 & (ndn3_46 | ~ndn3_44); - assign n5615 = n4949_1 & ~ndn3_2 & pinp_9_9_ & ~preset; - assign n5616 = ~preset & n_n9349 & (ndn3_2 | ~n4949_1); - assign n5617 = ~ndn3_2 & ~preset & psv13_1_1_ & n4949_1; - assign n5618 = ~preset & n_n9323 & (ndn3_2 | ~n4949_1); - assign n5619_1 = ~ndn3_2 & ~preset & pinp_5_5_ & n4949_1; - assign n5620 = ~preset & n_n9183 & (ndn3_2 | ~n4949_1); - assign n5621 = ~preset & n_n8854 & (~nen3_22 | ndn3_22); - assign n5622 = n4949_1 & ~ndn3_2 & pinp_3_3_ & ~preset; - assign n5623 = ~preset & n_n9137 & (ndn3_2 | ~n4949_1); - assign n5624_1 = ~preset & n_n9319 & (nsr3_13 | ndn3_15); - assign n5625 = ~preset & n4881 & (~n4954_1 ^ ~n4955); - assign n5626 = n7187 & ((n4912 & n4938) | (n_n9353 & (n4912 | n4938))); - assign n5627 = ~preset & n_n9395 & (ndn3_28 | ~nen3_28); - assign n5628 = ~preset & n_n7923 & (~ngfdn_3 | ndn3_50); - assign n5629_1 = ~ndn3_50 & ngfdn_3 & ~preset & n_n7779; - assign n5630 = ~preset & n_n8833 & (ndn3_13 | nsr3_13); - assign n5631 = ~preset & n_n8276 & (~ndn3_9 | ndn3_11); - assign n5632 = ~preset & n4847 & (~n4976 ^ ~n4977); - assign n5633 = ~preset & n_n7514 & (ndn3_46 | ~ndn3_44); - assign n5634_1 = ndn3_44 & n_n8188 & ~preset & ~ndn3_46; - assign n5635 = ~ndn3_2 & ~preset & psv33_15_15_ & n4949_1; - assign n5636 = ~preset & n_n8456 & (ndn3_2 | ~n4949_1); - assign n5637 = ~ndn3_2 & ~preset & psv39_13_13_ & n4949_1; - assign n5638 = ~preset & n_n8504 & (ndn3_2 | ~n4949_1); - assign n5639_1 = ~preset & n_n7950 & (ndn3_30 | nsr3_30); - assign n5640 = ~preset & n_n9315 & (ndn3_25 | ~ndn3_22); - assign n5641 = ~preset & n4889_1 & (~n4954_1 ^ ~n4955); - assign n5642 = ~preset & n_n8402 & (~ndn3_17 | ndn3_18); - assign n5643 = ~preset & n_n7684 & (~nen3_22 | ndn3_22); - assign n5644_1 = ~preset & n_n8552 & (~nen3_36 | ndn3_36); - assign n5645 = ~ndn3_2 & ~preset & psv39_4_4_ & n4949_1; - assign n5646 = ~preset & n_n7835 & (ndn3_2 | ~n4949_1); - assign n5647 = ~ndn3_2 & ~preset & psv2_10_10_ & n4949_1; - assign n5648 = ~preset & n_n7689 & (ndn3_2 | ~n4949_1); - assign n5649_1 = ~preset & n_n9494 & (nsr3_20 | ndn3_20); - assign n5650 = ~preset & n_n8982 & (ndn3_19 | ~nen3_19); - assign n5651 = ~preset & n_n8095 & (nsr3_35 | ndn3_35); - assign n5652 = ~preset & n_n8900 & (ndn3_30 | nsr3_30); - assign n5653 = ~preset & n_n8210 & (nsr3_14 | ndn3_14); - assign n5654_1 = ~preset & n_n8626 & (ndn3_34 | ~nen3_34); - assign n5655 = ~preset & n4860 & (~n4985 ^ ~n4986); - assign n5656 = ~preset & n_n7988 & (nsr3_35 | ndn3_35); - assign n5657 = ~preset & n_n8906 & (~nen3_39 | ndn3_39); - assign n5658 = ~preset & n4854_1 & (~n4969_1 ^ ~n4970); - assign n5659_1 = ~preset & n_n9268 & (ndn3_9 | ~ndn3_7); - assign n5660 = ~preset & n4852 & (~n4969_1 ^ ~n4970); - assign n5661 = ~preset & n_n8983 & (ndn3_17 | ~ndn3_16); - assign n5662 = ~preset & n_n7256 & (ndn3_46 | ~ndn3_44); - assign n5663 = ~ndn3_46 & ~preset & n_n9171 & ndn3_44; - assign n5664_1 = ~preset & n_n8939 & (ndn3_17 | ~ndn3_16); - assign n5665 = ~preset & n4882 & (~n4969_1 ^ ~n4970); - assign n5666 = ~ndn3_2 & ~preset & psv2_9_9_ & n4949_1; - assign n5667 = ~preset & n_n8739 & (ndn3_2 | ~n4949_1); - assign n5668 = ~preset & n_n9366 & (~ndn3_39 | ndn3_40); - assign n5669_1 = ~ndn3_40 & n_n7464 & ~preset & ndn3_39; - assign n5670 = ~preset & n_n9310 & (nsr3_38 | ndn3_38); - assign n5671 = ~preset & n_n7570 & (ndn3_46 | ~ndn3_44); - assign n5672 = n4853 & (n4980 ^ (n6352 | n6353)); - assign n5673 = ~preset & n_n9470 & (~ndn3_29 | ndn3_32); - assign n5674_1 = ~preset & n4880 & (~n4969_1 ^ ~n4970); - assign n5675 = ~preset & n_n9623 & (ndn3_42 | ~ndn3_40); - assign n5676 = ~preset & n_n9609 & (~ndn3_39 | ndn3_40); - assign n5677 = ~ndn3_2 & ~preset & psv2_1_1_ & n4949_1; - assign n5678 = ~preset & n_n9325 & (ndn3_2 | ~n4949_1); - assign n5679_1 = ~preset & n_n9342 & (~nen3_16 | ndn3_16); - assign n5680 = n4949_1 & ~ndn3_2 & pinp_1_1_ & ~preset; - assign n5681 = ~preset & n_n9054 & (ndn3_2 | ~n4949_1); - assign n5682 = ~preset & n_n7822 & (~nen3_22 | ndn3_22); - assign n5683 = ~ndn3_2 & ~preset & psv39_5_5_ & n4949_1; - assign n5684_1 = ~preset & n_n9502 & (ndn3_2 | ~n4949_1); - assign n5685 = ~preset & n_n8741 & (ndn3_29 | ~ndn3_28); - assign n5686 = ~preset & n4869_1 & (~n4954_1 ^ ~n4955); - assign n5687 = ~preset & n_n9371 & (~ndn3_39 | ndn3_40); - assign n5688 = ~ndn3_40 & ndn3_39 & ~preset & n_n8611; - assign n5689_1 = ~preset & n_n8980 & (ndn3_34 | ~nen3_34); - assign n5690 = ~ndn3_2 & ~preset & psv26_2_2_ & n4949_1; - assign n5691 = ~preset & n_n7743 & (ndn3_2 | ~n4949_1); - assign n5692 = ~preset & n_n9429 & (~ngfdn_3 | ndn3_50); - assign n5693 = ~ndn3_50 & n_n7217 & ~preset & ngfdn_3; - assign n5694_1 = ~preset & n_n6961 & (~ndn3_42 | ndn3_44); - assign n5695 = ~ndn3_44 & ndn3_42 & ~preset & n_n8989; - assign n5696 = ~preset & n_n8809 & (~ndn3_25 | ndn3_26); - assign n5697 = ~preset & n_n8340 & (ndn3_46 | ~ndn3_44); - assign n5698 = ndn3_44 & n_n8468 & ~preset & ~ndn3_46; - assign n5699_1 = ~ndn3_2 & ~preset & psv39_14_14_ & n4949_1; - assign n5700 = ~preset & n_n7936 & (ndn3_2 | ~n4949_1); - assign n5701 = ~preset & n_n8430 & (~ndn3_39 | ndn3_40); - assign n5702 = ~ndn3_40 & ndn3_39 & ~preset & n_n9106; - assign n5703 = ~preset & n_n9596 & (~nen3_22 | ndn3_22); - assign n5704_1 = ~preset & n_n7876 & (~nen3_16 | ndn3_16); - assign n5705 = n4917 & (n5975 | (n4975 & n7176)); - assign n5706 = n4856 & (~n_n8911 ^ (n_n8933 | n5000)); - assign n5707 = ~preset & n_n7887 & (ndn3_25 | ~ndn3_22); - assign n5708 = ~preset & n4889_1 & (~n4985 ^ ~n4986); - assign n5709_1 = ~preset & n_n8760 & (ndn3_4 | ~ndn3_2); - assign n5710 = ~preset & n4874_1 & (~n4976 ^ ~n4977); - assign n5711 = ~preset & n_n9264 & (ndn3_23 | nsr3_23); - assign n5712 = ~ndn3_2 & ~preset & psv39_0_0_ & n4949_1; - assign n5713 = ~preset & n_n7657 & (ndn3_2 | ~n4949_1); - assign n5714_1 = ~preset & n_n9102 & (~ndn3_39 | ndn3_40); - assign n5715 = n4846 & (n4987 ^ (n6433 | n6434)); - assign n5716 = ~preset & n_n9316 & (nsr3_20 | ndn3_20); - assign n5717 = ~preset & n_n7929 & (ndn3_30 | nsr3_30); - assign n5718 = ~preset & n_n7962 & (~ndn3_39 | ndn3_40); - assign n5719_1 = n4846 & (n4996 ^ (n6545 | n6546)); - assign n5720 = ~ndn3_2 & ~preset & psv18_14_14_ & n4949_1; - assign n5721 = ~preset & n_n7930 & (ndn3_2 | ~n4949_1); - assign n5722 = ~preset & n_n8864 & (~ndn3_29 | ndn3_32); - assign n5723 = n7186 & ((n4872 & n4933) | (n_n9448 & (n4872 | n4933))); - assign n5724_1 = ~n_n8354 & n4857 & (~n4915 ^ ~n4916); - assign n5725 = ~n4916 & ~n4915 & n_n8354 & n4856; - assign n5726 = ~n5001 & ~preset & n_n8354; - assign n5727 = ~preset & n_n7789 & (~nen3_36 | ndn3_36); - assign n5728 = ~preset & n_n8543 & (~nen3_39 | ndn3_39); - assign n5729_1 = ~preset & n4854_1 & (~n4976 ^ ~n4977); - assign n5730 = ~preset & n_n8480 & (ndn3_37 | nsr3_37); - assign n5731 = ~preset & n_n9487 & (nsr3_38 | ndn3_38); - assign n5732 = ~preset & n_n7967 & (~nen3_36 | ndn3_36); - assign n5733 = ~preset & n_n8744 & (ndn3_17 | ~ndn3_16); - assign n5734_1 = ~preset & n4882 & (~n4954_1 ^ ~n4955); - assign n5735 = ~preset & n_n8022 & (ndn3_42 | ~ndn3_40); - assign n5736 = n4863 & (n4980 ^ (n6352 | n6353)); - assign n5737 = ~preset & n_n9592 & (ndn3_30 | nsr3_30); - assign n5738 = ~preset & n_n8808 & (ndn3_29 | ~ndn3_28); - assign n5739_1 = ~preset & n_n9044 & (~nen3_36 | ndn3_36); - assign n5740 = ~preset & n4876 & (~n4954_1 ^ ~n4955); - assign n5741 = ~ndn3_2 & ~preset & psv39_3_3_ & n4949_1; - assign n5742 = ~preset & n_n9407 & (ndn3_2 | ~n4949_1); - assign n5743 = ~preset & n_n9132 & (nsr3_14 | ndn3_14); - assign n5744_1 = ~preset & n_n9337 & (ndn3_27 | ~ndn3_26); - assign n5745 = ~preset & n_n8589 & (ngfdn_3 | ~ndn3_46); - assign n5746 = n_n9221 & ndn3_46 & ~preset & ~ngfdn_3; - assign n5747 = ~preset & n_n7603 & (~ndn3_17 | ndn3_18); - assign n5748 = ~preset & n4877 & (~n4971 ^ ~n4972); - assign n5749_1 = n4908 & (n5975 | (n4975 & n7176)); - assign n5750 = n4856 & ((~n_n8913 & ~n_n8964 & ~n4968) | (n_n8964 & (n_n8913 | n4968))); - assign n5751 = ~ndn3_2 & ~preset & psv38_2_2_ & n4949_1; - assign n5752 = ~preset & n_n8638 & (ndn3_2 | ~n4949_1); - assign n5753 = ~preset & n_n7017 & (~nen3_22 | ndn3_22); - assign n5754_1 = ~ndn3_22 & ~preset & nen3_22 & n_n9087; - assign n5755 = ~preset & n_n9397 & (ndn3_25 | ~ndn3_22); - assign n5756 = ~preset & n_n8519 & (nsr3_13 | ndn3_15); - assign n5757 = ~preset & n_n9368 & (~nen3_22 | ndn3_22); - assign n5758 = ~preset & n_n8750 & (ndn3_42 | ~ndn3_40); - assign n5759_1 = ~ndn3_42 & ~preset & n_n7962 & ndn3_40; - assign n5760 = ~preset & n_n7968 & (ndn3_23 | nsr3_23); - assign n5761 = n4949_1 & ~ndn3_2 & pinp_14_14_ & ~preset; - assign n5762 = ~preset & n_n8000 & (ndn3_2 | ~n4949_1); - assign n5763 = n4949_1 & ~ndn3_2 & pinp_11_11_ & ~preset; - assign n5764_1 = ~preset & n_n8986 & (ndn3_2 | ~n4949_1); - assign n5765 = ~preset & n_n7820 & (ndn3_28 | ~nen3_28); - assign n5766 = ~preset & n4892 & (~n4971 ^ ~n4972); - assign n5767 = ~preset & n_n9333 & (~ndn3_42 | ndn3_44); - assign n5768 = n4861 & (n4987 ^ (n6433 | n6434)); - assign n5769_1 = ~preset & n_n9047 & (ndn3_23 | nsr3_23); - assign n5770 = ~preset & n_n8810 & (ndn3_19 | ~nen3_19); - assign n5771 = ~preset & n_n8381 & (nsr3_14 | ndn3_14); - assign n5772 = ~preset & n_n9041 & (~ndn3_42 | ndn3_44); - assign n5773 = ~preset & n_n8093 & (~ndn3_19 | ndn3_21); - assign n5774_1 = ~preset & n4885 & (~n4954_1 ^ ~n4955); - assign n5775 = ~preset & n_n7102 & (ndn3_42 | ~ndn3_40); - assign n5776 = ~ndn3_42 & ~preset & n_n9609 & ndn3_40; - assign n5777 = n7180 & ((n4931 & n4932) | (n_n8449 & (n4931 | n4932))); - assign n5778 = ~n_n8549 & n4857 & (~n4905 ^ ~n4906); - assign n5779_1 = ~n4906 & ~n4905 & n_n8549 & n4856; - assign n5780 = ~n5001 & ~preset & n_n8549; - assign n5781 = ~preset & n_n7681 & (nsr3_38 | ndn3_38); - assign n5782 = ~preset & n_n9346 & (ndn3_9 | ~ndn3_7); - assign n5783 = ~ndn3_2 & ~preset & psv38_9_9_ & n4949_1; - assign n5784_1 = ~preset & n_n9336 & (ndn3_2 | ~n4949_1); - assign n5785 = ~preset & n_n9134 & (ndn3_9 | ~ndn3_7); - assign n5786 = ~ndn3_2 & ~preset & psv18_5_5_ & n4949_1; - assign n5787 = ~preset & n_n9491 & (ndn3_2 | ~n4949_1); - assign n5788 = ~preset & n_n9334 & (~ndn3_29 | ndn3_32); - assign n5789_1 = ~ndn3_2 & ~preset & psv38_1_1_ & n4949_1; - assign n5790 = ~preset & n_n9045 & (ndn3_2 | ~n4949_1); - assign n5791 = ~preset & n_n9282 & (ngfdn_3 | ~ndn3_46); - assign n5792 = ~preset & n_n8697 & (ndn3_23 | nsr3_23); - assign n5793 = ~preset & n_n7875 & (nsr3_20 | ndn3_20); - assign n5794_1 = ~preset & n_n9036 & (ndn3_42 | ~ndn3_40); - assign n5795 = ~preset & n_n7527 & (ndn3_46 | ~ndn3_44); - assign n5796 = ~preset & n_n7454 & (ndn3_19 | ~nen3_19); - assign n5797 = ~preset & n_n8369 & (~ngfdn_3 | ndn3_50); - assign n5798 = ~ndn3_50 & ~preset & ngfdn_3 & n_n9508; - assign n5799_1 = ~preset & n_n9263 & (ndn3_27 | ~ndn3_26); - assign n5800 = ~preset & n4859_1 & (~n4969_1 ^ ~n4970); - assign n5801 = ~preset & n_n8153 & (~ndn3_11 | ndn3_12); - assign n5802 = ~preset & n4849_1 & (~n4976 ^ ~n4977); - assign n5803 = ~preset & n_n9004 & (ngfdn_3 | ~ndn3_46); - assign n5804_1 = ndn3_46 & n_n8951 & ~preset & ~ngfdn_3; - assign n5805 = ~preset & n_n8049 & (~ndn3_42 | ndn3_44); - assign n5806 = ~ndn3_44 & ndn3_42 & ~preset & n_n9589; - assign n5807 = ~preset & n_n9148 & (~ngfdn_3 | ndn3_50); - assign n5808 = ~ndn3_50 & ~preset & ngfdn_3 & n_n7606; - assign n5809_1 = ~preset & n_n7498 & (~ndn3_42 | ndn3_44); - assign n5810 = ~ndn3_44 & ndn3_42 & ~preset & n_n9391; - assign n5811 = ~preset & n_n7824 & (~ndn3_11 | ndn3_12); - assign n5812 = ~preset & n4849_1 & (~n4971 ^ ~n4972); - assign n5813 = ~preset & n_n7777 & (~nen3_22 | ndn3_22); - assign n5814_1 = ~ndn3_22 & ~preset & nen3_22 & n_n9100; - assign n5815 = ~ndn3_2 & ~preset & psv13_4_4_ & n4949_1; - assign n5816 = ~preset & n_n7826 & (ndn3_2 | ~n4949_1); - assign n5817 = ~preset & n_n8777 & (~ndn3_39 | ndn3_40); - assign n5818 = ~ndn3_40 & ~preset & ndn3_39 & n_n8858; - assign n5819_1 = ~ndn3_2 & ~preset & psv33_10_10_ & n4949_1; - assign n5820 = ~preset & n_n9300 & (ndn3_2 | ~n4949_1); - assign n5821 = ~preset & n_n7847 & (~ndn3_17 | ndn3_18); - assign n5822 = ~preset & n4877 & (~n4985 ^ ~n4986); - assign n5823 = ~preset & n_n7760 & (~nen3_22 | ndn3_22); - assign n5824_1 = ~preset & n_n8466 & (ngfdn_3 | ~ndn3_46); - assign n5825 = ~preset & n_n7911 & (ndn3_23 | nsr3_23); - assign n5826 = ~preset & n_n8582 & (ndn3_19 | ~nen3_19); - assign n5827 = ~preset & n_n7790 & (ndn3_27 | ~ndn3_26); - assign n5828 = ~preset & n_n8279 & (~ndn3_25 | ndn3_26); - assign n5829_1 = ~preset & n4851 & (~n4985 ^ ~n4986); - assign n5830 = ~ndn3_2 & ~preset & psv2_11_11_ & n4949_1; - assign n5831 = ~preset & n_n9387 & (ndn3_2 | ~n4949_1); - assign n5832 = ~preset & n_n9589 & (ndn3_42 | ~ndn3_40); - assign n5833 = ~preset & n_n8951 & (ndn3_46 | ~ndn3_44); - assign n5834_1 = ~preset & n_n9573 & (ndn3_46 | ~ndn3_44); - assign n5835 = n4853 & (n4996 ^ (n6545 | n6546)); - assign n5836 = ~preset & n_n8659 & (nsr3_14 | ndn3_14); - assign n5837 = ~preset & n_n8681 & (ndn3_42 | ~ndn3_40); - assign n5838 = ~ndn3_42 & ~preset & n_n8996 & ndn3_40; - assign n5839_1 = ~preset & n_n8042 & (nsr3_14 | ndn3_14); - assign n5840 = ~preset & n_n8941 & (ndn3_29 | ~ndn3_28); - assign n5841 = ~ndn3_2 & ~preset & psv33_6_6_ & n4949_1; - assign n5842 = ~preset & n_n7643 & (ndn3_2 | ~n4949_1); - assign n5843 = ~preset & n_n7775 & (ngfdn_3 | ~ndn3_46); - assign n5844_1 = n_n7083 & ndn3_46 & ~preset & ~ngfdn_3; - assign n5845 = ~preset & n_n9096 & (ngfdn_3 | ~ndn3_46); - assign n5846 = ndn3_46 & n_n8258 & ~preset & ~ngfdn_3; - assign n5847 = ~preset & n_n9189 & (ndn3_13 | nsr3_13); - assign n5848 = ~preset & n_n9341 & (~ndn3_17 | ndn3_18); - assign n5849_1 = ~preset & n_n8260 & (ndn3_13 | nsr3_13); - assign n5850 = ~preset & n_n7918 & (nsr3_38 | ndn3_38); - assign n5851 = ~preset & n_n8996 & (~ndn3_39 | ndn3_40); - assign n5852 = ~preset & n_n7806 & (nsr3_38 | ndn3_38); - assign n5853 = ~preset & n_n8024 & (ndn3_42 | ~ndn3_40); - assign n5854_1 = ~preset & n_n8678 & (~ndn3_42 | ndn3_44); - assign n5855 = ~ndn3_44 & ndn3_42 & ~preset & n_n7948; - assign n5856 = ~preset & n_n9432 & (~ndn3_42 | ndn3_44); - assign n5857 = ~ndn3_44 & ndn3_42 & ~preset & n_n9036; - assign n5858 = ~ndn3_2 & ~preset & psv38_5_5_ & n4949_1; - assign n5859_1 = ~preset & n_n9174 & (ndn3_2 | ~n4949_1); - assign n5860 = ~preset & n_n7757 & (ndn3_42 | ~ndn3_40); - assign n5861 = ~preset & n_n7831 & (ndn3_30 | nsr3_30); - assign n5862 = ~ndn3_2 & ~preset & psv13_5_5_ & n4949_1; - assign n5863 = ~preset & n_n9501 & (ndn3_2 | ~n4949_1); - assign n5864_1 = ~preset & n_n8445 & (nsr3_38 | ndn3_38); - assign n5865 = ~ndn3_2 & ~preset & psv2_3_3_ & n4949_1; - assign n5866 = ~preset & n_n9408 & (ndn3_2 | ~n4949_1); - assign n5867 = ~preset & n_n9489 & (ndn3_30 | nsr3_30); - assign n5868 = ~preset & n_n7821 & (ndn3_25 | ~ndn3_22); - assign n5869_1 = ~preset & n4889_1 & (~n4971 ^ ~n4972); - assign n5870 = ~preset & n_n7217 & (ngfdn_3 | ~ndn3_46); - assign n5871 = ~preset & n_n9321 & (ndn3_7 | ~ndn3_4); - assign n5872 = ~preset & n4879_1 & (~n4954_1 ^ ~n4955); - assign n5873 = ~preset & n_n8843 & (nsr3_20 | ndn3_20); - assign n5874_1 = ~preset & n_n7641 & (ndn3_23 | nsr3_23); - assign n5875 = ~preset & n_n8258 & (ndn3_46 | ~ndn3_44); - assign n5876 = ~preset & n_n8247 & (ndn3_42 | ~ndn3_40); - assign n5877 = ~preset & n_n8957 & (~ndn3_39 | ndn3_40); - assign n5878 = ~preset & n_n8959 & (~ndn3_39 | ndn3_40); - assign n5879_1 = n4846 & (n5004_1 ^ (n6527 | n6528)); - assign n5880 = ~ndn3_2 & ~preset & psv26_8_8_ & n4949_1; - assign n5881 = ~preset & n_n7954 & (ndn3_2 | ~n4949_1); - assign n5882 = ~preset & n_n9601 & (ndn3_13 | nsr3_13); - assign n5883 = ~preset & n_n9465 & (~ndn3_42 | ndn3_44); - assign n5884_1 = ~ndn3_44 & ndn3_42 & ~preset & n_n8022; - assign n5885 = ~ndn3_2 & ~preset & psv26_0_0_ & n4949_1; - assign n5886 = ~preset & n_n7656 & (ndn3_2 | ~n4949_1); - assign n5887 = ~preset & n_n8998 & (~ndn3_25 | ndn3_26); - assign n5888 = ~preset & n_n8282 & (~ndn3_11 | ndn3_12); - assign n5889_1 = ~preset & n4849_1 & (~n4985 ^ ~n4986); - assign n5890 = ~preset & n_n7546 & (ngfdn_3 | ~ndn3_46); - assign n5891 = ~ngfdn_3 & ~preset & n_n9235 & ndn3_46; - assign n5892 = ~preset & n_n7174 & (ndn3_46 | ~ndn3_44); - assign n5893 = n_n9632 & ndn3_44 & ~preset & ~ndn3_46; - assign n5894_1 = ~preset & n_n8742 & (~ndn3_25 | ndn3_26); - assign n5895 = ~preset & n4851 & (~n4954_1 ^ ~n4955); - assign n5896 = ~preset & n_n8006 & (ndn3_7 | ~ndn3_4); - assign n5897 = ~ndn3_2 & ~preset & psv13_13_13_ & n4949_1; - assign n5898 = ~preset & n_n8414 & (ndn3_2 | ~n4949_1); - assign n5899_1 = ~ndn3_2 & ~preset & psv13_8_8_ & n4949_1; - assign n5900 = ~preset & n_n7955 & (ndn3_2 | ~n4949_1); - assign n5901 = ~preset & n_n7160 & (~ndn3_39 | ndn3_40); - assign n5902 = ~ndn3_40 & ndn3_39 & ~preset & n_n8906; - assign n5903 = ~ndn3_2 & ~preset & psv33_13_13_ & n4949_1; - assign n5904_1 = ~preset & n_n9098 & (ndn3_2 | ~n4949_1); - assign n5905 = ~preset & n_n7640 & (~ndn3_29 | ndn3_32); - assign n5906 = ~preset & n_n7803 & (ndn3_7 | ~ndn3_4); - assign n5907 = ~preset & n4879_1 & (~n4976 ^ ~n4977); - assign n5908 = ~ndn3_2 & ~preset & psv33_11_11_ & n4949_1; - assign n5909_1 = ~preset & n_n8086 & (ndn3_2 | ~n4949_1); - assign n5910 = ~preset & n_n9339 & (~nen3_22 | ndn3_22); - assign n5911 = n4866 & (n4987 ^ (n6433 | n6434)); - assign n5912 = n4949_1 & ~ndn3_2 & pinp_4_4_ & ~preset; - assign n5913 = ~preset & n_n8736 & (ndn3_2 | ~n4949_1); - assign n5914_1 = ~preset & n_n8005 & (~nen3_16 | ndn3_16); - assign n5915 = ~preset & n_n7823 & (~nen3_16 | ndn3_16); - assign n5916 = ~preset & n4875 & (~n4971 ^ ~n4972); - assign n5917 = ~preset & n_n8545 & (~ndn3_25 | ndn3_26); - assign n5918 = ~preset & n4851 & (~n4976 ^ ~n4977); - assign n5919_1 = ~preset & n_n8219 & (nsr3_20 | ndn3_20); - assign n5920 = ~preset & n_n7236 & (~ndn3_19 | ndn3_21); - assign n5921 = ~preset & n_n7428 & (ndn3_29 | ~ndn3_28); - assign n5922 = ~preset & n4869_1 & (~n4971 ^ ~n4972); - assign n5923 = ~preset & n_n9597 & (nsr3_20 | ndn3_20); - assign n5924_1 = n4949_1 & ~ndn3_2 & pinp_10_10_ & ~preset; - assign n5925 = ~preset & n_n8110 & (ndn3_2 | ~n4949_1); - assign n5926 = ~preset & n_n9391 & (ndn3_42 | ~ndn3_40); - assign n5927 = n4863 & (n4996 ^ (n6545 | n6546)); - assign n5928 = ~preset & n_n7758 & (ndn3_30 | nsr3_30); - assign n5929_1 = ~preset & n_n8278 & (ndn3_29 | ~ndn3_28); - assign n5930 = ~preset & n4869_1 & (~n4985 ^ ~n4986); - assign n5931 = ~preset & n_n9125 & (~ndn3_42 | ndn3_44); - assign n5932 = n4861 & (n4996 ^ (n6545 | n6546)); - assign n5933 = ~preset & n_n9169 & (ndn3_42 | ~ndn3_40); - assign n5934_1 = n_n6974 & ndn3_40 & ~preset & ~ndn3_42; - assign n5935 = ~ndn3_2 & ~preset & psv38_15_15_ & n4949_1; - assign n5936 = ~preset & n_n9223 & (ndn3_2 | ~n4949_1); - assign n5937 = ~preset & n_n9135 & (ndn3_4 | ~ndn3_2); - assign n5938 = ~preset & n_n7898 & (~ndn3_42 | ndn3_44); - assign n5939_1 = ~preset & n_n8765 & (ndn3_46 | ~ndn3_44); - assign n5940 = ~preset & n_n7908 & (ndn3_37 | nsr3_37); - assign n5941 = ~preset & n_n7462 & (~ngfdn_3 | ndn3_50); - assign n5942 = ~ndn3_50 & n_n9219 & ~preset & ngfdn_3; - assign n5943 = ~preset & n_n7384 & (ndn3_46 | ~ndn3_44); - assign n5944_1 = ~preset & n_n9613 & (~nen3_39 | ndn3_39); - assign n5945 = ~preset & n4854_1 & (~n4985 ^ ~n4986); - assign n5946 = ~ndn3_2 & ~preset & psv13_3_3_ & n4949_1; - assign n5947 = ~preset & n_n9406 & (ndn3_2 | ~n4949_1); - assign n5948 = ~preset & n_n9611 & (~nen3_39 | ndn3_39); - assign n5949_1 = ~preset & n_n7324 & (ngfdn_3 | ~ndn3_46); - assign n5950 = ~preset & n_n9335 & (ndn3_37 | nsr3_37); - assign n5951 = ~preset & n_n9127 & (ndn3_37 | nsr3_37); - assign n5952 = ~ngfdn_3 & nsr1_2 & (~preset_0_0_ | nlc1_2); - assign n5953 = ~preset & n_n9400 & (~nen3_16 | ndn3_16); - assign n5954_1 = ~preset & n_n9343 & (nsr3_13 | ndn3_15); - assign n5955 = ~preset & n_n7054 & (ndn3_42 | ~ndn3_40); - assign n5956 = ~ndn3_42 & ~preset & n_n9576 & ndn3_40; - assign n5957 = ~preset & n_n7948 & (ndn3_42 | ~ndn3_40); - assign n5958 = ~preset & n_n7783 & (ndn3_46 | ~ndn3_44); - assign n5959_1 = n4853 & (n5004_1 ^ (n6527 | n6528)); - assign n5960 = ~preset & n_n7602 & (ndn3_23 | nsr3_23); - assign n5961 = ~preset & n_n7740 & (nsr3_20 | ndn3_20); - assign n5962 = ~preset & n_n7691 & (~ndn3_42 | ndn3_44); - assign n5963 = ~preset & n_n9483 & (~ngfdn_3 | ndn3_50); - assign n5964_1 = ~ndn3_50 & ~preset & ngfdn_3 & n_n8948; - assign n5965 = ~preset & n_n9049 & (nsr3_14 | ndn3_14); - assign n5966 = ~preset & n_n9588 & (ndn3_34 | ~nen3_34); - assign n5967 = ~preset & n4860 & (~n4969_1 ^ ~n4970); - assign n5968 = ~preset & n_n7791 & (~ndn3_9 | ndn3_11); - assign n5969_1 = ~preset & n_n7857 & (ndn3_46 | ~ndn3_44); - assign n5970 = ~ndn3_46 & ~preset & n_n7706 & ndn3_44; - assign n5971 = n4900 & (n5975 | (n4975 & n7176)); - assign n5972 = n4856 & (~n_n8631 ^ (n_n8561 | n4999_1)); - assign n5973 = n4897 & (n5975 | (n4975 & n7176)); - assign n5974_1 = n4856 & (n_n8913 ^ ~n4968); - assign n5975 = n7089 & n4967 & ~preset & ~n_n9247; - assign n5976 = ~ndn3_2 & ~preset & psv13_14_14_ & n4949_1; - assign n5977 = ~preset & n_n8114 & (ndn3_2 | ~n4949_1); - assign n5978 = ~ndn3_2 & ~preset & psv39_15_15_ & n4949_1; - assign n5979_1 = ~preset & n_n8491 & (ndn3_2 | ~n4949_1); - assign n5980 = ~preset & n_n8175 & (~nen3_22 | ndn3_22); - assign n5981 = ~ndn3_22 & ~preset & nen3_22 & n_n9252; - assign n5982 = ~preset & n_n9257 & (ndn3_13 | nsr3_13); - assign n5983 = ~preset & n_n8091 & (~ngfdn_3 | ndn3_50); - assign n5984_1 = ~ndn3_50 & n_n8466 & ~preset & ngfdn_3; - assign n5985 = ~preset & n_n8066 & (nsr3_14 | ndn3_14); - assign n5986 = ~ndn3_2 & ~preset & psv13_2_2_ & n4949_1; - assign n5987 = ~preset & n_n8053 & (ndn3_2 | ~n4949_1); - assign n5988 = ~preset & n_n7811 & (nsr3_13 | ndn3_15); - assign n5989_1 = ~preset & n_n7934 & (ndn3_13 | nsr3_13); - assign n5990 = ~preset & n_n7735 & (ndn3_30 | nsr3_30); - assign n5991 = ~preset & n_n7651 & (ndn3_30 | nsr3_30); - assign n5992 = ~preset & n_n9412 & (~ndn3_19 | ndn3_21); - assign n5993 = ~preset & n_n9398 & (~nen3_22 | ndn3_22); - assign n5994_1 = n4866 & (n4996 ^ (n6545 | n6546)); - assign n5995 = ~preset & n_n9064 & (nsr3_20 | ndn3_20); - assign n5996 = ~ndn3_2 & ~preset & psv2_15_15_ & n4949_1; - assign n5997 = ~preset & n_n8007 & (ndn3_2 | ~n4949_1); - assign n5998 = n4949_1 & ~ndn3_2 & pinp_15_15_ & ~preset; - assign n5999_1 = ~preset & n_n8482 & (ndn3_2 | ~n4949_1); - assign n6000 = ~ndn3_2 & ~preset & psv2_14_14_ & n4949_1; - assign n6001 = ~preset & n_n7937 & (ndn3_2 | ~n4949_1); - assign n6002 = n4949_1 & ~ndn3_2 & pinp_13_13_ & ~preset; - assign n6003 = ~preset & n_n7850 & (ndn3_2 | ~n4949_1); - assign n6004_1 = n7175 & ((n4918 & n4919_1) | (n_n9512 & (n4918 | n4919_1))); - assign n6005 = ~n_n9434 & n4857 & (~n4893 ^ ~n4894_1); - assign n6006 = ~n4894_1 & ~n4893 & n_n9434 & n4856; - assign n6007 = ~n5001 & ~preset & n_n9434; - assign n6008 = ~preset & n_n9399 & (nsr3_20 | ndn3_20); - assign n6009_1 = ~preset & n_n8333 & (ndn3_28 | ~nen3_28); - assign n6010 = ~preset & n4892 & (~n4985 ^ ~n4986); - assign n6011 = ~ndn3_2 & ~preset & psv18_11_11_ & n4949_1; - assign n6012 = ~preset & n_n7759 & (ndn3_2 | ~n4949_1); - assign n6013 = ~preset & n_n8661 & (nsr3_14 | ndn3_14); - assign n6014_1 = ~preset & n_n8132 & (ndn3_42 | ~ndn3_40); - assign n6015 = ~ndn3_42 & ~preset & n_n8150 & ndn3_40; - assign n6016 = ~preset & n_n8488 & (~nen3_22 | ndn3_22); - assign n6017 = ~ndn3_22 & n_n9412 & ~preset & nen3_22; - assign n6018 = ~preset & n_n7953 & (ndn3_13 | nsr3_13); - assign n6019_1 = ~preset & n_n7179 & (ngfdn_3 | ~ndn3_46); - assign n6020 = ndn3_46 & n_n7783 & ~preset & ~ngfdn_3; - assign n6021 = ~preset & n_n9265 & (~ndn3_17 | ndn3_18); - assign n6022 = ~preset & n4877 & (~n4969_1 ^ ~n4970); - assign n6023 = ~preset & n_n9052 & (ndn3_4 | ~ndn3_2); - assign n6024_1 = ~preset & n4874_1 & (~n4954_1 ^ ~n4955); - assign n6025 = ~preset & n_n9106 & (~nen3_39 | ndn3_39); - assign n6026 = ~preset & n4854_1 & (~n4954_1 ^ ~n4955); - assign n6027 = ~preset & n_n8702 & (~nen3_22 | ndn3_22); - assign n6028 = ~ndn3_22 & ~preset & nen3_22 & n_n8213; - assign n6029_1 = ~preset & n_n7190 & (~ndn3_42 | ndn3_44); - assign n6030 = ~ndn3_44 & ndn3_42 & ~preset & n_n8249; - assign n6031 = ~preset & n_n9635 & (~ndn3_42 | ndn3_44); - assign n6032 = n4861 & (n4980 ^ (n6352 | n6353)); - assign n6033 = ~preset & n_n8001 & (nsr3_38 | ndn3_38); - assign n6034_1 = ~preset & n_n9000 & (ndn3_25 | ~ndn3_22); - assign n6035 = ~preset & n_n9598 & (~nen3_16 | ndn3_16); - assign n6036 = ~preset & n4875 & (~n4969_1 ^ ~n4970); - assign n6037 = ~preset & n_n8786 & (ndn3_7 | ~ndn3_4); - assign n6038 = ~preset & n_n9602 & (ndn3_7 | ~ndn3_4); - assign n6039_1 = ~preset & n4879_1 & (~n4969_1 ^ ~n4970); - assign n6040 = ~preset & n_n8981 & (ndn3_29 | ~ndn3_28); - assign n6041 = ~preset & n_n8308 & (ndn3_46 | ~ndn3_44); - assign n6042 = ~preset & n_n8609 & (ndn3_42 | ~ndn3_40); - assign n6043 = n4863 & (n5004_1 ^ (n6527 | n6528)); - assign n6044_1 = ~preset & n_n8699 & (nsr3_20 | ndn3_20); - assign n6045 = ~preset & n_n8533 & (ndn3_23 | nsr3_23); - assign n6046 = ~preset & n_n9273 & (~ndn3_19 | ndn3_21); - assign n6047 = ~preset & n_n9311 & (nsr3_35 | ndn3_35); - assign n6048 = ~preset & n_n7148 & (~ndn3_42 | ndn3_44); - assign n6049_1 = ~ndn3_44 & ndn3_42 & ~preset & n_n9623; - assign n6050 = ~preset & n_n8227 & (~ndn3_11 | ndn3_12); - assign n6051 = ~preset & n_n7970 & (~ndn3_9 | ndn3_11); - assign n6052 = ~preset & n_n7581 & (~nen3_22 | ndn3_22); - assign n6053 = ~ndn3_22 & ~preset & nen3_22 & n_n9351; - assign n6054_1 = ~preset & n_n9008 & (ndn3_9 | ~ndn3_7); - assign n6055 = ~preset & n4852 & (~n4971 ^ ~n4972); - assign n6056 = ~ndn3_2 & ~preset & psv26_12_12_ & n4949_1; - assign n6057 = ~preset & n_n7814 & (ndn3_2 | ~n4949_1); - assign n6058 = ~preset & n_n7877 & (~ndn3_11 | ndn3_12); - assign n6059_1 = ~ndn3_2 & ~preset & psv26_11_11_ & n4949_1; - assign n6060 = ~preset & n_n7765 & (ndn3_2 | ~n4949_1); - assign n6061 = ~preset & n_n8758 & (ndn3_7 | ~ndn3_4); - assign n6062 = ~preset & n4879_1 & (~n4985 ^ ~n4986); - assign n6063 = ~preset & n_n7332 & (~ndn3_39 | ndn3_40); - assign n6064_1 = ~ndn3_40 & ~preset & ndn3_39 & n_n8991; - assign n6065 = ~ndn3_2 & ~preset & psv39_12_12_ & n4949_1; - assign n6066 = ~preset & n_n7816 & (ndn3_2 | ~n4949_1); - assign n6067 = ~preset & n_n7812 & (ndn3_13 | nsr3_13); - assign n6068 = ~preset & n_n8394 & (ndn3_13 | nsr3_13); - assign n6069_1 = ~preset & n_n8152 & (ndn3_17 | ~ndn3_16); - assign n6070 = ~preset & n4882 & (~n4976 ^ ~n4977); - assign n6071 = ~preset & n_n8597 & (~ndn3_17 | ndn3_18); - assign n6072 = ~preset & n4877 & (~n4976 ^ ~n4977); - assign n6073 = ~preset & n_n7889 & (nsr3_13 | ndn3_15); - assign n6074_1 = ~preset & n4881 & (~n4985 ^ ~n4986); - assign n6075 = ~preset & n_n7888 & (~nen3_16 | ndn3_16); - assign n6076 = ~preset & n4875 & (~n4985 ^ ~n4986); - assign n6077 = ~preset & n_n8225 & (ndn3_19 | ~nen3_19); - assign n6078 = ~preset & n_n7599 & (ndn3_37 | nsr3_37); - assign n6079_1 = ~preset & n_n7558 & (ngfdn_3 | ~ndn3_46); - assign n6080 = n1270 & (n4996 ^ (n6545 | n6546)); - assign n6081 = ~preset & n_n8377 & (ndn3_7 | ~ndn3_4); - assign n6082 = ~preset & n_n8208 & (~ndn3_17 | ndn3_18); - assign n6083 = n4952 & ((n4994_1 & n4995) | (n4986 & (~n4994_1 ^ ~n4995))); - assign n6084_1 = (n7157 | n7158) & (n7164 | n7165); - assign n6085 = n_n9568 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6086 = n_n8772 & (n6900 | (~ndn3_17 & ndn3_16)); - assign n6087 = n_n7914 & ~ndn3_7 & ndn3_4; - assign n6088 = n_n7913 & ndn3_11 & ~ndn3_12; - assign n6089_1 = ndn3_40 & n_n7908 & ~ndn3_42; - assign n6090 = ndn3_26 & ~ndn3_27 & n_n7932; - assign n6091 = n_n9632 & ~ngfdn_3 & ndn3_46; - assign n6092 = n_n8535 & nen3_16 & ~ndn3_16; - assign n6093 = ~ndn3_32 & ndn3_29 & n_n7910; - assign n6094_1 = ~ndn3_40 & n_n7909 & ndn3_39; - assign n6095 = n_n7912 & ndn3_19 & ~ndn3_21; - assign n6096 = n_n7911 & ~ndn3_25 & ndn3_22; - assign n6097 = ndn3_44 & n_n8512 & ~ndn3_46; - assign n6098 = n_n8106 & ndn3_17 & ~ndn3_18; - assign n6099 = n_n7935 & ((nen3_16 & ~ndn3_16) | n6908); - assign n6100 = n_n7936 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6101 = ndn3_2 & n_n7937 & ~ndn3_4; - assign n6102 = n_n7928 & nen3_39 & ~ndn3_39; - assign n6103 = ndn3_7 & ~ndn3_9 & n_n8114; - assign n6104 = ndn3_46 & ~ngfdn_3 & n_n9108; - assign n6105 = n_n7946 & ndn3_9 & ~ndn3_11; - assign n6106 = n_n7933 & ndn3_19 & ~ndn3_21; - assign n6107 = nen3_28 & n_n7931 & ~ndn3_28; - assign n6108 = n_n7927 & ~ndn3_46 & ndn3_44; - assign n6109 = ~ndn3_44 & n_n8445 & ndn3_42; - assign n6110 = nen3_34 & ~ndn3_34 & n_n8425; - assign n6111 = ~ndn3_36 & nen3_36 & n_n7929; - assign n6112 = n_n8516 & ndn3_17 & ~ndn3_18; - assign n6113 = n_n8219 & nen3_22 & ~ndn3_22; - assign n6114 = ~ndn3_15 & n_n7934 & ~nsr3_13; - assign n6115 = n_n7971 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6116 = n_n8014 & ((~ndn3_17 & ndn3_16) | n6900); - assign n6117 = ndn3_4 & ~ndn3_7 & n_n8456; - assign n6118 = ~ndn3_12 & n_n7970 & ndn3_11; - assign n6119 = ndn3_40 & n_n7966 & ~ndn3_42; - assign n6120 = ndn3_26 & ~ndn3_27 & n_n8004; - assign n6121 = n_n8468 & ~ngfdn_3 & ndn3_46; - assign n6122 = n_n7969 & nen3_16 & ~ndn3_16; - assign n6123 = ~ndn3_32 & ndn3_29 & n_n9077; - assign n6124 = ~ndn3_40 & n_n7967 & ndn3_39; - assign n6125 = ~ndn3_21 & n_n8208 & ndn3_19; - assign n6126 = n_n7968 & ~ndn3_25 & ndn3_22; - assign n6127 = ndn3_44 & n_n8864 & ~ndn3_46; - assign n6128 = n_n8519 & ndn3_17 & ~ndn3_18; - assign n6129 = n_n8006 & (n6908 | (nen3_16 & ~ndn3_16)); - assign n6130 = n_n8491 & (n6909 | (~ndn3_25 & ndn3_22)); - assign n6131 = ndn3_2 & n_n8007 & ~ndn3_4; - assign n6132 = n_n8078 & nen3_39 & ~ndn3_39; - assign n6133 = n_n8502 & ~ndn3_9 & ndn3_7; - assign n6134 = n_n8580 & ~ngfdn_3 & ndn3_46; - assign n6135 = n_n8192 & ndn3_9 & ~ndn3_11; - assign n6136 = ~ndn3_21 & n_n8005 & ndn3_19; - assign n6137 = nen3_28 & ~ndn3_28 & n_n8003; - assign n6138 = ndn3_44 & ~ndn3_46 & n_n9355; - assign n6139 = ~ndn3_44 & n_n8001 & ndn3_42; - assign n6140 = nen3_34 & ~ndn3_34 & n_n8839; - assign n6141 = ~ndn3_36 & nen3_36 & n_n8900; - assign n6142 = n_n8584 & ndn3_17 & ~ndn3_18; - assign n6143 = n_n8064 & nen3_22 & ~ndn3_22; - assign n6144 = n_n8344 & ~nsr3_13 & ~ndn3_15; - assign n6145 = ~preset & n_n8775 & (ndn3_4 | ~ndn3_2); - assign n6146 = ~preset & n4874_1 & (~n4985 ^ ~n4986); - assign n6147 = n_n8758 & (n6908 | (nen3_16 & ~ndn3_16)); - assign n6148 = n_n8504 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6149 = ndn3_2 & ~ndn3_4 & n_n7890; - assign n6150 = ~ndn3_39 & nen3_39 & n_n7988; - assign n6151 = ndn3_7 & ~ndn3_9 & n_n8414; - assign n6152 = ndn3_46 & ~ngfdn_3 & n_n8626; - assign n6153 = n_n9067 & ndn3_9 & ~ndn3_11; - assign n6154 = ~ndn3_21 & n_n7888 & ndn3_19; - assign n6155 = nen3_28 & ~ndn3_28 & n_n7887; - assign n6156 = ndn3_44 & n_n9623 & ~ndn3_46; - assign n6157 = ~ndn3_44 & n_n7885 & ndn3_42; - assign n6158 = nen3_34 & n_n8333 & ~ndn3_34; - assign n6159 = n_n9092 & nen3_36 & ~ndn3_36; - assign n6160 = n_n8282 & ndn3_17 & ~ndn3_18; - assign n6161 = ~ndn3_22 & nen3_22 & n_n9064; - assign n6162 = ~ndn3_15 & n_n8394 & ~nsr3_13; - assign n6163 = n_n8775 & (n6899 | (nen3_22 & ~ndn3_22)); - assign n6164 = n_n7849 & ((~ndn3_17 & ndn3_16) | n6900); - assign n6165 = ndn3_4 & n_n9098 & ~ndn3_7; - assign n6166 = n_n7848 & ndn3_11 & ~ndn3_12; - assign n6167 = ndn3_40 & n_n8480 & ~ndn3_42; - assign n6168 = ndn3_26 & ~ndn3_27 & n_n9520; - assign n6169 = n_n8470 & ~ngfdn_3 & ndn3_46; - assign n6170 = n_n8909 & nen3_16 & ~ndn3_16; - assign n6171 = ~ndn3_32 & ndn3_29 & n_n7845; - assign n6172 = n_n7844 & ndn3_39 & ~ndn3_40; - assign n6173 = ~ndn3_21 & n_n7847 & ndn3_19; - assign n6174 = n_n7846 & ~ndn3_25 & ndn3_22; - assign n6175 = ndn3_44 & ~ndn3_46 & n_n8277; - assign n6176 = ~ndn3_18 & n_n7889 & ndn3_17; - assign n6177 = ~preset & n_n7452 & (ndn3_29 | ~ndn3_28); - assign n6178 = n7123 & ((n4934_1 & n4937) | (n_n8821 & (n4934_1 | n4937))); - assign n6179 = ~n_n9638 & n4857 & (~n4870 ^ ~n4871); - assign n6180 = ~n4871 & ~n4870 & n_n9638 & n4856; - assign n6181 = ~n5001 & ~preset & n_n9638; - assign n6182 = ~preset & n_n7522 & (ndn3_42 | ~ndn3_40); - assign n6183 = ~ndn3_42 & ~preset & n_n9102 & ndn3_40; - assign n6184 = ~preset & n_n9235 & (ndn3_46 | ~ndn3_44); - assign n6185 = ~preset & n_n9486 & (ndn3_42 | ~ndn3_40); - assign n6186 = ~preset & n_n9130 & (ndn3_23 | nsr3_23); - assign n6187 = ~ndn3_2 & ~preset & psv38_11_11_ & n4949_1; - assign n6188 = ~preset & n_n7709 & (ndn3_2 | ~n4949_1); - assign n6189 = ~preset & n_n7819 & (nsr3_35 | ndn3_35); - assign n6190 = ~ndn3_2 & ~preset & psv18_15_15_ & n4949_1; - assign n6191 = ~preset & n_n8002 & (ndn3_2 | ~n4949_1); - assign n6192 = ~preset & n_n9467 & (ndn3_34 | ~nen3_34); - assign n6193 = ~preset & n4860 & (~n4976 ^ ~n4977); - assign n6194 = ~preset & n_n9548 & (ngfdn_3 | ~ndn3_46); - assign n6195 = ndn3_46 & n_n7384 & ~preset & ~ngfdn_3; - assign n6196 = ~preset & n_n7707 & (ndn3_37 | nsr3_37); - assign n6197 = ~n5001 & ~preset & n_n8557; - assign n6198 = n_n8584 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6199 = nsr3_20 & ndn3_17 & n_n8583; - assign n6200 = nsr3_35 & ndn3_29 & n_n8941; - assign n6201 = nen3_34 & n_n8864 & nsr3_37; - assign n6202 = ndn3_26 & nsr3_30 & n_n8581; - assign n6203 = n_n8580 & nsr3_38 & nen3_36; - assign n6204 = ndn3_19 & nsr3_23 & n_n8582; - assign n6205 = n_n8227 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6206 = n_n8226 & ndn3_17 & nsr3_20; - assign n6207 = n_n8224 & ndn3_29 & nsr3_35; - assign n6208 = nen3_34 & n_n8223 & nsr3_37; - assign n6209 = ndn3_26 & nsr3_30 & n_n9205; - assign n6210 = n_n8222 & nsr3_38 & nen3_36; - assign n6211 = ndn3_19 & n_n8225 & nsr3_23; - assign n6212 = n_n8203 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6213 = nsr3_20 & ndn3_17 & n_n9019; - assign n6214 = n_n8201 & ndn3_29 & nsr3_35; - assign n6215 = nen3_34 & n_n9110 & nsr3_37; - assign n6216 = ndn3_26 & nsr3_30 & n_n9615; - assign n6217 = n_n9516 & nsr3_38 & nen3_36; - assign n6218 = ndn3_19 & n_n8202 & nsr3_23; - assign n6219 = n_n7951 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6220 = nsr3_20 & ndn3_17 & n_n8753; - assign n6221 = nsr3_35 & ndn3_29 & n_n7474; - assign n6222 = nen3_34 & n_n9518 & nsr3_37; - assign n6223 = ndn3_26 & nsr3_30 & n_n9286; - assign n6224 = n_n7947 & nsr3_38 & nen3_36; - assign n6225 = n_n7588 & nsr3_23 & ndn3_19; - assign n6226 = n_n9141 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6227 = nsr3_20 & ndn3_17 & n_n7375; - assign n6228 = nsr3_35 & n_n7373 & ndn3_29; - assign n6229 = nen3_34 & n_n8499 & nsr3_37; - assign n6230 = ndn3_26 & nsr3_30 & n_n7487; - assign n6231 = n_n8135 & nsr3_38 & nen3_36; - assign n6232 = n_n7374 & nsr3_23 & ndn3_19; - assign n6233 = n_n9015 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6234 = nsr3_20 & ndn3_17 & n_n8104; - assign n6235 = n_n8828 & ndn3_29 & nsr3_35; - assign n6236 = nen3_34 & n_n7670 & nsr3_37; - assign n6237 = ndn3_26 & n_n7341 & nsr3_30; - assign n6238 = nen3_36 & n_n8862 & nsr3_38; - assign n6239 = n_n7342 & nsr3_23 & ndn3_19; - assign n6240 = n_n9318 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6241 = nsr3_20 & ndn3_17 & n_n8744; - assign n6242 = nsr3_35 & ndn3_29 & n_n8741; - assign n6243 = nen3_34 & n_n9042 & nsr3_37; - assign n6244 = ndn3_26 & n_n8742 & nsr3_30; - assign n6245 = n_n9308 & nsr3_38 & nen3_36; - assign n6246 = n_n8743 & nsr3_23 & ndn3_19; - assign n6247 = n_n9401 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6248 = n_n8811 & ndn3_17 & nsr3_20; - assign n6249 = nsr3_35 & ndn3_29 & n_n8808; - assign n6250 = nen3_34 & n_n9126 & nsr3_37; - assign n6251 = ndn3_26 & nsr3_30 & n_n8809; - assign n6252 = n_n9390 & nsr3_38 & nen3_36; - assign n6253 = n_n8810 & nsr3_23 & ndn3_19; - assign n6254 = n_n7824 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6255 = nsr3_20 & ndn3_17 & n_n8729; - assign n6256 = nsr3_35 & ndn3_29 & n_n7428; - assign n6257 = nen3_34 & n_n7598 & nsr3_37; - assign n6258 = n_n7485 & nsr3_30 & ndn3_26; - assign n6259 = n_n8898 & nsr3_38 & nen3_36; - assign n6260 = n_n7429 & nsr3_23 & ndn3_19; - assign n6261 = n_n9496 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6262 = nsr3_20 & ndn3_17 & n_n8884; - assign n6263 = n_n8881 & ndn3_29 & nsr3_35; - assign n6264 = nen3_34 & n_n9473 & nsr3_37; - assign n6265 = ndn3_26 & n_n8882 & nsr3_30; - assign n6266 = nen3_36 & n_n9485 & nsr3_38; - assign n6267 = ndn3_19 & n_n8883 & nsr3_23; - assign n6268 = n_n7877 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6269 = nsr3_20 & ndn3_17 & n_n8727; - assign n6270 = nsr3_35 & n_n7452 & ndn3_29; - assign n6271 = nen3_34 & n_n7640 & nsr3_37; - assign n6272 = n_n7453 & nsr3_30 & ndn3_26; - assign n6273 = n_n9458 & nsr3_38 & nen3_36; - assign n6274 = ndn3_19 & nsr3_23 & n_n7454; - assign n6275 = n_n9599 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6276 = nsr3_20 & ndn3_17 & n_n8939; - assign n6277 = n_n8937 & ndn3_29 & nsr3_35; - assign n6278 = nen3_34 & n_n9470 & nsr3_37; - assign n6279 = ndn3_26 & nsr3_30 & n_n8938; - assign n6280 = nen3_36 & n_n9588 & nsr3_38; - assign n6281 = n_n9139 & nsr3_23 & ndn3_19; - assign n6282 = n_n8984 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6283 = nsr3_20 & ndn3_17 & n_n8983; - assign n6284 = nsr3_35 & n_n8981 & ndn3_29; - assign n6285 = nen3_34 & n_n9334 & nsr3_37; - assign n6286 = ndn3_26 & n_n8998 & nsr3_30; - assign n6287 = n_n8980 & nsr3_38 & nen3_36; - assign n6288 = n_n8982 & nsr3_23 & ndn3_19; - assign n6289 = n_n8153 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6290 = nsr3_20 & n_n8152 & ndn3_17; - assign n6291 = n_n8177 & ndn3_29 & nsr3_35; - assign n6292 = nen3_34 & nsr3_37 & n_n8628; - assign n6293 = ndn3_26 & n_n8545 & nsr3_30; - assign n6294 = nen3_36 & n_n9467 & nsr3_38; - assign n6295 = n_n8151 & nsr3_23 & ndn3_19; - assign n6296 = n_n8282 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6297 = nsr3_20 & ndn3_17 & n_n8281; - assign n6298 = nsr3_35 & ndn3_29 & n_n8278; - assign n6299 = nen3_34 & n_n8277 & nsr3_37; - assign n6300 = ndn3_26 & n_n8279 & nsr3_30; - assign n6301 = n_n8626 & nsr3_38 & nen3_36; - assign n6302 = n_n8280 & nsr3_23 & ndn3_19; - assign n6303 = n_n8516 & (nsr3_13 ? ndn3_12 : nsr3_14); - assign n6304 = nsr3_20 & ndn3_17 & n_n8515; - assign n6305 = n_n8513 & ndn3_29 & nsr3_35; - assign n6306 = nen3_34 & n_n8512 & nsr3_37; - assign n6307 = ndn3_26 & nsr3_30 & n_n9203; - assign n6308 = n_n9108 & nsr3_38 & nen3_36; - assign n6309 = n_n8514 & nsr3_23 & ndn3_19; - assign n6310 = ~preset & n_n6991 & (ngfdn_3 | ~ndn3_46); - assign n6311 = ndn3_46 & n_n7896 & ~preset & ~ngfdn_3; - assign n6312 = ~preset & n_n7271 & (ngfdn_3 | ~ndn3_46); - assign n6313 = ~ngfdn_3 & ~preset & n_n8308 & ndn3_46; - assign n6314 = ~preset & n_n7252 & (ngfdn_3 | ~ndn3_46); - assign n6315 = n_n7444 & ndn3_46 & ~preset & ~ngfdn_3; - assign n6316 = ~preset & n_n8871 & (~nen3_39 | ndn3_39); - assign n6317 = ~preset & n_n8592 & (ndn3_46 | ~ndn3_44); - assign n6318 = ~ndn3_46 & ~preset & n_n9259 & ndn3_44; - assign n6319 = ~preset & n_n9401 & (~ndn3_11 | ndn3_12); - assign n6320 = ~preset & n_n8150 & (~ndn3_39 | ndn3_40); - assign n6321 = n4846 & (n4980 ^ (n6352 | n6353)); - assign n6322 = n_n7813 & ((nen3_16 & ~ndn3_16) | n6908); - assign n6323 = n_n7816 & (n6909 | (~ndn3_25 & ndn3_22)); - assign n6324 = ndn3_2 & n_n7817 & ~ndn3_4; - assign n6325 = ~ndn3_39 & nen3_39 & n_n7807; - assign n6326 = n_n7815 & ~ndn3_9 & ndn3_7; - assign n6327 = ndn3_46 & ~ngfdn_3 & n_n8222; - assign n6328 = ~ndn3_11 & n_n7814 & ndn3_9; - assign n6329 = n_n7810 & ndn3_19 & ~ndn3_21; - assign n6330 = nen3_28 & ~ndn3_28 & n_n8473; - assign n6331 = ndn3_44 & n_n8022 & ~ndn3_46; - assign n6332 = ~ndn3_44 & n_n7806 & ndn3_42; - assign n6333 = nen3_34 & ~ndn3_34 & n_n7859; - assign n6334 = ~ndn3_36 & nen3_36 & n_n7808; - assign n6335 = ~ndn3_18 & n_n8227 & ndn3_17; - assign n6336 = n_n8657 & nen3_22 & ~ndn3_22; - assign n6337 = ~ndn3_15 & n_n7812 & ~nsr3_13; - assign n6338 = n_n7793 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6339 = n_n7792 & ((~ndn3_17 & ndn3_16) | n6900); - assign n6340 = n_n8267 & ~ndn3_7 & ndn3_4; - assign n6341 = ~ndn3_12 & n_n7791 & ndn3_11; - assign n6342 = n_n7788 & ~ndn3_42 & ndn3_40; - assign n6343 = ndn3_26 & ~ndn3_27 & n_n7809; - assign n6344 = ndn3_46 & n_n9635 & ~ngfdn_3; - assign n6345 = n_n9525 & nen3_16 & ~ndn3_16; - assign n6346 = ~ndn3_32 & ndn3_29 & n_n7790; - assign n6347 = ~ndn3_40 & n_n7789 & ndn3_39; - assign n6348 = n_n8402 & ndn3_19 & ~ndn3_21; - assign n6349 = n_n8841 & ~ndn3_25 & ndn3_22; - assign n6350 = ndn3_44 & n_n8223 & ~ndn3_46; - assign n6351 = ~ndn3_18 & ndn3_17 & n_n7811; - assign n6352 = (n7062 | n7063) & (n7069 | n7070); - assign n6353 = n5002 & ((n4988 & n4989_1) | (n4976 & (n4988 ^ n4989_1))); - assign n6354 = ~ndn3_2 & ~preset & psv2_5_5_ & n4949_1; - assign n6355 = ~preset & n_n9503 & (ndn3_2 | ~n4949_1); - assign n6356 = ~preset & n_n7779 & (ngfdn_3 | ~ndn3_46); - assign n6357 = n_n7764 & ((nen3_16 & ~ndn3_16) | n6908); - assign n6358 = n_n8506 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6359 = ndn3_2 & n_n9387 & ~ndn3_4; - assign n6360 = n_n7990 & nen3_39 & ~ndn3_39; - assign n6361 = n_n7766 & ~ndn3_9 & ndn3_7; - assign n6362 = n_n9516 & ~ngfdn_3 & ndn3_46; - assign n6363 = ~ndn3_11 & n_n7765 & ndn3_9; - assign n6364 = n_n7762 & ndn3_19 & ~ndn3_21; - assign n6365 = n_n8852 & ~ndn3_28 & nen3_28; - assign n6366 = ndn3_44 & n_n7757 & ~ndn3_46; - assign n6367 = ~ndn3_44 & n_n7918 & ndn3_42; - assign n6368 = nen3_34 & n_n9157 & ~ndn3_34; - assign n6369 = ~ndn3_36 & n_n7758 & nen3_36; - assign n6370 = n_n8203 & ndn3_17 & ~ndn3_18; - assign n6371 = n_n7761 & nen3_22 & ~ndn3_22; - assign n6372 = n_n8396 & ~nsr3_13 & ~ndn3_15; - assign n6373 = n_n7901 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6374 = n_n7713 & (n6900 | (~ndn3_17 & ndn3_16)); - assign n6375 = ndn3_4 & n_n8086 & ~ndn3_7; - assign n6376 = n_n9210 & ndn3_11 & ~ndn3_12; - assign n6377 = ndn3_40 & n_n7707 & ~ndn3_42; - assign n6378 = ndn3_26 & n_n7760 & ~ndn3_27; - assign n6379 = ndn3_46 & ~ngfdn_3 & n_n7706; - assign n6380 = ~ndn3_16 & n_n8066 & nen3_16; - assign n6381 = ~ndn3_32 & ndn3_29 & n_n7710; - assign n6382 = ~ndn3_40 & n_n7708 & ndn3_39; - assign n6383 = ~ndn3_21 & n_n7712 & ndn3_19; - assign n6384 = n_n7711 & ~ndn3_25 & ndn3_22; - assign n6385 = ndn3_44 & n_n9110 & ~ndn3_46; - assign n6386 = n_n7763 & ndn3_17 & ~ndn3_18; - assign n6387 = n_n8760 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6388 = n_n7668 & ((~ndn3_17 & ndn3_16) | n6900); - assign n6389 = ndn3_4 & n_n9300 & ~ndn3_7; - assign n6390 = ~ndn3_12 & ndn3_11 & n_n8276; - assign n6391 = n_n9505 & ~ndn3_42 & ndn3_40; - assign n6392 = ndn3_26 & ~ndn3_27 & n_n7684; - assign n6393 = ndn3_46 & ~ngfdn_3 & n_n7898; - assign n6394 = n_n8221 & nen3_16 & ~ndn3_16; - assign n6395 = ~ndn3_32 & ndn3_29 & n_n7666; - assign n6396 = n_n7664 & ndn3_39 & ~ndn3_40; - assign n6397 = ~ndn3_21 & n_n8597 & ndn3_19; - assign n6398 = n_n7667 & ~ndn3_25 & ndn3_22; - assign n6399 = n_n8628 & ~ndn3_46 & ndn3_44; - assign n6400 = n_n7687 & ndn3_17 & ~ndn3_18; - assign n6401 = n_n7803 & (n6908 | (nen3_16 & ~ndn3_16)); - assign n6402 = n_n8116 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6403 = ndn3_2 & n_n7689 & ~ndn3_4; - assign n6404 = n_n7682 & nen3_39 & ~ndn3_39; - assign n6405 = n_n9119 & ~ndn3_9 & ndn3_7; - assign n6406 = ndn3_46 & n_n9467 & ~ngfdn_3; - assign n6407 = n_n7688 & ndn3_9 & ~ndn3_11; - assign n6408 = n_n7686 & ndn3_19 & ~ndn3_21; - assign n6409 = nen3_28 & ~ndn3_28 & n_n7683; - assign n6410 = ndn3_44 & n_n8024 & ~ndn3_46; - assign n6411 = ~ndn3_44 & n_n7681 & ndn3_42; - assign n6412 = nen3_34 & ~ndn3_34 & n_n8889; - assign n6413 = n_n7732 & nen3_36 & ~ndn3_36; - assign n6414 = n_n8153 & ndn3_17 & ~ndn3_18; - assign n6415 = n_n7685 & nen3_22 & ~ndn3_22; - assign n6416 = ~ndn3_15 & n_n9257 & ~nsr3_13; - assign n6417 = n_n8786 & (n6908 | (nen3_16 & ~ndn3_16)); - assign n6418 = n_n8416 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6419 = ndn3_2 & n_n8739 & ~ndn3_4; - assign n6420 = n_n6968 & nen3_39 & ~ndn3_39; - assign n6421 = n_n7866 & ~ndn3_9 & ndn3_7; - assign n6422 = ndn3_46 & ~ngfdn_3 & n_n8980; - assign n6423 = n_n7424 & ndn3_9 & ~ndn3_11; - assign n6424 = n_n9342 & ndn3_19 & ~ndn3_21; - assign n6425 = n_n9338 & ~ndn3_28 & nen3_28; - assign n6426 = ndn3_44 & n_n8989 & ~ndn3_46; - assign n6427 = n_n7920 & ndn3_42 & ~ndn3_44; - assign n6428 = nen3_34 & ~ndn3_34 & n_n9159; - assign n6429 = ~ndn3_36 & n_n7831 & nen3_36; - assign n6430 = n_n8984 & ndn3_17 & ~ndn3_18; - assign n6431 = n_n7225 & nen3_22 & ~ndn3_22; - assign n6432 = n_n8833 & ~nsr3_13 & ~ndn3_15; - assign n6433 = (n7048 | n7049) & (n7055 | n7056); - assign n6434 = n4966 & ((n5007 & n5008) | (n4969_1 & (~n5007 ^ ~n5008))); - assign n6435 = n_n8375 & ((nen3_16 & ~ndn3_16) | n6908); - assign n6436 = n_n7956 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6437 = ndn3_2 & n_n9023 & ~ndn3_4; - assign n6438 = ~ndn3_39 & nen3_39 & n_n8095; - assign n6439 = ndn3_7 & ~ndn3_9 & n_n7955; - assign n6440 = ndn3_46 & ~ngfdn_3 & n_n7947; - assign n6441 = ~ndn3_11 & ndn3_9 & n_n7954; - assign n6442 = n_n9021 & ndn3_19 & ~ndn3_21; - assign n6443 = nen3_28 & n_n9618 & ~ndn3_28; - assign n6444 = ndn3_44 & n_n7948 & ~ndn3_46; - assign n6445 = n_n7949 & ndn3_42 & ~ndn3_44; - assign n6446 = nen3_34 & n_n8891 & ~ndn3_34; - assign n6447 = ~ndn3_36 & nen3_36 & n_n7950; - assign n6448 = ~ndn3_18 & ndn3_17 & n_n7951; - assign n6449 = n_n8843 & nen3_22 & ~ndn3_22; - assign n6450 = ~ndn3_15 & n_n7953 & ~nsr3_13; - assign n6451 = n_n7696 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6452 = n_n7695 & ((~ndn3_17 & ndn3_16) | n6900); - assign n6453 = ndn3_4 & ~ndn3_7 & n_n9302; - assign n6454 = n_n7694 & ndn3_11 & ~ndn3_12; - assign n6455 = ndn3_40 & ~ndn3_42 & n_n8326; - assign n6456 = ndn3_26 & ~ndn3_27 & n_n8854; - assign n6457 = ndn3_46 & ~ngfdn_3 & n_n7691; - assign n6458 = ~ndn3_16 & nen3_16 & n_n8659; - assign n6459 = ~ndn3_32 & ndn3_29 & n_n7693; - assign n6460 = ~ndn3_40 & n_n8410 & ndn3_39; - assign n6461 = ~ndn3_21 & n_n8599 & ndn3_19; - assign n6462 = n_n8697 & ~ndn3_25 & ndn3_22; - assign n6463 = ndn3_44 & n_n9518 & ~ndn3_46; - assign n6464 = n_n7952 & ndn3_17 & ~ndn3_18; - assign n6465 = n_n9347 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6466 = n_n9346 & (n6900 | (~ndn3_17 & ndn3_16)); - assign n6467 = n_n9348 & ~ndn3_7 & ndn3_4; - assign n6468 = n_n9345 & ndn3_11 & ~ndn3_12; - assign n6469 = ndn3_40 & n_n9335 & ~ndn3_42; - assign n6470 = ndn3_26 & n_n9339 & ~ndn3_27; - assign n6471 = ndn3_46 & ~ngfdn_3 & n_n9333; - assign n6472 = n_n9344 & nen3_16 & ~ndn3_16; - assign n6473 = ~ndn3_32 & ndn3_29 & n_n9337; - assign n6474 = ~ndn3_40 & ndn3_39 & n_n9455; - assign n6475 = ~ndn3_21 & n_n9341 & ndn3_19; - assign n6476 = n_n9340 & ~ndn3_25 & ndn3_22; - assign n6477 = ndn3_44 & n_n9334 & ~ndn3_46; - assign n6478 = ~ndn3_18 & ndn3_17 & n_n9343; - assign n6479 = ~preset & n_n9267 & (~ndn3_9 | ndn3_11); - assign n6480 = ~preset & n4847 & (~n4969_1 ^ ~n4970); - assign n6481 = n_n9602 & (n6908 | (nen3_16 & ~ndn3_16)); - assign n6482 = n_n9605 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6483 = n_n9606 & ~ndn3_4 & ndn3_2; - assign n6484 = n_n9591 & nen3_39 & ~ndn3_39; - assign n6485 = n_n9604 & ~ndn3_9 & ndn3_7; - assign n6486 = ndn3_46 & ~ngfdn_3 & n_n9588; - assign n6487 = n_n9603 & ndn3_9 & ~ndn3_11; - assign n6488 = ~ndn3_21 & n_n9598 & ndn3_19; - assign n6489 = nen3_28 & ~ndn3_28 & n_n9595; - assign n6490 = ndn3_44 & n_n9589 & ~ndn3_46; - assign n6491 = n_n9590 & ndn3_42 & ~ndn3_44; - assign n6492 = nen3_34 & ~ndn3_34 & n_n9593; - assign n6493 = ~ndn3_36 & nen3_36 & n_n9592; - assign n6494 = n_n9599 & ndn3_17 & ~ndn3_18; - assign n6495 = n_n9597 & nen3_22 & ~ndn3_22; - assign n6496 = ~ndn3_15 & n_n9601 & ~nsr3_13; - assign n6497 = n_n9269 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6498 = n_n9268 & (n6900 | (~ndn3_17 & ndn3_16)); - assign n6499 = n_n9270 & ~ndn3_7 & ndn3_4; - assign n6500 = ~ndn3_12 & n_n9267 & ndn3_11; - assign n6501 = ndn3_40 & n_n9260 & ~ndn3_42; - assign n6502 = ndn3_26 & n_n9596 & ~ndn3_27; - assign n6503 = ndn3_46 & ~ngfdn_3 & n_n9259; - assign n6504 = n_n9266 & nen3_16 & ~ndn3_16; - assign n6505 = ~ndn3_32 & ndn3_29 & n_n9263; - assign n6506 = ~ndn3_40 & ndn3_39 & n_n9261; - assign n6507 = ~ndn3_21 & n_n9265 & ndn3_19; - assign n6508 = n_n9264 & ~ndn3_25 & ndn3_22; - assign n6509 = ndn3_44 & n_n9470 & ~ndn3_46; - assign n6510 = n_n9600 & ndn3_17 & ~ndn3_18; - assign n6511 = n_n8377 & (n6908 | (nen3_16 & ~ndn3_16)); - assign n6512 = n_n9121 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6513 = n_n7881 & ~ndn3_4 & ndn3_2; - assign n6514 = n_n7874 & nen3_39 & ~ndn3_39; - assign n6515 = n_n7880 & ~ndn3_9 & ndn3_7; - assign n6516 = ndn3_46 & ~ngfdn_3 & n_n9458; - assign n6517 = n_n8051 & ndn3_9 & ~ndn3_11; - assign n6518 = n_n7876 & ndn3_19 & ~ndn3_21; - assign n6519 = nen3_28 & n_n9000 & ~ndn3_28; - assign n6520 = ndn3_44 & n_n8609 & ~ndn3_46; - assign n6521 = ~ndn3_44 & n_n7873 & ndn3_42; - assign n6522 = nen3_34 & n_n9327 & ~ndn3_34; - assign n6523 = ~ndn3_36 & nen3_36 & n_n7980; - assign n6524 = ~ndn3_18 & n_n7877 & ndn3_17; - assign n6525 = n_n7875 & nen3_22 & ~ndn3_22; - assign n6526 = n_n7879 & ~nsr3_13 & ~ndn3_15; - assign n6527 = n4965 & ((n4978 & n4979_1) | (n4972 & (~n4978 ^ ~n4979_1))); - assign n6528 = (n6922 | n6923) & (n6929 | n6930); - assign n6529 = n_n9404 & ((nen3_16 & ~ndn3_16) | n6908); - assign n6530 = n_n9407 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6531 = ndn3_2 & n_n9408 & ~ndn3_4; - assign n6532 = n_n9393 & nen3_39 & ~ndn3_39; - assign n6533 = ndn3_7 & ~ndn3_9 & n_n9406; - assign n6534 = n_n9390 & ~ngfdn_3 & ndn3_46; - assign n6535 = n_n9405 & ndn3_9 & ~ndn3_11; - assign n6536 = ~ndn3_21 & n_n9400 & ndn3_19; - assign n6537 = nen3_28 & ~ndn3_28 & n_n9397; - assign n6538 = ndn3_44 & n_n9391 & ~ndn3_46; - assign n6539 = n_n9392 & ndn3_42 & ~ndn3_44; - assign n6540 = nen3_34 & n_n9395 & ~ndn3_34; - assign n6541 = ~ndn3_36 & nen3_36 & n_n9394; - assign n6542 = ~ndn3_18 & n_n9401 & ndn3_17; - assign n6543 = ~ndn3_22 & nen3_22 & n_n9399; - assign n6544 = n_n9403 & ~nsr3_13 & ~ndn3_15; - assign n6545 = (n6964 | n6965) & (n6971 | n6972); - assign n6546 = n4973 & ((n4981 & n4982) | (n4955 & (~n4981 ^ ~n4982))); - assign n6547 = n_n7742 & (n6908 | (nen3_16 & ~ndn3_16)); - assign n6548 = n_n7837 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6549 = ndn3_2 & ~ndn3_4 & n_n7744; - assign n6550 = ~ndn3_39 & nen3_39 & n_n7734; - assign n6551 = ndn3_7 & ~ndn3_9 & n_n8053; - assign n6552 = n_n8135 & ~ngfdn_3 & ndn3_46; - assign n6553 = n_n7743 & ndn3_9 & ~ndn3_11; - assign n6554 = n_n7741 & ndn3_19 & ~ndn3_21; - assign n6555 = nen3_28 & n_n7738 & ~ndn3_28; - assign n6556 = ndn3_44 & n_n8247 & ~ndn3_46; - assign n6557 = ~ndn3_44 & n_n9059 & ndn3_42; - assign n6558 = nen3_34 & n_n7736 & ~ndn3_34; - assign n6559 = ~ndn3_36 & n_n7735 & nen3_36; - assign n6560 = ~ndn3_18 & n_n9141 & ndn3_17; - assign n6561 = ~ndn3_22 & nen3_22 & n_n7740; - assign n6562 = ~ndn3_15 & n_n9189 & ~nsr3_13; - assign n6563 = n_n7655 & ((nen3_16 & ~ndn3_16) | n6908); - assign n6564 = n_n7657 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6565 = n_n8770 & ~ndn3_4 & ndn3_2; - assign n6566 = ~ndn3_39 & nen3_39 & n_n7650; - assign n6567 = n_n8619 & ~ndn3_9 & ndn3_7; - assign n6568 = ndn3_46 & ~ngfdn_3 & n_n8862; - assign n6569 = ~ndn3_11 & ndn3_9 & n_n7656; - assign n6570 = ~ndn3_21 & n_n7654 & ndn3_19; - assign n6571 = nen3_28 & ~ndn3_28 & n_n7652; - assign n6572 = ndn3_44 & ~ndn3_46 & n_n8249; - assign n6573 = n_n9061 & ndn3_42 & ~ndn3_44; - assign n6574 = nen3_34 & ~ndn3_34 & n_n9075; - assign n6575 = ~ndn3_36 & n_n7651 & nen3_36; - assign n6576 = ~ndn3_18 & ndn3_17 & n_n9015; - assign n6577 = n_n7653 & nen3_22 & ~ndn3_22; - assign n6578 = ~ndn3_15 & n_n8260 & ~nsr3_13; - assign n6579 = n_n8641 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6580 = n_n9566 & (n6900 | (~ndn3_17 & ndn3_16)); - assign n6581 = n_n7511 & ~ndn3_7 & ndn3_4; - assign n6582 = n_n8075 & ndn3_11 & ~ndn3_12; - assign n6583 = ndn3_40 & ~ndn3_42 & n_n8477; - assign n6584 = ndn3_26 & ~ndn3_27 & n_n7728; - assign n6585 = n_n8670 & ~ngfdn_3 & ndn3_46; - assign n6586 = ~ndn3_16 & nen3_16 & n_n8210; - assign n6587 = n_n8526 & ndn3_29 & ~ndn3_32; - assign n6588 = ~ndn3_40 & n_n7995 & ndn3_39; - assign n6589 = n_n7510 & ndn3_19 & ~ndn3_21; - assign n6590 = n_n9522 & ~ndn3_25 & ndn3_22; - assign n6591 = ndn3_44 & n_n7670 & ~ndn3_46; - assign n6592 = n_n7661 & ndn3_17 & ~ndn3_18; - assign n6593 = n_n9052 & (n6899 | (nen3_22 & ~ndn3_22)); - assign n6594 = n_n9051 & ((~ndn3_17 & ndn3_16) | n6900); - assign n6595 = n_n9053 & ~ndn3_7 & ndn3_4; - assign n6596 = n_n9050 & ndn3_11 & ~ndn3_12; - assign n6597 = ndn3_40 & n_n9043 & ~ndn3_42; - assign n6598 = ndn3_26 & n_n9368 & ~ndn3_27; - assign n6599 = ndn3_46 & ~ngfdn_3 & n_n9041; - assign n6600 = ~ndn3_16 & n_n9049 & nen3_16; - assign n6601 = ~ndn3_32 & ndn3_29 & n_n9046; - assign n6602 = ~ndn3_40 & n_n9044 & ndn3_39; - assign n6603 = n_n9048 & ndn3_19 & ~ndn3_21; - assign n6604 = n_n9047 & ~ndn3_25 & ndn3_22; - assign n6605 = ndn3_44 & n_n9042 & ~ndn3_46; - assign n6606 = n_n9319 & ndn3_17 & ~ndn3_18; - assign n6607 = n_n9321 & (n6908 | (nen3_16 & ~ndn3_16)); - assign n6608 = n_n9324 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6609 = ndn3_2 & n_n9325 & ~ndn3_4; - assign n6610 = ~ndn3_39 & n_n9311 & nen3_39; - assign n6611 = n_n9323 & ~ndn3_9 & ndn3_7; - assign n6612 = ndn3_46 & ~ngfdn_3 & n_n9308; - assign n6613 = n_n9322 & ndn3_9 & ~ndn3_11; - assign n6614 = n_n9317 & ndn3_19 & ~ndn3_21; - assign n6615 = nen3_28 & ~ndn3_28 & n_n9315; - assign n6616 = ndn3_44 & n_n9309 & ~ndn3_46; - assign n6617 = ~ndn3_44 & n_n9310 & ndn3_42; - assign n6618 = nen3_34 & ~ndn3_34 & n_n9313; - assign n6619 = ~ndn3_36 & nen3_36 & n_n9312; - assign n6620 = n_n9318 & ndn3_17 & ~ndn3_18; - assign n6621 = n_n9316 & nen3_22 & ~ndn3_22; - assign n6622 = n_n9320 & ~nsr3_13 & ~ndn3_15; - assign n6623 = n_n7553 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6624 = n_n9563 & ((~ndn3_17 & ndn3_16) | n6900); - assign n6625 = n_n7554 & ~ndn3_7 & ndn3_4; - assign n6626 = ~ndn3_12 & n_n8298 & ndn3_11; - assign n6627 = ndn3_40 & ~ndn3_42 & n_n8636; - assign n6628 = ndn3_26 & ~ndn3_27 & n_n7739; - assign n6629 = n_n9239 & ~ngfdn_3 & ndn3_46; - assign n6630 = ~ndn3_16 & nen3_16 & n_n8381; - assign n6631 = ~ndn3_32 & n_n7552 & ndn3_29; - assign n6632 = ~ndn3_40 & ndn3_39 & n_n7993; - assign n6633 = ~ndn3_21 & n_n8035 & ndn3_19; - assign n6634 = ndn3_22 & n_n8533 & ~ndn3_25; - assign n6635 = ndn3_44 & n_n8499 & ~ndn3_46; - assign n6636 = ~ndn3_18 & ndn3_17 & n_n9528; - assign n6637 = n_n9135 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6638 = n_n9134 & (n6900 | (~ndn3_17 & ndn3_16)); - assign n6639 = n_n9136 & ~ndn3_7 & ndn3_4; - assign n6640 = n_n9133 & ndn3_11 & ~ndn3_12; - assign n6641 = ndn3_40 & n_n9127 & ~ndn3_42; - assign n6642 = ndn3_26 & n_n9398 & ~ndn3_27; - assign n6643 = ndn3_46 & ~ngfdn_3 & n_n9125; - assign n6644 = ~ndn3_16 & nen3_16 & n_n9132; - assign n6645 = ~ndn3_32 & ndn3_29 & n_n9129; - assign n6646 = ~ndn3_40 & ndn3_39 & n_n9128; - assign n6647 = n_n9131 & ndn3_19 & ~ndn3_21; - assign n6648 = ndn3_22 & n_n9130 & ~ndn3_25; - assign n6649 = ndn3_44 & ~ndn3_46 & n_n9126; - assign n6650 = n_n9402 & ndn3_17 & ~ndn3_18; - assign n6651 = n_n8791 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6652 = n_n9008 & (n6900 | (~ndn3_17 & ndn3_16)); - assign n6653 = n_n7604 & ~ndn3_7 & ndn3_4; - assign n6654 = n_n8296 & ndn3_11 & ~ndn3_12; - assign n6655 = ndn3_40 & n_n7599 & ~ndn3_42; - assign n6656 = ndn3_26 & n_n7822 & ~ndn3_27; - assign n6657 = n_n9237 & ~ngfdn_3 & ndn3_46; - assign n6658 = ~ndn3_16 & nen3_16 & n_n8042; - assign n6659 = n_n7601 & ndn3_29 & ~ndn3_32; - assign n6660 = ~ndn3_40 & ndn3_39 & n_n8253; - assign n6661 = ~ndn3_21 & ndn3_19 & n_n7603; - assign n6662 = ndn3_22 & ~ndn3_25 & n_n7602; - assign n6663 = ndn3_44 & n_n7598 & ~ndn3_46; - assign n6664 = n_n8233 & ndn3_17 & ~ndn3_18; - assign n6665 = n_n7825 & ((nen3_16 & ~ndn3_16) | n6908); - assign n6666 = n_n7835 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6667 = ndn3_2 & ~ndn3_4 & n_n7827; - assign n6668 = ~ndn3_39 & n_n7819 & nen3_39; - assign n6669 = ndn3_7 & ~ndn3_9 & n_n7826; - assign n6670 = ndn3_46 & ~ngfdn_3 & n_n8898; - assign n6671 = n_n8617 & ndn3_9 & ~ndn3_11; - assign n6672 = ~ndn3_21 & n_n7823 & ndn3_19; - assign n6673 = nen3_28 & n_n7821 & ~ndn3_28; - assign n6674 = ndn3_44 & n_n9036 & ~ndn3_46; - assign n6675 = n_n9081 & ndn3_42 & ~ndn3_44; - assign n6676 = nen3_34 & n_n7820 & ~ndn3_34; - assign n6677 = ~ndn3_36 & nen3_36 & n_n7925; - assign n6678 = n_n7824 & ndn3_17 & ~ndn3_18; - assign n6679 = ~ndn3_22 & n_n8699 & nen3_22; - assign n6680 = n_n9186 & ~nsr3_13 & ~ndn3_15; - assign n6681 = n_n9499 & ((nen3_16 & ~ndn3_16) | n6908); - assign n6682 = n_n9502 & ((~ndn3_25 & ndn3_22) | n6909); - assign n6683 = ndn3_2 & n_n9503 & ~ndn3_4; - assign n6684 = n_n9488 & nen3_39 & ~ndn3_39; - assign n6685 = ndn3_7 & ~ndn3_9 & n_n9501; - assign n6686 = ndn3_46 & n_n9485 & ~ngfdn_3; - assign n6687 = n_n9500 & ndn3_9 & ~ndn3_11; - assign n6688 = n_n9495 & ndn3_19 & ~ndn3_21; - assign n6689 = nen3_28 & n_n9492 & ~ndn3_28; - assign n6690 = ndn3_44 & n_n9486 & ~ndn3_46; - assign n6691 = ~ndn3_44 & n_n9487 & ndn3_42; - assign n6692 = nen3_34 & ~ndn3_34 & n_n9490; - assign n6693 = ~ndn3_36 & n_n9489 & nen3_36; - assign n6694 = n_n9496 & ndn3_17 & ~ndn3_18; - assign n6695 = n_n9494 & nen3_22 & ~ndn3_22; - assign n6696 = n_n9498 & ~nsr3_13 & ~ndn3_15; - assign n6697 = n_n9181 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6698 = n_n9180 & (n6900 | (~ndn3_17 & ndn3_16)); - assign n6699 = ndn3_4 & ~ndn3_7 & n_n9182; - assign n6700 = n_n9179 & ndn3_11 & ~ndn3_12; - assign n6701 = ndn3_40 & n_n9172 & ~ndn3_42; - assign n6702 = ndn3_26 & ~ndn3_27 & n_n9493; - assign n6703 = ndn3_46 & ~ngfdn_3 & n_n9171; - assign n6704 = n_n9178 & nen3_16 & ~ndn3_16; - assign n6705 = ~ndn3_32 & ndn3_29 & n_n9175; - assign n6706 = ~ndn3_40 & ndn3_39 & n_n9173; - assign n6707 = n_n9177 & ndn3_19 & ~ndn3_21; - assign n6708 = n_n9176 & ~ndn3_25 & ndn3_22; - assign n6709 = ndn3_44 & n_n9473 & ~ndn3_46; - assign n6710 = n_n9497 & ndn3_17 & ~ndn3_18; - assign n6711 = n_n8789 & ((nen3_22 & ~ndn3_22) | n6899); - assign n6712 = n_n8961 & ((~ndn3_17 & ndn3_16) | n6900); - assign n6713 = ndn3_4 & n_n7643 & ~ndn3_7; - assign n6714 = n_n7642 & ndn3_11 & ~ndn3_12; - assign n6715 = ndn3_40 & n_n8328 & ~ndn3_42; - assign n6716 = ndn3_26 & ~ndn3_27 & n_n8856; - assign n6717 = n_n8188 & ~ngfdn_3 & ndn3_46; - assign n6718 = ~ndn3_16 & n_n8661 & nen3_16; - assign n6719 = ~ndn3_32 & ndn3_29 & n_n7649; - assign n6720 = ~ndn3_40 & n_n8552 & ndn3_39; - assign n6721 = n_n8058 & ndn3_19 & ~ndn3_21; - assign n6722 = n_n7641 & ~ndn3_25 & ndn3_22; - assign n6723 = ndn3_44 & n_n7640 & ~ndn3_46; - assign n6724 = n_n7878 & ndn3_17 & ~ndn3_18; - assign n6725 = ~preset & n_n7726 & (~ndn3_39 | ndn3_40); - assign n6726 = ~ndn3_40 & ndn3_39 & ~preset & n_n7376; - assign n6727 = ~preset & n_n9260 & (ndn3_37 | nsr3_37); - assign n6728 = ~preset & n_n9172 & (ndn3_37 | nsr3_37); - assign n6729 = nsr3_14 & ~nsr3_13 & n_n8649; - assign n6730 = nsr3_20 & ndn3_17 & n_n8648; - assign n6731 = n_n8650 & nsr3_13 & ndn3_12; - assign n6732 = n_n8796 & ndn3_29 & nsr3_35; - assign n6733 = nen3_34 & n_n8647 & nsr3_37; - assign n6734 = ndn3_26 & n_n9242 & nsr3_30; - assign n6735 = n_n8646 & nsr3_38 & nen3_36; - assign n6736 = n_n9013 & nsr3_23 & ndn3_19; - assign n6737 = n_n7629 & ~nsr3_13 & nsr3_14; - assign n6738 = n_n7628 & ndn3_17 & nsr3_20; - assign n6739 = n_n7630 & nsr3_13 & ndn3_12; - assign n6740 = nsr3_35 & n_n8613 & ndn3_29; - assign n6741 = nen3_34 & n_n8875 & nsr3_37; - assign n6742 = ndn3_26 & nsr3_30 & n_n8141; - assign n6743 = n_n7627 & nsr3_38 & nen3_36; - assign n6744 = ndn3_19 & nsr3_23 & n_n7983; - assign n6745 = n_n9165 & ~nsr3_13 & nsr3_14; - assign n6746 = nsr3_20 & ndn3_17 & n_n9164; - assign n6747 = n_n9166 & nsr3_13 & ndn3_12; - assign n6748 = n_n9161 & ndn3_29 & nsr3_35; - assign n6749 = nen3_34 & n_n9160 & nsr3_37; - assign n6750 = ndn3_26 & nsr3_30 & n_n9162; - assign n6751 = n_n9578 & nsr3_38 & nen3_36; - assign n6752 = n_n9163 & nsr3_23 & ndn3_19; - assign n6753 = nsr3_14 & ~nsr3_13 & n_n8240; - assign n6754 = nsr3_20 & ndn3_17 & n_n8239; - assign n6755 = n_n8241 & nsr3_13 & ndn3_12; - assign n6756 = n_n8312 & ndn3_29 & nsr3_35; - assign n6757 = nen3_34 & n_n8236 & nsr3_37; - assign n6758 = ndn3_26 & n_n8237 & nsr3_30; - assign n6759 = nen3_36 & nsr3_38 & n_n8235; - assign n6760 = n_n8238 & nsr3_23 & ndn3_19; - assign n6761 = n_n8574 & ~nsr3_13 & nsr3_14; - assign n6762 = nsr3_20 & n_n8573 & ndn3_17; - assign n6763 = n_n8575 & nsr3_13 & ndn3_12; - assign n6764 = nsr3_35 & ndn3_29 & n_n8572; - assign n6765 = nen3_34 & n_n8571 & nsr3_37; - assign n6766 = ndn3_26 & nsr3_30 & n_n8970; - assign n6767 = n_n8570 & nsr3_38 & nen3_36; - assign n6768 = ndn3_19 & n_n9150 & nsr3_23; - assign n6769 = nsr3_14 & n_n9362 & ~nsr3_13; - assign n6770 = nsr3_20 & ndn3_17 & n_n9552; - assign n6771 = n_n9363 & nsr3_13 & ndn3_12; - assign n6772 = n_n9359 & ndn3_29 & nsr3_35; - assign n6773 = nen3_34 & n_n9358 & nsr3_37; - assign n6774 = ndn3_26 & nsr3_30 & n_n9360; - assign n6775 = n_n9357 & nsr3_38 & nen3_36; - assign n6776 = ndn3_19 & n_n9361 & nsr3_23; - assign n6777 = n_n9292 & ~nsr3_13 & nsr3_14; - assign n6778 = nsr3_20 & ndn3_17 & n_n9291; - assign n6779 = ndn3_12 & n_n9410 & nsr3_13; - assign n6780 = n_n9289 & ndn3_29 & nsr3_35; - assign n6781 = nen3_34 & n_n9539 & nsr3_37; - assign n6782 = ndn3_26 & n_n9290 & nsr3_30; - assign n6783 = n_n9296 & nsr3_38 & nen3_36; - assign n6784 = n_n9298 & nsr3_23 & ndn3_19; - assign n6785 = nsr3_14 & ~nsr3_13 & n_n8273; - assign n6786 = nsr3_20 & ndn3_17 & n_n8272; - assign n6787 = ndn3_12 & nsr3_13 & n_n8274; - assign n6788 = nsr3_35 & ndn3_29 & n_n8348; - assign n6789 = nen3_34 & n_n8269 & nsr3_37; - assign n6790 = ndn3_26 & n_n8270 & nsr3_30; - assign n6791 = nen3_36 & n_n8508 & nsr3_38; - assign n6792 = n_n8271 & nsr3_23 & ndn3_19; - assign n6793 = nsr3_14 & n_n9560 & ~nsr3_13; - assign n6794 = nsr3_20 & ndn3_17 & n_n9559; - assign n6795 = ndn3_12 & n_n9561 & nsr3_13; - assign n6796 = n_n9556 & ndn3_29 & nsr3_35; - assign n6797 = nen3_34 & n_n9555 & nsr3_37; - assign n6798 = ndn3_26 & n_n9557 & nsr3_30; - assign n6799 = nen3_36 & n_n9554 & nsr3_38; - assign n6800 = n_n9558 & nsr3_23 & ndn3_19; - assign n6801 = nsr3_14 & ~nsr3_13 & n_n9510; - assign n6802 = nsr3_20 & ndn3_17 & n_n7854; - assign n6803 = ndn3_12 & n_n8037 & nsr3_13; - assign n6804 = n_n7852 & ndn3_29 & nsr3_35; - assign n6805 = nen3_34 & nsr3_37 & n_n8756; - assign n6806 = ndn3_26 & nsr3_30 & n_n8972; - assign n6807 = n_n8171 & nsr3_38 & nen3_36; - assign n6808 = n_n7853 & nsr3_23 & ndn3_19; - assign n6809 = nsr3_14 & ~nsr3_13 & n_n7771; - assign n6810 = n_n7770 & ndn3_17 & nsr3_20; - assign n6811 = n_n7961 & nsr3_13 & ndn3_12; - assign n6812 = nsr3_35 & ndn3_29 & n_n9331; - assign n6813 = nen3_34 & n_n7768 & nsr3_37; - assign n6814 = ndn3_26 & nsr3_30 & n_n7769; - assign n6815 = nen3_36 & n_n8173 & nsr3_38; - assign n6816 = n_n8803 & nsr3_23 & ndn3_19; - assign n6817 = nsr3_14 & n_n8199 & ~nsr3_13; - assign n6818 = nsr3_20 & n_n9280 & ndn3_17; - assign n6819 = n_n8200 & nsr3_13 & ndn3_12; - assign n6820 = n_n8197 & ndn3_29 & nsr3_35; - assign n6821 = nen3_34 & n_n8710 & nsr3_37; - assign n6822 = ndn3_26 & nsr3_30 & n_n8366; - assign n6823 = nen3_36 & n_n8196 & nsr3_38; - assign n6824 = n_n8198 & nsr3_23 & ndn3_19; - assign n6825 = n_n9441 & ~nsr3_13 & nsr3_14; - assign n6826 = nsr3_20 & ndn3_17 & n_n9550; - assign n6827 = ndn3_12 & n_n9442 & nsr3_13; - assign n6828 = nsr3_35 & ndn3_29 & n_n9438; - assign n6829 = nen3_34 & n_n9437 & nsr3_37; - assign n6830 = ndn3_26 & nsr3_30 & n_n9439; - assign n6831 = n_n9436 & nsr3_38 & nen3_36; - assign n6832 = n_n9440 & nsr3_23 & ndn3_19; - assign n6833 = nsr3_14 & ~nsr3_13 & n_n7584; - assign n6834 = n_n8447 & ndn3_17 & nsr3_20; - assign n6835 = n_n8691 & nsr3_13 & ndn3_12; - assign n6836 = nsr3_35 & ndn3_29 & n_n8968; - assign n6837 = nen3_34 & n_n7582 & nsr3_37; - assign n6838 = ndn3_26 & n_n7583 & nsr3_30; - assign n6839 = n_n8016 & nsr3_38 & nen3_36; - assign n6840 = n_n7985 & nsr3_23 & ndn3_19; - assign n6841 = n_n7704 & ~nsr3_13 & nsr3_14; - assign n6842 = nsr3_20 & ndn3_17 & n_n8685; - assign n6843 = n_n8577 & nsr3_13 & ndn3_12; - assign n6844 = n_n9294 & ndn3_29 & nsr3_35; - assign n6845 = nen3_34 & nsr3_37 & n_n8118; - assign n6846 = ndn3_26 & n_n7702 & nsr3_30; - assign n6847 = n_n7701 & nsr3_38 & nen3_36; - assign n6848 = ndn3_19 & nsr3_23 & n_n7703; - assign n6849 = nsr3_14 & n_n8531 & ~nsr3_13; - assign n6850 = nsr3_20 & ndn3_17 & n_n8530; - assign n6851 = ndn3_12 & nsr3_13 & n_n8615; - assign n6852 = n_n9275 & ndn3_29 & nsr3_35; - assign n6853 = nen3_34 & n_n8529 & nsr3_37; - assign n6854 = ndn3_26 & n_n9244 & nsr3_30; - assign n6855 = n_n8528 & nsr3_38 & nen3_36; - assign n6856 = ndn3_19 & nsr3_23 & n_n8935; - assign n6857 = n6849 | n6850 | n6851 | n6852; - assign n6858 = n6853 | n6854 | n6855 | n6856; - assign n6859 = n6753 | n6754 | n6755 | n6756; - assign n6860 = n6757 | n6758 | n6759 | n6760; - assign n6861 = n6761 | n6762 | n6763 | n6764; - assign n6862 = n6765 | n6766 | n6767 | n6768; - assign n6863 = n6769 | n6770 | n6771 | n6772; - assign n6864 = n6773 | n6774 | n6775 | n6776; - assign n6865 = n6833 | n6834 | n6835 | n6836; - assign n6866 = n6837 | n6838 | n6839 | n6840; - assign n6867 = n6841 | n6842 | n6843 | n6844; - assign n6868 = n6845 | n6846 | n6847 | n6848; - assign n6869 = n6737 | n6738 | n6739 | n6740; - assign n6870 = n6741 | n6742 | n6743 | n6744; - assign n6871 = n6809 | n6810 | n6811 | n6812; - assign n6872 = n6813 | n6814 | n6815 | n6816; - assign n6873 = n6793 | n6794 | n6795 | n6796; - assign n6874 = n6797 | n6798 | n6799 | n6800; - assign n6875 = n6745 | n6746 | n6747 | n6748; - assign n6876 = n6749 | n6750 | n6751 | n6752; - assign n6877 = n6729 | n6730 | n6731 | n6732; - assign n6878 = n6733 | n6734 | n6735 | n6736; - assign n6879 = n6801 | n6802 | n6803 | n6804; - assign n6880 = n6805 | n6806 | n6807 | n6808; - assign n6881 = n6777 | n6778 | n6779 | n6780; - assign n6882 = n6781 | n6782 | n6783 | n6784; - assign n6883 = n6825 | n6826 | n6827 | n6828; - assign n6884 = n6829 | n6830 | n6831 | n6832; - assign n6885 = n6785 | n6786 | n6787 | n6788; - assign n6886 = n6789 | n6790 | n6791 | n6792; - assign n6887 = n6817 | n6818 | n6819 | n6820; - assign n6888 = n6821 | n6822 | n6823 | n6824; - assign n6889 = n6857 | n6858 | n6859 | n6860; - assign n6890 = n6861 | n6862 | n6863 | n6864; - assign n6891 = n6865 | n6866 | n6867 | n6868; - assign n6892 = n6869 | n6870 | n6871 | n6872; - assign n6893 = n6873 | n6874 | n6875 | n6876; - assign n6894 = n6877 | n6878 | n6879 | n6880; - assign n6895 = n6881 | n6882 | n6883 | n6884; - assign n6896 = n6885 | n6886 | n6887 | n6888; - assign n6897 = n6889 | n6890 | n6891 | n6892; - assign n6898 = n6893 | n6894 | n6895 | n6896; - assign n6899 = (~ndn3_9 & ndn3_7) | (ndn3_25 & ~ndn3_26); - assign n6900 = (ndn3_9 & ~ndn3_11) | (~nsr3_13 & ~ndn3_15); - assign n6901 = (n_n8779 & n4960) | (n_n7876 & n4961); - assign n6902 = (n_n7644 & n4958) | (n_n9000 & n4959_1); - assign n6903 = n6713 | n6714 | n6715 | n6716; - assign n6904 = n6717 | n6718 | n6719 | n6720; - assign n6905 = n6721 | n6722 | n6723 | n6724; - assign n6906 = n6905 | n6711 | n6712; - assign n6907 = n6901 | n6902 | n6903 | n6904; - assign n6908 = (~ndn3_19 & nen3_19) | (ndn3_11 & ~ndn3_12); - assign n6909 = (~ndn3_29 & ndn3_28) | (~ndn3_7 & ndn3_4); - assign n6910 = (n_n9230 & n4963) | (n_n7878 & n4964_1); - assign n6911 = n6514 | n6513 | (n_n8856 & n4962); - assign n6912 = n6515 | n6516 | n6517 | n6518; - assign n6913 = n6519 | n6520 | n6521 | n6522; - assign n6914 = n6523 | n6524 | n6525 | n6526; - assign n6915 = n6914 | n6511 | n6512; - assign n6916 = n6910 | n6911 | n6912 | n6913; - assign n6917 = (n_n9491 & n4963) | (n_n9497 & n4964_1); - assign n6918 = n6684 | n6683 | (n_n9493 & n4962); - assign n6919 = n6685 | n6686 | n6687 | n6688; - assign n6920 = n6689 | n6690 | n6691 | n6692; - assign n6921 = n6693 | n6694 | n6695 | n6696; - assign n6922 = n6921 | n6681 | n6682; - assign n6923 = n6917 | n6918 | n6919 | n6920; - assign n6924 = (n_n9495 & n4961) | (n_n9174 & n4960); - assign n6925 = (n_n9183 & n4958) | (n_n9492 & n4959_1); - assign n6926 = n6699 | n6700 | n6701 | n6702; - assign n6927 = n6703 | n6704 | n6705 | n6706; - assign n6928 = n6707 | n6708 | n6709 | n6710; - assign n6929 = n6928 | n6697 | n6698; - assign n6930 = n6924 | n6925 | n6926 | n6927; - assign n6931 = (n_n9232 & n4963) | (n_n8233 & n4964_1); - assign n6932 = n6668 | n6667 | (n_n7822 & n4962); - assign n6933 = n6669 | n6670 | n6671 | n6672; - assign n6934 = n6673 | n6674 | n6675 | n6676; - assign n6935 = n6677 | n6678 | n6679 | n6680; - assign n6936 = n6935 | n6665 | n6666; - assign n6937 = n6931 | n6932 | n6933 | n6934; - assign n6938 = (n_n7600 & n4960) | (n_n7823 & n4961); - assign n6939 = (n_n7821 & n4959_1) | (n_n8736 & n4958); - assign n6940 = n6653 | n6654 | n6655 | n6656; - assign n6941 = n6657 | n6658 | n6659 | n6660; - assign n6942 = n6661 | n6662 | n6663 | n6664; - assign n6943 = n6942 | n6651 | n6652; - assign n6944 = n6938 | n6939 | n6940 | n6941; - assign n6945 = (n_n9212 & n4960) | (n_n9400 & n4961); - assign n6946 = (n_n9137 & n4958) | (n_n9397 & n4959_1); - assign n6947 = n6639 | n6640 | n6641 | n6642; - assign n6948 = n6643 | n6644 | n6645 | n6646; - assign n6949 = n6647 | n6648 | n6649 | n6650; - assign n6950 = n6949 | n6637 | n6638; - assign n6951 = n6945 | n6946 | n6947 | n6948; - assign n6952 = (n_n9402 & n4964_1) | (n_n9396 & n4963); - assign n6953 = n6532 | n6531 | (n_n9398 & n4962); - assign n6954 = n6533 | n6534 | n6535 | n6536; - assign n6955 = n6537 | n6538 | n6539 | n6540; - assign n6956 = n6541 | n6542 | n6543 | n6544; - assign n6957 = n6956 | n6529 | n6530; - assign n6958 = n6952 | n6953 | n6954 | n6955; - assign n6959 = (n_n7741 & n4961) | (n_n8638 & n4960); - assign n6960 = (n_n8009 & n4958) | (n_n7738 & n4959_1); - assign n6961 = n6625 | n6626 | n6627 | n6628; - assign n6962 = n6629 | n6630 | n6631 | n6632; - assign n6963 = n6633 | n6634 | n6635 | n6636; - assign n6964 = n6963 | n6623 | n6624; - assign n6965 = n6959 | n6960 | n6961 | n6962; - assign n6966 = (n_n7737 & n4963) | (n_n9528 & n4964_1); - assign n6967 = n6550 | n6549 | (n_n7739 & n4962); - assign n6968 = n6551 | n6552 | n6553 | n6554; - assign n6969 = n6555 | n6556 | n6557 | n6558; - assign n6970 = n6559 | n6560 | n6561 | n6562; - assign n6971 = n6970 | n6547 | n6548; - assign n6972 = n6966 | n6967 | n6968 | n6969; - assign n6973 = (n_n9317 & n4961) | (n_n9045 & n4960); - assign n6974 = (n_n9315 & n4959_1) | (n_n9054 & n4958); - assign n6975 = n6595 | n6596 | n6597 | n6598; - assign n6976 = n6599 | n6600 | n6601 | n6602; - assign n6977 = n6603 | n6604 | n6605 | n6606; - assign n6978 = n6977 | n6593 | n6594; - assign n6979 = n6973 | n6974 | n6975 | n6976; - assign n6980 = (n_n9314 & n4963) | (n_n9319 & n4964_1); - assign n6981 = n6610 | n6609 | (n_n9368 & n4962); - assign n6982 = n6611 | n6612 | n6613 | n6614; - assign n6983 = n6615 | n6616 | n6617 | n6618; - assign n6984 = n6619 | n6620 | n6621 | n6622; - assign n6985 = n6984 | n6607 | n6608; - assign n6986 = n6980 | n6981 | n6982 | n6983; - assign n6987 = (n_n7509 & n4960) | (n_n7654 & n4961); - assign n6988 = (n_n8011 & n4958) | (n_n7652 & n4959_1); - assign n6989 = n6581 | n6582 | n6583 | n6584; - assign n6990 = n6585 | n6586 | n6587 | n6588; - assign n6991 = n6589 | n6590 | n6591 | n6592; - assign n6992 = n6991 | n6579 | n6580; - assign n6993 = n6987 | n6988 | n6989 | n6990; - assign n6994 = (n_n8033 & n4963) | (n_n7661 & n4964_1); - assign n6995 = n6566 | n6565 | (n_n7728 & n4962); - assign n6996 = n6567 | n6568 | n6569 | n6570; - assign n6997 = n6571 | n6572 | n6573 | n6574; - assign n6998 = n6575 | n6576 | n6577 | n6578; - assign n6999 = n6998 | n6563 | n6564; - assign n7000 = n6994 | n6995 | n6996 | n6997; - assign n7001 = (n_n9262 & n4960) | (n_n9598 & n4961); - assign n7002 = (n_n9595 & n4959_1) | (n_n9271 & n4958); - assign n7003 = n6499 | n6500 | n6501 | n6502; - assign n7004 = n6503 | n6504 | n6505 | n6506; - assign n7005 = n6507 | n6508 | n6509 | n6510; - assign n7006 = n7005 | n6497 | n6498; - assign n7007 = n7001 | n7002 | n7003 | n7004; - assign n7008 = (n_n9594 & n4963) | (n_n9600 & n4964_1); - assign n7009 = n6484 | n6483 | (n_n9596 & n4962); - assign n7010 = n6485 | n6486 | n6487 | n6488; - assign n7011 = n6489 | n6490 | n6491 | n6492; - assign n7012 = n6493 | n6494 | n6495 | n6496; - assign n7013 = n7012 | n6481 | n6482; - assign n7014 = n7008 | n7009 | n7010 | n7011; - assign n7015 = (n_n7686 & n4961) | (n_n7665 & n4960); - assign n7016 = (n_n7683 & n4959_1) | (n_n8110 & n4958); - assign n7017 = n6389 | n6390 | n6391 | n6392; - assign n7018 = n6393 | n6394 | n6395 | n6396; - assign n7019 = n6397 | n6398 | n6399 | n6400; - assign n7020 = n7019 | n6387 | n6388; - assign n7021 = n7015 | n7016 | n7017 | n7018; - assign n7022 = (n_n8586 & n4963) | (n_n7687 & n4964_1); - assign n7023 = n6404 | n6403 | (n_n7684 & n4962); - assign n7024 = n6405 | n6406 | n6407 | n6408; - assign n7025 = n6409 | n6410 | n6411 | n6412; - assign n7026 = n6413 | n6414 | n6415 | n6416; - assign n7027 = n7026 | n6401 | n6402; - assign n7028 = n7022 | n7023 | n7024 | n7025; - assign n7029 = (n_n9342 & n4961) | (n_n9336 & n4960); - assign n7030 = (n_n9338 & n4959_1) | (n_n9349 & n4958); - assign n7031 = n6467 | n6468 | n6469 | n6470; - assign n7032 = n6471 | n6472 | n6473 | n6474; - assign n7033 = n6475 | n6476 | n6477 | n6478; - assign n7034 = n7033 | n6465 | n6466; - assign n7035 = n7029 | n7030 | n7031 | n7032; - assign n7036 = (n_n6976 & n4963) | (n_n9343 & n4964_1); - assign n7037 = n6420 | n6419 | (n_n9339 & n4962); - assign n7038 = n6421 | n6422 | n6423 | n6424; - assign n7039 = n6425 | n6426 | n6427 | n6428; - assign n7040 = n6429 | n6430 | n6431 | n6432; - assign n7041 = n7040 | n6417 | n6418; - assign n7042 = n7036 | n7037 | n7038 | n7039; - assign n7043 = (n_n9021 & n4961) | (n_n7692 & n4960); - assign n7044 = (n_n7697 & n4958) | (n_n9618 & n4959_1); - assign n7045 = n6453 | n6454 | n6455 | n6456; - assign n7046 = n6457 | n6458 | n6459 | n6460; - assign n7047 = n6461 | n6462 | n6463 | n6464; - assign n7048 = n7047 | n6451 | n6452; - assign n7049 = n7043 | n7044 | n7045 | n7046; - assign n7050 = (n_n8966 & n4963) | (n_n7952 & n4964_1); - assign n7051 = n6438 | n6437 | (n_n8854 & n4962); - assign n7052 = n6439 | n6440 | n6441 | n6442; - assign n7053 = n6443 | n6444 | n6445 | n6446; - assign n7054 = n6447 | n6448 | n6449 | n6450; - assign n7055 = n7054 | n6435 | n6436; - assign n7056 = n7050 | n7051 | n7052 | n7053; - assign n7057 = (n_n7762 & n4961) | (n_n7709 & n4960); - assign n7058 = (n_n8852 & n4959_1) | (n_n8986 & n4958); - assign n7059 = n6375 | n6376 | n6377 | n6378; - assign n7060 = n6379 | n6380 | n6381 | n6382; - assign n7061 = n6383 | n6384 | n6385 | n6386; - assign n7062 = n7061 | n6373 | n6374; - assign n7063 = n7057 | n7058 | n7059 | n7060; - assign n7064 = (n_n7763 & n4964_1) | (n_n7759 & n4963); - assign n7065 = n6360 | n6359 | (n_n7760 & n4962); - assign n7066 = n6361 | n6362 | n6363 | n6364; - assign n7067 = n6365 | n6366 | n6367 | n6368; - assign n7068 = n6369 | n6370 | n6371 | n6372; - assign n7069 = n7068 | n6357 | n6358; - assign n7070 = n7064 | n7065 | n7066 | n7067; - assign n7071 = (n_n8408 & n4963) | (n_n7811 & n4964_1); - assign n7072 = n6325 | n6324 | (n_n7809 & n4962); - assign n7073 = n6326 | n6327 | n6328 | n6329; - assign n7074 = n6330 | n6331 | n6332 | n6333; - assign n7075 = n6334 | n6335 | n6336 | n6337; - assign n7076 = n7075 | n6322 | n6323; - assign n7077 = n7071 | n7072 | n7073 | n7074; - assign n7078 = (n_n8088 & n4960) | (n_n7810 & n4961); - assign n7079 = (n_n8108 & n4958) | (n_n8473 & n4959_1); - assign n7080 = n6340 | n6341 | n6342 | n6343; - assign n7081 = n6344 | n6345 | n6346 | n6347; - assign n7082 = n6348 | n6349 | n6350 | n6351; - assign n7083 = n7082 | n6338 | n6339; - assign n7084 = n7078 | n7079 | n7080 | n7081; - assign n7085 = n_n9248 & ~n_n7306; - assign n7086 = (nsr3_38 & nen3_36) | (nsr3_23 & ndn3_19); - assign n7087 = (nsr3_37 & nen3_34) | (nsr3_30 & ndn3_26); - assign n7088 = (ndn3_29 & nsr3_35) | (ndn3_17 & nsr3_20); - assign n7089 = n4974_1 & n_n9198; - assign n7090 = n6305 | n6303 | n6304; - assign n7091 = n6306 | n6307 | n6308 | n6309; - assign n7092 = n6298 | n6296 | n6297; - assign n7093 = n6299 | n6300 | n6301 | n6302; - assign n7094 = n6284 | n6282 | n6283; - assign n7095 = n6285 | n6286 | n6287 | n6288; - assign n7096 = n6263 | n6261 | n6262; - assign n7097 = n6264 | n6265 | n6266 | n6267; - assign n7098 = n6256 | n6254 | n6255; - assign n7099 = n6257 | n6258 | n6259 | n6260; - assign n7100 = n6235 | n6233 | n6234; - assign n7101 = n6236 | n6237 | n6238 | n6239; - assign n7102 = n6242 | n6240 | n6241; - assign n7103 = n6243 | n6244 | n6245 | n6246; - assign n7104 = n6228 | n6226 | n6227; - assign n7105 = n6229 | n6230 | n6231 | n6232; - assign n7106 = n6249 | n6247 | n6248; - assign n7107 = n6250 | n6251 | n6252 | n6253; - assign n7108 = n6270 | n6268 | n6269; - assign n7109 = n6271 | n6272 | n6273 | n6274; - assign n7110 = n6277 | n6275 | n6276; - assign n7111 = n6278 | n6279 | n6280 | n6281; - assign n7112 = n6221 | n6219 | n6220; - assign n7113 = n6222 | n6223 | n6224 | n6225; - assign n7114 = n6291 | n6289 | n6290; - assign n7115 = n6292 | n6293 | n6294 | n6295; - assign n7116 = n6214 | n6212 | n6213; - assign n7117 = n6215 | n6216 | n6217 | n6218; - assign n7118 = n6207 | n6205 | n6206; - assign n7119 = n6208 | n6209 | n6210 | n6211; - assign n7120 = n6201 | n6202 | n6203 | n6204; - assign n7121 = n5001 & ~n_n8557 & n4856; - assign n7122 = n4856 & n_n8557; - assign n7123 = n_n9638 & n4856 & (n7094 | n7095); - assign n7124 = (n_n9225 & n4960) | (n_n7888 & n4961); - assign n7125 = (n_n7887 & n4959_1) | (n_n7850 & n4958); - assign n7126 = n6165 | n6166 | n6167 | n6168; - assign n7127 = n6169 | n6170 | n6171 | n6172; - assign n7128 = n6173 | n6174 | n6175 | n6176; - assign n7129 = n7128 | n6163 | n6164; - assign n7130 = n7124 | n7125 | n7126 | n7127; - assign n7131 = (n_n7886 & n4963) | (n_n7889 & n4964_1); - assign n7132 = n6150 | n6149 | (n_n9520 & n4962); - assign n7133 = n6151 | n6152 | n6153 | n6154; - assign n7134 = n6155 | n6156 | n6157 | n6158; - assign n7135 = n6159 | n6160 | n6161 | n6162; - assign n7136 = n7135 | n6147 | n6148; - assign n7137 = n7131 | n7132 | n7133 | n7134; - assign n7138 = (n_n8519 & n4964_1) | (n_n8002 & n4963); - assign n7139 = n6132 | n6131 | (n_n8004 & n4962); - assign n7140 = n6133 | n6134 | n6135 | n6136; - assign n7141 = n6137 | n6138 | n6139 | n6140; - assign n7142 = n6141 | n6142 | n6143 | n6144; - assign n7143 = n7142 | n6129 | n6130; - assign n7144 = n7138 | n7139 | n7140 | n7141; - assign n7145 = (n_n8005 & n4961) | (n_n9223 & n4960); - assign n7146 = (n_n8003 & n4959_1) | (n_n8482 & n4958); - assign n7147 = n6117 | n6118 | n6119 | n6120; - assign n7148 = n6121 | n6122 | n6123 | n6124; - assign n7149 = n6125 | n6126 | n6127 | n6128; - assign n7150 = n7149 | n6115 | n6116; - assign n7151 = n7145 | n7146 | n7147 | n7148; - assign n7152 = (n_n8139 & n4960) | (n_n7933 & n4961); - assign n7153 = (n_n8000 & n4958) | (n_n7931 & n4959_1); - assign n7154 = n6087 | n6088 | n6089_1 | n6090; - assign n7155 = n6091 | n6092 | n6093 | n6094_1; - assign n7156 = n6095 | n6096 | n6097 | n6098; - assign n7157 = n7156 | n6085 | n6086; - assign n7158 = n7152 | n7153 | n7154 | n7155; - assign n7159 = (n_n8106 & n4964_1) | (n_n7930 & n4963); - assign n7160 = n6102 | n6101 | (n_n7932 & n4962); - assign n7161 = n6103 | n6104 | n6105 | n6106; - assign n7162 = n6107 | n6108 | n6109 | n6110; - assign n7163 = n6111 | n6112 | n6113 | n6114; - assign n7164 = n7163 | n6099 | n6100; - assign n7165 = n7159 | n7160 | n7161 | n7162; - assign n7166 = ~n_n8869 & ~n_n8603 & ~n_n8798; - assign n7167 = ~n4924_1 & n4953 & (n_n8933 ^ n5000); - assign n7168 = n7166 & (n_n8911 ^ (n_n8933 | n5000)); - assign n7169 = ~n4927 & n7167; - assign n7170 = ~n4928 & n7168 & (~n_n8993 ^ ~n5005); - assign n7171 = ~n4943 & n7169 & (~n_n8561 ^ ~n4999_1); - assign n7172 = ~n4947 & n7171; - assign n7173 = ~n4899_1 & n7170 & (~n_n8913 ^ ~n4968); - assign n7174 = preset | ~n_n9198 | ~n4967 | ~n4974_1; - assign n7175 = n_n9434 & n4856 & (n7096 | n7097); - assign n7176 = ~n4967 & ~preset; - assign n7177 = pdn | preset | (nsr3_23 & ~nak3_13); - assign n7178 = pdn | preset | (nsr3_13 & ~nak3_13); - assign n7179 = pdn | preset | (nsr3_38 & ~nak3_13); - assign n7180 = n_n8549 & n4856 & (n7090 | n7091); - assign n7181 = n4856 & (n_n8652 ? ~n4910 : (n4910 & n5001)); - assign n7182 = ~n_n8707 & (n4911 ^ (n7104 | n7105)); - assign n7183 = n_n8707 & n4856 & (~n4911 ^ n4913); - assign n7184 = n7183 | (n4856 & n5001 & n7182); - assign n7185 = pdn | preset | (nsr3_30 & ~ndn3_26); - assign n7186 = n_n8354 & n4856 & (n7116 | n7117); - assign n7187 = n_n9512 & n4856 & (n7098 | n7099); - assign n7188 = n5001 & n4856 & n4920; - assign n7189 = n4856 & n_n9512; - assign n7190 = n5626 | (~preset & n_n9512 & ~n5001); - assign n7191 = pdn | preset | (nsr3_35 & ~nak3_13); - assign n7192 = n_n9416 & n4856 & (n7108 | n7109); - assign n7193 = pdn | (~nak3_13 & (preset | nsr3_14)); - assign n7194 = ~n_n8603 & ~n5975 & (~n4975 | ~n7176); - assign n7195 = ~n6866 & ~n_n8603 & ~n6865; - assign n7196 = ~n4856 & n_n8603; - assign n7197 = ~n4898 & (n7194 | n7195); - assign n7198 = n4974_1 & n4967 & ~preset & n_n9198; - assign n7199 = n_n8449 & n4856 & (n7092 | n7093); - assign n7200 = n_n9448 & n4856 & (n7114 | n7115); - assign n7201 = n_n9537 & n4856 & (n7110 | n7111); - assign n7202 = n_n8929 & ~preset; - assign n7203 = ~preset & (n6897 | n6898); - assign n7204 = ~n_n9284 & (n4909_1 ^ (n7102 | n7103)); - assign n7205 = n_n9284 & n4856 & (~n4909_1 ^ n4936); - assign n7206 = n7205 | (n4856 & n5001 & n7204); - assign n7207 = n_n8821 & n4856 & (n7112 | n7113); - assign n7208 = ~n_n9353 & (n4912 ^ (n7106 | n7107)); - assign n7209 = n_n9353 & n4856 & (~n4912 ^ n4938); - assign n7210 = pdn | preset | (nsr3_37 & ~nen3_34); - assign n7211 = pdn | preset | (~nak3_13 & nsr3_20); - assign n7212 = n_n8419 & n4856 & (n7118 | n7119); - always @ (posedge clock) begin - n_n9280 <= n491; - n_n9172 <= n496; - n_n9260 <= n501; - n_n7726 <= n506; - n_n8270 <= n511; - n_n8196 <= n516; - n_n9150 <= n521; - n_n9267 <= n526; - n_n7779 <= n531; - n_n9503 <= n536; - n_n8150 <= n541; - n_n9401 <= n546; - n_n7341 <= n551; - n_n9180 <= n556; - n_n8592 <= n561; - n_n8871 <= n566; - n_n7252 <= n571; - n_n7271 <= n576; - n_n6991 <= n581; - n_n8557 <= n586; - n_n7707 <= n591; - n_n7552 <= n596; - ndn3_23 <= n601; - n_n9548 <= n606; - n_n9467 <= n611; - n_n8002 <= n616; - n_n6950 <= n621; - n_n8930 <= n626; - n_n7244 <= n631; - n_n7819 <= n636; - n_n8883 <= n641; - n_n7709 <= n646; - n_n9580 <= n651; - n_n9130 <= n656; - n_n9486 <= n661; - n_n9235 <= n666; - n_n7522 <= n671; - n_n7373 <= n676; - n_n9085 <= n681; - n_n9638 <= n686; - n_n7452 <= n691; - n_n8775 <= n696; - n_n7654 <= n701; - n_n8410 <= n706; - n_n8208 <= n711; - n_n8377 <= n716; - n_n7558 <= n721; - n_n7599 <= n726; - n_n8225 <= n731; - n_n8202 <= n736; - n_n7670 <= n741; - n_n7888 <= n746; - n_n7889 <= n751; - n_n8597 <= n756; - n_n8152 <= n761; - n_n8394 <= n766; - n_n7812 <= n771; - n_n7816 <= n776; - n_n9141 <= n781; - n_n7332 <= n786; - n_n8758 <= n791; - n_n7765 <= n796; - n_n7877 <= n801; - n_n7814 <= n806; - n_n9008 <= n811; - n_n7581 <= n816; - n_n7376 <= n821; - n_n7970 <= n826; - pover_0_0_ <= n831; - n_n8599 <= n835; - n_n8227 <= n840; - n_n9442 <= n845; - n_n9485 <= n850; - n_n7148 <= n855; - n_n9311 <= n860; - n_n9273 <= n865; - ndn3_9 <= n870; - n_n8613 <= n875; - n_n8533 <= n880; - n_n8699 <= n885; - n_n8609 <= n890; - n_n8308 <= n895; - n_n8655 <= n900; - n_n8981 <= n905; - n_n7583 <= n910; - n_n9198 <= n915; - n_n9602 <= n920; - n_n8786 <= n925; - n_n9598 <= n930; - n_n7738 <= n935; - n_n8573 <= n940; - n_n9473 <= n945; - n_n9000 <= n950; - n_n8001 <= n955; - n_n9554 <= n960; - n_n8508 <= n965; - n_n9635 <= n970; - n_n7190 <= n975; - n_n8702 <= n980; - n_n9106 <= n985; - n_n7409 <= n990; - n_n9437 <= n995; - n_n9052 <= n1000; - n_n8647 <= n1005; - n_n9265 <= n1010; - n_n7179 <= n1015; - ndn3_13 <= n1020; - ndn3_17 <= n1025; - ndn3_25 <= n1030; - ndn3_29 <= n1035; - n_n9539 <= n1040; - n_n7953 <= n1045; - n_n8488 <= n1050; - nen3_22 <= n1055; - n_n9438 <= n1060; - n_n8132 <= n1065; - n_n8661 <= n1070; - n_n7759 <= n1075; - n_n8333 <= n1080; - n_n9399 <= n1085; - n_n7798 <= n1090; - n_n9434 <= n1095; - n_n7910 <= n1100; - n_n9528 <= n1105; - n_n7850 <= n1110; - n_n8251 <= n1115; - n_n7937 <= n1120; - n_n8482 <= n1125; - n_n9290 <= n1130; - n_n8007 <= n1135; - n_n7556 <= n1140; - n_n9064 <= n1145; - n_n9398 <= n1150; - n_n9412 <= n1155; - n_n9361 <= n1160; - n_n9304 <= n1165; - n_n7651 <= n1170; - n_n7712 <= n1175; - n_n7735 <= n1180; - n_n7934 <= n1185; - n_n7811 <= n1190; - n_n8053 <= n1195; - n_n9015 <= n1200; - n_n8066 <= n1205; - n_n9518 <= n1210; - n_n8091 <= n1215; - n_n9257 <= n1220; - n_n8175 <= n1225; - n_n8491 <= n1230; - n_n8114 <= n1235; - n_n7951 <= n1240; - n_n8913 <= n1245; - n_n8035 <= n1250; - n_n8631 <= n1255; - n_n8243 <= n1260; - n_n7857 <= n1265; - ngfdn_3 <= n1270; - n_n7791 <= n1275; - n_n9175 <= n1280; - n_n9588 <= n1285; - n_n9049 <= n1290; - n_n9483 <= n1295; - n_n9410 <= n1300; - n_n7691 <= n1305; - n_n7740 <= n1310; - n_n7602 <= n1315; - n_n7783 <= n1320; - n_n7948 <= n1325; - n_n7054 <= n1330; - n_n9343 <= n1335; - n_n9400 <= n1340; - nsr1_2 <= n1345; - n_n9127 <= n1350; - n_n8531 <= n1355; - n_n9335 <= n1360; - n_n7324 <= n1365; - n_n9611 <= n1370; - n_n8112 <= n1375; - n_n9406 <= n1380; - n_n9618 <= n1385; - n_n9613 <= n1390; - n_n9242 <= n1395; - n_n7384 <= n1400; - n_n8884 <= n1405; - n_n7462 <= n1410; - n_n7908 <= n1415; - n_n8765 <= n1420; - n_n7909 <= n1425; - n_n7898 <= n1430; - n_n9135 <= n1435; - n_n8862 <= n1440; - n_n8037 <= n1445; - ndn3_18 <= n1450; - ndn3_22 <= n1455; - n_n8974 <= n1460; - n_n7286 <= n1465; - n_n9223 <= n1470; - n_n7306 <= n1475; - n_n9169 <= n1480; - n_n9125 <= n1485; - nen3_39 <= n1490; - n_n8278 <= n1495; - n_n9557 <= n1500; - n_n7758 <= n1505; - n_n9391 <= n1510; - n_n8110 <= n1515; - n_n9597 <= n1520; - n_n8568 <= n1525; - n_n7428 <= n1530; - n_n7931 <= n1535; - n_n7742 <= n1540; - n_n7236 <= n1545; - n_n8219 <= n1550; - n_n9568 <= n1555; - n_n9200 <= n1560; - n_n8545 <= n1565; - n_n7823 <= n1570; - n_n8005 <= n1575; - n_n8736 <= n1580; - n_n9339 <= n1585; - n_n8499 <= n1590; - n_n8086 <= n1595; - n_n7803 <= n1600; - n_n7640 <= n1605; - n_n9098 <= n1610; - n_n7160 <= n1615; - n_n7713 <= n1620; - n_n9566 <= n1625; - n_n7955 <= n1630; - n_n8414 <= n1635; - n_n8006 <= n1640; - n_n9560 <= n1645; - n_n8742 <= n1650; - n_n7174 <= n1655; - n_n8882 <= n1660; - n_n7546 <= n1665; - n_n8282 <= n1670; - n_n8998 <= n1675; - n_n7656 <= n1680; - n_n9465 <= n1685; - n_n9601 <= n1690; - n_n8875 <= n1695; - n_n7954 <= n1700; - n_n8959 <= n1705; - n_n8957 <= n1710; - n_n8247 <= n1715; - n_n8258 <= n1720; - n_n7641 <= n1725; - n_n8843 <= n1730; - n_n9321 <= n1735; - n_n7702 <= n1740; - nsr3_23 <= n1745; - n_n8199 <= n1750; - n_n7983 <= n1755; - n_n7217 <= n1760; - n_n7821 <= n1765; - n_n9489 <= n1770; - n_n8348 <= n1775; - n_n9408 <= n1780; - n_n8445 <= n1785; - n_n9501 <= n1790; - n_n7831 <= n1795; - n_n7757 <= n1800; - n_n9174 <= n1805; - n_n9432 <= n1810; - n_n8678 <= n1815; - n_n8024 <= n1820; - n_n7806 <= n1825; - n_n8996 <= n1830; - n_n7918 <= n1835; - n_n8260 <= n1840; - n_n9341 <= n1845; - n_n9189 <= n1850; - n_n9096 <= n1855; - ndn3_30 <= n1860; - n_n7775 <= n1865; - n_n7693 <= n1870; - nen3_16 <= n1875; - n_n7643 <= n1880; - n_n8941 <= n1885; - n_n8042 <= n1890; - n_n8681 <= n1895; - n_n8659 <= n1900; - n_n9110 <= n1905; - n_n9573 <= n1910; - n_n8951 <= n1915; - n_n9589 <= n1920; - n_n9387 <= n1925; - n_n8279 <= n1930; - n_n7790 <= n1935; - n_n8406 <= n1940; - n_n8582 <= n1945; - n_n7911 <= n1950; - n_n7474 <= n1955; - n_n8466 <= n1960; - n_n6984 <= n1965; - n_n7760 <= n1970; - n_n7847 <= n1975; - n_n9559 <= n1980; - n_n7362 <= n1985; - n_n9300 <= n1990; - n_n9550 <= n1995; - n_n9492 <= n2000; - n_n8777 <= n2005; - n_n7764 <= n2010; - n_n7826 <= n2015; - n_n7777 <= n2020; - n_n7824 <= n2025; - n_n8173 <= n2030; - n_n7498 <= n2035; - n_n9148 <= n2040; - n_n8753 <= n2045; - n_n8772 <= n2050; - n_n8049 <= n2055; - n_n9362 <= n2060; - ndn1_4 <= n2065; - n_n9561 <= n2070; - n_n9004 <= n2075; - n_n8203 <= n2080; - n_n8153 <= n2085; - n_n9263 <= n2090; - n_n8369 <= n2095; - n_n9331 <= n2100; - n_n7454 <= n2105; - ndn3_7 <= n2110; - n_n7527 <= n2115; - n_n9036 <= n2120; - n_n7875 <= n2125; - n_n8697 <= n2130; - n_n9497 <= n2135; - n_n7291 <= n2140; - nsr3_13 <= n2145; - nsr3_38 <= n2150; - n_n8240 <= n2155; - n_n7703 <= n2160; - n_n9282 <= n2165; - n_n8237 <= n2170; - n_n8935 <= n2175; - n_n9244 <= n2180; - n_n8648 <= n2185; - n_n8235 <= n2190; - n_n8611 <= n2195; - n_n9045 <= n2200; - n_n9334 <= n2205; - n_n8572 <= n2210; - n_n9491 <= n2215; - n_n9134 <= n2220; - n_n9555 <= n2225; - n_n9336 <= n2230; - n_n7050 <= n2235; - n_n9346 <= n2240; - n_n7140 <= n2245; - n_n7681 <= n2250; - n_n6948 <= n2255; - n_n8549 <= n2260; - ndn3_19 <= n2265; - ndn3_28 <= n2270; - n_n7102 <= n2275; - n_n8093 <= n2280; - n_n9041 <= n2285; - n_n8381 <= n2290; - n_n8810 <= n2295; - nen3_36 <= n2300; - n_n9047 <= n2305; - n_n9333 <= n2310; - n_n7736 <= n2315; - n_n7820 <= n2320; - n_n8986 <= n2325; - n_n8891 <= n2330; - n_n8000 <= n2335; - n_n7968 <= n2340; - n_n8750 <= n2345; - n_n9558 <= n2350; - n_n9368 <= n2355; - n_n8519 <= n2360; - n_n6956 <= n2365; - n_n8298 <= n2370; - n_n9397 <= n2375; - n_n7017 <= n2380; - n_n8638 <= n2385; - n_n9552 <= n2390; - n_n8964 <= n2395; - n_n8016 <= n2400; - n_n7603 <= n2405; - n_n7696 <= n2410; - n_n8589 <= n2415; - n_n9337 <= n2420; - n_n9132 <= n2425; - n_n8652 <= n2430; - n_n8707 <= n2435; - n_n9407 <= n2440; - n_n9044 <= n2445; - n_n8808 <= n2450; - nsr3_30 <= n2455; - n_n8274 <= n2460; - n_n8615 <= n2465; - n_n8238 <= n2470; - n_n7854 <= n2475; - n_n8649 <= n2480; - n_n8236 <= n2485; - n_n8269 <= n2490; - n_n9592 <= n2495; - n_n8022 <= n2500; - n_n8744 <= n2505; - n_n8529 <= n2510; - n_n7967 <= n2515; - n_n9487 <= n2520; - n_n8685 <= n2525; - n_n9531 <= n2530; - n_n9510 <= n2535; - n_n7771 <= n2540; - n_n8480 <= n2545; - n_n8543 <= n2550; - n_n7789 <= n2555; - ndn3_11 <= n2560; - ndn3_15 <= n2565; - ndn3_21 <= n2570; - n_n7584 <= n2575; - n_n8354 <= n2580; - n_n6952 <= n2585; - n_n8864 <= n2590; - n_n7930 <= n2595; - n_n7962 <= n2600; - n_n7929 <= n2605; - n_n9316 <= n2610; - n_n9102 <= n2615; - n_n7308 <= n2620; - n_n7657 <= n2625; - n_n9264 <= n2630; - n_n8760 <= n2635; - n_n6912 <= n2640; - n_n7887 <= n2645; - n_n8911 <= n2650; - n_n7952 <= n2655; - n_n8704 <= n2660; - n_n7876 <= n2665; - n_n9596 <= n2670; - n_n8430 <= n2675; - n_n9019 <= n2680; - n_n7699 <= n2685; - n_n7375 <= n2690; - n_n7936 <= n2695; - n_n8340 <= n2700; - n_n8809 <= n2705; - n_n6961 <= n2710; - n_n9429 <= n2715; - n_n7743 <= n2720; - n_n8980 <= n2725; - n_n7582 <= n2730; - n_n8968 <= n2735; - n_n9371 <= n2740; - n_n8741 <= n2745; - n_n9502 <= n2750; - n_n9373 <= n2755; - n_n9248 <= n2760; - n_n7822 <= n2765; - n_n9054 <= n2770; - n_n8273 <= n2775; - n_n6937 <= n2780; - n_n9342 <= n2785; - n_n9325 <= n2790; - n_n9609 <= n2795; - n_n9623 <= n2800; - n_n9470 <= n2805; - n_n7570 <= n2810; - n_n9310 <= n2815; - n_n9366 <= n2820; - n_n7181 <= n2825; - n_n8739 <= n2830; - n_n8939 <= n2835; - n_n7256 <= n2840; - n_n8983 <= n2845; - n_n7487 <= n2850; - n_n9268 <= n2855; - n_n8906 <= n2860; - n_n7988 <= n2865; - n_n9181 <= n2870; - n_n8725 <= n2875; - n_n8626 <= n2880; - ndn3_27 <= n2885; - n_n8210 <= n2890; - n_n7415 <= n2895; - n_n8900 <= n2900; - nen3_19 <= n2905; - n_n8762 <= n2910; - n_n8512 <= n2915; - n_n8095 <= n2920; - n_n8982 <= n2925; - n_n7387 <= n2930; - n_n9494 <= n2935; - n_n7689 <= n2940; - n_n7835 <= n2945; - n_n9157 <= n2950; - n_n8552 <= n2955; - n_n7381 <= n2960; - n_n9446 <= n2965; - n_n8633 <= n2970; - n_n7684 <= n2975; - n_n7310 <= n2980; - n_n8402 <= n2985; - n_n9315 <= n2990; - n_n7950 <= n2995; - n_n8504 <= n3000; - n_n8456 <= n3005; - n_n7514 <= n3010; - n_n7315 <= n3015; - n_n9476 <= n3020; - n_n8276 <= n3025; - n_n8833 <= n3030; - n_n7923 <= n3035; - n_n9395 <= n3040; - n_n9512 <= n3045; - n_n9319 <= n3050; - nsr3_35 <= n3055; - n_n7154 <= n3060; - n_n9495 <= n3065; - n_n9137 <= n3070; - n_n8854 <= n3075; - n_n9183 <= n3080; - n_n9323 <= n3085; - n_n9349 <= n3090; - n_n7896 <= n3095; - n_n8073 <= n3100; - n_n8970 <= n3105; - n_n9314 <= n3110; - n_n8486 <= n3115; - n_n7246 <= n3120; - n_n7866 <= n3125; - n_n9599 <= n3130; - n_n7635 <= n3135; - n_n8984 <= n3140; - n_n7360 <= n3145; - n_n8794 <= n3150; - n_n9108 <= n3155; - n_n9286 <= n3160; - ndn3_12 <= n3165; - ndn3_16 <= n3170; - n_n7708 <= n3175; - n_n7807 <= n3180; - n_n7650 <= n3185; - n_n7947 <= n3190; - n_n9500 <= n3195; - n_n7734 <= n3200; - n_n8464 <= n3205; - n_n7659 <= n3210; - n_n7630 <= n3215; - n_n7756 <= n3220; - n_n8691 <= n3225; - n_n9176 <= n3230; - n_n9327 <= n3235; - n_n7995 <= n3240; - n_n7395 <= n3245; - n_n7878 <= n3250; - n_n7507 <= n3255; - n_n7959 <= n3260; - n_n7825 <= n3265; - n_n8009 <= n3270; - n_n8281 <= n3275; - n_n7685 <= n3280; - n_n8106 <= n3285; - n_n7687 <= n3290; - n_n7766 <= n3295; - n_n7880 <= n3300; - n_n8961 <= n3305; - n_n8014 <= n3310; - n_n9278 <= n3315; - n_n9087 <= n3320; - n_n9182 <= n3325; - n_n7852 <= n3330; - n_n9324 <= n3335; - nak3_13 <= n3340; - n_n9416 <= n3345; - nsr3_14 <= n3350; - n_n8603 <= n3355; - n_n7026 <= n3360; - n_n8856 <= n3365; - n_n8272 <= n3370; - n_n9312 <= n3375; - n_n7985 <= n3380; - n_n8312 <= n3385; - n_n7231 <= n3390; - n_n9396 <= n3395; - n_n8801 <= n3400; - n_n8683 <= n3405; - ndn3_39 <= n3410; - n_n8245 <= n3415; - n_n9458 <= n3420; - n_n9302 <= n3425; - n_n7392 <= n3430; - n_n6963 <= n3435; - n_n7808 <= n3440; - n_n7225 <= n3445; - n_n7817 <= n3450; - n_n8201 <= n3455; - n_n7793 <= n3460; - n_n8177 <= n3465; - n_n8389 <= n3470; - n_n9440 <= n3475; - n_n7683 <= n3480; - n_n7761 <= n3485; - n_n7667 <= n3490; - n_n7980 <= n3495; - n_n7509 <= n3500; - n_n7813 <= n3505; - n_n8396 <= n3510; - n_n9535 <= n3515; - n_n7209 <= n3520; - n_n7003 <= n3525; - n_n7695 <= n3530; - n_n7624 <= n3535; - n_n8791 <= n3540; - n_n7374 <= n3545; - n_n7429 <= n3550; - n_n7944 <= n3555; - n_n9266 <= n3560; - n_n8100 <= n3565; - n_n6988 <= n3570; - n_n6986 <= n3575; - n_n8933 <= n3580; - n_n7117 <= n3585; - n_n9043 <= n3590; - n_n8241 <= n3595; - n_n9219 <= n3600; - n_n8198 <= n3605; - n_n8081 <= n3610; - n_n8575 <= n3615; - n_n8710 <= n3620; - n_n7622 <= n3625; - n_n7966 <= n3630; - n_n7885 <= n3635; - n_n7033 <= n3640; - ndn3_34 <= n3645; - n_n9186 <= n3650; - ndn3_50 <= n3655; - n_n7879 <= n3660; - n_n7019 <= n3665; - n_n9171 <= n3670; - n_n7261 <= n3675; - n_n8223 <= n3680; - n_n8989 <= n3685; - n_n7993 <= n3690; - n_n7845 <= n3695; - n_n8253 <= n3700; - n_n8889 <= n3705; - n_n7809 <= n3710; - n_n8918 <= n3715; - n_n8515 <= n3720; - n_n7933 <= n3725; - n_n8075 <= n3730; - n_n7338 <= n3735; - n_n8104 <= n3740; - n_n8171 <= n3745; - n_n9059 <= n3750; - n_n9023 <= n3755; - n_n7692 <= n3760; - n_n9441 <= n3765; - n_n6920 <= n3770; - n_n8831 <= n3775; - n_n8441 <= n3780; - n_n9576 <= n3785; - n_n9252 <= n3790; - n_n9363 <= n3795; - ndn3_4 <= n3800; - n_n9247 <= n3805; - n_n7561 <= n3810; - n_n8923 <= n3815; - n_n7978 <= n3820; - n_n8978 <= n3825; - n_n9499 <= n3830; - n_n8713 <= n3835; - n_n8944 <= n3840; - n_n8239 <= n3845; - n_n7652 <= n3850; - n_n9042 <= n3855; - n_n8530 <= n3860; - n_n9271 <= n3865; - n_n9318 <= n3870; - n_n7706 <= n3875; - n_n7964 <= n3880; - n_n8222 <= n3885; - n_n8898 <= n3890; - n_n7976 <= n3895; - n_n7649 <= n3900; - n_n7604 <= n3905; - n_n7961 <= n3910; - n_n7424 <= n3915; - n_n7476 <= n3920; - n_n9259 <= n3925; - n_n9309 <= n3930; - n_n9161 <= n3935; - n_n8436 <= n3940; - n_n9121 <= n3945; - n_n8061 <= n3950; - n_n8004 <= n3955; - n_n9360 <= n3960; - n_n9205 <= n3965; - n_n8392 <= n3970; - n_n9034 <= n3975; - n_n8375 <= n3980; - n_n8328 <= n3985; - n_n9298 <= n3990; - n_n7598 <= n3995; - n_n8506 <= n4000; - pdn <= n4005; - n_n7737 <= n4009; - n_n7420 <= n4014; - n_n9291 <= n4019; - n_n7946 <= n4024; - n_n8584 <= n4029; - n_n9308 <= n4034; - n_n9403 <= n4039; - n_n7284 <= n4044; - n_n9270 <= n4049; - n_n7390 <= n4054; - n_n9351 <= n4059; - n_n6968 <= n4064; - n_n8668 <= n4069; - n_n9605 <= n4074; - n_n7013 <= n4079; - n_n9626 <= n4084; - n_n8200 <= n4089; - n_n9028 <= n4094; - n_n8803 <= n4099; - n_n9570 <= n4104; - n_n8366 <= n4109; - n_n9050 <= n4114; - n_n8650 <= n4119; - n_n8574 <= n4124; - n_n7276 <= n4129; - n_n9212 <= n4134; - n_n8384 <= n4139; - ndn3_35 <= n4144; - n_n8449 <= n4149; - ndn3_46 <= n4154; - n_n7554 <= n4159; - n_n8743 <= n4164; - n_n8277 <= n4169; - n_n9359 <= n4174; - n_n8425 <= n4179; - n_n9104 <= n4184; - n_n9221 <= n4189; - n_n9448 <= n4194; - n_n9537 <= n4199; - n_n8003 <= n4204; - n_n7467 <= n4209; - n_n8233 <= n4214; - n_n7932 <= n4219; - n_n8064 <= n4224; - n_n9162 <= n4229; - n_n7971 <= n4234; - n_n8055 <= n4239; - n_n7711 <= n4244; - n_n8256 <= n4249; - n_n7925 <= n4254; - n_n7762 <= n4259; - n_n7668 <= n4264; - n_n7914 <= n4269; - n_n7873 <= n4274; - n_n7849 <= n4279; - n_n9421 <= n4284; - n_n7626 <= n4289; - n_n7848 <= n4294; - n_n8263 <= n4299; - n_n9100 <= n4304; - n_n9393 <= n4309; - n_n9591 <= n4314; - n_n7588 <= n4319; - n_n9123 <= n4324; - n_n9159 <= n4329; - n_n9128 <= n4334; - n_n8045 <= n4339; - n_n7728 <= n4344; - n_n8929 <= n4349; - n_n7739 <= n4354; - n_n9355 <= n4359; - n_n9394 <= n4364; - n_n8470 <= n4369; - n_n8571 <= n4374; - n_n8796 <= n4379; - ndn3_36 <= n4384; - n_n7990 <= n4389; - n_n8781 <= n4394; - n_n8817 <= n4399; - n_n9160 <= n4404; - n_n9092 <= n4409; - n_n8513 <= n4414; - n_n8213 <= n4419; - n_n8581 <= n4424; - n_n9284 <= n4429; - n_n7837 <= n4434; - n_n8224 <= n4439; - n_n9203 <= n4444; - n_n7655 <= n4449; - n_n8946 <= n4454; - n_n7052 <= n4459; - n_n9615 <= n4464; - n_n8473 <= n4469; - n_n7741 <= n4474; - n_n9460 <= n4479; - n_n7912 <= n4484; - n_n7606 <= n4489; - n_n9021 <= n4494; - n_n7781 <= n4499; - n_n7810 <= n4504; - n_n7108 <= n4509; - n_n7697 <= n4514; - n_n7642 <= n4519; - n_n9595 <= n4524; - n_n7694 <= n4529; - n_n8221 <= n4534; - n_n7600 <= n4539; - n_n7935 <= n4544; - n_n9230 <= n4549; - n_n7701 <= n4554; - n_n7510 <= n4559; - n_n7627 <= n4564; - n_n8502 <= n4569; - n_n8516 <= n4574; - n_n7913 <= n4579; - n_n9320 <= n4584; - n_n7411 <= n4589; - n_n9129 <= n4594; - n_n9053 <= n4599; - n_n7069 <= n4604; - n_n8617 <= n4609; - n_n7242 <= n4614; - n_n8230 <= n4619; - n_n9294 <= n4624; - n_n8249 <= n4629; - n_n8972 <= n4634; - n_n7074 <= n4639; - n_n7493 <= n4644; - n_n8290 <= n4649; - n_n8821 <= n4654; - n_n7769 <= n4659; - n_n7491 <= n4664; - n_n9600 <= n4669; - n_n9317 <= n4674; - n_n8047 <= n4679; - n_n9629 <= n4684; - n_n9126 <= n4689; - n_n9508 <= n4694; - n_n9155 <= n4699; - n_n8528 <= n4704; - ndn3_37 <= n4709; - ndn3_42 <= n4714; - n_n9358 <= n4719; - n_n8185 <= n4724; - nen3_28 <= n4729; - n_n8839 <= n4734; - n_n7903 <= n4739; - n_n9139 <= n4744; - n_n9075 <= n4749; - n_n9439 <= n4754; - n_n9353 <= n4759; - n_n7665 <= n4764; - n_n8798 <= n4769; - n_n7146 <= n4774; - n_n7890 <= n4779; - n_n7176 <= n4784; - n_n8477 <= n4789; - n_n8514 <= n4794; - n_n8636 <= n4799; - n_n7183 <= n4804; - n_n8657 <= n4809; - n_n9493 <= n4814; - n_n7969 <= n4819; - n_n9255 <= n4824; - n_n8535 <= n4829; - n_n8619 <= n4834; - n_n8909 <= n4839; - n_n7744 <= n4844; - n_n9119 <= n4849; - n_n7827 <= n4854; - n_n8916 <= n4859; - n_n8729 <= n4864; - n_n9011 <= n4869; - n_n8779 <= n4874; - n_n6980 <= n4879; - n_n7715 <= n4884; - n_n9067 <= n4889; - n_n9164 <= n4894; - n_n7402 <= n4899; - n_n8938 <= n4904; - n_n9046 <= n4909; - n_n8789 <= n4914; - n_n9390 <= n4919; - n_n7768 <= n4924; - n_n9136 <= n4929; - n_n8670 <= n4934; - n_n8644 <= n4939; - n_n9178 <= n4944; - n_n8188 <= n4949; - n_n7083 <= n4954; - n_n9344 <= n4959; - n_n7366 <= n4964; - n_n8361 <= n4969; - n_n9228 <= n4974; - n_n9402 <= n4979; - n_n8510 <= n4984; - n_n8881 <= n4989; - n_n9404 <= n4994; - n_n9424 <= n4999; - n_n9031 <= n5004; - nsr3_37 <= n5009; - n_n8197 <= n5014; - n_n8468 <= n5019; - n_n7121 <= n5024; - n_n7511 <= n5029; - ndn3_44 <= n5034; - n_n9322 <= n5039; - n_n7682 <= n5044; - n_n9603 <= n5049; - nlc1_2 <= n5054; - n_n8408 <= n5059; - n_n8577 <= n5064; - n_n7079 <= n5069; - n_n8828 <= n5074; - n_n9340 <= n5079; - n_n8586 <= n5084; - n_n7901 <= n5089; - n_n8628 <= n5094; - n_n8869 <= n5099; - n_n7710 <= n5104; - n_n8993 <= n5109; - n_n9586 <= n5114; - n_n8852 <= n5119; - n_n8583 <= n5124; - n_n8011 <= n5129; - n_n7717 <= n5134; - n_n8326 <= n5139; - n_n9163 <= n5144; - n_n8344 <= n5149; - n_n8296 <= n5154; - n_n8116 <= n5159; - n_n8267 <= n5164; - n_n7686 <= n5169; - n_n9061 <= n5174; - n_n9338 <= n5179; - n_n7688 <= n5184; - n_n9081 <= n5189; - n_n6910 <= n5194; - n_n8727 <= n5199; - n_n7674 <= n5204; - n_n7330 <= n5209; - n_n8966 <= n5214; - n_n7843 <= n5219; - n_n8847 <= n5224; - n_n9376 <= n5229; - n_n7553 <= n5234; - n_n9292 <= n5239; - n_n7464 <= n5244; - n_n8146 <= n5249; - n_n8439 <= n5254; - n_n9498 <= n5259; - n_n8118 <= n5264; - n_n9452 <= n5269; - n_n9239 <= n5274; - n_n9237 <= n5279; - n_n9488 <= n5284; - ndn3_2 <= n5289; - n_n9522 <= n5294; - n_n9313 <= n5299; - n_n7435 <= n5304; - n_n8665 <= n5309; - n_n9593 <= n5314; - n_n8303 <= n5319; - n_n7022 <= n5324; - n_n9173 <= n5329; - n_n9261 <= n5334; - n_n7150 <= n5339; - n_n9455 <= n5344; - n_n8371 <= n5349; - nsr3_20 <= n5354; - n_n8271 <= n5359; - n_n9542 <= n5364; - n_n7444 <= n5369; - ndn3_40 <= n5374; - n_n7130 <= n5379; - n_n9347 <= n5384; - n_n8102 <= n5389; - n_n9225 <= n5394; - n_n8462 <= n5399; - n_n8088 <= n5404; - n_n9026 <= n5409; - n_n9289 <= n5414; - n_n7661 <= n5419; - n_n8108 <= n5424; - n_n8921 <= n5429; - n_n7859 <= n5434; - n_n7732 <= n5439; - n_n7956 <= n5444; - n_n9520 <= n5449; - n_n7666 <= n5454; - n_n7678 <= n5459; - n_n7846 <= n5464; - n_n8280 <= n5469; - n_n8841 <= n5474; - n_n7336 <= n5479; - n_n8226 <= n5484; - n_n8151 <= n5489; - n_n7644 <= n5494; - n_n8770 <= n5499; - n_n8423 <= n5504; - n_n7763 <= n5509; - n_n9525 <= n5514; - n_n8033 <= n5519; - n_n7881 <= n5524; - n_n7815 <= n5529; - n_n9232 <= n5534; - n_n7792 <= n5539; - n_n9563 <= n5544; - n_n8672 <= n5549; - n_n7346 <= n5554; - n_n7949 <= n5559; - n_n8756 <= n5564; - n_n8641 <= n5569; - n_n8192 <= n5574; - n_n8058 <= n5579; - n_n8561 <= n5584; - n_n9306 <= n5589; - n_n9165 <= n5594; - n_n8850 <= n5599; - n_n9210 <= n5604; - ndn2_2 <= n5609; - n_n7342 <= n5614; - n_n8051 <= n5619; - n_n7136 <= n5624; - n_n9348 <= n5629; - n_n9006 <= n5634; - n_n7653 <= n5639; - n_n7905 <= n5644; - n_n9166 <= n5649; - n_n7065 <= n5654; - n_n9490 <= n5659; - n_n7024 <= n5664; - n_n7586 <= n5669; - n_n8416 <= n5674; - n_n8937 <= n5679; - n_n8141 <= n5684; - n_n7853 <= n5689; - n_n8121 <= n5694; - n_n9604 <= n5699; - n_n9496 <= n5704; - n_n8195 <= n5709; - n_n9516 <= n5714; - n_n9077 <= n5719; - n_n9436 <= n5724; - n_n9051 <= n5729; - n_n7664 <= n5734; - n_n8419 <= n5739; - n_n7874 <= n5744; - n_n9133 <= n5749; - n_n9392 <= n5754; - n_n7770 <= n5759; - ndn3_32 <= n5764; - n_n7601 <= n5769; - n_n8206 <= n5774; - n_n7927 <= n5779; - n_n9606 <= n5784; - n_n7111 <= n5789; - n_n9269 <= n5794; - ndn3_38 <= n5799; - n_n7886 <= n5804; - n_n9179 <= n5809; - n_n9357 <= n5814; - n_n9594 <= n5819; - n_n7628 <= n5824; - n_n8454 <= n5829; - ndn3_20 <= n5834; - n_n9505 <= n5839; - nen3_34 <= n5844; - n_n9632 <= n5849; - n_n7076 <= n5854; - n_n9262 <= n5859; - n_n9048 <= n5864; - n_n9578 <= n5869; - n_n8135 <= n5874; - ndn3_26 <= n5879; - n_n7500 <= n5884; - n_n6974 <= n5889; - n_n8605 <= n5894; - n_n9296 <= n5899; - n_n7156 <= n5904; - n_n7920 <= n5909; - n_n8895 <= n5914; - n_n8991 <= n5919; - n_n8139 <= n5924; - n_n9275 <= n5929; - n_n7203 <= n5934; - n_n9590 <= n5939; - n_n7344 <= n5944; - n_n6976 <= n5949; - n_n7629 <= n5954; - ndn3_14 <= n5959; - n_n7862 <= n5964; - n_n9013 <= n5969; - n_n7288 <= n5974; - n_n8078 <= n5979; - n_n7334 <= n5984; - n_n7704 <= n5989; - n_n7788 <= n5994; - n_n8526 <= n5999; - n_n9556 <= n6004; - n_n9345 <= n6009; - n_n8447 <= n6014; - n_n7485 <= n6019; - n_n8570 <= n6024; - n_n7453 <= n6029; - n_n7928 <= n6034; - n_n8646 <= n6039; - n_n9405 <= n6044; - n_n8948 <= n6049; - n_n9131 <= n6054; - n_n8216 <= n6059; - n_n9177 <= n6064; - n_n7844 <= n6069; - n_n8811 <= n6074; - n_n9145 <= n6079; - n_n8428 <= n6084; - n_n8858 <= n6089; - n_n8580 <= n6094; - end -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/ex1010/ex1010.v b/fpga_flow/benchmarks/Verilog/MCNC/ex1010/ex1010.v deleted file mode 100644 index 47c44a6c9..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/ex1010/ex1010.v +++ /dev/null @@ -1,930 +0,0 @@ -// Benchmark "TOP" written by ABC on Mon Feb 4 17:31:22 2019 - -module ex1010 ( - i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, - o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_ ); - input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_; - output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_; - wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, - n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, - n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, - n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, - n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, - n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, - n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, - n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, - n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, - n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, - n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, - n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, - n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, - n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, - n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, - n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, - n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, - n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, - n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, - n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, - n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, - n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, - n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, - n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, - n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, - n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, - n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, - n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, - n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, - n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, - n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, - n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, - n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, - n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, - n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, - n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, - n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, - n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, - n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, - n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, - n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, - n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, - n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, - n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, - n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, - n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, - n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, - n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, - n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, - n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, - n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, - n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, - n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, - n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, - n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, - n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, - n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, - n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, - n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, - n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, - n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, - n772, n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783, - n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, - n796, n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, - n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, - n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, - n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, - n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, - n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, - n868, n869; - assign o_0_ = ~n418; - assign o_1_ = ~n31; - assign o_2_ = ~n403; - assign o_3_ = ~n378; - assign o_4_ = ~n349; - assign o_5_ = ~n30; - assign o_6_ = ~n270; - assign o_7_ = ~n216; - assign o_8_ = ~n170; - assign o_9_ = ~n109; - assign n30 = n155 & n50 & n301 & n302 & n303 & n304 & n305 & n306; - assign n31 = n97 & n404 & n151 & n405 & n406 & n407 & n408 & n409; - assign n32 = (n436 | n458) & (n219 | n479); - assign n33 = ~i_9_ | n429; - assign n34 = n423 | n446; - assign n35 = n32 & (n33 | n34); - assign n36 = (n222 | n481) & (n43 | n480); - assign n37 = ~i_9_ | n419; - assign n38 = n423 | n457; - assign n39 = n36 & (n37 | n38); - assign n40 = i_9_ | n440; - assign n41 = n420 | n441; - assign n42 = n419 | n450; - assign n43 = i_9_ | n421; - assign n44 = (n42 | n43) & (n40 | n41); - assign n45 = n219 | n103; - assign n46 = n439 | n290; - assign n47 = n565 & n320 & n566; - assign n48 = n563 & n564 & (n272 | n476); - assign n49 = n561 & n562 & n125 & n556 & n560 & n557; - assign n50 = n45 & n46 & n44 & n35 & n39 & n47 & n48 & n49; - assign n51 = n40 | n456; - assign n52 = n436 | n203; - assign n53 = ~i_9_ | n427; - assign n54 = n426 | n446; - assign n55 = n51 & n52 & (n53 | n54); - assign n56 = n37 | n262; - assign n57 = n272 | n487; - assign n58 = n319 & (n219 | n488); - assign n59 = n555 & n55 & (n91 | n489); - assign n60 = n53 | n92; - assign n61 = n219 | n485; - assign n62 = n33 | n486; - assign n63 = n388 & n554 & (n53 | n483); - assign n64 = n56 & n57 & n58 & n59 & n60 & n61 & n62 & n63; - assign n65 = n552 & (n37 | n490); - assign n66 = n436 | n491; - assign n67 = (n33 | n469) & (n96 | n43); - assign n68 = n219 | n339; - assign n69 = (n37 | n478) & (n439 | n494); - assign n70 = n553 & n328 & (n309 | n481); - assign n71 = n65 & n66 & n67 & n68 & n69 & n70; - assign n72 = n91 | n496; - assign n73 = n100 | n41; - assign n74 = (n309 | n463) & (n222 | n495); - assign n75 = (n222 | n463) & (n43 | n255); - assign n76 = (n422 | n462) & (n43 | n223); - assign n77 = n72 & n73 & n74 & n75 & n76; - assign n78 = n219 | n498; - assign n79 = n436 | n480; - assign n80 = (n436 | n447) & (n222 | n497); - assign n81 = (n86 | n475) & (n258 | n499); - assign n82 = (n309 | n480) & (n40 | n493); - assign n83 = n78 & n79 & n80 & n81 & n82; - assign n84 = (n443 | n86) & (n462 | n502); - assign n85 = n225 & n551 & (n258 | n500); - assign n86 = i_9_ | n460; - assign n87 = n433 | n466; - assign n88 = n84 & n85 & (n86 | n87); - assign n89 = (n222 | n203) & (n33 | n150); - assign n90 = n549 & n550 & (n219 | n199); - assign n91 = ~i_9_ | n466; - assign n92 = n435 | n442; - assign n93 = n89 & n90 & (n91 | n92); - assign n94 = n462 | n507; - assign n95 = n548 & n124 & (n100 | n506); - assign n96 = n441 | n442; - assign n97 = n94 & n95 & (n96 | n86); - assign n98 = (n219 | n92) & (n53 | n469); - assign n99 = n431 | n432; - assign n100 = i_9_ | n457; - assign n101 = n98 & (n99 | n100); - assign n102 = (n100 | n508) & (n33 | n489); - assign n103 = n423 | n460; - assign n104 = n102 & (n37 | n103); - assign n105 = (n86 | n465) & (n464 | n219); - assign n106 = n64 & n71 & n50 & n83 & n88 & n77; - assign n107 = n589 & n593 & n592 & n586 & n585 & n588; - assign n108 = n580 & n584 & n583 & n579 & n577 & n575; - assign n109 = n97 & n101 & n93 & n105 & n104 & n106 & n107 & n108; - assign n110 = n623 & (n100 | n514); - assign n111 = n37 | n507; - assign n112 = n86 | (n468 & n492); - assign n113 = n622 & (n462 | n498); - assign n114 = n620 & n621 & (n43 | n310); - assign n115 = n619 & n285 & n561 & n209 & n56 & n618 & n299 & n616; - assign n116 = n110 & n111 & n112 & n113 & n114 & n115; - assign n117 = (n37 | n471) & (n33 | n520); - assign n118 = n53 | n34; - assign n119 = (n91 | n523) & (n462 | n488); - assign n120 = n609 & n608 & (n100 | n475); - assign n121 = n312 & n613 & (n309 | n458); - assign n122 = n611 & n610 & (n447 | n43); - assign n123 = n117 & n118 & n119 & n120 & n121 & n122; - assign n124 = n462 | n505; - assign n125 = n43 | n468; - assign n126 = n73 & (n222 | n518); - assign n127 = (n86 | n525) & (n272 | n465); - assign n128 = n606 & (n309 | n524); - assign n129 = n603 & (n462 | n526); - assign n130 = n601 & n602 & (n439 | n498); - assign n131 = n605 & n604 & (n37 | n461); - assign n132 = n124 & n125 & n126 & n127 & n128 & n129 & n130 & n131; - assign n133 = (n272 | n495) & (n91 | n103); - assign n134 = n454 | n100; - assign n135 = n600 & (n309 | n484); - assign n136 = n462 | n477; - assign n137 = n598 & n599 & (n219 | n500); - assign n138 = n596 & n597 & (n222 | n42); - assign n139 = n133 & n134 & n135 & n136 & n137 & n138; - assign n140 = (n91 | n511) & (n272 | n528); - assign n141 = n594 & n595 & (n91 | n34); - assign n142 = n420 | n432; - assign n143 = n140 & n141 & (n86 | n142); - assign n144 = (n272 | n529) & (n258 | n503); - assign n145 = n86 | n530; - assign n146 = (n53 | n103) & (n424 | n462); - assign n147 = n144 & n145 & n146 & n61; - assign n148 = (n309 | n531) & (n436 | n456); - assign n149 = (n86 | n532) & (n100 | n472); - assign n150 = n421 | n442; - assign n151 = n148 & n149 & (n91 | n150); - assign n152 = (n40 & n436) | n533; - assign n153 = n380 & (n53 | n496); - assign n154 = n423 | n435; - assign n155 = n152 & n153 & (n91 | n154); - assign n156 = (n100 | n531) & (n91 | n534); - assign n157 = n426 | n466; - assign n158 = n156 & (n86 | n157); - assign n159 = (n33 | n505) & (n91 | n38); - assign n160 = n433 | n460; - assign n161 = n159 & (n33 | n160); - assign n162 = (n436 | n513) & (n33 | n92); - assign n163 = (n53 | n509) & (n222 | n512); - assign n164 = (n222 | n513) & (n37 | n467); - assign n165 = (n258 | n467) & (n43 | n501); - assign n166 = n626 & n625 & (n309 | n42); - assign n167 = n633 & n634 & n631 & n630 & n629 & n387 & n628 & n627; - assign n168 = n139 & n143 & n147 & n151 & n123 & n132 & n116 & n644; - assign n169 = n640 & n641 & n639 & n638 & n637 & n642 & n636 & n635; - assign n170 = n162 & n163 & n164 & n165 & n166 & n167 & n168 & n169; - assign n171 = (n37 | n92) & (n43 | n484); - assign n172 = n648 & n649 & (n458 | n86); - assign n173 = n647 & (n100 | n294); - assign n174 = n645 & n646 & (n219 | n540); - assign n175 = n171 & n172 & n173 & n174; - assign n176 = n33 | n477; - assign n177 = n272 | n255; - assign n178 = (n91 | n538) & (n452 | n43); - assign n179 = n91 | n504; - assign n180 = (n100 | n492) & (n258 | n504); - assign n181 = n559 & (n53 | n290); - assign n182 = n176 & n177 & n178 & n179 & n180 & n181; - assign n183 = n428 | n100; - assign n184 = n219 | n34; - assign n185 = (n436 | n472) & (n43 | n474); - assign n186 = n40 | n542; - assign n187 = (n91 | n339) & (n445 | n219); - assign n188 = (n40 | n525) & (n219 | n505); - assign n189 = n183 & n184 & n185 & n186 & n187 & n188; - assign n190 = n436 | n525; - assign n191 = n86 | n512; - assign n192 = (n86 | n480) & (n436 | n544); - assign n193 = n53 | n486; - assign n194 = n309 | n543; - assign n195 = (n258 | n251) & (n222 | n294); - assign n196 = n190 & n191 & n192 & n193 & n194 & n195; - assign n197 = (n96 | n100) & (n272 | n532); - assign n198 = n350 & n351 & (n40 | n513); - assign n199 = n450 | n457; - assign n200 = n197 & n198 & (n53 | n199); - assign n201 = (n462 | n496) & (n37 | n522); - assign n202 = (n309 | n517) & (n439 | n539); - assign n203 = n423 | n432; - assign n204 = n201 & n202 & (n86 | n203); - assign n205 = (n222 | n142) & (n272 | n521); - assign n206 = (n439 | n496) & (n33 | n470); - assign n207 = n205 & n206; - assign n208 = (n86 | n519) & (n100 | n537); - assign n209 = n53 | n150; - assign n210 = n674 & n673 & (n272 | n514); - assign n211 = n566 & n563 & n234 & n605 & n672 & n671; - assign n212 = n64 & n139 & (n461 | n91); - assign n213 = n676 & n675 & (n53 | n539); - assign n214 = n196 & n200 & n204 & n207 & n182 & n189 & n175; - assign n215 = n670 & n227 & n668 & n667 & n663 & n662 & n666 & n661; - assign n216 = n208 & n209 & n210 & n211 & n212 & n213 & n214 & n215; - assign n217 = n258 | n92; - assign n218 = (n309 | n542) & (n40 | n518); - assign n219 = ~i_9_ | n451; - assign n220 = n217 & n218 & (n219 | n38); - assign n221 = (n86 | n513) & (n462 | n545); - assign n222 = i_9_ | n425; - assign n223 = n442 | n466; - assign n224 = n221 & (n222 | n223); - assign n225 = n272 | n501; - assign n226 = n438 | n439; - assign n227 = n456 | n100; - assign n228 = n45 & n72 & (n43 | n525); - assign n229 = n686 & n685 & (n309 | n294); - assign n230 = n276 & n652 & n684 & n277; - assign n231 = n224 & n158 & n220 & n44 & n404 & n693 & n692 & n690; - assign n232 = n225 & n226 & n227 & n176 & n228 & n229 & n230 & n231; - assign n233 = n434 | n33; - assign n234 = n462 | n478; - assign n235 = n674 & (n40 | n536); - assign n236 = (n258 | n527) & (n222 | n510); - assign n237 = n33 | n523; - assign n238 = (n40 | n519) & (n37 | n259); - assign n239 = n439 | (n339 & n516); - assign n240 = n682 & n683 & (n100 | n541); - assign n241 = n233 & n234 & n235 & n236 & n237 & n238 & n239 & n240; - assign n242 = (n53 | n534) & (n462 | n54); - assign n243 = n96 | n272; - assign n244 = n681 & (n86 | n501); - assign n245 = n43 | n491; - assign n246 = n46 & n615 & (n91 | n479); - assign n247 = n679 & n680 & (n436 | n508); - assign n248 = n242 & n243 & n244 & n245 & n246 & n247; - assign n249 = n392 & (n40 | n492); - assign n250 = n678 & n677 & (n33 | n546); - assign n251 = n442 | n446; - assign n252 = n249 & n250 & (n53 | n251); - assign n253 = n272 | n536; - assign n254 = (n258 | n540) & (n86 | n515); - assign n255 = n431 | n441; - assign n256 = n253 & n254 & (n40 | n255); - assign n257 = (n91 | n520) & (n456 | n43); - assign n258 = ~i_9_ | n441; - assign n259 = n420 | n440; - assign n260 = n257 & (n258 | n259); - assign n261 = (n222 | n468) & (n258 | n339); - assign n262 = n420 | n449; - assign n263 = n261 & (n53 | n262); - assign n264 = (n37 | n290) & (n454 | n86); - assign n265 = (n219 | n511) & (n33 | n494); - assign n266 = n710 & n709 & (n309 | n506); - assign n267 = n713 & n712 & (n33 | n479); - assign n268 = n252 & n256 & n260 & n263 & n241 & n248 & n232 & n717; - assign n269 = n700 & n177 & n699 & n698 & n695 & n694 & n697 & n708; - assign n270 = n264 & n265 & n266 & n267 & n268 & n269; - assign n271 = (n100 | n535) & (n439 | n251); - assign n272 = i_9_ | n449; - assign n273 = n271 & (n272 | n42); - assign n274 = n91 | n546; - assign n275 = n439 | n546; - assign n276 = n436 | n476; - assign n277 = n219 | n150; - assign n278 = n253 & n719 & (n309 | n528); - assign n279 = n714 & (n91 | n526); - assign n280 = n321 & (n37 | n438); - assign n281 = n721 & n720 & (n86 | n41); - assign n282 = n274 & n275 & n276 & n277 & n278 & n279 & n280 & n281; - assign n283 = n219 | n478; - assign n284 = n428 | n436; - assign n285 = n100 | n521; - assign n286 = n665 & (n455 | n219); - assign n287 = n161 & n283 & n263 & n284 & n285 & n286; - assign n288 = (n40 | n497) & (n37 | n539); - assign n289 = n718 & (n219 | n486); - assign n290 = n453 | n460; - assign n291 = n288 & n289 & (n290 | n91); - assign n292 = n43 | (n476 & n506); - assign n293 = n686 & (n53 | n473); - assign n294 = n423 | n466; - assign n295 = n292 & n293 & (n272 | n294); - assign n296 = n219 | n469; - assign n297 = n100 | n533; - assign n298 = (n272 | n543) & (n462 | n486); - assign n299 = n455 | n53; - assign n300 = n296 & n297 & n298 & n299; - assign n301 = (n436 | n529) & (n219 | n547); - assign n302 = n749 & n748 & (n91 | n516); - assign n303 = n282 & n287 & n291 & n295 & n300 & n252 & n224 & n196; - assign n304 = n747 & n746 & n745 & n744 & n743 & n742 & n741 & n740; - assign n305 = n738 & n739 & n730 & n732 & n731 & n737 & n736 & n735; - assign n306 = n729 & n728 & n727 & n726 & n725 & n724 & n723 & n722; - assign n307 = n678 & (n219 | n490); - assign n308 = (n219 | n507) & (n459 | n462); - assign n309 = i_9_ | n446; - assign n310 = n419 | n433; - assign n311 = n307 & n308 & (n309 | n310); - assign n312 = n53 | n503; - assign n313 = n710 & n632 & (n309 | n501); - assign n314 = n753 & n590 & n190 & n78 & n79 & n51; - assign n315 = n469 | n91; - assign n316 = n669 & n649 & (n37 | n477); - assign n317 = n751 & n752 & (n439 | n92); - assign n318 = n311 & n312 & n313 & n314 & n315 & n234 & n316 & n317; - assign n319 = n447 | n100; - assign n320 = n219 | n477; - assign n321 = n219 | n154; - assign n322 = (n439 | n461) & (n100 | n530); - assign n323 = n222 | n472; - assign n324 = n654 & (n91 | n259); - assign n325 = (n222 | n537) & (n37 | n482); - assign n326 = n750 & n738 & (n272 | n484); - assign n327 = n319 & n320 & n321 & n322 & n323 & n324 & n325 & n326; - assign n328 = n436 | n492; - assign n329 = n53 | n489; - assign n330 = n452 | n100; - assign n331 = (n465 | n43) & (n272 | n512); - assign n332 = (n439 | n538) & (n37 | n527); - assign n333 = n462 | n538; - assign n334 = (n462 | n520) & (n424 | n219); - assign n335 = n258 | n490; - assign n336 = n328 & n329 & n330 & n331 & n332 & n333 & n334 & n335; - assign n337 = n53 | n520; - assign n338 = n43 | n203; - assign n339 = n420 | n425; - assign n340 = n337 & n338 & (n53 | n339); - assign n341 = n759 & n758 & (n462 | n527); - assign n342 = n602 & n757 & (n258 | n479); - assign n343 = n614 & n756 & (n43 | n497); - assign n344 = n755 & n754 & (n43 | n294); - assign n345 = n599 & n274 & n761 & n763 & n762 & n765 & n764 & n766; - assign n346 = n773 & n621 & n772 & n771; - assign n347 = n769 & n770 & n552 & n562 & n768 & n767; - assign n348 = n340 & n300 & n248 & n220 & n327 & n336 & n318 & n777; - assign n349 = n341 & n342 & n343 & n344 & n345 & n346 & n347 & n348; - assign n350 = n99 | n272; - assign n351 = n462 | n103; - assign n352 = n340 & (n459 | n219); - assign n353 = (n436 | n468) & (n33 | n467); - assign n354 = n94 & n582 & (n43 | n541); - assign n355 = n315 & n782 & (n258 | n511); - assign n356 = n739 & n780 & (n222 | n491); - assign n357 = n297 & n350 & n351 & n352 & n353 & n354 & n355 & n356; - assign n358 = (n436 | n532) & (n91 | n470); - assign n359 = n40 | n528; - assign n360 = (n43 | n515) & (n424 | n53); - assign n361 = n222 | n536; - assign n362 = n779 & n676 & (n100 | n142); - assign n363 = n778 & n760 & (n91 | n477); - assign n364 = n358 & n359 & n360 & n361 & n362 & n363; - assign n365 = (n222 | n524) & (n436 | n537); - assign n366 = n100 | n532; - assign n367 = (n91 | n498) & (n40 | n541); - assign n368 = (n33 | n154) & (n222 | n541); - assign n369 = n53 | n502; - assign n370 = n569 & (n436 | n157); - assign n371 = n365 & n366 & n367 & n368 & n369 & n370; - assign n372 = n801 & n800 & (n455 | n462); - assign n373 = n798 & n797 & (n272 | n530); - assign n374 = n364 & n371 & n357 & n804 & n88 & n55 & n116 & n803; - assign n375 = n795 & n794 & (n290 | n219); - assign n376 = n792 & n791 & (n100 | n493); - assign n377 = n788 & n789 & n787 & n786 & n785 & n217 & n784 & n783; - assign n378 = n372 & n373 & n374 & n375 & n376 & n377; - assign n379 = n462 | (n444 & n534); - assign n380 = n258 | n507; - assign n381 = n808 & (n53 | n471); - assign n382 = n809 & n810 & (n100 | n501); - assign n383 = n806 & n807 & (n53 | n461); - assign n384 = n759 & n805 & (n40 | n484); - assign n385 = n379 & n380 & n381 & n382 & n383 & n384; - assign n386 = n86 | n514; - assign n387 = n219 | n496; - assign n388 = n91 | n482; - assign n389 = n101 & (n272 | n519); - assign n390 = n40 | n514; - assign n391 = n37 | n154; - assign n392 = n430 | n100; - assign n393 = n596 & n597 & (n439 | n520); - assign n394 = n386 & n387 & n388 & n389 & n390 & n391 & n392 & n393; - assign n395 = (n222 | n447) & (n37 | n339); - assign n396 = n43 | (n454 & n510); - assign n397 = n811 & (n37 | n434); - assign n398 = n813 & (n462 | n546); - assign n399 = n812 & (n53 | n498); - assign n400 = n817 & n818 & (n439 | n103); - assign n401 = n816 & n815 & (n272 | n508); - assign n402 = n182 & n143 & n260 & n827 & n93 & n828 & n826 & n822; - assign n403 = n395 & n396 & n397 & n398 & n399 & n400 & n401 & n402; - assign n404 = n33 | n534; - assign n405 = (n37 | n502) & (n86 | n524); - assign n406 = (n100 | n518) & (n222 | n454); - assign n407 = n318 & n287 & n256 & n200 & n394 & n364 & n273; - assign n408 = n111 & n606 & n808 & n849 & n848 & n847 & n846 & n845; - assign n409 = n843 & n564 & n842 & n840 & n832 & n831 & n830 & n836; - assign n410 = (n86 | n533) & (n439 | n199); - assign n411 = n438 | n91; - assign n412 = n858 & n555 & (n43 | n533); - assign n413 = n721 & n857 & (n100 | n517); - assign n414 = n781 & n856 & (n462 | n499); - assign n415 = n855 & n854 & (n309 | n468); - assign n416 = n852 & n851 & (n33 | n444); - assign n417 = n132 & n83 & n175 & n868 & n867 & n869 & n866 & n862; - assign n418 = n410 & n411 & n412 & n413 & n414 & n415 & n416 & n417; - assign n419 = i_8_ | i_6_ | ~i_7_; - assign n420 = ~i_5_ | ~i_3_ | i_4_; - assign n421 = ~i_0_ | ~i_1_ | ~i_2_; - assign n422 = n420 | n421; - assign n423 = i_5_ | i_3_ | ~i_4_; - assign n424 = n421 | n423; - assign n425 = ~i_0_ | ~i_1_ | i_2_; - assign n426 = ~i_3_ | ~i_4_ | i_5_; - assign n427 = ~i_6_ | ~i_7_ | i_8_; - assign n428 = n426 | n427; - assign n429 = ~i_6_ | ~i_7_ | ~i_8_; - assign n430 = n420 | n429; - assign n431 = ~i_5_ | i_3_ | i_4_; - assign n432 = i_8_ | i_6_ | i_7_; - assign n433 = i_5_ | i_3_ | i_4_; - assign n434 = n425 | n433; - assign n435 = ~i_2_ | ~i_0_ | i_1_; - assign n436 = i_9_ | n435; - assign n437 = i_8_ | ~i_6_ | i_7_; - assign n438 = n433 | n435; - assign n439 = ~i_9_ | n437; - assign n440 = i_2_ | ~i_0_ | i_1_; - assign n441 = ~i_8_ | ~i_6_ | i_7_; - assign n442 = ~i_3_ | ~i_4_ | ~i_5_; - assign n443 = n419 | n442; - assign n444 = n431 | n440; - assign n445 = n433 | n440; - assign n446 = ~i_2_ | i_0_ | ~i_1_; - assign n447 = n419 | n420; - assign n448 = n431 | n437; - assign n449 = i_2_ | i_0_ | ~i_1_; - assign n450 = i_5_ | ~i_3_ | i_4_; - assign n451 = ~i_8_ | i_6_ | ~i_7_; - assign n452 = n450 | n451; - assign n453 = ~i_5_ | i_3_ | ~i_4_; - assign n454 = n429 | n453; - assign n455 = n423 | n449; - assign n456 = n423 | n441; - assign n457 = ~i_2_ | i_0_ | i_1_; - assign n458 = n429 | n431; - assign n459 = n433 | n457; - assign n460 = i_2_ | i_0_ | i_1_; - assign n461 = n450 | n460; - assign n462 = ~i_9_ | n432; - assign n463 = n423 | n429; - assign n464 = n431 | n460; - assign n465 = n427 | n433; - assign n466 = ~i_8_ | i_6_ | i_7_; - assign n467 = n421 | n450; - assign n468 = n423 | n437; - assign n469 = n421 | n431; - assign n470 = n425 | n426; - assign n471 = n425 | n453; - assign n472 = n433 | n441; - assign n473 = n426 | n440; - assign n474 = n453 | n466; - assign n475 = n423 | n451; - assign n476 = n432 | n450; - assign n477 = n426 | n457; - assign n478 = n420 | n460; - assign n479 = n420 | n435; - assign n480 = n432 | n453; - assign n481 = n426 | n429; - assign n482 = n421 | n426; - assign n483 = n421 | n453; - assign n484 = n427 | n453; - assign n485 = n425 | n431; - assign n486 = n431 | n446; - assign n487 = n420 | n427; - assign n488 = n431 | n449; - assign n489 = n453 | n457; - assign n490 = n425 | n450; - assign n491 = n420 | n466; - assign n492 = n429 | n450; - assign n493 = n441 | n453; - assign n494 = n442 | n449; - assign n495 = n429 | n433; - assign n496 = n426 | n460; - assign n497 = n431 | n466; - assign n498 = n431 | n435; - assign n499 = n449 | n453; - assign n500 = n440 | n450; - assign n501 = n442 | n451; - assign n502 = n431 | n457; - assign n503 = n423 | n440; - assign n504 = n426 | n449; - assign n505 = n435 | n453; - assign n506 = n420 | n437; - assign n507 = n442 | n460; - assign n508 = n419 | n423; - assign n509 = n423 | n425; - assign n510 = n437 | n453; - assign n511 = n420 | n457; - assign n512 = n441 | n450; - assign n513 = n419 | n426; - assign n514 = n432 | n433; - assign n515 = n433 | n451; - assign n516 = n435 | n450; - assign n517 = n426 | n451; - assign n518 = n433 | n437; - assign n519 = n451 | n453; - assign n520 = n421 | n433; - assign n521 = n437 | n442; - assign n522 = n426 | n435; - assign n523 = n442 | n457; - assign n524 = n429 | n442; - assign n525 = n427 | n442; - assign n526 = n420 | n446; - assign n527 = n440 | n442; - assign n528 = n431 | n451; - assign n529 = n426 | n441; - assign n530 = n420 | n451; - assign n531 = n437 | n450; - assign n532 = n427 | n431; - assign n533 = n427 | n450; - assign n534 = n433 | n446; - assign n535 = n419 | n453; - assign n536 = n432 | n442; - assign n537 = n423 | n427; - assign n538 = n446 | n453; - assign n539 = n449 | n450; - assign n540 = n433 | n449; - assign n541 = n426 | n432; - assign n542 = n419 | n431; - assign n543 = n426 | n437; - assign n544 = n450 | n466; - assign n545 = n446 | n450; - assign n546 = n440 | n453; - assign n547 = n425 | n442; - assign n548 = n462 | n259; - assign n549 = n439 | n504; - assign n550 = n91 | n503; - assign n551 = (n222 | n493) & (n424 | n33); - assign n552 = n53 | n479; - assign n553 = n436 | n493; - assign n554 = (n222 | n484) & (n33 | n339); - assign n555 = n456 | n86; - assign n556 = n315 & n338 & (n462 | n470); - assign n557 = n323 & n411 & (n33 | n471); - assign n558 = n40 | n157; - assign n559 = n91 | n473; - assign n560 = n558 & n559 & (n309 | n474); - assign n561 = n53 | n467; - assign n562 = n157 | n43; - assign n563 = n309 | n475; - assign n564 = n272 | n203; - assign n565 = n428 | n86; - assign n566 = n33 | n478; - assign n567 = (n219 | n467) & (n422 | n37); - assign n568 = (n37 | n424) & (n91 | n483); - assign n569 = n222 | n430; - assign n570 = n569 & (n428 | n222); - assign n571 = (n222 | n99) & (n258 | n485); - assign n572 = (n436 | n510) & (n434 | n439); - assign n573 = n99 | n436; - assign n574 = n33 | n509; - assign n575 = n572 & n573 & n571 & n233 & n570 & n574 & n568 & n567; - assign n576 = n96 | n40; - assign n577 = n576 & n226 & (n40 | n443); - assign n578 = (n33 | n445) & (n37 | n444); - assign n579 = n578 & (n439 | n54); - assign n580 = n309 | (n447 & n448); - assign n581 = n272 | n454; - assign n582 = n272 | n452; - assign n583 = n581 & n582 & (n272 | n493); - assign n584 = n443 | n272; - assign n585 = (n33 & n258) | n455; - assign n586 = (n33 | n511) & (n272 | n456); - assign n587 = n100 | n42; - assign n588 = n587 & n330 & (n100 | n203); - assign n589 = (n459 | n53) & (n100 | n458); - assign n590 = n463 | n86; - assign n591 = n290 | n462; - assign n592 = n590 & n591 & (n448 | n86); - assign n593 = n258 | n461; - assign n594 = n40 | n476; - assign n595 = n91 | n527; - assign n596 = n458 | n43; - assign n597 = n439 | n505; - assign n598 = n40 | n524; - assign n599 = n40 | n465; - assign n600 = n91 | n262; - assign n601 = n258 | n498; - assign n602 = n436 | n223; - assign n603 = n40 | n521; - assign n604 = (n258 | n477) & (n309 | n510); - assign n605 = n439 | n38; - assign n606 = n430 | n436; - assign n607 = n100 | n481; - assign n608 = n607 & (n100 | n484); - assign n609 = n100 | n463; - assign n610 = n549 & n584 & (n43 | n521); - assign n611 = n422 | n258; - assign n612 = n222 | n456; - assign n613 = n612 & (n439 | n485); - assign n614 = n219 | n520; - assign n615 = n436 | n518; - assign n616 = n614 & n615 & (n219 | n470); - assign n617 = n40 | n508; - assign n618 = n617 & (n219 | n503); - assign n619 = n86 | n472; - assign n620 = n222 | n443; - assign n621 = n462 | n339; - assign n622 = (n436 | n42) & (n439 | n522); - assign n623 = n219 | n259; - assign n624 = n40 | (n491 & n529); - assign n625 = n391 & n624 & (n436 | n514); - assign n626 = (n40 | n458) & (n33 | n500); - assign n627 = (n272 | n497) & (n258 | n262); - assign n628 = (n33 | n38) & (n272 | n87); - assign n629 = (n33 | n502) & (n100 | n468); - assign n630 = (n33 | n461) & (n91 | n478); - assign n631 = (n219 | n482) & (n86 | n294); - assign n632 = n462 | n467; - assign n633 = n632 & (n43 | n495); - assign n634 = n222 | n501; - assign n635 = (n436 | n443) & (n222 | n515); - assign n636 = (n37 | n479) & (n462 | n92); - assign n637 = (n40 | n517) & (n37 | n516); - assign n638 = n309 | (n491 & n497); - assign n639 = (n272 | n518) & (n37 | n499); - assign n640 = (n100 | n519) & (n219 | n489); - assign n641 = n100 | n87; - assign n642 = n91 | n251; - assign n643 = (n258 | n464) & (n86 | n535); - assign n644 = n158 & n161 & n155 & n71 & n35 & n643; - assign n645 = n436 | n454; - assign n646 = n43 | n87; - assign n647 = n272 | n310; - assign n648 = n86 | n541; - assign n649 = n439 | n502; - assign n650 = n43 | (n493 & n513); - assign n651 = (n258 | n520) & (n43 | n475); - assign n652 = n53 | n470; - assign n653 = n652 & (n439 | n470); - assign n654 = n222 | n532; - assign n655 = n654 & (n91 | n509); - assign n656 = (n434 | n91) & (n222 | n528); - assign n657 = (n436 | n536) & (n222 | n87); - assign n658 = n436 | n484; - assign n659 = n658 & (n462 | n516); - assign n660 = n462 | n154; - assign n661 = n659 & n660 & n657 & n656 & n655 & n653 & n651 & n650; - assign n662 = (n40 | n42) & (n436 | n465); - assign n663 = n40 | (n510 & n537); - assign n664 = (n37 | n445) & (n40 | n448); - assign n665 = n258 | n54; - assign n666 = n665 & n664 & (n309 | n536); - assign n667 = (n272 | n517) & (n37 | n34); - assign n668 = (n100 | n529) & (n53 | n523); - assign n669 = n462 | n199; - assign n670 = n669 & (n100 | n513); - assign n671 = (n37 | n503) & (n33 | n527); - assign n672 = (n219 | n538) & (n444 | n91); - assign n673 = (n272 | n524) & (n258 | n34); - assign n674 = n272 | n463; - assign n675 = (n219 | n526) & (n309 | n157); - assign n676 = n439 | n507; - assign n677 = (n439 | n479) & (n258 | n150); - assign n678 = n309 | n537; - assign n679 = n436 | n531; - assign n680 = n430 | n43; - assign n681 = n309 | n530; - assign n682 = n272 | n492; - assign n683 = n309 | n508; - assign n684 = n219 | n483; - assign n685 = (n33 | n545) & (n439 | n473); - assign n686 = n33 | n488; - assign n687 = n43 | n528; - assign n688 = n687 & (n33 | n490); - assign n689 = n53 | n494; - assign n690 = n689 & n688 & (n53 | n527); - assign n691 = n462 | n540; - assign n692 = n691 & n623 & (n272 | n535); - assign n693 = (n219 | n509) & (n37 | n523); - assign n694 = (n462 | n509) & (n43 | n518); - assign n695 = (n40 | n487) & (n53 | n505); - assign n696 = (n444 | n53) & (n40 | n544); - assign n697 = n390 & n696 & (n428 | n309); - assign n698 = (n37 | n538) & (n258 | n545); - assign n699 = n179 & (n91 | n494); - assign n700 = (n439 | n262) & (n272 | n41); - assign n701 = (n91 | n199) & (n258 | n523); - assign n702 = (n258 | n38) & (n100 | n476); - assign n703 = n619 & (n86 | n518); - assign n704 = (n222 | n448) & (n43 | n142); - assign n705 = (n436 | n530) & (n462 | n522); - assign n706 = (n436 | n515) & (n219 | n516); - assign n707 = n706 & (n436 | n310); - assign n708 = n550 & n60 & n703 & n702 & n701 & n705 & n704 & n707; - assign n709 = (n309 | n512) & (n53 | n545); - assign n710 = n40 | n515; - assign n711 = n351 & (n99 | n86); - assign n712 = n620 & n711 & (n43 | n543); - assign n713 = (n272 | n472) & (n91 | n54); - assign n714 = n309 | n535; - assign n715 = n714 & (n430 | n40); - assign n716 = (n219 | n494) & (n33 | n540); - assign n717 = n207 & n123 & n104 & n39 & n716 & n715; - assign n718 = (n40 | n506) & (n258 | n470); - assign n719 = (n272 | n542) & (n53 | n499); - assign n720 = (n436 | n517) & (n43 | n544); - assign n721 = n53 | n477; - assign n722 = (n53 | n482) & (n439 | n150); - assign n723 = (n439 | n483) & (n422 | n219); - assign n724 = (n43 | n508) & (n424 | n258); - assign n725 = (n33 & n258) | n547; - assign n726 = n222 | (n487 & n543); - assign n727 = (n33 | n516) & (n439 | n490); - assign n728 = n598 & (n436 | n528); - assign n729 = n595 & (n462 | n500); - assign n730 = (n40 | n535) & (n37 | n546); - assign n731 = n186 & (n309 | n142); - assign n732 = n309 | (n255 & n519); - assign n733 = (n430 | n272) & (n309 | n514); - assign n734 = n100 | n524; - assign n735 = n734 & n733 & (n272 | n475); - assign n736 = (n258 | n489) & (n100 | n536); - assign n737 = (n258 | n103) & (n462 | n38); - assign n738 = n444 | n219; - assign n739 = n462 | n503; - assign n740 = n386 & (n258 | n160); - assign n741 = (n422 | n33) & (n43 | n524); - assign n742 = (n222 | n521) & (n448 | n43); - assign n743 = n436 | (n495 & n512); - assign n744 = n681 & (n37 | n494); - assign n745 = (n219 | n523) & (n272 | n541); - assign n746 = (n37 | n496) & (n258 | n199); - assign n747 = n612 & (n434 | n258); - assign n748 = (n219 | n502) & (n272 | n537); - assign n749 = n219 | n522; - assign n750 = n219 | n262; - assign n751 = (n222 | n506) & (n43 | n472); - assign n752 = n595 & n194 & (n436 | n448); - assign n753 = n462 | n471; - assign n754 = (n258 | n483) & (n43 | n531); - assign n755 = n424 | n91; - assign n756 = n222 | (n529 & n530); - assign n757 = (n434 | n219) & (n222 | n542); - assign n758 = (n37 | n498) & (n436 | n294); - assign n759 = n258 | n546; - assign n760 = n40 | n472; - assign n761 = n760 & (n445 | n258); - assign n762 = (n309 | n525) & (n439 | n445); - assign n763 = (n309 | n493) & (n462 | n251); - assign n764 = n118 & (n219 | n534); - assign n765 = n272 | (n157 & n506); - assign n766 = n600 & n607 & (n33 | n539); - assign n767 = (n86 | n536) & (n37 | n511); - assign n768 = (n219 | n160) & (n86 | n517); - assign n769 = n222 | n519; - assign n770 = n222 | n525; - assign n771 = n40 | (n468 & n543); - assign n772 = (n91 | n486) & (n33 | n526); - assign n773 = n100 | (n495 & n544); - assign n774 = (n436 | n542) & (n222 | n517); - assign n775 = (n439 | n34) & (n40 | n463); - assign n776 = n258 | n534; - assign n777 = n189 & n147 & n77 & n776 & n775 & n774; - assign n778 = n309 | n476; - assign n779 = n436 | n519; - assign n780 = n680 & n652 & (n33 | n483); - assign n781 = n439 | n499; - assign n782 = n781 & n734 & (n37 | n486); - assign n783 = (n422 | n53) & (n43 | n517); - assign n784 = (n222 | n452) & (n258 | n469); - assign n785 = (n222 | n535) & (n462 | n490); - assign n786 = (n436 | n475) & (n91 | n522); - assign n787 = (n438 | n219) & (n33 | n498); - assign n788 = (n219 | n546) & (n37 | n500); - assign n789 = n445 | n91; - assign n790 = (n447 | n272) & (n37 | n504); - assign n791 = n184 & n790 & (n40 | n87); - assign n792 = (n53 & n258) | n488; - assign n793 = (n100 | n310) & (n91 | n502); - assign n794 = n793 & (n86 | n223); - assign n795 = n86 | (n491 & n529); - assign n796 = n558 & (n86 | n537); - assign n797 = n769 & n796 & (n43 | n542); - assign n798 = n753 & (n258 | n516); - assign n799 = (n258 | n526) & (n100 | n512); - assign n800 = n691 & n799 & (n272 | n531); - assign n801 = (n272 | n491) & (n33 | n504); - assign n802 = (n86 | n310) & (n37 | n199); - assign n803 = n44 & n802 & (n439 | n477); - assign n804 = n241 & n204 & n282; - assign n805 = n658 & n755 & (n91 | n500); - assign n806 = (n459 | n91) & (n53 | n504); - assign n807 = n57 & (n219 | n471); - assign n808 = n422 | n439; - assign n809 = n749 & (n222 | n465); - assign n810 = (n428 | n43) & (n462 | n150); - assign n811 = (n37 | n485) & (n222 | n533); - assign n812 = n436 | (n463 & n524); - assign n813 = n40 | (n142 & n530); - assign n814 = (n445 | n462) & (n444 | n258); - assign n815 = n814 & (n443 | n309); - assign n816 = (n272 | n481) & (n309 | n529); - assign n817 = (n258 | n478) & (n53 | n511); - assign n818 = n68 & n62 & (n439 | n160); - assign n819 = (n467 | n91) & (n462 | n482); - assign n820 = n687 & n819 & (n439 | n509); - assign n821 = (n33 | n473) & (n53 | n516); - assign n822 = n821 & n820 & (n40 | n531); - assign n823 = n91 | n499; - assign n824 = n823 & n689 & (n53 | n540); - assign n825 = (n436 | n543) & (n86 | n495); - assign n826 = n825 & n824 & (n258 | n505); - assign n827 = (n42 | n86) & (n428 | n272); - assign n828 = n394 & n357 & n385 & n311 & n295 & n336; - assign n829 = (n43 | n514) & (n462 | n483); - assign n830 = n684 & n829 & (n443 | n43); - assign n831 = (n91 | n490) & (n222 | n41); - assign n832 = (n436 | n501) & (n462 | n485); - assign n833 = (n436 | n41) & (n33 | n522); - assign n834 = n645 & n833 & (n438 | n258); - assign n835 = n603 & (n40 | n474); - assign n836 = n835 & n834 & (n309 | n521); - assign n837 = (n219 | n499) & (n272 | n142); - assign n838 = n683 & n837 & (n462 | n262); - assign n839 = (n272 | n458) & (n455 | n91); - assign n840 = n839 & n838 & (n439 | n488); - assign n841 = n647 & (n100 | n223); - assign n842 = n609 & n841 & (n439 | n511); - assign n843 = n33 | (n459 & n464); - assign n844 = (n436 | n506) & (n53 | n490); - assign n845 = n565 & n844 & (n43 | n41); - assign n846 = (n219 | n251) & (n91 | n505); - assign n847 = n37 | (n54 & n251); - assign n848 = (n439 | n540) & (n430 | n309); - assign n849 = n611 & (n462 | n464); - assign n850 = (n436 | n535) & (n43 | n487); - assign n851 = n275 & n850 & (n40 | n452); - assign n852 = n617 & (n40 | n475); - assign n853 = (n96 | n309) & (n40 | n310); - assign n854 = n853 & (n309 | n492); - assign n855 = (n258 | n538) & (n309 | n544); - assign n856 = (n219 | n504) & (n462 | n494); - assign n857 = n37 | n455; - assign n858 = n43 | n536; - assign n859 = (n37 & n53) | n547; - assign n860 = n779 & n859 & (n222 | n508); - assign n861 = n53 | (n154 & n259); - assign n862 = n861 & n860 & (n40 | n512); - assign n863 = (n53 | n538) & (n439 | n500); - assign n864 = n863 & (n100 | n543); - assign n865 = (n462 | n489) & (n100 | n510); - assign n866 = n865 & n864 & (n448 | n100); - assign n867 = (n436 | n481) & (n462 | n34); - assign n868 = (n436 | n474) & (n258 | n494); - assign n869 = n385 & n371 & n273 & n291 & n232 & n327; -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/ex5p/ex5p.v b/fpga_flow/benchmarks/Verilog/MCNC/ex5p/ex5p.v deleted file mode 100644 index 098a862f5..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/ex5p/ex5p.v +++ /dev/null @@ -1,588 +0,0 @@ -// Benchmark "TOP" written by ABC on Mon Feb 4 17:31:57 2019 - -module ex5p ( - i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, - o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, - o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, - o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, - o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_, - o_41_, o_42_, o_43_, o_44_, o_45_, o_46_, o_47_, o_48_, o_49_, o_50_, - o_51_, o_52_, o_53_, o_54_, o_55_, o_56_, o_57_, o_58_, o_59_, o_60_, - o_61_, o_62_ ); - input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_; - output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, - o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, - o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, - o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_, - o_41_, o_42_, o_43_, o_44_, o_45_, o_46_, o_47_, o_48_, o_49_, o_50_, - o_51_, o_52_, o_53_, o_54_, o_55_, o_56_, o_57_, o_58_, o_59_, o_60_, - o_61_, o_62_; - wire n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, - n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, - n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, - n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, - n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, - n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, - n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, - n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, - n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, - n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, - n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, - n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, - n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, - n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, - n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, - n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, - n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, - n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, - n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, - n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, - n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, - n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, - n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, - n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, - n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, - n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, - n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, - n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, - n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, - n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, - n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, - n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, - n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, - n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, - n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, - n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, - n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, - n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, - n589, n590, n591, n592, n593, n594, n595, n596, n597; - assign o_0_ = ~n365; - assign o_1_ = ~n361; - assign o_2_ = ~n403; - assign o_3_ = ~n370; - assign o_4_ = ~n450; - assign o_5_ = ~n357; - assign o_6_ = ~n136; - assign o_7_ = ~n180; - assign o_8_ = ~n452; - assign o_9_ = ~n491; - assign o_10_ = ~n139; - assign o_11_ = ~n179; - assign o_12_ = ~n385; - assign o_13_ = ~n471; - assign o_14_ = ~n507; - assign o_15_ = ~n138; - assign o_16_ = ~n407; - assign o_17_ = ~n354; - assign o_18_ = ~n421; - assign o_19_ = ~n420; - assign o_20_ = ~n142; - assign o_21_ = ~n145; - assign o_22_ = ~n148; - assign o_23_ = ~n352; - assign o_24_ = ~n504; - assign o_25_ = ~n200; - assign o_26_ = ~n151; - assign o_27_ = ~n260; - assign o_28_ = ~n556; - assign o_29_ = ~n506; - assign o_30_ = ~n150; - assign o_31_ = ~n347; - assign o_32_ = ~n344; - assign o_33_ = ~n340; - assign o_34_ = ~n336; - assign o_35_ = ~n332; - assign o_36_ = ~n328; - assign o_37_ = ~n321; - assign o_38_ = ~n314; - assign o_39_ = ~n308; - assign o_40_ = ~n303; - assign o_41_ = ~n296; - assign o_42_ = ~n291; - assign o_43_ = ~n284; - assign o_44_ = ~n276; - assign o_45_ = ~n274; - assign o_46_ = ~n268; - assign o_47_ = ~n264; - assign o_48_ = ~n259; - assign o_49_ = ~n257; - assign o_50_ = ~n252; - assign o_51_ = ~n245; - assign o_52_ = ~n238; - assign o_53_ = ~n232; - assign o_54_ = ~n226; - assign o_55_ = ~n220; - assign o_56_ = ~n214; - assign o_57_ = ~n205; - assign o_58_ = ~n197; - assign o_59_ = ~n189; - assign o_60_ = ~n182; - assign o_61_ = ~n173; - assign o_62_ = ~n164; - assign n134 = n155 | n439; - assign n135 = n155 | n441; - assign n136 = n134 & n135; - assign n137 = n436 | n339; - assign n138 = n445 | n339; - assign n139 = n137 & n138; - assign n140 = n462 | n152; - assign n141 = n463 | n152; - assign n142 = n140 & n141; - assign n143 = n439 | n152; - assign n144 = n441 | n152; - assign n145 = n143 & n144; - assign n146 = n434 | n152; - assign n147 = n446 | n152; - assign n148 = n146 & n147; - assign n149 = n434 | n373; - assign n150 = n434 | n369; - assign n151 = n149 & n150; - assign n152 = i_2_ | ~i_0_ | i_1_; - assign n153 = n152 | ~n381; - assign n154 = ~i_3_ | ~i_4_ | ~i_5_; - assign n155 = i_0_ | i_1_ | ~i_2_; - assign n156 = n154 | n155; - assign n157 = i_0_ | i_1_ | i_2_; - assign n158 = n157 | ~n366; - assign n159 = n373 & n338; - assign n160 = n514 & n505 & n363; - assign n161 = n515 & n339 & n269 & n195 & n496; - assign n162 = n179 & n458 & n408 & n461 & n374; - assign n163 = n150 & n516 & n517 & n176 & n454; - assign n164 = n159 & n160 & n161 & n162 & n163; - assign n165 = n398 & n533 & n535; - assign n166 = n523 & n524; - assign n167 = n412 & n503; - assign n168 = n504 & n363; - assign n169 = n450 & n556; - assign n170 = n372 & n555 & n180; - assign n171 = n254 & n243 & n400; - assign n172 = n518 & n192 & n554; - assign n173 = n165 & n166 & n167 & n168 & n169 & n170 & n171 & n172; - assign n174 = n208 & n309 & n563 & n421 & n254 & n518; - assign n175 = n410 & n560 & n192 & n165 & n457 & n461 & n150 & n516; - assign n176 = n452 & n451; - assign n177 = n362 & n552 & n454; - assign n178 = n369 | n462; - assign n179 = n436 | n409; - assign n180 = n436 | n270; - assign n181 = n369 | n463; - assign n182 = n174 & n175 & n176 & n177 & n178 & n179 & n180 & n181; - assign n183 = n411 & (n157 | ~n382) & n412; - assign n184 = n548 & n298; - assign n185 = n418 & (n239 | n409); - assign n186 = n569 & n570 & n310 & n345 & n169 & n334 & n255 & n163; - assign n187 = n265 & n573 & n170 & n203; - assign n188 = n594 & n493 & n487 & n483 & n408 & n397 & ~n383 & n387; - assign n189 = n183 & n184 & n185 & n186 & n187 & n188; - assign n190 = n576 & n575 & n532 & n451 & n414 & n140 & n297 & ~n367; - assign n191 = n493 & ~n383 & n492; - assign n192 = n405 & n550 & n404 & n145 & n551 & n549; - assign n193 = n563 & n272; - assign n194 = n421 & n485 & n487; - assign n195 = n478 & n481 & n475 & n477; - assign n196 = n351 & n158 & (n154 | n157); - assign n197 = n190 & n191 & n192 & n193 & n194 & n195 & n138 & n196; - assign n198 = n470 & n468; - assign n199 = n150 & n536; - assign n200 = n270 | n443; - assign n201 = n261 & n471 & n394; - assign n202 = n228 & n414 & (n339 | ~n382); - assign n203 = n179 & n572; - assign n204 = n221 & n215 & n422 & n185 & n423 & n300; - assign n205 = n198 & n199 & n200 & n201 & n166 & n202 & n203 & n204; - assign n206 = n578 & n579 & n554 & n169; - assign n207 = n310 & n577; - assign n208 = n496 & n562; - assign n209 = n580 & ~n395 & n491; - assign n210 = n149 & n378 & n370 & n419 & n306; - assign n211 = n501 & n563; - assign n212 = n180 & n518; - assign n213 = n228 & n171 & n467 & n196 & n594 & n376 & n534 & n471; - assign n214 = n206 & n207 & n208 & n209 & n210 & n211 & n212 & n213; - assign n215 = n563 & n183; - assign n216 = n537 & ~n367 & n451; - assign n217 = n534 & n275 & n139 & n142; - assign n218 = n570 & n571 & n184 & n581 & n337 & n582; - assign n219 = n156 & n171 & n427 & n200; - assign n220 = n215 & n216 & n180 & n166 & n217 & n218 & n219; - assign n221 = n396 & n180 & n159; - assign n222 = n474 & n247; - assign n223 = n519 & n348 & n494; - assign n224 = n472 & n470; - assign n225 = n572 & n575 & n478 & n538 & n158 & n458 & n534 & n468; - assign n226 = n209 & n219 & n193 & n221 & n222 & n223 & n224 & n225; - assign n227 = n449 & n452; - assign n228 = n525 & n526; - assign n229 = n146 & n527 & n528 & n529 & n530; - assign n230 = n391 & n392 & (n393 | n339); - assign n231 = n476 & n583 & n537 & n137 & n141 & n534; - assign n232 = n174 & n218 & n227 & n228 & n229 & n230 & n231; - assign n233 = n351 & n215; - assign n234 = n254 & n494 & n559 & n509 & n262 & n292 & n426; - assign n235 = n387 & n491; - assign n236 = n384 & n385 & (n373 | n386); - assign n237 = n510 & n548; - assign n238 = n233 & n234 & n224 & n235 & n236 & n186 & n162 & n237; - assign n239 = ~n381 & ~n382; - assign n240 = n155 | n239; - assign n241 = n255 & n240 & n389 & n387 & n584 & n491; - assign n242 = n488 & n489; - assign n243 = n421 & n482; - assign n244 = n254 & n494 & n453; - assign n245 = n175 & n212 & n227 & n233 & n241 & n242 & n243 & n244; - assign n246 = n560 & n203; - assign n247 = n408 & ((~n381 & ~n382) | n409); - assign n248 = n200 & n483 & n486; - assign n249 = n540 & n539; - assign n250 = n524 & n192 & n412 & n501 & n168 & n288 & n293; - assign n251 = n535 & n543 & n546 & n477 & n380 & n533; - assign n252 = n246 & n247 & n248 & n249 & n250 & n251; - assign n253 = n288 & n248 & n342 & n586 & n266; - assign n254 = n155 | n446; - assign n255 = n155 | n443; - assign n256 = n350 & n158 & n351 & n520; - assign n257 = n193 & n235 & n253 & n254 & n255 & n256; - assign n258 = n254 & n241 & n135 & n134; - assign n259 = n258 & n253 & n242 & n160; - assign n260 = n443 | n339; - assign n261 = n434 | n339; - assign n262 = n429 & n281 & n248; - assign n263 = n417 & n224 & (n393 | n270); - assign n264 = n260 & n190 & n139 & n261 & n262 & n250 & n263; - assign n265 = n421 & n156 & n468 & n200; - assign n266 = n210 & n585 & n345 & n207; - assign n267 = n196 & n496 & n160 & n396 & n180 & n515; - assign n268 = n265 & n191 & n206 & n263 & n266 & n267; - assign n269 = n493 & n492 & n194 & n196 & ~n383; - assign n270 = i_2_ | i_0_ | ~i_1_; - assign n271 = n260 & n261; - assign n272 = n500 & n330 & n420 & n411 & n497 & n498; - assign n273 = n577 & n206 & n210; - assign n274 = n269 & n168 & n270 & n271 & n272 & n217 & n273; - assign n275 = n530 & n568 & n146 & n529; - assign n276 = n211 & n273 & n161 & n275; - assign n277 = n567 & n530 & n482 & ~n415 & n137 & n228 & ~n395; - assign n278 = n196 & n330 & n451 & n431 & n254 & n491 & n588 & n589; - assign n279 = n484 & n363 & n486 & n502; - assign n280 = n180 & (n270 | n355); - assign n281 = n476 & n583 & n468 & n396; - assign n282 = n298 & n417 & n222; - assign n283 = n511 & n405 & n499 & n508 & n374 & n377 & n179 & n595; - assign n284 = n277 & n278 & n249 & n279 & n280 & n281 & n282 & n283; - assign n285 = n477 & n394 & n471 & n378; - assign n286 = n413 & n423 & n590 & n138 & n144 & n228; - assign n287 = n179 & n553; - assign n288 = n422 & n243; - assign n289 = n419 & n420 & n579; - assign n290 = n549 & n406 & n410 & n563 & n569 & n411 & n380 & n596; - assign n291 = n285 & n286 & n248 & n278 & n287 & n288 & n289 & n290; - assign n292 = n288 & n404 & (n152 | ~n366); - assign n293 = n326 & n426 & n258; - assign n294 = n585 & n586 & n345 & n248; - assign n295 = n547 & n405 & n560 & n542 & n543 & n546; - assign n296 = n292 & n293 & n294 & n193 & n207 & n223 & n295; - assign n297 = n458 & n246 & n247; - assign n298 = n402 & n547; - assign n299 = n356 & n550 & n564; - assign n300 = n254 & n400 & n543; - assign n301 = n405 & n318 & n473 & n536 & n476 & n469 & n474 & n409; - assign n302 = n482 & n411 & n153 & n339 & n380 & n330 & n523; - assign n303 = n275 & n297 & n298 & n299 & n300 & n279 & n301 & n302; - assign n304 = n573 & n185 & n581 & n587 & n315 & n167 & n203 & n591; - assign n305 = n153 & n531; - assign n306 = n356 & n564 & n184; - assign n307 = n470 & n142 & n145 & n194 & n261 & ~n382; - assign n308 = n277 & n285 & n304 & n305 & n306 & n258 & n307; - assign n309 = n196 & n492 & n561; - assign n310 = n142 & n275 & ~n415; - assign n311 = n149 & n298 & n419; - assign n312 = n147 & n370 & n508; - assign n313 = n327 & n503 & n363; - assign n314 = n309 & n310 & n206 & n294 & n311 & n312 & n208 & n313; - assign n315 = n575 & n576 & n457 & n454; - assign n316 = n448 & n513 & n459; - assign n317 = n447 & n512 & n136 & n145 & n526 & n495 & n460; - assign n318 = n525 & n478 & n481; - assign n319 = n405 & n562 & n578 & n230 & n532 & n371; - assign n320 = n541 & n556 & n147 & n449 & n510 & n551 & n565 & n597; - assign n321 = n315 & n316 & n317 & n211 & n234 & n318 & n319 & n320; - assign n322 = n477 & n550 & n342 & n318 & n311 & n471 & n470 & n592; - assign n323 = n146 & n590; - assign n324 = n561 & n548 & n531 & n491 & ~n382 & n387; - assign n325 = n356 & n507; - assign n326 = n242 & n256; - assign n327 = n482 & n254; - assign n328 = n322 & n323 & n193 & n324 & n325 & n326 & n327 & n194; - assign n329 = n325 & n353 & (n152 | ~n381); - assign n330 = n515 & n495; - assign n331 = n531 & n486 & n485; - assign n332 = n243 & n293 & n322 & n323 & n329 & n330 & n211 & n331; - assign n333 = n143 & (n152 | ~n382); - assign n334 = n416 & (n270 | ~n366) & n417; - assign n335 = n518 & n398 & n243 & n180 & n254 & n508; - assign n336 = n286 & n304 & n324 & n298 & n333 & n334 & n335; - assign n337 = n572 & n578 & n287; - assign n338 = n152 & n511 & n312 & n402 & n512 & n513; - assign n339 = ~i_2_ | i_0_ | ~i_1_; - assign n340 = n216 & n301 & n211 & n337 & n338 & n208 & n339 & n269; - assign n341 = n550 & n311 & n329; - assign n342 = n206 & n223; - assign n343 = n180 & n482; - assign n344 = n279 & n341 & n258 & n342 & n326 & n272 & n165 & n343; - assign n345 = n202 & n413 & n567; - assign n346 = n523 & n505 & n229 & n305 & n330 & n363 & ~n415; - assign n347 = n345 & n206 & n171 & n334 & n224 & n262 & n341 & n346; - assign n348 = n157 | n370; - assign n349 = n519 & n520; - assign n350 = n154 | n157; - assign n351 = n445 | n157; - assign n352 = n348 & n349 & n350 & n351; - assign n353 = n152 | ~n366; - assign n354 = n153 & n353; - assign n355 = n435 | n442; - assign n356 = n442 | n444; - assign n357 = n355 & n356; - assign n358 = n157 | n462; - assign n359 = n488 & n515 & n178 & n552 & n316 & n396 & n486 & n593; - assign n360 = (~n366 & ~n381) | n438; - assign n361 = n143 & n358 & n134 & n140 & n359 & n360; - assign n362 = n409 | n463; - assign n363 = n358 & n506; - assign n364 = n468 & n483 & n489 & n142 & n509 & n465; - assign n365 = n181 & n362 & n363 & n317 & n359 & n364; - assign n366 = i_3_ & i_4_ & ~i_5_; - assign n367 = ~n369 & (~n154 | n366); - assign n368 = n369 | (n356 & n378); - assign n369 = ~i_0_ | ~i_1_ | ~i_2_; - assign n370 = n438 | n444; - assign n371 = n368 & (n369 | n370); - assign n372 = n445 | n373; - assign n373 = ~i_2_ | ~i_0_ | i_1_; - assign n374 = n372 & ((n154 & ~n366) | n373); - assign n375 = n339 | n239; - assign n376 = n464 & n465; - assign n377 = n376 & (n270 | n154); - assign n378 = n440 | n444; - assign n379 = n270 | (n356 & n378); - assign n380 = n180 & (n270 | ~n381); - assign n381 = ~i_5_ & ~i_3_ & i_4_; - assign n382 = i_5_ & ~i_3_ & i_4_; - assign n383 = ~n155 & (n381 | n382); - assign n384 = n373 | n355; - assign n385 = n436 | n373; - assign n386 = n435 | n440; - assign n387 = n155 | n436; - assign n388 = n387 & (n155 | ~n381); - assign n389 = n155 | (n355 & n386); - assign n390 = ~n157 & (~n154 | n366); - assign n391 = n378 | n339; - assign n392 = n140 & n138 & n566; - assign n393 = n154 & ~n366; - assign n394 = n260 & n376 & (n393 | n270); - assign n395 = ~n339 & (n381 | n382); - assign n396 = n270 | n439; - assign n397 = n396 & (n270 | ~n382); - assign n398 = n198 & n397 & (n270 | ~n381); - assign n399 = n155 | ~n382; - assign n400 = n136 & (n239 | n155); - assign n401 = n369 | (n355 & n386); - assign n402 = n443 | n373; - assign n403 = n435 | n438; - assign n404 = n149 & n402 & (n373 | n403); - assign n405 = n236 & (n239 | n373); - assign n406 = n372 & (n393 | n373); - assign n407 = n409 | n445; - assign n408 = n459 & n460; - assign n409 = ~i_0_ | ~i_1_ | i_2_; - assign n410 = n407 & n408 & (n393 | n409); - assign n411 = n436 | n157; - assign n412 = n157 | ~n381; - assign n413 = n137 & (n339 | ~n381); - assign n414 = n391 & n565 & n534; - assign n415 = ~n339 & (~n154 | n366); - assign n416 = n271 & n377; - assign n417 = n471 & n379; - assign n418 = n407 & n455 & n456; - assign n419 = n385 & (n373 | ~n381); - assign n420 = n412 & (n157 | ~n382); - assign n421 = n155 | ~n366; - assign n422 = n421 & (n155 | n154); - assign n423 = n339 | (n239 & n393); - assign n424 = n373 | n393; - assign n425 = n155 | (n356 & n378); - assign n426 = n425 & (n155 | n370); - assign n427 = n434 | n270; - assign n428 = n270 | (n386 & n403); - assign n429 = n280 & n427 & n428; - assign n430 = n409 | (n434 & n443); - assign n431 = n386 & n355 & n430; - assign n432 = i_3_ | i_4_ | i_5_; - assign n433 = ~i_6_ | ~i_7_; - assign n434 = n432 | n433; - assign n435 = i_3_ | i_4_ | ~i_5_; - assign n436 = n433 | n435; - assign n437 = i_5_ | ~i_3_ | i_4_; - assign n438 = i_6_ | i_7_; - assign n439 = n437 | n438; - assign n440 = i_6_ | ~i_7_; - assign n441 = n437 | n440; - assign n442 = ~i_6_ | i_7_; - assign n443 = n432 | n442; - assign n444 = ~i_5_ | ~i_3_ | i_4_; - assign n445 = n433 | n444; - assign n446 = n433 | n437; - assign n447 = n369 | n441; - assign n448 = n369 | n439; - assign n449 = n369 | n446; - assign n450 = n437 | n442; - assign n451 = n447 & n448 & n449 & n450; - assign n452 = n436 | n369; - assign n453 = n369 | n445; - assign n454 = ~n367 & n453; - assign n455 = n409 | n356; - assign n456 = n409 | n378; - assign n457 = n409 | n446; - assign n458 = n457 & n418; - assign n459 = n439 | n409; - assign n460 = n441 | n409; - assign n461 = n403 & n431; - assign n462 = n432 | n438; - assign n463 = n432 | n440; - assign n464 = n339 | n462; - assign n465 = n339 | n463; - assign n466 = n403 | n339; - assign n467 = n466 & n271; - assign n468 = n270 | n441; - assign n469 = n468 & n396; - assign n470 = n270 | n446; - assign n471 = n270 | n445; - assign n472 = n270 | n370; - assign n473 = n470 & n379 & n471 & n472; - assign n474 = n270 | ~n366; - assign n475 = n474 & n473; - assign n476 = n270 | ~n382; - assign n477 = n476 & n469; - assign n478 = n377 & n467; - assign n479 = n386 | n339; - assign n480 = n355 | n339; - assign n481 = n479 & n375 & n137 & n480; - assign n482 = n155 | n445; - assign n483 = n270 | n463; - assign n484 = n427 & n200 & n483; - assign n485 = n484 & n380; - assign n486 = n270 | n462; - assign n487 = n486 & n156; - assign n488 = n155 | n462; - assign n489 = n155 | n463; - assign n490 = n255 & n242; - assign n491 = n434 | n155; - assign n492 = n387 & n491 & n490; - assign n493 = n136 & n327; - assign n494 = n446 | n157; - assign n495 = n441 | n157; - assign n496 = n494 & n495; - assign n497 = n355 | n157; - assign n498 = n386 | n157; - assign n499 = n411 & n497 & n498; - assign n500 = n403 | n157; - assign n501 = n500 & n499; - assign n502 = n434 | n157; - assign n503 = n502 & n501; - assign n504 = n443 | n157; - assign n505 = n412 & n504 & n503; - assign n506 = n157 | n463; - assign n507 = n445 | n152; - assign n508 = n378 & n325; - assign n509 = n441 | n373; - assign n510 = n439 | n373; - assign n511 = n509 & n510; - assign n512 = n373 | n463; - assign n513 = n373 | n462; - assign n514 = n157 | ~n382; - assign n515 = n439 | n157; - assign n516 = n369 | n443; - assign n517 = n393 | n409; - assign n518 = n486 & n156 & n484; - assign n519 = n378 | n157; - assign n520 = n356 | n157; - assign n521 = n584 & n491 & n255; - assign n522 = n521 & n489 & n488 & n349 & n351 & n388 & n389 & ~n390; - assign n523 = n494 & n522; - assign n524 = n514 & n330; - assign n525 = n439 | n339; - assign n526 = n441 | n339; - assign n527 = n355 | n152; - assign n528 = n386 | n152; - assign n529 = n403 | n152; - assign n530 = n443 | n152; - assign n531 = n436 | n152; - assign n532 = n141 & n229 & n305; - assign n533 = n137 & n201 & ~n395; - assign n534 = n446 | n339; - assign n535 = n230 & n532 & n534 & n228; - assign n536 = n516 & n181 & n178; - assign n537 = n239 | n369; - assign n538 = n537 & n451 & n454 & n401 & n371; - assign n539 = n407 & n455; - assign n540 = ~n366 | n409; - assign n541 = n409 | n370; - assign n542 = n540 & n408 & n539 & n456 & n541 & n457; - assign n543 = n452 & n538; - assign n544 = n369 | n403; - assign n545 = n154 | n409; - assign n546 = n544 & n545 & n199; - assign n547 = n513 & n512; - assign n548 = n154 | n152; - assign n549 = n325 & n547 & n353 & n548; - assign n550 = n147 & n378 & n370; - assign n551 = n152 | ~n382; - assign n552 = n409 | n462; - assign n553 = n239 | n409; - assign n554 = n543 & n546 & n461 & n542 & n552 & n553 & n179 & n362; - assign n555 = n373 | ~n382; - assign n556 = n446 | n373; - assign n557 = n356 | n373; - assign n558 = n378 | n373; - assign n559 = n373 | n370; - assign n560 = n511 & n169 & n406 & n557 & n558 & n559; - assign n561 = n136 & ~n383; - assign n562 = n515 & n514 & n412; - assign n563 = n502 & n168; - assign n564 = n507 & n353; - assign n565 = n339 | n370; - assign n566 = n356 | n339; - assign n567 = n138 & n566; - assign n568 = n531 & n527 & n528; - assign n569 = n153 & n333; - assign n570 = n144 & n299; - assign n571 = n149 & n419; - assign n572 = n362 & n552 & n461; - assign n573 = n326 & n571 & n524 & n168; - assign n574 = n452 & n537 & n401; - assign n575 = n517 & n199; - assign n576 = n544 & n574; - assign n577 = n153 & n333 & n144 & n147; - assign n578 = n558 & n424 & n372 & n557; - assign n579 = n509 & n510 & n555; - assign n580 = n350 & n490; - assign n581 = n169 & n579; - assign n582 = n473 & n536 & n569 & n150 & n458 & n271; - assign n583 = n270 | ~n381; - assign n584 = n155 | n403; - assign n585 = n466 & n416 & n480 & n479; - assign n586 = n429 & n281 & n263; - assign n587 = n534 & n494; - assign n588 = n457 & n261 & n470; - assign n589 = n580 & n587 & n568 & n574 & n536 & n177 & n388 & n400; - assign n590 = n142 & n530; - assign n591 = n451 & n408 & n374; - assign n592 = n145 & n339 & n474; - assign n593 = n510 & n525 & n464; - assign n594 = n239 | n270; - assign n595 = n545 & n260; - assign n596 = n151 & n402 & n427; - assign n597 = n418 & n475 & n522 & n534 & n348 & n399; -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/frisc/frisc.v b/fpga_flow/benchmarks/Verilog/MCNC/frisc/frisc.v deleted file mode 100644 index ea0d1ca1f..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/frisc/frisc.v +++ /dev/null @@ -1,4994 +0,0 @@ -// Benchmark "top" written by ABC on Mon Feb 4 17:32:32 2019 - -module frisc ( - tin_pdata_8_8_, tin_pdata_0_0_, tin_pdata_7_7_, preset_0_0_, - tin_pdata_2_2_, tin_pdata_9_9_, tin_pdata_1_1_, tin_pdata_4_4_, pclk, - pirq_0_0_, tin_pdata_10_10_, tin_pdata_3_3_, tin_pdata_6_6_, - tin_pdata_15_15_, tin_pdata_11_11_, tin_pdata_14_14_, tin_pdata_12_12_, - tin_pdata_5_5_, preset, tin_pdata_13_13_, - ppeakb_7_7_, ppeakp_12_12_, ppeakp_0_0_, ppeaka_7_7_, ppeaki_15_15_, - ppeaki_11_11_, ppeaki_3_3_, paddress_3_3_, pdata_8_8_, pdata_0_0_, - ppeakb_14_14_, ppeakb_10_10_, ppeakb_8_8_, ppeakp_1_1_, ppeaka_14_14_, - ppeaka_10_10_, ppeaka_8_8_, ppeaki_4_4_, paddress_15_15_, - paddress_11_11_, paddress_2_2_, ppeakb_9_9_, ppeakp_2_2_, ppeaka_9_9_, - ppeaks_12_12_, ppeaks_0_0_, ppeaki_5_5_, paddress_5_5_, pdata_7_7_, - ppeakb_15_15_, ppeakp_3_3_, pwr_0_0_, ppeaks_1_1_, ppeaki_6_6_, - paddress_4_4_, piack_0_0_, ppeakp_13_13_, ppeakp_4_4_, ppeaka_15_15_, - ppeaka_11_11_, ppeaks_2_2_, ppeaki_7_7_, paddress_10_10_, - paddress_7_7_, pdata_2_2_, ppeakp_5_5_, ppeaks_13_13_, ppeaks_3_3_, - ppeaki_14_14_, ppeaki_10_10_, ppeaki_8_8_, paddress_6_6_, ppeakp_6_6_, - ppeaks_4_4_, ppeaki_9_9_, paddress_9_9_, pdata_9_9_, pdata_1_1_, - ppeakb_11_11_, ppeakp_7_7_, ppeaks_5_5_, paddress_13_13_, - paddress_8_8_, ppeakp_14_14_, ppeakp_10_10_, ppeakp_8_8_, ppeaks_6_6_, - ppeaki_13_13_, pdata_4_4_, ppeakb_0_0_, ppeakp_9_9_, ppeaka_0_0_, - ppeaks_7_7_, ppeakb_1_1_, ppeaka_1_1_, ppeaks_10_10_, ppeaks_8_8_, - pdata_10_10_, pdata_3_3_, ppeakb_12_12_, ppeakb_2_2_, ppeaka_12_12_, - ppeaka_2_2_, ppeaks_15_15_, ppeaks_9_9_, ppeakb_3_3_, ppeakp_15_15_, - ppeakp_11_11_, ppeaka_13_13_, ppeaka_3_3_, paddress_14_14_, - paddress_12_12_, pdata_6_6_, ppeakb_13_13_, ppeakb_4_4_, pdn, - ppeaka_4_4_, ppeaki_0_0_, prd_0_0_, pdata_15_15_, pdata_11_11_, - ppeakb_5_5_, ppeaka_5_5_, ppeaks_14_14_, ppeaki_1_1_, paddress_1_1_, - pdata_14_14_, pdata_12_12_, pdata_5_5_, ppeakb_6_6_, ppeaka_6_6_, - ppeaks_11_11_, ppeaki_12_12_, ppeaki_2_2_, paddress_0_0_, pdata_13_13_ ); - input tin_pdata_8_8_, tin_pdata_0_0_, tin_pdata_7_7_, preset_0_0_, - tin_pdata_2_2_, tin_pdata_9_9_, tin_pdata_1_1_, tin_pdata_4_4_, pclk, - pirq_0_0_, tin_pdata_10_10_, tin_pdata_3_3_, tin_pdata_6_6_, - tin_pdata_15_15_, tin_pdata_11_11_, tin_pdata_14_14_, tin_pdata_12_12_, - tin_pdata_5_5_, preset, tin_pdata_13_13_; - output ppeakb_7_7_, ppeakp_12_12_, ppeakp_0_0_, ppeaka_7_7_, ppeaki_15_15_, - ppeaki_11_11_, ppeaki_3_3_, paddress_3_3_, pdata_8_8_, pdata_0_0_, - ppeakb_14_14_, ppeakb_10_10_, ppeakb_8_8_, ppeakp_1_1_, ppeaka_14_14_, - ppeaka_10_10_, ppeaka_8_8_, ppeaki_4_4_, paddress_15_15_, - paddress_11_11_, paddress_2_2_, ppeakb_9_9_, ppeakp_2_2_, ppeaka_9_9_, - ppeaks_12_12_, ppeaks_0_0_, ppeaki_5_5_, paddress_5_5_, pdata_7_7_, - ppeakb_15_15_, ppeakp_3_3_, pwr_0_0_, ppeaks_1_1_, ppeaki_6_6_, - paddress_4_4_, piack_0_0_, ppeakp_13_13_, ppeakp_4_4_, ppeaka_15_15_, - ppeaka_11_11_, ppeaks_2_2_, ppeaki_7_7_, paddress_10_10_, - paddress_7_7_, pdata_2_2_, ppeakp_5_5_, ppeaks_13_13_, ppeaks_3_3_, - ppeaki_14_14_, ppeaki_10_10_, ppeaki_8_8_, paddress_6_6_, ppeakp_6_6_, - ppeaks_4_4_, ppeaki_9_9_, paddress_9_9_, pdata_9_9_, pdata_1_1_, - ppeakb_11_11_, ppeakp_7_7_, ppeaks_5_5_, paddress_13_13_, - paddress_8_8_, ppeakp_14_14_, ppeakp_10_10_, ppeakp_8_8_, ppeaks_6_6_, - ppeaki_13_13_, pdata_4_4_, ppeakb_0_0_, ppeakp_9_9_, ppeaka_0_0_, - ppeaks_7_7_, ppeakb_1_1_, ppeaka_1_1_, ppeaks_10_10_, ppeaks_8_8_, - pdata_10_10_, pdata_3_3_, ppeakb_12_12_, ppeakb_2_2_, ppeaka_12_12_, - ppeaka_2_2_, ppeaks_15_15_, ppeaks_9_9_, ppeakb_3_3_, ppeakp_15_15_, - ppeakp_11_11_, ppeaka_13_13_, ppeaka_3_3_, paddress_14_14_, - paddress_12_12_, pdata_6_6_, ppeakb_13_13_, ppeakb_4_4_, pdn, - ppeaka_4_4_, ppeaki_0_0_, prd_0_0_, pdata_15_15_, pdata_11_11_, - ppeakb_5_5_, ppeaka_5_5_, ppeaks_14_14_, ppeaki_1_1_, paddress_1_1_, - pdata_14_14_, pdata_12_12_, pdata_5_5_, ppeakb_6_6_, ppeaka_6_6_, - ppeaks_11_11_, ppeaki_12_12_, ppeaki_2_2_, paddress_0_0_, pdata_13_13_; - reg ndout, ppeakb_12_12_, ppeakb_1_1_, ppeaka_6_6_, \[4295] , \[4310] , - ppeaks_5_5_, ppeakp_10_10_, \[4355] , \[4370] , \[4385] , \[4400] , - \[4415] , \[4430] , \[4445] , \[4460] , \[4475] , \[4490] , \[4505] , - \[4520] , \[4535] , \[4550] , \[4565] , \[4580] , \[4595] , \[4610] , - \[4625] , \[4640] , \[4655] , \[4670] , \[4700] , \[4715] , \[4730] , - \[4745] , \[4760] , \[4775] , \[4790] , \[4805] , \[4820] , \[4835] , - \[4850] , \[4865] , \[4880] , \[4895] , \[4910] , \[4925] , \[4940] , - \[4955] , \[4970] , ppeakb_0_0_, ppeaka_7_7_, \[5015] , \[5030] , - ppeaks_4_4_, ppeakp_11_11_, \[5075] , \[5090] , \[5105] , \[5120] , - \[5135] , \[5150] , \[5165] , \[5180] , \[5195] , \[5210] , \[5225] , - \[5240] , \[5255] , \[5270] , \[5285] , \[5300] , \[5315] , \[5330] , - \[5345] , \[5360] , \[5375] , \[5390] , \[5405] , \[5420] , \[5435] , - \[5450] , \[5465] , \[5480] , \[5495] , \[5510] , \[5525] , \[5540] , - \[5555] , \[5570] , \[5600] , \[5615] , \[5630] , \[5645] , \[5660] , - \[5675] , ppeakb_10_10_, ppeaka_8_8_, \[5720] , ppeaks_14_14_, - ppeaks_7_7_, ppeakp_12_12_, \[5780] , \[5795] , \[5810] , \[5825] , - \[5840] , \[5855] , \[5870] , \[5885] , \[5900] , \[5915] , \[5930] , - \[5945] , \[5960] , \[5975] , \[5990] , \[6005] , \[6020] , \[6035] , - \[6050] , \[6065] , \[6080] , \[6095] , \[6110] , \[6125] , \[6140] , - \[6155] , \[6170] , \[6185] , \[6200] , \[6215] , \[6230] , \[6245] , - \[6260] , \[6275] , \[6290] , \[6305] , \[6320] , \[6335] , \[6350] , - \[6365] , ppeakb_11_11_, ppeakb_2_2_, \[6410] , ppeaks_15_15_, - ppeaks_6_6_, ppeakp_13_13_, \[6470] , \[6485] , \[6500] , \[6515] , - \[6530] , \[6545] , \[6560] , \[6575] , \[6590] , \[6605] , \[6620] , - \[6635] , \[6650] , \[6665] , \[6680] , \[6695] , \[6710] , \[6725] , - \[6740] , \[6755] , \[6770] , \[6785] , \[6815] , \[6830] , \[6845] , - \[6860] , \[6875] , \[6890] , \[6905] , \[6920] , \[6935] , \[6950] , - \[6965] , \[6980] , \[6995] , \[7010] , \[7025] , \[7055] , - ppeaks_12_12_, ppeaks_1_1_, ppeakp_3_3_, \[7115] , \[7130] , \[7145] , - \[7160] , \[7175] , \[7190] , \[7205] , \[7220] , \[7235] , \[7250] , - \[7265] , \[7280] , \[7295] , \[7310] , \[7325] , \[7340] , \[7355] , - \[7370] , \[7385] , \[7400] , \[7415] , \[7430] , \[7445] , \[7460] , - \[7475] , \[7490] , \[7505] , \[7520] , \[7535] , \[7550] , \[7565] , - \[7580] , \[7595] , \[7625] , \[7640] , \[7655] , \[7670] , \[7685] , - ppeaks_13_13_, ppeakp_7_7_, ppeakp_2_2_, \[7745] , \[7760] , \[7775] , - \[7790] , \[7805] , \[7820] , \[7835] , \[7850] , \[7865] , \[7880] , - \[7895] , \[7910] , \[7925] , \[7940] , \[7955] , \[7970] , \[8000] , - \[8015] , \[8030] , \[8045] , \[8060] , \[8075] , \[8090] , \[8105] , - \[8120] , \[8135] , \[8150] , \[8165] , \[8180] , \[8195] , \[8210] , - \[8225] , \[8240] , \[8255] , \[8285] , \[8300] , \[8315] , \[8330] , - ppeaks_3_3_, ppeakp_8_8_, ppeakp_1_1_, \[8390] , \[8405] , \[8420] , - \[8435] , \[8450] , \[8465] , \[8480] , \[8495] , \[8510] , \[8525] , - \[8540] , \[8555] , \[8570] , \[8585] , \[8600] , \[8615] , \[8630] , - \[8645] , \[8660] , \[8675] , \[8690] , \[8705] , \[8720] , \[8735] , - \[8750] , \[8765] , \[8780] , \[8810] , \[8825] , \[8840] , \[8855] , - \[8870] , \[8885] , \[8900] , \[8915] , \[8930] , \[8945] , \[8960] , - \[8975] , ppeaks_11_11_, ppeaks_2_2_, ppeakp_9_9_, ppeakp_0_0_, - \[9050] , \[9065] , \[9080] , \[9095] , \[9110] , \[9125] , \[9140] , - \[9155] , \[9170] , \[9185] , \[9200] , \[9215] , \[9230] , \[9245] , - \[9260] , \[9275] , \[9290] , \[9305] , \[9320] , \[9335] , \[9350] , - \[9365] , \[9380] , \[9395] , \[9410] , \[9440] , \[9455] , \[9470] , - \[9485] , \[9500] , \[9515] , \[9530] , \[9545] , \[9560] , \[9575] , - \[9590] , \[9605] , \[9620] , \[9635] , \[9650] , \[9665] , \[9680] , - ppeaki_6_6_, \[9710] , \[9725] , \[9740] , \[9770] , \[9785] , - \[9800] , \[9815] , \[9830] , \[9845] , \[9860] , \[9875] , \[9890] , - \[9905] , \[9920] , \[9935] , \[9950] , \[9980] , \[9995] , \[10010] , - \[10025] , \[10040] , \[10055] , \[10070] , \[10085] , \[10100] , - \[10115] , \[10130] , \[10145] , \[10175] , \[10190] , \[10205] , - \[10220] , ppeaki_15_15_, ppeaki_4_4_, \[10265] , \[10280] , \[10310] , - \[10325] , \[10340] , \[10355] , \[10370] , \[10400] , \[10415] , - \[10430] , \[10445] , \[10460] , \[10475] , \[10490] , \[10505] , - ppeaki_14_14_, ppeaki_5_5_, \[10550] , \[10565] , \[10580] , \[10595] , - \[10610] , \[10625] , \[10655] , \[10670] , \[10685] , \[10700] , - \[10715] , \[10730] , \[10745] , \[10760] , \[10775] , \[10790] , - \[10805] , \[10820] , \[10850] , \[10865] , \[10880] , \[10895] , - \[10925] , \[10940] , \[10955] , \[10970] , \[10985] , \[11015] , - \[11030] , \[11045] , \[11060] , \[11075] , \[11090] , \[11120] , - \[11135] , \[11150] , \[11165] , \[11180] , \[11195] , \[11210] , - \[11225] , \[11240] , \[11255] , \[11270] , \[11285] , \[11300] , - \[11315] , \[11330] , \[11345] , \[11375] , \[11390] , \[11405] , - \[11420] , \[11435] , \[11450] , \[11465] , \[11480] , \[11495] , - \[11510] , \[11525] , \[11540] , \[11555] , \[11570] , \[11585] , - \[11600] , \[11615] , \[11630] , \[11645] , \[11660] , \[11675] , - \[11690] , \[11705] , \[11720] , \[11735] , \[11750] , \[11765] , - \[11780] , \[11795] , \[11810] , ppeaki_9_9_, ppeakb_14_14_, \[11885] , - \[11900] , \[11915] , \[11930] , ppeaki_8_8_, ppeakb_15_15_, \[12005] , - \[12020] , \[12035] , \[12050] , \[12065] , \[12080] , ppeaki_7_7_, - \[12125] , \[12140] , \[12155] , \[12170] , \[12185] , \[12200] , - ppeakb_13_13_, \[12245] , \[12260] , \[12275] , ppeaki_13_13_, - ppeaki_2_2_, \[12335] , \[12350] , \[12365] , \[12380] , \[12395] , - \[12410] , \[12425] , \[12440] , \[12455] , \[12470] , \[12485] , - ppeaki_12_12_, ppeaki_3_3_, \[12545] , \[12560] , \[12575] , \[12590] , - \[12605] , \[12620] , \[12635] , \[12650] , \[12665] , \[12680] , - \[12695] , ppeaki_11_11_, ppeaki_0_0_, \[12770] , \[12800] , \[12815] , - \[12830] , \[12845] , \[12860] , \[12875] , \[12890] , \[12905] , - \[12920] , \[12935] , ppeaki_10_10_, ppeaki_1_1_, \[13010] , \[13025] , - \[13040] , \[13055] , \[13070] , \[13085] , \[13100] , \[13115] , - \[13130] , \[13160] , \[13175] , ppeakb_4_4_, ppeaka_9_9_, \[13220] , - \[13235] , \[13250] , \[13265] , \[13280] , \[13295] , \[13310] , - \[13325] , \[13340] , \[13355] , \[13370] , \[13385] , \[13400] , - \[13415] , \[13430] , \[13445] , \[13460] , \[13475] , \[13490] , - \[13505] , ppeakb_5_5_, \[13550] , ppeakp_6_6_, \[13580] , \[13595] , - \[13610] , \[13625] , \[13640] , \[13655] , \[13670] , \[13685] , - \[13700] , \[13715] , \[13730] , \[13745] , \[13775] , \[13790] , - \[13805] , \[13820] , \[13835] , \[13850] , \[13865] , \[13880] , - \[13895] , ppeaka_11_11_, ppeaka_0_0_, ppeakp_5_5_, \[13955] , - \[13970] , \[13985] , \[14000] , \[14015] , \[14030] , \[14045] , - \[14060] , \[14075] , \[14090] , \[14105] , \[14120] , \[14135] , - \[14150] , \[14165] , \[14180] , \[14210] , \[14225] , \[14240] , - \[14255] , \[14270] , \[14285] , ppeakb_3_3_, ppeaka_10_10_, - ppeaka_1_1_, ppeakp_4_4_, \[14360] , \[14375] , \[14390] , \[14405] , - \[14420] , \[14435] , \[14450] , \[14465] , \[14480] , \[14495] , - \[14510] , \[14525] , \[14540] , \[14555] , \[14570] , \[14585] , - \[14600] , \[14615] , \[14630] , \[14660] , \[14675] , \[14690] , - \[14705] , ppeakb_8_8_, ppeaka_13_13_, ppeaka_2_2_, \[14765] , - ppeaks_9_9_, ppeakp_14_14_, \[14810] , \[14825] , \[14840] , \[14855] , - \[14870] , \[14885] , \[14900] , \[14915] , \[14930] , \[14960] , - \[14975] , \[14990] , \[15005] , \[15020] , \[15035] , \[15050] , - \[15065] , \[15080] , ppeakb_9_9_, ppeaka_12_12_, ppeaka_3_3_, - \[15140] , ppeaks_8_8_, ppeakp_15_15_, \[15185] , \[15200] , \[15215] , - \[15230] , \[15245] , \[15260] , \[15275] , \[15290] , \[15305] , - \[15320] , \[15335] , \[15350] , \[15365] , \[15380] , \[15395] , - \[15410] , \[15425] , \[15440] , ppeakb_6_6_, ppeaka_15_15_, - ppeaka_4_4_, \[15500] , \[15515] , ppeaks_0_0_, \[15545] , \[15560] , - \[15575] , \[15590] , \[15605] , \[15620] , \[15635] , \[15650] , - \[15665] , \[15680] , \[15695] , \[15710] , \[15725] , \[15755] , - \[15770] , \[15785] , ppeakb_7_7_, ppeaka_14_14_, ppeaka_5_5_, - \[15845] , \[15860] , ppeaks_10_10_, \[15890] , \[15905] , \[15920] , - \[15935] , \[15950] , \[15965] , \[15980] , \[15995] , \[16010] , - \[16025] , \[16040] , \[16055] , \[16070] , \[16085] , \[16100] , - paddress_8_8_, \[16907] , \[16920] , \[16933] , paddress_9_9_, - \[16959] , \[16972] , \[16985] , \[16998] , \[17011] , \[17024] , - \[17037] , \[17050] , \[17063] , \[17076] , \[17089] , \[17102] , - \[17115] , \[17128] , \[17141] , \[17154] , \[17167] , \[17180] , - \[17193] , \[17206] , \[17219] , \[17232] , \[17245] , \[17258] , - \[17271] , \[17284] , \[17297] , \[17310] , \[17323] , \[17336] , - \[17349] , \[17362] , \[17375] , \[17388] , paddress_11_11_, \[17414] , - \[17427] , \[17453] , paddress_10_10_, \[17479] , \[17492] , \[17505] , - \[17518] , \[17531] , \[17544] , paddress_13_13_, \[17570] , \[17583] , - \[17596] , \[17609] , paddress_12_12_, \[17635] , \[17648] , \[17661] , - \[17674] , paddress_15_15_, \[17700] , \[17713] , paddress_14_14_, - \[17739] , \[17752] , \[17765] , \[17778] , \[17791] , \[17804] , - \[17817] , pwr_0_0_, \[17843] , \[17856] , \[17869] , \[17882] , - prd_0_0_, \[17908] , \[17921] , \[17934] , \[17947] , \[17960] , - \[17973] , \[17986] , \[17999] , \[18012] , \[18025] , \[18038] , pdn, - \[18064] , \[18077] , \[18090] , \[18103] , \[18116] , \[18129] , - \[18142] , \[18155] , \[18168] , \[18181] , \[18194] , \[18207] , - \[18220] , \[18233] , \[18246] , paddress_0_0_, piack_0_0_, \[18285] , - \[18298] , \[18311] , paddress_1_1_, \[18337] , \[18350] , \[18363] , - \[18376] , \[18389] , paddress_2_2_, \[18415] , \[18428] , \[18441] , - paddress_3_3_, \[18467] , \[18480] , \[18493] , \[18506] , - paddress_4_4_, paddress_5_5_, \[18545] , paddress_6_6_, \[18571] , - \[18584] , \[18597] , \[18610] , paddress_7_7_, \[18636] ; - wire n3696_1, n3697, n3698, n3699, n3700, n3701_1, n3702, n3703, n3704, - n3705, n3706_1, n3707, n3708, n3709, n3710, n3711_1, n3712, n3713, - n3714, n3715, n3716_1, n3717, n3718, n3719, n3720, n3721_1, n3722, - n3723, n3724, n3725, n3726_1, n3727, n3728, n3729, n3730, n3731_1, - n3732, n3733, n3734, n3735, n3736_1, n3737, n3738, n3739, n3740, - n3741_1, n3742, n3743, n3744, n3745, n3746_1, n3747, n3748, n3749, - n3750_1, n3751, n3752, n3753, n3754_1, n3755, n3756, n3757, n3758_1, - n3759, n3760, n3761, n3762, n3763_1, n3764, n3765, n3766, n3767, - n3768_1, n3769, n3770, n3771, n3772_1, n3773, n3774, n3775, n3776, - n3777_1, n3778, n3779, n3780, n3781, n3782_1, n3783, n3784, n3785, - n3786, n3787_1, n3788, n3789, n3790, n3791, n3792_1, n3793, n3794, - n3795, n3796, n3797_1, n3798, n3799, n3800, n3801, n3802_1, n3803, - n3804, n3805, n3806, n3807_1, n3808, n3809, n3810, n3811, n3812_1, - n3813, n3814, n3815, n3816, n3817_1, n3818, n3819, n3820, n3821, - n3822_1, n3823, n3824, n3825, n3826, n3827_1, n3828, n3829, n3830, - n3831, n3832_1, n3833, n3834, n3835, n3836, n3837_1, n3838, n3839, - n3840, n3841, n3842_1, n3843, n3844, n3845, n3846, n3847_1, n3848, - n3849, n3850, n3851, n3852_1, n3853, n3854, n3855, n3856_1, n3857, - n3858, n3859, n3860_1, n3861, n3862, n3863, n3864_1, n3865, n3866, - n3867, n3868, n3869_1, n3870, n3871, n3872, n3873, n3874_1, n3875, - n3876, n3877, n3878_1, n3879, n3880, n3881, n3882, n3883_1, n3884, - n3885, n3886, n3887, n3888_1, n3889, n3890, n3891, n3892, n3893_1, - n3894, n3895, n3896, n3897, n3898_1, n3899, n3900, n3901, n3902, - n3903_1, n3904, n3905, n3906, n3907, n3908_1, n3909, n3910, n3911, - n3912, n3913_1, n3914, n3915, n3916, n3917, n3918_1, n3919, n3920, - n3921, n3922, n3923_1, n3924, n3925, n3926, n3927, n3928_1, n3929, - n3930, n3931, n3932, n3933_1, n3934, n3935, n3936, n3937, n3938_1, - n3939, n3940, n3941, n3942, n3943_1, n3944, n3945, n3946, n3947, - n3948_1, n3949, n3950, n3951, n3952, n3953_1, n3954, n3955, n3956, - n3957_1, n3958, n3959, n3960, n3961, n3962_1, n3963, n3964, n3965, - n3966, n3967_1, n3968, n3969, n3970, n3971, n3972_1, n3973, n3974, - n3975, n3976_1, n3977, n3978, n3979, n3980, n3981_1, n3982, n3983, - n3984, n3985, n3986_1, n3987, n3988, n3989, n3990, n3991_1, n3992, - n3993, n3994, n3995, n3996_1, n3997, n3998, n3999, n4000, n4001_1, - n4002, n4003, n4004, n4005, n4006_1, n4007, n4008, n4009, n4010, - n4011_1, n4012, n4013, n4014, n4015, n4016_1, n4017, n4018, n4019, - n4020, n4021_1, n4022, n4023, n4024, n4025, n4026_1, n4027, n4028, - n4029, n4030, n4031_1, n4032, n4033, n4034, n4035, n4036_1, n4037, - n4038, n4039, n4040, n4041_1, n4042, n4043, n4044, n4045, n4046_1, - n4047, n4048, n4049, n4050, n4051_1, n4052, n4053, n4054, n4055, - n4056_1, n4057, n4058, n4059, n4060, n4061_1, n4062, n4063, n4064, - n4065, n4066_1, n4067, n4068, n4069, n4070, n4071_1, n4072, n4073, - n4074, n4075, n4076_1, n4077, n4078, n4079, n4080, n4081_1, n4082, - n4083, n4084, n4085, n4086_1, n4087, n4088, n4089, n4090, n4091_1, - n4092, n4093, n4094, n4095, n4096_1, n4097, n4098, n4099, n4100, - n4101_1, n4102, n4103, n4104, n4105, n4106_1, n4107, n4108, n4109, - n4110, n4111_1, n4112, n4113, n4114, n4115, n4116_1, n4117, n4118, - n4119, n4120, n4121_1, n4122, n4123, n4124, n4125, n4126_1, n4127, - n4128, n4129, n4130, n4131_1, n4132, n4133, n4134, n4135, n4136_1, - n4137, n4138, n4139, n4140, n4141_1, n4142, n4143, n4144, n4145, - n4146_1, n4147, n4148, n4149, n4150_1, n4151, n4152, n4153, n4154, - n4155_1, n4156, n4157, n4158, n4159, n4160_1, n4161, n4162, n4163, - n4164, n4165_1, n4166, n4167, n4168, n4169_1, n4170, n4171, n4172, - n4173, n4174_1, n4175, n4176, n4177, n4178, n4179_1, n4180, n4181, - n4182, n4183, n4184_1, n4185, n4186, n4187, n4188, n4189_1, n4190, - n4191, n4192, n4193, n4194_1, n4195, n4196, n4197, n4198, n4199_1, - n4200, n4201, n4202, n4203_1, n4204, n4205, n4206, n4207, n4208_1, - n4209, n4210, n4211, n4212, n4213_1, n4214, n4215, n4216, n4217, - n4218_1, n4219, n4220, n4221, n4222, n4223_1, n4224, n4225, n4226, - n4227_1, n4228, n4229, n4230, n4231, n4232_1, n4233, n4234, n4235, - n4236, n4237_1, n4238, n4239, n4240, n4241, n4242_1, n4243, n4244, - n4245, n4246, n4247_1, n4248, n4249, n4250, n4251_1, n4252, n4253, - n4254, n4255, n4256_1, n4257, n4258, n4259, n4260, n4261_1, n4262, - n4263, n4264, n4265_1, n4266, n4267, n4268, n4269, n4270_1, n4271, - n4272, n4273, n4274, n4275_1, n4276, n4277, n4278, n4279, n4280_1, - n4281, n4282, n4283, n4284, n4285_1, n4286, n4287, n4288, n4289, - n4290_1, n4291, n4292, n4293, n4294, n4295_1, n4296, n4297, n4298, - n4299, n4300_1, n4301, n4302, n4303, n4304_1, n4305, n4306, n4307, - n4308, n4309_1, n4310, n4311, n4312, n4313, n4314_1, n4315, n4316, - n4317, n4318, n4319_1, n4320, n4321, n4322, n4323, n4324_1, n4325, - n4326, n4327, n4328_1, n4329, n4330, n4331, n4332, n4333_1, n4334, - n4335, n4336, n4337, n4338_1, n4339, n4340, n4341, n4342, n4343_1, - n4344, n4345, n4346, n4347, n4348_1, n4349, n4350, n4351, n4352, - n4353_1, n4354, n4355, n4356, n4357, n4358_1, n4359, n4360, n4361, - n4362, n4363_1, n4364, n4365, n4366, n4367, n4368_1, n4369, n4370, - n4371, n4372, n4373_1, n4374, n4375, n4376, n4377, n4378_1, n4379, - n4380, n4381, n4382, n4383_1, n4384, n4385, n4386, n4387_1, n4388, - n4389, n4390, n4391, n4392_1, n4393, n4394, n4395, n4396, n4397_1, - n4398, n4399, n4400, n4401, n4402_1, n4403, n4404, n4405, n4406, - n4407_1, n4408, n4409, n4410, n4411, n4412_1, n4413, n4414, n4415, - n4416, n4417_1, n4418, n4419, n4420, n4421, n4422_1, n4423, n4424, - n4425, n4426, n4427_1, n4428, n4429, n4430, n4431, n4432_1, n4433, - n4434, n4435, n4436, n4437_1, n4438, n4439, n4440, n4441, n4442_1, - n4443, n4444, n4445, n4446, n4447_1, n4448, n4449, n4450, n4451, - n4452_1, n4453, n4454, n4455, n4456, n4457_1, n4458, n4459, n4460, - n4461, n4462_1, n4463, n4464, n4465, n4466_1, n4467, n4468, n4469, - n4470_1, n4471, n4472, n4473, n4474, n4475_1, n4476, n4477, n4478, - n4479, n4480_1, n4481, n4482, n4483, n4484, n4485_1, n4486, n4487, - n4488, n4489_1, n4490, n4491, n4492, n4493, n4494_1, n4495, n4496, - n4497, n4498, n4499_1, n4500, n4501, n4502, n4503, n4504_1, n4505, - n4506, n4507, n4508, n4509_1, n4510, n4511, n4512, n4513, n4514_1, - n4515, n4516, n4517, n4518_1, n4519, n4520, n4521, n4522, n4523_1, - n4524, n4525, n4526, n4527, n4528_1, n4529, n4530, n4531, n4532, - n4533_1, n4534, n4535, n4536, n4537_1, n4538, n4539, n4540, n4541, - n4542_1, n4543, n4544, n4545, n4546, n4547_1, n4548, n4549, n4550, - n4551, n4552_1, n4553, n4554, n4555, n4556, n4557_1, n4558, n4559, - n4560, n4561_1, n4562, n4563, n4564, n4565_1, n4566, n4567, n4568, - n4569, n4570_1, n4571, n4572, n4573, n4574_1, n4575, n4576, n4577, - n4578, n4579_1, n4580, n4581, n4582, n4583, n4584_1, n4585, n4586, - n4587, n4588, n4589_1, n4590, n4591, n4592, n4593, n4594_1, n4595, - n4596, n4597, n4598_1, n4599, n4600, n4601, n4602, n4603, n4604, n4605, - n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615, - n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625, - n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635, - n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645, - n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655, - n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665, - n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675, - n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685, - n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695, - n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705, - n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715, - n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725, - n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735, - n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745, - n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755, - n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765, - n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775, - n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785, - n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795, - n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805, - n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815, - n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825, - n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835, - n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845, - n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855, - n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865, - n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875, - n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885, - n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895, - n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905, - n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915, - n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925, - n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935, - n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945, - n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955, - n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965, - n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975, - n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985, - n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995, - n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005, - n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015, - n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025, - n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035, - n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045, - n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055, - n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065, - n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075, - n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085, - n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095, - n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105, - n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115, - n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125, - n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135, - n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145, - n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155, - n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165, - n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175, - n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185, - n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195, - n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205, - n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215, - n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225, - n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235, - n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245, - n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255, - n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265, - n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275, - n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285, - n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295, - n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305, - n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315, - n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325, - n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335, - n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345, - n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355, - n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365, - n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375, - n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385, - n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395, - n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405, - n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415, - n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425, - n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435, - n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445, - n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455, - n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465, - n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475, - n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485, - n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495, - n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505, - n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515, - n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525, - n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535, - n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545, - n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555, - n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565, - n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575, - n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585, - n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595, - n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605, - n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615, - n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625, - n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635, - n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645, - n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655, - n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665, - n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675, - n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685, - n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695, - n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705, - n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714, n5715, - n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725, - n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735, - n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744, n5745, - n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755, - n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765, - n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775, - n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785, - n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795, - n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805, - n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815, - n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825, - n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835, - n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845, - n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855, - n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865, - n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875, - n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885, - n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895, - n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905, - n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915, - n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925, - n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935, - n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945, - n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955, - n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965, - n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975, - n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985, - n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995, - n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005, - n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014, n6015, - n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025, - n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035, - n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045, - n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055, - n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065, - n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075, - n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085, - n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095, - n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105, - n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115, - n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125, - n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135, - n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145, - n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155, - n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165, - n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175, - n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185, - n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195, - n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205, - n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215, - n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225, - n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235, - n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245, - n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255, - n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265, - n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275, - n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285, - n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295, - n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305, - n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315, - n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325, - n6326, n6327, n6328, n6329, n6330, n6331, n6332, n273, n278, n282, - n286, n290, n295, n300, n304, n308, n313, n318, n323, n328, n333, n338, - n343, n348, n353, n358, n363, n368, n373, n378, n383, n388, n393, n398, - n403, n408, n413, n418, n423, n428, n433, n438, n443, n448, n453, n458, - n463, n468, n473, n478, n483, n488, n493, n498, n503, n508, n513, n517, - n521, n526, n531, n535, n539, n544, n549, n554, n559, n564, n569, n574, - n579, n584, n589, n594, n599, n604, n609, n614, n619, n624, n629, n634, - n639, n644, n649, n654, n659, n664, n669, n674, n679, n684, n689, n694, - n699, n704, n709, n714, n719, n724, n729, n734, n739, n743, n747, n752, - n756, n760, n764, n769, n774, n779, n784, n789, n794, n799, n804, n809, - n814, n819, n824, n829, n834, n839, n844, n849, n854, n859, n864, n869, - n874, n879, n884, n889, n894, n899, n904, n909, n914, n919, n924, n929, - n934, n939, n944, n949, n954, n959, n964, n968, n972, n977, n981, n985, - n989, n994, n999, n1004, n1009, n1014, n1019, n1024, n1029, n1034, - n1039, n1044, n1049, n1054, n1059, n1064, n1069, n1074, n1079, n1084, - n1089, n1094, n1099, n1104, n1109, n1114, n1119, n1124, n1129, n1134, - n1139, n1144, n1149, n1154, n1159, n1164, n1169, n1174, n1179, n1183, - n1187, n1191, n1196, n1201, n1206, n1211, n1216, n1221, n1226, n1231, - n1236, n1241, n1246, n1251, n1256, n1261, n1266, n1271, n1276, n1281, - n1286, n1291, n1296, n1301, n1306, n1311, n1316, n1321, n1326, n1331, - n1336, n1341, n1346, n1351, n1356, n1361, n1366, n1371, n1376, n1381, - n1385, n1389, n1393, n1398, n1403, n1408, n1413, n1418, n1423, n1428, - n1433, n1438, n1443, n1448, n1453, n1458, n1463, n1468, n1473, n1478, - n1483, n1488, n1493, n1498, n1503, n1508, n1513, n1518, n1523, n1528, - n1533, n1538, n1543, n1548, n1553, n1558, n1563, n1568, n1573, n1578, - n1583, n1587, n1591, n1595, n1600, n1605, n1610, n1615, n1620, n1625, - n1630, n1635, n1640, n1645, n1650, n1655, n1660, n1665, n1670, n1675, - n1680, n1685, n1690, n1695, n1700, n1705, n1710, n1715, n1720, n1725, - n1730, n1735, n1740, n1745, n1750, n1755, n1760, n1765, n1770, n1775, - n1780, n1785, n1790, n1794, n1798, n1802, n1806, n1811, n1816, n1821, - n1826, n1831, n1836, n1841, n1846, n1851, n1856, n1861, n1866, n1871, - n1876, n1881, n1886, n1891, n1896, n1901, n1906, n1911, n1916, n1921, - n1926, n1931, n1936, n1941, n1946, n1951, n1956, n1961, n1966, n1971, - n1976, n1981, n1986, n1991, n1996, n2001, n2006, n2011, n2016, n2020, - n2025, n2030, n2035, n2040, n2045, n2050, n2055, n2060, n2065, n2070, - n2075, n2080, n2085, n2090, n2095, n2100, n2105, n2110, n2115, n2120, - n2125, n2130, n2135, n2140, n2145, n2150, n2155, n2160, n2165, n2170, - n2175, n2180, n2184, n2188, n2193, n2198, n2203, n2208, n2213, n2218, - n2223, n2228, n2233, n2238, n2243, n2248, n2253, n2258, n2263, n2267, - n2271, n2276, n2281, n2286, n2291, n2296, n2301, n2306, n2311, n2316, - n2321, n2326, n2331, n2336, n2341, n2346, n2351, n2356, n2361, n2366, - n2371, n2376, n2381, n2386, n2391, n2396, n2401, n2406, n2411, n2416, - n2421, n2426, n2431, n2436, n2441, n2446, n2451, n2456, n2461, n2466, - n2471, n2476, n2481, n2486, n2491, n2496, n2501, n2506, n2511, n2516, - n2521, n2526, n2531, n2536, n2541, n2546, n2551, n2556, n2561, n2566, - n2571, n2576, n2581, n2586, n2591, n2596, n2601, n2606, n2611, n2616, - n2621, n2626, n2631, n2636, n2641, n2646, n2651, n2656, n2661, n2666, - n2670, n2674, n2679, n2684, n2689, n2694, n2698, n2702, n2707, n2712, - n2717, n2722, n2727, n2732, n2736, n2741, n2746, n2751, n2756, n2761, - n2766, n2770, n2775, n2780, n2785, n2789, n2793, n2798, n2803, n2808, - n2813, n2818, n2823, n2828, n2833, n2838, n2843, n2848, n2852, n2856, - n2861, n2866, n2871, n2876, n2881, n2886, n2891, n2896, n2901, n2906, - n2911, n2915, n2919, n2924, n2929, n2934, n2939, n2944, n2949, n2954, - n2959, n2964, n2969, n2974, n2978, n2982, n2987, n2992, n2997, n3002, - n3007, n3012, n3017, n3022, n3027, n3032, n3037, n3041, n3045, n3050, - n3055, n3060, n3065, n3070, n3075, n3080, n3085, n3090, n3095, n3100, - n3105, n3110, n3115, n3120, n3125, n3130, n3135, n3140, n3145, n3149, - n3154, n3158, n3163, n3168, n3173, n3178, n3183, n3188, n3193, n3198, - n3203, n3208, n3213, n3218, n3223, n3228, n3233, n3238, n3243, n3248, - n3253, n3258, n3263, n3267, n3271, n3275, n3280, n3285, n3290, n3295, - n3300, n3305, n3310, n3315, n3320, n3325, n3330, n3335, n3340, n3345, - n3350, n3355, n3360, n3365, n3370, n3375, n3380, n3385, n3389, n3393, - n3397, n3401, n3406, n3411, n3416, n3421, n3426, n3431, n3436, n3441, - n3446, n3451, n3456, n3461, n3466, n3471, n3476, n3481, n3486, n3491, - n3496, n3501, n3506, n3511, n3516, n3520, n3524, n3528, n3533, n3537, - n3541, n3546, n3551, n3556, n3561, n3566, n3571, n3576, n3581, n3586, - n3591, n3596, n3601, n3606, n3611, n3616, n3621, n3626, n3631, n3635, - n3639, n3643, n3648, n3652, n3656, n3661, n3666, n3671, n3676, n3681, - n3686, n3691, n3696, n3701, n3706, n3711, n3716, n3721, n3726, n3731, - n3736, n3741, n3746, n3750, n3754, n3758, n3763, n3768, n3772, n3777, - n3782, n3787, n3792, n3797, n3802, n3807, n3812, n3817, n3822, n3827, - n3832, n3837, n3842, n3847, n3852, n3856, n3860, n3864, n3869, n3874, - n3878, n3883, n3888, n3893, n3898, n3903, n3908, n3913, n3918, n3923, - n3928, n3933, n3938, n3943, n3948, n3953, n3957, n3962, n3967, n3972, - n3976, n3981, n3986, n3991, n3996, n4001, n4006, n4011, n4016, n4021, - n4026, n4031, n4036, n4041, n4046, n4051, n4056, n4061, n4066, n4071, - n4076, n4081, n4086, n4091, n4096, n4101, n4106, n4111, n4116, n4121, - n4126, n4131, n4136, n4141, n4146, n4150, n4155, n4160, n4165, n4169, - n4174, n4179, n4184, n4189, n4194, n4199, n4203, n4208, n4213, n4218, - n4223, n4227, n4232, n4237, n4242, n4247, n4251, n4256, n4261, n4265, - n4270, n4275, n4280, n4285, n4290, n4295, n4300, n4304, n4309, n4314, - n4319, n4324, n4328, n4333, n4338, n4343, n4348, n4353, n4358, n4363, - n4368, n4373, n4378, n4383, n4387, n4392, n4397, n4402, n4407, n4412, - n4417, n4422, n4427, n4432, n4437, n4442, n4447, n4452, n4457, n4462, - n4466, n4470, n4475, n4480, n4485, n4489, n4494, n4499, n4504, n4509, - n4514, n4518, n4523, n4528, n4533, n4537, n4542, n4547, n4552, n4557, - n4561, n4565, n4570, n4574, n4579, n4584, n4589, n4594, n4598; - assign pdata_8_8_ = \[17882] ? \[16959] : tin_pdata_8_8_; - assign pdata_0_0_ = \[17479] ? \[18337] : tin_pdata_0_0_; - assign pdata_7_7_ = \[17869] ? \[16907] : tin_pdata_7_7_; - assign pdata_2_2_ = \[18181] ? \[17323] : tin_pdata_2_2_; - assign pdata_9_9_ = \[18571] ? \[17765] : tin_pdata_9_9_; - assign pdata_1_1_ = \[18116] ? \[17258] : tin_pdata_1_1_; - assign pdata_4_4_ = \[18038] ? \[17193] : tin_pdata_4_4_; - assign pdata_10_10_ = \[17011] ? \[17921] : tin_pdata_10_10_; - assign pdata_3_3_ = \[17960] ? \[17128] : tin_pdata_3_3_; - assign pdata_6_6_ = \[17934] ? \[17063] : tin_pdata_6_6_; - assign pdata_15_15_ = \[17947] ? \[17076] : tin_pdata_15_15_; - assign pdata_11_11_ = \[17336] ? \[18194] : tin_pdata_11_11_; - assign pdata_14_14_ = \[18584] ? \[17778] : tin_pdata_14_14_; - assign pdata_12_12_ = \[17141] ? \[17973] : tin_pdata_12_12_; - assign pdata_5_5_ = \[17908] ? \[16998] : tin_pdata_5_5_; - assign pdata_13_13_ = \[18350] ? \[17492] : tin_pdata_13_13_; - assign n273 = n5632 | (pdata_2_2_ & n3696_1); - assign n278 = n5690 | n5687 | n5688; - assign n282 = n5694 | n5691 | n5692; - assign n286 = n5700 | n5698 | n5699; - assign n290 = n5703 | n5596 | n5597; - assign n295 = n5704 | n5593 | n5594; - assign n300 = n5715 | n5713 | n5714; - assign n304 = n5573 | n5575 | n5576 | n5727; - assign n308 = n5572 | (pdata_0_0_ & n3703); - assign n313 = n5571 | (pdata_11_11_ & n3703); - assign n318 = ~preset & (n3792_1 ? pdata_6_6_ : \[4385] ); - assign n323 = n5570 | (pdata_1_1_ & n3705); - assign n328 = n5569 | (pdata_12_12_ & n3705); - assign n333 = ~preset & (n3817_1 ? pdata_7_7_ : \[4430] ); - assign n338 = ~preset & (n3817_1 ? pdata_2_2_ : \[4445] ); - assign n343 = ~preset & (n3817_1 ? pdata_13_13_ : \[4460] ); - assign n348 = n5568 | (pdata_8_8_ & n3708); - assign n353 = n5567 | (pdata_3_3_ & n4504); - assign n358 = n5566 | (pdata_14_14_ & n4504); - assign n363 = n5564 | n5565; - assign n368 = n5562 | n5563; - assign n373 = n5560 | n5561; - assign n378 = ~preset & (n3813 ? pdata_5_5_ : \[4565] ); - assign n383 = ~preset & (n3813 ? pdata_0_0_ : \[4580] ); - assign n388 = ~preset & (n3813 ? pdata_11_11_ : \[4595] ); - assign n393 = n5559 | (pdata_6_6_ & n3711_1); - assign n398 = (n4160 & n3712) | (\[4625] & n3713); - assign n403 = (n4160 & n3714) | (\[4640] & n3713); - assign n408 = n5481 | n5482; - assign n413 = n5480 | (\[4670] & n3707); - assign n418 = n5478 | n5479; - assign n423 = n5477 | (\[4715] & n3717); - assign n428 = (\[4730] & n3717) | (n3718 & n3719); - assign n433 = n5461 | (n4547 & n3720); - assign n438 = n5460 | (\[4760] & n3710); - assign n443 = n5459 | (\[4775] & n3710); - assign n448 = n5457 | n5458; - assign n453 = (n3712 & n3723) | (\[4805] & n3722); - assign n458 = (n3714 & n3723) | (\[4820] & n3722); - assign n463 = ~preset & (n3825 ? n3724 : \[4835] ); - assign n468 = n5378 | (n3726_1 & n3727); - assign n473 = (n3728 & n3730) | (\[4865] & n3729); - assign n478 = n5342 | (n3730 & (~n3930 ^ n3931)); - assign n483 = n5341 | (n3731_1 & n3732); - assign n488 = (n3733 & n3735) | (\[4910] & n3734); - assign n493 = (\[4925] & n3722) | (n3723 & n3736_1); - assign n498 = (\[4940] & n3722) | (n3723 & n3737); - assign n503 = (n3724 & n3739) | (\[4955] & n3738); - assign n508 = n5340 | (pdata_1_1_ & n3696_1); - assign n513 = n5862 | n5859 | n5860; - assign n517 = n5868 | n5866 | n5867; - assign n521 = n5869 | n5319 | n5320; - assign n526 = n5870 | n5316 | n5317; - assign n531 = n5876 | n5874 | n5875; - assign n535 = n5298 | n5300 | n5301 | n5878; - assign n539 = n5297 | (pdata_1_1_ & n3703); - assign n544 = n5296 | (pdata_10_10_ & n3703); - assign n549 = n5295 | (pdata_2_2_ & n3705); - assign n554 = n5294 | (pdata_11_11_ & n3705); - assign n559 = ~preset & (n3817_1 ? pdata_8_8_ : \[5135] ); - assign n564 = ~preset & (n3817_1 ? pdata_1_1_ : \[5150] ); - assign n569 = ~preset & (n3817_1 ? pdata_14_14_ : \[5165] ); - assign n574 = n5293 | (pdata_7_7_ & n3708); - assign n579 = n5292 | (pdata_4_4_ & n4504); - assign n584 = n5291 | (pdata_13_13_ & n4504); - assign n589 = n5289 | n5290; - assign n594 = n5287 | n5288; - assign n599 = n5285 | n5286; - assign n604 = ~preset & (n3813 ? pdata_4_4_ : \[5270] ); - assign n609 = ~preset & (n3813 ? pdata_1_1_ : \[5285] ); - assign n614 = ~preset & (n3813 ? pdata_10_10_ : \[5300] ); - assign n619 = n5284 | (pdata_7_7_ & n3711_1); - assign n624 = n5283 | (n4160 & (n3893_1 ^ n3894)); - assign n629 = n5282 | (\[5345] & n3713); - assign n634 = n5281 | (n3714 & n3715); - assign n639 = n5280 | (\[5375] & n3707); - assign n644 = n5279 | (n3716_1 & (n3893_1 ^ n3894)); - assign n649 = n5278 | (n3716_1 & n3720); - assign n654 = n5277 | (\[5420] & n3717); - assign n659 = (\[5435] & n3717) | (n3718 & n3740); - assign n664 = n5275 | n5276; - assign n669 = n5274 | (n4106 & n3720); - assign n674 = (n3709 & n3740) | (\[5480] & n3710); - assign n679 = n5273 | (n3721_1 & n3741_1); - assign n684 = n5272 | (\[5510] & n3722); - assign n689 = n5271 | (\[5525] & n3722); - assign n694 = ~preset & (n3825 ? n3742 : \[5540] ); - assign n699 = n5270 | (n3727 & n3743); - assign n704 = (\[5570] & n3729) | (n3730 & n3733); - assign n709 = n5269 | (n3732 & n3744); - assign n714 = (n3728 & n3735) | (\[5615] & n3734); - assign n719 = n5268 | (n4081 & n3744); - assign n724 = (\[5645] & n3722) | (n3723 & n3745); - assign n729 = (\[5660] & n3738) | (n3739 & n3746_1); - assign n734 = n5267 | (pdata_0_0_ & n3696_1); - assign n739 = n5882 | n5879 | n5880; - assign n743 = n5888 | n5886 | n5887; - assign n747 = n5889 | n5246 | n5247; - assign n752 = n5895 | n5893 | n5894; - assign n756 = n5901 | n5899 | n5900; - assign n760 = n5214 | n5216 | n5217 | n5903; - assign n764 = n5213 | (pdata_2_2_ & n3703); - assign n769 = ~preset & (n3792_1 ? pdata_4_4_ : \[5795] ); - assign n774 = ~preset & (n3792_1 ? pdata_8_8_ : \[5810] ); - assign n779 = ~preset & (n3817_1 ? pdata_9_9_ : \[5825] ); - assign n784 = ~preset & (n3817_1 ? pdata_4_4_ : \[5840] ); - assign n789 = ~preset & (n3817_1 ? pdata_11_11_ : \[5855] ); - assign n794 = n5212 | (pdata_6_6_ & n3708); - assign n799 = n5211 | (pdata_5_5_ & n4504); - assign n804 = n5209 | n5210; - assign n809 = n5207 | n5208; - assign n814 = n5205 | n5206; - assign n819 = n5203 | n5204; - assign n824 = ~preset & (n3813 ? pdata_7_7_ : \[5960] ); - assign n829 = ~preset & (n3813 ? pdata_14_14_ : \[5975] ); - assign n834 = ~preset & (n3813 ? pdata_9_9_ : \[5990] ); - assign n839 = n5202 | (pdata_8_8_ & n3711_1); - assign n844 = (n4160 & n3747) | (\[6020] & n3713); - assign n849 = n5201 | (\[6035] & n3713); - assign n854 = n5199 | n5200; - assign n859 = n5198 | (\[6065] & n3707); - assign n864 = (n3706_1 & n3740) | (\[6080] & n3707); - assign n869 = n5196 | n5197; - assign n874 = (\[6110] & n3717) | (n3718 & n3741_1); - assign n879 = n5195 | (n4547 & (n3893_1 ^ n3894)); - assign n884 = n5193 | n5194; - assign n889 = n5191 | n5192; - assign n894 = n5190 | (\[6170] & n3710); - assign n899 = n5188 | n5189; - assign n904 = (\[6200] & n3722) | (n3723 & n3747); - assign n909 = (\[6215] & n3722) | (n3723 & n3740); - assign n914 = ~preset & (n3825 ? n3728 : \[6230] ); - assign n919 = n5187 | (n3742 & n3748); - assign n924 = n5186 | (n3727 & n3736_1); - assign n929 = n5185 | (n3732 & n3749); - assign n934 = n5184 | (n3732 & n3743); - assign n939 = (\[6305] & n3734) | (n3735 & n3736_1); - assign n944 = n5183 | (n3750_1 & (~n3930 ^ n3931)); - assign n949 = (\[6335] & n3722) | (n3723 & n3752); - assign n954 = (\[6350] & n3738) | (n3739 & n3744); - assign n959 = n5182 | (n3739 & (~n3930 ^ n3931)); - assign n964 = n5907 | n5904 | n5905; - assign n968 = n5911 | n5908 | n5909; - assign n972 = n5912 | n5159 | n5160; - assign n977 = n5918 | n5916 | n5917; - assign n981 = n5924 | n5922 | n5923; - assign n985 = n5127 | n5129 | n5130 | n5926; - assign n989 = n5126 | (pdata_12_12_ & n3703); - assign n994 = ~preset & (n3792_1 ? pdata_5_5_ : \[6485] ); - assign n999 = ~preset & (n3792_1 ? pdata_7_7_ : \[6500] ); - assign n1004 = ~preset & (n3817_1 ? pdata_10_10_ : \[6515] ); - assign n1009 = ~preset & (n3817_1 ? pdata_3_3_ : \[6530] ); - assign n1014 = ~preset & (n3817_1 ? pdata_12_12_ : \[6545] ); - assign n1019 = n5125 | (pdata_5_5_ & n3708); - assign n1024 = n5124 | (pdata_6_6_ & n4504); - assign n1029 = n5123 | (pdata_15_15_ & n4504); - assign n1034 = n5121 | n5122; - assign n1039 = n5119 | n5120; - assign n1044 = ~preset & (n3813 ? pdata_6_6_ : \[6635] ); - assign n1049 = ~preset & (n3813 ? pdata_15_15_ : \[6650] ); - assign n1054 = ~preset & (n3813 ? pdata_8_8_ : \[6665] ); - assign n1059 = n5118 | (pdata_9_9_ & n3711_1); - assign n1064 = n5117 | (\[6695] & n3713); - assign n1069 = n5116 | (\[6710] & n3713); - assign n1074 = n5115 | (n3715 & n3740); - assign n1079 = (n3706_1 & n3741_1) | (\[6740] & n3707); - assign n1084 = (n3706_1 & n3719) | (\[6755] & n3707); - assign n1089 = n5113 | n5114; - assign n1094 = n5112 | (\[6785] & n3717); - assign n1099 = n5110 | n5111; - assign n1104 = n5108 | n5109; - assign n1109 = (n3709 & n3747) | (\[6845] & n3710); - assign n1114 = (n3709 & n3714) | (\[6860] & n3710); - assign n1119 = n5107 | (\[6875] & n3722); - assign n1124 = n5106 | (\[6890] & n3722); - assign n1129 = ~preset & (n3825 ? n3746_1 : \[6905] ); - assign n1134 = n5105 | (n3744 & n3748); - assign n1139 = n5104 | (n3727 & n3749); - assign n1144 = n5103 | (n3732 & n3736_1); - assign n1149 = n5102 | (n3726_1 & n3732); - assign n1154 = (\[6980] & n3734) | (n3735 & n3753); - assign n1159 = (n3746_1 & n3750_1) | (\[6995] & n3751); - assign n1164 = n5101 | (n3723 & (~n3930 ^ n3931)); - assign n1169 = (\[7025] & n3738) | (n3739 & n3742); - assign n1174 = n5927 | n5098 | n5099; - assign n1179 = n5933 | n5931 | n5932; - assign n1183 = n5939 | n5937 | n5938; - assign n1187 = n5066 | n5068 | n5069 | n5941; - assign n1191 = n5065 | (pdata_7_7_ & n3703); - assign n1196 = ~preset & (n3792_1 ? pdata_2_2_ : \[7130] ); - assign n1201 = ~preset & (n3817_1 ? pdata_11_11_ : \[7145] ); - assign n1206 = ~preset & (n3817_1 ? pdata_6_6_ : \[7160] ); - assign n1211 = n5064 | (pdata_1_1_ & n3708); - assign n1216 = n5063 | (pdata_12_12_ & n3708); - assign n1221 = n5062 | (pdata_15_15_ & n3708); - assign n1226 = n5061 | (pdata_10_10_ & n4504); - assign n1231 = n5059 | n5060; - assign n1236 = n5057 | n5058; - assign n1241 = ~preset & (n3813 ? pdata_9_9_ : \[7265] ); - assign n1246 = ~preset & (n3813 ? pdata_4_4_ : \[7280] ); - assign n1251 = ~preset & (n3813 ? pdata_15_15_ : \[7295] ); - assign n1256 = n5056 | (pdata_2_2_ & n3711_1); - assign n1261 = n5055 | (pdata_13_13_ & n3711_1); - assign n1266 = n5054 | (\[7340] & n3713); - assign n1271 = n5053 | (n3715 & n3719); - assign n1276 = (n3706_1 & n3720) | (\[7370] & n3707); - assign n1281 = n5052 | (n3716_1 & n3747); - assign n1286 = n5051 | (n3716_1 & n3740); - assign n1291 = n5050 | (n3718 & (n3893_1 ^ n3894)); - assign n1296 = n5049 | (\[7430] & n3717); - assign n1301 = n5047 | n5048; - assign n1306 = n5046 | (n4106 & n3714); - assign n1311 = (n3709 & n3741_1) | (\[7475] & n3710); - assign n1316 = n5045 | (n3721_1 & (n3893_1 ^ n3894)); - assign n1321 = n5043 | n5044; - assign n1326 = n5042 | (\[7520] & n3722); - assign n1331 = ~preset & (n3825 ? n3753 : \[7535] ); - assign n1336 = n5041 | (n3731_1 & n3748); - assign n1341 = n5040 | (n3727 & n3733); - assign n1346 = n5039 | (n3727 & n3752); - assign n1351 = (\[7595] & n3729) | (n3730 & n3744); - assign n1356 = (n3724 & n3750_1) | (\[7625] & n3751); - assign n1361 = n5038 | (n4081 & n3749); - assign n1366 = n5037 | (n4081 & n3743); - assign n1371 = (\[7670] & n3722) | (n3723 & n3746_1); - assign n1376 = n5942 | n5034 | n5035; - assign n1381 = n5948 | n5946 | n5947; - assign n1385 = n5016 | n5018 | n5019 | n5950; - assign n1389 = n5012 | n5014 | n5015 | n5952; - assign n1393 = n5011 | (pdata_6_6_ & n3703); - assign n1398 = ~preset & (n3792_1 ? pdata_3_3_ : \[7760] ); - assign n1403 = ~preset & (n3817_1 ? pdata_12_12_ : \[7775] ); - assign n1408 = ~preset & (n3817_1 ? pdata_5_5_ : \[7790] ); - assign n1413 = n5010 | (pdata_2_2_ & n3708); - assign n1418 = n5009 | (pdata_11_11_ & n3708); - assign n1423 = n5008 | (pdata_0_0_ & n4504); - assign n1428 = n5007 | (pdata_9_9_ & n4504); - assign n1433 = n5005 | n5006; - assign n1438 = n5003 | n5004; - assign n1443 = ~preset & (n3813 ? pdata_8_8_ : \[7895] ); - assign n1448 = ~preset & (n3813 ? pdata_5_5_ : \[7910] ); - assign n1453 = ~preset & (n3813 ? pdata_14_14_ : \[7925] ); - assign n1458 = n5002 | (pdata_3_3_ & n3711_1); - assign n1463 = n5001 | (pdata_12_12_ & n3711_1); - assign n1468 = (n4160 & n3720) | (\[7970] & n3713); - assign n1473 = n5000 | (\[8000] & n3707); - assign n1478 = n4998 | n4999; - assign n1483 = n4996 | n4997; - assign n1488 = (n3712 & n3718) | (\[8045] & n3717); - assign n1493 = n4995 | (\[8060] & n3717); - assign n1498 = n4994 | (n4547 & n3741_1); - assign n1503 = n4992 | n4993; - assign n1508 = n4991 | (\[8105] & n3710); - assign n1513 = n4990 | (n3712 & n3721_1); - assign n1518 = n4988 | n4989; - assign n1523 = n4987 | (n3719 & n3721_1); - assign n1528 = ~preset & (n3825 ? n3733 : \[8165] ); - assign n1533 = n4986 | (n3726_1 & n3748); - assign n1538 = n4985 | (n3727 & n3753); - assign n1543 = n4984 | (n3727 & (~n3930 ^ n3931)); - assign n1548 = (\[8225] & n3729) | (n3730 & n3742); - assign n1553 = (\[8240] & n3734) | (n3735 & n3749); - assign n1558 = (n3742 & n3750_1) | (\[8255] & n3751); - assign n1563 = n4983 | (n4081 & n3737); - assign n1568 = (\[8300] & n3722) | (n3723 & n3728); - assign n1573 = (\[8315] & n3738) | (n3739 & n3752); - assign n1578 = n5953 | n4980 | n4981; - assign n1583 = n5959 | n5957 | n5958; - assign n1587 = n4962 | n4964 | n4965 | n5961; - assign n1591 = n4958 | n4960 | n4961 | n5963; - assign n1595 = n4957 | (pdata_9_9_ & n3703); - assign n1600 = ~preset & (n3792_1 ? pdata_0_0_ : \[8405] ); - assign n1605 = ~preset & (n3817_1 ? pdata_13_13_ : \[8420] ); - assign n1610 = ~preset & (n3817_1 ? pdata_8_8_ : \[8435] ); - assign n1615 = ~preset & (n3817_1 ? pdata_15_15_ : \[8450] ); - assign n1620 = n4956 | (pdata_10_10_ & n3708); - assign n1625 = n4955 | (pdata_1_1_ & n4504); - assign n1630 = n4954 | (pdata_12_12_ & n4504); - assign n1635 = n4952 | n4953; - assign n1640 = ~preset & (n3813 ? pdata_0_0_ : \[8525] ); - assign n1645 = ~preset & (n3813 ? pdata_11_11_ : \[8540] ); - assign n1650 = ~preset & (n3813 ? pdata_2_2_ : \[8555] ); - assign n1655 = ~preset & (n3813 ? pdata_13_13_ : \[8570] ); - assign n1660 = n4951 | (pdata_4_4_ & n3711_1); - assign n1665 = n4950 | (pdata_15_15_ & n3711_1); - assign n1670 = (n4160 & n3741_1) | (\[8615] & n3713); - assign n1675 = n4949 | (n3706_1 & (n3893_1 ^ n3894)); - assign n1680 = n4948 | (\[8645] & n3707); - assign n1685 = n4947 | (n3712 & n3716_1); - assign n1690 = n4946 | (n3714 & n3716_1); - assign n1695 = n4945 | (\[8690] & n3717); - assign n1700 = n4944 | (\[8705] & n3717); - assign n1705 = n4943 | (n4547 & n3747); - assign n1710 = n4942 | (n4106 & n3740); - assign n1715 = n4941 | (\[8750] & n3710); - assign n1720 = (n3709 & n3719) | (\[8765] & n3710); - assign n1725 = n4940 | (n3720 & n3721_1); - assign n1730 = n4939 | (\[8810] & n3722); - assign n1735 = n4938 | (n3743 & n3748); - assign n1740 = n4937 | (n3727 & n3746_1); - assign n1745 = n4936 | (n3727 & n3737); - assign n1750 = (n3724 & n3730) | (\[8870] & n3729); - assign n1755 = (\[8885] & n3729) | (n3730 & n3745); - assign n1760 = n4935 | (n3732 & n3742); - assign n1765 = (n3744 & n3750_1) | (\[8915] & n3751); - assign n1770 = n4934 | (n4081 & n3753); - assign n1775 = n4933 | (n4081 & n3731_1); - assign n1780 = (\[8960] & n3722) | (n3723 & n3733); - assign n1785 = (n3728 & n3739) | (\[8975] & n3738); - assign n1790 = n5969 | n5967 | n5968; - assign n1794 = n5975 | n5973 | n5974; - assign n1798 = n4901 | n4903 | n4904 | n5977; - assign n1802 = n4897 | n4899 | n4900 | n5979; - assign n1806 = n4896 | (pdata_8_8_ & n3703); - assign n1811 = ~preset & (n3792_1 ? pdata_1_1_ : \[9065] ); - assign n1816 = ~preset & (n3817_1 ? pdata_14_14_ : \[9080] ); - assign n1821 = ~preset & (n3817_1 ? pdata_7_7_ : \[9095] ); - assign n1826 = n4895 | (pdata_0_0_ & n3708); - assign n1831 = n4894 | (pdata_9_9_ & n3708); - assign n1836 = n4893 | (pdata_2_2_ & n4504); - assign n1841 = n4892 | (pdata_11_11_ & n4504); - assign n1846 = n4890 | n4891; - assign n1851 = ~preset & (n3813 ? pdata_1_1_ : \[9185] ); - assign n1856 = ~preset & (n3813 ? pdata_10_10_ : \[9200] ); - assign n1861 = ~preset & (n3813 ? pdata_3_3_ : \[9215] ); - assign n1866 = ~preset & (n3813 ? pdata_12_12_ : \[9230] ); - assign n1871 = n4889 | (pdata_5_5_ & n3711_1); - assign n1876 = n4888 | (pdata_14_14_ & n3711_1); - assign n1881 = n4887 | (\[9275] & n3713); - assign n1886 = (n3706_1 & n3712) | (\[9290] & n3707); - assign n1891 = n4886 | (\[9305] & n3707); - assign n1896 = n4884 | n4885; - assign n1901 = n4882 | n4883; - assign n1906 = (\[9350] & n3717) | (n3718 & n3747); - assign n1911 = (n3714 & n3718) | (\[9365] & n3717); - assign n1916 = n4880 | n4881; - assign n1921 = n4879 | (n4106 & n3719); - assign n1926 = n4878 | (\[9410] & n3710); - assign n1931 = n4876 | n4877; - assign n1936 = n4875 | (n3723 & (n3893_1 ^ n3894)); - assign n1941 = (n3720 & n3723) | (\[9470] & n3722); - assign n1946 = ~preset & (n3825 ? n3736_1 : \[9485] ); - assign n1951 = n4874 | (n3737 & n3748); - assign n1956 = n4873 | (n3727 & n3728); - assign n1961 = n4872 | (n3727 & n3745); - assign n1966 = (\[9545] & n3729) | (n3730 & n3746_1); - assign n1971 = (\[9560] & n3729) | (n3730 & n3752); - assign n1976 = n4871 | (n3724 & n3732); - assign n1981 = (n3731_1 & n3750_1) | (\[9590] & n3751); - assign n1986 = n4870 | (n4081 & n3736_1); - assign n1991 = n4869 | (n4081 & n3726_1); - assign n1996 = (\[9635] & n3722) | (n3723 & n3753); - assign n2001 = (\[9650] & n3722) | (n3723 & n3743); - assign n2006 = n4868 | (pdata_1_1_ & n3754_1); - assign n2011 = n4867 | (pdata_12_12_ & n3754_1); - assign n2016 = n4865 | (n3755 & n3756) | n4866; - assign n2020 = ~preset & (n3813 ? pdata_2_2_ : \[9710] ); - assign n2025 = n4864 | (\[9725] & n3707); - assign n2030 = n4863 | (\[9740] & n3707); - assign n2035 = n4862 | (\[9770] & n3710); - assign n2040 = n4860 | n4861; - assign n2045 = n4859 | (n3745 & n3748); - assign n2050 = n4858 | (n3727 & n3742); - assign n2055 = (\[9830] & n3729) | (n3730 & n3736_1); - assign n2060 = (\[9845] & n3729) | (n3730 & n3737); - assign n2065 = (n3726_1 & n3750_1) | (\[9860] & n3751); - assign n2070 = n4857 | (n4081 & n3728); - assign n2075 = n4856 | (n4081 & (~n3930 ^ n3931)); - assign n2080 = (\[9905] & n3722) | (n3723 & n3731_1); - assign n2085 = (n3733 & n3739) | (\[9920] & n3738); - assign n2090 = n4855 | (pdata_0_0_ & n3754_1); - assign n2095 = n4854 | (pdata_6_6_ & n3757); - assign n2100 = ~preset & (n3813 ? pdata_12_12_ : \[9980] ); - assign n2105 = (n3706_1 & n3747) | (\[9995] & n3707); - assign n2110 = (n3706_1 & n3714) | (\[10010] & n3707); - assign n2115 = n4853 | (n3709 & (n3893_1 ^ n3894)); - assign n2120 = (n3709 & n3720) | (\[10040] & n3710); - assign n2125 = n4852 | (n3721_1 & n3740); - assign n2130 = n4851 | (n3748 & n3752); - assign n2135 = n4850 | (n3724 & n3727); - assign n2140 = (\[10100] & n3729) | (n3730 & n3753); - assign n2145 = (\[10115] & n3729) | (n3730 & n3743); - assign n2150 = (n3743 & n3750_1) | (\[10130] & n3751); - assign n2155 = n4849 | (n4081 & n3733); - assign n2160 = (\[10175] & n3722) | (n3723 & n3744); - assign n2165 = (\[10190] & n3738) | (n3739 & n3745); - assign n2170 = n4848 | (pdata_10_10_ & n3754_1); - assign n2175 = n4847 | (pdata_5_5_ & n3757); - assign n2180 = n4846 | (\[12200] & (n5627 | n5628)); - assign n2184 = n4844 | (n3756 & n3758_1) | n4845; - assign n2188 = ~preset & (n3813 ? pdata_6_6_ : \[10265] ); - assign n2193 = n4842 | n4843; - assign n2198 = (n3709 & n3712) | (\[10310] & n3710); - assign n2203 = n4840 | n4841; - assign n2208 = n4838 | n4839; - assign n2213 = n4837 | (n3748 & (~n3930 ^ n3931)); - assign n2218 = n4836 | (n3727 & n3731_1); - assign n2223 = (n3726_1 & n3730) | (\[10400] & n3729); - assign n2228 = (n3737 & n3750_1) | (\[10415] & n3751); - assign n2233 = n4835 | (n4081 & n3724); - assign n2238 = n4834 | (n4081 & n3745); - assign n2243 = (\[10460] & n3722) | (n3723 & n3742); - assign n2248 = n4833 | (pdata_2_2_ & n3754_1); - assign n2253 = n4832 | (pdata_11_11_ & n3754_1); - assign n2258 = n4831 | (pdata_4_4_ & n3757); - assign n2263 = n4830 | (\[12080] & (n5627 | n5628)); - assign n2267 = n4828 | (n3756 & n3759) | n4829; - assign n2271 = n4827 | (pdata_0_0_ & n3711_1); - assign n2276 = n4826 | (n3716_1 & n3741_1); - assign n2281 = n4825 | (n3716_1 & n3719); - assign n2286 = n4824 | (\[10595] & n3710); - assign n2291 = n4823 | (n3721_1 & n3747); - assign n2296 = n4822 | (n3714 & n3721_1); - assign n2301 = n4821 | (n3727 & n3744); - assign n2306 = (\[10670] & n3729) | (n3730 & n3749); - assign n2311 = (\[10685] & n3729) | (n3730 & n3731_1); - assign n2316 = (n3745 & n3750_1) | (\[10700] & n3751); - assign n2321 = n4820 | (n4081 & n3746_1); - assign n2326 = n4819 | (n4081 & n3752); - assign n2331 = (\[10745] & n3722) | (n3723 & n3724); - assign n2336 = n4818 | (pdata_13_13_ & n3696_1); - assign n2341 = n4817 | (pdata_8_8_ & n3754_1); - assign n2346 = n4816 | (pdata_3_3_ & n3757); - assign n2351 = n4815 | (pdata_1_1_ & n3760); - assign n2356 = n4814 | (pdata_12_12_ & n3760); - assign n2361 = n4813 | (pdata_10_10_ & n3711_1); - assign n2366 = n4812 | (\[10865] & n3717); - assign n2371 = n4810 | n4811; - assign n2376 = n4809 | (\[10895] & n3722); - assign n2381 = ~preset & (n3825 ? n3726_1 : \[10925] ); - assign n2386 = n4808 | (n3732 & n3753); - assign n2391 = n4807 | (n3732 & n3745); - assign n2396 = (\[10970] & n3734) | (n3735 & n3742); - assign n2401 = (n3750_1 & n3752) | (\[10985] & n3751); - assign n2406 = (n3726_1 & n3739) | (\[11015] & n3738); - assign n2411 = n4806 | (pdata_12_12_ & n3696_1); - assign n2416 = n4805 | (pdata_9_9_ & n3754_1); - assign n2421 = n4804 | (pdata_2_2_ & n3757); - assign n2426 = n4803 | (pdata_7_7_ & n3757); - assign n2431 = n4802 | (pdata_13_13_ & n3760); - assign n2436 = n4801 | (\[11120] & n3713); - assign n2441 = (\[11135] & n3717) | (n3718 & n3720); - assign n2446 = n4800 | (n4547 & n3712); - assign n2451 = (\[11165] & n3722) | (n3723 & n3741_1); - assign n2456 = (n3719 & n3723) | (\[11180] & n3722); - assign n2461 = n4799 | (n3732 & n3733); - assign n2466 = n4798 | (n3732 & n3737); - assign n2471 = (\[11225] & n3734) | (n3735 & n3744); - assign n2476 = n4797 | (n4081 & n3742); - assign n2481 = (\[11255] & n3738) | (n3739 & n3749); - assign n2486 = (n3731_1 & n3739) | (\[11270] & n3738); - assign n2491 = n4796 | (pdata_15_15_ & n3696_1); - assign n2496 = n4795 | (pdata_6_6_ & n3754_1); - assign n2501 = n4794 | (pdata_1_1_ & n3757); - assign n2506 = n4793 | (pdata_8_8_ & n3757); - assign n2511 = n4792 | (pdata_3_3_ & n3760); - assign n2516 = (n4160 & n3740) | (\[11375] & n3713); - assign n2521 = n4790 | n4791; - assign n2526 = n4789 | (\[11405] & n3722); - assign n2531 = ~preset & (n3825 ? n3744 : \[11420] ); - assign n2536 = n4788 | (n3728 & n3732); - assign n2541 = n4787 | (n3732 & (~n3930 ^ n3931)); - assign n2546 = (\[11465] & n3734) | (n3735 & n3746_1); - assign n2551 = (\[11480] & n3722) | (n3723 & n3749); - assign n2556 = (n3736_1 & n3739) | (\[11495] & n3738); - assign n2561 = (n3737 & n3739) | (\[11510] & n3738); - assign n2566 = n4786 | (pdata_14_14_ & n3696_1); - assign n2571 = n4785 | (pdata_7_7_ & n3754_1); - assign n2576 = n4784 | (pdata_0_0_ & n3757); - assign n2581 = n4783 | (pdata_9_9_ & n3757); - assign n2586 = n4782 | (pdata_2_2_ & n3760); - assign n2591 = n4781 | (pdata_11_11_ & n3760); - assign n2596 = n4780 | (n4547 & n3714); - assign n2601 = ~preset & (n3825 ? n3749 : \[11630] ); - assign n2606 = ~preset & (n3825 ? n3731_1 : \[11645] ); - assign n2611 = n4779 | (n3732 & n3746_1); - assign n2616 = n4778 | (n3732 & n3752); - assign n2621 = (n3724 & n3735) | (\[11690] & n3734); - assign n2626 = (\[11705] & n3722) | (n3723 & n3726_1); - assign n2631 = (\[11720] & n3738) | (n3739 & n3753); - assign n2636 = (\[11735] & n3738) | (n3739 & n3743); - assign n2641 = n4777 | (pdata_9_9_ & n3696_1); - assign n2646 = n4776 | (pdata_4_4_ & n3754_1); - assign n2651 = n4775 | (pdata_15_15_ & n3754_1); - assign n2656 = n4774 | (pdata_10_10_ & n3757); - assign n2661 = n4773 | (pdata_5_5_ & n3760); - assign n2666 = n4771 | (n3756 & n3761) | n4772; - assign n2670 = n5983 | n5980 | n5981; - assign n2674 = n4760 | (pdata_5_5_ & n3754_1); - assign n2679 = n4759 | (pdata_14_14_ & n3754_1); - assign n2684 = n4758 | (pdata_11_11_ & n3757); - assign n2689 = n4757 | (pdata_4_4_ & n3760); - assign n2694 = n4755 | (n3756 & n3762) | n4756; - assign n2698 = n4753 | n5985 | n5986 | n5987; - assign n2702 = (n3736_1 & n3764) | (\[12005] & n3763_1); - assign n2707 = n4743 | (pdata_11_11_ & n3696_1); - assign n2712 = n4742 | (pdata_13_13_ & n3754_1); - assign n2717 = n4741 | (pdata_12_12_ & n3757); - assign n2722 = n4740 | (pdata_7_7_ & n3760); - assign n2727 = n4739 | (pdata_14_14_ & n3760); - assign n2732 = n4737 | (n3756 & n3765) | n4738; - assign n2736 = (n3743 & n3764) | (\[12125] & n3763_1); - assign n2741 = n4736 | (pdata_10_10_ & n3696_1); - assign n2746 = n4735 | (pdata_3_3_ & n3754_1); - assign n2751 = n4734 | (pdata_13_13_ & n3757); - assign n2756 = n4733 | (pdata_6_6_ & n3760); - assign n2761 = n4732 | (pdata_15_15_ & n3760); - assign n2766 = n4730 | n5989 | n5990 | n5991; - assign n2770 = (n3728 & n3750_1) | (\[12245] & n3751); - assign n2775 = n4720 | (pdata_14_14_ & n3757); - assign n2780 = n4719 | (pdata_9_9_ & n3760); - assign n2785 = n4718 | (\[11090] & (n5627 | n5628)); - assign n2789 = n4716 | (n3756 & n3766) | n4717; - assign n2793 = n4715 | (\[12335] & n3704); - assign n2798 = n4713 | n4714; - assign n2803 = n4712 | (n3962 & n3719); - assign n2808 = n4711 | (n3736_1 & n3767); - assign n2813 = n4710 | (n3737 & n3767); - assign n2818 = n4709 | (n3724 & n3748); - assign n2823 = n4708 | (n3735 & (~n3930 ^ n3931)); - assign n2828 = (n3731_1 & n3764) | (\[12440] & n3763_1); - assign n2833 = (n3733 & n3750_1) | (\[12455] & n3751); - assign n2838 = n4707 | (pdata_15_15_ & n3757); - assign n2843 = n4706 | (pdata_8_8_ & n3760); - assign n2848 = n4705 | (\[10820] & (n5627 | n5628)); - assign n2852 = n4703 | (n3756 & n3768_1) | n4704; - assign n2856 = n4701 | n4702; - assign n2861 = (n4427 & n3741_1) | (\[12560] & n3704); - assign n2866 = n4700 | (n3962 & n3747); - assign n2871 = n4698 | n4699; - assign n2876 = n4697 | (n3749 & n3767); - assign n2881 = n4696 | (n3745 & n3767); - assign n2886 = n4695 | (n3746_1 & n3748); - assign n2891 = (\[12650] & n3734) | (n3735 & n3752); - assign n2896 = (n3726_1 & n3764) | (\[12665] & n3763_1); - assign n2901 = (n3750_1 & n3753) | (\[12680] & n3751); - assign n2906 = n4694 | (pdata_0_0_ & n3760); - assign n2911 = n4692 | (n3756 & n3769) | n4693; - assign n2915 = n4690 | (n3756 & n3770) | n4691; - assign n2919 = n4688 | n4689; - assign n2924 = n4686 | n4687; - assign n2929 = n4684 | n4685; - assign n2934 = n4682 | n4683; - assign n2939 = n4681 | (n3733 & n3767); - assign n2944 = n4680 | (n3726_1 & n3767); - assign n2949 = n4679 | (n3728 & n3748); - assign n2954 = (n3749 & n3764) | (\[12890] & n3763_1); - assign n2959 = (n3742 & n3764) | (\[12905] & n3763_1); - assign n2964 = (n3736_1 & n3750_1) | (\[12920] & n3751); - assign n2969 = n4678 | (pdata_10_10_ & n3760); - assign n2974 = n4676 | (n3756 & n3771) | n4677; - assign n2978 = n4674 | (n3756 & n3772_1) | n4675; - assign n2982 = n4672 | n4673; - assign n2987 = n4671 | (n3715 & (n3893_1 ^ n3894)); - assign n2992 = n4670 | (n3715 & n3720); - assign n2997 = n4668 | n4669; - assign n3002 = n4667 | (n3962 & n3740); - assign n3007 = n4666 | (n4106 & n3741_1); - assign n3012 = n4665 | (n3753 & n3767); - assign n3017 = n4664 | (n3743 & n3767); - assign n3022 = n4663 | (n3733 & n3748); - assign n3027 = (n3744 & n3764) | (\[13160] & n3763_1); - assign n3032 = (n3749 & n3750_1) | (\[13175] & n3751); - assign n3037 = n5995 | n5992 | n5993; - assign n3041 = n6001 | n5999 | n6000; - assign n3045 = n4644 | (pdata_3_3_ & n3703); - assign n3050 = n4643 | (pdata_14_14_ & n3703); - assign n3055 = ~preset & (n3792_1 ? pdata_14_14_ : \[13250] ); - assign n3060 = n4642 | (pdata_9_9_ & n3705); - assign n3065 = ~preset & (n3817_1 ? pdata_4_4_ : \[13280] ); - assign n3070 = n4640 | n4641; - assign n3075 = n4638 | n4639; - assign n3080 = n4636 | n4637; - assign n3085 = n4634 | n4635; - assign n3090 = (n4427 & n3747) | (\[13355] & n3704); - assign n3095 = (n4427 & n3740) | (\[13370] & n3704); - assign n3100 = n4632 | n4633; - assign n3105 = n4631 | (n3962 & (n3893_1 ^ n3894)); - assign n3110 = n4629 | n4630; - assign n3115 = n4627 | n4628; - assign n3120 = ~preset & (n3825 ? n3752 : \[13445] ); - assign n3125 = n4626 | (n3744 & n3767); - assign n3130 = n4625 | (n3748 & n3753); - assign n3135 = (\[13490] & n3734) | (n3735 & n3743); - assign n3140 = (n3746_1 & n3764) | (\[13505] & n3763_1); - assign n3145 = n6005 | n6002 | n6003; - assign n3149 = n6006 | n4612 | n4613; - assign n3154 = n4608 | n4610 | n4611 | n6008; - assign n3158 = n4607 | (pdata_15_15_ & n3703); - assign n3163 = ~preset & (n3792_1 ? pdata_13_13_ : \[13595] ); - assign n3168 = n4606 | (pdata_10_10_ & n3705); - assign n3173 = ~preset & (n3817_1 ? pdata_3_3_ : \[13625] ); - assign n3178 = n4604 | n4605; - assign n3183 = n4602 | n4603; - assign n3188 = n4600 | n4601; - assign n3193 = n4598_1 | n4599; - assign n3198 = n4597 | (\[13700] & n3713); - assign n3203 = n4596 | (\[13715] & n3704); - assign n3208 = (n4427 & n3719) | (\[13730] & n3704); - assign n3213 = n4594_1 | n4595; - assign n3218 = n4593 | (n3962 & n3714); - assign n3223 = n4591 | n4592; - assign n3228 = ~preset & (n3825 ? n3745 : \[13805] ); - assign n3233 = n4590 | (n3731_1 & n3767); - assign n3238 = n4589_1 | (n3736_1 & n3748); - assign n3243 = (n3726_1 & n3735) | (\[13850] & n3734); - assign n3248 = (n3724 & n3764) | (\[13865] & n3763_1); - assign n3253 = n4588 | (n3764 & (~n3930 ^ n3931)); - assign n3258 = n4587 | (pdata_8_8_ & n3696_1); - assign n3263 = n6014 | n6012 | n6013; - assign n3267 = n6018 | n4577 | n6016; - assign n3271 = n4560 | n4562 | n4563 | n6020; - assign n3275 = n4559 | (pdata_5_5_ & n3703); - assign n3280 = n4558 | (pdata_0_0_ & n3705); - assign n3285 = n4557_1 | (pdata_7_7_ & n3705); - assign n3290 = ~preset & (n3817_1 ? pdata_2_2_ : \[14000] ); - assign n3295 = n4556 | (pdata_13_13_ & n3708); - assign n3300 = n4555 | (pdata_8_8_ & n4504); - assign n3305 = n4553 | n4554; - assign n3310 = n4551 | n4552_1; - assign n3315 = n4549 | n4550; - assign n3320 = n4548 | (pdata_11_11_ & n3711_1); - assign n3325 = n4547_1 | (\[14105] & n3704); - assign n3330 = (n4427 & n3714) | (\[14120] & n3704); - assign n3335 = n4546 | (n3715 & n3741_1); - assign n3340 = n4544 | n4545; - assign n3345 = n4543 | (n3962 & n3720); - assign n3350 = n4542_1 | (n4106 & n3747); - assign n3355 = n4541 | (n3724 & n3767); - assign n3360 = n4540 | (n3748 & n3749); - assign n3365 = (\[14240] & n3734) | (n3735 & n3745); - assign n3370 = (n3733 & n3764) | (\[14255] & n3763_1); - assign n3375 = (n3752 & n3764) | (\[14270] & n3763_1); - assign n3380 = n4539 | (pdata_7_7_ & n3696_1); - assign n3385 = n4537_1 | n6022 | n6023 | n6024; - assign n3389 = n6028 | n4527 | n6026; - assign n3393 = n6032 | n4513 | n6030; - assign n3397 = n4496 | n4498 | n4499_1 | n6034; - assign n3401 = n4495 | (pdata_4_4_ & n3703); - assign n3406 = n4494_1 | (pdata_13_13_ & n3703); - assign n3411 = ~preset & (n3792_1 ? pdata_15_15_ : \[14390] ); - assign n3416 = n4493 | (pdata_8_8_ & n3705); - assign n3421 = ~preset & (n3817_1 ? pdata_1_1_ : \[14420] ); - assign n3426 = n4492 | (pdata_14_14_ & n3708); - assign n3431 = n4491 | (pdata_7_7_ & n4504); - assign n3436 = n4489_1 | n4490; - assign n3441 = n4487 | n4488; - assign n3446 = n4485_1 | n4486; - assign n3451 = n4484 | (pdata_1_1_ & n3711_1); - assign n3456 = n4483 | (\[14525] & n3704); - assign n3461 = n4482 | (\[14540] & n3704); - assign n3466 = n4480_1 | n4481; - assign n3471 = n4479 | (n3962 & n3712); - assign n3476 = n4477 | n4478; - assign n3481 = n4475_1 | n4476; - assign n3486 = n4474 | (n3725 & (~n3930 ^ n3931)); - assign n3491 = n4473 | (n3742 & n3767); - assign n3496 = (\[14660] & n3734) | (n3735 & n3737); - assign n3501 = (n3728 & n3764) | (\[14675] & n3763_1); - assign n3506 = (n3745 & n3764) | (\[14690] & n3763_1); - assign n3511 = n4472 | (pdata_6_6_ & n3696_1); - assign n3516 = n4470_1 | n6036 | n6037 | n6038; - assign n3520 = n6044 | n6042 | n6043; - assign n3524 = n6048 | n4451 | n6046; - assign n3528 = n6049 | n4435 | n4436; - assign n3533 = n6055 | n6053 | n6054; - assign n3537 = n4417_1 | n4419 | n4420 | n6057; - assign n3541 = ~preset & (n3792_1 ? pdata_10_10_ : \[14810] ); - assign n3546 = n4416 | (pdata_5_5_ & n3705); - assign n3551 = ~preset & (n3817_1 ? pdata_0_0_ : \[14840] ); - assign n3556 = ~preset & (n3817_1 ? pdata_9_9_ : \[14855] ); - assign n3561 = n4415 | (pdata_4_4_ & n3708); - assign n3566 = n4413 | n4414; - assign n3571 = n4411 | n4412_1; - assign n3576 = n4409 | n4410; - assign n3581 = ~preset & (n3813 ? pdata_7_7_ : \[14930] ); - assign n3586 = n4408 | (\[14960] & n3704); - assign n3591 = n4406 | n4407_1; - assign n3596 = n4404 | n4405; - assign n3601 = n4402_1 | n4403; - assign n3606 = n4401 | (n4106 & n3712); - assign n3611 = n4400 | (n3728 & n3767); - assign n3616 = n4399 | (n3767 & (~n3930 ^ n3931)); - assign n3621 = (n3737 & n3764) | (\[15065] & n3763_1); - assign n3626 = n4398 | (pdata_5_5_ & n3696_1); - assign n3631 = n4396 | n6059 | n6060 | n6061; - assign n3635 = n6067 | n6065 | n6066; - assign n3639 = n6071 | n4378_1 | n6069; - assign n3643 = n6072 | n4362 | n4363_1; - assign n3648 = n6078 | n6076 | n6077; - assign n3652 = n4344 | n4346 | n4347 | n6080; - assign n3656 = ~preset & (n3792_1 ? pdata_9_9_ : \[15185] ); - assign n3661 = n4343_1 | (pdata_6_6_ & n3705); - assign n3666 = n4342 | (pdata_15_15_ & n3705); - assign n3671 = ~preset & (n3817_1 ? pdata_10_10_ : \[15230] ); - assign n3676 = n4341 | (pdata_3_3_ & n3708); - assign n3681 = n4339 | n4340; - assign n3686 = n4337 | n4338_1; - assign n3691 = n4335 | n4336; - assign n3696 = ~preset & (n3813 ? pdata_13_13_ : \[15305] ); - assign n3701 = (n4160 & n3719) | (\[15320] & n3713); - assign n3706 = n4334 | (\[15335] & n3704); - assign n3711 = n4333_1 | (n3715 & n3747); - assign n3716 = n4331 | n4332; - assign n3721 = n4330 | (n4106 & (n3893_1 ^ n3894)); - assign n3726 = n4329 | (n3746_1 & n3767); - assign n3731 = n4328_1 | (n3752 & n3767); - assign n3736 = (n3753 & n3764) | (\[15425] & n3763_1); - assign n3741 = n4327 | (pdata_4_4_ & n3696_1); - assign n3746 = n4325 | n6082 | n6083 | n6084; - assign n3750 = n4315 | n6085 | n6086 | n6087; - assign n3754 = n6091 | n4302 | n6089; - assign n3758 = n6092 | n4286 | n4287; - assign n3763 = n6093 | n4283 | n4284; - assign n3768 = n6099 | n6097 | n6098; - assign n3772 = ~preset & (n3792_1 ? pdata_12_12_ : \[15545] ); - assign n3777 = n4268 | (pdata_3_3_ & n3705); - assign n3782 = n4267 | (pdata_14_14_ & n3705); - assign n3787 = ~preset & (n3817_1 ? pdata_5_5_ : \[15590] ); - assign n3792 = ~preset & (n3817_1 ? pdata_0_0_ : \[15605] ); - assign n3797 = n4265_1 | n4266; - assign n3802 = n4263 | n4264; - assign n3807 = n4261_1 | n4262; - assign n3812 = ~preset & (n3813 ? pdata_3_3_ : \[15665] ); - assign n3817 = (n4427 & n3712) | (\[15680] & n3704); - assign n3822 = n4260 | (\[15695] & n3704); - assign n3827 = n4258 | n4259; - assign n3832 = n4257 | (n4547 & n3719); - assign n3837 = ~preset & (n3825 ? n3737 : \[15755] ); - assign n3842 = (n3731_1 & n3735) | (\[15770] & n3734); - assign n3847 = n4256_1 | (pdata_3_3_ & n3696_1); - assign n3852 = n6103 | n6100 | n6101; - assign n3856 = n6109 | n6107 | n6108; - assign n3860 = n6113 | n4237_1 | n6111; - assign n3864 = n6114 | n4221 | n4222; - assign n3869 = n6115 | n4218_1 | n4219; - assign n3874 = n6121 | n6119 | n6120; - assign n3878 = ~preset & (n3792_1 ? pdata_11_11_ : \[15890] ); - assign n3883 = n4203_1 | (pdata_4_4_ & n3705); - assign n3888 = n4202 | (pdata_13_13_ & n3705); - assign n3893 = ~preset & (n3817_1 ? pdata_6_6_ : \[15935] ); - assign n3898 = ~preset & (n3817_1 ? pdata_15_15_ : \[15950] ); - assign n3903 = n4200 | n4201; - assign n3908 = n4198 | n4199_1; - assign n3913 = n4196 | n4197; - assign n3918 = n4194_1 | n4195; - assign n3923 = n4193 | (n4427 & (n3893_1 ^ n3894)); - assign n3928 = (n4427 & n3720) | (\[16040] & n3704); - assign n3933 = n4192 | (n3712 & n3715); - assign n3938 = n4191 | (n4547 & n3740); - assign n3943 = n4190 | (n3962 & n3741_1); - assign n3948 = ~preset & (n3825 ? n3743 : \[16100] ); - assign n3953 = n6140 | n6141; - assign n3957 = n4175 | n6142; - assign n3962 = n3876 & n3798 & ~preset & ~\[16920] ; - assign n3967 = n4141 | (n3798 & n3803 & n6143); - assign n3972 = n6149 | n6150; - assign n3976 = n4163 | n6151; - assign n3981 = \[16972] & ~preset & ~\[16920] ; - assign n3986 = ~\[18389] & ~preset & \[16985] ; - assign n3991 = n4161 | n6152; - assign n3996 = ~preset & (\[17011] | n3858 | n3859); - assign n4001 = ~preset & ~pdn; - assign n4006 = ~preset & ~\[17102] & (\[17037] | \[18025] ); - assign n4011 = \[17115] & ~preset & ~\[17050] ; - assign n4016 = n4159 | n6153; - assign n4021 = n4157 | n6154; - assign n4026 = \[17089] & ~preset & ~pdn; - assign n4031 = ~\[17102] & ~preset & \[17037] ; - assign n4036 = n4011 | (n3798 & n3826 & n6155); - assign n4041 = n4155_1 | n6156; - assign n4046 = ~preset & (\[17141] | n3858 | n3859); - assign n4051 = \[17154] & ~preset & ~\[17102] ; - assign n4056 = n3819 & n3798 & ~preset & ~\[17167] ; - assign n4061 = n4081 | (n3798 & n3827_1 & n6157); - assign n4066 = n4153 | n6158; - assign n4071 = n4096 | (n3798 & n3808 & n6159); - assign n4076 = \[17219] & ~preset & ~\[17050] ; - assign n4081 = ~\[17232] & ~preset & \[17180] ; - assign n4086 = ~preset & \[17245] & (~n3798 | ~n3811); - assign n4091 = n4151 | n6160; - assign n4096 = ~\[17271] & ~preset & \[17206] ; - assign n4101 = n4504 | (n3798 & n3802_1 & n6161); - assign n4106 = n3812_1 & n3798 & ~preset & ~\[17297] ; - assign n4111 = ~\[17388] & ~preset & \[17310] ; - assign n4116 = n4149 | n6162; - assign n4121 = ~preset & (\[17336] | n3858 | n3859); - assign n4126 = \[17349] & ~preset & ~\[17271] ; - assign n4131 = \[17362] & ~preset & ~\[17167] ; - assign n4136 = \[17375] & ~preset & ~\[17297] ; - assign n4141 = ~\[17388] & ~preset & \[16933] ; - assign n4146 = n6168 | n6169; - assign n4150 = \[17843] & ~preset & ~\[17414] ; - assign n4155 = ~preset & ~\[17700] & (\[17427] | \[17518] ); - assign n4160 = n5734 & n5729 & ~preset & n3798; - assign n4165 = n6175 | n6176; - assign n4169 = ~preset & (\[17479] | n3858 | n3859); - assign n4174 = n4127 | n6177; - assign n4179 = \[17505] & ~preset & ~\[17414] ; - assign n4184 = ~preset & ~\[17700] & (\[17518] | \[17817] ); - assign n4189 = n4126_1 | (\[17531] & n3784); - assign n4194 = ~preset & (n3877 ? ppeaki_7_7_ : \[17544] ); - assign n4199 = n6183 | n6184; - assign n4203 = ~preset & ~n3786 & (\[17570] | n3785); - assign n4208 = ~preset & ~\[17700] & (\[17583] | \[17648] ); - assign n4213 = n4114 | (~n3786 & n6195); - assign n4218 = ~preset & (n3877 ? ppeaki_6_6_ : \[17609] ); - assign n4223 = n6201 | n6202; - assign n4227 = ~preset & ~n3786 & (\[17570] | \[17635] ); - assign n4232 = ~preset & ~\[17700] & (\[17427] | \[17648] ); - assign n4237 = n6191 & n6188 & ~preset & n6187; - assign n4242 = ~preset & (n3877 ? ppeaki_5_5_ : \[17674] ); - assign n4247 = n6208 | n6209; - assign n4251 = \[18142] & ~preset & ~\[17700] ; - assign n4256 = ~preset & (n3877 ? ppeaki_4_4_ : \[17713] ); - assign n4261 = n6215 | n6216; - assign n4265 = \[17739] & ~preset & ~\[17700] ; - assign n4270 = n3784 & (\[17752] | (n3798 & n5729)); - assign n4275 = n4082 | n6217; - assign n4280 = n4080 | n6218; - assign n4285 = ~preset & ~\[17414] & (\[17791] | n3788); - assign n4290 = n3786 & ~preset & ~pdn; - assign n4295 = n4079 | (~preset & ~\[17700] & \[17817] ); - assign n4300 = n6229 | n6227 | n6228; - assign n4304 = ~preset & ~\[17414] & (\[17843] | (\[17791] & ~\[17843] )); - assign n4309 = ~preset & (\[17856] | n3790); - assign n4314 = ~preset & (\[17869] | n3858 | n3859); - assign n4319 = ~preset & (\[17882] | n3858 | n3859); - assign n4324 = n6254 | n6251 | n6252; - assign n4328 = ~preset & (\[17908] | n3858 | n3859); - assign n4333 = n4077 | n6255; - assign n4338 = ~preset & (\[17934] | n3858 | n3859); - assign n4343 = ~preset & (\[17947] | n3858 | n3859); - assign n4348 = ~preset & (\[17960] | n3858 | n3859); - assign n4353 = n4075 | n6256; - assign n4358 = ~preset & ~n3786 & (\[17635] | \[17986] ); - assign n4363 = ~preset & ~\[17700] & (\[17999] | \[18077] ); - assign n4368 = n4073 | n4074; - assign n4373 = n3779 & (\[18025] | (n3798 & n3806)); - assign n4378 = ~preset & (\[18038] | n3858 | n3859); - assign n4383 = ~preset & ~pdn & (\[17414] | n3786); - assign n4387 = n4072 | (~preset & ~pdn & \[18064] ); - assign n4392 = ~preset & ~\[17700] & (\[17583] | \[18077] ); - assign n4397 = n4070 | n4071_1; - assign n4402 = ~\[18168] & ~preset & \[18103] ; - assign n4407 = ~preset & (\[18116] | n3858 | n3859); - assign n4412 = n4068 | n4069; - assign n4417 = ~preset & ~\[17700] & (\[18142] | \[18220] ); - assign n4422 = n4066_1 | n4067; - assign n4427 = n5730 & n5729 & ~preset & n3798; - assign n4432 = ~preset & (\[18181] | n3858 | n3859); - assign n4437 = n4064 | n6258; - assign n4442 = ~preset & ~pdn & (\[18207] | n3790); - assign n4447 = ~preset & ~\[17700] & (\[17999] | \[18220] ); - assign n4452 = n4062 | n4063; - assign n4457 = \[18246] & ~preset & ~\[17453] ; - assign n4462 = n6264 | n6265; - assign n4466 = n4050 | n4251 | n4049; - assign n4470 = n4048 | (n3798 & n3800 & n6266); - assign n4475 = ~\[18376] & ~preset & \[18298] ; - assign n4480 = ~preset & ~\[18389] & (\[18311] | \[18506] ); - assign n4485 = n6272 | n6273; - assign n4489 = n4035 | n6274; - assign n4494 = ~preset & (\[18350] | n3858 | n3859); - assign n4499 = ~preset & ~\[18415] & (\[18363] | (\[18285] & ~\[18363] )); - assign n4504 = ~\[18376] & ~preset & \[17284] ; - assign n4509 = ~\[18389] & ~preset & \[18311] ; - assign n4514 = n6280 | n6281; - assign n4518 = ~\[18415] & ~preset & \[18363] ; - assign n4523 = ~\[18493] & ~preset & \[18428] ; - assign n4528 = \[18441] & ~preset & ~\[17232] ; - assign n4533 = n6287 | n6288; - assign n4537 = n4013 | n4014; - assign n4542 = \[18480] & ~preset & ~\[18415] ; - assign n4547 = n3821 & n3798 & ~preset & ~\[18493] ; - assign n4552 = n3778 & (\[18506] | (n3798 & n3801)); - assign n4557 = n6295 | n6296; - assign n4561 = n6302 | n6303; - assign n4565 = ~preset & ((\[18545] & (pdn | n3874_1)) | (~pdn & n3874_1)); - assign n4570 = n6309 | n6310; - assign n4574 = ~preset & (\[18571] | n3858 | n3859); - assign n4579 = ~preset & (\[18584] | n3858 | n3859); - assign n4584 = n3982 | (~preset & ~pdn & \[18597] ); - assign n4589 = n6316 | (\[18610] & n3784) | n6317; - assign n4594 = n6323 | n6324; - assign n4598 = n6332 | n3970 | n6331; - assign n3696_1 = ~\[17843] & ~preset & \[17791] ; - assign n3697 = n3857 & n3815 & n3756 & n3796; - assign n3698 = n3857 & n3814 & n3756 & n3796; - assign n3699 = n3857 & (n3702 | (n3756 & n3828)); - assign n3700 = n3857 & n3843 & n3756 & n3796; - assign n3701_1 = n3962_1 & n3756 & n3857; - assign n3702 = n3804 & (n5628 | (~n3955 & n3963)); - assign n3703 = ~\[18246] & ~preset & \[17453] ; - assign n3704 = ~preset & (~n3798 | ~n5729 | ~n5730); - assign n3705 = ~\[17154] & ~preset & \[17102] ; - assign n3706_1 = n3800 & n3798 & ~preset & ~\[18285] ; - assign n3707 = ~preset & (\[18285] | ~n3798 | ~n3800); - assign n3708 = ~\[17362] & ~preset & \[17167] ; - assign n3709 = n3801 & n3798 & ~preset & ~\[18506] ; - assign n3710 = ~preset & (\[18506] | ~n3798 | ~n3801); - assign n3711_1 = \[17388] & ~preset & ~\[17310] ; - assign n3712 = ((~n3891 ^ n3945) & (~n3893_1 | (n3893_1 & n3894))) | (n3893_1 & ~n3894 & (n3891 ^ n3945)); - assign n3713 = ~preset & (~n3798 | ~n5729 | ~n5734); - assign n3714 = ((n5483 | n5484) & (~n3880 ^ n3902)) | (~n5483 & ~n5484 & (~n3880 ^ ~n3902)); - assign n3715 = \[18168] & ~preset & ~\[18103] ; - assign n3716_1 = ~\[18363] & ~preset & \[18285] ; - assign n3717 = ~preset & (\[17284] | ~n3798 | ~n3802_1); - assign n3718 = n3802_1 & n3798 & ~preset & ~\[17284] ; - assign n3719 = n3916 ? ((n3914 & n3915) | (n3892 & (n3914 ^ n3915))) : (n3892 ? (~n3914 & ~n3915) : (~n3914 | (n3914 & ~n3915))); - assign n3720 = ((n5485 | n5486) & (~n3896 ^ n3917)) | (~n5485 & ~n5486 & (~n3896 ^ ~n3917)); - assign n3721_1 = \[18506] & ~preset & ~\[18311] ; - assign n3722 = ~preset & (\[16933] | ~n3798 | ~n3803); - assign n3723 = n3803 & n3798 & ~preset & ~\[16933] ; - assign n3724 = (ppeaka_6_6_ & n3810 & (n3861 ^ ~n3924)) | ((~ppeaka_6_6_ | ~n3810) & (~n3861 ^ ~n3924)); - assign n3725 = ~preset & n3825; - assign n3726_1 = (ppeaka_10_10_ & n3810 & (n3866 ^ ~n3926)) | ((~ppeaka_10_10_ | ~n3810) & (~n3866 ^ ~n3926)); - assign n3727 = ~\[17986] & ~preset & \[17635] ; - assign n3728 = (ppeaka_4_4_ & n3810 & (n3872 ^ ~n3929)) | ((~ppeaka_4_4_ | ~n3810) & (~n3872 ^ ~n3929)); - assign n3729 = ~preset & (\[18025] | ~n3798 | ~n3806); - assign n3730 = n3806 & n3798 & ~preset & ~\[18025] ; - assign n3731_1 = (ppeaka_9_9_ & n3810 & (n3864_1 ^ ~n3932)) | ((~ppeaka_9_9_ | ~n3810) & (~n3864_1 ^ ~n3932)); - assign n3732 = \[18025] & ~preset & ~\[17037] ; - assign n3733 = (ppeaka_3_3_ & n3810 & (n3850 ^ ~n3933_1)) | ((~ppeaka_3_3_ | ~n3810) & (~n3850 ^ ~n3933_1)); - assign n3734 = ~preset & (\[17206] | ~n3798 | ~n3808); - assign n3735 = n3808 & n3798 & ~preset & ~\[17206] ; - assign n3736_1 = ((n3870 ^ n3934) & (n3780 | ~n3944)) | (~n3780 & n3944 & (~n3870 ^ n3934)); - assign n3737 = (ppeaka_12_12_ & n3810 & (n3860_1 ^ ~n3935)) | ((~ppeaka_12_12_ | ~n3810) & (~n3860_1 ^ ~n3935)); - assign n3738 = ~preset & (\[17245] | ~n3798 | ~n3811); - assign n3739 = n3811 & n3798 & ~preset & ~\[17245] ; - assign n3740 = n3937 ? ((n3903_1 & n3920) | (n3885 & (n3903_1 | n3920))) : ((~n3903_1 & ~n3920) | (~n3885 & (~n3903_1 | ~n3920))); - assign n3741_1 = ((n5487 | n5488) & (~n3898_1 ^ n3938_1)) | (~n5487 & ~n5488 & (~n3898_1 ^ ~n3938_1)); - assign n3742 = (ppeaka_7_7_ & n3810 & (n3873 ^ ~n3925)) | ((~ppeaka_7_7_ | ~n3810) & (~n3873 ^ ~n3925)); - assign n3743 = (ppeaka_11_11_ & n3810 & (n3869_1 ^ ~n3927)) | ((~ppeaka_11_11_ | ~n3810) & (~n3869_1 ^ ~n3927)); - assign n3744 = (ppeaka_8_8_ & n3810 & (n3865 ^ ~n3939)) | ((~ppeaka_8_8_ | ~n3810) & (~n3865 ^ ~n3939)); - assign n3745 = (ppeaka_13_13_ & n3810 & (n3863 ^ ~n3936)) | ((~ppeaka_13_13_ | ~n3810) & (~n3863 ^ ~n3936)); - assign n3746_1 = (ppeaka_5_5_ & n3810 & (n3871 ^ ~n3928_1)) | ((~ppeaka_5_5_ | ~n3810) & (~n3871 ^ ~n3928_1)); - assign n3747 = ((n5493 | n5761) & (~n3884 ^ n3919)) | (~n5493 & ~n5761 & (~n3884 ^ ~n3919)); - assign n3748 = \[18077] & ~preset & ~\[17999] ; - assign n3749 = (~n5814 & ((~n3848 & n5811) | (~ppeaks_0_0_ & (n3848 | n5811)))) | (~n3848 & ~n5811 & n5814); - assign n3750_1 = n3827_1 & n3798 & ~preset & ~\[17180] ; - assign n3751 = ~preset & (\[17180] | ~n3798 | ~n3827_1); - assign n3752 = (ppeaka_14_14_ & n3810 & (n3867 ^ ~n3940)) | ((~ppeaka_14_14_ | ~n3810) & (~n3867 ^ ~n3940)); - assign n3753 = (ppeaka_2_2_ & n3810 & (n3849 ^ ~n3943_1)) | ((~ppeaka_2_2_ | ~n3810) & (~n3849 ^ ~n3943_1)); - assign n3754_1 = ~\[17505] & ~preset & \[17414] ; - assign n3755 = (ppeaki_10_10_ & n3883_1) | (ppeaki_14_14_ & n3796); - assign n3756 = ~preset & (\[18636] | (~n3798 & n5672)); - assign n3757 = \[18220] & ~preset & ~\[18142] ; - assign n3758_1 = (ppeaki_12_12_ & n3796) | (ppeaki_8_8_ & n3883_1); - assign n3759 = (ppeaki_13_13_ & n3796) | (ppeaki_9_9_ & n3883_1); - assign n3760 = ~\[17635] & ~preset & \[17570] ; - assign n3761 = ppeaki_13_13_ & n3883_1; - assign n3762 = ppeaki_12_12_ & n3883_1; - assign n3763_1 = ~preset & (\[17115] | ~n3798 | ~n3826); - assign n3764 = n3826 & n3798 & ~preset & ~\[17115] ; - assign n3765 = (ppeaki_11_11_ & n3883_1) | (ppeaki_15_15_ & n3796); - assign n3766 = (ppeaki_10_10_ & n3796) | (ppeaki_6_6_ & n3883_1); - assign n3767 = ~\[17648] & ~preset & \[17427] ; - assign n3768_1 = (ppeaki_7_7_ & n3883_1) | (ppeaki_11_11_ & n3796); - assign n3769 = ppeaki_15_15_ & n3883_1; - assign n3770 = (ppeaki_8_8_ & n3796) | (ppeaki_4_4_ & n3883_1); - assign n3771 = ppeaki_14_14_ & n3883_1; - assign n3772_1 = (ppeaki_9_9_ & n3796) | (ppeaki_5_5_ & n3883_1); - assign n3773 = ~preset & n3824 & (n6130 | n6131); - assign n3774 = ~preset & n3813 & (n6130 | n6131); - assign n3775 = ~preset & n3818 & (n6130 | n6131); - assign n3776 = ~preset & n3807_1 & (n6130 | n6131); - assign n3777_1 = ~preset & n3820 & (n6130 | n6131); - assign n3778 = ~preset & ~\[18389] ; - assign n3779 = ~preset & ~\[17102] ; - assign n3780 = \[17180] & ~\[17232] ; - assign n3781 = \[17206] & ~\[17271] ; - assign n3782_1 = ~preset & ~\[17700] ; - assign n3783 = \[18636] | (~n3798 & n5672); - assign n3784 = ~preset & ~\[18636] & (n3798 | ~n5672); - assign n3785 = \[18467] | (n3795 & ~n3804); - assign n3786 = n6193 | (n6190 & n6191 & n6192); - assign n3787_1 = n3798 & ~n3797_1 & ~\[18610] & n3796; - assign n3788 = ~pdn & (\[17024] ? \[18545] : preset_0_0_); - assign n3789 = (~\[17518] & \[17817] ) | (~\[17037] & \[18025] ); - assign n3790 = ~n5631 & (~n5677 | ~n5678) & n5679; - assign n3791 = n4160 | n4427 | n6133 | n6134; - assign n3792_1 = n5729 & n3814 & ~\[18168] & n3798; - assign n3793 = \[17999] & ~\[18220] ; - assign n3794 = \[18363] & ~\[18415] ; - assign n3795 = ~pdn & ((\[17024] & ~\[18545] ) | (~preset_0_0_ & (~\[17024] | ~\[18545] ))); - assign n3796 = ~n3881 & n3875 & ~n3829 & ~n3862; - assign n3797_1 = n5659 | n5660 | n5661 | n5662; - assign n3798 = n5671 | (~n3797_1 & (n5664 | n5668)); - assign n3799 = pdn & ~\[17089] ; - assign n3800 = ~n3881 & ~n3875 & n3829 & ~n3862; - assign n3801 = ~n3881 & n3875 & n3829 & n3862; - assign n3802_1 = n3881 & n3875 & n3829 & ~n3862; - assign n3803 = n3881 & ~n3875 & n3829 & n3862; - assign n3804 = \[18064] ? \[18129] : pirq_0_0_; - assign n3805 = \[17635] & ~\[17986] ; - assign n3806 = ~n3875 & ~n3829 & ~n3862 & n3881; - assign n3807_1 = ~\[17037] & \[18025] ; - assign n3808 = n3881 & n3875 & ~n3829 & ~n3862; - assign n3809 = n3808 & ~\[17206] & n3798; - assign n3810 = n3803 & ~\[16933] & n3798; - assign n3811 = n3881 & n3875 & n3829 & n3862; - assign n3812_1 = n3881 & ~n3875 & ~n3829 & n3862; - assign n3813 = n3801 & ~\[18506] & n3798; - assign n3814 = (n5680 & n5681) | (n3852_1 & n5682); - assign n3815 = (n5683 & n5684) | (n3852_1 & n5685); - assign n3816 = ~\[17570] & (\[18467] | (n3795 & ~n3804)); - assign n3817_1 = n3800 & ~\[18285] & n3798; - assign n3818 = ~\[17583] & \[17648] ; - assign n3819 = n3881 & ~n3875 & n3829 & ~n3862; - assign n3820 = n3802_1 & ~\[17284] & n3798; - assign n3821 = ~n3881 & ~n3875 & ~n3829 & n3862; - assign n3822_1 = n3826 & ~\[17115] & n3798; - assign n3823 = n3827_1 & ~\[17180] & n3798; - assign n3824 = ~\[17518] & \[17817] ; - assign n3825 = n3804 & n3795 & ~\[17817] & ~\[18467] ; - assign n3826 = ~n3881 & n3875 & n3829 & ~n3862; - assign n3827_1 = n3881 & n3875 & ~n3829 & n3862; - assign n3828 = ~n3881 & ~n3875 & n3829 & n3862; - assign n3829 = \[17531] ? \[18012] : ppeaki_2_2_; - assign n3830 = (n3845 & n5633) | (n3844 & n5634); - assign n3831 = (n3845 & n3847_1) | (n5635 & n5636); - assign n3832_1 = (n3852_1 & n5637) | (n3851 & n5638); - assign n3833 = (n3853 & n5640) | (n3847_1 & n5639); - assign n3834 = (n3846 & n5641) | (n3845 & n3854); - assign n3835 = (n3855 & n5642) | (n3851 & n5643); - assign n3836 = (n3853 & n5645) | (n3847_1 & n5644); - assign n3837_1 = (n3847_1 & n3855) | (n5646 & n5647); - assign n3838 = (n3854 & n5648) | (n3853 & n5649); - assign n3839 = (n3852_1 & n5650) | (n3851 & n5651); - assign n3840 = (n3854 & n5652) | (n3853 & n5653); - assign n3841 = (n3851 & n5655) | (n3845 & n5654); - assign n3842_1 = (n3854 & n3855) | (n3846 & n5656); - assign n3843 = (n3855 & n5657) | (n3844 & n5658); - assign n3844 = ~\[17609] & \[17674] ; - assign n3845 = ppeaki_4_4_ & ppeaki_5_5_; - assign n3846 = \[17544] & \[17752] ; - assign n3847_1 = ~\[17752] & ppeaki_6_6_ & ppeaki_7_7_; - assign n3848 = n3809 | n3822_1 | n3823 | n5791; - assign n3849 = n5806 | (ppeaks_2_2_ & n3848); - assign n3850 = n5803 | (ppeaks_3_3_ & n3848); - assign n3851 = \[17752] & ~\[17544] & \[17609] ; - assign n3852_1 = ~\[17752] & ~ppeaki_5_5_ & ~ppeaki_7_7_; - assign n3853 = \[17752] & \[17544] & ~\[17674] ; - assign n3854 = ~\[17752] & ~ppeaki_6_6_ & ppeaki_7_7_; - assign n3855 = ~ppeaki_4_4_ & ppeaki_5_5_; - assign n3856_1 = (pdn & ~\[17089] ) | (~\[17596] & n3790); - assign n3857 = n3856_1 | \[18636] | (~n3798 & n5672); - assign n3858 = n3818 | (~\[17284] & n3798 & n3802_1); - assign n3859 = n3789 | n3809 | n3822_1 | n3823; - assign n3860_1 = n5851 | (ppeaks_12_12_ & n3848); - assign n3861 = n5794 | (ppeaks_6_6_ & n3848); - assign n3862 = \[17531] ? \[18090] : ppeaki_3_3_; - assign n3863 = n5848 | (ppeaks_13_13_ & n3848); - assign n3864_1 = n5829 | (ppeaks_9_9_ & n3848); - assign n3865 = n5832 | (ppeaks_8_8_ & n3848); - assign n3866 = n5826 | (ppeaks_10_10_ & n3848); - assign n3867 = n5845 | (ppeaks_14_14_ & n3848); - assign n3868 = n5842 | (ppeaks_15_15_ & n3848); - assign n3869_1 = n5854 | (ppeaks_11_11_ & n3848); - assign n3870 = n5817 | (ppeaks_1_1_ & n3848); - assign n3871 = n5797 | (ppeaks_5_5_ & n3848); - assign n3872 = n5800 | (ppeaks_4_4_ & n3848); - assign n3873 = n5835 | (ppeaks_7_7_ & n3848); - assign n3874_1 = \[17024] ? \[18545] : preset_0_0_; - assign n3875 = \[17531] ? \[18155] : ppeaki_0_0_; - assign n3876 = ~n3881 & n3875 & ~n3829 & n3862; - assign n3877 = n5728 & n3798 & ~\[17752] & ~n3797_1; - assign n3878_1 = n5736 | n5735 | (~\[18103] & \[18168] ); - assign n3879 = (\[17037] & ~\[17102] ) | (\[17284] & ~\[18376] ); - assign n3880 = n5745 | (ppeaks_12_12_ & (n3878_1 | n5737)); - assign n3881 = \[17531] ? \[18233] : ppeaki_1_1_; - assign n3882 = n5786 | (ppeaks_15_15_ & (n3878_1 | n5737)); - assign n3883_1 = n3829 | (~n3829 & n3862) | (~n3829 & ~n3862 & n3881); - assign n3884 = n5759 | (ppeaks_3_3_ & (n3878_1 | n5737)); - assign n3885 = n5780 | (ppeaks_13_13_ & (n3878_1 | n5737)); - assign n3886 = n5772 | (ppeaks_8_8_ & (n3878_1 | n5737)); - assign n3887 = n5763 | (ppeaks_4_4_ & (n3878_1 | n5737)); - assign n3888_1 = n5757 | (ppeaks_2_2_ & (n3878_1 | n5737)); - assign n3889 = n5765 | (ppeaks_5_5_ & (n3878_1 | n5737)); - assign n3890 = n5770 | (ppeaks_7_7_ & (n3878_1 | n5737)); - assign n3891 = n5743 | (ppeaks_1_1_ & (n3878_1 | n5737)); - assign n3892 = n5782 | (ppeaks_14_14_ & (n3878_1 | n5737)); - assign n3893_1 = n3810 | n3820 | n3878_1 | n5739; - assign n3894 = n5741 | (ppeaks_0_0_ & (n3878_1 | n5737)); - assign n3895 = n5778 | (ppeaks_11_11_ & (n3878_1 | n5737)); - assign n3896 = n5774 | (ppeaks_9_9_ & (n3878_1 | n5737)); - assign n3897 = n5776 | (ppeaks_10_10_ & (n3878_1 | n5737)); - assign n3898_1 = n5767 | (ppeaks_6_6_ & (n3878_1 | n5737)); - assign n3899 = n5716 | n5717 | n5718 | n5719; - assign n3900 = (~n3878_1 & ~n3945 & ~n5737 & ~n5739) | (n3945 & (n3878_1 | n5737 | n5739)); - assign n3901 = (n3893_1 & ((n3894 & n3945) | (n3891 & (n3894 | n3945)))) | (n3891 & ~n3893_1 & ~n3945); - assign n3902 = n5755 | (~ppeaka_12_12_ & ~n5532 & ~n5533); - assign n3903_1 = (n3880 & n3902) | ((n3880 | n3902) & (n5483 | n5484)); - assign n3904 = n5535 | n5534 | (~ppeaka_11_11_ & ~n3952); - assign n3905 = (n3910 & n3911) | (n3897 & (n3910 | n3911)); - assign n3906 = n3895 | n5534 | n5535 | n5536; - assign n3907 = n5749 | (n3948_1 & ~n5541 & ~n5542); - assign n3908_1 = (n3912 & n3913_1) | (n3887 & (n3912 | n3913_1)); - assign n3909 = n5749 | n3889 | n5539; - assign n3910 = ~n3952 ^ (~n5537 & (n3941 | ~n5751)); - assign n3911 = (n3896 & n3917) | ((n3896 | n3917) & (n5485 | n5486)); - assign n3912 = ~n3947 ^ ((n3792_1 | n3900) & ~n5541); - assign n3913_1 = (n3884 & n3919) | ((n3884 | n3919) & (n5493 | n5761)); - assign n3914 = n5468 | n5784; - assign n3915 = (n3903_1 & n3920) | (n3885 & (n3903_1 | n3920)); - assign n3916 = (~n3882 & ~n5462 & ~n5463 & ~n5790) | (n3882 & (n5462 | n5463 | n5790)); - assign n3917 = n5519 | n5518 | (~n3792_1 & ~n3949); - assign n3918_1 = n5544 | n5543 | (~ppeaka_2_2_ & ~n3945); - assign n3919 = (n3901 & n3918_1) | (n3888_1 & (n3901 | n3918_1)); - assign n3920 = n3950 ^ (n5532 | n5533); - assign n3921 = ~n3949 ^ ~n3953_1; - assign n3922 = (n3898_1 & n3938_1) | ((n3898_1 | n3938_1) & (n5487 | n5488)); - assign n3923_1 = (n3890 & n3922) | ((n3890 | n3922) & (~n3949 ^ ~n3953_1)); - assign n3924 = (n3928_1 & n5822) | (n3871 & (n3928_1 | n5822)); - assign n3925 = (n3924 & n5823) | (n3861 & (n3924 | n5823)); - assign n3926 = (n3932 & n5838) | (n3864_1 & (n3932 | n5838)); - assign n3927 = (n3926 & n5839) | (n3866 & (n3926 | n5839)); - assign n3928_1 = (n3929 & n5821) | (n3872 & (n3929 | n5821)); - assign n3929 = (n3933_1 & n5820) | (n3850 & (n3933_1 | n5820)); - assign n3930 = n3868 ? ((~n3940 & ~n5858) | (~n3867 & (~n3940 | ~n5858))) : ((n3940 & n5858) | (n3867 & (n3940 | n5858))); - assign n3931 = ~ppeaka_15_15_ | \[16933] | ~n3798 | ~n3803; - assign n3932 = (n3939 & n5837) | (n3865 & (n3939 | n5837)); - assign n3933_1 = (n3943_1 & n5819) | (n3849 & (n3943_1 | n5819)); - assign n3934 = (~ppeaks_0_0_ & ~n5814) | (~n3848 & (~n5811 | ~n5814)); - assign n3935 = (n3927 & n5855) | (n3869_1 & (n3927 | n5855)); - assign n3936 = (n3935 & n5856) | (n3860_1 & (n3935 | n5856)); - assign n3937 = ~n3892 ^ (n5468 | n5784); - assign n3938_1 = ~n3949 & (~ppeaka_6_6_ | ~n3792_1 | n5768); - assign n3939 = (n3925 & n5836) | (n3873 & (n3925 | n5836)); - assign n3940 = (n3936 & n5857) | (n3863 & (n3936 | n5857)); - assign n3941 = (~ppeaka_8_8_ & (~n3949 | (ppeaka_7_7_ & n3792_1))) | (~n3792_1 & ~n3949) | (n3792_1 & n3949 & ~ppeaka_7_7_ & ppeaka_8_8_); - assign n3942 = n3886 | n3941; - assign n3943_1 = (n3944 & n5818 & ~n3780 & n3870) | ((n3780 | ~n3944) & (n3870 | (~n3870 & n5818))); - assign n3944 = ~ppeaka_1_1_ | \[16933] | ~n3798 | ~n3803; - assign n3945 = ~ppeaka_1_1_ | ~n3798 | ~n5729 | ~n5730; - assign n3946 = ~ppeaka_2_2_ | ~n3798 | ~n5729 | ~n5730; - assign n3947 = ~ppeaka_4_4_ | ~n3798 | ~n5729 | ~n5730; - assign n3948_1 = ~ppeaka_5_5_ | ~n3798 | ~n5729 | ~n5730; - assign n3949 = n5538 | (~n5539 & ~n5749 & n5750); - assign n3950 = ~ppeaka_13_13_ | ~n3798 | ~n5729 | ~n5730; - assign n3951 = n5537 | (~ppeaka_8_8_ & ~ppeaka_9_9_ & ~n3941); - assign n3952 = ~ppeaka_10_10_ | ~n3798 | ~n5729 | ~n5730; - assign n3953_1 = ~ppeaka_7_7_ | ~n3798 | ~n5729 | ~n5730; - assign n3954 = ~ppeaka_11_11_ | ~n3798 | ~n5729 | ~n5730; - assign n3955 = n3874_1 | (~n5631 & (~n5677 | ~n5678)); - assign n3956 = n3829 & n3881 & (~n3862 ^ n3875); - assign n3957_1 = n3875 & (n3829 ? (~n3862 & ~n3881) : (n3862 & n3881)); - assign n3958 = n3881 & (n3829 ? (~n3862 & n3875) : (n3862 & ~n3875)); - assign n3959 = n3829 & (n3862 ? (n3875 ^ ~n3881) : (~n3875 & n3881)); - assign n3960 = n3959 | (n3796 & n3843); - assign n3961 = ~n3829 & ~n3862 & n3881; - assign n3962_1 = (~n3829 & n3862 & ~n3875) | (n3875 & (n3829 ? (~n3862 & n3881) : (n3862 & ~n3881))); - assign n3963 = ~\[17089] & ~preset & pdn; - assign n3964 = (n3829 & ~n3875 & (~n3862 ^ n3881)) | (~n3829 & ~n3862 & n3875 & ~n3881); - assign n3965 = ~preset & n3816 & (n6130 | n6131); - assign n3966 = (~n3829 & n3881 & (~n3862 | (n3862 & n3875))) | (n3829 & ~n3862 & n3875 & ~n3881); - assign n3967_1 = (n3829 & ~n3862 & n3881) | (~n3829 & n3862 & ~n3881) | (n3862 & (n3829 ? (n3875 ^ ~n3881) : (~n3875 & n3881))); - assign n3968 = n5629 | (~preset & (~n3857 | n5630)); - assign n3969 = n3798 & ~preset & \[16920] ; - assign n3970 = n3798 & (n3981_1 | n6316 | n6317); - assign n3971 = \[8255] & n4081 & (n6130 | n6131); - assign n3972_1 = \[6065] & n4518 & (n6130 | n6131); - assign n3973 = \[9410] & n4509 & (n6130 | n6131); - assign n3974 = \[10970] & n4096 & (n6130 | n6131); - assign n3975 = ppeaks_7_7_ & n3791 & (n6130 | n6131); - assign n3976_1 = ~n6131 & ~n6130 & ~preset & paddress_7_7_; - assign n3977 = \[12905] & n4011 & (n6130 | n6131); - assign n3978 = n3965 & \[11075] & n3804; - assign n3979 = ppeaka_7_7_ & (n4187 | n4188); - assign n3980 = ppeakp_7_7_ & (n4189_1 | (~n3804 & n3965)); - assign n3981_1 = \[18610] & n3784; - assign n3982 = n6311 & n6191 & ~preset & n6190; - assign n3983 = \[7625] & n4081 & (n6130 | n6131); - assign n3984 = \[6740] & n4518 & (n6130 | n6131); - assign n3985 = \[7475] & n4509 & (n6130 | n6131); - assign n3986_1 = \[11690] & n4096 & (n6130 | n6131); - assign n3987 = ppeaks_6_6_ & n3791 & (n6130 | n6131); - assign n3988 = ~n6131 & ~n6130 & ~preset & paddress_6_6_; - assign n3989 = \[13865] & n4011 & (n6130 | n6131); - assign n3990 = n3965 & \[9950] & n3804; - assign n3991_1 = ppeaka_6_6_ & (n4187 | n4188); - assign n3992 = ppeakp_6_6_ & (n4189_1 | (~n3804 & n3965)); - assign n3993 = \[6995] & n4081 & (n6130 | n6131); - assign n3994 = \[4670] & n4518 & (n6130 | n6131); - assign n3995 = \[8105] & n4509 & (n6130 | n6131); - assign n3996_1 = \[11465] & n4096 & (n6130 | n6131); - assign n3997 = ppeaks_5_5_ & n3791 & (n6130 | n6131); - assign n3998 = ~n6131 & ~n6130 & ~preset & paddress_5_5_; - assign n3999 = \[13505] & n4011 & (n6130 | n6131); - assign n4000 = n3965 & \[10220] & n3804; - assign n4001_1 = ppeaka_5_5_ & (n4187 | n4188); - assign n4002 = ppeakp_5_5_ & (n4189_1 | (~n3804 & n3965)); - assign n4003 = \[12245] & n4081 & (n6130 | n6131); - assign n4004 = \[5375] & n4518 & (n6130 | n6131); - assign n4005 = \[6170] & n4509 & (n6130 | n6131); - assign n4006_1 = \[5615] & n4096 & (n6130 | n6131); - assign n4007 = ppeaks_4_4_ & n3791 & (n6130 | n6131); - assign n4008 = ~n6131 & ~n6130 & ~preset & paddress_4_4_; - assign n4009 = \[14675] & n4011 & (n6130 | n6131); - assign n4010 = n3965 & \[10505] & n3804; - assign n4011_1 = ppeaka_4_4_ & (n4187 | n4188); - assign n4012 = ppeakp_4_4_ & (n4189_1 | (~n3804 & n3965)); - assign n4013 = n6289 & n3804 & ~\[18467] & n3795; - assign n4014 = n4001 & (\[18467] | (n3795 & ~n3804)); - assign n4015 = \[12455] & n4081 & (n6130 | n6131); - assign n4016_1 = \[9995] & n4518 & (n6130 | n6131); - assign n4017 = \[6845] & n4509 & (n6130 | n6131); - assign n4018 = \[4910] & n4096 & (n6130 | n6131); - assign n4019 = ppeaks_3_3_ & n3791 & (n6130 | n6131); - assign n4020 = ~n6131 & ~n6130 & ~preset & paddress_3_3_; - assign n4021_1 = \[14255] & n4011 & (n6130 | n6131); - assign n4022 = n3965 & \[10790] & n3804; - assign n4023 = ppeaka_3_3_ & (n4187 | n4188); - assign n4024 = ppeakp_3_3_ & (n4189_1 | (~n3804 & n3965)); - assign n4025 = \[12680] & n4081 & (n6130 | n6131); - assign n4026_1 = \[9725] & n4518 & (n6130 | n6131); - assign n4027 = \[4760] & n4509 & (n6130 | n6131); - assign n4028 = \[6980] & n4096 & (n6130 | n6131); - assign n4029 = ppeaks_2_2_ & n3791 & (n6130 | n6131); - assign n4030 = ~n6131 & ~n6130 & ~preset & paddress_2_2_; - assign n4031_1 = \[15425] & n4011 & (n6130 | n6131); - assign n4032 = n3965 & \[11060] & n3804; - assign n4033 = ppeaka_2_2_ & (n4187 | n4188); - assign n4034 = ppeakp_2_2_ & (n4189_1 | (~n3804 & n3965)); - assign n4035 = ~n3859 & ~n3858 & ~preset & \[18337] ; - assign n4036_1 = n3858 & ~preset & ppeaka_0_0_; - assign n4037 = \[12920] & n4081 & (n6130 | n6131); - assign n4038 = \[9290] & n4518 & (n6130 | n6131); - assign n4039 = \[10310] & n4509 & (n6130 | n6131); - assign n4040 = \[6305] & n4096 & (n6130 | n6131); - assign n4041_1 = ppeaks_1_1_ & n3791 & (n6130 | n6131); - assign n4042 = ~n6131 & ~n6130 & ~preset & paddress_1_1_; - assign n4043 = \[12005] & n4011 & (n6130 | n6131); - assign n4044 = n3965 & \[11315] & n3804; - assign n4045 = ppeaka_1_1_ & (n4187 | n4188); - assign n4046_1 = ppeakp_1_1_ & (n4189_1 | (~n3804 & n3965)); - assign n4047 = ~preset & n3793 & (n6130 | n6131); - assign n4048 = ~\[18415] & ~preset & \[18285] ; - assign n4049 = \[17739] & ~preset & piack_0_0_; - assign n4050 = ~\[17700] & ~preset & piack_0_0_; - assign n4051_1 = \[13175] & n4081 & (n6130 | n6131); - assign n4052 = \[8630] & n4518 & (n6130 | n6131); - assign n4053 = \[10025] & n4509 & (n6130 | n6131); - assign n4054 = \[8240] & n4096 & (n6130 | n6131); - assign n4055 = ppeaks_0_0_ & n3791 & (n6130 | n6131); - assign n4056_1 = ~n6131 & ~n6130 & ~preset & paddress_0_0_; - assign n4057 = \[12890] & n4011 & (n6130 | n6131); - assign n4058 = n3965 & \[11555] & n3804; - assign n4059 = ppeaka_0_0_ & (n4187 | n4188); - assign n4060 = ppeakp_0_0_ & (n4189_1 | (~n3804 & n3965)); - assign n4061_1 = n4150 & (n6130 | n6131); - assign n4062 = ~preset & \[18233] & (\[17531] | ~n3798); - assign n4063 = n3798 & ~\[17531] & ~preset & ppeaki_1_1_; - assign n4064 = ~n3859 & ~n3858 & ~preset & \[18194] ; - assign n4065 = n3858 & ~preset & ppeaka_11_11_; - assign n4066_1 = ~preset & \[18155] & (\[17531] | ~n3798); - assign n4067 = n3798 & ~\[17531] & ~preset & ppeaki_0_0_; - assign n4068 = n6257 & (\[18467] | ~n3795 | (n3795 & ~n3804)); - assign n4069 = n3804 & n3795 & ~preset & ~\[18467] ; - assign n4070 = ~preset & \[18090] & (\[17531] | ~n3798); - assign n4071_1 = n3798 & ~\[17531] & ~preset & ppeaki_3_3_; - assign n4072 = n3804 & n3795 & n4001 & ~\[18467] ; - assign n4073 = ~preset & \[18012] & (\[17531] | ~n3798); - assign n4074 = n3798 & ~\[17531] & ~preset & ppeaki_2_2_; - assign n4075 = ~n3859 & ~n3858 & ~preset & \[17973] ; - assign n4076_1 = n3858 & ~preset & ppeaka_12_12_; - assign n4077 = ~n3859 & ~n3858 & ~preset & \[17921] ; - assign n4078 = n3858 & ~preset & ppeaka_10_10_; - assign n4079 = n3804 & n3795 & ~\[18467] & n3782_1; - assign n4080 = ~n3859 & ~n3858 & ~preset & \[17778] ; - assign n4081_1 = n3858 & ~preset & ppeaka_14_14_; - assign n4082 = ~n3859 & ~n3858 & ~preset & \[17765] ; - assign n4083 = n3858 & ~preset & ppeaka_9_9_; - assign n4084 = \[10985] & n4081 & (n6130 | n6131); - assign n4085 = \[6080] & n4518 & (n6130 | n6131); - assign n4086_1 = \[5480] & n4509 & (n6130 | n6131); - assign n4087 = \[12650] & n4096 & (n6130 | n6131); - assign n4088 = ppeaks_14_14_ & n3791 & (n6130 | n6131); - assign n4089 = ~n6131 & ~n6130 & ~preset & paddress_14_14_; - assign n4090 = \[14270] & n4011 & (n6130 | n6131); - assign n4091_1 = n3965 & \[12260] & n3804; - assign n4092 = ppeaka_14_14_ & (n4187 | n4188); - assign n4093 = ppeakp_14_14_ & (n4189_1 | (~n3804 & n3965)); - assign n4094 = \[6320] & n4081 & (n6130 | n6131); - assign n4095 = \[6755] & n4518 & (n6130 | n6131); - assign n4096_1 = \[8765] & n4509 & (n6130 | n6131); - assign n4097 = \[12425] & n4096 & (n6130 | n6131); - assign n4098 = ppeaks_15_15_ & n3791 & (n6130 | n6131); - assign n4099 = ~n6131 & ~n6130 & ~preset & paddress_15_15_; - assign n4100 = \[13880] & n4011 & (n6130 | n6131); - assign n4101_1 = n3965 & \[12470] & n3804; - assign n4102 = ppeaka_15_15_ & (n4187 | n4188); - assign n4103 = ppeakp_15_15_ & (n4189_1 | (~n3804 & n3965)); - assign n4104 = \[10415] & n4081 & (n6130 | n6131); - assign n4105 = \[10010] & n4518 & (n6130 | n6131); - assign n4106_1 = \[6860] & n4509 & (n6130 | n6131); - assign n4107 = \[14660] & n4096 & (n6130 | n6131); - assign n4108 = ppeaks_12_12_ & n3791 & (n6130 | n6131); - assign n4109 = ~n6131 & ~n6130 & ~preset & paddress_12_12_; - assign n4110 = \[15065] & n4011 & (n6130 | n6131); - assign n4111_1 = n3965 & \[12050] & n3804; - assign n4112 = ppeaka_12_12_ & (n4187 | n4188); - assign n4113 = ppeakp_12_12_ & (n4189_1 | (~n3804 & n3965)); - assign n4114 = n6194 & (~n6187 | ~n6188 | ~n6191); - assign n4115 = \[17986] & (n5631 | (n5677 & n5678)); - assign n4116_1 = \[10700] & n4081 & (n6130 | n6131); - assign n4117 = \[9740] & n4518 & (n6130 | n6131); - assign n4118 = \[4775] & n4509 & (n6130 | n6131); - assign n4119 = \[14240] & n4096 & (n6130 | n6131); - assign n4120 = ppeaks_13_13_ & n3791 & (n6130 | n6131); - assign n4121_1 = ~n6131 & ~n6130 & ~preset & paddress_13_13_; - assign n4122 = \[14690] & n4011 & (n6130 | n6131); - assign n4123 = n3965 & \[12170] & n3804; - assign n4124 = ppeaka_13_13_ & (n4187 | n4188); - assign n4125 = ppeakp_13_13_ & (n4189_1 | (~n3804 & n3965)); - assign n4126_1 = n3798 & ~preset & ~\[18636] ; - assign n4127 = ~n3859 & ~n3858 & ~preset & \[17492] ; - assign n4128 = n3858 & ~preset & ppeaka_13_13_; - assign n4129 = \[9860] & n4081 & (n6130 | n6131); - assign n4130 = \[9305] & n4518 & (n6130 | n6131); - assign n4131_1 = \[9770] & n4509 & (n6130 | n6131); - assign n4132 = \[13850] & n4096 & (n6130 | n6131); - assign n4133 = ppeaks_10_10_ & n3791 & (n6130 | n6131); - assign n4134 = ~n6131 & ~n6130 & ~preset & paddress_10_10_; - assign n4135 = \[12665] & n4011 & (n6130 | n6131); - assign n4136_1 = n3965 & \[11795] & n3804; - assign n4137 = ppeaka_10_10_ & (n4187 | n4188); - assign n4138 = ppeakp_10_10_ & (n4189_1 | (~n3804 & n3965)); - assign n4139 = \[10130] & n4081 & (n6130 | n6131); - assign n4140 = \[8645] & n4518 & (n6130 | n6131); - assign n4141_1 = \[10595] & n4509 & (n6130 | n6131); - assign n4142 = \[13490] & n4096 & (n6130 | n6131); - assign n4143 = ppeaks_11_11_ & n3791 & (n6130 | n6131); - assign n4144 = ~n6131 & ~n6130 & ~preset & paddress_11_11_; - assign n4145 = \[12125] & n4011 & (n6130 | n6131); - assign n4146_1 = n3965 & \[11915] & n3804; - assign n4147 = ppeaka_11_11_ & (n4187 | n4188); - assign n4148 = ppeakp_11_11_ & (n4189_1 | (~n3804 & n3965)); - assign n4149 = ~n3859 & ~n3858 & ~preset & \[17323] ; - assign n4150_1 = n3858 & ~preset & ppeaka_2_2_; - assign n4151 = ~n3859 & ~n3858 & ~preset & \[17258] ; - assign n4152 = n3858 & ~preset & ppeaka_1_1_; - assign n4153 = ~n3859 & ~n3858 & ~preset & \[17193] ; - assign n4154 = n3858 & ~preset & ppeaka_4_4_; - assign n4155_1 = ~n3859 & ~n3858 & ~preset & \[17128] ; - assign n4156 = n3858 & ~preset & ppeaka_3_3_; - assign n4157 = ~n3859 & ~n3858 & ~preset & \[17076] ; - assign n4158 = n3858 & ~preset & ppeaka_15_15_; - assign n4159 = ~n3859 & ~n3858 & ~preset & \[17063] ; - assign n4160_1 = n3858 & ~preset & ppeaka_6_6_; - assign n4161 = ~n3859 & ~n3858 & ~preset & \[16998] ; - assign n4162 = n3858 & ~preset & ppeaka_5_5_; - assign n4163 = ~n3859 & ~n3858 & ~preset & \[16959] ; - assign n4164 = n3858 & ~preset & ppeaka_8_8_; - assign n4165_1 = \[9590] & n4081 & (n6130 | n6131); - assign n4166 = \[7370] & n4518 & (n6130 | n6131); - assign n4167 = \[10040] & n4509 & (n6130 | n6131); - assign n4168 = \[15770] & n4096 & (n6130 | n6131); - assign n4169_1 = ppeaks_9_9_ & n3791 & (n6130 | n6131); - assign n4170 = ~n6131 & ~n6130 & ~preset & paddress_9_9_; - assign n4171 = \[12440] & n4011 & (n6130 | n6131); - assign n4172 = n3965 & \[11570] & n3804; - assign n4173 = ppeaka_9_9_ & (n4187 | n4188); - assign n4174_1 = ppeakp_9_9_ & (n4189_1 | (~n3804 & n3965)); - assign n4175 = ~n3859 & ~n3858 & ~preset & \[16907] ; - assign n4176 = n3858 & ~preset & ppeaka_7_7_; - assign n4177 = \[8915] & n4081 & (n6130 | n6131); - assign n4178 = \[8000] & n4518 & (n6130 | n6131); - assign n4179_1 = \[8750] & n4509 & (n6130 | n6131); - assign n4180 = \[11225] & n4096 & (n6130 | n6131); - assign n4181 = ppeaks_8_8_ & n3791 & (n6130 | n6131); - assign n4182 = ~n6131 & ~n6130 & ~preset & paddress_8_8_; - assign n4183 = \[13160] & n4011 & (n6130 | n6131); - assign n4184_1 = n3965 & \[11330] & n3804; - assign n4185 = ppeaka_8_8_ & (n4187 | n4188); - assign n4186 = ppeakp_8_8_ & (n4189_1 | (~n3804 & n3965)); - assign n4187 = ~preset & n3817_1 & (n6130 | n6131); - assign n4188 = n4056 & (n6130 | n6131); - assign n4189_1 = n4031 & (n6130 | n6131); - assign n4190 = ~preset & \[16085] & (~n3798 | ~n5732); - assign n4191 = ~preset & \[16070] & (~n3798 | ~n5731); - assign n4192 = ~preset & \[16055] & (\[18103] | ~\[18168] ); - assign n4193 = \[16025] & n3704; - assign n4194_1 = ~preset & \[16010] & (~n3798 | ~n5733); - assign n4195 = n5733 & n3798 & ~preset & pdata_9_9_; - assign n4196 = ~preset & \[15995] & (~n3798 | ~n5733); - assign n4197 = n5733 & n3798 & ~preset & pdata_0_0_; - assign n4198 = ~preset & \[15980] & (~n3798 | ~n5732); - assign n4199_1 = n5732 & n3798 & ~preset & pdata_7_7_; - assign n4200 = ~preset & \[15965] & (~n3798 | ~n5731); - assign n4201 = n5731 & n3798 & ~preset & pdata_14_14_; - assign n4202 = ~preset & \[15920] & (~\[17102] | \[17154] ); - assign n4203_1 = ~preset & \[15905] & (~\[17102] | \[17154] ); - assign n4204 = n3857 & n3827_1 & \[9860] & n3756; - assign n4205 = n3963 & n3874_1 & \[10205] & n3857; - assign n4206 = n3857 & n3826 & \[12665] & n3756; - assign n4207 = n3857 & n3808 & \[13850] & n3756; - assign n4208_1 = n3857 & n3806 & \[10400] & n3756; - assign n4209 = n3857 & n3812_1 & \[6155] & n3756; - assign n4210 = n3857 & n3801 & \[8135] & n3756; - assign n4211 = n3876 & n3857 & \[14585] & n3756; - assign n4212 = n3857 & n3821 & \[5450] & n3756; - assign n4213_1 = n3857 & n3802_1 & \[8060] & n3756; - assign n4214 = n3857 & n3803 & \[8810] & n3756; - assign n4215 = n3857 & \[12860] & n3702; - assign n4216 = n3857 & n3800 & \[4700] & n3756; - assign n4217 = ppeaks_10_10_ & (n5708 | n5709); - assign n4218_1 = n3801 & \[15665] & n3756; - assign n4219 = \[15860] & (n3968 | n5701 | n5702); - assign n4220 = \[13130] & n3804 & (n5627 | n5628); - assign n4221 = n3801 & \[9980] & n3756; - assign n4222 = \[15845] & (n3968 | n5701 | n5702); - assign n4223_1 = \[9500] & n3804 & (n5627 | n5628); - assign n4224 = n3843 & n3796 & ppeaka_6_6_ & n3756; - assign n4225 = n3957_1 & \[8330] & n3756; - assign n4226 = n3811 & \[5660] & n3756; - assign n4227_1 = n3962_1 & ppeakb_5_5_ & n3756; - assign n4228 = n3819 & \[6560] & n3756; - assign n4229 = n3808 & \[11465] & n3756; - assign n4230 = n3800 & \[15590] & n3756; - assign n4231 = n3814 & n3796 & \[14105] & n3756; - assign n4232_1 = n3803 & \[7670] & n3756; - assign n4233 = n3815 & n3796 & ~ppeaka_5_5_ & n3756; - assign n4234 = n3815 & n3796 & ~ppeakb_5_5_ & n3756; - assign n4235 = ppeakp_5_5_ & (n3702 | (n3756 & n3828)); - assign n4236 = n3806 & \[14825] & n3756; - assign n4237_1 = ppeaka_5_5_ & ((n3756 & n3801) | n3968); - assign n4238 = n3857 & n3811 & \[8315] & n3756; - assign n4239 = n3857 & n3819 & \[14435] & n3756; - assign n4240 = n3957_1 & n3857 & \[15140] & n3756; - assign n4241 = n3857 & n3808 & \[12650] & n3756; - assign n4242_1 = n3857 & n3806 & \[15575] & n3756; - assign n4243 = n3857 & n3803 & \[6335] & n3756; - assign n4244 = n3857 & n3800 & \[9080] & n3756; - assign n4245 = ppeaka_14_14_ & ((n3756 & n3801) | n3968); - assign n4246 = n3966 & n3857 & ppeaka_7_7_ & n3756; - assign n4247_1 = n3857 & n3812_1 & \[13340] & n3756; - assign n4248 = n3857 & n3801 & \[14930] & n3756; - assign n4249 = n3876 & n3857 & \[15980] & n3756; - assign n4250 = n3857 & n3821 & \[5915] & n3756; - assign n4251_1 = n3857 & n3802_1 & \[14450] & n3756; - assign n4252 = n3857 & n3803 & \[5315] & n3756; - assign n4253 = n3857 & \[7055] & n3702; - assign n4254 = n3857 & n3800 & \[9095] & n3756; - assign n4255 = ppeakb_7_7_ & ((n3756 & n3960) | n3968); - assign n4256_1 = ~preset & \[15785] & (~\[17791] | \[17843] ); - assign n4257 = ~preset & \[15725] & (~n3798 | ~n5731); - assign n4258 = ~preset & \[15710] & (\[18103] | ~\[18168] ); - assign n4259 = n3715 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); - assign n4260 = n4427 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); - assign n4261_1 = ~preset & \[15650] & (~n3798 | ~n5733); - assign n4262 = n5733 & n3798 & ~preset & pdata_1_1_; - assign n4263 = ~preset & \[15635] & (~n3798 | ~n5732); - assign n4264 = n5732 & n3798 & ~preset & pdata_6_6_; - assign n4265_1 = ~preset & \[15620] & (~n3798 | ~n5731); - assign n4266 = n5731 & n3798 & ~preset & pdata_15_15_; - assign n4267 = ~preset & \[15575] & (~\[17102] | \[17154] ); - assign n4268 = ~preset & \[15560] & (~\[17102] | \[17154] ); - assign n4269 = n3857 & n3827_1 & \[13175] & n3756; - assign n4270_1 = n3963 & n3874_1 & \[9935] & n3857; - assign n4271 = n3857 & n3826 & \[12890] & n3756; - assign n4272 = n3857 & n3808 & \[8240] & n3756; - assign n4273 = n3857 & n3806 & \[10670] & n3756; - assign n4274 = n3857 & n3812_1 & \[15380] & n3756; - assign n4275_1 = n3857 & n3801 & \[7490] & n3756; - assign n4276 = n3876 & n3857 & \[13400] & n3756; - assign n4277 = n3857 & n3821 & \[6125] & n3756; - assign n4278 = n3857 & n3802_1 & \[7415] & n3756; - assign n4279 = n3857 & n3803 & \[9455] & n3756; - assign n4280_1 = n3857 & \[12605] & n3702; - assign n4281 = n3857 & n3800 & \[5390] & n3756; - assign n4282 = ppeaks_0_0_ & (n5708 | n5709); - assign n4283 = n3801 & \[9710] & n3756; - assign n4284 = \[15515] & (n3968 | n5701 | n5702); - assign n4285_1 = \[13475] & n3804 & (n5627 | n5628); - assign n4286 = n3801 & \[15305] & n3756; - assign n4287 = \[15500] & (n3968 | n5701 | n5702); - assign n4288 = \[9800] & n3804 & (n5627 | n5628); - assign n4289 = n3843 & n3796 & ppeaka_5_5_ & n3756; - assign n4290_1 = n3957_1 & \[14765] & n3756; - assign n4291 = n3811 & \[8975] & n3756; - assign n4292 = n3962_1 & ppeakb_4_4_ & n3756; - assign n4293 = n3819 & \[14870] & n3756; - assign n4294 = n3808 & \[5615] & n3756; - assign n4295_1 = n3800 & \[13280] & n3756; - assign n4296 = n3814 & n3796 & \[14525] & n3756; - assign n4297 = n3803 & \[8300] & n3756; - assign n4298 = n3815 & n3796 & ~ppeaka_4_4_ & n3756; - assign n4299 = n3815 & n3796 & ~ppeakb_4_4_ & n3756; - assign n4300_1 = ppeakp_4_4_ & (n3702 | (n3756 & n3828)); - assign n4301 = n3806 & \[15905] & n3756; - assign n4302 = ppeaka_4_4_ & ((n3756 & n3801) | n3968); - assign n4303 = n3957_1 & \[13550] & n3756; - assign n4304_1 = n3811 & \[6365] & n3756; - assign n4305 = n3962_1 & ppeakb_15_15_ & n3756; - assign n4306 = n3819 & \[7205] & n3756; - assign n4307 = n3808 & \[12425] & n3756; - assign n4308 = n3800 & \[15950] & n3756; - assign n4309_1 = n3814 & n3796 & \[13730] & n3756; - assign n4310 = n3803 & \[7010] & n3756; - assign n4311 = n3815 & n3796 & ~ppeaka_15_15_ & n3756; - assign n4312 = n3815 & n3796 & ~ppeakb_15_15_ & n3756; - assign n4313 = ppeakp_15_15_ & (n3702 | (n3756 & n3828)); - assign n4314_1 = n3806 & \[15215] & n3756; - assign n4315 = ppeaka_15_15_ & ((n3756 & n3801) | n3968); - assign n4316 = n3966 & ppeaka_6_6_ & n3756; - assign n4317 = n3821 & \[7865] & n3756; - assign n4318 = n3802_1 & \[6575] & n3756; - assign n4319_1 = n3876 & \[15635] & n3756; - assign n4320 = n3800 & \[7160] & n3756; - assign n4321 = n3814 & n3796 & \[4385] & n3756; - assign n4322 = n3803 & \[4610] & n3756; - assign n4323 = n3815 & n3796 & \[7745] & n3756; - assign n4324_1 = n3801 & \[10265] & n3756; - assign n4325 = ppeakb_6_6_ & ((n3756 & n3960) | n3968); - assign n4326 = \[7685] & n3804 & (n5627 | n5628); - assign n4327 = ~preset & \[15440] & (~\[17791] | \[17843] ); - assign n4328_1 = ~preset & \[15410] & (~\[17427] | \[17648] ); - assign n4329 = ~preset & \[15395] & (~\[17427] | \[17648] ); - assign n4330 = ~preset & \[15380] & (~n3798 | ~n5733); - assign n4331 = ~preset & \[15365] & (~n3798 | ~n5732); - assign n4332 = n3962 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); - assign n4333_1 = ~preset & \[15350] & (\[18103] | ~\[18168] ); - assign n4334 = n4427 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); - assign n4335 = ~preset & \[15290] & (~n3798 | ~n5733); - assign n4336 = n5733 & n3798 & ~preset & pdata_2_2_; - assign n4337 = ~preset & \[15275] & (~n3798 | ~n5732); - assign n4338_1 = n5732 & n3798 & ~preset & pdata_9_9_; - assign n4339 = ~preset & \[15260] & (~n3798 | ~n5731); - assign n4340 = n5731 & n3798 & ~preset & pdata_12_12_; - assign n4341 = ~preset & \[15245] & (~\[17167] | \[17362] ); - assign n4342 = ~preset & \[15215] & (~\[17102] | \[17154] ); - assign n4343_1 = ~preset & \[15200] & (~\[17102] | \[17154] ); - assign n4344 = ppeaka_15_15_ & (n5577 | n5720); - assign n4345 = n3963 & \[11285] & n3874_1; - assign n4346 = ppeakp_15_15_ & (n5722 | n5723 | n5725); - assign n4347 = n3801 & ppeakb_15_15_ & n3756; - assign n4348_1 = n3857 & n3827_1 & \[8915] & n3756; - assign n4349 = n3963 & n3874_1 & \[10775] & n3857; - assign n4350 = n3857 & n3826 & \[13160] & n3756; - assign n4351 = n3857 & n3808 & \[11225] & n3756; - assign n4352 = n3857 & n3806 & \[7595] & n3756; - assign n4353_1 = n3857 & n3812_1 & \[12590] & n3756; - assign n4354 = n3857 & n3801 & \[9440] & n3756; - assign n4355 = n3876 & n3857 & \[15365] & n3756; - assign n4356 = n3857 & n3821 & \[6815] & n3756; - assign n4357 = n3857 & n3802_1 & \[10865] & n3756; - assign n4358_1 = n3857 & n3803 & \[7520] & n3756; - assign n4359 = n3857 & \[13460] & n3702; - assign n4360 = n3857 & n3800 & \[6095] & n3756; - assign n4361 = ppeaks_8_8_ & (n5708 | n5709); - assign n4362 = n3801 & \[5975] & n3756; - assign n4363_1 = \[15140] & (n3968 | n5701 | n5702); - assign n4364 = \[10070] & n3804 & (n5627 | n5628); - assign n4365 = n3843 & n3796 & ppeaka_4_4_ & n3756; - assign n4366 = n3957_1 & \[15860] & n3756; - assign n4367 = n3811 & \[9920] & n3756; - assign n4368_1 = n3962_1 & ppeakb_3_3_ & n3756; - assign n4369 = n3819 & \[15245] & n3756; - assign n4370 = n3808 & \[4910] & n3756; - assign n4371 = n3800 & \[13625] & n3756; - assign n4372 = n3814 & n3796 & \[13355] & n3756; - assign n4373_1 = n3803 & \[8960] & n3756; - assign n4374 = n3815 & n3796 & ~ppeaka_3_3_ & n3756; - assign n4375 = n3815 & n3796 & ~ppeakb_3_3_ & n3756; - assign n4376 = ppeakp_3_3_ & (n3702 | (n3756 & n3828)); - assign n4377 = n3806 & \[15560] & n3756; - assign n4378_1 = ppeaka_3_3_ & ((n3756 & n3801) | n3968); - assign n4379 = n3857 & n3811 & \[11510] & n3756; - assign n4380 = n3857 & n3819 & \[7190] & n3756; - assign n4381 = n3957_1 & n3857 & \[15845] & n3756; - assign n4382 = n3857 & n3808 & \[14660] & n3756; - assign n4383_1 = n3857 & n3806 & \[4415] & n3756; - assign n4384 = n3857 & n3803 & \[4940] & n3756; - assign n4385 = n3857 & n3800 & \[7775] & n3756; - assign n4386 = ppeaka_12_12_ & ((n3756 & n3801) | n3968); - assign n4387_1 = n3966 & ppeaka_9_9_ & n3756; - assign n4388 = n3821 & \[4520] & n3756; - assign n4389 = n3802_1 & \[7850] & n3756; - assign n4390 = n3876 & \[15275] & n3756; - assign n4391 = n3800 & \[14855] & n3756; - assign n4392_1 = n3814 & n3796 & \[15185] & n3756; - assign n4393 = n3803 & \[6680] & n3756; - assign n4394 = n3815 & n3796 & \[8390] & n3756; - assign n4395 = n3801 & \[5990] & n3756; - assign n4396 = ppeakb_9_9_ & ((n3756 & n3960) | n3968); - assign n4397_1 = \[5720] & n3804 & (n5627 | n5628); - assign n4398 = ~preset & \[15080] & (~\[17791] | \[17843] ); - assign n4399 = ~preset & \[15050] & (~\[17427] | \[17648] ); - assign n4400 = ~preset & \[15035] & (~\[17427] | \[17648] ); - assign n4401 = ~preset & \[15020] & (~n3798 | ~n5733); - assign n4402_1 = ~preset & \[15005] & (~n3798 | ~n5732); - assign n4403 = n3962 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); - assign n4404 = ~preset & \[14990] & (~n3798 | ~n5731); - assign n4405 = n4547 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); - assign n4406 = ~preset & \[14975] & (\[18103] | ~\[18168] ); - assign n4407_1 = n3715 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); - assign n4408 = n4427 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); - assign n4409 = ~preset & \[14915] & (~n3798 | ~n5733); - assign n4410 = n5733 & n3798 & ~preset & pdata_3_3_; - assign n4411 = ~preset & \[14900] & (~n3798 | ~n5732); - assign n4412_1 = n5732 & n3798 & ~preset & pdata_8_8_; - assign n4413 = ~preset & \[14885] & (~n3798 | ~n5731); - assign n4414 = n5731 & n3798 & ~preset & pdata_13_13_; - assign n4415 = ~preset & \[14870] & (~\[17167] | \[17362] ); - assign n4416 = ~preset & \[14825] & (~\[17102] | \[17154] ); - assign n4417_1 = ppeaka_14_14_ & (n5577 | n5720); - assign n4418 = n3963 & \[11525] & n3874_1; - assign n4419 = ppeakp_14_14_ & (n5722 | n5723 | n5725); - assign n4420 = n3801 & ppeakb_14_14_ & n3756; - assign n4421 = n3857 & n3827_1 & \[9590] & n3756; - assign n4422_1 = n3963 & n3874_1 & \[11045] & n3857; - assign n4423 = n3857 & n3826 & \[12440] & n3756; - assign n4424 = n3857 & n3808 & \[15770] & n3756; - assign n4425 = n3857 & n3806 & \[10685] & n3756; - assign n4426 = n3857 & n3812_1 & \[5465] & n3756; - assign n4427_1 = n3857 & n3801 & \[8780] & n3756; - assign n4428 = n3876 & n3857 & \[14165] & n3756; - assign n4429 = n3857 & n3821 & \[4745] & n3756; - assign n4430 = n3857 & n3802_1 & \[11135] & n3756; - assign n4431 = n3857 & n3803 & \[9470] & n3756; - assign n4432_1 = n3857 & \[13820] & n3702; - assign n4433 = n3857 & n3800 & \[5405] & n3756; - assign n4434 = ppeaks_9_9_ & (n5708 | n5709); - assign n4435 = n3801 & \[5270] & n3756; - assign n4436 = \[14765] & (n3968 | n5701 | n5702); - assign n4437_1 = \[12875] & n3804 & (n5627 | n5628); - assign n4438 = n3843 & n3796 & ppeaka_3_3_ & n3756; - assign n4439 = n3957_1 & \[15515] & n3756; - assign n4440 = n3811 & \[11720] & n3756; - assign n4441 = n3962_1 & ppeakb_2_2_ & n3756; - assign n4442_1 = n3819 & \[7805] & n3756; - assign n4443 = n3808 & \[6980] & n3756; - assign n4444 = n3800 & \[14000] & n3756; - assign n4445 = n3814 & n3796 & \[13715] & n3756; - assign n4446 = n3803 & \[9635] & n3756; - assign n4447_1 = n3815 & n3796 & ~ppeaka_2_2_ & n3756; - assign n4448 = n3815 & n3796 & ~ppeakb_2_2_ & n3756; - assign n4449 = ppeakp_2_2_ & (n3702 | (n3756 & n3828)); - assign n4450 = n3806 & \[5105] & n3756; - assign n4451 = ppeaka_2_2_ & ((n3756 & n3801) | n3968); - assign n4452_1 = n3857 & n3811 & \[10190] & n3756; - assign n4453 = n3962_1 & n3857 & ppeakb_13_13_ & n3756; - assign n4454 = n3857 & n3819 & \[14015] & n3756; - assign n4455 = n3957_1 & n3857 & \[15500] & n3756; - assign n4456 = n3857 & n3808 & \[14240] & n3756; - assign n4457_1 = n3857 & n3806 & \[15920] & n3756; - assign n4458 = n3857 & n3803 & \[5645] & n3756; - assign n4459 = n3857 & n3800 & \[8420] & n3756; - assign n4460 = ppeaka_13_13_ & ((n3756 & n3801) | n3968); - assign n4461 = n3966 & ppeaka_8_8_ & n3756; - assign n4462_1 = n3821 & \[6605] & n3756; - assign n4463 = n3802_1 & \[14030] & n3756; - assign n4464 = n3876 & \[14900] & n3756; - assign n4465 = n3800 & \[8435] & n3756; - assign n4466_1 = n3814 & n3796 & \[5810] & n3756; - assign n4467 = n3803 & \[6005] & n3756; - assign n4468 = n3815 & n3796 & \[9050] & n3756; - assign n4469 = n3801 & \[6665] & n3756; - assign n4470_1 = ppeakb_8_8_ & ((n3756 & n3960) | n3968); - assign n4471 = \[6410] & n3804 & (n5627 | n5628); - assign n4472 = ~preset & \[14705] & (~\[17791] | \[17843] ); - assign n4473 = ~preset & \[14630] & (~\[17427] | \[17648] ); - assign n4474 = ~n3825 & ~preset & \[14615] ; - assign n4475_1 = ~preset & \[14600] & (~n3798 | ~n5733); - assign n4476 = n4106 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); - assign n4477 = ~preset & \[14585] & (~n3798 | ~n5732); - assign n4478 = n3962 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); - assign n4479 = ~preset & \[14570] & (~n3798 | ~n5732); - assign n4480_1 = ~preset & \[14555] & (\[18103] | ~\[18168] ); - assign n4481 = n3715 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); - assign n4482 = n4427 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); - assign n4483 = n4427 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); - assign n4484 = ~preset & \[14510] & (\[17310] | ~\[17388] ); - assign n4485_1 = ~preset & \[14495] & (~n3798 | ~n5733); - assign n4486 = n5733 & n3798 & ~preset & pdata_4_4_; - assign n4487 = ~preset & \[14480] & (~n3798 | ~n5732); - assign n4488 = n5732 & n3798 & ~preset & pdata_11_11_; - assign n4489_1 = ~preset & \[14465] & (~n3798 | ~n5732); - assign n4490 = n5732 & n3798 & ~preset & pdata_2_2_; - assign n4491 = ~preset & \[14450] & (~\[17284] | \[18376] ); - assign n4492 = ~preset & \[14435] & (~\[17167] | \[17362] ); - assign n4493 = ~preset & \[14405] & (~\[17102] | \[17154] ); - assign n4494_1 = ~preset & \[14375] & (~\[17453] | \[18246] ); - assign n4495 = ~preset & \[14360] & (~\[17453] | \[18246] ); - assign n4496 = ppeaka_4_4_ & (n5577 | n5720); - assign n4497 = n3963 & \[15440] & n3874_1; - assign n4498 = ppeakp_4_4_ & (n5722 | n5723 | n5725); - assign n4499_1 = n3801 & ppeakb_4_4_ & n3756; - assign n4500 = n3843 & n3796 & ppeaka_2_2_ & n3756; - assign n4501 = n3957_1 & \[5030] & n3756; - assign n4502 = n3811 & \[11495] & n3756; - assign n4503 = n3962_1 & ppeakb_1_1_ & n3756; - assign n4504_1 = n3819 & \[7175] & n3756; - assign n4505 = n3808 & \[6305] & n3756; - assign n4506 = n3800 & \[14420] & n3756; - assign n4507 = n3814 & n3796 & \[15680] & n3756; - assign n4508 = n3803 & \[4925] & n3756; - assign n4509_1 = n3815 & n3796 & ~ppeaka_1_1_ & n3756; - assign n4510 = n3815 & n3796 & ~ppeakb_1_1_ & n3756; - assign n4511 = ppeakp_1_1_ & (n3702 | (n3756 & n3828)); - assign n4512 = n3806 & \[4400] & n3756; - assign n4513 = ppeaka_1_1_ & ((n3756 & n3801) | n3968); - assign n4514_1 = n3843 & n3796 & ppeaka_11_11_ & n3756; - assign n4515 = n3957_1 & \[5015] & n3756; - assign n4516 = n3811 & \[11015] & n3756; - assign n4517 = n3962_1 & ppeakb_10_10_ & n3756; - assign n4518_1 = n3819 & \[8465] & n3756; - assign n4519 = n3808 & \[13850] & n3756; - assign n4520 = n3800 & \[6515] & n3756; - assign n4521 = n3814 & n3796 & \[14960] & n3756; - assign n4522 = n3803 & \[11705] & n3756; - assign n4523_1 = n3815 & n3796 & ~ppeaka_10_10_ & n3756; - assign n4524 = n3815 & n3796 & ~ppeakb_10_10_ & n3756; - assign n4525 = ppeakp_10_10_ & (n3702 | (n3756 & n3828)); - assign n4526 = n3806 & \[13610] & n3756; - assign n4527 = ppeaka_10_10_ & ((n3756 & n3801) | n3968); - assign n4528_1 = n3966 & ppeaka_3_3_ & n3756; - assign n4529 = n3821 & \[8510] & n3756; - assign n4530 = n3802_1 & \[4490] & n3756; - assign n4531 = n3876 & \[14045] & n3756; - assign n4532 = n3800 & \[6530] & n3756; - assign n4533_1 = n3814 & n3796 & \[7760] & n3756; - assign n4534 = n3803 & \[7940] & n3756; - assign n4535 = n3815 & n3796 & \[13220] & n3756; - assign n4536 = n3801 & \[9215] & n3756; - assign n4537_1 = ppeakb_3_3_ & ((n3756 & n3960) | n3968); - assign n4538 = \[15860] & n3804 & (n5627 | n5628); - assign n4539 = ~preset & \[14285] & (~\[17791] | \[17843] ); - assign n4540 = ~preset & \[14225] & (\[17999] | ~\[18077] ); - assign n4541 = ~preset & \[14210] & (~\[17427] | \[17648] ); - assign n4542_1 = ~preset & \[14180] & (~n3798 | ~n5733); - assign n4543 = ~preset & \[14165] & (~n3798 | ~n5732); - assign n4544 = ~preset & \[14150] & (~n3798 | ~n5732); - assign n4545 = n3962 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); - assign n4546 = ~preset & \[14135] & (\[18103] | ~\[18168] ); - assign n4547_1 = n4427 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); - assign n4548 = ~preset & \[14090] & (\[17310] | ~\[17388] ); - assign n4549 = ~preset & \[14075] & (~n3798 | ~n5733); - assign n4550 = n5733 & n3798 & ~preset & pdata_5_5_; - assign n4551 = ~preset & \[14060] & (~n3798 | ~n5732); - assign n4552_1 = n5732 & n3798 & ~preset & pdata_10_10_; - assign n4553 = ~preset & \[14045] & (~n3798 | ~n5732); - assign n4554 = n5732 & n3798 & ~preset & pdata_3_3_; - assign n4555 = ~preset & \[14030] & (~\[17284] | \[18376] ); - assign n4556 = ~preset & \[14015] & (~\[17167] | \[17362] ); - assign n4557_1 = ~preset & \[13985] & (~\[17102] | \[17154] ); - assign n4558 = ~preset & \[13970] & (~\[17102] | \[17154] ); - assign n4559 = ~preset & \[13955] & (~\[17453] | \[18246] ); - assign n4560 = ppeaka_5_5_ & (n5577 | n5720); - assign n4561_1 = n3963 & \[15080] & n3874_1; - assign n4562 = ppeakp_5_5_ & (n5722 | n5723 | n5725); - assign n4563 = n3801 & ppeakb_5_5_ & n3756; - assign n4564 = n3843 & n3796 & ppeaka_1_1_ & n3756; - assign n4565_1 = n3957_1 & \[4310] & n3756; - assign n4566 = n3811 & \[11255] & n3756; - assign n4567 = n3962_1 & ppeakb_0_0_ & n3756; - assign n4568 = n3819 & \[9110] & n3756; - assign n4569 = n3808 & \[8240] & n3756; - assign n4570_1 = n3800 & \[14840] & n3756; - assign n4571 = n3814 & n3796 & \[16025] & n3756; - assign n4572 = n3803 & \[11480] & n3756; - assign n4573 = n3815 & n3796 & ~ppeaka_0_0_ & n3756; - assign n4574_1 = n3815 & n3796 & ~ppeakb_0_0_ & n3756; - assign n4575 = ppeakp_0_0_ & (n3702 | (n3756 & n3828)); - assign n4576 = n3806 & \[13970] & n3756; - assign n4577 = ppeaka_0_0_ & ((n3756 & n3801) | n3968); - assign n4578 = n3857 & n3811 & \[11735] & n3756; - assign n4579_1 = n3962_1 & n3857 & ppeakb_11_11_ & n3756; - assign n4580 = n3857 & n3819 & \[7820] & n3756; - assign n4581 = n3957_1 & n3857 & \[4295] & n3756; - assign n4582 = n3857 & n3808 & \[13490] & n3756; - assign n4583 = n3857 & n3806 & \[5120] & n3756; - assign n4584_1 = n3857 & n3803 & \[9650] & n3756; - assign n4585 = n3857 & n3800 & \[7145] & n3756; - assign n4586 = ppeaka_11_11_ & ((n3756 & n3801) | n3968); - assign n4587 = ~preset & \[13895] & (~\[17791] | \[17843] ); - assign n4588 = \[13880] & n3763_1; - assign n4589_1 = ~preset & \[13835] & (\[17999] | ~\[18077] ); - assign n4590 = ~preset & \[13820] & (~\[17427] | \[17648] ); - assign n4591 = ~preset & \[13790] & (~n3798 | ~n5733); - assign n4592 = n4106 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); - assign n4593 = ~preset & \[13775] & (~n3798 | ~n5732); - assign n4594_1 = ~preset & \[13745] & (\[18103] | ~\[18168] ); - assign n4595 = n3715 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); - assign n4596 = n4427 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); - assign n4597 = n4160 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); - assign n4598_1 = ~preset & \[13685] & (~n3798 | ~n5733); - assign n4599 = n5733 & n3798 & ~preset & pdata_6_6_; - assign n4600 = ~preset & \[13670] & (~n3798 | ~n5732); - assign n4601 = n5732 & n3798 & ~preset & pdata_13_13_; - assign n4602 = ~preset & \[13655] & (~n3798 | ~n5732); - assign n4603 = n5732 & n3798 & ~preset & pdata_0_0_; - assign n4604 = ~preset & \[13640] & (~n3798 | ~n5731); - assign n4605 = n5731 & n3798 & ~preset & pdata_2_2_; - assign n4606 = ~preset & \[13610] & (~\[17102] | \[17154] ); - assign n4607 = ~preset & \[13580] & (~\[17453] | \[18246] ); - assign n4608 = ppeaka_6_6_ & (n5577 | n5720); - assign n4609 = n3963 & \[14705] & n3874_1; - assign n4610 = ppeakp_6_6_ & (n5722 | n5723 | n5725); - assign n4611 = n3801 & ppeakb_6_6_ & n3756; - assign n4612 = n3801 & \[6650] & n3756; - assign n4613 = \[13550] & (n3968 | n5701 | n5702); - assign n4614 = \[10355] & n3804 & (n5627 | n5628); - assign n4615 = n3966 & n3857 & ppeaka_5_5_ & n3756; - assign n4616 = n3857 & n3812_1 & \[14075] & n3756; - assign n4617 = n3857 & n3801 & \[7910] & n3756; - assign n4618 = n3876 & n3857 & \[5240] & n3756; - assign n4619 = n3857 & n3821 & \[7235] & n3756; - assign n4620 = n3857 & n3802_1 & \[5885] & n3756; - assign n4621 = n3857 & n3803 & \[9245] & n3756; - assign n4622 = n3857 & \[8330] & n3702; - assign n4623 = n3857 & n3800 & \[7790] & n3756; - assign n4624 = ppeakb_5_5_ & ((n3756 & n3960) | n3968); - assign n4625 = ~preset & \[13475] & (\[17999] | ~\[18077] ); - assign n4626 = ~preset & \[13460] & (~\[17427] | \[17648] ); - assign n4627 = ~preset & \[13430] & (~n3798 | ~n5733); - assign n4628 = n4106 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); - assign n4629 = ~preset & \[13415] & (~n3798 | ~n5732); - assign n4630 = n3962 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); - assign n4631 = ~preset & \[13400] & (~n3798 | ~n5732); - assign n4632 = ~preset & \[13385] & (\[18103] | ~\[18168] ); - assign n4633 = n3715 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); - assign n4634 = ~preset & \[13340] & (~n3798 | ~n5733); - assign n4635 = n5733 & n3798 & ~preset & pdata_7_7_; - assign n4636 = ~preset & \[13325] & (~n3798 | ~n5732); - assign n4637 = n5732 & n3798 & ~preset & pdata_12_12_; - assign n4638 = ~preset & \[13310] & (~n3798 | ~n5732); - assign n4639 = n5732 & n3798 & ~preset & pdata_1_1_; - assign n4640 = ~preset & \[13295] & (~n3798 | ~n5731); - assign n4641 = n5731 & n3798 & ~preset & pdata_1_1_; - assign n4642 = ~preset & \[13265] & (~\[17102] | \[17154] ); - assign n4643 = ~preset & \[13235] & (~\[17453] | \[18246] ); - assign n4644 = ~preset & \[13220] & (~\[17453] | \[18246] ); - assign n4645 = n3857 & n3811 & \[11270] & n3756; - assign n4646 = n3857 & n3819 & \[9125] & n3756; - assign n4647 = n3957_1 & n3857 & \[5720] & n3756; - assign n4648 = n3857 & n3808 & \[15770] & n3756; - assign n4649 = n3857 & n3806 & \[13265] & n3756; - assign n4650 = n3857 & n3803 & \[9905] & n3756; - assign n4651 = n3857 & n3800 & \[5825] & n3756; - assign n4652 = ppeaka_9_9_ & ((n3756 & n3801) | n3968); - assign n4653 = n3966 & n3857 & ppeaka_4_4_ & n3756; - assign n4654 = n3857 & n3812_1 & \[14495] & n3756; - assign n4655 = n3857 & n3801 & \[7280] & n3756; - assign n4656 = n3876 & n3857 & \[12545] & n3756; - assign n4657 = n3857 & n3821 & \[9170] & n3756; - assign n4658 = n3857 & n3802_1 & \[5195] & n3756; - assign n4659 = n3857 & n3803 & \[8585] & n3756; - assign n4660 = n3857 & \[14765] & n3702; - assign n4661 = n3857 & n3800 & \[5840] & n3756; - assign n4662 = ppeakb_4_4_ & ((n3756 & n3960) | n3968); - assign n4663 = ~preset & \[13130] & (\[17999] | ~\[18077] ); - assign n4664 = ~preset & \[13115] & (~\[17427] | \[17648] ); - assign n4665 = ~preset & \[13100] & (~\[17427] | \[17648] ); - assign n4666 = ~preset & \[13085] & (~n3798 | ~n5733); - assign n4667 = ~preset & \[13070] & (~n3798 | ~n5732); - assign n4668 = ~preset & \[13055] & (~n3798 | ~n5732); - assign n4669 = n3962 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); - assign n4670 = ~preset & \[13040] & (\[18103] | ~\[18168] ); - assign n4671 = ~preset & \[13025] & (\[18103] | ~\[18168] ); - assign n4672 = ~preset & \[13010] & (~n3798 | ~n5733); - assign n4673 = n5733 & n3798 & ~preset & pdata_8_8_; - assign n4674 = ~preset & ppeaki_1_1_ & (~n3857 | n5630); - assign n4675 = \[10805] & (n5628 | (~n3955 & n3963)); - assign n4676 = ~preset & ppeaki_10_10_ & (~n3857 | n5630); - assign n4677 = \[12935] & (n5628 | (~n3955 & n3963)); - assign n4678 = ~preset & \[12935] & (~\[17570] | \[17635] ); - assign n4679 = ~preset & \[12875] & (\[17999] | ~\[18077] ); - assign n4680 = ~preset & \[12860] & (~\[17427] | \[17648] ); - assign n4681 = ~preset & \[12845] & (~\[17427] | \[17648] ); - assign n4682 = ~preset & \[12830] & (~n3798 | ~n5733); - assign n4683 = n4106 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); - assign n4684 = ~preset & \[12815] & (~n3798 | ~n5732); - assign n4685 = n3962 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); - assign n4686 = ~preset & \[12800] & (\[18103] | ~\[18168] ); - assign n4687 = n3715 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); - assign n4688 = ~preset & \[12770] & (~n3798 | ~n5732); - assign n4689 = n5732 & n3798 & ~preset & pdata_14_14_; - assign n4690 = ~preset & ppeaki_0_0_ & (~n3857 | n5630); - assign n4691 = \[12695] & (n5628 | (~n3955 & n3963)); - assign n4692 = ~preset & ppeaki_11_11_ & (~n3857 | n5630); - assign n4693 = \[11600] & (n5628 | (~n3955 & n3963)); - assign n4694 = ~preset & \[12695] & (~\[17570] | \[17635] ); - assign n4695 = ~preset & \[12635] & (\[17999] | ~\[18077] ); - assign n4696 = ~preset & \[12620] & (~\[17427] | \[17648] ); - assign n4697 = ~preset & \[12605] & (~\[17427] | \[17648] ); - assign n4698 = ~preset & \[12590] & (~n3798 | ~n5733); - assign n4699 = n4106 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); - assign n4700 = ~preset & \[12575] & (~n3798 | ~n5732); - assign n4701 = ~preset & \[12545] & (~n3798 | ~n5732); - assign n4702 = n5732 & n3798 & ~preset & pdata_4_4_; - assign n4703 = ~preset & ppeaki_3_3_ & (~n3857 | n5630); - assign n4704 = \[11345] & (n5628 | (~n3955 & n3963)); - assign n4705 = ~preset & ppeaki_12_12_ & (~n3857 | n5630); - assign n4706 = ~preset & \[12485] & (~\[17570] | \[17635] ); - assign n4707 = ~preset & \[12470] & (\[18142] | ~\[18220] ); - assign n4708 = \[12425] & n3734; - assign n4709 = ~preset & \[12410] & (\[17999] | ~\[18077] ); - assign n4710 = ~preset & \[12395] & (~\[17427] | \[17648] ); - assign n4711 = ~preset & \[12380] & (~\[17427] | \[17648] ); - assign n4712 = ~preset & \[12365] & (~n3798 | ~n5732); - assign n4713 = ~preset & \[12350] & (~n3798 | ~n5732); - assign n4714 = n3962 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); - assign n4715 = n4427 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); - assign n4716 = ~preset & ppeaki_2_2_ & (~n3857 | n5630); - assign n4717 = \[11585] & (n5628 | (~n3955 & n3963)); - assign n4718 = ~preset & ppeaki_13_13_ & (~n3857 | n5630); - assign n4719 = ~preset & \[12275] & (~\[17570] | \[17635] ); - assign n4720 = ~preset & \[12260] & (\[18142] | ~\[18220] ); - assign n4721 = n3966 & ppeaka_13_13_ & n3756; - assign n4722 = n3821 & \[14885] & n3756; - assign n4723 = n3802_1 & \[5210] & n3756; - assign n4724 = n3876 & \[13670] & n3756; - assign n4725 = n3800 & \[4460] & n3756; - assign n4726 = n3814 & n3796 & \[13595] & n3756; - assign n4727 = n3803 & \[7325] & n3756; - assign n4728 = n3815 & n3796 & \[14375] & n3756; - assign n4729 = n3801 & \[8570] & n3756; - assign n4730 = ppeakb_13_13_ & ((n3756 & n3960) | n3968); - assign n4731 = \[15500] & n3804 & (n5627 | n5628); - assign n4732 = ~preset & \[12200] & (~\[17570] | \[17635] ); - assign n4733 = ~preset & \[12185] & (~\[17570] | \[17635] ); - assign n4734 = ~preset & \[12170] & (\[18142] | ~\[18220] ); - assign n4735 = ~preset & \[12155] & (~\[17414] | \[17505] ); - assign n4736 = ~preset & \[12140] & (~\[17791] | \[17843] ); - assign n4737 = ~preset & ppeaki_7_7_ & (~n3857 | n5630); - assign n4738 = \[12065] & (n5628 | (~n3955 & n3963)); - assign n4739 = ~preset & \[12080] & (~\[17570] | \[17635] ); - assign n4740 = ~preset & \[12065] & (~\[17570] | \[17635] ); - assign n4741 = ~preset & \[12050] & (\[18142] | ~\[18220] ); - assign n4742 = ~preset & \[12035] & (~\[17414] | \[17505] ); - assign n4743 = ~preset & \[12020] & (~\[17791] | \[17843] ); - assign n4744 = n3966 & ppeaka_15_15_ & n3756; - assign n4745 = n3821 & \[15620] & n3756; - assign n4746 = n3802_1 & \[6590] & n3756; - assign n4747 = n3876 & \[4535] & n3756; - assign n4748 = n3800 & \[8450] & n3756; - assign n4749 = n3814 & n3796 & \[14390] & n3756; - assign n4750 = n3803 & \[8600] & n3756; - assign n4751 = n3815 & n3796 & \[13580] & n3756; - assign n4752 = n3801 & \[7295] & n3756; - assign n4753 = ppeakb_15_15_ & ((n3756 & n3960) | n3968); - assign n4754 = \[13550] & n3804 & (n5627 | n5628); - assign n4755 = ~preset & ppeaki_8_8_ & (~n3857 | n5630); - assign n4756 = \[12485] & (n5628 | (~n3955 & n3963)); - assign n4757 = ~preset & \[11930] & (~\[17570] | \[17635] ); - assign n4758 = ~preset & \[11915] & (\[18142] | ~\[18220] ); - assign n4759 = ~preset & \[11900] & (~\[17414] | \[17505] ); - assign n4760 = ~preset & \[11885] & (~\[17414] | \[17505] ); - assign n4761 = n3966 & n3857 & ppeaka_14_14_ & n3756; - assign n4762 = n3857 & n3812_1 & \[7250] & n3756; - assign n4763 = n3857 & n3801 & \[7925] & n3756; - assign n4764 = n3876 & n3857 & \[12770] & n3756; - assign n4765 = n3857 & n3821 & \[15965] & n3756; - assign n4766 = n3857 & n3802_1 & \[4505] & n3756; - assign n4767 = n3857 & n3803 & \[9260] & n3756; - assign n4768 = n3857 & \[15140] & n3702; - assign n4769 = n3857 & n3800 & \[5165] & n3756; - assign n4770 = ppeakb_14_14_ & ((n3756 & n3960) | n3968); - assign n4771 = ~preset & ppeaki_9_9_ & (~n3857 | n5630); - assign n4772 = \[12275] & (n5628 | (~n3955 & n3963)); - assign n4773 = ~preset & \[11810] & (~\[17570] | \[17635] ); - assign n4774 = ~preset & \[11795] & (\[18142] | ~\[18220] ); - assign n4775 = ~preset & \[11780] & (~\[17414] | \[17505] ); - assign n4776 = ~preset & \[11765] & (~\[17414] | \[17505] ); - assign n4777 = ~preset & \[11750] & (~\[17791] | \[17843] ); - assign n4778 = ~preset & \[11675] & (\[17037] | ~\[18025] ); - assign n4779 = ~preset & \[11660] & (\[17037] | ~\[18025] ); - assign n4780 = ~preset & \[11615] & (~n3798 | ~n5731); - assign n4781 = ~preset & \[11600] & (~\[17570] | \[17635] ); - assign n4782 = ~preset & \[11585] & (~\[17570] | \[17635] ); - assign n4783 = ~preset & \[11570] & (\[18142] | ~\[18220] ); - assign n4784 = ~preset & \[11555] & (\[18142] | ~\[18220] ); - assign n4785 = ~preset & \[11540] & (~\[17414] | \[17505] ); - assign n4786 = ~preset & \[11525] & (~\[17791] | \[17843] ); - assign n4787 = ~preset & \[11450] & (\[17037] | ~\[18025] ); - assign n4788 = ~preset & \[11435] & (\[17037] | ~\[18025] ); - assign n4789 = n3723 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); - assign n4790 = ~preset & \[11390] & (~n3798 | ~n5731); - assign n4791 = n4547 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); - assign n4792 = ~preset & \[11345] & (~\[17570] | \[17635] ); - assign n4793 = ~preset & \[11330] & (\[18142] | ~\[18220] ); - assign n4794 = ~preset & \[11315] & (\[18142] | ~\[18220] ); - assign n4795 = ~preset & \[11300] & (~\[17414] | \[17505] ); - assign n4796 = ~preset & \[11285] & (~\[17791] | \[17843] ); - assign n4797 = ~preset & \[11240] & (~\[17180] | \[17232] ); - assign n4798 = ~preset & \[11210] & (\[17037] | ~\[18025] ); - assign n4799 = ~preset & \[11195] & (\[17037] | ~\[18025] ); - assign n4800 = ~preset & \[11150] & (~n3798 | ~n5731); - assign n4801 = n4160 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); - assign n4802 = ~preset & \[11090] & (~\[17570] | \[17635] ); - assign n4803 = ~preset & \[11075] & (\[18142] | ~\[18220] ); - assign n4804 = ~preset & \[11060] & (\[18142] | ~\[18220] ); - assign n4805 = ~preset & \[11045] & (~\[17414] | \[17505] ); - assign n4806 = ~preset & \[11030] & (~\[17791] | \[17843] ); - assign n4807 = ~preset & \[10955] & (\[17037] | ~\[18025] ); - assign n4808 = ~preset & \[10940] & (\[17037] | ~\[18025] ); - assign n4809 = n3723 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); - assign n4810 = ~preset & \[10880] & (~n3798 | ~n5731); - assign n4811 = n4547 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); - assign n4812 = n3718 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); - assign n4813 = ~preset & \[10850] & (\[17310] | ~\[17388] ); - assign n4814 = ~preset & \[10820] & (~\[17570] | \[17635] ); - assign n4815 = ~preset & \[10805] & (~\[17570] | \[17635] ); - assign n4816 = ~preset & \[10790] & (\[18142] | ~\[18220] ); - assign n4817 = ~preset & \[10775] & (~\[17414] | \[17505] ); - assign n4818 = ~preset & \[10760] & (~\[17791] | \[17843] ); - assign n4819 = ~preset & \[10730] & (~\[17180] | \[17232] ); - assign n4820 = ~preset & \[10715] & (~\[17180] | \[17232] ); - assign n4821 = ~preset & \[10655] & (~\[17635] | \[17986] ); - assign n4822 = ~preset & \[10625] & (\[18311] | ~\[18506] ); - assign n4823 = ~preset & \[10610] & (\[18311] | ~\[18506] ); - assign n4824 = n3709 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); - assign n4825 = ~preset & \[10580] & (~\[18285] | \[18363] ); - assign n4826 = ~preset & \[10565] & (~\[18285] | \[18363] ); - assign n4827 = ~preset & \[10550] & (\[17310] | ~\[17388] ); - assign n4828 = ~preset & ppeaki_5_5_ & (~n3857 | n5630); - assign n4829 = \[11810] & (n5628 | (~n3955 & n3963)); - assign n4830 = ~preset & ppeaki_14_14_ & (~n3857 | n5630); - assign n4831 = ~preset & \[10505] & (\[18142] | ~\[18220] ); - assign n4832 = ~preset & \[10490] & (~\[17414] | \[17505] ); - assign n4833 = ~preset & \[10475] & (~\[17414] | \[17505] ); - assign n4834 = ~preset & \[10445] & (~\[17180] | \[17232] ); - assign n4835 = ~preset & \[10430] & (~\[17180] | \[17232] ); - assign n4836 = ~preset & \[10370] & (~\[17635] | \[17986] ); - assign n4837 = ~preset & \[10355] & (\[17999] | ~\[18077] ); - assign n4838 = n3721_1 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); - assign n4839 = ~preset & \[10340] & (\[18311] | ~\[18506] ); - assign n4840 = n3721_1 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); - assign n4841 = ~preset & \[10325] & (\[18311] | ~\[18506] ); - assign n4842 = ~preset & \[10280] & (~\[18285] | \[18363] ); - assign n4843 = n3716_1 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); - assign n4844 = ~preset & ppeaki_4_4_ & (~n3857 | n5630); - assign n4845 = \[11930] & (n5628 | (~n3955 & n3963)); - assign n4846 = ~preset & ppeaki_15_15_ & (~n3857 | n5630); - assign n4847 = ~preset & \[10220] & (\[18142] | ~\[18220] ); - assign n4848 = ~preset & \[10205] & (~\[17414] | \[17505] ); - assign n4849 = ~preset & \[10145] & (~\[17180] | \[17232] ); - assign n4850 = ~preset & \[10085] & (~\[17635] | \[17986] ); - assign n4851 = ~preset & \[10070] & (\[17999] | ~\[18077] ); - assign n4852 = ~preset & \[10055] & (\[18311] | ~\[18506] ); - assign n4853 = \[10025] & n3710; - assign n4854 = ~preset & \[9950] & (\[18142] | ~\[18220] ); - assign n4855 = ~preset & \[9935] & (~\[17414] | \[17505] ); - assign n4856 = ~preset & \[9890] & (~\[17180] | \[17232] ); - assign n4857 = ~preset & \[9875] & (~\[17180] | \[17232] ); - assign n4858 = ~preset & \[9815] & (~\[17635] | \[17986] ); - assign n4859 = ~preset & \[9800] & (\[17999] | ~\[18077] ); - assign n4860 = n3721_1 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); - assign n4861 = ~preset & \[9785] & (\[18311] | ~\[18506] ); - assign n4862 = n3709 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); - assign n4863 = n3706_1 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); - assign n4864 = n3706_1 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); - assign n4865 = ~preset & ppeaki_6_6_ & (~n3857 | n5630); - assign n4866 = \[12185] & (n5628 | (~n3955 & n3963)); - assign n4867 = ~preset & \[9680] & (~\[17414] | \[17505] ); - assign n4868 = ~preset & \[9665] & (~\[17414] | \[17505] ); - assign n4869 = ~preset & \[9620] & (~\[17180] | \[17232] ); - assign n4870 = ~preset & \[9605] & (~\[17180] | \[17232] ); - assign n4871 = ~preset & \[9575] & (\[17037] | ~\[18025] ); - assign n4872 = ~preset & \[9530] & (~\[17635] | \[17986] ); - assign n4873 = ~preset & \[9515] & (~\[17635] | \[17986] ); - assign n4874 = ~preset & \[9500] & (\[17999] | ~\[18077] ); - assign n4875 = \[9455] & n3722; - assign n4876 = n3721_1 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); - assign n4877 = ~preset & \[9440] & (\[18311] | ~\[18506] ); - assign n4878 = n3709 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); - assign n4879 = ~preset & \[9395] & (~n3798 | ~n5733); - assign n4880 = ~preset & \[9380] & (~n3798 | ~n5731); - assign n4881 = n4547 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); - assign n4882 = ~preset & \[9335] & (~\[18285] | \[18363] ); - assign n4883 = n3716_1 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); - assign n4884 = ~preset & \[9320] & (~\[18285] | \[18363] ); - assign n4885 = n3716_1 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); - assign n4886 = n3706_1 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); - assign n4887 = n4160 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); - assign n4888 = ~preset & \[9260] & (\[17310] | ~\[17388] ); - assign n4889 = ~preset & \[9245] & (\[17310] | ~\[17388] ); - assign n4890 = ~preset & \[9170] & (~n3798 | ~n5731); - assign n4891 = n5731 & n3798 & ~preset & pdata_4_4_; - assign n4892 = ~preset & \[9155] & (~\[17284] | \[18376] ); - assign n4893 = ~preset & \[9140] & (~\[17284] | \[18376] ); - assign n4894 = ~preset & \[9125] & (~\[17167] | \[17362] ); - assign n4895 = ~preset & \[9110] & (~\[17167] | \[17362] ); - assign n4896 = ~preset & \[9050] & (~\[17453] | \[18246] ); - assign n4897 = ppeaka_0_0_ & (n5577 | n5720); - assign n4898 = n3963 & \[5675] & n3874_1; - assign n4899 = ppeakp_0_0_ & (n5722 | n5723 | n5725); - assign n4900 = n3801 & ppeakb_0_0_ & n3756; - assign n4901 = ppeaka_9_9_ & (n5577 | n5720); - assign n4902 = n3963 & \[11750] & n3874_1; - assign n4903 = ppeakp_9_9_ & (n5722 | n5723 | n5725); - assign n4904 = n3801 & ppeakb_9_9_ & n3756; - assign n4905 = n3857 & n3827_1 & \[12680] & n3756; - assign n4906 = n3963 & n3874_1 & \[10475] & n3857; - assign n4907 = n3857 & n3826 & \[15425] & n3756; - assign n4908 = n3857 & n3808 & \[6980] & n3756; - assign n4909 = n3857 & n3806 & \[10100] & n3756; - assign n4910 = n3857 & n3812_1 & \[14600] & n3756; - assign n4911 = n3857 & n3801 & \[10325] & n3756; - assign n4912 = n3876 & n3857 & \[14150] & n3756; - assign n4913 = n3857 & n3821 & \[10880] & n3756; - assign n4914 = n3857 & n3802_1 & \[8690] & n3756; - assign n4915 = n3857 & n3803 & \[5510] & n3756; - assign n4916 = n3857 & \[13100] & n3702; - assign n4917 = n3857 & n3800 & \[9320] & n3756; - assign n4918 = ppeaks_2_2_ & (n5708 | n5709); - assign n4919 = n3857 & n3827_1 & \[10130] & n3756; - assign n4920 = n3963 & n3874_1 & \[10490] & n3857; - assign n4921 = n3857 & n3826 & \[12125] & n3756; - assign n4922 = n3857 & n3808 & \[13490] & n3756; - assign n4923 = n3857 & n3806 & \[10115] & n3756; - assign n4924 = n3857 & n3812_1 & \[6830] & n3756; - assign n4925 = n3857 & n3801 & \[7505] & n3756; - assign n4926 = n3876 & n3857 & \[13415] & n3756; - assign n4927 = n3857 & n3821 & \[11390] & n3756; - assign n4928 = n3857 & n3802_1 & \[7430] & n3756; - assign n4929 = n3857 & n3803 & \[5525] & n3756; - assign n4930 = n3857 & \[13115] & n3702; - assign n4931 = n3857 & n3800 & \[9335] & n3756; - assign n4932 = ppeaks_11_11_ & (n5708 | n5709); - assign n4933 = ~preset & \[8945] & (~\[17180] | \[17232] ); - assign n4934 = ~preset & \[8930] & (~\[17180] | \[17232] ); - assign n4935 = ~preset & \[8900] & (\[17037] | ~\[18025] ); - assign n4936 = ~preset & \[8855] & (~\[17635] | \[17986] ); - assign n4937 = ~preset & \[8840] & (~\[17635] | \[17986] ); - assign n4938 = ~preset & \[8825] & (\[17999] | ~\[18077] ); - assign n4939 = n3723 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); - assign n4940 = ~preset & \[8780] & (\[18311] | ~\[18506] ); - assign n4941 = n3709 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); - assign n4942 = ~preset & \[8735] & (~n3798 | ~n5733); - assign n4943 = ~preset & \[8720] & (~n3798 | ~n5731); - assign n4944 = n3718 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); - assign n4945 = n3718 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); - assign n4946 = ~preset & \[8675] & (~\[18285] | \[18363] ); - assign n4947 = ~preset & \[8660] & (~\[18285] | \[18363] ); - assign n4948 = n3706_1 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); - assign n4949 = \[8630] & n3707; - assign n4950 = ~preset & \[8600] & (\[17310] | ~\[17388] ); - assign n4951 = ~preset & \[8585] & (\[17310] | ~\[17388] ); - assign n4952 = ~preset & \[8510] & (~n3798 | ~n5731); - assign n4953 = n5731 & n3798 & ~preset & pdata_3_3_; - assign n4954 = ~preset & \[8495] & (~\[17284] | \[18376] ); - assign n4955 = ~preset & \[8480] & (~\[17284] | \[18376] ); - assign n4956 = ~preset & \[8465] & (~\[17167] | \[17362] ); - assign n4957 = ~preset & \[8390] & (~\[17453] | \[18246] ); - assign n4958 = ppeaka_1_1_ & (n5577 | n5720); - assign n4959 = n3963 & \[4970] & n3874_1; - assign n4960 = ppeakp_1_1_ & (n5722 | n5723 | n5725); - assign n4961 = n3801 & ppeakb_1_1_ & n3756; - assign n4962 = ppeaka_8_8_ & (n5577 | n5720); - assign n4963 = n3963 & \[13895] & n3874_1; - assign n4964 = ppeakp_8_8_ & (n5722 | n5723 | n5725); - assign n4965 = n3801 & ppeakb_8_8_ & n3756; - assign n4966 = n3857 & n3827_1 & \[12455] & n3756; - assign n4967 = n3963 & n3874_1 & \[12155] & n3857; - assign n4968 = n3857 & n3826 & \[14255] & n3756; - assign n4969 = n3857 & n3808 & \[4910] & n3756; - assign n4970 = n3857 & n3806 & \[5570] & n3756; - assign n4971 = n3857 & n3812_1 & \[14180] & n3756; - assign n4972 = n3857 & n3801 & \[10610] & n3756; - assign n4973 = n3876 & n3857 & \[12575] & n3756; - assign n4974 = n3857 & n3821 & \[8720] & n3756; - assign n4975 = n3857 & n3802_1 & \[9350] & n3756; - assign n4976 = n3857 & n3803 & \[6200] & n3756; - assign n4977 = n3857 & \[12845] & n3702; - assign n4978 = n3857 & n3800 & \[7385] & n3756; - assign n4979 = ppeaks_3_3_ & (n5708 | n5709); - assign n4980 = n3801 & \[4565] & n3756; - assign n4981 = \[8330] & (n3968 | n5701 | n5702); - assign n4982 = \[12635] & n3804 & (n5627 | n5628); - assign n4983 = ~preset & \[8285] & (~\[17180] | \[17232] ); - assign n4984 = ~preset & \[8210] & (~\[17635] | \[17986] ); - assign n4985 = ~preset & \[8195] & (~\[17635] | \[17986] ); - assign n4986 = ~preset & \[8180] & (\[17999] | ~\[18077] ); - assign n4987 = ~preset & \[8150] & (\[18311] | ~\[18506] ); - assign n4988 = n3721_1 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); - assign n4989 = ~preset & \[8135] & (\[18311] | ~\[18506] ); - assign n4990 = ~preset & \[8120] & (\[18311] | ~\[18506] ); - assign n4991 = n3709 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); - assign n4992 = ~preset & \[8090] & (~n3798 | ~n5733); - assign n4993 = n4106 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); - assign n4994 = ~preset & \[8075] & (~n3798 | ~n5731); - assign n4995 = n3718 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); - assign n4996 = ~preset & \[8030] & (~\[18285] | \[18363] ); - assign n4997 = n3716_1 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); - assign n4998 = ~preset & \[8015] & (~\[18285] | \[18363] ); - assign n4999 = n3716_1 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); - assign n5000 = n3706_1 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); - assign n5001 = ~preset & \[7955] & (\[17310] | ~\[17388] ); - assign n5002 = ~preset & \[7940] & (\[17310] | ~\[17388] ); - assign n5003 = ~preset & \[7880] & (~n3798 | ~n5733); - assign n5004 = n5733 & n3798 & ~preset & pdata_15_15_; - assign n5005 = ~preset & \[7865] & (~n3798 | ~n5731); - assign n5006 = n5731 & n3798 & ~preset & pdata_6_6_; - assign n5007 = ~preset & \[7850] & (~\[17284] | \[18376] ); - assign n5008 = ~preset & \[7835] & (~\[17284] | \[18376] ); - assign n5009 = ~preset & \[7820] & (~\[17167] | \[17362] ); - assign n5010 = ~preset & \[7805] & (~\[17167] | \[17362] ); - assign n5011 = ~preset & \[7745] & (~\[17453] | \[18246] ); - assign n5012 = ppeaka_2_2_ & (n5577 | n5720); - assign n5013 = n3963 & ndout & n3874_1; - assign n5014 = ppeakp_2_2_ & (n5722 | n5723 | n5725); - assign n5015 = n3801 & ppeakb_2_2_ & n3756; - assign n5016 = ppeaka_7_7_ & (n5577 | n5720); - assign n5017 = n3963 & \[14285] & n3874_1; - assign n5018 = ppeakp_7_7_ & (n5722 | n5723 | n5725); - assign n5019 = n3801 & ppeakb_7_7_ & n3756; - assign n5020 = n3857 & n3827_1 & \[10700] & n3756; - assign n5021 = n3963 & n3874_1 & \[12035] & n3857; - assign n5022 = n3857 & n3826 & \[14690] & n3756; - assign n5023 = n3857 & n3808 & \[14240] & n3756; - assign n5024 = n3857 & n3806 & \[8885] & n3756; - assign n5025 = n3857 & n3812_1 & \[8090] & n3756; - assign n5026 = n3857 & n3801 & \[10340] & n3756; - assign n5027 = n3876 & n3857 & \[12815] & n3756; - assign n5028 = n3857 & n3821 & \[14990] & n3756; - assign n5029 = n3857 & n3802_1 & \[8705] & n3756; - assign n5030 = n3857 & n3803 & \[6890] & n3756; - assign n5031 = n3857 & \[12620] & n3702; - assign n5032 = n3857 & n3800 & \[8030] & n3756; - assign n5033 = ppeaks_13_13_ & (n5708 | n5709); - assign n5034 = n3801 & \[6635] & n3756; - assign n5035 = \[7685] & (n3968 | n5701 | n5702); - assign n5036 = \[12410] & n3804 & (n5627 | n5628); - assign n5037 = ~preset & \[7655] & (~\[17180] | \[17232] ); - assign n5038 = ~preset & \[7640] & (~\[17180] | \[17232] ); - assign n5039 = ~preset & \[7580] & (~\[17635] | \[17986] ); - assign n5040 = ~preset & \[7565] & (~\[17635] | \[17986] ); - assign n5041 = ~preset & \[7550] & (\[17999] | ~\[18077] ); - assign n5042 = n3723 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); - assign n5043 = n3721_1 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); - assign n5044 = ~preset & \[7505] & (\[18311] | ~\[18506] ); - assign n5045 = ~preset & \[7490] & (\[18311] | ~\[18506] ); - assign n5046 = ~preset & \[7460] & (~n3798 | ~n5733); - assign n5047 = ~preset & \[7445] & (~n3798 | ~n5731); - assign n5048 = n4547 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); - assign n5049 = n3718 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); - assign n5050 = \[7415] & n3717; - assign n5051 = ~preset & \[7400] & (~\[18285] | \[18363] ); - assign n5052 = ~preset & \[7385] & (~\[18285] | \[18363] ); - assign n5053 = ~preset & \[7355] & (\[18103] | ~\[18168] ); - assign n5054 = n4160 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); - assign n5055 = ~preset & \[7325] & (\[17310] | ~\[17388] ); - assign n5056 = ~preset & \[7310] & (\[17310] | ~\[17388] ); - assign n5057 = ~preset & \[7250] & (~n3798 | ~n5733); - assign n5058 = n5733 & n3798 & ~preset & pdata_14_14_; - assign n5059 = ~preset & \[7235] & (~n3798 | ~n5731); - assign n5060 = n5731 & n3798 & ~preset & pdata_5_5_; - assign n5061 = ~preset & \[7220] & (~\[17284] | \[18376] ); - assign n5062 = ~preset & \[7205] & (~\[17167] | \[17362] ); - assign n5063 = ~preset & \[7190] & (~\[17167] | \[17362] ); - assign n5064 = ~preset & \[7175] & (~\[17167] | \[17362] ); - assign n5065 = ~preset & \[7115] & (~\[17453] | \[18246] ); - assign n5066 = ppeaka_3_3_ & (n5577 | n5720); - assign n5067 = n3963 & \[15785] & n3874_1; - assign n5068 = ppeakp_3_3_ & (n5722 | n5723 | n5725); - assign n5069 = n3801 & ppeakb_3_3_ & n3756; - assign n5070 = n3857 & n3827_1 & \[12920] & n3756; - assign n5071 = n3963 & n3874_1 & \[9665] & n3857; - assign n5072 = n3857 & n3826 & \[12005] & n3756; - assign n5073 = n3857 & n3808 & \[6305] & n3756; - assign n5074 = n3857 & n3806 & \[9830] & n3756; - assign n5075 = n3857 & n3812_1 & \[15020] & n3756; - assign n5076 = n3857 & n3801 & \[8120] & n3756; - assign n5077 = n3876 & n3857 & \[14570] & n3756; - assign n5078 = n3857 & n3821 & \[11150] & n3756; - assign n5079 = n3857 & n3802_1 & \[8045] & n3756; - assign n5080 = n3857 & n3803 & \[4805] & n3756; - assign n5081 = n3857 & \[12380] & n3702; - assign n5082 = n3857 & n3800 & \[8660] & n3756; - assign n5083 = ppeaks_1_1_ & (n5708 | n5709); - assign n5084 = n3857 & n3827_1 & \[10415] & n3756; - assign n5085 = n3963 & n3874_1 & \[9680] & n3857; - assign n5086 = n3857 & n3826 & \[15065] & n3756; - assign n5087 = n3857 & n3808 & \[14660] & n3756; - assign n5088 = n3857 & n3806 & \[9845] & n3756; - assign n5089 = n3857 & n3812_1 & \[7460] & n3756; - assign n5090 = n3857 & n3801 & \[10625] & n3756; - assign n5091 = n3876 & n3857 & \[13775] & n3756; - assign n5092 = n3857 & n3821 & \[11615] & n3756; - assign n5093 = n3857 & n3802_1 & \[9365] & n3756; - assign n5094 = n3857 & n3803 & \[4820] & n3756; - assign n5095 = n3857 & \[12395] & n3702; - assign n5096 = n3857 & n3800 & \[8675] & n3756; - assign n5097 = ppeaks_12_12_ & (n5708 | n5709); - assign n5098 = n3801 & \[5960] & n3756; - assign n5099 = \[7055] & (n3968 | n5701 | n5702); - assign n5100 = \[6245] & n3804 & (n5627 | n5628); - assign n5101 = \[7010] & n3722; - assign n5102 = ~preset & \[6965] & (\[17037] | ~\[18025] ); - assign n5103 = ~preset & \[6950] & (\[17037] | ~\[18025] ); - assign n5104 = ~preset & \[6935] & (~\[17635] | \[17986] ); - assign n5105 = ~preset & \[6920] & (\[17999] | ~\[18077] ); - assign n5106 = n3723 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); - assign n5107 = n3723 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); - assign n5108 = ~preset & \[6830] & (~n3798 | ~n5733); - assign n5109 = n4106 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); - assign n5110 = ~preset & \[6815] & (~n3798 | ~n5731); - assign n5111 = n4547 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); - assign n5112 = n3718 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); - assign n5113 = ~preset & \[6770] & (~\[18285] | \[18363] ); - assign n5114 = n3716_1 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); - assign n5115 = ~preset & \[6725] & (\[18103] | ~\[18168] ); - assign n5116 = n4160 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); - assign n5117 = n4160 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); - assign n5118 = ~preset & \[6680] & (\[17310] | ~\[17388] ); - assign n5119 = ~preset & \[6620] & (~n3798 | ~n5733); - assign n5120 = n5733 & n3798 & ~preset & pdata_13_13_; - assign n5121 = ~preset & \[6605] & (~n3798 | ~n5731); - assign n5122 = n5731 & n3798 & ~preset & pdata_8_8_; - assign n5123 = ~preset & \[6590] & (~\[17284] | \[18376] ); - assign n5124 = ~preset & \[6575] & (~\[17284] | \[18376] ); - assign n5125 = ~preset & \[6560] & (~\[17167] | \[17362] ); - assign n5126 = ~preset & \[6470] & (~\[17453] | \[18246] ); - assign n5127 = ppeaka_13_13_ & (n5577 | n5720); - assign n5128 = n3963 & \[10760] & n3874_1; - assign n5129 = ppeakp_13_13_ & (n5722 | n5723 | n5725); - assign n5130 = n3801 & ppeakb_13_13_ & n3756; - assign n5131 = n3857 & n3827_1 & \[7625] & n3756; - assign n5132 = n3963 & n3874_1 & \[11300] & n3857; - assign n5133 = n3857 & n3826 & \[13865] & n3756; - assign n5134 = n3857 & n3808 & \[11690] & n3756; - assign n5135 = n3857 & n3806 & \[8870] & n3756; - assign n5136 = n3857 & n3812_1 & \[13085] & n3756; - assign n5137 = n3857 & n3801 & \[5495] & n3756; - assign n5138 = n3876 & n3857 & \[16085] & n3756; - assign n5139 = n3857 & n3821 & \[8075] & n3756; - assign n5140 = n3857 & n3802_1 & \[6110] & n3756; - assign n5141 = n3857 & n3803 & \[11165] & n3756; - assign n5142 = n3857 & \[14210] & n3702; - assign n5143 = n3857 & n3800 & \[10565] & n3756; - assign n5144 = ppeaks_6_6_ & (n5708 | n5709); - assign n5145 = n3857 & n3827_1 & \[6320] & n3756; - assign n5146 = n3963 & n3874_1 & \[11780] & n3857; - assign n5147 = n3857 & n3826 & \[13880] & n3756; - assign n5148 = n3857 & n3808 & \[12425] & n3756; - assign n5149 = n3857 & n3806 & \[4880] & n3756; - assign n5150 = n3857 & n3812_1 & \[9395] & n3756; - assign n5151 = n3857 & n3801 & \[8150] & n3756; - assign n5152 = n3876 & n3857 & \[12365] & n3756; - assign n5153 = n3857 & n3821 & \[15725] & n3756; - assign n5154 = n3857 & n3802_1 & \[4730] & n3756; - assign n5155 = n3857 & n3803 & \[11180] & n3756; - assign n5156 = n3857 & \[15050] & n3702; - assign n5157 = n3857 & n3800 & \[10580] & n3756; - assign n5158 = ppeaks_15_15_ & (n5708 | n5709); - assign n5159 = n3801 & \[7895] & n3756; - assign n5160 = \[6410] & (n3968 | n5701 | n5702); - assign n5161 = \[6920] & n3804 & (n5627 | n5628); - assign n5162 = n3966 & n3857 & ppeaka_2_2_ & n3756; - assign n5163 = n3857 & n3812_1 & \[15290] & n3756; - assign n5164 = n3857 & n3801 & \[8555] & n3756; - assign n5165 = n3876 & n3857 & \[14465] & n3756; - assign n5166 = n3857 & n3821 & \[13640] & n3756; - assign n5167 = n3857 & n3802_1 & \[9140] & n3756; - assign n5168 = n3857 & n3803 & \[7310] & n3756; - assign n5169 = n3857 & \[15515] & n3702; - assign n5170 = n3857 & n3800 & \[4445] & n3756; - assign n5171 = ppeakb_2_2_ & ((n3756 & n3960) | n3968); - assign n5172 = n3966 & n3857 & ppeaka_11_11_ & n3756; - assign n5173 = n3857 & n3812_1 & \[5255] & n3756; - assign n5174 = n3857 & n3801 & \[4595] & n3756; - assign n5175 = n3876 & n3857 & \[14480] & n3756; - assign n5176 = n3857 & n3821 & \[5930] & n3756; - assign n5177 = n3857 & n3802_1 & \[9155] & n3756; - assign n5178 = n3857 & n3803 & \[14090] & n3756; - assign n5179 = n3857 & \[4295] & n3702; - assign n5180 = n3857 & n3800 & \[5855] & n3756; - assign n5181 = ppeakb_11_11_ & ((n3756 & n3960) | n3968); - assign n5182 = \[6365] & n3738; - assign n5183 = \[6320] & n3751; - assign n5184 = ~preset & \[6290] & (\[17037] | ~\[18025] ); - assign n5185 = ~preset & \[6275] & (\[17037] | ~\[18025] ); - assign n5186 = ~preset & \[6260] & (~\[17635] | \[17986] ); - assign n5187 = ~preset & \[6245] & (\[17999] | ~\[18077] ); - assign n5188 = n3721_1 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); - assign n5189 = ~preset & \[6185] & (\[18311] | ~\[18506] ); - assign n5190 = n3709 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); - assign n5191 = ~preset & \[6155] & (~n3798 | ~n5733); - assign n5192 = n4106 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); - assign n5193 = ~preset & \[6140] & (~n3798 | ~n5731); - assign n5194 = n4547 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); - assign n5195 = ~preset & \[6125] & (~n3798 | ~n5731); - assign n5196 = ~preset & \[6095] & (~\[18285] | \[18363] ); - assign n5197 = n3716_1 & (n3886 ? (n3923_1 ^ ~n3941) : (~n3923_1 ^ ~n3941)); - assign n5198 = n3706_1 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); - assign n5199 = ~preset & \[6050] & (\[18103] | ~\[18168] ); - assign n5200 = n3715 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); - assign n5201 = n4160 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); - assign n5202 = ~preset & \[6005] & (\[17310] | ~\[17388] ); - assign n5203 = ~preset & \[5945] & (~n3798 | ~n5733); - assign n5204 = n5733 & n3798 & ~preset & pdata_12_12_; - assign n5205 = ~preset & \[5930] & (~n3798 | ~n5731); - assign n5206 = n5731 & n3798 & ~preset & pdata_11_11_; - assign n5207 = ~preset & \[5915] & (~n3798 | ~n5731); - assign n5208 = n5731 & n3798 & ~preset & pdata_7_7_; - assign n5209 = ~preset & \[5900] & (~n3798 | ~n5731); - assign n5210 = n5731 & n3798 & ~preset & pdata_0_0_; - assign n5211 = ~preset & \[5885] & (~\[17284] | \[18376] ); - assign n5212 = ~preset & \[5870] & (~\[17167] | \[17362] ); - assign n5213 = ~preset & \[5780] & (~\[17453] | \[18246] ); - assign n5214 = ppeaka_12_12_ & (n5577 | n5720); - assign n5215 = n3963 & \[11030] & n3874_1; - assign n5216 = ppeakp_12_12_ & (n5722 | n5723 | n5725); - assign n5217 = n3801 & ppeakb_12_12_ & n3756; - assign n5218 = n3857 & n3827_1 & \[8255] & n3756; - assign n5219 = n3963 & n3874_1 & \[11540] & n3857; - assign n5220 = n3857 & n3826 & \[12905] & n3756; - assign n5221 = n3857 & n3808 & \[10970] & n3756; - assign n5222 = n3857 & n3806 & \[8225] & n3756; - assign n5223 = n3857 & n3812_1 & \[12830] & n3756; - assign n5224 = n3857 & n3801 & \[4790] & n3756; - assign n5225 = n3876 & n3857 & \[15005] & n3756; - assign n5226 = n3857 & n3821 & \[6140] & n3756; - assign n5227 = n3857 & n3802_1 & \[6785] & n3756; - assign n5228 = n3857 & n3803 & \[11405] & n3756; - assign n5229 = n3857 & \[14630] & n3702; - assign n5230 = n3857 & n3800 & \[6770] & n3756; - assign n5231 = ppeaks_7_7_ & (n5708 | n5709); - assign n5232 = n3857 & n3827_1 & \[10985] & n3756; - assign n5233 = n3963 & n3874_1 & \[11900] & n3857; - assign n5234 = n3857 & n3826 & \[14270] & n3756; - assign n5235 = n3857 & n3808 & \[12650] & n3756; - assign n5236 = n3857 & n3806 & \[9560] & n3756; - assign n5237 = n3857 & n3812_1 & \[8735] & n3756; - assign n5238 = n3857 & n3801 & \[10055] & n3756; - assign n5239 = n3876 & n3857 & \[13070] & n3756; - assign n5240 = n3857 & n3821 & \[16070] & n3756; - assign n5241 = n3857 & n3802_1 & \[5435] & n3756; - assign n5242 = n3857 & n3803 & \[6215] & n3756; - assign n5243 = n3857 & \[15410] & n3702; - assign n5244 = n3857 & n3800 & \[7400] & n3756; - assign n5245 = ppeaks_14_14_ & (n5708 | n5709); - assign n5246 = n3801 & \[7265] & n3756; - assign n5247 = \[5720] & (n3968 | n5701 | n5702); - assign n5248 = \[7550] & n3804 & (n5627 | n5628); - assign n5249 = n3857 & n3811 & \[6350] & n3756; - assign n5250 = n3857 & n3819 & \[4475] & n3756; - assign n5251 = n3957_1 & n3857 & \[6410] & n3756; - assign n5252 = n3857 & n3808 & \[11225] & n3756; - assign n5253 = n3857 & n3806 & \[14405] & n3756; - assign n5254 = n3857 & n3803 & \[10175] & n3756; - assign n5255 = n3857 & n3800 & \[5135] & n3756; - assign n5256 = ppeaka_8_8_ & ((n3756 & n3801) | n3968); - assign n5257 = n3966 & n3857 & ppeaka_10_10_ & n3756; - assign n5258 = n3857 & n3812_1 & \[4550] & n3756; - assign n5259 = n3857 & n3801 & \[5300] & n3756; - assign n5260 = n3876 & n3857 & \[14060] & n3756; - assign n5261 = n3857 & n3821 & \[5225] & n3756; - assign n5262 = n3857 & n3802_1 & \[7220] & n3756; - assign n5263 = n3857 & n3803 & \[10850] & n3756; - assign n5264 = n3857 & \[5015] & n3702; - assign n5265 = n3857 & n3800 & \[15230] & n3756; - assign n5266 = ppeakb_10_10_ & ((n3756 & n3960) | n3968); - assign n5267 = ~preset & \[5675] & (~\[17791] | \[17843] ); - assign n5268 = ~preset & \[5630] & (~\[17180] | \[17232] ); - assign n5269 = ~preset & \[5600] & (\[17037] | ~\[18025] ); - assign n5270 = ~preset & \[5555] & (~\[17635] | \[17986] ); - assign n5271 = n3723 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); - assign n5272 = n3723 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); - assign n5273 = ~preset & \[5495] & (\[18311] | ~\[18506] ); - assign n5274 = ~preset & \[5465] & (~n3798 | ~n5733); - assign n5275 = ~preset & \[5450] & (~n3798 | ~n5731); - assign n5276 = n4547 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); - assign n5277 = n3718 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); - assign n5278 = ~preset & \[5405] & (~\[18285] | \[18363] ); - assign n5279 = ~preset & \[5390] & (~\[18285] | \[18363] ); - assign n5280 = n3706_1 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); - assign n5281 = ~preset & \[5360] & (\[18103] | ~\[18168] ); - assign n5282 = n4160 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); - assign n5283 = \[5330] & n3713; - assign n5284 = ~preset & \[5315] & (\[17310] | ~\[17388] ); - assign n5285 = ~preset & \[5255] & (~n3798 | ~n5733); - assign n5286 = n5733 & n3798 & ~preset & pdata_11_11_; - assign n5287 = ~preset & \[5240] & (~n3798 | ~n5732); - assign n5288 = n5732 & n3798 & ~preset & pdata_5_5_; - assign n5289 = ~preset & \[5225] & (~n3798 | ~n5731); - assign n5290 = n5731 & n3798 & ~preset & pdata_10_10_; - assign n5291 = ~preset & \[5210] & (~\[17284] | \[18376] ); - assign n5292 = ~preset & \[5195] & (~\[17284] | \[18376] ); - assign n5293 = ~preset & \[5180] & (~\[17167] | \[17362] ); - assign n5294 = ~preset & \[5120] & (~\[17102] | \[17154] ); - assign n5295 = ~preset & \[5105] & (~\[17102] | \[17154] ); - assign n5296 = ~preset & \[5090] & (~\[17453] | \[18246] ); - assign n5297 = ~preset & \[5075] & (~\[17453] | \[18246] ); - assign n5298 = ppeaka_11_11_ & (n5577 | n5720); - assign n5299 = n3963 & \[12020] & n3874_1; - assign n5300 = ppeakp_11_11_ & (n5722 | n5723 | n5725); - assign n5301 = n3801 & ppeakb_11_11_ & n3756; - assign n5302 = n3857 & n3827_1 & \[12245] & n3756; - assign n5303 = n3963 & n3874_1 & \[11765] & n3857; - assign n5304 = n3857 & n3826 & \[14675] & n3756; - assign n5305 = n3857 & n3808 & \[5615] & n3756; - assign n5306 = n3857 & n3806 & \[4865] & n3756; - assign n5307 = n3857 & n3812_1 & \[13790] & n3756; - assign n5308 = n3857 & n3801 & \[9785] & n3756; - assign n5309 = n3876 & n3857 & \[12350] & n3756; - assign n5310 = n3857 & n3821 & \[9380] & n3756; - assign n5311 = n3857 & n3802_1 & \[4715] & n3756; - assign n5312 = n3857 & n3803 & \[6875] & n3756; - assign n5313 = n3857 & \[15035] & n3702; - assign n5314 = n3857 & n3800 & \[8015] & n3756; - assign n5315 = ppeaks_4_4_ & (n5708 | n5709); - assign n5316 = n3801 & \[9185] & n3756; - assign n5317 = \[5030] & (n3968 | n5701 | n5702); - assign n5318 = \[13835] & n3804 & (n5627 | n5628); - assign n5319 = n3801 & \[9200] & n3756; - assign n5320 = \[5015] & (n3968 | n5701 | n5702); - assign n5321 = \[8180] & n3804 & (n5627 | n5628); - assign n5322 = n3857 & n3811 & \[7025] & n3756; - assign n5323 = n3857 & n3819 & \[5180] & n3756; - assign n5324 = n3957_1 & n3857 & \[7055] & n3756; - assign n5325 = n3857 & n3808 & \[10970] & n3756; - assign n5326 = n3857 & n3806 & \[13985] & n3756; - assign n5327 = n3857 & n3803 & \[10460] & n3756; - assign n5328 = n3857 & n3800 & \[4430] & n3756; - assign n5329 = ppeaka_7_7_ & ((n3756 & n3801) | n3968); - assign n5330 = n3966 & n3857 & ppeaka_0_0_ & n3756; - assign n5331 = n3857 & n3812_1 & \[15995] & n3756; - assign n5332 = n3857 & n3801 & \[4580] & n3756; - assign n5333 = n3876 & n3857 & \[13655] & n3756; - assign n5334 = n3857 & n3821 & \[5900] & n3756; - assign n5335 = n3857 & n3802_1 & \[7835] & n3756; - assign n5336 = n3857 & n3803 & \[10550] & n3756; - assign n5337 = n3857 & \[4310] & n3702; - assign n5338 = n3857 & n3800 & \[15605] & n3756; - assign n5339 = ppeakb_0_0_ & ((n3756 & n3960) | n3968); - assign n5340 = ~preset & \[4970] & (~\[17791] | \[17843] ); - assign n5341 = ~preset & \[4895] & (\[17037] | ~\[18025] ); - assign n5342 = \[4880] & n3729; - assign n5343 = n3804 & ~\[17986] & \[11915] & \[17635] ; - assign n5344 = ppeakp_11_11_ & (n3807_1 | (~n3804 & n3805)); - assign n5345 = ~\[17648] & \[16100] & \[17427] ; - assign n5346 = ~\[17232] & \[10130] & \[17180] ; - assign n5347 = n3811 & n3798 & ppeaka_11_11_ & ~\[17245] ; - assign n5348 = \[18077] & \[13115] & ~\[17999] ; - assign n5349 = n3803 & n3798 & ppeakb_11_11_ & ~\[16933] ; - assign n5350 = n3804 & ~\[17986] & \[12050] & \[17635] ; - assign n5351 = ppeakp_12_12_ & (n3807_1 | (~n3804 & n3805)); - assign n5352 = ~\[17648] & \[15755] & \[17427] ; - assign n5353 = ~\[17232] & \[10415] & \[17180] ; - assign n5354 = n3811 & n3798 & ppeaka_12_12_ & ~\[17245] ; - assign n5355 = \[18077] & \[12395] & ~\[17999] ; - assign n5356 = n3803 & n3798 & ppeakb_12_12_ & ~\[16933] ; - assign n5357 = n3804 & ~\[17986] & \[12170] & \[17635] ; - assign n5358 = ppeakp_13_13_ & (n3807_1 | (~n3804 & n3805)); - assign n5359 = ~\[17648] & \[13805] & \[17427] ; - assign n5360 = ~\[17232] & \[10700] & \[17180] ; - assign n5361 = n3811 & n3798 & ppeaka_13_13_ & ~\[17245] ; - assign n5362 = \[18077] & \[12620] & ~\[17999] ; - assign n5363 = n3803 & n3798 & ppeakb_13_13_ & ~\[16933] ; - assign n5364 = n3804 & ~\[17986] & \[12260] & \[17635] ; - assign n5365 = ppeakp_14_14_ & (n3807_1 | (~n3804 & n3805)); - assign n5366 = ~\[17648] & \[13445] & \[17427] ; - assign n5367 = ~\[17232] & \[10985] & \[17180] ; - assign n5368 = n3811 & n3798 & ppeaka_14_14_ & ~\[17245] ; - assign n5369 = \[18077] & \[15410] & ~\[17999] ; - assign n5370 = n3803 & n3798 & ppeakb_14_14_ & ~\[16933] ; - assign n5371 = n3804 & ~\[17986] & \[12470] & \[17635] ; - assign n5372 = ppeakp_15_15_ & (n3807_1 | (~n3804 & n3805)); - assign n5373 = ~\[17648] & \[14615] & \[17427] ; - assign n5374 = ~\[17232] & \[6320] & \[17180] ; - assign n5375 = n3811 & n3798 & ppeaka_15_15_ & ~\[17245] ; - assign n5376 = \[18077] & \[15050] & ~\[17999] ; - assign n5377 = n3803 & n3798 & ppeakb_15_15_ & ~\[16933] ; - assign n5378 = ~preset & \[4850] & (~\[17635] | \[17986] ); - assign n5379 = n3804 & ~\[17986] & \[11075] & \[17635] ; - assign n5380 = ppeakp_7_7_ & (n3807_1 | (~n3804 & n3805)); - assign n5381 = ~\[17648] & \[5540] & \[17427] ; - assign n5382 = ~\[17232] & \[8255] & \[17180] ; - assign n5383 = n3811 & n3798 & ppeaka_7_7_ & ~\[17245] ; - assign n5384 = \[18077] & \[14630] & ~\[17999] ; - assign n5385 = n3803 & n3798 & ppeakb_7_7_ & ~\[16933] ; - assign n5386 = n3804 & ~\[17986] & \[11330] & \[17635] ; - assign n5387 = ppeakp_8_8_ & (n3807_1 | (~n3804 & n3805)); - assign n5388 = ~\[17648] & \[11420] & \[17427] ; - assign n5389 = ~\[17232] & \[8915] & \[17180] ; - assign n5390 = n3811 & n3798 & ppeaka_8_8_ & ~\[17245] ; - assign n5391 = \[18077] & \[13460] & ~\[17999] ; - assign n5392 = n3803 & n3798 & ppeakb_8_8_ & ~\[16933] ; - assign n5393 = n3804 & ~\[17986] & \[11570] & \[17635] ; - assign n5394 = ppeakp_9_9_ & (n3807_1 | (~n3804 & n3805)); - assign n5395 = ~\[17648] & \[11645] & \[17427] ; - assign n5396 = ~\[17232] & \[9590] & \[17180] ; - assign n5397 = n3811 & n3798 & ppeaka_9_9_ & ~\[17245] ; - assign n5398 = \[18077] & \[13820] & ~\[17999] ; - assign n5399 = n3803 & n3798 & ppeakb_9_9_ & ~\[16933] ; - assign n5400 = n3804 & ~\[17986] & \[11795] & \[17635] ; - assign n5401 = ppeakp_10_10_ & (n3807_1 | (~n3804 & n3805)); - assign n5402 = ~\[17648] & \[10925] & \[17427] ; - assign n5403 = ~\[17232] & \[9860] & \[17180] ; - assign n5404 = n3811 & n3798 & ppeaka_10_10_ & ~\[17245] ; - assign n5405 = \[18077] & \[12860] & ~\[17999] ; - assign n5406 = n3803 & n3798 & ppeakb_10_10_ & ~\[16933] ; - assign n5407 = n3803 & n3798 & ppeaka_0_0_ & ~\[16933] ; - assign n5408 = n3804 & ~\[17986] & \[11555] & \[17635] ; - assign n5409 = ppeakp_0_0_ & (n3807_1 | (~n3804 & n3805)); - assign n5410 = ~\[17648] & \[11630] & \[17427] ; - assign n5411 = ~\[17232] & \[13175] & \[17180] ; - assign n5412 = n3811 & n3798 & ppeaka_0_0_ & ~\[17245] ; - assign n5413 = \[18077] & \[12605] & ~\[17999] ; - assign n5414 = n3803 & n3798 & ppeakb_0_0_ & ~\[16933] ; - assign n5415 = n3804 & ~\[17986] & \[11315] & \[17635] ; - assign n5416 = ppeakp_1_1_ & (n3807_1 | (~n3804 & n3805)); - assign n5417 = ~\[17648] & \[9485] & \[17427] ; - assign n5418 = ~\[17232] & \[12920] & \[17180] ; - assign n5419 = n3811 & n3798 & ppeaka_1_1_ & ~\[17245] ; - assign n5420 = \[18077] & \[12380] & ~\[17999] ; - assign n5421 = n3803 & n3798 & ppeakb_1_1_ & ~\[16933] ; - assign n5422 = n3804 & ~\[17986] & \[11060] & \[17635] ; - assign n5423 = ppeakp_2_2_ & (n3807_1 | (~n3804 & n3805)); - assign n5424 = ~\[17648] & \[7535] & \[17427] ; - assign n5425 = ~\[17232] & \[12680] & \[17180] ; - assign n5426 = n3811 & n3798 & ppeaka_2_2_ & ~\[17245] ; - assign n5427 = \[18077] & \[13100] & ~\[17999] ; - assign n5428 = n3803 & n3798 & ppeakb_2_2_ & ~\[16933] ; - assign n5429 = n3804 & ~\[17986] & \[10790] & \[17635] ; - assign n5430 = ppeakp_3_3_ & (n3807_1 | (~n3804 & n3805)); - assign n5431 = ~\[17648] & \[8165] & \[17427] ; - assign n5432 = ~\[17232] & \[12455] & \[17180] ; - assign n5433 = n3811 & n3798 & ppeaka_3_3_ & ~\[17245] ; - assign n5434 = \[18077] & \[12845] & ~\[17999] ; - assign n5435 = n3803 & n3798 & ppeakb_3_3_ & ~\[16933] ; - assign n5436 = n3804 & ~\[17986] & \[10505] & \[17635] ; - assign n5437 = ppeakp_4_4_ & (n3807_1 | (~n3804 & n3805)); - assign n5438 = ~\[17648] & \[6230] & \[17427] ; - assign n5439 = ~\[17232] & \[12245] & \[17180] ; - assign n5440 = n3811 & n3798 & ppeaka_4_4_ & ~\[17245] ; - assign n5441 = \[18077] & \[15035] & ~\[17999] ; - assign n5442 = n3803 & n3798 & ppeakb_4_4_ & ~\[16933] ; - assign n5443 = n3804 & ~\[17986] & \[10220] & \[17635] ; - assign n5444 = ppeakp_5_5_ & (n3807_1 | (~n3804 & n3805)); - assign n5445 = ~\[17648] & \[6905] & \[17427] ; - assign n5446 = ~\[17232] & \[6995] & \[17180] ; - assign n5447 = n3811 & n3798 & ppeaka_5_5_ & ~\[17245] ; - assign n5448 = \[18077] & \[15395] & ~\[17999] ; - assign n5449 = n3803 & n3798 & ppeakb_5_5_ & ~\[16933] ; - assign n5450 = n3804 & ~\[17986] & \[9950] & \[17635] ; - assign n5451 = ppeakp_6_6_ & (n3807_1 | (~n3804 & n3805)); - assign n5452 = ~\[17648] & \[4835] & \[17427] ; - assign n5453 = ~\[17232] & \[7625] & \[17180] ; - assign n5454 = n3811 & n3798 & ppeaka_6_6_ & ~\[17245] ; - assign n5455 = \[18077] & \[14210] & ~\[17999] ; - assign n5456 = n3803 & n3798 & ppeakb_6_6_ & ~\[16933] ; - assign n5457 = n3721_1 & (n3890 ? (n3921 ^ ~n3922) : (~n3921 ^ ~n3922)); - assign n5458 = ~preset & \[4790] & (\[18311] | ~\[18506] ); - assign n5459 = n3709 & (n3885 ? (n3903_1 ^ ~n3920) : (~n3903_1 ^ ~n3920)); - assign n5460 = n3709 & (n3888_1 ? (n3901 ^ ~n3918_1) : (~n3901 ^ ~n3918_1)); - assign n5461 = ~preset & \[4745] & (~n3798 | ~n5731); - assign n5462 = n5788 & ~n5468 & ~n5784; - assign n5463 = ~ppeaka_15_15_ & (~n3950 | (~n5532 & ~n5533)); - assign n5464 = ~\[18363] & \[6755] & \[18285] ; - assign n5465 = n3800 & n3798 & ppeaka_15_15_ & ~\[18285] ; - assign n5466 = n5730 & n5729 & ppeakb_15_15_ & n3798; - assign n5467 = n3801 & n3798 & \[13550] & ~\[18506] ; - assign n5468 = ~ppeaka_14_14_ & (~n3950 | (~n5532 & ~n5533)); - assign n5469 = ~\[18363] & \[9740] & \[18285] ; - assign n5470 = n3800 & n3798 & ppeaka_13_13_ & ~\[18285] ; - assign n5471 = n5730 & n5729 & ppeakb_13_13_ & n3798; - assign n5472 = n3801 & n3798 & \[15500] & ~\[18506] ; - assign n5473 = ~\[18363] & \[6080] & \[18285] ; - assign n5474 = n3800 & n3798 & ppeaka_14_14_ & ~\[18285] ; - assign n5475 = n5730 & n5729 & ppeakb_14_14_ & n3798; - assign n5476 = n3801 & n3798 & \[15140] & ~\[18506] ; - assign n5477 = n3718 & (n3887 ? (n3912 ^ ~n3913_1) : (~n3912 ^ ~n3913_1)); - assign n5478 = ~preset & \[4700] & (~\[18285] | \[18363] ); - assign n5479 = n3716_1 & (n3897 ? (n3910 ^ ~n3911) : (~n3910 ^ ~n3911)); - assign n5480 = n3706_1 & (n3889 ? (n3907 ^ ~n3908_1) : (~n3907 ^ ~n3908_1)); - assign n5481 = ~preset & \[4655] & (\[18103] | ~\[18168] ); - assign n5482 = n3715 & (n3895 ? (n3904 ^ ~n3905) : (~n3904 ^ ~n3905)); - assign n5483 = n3906 & ((n3910 & n3911) | (n3897 & (n3910 | n3911))); - assign n5484 = n3895 & (n5534 | n5535 | n5536); - assign n5485 = n3942 & ((n3921 & n3922) | (n3890 & (n3921 | n3922))); - assign n5486 = n3886 & n3941; - assign n5487 = n3909 & ((n3912 & n3913_1) | (n3887 & (n3912 | n3913_1))); - assign n5488 = n3889 & (n5539 | n5749); - assign n5489 = ~\[18363] & \[9725] & \[18285] ; - assign n5490 = n3800 & n3798 & ppeaka_2_2_ & ~\[18285] ; - assign n5491 = n5730 & n5729 & ppeakb_2_2_ & n3798; - assign n5492 = n3801 & n3798 & \[15515] & ~\[18506] ; - assign n5493 = ~ppeaka_3_3_ & ~n5541 & (n3792_1 | n3900); - assign n5494 = ~\[18363] & \[9995] & \[18285] ; - assign n5495 = n3800 & n3798 & ppeaka_3_3_ & ~\[18285] ; - assign n5496 = n5730 & n5729 & ppeakb_3_3_ & n3798; - assign n5497 = n3801 & n3798 & \[15860] & ~\[18506] ; - assign n5498 = ~\[18363] & \[5375] & \[18285] ; - assign n5499 = n3800 & n3798 & ppeaka_4_4_ & ~\[18285] ; - assign n5500 = n5730 & n5729 & ppeakb_4_4_ & n3798; - assign n5501 = n3801 & n3798 & \[14765] & ~\[18506] ; - assign n5502 = ~\[18363] & \[4670] & \[18285] ; - assign n5503 = n3800 & n3798 & ppeaka_5_5_ & ~\[18285] ; - assign n5504 = n5730 & n5729 & ppeakb_5_5_ & n3798; - assign n5505 = n3801 & n3798 & \[8330] & ~\[18506] ; - assign n5506 = ~\[18363] & \[6740] & \[18285] ; - assign n5507 = n3800 & n3798 & ppeaka_6_6_ & ~\[18285] ; - assign n5508 = n5730 & n5729 & ppeakb_6_6_ & n3798; - assign n5509 = n3801 & n3798 & \[7685] & ~\[18506] ; - assign n5510 = ~\[18363] & \[6065] & \[18285] ; - assign n5511 = n3800 & n3798 & ppeaka_7_7_ & ~\[18285] ; - assign n5512 = n5730 & n5729 & ppeakb_7_7_ & n3798; - assign n5513 = n3801 & n3798 & \[7055] & ~\[18506] ; - assign n5514 = ~\[18363] & \[8000] & \[18285] ; - assign n5515 = n3800 & n3798 & ppeaka_8_8_ & ~\[18285] ; - assign n5516 = n5730 & n5729 & ppeakb_8_8_ & n3798; - assign n5517 = n3801 & n3798 & \[6410] & ~\[18506] ; - assign n5518 = ~n5537 & ~n3941 & ~ppeaka_8_8_ & ppeaka_9_9_; - assign n5519 = ~ppeaka_9_9_ & ~n5537 & (ppeaka_8_8_ | n3941); - assign n5520 = ~\[18363] & \[7370] & \[18285] ; - assign n5521 = n3800 & n3798 & ppeaka_9_9_ & ~\[18285] ; - assign n5522 = n5730 & n5729 & ppeakb_9_9_ & n3798; - assign n5523 = n3801 & n3798 & \[5720] & ~\[18506] ; - assign n5524 = ~\[18363] & \[9305] & \[18285] ; - assign n5525 = n3800 & n3798 & ppeaka_10_10_ & ~\[18285] ; - assign n5526 = n5730 & n5729 & ppeakb_10_10_ & n3798; - assign n5527 = n3801 & n3798 & \[5015] & ~\[18506] ; - assign n5528 = ~\[18363] & \[8645] & \[18285] ; - assign n5529 = n3800 & n3798 & ppeaka_11_11_ & ~\[18285] ; - assign n5530 = n5730 & n5729 & ppeakb_11_11_ & n3798; - assign n5531 = n3801 & n3798 & \[4295] & ~\[18506] ; - assign n5532 = ~n5536 & ~n5534 & ~n5535 & n5753; - assign n5533 = ~n3792_1 & (n3949 | (~n3941 & n5751)); - assign n5534 = n5752 & (n5537 | (~n3941 & n5751)); - assign n5535 = n3954 & ~n5537 & (n3941 | ~n5751); - assign n5536 = ~ppeaka_11_11_ & ~n3952; - assign n5537 = n3949 & (~n3798 | ~n5729 | ~n5730); - assign n5538 = ~n3792_1 & (~n3900 | n5541); - assign n5539 = n3948_1 & (n3792_1 | n3900) & ~n5541; - assign n5540 = ~ppeaka_5_5_ & ~n3947; - assign n5541 = ~n5545 & ~n5543 & ~n5544 & n5747; - assign n5542 = ~n3900 & (~n3798 | ~n5729 | ~n5730); - assign n5543 = ~n5739 & ~n3878_1 & ~n5737 & n5746; - assign n5544 = n3946 & (n3878_1 | n5737 | n5739); - assign n5545 = ~ppeaka_2_2_ & ~n3945; - assign n5546 = ~\[18363] & \[10010] & \[18285] ; - assign n5547 = n3800 & n3798 & ppeaka_12_12_ & ~\[18285] ; - assign n5548 = n5730 & n5729 & ppeakb_12_12_ & n3798; - assign n5549 = n3801 & n3798 & \[15845] & ~\[18506] ; - assign n5550 = n5730 & n5729 & ppeaka_0_0_ & n3798; - assign n5551 = ~\[18363] & \[8630] & \[18285] ; - assign n5552 = n3800 & n3798 & ppeaka_0_0_ & ~\[18285] ; - assign n5553 = n5730 & n5729 & ppeakb_0_0_ & n3798; - assign n5554 = n3801 & n3798 & \[4310] & ~\[18506] ; - assign n5555 = ~\[18363] & \[9290] & \[18285] ; - assign n5556 = n3800 & n3798 & ppeaka_1_1_ & ~\[18285] ; - assign n5557 = n5730 & n5729 & ppeakb_1_1_ & n3798; - assign n5558 = n3801 & n3798 & \[5030] & ~\[18506] ; - assign n5559 = ~preset & \[4610] & (\[17310] | ~\[17388] ); - assign n5560 = ~preset & \[4550] & (~n3798 | ~n5733); - assign n5561 = n5733 & n3798 & ~preset & pdata_10_10_; - assign n5562 = ~preset & \[4535] & (~n3798 | ~n5732); - assign n5563 = n5732 & n3798 & ~preset & pdata_15_15_; - assign n5564 = ~preset & \[4520] & (~n3798 | ~n5731); - assign n5565 = n5731 & n3798 & ~preset & pdata_9_9_; - assign n5566 = ~preset & \[4505] & (~\[17284] | \[18376] ); - assign n5567 = ~preset & \[4490] & (~\[17284] | \[18376] ); - assign n5568 = ~preset & \[4475] & (~\[17167] | \[17362] ); - assign n5569 = ~preset & \[4415] & (~\[17102] | \[17154] ); - assign n5570 = ~preset & \[4400] & (~\[17102] | \[17154] ); - assign n5571 = ~preset & \[4370] & (~\[17453] | \[18246] ); - assign n5572 = ~preset & \[4355] & (~\[17453] | \[18246] ); - assign n5573 = ppeaka_10_10_ & (n5577 | n5720); - assign n5574 = n3963 & \[12140] & n3874_1; - assign n5575 = ppeakp_10_10_ & (n5722 | n5723 | n5725); - assign n5576 = n3801 & ppeakb_10_10_ & n3756; - assign n5577 = n3899 & n3756 & n3876; - assign n5578 = ~n3899 & n3756 & n3876; - assign n5579 = n3857 & n3827_1 & \[6995] & n3756; - assign n5580 = n3963 & n3874_1 & \[11885] & n3857; - assign n5581 = n3857 & n3826 & \[13505] & n3756; - assign n5582 = n3857 & n3808 & \[11465] & n3756; - assign n5583 = n3857 & n3806 & \[9545] & n3756; - assign n5584 = n3857 & n3812_1 & \[13430] & n3756; - assign n5585 = n3857 & n3801 & \[6185] & n3756; - assign n5586 = n3876 & n3857 & \[13055] & n3756; - assign n5587 = n3857 & n3821 & \[7445] & n3756; - assign n5588 = n3857 & n3802_1 & \[5420] & n3756; - assign n5589 = n3857 & n3803 & \[10895] & n3756; - assign n5590 = n3857 & \[15395] & n3702; - assign n5591 = n3857 & n3800 & \[10280] & n3756; - assign n5592 = ppeaks_5_5_ & (n5708 | n5709); - assign n5593 = n3801 & \[8525] & n3756; - assign n5594 = \[4310] & (n3968 | n5701 | n5702); - assign n5595 = \[14225] & n3804 & (n5627 | n5628); - assign n5596 = n3801 & \[8540] & n3756; - assign n5597 = \[4295] & (n3968 | n5701 | n5702); - assign n5598 = \[8825] & n3804 & (n5627 | n5628); - assign n5599 = n3857 & n3811 & \[4955] & n3756; - assign n5600 = n3857 & n3819 & \[5870] & n3756; - assign n5601 = n3957_1 & n3857 & \[7685] & n3756; - assign n5602 = n3857 & n3808 & \[11690] & n3756; - assign n5603 = n3857 & n3806 & \[15200] & n3756; - assign n5604 = n3857 & n3803 & \[10745] & n3756; - assign n5605 = n3857 & n3800 & \[15935] & n3756; - assign n5606 = ppeaka_6_6_ & ((n3756 & n3801) | n3968); - assign n5607 = n3966 & n3857 & ppeaka_1_1_ & n3756; - assign n5608 = n3857 & n3812_1 & \[15650] & n3756; - assign n5609 = n3857 & n3801 & \[5285] & n3756; - assign n5610 = n3876 & n3857 & \[13310] & n3756; - assign n5611 = n3857 & n3821 & \[13295] & n3756; - assign n5612 = n3857 & n3802_1 & \[8480] & n3756; - assign n5613 = n3857 & n3803 & \[14510] & n3756; - assign n5614 = n3857 & \[5030] & n3702; - assign n5615 = n3857 & n3800 & \[5150] & n3756; - assign n5616 = ppeakb_1_1_ & ((n3756 & n3960) | n3968); - assign n5617 = n3966 & n3857 & ppeaka_12_12_ & n3756; - assign n5618 = n3857 & n3812_1 & \[5945] & n3756; - assign n5619 = n3857 & n3801 & \[9230] & n3756; - assign n5620 = n3876 & n3857 & \[13325] & n3756; - assign n5621 = n3857 & n3821 & \[15260] & n3756; - assign n5622 = n3857 & n3802_1 & \[8495] & n3756; - assign n5623 = n3857 & n3803 & \[7955] & n3756; - assign n5624 = n3857 & \[15845] & n3702; - assign n5625 = n3857 & n3800 & \[6545] & n3756; - assign n5626 = ppeakb_12_12_ & ((n3756 & n3960) | n3968); - assign n5627 = ~n3955 & ~\[17089] & ~preset & pdn; - assign n5628 = n3790 & ~preset & ~\[17596] ; - assign n5629 = n5686 & (n3799 | (~\[17596] & n3790)); - assign n5630 = n3955 & pdn & ~\[17089] ; - assign n5631 = ~\[17856] & \[18207] ; - assign n5632 = ~preset & ndout & (~\[17791] | \[17843] ); - assign n5633 = ~\[17752] & ~ppeaki_6_6_ & ~ppeaki_7_7_; - assign n5634 = \[17752] & ~\[17544] & \[17713] ; - assign n5635 = \[17674] & \[17609] ; - assign n5636 = \[17752] & \[17544] & \[17713] ; - assign n5637 = ppeaki_6_6_ & ~ppeaki_4_4_; - assign n5638 = ~\[17713] & ~\[17674] ; - assign n5639 = ~ppeaki_5_5_ & ppeaki_4_4_; - assign n5640 = \[17713] & \[17609] ; - assign n5641 = \[17713] & ~\[17609] & \[17674] ; - assign n5642 = ~\[17752] & ppeaki_6_6_ & ~ppeaki_7_7_; - assign n5643 = ~\[17713] & \[17674] ; - assign n5644 = ~ppeaki_5_5_ & ~ppeaki_4_4_; - assign n5645 = ~\[17713] & \[17609] ; - assign n5646 = \[17674] & \[17609] ; - assign n5647 = \[17752] & \[17544] & ~\[17713] ; - assign n5648 = ~ppeaki_5_5_ & ~ppeaki_4_4_; - assign n5649 = ~\[17713] & ~\[17609] ; - assign n5650 = ppeaki_6_6_ & ppeaki_4_4_; - assign n5651 = \[17713] & ~\[17674] ; - assign n5652 = ~ppeaki_5_5_ & ppeaki_4_4_; - assign n5653 = \[17713] & ~\[17609] ; - assign n5654 = ~\[17752] & ppeaki_6_6_ & ~ppeaki_7_7_; - assign n5655 = \[17713] & \[17674] ; - assign n5656 = ~\[17713] & ~\[17609] & \[17674] ; - assign n5657 = ~\[17752] & ~ppeaki_6_6_ & ~ppeaki_7_7_; - assign n5658 = \[17752] & ~\[17544] & ~\[17713] ; - assign n5659 = n3843 | n3842_1; - assign n5660 = n3830 | n3831 | n3832_1 | n3833; - assign n5661 = n3834 | n3835 | n3836 | n3837_1; - assign n5662 = n3838 | n3839 | n3840 | n3841; - assign n5663 = ~\[18636] & ~\[18597] & \[17596] & ~\[17661] ; - assign n5664 = ~n3828 & n5663 & (n3875 | n3881); - assign n5665 = ~\[18636] & ~\[18597] & \[17596] & ~\[17661] ; - assign n5666 = n5665 & (n3875 | n3881); - assign n5667 = ~\[18636] & ~\[18597] & \[17596] & ~\[17661] ; - assign n5668 = ~n3828 & n5667 & (n3829 | n3862); - assign n5669 = ~\[18636] & ~\[18597] & \[17596] & ~\[17661] ; - assign n5670 = n5669 & (n3829 | n3862); - assign n5671 = ~n3796 & ~n3828 & (n5666 | n5670); - assign n5672 = ~\[18597] & \[17596] & ~\[17661] ; - assign n5673 = ~\[18207] & ~\[10805] & ~\[10820] ; - assign n5674 = ~\[11585] & ~\[11090] & ~\[11345] & ~\[11600] ; - assign n5675 = ~\[12065] & ~\[11810] & ~\[11930] & ~\[12080] ; - assign n5676 = ~\[12275] & ~\[12185] & ~\[12200] & ~\[12485] ; - assign n5677 = n5675 & n5674; - assign n5678 = n5676 & n5673 & ~\[12695] & ~\[12935] ; - assign n5679 = \[17986] & ~\[17804] ; - assign n5680 = ~\[17674] & ~\[17609] ; - assign n5681 = \[17752] & ~\[17544] & \[17713] ; - assign n5682 = ~ppeaki_6_6_ & ppeaki_4_4_; - assign n5683 = ~\[17674] & ~\[17609] ; - assign n5684 = \[17752] & ~\[17544] & ~\[17713] ; - assign n5685 = ~ppeaki_6_6_ & ~ppeaki_4_4_; - assign n5686 = ~preset & ((\[18064] & ~\[18129] ) | (~pirq_0_0_ & (~\[18064] | ~\[18129] ))); - assign n5687 = n5625 | (\[15545] & n3698); - assign n5688 = n5617 | (\[6470] & n3697) | n5624; - assign n5689 = n5618 | n5619 | n5620 | n5621; - assign n5690 = n5622 | n5623 | n5626 | n5689; - assign n5691 = n5615 | (\[9065] & n3698); - assign n5692 = n5607 | (\[5075] & n3697) | n5614; - assign n5693 = n5608 | n5609 | n5610 | n5611; - assign n5694 = n5612 | n5613 | n5616 | n5693; - assign n5695 = n5605 | n5604; - assign n5696 = (ppeakp_6_6_ & n3699) | (ppeaka_7_7_ & n3700); - assign n5697 = (\[12560] & n3698) | (~ppeaka_6_6_ & n3697); - assign n5698 = n5599 | (ppeakb_6_6_ & n3701_1) | (~ppeakb_6_6_ & n3697); - assign n5699 = n5600 | n5601 | n5602 | n5603; - assign n5700 = n5606 | n5695 | n5696 | n5697; - assign n5701 = n3756 & (n3964 | n3967_1); - assign n5702 = n3756 & (n3826 | n3961); - assign n5703 = n5598 | (\[7655] & n3756 & n3827_1); - assign n5704 = n5595 | (\[7640] & n3756 & n3827_1); - assign n5705 = ~n3874_1 & ~\[17089] & ~preset & pdn; - assign n5706 = ~n5631 & (~n5677 | ~n5678) & n5705; - assign n5707 = ~n3804 & (n5628 | (~n3955 & n3963)); - assign n5708 = n3857 & (n5706 | n5707); - assign n5709 = ~preset & (n3783 ? n3960 : ~n3856_1); - assign n5710 = n5589 | n5588; - assign n5711 = n5591 | n5580 | n5590; - assign n5712 = (\[14555] & n3698) | (\[13700] & n3697); - assign n5713 = n5579 | n5581 | n5582 | n5583; - assign n5714 = n5584 | n5585 | n5586 | n5587; - assign n5715 = n5592 | n5710 | n5711 | n5712; - assign n5716 = ppeakb_7_7_ | ppeakb_14_14_ | ppeakb_10_10_ | ppeakb_8_8_; - assign n5717 = ppeakb_9_9_ | ppeakb_15_15_ | ppeakb_11_11_ | ppeakb_0_0_; - assign n5718 = ppeakb_1_1_ | ppeakb_12_12_ | ppeakb_2_2_ | ppeakb_3_3_; - assign n5719 = ppeakb_13_13_ | ppeakb_4_4_ | ppeakb_5_5_ | ppeakb_6_6_; - assign n5720 = n3756 & (n3821 | n3828); - assign n5721 = n3963 & (\[17024] ? ~\[18545] : ~preset_0_0_); - assign n5722 = (n3756 & n3808) | (n3955 & n5721); - assign n5723 = n3756 & (n3957_1 | n3964); - assign n5724 = n3756 & (n3956 | n3958); - assign n5725 = n5724 | n5578 | (~preset & ~n3857); - assign n5726 = n5574 | (\[4850] & (n5627 | n5628)); - assign n5727 = n5726 | (\[6965] & n3756 & n3806); - assign n5728 = n3796 & ~\[18610] ; - assign n5729 = ~n3797_1 & ~\[18610] & n3796; - assign n5730 = n3814 & ~\[18168] ; - assign n5731 = n3821 & ~\[18493] ; - assign n5732 = n3876 & ~\[16920] ; - assign n5733 = n3812_1 & ~\[17297] ; - assign n5734 = n3815 & ~\[17453] ; - assign n5735 = n3798 & (n5733 | (~\[16920] & n3876)); - assign n5736 = n3798 & (n5731 | (n5729 & n5734)); - assign n5737 = n3810 | (~\[17284] & n3798 & n3802_1); - assign n5738 = (\[18285] & ~\[18363] ) | (~\[18311] & \[18506] ); - assign n5739 = n3813 | n3817_1 | n5550 | n5738; - assign n5740 = n5551 | (\[10025] & ~\[18311] & \[18506] ); - assign n5741 = n5552 | n5553 | n5554 | n5740; - assign n5742 = n5555 | (\[10310] & ~\[18311] & \[18506] ); - assign n5743 = n5556 | n5557 | n5558 | n5742; - assign n5744 = n5546 | (\[6860] & ~\[18311] & \[18506] ); - assign n5745 = n5547 | n5548 | n5549 | n5744; - assign n5746 = ~n3946 & ~ppeaka_1_1_; - assign n5747 = ~ppeaka_3_3_ & ~ppeaka_2_2_; - assign n5748 = ~n3948_1 & ~ppeaka_4_4_; - assign n5749 = n5540 | (n5748 & (n5541 | n5542)); - assign n5750 = ~ppeaka_6_6_ & ~ppeaka_5_5_; - assign n5751 = ~ppeaka_9_9_ & ~ppeaka_8_8_; - assign n5752 = ~n3954 & ~ppeaka_10_10_; - assign n5753 = ~ppeaka_12_12_ & ~ppeaka_11_11_; - assign n5754 = ~ppeaka_11_11_ & n3951 & (~ppeaka_10_10_ | ~n3792_1); - assign n5755 = (~n3951 & (~n3792_1 | (~n5532 & n5754))) | (n3792_1 & ~n5532 & n5754); - assign n5756 = n5489 | (\[4760] & ~\[18311] & \[18506] ); - assign n5757 = n5490 | n5491 | n5492 | n5756; - assign n5758 = n5494 | (\[6845] & ~\[18311] & \[18506] ); - assign n5759 = n5495 | n5496 | n5497 | n5758; - assign n5760 = ~ppeaka_2_2_ & ~n3893_1 & (~ppeaka_1_1_ | ~n3792_1); - assign n5761 = ~n5541 & ((n3792_1 & n5760) | (n3900 & (~n3792_1 | n5760))); - assign n5762 = n5498 | (\[6170] & ~\[18311] & \[18506] ); - assign n5763 = n5499 | n5500 | n5501 | n5762; - assign n5764 = n5502 | (\[8105] & ~\[18311] & \[18506] ); - assign n5765 = n5503 | n5504 | n5505 | n5764; - assign n5766 = n5506 | (\[7475] & ~\[18311] & \[18506] ); - assign n5767 = n5507 | n5508 | n5509 | n5766; - assign n5768 = ~n5749 & ~ppeaka_5_5_ & ~n5539; - assign n5769 = n5510 | (\[9410] & ~\[18311] & \[18506] ); - assign n5770 = n5511 | n5512 | n5513 | n5769; - assign n5771 = n5514 | (\[8750] & ~\[18311] & \[18506] ); - assign n5772 = n5515 | n5516 | n5517 | n5771; - assign n5773 = n5520 | (\[10040] & ~\[18311] & \[18506] ); - assign n5774 = n5521 | n5522 | n5523 | n5773; - assign n5775 = n5524 | (\[9770] & ~\[18311] & \[18506] ); - assign n5776 = n5525 | n5526 | n5527 | n5775; - assign n5777 = n5528 | (\[10595] & ~\[18311] & \[18506] ); - assign n5778 = n5529 | n5530 | n5531 | n5777; - assign n5779 = n5469 | (\[4775] & ~\[18311] & \[18506] ); - assign n5780 = n5470 | n5471 | n5472 | n5779; - assign n5781 = n5473 | (\[5480] & ~\[18311] & \[18506] ); - assign n5782 = n5474 | n5475 | n5476 | n5781; - assign n5783 = ~ppeaka_13_13_ & ppeaka_14_14_; - assign n5784 = n3792_1 ? (n5532 & n5783) : (~n3951 & ~n5532); - assign n5785 = n5464 | (\[8765] & ~\[18311] & \[18506] ); - assign n5786 = n5465 | n5466 | n5467 | n5785; - assign n5787 = ppeaka_15_15_ & ~ppeaka_14_14_; - assign n5788 = n5787 & n5730 & n3798 & n5729; - assign n5789 = ~ppeaka_15_15_ & ppeaka_14_14_; - assign n5790 = n3792_1 ? n5789 : (~n3951 & ~n5532); - assign n5791 = n3825 | (~\[18025] & n3798 & n3806); - assign n5792 = n5455 | n5452 | n5453; - assign n5793 = n5792 | n5450 | n5451; - assign n5794 = n5793 | n5454 | n5456; - assign n5795 = n5448 | n5445 | n5446; - assign n5796 = n5795 | n5443 | n5444; - assign n5797 = n5796 | n5447 | n5449; - assign n5798 = n5441 | n5438 | n5439; - assign n5799 = n5798 | n5436 | n5437; - assign n5800 = n5799 | n5440 | n5442; - assign n5801 = n5434 | n5431 | n5432; - assign n5802 = n5801 | n5429 | n5430; - assign n5803 = n5802 | n5433 | n5435; - assign n5804 = n5427 | n5424 | n5425; - assign n5805 = n5804 | n5422 | n5423; - assign n5806 = n5805 | n5426 | n5428; - assign n5807 = (\[17635] & ~\[17986] ) | (~\[17037] & \[18025] ); - assign n5808 = (\[17427] & ~\[17648] ) | (~\[17999] & \[18077] ); - assign n5809 = n5808 | n5807; - assign n5810 = n5809 | (~\[17245] & n3798 & n3811); - assign n5811 = n5810 | n5407; - assign n5812 = n5413 | n5410 | n5411; - assign n5813 = n5812 | n5408 | n5409; - assign n5814 = n5813 | n5412 | n5414; - assign n5815 = n5420 | n5417 | n5418; - assign n5816 = n5815 | n5415 | n5416; - assign n5817 = n5816 | n5419 | n5421; - assign n5818 = (n5811 & n5814) | (n3848 & (ppeaks_0_0_ | n5814)); - assign n5819 = n3803 & n3798 & ppeaka_2_2_ & ~\[16933] ; - assign n5820 = n3803 & n3798 & ppeaka_3_3_ & ~\[16933] ; - assign n5821 = n3803 & n3798 & ppeaka_4_4_ & ~\[16933] ; - assign n5822 = n3803 & n3798 & ppeaka_5_5_ & ~\[16933] ; - assign n5823 = n3803 & n3798 & ppeaka_6_6_ & ~\[16933] ; - assign n5824 = n5405 | n5402 | n5403; - assign n5825 = n5824 | n5400 | n5401; - assign n5826 = n5825 | n5404 | n5406; - assign n5827 = n5398 | n5395 | n5396; - assign n5828 = n5827 | n5393 | n5394; - assign n5829 = n5828 | n5397 | n5399; - assign n5830 = n5391 | n5388 | n5389; - assign n5831 = n5830 | n5386 | n5387; - assign n5832 = n5831 | n5390 | n5392; - assign n5833 = n5384 | n5381 | n5382; - assign n5834 = n5833 | n5379 | n5380; - assign n5835 = n5834 | n5383 | n5385; - assign n5836 = n3803 & n3798 & ppeaka_7_7_ & ~\[16933] ; - assign n5837 = n3803 & n3798 & ppeaka_8_8_ & ~\[16933] ; - assign n5838 = n3803 & n3798 & ppeaka_9_9_ & ~\[16933] ; - assign n5839 = n3803 & n3798 & ppeaka_10_10_ & ~\[16933] ; - assign n5840 = n5376 | n5373 | n5374; - assign n5841 = n5840 | n5371 | n5372; - assign n5842 = n5841 | n5375 | n5377; - assign n5843 = n5369 | n5366 | n5367; - assign n5844 = n5843 | n5364 | n5365; - assign n5845 = n5844 | n5368 | n5370; - assign n5846 = n5362 | n5359 | n5360; - assign n5847 = n5846 | n5357 | n5358; - assign n5848 = n5847 | n5361 | n5363; - assign n5849 = n5355 | n5352 | n5353; - assign n5850 = n5849 | n5350 | n5351; - assign n5851 = n5850 | n5354 | n5356; - assign n5852 = n5348 | n5345 | n5346; - assign n5853 = n5852 | n5343 | n5344; - assign n5854 = n5853 | n5347 | n5349; - assign n5855 = n3803 & n3798 & ppeaka_11_11_ & ~\[16933] ; - assign n5856 = n3803 & n3798 & ppeaka_12_12_ & ~\[16933] ; - assign n5857 = n3803 & n3798 & ppeaka_13_13_ & ~\[16933] ; - assign n5858 = n3803 & n3798 & ppeaka_14_14_ & ~\[16933] ; - assign n5859 = n5338 | (\[8405] & n3698); - assign n5860 = n5330 | (\[4355] & n3697) | n5337; - assign n5861 = n5331 | n5332 | n5333 | n5334; - assign n5862 = n5335 | n5336 | n5339 | n5861; - assign n5863 = n5328 | n5327; - assign n5864 = (ppeakp_7_7_ & n3699) | (ppeaka_8_8_ & n3700); - assign n5865 = (\[12335] & n3698) | (~ppeaka_7_7_ & n3697); - assign n5866 = n5322 | (ppeakb_7_7_ & n3701_1) | (~ppeakb_7_7_ & n3697); - assign n5867 = n5323 | n5324 | n5325 | n5326; - assign n5868 = n5329 | n5863 | n5864 | n5865; - assign n5869 = n5321 | (\[9620] & n3756 & n3827_1); - assign n5870 = n5318 | (\[9605] & n3756 & n3827_1); - assign n5871 = n5312 | n5311; - assign n5872 = n5314 | n5303 | n5313; - assign n5873 = (\[14975] & n3698) | (\[11120] & n3697); - assign n5874 = n5302 | n5304 | n5305 | n5306; - assign n5875 = n5307 | n5308 | n5309 | n5310; - assign n5876 = n5315 | n5871 | n5872 | n5873; - assign n5877 = n5299 | (\[5555] & (n5627 | n5628)); - assign n5878 = n5877 | (\[6290] & n3756 & n3806); - assign n5879 = n5265 | (\[14810] & n3698); - assign n5880 = n5257 | (\[5090] & n3697) | n5264; - assign n5881 = n5258 | n5259 | n5260 | n5261; - assign n5882 = n5262 | n5263 | n5266 | n5881; - assign n5883 = n5255 | n5254; - assign n5884 = (ppeakp_8_8_ & n3699) | (ppeaka_9_9_ & n3700); - assign n5885 = (\[15695] & n3698) | (~ppeaka_8_8_ & n3697); - assign n5886 = n5249 | (ppeakb_8_8_ & n3701_1) | (~ppeakb_8_8_ & n3697); - assign n5887 = n5250 | n5251 | n5252 | n5253; - assign n5888 = n5256 | n5883 | n5884 | n5885; - assign n5889 = n5248 | (\[8945] & n3756 & n3827_1); - assign n5890 = n5242 | n5241; - assign n5891 = n5244 | n5233 | n5243; - assign n5892 = (\[11375] & n3697) | (\[6725] & n3698); - assign n5893 = n5232 | n5234 | n5235 | n5236; - assign n5894 = n5237 | n5238 | n5239 | n5240; - assign n5895 = n5245 | n5890 | n5891 | n5892; - assign n5896 = n5228 | n5227; - assign n5897 = n5230 | n5219 | n5229; - assign n5898 = (\[13745] & n3698) | (\[9275] & n3697); - assign n5899 = n5218 | n5220 | n5221 | n5222; - assign n5900 = n5223 | n5224 | n5225 | n5226; - assign n5901 = n5231 | n5896 | n5897 | n5898; - assign n5902 = n5215 | (\[8855] & (n5627 | n5628)); - assign n5903 = n5902 | (\[11210] & n3756 & n3806); - assign n5904 = n5180 | (\[15890] & n3698); - assign n5905 = n5172 | (\[4370] & n3697) | n5179; - assign n5906 = n5173 | n5174 | n5175 | n5176; - assign n5907 = n5177 | n5178 | n5181 | n5906; - assign n5908 = n5170 | (\[7130] & n3698); - assign n5909 = n5162 | (\[5780] & n3697) | n5169; - assign n5910 = n5163 | n5164 | n5165 | n5166; - assign n5911 = n5167 | n5168 | n5171 | n5910; - assign n5912 = n5161 | (\[5630] & n3756 & n3827_1); - assign n5913 = n5155 | n5154; - assign n5914 = n5157 | n5146 | n5156; - assign n5915 = (\[15320] & n3697) | (\[7355] & n3698); - assign n5916 = n5145 | n5147 | n5148 | n5149; - assign n5917 = n5150 | n5151 | n5152 | n5153; - assign n5918 = n5158 | n5913 | n5914 | n5915; - assign n5919 = n5141 | n5140; - assign n5920 = n5143 | n5132 | n5142; - assign n5921 = (\[14135] & n3698) | (\[8615] & n3697); - assign n5922 = n5131 | n5133 | n5134 | n5135; - assign n5923 = n5136 | n5137 | n5138 | n5139; - assign n5924 = n5144 | n5919 | n5920 | n5921; - assign n5925 = n5128 | (\[9530] & (n5627 | n5628)); - assign n5926 = n5925 | (\[10955] & n3756 & n3806); - assign n5927 = n5100 | (\[11240] & n3756 & n3827_1); - assign n5928 = n5094 | n5093; - assign n5929 = n5096 | n5085 | n5095; - assign n5930 = (\[5360] & n3698) | (\[4640] & n3697); - assign n5931 = n5084 | n5086 | n5087 | n5088; - assign n5932 = n5089 | n5090 | n5091 | n5092; - assign n5933 = n5097 | n5928 | n5929 | n5930; - assign n5934 = n5080 | n5079; - assign n5935 = n5082 | n5071 | n5081; - assign n5936 = (\[16055] & n3698) | (\[4625] & n3697); - assign n5937 = n5070 | n5072 | n5073 | n5074; - assign n5938 = n5075 | n5076 | n5077 | n5078; - assign n5939 = n5083 | n5934 | n5935 | n5936; - assign n5940 = n5067 | (\[7565] & (n5627 | n5628)); - assign n5941 = n5940 | (\[11195] & n3756 & n3806); - assign n5942 = n5036 | (\[10430] & n3756 & n3827_1); - assign n5943 = n5030 | n5029; - assign n5944 = n5032 | n5021 | n5031; - assign n5945 = (\[6050] & n3698) | (\[5345] & n3697); - assign n5946 = n5020 | n5022 | n5023 | n5024; - assign n5947 = n5025 | n5026 | n5027 | n5028; - assign n5948 = n5033 | n5943 | n5944 | n5945; - assign n5949 = n5017 | (\[9815] & (n5627 | n5628)); - assign n5950 = n5949 | (\[8900] & n3756 & n3806); - assign n5951 = n5013 | (\[8195] & (n5627 | n5628)); - assign n5952 = n5951 | (\[10940] & n3756 & n3806); - assign n5953 = n4982 | (\[10715] & n3756 & n3827_1); - assign n5954 = n4976 | n4975; - assign n5955 = n4978 | n4967 | n4977; - assign n5956 = (\[15350] & n3698) | (\[6020] & n3697); - assign n5957 = n4966 | n4968 | n4969 | n4970; - assign n5958 = n4971 | n4972 | n4973 | n4974; - assign n5959 = n4979 | n5954 | n5955 | n5956; - assign n5960 = n4963 | (\[10655] & (n5627 | n5628)); - assign n5961 = n5960 | (\[5600] & n3756 & n3806); - assign n5962 = n4959 | (\[6260] & (n5627 | n5628)); - assign n5963 = n5962 | (\[6950] & n3756 & n3806); - assign n5964 = n4929 | n4928; - assign n5965 = n4931 | n4920 | n4930; - assign n5966 = (\[6710] & n3697) | (\[4655] & n3698); - assign n5967 = n4919 | n4921 | n4922 | n4923; - assign n5968 = n4924 | n4925 | n4926 | n4927; - assign n5969 = n4932 | n5964 | n5965 | n5966; - assign n5970 = n4915 | n4914; - assign n5971 = n4917 | n4906 | n4916; - assign n5972 = (\[15710] & n3698) | (\[6695] & n3697); - assign n5973 = n4905 | n4907 | n4908 | n4909; - assign n5974 = n4910 | n4911 | n4912 | n4913; - assign n5975 = n4918 | n5970 | n5971 | n5972; - assign n5976 = n4902 | (\[10370] & (n5627 | n5628)); - assign n5977 = n5976 | (\[4895] & n3756 & n3806); - assign n5978 = n4898 | (\[6935] & (n5627 | n5628)); - assign n5979 = n5978 | (\[6275] & n3756 & n3806); - assign n5980 = n4769 | (\[13250] & n3698); - assign n5981 = n4761 | (\[13235] & n3697) | n4768; - assign n5982 = n4762 | n4763 | n4764 | n4765; - assign n5983 = n4766 | n4767 | n4770 | n5982; - assign n5984 = n4754 | (\[7880] & n3756 & n3812_1); - assign n5985 = n5984 | n4751; - assign n5986 = n4744 | n4745 | n4746 | n4747; - assign n5987 = n4748 | n4749 | n4750 | n4752; - assign n5988 = n4731 | (\[6620] & n3756 & n3812_1); - assign n5989 = n5988 | n4728; - assign n5990 = n4721 | n4722 | n4723 | n4724; - assign n5991 = n4725 | n4726 | n4727 | n4729; - assign n5992 = n4661 | (\[5795] & n3698); - assign n5993 = n4653 | (\[14360] & n3697) | n4660; - assign n5994 = n4654 | n4655 | n4656 | n4657; - assign n5995 = n4658 | n4659 | n4662 | n5994; - assign n5996 = n4651 | n4650; - assign n5997 = (ppeakp_9_9_ & n3699) | (ppeaka_10_10_ & n3700); - assign n5998 = (\[16040] & n3698) | (~ppeaka_9_9_ & n3697); - assign n5999 = n4645 | (ppeakb_9_9_ & n3701_1) | (~ppeakb_9_9_ & n3697); - assign n6000 = n4646 | n4647 | n4648 | n4649; - assign n6001 = n4652 | n5996 | n5997 | n5998; - assign n6002 = n4623 | (\[6485] & n3698); - assign n6003 = n4615 | (\[13955] & n3697) | n4622; - assign n6004 = n4616 | n4617 | n4618 | n4619; - assign n6005 = n4620 | n4621 | n4624 | n6004; - assign n6006 = n4614 | (\[9890] & n3756 & n3827_1); - assign n6007 = n4609 | (\[10085] & (n5627 | n5628)); - assign n6008 = n6007 | (\[9575] & n3756 & n3806); - assign n6009 = n4585 | n4584_1; - assign n6010 = (ppeakp_11_11_ & n3699) | (ppeaka_12_12_ & n3700); - assign n6011 = (\[15335] & n3698) | (~ppeakb_11_11_ & n3697); - assign n6012 = n4579_1 | n4578 | (~ppeaka_11_11_ & n3697); - assign n6013 = n4580 | n4581 | n4582 | n4583; - assign n6014 = n4586 | n6009 | n6010 | n6011; - assign n6015 = n4575 | n4565_1 | n4566; - assign n6016 = n4567 | n4568 | n4569 | n4570_1; - assign n6017 = n4564 | n4571 | n4572 | n4576; - assign n6018 = n4573 | n4574_1 | n6015 | n6017; - assign n6019 = n4561_1 | (\[8840] & (n5627 | n5628)); - assign n6020 = n6019 | (\[11660] & n3756 & n3806); - assign n6021 = n4538 | (\[14915] & n3756 & n3812_1); - assign n6022 = n6021 | n4535; - assign n6023 = n4528_1 | n4529 | n4530 | n4531; - assign n6024 = n4532 | n4533_1 | n4534 | n4536; - assign n6025 = n4525 | n4515 | n4516; - assign n6026 = n4517 | n4518_1 | n4519 | n4520; - assign n6027 = n4514_1 | n4521 | n4522 | n4526; - assign n6028 = n4523_1 | n4524 | n6025 | n6027; - assign n6029 = n4511 | n4501 | n4502; - assign n6030 = n4503 | n4504_1 | n4505 | n4506; - assign n6031 = n4500 | n4507 | n4508 | n4512; - assign n6032 = n4509_1 | n4510 | n6029 | n6031; - assign n6033 = n4497 | (\[9515] & (n5627 | n5628)); - assign n6034 = n6033 | (\[11435] & n3756 & n3806); - assign n6035 = n4471 | (\[13010] & n3756 & n3812_1); - assign n6036 = n6035 | n4468; - assign n6037 = n4461 | n4462_1 | n4463 | n4464; - assign n6038 = n4465 | n4466_1 | n4467 | n4469; - assign n6039 = n4459 | n4458; - assign n6040 = (ppeakp_13_13_ & n3699) | (ppeaka_14_14_ & n3700); - assign n6041 = (\[14540] & n3698) | (~ppeakb_13_13_ & n3697); - assign n6042 = n4453 | n4452_1 | (~ppeaka_13_13_ & n3697); - assign n6043 = n4454 | n4455 | n4456 | n4457_1; - assign n6044 = n4460 | n6039 | n6040 | n6041; - assign n6045 = n4449 | n4439 | n4440; - assign n6046 = n4441 | n4442_1 | n4443 | n4444; - assign n6047 = n4438 | n4445 | n4446 | n4450; - assign n6048 = n4447_1 | n4448 | n6045 | n6047; - assign n6049 = n4437_1 | (\[9875] & n3756 & n3827_1); - assign n6050 = n4431 | n4430; - assign n6051 = n4433 | n4422_1 | n4432_1; - assign n6052 = (\[13040] & n3698) | (\[7970] & n3697); - assign n6053 = n4421 | n4423 | n4424 | n4425; - assign n6054 = n4426 | n4427_1 | n4428 | n4429; - assign n6055 = n4434 | n6050 | n6051 | n6052; - assign n6056 = n4418 | (\[7580] & (n5627 | n5628)); - assign n6057 = n6056 | (\[11675] & n3756 & n3806); - assign n6058 = n4397_1 | (\[16010] & n3756 & n3812_1); - assign n6059 = n6058 | n4394; - assign n6060 = n4387_1 | n4388 | n4389 | n4390; - assign n6061 = n4391 | n4392_1 | n4393 | n4395; - assign n6062 = n4385 | n4384; - assign n6063 = (ppeaka_13_13_ & n3700) | (ppeakp_12_12_ & n3699); - assign n6064 = (\[14120] & n3698) | (~ppeaka_12_12_ & n3697); - assign n6065 = n4379 | (ppeakb_12_12_ & n3701_1) | (~ppeakb_12_12_ & n3697); - assign n6066 = n4380 | n4381 | n4382 | n4383_1; - assign n6067 = n4386 | n6062 | n6063 | n6064; - assign n6068 = n4376 | n4366 | n4367; - assign n6069 = n4368_1 | n4369 | n4370 | n4371; - assign n6070 = n4365 | n4372 | n4373_1 | n4377; - assign n6071 = n4374 | n4375 | n6068 | n6070; - assign n6072 = n4364 | (\[10730] & n3756 & n3827_1); - assign n6073 = n4358_1 | n4357; - assign n6074 = n4360 | n4349 | n4359; - assign n6075 = (\[13385] & n3698) | (\[7340] & n3697); - assign n6076 = n4348_1 | n4350 | n4351 | n4352; - assign n6077 = n4353_1 | n4354 | n4355 | n4356; - assign n6078 = n4361 | n6073 | n6074 | n6075; - assign n6079 = n4345 | (\[8210] & (n5627 | n5628)); - assign n6080 = n6079 | (\[11450] & n3756 & n3806); - assign n6081 = n4326 | (\[13685] & n3756 & n3812_1); - assign n6082 = n6081 | n4323; - assign n6083 = n4316 | n4317 | n4318 | n4319_1; - assign n6084 = n4320 | n4321 | n4322 | n4324_1; - assign n6085 = n4303 | n4304_1 | n4305 | n4306; - assign n6086 = n4307 | n4308 | n4310 | n4314_1; - assign n6087 = n4309_1 | n4311 | n4312 | n4313; - assign n6088 = n4300_1 | n4290_1 | n4291; - assign n6089 = n4292 | n4293 | n4294 | n4295_1; - assign n6090 = n4289 | n4296 | n4297 | n4301; - assign n6091 = n4298 | n4299 | n6088 | n6090; - assign n6092 = n4288 | (\[10445] & n3756 & n3827_1); - assign n6093 = n4285_1 | (\[8930] & n3756 & n3827_1); - assign n6094 = n4279 | n4278; - assign n6095 = n4281 | n4270_1 | n4280_1; - assign n6096 = (\[13025] & n3698) | (\[5330] & n3697); - assign n6097 = n4269 | n4271 | n4272 | n4273; - assign n6098 = n4274 | n4275_1 | n4276 | n4277; - assign n6099 = n4282 | n6094 | n6095 | n6096; - assign n6100 = n4254 | (\[6500] & n3698); - assign n6101 = n4246 | (\[7115] & n3697) | n4253; - assign n6102 = n4247_1 | n4248 | n4249 | n4250; - assign n6103 = n4251_1 | n4252 | n4255 | n6102; - assign n6104 = n4244 | n4243; - assign n6105 = (ppeakp_14_14_ & n3699) | (ppeaka_15_15_ & n3700); - assign n6106 = (\[13370] & n3698) | (~ppeaka_14_14_ & n3697); - assign n6107 = n4238 | (ppeakb_14_14_ & n3701_1) | (~ppeakb_14_14_ & n3697); - assign n6108 = n4239 | n4240 | n4241 | n4242_1; - assign n6109 = n4245 | n6104 | n6105 | n6106; - assign n6110 = n4235 | n4225 | n4226; - assign n6111 = n4227_1 | n4228 | n4229 | n4230; - assign n6112 = n4224 | n4231 | n4232_1 | n4236; - assign n6113 = n4233 | n4234 | n6110 | n6112; - assign n6114 = n4223_1 | (\[8285] & n3756 & n3827_1); - assign n6115 = n4220 | (\[10145] & n3756 & n3827_1); - assign n6116 = n4214 | n4213_1; - assign n6117 = n4216 | n4205 | n4215; - assign n6118 = (\[12800] & n3698) | (\[6035] & n3697); - assign n6119 = n4204 | n4206 | n4207 | n4208_1; - assign n6120 = n4209 | n4210 | n4211 | n4212; - assign n6121 = n4217 | n6116 | n6117 | n6118; - assign n6122 = (\[17999] & ~\[18220] ) | (~\[17791] & n3788); - assign n6123 = (\[17180] & ~\[17232] ) | (~\[17050] & \[17115] ); - assign n6124 = (\[17206] & ~\[17271] ) | (\[16933] & ~\[17388] ); - assign n6125 = (\[18311] & ~\[18389] ) | (~\[17414] & \[17843] ); - assign n6126 = n6125 | n6124; - assign n6127 = n3789 | n3794 | n3879 | n6123; - assign n6128 = n3816 | n6122 | n6126 | n6127; - assign n6129 = n6128 | (~\[17167] & n3798 & n3819); - assign n6130 = n3858 | n3813 | n3817_1; - assign n6131 = n3792_1 | n5735 | n5736 | n6129; - assign n6132 = n4141 | (~preset & \[17284] & ~\[18376] ); - assign n6133 = n6132 | (~preset & n3798 & n5732); - assign n6134 = ~preset & n3798 & (n5731 | n5733); - assign n6135 = n4182 | n4181; - assign n6136 = n4183 | (ppeakb_8_8_ & n3777_1); - assign n6137 = (\[13460] & n3775) | (\[7595] & n3776); - assign n6138 = (\[11420] & n3773) | (\[6410] & n3774); - assign n6139 = n4177 | n4178 | n4179_1 | n4180; - assign n6140 = n4184_1 | n4185 | n6135 | n6136; - assign n6141 = n4186 | n6137 | n6138 | n6139; - assign n6142 = n4176 | (~preset & ppeakb_7_7_ & n3859); - assign n6143 = ~\[17388] & ~preset; - assign n6144 = n4170 | n4169_1; - assign n6145 = n4171 | (ppeakb_9_9_ & n3777_1); - assign n6146 = (\[13820] & n3775) | (\[10685] & n3776); - assign n6147 = (\[11645] & n3773) | (\[5720] & n3774); - assign n6148 = n4165_1 | n4166 | n4167 | n4168; - assign n6149 = n4172 | n4173 | n6144 | n6145; - assign n6150 = n4174_1 | n6146 | n6147 | n6148; - assign n6151 = n4164 | (~preset & ppeakb_8_8_ & n3859); - assign n6152 = n4162 | (~preset & ppeakb_5_5_ & n3859); - assign n6153 = n4160_1 | (~preset & ppeakb_6_6_ & n3859); - assign n6154 = n4158 | (~preset & ppeakb_15_15_ & n3859); - assign n6155 = ~\[17050] & ~preset; - assign n6156 = n4156 | (~preset & ppeakb_3_3_ & n3859); - assign n6157 = ~\[17232] & ~preset; - assign n6158 = n4154 | (~preset & ppeakb_4_4_ & n3859); - assign n6159 = ~\[17271] & ~preset; - assign n6160 = n4152 | (~preset & ppeakb_1_1_ & n3859); - assign n6161 = ~\[18376] & ~preset; - assign n6162 = n4150_1 | (~preset & ppeakb_2_2_ & n3859); - assign n6163 = n4144 | n4143; - assign n6164 = n4145 | (ppeakb_11_11_ & n3777_1); - assign n6165 = (\[13115] & n3775) | (\[10115] & n3776); - assign n6166 = (\[16100] & n3773) | (\[4295] & n3774); - assign n6167 = n4139 | n4140 | n4141_1 | n4142; - assign n6168 = n4146_1 | n4147 | n6163 | n6164; - assign n6169 = n4148 | n6165 | n6166 | n6167; - assign n6170 = n4134 | n4133; - assign n6171 = n4135 | (ppeakb_10_10_ & n3777_1); - assign n6172 = (\[12860] & n3775) | (\[10400] & n3776); - assign n6173 = (\[10925] & n3773) | (\[5015] & n3774); - assign n6174 = n4129 | n4130 | n4131_1 | n4132; - assign n6175 = n4136_1 | n4137 | n6170 | n6171; - assign n6176 = n4138 | n6172 | n6173 | n6174; - assign n6177 = n4128 | (~preset & ppeakb_13_13_ & n3859); - assign n6178 = n4121_1 | n4120; - assign n6179 = n4122 | (ppeakb_13_13_ & n3777_1); - assign n6180 = (\[12620] & n3775) | (\[8885] & n3776); - assign n6181 = (\[15500] & n3774) | (\[13805] & n3773); - assign n6182 = n4116_1 | n4117 | n4118 | n4119; - assign n6183 = n4123 | n4124 | n6178 | n6179; - assign n6184 = n4125 | n6180 | n6181 | n6182; - assign n6185 = ~n3883_1 | (~ppeaki_13_13_ & ~ppeaki_12_12_); - assign n6186 = ~n3883_1 | (~ppeaki_15_15_ & ~ppeaki_14_14_); - assign n6187 = n6185 & (~n3883_1 | (~ppeaki_15_15_ & ~ppeaki_14_14_)); - assign n6188 = ~n3759 & ~n3755 & ~n3758_1 & ~n3765; - assign n6189 = ~n3770 & ~n3766 & ~n3768_1 & ~n3772_1; - assign n6190 = n6188 & n6185 & n6186; - assign n6191 = n6189 & (\[18636] | (~n3798 & n5672)); - assign n6192 = \[17986] & \[17596] ; - assign n6193 = n4115 | \[17804] | (\[17986] & \[18597] ); - assign n6194 = ~\[18597] & ~preset & \[17596] ; - assign n6195 = n3790 & ~preset & ~\[17596] ; - assign n6196 = n4109 | n4108; - assign n6197 = n4110 | (ppeakb_12_12_ & n3777_1); - assign n6198 = (\[12395] & n3775) | (\[9845] & n3776); - assign n6199 = (\[15845] & n3774) | (\[15755] & n3773); - assign n6200 = n4104 | n4105 | n4106_1 | n4107; - assign n6201 = n4111_1 | n4112 | n6196 | n6197; - assign n6202 = n4113 | n6198 | n6199 | n6200; - assign n6203 = n4099 | n4098; - assign n6204 = n4100 | (ppeakb_15_15_ & n3777_1); - assign n6205 = (\[15050] & n3775) | (\[4880] & n3776); - assign n6206 = (\[14615] & n3773) | (\[13550] & n3774); - assign n6207 = n4094 | n4095 | n4096_1 | n4097; - assign n6208 = n4101_1 | n4102 | n6203 | n6204; - assign n6209 = n4103 | n6205 | n6206 | n6207; - assign n6210 = n4089 | n4088; - assign n6211 = n4090 | (ppeakb_14_14_ & n3777_1); - assign n6212 = (\[15410] & n3775) | (\[9560] & n3776); - assign n6213 = (\[15140] & n3774) | (\[13445] & n3773); - assign n6214 = n4084 | n4085 | n4086_1 | n4087; - assign n6215 = n4091_1 | n4092 | n6210 | n6211; - assign n6216 = n4093 | n6212 | n6213 | n6214; - assign n6217 = n4083 | (~preset & ppeakb_9_9_ & n3859); - assign n6218 = n4081_1 | (~preset & ppeakb_14_14_ & n3859); - assign n6219 = (\[17180] & ~\[17232] ) | (~\[17050] & \[17115] ); - assign n6220 = (\[17206] & ~\[17271] ) | (\[17232] & ~\[18441] ); - assign n6221 = (\[17583] & ~\[18077] ) | (~\[17427] & \[17518] ); - assign n6222 = (\[17050] & ~\[17219] ) | (\[17271] & ~\[17349] ); - assign n6223 = n3789 | n3879 | n6219 | n6220; - assign n6224 = n6223 | n6221 | n6222; - assign n6225 = n3789 & ~preset; - assign n6226 = pwr_0_0_ & ~preset; - assign n6227 = (~n3858 & ~n6224 & n6226) | (n6225 & (n3858 | n6224)); - assign n6228 = ~preset & (n3858 | (n3781 & n6224)); - assign n6229 = (n4011 | n4081) & (n3858 | n6224); - assign n6230 = (\[16933] & ~\[17388] ) | (~\[17414] & \[17843] ); - assign n6231 = (\[18311] & ~\[18389] ) | (\[18363] & ~\[18415] ); - assign n6232 = (\[17791] & ~\[17843] ) | (\[17453] & ~\[18246] ); - assign n6233 = (\[17102] & ~\[17154] ) | (\[17167] & ~\[17362] ); - assign n6234 = (\[17414] & ~\[17505] ) | (~\[17310] & \[17388] ); - assign n6235 = (~\[18142] & \[18220] ) | (~\[18311] & \[18506] ); - assign n6236 = (\[17570] & ~\[17635] ) | (\[18285] & ~\[18363] ); - assign n6237 = (\[18415] & ~\[18480] ) | (~\[18428] & \[18493] ); - assign n6238 = (~\[18298] & \[18376] ) | (~\[16985] & \[18389] ); - assign n6239 = (\[16920] & ~\[16972] ) | (\[17297] & ~\[17375] ); - assign n6240 = n6239 | n3879 | n6230; - assign n6241 = n6231 | n6232 | n6233 | n6234; - assign n6242 = n6235 | n6236 | n6237 | n6238; - assign n6243 = n6242 | n6240 | n6241; - assign n6244 = n6243 | n3816 | n6122; - assign n6245 = n6244 | (~\[17167] & n3798 & n3819); - assign n6246 = n3792_1 | n3813 | n3817_1 | n6245; - assign n6247 = ~preset & (n3816 | n6122); - assign n6248 = prd_0_0_ & ~preset; - assign n6249 = (~n3878_1 & ~n6246 & n6248) | (n6247 & (n3878_1 | n6246)); - assign n6250 = (n3706_1 | n3709) & (n3878_1 | n6246); - assign n6251 = (n4518 | n3791) & (n3878_1 | n6246); - assign n6252 = (n4150 | n4509) & (n3878_1 | n6246); - assign n6253 = (n4031 | n4056) & (n3878_1 | n6246); - assign n6254 = n6253 | n6249 | n6250; - assign n6255 = n4078 | (~preset & ppeakb_10_10_ & n3859); - assign n6256 = n4076_1 | (~preset & ppeakb_12_12_ & n3859); - assign n6257 = \[18129] & ~preset; - assign n6258 = n4065 | (~preset & ppeakb_11_11_ & n3859); - assign n6259 = n4057 | n4056_1; - assign n6260 = (\[10670] & n3776) | (ppeakb_0_0_ & n3777_1); - assign n6261 = (\[12605] & n3775) | (\[4310] & n3774); - assign n6262 = n4051_1 | (\[11630] & n3773) | n4061_1; - assign n6263 = n4052 | n4053 | n4054 | n4055; - assign n6264 = n4058 | n4059 | n6259 | n6260; - assign n6265 = n4060 | n6261 | n6262 | n6263; - assign n6266 = ~\[18415] & ~preset; - assign n6267 = n4047 | n4043; - assign n6268 = (\[9830] & n3776) | (ppeakb_1_1_ & n3777_1); - assign n6269 = (\[12380] & n3775) | (\[5030] & n3774); - assign n6270 = n4037 | (\[9485] & n3773) | n4038; - assign n6271 = n4039 | n4040 | n4041_1 | n4042; - assign n6272 = n4044 | n4045 | n6267 | n6268; - assign n6273 = n4046_1 | n6269 | n6270 | n6271; - assign n6274 = n4036_1 | (~preset & ppeakb_0_0_ & n3859); - assign n6275 = n4030 | n4029; - assign n6276 = n4031_1 | (ppeakb_2_2_ & n3777_1); - assign n6277 = (\[13100] & n3775) | (\[10100] & n3776); - assign n6278 = (\[15515] & n3774) | (\[7535] & n3773); - assign n6279 = n4025 | n4026_1 | n4027 | n4028; - assign n6280 = n4032 | n4033 | n6275 | n6276; - assign n6281 = n4034 | n6277 | n6278 | n6279; - assign n6282 = n4020 | n4019; - assign n6283 = n4021_1 | (ppeakb_3_3_ & n3777_1); - assign n6284 = (\[12845] & n3775) | (\[5570] & n3776); - assign n6285 = (\[15860] & n3774) | (\[8165] & n3773); - assign n6286 = n4015 | n4016_1 | n4017 | n4018; - assign n6287 = n4022 | n4023 | n6282 | n6283; - assign n6288 = n4024 | n6284 | n6285 | n6286; - assign n6289 = \[17700] & ~preset & ~pdn; - assign n6290 = n4008 | n4007; - assign n6291 = n4009 | (ppeakb_4_4_ & n3777_1); - assign n6292 = (\[15035] & n3775) | (\[4865] & n3776); - assign n6293 = (\[14765] & n3774) | (\[6230] & n3773); - assign n6294 = n4003 | n4004 | n4005 | n4006_1; - assign n6295 = n4010 | n4011_1 | n6290 | n6291; - assign n6296 = n4012 | n6292 | n6293 | n6294; - assign n6297 = n3998 | n3997; - assign n6298 = n3999 | (ppeakb_5_5_ & n3777_1); - assign n6299 = (\[15395] & n3775) | (\[9545] & n3776); - assign n6300 = (\[8330] & n3774) | (\[6905] & n3773); - assign n6301 = n3993 | n3994 | n3995 | n3996_1; - assign n6302 = n4000 | n4001_1 | n6297 | n6298; - assign n6303 = n4002 | n6299 | n6300 | n6301; - assign n6304 = n3988 | n3987; - assign n6305 = n3989 | (ppeakb_6_6_ & n3777_1); - assign n6306 = (\[14210] & n3775) | (\[8870] & n3776); - assign n6307 = (\[7685] & n3774) | (\[4835] & n3773); - assign n6308 = n3983 | n3984 | n3985 | n3986_1; - assign n6309 = n3990 | n3991_1 | n6304 | n6305; - assign n6310 = n3992 | n6306 | n6307 | n6308; - assign n6311 = \[17596] & ~preset & ~pdn; - assign n6312 = n3798 & ~preset & n3796; - assign n6313 = n3798 & n3797_1 & ~preset & n3796; - assign n6314 = n3798 & n3796 & ~preset & \[18168] ; - assign n6315 = n3798 & n3796 & ~preset & \[17453] ; - assign n6316 = ~n3783 & (n6313 | n6314); - assign n6317 = ~n3783 & (n6315 | (~n3787_1 & n6312)); - assign n6318 = n3976_1 | n3975; - assign n6319 = n3977 | (ppeakb_7_7_ & n3777_1); - assign n6320 = (\[14630] & n3775) | (\[8225] & n3776); - assign n6321 = (\[7055] & n3774) | (\[5540] & n3773); - assign n6322 = n3971 | n3972_1 | n3973 | n3974; - assign n6323 = n3978 | n3979 | n6318 | n6319; - assign n6324 = n3980 | n6320 | n6321 | n6322; - assign n6325 = ~preset & n3798 & (\[18493] | n3811); - assign n6326 = ~preset & n3798 & (\[18389] | \[18415] ); - assign n6327 = ~preset & n3798 & (\[17388] | \[18376] ); - assign n6328 = ~preset & n3798 & (\[17271] | \[17297] ); - assign n6329 = ~preset & n3798 & (\[17167] | \[17232] ); - assign n6330 = ~preset & n3798 & (\[17050] | \[17102] ); - assign n6331 = n6330 | n3969 | n6325; - assign n6332 = n6326 | n6327 | n6328 | n6329; - always @ (posedge pclk) begin - ndout <= n273; - ppeakb_12_12_ <= n278; - ppeakb_1_1_ <= n282; - ppeaka_6_6_ <= n286; - \[4295] <= n290; - \[4310] <= n295; - ppeaks_5_5_ <= n300; - ppeakp_10_10_ <= n304; - \[4355] <= n308; - \[4370] <= n313; - \[4385] <= n318; - \[4400] <= n323; - \[4415] <= n328; - \[4430] <= n333; - \[4445] <= n338; - \[4460] <= n343; - \[4475] <= n348; - \[4490] <= n353; - \[4505] <= n358; - \[4520] <= n363; - \[4535] <= n368; - \[4550] <= n373; - \[4565] <= n378; - \[4580] <= n383; - \[4595] <= n388; - \[4610] <= n393; - \[4625] <= n398; - \[4640] <= n403; - \[4655] <= n408; - \[4670] <= n413; - \[4700] <= n418; - \[4715] <= n423; - \[4730] <= n428; - \[4745] <= n433; - \[4760] <= n438; - \[4775] <= n443; - \[4790] <= n448; - \[4805] <= n453; - \[4820] <= n458; - \[4835] <= n463; - \[4850] <= n468; - \[4865] <= n473; - \[4880] <= n478; - \[4895] <= n483; - \[4910] <= n488; - \[4925] <= n493; - \[4940] <= n498; - \[4955] <= n503; - \[4970] <= n508; - ppeakb_0_0_ <= n513; - ppeaka_7_7_ <= n517; - \[5015] <= n521; - \[5030] <= n526; - ppeaks_4_4_ <= n531; - ppeakp_11_11_ <= n535; - \[5075] <= n539; - \[5090] <= n544; - \[5105] <= n549; - \[5120] <= n554; - \[5135] <= n559; - \[5150] <= n564; - \[5165] <= n569; - \[5180] <= n574; - \[5195] <= n579; - \[5210] <= n584; - \[5225] <= n589; - \[5240] <= n594; - \[5255] <= n599; - \[5270] <= n604; - \[5285] <= n609; - \[5300] <= n614; - \[5315] <= n619; - \[5330] <= n624; - \[5345] <= n629; - \[5360] <= n634; - \[5375] <= n639; - \[5390] <= n644; - \[5405] <= n649; - \[5420] <= n654; - \[5435] <= n659; - \[5450] <= n664; - \[5465] <= n669; - \[5480] <= n674; - \[5495] <= n679; - \[5510] <= n684; - \[5525] <= n689; - \[5540] <= n694; - \[5555] <= n699; - \[5570] <= n704; - \[5600] <= n709; - \[5615] <= n714; - \[5630] <= n719; - \[5645] <= n724; - \[5660] <= n729; - \[5675] <= n734; - ppeakb_10_10_ <= n739; - ppeaka_8_8_ <= n743; - \[5720] <= n747; - ppeaks_14_14_ <= n752; - ppeaks_7_7_ <= n756; - ppeakp_12_12_ <= n760; - \[5780] <= n764; - \[5795] <= n769; - \[5810] <= n774; - \[5825] <= n779; - \[5840] <= n784; - \[5855] <= n789; - \[5870] <= n794; - \[5885] <= n799; - \[5900] <= n804; - \[5915] <= n809; - \[5930] <= n814; - \[5945] <= n819; - \[5960] <= n824; - \[5975] <= n829; - \[5990] <= n834; - \[6005] <= n839; - \[6020] <= n844; - \[6035] <= n849; - \[6050] <= n854; - \[6065] <= n859; - \[6080] <= n864; - \[6095] <= n869; - \[6110] <= n874; - \[6125] <= n879; - \[6140] <= n884; - \[6155] <= n889; - \[6170] <= n894; - \[6185] <= n899; - \[6200] <= n904; - \[6215] <= n909; - \[6230] <= n914; - \[6245] <= n919; - \[6260] <= n924; - \[6275] <= n929; - \[6290] <= n934; - \[6305] <= n939; - \[6320] <= n944; - \[6335] <= n949; - \[6350] <= n954; - \[6365] <= n959; - ppeakb_11_11_ <= n964; - ppeakb_2_2_ <= n968; - \[6410] <= n972; - ppeaks_15_15_ <= n977; - ppeaks_6_6_ <= n981; - ppeakp_13_13_ <= n985; - \[6470] <= n989; - \[6485] <= n994; - \[6500] <= n999; - \[6515] <= n1004; - \[6530] <= n1009; - \[6545] <= n1014; - \[6560] <= n1019; - \[6575] <= n1024; - \[6590] <= n1029; - \[6605] <= n1034; - \[6620] <= n1039; - \[6635] <= n1044; - \[6650] <= n1049; - \[6665] <= n1054; - \[6680] <= n1059; - \[6695] <= n1064; - \[6710] <= n1069; - \[6725] <= n1074; - \[6740] <= n1079; - \[6755] <= n1084; - \[6770] <= n1089; - \[6785] <= n1094; - \[6815] <= n1099; - \[6830] <= n1104; - \[6845] <= n1109; - \[6860] <= n1114; - \[6875] <= n1119; - \[6890] <= n1124; - \[6905] <= n1129; - \[6920] <= n1134; - \[6935] <= n1139; - \[6950] <= n1144; - \[6965] <= n1149; - \[6980] <= n1154; - \[6995] <= n1159; - \[7010] <= n1164; - \[7025] <= n1169; - \[7055] <= n1174; - ppeaks_12_12_ <= n1179; - ppeaks_1_1_ <= n1183; - ppeakp_3_3_ <= n1187; - \[7115] <= n1191; - \[7130] <= n1196; - \[7145] <= n1201; - \[7160] <= n1206; - \[7175] <= n1211; - \[7190] <= n1216; - \[7205] <= n1221; - \[7220] <= n1226; - \[7235] <= n1231; - \[7250] <= n1236; - \[7265] <= n1241; - \[7280] <= n1246; - \[7295] <= n1251; - \[7310] <= n1256; - \[7325] <= n1261; - \[7340] <= n1266; - \[7355] <= n1271; - \[7370] <= n1276; - \[7385] <= n1281; - \[7400] <= n1286; - \[7415] <= n1291; - \[7430] <= n1296; - \[7445] <= n1301; - \[7460] <= n1306; - \[7475] <= n1311; - \[7490] <= n1316; - \[7505] <= n1321; - \[7520] <= n1326; - \[7535] <= n1331; - \[7550] <= n1336; - \[7565] <= n1341; - \[7580] <= n1346; - \[7595] <= n1351; - \[7625] <= n1356; - \[7640] <= n1361; - \[7655] <= n1366; - \[7670] <= n1371; - \[7685] <= n1376; - ppeaks_13_13_ <= n1381; - ppeakp_7_7_ <= n1385; - ppeakp_2_2_ <= n1389; - \[7745] <= n1393; - \[7760] <= n1398; - \[7775] <= n1403; - \[7790] <= n1408; - \[7805] <= n1413; - \[7820] <= n1418; - \[7835] <= n1423; - \[7850] <= n1428; - \[7865] <= n1433; - \[7880] <= n1438; - \[7895] <= n1443; - \[7910] <= n1448; - \[7925] <= n1453; - \[7940] <= n1458; - \[7955] <= n1463; - \[7970] <= n1468; - \[8000] <= n1473; - \[8015] <= n1478; - \[8030] <= n1483; - \[8045] <= n1488; - \[8060] <= n1493; - \[8075] <= n1498; - \[8090] <= n1503; - \[8105] <= n1508; - \[8120] <= n1513; - \[8135] <= n1518; - \[8150] <= n1523; - \[8165] <= n1528; - \[8180] <= n1533; - \[8195] <= n1538; - \[8210] <= n1543; - \[8225] <= n1548; - \[8240] <= n1553; - \[8255] <= n1558; - \[8285] <= n1563; - \[8300] <= n1568; - \[8315] <= n1573; - \[8330] <= n1578; - ppeaks_3_3_ <= n1583; - ppeakp_8_8_ <= n1587; - ppeakp_1_1_ <= n1591; - \[8390] <= n1595; - \[8405] <= n1600; - \[8420] <= n1605; - \[8435] <= n1610; - \[8450] <= n1615; - \[8465] <= n1620; - \[8480] <= n1625; - \[8495] <= n1630; - \[8510] <= n1635; - \[8525] <= n1640; - \[8540] <= n1645; - \[8555] <= n1650; - \[8570] <= n1655; - \[8585] <= n1660; - \[8600] <= n1665; - \[8615] <= n1670; - \[8630] <= n1675; - \[8645] <= n1680; - \[8660] <= n1685; - \[8675] <= n1690; - \[8690] <= n1695; - \[8705] <= n1700; - \[8720] <= n1705; - \[8735] <= n1710; - \[8750] <= n1715; - \[8765] <= n1720; - \[8780] <= n1725; - \[8810] <= n1730; - \[8825] <= n1735; - \[8840] <= n1740; - \[8855] <= n1745; - \[8870] <= n1750; - \[8885] <= n1755; - \[8900] <= n1760; - \[8915] <= n1765; - \[8930] <= n1770; - \[8945] <= n1775; - \[8960] <= n1780; - \[8975] <= n1785; - ppeaks_11_11_ <= n1790; - ppeaks_2_2_ <= n1794; - ppeakp_9_9_ <= n1798; - ppeakp_0_0_ <= n1802; - \[9050] <= n1806; - \[9065] <= n1811; - \[9080] <= n1816; - \[9095] <= n1821; - \[9110] <= n1826; - \[9125] <= n1831; - \[9140] <= n1836; - \[9155] <= n1841; - \[9170] <= n1846; - \[9185] <= n1851; - \[9200] <= n1856; - \[9215] <= n1861; - \[9230] <= n1866; - \[9245] <= n1871; - \[9260] <= n1876; - \[9275] <= n1881; - \[9290] <= n1886; - \[9305] <= n1891; - \[9320] <= n1896; - \[9335] <= n1901; - \[9350] <= n1906; - \[9365] <= n1911; - \[9380] <= n1916; - \[9395] <= n1921; - \[9410] <= n1926; - \[9440] <= n1931; - \[9455] <= n1936; - \[9470] <= n1941; - \[9485] <= n1946; - \[9500] <= n1951; - \[9515] <= n1956; - \[9530] <= n1961; - \[9545] <= n1966; - \[9560] <= n1971; - \[9575] <= n1976; - \[9590] <= n1981; - \[9605] <= n1986; - \[9620] <= n1991; - \[9635] <= n1996; - \[9650] <= n2001; - \[9665] <= n2006; - \[9680] <= n2011; - ppeaki_6_6_ <= n2016; - \[9710] <= n2020; - \[9725] <= n2025; - \[9740] <= n2030; - \[9770] <= n2035; - \[9785] <= n2040; - \[9800] <= n2045; - \[9815] <= n2050; - \[9830] <= n2055; - \[9845] <= n2060; - \[9860] <= n2065; - \[9875] <= n2070; - \[9890] <= n2075; - \[9905] <= n2080; - \[9920] <= n2085; - \[9935] <= n2090; - \[9950] <= n2095; - \[9980] <= n2100; - \[9995] <= n2105; - \[10010] <= n2110; - \[10025] <= n2115; - \[10040] <= n2120; - \[10055] <= n2125; - \[10070] <= n2130; - \[10085] <= n2135; - \[10100] <= n2140; - \[10115] <= n2145; - \[10130] <= n2150; - \[10145] <= n2155; - \[10175] <= n2160; - \[10190] <= n2165; - \[10205] <= n2170; - \[10220] <= n2175; - ppeaki_15_15_ <= n2180; - ppeaki_4_4_ <= n2184; - \[10265] <= n2188; - \[10280] <= n2193; - \[10310] <= n2198; - \[10325] <= n2203; - \[10340] <= n2208; - \[10355] <= n2213; - \[10370] <= n2218; - \[10400] <= n2223; - \[10415] <= n2228; - \[10430] <= n2233; - \[10445] <= n2238; - \[10460] <= n2243; - \[10475] <= n2248; - \[10490] <= n2253; - \[10505] <= n2258; - ppeaki_14_14_ <= n2263; - ppeaki_5_5_ <= n2267; - \[10550] <= n2271; - \[10565] <= n2276; - \[10580] <= n2281; - \[10595] <= n2286; - \[10610] <= n2291; - \[10625] <= n2296; - \[10655] <= n2301; - \[10670] <= n2306; - \[10685] <= n2311; - \[10700] <= n2316; - \[10715] <= n2321; - \[10730] <= n2326; - \[10745] <= n2331; - \[10760] <= n2336; - \[10775] <= n2341; - \[10790] <= n2346; - \[10805] <= n2351; - \[10820] <= n2356; - \[10850] <= n2361; - \[10865] <= n2366; - \[10880] <= n2371; - \[10895] <= n2376; - \[10925] <= n2381; - \[10940] <= n2386; - \[10955] <= n2391; - \[10970] <= n2396; - \[10985] <= n2401; - \[11015] <= n2406; - \[11030] <= n2411; - \[11045] <= n2416; - \[11060] <= n2421; - \[11075] <= n2426; - \[11090] <= n2431; - \[11120] <= n2436; - \[11135] <= n2441; - \[11150] <= n2446; - \[11165] <= n2451; - \[11180] <= n2456; - \[11195] <= n2461; - \[11210] <= n2466; - \[11225] <= n2471; - \[11240] <= n2476; - \[11255] <= n2481; - \[11270] <= n2486; - \[11285] <= n2491; - \[11300] <= n2496; - \[11315] <= n2501; - \[11330] <= n2506; - \[11345] <= n2511; - \[11375] <= n2516; - \[11390] <= n2521; - \[11405] <= n2526; - \[11420] <= n2531; - \[11435] <= n2536; - \[11450] <= n2541; - \[11465] <= n2546; - \[11480] <= n2551; - \[11495] <= n2556; - \[11510] <= n2561; - \[11525] <= n2566; - \[11540] <= n2571; - \[11555] <= n2576; - \[11570] <= n2581; - \[11585] <= n2586; - \[11600] <= n2591; - \[11615] <= n2596; - \[11630] <= n2601; - \[11645] <= n2606; - \[11660] <= n2611; - \[11675] <= n2616; - \[11690] <= n2621; - \[11705] <= n2626; - \[11720] <= n2631; - \[11735] <= n2636; - \[11750] <= n2641; - \[11765] <= n2646; - \[11780] <= n2651; - \[11795] <= n2656; - \[11810] <= n2661; - ppeaki_9_9_ <= n2666; - ppeakb_14_14_ <= n2670; - \[11885] <= n2674; - \[11900] <= n2679; - \[11915] <= n2684; - \[11930] <= n2689; - ppeaki_8_8_ <= n2694; - ppeakb_15_15_ <= n2698; - \[12005] <= n2702; - \[12020] <= n2707; - \[12035] <= n2712; - \[12050] <= n2717; - \[12065] <= n2722; - \[12080] <= n2727; - ppeaki_7_7_ <= n2732; - \[12125] <= n2736; - \[12140] <= n2741; - \[12155] <= n2746; - \[12170] <= n2751; - \[12185] <= n2756; - \[12200] <= n2761; - ppeakb_13_13_ <= n2766; - \[12245] <= n2770; - \[12260] <= n2775; - \[12275] <= n2780; - ppeaki_13_13_ <= n2785; - ppeaki_2_2_ <= n2789; - \[12335] <= n2793; - \[12350] <= n2798; - \[12365] <= n2803; - \[12380] <= n2808; - \[12395] <= n2813; - \[12410] <= n2818; - \[12425] <= n2823; - \[12440] <= n2828; - \[12455] <= n2833; - \[12470] <= n2838; - \[12485] <= n2843; - ppeaki_12_12_ <= n2848; - ppeaki_3_3_ <= n2852; - \[12545] <= n2856; - \[12560] <= n2861; - \[12575] <= n2866; - \[12590] <= n2871; - \[12605] <= n2876; - \[12620] <= n2881; - \[12635] <= n2886; - \[12650] <= n2891; - \[12665] <= n2896; - \[12680] <= n2901; - \[12695] <= n2906; - ppeaki_11_11_ <= n2911; - ppeaki_0_0_ <= n2915; - \[12770] <= n2919; - \[12800] <= n2924; - \[12815] <= n2929; - \[12830] <= n2934; - \[12845] <= n2939; - \[12860] <= n2944; - \[12875] <= n2949; - \[12890] <= n2954; - \[12905] <= n2959; - \[12920] <= n2964; - \[12935] <= n2969; - ppeaki_10_10_ <= n2974; - ppeaki_1_1_ <= n2978; - \[13010] <= n2982; - \[13025] <= n2987; - \[13040] <= n2992; - \[13055] <= n2997; - \[13070] <= n3002; - \[13085] <= n3007; - \[13100] <= n3012; - \[13115] <= n3017; - \[13130] <= n3022; - \[13160] <= n3027; - \[13175] <= n3032; - ppeakb_4_4_ <= n3037; - ppeaka_9_9_ <= n3041; - \[13220] <= n3045; - \[13235] <= n3050; - \[13250] <= n3055; - \[13265] <= n3060; - \[13280] <= n3065; - \[13295] <= n3070; - \[13310] <= n3075; - \[13325] <= n3080; - \[13340] <= n3085; - \[13355] <= n3090; - \[13370] <= n3095; - \[13385] <= n3100; - \[13400] <= n3105; - \[13415] <= n3110; - \[13430] <= n3115; - \[13445] <= n3120; - \[13460] <= n3125; - \[13475] <= n3130; - \[13490] <= n3135; - \[13505] <= n3140; - ppeakb_5_5_ <= n3145; - \[13550] <= n3149; - ppeakp_6_6_ <= n3154; - \[13580] <= n3158; - \[13595] <= n3163; - \[13610] <= n3168; - \[13625] <= n3173; - \[13640] <= n3178; - \[13655] <= n3183; - \[13670] <= n3188; - \[13685] <= n3193; - \[13700] <= n3198; - \[13715] <= n3203; - \[13730] <= n3208; - \[13745] <= n3213; - \[13775] <= n3218; - \[13790] <= n3223; - \[13805] <= n3228; - \[13820] <= n3233; - \[13835] <= n3238; - \[13850] <= n3243; - \[13865] <= n3248; - \[13880] <= n3253; - \[13895] <= n3258; - ppeaka_11_11_ <= n3263; - ppeaka_0_0_ <= n3267; - ppeakp_5_5_ <= n3271; - \[13955] <= n3275; - \[13970] <= n3280; - \[13985] <= n3285; - \[14000] <= n3290; - \[14015] <= n3295; - \[14030] <= n3300; - \[14045] <= n3305; - \[14060] <= n3310; - \[14075] <= n3315; - \[14090] <= n3320; - \[14105] <= n3325; - \[14120] <= n3330; - \[14135] <= n3335; - \[14150] <= n3340; - \[14165] <= n3345; - \[14180] <= n3350; - \[14210] <= n3355; - \[14225] <= n3360; - \[14240] <= n3365; - \[14255] <= n3370; - \[14270] <= n3375; - \[14285] <= n3380; - ppeakb_3_3_ <= n3385; - ppeaka_10_10_ <= n3389; - ppeaka_1_1_ <= n3393; - ppeakp_4_4_ <= n3397; - \[14360] <= n3401; - \[14375] <= n3406; - \[14390] <= n3411; - \[14405] <= n3416; - \[14420] <= n3421; - \[14435] <= n3426; - \[14450] <= n3431; - \[14465] <= n3436; - \[14480] <= n3441; - \[14495] <= n3446; - \[14510] <= n3451; - \[14525] <= n3456; - \[14540] <= n3461; - \[14555] <= n3466; - \[14570] <= n3471; - \[14585] <= n3476; - \[14600] <= n3481; - \[14615] <= n3486; - \[14630] <= n3491; - \[14660] <= n3496; - \[14675] <= n3501; - \[14690] <= n3506; - \[14705] <= n3511; - ppeakb_8_8_ <= n3516; - ppeaka_13_13_ <= n3520; - ppeaka_2_2_ <= n3524; - \[14765] <= n3528; - ppeaks_9_9_ <= n3533; - ppeakp_14_14_ <= n3537; - \[14810] <= n3541; - \[14825] <= n3546; - \[14840] <= n3551; - \[14855] <= n3556; - \[14870] <= n3561; - \[14885] <= n3566; - \[14900] <= n3571; - \[14915] <= n3576; - \[14930] <= n3581; - \[14960] <= n3586; - \[14975] <= n3591; - \[14990] <= n3596; - \[15005] <= n3601; - \[15020] <= n3606; - \[15035] <= n3611; - \[15050] <= n3616; - \[15065] <= n3621; - \[15080] <= n3626; - ppeakb_9_9_ <= n3631; - ppeaka_12_12_ <= n3635; - ppeaka_3_3_ <= n3639; - \[15140] <= n3643; - ppeaks_8_8_ <= n3648; - ppeakp_15_15_ <= n3652; - \[15185] <= n3656; - \[15200] <= n3661; - \[15215] <= n3666; - \[15230] <= n3671; - \[15245] <= n3676; - \[15260] <= n3681; - \[15275] <= n3686; - \[15290] <= n3691; - \[15305] <= n3696; - \[15320] <= n3701; - \[15335] <= n3706; - \[15350] <= n3711; - \[15365] <= n3716; - \[15380] <= n3721; - \[15395] <= n3726; - \[15410] <= n3731; - \[15425] <= n3736; - \[15440] <= n3741; - ppeakb_6_6_ <= n3746; - ppeaka_15_15_ <= n3750; - ppeaka_4_4_ <= n3754; - \[15500] <= n3758; - \[15515] <= n3763; - ppeaks_0_0_ <= n3768; - \[15545] <= n3772; - \[15560] <= n3777; - \[15575] <= n3782; - \[15590] <= n3787; - \[15605] <= n3792; - \[15620] <= n3797; - \[15635] <= n3802; - \[15650] <= n3807; - \[15665] <= n3812; - \[15680] <= n3817; - \[15695] <= n3822; - \[15710] <= n3827; - \[15725] <= n3832; - \[15755] <= n3837; - \[15770] <= n3842; - \[15785] <= n3847; - ppeakb_7_7_ <= n3852; - ppeaka_14_14_ <= n3856; - ppeaka_5_5_ <= n3860; - \[15845] <= n3864; - \[15860] <= n3869; - ppeaks_10_10_ <= n3874; - \[15890] <= n3878; - \[15905] <= n3883; - \[15920] <= n3888; - \[15935] <= n3893; - \[15950] <= n3898; - \[15965] <= n3903; - \[15980] <= n3908; - \[15995] <= n3913; - \[16010] <= n3918; - \[16025] <= n3923; - \[16040] <= n3928; - \[16055] <= n3933; - \[16070] <= n3938; - \[16085] <= n3943; - \[16100] <= n3948; - paddress_8_8_ <= n3953; - \[16907] <= n3957; - \[16920] <= n3962; - \[16933] <= n3967; - paddress_9_9_ <= n3972; - \[16959] <= n3976; - \[16972] <= n3981; - \[16985] <= n3986; - \[16998] <= n3991; - \[17011] <= n3996; - \[17024] <= n4001; - \[17037] <= n4006; - \[17050] <= n4011; - \[17063] <= n4016; - \[17076] <= n4021; - \[17089] <= n4026; - \[17102] <= n4031; - \[17115] <= n4036; - \[17128] <= n4041; - \[17141] <= n4046; - \[17154] <= n4051; - \[17167] <= n4056; - \[17180] <= n4061; - \[17193] <= n4066; - \[17206] <= n4071; - \[17219] <= n4076; - \[17232] <= n4081; - \[17245] <= n4086; - \[17258] <= n4091; - \[17271] <= n4096; - \[17284] <= n4101; - \[17297] <= n4106; - \[17310] <= n4111; - \[17323] <= n4116; - \[17336] <= n4121; - \[17349] <= n4126; - \[17362] <= n4131; - \[17375] <= n4136; - \[17388] <= n4141; - paddress_11_11_ <= n4146; - \[17414] <= n4150; - \[17427] <= n4155; - \[17453] <= n4160; - paddress_10_10_ <= n4165; - \[17479] <= n4169; - \[17492] <= n4174; - \[17505] <= n4179; - \[17518] <= n4184; - \[17531] <= n4189; - \[17544] <= n4194; - paddress_13_13_ <= n4199; - \[17570] <= n4203; - \[17583] <= n4208; - \[17596] <= n4213; - \[17609] <= n4218; - paddress_12_12_ <= n4223; - \[17635] <= n4227; - \[17648] <= n4232; - \[17661] <= n4237; - \[17674] <= n4242; - paddress_15_15_ <= n4247; - \[17700] <= n4251; - \[17713] <= n4256; - paddress_14_14_ <= n4261; - \[17739] <= n4265; - \[17752] <= n4270; - \[17765] <= n4275; - \[17778] <= n4280; - \[17791] <= n4285; - \[17804] <= n4290; - \[17817] <= n4295; - pwr_0_0_ <= n4300; - \[17843] <= n4304; - \[17856] <= n4309; - \[17869] <= n4314; - \[17882] <= n4319; - prd_0_0_ <= n4324; - \[17908] <= n4328; - \[17921] <= n4333; - \[17934] <= n4338; - \[17947] <= n4343; - \[17960] <= n4348; - \[17973] <= n4353; - \[17986] <= n4358; - \[17999] <= n4363; - \[18012] <= n4368; - \[18025] <= n4373; - \[18038] <= n4378; - pdn <= n4383; - \[18064] <= n4387; - \[18077] <= n4392; - \[18090] <= n4397; - \[18103] <= n4402; - \[18116] <= n4407; - \[18129] <= n4412; - \[18142] <= n4417; - \[18155] <= n4422; - \[18168] <= n4427; - \[18181] <= n4432; - \[18194] <= n4437; - \[18207] <= n4442; - \[18220] <= n4447; - \[18233] <= n4452; - \[18246] <= n4457; - paddress_0_0_ <= n4462; - piack_0_0_ <= n4466; - \[18285] <= n4470; - \[18298] <= n4475; - \[18311] <= n4480; - paddress_1_1_ <= n4485; - \[18337] <= n4489; - \[18350] <= n4494; - \[18363] <= n4499; - \[18376] <= n4504; - \[18389] <= n4509; - paddress_2_2_ <= n4514; - \[18415] <= n4518; - \[18428] <= n4523; - \[18441] <= n4528; - paddress_3_3_ <= n4533; - \[18467] <= n4537; - \[18480] <= n4542; - \[18493] <= n4547; - \[18506] <= n4552; - paddress_4_4_ <= n4557; - paddress_5_5_ <= n4561; - \[18545] <= n4565; - paddress_6_6_ <= n4570; - \[18571] <= n4574; - \[18584] <= n4579; - \[18597] <= n4584; - \[18610] <= n4589; - paddress_7_7_ <= n4594; - \[18636] <= n4598; - end -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/misex3/misex3.v b/fpga_flow/benchmarks/Verilog/MCNC/misex3/misex3.v deleted file mode 100644 index 95f1ee6e6..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/misex3/misex3.v +++ /dev/null @@ -1,805 +0,0 @@ -// Benchmark "TOP" written by ABC on Mon Feb 4 17:32:57 2019 - -module misex3 ( - a, b, c, d, e, f, g, h, i, j, k, l, m, n, - r2, s2, t2, u2, n2, o2, p2, q2, h2, i2, j2, k2, m2, l2 ); - input a, b, c, d, e, f, g, h, i, j, k, l, m, n; - output r2, s2, t2, u2, n2, o2, p2, q2, h2, i2, j2, k2, m2, l2; - wire n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, - n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, - n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, - n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, - n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, - n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, - n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, - n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, - n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, - n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, - n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, - n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, - n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, - n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, - n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, - n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, - n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, - n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, - n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, - n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, - n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, - n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, - n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, - n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, - n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, - n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, - n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, - n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, - n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, - n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, - n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, - n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, - n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, - n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, - n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, - n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, - n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, - n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, - n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, - n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, - n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, - n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, - n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, - n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, - n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, - n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, - n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, - n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, - n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, - n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, - n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, - n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, - n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, - n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, - n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, - n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, - n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, - n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, - n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, - n758, n759, n760, n761, n762; - assign r2 = ~n293; - assign s2 = ~n74; - assign t2 = ~n217; - assign u2 = ~n148; - assign n2 = ~n68; - assign o2 = ~n62; - assign p2 = ~n388; - assign q2 = ~n349; - assign h2 = ~n56; - assign i2 = ~n569; - assign j2 = ~n55; - assign k2 = ~n50; - assign m2 = ~n456; - assign l2 = ~n757 | ~n759 | n46 | ~n747 | n44 | n45 | n42 | n43; - assign n42 = f & (~n680 | ~n739 | ~n740); - assign n43 = ~f & (n475 | n476 | ~n735); - assign n44 = ~n & (~n722 | ~n724 | ~n728); - assign n45 = n & (~n518 | ~n730 | ~n731); - assign n46 = n548 | ~n744 | n544 | n547 | n542 | ~n543 | ~n540 | n541; - assign n47 = n675 | n676 | n372 | i | l; - assign n48 = n438 | n549 | n189; - assign n49 = n434 & n662 & n661 & n51 & n437 & n439; - assign n50 = n49 & n47 & n48; - assign n51 = n657 & n573 & n656 & n431 & n425 & n428; - assign n52 = n443 & n442 & n440 & n441; - assign n53 = n675 | n189 | n438; - assign n54 = n179 | n480 | n550 | n551; - assign n55 = n54 & n53 & n51 & n52; - assign n56 = n579 & n578 & n577 & n576 & n575 & n574 & n572 & n573; - assign n57 = (n95 | n408) & (n409 | n88); - assign n58 = n96 | n121; - assign n59 = n648 & ~n404 & n361 & n402; - assign n60 = n83 | n317; - assign n61 = (n362 | n300) & (n363 | n426); - assign n62 = ~n416 & ~n415 & ~n414 & n61 & n60 & n59 & n57 & n58; - assign n63 = j | n243 | n119 | n591; - assign n64 = (n177 | n362) & (n684 | n409); - assign n65 = ~n297 & (n95 | n253 | n298); - assign n66 = n620 & n619 & n572 & n618 & n617 & n69 & n574 & n211; - assign n67 = ~n422 & (n591 | (n710 & n711)); - assign n68 = ~n420 & ~n419 & n67 & n66 & n65 & n64 & n59 & n63; - assign n69 = n92 | n407 | n91; - assign n70 = n595 | n92; - assign n71 = n264 | ~d | n248; - assign n72 = n701 & (n236 | n79); - assign n73 = n232 & (n152 | n632); - assign n74 = ~n267 & ~n266 & ~n265 & n73 & n72 & n71 & n69 & n70; - assign n75 = ~h | ~k; - assign n76 = n75 | l; - assign n77 = n623 | ~n658; - assign n78 = ~n167 & (n77 | ~n586); - assign n79 = ~c | n459; - assign n80 = e | n521; - assign n81 = n612 & n302; - assign n82 = n81 & n79 & n80; - assign n83 = ~k | n199; - assign n84 = m | j | ~l; - assign n85 = n83 & (~n | n84); - assign n86 = n684 | n83; - assign n87 = (n192 | n605) & (n206 | n604); - assign n88 = ~g | n603; - assign n89 = n86 & n87 & (n85 | n88); - assign n90 = (n110 | n156) & (n113 | n275); - assign n91 = ~i | n538; - assign n92 = ~a | n521; - assign n93 = n90 & (n91 | n92); - assign n94 = ~g | n600; - assign n95 = n285 & n397; - assign n96 = ~k | n167; - assign n97 = n96 | n94 | n95; - assign n98 = n601 | n199; - assign n99 = ~i | n368; - assign n100 = n98 & (~n | n99); - assign n101 = ~h | n538; - assign n102 = ~n | n129; - assign n103 = h | n538; - assign n104 = (n100 | n103) & (n101 | n102); - assign n105 = ~g | n249; - assign n106 = h | n197; - assign n107 = (n100 | n106) & (n102 | n105); - assign n108 = ~k | n179; - assign n109 = n108 & (n | n84); - assign n110 = n608 & n287 & n607; - assign n111 = (n101 | n92) & (n110 | n105); - assign n112 = n135 | n119; - assign n113 = n218 & n295; - assign n114 = ~g | n393; - assign n115 = n112 & n111 & (n113 | n114); - assign n116 = (n110 | n164) & (n113 | n189); - assign n117 = e | n609; - assign n118 = n116 & (n92 | n117); - assign n119 = ~a | n271; - assign n120 = ~e | n609; - assign n121 = n118 & (n119 | n120); - assign n122 = (n110 | n106) & (n113 | n202); - assign n123 = n122 & (n92 | n103); - assign n124 = n153 | n399; - assign n125 = ~n610 | ~g | n237; - assign n126 = j | n154; - assign n127 = ~i | n609; - assign n128 = n124 & n125 & (n126 | n127); - assign n129 = n401 & n512 & n527 & n760; - assign n130 = (n106 | n99) & (n129 | n105); - assign n131 = n519 | ~i | n121; - assign n132 = (n123 | n588) & (n95 | n128); - assign n133 = ~e | n271; - assign n134 = n131 & n132 & (n130 | n133); - assign n135 = ~h | n243; - assign n136 = h | n243; - assign n137 = (n100 | n136) & (n135 | n102); - assign n138 = ~n137 & (~n625 | (b & ~n479)); - assign n139 = ~n89 & (~n325 | ~n606); - assign n140 = ~n167 & (~n683 | (~n121 & ~n601)); - assign n141 = ~n95 & (~n687 | (~n96 & ~n127)); - assign n142 = n133 | n601 | n179 | n106; - assign n143 = n590 | n591; - assign n144 = n136 | n587 | n588; - assign n145 = ~n139 & ~n140 & (n | n134); - assign n146 = (n93 | n591) & (n104 | n616); - assign n147 = n688 & (n107 | n269); - assign n148 = n147 & n146 & n145 & n144 & n143 & n142 & n66 & ~n138; - assign n149 = n689 | n108; - assign n150 = (n372 | n193) & (n613 | n624); - assign n151 = ~f | n603; - assign n152 = n149 & n150 & (n109 | n151); - assign n153 = ~m | n611; - assign n154 = ~l | ~m; - assign n155 = n153 & (i | n154); - assign n156 = ~i | n197; - assign n157 = j | n197; - assign n158 = n156 & n157; - assign n159 = (n155 | n105) & (n158 | n589); - assign n160 = n690 & (n164 | n126); - assign n161 = n644 & n647; - assign n162 = i | n197; - assign n163 = n159 & n160 & (n161 | n162); - assign n164 = g | n249; - assign n165 = (n164 | n96) & (n | n163); - assign n166 = n75 | ~m | n; - assign n167 = ~m | n; - assign n168 = ~l | ~h | j; - assign n169 = n166 & (n167 | n168); - assign n170 = ~f | n243; - assign n171 = ~e | n196; - assign n172 = (n169 | n171) & (~n78 | n170); - assign n173 = n196 | d | n169; - assign n174 = d | n197; - assign n175 = n173 & (~n78 | n174); - assign n176 = j | n75; - assign n177 = n176 & (i | n75); - assign n178 = n299 & n300 & n76 & n177; - assign n179 = m | n; - assign n180 = j | n603; - assign n181 = ~l | n179; - assign n182 = (n180 | n181) & (n178 | n179); - assign n183 = ~e | n615; - assign n184 = ~n | n183; - assign n185 = (n99 | n184) & (n98 | n183); - assign n186 = ~n184 & ~n761 & (~n114 | ~n189); - assign n187 = ~n186 & (n185 | (n202 & n676)); - assign n188 = n183 | n391; - assign n189 = g | n393; - assign n190 = n187 & (n188 | (n114 & n189)); - assign n191 = (n206 | n624) & (n689 | n83); - assign n192 = k | n199; - assign n193 = ~j | n249; - assign n194 = n191 & (n192 | n193); - assign n195 = n194 & (n85 | n151); - assign n196 = ~f | g; - assign n197 = ~f | ~g; - assign n198 = (n169 | n196) & (~n78 | n197); - assign n199 = m | ~n; - assign n200 = ~l | n199; - assign n201 = (n180 | n200) & (n178 | n199); - assign n202 = h | n570; - assign n203 = (n100 | n202) & (n102 | n114); - assign n204 = n203 & (n201 | (n170 & n171)); - assign n205 = n691 & n692 & (n85 | n314); - assign n206 = l | n199; - assign n207 = ~k | n393; - assign n208 = n89 & n205 & (n206 | n207); - assign n209 = ~n152 & (~n133 | ~n430); - assign n210 = n595 | n599; - assign n211 = n595 | n353; - assign n212 = n693 & (~e | n195 | n324); - assign n213 = ~n209 & (n285 | (n165 & n595)); - assign n214 = n208 | n315; - assign n215 = (n172 | n119) & (n175 | n287); - assign n216 = n694 & (n182 | n302); - assign n217 = n216 & n190 & n215 & n214 & n213 & n212 & n210 & n211; - assign n218 = ~a | n560; - assign n219 = n167 | n218; - assign n220 = (n168 | n219) & (n218 | n166); - assign n221 = ~n658 | ~n586 | n623; - assign n222 = ~f & ~n538; - assign n223 = ~n219 & n221 & (n222 | ~n261); - assign n224 = e | n488; - assign n225 = e | n196; - assign n226 = ~n223 & (n220 | (n224 & n225)); - assign n227 = n393 | ~j | n372; - assign n228 = (n613 | n207) & (n109 | n314); - assign n229 = n640 & n643; - assign n230 = n227 & n228 & (n229 | n108); - assign n231 = ~e | n626; - assign n232 = n190 & n226 & (n230 | n231); - assign n233 = ~n83 & (~n252 | ~n639); - assign n234 = (n192 | n322) & (n256 | n206); - assign n235 = g | n603; - assign n236 = ~n233 & n234 & (n85 | n235); - assign n237 = k | n154; - assign n238 = (i | n161) & (~j | n237); - assign n239 = ~n591 & (~n91 | (~j & ~n538)); - assign n240 = ~n239 & (n | (n699 & n700)); - assign n241 = n165 & n240 & (n96 | n117); - assign n242 = ~i | n243; - assign n243 = ~e | ~g; - assign n244 = n242 & (j | n243); - assign n245 = n96 | n120; - assign n246 = n697 & (n120 | n126); - assign n247 = n696 & n695 & (n244 | n589); - assign n248 = n245 & (n | (n246 & n247)); - assign n249 = ~f | ~h; - assign n250 = n249 | n102 | e; - assign n251 = n629 & n88; - assign n252 = j | n609; - assign n253 = i | n602; - assign n254 = ~g | n360; - assign n255 = n254 & n253 & n251 & n252; - assign n256 = g | n75; - assign n257 = n698 & (n376 | (n628 & n649)); - assign n258 = (n94 | n96) & (n629 | n630); - assign n259 = ~l | n167; - assign n260 = n257 & n258 & (n255 | n259); - assign n261 = ~f | n538; - assign n262 = (n169 | n225) & (~n78 | n261); - assign n263 = ~n260 & (~n655 | (d & ~n524)); - assign n264 = a | ~b; - assign n265 = ~n201 & (~n325 | (~n261 & ~n616)); - assign n266 = ~n352 & (~n262 | n263); - assign n267 = ~n526 & (~n250 | (~n100 & ~n631)); - assign n268 = n344 & (n83 | n633); - assign n269 = ~b | n598; - assign n270 = n268 & (n194 | n269); - assign n271 = ~c | d; - assign n272 = n79 & (~f | n271); - assign n273 = (n100 | n634) & (n164 | n102); - assign n274 = n273 & n107; - assign n275 = ~i | n570; - assign n276 = j | n570; - assign n277 = n275 & n276; - assign n278 = (n155 | n114) & (n277 | n589); - assign n279 = n749 & (n189 | n126); - assign n280 = i | n570; - assign n281 = n278 & n279 & (n161 | n280); - assign n282 = (n96 | n189) & (n | n281); - assign n283 = n286 | g | n169; - assign n284 = n283 & (d | ~n78 | n243); - assign n285 = ~e | n264; - assign n286 = d | ~e; - assign n287 = c | ~a | ~b; - assign n288 = n285 & (n286 | n287); - assign n289 = (n236 | n635) & (n104 | n616); - assign n290 = (n260 | n288) & (n284 | ~n545); - assign n291 = n107 | n315; - assign n292 = (n182 | n272) & (n274 | n625); - assign n293 = n292 & n291 & n290 & n289 & n270 & n232; - assign n294 = n123 & (n119 | n136); - assign n295 = n596 & n594; - assign n296 = n112 & n111 & (n295 | n114); - assign n297 = ~n636 & (~n355 | (~n167 & ~n296)); - assign n298 = n | n126; - assign n299 = ~h | n360; - assign n300 = ~k | n603; - assign n301 = n180 & n300 & n299 & n176; - assign n302 = ~c | n524; - assign n303 = n302 & (~c | n196); - assign n304 = (n113 | n646) & (~j | n645); - assign n305 = ~j | n197; - assign n306 = n304 & (n110 | n305); - assign n307 = n121 & (n95 | n94); - assign n308 = ~n95 & ~n644 & (~n88 | ~n660); - assign n309 = ~n308 & (n329 | n339 | n435); - assign n310 = (n118 | n126) & (n306 | n237); - assign n311 = ~l | n519; - assign n312 = n309 & n310 & (n307 | n311); - assign n313 = n183 & n390; - assign n314 = f | n603; - assign n315 = ~b | n286; - assign n316 = (n314 | n315) & (n313 | n235); - assign n317 = n633 & n316; - assign n318 = (n80 & (~n | n371)) | (n & n371); - assign n319 = (n88 | n318) & (~n | n317); - assign n320 = n393 | ~j | n315; - assign n321 = n269 | n193; - assign n322 = ~j | n609; - assign n323 = n320 & n321 & (n313 | n322); - assign n324 = b | ~c; - assign n325 = ~f | n324; - assign n326 = (n315 | n643) & (n313 | n252); - assign n327 = j | n249; - assign n328 = n326 & (n269 | n327); - assign n329 = ~h | n621; - assign n330 = n328 & (n325 | n329); - assign n331 = (n316 | n84) & (n330 | n435); - assign n332 = m | k | ~l; - assign n333 = n331 & (n323 | n332); - assign n334 = (n315 | n640) & (n313 | n639); - assign n335 = i | n249; - assign n336 = n334 & (n269 | n335); - assign n337 = ~n199 & (~n336 | (~n253 & ~n371)); - assign n338 = ~n337 & (n80 | n179 | n253); - assign n339 = n303 & n637; - assign n340 = (n339 | n181) & (n325 | n200); - assign n341 = ~n318 & (~n704 | (~n332 & ~n605)); - assign n342 = n243 | n490 | ~j | n119; - assign n343 = n298 | n119 | n120; - assign n344 = n633 | ~n | n84; - assign n345 = n705 & (n301 | n340); - assign n346 = n65 & (n319 | n435); - assign n347 = (n312 & (~n | n333)) | (n & n333); - assign n348 = (n682 | n641) & (n338 | n433); - assign n349 = n348 & n347 & n346 & n345 & n344 & n343 & ~n341 & n342; - assign n350 = (n113 | n280) & (i | n645); - assign n351 = n350 & (n110 | n162); - assign n352 = ~a | n324; - assign n353 = ~b | n597; - assign n354 = n353 & n287 & n352; - assign n355 = n114 | n219; - assign n356 = (n599 | n105) & (n295 | n114); - assign n357 = n112 & (n92 | (n105 & n101)); - assign n358 = n355 & (n167 | (n356 & n357)); - assign n359 = n707 & (n285 | n630 | n605); - assign n360 = ~j | k; - assign n361 = n359 & (n358 | n360); - assign n362 = (n339 | n179) & (n325 | n199); - assign n363 = (n339 | n108) & (n325 | n83); - assign n364 = ~n88 & (~n706 | (~n167 & ~n433)); - assign n365 = ~n364 & (n629 | (n259 & n630)); - assign n366 = n365 & (n96 | n322); - assign n367 = n519 | n | n121; - assign n368 = ~k | m; - assign n369 = (n253 | n318) & (~n | n336); - assign n370 = n367 & (n368 | (n369 & n319)); - assign n371 = n395 & n315 & n606; - assign n372 = k | n179; - assign n373 = (n372 | n80) & (n371 | n192); - assign n374 = ~i | k | ~l | n167; - assign n375 = ~k | ~n610; - assign n376 = l | n167; - assign n377 = n374 & (n375 | (n376 & n259)); - assign n378 = ~j | n603; - assign n379 = n378 & n329; - assign n380 = n644 | n587 | n627; - assign n381 = n647 | n587 | n627; - assign n382 = n351 | n | n161; - assign n383 = (n294 | n377) & (n363 | n379); - assign n384 = n373 | n605; - assign n385 = (n95 | n366) & (~j | n370); - assign n386 = n362 | n299; - assign n387 = n361 & (n323 | n192); - assign n388 = n387 & n386 & n385 & n384 & n383 & n382 & n380 & n381; - assign n389 = ~n372 & (~n303 | ~n637); - assign n390 = n635 & n638; - assign n391 = ~n | n401; - assign n392 = n188 & (n390 | n391); - assign n393 = f | ~h; - assign n394 = (n393 | n315) & (n249 | n269); - assign n395 = n616 & n625; - assign n396 = e | n324; - assign n397 = ~b | n524; - assign n398 = n397 & n396 & n395 & n315; - assign n399 = ~i | n602; - assign n400 = (n398 | n399) & (~i | n394); - assign n401 = m | n360; - assign n402 = n399 | n | n80 | n401; - assign n403 = h & n610; - assign n404 = n403 & (n389 | (~n192 & ~n325)); - assign n405 = n253 | n641; - assign n406 = (n256 | n167) & (n376 | n176); - assign n407 = n | n592; - assign n408 = n405 & n406 & (n407 | n399); - assign n409 = (n108 | n80) & (n371 | n83); - assign n410 = i & ~n394; - assign n411 = n & (n410 | (~n127 & ~n313)); - assign n412 = j | i; - assign n413 = n412 | ~k | n259; - assign n414 = ~n115 & (~n413 | (n77 & ~n167)); - assign n415 = ~n527 & (n411 | (~n318 & ~n399)); - assign n416 = ~n591 & (~n709 | (~n110 & ~n327)); - assign n417 = ~n433 & (~n351 | (~n119 & ~n627)); - assign n418 = ~n311 & ~n & ~n251; - assign n419 = ~n95 & (n418 | (~n376 & ~n649)); - assign n420 = ~n83 & (~n328 | ~n336); - assign n421 = i & k; - assign n422 = ~n167 & (n417 | (~n294 & n421)); - assign n423 = n654 | ~f | n598; - assign n424 = j | k; - assign n425 = n259 | n399 | n423 | n424; - assign n426 = ~h | n600; - assign n427 = n651 | ~n | n557; - assign n428 = n427 | n426 | n332; - assign n429 = n650 | n114 | n181; - assign n430 = ~e | n521; - assign n431 = n429 | n430; - assign n432 = ~n545 | n655; - assign n433 = ~l | ~j | ~k; - assign n434 = n399 | n167 | n432 | n433; - assign n435 = ~l | n368; - assign n436 = n170 | n526; - assign n437 = n436 | ~n403 | n435; - assign n438 = n181 | n375; - assign n439 = n438 | n231 | n105; - assign n440 = n652 | n202 | n632; - assign n441 = ~n653 | n435 | n445; - assign n442 = n181 | n202 | n430 | ~n473; - assign n443 = n712 & (n332 | n427 | n378); - assign n444 = n106 | n613 | n231 | n658; - assign n445 = h | n621; - assign n446 = m | k | l; - assign n447 = n444 & (n436 | n445 | n446); - assign n448 = n551 | n | n446; - assign n449 = n448 & (n179 | n127 | n433); - assign n450 = k | n189 | n181 | n632; - assign n451 = n332 | n651 | ~h | n224; - assign n452 = n450 & n451; - assign n453 = n641 | n654 | n660 | n477; - assign n454 = n105 | n181 | n549 | n650; - assign n455 = (n449 | n480) & (n452 | n412); - assign n456 = n455 & n454 & n453 & n49 & n52 & n447; - assign n457 = i | n179; - assign n458 = (~k | n457) & (n179 | ~n412); - assign n459 = e | ~f; - assign n460 = a | n526; - assign n461 = j & ~n630 & (n459 | n460); - assign n462 = ~n758 & (~h | n438 | ~n479); - assign n463 = f | ~c | e; - assign n464 = ~n461 & n462 & (n458 | n463); - assign n465 = b | n199; - assign n466 = n200 & n83 & n465 & n298; - assign n467 = (b | n200) & (c | n181); - assign n468 = ~n167 & (~n737 | (~b & ~n479)); - assign n469 = h | j | n199; - assign n470 = (j | n83) & (~i | n663); - assign n471 = ~j | n199; - assign n472 = n469 & n470 & (~h | n471); - assign n473 = ~k & n610; - assign n474 = n473 & b & ~n199; - assign n475 = ~h & (n474 | (~i & ~n206)); - assign n476 = ~n673 & (~n521 | (~e & n324)); - assign n477 = f | n659; - assign n478 = n477 & (f | a | e); - assign n479 = c | d; - assign n480 = f | n479; - assign n481 = n669 | c | e; - assign n482 = b | e | ~n | n669; - assign n483 = n375 | ~n615 | ~h | n259; - assign n484 = (d | n734) & (n457 | n480); - assign n485 = n199 | n675; - assign n486 = ~n762 & n485 & n484 & n483 & n481 & n482; - assign n487 = c & ~n655; - assign n488 = f | g; - assign n489 = b | n488; - assign n490 = n | n237; - assign n491 = (j | n490) & (n199 | ~n626); - assign n492 = ~n199 & (~n741 | (~j & ~n525)); - assign n493 = n742 & (n670 | n671); - assign n494 = ~n492 & ~n756 & (i | n491); - assign n495 = n493 & n494 & (n457 | n271); - assign n496 = c | n488; - assign n497 = n664 & n463; - assign n498 = (n106 | n231) & (~j | n497); - assign n499 = (n716 | n167) & (n498 | n179); - assign n500 = n496 | n372; - assign n501 = (n527 | n671) & (n719 | n613); - assign n502 = n718 & (n436 | (n206 & n192)); - assign n503 = n502 & n501 & n499 & n500; - assign n504 = ~j & ~n372 & (~n271 | ~n302); - assign n505 = (b | n199) & (c | n179); - assign n506 = ~b | ~e | ~n | n666; - assign n507 = e | n505 | n650; - assign n508 = (n525 | n471) & (n457 | n479); - assign n509 = n478 | n167; - assign n510 = ~n626 | j | n192; - assign n511 = n510 & n509 & n508 & n507 & ~n504 & n506; - assign n512 = i | n368; - assign n513 = m | n603; - assign n514 = i | m; - assign n515 = n512 & n513 & (~l | n514); - assign n516 = n253 & n127; - assign n517 = (n426 | n446) & (n516 | n666); - assign n518 = n517 & (n401 | n151); - assign n519 = ~k | ~m; - assign n520 = n519 & (j | ~m); - assign n521 = c | ~d; - assign n522 = n81 & (g | n521); - assign n523 = ~n311 & n403 & (~n174 | ~n261); - assign n524 = ~e | f; - assign n525 = b | n524; - assign n526 = ~d | n615; - assign n527 = j | n368; - assign n528 = n99 & n527; - assign n529 = n717 & (h | n524 | n636); - assign n530 = (n521 | n525) & (~j | n716); - assign n531 = (i | n432) & (n254 | n665); - assign n532 = n634 & n550 & (n135 | n650); - assign n533 = n532 & n531 & n529 & n530; - assign n534 = ~c & ~n524; - assign n535 = (~n180 | ~n628) & (~n463 | n534); - assign n536 = ~j & (~n660 | (~n156 & ~n231)); - assign n537 = n396 & (a | c | e); - assign n538 = e | ~g; - assign n539 = ~n162 & (~n108 | ~n181); - assign n540 = n375 | n259 | n114; - assign n541 = ~n489 & (~n206 | ~n663); - assign n542 = ~n613 & (~n497 | (~c & ~n660)); - assign n543 = n438 | n101; - assign n544 = ~n231 & (n539 | (~n156 & ~n613)); - assign n545 = a & ~n615; - assign n546 = n545 & ~n655 & (~n630 | ~n672); - assign n547 = ~n457 & (~n631 | (~n105 & ~n231)); - assign n548 = ~n179 & (n535 | n536 | ~n715); - assign n549 = ~e | n479; - assign n550 = l | n424; - assign n551 = i | g | h; - assign n552 = n112 | n155 | n; - assign n553 = n119 | n245; - assign n554 = f | n167; - assign n555 = (n168 | n554) & (f | n166); - assign n556 = n555 | ~e | g; - assign n557 = f | n243; - assign n558 = n556 & (~n78 | n557); - assign n559 = ~n99 & ~g & n; - assign n560 = ~b | ~d; - assign n561 = (n203 | n560) & (n526 | ~n748); - assign n562 = (n175 | n287) & (n282 | n594); - assign n563 = n236 | n638; - assign n564 = (n352 | n558) & (~e | n561); - assign n565 = n608 | n172; - assign n566 = n677 & n553 & n552 & n342 & n143 & n63; - assign n567 = n226 & n270 & (n89 | n625); - assign n568 = n750 & n752 & n656 & n661 & n441 & n657 & n440 & n662; - assign n569 = n568 & n567 & n447 & n566 & n565 & n564 & n562 & n563; - assign n570 = f | ~g; - assign n571 = (g | n555) & (~n78 | n570); - assign n572 = n595 | n352; - assign n573 = n652 | n106 | n549; - assign n574 = n593 | n596; - assign n575 = n626 | ~a | n262; - assign n576 = n571 | ~d | ~n545; - assign n577 = n753 & (n654 | (n175 & n248)); - assign n578 = n282 | n596; - assign n579 = n566 & (n165 | n352); - assign n580 = l | ~n421; - assign n581 = ~l | ~h | i; - assign n582 = (~l & n622) | (n603 & (l | n622)); - assign n583 = ~h | n611; - assign n584 = ~l | n360; - assign n585 = ~l | n621; - assign n586 = n585 & n584 & n583 & n582 & n580 & n581; - assign n587 = n | n119; - assign n588 = ~i | n154; - assign n589 = l | n519; - assign n590 = n119 | n242; - assign n591 = n | n589; - assign n592 = j | n519; - assign n593 = n407 | n275; - assign n594 = ~a | n286; - assign n595 = n156 | n407; - assign n596 = ~e | ~a | ~c; - assign n597 = d | a; - assign n598 = ~d | e; - assign n599 = ~a | n598; - assign n600 = ~i | j; - assign n601 = ~l | n600; - assign n602 = ~g | ~h; - assign n603 = h | ~i; - assign n604 = ~g | n75; - assign n605 = ~j | n602; - assign n606 = n396 & n397; - assign n607 = n599 & n353; - assign n608 = n92 & n352; - assign n609 = g | ~h; - assign n610 = i & j; - assign n611 = ~j | l; - assign n612 = ~f | n521; - assign n613 = l | n179; - assign n614 = ~g | ~n421; - assign n615 = ~b | ~c; - assign n616 = d | n615; - assign n617 = n590 | n407; - assign n618 = n593 | n594; - assign n619 = n97 & n70 & n210; - assign n620 = (n595 | n287) & (n593 | n218); - assign n621 = i | ~j; - assign n622 = j | ~k; - assign n623 = k & ~n600; - assign n624 = ~k | n249; - assign n625 = ~b | n521; - assign n626 = ~c | ~d; - assign n627 = i | n243; - assign n628 = n614 & n605; - assign n629 = ~g | n621; - assign n630 = k | n167; - assign n631 = h | n459; - assign n632 = e | n626; - assign n633 = n269 | n151; - assign n634 = h | n196; - assign n635 = ~b | n459; - assign n636 = ~l | n412; - assign n637 = n612 & n272; - assign n638 = ~f | n560; - assign n639 = i | n609; - assign n640 = i | n393; - assign n641 = n622 | ~l | n167; - assign n642 = j | n602; - assign n643 = j | n393; - assign n644 = ~j | n154; - assign n645 = n538 | n92; - assign n646 = ~j | n570; - assign n647 = ~m | n360; - assign n648 = (n392 | n127) & (n400 | n391); - assign n649 = ~g | n622; - assign n650 = k | n600; - assign n651 = b | n626; - assign n652 = n621 | ~k | n181; - assign n653 = n222 & ~n526; - assign n654 = a | n615; - assign n655 = ~f | ~d | ~e; - assign n656 = ~n653 | n332 | n426; - assign n657 = n632 | n429; - assign n658 = k | n621; - assign n659 = d | e; - assign n660 = i | ~g | h; - assign n661 = n445 | n435 | n427; - assign n662 = n430 | n202 | n652; - assign n663 = n83 & n471; - assign n664 = ~g | n479; - assign n665 = a | n598; - assign n666 = m | n424; - assign n667 = ~h | n514; - assign n668 = k | n514; - assign n669 = h | n514; - assign n670 = m | n600; - assign n671 = n | n479; - assign n672 = h | n167; - assign n673 = g | n199; - assign n674 = h & ~n650; - assign n675 = e | n479; - assign n676 = h | n488; - assign n677 = n343 & n144 & n454 & n617 & n381 & n380; - assign n678 = (e & ~n119) | (~n92 & (~e | ~n119)); - assign n679 = (n479 & n674) | (~g & (~n479 | n674)); - assign n680 = n755 & (i | n466 | h); - assign n681 = ~n610 | l | n115; - assign n682 = n590 & n93; - assign n683 = n681 & (n682 | n584); - assign n684 = n642 & n253; - assign n685 = (n684 | n108) & (n109 | n88); - assign n686 = (n605 | n372) & (n604 | n613); - assign n687 = (n614 | n376) & (n88 | n259); - assign n688 = ~n141 & (n82 | (n685 & n686)); - assign n689 = n335 & n327; - assign n690 = (n588 | n106) & (n237 | n305); - assign n691 = n229 | n83; - assign n692 = n393 | ~j | n192; - assign n693 = ~a | b | ~d | n198; - assign n694 = (n607 | n165) & (n204 | n625); - assign n695 = (n161 | n627) & (n155 | n135); - assign n696 = n243 | ~j | n237; - assign n697 = (n588 | n136) & (n242 | n592); - assign n698 = n256 | n167; - assign n699 = (n155 | n101) & (n238 | n538); - assign n700 = (n588 | n103) & (n117 | n126); - assign n701 = (n182 | n612) & (n241 | n92); - assign n702 = ~n294 & (~n585 | (l & n610)); - assign n703 = ~n95 & (~n252 | ~n254 | ~n256); - assign n704 = (n84 | n88) & (n642 | n435); - assign n705 = (n167 | ~n702) & (n259 | ~n703); - assign n706 = n490 & (n96 | n611); - assign n707 = n354 | n360 | n167 | n105; - assign n708 = ~h | j; - assign n709 = (n113 | n643) & (~n678 | n708); - assign n710 = (n95 | n88) & (j | n645); - assign n711 = (n110 | n157) & (n113 | n276); - assign n712 = n167 | n127 | n584 | n423; - assign n713 = (d | n525) & (j | n436); - assign n714 = (b | c) & (n127 | n433); - assign n715 = (n253 | n463) & (n103 | ~n473); - assign n716 = n676 & n478; - assign n717 = a | b; - assign n718 = n433 | n487 | ~h | n199; - assign n719 = n496 & ~n534; - assign n720 = n478 & n665 & n432; - assign n721 = ~n523 & (g | n520 | n720); - assign n722 = n721 & (n670 | (n496 & n480)); - assign n723 = (n522 | n669) & (n164 | n666); - assign n724 = n723 & (n668 | (n202 & n664)); - assign n725 = n231 | n156 | n401; - assign n726 = n592 | n432; - assign n727 = n725 & n726 & (n719 | n667); - assign n728 = n518 & n727 & (n496 | n515); - assign n729 = (n436 | n667) & (n525 | n528); - assign n730 = n729 & (n515 | n436); - assign n731 = (n669 | n397) & (n525 | n668); - assign n732 = n526 | e | n472; - assign n733 = n672 | ~n597 | n636; - assign n734 = n754 & (~h | n438); - assign n735 = n732 & n733 & (~c | n734); - assign n736 = n | a | ~g; - assign n737 = (i | n665) & (~n545 | n659); - assign n738 = ~n468 & (n311 | ~n403 | n736); - assign n739 = n738 & (n665 | (n672 & n96)); - assign n740 = (n549 | n673) & (n179 | ~n679); - assign n741 = n489 & (e | n254); - assign n742 = ~n629 | k | n206; - assign n743 = ~n546 & (n537 | n554); - assign n744 = n743 & (n199 | (n714 & n713)); - assign n745 = (n720 | n376) & (n533 | n167); - assign n746 = (n192 | n327) & (~i | n503); - assign n747 = n745 & n746 & (n591 | n445); - assign n748 = ~h & (n559 | (~n601 & ~n673)); - assign n749 = (n588 | n202) & (n237 | n646); - assign n750 = n53 & n47 & n618; - assign n751 = n526 | n102 | n120; - assign n752 = n751 & (n651 | (n104 & n195)); - assign n753 = n449 | n480; - assign n754 = ~n473 | h | n179; - assign n755 = n467 | ~h | n375; - assign n756 = i & ~k & (~n376 | ~n613); - assign n757 = (n495 & (~h | n511)) | (h & n511); - assign n758 = ~h & (~n96 | (c & ~n457)); - assign n759 = (n464 & (~g | n486)) | (g & n486); - assign n760 = l | n368; - assign n761 = n760 & n512 & n527; - assign n762 = n674 & ~n167 & n460; -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/pdc/pdc.v b/fpga_flow/benchmarks/Verilog/MCNC/pdc/pdc.v deleted file mode 100644 index f1adc4cfa..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/pdc/pdc.v +++ /dev/null @@ -1,2558 +0,0 @@ -// Benchmark "TOP" written by ABC on Mon Feb 4 17:33:19 2019 - -module pdc ( - i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, - i_11_, i_12_, i_13_, i_14_, i_15_, - o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, - o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, - o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, - o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_ ); - input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, - i_10_, i_11_, i_12_, i_13_, i_14_, i_15_; - output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, - o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, - o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, - o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_; - wire n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, - n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, - n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, - n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, - n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, - n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, - n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, - n180, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, - n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, - n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, - n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, - n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, - n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, - n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, - n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, - n276, n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, - n288, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, - n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, - n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, - n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, - n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, - n348, n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, - n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, - n372, n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, - n384, n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, - n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, - n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, - n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, - n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, - n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, - n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, - n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, - n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, - n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, - n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, - n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, - n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, - n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, - n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, - n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, - n576, n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, - n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, - n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, - n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, - n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, - n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, - n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, - n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, - n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, - n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, - n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, - n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, - n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, - n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, - n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, - n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, - n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, - n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, - n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, - n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, - n816, n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, - n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, - n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, - n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, - n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, - n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, - n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, - n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, - n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, - n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, - n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, - n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, - n960, n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, - n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, - n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, - n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, - n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, - n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, - n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, - n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, - n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, - n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, - n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, - n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, - n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, - n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, - n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, - n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, - n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, - n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, - n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, - n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, - n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, - n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, - n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, - n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, - n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, - n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, - n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, - n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, - n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, - n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, - n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, - n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, - n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, - n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, - n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, - n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, - n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, - n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, - n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, - n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, - n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, - n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, - n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, - n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, - n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, - n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, - n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, - n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, - n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, - n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, - n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, - n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, - n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, - n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, - n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, - n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, - n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, - n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, - n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, - n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, - n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, - n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, - n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, - n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, - n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, - n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, - n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, - n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, - n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, - n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, - n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, - n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, - n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, - n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, - n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, - n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, - n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, - n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, - n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, - n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, - n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, - n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, - n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, - n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, - n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, - n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, - n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, - n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, - n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, - n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, - n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, - n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, - n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, - n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, - n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, - n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, - n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, - n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, - n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, - n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, - n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, - n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, - n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, - n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, - n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, - n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, - n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, - n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, - n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, - n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, - n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, - n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, - n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, - n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, - n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, - n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, - n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, - n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, - n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, - n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, - n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, - n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, - n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, - n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, - n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, - n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, - n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, - n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, - n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, - n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, - n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, - n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, - n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, - n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, - n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, - n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, - n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, - n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, - n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, - n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, - n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, - n2376, n2377, n2378, n2379, n2380, n2381; - assign o_0_ = ~n126 & (n124 | n161); - assign o_1_ = ~n126 & (n160 | ~n1042 | ~n1612); - assign o_2_ = ~n126 & (n158 | n159 | ~n714); - assign o_3_ = ~n126 & (~n2261 | ~n2266); - assign o_4_ = ~n126 & (~n2241 | ~n2250 | ~n2252); - assign o_5_ = ~n2380; - assign o_6_ = ~n157; - assign o_7_ = ~n126 & (n156 | ~n1365 | ~n1370); - assign o_8_ = ~n2379; - assign o_9_ = ~n126 & (n155 | ~n1984 | ~n1986); - assign o_10_ = ~n154; - assign o_11_ = ~n995; - assign o_12_ = ~n1187; - assign o_13_ = ~n1174; - assign o_14_ = ~n1353; - assign o_15_ = ~n152; - assign o_16_ = ~n126 & (~n2359 | ~n2361 | ~n2363); - assign o_17_ = ~n126 & (~n2347 | ~n2349 | ~n2351); - assign o_18_ = ~n126 & (~n2332 | ~n2334 | ~n2336); - assign o_19_ = ~n126 & (~n2318 | ~n2319 | ~n2320); - assign o_20_ = ~n126 & (~n2302 | ~n2304); - assign o_21_ = ~n151; - assign o_22_ = ~n927 | ~n1431 | n148 | n149; - assign o_23_ = ~n147; - assign o_24_ = ~n145; - assign o_25_ = ~n144; - assign o_26_ = ~n142; - assign o_27_ = n136 & ~n126 & n135; - assign o_28_ = ~n2378; - assign o_29_ = ~n126 & (~n866 | ~n2284 | ~n2285); - assign o_30_ = ~n134; - assign o_31_ = n132 | n130 | n131; - assign o_32_ = ~n129; - assign o_33_ = ~n2377; - assign o_34_ = ~n126 & (~n2280 | ~n2282); - assign o_35_ = ~n126 & (~n1622 | ~n1625 | ~n2278); - assign o_36_ = ~n128; - assign o_37_ = ~n126 & (n123 | n124 | n125); - assign o_38_ = n121 & ~n1251; - assign o_39_ = n121 & n122; - assign n96 = n1239 & n1264; - assign n97 = n1239 & n177; - assign n98 = n1228 & n1239; - assign n99 = ~n361 | ~n1373; - assign n100 = n98 & (n99 | ~n617); - assign n101 = n96 & (~n564 | ~n926); - assign n102 = ~n617 | ~n1176; - assign n103 = n96 & (n102 | ~n361); - assign n104 = n1252 & n1256; - assign n105 = ~n597 | ~n1377; - assign n106 = n104 & (n105 | ~n500); - assign n107 = n1256 & n1264; - assign n108 = n107 & (~n336 | ~n1334); - assign n109 = ~n305 | ~n653; - assign n110 = n107 & (n109 | ~n685); - assign n111 = n107 & (~n426 | ~n1378); - assign n112 = n107 & (~n777 | ~n1795); - assign n113 = ~n1214 & n1256; - assign n114 = n113 & (~n1330 | ~n1418); - assign n115 = n113 & (~n774 | ~n1795); - assign n116 = n1228 & n1231; - assign n117 = n116 & (~n653 | ~n1378); - assign n118 = n113 & (~n266 | ~n1175); - assign n119 = ~n226 | ~n845; - assign n120 = n116 & (n119 | ~n472); - assign n121 = n172 & (n173 | n174); - assign n122 = i_6_ & ~i_7_; - assign n123 = n178 & n1228; - assign n124 = ~n1365 | ~n1370 | n159 | ~n714; - assign n125 = n2267 | n1647 | n717; - assign n126 = ~n1988 | ~n1989 | n184 | n185 | ~n157 | n175 | n180 | n182; - assign n127 = ~n2277 & n1618 & n1617 & n923 & n748 & n817; - assign n128 = n126 | n127; - assign n129 = n895 & n896 & (~n136 | ~n1237); - assign n130 = ~n481 & (n897 | n898); - assign n131 = n899 & (n900 | n901); - assign n132 = n1646 | n1647; - assign n133 = n1990 & n1648 & n1365 & n904 & n895 & n863 & ~n159 & n460; - assign n134 = n126 | n133; - assign n135 = ~i_2_ & i_0_ & i_1_; - assign n136 = i_6_ & i_7_; - assign n137 = n907 | n777; - assign n138 = n916 & n917 & (n918 | n911); - assign n139 = n1654 & n1653 & n1652 & n1651 & ~n915 & n1650; - assign n140 = n1658 & n1657 & n1656 & n1655 & ~n913 & n914; - assign n141 = n1661 & n1660 & n1659 & n912 & ~n171 & n909; - assign n142 = n141 & n140 & n139 & n137 & n138; - assign n143 = n2288 & n919 & n1617 & n815 & n740 & n1457 & n747 & n746; - assign n144 = n126 | n143; - assign n145 = n923 & (~n161 | n924); - assign n146 = n748 & n817 & n727 & n889 & n1622 & n862; - assign n147 = n126 | n146; - assign n148 = n929 & (~n984 | ~n1141); - assign n149 = n928 & (~n677 | ~n1663); - assign n150 = n978 & n977 & n976 & n938 & n975 & n974 & n972 & n973; - assign n151 = n126 | n150; - assign n152 = n187 & (~i_0_ | i_1_ | i_2_); - assign n153 = n1859 & n927 & n1644 & n769 & n1537 & n1617 & n1618; - assign n154 = n126 | n153; - assign n155 = ~n1973 | ~n1977 | ~n358 | n1972 | n347 | n350 | n352 | n355; - assign n156 = n1213 & ~n1214; - assign n157 = (~i_3_ | n186) & (n187 | n188); - assign n158 = n1213 & n176; - assign n159 = n1215 & ~n1353; - assign n160 = ~n481 & ~n1235; - assign n161 = n158 | n156; - assign n162 = n98 & (~n362 | ~n495); - assign n163 = n1239 & n1252; - assign n164 = n163 & (~n216 | ~n316); - assign n165 = ~n1233 & n1253; - assign n166 = n165 & (~n654 | ~n1012); - assign n167 = n176 & n1231; - assign n168 = n167 & (~n1176 | ~n1373); - assign n169 = n107 & (~n329 | ~n1416); - assign n170 = n167 & (~n709 | ~n1335); - assign n171 = ~n907 & (~n879 | ~n979); - assign n172 = ~i_2_ & ~i_0_ & i_1_; - assign n173 = i_3_ & i_5_ & i_4_; - assign n174 = ~i_5_ & i_3_ & i_4_; - assign n175 = ~n2381 & (n156 | n158); - assign n176 = n122 & i_8_; - assign n177 = i_8_ & n136; - assign n178 = n172 & n1215; - assign n179 = n172 & n1216; - assign n180 = (n176 | n177) & (n178 | n179); - assign n181 = n1228 & n179; - assign n182 = (~n1227 | ~n1987) & (n123 | n181); - assign n183 = n1216 | ~n1229 | i_3_ | ~n1212; - assign n184 = n135 & n183; - assign n185 = ~n1235 & (~n1227 | (i_12_ & ~n943)); - assign n186 = i_0_ | i_1_ | i_2_; - assign n187 = i_0_ | ~i_2_; - assign n188 = i_1_ | ~i_3_; - assign n189 = ~n98 | n316; - assign n190 = n1240 | n1245; - assign n191 = n1240 | n1243; - assign n192 = n189 & (~n98 | (n190 & n191)); - assign n193 = ~n98 | n317; - assign n194 = ~n98 | n287; - assign n195 = n1245 | n1260; - assign n196 = n193 & n194 & (~n98 | n195); - assign n197 = ~n98 | n979; - assign n198 = n264 & n1207; - assign n199 = n197 & (~n98 | n198); - assign n200 = ~n98 | n1105; - assign n201 = n329 & n444; - assign n202 = n200 & (~n98 | n201); - assign n203 = ~n98 | n1262; - assign n204 = n1238 | n1245; - assign n205 = n203 & (~n98 | n204); - assign n206 = n1198 | n1263; - assign n207 = n205 & (~n98 | n206); - assign n208 = ~n98 | n527; - assign n209 = n330 & n442; - assign n210 = n208 & (~n98 | n209); - assign n211 = ~n97 | n284; - assign n212 = n313 & n226; - assign n213 = n211 & (~n97 | n212); - assign n214 = ~n97 | n191; - assign n215 = n214 & (~n97 | n190); - assign n216 = n1198 | n1206; - assign n217 = n215 & (~n97 | n216); - assign n218 = ~n97 | n287; - assign n219 = n195 & n356; - assign n220 = n218 & (~n97 | n219); - assign n221 = ~n97 | n1105; - assign n222 = n221 & (~n97 | n201); - assign n223 = ~n97 | n527; - assign n224 = n223 & (~n97 | n209); - assign n225 = ~n167 | n444; - assign n226 = n1198 | n1201; - assign n227 = n1217 | n1220; - assign n228 = n225 & (~n167 | (n226 & n227)); - assign n229 = n113 & (~n331 | ~n334); - assign n230 = n107 & (~n474 | ~n1207); - assign n231 = ~n96 | n216; - assign n232 = ~n96 | n251; - assign n233 = ~n96 | n316; - assign n234 = ~n96 | n1157; - assign n235 = ~n96 | n1248; - assign n236 = n834 & n1475 & n1928 & n1546 & n860 & n827; - assign n237 = n1930 & n1932 & n1681 & n933 & n934 & n1715 & n955 & n1931; - assign n238 = n1941 & n1943 & n1944 & n1948 & n1947 & n1838 & n1945 & n1946; - assign n239 = n238 & n237 & n236 & n235 & n234 & n233 & n231 & n232; - assign n240 = ~n96 | n1247; - assign n241 = ~n96 | n204; - assign n242 = ~n96 | n195; - assign n243 = ~n278 | n617; - assign n244 = ~n96 | n264; - assign n245 = n1927 & (~n278 | (n204 & n306)); - assign n246 = ~n268 | n2036; - assign n247 = (~n107 | n195) & (n263 | n907); - assign n248 = n247 & n246 & n245 & n244 & n243 & n242 & n240 & n241; - assign n249 = ~n167 | n316; - assign n250 = ~n96 | n317; - assign n251 = n1220 | n1238; - assign n252 = n249 & n250 & (~n107 | n251); - assign n253 = n278 | n107; - assign n254 = ~n755 & (n97 | n253); - assign n255 = ~n96 | n331; - assign n256 = ~n113 | n1250; - assign n257 = (~n107 | n1295) & (~n633 | n1866); - assign n258 = (~n96 | n190) & (~n97 | n749); - assign n259 = (~n167 | ~n268) & (n924 | n1968); - assign n260 = n252 & n248 & n239 & n1282 & n1286 & n1054 & n217 & n220; - assign n261 = n1962 & n1964 & n1967 & n1966 & n1965 & n1800 & n1842 & n1818; - assign n262 = n261 & n260 & n259 & n258 & n257 & n256 & ~n254 & n255; - assign n263 = n195 & n305; - assign n264 = n1219 | n1245; - assign n265 = ~i_15_ | n1218; - assign n266 = n1197 | n1204; - assign n267 = n266 & n265 & n263 & n264; - assign n268 = ~n190 | ~n617; - assign n269 = ~n327 & (~n263 | n268); - assign n270 = ~n167 | n604; - assign n271 = ~n167 | n204; - assign n272 = n1923 & (n1924 | n313); - assign n273 = (~n107 | n597) & (~n167 | n330); - assign n274 = n1926 & (~n348 | n604); - assign n275 = n1712 & n1502 & n1706 & n1750 & n1674 & n1680; - assign n276 = n1594 & n1860 & n1548 & n1602 & n1568 & n1573; - assign n277 = n276 & n275 & n274 & n273 & n272 & n271 & ~n269 & n270; - assign n278 = ~n1214 & n1253; - assign n279 = n278 & (~n284 | ~n287); - assign n280 = n191 | ~n353; - assign n281 = n116 & (~n287 | ~n979); - assign n282 = n1105 & n309; - assign n283 = ~n104 | n282; - assign n284 = n1217 | n1243; - assign n285 = ~n104 & ~n116; - assign n286 = n284 | n285; - assign n287 = n1243 | n1260; - assign n288 = n1204 | n1238; - assign n289 = n191 & n536 & n926; - assign n290 = n289 & n287 & n288; - assign n291 = ~n571 & n1292; - assign n292 = ~n381 & n1291; - assign n293 = n292 & n291 & ~n113 & ~n163; - assign n294 = n113 | n571; - assign n295 = n165 | n107; - assign n296 = ~n674 & (n167 | n294 | n295); - assign n297 = n1300 & n1299 & n1298 & n1297 & n1296 & n286 & ~n281 & n283; - assign n298 = n563 & n561 & n497; - assign n299 = (~n107 | n508) & (~n278 | n288); - assign n300 = (n292 | n879) & (~n96 | n926); - assign n301 = (n290 | ~n404) & (~n253 | n1293); - assign n302 = n1910 & n1909 & n1400 & n1398 & n1396 & n559 & ~n296 & n483; - assign n303 = n302 & n301 & n300 & n299 & n297 & n298; - assign n304 = n610 & n604; - assign n305 = n1204 | n1265; - assign n306 = n1204 | n1263; - assign n307 = n266 & n306 & n304 & n305; - assign n308 = n1207 & n226; - assign n309 = n1241 | n1243; - assign n310 = n206 & n284 & n308 & n309; - assign n311 = ~n98 | n227; - assign n312 = ~n98 | n284; - assign n313 = n1217 | n1245; - assign n314 = n311 & n312 & (~n98 | n313); - assign n315 = n314 & (~n98 | n226); - assign n316 = n1220 | n1240; - assign n317 = n1220 | n1260; - assign n318 = n317 & n316 & n216; - assign n319 = n316 & n474; - assign n320 = ~n165 | n319; - assign n321 = n571 | n104; - assign n322 = n321 & (~n227 | ~n822 | ~n1157); - assign n323 = ~n165 & ~n571; - assign n324 = n317 | n323; - assign n325 = n1308 & n1307 & n1306 & n1305 & n1304 & n1303 & n1301 & n1302; - assign n326 = n487 & n494 & (n318 | ~n404); - assign n327 = ~n294 & n1290; - assign n328 = n325 & n326 & (n327 | n251); - assign n329 = n1245 | n1249; - assign n330 = n1245 | n1255; - assign n331 = n1198 | n1255; - assign n332 = n331 & n329 & n330; - assign n333 = n1250 & n334; - assign n334 = n1198 | n1217; - assign n335 = (n291 | n333) & (~n98 | n334); - assign n336 = n1247 & n1248; - assign n337 = n336 & n316 & n204; - assign n338 = n343 | n354; - assign n339 = n338 & (~n755 | ~n924); - assign n340 = n165 | ~n291; - assign n341 = n340 & (~n921 | ~n1262); - assign n342 = n294 & (~n287 | ~n474); - assign n343 = n404 | n163; - assign n344 = ~n327 | n348; - assign n345 = ~n774 & (n343 | n344); - assign n346 = n404 | n165; - assign n347 = ~n1250 & (n96 | n346); - assign n348 = n98 | n97; - assign n349 = n113 | ~n291; - assign n350 = ~n265 & (n348 | n349); - assign n351 = n359 | n381 | n344; - assign n352 = ~n597 & (n278 | n351); - assign n353 = n1231 & n177; - assign n354 = n98 | ~n327; - assign n355 = ~n216 & (n353 | n354); - assign n356 = n1198 | n1265; - assign n357 = ~n98 & n1309; - assign n358 = n356 | n357; - assign n359 = n163 | n96; - assign n360 = n359 & (~n265 | ~n604 | ~n1311); - assign n361 = n1206 | n1221; - assign n362 = n1197 | n1245; - assign n363 = n361 & n362; - assign n364 = ~n97 | n495; - assign n365 = ~n97 | n566; - assign n366 = ~n96 | n447; - assign n367 = ~n96 | n426; - assign n368 = ~n96 | n688; - assign n369 = n1604 & n1701 & n2075 & n2076; - assign n370 = n2081 & n947 & n1719 & n2080 & n2079 & n998 & n2077 & n2078; - assign n371 = n2085 & n2086 & n1089 & n1846 & n1016 & n1007 & n1864 & n2087; - assign n372 = n371 & n370 & n369 & n368 & n367 & n366 & n364 & n365; - assign n373 = (~n116 | n1138) & (~n404 | n447); - assign n374 = n2109 & (n361 | ~n381); - assign n375 = n2108 & (~n165 | (n426 & n1331)); - assign n376 = n1131 & n1132 & n1078 & n2107; - assign n377 = n2103 & n2106 & n916 & n1810 & n1785 & n1822 & n2104 & n2105; - assign n378 = n2097 & n1709 & n2101 & n2100 & n2099 & n1697 & n2098 & n1687; - assign n379 = n2091 & n1484 & n2094 & n1525 & n2093 & n1574 & n2092 & n1565; - assign n380 = n379 & n378 & n377 & n376 & n375 & n374 & n373 & n372; - assign n381 = n404 | n167; - assign n382 = n163 | n107; - assign n383 = ~n845 & (n381 | n382); - assign n384 = ~n167 | n1331; - assign n385 = ~n167 | n688; - assign n386 = ~n278 | n1331; - assign n387 = ~n96 | n845; - assign n388 = n2110 & (~n107 | (n426 & n688)); - assign n389 = (~n163 | n361) & (~n167 | n426); - assign n390 = n2111 & (~n348 | n1331); - assign n391 = n390 & n380 & n389 & n388 & n387 & n386 & n384 & n385; - assign n392 = i_15_ | n1332; - assign n393 = n1243 | n1257; - assign n394 = n392 & n393; - assign n395 = ~n104 | n441; - assign n396 = ~n104 | n393; - assign n397 = (n394 | n911) & (~n253 | n1336); - assign n398 = n1340 & n2071 & (~n116 | n441); - assign n399 = n2069 & n1000 & n1805 & n1746 & n1747 & n2070; - assign n400 = n2061 & n2065 & n1776 & n1786 & n1819 & n2066 & n1752 & n1830; - assign n401 = n2049 & n2051 & n2054 & n2053 & n1694 & n2052 & n1710 & n1685; - assign n402 = n2043 & n2037 & n770 & n2045 & n2044 & n733 & n1510 & n722; - assign n403 = n402 & n401 & n400 & n399 & n398 & n397 & n395 & n396; - assign n404 = n1231 & ~n1232; - assign n405 = n404 & (~n430 | ~n529 | ~n709); - assign n406 = ~n167 | n1334; - assign n407 = ~n278 | n393; - assign n408 = ~n96 | n441; - assign n409 = n2073 & (~n278 | n429); - assign n410 = (~n107 | n1334) & (~n167 | n471); - assign n411 = n2074 & (~n348 | n393); - assign n412 = n411 & n410 & n409 & n408 & n407 & n406 & n403 & ~n405; - assign n413 = ~n107 | n1224; - assign n414 = ~n113 | n1152; - assign n415 = ~n113 | n1151; - assign n416 = ~n107 | n1341; - assign n417 = n990 & (n2036 | n1145); - assign n418 = n1345 & n1344 & n1342 & n1343; - assign n419 = n958 & n2035 & n1439 & n2034 & n2033 & n2032 & n2030 & n2031; - assign n420 = n2028 & n2029 & n1419 & n1725 & n1471 & n1499 & n1729 & n782; - assign n421 = n420 & n419 & n418 & n417 & n416 & n415 & n413 & n414; - assign n422 = ~n96 | n1330; - assign n423 = n1335 & n1330; - assign n424 = n421 & n422 & (~n107 | n423); - assign n425 = ~n97 | n471; - assign n426 = n1245 | n1265; - assign n427 = n425 & (~n97 | n426); - assign n428 = n427 & (~n97 | n356); - assign n429 = n709 & n473; - assign n430 = n1221 | n1240; - assign n431 = n429 & n430; - assign n432 = ~n107 | n471; - assign n433 = ~n107 | n1337; - assign n434 = ~n107 | n472; - assign n435 = (~n107 | n431) & (n907 | n908); - assign n436 = ~n278 | n441; - assign n437 = n2002 & n2001 & n2000 & n1999 & n1998 & n1997 & n989; - assign n438 = n1993 & n1996 & n1995 & n1714 & n1600 & n1605 & n1994 & n1554; - assign n439 = n438 & n437 & n436 & n435 & n434 & n433 & ~n170 & n432; - assign n440 = n1220 | n1246; - assign n441 = i_15_ | n1225; - assign n442 = n1198 | n1258; - assign n443 = n1224 & n1082; - assign n444 = n1198 | n1257; - assign n445 = n444 & n443 & n442 & n206 & n441 & n356 & n308 & n440; - assign n446 = ~n98 | n473; - assign n447 = n1245 | n1263; - assign n448 = n446 & (~n98 | n447); - assign n449 = (n119 | ~n206) & (n97 | n98); - assign n450 = ~n216 | ~n564; - assign n451 = ~n327 & (n450 | ~n1347); - assign n452 = ~n361 & (n96 | n354); - assign n453 = n163 | ~n292; - assign n454 = ~n1224 & (n104 | n453); - assign n455 = ~n291 & (~n316 | ~n685 | ~n1348); - assign n456 = ~n1145 & (~n327 | n359 | n381); - assign n457 = ~n1152 & (~n292 | n340 | n359); - assign n458 = n1230 | n1251; - assign n459 = n1230 | n1233; - assign n460 = n458 & (n459 | ~n819); - assign n461 = n1990 & n1624 & n1620; - assign n462 = n444 & n508; - assign n463 = n460 & n461 & (n462 | n459); - assign n464 = n442 & n469; - assign n465 = ~n450 & n464; - assign n466 = (~n97 | n465) & (~n98 | n464); - assign n467 = n393 & n1331; - assign n468 = n426 & n845; - assign n469 = n707 & n656; - assign n470 = n709 & n362; - assign n471 = n1243 | n1265; - assign n472 = n1201 | n1243; - assign n473 = n1243 | n1263; - assign n474 = n1219 | n1220; - assign n475 = n474 & n473 & n472 & n471 & n470 & n469 & n467 & n468; - assign n476 = ~n362 & (n278 | n381); - assign n477 = n1363 & n1362 & n1361 & n1360 & n766 & n239 & n439 & n428; - assign n478 = n2117 & n1359 & n328 & n252; - assign n479 = n2115 & n2113 & n1041 & n2114 & n2112 & n839 & n1385 & n869; - assign n480 = n479 & n478 & n477 & n466 & n463 & n391 & n412 & n424; - assign n481 = i_10_ | i_9_; - assign n482 = n481 | ~n897; - assign n483 = ~n98 | n508; - assign n484 = n483 & (~n98 | n467); - assign n485 = ~n96 | n227; - assign n486 = n485 & (~n99 | ~n163); - assign n487 = ~n163 | n227; - assign n488 = ~n96 | n1372; - assign n489 = n1221 | n1246; - assign n490 = n487 & n488 & (~n96 | n489); - assign n491 = ~n163 | n1372; - assign n492 = n250 & n491 & (~n163 | n489); - assign n493 = ~n96 | n1125; - assign n494 = ~n163 | n474; - assign n495 = ~i_15_ | n1223; - assign n496 = n493 & n494 & (~n96 | n495); - assign n497 = ~n98 | n1293; - assign n498 = n497 & (~n98 | n469); - assign n499 = n1258 | n1371; - assign n500 = n1221 | n1258; - assign n501 = n499 & n500; - assign n502 = (n501 | ~n571) & (~n113 | n251); - assign n503 = ~n96 | n288; - assign n504 = n1238 | n1376; - assign n505 = n422 & n503 & (~n96 | n504); - assign n506 = n879 | n675; - assign n507 = ~n107 | n499; - assign n508 = n1204 | n1249; - assign n509 = n1233 | ~n1239; - assign n510 = n506 & n507 & (n508 | n509); - assign n511 = ~n163 | n1375; - assign n512 = ~n163 | n530; - assign n513 = ~n98 | n1374; - assign n514 = ~n98 | n951; - assign n515 = n2185 & (~n929 | n984); - assign n516 = n875 | n509; - assign n517 = n516 & n515 & n514 & n513 & n511 & n512; - assign n518 = n682 & n504; - assign n519 = n1377 & n653; - assign n520 = n979 & n1262; - assign n521 = n1240 | n1371; - assign n522 = n1238 | n1371; - assign n523 = n1249 | n1376; - assign n524 = n523 & n522 & n521 & n520 & n518 & n519; - assign n525 = n430 & n926 & n1176; - assign n526 = n1217 | n1376; - assign n527 = n1243 | n1255; - assign n528 = n1241 | n1376; - assign n529 = n1221 | n1241; - assign n530 = n1241 | n1371; - assign n531 = n530 & n529 & n528 & n527 & n526 & n284 & n282 & n525; - assign n532 = n107 & (~n1175 | ~n1381 | ~n2184); - assign n533 = n528 & n1380; - assign n534 = ~n532 & (~n104 | (n525 & n533)); - assign n535 = ~n278 | n529; - assign n536 = n1204 | n1241; - assign n537 = n535 & (~n278 | n536); - assign n538 = ~n278 | n528; - assign n539 = ~n453 & n1349; - assign n540 = n1260 | n1371; - assign n541 = n538 & n537 & (n539 | n540); - assign n542 = n107 & (~n523 | ~n530 | ~n1382); - assign n543 = (~n98 | n592) & (n567 | ~n929); - assign n544 = (~n96 | n682) & (~n404 | n522); - assign n545 = n2203 & n2204 & (~n346 | n1375); - assign n546 = n944 & n765 & n541 & n534 & n517 & n510 & n1387 & n505; - assign n547 = n2198 & n2199 & n2200 & n2201 & n2197 & n2195 & n2202 & n1283; - assign n548 = n2191 & n2187 & n2188 & n200 & n2192 & n197 & n221 & n218; - assign n549 = n548 & n547 & n546 & n545 & n543 & n544; - assign n550 = n1395 & n1394 & n1393 & n1392 & n1391 & n1090 & n1389 & n1390; - assign n551 = n1321 & n1320 & n1319 & n1318 & n1317 & n280 & ~n171 & ~n279; - assign n552 = n2183 & (n1196 | ~n1388); - assign n553 = (~n113 | n1374) & (n521 | n2036); - assign n554 = n1843 & n2182 & (~n107 | n520); - assign n555 = n2178 & n2181 & n1761 & n1061 & n1836 & n2180 & n1095 & n2179; - assign n556 = n2172 & n1652 & n1659 & n2174 & n959 & n1682 & n2173 & n1728; - assign n557 = n2171 & n1428 & n1453 & n1479 & n1468 & n1464 & n1534 & n1448; - assign n558 = n557 & n556 & n555 & n554 & n553 & n552 & n550 & n551; - assign n559 = ~n97 | n508; - assign n560 = n559 & (~n97 | n467); - assign n561 = ~n97 | n1293; - assign n562 = n561 & (~n97 | n469); - assign n563 = ~n97 | n926; - assign n564 = n1337 & n1333; - assign n565 = n563 & (~n97 | n564); - assign n566 = ~i_15_ | n1332; - assign n567 = n1257 | n1371; - assign n568 = n566 & n567; - assign n569 = (n568 | ~n571) & (~n113 | n474); - assign n570 = ~n879 & (n116 | n165 | n381); - assign n571 = ~n1233 & n1256; - assign n572 = ~n1028 & (n346 | n571); - assign n573 = (~n116 | n984) & (~n165 | n528); - assign n574 = n1403 & n848 & n851 & n1402; - assign n575 = (~n321 | n592) & (~n404 | n504); - assign n576 = (n323 | n1125) & (~n253 | n1377); - assign n577 = n2138 & n2137 & n2136 & n1743 & n1130 & ~n572 & n1079; - assign n578 = n2134 & n1650 & n1852 & n1654 & n2135 & n1809 & n1824 & n1751; - assign n579 = n2128 & n1741 & n1119 & n1733 & n2129 & n1688 & n1707 & n1708; - assign n580 = n2121 & n2124 & n1542 & n1527 & n725 & n723 & n2122 & n2123; - assign n581 = n580 & n579 & n578 & n577 & n576 & n575 & n573 & n574; - assign n582 = ~n291 & (~n729 | ~n1405); - assign n583 = n381 & (~n316 | ~n1377 | ~n1406); - assign n584 = (n287 | ~n294) & (~n348 | n442); - assign n585 = n2211 & (~n404 | n1756); - assign n586 = n2208 & n2209 & (~n113 | n2210); - assign n587 = n2206 & n2207 & n1071 & n1531 & n1691 & n1834 & n1792 & n1816; - assign n588 = n2214 & n486 & n484 & n502 & n498 & n549 & n558 & n1414; - assign n589 = n2213 & n581 & n1411 & n477 & n421 & n403; - assign n590 = n589 & n588 & n587 & n586 & n584 & n585; - assign n591 = ~n98 | n685; - assign n592 = n1265 | n1371; - assign n593 = n591 & (~n98 | n592); - assign n594 = n593 & (~n98 | n305); - assign n595 = ~n96 | n1377; - assign n596 = ~n96 | n500; - assign n597 = n1204 | n1258; - assign n598 = n595 & n596 & (~n96 | n597); - assign n599 = ~n163 | n1377; - assign n600 = ~n163 | n500; - assign n601 = n599 & n600 & (~n163 | n597); - assign n602 = ~n96 | n523; - assign n603 = ~n96 | n566; - assign n604 = n1204 | n1257; - assign n605 = n602 & n603 & (~n96 | n604); - assign n606 = ~n163 | n523; - assign n607 = ~n163 | n566; - assign n608 = n606 & n607 & (~n163 | n604); - assign n609 = ~n167 | n528; - assign n610 = n1204 | n1246; - assign n611 = n609 & (~n167 | n610); - assign n612 = (~n167 | n1377) & (~n571 | n1141); - assign n613 = n2227 & (~n343 | n652); - assign n614 = n613 & n612 & n581; - assign n615 = ~n97 | n361; - assign n616 = ~n97 | n1373; - assign n617 = n1204 | n1206; - assign n618 = n615 & n616 & (~n97 | n617); - assign n619 = ~n97 | n685; - assign n620 = ~n97 | n592; - assign n621 = n619 & n620 & (~n97 | n305); - assign n622 = ~n96 | n526; - assign n623 = ~n96 | n1138; - assign n624 = n622 & n623 & (~n96 | n265); - assign n625 = ~n96 | n653; - assign n626 = n625 & (~n96 | n305); - assign n627 = ~n113 | n777; - assign n628 = n137 & n1461 & n1452; - assign n629 = n489 & n1415; - assign n630 = n627 & n628 & (~n107 | n629); - assign n631 = n798 & n654 & n752; - assign n632 = n631 & n264 & n204; - assign n633 = n96 | n107; - assign n634 = ~n738 & (n633 | ~n907); - assign n635 = ~n96 | n2372; - assign n636 = ~n96 | n629; - assign n637 = ~n278 | n654; - assign n638 = n1209 | ~n1388; - assign n639 = ~n278 | n777; - assign n640 = n2220 & n2219 & n2217 & n2218; - assign n641 = n2216 & n2215 & n1519 & n1513 & n1497 & n1478 & ~n103 & n1467; - assign n642 = n2225 & n2226 & n630 & n1420 & n1422 & n624 & n618 & n621; - assign n643 = n642 & n641 & n640 & n639 & n638 & n637 & n635 & n636; - assign n644 = ~n98 | n1138; - assign n645 = ~n98 | n984; - assign n646 = n644 & n645 & (~n98 | n265); - assign n647 = ~n404 | n500; - assign n648 = n647 & (~n105 | ~n404); - assign n649 = n500 & n566; - assign n650 = ~n571 | n649; - assign n651 = n1258 | n1376; - assign n652 = n1176 & n1373; - assign n653 = n1260 | n1376; - assign n654 = n1257 | n1376; - assign n655 = n361 & n654 & n653 & n652 & n518 & n651; - assign n656 = n1245 | n1258; - assign n657 = n1415 & ~n1114 & n1331; - assign n658 = n526 & n265; - assign n659 = n658 & n657 & n656 & ~n105 & n362; - assign n660 = n313 & n656 & n447 & n468 & n195 & n190; - assign n661 = ~n98 | n684; - assign n662 = ~n98 | n1028; - assign n663 = n661 & n662 & (~n98 | n306); - assign n664 = n597 & n610 & n306 & n265; - assign n665 = ~n97 | n684; - assign n666 = ~n97 | n1028; - assign n667 = ~n97 | n984; - assign n668 = n2027 & (~n97 | n664); - assign n669 = n1427 & n1428; - assign n670 = n1426 & n1425 & n1423 & n1424; - assign n671 = ~n98 | n597; - assign n672 = n671 & n670 & n669 & n663 & n668 & n667 & n665 & n666; - assign n673 = n288 | n675; - assign n674 = n1204 | n1260; - assign n675 = n1214 | ~n1239; - assign n676 = n673 & (n674 | n675); - assign n677 = n592 & n1028; - assign n678 = n507 & n676 & (n677 | ~n928); - assign n679 = ~n738 & (n344 | n453); - assign n680 = ~n359 & n911; - assign n681 = n680 & ~n346 & ~n98 & n291; - assign n682 = n1219 | n1376; - assign n683 = n488 & n493 & (~n167 | n682); - assign n684 = n1221 | n1263; - assign n685 = n1221 | n1265; - assign n686 = n684 & n685; - assign n687 = n329 & n204 & n1247; - assign n688 = n1245 | n1246; - assign n689 = n330 & n688 & n687 & n264; - assign n690 = n359 & (~n190 | ~n1429); - assign n691 = n165 & (~n523 | ~n1377); - assign n692 = n107 & (~n500 | ~n1247); - assign n693 = ~n292 & (~n362 | ~n752 | ~n1382); - assign n694 = (~n96 | n521) & (~n253 | n910); - assign n695 = n2253 & (~n278 | n1378); - assign n696 = n425 & n1005 & (~n113 | n1086); - assign n697 = n696 & n695 & n439 & n694 & n683 & n558; - assign n698 = n227 | n1234; - assign n699 = n822 | n1234; - assign n700 = n474 | n1234; - assign n701 = n879 | n1234; - assign n702 = n875 | n1234; - assign n703 = n1207 | n1234; - assign n704 = n226 | n1234; - assign n705 = n1645 & (n462 | n1234); - assign n706 = n705 & n704 & n703 & n702 & n701 & n700 & n698 & n699; - assign n707 = n1243 | n1258; - assign n708 = n441 & n393 & n473 & n707 & n536; - assign n709 = n1197 | n1243; - assign n710 = n472 & n709; - assign n711 = n227 | n713; - assign n712 = ~n136 | ~n1213; - assign n713 = ~n1213 | n1232; - assign n714 = n711 & n712 & (n713 | ~n716); - assign n715 = n178 & ~n1232; - assign n716 = n819 | ~n481 | ~n757; - assign n717 = n715 & (~n227 | n716); - assign n718 = ~n98 | n1341; - assign n719 = n2192 & n1276 & n1344; - assign n720 = n755 & n793; - assign n721 = n718 & n719 & (~n98 | n720); - assign n722 = ~n98 | n392; - assign n723 = ~n98 | n523; - assign n724 = ~n98 | n566; - assign n725 = ~n98 | n567; - assign n726 = n202 & (~n98 | n604); - assign n727 = n484 & n726 & n725 & n724 & n722 & n723; - assign n728 = ~n98 | n536; - assign n729 = n1334 & n688; - assign n730 = n728 & (~n98 | n729); - assign n731 = ~n97 | n879; - assign n732 = n731 & (~n97 | n470); - assign n733 = ~n97 | n1335; - assign n734 = ~n97 | n682; - assign n735 = n733 & n734 & (~n97 | n266); - assign n736 = ~n98 | n266; - assign n737 = ~n98 | n334; - assign n738 = n1265 | n1376; - assign n739 = n1198 | n1260; - assign n740 = (~n98 | n739) & (~n348 | n738); - assign n741 = ~n97 | n530; - assign n742 = ~n98 | n1797; - assign n743 = ~n97 | n440; - assign n744 = n740 & (~n97 | n774); - assign n745 = n1457 & n732; - assign n746 = n1466 & n1465 & n1464 & n1462 & n1463; - assign n747 = n737 & n1461 & n1460 & n1459 & n1458 & n1434 & n513; - assign n748 = n747 & n746 & n745 & n730 & n744 & n743 & n741 & n742; - assign n749 = n1198 | n1219; - assign n750 = ~n348 | n749; - assign n751 = n750 & n1435 & n1471 & n1470 & n1469 & n1467 & n1468; - assign n752 = n1197 | n1376; - assign n753 = n751 & (~n98 | n752); - assign n754 = ~n98 | n651; - assign n755 = n1198 | n1238; - assign n756 = n514 & n754 & (~n97 | n755); - assign n757 = n1446 & n822 & n462; - assign n758 = n757 | ~n1473; - assign n759 = n1151 & n1250; - assign n760 = (~n96 | n759) & (~n163 | n752); - assign n761 = n309 & n1247; - assign n762 = n1262 & n204; - assign n763 = n330 & n313 & n761 & n762; - assign n764 = n1477 & n1476 & n1474 & n1475; - assign n765 = n1383 & n208 & n872 & n869 & n223 & n870; - assign n766 = n1352 & n1351 & ~n449 & n1350; - assign n767 = n1340 & n314 & n298; - assign n768 = n2271 & n205 & n215 & n1928 & n834 & n1955 & n1626 & n852; - assign n769 = n768 & n767 & n766 & n466 & n765 & n574 & n764 & n672; - assign n770 = ~n97 | n392; - assign n771 = ~n97 | n523; - assign n772 = n770 & n771 & (~n97 | n604); - assign n773 = n98 & (~n610 | ~n777); - assign n774 = n1198 | n1241; - assign n775 = ~n98 | n774; - assign n776 = ~n96 | n530; - assign n777 = n1246 | n1376; - assign n778 = n776 & (~n96 | (n440 & n777)); - assign n779 = ~n163 | n440; - assign n780 = n779 & (~n163 | n777); - assign n781 = ~n359 | n739; - assign n782 = ~n96 | n1097; - assign n783 = ~n96 | n540; - assign n784 = (~n96 | n738) & (~n163 | n1097); - assign n785 = n780 & n784 & n783 & n782 & n781 & n512; - assign n786 = ~n163 | n1155; - assign n787 = ~n163 | n951; - assign n788 = n786 & n787 & (~n163 | n651); - assign n789 = n1417 & n924; - assign n790 = ~n98 | n789; - assign n791 = ~n96 | n1341; - assign n792 = ~n96 | n522; - assign n793 = n1263 | n1376; - assign n794 = n791 & n792 & (~n96 | n793); - assign n795 = n163 & (~n1224 | ~n1506); - assign n796 = n163 & (~n654 | ~n749 | ~n1507); - assign n797 = ~n96 | n749; - assign n798 = n1201 | n1376; - assign n799 = n798 & n738 & n540 & n313 & ~n102 & n191; - assign n800 = n359 & (~n190 | ~n1166); - assign n801 = n1505 & n255 & n1073; - assign n802 = n1532 & n1537 & n1526 & n1521 & n1518; - assign n803 = n2270 & n1951 & n1516 & n1436 & n1278 & n1195 & ~n103 & ~n164; - assign n804 = n2269 & n244 & n1915 & n1275 & n1959 & n1345 & n1313 & n1273; - assign n805 = n2268 & n2154 & n2089 & n2038 & n1991 & n1891 & ~n101 & n231; - assign n806 = n805 & n804 & n803 & n802 & n788 & n785 & n778 & n801; - assign n807 = n1553 & n1552 & n1551 & n1550 & n1549 & n1547 & n1548; - assign n808 = n1546 & n1545 & n366 & n232 & n241 & n1544; - assign n809 = n505 & (~n96 | n1867); - assign n810 = n1543 & n1542 & n1541 & n1540 & n1539 & n1538 & n1329 & n601; - assign n811 = n810 & n809 & n807 & n808; - assign n812 = n96 & (~n682 | ~n1415); - assign n813 = n163 & (~n305 | ~n774 | ~n1415); - assign n814 = n266 | ~n359; - assign n815 = n1611 & n1610 & n1609 & n1596 & n806 & n1588 & n1578 & n836; - assign n816 = i_7_ | i_6_; - assign n817 = n815 & (n816 | ~n1608); - assign n818 = n179 & ~n1232; - assign n819 = ~n879 | ~n1207; - assign n820 = n818 & (~n227 | ~n757 | n819); - assign n821 = n227 | ~n1619; - assign n822 = n1220 | n1249; - assign n823 = n822 | ~n1628; - assign n824 = n474 | ~n897; - assign n825 = n902 & ~n1473; - assign n826 = n700 & n824 & (n825 | n474); - assign n827 = ~n97 | n317; - assign n828 = n220 & (~n98 | n263); - assign n829 = n1563 & n1562 & n1560 & n1561; - assign n830 = n1559 & n1558 & n1557 & n621; - assign n831 = n427 & n593 & n830 & n829 & n828 & n827 & n193 & n194; - assign n832 = ~n97 | n536; - assign n833 = n832 & (~n97 | n729); - assign n834 = ~n97 | n1157; - assign n835 = ~n97 | n1797; - assign n836 = n1582 & n1581 & n1580 & n368 & n240 & n235 & n1579 & n234; - assign n837 = n1578 & n2228 & (~n163 | n774); - assign n838 = n837 & n836 & n833 & n835 & n636 & n491 & n488 & n834; - assign n839 = ~n97 | n529; - assign n840 = ~n97 | n528; - assign n841 = n839 & n840 & (~n97 | n610); - assign n842 = ~n96 | n1375; - assign n843 = n842 & (~n96 | n759); - assign n844 = n97 & (~n265 | ~n845); - assign n845 = n1201 | n1245; - assign n846 = ~n98 | n845; - assign n847 = ~n97 | n1336; - assign n848 = ~n97 | n1377; - assign n849 = n847 & n848 & (~n97 | n597); - assign n850 = ~n98 | n1336; - assign n851 = ~n98 | n1377; - assign n852 = ~n98 | n1261; - assign n853 = n210 & (~n98 | n597); - assign n854 = n562 & n498 & n670 & n849 & n853 & n852 & n850 & n851; - assign n855 = n1453 & n1451 & n1452; - assign n856 = n756 & n1472 & n1312; - assign n857 = n721 & n1450 & (~n98 | n752); - assign n858 = ~n97 | n2369; - assign n859 = n508 | ~n897; - assign n860 = ~n97 | n474; - assign n861 = n1858 & n1616 & (n888 | n508); - assign n862 = n861 & n860 & n859 & n858 & n857 & n856 & n751 & n855; - assign n863 = ~n136 | n1441; - assign n864 = ~n136 | n1364; - assign n865 = (~n136 | ~n159) & (n459 | n875); - assign n866 = n865 & n863 & n864; - assign n867 = ~n122 | n1364; - assign n868 = n867 & (~n122 | ~n159); - assign n869 = ~n97 | n1330; - assign n870 = ~n97 | n504; - assign n871 = n869 & n870 & (~n97 | n306); - assign n872 = ~n97 | n288; - assign n873 = n473 & n447; - assign n874 = n872 & (~n97 | n873); - assign n875 = i_15_ | n1218; - assign n876 = n875 | n825; - assign n877 = n163 & (~n266 | ~n305 | ~n752); - assign n878 = ~n481 & (n818 | ~n1234); - assign n879 = n1204 | n1219; - assign n880 = n459 & n902; - assign n881 = n879 | n880; - assign n882 = ~n159 | n1251; - assign n883 = n1251 | n1364; - assign n884 = n882 & n883 & (n226 | n459); - assign n885 = n816 | n1364; - assign n886 = n885 & (~n159 | n816); - assign n887 = n444 | ~n897; - assign n888 = n1235 & ~n1628; - assign n889 = n887 & (n888 | n444); - assign n890 = n1355 & n1442 & n2118; - assign n891 = n704 & n890 & (n825 | n226); - assign n892 = n703 & n1356 & n1444 & n1367 & n1613; - assign n893 = (n880 | n1207) & (n1235 | n481); - assign n894 = n893 & n891 & n889 & n884 & n892 & n886; - assign n895 = n1645 & n712 & n1368; - assign n896 = n458 & (~n1608 | (~n136 & n816)); - assign n897 = n1213 & ~n1233; - assign n898 = ~n713 | n715; - assign n899 = n2267 | n2276; - assign n900 = i_9_ & ~i_10_; - assign n901 = ~i_9_ & i_10_; - assign n902 = n713 & ~n1619; - assign n903 = ~n819 | n902; - assign n904 = n826 & n903 & n1641 & n892; - assign n905 = n868 & n2287 & (~n899 | ~n901); - assign n906 = n905 & n904 & ~n132 & n886; - assign n907 = ~n176 | ~n1239; - assign n908 = n709 & n1335; - assign n909 = n907 | n908; - assign n910 = n1219 | n1371; - assign n911 = n1232 | ~n1239; - assign n912 = n910 | n911; - assign n913 = ~n907 & (~n263 | ~n738); - assign n914 = n738 | n911; - assign n915 = ~n911 & (~n393 | ~n1102); - assign n916 = n911 | n688; - assign n917 = n2135 & n2104 & n2133; - assign n918 = n777 & n1649; - assign n919 = n741 & n743 & (~n97 | n774); - assign n920 = ~n98 | n761; - assign n921 = n264 & n979; - assign n922 = ~n97 | n921; - assign n923 = n1615 & n1614 & n1613 & n758; - assign n924 = n1198 | n1240; - assign n925 = n2289 & (n509 | (n1662 & n875)); - assign n926 = n1204 | n1240; - assign n927 = n676 & n925 & (n926 | n675); - assign n928 = n177 & n1256; - assign n929 = n1228 & n1256; - assign n930 = n165 | n278; - assign n931 = n930 & (~n685 | ~n1378); - assign n932 = ~n278 | n979; - assign n933 = ~n278 | n1207; - assign n934 = ~n278 | n474; - assign n935 = n2143 & (~n165 | n474); - assign n936 = n1196 | ~n1388; - assign n937 = n2100 & n2157 & n2075 & n1996 & n1877 & n2052; - assign n938 = n937 & n936 & n935 & n934 & n932 & n933; - assign n939 = n656 & n1665; - assign n940 = ~n165 | n939; - assign n941 = ~i_11_ | ~n900; - assign n942 = n941 | ~n1379; - assign n943 = i_11_ | n1202; - assign n944 = n943 | ~n1379; - assign n945 = ~n278 | n984; - assign n946 = ~n278 | n982; - assign n947 = ~n278 | n845; - assign n948 = n1995 & (~n278 | (n284 & n983)); - assign n949 = n948 & n947 & n945 & n946; - assign n950 = ~n278 | n939; - assign n951 = n1255 | n1371; - assign n952 = n1162 & n1028 & n1330; - assign n953 = n651 & n1029; - assign n954 = n953 & n952 & n684 & n288 & n951; - assign n955 = n251 | ~n278; - assign n956 = ~n278 | n1262; - assign n957 = ~n165 | n499; - assign n958 = ~n278 | n1341; - assign n959 = ~n278 | n522; - assign n960 = n1670 & (~n165 | n954); - assign n961 = n2291 & (~n278 | (n204 & n793)); - assign n962 = n2290 & n638 & n1949 & n1994 & n1931 & n1874 & n2050 & n2098; - assign n963 = n962 & n961 & n960 & n959 & n958 & n957 & n955 & n956; - assign n964 = n313 & n334; - assign n965 = n682 & n653 & n263 & n1676; - assign n966 = n739 & n789 & n964 & n965; - assign n967 = n1125 & ~n450 & n979; - assign n968 = n1335 & n1247 & n1373 & n1678 & n331 & n1102; - assign n969 = n774 & n777; - assign n970 = n329 & n317 & n495; - assign n971 = n970 & n793 & n798 & n969 & n968 & n967 & n657 & n525; - assign n972 = n1697 & n1696 & n1695 & n1694 & n1693 & n1692 & n1691 & n942; - assign n973 = n944 & n1690 & n1689 & n1688 & n1687 & n1685 & n1686; - assign n974 = n1705 & n1704 & n1703 & n1702 & n1701 & n1700 & n1698 & n1699; - assign n975 = n1713 & n1712 & n1711 & n1710 & n1709 & n1708 & n1706 & n1707; - assign n976 = n1721 & n1002 & n1730 & n1726; - assign n977 = n2298 & n2296 & n1936 & n1914 & n1684 & n963 & ~n166 & n949; - assign n978 = n2294 & n2295 & n1999 & n1913 & n2079 & n1998 & n1927 & n1937; - assign n979 = n1219 | n1243; - assign n980 = ~n116 | n979; - assign n981 = ~n116 | n287; - assign n982 = n798 & n1374 & n1224; - assign n983 = n1666 & n875 & n441; - assign n984 = n1201 | n1371; - assign n985 = n984 & n284 & n982 & n983; - assign n986 = ~n116 | n227; - assign n987 = ~n120 & n986 & (~n116 | n985); - assign n988 = ~n353 | n926; - assign n989 = ~n353 | n430; - assign n990 = ~n353 | ~n450; - assign n991 = n2162 & n2077 & n2161; - assign n992 = n1742 & n1741 & n1740 & n1739 & n1738 & n1737 & n1736 & n980; - assign n993 = n1735 & n1734 & n1733 & n1732 & ~n117 & n981; - assign n994 = (~n116 | n1144) & (~n353 | n1677); - assign n995 = n987 & n994 & n993 & n992 & n991 & n990 & n988 & n989; - assign n996 = ~n167 | n567; - assign n997 = ~n167 | n1157; - assign n998 = ~n167 | n566; - assign n999 = ~n167 | n508; - assign n1000 = ~n167 | n529; - assign n1001 = n1744 & n270 & n1743; - assign n1002 = n1722 & n537; - assign n1003 = n384 & n1440 & (~n167 | n982); - assign n1004 = n1003 & n1002 & n1001 & n1000 & n999 & n998 & n996 & n997; - assign n1005 = ~n167 | n393; - assign n1006 = ~n167 | n1139; - assign n1007 = ~n167 | n1138; - assign n1008 = ~n167 | n984; - assign n1009 = (~n381 | n658) & (~n404 | n982); - assign n1010 = n1969 & n1997 & n1919 & n2059 & n1878 & n1901 & n1117 & n1879; - assign n1011 = n1010 & n1004 & n1009 & n1008 & n1007 & n1005 & n1006; - assign n1012 = n1250 & n1104; - assign n1013 = ~n404 | n1012; - assign n1014 = ~n167 | n474; - assign n1015 = ~n167 | n979; - assign n1016 = ~n167 | n495; - assign n1017 = ~n170 & (~n381 | n2297); - assign n1018 = ~n404 | n654; - assign n1019 = n1899 & n2062 & n1884 & n1939 & n2165 & n1882; - assign n1020 = n1019 & n1018 & n1017 & n1016 & n1014 & n1015; - assign n1021 = ~n167 | n442; - assign n1022 = n1021 & (~n167 | (n330 & n527)); - assign n1023 = ~n167 | n707; - assign n1024 = n2096 & n1905 & n2058; - assign n1025 = n1023 & n1024 & (~n105 | ~n167); - assign n1026 = n684 & n1418; - assign n1027 = n288 & n873; - assign n1028 = n1263 | n1371; - assign n1029 = n1341 & n522; - assign n1030 = n1029 & n1028 & n204 & n1027 & n1026 & n720; - assign n1031 = n1748 & n1747 & n1745 & n1746; - assign n1032 = n1754 & n1753 & n1752 & n1751 & n1749 & n1750; - assign n1033 = n1956 & n1965 & (~n404 | n1030); - assign n1034 = n1279 & n1342 & n2132; - assign n1035 = n2299 & n1881 & n1933 & n1906 & n1880 & n2060; - assign n1036 = n1035 & n1034 & n1033 & n1022 & n1032 & n1031 & n1025 & n648; - assign n1037 = n381 & (~n964 | ~n1678); - assign n1038 = ~n774 | ~n329 | ~n604; - assign n1039 = n404 & (~n918 | n1038 | ~n1756); - assign n1040 = ~n176 | n1230; - assign n1041 = n1214 | n1230; - assign n1042 = n1040 & n1041; - assign n1043 = ~n105 & n1336; - assign n1044 = ~n571 | n1043; - assign n1045 = n107 & (~n500 | ~n1665); - assign n1046 = n331 & n951 & n1155; - assign n1047 = ~n104 | n1046; - assign n1048 = ~n113 | n1080; - assign n1049 = ~n278 | n610; - assign n1050 = n778 & (~n107 | n2307); - assign n1051 = n1050 & n1049 & n1048 & n919 & ~n115 & n538; - assign n1052 = n346 & (~n1247 | ~n1415); - assign n1053 = n1490 & n1489 & n1488 & n1487 & n1486 & n1485 & ~n773 & n1484; - assign n1054 = n1289 & n1287 & n1288; - assign n1055 = (~n404 | n2307) & (~n571 | n1795); - assign n1056 = n2309 & (~n104 | (n529 & n1136)); - assign n1057 = n1804 & n1051 & n1802 & n838 & n138 & n1783 & n972; - assign n1058 = n2308 & n2231 & n2167 & n2083 & n1722 & n1679 & n997 & ~n1052; - assign n1059 = n1058 & n1057 & n1056 & n1055 & n1054 & n630 & n1053 & n730; - assign n1060 = n104 & (~n447 | ~n1026 | ~n1381); - assign n1061 = ~n107 | n522; - assign n1062 = (~n104 | n953) & (n720 | n1292); - assign n1063 = n1062 & n416 & n1061; - assign n1064 = n104 & (~n1336 | ~n1664); - assign n1065 = n113 & (~n331 | ~n755); - assign n1066 = n571 & (~n651 | ~n755 | ~n951); - assign n1067 = n571 & (~n206 | ~n952 | ~n1026); - assign n1068 = n107 & (~n206 | ~n1027 | ~n1330); - assign n1069 = ~n113 | n1043; - assign n1070 = ~n107 | n1026; - assign n1071 = ~n113 | n2374; - assign n1072 = n1854 & n255 & (n1292 | n1162); - assign n1073 = n1499 & n1497 & n1498; - assign n1074 = ~n1067 & ~n1068 & (~n165 | n793); - assign n1075 = n2306 & n1063 & n1169 & n1823 & n1180 & n1812; - assign n1076 = n1075 & n1074 & n756 & n1073 & n1072 & n1071 & n1069 & n1070; - assign n1077 = n738 & n739; - assign n1078 = n489 | ~n571; - assign n1079 = ~n571 | n1372; - assign n1080 = n529 & n1415; - assign n1081 = n1078 & n1079 & (~n571 | n1080); - assign n1082 = n1221 | n1260; - assign n1083 = n1082 & n287 & ~n109 & n219; - assign n1084 = n471 & n674 & n426; - assign n1085 = n263 & n653 & n356; - assign n1086 = n287 & n1082; - assign n1087 = n685 & n592; - assign n1088 = n1087 & n1086 & n1085 & n1084 & n317; - assign n1089 = ~n113 | n685; - assign n1090 = ~n113 | n592; - assign n1091 = ~n113 | n317; - assign n1092 = (~n113 | n1083) & (~n571 | n1088); - assign n1093 = n1957 & n2145 & n1280 & n2030 & n2180 & n2142; - assign n1094 = n1093 & n1081 & n1092 & n1091 & n1089 & n1090; - assign n1095 = ~n113 | n951; - assign n1096 = n1095 & (~n113 | n651); - assign n1097 = n1220 | n1265; - assign n1098 = n739 & n1097 & n195; - assign n1099 = ~n653 & (n381 | n930); - assign n1100 = ~n107 | n470; - assign n1101 = n1887 & n2068 & n2102; - assign n1102 = n392 & n508; - assign n1103 = ~n169 & n1101 & (~n107 | n1102); - assign n1104 = n1151 & n1375; - assign n1105 = n1243 | n1249; - assign n1106 = n1105 & n1104 & n329 & n822 & n654; - assign n1107 = ~n104 | n1331; - assign n1108 = ~n104 | n444; - assign n1109 = (~n104 | n1106) & (~n107 | n654); - assign n1110 = n2136 & n1946 & n2230 & n2223 & n2311 & n1916 & n2166; - assign n1111 = n1110 & n1103 & n1109 & n1108 & n396 & n1107; - assign n1112 = n1105 & n201; - assign n1113 = ~n1114 & n1112 & n467 & n1102; - assign n1114 = ~n523 | ~n604; - assign n1115 = n571 & (~n392 | ~n822 | n1114); - assign n1116 = n329 & ~n1114; - assign n1117 = ~n167 | n1105; - assign n1118 = ~n167 | n329; - assign n1119 = ~n278 | n523; - assign n1120 = (~n346 | n1116) & (n1102 | n1290); - assign n1121 = ~n166 & ((~n107 & ~n571) | n1104); - assign n1122 = n1616 & n1430 & n2156 & n2081 & n1681 & n996 & n1680 & n998; - assign n1123 = n2323 & n1111 & n1779 & n1181 & n139 & n1675 & n1001 & n973; - assign n1124 = n1123 & n1122 & n1121 & n1120 & n1119 & n1118 & n225 & n1117; - assign n1125 = n1197 | n1371; - assign n1126 = n1125 & n1028; - assign n1127 = n116 | n253; - assign n1128 = (~n749 | ~n752) & (~n327 | n1127); - assign n1129 = ~n682 & (n321 | n930); - assign n1130 = ~n104 | n526; - assign n1131 = ~n104 | n1138; - assign n1132 = ~n104 | n845; - assign n1133 = n1823 & (~n104 | (n875 & n1224)); - assign n1134 = n507 & n2168 & n2224 & n2144 & n1922 & n2137 & n1889 & n2067; - assign n1135 = n1134 & n1133 & n1132 & n434 & n413 & n1131 & n395 & n1130; - assign n1136 = n1797 & n1157 & n1796; - assign n1137 = ~n571 | n1136; - assign n1138 = ~i_15_ | n1225; - assign n1139 = n472 & n875 & n845; - assign n1140 = n1139 & n1138 & n984; - assign n1141 = n499 & n567; - assign n1142 = n226 & n526 & n1141 & n441; - assign n1143 = n525 & ~n450 & n191 & ~n268; - assign n1144 = n879 & n1147; - assign n1145 = n1206 | n1220; - assign n1146 = n361 & n1145 & n1144 & n658; - assign n1147 = n313 & n1152 & n752 & n1731 & n263 & n1676; - assign n1148 = n1147 & n658 & n685; - assign n1149 = n1866 & n1224 & n1166 & n738 & ~n99 & n631; - assign n1150 = n953 & n474 & n251 & n1149 & n1085 & n720; - assign n1151 = n1220 | n1257; - assign n1152 = n1197 | n1220; - assign n1153 = n447 & n1152 & n1151 & n333 & n316 & n313; - assign n1154 = n426 & n738; - assign n1155 = n1220 | n1258; - assign n1156 = n284 & n265 & n227; - assign n1157 = n1220 | n1241; - assign n1158 = n1248 & n1334 & n951; - assign n1159 = n1158 & n1157 & n1156 & n1155 & n969 & n968 & n309 & ~n450; - assign n1160 = n334 & n749; - assign n1161 = n752 & n1507; - assign n1162 = n251 & n762; - assign n1163 = n1250 & n1374 & n610 & n688 & n489 & n313; - assign n1164 = n1163 & n1162 & n1161 & n1160 & n798 & n979; - assign n1165 = n1868 & n1867 & n1104 & n430 & n319 & ~n268 & n198 & n206; - assign n1166 = n789 & n521 & n1145; - assign n1167 = n1166 & n1165 & n873 & n195 & n361; - assign n1168 = n1833 & n1832 & n1831 & n1830 & n1829 & n1828 & ~n110 & n1827; - assign n1169 = n1826 & n1825 & ~n1060 & n1824; - assign n1170 = n1853 & n1852 & n1851 & n1850 & n1849 & n1848 & n1847 & n1100; - assign n1171 = n1063 & n1808 & n1802; - assign n1172 = n534 & n1790 & (~n104 | n1159); - assign n1173 = n2364 & n2365 & n2169 & n1267 & n1266 & n433 & n2087 & n1921; - assign n1174 = n1173 & n1172 & n1171 & n1170 & n1135 & n1111 & n1168 & n1169; - assign n1175 = n1335 & n682; - assign n1176 = n1240 | n1376; - assign n1177 = n227 & n1250 & n540; - assign n1178 = n1507 & n952 & n967 & n969 & n1795 & n1165 & n1870 & n1869; - assign n1179 = n1178 & n1177 & n926 & n504 & n1176 & n191 & n1175 & n1097; - assign n1180 = n1818 & n1817 & n1816 & n1815 & n1814 & ~n114 & n1813; - assign n1181 = n1839 & n1838 & n1837 & n1836 & n1835 & n1834 & n1096 & ~n1115; - assign n1182 = n1865 & n1855 & n1137 & n1864 & n1863 & n1390; - assign n1183 = n1846 & n1845 & n1844 & n1843 & n1842 & ~n118 & n414; - assign n1184 = n1812 & n1794 & n569; - assign n1185 = n2367 & (~n571 | n1179); - assign n1186 = n2366 & n1958 & n1942 & n1409 & ~n115 & n1268; - assign n1187 = n1186 & n1185 & n1184 & n1183 & n1182 & n1181 & n1094 & n1180; - assign n1188 = ~n96 | n755; - assign n1189 = ~n163 | n1341; - assign n1190 = ~n163 | n522; - assign n1191 = ~n163 | n288; - assign n1192 = n1512 & n1511 & n1510 & n598 & n1508 & n1509; - assign n1193 = ~n163 | (n306 & n720); - assign n1194 = n2149 & n1860 & n1912 & n1954 & n2123 & n2088 & n2041 & n2122; - assign n1195 = n1194 & n1193 & n794 & n1192 & n1191 & n1190 & n1188 & n1189; - assign n1196 = i_11_ | ~n901; - assign n1197 = ~i_15_ | n1196; - assign n1198 = i_12_ | i_14_ | i_13_; - assign n1199 = i_12_ | ~i_13_; - assign n1200 = i_11_ | ~n900; - assign n1201 = ~i_15_ | n1200; - assign n1202 = ~i_9_ | ~i_10_; - assign n1203 = n1202 & n941; - assign n1204 = ~i_14_ | i_12_ | i_13_; - assign n1205 = i_11_ | n481; - assign n1206 = ~i_15_ | n1205; - assign n1207 = n1197 | n1198; - assign n1208 = ~i_12_ | n1196; - assign n1209 = ~i_11_ | ~n901; - assign n1210 = ~i_12_ | n1200; - assign n1211 = n1199 & n1204 & n1210 & n1209 & n226 & n1208 & n1207 & n1203; - assign n1212 = i_3_ | i_5_ | i_4_; - assign n1213 = n172 & ~n1212; - assign n1214 = ~i_8_ | n816; - assign n1215 = i_5_ & ~i_3_ & ~i_4_; - assign n1216 = i_5_ & ~i_3_ & i_4_; - assign n1217 = i_15_ | n1200; - assign n1218 = n1200 | n1204; - assign n1219 = i_15_ | n1196; - assign n1220 = i_14_ | n1199; - assign n1221 = ~i_14_ | n1199; - assign n1222 = n481 & n1202; - assign n1223 = n1196 | n1221; - assign n1224 = n1201 | n1220; - assign n1225 = n1200 | n1221; - assign n1226 = n266 & n1209 & n941 & n1208 & n265 & n1210; - assign n1227 = n1226 & n1225 & n1224 & n1223 & n749 & n1152; - assign n1228 = ~i_8_ & n136; - assign n1229 = i_5_ | i_3_ | ~i_4_; - assign n1230 = ~n172 | n1229; - assign n1231 = ~n186 & ~n1212; - assign n1232 = i_8_ | ~n122; - assign n1233 = i_8_ | n816; - assign n1234 = n1230 | n1232; - assign n1235 = n1234 & n459; - assign n1236 = ~i_5_ & i_3_ & ~i_4_; - assign n1237 = n172 & n174; - assign n1238 = i_15_ | n1209; - assign n1239 = ~n186 & n1216; - assign n1240 = i_15_ | n1205; - assign n1241 = i_15_ | n941; - assign n1242 = ~i_12_ | i_13_; - assign n1243 = i_14_ | n1242; - assign n1244 = ~i_12_ | ~i_13_; - assign n1245 = i_14_ | n1244; - assign n1246 = ~i_15_ | n941; - assign n1247 = n1241 | n1245; - assign n1248 = n1198 | n1246; - assign n1249 = i_15_ | n943; - assign n1250 = n1198 | n1249; - assign n1251 = i_6_ | ~i_7_; - assign n1252 = ~i_8_ & ~n1251; - assign n1253 = ~n186 & n1215; - assign n1254 = ~i_11_ | n1202; - assign n1255 = i_15_ | n1254; - assign n1256 = ~n186 & ~n1229; - assign n1257 = ~i_15_ | n943; - assign n1258 = ~i_15_ | n1254; - assign n1259 = ~i_11_ | n481; - assign n1260 = i_15_ | n1259; - assign n1261 = n1220 | n1255; - assign n1262 = n1238 | n1243; - assign n1263 = ~i_15_ | n1209; - assign n1264 = i_8_ & ~n1251; - assign n1265 = ~i_15_ | n1259; - assign n1266 = ~n107 | n226; - assign n1267 = ~n107 | n227; - assign n1268 = ~n113 | n227; - assign n1269 = n1957 & n1815 & n1826 & n1956; - assign n1270 = n1955 & n1476 & n1954 & n1953 & n1952 & n1951 & n1949 & n1950; - assign n1271 = n1270 & n1269 & n1268 & n1267 & n1266 & n228; - assign n1272 = ~n96 | n1207; - assign n1273 = ~n96 | n474; - assign n1274 = n1273 & ~n230 & n1272; - assign n1275 = ~n96 | n334; - assign n1276 = ~n97 | n331; - assign n1277 = ~n97 | n334; - assign n1278 = ~n96 | n313; - assign n1279 = ~n167 | n331; - assign n1280 = ~n113 | n1797; - assign n1281 = n1958 & n1271 & n1118 & ~n229 & n222 & n224; - assign n1282 = n1281 & n1280 & n1279 & n1278 & n1277 & n1276 & n485 & n1275; - assign n1283 = ~n167 | n309; - assign n1284 = ~n167 | n1247; - assign n1285 = ~n167 | n1248; - assign n1286 = n1285 & n1283 & n1284; - assign n1287 = ~n278 | n309; - assign n1288 = ~n278 | n1248; - assign n1289 = ~n278 | n1247; - assign n1290 = ~n104 & ~n165; - assign n1291 = ~n116 & ~n278; - assign n1292 = ~n104 & ~n107; - assign n1293 = n1204 | n1255; - assign n1294 = n1293 & n508; - assign n1295 = n288 & n879; - assign n1296 = n1908 & (n911 | n508); - assign n1297 = n1828 & n1907 & n1788 & n1651 & n1753 & n1748; - assign n1298 = n1904 & n1749 & n1906 & n1905 & n1692 & n1717 & n1671 & n1689; - assign n1299 = n1892 & n731 & n1893 & n728 & n1626 & n1477 & n1482 & n1560; - assign n1300 = n1896 & n1599 & n1898 & n1564 & n1589 & n1897 & n1577 & n1570; - assign n1301 = n1789 & n1820 & n1829 & n1831 & n1888 & n1793 & n1806 & n1887; - assign n1302 = n1889 & n1851 & n1850 & n1108 & n324 & ~n322 & ~n164 & n320; - assign n1303 = n1737 & n1735 & n1021 & n986 & n1881 & n1880 & n1878 & n1879; - assign n1304 = n1886 & n1885 & n1884 & n1883 & n1773 & n1882 & n1777 & n1784; - assign n1305 = n1504 & n1501 & n1669 & n1875 & n1703 & n1874 & n1872 & n1873; - assign n1306 = n1693 & n1695 & n1686 & n1877 & n1711 & n1690 & n1876 & n1673; - assign n1307 = n852 & n1474 & n1871 & n1487 & n1509 & n1451 & n1547 & n1552; - assign n1308 = n1529 & n1539 & n1590 & n1593 & n1571 & n1572 & n1567 & n1601; - assign n1309 = ~n116 & ~n294; - assign n1310 = n617 & n306 & n305; - assign n1311 = n266 & n1310; - assign n1312 = ~n98 | n331; - assign n1313 = ~n163 | n331; - assign n1314 = ~n571 | n2375; - assign n1315 = n1890 & (~n165 | n331); - assign n1316 = n1315 & n1314 & n1312 & n1313; - assign n1317 = ~n107 | n191; - assign n1318 = n1922 & n1117 & n1920 & n1921; - assign n1319 = n1919 & n988 & n1769 & n1918 & n1917 & n1015 & n1825 & n1916; - assign n1320 = n1912 & n1557 & n1911 & n1544 & n1579 & n1582 & n1585 & n1587; - assign n1321 = n1603 & n1635 & n1555 & n1915 & n932 & n956 & n1913 & n1914; - assign n1322 = ~n404 | n442; - assign n1323 = n330 | ~n404; - assign n1324 = ~n404 | n527; - assign n1325 = n1324 & n1322 & n1323; - assign n1326 = ~n163 | n330; - assign n1327 = ~n163 | n527; - assign n1328 = ~n163 | n1261; - assign n1329 = n1328 & n1326 & n1327; - assign n1330 = n1221 | n1238; - assign n1331 = n1245 | n1257; - assign n1332 = n1221 | n943; - assign n1333 = n1206 | n1245; - assign n1334 = n1243 | n1246; - assign n1335 = i_15_ | n1223; - assign n1336 = n1221 | n1255; - assign n1337 = n1206 | n1243; - assign n1338 = ~n97 | n441; - assign n1339 = ~n98 | n1330; - assign n1340 = n1339 & n847 & n850 & n1338; - assign n1341 = n1220 | n1263; - assign n1342 = ~n167 | n1155; - assign n1343 = ~n113 | n1155; - assign n1344 = ~n97 | n1155; - assign n1345 = ~n96 | n1224; - assign n1346 = n1248 & n729; - assign n1347 = n423 & n1336 & n392; - assign n1348 = n684 & n1151; - assign n1349 = ~n165 & ~n321; - assign n1350 = ~n97 | n472; - assign n1351 = ~n98 | n472; - assign n1352 = n448 & (~n97 | (n873 & n1346)); - assign n1353 = ~i_0_ | i_1_; - assign n1354 = n1229 | n1353; - assign n1355 = n1251 | n1354; - assign n1356 = n816 | n1354; - assign n1357 = ~n136 | n1354; - assign n1358 = ~n122 | n1354; - assign n1359 = n1358 & n1357 & n1355 & n1356; - assign n1360 = n1271 & n2026 & (~n107 | n495); - assign n1361 = n2024 & n2023 & n2022 & n2021 & ~n456 & ~n457; - assign n1362 = n2018 & n2016 & n2020 & n1288 & n1791 & n2019 & n1732 & n1322; - assign n1363 = n2013 & n2005 & n2006 & n1536 & n1857 & n1472 & n619 & n718; - assign n1364 = n1212 | n1353; - assign n1365 = n883 & n864 & n867 & n885; - assign n1366 = n879 | ~n897; - assign n1367 = ~n897 | n1207; - assign n1368 = ~n1213 | n1251; - assign n1369 = n887 & n859 & n1621 & n2118 & n1623 & n1631; - assign n1370 = n1369 & n482 & n1368 & n1367 & n824 & n1366; - assign n1371 = ~i_14_ | n1242; - assign n1372 = n1246 | n1371; - assign n1373 = n1206 | n1371; - assign n1374 = n1217 | n1371; - assign n1375 = n1249 | n1371; - assign n1376 = ~i_14_ | n1244; - assign n1377 = n1255 | n1376; - assign n1378 = n1082 & n674; - assign n1379 = n1252 & n1253; - assign n1380 = n529 & n536; - assign n1381 = n1330 & n288; - assign n1382 = n526 & n653; - assign n1383 = n840 & n211 & n839 & n832; - assign n1384 = ~n98 | n1176; - assign n1385 = ~n98 | n430; - assign n1386 = ~n98 | n926; - assign n1387 = n1386 & n1384 & n1385; - assign n1388 = n1253 & n1264; - assign n1389 = ~n107 | n1176; - assign n1390 = ~n113 | n984; - assign n1391 = ~n168 & n1845 & (~n278 | n518); - assign n1392 = n2170 & n1661 & n1660 & n2169 & n2168 & n1008; - assign n1393 = n1798 & n2165 & n1762 & n1658 & n1827 & n1656; - assign n1394 = n1765 & n2167 & n1813 & n1848 & n1807 & n2166; - assign n1395 = n2155 & n2159 & n996 & n2164 & n2163 & n2162 & n2160 & n2161; - assign n1396 = ~n167 | n536; - assign n1397 = n406 & n1396 & n385; - assign n1398 = ~n96 | n875; - assign n1399 = n387 & n408 & n1398; - assign n1400 = ~n278 | n508; - assign n1401 = n407 & n1400 & n386; - assign n1402 = ~n97 | n526; - assign n1403 = ~n98 | n504; - assign n1404 = n447 & n649; - assign n1405 = n1374 & n1375; - assign n1406 = n521 & n910 & n653 & n191; - assign n1407 = n523 & n592 & n984 & n1125 & n528; - assign n1408 = n685 & n688 & n1138 & n566 & n495; - assign n1409 = ~n571 | n2376; - assign n1410 = n2139 & (n474 | ~n571); - assign n1411 = n1410 & n1409 & n1401 & n1005 & n999 & ~n570 & n384 & n569; - assign n1412 = n1397 & n2147 & (~n278 | n875); - assign n1413 = n2141 & n2145 & n1817 & n2144 & n1844 & n2143 & n2142 & n1767; - assign n1414 = n1413 & n1412 & n565 & n1399 & n562 & n560; - assign n1415 = n610 & n528; - assign n1416 = n566 & ~n1114; - assign n1417 = n1206 | n1376; - assign n1418 = n504 & n306; - assign n1419 = ~n278 | n489; - assign n1420 = n538 & n1419 & n1049; - assign n1421 = ~n96 | n685; - assign n1422 = n1421 & n626; - assign n1423 = ~n98 | n499; - assign n1424 = ~n98 | n500; - assign n1425 = ~n97 | n499; - assign n1426 = ~n97 | n500; - assign n1427 = ~n97 | n489; - assign n1428 = ~n97 | n1372; - assign n1429 = n793 & n752; - assign n1430 = n1293 | n509; - assign n1431 = ~n929 | n1372; - assign n1432 = (n509 | n536) & (n499 | ~n929); - assign n1433 = n1432 & n1431 & n1430 & n678 & ~n679; - assign n1434 = ~n98 | n798; - assign n1435 = ~n98 | n654; - assign n1436 = ~n163 | n1666; - assign n1437 = (~n343 | n654) & (n327 | n798); - assign n1438 = n1437 & n646 & n648 & n650 & n1436 & n1435 & n754 & n1434; - assign n1439 = ~n167 | n489; - assign n1440 = n1439 & n611; - assign n1441 = ~n1216 | n1353; - assign n1442 = n1251 | n1441; - assign n1443 = ~n122 | n1441; - assign n1444 = n816 | n1441; - assign n1445 = n1444 & n1442 & n1443; - assign n1446 = n474 & n226 & n875; - assign n1447 = ~n97 | n793; - assign n1448 = ~n97 | n522; - assign n1449 = ~n97 | n1341; - assign n1450 = n1449 & n1447 & n1448; - assign n1451 = ~n98 | n822; - assign n1452 = ~n97 | n651; - assign n1453 = ~n97 | n951; - assign n1454 = n1450 & n721; - assign n1455 = n855 & n860 & n727 & n1454; - assign n1456 = n2120 & n1953 & n2045 & n2119 & n2044 & n1893 & n1871 & n2148; - assign n1457 = n1456 & n736 & n735 & n560 & n364 & n222 & ~n162 & n199; - assign n1458 = ~n97 | n1145; - assign n1459 = ~n97 | n924; - assign n1460 = ~n98 | n1224; - assign n1461 = ~n97 | n777; - assign n1462 = ~n98 | n540; - assign n1463 = ~n98 | n1097; - assign n1464 = ~n97 | n540; - assign n1465 = ~n97 | n1097; - assign n1466 = ~n97 | n739; - assign n1467 = ~n97 | n752; - assign n1468 = ~n97 | n910; - assign n1469 = ~n98 | n910; - assign n1470 = ~n98 | n1152; - assign n1471 = ~n97 | n1152; - assign n1472 = ~n98 | n1155; - assign n1473 = n179 & ~n1233; - assign n1474 = ~n98 | n251; - assign n1475 = ~n97 | n251; - assign n1476 = ~n97 | n1261; - assign n1477 = ~n98 | n288; - assign n1478 = ~n97 | n654; - assign n1479 = ~n97 | n1375; - assign n1480 = ~n98 | n526; - assign n1481 = ~n98 | n441; - assign n1482 = ~n98 | n875; - assign n1483 = n1482 & n1481 & n1480 & n775 & n1478 & n1479; - assign n1484 = ~n98 | n489; - assign n1485 = ~n98 | n440; - assign n1486 = ~n98 | n1372; - assign n1487 = ~n98 | n1157; - assign n1488 = ~n98 | n530; - assign n1489 = ~n98 | n528; - assign n1490 = ~n98 | n529; - assign n1491 = ~n97 | n1151; - assign n1492 = ~n97 | n1250; - assign n1493 = ~n97 | n567; - assign n1494 = ~n98 | n1151; - assign n1495 = ~n98 | n1250; - assign n1496 = n772 & n1495 & n1494 & n365 & n1493 & n1491 & n1492; - assign n1497 = ~n96 | n651; - assign n1498 = ~n96 | n951; - assign n1499 = ~n96 | n1155; - assign n1500 = ~n163 | n393; - assign n1501 = ~n163 | n444; - assign n1502 = ~n163 | n329; - assign n1503 = ~n163 | n1105; - assign n1504 = ~n163 | n822; - assign n1505 = n1504 & n1503 & n1502 & n1500 & n1501; - assign n1506 = n334 & n1374; - assign n1507 = n1152 & n910; - assign n1508 = ~n96 | n707; - assign n1509 = ~n96 | n442; - assign n1510 = ~n96 | n1336; - assign n1511 = ~n96 | n1293; - assign n1512 = ~n96 | n656; - assign n1513 = ~n96 | n654; - assign n1514 = ~n163 | n1151; - assign n1515 = ~n163 | n1250; - assign n1516 = n1515 & n1513 & n1514; - assign n1517 = ~n96 | n1161; - assign n1518 = n1517 & n797 & n511 & ~n796; - assign n1519 = ~n96 | n798; - assign n1520 = ~n96 | n1374; - assign n1521 = n1520 & ~n795 & n1519; - assign n1522 = ~n163 | n567; - assign n1523 = ~n163 | n392; - assign n1524 = ~n163 | n508; - assign n1525 = ~n163 | n1331; - assign n1526 = n608 & n1525 & n1524 & n1522 & n1523; - assign n1527 = ~n163 | n984; - assign n1528 = ~n163 | n472; - assign n1529 = ~n163 | n226; - assign n1530 = ~n163 | n284; - assign n1531 = ~n163 | n2371; - assign n1532 = n1531 & n1530 & n1529 & n1527 & n1528; - assign n1533 = ~n97 | n1417; - assign n1534 = ~n97 | n521; - assign n1535 = ~n98 | n521; - assign n1536 = ~n98 | n1145; - assign n1537 = n1536 & n1535 & n1277 & n790 & n1533 & n1534; - assign n1538 = ~n163 | n707; - assign n1539 = ~n163 | n442; - assign n1540 = ~n163 | n1293; - assign n1541 = ~n163 | n656; - assign n1542 = ~n163 | n499; - assign n1543 = ~n163 | n1336; - assign n1544 = ~n96 | n1262; - assign n1545 = ~n96 | n473; - assign n1546 = ~n96 | n206; - assign n1547 = ~n163 | n206; - assign n1548 = ~n163 | n204; - assign n1549 = ~n163 | n447; - assign n1550 = ~n163 | n473; - assign n1551 = ~n163 | n1262; - assign n1552 = ~n163 | n251; - assign n1553 = ~n96 | n1028; - assign n1554 = ~n96 | n472; - assign n1555 = ~n96 | n284; - assign n1556 = n1399 & n1554 & n1555; - assign n1557 = ~n97 | n674; - assign n1558 = ~n97 | n653; - assign n1559 = ~n97 | n1082; - assign n1560 = ~n98 | n674; - assign n1561 = ~n98 | n2368; - assign n1562 = ~n98 | n653; - assign n1563 = ~n98 | n1082; - assign n1564 = ~n96 | n508; - assign n1565 = ~n96 | n1331; - assign n1566 = ~n96 | n393; - assign n1567 = ~n96 | n444; - assign n1568 = ~n96 | n329; - assign n1569 = n1568 & n1567 & n1566 & n1564 & n1565; - assign n1570 = ~n163 | n309; - assign n1571 = ~n163 | n1157; - assign n1572 = ~n163 | n1248; - assign n1573 = ~n163 | n1247; - assign n1574 = ~n163 | n688; - assign n1575 = ~n163 | n1334; - assign n1576 = ~n163 | n529; - assign n1577 = ~n163 | n536; - assign n1578 = n1577 & n1576 & n1575 & n1574 & n1573 & n1572 & n1570 & n1571; - assign n1579 = ~n96 | n309; - assign n1580 = ~n96 | n1334; - assign n1581 = ~n96 | n529; - assign n1582 = ~n96 | n536; - assign n1583 = ~n96 | n471; - assign n1584 = ~n96 | n1082; - assign n1585 = ~n96 | n674; - assign n1586 = ~n96 | n356; - assign n1587 = ~n96 | n287; - assign n1588 = n1587 & n242 & n1586 & n1585 & n1584 & n367 & n1583; - assign n1589 = ~n163 | n287; - assign n1590 = ~n163 | n317; - assign n1591 = ~n96 | n592; - assign n1592 = ~n163 | n471; - assign n1593 = ~n163 | n356; - assign n1594 = ~n163 | n195; - assign n1595 = n2127 & n2090 & n2124 & n2093 & n2042 & n1897; - assign n1596 = n1595 & n1594 & n1593 & n1592 & n1591 & n1589 & n1590; - assign n1597 = n2150 & n2004 & n1992 & n1387 & ~n100 & n192; - assign n1598 = n1597 & n1496 & n1053 & n1483 & n618 & n646; - assign n1599 = ~n163 | n979; - assign n1600 = ~n96 | n1335; - assign n1601 = ~n163 | n1207; - assign n1602 = ~n163 | n264; - assign n1603 = ~n96 | n879; - assign n1604 = ~n96 | n362; - assign n1605 = ~n96 | n709; - assign n1606 = n2046 & n2094 & n1898 & n2092 & n2126 & n2125 & n2047; - assign n1607 = n1606 & n1605 & n1604 & n1603 & n1602 & n1601 & n1599 & n1600; - assign n1608 = n172 & n173; - assign n1609 = n1607 & n1598 & n769 & n760; - assign n1610 = n2275 & n605 & n1556 & n594 & n830 & n811 & n829 & n1569; - assign n1611 = n2274 & n2272 & n1629 & n1634 & n1633 & n1635 & n842 & n2152; - assign n1612 = n706 & n1445 & n463 & n863 & n1359; - assign n1613 = n1207 | ~n1473; - assign n1614 = n227 | ~n1473; - assign n1615 = n879 | ~n1473; - assign n1616 = ~n98 | n1375; - assign n1617 = n753 & n1616 & n856; - assign n1618 = n858 & n1455; - assign n1619 = n715 | n123 | n818 | n181; - assign n1620 = n822 | n459; - assign n1621 = n822 | ~n897; - assign n1622 = n699 & n1621 & n1620 & n823; - assign n1623 = n227 | ~n897; - assign n1624 = n227 | n459; - assign n1625 = n1624 & n1614 & n1623 & n821 & n711 & n698; - assign n1626 = ~n97 | n875; - assign n1627 = n1626 & n1402 & n1350 & n1338 & n213 & ~n844; - assign n1628 = n898 | n1473 | n818; - assign n1629 = ~n96 | n392; - assign n1630 = n1569 & n1629 & n605; - assign n1631 = n875 | ~n897; - assign n1632 = n1357 & n1631 & n702 & n876; - assign n1633 = ~n96 | n822; - assign n1634 = ~n96 | n567; - assign n1635 = ~n96 | n1105; - assign n1636 = n1635 & n1634 & n1633 & n1630; - assign n1637 = n493 & n494 & n635 & n1607; - assign n1638 = n1422 & n250 & n1588 & n1596; - assign n1639 = n666 & n1339 & n1403 & n224 & n665 & n1961; - assign n1640 = n1639 & n663 & n448 & n207 & n871 & n764 & n874; - assign n1641 = n701 & n1358 & n1615 & n1366 & n1443; - assign n1642 = n2027 & n667 & n2152 & n1351 & n846 & n487 & n315 & n624; - assign n1643 = n1642 & n841 & n843 & n1627 & n727 & n669 & n810 & n1556; - assign n1644 = n831 & n1598 & n748; - assign n1645 = ~n136 | n1230; - assign n1646 = n1237 & ~n481 & ~n1214; - assign n1647 = n1236 & ~n1214 & n172 & ~n481; - assign n1648 = n891 & n1625 & n1632; - assign n1649 = n1247 & n610; - assign n1650 = n911 | n523; - assign n1651 = n1105 | n911; - assign n1652 = n907 | n1375; - assign n1653 = n911 | n1375; - assign n1654 = n911 | n567; - assign n1655 = n907 | n426; - assign n1656 = n907 | n592; - assign n1657 = n907 | n685; - assign n1658 = n907 | n653; - assign n1659 = n907 | n910; - assign n1660 = n907 | n1125; - assign n1661 = n907 | n682; - assign n1662 = n508 & n536; - assign n1663 = n1373 & n1125; - assign n1664 = n330 & n1293; - assign n1665 = n1664 & n1043; - assign n1666 = n1138 & n658; - assign n1667 = ~n278 | n527; - assign n1668 = ~n278 | n707; - assign n1669 = ~n278 | n442; - assign n1670 = n1669 & n1668 & n1667 & n950; - assign n1671 = ~n278 | n1105; - assign n1672 = ~n278 | n392; - assign n1673 = ~n278 | n444; - assign n1674 = ~n278 | n329; - assign n1675 = n1401 & n1674 & n1673 & n1671 & n1672; - assign n1676 = n1097 & n738 & n264 & n540 & n266; - assign n1677 = n1166 & n316 & n191 & ~n268; - assign n1678 = n965 & n1677 & n739 & n879 & n361; - assign n1679 = ~n278 | n1334; - assign n1680 = ~n278 | n604; - assign n1681 = ~n278 | n822; - assign n1682 = ~n278 | n530; - assign n1683 = n2081 & n1932 & n2156; - assign n1684 = n1683 & n1682 & n1681 & n1675 & n1054 & n1119 & n1679 & n1680; - assign n1685 = ~n165 | n393; - assign n1686 = ~n165 | n444; - assign n1687 = ~n165 | n566; - assign n1688 = ~n165 | n567; - assign n1689 = ~n165 | n1105; - assign n1690 = ~n165 | n822; - assign n1691 = ~n165 | n1796; - assign n1692 = ~n165 | n309; - assign n1693 = ~n165 | n1157; - assign n1694 = ~n165 | n529; - assign n1695 = ~n165 | n1248; - assign n1696 = ~n165 | n1372; - assign n1697 = ~n165 | n489; - assign n1698 = ~n165 | n1155; - assign n1699 = n1254 | ~n1379; - assign n1700 = ~n278 | n499; - assign n1701 = ~n278 | n500; - assign n1702 = ~n165 | n707; - assign n1703 = ~n165 | n442; - assign n1704 = ~n165 | n527; - assign n1705 = n2174 & n2220 & n1872 & n940 & n2029 & n1963; - assign n1706 = ~n165 | n265; - assign n1707 = ~n165 | n526; - assign n1708 = ~n165 | n984; - assign n1709 = ~n165 | n1138; - assign n1710 = ~n165 | n472; - assign n1711 = ~n165 | n226; - assign n1712 = ~n165 | n313; - assign n1713 = n2010 & n2194 & n2101 & n1875 & n1895 & n2054 & n1894; - assign n1714 = ~n278 | n471; - assign n1715 = ~n278 | n356; - assign n1716 = n2292 & (n1259 | ~n1388); - assign n1717 = ~n165 | n287; - assign n1718 = ~n278 | n592; - assign n1719 = ~n278 | n426; - assign n1720 = n2129 & n1929 & n2053 & n1873; - assign n1721 = n1720 & n1719 & n1718 & n1717 & n1716 & n1715 & ~n931 & n1714; - assign n1722 = ~n278 | n688; - assign n1723 = ~n278 | n774; - assign n1724 = ~n278 | n1372; - assign n1725 = ~n278 | n440; - assign n1726 = n1725 & n1724 & n1723 & n639; - assign n1727 = ~n278 | n1250; - assign n1728 = ~n278 | n1375; - assign n1729 = ~n278 | n1151; - assign n1730 = n1729 & n1728 & n1727 & n637; - assign n1731 = n739 & n1160; - assign n1732 = ~n116 | n2368; - assign n1733 = ~n116 | n592; - assign n1734 = ~n116 | n685; - assign n1735 = ~n116 | n317; - assign n1736 = ~n116 | n2373; - assign n1737 = ~n116 | n474; - assign n1738 = ~n116 | n910; - assign n1739 = ~n116 | n682; - assign n1740 = ~n116 | n1335; - assign n1741 = ~n116 | n1125; - assign n1742 = ~n116 | n495; - assign n1743 = ~n167 | n523; - assign n1744 = ~n167 | n392; - assign n1745 = ~n404 | n656; - assign n1746 = ~n404 | n707; - assign n1747 = ~n404 | n1336; - assign n1748 = ~n404 | n1293; - assign n1749 = ~n167 | n1262; - assign n1750 = ~n167 | n306; - assign n1751 = ~n167 | n504; - assign n1752 = ~n167 | n1330; - assign n1753 = ~n167 | n288; - assign n1754 = n2070 & n2106 & n1888 & n271; - assign n1755 = n317 & n1373 & n287; - assign n1756 = n1755 & n1408 & n1407 & n1380 & n1139 & n525 & ~n450 & n470; - assign n1757 = ~n404 | n951; - assign n1758 = ~n404 | n651; - assign n1759 = ~n167 | n500; - assign n1760 = ~n167 | n651; - assign n1761 = ~n167 | n951; - assign n1762 = ~n167 | n499; - assign n1763 = n2015 & n1970; - assign n1764 = n1763 & n1762 & n1761 & n1760 & n1759 & n1758 & n1757 & n1325; - assign n1765 = ~n167 | n592; - assign n1766 = ~n167 | n685; - assign n1767 = ~n167 | n1084; - assign n1768 = ~n167 | n356; - assign n1769 = ~n167 | n287; - assign n1770 = ~n167 | n317; - assign n1771 = n2095 & n1902 & n2056 & n2002 & n2055 & n1885; - assign n1772 = n1771 & n1770 & n1769 & n1768 & n1767 & n1765 & n1766; - assign n1773 = ~n404 | n444; - assign n1774 = ~n404 | n1105; - assign n1775 = ~n404 | n1331; - assign n1776 = n393 | ~n404; - assign n1777 = ~n404 | n822; - assign n1778 = n2219 & n1934 & n1966 & n2033 & n2130 & n2181 & n2064 & n1900; - assign n1779 = n1778 & n1730 & n1013 & n1777 & n1776 & n1775 & n1773 & n1774; - assign n1780 = ~n404 | n489; - assign n1781 = n2020 & n1883 & n2202; - assign n1782 = n2300 & n1967 & n2034 & n1903 & n1886 & n2063 & n2217 & n2131; - assign n1783 = n1782 & n1781 & n1780 & n1000 & n1397 & n1286 & n611 & n1726; - assign n1784 = ~n107 | n442; - assign n1785 = ~n107 | n656; - assign n1786 = ~n107 | n707; - assign n1787 = n1786 & n1785 & ~n1045 & n1784; - assign n1788 = ~n104 | n527; - assign n1789 = ~n104 | n1261; - assign n1790 = n1787 & n1788 & n1789; - assign n1791 = ~n571 | n1155; - assign n1792 = ~n571 | n2374; - assign n1793 = ~n571 | n1261; - assign n1794 = n1793 & n1792 & n1791 & n1044; - assign n1795 = n440 & n530; - assign n1796 = n536 & n729; - assign n1797 = n309 & n336; - assign n1798 = ~n107 | n1372; - assign n1799 = ~n104 | n1372; - assign n1800 = ~n107 | n774; - assign n1801 = n2019 & n2196 & n1920 & n1945; - assign n1802 = n1801 & n1800 & n1799 & n1798 & ~n108 & ~n112; - assign n1803 = n1047 & n1876 & n1472 & n854 & n1316 & n788; - assign n1804 = n1803 & n1794 & n1790 & n1764 & n974 & n1031; - assign n1805 = ~n104 | n473; - assign n1806 = ~n104 | n206; - assign n1807 = ~n107 | n1028; - assign n1808 = n1807 & n1805 & n1806; - assign n1809 = ~n113 | n499; - assign n1810 = ~n113 | n500; - assign n1811 = n1343 & (~n294 | (n793 & n1029)); - assign n1812 = n1811 & n1810 & n1809 & ~n1066 & n502 & ~n1065; - assign n1813 = ~n113 | n1028; - assign n1814 = ~n113 | n684; - assign n1815 = ~n113 | n1261; - assign n1816 = ~n571 | n1027; - assign n1817 = ~n113 | n1027; - assign n1818 = ~n113 | n2370; - assign n1819 = ~n104 | n707; - assign n1820 = ~n104 | n442; - assign n1821 = ~n104 | n499; - assign n1822 = ~n104 | n656; - assign n1823 = n1822 & n1821 & n1820 & n1819 & ~n106 & ~n1064; - assign n1824 = ~n104 | n1028; - assign n1825 = ~n107 | n527; - assign n1826 = ~n107 | n1261; - assign n1827 = ~n107 | n592; - assign n1828 = ~n104 | n287; - assign n1829 = ~n104 | n317; - assign n1830 = ~n104 | n471; - assign n1831 = ~n104 | n356; - assign n1832 = n2105 & n2066 & n1907; - assign n1833 = n2305 & n2179 & n2031 & n1947 & n1940 & n1917 & ~n111 & n432; - assign n1834 = ~n571 | n2210; - assign n1835 = ~n571 | n1112; - assign n1836 = ~n113 | n1375; - assign n1837 = n415 & n256; - assign n1838 = ~n113 | n822; - assign n1839 = ~n113 | n1113; - assign n1840 = n495 & n1125; - assign n1841 = n291 & ~n930; - assign n1842 = ~n113 | n2369; - assign n1843 = ~n113 | n910; - assign n1844 = ~n113 | n2376; - assign n1845 = ~n113 | n1125; - assign n1846 = ~n113 | n495; - assign n1847 = ~n104 | n362; - assign n1848 = ~n107 | n1125; - assign n1849 = ~n104 | n495; - assign n1850 = ~n104 | n1207; - assign n1851 = ~n104 | n474; - assign n1852 = ~n104 | n1125; - assign n1853 = ~n104 | n709; - assign n1854 = ~n113 | n2375; - assign n1855 = n1854 & n1069 & n1071; - assign n1856 = ~n97 | n1374; - assign n1857 = ~n97 | n1224; - assign n1858 = ~n97 | n798; - assign n1859 = n1858 & n1856 & n1857; - assign n1860 = ~n96 | n330; - assign n1861 = n1025 & n1684 & n1022 & n1859; - assign n1862 = n1861 & n1670 & n1192 & n1810 & n1860 & n1809; - assign n1863 = ~n571 | n1139; - assign n1864 = ~n113 | n1138; - assign n1865 = n2337 & n2082 & n2170 & n2107 & n2146 & n2138; - assign n1866 = n739 & n749; - assign n1867 = n684 & n306; - assign n1868 = n266 & n495; - assign n1869 = n441 & n658; - assign n1870 = n284 & n212; - assign n1871 = ~n98 | n474; - assign n1872 = ~n165 | n1261; - assign n1873 = ~n165 | n356; - assign n1874 = ~n165 | n206; - assign n1875 = ~n165 | n227; - assign n1876 = ~n404 | n1261; - assign n1877 = ~n165 | n1207; - assign n1878 = n226 | ~n404; - assign n1879 = n227 | ~n404; - assign n1880 = n206 | ~n404; - assign n1881 = n251 | ~n404; - assign n1882 = ~n404 | n474; - assign n1883 = ~n404 | n1157; - assign n1884 = ~n404 | n1207; - assign n1885 = n356 | ~n404; - assign n1886 = ~n404 | n1248; - assign n1887 = ~n107 | n444; - assign n1888 = ~n167 | n206; - assign n1889 = ~n104 | n226; - assign n1890 = n331 | ~n571; - assign n1891 = ~n163 | n926; - assign n1892 = n1551 & n1191 & n1511 & n1530 & n1540 & n1891; - assign n1893 = ~n98 | n879; - assign n1894 = ~n165 | n875; - assign n1895 = ~n165 | n284; - assign n1896 = n1895 & n1503 & n1524 & n1894 & n1667 & n1704; - assign n1897 = ~n163 | n674; - assign n1898 = ~n163 | n879; - assign n1899 = ~n404 | n979; - assign n1900 = ~n404 | n508; - assign n1901 = n284 | ~n404; - assign n1902 = ~n404 | n674; - assign n1903 = n309 | ~n404; - assign n1904 = n1903 & n1902 & n1901 & n1774 & n1899 & n1900; - assign n1905 = ~n167 | n1293; - assign n1906 = ~n404 | n1262; - assign n1907 = ~n104 | n674; - assign n1908 = (~n163 | n191) & (~n167 | n527); - assign n1909 = n999 & (n327 | (n1295 & n1294)); - assign n1910 = n293 | n875; - assign n1911 = ~n96 | n191; - assign n1912 = ~n96 | n527; - assign n1913 = ~n278 | n926; - assign n1914 = n191 | ~n278; - assign n1915 = ~n96 | n979; - assign n1916 = ~n107 | n1105; - assign n1917 = ~n107 | n287; - assign n1918 = ~n167 | n926; - assign n1919 = ~n167 | n284; - assign n1920 = ~n107 | n309; - assign n1921 = ~n107 | n926; - assign n1922 = ~n107 | n284; - assign n1923 = (n1649 | n911) & (n292 | n267); - assign n1924 = n291 & ~n453; - assign n1925 = n327 & ~n404; - assign n1926 = (n306 | n1925) & (n266 | ~n344); - assign n1927 = n190 | ~n278; - assign n1928 = ~n97 | n316; - assign n1929 = ~n278 | n317; - assign n1930 = n1929 & n1633 & n1586; - assign n1931 = n206 | ~n278; - assign n1932 = ~n278 | n1157; - assign n1933 = ~n167 | n251; - assign n1934 = ~n167 | n822; - assign n1935 = ~n167 | n216; - assign n1936 = ~n278 | n316; - assign n1937 = n216 | ~n278; - assign n1938 = n997 & n1937 & n1936 & n1935 & n1933 & n1934; - assign n1939 = ~n167 | n1207; - assign n1940 = ~n107 | n317; - assign n1941 = n1938 & n1014 & n1940 & n1939 & n1770 & n1768; - assign n1942 = ~n113 | n316; - assign n1943 = n1091 & n1942 & (n316 | ~n353); - assign n1944 = n1274 & (~n107 | n206); - assign n1945 = ~n107 | n1157; - assign n1946 = ~n107 | n822; - assign n1947 = ~n107 | n356; - assign n1948 = ~n107 | n216; - assign n1949 = ~n278 | n1261; - assign n1950 = n226 | ~n278; - assign n1951 = ~n96 | n226; - assign n1952 = n227 | ~n278; - assign n1953 = ~n97 | n822; - assign n1954 = ~n96 | n1261; - assign n1955 = ~n97 | n227; - assign n1956 = ~n167 | n1261; - assign n1957 = ~n113 | n1157; - assign n1958 = ~n113 | n1870; - assign n1959 = ~n96 | n774; - assign n1960 = n1959 & n1188; - assign n1961 = ~n97 | n2370; - assign n1962 = n1960 & n1961 & n835 & n1492 & n503 & n1466 & n1459 & n858; - assign n1963 = ~n278 | n331; - assign n1964 = n1963 & n1723 & n1727; - assign n1965 = ~n167 | n755; - assign n1966 = ~n167 | n1250; - assign n1967 = ~n167 | n774; - assign n1968 = ~n353 & ~n253 & ~n96 & ~n167; - assign n1969 = ~n165 | n334; - assign n1970 = n331 | ~n404; - assign n1971 = n1386 & n872 & n742 & n832 & n1515 & n1495 & n1969 & n1970; - assign n1972 = n339 | n341 | n342 | n345 | ~n1854 | ~n1971 | ~n1049 | ~n1835; - assign n1973 = (n291 | n337) & (~n354 | n1866); - assign n1974 = (n332 | n1292) & (~n453 | n1731); - assign n1975 = ~n360 & n1974 & (~n116 | n308); - assign n1976 = (n310 | ~n571) & (~n107 | n307); - assign n1977 = n1975 & n1976 & (~n348 | n1310); - assign n1978 = (n1291 | n674) & (n1925 | n604); - assign n1979 = (n289 | n327) & (~n351 | n610); - assign n1980 = (~n113 | n1112) & (~n346 | n687); - assign n1981 = n1980 & (~n268 | ~n404); - assign n1982 = (~n253 | n536) & (n330 | ~n930); - assign n1983 = (~n163 | n190) & (~n167 | n191); - assign n1984 = n1981 & n1978 & n1979 & n1982 & n1983 & n315 & n328 & n335; - assign n1985 = n192 & n196 & n199 & n207 & n210 & n1329 & n202; - assign n1986 = n1985 & n213 & n1325 & n262 & n303 & n1316 & n551 & n277; - assign n1987 = n334 & n1222; - assign n1988 = (n481 | n1042) & (~n116 | n1203); - assign n1989 = (n1042 | n1211) & (~n899 | n1222); - assign n1990 = n1446 | n459; - assign n1991 = ~n96 | n430; - assign n1992 = ~n97 | n430; - assign n1993 = n1992 & n1559 & n1545 & n1991 & n1581 & n1580 & n1583 & n1584; - assign n1994 = ~n278 | n1330; - assign n1995 = ~n278 | n472; - assign n1996 = ~n278 | n1335; - assign n1997 = ~n167 | n441; - assign n1998 = ~n278 | n1337; - assign n1999 = ~n278 | n430; - assign n2000 = ~n167 | n1337; - assign n2001 = ~n167 | n430; - assign n2002 = ~n167 | n1082; - assign n2003 = n591 & n644 & n311; - assign n2004 = ~n98 | ~n450; - assign n2005 = n2003 & n193 & n1561 & n615 & n189 & n2004 & n661 & n1424; - assign n2006 = n743 & n1460 & n1463 & n1485; - assign n2007 = n607 & n603 & n1189 & n791; - assign n2008 = n2007 & n1421 & n1328 & n600 & n1470 & n596; - assign n2009 = n1494 & n786 & n779; - assign n2010 = ~n165 | n1224; - assign n2011 = ~n98 | n1346; - assign n2012 = ~n97 | n2373; - assign n2013 = n2008 & n2009 & n1514 & n623 & n2012 & n2011 & n1698 & n2010; - assign n2014 = ~n165 | n440; - assign n2015 = ~n404 | n1155; - assign n2016 = n535 & n2014 & n2015; - assign n2017 = ~n120 & (n1292 | (n489 & n1155)); - assign n2018 = n2017 & n1736 & n1285 & n647 & ~n455 & ~n454 & ~n451 & ~n452; - assign n2019 = ~n104 | n440; - assign n2020 = ~n404 | n440; - assign n2021 = (n440 | ~n633) & (n1341 | n1925); - assign n2022 = (~n349 | n1248) & (~n382 | n1138); - assign n2023 = (~n294 | n445) & (n539 | n1097); - assign n2024 = ~n96 | n1348; - assign n2025 = (~n346 | n1151) & (~n348 | n444); - assign n2026 = n2025 & (~n98 | n1207); - assign n2027 = ~n97 | n1138; - assign n2028 = n1426 & n665 & n2027 & n1427 & n1449 & n1458 & n1491 & n1465; - assign n2029 = ~n278 | n1155; - assign n2030 = ~n113 | n1097; - assign n2031 = ~n107 | n1097; - assign n2032 = ~n167 | n1341; - assign n2033 = ~n167 | n1151; - assign n2034 = ~n167 | n440; - assign n2035 = ~n278 | n1145; - assign n2036 = ~n107 & ~n353; - assign n2037 = n1490 & n1563 & n1481; - assign n2038 = ~n163 | n1337; - assign n2039 = ~n163 | n430; - assign n2040 = n2038 & n2039; - assign n2041 = ~n163 | n1330; - assign n2042 = ~n163 | n1082; - assign n2043 = n2040 & n1528 & n2042 & n1543 & n1538 & n1550 & n2041 & n1508; - assign n2044 = ~n98 | n709; - assign n2045 = ~n98 | n1335; - assign n2046 = ~n163 | n709; - assign n2047 = ~n163 | n1335; - assign n2048 = n2047 & n2046 & n1500 & n1523; - assign n2049 = n2048 & n1629 & n1566 & n1575 & n1576 & n1592; - assign n2050 = ~n165 | n473; - assign n2051 = n1702 & n2050 & n1668; - assign n2052 = ~n165 | n709; - assign n2053 = ~n165 | n471; - assign n2054 = ~n165 | n441; - assign n2055 = ~n404 | n471; - assign n2056 = ~n404 | n1082; - assign n2057 = n2055 & n2056; - assign n2058 = ~n167 | n1336; - assign n2059 = ~n404 | n441; - assign n2060 = ~n404 | n1330; - assign n2061 = n2057 & n2060 & n2059 & n2058 & n1023 & n1740 & n1672 & n1679; - assign n2062 = ~n404 | n1335; - assign n2063 = ~n404 | n1334; - assign n2064 = n392 | ~n404; - assign n2065 = n2064 & n2062 & n2063; - assign n2066 = ~n104 | n1082; - assign n2067 = ~n104 | n472; - assign n2068 = ~n107 | n393; - assign n2069 = n2068 & n1853 & n2067 & n1744; - assign n2070 = ~n167 | n473; - assign n2071 = (~n107 | n392) & (~n404 | n473); - assign n2072 = ~n96 & ~n404; - assign n2073 = (~n295 | n1082) & (n1337 | n2072); - assign n2074 = (~n381 | n472) & (~n382 | n441); - assign n2075 = ~n278 | n495; - assign n2076 = ~n278 | n684; - assign n2077 = ~n353 | n361; - assign n2078 = ~n167 | n684; - assign n2079 = ~n278 | n1333; - assign n2080 = ~n278 | n361; - assign n2081 = ~n278 | n566; - assign n2082 = ~n113 | n566; - assign n2083 = ~n113 | n489; - assign n2084 = ~n167 | n1333; - assign n2085 = n2084 & n1657 & n1655 & n1814 & n2083 & n1759 & n2082 & n1766; - assign n2086 = (~n107 | n363) & (~n278 | n1138); - assign n2087 = ~n107 | n1333; - assign n2088 = ~n163 | n684; - assign n2089 = ~n163 | n1333; - assign n2090 = ~n163 | n685; - assign n2091 = n2090 & n1541 & n2089 & n724 & n1512 & n1549 & n2088; - assign n2092 = ~n163 | n495; - assign n2093 = ~n163 | n426; - assign n2094 = ~n163 | n362; - assign n2095 = ~n404 | n426; - assign n2096 = ~n167 | n656; - assign n2097 = n1742 & n1722 & n1734 & n1775 & n2095 & n2096; - assign n2098 = ~n165 | n447; - assign n2099 = ~n165 | n500; - assign n2100 = ~n165 | n362; - assign n2101 = ~n165 | n845; - assign n2102 = ~n107 | n1331; - assign n2103 = n2102 & n1745 & n1780 & n1107 & n1847 & n1849; - assign n2104 = n911 | n489; - assign n2105 = ~n104 | n426; - assign n2106 = ~n167 | n447; - assign n2107 = ~n571 | n1138; - assign n2108 = ~n162 & (~n930 | (n656 & n685)); - assign n2109 = (n323 | n495) & (~n346 | n684); - assign n2110 = ~n383 & (n447 | (~n113 & ~n278)); - assign n2111 = (~n404 | n1408) & (n1333 | n2072); - assign n2112 = n485 & n1005 & (~n294 | n475); - assign n2113 = ~n476 & (n327 | (n430 & n729)); - assign n2114 = (~n349 | n529) & (n291 | n1404); - assign n2115 = n1291 | n1082; - assign n2116 = (~n96 | n495) & (~n359 | n489); - assign n2117 = n2116 & (n481 | n459); - assign n2118 = n226 | ~n897; - assign n2119 = ~n98 | n682; - assign n2120 = ~n98 | n1125; - assign n2121 = n734 & n2120 & n2119 & n1480 & n1562 & n771 & n1489; - assign n2122 = ~n163 | n504; - assign n2123 = ~n163 | n1028; - assign n2124 = ~n163 | n592; - assign n2125 = ~n163 | n682; - assign n2126 = ~n163 | n1125; - assign n2127 = ~n163 | n653; - assign n2128 = n957 & n1486 & n1696 & n2127 & n2126 & n1522 & n2125; - assign n2129 = ~n165 | n592; - assign n2130 = ~n404 | n567; - assign n2131 = ~n404 | n1372; - assign n2132 = ~n404 | n499; - assign n2133 = n911 | n1372; - assign n2134 = n2133 & n1821 & n1799 & n1739 & n2132 & n2130 & n2131; - assign n2135 = n911 | n528; - assign n2136 = ~n104 | n567; - assign n2137 = ~n104 | n984; - assign n2138 = ~n571 | n984; - assign n2139 = (~n381 | n682) & (n910 | n1841); - assign n2140 = ~n278 | n1027; - assign n2141 = n2140 & ~n101 & ~n111; - assign n2142 = ~n113 | n1084; - assign n2143 = ~n278 | n2376; - assign n2144 = ~n107 | n2371; - assign n2145 = ~n113 | n1796; - assign n2146 = ~n113 | n1139; - assign n2147 = n1006 & n2146 & (~n167 | n362); - assign n2148 = ~n97 | n1125; - assign n2149 = ~n96 | n499; - assign n2150 = ~n97 | n1176; - assign n2151 = n1493 & n1558 & n2150 & n1553 & n2148 & n2149; - assign n2152 = ~n96 | n984; - assign n2153 = ~n278 | n1028; - assign n2154 = ~n96 | n1373; - assign n2155 = n2151 & n1634 & n1591 & n2154 & n2153 & n2152 & n1700; - assign n2156 = ~n278 | n567; - assign n2157 = ~n278 | n1125; - assign n2158 = ~n278 | n1373; - assign n2159 = n2158 & n2157 & n1724 & n1718 & n2156 & n945; - assign n2160 = ~n167 | n1028; - assign n2161 = ~n353 | n1373; - assign n2162 = ~n353 | n1176; - assign n2163 = ~n278 | n1176; - assign n2164 = ~n167 | n1372; - assign n2165 = ~n167 | n1125; - assign n2166 = ~n107 | n567; - assign n2167 = ~n113 | n1372; - assign n2168 = ~n107 | n984; - assign n2169 = ~n107 | n1373; - assign n2170 = ~n113 | n567; - assign n2171 = n667 & n666 & n1425; - assign n2172 = n783 & n1520 & n1498; - assign n2173 = n1205 | ~n1388; - assign n2174 = ~n278 | n951; - assign n2175 = ~n167 | n530; - assign n2176 = ~n278 | n521; - assign n2177 = ~n167 | n522; - assign n2178 = n2177 & n2175 & n2176; - assign n2179 = ~n107 | n540; - assign n2180 = ~n113 | n540; - assign n2181 = ~n167 | n1375; - assign n2182 = ~n928 | n1663; - assign n2183 = (~n278 | n653) & (n675 | n926); - assign n2184 = n533 & n879 & n504; - assign n2185 = n1200 | ~n1379; - assign n2186 = n620 & n194; - assign n2187 = n2186 & n645 & n312 & n616 & n214 & n1423 & n203 & n662; - assign n2188 = n1856 & n1535 & n1462 & n741; - assign n2189 = n1616 & n1469 & n1488; - assign n2190 = n1190 & n792 & n787 & n776 & n842 & n622 & n1287 & n1653; - assign n2191 = n2190 & n2189 & n595 & n599 & n1327 & n625 & n606 & n602; - assign n2192 = ~n98 | n522; - assign n2193 = ~n165 | n530; - assign n2194 = ~n165 | n1374; - assign n2195 = n1738 & n2193 & n2194; - assign n2196 = ~n104 | n530; - assign n2197 = n2196 & n1324 & ~n117 & n609; - assign n2198 = n1757 & (~n354 | (n191 & n1373)); - assign n2199 = ~n542 & (~n453 | (n526 & n1374)); - assign n2200 = (~n97 | n520) & (n680 | n910); - assign n2201 = (n327 | n524) & (~n294 | n531); - assign n2202 = ~n404 | n530; - assign n2203 = (~n165 | n525) & (~n340 | n951); - assign n2204 = (n309 | ~n348) & (~n359 | n528); - assign n2205 = n1863 & (~n930 | (n1293 & n1378)); - assign n2206 = n2205 & (~n359 | (n521 & n1176)); - assign n2207 = ~n582 & (n1292 | (n1294 & n1404)); - assign n2208 = ~n583 & (~n571 | (n536 & n1084)); - assign n2209 = (n285 | n875) & (~n104 | n1295); - assign n2210 = n508 & n467; - assign n2211 = (n288 | ~n346) & (n251 | ~n340); - assign n2212 = (~n97 | n216) & (~n165 | n508); - assign n2213 = n297 & n2212 & n380 & n325; - assign n2214 = n490 & n492 & n496; - assign n2215 = n1533 & n1447; - assign n2216 = ~n96 | n1026; - assign n2217 = ~n167 | n777; - assign n2218 = ~n167 | n793; - assign n2219 = ~n167 | n654; - assign n2220 = ~n278 | n651; - assign n2221 = (~n107 | n632) & (n1417 | n1968); - assign n2222 = ~n107 | n2372; - assign n2223 = ~n107 | n651; - assign n2224 = ~n107 | n1666; - assign n2225 = n2224 & n2223 & n2222 & n2221 & n1760 & n1070 & ~n110 & ~n634; - assign n2226 = (n1259 | ~n1388) & (~n253 | n793); - assign n2227 = n491 & (~n404 | (n682 & n1407)); - assign n2228 = ~n163 | n629; - assign n2229 = n2228 & n1699 & n1384 & n1326 & n1278 & n870 & ~n100 & n840; - assign n2230 = ~n104 | n1416; - assign n2231 = ~n104 | n629; - assign n2232 = n2231 & n2230 & n1758 & n1323 & n1289 & n1284 & ~n106 & n1118; - assign n2233 = (~n321 | n686) & (~n344 | n689); - assign n2234 = ~n690 & (~n404 | (n687 & n793)); - assign n2235 = ~n691 & (~n163 | (n651 & n1311)); - assign n2236 = ~n692 & (n597 | (~n167 & ~n930)); - assign n2237 = ~n693 & (n468 | n1309) & n2236; - assign n2238 = ~n344 & ~n353; - assign n2239 = (n304 | ~n346) & (n1333 | n2238); - assign n2240 = n2237 & n2239 & (~n354 | n1429); - assign n2241 = n2240 & n2235 & n2234 & n2233 & n2232 & n2229 & ~n169 & n1858; - assign n2242 = (n681 | n777) & (~n338 | n1417); - assign n2243 = (~n294 | n659) & (~n348 | n660); - assign n2244 = (~n268 | ~n381) & (n327 | n655); - assign n2245 = (~n253 | n330) & (~n453 | n798); - assign n2246 = (~n113 | n313) & (n291 | n447); - assign n2247 = (~n97 | n362) & (~n98 | n610); - assign n2248 = (~n104 | n265) & (n738 | n911); - assign n2249 = n248 & (n941 | ~n1379); - assign n2250 = n2242 & n2243 & n2244 & n2245 & n2246 & n2247 & n2249 & n2248; - assign n2251 = n391 & n277 & n683 & n550 & n672 & n1433 & n1438 & n643; - assign n2252 = n2251 & n594 & n598 & n601 & n1440 & n614 & n608 & n605; - assign n2253 = (~n107 | n1405) & (~n167 | n1406); - assign n2254 = (~n404 | n519) & (n710 | n1309); - assign n2255 = n2254 & (n357 | n471); - assign n2256 = ~n321 & ~n346; - assign n2257 = (n2256 | n910) & (n2238 | n1337); - assign n2258 = (~n294 | n708) & (~n571 | n1086); - assign n2259 = (~n97 | n429) & (~n321 | n1405); - assign n2260 = n2259 & (n327 | n1347); - assign n2261 = n2260 & n2257 & n2258 & n2255 & n863 & n446 & n1351 & n1350; - assign n2262 = (~n344 | n1334) & (~n348 | n707); - assign n2263 = n1040 & n2262 & (~n343 | n521); - assign n2264 = (~n96 | n1176) & (~n165 | n536); - assign n2265 = n2264 & n2263 & (n481 | n1234); - assign n2266 = n2265 & n697 & n1445 & n706 & n303 & n412 & n614 & n549; - assign n2267 = n1236 & n172 & ~n1233; - assign n2268 = n2039 & n1857 & n1856; - assign n2269 = n1272 & n233 & n1911; - assign n2270 = n486 & ~n800 & (~n163 | n799); - assign n2271 = (~n97 | n763) & (~n98 | n330); - assign n2272 = n1421 & n218 & n827; - assign n2273 = n196 & (~n97 | n195); - assign n2274 = n2273 & n814 & ~n813 & ~n812 & n496 & n492 & n428 & n490; - assign n2275 = n626 & n624; - assign n2276 = ~n1233 & n1237; - assign n2277 = ~n1612 | n181 | n820 | n2276 | n1646 | ~n1858; - assign n2278 = n826 & (n459 | (n481 & n474)); - assign n2279 = n565 & n217 & n881 & n806 & n808 & n807; - assign n2280 = n2279 & n2216 & n1955 & n1928 & ~n878 & ~n877 & n422 & n503; - assign n2281 = n854 & n862 & n866 & n1644 & n1643 & n838; - assign n2282 = n2281 & n1641 & n868 & n1640 & n1636 & n1632 & n1637 & n1638; - assign n2283 = n1251 & ~n122 & ~n136; - assign n2284 = (~n899 | ~n900) & (~n1608 | n2283); - assign n2285 = n1648 & ~n132 & n884; - assign n2286 = ~n1237 | n2283; - assign n2287 = n2286 & (n459 | (n474 & ~n819)); - assign n2288 = n731 & n728 & n2012 & n2011 & n920 & n1858 & n922 & n1455; - assign n2289 = n506 & n1430; - assign n2290 = n2099 & n2076 & n2153; - assign n2291 = n2140 & (~n930 | (n755 & n1418)); - assign n2292 = (~n165 | n426) & (~n278 | n287); - assign n2293 = n2185 & n2173 & n1952; - assign n2294 = n2293 & n2158 & n1969 & n2193 & n2014 & n2035 & n2176 & n1950; - assign n2295 = n2163 & n243 & n2080; - assign n2296 = (~n165 | n971) & (~n278 | n966); - assign n2297 = n749 & n1161; - assign n2298 = n1420 & (~n930 | n2297); - assign n2299 = n1876 & n2160 & n2078 & n2032 & n2177 & n2218; - assign n2300 = n2175 & n2164 & n1439; - assign n2301 = n2084 & n2001 & n1918; - assign n2302 = n2301 & n2000 & n1935 & n1118 & ~n1039 & ~n1037 & ~n168 & n995; - assign n2303 = n150 & n228 & (~n167 | n362); - assign n2304 = n2303 & n1764 & n1036 & n1783 & n1011 & n1779 & n1020 & n1772; - assign n2305 = (~n104 | n1087) & (~n107 | n1077); - assign n2306 = n1640 & n1195 & n811 & n1808 & n1036 & n963; - assign n2307 = n688 & n1380; - assign n2308 = n742 & n1453 & n1959 & n1419 & n1932 & n1682 & n2014 & n2193; - assign n2309 = n2256 | n969; - assign n2310 = ~n1099 & (~n404 | (n287 & n1087)); - assign n2311 = ~n107 | n1046; - assign n2312 = n2310 & n2311 & n2223; - assign n2313 = (n292 | n1098) & (n1349 | n1097); - assign n2314 = (~n104 | ~n109) & (~n354 | n739); - assign n2315 = (~n165 | n263) & (~n571 | n1136); - assign n2316 = (n317 | ~n346) & (n305 | ~n453); - assign n2317 = (~n98 | n774) & (n195 | n1292); - assign n2318 = n2312 & n2313 & n2314 & n2315 & n2316 & n2317 & n669 & n541; - assign n2319 = n1454 & n1433 & n785 & n746 & n841 & n831 & n1638 & n140; - assign n2320 = n993 & n1721 & n1096 & n1772 & n1168 & n1094 & n1076 & n1059; - assign n2321 = (~n294 | n654) & (~n929 | n1141); - assign n2322 = (~n165 | n1331) & (~n404 | n566); - assign n2323 = n2321 & n2322 & n1496 & n1516 & n1636 & n1526; - assign n2324 = n244 & n1478 & n1479 & n673 & n842 & n1915; - assign n2325 = ~n1128 & (~n340 | (n921 & n1335)); - assign n2326 = ~n1129 & (~n571 | (n1207 & n1840)); - assign n2327 = n2326 & (n1152 | (~n116 & n1841)); - assign n2328 = (~n346 | n1840) & (~n928 | n1126); - assign n2329 = (n362 | ~n381) & (n266 | n539); - assign n2330 = (n291 | n1250) & (n292 | n264); - assign n2331 = n2329 & n2330 & (n1292 | n879); - assign n2332 = n2331 & n2327 & n2328 & n2324 & n2325 & n2082 & n2170 & n2222; - assign n2333 = n510 & n1274 & (~n404 | n709); - assign n2334 = n2333 & n1411 & n745 & n760 & n1618 & n1518 & n1505 & n753; - assign n2335 = n938 & n1637 & n141; - assign n2336 = n2335 & n1020 & n992 & n1170 & n1183 & n1124 & n1804 & n1076; - assign n2337 = ~n113 | n1869; - assign n2338 = n2149 & n1451 & n1460 & n957 & n2099 & n1912; - assign n2339 = n1431 & (~n571 | n1142); - assign n2340 = (~n404 | n1140) & (n313 | n1924); - assign n2341 = (~n321 | n1156) & (n651 | n1349); - assign n2342 = n2341 & (~n349 | n1374); - assign n2343 = n2340 & n2342 & (n1662 | n509); - assign n2344 = (~n382 | n798) & (n323 | n951); - assign n2345 = n2344 & (~n294 | n1224); - assign n2346 = n1282 & (n292 | n334); - assign n2347 = n2343 & n2345 & n2346 & n2338 & n2339 & n1825 & n2145 & n2132; - assign n2348 = n517 & n418 & n335 & n1483 & n560 & n1438; - assign n2349 = n2348 & n1643 & n801 & n1532 & n780 & n1521; - assign n2350 = n987 & n949 & n975; - assign n2351 = n2350 & n1081 & n1011 & n1135 & n1182 & n1862 & n1059 & n1124; - assign n2352 = n2311 & n1517 & n946 & ~n114 & ~n108 & ~n112; - assign n2353 = ~n113 | n1143; - assign n2354 = n2353 & n2352 & n2337 & n1839 & ~n118 & n506; - assign n2355 = (~n97 | n1154) & (~n107 | n1153); - assign n2356 = n2355 & (~n113 | n1150); - assign n2357 = (~n167 | n1146) & (~n278 | n1148); - assign n2358 = n2357 & (~n96 | n1145); - assign n2359 = n2354 & n2356 & n2358 & n1414 & n678 & n424 & n372 & n262; - assign n2360 = n735 & n697 & n643 & n794 & n732 & n772; - assign n2361 = n2360 & n849 & n841 & n843 & n833 & n1627; - assign n2362 = n1630 & n874 & n871; - assign n2363 = n2362 & n1032 & n1004 & n1862 & n1855 & n1103 & n1787 & n1051; - assign n2364 = n1389 & n1317 & n1948; - assign n2365 = (~n107 | n1167) & (n1164 | n1292); - assign n2366 = n2083 & n1314 & n2167 & n627 & n1890 & n1048; - assign n2367 = n2353 & (~n294 | (n1149 & n1506)); - assign n2368 = n471 & n426 & n356; - assign n2369 = n1207 & n921; - assign n2370 = n206 & n762; - assign n2371 = n845 & n875 & n441; - assign n2372 = n682 & n266 & n495; - assign n2373 = n1207 & n470; - assign n2374 = n1293 & n469; - assign n2375 = n527 & n209; - assign n2376 = n879 & n470; - assign n2377 = n894 | n126; - assign n2378 = n906 | n126; - assign n2379 = n480 | n126; - assign n2380 = n590 | n126; - assign n2381 = n1259 & n1211 & ~i_12_ & n216; -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/s298/s298.v b/fpga_flow/benchmarks/Verilog/MCNC/s298/s298.v deleted file mode 100644 index 172950b5e..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/s298/s298.v +++ /dev/null @@ -1,69 +0,0 @@ -// Benchmark "s298.bench" written by ABC on Tue Mar 5 10:03:54 2019 - -module s298 ( clock, - G0, G1, G2, - G117, G132, G66, G118, G133, G67 ); - input G0, G1, G2, clock; - output G117, G132, G66, G118, G133, G67; - reg G10, G11, G12, G13, G14, G15, G16, G17, G18, G19, G20, G21, G22, G23; - wire n57, n59, n64, n66, n21_1, n26_1, n31_1, n36_1, n41_1, n46_1, n51_1, - n56_1, n61_1, n66_2, n71_1, n76_1, n81_1, n86_1; - assign n21_1 = ~G0 & ~G10; - assign n26_1 = ~G0 & (G10 ? (~G11 & (G12 | ~G13)) : G11); - assign n31_1 = ~G0 & ((G12 & (~G10 | ~G11)) | (G10 & G11 & ~G12)); - assign n36_1 = ~G0 & ((G11 & ((~G12 & G13) | (G10 & G12 & ~G13))) | (G13 & (~G10 | (~G11 & G12)))); - assign n41_1 = ~G0 & (G14 ^ (G23 | (G10 & G13 & n57))); - assign n57 = ~G11 & ~G12; - assign n46_1 = ~G0 & ~n59; - assign n59 = (G11 & (~G15 | (~G12 & G13 & ~G14 & ~G22))) | (~G15 & (G12 | ~G13 | G14 | ~G22)); - assign n51_1 = n59 & ((G13 & (~G14 | G16)) | (G12 & G14 & G16)); - assign n56_1 = n59 & ((~G13 & (G11 ? ~G12 : ~G14)) | (G14 & G17 & (G12 | G13))); - assign n61_1 = n59 & ((G14 & G18 & (G12 | G13)) | (~G13 & (~G14 | (G11 & ~G12)))); - assign n66_2 = n59 ? n64 : ~G10; - assign n64 = (G13 & (~G14 | G19)) | (G14 & ((~G11 & ~G12 & ~G13) | (G12 & G19))); - assign n71_1 = n59 ? (n66 & (G20 | (~G12 & ~G13))) : ~G10; - assign n66 = G14 & (~G11 | G12 | G13); - assign n76_1 = n59 & ((G12 & ((G11 & ~G13 & ~G14) | (G14 & G21))) | (G13 & G14 & G21)); - assign n81_1 = ~G0 & (G2 ^ G22); - assign n86_1 = ~G0 & (G1 ^ G23); - assign G117 = G18; - assign G132 = G20; - assign G66 = G16; - assign G118 = G19; - assign G133 = G21; - assign G67 = G17; - always @ (posedge clock) begin - G10 <= n21_1; - G11 <= n26_1; - G12 <= n31_1; - G13 <= n36_1; - G14 <= n41_1; - G15 <= n46_1; - G16 <= n51_1; - G17 <= n56_1; - G18 <= n61_1; - G19 <= n66_2; - G20 <= n71_1; - G21 <= n76_1; - G22 <= n81_1; - G23 <= n86_1; - end - initial begin - G10 <= 1'b0; - G11 <= 1'b0; - G12 <= 1'b0; - G13 <= 1'b0; - G14 <= 1'b0; - G15 <= 1'b0; - G16 <= 1'b0; - G17 <= 1'b0; - G18 <= 1'b0; - G19 <= 1'b0; - G20 <= 1'b0; - G21 <= 1'b0; - G22 <= 1'b0; - G23 <= 1'b0; - end -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/s38417/s38417.v b/fpga_flow/benchmarks/Verilog/MCNC/s38417/s38417.v deleted file mode 100644 index 3dc99f65b..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/s38417/s38417.v +++ /dev/null @@ -1,6731 +0,0 @@ -// Benchmark "TOP" written by ABC on Tue Mar 5 10:04:28 2019 - -module s38417 ( clock, - Pg3234, Pg3233, Pg3232, Pg3231, Pg3230, Pg3229, Pg3228, Pg3227, Pg3226, - Pg3225, Pg3224, Pg3223, Pg3222, Pg3221, Pg3220, Pg3219, Pg3218, Pg3217, - Pg3216, Pg3215, Pg3214, Pg3213, Pg3212, Pg2637, Pg1943, Pg1249, Pg563, - Pg51, - Pg27380, Pg26149, Pg26135, Pg26104, Pg25489, Pg25442, Pg25435, Pg25420, - Pg24734, Pg16496, Pg16437, Pg16399, Pg16355, Pg16297, Pg8275, Pg8274, - Pg8273, Pg8272, Pg8271, Pg8270, Pg8269, Pg8268, Pg8267, Pg8266, Pg8265, - Pg8264, Pg8263, Pg8262, Pg8261, Pg8260, Pg8259, Pg8258, Pg8251, Pg8249, - Pg8175, Pg8167, Pg8106, Pg8096, Pg8087, Pg8082, Pg8030, Pg8023, Pg8021, - Pg8012, Pg8007, Pg7961, Pg7956, Pg7909, Pg7519, Pg7487, Pg7425, Pg7390, - Pg7357, Pg7334, Pg7302, Pg7264, Pg7229, Pg7194, Pg7161, Pg7084, Pg7052, - Pg7014, Pg6979, Pg6944, Pg6911, Pg6895, Pg6837, Pg6782, Pg6750, Pg6712, - Pg6677, Pg6642, Pg6573, Pg6518, Pg6485, Pg6447, Pg6442, Pg6368, Pg6313, - Pg6231, Pg6225, Pg5796, Pg5747, Pg5738, Pg5695, Pg5686, Pg5657, Pg5648, - Pg5637, Pg5629, Pg5612, Pg5595, Pg5555, Pg5549, Pg5511, Pg5472, Pg5437, - Pg5388, Pg4590, Pg4450, Pg4323, Pg4321, Pg4200, Pg4090, Pg4088, Pg3993 ); - input Pg3234, Pg3233, Pg3232, Pg3231, Pg3230, Pg3229, Pg3228, Pg3227, - Pg3226, Pg3225, Pg3224, Pg3223, Pg3222, Pg3221, Pg3220, Pg3219, Pg3218, - Pg3217, Pg3216, Pg3215, Pg3214, Pg3213, Pg3212, Pg2637, Pg1943, Pg1249, - Pg563, Pg51, clock; - output Pg27380, Pg26149, Pg26135, Pg26104, Pg25489, Pg25442, Pg25435, - Pg25420, Pg24734, Pg16496, Pg16437, Pg16399, Pg16355, Pg16297, Pg8275, - Pg8274, Pg8273, Pg8272, Pg8271, Pg8270, Pg8269, Pg8268, Pg8267, Pg8266, - Pg8265, Pg8264, Pg8263, Pg8262, Pg8261, Pg8260, Pg8259, Pg8258, Pg8251, - Pg8249, Pg8175, Pg8167, Pg8106, Pg8096, Pg8087, Pg8082, Pg8030, Pg8023, - Pg8021, Pg8012, Pg8007, Pg7961, Pg7956, Pg7909, Pg7519, Pg7487, Pg7425, - Pg7390, Pg7357, Pg7334, Pg7302, Pg7264, Pg7229, Pg7194, Pg7161, Pg7084, - Pg7052, Pg7014, Pg6979, Pg6944, Pg6911, Pg6895, Pg6837, Pg6782, Pg6750, - Pg6712, Pg6677, Pg6642, Pg6573, Pg6518, Pg6485, Pg6447, Pg6442, Pg6368, - Pg6313, Pg6231, Pg6225, Pg5796, Pg5747, Pg5738, Pg5695, Pg5686, Pg5657, - Pg5648, Pg5637, Pg5629, Pg5612, Pg5595, Pg5555, Pg5549, Pg5511, Pg5472, - Pg5437, Pg5388, Pg4590, Pg4450, Pg4323, Pg4321, Pg4200, Pg4090, Pg4088, - Pg3993; - reg Pg8021, Ng2817, Ng2933, Ng13457, Ng2883, Ng2888, Ng2896, Ng2892, - Ng2903, Ng2900, Ng2908, Ng2912, Ng2917, Ng2924, Ng2920, Ng2984, Ng2985, - Ng2929, Ng2879, Ng2934, Ng2935, Ng2938, Ng2941, Ng2944, Ng2947, Ng2953, - Ng2956, Ng2959, Ng2962, Ng2963, Ng2966, Ng2969, Ng2972, Ng2975, Ng2978, - Ng2981, Ng2874, Ng1506, Ng1501, Ng1496, Ng1491, Ng1486, Ng1481, Ng1476, - Ng1471, Ng13439, Pg8251, Ng813, Pg4090, Ng809, Pg4323, Ng805, Pg4590, - Ng801, Pg6225, Ng797, Pg6442, Ng793, Pg6895, Ng789, Pg7334, Ng785, - Pg7519, Ng13423, Pg8249, Ng125, Pg4088, Ng121, Pg4321, Ng117, Pg8023, - Ng113, Pg8175, Ng109, Pg3993, Ng105, Pg4200, Ng101, Pg4450, Ng97, - Pg8096, Ng13407, Ng2200, Ng2195, Ng2190, Ng2185, Ng2180, Ng2175, - Ng2170, Ng2165, Ng13455, Ng3210, Ng3211, Ng3084, Ng3085, Ng3086, - Ng3087, Ng3091, Ng3092, Ng3093, Ng3094, Ng3095, Ng3096, Ng3097, Ng3098, - Ng3099, Ng3100, Ng3101, Ng3102, Ng3103, Ng3104, Ng3105, Ng3106, Ng3107, - Ng3108, Ng3155, Ng3158, Ng3161, Ng3164, Ng3167, Ng3170, Ng3173, Ng3176, - Ng3179, Ng3182, Ng3185, Ng3088, Ng3191, Ng3128, Ng3126, Ng3125, Ng3123, - Ng3120, Ng3110, Ng3139, Ng3135, Ng3147, Ng185, Ng130, Ng131, Ng129, - Ng133, Ng134, Ng132, Ng142, Ng143, Ng141, Ng145, Ng146, Ng144, Ng148, - Ng149, Ng147, Ng151, Ng152, Ng150, Ng154, Ng155, Ng153, Ng157, Ng158, - Ng156, Ng160, Ng161, Ng159, Ng163, Ng164, Ng162, Ng169, Ng170, Ng168, - Ng172, Ng173, Ng171, Ng175, Ng176, Ng174, Ng178, Ng179, Ng177, Ng186, - Ng189, Ng192, Ng231, Ng234, Ng237, Ng195, Ng198, Ng201, Ng240, Ng243, - Ng246, Ng204, Ng207, Ng210, Ng249, Ng252, Ng255, Ng213, Ng216, Ng219, - Ng258, Ng261, Ng264, Ng222, Ng225, Ng228, Ng267, Ng270, Ng273, Ng92, - Ng88, Ng83, Ng79, Ng74, Ng70, Ng65, Ng61, Ng56, Ng52, Ng11497, Ng11498, - Ng11499, Ng11500, Ng11501, Ng11502, Ng11503, Ng11504, Ng11505, Ng11506, - Ng11507, Ng11508, Ng408, Ng411, Ng414, Ng417, Ng420, Ng423, Ng427, - Ng428, Ng426, Ng429, Ng432, Ng435, Ng438, Ng441, Ng444, Ng448, Ng449, - Ng447, Ng312, Ng313, Ng314, Ng315, Ng316, Ng317, Ng318, Ng319, Ng320, - Ng322, Ng323, Ng321, Ng403, Ng404, Ng402, Ng450, Ng451, Ng452, Ng453, - Ng454, Ng279, Ng280, Ng281, Ng282, Ng283, Ng284, Ng285, Ng286, Ng287, - Ng288, Ng289, Ng290, Ng291, Ng299, Ng305, Ng298, Ng342, Ng349, Ng350, - Ng351, Ng352, Ng353, Ng357, Ng364, Ng365, Ng366, Ng367, Ng368, Ng372, - Ng379, Ng380, Ng381, Ng382, Ng383, Ng387, Ng394, Ng395, Ng396, Ng397, - Ng324, Ng554, Ng557, Ng510, Ng513, Ng523, Ng524, Ng564, Ng569, Ng570, - Ng571, Ng572, Ng573, Ng574, Ng565, Ng566, Ng567, Ng568, Ng489, Ng486, - Ng487, Ng488, Ng11512, Ng11515, Ng11516, Ng477, Ng478, Ng479, Ng480, - Ng484, Ng464, Ng11517, Ng11513, Ng11514, Ng528, Ng535, Ng542, Ng543, - Ng544, Ng548, Ng549, Ng8284, Ng558, Ng559, Ng576, Ng577, Ng575, Ng579, - Ng580, Ng578, Ng582, Ng583, Ng581, Ng585, Ng586, Ng584, Ng587, Ng590, - Ng593, Ng596, Ng599, Ng602, Ng614, Ng617, Ng620, Ng605, Ng608, Ng611, - Ng490, Ng493, Ng496, Ng506, Ng507, Pg16297, Ng525, Ng529, Ng530, Ng531, - Ng532, Ng533, Ng534, Ng536, Ng537, Ng538, Ng541, Ng630, Ng659, Ng640, - Ng633, Ng653, Ng646, Ng660, Ng672, Ng666, Ng679, Ng686, Ng692, Ng699, - Ng700, Ng698, Ng702, Ng703, Ng701, Ng705, Ng706, Ng704, Ng708, Ng709, - Ng707, Ng711, Ng712, Ng710, Ng714, Ng715, Ng713, Ng717, Ng718, Ng716, - Ng720, Ng721, Ng719, Ng723, Ng724, Ng722, Ng726, Ng727, Ng725, Ng729, - Ng730, Ng728, Ng732, Ng733, Ng731, Ng735, Ng736, Ng734, Ng738, Ng739, - Ng737, \[1612] , \[1594] , Ng853, Ng818, Ng819, Ng817, Ng821, Ng822, - Ng820, Ng830, Ng831, Ng829, Ng833, Ng834, Ng832, Ng836, Ng837, Ng835, - Ng839, Ng840, Ng838, Ng842, Ng843, Ng841, Ng845, Ng846, Ng844, Ng848, - Ng849, Ng847, Ng851, Ng852, Ng850, Ng857, Ng858, Ng856, Ng860, Ng861, - Ng859, Ng863, Ng864, Ng862, Ng866, Ng867, Ng865, Ng873, Ng876, Ng879, - Ng918, Ng921, Ng924, Ng882, Ng885, Ng888, Ng927, Ng930, Ng933, Ng891, - Ng894, Ng897, Ng936, Ng939, Ng942, Ng900, Ng903, Ng906, Ng945, Ng948, - Ng951, Ng909, Ng912, Ng915, Ng954, Ng957, Ng960, Ng780, Ng776, Ng771, - Ng767, Ng762, Ng758, Ng753, Ng749, Ng744, Ng740, Ng11524, Ng11525, - Ng11526, Ng11527, Ng11528, Ng11529, Ng11530, Ng11531, Ng11532, Ng11533, - Ng11534, Ng11535, Ng1095, Ng1098, Ng1101, Ng1104, Ng1107, Ng1110, - Ng1114, Ng1115, Ng1113, Ng1116, Ng1119, Ng1122, Ng1125, Ng1128, Ng1131, - Ng1135, Ng1136, Ng1134, Ng999, Ng1000, Ng1001, Ng1002, Ng1003, Ng1004, - Ng1005, Ng1006, Ng1007, Ng1009, Ng1010, Ng1008, Ng1090, Ng1091, Ng1089, - Ng1137, Ng1138, Ng1139, Ng1140, Ng1141, Ng966, Ng967, Ng968, Ng969, - Ng970, Ng971, Ng972, Ng973, Ng974, Ng975, Ng976, Ng977, Ng978, Ng986, - Ng992, Ng985, Ng1029, Ng1036, Ng1037, Ng1038, Ng1039, Ng1040, Ng1044, - Ng1051, Ng1052, Ng1053, Ng1054, Ng1055, Ng1059, Ng1066, Ng1067, Ng1068, - Ng1069, Ng1070, Ng1074, Ng1081, Ng1082, Ng1083, Ng1084, Ng1011, Ng1240, - Ng1243, Ng1196, Ng1199, Ng1209, Ng1210, Ng1250, Ng1255, Ng1256, Ng1257, - Ng1258, Ng1259, Ng1260, Ng1251, Ng1252, Ng1253, Ng1254, Ng1176, Ng1173, - Ng1174, Ng1175, Ng11539, Ng11542, Ng11543, Ng1164, Ng1165, Ng1166, - Ng1167, Ng1171, Ng1151, Ng11544, Ng11540, Ng11541, Ng1214, Ng1221, - Ng1228, Ng1229, Ng1230, Ng1234, Ng1235, Ng8293, Ng1244, Ng1245, Ng1262, - Ng1263, Ng1261, Ng1265, Ng1266, Ng1264, Ng1268, Ng1269, Ng1267, Ng1271, - Ng1272, Ng1270, Ng1273, Ng1276, Ng1279, Ng1282, Ng1285, Ng1288, Ng1300, - Ng1303, Ng1306, Ng1291, Ng1294, Ng1297, Ng1177, Ng1180, Ng1183, Ng1192, - Ng1193, Pg16355, Ng1211, Ng1215, Ng1216, Ng1217, Ng1218, Ng1219, - Ng1220, Ng1222, Ng1223, Ng1224, Ng1227, \[1605] , \[1603] , Ng1315, - Ng1316, Ng1345, Ng1326, Ng1319, Ng1339, Ng1332, Ng1346, Ng1358, Ng1352, - Ng1365, Ng1372, Ng1378, Ng1385, Ng1386, Ng1384, Ng1388, Ng1389, Ng1387, - Ng1391, Ng1392, Ng1390, Ng1394, Ng1395, Ng1393, Ng1397, Ng1398, Ng1396, - Ng1400, Ng1401, Ng1399, Ng1403, Ng1404, Ng1402, Ng1406, Ng1407, Ng1405, - Ng1409, Ng1410, Ng1408, Ng1412, Ng1413, Ng1411, Ng1415, Ng1416, Ng1414, - Ng1418, Ng1419, Ng1417, Ng1421, Ng1422, Ng1420, Ng1424, Ng1425, Ng1423, - Ng1512, Ng1513, Ng1511, Ng1515, Ng1516, Ng1514, Ng1524, Ng1525, Ng1523, - Ng1527, Ng1528, Ng1526, Ng1530, Ng1531, Ng1529, Ng1533, Ng1534, Ng1532, - Ng1536, Ng1537, Ng1535, Ng1539, Ng1540, Ng1538, Ng1542, Ng1543, Ng1541, - Ng1545, Ng1546, Ng1544, Ng1551, Ng1552, Ng1550, Ng1554, Ng1555, Ng1553, - Ng1557, Ng1558, Ng1556, Ng1560, Ng1561, Ng1559, Ng1567, Ng1570, Ng1573, - Ng1612, Ng1615, Ng1618, Ng1576, Ng1579, Ng1582, Ng1621, Ng1624, Ng1627, - Ng1585, Ng1588, Ng1591, Ng1630, Ng1633, Ng1636, Ng1594, Ng1597, Ng1600, - Ng1639, Ng1642, Ng1645, Ng1603, Ng1606, Ng1609, Ng1648, Ng1651, Ng1654, - Ng1466, Ng1462, Ng1457, Ng1453, Ng1448, Ng1444, Ng1439, Ng1435, Ng1430, - Ng1426, Ng11551, Ng11552, Ng11553, Ng11554, Ng11555, Ng11556, Ng11557, - Ng11558, Ng11559, Ng11560, Ng11561, Ng11562, Ng1789, Ng1792, Ng1795, - Ng1798, Ng1801, Ng1804, Ng1808, Ng1809, Ng1807, Ng1810, Ng1813, Ng1816, - Ng1819, Ng1822, Ng1825, Ng1829, Ng1830, Ng1828, Ng1693, Ng1694, Ng1695, - Ng1696, Ng1697, Ng1698, Ng1699, Ng1700, Ng1701, Ng1703, Ng1704, Ng1702, - Ng1784, Ng1785, Ng1783, Ng1831, Ng1832, Ng1833, Ng1834, Ng1835, Ng1660, - Ng1661, Ng1662, Ng1663, Ng1664, Ng1665, Ng1666, Ng1667, Ng1668, Ng1669, - Ng1670, Ng1671, Ng1672, Ng1680, Ng1686, Ng1679, Ng1723, Ng1730, Ng1731, - Ng1732, Ng1733, Ng1734, Ng1738, Ng1745, Ng1746, Ng1747, Ng1748, Ng1749, - Ng1753, Ng1760, Ng1761, Ng1762, Ng1763, Ng1764, Ng1768, Ng1775, Ng1776, - Ng1777, Ng1778, Ng1705, Ng1934, Ng1937, Ng1890, Ng1893, Ng1903, Ng1904, - Ng1944, Ng1949, Ng1950, Ng1951, Ng1952, Ng1953, Ng1954, Ng1945, Ng1946, - Ng1947, Ng1948, Ng1870, Ng1867, Ng1868, Ng1869, Ng11566, Ng11569, - Ng11570, Ng1858, Ng1859, Ng1860, Ng1861, Ng1865, Ng1845, Ng11571, - Ng11567, Ng11568, Ng1908, Ng1915, Ng1922, Ng1923, Ng1924, Ng1928, - Ng1929, Ng8302, Ng1938, Ng1939, Ng1956, Ng1957, Ng1955, Ng1959, Ng1960, - Ng1958, Ng1962, Ng1963, Ng1961, Ng1965, Ng1966, Ng1964, Ng1967, Ng1970, - Ng1973, Ng1976, Ng1979, Ng1982, Ng1994, Ng1997, Ng2000, Ng1985, Ng1988, - Ng1991, Ng1871, Ng1874, Ng1877, Ng1886, Ng1887, Pg16399, Ng1905, - Ng1909, Ng1910, Ng1911, Ng1912, Ng1913, Ng1914, Ng1916, Ng1917, Ng1918, - Ng1921, Ng2010, Ng2039, Ng2020, Ng2013, Ng2033, Ng2026, Ng2040, Ng2052, - Ng2046, Ng2059, Ng2066, Ng2072, Ng2079, Ng2080, Ng2078, Ng2082, Ng2083, - Ng2081, Ng2085, Ng2086, Ng2084, Ng2088, Ng2089, Ng2087, Ng2091, Ng2092, - Ng2090, Ng2094, Ng2095, Ng2093, Ng2097, Ng2098, Ng2096, Ng2100, Ng2101, - Ng2099, Ng2103, Ng2104, Ng2102, Ng2106, Ng2107, Ng2105, Ng2109, Ng2110, - Ng2108, Ng2112, Ng2113, Ng2111, Ng2115, Ng2116, Ng2114, Ng2118, Ng2119, - Ng2117, Ng2206, Ng2207, Ng2205, Ng2209, Ng2210, Ng2208, Ng2218, Ng2219, - Ng2217, Ng2221, Ng2222, Ng2220, Ng2224, Ng2225, Ng2223, Ng2227, Ng2228, - Ng2226, Ng2230, Ng2231, Ng2229, Ng2233, Ng2234, Ng2232, Ng2236, Ng2237, - Ng2235, Ng2239, Ng2240, Ng2238, Ng2245, Ng2246, Ng2244, Ng2248, Ng2249, - Ng2247, Ng2251, Ng2252, Ng2250, Ng2254, Ng2255, Ng2253, Ng2261, Ng2264, - Ng2267, Ng2306, Ng2309, Ng2312, Ng2270, Ng2273, Ng2276, Ng2315, Ng2318, - Ng2321, Ng2279, Ng2282, Ng2285, Ng2324, Ng2327, Ng2330, Ng2288, Ng2291, - Ng2294, Ng2333, Ng2336, Ng2339, Ng2297, Ng2300, Ng2303, Ng2342, Ng2345, - Ng2348, Ng2160, Ng2156, Ng2151, Ng2147, Ng2142, Ng2138, Ng2133, Ng2129, - Ng2124, Ng2120, Ng2256, \[1609] , Ng2257, Ng11578, Ng11579, Ng11580, - Ng11581, Ng11582, Ng11583, Ng11584, Ng11585, Ng11586, Ng11587, Ng11588, - Ng11589, Ng2483, Ng2486, Ng2489, Ng2492, Ng2495, Ng2498, Ng2502, - Ng2503, Ng2501, Ng2504, Ng2507, Ng2510, Ng2513, Ng2516, Ng2519, Ng2523, - Ng2524, Ng2522, Ng2387, Ng2388, Ng2389, Ng2390, Ng2391, Ng2392, Ng2393, - Ng2394, Ng2395, Ng2397, Ng2398, Ng2396, Ng2478, Ng2479, Ng2477, Ng2525, - Ng2526, Ng2527, Ng2528, Ng2529, Ng2354, Ng2355, Ng2356, Ng2357, Ng2358, - Ng2359, Ng2360, Ng2361, Ng2362, Ng2363, Ng2364, Ng2365, Ng2366, Ng2374, - Ng2380, Ng2373, Ng2417, Ng2424, Ng2425, Ng2426, Ng2427, Ng2428, Ng2432, - Ng2439, Ng2440, Ng2441, Ng2442, Ng2443, Ng2447, Ng2454, Ng2455, Ng2456, - Ng2457, Ng2458, Ng2462, Ng2469, Ng2470, Ng2471, Ng2472, Ng2399, Ng2628, - Ng2631, Ng2584, Ng2587, Ng2597, Ng2598, Ng2638, Ng2643, Ng2644, Ng2645, - Ng2646, Ng2647, Ng2648, Ng2639, Ng2640, Ng2641, Ng2642, Ng2564, Ng2561, - Ng2562, Ng2563, Ng11593, Ng11596, Ng11597, Ng2552, Ng2553, Ng2554, - Ng2555, Ng2559, Ng2539, Ng11598, Ng11594, Ng11595, Ng2602, Ng2609, - Ng2616, Ng2617, Ng2618, Ng2622, Ng2623, Ng8311, Ng2632, Ng2633, Ng2650, - Ng2651, Ng2649, Ng2653, Ng2654, Ng2652, Ng2656, Ng2657, Ng2655, Ng2659, - Ng2660, Ng2658, Ng2661, Ng2664, Ng2667, Ng2670, Ng2673, Ng2676, Ng2688, - Ng2691, Ng2694, Ng2679, Ng2682, Ng2685, Ng2565, Ng2568, Ng2571, Ng2580, - Ng2581, Pg16437, Ng2599, Ng2603, Ng2604, Ng2605, Ng2606, Ng2607, - Ng2608, Ng2610, Ng2611, Ng2612, Ng2615, Ng2704, Ng2733, Ng2714, Ng2707, - Ng2727, Ng2720, Ng2734, Ng2746, Ng2740, Ng2753, Ng2760, Ng2766, Ng2773, - Ng2774, Ng2772, Ng2776, Ng2777, Ng2775, Ng2779, Ng2780, Ng2778, Ng2782, - Ng2783, Ng2781, Ng2785, Ng2786, Ng2784, Ng2788, Ng2789, Ng2787, Ng2791, - Ng2792, Ng2790, Ng2794, Ng2795, Ng2793, Ng2797, Ng2798, Ng2796, Ng2800, - Ng2801, Ng2799, Ng2803, Ng2804, Ng2802, Ng2806, Ng2807, Ng2805, Ng2809, - Ng2810, Ng2808, Ng2812, Ng2813, Ng2811, Ng3054, Ng3079, Ng13475, - Ng3043, Ng3044, Ng3045, Ng3046, Ng3047, Ng3048, Ng3049, Ng3050, Ng3051, - Ng3052, Ng3053, Ng3055, Ng3056, Ng3057, Ng3058, Ng3059, Ng3060, Ng3061, - Ng3062, Ng3063, Ng3064, Ng3065, Ng3066, Ng3067, Ng3068, Ng3069, Ng3070, - Ng3071, Ng3072, Ng3073, Ng3074, Ng3075, Ng3076, Ng3077, Ng3078, Ng2997, - Ng2993, Ng2998, Ng3006, Ng3002, Ng3013, Ng3010, Ng3024, Ng3018, Ng3028, - Ng3036, Ng3032, Pg5388, Ng2986, Ng2987, Pg8275, Pg8274, Pg8273, Pg8272, - Pg8268, Pg8269, Pg8270, Pg8271, Ng3083, Pg8267, Ng2992, Pg8266, Pg8265, - Pg8264, Pg8262, Pg8263, Pg8260, Pg8261, Pg8259, Ng2990, Ng2991, Pg8258; - wire n4530, n4531_1, n4532, n4533, n4534, n4535, n4536_1, n4537, n4538, - n4539, n4540, n4541_1, n4542, n4543, n4544, n4545, n4546_1, n4547, - n4548, n4549, n4550_1, n4551, n4552, n4553, n4554, n4555_1, n4556, - n4557, n4558, n4559_1, n4560, n4561, n4562, n4563, n4564_1, n4565, - n4566, n4567, n4568_1, n4569, n4570, n4571, n4572, n4573_1, n4574, - n4575, n4576, n4577_1, n4578, n4579, n4580, n4581, n4582_1, n4583, - n4584, n4585, n4586_1, n4588, n4590, n4591_1, n4592, n4593, n4594, - n4596, n4598, n4600_1, n4601, n4602, n4603, n4604_1, n4606, n4608, - n4610, n4612, n4613_1, n4614, n4615, n4616, n4618, n4620, n4622, n4624, - n4625, n4626_1, n4628, n4630, n4632, n4633, n4634, n4636_1, n4638, - n4639, n4640_1, n4642, n4643, n4644, n4646, n4647, n4648_1, n4649, - n4650, n4651, n4652_1, n4653, n4654, n4655, n4656_1, n4657, n4658, - n4659, n4660_1, n4661, n4662, n4663, n4664_1, n4665, n4666, n4667, - n4668_1, n4669, n4670, n4671, n4672_1, n4673, n4674, n4675, n4676_1, - n4677, n4678, n4679, n4680_1, n4681, n4682, n4683, n4684_1, n4685, - n4686, n4687, n4688_1, n4689, n4690, n4691, n4692_1, n4693, n4694, - n4695, n4696_1, n4697, n4698, n4699, n4700_1, n4701, n4702, n4703, - n4704_1, n4705, n4706, n4707, n4708_1, n4709, n4710, n4711, n4712_1, - n4713, n4714, n4715, n4716_1, n4717, n4718, n4719, n4720_1, n4721, - n4722, n4723, n4724_1, n4725, n4726, n4727, n4728_1, n4729, n4730, - n4731, n4732_1, n4733, n4734, n4735, n4736, n4737_1, n4738, n4739, - n4740, n4741, n4742_1, n4743, n4744, n4745, n4746, n4747_1, n4748, - n4749, n4750, n4751, n4752_1, n4753, n4754, n4755, n4756_1, n4757, - n4758, n4759, n4760_1, n4761, n4762, n4763, n4764, n4765_1, n4766, - n4767, n4768, n4769_1, n4770, n4771, n4772, n4773, n4774_1, n4775, - n4776, n4777, n4778_1, n4779, n4780, n4781, n4782, n4783_1, n4784, - n4785, n4786, n4787_1, n4788, n4789, n4790, n4791, n4792_1, n4793, - n4794, n4795, n4796_1, n4797, n4798, n4799, n4800, n4801_1, n4802, - n4803, n4804, n4805_1, n4806, n4807, n4808, n4809, n4810_1, n4811, - n4812, n4813, n4814_1, n4815, n4816, n4817, n4818, n4819_1, n4820, - n4821, n4822, n4823, n4824_1, n4825, n4826, n4827, n4828, n4829_1, - n4830, n4831, n4832, n4833, n4834_1, n4835, n4836, n4837, n4838_1, - n4839, n4840, n4841, n4842_1, n4843, n4844, n4845, n4846_1, n4847, - n4848, n4849, n4850, n4851_1, n4852, n4853, n4854, n4855, n4856_1, - n4857, n4858, n4859, n4860, n4861_1, n4862, n4863, n4864, n4865, - n4866_1, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875, - n4876_1, n4877, n4878, n4879, n4880_1, n4881, n4882, n4883, n4884_1, - n4885, n4886, n4887, n4888_1, n4889, n4890, n4891, n4892_1, n4893, - n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901_1, n4902, n4903, - n4904, n4905, n4906, n4907, n4908, n4909, n4910_1, n4911, n4912, n4913, - n4914, n4915_1, n4916, n4917, n4918, n4919_1, n4920, n4921, n4922, - n4923, n4924_1, n4925, n4926, n4927, n4928_1, n4929, n4930, n4931, - n4932, n4933_1, n4934, n4935, n4936, n4937, n4938_1, n4939, n4940, - n4941, n4942, n4943_1, n4944, n4945, n4946, n4947, n4948_1, n4949, - n4950, n4951, n4952, n4953_1, n4954, n4955, n4956, n4957, n4958_1, - n4959, n4960, n4961, n4962, n4963_1, n4964, n4965, n4966, n4967, - n4968_1, n4969, n4970, n4971, n4972, n4973_1, n4974, n4975, n4976, - n4977, n4978_1, n4979, n4980, n4981, n4982, n4983_1, n4984, n4985, - n4986, n4987, n4988_1, n4989, n4990, n4991, n4992, n4993_1, n4994, - n4995, n4996, n4997, n4998_1, n4999, n5000, n5001, n5002, n5003_1, - n5004, n5005, n5006, n5007, n5008_1, n5009, n5010, n5011, n5012, - n5013_1, n5014, n5015, n5016, n5017, n5018_1, n5019, n5020, n5021, - n5022, n5023_1, n5024, n5025, n5026, n5027, n5028_1, n5029, n5030, - n5031, n5032, n5033_1, n5034, n5035, n5036, n5037, n5038_1, n5039, - n5040, n5041, n5042, n5043_1, n5044, n5045, n5046, n5047, n5049, n5050, - n5051, n5052, n5053_1, n5054, n5055, n5056, n5057, n5058_1, n5059, - n5060, n5061, n5062, n5063_1, n5064, n5065, n5066, n5067_1, n5068, - n5069, n5070, n5071, n5072_1, n5073, n5074, n5075, n5076, n5077_1, - n5078, n5079, n5080_1, n5081, n5082, n5083, n5084, n5087, n5089, n5091, - n5093, n5097, n5099, n5101, n5103, n5105_1, n5106, n5108, n5109, n5111, - n5112, n5114, n5115_1, n5117, n5118, n5122, n5124, n5126, n5127, n5128, - n5129, n5131, n5132, n5133, n5135_1, n5136, n5137, n5138, n5139, - n5140_1, n5142, n5144, n5145_1, n5147, n5149, n5151, n5153, n5154, - n5156, n5158, n5160_1, n5161, n5163, n5164, n5165_1, n5166, n5168, - n5170_1, n5171, n5173, n5174, n5175_1, n5176, n5178, n5180_1, n5181, - n5183, n5184, n5185_1, n5186, n5188, n5190_1, n5191, n5192, n5193, - n5196, n5198, n5200_1, n5202, n5204, n5206, n5208, n5210_1, n5213, - n5215_1, n5217, n5219, n5221, n5223, n5225_1, n5227, n5229, n5230_1, - n5232, n5234, n5236, n5239, n5241, n5243, n5245_1, n5247, n5249, n5251, - n5253, n5255_1, n5257, n5259, n5261, n5263, n5265_1, n5267, n5269, - n5271, n5273, n5275_1, n5277, n5279, n5281, n5284, n5286, n5289, n5291, - n5293, n5295_1, n5297, n5299, n5301, n5303, n5305_1, n5307, n5309, - n5311, n5312, n5313, n5314, n5315_1, n5316, n5317, n5318, n5319, - n5320_1, n5321, n5322, n5323, n5325_1, n5327, n5329, n5331, n5333, - n5335_1, n5337, n5339, n5340_1, n5342, n5344, n5345_1, n5347, n5349, - n5351, n5352, n5354, n5356, n5358, n5359, n5361, n5363, n5365_1, n5367, - n5369, n5371, n5373, n5375_1, n5377, n5379, n5381, n5383, n5385_1, - n5387, n5389, n5391, n5392, n5394, n5396, n5397, n5399, n5401, n5403, - n5404, n5406, n5408, n5410_1, n5411, n5413, n5415_1, n5417, n5419, - n5421, n5423, n5425_1, n5427, n5429, n5431, n5433, n5435_1, n5436, - n5437, n5438, n5439, n5440_1, n5441, n5442, n5443, n5444, n5445_1, - n5446, n5447, n5448, n5449, n5450_1, n5451, n5452, n5453, n5454, - n5455_1, n5456, n5457, n5458, n5459, n5460_1, n5461, n5462, n5463, - n5464, n5465_1, n5466, n5467, n5468, n5469, n5470_1, n5471, n5472, - n5473, n5474, n5475_1, n5476, n5477, n5478, n5479, n5480_1, n5481, - n5482, n5483, n5484, n5485_1, n5486, n5487, n5488, n5489, n5490_1, - n5491, n5492, n5493, n5494, n5495_1, n5496, n5497, n5498, n5499, - n5500_1, n5501, n5502, n5503, n5504, n5505_1, n5506, n5507, n5508, - n5509, n5510_1, n5511, n5512, n5513, n5514, n5515_1, n5516, n5517, - n5518, n5519, n5520_1, n5521, n5522, n5523, n5524, n5525_1, n5526, - n5527, n5528, n5529, n5530_1, n5531, n5532, n5533, n5534, n5535_1, - n5536, n5537, n5538, n5539, n5540_1, n5541, n5542, n5543, n5544, - n5545_1, n5546, n5547, n5548, n5549, n5550_1, n5551, n5552, n5553, - n5554, n5555_1, n5556, n5557, n5558, n5559, n5560_1, n5561, n5562, - n5563, n5564, n5565_1, n5566, n5567, n5568, n5569, n5570_1, n5571, - n5572, n5573, n5574, n5575_1, n5576, n5577, n5578, n5579, n5580_1, - n5581, n5582, n5583, n5584, n5585_1, n5586, n5587, n5588, n5589, - n5590_1, n5591, n5592, n5593, n5594, n5595_1, n5596, n5597, n5598, - n5599, n5600_1, n5601, n5602, n5603, n5604, n5605_1, n5606, n5607, - n5608, n5609, n5610_1, n5611, n5612, n5613, n5614, n5615_1, n5616, - n5617, n5618, n5619, n5620_1, n5621, n5622, n5623, n5624, n5625_1, - n5626, n5627, n5628, n5629, n5630_1, n5631, n5632, n5633, n5634, - n5635_1, n5636, n5637, n5638, n5639, n5640_1, n5641, n5642, n5643, - n5644, n5645_1, n5646, n5647, n5648, n5649, n5650_1, n5651, n5652, - n5653, n5654, n5655_1, n5656, n5657, n5658, n5659, n5660_1, n5661, - n5662, n5663, n5664, n5665_1, n5666, n5667, n5668, n5669, n5670_1, - n5671, n5672, n5677, n5679, n5681, n5683, n5685_1, n5687, n5689, n5691, - n5693, n5695_1, n5697, n5699, n5701, n5703, n5705_1, n5707, n5709, - n5711, n5713, n5715_1, n5717, n5719, n5721, n5723, n5725_1, n5727, - n5729, n5731, n5733, n5735_1, n5737, n5739, n5741, n5743, n5745_1, - n5747, n5817, n5818, n5819_1, n5820, n5821, n5822, n5823_1, n5824, - n5825, n5826, n5827, n5828_1, n5829, n5830, n5831, n5832, n5833_1, - n5834, n5835, n5836, n5837, n5838_1, n5839, n5840, n5841, n5842, - n5843_1, n5844, n5845, n5846, n5847, n5848_1, n5849, n5850, n5851, - n5852, n5853_1, n5854, n5855, n5856, n5857, n5858_1, n5859, n5860, - n5861, n5862, n5863_1, n5864, n5865, n5866, n5867, n5868_1, n5869, - n5870, n5871, n5872, n5873_1, n5874, n5875, n5876, n5877, n5878_1, - n5879, n5880, n5881, n5882, n5883_1, n5884, n5885, n5886, n5887, - n5888_1, n5889, n5890, n5891, n5892, n5893_1, n5894, n5895, n5896, - n5897, n5898_1, n5899, n5900, n5901, n5902, n5903_1, n5904, n5905, - n5906, n5907, n5908_1, n5909, n5910, n5911, n5912, n5913_1, n5914, - n5915, n5916, n5917, n5918_1, n5919, n5920, n5921, n5922, n5923_1, - n5924, n5925, n5926, n5927, n5928_1, n5929, n5930, n5931, n5932, - n5933_1, n5934, n5935, n5936, n5937, n5938_1, n5939, n5940, n5941, - n5942, n5943_1, n5944, n5945, n5946, n5947, n5948_1, n5949, n5950, - n5951, n5952, n5953_1, n5954, n5955, n5956, n5957, n5958_1, n5959, - n5960, n5961, n5962, n5963_1, n5964, n5965, n5966, n5967, n5968_1, - n5969, n5970, n5971, n5972, n5973_1, n5974, n5975, n5976, n5977, - n5978_1, n5979, n5980, n5981, n5982, n5983_1, n5984, n5985, n5986, - n5987, n5988_1, n5989, n5990, n5991, n5992, n5993_1, n5994, n5995, - n5996, n5997, n5998_1, n5999, n6000, n6001, n6002, n6003_1, n6004, - n6005, n6006, n6007, n6008_1, n6009, n6010, n6011, n6012, n6013_1, - n6014, n6015, n6016, n6017, n6018_1, n6019, n6020, n6021, n6022, - n6023_1, n6024, n6025, n6026, n6027, n6028_1, n6029, n6030, n6031, - n6032, n6033_1, n6034, n6035, n6036, n6037, n6038_1, n6039, n6040, - n6041, n6042, n6043_1, n6044, n6045, n6046, n6047, n6048_1, n6049, - n6050, n6051, n6052, n6053_1, n6054, n6055, n6056, n6057_1, n6058, - n6059, n6060, n6061, n6062_1, n6063, n6064, n6065, n6066_1, n6067, - n6068, n6069, n6070, n6071_1, n6072, n6073, n6074, n6075_1, n6076, - n6077, n6078, n6079, n6080_1, n6081, n6082, n6083, n6084_1, n6085, - n6086, n6087, n6088, n6089_1, n6090, n6091, n6092, n6093_1, n6094, - n6095, n6096, n6097, n6098_1, n6099, n6100, n6101, n6102_1, n6103, - n6104, n6105, n6106, n6107_1, n6108, n6109, n6110, n6111_1, n6112, - n6113, n6114, n6115, n6116_1, n6117, n6118, n6119, n6120_1, n6121, - n6122, n6123, n6124_1, n6125, n6126, n6127, n6128_1, n6129, n6130, - n6131, n6132, n6133_1, n6134, n6135, n6136, n6137, n6138_1, n6139, - n6140, n6141, n6142, n6143_1, n6144, n6145, n6146, n6147_1, n6148, - n6149, n6150, n6151_1, n6152, n6153, n6154, n6155_1, n6156, n6157, - n6158, n6159_1, n6160, n6161, n6162, n6163_1, n6164, n6165, n6166, - n6167_1, n6168, n6169, n6170, n6171_1, n6172, n6173, n6174, n6175_1, - n6176, n6177, n6178, n6179_1, n6180, n6181, n6182, n6183_1, n6184, - n6185, n6186, n6187_1, n6188, n6189, n6190, n6191_1, n6192, n6193, - n6194, n6195_1, n6196, n6197, n6198, n6199_1, n6200, n6201, n6202, - n6203_1, n6204, n6205, n6206, n6207_1, n6208, n6209, n6210, n6211_1, - n6212, n6213, n6214, n6215_1, n6216, n6217, n6218, n6219_1, n6221, - n6222, n6223_1, n6225, n6226, n6227_1, n6229, n6230, n6231_1, n6233, - n6234, n6235_1, n6236, n6237, n6238, n6239_1, n6240, n6241, n6242, - n6243, n6244_1, n6245, n6246, n6247, n6248, n6249_1, n6250, n6251, - n6252, n6253, n6254_1, n6255, n6256, n6257, n6258, n6259_1, n6260, - n6261, n6262, n6263_1, n6264, n6265, n6266, n6267_1, n6268, n6269, - n6270, n6271, n6272_1, n6273, n6274, n6275, n6276_1, n6277, n6278, - n6279, n6280, n6281_1, n6282, n6283, n6285_1, n6286, n6287, n6288, - n6289, n6290_1, n6291, n6292, n6293, n6294_1, n6295, n6296, n6297, - n6298, n6299_1, n6300, n6301, n6302, n6303_1, n6304, n6305, n6306, - n6307, n6308_1, n6309, n6310, n6311, n6312_1, n6313, n6314, n6315, - n6316, n6317_1, n6318, n6319, n6320, n6321_1, n6322, n6323, n6324, - n6325, n6326_1, n6327, n6328, n6329, n6330, n6331_1, n6332, n6333, - n6334, n6335, n6336_1, n6337, n6338, n6339, n6340, n6341_1, n6342, - n6343, n6344, n6345_1, n6346, n6347, n6348, n6349_1, n6350, n6351, - n6352, n6353_1, n6354, n6355, n6356, n6357, n6358_1, n6359, n6360, - n6361, n6362, n6363_1, n6364, n6365, n6366, n6367, n6368_1, n6369, - n6370, n6371, n6372, n6373_1, n6374, n6375, n6376, n6377, n6378_1, - n6379, n6380, n6381, n6382, n6383_1, n6384, n6385, n6386, n6387_1, - n6388, n6389, n6390, n6391_1, n6392, n6393, n6394, n6395_1, n6396, - n6397, n6398, n6399_1, n6400, n6401, n6402, n6403_1, n6404, n6405, - n6406, n6407, n6408_1, n6409, n6410, n6411, n6412_1, n6413, n6414, - n6415, n6416, n6417_1, n6418, n6419, n6420, n6421, n6422_1, n6423, - n6424, n6425, n6426_1, n6427, n6428, n6429, n6430, n6431_1, n6432, - n6433, n6434, n6435_1, n6436, n6437, n6438, n6439, n6440_1, n6441, - n6442, n6443, n6444, n6445_1, n6446, n6447, n6448, n6449, n6450_1, - n6451, n6452, n6453, n6454, n6455_1, n6456, n6457, n6458, n6459, - n6460_1, n6461, n6462, n6463, n6464, n6465_1, n6466, n6467, n6468, - n6469, n6470_1, n6471, n6472, n6473, n6474, n6476, n6478, n6479, - n6480_1, n6481, n6482, n6483, n6484, n6485_1, n6486, n6487, n6488, - n6489, n6490_1, n6491, n6492, n6493, n6494, n6495_1, n6496, n6497, - n6498, n6499, n6500_1, n6501, n6502, n6503, n6504, n6505_1, n6506, - n6507, n6508, n6509, n6510_1, n6511, n6512, n6513, n6514, n6515_1, - n6516, n6517, n6518, n6520_1, n6521, n6522, n6523, n6524, n6526, n6527, - n6528, n6529, n6530_1, n6531, n6532, n6533, n6534, n6535_1, n6536, - n6537, n6538, n6539, n6540_1, n6541, n6542, n6543, n6544, n6545_1, - n6546, n6547, n6548, n6549, n6550_1, n6551, n6552, n6553, n6554, - n6555_1, n6556, n6557, n6558, n6559, n6560_1, n6561, n6562, n6563, - n6564, n6565_1, n6566, n6567, n6568, n6569, n6570_1, n6571, n6572, - n6573, n6574_1, n6575, n6576, n6577, n6578, n6579_1, n6580, n6581, - n6582, n6583, n6584_1, n6585, n6586, n6587_1, n6588, n6589, n6591, - n6595, n6597_1, n6599, n6600, n6601, n6602_1, n6603, n6604, n6605, - n6606, n6607_1, n6608, n6610, n6612_1, n6614, n6615, n6616, n6617_1, - n6618, n6619, n6621, n6623, n6625, n6626, n6627_1, n6629, n6631, n6633, - n6635, n6637_1, n6639, n6641, n6643, n6645, n6647_1, n6649, n6651, - n6653, n6655, n6657_1, n6659, n6661, n6663, n6664, n6665, n6667_1, - n6669, n6671, n6673, n6675, n6677_1, n6679, n6681, n6683, n6685, - n6687_1, n6689, n6691, n6693, n6695, n6697_1, n6699, n6701, n6702_1, - n6703, n6705, n6707_1, n6709, n6711, n6713, n6715, n6717_1, n6719, - n6721, n6723, n6725, n6727_1, n6729, n6731, n6733, n6735, n6737_1, - n6739, n6740, n6741, n6743, n6745, n6747_1, n6749, n6751, n6753, n6755, - n6757_1, n6759, n6761, n6763, n6765, n6767_1, n6769, n6771, n6773, - n6775, n6777_1, n6779, n6781, n6783, n6785, n6787_1, n6789, n6791, - n6793, n6795, n6796, n6798, n6800, n6802_1, n6804, n6806, n6808, n6809, - n6811, n6813, n6815, n6816, n6818, n6820, n6822_1, n6823, n6825, - n6827_1, n6829, n6830, n6832_1, n6834, n6836, n6838, n6840, n6842_1, - n6843, n6845, n6847_1, n6849, n6850, n6852_1, n6854, n6856, n6857_1, - n6859, n6861, n6863, n6864, n6866, n6868, n6870, n6872_1, n6874, n6876, - n6877_1, n6879, n6881, n6883, n6884, n6886, n6888, n6890, n6891, n6893, - n6895, n6897_1, n6898, n6900, n6902_1, n6904, n6906, n6908, n6910, - n6911, n6913, n6915, n6917_1, n6918, n6920, n6922_1, n6924, n6925, - n6927, n6929, n6932, n6934, n6936_1, n6938, n6940, n6942, n6944, - n6946_1, n6948, n6949, n6950, n6951_1, n6952, n6953, n6955, n6957, - n6959, n6961_1, n6963, n6965, n6967, n6969, n6971_1, n6973, n6975, - n6977, n6978, n6979, n6980, n6981_1, n6982, n6983, n6985, n6987, n6989, - n6991_1, n6993, n6995, n6997, n6999, n7001_1, n7003, n7005, n7007, - n7009, n7011_1, n7013, n7015, n7017, n7019, n7021_1, n7023, n7025, - n7027, n7029, n7031_1, n7033, n7035, n7037, n7039, n7041_1, n7043, - n7045, n7047, n7049, n7051_1, n7053, n7055, n7057, n7059, n7061_1, - n7062, n7063, n7065, n7067, n7069, n7070, n7071_1, n7073, n7075, n7077, - n7078, n7079, n7081_1, n7083, n7085, n7086_1, n7087, n7089, n7091_1, - n7093, n7094, n7095, n7097, n7099, n7101_1, n7102, n7103, n7105, n7107, - n7109, n7110, n7111_1, n7113, n7115, n7117, n7118, n7119, n7121_1, - n7123, n7125, n7127, n7129, n7131_1, n7132, n7134, n7136_1, n7138, - n7139, n7141_1, n7143, n7145, n7147, n7149, n7151_1, n7153, n7155, - n7157, n7158, n7160_1, n7162, n7164, n7165, n7167_1, n7169, n7171, - n7173, n7175, n7177, n7179, n7181, n7183, n7184_1, n7186, n7188_1, - n7190, n7191, n7193, n7195, n7197, n7199, n7201, n7203, n7205, n7207, - n7209_1, n7210, n7212, n7214, n7216, n7217, n7219, n7221, n7223, n7225, - n7227, n7229, n7231, n7233, n7235, n7236, n7238_1, n7240, n7242_1, - n7243, n7245, n7247, n7249, n7251, n7253, n7255_1, n7257, n7259, n7261, - n7262, n7264, n7266, n7268, n7269, n7271, n7273, n7275, n7277, n7279, - n7281, n7283, n7285, n7287, n7288, n7290, n7292, n7294, n7295, n7297, - n7299, n7301, n7303, n7305, n7307, n7309, n7311, n7313, n7314, n7316, - n7318, n7320, n7321, n7323, n7325, n7327, n7329, n7331, n7333, n7335, - n7337, n7339, n7341, n7343, n7345, n7347, n7349, n7351, n7353, n7355, - n7357, n7359, n7361, n7363, n7365, n7367, n7369, n7371, n7373, n7375, - n7377, n7379, n7381, n7383, n7385, n7387, n7389, n7391, n7393, n7395, - n7397, n7399, n7401, n7403, n7405, n7407, n7409, n7411, n7413, n7415, - n7417, n7419, n7421, n7423, n7425, n7427, n7429, n7431, n7433, n7435, - n7437, n7439, n7441, n7443, n7445, n7447, n7449, n7451, n7453, n7455, - n7457, n7459, n7461, n7463, n7465, n7467, n7469, n7471, n7473, n7475, - n7477, n7479, n7481, n7483, n7485, n7487, n7489, n7491, n7493, n7495, - n7497, n7499, n7501, n7503, n7505, n7507, n7509, n7511, n7513, n7515, - n7517, n7519, n7521, n7523, n7525, n7527, n7529, n7531, n7533, n7535, - n7537, n7539, n7541, n7543, n7545, n7547, n7549, n7551, n7553, n7555, - n7557, n7559, n7561, n7563, n7565, n7567, n7569, n7571, n7573, n7575, - n7577, n7579, n7581, n7583, n7585, n7587, n7589, n7591, n7593, n7595, - n7597, n7599, n7601, n7603, n7605, n7607, n7609, n7611, n7613, n7615, - n7617, n7619, n7621, n7622, n7624, n7626, n7628, n7630, n7632, n7634, - n7636, n7638, n7640, n7642, n7644, n7646, n7648, n7650, n7652, n7654, - n7656, n7658, n7660, n7662, n7664, n7666, n7668, n7670, n7672, n7674, - n7676, n7678, n7680, n7682, n7684, n7686, n7688, n7690, n7692, n7694, - n7696, n7698, n7700, n7702, n7704, n7706, n7708, n7710, n7712, n7714, - n7716, n7718, n7720, n7722, n7724, n7726, n7728, n7730, n7732, n7734, - n7736, n7738, n7740, n7742, n7744, n7746, n7748, n7750, n7752, n7754, - n7756, n7758, n7760, n7762, n7764, n7766, n7768, n7770, n7772, n7774, - n7776, n7778, n7780, n7782, n7784, n7786, n7788, n7790, n7792, n7794, - n7796, n7798, n7800, n7802, n7804, n7806, n7808, n7810, n7812, n7814, - n7816, n7818, n7820, n7822, n7824, n7826, n7828, n7830, n7832, n7834, - n7836, n7838, n7840, n7842, n7844, n7846, n7848, n7850, n7852, n7854, - n7856, n7858, n7860, n7862, n7864, n7866, n7868, n7870, n7872, n7874, - n7876, n7878, n7880, n7882, n7884, n7886, n7888, n7890, n7892, n7894, - n7896, n7898, n7900, n7902, n7904, n7906, n7908, n7910, n7912, n7914, - n7916, n7918, n7920, n7922, n7924, n7926, n7928, n7930, n7932, n7934, - n7936, n7938, n7940, n7942, n7944, n7946, n7948, n7950, n7952, n7954, - n7956, n7958, n7960, n7962, n7964, n7966, n7968, n7970, n7972, n7974, - n7976, n7978, n7980, n7982, n7984, n7986, n7988, n7990, n7992, n7994, - n7996, n7998, n8000, n8002, n8004, n8006, n8008, n8010, n8012, n8014, - n8016, n8018, n8020, n8022, n8024, n8026, n8028, n8030, n8032, n8034, - n8036, n8038, n8040, n8042, n8044, n8046, n8048, n8050, n8052, n8054, - n8056, n8058, n8060, n8062, n8064, n8066, n8068, n8070, n8072, n8074, - n8076, n8078, n8080, n8082, n8084, n8086, n8088, n8090, n8092, n8094, - n8096, n8098, n8100, n8102, n8104, n8106, n8108, n8110, n8112, n8114, - n8116, n8118, n8120, n8122, n8124, n8126, n8128, n8130, n8132, n8134, - n8136, n8138, n8140, n8142, n8144, n8146, n8148, n8150, n8152, n8154, - n8156, n8158, n8160, n8162, n8164, n8166, n8168, n8170, n8172, n8174, - n8176, n8178, n8180, n8182, n8184, n8186, n8188, n8190, n8192, n8194, - n8196, n8198, n8200, n8202, n8204, n8206, n8208, n8210, n8212, n8214, - n8216, n8218, n8220, n8222, n8224, n8226, n8228, n8230, n8232, n8234, - n8236, n8238, n8240, n8242, n8244, n8246, n8248, n8250, n8252, n8254, - n8256, n8258, n8260, n8262, n8264, n8266, n8268, n8270, n8272, n8274, - n8276, n8278, n8280, n8282, n8284, n8286, n8288, n8290, n8292, n8294, - n8296, n8298, n8300, n8302, n8304, n8306, n8308, n8310, n8312, n8314, - n8316, n8318, n8320, n8322, n8324, n8326, n8328, n8330, n8332, n8334, - n8336, n8338, n8340, n8342, n8344, n8346, n8348, n8350, n8352, n8354, - n8356, n8358, n8360, n8362, n8364, n8366, n8368, n8370, n8372, n8374, - n8376, n8378, n8380, n8382, n8384, n8386, n8388, n8390, n8392, n8394, - n8396, n8398, n8400, n8402, n8404, n8406, n8408, n8410, n8412, n8414, - n8416, n8418, n8420, n8422, n8424, n8426, n8428, n8430, n8432, n8434, - n8436, n8438, n8440, n8442, n8444, n8446, n8448, n8450, n8451, n8452, - n8453, n8454, n8455, n8456, n8457, n8458, n8459, n8460, n8461, n8462, - n8463, n8464, n8465, n8466, n8467, n8468, n8469, n8470, n8471, n8472, - n8473, n8474, n8475, n8476, n8477, n8478, n8479, n8480, n8481, n8482, - n8483, n8484, n8485, n8486, n8487, n8488, n8489, n8490, n8491, n8492, - n8493, n8494, n8495, n8496, n8497, n8498, n8499, n8500, n8501, n8502, - n8503, n8504, n8505, n8506, n8507, n8508, n8509, n8510, n8511, n8512, - n8513, n8514, n8515, n8516, n8517, n8518, n8519, n8520, n8521, n8522, - n8523, n8524, n8525, n8526, n8527, n8528, n8529, n8530, n8531, n8532, - n8533, n8534, n8535, n8536, n8537, n8538, n8539, n8540, n8541, n8542, - n8543, n8544, n8545, n8546, n8547, n8548, n8549, n8550, n8551, n8552, - n8553, n8554, n8555, n8556, n8557, n8558, n8559, n8560, n8561, n8562, - n8563, n8564, n8565, n8566, n8567, n8568, n8569, n8570, n8571, n8572, - n8573, n8574, n8575, n8576, n8577, n8578, n8579, n8580, n8581, n8582, - n8583, n8584, n8585, n8586, n8587, n8588, n8589, n8590, n8591, n8592, - n8593, n8594, n8595, n8596, n8597, n8598, n8599, n8600, n8601, n8603, - n8605, n8606, n8607, n8608, n8609, n8610, n8611, n8612, n8613, n8614, - n8615, n8616, n8617, n8618, n8619, n8620, n8621, n8622, n8623, n8624, - n8625, n8626, n8627, n8628, n8629, n8630, n8631, n8632, n8633, n8634, - n8635, n8636, n8637, n8638, n8639, n8640, n8641, n8642, n8643, n8644, - n8645, n8646, n8647, n8648, n8649, n8650, n8651, n8652, n8653, n8654, - n8655, n8656, n8657, n8658, n8659, n8660, n8661, n8662, n8663, n8664, - n8665, n8666, n8667, n8668, n8669, n8670, n8671, n8672, n8673, n8674, - n8675, n8676, n8677, n8678, n8679, n8680, n8681, n8682, n8683, n8684, - n8685, n8686, n8687, n8688, n8689, n8690, n8691, n8692, n8693, n8694, - n8695, n8696, n8697, n8698, n8699, n8700, n8701, n8702, n8703, n8704, - n8705, n8706, n8707, n8708, n8709, n8710, n8711, n8712, n8713, n8714, - n8715, n8716, n8717, n8718, n8719, n8720, n8721, n8722, n8723, n8724, - n8725, n8726, n8727, n8728, n8729, n8730, n8731, n8732, n8733, n8734, - n8735, n8736, n8737, n8738, n8739, n8740, n8741, n8742, n8743, n8744, - n8745, n8746, n8747, n8748, n8749, n8750, n8752, n8753, n8754, n8755, - n8756, n8757, n8758, n8759, n8760, n8761, n8762, n8763, n8764, n8765, - n8766, n8767, n270_1, n274_1, n279_1, n284_1, n289_1, n294_1, n299_1, - n304_1, n309_1, n314_1, n319_1, n324_1, n329, n334_1, n339, n344, - n349_1, n353_1, n358_1, n362_1, n366_1, n370_1, n374_1, n378_1, n382_1, - n386, n390_1, n394, n398_1, n402_1, n406, n410_1, n414_1, n418_1, - n422_1, n426_1, n430_1, n435_1, n440_1, n445_1, n450_1, n455_1, n460_1, - n465, n470_1, n475_1, n480_1, n483_1, n488_1, n491_1, n496_1, n499_1, - n504_1, n507, n512_1, n515_1, n520_1, n523_1, n528_1, n531_1, n536_1, - n539_1, n544_1, n547_1, n552_1, n555_1, n560_1, n563_1, n568_1, n571_1, - n576_1, n579, n584_1, n587_1, n592_1, n595_1, n600_1, n603_1, n608_1, - n611_1, n616, n619_1, n624_1, n629_1, n634_1, n639_1, n644_1, n649_1, - n654_1, n659_1, n664_1, n669_1, n674, n679_1, n684_1, n689_1, n694, - n699_1, n704_1, n709_1, n714_1, n719_1, n724_1, n729, n734_1, n739_1, - n744_1, n749_1, n754_1, n759_1, n764_1, n769_1, n774, n779, n784_1, - n789_1, n794_1, n799_1, n804_1, n809_1, n814_1, n819_1, n824_1, n829_1, - n834_1, n839_1, n844_1, n848_1, n853_1, n858_1, n863_1, n868_1, n872_1, - n876_1, n880_1, n884_1, n888_1, n893_1, n898_1, n903_1, n908_1, n913_1, - n918_1, n923_1, n928, n933_1, n938_1, n943_1, n948_1, n953_1, n958, - n963_1, n968_1, n973_1, n978_1, n983_1, n988_1, n993_1, n998, n1003, - n1008_1, n1013_1, n1018, n1023_1, n1028_1, n1033, n1038_1, n1043_1, - n1048, n1053, n1058_1, n1063, n1068_1, n1073_1, n1078_1, n1083_1, - n1088_1, n1093_1, n1098_1, n1103_1, n1108, n1113_1, n1118_1, n1123_1, - n1128_1, n1133_1, n1138_1, n1143_1, n1148_1, n1153_1, n1158_1, n1163_1, - n1168_1, n1173_1, n1178, n1183_1, n1188_1, n1193_1, n1198_1, n1203_1, - n1208_1, n1213_1, n1218_1, n1223_1, n1228_1, n1233_1, n1238_1, n1243_1, - n1248_1, n1253_1, n1258_1, n1263_1, n1268, n1273_1, n1278, n1283_1, - n1288, n1293_1, n1298, n1303, n1308_1, n1313, n1318, n1323_1, n1328_1, - n1333_1, n1338_1, n1343_1, n1348, n1353, n1358_1, n1363_1, n1368, - n1373_1, n1378_1, n1383, n1388, n1393, n1398_1, n1403, n1408_1, n1413, - n1418_1, n1423_1, n1428_1, n1433_1, n1438_1, n1443_1, n1448_1, n1453, - n1458_1, n1463_1, n1468_1, n1473_1, n1478_1, n1483_1, n1488_1, n1493, - n1498, n1503, n1508, n1513_1, n1518_1, n1523_1, n1528, n1533_1, - n1537_1, n1542_1, n1546_1, n1551_1, n1555_1, n1560_1, n1564, n1569_1, - n1573, n1578, n1582_1, n1587, n1591, n1596, n1600_1, n1604_1, n1608, - n1613, n1618_1, n1623_1, n1627_1, n1631, n1635, n1639_1, n1643, - n1647_1, n1651, n1655, n1659_1, n1663_1, n1667, n1671_1, n1675_1, - n1679_1, n1683_1, n1687_1, n1691_1, n1695, n1699_1, n1703, n1707, - n1711_1, n1715, n1719, n1724_1, n1729_1, n1734_1, n1739_1, n1743, - n1747, n1752_1, n1756, n1761_1, n1765, n1770_1, n1774_1, n1779_1, - n1783_1, n1788, n1792_1, n1797_1, n1801_1, n1806_1, n1811_1, n1816_1, - n1821_1, n1825_1, n1829, n1833, n1838, n1843_1, n1848, n1853_1, - n1858_1, n1863, n1867_1, n1871_1, n1875_1, n1879_1, n1883_1, n1888, - n1892, n1897_1, n1902_1, n1906_1, n1911_1, n1915_1, n1920_1, n1925, - n1930_1, n1935_1, n1940_1, n1945_1, n1950, n1955, n1960_1, n1965, - n1970_1, n1975, n1980, n1985, n1990_1, n1995_1, n2000_1, n2005_1, - n2010, n2015_1, n2020_1, n2025_1, n2030, n2035_1, n2040, n2045_1, - n2050_1, n2054_1, n2059_1, n2064_1, n2067, n2072_1, n2077_1, n2082, - n2087_1, n2092_1, n2097_1, n2102_1, n2107_1, n2112, n2117_1, n2122_1, - n2127_1, n2132, n2137, n2142_1, n2147_1, n2152_1, n2157_1, n2162_1, - n2167_1, n2172_1, n2177, n2182_1, n2187_1, n2192_1, n2197, n2202, - n2207_1, n2212_1, n2217_1, n2222, n2227_1, n2232, n2237_1, n2242, - n2247_1, n2252, n2257_1, n2262, n2267, n2272, n2277, n2282, n2287, - n2292, n2297_1, n2302, n2307, n2312, n2317, n2322, n2327_1, n2332_1, - n2337, n2342, n2347, n2352, n2357, n2362_1, n2367_1, n2372, n2377, - n2382, n2387, n2391, n2395_1, n2399, n2404, n2409, n2414, n2419, - n2424_1, n2429_1, n2434, n2439, n2444_1, n2449, n2454, n2459, n2464, - n2469, n2474, n2479, n2484, n2489_1, n2494, n2499_1, n2504_1, n2509, - n2514_1, n2519_1, n2524_1, n2529, n2534_1, n2539, n2544, n2549, n2554, - n2559, n2564, n2569, n2574, n2579, n2584_1, n2589, n2594, n2599_1, - n2604, n2609, n2614, n2619_1, n2624, n2629, n2634, n2639, n2644, n2649, - n2654, n2659, n2664, n2669, n2674, n2679, n2684, n2689, n2694_1, - n2699_1, n2704_1, n2709, n2714_1, n2719, n2724_1, n2729_1, n2734_1, - n2739_1, n2744_1, n2749_1, n2754_1, n2759_1, n2764_1, n2769_1, n2774_1, - n2779_1, n2784_1, n2789_1, n2794_1, n2799_1, n2804_1, n2809_1, n2814_1, - n2819_1, n2824_1, n2829_1, n2834_1, n2839_1, n2844_1, n2849_1, n2854_1, - n2859_1, n2864_1, n2869_1, n2874_1, n2879_1, n2884_1, n2889, n2894, - n2899, n2904, n2909_1, n2914_1, n2919_1, n2924_1, n2929_1, n2934_1, - n2939_1, n2944_1, n2949_1, n2954_1, n2959_1, n2964_1, n2969_1, n2974_1, - n2979_1, n2984_1, n2989_1, n2994_1, n2999, n3004_1, n3009_1, n3014, - n3019_1, n3024_1, n3029_1, n3034_1, n3039_1, n3043_1, n3048_1, n3052_1, - n3057_1, n3061_1, n3066_1, n3070, n3075, n3079_1, n3084_1, n3088_1, - n3093_1, n3097_1, n3102, n3106_1, n3110_1, n3114_1, n3119_1, n3124_1, - n3129_1, n3133_1, n3137_1, n3141_1, n3145_1, n3149_1, n3153_1, n3157_1, - n3161_1, n3165_1, n3169_1, n3173_1, n3177_1, n3181_1, n3185_1, n3189_1, - n3193_1, n3197_1, n3201_1, n3205_1, n3209_1, n3213_1, n3217_1, n3221_1, - n3225_1, n3230_1, n3235_1, n3240_1, n3245_1, n3249_1, n3253_1, n3258_1, - n3262_1, n3267_1, n3271_1, n3276_1, n3280_1, n3285_1, n3289_1, n3294_1, - n3298_1, n3303_1, n3307_1, n3312_1, n3317_1, n3322_1, n3327_1, n3331_1, - n3335_1, n3339_1, n3344_1, n3349_1, n3354_1, n3359_1, n3364_1, n3369_1, - n3373_1, n3377_1, n3381_1, n3385_1, n3389_1, n3394_1, n3398_1, n3403_1, - n3408_1, n3412_1, n3417_1, n3421_1, n3426_1, n3431_1, n3436_1, n3441_1, - n3446_1, n3451_1, n3456_1, n3461_1, n3466_1, n3471_1, n3476_1, n3481_1, - n3486_1, n3491_1, n3496_1, n3501_1, n3506_1, n3511_1, n3516_1, n3521_1, - n3526_1, n3531_1, n3536_1, n3541_1, n3546_1, n3551_1, n3556_1, n3560_1, - n3565_1, n3570_1, n3573_1, n3578_1, n3583_1, n3588_1, n3593_1, n3598_1, - n3603_1, n3608_1, n3613_1, n3618_1, n3623_1, n3628_1, n3632_1, n3636_1, - n3641_1, n3646_1, n3651_1, n3656_1, n3661_1, n3666_1, n3671_1, n3676_1, - n3681_1, n3686_1, n3691_1, n3696_1, n3701_1, n3706_1, n3711_1, n3716_1, - n3721_1, n3726_1, n3731_1, n3736_1, n3741_1, n3746_1, n3751_1, n3756_1, - n3761, n3766_1, n3771, n3776_1, n3781_1, n3786, n3791, n3796_1, n3801, - n3806, n3811_1, n3816, n3821, n3826_1, n3831_1, n3836_1, n3841_1, - n3846_1, n3851_1, n3856_1, n3861_1, n3866, n3871_1, n3876_1, n3881_1, - n3886_1, n3891, n3896, n3901, n3906, n3911, n3916_1, n3921, n3926_1, - n3931, n3936, n3941_1, n3946, n3951, n3956, n3961_1, n3966, n3971, - n3976, n3981, n3986, n3991, n3996_1, n4001_1, n4006_1, n4011_1, - n4016_1, n4021, n4026, n4031_1, n4036, n4041_1, n4046, n4051, n4056, - n4061, n4066_1, n4071_1, n4076, n4081_1, n4086_1, n4091, n4096_1, - n4101, n4106, n4111_1, n4116_1, n4121, n4126, n4131, n4136_1, n4141, - n4146, n4151, n4156, n4161, n4166, n4171, n4176, n4181_1, n4186, - n4191_1, n4196, n4201, n4206, n4211, n4216, n4221, n4226, n4231, - n4236_1, n4241_1, n4246, n4251, n4256, n4261_1, n4266, n4271, n4276, - n4281_1, n4286, n4291_1, n4296, n4301, n4306_1, n4311_1, n4316, n4321, - n4326, n4331_1, n4336_1, n4341_1, n4346, n4351, n4356, n4361, n4366, - n4371, n4376, n4381, n4386, n4391, n4396, n4401, n4406, n4411, n4416, - n4421, n4426, n4431, n4436, n4441, n4446_1, n4451_1, n4456_1, n4461, - n4466, n4471, n4476, n4481, n4486, n4491, n4496, n4501, n4506_1, n4511, - n4516, n4521, n4526, n4531, n4536, n4541, n4546, n4550, n4555, n4559, - n4564, n4568, n4573, n4577, n4582, n4586, n4591, n4595, n4600, n4604, - n4609, n4613, n4617, n4621, n4626, n4631, n4636, n4640, n4644_1, n4648, - n4652, n4656, n4660, n4664, n4668, n4672, n4676, n4680, n4684, n4688, - n4692, n4696, n4700, n4704, n4708, n4712, n4716, n4720, n4724, n4728, - n4732, n4737, n4742, n4747, n4752, n4756, n4760, n4765, n4769, n4774, - n4778, n4783, n4787, n4792, n4796, n4801, n4805, n4810, n4814, n4819, - n4824, n4829, n4834, n4838, n4842, n4846, n4851, n4856, n4861, n4866, - n4871_1, n4876, n4880, n4884, n4888, n4892, n4896_1, n4901, n4905_1, - n4910, n4915, n4919, n4924, n4928, n4933, n4938, n4943, n4948, n4953, - n4958, n4963, n4968, n4973, n4978, n4983, n4988, n4993, n4998, n5003, - n5008, n5013, n5018, n5023, n5028, n5033, n5038, n5043, n5048, n5053, - n5058, n5063, n5067, n5072, n5077, n5080, n5085, n5090, n5095, n5100, - n5105, n5110, n5115, n5120, n5125, n5130, n5135, n5140, n5145, n5150, - n5155, n5160, n5165, n5170, n5175, n5180, n5185, n5190, n5195, n5200, - n5205, n5210, n5215, n5220, n5225, n5230, n5235, n5240, n5245, n5250, - n5255, n5260, n5265, n5270, n5275, n5280, n5285, n5290, n5295, n5300, - n5305, n5310, n5315, n5320, n5325, n5330, n5335, n5340, n5345, n5350, - n5355, n5360, n5365, n5370, n5375, n5380, n5385, n5390, n5395, n5400, - n5405, n5410, n5415, n5420, n5425, n5430, n5435, n5440, n5445, n5450, - n5455, n5460, n5465, n5470, n5475, n5480, n5485, n5490, n5495, n5500, - n5505, n5510, n5515, n5520, n5525, n5530, n5535, n5540, n5545, n5550, - n5555, n5560, n5565, n5570, n5575, n5580, n5585, n5590, n5595, n5600, - n5605, n5610, n5615, n5620, n5625, n5630, n5635, n5640, n5645, n5650, - n5655, n5660, n5665, n5670, n5675, n5680, n5685, n5690, n5695, n5700, - n5705, n5710, n5715, n5720, n5725, n5730, n5735, n5740, n5745, n5750, - n5755, n5760, n5765, n5770, n5775, n5780, n5785, n5790, n5795, n5800, - n5805, n5810, n5815, n5819, n5823, n5828, n5833, n5838, n5843, n5848, - n5853, n5858, n5863, n5868, n5873, n5878, n5883, n5888, n5893, n5898, - n5903, n5908, n5913, n5918, n5923, n5928, n5933, n5938, n5943, n5948, - n5953, n5958, n5963, n5968, n5973, n5978, n5983, n5988, n5993, n5998, - n6003, n6008, n6013, n6018, n6023, n6028, n6033, n6038, n6043, n6048, - n6053, n6057, n6062, n6066, n6071, n6075, n6080, n6084, n6089, n6093, - n6098, n6102, n6107, n6111, n6116, n6120, n6124, n6128, n6133, n6138, - n6143, n6147, n6151, n6155, n6159, n6163, n6167, n6171, n6175, n6179, - n6183, n6187, n6191, n6195, n6199, n6203, n6207, n6211, n6215, n6219, - n6223, n6227, n6231, n6235, n6239, n6244, n6249, n6254, n6259, n6263, - n6267, n6272, n6276, n6281, n6285, n6290, n6294, n6299, n6303, n6308, - n6312, n6317, n6321, n6326, n6331, n6336, n6341, n6345, n6349, n6353, - n6358, n6363, n6368, n6373, n6378, n6383, n6387, n6391, n6395, n6399, - n6403, n6408, n6412, n6417, n6422, n6426, n6431, n6435, n6440, n6445, - n6450, n6455, n6460, n6465, n6470, n6475, n6480, n6485, n6490, n6495, - n6500, n6505, n6510, n6515, n6520, n6525, n6530, n6535, n6540, n6545, - n6550, n6555, n6560, n6565, n6570, n6574, n6579, n6584, n6587, n6592, - n6597, n6602, n6607, n6612, n6617, n6622, n6627, n6632, n6637, n6642, - n6647, n6652, n6657, n6662, n6667, n6672, n6677, n6682, n6687, n6692, - n6697, n6702, n6707, n6712, n6717, n6722, n6727, n6732, n6737, n6742, - n6747, n6752, n6757, n6762, n6767, n6772, n6777, n6782, n6787, n6792, - n6797, n6802, n6807, n6812, n6817, n6822, n6827, n6832, n6837, n6842, - n6847, n6852, n6857, n6862, n6867, n6872, n6877, n6882, n6887, n6892, - n6897, n6902, n6907, n6912, n6917, n6922, n6926, n6931, n6936, n6941, - n6946, n6951, n6956, n6961, n6966, n6971, n6976, n6981, n6986, n6991, - n6996, n7001, n7006, n7011, n7016, n7021, n7026, n7031, n7036, n7041, - n7046, n7051, n7056, n7061, n7066, n7071, n7076, n7081, n7086, n7091, - n7096, n7101, n7106, n7111, n7116, n7121, n7126, n7131, n7136, n7141, - n7146, n7151, n7156, n7160, n7163, n7167, n7172, n7176, n7180, n7184, - n7188, n7192, n7196, n7200, n7204, n7209, n7213, n7218, n7222, n7226, - n7230, n7234, n7238, n7242, n7246, n7250, n7255, n7260; - assign Pg27380 = ~n893_1; - assign Pg26149 = ~n6140; - assign Pg26135 = ~n853_1; - assign Pg26104 = ~n6148; - assign Pg25489 = ~n7621; - assign n858_1 = ~Pg3233 | Pg3230; - assign Pg25435 = ~n863_1; - assign Pg24734 = ~n868_1; - assign Pg16496 = ~n4652_1; - assign n4530 = ~Pg8269 ^ ~Pg8268; - assign n4531_1 = ~Pg8271 ^ ~Pg8270; - assign n4532 = ~n4530 ^ ~n4531_1; - assign n4533 = ~Pg8262 ^ ~Pg8264; - assign n4534 = ~Pg8265 ^ ~Pg8266; - assign n4535 = ~n4533 ^ ~n4534; - assign n4536_1 = ~Pg8259 ^ ~Pg8261; - assign n4537 = ~Pg8260 ^ ~Pg8263; - assign n4538 = ~n4536_1 ^ ~n4537; - assign n4539 = ~Pg8272 ^ ~Pg8273; - assign n4540 = ~Pg8275 ^ ~Pg8274; - assign n4541_1 = ~n4539 ^ ~n4540; - assign n4542 = (~Ng1315 | ~Ng324) & (~\[1605] | ~Ng394); - assign n4543 = n4542 & (~\[1603] | ~Ng396); - assign n4544 = (~Ng1315 | ~Ng383) & (~\[1605] | ~Ng379); - assign n4545 = n4544 & (~\[1603] | ~Ng381); - assign n4546_1 = (~Ng1315 | ~Ng1011) & (~\[1605] | ~Ng1081); - assign n4547 = n4546_1 & (~\[1603] | ~Ng1083); - assign n4548 = (~Ng1315 | ~Ng368) & (~\[1605] | ~Ng364); - assign n4549 = n4548 & (~\[1603] | ~Ng366); - assign n4550_1 = (~Ng1315 | ~Ng1070) & (~\[1605] | ~Ng1066); - assign n4551 = n4550_1 & (~\[1603] | ~Ng1068); - assign n4552 = (~Ng1315 | ~Ng1705) & (~\[1605] | ~Ng1775); - assign n4553 = n4552 & (~\[1603] | ~Ng1777); - assign n4554 = (~Ng1315 | ~Ng353) & (~\[1605] | ~Ng349); - assign n4555_1 = n4554 & (~\[1603] | ~Ng351); - assign n4556 = (~Ng1315 | ~Ng1055) & (~\[1605] | ~Ng1051); - assign n4557 = n4556 & (~\[1603] | ~Ng1053); - assign n4558 = (~Ng1315 | ~Ng1764) & (~\[1605] | ~Ng1760); - assign n4559_1 = n4558 & (~\[1603] | ~Ng1762); - assign n4560 = (~Ng1315 | ~Ng2399) & (~\[1605] | ~Ng2469); - assign n4561 = n4560 & (~\[1603] | ~Ng2471); - assign n4562 = (~Ng1315 | ~Ng1040) & (~\[1605] | ~Ng1036); - assign n4563 = n4562 & (~\[1603] | ~Ng1038); - assign n4564_1 = (~Ng1315 | ~Ng1749) & (~\[1605] | ~Ng1745); - assign n4565 = n4564_1 & (~\[1603] | ~Ng1747); - assign n4566 = (~Ng1315 | ~Ng2458) & (~\[1605] | ~Ng2454); - assign n4567 = n4566 & (~\[1603] | ~Ng2456); - assign n4568_1 = (~Ng1315 | ~Ng1734) & (~\[1605] | ~Ng1730); - assign n4569 = n4568_1 & (~\[1603] | ~Ng1732); - assign n4570 = (~Ng1315 | ~Ng2443) & (~\[1605] | ~Ng2439); - assign n4571 = n4570 & (~\[1603] | ~Ng2441); - assign n4572 = (~Ng1315 | ~Ng2428) & (~\[1605] | ~Ng2424); - assign n4573_1 = n4572 & (~\[1603] | ~Ng2426); - assign n4574 = (~Ng1315 | ~Ng496) & (~\[1605] | ~Ng490); - assign n4575 = n4574 & (~\[1603] | ~Ng493); - assign n4576 = (~Ng1315 | ~Ng1183) & (~\[1605] | ~Ng1177); - assign n4577_1 = n4576 & (~\[1603] | ~Ng1180); - assign n4578 = (~Ng1315 | ~Ng1877) & (~\[1605] | ~Ng1871); - assign n4579 = n4578 & (~\[1603] | ~Ng1874); - assign n4580 = (~Ng1315 | ~Ng2571) & (~\[1605] | ~Ng2565); - assign n4581 = n4580 & (~\[1603] | ~Ng2568); - assign n4582_1 = (~Ng853 | Ng447) & (~\[1612] | Ng448); - assign n4583 = n4582_1 & (~\[1594] | Ng449); - assign n4584 = (~Ng853 | Ng402) & (~\[1612] | Ng403); - assign n4585 = n4584 & (~\[1594] | Ng404); - assign n4586_1 = (~\[1605] | Ng479) & (~\[1603] | Ng477); - assign n1888 = n4586_1 & (~Ng1315 | Ng478); - assign n4588 = (~\[1605] | Ng464) & (~\[1603] | Ng480); - assign n1902_1 = n4588 & (~Ng1315 | Ng484); - assign n4590 = (~Ng853 | Ng1134) & (~\[1612] | Ng1135); - assign n4591_1 = n4590 & (~\[1594] | Ng1136); - assign n4592 = (~Ng853 | Ng1089) & (~\[1612] | Ng1090); - assign n4593 = n4592 & (~\[1594] | Ng1091); - assign n4594 = (~\[1605] | Ng1166) & (~\[1603] | Ng1164); - assign n3394_1 = n4594 & (~Ng1315 | Ng1165); - assign n4596 = (~\[1605] | Ng488) & (~\[1603] | Ng486); - assign n1911_1 = n4596 & (~Ng1315 | Ng487); - assign n4598 = (~\[1605] | Ng1151) & (~\[1603] | Ng1167); - assign n3408_1 = n4598 & (~Ng1315 | Ng1171); - assign n4600_1 = (~Ng853 | Ng1828) & (~\[1612] | Ng1829); - assign n4601 = n4600_1 & (~\[1594] | Ng1830); - assign n4602 = (~Ng853 | Ng1783) & (~\[1612] | Ng1784); - assign n4603 = n4602 & (~\[1594] | Ng1785); - assign n4604_1 = (~\[1605] | Ng1860) & (~\[1603] | Ng1858); - assign n4901 = n4604_1 & (~Ng1315 | Ng1859); - assign n4606 = (~Ng1315 | ~Ng573) & (~\[1605] | ~Ng569); - assign n1739_1 = n4606 & (~\[1603] | ~Ng571); - assign n4608 = (~\[1605] | Ng1175) & (~\[1603] | Ng1173); - assign n3417_1 = n4608 & (~Ng1315 | Ng1174); - assign n4610 = (~\[1605] | Ng1845) & (~\[1603] | Ng1861); - assign n4915 = n4610 & (~Ng1315 | Ng1865); - assign n4612 = (~Ng853 | Ng2522) & (~\[1612] | Ng2523); - assign n4613_1 = n4612 & (~\[1594] | Ng2524); - assign n4614 = (~Ng853 | Ng2477) & (~\[1612] | Ng2478); - assign n4615 = n4614 & (~\[1594] | Ng2479); - assign n4616 = (~\[1605] | Ng2554) & (~\[1603] | Ng2552); - assign n6408 = n4616 & (~Ng1315 | Ng2553); - assign n4618 = (~Ng1315 | ~Ng1259) & (~\[1605] | ~Ng1255); - assign n3245_1 = n4618 & (~\[1603] | ~Ng1257); - assign n4620 = (~\[1605] | Ng1869) & (~\[1603] | Ng1867); - assign n4924 = n4620 & (~Ng1315 | Ng1868); - assign n4622 = (~\[1605] | Ng2539) & (~\[1603] | Ng2555); - assign n6422 = n4622 & (~Ng1315 | Ng2559); - assign n4624 = (~Ng853 | Ng321) & (~\[1612] | Ng322); - assign n4625 = n4624 & (~\[1594] | Ng323); - assign n4626_1 = (~Ng1315 | ~Ng1953) & (~\[1605] | ~Ng1949); - assign n4752 = n4626_1 & (~\[1603] | ~Ng1951); - assign n4628 = (~\[1605] | Ng2563) & (~\[1603] | Ng2561); - assign n6431 = n4628 & (~Ng1315 | Ng2562); - assign n4630 = (~Ng1315 | ~Ng489) & (~\[1605] | ~Ng565); - assign n1875_1 = n4630 & (~\[1603] | ~Ng567); - assign n4632 = (~Ng853 | Ng1008) & (~\[1612] | Ng1009); - assign n4633 = n4632 & (~\[1594] | Ng1010); - assign n4634 = (~Ng1315 | ~Ng2647) & (~\[1605] | ~Ng2643); - assign n6259 = n4634 & (~\[1603] | ~Ng2645); - assign n4636_1 = (~Ng1315 | ~Ng1176) & (~\[1605] | ~Ng1251); - assign n3381_1 = n4636_1 & (~\[1603] | ~Ng1253); - assign n4638 = (~Ng853 | Ng1702) & (~\[1612] | Ng1703); - assign n4639 = n4638 & (~\[1594] | Ng1704); - assign n4640_1 = (~Ng1315 | ~Ng1870) & (~\[1605] | ~Ng1945); - assign n4888 = n4640_1 & (~\[1603] | ~Ng1947); - assign n4642 = (~Ng853 | Ng2396) & (~\[1612] | Ng2397); - assign n4643 = n4642 & (~\[1594] | Ng2398); - assign n4644 = (~Ng1315 | ~Ng2564) & (~\[1605] | ~Ng2639); - assign n6395 = n4644 & (~\[1603] | ~Ng2641); - assign n4646 = (~Ng853 | Ng141) & (~\[1594] | Ng143); - assign n4647 = n4646 & (~\[1612] | Ng142); - assign n4648_1 = (~Ng853 | Ng144) & (~\[1594] | Ng146); - assign n4649 = n4648_1 & (~\[1612] | Ng145); - assign n4650 = (~Ng853 | Ng829) & (~\[1594] | Ng831); - assign n4651 = n4650 & (~\[1612] | Ng830); - assign n4652_1 = Ng2987 & (~Pg5388 | Ng2986); - assign n4653 = (~Ng853 | Ng147) & (~\[1594] | Ng149); - assign n4654 = n4653 & (~\[1612] | Ng148); - assign n4655 = (~Ng853 | Ng832) & (~\[1594] | Ng834); - assign n4656_1 = n4655 & (~\[1612] | Ng833); - assign n4657 = (~Ng853 | Ng1523) & (~\[1594] | Ng1525); - assign n4658 = n4657 & (~\[1612] | Ng1524); - assign n4659 = (~Ng853 | Ng150) & (~\[1594] | Ng152); - assign n4660_1 = n4659 & (~\[1612] | Ng151); - assign n4661 = (~\[1594] | ~Ng216) & (~Ng853 | ~Ng219); - assign n4662 = n4661 & (~\[1612] | ~Ng213); - assign n4663 = (~Ng853 | Ng835) & (~\[1594] | Ng837); - assign n4664_1 = n4663 & (~\[1612] | Ng836); - assign n4665 = (~Ng853 | Ng1526) & (~\[1594] | Ng1528); - assign n4666 = n4665 & (~\[1612] | Ng1527); - assign n4667 = (~Ng853 | Ng2217) & (~\[1594] | Ng2219); - assign n4668_1 = n4667 & (~\[1612] | Ng2218); - assign n4669 = (~Ng853 | Ng153) & (~\[1612] | Ng154); - assign n4670 = n4669 & (~\[1594] | Ng155); - assign n4671 = (~\[1612] | ~Ng222) & (~\[1594] | ~Ng225); - assign n4672_1 = n4671 & (~Ng853 | ~Ng228); - assign n4673 = (~Ng853 | Ng838) & (~\[1612] | Ng839); - assign n4674 = n4673 & (~\[1594] | Ng840); - assign n4675 = (~\[1612] | ~Ng900) & (~\[1594] | ~Ng903); - assign n4676_1 = n4675 & (~Ng853 | ~Ng906); - assign n4677 = (~Ng853 | Ng1529) & (~\[1612] | Ng1530); - assign n4678 = n4677 & (~\[1594] | Ng1531); - assign n4679 = (~Ng853 | Ng2220) & (~\[1612] | Ng2221); - assign n4680_1 = n4679 & (~\[1594] | Ng2222); - assign n4681 = (~Ng853 | Ng156) & (~\[1612] | Ng157); - assign n4682 = n4681 & (~\[1594] | Ng158); - assign n4683 = (~Ng853 | ~Ng237) & (~\[1612] | ~Ng231); - assign n4684_1 = n4683 & (~\[1594] | ~Ng234); - assign n4685 = (~Ng1315 | Ng698) & (~\[1605] | Ng699); - assign n4686 = n4685 & (~\[1603] | Ng700); - assign n4687 = (~Ng1315 | Ng725) & (~\[1605] | Ng726); - assign n4688_1 = n4687 & (~\[1603] | Ng727); - assign n4689 = (~Ng853 | Ng841) & (~\[1612] | Ng842); - assign n4690 = n4689 & (~\[1594] | Ng843); - assign n4691 = (~Ng853 | ~Ng915) & (~\[1612] | ~Ng909); - assign n4692_1 = n4691 & (~\[1594] | ~Ng912); - assign n4693 = (~Ng853 | Ng1532) & (~\[1612] | Ng1533); - assign n4694 = n4693 & (~\[1594] | Ng1534); - assign n4695 = (~Ng853 | ~Ng1600) & (~\[1612] | ~Ng1594); - assign n4696_1 = n4695 & (~\[1594] | ~Ng1597); - assign n4697 = (~Ng853 | Ng2223) & (~\[1612] | Ng2224); - assign n4698 = n4697 & (~\[1594] | Ng2225); - assign n4699 = (~Ng853 | Ng159) & (~\[1612] | Ng160); - assign n4700_1 = n4699 & (~\[1594] | Ng161); - assign n4701 = (~Ng853 | ~Ng246) & (~\[1612] | ~Ng240); - assign n4702 = n4701 & (~\[1594] | ~Ng243); - assign n4703 = (~Ng1315 | Ng701) & (~\[1605] | Ng702); - assign n4704_1 = n4703 & (~\[1603] | Ng703); - assign n4705 = (~Ng853 | Ng844) & (~\[1612] | Ng845); - assign n4706 = n4705 & (~\[1594] | Ng846); - assign n4707 = (~Ng853 | ~Ng924) & (~\[1612] | ~Ng918); - assign n4708_1 = n4707 & (~\[1594] | ~Ng921); - assign n4709 = (~Ng1315 | Ng1384) & (~\[1605] | Ng1385); - assign n4710 = n4709 & (~\[1603] | Ng1386); - assign n4711 = (~Ng1315 | Ng1411) & (~\[1605] | Ng1412); - assign n4712_1 = n4711 & (~\[1603] | Ng1413); - assign n4713 = (~Ng853 | Ng1535) & (~\[1612] | Ng1536); - assign n4714 = n4713 & (~\[1594] | Ng1537); - assign n4715 = (~Ng853 | ~Ng1609) & (~\[1612] | ~Ng1603); - assign n4716_1 = n4715 & (~\[1594] | ~Ng1606); - assign n4717 = (~Ng853 | Ng2226) & (~\[1612] | Ng2227); - assign n4718 = n4717 & (~\[1594] | Ng2228); - assign n4719 = (~Ng853 | ~Ng2294) & (~\[1612] | ~Ng2288); - assign n4720_1 = n4719 & (~\[1594] | ~Ng2291); - assign n4721 = (~Ng853 | Ng129) & (~\[1612] | Ng130); - assign n4722 = n4721 & (~\[1594] | Ng131); - assign n4723 = (~Ng853 | Ng162) & (~\[1612] | Ng163); - assign n4724_1 = n4723 & (~\[1594] | Ng164); - assign n4725 = (~Ng853 | ~Ng255) & (~\[1612] | ~Ng249); - assign n4726 = n4725 & (~\[1594] | ~Ng252); - assign n4727 = (~Ng1315 | Ng704) & (~\[1605] | Ng705); - assign n4728_1 = n4727 & (~\[1603] | Ng706); - assign n4729 = (~Ng853 | Ng847) & (~\[1612] | Ng848); - assign n4730 = n4729 & (~\[1594] | Ng849); - assign n4731 = (~Ng853 | ~Ng933) & (~\[1612] | ~Ng927); - assign n4732_1 = n4731 & (~\[1594] | ~Ng930); - assign n4733 = (~Ng1315 | Ng1387) & (~\[1605] | Ng1388); - assign n4734 = n4733 & (~\[1603] | Ng1389); - assign n4735 = (~Ng853 | Ng1538) & (~\[1612] | Ng1539); - assign n4736 = n4735 & (~\[1594] | Ng1540); - assign n4737_1 = (~Ng853 | ~Ng1618) & (~\[1612] | ~Ng1612); - assign n4738 = n4737_1 & (~\[1594] | ~Ng1615); - assign n4739 = (~Ng1315 | Ng2078) & (~\[1605] | Ng2079); - assign n4740 = n4739 & (~\[1603] | Ng2080); - assign n4741 = (~Ng1315 | Ng2105) & (~\[1605] | Ng2106); - assign n4742_1 = n4741 & (~\[1603] | Ng2107); - assign n4743 = (~Ng853 | Ng2229) & (~\[1612] | Ng2230); - assign n4744 = n4743 & (~\[1594] | Ng2231); - assign n4745 = (~Ng853 | ~Ng2303) & (~\[1612] | ~Ng2297); - assign n4746 = n4745 & (~\[1594] | ~Ng2300); - assign n4747_1 = (~Ng853 | Ng132) & (~\[1612] | Ng133); - assign n4748 = n4747_1 & (~\[1594] | Ng134); - assign n4749 = (~Ng853 | ~Ng264) & (~\[1612] | ~Ng258); - assign n4750 = n4749 & (~\[1594] | ~Ng261); - assign n4751 = (~Ng853 | Ng11499) & (~\[1612] | Ng11497); - assign n4752_1 = n4751 & (~\[1594] | Ng11498); - assign n4753 = (~Ng853 | ~Ng435) & (~\[1612] | ~Ng429); - assign n4754 = n4753 & (~\[1594] | ~Ng432); - assign n4755 = (~Ng1315 | Ng707) & (~\[1605] | Ng708); - assign n4756_1 = n4755 & (~\[1603] | Ng709); - assign n4757 = (~Ng853 | Ng817) & (~\[1612] | Ng818); - assign n4758 = n4757 & (~\[1594] | Ng819); - assign n4759 = (~Ng853 | Ng850) & (~\[1612] | Ng851); - assign n4760_1 = n4759 & (~\[1594] | Ng852); - assign n4761 = (~Ng853 | ~Ng942) & (~\[1612] | ~Ng936); - assign n4762 = n4761 & (~\[1594] | ~Ng939); - assign n4763 = (~Ng1315 | Ng1390) & (~\[1605] | Ng1391); - assign n4764 = n4763 & (~\[1603] | Ng1392); - assign n4765_1 = (~Ng853 | Ng1541) & (~\[1612] | Ng1542); - assign n4766 = n4765_1 & (~\[1594] | Ng1543); - assign n4767 = (~Ng853 | ~Ng1627) & (~\[1612] | ~Ng1621); - assign n4768 = n4767 & (~\[1594] | ~Ng1624); - assign n4769_1 = (~Ng1315 | Ng2081) & (~\[1605] | Ng2082); - assign n4770 = n4769_1 & (~\[1603] | Ng2083); - assign n4771 = (~Ng853 | Ng2232) & (~\[1612] | Ng2233); - assign n4772 = n4771 & (~\[1594] | Ng2234); - assign n4773 = (~Ng853 | ~Ng2312) & (~\[1612] | ~Ng2306); - assign n4774_1 = n4773 & (~\[1594] | ~Ng2309); - assign n4775 = (~Ng1315 | Ng2772) & (~\[1605] | Ng2773); - assign n4776 = n4775 & (~\[1603] | Ng2774); - assign n4777 = (~Ng1315 | Ng2799) & (~\[1605] | Ng2800); - assign n4778_1 = n4777 & (~\[1603] | Ng2801); - assign n4779 = (~Ng853 | ~Ng192) & (~\[1612] | ~Ng186); - assign n4780 = n4779 & (~\[1594] | ~Ng189); - assign n4781 = (~Ng853 | ~Ng273) & (~\[1612] | ~Ng267); - assign n4782 = n4781 & (~\[1594] | ~Ng270); - assign n4783_1 = (~Ng853 | Ng11502) & (~\[1612] | Ng11500); - assign n4784 = n4783_1 & (~\[1594] | Ng11501); - assign n4785 = (~Ng853 | ~Ng444) & (~\[1612] | ~Ng438); - assign n4786 = n4785 & (~\[1594] | ~Ng441); - assign n4787_1 = (~Ng1315 | Ng710) & (~\[1605] | Ng711); - assign n4788 = n4787_1 & (~\[1603] | Ng712); - assign n4789 = (~Ng853 | Ng820) & (~\[1612] | Ng821); - assign n4790 = n4789 & (~\[1594] | Ng822); - assign n4791 = (~Ng853 | ~Ng951) & (~\[1612] | ~Ng945); - assign n4792_1 = n4791 & (~\[1594] | ~Ng948); - assign n4793 = (~Ng853 | Ng11526) & (~\[1612] | Ng11524); - assign n4794 = n4793 & (~\[1594] | Ng11525); - assign n4795 = (~Ng853 | ~Ng1122) & (~\[1612] | ~Ng1116); - assign n4796_1 = n4795 & (~\[1594] | ~Ng1119); - assign n4797 = (~Ng1315 | Ng1393) & (~\[1605] | Ng1394); - assign n4798 = n4797 & (~\[1603] | Ng1395); - assign n4799 = (~Ng853 | Ng1511) & (~\[1612] | Ng1512); - assign n4800 = n4799 & (~\[1594] | Ng1513); - assign n4801_1 = (~Ng853 | Ng1544) & (~\[1612] | Ng1545); - assign n4802 = n4801_1 & (~\[1594] | Ng1546); - assign n4803 = (~Ng853 | ~Ng1636) & (~\[1612] | ~Ng1630); - assign n4804 = n4803 & (~\[1594] | ~Ng1633); - assign n4805_1 = (~Ng1315 | Ng2084) & (~\[1605] | Ng2085); - assign n4806 = n4805_1 & (~\[1603] | Ng2086); - assign n4807 = (~Ng853 | Ng2235) & (~\[1612] | Ng2236); - assign n4808 = n4807 & (~\[1594] | Ng2237); - assign n4809 = (~Ng853 | ~Ng2321) & (~\[1612] | ~Ng2315); - assign n4810_1 = n4809 & (~\[1594] | ~Ng2318); - assign n4811 = (~Ng1315 | Ng2775) & (~\[1605] | Ng2776); - assign n4812 = n4811 & (~\[1603] | Ng2777); - assign n4813 = (~Ng853 | ~Ng201) & (~\[1612] | ~Ng195); - assign n4814_1 = n4813 & (~\[1594] | ~Ng198); - assign n4815 = (~Ng853 | Ng11505) & (~\[1612] | Ng11503); - assign n4816 = n4815 & (~\[1594] | Ng11504); - assign n4817 = (~Ng1315 | Ng713) & (~\[1605] | Ng714); - assign n4818 = n4817 & (~\[1603] | Ng715); - assign n4819_1 = (~Ng1315 | Ng731) & (~\[1605] | Ng732); - assign n4820 = n4819_1 & (~\[1603] | Ng733); - assign n4821 = (~Ng853 | ~Ng879) & (~\[1612] | ~Ng873); - assign n4822 = n4821 & (~\[1594] | ~Ng876); - assign n4823 = (~Ng853 | ~Ng960) & (~\[1612] | ~Ng954); - assign n4824_1 = n4823 & (~\[1594] | ~Ng957); - assign n4825 = (~Ng853 | Ng11529) & (~\[1612] | Ng11527); - assign n4826 = n4825 & (~\[1594] | Ng11528); - assign n4827 = (~Ng853 | ~Ng1131) & (~\[1612] | ~Ng1125); - assign n4828 = n4827 & (~\[1594] | ~Ng1128); - assign n4829_1 = (~Ng1315 | Ng1396) & (~\[1605] | Ng1397); - assign n4830 = n4829_1 & (~\[1603] | Ng1398); - assign n4831 = (~Ng853 | Ng1514) & (~\[1612] | Ng1515); - assign n4832 = n4831 & (~\[1594] | Ng1516); - assign n4833 = (~Ng853 | ~Ng1645) & (~\[1612] | ~Ng1639); - assign n4834_1 = n4833 & (~\[1594] | ~Ng1642); - assign n4835 = (~Ng853 | Ng11553) & (~\[1612] | Ng11551); - assign n4836 = n4835 & (~\[1594] | Ng11552); - assign n4837 = (~Ng853 | ~Ng1816) & (~\[1612] | ~Ng1810); - assign n4838_1 = n4837 & (~\[1594] | ~Ng1813); - assign n4839 = (~Ng1315 | Ng2087) & (~\[1605] | Ng2088); - assign n4840 = n4839 & (~\[1603] | Ng2089); - assign n4841 = (~Ng853 | Ng2205) & (~\[1612] | Ng2206); - assign n4842_1 = n4841 & (~\[1594] | Ng2207); - assign n4843 = (~Ng853 | Ng2238) & (~\[1612] | Ng2239); - assign n4844 = n4843 & (~\[1594] | Ng2240); - assign n4845 = (~Ng853 | ~Ng2330) & (~\[1612] | ~Ng2324); - assign n4846_1 = n4845 & (~\[1594] | ~Ng2327); - assign n4847 = (~Ng1315 | Ng2778) & (~\[1605] | Ng2779); - assign n4848 = n4847 & (~\[1603] | Ng2780); - assign n4849 = (~Ng853 | ~Ng210) & (~\[1612] | ~Ng204); - assign n4850 = n4849 & (~\[1594] | ~Ng207); - assign n4851_1 = (~Ng853 | Ng11508) & (~\[1612] | Ng11506); - assign n4852 = n4851_1 & (~\[1594] | Ng11507); - assign n4853 = (~Ng1315 | Ng716) & (~\[1605] | Ng717); - assign n4854 = n4853 & (~\[1603] | Ng718); - assign n4855 = (~Ng853 | ~Ng888) & (~\[1612] | ~Ng882); - assign n4856_1 = n4855 & (~\[1594] | ~Ng885); - assign n4857 = (~Ng853 | Ng11532) & (~\[1612] | Ng11530); - assign n4858 = n4857 & (~\[1594] | Ng11531); - assign n4859 = (~Ng1315 | Ng1399) & (~\[1605] | Ng1400); - assign n4860 = n4859 & (~\[1603] | Ng1401); - assign n4861_1 = (~Ng1315 | Ng1417) & (~\[1605] | Ng1418); - assign n4862 = n4861_1 & (~\[1603] | Ng1419); - assign n4863 = (~Ng853 | ~Ng1573) & (~\[1612] | ~Ng1567); - assign n4864 = n4863 & (~\[1594] | ~Ng1570); - assign n4865 = (~Ng853 | ~Ng1654) & (~\[1612] | ~Ng1648); - assign n4866_1 = n4865 & (~\[1594] | ~Ng1651); - assign n4867 = (~Ng853 | Ng11556) & (~\[1612] | Ng11554); - assign n4868 = n4867 & (~\[1594] | Ng11555); - assign n4869 = (~Ng853 | ~Ng1825) & (~\[1612] | ~Ng1819); - assign n4870 = n4869 & (~\[1594] | ~Ng1822); - assign n4871 = (~Ng1315 | Ng2090) & (~\[1605] | Ng2091); - assign n4872 = n4871 & (~\[1603] | Ng2092); - assign n4873 = (~Ng853 | Ng2208) & (~\[1612] | Ng2209); - assign n4874 = n4873 & (~\[1594] | Ng2210); - assign n4875 = (~Ng853 | ~Ng2339) & (~\[1612] | ~Ng2333); - assign n4876_1 = n4875 & (~\[1594] | ~Ng2336); - assign n4877 = (~Ng853 | Ng11580) & (~\[1612] | Ng11578); - assign n4878 = n4877 & (~\[1594] | Ng11579); - assign n4879 = (~Ng853 | ~Ng2510) & (~\[1612] | ~Ng2504); - assign n4880_1 = n4879 & (~\[1594] | ~Ng2507); - assign n4881 = (~Ng1315 | Ng2781) & (~\[1605] | Ng2782); - assign n4882 = n4881 & (~\[1603] | Ng2783); - assign n4883 = (~Ng853 | Ng168) & (~\[1594] | Ng170); - assign n4884_1 = n4883 & (~\[1612] | Ng169); - assign n4885 = (~Ng1315 | Ng719) & (~\[1605] | Ng720); - assign n4886 = n4885 & (~\[1603] | Ng721); - assign n4887 = (~Ng853 | ~Ng897) & (~\[1612] | ~Ng891); - assign n4888_1 = n4887 & (~\[1594] | ~Ng894); - assign n4889 = (~Ng853 | Ng11535) & (~\[1612] | Ng11533); - assign n4890 = n4889 & (~\[1594] | Ng11534); - assign n4891 = (~Ng1315 | Ng1402) & (~\[1605] | Ng1403); - assign n4892_1 = n4891 & (~\[1603] | Ng1404); - assign n4893 = (~Ng853 | ~Ng1582) & (~\[1612] | ~Ng1576); - assign n4894 = n4893 & (~\[1594] | ~Ng1579); - assign n4895 = (~Ng853 | Ng11559) & (~\[1612] | Ng11557); - assign n4896 = n4895 & (~\[1594] | Ng11558); - assign n4897 = (~Ng1315 | Ng2093) & (~\[1605] | Ng2094); - assign n4898 = n4897 & (~\[1603] | Ng2095); - assign n4899 = (~Ng1315 | Ng2111) & (~\[1605] | Ng2112); - assign n4900 = n4899 & (~\[1603] | Ng2113); - assign n4901_1 = (~Ng853 | ~Ng2267) & (~\[1612] | ~Ng2261); - assign n4902 = n4901_1 & (~\[1594] | ~Ng2264); - assign n4903 = (~Ng853 | ~Ng2348) & (~\[1612] | ~Ng2342); - assign n4904 = n4903 & (~\[1594] | ~Ng2345); - assign n4905 = (~Ng853 | Ng11583) & (~\[1612] | Ng11581); - assign n4906 = n4905 & (~\[1594] | Ng11582); - assign n4907 = (~Ng853 | ~Ng2519) & (~\[1612] | ~Ng2513); - assign n4908 = n4907 & (~\[1594] | ~Ng2516); - assign n4909 = (~Ng1315 | Ng2784) & (~\[1605] | Ng2785); - assign n4910_1 = n4909 & (~\[1603] | Ng2786); - assign n4911 = (~Ng1315 | Ng722) & (~\[1605] | Ng723); - assign n4912 = n4911 & (~\[1603] | Ng724); - assign n4913 = (~Ng853 | Ng856) & (~\[1594] | Ng858); - assign n4914 = n4913 & (~\[1612] | Ng857); - assign n4915_1 = (~Ng1315 | Ng1405) & (~\[1605] | Ng1406); - assign n4916 = n4915_1 & (~\[1603] | Ng1407); - assign n4917 = (~Ng853 | ~Ng1591) & (~\[1612] | ~Ng1585); - assign n4918 = n4917 & (~\[1594] | ~Ng1588); - assign n4919_1 = (~Ng853 | Ng11562) & (~\[1612] | Ng11560); - assign n4920 = n4919_1 & (~\[1594] | Ng11561); - assign n4921 = (~Ng1315 | Ng2096) & (~\[1605] | Ng2097); - assign n4922 = n4921 & (~\[1603] | Ng2098); - assign n4923 = (~Ng853 | ~Ng2276) & (~\[1612] | ~Ng2270); - assign n4924_1 = n4923 & (~\[1594] | ~Ng2273); - assign n4925 = (~Ng853 | Ng11586) & (~\[1612] | Ng11584); - assign n4926 = n4925 & (~\[1594] | Ng11585); - assign n4927 = (~Ng1315 | Ng2787) & (~\[1605] | Ng2788); - assign n4928_1 = n4927 & (~\[1603] | Ng2789); - assign n4929 = (~Ng1315 | Ng2805) & (~\[1605] | Ng2806); - assign n4930 = n4929 & (~\[1603] | Ng2807); - assign n4931 = (~Ng1315 | Ng1408) & (~\[1605] | Ng1409); - assign n4932 = n4931 & (~\[1603] | Ng1410); - assign n4933_1 = (~Ng853 | Ng1550) & (~\[1612] | Ng1551); - assign n4934 = n4933_1 & (~\[1594] | Ng1552); - assign n4935 = (~Ng1315 | Ng2099) & (~\[1605] | Ng2100); - assign n4936 = n4935 & (~\[1603] | Ng2101); - assign n4937 = (~Ng853 | ~Ng2285) & (~\[1612] | ~Ng2279); - assign n4938_1 = n4937 & (~\[1594] | ~Ng2282); - assign n4939 = (~Ng853 | Ng11589) & (~\[1612] | Ng11587); - assign n4940 = n4939 & (~\[1594] | Ng11588); - assign n4941 = (~Ng1315 | Ng2790) & (~\[1605] | Ng2791); - assign n4942 = n4941 & (~\[1603] | Ng2792); - assign n4943_1 = (~Ng1315 | Ng2102) & (~\[1605] | Ng2103); - assign n4944 = n4943_1 & (~\[1603] | Ng2104); - assign n4945 = (~Ng853 | Ng2244) & (~\[1612] | Ng2245); - assign n4946 = n4945 & (~\[1594] | Ng2246); - assign n4947 = (~Ng1315 | Ng2793) & (~\[1605] | Ng2794); - assign n4948_1 = n4947 & (~\[1603] | Ng2795); - assign n4949 = (~Ng853 | Ng314) & (~\[1612] | Ng312); - assign n4950 = n4949 & (~\[1594] | Ng313); - assign n4951 = (~Ng1315 | Ng2796) & (~\[1605] | Ng2797); - assign n4952 = n4951 & (~\[1603] | Ng2798); - assign n4953_1 = (~Ng853 | Ng317) & (~\[1612] | Ng315); - assign n4954 = n4953_1 & (~\[1594] | Ng316); - assign n4955 = (~Ng853 | Ng1001) & (~\[1612] | Ng999); - assign n4956 = n4955 & (~\[1594] | Ng1000); - assign n4957 = (~Ng853 | Ng320) & (~\[1612] | Ng318); - assign n4958_1 = n4957 & (~\[1594] | Ng319); - assign n4959 = (~Ng853 | Ng1004) & (~\[1612] | Ng1002); - assign n4960 = n4959 & (~\[1594] | Ng1003); - assign n4961 = (~Ng853 | Ng1695) & (~\[1612] | Ng1693); - assign n4962 = n4961 & (~\[1594] | Ng1694); - assign n4963_1 = (~Ng1315 | ~Ng620) & (~\[1605] | ~Ng614); - assign n4964 = n4963_1 & (~\[1603] | ~Ng617); - assign n4965 = (~Ng853 | Ng1007) & (~\[1612] | Ng1005); - assign n4966 = n4965 & (~\[1594] | Ng1006); - assign n4967 = (~Ng853 | Ng1698) & (~\[1612] | Ng1696); - assign n4968_1 = n4967 & (~\[1594] | Ng1697); - assign n4969 = (~Ng853 | Ng2389) & (~\[1612] | Ng2387); - assign n4970 = n4969 & (~\[1594] | Ng2388); - assign n4971 = (~Ng1315 | ~Ng1306) & (~\[1605] | ~Ng1300); - assign n4972 = n4971 & (~\[1603] | ~Ng1303); - assign n4973_1 = (~Ng853 | Ng1701) & (~\[1612] | Ng1699); - assign n4974 = n4973_1 & (~\[1594] | Ng1700); - assign n4975 = (~Ng853 | Ng2392) & (~\[1612] | Ng2390); - assign n4976 = n4975 & (~\[1594] | Ng2391); - assign n4977 = (~Ng1315 | ~Ng2000) & (~\[1605] | ~Ng1994); - assign n4978_1 = n4977 & (~\[1603] | ~Ng1997); - assign n4979 = (~Ng853 | Ng2395) & (~\[1612] | Ng2393); - assign n4980 = n4979 & (~\[1594] | Ng2394); - assign n4981 = (~Ng1315 | ~Ng2694) & (~\[1605] | ~Ng2688); - assign n4982 = n4981 & (~\[1603] | ~Ng2691); - assign n4983_1 = (~Ng1315 | Ng575) & (~\[1605] | Ng576); - assign n4984 = n4983_1 & (~\[1603] | Ng577); - assign n4985 = (~Ng1315 | Ng578) & (~\[1605] | Ng579); - assign n4986 = n4985 & (~\[1603] | Ng580); - assign n4987 = (~Ng1315 | Ng1261) & (~\[1605] | Ng1262); - assign n4988_1 = n4987 & (~\[1603] | Ng1263); - assign n4989 = (~Ng853 | ~Ng414) & (~\[1612] | ~Ng408); - assign n4990 = n4989 & (~\[1594] | ~Ng411); - assign n4991 = (~Ng1315 | Ng581) & (~\[1605] | Ng582); - assign n4992 = n4991 & (~\[1603] | Ng583); - assign n4993_1 = (~Ng1315 | Ng1264) & (~\[1605] | Ng1265); - assign n4994 = n4993_1 & (~\[1603] | Ng1266); - assign n4995 = (~Ng1315 | Ng1955) & (~\[1605] | Ng1956); - assign n4996 = n4995 & (~\[1603] | Ng1957); - assign n4997 = (~Ng853 | ~Ng423) & (~\[1612] | ~Ng417); - assign n4998_1 = n4997 & (~\[1594] | ~Ng420); - assign n4999 = (~Ng1315 | Ng584) & (~\[1605] | Ng585); - assign n5000 = n4999 & (~\[1603] | Ng586); - assign n5001 = (~Ng853 | ~Ng1101) & (~\[1612] | ~Ng1095); - assign n5002 = n5001 & (~\[1594] | ~Ng1098); - assign n5003_1 = (~Ng1315 | Ng1267) & (~\[1605] | Ng1268); - assign n5004 = n5003_1 & (~\[1603] | Ng1269); - assign n5005 = (~Ng1315 | Ng1958) & (~\[1605] | Ng1959); - assign n5006 = n5005 & (~\[1603] | Ng1960); - assign n5007 = (~Ng1315 | Ng2649) & (~\[1605] | Ng2650); - assign n5008_1 = n5007 & (~\[1603] | Ng2651); - assign n5009 = (~Ng853 | ~Ng1110) & (~\[1612] | ~Ng1104); - assign n5010 = n5009 & (~\[1594] | ~Ng1107); - assign n5011 = (~Ng1315 | Ng1270) & (~\[1605] | Ng1271); - assign n5012 = n5011 & (~\[1603] | Ng1272); - assign n5013_1 = (~Ng853 | ~Ng1795) & (~\[1612] | ~Ng1789); - assign n5014 = n5013_1 & (~\[1594] | ~Ng1792); - assign n5015 = (~Ng1315 | Ng1961) & (~\[1605] | Ng1962); - assign n5016 = n5015 & (~\[1603] | Ng1963); - assign n5017 = (~Ng1315 | Ng2652) & (~\[1605] | Ng2653); - assign n5018_1 = n5017 & (~\[1603] | Ng2654); - assign n5019 = (~Ng853 | Ng171) & (~\[1594] | Ng173); - assign n5020 = n5019 & (~\[1612] | Ng172); - assign n5021 = (~Ng853 | ~Ng1804) & (~\[1612] | ~Ng1798); - assign n5022 = n5021 & (~\[1594] | ~Ng1801); - assign n5023_1 = (~Ng1315 | Ng1964) & (~\[1605] | Ng1965); - assign n5024 = n5023_1 & (~\[1603] | Ng1966); - assign n5025 = (~Ng853 | ~Ng2489) & (~\[1612] | ~Ng2483); - assign n5026 = n5025 & (~\[1594] | ~Ng2486); - assign n5027 = (~Ng1315 | Ng2655) & (~\[1605] | Ng2656); - assign n5028_1 = n5027 & (~\[1603] | Ng2657); - assign n5029 = (~Ng853 | Ng174) & (~\[1612] | Ng175); - assign n5030 = n5029 & (~\[1594] | Ng176); - assign n5031 = (~Ng853 | Ng859) & (~\[1612] | Ng860); - assign n5032 = n5031 & (~\[1594] | Ng861); - assign n5033_1 = (~Ng853 | ~Ng2498) & (~\[1612] | ~Ng2492); - assign n5034 = n5033_1 & (~\[1594] | ~Ng2495); - assign n5035 = (~Ng1315 | Ng2658) & (~\[1605] | Ng2659); - assign n5036 = n5035 & (~\[1603] | Ng2660); - assign n5037 = (~Ng853 | Ng862) & (~\[1612] | Ng863); - assign n5038_1 = n5037 & (~\[1594] | Ng864); - assign n5039 = (~Ng853 | Ng1553) & (~\[1612] | Ng1554); - assign n5040 = n5039 & (~\[1594] | Ng1555); - assign n5041 = (~Ng853 | Ng1556) & (~\[1612] | Ng1557); - assign n5042 = n5041 & (~\[1594] | Ng1558); - assign n5043_1 = (~Ng853 | Ng2247) & (~\[1612] | Ng2248); - assign n5044 = n5043_1 & (~\[1594] | Ng2249); - assign n5045 = (~Ng853 | Ng2250) & (~\[1612] | Ng2251); - assign n5046 = n5045 & (~\[1594] | Ng2252); - assign n5047 = Ng2879 & (~Pg8021 | Ng2929); - assign n358_1 = ~n5047; - assign n5049 = (~Ng853 | Ng426) & (~\[1612] | Ng427); - assign n5050 = n5049 & (~\[1594] | Ng428); - assign n5051 = (~Ng853 | Ng1113) & (~\[1612] | Ng1114); - assign n5052 = n5051 & (~\[1594] | Ng1115); - assign n5053_1 = (~Ng1315 | ~Ng611) & (~\[1605] | ~Ng605); - assign n5054 = n5053_1 & (~\[1603] | ~Ng608); - assign n5055 = (~Ng853 | Ng1807) & (~\[1612] | Ng1808); - assign n5056 = n5055 & (~\[1594] | Ng1809); - assign n5057 = (~Ng1315 | ~Ng1297) & (~\[1605] | ~Ng1291); - assign n5058_1 = n5057 & (~\[1603] | ~Ng1294); - assign n5059 = (~Ng853 | Ng2501) & (~\[1612] | Ng2502); - assign n5060 = n5059 & (~\[1594] | Ng2503); - assign n5061 = (~Ng1315 | ~Ng1991) & (~\[1605] | ~Ng1985); - assign n5062 = n5061 & (~\[1603] | ~Ng1988); - assign n5063_1 = (~Ng1315 | ~Ng2685) & (~\[1605] | ~Ng2679); - assign n5064 = n5063_1 & (~\[1603] | ~Ng2682); - assign n5065 = ~Ng557 & (Ng525 | Ng510); - assign n5066 = ~Ng510 & (Ng525 | Ng557); - assign n5067_1 = ~Ng1243 & (Ng1211 | Ng1196); - assign n5068 = ~Ng1196 & (Ng1211 | Ng1243); - assign n5069 = ~Ng1937 & (Ng1905 | Ng1890); - assign n5070 = ~Ng1890 & (Ng1905 | Ng1937); - assign n5071 = ~Ng2631 & (Ng2599 | Ng2584); - assign n5072_1 = ~Ng2584 & (Ng2599 | Ng2631); - assign n5073 = n1739_1 | ~Ng185 | ~Ng524; - assign n5074 = (~Ng1315 | ~Ng593) & (~\[1605] | ~Ng587); - assign n5075 = n5073 & n5074 & (~\[1603] | ~Ng590); - assign n5076 = n3245_1 | ~Ng185 | ~Ng1210; - assign n5077_1 = (~Ng1315 | ~Ng1279) & (~\[1605] | ~Ng1273); - assign n5078 = n5076 & n5077_1 & (~\[1603] | ~Ng1276); - assign n5079 = n4752 | ~Ng185 | ~Ng1904; - assign n5080_1 = (~Ng1315 | ~Ng1973) & (~\[1605] | ~Ng1967); - assign n5081 = n5079 & n5080_1 & (~\[1603] | ~Ng1970); - assign n5082 = n6259 | ~Ng185 | ~Ng2598; - assign n5083 = (~Ng1315 | ~Ng2667) & (~\[1605] | ~Ng2661); - assign n5084 = n5082 & n5083 & (~\[1603] | ~Ng2664); - assign n274_1 = ~Pg51 & Ng13457; - assign n279_1 = ~Pg51 & Ng2817; - assign n5087 = n6275 & (~Ng659 | n6276_1); - assign n2127_1 = ~n5087; - assign n5089 = n6275 & (~Ng1345 | n6276_1); - assign n3646_1 = ~n5089; - assign n5091 = n6275 & (~Ng2039 | n6276_1); - assign n5140 = ~n5091; - assign n5093 = n6275 & (~Ng2733 | n6276_1); - assign n6647 = ~n5093; - assign n284_1 = Pg51 | Ng2933; - assign n6922 = Ng3079 | Pg3234; - assign n5097 = n6270 & (n6271 | ~Ng554); - assign n1724_1 = ~n5097; - assign n5099 = n6270 & (n6271 | ~Ng1240); - assign n3230_1 = ~n5099; - assign n5101 = n6270 & (n6271 | ~Ng1934); - assign n4737 = ~n5101; - assign n5103 = n6270 & (n6271 | ~Ng2628); - assign n6244 = ~n5103; - assign n5105_1 = n6274 ^ ~Ng640; - assign n5106 = ~\[1603] | ~Ng630; - assign n2132 = n5105_1 & n5106; - assign n5108 = n6273 ^ ~Ng1326; - assign n5109 = ~\[1603] | ~Ng1316; - assign n3651_1 = n5108 & n5109; - assign n5111 = n6272_1 ^ ~Ng2020; - assign n5112 = ~\[1603] | ~Ng2010; - assign n5145 = n5111 & n5112; - assign n5114 = n6269 ^ ~Ng2714; - assign n5115_1 = ~\[1603] | ~Ng2704; - assign n6652 = n5114 & n5115_1; - assign n5117 = n6258 | Pg8021; - assign n5118 = ~Ng2883 ^ ~Ng13457; - assign n289_1 = n5117 | n5118; - assign n6912 = ~Pg3234 & Ng13475; - assign n6917 = ~Pg3234 & Ng3054; - assign n5122 = ~n6266 ^ ~Ng633; - assign n2137 = n5122 & n5106; - assign n5124 = ~n6264 ^ ~Ng1319; - assign n3656_1 = n5124 & n5109; - assign n5126 = ~n4950 | n4954 | n4958_1; - assign n5127 = Ng2896 | Ng2900 | Ng2908 | Ng2892 | Ng2903; - assign n5128 = n5126 & (n5127 | ~n6231_1); - assign n5129 = ~n6262 ^ ~Ng2013; - assign n5150 = n5129 & n5112; - assign n5131 = ~n4956 | n4960 | n4966; - assign n5132 = n5131 & (n5127 | ~n6227_1); - assign n5133 = ~n6260 ^ ~Ng2707; - assign n6657 = n5133 & n5115_1; - assign n5135_1 = ~n4962 | n4968_1 | n4974; - assign n5136 = n5135_1 & (n5127 | ~n6223_1); - assign n5137 = ~n4970 | n4976 | n4980; - assign n5138 = n5137 & (n5127 | ~n6219_1); - assign n5139 = n5117 & (Pg8021 | n6237); - assign n5140_1 = ~n6258 ^ ~Ng2912; - assign n324_1 = n5139 | n5140_1; - assign n5142 = n6192 & (~n8750 | (~n4575 & ~n5054)); - assign n2059_1 = ~n5142; - assign n5144 = n6234 & (Pg3234 | n6233); - assign n5145_1 = ~n6256 ^ ~Ng3018; - assign n7141 = n5144 | n5145_1; - assign n5147 = n6187_1 & (~n8750 | (~n4577_1 & ~n5058_1)); - assign n3565_1 = ~n5147; - assign n5149 = n6182 & (~n8750 | (~n4579 & ~n5062)); - assign n5072 = ~n5149; - assign n5151 = ~Ng2888 ^ ~n6268; - assign n294_1 = ~n5117 & n5151; - assign n5153 = ~\[1605] | ~Ng630; - assign n5154 = \[1605] & n6579_1; - assign n2377 = n5153 & (Ng738 | n5154); - assign n5156 = n6177 & (~n8750 | (~n4581 & ~n5064)); - assign n6579 = ~n5156; - assign n5158 = \[1603] & n6579_1; - assign n2382 = n5106 & (Ng739 | n5158); - assign n5160_1 = ~\[1605] | ~Ng1316; - assign n5161 = \[1605] & n6578; - assign n3896 = n5160_1 & (Ng1424 | n5161); - assign n5163 = n8547 & n8548 & (~\[1605] | Ng729); - assign n5164 = n4820 & n5163 & (~\[1603] | Ng730); - assign n5165_1 = ~Ng1315 | ~Ng630; - assign n5166 = Ng1315 & n6579_1; - assign n2387 = n5165_1 & (Ng737 | n5166); - assign n5168 = \[1603] & n6578; - assign n3901 = n5109 & (Ng1425 | n5168); - assign n5170_1 = ~\[1605] | ~Ng2010; - assign n5171 = \[1605] & n6577; - assign n5390 = n5170_1 & (Ng2118 | n5171); - assign n5173 = n8544 & n8545 & (~\[1605] | Ng1415); - assign n5174 = n4862 & n5173 & (~\[1603] | Ng1416); - assign n5175_1 = ~Ng1315 | ~Ng1316; - assign n5176 = Ng1315 & n6578; - assign n3906 = n5175_1 & (Ng1423 | n5176); - assign n5178 = \[1603] & n6577; - assign n5395 = n5112 & (Ng2119 | n5178); - assign n5180_1 = ~\[1605] | ~Ng2704; - assign n5181 = \[1605] & n6575; - assign n6897 = n5180_1 & (Ng2812 | n5181); - assign n5183 = n8541 & n8542 & (~\[1605] | Ng2109); - assign n5184 = n4900 & n5183 & (~\[1603] | Ng2110); - assign n5185_1 = ~Ng1315 | ~Ng2010; - assign n5186 = Ng1315 & n6577; - assign n5400 = n5185_1 & (Ng2117 | n5186); - assign n5188 = \[1603] & n6575; - assign n6902 = n5115_1 & (Ng2813 | n5188); - assign n5190_1 = n8538 & n8539 & (~\[1605] | Ng2803); - assign n5191 = n4930 & n5190_1 & (~\[1603] | Ng2804); - assign n5192 = ~Ng1315 | ~Ng2704; - assign n5193 = Ng1315 & n6575; - assign n6907 = n5192 & (Ng2811 | n5193); - assign n868_1 = ~n858_1 & (n5978_1 | Ng3123); - assign n5196 = ~Ng653 ^ ~n6267_1; - assign n2142_1 = n5196 & n5106; - assign n5198 = ~Ng1339 ^ ~n6265; - assign n3661_1 = n5198 & n5109; - assign n5200_1 = ~n6572 ^ ~Ng3006; - assign n7116 = n5200_1 & ~n6234; - assign n5202 = ~Ng2033 ^ ~n6263_1; - assign n5155 = n5202 & n5112; - assign n5204 = ~Ng2727 ^ ~n6261; - assign n6662 = n5204 & n5115_1; - assign n5206 = ~Ng2917 ^ ~n6259_1; - assign n329 = ~n5139 & n5206; - assign n5208 = ~n6254_1 ^ ~Ng2896; - assign n299_1 = ~n5117 & n5208; - assign n5210_1 = ~Ng3028 ^ ~n6257; - assign n7146 = ~n5144 & n5210_1; - assign n863_1 = ~n858_1 & (n5978_1 | Ng3125); - assign n5213 = ~n6250 ^ ~Ng646; - assign n2147_1 = n5213 & n5106; - assign n5215_1 = ~n6247 ^ ~Ng1332; - assign n3666_1 = n5215_1 & n5109; - assign n5217 = ~n6244_1 ^ ~Ng2026; - assign n5160 = n5217 & n5112; - assign n5219 = ~n6240 ^ ~Ng2720; - assign n6667 = n5219 & n5115_1; - assign n5221 = n6253 ^ ~Ng3002; - assign n7121 = n5221 & ~n6234; - assign n5223 = ~n6235_1 ^ ~Ng3036; - assign n7151 = ~n5144 & n5223; - assign n5225_1 = ~Ng2892 ^ ~n6255; - assign n304_1 = ~n5117 & n5225_1; - assign n5227 = ~n6238 ^ ~Ng2924; - assign n334_1 = ~n5139 & n5227; - assign n5229 = n6252 ^ ~Ng88; - assign n5230_1 = n6521 | n5127; - assign n1263_1 = n5229 & n5230_1; - assign n5232 = n6249_1 ^ ~Ng776; - assign n2769_1 = n5232 & n5230_1; - assign n5234 = n6246 ^ ~Ng1462; - assign n4276 = n5234 & n5230_1; - assign n5236 = n6243 ^ ~Ng2156; - assign n5770 = n5236 & n5230_1; - assign n853_1 = n6039 & n6038_1 & n6037 & n6035 & n6036 & n6040 & n6041 & n6042; - assign n5239 = ~Ng660 ^ ~n6251; - assign n2152_1 = n5239 & n5106; - assign n5241 = ~Ng1346 ^ ~n6248; - assign n3671_1 = n5241 & n5109; - assign n5243 = Ng3013 ^ ~n6573; - assign n7126 = n5243 & ~n6234; - assign n5245_1 = ~Ng2040 ^ ~n6245; - assign n5165 = n5245_1 & n5112; - assign n5247 = ~Ng2734 ^ ~n6241; - assign n6672 = n5247 & n5115_1; - assign n5249 = ~Ng2920 ^ ~n6239_1; - assign n339 = ~n5139 & n5249; - assign n5251 = ~n6574_1 ^ ~Ng2903; - assign n309_1 = ~n5117 & n5251; - assign n5253 = ~Ng3032 ^ ~n6236; - assign n7156 = ~n5144 & n5253; - assign n5255_1 = ~n6215_1 ^ ~Ng83; - assign n1268 = n5255_1 & n5230_1; - assign n5257 = ~n6211_1 ^ ~Ng771; - assign n2774_1 = n5257 & n5230_1; - assign n5259 = ~n6207_1 ^ ~Ng1457; - assign n4281_1 = n5259 & n5230_1; - assign n5261 = ~n6203_1 ^ ~Ng2151; - assign n5775 = n5261 & n5230_1; - assign n5263 = ~n6213 ^ ~Ng672; - assign n2157_1 = n5263 & n5106; - assign n5265_1 = ~n6209 ^ ~Ng1358; - assign n3676_1 = n5265_1 & n5109; - assign n5267 = ~n6205 ^ ~Ng2052; - assign n5170 = n5267 & n5112; - assign n5269 = ~n6201 ^ ~Ng2746; - assign n6677 = n5269 & n5115_1; - assign n5271 = n6197 ^ ~Ng3010; - assign n7131 = n5271 & ~n6234; - assign n5273 = ~Ng2900 ^ ~n6199_1; - assign n314_1 = ~n5117 & n5273; - assign n5275_1 = ~Ng79 ^ ~n6216; - assign n1273_1 = n5275_1 & n5230_1; - assign n5277 = ~Ng767 ^ ~n6212; - assign n2779_1 = n5277 & n5230_1; - assign n5279 = ~Ng1453 ^ ~n6208; - assign n4286 = n5279 & n5230_1; - assign n5281 = ~Ng2147 ^ ~n6204; - assign n5780 = n5281 & n5230_1; - assign n893_1 = ~n858_1 & n5977 & (Ng185 | n5978_1); - assign n5284 = ~Ng666 ^ ~n6214; - assign n2162_1 = n5284 & n5106; - assign n5286 = ~Ng1352 ^ ~n6210; - assign n3681_1 = n5286 & n5109; - assign n7136 = ~n6234 & ~n6584_1; - assign n5289 = ~Ng2046 ^ ~n6206; - assign n5175 = n5289 & n5112; - assign n5291 = ~Ng2740 ^ ~n6202; - assign n6682 = n5291 & n5115_1; - assign n5293 = ~Ng2908 ^ ~n6200; - assign n319_1 = ~n5117 & n5293; - assign n5295_1 = ~n6175_1 ^ ~Ng74; - assign n1278 = n5295_1 & n5230_1; - assign n5297 = ~n6168 ^ ~Ng762; - assign n2784_1 = n5297 & n5230_1; - assign n5299 = ~n6161 ^ ~Ng1448; - assign n4291_1 = n5299 & n5230_1; - assign n5301 = ~n6154 ^ ~Ng2142; - assign n5785 = n5301 & n5230_1; - assign n5303 = ~n6564 ^ ~Ng679; - assign n2167_1 = n5303 & n5106; - assign n5305_1 = ~n6560_1 ^ ~Ng1365; - assign n3686_1 = n5305_1 & n5109; - assign n5307 = ~n6556 ^ ~Ng2059; - assign n5180 = n5307 & n5112; - assign n5309 = ~n6550_1 ^ ~Ng2753; - assign n6687 = n5309 & n5115_1; - assign n5311 = n5918_1 & n5916 & n5917; - assign n5312 = n4672_1 ^ ~n5947; - assign n5313 = n5311 & n5312; - assign n5314 = n5898_1 & n5896 & n5897; - assign n5315_1 = n4692_1 ^ ~n5940; - assign n5316 = n5314 & n5315_1; - assign n5317 = n5878_1 & n5876 & n5877; - assign n5318 = n4716_1 ^ ~n5933_1; - assign n5319 = n5317 & n5318; - assign n5320_1 = n5858_1 & n5856 & n5857; - assign n5321 = n4746 ^ ~n5926; - assign n5322 = n5320_1 & n5321; - assign n5323 = ~Ng70 ^ ~n6176; - assign n1283_1 = n5323 & n5230_1; - assign n5325_1 = ~Ng758 ^ ~n6169; - assign n2789_1 = n5325_1 & n5230_1; - assign n5327 = ~Ng1444 ^ ~n6162; - assign n4296 = n5327 & n5230_1; - assign n5329 = ~Ng2138 ^ ~n6155_1; - assign n5790 = n5329 & n5230_1; - assign n5331 = ~Ng686 ^ ~n6109; - assign n2172_1 = n5331 & n5106; - assign n5333 = ~Ng1372 ^ ~n6087; - assign n3691_1 = n5333 & n5109; - assign n5335_1 = ~Ng2066 ^ ~n6065; - assign n5185 = n5335_1 & n5112; - assign n5337 = ~Ng2760 ^ ~n6043_1; - assign n6692 = n5337 & n5115_1; - assign n5339 = n6571 | ~n4583 | ~Ng2257; - assign n5340_1 = \[1612] & ~n6174; - assign n1443_1 = (~\[1612] | n5339) & (n5340_1 | Ng448); - assign n5342 = \[1594] & ~n6174; - assign n1448_1 = (~\[1594] | n5339) & (Ng449 | n5342); - assign n5344 = n6570_1 | ~n4591_1 | ~Ng2257; - assign n5345_1 = \[1612] & ~n6167_1; - assign n2949_1 = (~\[1612] | n5344) & (n5345_1 | Ng1135); - assign n5347 = Ng853 & ~n6174; - assign n1453 = (~Ng853 | n5339) & (n5347 | Ng447); - assign n5349 = \[1594] & ~n6167_1; - assign n2954_1 = (~\[1594] | n5344) & (Ng1136 | n5349); - assign n5351 = n6569 | ~n4601 | ~Ng2257; - assign n5352 = \[1612] & ~n6160; - assign n4456_1 = (~\[1612] | n5351) & (n5352 | Ng1829); - assign n5354 = Ng853 & ~n6167_1; - assign n2959_1 = (~Ng853 | n5344) & (n5354 | Ng1134); - assign n5356 = \[1594] & ~n6160; - assign n4461 = (~\[1594] | n5351) & (Ng1830 | n5356); - assign n5358 = n6568 | ~n4613_1 | ~Ng2257; - assign n5359 = \[1612] & ~n6153; - assign n5963 = (~\[1612] | n5358) & (n5359 | Ng2523); - assign n5361 = Ng853 & ~n6160; - assign n4466 = (~Ng853 | n5351) & (n5361 | Ng1828); - assign n5363 = \[1594] & ~n6153; - assign n5968 = (~\[1594] | n5358) & (Ng2524 | n5363); - assign n5365_1 = Ng853 & ~n6153; - assign n5973 = (~Ng853 | n5358) & (n5365_1 | Ng2522); - assign n5367 = ~n6033_1 ^ ~Ng65; - assign n1288 = n5367 & n5230_1; - assign n5369 = ~n6029 ^ ~Ng753; - assign n2794_1 = n5369 & n5230_1; - assign n5371 = ~n6025 ^ ~Ng1439; - assign n4301 = n5371 & n5230_1; - assign n5373 = ~n6021 ^ ~Ng2133; - assign n5795 = n5373 & n5230_1; - assign n5375_1 = ~Ng692 ^ ~n6110; - assign n2177 = n5375_1 & n5106; - assign n5377 = ~Ng1378 ^ ~n6088; - assign n3696_1 = n5377 & n5109; - assign n5379 = ~Ng2072 ^ ~n6066_1; - assign n5190 = n5379 & n5112; - assign n5381 = ~Ng2766 ^ ~n6044; - assign n6697 = n5381 & n5115_1; - assign n5383 = ~Ng61 ^ ~n6034; - assign n1293_1 = n5383 & n5230_1; - assign n5385_1 = ~Ng749 ^ ~n6030; - assign n2799_1 = n5385_1 & n5230_1; - assign n5387 = ~Ng1435 ^ ~n6026; - assign n4306_1 = n5387 & n5230_1; - assign n5389 = ~Ng2129 ^ ~n6022; - assign n5800 = n5389 & n5230_1; - assign n5391 = ~\[1612] | n6530_1; - assign n5392 = n4990 & ~n5663 & Ng2257; - assign n1398_1 = n5391 & (Ng427 | (\[1612] & n5392)); - assign n5394 = ~\[1594] | n6530_1; - assign n1403 = n5394 & (Ng428 | (\[1594] & n5392)); - assign n5396 = ~\[1612] | n6529; - assign n5397 = n5002 & ~n5666 & Ng2257; - assign n2904 = n5396 & (Ng1114 | (\[1612] & n5397)); - assign n5399 = ~Ng853 | n6530_1; - assign n1408_1 = n5399 & (Ng426 | (Ng853 & n5392)); - assign n5401 = ~\[1594] | n6529; - assign n2909_1 = n5401 & (Ng1115 | (\[1594] & n5397)); - assign n5403 = ~\[1612] | n6528; - assign n5404 = n5014 & ~n5669 & Ng2257; - assign n4411 = n5403 & (Ng1808 | (\[1612] & n5404)); - assign n5406 = ~Ng853 | n6529; - assign n2914_1 = n5406 & (Ng1113 | (Ng853 & n5397)); - assign n5408 = ~\[1594] | n6528; - assign n4416 = n5408 & (Ng1809 | (\[1594] & n5404)); - assign n5410_1 = ~\[1612] | n6527; - assign n5411 = n5026 & ~n5672 & Ng2257; - assign n5918 = n5410_1 & (Ng2502 | (\[1612] & n5411)); - assign n5413 = ~Ng853 | n6528; - assign n4421 = n5413 & (Ng1807 | (Ng853 & n5404)); - assign n5415_1 = ~\[1594] | n6527; - assign n5923 = n5415_1 & (Ng2503 | (\[1594] & n5411)); - assign n5417 = ~Ng853 | n6527; - assign n5928 = n5417 & (Ng2501 | (Ng853 & n5411)); - assign n5419 = ~n5971 ^ ~Ng56; - assign n1298 = n5419 & n5230_1; - assign n5421 = ~n5968_1 ^ ~Ng744; - assign n2804_1 = n5421 & n5230_1; - assign n5423 = ~n5965 ^ ~Ng1430; - assign n4311_1 = n5423 & n5230_1; - assign n5425_1 = ~n5962 ^ ~Ng2124; - assign n5805 = n5425_1 & n5230_1; - assign n5427 = ~Ng52 ^ ~n5972; - assign n1303 = n5427 & n5230_1; - assign n5429 = ~Ng740 ^ ~n5969; - assign n2809_1 = n5429 & n5230_1; - assign n5431 = ~Ng1426 ^ ~n5966; - assign n4316 = n5431 & n5230_1; - assign n5433 = ~Ng2120 ^ ~n5963_1; - assign n5810 = n5433 & n5230_1; - assign n5435_1 = n5542 | n5920; - assign n5436 = n4585 | n6013_1; - assign n5437 = n5435_1 & n5436 & (~n4958_1 | ~n5542); - assign n5438 = n5544 | n5900; - assign n5439 = n4593 | n6005; - assign n5440_1 = n5438 & n5439 & (~n4966 | ~n5544); - assign n5441 = n5546 | n5880; - assign n5442 = n4603 | n5997; - assign n5443 = n5441 & n5442 & (~n4974 | ~n5546); - assign n5444 = n5548 | n5860; - assign n5445_1 = n4615 | n5989; - assign n5446 = n5444 & n5445_1 & (~n4980 | ~n5548); - assign n5447 = n4672_1 ^ ~n5311; - assign n5448 = ~n5030 & ~n5923_1; - assign n5449 = (n5448 | ~n5828_1) & (n5447 | ~n5925); - assign n5450_1 = ~n4684_1 ^ ~n6379; - assign n5451 = Ng101 & ~n5923_1; - assign n5452 = (n5451 | ~n5828_1) & (n5450_1 | ~n5925); - assign n5453 = n4692_1 ^ ~n5314; - assign n5454 = ~n5038_1 & ~n5903_1; - assign n5455_1 = (n5454 | ~n5829) & (n5453 | ~n5905); - assign n5456 = ~n4702 ^ ~n6378_1; - assign n5457 = Ng109 & ~n5923_1; - assign n5458 = (n5457 | ~n5828_1) & (n5456 | ~n5925); - assign n5459 = ~n4708_1 ^ ~n6355; - assign n5460_1 = Ng789 & ~n5903_1; - assign n5461 = (n5460_1 | ~n5829) & (n5459 | ~n5905); - assign n5462 = n4716_1 ^ ~n5317; - assign n5463 = ~n5042 & ~n5883_1; - assign n5464 = (n5463 | ~n5830) & (n5462 | ~n5885); - assign n5465_1 = ~n4732_1 ^ ~n6354; - assign n5466 = Ng797 & ~n5903_1; - assign n5467 = (n5466 | ~n5829) & (n5465_1 | ~n5905); - assign n5468 = ~n4738 ^ ~n6331_1; - assign n5469 = Ng1476 & ~n5883_1; - assign n5470_1 = (n5469 | ~n5830) & (n5468 | ~n5885); - assign n5471 = n4746 ^ ~n5320_1; - assign n5472 = ~n5046 & ~n5863_1; - assign n5473 = (n5472 | ~n5831) & (n5471 | ~n5865); - assign n5474 = ~n4768 ^ ~n6330; - assign n5475_1 = Ng1486 & ~n5883_1; - assign n5476 = (n5475_1 | ~n5830) & (n5474 | ~n5885); - assign n5477 = ~n4774_1 ^ ~n6307; - assign n5478 = Ng2170 & ~n5863_1; - assign n5479 = (n5478 | ~n5831) & (n5477 | ~n5865); - assign n5480_1 = n4782 ^ ~n5313; - assign n5481 = ~n5020 & ~n5923_1; - assign n5482 = (n5481 | ~n5828_1) & (n5480_1 | ~n5925); - assign n5483 = ~n4810_1 ^ ~n6306; - assign n5484 = Ng2180 & ~n5863_1; - assign n5485_1 = (n5484 | ~n5831) & (n5483 | ~n5865); - assign n5486 = ~n4814_1 ^ ~n6380; - assign n5487 = Ng105 & ~n5923_1; - assign n5488 = (n5487 | ~n5828_1) & (n5486 | ~n5925); - assign n5489 = n4824_1 ^ ~n5316; - assign n5490_1 = ~n5032 & ~n5903_1; - assign n5491 = (n5490_1 | ~n5829) & (n5489 | ~n5905); - assign n5492 = ~n4856_1 ^ ~n6356; - assign n5493 = Ng793 & ~n5903_1; - assign n5494 = (n5493 | ~n5829) & (n5492 | ~n5905); - assign n5495_1 = n4866_1 ^ ~n5319; - assign n5496 = ~n5040 & ~n5883_1; - assign n5497 = (n5496 | ~n5830) & (n5495_1 | ~n5885); - assign n5498 = ~n4894 ^ ~n6332; - assign n5499 = Ng1481 & ~n5883_1; - assign n5500_1 = (n5499 | ~n5830) & (n5498 | ~n5885); - assign n5501 = n4904 ^ ~n5322; - assign n5502 = ~n5044 & ~n5863_1; - assign n5503 = (n5502 | ~n5831) & (n5501 | ~n5865); - assign n5504 = ~n4924_1 ^ ~n6308_1; - assign n5505_1 = Ng2175 & ~n5863_1; - assign n5506 = (n5505_1 | ~n5831) & (n5504 | ~n5865); - assign n5507 = ~n4854 | n4964; - assign n5508 = ~n4964 & ~n5981; - assign n5509 = n5507 & ~n5826 & (n4854 | n5508); - assign n5510_1 = n5981 & n5054; - assign n5511 = ~n5826 & (n5510_1 | ~n6981_1); - assign n5512 = n5981 & n4964; - assign n5513 = ~n5826 & (n5512 | ~n6982); - assign n5514 = ~n4818 | n5054; - assign n5515_1 = n5514 & ~n5826 & (n4818 | ~n8450); - assign n5516 = ~n5826 & (n5510_1 | ~n6980); - assign n5517 = ~n4686 | n4964; - assign n5518 = n5517 & ~n5826 & (n4686 | n5508); - assign n5519 = ~n4788 | n4964; - assign n5520_1 = n5519 & ~n5826 & (n4788 | n5508); - assign n5521 = ~n4886 | n5054; - assign n5522 = n5521 & ~n5826 & (n4886 | ~n8450); - assign n5523 = Pg563 | n5979 | Ng559 | ~n6600; - assign n5524 = ~n6016 & (n5523 | (Ng8284 & ~n5825)); - assign n5525_1 = ~n4916 | n5058_1; - assign n5526 = n5525_1 & ~n5823_1 & (n4916 | ~n8451); - assign n5527 = ~n4892_1 | n4972; - assign n5528 = ~n4972 & ~n5955; - assign n5529 = n5527 & ~n5823_1 & (n4892_1 | n5528); - assign n5530_1 = n5955 & n5058_1; - assign n5531 = ~n5823_1 & (n5530_1 | ~n6951_1); - assign n5532 = n5955 & n4972; - assign n5533 = ~n5823_1 & (n5532 | ~n6952); - assign n5534 = ~n4860 | n5058_1; - assign n5535_1 = n5534 & ~n5823_1 & (n4860 | ~n8451); - assign n5536 = ~n5823_1 & (n5530_1 | ~n6950); - assign n5537 = ~n4710 | n4972; - assign n5538 = n5537 & ~n5823_1 & (n4710 | n5528); - assign n5539 = ~n4830 | n4972; - assign n5540_1 = n5539 & ~n5823_1 & (n4830 | n5528); - assign n5541 = (~n5911 & (n4958_1 | n6514)) | (~n4958_1 & n6514); - assign n5542 = ~n4950 & ~n8584 & (n4954 | n5541); - assign n5543 = (~n5891 & (n4966 | n6504)) | (~n4966 & n6504); - assign n5544 = ~n4956 & ~n8583 & (n4960 | n5543); - assign n5545_1 = (~n5871 & (n4974 | n6494)) | (~n4974 & n6494); - assign n5546 = ~n4962 & ~n8582 & (n4968_1 | n5545_1); - assign n5547 = (~n5851 & (n4980 | n6484)) | (~n4980 & n6484); - assign n5548 = ~n4970 & ~n8581 & (n4976 | n5547); - assign n5549 = ~n6601 | Pg1249 | Ng1245; - assign n5550_1 = ~n5958_1 & (n5549 | (Ng8293 & ~n5822)); - assign n5551 = ~n5914 & (~n4958_1 | n5908_1 | ~n6514); - assign n5552 = ~n4950 & ~n8577 & (n4954 | n5551); - assign n5553 = ~n5894 & (~n4966 | n5888_1 | ~n6504); - assign n5554 = ~n4956 & ~n8572 & (n4960 | n5553); - assign n5555_1 = ~n5874 & (~n4974 | n5868_1 | ~n6494); - assign n5556 = ~n4962 & ~n8567 & (n4968_1 | n5555_1); - assign n5557 = ~n5854 & (~n4980 | n5848_1 | ~n6484); - assign n5558 = ~n4970 & ~n8562 & (n4976 | n5557); - assign n5559 = (~n4872 & n8452) | (n4978_1 & (n4872 | n8452)); - assign n5560_1 = n5559 & ~n5820; - assign n5561 = (~n4936 & ~n8453) | (n5062 & (n4936 | ~n8453)); - assign n5562 = n5561 & ~n5820; - assign n5563 = (~n4922 & n8452) | (n4978_1 & (n4922 | n8452)); - assign n5564 = n5563 & ~n5820; - assign n5565_1 = n5062 & ~n5840; - assign n5566 = ~n5820 & (n5565_1 | ~n6617_1); - assign n5567 = n4978_1 & ~n5840; - assign n5568 = ~n5820 & (n5567 | ~n6618); - assign n5569 = (~n4898 & ~n8453) | (n5062 & (n4898 | ~n8453)); - assign n5570_1 = n5569 & ~n5820; - assign n5571 = ~n5820 & (n5565_1 | ~n6616); - assign n5572 = (~n4740 & n8452) | (n4978_1 & (n4740 | n8452)); - assign n5573 = n5572 & ~n5820; - assign n5574 = ~n6602_1 | Pg1943 | Ng1939; - assign n5575_1 = ~n5843_1 & (n5574 | (Ng8302 & ~n5819_1)); - assign n5576 = n5591 | ~Ng8311; - assign n5577 = n5576 | ~n8554; - assign n5578 = (~n4910_1 & n8454) | (n4982 & (n4910_1 | n8454)); - assign n5579 = ~n5576 & n5578; - assign n5580_1 = (~n4948_1 & ~n8455) | (n5064 & (n4948_1 | ~n8455)); - assign n5581 = ~n5576 & n5580_1; - assign n5582 = (~n4942 & n8454) | (n4982 & (n4942 | n8454)); - assign n5583 = ~n5576 & n5582; - assign n5584 = n5064 & ~n5833_1; - assign n5585_1 = ~n5576 & (n5584 | ~n6606); - assign n5586 = n4982 & ~n5833_1; - assign n5587 = ~n5576 & (n5586 | ~n6607_1); - assign n5588 = (~n4928_1 & ~n8455) | (n5064 & (n4928_1 | ~n8455)); - assign n5589 = ~n5576 & n5588; - assign n5590_1 = ~n5576 & (n5584 | ~n6605); - assign n5591 = ~n6603 | Pg2637 | Ng2633; - assign n5592 = ~n5836 & (n5591 | (Ng8311 & ~n5817)); - assign n5593 = Ng2874 ^ ~Ng2981; - assign n5594 = Ng2978 ^ ~Ng2975; - assign n5595_1 = ~Ng2874 ^ ~Ng2981; - assign n5596 = ~Ng2978 ^ ~Ng2975; - assign n5597 = (n5593 | n5594) & (n5595_1 | n5596); - assign n5598 = Ng2972 ^ ~Ng2969; - assign n5599 = Ng2966 ^ ~Ng2963; - assign n5600_1 = ~Ng2972 ^ ~Ng2969; - assign n5601 = ~Ng2966 ^ ~Ng2963; - assign n5602 = (n5598 | n5599) & (n5600_1 | n5601); - assign n5603 = Ng2959 ^ ~Ng2956; - assign n5604 = Ng2953 ^ ~Ng2947; - assign n5605_1 = ~Ng2959 ^ ~Ng2956; - assign n5606 = ~Ng2953 ^ ~Ng2947; - assign n5607 = (n5603 | n5604) & (n5605_1 | n5606); - assign n5608 = Ng2944 ^ ~Ng2941; - assign n5609 = Ng2938 ^ ~Ng2935; - assign n5610_1 = ~Ng2944 ^ ~Ng2941; - assign n5611 = ~Ng2938 ^ ~Ng2935; - assign n5612 = (n5608 | n5609) & (n5610_1 | n5611); - assign n5613 = ~n5826 & (n5512 | ~n6978); - assign n5614 = ~n5826 & (n5510_1 | ~n6979); - assign n5615_1 = n5509 ^ ~n5522; - assign n5616 = n5515_1 ^ ~n5520_1; - assign n5617 = ~n5509 ^ ~n5522; - assign n5618 = ~n5515_1 ^ ~n5520_1; - assign n5619 = (n5615_1 | n5616) & (n5617 | n5618); - assign n5620_1 = n5516 ^ ~n5518; - assign n5621 = n5511 ^ ~n5513; - assign n5622 = ~n5516 ^ ~n5518; - assign n5623 = ~n5511 ^ ~n5513; - assign n5624 = (n5620_1 | n5621) & (n5622 | n5623); - assign n5625_1 = ~n5823_1 & (n5532 | ~n6948); - assign n5626 = ~n5823_1 & (n5530_1 | ~n6949); - assign n5627 = n5535_1 ^ ~n5540_1; - assign n5628 = n5526 ^ ~n5529; - assign n5629 = ~n5535_1 ^ ~n5540_1; - assign n5630_1 = ~n5526 ^ ~n5529; - assign n5631 = (n5627 | n5628) & (n5629 | n5630_1); - assign n5632 = n5536 ^ ~n5538; - assign n5633 = n5531 ^ ~n5533; - assign n5634 = ~n5536 ^ ~n5538; - assign n5635_1 = ~n5531 ^ ~n5533; - assign n5636 = (n5632 | n5633) & (n5634 | n5635_1); - assign n5637 = ~n5820 & (n5567 | ~n6614); - assign n5638 = ~n5820 & (n5565_1 | ~n6615); - assign n5639 = n5560_1 ^ ~n5570_1; - assign n5640_1 = n5562 ^ ~n5564; - assign n5641 = ~n5560_1 ^ ~n5570_1; - assign n5642 = ~n5562 ^ ~n5564; - assign n5643 = (n5639 | n5640_1) & (n5641 | n5642); - assign n5644 = n5571 ^ ~n5573; - assign n5645_1 = n5566 ^ ~n5568; - assign n5646 = ~n5571 ^ ~n5573; - assign n5647 = ~n5566 ^ ~n5568; - assign n5648 = (n5644 | n5645_1) & (n5646 | n5647); - assign n5649 = ~n5576 & (n5586 | ~n6599); - assign n5650_1 = ~n5576 & (n5584 | ~n6604); - assign n5651 = n5579 ^ ~n5589; - assign n5652 = n5581 ^ ~n5583; - assign n5653 = ~n5579 ^ ~n5589; - assign n5654 = ~n5581 ^ ~n5583; - assign n5655_1 = (n5651 | n5652) & (n5653 | n5654); - assign n5656 = ~n5590_1 ^ ~n5577; - assign n5657 = n5585_1 ^ ~n5587; - assign n5658 = n5577 ^ ~n5590_1; - assign n5659 = ~n5585_1 ^ ~n5587; - assign n5660_1 = (n5656 | n5657) & (n5658 | n5659); - assign n5661 = n6515_1 | ~n4998_1 | ~n5662; - assign n5662 = n6170 & ~n5020 & ~n5030; - assign n5663 = n5661 & (n5662 | n4998_1); - assign n5664 = n6505_1 | ~n5010 | ~n5665_1; - assign n5665_1 = n6163_1 & ~n5032 & ~n5038_1; - assign n5666 = n5664 & (n5665_1 | n5010); - assign n5667 = n6495_1 | ~n5022 | ~n5668; - assign n5668 = n6156 & ~n5040 & ~n5042; - assign n5669 = n5667 & (n5668 | n5022); - assign n5670_1 = n6485_1 | ~n5034 | ~n5671; - assign n5671 = n6149 & ~n5044 & ~n5046; - assign n5672 = n5670_1 & (n5671 | n5034); - assign n6133 = ~n5034; - assign n4626 = ~n5022; - assign n3119_1 = ~n5010; - assign n1613 = ~n4998_1; - assign n5677 = n5834 & (~Ng2584 | n5835); - assign n7101 = ~n5677; - assign n5679 = (~n5071 | ~n8458) & (n5649 | n5836); - assign n7096 = ~n5679; - assign n5681 = (~n5071 | ~n8459) & (n5650_1 | n5836); - assign n7091 = ~n5681; - assign n5683 = n5837 & (~n5071 | ~n8460); - assign n7086 = ~n5683; - assign n5685_1 = n5837 & (~n5071 | ~n8461); - assign n7081 = ~n5685_1; - assign n5687 = ~n5818 & (~n5071 | ~n8462); - assign n7076 = ~n5687; - assign n5689 = ~n5592 & (~n5071 | ~n8463); - assign n7071 = ~n5689; - assign n5691 = ~n5592 & (~n5071 | ~n8464); - assign n7066 = ~n5691; - assign n5693 = ~n5818 & (~n5071 | ~n8465); - assign n7061 = ~n5693; - assign n5695_1 = n5841 & (~Ng1890 | n5842); - assign n7056 = ~n5695_1; - assign n5697 = (~n5069 | ~n8468) & (n5637 | n5843_1); - assign n7051 = ~n5697; - assign n5699 = (~n5069 | ~n8469) & (n5638 | n5843_1); - assign n7046 = ~n5699; - assign n5701 = n5844 & (~n5069 | ~n8470); - assign n7041 = ~n5701; - assign n5703 = n5844 & (~n5069 | ~n8471); - assign n7036 = ~n5703; - assign n5705_1 = ~n5821 & (~n5069 | ~n8472); - assign n7031 = ~n5705_1; - assign n5707 = ~n5575_1 & (~n5069 | ~n8473); - assign n7026 = ~n5707; - assign n5709 = ~n5575_1 & (~n5069 | ~n8474); - assign n7021 = ~n5709; - assign n5711 = ~n5821 & (~n5069 | ~n8475); - assign n7016 = ~n5711; - assign n5713 = n5956 & (~Ng1196 | n5957); - assign n7011 = ~n5713; - assign n5715_1 = (~n5067_1 | ~n8502) & (n5625_1 | n5958_1); - assign n7006 = ~n5715_1; - assign n5717 = (~n5067_1 | ~n8503) & (n5626 | n5958_1); - assign n7001 = ~n5717; - assign n5719 = n5959 & (~n5067_1 | ~n8504); - assign n6996 = ~n5719; - assign n5721 = n5959 & (~n5067_1 | ~n8505); - assign n6991 = ~n5721; - assign n5723 = ~n5824 & (~n5067_1 | ~n8506); - assign n6986 = ~n5723; - assign n5725_1 = ~n5550_1 & (~n5067_1 | ~n8507); - assign n6981 = ~n5725_1; - assign n5727 = ~n5550_1 & (~n5067_1 | ~n8508); - assign n6976 = ~n5727; - assign n5729 = ~n5824 & (~n5067_1 | ~n8509); - assign n6971 = ~n5729; - assign n5731 = n5982 & (~Ng510 | n5983_1); - assign n6966 = ~n5731; - assign n5733 = (~n5065 | ~n8512) & (n5613 | n6016); - assign n6961 = ~n5733; - assign n5735_1 = (~n5065 | ~n8513) & (n5614 | n6016); - assign n6956 = ~n5735_1; - assign n5737 = n6017 & (~n5065 | ~n8514); - assign n6951 = ~n5737; - assign n5739 = n6017 & (~n5065 | ~n8515); - assign n6946 = ~n5739; - assign n5741 = ~n5827 & (~n5065 | ~n8516); - assign n6941 = ~n5741; - assign n5743 = ~n5524 & (~n5065 | ~n8517); - assign n6936 = ~n5743; - assign n5745_1 = ~n5524 & (~n5065 | ~n8518); - assign n6931 = ~n5745_1; - assign n5747 = ~n5827 & (~n5065 | ~n8519); - assign n6926 = ~n5747; - assign n6637 = ~Ng2366; - assign n6627 = ~Ng2364; - assign n6622 = ~Ng2362; - assign n6617 = ~Ng2360; - assign n6612 = ~Ng2358; - assign n6607 = ~Ng2356; - assign n6602 = ~Ng2354; - assign n6597 = ~Ng2528; - assign n6592 = ~Ng2526; - assign n6116 = ~Ng2165; - assign n6107 = ~Ng2170; - assign n6098 = ~Ng2175; - assign n6089 = ~Ng2180; - assign n6080 = ~Ng2185; - assign n6071 = ~Ng2190; - assign n6062 = ~Ng2195; - assign n6053 = ~Ng2200; - assign n5130 = ~Ng1672; - assign n5120 = ~Ng1670; - assign n5115 = ~Ng1668; - assign n5110 = ~Ng1666; - assign n5105 = ~Ng1664; - assign n5100 = ~Ng1662; - assign n5095 = ~Ng1660; - assign n5090 = ~Ng1834; - assign n5085 = ~Ng1832; - assign n4609 = ~Ng1471; - assign n4600 = ~Ng1476; - assign n4591 = ~Ng1481; - assign n4582 = ~Ng1486; - assign n4573 = ~Ng1491; - assign n4564 = ~Ng1496; - assign n4555 = ~Ng1501; - assign n4546 = ~Ng1506; - assign n3623_1 = ~Ng978; - assign n3613_1 = ~Ng976; - assign n3608_1 = ~Ng974; - assign n3603_1 = ~Ng972; - assign n3598_1 = ~Ng970; - assign n3593_1 = ~Ng968; - assign n3588_1 = ~Ng966; - assign n3583_1 = ~Ng1140; - assign n3578_1 = ~Ng1138; - assign n3102 = ~Ng785; - assign n3093_1 = ~Ng789; - assign n3084_1 = ~Ng793; - assign n3075 = ~Ng797; - assign n3066_1 = ~Ng801; - assign n3057_1 = ~Ng805; - assign n3048_1 = ~Ng809; - assign n3039_1 = ~Ng813; - assign n2117_1 = ~Ng291; - assign n2107_1 = ~Ng289; - assign n2102_1 = ~Ng287; - assign n2097_1 = ~Ng285; - assign n2092_1 = ~Ng283; - assign n2087_1 = ~Ng281; - assign n2082 = ~Ng279; - assign n2077_1 = ~Ng453; - assign n2072_1 = ~Ng451; - assign n1596 = ~Ng97; - assign n1587 = ~Ng101; - assign n1578 = ~Ng105; - assign n1569_1 = ~Ng109; - assign n1560_1 = ~Ng113; - assign n1551_1 = ~Ng117; - assign n1542_1 = ~Ng121; - assign n1533_1 = ~Ng125; - assign n5817 = n5833_1 & n5838_1 & (~\[1605] | Ng2809); - assign n5818 = ~n5836 & (n5576 | n5817); - assign n5819_1 = n5840 & n5845 & (~\[1605] | Ng2115); - assign n5820 = n5574 | ~Ng8302; - assign n5821 = ~n5843_1 & (n5819_1 | n5820); - assign n5822 = ~n5955 & n5960 & (~\[1605] | Ng1421); - assign n5823_1 = n5549 | ~Ng8293; - assign n5824 = ~n5958_1 & (n5822 | n5823_1); - assign n5825 = ~n5981 & n6018_1 & (~\[1605] | Ng735); - assign n5826 = n5523 | ~Ng8284; - assign n5827 = ~n6016 & (n5825 | n5826); - assign n5828_1 = ~n5925 & (~n5923_1 | ~n5947); - assign n5829 = ~n5905 & (~n5903_1 | ~n5940); - assign n5830 = ~n5885 & (~n5883_1 | ~n5933_1); - assign n5831 = ~n5865 & (~n5863_1 | ~n5926); - assign n5832 = n4952 | n4930 | n4882 | n4812 | n4778_1 | n4848; - assign n5833_1 = ~n4928_1 | ~n4776 | ~n4910_1 | ~n8457 | ~n4942 | n5832; - assign n5834 = (~Ng2631 | n8556) & n8557; - assign n5835 = n5655_1 ^ ~n5660_1; - assign n5836 = n5071 | ~n5072_1; - assign n5837 = ~n5591 | n5836; - assign n5838_1 = (~Ng1315 | Ng2808) & (~\[1603] | Ng2810); - assign n5839 = n4944 | n4900 | n4840 | n4770 | n4742_1 | n4806; - assign n5840 = ~n4898 | ~n4740 | ~n4872 | ~n8467 | ~n4922 | n5839; - assign n5841 = (~Ng1937 | n8559) & n8560; - assign n5842 = n5643 ^ ~n5648; - assign n5843_1 = n5069 | ~n5070; - assign n5844 = ~n5574 | n5843_1; - assign n5845 = (~Ng1315 | Ng2114) & (~\[1603] | Ng2116); - assign n5846 = (n6297 | ~n6298) & (n6299_1 | n6300); - assign n5847 = n4846_1 ^ ~Ng2190; - assign n5848_1 = ~n5849 & (~n8481 | (n5846 & n5847)); - assign n5849 = n4946 | ~Ng2257; - assign n5850 = n6300 | n6482 | ~n6298 | n6299_1 | n5847 | n5853_1 | n6296 | n6297; - assign n5851 = ~n6485_1 & (n5849 | n5850); - assign n5852 = (n6293 | n6294_1) & (n6295 | n6296); - assign n5853_1 = ~n4746 ^ ~n5046; - assign n5854 = ~n5849 & (~n8478 | (n5852 & n5853_1)); - assign n5855 = n6301 & ~n6308_1 & ~n6488; - assign n5856 = n5855 & (n4846_1 | ~n5926); - assign n5857 = n4720_1 ^ ~n5926; - assign n5858_1 = (n4876_1 & n5926) | (~n4846_1 & (~n4876_1 | n5926)); - assign n5859 = ~n5989 & ~n6483; - assign n5860 = ~n4970 & n4980; - assign n5861 = n5860 & n4976 & n5859; - assign n5862 = ~n4643 & (n5861 | (~n5989 & ~n5990)); - assign n5863_1 = n5445_1 & ~n5862 & (n4970 | ~n6485_1); - assign n5864 = n6219_1 & n5926; - assign n5865 = n5863_1 & (n5864 | ~n6626); - assign n5866 = (n6321_1 | ~n6322) & (n6323 | n6324); - assign n5867 = n4804 ^ ~Ng1496; - assign n5868_1 = ~n5869 & (~n8487 | (n5866 & n5867)); - assign n5869 = n4934 | ~Ng2257; - assign n5870 = n6324 | n6492 | ~n6322 | n6323 | n5867 | n5873_1 | n6320 | n6321_1; - assign n5871 = ~n6495_1 & (n5869 | n5870); - assign n5872 = (n6317_1 | n6318) & (n6319 | n6320); - assign n5873_1 = ~n4716_1 ^ ~n5042; - assign n5874 = ~n5869 & (~n8484 | (n5872 & n5873_1)); - assign n5875 = n6325 & ~n6332 & ~n6498; - assign n5876 = n5875 & (n4804 | ~n5933_1); - assign n5877 = n4696_1 ^ ~n5933_1; - assign n5878_1 = (n4834_1 & n5933_1) | (~n4804 & (~n4834_1 | n5933_1)); - assign n5879 = ~n5997 & ~n6493; - assign n5880 = ~n4962 & n4974; - assign n5881 = n5880 & n4968_1 & n5879; - assign n5882 = ~n4639 & (n5881 | (~n5997 & ~n5998_1)); - assign n5883_1 = n5442 & ~n5882 & (n4962 | ~n6495_1); - assign n5884 = n6223_1 & n5933_1; - assign n5885 = n5883_1 & (n5884 | ~n6664); - assign n5886 = (n6345_1 | ~n6346) & (n6347 | n6348); - assign n5887 = n4762 ^ ~Ng805; - assign n5888_1 = ~n5889 & (~n8493 | (n5886 & n5887)); - assign n5889 = n4914 | ~Ng2257; - assign n5890 = n6348 | n6502 | ~n6346 | n6347 | n5887 | n5893_1 | n6344 | n6345_1; - assign n5891 = ~n6505_1 & (n5889 | n5890); - assign n5892 = (n6341_1 | n6342) & (n6343 | n6344); - assign n5893_1 = ~n4692_1 ^ ~n5038_1; - assign n5894 = ~n5889 & (~n8490 | (n5892 & n5893_1)); - assign n5895 = n6349_1 & ~n6356 & ~n6508; - assign n5896 = n5895 & (n4762 | ~n5940); - assign n5897 = n4676_1 ^ ~n5940; - assign n5898_1 = (n4792_1 & n5940) | (~n4762 & (~n4792_1 | n5940)); - assign n5899 = ~n6005 & ~n6503; - assign n5900 = ~n4956 & n4966; - assign n5901 = n5900 & n4960 & n5899; - assign n5902 = ~n4633 & (n5901 | (~n6005 & ~n6006)); - assign n5903_1 = n5439 & ~n5902 & (n4956 | ~n6505_1); - assign n5904 = n6227_1 & n5940; - assign n5905 = n5903_1 & (n5904 | ~n6702_1); - assign n5906 = (n6369 | ~n6370) & (n6371 | n6372); - assign n5907 = n4726 ^ ~Ng117; - assign n5908_1 = ~n5909 & (~n8499 | (n5906 & n5907)); - assign n5909 = n4884_1 | ~Ng2257; - assign n5910 = n6372 | n6512 | ~n6370 | n6371 | n5907 | n5913_1 | n6368_1 | n6369; - assign n5911 = ~n6515_1 & (n5909 | n5910); - assign n5912 = (n6365 | n6366) & (n6367 | n6368_1); - assign n5913_1 = ~n4672_1 ^ ~n5030; - assign n5914 = ~n5909 & (~n8496 | (n5912 & n5913_1)); - assign n5915 = n6373_1 & ~n6380 & ~n6518; - assign n5916 = n5915 & (n4726 | ~n5947); - assign n5917 = n4662 ^ ~n5947; - assign n5918_1 = (n4750 & n5947) | (~n4726 & (~n4750 | n5947)); - assign n5919 = ~n6013_1 & ~n6513; - assign n5920 = ~n4950 & n4958_1; - assign n5921 = n5920 & n4954 & n5919; - assign n5922 = ~n4625 & (n5921 | (~n6013_1 & ~n6014)); - assign n5923_1 = n5436 & ~n5922 & (n4950 | ~n6515_1); - assign n5924 = n6231_1 & n5947; - assign n5925 = n5923_1 & (n5924 | ~n6740); - assign n5926 = ~n4970 | n4976 | ~n4980; - assign n5927 = n5856 & (~n4846_1 | n5926); - assign n5928_1 = n5927 & n5857; - assign n5929 = Ng2200 & ~n5863_1; - assign n5930 = Ng2195 & ~n5863_1; - assign n5931 = Ng2185 & ~n5863_1; - assign n5932 = Ng2165 & ~n5863_1; - assign n5933_1 = ~n4962 | n4968_1 | ~n4974; - assign n5934 = n5876 & (~n4804 | n5933_1); - assign n5935 = n5934 & n5877; - assign n5936 = Ng1506 & ~n5883_1; - assign n5937 = Ng1501 & ~n5883_1; - assign n5938_1 = Ng1491 & ~n5883_1; - assign n5939 = Ng1471 & ~n5883_1; - assign n5940 = ~n4956 | n4960 | ~n4966; - assign n5941 = n5896 & (~n4762 | n5940); - assign n5942 = n5941 & n5897; - assign n5943_1 = Ng813 & ~n5903_1; - assign n5944 = Ng809 & ~n5903_1; - assign n5945 = Ng801 & ~n5903_1; - assign n5946 = Ng785 & ~n5903_1; - assign n5947 = ~n4950 | n4954 | ~n4958_1; - assign n5948_1 = n5916 & (~n4726 | n5947); - assign n5949 = n5948_1 & n5917; - assign n5950 = Ng125 & ~n5923_1; - assign n5951 = Ng121 & ~n5923_1; - assign n5952 = Ng113 & ~n5923_1; - assign n5953_1 = Ng97 & ~n5923_1; - assign n5954 = n4916 & (~n8500 | (\[1603] & ~Ng1425)); - assign n5955 = n5954 & n4892_1 & n4860 & n4710 & n4830 & ~n8501; - assign n5956 = (~Ng1243 | n8612) & n8613; - assign n5957 = n5631 ^ ~n5636; - assign n5958_1 = n5067_1 | ~n5068; - assign n5959 = ~n5549 | n5958_1; - assign n5960 = (~Ng1315 | Ng1420) & (~\[1603] | Ng1422); - assign n5961 = n5926 & (n4970 | ~n5990 | ~n6483); - assign n5962 = n6021 & Ng2133 & Ng2129; - assign n5963_1 = n5962 & Ng2124; - assign n5964 = n5933_1 & (n4962 | ~n5998_1 | ~n6493); - assign n5965 = n6025 & Ng1439 & Ng1435; - assign n5966 = n5965 & Ng1430; - assign n5967 = n5940 & (n4956 | ~n6006 | ~n6503); - assign n5968_1 = n6029 & Ng753 & Ng749; - assign n5969 = n5968_1 & Ng744; - assign n5970 = n5947 & (n4950 | ~n6014 | ~n6513); - assign n5971 = n6033_1 & Ng65 & Ng61; - assign n5972 = n5971 & Ng56; - assign n5973_1 = n6522 | n5975; - assign n5974 = ~Ng3135 | n6524; - assign n5975 = ~Ng3147 | n6131; - assign n5976 = n5973_1 & (n5974 | n5975); - assign n5977 = n6531 & (Ng3120 | ~Ng3135 | ~n6977); - assign n5978_1 = n5974 | Ng3147 | n6131; - assign n5979 = \[1605] & ~Ng8284; - assign n5980 = n4886 & (~n8510 | (\[1603] & ~Ng739)); - assign n5981 = n5980 & n4854 & n4818 & n4686 & n4788 & ~n8511; - assign n5982 = (~Ng557 | n8619) & n8620; - assign n5983_1 = n5619 ^ ~n5624; - assign n5984 = ~n5034 | ~n5671 | ~Ng2257 | ~n6485_1; - assign n5985 = n5034 & (n5060 | ~n5671); - assign n5986 = ~n5034 & (n5060 | n5671); - assign n5987 = n5026 | ~Ng2257; - assign n5988_1 = n5984 & (n5985 | n5986 | n5987); - assign n5989 = n5849 | n6291 | n6292 | n6479 | n6480_1 | n6481; - assign n5990 = n4970 | ~n4976 | n4980; - assign n5991 = (~n5859 | ~n5860) & (n5989 | n5990); - assign n5992 = ~n5022 | ~n5668 | ~Ng2257 | ~n6495_1; - assign n5993_1 = n5022 & (n5056 | ~n5668); - assign n5994 = ~n5022 & (n5056 | n5668); - assign n5995 = n5014 | ~Ng2257; - assign n5996 = n5992 & (n5993_1 | n5994 | n5995); - assign n5997 = n5869 | n6315 | n6316 | n6489 | n6490_1 | n6491; - assign n5998_1 = n4962 | ~n4968_1 | n4974; - assign n5999 = (~n5879 | ~n5880) & (n5997 | n5998_1); - assign n6000 = ~n5010 | ~n5665_1 | ~Ng2257 | ~n6505_1; - assign n6001 = n5010 & (n5052 | ~n5665_1); - assign n6002 = ~n5010 & (n5052 | n5665_1); - assign n6003_1 = n5002 | ~Ng2257; - assign n6004 = n6000 & (n6001 | n6002 | n6003_1); - assign n6005 = n5889 | n6339 | n6340 | n6499 | n6500_1 | n6501; - assign n6006 = n4956 | ~n4960 | n4966; - assign n6007 = (~n5899 | ~n5900) & (n6005 | n6006); - assign n6008_1 = ~n4998_1 | ~n5662 | ~Ng2257 | ~n6515_1; - assign n6009 = n4998_1 & (n5050 | ~n5662); - assign n6010 = ~n4998_1 & (n5050 | n5662); - assign n6011 = n4990 | ~Ng2257; - assign n6012 = n6008_1 & (n6009 | n6010 | n6011); - assign n6013_1 = n5909 | n6363_1 | n6364 | n6509 | n6510_1 | n6511; - assign n6014 = n4950 | ~n4954 | n4958_1; - assign n6015 = (~n5919 | ~n5920) & (n6013_1 | n6014); - assign n6016 = n5065 | ~n5066; - assign n6017 = ~n5523 | n6016; - assign n6018_1 = (~Ng1315 | Ng734) & (~\[1603] | Ng736); - assign n6019 = n5034 | ~n5060 | n5671; - assign n6020 = ~n5987 & (~n5060 | n5670_1) & n6019; - assign n6021 = n6154 & Ng2142 & Ng2138; - assign n6022 = n6021 & Ng2133; - assign n6023_1 = n5022 | ~n5056 | n5668; - assign n6024 = ~n5995 & (~n5056 | n5667) & n6023_1; - assign n6025 = n6161 & Ng1448 & Ng1444; - assign n6026 = n6025 & Ng1439; - assign n6027 = n5010 | ~n5052 | n5665_1; - assign n6028_1 = ~n6003_1 & (~n5052 | n5664) & n6027; - assign n6029 = n6168 & Ng762 & Ng758; - assign n6030 = n6029 & Ng753; - assign n6031 = n4998_1 | ~n5050 | n5662; - assign n6032 = ~n6011 & (~n5050 | n5661) & n6031; - assign n6033_1 = n6175_1 & Ng74 & Ng70; - assign n6034 = n6033_1 & Ng65; - assign n6035 = ~n858_1 & n5976; - assign n6036 = (~Ng3105 | n6549) & (n5978_1 | Ng3128); - assign n6037 = (~Ng3103 | n6547) & (~Ng3104 | n6548); - assign n6038_1 = (n6545_1 | ~Ng3101) & (n6546 | ~Ng3102); - assign n6039 = (n6542 | ~Ng3099) & (n6543 | ~Ng3100); - assign n6040 = (n6540_1 | ~Ng3097) & (n6541 | ~Ng3098); - assign n6041 = (~Ng3107 | n6536) & (~Ng3108 | n6538); - assign n6042 = (~Ng3106 | n6535_1) & (n6531 | ~n8756); - assign n6043_1 = Ng2753 & n6550_1; - assign n6044 = Ng2760 & n6043_1; - assign n6045 = (~n4573_1 | ~n5028_1) & (n4567 | ~n5008_1); - assign n6046 = n5008_1 & (~n8522 | (n4571 & ~n5028_1)); - assign n6047 = n4573_1 & (~n8521 | (n4567 & ~n5018_1)); - assign n6048_1 = n5028_1 & n5018_1; - assign n6049 = ~n5008_1 & (n6047 | (n4561 & n6048_1)); - assign n6050 = ~n4573_1 & (n6046 | (~n5036 & ~n6057_1)); - assign n6051 = ~n5028_1 | n4561 | n4571; - assign n6052 = n6051 & (~n4567 | (n4571 & ~n5028_1)); - assign n6053_1 = n5028_1 & (n4573_1 | ~n5036); - assign n6054 = n4567 & (~n5036 | (~n4571 & n6048_1)); - assign n6055 = ~n6054 & (n4561 | n5008_1 | n5036); - assign n6056 = (~n5018_1 & (n4573_1 | n5028_1)) | (~n4573_1 & n5028_1); - assign n6057_1 = n4567 | n4571; - assign n6058 = (~n4561 | n6053_1) & (n6056 | n6057_1); - assign n6059 = n4573_1 | n5018_1 | n6052; - assign n6060 = (~n5008_1 & ~n7061_1) | (n6058 & (n5008_1 | ~n7061_1)); - assign n6061 = n6059 & (~n4573_1 | n6055) & n6060; - assign n6062_1 = n6395 | ~Ng185 | ~Ng2616; - assign n6063 = (~\[1603] | ~Ng2673) & (~\[1605] | ~Ng2670); - assign n6064 = n6062_1 & n6063 & (~Ng1315 | ~Ng2676); - assign n6065 = Ng2059 & n6556; - assign n6066_1 = Ng2066 & n6065; - assign n6067 = (~n4569 | ~n5016) & (n4559_1 | ~n4996); - assign n6068 = n4996 & (~n8525 | (n4565 & ~n5016)); - assign n6069 = n4569 & (~n8524 | (n4559_1 & ~n5006)); - assign n6070 = n5016 & n5006; - assign n6071_1 = ~n4996 & (n6069 | (n4553 & n6070)); - assign n6072 = ~n4569 & (n6068 | (~n5024 & ~n6079)); - assign n6073 = ~n5016 | n4553 | n4565; - assign n6074 = n6073 & (~n4559_1 | (n4565 & ~n5016)); - assign n6075_1 = n5016 & (n4569 | ~n5024); - assign n6076 = n4559_1 & (~n5024 | (~n4565 & n6070)); - assign n6077 = ~n6076 & (n4553 | n4996 | n5024); - assign n6078 = (~n5006 & (n4569 | n5016)) | (~n4569 & n5016); - assign n6079 = n4559_1 | n4565; - assign n6080_1 = (~n4553 | n6075_1) & (n6078 | n6079); - assign n6081 = n4569 | n5006 | n6074; - assign n6082 = (~n4996 & ~n7077) | (n6080_1 & (n4996 | ~n7077)); - assign n6083 = n6081 & (~n4569 | n6077) & n6082; - assign n6084_1 = n4888 | ~Ng185 | ~Ng1922; - assign n6085 = (~\[1603] | ~Ng1979) & (~\[1605] | ~Ng1976); - assign n6086 = n6084_1 & n6085 & (~Ng1315 | ~Ng1982); - assign n6087 = Ng1365 & n6560_1; - assign n6088 = Ng1372 & n6087; - assign n6089_1 = (~n4563 | ~n5004) & (n4551 | ~n4988_1); - assign n6090 = n4988_1 & (~n8528 | (n4557 & ~n5004)); - assign n6091 = n4563 & (~n8527 | (n4551 & ~n4994)); - assign n6092 = n5004 & n4994; - assign n6093_1 = ~n4988_1 & (n6091 | (n4547 & n6092)); - assign n6094 = ~n4563 & (n6090 | (~n5012 & ~n6101)); - assign n6095 = ~n5004 | n4547 | n4557; - assign n6096 = n6095 & (~n4551 | (n4557 & ~n5004)); - assign n6097 = n5004 & (n4563 | ~n5012); - assign n6098_1 = n4551 & (~n5012 | (~n4557 & n6092)); - assign n6099 = ~n6098_1 & (n4547 | n4988_1 | n5012); - assign n6100 = (~n4994 & (n4563 | n5004)) | (~n4563 & n5004); - assign n6101 = n4551 | n4557; - assign n6102_1 = (~n4547 | n6097) & (n6100 | n6101); - assign n6103 = n4563 | n4994 | n6096; - assign n6104 = (~n4988_1 & ~n7093) | (n6102_1 & (n4988_1 | ~n7093)); - assign n6105 = n6103 & (~n4563 | n6099) & n6104; - assign n6106 = n3381_1 | ~Ng185 | ~Ng1228; - assign n6107_1 = (~\[1603] | ~Ng1285) & (~\[1605] | ~Ng1282); - assign n6108 = n6106 & n6107_1 & (~Ng1315 | ~Ng1288); - assign n6109 = Ng679 & n6564; - assign n6110 = Ng686 & n6109; - assign n6111_1 = (~n4555_1 | ~n4992) & (n4545 | ~n4984); - assign n6112 = n4984 & (~n8531 | (n4549 & ~n4992)); - assign n6113 = n4555_1 & (~n8530 | (n4545 & ~n4986)); - assign n6114 = n4992 & n4986; - assign n6115 = ~n4984 & (n6113 | (n4543 & n6114)); - assign n6116_1 = ~n4555_1 & (n6112 | (~n5000 & ~n6123)); - assign n6117 = ~n4992 | n4543 | n4549; - assign n6118 = n6117 & (~n4545 | (n4549 & ~n4992)); - assign n6119 = n4992 & (n4555_1 | ~n5000); - assign n6120_1 = n4545 & (~n5000 | (~n4549 & n6114)); - assign n6121 = ~n6120_1 & (n4543 | n4984 | n5000); - assign n6122 = (~n4986 & (n4555_1 | n4992)) | (~n4555_1 & n4992); - assign n6123 = n4545 | n4549; - assign n6124_1 = (~n4543 | n6119) & (n6122 | n6123); - assign n6125 = n4555_1 | n4986 | n6118; - assign n6126 = (~n4984 & ~n7109) | (n6124_1 & (n4984 | ~n7109)); - assign n6127 = n6125 & (~n4555_1 | n6121) & n6126; - assign n6128_1 = n1875_1 | ~Ng185 | ~Ng542; - assign n6129 = (~\[1603] | ~Ng599) & (~\[1605] | ~Ng596); - assign n6130 = n6128_1 & n6129 & (~Ng1315 | ~Ng602); - assign n6131 = Ng3126 | Ng3191 | Ng3126 | Ng3110; - assign n6132 = n5973_1 & n5978_1; - assign n6133_1 = (n6542 | ~Ng3161) & (n6540_1 | ~Ng3155); - assign n6134 = (n6543 | ~Ng3164) & (n6541 | ~Ng3158); - assign n6135 = (n6545_1 | ~Ng3167) & (n6546 | ~Ng3170); - assign n6136 = (n6548 | ~Ng3176) & (n6549 | ~Ng3179); - assign n6137 = n6547 | ~Ng3173; - assign n6138_1 = (n6536 | ~Ng3185) & (n6535_1 | ~Ng3182); - assign n6139 = (n6132 | ~Ng3135) & (n6538 | ~Ng3088); - assign n6140 = n6139 & n6138_1 & n6137 & n6136 & n6135 & ~n858_1 & n6133_1 & n6134; - assign n6141 = (n6536 | ~Ng3095) & (n6538 | ~Ng3096); - assign n6142 = (n6549 | ~Ng3093) & (n6535_1 | ~Ng3094); - assign n6143_1 = (n6547 | ~Ng3091) & (n6548 | ~Ng3092); - assign n6144 = (n6545_1 | ~Ng3086) & (n6546 | ~Ng3087); - assign n6145 = (n6542 | ~Ng3084) & (n6543 | ~Ng3085); - assign n6146 = (n6540_1 | ~Ng3210) & (n6541 | ~Ng3211); - assign n6147_1 = n8532 & (~Ng3120 | (n5976 & n5978_1)); - assign n6148 = n6147_1 & n6146 & n6145 & n6144 & n6143_1 & ~n858_1 & n6141 & n6142; - assign n6149 = Ng2175 & Ng2190 & Ng2185 & Ng2195 & Ng2200 & Ng2180 & Ng2165 & Ng2170; - assign n6150 = n6149 & (~n8533 | (\[1594] & ~Ng2255)); - assign n6151_1 = n4880_1 & (~n4908 | ~n6150); - assign n6152 = ~n4880_1 & (n4908 | n6150); - assign n6153 = ~Ng2257 | n6151_1 | n6152; - assign n6154 = n6203_1 & Ng2151 & Ng2147; - assign n6155_1 = n6154 & Ng2142; - assign n6156 = Ng1481 & Ng1496 & Ng1491 & Ng1501 & Ng1506 & Ng1486 & Ng1471 & Ng1476; - assign n6157 = n6156 & (~n8534 | (\[1594] & ~Ng1561)); - assign n6158 = n4838_1 & (~n4870 | ~n6157); - assign n6159_1 = ~n4838_1 & (n4870 | n6157); - assign n6160 = ~Ng2257 | n6158 | n6159_1; - assign n6161 = n6207_1 & Ng1457 & Ng1453; - assign n6162 = n6161 & Ng1448; - assign n6163_1 = Ng793 & Ng805 & Ng801 & Ng809 & Ng813 & Ng797 & Ng785 & Ng789; - assign n6164 = n6163_1 & (~n8535 | (\[1594] & ~Ng867)); - assign n6165 = n4796_1 & (~n4828 | ~n6164); - assign n6166 = ~n4796_1 & (n4828 | n6164); - assign n6167_1 = ~Ng2257 | n6165 | n6166; - assign n6168 = n6211_1 & Ng771 & Ng767; - assign n6169 = n6168 & Ng762; - assign n6170 = Ng105 & Ng117 & Ng113 & Ng121 & Ng125 & Ng109 & Ng97 & Ng101; - assign n6171_1 = n6170 & (~n8536 | (\[1594] & ~Ng179)); - assign n6172 = n4754 & (~n4786 | ~n6171_1); - assign n6173 = ~n4754 & (n4786 | n6171_1); - assign n6174 = ~Ng2257 | n6172 | n6173; - assign n6175_1 = n6215_1 & Ng83 & Ng79; - assign n6176 = n6175_1 & Ng74; - assign n6177 = ~n4581 | n4982 | ~Ng2584; - assign n6178 = ~n5028_1 | Pg3229 | n5018_1; - assign n6179_1 = n6178 & (~Pg3229 | n5036) & ~n8670; - assign n6180 = ~n4926 | Pg3229 | n4906; - assign n6181 = n6180 & (~Pg3229 | n4940) & ~n8675; - assign n6182 = ~n4579 | n4978_1 | ~Ng1890; - assign n6183_1 = ~n5016 | Pg3229 | n5006; - assign n6184 = n6183_1 & (~Pg3229 | n5024) & ~n8681; - assign n6185 = ~n4896 | Pg3229 | n4868; - assign n6186 = n6185 & (~Pg3229 | n4920) & ~n8686; - assign n6187_1 = ~n4577_1 | n4972 | ~Ng1196; - assign n6188 = ~n5004 | Pg3229 | n4994; - assign n6189 = n6188 & (~Pg3229 | n5012) & ~n8692; - assign n6190 = ~n4858 | Pg3229 | n4826; - assign n6191_1 = n6190 & (~Pg3229 | n4890) & ~n8697; - assign n6192 = ~n4575 | n4964 | ~Ng510; - assign n6193 = ~n4992 | Pg3229 | n4986; - assign n6194 = n6193 & (~Pg3229 | n5000) & ~n8703; - assign n6195_1 = ~n4816 | Pg3229 | n4784; - assign n6196 = n6195_1 & (~Pg3229 | n4852) & ~n8708; - assign n6197 = ~Ng3013 | n6573; - assign n6198 = n6197 | ~Ng3010; - assign n6199_1 = Ng2903 & n6574_1; - assign n6200 = Ng2900 & n6199_1; - assign n6201 = n6240 & Ng2734 & Ng2720; - assign n6202 = n6201 & Ng2746; - assign n6203_1 = ~n6242 & Ng2160 & Ng2156; - assign n6204 = n6203_1 & Ng2151; - assign n6205 = n6244_1 & Ng2040 & Ng2026; - assign n6206 = n6205 & Ng2052; - assign n6207_1 = ~n6242 & Ng1466 & Ng1462; - assign n6208 = n6207_1 & Ng1457; - assign n6209 = n6247 & Ng1346 & Ng1332; - assign n6210 = n6209 & Ng1358; - assign n6211_1 = ~n6242 & Ng780 & Ng776; - assign n6212 = n6211_1 & Ng771; - assign n6213 = n6250 & Ng660 & Ng646; - assign n6214 = n6213 & Ng672; - assign n6215_1 = ~n6242 & Ng92 & Ng88; - assign n6216 = n6215_1 & Ng83; - assign n6217 = n6395_1 | ~n5127 | ~n5137 | n6396 | n6397 | n6398; - assign n6218 = n6404 | n6402 | n6403_1 | n6399_1 | n6400 | n6401; - assign n6219_1 = ~n4980 | ~n4970 | ~n4976; - assign n6143 = (n6217 | n6218) & (n6219_1 | ~n6487); - assign n6221 = n6405 | ~n5127 | ~n5135_1 | n6406 | n6407 | n6408_1; - assign n6222 = n6414 | n6412_1 | n6413 | n6409 | n6410 | n6411; - assign n6223_1 = ~n4974 | ~n4962 | ~n4968_1; - assign n4636 = (n6221 | n6222) & (n6223_1 | ~n6497); - assign n6225 = n6415 | ~n5127 | ~n5131 | n6416 | n6417_1 | n6418; - assign n6226 = n6424 | n6422_1 | n6423 | n6419 | n6420 | n6421; - assign n6227_1 = ~n4966 | ~n4956 | ~n4960; - assign n3129_1 = (n6225 | n6226) & (n6227_1 | ~n6507); - assign n6229 = n6425 | ~n5126 | ~n5127 | n6426_1 | n6427 | n6428; - assign n6230 = n6434 | n6432 | n6433 | n6429 | n6430 | n6431_1; - assign n6231_1 = ~n4958_1 | ~n4950 | ~n4954; - assign n1623_1 = (n6229 | n6230) & (n6231_1 | ~n6517); - assign n6233 = ~Ng3028 & ~Ng3036 & Ng3032 & Ng3018; - assign n6234 = n6256 | Pg3234; - assign n6235_1 = n6256 & Ng3028 & Ng3018; - assign n6236 = n6235_1 & Ng3036; - assign n6237 = ~Ng2917 & ~Ng2924 & Ng2912 & Ng2920; - assign n6238 = n6258 & Ng2912 & Ng2917; - assign n6239_1 = n6238 & Ng2924; - assign n6240 = n6260 & Ng2727 & Ng2707; - assign n6241 = n6240 & Ng2720; - assign n6242 = ~Ng853 | ~n5127; - assign n6243 = n6242 | ~Ng2160; - assign n6244_1 = n6262 & Ng2033 & Ng2013; - assign n6245 = n6244_1 & Ng2026; - assign n6246 = n6242 | ~Ng1466; - assign n6247 = n6264 & Ng1339 & Ng1319; - assign n6248 = n6247 & Ng1332; - assign n6249_1 = n6242 | ~Ng780; - assign n6250 = n6266 & Ng653 & Ng633; - assign n6251 = n6250 & Ng646; - assign n6252 = n6242 | ~Ng92; - assign n6253 = ~n6572 | ~Ng3006; - assign n6254_1 = Ng2883 & Ng13457 & Ng2888; - assign n6255 = n6254_1 & Ng2896; - assign n6256 = n6551 & Ng13475; - assign n6257 = n6256 & Ng3018; - assign n6258 = Ng2888 & Ng2908 & Ng2903 & Ng2892 & ~Ng2883 & Ng13457 & ~Ng2900 & ~Ng2896; - assign n6259_1 = n6258 & Ng2912; - assign n6260 = Ng1315 & ~Ng2733 & Ng2714; - assign n6261 = n6260 & Ng2707; - assign n6262 = Ng1315 & ~Ng2039 & Ng2020; - assign n6263_1 = n6262 & Ng2013; - assign n6264 = Ng1315 & ~Ng1345 & Ng1326; - assign n6265 = n6264 & Ng1319; - assign n6266 = Ng1315 & ~Ng659 & Ng640; - assign n6267_1 = n6266 & Ng633; - assign n6268 = Ng2883 & Ng13457; - assign n6269 = ~Ng1315 | Ng2733; - assign n6270 = ~Ng1315 | n6271; - assign n6271 = Ng1315 & n6555_1; - assign n6272_1 = ~Ng1315 | Ng2039; - assign n6273 = ~Ng1315 | Ng1345; - assign n6274 = ~Ng1315 | Ng659; - assign n6275 = ~Ng1315 | n6276_1; - assign n6276_1 = n8750 & Ng1315; - assign n6277 = ~n5848_1 & n5851 & (n4643 | ~n5859); - assign n6278 = ~n5868_1 & n5871 & (n4639 | ~n5879); - assign n6279 = ~n5888_1 & n5891 & (n4633 | ~n5899); - assign n6280 = ~n5908_1 & n5911 & (n4625 | ~n5919); - assign n6281_1 = ~Ng185 | ~Ng3139; - assign n6282 = n6281_1 & ~n6523 & (Ng3139 | ~n8756); - assign n6283 = ~Pg3234 & (n6234 | ~n6394); - assign n7111 = ~n6283; - assign n6285_1 = n4744 ^ ~Ng2195; - assign n6286 = n4874 ^ ~Ng2170; - assign n6287 = n4680_1 ^ ~Ng2180; - assign n6288 = n4668_1 ^ ~Ng2175; - assign n6289 = n4772 ^ ~Ng2200; - assign n6290_1 = n4718 ^ ~Ng2190; - assign n6291 = n4698 ^ ~Ng2185; - assign n6292 = n4842_1 ^ ~Ng2165; - assign n6293 = n4924_1 ^ ~Ng2175; - assign n6294_1 = n4902 ^ ~Ng2165; - assign n6295 = n4720_1 ^ ~Ng2195; - assign n6296 = n4938_1 ^ ~Ng2185; - assign n6297 = n4810_1 ^ ~Ng2180; - assign n6298 = n4904 ^ ~n5044; - assign n6299_1 = n4876_1 ^ ~Ng2200; - assign n6300 = n4774_1 ^ ~Ng2170; - assign n6301 = n4938_1 ^ ~n5926; - assign n6302 = ~n4902 ^ ~n5926; - assign n6303_1 = ~n4774_1 ^ ~n5926; - assign n6304 = ~n4924_1 ^ ~n5926; - assign n6305 = ~n4810_1 ^ ~n5926; - assign n6306 = n6304 | n6308_1; - assign n6307 = n5864 | n6302; - assign n6308_1 = n6303_1 | n6307; - assign n6309 = n4658 ^ ~Ng1481; - assign n6310 = n4666 ^ ~Ng1486; - assign n6311 = n4800 ^ ~Ng1471; - assign n6312_1 = n4678 ^ ~Ng1491; - assign n6313 = n4832 ^ ~Ng1476; - assign n6314 = n4694 ^ ~Ng1496; - assign n6315 = n4736 ^ ~Ng1506; - assign n6316 = n4714 ^ ~Ng1501; - assign n6317_1 = n4894 ^ ~Ng1481; - assign n6318 = n4864 ^ ~Ng1471; - assign n6319 = n4696_1 ^ ~Ng1501; - assign n6320 = n4918 ^ ~Ng1491; - assign n6321_1 = n4768 ^ ~Ng1486; - assign n6322 = n4866_1 ^ ~n5040; - assign n6323 = n4834_1 ^ ~Ng1506; - assign n6324 = n4738 ^ ~Ng1476; - assign n6325 = n4918 ^ ~n5933_1; - assign n6326_1 = ~n4864 ^ ~n5933_1; - assign n6327 = ~n4738 ^ ~n5933_1; - assign n6328 = ~n4894 ^ ~n5933_1; - assign n6329 = ~n4768 ^ ~n5933_1; - assign n6330 = n6328 | n6332; - assign n6331_1 = n5884 | n6326_1; - assign n6332 = n6327 | n6331_1; - assign n6333 = n4651 ^ ~Ng793; - assign n6334 = n4790 ^ ~Ng789; - assign n6335 = n4706 ^ ~Ng813; - assign n6336_1 = n4656_1 ^ ~Ng797; - assign n6337 = n4690 ^ ~Ng809; - assign n6338 = n4674 ^ ~Ng805; - assign n6339 = n4664_1 ^ ~Ng801; - assign n6340 = n4758 ^ ~Ng785; - assign n6341_1 = n4856_1 ^ ~Ng793; - assign n6342 = n4822 ^ ~Ng785; - assign n6343 = n4676_1 ^ ~Ng809; - assign n6344 = n4888_1 ^ ~Ng801; - assign n6345_1 = n4732_1 ^ ~Ng797; - assign n6346 = n4824_1 ^ ~n5032; - assign n6347 = n4792_1 ^ ~Ng813; - assign n6348 = n4708_1 ^ ~Ng789; - assign n6349_1 = n4888_1 ^ ~n5940; - assign n6350 = ~n4822 ^ ~n5940; - assign n6351 = ~n4708_1 ^ ~n5940; - assign n6352 = ~n4856_1 ^ ~n5940; - assign n6353_1 = ~n4732_1 ^ ~n5940; - assign n6354 = n6352 | n6356; - assign n6355 = n5904 | n6350; - assign n6356 = n6351 | n6355; - assign n6357 = n4647 ^ ~Ng105; - assign n6358_1 = n4748 ^ ~Ng101; - assign n6359 = n4682 ^ ~Ng125; - assign n6360 = n4649 ^ ~Ng109; - assign n6361 = n4670 ^ ~Ng121; - assign n6362 = n4660_1 ^ ~Ng117; - assign n6363_1 = n4654 ^ ~Ng113; - assign n6364 = n4722 ^ ~Ng97; - assign n6365 = n4814_1 ^ ~Ng105; - assign n6366 = n4780 ^ ~Ng97; - assign n6367 = n4662 ^ ~Ng121; - assign n6368_1 = n4850 ^ ~Ng113; - assign n6369 = n4702 ^ ~Ng109; - assign n6370 = n4782 ^ ~n5020; - assign n6371 = n4750 ^ ~Ng125; - assign n6372 = n4684_1 ^ ~Ng101; - assign n6373_1 = n4850 ^ ~n5947; - assign n6374 = ~n4780 ^ ~n5947; - assign n6375 = ~n4684_1 ^ ~n5947; - assign n6376 = ~n4814_1 ^ ~n5947; - assign n6377 = ~n4702 ^ ~n5947; - assign n6378_1 = n6376 | n6380; - assign n6379 = n5924 | n6374; - assign n6380 = n6375 | n6379; - assign n6381 = ~n4846_1 ^ ~n5855; - assign n6382 = (~Ng2190 | n5863_1) & (~n5865 | n6381); - assign n6383_1 = ~n4804 ^ ~n5875; - assign n6384 = (~Ng1496 | n5883_1) & (~n5885 | n6383_1); - assign n6385 = ~n4762 ^ ~n5895; - assign n6386 = (~Ng805 | n5903_1) & (~n5905 | n6385); - assign n6387_1 = ~n4726 ^ ~n5915; - assign n6388 = (~Ng117 | n5923_1) & (~n5925 | n6387_1); - assign n6389 = Pg3229 ^ ~n4878; - assign n6390 = Pg3229 ^ ~n4836; - assign n6391_1 = Pg3229 ^ ~n4794; - assign n6392 = Pg3229 ^ ~n4752_1; - assign n6393 = Ng13475 & Ng2993; - assign n6394 = ~n6393 ^ ~Ng2998; - assign n6395_1 = n4904 ^ ~Ng2120; - assign n6396 = n4876_1 ^ ~Ng2129; - assign n6397 = n4746 ^ ~Ng2124; - assign n6398 = n4720_1 ^ ~Ng2133; - assign n6399_1 = n4924_1 ^ ~Ng2151; - assign n6400 = n4938_1 ^ ~Ng2142; - assign n6401 = n4846_1 ^ ~Ng2138; - assign n6402 = n4902 ^ ~Ng2160; - assign n6403_1 = n4810_1 ^ ~Ng2147; - assign n6404 = n4774_1 ^ ~Ng2156; - assign n6405 = n4866_1 ^ ~Ng1426; - assign n6406 = n4834_1 ^ ~Ng1435; - assign n6407 = n4716_1 ^ ~Ng1430; - assign n6408_1 = n4696_1 ^ ~Ng1439; - assign n6409 = n4894 ^ ~Ng1457; - assign n6410 = n4918 ^ ~Ng1448; - assign n6411 = n4804 ^ ~Ng1444; - assign n6412_1 = n4864 ^ ~Ng1466; - assign n6413 = n4768 ^ ~Ng1453; - assign n6414 = n4738 ^ ~Ng1462; - assign n6415 = n4824_1 ^ ~Ng740; - assign n6416 = n4792_1 ^ ~Ng749; - assign n6417_1 = n4692_1 ^ ~Ng744; - assign n6418 = n4676_1 ^ ~Ng753; - assign n6419 = n4856_1 ^ ~Ng771; - assign n6420 = n4888_1 ^ ~Ng762; - assign n6421 = n4762 ^ ~Ng758; - assign n6422_1 = n4822 ^ ~Ng780; - assign n6423 = n4732_1 ^ ~Ng767; - assign n6424 = n4708_1 ^ ~Ng776; - assign n6425 = n4782 ^ ~Ng52; - assign n6426_1 = n4750 ^ ~Ng61; - assign n6427 = n4672_1 ^ ~Ng56; - assign n6428 = n4662 ^ ~Ng65; - assign n6429 = n4814_1 ^ ~Ng83; - assign n6430 = n4850 ^ ~Ng74; - assign n6431_1 = n4726 ^ ~Ng70; - assign n6432 = n4780 ^ ~Ng92; - assign n6433 = n4702 ^ ~Ng79; - assign n6434 = n4684_1 ^ ~Ng88; - assign n6435_1 = n4952 ^ ~Ng2760; - assign n6436 = n4942 ^ ~Ng2740; - assign n6437 = n4948_1 ^ ~Ng2753; - assign n6438 = n4778_1 ^ ~Ng2766; - assign n6439 = n4812 ^ ~Ng2707; - assign n6440_1 = n4910_1 ^ ~Ng2734; - assign n6441 = n4848 ^ ~Ng2727; - assign n6442 = n4882 ^ ~Ng2720; - assign n6443 = n4928_1 ^ ~Ng2746; - assign n6444 = n4776 ^ ~Ng2714; - assign n6445_1 = n4944 ^ ~Ng2066; - assign n6446 = n4922 ^ ~Ng2046; - assign n6447 = n4936 ^ ~Ng2059; - assign n6448 = n4742_1 ^ ~Ng2072; - assign n6449 = n4770 ^ ~Ng2013; - assign n6450_1 = n4872 ^ ~Ng2040; - assign n6451 = n4806 ^ ~Ng2033; - assign n6452 = n4840 ^ ~Ng2026; - assign n6453 = n4898 ^ ~Ng2052; - assign n6454 = n4740 ^ ~Ng2020; - assign n6455_1 = n4932 ^ ~Ng1372; - assign n6456 = n4892_1 ^ ~Ng1352; - assign n6457 = n4916 ^ ~Ng1365; - assign n6458 = n4712_1 ^ ~Ng1378; - assign n6459 = n4734 ^ ~Ng1319; - assign n6460_1 = n4830 ^ ~Ng1346; - assign n6461 = n4764 ^ ~Ng1339; - assign n6462 = n4798 ^ ~Ng1332; - assign n6463 = n4860 ^ ~Ng1358; - assign n6464 = n4710 ^ ~Ng1326; - assign n6465_1 = n4912 ^ ~Ng686; - assign n6466 = n4854 ^ ~Ng666; - assign n6467 = n4886 ^ ~Ng679; - assign n6468 = n4688_1 ^ ~Ng692; - assign n6469 = n4704_1 ^ ~Ng633; - assign n6470_1 = n4788 ^ ~Ng660; - assign n6471 = n4728_1 ^ ~Ng653; - assign n6472 = n4756_1 ^ ~Ng646; - assign n6473 = n4818 ^ ~Ng672; - assign n6474 = n4686 ^ ~Ng640; - assign n6417 = ~n6603; - assign n6476 = ~n5072_1 | n5591; - assign n4910 = ~n6602_1; - assign n6478 = ~n5070 | n5574; - assign n6479 = ~n4808 ^ ~n5046; - assign n6480_1 = ~n4844 ^ ~n5044; - assign n6481 = n6290_1 | n6288 | n6289 | n6285_1 | n6286 | n6287; - assign n6482 = n6295 | n6293 | n6294_1; - assign n6483 = n5848_1 | n5854; - assign n6484 = ~n5849 & n5850; - assign n6485_1 = Ng2257 & n4946; - assign n6486 = n4938_1 & n4720_1 & n4902 & n4846_1 & n4876_1; - assign n6487 = n4904 & n4810_1 & n6486 & n4746 & n4924_1 & n4774_1; - assign n6488 = n6304 | n6305; - assign n6489 = ~n4766 ^ ~n5042; - assign n6490_1 = ~n4802 ^ ~n5040; - assign n6491 = n6314 | n6312_1 | n6313 | n6309 | n6310 | n6311; - assign n6492 = n6319 | n6317_1 | n6318; - assign n6493 = n5868_1 | n5874; - assign n6494 = ~n5869 & n5870; - assign n6495_1 = Ng2257 & n4934; - assign n6496 = n4918 & n4696_1 & n4864 & n4804 & n4834_1; - assign n6497 = n4866_1 & n4768 & n6496 & n4716_1 & n4894 & n4738; - assign n6498 = n6328 | n6329; - assign n6499 = ~n4730 ^ ~n5038_1; - assign n6500_1 = ~n4760_1 ^ ~n5032; - assign n6501 = n6338 | n6336_1 | n6337 | n6333 | n6334 | n6335; - assign n6502 = n6343 | n6341_1 | n6342; - assign n6503 = n5888_1 | n5894; - assign n6504 = ~n5889 & n5890; - assign n6505_1 = Ng2257 & n4914; - assign n6506 = n4888_1 & n4676_1 & n4822 & n4762 & n4792_1; - assign n6507 = n4824_1 & n4732_1 & n6506 & n4692_1 & n4856_1 & n4708_1; - assign n6508 = n6352 | n6353_1; - assign n6509 = ~n4700_1 ^ ~n5030; - assign n6510_1 = ~n4724_1 ^ ~n5020; - assign n6511 = n6362 | n6360 | n6361 | n6357 | n6358_1 | n6359; - assign n6512 = n6367 | n6365 | n6366; - assign n6513 = n5908_1 | n5914; - assign n6514 = ~n5909 & n5910; - assign n6515_1 = Ng2257 & n4884_1; - assign n6516 = n4850 & n4662 & n4780 & n4726 & n4750; - assign n6517 = n4782 & n4702 & n6516 & n4672_1 & n4814_1 & n4684_1; - assign n6518 = n6376 | n6377; - assign n3403_1 = ~n6601; - assign n6520_1 = ~n5068 | n5549; - assign n6521 = ~Ng853 | ~Ng2257; - assign n6522 = Ng3139 | Ng3120; - assign n6523 = Ng3126 | Ng3191 | Ng3126 | ~Ng3110; - assign n6524 = Ng3139 | ~Ng3120; - assign n1897_1 = ~n6600; - assign n6526 = ~n5066 | n5523; - assign n6527 = ~n5060 | n5672 | n5987; - assign n6528 = ~n5056 | n5669 | n5995; - assign n6529 = ~n5052 | n5666 | n6003_1; - assign n6530_1 = ~n5050 | n5663 | n6011; - assign n6531 = n6522 | n6131 | Ng3135 | Ng3147; - assign n6532 = Ng3147 | n6523; - assign n6533 = ~Ng3139 | Ng3120; - assign n6534 = ~Ng3135 | n6532; - assign n6535_1 = n6533 | n6534; - assign n6536 = n5974 | n6532; - assign n6537 = ~Ng3139 | ~Ng3120; - assign n6538 = n6534 | n6537; - assign n6539 = Ng3135 | n6532; - assign n6540_1 = n6522 | n6539; - assign n6541 = n6533 | n6539; - assign n6542 = n6524 | n6539; - assign n6543 = n6537 | n6539; - assign n6544 = ~Ng3147 | n6523 | Ng3135; - assign n6545_1 = n6522 | n6544; - assign n6546 = n6533 | n6544; - assign n6547 = n6524 | n6544; - assign n6548 = n6537 | n6544; - assign n6549 = n6522 | n6534; - assign n6550_1 = n6201 & Ng2740 & Ng2746; - assign n6551 = ~Ng3010 & ~Ng3006 & ~Ng2993 & Ng3002 & Ng3013 & Ng2998 & Ng3024; - assign n6552 = ~n5018_1 | ~n5036; - assign n6553 = n4571 & ~n5018_1 & ~n6045; - assign n6554 = n6050 | n6553 | n6049; - assign n6555_1 = Ng3028 & n6551 & ~Ng3032 & Ng3018 & ~Ng3036; - assign n6556 = n6205 & Ng2046 & Ng2052; - assign n6557 = ~n5006 | ~n5024; - assign n6558 = n4565 & ~n5006 & ~n6067; - assign n6559 = n6072 | n6558 | n6071_1; - assign n6560_1 = n6209 & Ng1352 & Ng1358; - assign n6561 = ~n4994 | ~n5012; - assign n6562 = n4557 & ~n4994 & ~n6089_1; - assign n6563 = n6094 | n6562 | n6093_1; - assign n6564 = n6213 & Ng666 & Ng672; - assign n6565_1 = ~n4986 | ~n5000; - assign n6566 = n4549 & ~n4986 & ~n6111_1; - assign n6567 = n6116_1 | n6566 | n6115; - assign n6568 = n8661 & (n4880_1 | ~n4908 | ~n6150); - assign n6569 = n8662 & (n4838_1 | ~n4870 | ~n6157); - assign n6570_1 = n8663 & (n4796_1 | ~n4828 | ~n6164); - assign n6571 = n8664 & (n4754 | ~n4786 | ~n6171_1); - assign n6572 = Ng2998 & n6393; - assign n6573 = ~Ng3006 | ~Ng3002 | ~n6572; - assign n6574_1 = n6254_1 & Ng2892 & Ng2896; - assign n6575 = Ng2599 & ~Ng2733 & Ng2612; - assign n6576 = n5127 | Ng2912 | Ng2920 | ~Ng2924 | Ng2917 | ~Ng2883 | Ng2888; - assign n6577 = Ng1905 & ~Ng2039 & Ng1918; - assign n6578 = Ng1211 & ~Ng1345 & Ng1224; - assign n6579_1 = Ng525 & ~Ng659 & Ng538; - assign n6580 = ~n4902 ^ ~n5864; - assign n6581 = ~n4864 ^ ~n5884; - assign n6582 = ~n4822 ^ ~n5904; - assign n6583 = ~n4780 ^ ~n5924; - assign n6584_1 = ~Ng3024 ^ ~n6198; - assign n6585 = ~n4880_1 ^ ~n6150; - assign n6586 = ~n4838_1 ^ ~n6157; - assign n6587_1 = ~n4796_1 ^ ~n6164; - assign n6588 = ~n4754 ^ ~n6171_1; - assign n6589 = ~n4532 ^ ~n4541_1; - assign n7213 = ~Ng3083 ^ ~n6589; - assign n6591 = ~n4535 ^ ~n4538; - assign n7255 = ~Ng2990 ^ ~n6591; - assign n7209 = n6589 ^ ~n8762; - assign n7260 = n6591 ^ ~n8762; - assign n6595 = ~n5607 ^ ~n5612; - assign n344 = ~Ng2934 ^ ~n6595; - assign n6597_1 = ~n5597 ^ ~n5602; - assign n349_1 = ~Ng2962 ^ ~n6597_1; - assign n6599 = (~n4952 & ~n8454) | (~n4982 & (n4952 | ~n8454)); - assign n6600 = n8550 & (~Ng8284 | ~Ng544); - assign n6601 = (n8551 & (~Ng8293 | ~Ng1230)) | (Ng8293 & ~Ng1230); - assign n6602_1 = (n8552 & (~Ng8302 | ~Ng1924)) | (Ng8302 & ~Ng1924); - assign n6603 = (n8553 & (~Ng8311 | ~Ng2618)) | (Ng8311 & ~Ng2618); - assign n6604 = (~n5064 & (n4778_1 | n8455)) | (~n4778_1 & n8455); - assign n6605 = (~n5064 & (n4812 | n8455)) | (~n4812 & n8455); - assign n6606 = (~n5064 & (n4882 | n8455)) | (~n4882 & n8455); - assign n6607_1 = (~n4848 & ~n8454) | (~n4982 & (n4848 | ~n8454)); - assign n6608 = (Ng1315 & n6603) | (~Ng3108 & (~Ng1315 | n6603)); - assign n784_1 = ~n6608; - assign n6610 = (\[1603] & n6603) | (~Ng3107 & (~\[1603] | n6603)); - assign n779 = ~n6610; - assign n6612_1 = (\[1605] & n6603) | (~Ng3106 & (~\[1605] | n6603)); - assign n774 = ~n6612_1; - assign n6614 = (~n4944 & ~n8452) | (~n4978_1 & (n4944 | ~n8452)); - assign n6615 = (~n5062 & (n4742_1 | n8453)) | (~n4742_1 & n8453); - assign n6616 = (~n5062 & (n4770 | n8453)) | (~n4770 & n8453); - assign n6617_1 = (~n5062 & (n4840 | n8453)) | (~n4840 & n8453); - assign n6618 = (~n4806 & ~n8452) | (~n4978_1 & (n4806 | ~n8452)); - assign n6619 = (Ng853 & n8565) | (~Ng2392 & (~Ng853 | n8565)); - assign n6003 = ~n6619; - assign n6621 = (\[1594] & n8565) | (~Ng2391 & (~\[1594] | n8565)); - assign n5998 = ~n6621; - assign n6623 = (\[1612] & n8565) | (~Ng2390 & (~\[1612] | n8565)); - assign n5993 = ~n6623; - assign n6625 = n6486 & ~n4924_1 & ~n4904 & ~n4810_1 & ~n4746 & ~n4774_1; - assign n6626 = (~n5926 & n6625) | (n6487 & (n5926 | n6625)); - assign n6627_1 = (~Ng853 & ~Ng2348) | (~n5503 & (Ng853 | ~Ng2348)); - assign n5760 = ~n6627_1; - assign n6629 = (~\[1594] & ~Ng2345) | (~n5503 & (\[1594] | ~Ng2345)); - assign n5755 = ~n6629; - assign n6631 = (~\[1612] & ~Ng2342) | (~n5503 & (\[1612] | ~Ng2342)); - assign n5750 = ~n6631; - assign n6633 = (~Ng853 & ~Ng2321) | (~n5485_1 & (Ng853 | ~Ng2321)); - assign n5670 = ~n6633; - assign n6635 = (~\[1594] & ~Ng2318) | (~n5485_1 & (\[1594] | ~Ng2318)); - assign n5665 = ~n6635; - assign n6637_1 = (~\[1612] & ~Ng2315) | (~n5485_1 & (\[1612] | ~Ng2315)); - assign n5660 = ~n6637_1; - assign n6639 = (~Ng853 & ~Ng2312) | (~n5479 & (Ng853 | ~Ng2312)); - assign n5640 = ~n6639; - assign n6641 = (~\[1594] & ~Ng2309) | (~n5479 & (\[1594] | ~Ng2309)); - assign n5635 = ~n6641; - assign n6643 = (~\[1612] & ~Ng2306) | (~n5479 & (\[1612] | ~Ng2306)); - assign n5630 = ~n6643; - assign n6645 = (~Ng853 & ~Ng2303) | (~n5473 & (Ng853 | ~Ng2303)); - assign n5745 = ~n6645; - assign n6647_1 = (~\[1594] & ~Ng2300) | (~n5473 & (\[1594] | ~Ng2300)); - assign n5740 = ~n6647_1; - assign n6649 = (~\[1612] & ~Ng2297) | (~n5473 & (\[1612] | ~Ng2297)); - assign n5735 = ~n6649; - assign n6651 = (~Ng853 & ~Ng2276) | (~n5506 & (Ng853 | ~Ng2276)); - assign n5655 = ~n6651; - assign n6653 = (~\[1594] & ~Ng2273) | (~n5506 & (\[1594] | ~Ng2273)); - assign n5650 = ~n6653; - assign n6655 = (~\[1612] & ~Ng2270) | (~n5506 & (\[1612] | ~Ng2270)); - assign n5645 = ~n6655; - assign n6657_1 = (Ng853 & n8570) | (~Ng1698 & (~Ng853 | n8570)); - assign n4496 = ~n6657_1; - assign n6659 = (\[1594] & n8570) | (~Ng1697 & (~\[1594] | n8570)); - assign n4491 = ~n6659; - assign n6661 = (\[1612] & n8570) | (~Ng1696 & (~\[1612] | n8570)); - assign n4486 = ~n6661; - assign n6663 = n6496 & ~n4894 & ~n4866_1 & ~n4768 & ~n4716_1 & ~n4738; - assign n6664 = (~n5933_1 & n6663) | (n6497 & (n5933_1 | n6663)); - assign n6665 = (~Ng853 & ~Ng1654) | (~n5497 & (Ng853 | ~Ng1654)); - assign n4266 = ~n6665; - assign n6667_1 = (~\[1594] & ~Ng1651) | (~n5497 & (\[1594] | ~Ng1651)); - assign n4261_1 = ~n6667_1; - assign n6669 = (~\[1612] & ~Ng1648) | (~n5497 & (\[1612] | ~Ng1648)); - assign n4256 = ~n6669; - assign n6671 = (~Ng853 & ~Ng1627) | (~n5476 & (Ng853 | ~Ng1627)); - assign n4176 = ~n6671; - assign n6673 = (~\[1594] & ~Ng1624) | (~n5476 & (\[1594] | ~Ng1624)); - assign n4171 = ~n6673; - assign n6675 = (~\[1612] & ~Ng1621) | (~n5476 & (\[1612] | ~Ng1621)); - assign n4166 = ~n6675; - assign n6677_1 = (~Ng853 & ~Ng1618) | (~n5470_1 & (Ng853 | ~Ng1618)); - assign n4146 = ~n6677_1; - assign n6679 = (~\[1594] & ~Ng1615) | (~n5470_1 & (\[1594] | ~Ng1615)); - assign n4141 = ~n6679; - assign n6681 = (~\[1612] & ~Ng1612) | (~n5470_1 & (\[1612] | ~Ng1612)); - assign n4136_1 = ~n6681; - assign n6683 = (~Ng853 & ~Ng1609) | (~n5464 & (Ng853 | ~Ng1609)); - assign n4251 = ~n6683; - assign n6685 = (~\[1594] & ~Ng1606) | (~n5464 & (\[1594] | ~Ng1606)); - assign n4246 = ~n6685; - assign n6687_1 = (~\[1612] & ~Ng1603) | (~n5464 & (\[1612] | ~Ng1603)); - assign n4241_1 = ~n6687_1; - assign n6689 = (~Ng853 & ~Ng1582) | (~n5500_1 & (Ng853 | ~Ng1582)); - assign n4161 = ~n6689; - assign n6691 = (~\[1594] & ~Ng1579) | (~n5500_1 & (\[1594] | ~Ng1579)); - assign n4156 = ~n6691; - assign n6693 = (~\[1612] & ~Ng1576) | (~n5500_1 & (\[1612] | ~Ng1576)); - assign n4151 = ~n6693; - assign n6695 = (Ng853 & n8575) | (~Ng1004 & (~Ng853 | n8575)); - assign n2989_1 = ~n6695; - assign n6697_1 = (\[1594] & n8575) | (~Ng1003 & (~\[1594] | n8575)); - assign n2984_1 = ~n6697_1; - assign n6699 = (\[1612] & n8575) | (~Ng1002 & (~\[1612] | n8575)); - assign n2979_1 = ~n6699; - assign n6701 = n6506 & ~n4856_1 & ~n4824_1 & ~n4732_1 & ~n4692_1 & ~n4708_1; - assign n6702_1 = (~n5940 & n6701) | (n6507 & (n5940 | n6701)); - assign n6703 = (~Ng853 & ~Ng960) | (~n5491 & (Ng853 | ~Ng960)); - assign n2759_1 = ~n6703; - assign n6705 = (~\[1594] & ~Ng957) | (~n5491 & (\[1594] | ~Ng957)); - assign n2754_1 = ~n6705; - assign n6707_1 = (~\[1612] & ~Ng954) | (~n5491 & (\[1612] | ~Ng954)); - assign n2749_1 = ~n6707_1; - assign n6709 = (~Ng853 & ~Ng933) | (~n5467 & (Ng853 | ~Ng933)); - assign n2669 = ~n6709; - assign n6711 = (~\[1594] & ~Ng930) | (~n5467 & (\[1594] | ~Ng930)); - assign n2664 = ~n6711; - assign n6713 = (~\[1612] & ~Ng927) | (~n5467 & (\[1612] | ~Ng927)); - assign n2659 = ~n6713; - assign n6715 = (~Ng853 & ~Ng924) | (~n5461 & (Ng853 | ~Ng924)); - assign n2639 = ~n6715; - assign n6717_1 = (~\[1594] & ~Ng921) | (~n5461 & (\[1594] | ~Ng921)); - assign n2634 = ~n6717_1; - assign n6719 = (~\[1612] & ~Ng918) | (~n5461 & (\[1612] | ~Ng918)); - assign n2629 = ~n6719; - assign n6721 = (~Ng853 & ~Ng915) | (~n5455_1 & (Ng853 | ~Ng915)); - assign n2744_1 = ~n6721; - assign n6723 = (~\[1594] & ~Ng912) | (~n5455_1 & (\[1594] | ~Ng912)); - assign n2739_1 = ~n6723; - assign n6725 = (~\[1612] & ~Ng909) | (~n5455_1 & (\[1612] | ~Ng909)); - assign n2734_1 = ~n6725; - assign n6727_1 = (~Ng853 & ~Ng888) | (~n5494 & (Ng853 | ~Ng888)); - assign n2654 = ~n6727_1; - assign n6729 = (~\[1594] & ~Ng885) | (~n5494 & (\[1594] | ~Ng885)); - assign n2649 = ~n6729; - assign n6731 = (~\[1612] & ~Ng882) | (~n5494 & (\[1612] | ~Ng882)); - assign n2644 = ~n6731; - assign n6733 = (Ng853 & n8580) | (~Ng317 & (~Ng853 | n8580)); - assign n1483_1 = ~n6733; - assign n6735 = (\[1594] & n8580) | (~Ng316 & (~\[1594] | n8580)); - assign n1478_1 = ~n6735; - assign n6737_1 = (\[1612] & n8580) | (~Ng315 & (~\[1612] | n8580)); - assign n1473_1 = ~n6737_1; - assign n6739 = n6516 & ~n4814_1 & ~n4782 & ~n4702 & ~n4672_1 & ~n4684_1; - assign n6740 = (~n5947 & n6739) | (n6517 & (n5947 | n6739)); - assign n6741 = (~Ng853 & ~Ng273) | (~n5482 & (Ng853 | ~Ng273)); - assign n1253_1 = ~n6741; - assign n6743 = (~\[1594] & ~Ng270) | (~n5482 & (\[1594] | ~Ng270)); - assign n1248_1 = ~n6743; - assign n6745 = (~\[1612] & ~Ng267) | (~n5482 & (\[1612] | ~Ng267)); - assign n1243_1 = ~n6745; - assign n6747_1 = (~Ng853 & ~Ng246) | (~n5458 & (Ng853 | ~Ng246)); - assign n1163_1 = ~n6747_1; - assign n6749 = (~\[1594] & ~Ng243) | (~n5458 & (\[1594] | ~Ng243)); - assign n1158_1 = ~n6749; - assign n6751 = (~\[1612] & ~Ng240) | (~n5458 & (\[1612] | ~Ng240)); - assign n1153_1 = ~n6751; - assign n6753 = (~Ng853 & ~Ng237) | (~n5452 & (Ng853 | ~Ng237)); - assign n1133_1 = ~n6753; - assign n6755 = (~\[1594] & ~Ng234) | (~n5452 & (\[1594] | ~Ng234)); - assign n1128_1 = ~n6755; - assign n6757_1 = (~\[1612] & ~Ng231) | (~n5452 & (\[1612] | ~Ng231)); - assign n1123_1 = ~n6757_1; - assign n6759 = (~Ng853 & ~Ng228) | (~n5449 & (Ng853 | ~Ng228)); - assign n1238_1 = ~n6759; - assign n6761 = (~\[1594] & ~Ng225) | (~n5449 & (\[1594] | ~Ng225)); - assign n1233_1 = ~n6761; - assign n6763 = (~\[1612] & ~Ng222) | (~n5449 & (\[1612] | ~Ng222)); - assign n1228_1 = ~n6763; - assign n6765 = (~Ng853 & ~Ng201) | (~n5488 & (Ng853 | ~Ng201)); - assign n1148_1 = ~n6765; - assign n6767_1 = (~\[1594] & ~Ng198) | (~n5488 & (\[1594] | ~Ng198)); - assign n1143_1 = ~n6767_1; - assign n6769 = (~\[1612] & ~Ng195) | (~n5488 & (\[1612] | ~Ng195)); - assign n1138_1 = ~n6769; - assign n6771 = (~Ng853 & ~Ng2395) | (~n5446 & (Ng853 | ~Ng2395)); - assign n6018 = ~n6771; - assign n6773 = (\[1594] & ~n5446) | (~Ng2394 & (~\[1594] | ~n5446)); - assign n6013 = ~n6773; - assign n6775 = (~\[1612] & ~Ng2393) | (~n5446 & (\[1612] | ~Ng2393)); - assign n6008 = ~n6775; - assign n6777_1 = (~Ng853 & ~Ng1701) | (~n5443 & (Ng853 | ~Ng1701)); - assign n4511 = ~n6777_1; - assign n6779 = (\[1594] & ~n5443) | (~Ng1700 & (~\[1594] | ~n5443)); - assign n4506_1 = ~n6779; - assign n6781 = (~\[1612] & ~Ng1699) | (~n5443 & (\[1612] | ~Ng1699)); - assign n4501 = ~n6781; - assign n6783 = (~Ng853 & ~Ng1007) | (~n5440_1 & (Ng853 | ~Ng1007)); - assign n3004_1 = ~n6783; - assign n6785 = (\[1594] & ~n5440_1) | (~Ng1006 & (~\[1594] | ~n5440_1)); - assign n2999 = ~n6785; - assign n6787_1 = (~\[1612] & ~Ng1005) | (~n5440_1 & (\[1612] | ~Ng1005)); - assign n2994_1 = ~n6787_1; - assign n6789 = (~Ng853 & ~Ng320) | (~n5437 & (Ng853 | ~Ng320)); - assign n1498 = ~n6789; - assign n6791 = (\[1594] & ~n5437) | (~Ng319 & (~\[1594] | ~n5437)); - assign n1493 = ~n6791; - assign n6793 = (~\[1612] & ~Ng318) | (~n5437 & (\[1612] | ~Ng318)); - assign n1488_1 = ~n6793; - assign n6795 = (n5865 & n8585) | (n5929 & (~n5865 | n8585)); - assign n6796 = (Ng853 & ~n6795) | (~Ng2339 & (~Ng853 | ~n6795)); - assign n5730 = ~n6796; - assign n6798 = (\[1594] & ~n6795) | (~Ng2336 & (~\[1594] | ~n6795)); - assign n5725 = ~n6798; - assign n6800 = (\[1612] & ~n6795) | (~Ng2333 & (~\[1612] | ~n6795)); - assign n5720 = ~n6800; - assign n6802_1 = (~Ng853 & ~Ng2330) | (n6382 & (Ng853 | ~Ng2330)); - assign n5700 = ~n6802_1; - assign n6804 = (~\[1594] & ~Ng2327) | (n6382 & (\[1594] | ~Ng2327)); - assign n5695 = ~n6804; - assign n6806 = (~\[1612] & ~Ng2324) | (n6382 & (\[1612] | ~Ng2324)); - assign n5690 = ~n6806; - assign n6808 = (n5865 & n8586) | (n5930 & (~n5865 | n8586)); - assign n6809 = (Ng853 & ~n6808) | (~Ng2294 & (~Ng853 | ~n6808)); - assign n5715 = ~n6809; - assign n6811 = (\[1594] & ~n6808) | (~Ng2291 & (~\[1594] | ~n6808)); - assign n5710 = ~n6811; - assign n6813 = (\[1612] & ~n6808) | (~Ng2288 & (~\[1612] | ~n6808)); - assign n5705 = ~n6813; - assign n6815 = (n5865 & n8588) | (n5931 & (~n5865 | n8588)); - assign n6816 = (Ng853 & ~n6815) | (~Ng2285 & (~Ng853 | ~n6815)); - assign n5685 = ~n6816; - assign n6818 = (\[1594] & ~n6815) | (~Ng2282 & (~\[1594] | ~n6815)); - assign n5680 = ~n6818; - assign n6820 = (\[1612] & ~n6815) | (~Ng2279 & (~\[1612] | ~n6815)); - assign n5675 = ~n6820; - assign n6822_1 = (n5865 & n6580) | (n5932 & (~n5865 | n6580)); - assign n6823 = (Ng853 & ~n6822_1) | (~Ng2267 & (~Ng853 | ~n6822_1)); - assign n5625 = ~n6823; - assign n6825 = (\[1594] & ~n6822_1) | (~Ng2264 & (~\[1594] | ~n6822_1)); - assign n5620 = ~n6825; - assign n6827_1 = (\[1612] & ~n6822_1) | (~Ng2261 & (~\[1612] | ~n6822_1)); - assign n5615 = ~n6827_1; - assign n6829 = (n5885 & n8589) | (n5936 & (~n5885 | n8589)); - assign n6830 = (Ng853 & ~n6829) | (~Ng1645 & (~Ng853 | ~n6829)); - assign n4236_1 = ~n6830; - assign n6832_1 = (\[1594] & ~n6829) | (~Ng1642 & (~\[1594] | ~n6829)); - assign n4231 = ~n6832_1; - assign n6834 = (\[1612] & ~n6829) | (~Ng1639 & (~\[1612] | ~n6829)); - assign n4226 = ~n6834; - assign n6836 = (~Ng853 & ~Ng1636) | (n6384 & (Ng853 | ~Ng1636)); - assign n4206 = ~n6836; - assign n6838 = (~\[1594] & ~Ng1633) | (n6384 & (\[1594] | ~Ng1633)); - assign n4201 = ~n6838; - assign n6840 = (~\[1612] & ~Ng1630) | (n6384 & (\[1612] | ~Ng1630)); - assign n4196 = ~n6840; - assign n6842_1 = (n5885 & n8590) | (n5937 & (~n5885 | n8590)); - assign n6843 = (Ng853 & ~n6842_1) | (~Ng1600 & (~Ng853 | ~n6842_1)); - assign n4221 = ~n6843; - assign n6845 = (\[1594] & ~n6842_1) | (~Ng1597 & (~\[1594] | ~n6842_1)); - assign n4216 = ~n6845; - assign n6847_1 = (\[1612] & ~n6842_1) | (~Ng1594 & (~\[1612] | ~n6842_1)); - assign n4211 = ~n6847_1; - assign n6849 = (n5885 & n8592) | (n5938_1 & (~n5885 | n8592)); - assign n6850 = (Ng853 & ~n6849) | (~Ng1591 & (~Ng853 | ~n6849)); - assign n4191_1 = ~n6850; - assign n6852_1 = (\[1594] & ~n6849) | (~Ng1588 & (~\[1594] | ~n6849)); - assign n4186 = ~n6852_1; - assign n6854 = (\[1612] & ~n6849) | (~Ng1585 & (~\[1612] | ~n6849)); - assign n4181_1 = ~n6854; - assign n6856 = (n5885 & n6581) | (n5939 & (~n5885 | n6581)); - assign n6857_1 = (Ng853 & ~n6856) | (~Ng1573 & (~Ng853 | ~n6856)); - assign n4131 = ~n6857_1; - assign n6859 = (\[1594] & ~n6856) | (~Ng1570 & (~\[1594] | ~n6856)); - assign n4126 = ~n6859; - assign n6861 = (\[1612] & ~n6856) | (~Ng1567 & (~\[1612] | ~n6856)); - assign n4121 = ~n6861; - assign n6863 = (n5905 & n8593) | (n5943_1 & (~n5905 | n8593)); - assign n6864 = (Ng853 & ~n6863) | (~Ng951 & (~Ng853 | ~n6863)); - assign n2729_1 = ~n6864; - assign n6866 = (\[1594] & ~n6863) | (~Ng948 & (~\[1594] | ~n6863)); - assign n2724_1 = ~n6866; - assign n6868 = (\[1612] & ~n6863) | (~Ng945 & (~\[1612] | ~n6863)); - assign n2719 = ~n6868; - assign n6870 = (~Ng853 & ~Ng942) | (n6386 & (Ng853 | ~Ng942)); - assign n2699_1 = ~n6870; - assign n6872_1 = (~\[1594] & ~Ng939) | (n6386 & (\[1594] | ~Ng939)); - assign n2694_1 = ~n6872_1; - assign n6874 = (~\[1612] & ~Ng936) | (n6386 & (\[1612] | ~Ng936)); - assign n2689 = ~n6874; - assign n6876 = (n5905 & n8594) | (n5944 & (~n5905 | n8594)); - assign n6877_1 = (Ng853 & ~n6876) | (~Ng906 & (~Ng853 | ~n6876)); - assign n2714_1 = ~n6877_1; - assign n6879 = (\[1594] & ~n6876) | (~Ng903 & (~\[1594] | ~n6876)); - assign n2709 = ~n6879; - assign n6881 = (\[1612] & ~n6876) | (~Ng900 & (~\[1612] | ~n6876)); - assign n2704_1 = ~n6881; - assign n6883 = (n5905 & n8596) | (n5945 & (~n5905 | n8596)); - assign n6884 = (Ng853 & ~n6883) | (~Ng897 & (~Ng853 | ~n6883)); - assign n2684 = ~n6884; - assign n6886 = (\[1594] & ~n6883) | (~Ng894 & (~\[1594] | ~n6883)); - assign n2679 = ~n6886; - assign n6888 = (\[1612] & ~n6883) | (~Ng891 & (~\[1612] | ~n6883)); - assign n2674 = ~n6888; - assign n6890 = (n5905 & n6582) | (n5946 & (~n5905 | n6582)); - assign n6891 = (Ng853 & ~n6890) | (~Ng879 & (~Ng853 | ~n6890)); - assign n2624 = ~n6891; - assign n6893 = (\[1594] & ~n6890) | (~Ng876 & (~\[1594] | ~n6890)); - assign n2619_1 = ~n6893; - assign n6895 = (\[1612] & ~n6890) | (~Ng873 & (~\[1612] | ~n6890)); - assign n2614 = ~n6895; - assign n6897_1 = (n5925 & n8597) | (n5950 & (~n5925 | n8597)); - assign n6898 = (Ng853 & ~n6897_1) | (~Ng264 & (~Ng853 | ~n6897_1)); - assign n1223_1 = ~n6898; - assign n6900 = (\[1594] & ~n6897_1) | (~Ng261 & (~\[1594] | ~n6897_1)); - assign n1218_1 = ~n6900; - assign n6902_1 = (\[1612] & ~n6897_1) | (~Ng258 & (~\[1612] | ~n6897_1)); - assign n1213_1 = ~n6902_1; - assign n6904 = (~Ng853 & ~Ng255) | (n6388 & (Ng853 | ~Ng255)); - assign n1193_1 = ~n6904; - assign n6906 = (~\[1594] & ~Ng252) | (n6388 & (\[1594] | ~Ng252)); - assign n1188_1 = ~n6906; - assign n6908 = (~\[1612] & ~Ng249) | (n6388 & (\[1612] | ~Ng249)); - assign n1183_1 = ~n6908; - assign n6910 = (n5925 & n8598) | (n5951 & (~n5925 | n8598)); - assign n6911 = (Ng853 & ~n6910) | (~Ng219 & (~Ng853 | ~n6910)); - assign n1208_1 = ~n6911; - assign n6913 = (\[1594] & ~n6910) | (~Ng216 & (~\[1594] | ~n6910)); - assign n1203_1 = ~n6913; - assign n6915 = (\[1612] & ~n6910) | (~Ng213 & (~\[1612] | ~n6910)); - assign n1198_1 = ~n6915; - assign n6917_1 = (n5925 & n8600) | (n5952 & (~n5925 | n8600)); - assign n6918 = (Ng853 & ~n6917_1) | (~Ng210 & (~Ng853 | ~n6917_1)); - assign n1178 = ~n6918; - assign n6920 = (\[1594] & ~n6917_1) | (~Ng207 & (~\[1594] | ~n6917_1)); - assign n1173_1 = ~n6920; - assign n6922_1 = (\[1612] & ~n6917_1) | (~Ng204 & (~\[1612] | ~n6917_1)); - assign n1168_1 = ~n6922_1; - assign n6924 = (n5925 & n6583) | (n5953_1 & (~n5925 | n6583)); - assign n6925 = (Ng853 & ~n6924) | (~Ng192 & (~Ng853 | ~n6924)); - assign n1118_1 = ~n6925; - assign n6927 = (\[1594] & ~n6924) | (~Ng189 & (~\[1594] | ~n6924)); - assign n1113_1 = ~n6927; - assign n6929 = (\[1612] & ~n6924) | (~Ng186 & (~\[1612] | ~n6924)); - assign n1108 = ~n6929; - assign n5077 = (Ng1886 & Ng1887) | (n8605 & (~Ng1886 | Ng1887)); - assign n6932 = (Ng2580 & ~Ng2581) | (n8606 & (~Ng2580 | ~Ng2581)); - assign n6584 = ~n6932; - assign n6934 = n8607 & (\[1594] | ~Ng305 | ~Ng299); - assign n1618_1 = ~n6934; - assign n6936_1 = (~Ng986 & Ng985) | (n8608 & (Ng986 | Ng985)); - assign n3124_1 = ~n6936_1; - assign n6938 = (~Ng1680 & Ng1679) | (n8609 & (Ng1680 | Ng1679)); - assign n4631 = ~n6938; - assign n6940 = (~Ng2374 & Ng2373) | (n8610 & (Ng2374 | Ng2373)); - assign n6138 = ~n6940; - assign n6942 = (Ng1315 & n6602_1) | (~Ng3105 & (~Ng1315 | n6602_1)); - assign n769_1 = ~n6942; - assign n6944 = (\[1603] & n6602_1) | (~Ng3104 & (~\[1603] | n6602_1)); - assign n764_1 = ~n6944; - assign n6946_1 = (\[1605] & n6602_1) | (~Ng3103 & (~\[1605] | n6602_1)); - assign n759_1 = ~n6946_1; - assign n6948 = (~n4932 & ~n5528) | (~n4972 & (n4932 | ~n5528)); - assign n6949 = (~n5058_1 & (n4712_1 | n8451)) | (~n4712_1 & n8451); - assign n6950 = (~n5058_1 & (n4734 | n8451)) | (~n4734 & n8451); - assign n6951_1 = (~n5058_1 & (n4798 | n8451)) | (~n4798 & n8451); - assign n6952 = (~n4764 & ~n5528) | (~n4972 & (n4764 | ~n5528)); - assign n6953 = (Ng853 & n8614) | (~Ng2389 & (~Ng853 | n8614)); - assign n5988 = ~n6953; - assign n6955 = (\[1594] & n8614) | (~Ng2388 & (~\[1594] | n8614)); - assign n5983 = ~n6955; - assign n6957 = (\[1612] & n8614) | (~Ng2387 & (~\[1612] | n8614)); - assign n5978 = ~n6957; - assign n6959 = (Ng853 & n8615) | (~Ng1695 & (~Ng853 | n8615)); - assign n4481 = ~n6959; - assign n6961_1 = (\[1594] & n8615) | (~Ng1694 & (~\[1594] | n8615)); - assign n4476 = ~n6961_1; - assign n6963 = (\[1612] & n8615) | (~Ng1693 & (~\[1612] | n8615)); - assign n4471 = ~n6963; - assign n6965 = (Ng853 & n8616) | (~Ng1001 & (~Ng853 | n8616)); - assign n2974_1 = ~n6965; - assign n6967 = (\[1594] & n8616) | (~Ng1000 & (~\[1594] | n8616)); - assign n2969_1 = ~n6967; - assign n6969 = (\[1612] & n8616) | (~Ng999 & (~\[1612] | n8616)); - assign n2964_1 = ~n6969; - assign n6971_1 = (Ng853 & n8617) | (~Ng314 & (~Ng853 | n8617)); - assign n1468_1 = ~n6971_1; - assign n6973 = (\[1594] & n8617) | (~Ng313 & (~\[1594] | n8617)); - assign n1463_1 = ~n6973; - assign n6975 = (\[1612] & n8617) | (~Ng312 & (~\[1612] | n8617)); - assign n1458_1 = ~n6975; - assign n6977 = (Ng3147 & n6282) | (~n6131 & (~Ng3147 | n6282)); - assign n6978 = (~n4912 & ~n5508) | (~n4964 & (n4912 | ~n5508)); - assign n6979 = (~n5054 & (n4688_1 | n8450)) | (~n4688_1 & n8450); - assign n6980 = (~n5054 & (n4704_1 | n8450)) | (~n4704_1 & n8450); - assign n6981_1 = (~n5054 & (n4756_1 | n8450)) | (~n4756_1 & n8450); - assign n6982 = (~n4728_1 & ~n5508) | (~n4964 & (n4728_1 | ~n5508)); - assign n6983 = (Ng853 & n8621) | (~Ng2498 & (~Ng853 | n8621)); - assign n5913 = ~n6983; - assign n6985 = (\[1594] & n8621) | (~Ng2495 & (~\[1594] | n8621)); - assign n5908 = ~n6985; - assign n6987 = (\[1612] & n8621) | (~Ng2492 & (~\[1612] | n8621)); - assign n5903 = ~n6987; - assign n6989 = (~Ng2396 & ~n8623) | (~n5991 & (~Ng2396 | n8623)); - assign n6033 = ~n6989; - assign n6991_1 = (~n5991 & n8624) | (~Ng2398 & (~n5991 | ~n8624)); - assign n6028 = ~n6991_1; - assign n6993 = (~Ng2397 & ~n8625) | (~n5991 & (~Ng2397 | n8625)); - assign n6023 = ~n6993; - assign n6995 = (Ng853 & n8626) | (~Ng1804 & (~Ng853 | n8626)); - assign n4406 = ~n6995; - assign n6997 = (\[1594] & n8626) | (~Ng1801 & (~\[1594] | n8626)); - assign n4401 = ~n6997; - assign n6999 = (\[1612] & n8626) | (~Ng1798 & (~\[1612] | n8626)); - assign n4396 = ~n6999; - assign n7001_1 = (~Ng1702 & ~n8628) | (~n5999 & (~Ng1702 | n8628)); - assign n4526 = ~n7001_1; - assign n7003 = (~n5999 & n8629) | (~Ng1704 & (~n5999 | ~n8629)); - assign n4521 = ~n7003; - assign n7005 = (~Ng1703 & ~n8630) | (~n5999 & (~Ng1703 | n8630)); - assign n4516 = ~n7005; - assign n7007 = (Ng853 & n8631) | (~Ng1110 & (~Ng853 | n8631)); - assign n2899 = ~n7007; - assign n7009 = (\[1594] & n8631) | (~Ng1107 & (~\[1594] | n8631)); - assign n2894 = ~n7009; - assign n7011_1 = (\[1612] & n8631) | (~Ng1104 & (~\[1612] | n8631)); - assign n2889 = ~n7011_1; - assign n7013 = (~Ng1008 & ~n8633) | (~n6007 & (~Ng1008 | n8633)); - assign n3019_1 = ~n7013; - assign n7015 = (~n6007 & n8634) | (~Ng1010 & (~n6007 | ~n8634)); - assign n3014 = ~n7015; - assign n7017 = (~Ng1009 & ~n8635) | (~n6007 & (~Ng1009 | n8635)); - assign n3009_1 = ~n7017; - assign n7019 = (Ng853 & n8636) | (~Ng423 & (~Ng853 | n8636)); - assign n1393 = ~n7019; - assign n7021_1 = (\[1594] & n8636) | (~Ng420 & (~\[1594] | n8636)); - assign n1388 = ~n7021_1; - assign n7023 = (\[1612] & n8636) | (~Ng417 & (~\[1612] | n8636)); - assign n1383 = ~n7023; - assign n7025 = (~Ng321 & ~n8638) | (~n6015 & (~Ng321 | n8638)); - assign n1513_1 = ~n7025; - assign n7027 = (~n6015 & n8639) | (~Ng323 & (~n6015 | ~n8639)); - assign n1508 = ~n7027; - assign n7029 = (~Ng322 & ~n8640) | (~n6015 & (~Ng322 | n8640)); - assign n1503 = ~n7029; - assign n7031_1 = (Ng853 & n8642) | (~Ng2489 & (~Ng853 | n8642)); - assign n5898 = ~n7031_1; - assign n7033 = (\[1594] & n8642) | (~Ng2486 & (~\[1594] | n8642)); - assign n5893 = ~n7033; - assign n7035 = (\[1612] & n8642) | (~Ng2483 & (~\[1612] | n8642)); - assign n5888 = ~n7035; - assign n7037 = (Ng853 & n8644) | (~Ng1795 & (~Ng853 | n8644)); - assign n4391 = ~n7037; - assign n7039 = (\[1594] & n8644) | (~Ng1792 & (~\[1594] | n8644)); - assign n4386 = ~n7039; - assign n7041_1 = (\[1612] & n8644) | (~Ng1789 & (~\[1612] | n8644)); - assign n4381 = ~n7041_1; - assign n7043 = (Ng853 & n8646) | (~Ng1101 & (~Ng853 | n8646)); - assign n2884_1 = ~n7043; - assign n7045 = (\[1594] & n8646) | (~Ng1098 & (~\[1594] | n8646)); - assign n2879_1 = ~n7045; - assign n7047 = (\[1612] & n8646) | (~Ng1095 & (~\[1612] | n8646)); - assign n2874_1 = ~n7047; - assign n7049 = (Ng853 & n8648) | (~Ng414 & (~Ng853 | n8648)); - assign n1378_1 = ~n7049; - assign n7051_1 = (\[1594] & n8648) | (~Ng411 & (~\[1594] | n8648)); - assign n1373_1 = ~n7051_1; - assign n7053 = (\[1612] & n8648) | (~Ng408 & (~\[1612] | n8648)); - assign n1368 = ~n7053; - assign n7055 = (Ng1315 & n6601) | (~Ng3102 & (~Ng1315 | n6601)); - assign n754_1 = ~n7055; - assign n7057 = (\[1603] & n6601) | (~Ng3101 & (~\[1603] | n6601)); - assign n749_1 = ~n7057; - assign n7059 = (\[1605] & n6601) | (~Ng3100 & (~\[1605] | n6601)); - assign n744_1 = ~n7059; - assign n7061_1 = n4571 & (~n6056 | (~n4567 & ~n6053_1)); - assign n7062 = (~n6061 & n6064) | (n5084 & (~n6061 | ~n6064)); - assign n7063 = (Ng1315 & n8650) | (~Ng2694 & (~Ng1315 | n8650)); - assign n6540 = ~n7063; - assign n7065 = (\[1603] & n8650) | (~Ng2691 & (~\[1603] | n8650)); - assign n6535 = ~n7065; - assign n7067 = (\[1605] & n8650) | (~Ng2688 & (~\[1605] | n8650)); - assign n6530 = ~n7067; - assign n7069 = n5084 | n6064; - assign n7070 = n6061 & n7069 & (~n5084 | n6554); - assign n7071_1 = (Ng1315 & n8651) | (~Ng2685 & (~Ng1315 | n8651)); - assign n6555 = ~n7071_1; - assign n7073 = (\[1603] & n8651) | (~Ng2682 & (~\[1603] | n8651)); - assign n6550 = ~n7073; - assign n7075 = (\[1605] & n8651) | (~Ng2679 & (~\[1605] | n8651)); - assign n6545 = ~n7075; - assign n7077 = n4565 & (~n6078 | (~n4559_1 & ~n6075_1)); - assign n7078 = (~n6083 & n6086) | (n5081 & (~n6083 | ~n6086)); - assign n7079 = (Ng1315 & n8653) | (~Ng2000 & (~Ng1315 | n8653)); - assign n5033 = ~n7079; - assign n7081_1 = (\[1603] & n8653) | (~Ng1997 & (~\[1603] | n8653)); - assign n5028 = ~n7081_1; - assign n7083 = (\[1605] & n8653) | (~Ng1994 & (~\[1605] | n8653)); - assign n5023 = ~n7083; - assign n7085 = n5081 | n6086; - assign n7086_1 = n6083 & n7085 & (~n5081 | n6559); - assign n7087 = (Ng1315 & n8654) | (~Ng1991 & (~Ng1315 | n8654)); - assign n5048 = ~n7087; - assign n7089 = (\[1603] & n8654) | (~Ng1988 & (~\[1603] | n8654)); - assign n5043 = ~n7089; - assign n7091_1 = (\[1605] & n8654) | (~Ng1985 & (~\[1605] | n8654)); - assign n5038 = ~n7091_1; - assign n7093 = n4557 & (~n6100 | (~n4551 & ~n6097)); - assign n7094 = (~n6105 & n6108) | (n5078 & (~n6105 | ~n6108)); - assign n7095 = (Ng1315 & n8656) | (~Ng1306 & (~Ng1315 | n8656)); - assign n3526_1 = ~n7095; - assign n7097 = (\[1603] & n8656) | (~Ng1303 & (~\[1603] | n8656)); - assign n3521_1 = ~n7097; - assign n7099 = (\[1605] & n8656) | (~Ng1300 & (~\[1605] | n8656)); - assign n3516_1 = ~n7099; - assign n7101_1 = n5078 | n6108; - assign n7102 = n6105 & n7101_1 & (~n5078 | n6563); - assign n7103 = (Ng1315 & n8657) | (~Ng1297 & (~Ng1315 | n8657)); - assign n3541_1 = ~n7103; - assign n7105 = (\[1603] & n8657) | (~Ng1294 & (~\[1603] | n8657)); - assign n3536_1 = ~n7105; - assign n7107 = (\[1605] & n8657) | (~Ng1291 & (~\[1605] | n8657)); - assign n3531_1 = ~n7107; - assign n7109 = n4549 & (~n6122 | (~n4545 & ~n6119)); - assign n7110 = (~n6127 & n6130) | (n5075 & (~n6127 | ~n6130)); - assign n7111_1 = (Ng1315 & n8659) | (~Ng620 & (~Ng1315 | n8659)); - assign n2020_1 = ~n7111_1; - assign n7113 = (\[1603] & n8659) | (~Ng617 & (~\[1603] | n8659)); - assign n2015_1 = ~n7113; - assign n7115 = (\[1605] & n8659) | (~Ng614 & (~\[1605] | n8659)); - assign n2010 = ~n7115; - assign n7117 = n5075 | n6130; - assign n7118 = n6127 & n7117 & (~n5075 | n6567); - assign n7119 = (Ng1315 & n8660) | (~Ng611 & (~Ng1315 | n8660)); - assign n2035_1 = ~n7119; - assign n7121_1 = (\[1603] & n8660) | (~Ng608 & (~\[1603] | n8660)); - assign n2030 = ~n7121_1; - assign n7123 = (\[1605] & n8660) | (~Ng605 & (~\[1605] | n8660)); - assign n2025_1 = ~n7123; - assign n7125 = (~n8665 & n8666) | (~Ng2658 & (n8665 | n8666)); - assign n6495 = ~n7125; - assign n7127 = (n8666 & ~n8667) | (~Ng2660 & (n8666 | n8667)); - assign n6490 = ~n7127; - assign n7129 = (n8666 & ~n8668) | (~Ng2659 & (n8666 | n8668)); - assign n6485 = ~n7129; - assign n7131_1 = (n6552 & ~n8669) | (n5018_1 & (n6552 | n8669)); - assign n7132 = (~Ng2655 & n8665) | (~n7131_1 & (~Ng2655 | ~n8665)); - assign n6480 = ~n7132; - assign n7134 = (~n7131_1 & ~n8667) | (~Ng2657 & (~n7131_1 | n8667)); - assign n6475 = ~n7134; - assign n7136_1 = (~Ng2656 & n8668) | (~n7131_1 & (~Ng2656 | ~n8668)); - assign n6470 = ~n7136_1; - assign n7138 = (~n5028_1 & n8669) | (n5018_1 & (n5028_1 | n8669)); - assign n7139 = (~Ng2652 & n8665) | (~n7138 & (~Ng2652 | ~n8665)); - assign n6465 = ~n7139; - assign n7141_1 = (~n7138 & ~n8667) | (~Ng2654 & (~n7138 | n8667)); - assign n6460 = ~n7141_1; - assign n7143 = (~Ng2653 & n8668) | (~n7138 & (~Ng2653 | ~n8668)); - assign n6455 = ~n7143; - assign n7145 = (~Ng2649 & n8665) | (~n6179_1 & (~Ng2649 | ~n8665)); - assign n6450 = ~n7145; - assign n7147 = (~n6179_1 & ~n8667) | (~Ng2651 & (~n6179_1 | n8667)); - assign n6445 = ~n7147; - assign n7149 = (~Ng2650 & n8668) | (~n6179_1 & (~Ng2650 | ~n8668)); - assign n6440 = ~n7149; - assign n7151_1 = (n8671 & n8672) | (~Ng11589 & (~n8671 | n8672)); - assign n5883 = ~n7151_1; - assign n7153 = (n8672 & n8673) | (~Ng11588 & (n8672 | ~n8673)); - assign n5878 = ~n7153; - assign n7155 = (n8672 & n8674) | (~Ng11587 & (n8672 | ~n8674)); - assign n5873 = ~n7155; - assign n7157 = (n4906 | ~n6389) & ~n8764; - assign n7158 = (~Ng11586 & ~n8671) | (~n7157 & (~Ng11586 | n8671)); - assign n5868 = ~n7158; - assign n7160_1 = (~n7157 & n8673) | (~Ng11585 & (~n7157 | ~n8673)); - assign n5863 = ~n7160_1; - assign n7162 = (~Ng11584 & ~n8674) | (~n7157 & (~Ng11584 | n8674)); - assign n5858 = ~n7162; - assign n7164 = (~n4926 & n6389) | (n4906 & (n4926 | n6389)); - assign n7165 = (~Ng11583 & ~n8671) | (~n7164 & (~Ng11583 | n8671)); - assign n5853 = ~n7165; - assign n7167_1 = (~n7164 & n8673) | (~Ng11582 & (~n7164 | ~n8673)); - assign n5848 = ~n7167_1; - assign n7169 = (~Ng11581 & ~n8674) | (~n7164 & (~Ng11581 | n8674)); - assign n5843 = ~n7169; - assign n7171 = (~Ng11580 & ~n8671) | (~n6181 & (~Ng11580 | n8671)); - assign n5838 = ~n7171; - assign n7173 = (~n6181 & n8673) | (~Ng11579 & (~n6181 | ~n8673)); - assign n5833 = ~n7173; - assign n7175 = (~Ng11578 & ~n8674) | (~n6181 & (~Ng11578 | n8674)); - assign n5828 = ~n7175; - assign n7177 = (~n8676 & n8677) | (~Ng1964 & (n8676 | n8677)); - assign n4988 = ~n7177; - assign n7179 = (n8677 & ~n8678) | (~Ng1966 & (n8677 | n8678)); - assign n4983 = ~n7179; - assign n7181 = (n8677 & ~n8679) | (~Ng1965 & (n8677 | n8679)); - assign n4978 = ~n7181; - assign n7183 = (n6557 & ~n8680) | (n5006 & (n6557 | n8680)); - assign n7184_1 = (~Ng1961 & n8676) | (~n7183 & (~Ng1961 | ~n8676)); - assign n4973 = ~n7184_1; - assign n7186 = (~n7183 & ~n8678) | (~Ng1963 & (~n7183 | n8678)); - assign n4968 = ~n7186; - assign n7188_1 = (~Ng1962 & n8679) | (~n7183 & (~Ng1962 | ~n8679)); - assign n4963 = ~n7188_1; - assign n7190 = (~n5016 & n8680) | (n5006 & (n5016 | n8680)); - assign n7191 = (~Ng1958 & n8676) | (~n7190 & (~Ng1958 | ~n8676)); - assign n4958 = ~n7191; - assign n7193 = (~n7190 & ~n8678) | (~Ng1960 & (~n7190 | n8678)); - assign n4953 = ~n7193; - assign n7195 = (~Ng1959 & n8679) | (~n7190 & (~Ng1959 | ~n8679)); - assign n4948 = ~n7195; - assign n7197 = (~Ng1955 & n8676) | (~n6184 & (~Ng1955 | ~n8676)); - assign n4943 = ~n7197; - assign n7199 = (~n6184 & ~n8678) | (~Ng1957 & (~n6184 | n8678)); - assign n4938 = ~n7199; - assign n7201 = (~Ng1956 & n8679) | (~n6184 & (~Ng1956 | ~n8679)); - assign n4933 = ~n7201; - assign n7203 = (n8682 & n8683) | (~Ng11562 & (~n8682 | n8683)); - assign n4376 = ~n7203; - assign n7205 = (n8683 & n8684) | (~Ng11561 & (n8683 | ~n8684)); - assign n4371 = ~n7205; - assign n7207 = (n8683 & n8685) | (~Ng11560 & (n8683 | ~n8685)); - assign n4366 = ~n7207; - assign n7209_1 = (n4868 | ~n6390) & ~n8765; - assign n7210 = (~Ng11559 & ~n8682) | (~n7209_1 & (~Ng11559 | n8682)); - assign n4361 = ~n7210; - assign n7212 = (~n7209_1 & n8684) | (~Ng11558 & (~n7209_1 | ~n8684)); - assign n4356 = ~n7212; - assign n7214 = (~Ng11557 & ~n8685) | (~n7209_1 & (~Ng11557 | n8685)); - assign n4351 = ~n7214; - assign n7216 = (~n4896 & n6390) | (n4868 & (n4896 | n6390)); - assign n7217 = (~Ng11556 & ~n8682) | (~n7216 & (~Ng11556 | n8682)); - assign n4346 = ~n7217; - assign n7219 = (~n7216 & n8684) | (~Ng11555 & (~n7216 | ~n8684)); - assign n4341_1 = ~n7219; - assign n7221 = (~Ng11554 & ~n8685) | (~n7216 & (~Ng11554 | n8685)); - assign n4336_1 = ~n7221; - assign n7223 = (~Ng11553 & ~n8682) | (~n6186 & (~Ng11553 | n8682)); - assign n4331_1 = ~n7223; - assign n7225 = (~n6186 & n8684) | (~Ng11552 & (~n6186 | ~n8684)); - assign n4326 = ~n7225; - assign n7227 = (~Ng11551 & ~n8685) | (~n6186 & (~Ng11551 | n8685)); - assign n4321 = ~n7227; - assign n7229 = (~n8687 & n8688) | (~Ng1270 & (n8687 | n8688)); - assign n3481_1 = ~n7229; - assign n7231 = (n8688 & ~n8689) | (~Ng1272 & (n8688 | n8689)); - assign n3476_1 = ~n7231; - assign n7233 = (n8688 & ~n8690) | (~Ng1271 & (n8688 | n8690)); - assign n3471_1 = ~n7233; - assign n7235 = (n6561 & ~n8691) | (n4994 & (n6561 | n8691)); - assign n7236 = (~Ng1267 & n8687) | (~n7235 & (~Ng1267 | ~n8687)); - assign n3466_1 = ~n7236; - assign n7238_1 = (~n7235 & ~n8689) | (~Ng1269 & (~n7235 | n8689)); - assign n3461_1 = ~n7238_1; - assign n7240 = (~Ng1268 & n8690) | (~n7235 & (~Ng1268 | ~n8690)); - assign n3456_1 = ~n7240; - assign n7242_1 = (~n5004 & n8691) | (n4994 & (n5004 | n8691)); - assign n7243 = (~Ng1264 & n8687) | (~n7242_1 & (~Ng1264 | ~n8687)); - assign n3451_1 = ~n7243; - assign n7245 = (~n7242_1 & ~n8689) | (~Ng1266 & (~n7242_1 | n8689)); - assign n3446_1 = ~n7245; - assign n7247 = (~Ng1265 & n8690) | (~n7242_1 & (~Ng1265 | ~n8690)); - assign n3441_1 = ~n7247; - assign n7249 = (~Ng1261 & n8687) | (~n6189 & (~Ng1261 | ~n8687)); - assign n3436_1 = ~n7249; - assign n7251 = (~n6189 & ~n8689) | (~Ng1263 & (~n6189 | n8689)); - assign n3431_1 = ~n7251; - assign n7253 = (~Ng1262 & n8690) | (~n6189 & (~Ng1262 | ~n8690)); - assign n3426_1 = ~n7253; - assign n7255_1 = (n8693 & n8694) | (~Ng11535 & (~n8693 | n8694)); - assign n2869_1 = ~n7255_1; - assign n7257 = (n8694 & n8695) | (~Ng11534 & (n8694 | ~n8695)); - assign n2864_1 = ~n7257; - assign n7259 = (n8694 & n8696) | (~Ng11533 & (n8694 | ~n8696)); - assign n2859_1 = ~n7259; - assign n7261 = (n4826 | ~n6391_1) & ~n8766; - assign n7262 = (~Ng11532 & ~n8693) | (~n7261 & (~Ng11532 | n8693)); - assign n2854_1 = ~n7262; - assign n7264 = (~n7261 & n8695) | (~Ng11531 & (~n7261 | ~n8695)); - assign n2849_1 = ~n7264; - assign n7266 = (~Ng11530 & ~n8696) | (~n7261 & (~Ng11530 | n8696)); - assign n2844_1 = ~n7266; - assign n7268 = (~n4858 & n6391_1) | (n4826 & (n4858 | n6391_1)); - assign n7269 = (~Ng11529 & ~n8693) | (~n7268 & (~Ng11529 | n8693)); - assign n2839_1 = ~n7269; - assign n7271 = (~n7268 & n8695) | (~Ng11528 & (~n7268 | ~n8695)); - assign n2834_1 = ~n7271; - assign n7273 = (~Ng11527 & ~n8696) | (~n7268 & (~Ng11527 | n8696)); - assign n2829_1 = ~n7273; - assign n7275 = (~Ng11526 & ~n8693) | (~n6191_1 & (~Ng11526 | n8693)); - assign n2824_1 = ~n7275; - assign n7277 = (~n6191_1 & n8695) | (~Ng11525 & (~n6191_1 | ~n8695)); - assign n2819_1 = ~n7277; - assign n7279 = (~Ng11524 & ~n8696) | (~n6191_1 & (~Ng11524 | n8696)); - assign n2814_1 = ~n7279; - assign n7281 = (~n8698 & n8699) | (~Ng584 & (n8698 | n8699)); - assign n1975 = ~n7281; - assign n7283 = (n8699 & ~n8700) | (~Ng586 & (n8699 | n8700)); - assign n1970_1 = ~n7283; - assign n7285 = (n8699 & ~n8701) | (~Ng585 & (n8699 | n8701)); - assign n1965 = ~n7285; - assign n7287 = (n6565_1 & ~n8702) | (n4986 & (n6565_1 | n8702)); - assign n7288 = (~Ng581 & n8698) | (~n7287 & (~Ng581 | ~n8698)); - assign n1960_1 = ~n7288; - assign n7290 = (~n7287 & ~n8700) | (~Ng583 & (~n7287 | n8700)); - assign n1955 = ~n7290; - assign n7292 = (~Ng582 & n8701) | (~n7287 & (~Ng582 | ~n8701)); - assign n1950 = ~n7292; - assign n7294 = (~n4992 & n8702) | (n4986 & (n4992 | n8702)); - assign n7295 = (~Ng578 & n8698) | (~n7294 & (~Ng578 | ~n8698)); - assign n1945_1 = ~n7295; - assign n7297 = (~n7294 & ~n8700) | (~Ng580 & (~n7294 | n8700)); - assign n1940_1 = ~n7297; - assign n7299 = (~Ng579 & n8701) | (~n7294 & (~Ng579 | ~n8701)); - assign n1935_1 = ~n7299; - assign n7301 = (~Ng575 & n8698) | (~n6194 & (~Ng575 | ~n8698)); - assign n1930_1 = ~n7301; - assign n7303 = (~n6194 & ~n8700) | (~Ng577 & (~n6194 | n8700)); - assign n1925 = ~n7303; - assign n7305 = (~Ng576 & n8701) | (~n6194 & (~Ng576 | ~n8701)); - assign n1920_1 = ~n7305; - assign n7307 = (n8704 & n8705) | (~Ng11508 & (~n8704 | n8705)); - assign n1363_1 = ~n7307; - assign n7309 = (n8705 & n8706) | (~Ng11507 & (n8705 | ~n8706)); - assign n1358_1 = ~n7309; - assign n7311 = (n8705 & n8707) | (~Ng11506 & (n8705 | ~n8707)); - assign n1353 = ~n7311; - assign n7313 = (n4784 | ~n6392) & ~n8767; - assign n7314 = (~Ng11505 & ~n8704) | (~n7313 & (~Ng11505 | n8704)); - assign n1348 = ~n7314; - assign n7316 = (~n7313 & n8706) | (~Ng11504 & (~n7313 | ~n8706)); - assign n1343_1 = ~n7316; - assign n7318 = (~Ng11503 & ~n8707) | (~n7313 & (~Ng11503 | n8707)); - assign n1338_1 = ~n7318; - assign n7320 = (~n4816 & n6392) | (n4784 & (n4816 | n6392)); - assign n7321 = (~Ng11502 & ~n8704) | (~n7320 & (~Ng11502 | n8704)); - assign n1333_1 = ~n7321; - assign n7323 = (~n7320 & n8706) | (~Ng11501 & (~n7320 | ~n8706)); - assign n1328_1 = ~n7323; - assign n7325 = (~Ng11500 & ~n8707) | (~n7320 & (~Ng11500 | n8707)); - assign n1323_1 = ~n7325; - assign n7327 = (~Ng11499 & ~n8704) | (~n6196 & (~Ng11499 | n8704)); - assign n1318 = ~n7327; - assign n7329 = (~n6196 & n8706) | (~Ng11498 & (~n6196 | ~n8706)); - assign n1313 = ~n7329; - assign n7331 = (~Ng11497 & ~n8707) | (~n6196 & (~Ng11497 | n8707)); - assign n1308_1 = ~n7331; - assign n7333 = (Ng853 & n8709) | (~Ng2519 & (~Ng853 | n8709)); - assign n5958 = ~n7333; - assign n7335 = (\[1594] & n8709) | (~Ng2516 & (~\[1594] | n8709)); - assign n5953 = ~n7335; - assign n7337 = (\[1612] & n8709) | (~Ng2513 & (~\[1612] | n8709)); - assign n5948 = ~n7337; - assign n7339 = (Ng853 & n8710) | (~Ng2510 & (~Ng853 | n8710)); - assign n5943 = ~n7339; - assign n7341 = (\[1594] & n8710) | (~Ng2507 & (~\[1594] | n8710)); - assign n5938 = ~n7341; - assign n7343 = (\[1612] & n8710) | (~Ng2504 & (~\[1612] | n8710)); - assign n5933 = ~n7343; - assign n7345 = (Ng853 & n8711) | (~Ng1825 & (~Ng853 | n8711)); - assign n4451_1 = ~n7345; - assign n7347 = (\[1594] & n8711) | (~Ng1822 & (~\[1594] | n8711)); - assign n4446_1 = ~n7347; - assign n7349 = (\[1612] & n8711) | (~Ng1819 & (~\[1612] | n8711)); - assign n4441 = ~n7349; - assign n7351 = (Ng853 & n8712) | (~Ng1816 & (~Ng853 | n8712)); - assign n4436 = ~n7351; - assign n7353 = (\[1594] & n8712) | (~Ng1813 & (~\[1594] | n8712)); - assign n4431 = ~n7353; - assign n7355 = (\[1612] & n8712) | (~Ng1810 & (~\[1612] | n8712)); - assign n4426 = ~n7355; - assign n7357 = (Ng853 & n8713) | (~Ng1131 & (~Ng853 | n8713)); - assign n2944_1 = ~n7357; - assign n7359 = (\[1594] & n8713) | (~Ng1128 & (~\[1594] | n8713)); - assign n2939_1 = ~n7359; - assign n7361 = (\[1612] & n8713) | (~Ng1125 & (~\[1612] | n8713)); - assign n2934_1 = ~n7361; - assign n7363 = (Ng853 & n8714) | (~Ng1122 & (~Ng853 | n8714)); - assign n2929_1 = ~n7363; - assign n7365 = (\[1594] & n8714) | (~Ng1119 & (~\[1594] | n8714)); - assign n2924_1 = ~n7365; - assign n7367 = (\[1612] & n8714) | (~Ng1116 & (~\[1612] | n8714)); - assign n2919_1 = ~n7367; - assign n7369 = (Ng853 & n8715) | (~Ng444 & (~Ng853 | n8715)); - assign n1438_1 = ~n7369; - assign n7371 = (\[1594] & n8715) | (~Ng441 & (~\[1594] | n8715)); - assign n1433_1 = ~n7371; - assign n7373 = (\[1612] & n8715) | (~Ng438 & (~\[1612] | n8715)); - assign n1428_1 = ~n7373; - assign n7375 = (Ng853 & n8716) | (~Ng435 & (~Ng853 | n8716)); - assign n1423_1 = ~n7375; - assign n7377 = (\[1594] & n8716) | (~Ng432 & (~\[1594] | n8716)); - assign n1418_1 = ~n7377; - assign n7379 = (\[1612] & n8716) | (~Ng429 & (~\[1612] | n8716)); - assign n1413 = ~n7379; - assign n7381 = (Ng1315 & n8717) | (~Ng2571 & (~Ng1315 | n8717)); - assign n6570 = ~n7381; - assign n7383 = (\[1603] & n8717) | (~Ng2568 & (~\[1603] | n8717)); - assign n6565 = ~n7383; - assign n7385 = (\[1605] & n8717) | (~Ng2565 & (~\[1605] | n8717)); - assign n6560 = ~n7385; - assign n7387 = (~n8718 & n8719) | (~Ng2477 & (n8718 | n8719)); - assign n6048 = ~n7387; - assign n7389 = (n8719 & ~n8720) | (~Ng2479 & (n8719 | n8720)); - assign n6043 = ~n7389; - assign n7391 = (n8719 & ~n8721) | (~Ng2478 & (n8719 | n8721)); - assign n6038 = ~n7391; - assign n7393 = (Ng1315 & n8722) | (~Ng1877 & (~Ng1315 | n8722)); - assign n5063 = ~n7393; - assign n7395 = (\[1603] & n8722) | (~Ng1874 & (~\[1603] | n8722)); - assign n5058 = ~n7395; - assign n7397 = (\[1605] & n8722) | (~Ng1871 & (~\[1605] | n8722)); - assign n5053 = ~n7397; - assign n7399 = (~n8718 & n8723) | (~Ng1783 & (n8718 | n8723)); - assign n4541 = ~n7399; - assign n7401 = (~n8720 & n8723) | (~Ng1785 & (n8720 | n8723)); - assign n4536 = ~n7401; - assign n7403 = (~n8721 & n8723) | (~Ng1784 & (n8721 | n8723)); - assign n4531 = ~n7403; - assign n7405 = (Ng1315 & n8724) | (~Ng1183 & (~Ng1315 | n8724)); - assign n3556_1 = ~n7405; - assign n7407 = (\[1603] & n8724) | (~Ng1180 & (~\[1603] | n8724)); - assign n3551_1 = ~n7407; - assign n7409 = (\[1605] & n8724) | (~Ng1177 & (~\[1605] | n8724)); - assign n3546_1 = ~n7409; - assign n7411 = (~n8718 & n8725) | (~Ng1089 & (n8718 | n8725)); - assign n3034_1 = ~n7411; - assign n7413 = (~n8720 & n8725) | (~Ng1091 & (n8720 | n8725)); - assign n3029_1 = ~n7413; - assign n7415 = (~n8721 & n8725) | (~Ng1090 & (n8721 | n8725)); - assign n3024_1 = ~n7415; - assign n7417 = (Ng1315 & n8726) | (~Ng496 & (~Ng1315 | n8726)); - assign n2050_1 = ~n7417; - assign n7419 = (\[1603] & n8726) | (~Ng493 & (~\[1603] | n8726)); - assign n2045_1 = ~n7419; - assign n7421 = (\[1605] & n8726) | (~Ng490 & (~\[1605] | n8726)); - assign n2040 = ~n7421; - assign n7423 = (~n8718 & n8727) | (~Ng402 & (n8718 | n8727)); - assign n1528 = ~n7423; - assign n7425 = (~n8720 & n8727) | (~Ng404 & (n8720 | n8727)); - assign n1523_1 = ~n7425; - assign n7427 = (~n8721 & n8727) | (~Ng403 & (n8721 | n8727)); - assign n1518_1 = ~n7427; - assign n7429 = (Ng1315 & n6600) | (~Ng3099 & (~Ng1315 | n6600)); - assign n739_1 = ~n7429; - assign n7431 = (\[1603] & n6600) | (~Ng3098 & (~\[1603] | n6600)); - assign n734_1 = ~n7431; - assign n7433 = (\[1605] & n6600) | (~Ng3097 & (~\[1605] | n6600)); - assign n729 = ~n7433; - assign n7435 = (~n6234 & n8728) | (Pg3234 & (n6234 | n8728)); - assign n7106 = ~n7435; - assign n7437 = (~n5193 & ~Ng2808) | (~n5191 & (n5193 | ~Ng2808)); - assign n6892 = ~n7437; - assign n7439 = (~n5188 & ~Ng2810) | (~n5191 & (n5188 | ~Ng2810)); - assign n6887 = ~n7439; - assign n7441 = (~n5181 & ~Ng2809) | (~n5191 & (n5181 | ~Ng2809)); - assign n6882 = ~n7441; - assign n7443 = (~Ng2253 & n8729) | (n6149 & (~Ng2253 | ~n8729)); - assign n5610 = ~n7443; - assign n7445 = (n8730 & ~Ng2255) | (n6149 & (~n8730 | ~Ng2255)); - assign n5605 = ~n7445; - assign n7447 = (~Ng2254 & n8731) | (n6149 & (~Ng2254 | ~n8731)); - assign n5600 = ~n7447; - assign n7449 = (~Ng2250 & n8729) | (Ng2165 & (~Ng2250 | ~n8729)); - assign n5595 = ~n7449; - assign n7451 = (Ng2165 & ~n8730) | (~Ng2252 & (Ng2165 | n8730)); - assign n5590 = ~n7451; - assign n7453 = (~Ng2251 & n8731) | (Ng2165 & (~Ng2251 | ~n8731)); - assign n5585 = ~n7453; - assign n7455 = (~Ng2247 & n8729) | (Ng2170 & (~Ng2247 | ~n8729)); - assign n5580 = ~n7455; - assign n7457 = (Ng2170 & ~n8730) | (~Ng2249 & (Ng2170 | n8730)); - assign n5575 = ~n7457; - assign n7459 = (~Ng2248 & n8731) | (Ng2170 & (~Ng2248 | ~n8731)); - assign n5570 = ~n7459; - assign n7461 = (~n8729 & n8732) | (~Ng2244 & (n8729 | n8732)); - assign n5565 = ~n7461; - assign n7463 = (~n8730 & n8732) | (~Ng2246 & (n8730 | n8732)); - assign n5560 = ~n7463; - assign n7465 = (~n8731 & n8732) | (~Ng2245 & (n8731 | n8732)); - assign n5555 = ~n7465; - assign n7467 = (~n5186 & ~Ng2114) | (~n5184 & (n5186 | ~Ng2114)); - assign n5385 = ~n7467; - assign n7469 = (~n5178 & ~Ng2116) | (~n5184 & (n5178 | ~Ng2116)); - assign n5380 = ~n7469; - assign n7471 = (~n5171 & ~Ng2115) | (~n5184 & (n5171 | ~Ng2115)); - assign n5375 = ~n7471; - assign n7473 = (~Ng1559 & n8729) | (n6156 & (~Ng1559 | ~n8729)); - assign n4116_1 = ~n7473; - assign n7475 = (n8730 & ~Ng1561) | (n6156 & (~n8730 | ~Ng1561)); - assign n4111_1 = ~n7475; - assign n7477 = (~Ng1560 & n8731) | (n6156 & (~Ng1560 | ~n8731)); - assign n4106 = ~n7477; - assign n7479 = (~Ng1556 & n8729) | (Ng1471 & (~Ng1556 | ~n8729)); - assign n4101 = ~n7479; - assign n7481 = (Ng1471 & ~n8730) | (~Ng1558 & (Ng1471 | n8730)); - assign n4096_1 = ~n7481; - assign n7483 = (~Ng1557 & n8731) | (Ng1471 & (~Ng1557 | ~n8731)); - assign n4091 = ~n7483; - assign n7485 = (~Ng1553 & n8729) | (Ng1476 & (~Ng1553 | ~n8729)); - assign n4086_1 = ~n7485; - assign n7487 = (Ng1476 & ~n8730) | (~Ng1555 & (Ng1476 | n8730)); - assign n4081_1 = ~n7487; - assign n7489 = (~Ng1554 & n8731) | (Ng1476 & (~Ng1554 | ~n8731)); - assign n4076 = ~n7489; - assign n7491 = (~n8729 & n8733) | (~Ng1550 & (n8729 | n8733)); - assign n4071_1 = ~n7491; - assign n7493 = (~n8730 & n8733) | (~Ng1552 & (n8730 | n8733)); - assign n4066_1 = ~n7493; - assign n7495 = (~n8731 & n8733) | (~Ng1551 & (n8731 | n8733)); - assign n4061 = ~n7495; - assign n7497 = (~n5176 & ~Ng1420) | (~n5174 & (n5176 | ~Ng1420)); - assign n3891 = ~n7497; - assign n7499 = (~n5168 & ~Ng1422) | (~n5174 & (n5168 | ~Ng1422)); - assign n3886_1 = ~n7499; - assign n7501 = (~n5161 & ~Ng1421) | (~n5174 & (n5161 | ~Ng1421)); - assign n3881_1 = ~n7501; - assign n7503 = (~Ng865 & n8729) | (n6163_1 & (~Ng865 | ~n8729)); - assign n2609 = ~n7503; - assign n7505 = (n8730 & ~Ng867) | (n6163_1 & (~n8730 | ~Ng867)); - assign n2604 = ~n7505; - assign n7507 = (~Ng866 & n8731) | (n6163_1 & (~Ng866 | ~n8731)); - assign n2599_1 = ~n7507; - assign n7509 = (~Ng862 & n8729) | (Ng785 & (~Ng862 | ~n8729)); - assign n2594 = ~n7509; - assign n7511 = (Ng785 & ~n8730) | (~Ng864 & (Ng785 | n8730)); - assign n2589 = ~n7511; - assign n7513 = (~Ng863 & n8731) | (Ng785 & (~Ng863 | ~n8731)); - assign n2584_1 = ~n7513; - assign n7515 = (~Ng859 & n8729) | (Ng789 & (~Ng859 | ~n8729)); - assign n2579 = ~n7515; - assign n7517 = (Ng789 & ~n8730) | (~Ng861 & (Ng789 | n8730)); - assign n2574 = ~n7517; - assign n7519 = (~Ng860 & n8731) | (Ng789 & (~Ng860 | ~n8731)); - assign n2569 = ~n7519; - assign n7521 = (~n8729 & n8734) | (~Ng856 & (n8729 | n8734)); - assign n2564 = ~n7521; - assign n7523 = (~n8730 & n8734) | (~Ng858 & (n8730 | n8734)); - assign n2559 = ~n7523; - assign n7525 = (~n8731 & n8734) | (~Ng857 & (n8731 | n8734)); - assign n2554 = ~n7525; - assign n7527 = (~n5166 & ~Ng734) | (~n5164 & (n5166 | ~Ng734)); - assign n2372 = ~n7527; - assign n7529 = (~n5158 & ~Ng736) | (~n5164 & (n5158 | ~Ng736)); - assign n2367_1 = ~n7529; - assign n7531 = (~n5154 & ~Ng735) | (~n5164 & (n5154 | ~Ng735)); - assign n2362_1 = ~n7531; - assign n7533 = (~Ng177 & n8729) | (n6170 & (~Ng177 | ~n8729)); - assign n1103_1 = ~n7533; - assign n7535 = (n8730 & ~Ng179) | (n6170 & (~n8730 | ~Ng179)); - assign n1098_1 = ~n7535; - assign n7537 = (~Ng178 & n8731) | (n6170 & (~Ng178 | ~n8731)); - assign n1093_1 = ~n7537; - assign n7539 = (~Ng174 & n8729) | (Ng97 & (~Ng174 | ~n8729)); - assign n1088_1 = ~n7539; - assign n7541 = (Ng97 & ~n8730) | (~Ng176 & (Ng97 | n8730)); - assign n1083_1 = ~n7541; - assign n7543 = (~Ng175 & n8731) | (Ng97 & (~Ng175 | ~n8731)); - assign n1078_1 = ~n7543; - assign n7545 = (~Ng171 & n8729) | (Ng101 & (~Ng171 | ~n8729)); - assign n1073_1 = ~n7545; - assign n7547 = (~Ng173 & n8730) | (Ng101 & (~Ng173 | ~n8730)); - assign n1068_1 = ~n7547; - assign n7549 = (Ng101 & ~n8731) | (~Ng172 & (Ng101 | n8731)); - assign n1063 = ~n7549; - assign n7551 = (~n8729 & n8735) | (~Ng168 & (n8729 | n8735)); - assign n1058_1 = ~n7551; - assign n7553 = (~n8730 & n8735) | (~Ng170 & (n8730 | n8735)); - assign n1053 = ~n7553; - assign n7555 = (~n8731 & n8735) | (~Ng169 & (n8731 | n8735)); - assign n1048 = ~n7555; - assign n7557 = (Ng1315 & n8736) | (~Ng2676 & (~Ng1315 | n8736)); - assign n6525 = ~n7557; - assign n7559 = (\[1603] & n8736) | (~Ng2673 & (~\[1603] | n8736)); - assign n6520 = ~n7559; - assign n7561 = (\[1605] & n8736) | (~Ng2670 & (~\[1605] | n8736)); - assign n6515 = ~n7561; - assign n7563 = (Ng1315 & n8737) | (~Ng2667 & (~Ng1315 | n8737)); - assign n6510 = ~n7563; - assign n7565 = (\[1603] & n8737) | (~Ng2664 & (~\[1603] | n8737)); - assign n6505 = ~n7565; - assign n7567 = (\[1605] & n8737) | (~Ng2661 & (~\[1605] | n8737)); - assign n6500 = ~n7567; - assign n7569 = (~Pg3229 & ~Ng2380) | (Ng2366 & (Pg3229 | ~Ng2380)); - assign n6632 = ~n7569; - assign n7571 = (Ng2160 & ~n8738) | (n6242 & (~Ng2160 | ~n8738)); - assign n5765 = ~n7571; - assign n7573 = (Ng1315 & n8739) | (~Ng1982 & (~Ng1315 | n8739)); - assign n5018 = ~n7573; - assign n7575 = (\[1603] & n8739) | (~Ng1979 & (~\[1603] | n8739)); - assign n5013 = ~n7575; - assign n7577 = (\[1605] & n8739) | (~Ng1976 & (~\[1605] | n8739)); - assign n5008 = ~n7577; - assign n7579 = (Ng1315 & n8740) | (~Ng1973 & (~Ng1315 | n8740)); - assign n5003 = ~n7579; - assign n7581 = (\[1603] & n8740) | (~Ng1970 & (~\[1603] | n8740)); - assign n4998 = ~n7581; - assign n7583 = (\[1605] & n8740) | (~Ng1967 & (~\[1605] | n8740)); - assign n4993 = ~n7583; - assign n7585 = (~Pg3229 & ~Ng1686) | (Ng1672 & (Pg3229 | ~Ng1686)); - assign n5125 = ~n7585; - assign n7587 = (Ng1466 & ~n8738) | (n6242 & (~Ng1466 | ~n8738)); - assign n4271 = ~n7587; - assign n7589 = (Ng1315 & n8741) | (~Ng1288 & (~Ng1315 | n8741)); - assign n3511_1 = ~n7589; - assign n7591 = (\[1603] & n8741) | (~Ng1285 & (~\[1603] | n8741)); - assign n3506_1 = ~n7591; - assign n7593 = (\[1605] & n8741) | (~Ng1282 & (~\[1605] | n8741)); - assign n3501_1 = ~n7593; - assign n7595 = (Ng1315 & n8742) | (~Ng1279 & (~Ng1315 | n8742)); - assign n3496_1 = ~n7595; - assign n7597 = (\[1603] & n8742) | (~Ng1276 & (~\[1603] | n8742)); - assign n3491_1 = ~n7597; - assign n7599 = (\[1605] & n8742) | (~Ng1273 & (~\[1605] | n8742)); - assign n3486_1 = ~n7599; - assign n7601 = (~Pg3229 & ~Ng992) | (Ng978 & (Pg3229 | ~Ng992)); - assign n3618_1 = ~n7601; - assign n7603 = (Ng780 & ~n8738) | (n6242 & (~Ng780 | ~n8738)); - assign n2764_1 = ~n7603; - assign n7605 = (Ng1315 & n8743) | (~Ng602 & (~Ng1315 | n8743)); - assign n2005_1 = ~n7605; - assign n7607 = (\[1603] & n8743) | (~Ng599 & (~\[1603] | n8743)); - assign n2000_1 = ~n7607; - assign n7609 = (\[1605] & n8743) | (~Ng596 & (~\[1605] | n8743)); - assign n1995_1 = ~n7609; - assign n7611 = (Ng1315 & n8744) | (~Ng593 & (~Ng1315 | n8744)); - assign n1990_1 = ~n7611; - assign n7613 = (\[1603] & n8744) | (~Ng590 & (~\[1603] | n8744)); - assign n1985 = ~n7613; - assign n7615 = (\[1605] & n8744) | (~Ng587 & (~\[1605] | n8744)); - assign n1980 = ~n7615; - assign n7617 = (~Pg3229 & ~Ng305) | (Ng291 & (Pg3229 | ~Ng305)); - assign n2112 = ~n7617; - assign n7619 = (Ng92 & ~n8738) | (n6242 & (~Ng92 | ~n8738)); - assign n1258_1 = ~n7619; - assign n7621 = ~n8746 & (~Ng3147 | n6537 | ~Ng3097); - assign n7622 = (~\[1612] & ~Ng11593) | (n5137 & (\[1612] | ~Ng11593)); - assign n6341 = ~n7622; - assign n7624 = (~Ng853 & ~Ng2554) | (n5990 & (Ng853 | ~Ng2554)); - assign n6363 = ~n7624; - assign n7626 = (\[1594] & n5990) | (~Ng2553 & (~\[1594] | n5990)); - assign n6358 = ~n7626; - assign n7628 = (~\[1612] & ~Ng2552) | (n5990 & (\[1612] | ~Ng2552)); - assign n6353 = ~n7628; - assign n7630 = (~Ng853 & ~Ng11595) | (n6219_1 & (Ng853 | ~Ng11595)); - assign n6391 = ~n7630; - assign n7632 = (~\[1594] & ~Ng11594) | (n6219_1 & (\[1594] | ~Ng11594)); - assign n6387 = ~n7632; - assign n7634 = (~\[1612] & ~Ng11598) | (n6219_1 & (\[1612] | ~Ng11598)); - assign n6383 = ~n7634; - assign n7636 = (~Ng853 & ~Ng11597) | (n5137 & (Ng853 | ~Ng11597)); - assign n6349 = ~n7636; - assign n7638 = (~\[1594] & ~Ng11596) | (n5137 & (\[1594] | ~Ng11596)); - assign n6345 = ~n7638; - assign n7640 = (~\[1612] & ~Ng11566) | (n5135_1 & (\[1612] | ~Ng11566)); - assign n4834 = ~n7640; - assign n7642 = (~Ng853 & ~Ng1860) | (n5998_1 & (Ng853 | ~Ng1860)); - assign n4856 = ~n7642; - assign n7644 = (\[1594] & n5998_1) | (~Ng1859 & (~\[1594] | n5998_1)); - assign n4851 = ~n7644; - assign n7646 = (~\[1612] & ~Ng1858) | (n5998_1 & (\[1612] | ~Ng1858)); - assign n4846 = ~n7646; - assign n7648 = (~Ng853 & ~Ng11568) | (n6223_1 & (Ng853 | ~Ng11568)); - assign n4884 = ~n7648; - assign n7650 = (~\[1594] & ~Ng11567) | (n6223_1 & (\[1594] | ~Ng11567)); - assign n4880 = ~n7650; - assign n7652 = (~\[1612] & ~Ng11571) | (n6223_1 & (\[1612] | ~Ng11571)); - assign n4876 = ~n7652; - assign n7654 = (~Ng853 & ~Ng11570) | (n5135_1 & (Ng853 | ~Ng11570)); - assign n4842 = ~n7654; - assign n7656 = (~\[1594] & ~Ng11569) | (n5135_1 & (\[1594] | ~Ng11569)); - assign n4838 = ~n7656; - assign n7658 = (~\[1612] & ~Ng11539) | (n5131 & (\[1612] | ~Ng11539)); - assign n3327_1 = ~n7658; - assign n7660 = (~Ng853 & ~Ng1166) | (n6006 & (Ng853 | ~Ng1166)); - assign n3349_1 = ~n7660; - assign n7662 = (\[1594] & n6006) | (~Ng1165 & (~\[1594] | n6006)); - assign n3344_1 = ~n7662; - assign n7664 = (~\[1612] & ~Ng1164) | (n6006 & (\[1612] | ~Ng1164)); - assign n3339_1 = ~n7664; - assign n7666 = (~Ng853 & ~Ng11541) | (n6227_1 & (Ng853 | ~Ng11541)); - assign n3377_1 = ~n7666; - assign n7668 = (~\[1594] & ~Ng11540) | (n6227_1 & (\[1594] | ~Ng11540)); - assign n3373_1 = ~n7668; - assign n7670 = (~\[1612] & ~Ng11544) | (n6227_1 & (\[1612] | ~Ng11544)); - assign n3369_1 = ~n7670; - assign n7672 = (~Ng853 & ~Ng11543) | (n5131 & (Ng853 | ~Ng11543)); - assign n3335_1 = ~n7672; - assign n7674 = (~\[1594] & ~Ng11542) | (n5131 & (\[1594] | ~Ng11542)); - assign n3331_1 = ~n7674; - assign n7676 = (~\[1612] & ~Ng11512) | (n5126 & (\[1612] | ~Ng11512)); - assign n1821_1 = ~n7676; - assign n7678 = (~Ng853 & ~Ng479) | (n6014 & (Ng853 | ~Ng479)); - assign n1843_1 = ~n7678; - assign n7680 = (\[1594] & n6014) | (~Ng478 & (~\[1594] | n6014)); - assign n1838 = ~n7680; - assign n7682 = (~\[1612] & ~Ng477) | (n6014 & (\[1612] | ~Ng477)); - assign n1833 = ~n7682; - assign n7684 = (~Ng853 & ~Ng11514) | (n6231_1 & (Ng853 | ~Ng11514)); - assign n1871_1 = ~n7684; - assign n7686 = (~\[1594] & ~Ng11513) | (n6231_1 & (\[1594] | ~Ng11513)); - assign n1867_1 = ~n7686; - assign n7688 = (~\[1612] & ~Ng11517) | (n6231_1 & (\[1612] | ~Ng11517)); - assign n1863 = ~n7688; - assign n7690 = (~Ng853 & ~Ng11516) | (n5126 & (Ng853 | ~Ng11516)); - assign n1829 = ~n7690; - assign n7692 = (~\[1594] & ~Ng11515) | (n5126 & (\[1594] | ~Ng11515)); - assign n1825_1 = ~n7692; - assign n7694 = (~Ng853 & ~Ng2563) | (n4908 & (Ng853 | ~Ng2563)); - assign n6336 = ~n7694; - assign n7696 = (\[1594] & n4908) | (~Ng2562 & (~\[1594] | n4908)); - assign n6331 = ~n7696; - assign n7698 = (~\[1612] & ~Ng2561) | (n4908 & (\[1612] | ~Ng2561)); - assign n6326 = ~n7698; - assign n7700 = (~Ng853 & ~Ng2539) | (~n5034 & (Ng853 | ~Ng2539)); - assign n6378 = ~n7700; - assign n7702 = (\[1594] & ~n5034) | (~Ng2559 & (~\[1594] | ~n5034)); - assign n6373 = ~n7702; - assign n7704 = (~\[1612] & ~Ng2555) | (~n5034 & (\[1612] | ~Ng2555)); - assign n6368 = ~n7704; - assign n7706 = (n6521 & ~Ng2238) | (~n5044 & (~n6521 | ~Ng2238)); - assign n5550 = ~n7706; - assign n7708 = (~n5044 & ~n8747) | (~Ng2240 & (~n5044 | n8747)); - assign n5545 = ~n7708; - assign n7710 = (~Ng2239 & n8748) | (~n5044 & (~Ng2239 | ~n8748)); - assign n5540 = ~n7710; - assign n7712 = (n6521 & ~Ng2235) | (~n5046 & (~n6521 | ~Ng2235)); - assign n5535 = ~n7712; - assign n7714 = (~n5046 & ~n8747) | (~Ng2237 & (~n5046 | n8747)); - assign n5530 = ~n7714; - assign n7716 = (~Ng2236 & n8748) | (~n5046 & (~Ng2236 | ~n8748)); - assign n5525 = ~n7716; - assign n7718 = (n6521 & ~Ng2232) | (Ng2200 & (~n6521 | ~Ng2232)); - assign n5520 = ~n7718; - assign n7720 = (Ng2200 & ~n8747) | (~Ng2234 & (Ng2200 | n8747)); - assign n5515 = ~n7720; - assign n7722 = (~Ng2233 & n8748) | (Ng2200 & (~Ng2233 | ~n8748)); - assign n5510 = ~n7722; - assign n7724 = (n6521 & ~Ng2229) | (Ng2195 & (~n6521 | ~Ng2229)); - assign n5505 = ~n7724; - assign n7726 = (Ng2195 & ~n8747) | (~Ng2231 & (Ng2195 | n8747)); - assign n5500 = ~n7726; - assign n7728 = (~Ng2230 & n8748) | (Ng2195 & (~Ng2230 | ~n8748)); - assign n5495 = ~n7728; - assign n7730 = (n6521 & ~Ng2226) | (Ng2190 & (~n6521 | ~Ng2226)); - assign n5490 = ~n7730; - assign n7732 = (Ng2190 & ~n8747) | (~Ng2228 & (Ng2190 | n8747)); - assign n5485 = ~n7732; - assign n7734 = (~Ng2227 & n8748) | (Ng2190 & (~Ng2227 | ~n8748)); - assign n5480 = ~n7734; - assign n7736 = (n6521 & ~Ng2223) | (Ng2185 & (~n6521 | ~Ng2223)); - assign n5475 = ~n7736; - assign n7738 = (Ng2185 & ~n8747) | (~Ng2225 & (Ng2185 | n8747)); - assign n5470 = ~n7738; - assign n7740 = (~Ng2224 & n8748) | (Ng2185 & (~Ng2224 | ~n8748)); - assign n5465 = ~n7740; - assign n7742 = (n6521 & ~Ng2220) | (Ng2180 & (~n6521 | ~Ng2220)); - assign n5460 = ~n7742; - assign n7744 = (Ng2180 & ~n8747) | (~Ng2222 & (Ng2180 | n8747)); - assign n5455 = ~n7744; - assign n7746 = (~Ng2221 & n8748) | (Ng2180 & (~Ng2221 | ~n8748)); - assign n5450 = ~n7746; - assign n7748 = (n6521 & ~Ng2217) | (Ng2175 & (~n6521 | ~Ng2217)); - assign n5445 = ~n7748; - assign n7750 = (~Ng2219 & n8747) | (Ng2175 & (~Ng2219 | ~n8747)); - assign n5440 = ~n7750; - assign n7752 = (Ng2175 & ~n8748) | (~Ng2218 & (Ng2175 | n8748)); - assign n5435 = ~n7752; - assign n7754 = (n6521 & ~Ng2208) | (Ng2170 & (~n6521 | ~Ng2208)); - assign n5430 = ~n7754; - assign n7756 = (Ng2170 & ~n8747) | (~Ng2210 & (Ng2170 | n8747)); - assign n5425 = ~n7756; - assign n7758 = (~Ng2209 & n8748) | (Ng2170 & (~Ng2209 | ~n8748)); - assign n5420 = ~n7758; - assign n7760 = (n6521 & ~Ng2205) | (Ng2165 & (~n6521 | ~Ng2205)); - assign n5415 = ~n7760; - assign n7762 = (Ng2165 & ~n8747) | (~Ng2207 & (Ng2165 | n8747)); - assign n5410 = ~n7762; - assign n7764 = (~Ng2206 & n8748) | (Ng2165 & (~Ng2206 | ~n8748)); - assign n5405 = ~n7764; - assign n7766 = (~Ng853 & ~Ng1869) | (n4870 & (Ng853 | ~Ng1869)); - assign n4829 = ~n7766; - assign n7768 = (\[1594] & n4870) | (~Ng1868 & (~\[1594] | n4870)); - assign n4824 = ~n7768; - assign n7770 = (~\[1612] & ~Ng1867) | (n4870 & (\[1612] | ~Ng1867)); - assign n4819 = ~n7770; - assign n7772 = (~Ng853 & ~Ng1845) | (~n5022 & (Ng853 | ~Ng1845)); - assign n4871_1 = ~n7772; - assign n7774 = (\[1594] & ~n5022) | (~Ng1865 & (~\[1594] | ~n5022)); - assign n4866 = ~n7774; - assign n7776 = (~\[1612] & ~Ng1861) | (~n5022 & (\[1612] | ~Ng1861)); - assign n4861 = ~n7776; - assign n7778 = (n6521 & ~Ng1544) | (~n5040 & (~n6521 | ~Ng1544)); - assign n4056 = ~n7778; - assign n7780 = (~n5040 & ~n8747) | (~Ng1546 & (~n5040 | n8747)); - assign n4051 = ~n7780; - assign n7782 = (~Ng1545 & n8748) | (~n5040 & (~Ng1545 | ~n8748)); - assign n4046 = ~n7782; - assign n7784 = (n6521 & ~Ng1541) | (~n5042 & (~n6521 | ~Ng1541)); - assign n4041_1 = ~n7784; - assign n7786 = (~n5042 & ~n8747) | (~Ng1543 & (~n5042 | n8747)); - assign n4036 = ~n7786; - assign n7788 = (~Ng1542 & n8748) | (~n5042 & (~Ng1542 | ~n8748)); - assign n4031_1 = ~n7788; - assign n7790 = (n6521 & ~Ng1538) | (Ng1506 & (~n6521 | ~Ng1538)); - assign n4026 = ~n7790; - assign n7792 = (Ng1506 & ~n8747) | (~Ng1540 & (Ng1506 | n8747)); - assign n4021 = ~n7792; - assign n7794 = (~Ng1539 & n8748) | (Ng1506 & (~Ng1539 | ~n8748)); - assign n4016_1 = ~n7794; - assign n7796 = (n6521 & ~Ng1535) | (Ng1501 & (~n6521 | ~Ng1535)); - assign n4011_1 = ~n7796; - assign n7798 = (Ng1501 & ~n8747) | (~Ng1537 & (Ng1501 | n8747)); - assign n4006_1 = ~n7798; - assign n7800 = (~Ng1536 & n8748) | (Ng1501 & (~Ng1536 | ~n8748)); - assign n4001_1 = ~n7800; - assign n7802 = (n6521 & ~Ng1532) | (Ng1496 & (~n6521 | ~Ng1532)); - assign n3996_1 = ~n7802; - assign n7804 = (Ng1496 & ~n8747) | (~Ng1534 & (Ng1496 | n8747)); - assign n3991 = ~n7804; - assign n7806 = (~Ng1533 & n8748) | (Ng1496 & (~Ng1533 | ~n8748)); - assign n3986 = ~n7806; - assign n7808 = (n6521 & ~Ng1529) | (Ng1491 & (~n6521 | ~Ng1529)); - assign n3981 = ~n7808; - assign n7810 = (Ng1491 & ~n8747) | (~Ng1531 & (Ng1491 | n8747)); - assign n3976 = ~n7810; - assign n7812 = (~Ng1530 & n8748) | (Ng1491 & (~Ng1530 | ~n8748)); - assign n3971 = ~n7812; - assign n7814 = (n6521 & ~Ng1526) | (Ng1486 & (~n6521 | ~Ng1526)); - assign n3966 = ~n7814; - assign n7816 = (~Ng1528 & n8747) | (Ng1486 & (~Ng1528 | ~n8747)); - assign n3961_1 = ~n7816; - assign n7818 = (Ng1486 & ~n8748) | (~Ng1527 & (Ng1486 | n8748)); - assign n3956 = ~n7818; - assign n7820 = (n6521 & ~Ng1523) | (Ng1481 & (~n6521 | ~Ng1523)); - assign n3951 = ~n7820; - assign n7822 = (~Ng1525 & n8747) | (Ng1481 & (~Ng1525 | ~n8747)); - assign n3946 = ~n7822; - assign n7824 = (Ng1481 & ~n8748) | (~Ng1524 & (Ng1481 | n8748)); - assign n3941_1 = ~n7824; - assign n7826 = (n6521 & ~Ng1514) | (Ng1476 & (~n6521 | ~Ng1514)); - assign n3936 = ~n7826; - assign n7828 = (Ng1476 & ~n8747) | (~Ng1516 & (Ng1476 | n8747)); - assign n3931 = ~n7828; - assign n7830 = (~Ng1515 & n8748) | (Ng1476 & (~Ng1515 | ~n8748)); - assign n3926_1 = ~n7830; - assign n7832 = (n6521 & ~Ng1511) | (Ng1471 & (~n6521 | ~Ng1511)); - assign n3921 = ~n7832; - assign n7834 = (Ng1471 & ~n8747) | (~Ng1513 & (Ng1471 | n8747)); - assign n3916_1 = ~n7834; - assign n7836 = (~Ng1512 & n8748) | (Ng1471 & (~Ng1512 | ~n8748)); - assign n3911 = ~n7836; - assign n7838 = (~Ng853 & ~Ng1175) | (n4828 & (Ng853 | ~Ng1175)); - assign n3322_1 = ~n7838; - assign n7840 = (\[1594] & n4828) | (~Ng1174 & (~\[1594] | n4828)); - assign n3317_1 = ~n7840; - assign n7842 = (~\[1612] & ~Ng1173) | (n4828 & (\[1612] | ~Ng1173)); - assign n3312_1 = ~n7842; - assign n7844 = (~Ng853 & ~Ng1151) | (~n5010 & (Ng853 | ~Ng1151)); - assign n3364_1 = ~n7844; - assign n7846 = (\[1594] & ~n5010) | (~Ng1171 & (~\[1594] | ~n5010)); - assign n3359_1 = ~n7846; - assign n7848 = (~\[1612] & ~Ng1167) | (~n5010 & (\[1612] | ~Ng1167)); - assign n3354_1 = ~n7848; - assign n7850 = (n6521 & ~Ng850) | (~n5032 & (~n6521 | ~Ng850)); - assign n2549 = ~n7850; - assign n7852 = (~n5032 & ~n8747) | (~Ng852 & (~n5032 | n8747)); - assign n2544 = ~n7852; - assign n7854 = (~Ng851 & n8748) | (~n5032 & (~Ng851 | ~n8748)); - assign n2539 = ~n7854; - assign n7856 = (n6521 & ~Ng847) | (~n5038_1 & (~n6521 | ~Ng847)); - assign n2534_1 = ~n7856; - assign n7858 = (~n5038_1 & ~n8747) | (~Ng849 & (~n5038_1 | n8747)); - assign n2529 = ~n7858; - assign n7860 = (~Ng848 & n8748) | (~n5038_1 & (~Ng848 | ~n8748)); - assign n2524_1 = ~n7860; - assign n7862 = (n6521 & ~Ng844) | (Ng813 & (~n6521 | ~Ng844)); - assign n2519_1 = ~n7862; - assign n7864 = (Ng813 & ~n8747) | (~Ng846 & (Ng813 | n8747)); - assign n2514_1 = ~n7864; - assign n7866 = (~Ng845 & n8748) | (Ng813 & (~Ng845 | ~n8748)); - assign n2509 = ~n7866; - assign n7868 = (n6521 & ~Ng841) | (Ng809 & (~n6521 | ~Ng841)); - assign n2504_1 = ~n7868; - assign n7870 = (Ng809 & ~n8747) | (~Ng843 & (Ng809 | n8747)); - assign n2499_1 = ~n7870; - assign n7872 = (~Ng842 & n8748) | (Ng809 & (~Ng842 | ~n8748)); - assign n2494 = ~n7872; - assign n7874 = (n6521 & ~Ng838) | (Ng805 & (~n6521 | ~Ng838)); - assign n2489_1 = ~n7874; - assign n7876 = (Ng805 & ~n8747) | (~Ng840 & (Ng805 | n8747)); - assign n2484 = ~n7876; - assign n7878 = (~Ng839 & n8748) | (Ng805 & (~Ng839 | ~n8748)); - assign n2479 = ~n7878; - assign n7880 = (n6521 & ~Ng835) | (Ng801 & (~n6521 | ~Ng835)); - assign n2474 = ~n7880; - assign n7882 = (~Ng837 & n8747) | (Ng801 & (~Ng837 | ~n8747)); - assign n2469 = ~n7882; - assign n7884 = (Ng801 & ~n8748) | (~Ng836 & (Ng801 | n8748)); - assign n2464 = ~n7884; - assign n7886 = (n6521 & ~Ng832) | (Ng797 & (~n6521 | ~Ng832)); - assign n2459 = ~n7886; - assign n7888 = (~Ng834 & n8747) | (Ng797 & (~Ng834 | ~n8747)); - assign n2454 = ~n7888; - assign n7890 = (Ng797 & ~n8748) | (~Ng833 & (Ng797 | n8748)); - assign n2449 = ~n7890; - assign n7892 = (n6521 & ~Ng829) | (Ng793 & (~n6521 | ~Ng829)); - assign n2444_1 = ~n7892; - assign n7894 = (~Ng831 & n8747) | (Ng793 & (~Ng831 | ~n8747)); - assign n2439 = ~n7894; - assign n7896 = (Ng793 & ~n8748) | (~Ng830 & (Ng793 | n8748)); - assign n2434 = ~n7896; - assign n7898 = (n6521 & ~Ng820) | (Ng789 & (~n6521 | ~Ng820)); - assign n2429_1 = ~n7898; - assign n7900 = (Ng789 & ~n8747) | (~Ng822 & (Ng789 | n8747)); - assign n2424_1 = ~n7900; - assign n7902 = (~Ng821 & n8748) | (Ng789 & (~Ng821 | ~n8748)); - assign n2419 = ~n7902; - assign n7904 = (n6521 & ~Ng817) | (Ng785 & (~n6521 | ~Ng817)); - assign n2414 = ~n7904; - assign n7906 = (Ng785 & ~n8747) | (~Ng819 & (Ng785 | n8747)); - assign n2409 = ~n7906; - assign n7908 = (~Ng818 & n8748) | (Ng785 & (~Ng818 | ~n8748)); - assign n2404 = ~n7908; - assign n7910 = (~Ng853 & ~Ng488) | (n4786 & (Ng853 | ~Ng488)); - assign n1816_1 = ~n7910; - assign n7912 = (\[1594] & n4786) | (~Ng487 & (~\[1594] | n4786)); - assign n1811_1 = ~n7912; - assign n7914 = (~\[1612] & ~Ng486) | (n4786 & (\[1612] | ~Ng486)); - assign n1806_1 = ~n7914; - assign n7916 = (~Ng853 & ~Ng464) | (~n4998_1 & (Ng853 | ~Ng464)); - assign n1858_1 = ~n7916; - assign n7918 = (\[1594] & ~n4998_1) | (~Ng484 & (~\[1594] | ~n4998_1)); - assign n1853_1 = ~n7918; - assign n7920 = (~\[1612] & ~Ng480) | (~n4998_1 & (\[1612] | ~Ng480)); - assign n1848 = ~n7920; - assign n7922 = (n6521 & ~Ng162) | (~n5020 & (~n6521 | ~Ng162)); - assign n1043_1 = ~n7922; - assign n7924 = (~n5020 & ~n8747) | (~Ng164 & (~n5020 | n8747)); - assign n1038_1 = ~n7924; - assign n7926 = (~Ng163 & n8748) | (~n5020 & (~Ng163 | ~n8748)); - assign n1033 = ~n7926; - assign n7928 = (n6521 & ~Ng159) | (~n5030 & (~n6521 | ~Ng159)); - assign n1028_1 = ~n7928; - assign n7930 = (~n5030 & ~n8747) | (~Ng161 & (~n5030 | n8747)); - assign n1023_1 = ~n7930; - assign n7932 = (~Ng160 & n8748) | (~n5030 & (~Ng160 | ~n8748)); - assign n1018 = ~n7932; - assign n7934 = (n6521 & ~Ng156) | (Ng125 & (~n6521 | ~Ng156)); - assign n1013_1 = ~n7934; - assign n7936 = (Ng125 & ~n8747) | (~Ng158 & (Ng125 | n8747)); - assign n1008_1 = ~n7936; - assign n7938 = (~Ng157 & n8748) | (Ng125 & (~Ng157 | ~n8748)); - assign n1003 = ~n7938; - assign n7940 = (n6521 & ~Ng153) | (Ng121 & (~n6521 | ~Ng153)); - assign n998 = ~n7940; - assign n7942 = (Ng121 & ~n8747) | (~Ng155 & (Ng121 | n8747)); - assign n993_1 = ~n7942; - assign n7944 = (~Ng154 & n8748) | (Ng121 & (~Ng154 | ~n8748)); - assign n988_1 = ~n7944; - assign n7946 = (n6521 & ~Ng150) | (Ng117 & (~n6521 | ~Ng150)); - assign n983_1 = ~n7946; - assign n7948 = (~Ng152 & n8747) | (Ng117 & (~Ng152 | ~n8747)); - assign n978_1 = ~n7948; - assign n7950 = (Ng117 & ~n8748) | (~Ng151 & (Ng117 | n8748)); - assign n973_1 = ~n7950; - assign n7952 = (n6521 & ~Ng147) | (Ng113 & (~n6521 | ~Ng147)); - assign n968_1 = ~n7952; - assign n7954 = (~Ng149 & n8747) | (Ng113 & (~Ng149 | ~n8747)); - assign n963_1 = ~n7954; - assign n7956 = (Ng113 & ~n8748) | (~Ng148 & (Ng113 | n8748)); - assign n958 = ~n7956; - assign n7958 = (n6521 & ~Ng144) | (Ng109 & (~n6521 | ~Ng144)); - assign n953_1 = ~n7958; - assign n7960 = (~Ng146 & n8747) | (Ng109 & (~Ng146 | ~n8747)); - assign n948_1 = ~n7960; - assign n7962 = (Ng109 & ~n8748) | (~Ng145 & (Ng109 | n8748)); - assign n943_1 = ~n7962; - assign n7964 = (n6521 & ~Ng141) | (Ng105 & (~n6521 | ~Ng141)); - assign n938_1 = ~n7964; - assign n7966 = (~Ng143 & n8747) | (Ng105 & (~Ng143 | ~n8747)); - assign n933_1 = ~n7966; - assign n7968 = (Ng105 & ~n8748) | (~Ng142 & (Ng105 | n8748)); - assign n928 = ~n7968; - assign n7970 = (n6521 & ~Ng132) | (Ng101 & (~n6521 | ~Ng132)); - assign n923_1 = ~n7970; - assign n7972 = (Ng101 & ~n8747) | (~Ng134 & (Ng101 | n8747)); - assign n918_1 = ~n7972; - assign n7974 = (~Ng133 & n8748) | (Ng101 & (~Ng133 | ~n8748)); - assign n913_1 = ~n7974; - assign n7976 = (n6521 & ~Ng129) | (Ng97 & (~n6521 | ~Ng129)); - assign n908_1 = ~n7976; - assign n7978 = (Ng97 & ~n8747) | (~Ng131 & (Ng97 | n8747)); - assign n903_1 = ~n7978; - assign n7980 = (~Ng130 & n8748) | (Ng97 & (~Ng130 | ~n8748)); - assign n898_1 = ~n7980; - assign n7982 = (~Ng2879 & n8749) | (~Pg8096 & (Ng2879 | n8749)); - assign n616 = ~n7982; - assign n7984 = (Ng2879 & ~n8763) | (~Ng13455 & (~Ng2879 | ~n8763)); - assign n664_1 = ~n7984; - assign n7986 = (~Ng2879 & ~Ng13439) | (n8749 & (Ng2879 | ~Ng13439)); - assign n475_1 = ~n7986; - assign n7988 = (~Ng2879 & ~n8763) | (~Pg7519 & (Ng2879 | ~n8763)); - assign n544_1 = ~n7988; - assign n7990 = (n5192 & ~Ng2805) | (~n5064 & (~n5192 | ~Ng2805)); - assign n6877 = ~n7990; - assign n7992 = (~n5064 & ~n5115_1) | (~Ng2807 & (~n5064 | n5115_1)); - assign n6872 = ~n7992; - assign n7994 = (n5180_1 & ~Ng2806) | (~n5064 & (~n5180_1 | ~Ng2806)); - assign n6867 = ~n7994; - assign n7996 = (n5192 & ~Ng2802) | (~n4982 & (~n5192 | ~Ng2802)); - assign n6862 = ~n7996; - assign n7998 = (n5115_1 & ~Ng2804) | (~n4982 & (~n5115_1 | ~Ng2804)); - assign n6857 = ~n7998; - assign n8000 = (n5180_1 & ~Ng2803) | (~n4982 & (~n5180_1 | ~Ng2803)); - assign n6852 = ~n8000; - assign n8002 = (~n5193 & ~Ng2799) | (Ng2766 & (n5193 | ~Ng2799)); - assign n6847 = ~n8002; - assign n8004 = (n5188 & Ng2766) | (~Ng2801 & (~n5188 | Ng2766)); - assign n6842 = ~n8004; - assign n8006 = (~n5181 & ~Ng2800) | (Ng2766 & (n5181 | ~Ng2800)); - assign n6837 = ~n8006; - assign n8008 = (~n5193 & ~Ng2796) | (Ng2760 & (n5193 | ~Ng2796)); - assign n6832 = ~n8008; - assign n8010 = (n5188 & Ng2760) | (~Ng2798 & (~n5188 | Ng2760)); - assign n6827 = ~n8010; - assign n8012 = (~n5181 & ~Ng2797) | (Ng2760 & (n5181 | ~Ng2797)); - assign n6822 = ~n8012; - assign n8014 = (~n5193 & ~Ng2793) | (Ng2753 & (n5193 | ~Ng2793)); - assign n6817 = ~n8014; - assign n8016 = (n5188 & Ng2753) | (~Ng2795 & (~n5188 | Ng2753)); - assign n6812 = ~n8016; - assign n8018 = (~n5181 & ~Ng2794) | (Ng2753 & (n5181 | ~Ng2794)); - assign n6807 = ~n8018; - assign n8020 = (~n5193 & ~Ng2790) | (Ng2740 & (n5193 | ~Ng2790)); - assign n6802 = ~n8020; - assign n8022 = (n5188 & Ng2740) | (~Ng2792 & (~n5188 | Ng2740)); - assign n6797 = ~n8022; - assign n8024 = (~n5181 & ~Ng2791) | (Ng2740 & (n5181 | ~Ng2791)); - assign n6792 = ~n8024; - assign n8026 = (~n5193 & ~Ng2787) | (Ng2746 & (n5193 | ~Ng2787)); - assign n6787 = ~n8026; - assign n8028 = (n5188 & Ng2746) | (~Ng2789 & (~n5188 | Ng2746)); - assign n6782 = ~n8028; - assign n8030 = (~n5181 & ~Ng2788) | (Ng2746 & (n5181 | ~Ng2788)); - assign n6777 = ~n8030; - assign n8032 = (~n5193 & ~Ng2784) | (Ng2734 & (n5193 | ~Ng2784)); - assign n6772 = ~n8032; - assign n8034 = (n5188 & Ng2734) | (~Ng2786 & (~n5188 | Ng2734)); - assign n6767 = ~n8034; - assign n8036 = (~n5181 & ~Ng2785) | (Ng2734 & (n5181 | ~Ng2785)); - assign n6762 = ~n8036; - assign n8038 = (~n5193 & ~Ng2781) | (Ng2720 & (n5193 | ~Ng2781)); - assign n6757 = ~n8038; - assign n8040 = (n5188 & Ng2720) | (~Ng2783 & (~n5188 | Ng2720)); - assign n6752 = ~n8040; - assign n8042 = (~n5181 & ~Ng2782) | (Ng2720 & (n5181 | ~Ng2782)); - assign n6747 = ~n8042; - assign n8044 = (~n5193 & ~Ng2778) | (Ng2727 & (n5193 | ~Ng2778)); - assign n6742 = ~n8044; - assign n8046 = (n5188 & Ng2727) | (~Ng2780 & (~n5188 | Ng2727)); - assign n6737 = ~n8046; - assign n8048 = (~n5181 & ~Ng2779) | (Ng2727 & (n5181 | ~Ng2779)); - assign n6732 = ~n8048; - assign n8050 = (~n5193 & ~Ng2775) | (Ng2707 & (n5193 | ~Ng2775)); - assign n6727 = ~n8050; - assign n8052 = (n5188 & Ng2707) | (~Ng2777 & (~n5188 | Ng2707)); - assign n6722 = ~n8052; - assign n8054 = (~n5181 & ~Ng2776) | (Ng2707 & (n5181 | ~Ng2776)); - assign n6717 = ~n8054; - assign n8056 = (~n5193 & ~Ng2772) | (Ng2714 & (n5193 | ~Ng2772)); - assign n6712 = ~n8056; - assign n8058 = (n5188 & Ng2714) | (~Ng2774 & (~n5188 | Ng2714)); - assign n6707 = ~n8058; - assign n8060 = (~n5181 & ~Ng2773) | (Ng2714 & (n5181 | ~Ng2773)); - assign n6702 = ~n8060; - assign n8062 = (n5185_1 & ~Ng2111) | (~n5062 & (~n5185_1 | ~Ng2111)); - assign n5370 = ~n8062; - assign n8064 = (~n5062 & ~n5112) | (~Ng2113 & (~n5062 | n5112)); - assign n5365 = ~n8064; - assign n8066 = (n5170_1 & ~Ng2112) | (~n5062 & (~n5170_1 | ~Ng2112)); - assign n5360 = ~n8066; - assign n8068 = (n5185_1 & ~Ng2108) | (~n4978_1 & (~n5185_1 | ~Ng2108)); - assign n5355 = ~n8068; - assign n8070 = (n5112 & ~Ng2110) | (~n4978_1 & (~n5112 | ~Ng2110)); - assign n5350 = ~n8070; - assign n8072 = (n5170_1 & ~Ng2109) | (~n4978_1 & (~n5170_1 | ~Ng2109)); - assign n5345 = ~n8072; - assign n8074 = (~n5186 & ~Ng2105) | (Ng2072 & (n5186 | ~Ng2105)); - assign n5340 = ~n8074; - assign n8076 = (n5178 & Ng2072) | (~Ng2107 & (~n5178 | Ng2072)); - assign n5335 = ~n8076; - assign n8078 = (~n5171 & ~Ng2106) | (Ng2072 & (n5171 | ~Ng2106)); - assign n5330 = ~n8078; - assign n8080 = (~n5186 & ~Ng2102) | (Ng2066 & (n5186 | ~Ng2102)); - assign n5325 = ~n8080; - assign n8082 = (n5178 & Ng2066) | (~Ng2104 & (~n5178 | Ng2066)); - assign n5320 = ~n8082; - assign n8084 = (~n5171 & ~Ng2103) | (Ng2066 & (n5171 | ~Ng2103)); - assign n5315 = ~n8084; - assign n8086 = (~n5186 & ~Ng2099) | (Ng2059 & (n5186 | ~Ng2099)); - assign n5310 = ~n8086; - assign n8088 = (n5178 & Ng2059) | (~Ng2101 & (~n5178 | Ng2059)); - assign n5305 = ~n8088; - assign n8090 = (~n5171 & ~Ng2100) | (Ng2059 & (n5171 | ~Ng2100)); - assign n5300 = ~n8090; - assign n8092 = (~n5186 & ~Ng2096) | (Ng2046 & (n5186 | ~Ng2096)); - assign n5295 = ~n8092; - assign n8094 = (n5178 & Ng2046) | (~Ng2098 & (~n5178 | Ng2046)); - assign n5290 = ~n8094; - assign n8096 = (~n5171 & ~Ng2097) | (Ng2046 & (n5171 | ~Ng2097)); - assign n5285 = ~n8096; - assign n8098 = (~n5186 & ~Ng2093) | (Ng2052 & (n5186 | ~Ng2093)); - assign n5280 = ~n8098; - assign n8100 = (n5178 & Ng2052) | (~Ng2095 & (~n5178 | Ng2052)); - assign n5275 = ~n8100; - assign n8102 = (~n5171 & ~Ng2094) | (Ng2052 & (n5171 | ~Ng2094)); - assign n5270 = ~n8102; - assign n8104 = (~n5186 & ~Ng2090) | (Ng2040 & (n5186 | ~Ng2090)); - assign n5265 = ~n8104; - assign n8106 = (n5178 & Ng2040) | (~Ng2092 & (~n5178 | Ng2040)); - assign n5260 = ~n8106; - assign n8108 = (~n5171 & ~Ng2091) | (Ng2040 & (n5171 | ~Ng2091)); - assign n5255 = ~n8108; - assign n8110 = (~n5186 & ~Ng2087) | (Ng2026 & (n5186 | ~Ng2087)); - assign n5250 = ~n8110; - assign n8112 = (n5178 & Ng2026) | (~Ng2089 & (~n5178 | Ng2026)); - assign n5245 = ~n8112; - assign n8114 = (~n5171 & ~Ng2088) | (Ng2026 & (n5171 | ~Ng2088)); - assign n5240 = ~n8114; - assign n8116 = (~n5186 & ~Ng2084) | (Ng2033 & (n5186 | ~Ng2084)); - assign n5235 = ~n8116; - assign n8118 = (n5178 & Ng2033) | (~Ng2086 & (~n5178 | Ng2033)); - assign n5230 = ~n8118; - assign n8120 = (~n5171 & ~Ng2085) | (Ng2033 & (n5171 | ~Ng2085)); - assign n5225 = ~n8120; - assign n8122 = (~n5186 & ~Ng2081) | (Ng2013 & (n5186 | ~Ng2081)); - assign n5220 = ~n8122; - assign n8124 = (n5178 & Ng2013) | (~Ng2083 & (~n5178 | Ng2013)); - assign n5215 = ~n8124; - assign n8126 = (~n5171 & ~Ng2082) | (Ng2013 & (n5171 | ~Ng2082)); - assign n5210 = ~n8126; - assign n8128 = (~n5186 & ~Ng2078) | (Ng2020 & (n5186 | ~Ng2078)); - assign n5205 = ~n8128; - assign n8130 = (n5178 & Ng2020) | (~Ng2080 & (~n5178 | Ng2020)); - assign n5200 = ~n8130; - assign n8132 = (~n5171 & ~Ng2079) | (Ng2020 & (n5171 | ~Ng2079)); - assign n5195 = ~n8132; - assign n8134 = (n5175_1 & ~Ng1417) | (~n5058_1 & (~n5175_1 | ~Ng1417)); - assign n3876_1 = ~n8134; - assign n8136 = (~n5058_1 & ~n5109) | (~Ng1419 & (~n5058_1 | n5109)); - assign n3871_1 = ~n8136; - assign n8138 = (n5160_1 & ~Ng1418) | (~n5058_1 & (~n5160_1 | ~Ng1418)); - assign n3866 = ~n8138; - assign n8140 = (n5175_1 & ~Ng1414) | (~n4972 & (~n5175_1 | ~Ng1414)); - assign n3861_1 = ~n8140; - assign n8142 = (n5109 & ~Ng1416) | (~n4972 & (~n5109 | ~Ng1416)); - assign n3856_1 = ~n8142; - assign n8144 = (n5160_1 & ~Ng1415) | (~n4972 & (~n5160_1 | ~Ng1415)); - assign n3851_1 = ~n8144; - assign n8146 = (~n5176 & ~Ng1411) | (Ng1378 & (n5176 | ~Ng1411)); - assign n3846_1 = ~n8146; - assign n8148 = (n5168 & Ng1378) | (~Ng1413 & (~n5168 | Ng1378)); - assign n3841_1 = ~n8148; - assign n8150 = (~n5161 & ~Ng1412) | (Ng1378 & (n5161 | ~Ng1412)); - assign n3836_1 = ~n8150; - assign n8152 = (~n5176 & ~Ng1408) | (Ng1372 & (n5176 | ~Ng1408)); - assign n3831_1 = ~n8152; - assign n8154 = (n5168 & Ng1372) | (~Ng1410 & (~n5168 | Ng1372)); - assign n3826_1 = ~n8154; - assign n8156 = (~n5161 & ~Ng1409) | (Ng1372 & (n5161 | ~Ng1409)); - assign n3821 = ~n8156; - assign n8158 = (~n5176 & ~Ng1405) | (Ng1365 & (n5176 | ~Ng1405)); - assign n3816 = ~n8158; - assign n8160 = (n5168 & Ng1365) | (~Ng1407 & (~n5168 | Ng1365)); - assign n3811_1 = ~n8160; - assign n8162 = (~n5161 & ~Ng1406) | (Ng1365 & (n5161 | ~Ng1406)); - assign n3806 = ~n8162; - assign n8164 = (~n5176 & ~Ng1402) | (Ng1352 & (n5176 | ~Ng1402)); - assign n3801 = ~n8164; - assign n8166 = (n5168 & Ng1352) | (~Ng1404 & (~n5168 | Ng1352)); - assign n3796_1 = ~n8166; - assign n8168 = (~n5161 & ~Ng1403) | (Ng1352 & (n5161 | ~Ng1403)); - assign n3791 = ~n8168; - assign n8170 = (~n5176 & ~Ng1399) | (Ng1358 & (n5176 | ~Ng1399)); - assign n3786 = ~n8170; - assign n8172 = (n5168 & Ng1358) | (~Ng1401 & (~n5168 | Ng1358)); - assign n3781_1 = ~n8172; - assign n8174 = (~n5161 & ~Ng1400) | (Ng1358 & (n5161 | ~Ng1400)); - assign n3776_1 = ~n8174; - assign n8176 = (~n5176 & ~Ng1396) | (Ng1346 & (n5176 | ~Ng1396)); - assign n3771 = ~n8176; - assign n8178 = (n5168 & Ng1346) | (~Ng1398 & (~n5168 | Ng1346)); - assign n3766_1 = ~n8178; - assign n8180 = (~n5161 & ~Ng1397) | (Ng1346 & (n5161 | ~Ng1397)); - assign n3761 = ~n8180; - assign n8182 = (~n5176 & ~Ng1393) | (Ng1332 & (n5176 | ~Ng1393)); - assign n3756_1 = ~n8182; - assign n8184 = (n5168 & Ng1332) | (~Ng1395 & (~n5168 | Ng1332)); - assign n3751_1 = ~n8184; - assign n8186 = (~n5161 & ~Ng1394) | (Ng1332 & (n5161 | ~Ng1394)); - assign n3746_1 = ~n8186; - assign n8188 = (~n5176 & ~Ng1390) | (Ng1339 & (n5176 | ~Ng1390)); - assign n3741_1 = ~n8188; - assign n8190 = (n5168 & Ng1339) | (~Ng1392 & (~n5168 | Ng1339)); - assign n3736_1 = ~n8190; - assign n8192 = (~n5161 & ~Ng1391) | (Ng1339 & (n5161 | ~Ng1391)); - assign n3731_1 = ~n8192; - assign n8194 = (~n5176 & ~Ng1387) | (Ng1319 & (n5176 | ~Ng1387)); - assign n3726_1 = ~n8194; - assign n8196 = (n5168 & Ng1319) | (~Ng1389 & (~n5168 | Ng1319)); - assign n3721_1 = ~n8196; - assign n8198 = (~n5161 & ~Ng1388) | (Ng1319 & (n5161 | ~Ng1388)); - assign n3716_1 = ~n8198; - assign n8200 = (~n5176 & ~Ng1384) | (Ng1326 & (n5176 | ~Ng1384)); - assign n3711_1 = ~n8200; - assign n8202 = (n5168 & Ng1326) | (~Ng1386 & (~n5168 | Ng1326)); - assign n3706_1 = ~n8202; - assign n8204 = (~n5161 & ~Ng1385) | (Ng1326 & (n5161 | ~Ng1385)); - assign n3701_1 = ~n8204; - assign n8206 = (n5165_1 & ~Ng731) | (~n5054 & (~n5165_1 | ~Ng731)); - assign n2357 = ~n8206; - assign n8208 = (~n5054 & ~n5106) | (~Ng733 & (~n5054 | n5106)); - assign n2352 = ~n8208; - assign n8210 = (n5153 & ~Ng732) | (~n5054 & (~n5153 | ~Ng732)); - assign n2347 = ~n8210; - assign n8212 = (n5165_1 & ~Ng728) | (~n4964 & (~n5165_1 | ~Ng728)); - assign n2342 = ~n8212; - assign n8214 = (n5106 & ~Ng730) | (~n4964 & (~n5106 | ~Ng730)); - assign n2337 = ~n8214; - assign n8216 = (n5153 & ~Ng729) | (~n4964 & (~n5153 | ~Ng729)); - assign n2332_1 = ~n8216; - assign n8218 = (~n5166 & ~Ng725) | (Ng692 & (n5166 | ~Ng725)); - assign n2327_1 = ~n8218; - assign n8220 = (n5158 & Ng692) | (~Ng727 & (~n5158 | Ng692)); - assign n2322 = ~n8220; - assign n8222 = (~n5154 & ~Ng726) | (Ng692 & (n5154 | ~Ng726)); - assign n2317 = ~n8222; - assign n8224 = (~n5166 & ~Ng722) | (Ng686 & (n5166 | ~Ng722)); - assign n2312 = ~n8224; - assign n8226 = (n5158 & Ng686) | (~Ng724 & (~n5158 | Ng686)); - assign n2307 = ~n8226; - assign n8228 = (~n5154 & ~Ng723) | (Ng686 & (n5154 | ~Ng723)); - assign n2302 = ~n8228; - assign n8230 = (~n5166 & ~Ng719) | (Ng679 & (n5166 | ~Ng719)); - assign n2297_1 = ~n8230; - assign n8232 = (n5158 & Ng679) | (~Ng721 & (~n5158 | Ng679)); - assign n2292 = ~n8232; - assign n8234 = (~n5154 & ~Ng720) | (Ng679 & (n5154 | ~Ng720)); - assign n2287 = ~n8234; - assign n8236 = (~n5166 & ~Ng716) | (Ng666 & (n5166 | ~Ng716)); - assign n2282 = ~n8236; - assign n8238 = (n5158 & Ng666) | (~Ng718 & (~n5158 | Ng666)); - assign n2277 = ~n8238; - assign n8240 = (~n5154 & ~Ng717) | (Ng666 & (n5154 | ~Ng717)); - assign n2272 = ~n8240; - assign n8242 = (~n5166 & ~Ng713) | (Ng672 & (n5166 | ~Ng713)); - assign n2267 = ~n8242; - assign n8244 = (n5158 & Ng672) | (~Ng715 & (~n5158 | Ng672)); - assign n2262 = ~n8244; - assign n8246 = (~n5154 & ~Ng714) | (Ng672 & (n5154 | ~Ng714)); - assign n2257_1 = ~n8246; - assign n8248 = (~n5166 & ~Ng710) | (Ng660 & (n5166 | ~Ng710)); - assign n2252 = ~n8248; - assign n8250 = (n5158 & Ng660) | (~Ng712 & (~n5158 | Ng660)); - assign n2247_1 = ~n8250; - assign n8252 = (~n5154 & ~Ng711) | (Ng660 & (n5154 | ~Ng711)); - assign n2242 = ~n8252; - assign n8254 = (~n5166 & ~Ng707) | (Ng646 & (n5166 | ~Ng707)); - assign n2237_1 = ~n8254; - assign n8256 = (n5158 & Ng646) | (~Ng709 & (~n5158 | Ng646)); - assign n2232 = ~n8256; - assign n8258 = (~n5154 & ~Ng708) | (Ng646 & (n5154 | ~Ng708)); - assign n2227_1 = ~n8258; - assign n8260 = (~n5166 & ~Ng704) | (Ng653 & (n5166 | ~Ng704)); - assign n2222 = ~n8260; - assign n8262 = (n5158 & Ng653) | (~Ng706 & (~n5158 | Ng653)); - assign n2217_1 = ~n8262; - assign n8264 = (~n5154 & ~Ng705) | (Ng653 & (n5154 | ~Ng705)); - assign n2212_1 = ~n8264; - assign n8266 = (~n5166 & ~Ng701) | (Ng633 & (n5166 | ~Ng701)); - assign n2207_1 = ~n8266; - assign n8268 = (n5158 & Ng633) | (~Ng703 & (~n5158 | Ng633)); - assign n2202 = ~n8268; - assign n8270 = (~n5154 & ~Ng702) | (Ng633 & (n5154 | ~Ng702)); - assign n2197 = ~n8270; - assign n8272 = (~n5166 & ~Ng698) | (Ng640 & (n5166 | ~Ng698)); - assign n2192_1 = ~n8272; - assign n8274 = (n5158 & Ng640) | (~Ng700 & (~n5158 | Ng640)); - assign n2187_1 = ~n8274; - assign n8276 = (~n5154 & ~Ng699) | (Ng640 & (n5154 | ~Ng699)); - assign n2182_1 = ~n8276; - assign n8278 = (~Ng2879 & ~Ng2975) | (~Pg4590 & (Ng2879 | ~Ng2975)); - assign n504_1 = ~n8278; - assign n8280 = (~Ng2879 & ~Ng2978) | (~Pg4323 & (Ng2879 | ~Ng2978)); - assign n496_1 = ~n8280; - assign n8282 = (~Ng2879 & ~Ng2981) | (~Pg4090 & (Ng2879 | ~Ng2981)); - assign n488_1 = ~n8282; - assign n8284 = (~Ng2879 & ~Ng2874) | (~Pg8251 & (Ng2879 | ~Ng2874)); - assign n480_1 = ~n8284; - assign n8286 = (~Ng2879 & ~Ng2935) | (~Pg4450 & (Ng2879 | ~Ng2935)); - assign n608_1 = ~n8286; - assign n8288 = (~Ng2879 & ~Ng2938) | (~Pg4200 & (Ng2879 | ~Ng2938)); - assign n600_1 = ~n8288; - assign n8290 = (~Ng2879 & ~Ng2941) | (~Pg3993 & (Ng2879 | ~Ng2941)); - assign n592_1 = ~n8290; - assign n8292 = (~Ng2879 & ~Ng2944) | (~Pg8175 & (Ng2879 | ~Ng2944)); - assign n584_1 = ~n8292; - assign n8294 = (~Ng2879 & ~Ng2947) | (~Pg8023 & (Ng2879 | ~Ng2947)); - assign n576_1 = ~n8294; - assign n8296 = (~Ng2879 & ~Ng2953) | (~Pg4321 & (Ng2879 | ~Ng2953)); - assign n568_1 = ~n8296; - assign n8298 = (~Ng2879 & ~Ng2956) | (~Pg4088 & (Ng2879 | ~Ng2956)); - assign n560_1 = ~n8298; - assign n8300 = (~Ng2879 & ~Ng2959) | (~Pg8249 & (Ng2879 | ~Ng2959)); - assign n552_1 = ~n8300; - assign n8302 = (~Ng2879 & ~Ng2963) | (~Pg7334 & (Ng2879 | ~Ng2963)); - assign n536_1 = ~n8302; - assign n8304 = (~Ng2879 & ~Ng2966) | (~Pg6895 & (Ng2879 | ~Ng2966)); - assign n528_1 = ~n8304; - assign n8306 = (~Ng2879 & ~Ng2969) | (~Pg6442 & (Ng2879 | ~Ng2969)); - assign n520_1 = ~n8306; - assign n8308 = (~Ng2879 & ~Ng2972) | (~Pg6225 & (Ng2879 | ~Ng2972)); - assign n512_1 = ~n8308; - assign n8310 = (~Ng1315 & ~Ng3084) | (~Ng559 & (Ng1315 | ~Ng3084)); - assign n679_1 = ~n8310; - assign n8312 = (~\[1603] & ~Ng3211) | (~Ng559 & (\[1603] | ~Ng3211)); - assign n674 = ~n8312; - assign n8314 = (~\[1605] & ~Ng3210) | (~Ng559 & (\[1605] | ~Ng3210)); - assign n669_1 = ~n8314; - assign n8316 = (~Ng1315 & ~Ng3088) | (~Ng8311 & (Ng1315 | ~Ng3088)); - assign n844_1 = ~n8316; - assign n8318 = (~\[1603] & ~Ng3185) | (~Ng8311 & (\[1603] | ~Ng3185)); - assign n839_1 = ~n8318; - assign n8320 = (~\[1605] & ~Ng3182) | (~Ng8311 & (\[1605] | ~Ng3182)); - assign n834_1 = ~n8320; - assign n8322 = (~Ng1315 & ~Ng3179) | (~Ng8302 & (Ng1315 | ~Ng3179)); - assign n829_1 = ~n8322; - assign n8324 = (~\[1603] & ~Ng3176) | (~Ng8302 & (\[1603] | ~Ng3176)); - assign n824_1 = ~n8324; - assign n8326 = (~\[1605] & ~Ng3173) | (~Ng8302 & (\[1605] | ~Ng3173)); - assign n819_1 = ~n8326; - assign n8328 = (~Ng1315 & ~Ng3170) | (~Ng8293 & (Ng1315 | ~Ng3170)); - assign n814_1 = ~n8328; - assign n8330 = (~\[1603] & ~Ng3167) | (~Ng8293 & (\[1603] | ~Ng3167)); - assign n809_1 = ~n8330; - assign n8332 = (~\[1605] & ~Ng3164) | (~Ng8293 & (\[1605] | ~Ng3164)); - assign n804_1 = ~n8332; - assign n8334 = (~Ng1315 & ~Ng3161) | (~Ng8284 & (Ng1315 | ~Ng3161)); - assign n799_1 = ~n8334; - assign n8336 = (~\[1603] & ~Ng3158) | (~Ng8284 & (\[1603] | ~Ng3158)); - assign n794_1 = ~n8336; - assign n8338 = (~\[1605] & ~Ng3155) | (~Ng8284 & (\[1605] | ~Ng3155)); - assign n789_1 = ~n8338; - assign n8340 = (~Ng1315 & ~Ng3096) | (~Ng2633 & (Ng1315 | ~Ng3096)); - assign n724_1 = ~n8340; - assign n8342 = (~\[1603] & ~Ng3095) | (~Ng2633 & (\[1603] | ~Ng3095)); - assign n719_1 = ~n8342; - assign n8344 = (~\[1605] & ~Ng3094) | (~Ng2633 & (\[1605] | ~Ng3094)); - assign n714_1 = ~n8344; - assign n8346 = (~Ng1315 & ~Ng3093) | (~Ng1939 & (Ng1315 | ~Ng3093)); - assign n709_1 = ~n8346; - assign n8348 = (~\[1603] & ~Ng3092) | (~Ng1939 & (\[1603] | ~Ng3092)); - assign n704_1 = ~n8348; - assign n8350 = (~\[1605] & ~Ng3091) | (~Ng1939 & (\[1605] | ~Ng3091)); - assign n699_1 = ~n8350; - assign n8352 = (~Ng1315 & ~Ng3087) | (~Ng1245 & (Ng1315 | ~Ng3087)); - assign n694 = ~n8352; - assign n8354 = (~\[1603] & ~Ng3086) | (~Ng1245 & (\[1603] | ~Ng3086)); - assign n689_1 = ~n8354; - assign n8356 = (~\[1605] & ~Ng3085) | (~Ng1245 & (\[1605] | ~Ng3085)); - assign n684_1 = ~n8356; - assign n8358 = (Ng2987 & ~Ng3074) | (~Ng3056 & (~Ng2987 | ~Ng3074)); - assign n7230 = ~n8358; - assign n8360 = (Ng2987 & ~Ng3073) | (~Ng3055 & (~Ng2987 | ~Ng3073)); - assign n7226 = ~n8360; - assign n8362 = (Ng2987 & ~Ng3072) | (~Ng3053 & (~Ng2987 | ~Ng3072)); - assign n7222 = ~n8362; - assign n8364 = (Ng2987 & ~Ng3071) | (~Ng3052 & (~Ng2987 | ~Ng3071)); - assign n7218 = ~n8364; - assign n8366 = (Ng2987 & ~Ng3070) | (~Ng3051 & (~Ng2987 | ~Ng3070)); - assign n7204 = ~n8366; - assign n8368 = (Ng2987 & ~Ng3069) | (~Ng3050 & (~Ng2987 | ~Ng3069)); - assign n7200 = ~n8368; - assign n8370 = (Ng2987 & ~Ng3068) | (~Ng3049 & (~Ng2987 | ~Ng3068)); - assign n7196 = ~n8370; - assign n8372 = (Ng2987 & ~Ng3067) | (~Ng3048 & (~Ng2987 | ~Ng3067)); - assign n7192 = ~n8372; - assign n8374 = (Ng2987 & ~Ng3066) | (~Ng3047 & (~Ng2987 | ~Ng3066)); - assign n7188 = ~n8374; - assign n8376 = (Ng2987 & ~Ng3065) | (~Ng3046 & (~Ng2987 | ~Ng3065)); - assign n7184 = ~n8376; - assign n8378 = (Ng2987 & ~Ng3064) | (~Ng3045 & (~Ng2987 | ~Ng3064)); - assign n7180 = ~n8378; - assign n8380 = (Ng2987 & ~Ng3063) | (~Ng3044 & (~Ng2987 | ~Ng3063)); - assign n7176 = ~n8380; - assign n8382 = (Ng2987 & ~Ng3062) | (~Ng3043 & (~Ng2987 | ~Ng3062)); - assign n7172 = ~n8382; - assign n8384 = (Ng2987 & ~Ng2997) | (~Ng3061 & (~Ng2987 | ~Ng2997)); - assign n7250 = ~n8384; - assign n8386 = (Ng2987 & ~Ng3078) | (~Ng3060 & (~Ng2987 | ~Ng3078)); - assign n7246 = ~n8386; - assign n8388 = (Ng2987 & ~Ng3077) | (~Ng3059 & (~Ng2987 | ~Ng3077)); - assign n7242 = ~n8388; - assign n8390 = (Ng2987 & ~Ng3076) | (~Ng3058 & (~Ng2987 | ~Ng3076)); - assign n7238 = ~n8390; - assign n8392 = (Ng2987 & ~Ng3075) | (~Ng3057 & (~Ng2987 | ~Ng3075)); - assign n7234 = ~n8392; - assign n8394 = (Ng2879 & ~Ng2874) | (~Ng2200 & (~Ng2879 | ~Ng2874)); - assign n624_1 = ~n8394; - assign n8396 = (Ng2879 & ~Ng2978) | (~Ng2190 & (~Ng2879 | ~Ng2978)); - assign n634_1 = ~n8396; - assign n8398 = (Ng2879 & ~Ng2981) | (~Ng2195 & (~Ng2879 | ~Ng2981)); - assign n629_1 = ~n8398; - assign n8400 = (Ng2879 & ~Ng2975) | (~Ng2185 & (~Ng2879 | ~Ng2975)); - assign n639_1 = ~n8400; - assign n8402 = (Ng2879 & ~Ng2972) | (~Ng2180 & (~Ng2879 | ~Ng2972)); - assign n644_1 = ~n8402; - assign n8404 = (Ng2879 & ~Ng2969) | (~Ng2175 & (~Ng2879 | ~Ng2969)); - assign n649_1 = ~n8404; - assign n8406 = (Ng2879 & ~Ng2966) | (~Ng2170 & (~Ng2879 | ~Ng2966)); - assign n654_1 = ~n8406; - assign n8408 = (Ng2879 & ~Ng2963) | (~Ng2165 & (~Ng2879 | ~Ng2963)); - assign n659_1 = ~n8408; - assign n8410 = (Ng2879 & ~Ng2935) | (~Ng1471 & (~Ng2879 | ~Ng2935)); - assign n470_1 = ~n8410; - assign n8412 = (Ng2879 & ~Ng2938) | (~Ng1476 & (~Ng2879 | ~Ng2938)); - assign n465 = ~n8412; - assign n8414 = (Ng2879 & ~Ng2941) | (~Ng1481 & (~Ng2879 | ~Ng2941)); - assign n460_1 = ~n8414; - assign n8416 = (Ng2879 & ~Ng2944) | (~Ng1486 & (~Ng2879 | ~Ng2944)); - assign n455_1 = ~n8416; - assign n8418 = (Ng2879 & ~Ng2947) | (~Ng1491 & (~Ng2879 | ~Ng2947)); - assign n450_1 = ~n8418; - assign n8420 = (Ng2879 & ~Ng2953) | (~Ng1496 & (~Ng2879 | ~Ng2953)); - assign n445_1 = ~n8420; - assign n8422 = (Ng2879 & ~Ng2956) | (~Ng1501 & (~Ng2879 | ~Ng2956)); - assign n440_1 = ~n8422; - assign n8424 = (Ng2879 & ~Ng2959) | (~Ng1506 & (~Ng2879 | ~Ng2959)); - assign n435_1 = ~n8424; - assign n8426 = (~Ng1315 & ~Ng2704) | (~Ng2584 & (Ng1315 | ~Ng2704)); - assign n6642 = ~n8426; - assign n8428 = (Ng1315 & ~Ng2631) | (~Ng2584 & (~Ng1315 | ~Ng2631)); - assign n6254 = ~n8428; - assign n8430 = (Ng1315 & Ng2628) | (~Ng2631 & (~Ng1315 | Ng2628)); - assign n6249 = ~n8430; - assign n8432 = (~Ng1315 & ~Ng2010) | (~Ng1890 & (Ng1315 | ~Ng2010)); - assign n5135 = ~n8432; - assign n8434 = (Ng1315 & ~Ng1937) | (~Ng1890 & (~Ng1315 | ~Ng1937)); - assign n4747 = ~n8434; - assign n8436 = (Ng1315 & Ng1934) | (~Ng1937 & (~Ng1315 | Ng1934)); - assign n4742 = ~n8436; - assign n8438 = (~Ng1315 & ~Ng1316) | (~Ng1196 & (Ng1315 | ~Ng1316)); - assign n3641_1 = ~n8438; - assign n8440 = (Ng1315 & ~Ng1243) | (~Ng1196 & (~Ng1315 | ~Ng1243)); - assign n3240_1 = ~n8440; - assign n8442 = (Ng1315 & Ng1240) | (~Ng1243 & (~Ng1315 | Ng1240)); - assign n3235_1 = ~n8442; - assign n8444 = (~Ng1315 & ~Ng630) | (~Ng510 & (Ng1315 | ~Ng630)); - assign n2122_1 = ~n8444; - assign n8446 = (Ng1315 & ~Ng557) | (~Ng510 & (~Ng1315 | ~Ng557)); - assign n1734_1 = ~n8446; - assign n8448 = (Ng1315 & Ng554) | (~Ng557 & (~Ng1315 | Ng554)); - assign n1729_1 = ~n8448; - assign n8450 = n5054 | n5981; - assign n8451 = n5058_1 | n5955; - assign n8452 = ~n4978_1 & n5840; - assign n8453 = n5062 | ~n5840; - assign n8454 = ~n4982 & n5833_1; - assign n8455 = n5064 | ~n5833_1; - assign n8456 = (~Ng1315 | Ng2811) & (~\[1605] | Ng2812); - assign n8457 = n4948_1 & (~n8456 | (\[1603] & ~Ng2813)); - assign n8458 = (Ng2611 | n6476) & (n5072_1 | n5577); - assign n8459 = (n5072_1 | ~n5590_1) & (n6476 | Ng2610); - assign n8460 = (n5072_1 | ~n5587) & (n6476 | Ng2608); - assign n8461 = (n5072_1 | ~n5585_1) & (n6476 | Ng2607); - assign n8462 = (n5072_1 | ~n5579) & (n6476 | Ng2606); - assign n8463 = (n5072_1 | ~n5589) & (n6476 | Ng2605); - assign n8464 = (n5072_1 | ~n5583) & (n6476 | Ng2604); - assign n8465 = (n5072_1 | ~n5581) & (n6476 | Ng2603); - assign n8466 = (~Ng1315 | Ng2117) & (~\[1605] | Ng2118); - assign n8467 = n4936 & (~n8466 | (\[1603] & ~Ng2119)); - assign n8468 = (n5070 | ~n5573) & (n6478 | Ng1917); - assign n8469 = (n5070 | ~n5571) & (n6478 | Ng1916); - assign n8470 = (n5070 | ~n5568) & (n6478 | Ng1914); - assign n8471 = (n5070 | ~n5566) & (n6478 | Ng1913); - assign n8472 = (n5070 | ~n5560_1) & (n6478 | Ng1912); - assign n8473 = (n5070 | ~n5570_1) & (n6478 | Ng1911); - assign n8474 = (n5070 | ~n5564) & (n6478 | Ng1910); - assign n8475 = (n5070 | ~n5562) & (n6478 | Ng1909); - assign n8476 = (n6293 | n5853_1) & (n6294_1 | n6295); - assign n8477 = (n6295 | n5853_1) & (n6293 | n6296); - assign n8478 = (~n6296 | ~n8476) & (~n6294_1 | ~n8477); - assign n8479 = (n5847 | n6297) & (~n6298 | n6299_1); - assign n8480 = (n5847 | n6299_1) & (n6297 | n6300); - assign n8481 = (~n6300 | ~n8479) & (n6298 | ~n8480); - assign n8482 = (n6317_1 | n5873_1) & (n6318 | n6319); - assign n8483 = (n6319 | n5873_1) & (n6317_1 | n6320); - assign n8484 = (~n6320 | ~n8482) & (~n6318 | ~n8483); - assign n8485 = (n5867 | n6321_1) & (~n6322 | n6323); - assign n8486 = (n5867 | n6323) & (n6321_1 | n6324); - assign n8487 = (~n6324 | ~n8485) & (n6322 | ~n8486); - assign n8488 = (n6341_1 | n5893_1) & (n6342 | n6343); - assign n8489 = (n6343 | n5893_1) & (n6341_1 | n6344); - assign n8490 = (~n6344 | ~n8488) & (~n6342 | ~n8489); - assign n8491 = (n5887 | n6345_1) & (~n6346 | n6347); - assign n8492 = (n5887 | n6347) & (n6345_1 | n6348); - assign n8493 = (~n6348 | ~n8491) & (n6346 | ~n8492); - assign n8494 = (n6365 | n5913_1) & (n6366 | n6367); - assign n8495 = (n6367 | n5913_1) & (n6365 | n6368_1); - assign n8496 = (~n6368_1 | ~n8494) & (~n6366 | ~n8495); - assign n8497 = (n5907 | n6369) & (~n6370 | n6371); - assign n8498 = (n5907 | n6371) & (n6369 | n6372); - assign n8499 = (~n6372 | ~n8497) & (n6370 | ~n8498); - assign n8500 = (~Ng1315 | Ng1423) & (~\[1605] | Ng1424); - assign n8501 = n4932 | n4862 | n4798 | n4734 | n4712_1 | n4764; - assign n8502 = (n5068 | ~n5538) & (n6520_1 | Ng1223); - assign n8503 = (n5068 | ~n5536) & (n6520_1 | Ng1222); - assign n8504 = (n5068 | ~n5533) & (n6520_1 | Ng1220); - assign n8505 = (n5068 | ~n5531) & (n6520_1 | Ng1219); - assign n8506 = (n5068 | ~n5540_1) & (n6520_1 | Ng1218); - assign n8507 = (n5068 | ~n5535_1) & (n6520_1 | Ng1217); - assign n8508 = (n5068 | ~n5529) & (n6520_1 | Ng1216); - assign n8509 = (n5068 | ~n5526) & (n6520_1 | Ng1215); - assign n8510 = (~Ng1315 | Ng737) & (~\[1605] | Ng738); - assign n8511 = n4912 | n4820 | n4756_1 | n4704_1 | n4688_1 | n4728_1; - assign n8512 = (n5066 | ~n5518) & (n6526 | Ng537); - assign n8513 = (n5066 | ~n5516) & (n6526 | Ng536); - assign n8514 = (n5066 | ~n5513) & (n6526 | Ng534); - assign n8515 = (n5066 | ~n5511) & (n6526 | Ng533); - assign n8516 = (n5066 | ~n5520_1) & (n6526 | Ng532); - assign n8517 = (n5066 | ~n5515_1) & (n6526 | Ng531); - assign n8518 = (n5066 | ~n5509) & (n6526 | Ng530); - assign n8519 = (n5066 | ~n5522) & (n6526 | Ng529); - assign n8520 = n5028_1 | n4561 | n4571; - assign n8521 = n8520 & (n6552 | n6057_1); - assign n8522 = (~n5018_1 | n6051) & (~n4567 | n6552); - assign n8523 = n5016 | n4553 | n4565; - assign n8524 = n8523 & (n6557 | n6079); - assign n8525 = (~n5006 | n6073) & (~n4559_1 | n6557); - assign n8526 = n5004 | n4547 | n4557; - assign n8527 = n8526 & (n6561 | n6101); - assign n8528 = (~n4994 | n6095) & (~n4551 | n6561); - assign n8529 = n4992 | n4543 | n4549; - assign n8530 = n8529 & (n6565_1 | n6123); - assign n8531 = (~n4986 | n6117) & (~n4545 | n6565_1); - assign n8532 = n6531 | ~n8745; - assign n8533 = (~Ng853 | Ng2253) & (~\[1612] | Ng2254); - assign n8534 = (~Ng853 | Ng1559) & (~\[1612] | Ng1560); - assign n8535 = (~Ng853 | Ng865) & (~\[1612] | Ng866); - assign n8536 = (~Ng853 | Ng177) & (~\[1612] | Ng178); - assign n8537 = n6437 | n6435_1 | n6436; - assign n8538 = n6440_1 | n6441 | n6442 | n6443 | n6439 | n8537 | n6444 | n6438; - assign n8539 = ~Ng1315 | Ng2802; - assign n8540 = n6447 | n6445_1 | n6446; - assign n8541 = n6450_1 | n6451 | n6452 | n6453 | n6449 | n8540 | n6454 | n6448; - assign n8542 = ~Ng1315 | Ng2108; - assign n8543 = n6457 | n6455_1 | n6456; - assign n8544 = n6460_1 | n6461 | n6462 | n6463 | n6459 | n8543 | n6464 | n6458; - assign n8545 = ~Ng1315 | Ng1414; - assign n8546 = n6467 | n6465_1 | n6466; - assign n8547 = n6470_1 | n6471 | n6472 | n6473 | n6469 | n8546 | n6474 | n6468; - assign n8548 = ~Ng1315 | Ng728; - assign n8549 = n6522 & (Ng3139 | ~n8756); - assign n8550 = ~Ng548 | \[1605] | Ng8284; - assign n8551 = (~\[1605] & ~Ng1234) | (n6600 & (\[1605] | ~Ng1234)); - assign n8552 = (~\[1605] & ~Ng1928) | (n6601 & (\[1605] | ~Ng1928)); - assign n8553 = (~\[1605] & ~Ng2622) | (n6602_1 & (\[1605] | ~Ng2622)); - assign n8554 = (~n4776 & n8454) | (n4982 & (n4776 | n8454)); - assign n8555 = (~Pg3229 & Ng2615) | (Ng2612 & (Pg3229 | Ng2615)); - assign n8556 = n5649 ^ ~n5650_1; - assign n8557 = ~n8555 | Ng2631 | n6476; - assign n8558 = (~Pg3229 & Ng1921) | (Ng1918 & (Pg3229 | Ng1921)); - assign n8559 = n5637 ^ ~n5638; - assign n8560 = ~n8558 | Ng1937 | n6478; - assign n8561 = ~n4980 & (n6485_1 | (~n4643 & ~n5989)); - assign n8562 = n4976 & (n8561 | (n4980 & ~n6277)); - assign n8563 = ~n4976 & (n4970 | n5558); - assign n8564 = n4976 & ~n5558 & (~n4970 | n4980); - assign n8565 = ~n5445_1 | n8563 | n8564; - assign n8566 = ~n4974 & (n6495_1 | (~n4639 & ~n5997)); - assign n8567 = n4968_1 & (n8566 | (n4974 & ~n6278)); - assign n8568 = ~n4968_1 & (n4962 | n5556); - assign n8569 = n4968_1 & ~n5556 & (~n4962 | n4974); - assign n8570 = ~n5442 | n8568 | n8569; - assign n8571 = ~n4966 & (n6505_1 | (~n4633 & ~n6005)); - assign n8572 = n4960 & (n8571 | (n4966 & ~n6279)); - assign n8573 = ~n4960 & (n4956 | n5554); - assign n8574 = n4960 & ~n5554 & (~n4956 | n4966); - assign n8575 = ~n5439 | n8573 | n8574; - assign n8576 = ~n4958_1 & (n6515_1 | (~n4625 & ~n6013_1)); - assign n8577 = n4954 & (n8576 | (n4958_1 & ~n6280)); - assign n8578 = ~n4954 & (n4950 | n5552); - assign n8579 = n4954 & ~n5552 & (~n4950 | n4958_1); - assign n8580 = ~n5436 | n8578 | n8579; - assign n8581 = n4976 & (~n4980 | ~Ng2257 | n6483); - assign n8582 = n4968_1 & (~n4974 | ~Ng2257 | n6493); - assign n8583 = n4960 & (~n4966 | ~Ng2257 | n6503); - assign n8584 = n4954 & (~n4958_1 | ~Ng2257 | n6513); - assign n8585 = n4876_1 ^ ~n5928_1; - assign n8586 = n4720_1 ^ ~n5927; - assign n8587 = n4938_1 | n6488 | n6308_1; - assign n8588 = n8587 & (~n4938_1 | (~n6308_1 & ~n6488)); - assign n8589 = n4834_1 ^ ~n5935; - assign n8590 = n4696_1 ^ ~n5934; - assign n8591 = n4918 | n6498 | n6332; - assign n8592 = n8591 & (~n4918 | (~n6332 & ~n6498)); - assign n8593 = n4792_1 ^ ~n5942; - assign n8594 = n4676_1 ^ ~n5941; - assign n8595 = n4888_1 | n6508 | n6356; - assign n8596 = n8595 & (~n4888_1 | (~n6356 & ~n6508)); - assign n8597 = n4750 ^ ~n5949; - assign n8598 = n4662 ^ ~n5948_1; - assign n8599 = n4850 | n6518 | n6380; - assign n8600 = n8599 & (~n4850 | (~n6380 & ~n6518)); - assign n8601 = Ng506 | \[1603] | Pg16297; - assign n2064_1 = n8601 & (~Ng506 | Ng507); - assign n8603 = (\[1603] & n2064_1) | (Pg16355 & (~\[1603] | n2064_1)); - assign n3570_1 = (Ng1192 & Ng1193) | (n8603 & (~Ng1192 | Ng1193)); - assign n8605 = (\[1603] & n3570_1) | (Pg16399 & (~\[1603] | n3570_1)); - assign n8606 = (\[1603] & ~n5077) | (~Pg16437 & (~\[1603] | ~n5077)); - assign n8607 = Ng298 | Ng299; - assign n8608 = (~\[1594] & ~Ng992) | (n6934 & (\[1594] | ~Ng992)); - assign n8609 = (~\[1594] & ~Ng1686) | (n6936_1 & (\[1594] | ~Ng1686)); - assign n8610 = (~\[1594] & ~Ng2380) | (n6938 & (\[1594] | ~Ng2380)); - assign n8611 = (~Pg3229 & Ng1227) | (Ng1224 & (Pg3229 | Ng1227)); - assign n8612 = n5625_1 ^ ~n5626; - assign n8613 = ~n8611 | Ng1243 | n6520_1; - assign n8614 = ~n5445_1 | n5961; - assign n8615 = ~n5442 | n5964; - assign n8616 = ~n5439 | n5967; - assign n8617 = ~n5436 | n5970; - assign n8618 = (~Pg3229 & Ng541) | (Ng538 & (Pg3229 | Ng541)); - assign n8619 = n5613 ^ ~n5614; - assign n8620 = ~n8618 | Ng557 | n6526; - assign n8621 = n5034 ^ ~n5988_1; - assign n8622 = (n5990 & n6484) | (Ng2257 & (~n5990 | n6484)); - assign n8623 = Ng853 & n8622; - assign n8624 = \[1594] & n8622; - assign n8625 = \[1612] & n8622; - assign n8626 = n5022 ^ ~n5996; - assign n8627 = (n5998_1 & n6494) | (Ng2257 & (~n5998_1 | n6494)); - assign n8628 = Ng853 & n8627; - assign n8629 = \[1594] & n8627; - assign n8630 = \[1612] & n8627; - assign n8631 = n5010 ^ ~n6004; - assign n8632 = (n6006 & n6504) | (Ng2257 & (~n6006 | n6504)); - assign n8633 = Ng853 & n8632; - assign n8634 = \[1594] & n8632; - assign n8635 = \[1612] & n8632; - assign n8636 = n4998_1 ^ ~n6012; - assign n8637 = (n6014 & n6514) | (Ng2257 & (~n6014 | n6514)); - assign n8638 = Ng853 & n8637; - assign n8639 = \[1594] & n8637; - assign n8640 = \[1612] & n8637; - assign n8641 = n6020 | n5411; - assign n8642 = ~n5026 ^ ~n8641; - assign n8643 = n6024 | n5404; - assign n8644 = ~n5014 ^ ~n8643; - assign n8645 = n6028_1 | n5397; - assign n8646 = ~n5002 ^ ~n8645; - assign n8647 = n6032 | n5392; - assign n8648 = ~n4990 ^ ~n8647; - assign n8649 = n6555_1 | n4982; - assign n8650 = n8649 & (n6554 | ~n6555_1 | ~n7062); - assign n8651 = (n6555_1 & ~n7070) | (n5064 & (~n6555_1 | ~n7070)); - assign n8652 = n6555_1 | n4978_1; - assign n8653 = n8652 & (~n6555_1 | n6559 | ~n7078); - assign n8654 = (n6555_1 & ~n7086_1) | (n5062 & (~n6555_1 | ~n7086_1)); - assign n8655 = n6555_1 | n4972; - assign n8656 = n8655 & (~n6555_1 | n6563 | ~n7094); - assign n8657 = (n6555_1 & ~n7102) | (n5058_1 & (~n6555_1 | ~n7102)); - assign n8658 = n6555_1 | n4964; - assign n8659 = n8658 & (~n6555_1 | n6567 | ~n7110); - assign n8660 = (n6555_1 & ~n7118) | (n5054 & (~n6555_1 | ~n7118)); - assign n8661 = ~n4880_1 | n4908 | n6150; - assign n8662 = ~n4838_1 | n4870 | n6157; - assign n8663 = ~n4796_1 | n4828 | n6164; - assign n8664 = ~n4754 | n4786 | n6171_1; - assign n8665 = ~Ng1315 | n5156; - assign n8666 = n6048_1 & n8669; - assign n8667 = ~\[1603] | n5156; - assign n8668 = ~\[1605] | n5156; - assign n8669 = Pg3229 ^ ~n5008_1; - assign n8670 = ~n5008_1 & n5036 & (n5018_1 | ~n5028_1); - assign n8671 = Ng853 & n5138; - assign n8672 = n4906 & n4926 & n6389; - assign n8673 = \[1594] & n5138; - assign n8674 = \[1612] & n5138; - assign n8675 = ~n4878 & n4940 & (n4906 | ~n4926); - assign n8676 = ~Ng1315 | n5149; - assign n8677 = n6070 & n8680; - assign n8678 = ~\[1603] | n5149; - assign n8679 = ~\[1605] | n5149; - assign n8680 = Pg3229 ^ ~n4996; - assign n8681 = ~n4996 & n5024 & (n5006 | ~n5016); - assign n8682 = Ng853 & n5136; - assign n8683 = n4868 & n4896 & n6390; - assign n8684 = \[1594] & n5136; - assign n8685 = \[1612] & n5136; - assign n8686 = ~n4836 & n4920 & (n4868 | ~n4896); - assign n8687 = ~Ng1315 | n5147; - assign n8688 = n6092 & n8691; - assign n8689 = ~\[1603] | n5147; - assign n8690 = ~\[1605] | n5147; - assign n8691 = Pg3229 ^ ~n4988_1; - assign n8692 = ~n4988_1 & n5012 & (n4994 | ~n5004); - assign n8693 = Ng853 & n5132; - assign n8694 = n4826 & n4858 & n6391_1; - assign n8695 = \[1594] & n5132; - assign n8696 = \[1612] & n5132; - assign n8697 = ~n4794 & n4890 & (n4826 | ~n4858); - assign n8698 = ~Ng1315 | n5142; - assign n8699 = n6114 & n8702; - assign n8700 = ~\[1603] | n5142; - assign n8701 = ~\[1605] | n5142; - assign n8702 = Pg3229 ^ ~n4984; - assign n8703 = ~n4984 & n5000 & (n4986 | ~n4992); - assign n8704 = Ng853 & n5128; - assign n8705 = n4784 & n4816 & n6392; - assign n8706 = \[1594] & n5128; - assign n8707 = \[1612] & n5128; - assign n8708 = ~n4752_1 & n4852 & (n4784 | ~n4816); - assign n8709 = n4908 ^ ~n8755; - assign n8710 = n4880_1 ^ ~n8757; - assign n8711 = n4870 ^ ~n8754; - assign n8712 = n4838_1 ^ ~n8758; - assign n8713 = n4828 ^ ~n8753; - assign n8714 = n4796_1 ^ ~n8759; - assign n8715 = n4786 ^ ~n8752; - assign n8716 = n4754 ^ ~n8760; - assign n8717 = ~Ng2584 | ~n4581 | ~n4982; - assign n8718 = ~Ng853 | ~Ng2257; - assign n8719 = n4615 & ~n5989; - assign n8720 = ~\[1594] | ~Ng2257; - assign n8721 = ~\[1612] | ~Ng2257; - assign n8722 = ~Ng1890 | ~n4579 | ~n4978_1; - assign n8723 = n4603 & ~n5997; - assign n8724 = ~Ng1196 | ~n4577_1 | ~n4972; - assign n8725 = n4593 & ~n6005; - assign n8726 = ~Ng510 | ~n4575 | ~n4964; - assign n8727 = n4585 & ~n6013_1; - assign n8728 = Ng13475 ^ ~Ng2993; - assign n8729 = ~Ng853 | n6576; - assign n8730 = ~\[1594] | n6576; - assign n8731 = ~\[1612] | n6576; - assign n8732 = ~Ng2185 | Ng2190 | Ng2195 | ~Ng2200; - assign n8733 = ~Ng1491 | Ng1496 | Ng1501 | ~Ng1506; - assign n8734 = ~Ng801 | Ng805 | Ng809 | ~Ng813; - assign n8735 = ~Ng113 | Ng117 | Ng121 | ~Ng125; - assign n8736 = n6555_1 | n6064; - assign n8737 = n6555_1 | n5084; - assign n8738 = n6242 & n5230_1; - assign n8739 = n6555_1 | n6086; - assign n8740 = n6555_1 | n5081; - assign n8741 = n6555_1 | n6108; - assign n8742 = n6555_1 | n5078; - assign n8743 = n6555_1 | n6130; - assign n8744 = n6555_1 | n5075; - assign n8745 = Ng2985 | Ng2984; - assign n8746 = ~Ng3147 & (~n8549 | (~Ng3120 & n8745)); - assign n8747 = ~\[1594] | ~Ng2257; - assign n8748 = ~\[1612] | ~Ng2257; - assign n8749 = n6595 ^ ~n8761; - assign n8750 = Ng3006 | Ng3010 | Ng3024 | Ng3002 | Ng3013; - assign n5815 = ~n6576; - assign n8752 = n4583 | ~Ng2257 | n6571; - assign n8753 = n4591_1 | ~Ng2257 | n6570_1; - assign n8754 = n4601 | ~Ng2257 | n6569; - assign n8755 = n4613_1 | ~Ng2257 | n6568; - assign n8756 = Ng2991 | Ng2992; - assign n8757 = ~Ng2257 | n6585; - assign n8758 = ~Ng2257 | n6586; - assign n8759 = ~Ng2257 | n6587_1; - assign n8760 = ~Ng2257 | n6588; - assign n8761 = Pg3231 | ~Ng3139; - assign n8762 = Pg3231 | ~Ng3120; - assign n8763 = ~n6597_1 ^ ~n8761; - assign n8764 = ~n6389 & n4906 & n4940; - assign n8765 = ~n6390 & n4868 & n4920; - assign n8766 = ~n6391_1 & n4826 & n4890; - assign n8767 = ~n6392 & n4784 & n4852; - assign Pg25442 = n858_1; - assign Pg25420 = n858_1; - assign Pg8167 = \[1594] ; - assign Pg8106 = \[1605] ; - assign Pg8087 = \[1612] ; - assign Pg8082 = \[1594] ; - assign Pg8030 = \[1603] ; - assign Pg8012 = \[1612] ; - assign Pg8007 = \[1594] ; - assign Pg7961 = \[1612] ; - assign Pg7956 = \[1594] ; - assign Pg7909 = \[1612] ; - assign Pg7487 = \[1603] ; - assign Pg7425 = \[1605] ; - assign Pg7390 = \[1603] ; - assign Pg7357 = \[1603] ; - assign Pg7302 = \[1605] ; - assign Pg7264 = \[1594] ; - assign Pg7229 = \[1605] ; - assign Pg7194 = \[1603] ; - assign Pg7161 = \[1603] ; - assign Pg7084 = \[1594] ; - assign Pg7052 = \[1605] ; - assign Pg7014 = \[1594] ; - assign Pg6979 = \[1605] ; - assign Pg6944 = \[1603] ; - assign Pg6911 = \[1603] ; - assign Pg6837 = \[1612] ; - assign Pg6782 = \[1594] ; - assign Pg6750 = \[1605] ; - assign Pg6712 = \[1594] ; - assign Pg6677 = \[1605] ; - assign Pg6642 = \[1603] ; - assign Pg6573 = \[1612] ; - assign Pg6518 = \[1594] ; - assign Pg6485 = \[1605] ; - assign Pg6447 = \[1594] ; - assign Pg6368 = \[1612] ; - assign Pg6313 = \[1594] ; - assign Pg6231 = \[1612] ; - assign Pg5796 = \[1603] ; - assign Pg5747 = \[1605] ; - assign Pg5738 = \[1603] ; - assign Pg5695 = \[1605] ; - assign Pg5686 = \[1603] ; - assign Pg5657 = \[1605] ; - assign Pg5648 = \[1603] ; - assign Pg5637 = \[1609] ; - assign Pg5629 = \[1605] ; - assign Pg5612 = \[1609] ; - assign Pg5595 = \[1609] ; - assign Pg5555 = \[1612] ; - assign Pg5549 = \[1609] ; - assign Pg5511 = \[1612] ; - assign Pg5472 = \[1612] ; - assign Pg5437 = \[1612] ; - assign n270_1 = Pg51; - assign n353_1 = Pg8021; - assign n362_1 = Pg3212; - assign n366_1 = Pg3228; - assign n370_1 = Pg3227; - assign n374_1 = Pg3226; - assign n378_1 = Pg3225; - assign n382_1 = Pg3224; - assign n386 = Pg3223; - assign n390_1 = Pg3222; - assign n394 = Pg3221; - assign n398_1 = Pg3232; - assign n402_1 = Pg3220; - assign n406 = Pg3219; - assign n410_1 = Pg3218; - assign n414_1 = Pg3217; - assign n418_1 = Pg3216; - assign n422_1 = Pg3215; - assign n426_1 = Pg3214; - assign n430_1 = Pg3213; - assign n483_1 = Pg8251; - assign n491_1 = Pg4090; - assign n499_1 = Pg4323; - assign n507 = Pg4590; - assign n515_1 = Pg6225; - assign n523_1 = Pg6442; - assign n531_1 = Pg6895; - assign n539_1 = Pg7334; - assign n547_1 = Pg7519; - assign n555_1 = Pg8249; - assign n563_1 = Pg4088; - assign n571_1 = Pg4321; - assign n579 = Pg8023; - assign n587_1 = Pg8175; - assign n595_1 = Pg3993; - assign n603_1 = Pg4200; - assign n611_1 = Pg4450; - assign n619_1 = Pg8096; - assign n848_1 = Pg24734; - assign n872_1 = Pg26104; - assign n876_1 = Pg25435; - assign n880_1 = Pg27380; - assign n884_1 = Pg26149; - assign n888_1 = Pg26135; - assign n1537_1 = Ng450; - assign n1546_1 = Ng452; - assign n1555_1 = Ng454; - assign n1564 = Ng280; - assign n1573 = Ng282; - assign n1582_1 = Ng284; - assign n1591 = Ng286; - assign n1600_1 = Ng288; - assign n1604_1 = Ng13407; - assign n1608 = Ng290; - assign n1627_1 = Ng11497; - assign n1631 = Ng342; - assign n1635 = Ng11498; - assign n1639_1 = Ng350; - assign n1643 = Ng11499; - assign n1647_1 = Ng352; - assign n1651 = Ng11500; - assign n1655 = Ng357; - assign n1659_1 = Ng11501; - assign n1663_1 = Ng365; - assign n1667 = Ng11502; - assign n1671_1 = Ng367; - assign n1675_1 = Ng11503; - assign n1679_1 = Ng372; - assign n1683_1 = Ng11504; - assign n1687_1 = Ng380; - assign n1691_1 = Ng11505; - assign n1695 = Ng382; - assign n1699_1 = Ng11506; - assign n1703 = Ng387; - assign n1707 = Ng11507; - assign n1711_1 = Ng395; - assign n1715 = Ng11508; - assign n1719 = Ng397; - assign n1743 = Ng513; - assign n1747 = Ng523; - assign n1752_1 = Ng11512; - assign n1756 = Ng564; - assign n1761_1 = Ng11515; - assign n1765 = Ng570; - assign n1770_1 = Ng11516; - assign n1774_1 = Ng572; - assign n1779_1 = Ng11517; - assign n1783_1 = Ng574; - assign n1788 = Ng11513; - assign n1792_1 = Ng566; - assign n1797_1 = Ng11514; - assign n1801_1 = Ng568; - assign n1879_1 = Ng528; - assign n1883_1 = Ng535; - assign n1892 = Ng543; - assign n1906_1 = Ng549; - assign n1915_1 = Ng558; - assign n2054_1 = Ng8284; - assign n2067 = Pg16297; - assign n2391 = Ng13457; - assign n2395_1 = \[1612] ; - assign n2399 = \[1594] ; - assign n3043_1 = Ng1137; - assign n3052_1 = Ng1139; - assign n3061_1 = Ng1141; - assign n3070 = Ng967; - assign n3079_1 = Ng969; - assign n3088_1 = Ng971; - assign n3097_1 = Ng973; - assign n3106_1 = Ng975; - assign n3110_1 = Ng13423; - assign n3114_1 = Ng977; - assign n3133_1 = Ng11524; - assign n3137_1 = Ng1029; - assign n3141_1 = Ng11525; - assign n3145_1 = Ng1037; - assign n3149_1 = Ng11526; - assign n3153_1 = Ng1039; - assign n3157_1 = Ng11527; - assign n3161_1 = Ng1044; - assign n3165_1 = Ng11528; - assign n3169_1 = Ng1052; - assign n3173_1 = Ng11529; - assign n3177_1 = Ng1054; - assign n3181_1 = Ng11530; - assign n3185_1 = Ng1059; - assign n3189_1 = Ng11531; - assign n3193_1 = Ng1067; - assign n3197_1 = Ng11532; - assign n3201_1 = Ng1069; - assign n3205_1 = Ng11533; - assign n3209_1 = Ng1074; - assign n3213_1 = Ng11534; - assign n3217_1 = Ng1082; - assign n3221_1 = Ng11535; - assign n3225_1 = Ng1084; - assign n3249_1 = Ng1199; - assign n3253_1 = Ng1209; - assign n3258_1 = Ng11539; - assign n3262_1 = Ng1250; - assign n3267_1 = Ng11542; - assign n3271_1 = Ng1256; - assign n3276_1 = Ng11543; - assign n3280_1 = Ng1258; - assign n3285_1 = Ng11544; - assign n3289_1 = Ng1260; - assign n3294_1 = Ng11540; - assign n3298_1 = Ng1252; - assign n3303_1 = Ng11541; - assign n3307_1 = Ng1254; - assign n3385_1 = Ng1214; - assign n3389_1 = Ng1221; - assign n3398_1 = Ng1229; - assign n3412_1 = Ng1235; - assign n3421_1 = Ng1244; - assign n3560_1 = Ng8293; - assign n3573_1 = Pg16355; - assign n3628_1 = Ng13475; - assign n3632_1 = \[1605] ; - assign n3636_1 = \[1603] ; - assign n4550 = Ng1831; - assign n4559 = Ng1833; - assign n4568 = Ng1835; - assign n4577 = Ng1661; - assign n4586 = Ng1663; - assign n4595 = Ng1665; - assign n4604 = Ng1667; - assign n4613 = Ng1669; - assign n4617 = Ng13439; - assign n4621 = Ng1671; - assign n4640 = Ng11551; - assign n4644_1 = Ng1723; - assign n4648 = Ng11552; - assign n4652 = Ng1731; - assign n4656 = Ng11553; - assign n4660 = Ng1733; - assign n4664 = Ng11554; - assign n4668 = Ng1738; - assign n4672 = Ng11555; - assign n4676 = Ng1746; - assign n4680 = Ng11556; - assign n4684 = Ng1748; - assign n4688 = Ng11557; - assign n4692 = Ng1753; - assign n4696 = Ng11558; - assign n4700 = Ng1761; - assign n4704 = Ng11559; - assign n4708 = Ng1763; - assign n4712 = Ng11560; - assign n4716 = Ng1768; - assign n4720 = Ng11561; - assign n4724 = Ng1776; - assign n4728 = Ng11562; - assign n4732 = Ng1778; - assign n4756 = Ng1893; - assign n4760 = Ng1903; - assign n4765 = Ng11566; - assign n4769 = Ng1944; - assign n4774 = Ng11569; - assign n4778 = Ng1950; - assign n4783 = Ng11570; - assign n4787 = Ng1952; - assign n4792 = Ng11571; - assign n4796 = Ng1954; - assign n4801 = Ng11567; - assign n4805 = Ng1946; - assign n4810 = Ng11568; - assign n4814 = Ng1948; - assign n4892 = Ng1908; - assign n4896_1 = Ng1915; - assign n4905_1 = Ng1923; - assign n4919 = Ng1929; - assign n4928 = Ng1938; - assign n5067 = Ng8302; - assign n5080 = Pg16399; - assign n5819 = Ng2256; - assign n5823 = \[1609] ; - assign n6057 = Ng2525; - assign n6066 = Ng2527; - assign n6075 = Ng2529; - assign n6084 = Ng2355; - assign n6093 = Ng2357; - assign n6102 = Ng2359; - assign n6111 = Ng2361; - assign n6120 = Ng2363; - assign n6124 = Ng13455; - assign n6128 = Ng2365; - assign n6147 = Ng11578; - assign n6151 = Ng2417; - assign n6155 = Ng11579; - assign n6159 = Ng2425; - assign n6163 = Ng11580; - assign n6167 = Ng2427; - assign n6171 = Ng11581; - assign n6175 = Ng2432; - assign n6179 = Ng11582; - assign n6183 = Ng2440; - assign n6187 = Ng11583; - assign n6191 = Ng2442; - assign n6195 = Ng11584; - assign n6199 = Ng2447; - assign n6203 = Ng11585; - assign n6207 = Ng2455; - assign n6211 = Ng11586; - assign n6215 = Ng2457; - assign n6219 = Ng11587; - assign n6223 = Ng2462; - assign n6227 = Ng11588; - assign n6231 = Ng2470; - assign n6235 = Ng11589; - assign n6239 = Ng2472; - assign n6263 = Ng2587; - assign n6267 = Ng2597; - assign n6272 = Ng11593; - assign n6276 = Ng2638; - assign n6281 = Ng11596; - assign n6285 = Ng2644; - assign n6290 = Ng11597; - assign n6294 = Ng2646; - assign n6299 = Ng11598; - assign n6303 = Ng2648; - assign n6308 = Ng11594; - assign n6312 = Ng2640; - assign n6317 = Ng11595; - assign n6321 = Ng2642; - assign n6399 = Ng2602; - assign n6403 = Ng2609; - assign n6412 = Ng2617; - assign n6426 = Ng2623; - assign n6435 = Ng2632; - assign n6574 = Ng8311; - assign n6587 = Pg16437; - assign n7160 = Pg3234; - assign n7163 = Pg5388; - assign n7167 = Pg16496; - always @ (posedge clock) begin - Pg8021 <= n270_1; - Ng2817 <= n274_1; - Ng2933 <= n279_1; - Ng13457 <= n284_1; - Ng2883 <= n289_1; - Ng2888 <= n294_1; - Ng2896 <= n299_1; - Ng2892 <= n304_1; - Ng2903 <= n309_1; - Ng2900 <= n314_1; - Ng2908 <= n319_1; - Ng2912 <= n324_1; - Ng2917 <= n329; - Ng2924 <= n334_1; - Ng2920 <= n339; - Ng2984 <= n344; - Ng2985 <= n349_1; - Ng2929 <= n353_1; - Ng2879 <= n358_1; - Ng2934 <= n362_1; - Ng2935 <= n366_1; - Ng2938 <= n370_1; - Ng2941 <= n374_1; - Ng2944 <= n378_1; - Ng2947 <= n382_1; - Ng2953 <= n386; - Ng2956 <= n390_1; - Ng2959 <= n394; - Ng2962 <= n398_1; - Ng2963 <= n402_1; - Ng2966 <= n406; - Ng2969 <= n410_1; - Ng2972 <= n414_1; - Ng2975 <= n418_1; - Ng2978 <= n422_1; - Ng2981 <= n426_1; - Ng2874 <= n430_1; - Ng1506 <= n435_1; - Ng1501 <= n440_1; - Ng1496 <= n445_1; - Ng1491 <= n450_1; - Ng1486 <= n455_1; - Ng1481 <= n460_1; - Ng1476 <= n465; - Ng1471 <= n470_1; - Ng13439 <= n475_1; - Pg8251 <= n480_1; - Ng813 <= n483_1; - Pg4090 <= n488_1; - Ng809 <= n491_1; - Pg4323 <= n496_1; - Ng805 <= n499_1; - Pg4590 <= n504_1; - Ng801 <= n507; - Pg6225 <= n512_1; - Ng797 <= n515_1; - Pg6442 <= n520_1; - Ng793 <= n523_1; - Pg6895 <= n528_1; - Ng789 <= n531_1; - Pg7334 <= n536_1; - Ng785 <= n539_1; - Pg7519 <= n544_1; - Ng13423 <= n547_1; - Pg8249 <= n552_1; - Ng125 <= n555_1; - Pg4088 <= n560_1; - Ng121 <= n563_1; - Pg4321 <= n568_1; - Ng117 <= n571_1; - Pg8023 <= n576_1; - Ng113 <= n579; - Pg8175 <= n584_1; - Ng109 <= n587_1; - Pg3993 <= n592_1; - Ng105 <= n595_1; - Pg4200 <= n600_1; - Ng101 <= n603_1; - Pg4450 <= n608_1; - Ng97 <= n611_1; - Pg8096 <= n616; - Ng13407 <= n619_1; - Ng2200 <= n624_1; - Ng2195 <= n629_1; - Ng2190 <= n634_1; - Ng2185 <= n639_1; - Ng2180 <= n644_1; - Ng2175 <= n649_1; - Ng2170 <= n654_1; - Ng2165 <= n659_1; - Ng13455 <= n664_1; - Ng3210 <= n669_1; - Ng3211 <= n674; - Ng3084 <= n679_1; - Ng3085 <= n684_1; - Ng3086 <= n689_1; - Ng3087 <= n694; - Ng3091 <= n699_1; - Ng3092 <= n704_1; - Ng3093 <= n709_1; - Ng3094 <= n714_1; - Ng3095 <= n719_1; - Ng3096 <= n724_1; - Ng3097 <= n729; - Ng3098 <= n734_1; - Ng3099 <= n739_1; - Ng3100 <= n744_1; - Ng3101 <= n749_1; - Ng3102 <= n754_1; - Ng3103 <= n759_1; - Ng3104 <= n764_1; - Ng3105 <= n769_1; - Ng3106 <= n774; - Ng3107 <= n779; - Ng3108 <= n784_1; - Ng3155 <= n789_1; - Ng3158 <= n794_1; - Ng3161 <= n799_1; - Ng3164 <= n804_1; - Ng3167 <= n809_1; - Ng3170 <= n814_1; - Ng3173 <= n819_1; - Ng3176 <= n824_1; - Ng3179 <= n829_1; - Ng3182 <= n834_1; - Ng3185 <= n839_1; - Ng3088 <= n844_1; - Ng3191 <= n848_1; - Ng3128 <= n853_1; - Ng3126 <= n858_1; - Ng3125 <= n863_1; - Ng3123 <= n868_1; - Ng3120 <= n872_1; - Ng3110 <= n876_1; - Ng3139 <= n880_1; - Ng3135 <= n884_1; - Ng3147 <= n888_1; - Ng185 <= n893_1; - Ng130 <= n898_1; - Ng131 <= n903_1; - Ng129 <= n908_1; - Ng133 <= n913_1; - Ng134 <= n918_1; - Ng132 <= n923_1; - Ng142 <= n928; - Ng143 <= n933_1; - Ng141 <= n938_1; - Ng145 <= n943_1; - Ng146 <= n948_1; - Ng144 <= n953_1; - Ng148 <= n958; - Ng149 <= n963_1; - Ng147 <= n968_1; - Ng151 <= n973_1; - Ng152 <= n978_1; - Ng150 <= n983_1; - Ng154 <= n988_1; - Ng155 <= n993_1; - Ng153 <= n998; - Ng157 <= n1003; - Ng158 <= n1008_1; - Ng156 <= n1013_1; - Ng160 <= n1018; - Ng161 <= n1023_1; - Ng159 <= n1028_1; - Ng163 <= n1033; - Ng164 <= n1038_1; - Ng162 <= n1043_1; - Ng169 <= n1048; - Ng170 <= n1053; - Ng168 <= n1058_1; - Ng172 <= n1063; - Ng173 <= n1068_1; - Ng171 <= n1073_1; - Ng175 <= n1078_1; - Ng176 <= n1083_1; - Ng174 <= n1088_1; - Ng178 <= n1093_1; - Ng179 <= n1098_1; - Ng177 <= n1103_1; - Ng186 <= n1108; - Ng189 <= n1113_1; - Ng192 <= n1118_1; - Ng231 <= n1123_1; - Ng234 <= n1128_1; - Ng237 <= n1133_1; - Ng195 <= n1138_1; - Ng198 <= n1143_1; - Ng201 <= n1148_1; - Ng240 <= n1153_1; - Ng243 <= n1158_1; - Ng246 <= n1163_1; - Ng204 <= n1168_1; - Ng207 <= n1173_1; - Ng210 <= n1178; - Ng249 <= n1183_1; - Ng252 <= n1188_1; - Ng255 <= n1193_1; - Ng213 <= n1198_1; - Ng216 <= n1203_1; - Ng219 <= n1208_1; - Ng258 <= n1213_1; - Ng261 <= n1218_1; - Ng264 <= n1223_1; - Ng222 <= n1228_1; - Ng225 <= n1233_1; - Ng228 <= n1238_1; - Ng267 <= n1243_1; - Ng270 <= n1248_1; - Ng273 <= n1253_1; - Ng92 <= n1258_1; - Ng88 <= n1263_1; - Ng83 <= n1268; - Ng79 <= n1273_1; - Ng74 <= n1278; - Ng70 <= n1283_1; - Ng65 <= n1288; - Ng61 <= n1293_1; - Ng56 <= n1298; - Ng52 <= n1303; - Ng11497 <= n1308_1; - Ng11498 <= n1313; - Ng11499 <= n1318; - Ng11500 <= n1323_1; - Ng11501 <= n1328_1; - Ng11502 <= n1333_1; - Ng11503 <= n1338_1; - Ng11504 <= n1343_1; - Ng11505 <= n1348; - Ng11506 <= n1353; - Ng11507 <= n1358_1; - Ng11508 <= n1363_1; - Ng408 <= n1368; - Ng411 <= n1373_1; - Ng414 <= n1378_1; - Ng417 <= n1383; - Ng420 <= n1388; - Ng423 <= n1393; - Ng427 <= n1398_1; - Ng428 <= n1403; - Ng426 <= n1408_1; - Ng429 <= n1413; - Ng432 <= n1418_1; - Ng435 <= n1423_1; - Ng438 <= n1428_1; - Ng441 <= n1433_1; - Ng444 <= n1438_1; - Ng448 <= n1443_1; - Ng449 <= n1448_1; - Ng447 <= n1453; - Ng312 <= n1458_1; - Ng313 <= n1463_1; - Ng314 <= n1468_1; - Ng315 <= n1473_1; - Ng316 <= n1478_1; - Ng317 <= n1483_1; - Ng318 <= n1488_1; - Ng319 <= n1493; - Ng320 <= n1498; - Ng322 <= n1503; - Ng323 <= n1508; - Ng321 <= n1513_1; - Ng403 <= n1518_1; - Ng404 <= n1523_1; - Ng402 <= n1528; - Ng450 <= n1533_1; - Ng451 <= n1537_1; - Ng452 <= n1542_1; - Ng453 <= n1546_1; - Ng454 <= n1551_1; - Ng279 <= n1555_1; - Ng280 <= n1560_1; - Ng281 <= n1564; - Ng282 <= n1569_1; - Ng283 <= n1573; - Ng284 <= n1578; - Ng285 <= n1582_1; - Ng286 <= n1587; - Ng287 <= n1591; - Ng288 <= n1596; - Ng289 <= n1600_1; - Ng290 <= n1604_1; - Ng291 <= n1608; - Ng299 <= n1613; - Ng305 <= n1618_1; - Ng298 <= n1623_1; - Ng342 <= n1627_1; - Ng349 <= n1631; - Ng350 <= n1635; - Ng351 <= n1639_1; - Ng352 <= n1643; - Ng353 <= n1647_1; - Ng357 <= n1651; - Ng364 <= n1655; - Ng365 <= n1659_1; - Ng366 <= n1663_1; - Ng367 <= n1667; - Ng368 <= n1671_1; - Ng372 <= n1675_1; - Ng379 <= n1679_1; - Ng380 <= n1683_1; - Ng381 <= n1687_1; - Ng382 <= n1691_1; - Ng383 <= n1695; - Ng387 <= n1699_1; - Ng394 <= n1703; - Ng395 <= n1707; - Ng396 <= n1711_1; - Ng397 <= n1715; - Ng324 <= n1719; - Ng554 <= n1724_1; - Ng557 <= n1729_1; - Ng510 <= n1734_1; - Ng513 <= n1739_1; - Ng523 <= n1743; - Ng524 <= n1747; - Ng564 <= n1752_1; - Ng569 <= n1756; - Ng570 <= n1761_1; - Ng571 <= n1765; - Ng572 <= n1770_1; - Ng573 <= n1774_1; - Ng574 <= n1779_1; - Ng565 <= n1783_1; - Ng566 <= n1788; - Ng567 <= n1792_1; - Ng568 <= n1797_1; - Ng489 <= n1801_1; - Ng486 <= n1806_1; - Ng487 <= n1811_1; - Ng488 <= n1816_1; - Ng11512 <= n1821_1; - Ng11515 <= n1825_1; - Ng11516 <= n1829; - Ng477 <= n1833; - Ng478 <= n1838; - Ng479 <= n1843_1; - Ng480 <= n1848; - Ng484 <= n1853_1; - Ng464 <= n1858_1; - Ng11517 <= n1863; - Ng11513 <= n1867_1; - Ng11514 <= n1871_1; - Ng528 <= n1875_1; - Ng535 <= n1879_1; - Ng542 <= n1883_1; - Ng543 <= n1888; - Ng544 <= n1892; - Ng548 <= n1897_1; - Ng549 <= n1902_1; - Ng8284 <= n1906_1; - Ng558 <= n1911_1; - Ng559 <= n1915_1; - Ng576 <= n1920_1; - Ng577 <= n1925; - Ng575 <= n1930_1; - Ng579 <= n1935_1; - Ng580 <= n1940_1; - Ng578 <= n1945_1; - Ng582 <= n1950; - Ng583 <= n1955; - Ng581 <= n1960_1; - Ng585 <= n1965; - Ng586 <= n1970_1; - Ng584 <= n1975; - Ng587 <= n1980; - Ng590 <= n1985; - Ng593 <= n1990_1; - Ng596 <= n1995_1; - Ng599 <= n2000_1; - Ng602 <= n2005_1; - Ng614 <= n2010; - Ng617 <= n2015_1; - Ng620 <= n2020_1; - Ng605 <= n2025_1; - Ng608 <= n2030; - Ng611 <= n2035_1; - Ng490 <= n2040; - Ng493 <= n2045_1; - Ng496 <= n2050_1; - Ng506 <= n2054_1; - Ng507 <= n2059_1; - Pg16297 <= n2064_1; - Ng525 <= n2067; - Ng529 <= n2072_1; - Ng530 <= n2077_1; - Ng531 <= n2082; - Ng532 <= n2087_1; - Ng533 <= n2092_1; - Ng534 <= n2097_1; - Ng536 <= n2102_1; - Ng537 <= n2107_1; - Ng538 <= n2112; - Ng541 <= n2117_1; - Ng630 <= n2122_1; - Ng659 <= n2127_1; - Ng640 <= n2132; - Ng633 <= n2137; - Ng653 <= n2142_1; - Ng646 <= n2147_1; - Ng660 <= n2152_1; - Ng672 <= n2157_1; - Ng666 <= n2162_1; - Ng679 <= n2167_1; - Ng686 <= n2172_1; - Ng692 <= n2177; - Ng699 <= n2182_1; - Ng700 <= n2187_1; - Ng698 <= n2192_1; - Ng702 <= n2197; - Ng703 <= n2202; - Ng701 <= n2207_1; - Ng705 <= n2212_1; - Ng706 <= n2217_1; - Ng704 <= n2222; - Ng708 <= n2227_1; - Ng709 <= n2232; - Ng707 <= n2237_1; - Ng711 <= n2242; - Ng712 <= n2247_1; - Ng710 <= n2252; - Ng714 <= n2257_1; - Ng715 <= n2262; - Ng713 <= n2267; - Ng717 <= n2272; - Ng718 <= n2277; - Ng716 <= n2282; - Ng720 <= n2287; - Ng721 <= n2292; - Ng719 <= n2297_1; - Ng723 <= n2302; - Ng724 <= n2307; - Ng722 <= n2312; - Ng726 <= n2317; - Ng727 <= n2322; - Ng725 <= n2327_1; - Ng729 <= n2332_1; - Ng730 <= n2337; - Ng728 <= n2342; - Ng732 <= n2347; - Ng733 <= n2352; - Ng731 <= n2357; - Ng735 <= n2362_1; - Ng736 <= n2367_1; - Ng734 <= n2372; - Ng738 <= n2377; - Ng739 <= n2382; - Ng737 <= n2387; - \[1612] <= n2391; - \[1594] <= n2395_1; - Ng853 <= n2399; - Ng818 <= n2404; - Ng819 <= n2409; - Ng817 <= n2414; - Ng821 <= n2419; - Ng822 <= n2424_1; - Ng820 <= n2429_1; - Ng830 <= n2434; - Ng831 <= n2439; - Ng829 <= n2444_1; - Ng833 <= n2449; - Ng834 <= n2454; - Ng832 <= n2459; - Ng836 <= n2464; - Ng837 <= n2469; - Ng835 <= n2474; - Ng839 <= n2479; - Ng840 <= n2484; - Ng838 <= n2489_1; - Ng842 <= n2494; - Ng843 <= n2499_1; - Ng841 <= n2504_1; - Ng845 <= n2509; - Ng846 <= n2514_1; - Ng844 <= n2519_1; - Ng848 <= n2524_1; - Ng849 <= n2529; - Ng847 <= n2534_1; - Ng851 <= n2539; - Ng852 <= n2544; - Ng850 <= n2549; - Ng857 <= n2554; - Ng858 <= n2559; - Ng856 <= n2564; - Ng860 <= n2569; - Ng861 <= n2574; - Ng859 <= n2579; - Ng863 <= n2584_1; - Ng864 <= n2589; - Ng862 <= n2594; - Ng866 <= n2599_1; - Ng867 <= n2604; - Ng865 <= n2609; - Ng873 <= n2614; - Ng876 <= n2619_1; - Ng879 <= n2624; - Ng918 <= n2629; - Ng921 <= n2634; - Ng924 <= n2639; - Ng882 <= n2644; - Ng885 <= n2649; - Ng888 <= n2654; - Ng927 <= n2659; - Ng930 <= n2664; - Ng933 <= n2669; - Ng891 <= n2674; - Ng894 <= n2679; - Ng897 <= n2684; - Ng936 <= n2689; - Ng939 <= n2694_1; - Ng942 <= n2699_1; - Ng900 <= n2704_1; - Ng903 <= n2709; - Ng906 <= n2714_1; - Ng945 <= n2719; - Ng948 <= n2724_1; - Ng951 <= n2729_1; - Ng909 <= n2734_1; - Ng912 <= n2739_1; - Ng915 <= n2744_1; - Ng954 <= n2749_1; - Ng957 <= n2754_1; - Ng960 <= n2759_1; - Ng780 <= n2764_1; - Ng776 <= n2769_1; - Ng771 <= n2774_1; - Ng767 <= n2779_1; - Ng762 <= n2784_1; - Ng758 <= n2789_1; - Ng753 <= n2794_1; - Ng749 <= n2799_1; - Ng744 <= n2804_1; - Ng740 <= n2809_1; - Ng11524 <= n2814_1; - Ng11525 <= n2819_1; - Ng11526 <= n2824_1; - Ng11527 <= n2829_1; - Ng11528 <= n2834_1; - Ng11529 <= n2839_1; - Ng11530 <= n2844_1; - Ng11531 <= n2849_1; - Ng11532 <= n2854_1; - Ng11533 <= n2859_1; - Ng11534 <= n2864_1; - Ng11535 <= n2869_1; - Ng1095 <= n2874_1; - Ng1098 <= n2879_1; - Ng1101 <= n2884_1; - Ng1104 <= n2889; - Ng1107 <= n2894; - Ng1110 <= n2899; - Ng1114 <= n2904; - Ng1115 <= n2909_1; - Ng1113 <= n2914_1; - Ng1116 <= n2919_1; - Ng1119 <= n2924_1; - Ng1122 <= n2929_1; - Ng1125 <= n2934_1; - Ng1128 <= n2939_1; - Ng1131 <= n2944_1; - Ng1135 <= n2949_1; - Ng1136 <= n2954_1; - Ng1134 <= n2959_1; - Ng999 <= n2964_1; - Ng1000 <= n2969_1; - Ng1001 <= n2974_1; - Ng1002 <= n2979_1; - Ng1003 <= n2984_1; - Ng1004 <= n2989_1; - Ng1005 <= n2994_1; - Ng1006 <= n2999; - Ng1007 <= n3004_1; - Ng1009 <= n3009_1; - Ng1010 <= n3014; - Ng1008 <= n3019_1; - Ng1090 <= n3024_1; - Ng1091 <= n3029_1; - Ng1089 <= n3034_1; - Ng1137 <= n3039_1; - Ng1138 <= n3043_1; - Ng1139 <= n3048_1; - Ng1140 <= n3052_1; - Ng1141 <= n3057_1; - Ng966 <= n3061_1; - Ng967 <= n3066_1; - Ng968 <= n3070; - Ng969 <= n3075; - Ng970 <= n3079_1; - Ng971 <= n3084_1; - Ng972 <= n3088_1; - Ng973 <= n3093_1; - Ng974 <= n3097_1; - Ng975 <= n3102; - Ng976 <= n3106_1; - Ng977 <= n3110_1; - Ng978 <= n3114_1; - Ng986 <= n3119_1; - Ng992 <= n3124_1; - Ng985 <= n3129_1; - Ng1029 <= n3133_1; - Ng1036 <= n3137_1; - Ng1037 <= n3141_1; - Ng1038 <= n3145_1; - Ng1039 <= n3149_1; - Ng1040 <= n3153_1; - Ng1044 <= n3157_1; - Ng1051 <= n3161_1; - Ng1052 <= n3165_1; - Ng1053 <= n3169_1; - Ng1054 <= n3173_1; - Ng1055 <= n3177_1; - Ng1059 <= n3181_1; - Ng1066 <= n3185_1; - Ng1067 <= n3189_1; - Ng1068 <= n3193_1; - Ng1069 <= n3197_1; - Ng1070 <= n3201_1; - Ng1074 <= n3205_1; - Ng1081 <= n3209_1; - Ng1082 <= n3213_1; - Ng1083 <= n3217_1; - Ng1084 <= n3221_1; - Ng1011 <= n3225_1; - Ng1240 <= n3230_1; - Ng1243 <= n3235_1; - Ng1196 <= n3240_1; - Ng1199 <= n3245_1; - Ng1209 <= n3249_1; - Ng1210 <= n3253_1; - Ng1250 <= n3258_1; - Ng1255 <= n3262_1; - Ng1256 <= n3267_1; - Ng1257 <= n3271_1; - Ng1258 <= n3276_1; - Ng1259 <= n3280_1; - Ng1260 <= n3285_1; - Ng1251 <= n3289_1; - Ng1252 <= n3294_1; - Ng1253 <= n3298_1; - Ng1254 <= n3303_1; - Ng1176 <= n3307_1; - Ng1173 <= n3312_1; - Ng1174 <= n3317_1; - Ng1175 <= n3322_1; - Ng11539 <= n3327_1; - Ng11542 <= n3331_1; - Ng11543 <= n3335_1; - Ng1164 <= n3339_1; - Ng1165 <= n3344_1; - Ng1166 <= n3349_1; - Ng1167 <= n3354_1; - Ng1171 <= n3359_1; - Ng1151 <= n3364_1; - Ng11544 <= n3369_1; - Ng11540 <= n3373_1; - Ng11541 <= n3377_1; - Ng1214 <= n3381_1; - Ng1221 <= n3385_1; - Ng1228 <= n3389_1; - Ng1229 <= n3394_1; - Ng1230 <= n3398_1; - Ng1234 <= n3403_1; - Ng1235 <= n3408_1; - Ng8293 <= n3412_1; - Ng1244 <= n3417_1; - Ng1245 <= n3421_1; - Ng1262 <= n3426_1; - Ng1263 <= n3431_1; - Ng1261 <= n3436_1; - Ng1265 <= n3441_1; - Ng1266 <= n3446_1; - Ng1264 <= n3451_1; - Ng1268 <= n3456_1; - Ng1269 <= n3461_1; - Ng1267 <= n3466_1; - Ng1271 <= n3471_1; - Ng1272 <= n3476_1; - Ng1270 <= n3481_1; - Ng1273 <= n3486_1; - Ng1276 <= n3491_1; - Ng1279 <= n3496_1; - Ng1282 <= n3501_1; - Ng1285 <= n3506_1; - Ng1288 <= n3511_1; - Ng1300 <= n3516_1; - Ng1303 <= n3521_1; - Ng1306 <= n3526_1; - Ng1291 <= n3531_1; - Ng1294 <= n3536_1; - Ng1297 <= n3541_1; - Ng1177 <= n3546_1; - Ng1180 <= n3551_1; - Ng1183 <= n3556_1; - Ng1192 <= n3560_1; - Ng1193 <= n3565_1; - Pg16355 <= n3570_1; - Ng1211 <= n3573_1; - Ng1215 <= n3578_1; - Ng1216 <= n3583_1; - Ng1217 <= n3588_1; - Ng1218 <= n3593_1; - Ng1219 <= n3598_1; - Ng1220 <= n3603_1; - Ng1222 <= n3608_1; - Ng1223 <= n3613_1; - Ng1224 <= n3618_1; - Ng1227 <= n3623_1; - \[1605] <= n3628_1; - \[1603] <= n3632_1; - Ng1315 <= n3636_1; - Ng1316 <= n3641_1; - Ng1345 <= n3646_1; - Ng1326 <= n3651_1; - Ng1319 <= n3656_1; - Ng1339 <= n3661_1; - Ng1332 <= n3666_1; - Ng1346 <= n3671_1; - Ng1358 <= n3676_1; - Ng1352 <= n3681_1; - Ng1365 <= n3686_1; - Ng1372 <= n3691_1; - Ng1378 <= n3696_1; - Ng1385 <= n3701_1; - Ng1386 <= n3706_1; - Ng1384 <= n3711_1; - Ng1388 <= n3716_1; - Ng1389 <= n3721_1; - Ng1387 <= n3726_1; - Ng1391 <= n3731_1; - Ng1392 <= n3736_1; - Ng1390 <= n3741_1; - Ng1394 <= n3746_1; - Ng1395 <= n3751_1; - Ng1393 <= n3756_1; - Ng1397 <= n3761; - Ng1398 <= n3766_1; - Ng1396 <= n3771; - Ng1400 <= n3776_1; - Ng1401 <= n3781_1; - Ng1399 <= n3786; - Ng1403 <= n3791; - Ng1404 <= n3796_1; - Ng1402 <= n3801; - Ng1406 <= n3806; - Ng1407 <= n3811_1; - Ng1405 <= n3816; - Ng1409 <= n3821; - Ng1410 <= n3826_1; - Ng1408 <= n3831_1; - Ng1412 <= n3836_1; - Ng1413 <= n3841_1; - Ng1411 <= n3846_1; - Ng1415 <= n3851_1; - Ng1416 <= n3856_1; - Ng1414 <= n3861_1; - Ng1418 <= n3866; - Ng1419 <= n3871_1; - Ng1417 <= n3876_1; - Ng1421 <= n3881_1; - Ng1422 <= n3886_1; - Ng1420 <= n3891; - Ng1424 <= n3896; - Ng1425 <= n3901; - Ng1423 <= n3906; - Ng1512 <= n3911; - Ng1513 <= n3916_1; - Ng1511 <= n3921; - Ng1515 <= n3926_1; - Ng1516 <= n3931; - Ng1514 <= n3936; - Ng1524 <= n3941_1; - Ng1525 <= n3946; - Ng1523 <= n3951; - Ng1527 <= n3956; - Ng1528 <= n3961_1; - Ng1526 <= n3966; - Ng1530 <= n3971; - Ng1531 <= n3976; - Ng1529 <= n3981; - Ng1533 <= n3986; - Ng1534 <= n3991; - Ng1532 <= n3996_1; - Ng1536 <= n4001_1; - Ng1537 <= n4006_1; - Ng1535 <= n4011_1; - Ng1539 <= n4016_1; - Ng1540 <= n4021; - Ng1538 <= n4026; - Ng1542 <= n4031_1; - Ng1543 <= n4036; - Ng1541 <= n4041_1; - Ng1545 <= n4046; - Ng1546 <= n4051; - Ng1544 <= n4056; - Ng1551 <= n4061; - Ng1552 <= n4066_1; - Ng1550 <= n4071_1; - Ng1554 <= n4076; - Ng1555 <= n4081_1; - Ng1553 <= n4086_1; - Ng1557 <= n4091; - Ng1558 <= n4096_1; - Ng1556 <= n4101; - Ng1560 <= n4106; - Ng1561 <= n4111_1; - Ng1559 <= n4116_1; - Ng1567 <= n4121; - Ng1570 <= n4126; - Ng1573 <= n4131; - Ng1612 <= n4136_1; - Ng1615 <= n4141; - Ng1618 <= n4146; - Ng1576 <= n4151; - Ng1579 <= n4156; - Ng1582 <= n4161; - Ng1621 <= n4166; - Ng1624 <= n4171; - Ng1627 <= n4176; - Ng1585 <= n4181_1; - Ng1588 <= n4186; - Ng1591 <= n4191_1; - Ng1630 <= n4196; - Ng1633 <= n4201; - Ng1636 <= n4206; - Ng1594 <= n4211; - Ng1597 <= n4216; - Ng1600 <= n4221; - Ng1639 <= n4226; - Ng1642 <= n4231; - Ng1645 <= n4236_1; - Ng1603 <= n4241_1; - Ng1606 <= n4246; - Ng1609 <= n4251; - Ng1648 <= n4256; - Ng1651 <= n4261_1; - Ng1654 <= n4266; - Ng1466 <= n4271; - Ng1462 <= n4276; - Ng1457 <= n4281_1; - Ng1453 <= n4286; - Ng1448 <= n4291_1; - Ng1444 <= n4296; - Ng1439 <= n4301; - Ng1435 <= n4306_1; - Ng1430 <= n4311_1; - Ng1426 <= n4316; - Ng11551 <= n4321; - Ng11552 <= n4326; - Ng11553 <= n4331_1; - Ng11554 <= n4336_1; - Ng11555 <= n4341_1; - Ng11556 <= n4346; - Ng11557 <= n4351; - Ng11558 <= n4356; - Ng11559 <= n4361; - Ng11560 <= n4366; - Ng11561 <= n4371; - Ng11562 <= n4376; - Ng1789 <= n4381; - Ng1792 <= n4386; - Ng1795 <= n4391; - Ng1798 <= n4396; - Ng1801 <= n4401; - Ng1804 <= n4406; - Ng1808 <= n4411; - Ng1809 <= n4416; - Ng1807 <= n4421; - Ng1810 <= n4426; - Ng1813 <= n4431; - Ng1816 <= n4436; - Ng1819 <= n4441; - Ng1822 <= n4446_1; - Ng1825 <= n4451_1; - Ng1829 <= n4456_1; - Ng1830 <= n4461; - Ng1828 <= n4466; - Ng1693 <= n4471; - Ng1694 <= n4476; - Ng1695 <= n4481; - Ng1696 <= n4486; - Ng1697 <= n4491; - Ng1698 <= n4496; - Ng1699 <= n4501; - Ng1700 <= n4506_1; - Ng1701 <= n4511; - Ng1703 <= n4516; - Ng1704 <= n4521; - Ng1702 <= n4526; - Ng1784 <= n4531; - Ng1785 <= n4536; - Ng1783 <= n4541; - Ng1831 <= n4546; - Ng1832 <= n4550; - Ng1833 <= n4555; - Ng1834 <= n4559; - Ng1835 <= n4564; - Ng1660 <= n4568; - Ng1661 <= n4573; - Ng1662 <= n4577; - Ng1663 <= n4582; - Ng1664 <= n4586; - Ng1665 <= n4591; - Ng1666 <= n4595; - Ng1667 <= n4600; - Ng1668 <= n4604; - Ng1669 <= n4609; - Ng1670 <= n4613; - Ng1671 <= n4617; - Ng1672 <= n4621; - Ng1680 <= n4626; - Ng1686 <= n4631; - Ng1679 <= n4636; - Ng1723 <= n4640; - Ng1730 <= n4644_1; - Ng1731 <= n4648; - Ng1732 <= n4652; - Ng1733 <= n4656; - Ng1734 <= n4660; - Ng1738 <= n4664; - Ng1745 <= n4668; - Ng1746 <= n4672; - Ng1747 <= n4676; - Ng1748 <= n4680; - Ng1749 <= n4684; - Ng1753 <= n4688; - Ng1760 <= n4692; - Ng1761 <= n4696; - Ng1762 <= n4700; - Ng1763 <= n4704; - Ng1764 <= n4708; - Ng1768 <= n4712; - Ng1775 <= n4716; - Ng1776 <= n4720; - Ng1777 <= n4724; - Ng1778 <= n4728; - Ng1705 <= n4732; - Ng1934 <= n4737; - Ng1937 <= n4742; - Ng1890 <= n4747; - Ng1893 <= n4752; - Ng1903 <= n4756; - Ng1904 <= n4760; - Ng1944 <= n4765; - Ng1949 <= n4769; - Ng1950 <= n4774; - Ng1951 <= n4778; - Ng1952 <= n4783; - Ng1953 <= n4787; - Ng1954 <= n4792; - Ng1945 <= n4796; - Ng1946 <= n4801; - Ng1947 <= n4805; - Ng1948 <= n4810; - Ng1870 <= n4814; - Ng1867 <= n4819; - Ng1868 <= n4824; - Ng1869 <= n4829; - Ng11566 <= n4834; - Ng11569 <= n4838; - Ng11570 <= n4842; - Ng1858 <= n4846; - Ng1859 <= n4851; - Ng1860 <= n4856; - Ng1861 <= n4861; - Ng1865 <= n4866; - Ng1845 <= n4871_1; - Ng11571 <= n4876; - Ng11567 <= n4880; - Ng11568 <= n4884; - Ng1908 <= n4888; - Ng1915 <= n4892; - Ng1922 <= n4896_1; - Ng1923 <= n4901; - Ng1924 <= n4905_1; - Ng1928 <= n4910; - Ng1929 <= n4915; - Ng8302 <= n4919; - Ng1938 <= n4924; - Ng1939 <= n4928; - Ng1956 <= n4933; - Ng1957 <= n4938; - Ng1955 <= n4943; - Ng1959 <= n4948; - Ng1960 <= n4953; - Ng1958 <= n4958; - Ng1962 <= n4963; - Ng1963 <= n4968; - Ng1961 <= n4973; - Ng1965 <= n4978; - Ng1966 <= n4983; - Ng1964 <= n4988; - Ng1967 <= n4993; - Ng1970 <= n4998; - Ng1973 <= n5003; - Ng1976 <= n5008; - Ng1979 <= n5013; - Ng1982 <= n5018; - Ng1994 <= n5023; - Ng1997 <= n5028; - Ng2000 <= n5033; - Ng1985 <= n5038; - Ng1988 <= n5043; - Ng1991 <= n5048; - Ng1871 <= n5053; - Ng1874 <= n5058; - Ng1877 <= n5063; - Ng1886 <= n5067; - Ng1887 <= n5072; - Pg16399 <= n5077; - Ng1905 <= n5080; - Ng1909 <= n5085; - Ng1910 <= n5090; - Ng1911 <= n5095; - Ng1912 <= n5100; - Ng1913 <= n5105; - Ng1914 <= n5110; - Ng1916 <= n5115; - Ng1917 <= n5120; - Ng1918 <= n5125; - Ng1921 <= n5130; - Ng2010 <= n5135; - Ng2039 <= n5140; - Ng2020 <= n5145; - Ng2013 <= n5150; - Ng2033 <= n5155; - Ng2026 <= n5160; - Ng2040 <= n5165; - Ng2052 <= n5170; - Ng2046 <= n5175; - Ng2059 <= n5180; - Ng2066 <= n5185; - Ng2072 <= n5190; - Ng2079 <= n5195; - Ng2080 <= n5200; - Ng2078 <= n5205; - Ng2082 <= n5210; - Ng2083 <= n5215; - Ng2081 <= n5220; - Ng2085 <= n5225; - Ng2086 <= n5230; - Ng2084 <= n5235; - Ng2088 <= n5240; - Ng2089 <= n5245; - Ng2087 <= n5250; - Ng2091 <= n5255; - Ng2092 <= n5260; - Ng2090 <= n5265; - Ng2094 <= n5270; - Ng2095 <= n5275; - Ng2093 <= n5280; - Ng2097 <= n5285; - Ng2098 <= n5290; - Ng2096 <= n5295; - Ng2100 <= n5300; - Ng2101 <= n5305; - Ng2099 <= n5310; - Ng2103 <= n5315; - Ng2104 <= n5320; - Ng2102 <= n5325; - Ng2106 <= n5330; - Ng2107 <= n5335; - Ng2105 <= n5340; - Ng2109 <= n5345; - Ng2110 <= n5350; - Ng2108 <= n5355; - Ng2112 <= n5360; - Ng2113 <= n5365; - Ng2111 <= n5370; - Ng2115 <= n5375; - Ng2116 <= n5380; - Ng2114 <= n5385; - Ng2118 <= n5390; - Ng2119 <= n5395; - Ng2117 <= n5400; - Ng2206 <= n5405; - Ng2207 <= n5410; - Ng2205 <= n5415; - Ng2209 <= n5420; - Ng2210 <= n5425; - Ng2208 <= n5430; - Ng2218 <= n5435; - Ng2219 <= n5440; - Ng2217 <= n5445; - Ng2221 <= n5450; - Ng2222 <= n5455; - Ng2220 <= n5460; - Ng2224 <= n5465; - Ng2225 <= n5470; - Ng2223 <= n5475; - Ng2227 <= n5480; - Ng2228 <= n5485; - Ng2226 <= n5490; - Ng2230 <= n5495; - Ng2231 <= n5500; - Ng2229 <= n5505; - Ng2233 <= n5510; - Ng2234 <= n5515; - Ng2232 <= n5520; - Ng2236 <= n5525; - Ng2237 <= n5530; - Ng2235 <= n5535; - Ng2239 <= n5540; - Ng2240 <= n5545; - Ng2238 <= n5550; - Ng2245 <= n5555; - Ng2246 <= n5560; - Ng2244 <= n5565; - Ng2248 <= n5570; - Ng2249 <= n5575; - Ng2247 <= n5580; - Ng2251 <= n5585; - Ng2252 <= n5590; - Ng2250 <= n5595; - Ng2254 <= n5600; - Ng2255 <= n5605; - Ng2253 <= n5610; - Ng2261 <= n5615; - Ng2264 <= n5620; - Ng2267 <= n5625; - Ng2306 <= n5630; - Ng2309 <= n5635; - Ng2312 <= n5640; - Ng2270 <= n5645; - Ng2273 <= n5650; - Ng2276 <= n5655; - Ng2315 <= n5660; - Ng2318 <= n5665; - Ng2321 <= n5670; - Ng2279 <= n5675; - Ng2282 <= n5680; - Ng2285 <= n5685; - Ng2324 <= n5690; - Ng2327 <= n5695; - Ng2330 <= n5700; - Ng2288 <= n5705; - Ng2291 <= n5710; - Ng2294 <= n5715; - Ng2333 <= n5720; - Ng2336 <= n5725; - Ng2339 <= n5730; - Ng2297 <= n5735; - Ng2300 <= n5740; - Ng2303 <= n5745; - Ng2342 <= n5750; - Ng2345 <= n5755; - Ng2348 <= n5760; - Ng2160 <= n5765; - Ng2156 <= n5770; - Ng2151 <= n5775; - Ng2147 <= n5780; - Ng2142 <= n5785; - Ng2138 <= n5790; - Ng2133 <= n5795; - Ng2129 <= n5800; - Ng2124 <= n5805; - Ng2120 <= n5810; - Ng2256 <= n5815; - \[1609] <= n5819; - Ng2257 <= n5823; - Ng11578 <= n5828; - Ng11579 <= n5833; - Ng11580 <= n5838; - Ng11581 <= n5843; - Ng11582 <= n5848; - Ng11583 <= n5853; - Ng11584 <= n5858; - Ng11585 <= n5863; - Ng11586 <= n5868; - Ng11587 <= n5873; - Ng11588 <= n5878; - Ng11589 <= n5883; - Ng2483 <= n5888; - Ng2486 <= n5893; - Ng2489 <= n5898; - Ng2492 <= n5903; - Ng2495 <= n5908; - Ng2498 <= n5913; - Ng2502 <= n5918; - Ng2503 <= n5923; - Ng2501 <= n5928; - Ng2504 <= n5933; - Ng2507 <= n5938; - Ng2510 <= n5943; - Ng2513 <= n5948; - Ng2516 <= n5953; - Ng2519 <= n5958; - Ng2523 <= n5963; - Ng2524 <= n5968; - Ng2522 <= n5973; - Ng2387 <= n5978; - Ng2388 <= n5983; - Ng2389 <= n5988; - Ng2390 <= n5993; - Ng2391 <= n5998; - Ng2392 <= n6003; - Ng2393 <= n6008; - Ng2394 <= n6013; - Ng2395 <= n6018; - Ng2397 <= n6023; - Ng2398 <= n6028; - Ng2396 <= n6033; - Ng2478 <= n6038; - Ng2479 <= n6043; - Ng2477 <= n6048; - Ng2525 <= n6053; - Ng2526 <= n6057; - Ng2527 <= n6062; - Ng2528 <= n6066; - Ng2529 <= n6071; - Ng2354 <= n6075; - Ng2355 <= n6080; - Ng2356 <= n6084; - Ng2357 <= n6089; - Ng2358 <= n6093; - Ng2359 <= n6098; - Ng2360 <= n6102; - Ng2361 <= n6107; - Ng2362 <= n6111; - Ng2363 <= n6116; - Ng2364 <= n6120; - Ng2365 <= n6124; - Ng2366 <= n6128; - Ng2374 <= n6133; - Ng2380 <= n6138; - Ng2373 <= n6143; - Ng2417 <= n6147; - Ng2424 <= n6151; - Ng2425 <= n6155; - Ng2426 <= n6159; - Ng2427 <= n6163; - Ng2428 <= n6167; - Ng2432 <= n6171; - Ng2439 <= n6175; - Ng2440 <= n6179; - Ng2441 <= n6183; - Ng2442 <= n6187; - Ng2443 <= n6191; - Ng2447 <= n6195; - Ng2454 <= n6199; - Ng2455 <= n6203; - Ng2456 <= n6207; - Ng2457 <= n6211; - Ng2458 <= n6215; - Ng2462 <= n6219; - Ng2469 <= n6223; - Ng2470 <= n6227; - Ng2471 <= n6231; - Ng2472 <= n6235; - Ng2399 <= n6239; - Ng2628 <= n6244; - Ng2631 <= n6249; - Ng2584 <= n6254; - Ng2587 <= n6259; - Ng2597 <= n6263; - Ng2598 <= n6267; - Ng2638 <= n6272; - Ng2643 <= n6276; - Ng2644 <= n6281; - Ng2645 <= n6285; - Ng2646 <= n6290; - Ng2647 <= n6294; - Ng2648 <= n6299; - Ng2639 <= n6303; - Ng2640 <= n6308; - Ng2641 <= n6312; - Ng2642 <= n6317; - Ng2564 <= n6321; - Ng2561 <= n6326; - Ng2562 <= n6331; - Ng2563 <= n6336; - Ng11593 <= n6341; - Ng11596 <= n6345; - Ng11597 <= n6349; - Ng2552 <= n6353; - Ng2553 <= n6358; - Ng2554 <= n6363; - Ng2555 <= n6368; - Ng2559 <= n6373; - Ng2539 <= n6378; - Ng11598 <= n6383; - Ng11594 <= n6387; - Ng11595 <= n6391; - Ng2602 <= n6395; - Ng2609 <= n6399; - Ng2616 <= n6403; - Ng2617 <= n6408; - Ng2618 <= n6412; - Ng2622 <= n6417; - Ng2623 <= n6422; - Ng8311 <= n6426; - Ng2632 <= n6431; - Ng2633 <= n6435; - Ng2650 <= n6440; - Ng2651 <= n6445; - Ng2649 <= n6450; - Ng2653 <= n6455; - Ng2654 <= n6460; - Ng2652 <= n6465; - Ng2656 <= n6470; - Ng2657 <= n6475; - Ng2655 <= n6480; - Ng2659 <= n6485; - Ng2660 <= n6490; - Ng2658 <= n6495; - Ng2661 <= n6500; - Ng2664 <= n6505; - Ng2667 <= n6510; - Ng2670 <= n6515; - Ng2673 <= n6520; - Ng2676 <= n6525; - Ng2688 <= n6530; - Ng2691 <= n6535; - Ng2694 <= n6540; - Ng2679 <= n6545; - Ng2682 <= n6550; - Ng2685 <= n6555; - Ng2565 <= n6560; - Ng2568 <= n6565; - Ng2571 <= n6570; - Ng2580 <= n6574; - Ng2581 <= n6579; - Pg16437 <= n6584; - Ng2599 <= n6587; - Ng2603 <= n6592; - Ng2604 <= n6597; - Ng2605 <= n6602; - Ng2606 <= n6607; - Ng2607 <= n6612; - Ng2608 <= n6617; - Ng2610 <= n6622; - Ng2611 <= n6627; - Ng2612 <= n6632; - Ng2615 <= n6637; - Ng2704 <= n6642; - Ng2733 <= n6647; - Ng2714 <= n6652; - Ng2707 <= n6657; - Ng2727 <= n6662; - Ng2720 <= n6667; - Ng2734 <= n6672; - Ng2746 <= n6677; - Ng2740 <= n6682; - Ng2753 <= n6687; - Ng2760 <= n6692; - Ng2766 <= n6697; - Ng2773 <= n6702; - Ng2774 <= n6707; - Ng2772 <= n6712; - Ng2776 <= n6717; - Ng2777 <= n6722; - Ng2775 <= n6727; - Ng2779 <= n6732; - Ng2780 <= n6737; - Ng2778 <= n6742; - Ng2782 <= n6747; - Ng2783 <= n6752; - Ng2781 <= n6757; - Ng2785 <= n6762; - Ng2786 <= n6767; - Ng2784 <= n6772; - Ng2788 <= n6777; - Ng2789 <= n6782; - Ng2787 <= n6787; - Ng2791 <= n6792; - Ng2792 <= n6797; - Ng2790 <= n6802; - Ng2794 <= n6807; - Ng2795 <= n6812; - Ng2793 <= n6817; - Ng2797 <= n6822; - Ng2798 <= n6827; - Ng2796 <= n6832; - Ng2800 <= n6837; - Ng2801 <= n6842; - Ng2799 <= n6847; - Ng2803 <= n6852; - Ng2804 <= n6857; - Ng2802 <= n6862; - Ng2806 <= n6867; - Ng2807 <= n6872; - Ng2805 <= n6877; - Ng2809 <= n6882; - Ng2810 <= n6887; - Ng2808 <= n6892; - Ng2812 <= n6897; - Ng2813 <= n6902; - Ng2811 <= n6907; - Ng3054 <= n6912; - Ng3079 <= n6917; - Ng13475 <= n6922; - Ng3043 <= n6926; - Ng3044 <= n6931; - Ng3045 <= n6936; - Ng3046 <= n6941; - Ng3047 <= n6946; - Ng3048 <= n6951; - Ng3049 <= n6956; - Ng3050 <= n6961; - Ng3051 <= n6966; - Ng3052 <= n6971; - Ng3053 <= n6976; - Ng3055 <= n6981; - Ng3056 <= n6986; - Ng3057 <= n6991; - Ng3058 <= n6996; - Ng3059 <= n7001; - Ng3060 <= n7006; - Ng3061 <= n7011; - Ng3062 <= n7016; - Ng3063 <= n7021; - Ng3064 <= n7026; - Ng3065 <= n7031; - Ng3066 <= n7036; - Ng3067 <= n7041; - Ng3068 <= n7046; - Ng3069 <= n7051; - Ng3070 <= n7056; - Ng3071 <= n7061; - Ng3072 <= n7066; - Ng3073 <= n7071; - Ng3074 <= n7076; - Ng3075 <= n7081; - Ng3076 <= n7086; - Ng3077 <= n7091; - Ng3078 <= n7096; - Ng2997 <= n7101; - Ng2993 <= n7106; - Ng2998 <= n7111; - Ng3006 <= n7116; - Ng3002 <= n7121; - Ng3013 <= n7126; - Ng3010 <= n7131; - Ng3024 <= n7136; - Ng3018 <= n7141; - Ng3028 <= n7146; - Ng3036 <= n7151; - Ng3032 <= n7156; - Pg5388 <= n7160; - Ng2986 <= n7163; - Ng2987 <= n7167; - Pg8275 <= n7172; - Pg8274 <= n7176; - Pg8273 <= n7180; - Pg8272 <= n7184; - Pg8268 <= n7188; - Pg8269 <= n7192; - Pg8270 <= n7196; - Pg8271 <= n7200; - Ng3083 <= n7204; - Pg8267 <= n7209; - Ng2992 <= n7213; - Pg8266 <= n7218; - Pg8265 <= n7222; - Pg8264 <= n7226; - Pg8262 <= n7230; - Pg8263 <= n7234; - Pg8260 <= n7238; - Pg8261 <= n7242; - Pg8259 <= n7246; - Ng2990 <= n7250; - Ng2991 <= n7255; - Pg8258 <= n7260; - end -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/s38584/s38584.v b/fpga_flow/benchmarks/Verilog/MCNC/s38584/s38584.v deleted file mode 100644 index 075e52556..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/s38584/s38584.v +++ /dev/null @@ -1,7675 +0,0 @@ -// Benchmark "TOP" written by ABC on Tue Mar 5 10:05:28 2019 - -module s38584 ( clock, - Pg6753, Pg6752, Pg6751, Pg6750, Pg6749, Pg6748, Pg6747, Pg6746, Pg6745, - Pg6744, Pg135, Pg134, Pg127, Pg126, Pg125, Pg124, Pg120, Pg116, Pg115, - Pg114, Pg113, Pg100, Pg99, Pg92, Pg91, Pg90, Pg84, Pg73, Pg72, Pg64, - Pg57, Pg56, Pg54, Pg53, Pg44, Pg36, Pg35, Pg5, - Pg34972, Pg34956, Pg34927, Pg34925, Pg34923, Pg34921, Pg34919, Pg34917, - Pg34915, Pg34913, Pg34839, Pg34788, Pg34597, Pg34437, Pg34436, Pg34435, - Pg34425, Pg34383, Pg34240, Pg34239, Pg34238, Pg34237, Pg34236, Pg34235, - Pg34234, Pg34233, Pg34232, Pg34221, Pg34201, Pg33959, Pg33950, Pg33949, - Pg33948, Pg33947, Pg33946, Pg33945, Pg33935, Pg33894, Pg33874, Pg33659, - Pg33636, Pg33533, Pg33435, Pg33079, Pg32975, Pg32454, Pg32429, Pg32185, - Pg31863, Pg31862, Pg31861, Pg31860, Pg31793, Pg31665, Pg31656, Pg31521, - Pg30332, Pg30331, Pg30330, Pg30329, Pg30327, Pg29221, Pg29220, Pg29219, - Pg29218, Pg29217, Pg29216, Pg29215, Pg29214, Pg29213, Pg29212, Pg29211, - Pg29210, Pg28753, Pg28042, Pg28041, Pg28030, Pg27831, Pg26877, Pg26876, - Pg26875, Pg26801, Pg25590, Pg25589, Pg25588, Pg25587, Pg25586, Pg25585, - Pg25584, Pg25583, Pg25582, Pg25259, Pg25219, Pg25167, Pg25114, Pg24185, - Pg24184, Pg24183, Pg24182, Pg24181, Pg24180, Pg24179, Pg24178, Pg24177, - Pg24176, Pg24175, Pg24174, Pg24173, Pg24172, Pg24171, Pg24170, Pg24169, - Pg24168, Pg24167, Pg24166, Pg24165, Pg24164, Pg24163, Pg24162, Pg24161, - Pg24151, Pg23759, Pg23683, Pg23652, Pg23612, Pg23190, Pg23002, Pg21727, - Pg21698, Pg21292, Pg21270, Pg21245, Pg21176, Pg20901, Pg20899, Pg20763, - Pg20654, Pg20652, Pg20557, Pg20049, Pg19357, Pg19334, Pg18881, Pg18101, - Pg18100, Pg18099, Pg18098, Pg18097, Pg18096, Pg18095, Pg18094, Pg18092, - Pg17871, Pg17845, Pg17819, Pg17813, Pg17787, Pg17778, Pg17764, Pg17760, - Pg17743, Pg17739, Pg17722, Pg17715, Pg17711, Pg17688, Pg17685, Pg17678, - Pg17674, Pg17649, Pg17646, Pg17639, Pg17607, Pg17604, Pg17580, Pg17577, - Pg17519, Pg17423, Pg17404, Pg17400, Pg17320, Pg17316, Pg17291, Pg16955, - Pg16924, Pg16874, Pg16775, Pg16748, Pg16744, Pg16722, Pg16718, Pg16693, - Pg16686, Pg16659, Pg16656, Pg16627, Pg16624, Pg16603, Pg14828, Pg14779, - Pg14749, Pg14738, Pg14705, Pg14694, Pg14673, Pg14662, Pg14635, Pg14597, - Pg14518, Pg14451, Pg14421, Pg14217, Pg14201, Pg14189, Pg14167, Pg14147, - Pg14125, Pg14096, Pg13966, Pg13926, Pg13906, Pg13895, Pg13881, Pg13865, - Pg13272, Pg13259, Pg13099, Pg13085, Pg13068, Pg13049, Pg13039, Pg12923, - Pg12919, Pg12833, Pg12832, Pg12470, Pg12422, Pg12368, Pg12350, Pg12300, - Pg12238, Pg12184, Pg11770, Pg11678, Pg11447, Pg11418, Pg11388, Pg11349, - Pg10527, Pg10500, Pg10306, Pg10122, Pg9817, Pg9743, Pg9741, Pg9682, - Pg9680, Pg9617, Pg9615, Pg9555, Pg9553, Pg9497, Pg9251, Pg9048, Pg9019, - Pg8920, Pg8919, Pg8918, Pg8917, Pg8916, Pg8915, Pg8870, Pg8839, Pg8789, - Pg8788, Pg8787, Pg8786, Pg8785, Pg8784, Pg8783, Pg8719, Pg8475, Pg8416, - Pg8403, Pg8398, Pg8358, Pg8353, Pg8344, Pg8342, Pg8291, Pg8283, Pg8279, - Pg8277, Pg8235, Pg8215, Pg8178, Pg8132, Pg7946, Pg7916, Pg7540, Pg7260, - Pg7257, Pg7245, Pg7243 ); - input Pg6753, Pg6752, Pg6751, Pg6750, Pg6749, Pg6748, Pg6747, Pg6746, - Pg6745, Pg6744, Pg135, Pg134, Pg127, Pg126, Pg125, Pg124, Pg120, Pg116, - Pg115, Pg114, Pg113, Pg100, Pg99, Pg92, Pg91, Pg90, Pg84, Pg73, Pg72, - Pg64, Pg57, Pg56, Pg54, Pg53, Pg44, Pg36, Pg35, Pg5, clock; - output Pg34972, Pg34956, Pg34927, Pg34925, Pg34923, Pg34921, Pg34919, - Pg34917, Pg34915, Pg34913, Pg34839, Pg34788, Pg34597, Pg34437, Pg34436, - Pg34435, Pg34425, Pg34383, Pg34240, Pg34239, Pg34238, Pg34237, Pg34236, - Pg34235, Pg34234, Pg34233, Pg34232, Pg34221, Pg34201, Pg33959, Pg33950, - Pg33949, Pg33948, Pg33947, Pg33946, Pg33945, Pg33935, Pg33894, Pg33874, - Pg33659, Pg33636, Pg33533, Pg33435, Pg33079, Pg32975, Pg32454, Pg32429, - Pg32185, Pg31863, Pg31862, Pg31861, Pg31860, Pg31793, Pg31665, Pg31656, - Pg31521, Pg30332, Pg30331, Pg30330, Pg30329, Pg30327, Pg29221, Pg29220, - Pg29219, Pg29218, Pg29217, Pg29216, Pg29215, Pg29214, Pg29213, Pg29212, - Pg29211, Pg29210, Pg28753, Pg28042, Pg28041, Pg28030, Pg27831, Pg26877, - Pg26876, Pg26875, Pg26801, Pg25590, Pg25589, Pg25588, Pg25587, Pg25586, - Pg25585, Pg25584, Pg25583, Pg25582, Pg25259, Pg25219, Pg25167, Pg25114, - Pg24185, Pg24184, Pg24183, Pg24182, Pg24181, Pg24180, Pg24179, Pg24178, - Pg24177, Pg24176, Pg24175, Pg24174, Pg24173, Pg24172, Pg24171, Pg24170, - Pg24169, Pg24168, Pg24167, Pg24166, Pg24165, Pg24164, Pg24163, Pg24162, - Pg24161, Pg24151, Pg23759, Pg23683, Pg23652, Pg23612, Pg23190, Pg23002, - Pg21727, Pg21698, Pg21292, Pg21270, Pg21245, Pg21176, Pg20901, Pg20899, - Pg20763, Pg20654, Pg20652, Pg20557, Pg20049, Pg19357, Pg19334, Pg18881, - Pg18101, Pg18100, Pg18099, Pg18098, Pg18097, Pg18096, Pg18095, Pg18094, - Pg18092, Pg17871, Pg17845, Pg17819, Pg17813, Pg17787, Pg17778, Pg17764, - Pg17760, Pg17743, Pg17739, Pg17722, Pg17715, Pg17711, Pg17688, Pg17685, - Pg17678, Pg17674, Pg17649, Pg17646, Pg17639, Pg17607, Pg17604, Pg17580, - Pg17577, Pg17519, Pg17423, Pg17404, Pg17400, Pg17320, Pg17316, Pg17291, - Pg16955, Pg16924, Pg16874, Pg16775, Pg16748, Pg16744, Pg16722, Pg16718, - Pg16693, Pg16686, Pg16659, Pg16656, Pg16627, Pg16624, Pg16603, Pg14828, - Pg14779, Pg14749, Pg14738, Pg14705, Pg14694, Pg14673, Pg14662, Pg14635, - Pg14597, Pg14518, Pg14451, Pg14421, Pg14217, Pg14201, Pg14189, Pg14167, - Pg14147, Pg14125, Pg14096, Pg13966, Pg13926, Pg13906, Pg13895, Pg13881, - Pg13865, Pg13272, Pg13259, Pg13099, Pg13085, Pg13068, Pg13049, Pg13039, - Pg12923, Pg12919, Pg12833, Pg12832, Pg12470, Pg12422, Pg12368, Pg12350, - Pg12300, Pg12238, Pg12184, Pg11770, Pg11678, Pg11447, Pg11418, Pg11388, - Pg11349, Pg10527, Pg10500, Pg10306, Pg10122, Pg9817, Pg9743, Pg9741, - Pg9682, Pg9680, Pg9617, Pg9615, Pg9555, Pg9553, Pg9497, Pg9251, Pg9048, - Pg9019, Pg8920, Pg8919, Pg8918, Pg8917, Pg8916, Pg8915, Pg8870, Pg8839, - Pg8789, Pg8788, Pg8787, Pg8786, Pg8785, Pg8784, Pg8783, Pg8719, Pg8475, - Pg8416, Pg8403, Pg8398, Pg8358, Pg8353, Pg8344, Pg8342, Pg8291, Pg8283, - Pg8279, Pg8277, Pg8235, Pg8215, Pg8178, Pg8132, Pg7946, Pg7916, Pg7540, - Pg7260, Pg7257, Pg7245, Pg7243; - reg Ng5057, Ng2771, Ng1882, Ng2299, Ng4040, Ng2547, Ng559, Ng3243, Ng452, - Ng3542, Ng5232, Ng5813, Ng2907, Ng1744, Ng5909, Ng1802, Ng3554, Ng6219, - Ng807, Ng6031, Ng847, Ng976, Ng4172, Ng4372, Ng3512, Ng749, Ng3490, - Pg12350, Ng4235, Ng1600, Ng1714, Pg14451, Ng3155, Ng2236, Ng4555, - Ng3698, Ng1736, Ng1968, Ng4621, Ng5607, Ng2657, Pg12300, Ng490, Ng311, - Ng772, Ng5587, Ng6177, Ng6377, Ng3167, Ng5615, Ng4567, Ng3457, Ng6287, - Pg7946, Ng2563, Ng4776, Ng4593, Ng6199, Ng2295, Ng1384, Ng1339, Ng5180, - Ng2844, Ng1024, Ng5591, Ng3598, Ng4264, Ng767, Ng5853, Pg13865, Ng2089, - Ng4933, Ng4521, Ng5507, Pg16656, Ng6291, Ng294, Ng5559, Pg9617, Pg9741, - Ng3813, Ng562, Ng608, Ng1205, Ng3909, Ng6259, Ng5905, Ng921, Ng2955, - Ng203, Ng1099, Ng4878, Ng5204, Pg17604, Ng3606, Ng1926, Ng6215, Ng3586, - Ng291, Ng4674, Ng3570, Pg9048, Pg17607, Ng1862, Ng676, Ng843, Ng4332, - Ng4153, Pg17711, Ng6336, Ng622, Ng3506, Ng4558, Pg17685, Ng3111, - \[4430] , Ng26936, Ng939, Ng278, Ng4492, Ng4864, Ng1036, \[4427] , - Ng1178, Ng3239, Ng718, Ng6195, Ng1135, Ng6395, \[4415] , Ng554, Ng496, - Ng3853, Ng5134, Pg17404, Pg8344, Ng2485, Ng925, Ng48, Ng5555, Pg14096, - Ng1798, Ng4076, Ng2941, Ng3905, Ng763, Ng6255, Ng4375, Ng4871, Ng4722, - Ng590, Pg13099, Ng1632, Pg12238, Ng3100, Ng1495, Ng1437, Ng6154, - Ng1579, Ng5567, Ng1752, Ng1917, Ng744, Ng4737, \[4661] , Ng6267, - Pg16659, Ng1442, Ng5965, Ng4477, Pg10500, Ng4643, Ng5264, Pg14779, - Ng2610, Ng5160, Ng5933, Ng1454, Ng753, Ng1296, Ng3151, Ng2980, Ng6727, - Ng3530, Ng4104, Ng1532, Pg9251, Ng2177, Ng52, Ng4754, Ng1189, Ng2287, - Ng4273, Ng1389, Ng1706, Ng5835, Ng1171, Ng4269, Ng2399, Ng4983, Ng5611, - Pg16627, Ng4572, Ng3143, Ng2898, Ng3343, Ng3235, Ng4543, Ng3566, - Ng4534, Ng4961, Ng4927, Ng2259, Ng2819, Pg7257, Ng5802, Ng2852, Ng417, - Ng681, Ng437, Ng351, Ng5901, Ng2886, Ng3494, Ng5511, Ng3518, Ng1604, - Ng5092, Ng4831, Ng4382, Ng6386, Ng479, Ng3965, Ng4749, Ng2008, Ng736, - Ng3933, Ng222, Ng3050, Ng1052, Pg17580, Ng2122, Ng2465, Ng5889, Ng4495, - Pg8719, Ng4653, Ng3179, Ng1728, Ng2433, Ng3835, Ng6187, Ng4917, Ng1070, - Ng822, Pg17715, Ng914, Ng5339, Ng4164, Ng969, Ng2807, Ng4054, Ng6191, - Ng5077, Ng5523, Ng3680, Ng6637, Ng174, Ng1682, Ng355, Ng1087, Ng1105, - Ng2342, Ng6307, Ng3802, Ng6159, Ng2255, Ng2815, Ng911, Ng43, Pg16775, - Ng1748, Ng5551, Ng3558, Ng5499, Ng2960, Ng3901, Ng4888, Ng6251, - Pg17649, Ng1373, Pg8215, Ng157, Ng2783, Ng4281, Ng3574, Ng2112, Ng1283, - Ng433, Ng4297, Pg14738, Pg13272, Ng758, Ng4639, Ng6537, Ng5543, Pg8475, - Ng5961, Ng6243, Ng632, Pg12919, Ng3889, Ng3476, Ng1664, Ng1246, Ng6629, - Ng246, Ng4049, Pg7260, Ng2932, Ng4575, Ng4098, Ng4498, Ng528, Ng16, - Ng3139, \[4432] , Ng4584, Ng142, Pg17639, Ng5831, Ng239, Ng1216, - Ng2848, Ng5022, Pg16955, Ng1030, Pg13881, Ng3231, Pg9817, Ng1430, - Ng4452, Ng2241, Ng1564, Pg9680, Ng6148, Ng6649, Ng110, Pg14147, Ng225, - Ng4486, Ng4504, Ng5873, Ng5037, Ng2319, Ng5495, Pg11770, Ng5208, - Ng5579, Ng5869, Ng1589, Ng5752, Ng6279, Ng5917, Ng2975, Ng6167, - Pg13966, Ng2599, Ng1448, Pg14125, Ng2370, Ng5164, Ng1333, Ng153, - Ng6549, Ng4087, Ng4801, Ng2984, Ng3961, Ng962, Ng101, Pg8918, Ng6625, - Ng51, Ng1018, Pg17320, Ng4045, Ng1467, Ng2461, Ng2756, Ng5990, Ng1256, - Ng5029, Ng6519, Ng1816, Ng4369, Ng4578, Ng4459, Ng3831, Ng2514, Ng3288, - Ng2403, Ng2145, Ng1700, Ng513, Ng2841, Ng5297, Ng2763, Ng4793, Ng952, - Ng1263, Ng1950, Ng5138, Ng2307, Ng5109, Pg8398, Ng4664, Ng2223, Ng5808, - Ng6645, Ng2016, Ng3873, Pg13926, Ng2315, Ng2811, Ng5957, Ng2047, - Ng3869, Pg17760, Ng5575, Ng46, Ng3752, Ng3917, Pg8783, Ng1585, Ng4388, - Ng6275, Ng6311, Pg8916, Ng1041, Ng2595, Ng2537, \[4426] , Ng4430, - Ng4564, Ng4826, Ng6239, Ng232, Ng5268, Ng6545, Ng2417, Ng1772, Ng5052, - Pg9615, Ng1890, Ng2629, Ng572, Ng2130, Ng4108, Ng4308, Ng475, Ng990, - Ng45, Pg12184, Ng3990, Ng5881, Ng1992, Ng3171, Ng812, Ng832, Ng5897, - Ng4571, Pg13895, Ng4455, Ng2902, Ng333, Ng168, Ng2823, Ng3684, Ng3639, - Pg14597, Ng3338, Ng5406, Ng269, Ng401, Ng6040, Ng441, Pg9553, Ng3808, - Ng10384, Ng3957, Ng4093, Ng1760, Pg12422, Ng160, Ng2279, Ng3498, Ng586, - Pg14201, Ng2619, Ng1183, Ng1608, Pg8785, Pg17577, Ng1779, Ng2652, - Ng2193, Ng2393, Ng661, Ng4950, Ng5535, Ng2834, Ng1361, Ng6235, Ng1146, - Ng2625, Ng150, Ng1696, Ng6555, Pg14189, Ng3881, Ng6621, Ng3470, Ng3897, - Ng518, Ng538, Ng2606, Ng1472, Ng542, Ng5188, Ng5689, Pg13259, Ng405, - Ng5216, Ng6494, Ng4669, Ng996, Ng4531, Ng2860, Ng4743, Ng6593, Pg8291, - Ng4411, Ng1413, Ng26960, Pg13039, Ng6641, Ng1936, Ng55, Ng504, Ng2587, - Ng4480, Ng2311, Ng3602, Ng5571, Ng3578, Pg9555, Ng5827, Ng3582, Ng6271, - Ng4688, Ng2380, Ng5196, Ng3227, Ng2020, Pg14518, Pg17316, Ng6541, - Ng3203, Ng1668, Ng4760, Ng262, Ng1840, Ng5467, Ng460, Ng6209, \[4436] , - Pg14662, Ng655, Ng3502, Ng2204, Ng5256, Ng4608, Ng794, Pg13906, Ng4423, - Ng3689, Ng5685, Ng703, Ng862, Ng3247, Ng2040, Ng4146, Ng4633, Pg7916, - Ng4732, Pg9497, Ng5817, Ng2351, Ng2648, Ng6736, Ng4944, Ng4072, Pg7540, - Ng4443, Ng3466, Ng4116, Ng5041, Ng4434, Ng3827, Ng6500, Pg17813, - Ng3133, Ng3333, Ng979, Ng4681, Ng298, Ng2667, Pg8789, Ng1894, Ng2988, - Ng3538, Ng301, Ng341, Ng827, Pg17291, Ng2555, Ng5011, Ng199, Ng6523, - Ng1526, Ng4601, Ng854, Ng1484, Ng4922, Ng5080, Ng5863, Ng4581, Ng2518, - Ng2567, Ng568, Ng3263, Ng6613, Ng6044, Ng6444, Ng2965, Ng5857, Ng1616, - Ng890, Pg17646, Ng3562, Pg10122, Ng1404, Ng3817, Ng93, Ng4501, Ng287, - Ng2724, Ng4704, Ng22, Ng2878, Ng5220, Ng617, Pg12368, Ng316, Ng1277, - Ng6513, Ng336, Ng2882, Ng933, Ng1906, Ng305, Ng8, Ng2799, Pg14167, - Pg17787, Ng4912, Ng4157, Ng2541, Ng2153, Ng550, Ng255, Ng1945, Ng5240, - Ng1478, Ng3863, Ng1959, Ng3480, Ng6653, Pg17764, Ng2864, Ng4894, - Pg17678, Ng3857, Pg16693, Ng499, Ng1002, Ng776, Ng1236, Ng4646, Ng2476, - Ng1657, Ng2375, Ng63, Pg17739, Ng358, Ng896, Ng283, Ng3161, Ng2384, - Pg14828, Ng4616, Ng4561, Ng2024, Ng3451, Ng2795, Ng613, Ng4527, Ng1844, - Ng5937, Ng4546, Ng2523, Pg11349, Ng2643, Ng1489, Pg8358, Ng2551, - Ng5156, \[4421] , Pg8279, Pg8839, Ng1955, Ng6049, Ng2273, Pg14749, - Ng4771, Ng6098, Ng3147, Ng3347, Ng2269, Ng191, Ng2712, Ng626, Ng2729, - Ng5357, Ng4991, Pg17819, Ng4709, Ng2927, Ng4340, Ng5929, Ng4907, - Pg16874, Ng4035, Ng2946, Ng918, Ng4082, Pg9743, Ng2036, Ng577, Ng1620, - Ng2831, Ng667, Ng930, Ng3937, Ng817, Ng1249, Ng837, Pg16924, Ng599, - Ng5475, Ng739, Ng5949, Ng6682, Ng904, Ng2873, Ng1854, Ng5084, Ng5603, - Pg8870, Ng2495, Ng2437, Ng2102, Ng2208, Ng2579, Ng4064, Ng4899, Ng2719, - Ng4785, Ng5583, Ng781, Ng6173, Pg17743, Ng2917, Ng686, Ng1252, Ng671, - Ng2265, Ng6283, Pg14705, Pg17519, Pg8784, Ng5527, Ng4489, Ng1974, - Ng1270, Ng4966, Ng6227, Ng3929, Ng5503, Ng4242, Ng5925, Ng1124, Ng4955, - Ng5224, Ng2012, Ng6203, Ng5120, Pg17674, Ng2389, Ng4438, Ng2429, - Ng2787, Ng1287, Ng2675, \[4507] , Ng4836, Ng1199, Pg19357, Ng5547, - Ng2138, Pg16744, Ng2338, Pg8919, Ng6247, Ng2791, Ng3949, Ng1291, - Ng5945, Ng5244, Ng2759, Ng6741, Ng785, Ng1259, Ng3484, Ng209, Ng6609, - Ng5517, Ng2449, Ng2575, Ng65, Ng2715, Ng936, Ng2098, Ng4462, Ng604, - Ng6589, Ng1886, Pg17845, Pg17871, Ng429, Ng1870, Ng4249, Ng1825, - Ng1008, Ng4392, Ng3546, Ng5236, Ng1768, Ng4854, Ng3925, Ng6509, Ng732, - Ng2504, Ng1322, Ng4520, Pg8917, Ng2185, Ng37, Ng4031, Ng2070, \[4658] , - Ng4176, Pg11418, Ng4405, Ng872, Ng6181, Ng6381, Ng4765, Ng5563, Ng1395, - Ng1913, Ng2331, Ng6263, Ng50, Ng3945, Ng347, Ng4473, Ng1266, Ng5489, - Ng714, Ng2748, Ng5471, Ng4540, Ng6723, Ng6605, Ng2445, Ng2173, Pg9019, - Ng2491, Ng4849, Ng2169, Ng2283, Ng6585, \[4428] , Ng2407, Ng2868, - Ng2767, Ng1783, Pg16718, Ng1312, Ng5212, Ng4245, Ng645, Ng4291, - \[4435] , Ng182, Ng1129, Ng2227, Pg8788, Ng2246, Ng1830, Ng3590, Ng392, - Ng1592, Ng6505, Ng1221, Ng5921, \[4431] , Ng146, Ng218, Ng1932, Ng1624, - Ng5062, Ng5462, Ng2689, Ng6573, Ng1677, Ng2028, Ng2671, Pg10527, - Pg7243, Ng1848, \[4434] , Ng5485, Ng2741, Pg11678, Ng2638, Ng4122, - Ng4322, Ng5941, Ng2108, Pg13068, Ng25, Ng1644, Ng595, Ng2217, Ng1319, - Ng2066, Ng1152, Ng5252, Ng2165, Ng2571, Ng5176, Pg14673, Ng1211, - Ng2827, Pg14217, Ng4859, Ng424, Ng1274, Pg17423, Ng85, Ng2803, Ng1821, - Ng2509, Ng5073, Ng1280, \[4651] , Pg13085, Ng6633, Ng5124, Pg17400, - Ng6303, Ng5069, Ng2994, Ng650, Ng1636, Ng3921, Ng2093, Ng6732, Ng1306, - Ng1061, Ng3462, Ng2181, Ng956, Ng1756, Ng5849, Ng4112, Ng2685, Ng2197, - Ng2421, Ng1046, Ng482, Ng4401, Ng1514, Ng329, Ng6565, Ng2950, Ng1345, - Ng6533, Pg14421, Ng4727, Pg12470, Ng1536, Ng3941, Ng370, Ng5694, - Ng1858, Ng446, Ng3219, Ng1811, Ng6601, Ng2441, Ng1874, Ng4349, Ng6581, - Ng6597, Ng3610, Ng2890, Ng1978, Ng1612, Ng112, Ng2856, Ng1982, Pg17722, - Ng5228, Ng4119, Ng6390, Ng1542, Ng4258, Ng4818, Ng5033, Ng4717, Ng1554, - Ng3849, Pg17778, Ng3199, Ng5845, Ng4975, Ng790, Ng5913, Ng1902, Ng6163, - Ng4125, Ng4821, Ng4939, Pg19334, Ng3207, Ng4483, Ng3259, Ng5142, - Ng5248, Ng2126, Ng3694, Ng5481, Ng1964, Ng5097, Ng3215, Pg16748, Ng111, - Ng4427, Ng2779, Pg8786, Pg7245, Ng1720, Ng1367, Ng5112, Ng4145, Ng2161, - Ng376, Ng2361, Pg11447, Ng582, Ng2051, Ng1193, Ng2327, Ng907, Ng947, - Ng1834, Ng3594, Ng2999, Ng2303, Pg17688, Ng699, Ng723, Ng5703, Ng546, - Ng2472, Ng5953, Pg8277, Ng1740, Ng3550, Ng3845, Ng2116, Pg14635, - Ng3195, Ng3913, Pg10306, Ng1687, Ng2681, Ng2533, Ng324, Ng2697, Ng4417, - Ng6561, Ng1141, Pg12923, Ng2413, Ng1710, Ng6527, Ng3255, Ng1691, - Ng2936, Ng5644, Ng5152, Ng5352, Pg8915, Ng2775, Ng2922, Ng1111, Ng5893, - Pg16603, Ng6617, Ng2060, Ng4512, Ng5599, Ng3401, Ng4366, Pg16722, - \[4433] , Ng3129, Ng3329, Ng5170, Ng26959, Ng5821, Ng6299, Pg8416, - Ng2079, Ng4698, Ng3703, Ng1559, Ng943, Ng411, Pg9682, Ng3953, Ng2704, - Ng6035, Ng1300, Ng4057, Ng5200, Ng4843, Ng5046, Ng2250, Ng26885, - Ng4549, Ng2453, Ng5841, Pg14694, Ng2912, Ng2357, Pg8920, Ng164, Ng4253, - Ng5016, Ng3119, Ng1351, Ng1648, Ng6972, Ng5115, Ng3352, Ng6657, Ng4552, - Ng3893, Ng3211, Pg13049, Pg16624, Ng5595, Ng3614, Ng2894, Ng3125, - Pg16686, Ng3821, Ng4141, Ng6974, Ng5272, Ng2735, Ng728, Ng6295, Ng2661, - Ng1988, Ng5128, Ng1548, Ng3106, Ng4659, Ng4358, Ng1792, Ng2084, Ng3187, - Ng4311, Ng2583, Ng3003, Ng1094, Ng3841, Ng4284, Ng3191, Ng4239, Ng4180, - Ng691, Ng534, Ng385, Ng2004, Ng2527, Ng5456, Ng4420, Ng5148, Ng4507, - Ng5348, Ng3223, Ng2970, Ng5698, Ng5260, Ng1521, Ng3522, Ng3115, Ng3251, - Pg12832, Ng4628, Ng1996, Pg8342, Ng4515, Pg8787, Ng4300, Ng1724, - Ng1379, Pg11388, Ng1878, Ng5619, Ng71, \[4437] ; - wire n4124_1, n4133, n4135, n4136, n4151_1, n4162, n4205, n4206_1, n4207, - n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216_1, n4217, - n4218, n4219, n4220, n4221, n4223, n4225, n4227, n4229, n4231, n4233, - n4235, n4237, n4239, n4241, n4243, n4245, n4247, n4249_1, n4251, n4252, - n4254_1, n4256, n4258, n4260, n4262, n4265, n4267, n4269, n4271, n4273, - n4275, n4277, n4279, n4281, n4283, n4285, n4287, n4289, n4291, n4293, - n4295, n4297, n4299, n4301, n4303, n4305, n4307, n4309, n4311, n4313, - n4315, n4317, n4319, n4321, n4323, n4325, n4327, n4329, n4331, n4333, - n4335, n4337, n4339, n4341, n4343, n4345, n4347, n4349, n4351, n4353, - n4355, n4357, n4359, n4361, n4363, n4365, n4367, n4369_1, n4371, n4373, - n4375, n4377, n4379, n4382, n4384, n4385, n4388, n4390, n4392, n4394, - n4396, n4398, n4400, n4402, n4404, n4406, n4408, n4410, n4412, n4414, - n4416, n4418, n4420, n4423, n4425, n4427, n4429, n4431, n4433, n4435, - n4437_1, n4439, n4441, n4443, n4445, n4448, n4450, n4452_1, n4454, - n4456_1, n4458, n4460_1, n4462, n4464, n4466, n4468, n4470_1, n4472, - n4474, n4475_1, n4477, n4479, n4481, n4483, n4485_1, n4487, n4489_1, - n4491, n4493, n4495_1, n4497, n4499_1, n4501, n4503, n4505, n4507, - n4509, n4512, n4514_1, n4516, n4518, n4520, n4521, n4522, n4524_1, - n4526, n4528, n4530, n4532, n4534_1, n4536, n4538, n4541, n4543, n4545, - n4547, n4549_1, n4551, n4553, n4555, n4557, n4558, n4560, n4562, n4564, - n4567, n4569, n4571, n4573, n4575, n4577, n4579, n4581, n4583, n4585, - n4587, n4589, n4591, n4593, n4595, n4597, n4599, n4601, n4603, n4605, - n4607_1, n4609, n4611, n4613, n4615, n4617_1, n4619, n4621, n4623, - n4625, n4627_1, n4629, n4631_1, n4633, n4635, n4637, n4639, n4641, - n4643, n4645, n4647, n4649, n4651, n4653, n4655, n4657, n4659, n4661, - n4663, n4665, n4667, n4669, n4671, n4673, n4675, n4677, n4679, n4681, - n4683, n4685, n4687_1, n4689, n4692, n4695, n4697, n4699, n4701, n4703, - n4705, n4707, n4709, n4711, n4713, n4715, n4717, n4719, n4722, n4724, - n4726, n4728, n4730, n4732, n4734, n4736, n4738, n4740, n4742, n4744, - n4746_1, n4748, n4750, n4752, n4754, n4756_1, n4758, n4760, n4762, - n4764, n4766_1, n4768, n4770, n4772, n4774, n4776, n4778, n4780, - n4782_1, n4784, n4786, n4788, n4790, n4792, n4794, n4796, n4798, n4800, - n4802_1, n4804, n4806, n4808, n4810, n4812_1, n4814, n4816, n4818, - n4820, n4822_1, n4824, n4826, n4828, n4830, n4832, n4834, n4836, n4838, - n4840, n4842, n4844, n4846, n4848, n4850, n4852, n4854, n4856, n4858, - n4860, n4862, n4864, n4866, n4868, n4870, n4872, n4874, n4876, n4878, - n4880, n4882_1, n4884, n4886, n4887, n4889, n4891, n4893, n4895, n4898, - n4900, n4902, n4904_1, n4906, n4908, n4909, n4911, n4913, n4915, n4917, - n4919, n4921, n4923, n4925, n4927, n4929, n4931, n4933, n4935, n4937, - n4939_1, n4941, n4943, n4945, n4947, n4949, n4951, n4953, n4955, n4958, - n4960, n4962, n4964, n4966, n4968, n4970, n4972, n4974, n4976, n4978_1, - n4980, n4982, n4984, n4986, n4988, n4990, n4992_1, n4994, n4996, n4998, - n5000, n5002_1, n5004, n5006, n5008, n5010, n5012, n5014, n5016_1, - n5018, n5020, n5022, n5025, n5027, n5029, n5031, n5034, n5036_1, n5038, - n5040, n5042, n5044, n5046, n5048, n5049, n5050, n5052, n5054, n5057, - n5059, n5061, n5063, n5065, n5067, n5069_1, n5072, n5074, n5076, n5078, - n5080, n5082, n5084, n5086, n5088, n5090, n5091, n5093, n5095, n5097, - n5099, n5102, n5104, n5106, n5108, n5110, n5112, n5114, n5116_1, n5118, - n5120, n5122, n5124, n5126_1, n5128, n5131_1, n5132, n5134, n5136, - n5139, n5141_1, n5143, n5145, n5147, n5149, n5151, n5153, n5155, n5157, - n5159, n5161, n5163, n5165, n5167, n5169, n5170, n5172, n5174, n5176, - n5178, n5180, n5182, n5184, n5186, n5188, n5190, n5192, n5194, n5196, - n5198, n5200, n5202, n5204, n5206, n5208, n5210, n5212, n5214, n5216, - n5218, n5220, n5222, n5224, n5226, n5228, n5230, n5232, n5234, n5236, - n5238, n5240, n5242, n5244, n5246, n5248, n5250, n5252, n5254, n5256, - n5258, n5260, n5262, n5264, n5266, n5268, n5270, n5272, n5274, n5276, - n5278, n5280, n5283, n5285, n5287, n5289, n5291, n5293, n5296, n5298_1, - n5300, n5302, n5304, n5306, n5308, n5310, n5312, n5314, n5316, n5318_1, - n5320, n5322_1, n5324, n5326, n5328, n5330, n5332, n5334, n5336, n5338, - n5340, n5342, n5344, n5346, n5348, n5350, n5352, n5354, n5356, n5358, - n5360, n5362, n5365, n5367, n5370, n5372, n5374, n5376, n5378, n5380, - n5382, n5384, n5386, n5388, n5390, n5392, n5394, n5396, n5398, n5400, - n5402, n5404, n5406, n5408, n5410, n5412, n5414, n5416_1, n5418, n5420, - n5422, n5424, n5425, n5427, n5429, n5431, n5433, n5435, n5437, n5439, - n5441, n5443, n5445, n5447, n5449, n5451, n5453, n5455, n5457, n5459, - n5461_1, n5463, n5465, n5467, n5469, n5471, n5473, n5475, n5477, n5479, - n5481, n5483, n5485, n5487, n5489, n5491, n5493, n5495, n5497, n5499, - n5501, n5503, n5505, n5507, n5509, n5511, n5513, n5515, n5517, n5519, - n5521, n5523, n5525, n5527, n5529, n5531, n5533, n5535, n5537, n5539, - n5541, n5543, n5545, n5547, n5549, n5551, n5553, n5555, n5557, n5559, - n5560, n5562, n5564, n5566, n5568, n5570, n5572, n5574, n5576, n5578, - n5580, n5582, n5584, n5586, n5588, n5590, n5592, n5594, n5596, n5598_1, - n5600, n5602, n5604, n5606, n5608, n5610, n5612, n5614, n5616, n5618, - n5620, n5622, n5624, n5626, n5628_1, n5630, n5632, n5634, n5636, - n5638_1, n5640, n5642, n5644, n5646, n5648, n5650, n5652, n5654, n5656, - n5658, n5660, n5662_1, n5664, n5666, n5668, n5669, n5671_1, n5673, - n5675, n5677, n5679, n5681, n5683, n5685, n5687, n5689, n5691, n5693, - n5695_1, n5697, n5699, n5701, n5703, n5705, n5707, n5709, n5711, n5713, - n5715, n5717, n5719, n5721, n5723, n5725, n5727, n5729, n5730, n5731, - n5733, n5735, n5737, n5739, n5741, n5743, n5745, n5747, n5749, n5751, - n5753_1, n5755, n5757, n5759, n5761, n5763_1, n5765, n5767, n5769, - n5771, n5773, n5775, n5777, n5779, n5781, n5783, n5785, n5787, n5789, - n5791_1, n5793, n5795, n5797, n5799, n5801_1, n5803, n5805, n5807, - n5809, n5811_1, n5813, n5815, n5817, n5819, n5821, n5823, n5825, n5827, - n5829, n5831, n5833, n5835, n5837, n5839, n5841, n5843, n5845, n5847, - n5849, n5851, n5853, n5855, n5857, n5859_1, n5861, n5863, n5865, n5866, - n5867, n5868, n5869_1, n5871, n5872, n5873, n5874_1, n5875, n5876, - n5877, n5878, n5880, n5881, n5882, n5883, n5884_1, n5885, n5886, n5887, - n5888, n5889, n5892, n5894, n5895, n5897, n5898_1, n5899, n5901, n5902, - n5903, n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5914, - n5915, n5916, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925, - n5926, n5927, n5929, n5930, n5931, n5933, n5934, n5935, n5936, n5938, - n5939, n5940, n5941, n5942, n5944, n5945, n5947, n5948, n5949, n5950, - n5951, n5952, n5953, n5954, n5956_1, n5957, n5958, n5959, n5960, n5961, - n5962, n5963, n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, - n5972, n5973, n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, - n5982, n5983, n5984, n5985, n5988, n5989, n5990_1, n5991, n5992, n5993, - n5994, n5995, n5996, n5997, n5998_1, n5999, n6000, n6001, n6002, n6003, - n6004, n6005, n6006, n6007, n6008_1, n6009, n6010, n6011, n6012_1, - n6013, n6014, n6015, n6016, n6017_1, n6018, n6019, n6020, n6021, n6022, - n6023, n6024, n6025, n6026, n6027_1, n6028, n6029, n6030, n6031, n6032, - n6033, n6034, n6035, n6036, n6037, n6038, n6039, n6040, n6041, n6042_1, - n6043, n6044, n6045, n6046, n6047, n6048, n6049, n6050, n6051, n6052, - n6053, n6054, n6055, n6056_1, n6057, n6058, n6059, n6060, n6061_1, - n6062, n6063, n6064, n6065, n6066, n6067, n6068, n6069, n6070, n6071, - n6072, n6073, n6074, n6075, n6076, n6077, n6078, n6079, n6080, n6081_1, - n6082, n6083, n6084, n6085, n6086, n6087, n6088, n6089, n6090, n6091_1, - n6092, n6093, n6094, n6095, n6096_1, n6097, n6098, n6099, n6100, n6101, - n6102, n6103, n6104_1, n6105, n6106, n6107, n6108, n6109, n6110, n6111, - n6112, n6113, n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, - n6122, n6123, n6124, n6125, n6126, n6127_1, n6128, n6129, n6130, n6131, - n6132, n6133, n6134, n6135, n6136, n6137_1, n6138, n6139, n6140, n6141, - n6142_1, n6143, n6144, n6145, n6146, n6147_1, n6148, n6149, n6150, - n6151, n6152_1, n6153, n6154, n6155, n6156_1, n6157, n6158, n6159, - n6160_1, n6161, n6162, n6163, n6164, n6165_1, n6166, n6167, n6168, - n6169_1, n6170, n6171, n6172, n6173, n6174, n6175, n6176, n6177, n6178, - n6179_1, n6180, n6181, n6182, n6183_1, n6184, n6185, n6186, n6187, - n6188, n6189, n6190, n6191, n6192_1, n6193, n6194, n6195, n6196_1, - n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205, n6206_1, - n6207, n6208, n6209, n6210, n6211_1, n6212, n6213, n6214, n6215, - n6216_1, n6217, n6218, n6219, n6220, n6221_1, n6222, n6223, n6224, - n6225, n6226_1, n6227, n6228, n6229, n6230_1, n6231, n6232, n6233, - n6234, n6235_1, n6236, n6237, n6238, n6239, n6240_1, n6241, n6242, - n6243, n6244, n6245_1, n6246, n6247, n6248, n6249, n6250_1, n6251, - n6252, n6253, n6254, n6255_1, n6256, n6257, n6258, n6259, n6260_1, - n6261, n6262, n6263, n6264, n6265_1, n6266, n6267, n6268, n6269, - n6270_1, n6271, n6272, n6273, n6274, n6275_1, n6276, n6277, n6278, - n6279_1, n6280, n6281, n6282, n6283, n6284_1, n6285, n6286, n6287, - n6288, n6289_1, n6290, n6291, n6292, n6293_1, n6294, n6295, n6296, - n6297_1, n6298, n6299, n6300, n6301, n6302_1, n6303, n6304, n6305, - n6306, n6307, n6308, n6309, n6310_1, n6311, n6312, n6313, n6314, - n6315_1, n6316, n6317, n6318, n6319, n6320_1, n6321, n6322, n6323, - n6324, n6325, n6326, n6327, n6328, n6329, n6330_1, n6331, n6332, n6333, - n6334, n6335_1, n6336, n6337, n6338, n6339, n6340_1, n6341, n6342, - n6343, n6344, n6345, n6346, n6347, n6348, n6349_1, n6350, n6351, n6352, - n6353, n6354_1, n6355, n6356, n6357, n6358, n6359_1, n6360, n6361, - n6362, n6363, n6364, n6365, n6366, n6367, n6368, n6369_1, n6370, n6371, - n6372, n6373_1, n6374, n6375, n6376_1, n6377, n6378, n6379, n6380_1, - n6381, n6382, n6383, n6384, n6385_1, n6386, n6387, n6388, n6389, - n6390_1, n6391, n6392, n6393, n6394, n6395_1, n6396, n6397, n6398, - n6399_1, n6400, n6401, n6402, n6403_1, n6404, n6405, n6406, n6407, - n6408, n6409, n6410, n6411, n6412, n6413_1, n6414, n6415, n6416, - n6417_1, n6418, n6419, n6420, n6421, n6422_1, n6423, n6424, n6425, - n6426, n6427_1, n6428, n6429, n6430, n6431, n6432_1, n6433, n6434, - n6435, n6436, n6437_1, n6438, n6439, n6440, n6441, n6442_1, n6443, - n6444, n6445, n6446, n6447_1, n6448, n6449, n6450, n6451, n6452_1, - n6453, n6454, n6455, n6456, n6457_1, n6458, n6459, n6460, n6461, - n6462_1, n6463, n6464, n6465, n6466, n6467_1, n6468, n6469, n6470, - n6471, n6472_1, n6473, n6474, n6475, n6476, n6477_1, n6478, n6479, - n6480, n6481, n6482_1, n6483, n6484, n6485, n6486, n6487_1, n6488, - n6489, n6490, n6491, n6492_1, n6493, n6494, n6495, n6496, n6497_1, - n6498, n6499, n6500, n6501, n6502_1, n6503, n6504, n6505, n6506, - n6507_1, n6508, n6509, n6510, n6511, n6512_1, n6513, n6514, n6515, - n6516, n6517_1, n6518, n6519, n6520, n6521, n6522_1, n6523, n6524, - n6525, n6526_1, n6527, n6528, n6529, n6530, n6531_1, n6532, n6533, - n6534, n6535, n6536_1, n6537, n6538, n6539, n6540, n6541_1, n6542, - n6543, n6544, n6545, n6546_1, n6547, n6548, n6549, n6550, n6551_1, - n6552, n6553, n6554, n6555_1, n6556, n6557, n6558, n6559, n6560_1, - n6561, n6562, n6563, n6564, n6565_1, n6566, n6567, n6568, n6569, - n6570_1, n6571, n6572, n6573, n6574, n6575_1, n6576, n6577, n6578, - n6579, n6580_1, n6581, n6582, n6583, n6584, n6585_1, n6586, n6587, - n6588, n6589, n6590_1, n6591, n6592, n6593, n6594, n6595_1, n6596, - n6597, n6598, n6599, n6600_1, n6601, n6602, n6603, n6604, n6605_1, - n6606, n6607, n6608, n6609, n6610_1, n6611, n6612, n6613, n6614, - n6615_1, n6616, n6617, n6618, n6619, n6620_1, n6621, n6622, n6623, - n6624_1, n6625, n6626, n6627, n6628, n6629_1, n6630, n6631, n6632, - n6633, n6634_1, n6635, n6636, n6637, n6638_1, n6639, n6640, n6641, - n6642_1, n6643, n6644, n6645, n6646_1, n6647, n6648, n6649, n6650, - n6651_1, n6652, n6653, n6654, n6655, n6656_1, n6657, n6658, n6659, - n6660, n6661_1, n6662, n6663, n6664, n6665_1, n6666, n6667, n6668, - n6669, n6670_1, n6671, n6672, n6673, n6674, n6675_1, n6676, n6677, - n6678, n6679, n6680_1, n6681, n6682, n6683, n6684, n6685, n6686, n6687, - n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695, n6696, n6697, - n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705, n6706, n6707, - n6708, n6709, n6710, n6711, n6712, n6713, n6714, n6715, n6716, n6717, - n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725, n6726, n6727, - n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735, n6736, n6737, - n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6745, n6746, n6747, - n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755, n6756, n6757, - n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765, n6766, n6767, - n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775, n6776, n6777, - n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785, n6786, n6787, - n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795, n6796, n6797, - n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805, n6806, n6807, - n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815, n6816, n6817, - n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825, n6826, n6827, - n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835, n6836, n6837, - n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845, n6846, n6847, - n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855, n6856, n6857, - n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865, n6866, n6867, - n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875, n6876, n6877, - n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885, n6886, n6887, - n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895, n6896, n6897, - n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905, n6906, n6907, - n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915, n6916, n6917, - n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925, n6926, n6927, - n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935, n6936, n6937, - n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945, n6946, n6947, - n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955, n6956, n6957, - n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965, n6966, n6967, - n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975, n6976, n6977, - n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985, n6986, n6987, - n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995, n6996, n6997, - n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005, n7006, n7007, - n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015, n7016, n7017, - n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025, n7026, n7027, - n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035, n7036, n7037, - n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045, n7046, n7047, - n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055, n7056, n7057, - n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065, n7066, n7067, - n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075, n7076, n7077, - n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085, n7086, n7087, - n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095, n7096, n7097, - n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105, n7106, n7107, - n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115, n7116, n7117, - n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125, n7126, n7127, - n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135, n7136, n7137, - n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145, n7146, n7147, - n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155, n7156, n7157, - n7158, n7159, n7160, n7161, n7162, n7163, n7164, n7165, n7166, n7167, - n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175, n7176, n7177, - n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185, n7186, n7187, - n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195, n7196, n7197, - n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205, n7206, n7207, - n7208, n7209, n7210, n7211, n7212, n7213, n7214, n7215, n7216, n7217, - n7218, n7219, n7220, n7221, n7222, n7223, n7224, n7225, n7226, n7227, - n7228, n7229, n7230, n7231, n7232, n7233, n7234, n7235, n7236, n7237, - n7238, n7239, n7240, n7241, n7242, n7243, n7244, n7245, n7246, n7247, - n7248, n7249, n7250, n7251, n7252, n7253, n7254, n7255, n7256, n7257, - n7258, n7259, n7260, n7261, n7262, n7263, n7264, n7265, n7266, n7267, - n7268, n7269, n7270, n7271, n7272, n7273, n7274, n7275, n7276, n7277, - n7278, n7279, n7280, n7281, n7282, n7283, n7284, n7285, n7286, n7287, - n7288, n7289, n7290, n7291, n7292, n7293, n7294, n7295, n7296, n7297, - n7298, n7299, n7300, n7301, n7302, n7303, n7304, n7305, n7306, n7307, - n7308, n7309, n7310, n7311, n7312, n7313, n7314, n7315, n7316, n7317, - n7318, n7319, n7320, n7321, n7322, n7323, n7324, n7325, n7326, n7327, - n7328, n7329, n7330, n7331, n7332, n7333, n7334, n7335, n7336, n7337, - n7338, n7339, n7340, n7341, n7342, n7343, n7344, n7345, n7346, n7347, - n7348, n7349, n7350, n7351, n7352, n7353, n7354, n7355, n7356, n7357, - n7358, n7359, n7360, n7361, n7362, n7363, n7364, n7365, n7366, n7367, - n7368, n7369, n7370, n7371, n7372, n7373, n7374, n7375, n7376, n7377, - n7378, n7379, n7380, n7381, n7382, n7383, n7384, n7385, n7386, n7387, - n7388, n7389, n7390, n7391, n7392, n7393, n7394, n7395, n7396, n7397, - n7398, n7399, n7400, n7401, n7402, n7403, n7404, n7405, n7406, n7407, - n7408, n7409, n7410, n7411, n7412, n7413, n7414, n7415, n7416, n7417, - n7418, n7419, n7420, n7421, n7422, n7423, n7424, n7425, n7426, n7427, - n7428, n7429, n7430, n7431, n7432, n7433, n7434, n7435, n7436, n7437, - n7438, n7439, n7440, n7441, n7442, n7443, n7444, n7445, n7446, n7447, - n7448, n7449, n7450, n7451, n7452, n7453, n7454, n7455, n7456, n7457, - n7458, n7459, n7460, n7461, n7462, n7463, n7464, n7465, n7466, n7467, - n7468, n7469, n7470, n7471, n7472, n7473, n7474, n7475, n7476, n7477, - n7478, n7479, n7480, n7481, n7482, n7483, n7484, n7485, n7486, n7487, - n7488, n7489, n7490, n7491, n7492, n7493, n7494, n7495, n7496, n7497, - n7498, n7499, n7500, n7501, n7502, n7503, n7504, n7505, n7506, n7507, - n7508, n7509, n7510, n7511, n7512, n7513, n7514, n7515, n7516, n7517, - n7518, n7519, n7520, n7521, n7522, n7523, n7524, n7525, n7526, n7527, - n7528, n7529, n7530, n7531, n7532, n7533, n7534, n7535, n7536, n7537, - n7538, n7539, n7540, n7541, n7542, n7543, n7544, n7545, n7546, n7547, - n7548, n7549, n7550, n7551, n7552, n7553, n7554, n7555, n7556, n7557, - n7558, n7559, n7560, n7561, n7562, n7563, n7564, n7565, n7566, n7567, - n7568, n7569, n7570, n7571, n7572, n7573, n7574, n7575, n7576, n7577, - n7578, n7579, n7580, n7581, n7582, n7583, n7584, n7585, n7586, n7587, - n7588, n7589, n7590, n7591, n7592, n7593, n7594, n7595, n7596, n7597, - n7598, n7599, n7600, n7601, n7602, n7603, n7604, n7605, n7606, n7607, - n7608, n7609, n7610, n7611, n7612, n7613, n7614, n7615, n7616, n7617, - n7618, n7619, n7620, n7621, n7622, n7623, n7624, n7625, n7626, n7627, - n7628, n7629, n7630, n7631, n7632, n7633, n7634, n7635, n7636, n7637, - n7638, n7639, n7640, n7641, n7642, n7643, n7644, n7645, n7646, n7647, - n7648, n7649, n7650, n7651, n7652, n7653, n7654, n7655, n7656, n7657, - n7658, n7659, n7660, n7661, n7662, n7663, n7664, n7665, n7666, n7667, - n7668, n7669, n7670, n7671, n7672, n7673, n7674, n7675, n7676, n7677, - n7678, n7679, n7680, n7681, n7682, n7683, n7684, n7685, n7686, n7687, - n7688, n7689, n7690, n7691, n7692, n7693, n7694, n7695, n7696, n7697, - n7698, n7699, n7700, n7701, n7702, n7703, n7704, n7705, n7706, n7707, - n7708, n7709, n7710, n7711, n7712, n7713, n7714, n7715, n7716, n7717, - n7718, n7719, n7720, n7721, n7722, n7723, n7724, n7725, n7726, n7727, - n7728, n7729, n7730, n7731, n7732, n7733, n7734, n7735, n7736, n7737, - n7738, n7739, n7740, n7741, n7742, n7743, n7744, n7745, n7746, n7747, - n7748, n7749, n7750, n7751, n7752, n7753, n7754, n7755, n7756, n7757, - n7758, n7759, n7760, n7761, n7762, n7763, n7764, n7765, n7766, n7767, - n7768, n7769, n7770, n7771, n7772, n7773, n7774, n7775, n7776, n7777, - n7778, n7779, n7780, n7781, n7782, n7783, n7784, n7785, n7786, n7787, - n7788, n7789, n7790, n7791, n7792, n7793, n7794, n7795, n7796, n7797, - n7798, n7799, n7800, n7801, n7802, n7803, n7804, n7805, n7806, n7807, - n7808, n7809, n7810, n7811, n7812, n7813, n7814, n7815, n7816, n7817, - n7818, n7819, n7820, n7821, n7822, n7823, n7824, n7825, n7826, n7827, - n7828, n7829, n7830, n7831, n7832, n7833, n7834, n7835, n7836, n7837, - n7838, n7839, n7840, n7841, n7842, n7843, n7844, n7845, n7846, n7847, - n7848, n7849, n7850, n7851, n7852, n7853, n7854, n7855, n7856, n7857, - n7858, n7859, n7860, n7861, n7862, n7863, n7864, n7865, n7866, n7867, - n7868, n7869, n7870, n7871, n7872, n7873, n7874, n7875, n7876, n7877, - n7878, n7879, n7880, n7881, n7882, n7883, n7884, n7885, n7886, n7887, - n7888, n7889, n7890, n7891, n7892, n7893, n7894, n7895, n7896, n7897, - n7898, n7899, n7900, n7901, n7902, n7903, n7904, n7905, n7906, n7907, - n7908, n7909, n7910, n7911, n7912, n7913, n7914, n7915, n7916, n7917, - n7918, n7919, n7920, n7921, n7922, n7923, n7924, n7925, n7926, n7927, - n7928, n7929, n7930, n7931, n7932, n7933, n7934, n7935, n7936, n7937, - n7938, n7939, n7940, n7941, n7942, n7943, n7944, n7945, n7946, n7947, - n7948, n7949, n7950, n7951, n7952, n7953, n7954, n7955, n7956, n7957, - n7958, n7959, n7960, n7961, n7962, n7963, n7964, n7965, n7966, n7967, - n7968, n7969, n7970, n7971, n7972, n7973, n7974, n7975, n7976, n7977, - n7978, n7979, n7980, n7981, n7982, n7983, n7984, n7985, n7986, n7987, - n7988, n7989, n7990, n7991, n7992, n7993, n7994, n7995, n7996, n7997, - n7998, n7999, n8000, n8001, n8002, n8003, n8004, n8005, n8006, n8007, - n8008, n8009, n8010, n8011, n8012, n8013, n8014, n8015, n8016, n8017, - n8018, n8019, n8020, n8021, n8022, n8023, n8024, n8025, n8026, n8027, - n8028, n8029, n8030, n8031, n8032, n8033, n8034, n8035, n8036, n8037, - n8038, n8039, n8040, n8041, n8042, n8043, n8044, n8045, n8046, n8047, - n8048, n8049, n8050, n8051, n8052, n8053, n8054, n8055, n8056, n8057, - n8058, n8059, n8061, n8062, n8063, n8064, n8065, n8066, n8067, n8068, - n8069, n8070, n8071, n8072, n8073, n8074, n8075, n8076, n8077, n8078, - n8079, n8080, n8081, n8082, n8083, n8084, n8085, n8086, n8087, n8088, - n8089, n8090, n8091, n8092, n8093, n8094, n8095, n8096, n8097, n8098, - n8099, n8100, n8101, n8102, n8103, n8104, n8105, n8106, n8107, n8108, - n8109, n8110, n8111, n8112, n8113, n8114, n8115, n8116, n8117, n8118, - n8119, n8120, n8121, n8122, n8123, n8124, n8125, n8126, n8127, n8128, - n8129, n8130, n8131, n8132, n8133, n8134, n8135, n8136, n8137, n8138, - n8139, n8140, n8141, n8142, n8143, n8144, n8145, n8146, n8147, n8148, - n8149, n8150, n8151, n8153, n8154, n8155, n8156, n8157, n8158, n8159, - n8160, n8161, n8162, n8163, n8164, n8165, n8166, n8167, n8168, n8169, - n8170, n8171, n8172, n8173, n8174, n8175, n8176, n8177, n8178, n8179, - n8180, n8181, n8182, n8183, n8184, n8185, n8186, n8187, n8188, n8189, - n8190, n8191, n8192, n8193, n8194, n8195, n8196, n8197, n8198, n8199, - n8200, n8201, n8202, n8203, n8204, n8205, n8206, n8207, n8208, n8209, - n8210, n8211, n8212, n8213, n8214, n8215, n8216, n8217, n8218, n8219, - n8220, n8221, n8222, n8223, n8224, n8225, n8226, n8227, n8228, n8229, - n8230, n8231, n8232, n8233, n8234, n8235, n8236, n8237, n8238, n8239, - n8240, n8241, n8242, n8243, n8244, n8245, n8246, n8247, n8248, n8249, - n8250, n8251, n8252, n8253, n8254, n8255, n8256, n8257, n8258, n8259, - n8260, n8261, n8262, n8263, n8264, n8265, n8266, n8267, n8268, n8269, - n8270, n8271, n8272, n8273, n8274, n8275, n8276, n8277, n8278, n8279, - n8280, n8281, n8282, n8283, n8284, n8285, n8286, n8287, n8288, n8289, - n8290, n8291, n8292, n8293, n8294, n8295, n8296, n8297, n8298, n8299, - n8300, n8301, n8302, n8303, n8304, n8305, n8306, n8307, n8308, n8309, - n8310, n8311, n8312, n8313, n8314, n8315, n8316, n8317, n8318, n8319, - n8320, n8321, n8322, n8323, n8324, n8325, n8326, n8327, n8328, n8329, - n8330, n8331, n8332, n8333, n8334, n8335, n8336, n8337, n8338, n8339, - n8340, n8341, n8342, n8343, n8344, n8346, n8347, n8348, n8350, n8351, - n8352, n8353, n8354, n8355, n8356, n8357, n8358, n8359, n8360, n8361, - n8362, n8363, n8364, n8365, n8366, n8367, n8368, n8369, n8370, n8371, - n8372, n8373, n8374, n8375, n8376, n8377, n8378, n8379, n8380, n8381, - n8382, n8383, n8384, n8385, n8386, n8387, n8388, n8389, n8390, n8391, - n8392, n8393, n8394, n8395, n8396, n8397, n8398, n8399, n8400, n8401, - n8402, n8403, n8404, n8405, n8406, n8407, n8408, n8409, n8410, n8411, - n8412, n8413, n8414, n8415, n8416, n8417, n8418, n8419, n8420, n8421, - n8422, n8423, n8424, n8425, n8426, n8427, n8428, n8429, n8430, n8431, - n8432, n8433, n8434, n8435, n8436, n8437, n8438, n8439, n8440, n8441, - n8442, n8443, n8444, n8445, n8446, n8447, n8448, n8449, n8450, n8451, - n8452, n8453, n8454, n8455, n8456, n8457, n8458, n8459, n8460, n8461, - n8462, n8463, n8464, n8465, n8466, n8467, n8468, n8469, n8470, n8471, - n8472, n8473, n8474, n8475, n8476, n8477, n8478, n8479, n8480, n8481, - n8482, n8483, n8484, n8485, n8486, n8487, n8488, n8489, n8490, n8491, - n8492, n8493, n8494, n8495, n8496, n8497, n8498, n8499, n8500, n8501, - n8502, n8503, n8504, n8505, n8506, n8507, n8508, n8509, n8510, n8511, - n8512, n8513, n8514, n8515, n8516, n8517, n8518, n8519, n8520, n8521, - n8522, n8523, n8524, n8525, n8526, n8527, n8528, n8529, n8533, n8534, - n8535, n8540, n8541, n8542, n8543, n8544, n8546, n8548, n8550, n8552, - n8554, n8556, n8558, n8560, n8562, n8563, n8565, n8566, n8568, n8569, - n8571, n8572, n8574, n8576, n8577, n8579, n8580, n8582, n8584, n8586, - n8587, n8589, n8590, n8592, n8593, n8595, n8596, n8598, n8599, n8601, - n8602, n8604, n8605, n8607, n8608, n8610, n8614, n8616, n8618, n8620, - n8622, n8624, n8626, n8628, n8630, n8632, n8634, n8636, n8637, n8639, - n8641, n8642, n8644, n8645, n8647, n8648, n8649, n8650, n8651, n8652, - n8653, n8654, n8655, n8656, n8657, n8658, n8659, n8660, n8661, n8662, - n8663, n8664, n8665, n8667, n8668, n8669, n8670, n8671, n8673, n8674, - n8676, n8678, n8680, n8681, n8683, n8685, n8686, n8688, n8690, n8691, - n8693, n8695, n8696, n8698, n8700, n8701, n8703, n8705, n8706, n8708, - n8710, n8711, n8713, n8715, n8716, n8718, n8720, n8722, n8723, n8724, - n8726, n8728, n8730, n8732, n8734, n8736, n8738, n8740, n8742, n8744, - n8745, n8747, n8748, n8750, n8752, n8754, n8756, n8758, n8760, n8761, - n8762, n8764, n8766, n8768, n8770, n8771, n8772, n8774, n8776, n8778, - n8779, n8780, n8782, n8784, n8786, n8788, n8790, n8792, n8794, n8796, - n8798, n8800, n8802, n8804, n8806, n8808, n8810, n8812, n8814, n8816, - n8818, n8820, n8822, n8824, n8826, n8828, n8830, n8832, n8834, n8836, - n8838, n8839, n8841, n8842, n8844, n8845, n8847, n8849, n8851, n8853, - n8855, n8857, n8859, n8861, n8863, n8864, n8866, n8867, n8869, n8871, - n8873, n8874, n8876, n8877, n8879, n8881, n8883, n8884, n8886, n8887, - n8889, n8891, n8893, n8894, n8896, n8897, n8899, n8901, n8903, n8904, - n8906, n8907, n8909, n8910, n8912, n8914, n8915, n8917, n8919, n8920, - n8922, n8923, n8925, n8927, n8929, n8930, n8932, n8933, n8935, n8937, - n8939, n8940, n8942, n8943, n8945, n8947, n8949, n8950, n8952, n8954, - n8956, n8957, n8959, n8961, n8962, n8964, n8966, n8968, n8970, n8972, - n8974, n8976, n8978, n8980, n8982, n8984, n8986, n8988, n8990, n8992, - n8994, n8996, n8998, n9000, n9002, n9004, n9006, n9008, n9010, n9012, - n9014, n9016, n9018, n9020, n9022, n9024, n9026, n9028, n9030, n9032, - n9034, n9036, n9038, n9040, n9042, n9044, n9046, n9048, n9050, n9052, - n9054, n9056, n9058, n9060, n9062, n9064, n9066, n9068, n9070, n9071, - n9072, n9073, n9074, n9075, n9076, n9077, n9078, n9079, n9080, n9081, - n9082, n9083, n9084, n9085, n9086, n9087, n9088, n9089, n9090, n9091, - n9092, n9093, n9094, n9095, n9096, n9097, n9098, n9099, n9100, n9101, - n9102, n9103, n9104, n9105, n9106, n9107, n9108, n9109, n9110, n9111, - n9112, n9113, n9114, n9115, n9116, n9117, n9118, n9119, n9120, n9121, - n9122, n9123, n9124, n9125, n9126, n9127, n9128, n9129, n9130, n9131, - n9132, n9133, n9134, n9135, n9136, n9137, n9138, n9139, n9140, n9141, - n9142, n9143, n9144, n9145, n9146, n9147, n9148, n9149, n9150, n9151, - n9152, n9153, n9154, n9155, n9156, n9157, n9158, n9159, n9160, n9161, - n9162, n9163, n9164, n9165, n9166, n9167, n9168, n9169, n9170, n9171, - n9172, n9173, n9174, n9175, n9176, n9177, n9178, n9179, n9180, n9181, - n9182, n9183, n9184, n9185, n9186, n9187, n9188, n9189, n9190, n9191, - n9192, n9193, n9194, n9195, n9196, n9197, n9198, n9199, n9200, n9201, - n9202, n9203, n9204, n9205, n9206, n9207, n9208, n9209, n9210, n9211, - n9212, n9213, n9214, n9215, n9216, n9217, n9218, n9219, n9220, n9221, - n9222, n9223, n9224, n9225, n9226, n9227, n9228, n9229, n9230, n9231, - n9232, n9233, n9234, n9235, n9236, n9237, n9238, n9239, n9240, n9241, - n9242, n9243, n9244, n9245, n9246, n9247, n9248, n9249, n9250, n9251, - n9252, n9253, n9254, n9255, n9256, n9257, n9258, n9259, n9260, n9261, - n9262, n9263, n9264, n9265, n9266, n9267, n9268, n9269, n9270, n9271, - n9272, n9273, n9274, n9275, n9276, n9277, n9278, n9279, n9280, n9281, - n9282, n9283, n9284, n9285, n9286, n9287, n9288, n9289, n9290, n9291, - n9292, n9293, n9294, n9295, n9296, n9297, n9298, n9299, n9300, n9301, - n9302, n9303, n9304, n9305, n9306, n9307, n9308, n9309, n9310, n9311, - n9312, n9313, n9314, n9315, n9316, n9317, n9318, n9319, n9320, n9321, - n9322, n9323, n9324, n9325, n9326, n9327, n9328, n9329, n9330, n9331, - n9332, n9333, n9334, n9335, n9336, n9337, n9338, n9339, n9340, n9341, - n9342, n9343, n9344, n9345, n9346, n9347, n9348, n9349, n9350, n9351, - n9352, n9353, n9354, n9355, n9356, n9357, n9358, n9359, n9360, n9361, - n9362, n9363, n9364, n9365, n9366, n9367, n9368, n9369, n9370, n9371, - n9372, n9373, n9374, n9375, n9376, n9377, n9378, n9379, n9380, n9381, - n9382, n9383, n9384, n9385, n9386, n9387, n9388, n9389, n9390, n9391, - n9392, n9393, n9394, n9395, n9396, n9397, n9398, n9399, n9400, n9401, - n9402, n9417, n9418, n9419, n9420, n9421, n9422, n9423, n9424, n9425, - n9426, n9427, n9428, n9429, n9430, n9431, n9432, n9433, n9434, n9435, - n9436, n9437, n9438, n9439, n9440, n9441, n9442, n9443, n9444, n9445, - n9446, n9447, n9448, n9449, n9450, n9451, n9452, n9453, n9454, n9455, - n9456, n9457, n9458, n9459, n9460, n9461, n9462, n9463, n9464, n9465, - n9466, n9467, n9468, n9469, n9470, n9471, n9472, n9473, n9474, n687, - n692_1, n697_1, n702_1, n707_1, n712, n716, n721_1, n726_1, n731_1, - n736_1, n741_1, n746_1, n751_1, n756_1, n761_1, n766_1, n771_1, n776_1, - n780_1, n785_1, n790_1, n795_1, n800_1, n805_1, n810_1, n815_1, n820_1, - n823_1, n828_1, n833_1, n837_1, n841_1, n846_1, n851_1, n856_1, n861_1, - n866_1, n871_1, n876_1, n881_1, n886_1, n890_1, n895_1, n900_1, n905_1, - n910_1, n914_1, n919_1, n924_1, n929, n934_1, n939_1, n944_1, n948_1, - n953_1, n958_1, n963_1, n968_1, n973_1, n978_1, n983_1, n988_1, n993_1, - n998_1, n1003_1, n1008_1, n1013_1, n1018_1, n1022_1, n1026_1, n1031_1, - n1036_1, n1041_1, n1045_1, n1049_1, n1054_1, n1059_1, n1064_1, n1068_1, - n1072_1, n1077_1, n1082, n1087_1, n1092_1, n1097_1, n1102, n1107_1, - n1112_1, n1117, n1122_1, n1127, n1132_1, n1136_1, n1140_1, n1145_1, - n1150_1, n1155_1, n1160_1, n1165_1, n1170_1, n1174, n1177, n1181, - n1186, n1191_1, n1196_1, n1201_1, n1205_1, n1209_1, n1214, n1219_1, - n1224_1, n1228_1, n1232_1, n1237_1, n1242_1, n1247, n1252, n1257_1, - n1262, n1267_1, n1272_1, n1277_1, n1282_1, n1287_1, n1292_1, n1297_1, - n1302, n1307_1, n1312_1, n1317_1, n1322_1, n1327_1, n1331_1, n1335_1, - n1339_1, n1344, n1349_1, n1354_1, n1358_1, n1362_1, n1367, n1372_1, - n1377_1, n1382_1, n1387_1, n1392_1, n1397_1, n1402_1, n1407_1, n1411_1, - n1415_1, n1420, n1423, n1428_1, n1433_1, n1438_1, n1442, n1447, - n1452_1, n1457, n1462_1, n1467, n1472_1, n1477, n1481, n1485_1, n1490, - n1495_1, n1500, n1504, n1509, n1513, n1517, n1522_1, n1527, n1532_1, - n1537_1, n1542_1, n1547_1, n1552_1, n1557_1, n1562_1, n1567, n1572_1, - n1577_1, n1581, n1586, n1591_1, n1596_1, n1601_1, n1606_1, n1611_1, - n1616, n1621_1, n1626_1, n1631_1, n1636_1, n1641_1, n1646_1, n1650, - n1654, n1659, n1664_1, n1669_1, n1674, n1679_1, n1684_1, n1689_1, - n1694_1, n1699_1, n1704_1, n1709_1, n1714, n1717_1, n1722_1, n1727_1, - n1732_1, n1737_1, n1742_1, n1747_1, n1752, n1757_1, n1762_1, n1767_1, - n1772, n1777, n1782_1, n1787_1, n1792, n1797, n1802, n1807_1, n1812_1, - n1816_1, n1821_1, n1826_1, n1831_1, n1836_1, n1840, n1844_1, n1849_1, - n1854, n1859_1, n1864_1, n1868, n1873_1, n1878_1, n1883_1, n1888_1, - n1893_1, n1898_1, n1903_1, n1908_1, n1912_1, n1916_1, n1920_1, n1925_1, - n1930_1, n1935_1, n1940_1, n1945_1, n1950_1, n1955, n1959, n1964, - n1969_1, n1974_1, n1979_1, n1983_1, n1988, n1993_1, n1998_1, n2002_1, - n2007_1, n2012_1, n2017_1, n2022_1, n2027_1, n2031, n2035, n2040, - n2045, n2050, n2055_1, n2060, n2065_1, n2070, n2074, n2078_1, n2083, - n2087, n2092, n2096_1, n2101_1, n2106_1, n2111, n2116, n2120_1, n2124, - n2127_1, n2131_1, n2136, n2141_1, n2146, n2150, n2154, n2159_1, - n2164_1, n2169_1, n2173_1, n2178, n2183_1, n2188_1, n2193, n2198, - n2203_1, n2208_1, n2212, n2217_1, n2222, n2227, n2232_1, n2237_1, - n2242_1, n2247, n2252, n2257, n2261_1, n2265, n2270_1, n2275, n2280_1, - n2285_1, n2289_1, n2293_1, n2297_1, n2301_1, n2306, n2309_1, n2313, - n2318_1, n2323_1, n2328_1, n2331_1, n2336_1, n2341_1, n2345_1, n2349_1, - n2354_1, n2359_1, n2364_1, n2369_1, n2374_1, n2379_1, n2384_1, n2388_1, - n2393_1, n2398_1, n2403_1, n2408_1, n2413, n2418, n2423, n2428_1, - n2432, n2436_1, n2441_1, n2445, n2449_1, n2454_1, n2458, n2463_1, - n2468_1, n2473_1, n2478_1, n2483, n2488_1, n2493, n2498_1, n2502, - n2506, n2511_1, n2516, n2521_1, n2525, n2530, n2535_1, n2540, n2545_1, - n2550_1, n2555_1, n2560_1, n2565_1, n2570, n2575, n2580_1, n2585_1, - n2590_1, n2595_1, n2600_1, n2605_1, n2610_1, n2615_1, n2619_1, n2624_1, - n2629_1, n2634_1, n2639_1, n2644_1, n2649_1, n2654, n2659_1, n2663, - n2668_1, n2672_1, n2677_1, n2682_1, n2687_1, n2692_1, n2697, n2701_1, - n2705_1, n2710_1, n2715_1, n2720_1, n2725_1, n2729_1, n2733_1, n2738_1, - n2743, n2748_1, n2752_1, n2755_1, n2760_1, n2765_1, n2770, n2774_1, - n2778_1, n2783_1, n2788_1, n2793_1, n2798_1, n2803_1, n2808_1, n2813_1, - n2818_1, n2823_1, n2828, n2833_1, n2838_1, n2843_1, n2848_1, n2852_1, - n2857_1, n2862_1, n2867_1, n2872_1, n2876_1, n2881_1, n2885_1, n2890_1, - n2895_1, n2899_1, n2904_1, n2909_1, n2914_1, n2919_1, n2924_1, n2929_1, - n2934_1, n2937_1, n2941_1, n2946_1, n2951_1, n2956_1, n2961_1, n2966_1, - n2971_1, n2975_1, n2979_1, n2984_1, n2989_1, n2994_1, n2999_1, n3004_1, - n3009_1, n3013_1, n3018_1, n3023_1, n3028_1, n3033_1, n3038_1, n3042_1, - n3047, n3052, n3057, n3061, n3065_1, n3070, n3075, n3079, n3082, - n3086_1, n3091, n3096_1, n3101_1, n3106, n3111, n3116_1, n3121, n3126, - n3131_1, n3136, n3141_1, n3146, n3151_1, n3156_1, n3161, n3165, - n3170_1, n3175_1, n3180_1, n3185_1, n3190, n3195, n3200, n3205, - n3210_1, n3215, n3219_1, n3223_1, n3228, n3232_1, n3237, n3242_1, - n3247_1, n3252, n3257_1, n3262_1, n3267, n3270, n3275_1, n3279_1, - n3282_1, n3286_1, n3291_1, n3296_1, n3301, n3306_1, n3311, n3316_1, - n3321, n3326_1, n3331_1, n3336, n3340_1, n3345, n3350_1, n3355_1, - n3360, n3365_1, n3370_1, n3375, n3379, n3382_1, n3386_1, n3391_1, - n3396_1, n3401_1, n3406_1, n3411, n3416, n3421_1, n3426_1, n3431_1, - n3435_1, n3439, n3444_1, n3449, n3454, n3459_1, n3464_1, n3468_1, - n3471, n3476_1, n3480_1, n3485_1, n3490, n3495_1, n3500_1, n3505, - n3510_1, n3515, n3519_1, n3524, n3528_1, n3533, n3538, n3543, n3548, - n3553, n3558, n3561, n3566_1, n3571_1, n3576, n3581_1, n3586_1, - n3591_1, n3595, n3599, n3604, n3608_1, n3613_1, n3618_1, n3623, n3627, - n3631, n3636_1, n3641, n3646_1, n3651_1, n3656_1, n3661, n3665_1, - n3670_1, n3675, n3680_1, n3685_1, n3690_1, n3695, n3700, n3705, - n3710_1, n3715_1, n3720_1, n3725, n3730, n3735, n3740, n3745, n3750_1, - n3755_1, n3760, n3765_1, n3770_1, n3775, n3779, n3783_1, n3788_1, - n3792, n3797_1, n3802_1, n3807_1, n3812_1, n3817_1, n3822_1, n3827_1, - n3832_1, n3837_1, n3842_1, n3847_1, n3851_1, n3856, n3861_1, n3866_1, - n3871_1, n3876_1, n3881_1, n3886, n3891_1, n3896, n3900_1, n3903_1, - n3907_1, n3912, n3917, n3922, n3927, n3932, n3937_1, n3942_1, n3947, - n3952_1, n3957_1, n3962, n3967_1, n3971_1, n3975, n3980_1, n3984_1, - n3988, n3992, n3996_1, n4001, n4006, n4010_1, n4015, n4020, n4025_1, - n4030, n4035_1, n4039_1, n4042, n4047_1, n4052_1, n4057, n4062, n4066, - n4070_1, n4075, n4080, n4084, n4089_1, n4094_1, n4099, n4104, n4109, - n4114_1, n4119, n4124, n4128, n4133_1, n4138_1, n4142_1, n4147, n4151, - n4156_1, n4160_1, n4164, n4169_1, n4174, n4178_1, n4182_1, n4187, - n4192_1, n4197, n4202_1, n4206, n4211_1, n4216, n4221_1, n4226_1, - n4231_1, n4235_1, n4239_1, n4244, n4249, n4254, n4259_1, n4263_1, - n4267_1, n4272_1, n4277_1, n4282, n4287_1, n4291_1, n4296_1, n4301_1, - n4306, n4311_1, n4316_1, n4321_1, n4326_1, n4331_1, n4336_1, n4340_1, - n4344_1, n4349_1, n4354_1, n4359_1, n4364_1, n4369, n4374_1, n4379_1, - n4384_1, n4389_1, n4393_1, n4397_1, n4402_1, n4407_1, n4412_1, n4417_1, - n4422, n4427_1, n4432_1, n4437, n4442_1, n4447, n4452, n4456, n4460, - n4465_1, n4470, n4475, n4480, n4485, n4489, n4492_1, n4495, n4499, - n4504, n4509_1, n4514, n4519, n4524, n4529, n4534, n4539, n4544_1, - n4549, n4554, n4559_1, n4564_1, n4569_1, n4574, n4578, n4582_1, - n4587_1, n4592, n4597_1, n4602, n4607, n4612, n4617, n4622, n4627, - n4631, n4636, n4640_1, n4644, n4648, n4652_1, n4657_1, n4662, n4667_1, - n4672_1, n4677_1, n4682, n4687, n4692_1, n4697_1, n4702_1, n4707_1, - n4712_1, n4717_1, n4722_1, n4727_1, n4731_1, n4736_1, n4741_1, n4746, - n4751_1, n4756, n4761_1, n4766, n4770_1, n4773_1, n4777_1, n4782, - n4787_1, n4792_1, n4797, n4802, n4807_1, n4812, n4817, n4822, n4827, - n4832_1, n4837_1, n4842_1, n4846_1, n4851_1, n4855_1, n4859_1, n4864_1, - n4868_1, n4873_1, n4877, n4882, n4887_1, n4890, n4894_1, n4899, n4904, - n4909_1, n4914_1, n4919_1, n4924_1, n4929_1, n4934_1, n4939, n4944, - n4948_1, n4953_1, n4958_1, n4963_1, n4968_1, n4973, n4978, n4983_1, - n4987, n4992, n4997, n5002, n5007, n5011_1, n5016, n5021, n5026, - n5031_1, n5036, n5041, n5046_1, n5051_1, n5056_1, n5060, n5064, n5069, - n5074_1, n5079_1, n5083_1, n5088_1, n5093_1, n5098, n5103, n5107, - n5111, n5116, n5121, n5126, n5131, n5136_1, n5141, n5146, n5151_1, - n5156, n5160_1, n5165_1, n5170_1, n5175_1, n5180_1, n5185_1, n5190_1, - n5195_1, n5200_1, n5205_1, n5210_1, n5214_1, n5218_1, n5223_1, n5228_1, - n5233_1, n5237_1, n5241_1, n5246_1, n5251, n5256_1, n5261, n5265_1, - n5269_1, n5273, n5278_1, n5283_1, n5288_1, n5293_1, n5298, n5303_1, - n5308_1, n5313_1, n5318, n5322, n5326_1, n5331_1, n5335_1, n5339_1, - n5344_1, n5349, n5353_1, n5356_1, n5361_1, n5366_1, n5371_1, n5376_1, - n5381_1, n5385_1, n5389_1, n5393_1, n5398_1, n5402_1, n5406_1, n5411_1, - n5416, n5421_1, n5426_1, n5431_1, n5436, n5441_1, n5446_1, n5451_1, - n5456_1, n5461, n5466_1, n5471_1, n5476_1, n5481_1, n5486_1, n5491_1, - n5496_1, n5501_1, n5506_1, n5511_1, n5516_1, n5521_1, n5526_1, n5531_1, - n5536_1, n5541_1, n5545_1, n5549_1, n5554_1, n5558_1, n5563_1, n5568_1, - n5573_1, n5578_1, n5583_1, n5588_1, n5593_1, n5598, n5603_1, n5608_1, - n5613_1, n5618_1, n5623_1, n5628, n5633, n5638, n5643_1, n5648_1, - n5653, n5658_1, n5662, n5666_1, n5671, n5676_1, n5681_1, n5686, n5690, - n5695, n5700_1, n5705_1, n5710_1, n5714, n5718, n5723_1, n5728, - n5733_1, n5738_1, n5743_1, n5748, n5753, n5758_1, n5763, n5768, n5772, - n5776, n5781_1, n5786, n5791, n5796, n5801, n5806, n5811, n5816_1, - n5821_1, n5825_1, n5828_1, n5833_1, n5838_1, n5842_1, n5846, n5850_1, - n5855_1, n5859, n5864, n5869, n5874, n5879_1, n5884, n5888_1, n5893_1, - n5898, n5903_1, n5908_1, n5913_1, n5918_1, n5923_1, n5928_1, n5933_1, - n5937, n5941_1, n5946_1, n5951_1, n5956, n5961_1, n5966_1, n5971_1, - n5975_1, n5980_1, n5985_1, n5990, n5994_1, n5998, n6003_1, n6008, - n6012, n6017, n6022_1, n6027, n6032_1, n6037_1, n6042, n6047_1, - n6052_1, n6056, n6061, n6066_1, n6071_1, n6076_1, n6081, n6086_1, - n6091, n6096, n6100_1, n6104, n6109_1, n6114_1, n6119_1, n6123_1, - n6127, n6132_1, n6137, n6142, n6147, n6152, n6156, n6160, n6165, n6169, - n6174_1, n6179, n6183, n6188_1, n6192, n6196, n6201_1, n6206, n6211, - n6216, n6221, n6226, n6230, n6235, n6240, n6245, n6250, n6255, n6260, - n6265, n6270, n6275, n6279, n6284, n6289, n6293, n6297, n6302, n6306_1, - n6310, n6315, n6320, n6325_1, n6330, n6335, n6340, n6344_1, n6349, - n6354, n6359, n6364_1, n6369, n6373, n6376, n6380, n6385, n6390, n6395, - n6399, n6403, n6408_1, n6413, n6417, n6422, n6427, n6432, n6437, n6442, - n6447, n6452, n6457, n6462, n6467, n6472, n6477, n6482, n6487, n6492, - n6497, n6502, n6507, n6512, n6517, n6522, n6526, n6531, n6536, n6541, - n6546, n6551, n6555, n6560, n6565, n6570, n6575, n6580, n6585, n6590, - n6595, n6600, n6605, n6610, n6615, n6620, n6624, n6629, n6634, n6638, - n6642, n6646, n6651, n6656, n6661, n6665, n6670, n6675, n6680; - assign Pg34972 = ~n8177 | ~Ng22; - assign n4124_1 = Ng4369 & (Ng4366 | n6090); - assign Pg34927 = ~n5895 | ~Ng22; - assign Pg34925 = ~n5912 | ~Ng22; - assign Pg34923 = ~n4252 | ~Ng22; - assign Pg34921 = ~n5892 | ~Ng22; - assign Pg34919 = ~n5869_1 | ~Ng22; - assign Pg34917 = ~n5669 | ~Ng22; - assign Pg34915 = ~n5903 | ~Ng22; - assign Pg34913 = ~n4909 | ~Ng22; - assign n4133 = Ng890 & (Ng528 | n5931 | ~Ng479); - assign Pg34597 = 1'b0; - assign n4135 = ~Pg113 | ~Ng2868; - assign n4136 = ~Pg113 | ~Ng2873; - assign Pg34435 = ~n9417; - assign Pg34425 = ~n5945 | ~n6265_1; - assign Pg34383 = ~n6264 | n5901 | ~n5930; - assign Pg34240 = 1'b0; - assign Pg34239 = 1'b0; - assign Pg34238 = 1'b0; - assign Pg34237 = 1'b0; - assign Pg34236 = 1'b0; - assign Pg34235 = 1'b0; - assign Pg34234 = 1'b0; - assign Pg34233 = 1'b0; - assign Pg34232 = 1'b0; - assign Pg34221 = ~n5929 | ~n6265_1; - assign Pg34201 = ~n6264 | n5938 | ~n6122; - assign n4151_1 = Ng4646 & (n5875 | n5915); - assign Pg33950 = 1'b0; - assign Pg33949 = 1'b0; - assign Pg33948 = 1'b0; - assign Pg33947 = 1'b0; - assign Pg33946 = 1'b0; - assign Pg33945 = 1'b0; - assign Pg33935 = ~n5936; - assign Pg33874 = ~Ng4507 | \[4507] | n5924; - assign Pg33659 = ~n9418 | n5947 | ~n6264; - assign Pg33636 = ~n5950; - assign n4162 = Pg17291 & (~Ng1171 | n5914); - assign Pg33435 = (n9185 & (~Ng2729 | n9186)) | (Ng2729 & n9186); - assign Pg33079 = (n9183 & (~Ng2729 | n9184)) | (Ng2729 & n9184); - assign Pg32975 = ~n7527; - assign Pg32454 = 1'b0; - assign Pg32429 = 1'b0; - assign Pg32185 = n6847 & n6844 & n6845 & n6846; - assign Pg31863 = ~n8207; - assign Pg31862 = ~n8080; - assign Pg31860 = ~n8192; - assign Pg31793 = ~n4220; - assign Pg31521 = ~n9417; - assign Pg30331 = ~Ng2831; - assign Pg30330 = ~Ng2834; - assign Pg30329 = ~\[4426] ; - assign Pg30327 = ~Ng37; - assign Pg28042 = n4218 | n4219; - assign Pg28041 = n4217 | ~n8478; - assign Pg28030 = n4215 | n4216_1; - assign Pg26877 = ~n4214; - assign Pg26876 = ~n4211; - assign Pg26875 = ~n4208; - assign Pg26801 = ~n7527; - assign Pg25590 = 1'b0; - assign Pg25589 = 1'b0; - assign Pg25588 = 1'b0; - assign Pg25587 = 1'b0; - assign Pg25586 = 1'b0; - assign Pg25585 = 1'b0; - assign Pg25584 = 1'b0; - assign Pg25583 = 1'b0; - assign Pg25582 = 1'b0; - assign Pg25259 = ~n8080; - assign Pg25167 = ~n8207; - assign Pg25114 = ~n8192; - assign Pg24151 = 1'b0; - assign Pg23759 = ~Ng2831; - assign Pg23652 = ~Ng2834; - assign Pg23612 = ~\[4426] ; - assign Pg23190 = ~Ng25 & ~Ng22; - assign Pg23002 = ~Ng37; - assign Pg21727 = ~Pg35 & Ng3003; - assign Pg12833 = ~Pg5; - assign n4205 = ~Pg35 | n8382; - assign n4206_1 = Ng1830 | Ng2098 | Ng1696 | Ng1964; - assign n4207 = n6127_1 & Pg35; - assign n4208 = n4206_1 & n4207; - assign n4209 = Ng1710 | Ng1858 | Ng1844 | Ng2126 | Ng1724 | Ng2112 | Ng1992 | Ng1978; - assign n4210 = n5989 & Pg35; - assign n4211 = n4209 & n4210; - assign n4212 = Ng1913 | Ng2047 | Ng1932 | Ng1798 | Ng1664 | Ng1779 | Ng1644 | Ng2066; - assign n4213 = n5988 & Pg35; - assign n4214 = n4212 & n4213; - assign n4215 = n7837 & ~n8125 & (~n5906 | ~n8212); - assign n4216_1 = ~n5906 & (~n5902 | ~n5905) & n7838; - assign n4217 = ~Pg35 | n6128; - assign n4218 = ~Pg35 | Ng962; - assign n4219 = ~Pg35 | Ng1306; - assign n4220 = n6888 & (n6889 | n6890 | ~n9117); - assign n4221 = n6702 & n6703 & (Pg35 | ~Ng5052); - assign n687 = ~n4221; - assign n4223 = n6247 & (n6241 | n6246 | n6238); - assign n692_1 = ~n4223; - assign n4225 = n6439 & n6440 & (~n6006 | n6441); - assign n697_1 = ~n4225; - assign n4227 = n6374 & (Pg35 | ~Ng2380); - assign n702_1 = ~n4227; - assign n4229 = n7300 & n7301 & (n4205 | n7302); - assign n721_1 = ~n4229; - assign n4231 = n7273 & n7274 & (n4205 | n7275); - assign n731_1 = ~n4231; - assign n4233 = n7141 & n7142 & (n4205 | n7143); - assign n736_1 = ~n4233; - assign n4235 = n6172 & (Pg35 | ~Ng2984); - assign n746_1 = ~n4235; - assign n4237 = n6460 & n6461 & (~n5998_1 | n6462_1); - assign n751_1 = ~n4237; - assign n4239 = n7041 & n7042 & (n4205 | n7043); - assign n756_1 = ~n4239; - assign n4241 = (n6452_1 | ~Ng1802) & (n6616 | ~Ng1772); - assign n761_1 = ~n4241; - assign n4243 = n7229 & n7230 & (n4205 | n6723); - assign n766_1 = ~n4243; - assign n4245 = (~Ng6215 | n6667) & (~Ng6219 | n6668); - assign n771_1 = ~n4245; - assign n4247 = n6098 & n6099 & (Ng807 | n6093); - assign n776_1 = ~n4247; - assign n4249_1 = Ng1061 ^ n8020; - assign n790_1 = n4249_1 | ~n9152; - assign n4251 = Ng4172 | Ng4153; - assign n4252 = n6024 & n6021 & n6022 & n6023; - assign n795_1 = n4251 & Pg35; - assign n4254_1 = (n6726 | n6732) & (Pg35 | ~Ng3506); - assign n805_1 = ~n4254_1; - assign n4256 = n6874 & n6875 & (Ng749 | n6876); - assign n810_1 = ~n4256; - assign n4258 = (~Pg17739 & (~Pg14738 | Pg12350)) | (Pg14738 & Pg12350); - assign n820_1 = n4258 & ~Pg13068 & ~Pg17607 & Pg35 & ~Pg17646; - assign n4260 = n6483 & n6484 & (~n6010 | n6485); - assign n828_1 = ~n4260; - assign n4262 = n6623 & n6624_1 & (~n8312 | ~Ng1714); - assign n833_1 = ~n4262; - assign n841_1 = ~n6738 & ~Ng3155; - assign n4265 = n7692 & n7693 & (~Ng2165 | ~n8424); - assign n846_1 = ~n4265; - assign n4267 = ~Ng3689 | n8508; - assign n856_1 = Ng3694 & (~Pg35 | n4267); - assign n4269 = n6463 & n6464 & (~n5998_1 | n6465); - assign n861_1 = ~n4269; - assign n4271 = n7364 & (Pg35 | ~Ng1964); - assign n866_1 = ~n4271; - assign n4273 = (~Ng4621 | n6202) & (n6201 | ~Ng4639); - assign n871_1 = ~n4273; - assign n4275 = n7067 & n7068 & (n4205 | n7069); - assign n876_1 = ~n4275; - assign n4277 = n7340 & ~n9252 & (Pg35 | ~Ng2652); - assign n881_1 = ~n4277; - assign n4279 = (~Pg17711 & (~Pg14694 | Pg12300)) | (Pg14694 & Pg12300); - assign n886_1 = n4279 & ~Pg13049 & ~Pg17580 & Pg35 & ~Pg17604; - assign n4281 = n7755 & n7756 & (Ng490 | ~n8470); - assign n890_1 = ~n4281; - assign n4283 = n6293_1 & n6294 & (Ng772 | n6295); - assign n900_1 = ~n4283; - assign n4285 = n7081 & n7082 & (n4205 | n7083); - assign n905_1 = ~n4285; - assign n4287 = n7437 & ~n9281 & (~Ng6177 | n7438); - assign n910_1 = ~n4287; - assign n4289 = (n6738 | n6739) & (Pg35 | ~Ng3161); - assign n919_1 = ~n4289; - assign n4291 = n7061 & n7062 & (n4205 | n7063); - assign n924_1 = ~n4291; - assign n4293 = ~n5990_1 & n6706 & (~n6860 | ~Ng4543); - assign n929 = ~n4293; - assign n4295 = n7625 & (Ng3457 | n7626) & ~n9308; - assign n934_1 = ~n4295; - assign n4297 = n6969 & ~n9452 & (n4205 | n6970); - assign n939_1 = ~n4297; - assign n4299 = n6352 & n6353 & (~n6000 | n6354_1); - assign n948_1 = ~n4299; - assign n4301 = n6326 & (n6327 | n6328 | ~Ng4801); - assign n953_1 = ~n4301; - assign n4303 = n6221_1 & n6222 & (Pg35 | ~Ng4584); - assign n958_1 = ~n4303; - assign n4305 = ~Pg35 | ~Ng6199; - assign n963_1 = ~n4305; - assign n4307 = n6388 & n6389 & (~n6012_1 | n6390_1); - assign n968_1 = ~n4307; - assign n4309 = n7962 & n7963 & (Pg35 | ~Ng1379); - assign n973_1 = ~n4309; - assign n4311 = n8005 & (Pg35 | ~Ng1579); - assign n978_1 = ~n4311; - assign n4313 = (~Ng5176 | n6696) & (~Ng5180 | n6697); - assign n983_1 = ~n4313; - assign n4315 = n6179_1 & (Pg35 | ~Ng2890); - assign n988_1 = ~n4315; - assign n4317 = n6870 & n6871 & (Pg35 | ~Ng1018); - assign n993_1 = ~n4317; - assign n4319 = n7078 & n7079 & (n4205 | n7080); - assign n998_1 = ~n4319; - assign n4321 = n7242 & n7243 & (n4205 | n7244); - assign n1003_1 = ~n4321; - assign n4323 = (n8033 | ~Ng4258) & (n7997 | ~Ng4264); - assign n1008_1 = ~n4323; - assign n4325 = n6486 & n6487_1 & (Ng767 | n6488); - assign n1013_1 = ~n4325; - assign n4327 = ~Pg35 | ~Ng5853; - assign n1018_1 = ~n4327; - assign n4329 = n6277 & n6278 & (n6279_1 | n6276); - assign n1031_1 = ~n4329; - assign n4331 = ~Pg35 | ~Ng5507; - assign n1041_1 = ~n4331; - assign n4333 = n6966 & n6967 & (n4205 | n6968); - assign n1049_1 = ~n4333; - assign n4335 = n6650 & n6651_1 & (Pg35 | ~Ng291); - assign n1054_1 = ~n4335; - assign n4337 = n7057 & ~n9458 & (n4205 | n6682); - assign n1059_1 = ~n4337; - assign n4339 = ~n7985 & (Pg35 | ~Ng559); - assign n1077_1 = ~n4339; - assign n4341 = n6258 & (Ng608 | n6259) & ~n9441; - assign n1082 = ~n4341; - assign n4343 = n7213 & n7214 & (n4205 | n7215); - assign n1092_1 = ~n4343; - assign n4345 = n6946 & n6947 & (n4205 | n6948); - assign n1097_1 = ~n4345; - assign n4347 = n7003 & ~n9455 & (n4205 | n6673); - assign n1102 = ~n4347; - assign n4349 = (~Ng921 | n7975) & (n7974 | ~Ng904); - assign n1107_1 = ~n4349; - assign n4351 = ~Pg35 | ~n8251; - assign n1127 = Ng4871 & n4351; - assign n4353 = n7114 & n7115 & (n4205 | n7116); - assign n1132_1 = ~n4353; - assign n4355 = n7237 & n7238 & (n4205 | n7239); - assign n1140_1 = ~n4355; - assign n4357 = n6799 & n6800 & (n6795 | ~Ng1926); - assign n1145_1 = ~n4357; - assign n4359 = (n6668 | n6669) & (Pg35 | ~Ng6209); - assign n1150_1 = ~n4359; - assign n4361 = n7250 & n7251 & (n4205 | n7252); - assign n1155_1 = ~n4361; - assign n4363 = n6840 & n6841 & (Pg35 | ~Ng287); - assign n1160_1 = ~n4363; - assign n4365 = ~Pg35 | ~n8253; - assign n1165_1 = Ng4646 & n4365; - assign n4367 = n7261 & n7262 & (n4205 | n7263); - assign n1170_1 = ~n4367; - assign n4369_1 = n6609 & (n6433 | ~Ng1862); - assign n1181 = ~n4369_1; - assign n4371 = n7748 & n7749 & (Pg35 | ~Ng671); - assign n1186 = ~n4371; - assign n4373 = Ng843 ^ n8022; - assign n1191_1 = Ng837 & (~Pg35 | n4373); - assign n4375 = n6215 & (n6216_1 | ~Ng4322 | ~n8236); - assign n1196_1 = ~n4375; - assign n4377 = (Pg35 | ~Ng6395) & (n6503 | ~n9421); - assign n1209_1 = ~n4377; - assign n4379 = n6132 & n6133 & (Ng622 | n6134); - assign n1214 = ~n4379; - assign n1219_1 = ~n6728 & ~Ng3506; - assign n4382 = n7333 & (Pg35 | ~Ng2834); - assign n1237_1 = ~n4382; - assign n4384 = Ng255 | Ng269 | Ng262 | ~Ng246 | ~Ng239 | ~Ng232 | ~Ng225; - assign n4385 = Ng255 & Ng262 & Ng269 & ~Ng225 & ~Ng232 & ~Ng246 & ~Ng239; - assign n1252 = n4384 & Pg35 & (Ng278 | n4385); - assign n1262 = Ng4836 & n4351; - assign n4388 = (~Ng1036 | ~n9116) & (n6642_1 | ~Ng1030); - assign n1267_1 = ~n4388; - assign n4390 = n7554 & n7763 & (Pg35 | ~Ng5272); - assign n1272_1 = ~n4390; - assign n4392 = n7303 & ~n9469 & (n4205 | n7304); - assign n1282_1 = ~n4392; - assign n4394 = n7434 & (n4205 | (Ng6195 & n7435)); - assign n1292_1 = ~n4394; - assign n4396 = n7883 & n7884 & (Ng1135 | ~n8486); - assign n1297_1 = ~n4396; - assign n4398 = n6504 & n6505 & (n6506 | ~Ng6395); - assign n1302 = ~n4398; - assign n4400 = n6092 & (n6093 | ~Ng807); - assign n1312_1 = ~n4400; - assign n4402 = ~Pg35 | ~Ng3853; - assign n1322_1 = ~n4402; - assign n4404 = n6759 & n6760 & (n6755 | ~Ng2485); - assign n1339_1 = ~n4404; - assign n4406 = n6832 & n6833 & (Ng925 | n6834); - assign n1344 = ~n4406; - assign n4408 = n7099 & n7100 & (n4205 | n7101); - assign n1354_1 = ~n4408; - assign n4410 = n6807 & n6808 & (~Ng1798 | n6806); - assign n1362_1 = ~n4410; - assign n4412 = n6521 & n7806 & (Ng4076 | n7807); - assign n1367 = ~n4412; - assign n4414 = n7175 & n7176 & (n4205 | n6713); - assign n1377_1 = ~n4414; - assign n4416 = n6645 & n6646_1 & (Ng763 | n6647); - assign n1382_1 = ~n4416; - assign n4418 = n6987 & n6988 & (n4205 | n6989); - assign n1387_1 = ~n4418; - assign n4420 = n7852 & (Pg35 | ~Ng4427); - assign n1392_1 = ~n4420; - assign n1397_1 = Ng4864 & n4351; - assign n4423 = n6157 & (Pg35 | ~Ng4717); - assign n1402_1 = ~n4423; - assign n4425 = n6838 & (Ng590 | n6839) & ~n9448; - assign n1407_1 = ~n4425; - assign n4427 = ~n7376 & ~n9274 & (Pg35 | ~Ng1612); - assign n1415_1 = ~n4427; - assign n4429 = (~Pg17674 & (~Pg14662 | Pg12238)) | (Pg14662 & Pg12238); - assign n1420 = n4429 & ~Pg13039 & ~Pg17519 & Pg35 & ~Pg17577; - assign n4431 = n7463 & (Ng6154 | n7464) & ~n9284; - assign n1438_1 = ~n4431; - assign n4433 = n7054 & n7055 & (n4205 | n7056); - assign n1447 = ~n4433; - assign n4435 = n6455 & n6456 & (~n5998_1 | ~n8308); - assign n1452_1 = ~n4435; - assign n4437_1 = n7395 & n7396 & (Ng744 | n7397); - assign n1462_1 = ~n4437_1; - assign n4439 = n6156_1 & (Pg35 | ~Ng4722); - assign n1467 = ~n4439; - assign n4441 = n6981 & n6982 & (n4205 | n6983); - assign n1477 = ~n4441; - assign n4443 = n6999 & (Pg35 | ~Ng5961); - assign n1490 = ~n4443; - assign n4445 = n8018 & n8019 & (~Pg17400 | n8014); - assign n1500 = ~n4445; - assign n1504 = Ng4633 & (~Pg35 | (~Ng4639 & ~n6208)); - assign n4448 = n7120 & n7121 & (n4205 | n7122); - assign n1509 = ~n4448; - assign n4450 = ~Pg35 | ~Ng5160; - assign n1522_1 = ~n4450; - assign n4452_1 = n7026 & n7027 & (n4205 | n7028); - assign n1527 = ~n4452_1; - assign n4454 = n6140 & n6141; - assign n1542_1 = ~n4454; - assign n4456_1 = ~Pg35 | ~Ng3151; - assign n1547_1 = ~n4456_1; - assign n4458 = (Pg35 | ~Ng3522) & (n6725 | n6726); - assign n1562_1 = ~n4458; - assign n4460_1 = n6521 & n6522_1 & (Ng4104 | n6523); - assign n1567 = ~n4460_1; - assign n4462 = n9378 ^ Pg9251; - assign n1577_1 = n4462 & Pg35; - assign n4464 = n6399_1 & n6400 & (~n6008_1 | ~n8287); - assign n1581 = ~n4464; - assign n4466 = n6576 & (n6377 | ~Ng2287); - assign n1601_1 = ~n4466; - assign n4468 = (~Ng4269 | n8000) & (n7999 | ~Ng4273); - assign n1606_1 = ~n4468; - assign n4470_1 = n7880 & ~n9437 & (Pg35 | ~Ng1384); - assign n1611_1 = ~n4470_1; - assign n4472 = n7467 & (Pg35 | ~Ng5831); - assign n1621_1 = ~n4472; - assign n4474 = n5959 & (~Ng1193 | (~Ng1171 & Ng1183)); - assign n4475_1 = Pg7916 ^ Ng1171; - assign n1626_1 = Pg35 & (n4474 | n4475_1); - assign n4477 = (~Ng4264 | n8032) & (n7998 | ~Ng4269); - assign n1631_1 = ~n4477; - assign n4479 = (n6311 | n6312) & (Pg35 | ~Ng4818); - assign n1641_1 = ~n4479; - assign n4481 = n7064 & n7065 & (n4205 | n7066); - assign n1646_1 = ~n4481; - assign n4483 = Ng4864 | Ng4878 | Ng4836 | Ng4871; - assign n1654 = Pg35 & ~n9298 & (n4483 | ~n8760); - assign n4485_1 = n7954 & (Pg35 | ~Ng3139); - assign n1659 = ~n4485_1; - assign n4487 = n7305 & ~n9470 & (n4205 | n7306); - assign n1674 = ~n4487; - assign n4489_1 = ~n5990_1 & ~n5993 & (~n6860 | ~Ng4540); - assign n1679_1 = ~n4489_1; - assign n4491 = n7264 & n7265 & (n4205 | n7266); - assign n1684_1 = ~n4491; - assign n4493 = n7767 & (~Pg35 | n7766 | n7768); - assign n1694_1 = ~n4493; - assign n4495_1 = n6152_1 & (Pg35 | ~Ng4912); - assign n1699_1 = ~n4495_1; - assign n4497 = n7354 & (Pg35 | ~Ng2255); - assign n1704_1 = ~n4497; - assign n4499_1 = n6227 & (n6228 | n6226_1 | n6229); - assign n1709_1 = ~n4499_1; - assign n4501 = n7858 & (~Ng4375 | (Pg35 & ~Ng4382)); - assign n1714 = ~n4501; - assign n4503 = n6178 & (Pg35 | ~Ng2844); - assign n1722_1 = ~n4503; - assign n4505 = (n7758 | ~Ng417) & (n8027 | ~Ng446); - assign n1727_1 = ~n4505; - assign n4507 = n7044 & n7045 & (n4205 | n7046); - assign n1747_1 = ~n4507; - assign n4509 = n7951 & (Pg35 | ~Ng3490); - assign n1757_1 = ~n4509; - assign n1762_1 = ~n6687 & ~Ng5511; - assign n4512 = (n6728 | n6729) & (Pg35 | ~Ng3512); - assign n1767_1 = ~n4512; - assign n4514_1 = n6467_1 & (Pg35 | ~Ng1687); - assign n1772 = ~n4514_1; - assign n4516 = n7495 & n7761 & (Pg35 | ~Ng5965); - assign n1782_1 = ~n4516; - assign n4518 = n7855 & n7856 & n7857; - assign n1787_1 = ~n4518; - assign n4520 = Ng518 & Ng203 & ~Ng513; - assign n4521 = Ng182 & (Ng168 | Ng174); - assign n4522 = Ng168 & Ng174; - assign n1797 = Pg35 & n4520 & (n4521 | n4522); - assign n4524_1 = n7171 & (Pg35 | ~Ng3961); - assign n1802 = ~n4524_1; - assign n4526 = (n7790 | ~n9147) & (n7791 | ~Ng4749); - assign n1807_1 = ~n4526; - assign n4528 = n6411 & (Pg35 | ~Ng2089); - assign n1812_1 = ~n4528; - assign n4530 = n7198 & n7199 & (n4205 | n7200); - assign n1821_1 = ~n4530; - assign n4532 = Ng1052 ^ n7888; - assign n1836_1 = Pg35 & n4532 & ~Ng979; - assign n4534_1 = n6562 & n6563 & (n6359_1 | ~Ng2465); - assign n1849_1 = ~n4534_1; - assign n4536 = n7050 & n7051 & (n4205 | n7052); - assign n1854 = ~n4536; - assign n4538 = ~n5990_1 & n6708 & (~n6860 | ~Ng4480); - assign n1859_1 = ~n4538; - assign n1864_1 = ~Ng358 & Pg35 & ~Pg8719; - assign n4541 = (Pg35 | ~Ng3171) & (n6735 | n6736); - assign n1873_1 = ~n4541; - assign n4543 = n6620_1 & (n6452_1 | ~Ng1728); - assign n1878_1 = ~n4543; - assign n4545 = n6356 & (Pg35 | ~Ng2514); - assign n1883_1 = ~n4545; - assign n4547 = n7569 & (Pg35 | ~Ng3831); - assign n1888_1 = ~n4547; - assign n4549_1 = ~Pg35 | ~Ng4917; - assign n1898_1 = ~n4549_1; - assign n4551 = (Pg35 | ~Ng1199) & (n4474 | ~n8747); - assign n1903_1 = ~n4551; - assign n4553 = (n7903 | n7904) & (Pg35 | ~Ng832); - assign n1908_1 = ~n4553; - assign n4555 = n7392 & n7393 & (Ng914 | n7394); - assign n1916_1 = ~n4555; - assign n4557 = n6638_1 & ~n9361 & (Ng1008 | n7385); - assign n4558 = ~n6638_1 | n8083; - assign n1930_1 = Pg35 & (n4557 | (Ng969 & n4558)); - assign n4560 = n6231 & (n6228 | n6230_1 | n6232); - assign n1935_1 = ~n4560; - assign n4562 = n6527 & n6528 & (n6529 | ~Ng4054); - assign n1940_1 = ~n4562; - assign n4564 = n7922 & (Pg35 | ~Ng6187); - assign n1945_1 = ~n4564; - assign n1950_1 = Ng5073 & (~Pg35 | Ng5069); - assign n4567 = (n6687 | n6688) & (Pg35 | ~Ng5517); - assign n1955 = ~n4567; - assign n4569 = n6910 & n6911 & (n4205 | n6912); - assign n1964 = ~n4569; - assign n4571 = n6469 & (n6470 | ~Ng1682); - assign n1974_1 = ~n4571; - assign n4573 = n7887 & ~n9473 & (Ng1105 | ~n8488); - assign n1988 = ~n4573; - assign n4575 = n6954 & n6955 & (n4205 | n6956); - assign n1998_1 = ~n4575; - assign n4577 = n7355 & ~n9261 & (Pg35 | ~Ng2250); - assign n2012_1 = ~n4577; - assign n4579 = n6234 & (n6228 | n6233 | n6235_1); - assign n2017_1 = ~n4579; - assign n4581 = n7736 & n7737 & (Ng911 | ~n8341); - assign n2022_1 = ~n4581; - assign n4583 = n6457_1 & n6458 & (~n5998_1 | n6459); - assign n2035 = ~n4583; - assign n4585 = n7058 & n7059 & (n4205 | n7060); - assign n2040 = ~n4585; - assign n4587 = n7267 & n7268 & (n4205 | n7269); - assign n2045 = ~n4587; - assign n4589 = n7928 & (Pg35 | ~Ng5495); - assign n2050 = ~n4589; - assign n4591 = n6167 & (Pg35 | ~Ng2950); - assign n2055_1 = ~n4591; - assign n4593 = n7216 & n7217 & (n4205 | n7218); - assign n2060 = ~n4593; - assign n4595 = n6949 & n6950 & (n4205 | n6663); - assign n2070 = ~n4595; - assign n4597 = n6825 & n6826 & (Pg35 | ~Ng1367); - assign n2078_1 = ~n4597; - assign n4599 = n6493 & n6494 & (Pg35 | ~Ng153); - assign n2087 = ~n4599; - assign n4601 = n6245_1 & (n6241 | n6244 | n6235_1); - assign n2092 = ~n4601; - assign n4603 = n7258 & n7259 & (n4205 | n7260); - assign n2101_1 = ~n4603; - assign n4605 = n6592 & (Pg35 | ~Ng2108); - assign n2106_1 = ~n4605; - assign n4607_1 = n8029 & (Pg35 | ~Ng437); - assign n2116 = ~n4607_1; - assign n4609 = n6835 & n6836 & (Ng758 | n6837); - assign n2131_1 = ~n4609; - assign n4611 = n7919 & (Pg35 | ~Ng6533); - assign n2141_1 = ~n4611; - assign n4613 = n7105 & n7106 & (n4205 | n7107); - assign n2146 = ~n4613; - assign n4615 = n7007 & ~n9456 & (n4205 | n7008); - assign n2154 = ~n4615; - assign n4617_1 = n6951 & n6952 & (n4205 | n6953); - assign n2159_1 = ~n4617_1; - assign n4619 = n6100 & n6101 & (Ng632 | n6102); - assign n2164_1 = ~n4619; - assign n4621 = n7222 & n7223 & (n4205 | n7224); - assign n2173_1 = ~n4621; - assign n4623 = n6817 & n6818 & (~Ng1664 | n6816); - assign n2183_1 = ~n4623; - assign n4625 = n8014 & (Pg35 | ~\[4421] ); - assign n2188_1 = ~n4625; - assign n4627_1 = n6915 & n6916 & (n4205 | n6917); - assign n2193 = ~n4627_1; - assign n4629 = n7896 & (Pg35 | ~Ng269); - assign n2198 = ~n4629; - assign n4631_1 = ~Ng4040 | n8507; - assign n2203_1 = Ng4045 & (~Pg35 | n4631_1); - assign n4633 = n7847 & (~Ng4438 | (Pg35 & ~Ng4382)); - assign n2208_1 = ~n4633; - assign n4635 = ~n6680 & (Pg35 | ~\[4437] ); - assign n2217_1 = ~n4635; - assign n4637 = Ng4681 | Ng4688 | Ng4674 | Ng4646; - assign n6680 = Pg35 & ~n9300 & (n4637 | ~n8761); - assign n4639 = n6521 & n6862 & (~Pg35 | n6863); - assign n2222 = ~n4639; - assign n4641 = ~n5990_1 & n6710 & (~n6860 | ~Ng4495); - assign n2227 = ~n4641; - assign n4643 = (n6220 | n6223) & (Pg35 | ~Ng4332); - assign n2252 = ~n4643; - assign n4645 = n6298 & n6299 & (Pg35 | ~Ng298); - assign n2257 = ~n4645; - assign n4647 = n7468 & ~n9285 & (~Ng5831 | n7469); - assign n2265 = ~n4647; - assign n4649 = n7898 & (Pg35 | ~Ng262); - assign n2270_1 = ~n4649; - assign n4651 = n6830 & n6831 & (Pg35 | ~Ng1024); - assign n2293_1 = ~n4651; - assign n4653 = n7307 & n7308 & (n4205 | n7309); - assign n2301_1 = ~n4653; - assign n4655 = n6394 & (n6395_1 | ~Ng2241); - assign n2318_1 = ~n4655; - assign n4657 = n8003 & n8004 & (Ng1564 | ~n8495); - assign n2323_1 = ~n4657; - assign n4659 = n6901 & n6902 & (n4205 | n6903); - assign n2336_1 = ~n4659; - assign n4661 = n7902 & (Pg35 | ~Ng872); - assign n2349_1 = ~n4661; - assign n4663 = ~n5991 & n6710 & (~n6860 | ~Ng4501); - assign n2359_1 = ~n4663; - assign n4665 = (~Ng5869 | n6676) & (~Ng5873 | n6677); - assign n2364_1 = ~n4665; - assign n4667 = n6857 & (n6855 | ~Ng5037 | ~n8723); - assign n2369_1 = ~n4667; - assign n4669 = n6773 & n6769 & n6774; - assign n2374_1 = ~n4669; - assign n4671 = n7153 & n7154 & (n4205 | n7155); - assign n2388_1 = ~n4671; - assign n4673 = n7087 & n7088 & (n4205 | n7089); - assign n2393_1 = ~n4673; - assign n4675 = (n6677 | n6678) & (Pg35 | ~Ng5863); - assign n2398_1 = ~n4675; - assign n4677 = n8005 & (Pg35 | ~Ng1585); - assign n2403_1 = ~n4677; - assign n4679 = n6973 & n6974 & (n4205 | n6975); - assign n2413 = ~n4679; - assign n4681 = n7038 & n7039 & (n4205 | n7040); - assign n2418 = ~n4681; - assign n4683 = n7923 & n7924 & (~n8386 | ~Ng6167); - assign n2428_1 = ~n4683; - assign n4685 = n6551_1 & n6552 & (n6340_1 | ~Ng2599); - assign n2436_1 = ~n4685; - assign n4687_1 = n7876 & ~n9472 & (Ng1448 | ~n8483); - assign n2441_1 = ~n4687_1; - assign n4689 = n7683 & n7684 & (~Ng2299 | ~n8421); - assign n2449_1 = ~n4689; - assign n2454_1 = ~n6697 & ~Ng5164; - assign n4692 = n6652 & n6653 & (Pg35 | ~Ng150); - assign n2463_1 = ~n4692; - assign n2468_1 = ~n6658 & ~Ng6549; - assign n4695 = (n7565 | n7566) & (Pg35 | ~Ng4076); - assign n2473_1 = ~n4695; - assign n4697 = n6329 & n6330_1 & (Pg35 | ~Ng4793); - assign n2478_1 = ~n4697; - assign n4699 = n7180 & n7181 & (n4205 | n7182); - assign n2488_1 = ~n4699; - assign n4701 = n6918 & n6919 & (n4205 | n6920); - assign n2506 = ~n4701; - assign n4703 = n7390 & n7391 & (Pg35 | ~Ng1002); - assign n2516 = ~n4703; - assign n4705 = Pg35 & ((~n5425 & ~n5965) | ~n8510); - assign n2521_1 = n4705 & ~Pg17320 & ~Pg17423 & ~Pg17404; - assign n4707 = n7346 & ~n9256 & (Pg35 | ~Ng2441); - assign n2535_1 = ~n4707; - assign n4709 = n6333 & n6743 & (~Pg35 | n6744); - assign n2540 = ~n4709; - assign n4711 = (Pg35 | ~Ng6049) & (n6509 | ~n9423); - assign n2545_1 = ~n4711; - assign n4713 = n7732 & n7733 & (Ng1256 | ~n8335); - assign n2550_1 = ~n4713; - assign n4715 = n6852 & n6853 & (n6851 | ~Ng5016); - assign n2555_1 = ~n4715; - assign n4717 = n6451 & (n6452_1 | ~Ng1816); - assign n2565_1 = ~n4717; - assign n4719 = ~n1654 & (Pg35 | ~Ng4572); - assign n2575 = ~n4719; - assign n2580_1 = Pg35 & (~Ng4462 | ~n6290 | ~Ng10384); - assign n4722 = n7570 & ~n9301 & (~Ng3831 | n7571); - assign n2585_1 = ~n4722; - assign n4724 = (Pg35 | ~Ng3352) & (n6538 | ~n9425); - assign n2595_1 = ~n4724; - assign n4726 = n6570_1 & (Pg35 | ~Ng2399); - assign n2600_1 = ~n4726; - assign n4728 = n6182 & (Pg35 | ~Ng2138); - assign n2605_1 = ~n4728; - assign n4730 = n7374 & (Pg35 | ~Ng1696); - assign n2610_1 = ~n4730; - assign n4732 = (n7983 | ~Ng513) & (n7987 | ~Ng504); - assign n2615_1 = ~n4732; - assign n4734 = (Pg35 | ~Ng5357) & (n6517_1 | ~n9422); - assign n2624_1 = ~n4734; - assign n4736 = n6333 & n6334 & (Ng2763 | n6335_1); - assign n2629_1 = ~n4736; - assign n4738 = (n6322 | n6323) & (Pg35 | ~Ng4818); - assign n2634_1 = ~n4738; - assign n4740 = n6144 & n6145; - assign n2639_1 = ~n4740; - assign n4742 = n6868 & n6869 & (Ng1263 | ~n8336); - assign n2644_1 = ~n4742; - assign n4744 = n6432_1 & (n6433 | ~Ng1950); - assign n2649_1 = ~n4744; - assign n4746_1 = n7529 & ~n9293 & (~Ng5138 | n7530); - assign n2654 = ~n4746_1; - assign n4748 = n6382 & n6383 & (~n6012_1 | n6384); - assign n2659_1 = ~n4748; - assign n4750 = (n6197 | n6198) & (Pg35 | ~Ng4659); - assign n2672_1 = ~n4750; - assign n4752 = n6777 & n6778 & (~Ng2223 | n6776); - assign n2677_1 = ~n4752; - assign n4754 = n7494 & (Ng5808 | n7495) & ~n9288; - assign n2682_1 = ~n4754; - assign n4756_1 = n6904 & n6905 & (n4205 | n6906); - assign n2687_1 = ~n4756_1; - assign n4758 = n6420 & n6421 & (~n6004 | n6422_1); - assign n2692_1 = ~n4758; - assign n4760 = (~Ng3869 | n6717) & (~Ng3873 | n6718); - assign n2697 = ~n4760; - assign n4762 = n6378 & ~n9444 & (~n6012_1 | n6379); - assign n2705_1 = ~n4762; - assign n4764 = n7864 & (Pg35 | ~Ng2799); - assign n2710_1 = ~n4764; - assign n4766_1 = n7009 & n7010 & (n4205 | n7011); - assign n2715_1 = ~n4766_1; - assign n4768 = n6589 & ~n9432 & (~Ng2047 | n6588); - assign n2720_1 = ~n4768; - assign n4770 = (n6718 | n6719) & (Pg35 | ~Ng3863); - assign n2725_1 = ~n4770; - assign n4772 = n7090 & n7091 & (n4205 | n7092); - assign n2733_1 = ~n4772; - assign n4774 = n7210 & n7211 & (n4205 | n7212); - assign n2748_1 = ~n4774; - assign n4776 = (~Pg35 | ~Ng4411) & (n7854 | ~Ng4401); - assign n2760_1 = ~n4776; - assign n4778 = n6976 & ~n9454 & (n4205 | n6977); - assign n2765_1 = ~n4778; - assign n4780 = n6945 & (Pg35 | ~Ng6307); - assign n2770 = ~n4780; - assign n4782_1 = n7970 & n7971 & (Pg35 | ~Ng1036); - assign n2778_1 = ~n4782_1; - assign n4784 = n7341 & ~n9253 & (Pg35 | ~Ng2575); - assign n2783_1 = ~n4784; - assign n4786 = n6559 & (Pg35 | ~Ng2533); - assign n2788_1 = ~n4786; - assign n4788 = (~Pg35 | ~Ng4443) & (n7845 | ~Ng4434); - assign n2798_1 = ~n4788; - assign n4790 = n7464 & n7760 & (Pg35 | ~Ng6311); - assign n2808_1 = ~n4790; - assign n4792 = n6993 & n6994 & (n4205 | n6995); - assign n2813_1 = ~n4792; - assign n4794 = n7900 & (Pg35 | ~Ng255); - assign n2818_1 = ~n4794; - assign n4796 = n7117 & n7118 & (n4205 | n7119); - assign n2823_1 = ~n4796; - assign n4798 = ~Pg35 | ~Ng6545; - assign n2828 = ~n4798; - assign n4800 = n7347 & ~n9257 & (~Ng2417 | n7348); - assign n2833_1 = ~n4800; - assign n4802_1 = n6617 & n6618 & (n6452_1 | ~Ng1772); - assign n2838_1 = ~n4802_1; - assign n4804 = n6849 & ~n9233 & (Pg35 | ~Ng5046); - assign n2843_1 = ~n4804; - assign n4806 = n6434 & n6435 & (~n6006 | n6436); - assign n2852_1 = ~n4806; - assign n4808 = (n6340_1 | ~Ng2629) & (n6550 | ~Ng2599); - assign n2857_1 = ~n4808; - assign n4810 = n7829 & n7830 & (Ng572 | n7831); - assign n2862_1 = ~n4810; - assign n4812_1 = ~Pg35 | ~Ng2130; - assign n2867_1 = ~n4812_1; - assign n4814 = n6521 & n6711 & (Ng4108 | n6712); - assign n2872_1 = ~n4814; - assign n4816 = n8028 & (Pg35 | ~Ng424); - assign n2881_1 = ~n4816; - assign n4818 = ~n3847_1 & (Pg35 | ~Ng753); - assign n2895_1 = ~n4818; - assign n4820 = (Pg35 | ~Ng4054) & (n6526_1 | ~n9419); - assign n2899_1 = ~n4820; - assign n4822_1 = (Pg35 | ~Ng5873) & (n6674 | n6675_1); - assign n2904_1 = ~n4822_1; - assign n4824 = n7362 & ~n9266 & (~Ng1992 | n7363); - assign n2909_1 = ~n4824; - assign n4826 = (~Ng3167 | n6737) & (~Ng3171 | n6738); - assign n2914_1 = ~n4826; - assign n4828 = (Pg35 | ~Ng843) & (~Ng837 | ~n8838); - assign n2919_1 = ~n4828; - assign n4830 = (~n7739 | ~n9149) & (n7977 | ~Ng817); - assign n2924_1 = ~n4830; - assign n4832 = n7004 & n7005 & (n4205 | n7006); - assign n2929_1 = ~n4832; - assign n4834 = n7916 & (n7915 | (n7917 & ~Ng26885)); - assign n2951_1 = ~n4834; - assign n4836 = n7863 & (Pg35 | ~Ng2811); - assign n2961_1 = ~n4836; - assign n4838 = n7626 & n7809 & (Pg35 | ~Ng3614); - assign n2966_1 = ~n4838; - assign n4840 = (Pg35 | ~Ng3703) & (n6532 | ~n9424); - assign n2971_1 = ~n4840; - assign n4842 = n7897 & (Pg35 | ~Ng239); - assign n2989_1 = ~n4842; - assign n4844 = n7596 & (Ng3808 | n7597) & ~n9304; - assign n3013_1 = ~n4844; - assign n4846 = Ng10384 & Ng4473; - assign n3018_1 = Ng4462 | ~n6290 | ~Pg35 | n4846; - assign n4848 = n7183 & n7184 & (n4205 | n7185); - assign n3023_1 = ~n4848; - assign n4850 = n7169 & n7170 & (Pg35 | ~Ng4087); - assign n3028_1 = ~n4850; - assign n4852 = n6813 & n6809 & n6814; - assign n3033_1 = ~n4852; - assign n4854 = (~Pg17760 & (~Pg14779 | Pg12422)) | (Pg14779 & Pg12422); - assign n3038_1 = n4854 & ~Pg13085 & ~Pg17649 & Pg35 & ~Pg17685; - assign n4856 = n6301 & n6302_1 & (Pg35 | ~Ng157); - assign n3042_1 = ~n4856; - assign n4858 = n7598 & (n4205 | (Ng3498 & n7599)); - assign n3052 = ~n4858; - assign n4860 = n7752 & n7753 & (Ng586 | n7754); - assign n3057 = ~n4860; - assign n4862 = n6749 & n6750 & (n6745 | ~Ng2619); - assign n3065_1 = ~n4862; - assign n4864 = n7388 & (Ng1183 | n7389); - assign n3070 = ~n4864; - assign n4866 = n6480 & n6481 & (~n6010 | n6482_1); - assign n3075 = ~n4866; - assign n4868 = n6611 & ~n9434 & (~Ng1779 | n6610_1); - assign n3086_1 = ~n4868; - assign n4870 = ~n7660 & (~Pg35 | n7658 | ~Ng2652); - assign n3091 = ~n4870; - assign n4872 = n7356 & ~n9262 & (Pg35 | ~Ng2173); - assign n3096_1 = ~n4872; - assign n4874 = n7349 & (Pg35 | ~Ng2389); - assign n3101_1 = ~n4874; - assign n4876 = n7772 & (~Pg35 | n7771 | n7773); - assign n3111 = ~n4876; - assign n4878 = (Pg35 | ~Ng5527) & (n6684 | n6685); - assign n3116_1 = ~n4878; - assign n4880 = n7333 & (Pg35 | ~Ng2803); - assign n3121 = ~n4880; - assign n4882_1 = n7380 & n7381 & (Pg35 | ~Ng1345); - assign n3126 = ~n4882_1; - assign n4884 = n6996 & n6997 & (n4205 | n6998); - assign n3131_1 = ~n4884; - assign n4886 = Ng1146 & (~n4887 | ~Ng1152); - assign n4887 = ~Ng1183 & Pg13259 & ~Ng1171; - assign n3136 = Pg35 & (n4886 | (n4887 & ~Ng1099)); - assign n4889 = n6747 & n6748 & (~Ng2625 | n6746); - assign n3141_1 = ~n4889; - assign n4891 = n6842 & n6843 & (Pg35 | ~Ng164); - assign n3146 = ~n4891; - assign n4893 = n7375 & ~n9273 & (Pg35 | ~Ng1691); - assign n3151_1 = ~n4893; - assign n4895 = (n6656_1 | n6662) & (Pg35 | ~Ng6549); - assign n3156_1 = ~n4895; - assign n3161 = \[4431] & Pg35; - assign n4898 = (Pg35 | ~Ng3873) & (n6715 | n6716); - assign n3165 = ~n4898; - assign n4900 = n6921 & n6922 & (n4205 | n6923); - assign n3170_1 = ~n4900; - assign n4902 = n7952 & n7953 & (~n8405 | ~Ng3470); - assign n3175_1 = ~n4902; - assign n4904_1 = n7177 & n7178 & (n4205 | n7179); - assign n3180_1 = ~n4904_1; - assign n4906 = (n7983 | ~Ng518) & (n7987 | ~Ng513); - assign n3185_1 = ~n4906; - assign n4908 = Ng538 | Ng209; - assign n4909 = n6068 & n6065 & n6066 & n6067; - assign n3190 = n4908 & Pg35; - assign n4911 = n6545 & ~n9428 & (~Ng2606 | n6544); - assign n3195 = ~n4911; - assign n4913 = n7874 & n7875 & (Ng1472 | ~n8482); - assign n3200 = ~n4913; - assign n4915 = (n7743 | n8026) & (Pg35 | ~Ng546); - assign n3205 = ~n4915; - assign n4917 = (Pg35 | ~Ng5180) & (n6694 | n6695); - assign n3210_1 = ~n4917; - assign n4919 = n7150 & n7151 & (n4205 | n7152); - assign n3228 = ~n4919; - assign n4921 = n6195 & (n6196_1 | ~Ng4664 | ~n8230); - assign n3237 = ~n4921; - assign n4923 = n8014 & (Pg35 | ~Ng1236); - assign n3242_1 = ~n4923; - assign n4925 = (Pg35 | ~\[4507] ) & (n7994 | n7995); - assign n3247_1 = ~n4925; - assign n4927 = n6177 & (Pg35 | ~Ng2852); - assign n3252 = ~n4927; - assign n4929 = n6285 & n6286 & (n6287 | n6284_1); - assign n3257_1 = ~n4929; - assign n4931 = n6936 & n6937 & (n4205 | n6938); - assign n3262_1 = ~n4931; - assign n4933 = (Pg35 | ~Ng1542) & (n5559 | ~n8744); - assign n3275_1 = ~n4933; - assign n4935 = n6907 & n6908 & (n4205 | n6909); - assign n3286_1 = ~n4935; - assign n4937 = (n6433 | ~Ng1936) & (n6605_1 | ~Ng1906); - assign n3291_1 = ~n4937; - assign n4939_1 = n7988 & (n7986 | n7755); - assign n3301 = ~n4939_1; - assign n4941 = n6753 & n6749 & n6754; - assign n3306_1 = ~n4941; - assign n4943 = n6710 & n6861 & (Pg35 | ~Ng4477); - assign n3311 = ~n4943; - assign n4945 = n6380_1 & n6381 & (~n6012_1 | ~n8279); - assign n3316_1 = ~n4945; - assign n4947 = n7240 & ~n9466 & (n4205 | n7241); - assign n3321 = ~n4947; - assign n4949 = n7093 & n7094 & (n4205 | n7095); - assign n3326_1 = ~n4949; - assign n4951 = n7256 & ~n9468 & (n4205 | n7257); - assign n3331_1 = ~n4951; - assign n4953 = n7253 & n7254 & (n4205 | n7255); - assign n3345 = ~n4953; - assign n4955 = n6978 & n6979 & (n4205 | n6980); - assign n3350_1 = ~n4955; - assign n3355_1 = Ng4681 & n4365; - assign n4958 = n7159 & n7160 & (n4205 | n7161); - assign n3365_1 = ~n4958; - assign n4960 = n7310 & ~n9471 & (n4205 | n7311); - assign n3370_1 = ~n4960; - assign n4962 = n6418 & n6419 & (~n6004 | ~n8295); - assign n3375 = ~n4962; - assign n4964 = n7403 & (n4205 | (Ng6541 & n7404)); - assign n3386_1 = ~n4964; - assign n4966 = n7283 & n7284 & (n4205 | n6733); - assign n3391_1 = ~n4966; - assign n4968 = n6626 & (Pg35 | ~Ng1636); - assign n3396_1 = ~n4968; - assign n4970 = n7788 & (~Pg35 | n7787 | n7789); - assign n3401_1 = ~n4970; - assign n4972 = n7899 & (Pg35 | ~Ng232); - assign n3406_1 = ~n4972; - assign n4974 = n7989 & (Pg35 | ~Ng168); - assign n3421_1 = ~n4974; - assign n4976 = (n6666 | n6672) & (Pg35 | ~Ng6203); - assign n3426_1 = ~n4976; - assign n4978_1 = (n7910 | n7911) & (Pg35 | ~Ng355); - assign n3431_1 = ~n4978_1; - assign n4980 = ~Pg35 | ~Ng3502; - assign n3444_1 = ~n4980; - assign n4982 = n6578 & ~n9431 & (~Ng2204 | n6577); - assign n3449 = ~n4982; - assign n4984 = n7125 & n7126 & (n4205 | n7127); - assign n3454 = ~n4984; - assign n4986 = n6217 & n6218 & (Pg35 | ~Ng4601); - assign n3459_1 = ~n4986; - assign n4988 = n6112 & n6113 & (Ng794 | n6114); - assign n3464_1 = ~n4988; - assign n4990 = n8025 & (~Ng703 | n8024); - assign n3485_1 = ~n4990; - assign n4992_1 = n7297 & n7298 & (n4205 | n7299); - assign n3495_1 = ~n4992_1; - assign n4994 = n6595_1 & n6596 & (n6414 | ~Ng2040); - assign n3500_1 = ~n4994; - assign n4996 = n6164 & (Pg35 | ~Ng4176); - assign n3505 = ~n4996; - assign n4998 = (~Ng4633 | n6207) & (~Ng4628 | n6209); - assign n3510_1 = ~n4998; - assign n5000 = n6159 & (Pg35 | ~Ng4727); - assign n3519_1 = ~n5000; - assign n5002_1 = n7470 & ~n9286 & (~n6884 | ~n8444); - assign n3528_1 = ~n5002_1; - assign n5004 = n6769 & n6770 & (n6765 | ~Ng2351); - assign n3533 = ~n5004; - assign n5006 = ~Ng6727 | ~n8502; - assign n3543 = Ng6732 & (~Pg35 | n5006); - assign n5008 = (n6521 | n7943) & (Pg35 | ~Ng4125); - assign n3553 = ~n5008; - assign n5010 = n7603 & ~n9306 & (~n8105 | ~n8453); - assign n3566_1 = ~n5010; - assign n5012 = n7804 & n7805 & (n7801 | ~n8473); - assign n3571_1 = ~n5012; - assign n5014 = n6856 & (n6855 | ~Ng5041 | ~n8379); - assign n3576 = ~n5014; - assign n5016_1 = ~Ng4452 & (n7844 | n7846 | ~Ng4430); - assign n3581_1 = ~n5016_1; - assign n5018 = n7432 & (Ng6500 | n7433) & ~n9280; - assign n3591_1 = ~n5018; - assign n5020 = n7629 & (Pg35 | ~Ng3129); - assign n3599 = ~n5020; - assign n5022 = n7810 & (Pg35 | ~Ng3263); - assign n3604 = ~n5022; - assign n3613_1 = Ng4674 & n4365; - assign n5025 = n6491 & n6492_1 & (Pg35 | ~Ng294); - assign n3618_1 = ~n5025; - assign n5027 = n6803 & n6799 & n6804; - assign n3631 = ~n5027; - assign n5029 = n6165_1 & (Pg35 | ~Ng2994); - assign n3636_1 = ~n5029; - assign n5031 = n7276 & n7277 & (n4205 | n7278); - assign n3641 = ~n5031; - assign n3646_1 = Ng160 & (~Pg35 | ~n9218); - assign n5034 = n7823 & n7824 & (Pg35 | ~Ng822); - assign n3656_1 = ~n5034; - assign n5036_1 = ~Ng1008 & ~Ng969 & ~n4558; - assign n3661 = Pg35 & ~n9151 & (n5036_1 | ~n8511); - assign n5038 = n6554 & (n6340_1 | ~Ng2555); - assign n3665_1 = ~n5038; - assign n5040 = n7433 & n7759 & (Pg35 | ~Ng6657); - assign n3670_1 = ~n5040; - assign n5042 = n7406 & ~n9277 & (~Ng6523 | n7407); - assign n3680_1 = ~n5042; - assign n5044 = n7378 & (Ng1526 | n7379); - assign n3685_1 = ~n5044; - assign n5046 = (n6219 | n6220) & (Pg35 | ~Ng4593); - assign n3690_1 = ~n5046; - assign n5048 = ~n5049 | Ng854; - assign n5049 = ~Pg8719 | Ng385 | ~Ng376 | ~Ng370; - assign n5050 = n6250_1 | ~n9329; - assign n3695 = n5048 & Pg35 & (n5049 | n5050); - assign n5052 = n7730 & (n7731 | ~Ng1484); - assign n3700 = ~n5052; - assign n5054 = n6155 & (Pg35 | ~Ng4917); - assign n3705 = ~n5054; - assign n3710_1 = Ng5077 & (~Pg35 | ~n8914); - assign n5057 = (n6675_1 | n6681) & (Pg35 | ~Ng5857); - assign n3715_1 = ~n5057; - assign n5059 = ~n7669 & (~Pg35 | n7667 | ~Ng2518); - assign n3725 = ~n5059; - assign n5061 = n6337 & (Pg35 | ~Ng2648); - assign n3730 = ~n5061; - assign n5063 = n7907 & n7908 & (Ng568 | n7909); - assign n3735 = ~n5063; - assign n5065 = n7279 & (Pg35 | ~Ng3259); - assign n3740 = ~n5065; - assign n5067 = n6927 & n6928 & (n4205 | n6929); - assign n3745 = ~n5067; - assign n5069_1 = ~Ng6035 | ~n8504; - assign n3750_1 = Ng6040 & (~Pg35 | n5069_1); - assign n3765_1 = ~n6677 & ~Ng5857; - assign n5072 = n6474 & n6475 & (~n6010 | n6476); - assign n3770_1 = ~n5072; - assign n5074 = n7226 & n7227 & (n4205 | n7228); - assign n3783_1 = ~n5074; - assign n5076 = n7572 & ~n9302 & (~n6889 | ~n8451); - assign n3797_1 = ~n5076; - assign n5078 = ~n5991 & n6708 & (~n6860 | ~Ng4498); - assign n3807_1 = ~n5078; - assign n5080 = n7870 & n7871 & (Pg35 | ~Ng2719); - assign n3817_1 = ~n5080; - assign n5082 = n7795 & (~Pg35 | n7794 | n7796); - assign n3822_1 = ~n5082; - assign n5084 = n7109 & n7110 & (n4205 | n7111); - assign n3837_1 = ~n5084; - assign n5086 = n6149 & n6150 & (Ng617 | n6151); - assign n3842_1 = ~n5086; - assign n5088 = n7915 & (Pg35 | ~Ng324); - assign n3851_1 = ~n5088; - assign n5090 = Ng1270 & ~n6829; - assign n5091 = ~n5965 | ~Ng1536; - assign n3856 = Ng1274 & (~Pg35 | (n5090 & n5091)); - assign n5093 = n7920 & n7921 & (~n8381 | ~Ng6513); - assign n3861_1 = ~n5093; - assign n5095 = n7913 & n7914 & (n7915 | ~Ng305); - assign n3866_1 = ~n5095; - assign n5097 = Ng925 & ~n6834; - assign n3876_1 = Ng930 & (~Pg35 | (n5097 & ~n6128)); - assign n5099 = n6606 & n6607 & (n6433 | ~Ng1906); - assign n3881_1 = ~n5099; - assign n3886 = Pg6745 & Pg35; - assign n5102 = n7865 & (Pg35 | ~\[4428] ); - assign n3896 = ~n5102; - assign n5104 = n6153 & (Pg35 | ~Ng4907); - assign n3907_1 = ~n5104; - assign n5106 = n6163 & (Pg35 | ~Ng4146); - assign n3912 = ~n5106; - assign n5108 = n6557 & n6558 & (~n8269 | ~Ng2541); - assign n3917 = ~n5108; - assign n5110 = n6587 & (n6395_1 | ~Ng2153); - assign n3922 = ~n5110; - assign n5112 = n7901 & (Pg35 | ~Ng225); - assign n3932 = ~n5112; - assign n5114 = n7710 & n7711 & (~Ng1874 | ~n8431); - assign n3937_1 = ~n5114; - assign n5116_1 = n7135 & n7136 & (n4205 | n7137); - assign n3942_1 = ~n5116_1; - assign n5118 = n7872 & n7873 & (Ng1478 | ~n8481); - assign n3947 = ~n5118; - assign n5120 = (n6716 | n6722) & (Pg35 | ~Ng3857); - assign n3952_1 = ~n5120; - assign n5122 = ~n7705 & (~Pg35 | n7704 | ~Ng1959); - assign n3957_1 = ~n5122; - assign n5124 = n7601 & ~n9305 & (~Ng3480 | n7602); - assign n3962 = ~n5124; - assign n5126_1 = n6899 & ~n9450 & (n4205 | n6900); - assign n3967_1 = ~n5126_1; - assign n5128 = n7779 & (~Pg35 | n6125 | n7778); - assign n3980_1 = ~n5128; - assign n3988 = ~n6718 & ~Ng3857; - assign n5131_1 = Ng499 & (n7986 | ~Ng513); - assign n5132 = ~n7986 & (~Ng518 | ~n8468); - assign n3996_1 = Pg35 & (n5131_1 | n5132); - assign n5134 = n7818 & (~n6638_1 | Ng1002 | n7819); - assign n4001 = ~n5134; - assign n5136 = n6255_1 & n6256 & (Ng776 | n6257); - assign n4006 = ~n5136; - assign n4015 = ~n6198 & ~Ng4674 & ~Ng4646 & ~Ng4681; - assign n5139 = n6819 & n6820 & (n6815 | ~Ng1657); - assign n4025_1 = ~n5139; - assign n5141_1 = n6376_1 & (n6377 | ~Ng2375); - assign n4030 = ~n5141_1; - assign n5143 = (Pg35 | ~Ng278) & (Ng283 | n7834); - assign n4052_1 = ~n5143; - assign n5145 = (n6736 | n6742) & (Pg35 | ~Ng3155); - assign n4057 = ~n5145; - assign n5147 = ~n7678 & (~Pg35 | n7677 | ~Ng2384); - assign n4062 = ~n5147; - assign n5149 = n6213 & (~n6212 | n6214 | ~Ng4608); - assign n4070_1 = ~n5149; - assign n5151 = n6415 & n6416 & (~n6004 | n6417_1); - assign n4080 = ~n5151; - assign n5153 = n7866 & (Pg35 | ~Ng2791); - assign n4089_1 = ~n5153; - assign n5155 = n6187 & n6188 & (Ng613 | n6189); - assign n4094_1 = ~n5155; - assign n5157 = n6614 & (Pg35 | ~Ng1840); - assign n4104 = ~n5157; - assign n5159 = n7023 & n7024 & (n4205 | n7025); - assign n4109 = ~n5159; - assign n5161 = ~n5991 & ~n5993 & (~n6860 | ~Ng4567); - assign n4114_1 = ~n5161; - assign n5163 = n7345 & ~n9255 & (Pg35 | ~Ng2518); - assign n4119 = ~n5163; - assign n5165 = (~Pg16718 & (~Pg13895 | Pg11349)) | (Pg13895 & Pg11349); - assign n4124 = n5165 & ~Pg14421 & ~Pg16603 & Pg35 & ~Pg16624; - assign n5167 = n6339 & (n6340_1 | ~Ng2643); - assign n4128 = ~n5167; - assign n5169 = Ng1489 & (~n5170 | ~Ng1495); - assign n5170 = ~Ng1514 & Pg13272 & ~Ng1526; - assign n4133_1 = Pg35 & (n5169 | (n5170 & ~Ng1442)); - assign n5172 = n7342 & ~n9254 & (~Ng2551 | n7343); - assign n4142_1 = ~n5172; - assign n5174 = n7526 & (n4205 | (Ng5156 & n7527)); - assign n4147 = ~n5174; - assign n5176 = n6510 & n6511 & (n6512_1 | ~Ng6049); - assign n4169_1 = ~n5176; - assign n5178 = n6579 & n6580_1 & (~n8283 | ~Ng2273); - assign n4174 = ~n5178; - assign n5180 = n7783 & (~Pg35 | n7782 | n7784); - assign n4182_1 = ~n5180; - assign n5182 = n7627 & (n4205 | (Ng3147 & n7628)); - assign n4192_1 = ~n5182; - assign n5184 = ~Ng3338 | n8509; - assign n4197 = Ng3343 & (~Pg35 | n5184); - assign n5186 = n6581 & (Pg35 | ~Ng2265); - assign n4202_1 = ~n5186; - assign n5188 = n6115 & n6116 & (Ng626 | n6117); - assign n4216 = ~n5188; - assign n5190 = n6333 & n7811 & (~Pg35 | n7812); - assign n4221_1 = ~n5190; - assign n5192 = n6518 & n6519 & (n6520 | ~Ng5357); - assign n4226_1 = ~n5192; - assign n5194 = n6318 & n6319 & (Pg35 | ~Ng4983); - assign n4231_1 = ~n5194; - assign n5196 = n6325 & (Pg35 | ~Ng4785); - assign n4239_1 = ~n5196; - assign n5198 = n7029 & n7030 & (n4205 | n7031); - assign n4254 = ~n5198; - assign n5200 = n6154 & (Pg35 | ~Ng4922); - assign n4259_1 = ~n5200; - assign n5202 = n7597 & n7808 & (Pg35 | ~Ng3965); - assign n4267_1 = ~n5202; - assign n5204 = n6872 & n6873 & (Ng918 | ~n8342); - assign n4277_1 = ~n5204; - assign n5206 = n6521 & n7860 & (~Pg35 | n7861); - assign n4282 = ~n5206; - assign n5208 = n7361 & ~n9265 & (Pg35 | ~Ng2016); - assign n4291_1 = ~n5208; - assign n5210 = n7398 & n7399 & (Ng577 | n7400); - assign n4296_1 = ~n5210; - assign n5212 = n6471 & n6472_1 & (~n6010 | n6473); - assign n4301_1 = ~n5212; - assign n5214 = n7334 & (Pg35 | ~Ng2771); - assign n4306 = ~n5214; - assign n5216 = n6643 & n6644 & (Ng930 | ~n5097); - assign n4316_1 = ~n5216; - assign n5218 = n7195 & n7196 & (n4205 | n7197); - assign n4321_1 = ~n5218; - assign n5220 = (Pg35 | ~Ng812) & (~n7739 | ~n8961); - assign n4326_1 = ~n5220; - assign n5222 = ~n8023 & (~Ng837 | (n7758 & ~n8021)); - assign n4336_1 = ~n5222; - assign n5224 = n6489 & (Ng599 | n6490) & ~n9446; - assign n4344_1 = ~n5224; - assign n5226 = n7929 & n7930 & (~n8394 | ~Ng5475); - assign n4349_1 = ~n5226; - assign n5228 = (n7742 | n7743) & (Pg35 | ~Ng736); - assign n4354_1 = ~n5228; - assign n5230 = n7015 & n7016 & (n4205 | n7017); - assign n4359_1 = ~n5230; - assign n5232 = (Pg35 | ~Ng6741) & (n6497_1 | ~n9420); - assign n4364_1 = ~n5232; - assign n5234 = n6174 & (Pg35 | ~Ng2868); - assign n4374_1 = ~n5234; - assign n5236 = n7940 & ~n9350 & (n7941 | ~Ng5080); - assign n4384_1 = ~n5236; - assign n5238 = n7070 & n7071 & (n4205 | n7072); - assign n4389_1 = ~n5238; - assign n5240 = (n6359_1 | ~Ng2495) & (n6561 | ~Ng2465); - assign n4397_1 = ~n5240; - assign n5242 = n6367 & n6368 & (~n6002 | n6369_1); - assign n4402_1 = ~n5242; - assign n5244 = n7359 & (Pg35 | ~Ng2098); - assign n4407_1 = ~n5244; - assign n5246 = n6344 & n6345 & (~n6000 | ~n8265); - assign n4417_1 = ~n5246; - assign n5248 = n6314 & (Pg35 | ~Ng4975); - assign n4427_1 = ~n5248; - assign n5250 = n6331 & n6332 & (n6323 | ~Ng4785); - assign n4437 = ~n5250; - assign n5252 = n7084 & n7085 & (n4205 | n7086); - assign n4442_1 = ~n5252; - assign n5254 = n6184 & n6185 & (Ng781 | n6186); - assign n4447 = ~n5254; - assign n5256 = n7981 & n7982 & (n7983 | ~Ng686); - assign n4465_1 = ~n5256; - assign n5258 = n7815 & n7816 & (Ng1252 | n7817); - assign n4470 = ~n5258; - assign n5260 = (n7750 | n7751) & (Pg35 | ~Ng667); - assign n4475 = ~n5260; - assign n5262 = n6971 & ~n9453 & (n4205 | n6972); - assign n4485 = ~n5262; - assign n5264 = (~Ng5523 | n6686) & (~Ng5527 | n6687); - assign n4499 = ~n5264; - assign n5266 = n6827 & n6828 & (Ng1270 | n6829); - assign n4514 = ~n5266; - assign n5268 = n6315_1 & (n6316 | n6317 | ~Ng4991); - assign n4519 = ~n5268; - assign n5270 = (Pg35 | ~Ng6219) & (n6665_1 | n6666); - assign n4524 = ~n5270; - assign n5272 = n7201 & n7202 & (n4205 | n7203); - assign n4529 = ~n5272; - assign n5274 = n7496 & (n4205 | (Ng5503 & n7497)); - assign n4534 = ~n5274; - assign n5276 = n7032 & n7033 & (n4205 | n7034); - assign n4544_1 = ~n5276; - assign n5278 = n7147 & n7148 & (n4205 | n7149); - assign n4559_1 = ~n5278; - assign n5280 = n6423 & n6424 & (~n6004 | n6425); - assign n4564_1 = ~n5280; - assign n4569_1 = ~n6668 & ~Ng6203; - assign n5283 = n7350 & ~n9258 & (Pg35 | ~Ng2384); - assign n4582_1 = ~n5283; - assign n5285 = n6370 & n6371 & (~n6002 | n6372); - assign n4592 = ~n5285; - assign n5287 = n6240_1 & (n6241 | n6239 | n6229); - assign n4597_1 = ~n5287; - assign n5289 = n6138 & n6139; - assign n4602 = ~n5289; - assign n5291 = n6546_1 & n6547 & (~n8262 | ~Ng2675); - assign n4607 = ~n5291; - assign n5293 = n7996 & (Pg35 | ~Ng4358); - assign n4612 = ~n5293; - assign n4617 = ~n6193 & ~Ng4864 & ~Ng4871 & ~Ng4836; - assign n5296 = n7102 & n7103 & (n4205 | n7104); - assign n4631 = ~n5296; - assign n5298_1 = n6183_1 & (Pg35 | ~Ng2130); - assign n4636 = ~n5298_1; - assign n5300 = n6567 & ~n9430 & (~Ng2338 | n6566); - assign n4644 = ~n5300; - assign n5302 = n6990 & n6991 & (n4205 | n6992); - assign n4652_1 = ~n5302; - assign n5304 = n7867 & (Pg35 | ~Ng2779); - assign n4657_1 = ~n5304; - assign n5306 = n7188 & n7189 & (n4205 | n7190); - assign n4662 = ~n5306; - assign n5308 = n7018 & n7019 & (n4205 | n7020); - assign n4672_1 = ~n5308; - assign n5310 = n7132 & n7133 & (n4205 | n7134); - assign n4677_1 = ~n5310; - assign n5312 = n6333 & n6541_1 & (Ng2759 | n6542); - assign n4682 = ~n5312; - assign n5314 = n6498 & n6499 & (n6500 | ~Ng6741); - assign n4687 = ~n5314; - assign n5316 = n6146 & n6147_1 & (Ng785 | n6148); - assign n4692_1 = ~n5316; - assign n5318_1 = n7382 & n7383 & (Ng1259 | n7384); - assign n4697_1 = ~n5318_1; - assign n5320 = n7600 & (Pg35 | ~Ng3480); - assign n4702_1 = ~n5320; - assign n5322_1 = n6930 & n6931 & (n4205 | n6932); - assign n4712_1 = ~n5322_1; - assign n5324 = (n6685 | n6691) & (Pg35 | ~Ng5511); - assign n4717_1 = ~n5324; - assign n5326 = n6360 & ~n9443 & (~n6002 | n6361); - assign n4722_1 = ~n5326; - assign n5328 = n6346 & n6347 & (~n6000 | n6348); - assign n4727_1 = ~n5328; - assign n5330 = n7892 & n7893 & (Pg35 | ~Ng921); - assign n4741_1 = ~n5330; - assign n5332 = n7360 & ~n9264 & (Pg35 | ~Ng2093); - assign n4746 = ~n5332; - assign n5334 = (~Pg35 | n6290) & (~Ng4473 | n6292); - assign n4751_1 = ~n5334; - assign n5336 = n6296 & (Ng604 | n6297_1) & ~n9442; - assign n4756 = ~n5336; - assign n5338 = n6896 & n6897 & (n4205 | n6898); - assign n4761_1 = ~n5338; - assign n5340 = n6437_1 & n6438 & (~n6006 | ~n8302); - assign n4766 = ~n5340; - assign n5342 = n6445 & n6446 & (~n6006 | n6447_1); - assign n4782 = ~n5342; - assign n5344 = n6161 & (Pg35 | ~Ng4253); - assign n4787_1 = ~n5344; - assign n5346 = ~n7714 & (~Pg35 | n7712 | ~Ng1825); - assign n4792_1 = ~n5346; - assign n5348 = ~n7973 & (~Ng969 | (Pg35 & n4558)); - assign n4797 = ~n5348; - assign n5350 = n7843 & (Pg35 | ~Ng4417); - assign n4802 = ~n5350; - assign n5352 = n7231 & n7232 & (n4205 | n7233); - assign n4807_1 = ~n5352; - assign n5354 = n7138 & n7139 & (n4205 | n7140); - assign n4812 = ~n5354; - assign n5356 = n7371 & ~n9271 & (Pg35 | ~Ng1748); - assign n4817 = ~n5356; - assign n5358 = (n6192_1 | n6193) & (Pg35 | ~Ng4849); - assign n4822 = ~n5358; - assign n5360 = n7204 & n7205 & (n4205 | n7206); - assign n4827 = ~n5360; - assign n5362 = n7408 & ~n9278 & (~n8213 | ~n8440); - assign n4832_1 = ~n5362; - assign n4837_1 = Pg35 & ~n8535; - assign n5365 = n7674 & n7675 & (~Ng2433 | ~n8418); - assign n4842_1 = ~n5365; - assign n5367 = n6783 & n6779 & n6784; - assign n4859_1 = ~n5367; - assign n4864_1 = ~n6175; - assign n5370 = (n6414 | ~Ng2070) & (n6594 | ~Ng2040); - assign n4873_1 = ~n5370; - assign n5372 = (~Pg16775 & (~Pg13966 | Pg11418)) | (Pg13966 & Pg11418); - assign n4887_1 = n5372 & ~Pg14518 & ~Pg16659 & Pg35 & ~Pg16693; - assign n5374 = n7436 & (Pg35 | ~Ng6177); - assign n4899 = ~n5374; - assign n5376 = n7096 & n7097 & (n4205 | n7098); - assign n4914_1 = ~n5376; - assign n5378 = Ng1395 ^ n7877; - assign n4919_1 = Pg35 & n5378 & ~Ng1322; - assign n5380 = n6600_1 & ~n9433 & (~Ng1913 | n6599); - assign n4924_1 = ~n5380; - assign n5382 = n6573 & n6574 & (n6377 | ~Ng2331); - assign n4929_1 = ~n5382; - assign n5384 = n6984 & n6985 & (n4205 | n6986); - assign n4934_1 = ~n5384; - assign n5386 = n7191 & ~n9464 & (n4205 | n7192); - assign n4944 = ~n5386; - assign n5388 = (~Ng1266 | n7967) & (n7966 | ~Ng1249); - assign n4958_1 = ~n5388; - assign n5390 = n7498 & (Pg35 | ~Ng5485); - assign n4963_1 = ~n5390; - assign n5392 = n7746 & n7747 & (Pg35 | ~Ng676); - assign n4968_1 = ~n5392; - assign n5394 = n6864 & n6865 & (Pg35 | ~Ng2741); - assign n4973 = ~n5394; - assign n5396 = n7501 & ~n9290 & (~n8100 | ~n8446); - assign n4978 = ~n5396; - assign n5398 = n6706 & n6861 & (Pg35 | ~Ng4423); - assign n4983_1 = ~n5398; - assign n5400 = n6892 & n6893 & (n4205 | n6894); - assign n4992 = ~n5400; - assign n5402 = n6362 & n6363 & (~n6002 | ~n8272); - assign n4997 = ~n5402; - assign n5404 = n6401 & n6402 & (~n6008_1 | n6403_1); - assign n5002 = ~n5404; - assign n5406 = n6757 & n6758 & (~Ng2491 | n6756); - assign n5011_1 = ~n5406; - assign n5408 = n6194 & ~n9439 & (Pg35 | ~Ng4843); - assign n5016 = ~n5408; - assign n5410 = n6404 & n6405 & (~n6008_1 | n6406); - assign n5021 = ~n5410; - assign n5412 = n7352 & ~n9260 & (~Ng2283 | n7353); - assign n5026 = ~n5412; - assign n5414 = n6939 & n6940 & (n4205 | n6941); - assign n5031_1 = ~n5414; - assign n5416_1 = n7334 & (Pg35 | ~Ng2831); - assign n5036 = ~n5416_1; - assign n5418 = n6568 & n6569 & (~n8276 | ~Ng2407); - assign n5041 = ~n5418; - assign n5420 = n6173 & (Pg35 | ~Ng2988); - assign n5046_1 = ~n5420; - assign n5422 = n7869 & (Pg35 | ~Ng2763); - assign n5051_1 = ~n5422; - assign n5424 = n6631 & ~n9356 & (n5964 | Ng1351); - assign n5425 = ~n6631 | n8082; - assign n5064 = Pg35 & (n5424 | (Ng1312 & n5425)); - assign n5427 = n7112 & n7113 & (n4205 | n6692); - assign n5069 = ~n5427; - assign n5429 = n6160_1 & (Pg35 | ~Ng4249); - assign n5074_1 = ~n5429; - assign n5431 = (n7826 | ~Ng446) & (~Ng645 | ~n8475); - assign n5079_1 = ~n5431; - assign n5433 = n7906 & ~n8132 & (Pg35 | ~Ng728); - assign n5088_1 = ~n5433; - assign n5435 = n7990 & (Pg35 | ~Ng405); - assign n5093_1 = ~n5435; - assign n5437 = n7885 & n7886 & (Ng1129 | ~n8487); - assign n5098 = ~n5437; - assign n5439 = (n6395_1 | ~Ng2227) & (n6583 | ~Ng2197); - assign n5103 = ~n5439; - assign n5441 = n7370 & ~n9270 & (Pg35 | ~Ng1825); - assign n5116 = ~n5441; - assign n5443 = n7248 & ~n9467 & (n4205 | n7249); - assign n5121 = ~n5443; - assign n5445 = n8030 & n8031 & (Pg35 | ~Ng401); - assign n5126 = ~n5445; - assign n5447 = n6630 & (n6470 | ~Ng1592); - assign n5131 = ~n5447; - assign n5449 = n8012 & n8013 & (Ng1221 | ~n8497); - assign n5141 = ~n5449; - assign n5451 = n7035 & n7036 & (n4205 | n7037); - assign n5146 = ~n5451; - assign n5453 = (n7401 | n7402) & (Pg35 | ~Ng142); - assign n5156 = ~n5453; - assign n5455 = n6797 & n6798 & (~Ng1932 | n6796); - assign n5165_1 = ~n5455; - assign n5457 = n6823 & n6819 & n6824; - assign n5170_1 = ~n5457; - assign n5459 = n7525 & ~n9292 & (Pg35 | ~Ng5467); - assign n5180_1 = ~n5459; - assign n5461_1 = ~Pg35 | ~Ng2689; - assign n5185_1 = ~n5461_1; - assign n5463 = (Pg35 | ~Ng6565) & (n6655 | n6656_1); - assign n5190_1 = ~n5463; - assign n5465 = n7728 & n7729 & (~Ng1604 | ~n8437); - assign n5195_1 = ~n5465; - assign n5467 = n6793 & n6794 & (Pg35 | ~Ng2036); - assign n5200_1 = ~n5467; - assign n5469 = n6548 & (Pg35 | ~Ng2667); - assign n5205_1 = ~n5469; - assign n5471 = n8009 & n8010 & (~Pg17423 | n8005); - assign n5210_1 = ~n5471; - assign n5473 = n7856 & n7859 & (Pg35 | ~Ng4411); - assign n5214_1 = ~n5473; - assign n5475 = n6612 & n6613 & (~n8305 | ~Ng1848); - assign n5218_1 = ~n5475; - assign n5477 = n7935 & ~n9474 & (\[4434] | n7936); - assign n5223_1 = ~n5477; - assign n5479 = n7499 & ~n9289 & (~Ng5485 | n7500); - assign n5228_1 = ~n5479; - assign n5481 = (n7335 | n7336) & (Pg35 | ~Ng2735); - assign n5233_1 = ~n5481; - assign n5483 = n7665 & n7666 & (~Ng2567 | ~n8414); - assign n5241_1 = ~n5483; - assign n5485 = n7798 & n7799 & (n7800 | n7801); - assign n5246_1 = ~n5485; - assign n5487 = n6224 & n6225 & (Pg35 | ~Ng4311); - assign n5251 = ~n5487; - assign n5489 = n7021 & ~n9457 & (n4205 | n7022); - assign n5256_1 = ~n5489; - assign n5491 = n6622 & ~n9435 & (~Ng1644 | n6621); - assign n5273 = ~n5491; - assign n5493 = n6648 & (Ng595 | n6649) & ~n9447; - assign n5278_1 = ~n5493; - assign n5495 = n6779 & n6780 & (n6775 | ~Ng2217); - assign n5283_1 = ~n5495; - assign n5497 = Ng1404 ^ n8011; - assign n5288_1 = n5497 | ~n9150; - assign n5499 = n6787 & n6788 & (~Ng2066 | n6786); - assign n5293_1 = ~n5499; - assign n5501 = n7128 & ~n9461 & (n4205 | n7129); - assign n5303_1 = ~n5501; - assign n5503 = n6392 & (Pg35 | ~Ng2246); - assign n5308_1 = ~n5503; - assign n5505 = n6349_1 & n6350 & (~n6000 | n6351); - assign n5313_1 = ~n5505; - assign n5507 = (n6697 | n6698) & (Pg35 | ~Ng5170); - assign n5318 = ~n5507; - assign n5509 = n7862 & (Pg35 | ~Ng2823); - assign n5331_1 = ~n5509; - assign n5511 = n6190 & (n6191 | ~Ng4854 | ~n8228); - assign n5339_1 = ~n5511; - assign n5513 = n6636 & n6637 & (Ng1274 | ~n5090); - assign n5349 = ~n5513; - assign n5515 = n6237 & (n6228 | n6236 | n6238); - assign n5361_1 = ~n5515; - assign n5517 = n6358 & (n6359_1 | ~Ng2509); - assign n5371_1 = ~n5517; - assign n5519 = n7881 & n7882 & (Pg35 | ~Ng1266); - assign n5381_1 = ~n5519; - assign n5521 = n6913 & ~n9451 & (n4205 | n6914); - assign n5393_1 = ~n5521; - assign n5523 = n7531 & ~n9294 & (~n6885 | ~n8449); - assign n5398_1 = ~n5523; - assign n5525 = n6957 & n6958 & (n4205 | n6959); - assign n5406_1 = ~n5525; - assign n5527 = n6137_1 & (Pg35 | ~Ng2999); - assign n5416 = ~n5527; - assign n5529 = n7827 & (Pg35 | ~Ng699); - assign n5421_1 = ~n5529; - assign n5531 = n6627 & n6628 & (n6470 | ~Ng1636); - assign n5426_1 = ~n5531; - assign n5533 = n7207 & n7208 & (n4205 | n7209); - assign n5431_1 = ~n5533; - assign n5535 = ~n7696 & (~Pg35 | n7695 | ~Ng2093); - assign n5436 = ~n5535; - assign n5537 = (Pg35 | ~Ng1052) & (n7889 | ~n9148); - assign n5451_1 = ~n5537; - assign n5539 = n6396 & n6397 & (~n6008_1 | n6398); - assign n5461 = ~n5539; - assign n5541 = n7968 & n7969 & (Ng956 | ~n8498); - assign n5466_1 = ~n5541; - assign n5543 = n6453 & ~n9445 & (~n5998_1 | n6454); - assign n5471_1 = ~n5543; - assign n5545 = n7465 & (n4205 | (Ng5849 & n7466)); - assign n5476_1 = ~n5545; - assign n5547 = n7337 & ~n9251 & (~Ng2685 | n7338); - assign n5486_1 = ~n5547; - assign n5549 = n6584 & n6585_1 & (n6395_1 | ~Ng2197); - assign n5491_1 = ~n5549; - assign n5551 = n6565_1 & (n6359_1 | ~Ng2421); - assign n5496_1 = ~n5551; - assign n5553 = n7891 & ~n9438 & (Pg35 | ~Ng1041); - assign n5501_1 = ~n5553; - assign n5555 = n7755 & n7832 & (~Pg35 | n7833); - assign n5506_1 = ~n5555; - assign n5557 = ~Ng4405 & (n7846 | ~Ng4388 | n7853); - assign n5511_1 = ~n5557; - assign n5559 = n5958 & (~Ng1536 | (Ng1526 & ~Ng1514)); - assign n5560 = Pg7946 ^ Ng1514; - assign n5516_1 = Pg35 & (n5559 | n5560); - assign n5562 = (~Ng6561 | n6657) & (~Ng6565 | n6658); - assign n5526_1 = ~n5562; - assign n5564 = n6168 & (Pg35 | ~Ng2936); - assign n5531_1 = ~n5564; - assign n5566 = n7813 & (~n6631 | Ng1345 | n7814); - assign n5536_1 = ~n5566; - assign n5568 = ~Pg35 | ~Ng4727; - assign n5549_1 = ~n5568; - assign n5570 = (~Pg17778 & (~Pg14828 | Pg12470)) | (Pg14828 & Pg12470); - assign n5554_1 = n5570 & ~Pg13099 & ~Pg17688 & Pg35 & ~Pg17722; - assign n5572 = n7193 & ~n9465 & (n4205 | n7194); - assign n5563_1 = ~n5572; - assign n5574 = n7367 & ~n9269 & (~Ng1858 | n7368); - assign n5578_1 = ~n5574; - assign n5576 = n7895 & (Pg35 | ~Ng246); - assign n5583_1 = ~n5576; - assign n5578 = n7315 & n7316 & (n4205 | n7317); - assign n5588_1 = ~n5578; - assign n5580 = n7719 & n7720 & (~Ng1740 | ~n8434); - assign n5593_1 = ~n5580; - assign n5582 = n6933 & n6934 & (n4205 | n6935); - assign n5598 = ~n5582; - assign n5584 = n6364 & n6365 & (~n6002 | n6366); - assign n5603_1 = ~n5584; - assign n5586 = n6430 & (Pg35 | ~Ng1955); - assign n5608_1 = ~n5586; - assign n5588 = n6942 & n6943 & (n4205 | n6944); - assign n5618_1 = ~n5588; - assign n5590 = n6895 & ~n9449 & (n4205 | n6654); - assign n5623_1 = ~n5590; - assign n5592 = n7234 & n7235 & (n4205 | n7236); - assign n5628 = ~n5592; - assign n5594 = n6603 & (Pg35 | ~Ng1974); - assign n5638 = ~n5594; - assign n5596 = n6477_1 & n6478 & (~n6010 | n6479); - assign n5643_1 = ~n5596; - assign n5598_1 = n6601 & n6602 & (~n8298 | ~Ng1982); - assign n5658_1 = ~n5598_1; - assign n5600 = n7144 & n7145 & (n4205 | n7146); - assign n5666_1 = ~n5600; - assign n5602 = n7802 & n7803 & (n7801 | ~n8472); - assign n5671 = ~n5602; - assign n5604 = ~Ng6381 | n8503; - assign n5676_1 = Ng6386 & (~Pg35 | n5604); - assign n5606 = n6848 & ~n9232 & (Pg35 | ~Ng5029); - assign n5695 = ~n5606; - assign n5608 = n6158 & (Pg35 | ~Ng4732); - assign n5700_1 = ~n5608; - assign n5610 = n7567 & (n4205 | (Ng3849 & n7568)); - assign n5710_1 = ~n5610; - assign n5612 = n7324 & n7325 & (n4205 | n7326); - assign n5718 = ~n5612; - assign n5614 = n7925 & (Pg35 | ~Ng5841); - assign n5723_1 = ~n5614; - assign n5616 = n6320_1 & n6321 & (n6312 | ~Ng4975); - assign n5728 = ~n5616; - assign n5618 = n6129 & n6130 & (Ng790 | n6131); - assign n5733_1 = ~n5618; - assign n5620 = n7000 & n7001 & (n4205 | n7002); - assign n5738_1 = ~n5620; - assign n5622 = n7366 & ~n9268 & (Pg35 | ~Ng1882); - assign n5743_1 = ~n5622; - assign n5624 = n7439 & ~n9282 & (~n6886 | ~n8442); - assign n5748 = ~n5624; - assign n5626 = n7762 & (Pg35 | ~Ng5619); - assign n5758_1 = ~n5626; - assign n5628_1 = (n7774 | ~n9144) & (n7775 | ~Ng4939); - assign n5763 = ~n5628_1; - assign n5630 = n7321 & n7322 & (n4205 | n7323); - assign n5772 = ~n5630; - assign n5632 = n7288 & n7289 & (n4205 | n7290); - assign n5781_1 = ~n5632; - assign n5634 = n7528 & (Pg35 | ~Ng5138); - assign n5786 = ~n5634; - assign n5636 = n7130 & ~n9462 & (n4205 | n7131); - assign n5791 = ~n5636; - assign n5638_1 = n7357 & ~n9263 & (~Ng2126 | n7358); - assign n5796 = ~n5638_1; - assign n5640 = n7365 & ~n9267 & (Pg35 | ~Ng1959); - assign n5811 = ~n5640; - assign n5642 = n7937 & n7938 & (Ng5097 | ~n8494); - assign n5816_1 = ~n5642; - assign n5644 = n7318 & n7319 & (n4205 | n7320); - assign n5821_1 = ~n5644; - assign n5646 = ~n7851 & ((Pg35 & Ng4388) | ~Ng4430); - assign n5833_1 = ~n5646; - assign n5648 = n7868 & (Pg35 | ~Ng2767); - assign n5838_1 = ~n5648; - assign n5650 = n7848 & n7849 & (n7844 | n7846); - assign n5846 = ~n5650; - assign n5652 = n6866 & n6867 & (Pg35 | ~Ng1361); - assign n5855_1 = ~n5652; - assign n5654 = n6407 & n6408 & (~n6008_1 | n6409); - assign n5869 = ~n5654; - assign n5656 = (n6377 | ~Ng2361) & (n6572 | ~Ng2331); - assign n5879_1 = ~n5656; - assign n5658 = n6877 & n6878 & (Ng582 | n6879); - assign n5888_1 = ~n5658; - assign n5660 = n7351 & ~n9259 & (Pg35 | ~Ng2307); - assign n5903_1 = ~n5660; - assign n5662_1 = n7820 & n7821 & (Ng907 | n7822); - assign n5908_1 = ~n5662_1; - assign n5664 = n7369 & (Pg35 | ~Ng1830); - assign n5918_1 = ~n5664; - assign n5666 = n7245 & n7246 & (n4205 | n7247); - assign n5923_1 = ~n5666; - assign n5668 = Ng2932 | Ng2999; - assign n5669 = n6085 & n6082 & n6083 & n6084; - assign n5928_1 = n5668 & Pg35; - assign n5671_1 = n6385_1 & n6386 & (~n6012_1 | n6387); - assign n5933_1 = ~n5671_1; - assign n5673 = n7825 & n7826 & (Pg35 | ~Ng681); - assign n5941_1 = ~n5673; - assign n5675 = n7740 & n7741 & (Pg35 | ~Ng827); - assign n5946_1 = ~n5675; - assign n5677 = n6513 & n6514 & (Pg35 | ~Ng5698); - assign n5951_1 = ~n5677; - assign n5679 = n6556 & ~n9429 & (~Ng2472 | n6555_1); - assign n5961_1 = ~n5679; - assign n5681 = n7012 & n7013 & (n4205 | n7014); - assign n5966_1 = ~n5681; - assign n5683 = n6449 & (Pg35 | ~Ng1821); - assign n5975_1 = ~n5683; - assign n5685 = n7270 & n7271 & (n4205 | n7272); - assign n5980_1 = ~n5685; - assign n5687 = n7948 & (Pg35 | ~Ng3841); - assign n5985_1 = ~n5687; - assign n5689 = n6590_1 & n6591 & (~n8291 | ~Ng2116); - assign n5990 = ~n5689; - assign n5691 = n7285 & n7286 & (n4205 | n7287); - assign n5998 = ~n5691; - assign n5693 = n7172 & n7173 & (n4205 | n7174); - assign n6003_1 = ~n5693; - assign n5695_1 = n6181 & (Pg35 | ~Ng2689); - assign n6032_1 = ~n5695_1; - assign n5697 = ~n8329 & (Pg35 | ~Ng4382); - assign n6037_1 = ~n5697; - assign n5699 = (n6658 | n6659) & (Pg35 | ~Ng6555); - assign n6042 = ~n5699; - assign n5701 = n7734 & (n7735 | ~Ng1141); - assign n6047_1 = ~n5701; - assign n5703 = n6625 & (Pg35 | ~Ng1706); - assign n6061 = ~n5703; - assign n5705 = n7405 & (Pg35 | ~Ng6523); - assign n6066_1 = ~n5705; - assign n5707 = n7291 & n7292 & (n4205 | n7293); - assign n6071_1 = ~n5707; - assign n5709 = ~n7723 & (~Pg35 | n7721 | ~Ng1691); - assign n6076_1 = ~n5709; - assign n5711 = n6169_1 & (Pg35 | ~Ng2922); - assign n6081 = ~n5711; - assign n5713 = n7931 & (Pg35 | ~Ng5148); - assign n6091 = ~n5713; - assign n5715 = ~\[4415] | n8506; - assign n6096 = Ng5348 & (~Pg35 | n5715); - assign n5717 = n6243 & (n6241 | n6242 | n6232); - assign n6104 = ~n5717; - assign n5719 = n6170 & (Pg35 | ~Ng2912); - assign n6109_1 = ~n5719; - assign n5721 = n7047 & n7048 & (n4205 | n7049); - assign n6119_1 = ~n5721; - assign n5723 = n6924 & n6925 & (n4205 | n6926); - assign n6127 = ~n5723; - assign n5725 = n6789 & n6790 & (n6785 | ~Ng2060); - assign n6132_1 = ~n5725; - assign n5727 = n7073 & n7074 & (n4205 | n7075); - assign n6142 = ~n5727; - assign n5729 = Pg135 | n6097; - assign n5730 = ~Ng4349 | ~Ng4358; - assign n5731 = ~Ng4633 | n8232; - assign n6152 = Pg35 & (n5729 | n5730 | n5731); - assign n5733 = n7630 & ~n9309 & (n7631 | ~Ng3129); - assign n6165 = ~n5733; - assign n5735 = (n6695 | n6701) & (Pg35 | ~Ng5164); - assign n6174_1 = ~n5735; - assign n5737 = n7926 & n7927 & (~n8390 | ~Ng5821); - assign n6183 = ~n5737; - assign n5739 = n6960 & n6961 & (n4205 | n6962); - assign n6188_1 = ~n5739; - assign n5741 = n7701 & n7702 & (~Ng2008 | ~n8428); - assign n6196 = ~n5741; - assign n5743 = n6533 & n6534 & (n6535 | ~Ng3703); - assign n6206 = ~n5743; - assign n5745 = n6142_1 & n6143; - assign n6216 = ~n5745; - assign n5747 = n7757 & ~n9330 & (n7758 | ~Ng411); - assign n6221 = ~n5747; - assign n5749 = n7186 & ~n9463 & (n4205 | n7187); - assign n6230 = ~n5749; - assign n5751 = n6180 & (Pg35 | ~Ng2697); - assign n6235 = ~n5751; - assign n5753_1 = n7960 & n7961 & (Ng1300 | ~n8496); - assign n6245 = ~n5753_1; - assign n5755 = n7156 & n7157 & (n4205 | n7158); - assign n6255 = ~n5755; - assign n5757 = n6854 & (n6855 | ~Ng5046 | ~n8722); - assign n6265 = ~n5757; - assign n5759 = ~n7687 & (~Pg35 | n7686 | ~Ng2250); - assign n6270 = ~n5759; - assign n5761 = ~n5991 & n6706 & (~n6860 | ~Ng4546); - assign n6279 = ~n5761; - assign n5763_1 = n6763 & n6764 & (Pg35 | ~Ng2461); - assign n6284 = ~n5763_1; - assign n5765 = n6171 & (Pg35 | ~Ng2907); - assign n6297 = ~n5765; - assign n5767 = n6767 & n6768 & (~Ng2357 | n6766); - assign n6302 = ~n5767; - assign n5769 = n6880 & n6881 & (Pg35 | ~Ng146); - assign n6310 = ~n5769; - assign n5771 = n6162 & (Pg35 | ~Ng4300); - assign n6315 = ~n5771; - assign n5773 = n6858 & (n6855 | Ng5016 | ~n8380); - assign n6320 = ~n5773; - assign n5775 = n7955 & n7956 & (~n8409 | ~Ng3119); - assign n6325_1 = ~n5775; - assign n5777 = ~n7965 & (~Ng1312 | (Pg35 & n5425)); - assign n6330 = ~n5777; - assign n5779 = n7553 & (Ng5115 | n7554) & ~n9296; - assign n6344_1 = ~n5779; - assign n5781 = n6539 & n6540 & (Pg35 | ~Ng3347); - assign n6349 = ~n5781; - assign n5783 = n6891 & (Pg35 | ~Ng6653); - assign n6354 = ~n5783; - assign n5785 = n7219 & n7220 & (n4205 | n7221); - assign n6364_1 = ~n5785; - assign n5787 = n7280 & n7281 & (n4205 | n7282); - assign n6369 = ~n5787; - assign n5789 = n7076 & ~n9459 & (n4205 | n7077); - assign n6380 = ~n5789; - assign n5791_1 = n7225 & (Pg35 | ~Ng3610); - assign n6385 = ~n5791_1; - assign n5793 = n6176 & (Pg35 | ~Ng2860); - assign n6390 = ~n5793; - assign n5795 = n7949 & n7950 & (~n8401 | ~Ng3821); - assign n6403 = ~n5795; - assign n5797 = n7944 & n7945 & (Pg35 | ~Ng4057); - assign n6408_1 = ~n5797; - assign n5799 = n7108 & (Pg35 | ~Ng5268); - assign n6417 = ~n5799; - assign n5801_1 = n6333 & n7656 & (Ng2735 | n7657); - assign n6422 = ~n5801_1; - assign n5803 = n6963 & n6964 & (n4205 | n6965); - assign n6432 = ~n5803; - assign n5805 = n7339 & (Pg35 | ~Ng2657); - assign n6437 = ~n5805; - assign n5807 = n7932 & n7933 & (n7934 | ~Ng5128); - assign n6447 = ~n5807; - assign n5809 = n7655 & ~n9312 & (Pg35 | ~Ng3111); - assign n6457 = ~n5809; - assign n5811_1 = n6199 & ~n9440 & (Pg35 | ~Ng4653); - assign n6462 = ~n5811_1; - assign n5813 = (Pg35 | ~Ng4349) & (n5968 | ~n8636); - assign n6467 = ~n5813; - assign n5815 = n6809 & n6810 & (n6805 | ~Ng1792); - assign n6472 = ~n5815; - assign n5817 = n6413_1 & (n6414 | ~Ng2084); - assign n6477 = ~n5817; - assign n5819 = n7330 & n7331 & (n4205 | n7332); - assign n6482 = ~n5819; - assign n5821 = n8233 ^ Ng4311; - assign n6487 = n5821 & ~n8235; - assign n5823 = n6341 & n6342 & (~n6000 | n6343); - assign n6492 = ~n5823; - assign n5825 = n7327 & n7328 & (n4205 | n7329); - assign n6517 = ~n5825; - assign n5827 = n7991 & n7992 & (Ng385 | n7993); - assign n6541 = ~n5827; - assign n5829 = n6426 & n6427_1 & (~n6004 | n6428); - assign n6546 = ~n5829; - assign n5831 = n7344 & (Pg35 | ~Ng2523); - assign n6551 = ~n5831; - assign n5833 = n7312 & n7313 & (n4205 | n7314); - assign n6580 = ~n5833; - assign n5835 = n6166 & (Pg35 | ~Ng2960); - assign n6585 = ~n5835; - assign n5837 = ~Ng5689 | ~n8505; - assign n6590 = Ng5694 & (~Pg35 | n5837); - assign n5839 = n7123 & ~n9460 & (n4205 | n7124); - assign n6595 = ~n5839; - assign n5841 = (~Ng3518 | n6727) & (~Ng3522 | n6728); - assign n6605 = ~n5841; - assign n5843 = n7632 & ~n9310 & (~n6890 | ~n8456); - assign n6610 = ~n5843; - assign n5845 = n7294 & n7295 & (n4205 | n7296); - assign n6615 = ~n5845; - assign n5847 = n7843 & (Pg35 | ~Ng4455); - assign n6620 = ~n5847; - assign n5849 = n6210 & n6211_1 & (n6206_1 | ~Ng4628); - assign n6624 = ~n5849; - assign n5851 = n6598 & (n6414 | ~Ng1996); - assign n6629 = ~n5851; - assign n5853 = n7841 & ~n8127 & (Pg35 | ~Ng4527); - assign n6638 = ~n5853; - assign n5855 = n7372 & ~n9272 & (~Ng1724 | n7373); - assign n6651 = ~n5855; - assign n5857 = (~Ng1379 | ~n9115) & (n6635 | ~Ng1373); - assign n6656 = ~n5857; - assign n5859_1 = (~Pg16744 & (~Pg13926 | Pg11388)) | (Pg13926 & Pg11388); - assign n6661 = n5859_1 & ~Pg14451 & ~Pg16627 & Pg35 & ~Pg16656; - assign n5861 = n6442_1 & n6443 & (~n6006 | n6444); - assign n6665 = ~n5861; - assign n5863 = n7053 & (Pg35 | ~Ng5615); - assign n6670 = ~n5863; - assign n5865 = Pg35 & (Ng5845 | Ng5831); - assign n5866 = Ng2724 | Ng2729; - assign n5867 = n8206 & Ng2735; - assign n5868 = ~n8373 & (n5866 | (n5867 & ~Ng2771)); - assign n5869_1 = n6058 & n6059 & n6060; - assign n3891_1 = ~n5869_1; - assign n5871 = n8259 | ~Ng1514; - assign n5872 = Pg17423 & (n5871 | ~Ng1526); - assign n5873 = Pg17320 & (Ng1526 | n5871); - assign n5874_1 = Ng4709 | ~Ng4785; - assign n5875 = n8208 | n8316; - assign n5876 = Ng4674 & (n5874_1 | n5875 | ~Ng4743); - assign n5877 = ~Ng3129 & ~Ng3143; - assign n5878 = ~n8373 & (n5866 | (n5867 & ~Ng2803)); - assign n2738_1 = ~n5669; - assign n5880 = Ng4420 | Ng4427; - assign n5881 = Pg35 & (Ng6537 | Ng6523); - assign n5882 = n8210 | n8317; - assign n5883 = ~Ng4888 | Ng4899 | Ng4975; - assign n5884_1 = Ng4836 & (n5882 | n5883); - assign n5885 = Pg35 & (Ng6191 | Ng6177); - assign n5886 = ~Ng1183 | n8288; - assign n5887 = Pg17400 & (n5886 | ~Ng1171); - assign n5888 = ~Ng4899 | Ng4975; - assign n5889 = Ng4871 & (n5882 | n5888 | ~Ng4944); - assign n2237_1 = ~n4252; - assign n2890_1 = ~n4909; - assign n5892 = n6075 & n6076 & n6077; - assign n1349_1 = ~n5892; - assign n5894 = Pg17316 & (Ng1171 | n5886); - assign n5895 = n6033 & n6034 & n6035; - assign n2511_1 = ~n5895; - assign n5897 = n5970 | ~Ng4180; - assign n5898_1 = ~n5997 & (n5897 | (Ng1105 & ~Ng947)); - assign n5899 = ~n8370 & (n5866 | (n5867 & ~Ng2783)); - assign n5648_1 = ~n5930; - assign n5901 = n6273 & n6272 & n6271 & n6269 & n6266 & n6267 & n6268 & n6270_1; - assign n5902 = Pg35 & (Ng3480 | Ng3494); - assign n5903 = n6042_1 & n6039 & n6040 & n6041; - assign n1586 = ~n5903; - assign n5905 = Pg35 & (Ng5152 | Ng5138); - assign n5906 = Pg35 & (Ng3845 | Ng3831); - assign n5907 = Ng4899 | ~Ng4975; - assign n5908 = Ng4864 & (n5882 | n5907 | ~Ng4933); - assign n5909 = Ng1514 | n8259; - assign n5910 = Pg17404 & (~Ng1526 | n5909); - assign n5911 = Ng1430 & (Ng1526 | n5909); - assign n5912 = n6050 & n6047 & n6048 & n6049; - assign n4939 = ~n5912; - assign n5914 = Ng1183 | n8288; - assign n5915 = ~Ng4698 | Ng4709 | Ng4785; - assign n5916 = ~n8255 & (n5866 | (n5867 & ~Ng2787)); - assign n4035_1 = ~n5929; - assign n5918 = Pg35 & (Ng5499 | Ng5485); - assign n5919 = ~n8370 & (n5866 | (n5867 & ~Ng2815)); - assign n5920 = ~n8255 & (n5866 | (n5867 & ~Ng2819)); - assign n5921 = Ng1087 & (Ng1171 | n5914); - assign n5922 = n5971 | ~Ng4180; - assign n5923 = ~n5999 & (n5922 | (Ng1300 & ~Ng1291)); - assign n5924 = ~Pg134 & (~Pg99 | ~Ng37); - assign n5925 = ~n7957 & (n5866 | (n5867 & ~Ng2807)); - assign n5926 = ~Ng4899 | ~Ng4975; - assign n5927 = Ng4878 & (n5882 | n5926 | ~Ng4955); - assign n3802_1 = ~n5945; - assign n5929 = n6123 & (n6124 | n6125 | n6126); - assign n5930 = n6108 & n6106 & n6103 & n6104_1 & n6105 & n6107; - assign n5931 = n8184 | n8185; - assign n6497 = ~Pg35 & Ng2975; - assign n5933 = Ng482 & ~Ng528 & Ng490; - assign n5934 = ~n8469 & (Ng528 | n5933); - assign n5935 = n5883 & n6136 & (n5907 | ~Ng4933); - assign n5936 = n5935 & \[4651] & \[4658] & ~n5924; - assign n2341_1 = ~n6122; - assign n5938 = n6310_1 & n6309 & n6308 & n6306 & n6303 & n6304 & n6305 & n6307; - assign n5939 = ~Ng4709 | Ng4785; - assign n5940 = Ng4681 & (n5875 | n5939 | ~Ng4754); - assign n5941 = ~n7957 & (n5866 | (n5867 & ~Ng2775)); - assign n5942 = ~n6001 & (n5922 | (Ng1472 & ~Ng1291)); - assign n3296_1 = ~n8177; - assign n5944 = ~n6003 & (n5897 | (Ng956 & ~Ng947)); - assign n5945 = ~n6109 & (n6090 | (n6110 & n6111)); - assign n2027_1 = ~n9418; - assign n5947 = n8226 | n8227; - assign n5948 = ~n6005 & (n5897 | (Ng1129 & ~Ng947)); - assign n5949 = n5915 & n6135 & (n5939 | ~Ng4754); - assign n5950 = n5949 & \[4651] & \[4658] & ~n5924; - assign n5951 = ~Ng4709 | ~Ng4785; - assign n5952 = Ng4688 & (n5875 | n5951 | ~Ng4765); - assign n5953 = ~n6007 & (n5922 | (Ng1478 & ~Ng1291)); - assign n5954 = ~n6009 & (n5897 | (Ng1135 & ~Ng947)); - assign n6179 = ~Pg35 & Ng4392; - assign n5956_1 = ~n6011 & (n5922 | (Ng1448 & ~Ng1291)); - assign n5957 = \[4436] & (~Pg12368 | Pg9048); - assign n5958 = n5963 & Pg7946 & (n5964 | n5965); - assign n5959 = n7386 & Pg7916 & n8439; - assign n5960 = ~Ng518 & ~Ng482 & ~n8181 & ~Ng499 & ~Ng528 & ~Ng490; - assign n5961 = n9154 & (~Ng718 | ~Ng655 | ~Ng753); - assign n5962 = n5960 & n5961 & (~Ng807 | ~Ng554); - assign n5963 = Ng1339 & Ng1521 & ~Ng1532; - assign n5964 = n8082 & Ng1367 & Ng1345 & Ng1379; - assign n5965 = Ng1351 | Ng1312; - assign n5966 = ~Pg113 & ~n5924; - assign n5967 = Pg72 | Pg73; - assign n5968 = Ng65 & (n5966 | n5967); - assign n5969 = ~Ng691 | Ng209; - assign n5970 = ~Pg134 & (n5969 | ~n6128); - assign n5971 = ~Pg134 & (n5091 | n5969); - assign n5972 = ~n4252 ^ n5912; - assign n5973 = ~n5895 ^ n5903; - assign n5974 = n4252 ^ n5912; - assign n5975 = n5895 ^ n5903; - assign n5976 = (n5972 | n5973) & (n5974 | n5975); - assign n5977 = ~n4909 ^ n5669; - assign n5978 = ~n5869_1 ^ n5892; - assign n5979 = n4909 ^ n5669; - assign n5980 = n5869_1 ^ n5892; - assign n5981 = (n5977 | n5978) & (n5979 | n5980); - assign n5982 = n7978 & n7979; - assign n5983 = Ng225 | n8137; - assign n5984 = ~n8137 | ~Ng225; - assign n5985 = ~n9436 & (n5982 | (n5983 & n5984)); - assign n2498_1 = ~n5949; - assign n6675 = ~n5935; - assign n5988 = Ng2357 | Ng2491 | Ng2223 | Ng2472 | Ng2204 | Ng2625 | Ng2338 | Ng2606; - assign n5989 = Ng2283 | Ng2685 | Ng2417 | Ng2537 | Ng2671 | Ng2551 | Ng2403 | Ng2269; - assign n5990_1 = ~n6860 & (~Pg73 | Pg72); - assign n5991 = ~n6860 & (Pg73 | ~Pg72); - assign n5992 = ~Pg35 & (~n6015 | ~n8158); - assign n5993 = Ng4578 & ~n6860; - assign n5994 = ~Ng2756 | ~Ng2748 | ~Ng2735 | ~Ng2741; - assign n5995 = n8198 & Pg35; - assign n5996 = n5994 & n5995 & (Ng2756 | Ng2748); - assign n5997 = ~n5970 & n6448 & (~Ng1105 | Ng947); - assign n5998_1 = Pg35 & (n5898_1 | (~\[4421] & n5997)); - assign n5999 = ~n5971 & n6336 & (~Ng1300 | Ng1291); - assign n6000 = Pg35 & (n5923 | (n5999 & ~Ng1585)); - assign n6001 = ~n5971 & n6355 & (~Ng1472 | Ng1291); - assign n6002 = Pg35 & (n5942 | (Ng1585 & n6001)); - assign n6003 = ~n5970 & n6410 & (~Ng956 | Ng947); - assign n6004 = Pg35 & (n5944 | (~\[4421] & n6003)); - assign n6005 = ~n5970 & n6429 & (~Ng1129 | Ng947); - assign n6006 = Pg35 & (n5948 | (\[4421] & n6005)); - assign n6007 = ~n5971 & n6391 & (~Ng1478 | Ng1291); - assign n6008_1 = Pg35 & (n5953 | (n6007 & Ng1585)); - assign n6009 = ~n5970 & n6466 & (~Ng1135 | Ng947); - assign n6010 = Pg35 & (n5954 | (n6009 & \[4421] )); - assign n6011 = ~n5971 & n6373_1 & (~Ng1448 | Ng1291); - assign n6012_1 = Pg35 & (n5956_1 | (~Ng1585 & n6011)); - assign n6013 = (n6027_1 | ~Ng758) & (~Ng586 | n8157); - assign n6014 = ~n5992 & n9071 & (n6063 | ~Ng613); - assign n6015 = n8147 | n8150; - assign n6016 = n6013 & n6014 & (n6015 | ~Ng794); - assign n6017_1 = (n6031 | ~Ng2950) & (n6056_1 | ~Ng2955); - assign n6018 = n6036 & n9070 & (~Ng2868 | n8149); - assign n6019 = n8151 | ~Ng51 | n8148; - assign n6020 = n6017_1 & n6018 & (~Ng37 | n6019); - assign n6021 = (Ng4927 | n8168) & (Ng4737 | n8169); - assign n6022 = (~Ng947 | n8163) & (~Ng4300 | n8166); - assign n6023 = (~Ng1291 | n8161) & (n6016 | n8142); - assign n6024 = n9072 & (~Ng4172 | n8155); - assign n6025 = (n6015 | ~Ng785) & (~Ng568 | n8157); - assign n6026 = ~n5992 & n9079 & (~\[4426] | n8159); - assign n6027_1 = n8151 | ~Ng51 | n8150; - assign n6028 = n6025 & n6026 & (n6027_1 | ~Ng744); - assign n6029 = (~Pg92 | n6019) & (~Pg127 | n8149); - assign n6030 = n9078 & (~Ng2975 | n6056_1); - assign n6031 = ~n8144 | ~Ng51 | n8150; - assign n6032 = n6029 & n6030 & (n6031 | ~Ng2970); - assign n6033 = (n8155 | ~Ng4146) & (n8166 | ~Ng4249); - assign n6034 = (n8173 | ~Ng2697) & (n6028 | n8142); - assign n6035 = n9080 & n9081 & (n8163 | ~Ng939); - assign n6036 = ~Ng51 | n8143 | ~n8144; - assign n6037 = (n8149 | ~Ng2890) & (n8174 | ~Ng2984); - assign n6038 = n6036 & n6037 & (~Pg100 | n6019); - assign n6039 = (n8161 | ~Ng1287) & (n8163 | ~Ng943); - assign n6040 = (n8166 | ~Ng4245) & (n8171 | ~Ng2145); - assign n6041 = (n8155 | ~Ng4157) & (n8173 | ~Ng2704); - assign n6042_1 = n9086 & (n8142 | (n9085 & n9083)); - assign n6043 = (n6031 | ~Ng2960) & (n6056_1 | ~Ng2965); - assign n6044 = (n8149 | ~Ng2873) & (~\[4433] | n6019); - assign n6045 = n8150 | ~Ng48 | n8146; - assign n6046 = n6043 & n6044 & (n6045 | ~Ng2878); - assign n6047 = (~Ng2689 | n8173) & (n8163 | Ng952); - assign n6048 = (n8155 | ~Ng4176) & (~Ng2130 | n8171); - assign n6049 = (n8161 | Ng1296) & (n8166 | ~Ng4253); - assign n6050 = n9077 & (n8142 | (n9076 & n9074)); - assign n6051 = (n8159 | ~Ng546) & (~Ng582 | n8157); - assign n6052 = ~n5992 & n9093 & (n6063 | ~Ng622); - assign n6053 = n6051 & n6052 & (n6027_1 | ~Ng767); - assign n6054 = (n6045 | ~Ng2864) & (n6080 | ~Ng2860); - assign n6055 = (n6031 | ~Ng2922) & (n8149 | Ng2994); - assign n6056_1 = n8150 | ~n8144 | Ng51; - assign n6057 = n6054 & n6055 & (n6056_1 | ~Ng2927); - assign n6058 = (n8168 | ~Ng4907) & (n8173 | ~Ng3151); - assign n6059 = (n8169 | ~Ng4717) & (n6053 | n8142); - assign n6060 = n9094 & n9095 & (n6057 | n8142); - assign n6061_1 = (~Ng595 | n8157) & (Pg35 | n8158); - assign n6062 = (n8159 | ~Ng538) & (n6027_1 | ~Ng776); - assign n6063 = n8143 | n8156; - assign n6064 = n6061_1 & n6062 & (n6063 | ~Ng632); - assign n6065 = (n8169 | ~Ng4727) & (n8171 | ~Ng6199); - assign n6066 = (n8168 | ~Ng4917) & (n8173 | ~Ng3853); - assign n6067 = (n8153 | ~Ng45) & (n6064 | n8142); - assign n6068 = n9089 & (n8142 | (n9088 & n9087)); - assign n6069 = (n6015 | ~Ng807) & (~Ng577 | n8157); - assign n6070 = ~n5992 & n9097 & (n8159 | ~Ng542); - assign n6071 = n6069 & n6070 & (n6027_1 | ~Ng763); - assign n6072 = (n6031 | ~Ng2936) & (n6080 | ~Ng2894); - assign n6073 = n6036 & n9096 & (n8149 | ~Ng2988); - assign n6074 = n6072 & n6073 & (n6056_1 | ~Ng2941); - assign n6075 = (n8169 | ~Ng4722) & (n6071 | n8142); - assign n6076 = (n8171 | ~Ng5160) & (n8173 | ~Ng6545); - assign n6077 = n9098 & n9099 & (n6074 | n8142); - assign n6078 = (n6045 | ~Ng2856) & (n6056_1 | ~Ng2917); - assign n6079 = (n6031 | ~Ng2912) & (n8149 | ~Ng2999); - assign n6080 = n8154 | ~Ng48 | n8150; - assign n6081_1 = n6078 & n6079 & (n6080 | ~Ng2852); - assign n6082 = (n8168 | ~Ng4922) & (n8173 | ~Ng3502); - assign n6083 = (n8169 | ~Ng4732) & (n8171 | ~Ng5853); - assign n6084 = (n8153 | ~Ng46) & (n6081_1 | n8142); - assign n6085 = n9092 & (n8142 | (n9091 & n9090)); - assign n6086 = n5981 ^ n5976; - assign n6087 = n6086 & (~Ng55 | (~Pg56 & Pg54)); - assign n6088 = ~n6086 & Ng55 & (Pg56 | ~Pg54); - assign n6089 = ~n8177 & ~Pg53 & ~Pg56 & ~Pg54; - assign n6090 = n8179 | Ng4311 | n8178; - assign n6091_1 = n5962 & (~Pg12184 | Pg11678); - assign n6092 = (n7743 | ~Ng554) & (Pg35 | ~Ng807); - assign n6093 = ~Ng794 | n6114; - assign n6094 = n9158 & (Ng4584 | ~Ng4608 | Ng4593); - assign n6095 = Ng4584 ^ Ng4608; - assign n6096_1 = Ng4601 ^ Ng4593; - assign n6097 = n6094 & (Ng4616 | n6095 | n6096_1); - assign n6098 = ~n6093 | ~Ng807 | n7743; - assign n6099 = Pg35 | ~Ng794; - assign n6100 = ~Ng632 | ~n6102 | n8183; - assign n6101 = Pg35 | ~Ng626; - assign n6102 = ~Ng626 | n6117; - assign n6103 = n8068 | n6269; - assign n6104_1 = ~Ng2070 | n6267 | Ng2040; - assign n6105 = ~Ng1936 | n6272 | Ng1906; - assign n6106 = ~Ng2227 | n6271 | Ng2197; - assign n6107 = (n8078 | n6266) & (n8080 | n6268); - assign n6108 = (n8070 | n6270_1) & (n8066 | n6273); - assign n6109 = ~n6124 & (~n9100 | ~n9101); - assign n6110 = (n5730 | n7445) & (n8191 | n8192); - assign n6111 = (n8188 | n7507) & (n8190 | n7476); - assign n6112 = ~Ng794 | ~n6114 | n7743; - assign n6113 = Pg35 | ~Ng790; - assign n6114 = ~Ng790 | n6131; - assign n6115 = ~Ng626 | ~n6117 | n8183; - assign n6116 = Pg35 | ~Ng622; - assign n6117 = ~Ng622 | n6134; - assign n6118 = (n8205 | n6306) & (n8207 | n6310_1); - assign n6119 = (n8203 | n6303) & (n8204 | n6305); - assign n6120 = (n8201 | n6309) & (n8202 | n6308); - assign n6121 = (n8197 | n6307) & (n8199 | n6304); - assign n6122 = n6121 & n6118 & n6119 & n6120; - assign n6123 = n8065 | n6090 | n7796; - assign n6124 = n8179 | ~Ng4311 | n8178; - assign n6125 = n5926 | n8211; - assign n6126 = ~Ng4878 | n8210; - assign n6127_1 = Ng2389 | Ng2657 | Ng2523 | Ng2255; - assign n6128 = Ng1193 & (Ng969 | Ng1008); - assign n6129 = ~Ng790 | ~n6131 | n7743; - assign n6130 = Pg35 | ~Ng785; - assign n6131 = ~Ng785 | n6148; - assign n6132 = ~Ng622 | ~n6134 | n8183; - assign n6133 = Pg35 | ~Ng617; - assign n6134 = ~Ng617 | n6151; - assign n6135 = (n5874_1 | ~Ng4743) & (n5951 | ~Ng4765); - assign n6136 = (n5888 | ~Ng4944) & (n5926 | ~Ng4955); - assign n6137_1 = ~Pg35 | ~Ng2994; - assign n6138 = (~Pg35 | ~Ng1287) & ~n8478; - assign n6139 = Pg35 | ~Ng1283; - assign n6140 = n4219 & (~Pg35 | ~Ng1296); - assign n6141 = Pg35 | ~Ng1291; - assign n6142_1 = n4217 & (~Pg35 | ~Ng943); - assign n6143 = Pg35 | ~Ng939; - assign n6144 = n4218 & (~Pg35 | ~Ng952); - assign n6145 = Pg35 | ~Ng947; - assign n6146 = ~Ng785 | ~n6148 | n7743; - assign n6147_1 = Pg35 | ~Ng781; - assign n6148 = ~Ng781 | n6186; - assign n6149 = ~Ng617 | ~n6151 | n8183; - assign n6150 = Pg35 | ~Ng613; - assign n6151 = ~Ng613 | n6189; - assign n6152_1 = ~Pg35 | ~Ng4927; - assign n6153 = ~Pg35 | ~Ng4912; - assign n6154 = ~Pg35 | ~Ng4907; - assign n6155 = ~Pg35 | ~Ng4922; - assign n6156_1 = ~Pg35 | ~Ng4737; - assign n6157 = ~Pg35 | ~Ng4722; - assign n6158 = ~Pg35 | ~Ng4717; - assign n6159 = ~Pg35 | ~Ng4732; - assign n6160_1 = ~Pg35 | ~Ng4245; - assign n6161 = ~Pg35 | ~Ng4249; - assign n6162 = ~Pg35 | ~Ng4253; - assign n6163 = ~Pg35 | ~Ng4157; - assign n6164 = ~Pg35 | ~Ng4146; - assign n6165_1 = ~Pg35 | ~Ng2988; - assign n6166 = ~Pg35 | ~Ng2970; - assign n6167 = ~Pg35 | ~Ng2960; - assign n6168 = ~Pg35 | ~Ng2950; - assign n6169_1 = ~Pg35 | ~Ng2936; - assign n6170 = ~Pg35 | ~Ng2922; - assign n6171 = ~Pg35 | ~Ng2912; - assign n6172 = ~Pg35 | ~Ng2907; - assign n6173 = ~Pg35 | ~Ng2868; - assign n6174 = ~Pg35 | ~Ng2873; - assign n6175 = (~Pg35 | ~Ng37) & n9187; - assign n6176 = ~Pg35 | ~Ng2894; - assign n6177 = ~Pg35 | ~Ng2860; - assign n6178 = ~Pg35 | ~Ng2852; - assign n6179_1 = ~Pg35 | ~Ng2844; - assign n6180 = ~Pg35 | ~Ng2704; - assign n6181 = ~Pg35 | ~Ng2697; - assign n6182 = ~Pg35 | ~Ng2145; - assign n6183_1 = ~Pg35 | ~Ng2138; - assign n6184 = ~Ng781 | ~n6186 | n7743; - assign n6185 = Pg35 | ~Ng776; - assign n6186 = ~Ng776 | n6257; - assign n6187 = ~Ng613 | ~n6189 | n8183; - assign n6188 = Pg35 | ~Ng608; - assign n6189 = ~Ng608 | n6259; - assign n6190 = (Pg35 | ~Ng4854) & (n6193 | ~Ng4859); - assign n6191 = ~Ng4849 | n8229; - assign n6192_1 = n6191 ^ Ng4854; - assign n6193 = ~Pg35 | ~n8228; - assign n6194 = n8229 | Ng4849 | ~n8228; - assign n6195 = (Pg35 | ~Ng4664) & (n6198 | ~Ng4669); - assign n6196_1 = ~Ng4659 | n8231; - assign n6197 = n6196_1 ^ Ng4664; - assign n6198 = ~Pg35 | ~n8230; - assign n6199 = n8231 | Ng4659 | ~n8230; - assign n6200 = n5968 | Ng4643; - assign n6201 = Pg35 & (Ng4621 | n6200); - assign n6202 = Ng4639 | n6205; - assign n6203 = ~n5968 & (~Ng4621 | Ng4639 | ~Ng4628); - assign n6204 = ~n5968 & Ng4340; - assign n6205 = ~Pg35 | n6200; - assign n6206_1 = n6202 & (Ng4621 | n6205); - assign n6207 = n6206_1 & (Ng4628 | n6205); - assign n6208 = ~Ng4621 | n6200; - assign n6209 = Pg35 & (Ng4633 | ~Ng4639 | n6208); - assign n6210 = n6208 | ~Ng4639 | Ng4628; - assign n6211_1 = Pg35 | ~Ng4621; - assign n6212 = ~n5968 & (~Ng4616 | ~n8234); - assign n6213 = (~Ng4616 | n6220) & (Pg35 | ~Ng4608); - assign n6214 = ~Ng4601 | n8061; - assign n6215 = (Pg35 | ~Ng4322) & (~Ng4332 | n8235); - assign n6216_1 = n5968 | n8062; - assign n6217 = ~Ng4608 | ~n6214 | n6220; - assign n6218 = Ng4608 | ~n6212 | n6214; - assign n6219 = Ng4601 ^ n8061; - assign n6220 = ~Pg35 | ~n6212; - assign n6221_1 = n8234 | n6220 | ~Ng4593; - assign n6222 = ~n8234 | ~n6212 | Ng4593; - assign n6223 = ~n8062 ^ Ng4584; - assign n6224 = n8236 | ~Ng4322 | n8235; - assign n6225 = ~n8236 | n6216_1 | Ng4322; - assign n6226_1 = ~n8329 & (~Pg35 | Ng2827); - assign n6227 = n9193 & (~Pg35 | ~n6229 | ~Ng2819); - assign n6228 = n5966 & Ng111; - assign n6229 = ~Ng2729 | n5994 | ~Ng2724; - assign n6230_1 = ~n8329 & (~Pg35 | Ng2811); - assign n6231 = n9194 & (~Pg35 | ~n6232 | ~Ng2807); - assign n6232 = Ng2729 | n5994 | ~Ng2724; - assign n6233 = ~n8329 & (~Pg35 | Ng2823); - assign n6234 = n9195 & (~Pg35 | ~n6235_1 | ~Ng2815); - assign n6235_1 = ~Ng2729 | n5994 | Ng2724; - assign n6236 = ~n8329 & (~Pg35 | Ng2799); - assign n6237 = n9196 & (~Pg35 | ~n6238 | ~Ng2803); - assign n6238 = n5994 | n5866; - assign n6239 = ~n8329 & (~Pg35 | Ng2795); - assign n6240_1 = n9197 & (~Pg35 | ~n6229 | ~Ng2787); - assign n6241 = n5966 & Ng85; - assign n6242 = ~n8329 & (~Pg35 | Ng2779); - assign n6243 = n9198 & (~Pg35 | ~n6232 | ~Ng2775); - assign n6244 = ~n8329 & (~Pg35 | Ng2791); - assign n6245_1 = n9199 & (~Pg35 | ~n6235_1 | ~Ng2783); - assign n6246 = ~n8329 & (~Pg35 | Ng2767); - assign n6247 = n9200 & (~Pg35 | ~n6238 | ~Ng2771); - assign n6248 = ~Ng182 ^ n9201; - assign n6249 = (Ng392 & ~Ng441) | (~Ng411 & (~Ng392 | ~Ng441)); - assign n6250_1 = ~Ng417 & n6248 & n6249 & ~Ng691; - assign n6251 = ~Ng703 & ~n5049 & n5050; - assign n6252 = Ng376 & Ng385 & Pg8719; - assign n6253 = Ng896 & (n6252 | n6251); - assign n6254 = (~Ng890 | ~Ng896) & (n6253 | ~Ng862); - assign n6255_1 = ~Ng776 | ~n6257 | n7743; - assign n6256 = Pg35 | ~Ng772; - assign n6257 = ~Ng772 | n6295; - assign n6258 = Pg35 | ~Ng604; - assign n6259 = ~Ng604 | n6297_1; - assign n6260_1 = ~Ng4141 & ~Ng4082; - assign n6261 = Ng4093 | Ng4098; - assign n6262 = ~Ng4076 | ~Ng4112; - assign n6263 = n6260_1 & (Ng4087 | n6261 | n6262); - assign n6264 = Pg113 & ~n5924; - assign n6265_1 = (~n6090 | ~n6124) & n6264; - assign n6266 = ~Ng504 | Ng528 | n8186; - assign n6267 = n8187 | Ng504 | Ng528; - assign n6268 = n8186 | Ng504 | Ng528; - assign n6269 = ~Ng528 | ~Ng504 | n8187; - assign n6270_1 = ~Ng504 | ~Ng528 | n8186; - assign n6271 = Ng504 | ~Ng528 | n8186; - assign n6272 = n8187 | Ng528 | ~Ng504; - assign n6273 = n8187 | ~Ng528 | Ng504; - assign n6274 = (~Ng4961 | ~n8237) & ~n8238; - assign n6275_1 = (~n8237 | ~Ng4950) & ~n8238; - assign n6276 = (~Pg35 | ~n8238) & (~n8237 | ~Ng4939); - assign n6277 = Pg35 | ~Ng4939; - assign n6278 = ~Pg35 | ~n6279_1 | ~Ng4933; - assign n6279_1 = n7774 & n8237; - assign n6280 = ~n8238 & (~n8237 | ~Ng4894); - assign n6281 = n8239 | ~Ng101; - assign n6282 = n6281 & (~Ng4771 | ~n8239); - assign n6283 = n6281 & (~n8239 | ~Ng4760); - assign n6284_1 = (~Pg35 | n6281) & (~n8239 | ~Ng4749); - assign n6285 = Pg35 | ~Ng4749; - assign n6286 = ~Pg35 | ~n6287 | ~Ng4743; - assign n6287 = n7790 & n8239; - assign n6288 = n6281 & (~n8239 | ~Ng4704); - assign n6289_1 = ~n5967 & (n5924 | Ng4507); - assign n6290 = ~Ng26960 | n6289_1 | Ng4477; - assign n6291 = n6290 & ~Ng4459 & (Ng4462 | ~Ng4473); - assign n6292 = Ng4643 & Pg35 & Ng4462 & ~Ng10384; - assign n6293_1 = ~Ng772 | ~n6295 | n7743; - assign n6294 = Pg35 | ~Ng767; - assign n6295 = ~Ng767 | n6488; - assign n6296 = Pg35 | ~Ng599; - assign n6297_1 = ~Ng599 | n6490; - assign n6298 = Ng142 | n8245; - assign n6299 = ~Ng142 | n7834 | ~n8245; - assign n6300 = n4520 & (Ng182 | Ng174 | Ng168); - assign n6301 = Ng160 | n9218; - assign n6302_1 = ~n9218 | ~Ng160 | n7402; - assign n6303 = n8200 | ~Ng2756 | Ng2741; - assign n6304 = n8195 | n8198; - assign n6305 = ~Ng2741 | n8196; - assign n6306 = ~Ng2756 | ~Ng2741 | n8200; - assign n6307 = Ng2741 | n8196; - assign n6308 = n8200 | Ng2741 | Ng2756; - assign n6309 = n8200 | Ng2756 | ~Ng2741; - assign n6310_1 = n8195 | ~n8206; - assign n6311 = n6126 ^ Ng4983; - assign n6312 = ~Pg35 | n6317; - assign n6313 = (n5907 | ~n8252) & (~Pg35 | n5888); - assign n6314 = (n6312 | ~Ng4899) & (n6313 | n8251); - assign n6315_1 = (Pg35 | ~Ng4991) & (n6312 | ~Ng4966); - assign n6316 = n6126 | ~Ng4983; - assign n6317 = n8251 | n8252; - assign n6318 = n6316 | Ng4991 | n6317; - assign n6319 = ~Ng4991 | n6312 | ~n6316; - assign n6320_1 = ~n8252 | Ng4975 | n8251; - assign n6321 = Pg35 | ~Ng4966; - assign n6322 = n8065 ^ Ng4793; - assign n6323 = ~Pg35 | n6328; - assign n6324 = (~Pg35 | n5939) & (n5874_1 | ~n8254); - assign n6325 = (n6323 | ~Ng4709) & (n6324 | n8253); - assign n6326 = (Pg35 | ~Ng4801) & (n6323 | ~Ng4776); - assign n6327 = n8065 | ~Ng4793; - assign n6328 = n8253 | n8254; - assign n6329 = n6327 | Ng4801 | n6328; - assign n6330_1 = ~Ng4801 | n6323 | ~n6327; - assign n6331 = ~n8254 | Ng4785 | n8253; - assign n6332 = Pg35 | ~Ng4776; - assign n6333 = ~Pg35 | Ng2841; - assign n6334 = n9223 & (~Pg35 | ~Ng2763 | ~n6335_1); - assign n6335_1 = ~Ng2759 | n6542; - assign n6336 = ~Ng2689 | ~Ng2697 | ~Ng2704; - assign n6337 = (~n6000 | n8261) & (~n8262 | ~Ng2567); - assign n6338 = ~n5923 & (~n5999 | Ng1589); - assign n6339 = (Pg35 & ~n8648) | (~Ng2629 & (~Pg35 | ~n8648)); - assign n6340_1 = ~Pg35 | n8263; - assign n6341 = Pg35 | ~Ng2571; - assign n6342 = ~Pg35 | ~n6343 | ~Ng2583; - assign n6343 = n8066 | ~n8263; - assign n6344 = Pg35 | ~Ng2583; - assign n6345 = ~Pg35 | ~Ng2579 | n8265; - assign n6346 = Pg35 | ~Ng2579; - assign n6347 = ~Pg35 | ~n6348 | ~Ng2575; - assign n6348 = ~Ng2629 | n8266; - assign n6349_1 = Pg35 | ~Ng2563; - assign n6350 = ~Pg35 | ~n6351 | ~Ng2571; - assign n6351 = ~n8263 | ~Ng2599 | Ng2629; - assign n6352 = Pg35 | ~Ng2567; - assign n6353 = ~Pg35 | ~n6354_1 | ~Ng2563; - assign n6354_1 = Ng2599 | n8266; - assign n6355 = ~Ng2689 | ~Ng2697 | Ng2704; - assign n6356 = (~n6002 | n8268) & (~n8269 | ~Ng2433); - assign n6357 = ~n5942 & (~n6001 | ~Ng1589); - assign n6358 = (Pg35 & ~n8650) | (~Ng2495 & (~Pg35 | ~n8650)); - assign n6359_1 = ~Pg35 | n8270; - assign n6360 = Pg35 | ~Ng2437; - assign n6361 = n8068 | ~n8270; - assign n6362 = Pg35 | ~Ng2449; - assign n6363 = ~Pg35 | ~Ng2445 | n8272; - assign n6364 = Pg35 | ~Ng2445; - assign n6365 = ~Pg35 | ~n6366 | ~Ng2441; - assign n6366 = ~Ng2495 | n8273; - assign n6367 = Pg35 | ~Ng2429; - assign n6368 = ~Pg35 | ~n6369_1 | ~Ng2437; - assign n6369_1 = ~n8270 | ~Ng2465 | Ng2495; - assign n6370 = Pg35 | ~Ng2433; - assign n6371 = ~Pg35 | ~n6372 | ~Ng2429; - assign n6372 = Ng2465 | n8273; - assign n6373_1 = ~Ng2704 | ~Ng2689 | Ng2697; - assign n6374 = (~n6012_1 | n8275) & (~n8276 | ~Ng2299); - assign n6375 = ~n5956_1 & (~n6011 | Ng1589); - assign n6376_1 = (Pg35 & ~n8652) | (~Ng2361 & (~Pg35 | ~n8652)); - assign n6377 = ~Pg35 | n8277; - assign n6378 = Pg35 | ~Ng2303; - assign n6379 = n8070 | ~n8277; - assign n6380_1 = Pg35 | ~Ng2315; - assign n6381 = ~Pg35 | ~Ng2311 | n8279; - assign n6382 = Pg35 | ~Ng2311; - assign n6383 = ~Pg35 | ~n6384 | ~Ng2307; - assign n6384 = ~Ng2361 | n8280; - assign n6385_1 = Pg35 | ~Ng2295; - assign n6386 = ~Pg35 | ~n6387 | ~Ng2303; - assign n6387 = ~n8277 | ~Ng2331 | Ng2361; - assign n6388 = Pg35 | ~Ng2299; - assign n6389 = ~Pg35 | ~n6390_1 | ~Ng2295; - assign n6390_1 = Ng2331 | n8280; - assign n6391 = Ng2704 | ~Ng2689 | Ng2697; - assign n6392 = (~n6008_1 | n8282) & (~n8283 | ~Ng2165); - assign n6393 = ~n5953 & (~n6007 | ~Ng1589); - assign n6394 = (Pg35 & ~n8654) | (~Ng2227 & (~Pg35 | ~n8654)); - assign n6395_1 = ~Pg35 | n8284; - assign n6396 = Pg35 | ~Ng2169; - assign n6397 = ~Pg35 | ~n6398 | ~Ng2181; - assign n6398 = Ng2197 | n8285; - assign n6399_1 = Pg35 | ~Ng2181; - assign n6400 = ~Pg35 | ~Ng2177 | n8287; - assign n6401 = Pg35 | ~Ng2177; - assign n6402 = ~Pg35 | ~n6403_1 | ~Ng2173; - assign n6403_1 = n8285 | ~Ng2153; - assign n6404 = Pg35 | ~Ng2161; - assign n6405 = ~Pg35 | ~n6406 | ~Ng2169; - assign n6406 = ~n8284 | ~Ng2197 | Ng2227; - assign n6407 = Pg35 | ~Ng2165; - assign n6408 = ~Pg35 | ~n6409 | ~Ng2161; - assign n6409 = ~Ng2153 | Ng2197 | ~n8284; - assign n6410 = ~Ng2130 | ~Ng2138 | ~Ng2145; - assign n6411 = (~n6004 | n8290) & (~n8291 | ~Ng2008); - assign n6412 = ~n5944 & (~n6003 | Ng1246); - assign n6413_1 = (Pg35 & ~n8656) | (~Ng2070 & (~Pg35 | ~n8656)); - assign n6414 = ~Pg35 | n8292; - assign n6415 = Pg35 | ~Ng2012; - assign n6416 = ~Pg35 | ~n6417_1 | ~Ng2024; - assign n6417_1 = Ng2040 | n8293; - assign n6418 = Pg35 | ~Ng2024; - assign n6419 = ~Pg35 | ~Ng2020 | n8295; - assign n6420 = Pg35 | ~Ng2020; - assign n6421 = ~Pg35 | ~n6422_1 | ~Ng2016; - assign n6422_1 = n8293 | ~Ng1996; - assign n6423 = Pg35 | ~Ng2004; - assign n6424 = ~Pg35 | ~n6425 | ~Ng2012; - assign n6425 = ~n8292 | ~Ng2040 | Ng2070; - assign n6426 = Pg35 | ~Ng2008; - assign n6427_1 = ~Pg35 | ~n6428 | ~Ng2004; - assign n6428 = ~Ng1996 | Ng2040 | ~n8292; - assign n6429 = ~Ng2130 | ~Ng2138 | Ng2145; - assign n6430 = (~n6006 | n8297) & (~n8298 | ~Ng1874); - assign n6431 = ~n5948 & (~n6005 | ~Ng1246); - assign n6432_1 = (Pg35 & ~n8658) | (~Ng1936 & (~Pg35 | ~n8658)); - assign n6433 = ~Pg35 | n8299; - assign n6434 = Pg35 | ~Ng1878; - assign n6435 = ~Pg35 | ~n6436 | ~Ng1890; - assign n6436 = Ng1906 | n8300; - assign n6437_1 = Pg35 | ~Ng1890; - assign n6438 = ~Pg35 | ~Ng1886 | n8302; - assign n6439 = Pg35 | ~Ng1886; - assign n6440 = ~Pg35 | ~n6441 | ~Ng1882; - assign n6441 = n8300 | ~Ng1862; - assign n6442_1 = Pg35 | ~Ng1870; - assign n6443 = ~Pg35 | ~n6444 | ~Ng1878; - assign n6444 = ~n8299 | ~Ng1906 | Ng1936; - assign n6445 = Pg35 | ~Ng1874; - assign n6446 = ~Pg35 | ~n6447_1 | ~Ng1870; - assign n6447_1 = ~Ng1862 | Ng1906 | ~n8299; - assign n6448 = ~Ng2145 | ~Ng2130 | Ng2138; - assign n6449 = (~n5998_1 | n8304) & (~n8305 | ~Ng1740); - assign n6450 = ~n5898_1 & (~n5997 | Ng1246); - assign n6451 = (Pg35 & ~n8660) | (~Ng1802 & (~Pg35 | ~n8660)); - assign n6452_1 = ~Pg35 | n8306; - assign n6453 = Pg35 | ~Ng1744; - assign n6454 = n8078 | ~n8306; - assign n6455 = Pg35 | ~Ng1756; - assign n6456 = ~Pg35 | ~Ng1752 | n8308; - assign n6457_1 = Pg35 | ~Ng1752; - assign n6458 = ~Pg35 | ~n6459 | ~Ng1748; - assign n6459 = ~Ng1802 | n8309; - assign n6460 = Pg35 | ~Ng1736; - assign n6461 = ~Pg35 | ~n6462_1 | ~Ng1744; - assign n6462_1 = ~n8306 | ~Ng1772 | Ng1802; - assign n6463 = Pg35 | ~Ng1740; - assign n6464 = ~Pg35 | ~n6465 | ~Ng1736; - assign n6465 = Ng1772 | n8309; - assign n6466 = Ng2145 | ~Ng2130 | Ng2138; - assign n6467_1 = (~n6010 | n8311) & (~n8312 | ~Ng1604); - assign n6468 = ~n5954 & (~n6009 | ~Ng1246); - assign n6469 = (Pg35 & ~n8662) | (~Ng1668 & (~Pg35 | ~n8662)); - assign n6470 = ~Pg35 | n8313; - assign n6471 = Pg35 | ~Ng1608; - assign n6472_1 = ~Pg35 | ~n6473 | ~Ng1620; - assign n6473 = n8080 | ~n8313; - assign n6474 = Pg35 | ~Ng1620; - assign n6475 = ~Pg35 | ~n6476 | ~Ng1616; - assign n6476 = Ng1592 | n8314; - assign n6477_1 = Pg35 | ~Ng1616; - assign n6478 = ~Pg35 | ~n6479 | ~Ng1612; - assign n6479 = ~Ng1668 | n8315; - assign n6480 = Pg35 | ~Ng1600; - assign n6481 = ~Pg35 | ~n6482_1 | ~Ng1608; - assign n6482_1 = Ng1668 | n8314; - assign n6483 = Pg35 | ~Ng1604; - assign n6484 = ~Pg35 | ~n6485 | ~Ng1600; - assign n6485 = Ng1636 | n8315; - assign n6486 = ~Ng767 | ~n6488 | n7743; - assign n6487_1 = Pg35 | ~Ng763; - assign n6488 = ~Ng763 | n6647; - assign n6489 = Pg35 | ~Ng595; - assign n6490 = ~Ng595 | n6649; - assign n6491 = Ng298 | n8244; - assign n6492_1 = ~n8244 | n7834 | ~Ng298; - assign n6493 = Ng157 | n8250; - assign n6494 = ~n8250 | n7402 | ~Ng157; - assign n6495 = (~Pg35 | n7426) & (n6500 | ~Ng6682); - assign n6496 = ~Ng6741 | Ng6682; - assign n6497_1 = n6495 & (~n5884_1 | n6496); - assign n6498 = Pg35 | ~Ng6736; - assign n6499 = ~Pg35 | ~n5884_1 | Ng6741 | ~n9420; - assign n6500 = ~Pg35 | n5884_1; - assign n6501 = (~Pg35 | n7454) & (n6506 | ~Ng6336); - assign n6502_1 = ~Ng6395 | Ng6336; - assign n6503 = n6501 & (~n5952 | n6502_1); - assign n6504 = Pg35 | ~Ng6390; - assign n6505 = ~Pg35 | ~n5952 | Ng6395 | ~n9421; - assign n6506 = ~Pg35 | n5952; - assign n6507_1 = (~Pg35 | n7488) & (n6512_1 | ~Ng5990); - assign n6508 = ~Ng6049 | Ng5990; - assign n6509 = n6507_1 & (~n5940 | n6508); - assign n6510 = Pg35 | ~Ng6044; - assign n6511 = ~Pg35 | ~n5940 | Ng6049 | ~n9423; - assign n6512_1 = ~Pg35 | n5940; - assign n6513 = n7791 | ~Ng5703; - assign n6514 = ~n9224 | Ng5703 | n8322; - assign n6515 = (~Pg35 | n7548) & (n6520 | ~Ng5297); - assign n6516 = ~Ng5357 | Ng5297; - assign n6517_1 = n6515 & (~n4151_1 | n6516); - assign n6518 = Pg35 | ~Ng5352; - assign n6519 = ~Pg35 | ~n4151_1 | Ng5357 | ~n9422; - assign n6520 = ~Pg35 | n4151_1; - assign n6521 = ~Pg35 | Ng2841; - assign n6522_1 = n9226 & (~Pg35 | ~Ng4104 | ~n6523); - assign n6523 = ~Ng4108 | n6712; - assign n6524 = (~Pg35 | n7590) & (n6529 | ~Ng3990); - assign n6525 = ~Ng4054 | Ng3990; - assign n6526_1 = n6524 & (~n5927 | n6525); - assign n6527 = Pg35 | ~Ng4049; - assign n6528 = ~Pg35 | ~n5927 | Ng4054 | ~n9419; - assign n6529 = ~Pg35 | n5927; - assign n6530 = (~Pg35 | n8327) & (n6535 | ~Ng3639); - assign n6531_1 = ~Ng3703 | Ng3639; - assign n6532 = n6530 & (~n5889 | n6531_1); - assign n6533 = Pg35 | ~Ng3698; - assign n6534 = ~Pg35 | ~n5889 | Ng3703 | ~n9424; - assign n6535 = ~Pg35 | n5889; - assign n6536_1 = (n7775 | ~Ng3288) & (~Pg35 | n7638); - assign n6537 = ~Ng3352 | Ng3288; - assign n6538 = n6536_1 & (~n5908 | n6537); - assign n6539 = n7775 | ~Ng3352; - assign n6540 = ~n9425 | Ng3352 | n8328; - assign n6541_1 = n9227 & (~Pg35 | ~Ng2759 | ~n6542); - assign n6542 = ~Ng2756 | n8258; - assign n6543 = ~Pg35 | n5966; - assign n6544 = n6543 & (~Pg35 | (n5911 & ~n6273)); - assign n6545 = Pg35 | ~Ng2555; - assign n6546_1 = Pg35 | ~Ng2671; - assign n6547 = Ng2675 | ~Pg35 | n8261; - assign n6548 = (~Ng2671 | ~n8262) & (n8261 | ~n8680); - assign n6549 = ~n6273 & n8330; - assign n6550 = Pg35 & (n6549 | ~n8263); - assign n6551_1 = n8266 | ~Pg35 | n6549; - assign n6552 = Pg35 | ~Ng2606; - assign n6553 = ~Ng2555 & (Ng2599 | ~n8263); - assign n6554 = ~Pg35 | n6549 | n6553 | Ng2629; - assign n6555_1 = n6543 & (~Pg35 | (n5872 & ~n6269)); - assign n6556 = Pg35 | ~Ng2421; - assign n6557 = Pg35 | ~Ng2537; - assign n6558 = Ng2541 | ~Pg35 | n8268; - assign n6559 = (~Ng2537 | ~n8269) & (n8268 | ~n8685); - assign n6560_1 = ~n6269 & n8330; - assign n6561 = Pg35 & (n6560_1 | ~n8270); - assign n6562 = n8273 | ~Pg35 | n6560_1; - assign n6563 = Pg35 | ~Ng2472; - assign n6564 = ~Ng2421 & (Ng2465 | ~n8270); - assign n6565_1 = ~Pg35 | n6560_1 | n6564 | Ng2495; - assign n6566 = n6543 & (~Pg35 | (n5910 & ~n6270_1)); - assign n6567 = Pg35 | ~Ng2287; - assign n6568 = Pg35 | ~Ng2403; - assign n6569 = Ng2407 | ~Pg35 | n8275; - assign n6570_1 = (~Ng2403 | ~n8276) & (n8275 | ~n8690); - assign n6571 = ~n6270_1 & n8330; - assign n6572 = Pg35 & (n6571 | ~n8277); - assign n6573 = n8280 | ~Pg35 | n6571; - assign n6574 = Pg35 | ~Ng2338; - assign n6575_1 = ~Ng2287 & (Ng2331 | ~n8277); - assign n6576 = ~Pg35 | n6571 | n6575_1 | Ng2361; - assign n6577 = n6543 & (~Pg35 | (n5873 & ~n6271)); - assign n6578 = Pg35 | ~Ng2153; - assign n6579 = Pg35 | ~Ng2269; - assign n6580_1 = Ng2273 | ~Pg35 | n8282; - assign n6581 = (~Ng2269 | ~n8283) & (n8282 | ~n8695); - assign n6582 = ~n6271 & n8330; - assign n6583 = Pg35 & (n6582 | ~n8284); - assign n6584 = ~Pg35 | n6582 | ~n8284 | ~Ng2153; - assign n6585_1 = Pg35 | ~Ng2204; - assign n6586 = ~Ng2153 & (Ng2197 | ~n8284); - assign n6587 = ~Pg35 | n6582 | n6586 | Ng2227; - assign n6588 = n6543 & (~Pg35 | (n5921 & ~n6267)); - assign n6589 = Pg35 | ~Ng1996; - assign n6590_1 = Pg35 | ~Ng2112; - assign n6591 = Ng2116 | ~Pg35 | n8290; - assign n6592 = (~Ng2112 | ~n8291) & (n8290 | ~n8700); - assign n6593 = ~n6267 & n8330; - assign n6594 = Pg35 & (n6593 | ~n8292); - assign n6595_1 = ~Pg35 | n6593 | ~n8292 | ~Ng1996; - assign n6596 = Pg35 | ~Ng2047; - assign n6597 = ~Ng1996 & (Ng2040 | ~n8292); - assign n6598 = ~Pg35 | n6593 | n6597 | Ng2070; - assign n6599 = n6543 & (~Pg35 | (n5887 & ~n6272)); - assign n6600_1 = Pg35 | ~Ng1862; - assign n6601 = Pg35 | ~Ng1978; - assign n6602 = Ng1982 | ~Pg35 | n8297; - assign n6603 = (~Ng1978 | ~n8298) & (n8297 | ~n8705); - assign n6604 = ~n6272 & n8330; - assign n6605_1 = Pg35 & (n6604 | ~n8299); - assign n6606 = ~Pg35 | n6604 | ~n8299 | ~Ng1862; - assign n6607 = Pg35 | ~Ng1913; - assign n6608 = ~Ng1862 & (Ng1906 | ~n8299); - assign n6609 = ~Pg35 | n6604 | n6608 | Ng1936; - assign n6610_1 = n6543 & (~Pg35 | (n5894 & ~n6266)); - assign n6611 = Pg35 | ~Ng1728; - assign n6612 = Pg35 | ~Ng1844; - assign n6613 = Ng1848 | ~Pg35 | n8304; - assign n6614 = (~Ng1844 | ~n8305) & (n8304 | ~n8710); - assign n6615_1 = ~n6266 & n8330; - assign n6616 = Pg35 & (n6615_1 | ~n8306); - assign n6617 = n8309 | ~Pg35 | n6615_1; - assign n6618 = Pg35 | ~Ng1779; - assign n6619 = ~Ng1728 & (Ng1772 | ~n8306); - assign n6620_1 = ~Pg35 | n6615_1 | n6619 | Ng1802; - assign n6621 = n6543 & (~Pg35 | (n4162 & ~n6268)); - assign n6622 = Pg35 | ~Ng1592; - assign n6623 = Pg35 | ~Ng1710; - assign n6624_1 = Ng1714 | ~Pg35 | n8311; - assign n6625 = (~Ng1710 | ~n8312) & (n8311 | ~n8715); - assign n6626 = (n6470 | ~Ng1668) & (n8314 | n9114); - assign n6627 = n9114 | ~Pg35 | n8315; - assign n6628 = Pg35 | ~Ng1644; - assign n6629_1 = ~Ng1592 & (Ng1636 | ~n8313); - assign n6630 = ~Pg35 | n6629_1 | Ng1668 | n9114; - assign n6631 = Ng1333 | Ng1322; - assign n6632 = n6631 & (Ng1345 | ~n8333); - assign n6633 = n6632 & (Ng1361 | ~n8333); - assign n6634_1 = n6633 & (Ng1367 | ~n8333); - assign n6635 = Pg35 & (~n6634_1 | Ng1379 | ~n8333); - assign n6636 = n8005 | ~Ng1274 | n5090; - assign n6637 = Pg35 | ~Ng1270; - assign n6638_1 = Ng990 | Ng979; - assign n6639 = n6638_1 & (Ng1002 | ~n8339); - assign n6640 = n6639 & (Ng1018 | ~n8339); - assign n6641 = n6640 & (Ng1024 | ~n8339); - assign n6642_1 = Pg35 & (~n6641 | Ng1036 | ~n8339); - assign n6643 = n8014 | ~Ng930 | n5097; - assign n6644 = Pg35 | ~Ng925; - assign n6645 = ~Ng763 | ~n6647 | n7743; - assign n6646_1 = Pg35 | ~Ng758; - assign n6647 = ~Ng758 | n6837; - assign n6648 = Pg35 | ~Ng590; - assign n6649 = ~Ng590 | n6839; - assign n6650 = Ng294 | n8243; - assign n6651_1 = ~n8243 | n7834 | ~Ng294; - assign n6652 = Ng153 | n8249; - assign n6653 = ~n8249 | n7402 | ~Ng153; - assign n6654 = ~Ng6561 | n8346; - assign n6655 = n6654 & (~n4287_1 | (Ng6561 & Ng6565)); - assign n6656_1 = n7942 & n8344; - assign n6657 = Pg35 & (Ng6565 | n6656_1); - assign n6658 = n6656_1 | ~Pg35 | Ng6561; - assign n6659 = ~Ng6555 | ~Ng6549; - assign n6660 = Ng6555 | ~Ng6549; - assign n6661_1 = ~Ng6555 | Ng6549; - assign n6662 = n6660 & (~Pg35 | n6661_1); - assign n6663 = ~Ng6215 | n8348; - assign n6664 = ~Pg35 | ~Ng6227; - assign n6665_1 = n6663 & (n6664 | (Ng6215 & Ng6219)); - assign n6666 = n8218 & n8347; - assign n6667 = Pg35 & (Ng6219 | n6666); - assign n6668 = n6666 | ~Pg35 | Ng6215; - assign n6669 = ~Ng6203 | ~Ng6209; - assign n6670_1 = ~Ng6203 | Ng6209; - assign n6671 = Ng6203 | ~Ng6209; - assign n6672 = n6670_1 & (~Pg35 | n6671); - assign n6673 = ~Ng5869 | n8350; - assign n6674 = n6673 & (~n1064_1 | (Ng5869 & Ng5873)); - assign n6675_1 = n8218 & n8344; - assign n6676 = Pg35 & (Ng5873 | n6675_1); - assign n6677 = n6675_1 | ~Pg35 | Ng5869; - assign n6678 = ~Ng5863 | ~Ng5857; - assign n6679 = Ng5863 | ~Ng5857; - assign n6680_1 = ~Ng5863 | Ng5857; - assign n6681 = n6679 & (~Pg35 | n6680_1); - assign n6682 = ~Ng5523 | n8351; - assign n6683 = ~Pg35 | ~Ng5535; - assign n6684 = n6682 & (n6683 | (Ng5523 & Ng5527)); - assign n6685 = ~n6261 & n8347; - assign n6686 = Pg35 & (Ng5527 | n6685); - assign n6687 = n6685 | ~Pg35 | Ng5523; - assign n6688 = ~Ng5517 | ~Ng5511; - assign n6689 = Ng5517 | ~Ng5511; - assign n6690 = ~Ng5517 | Ng5511; - assign n6691 = n6689 & (~Pg35 | n6690); - assign n6692 = ~Ng5176 | n8352; - assign n6693 = ~Pg35 | ~Ng5188; - assign n6694 = n6692 & (n6693 | (Ng5176 & Ng5180)); - assign n6695 = ~n6261 & n8344; - assign n6696 = Pg35 & (Ng5180 | n6695); - assign n6697 = n6695 | ~Pg35 | Ng5176; - assign n6698 = ~Ng5170 | ~Ng5164; - assign n6699 = Ng5170 | ~Ng5164; - assign n6700 = ~Ng5170 | Ng5164; - assign n6701 = n6699 & (~Pg35 | n6700); - assign n6702 = n9230 | ~Pg35 | Ng5057; - assign n6703 = ~n9230 | n6855 | ~Ng5057; - assign n6704 = (n6860 & ~Ng4549) | (~n5967 & (~n6860 | ~Ng4549)); - assign n6705 = ~n5993 & n6704; - assign n6706 = n6860 | ~Ng4575; - assign n6707 = (n6860 & ~Ng4504) | (~n5967 & (~n6860 | ~Ng4504)); - assign n6708 = n6860 | ~Ng4572; - assign n6709 = n6707 & n6708; - assign n6710 = ~\[4437] | n6860; - assign n6711 = n9231 & (~Pg35 | ~Ng4108 | ~n6712); - assign n6712 = ~Ng4098 | n8326; - assign n6713 = ~Ng3869 | n8365; - assign n6714 = ~Pg35 | ~Ng3881; - assign n6715 = n6713 & (n6714 | (Ng3869 & Ng3873)); - assign n6716 = n8220 & n8347; - assign n6717 = Pg35 & (Ng3873 | n6716); - assign n6718 = n6716 | ~Pg35 | Ng3869; - assign n6719 = ~Ng3857 | ~Ng3863; - assign n6720 = ~Ng3857 | Ng3863; - assign n6721 = Ng3857 | ~Ng3863; - assign n6722 = n6720 & (~Pg35 | n6721); - assign n6723 = ~Ng3518 | n8366; - assign n6724 = ~Pg35 | ~Ng3530; - assign n6725 = n6723 & (n6724 | (Ng3518 & Ng3522)); - assign n6726 = n8220 & n8344; - assign n6727 = Pg35 & (Ng3522 | n6726); - assign n6728 = n6726 | ~Pg35 | Ng3518; - assign n6729 = ~Ng3512 | ~Ng3506; - assign n6730 = Ng3512 | ~Ng3506; - assign n6731 = ~Ng3512 | Ng3506; - assign n6732 = n6730 & (~Pg35 | n6731); - assign n6733 = ~Ng3167 | n8367; - assign n6734 = ~Pg35 | ~Ng3179; - assign n6735 = n6733 & (n6734 | (Ng3167 & Ng3171)); - assign n6736 = n7942 & n8347; - assign n6737 = Pg35 & (Ng3171 | n6736); - assign n6738 = n6736 | ~Pg35 | Ng3167; - assign n6739 = ~Ng3161 | ~Ng3155; - assign n6740 = Ng3161 | ~Ng3155; - assign n6741 = ~Ng3161 | Ng3155; - assign n6742 = n6740 & (~Pg35 | n6741); - assign n6743 = Pg35 | ~Ng2748; - assign n6744 = n8258 ^ Ng2756; - assign n6745 = ~Pg35 | n5920; - assign n6746 = n6543 & (~Pg35 | ~n6306) & n6745; - assign n6747 = n8085 | ~n8329 | ~n5920 | n6306; - assign n6748 = Pg35 | ~Ng2610; - assign n6749 = n8369 | n6306 | ~n8368; - assign n6750 = (Pg35 | ~Ng2625) & (~Ng2610 | n8369); - assign n6751 = (n6745 & ~Ng2587) | (~Ng2610 & (~n6745 | ~Ng2587)); - assign n6752 = n6751 & n6749; - assign n6753 = ~n8415 | Ng2619 | n8369; - assign n6754 = (Pg35 | ~Ng2595) & (n6745 | ~Ng2587); - assign n6755 = ~Pg35 | n5919; - assign n6756 = n6543 & (~Pg35 | ~n6303) & n6755; - assign n6757 = n8087 | ~n8329 | ~n5919 | n6303; - assign n6758 = Pg35 | ~Ng2476; - assign n6759 = n8371 | n6303 | ~n8368; - assign n6760 = (Pg35 | ~Ng2491) & (~Ng2476 | n8371); - assign n6761 = (n6755 & ~Ng2453) | (~Ng2476 & (~n6755 | ~Ng2453)); - assign n6762 = n6761 & n6759; - assign n6763 = ~Pg35 | ~Ng2453 | n8416; - assign n6764 = n6759 & (Ng2485 | Ng2476 | n8371); - assign n6765 = ~Pg35 | n5925; - assign n6766 = n6543 & (~Pg35 | ~n6305) & n6765; - assign n6767 = n8089 | ~n8329 | ~n5925 | n6305; - assign n6768 = Pg35 | ~Ng2342; - assign n6769 = n8372 | n6305 | ~n8368; - assign n6770 = (Pg35 | ~Ng2357) & (~Ng2342 | n8372); - assign n6771 = (n6765 & ~Ng2319) | (~Ng2342 & (~n6765 | ~Ng2319)); - assign n6772 = n6771 & n6769; - assign n6773 = ~n8422 | Ng2351 | n8372; - assign n6774 = (Pg35 | ~Ng2327) & (n6765 | ~Ng2319); - assign n6775 = ~Pg35 | n5878; - assign n6776 = n6543 & (~Pg35 | ~n6307) & n6775; - assign n6777 = n8091 | ~n8329 | ~n5878 | n6307; - assign n6778 = Pg35 | ~Ng2208; - assign n6779 = n8374 | n6307 | ~n8368; - assign n6780 = (Pg35 | ~Ng2223) & (~Ng2208 | n8374); - assign n6781 = (n6775 & ~Ng2185) | (~Ng2208 & (~n6775 | ~Ng2185)); - assign n6782 = n6781 & n6779; - assign n6783 = ~n8425 | Ng2217 | n8374; - assign n6784 = (Pg35 | ~Ng2193) & (n6775 | ~Ng2185); - assign n6785 = ~Pg35 | n5916; - assign n6786 = n6543 & (~Pg35 | ~n6309) & n6785; - assign n6787 = n8093 | ~n8329 | ~n5916 | n6309; - assign n6788 = Pg35 | ~Ng2051; - assign n6789 = n8375 | n6309 | ~n8368; - assign n6790 = (Pg35 | ~Ng2066) & (~Ng2051 | n8375); - assign n6791 = (n6785 & ~Ng2028) | (~Ng2051 & (~n6785 | ~Ng2028)); - assign n6792 = n6791 & n6789; - assign n6793 = ~Pg35 | ~Ng2028 | n8426; - assign n6794 = n6789 & (Ng2051 | Ng2060 | n8375); - assign n6795 = ~Pg35 | n5899; - assign n6796 = n6543 & (~Pg35 | ~n6308) & n6795; - assign n6797 = n8095 | ~n8329 | ~n5899 | n6308; - assign n6798 = Pg35 | ~Ng1917; - assign n6799 = n8376 | n6308 | ~n8368; - assign n6800 = (Pg35 | ~Ng1932) & (~Ng1917 | n8376); - assign n6801 = (n6795 & ~Ng1894) | (~Ng1917 & (~n6795 | ~Ng1894)); - assign n6802 = n6801 & n6799; - assign n6803 = ~n8432 | Ng1926 | n8376; - assign n6804 = (Pg35 | ~Ng1902) & (n6795 | ~Ng1894); - assign n6805 = ~Pg35 | n5941; - assign n6806 = n6543 & (~Pg35 | ~n6304) & n6805; - assign n6807 = n8097 | ~n8329 | ~n5941 | n6304; - assign n6808 = Pg35 | ~Ng1783; - assign n6809 = n8377 | n6304 | ~n8368; - assign n6810 = (Pg35 | ~Ng1798) & (~Ng1783 | n8377); - assign n6811 = (n6805 & ~Ng1760) | (~Ng1783 & (~n6805 | ~Ng1760)); - assign n6812 = n6811 & n6809; - assign n6813 = ~n8435 | Ng1792 | n8377; - assign n6814 = (Pg35 | ~Ng1768) & (n6805 | ~Ng1760); - assign n6815 = ~Pg35 | n5868; - assign n6816 = n6543 & (~Pg35 | ~n6310_1) & n6815; - assign n6817 = n8099 | ~n8329 | ~n5868 | n6310_1; - assign n6818 = Pg35 | ~Ng1648; - assign n6819 = n8378 | n6310_1 | ~n8368; - assign n6820 = (Pg35 | ~Ng1664) & (~Ng1648 | n8378); - assign n6821 = (n6815 & ~Ng1624) | (~Ng1648 & (~n6815 | ~Ng1624)); - assign n6822 = n6821 & n6819; - assign n6823 = ~n8438 | Ng1657 | n8378; - assign n6824 = (Pg35 | ~Ng1632) & (n6815 | ~Ng1624); - assign n6825 = ~Ng1373 | ~Pg35 | n6634_1; - assign n6826 = Ng1373 | ~n6634_1 | n7814; - assign n6827 = ~Ng1270 | ~n6829 | n8005; - assign n6828 = Pg35 | ~Ng1263; - assign n6829 = ~Ng1263 | ~n8336; - assign n6830 = ~Ng1030 | ~Pg35 | n6641; - assign n6831 = Ng1030 | ~n6641 | n7819; - assign n6832 = ~Ng925 | ~n6834 | n8014; - assign n6833 = Pg35 | ~Ng918; - assign n6834 = ~Ng918 | ~n8342; - assign n6835 = ~Ng758 | ~n6837 | n7743; - assign n6836 = Pg35 | ~Ng749; - assign n6837 = ~Ng749 | n6876; - assign n6838 = Pg35 | ~Ng582; - assign n6839 = ~Ng582 | n6879; - assign n6840 = ~n8242 | Ng291; - assign n6841 = ~Ng291 | n7834 | n8242; - assign n6842 = ~n8248 | Ng150; - assign n6843 = ~Ng150 | n7402 | n8248; - assign n6844 = (~Ng2950 | ~Ng2955) & (~Ng2927 | ~Ng2922); - assign n6845 = ~Ng2936 | ~Ng2941; - assign n6846 = (~Ng2975 | ~Ng2970) & (~Ng2902 | ~Ng2907); - assign n6847 = (~Ng2965 | ~Ng2960) & (~Ng2917 | ~Ng2912); - assign n6848 = n6855 | ~n8353 | ~Ng5033 | ~n8355; - assign n6849 = n6855 | ~Ng5052 | ~n8357 | ~n9229; - assign n6850 = n8364 | ~Ng5029 | Ng5062; - assign n6851 = Pg35 & n6850 & (Ng5029 | ~Ng5062); - assign n6852 = ~Ng5029 | n6855 | Ng5016 | Ng5022; - assign n6853 = ~Pg35 | n8355; - assign n6854 = n9234 & (~Pg35 | Ng5046 | n8722); - assign n6855 = ~Pg35 | n8364; - assign n6856 = n9235 & (~Pg35 | Ng5041 | n8379); - assign n6857 = n9236 & (~Pg35 | Ng5037 | n8723); - assign n6858 = n9237 & (~Pg35 | ~Ng5016 | n8380); - assign n6859 = ~Ng4372 | ~Pg35 | Ng4581; - assign n6860 = ~Pg35 | ~Ng4581; - assign n6861 = n6859 & (n6860 | (Pg72 & Pg73)); - assign n6862 = Pg35 | ~Ng4093; - assign n6863 = n8326 ^ Ng4098; - assign n6864 = ~n8257 | ~Ng2748 | n7336; - assign n6865 = ~Ng2841 | Ng2748 | n8257; - assign n6866 = ~Ng1367 | ~Pg35 | n6633; - assign n6867 = n7814 | ~n6633 | Ng1367; - assign n6868 = n8336 | ~Ng1263 | n8005; - assign n6869 = Pg35 | ~Ng1259; - assign n6870 = ~Ng1024 | ~Pg35 | n6640; - assign n6871 = n7819 | ~n6640 | Ng1024; - assign n6872 = n8342 | ~Ng918 | n8014; - assign n6873 = Pg35 | ~Ng914; - assign n6874 = ~Ng749 | ~n6876 | n7743; - assign n6875 = Pg35 | ~Ng744; - assign n6876 = ~Ng744 | n7397; - assign n6877 = ~Ng582 | ~n6879 | n8183; - assign n6878 = Pg35 | ~Ng577; - assign n6879 = ~Ng577 | n7400; - assign n6880 = Ng164 | ~n8247; - assign n6881 = n8247 | n7402 | ~Ng164; - assign n6882 = (~n5880 | ~n8105) & ~n8213; - assign n6883 = n6885 | n6886; - assign n6884 = Pg35 & Ng5817; - assign n6885 = Pg35 & Ng5124; - assign n6886 = Pg35 & Ng6163; - assign n6887 = n6883 & (n6884 | (n6885 & n6886)); - assign n6888 = n8104 | n8101 | n8103 | n5880 | n8213 | n8105; - assign n6889 = Pg35 & Ng3817; - assign n6890 = Pg35 & Ng3115; - assign n6891 = (n4205 | n7404) & (~n8381 | ~Ng6657); - assign n6892 = Pg35 | ~Ng6649; - assign n6893 = ~Pg35 | ~n6894 | ~Ng6605; - assign n6894 = ~Ng6561 | n8383; - assign n6895 = Pg35 | ~Ng6645; - assign n6896 = Pg35 | ~Ng6641; - assign n6897 = ~Pg35 | ~n6898 | ~Ng6589; - assign n6898 = ~Ng6561 | n8384; - assign n6899 = Pg35 | ~Ng6637; - assign n6900 = n8222 | n6659; - assign n6901 = Pg35 | ~Ng6633; - assign n6902 = ~Pg35 | ~n6903 | ~Ng6649; - assign n6903 = n6659 | n8383; - assign n6904 = Pg35 | ~Ng6629; - assign n6905 = ~Pg35 | ~n6906 | ~Ng6645; - assign n6906 = n8346 | n6659; - assign n6907 = Pg35 | ~Ng6625; - assign n6908 = ~Pg35 | ~n6909 | ~Ng6641; - assign n6909 = n6659 | n8384; - assign n6910 = Pg35 | ~Ng6621; - assign n6911 = ~Pg35 | ~n6912 | ~Ng6637; - assign n6912 = n8222 | n6661_1; - assign n6913 = Pg35 | ~Ng6617; - assign n6914 = n6661_1 | n8383; - assign n6915 = Pg35 | ~Ng6613; - assign n6916 = ~Pg35 | ~n6917 | ~Ng6629; - assign n6917 = n8346 | n6661_1; - assign n6918 = Pg35 | ~Ng6609; - assign n6919 = ~Pg35 | ~n6920 | ~Ng6625; - assign n6920 = n6661_1 | n8384; - assign n6921 = Pg35 | ~Ng6601; - assign n6922 = ~Pg35 | ~n6923 | ~Ng6621; - assign n6923 = n8222 | n6660; - assign n6924 = Pg35 | ~Ng6593; - assign n6925 = ~Pg35 | ~n6926 | ~Ng6617; - assign n6926 = n8383 | n6660; - assign n6927 = Pg35 | ~Ng6585; - assign n6928 = ~Pg35 | ~n6929 | ~Ng6613; - assign n6929 = n8346 | n6660; - assign n6930 = Pg35 | ~Ng6581; - assign n6931 = ~Pg35 | ~n6932 | ~Ng6609; - assign n6932 = n8384 | n6660; - assign n6933 = Pg35 | ~Ng6605; - assign n6934 = ~Pg35 | ~n6935 | ~Ng6601; - assign n6935 = n8222 | n8385; - assign n6936 = Pg35 | ~Ng6597; - assign n6937 = ~Pg35 | ~n6938 | ~Ng6593; - assign n6938 = n8383 | n8385; - assign n6939 = Pg35 | ~Ng6589; - assign n6940 = ~Pg35 | ~n6941 | ~Ng6585; - assign n6941 = n8346 | n8385; - assign n6942 = Pg35 | ~Ng6573; - assign n6943 = ~Pg35 | ~n6944 | ~Ng6581; - assign n6944 = n8384 | n8385; - assign n6945 = (n4205 | n7435) & (~n8386 | ~Ng6311); - assign n6946 = Pg35 | ~Ng6303; - assign n6947 = ~Pg35 | ~n6948 | ~Ng6259; - assign n6948 = ~Ng6215 | n8387; - assign n6949 = Pg35 | ~Ng6299; - assign n6950 = ~Pg35 | ~n6663 | ~Ng6251; - assign n6951 = Pg35 | ~Ng6295; - assign n6952 = ~Pg35 | ~n6953 | ~Ng6243; - assign n6953 = ~Ng6215 | n8388; - assign n6954 = Pg35 | ~Ng6291; - assign n6955 = ~Pg35 | ~n6956 | ~Ng6307; - assign n6956 = n8217 | n6669; - assign n6957 = Pg35 | ~Ng6287; - assign n6958 = ~Pg35 | ~n6959 | ~Ng6303; - assign n6959 = n6669 | n8387; - assign n6960 = Pg35 | ~Ng6283; - assign n6961 = ~Pg35 | ~n6962 | ~Ng6299; - assign n6962 = n8348 | n6669; - assign n6963 = Pg35 | ~Ng6279; - assign n6964 = ~Pg35 | ~n6965 | ~Ng6295; - assign n6965 = n6669 | n8388; - assign n6966 = Pg35 | ~Ng6275; - assign n6967 = ~Pg35 | ~n6968 | ~Ng6291; - assign n6968 = n8217 | n6671; - assign n6969 = Pg35 | ~Ng6271; - assign n6970 = n6671 | n8387; - assign n6971 = Pg35 | ~Ng6267; - assign n6972 = n8348 | n6671; - assign n6973 = Pg35 | ~Ng6263; - assign n6974 = ~Pg35 | ~n6975 | ~Ng6279; - assign n6975 = n6671 | n8388; - assign n6976 = Pg35 | ~Ng6255; - assign n6977 = n8217 | n6670_1; - assign n6978 = Pg35 | ~Ng6247; - assign n6979 = ~Pg35 | ~n6980 | ~Ng6271; - assign n6980 = n8387 | n6670_1; - assign n6981 = Pg35 | ~Ng6239; - assign n6982 = ~Pg35 | ~n6983 | ~Ng6267; - assign n6983 = n8348 | n6670_1; - assign n6984 = Pg35 | ~Ng6235; - assign n6985 = ~Pg35 | ~n6986 | ~Ng6263; - assign n6986 = n8388 | n6670_1; - assign n6987 = Pg35 | ~Ng6259; - assign n6988 = ~Pg35 | ~n6989 | ~Ng6255; - assign n6989 = n8217 | n8389; - assign n6990 = Pg35 | ~Ng6251; - assign n6991 = ~Pg35 | ~n6992 | ~Ng6247; - assign n6992 = n8387 | n8389; - assign n6993 = Pg35 | ~Ng6243; - assign n6994 = ~Pg35 | ~n6995 | ~Ng6239; - assign n6995 = n8348 | n8389; - assign n6996 = Pg35 | ~Ng6227; - assign n6997 = ~Pg35 | ~n6998 | ~Ng6235; - assign n6998 = n8388 | n8389; - assign n6999 = (n4205 | n7466) & (~n8390 | ~Ng5965); - assign n7000 = Pg35 | ~Ng5957; - assign n7001 = ~Pg35 | ~n7002 | ~Ng5913; - assign n7002 = ~Ng5869 | n8391; - assign n7003 = Pg35 | ~Ng5953; - assign n7004 = Pg35 | ~Ng5949; - assign n7005 = ~Pg35 | ~n7006 | ~Ng5897; - assign n7006 = ~Ng5869 | n8392; - assign n7007 = Pg35 | ~Ng5945; - assign n7008 = n8223 | n6678; - assign n7009 = Pg35 | ~Ng5941; - assign n7010 = ~Pg35 | ~n7011 | ~Ng5957; - assign n7011 = n6678 | n8391; - assign n7012 = Pg35 | ~Ng5937; - assign n7013 = ~Pg35 | ~n7014 | ~Ng5953; - assign n7014 = n8350 | n6678; - assign n7015 = Pg35 | ~Ng5933; - assign n7016 = ~Pg35 | ~n7017 | ~Ng5949; - assign n7017 = n6678 | n8392; - assign n7018 = Pg35 | ~Ng5929; - assign n7019 = ~Pg35 | ~n7020 | ~Ng5945; - assign n7020 = n8223 | n6680_1; - assign n7021 = Pg35 | ~Ng5925; - assign n7022 = n6680_1 | n8391; - assign n7023 = Pg35 | ~Ng5921; - assign n7024 = ~Pg35 | ~n7025 | ~Ng5937; - assign n7025 = n8350 | n6680_1; - assign n7026 = Pg35 | ~Ng5917; - assign n7027 = ~Pg35 | ~n7028 | ~Ng5933; - assign n7028 = n6680_1 | n8392; - assign n7029 = Pg35 | ~Ng5909; - assign n7030 = ~Pg35 | ~n7031 | ~Ng5929; - assign n7031 = n8223 | n6679; - assign n7032 = Pg35 | ~Ng5901; - assign n7033 = ~Pg35 | ~n7034 | ~Ng5925; - assign n7034 = n8391 | n6679; - assign n7035 = Pg35 | ~Ng5893; - assign n7036 = ~Pg35 | ~n7037 | ~Ng5921; - assign n7037 = n8350 | n6679; - assign n7038 = Pg35 | ~Ng5889; - assign n7039 = ~Pg35 | ~n7040 | ~Ng5917; - assign n7040 = n8392 | n6679; - assign n7041 = Pg35 | ~Ng5913; - assign n7042 = ~Pg35 | ~n7043 | ~Ng5909; - assign n7043 = n8223 | n8393; - assign n7044 = Pg35 | ~Ng5905; - assign n7045 = ~Pg35 | ~n7046 | ~Ng5901; - assign n7046 = n8391 | n8393; - assign n7047 = Pg35 | ~Ng5897; - assign n7048 = ~Pg35 | ~n7049 | ~Ng5893; - assign n7049 = n8350 | n8393; - assign n7050 = Pg35 | ~Ng5881; - assign n7051 = ~Pg35 | ~n7052 | ~Ng5889; - assign n7052 = n8392 | n8393; - assign n7053 = (n4205 | n7497) & (~n8394 | ~Ng5619); - assign n7054 = Pg35 | ~Ng5611; - assign n7055 = ~Pg35 | ~n7056 | ~Ng5567; - assign n7056 = ~Ng5523 | n8395; - assign n7057 = Pg35 | ~Ng5607; - assign n7058 = Pg35 | ~Ng5603; - assign n7059 = ~Pg35 | ~n7060 | ~Ng5551; - assign n7060 = ~Ng5523 | n8396; - assign n7061 = Pg35 | ~Ng5599; - assign n7062 = ~Pg35 | ~n7063 | ~Ng5615; - assign n7063 = n8221 | n6688; - assign n7064 = Pg35 | ~Ng5595; - assign n7065 = ~Pg35 | ~n7066 | ~Ng5611; - assign n7066 = n6688 | n8395; - assign n7067 = Pg35 | ~Ng5591; - assign n7068 = ~Pg35 | ~n7069 | ~Ng5607; - assign n7069 = n8351 | n6688; - assign n7070 = Pg35 | ~Ng5587; - assign n7071 = ~Pg35 | ~n7072 | ~Ng5603; - assign n7072 = n6688 | n8396; - assign n7073 = Pg35 | ~Ng5583; - assign n7074 = ~Pg35 | ~n7075 | ~Ng5599; - assign n7075 = n8221 | n6690; - assign n7076 = Pg35 | ~Ng5579; - assign n7077 = n6690 | n8395; - assign n7078 = Pg35 | ~Ng5575; - assign n7079 = ~Pg35 | ~n7080 | ~Ng5591; - assign n7080 = n8351 | n6690; - assign n7081 = Pg35 | ~Ng5571; - assign n7082 = ~Pg35 | ~n7083 | ~Ng5587; - assign n7083 = n6690 | n8396; - assign n7084 = Pg35 | ~Ng5563; - assign n7085 = ~Pg35 | ~n7086 | ~Ng5583; - assign n7086 = n8221 | n6689; - assign n7087 = Pg35 | ~Ng5555; - assign n7088 = ~Pg35 | ~n7089 | ~Ng5579; - assign n7089 = n8395 | n6689; - assign n7090 = Pg35 | ~Ng5547; - assign n7091 = ~Pg35 | ~n7092 | ~Ng5575; - assign n7092 = n8351 | n6689; - assign n7093 = Pg35 | ~Ng5543; - assign n7094 = ~Pg35 | ~n7095 | ~Ng5571; - assign n7095 = n8396 | n6689; - assign n7096 = Pg35 | ~Ng5567; - assign n7097 = ~Pg35 | ~n7098 | ~Ng5563; - assign n7098 = n8221 | n8397; - assign n7099 = Pg35 | ~Ng5559; - assign n7100 = ~Pg35 | ~n7101 | ~Ng5555; - assign n7101 = n8395 | n8397; - assign n7102 = Pg35 | ~Ng5551; - assign n7103 = ~Pg35 | ~n7104 | ~Ng5547; - assign n7104 = n8351 | n8397; - assign n7105 = Pg35 | ~Ng5535; - assign n7106 = ~Pg35 | ~n7107 | ~Ng5543; - assign n7107 = n8396 | n8397; - assign n7108 = (n7934 | ~Ng5272) & (n4205 | n7527); - assign n7109 = Pg35 | ~Ng5264; - assign n7110 = ~Pg35 | ~n7111 | ~Ng5220; - assign n7111 = ~Ng5176 | n8398; - assign n7112 = Pg35 | ~Ng5260; - assign n7113 = ~Pg35 | ~n6692 | ~Ng5212; - assign n7114 = Pg35 | ~Ng5256; - assign n7115 = ~Pg35 | ~n7116 | ~Ng5204; - assign n7116 = ~Ng5176 | n8399; - assign n7117 = Pg35 | ~Ng5252; - assign n7118 = ~Pg35 | ~n7119 | ~Ng5268; - assign n7119 = n8225 | n6698; - assign n7120 = Pg35 | ~Ng5248; - assign n7121 = ~Pg35 | ~n7122 | ~Ng5264; - assign n7122 = n6698 | n8398; - assign n7123 = Pg35 | ~Ng5244; - assign n7124 = n8352 | n6698; - assign n7125 = Pg35 | ~Ng5240; - assign n7126 = ~Pg35 | ~n7127 | ~Ng5256; - assign n7127 = n6698 | n8399; - assign n7128 = Pg35 | ~Ng5236; - assign n7129 = n8225 | n6700; - assign n7130 = Pg35 | ~Ng5232; - assign n7131 = n6700 | n8398; - assign n7132 = Pg35 | ~Ng5228; - assign n7133 = ~Pg35 | ~n7134 | ~Ng5244; - assign n7134 = n8352 | n6700; - assign n7135 = Pg35 | ~Ng5224; - assign n7136 = ~Pg35 | ~n7137 | ~Ng5240; - assign n7137 = n6700 | n8399; - assign n7138 = Pg35 | ~Ng5216; - assign n7139 = ~Pg35 | ~n7140 | ~Ng5236; - assign n7140 = n8225 | n6699; - assign n7141 = Pg35 | ~Ng5208; - assign n7142 = ~Pg35 | ~n7143 | ~Ng5232; - assign n7143 = n8398 | n6699; - assign n7144 = Pg35 | ~Ng5200; - assign n7145 = ~Pg35 | ~n7146 | ~Ng5228; - assign n7146 = n8352 | n6699; - assign n7147 = Pg35 | ~Ng5196; - assign n7148 = ~Pg35 | ~n7149 | ~Ng5224; - assign n7149 = n8399 | n6699; - assign n7150 = Pg35 | ~Ng5220; - assign n7151 = ~Pg35 | ~n7152 | ~Ng5216; - assign n7152 = n8225 | n8400; - assign n7153 = Pg35 | ~Ng5212; - assign n7154 = ~Pg35 | ~n7155 | ~Ng5208; - assign n7155 = n8398 | n8400; - assign n7156 = Pg35 | ~Ng5204; - assign n7157 = ~Pg35 | ~n7158 | ~Ng5200; - assign n7158 = n8352 | n8400; - assign n7159 = Pg35 | ~Ng5188; - assign n7160 = ~Pg35 | ~n7161 | ~Ng5196; - assign n7161 = n8399 | n8400; - assign n7162 = (~Ng4507 & n9239) | (~Pg113 & (~Ng4507 | ~n9239)); - assign n7163 = n7162 & Pg35; - assign n7164 = n9241 | ~Pg115 | Ng4157; - assign n7165 = ~n9241 | Pg115 | Ng4157; - assign n7166 = n9240 | ~Pg126 | Ng4146; - assign n7167 = ~n9240 | Pg126 | Ng4146; - assign n7168 = n7167 & n7164 & n7165 & n7166; - assign n7169 = ~n8325 | n7566 | ~Ng4093; - assign n7170 = ~Ng2841 | Ng4093 | n8325; - assign n7171 = (n4205 | n7568) & (~n8401 | ~Ng3965); - assign n7172 = Pg35 | ~Ng3957; - assign n7173 = ~Pg35 | ~n7174 | ~Ng3913; - assign n7174 = ~Ng3869 | n8402; - assign n7175 = Pg35 | ~Ng3953; - assign n7176 = ~Pg35 | ~n6713 | ~Ng3905; - assign n7177 = Pg35 | ~Ng3949; - assign n7178 = ~Pg35 | ~n7179 | ~Ng3897; - assign n7179 = ~Ng3869 | n8403; - assign n7180 = Pg35 | ~Ng3945; - assign n7181 = ~Pg35 | ~n7182 | ~Ng3961; - assign n7182 = n8219 | n6719; - assign n7183 = Pg35 | ~Ng3941; - assign n7184 = ~Pg35 | ~n7185 | ~Ng3957; - assign n7185 = n6719 | n8402; - assign n7186 = Pg35 | ~Ng3937; - assign n7187 = n8365 | n6719; - assign n7188 = Pg35 | ~Ng3933; - assign n7189 = ~Pg35 | ~n7190 | ~Ng3949; - assign n7190 = n6719 | n8403; - assign n7191 = Pg35 | ~Ng3929; - assign n7192 = n8219 | n6721; - assign n7193 = Pg35 | ~Ng3925; - assign n7194 = n6721 | n8402; - assign n7195 = Pg35 | ~Ng3921; - assign n7196 = ~Pg35 | ~n7197 | ~Ng3937; - assign n7197 = n8365 | n6721; - assign n7198 = Pg35 | ~Ng3917; - assign n7199 = ~Pg35 | ~n7200 | ~Ng3933; - assign n7200 = n6721 | n8403; - assign n7201 = Pg35 | ~Ng3909; - assign n7202 = ~Pg35 | ~n7203 | ~Ng3929; - assign n7203 = n8219 | n6720; - assign n7204 = Pg35 | ~Ng3901; - assign n7205 = ~Pg35 | ~n7206 | ~Ng3925; - assign n7206 = n8402 | n6720; - assign n7207 = Pg35 | ~Ng3893; - assign n7208 = ~Pg35 | ~n7209 | ~Ng3921; - assign n7209 = n8365 | n6720; - assign n7210 = Pg35 | ~Ng3889; - assign n7211 = ~Pg35 | ~n7212 | ~Ng3917; - assign n7212 = n8403 | n6720; - assign n7213 = Pg35 | ~Ng3913; - assign n7214 = ~Pg35 | ~n7215 | ~Ng3909; - assign n7215 = n8219 | n8404; - assign n7216 = Pg35 | ~Ng3905; - assign n7217 = ~Pg35 | ~n7218 | ~Ng3901; - assign n7218 = n8402 | n8404; - assign n7219 = Pg35 | ~Ng3897; - assign n7220 = ~Pg35 | ~n7221 | ~Ng3893; - assign n7221 = n8365 | n8404; - assign n7222 = Pg35 | ~Ng3881; - assign n7223 = ~Pg35 | ~n7224 | ~Ng3889; - assign n7224 = n8403 | n8404; - assign n7225 = (n4205 | n7599) & (~n8405 | ~Ng3614); - assign n7226 = Pg35 | ~Ng3606; - assign n7227 = ~Pg35 | ~n7228 | ~Ng3562; - assign n7228 = ~Ng3518 | n8406; - assign n7229 = Pg35 | ~Ng3602; - assign n7230 = ~Pg35 | ~n6723 | ~Ng3554; - assign n7231 = Pg35 | ~Ng3598; - assign n7232 = ~Pg35 | ~n7233 | ~Ng3546; - assign n7233 = ~Ng3518 | n8407; - assign n7234 = Pg35 | ~Ng3594; - assign n7235 = ~Pg35 | ~n7236 | ~Ng3610; - assign n7236 = n8224 | n6729; - assign n7237 = Pg35 | ~Ng3590; - assign n7238 = ~Pg35 | ~n7239 | ~Ng3606; - assign n7239 = n6729 | n8406; - assign n7240 = Pg35 | ~Ng3586; - assign n7241 = n8366 | n6729; - assign n7242 = Pg35 | ~Ng3582; - assign n7243 = ~Pg35 | ~n7244 | ~Ng3598; - assign n7244 = n6729 | n8407; - assign n7245 = Pg35 | ~Ng3578; - assign n7246 = ~Pg35 | ~n7247 | ~Ng3594; - assign n7247 = n8224 | n6731; - assign n7248 = Pg35 | ~Ng3574; - assign n7249 = n6731 | n8406; - assign n7250 = Pg35 | ~Ng3570; - assign n7251 = ~Pg35 | ~n7252 | ~Ng3586; - assign n7252 = n8366 | n6731; - assign n7253 = Pg35 | ~Ng3566; - assign n7254 = ~Pg35 | ~n7255 | ~Ng3582; - assign n7255 = n6731 | n8407; - assign n7256 = Pg35 | ~Ng3558; - assign n7257 = n8224 | n6730; - assign n7258 = Pg35 | ~Ng3550; - assign n7259 = ~Pg35 | ~n7260 | ~Ng3574; - assign n7260 = n8406 | n6730; - assign n7261 = Pg35 | ~Ng3542; - assign n7262 = ~Pg35 | ~n7263 | ~Ng3570; - assign n7263 = n8366 | n6730; - assign n7264 = Pg35 | ~Ng3538; - assign n7265 = ~Pg35 | ~n7266 | ~Ng3566; - assign n7266 = n8407 | n6730; - assign n7267 = Pg35 | ~Ng3562; - assign n7268 = ~Pg35 | ~n7269 | ~Ng3558; - assign n7269 = n8224 | n8408; - assign n7270 = Pg35 | ~Ng3554; - assign n7271 = ~Pg35 | ~n7272 | ~Ng3550; - assign n7272 = n8406 | n8408; - assign n7273 = Pg35 | ~Ng3546; - assign n7274 = ~Pg35 | ~n7275 | ~Ng3542; - assign n7275 = n8366 | n8408; - assign n7276 = Pg35 | ~Ng3530; - assign n7277 = ~Pg35 | ~n7278 | ~Ng3538; - assign n7278 = n8407 | n8408; - assign n7279 = (n4205 | n7628) & (~n8409 | ~Ng3263); - assign n7280 = Pg35 | ~Ng3255; - assign n7281 = ~Pg35 | ~n7282 | ~Ng3211; - assign n7282 = ~Ng3167 | n8410; - assign n7283 = Pg35 | ~Ng3251; - assign n7284 = ~Pg35 | ~n6733 | ~Ng3203; - assign n7285 = Pg35 | ~Ng3247; - assign n7286 = ~Pg35 | ~n7287 | ~Ng3195; - assign n7287 = ~Ng3167 | n8411; - assign n7288 = Pg35 | ~Ng3243; - assign n7289 = ~Pg35 | ~n7290 | ~Ng3259; - assign n7290 = n8216 | n6739; - assign n7291 = Pg35 | ~Ng3239; - assign n7292 = ~Pg35 | ~n7293 | ~Ng3255; - assign n7293 = n6739 | n8410; - assign n7294 = Pg35 | ~Ng3235; - assign n7295 = ~Pg35 | ~n7296 | ~Ng3251; - assign n7296 = n8367 | n6739; - assign n7297 = Pg35 | ~Ng3231; - assign n7298 = ~Pg35 | ~n7299 | ~Ng3247; - assign n7299 = n6739 | n8411; - assign n7300 = Pg35 | ~Ng3227; - assign n7301 = ~Pg35 | ~n7302 | ~Ng3243; - assign n7302 = n8216 | n6741; - assign n7303 = Pg35 | ~Ng3223; - assign n7304 = n6741 | n8410; - assign n7305 = Pg35 | ~Ng3219; - assign n7306 = n8367 | n6741; - assign n7307 = Pg35 | ~Ng3215; - assign n7308 = ~Pg35 | ~n7309 | ~Ng3231; - assign n7309 = n6741 | n8411; - assign n7310 = Pg35 | ~Ng3207; - assign n7311 = n8216 | n6740; - assign n7312 = Pg35 | ~Ng3199; - assign n7313 = ~Pg35 | ~n7314 | ~Ng3223; - assign n7314 = n8410 | n6740; - assign n7315 = Pg35 | ~Ng3191; - assign n7316 = ~Pg35 | ~n7317 | ~Ng3219; - assign n7317 = n8367 | n6740; - assign n7318 = Pg35 | ~Ng3187; - assign n7319 = ~Pg35 | ~n7320 | ~Ng3215; - assign n7320 = n8411 | n6740; - assign n7321 = Pg35 | ~Ng3211; - assign n7322 = ~Pg35 | ~n7323 | ~Ng3207; - assign n7323 = n8216 | n8412; - assign n7324 = Pg35 | ~Ng3203; - assign n7325 = ~Pg35 | ~n7326 | ~Ng3199; - assign n7326 = n8410 | n8412; - assign n7327 = Pg35 | ~Ng3195; - assign n7328 = ~Pg35 | ~n7329 | ~Ng3191; - assign n7329 = n8367 | n8412; - assign n7330 = Pg35 | ~Ng3179; - assign n7331 = ~Pg35 | ~n7332 | ~Ng3187; - assign n7332 = n8411 | n8412; - assign n7333 = n9246 | ~Pg35 | n9245; - assign n7334 = n9250 | ~Pg35 | n9249; - assign n7335 = n8106 ^ Ng2741; - assign n7336 = ~Pg35 | ~Ng2841; - assign n7337 = Ng2681 | Ng2675 | ~n8414; - assign n7338 = ~Pg35 | n8413; - assign n7339 = (~n8414 & ~Ng2661) | (n7338 & (~n8414 | Ng2661)); - assign n7340 = n8415 | n8107 | n8369; - assign n7341 = n8369 | n8264 | n8205; - assign n7342 = Ng2547 | Ng2541 | ~n8418; - assign n7343 = ~Pg35 | n8417; - assign n7344 = (~Ng2527 & ~n8418) | (n7343 & (Ng2527 | ~n8418)); - assign n7345 = n8419 | n8108 | n8371; - assign n7346 = n8371 | n8271 | n8203; - assign n7347 = Ng2413 | Ng2407 | ~n8421; - assign n7348 = ~Pg35 | n8420; - assign n7349 = (~n8421 & ~Ng2393) | (n7348 & (~n8421 | Ng2393)); - assign n7350 = n8422 | n8109 | n8372; - assign n7351 = n8372 | n8278 | n8204; - assign n7352 = Ng2279 | Ng2273 | ~n8424; - assign n7353 = ~Pg35 | n8423; - assign n7354 = (~n8424 & ~Ng2259) | (n7353 & (~n8424 | Ng2259)); - assign n7355 = n8425 | n8110 | n8374; - assign n7356 = n8374 | n8286 | n8197; - assign n7357 = Ng2122 | Ng2116 | ~n8428; - assign n7358 = ~Pg35 | n8427; - assign n7359 = (~Ng2102 & ~n8428) | (n7358 & (Ng2102 | ~n8428)); - assign n7360 = n8429 | n8111 | n8375; - assign n7361 = n8375 | n8294 | n8201; - assign n7362 = Ng1988 | Ng1982 | ~n8431; - assign n7363 = ~Pg35 | n8430; - assign n7364 = (~Ng1968 & ~n8431) | (n7363 & (Ng1968 | ~n8431)); - assign n7365 = n8432 | n8112 | n8376; - assign n7366 = n8376 | n8301 | n8202; - assign n7367 = Ng1854 | Ng1848 | ~n8434; - assign n7368 = ~Pg35 | n8433; - assign n7369 = (~n8434 & ~Ng1834) | (n7368 & (~n8434 | Ng1834)); - assign n7370 = n8435 | n8113 | n8377; - assign n7371 = n8377 | n8307 | n8199; - assign n7372 = Ng1720 | Ng1714 | ~n8437; - assign n7373 = ~Pg35 | n8436; - assign n7374 = (~n8437 & ~Ng1700) | (n7373 & (~n8437 | Ng1700)); - assign n7375 = n8438 | n8114 | n8378; - assign n7376 = ~n8207 & ~n8378 & (~Ng1636 | Ng1592); - assign n7377 = ~n5559 & (~Ng1526 | ~n7379); - assign n7378 = (n7377 & (Pg35 | ~Ng1514)) | (~Pg35 & ~Ng1514); - assign n7379 = ~Pg7946 | ~Ng1514; - assign n7380 = ~Ng1361 | ~Pg35 | n6632; - assign n7381 = n7814 | ~n6632 | Ng1361; - assign n7382 = ~Ng1259 | ~n7384 | n8005; - assign n7383 = Pg35 | ~Ng1256; - assign n7384 = ~Ng1256 | ~n8335; - assign n7385 = n8083 & Ng1024 & Ng1002 & Ng1036; - assign n7386 = n7385 | Ng1008 | Ng969; - assign n7387 = ~n4474 & (~Ng1183 | ~n7389); - assign n7388 = (Pg35 & n7387) | (~Ng1171 & (~Pg35 | n7387)); - assign n7389 = ~Pg7916 | ~Ng1171; - assign n7390 = ~Ng1018 | ~Pg35 | n6639; - assign n7391 = n7819 | ~n6639 | Ng1018; - assign n7392 = ~Ng914 | ~n7394 | n8014; - assign n7393 = Pg35 | ~Ng911; - assign n7394 = ~Ng911 | ~n8341; - assign n7395 = ~Ng744 | ~n7397 | n7743; - assign n7396 = Pg35 | ~Ng739; - assign n7397 = ~n6091_1 | ~Ng739 | n8180; - assign n7398 = ~Ng577 | ~n7400 | n8183; - assign n7399 = Pg35 | ~Ng586; - assign n7400 = ~Ng586 | n7754; - assign n7401 = ~n4520 ^ Ng146; - assign n7402 = ~Pg35 | n8246; - assign n7403 = ~Ng6541 | ~n8381 | ~n8382; - assign n7404 = ~Ng6561 | n8222; - assign n7405 = (n7407 & (n8441 | Ng6527)) | (n8441 & ~Ng6527); - assign n7406 = Ng6519 | Ng6513 | n8441; - assign n7407 = ~Pg35 | ~n8440; - assign n7408 = ~Ng6505 | Ng6500 | n8441; - assign n7409 = (~Pg13099 | ~Ng6593) & (~Ng6605 | ~Ng6723); - assign n7410 = (~Pg17764 | ~Ng6649) & (~Pg17722 | ~Ng6597); - assign n7411 = (~Pg17871 | ~Ng6617) & (~Pg12470 | ~Ng6601); - assign n7412 = ~Ng6633 | ~Pg14749 | n7423; - assign n7413 = (n7410 | n6496) & (n7409 | n7426); - assign n7414 = ~Ng6741 | ~Ng6682; - assign n7415 = n7412 & n7413 & (n7411 | n7414); - assign n7416 = (~Pg13099 | ~Ng6581) & (~Ng6589 | ~Ng6723); - assign n7417 = (~Pg17871 | ~Ng6609) & (~Pg12470 | ~Ng6585); - assign n7418 = ~Ng6641 | ~Pg17764 | n7414; - assign n7419 = ~Ng6625 | ~Pg14749 | n7426; - assign n7420 = (n7417 | n6496) & (n7416 | n7423); - assign n7421 = n7418 & n7419 & n7420; - assign n7422 = n9123 & (~Pg17778 | n6496 | ~Ng6637); - assign n7423 = Ng6682 | Ng6741; - assign n7424 = n7422 & (~Pg14828 | n7423 | ~Ng6621); - assign n7425 = n9122 & (~Pg17778 | n7414 | ~Ng6629); - assign n7426 = Ng6741 | ~Ng6682; - assign n7427 = n7425 & (~Pg14828 | n7426 | ~Ng6613); - assign n7428 = (n7421 & Ng6727) | (n7415 & (n7421 | ~Ng6727)); - assign n7429 = (n7427 & n9279) | (n7424 & (n7427 | ~n9279)); - assign n7430 = ~Ng6727 | ~Pg17722 | n7414; - assign n7431 = n7428 & n7429 & (n7430 | ~Ng6657); - assign n7432 = Pg35 | ~Ng6505; - assign n7433 = ~Pg35 | ~n5884_1 | n7431; - assign n7434 = ~Ng6195 | ~n8382 | ~n8386; - assign n7435 = ~Ng6215 | n8217; - assign n7436 = (n7438 & (n8443 | Ng6181)) | (n8443 & ~Ng6181); - assign n7437 = Ng6173 | Ng6167 | n8443; - assign n7438 = ~Pg35 | ~n8442; - assign n7439 = ~Ng6159 | Ng6154 | n8443; - assign n7440 = (~Pg17743 | ~Ng6303) & (~Pg17685 | ~Ng6251); - assign n7441 = (~Pg13085 | ~Ng6247) & (~Ng6259 | ~Ng6377); - assign n7442 = (~Pg17845 | ~Ng6271) & (~Pg12422 | ~Ng6255); - assign n7443 = ~Ng6287 | ~Pg14705 | n7457; - assign n7444 = (n7441 | n7454) & (n7440 | n6502_1); - assign n7445 = ~Ng6395 | ~Ng6336; - assign n7446 = n7443 & n7444 & (n7442 | n7445); - assign n7447 = (~Pg13085 | ~Ng6235) & (~Ng6243 | ~Ng6377); - assign n7448 = (~Pg17845 | ~Ng6263) & (~Pg12422 | ~Ng6239); - assign n7449 = ~Ng6295 | ~Pg17743 | n7445; - assign n7450 = ~Ng6279 | ~Pg14705 | n7454; - assign n7451 = (n7448 | n6502_1) & (n7447 | n7457); - assign n7452 = n7449 & n7450 & n7451; - assign n7453 = n9125 & (~Pg17760 | n6502_1 | ~Ng6291); - assign n7454 = Ng6395 | ~Ng6336; - assign n7455 = n7453 & (~Pg17649 | n7454 | ~Ng6307); - assign n7456 = n9124 & (~Pg14779 | n7454 | ~Ng6267); - assign n7457 = Ng6336 | Ng6395; - assign n7458 = n7456 & (~Pg17649 | n7457 | ~Ng6299); - assign n7459 = (n7452 & Ng6381) | (n7446 & (n7452 | ~Ng6381)); - assign n7460 = (n7458 & n9283) | (n7455 & (n7458 | ~n9283)); - assign n7461 = ~Ng6381 | ~Pg17685 | n7445; - assign n7462 = n7459 & n7460 & (n7461 | ~Ng6311); - assign n7463 = Pg35 | ~Ng6159; - assign n7464 = ~Pg35 | ~n5952 | n7462; - assign n7465 = ~Ng5849 | ~n8382 | ~n8390; - assign n7466 = ~Ng5869 | n8223; - assign n7467 = (n7469 & (n8445 | Ng5835)) | (n8445 & ~Ng5835); - assign n7468 = Ng5827 | Ng5821 | n8445; - assign n7469 = ~Pg35 | ~n8444; - assign n7470 = ~Ng5813 | Ng5808 | n8445; - assign n7471 = (~Pg13068 | ~Ng5901) & (~Ng5913 | ~Ng6031); - assign n7472 = (~Pg17715 | ~Ng5957) & (~Pg17646 | ~Ng5905); - assign n7473 = (~Pg17819 | ~Ng5925) & (~Pg12350 | ~Ng5909); - assign n7474 = ~Ng5941 | ~Pg14673 | n7485; - assign n7475 = (n7472 | n6508) & (n7471 | n7488); - assign n7476 = ~Ng6049 | ~Ng5990; - assign n7477 = n7474 & n7475 & (n7473 | n7476); - assign n7478 = (~Pg13068 | ~Ng5889) & (~Ng5897 | ~Ng6031); - assign n7479 = (~Pg17819 | ~Ng5917) & (~Pg12350 | ~Ng5893); - assign n7480 = ~Ng5933 | ~Pg14673 | n7488; - assign n7481 = ~Ng5949 | ~Pg17715 | n7476; - assign n7482 = (n7479 | n6508) & (n7478 | n7485); - assign n7483 = n7480 & n7481 & n7482; - assign n7484 = n9127 & (~Pg17739 | n6508 | ~Ng5945); - assign n7485 = Ng5990 | Ng6049; - assign n7486 = n7484 & (~Pg14738 | n7485 | ~Ng5929); - assign n7487 = n9126 & (~Pg17739 | n7476 | ~Ng5937); - assign n7488 = Ng6049 | ~Ng5990; - assign n7489 = n7487 & (~Pg14738 | n7488 | ~Ng5921); - assign n7490 = (n7483 & Ng6035) | (n7477 & (n7483 | ~Ng6035)); - assign n7491 = (n7489 & n9287) | (n7486 & (n7489 | ~n9287)); - assign n7492 = ~Ng6035 | ~Pg17646 | n7476; - assign n7493 = n7490 & n7491 & (n7492 | ~Ng5965); - assign n7494 = Pg35 | ~Ng5813; - assign n7495 = ~Pg35 | ~n5940 | n7493; - assign n7496 = ~Ng5503 | ~n8382 | ~n8394; - assign n7497 = ~Ng5523 | n8221; - assign n7498 = (n7500 & (n8447 | Ng5489)) | (n8447 & ~Ng5489); - assign n7499 = Ng5481 | Ng5475 | n8447; - assign n7500 = ~Pg35 | ~n8446; - assign n7501 = Ng5462 | n8447 | ~Ng5467; - assign n7502 = (~Pg17678 | ~Ng5611) & (~Pg17604 | ~Ng5559); - assign n7503 = (~Pg13049 | ~Ng5555) & (~Ng5567 | ~Ng5685); - assign n7504 = (~Pg17813 | ~Ng5579) & (~Pg12300 | ~Ng5563); - assign n7505 = ~Ng5595 | ~Pg14635 | n7516; - assign n7506 = (n7503 | n7519) & (n7502 | n8321); - assign n7507 = ~Ng5703 | ~Ng5644; - assign n7508 = n7505 & n7506 & (n7504 | n7507); - assign n7509 = (~Pg17813 | ~Ng5571) & (~Pg12300 | ~Ng5547); - assign n7510 = (~Pg13049 | ~Ng5543) & (~Ng5551 | ~Ng5685); - assign n7511 = ~Ng5603 | ~Pg17678 | n7507; - assign n7512 = ~Ng5587 | ~Pg14635 | n7519; - assign n7513 = (n7510 | n7516) & (n7509 | n8321); - assign n7514 = n7511 & n7512 & n7513; - assign n7515 = n9129 & (~Pg17711 | n8321 | ~Ng5599); - assign n7516 = Ng5644 | Ng5703; - assign n7517 = n7515 & (~Pg14694 | n7516 | ~Ng5583); - assign n7518 = n9128 & (~Pg17711 | n7507 | ~Ng5591); - assign n7519 = Ng5703 | ~Ng5644; - assign n7520 = n7518 & (~Pg14694 | n7519 | ~Ng5575); - assign n7521 = (n7514 & Ng5689) | (n7508 & (n7514 | ~Ng5689)); - assign n7522 = (n7520 & n9291) | (n7517 & (n7520 | ~n9291)); - assign n7523 = ~Ng5689 | ~Pg17604 | n7507; - assign n7524 = n7521 & n7522 & (n7523 | ~Ng5619); - assign n7525 = n8322 | Ng5462 | n7524; - assign n7526 = ~n8382 | ~Ng5156 | n7934; - assign n7527 = ~Ng5176 | n8225; - assign n7528 = (n7530 & (n8450 | Ng5142)) | (n8450 & ~Ng5142); - assign n7529 = Ng5134 | Ng5128 | n8450; - assign n7530 = ~Pg35 | ~n8449; - assign n7531 = ~Ng5120 | Ng5115 | n8450; - assign n7532 = (~Pg17787 | ~Ng5232) & (~Pg12238 | ~Ng5216); - assign n7533 = (~Pg13039 | ~Ng5208) & (~Ng5220 | ~Ng5339); - assign n7534 = (~Pg17639 | ~Ng5264) & (~Pg17577 | ~Ng5212); - assign n7535 = ~Ng5248 | ~Pg14597 | n7545; - assign n7536 = (n7533 | n7548) & (n7532 | n8192); - assign n7537 = n7535 & n7536 & (n7534 | n6516); - assign n7538 = (~Pg17787 | ~Ng5224) & (~Pg12238 | ~Ng5200); - assign n7539 = (~Pg13039 | ~Ng5196) & (~Ng5204 | ~Ng5339); - assign n7540 = ~Ng5240 | ~Pg14597 | n7548; - assign n7541 = ~Ng5256 | ~Pg17639 | n8192; - assign n7542 = (n7539 | n7545) & (n7538 | n6516); - assign n7543 = n7540 & n7541 & n7542; - assign n7544 = n9131 & (~Pg17519 | n7548 | ~Ng5268); - assign n7545 = Ng5297 | Ng5357; - assign n7546 = n7544 & (~Pg14662 | n7545 | ~Ng5236); - assign n7547 = n9130 & (~Pg17674 | n8192 | ~Ng5244); - assign n7548 = Ng5357 | ~Ng5297; - assign n7549 = n7547 & (~Pg14662 | n7548 | ~Ng5228); - assign n7550 = (n7537 & (~\[4415] | n7543)) | (\[4415] & n7543); - assign n7551 = (n7549 & n9295) | (n7546 & (n7549 | ~n9295)); - assign n7552 = n7550 & n7551 & (~Ng5272 | ~n8448); - assign n7553 = Pg35 | ~Ng5120; - assign n7554 = ~Pg35 | ~n4151_1 | n7552; - assign n7555 = n5907 & n5888 & (Ng4927 | n5926); - assign n7556 = Ng4975 | ~Ng4912 | Ng4899; - assign n7557 = (n5888 | ~Ng4922) & (n5926 | ~Ng4917); - assign n7558 = n7556 & n7557 & (n5907 | ~Ng4907); - assign n7559 = ~Ng4966 & (~n5935 | ~Ng4983) & ~n9297; - assign n7560 = n5939 & n5874_1 & (Ng4737 | n5951); - assign n7561 = Ng4785 | ~Ng4722 | Ng4709; - assign n7562 = (n5874_1 | ~Ng4717) & (n5951 | ~Ng4727); - assign n7563 = n7561 & n7562 & (n5939 | ~Ng4732); - assign n7564 = ~Ng4776 & (~n5949 | ~Ng4793) & ~n9299; - assign n7565 = n8121 ^ Ng4087; - assign n7566 = ~Pg35 | ~Ng2841; - assign n7567 = ~Ng3849 | ~n8382 | ~n8401; - assign n7568 = ~Ng3869 | n8219; - assign n7569 = (n7571 & (n8452 | Ng3835)) | (n8452 & ~Ng3835); - assign n7570 = Ng3827 | Ng3821 | n8452; - assign n7571 = ~Pg35 | ~n8451; - assign n7572 = ~Ng3813 | Ng3808 | n8452; - assign n7573 = (~Pg14518 | ~Ng3901) & (~Ng3913 | ~Ng4031); - assign n7574 = (~Pg16748 | ~Ng3957) & (~Pg16693 | ~Ng3905); - assign n7575 = (~Pg16955 | ~Ng3925) & (~Pg11418 | ~Ng3909); - assign n7576 = ~Ng3941 | ~Pg13906 | n7587; - assign n7577 = (n7574 | n6525) & (n7573 | n7590); - assign n7578 = ~Ng4054 | ~Ng3990; - assign n7579 = n7576 & n7577 & (n7575 | n7578); - assign n7580 = (~Pg16955 | ~Ng3917) & (~Pg11418 | ~Ng3893); - assign n7581 = (~Pg14518 | ~Ng3889) & (~Ng3897 | ~Ng4031); - assign n7582 = ~Ng3949 | ~Pg16748 | n7578; - assign n7583 = ~Ng3933 | ~Pg13906 | n7590; - assign n7584 = (n7581 | n7587) & (n7580 | n6525); - assign n7585 = n7582 & n7583 & n7584; - assign n7586 = n9137 & (~Pg16659 | n7590 | ~Ng3961); - assign n7587 = Ng3990 | Ng4054; - assign n7588 = n7586 & (~Pg13966 | n7587 | ~Ng3929); - assign n7589 = n9136 & (~Pg16775 | n7578 | ~Ng3937); - assign n7590 = Ng4054 | ~Ng3990; - assign n7591 = n7589 & (~Pg13966 | n7590 | ~Ng3921); - assign n7592 = (n7585 & Ng4040) | (n7579 & (n7585 | ~Ng4040)); - assign n7593 = (n7591 & n9303) | (n7588 & (n7591 | ~n9303)); - assign n7594 = ~Ng4040 | ~Pg16693 | n7578; - assign n7595 = n7592 & n7593 & (n7594 | ~Ng3965); - assign n7596 = Pg35 | ~Ng3813; - assign n7597 = ~Pg35 | ~n5927 | n7595; - assign n7598 = ~Ng3498 | ~n8382 | ~n8405; - assign n7599 = ~Ng3518 | n8224; - assign n7600 = (n7602 & (n8454 | Ng3484)) | (n8454 & ~Ng3484); - assign n7601 = Ng3476 | Ng3470 | n8454; - assign n7602 = ~Pg35 | ~n8453; - assign n7603 = ~Ng3462 | Ng3457 | n8454; - assign n7604 = (~Pg16924 | ~Ng3574) & (~Pg11388 | ~Ng3558); - assign n7605 = (~Pg14451 | ~Ng3550) & (~Ng3562 | ~Ng3680); - assign n7606 = (~Pg16722 | ~Ng3606) & (~Pg16656 | ~Ng3554); - assign n7607 = ~Ng3590 | ~Pg13881 | n8455; - assign n7608 = (n7605 | n8327) & (n7604 | n7619); - assign n7609 = n7607 & n7608 & (n7606 | n6531_1); - assign n7610 = (~Pg14451 | ~Ng3538) & (~Ng3546 | ~Ng3680); - assign n7611 = (~Pg16924 | ~Ng3566) & (~Pg11388 | ~Ng3542); - assign n7612 = ~Ng3582 | ~Pg13881 | n8327; - assign n7613 = ~Ng3598 | ~Pg16722 | n7619; - assign n7614 = (n7611 | n6531_1) & (n7610 | n8455); - assign n7615 = n7612 & n7613 & n7614; - assign n7616 = n9139 & (~Pg16627 | n8327 | ~Ng3610); - assign n7617 = n7616 & (~Pg16744 | n6531_1 | ~Ng3594); - assign n7618 = n9138 & (~Pg13926 | n8327 | ~Ng3570); - assign n7619 = ~Ng3703 | ~Ng3639; - assign n7620 = n7618 & (~Pg16744 | n7619 | ~Ng3586); - assign n7621 = (n7615 & Ng3689) | (n7609 & (n7615 | ~Ng3689)); - assign n7622 = (n7620 & n9307) | (n7617 & (n7620 | ~n9307)); - assign n7623 = ~Ng3689 | ~Pg16656 | n7619; - assign n7624 = n7621 & n7622 & (n7623 | ~Ng3614); - assign n7625 = Pg35 | ~Ng3462; - assign n7626 = ~Pg35 | ~n5889 | n7624; - assign n7627 = ~Ng3147 | ~n8382 | ~n8409; - assign n7628 = ~Ng3167 | n8216; - assign n7629 = (n7631 & (n8457 | Ng3133)) | (n8457 & ~Ng3133); - assign n7630 = Ng3125 | Ng3119 | n8457; - assign n7631 = ~Pg35 | ~n8456; - assign n7632 = Ng3106 | n8457 | ~Ng3111; - assign n7633 = (~Pg16686 | ~Ng3255) & (~Pg16624 | ~Ng3203); - assign n7634 = (~Pg16874 | ~Ng3223) & (~Pg11349 | ~Ng3207); - assign n7635 = (~Pg14421 | ~Ng3199) & (~Ng3211 | ~Ng3329); - assign n7636 = ~Ng3239 | ~Pg13865 | n7649; - assign n7637 = (n7634 | n8189) & (n7633 | n6537); - assign n7638 = Ng3352 | ~Ng3288; - assign n7639 = n7636 & n7637 & (n7635 | n7638); - assign n7640 = (~Pg16874 | ~Ng3215) & (~Pg11349 | ~Ng3191); - assign n7641 = (~Pg14421 | ~Ng3187) & (~Ng3195 | ~Ng3329); - assign n7642 = ~Ng3247 | ~Pg16686 | n8189; - assign n7643 = ~Ng3231 | ~Pg13865 | n7638; - assign n7644 = (n7641 | n7649) & (n7640 | n6537); - assign n7645 = n7642 & n7643 & n7644; - assign n7646 = n9141 & (~Pg16718 | n6537 | ~Ng3243); - assign n7647 = n7646 & (~Pg16603 | n7638 | ~Ng3259); - assign n7648 = n9140 & (~Pg13895 | n7638 | ~Ng3219); - assign n7649 = Ng3288 | Ng3352; - assign n7650 = n7648 & (~Pg16603 | n7649 | ~Ng3251); - assign n7651 = (n7645 & Ng3338) | (n7639 & (n7645 | ~Ng3338)); - assign n7652 = (n7650 & n9311) | (n7647 & (n7650 | ~n9311)); - assign n7653 = ~Ng3338 | ~Pg16624 | n8189; - assign n7654 = n7651 & n7652 & (n7653 | ~Ng3263); - assign n7655 = n8328 | Ng3106 | n7654; - assign n7656 = n9313 & (~Pg35 | ~Ng2735 | ~n7657); - assign n7657 = ~Ng2729 | n8256; - assign n7658 = n5920 & (~n7659 | ~n8415); - assign n7659 = ~Ng2638 | ~Ng2652 | ~n8415; - assign n7660 = Ng2638 & (~Pg35 | (n5920 & n7659)); - assign n7661 = (~Ng2619 | ~Ng2571) & (~Ng2579 | ~Ng2587); - assign n7662 = Ng2587 | Ng2619 | ~Ng2575; - assign n7663 = (n8205 | ~Ng2583) & (~Ng2563 | n8415); - assign n7664 = n7662 & n7663 & (Ng2610 | n7661); - assign n7665 = n6745 | ~Ng2638; - assign n7666 = (Pg35 | ~Ng2619) & (n7664 | n8369); - assign n7667 = n5919 & (~n7668 | ~n8419); - assign n7668 = ~Ng2504 | ~Ng2518 | ~n8419; - assign n7669 = Ng2504 & (~Pg35 | (n5919 & n7668)); - assign n7670 = (~Ng2485 | ~Ng2437) & (~Ng2445 | ~Ng2453); - assign n7671 = Ng2453 | Ng2485 | ~Ng2441; - assign n7672 = (n8203 | ~Ng2449) & (~Ng2429 | n8419); - assign n7673 = n7671 & n7672 & (Ng2476 | n7670); - assign n7674 = n6755 | ~Ng2504; - assign n7675 = (Pg35 | ~Ng2485) & (n7673 | n8371); - assign n7676 = n8422 & Ng2384 & Ng2370; - assign n7677 = n5925 & (n7676 | ~n8422); - assign n7678 = Ng2370 & (~Pg35 | (n5925 & ~n7676)); - assign n7679 = (~Ng2351 | ~Ng2303) & (~Ng2311 | ~Ng2319); - assign n7680 = Ng2319 | Ng2351 | ~Ng2307; - assign n7681 = (n8204 | ~Ng2315) & (~Ng2295 | n8422); - assign n7682 = n7680 & n7681 & (Ng2342 | n7679); - assign n7683 = n6765 | ~Ng2370; - assign n7684 = (Pg35 | ~Ng2351) & (n7682 | n8372); - assign n7685 = n8425 & Ng2250 & Ng2236; - assign n7686 = n5878 & (n7685 | ~n8425); - assign n7687 = Ng2236 & (~Pg35 | (n5878 & ~n7685)); - assign n7688 = (~Ng2217 | ~Ng2169) & (~Ng2177 | ~Ng2185); - assign n7689 = Ng2185 | Ng2217 | ~Ng2173; - assign n7690 = (n8197 | ~Ng2181) & (~Ng2161 | n8425); - assign n7691 = n7689 & n7690 & (Ng2208 | n7688); - assign n7692 = n6775 | ~Ng2236; - assign n7693 = (Pg35 | ~Ng2217) & (n7691 | n8374); - assign n7694 = n8429 & Ng2093 & Ng2079; - assign n7695 = n5916 & (n7694 | ~n8429); - assign n7696 = Ng2079 & (~Pg35 | (n5916 & ~n7694)); - assign n7697 = (~Ng2060 | ~Ng2012) & (~Ng2020 | ~Ng2028); - assign n7698 = Ng2028 | Ng2060 | ~Ng2016; - assign n7699 = (n8201 | ~Ng2024) & (~Ng2004 | n8429); - assign n7700 = n7698 & n7699 & (Ng2051 | n7697); - assign n7701 = n6785 | ~Ng2079; - assign n7702 = (Pg35 | ~Ng2060) & (n7700 | n8375); - assign n7703 = n8432 & Ng1959 & Ng1945; - assign n7704 = n5899 & (n7703 | ~n8432); - assign n7705 = Ng1945 & (~Pg35 | (n5899 & ~n7703)); - assign n7706 = (~Ng1926 | ~Ng1878) & (~Ng1886 | ~Ng1894); - assign n7707 = Ng1894 | Ng1926 | ~Ng1882; - assign n7708 = (n8202 | ~Ng1890) & (~Ng1870 | n8432); - assign n7709 = n7707 & n7708 & (Ng1917 | n7706); - assign n7710 = n6795 | ~Ng1945; - assign n7711 = (Pg35 | ~Ng1926) & (n7709 | n8376); - assign n7712 = n5941 & (~n7713 | ~n8435); - assign n7713 = ~Ng1811 | ~Ng1825 | ~n8435; - assign n7714 = Ng1811 & (~Pg35 | (n5941 & n7713)); - assign n7715 = (~Ng1792 | ~Ng1744) & (~Ng1752 | ~Ng1760); - assign n7716 = Ng1760 | Ng1792 | ~Ng1748; - assign n7717 = (n8199 | ~Ng1756) & (~Ng1736 | n8435); - assign n7718 = n7716 & n7717 & (Ng1783 | n7715); - assign n7719 = n6805 | ~Ng1811; - assign n7720 = (Pg35 | ~Ng1792) & (n7718 | n8377); - assign n7721 = n5868 & (~n7722 | ~n8438); - assign n7722 = ~Ng1677 | ~Ng1691 | ~n8438; - assign n7723 = Ng1677 & (~Pg35 | (n5868 & n7722)); - assign n7724 = (~Ng1657 | ~Ng1608) & (~Ng1616 | ~Ng1624); - assign n7725 = Ng1624 | Ng1657 | ~Ng1612; - assign n7726 = (n8207 | ~Ng1620) & (~Ng1600 | n8438); - assign n7727 = n7725 & n7726 & (Ng1648 | n7724); - assign n7728 = n6815 | ~Ng1677; - assign n7729 = (Pg35 | ~Ng1657) & (n7727 | n8378); - assign n7730 = (Pg35 & ~n8771) | (~Ng1472 & (~Pg35 | ~n8771)); - assign n7731 = ~Pg35 | n5170; - assign n7732 = n8335 | ~Ng1256 | n8005; - assign n7733 = Pg35 | ~Ng1252; - assign n7734 = (Pg35 & ~n8779) | (~Ng1129 & (~Pg35 | ~n8779)); - assign n7735 = ~Pg35 | n4887; - assign n7736 = n8341 | ~Ng911 | n8014; - assign n7737 = Pg35 | ~Ng907; - assign n7738 = ~Ng847 | ~Ng812; - assign n7739 = n7738 & (Ng837 | ~Ng847); - assign n7740 = ~n7739 | ~n9326 | Ng723; - assign n7741 = ~Ng723 | n7904 | n9326; - assign n7742 = ~n6091_1 ^ Ng739; - assign n7743 = ~Pg35 | n8180; - assign n7744 = ~Ng699 | ~Ng681 | n8465 | Ng645 | n8466 | Ng650; - assign n7745 = Ng703 & (n7744 | ~n8122); - assign n7746 = n9327 | ~n7745 | Ng714; - assign n7747 = ~n9327 | n7751 | ~Ng714; - assign n7748 = ~n8467 | ~n7745 | Ng676; - assign n7749 = n8467 | n7751 | ~Ng676; - assign n7750 = ~n8122 ^ Ng671; - assign n7751 = ~Pg35 | ~n7745; - assign n7752 = ~Ng586 | ~n7754 | n8183; - assign n7753 = Pg35 | ~Ng572; - assign n7754 = ~Ng572 | n7831; - assign n7755 = ~Pg35 | n8468; - assign n7756 = n9328 & (~Pg35 | ~Ng490 | n8470); - assign n7757 = Ng417 | n9329 | n8027; - assign n7758 = ~Pg35 | ~n7976; - assign n7759 = n6500 | ~Ng5011; - assign n7760 = n6506 | ~Ng4826; - assign n7761 = n6512_1 | ~Ng4831; - assign n7762 = (n7791 | ~Ng4821) & (n7524 | n8322); - assign n7763 = ~\[4427] | n6520; - assign n7764 = (n7578 & Ng4049) | (n6525 & (n7578 | ~Ng4049)); - assign n7765 = (n7587 & (~Ng4045 | n7590)) | (Ng4045 & n7590); - assign n7766 = ~Ng4961 & (~n5927 | (n7764 & n7765)); - assign n7767 = n6529 | ~Ng4961; - assign n7768 = n8211 | n5888; - assign n7769 = (~Ng3694 & n8455) | (n8327 & (Ng3694 | n8455)); - assign n7770 = (n7619 & Ng3698) | (n6531_1 & (n7619 | ~Ng3698)); - assign n7771 = ~Ng4950 & (~n5889 | (n7769 & n7770)); - assign n7772 = n6535 | ~Ng4950; - assign n7773 = n8211 | n5907; - assign n7774 = n8211 | Ng4975 | Ng4899; - assign n7775 = ~Pg35 | n5908; - assign n7776 = (n7423 & (~Ng6732 | n7426)) | (Ng6732 & n7426); - assign n7777 = (n7414 & Ng6736) | (n6496 & (n7414 | ~Ng6736)); - assign n7778 = ~Ng4894 & (~n5884_1 | (n7776 & n7777)); - assign n7779 = n6500 | ~Ng4894; - assign n7780 = (~Ng6386 & n7457) | (n7454 & (Ng6386 | n7457)); - assign n7781 = (n7445 & Ng6390) | (n6502_1 & (n7445 | ~Ng6390)); - assign n7782 = ~Ng4771 & (~n5952 | (n7780 & n7781)); - assign n7783 = n6506 | ~Ng4771; - assign n7784 = n8209 | n5939; - assign n7785 = (n7485 & (~Ng6040 | n7488)) | (Ng6040 & n7488); - assign n7786 = (n7476 & Ng6044) | (n6508 & (n7476 | ~Ng6044)); - assign n7787 = ~Ng4760 & (~n5940 | (n7785 & n7786)); - assign n7788 = n6512_1 | ~Ng4760; - assign n7789 = n8209 | n5874_1; - assign n7790 = n8209 | Ng4785 | Ng4709; - assign n7791 = ~Pg35 | n5876; - assign n7792 = (n8192 & Ng5352) | (n6516 & (n8192 | ~Ng5352)); - assign n7793 = (n7545 & (~Ng5348 | n7548)) | (Ng5348 & n7548); - assign n7794 = ~Ng4704 & (~n4151_1 | (n7792 & n7793)); - assign n7795 = n6520 | ~Ng4704; - assign n7796 = n5951 | n8209; - assign n7797 = Pg35 & (Ng4057 | Ng4064 | ~n8471); - assign n7798 = Pg35 | ~Ng4119; - assign n7799 = ~Pg35 | ~n7800 | ~Ng4122; - assign n7800 = n8323 | ~n8471; - assign n7801 = ~Pg35 | ~Ng4145; - assign n7802 = Pg35 | ~Ng4116; - assign n7803 = ~Ng4119 | ~Pg35 | n8472; - assign n7804 = Pg35 | ~Ng4112; - assign n7805 = ~Ng4116 | ~Pg35 | n8473; - assign n7806 = n9336 & (~Pg35 | ~Ng4076 | ~n7807); - assign n7807 = ~n8324 | ~Ng4082; - assign n7808 = n6529 | ~Ng4035; - assign n7809 = n6535 | ~Ng3684; - assign n7810 = (n7775 | ~Ng3333) & (n7654 | n8328); - assign n7811 = Pg35 | ~Ng2724; - assign n7812 = n8256 ^ Ng2729; - assign n7813 = n9337 & (~Pg35 | n6631 | ~Ng1345); - assign n7814 = ~Pg35 | ~n8333; - assign n7815 = ~Ng1252 | ~n7817 | n8005; - assign n7816 = Pg35 | ~Ng1280; - assign n7817 = n8334 | ~Ng1280; - assign n7818 = n9338 & (~Pg35 | n6638_1 | ~Ng1002); - assign n7819 = ~Pg35 | ~n8339; - assign n7820 = ~Ng907 | ~n7822 | n8014; - assign n7821 = Pg35 | ~Ng936; - assign n7822 = n8340 | ~Ng936; - assign n7823 = n8464 | ~n7739 | Ng827; - assign n7824 = ~n8464 | n7904 | ~Ng827; - assign n7825 = n7758 | ~Ng699; - assign n7826 = ~Pg35 | n8474; - assign n7827 = (n7826 | ~Ng681) & (~Ng650 | ~n8475); - assign n7828 = ~n7986 & (~Ng703 | Ng714); - assign n7829 = ~Ng572 | ~n7831 | n8183; - assign n7830 = Pg35 | ~Ng568; - assign n7831 = ~Ng568 | n7909; - assign n7832 = Pg35 | ~Ng528; - assign n7833 = ~n5934 ^ Ng482; - assign n7834 = ~Pg35 | ~n8241; - assign n7835 = n5881 | n5885; - assign n7836 = n7835 & (n5918 | (n5881 & n5885)); - assign n7837 = ~n5905 & n5877 & ~n5902; - assign n7838 = ~n8212 & (n5877 | (~n5902 & ~n5905)); - assign n7839 = Ng4531 & Ng4581; - assign n7840 = Pg10306 & Pg35; - assign n7841 = ~Pg35 | ~Ng4515 | ~Ng4521; - assign n7842 = n7853 | Ng4392 | Ng4417; - assign n7843 = (~Pg35 | n7842) & (~Ng4392 | ~n8479); - assign n7844 = Ng4452 | Ng4438 | Ng4443 | Pg7245 | Pg7260; - assign n7845 = Pg35 & (~Ng4392 | n7844); - assign n7846 = ~Pg35 | Ng4392; - assign n7847 = ~Pg35 | ~Ng4392 | n7844; - assign n7848 = Pg35 | ~Ng4443; - assign n7849 = ~Ng4438 | ~Pg35 | Ng4382; - assign n7850 = Ng4401 ^ Ng4434; - assign n7851 = Pg35 & (n7850 | (Ng4388 & ~Ng4430)); - assign n7852 = ~Pg35 | ~Ng4423; - assign n7853 = Ng4411 | Ng4405 | Ng4375 | Pg7257 | Pg7243; - assign n7854 = Pg35 & (~Ng4392 | n7853); - assign n7855 = ~Ng4382 | ~n8479 | Ng4375; - assign n7856 = ~Ng4375 | Ng4382 | ~n8479; - assign n7857 = (n7842 & (Pg35 | ~Ng4388)) | (~Pg35 & ~Ng4388); - assign n7858 = ~Pg35 | ~Ng4392 | n7853; - assign n7859 = n7853 | n7846; - assign n7860 = Pg35 | ~Ng4141; - assign n7861 = ~n8324 ^ Ng4082; - assign n7862 = (~n5995 | ~Ng2827) & (~n5996 | Ng2595); - assign n7863 = (~n5995 | ~Ng2823) & (~n5996 | Ng2461); - assign n7864 = (~n5995 | ~Ng2811) & (~n5996 | Ng2327); - assign n7865 = (~n5995 | ~Ng2799) & (~n5996 | Ng2193); - assign n7866 = (~n5995 | ~Ng2795) & (~n5996 | Ng2036); - assign n7867 = (~n5995 | ~Ng2791) & (~n5996 | Ng1902); - assign n7868 = (~n5995 | ~Ng2779) & (~n5996 | Ng1768); - assign n7869 = (~n5995 | ~Ng2767) & (~n5996 | Ng1632); - assign n7870 = ~n8255 | n7336 | ~Ng2724; - assign n7871 = ~Ng2841 | Ng2724 | n8255; - assign n7872 = Pg35 | ~Ng1437; - assign n7873 = ~Pg35 | ~Ng1478 | n8481; - assign n7874 = Pg35 | ~Ng1467; - assign n7875 = ~Pg35 | ~Ng1472 | n8482; - assign n7876 = ~Pg35 | ~Ng1448 | n8483; - assign n7877 = Pg12923 & (Pg7946 | Pg19357 | Ng1333); - assign n7878 = Ng1395 & n7877; - assign n7879 = ~n5425 & (Ng1384 | ~Ng1351); - assign n7880 = ~Ng1389 | ~Pg35 | n7879; - assign n7881 = Ng1280 | n8334; - assign n7882 = ~Ng1280 | n8005 | ~n8334; - assign n7883 = Pg35 | ~Ng1094; - assign n7884 = ~Pg35 | ~Ng1135 | n8486; - assign n7885 = Pg35 | ~Ng1124; - assign n7886 = ~Pg35 | ~Ng1129 | n8487; - assign n7887 = ~Pg35 | ~Ng1105 | n8488; - assign n7888 = Pg12919 & (Pg7916 | Pg19334 | Ng990); - assign n7889 = (~Pg35 | ~Ng1061) & (~n7888 | ~Ng1052); - assign n7890 = ~n4558 & (~Ng1008 | Ng1041); - assign n7891 = ~Ng1046 | ~Pg35 | n7890; - assign n7892 = Ng936 | n8340; - assign n7893 = ~Ng936 | n8014 | ~n8340; - assign n7894 = Pg35 & ~Ng890; - assign n7895 = (n8492 | ~Ng872) & (~Ng446 | n8491); - assign n7896 = (~Ng246 | n8491) & (~Pg14167 | n8492); - assign n7897 = (~Ng269 | n8491) & (~Pg14147 | n8492); - assign n7898 = (~Ng239 | n8491) & (~Pg14125 | n8492); - assign n7899 = (~Ng262 | n8491) & (~Pg14096 | n8492); - assign n7900 = (~Ng232 | n8491) & (~Pg14217 | n8492); - assign n7901 = (~Ng255 | n8491) & (~Pg14201 | n8492); - assign n7902 = (~Ng225 | n8491) & (~Pg14189 | n8492); - assign n7903 = n8131 ^ Ng822; - assign n7904 = ~Pg35 | ~n7739; - assign n7905 = Pg35 & (~Ng847 | ~Ng843); - assign n7906 = ~Pg35 | ~\[4435] | n8122; - assign n7907 = ~Ng568 | ~n7909 | n8183; - assign n7908 = Pg35 | ~Ng562; - assign n7909 = ~n5957 | ~Ng562 | n8182; - assign n7910 = ~Ng355 & (~Pg35 | (Ng351 & ~Ng333)); - assign n7911 = ~\[4436] & ~Ng351; - assign n7912 = ~Ng305 & (Ng311 | ~Ng324); - assign n7913 = ~Pg35 | ~Ng336 | ~n8493; - assign n7914 = Pg35 | ~Ng311; - assign n7915 = ~Pg35 | n8493; - assign n7916 = (Pg35 & (Ng329 | n9349)) | (~Ng329 & n9349); - assign n7917 = (~Ng305 & Ng336) | (~Ng311 & (~Ng305 | ~Ng336)); - assign n7918 = ~Ng311 & ~Ng305; - assign n7919 = (~Ng6537 | ~n8381) & (n7404 | ~n8863); - assign n7920 = Pg35 | ~Ng6509; - assign n7921 = Ng6513 | ~Pg35 | n7404; - assign n7922 = (~Ng6191 | ~n8386) & (n7435 | ~n8873); - assign n7923 = Pg35 | ~Ng6163; - assign n7924 = Ng6167 | ~Pg35 | n7435; - assign n7925 = (~Ng5845 | ~n8390) & (n7466 | ~n8883); - assign n7926 = Pg35 | ~Ng5817; - assign n7927 = Ng5821 | ~Pg35 | n7466; - assign n7928 = (~Ng5499 | ~n8394) & (n7497 | ~n8893); - assign n7929 = Pg35 | ~Ng5471; - assign n7930 = Ng5475 | ~Pg35 | n7497; - assign n7931 = (~Ng5152 | n7934) & (n7527 | ~n8903); - assign n7932 = Pg35 | ~Ng5124; - assign n7933 = Ng5128 | ~Pg35 | n7527; - assign n7934 = ~Pg35 | ~n7527; - assign n7935 = Pg35 | ~Ng5097; - assign n7936 = ~Ng5097 | ~n8494; - assign n7937 = Pg35 | ~Ng5092; - assign n7938 = ~Pg35 | ~Ng5097 | n8494; - assign n7939 = Ng5092 & Pg35; - assign n7940 = ~Ng5077 | ~Pg35 | Ng5073; - assign n7941 = Pg35 & ~Ng5084; - assign n7942 = Ng4098 & ~Ng4093; - assign n7943 = n7942 & Ng4076 & ~Ng4064 & n6260_1 & Ng4087 & ~Ng4057; - assign n7944 = ~Ng2841 | n8323 | Ng4141; - assign n7945 = ~Ng4141 | n7566 | ~n8323; - assign n7946 = (Ng4064 & (Pg35 | ~Ng4072)) | (~Pg35 & ~Ng4072); - assign n7947 = n7946 & n6521; - assign n7948 = (~Ng3845 | ~n8401) & (n7568 | ~n8919); - assign n7949 = Pg35 | ~Ng3817; - assign n7950 = Ng3821 | ~Pg35 | n7568; - assign n7951 = (~Ng3494 | ~n8405) & (n7599 | ~n8929); - assign n7952 = Pg35 | ~Ng3466; - assign n7953 = Ng3470 | ~Pg35 | n7599; - assign n7954 = (n7628 | ~n8939) & (~n8409 | ~Ng3143); - assign n7955 = Pg35 | ~Ng3115; - assign n7956 = Ng3119 | ~Pg35 | n7628; - assign n7957 = ~Ng2715 | Ng2719; - assign n7958 = (Pg35 & n8370) | (~Ng2715 & (~Pg35 | n8370)); - assign n7959 = n7957 & n6333 & n7958; - assign n7960 = Pg35 | ~Ng1484; - assign n7961 = ~Pg35 | ~Ng1300 | n8496; - assign n7962 = ~Pg35 | ~n5425 | ~Ng1384; - assign n7963 = n8484 | Ng1384 | n5425; - assign n7964 = ~Ng1361 | ~Ng1373; - assign n7965 = ~n8484 & (~n6631 | (n7964 & ~n9355)); - assign n7966 = Pg35 & (~Pg12923 | Ng1266); - assign n7967 = Ng1249 | n8005; - assign n7968 = Pg35 | ~Ng1141; - assign n7969 = ~Pg35 | ~Ng956 | n8498; - assign n7970 = ~Pg35 | ~n4558 | ~Ng1041; - assign n7971 = n8489 | Ng1041 | n4558; - assign n7972 = ~Ng1018 | ~Ng1030; - assign n7973 = ~n8489 & (~n6638_1 | (n7972 & ~n9360)); - assign n7974 = Pg35 & (~Pg12919 | Ng921); - assign n7975 = Ng904 | n8014; - assign n7976 = ~Ng370 | ~Ng385 | n7993; - assign n7977 = Pg35 & (~n7739 | Ng832 | n7976); - assign n7978 = n8533 | n8534; - assign n7979 = n8138 | n8139; - assign n7980 = n5960 | ~Ng732; - assign n7981 = ~n8123 | ~Pg35 | n7986; - assign n7982 = Pg35 | ~Ng691; - assign n7983 = ~Pg35 | ~n7986; - assign n7984 = n5957 ^ Ng562; - assign n7985 = n7984 & (~Ng632 | ~Ng626) & ~n8183; - assign n7986 = ~Ng358 | ~Ng385 | Ng376; - assign n7987 = Pg35 & (n7986 | ~n8468); - assign n7988 = (~n7983 & ~Ng504) | (~Ng499 & (n7983 | ~Ng504)); - assign n7989 = (~Ng246 | n8499) & (~n8500 | ~Ng460); - assign n7990 = (~Ng446 | n8499) & (~Ng182 | ~n8500); - assign n7991 = Pg35 | ~Ng376; - assign n7992 = ~Pg35 | ~Ng385 | ~n7993; - assign n7993 = ~Ng376 | ~Ng358; - assign n7994 = Ng4322 | ~Pg35 | Ng4332 | Ng4311 | n8191; - assign n7995 = Ng4340 | ~Ng4643; - assign n7996 = Ng4593 | n8232 | Ng4584 | Ng4608 | ~Ng4633 | Ng4616 | n7994 | Ng4601; - assign n7997 = ~Pg35 | Ng4258; - assign n7998 = n7997 & (~Pg35 | Ng4264); - assign n7999 = n7998 & (~Pg35 | Ng4269); - assign n8000 = Pg35 & (~Ng4264 | Ng4273 | ~Ng4258); - assign n8001 = (Ng2715 & (Pg35 | ~Ng2712)) | (~Pg35 & ~Ng2712); - assign n8002 = n8001 & n6333; - assign n8003 = Pg35 | ~Ng1548; - assign n8004 = ~Pg35 | ~Ng1564 | n8495; - assign n8005 = ~Pg35 | ~Pg12923; - assign n8006 = Ng1548 & Pg35; - assign n8007 = n8140 & ~n5425 & ~n5965; - assign n8008 = n8007 & Pg35; - assign n8009 = Pg35 | ~Ng1589; - assign n8010 = ~Pg10527 | ~Pg35 | Pg17423; - assign n8011 = Pg35 & ~Pg12923; - assign n8012 = Pg35 | ~Ng1205; - assign n8013 = ~Pg35 | ~Ng1221 | n8497; - assign n8014 = ~Pg35 | ~Pg12919; - assign n8015 = Ng1205 & Pg35; - assign n8016 = n8141 & n5036_1; - assign n8017 = n8016 & Pg35; - assign n8018 = Pg35 | ~Ng1246; - assign n8019 = ~Pg10500 | ~Pg35 | Pg17400; - assign n8020 = Pg35 & ~Pg12919; - assign n8021 = Pg35 & n7738 & (~Ng832 | ~Ng827); - assign n8022 = ~n7976 & Ng847; - assign n8023 = Ng703 & (~Pg35 | (~Ng837 & n8022)); - assign n8024 = n7758 & (~Pg35 | (Ng837 & ~n7738)); - assign n8025 = (Pg35 & (Ng847 | n9398)) | (~Ng847 & n9398); - assign n8026 = Ng691 & ~Ng542; - assign n8027 = ~Pg35 | n7976; - assign n8028 = (n7758 | ~Ng475) & (n8027 | ~Ng246); - assign n8029 = (n7758 | ~Ng433) & (n8027 | ~Ng269); - assign n8030 = n7758 | ~Ng392; - assign n8031 = ~Ng854 | Ng703 | n8027; - assign n8032 = Pg35 & (Ng4269 | ~Ng4258); - assign n8033 = Ng4264 & Pg35; - assign n8034 = ~Ng4349 | n8063; - assign n8035 = Pg35 & n8034; - assign n8036 = ~n8126 & ~Ng2988; - assign n8037 = ~Ng4564 | ~Ng4555 | ~Ng4561 | ~Ng4558; - assign n8038 = n8037 & ~Ng2988; - assign n8039 = Pg35 & ~Ng2667; - assign n8040 = Pg35 & ~Ng2527; - assign n8041 = Pg35 & ~Ng2399; - assign n8042 = Pg35 & ~Ng2265; - assign n8043 = Pg35 & ~Ng2102; - assign n8044 = Pg35 & ~Ng1968; - assign n8045 = Pg35 & ~Ng1840; - assign n8046 = Pg35 & ~Ng1706; - assign n8047 = n8115 | ~Ng1542; - assign n8048 = Pg35 & n8047; - assign n8049 = n8117 | ~Ng1199; - assign n8050 = Pg35 & n8049; - assign n8051 = Pg35 & ~Ng6533; - assign n8052 = Pg35 & ~Ng6187; - assign n8053 = Pg35 & ~Ng5841; - assign n8054 = Pg35 & ~Ng5495; - assign n8055 = Pg35 & ~Ng5148; - assign n8056 = Pg35 & ~Ng3841; - assign n8057 = Pg35 & ~Ng3490; - assign n8058 = Pg35 & ~Ng3139; - assign n8059 = ~n6252 & (Pg35 | ~Ng385); - assign n1117 = ~n8059; - assign n8061 = ~Ng4593 | ~n8234; - assign n8062 = Ng4332 & Ng4322 & n8233; - assign n8063 = ~Ng4628 | n8232; - assign n8064 = Ng4349 ^ n8063; - assign n8065 = ~Ng4688 | n8208; - assign n8066 = Ng2599 | ~Ng2629; - assign n8067 = ~n8066 ^ Ng112; - assign n8068 = Ng2465 | ~Ng2495; - assign n8069 = ~n8068 ^ Ng112; - assign n8070 = Ng2331 | ~Ng2361; - assign n8071 = ~n8070 ^ Ng112; - assign n8072 = Ng2197 | ~Ng2227; - assign n8073 = ~n8072 ^ Ng112; - assign n8074 = Ng2040 | ~Ng2070; - assign n8075 = ~n8074 ^ Ng112; - assign n8076 = Ng1906 | ~Ng1936; - assign n8077 = ~n8076 ^ Ng112; - assign n8078 = Ng1772 | ~Ng1802; - assign n8079 = ~n8078 ^ Ng112; - assign n8080 = Ng1636 | ~Ng1668; - assign n8081 = ~n8080 ^ Ng112; - assign n8082 = ~Ng1339 ^ Ng1322; - assign n8083 = ~Ng996 ^ Ng979; - assign n8084 = Ng2610 | ~Ng2619; - assign n8085 = Ng110 ^ n8084; - assign n8086 = Ng2476 | ~Ng2485; - assign n8087 = Ng110 ^ n8086; - assign n8088 = Ng2342 | ~Ng2351; - assign n8089 = Ng110 ^ n8088; - assign n8090 = Ng2208 | ~Ng2217; - assign n8091 = Ng110 ^ n8090; - assign n8092 = Ng2051 | ~Ng2060; - assign n8093 = Ng110 ^ n8092; - assign n8094 = Ng1917 | ~Ng1926; - assign n8095 = Ng110 ^ n8094; - assign n8096 = Ng1783 | ~Ng1792; - assign n8097 = Ng110 ^ n8096; - assign n8098 = Ng1648 | ~Ng1657; - assign n8099 = Ng110 ^ n8098; - assign n8100 = Pg35 & Ng5471; - assign n8101 = (n6884 | n6883) & (n8100 | n6887); - assign n8102 = n6883 | n8100 | n6884; - assign n8103 = n6890 & n8102; - assign n8104 = n6889 & (n6890 | n8102); - assign n8105 = Pg35 & Ng3466; - assign n8106 = ~Ng2735 | n7657; - assign n8107 = ~Ng2652 ^ Ng2648; - assign n8108 = ~Ng2514 ^ Ng2518; - assign n8109 = ~Ng2384 ^ Ng2380; - assign n8110 = ~Ng2250 ^ Ng2246; - assign n8111 = ~Ng2089 ^ Ng2093; - assign n8112 = ~Ng1955 ^ Ng1959; - assign n8113 = ~Ng1821 ^ Ng1825; - assign n8114 = ~Ng1687 ^ Ng1691; - assign n8115 = ~Pg7946 | ~Ng1526 | n5963 | Ng1514; - assign n8116 = n8115 ^ Ng1542; - assign n8117 = ~Pg7916 | Ng1171 | ~Ng1183 | n8439; - assign n8118 = n8117 ^ Ng1199; - assign n8119 = ~n5935 ^ n7558; - assign n8120 = ~n5949 ^ n7563; - assign n8121 = ~Ng4076 | n7807; - assign n8122 = ~Ng504 & Ng499 & n5933 & ~n7976; - assign n8123 = Ng691 | ~Ng703 | n7744; - assign n8124 = (n7828 | ~Ng691) & (n7986 | n8123); - assign n8125 = (n5918 | n7835) & (n5865 | n7836); - assign n8126 = Ng4489 & Ng4483 & Ng4486 & Ng4492; - assign n8127 = ~Ng4521 & ~n9340 & (n8126 | Ng4527); - assign n8128 = ~n5958 & (~Ng1536 | (~n8047 & Ng1413)); - assign n8129 = ~n7878 ^ Ng1404; - assign n8130 = ~n5959 & (~Ng1193 | (~n8049 & Ng1070)); - assign n8131 = ~Ng817 | ~Ng832 | n7976; - assign n8132 = n8122 & (Ng728 | (Ng661 & Pg35)); - assign n8133 = n8495 & Ng1564; - assign n8134 = ~n8133 ^ Ng1559; - assign n8135 = n8497 & Ng1221; - assign n8136 = ~n8135 ^ Ng1216; - assign n8137 = Ng232 ^ Ng255; - assign n8138 = ~Ng246 ^ Ng269; - assign n8139 = ~Ng239 ^ Ng262; - assign n8140 = Ng1322 ^ Ng1579; - assign n8141 = Ng1236 ^ Ng979; - assign n8142 = ~Pg54 | Pg57 | Pg56 | Pg53 | Ng55; - assign n8143 = ~Ng50 | Ng16; - assign n8144 = Ng46 & Ng48 & Ng45 & Ng8 & ~Ng52; - assign n8145 = Ng45 | Ng46 | Ng8; - assign n8146 = Ng52 | ~Ng51 | n8145; - assign n8147 = Ng48 | n8146; - assign n8148 = Ng50 | ~Ng16; - assign n8149 = n8147 | n8148; - assign n8150 = Ng16 | Ng50; - assign n8151 = ~Ng52 | Ng48 | n8145; - assign n3827_1 = ~n8142; - assign n8153 = Pg53 | ~n8142; - assign n8154 = n8145 | Ng51 | Ng52; - assign n8155 = n8142 | n6080; - assign n8156 = Ng48 | n8154; - assign n8157 = n8151 | Ng51 | n8143; - assign n8158 = n8157 & n6063 & n6027_1; - assign n8159 = n8150 | n8156; - assign n8160 = n8148 | n8156; - assign n8161 = n8142 | n8160; - assign n8162 = n8143 | n8147; - assign n8163 = n8142 | n8162; - assign n8164 = ~Ng48 | n8143; - assign n8165 = n8146 | n8164; - assign n8166 = n8142 | n8165; - assign n8167 = n8142 | Ng48 | ~Ng50 | ~Ng16; - assign n8168 = n8146 | n8167; - assign n8169 = n8154 | n8167; - assign n8170 = n8154 | n8164; - assign n8171 = n8142 | n8170; - assign n8172 = Ng51 | n8145 | ~Ng52 | n8164; - assign n8173 = n8142 | n8172; - assign n8174 = n8148 | ~n8144 | Ng51; - assign n8175 = Ng1291 | n8161; - assign n8176 = Ng947 | n8163; - assign n8177 = n6087 | n6088; - assign n8178 = Ng4322 ^ Pg72; - assign n8179 = Ng4332 ^ Pg73; - assign n8180 = Pg11678 & ~Ng736; - assign n8181 = Ng370 | ~Ng385 | n7993; - assign n8182 = Pg9048 & ~Ng559; - assign n8183 = ~Pg35 | n8182; - assign n8184 = Ng490 ^ Pg73; - assign n8185 = Ng482 ^ Pg72; - assign n8186 = Ng518 | n5931; - assign n8187 = n5931 | ~Ng518; - assign n8188 = ~Ng4349 | Ng4358; - assign n8189 = ~Ng3352 | ~Ng3288; - assign n8190 = Ng4349 | ~Ng4358; - assign n8191 = Ng4358 | Ng4349; - assign n8192 = ~Ng5357 | ~Ng5297; - assign n8193 = Ng2759 ^ Pg72; - assign n8194 = Ng2763 ^ Pg73; - assign n8195 = n8193 | n8194; - assign n8196 = n8195 | ~Ng2756 | Ng2748; - assign n8197 = ~Ng2208 | Ng2217; - assign n8198 = ~Ng2741 | Ng2756 | Ng2748; - assign n8199 = ~Ng1783 | Ng1792; - assign n8200 = ~Ng2748 | n8195; - assign n8201 = ~Ng2051 | Ng2060; - assign n8202 = ~Ng1917 | Ng1926; - assign n8203 = ~Ng2476 | Ng2485; - assign n8204 = ~Ng2342 | Ng2351; - assign n8205 = ~Ng2610 | Ng2619; - assign n8206 = ~Ng2741 & ~Ng2756 & ~Ng2748; - assign n8207 = ~Ng1648 | Ng1657; - assign n8208 = ~Ng4669 | ~Ng4659 | ~Ng4653; - assign n8209 = ~Ng4793 | ~Ng4776 | Ng4801; - assign n8210 = ~Ng4859 | ~Ng4843 | ~Ng4849; - assign n8211 = ~Ng4983 | ~Ng4966 | Ng4991; - assign n8212 = n7835 | n5865 | n5918; - assign n8213 = Pg35 & Ng6509; - assign n8214 = n8102 | n5880 | n6890 | n8105 | n6889 | n8213; - assign n8215 = ~n8212 & ~n5906 & ~n5905 & n5877 & ~n5902; - assign n8216 = ~Ng3171 | ~Ng3179; - assign n8217 = ~Ng6219 | ~Ng6227; - assign n8218 = ~Ng4098 & Ng4093; - assign n8219 = ~Ng3873 | ~Ng3881; - assign n8220 = Ng4098 & Ng4093; - assign n8221 = ~Ng5527 | ~Ng5535; - assign n8222 = ~Ng6565 | ~Ng6573; - assign n8223 = ~Ng5873 | ~Ng5881; - assign n8224 = ~Ng3522 | ~Ng3530; - assign n8225 = ~Ng5180 | ~Ng5188; - assign n8226 = Ng4108 ^ Pg72; - assign n8227 = Ng4104 ^ Pg73; - assign n8228 = n6126 & ~n8251; - assign n8229 = ~Ng4878 | ~Ng4843; - assign n8230 = n8065 & ~n8253; - assign n8231 = ~Ng4688 | ~Ng4653; - assign n8232 = ~Ng4340 | ~Ng4621 | Ng4639; - assign n8233 = ~n8034 & Ng4358; - assign n8234 = Ng4584 & n8062; - assign n8235 = ~Pg35 | n6216_1; - assign n8236 = Ng4311 & n8233; - assign n8237 = n5924 | Ng4818 | \[4661] ; - assign n8238 = ~n8237 & Ng71; - assign n8239 = n5924 | Ng4818 | \[4661] ; - assign n8240 = (~Ng278 & n4385) | (~n4384 & (Ng278 | n4385)); - assign n8241 = n8240 & ~n5962 & Ng691; - assign n8242 = Ng287 & Ng283 & n8241; - assign n8243 = ~n8242 | ~Ng291; - assign n8244 = ~Ng294 | n8243; - assign n8245 = ~Ng298 | n8244; - assign n8246 = ~Ng691 | n5962 | n6300; - assign n8247 = n4520 & Ng146 & ~n8246; - assign n8248 = Ng164 & n8247; - assign n8249 = ~n8248 | ~Ng150; - assign n8250 = ~Ng153 | n8249; - assign n8251 = Ng63 & n5966 & ~n6124; - assign n8252 = ~n6316 & Ng4966; - assign n8253 = Ng63 & n5966 & ~n6090; - assign n8254 = ~n6327 & Ng4776; - assign n8255 = ~Ng2715 | ~Ng2719; - assign n8256 = ~Ng2724 | n8255; - assign n8257 = n8106 | ~Ng2741; - assign n8258 = ~Ng2748 | n8257; - assign n8259 = ~Ng1322 | Ng1564 | Ng1548 | ~Ng1404 | Ng1559 | Ng1554; - assign n8260 = ~Ng2629 & ~Ng2555; - assign n8261 = ~n8260 | ~n8263; - assign n8262 = n8261 & Pg35; - assign n8263 = n5911 | ~n5999; - assign n8264 = Ng2599 & ~Ng2555; - assign n8265 = n8263 & n8264; - assign n8266 = ~n8263 | ~Ng2555; - assign n8267 = ~Ng2495 & ~Ng2421; - assign n8268 = ~n8267 | ~n8270; - assign n8269 = n8268 & Pg35; - assign n8270 = n5872 | ~n6001; - assign n8271 = Ng2465 & ~Ng2421; - assign n8272 = n8270 & n8271; - assign n8273 = ~n8270 | ~Ng2421; - assign n8274 = ~Ng2361 & ~Ng2287; - assign n8275 = ~n8274 | ~n8277; - assign n8276 = n8275 & Pg35; - assign n8277 = n5910 | ~n6011; - assign n8278 = Ng2331 & ~Ng2287; - assign n8279 = n8277 & n8278; - assign n8280 = ~n8277 | ~Ng2287; - assign n8281 = ~Ng2227 & ~Ng2153; - assign n8282 = ~n8281 | ~n8284; - assign n8283 = n8282 & Pg35; - assign n8284 = n5873 | ~n6007; - assign n8285 = ~Ng2227 | ~n8284; - assign n8286 = Ng2197 & ~Ng2153; - assign n8287 = n8284 & n8286; - assign n8288 = ~Ng979 | Ng1221 | Ng1205 | Ng1211 | ~Ng1061 | Ng1216; - assign n8289 = ~Ng2070 & ~Ng1996; - assign n8290 = ~n8289 | ~n8292; - assign n8291 = n8290 & Pg35; - assign n8292 = n5921 | ~n6003; - assign n8293 = ~Ng2070 | ~n8292; - assign n8294 = Ng2040 & ~Ng1996; - assign n8295 = n8292 & n8294; - assign n8296 = ~Ng1936 & ~Ng1862; - assign n8297 = ~n8296 | ~n8299; - assign n8298 = n8297 & Pg35; - assign n8299 = n5887 | ~n6005; - assign n8300 = ~Ng1936 | ~n8299; - assign n8301 = Ng1906 & ~Ng1862; - assign n8302 = n8299 & n8301; - assign n8303 = ~Ng1802 & ~Ng1728; - assign n8304 = ~n8303 | ~n8306; - assign n8305 = n8304 & Pg35; - assign n8306 = n5894 | ~n5997; - assign n8307 = Ng1772 & ~Ng1728; - assign n8308 = n8306 & n8307; - assign n8309 = ~n8306 | ~Ng1728; - assign n8310 = ~Ng1592 & ~Ng1668; - assign n8311 = ~n8310 | ~n8313; - assign n8312 = n8311 & Pg35; - assign n8313 = n4162 | ~n6009; - assign n8314 = ~Ng1636 | ~n8313; - assign n8315 = ~Ng1592 | ~n8313; - assign n8316 = Ng4801 | Ng4793 | ~Ng4776; - assign n8317 = Ng4991 | Ng4983 | ~Ng4966; - assign n8318 = n5966 & Ng93; - assign n8319 = n6124 | ~n8318; - assign n8320 = n6090 | ~n8318; - assign n8321 = ~Ng5703 | Ng5644; - assign n8322 = ~Pg35 | ~n5876; - assign n8323 = ~Ng4057 | ~Ng4064; - assign n8324 = ~n8323 & Ng4141; - assign n8325 = ~Ng4087 | n8121; - assign n8326 = ~Ng4093 | n8325; - assign n8327 = Ng3703 | ~Ng3639; - assign n8328 = ~Pg35 | ~n5908; - assign n8329 = Pg35 & n5966; - assign n8330 = n5966 & Ng112; - assign n8331 = n8082 | Ng1351; - assign n8332 = ~n8082 | n7964 | ~Ng1351; - assign n8333 = ~n9355 & n8332 & ~Ng1312 & n8331; - assign n8334 = ~Pg12923 | ~Ng1266 | ~Ng1249; - assign n8335 = Ng1252 & ~n7817; - assign n8336 = Ng1259 & ~n7384; - assign n8337 = n8083 | Ng1008; - assign n8338 = ~n8083 | ~Ng1008 | n7972; - assign n8339 = ~n9360 & n8338 & ~Ng969 & n8337; - assign n8340 = ~Pg12919 | ~Ng921 | ~Ng904; - assign n8341 = Ng907 & ~n7822; - assign n8342 = Ng914 & ~n7394; - assign n8343 = Ng43 & ~n5947 & n5966; - assign n8344 = ~Ng4087 & n8343; - assign n4287_1 = Pg35 & Ng6573; - assign n8346 = ~Ng6565 | Ng6573; - assign n8347 = Ng4087 & n8343; - assign n8348 = ~Ng6219 | Ng6227; - assign n1064_1 = Pg35 & Ng5881; - assign n8350 = ~Ng5873 | Ng5881; - assign n8351 = ~Ng5527 | Ng5535; - assign n8352 = ~Ng5180 | Ng5188; - assign n8353 = ~Ng5029 | ~Ng5016 | ~Ng5062; - assign n8354 = ~Ng5033 | n8353 | ~Ng5037; - assign n8355 = ~Ng5022 | Ng5029 | Ng5016; - assign n8356 = n8355 | Ng5033 | Ng5037; - assign n8357 = n8356 | Ng5046 | Ng5041; - assign n8358 = Ng5057 & ~Ng5046 & Ng5022; - assign n8359 = Ng5062 & Ng5046 & ~Ng5057; - assign n8360 = n8358 & Pg84 & ~Ng5041; - assign n8361 = n8359 & ~Pg84 & Ng5052; - assign n8362 = n8358 & ~Pg84 & ~Ng5052; - assign n8363 = Pg84 & Ng5041 & n8359; - assign n8364 = n8360 | n8361 | n8362 | n8363; - assign n8365 = ~Ng3873 | Ng3881; - assign n8366 = ~Ng3522 | Ng3530; - assign n8367 = ~Ng3171 | Ng3179; - assign n8368 = n5966 & Ng110; - assign n8369 = ~Pg35 | ~n5920; - assign n8370 = Ng2715 | ~Ng2719; - assign n8371 = ~Pg35 | ~n5919; - assign n8372 = ~Pg35 | ~n5925; - assign n8373 = Ng2719 | Ng2715; - assign n8374 = ~Pg35 | ~n5878; - assign n8375 = ~Pg35 | ~n5916; - assign n8376 = ~Pg35 | ~n5899; - assign n8377 = ~Pg35 | ~n5941; - assign n8378 = ~Pg35 | ~n5868; - assign n8379 = n8356 & n8354; - assign n8380 = Ng5062 | Ng5022; - assign n8381 = n7404 & Pg35; - assign n8382 = Ng4180 & ~Ng4284; - assign n8383 = Ng6565 | ~Ng6573; - assign n8384 = Ng6565 | Ng6573; - assign n8385 = Ng6555 | Ng6549 | Ng6561; - assign n8386 = n7435 & Pg35; - assign n8387 = Ng6219 | ~Ng6227; - assign n8388 = Ng6219 | Ng6227; - assign n8389 = Ng6203 | Ng6215 | Ng6209; - assign n8390 = n7466 & Pg35; - assign n8391 = Ng5873 | ~Ng5881; - assign n8392 = Ng5873 | Ng5881; - assign n8393 = Ng5863 | Ng5857 | Ng5869; - assign n8394 = n7497 & Pg35; - assign n8395 = Ng5527 | ~Ng5535; - assign n8396 = Ng5527 | Ng5535; - assign n8397 = Ng5517 | Ng5511 | Ng5523; - assign n8398 = Ng5180 | ~Ng5188; - assign n8399 = Ng5180 | Ng5188; - assign n8400 = Ng5170 | Ng5164 | Ng5176; - assign n8401 = n7568 & Pg35; - assign n8402 = Ng3873 | ~Ng3881; - assign n8403 = Ng3873 | Ng3881; - assign n8404 = Ng3857 | Ng3869 | Ng3863; - assign n8405 = n7599 & Pg35; - assign n8406 = Ng3522 | ~Ng3530; - assign n8407 = Ng3522 | Ng3530; - assign n8408 = Ng3512 | Ng3506 | Ng3518; - assign n8409 = n7628 & Pg35; - assign n8410 = Ng3171 | ~Ng3179; - assign n8411 = Ng3171 | Ng3179; - assign n8412 = Ng3161 | Ng3155 | Ng3167; - assign n8413 = Ng2619 & n5920 & Ng2587; - assign n8414 = Pg35 & n8413; - assign n8415 = ~Ng2610 | Ng2587; - assign n8416 = Ng2485 & n5919; - assign n8417 = Ng2453 & n8416; - assign n8418 = Pg35 & n8417; - assign n8419 = ~Ng2476 | Ng2453; - assign n8420 = Ng2351 & n5925 & Ng2319; - assign n8421 = Pg35 & n8420; - assign n8422 = ~Ng2342 | Ng2319; - assign n8423 = Ng2217 & n5878 & Ng2185; - assign n8424 = Pg35 & n8423; - assign n8425 = ~Ng2208 | Ng2185; - assign n8426 = Ng2060 & n5916; - assign n8427 = Ng2028 & n8426; - assign n8428 = Pg35 & n8427; - assign n8429 = ~Ng2051 | Ng2028; - assign n8430 = Ng1926 & n5899 & Ng1894; - assign n8431 = Pg35 & n8430; - assign n8432 = ~Ng1917 | Ng1894; - assign n8433 = Ng1792 & n5941 & Ng1760; - assign n8434 = Pg35 & n8433; - assign n8435 = ~Ng1783 | Ng1760; - assign n8436 = Ng1657 & n5868 & Ng1624; - assign n8437 = Pg35 & n8436; - assign n8438 = ~Ng1648 | Ng1624; - assign n8439 = Ng996 & Ng1178 & ~Ng1189; - assign n8440 = ~n5884_1 | n7430; - assign n8441 = ~Pg35 | n8440; - assign n8442 = ~n5952 | n7461; - assign n8443 = ~Pg35 | n8442; - assign n8444 = ~n5940 | n7492; - assign n8445 = ~Pg35 | n8444; - assign n8446 = ~n5876 | n7523; - assign n8447 = ~Pg35 | n8446; - assign n8448 = \[4415] & Pg17577 & ~n8192; - assign n8449 = ~n4151_1 | ~n8448; - assign n8450 = ~Pg35 | n8449; - assign n8451 = ~n5927 | n7594; - assign n8452 = ~Pg35 | n8451; - assign n8453 = ~n5889 | n7623; - assign n8454 = ~Pg35 | n8453; - assign n8455 = Ng3639 | Ng3703; - assign n8456 = ~n5908 | n7653; - assign n8457 = ~Pg35 | n8456; - assign n8458 = Pg13272 & Ng1526 & ~Ng1514; - assign n8459 = Ng1514 & Ng1526 & Pg13272; - assign n8460 = Ng1514 & Pg13272 & ~Ng1526; - assign n8461 = Ng1183 & Pg13259 & ~Ng1171; - assign n8462 = Ng1183 & Ng1171 & Pg13259; - assign n8463 = Pg13259 & Ng1171 & ~Ng1183; - assign n8464 = n8131 | ~Ng822; - assign n8465 = Ng661 ^ Ng728; - assign n8466 = Ng655 ^ Ng718; - assign n8467 = n8122 & Ng671; - assign n8468 = ~Ng667 | Ng686; - assign n8469 = Ng513 | n7986 | ~Ng518; - assign n8470 = Ng482 & n5934; - assign n8471 = ~Ng4076 & ~n6261 & n6260_1 & ~Ng4087; - assign n8472 = n8471 & Ng4057 & ~Ng4064; - assign n8473 = n8471 & ~Ng4057 & Ng4064; - assign n8474 = n8181 | n8476 | n8477; - assign n8475 = n8474 & Pg35; - assign n8476 = ~Ng691 & (Ng411 | Ng424 | ~Ng417); - assign n8477 = Ng691 & (Ng499 | Ng518); - assign n8478 = n5091 & Pg35; - assign n8479 = n7853 & Pg35; - assign n8480 = Ng1442 & ~Ng1495; - assign n8481 = Ng1437 & n8460 & n8480; - assign n8482 = Ng1467 & n8459 & n8480; - assign n8483 = Ng1454 & n8458 & n8480; - assign n8484 = ~Pg35 | ~Ng1351; - assign n8485 = Ng1099 & ~Ng1152; - assign n8486 = Ng1094 & n8463 & n8485; - assign n8487 = Ng1124 & n8462 & n8485; - assign n8488 = Ng1111 & n8461 & n8485; - assign n8489 = ~Pg35 | ~Ng1008; - assign n8490 = ~Ng862 & Ng890 & ~Ng896; - assign n8491 = ~Pg35 | n8490; - assign n8492 = ~Pg35 | ~n8490; - assign n8493 = (Ng324 & ~Ng305) | (~Ng311 & (~Ng324 | ~Ng305)); - assign n8494 = Ng5084 & Ng5092; - assign n8495 = Ng1430 & Ng1548; - assign n8496 = Ng1484 & n5170 & n8480; - assign n8497 = Ng1087 & Ng1205; - assign n8498 = Ng1141 & n4887 & n8485; - assign n8499 = ~Pg35 | n8181; - assign n8500 = n8181 & Pg35; - assign n8501 = Pg8291 & Ng218; - assign n8502 = Pg17688 & Pg17778 & Pg14828 & Pg12470; - assign n8503 = ~Pg17760 | ~Pg17649 | ~Pg14779 | ~Pg12422; - assign n8504 = Pg17607 & Pg17739 & Pg14738 & Pg12350; - assign n8505 = Pg17580 & Pg17711 & Pg14694 & Pg12300; - assign n8506 = ~Pg17674 | ~Pg17519 | ~Pg14662 | ~Pg12238; - assign n8507 = ~Pg16775 | ~Pg16659 | ~Pg13966 | ~Pg11418; - assign n8508 = ~Pg16744 | ~Pg16627 | ~Pg13926 | ~Pg11388; - assign n8509 = ~Pg16718 | ~Pg16603 | ~Pg13895 | ~Pg11349; - assign n8510 = n8133 & Ng1554; - assign n8511 = n8135 & Ng1211; - assign n8512 = ~n7430 ^ n7431; - assign n8513 = n7461 ^ n7462; - assign n8514 = ~n7492 ^ n7493; - assign n8515 = ~n7523 ^ n7524; - assign n8516 = n8448 ^ n7552; - assign n8517 = ~n7594 ^ n7595; - assign n8518 = ~n7623 ^ n7624; - assign n8519 = ~n7653 ^ n7654; - assign n8520 = Ng1319 | n5091; - assign n8521 = ~Ng1448 ^ n8520; - assign n8522 = ~Ng1300 ^ n8520; - assign n8523 = ~Ng1472 ^ n8520; - assign n8524 = ~Ng1478 ^ n8520; - assign n8525 = ~n6128 | Ng976; - assign n8526 = ~Ng1105 ^ n8525; - assign n8527 = ~Ng956 ^ n8525; - assign n8528 = ~Ng1129 ^ n8525; - assign n8529 = ~Ng1135 ^ n8525; - assign n6560 = Ng4534 ^ n7840; - assign n4047_1 = Ng862 ^ n7894; - assign n1777 = Ng5084 ^ n7939; - assign n8533 = Ng246 ^ Ng269; - assign n8534 = Ng239 ^ Ng262; - assign n8535 = n5985 ^ n7980; - assign n6452 = Ng1430 ^ n8006; - assign n4627 = Ng1333 ^ n8008; - assign n1087_1 = Ng1087 ^ n8015; - assign n5768 = Ng990 ^ n8017; - assign n8540 = ~Pg9019 ^ Ng4291; - assign n8541 = ~Pg9019 ^ n8540; - assign n8542 = ~Pg8839 ^ Ng4281; - assign n8543 = ~Pg8839 ^ n8542; - assign n8544 = ~n9153 & (Pg35 | ~Ng2980); - assign n2483 = ~n8544; - assign n8546 = (Pg35 & n9162) | (~Ng4366 & (~Pg35 | n9162)); - assign n800_1 = ~n8546; - assign n8548 = ~n9164 & (Pg35 | ~Ng2955); - assign n3760 = ~n8548; - assign n8550 = ~n9166 & (Pg35 | ~Ng2941); - assign n1112_1 = ~n8550; - assign n8552 = ~n9168 & (Pg35 | ~Ng2927); - assign n1372_1 = ~n8552; - assign n8554 = ~n9169 & (Pg35 | ~Ng2965); - assign n2423 = ~n8554; - assign n8556 = ~n9171 & (Pg35 | ~Ng2917); - assign n4244 = ~n8556; - assign n8558 = ~n9172 & (Pg35 | ~Ng2902); - assign n4460 = ~n8558; - assign n8560 = ~n9174 & (Pg35 | ~Ng2970); - assign n2946_1 = ~n8560; - assign n8562 = Ng55 | Ng2980; - assign n8563 = (Pg35 & ~n8562) | (~Ng2886 & (~Pg35 | ~n8562)); - assign n1552_1 = ~n8563; - assign n8565 = ~Pg44 | Ng2890; - assign n8566 = (Pg35 & ~n8565) | (~Ng2873 & (~Pg35 | ~n8565)); - assign n5633 = ~n8566; - assign n8568 = Ng2946 | Ng2886; - assign n8569 = (Pg35 & ~n8568) | (~Ng2878 & (~Pg35 | ~n8568)); - assign n1752 = ~n8569; - assign n8571 = ~Pg91 | Ng2878; - assign n8572 = (Pg35 & ~n8571) | (~Ng2882 & (~Pg35 | ~n8571)); - assign n3832_1 = ~n8572; - assign n8574 = ~n9176 & (Pg35 | ~Ng2898); - assign n3871_1 = ~n8574; - assign n8576 = Ng2898 | ~n8215; - assign n8577 = (Pg35 & ~n8576) | (~Ng2864 & (~Pg35 | ~n8576)); - assign n1664_1 = ~n8577; - assign n8579 = Ng2864 | n8214; - assign n8580 = (Pg35 & ~n8579) | (~Ng2856 & (~Pg35 | ~n8579)); - assign n3975 = ~n8580; - assign n8582 = ~n9178 & (Pg35 | ~Ng2848); - assign n5653 = ~n8582; - assign n8584 = ~n9180 & (Pg35 | ~\[4433] ); - assign n2280_1 = ~n8584; - assign n8586 = Ng4242 | Ng4300; - assign n8587 = (~Pg35 & ~Ng4297) | (~n8586 & (Pg35 | ~Ng4297)); - assign n6646 = ~n8587; - assign n8589 = Ng4176 | Ng4072; - assign n8590 = (Pg35 & ~n8589) | (~Ng4172 & (~Pg35 | ~n8589)); - assign n4882 = ~n8590; - assign n8592 = Ng1283 | Ng1277; - assign n8593 = (Pg35 & ~n8592) | (~Ng1296 & (~Pg35 | ~n8592)); - assign n2111 = ~n8593; - assign n8595 = Ng933 | Ng939; - assign n8596 = (Pg35 & ~n8595) | (~Ng952 & (~Pg35 | ~n8595)); - assign n1247 = ~n8596; - assign n8598 = Ng534 | Ng301; - assign n8599 = (Pg35 & ~n8598) | (~Ng542 & (~Pg35 | ~n8598)); - assign n6536 = ~n8599; - assign n8601 = ~Ng691 | Ng546; - assign n8602 = (Pg35 & ~n8601) | (~Ng538 & (~Pg35 | ~n8601)); - assign n5956 = ~n8602; - assign n8604 = Ng199 | Ng222; - assign n8605 = (Pg35 & ~n8604) | (~\[4426] & (~Pg35 | ~n8604)); - assign n3675 = ~n8605; - assign n8607 = ~\[4435] | Ng550; - assign n8608 = (Pg35 & ~n8607) | (~Ng534 & (~Pg35 | ~n8607)); - assign n3927 = ~n8608; - assign n8610 = (~Pg35 & ~Ng37) | (~\[4433] & (Pg35 | ~Ng37)); - assign n6160 = ~n8610; - assign n4667_1 = ~n9188; - assign n5913_1 = ~n9189; - assign n8614 = (~Pg35 & ~Ng550) | (~\[4426] & (Pg35 | ~Ng550)); - assign n2793_1 = ~n8614; - assign n8616 = ~n9190 & (Ng4878 | n6193 | ~Ng4843); - assign n6260 = ~n8616; - assign n8618 = ~n9191 & (Ng4688 | n6198 | ~Ng4653); - assign n1868 = ~n8618; - assign n8620 = (Pg35 & n9192) | (~Ng4643 & (~Pg35 | n9192)); - assign n4249 = ~n8620; - assign n8622 = (n6254 & (Pg35 | ~Ng446)) | (~Pg35 & ~Ng446); - assign n3775 = ~n8622; - assign n8624 = (Pg35 & n9206) | (~Ng4961 & (~Pg35 | n9206)); - assign n4554 = ~n8624; - assign n8626 = (Pg35 & n9208) | (~Ng4950 & (~Pg35 | n9208)); - assign n3548 = ~n8626; - assign n8628 = (Pg35 & n9210) | (~Ng4894 & (~Pg35 | n9210)); - assign n2065_1 = ~n8628; - assign n8630 = (Pg35 & n9212) | (~Ng4771 & (~Pg35 | n9212)); - assign n4909_1 = ~n8630; - assign n8632 = (Pg35 & n9214) | (~Ng4760 & (~Pg35 | n9214)); - assign n1591_1 = ~n8632; - assign n8634 = (Pg35 & n9216) | (~Ng4704 & (~Pg35 | n9216)); - assign n6201_1 = ~n8634; - assign n8636 = (n8035 & Ng4358) | (~n8034 & (n8035 | ~Ng4358)); - assign n8637 = n9217 & (~Pg35 | n5968 | n8064); - assign n5613_1 = ~n8637; - assign n8639 = (Pg35 & n6291) | (~Ng4369 & (~Pg35 | n6291)); - assign n4953_1 = ~n8639; - assign n8641 = n9219 & (\[4437] | n5967 | ~Ng4581); - assign n8642 = (Pg35 & n9220) | (~Ng4492 & (~Pg35 | n9220)); - assign n6008 = ~n8642; - assign n8644 = n9221 & (n5967 | ~Ng4581 | Ng4575); - assign n8645 = (Pg35 & n9222) | (~Ng4564 & (~Pg35 | n9222)); - assign n1689_1 = ~n8645; - assign n8647 = n8263 & (n6338 | n8260 | ~Ng2643); - assign n8648 = n8647 & (~n9106 | (n5999 & ~Ng1589)); - assign n8649 = n8270 & (n6357 | n8267 | ~Ng2509); - assign n8650 = n8649 & ((n6001 & Ng1589) | ~n9107); - assign n8651 = n8277 & (n6375 | n8274 | ~Ng2375); - assign n8652 = n8651 & (~n9108 | (n6011 & ~Ng1589)); - assign n8653 = n8284 & (n6393 | n8281 | ~Ng2241); - assign n8654 = n8653 & ((n6007 & Ng1589) | ~n9109); - assign n8655 = n8292 & (n6412 | n8289 | ~Ng2084); - assign n8656 = n8655 & (~n9110 | (n6003 & ~Ng1246)); - assign n8657 = n8299 & (n6431 | n8296 | ~Ng1950); - assign n8658 = n8657 & ((n6005 & Ng1246) | ~n9111); - assign n8659 = n8306 & (n6450 | n8303 | ~Ng1816); - assign n8660 = n8659 & (~n9112 | (n5997 & ~Ng1246)); - assign n8661 = n8313 & (n6468 | n8310 | ~Ng1682); - assign n8662 = n8661 & ((n6009 & Ng1246) | ~n9113); - assign n8663 = (n5967 | Ng269) & (~Pg72 | Ng262); - assign n8664 = n8663 & (~Pg73 | (~Pg72 & Ng255)); - assign n8665 = (Pg35 & ~n8664) | (~\[4432] & (~Pg35 | ~n8664)); - assign n1317_1 = ~n8665; - assign n8667 = Ng239 | Pg73 | ~Pg72; - assign n8668 = Ng246 | n5967; - assign n8669 = (Ng232 & (~Pg72 | Ng225)) | (Pg72 & Ng225); - assign n8670 = n8667 & n8668 & (~Pg73 | n8669); - assign n8671 = (Pg35 & ~n8670) | (~Ng479 & (~Pg35 | ~n8670)); - assign n2247 = ~n8671; - assign n8673 = (n5876 & n8321) | (~Ng5644 & (~n5876 | n8321)); - assign n8674 = ~n9225 & (Pg35 | ~Ng5703); - assign n6086_1 = ~n8674; - assign n8676 = (Pg35 & ~n8644) | (~Ng4552 & (~Pg35 | ~n8644)); - assign n6413 = ~n8676; - assign n8678 = (Pg35 & ~n8641) | (~Ng4515 & (~Pg35 | ~n8641)); - assign n6340 = ~n8678; - assign n8680 = (Ng2667 & Ng2661) | (n8039 & (Ng2667 | ~Ng2661)); - assign n8681 = (~n8262 & ~Ng2661) | (~Ng2667 & (n8262 | ~Ng2661)); - assign n3623 = ~n8681; - assign n8683 = (~n8262 & ~Ng2643) | (~Ng2648 & (n8262 | ~Ng2643)); - assign n3538 = ~n8683; - assign n8685 = (n8040 & (~Ng2533 | Ng2527)) | (Ng2533 & Ng2527); - assign n8686 = (~n8269 & ~Ng2527) | (~Ng2533 & (n8269 | ~Ng2527)); - assign n6022_1 = ~n8686; - assign n8688 = (~n8269 & ~Ng2509) | (~Ng2514 & (n8269 | ~Ng2509)); - assign n2590_1 = ~n8688; - assign n8690 = (Ng2399 & Ng2393) | (n8041 & (Ng2399 | ~Ng2393)); - assign n8691 = (~n8276 & ~Ng2393) | (~Ng2399 & (n8276 | ~Ng2393)); - assign n1636_1 = ~n8691; - assign n8693 = (~n8276 & ~Ng2375) | (~Ng2380 & (n8276 | ~Ng2375)); - assign n3360 = ~n8693; - assign n8695 = (Ng2265 & Ng2259) | (n8042 & (Ng2265 | ~Ng2259)); - assign n8696 = (~n8283 & ~Ng2259) | (~Ng2265 & (n8283 | ~Ng2259)); - assign n4480 = ~n8696; - assign n8698 = (~n8283 & ~Ng2241) | (~Ng2246 & (n8283 | ~Ng2241)); - assign n5111 = ~n8698; - assign n8700 = (n8043 & (~Ng2108 | Ng2102)) | (Ng2108 & Ng2102); - assign n8701 = (~n8291 & ~Ng2102) | (~Ng2108 & (n8291 | ~Ng2102)); - assign n5261 = ~n8701; - assign n8703 = (~n8291 & ~Ng2084) | (~Ng2089 & (n8291 | ~Ng2084)); - assign n1026_1 = ~n8703; - assign n8705 = (n8044 & (~Ng1974 | Ng1968)) | (Ng1974 & Ng1968); - assign n8706 = (~n8298 & ~Ng1968) | (~Ng1974 & (n8298 | ~Ng1968)); - assign n4509_1 = ~n8706; - assign n8708 = (~n8298 & ~Ng1950) | (~Ng1955 & (n8298 | ~Ng1950)); - assign n4164 = ~n8708; - assign n8710 = (Ng1840 & Ng1834) | (n8045 & (Ng1840 | ~Ng1834)); - assign n8711 = (~n8305 & ~Ng1834) | (~Ng1840 & (n8305 | ~Ng1834)); - assign n3411 = ~n8711; - assign n8713 = (~n8305 & ~Ng1816) | (~Ng1821 & (n8305 | ~Ng1816)); - assign n5366_1 = ~n8713; - assign n8715 = (Ng1706 & Ng1700) | (n8046 & (Ng1706 | ~Ng1700)); - assign n8716 = (~n8312 & ~Ng1700) | (~Ng1706 & (n8312 | ~Ng1700)); - assign n1616 = ~n8716; - assign n8718 = (~n8312 & ~Ng1682) | (~Ng1687 & (n8312 | ~Ng1682)); - assign n6012 = ~n8718; - assign n8720 = n9228 & (~Pg35 | n8245 | ~Ng142); - assign n1826_1 = ~n8720; - assign n8722 = (n8354 & (Ng5041 | n8356)) | (~Ng5041 & n8356); - assign n8723 = (n8353 & (Ng5033 | n8355)) | (~Ng5033 & n8355); - assign n8724 = ~n9238 & (Ng283 | n7834 | ~Ng287); - assign n3812_1 = ~n8724; - assign n8726 = (n7168 & (Pg35 | ~Ng4122)) | (~Pg35 & ~Ng4122); - assign n1201_1 = ~n8726; - assign n8728 = (~n7338 & ~Ng2681) | (~Ng2675 & (n7338 | ~Ng2681)); - assign n6017 = ~n8728; - assign n8730 = (~n7343 & ~Ng2547) | (~Ng2541 & (n7343 | ~Ng2547)); - assign n712 = ~n8730; - assign n8732 = (~n7348 & ~Ng2413) | (~Ng2407 & (n7348 | ~Ng2413)); - assign n6056 = ~n8732; - assign n8734 = (~n7353 & ~Ng2279) | (~Ng2273 & (n7353 | ~Ng2279)); - assign n3047 = ~n8734; - assign n8736 = (~n7358 & ~Ng2122) | (~Ng2116 & (n7358 | ~Ng2122)); - assign n1844_1 = ~n8736; - assign n8738 = (~n7363 & ~Ng1988) | (~Ng1982 & (n7363 | ~Ng1988)); - assign n6442 = ~n8738; - assign n8740 = (~n7368 & ~Ng1854) | (~Ng1848 & (n7368 | ~Ng1854)); - assign n4379_1 = ~n8740; - assign n8742 = (~n7373 & ~Ng1720) | (~Ng1714 & (n7373 | ~Ng1720)); - assign n5850_1 = ~n8742; - assign n8744 = (n8048 & Ng1413) | (~n8047 & (n8048 | ~Ng1413)); - assign n8745 = n9275 & (~Pg35 | n5559 | n8116); - assign n5681_1 = ~n8745; - assign n8747 = (n8050 & Ng1070) | (~n8049 & (n8050 | ~Ng1070)); - assign n8748 = n9276 & (~Pg35 | n4474 | n8118); - assign n4622 = ~n8748; - assign n8750 = (~n7407 & ~Ng6519) | (~Ng6513 & (n7407 | ~Ng6519)); - assign n2560_1 = ~n8750; - assign n8752 = (~n7438 & ~Ng6173) | (~Ng6167 & (n7438 | ~Ng6173)); - assign n4452 = ~n8752; - assign n8754 = (~n7469 & ~Ng5827) | (~Ng5821 & (n7469 | ~Ng5827)); - assign n3340_1 = ~n8754; - assign n8756 = (~n7500 & ~Ng5481) | (~Ng5475 & (n7500 | ~Ng5481)); - assign n5806 = ~n8756; - assign n8758 = (~n7530 & ~Ng5134) | (~Ng5128 & (n7530 | ~Ng5134)); - assign n1327_1 = ~n8758; - assign n8760 = ~n7559 & n8211 & (n8119 | n8317); - assign n8761 = ~n7564 & n8209 & (n8120 | n8316); - assign n8762 = (~n7571 & ~Ng3827) | (~Ng3821 & (n7571 | ~Ng3827)); - assign n3586_1 = ~n8762; - assign n8764 = (~n7602 & ~Ng3476) | (~Ng3470 & (n7602 | ~Ng3476)); - assign n2178 = ~n8764; - assign n8766 = (~n7631 & ~Ng3125) | (~Ng3119 & (n7631 | ~Ng3125)); - assign n6395 = ~n8766; - assign n8768 = ~n9315 & (Pg35 | ~Ng1478); - assign n1532_1 = ~n8768; - assign n8770 = ~Ng1489 & ~Ng1442; - assign n8771 = n8522 & n5170 & (Ng1484 | n8770); - assign n8772 = ~n9317 & (Pg35 | ~Ng1448); - assign n2530 = ~n8772; - assign n8774 = ~n9319 & (Pg35 | ~Ng1442); - assign n1433_1 = ~n8774; - assign n8776 = ~n9321 & (Pg35 | ~Ng1135); - assign n6114_1 = ~n8776; - assign n8778 = ~Ng1146 & ~Ng1099; - assign n8779 = n8527 & n4887 & (Ng1141 | n8778); - assign n8780 = ~n9323 & (Pg35 | ~Ng1105); - assign n4549 = ~n8780; - assign n8782 = ~n9325 & (Pg35 | ~Ng1099); - assign n6502 = ~n8782; - assign n8784 = n9331 & (~Pg35 | n8360 | n8362); - assign n5411_1 = ~n8784; - assign n8786 = n9332 & (~Pg35 | n8361 | n8363); - assign n5376_1 = ~n8786; - assign n8788 = n9333 & (~Ng4521 | (Pg35 & n9334)); - assign n4099 = ~n8788; - assign n8790 = n9335 & (Pg35 | ~Ng2841); - assign n5753 = ~n8790; - assign n8792 = (~n7797 & ~Ng4145) | (~Ng4112 & (n7797 | ~Ng4145)); - assign n5481_1 = ~n8792; - assign n8794 = (~Ng661 & ~n8475) | (~Ng728 & (~Ng661 | n8475)); - assign n6427 = ~n8794; - assign n8796 = (~Ng718 & ~n8475) | (~Ng661 & (~Ng718 | n8475)); - assign n3106 = ~n8796; - assign n8798 = (~Ng655 & ~n8475) | (~Ng718 & (~Ng655 | n8475)); - assign n1287_1 = ~n8798; - assign n8800 = (~Ng650 & ~n8475) | (~Ng655 & (~Ng650 | n8475)); - assign n3439 = ~n8800; - assign n8802 = (Pg35 & n8124) | (~\[4435] & (~Pg35 | n8124)); - assign n6531 = ~n8802; - assign n8804 = (~Ng645 & ~n8475) | (~Ng681 & (~Ng645 | n8475)); - assign n1732_1 = ~n8804; - assign n8806 = (n7839 & (Pg35 | ~Ng4512)) | (~Pg35 & ~Ng4512); - assign n1036_1 = ~n8806; - assign n8808 = (~Pg35 & ~Ng4459) | (~Ng4473 & (Pg35 | ~Ng4459)); - assign n2570 = ~n8808; - assign n8810 = (Pg35 & n9339) | (~Ng4462 & (~Pg35 | n9339)); - assign n3720_1 = ~n8810; - assign n8812 = (~Pg35 & ~Ng4558) | (~Pg6749 & (Pg35 | ~Ng4558)); - assign n4075 = ~n8812; - assign n8814 = (~Pg35 & ~Ng4561) | (~Pg6750 & (Pg35 | ~Ng4561)); - assign n2803_1 = ~n8814; - assign n8816 = (~Pg35 & ~Ng4555) | (~Pg6748 & (Pg35 | ~Ng4555)); - assign n1224_1 = ~n8816; - assign n8818 = (~Pg35 & ~Ng4489) | (~Pg6750 & (Pg35 | ~Ng4489)); - assign n1257_1 = ~n8818; - assign n8820 = (~Pg35 & ~Ng4486) | (~Pg6749 & (Pg35 | ~Ng4486)); - assign n4504 = ~n8820; - assign n8822 = (~Pg35 & ~Ng4483) | (~Pg6748 & (Pg35 | ~Ng4483)); - assign n2354_1 = ~n8822; - assign n8824 = (n9241 & (Pg35 | ~Ng4153)) | (~Pg35 & ~Ng4153); - assign n1925_1 = ~n8824; - assign n8826 = (Pg35 & n9240) | (~Ng4104 & (~Pg35 | n9240)); - assign n5864 = ~n8826; - assign n8828 = n9341 & (Pg35 | ~Ng2841); - assign n4211_1 = ~n8828; - assign n8830 = (n8128 & (Pg35 | ~Ng1532)) | (~Pg35 & ~Ng1532); - assign n5558_1 = ~n8830; - assign n8832 = n9342 & (~Pg35 | n8129 | Ng1322); - assign n3792 = ~n8832; - assign n8834 = (n8130 & (Pg35 | ~Ng1189)) | (~Pg35 & ~Ng1189); - assign n5898 = ~n8834; - assign n8836 = (Pg35 & n9343) | (~Ng890 & (~Pg35 | n9343)); - assign n3490 = ~n8836; - assign n8838 = n9344 & (Ng812 | (n8022 & Ng843)); - assign n8839 = (~Ng732 & n9345) | (~Ng753 & (~Ng732 | ~n9345)); - assign n1537_1 = ~n8839; - assign n8841 = n8468 & ~n9346 & (~Ng528 | n8469); - assign n8842 = (Pg35 & ~n8841) | (~Ng518 & (~Pg35 | ~n8841)); - assign n2232_1 = ~n8842; - assign n8844 = Pg35 & (Ng333 | Ng355); - assign n8845 = (~Ng351 & ~n8844) | (Pg35 & (Ng351 | ~n8844)); - assign n1979_1 = ~n8845; - assign n8847 = n9347 & (Pg35 | ~Ng347); - assign n1742_1 = ~n8847; - assign n8849 = (Ng347 & (Pg35 | ~Ng333)) | (~Pg35 & ~Ng333); - assign n3558 = ~n8849; - assign n8851 = n9348 & (Pg35 | ~\[4436] ); - assign n5151_1 = ~n8851; - assign n8853 = (Pg35 & ~Ng316) | (~\[4431] & (~Pg35 | ~Ng316)); - assign n3651_1 = ~n8853; - assign n8855 = (n7912 & (Pg35 | ~Ng336)) | (~Pg35 & ~Ng336); - assign n6027 = ~n8855; - assign n8857 = (n7918 & (Pg35 | ~Ng316)) | (~Pg35 & ~Ng316); - assign n6275 = ~n8857; - assign n8859 = (~Pg35 & ~Ng305) | (~Pg6744 & (Pg35 | ~Ng305)); - assign n895_1 = ~n8859; - assign n8861 = (n8381 & ~Ng6505) | (~Ng6541 & (~n8381 | ~Ng6505)); - assign n5136_1 = ~n8861; - assign n8863 = (Ng6533 & Ng6527) | (n8051 & (Ng6533 | ~Ng6527)); - assign n8864 = (~n8381 & ~Ng6527) | (~Ng6533 & (n8381 | ~Ng6527)); - assign n5541_1 = ~n8864; - assign n8866 = ~Pg9817 & (Ng6444 | (Pg9743 & ~Ng6494)); - assign n8867 = (~Pg35 & ~Ng6494) | (~n8866 & (Pg35 | ~Ng6494)); - assign n3755_1 = ~n8867; - assign n8869 = (Pg35 & ~Ng6727) | (~Ng6444 & (~Pg35 | ~Ng6727)); - assign n2306 = ~n8869; - assign n8871 = (n8386 & ~Ng6159) | (~Ng6195 & (~n8386 | ~Ng6159)); - assign n2007_1 = ~n8871; - assign n8873 = (Ng6187 & Ng6181) | (n8052 & (Ng6187 | ~Ng6181)); - assign n8874 = (~n8386 & ~Ng6181) | (~Ng6187 & (n8386 | ~Ng6181)); - assign n1893_1 = ~n8874; - assign n8876 = ~Pg9741 & (Ng6098 | (Pg9682 & ~Ng6148)); - assign n8877 = (~Pg35 & ~Ng6148) | (~n8876 & (Pg35 | ~Ng6148)); - assign n4187 = ~n8877; - assign n8879 = (Pg35 & ~Ng6381) | (~Ng6098 & (~Pg35 | ~Ng6381)); - assign n1068_1 = ~n8879; - assign n8881 = (n8390 & ~Ng5813) | (~Ng5849 & (~n8390 | ~Ng5813)); - assign n741_1 = ~n8881; - assign n8883 = (Ng5841 & Ng5835) | (n8053 & (Ng5841 | ~Ng5835)); - assign n8884 = (~n8390 & ~Ng5835) | (~Ng5841 & (n8390 | ~Ng5835)); - assign n6289 = ~n8884; - assign n8886 = ~Pg9680 & (Ng5752 | (Pg9617 & ~Ng5802)); - assign n8887 = (~Pg35 & ~Ng5802) | (~n8886 & (Pg35 | ~Ng5802)); - assign n2408_1 = ~n8887; - assign n8889 = (Pg35 & ~Ng6035) | (~Ng5752 & (~Pg35 | ~Ng6035)); - assign n2328_1 = ~n8889; - assign n8891 = (n8394 & ~Ng5467) | (~Ng5503 & (~n8394 | ~Ng5467)); - assign n3416 = ~n8891; - assign n8893 = (Ng5495 & Ng5489) | (n8054 & (Ng5495 | ~Ng5489)); - assign n8894 = (~n8394 & ~Ng5489) | (~Ng5495 & (n8394 | ~Ng5489)); - assign n2379_1 = ~n8894; - assign n8896 = ~Pg9615 & (Ng5406 | (Pg9555 & ~Ng5456)); - assign n8897 = (~Pg35 & ~Ng5456) | (~n8896 & (Pg35 | ~Ng5456)); - assign n2984_1 = ~n8897; - assign n8899 = (Pg35 & ~Ng5689) | (~Ng5406 & (~Pg35 | ~Ng5689)); - assign n2848_1 = ~n8899; - assign n8901 = (~n7934 & ~Ng5120) | (~Ng5156 & (n7934 | ~Ng5120)); - assign n4574 = ~n8901; - assign n8903 = (Ng5148 & Ng5142) | (n8055 & (Ng5148 | ~Ng5142)); - assign n8904 = (n7934 & ~Ng5142) | (~Ng5148 & (~n7934 | ~Ng5142)); - assign n6565 = ~n8904; - assign n8906 = ~Pg9497 & (Ng5022 | (Pg9553 & ~Ng5112)); - assign n8907 = (~Pg35 & ~Ng5112) | (~n8906 & (Pg35 | ~Ng5112)); - assign n2285_1 = ~n8907; - assign n8909 = ~Pg9553 & (Ng5062 | (Pg9497 & ~Ng5109)); - assign n8910 = (~Pg35 & ~Ng5109) | (~n8909 & (Pg35 | ~Ng5109)); - assign n5175_1 = ~n8910; - assign n8912 = (~Pg35 & ~Ng5062) | (~\[4415] & (Pg35 | ~Ng5062)); - assign n3009_1 = ~n8912; - assign n8914 = (Ng5069 & Ng5084) | (Ng5073 & (Ng5069 | ~Ng5084)); - assign n8915 = ~n9351 & (n7566 | ~Ng4057 | Ng4064); - assign n6250 = ~n8915; - assign n8917 = (n8401 & ~Ng3813) | (~Ng3849 & (~n8401 | ~Ng3813)); - assign n1072_1 = ~n8917; - assign n8919 = (Ng3841 & Ng3835) | (n8056 & (Ng3841 | ~Ng3835)); - assign n8920 = (~n8401 & ~Ng3835) | (~Ng3841 & (n8401 | ~Ng3835)); - assign n6507 = ~n8920; - assign n8922 = ~Pg8398 & (Ng3752 | (Pg8344 & ~Ng3802)); - assign n8923 = (~Pg35 & ~Ng3802) | (~n8922 & (Pg35 | ~Ng3802)); - assign n2743 = ~n8923; - assign n8925 = (Pg35 & ~Ng4040) | (~Ng3752 & (~Pg35 | ~Ng4040)); - assign n2668_1 = ~n8925; - assign n8927 = (n8405 & ~Ng3462) | (~Ng3498 & (~n8405 | ~Ng3462)); - assign n5456_1 = ~n8927; - assign n8929 = (Ng3490 & Ng3484) | (n8057 & (Ng3490 | ~Ng3484)); - assign n8930 = (~n8405 & ~Ng3484) | (~Ng3490 & (n8405 | ~Ng3484)); - assign n815_1 = ~n8930; - assign n8932 = ~Pg8342 & (Ng3401 | (Pg8279 & ~Ng3451)); - assign n8933 = (~Pg35 & ~Ng3451) | (~n8932 & (Pg35 | ~Ng3451)); - assign n6147 = ~n8933; - assign n8935 = (Pg35 & ~Ng3689) | (~Ng3401 & (~Pg35 | ~Ng3689)); - assign n6634 = ~n8935; - assign n8937 = (n8409 & ~Ng3111) | (~Ng3147 & (~n8409 | ~Ng3111)); - assign n1232_1 = ~n8937; - assign n8939 = (Ng3139 & Ng3133) | (n8058 & (Ng3139 | ~Ng3133)); - assign n8940 = (~n8409 & ~Ng3133) | (~Ng3139 & (n8409 | ~Ng3133)); - assign n2242_1 = ~n8940; - assign n8942 = ~Pg8277 & (Ng3050 | (Pg8215 & ~Ng3100)); - assign n8943 = (~Pg35 & ~Ng3100) | (~n8942 & (Pg35 | ~Ng3100)); - assign n1831_1 = ~n8943; - assign n8945 = (Pg35 & ~Ng3338) | (~Ng3050 & (~Pg35 | ~Ng3338)); - assign n5971_1 = ~n8945; - assign n8947 = n9352 & (~Pg35 | n8134 | n8510); - assign n6211 = ~n8947; - assign n8949 = ~n8510 & ((n8133 & Ng1559) | Ng1554); - assign n8950 = (Pg35 & ~n8949) | (~Ng1559 & (~Pg35 | ~n8949)); - assign n5705_1 = ~n8950; - assign n8952 = (Pg35 & n9354) | (~Ng1521 & (~Pg35 | n9354)); - assign n5446_1 = ~n8952; - assign n8954 = n9357 & (~Pg35 | n8136 | n8511); - assign n2275 = ~n8954; - assign n8956 = ~n8511 & ((n8135 & Ng1216) | Ng1211); - assign n8957 = (Pg35 & ~n8956) | (~Ng1216 & (~Pg35 | ~n8956)); - assign n5326_1 = ~n8957; - assign n8959 = (Pg35 & n9359) | (~Ng1178 & (~Pg35 | n9359)); - assign n2493 = ~n8959; - assign n8961 = (~n8027 & ~Ng817) | (~n7758 & (~n8027 | Ng817)); - assign n8962 = (n7983 & ~Ng686) | (~Ng667 & (~n7983 | ~Ng686)); - assign n4311_1 = ~n8962; - assign n8964 = (n8500 & ~Ng452) | (~Ng460 & (~n8500 | ~Ng452)); - assign n726_1 = ~n8964; - assign n8966 = (~Ng174 & n8500) | (~Ng182 & (~Ng174 | ~n8500)); - assign n1969_1 = ~n8966; - assign n8968 = (~Ng168 & n8500) | (~Ng174 & (~Ng168 | ~n8500)); - assign n2956_1 = ~n8968; - assign n8970 = (Pg35 & n9362) | (~Ng358 & (~Pg35 | n9362)); - assign n5568_1 = ~n8970; - assign n8972 = (Pg35 & n9363) | (~Ng370 & (~Pg35 | n9363)); - assign n5874 = ~n8972; - assign n8974 = (n9365 & (Pg35 | ~Ng191)) | (~Pg35 & ~Ng191); - assign n4707_1 = ~n8974; - assign n8976 = (Pg35 & n9367) | (~Ng222 & (~Pg35 | n9367)); - assign n4138_1 = ~n8976; - assign n8978 = (Pg35 & Ng218) | (~Ng209 & (~Pg35 | Ng218)); - assign n3267 = ~n8978; - assign n8980 = n9368 & (~Pg35 | ~n5006 | Ng6736); - assign n5441_1 = ~n8980; - assign n8982 = (Pg35 & n9369) | (~Ng6723 & (~Pg35 | n9369)); - assign n1557_1 = ~n8982; - assign n8984 = n9370 & (~Pg35 | ~n5604 | Ng6390); - assign n1792 = ~n8984; - assign n8986 = (Pg35 & n9371) | (~Ng6377 & (~Pg35 | n9371)); - assign n4904 = ~n8986; - assign n8988 = n9372 & (~Pg35 | ~n5069_1 | Ng6044); - assign n2999_1 = ~n8988; - assign n8990 = (Pg35 & n9373) | (~Ng6031 & (~Pg35 | n9373)); - assign n6240 = ~n8990; - assign n8992 = n9374 & (~Pg35 | ~n5837 | Ng5698); - assign n5573_1 = ~n8992; - assign n8994 = (Pg35 & n9375) | (~Ng5685 & (~Pg35 | n9375)); - assign n3215 = ~n8994; - assign n8996 = n9376 & (~Pg35 | ~n5715 | Ng5352); - assign n6575 = ~n8996; - assign n8998 = (Pg35 & n9377) | (~Ng5339 & (~Pg35 | n9377)); - assign n1307_1 = ~n8998; - assign n9000 = (Pg35 & n9378) | (~Ng4308 & (~Pg35 | n9378)); - assign n2212 = ~n9000; - assign n9002 = (Pg35 & ~n9383) | (~Ng4235 & (~Pg35 | ~n9383)); - assign n4539 = ~n9002; - assign n9004 = n9384 & (~Pg35 | ~n4631_1 | Ng4049); - assign n2525 = ~n9004; - assign n9006 = (Pg35 & n9385) | (~Ng4031 & (~Pg35 | n9385)); - assign n707_1 = ~n9006; - assign n9008 = n9386 & (~Pg35 | ~n4267 | Ng3698); - assign n5801 = ~n9008; - assign n9010 = (Pg35 & n9387) | (~Ng3680 & (~Pg35 | n9387)); - assign n3476_1 = ~n9010; - assign n9012 = n9388 & (~Pg35 | ~n5184 | Ng3347); - assign n1669_1 = ~n9012; - assign n9014 = (Pg35 & n9389) | (~Ng3329 & (~Pg35 | n9389)); - assign n2979_1 = ~n9014; - assign n9016 = (Pg35 & ~Ng496) | (~Ng1554 & (~Pg35 | ~Ng496)); - assign n6052_1 = ~n9016; - assign n9018 = (Pg35 & n9391) | (~Ng1339 & (~Pg35 | n9391)); - assign n944_1 = ~n9018; - assign n9020 = (Pg35 & n9392) | (~Ng1306 & (~Pg35 | n9392)); - assign n1572_1 = ~n9020; - assign n9022 = (Pg35 & n9393) | (~Ng1526 & (~Pg35 | n9393)); - assign n6600 = ~n9022; - assign n9024 = (n7731 & ~Ng1495) | (~Ng1442 & (~n7731 | ~Ng1495)); - assign n1485_1 = ~n9024; - assign n9026 = (~n7731 & ~Ng1495) | (~Ng1489 & (n7731 | ~Ng1495)); - assign n1428_1 = ~n9026; - assign n9028 = (~Pg35 & ~Ng1211) | (~\[4432] & (Pg35 | ~Ng1211)); - assign n2169_1 = ~n9028; - assign n9030 = (Pg35 & n9395) | (~Ng996 & (~Pg35 | n9395)); - assign n3515 = ~n9030; - assign n9032 = (Pg35 & n9396) | (~Ng962 & (~Pg35 | n9396)); - assign n1596_1 = ~n9032; - assign n9034 = (Pg35 & n9397) | (~Ng1183 & (~Pg35 | n9397)); - assign n1277_1 = ~n9034; - assign n9036 = (n7735 & ~Ng1152) | (~Ng1099 & (~n7735 | ~Ng1152)); - assign n1122_1 = ~n9036; - assign n9038 = (~n7735 & ~Ng1152) | (~Ng1146 & (n7735 | ~Ng1152)); - assign n5298 = ~n9038; - assign n9040 = (n7758 & ~Ng854) | (~Ng847 & (~n7758 | ~Ng854)); - assign n785_1 = ~n9040; - assign n9042 = (~n7758 & ~Ng441) | (~Ng475 & (n7758 | ~Ng441)); - assign n3004_1 = ~n9042; - assign n9044 = (n7758 & ~Ng441) | (~Ng437 & (~n7758 | ~Ng441)); - assign n1737_1 = ~n9044; - assign n9046 = (~n7758 & ~Ng429) | (~Ng433 & (n7758 | ~Ng429)); - assign n4777_1 = ~n9046; - assign n9048 = (n7758 & ~Ng429) | (~Ng401 & (~n7758 | ~Ng429)); - assign n2994_1 = ~n9048; - assign n9050 = (~n7758 & ~Ng424) | (~Ng411 & (n7758 | ~Ng424)); - assign n5344_1 = ~n9050; - assign n9052 = (~n7758 & ~Ng405) | (~Ng392 & (n7758 | ~Ng405)); - assign n3223_1 = ~n9052; - assign n9054 = (Pg35 & n9401) | (~Ng2946 & (~Pg35 | n9401)); - assign n5884 = ~n9054; - assign n9056 = (Pg35 & n9402) | (~Ng4239 & (~Pg35 | n9402)); - assign n3788_1 = ~n9056; - assign n9058 = (n8540 & (Pg35 | ~Ng4291)) | (~Pg35 & ~Ng4291); - assign n4272_1 = ~n9058; - assign n9060 = (n8541 & (Pg35 | ~Ng4284)) | (~Pg35 & ~Ng4284); - assign n5007 = ~n9060; - assign n9062 = (n8542 & (Pg35 | ~Ng4281)) | (~Pg35 & ~Ng4281); - assign n6512 = ~n9062; - assign n9064 = (Pg35 & n8543) | (~Ng4245 & (~Pg35 | n8543)); - assign n4160_1 = ~n9064; - assign n9066 = (Pg35 & Ng4239) | (~Ng4273 & (~Pg35 | Ng4239)); - assign n6522 = ~n9066; - assign n9068 = (Pg35 & n9379) | (~Ng4180 & (~Pg35 | n9379)); - assign n2384_1 = ~n9068; - assign n9070 = n6045 | ~Ng2882; - assign n9071 = ~Ng534 | n8159; - assign n9072 = (n8153 | ~Ng16) & (n6020 | n8142); - assign n9073 = n6015 | ~Ng790; - assign n9074 = ~n5992 & n9073 & (n6027_1 | ~Ng749); - assign n9075 = (n6063 | ~Ng608) & (n8159 | Ng550); - assign n9076 = n9075 & (~Ng572 | n8157); - assign n9077 = (n8153 | ~Ng50) & (n6046 | n8142); - assign n9078 = (n6045 | ~Ng2886) & (~Ng2980 | n8174); - assign n9079 = n6063 | ~Ng604; - assign n9080 = (n8153 | ~Ng51) & (n6032 | n8142); - assign n9081 = (n8161 | ~Ng1283) & (n8171 | ~Ng2138); - assign n9082 = n6063 | ~Ng599; - assign n9083 = ~n5992 & n9082 & (n8157 | ~Ng562); - assign n9084 = (n6015 | ~Ng781) & (n6027_1 | ~Ng739); - assign n9085 = n9084 & (n8159 | ~Ng199); - assign n9086 = (n8153 | ~Ng52) & (n6038 | n8142); - assign n9087 = (n6045 | ~Ng2848) & (n6056_1 | ~Ng2902); - assign n9088 = (n6031 | ~Ng2907) & (n6080 | ~Ng2844); - assign n9089 = (~Ng1300 | n8175) & (~Ng956 | n8176); - assign n9090 = (Pg35 | n8158) & (n6027_1 | ~Ng772); - assign n9091 = (n6063 | ~Ng626) & (~Ng590 | n8157); - assign n9092 = (~Ng1472 | n8175) & (~Ng1129 | n8176); - assign n9093 = n6015 | ~Ng554; - assign n9094 = (~Ng1448 | n8175) & (~Ng1105 | n8176); - assign n9095 = (n8153 | ~Ng8) & (n8171 | ~Ng5507); - assign n9096 = n6045 | ~Ng2898; - assign n9097 = n6063 | ~Ng617; - assign n9098 = (~Ng1478 | n8175) & (~Ng1135 | n8176); - assign n9099 = (n8153 | ~Ng48) & (n8168 | ~Ng4912); - assign n9100 = (n8188 | n8189) & (n8190 | n7619); - assign n9101 = (n5730 | n7578) & (n8191 | n7414); - assign n9102 = (n7404 | ~n7942) & (n7466 | ~n8218); - assign n9103 = (n7599 | ~n8220) & (n6261 | n7527); - assign n9104 = (n7435 | ~n8218) & (n7628 | ~n7942); - assign n9105 = (n7568 | ~n8220) & (n6261 | n7497); - assign n9106 = ~n5923 & (n8260 | ~Ng2643); - assign n9107 = ~n5942 & (n8267 | ~Ng2509); - assign n9108 = ~n5956_1 & (n8274 | ~Ng2375); - assign n9109 = ~n5953 & (n8281 | ~Ng2241); - assign n9110 = ~n5944 & (n8289 | ~Ng2084); - assign n9111 = ~n5948 & (n8296 | ~Ng1950); - assign n9112 = ~n5898_1 & (n8303 | ~Ng1816); - assign n9113 = ~n5954 & (n8310 | ~Ng1682); - assign n9114 = ~n6268 & n8330; - assign n9115 = Pg35 & (~n6634_1 | (~Ng1373 & n8333)); - assign n9116 = Pg35 & (~n6641 | (~Ng1030 & n8339)); - assign n9117 = ~n8102 & (n6882 | (~n5880 & ~n8105)); - assign n9118 = (Ng2236 | n8373) & (Ng2370 | n7957); - assign n9119 = (n7957 | ~Ng2807) & (~Ng2803 | n8373); - assign n9120 = (Ng1945 | n8370) & (Ng2079 | n8255); - assign n9121 = (n7957 | ~Ng2775) & (~Ng2771 | n8373); - assign n9122 = ~Ng6645 | ~Pg17688 | n7423; - assign n9123 = ~Ng6653 | ~Pg17688 | n7426; - assign n9124 = ~Ng6283 | ~Pg17760 | n7445; - assign n9125 = ~Ng6275 | ~Pg14779 | n7457; - assign n9126 = ~Ng5953 | ~Pg17607 | n7485; - assign n9127 = ~Ng5961 | ~Pg17607 | n7488; - assign n9128 = ~Ng5607 | ~Pg17580 | n7516; - assign n9129 = ~Ng5615 | ~Pg17580 | n7519; - assign n9130 = ~Ng5260 | ~Pg17519 | n7545; - assign n9131 = ~Ng5252 | ~Pg17674 | n6516; - assign n9132 = (~Ng4836 | ~Ng5011) & (~Ng4864 | Ng3333); - assign n9133 = (~Ng4871 | ~Ng3684) & (~Ng4878 | Ng4035); - assign n9134 = (~\[4427] | ~Ng4646) & (~Ng4674 | Ng4821); - assign n9135 = (~Ng4681 | ~Ng4831) & (~Ng4688 | Ng4826); - assign n9136 = ~Ng3953 | ~Pg16659 | n7587; - assign n9137 = ~Ng3945 | ~Pg16775 | n6525; - assign n9138 = ~Ng3602 | ~Pg16627 | n8455; - assign n9139 = ~Ng3578 | ~Pg13926 | n8455; - assign n9140 = ~Ng3235 | ~Pg16718 | n8189; - assign n9141 = ~Ng3227 | ~Pg13895 | n7649; - assign n9142 = (n6537 & (n8189 | Ng3347)) | (n8189 & ~Ng3347); - assign n9143 = (n7638 & (~Ng3343 | n7649)) | (Ng3343 & n7649); - assign n9144 = ~n8328 & (Ng4939 | (n9142 & n9143)); - assign n9145 = (~Ng5694 & n7519) | (n7516 & (Ng5694 | n7519)); - assign n9146 = (n8321 & Ng5698) | (n7507 & (n8321 | ~Ng5698)); - assign n9147 = ~n8322 & (Ng4749 | (n9145 & n9146)); - assign n9148 = ~Ng979 & (~n7888 | ~Ng1061 | ~Ng1052); - assign n9149 = Ng832 & (~n7758 | (Pg35 & ~Ng817)); - assign n9150 = (~Pg35 | Pg19357) & (~Ng1395 | n8005); - assign n9151 = Pg17316 | Pg17400 | Pg17291; - assign n9152 = (n8014 | ~Ng1052) & (~Pg35 | Pg19334); - assign n9153 = Pg35 & (n6089 | Ng2984); - assign n9154 = Ng753 | Ng655 | Ng718; - assign n9155 = ~Ng4332 & (n5967 | (Pg90 & ~Ng2994)); - assign n9156 = ~Ng4322 & (n9155 | (Ng4332 & Ng4311)); - assign n9157 = ~Ng4332 & Ng4322 & (n5967 | ~Ng4515); - assign n9158 = Ng4608 | ~Ng4593 | Ng4601 | ~Ng4584; - assign n9159 = ~Ng4349 & (Ng4340 | n9156 | n9157); - assign n9160 = ~n9159 & (n5729 | Ng4340 | ~Ng4349); - assign n9161 = (Ng4340 & ~Ng4349) | (n5729 & (~Ng4340 | ~Ng4349)); - assign n9162 = (n9160 & (~Ng4358 | n9161)) | (Ng4358 & n9161); - assign n9163 = ~Pg91 | n4212 | n4213 | Ng2965; - assign n9164 = n9163 & Pg35; - assign n9165 = n4206_1 | n4207 | n4209 | n4210 | Ng2955 | n8214 | ~n8215 | Ng2946; - assign n9166 = n9165 & Pg35; - assign n9167 = Ng2941 | Ng4072 | Ng4153; - assign n9168 = n9167 & Pg35; - assign n9169 = Pg35 & ~n9426; - assign n9170 = Ng2932 | ~Pg44 | Ng2927; - assign n9171 = n9170 & Pg35; - assign n9172 = Pg35 & ~n9427; - assign n9173 = n5969 | Ng301 | Ng2902; - assign n9174 = n9173 & Pg35; - assign n9175 = Ng2882 | n4213 | n4212; - assign n9176 = n9175 & Pg35; - assign n9177 = Ng2856 | n4209 | n4210; - assign n9178 = n9177 & Pg35; - assign n9179 = Ng2848 | n4207 | n4206_1; - assign n9180 = n9179 & Pg35; - assign n9181 = n9103 & ~Ng4087 & n9102; - assign n9182 = n9105 & n9104 & Ng4087; - assign n9183 = (~Ng2724 & ~Ng2803) | (~Ng2807 & (Ng2724 | ~Ng2803)); - assign n9184 = (~Ng2724 & ~Ng2815) | (~Ng2819 & (Ng2724 | ~Ng2815)); - assign n9185 = (~Ng2724 & ~Ng2771) | (~Ng2775 & (Ng2724 | ~Ng2771)); - assign n9186 = (~Ng2724 & ~Ng2783) | (~Ng2787 & (Ng2724 | ~Ng2783)); - assign n9187 = Pg35 | ~Ng2894; - assign n9188 = ~Pg35 | ~Ng1291; - assign n9189 = ~Pg35 | ~Ng947; - assign n9190 = Ng4878 & (~Pg35 | (~Ng4843 & n8228)); - assign n9191 = Ng4688 & (~Pg35 | (~Ng4653 & n8230)); - assign n9192 = (~n6203 & n6204) | (~Ng4340 & (n6203 | n6204)); - assign n9193 = Pg35 | ~Ng2827; - assign n9194 = Pg35 | ~Ng2815; - assign n9195 = Pg35 | ~Ng2819; - assign n9196 = Pg35 | ~Ng2807; - assign n9197 = Pg35 | ~Ng2795; - assign n9198 = Pg35 | ~Ng2783; - assign n9199 = Pg35 | ~Ng2787; - assign n9200 = Pg35 | ~Ng2775; - assign n9201 = (Ng392 & ~Ng452) | (~Ng174 & (~Ng392 | ~Ng452)); - assign n9202 = (~Ng405 & ~Ng424) | (~Ng437 & (Ng405 | ~Ng424)); - assign n9203 = (~Ng405 & ~Ng437) | (~Ng401 & (Ng405 | ~Ng437)); - assign n9204 = (n9202 & (~Ng392 | n9203)) | (Ng392 & n9203); - assign n9205 = n7768 & n8237; - assign n9206 = (~Ng4955 & n9205) | (n6274 & (~Ng4955 | ~n9205)); - assign n9207 = n7773 & n8237; - assign n9208 = (~Ng4944 & n9207) | (n6275_1 & (~Ng4944 | ~n9207)); - assign n9209 = n6125 & n8237; - assign n9210 = (~Ng4888 & n9209) | (n6280 & (~Ng4888 | ~n9209)); - assign n9211 = n7784 & n8239; - assign n9212 = (~Ng4765 & n9211) | (n6282 & (~Ng4765 | ~n9211)); - assign n9213 = n7789 & n8239; - assign n9214 = (~Ng4754 & n9213) | (n6283 & (~Ng4754 | ~n9213)); - assign n9215 = n7796 & n8239; - assign n9216 = (~Ng4698 & n9215) | (n6288 & (~Ng4698 | ~n9215)); - assign n9217 = Pg35 | ~Ng4340; - assign n9218 = ~Ng157 | n8250; - assign n9219 = Ng4512 | Ng4581; - assign n9220 = (n5967 & ~n8641) | (n8036 & (~n5967 | ~n8641)); - assign n9221 = Ng4552 | Ng4581; - assign n9222 = (n5967 & ~n8644) | (n8038 & (~n5967 | ~n8644)); - assign n9223 = Pg35 | ~Ng2759; - assign n9224 = n8320 | ~n5876 | n8188; - assign n9225 = Pg35 & n9224 & (~n7519 | ~n8673); - assign n9226 = Pg35 | ~Ng4108; - assign n9227 = Pg35 | ~Ng2756; - assign n9228 = Pg35 | ~Ng301; - assign n9229 = ~Ng5046 | n8354 | ~Ng5041; - assign n9230 = (n8357 & (~Ng5052 | n9229)) | (Ng5052 & n9229); - assign n9231 = Pg35 | ~Ng4098; - assign n9232 = ~Ng5033 & (~n8353 | (Pg35 & ~n8355)); - assign n9233 = ~Ng5052 & (~n9229 | (Pg35 & ~n8357)); - assign n9234 = Pg35 | ~Ng5041; - assign n9235 = Pg35 | ~Ng5037; - assign n9236 = Pg35 | ~Ng5033; - assign n9237 = Pg35 | ~Ng5022; - assign n9238 = Ng283 & (~Pg35 | (~Ng287 & n8241)); - assign n9239 = ~Ng4473 | Ng4459; - assign n9240 = (~Pg120 & ~Ng4146) | (~Pg124 & (~Pg120 | Ng4146)); - assign n9241 = (~Pg114 & ~Ng4157) | (~Pg116 & (~Pg114 | Ng4157)); - assign n9242 = (~Ng2504 & ~Ng2715) | (~Ng2638 & (~Ng2504 | Ng2715)); - assign n9243 = (Ng2819 & (Ng2815 | Ng2715)) | (Ng2815 & ~Ng2715); - assign n9244 = ~n8206 | n5866 | Ng2735; - assign n9245 = n9244 & (~n9118 | (Ng2719 & n9242)); - assign n9246 = ~n9244 & (~n9119 | (Ng2719 & n9243)); - assign n9247 = (~Ng1677 & ~Ng2715) | (~Ng1811 & (~Ng1677 | Ng2715)); - assign n9248 = (Ng2787 & (Ng2783 | Ng2715)) | (Ng2783 & ~Ng2715); - assign n9249 = n9244 & (~n9120 | (~Ng2719 & n9247)); - assign n9250 = ~n9244 & (~n9121 | (Ng2719 & n9248)); - assign n9251 = Ng2681 & (~Pg35 | (Ng2675 & n8413)); - assign n9252 = Pg35 & Ng2657 & (~n5920 | n8415); - assign n9253 = Pg35 & Ng2595 & (~n5920 | n8205); - assign n9254 = Ng2547 & (~Pg35 | (Ng2541 & n8417)); - assign n9255 = Pg35 & Ng2523 & (~n5919 | n8419); - assign n9256 = Pg35 & Ng2461 & (~n5919 | n8203); - assign n9257 = Ng2413 & (~Pg35 | (Ng2407 & n8420)); - assign n9258 = Pg35 & Ng2389 & (~n5925 | n8422); - assign n9259 = Pg35 & Ng2327 & (~n5925 | n8204); - assign n9260 = Ng2279 & (~Pg35 | (Ng2273 & n8423)); - assign n9261 = Pg35 & Ng2255 & (~n5878 | n8425); - assign n9262 = Pg35 & Ng2193 & (~n5878 | n8197); - assign n9263 = Ng2122 & (~Pg35 | (Ng2116 & n8427)); - assign n9264 = Pg35 & Ng2098 & (~n5916 | n8429); - assign n9265 = Pg35 & Ng2036 & (~n5916 | n8201); - assign n9266 = Ng1988 & (~Pg35 | (Ng1982 & n8430)); - assign n9267 = Pg35 & Ng1964 & (~n5899 | n8432); - assign n9268 = Pg35 & Ng1902 & (~n5899 | n8202); - assign n9269 = Ng1854 & (~Pg35 | (Ng1848 & n8433)); - assign n9270 = Pg35 & Ng1830 & (~n5941 | n8435); - assign n9271 = Pg35 & Ng1768 & (~n5941 | n8199); - assign n9272 = Ng1720 & (~Pg35 | (Ng1714 & n8436)); - assign n9273 = Pg35 & Ng1696 & (~n5868 | n8438); - assign n9274 = Pg35 & Ng1632 & (~n5868 | n8207); - assign n9275 = Pg35 | ~Ng1536; - assign n9276 = Pg35 | ~Ng1193; - assign n9277 = Ng6519 & (~Pg35 | (~n8440 & Ng6513)); - assign n9278 = Ng6500 & (~Pg35 | (~n8440 & ~Ng6505)); - assign n9279 = ~Pg12470 ^ Ng6727; - assign n9280 = Pg35 & Ng6500 & (~n5884_1 | n8512); - assign n9281 = Ng6173 & (~Pg35 | (~n8442 & Ng6167)); - assign n9282 = Ng6154 & (~Pg35 | (~n8442 & ~Ng6159)); - assign n9283 = ~Pg12422 ^ Ng6381; - assign n9284 = Pg35 & Ng6154 & (~n5952 | ~n8513); - assign n9285 = Ng5827 & (~Pg35 | (~n8444 & Ng5821)); - assign n9286 = Ng5808 & (~Pg35 | (~n8444 & ~Ng5813)); - assign n9287 = ~Pg12350 ^ Ng6035; - assign n9288 = Pg35 & Ng5808 & (~n5940 | n8514); - assign n9289 = Ng5481 & (~Pg35 | (~n8446 & Ng5475)); - assign n9290 = (~Pg35 | (~n8446 & ~Ng5467)) & Ng5462; - assign n9291 = ~Pg12300 ^ Ng5689; - assign n9292 = Pg35 & Ng5462 & (~n5876 | n8515); - assign n9293 = Ng5134 & (~Pg35 | (~n8449 & Ng5128)); - assign n9294 = Ng5115 & (~Pg35 | (~n8449 & ~Ng5120)); - assign n9295 = ~\[4415] ^ Pg12238; - assign n9296 = Pg35 & Ng5115 & (~n4151_1 | n8516); - assign n9297 = ~Ng4983 & (n7555 | Ng4991); - assign n9298 = n9133 & n9132 & n4483; - assign n9299 = ~Ng4793 & (n7560 | Ng4801); - assign n9300 = n9135 & n9134 & n4637; - assign n9301 = Ng3827 & (~Pg35 | (~n8451 & Ng3821)); - assign n9302 = Ng3808 & (~Pg35 | (~n8451 & ~Ng3813)); - assign n9303 = ~Pg11418 ^ Ng4040; - assign n9304 = Pg35 & Ng3808 & (~n5927 | n8517); - assign n9305 = Ng3476 & (~Pg35 | (~n8453 & Ng3470)); - assign n9306 = Ng3457 & (~Pg35 | (~n8453 & ~Ng3462)); - assign n9307 = ~Pg11388 ^ Ng3689; - assign n9308 = Pg35 & Ng3457 & (~n5889 | n8518); - assign n9309 = Ng3125 & (~Pg35 | (~n8456 & Ng3119)); - assign n9310 = (~Pg35 | (~n8456 & ~Ng3111)) & Ng3106; - assign n9311 = ~Pg11349 ^ Ng3338; - assign n9312 = Pg35 & Ng3106 & (~n5908 | n8519); - assign n9313 = Pg35 | ~Ng2729; - assign n9314 = n8521 & n8458 & (Ng1454 | n8770); - assign n9315 = Pg35 & (n9314 | (~n8458 & Ng1454)); - assign n9316 = n8523 & n8459 & (Ng1467 | n8770); - assign n9317 = Pg35 & (n9316 | (~n8459 & Ng1467)); - assign n9318 = n8524 & n8460 & (Ng1437 | n8770); - assign n9319 = Pg35 & (n9318 | (~n8460 & Ng1437)); - assign n9320 = n8526 & n8461 & (Ng1111 | n8778); - assign n9321 = Pg35 & (n9320 | (~n8461 & Ng1111)); - assign n9322 = n8528 & n8462 & (Ng1124 | n8778); - assign n9323 = Pg35 & (n9322 | (~n8462 & Ng1124)); - assign n9324 = n8529 & n8463 & (Ng1094 | n8778); - assign n9325 = Pg35 & (n9324 | (~n8463 & Ng1094)); - assign n9326 = Ng827 & ~n8464; - assign n9327 = ~Ng676 | ~n8467; - assign n9328 = Pg35 | ~Ng482; - assign n9329 = ~Ng417 ^ n9204; - assign n9330 = Ng417 & (~Pg35 | (~n7976 & n9329)); - assign n9331 = Pg35 | ~Ng5057; - assign n9332 = Pg35 | ~Ng5069; - assign n9333 = Ng4521 | ~Pg35 | n5729; - assign n9334 = ~n8126 ^ Ng4527; - assign n9335 = ~Ng26936 | ~Pg35 | Ng4125; - assign n9336 = Pg35 | ~Ng4082; - assign n9337 = Pg35 | ~Ng1351; - assign n9338 = Pg35 | ~Ng1008; - assign n9339 = Ng10384 | Ng4473; - assign n9340 = n8126 & (~Pg35 | Ng4527); - assign n9341 = ~Ng26936 | ~Pg35 | Ng2712; - assign n9342 = Pg35 | ~Ng1395; - assign n9343 = (~Ng896 & ~Ng862) | (Ng890 & (Ng896 | ~Ng862)); - assign n9344 = ~Ng812 | ~n7758 | n7905; - assign n9345 = ~Pg35 | n5960; - assign n9346 = ~Ng528 & (n5933 | n8469); - assign n9347 = ~Pg35 | ~Pg7540 | Ng347; - assign n9348 = ~Pg35 | ~Ng329 | ~n8493 | Ng341; - assign n9349 = ~Pg35 | Ng311 | Ng305 | Ng26885; - assign n9350 = n7941 & ~Ng5080 & (Ng5069 | ~Ng5077); - assign n9351 = Ng4064 & (~Pg35 | (~Ng4057 & Ng2841)); - assign n9352 = Pg35 | ~Ng1564; - assign n9353 = ~Ng1526 | n7379; - assign n9354 = (~Ng1306 & n9353) | (~Ng1339 & (~Ng1306 | ~n9353)); - assign n9355 = ~n8082 & Ng1389; - assign n9356 = Ng1351 & (n9355 | n7964); - assign n9357 = Pg35 | ~Ng1221; - assign n9358 = ~Ng1183 | n7389; - assign n9359 = (~Ng962 & n9358) | (~Ng996 & (~Ng962 | ~n9358)); - assign n9360 = ~n8083 & Ng1046; - assign n9361 = Ng1008 & (n9360 | n7972); - assign n9362 = ~n6252 ^ Ng370; - assign n9363 = ~Ng376 ^ Ng358; - assign n9364 = ~Pg8358 ^ Ng191; - assign n9365 = (~Ng209 & (~n8501 | n9364)) | (n8501 & n9364); - assign n9366 = n8501 & n9364; - assign n9367 = ~Pg8358 ^ n9366; - assign n9368 = Pg35 | ~Ng6727; - assign n9369 = ~Ng6727 ^ n8502; - assign n9370 = Pg35 | ~Ng6381; - assign n9371 = n8503 ^ Ng6381; - assign n9372 = Pg35 | ~Ng6035; - assign n9373 = ~Ng6035 ^ n8504; - assign n9374 = Pg35 | ~Ng5689; - assign n9375 = ~Ng5689 ^ n8505; - assign n9376 = Pg35 | ~\[4415] ; - assign n9377 = n8506 ^ \[4415] ; - assign n9378 = ~Pg9251 ^ Ng4308; - assign n9379 = (Ng4145 & (~Ng4253 | Ng4164)) | (Ng4253 & Ng4164); - assign n9380 = ~Pg8870 | Ng4235; - assign n9381 = Pg8918 | Pg8917 | Pg8920 | Pg8919 | Pg11770 | Pg8916 | Pg8915; - assign n9382 = n9380 & (Pg8870 | (~Ng4235 & n9381)); - assign n9383 = n9382 ^ n9379; - assign n9384 = Pg35 | ~Ng4040; - assign n9385 = n8507 ^ Ng4040; - assign n9386 = Pg35 | ~Ng3689; - assign n9387 = n8508 ^ Ng3689; - assign n9388 = Pg35 | ~Ng3338; - assign n9389 = n8509 ^ Ng3338; - assign n9390 = Pg13272 | Pg7946 | Pg19357 | Ng1333 | Pg8475; - assign n9391 = n8007 ^ n9390; - assign n9392 = (~Pg7946 & ~Ng1532) | (~Ng1521 & (Pg7946 | ~Ng1532)); - assign n9393 = (~Pg7946 & ~Ng1521) | (~Ng1339 & (Pg7946 | ~Ng1521)); - assign n9394 = Pg13259 | Pg7916 | Pg19334 | Ng990 | Pg8416; - assign n9395 = n8016 ^ n9394; - assign n9396 = (~Pg7916 & ~Ng1189) | (~Ng1178 & (Pg7916 | ~Ng1189)); - assign n9397 = (~Pg7916 & ~Ng1178) | (~Ng996 & (Pg7916 | ~Ng1178)); - assign n9398 = n8027 | ~Ng822 | ~Ng817 | ~Ng723; - assign n9399 = ~Pg8786 | Ng4180; - assign n9400 = Pg8785 | Pg8787 | Pg8783 | Pg8784 | Pg11447 | Pg8788 | Pg8789; - assign n9401 = n9399 & (Pg8786 | (~Ng4180 & n9400)); - assign n9402 = Ng4297 | Pg10122; - assign n1335_1 = ~n6714; - assign n1472_1 = Pg35 & Pg113; - assign n2083 = ~n6734; - assign n2136 = ~n6202; - assign n3336 = ~n6683; - assign n3524 = ~n6693; - assign n3847_1 = Pg35 & Pg64; - assign n4156_1 = ~n6724; - assign n4331_1 = ~n7967; - assign n4369 = ~n7975; - assign n4587_1 = ~n7852; - assign n5686 = ~n7997; - assign n6226 = ~n6664; - assign n1242_1 = Pg35 & Pg125; - assign n9417 = Ng4125 | n6263 | Ng4057 | Ng4064; - assign n9418 = n5947 | n9181 | n9182; - assign n9419 = n8319 | n5730 | ~n5927; - assign n9420 = n8319 | ~n5884_1 | n8191; - assign n9421 = n8320 | n5730 | ~n5952; - assign n9422 = n8320 | ~n4151_1 | n8191; - assign n9423 = n8320 | ~n5940 | n8190; - assign n9424 = n8319 | ~n5889 | n8190; - assign n9425 = n8319 | ~n5908 | n8188; - assign n9426 = n4218 & n4219 & ~Ng2975; - assign n9427 = ~n8478 & n4217 & ~Ng2917; - assign n9428 = n8329 & n8067 & n5911 & ~n6273; - assign n9429 = n8329 & n8069 & n5872 & ~n6269; - assign n9430 = n8329 & n8071 & n5910 & ~n6270_1; - assign n9431 = n8329 & n8073 & n5873 & ~n6271; - assign n9432 = n8329 & n8075 & n5921 & ~n6267; - assign n9433 = n8329 & n8077 & n5887 & ~n6272; - assign n9434 = n8329 & n8079 & n5894 & ~n6266; - assign n9435 = n8329 & n8081 & n4162 & ~n6268; - assign n9436 = n7979 & n5983 & n7978 & n5984; - assign n9437 = ~Ng1389 & n7879 & ~n8484; - assign n9438 = ~Ng1046 & n7890 & ~n8489; - assign n9439 = n8229 & ~n6193 & Ng4849; - assign n9440 = n8231 & ~n6198 & Ng4659; - assign n9441 = Ng608 & n6259 & ~n8183; - assign n9442 = Ng604 & n6297_1 & ~n8183; - assign n9443 = n6361 & Ng2449 & Pg35; - assign n9444 = n6379 & Ng2315 & Pg35; - assign n9445 = n6454 & Ng1756 & Pg35; - assign n9446 = Ng599 & n6490 & ~n8183; - assign n9447 = Ng595 & n6649 & ~n8183; - assign n9448 = Ng590 & n6839 & ~n8183; - assign n9449 = n6654 & Ng6597 & Pg35; - assign n9450 = n6900 & Ng6653 & Pg35; - assign n9451 = n6914 & Ng6633 & Pg35; - assign n9452 = n6970 & Ng6287 & Pg35; - assign n9453 = n6972 & Ng6283 & Pg35; - assign n9454 = n6977 & Ng6275 & Pg35; - assign n9455 = n6673 & Ng5905 & Pg35; - assign n9456 = n7008 & Ng5961 & Pg35; - assign n9457 = n7022 & Ng5941 & Pg35; - assign n9458 = n6682 & Ng5559 & Pg35; - assign n9459 = n7077 & Ng5595 & Pg35; - assign n9460 = n7124 & Ng5260 & Pg35; - assign n9461 = n7129 & Ng5252 & Pg35; - assign n9462 = n7131 & Ng5248 & Pg35; - assign n9463 = n7187 & Ng3953 & Pg35; - assign n9464 = n7192 & Ng3945 & Pg35; - assign n9465 = n7194 & Ng3941 & Pg35; - assign n9466 = n7241 & Ng3602 & Pg35; - assign n9467 = n7249 & Ng3590 & Pg35; - assign n9468 = n7257 & Ng3578 & Pg35; - assign n9469 = n7304 & Ng3239 & Pg35; - assign n9470 = n7306 & Ng3235 & Pg35; - assign n9471 = n7311 & Ng3227 & Pg35; - assign n9472 = ~Pg35 & Ng1454; - assign n9473 = ~Pg35 & Ng1111; - assign n9474 = n7936 & \[4434] & Pg35; - assign n1457 = ~n6802; - assign n5056_1 = ~n6812; - assign n6335 = ~n6822; - assign n4736_1 = ~n8002; - assign n6137 = ~n6709; - assign n1517 = ~n6752; - assign n4020 = ~n6762; - assign n1993_1 = ~n6772; - assign n4412_1 = ~n6782; - assign n5893_1 = ~n6792; - assign n4422 = ~n7947; - assign n4432_1 = ~n7959; - assign n6359 = ~n6705; - assign n6570 = ~n7163; - assign Pg34956 = n4124_1; - assign Pg34839 = n4124_1; - assign Pg34788 = n4133; - assign Pg34437 = n4135; - assign Pg34436 = n4136; - assign Pg33959 = n4151_1; - assign Pg33894 = n4133; - assign Pg33533 = n4162; - assign Pg31861 = \[4415] ; - assign Pg31665 = n4135; - assign Pg31656 = n4136; - assign Pg30332 = \[4421] ; - assign Pg29221 = \[4426] ; - assign Pg29220 = \[4427] ; - assign Pg29219 = \[4428] ; - assign Pg29218 = \[4507] ; - assign Pg29217 = \[4430] ; - assign Pg29216 = \[4431] ; - assign Pg29215 = \[4432] ; - assign Pg29214 = \[4433] ; - assign Pg29213 = \[4434] ; - assign Pg29212 = \[4435] ; - assign Pg29211 = \[4436] ; - assign Pg29210 = \[4437] ; - assign Pg28753 = n4151_1; - assign Pg27831 = n4162; - assign Pg25219 = \[4415] ; - assign Pg24185 = Pg44; - assign Pg24184 = Pg135; - assign Pg24183 = Pg134; - assign Pg24182 = Pg127; - assign Pg24181 = Pg126; - assign Pg24180 = Pg125; - assign Pg24179 = Pg124; - assign Pg24178 = Pg120; - assign Pg24177 = Pg116; - assign Pg24176 = Pg115; - assign Pg24175 = Pg114; - assign Pg24174 = Pg113; - assign Pg24173 = Pg100; - assign Pg24172 = Pg99; - assign Pg24171 = Pg92; - assign Pg24170 = Pg91; - assign Pg24169 = Pg90; - assign Pg24168 = Pg84; - assign Pg24167 = Pg73; - assign Pg24166 = Pg72; - assign Pg24165 = Pg64; - assign Pg24164 = Pg57; - assign Pg24163 = Pg56; - assign Pg24162 = Pg54; - assign Pg24161 = Pg53; - assign Pg23683 = \[4421] ; - assign Pg21698 = Pg36; - assign Pg21292 = \[4426] ; - assign Pg21270 = \[4430] ; - assign Pg21245 = \[4427] ; - assign Pg21176 = \[4431] ; - assign Pg20901 = \[4432] ; - assign Pg20899 = \[4435] ; - assign Pg20763 = \[4436] ; - assign Pg20654 = \[4428] ; - assign Pg20652 = \[4433] ; - assign Pg20557 = \[4434] ; - assign Pg20049 = \[4437] ; - assign Pg18881 = \[4507] ; - assign Pg18101 = Pg6746; - assign Pg18100 = Pg6751; - assign Pg18099 = Pg6745; - assign Pg18098 = Pg6744; - assign Pg18097 = Pg6747; - assign Pg18096 = Pg6750; - assign Pg18095 = Pg6749; - assign Pg18094 = Pg6748; - assign Pg18092 = Pg6753; - assign Pg8403 = \[4651] ; - assign Pg8353 = \[4651] ; - assign Pg8283 = \[4658] ; - assign Pg8235 = \[4658] ; - assign Pg8178 = \[4661] ; - assign Pg8132 = \[4661] ; - assign n716 = Pg9048; - assign n780_1 = Pg17715; - assign n823_1 = Pg8920; - assign n837_1 = Pg16656; - assign n851_1 = Ng4571; - assign n914_1 = Pg17743; - assign n1022_1 = Pg16874; - assign n1045_1 = Pg16627; - assign n1136_1 = Pg17580; - assign n1174 = Pg12368; - assign n1177 = Pg17739; - assign n1205_1 = Pg14694; - assign n1228_1 = Pg17649; - assign n1331_1 = Pg17320; - assign n1358_1 = Pg14217; - assign n1411_1 = Pg17722; - assign n1423 = Pg8215; - assign n1442 = Pg10527; - assign n1481 = Pg16775; - assign n1495_1 = Ng26960; - assign n1513 = Pg12422; - assign n1650 = Pg16744; - assign n1717_1 = Pg9617; - assign n1816_1 = Pg11678; - assign n1840 = Pg17711; - assign n1912_1 = Pg14673; - assign n1920_1 = Pg17639; - assign n1959 = Pg16722; - assign n1983_1 = Pg17400; - assign n2002_1 = Pg8344; - assign n2031 = Pg13966; - assign n2074 = Pg17760; - assign n2096_1 = Pg8839; - assign n2120_1 = Pg10122; - assign n2124 = Pg12350; - assign n2127_1 = Pg19357; - assign n2150 = Pg7946; - assign n2261_1 = Pg14597; - assign n2289_1 = Pg14518; - assign n2297_1 = Pg16924; - assign n2309_1 = Pg17423; - assign n2313 = Pg7245; - assign n2331_1 = Pg9682; - assign n2345_1 = Pg14125; - assign n2432 = Pg11418; - assign n2445 = Pg14096; - assign n2458 = Pg8475; - assign n2502 = Pg8870; - assign n2619_1 = Ng26936; - assign n2663 = Pg9497; - assign n2701_1 = Pg11388; - assign n2729_1 = Pg14779; - assign n2752_1 = Pg11447; - assign n2755_1 = Pg12923; - assign n2774_1 = Pg8915; - assign n2876_1 = Pg9251; - assign n2885_1 = Pg8416; - assign n2934_1 = Ng6974; - assign n2937_1 = Pg11349; - assign n2941_1 = Ng26959; - assign n2975_1 = Pg17787; - assign n3061 = Pg14189; - assign n3079 = Pg8784; - assign n3082 = Pg17519; - assign n3219_1 = Pg19334; - assign n3232_1 = Pg9743; - assign n3270 = Pg7257; - assign n3279_1 = Ng10384; - assign n3282_1 = Pg17577; - assign n3379 = Pg16693; - assign n3382_1 = Pg17291; - assign n3435_1 = Pg12238; - assign n3468_1 = Pg16955; - assign n3471 = Pg10306; - assign n3480_1 = Pg17678; - assign n3561 = Pg7260; - assign n3595 = Pg13049; - assign n3608_1 = Pg13259; - assign n3627 = Pg8788; - assign n3779 = Pg17607; - assign n3900_1 = Pg14147; - assign n3903_1 = Pg13039; - assign n3971_1 = Pg14749; - assign n3984_1 = Pg14635; - assign n3992 = Pg16659; - assign n4010_1 = Pg10500; - assign n4039_1 = Pg14738; - assign n4042 = Pg8719; - assign n4066 = Pg12470; - assign n4084 = Pg8279; - assign n4151 = Pg12919; - assign n4178_1 = Pg17871; - assign n4206 = Pg8358; - assign n4235_1 = Pg13068; - assign n4263_1 = Pg14421; - assign n4340_1 = Pg14451; - assign n4393_1 = Pg8917; - assign n4456 = Pg14705; - assign n4489 = Pg17845; - assign n4492_1 = Pg17674; - assign n4495 = Pg8783; - assign n4578 = Pg14662; - assign n4640_1 = Pg13926; - assign n4648 = Pg8918; - assign n4731_1 = \[4507] ; - assign n4770_1 = Pg13085; - assign n4773_1 = Pg13099; - assign n4846_1 = Pg13272; - assign n4851_1 = Ng6972; - assign n4855_1 = Pg8916; - assign n4868_1 = Pg16748; - assign n4877 = \[4661] ; - assign n4890 = Pg7243; - assign n4894_1 = Pg14167; - assign n4948_1 = Pg7540; - assign n4987 = Pg17764; - assign n5060 = Pg13895; - assign n5083_1 = Pg9019; - assign n5107 = Pg8787; - assign n5160_1 = Pg8291; - assign n5237_1 = Pg12184; - assign n5265_1 = Pg17646; - assign n5269_1 = Ng25; - assign n5322 = Pg17819; - assign n5335_1 = Pg14201; - assign n5353_1 = Pg17404; - assign n5356_1 = Pg33435; - assign n5385_1 = \[4658] ; - assign n5389_1 = Pg17685; - assign n5402_1 = Pg17316; - assign n5521_1 = Ng26885; - assign n5545_1 = Pg16624; - assign n5662 = Pg17688; - assign n5690 = \[4651] ; - assign n5714 = Pg14828; - assign n5776 = Ng4520; - assign n5825_1 = Pg13906; - assign n5828_1 = Pg33079; - assign n5842_1 = Pg8785; - assign n5859 = Pg9553; - assign n5937 = Pg17778; - assign n5994_1 = Pg17813; - assign n6100_1 = Pg11770; - assign n6123_1 = Pg16718; - assign n6156 = Pg13881; - assign n6169 = Pg16686; - assign n6192 = Pg7916; - assign n6293 = Pg12300; - assign n6306_1 = Pg8919; - assign n6373 = Pg17604; - assign n6376 = Pg16603; - assign n6399 = Pg13865; - assign n6526 = Pg8789; - assign n6555 = Pg9555; - assign n6642 = Pg8786; - always @ (posedge clock) begin - Ng5057 <= n687; - Ng2771 <= n692_1; - Ng1882 <= n697_1; - Ng2299 <= n702_1; - Ng4040 <= n707_1; - Ng2547 <= n712; - Ng559 <= n716; - Ng3243 <= n721_1; - Ng452 <= n726_1; - Ng3542 <= n731_1; - Ng5232 <= n736_1; - Ng5813 <= n741_1; - Ng2907 <= n746_1; - Ng1744 <= n751_1; - Ng5909 <= n756_1; - Ng1802 <= n761_1; - Ng3554 <= n766_1; - Ng6219 <= n771_1; - Ng807 <= n776_1; - Ng6031 <= n780_1; - Ng847 <= n785_1; - Ng976 <= n790_1; - Ng4172 <= n795_1; - Ng4372 <= n800_1; - Ng3512 <= n805_1; - Ng749 <= n810_1; - Ng3490 <= n815_1; - Pg12350 <= n820_1; - Ng4235 <= n823_1; - Ng1600 <= n828_1; - Ng1714 <= n833_1; - Pg14451 <= n837_1; - Ng3155 <= n841_1; - Ng2236 <= n846_1; - Ng4555 <= n851_1; - Ng3698 <= n856_1; - Ng1736 <= n861_1; - Ng1968 <= n866_1; - Ng4621 <= n871_1; - Ng5607 <= n876_1; - Ng2657 <= n881_1; - Pg12300 <= n886_1; - Ng490 <= n890_1; - Ng311 <= n895_1; - Ng772 <= n900_1; - Ng5587 <= n905_1; - Ng6177 <= n910_1; - Ng6377 <= n914_1; - Ng3167 <= n919_1; - Ng5615 <= n924_1; - Ng4567 <= n929; - Ng3457 <= n934_1; - Ng6287 <= n939_1; - Pg7946 <= n944_1; - Ng2563 <= n948_1; - Ng4776 <= n953_1; - Ng4593 <= n958_1; - Ng6199 <= n963_1; - Ng2295 <= n968_1; - Ng1384 <= n973_1; - Ng1339 <= n978_1; - Ng5180 <= n983_1; - Ng2844 <= n988_1; - Ng1024 <= n993_1; - Ng5591 <= n998_1; - Ng3598 <= n1003_1; - Ng4264 <= n1008_1; - Ng767 <= n1013_1; - Ng5853 <= n1018_1; - Pg13865 <= n1022_1; - Ng2089 <= n1026_1; - Ng4933 <= n1031_1; - Ng4521 <= n1036_1; - Ng5507 <= n1041_1; - Pg16656 <= n1045_1; - Ng6291 <= n1049_1; - Ng294 <= n1054_1; - Ng5559 <= n1059_1; - Pg9617 <= n1064_1; - Pg9741 <= n1068_1; - Ng3813 <= n1072_1; - Ng562 <= n1077_1; - Ng608 <= n1082; - Ng1205 <= n1087_1; - Ng3909 <= n1092_1; - Ng6259 <= n1097_1; - Ng5905 <= n1102; - Ng921 <= n1107_1; - Ng2955 <= n1112_1; - Ng203 <= n1117; - Ng1099 <= n1122_1; - Ng4878 <= n1127; - Ng5204 <= n1132_1; - Pg17604 <= n1136_1; - Ng3606 <= n1140_1; - Ng1926 <= n1145_1; - Ng6215 <= n1150_1; - Ng3586 <= n1155_1; - Ng291 <= n1160_1; - Ng4674 <= n1165_1; - Ng3570 <= n1170_1; - Pg9048 <= n1174; - Pg17607 <= n1177; - Ng1862 <= n1181; - Ng676 <= n1186; - Ng843 <= n1191_1; - Ng4332 <= n1196_1; - Ng4153 <= n1201_1; - Pg17711 <= n1205_1; - Ng6336 <= n1209_1; - Ng622 <= n1214; - Ng3506 <= n1219_1; - Ng4558 <= n1224_1; - Pg17685 <= n1228_1; - Ng3111 <= n1232_1; - \[4430] <= n1237_1; - Ng26936 <= n1242_1; - Ng939 <= n1247; - Ng278 <= n1252; - Ng4492 <= n1257_1; - Ng4864 <= n1262; - Ng1036 <= n1267_1; - \[4427] <= n1272_1; - Ng1178 <= n1277_1; - Ng3239 <= n1282_1; - Ng718 <= n1287_1; - Ng6195 <= n1292_1; - Ng1135 <= n1297_1; - Ng6395 <= n1302; - \[4415] <= n1307_1; - Ng554 <= n1312_1; - Ng496 <= n1317_1; - Ng3853 <= n1322_1; - Ng5134 <= n1327_1; - Pg17404 <= n1331_1; - Pg8344 <= n1335_1; - Ng2485 <= n1339_1; - Ng925 <= n1344; - Ng48 <= n1349_1; - Ng5555 <= n1354_1; - Pg14096 <= n1358_1; - Ng1798 <= n1362_1; - Ng4076 <= n1367; - Ng2941 <= n1372_1; - Ng3905 <= n1377_1; - Ng763 <= n1382_1; - Ng6255 <= n1387_1; - Ng4375 <= n1392_1; - Ng4871 <= n1397_1; - Ng4722 <= n1402_1; - Ng590 <= n1407_1; - Pg13099 <= n1411_1; - Ng1632 <= n1415_1; - Pg12238 <= n1420; - Ng3100 <= n1423; - Ng1495 <= n1428_1; - Ng1437 <= n1433_1; - Ng6154 <= n1438_1; - Ng1579 <= n1442; - Ng5567 <= n1447; - Ng1752 <= n1452_1; - Ng1917 <= n1457; - Ng744 <= n1462_1; - Ng4737 <= n1467; - \[4661] <= n1472_1; - Ng6267 <= n1477; - Pg16659 <= n1481; - Ng1442 <= n1485_1; - Ng5965 <= n1490; - Ng4477 <= n1495_1; - Pg10500 <= n1500; - Ng4643 <= n1504; - Ng5264 <= n1509; - Pg14779 <= n1513; - Ng2610 <= n1517; - Ng5160 <= n1522_1; - Ng5933 <= n1527; - Ng1454 <= n1532_1; - Ng753 <= n1537_1; - Ng1296 <= n1542_1; - Ng3151 <= n1547_1; - Ng2980 <= n1552_1; - Ng6727 <= n1557_1; - Ng3530 <= n1562_1; - Ng4104 <= n1567; - Ng1532 <= n1572_1; - Pg9251 <= n1577_1; - Ng2177 <= n1581; - Ng52 <= n1586; - Ng4754 <= n1591_1; - Ng1189 <= n1596_1; - Ng2287 <= n1601_1; - Ng4273 <= n1606_1; - Ng1389 <= n1611_1; - Ng1706 <= n1616; - Ng5835 <= n1621_1; - Ng1171 <= n1626_1; - Ng4269 <= n1631_1; - Ng2399 <= n1636_1; - Ng4983 <= n1641_1; - Ng5611 <= n1646_1; - Pg16627 <= n1650; - Ng4572 <= n1654; - Ng3143 <= n1659; - Ng2898 <= n1664_1; - Ng3343 <= n1669_1; - Ng3235 <= n1674; - Ng4543 <= n1679_1; - Ng3566 <= n1684_1; - Ng4534 <= n1689_1; - Ng4961 <= n1694_1; - Ng4927 <= n1699_1; - Ng2259 <= n1704_1; - Ng2819 <= n1709_1; - Pg7257 <= n1714; - Ng5802 <= n1717_1; - Ng2852 <= n1722_1; - Ng417 <= n1727_1; - Ng681 <= n1732_1; - Ng437 <= n1737_1; - Ng351 <= n1742_1; - Ng5901 <= n1747_1; - Ng2886 <= n1752; - Ng3494 <= n1757_1; - Ng5511 <= n1762_1; - Ng3518 <= n1767_1; - Ng1604 <= n1772; - Ng5092 <= n1777; - Ng4831 <= n1782_1; - Ng4382 <= n1787_1; - Ng6386 <= n1792; - Ng479 <= n1797; - Ng3965 <= n1802; - Ng4749 <= n1807_1; - Ng2008 <= n1812_1; - Ng736 <= n1816_1; - Ng3933 <= n1821_1; - Ng222 <= n1826_1; - Ng3050 <= n1831_1; - Ng1052 <= n1836_1; - Pg17580 <= n1840; - Ng2122 <= n1844_1; - Ng2465 <= n1849_1; - Ng5889 <= n1854; - Ng4495 <= n1859_1; - Pg8719 <= n1864_1; - Ng4653 <= n1868; - Ng3179 <= n1873_1; - Ng1728 <= n1878_1; - Ng2433 <= n1883_1; - Ng3835 <= n1888_1; - Ng6187 <= n1893_1; - Ng4917 <= n1898_1; - Ng1070 <= n1903_1; - Ng822 <= n1908_1; - Pg17715 <= n1912_1; - Ng914 <= n1916_1; - Ng5339 <= n1920_1; - Ng4164 <= n1925_1; - Ng969 <= n1930_1; - Ng2807 <= n1935_1; - Ng4054 <= n1940_1; - Ng6191 <= n1945_1; - Ng5077 <= n1950_1; - Ng5523 <= n1955; - Ng3680 <= n1959; - Ng6637 <= n1964; - Ng174 <= n1969_1; - Ng1682 <= n1974_1; - Ng355 <= n1979_1; - Ng1087 <= n1983_1; - Ng1105 <= n1988; - Ng2342 <= n1993_1; - Ng6307 <= n1998_1; - Ng3802 <= n2002_1; - Ng6159 <= n2007_1; - Ng2255 <= n2012_1; - Ng2815 <= n2017_1; - Ng911 <= n2022_1; - Ng43 <= n2027_1; - Pg16775 <= n2031; - Ng1748 <= n2035; - Ng5551 <= n2040; - Ng3558 <= n2045; - Ng5499 <= n2050; - Ng2960 <= n2055_1; - Ng3901 <= n2060; - Ng4888 <= n2065_1; - Ng6251 <= n2070; - Pg17649 <= n2074; - Ng1373 <= n2078_1; - Pg8215 <= n2083; - Ng157 <= n2087; - Ng2783 <= n2092; - Ng4281 <= n2096_1; - Ng3574 <= n2101_1; - Ng2112 <= n2106_1; - Ng1283 <= n2111; - Ng433 <= n2116; - Ng4297 <= n2120_1; - Pg14738 <= n2124; - Pg13272 <= n2127_1; - Ng758 <= n2131_1; - Ng4639 <= n2136; - Ng6537 <= n2141_1; - Ng5543 <= n2146; - Pg8475 <= n2150; - Ng5961 <= n2154; - Ng6243 <= n2159_1; - Ng632 <= n2164_1; - Pg12919 <= n2169_1; - Ng3889 <= n2173_1; - Ng3476 <= n2178; - Ng1664 <= n2183_1; - Ng1246 <= n2188_1; - Ng6629 <= n2193; - Ng246 <= n2198; - Ng4049 <= n2203_1; - Pg7260 <= n2208_1; - Ng2932 <= n2212; - Ng4575 <= n2217_1; - Ng4098 <= n2222; - Ng4498 <= n2227; - Ng528 <= n2232_1; - Ng16 <= n2237_1; - Ng3139 <= n2242_1; - \[4432] <= n2247; - Ng4584 <= n2252; - Ng142 <= n2257; - Pg17639 <= n2261_1; - Ng5831 <= n2265; - Ng239 <= n2270_1; - Ng1216 <= n2275; - Ng2848 <= n2280_1; - Ng5022 <= n2285_1; - Pg16955 <= n2289_1; - Ng1030 <= n2293_1; - Pg13881 <= n2297_1; - Ng3231 <= n2301_1; - Pg9817 <= n2306; - Ng1430 <= n2309_1; - Ng4452 <= n2313; - Ng2241 <= n2318_1; - Ng1564 <= n2323_1; - Pg9680 <= n2328_1; - Ng6148 <= n2331_1; - Ng6649 <= n2336_1; - Ng110 <= n2341_1; - Pg14147 <= n2345_1; - Ng225 <= n2349_1; - Ng4486 <= n2354_1; - Ng4504 <= n2359_1; - Ng5873 <= n2364_1; - Ng5037 <= n2369_1; - Ng2319 <= n2374_1; - Ng5495 <= n2379_1; - Pg11770 <= n2384_1; - Ng5208 <= n2388_1; - Ng5579 <= n2393_1; - Ng5869 <= n2398_1; - Ng1589 <= n2403_1; - Ng5752 <= n2408_1; - Ng6279 <= n2413; - Ng5917 <= n2418; - Ng2975 <= n2423; - Ng6167 <= n2428_1; - Pg13966 <= n2432; - Ng2599 <= n2436_1; - Ng1448 <= n2441_1; - Pg14125 <= n2445; - Ng2370 <= n2449_1; - Ng5164 <= n2454_1; - Ng1333 <= n2458; - Ng153 <= n2463_1; - Ng6549 <= n2468_1; - Ng4087 <= n2473_1; - Ng4801 <= n2478_1; - Ng2984 <= n2483; - Ng3961 <= n2488_1; - Ng962 <= n2493; - Ng101 <= n2498_1; - Pg8918 <= n2502; - Ng6625 <= n2506; - Ng51 <= n2511_1; - Ng1018 <= n2516; - Pg17320 <= n2521_1; - Ng4045 <= n2525; - Ng1467 <= n2530; - Ng2461 <= n2535_1; - Ng2756 <= n2540; - Ng5990 <= n2545_1; - Ng1256 <= n2550_1; - Ng5029 <= n2555_1; - Ng6519 <= n2560_1; - Ng1816 <= n2565_1; - Ng4369 <= n2570; - Ng4578 <= n2575; - Ng4459 <= n2580_1; - Ng3831 <= n2585_1; - Ng2514 <= n2590_1; - Ng3288 <= n2595_1; - Ng2403 <= n2600_1; - Ng2145 <= n2605_1; - Ng1700 <= n2610_1; - Ng513 <= n2615_1; - Ng2841 <= n2619_1; - Ng5297 <= n2624_1; - Ng2763 <= n2629_1; - Ng4793 <= n2634_1; - Ng952 <= n2639_1; - Ng1263 <= n2644_1; - Ng1950 <= n2649_1; - Ng5138 <= n2654; - Ng2307 <= n2659_1; - Ng5109 <= n2663; - Pg8398 <= n2668_1; - Ng4664 <= n2672_1; - Ng2223 <= n2677_1; - Ng5808 <= n2682_1; - Ng6645 <= n2687_1; - Ng2016 <= n2692_1; - Ng3873 <= n2697; - Pg13926 <= n2701_1; - Ng2315 <= n2705_1; - Ng2811 <= n2710_1; - Ng5957 <= n2715_1; - Ng2047 <= n2720_1; - Ng3869 <= n2725_1; - Pg17760 <= n2729_1; - Ng5575 <= n2733_1; - Ng46 <= n2738_1; - Ng3752 <= n2743; - Ng3917 <= n2748_1; - Pg8783 <= n2752_1; - Ng1585 <= n2755_1; - Ng4388 <= n2760_1; - Ng6275 <= n2765_1; - Ng6311 <= n2770; - Pg8916 <= n2774_1; - Ng1041 <= n2778_1; - Ng2595 <= n2783_1; - Ng2537 <= n2788_1; - \[4426] <= n2793_1; - Ng4430 <= n2798_1; - Ng4564 <= n2803_1; - Ng4826 <= n2808_1; - Ng6239 <= n2813_1; - Ng232 <= n2818_1; - Ng5268 <= n2823_1; - Ng6545 <= n2828; - Ng2417 <= n2833_1; - Ng1772 <= n2838_1; - Ng5052 <= n2843_1; - Pg9615 <= n2848_1; - Ng1890 <= n2852_1; - Ng2629 <= n2857_1; - Ng572 <= n2862_1; - Ng2130 <= n2867_1; - Ng4108 <= n2872_1; - Ng4308 <= n2876_1; - Ng475 <= n2881_1; - Ng990 <= n2885_1; - Ng45 <= n2890_1; - Pg12184 <= n2895_1; - Ng3990 <= n2899_1; - Ng5881 <= n2904_1; - Ng1992 <= n2909_1; - Ng3171 <= n2914_1; - Ng812 <= n2919_1; - Ng832 <= n2924_1; - Ng5897 <= n2929_1; - Ng4571 <= n2934_1; - Pg13895 <= n2937_1; - Ng4455 <= n2941_1; - Ng2902 <= n2946_1; - Ng333 <= n2951_1; - Ng168 <= n2956_1; - Ng2823 <= n2961_1; - Ng3684 <= n2966_1; - Ng3639 <= n2971_1; - Pg14597 <= n2975_1; - Ng3338 <= n2979_1; - Ng5406 <= n2984_1; - Ng269 <= n2989_1; - Ng401 <= n2994_1; - Ng6040 <= n2999_1; - Ng441 <= n3004_1; - Pg9553 <= n3009_1; - Ng3808 <= n3013_1; - Ng10384 <= n3018_1; - Ng3957 <= n3023_1; - Ng4093 <= n3028_1; - Ng1760 <= n3033_1; - Pg12422 <= n3038_1; - Ng160 <= n3042_1; - Ng2279 <= n3047; - Ng3498 <= n3052; - Ng586 <= n3057; - Pg14201 <= n3061; - Ng2619 <= n3065_1; - Ng1183 <= n3070; - Ng1608 <= n3075; - Pg8785 <= n3079; - Pg17577 <= n3082; - Ng1779 <= n3086_1; - Ng2652 <= n3091; - Ng2193 <= n3096_1; - Ng2393 <= n3101_1; - Ng661 <= n3106; - Ng4950 <= n3111; - Ng5535 <= n3116_1; - Ng2834 <= n3121; - Ng1361 <= n3126; - Ng6235 <= n3131_1; - Ng1146 <= n3136; - Ng2625 <= n3141_1; - Ng150 <= n3146; - Ng1696 <= n3151_1; - Ng6555 <= n3156_1; - Pg14189 <= n3161; - Ng3881 <= n3165; - Ng6621 <= n3170_1; - Ng3470 <= n3175_1; - Ng3897 <= n3180_1; - Ng518 <= n3185_1; - Ng538 <= n3190; - Ng2606 <= n3195; - Ng1472 <= n3200; - Ng542 <= n3205; - Ng5188 <= n3210_1; - Ng5689 <= n3215; - Pg13259 <= n3219_1; - Ng405 <= n3223_1; - Ng5216 <= n3228; - Ng6494 <= n3232_1; - Ng4669 <= n3237; - Ng996 <= n3242_1; - Ng4531 <= n3247_1; - Ng2860 <= n3252; - Ng4743 <= n3257_1; - Ng6593 <= n3262_1; - Pg8291 <= n3267; - Ng4411 <= n3270; - Ng1413 <= n3275_1; - Ng26960 <= n3279_1; - Pg13039 <= n3282_1; - Ng6641 <= n3286_1; - Ng1936 <= n3291_1; - Ng55 <= n3296_1; - Ng504 <= n3301; - Ng2587 <= n3306_1; - Ng4480 <= n3311; - Ng2311 <= n3316_1; - Ng3602 <= n3321; - Ng5571 <= n3326_1; - Ng3578 <= n3331_1; - Pg9555 <= n3336; - Ng5827 <= n3340_1; - Ng3582 <= n3345; - Ng6271 <= n3350_1; - Ng4688 <= n3355_1; - Ng2380 <= n3360; - Ng5196 <= n3365_1; - Ng3227 <= n3370_1; - Ng2020 <= n3375; - Pg14518 <= n3379; - Pg17316 <= n3382_1; - Ng6541 <= n3386_1; - Ng3203 <= n3391_1; - Ng1668 <= n3396_1; - Ng4760 <= n3401_1; - Ng262 <= n3406_1; - Ng1840 <= n3411; - Ng5467 <= n3416; - Ng460 <= n3421_1; - Ng6209 <= n3426_1; - \[4436] <= n3431_1; - Pg14662 <= n3435_1; - Ng655 <= n3439; - Ng3502 <= n3444_1; - Ng2204 <= n3449; - Ng5256 <= n3454; - Ng4608 <= n3459_1; - Ng794 <= n3464_1; - Pg13906 <= n3468_1; - Ng4423 <= n3471; - Ng3689 <= n3476_1; - Ng5685 <= n3480_1; - Ng703 <= n3485_1; - Ng862 <= n3490; - Ng3247 <= n3495_1; - Ng2040 <= n3500_1; - Ng4146 <= n3505; - Ng4633 <= n3510_1; - Pg7916 <= n3515; - Ng4732 <= n3519_1; - Pg9497 <= n3524; - Ng5817 <= n3528_1; - Ng2351 <= n3533; - Ng2648 <= n3538; - Ng6736 <= n3543; - Ng4944 <= n3548; - Ng4072 <= n3553; - Pg7540 <= n3558; - Ng4443 <= n3561; - Ng3466 <= n3566_1; - Ng4116 <= n3571_1; - Ng5041 <= n3576; - Ng4434 <= n3581_1; - Ng3827 <= n3586_1; - Ng6500 <= n3591_1; - Pg17813 <= n3595; - Ng3133 <= n3599; - Ng3333 <= n3604; - Ng979 <= n3608_1; - Ng4681 <= n3613_1; - Ng298 <= n3618_1; - Ng2667 <= n3623; - Pg8789 <= n3627; - Ng1894 <= n3631; - Ng2988 <= n3636_1; - Ng3538 <= n3641; - Ng301 <= n3646_1; - Ng341 <= n3651_1; - Ng827 <= n3656_1; - Pg17291 <= n3661; - Ng2555 <= n3665_1; - Ng5011 <= n3670_1; - Ng199 <= n3675; - Ng6523 <= n3680_1; - Ng1526 <= n3685_1; - Ng4601 <= n3690_1; - Ng854 <= n3695; - Ng1484 <= n3700; - Ng4922 <= n3705; - Ng5080 <= n3710_1; - Ng5863 <= n3715_1; - Ng4581 <= n3720_1; - Ng2518 <= n3725; - Ng2567 <= n3730; - Ng568 <= n3735; - Ng3263 <= n3740; - Ng6613 <= n3745; - Ng6044 <= n3750_1; - Ng6444 <= n3755_1; - Ng2965 <= n3760; - Ng5857 <= n3765_1; - Ng1616 <= n3770_1; - Ng890 <= n3775; - Pg17646 <= n3779; - Ng3562 <= n3783_1; - Pg10122 <= n3788_1; - Ng1404 <= n3792; - Ng3817 <= n3797_1; - Ng93 <= n3802_1; - Ng4501 <= n3807_1; - Ng287 <= n3812_1; - Ng2724 <= n3817_1; - Ng4704 <= n3822_1; - Ng22 <= n3827_1; - Ng2878 <= n3832_1; - Ng5220 <= n3837_1; - Ng617 <= n3842_1; - Pg12368 <= n3847_1; - Ng316 <= n3851_1; - Ng1277 <= n3856; - Ng6513 <= n3861_1; - Ng336 <= n3866_1; - Ng2882 <= n3871_1; - Ng933 <= n3876_1; - Ng1906 <= n3881_1; - Ng305 <= n3886; - Ng8 <= n3891_1; - Ng2799 <= n3896; - Pg14167 <= n3900_1; - Pg17787 <= n3903_1; - Ng4912 <= n3907_1; - Ng4157 <= n3912; - Ng2541 <= n3917; - Ng2153 <= n3922; - Ng550 <= n3927; - Ng255 <= n3932; - Ng1945 <= n3937_1; - Ng5240 <= n3942_1; - Ng1478 <= n3947; - Ng3863 <= n3952_1; - Ng1959 <= n3957_1; - Ng3480 <= n3962; - Ng6653 <= n3967_1; - Pg17764 <= n3971_1; - Ng2864 <= n3975; - Ng4894 <= n3980_1; - Pg17678 <= n3984_1; - Ng3857 <= n3988; - Pg16693 <= n3992; - Ng499 <= n3996_1; - Ng1002 <= n4001; - Ng776 <= n4006; - Ng1236 <= n4010_1; - Ng4646 <= n4015; - Ng2476 <= n4020; - Ng1657 <= n4025_1; - Ng2375 <= n4030; - Ng63 <= n4035_1; - Pg17739 <= n4039_1; - Ng358 <= n4042; - Ng896 <= n4047_1; - Ng283 <= n4052_1; - Ng3161 <= n4057; - Ng2384 <= n4062; - Pg14828 <= n4066; - Ng4616 <= n4070_1; - Ng4561 <= n4075; - Ng2024 <= n4080; - Ng3451 <= n4084; - Ng2795 <= n4089_1; - Ng613 <= n4094_1; - Ng4527 <= n4099; - Ng1844 <= n4104; - Ng5937 <= n4109; - Ng4546 <= n4114_1; - Ng2523 <= n4119; - Pg11349 <= n4124; - Ng2643 <= n4128; - Ng1489 <= n4133_1; - Pg8358 <= n4138_1; - Ng2551 <= n4142_1; - Ng5156 <= n4147; - \[4421] <= n4151; - Pg8279 <= n4156_1; - Pg8839 <= n4160_1; - Ng1955 <= n4164; - Ng6049 <= n4169_1; - Ng2273 <= n4174; - Pg14749 <= n4178_1; - Ng4771 <= n4182_1; - Ng6098 <= n4187; - Ng3147 <= n4192_1; - Ng3347 <= n4197; - Ng2269 <= n4202_1; - Ng191 <= n4206; - Ng2712 <= n4211_1; - Ng626 <= n4216; - Ng2729 <= n4221_1; - Ng5357 <= n4226_1; - Ng4991 <= n4231_1; - Pg17819 <= n4235_1; - Ng4709 <= n4239_1; - Ng2927 <= n4244; - Ng4340 <= n4249; - Ng5929 <= n4254; - Ng4907 <= n4259_1; - Pg16874 <= n4263_1; - Ng4035 <= n4267_1; - Ng2946 <= n4272_1; - Ng918 <= n4277_1; - Ng4082 <= n4282; - Pg9743 <= n4287_1; - Ng2036 <= n4291_1; - Ng577 <= n4296_1; - Ng1620 <= n4301_1; - Ng2831 <= n4306; - Ng667 <= n4311_1; - Ng930 <= n4316_1; - Ng3937 <= n4321_1; - Ng817 <= n4326_1; - Ng1249 <= n4331_1; - Ng837 <= n4336_1; - Pg16924 <= n4340_1; - Ng599 <= n4344_1; - Ng5475 <= n4349_1; - Ng739 <= n4354_1; - Ng5949 <= n4359_1; - Ng6682 <= n4364_1; - Ng904 <= n4369; - Ng2873 <= n4374_1; - Ng1854 <= n4379_1; - Ng5084 <= n4384_1; - Ng5603 <= n4389_1; - Pg8870 <= n4393_1; - Ng2495 <= n4397_1; - Ng2437 <= n4402_1; - Ng2102 <= n4407_1; - Ng2208 <= n4412_1; - Ng2579 <= n4417_1; - Ng4064 <= n4422; - Ng4899 <= n4427_1; - Ng2719 <= n4432_1; - Ng4785 <= n4437; - Ng5583 <= n4442_1; - Ng781 <= n4447; - Ng6173 <= n4452; - Pg17743 <= n4456; - Ng2917 <= n4460; - Ng686 <= n4465_1; - Ng1252 <= n4470; - Ng671 <= n4475; - Ng2265 <= n4480; - Ng6283 <= n4485; - Pg14705 <= n4489; - Pg17519 <= n4492_1; - Pg8784 <= n4495; - Ng5527 <= n4499; - Ng4489 <= n4504; - Ng1974 <= n4509_1; - Ng1270 <= n4514; - Ng4966 <= n4519; - Ng6227 <= n4524; - Ng3929 <= n4529; - Ng5503 <= n4534; - Ng4242 <= n4539; - Ng5925 <= n4544_1; - Ng1124 <= n4549; - Ng4955 <= n4554; - Ng5224 <= n4559_1; - Ng2012 <= n4564_1; - Ng6203 <= n4569_1; - Ng5120 <= n4574; - Pg17674 <= n4578; - Ng2389 <= n4582_1; - Ng4438 <= n4587_1; - Ng2429 <= n4592; - Ng2787 <= n4597_1; - Ng1287 <= n4602; - Ng2675 <= n4607; - \[4507] <= n4612; - Ng4836 <= n4617; - Ng1199 <= n4622; - Pg19357 <= n4627; - Ng5547 <= n4631; - Ng2138 <= n4636; - Pg16744 <= n4640_1; - Ng2338 <= n4644; - Pg8919 <= n4648; - Ng6247 <= n4652_1; - Ng2791 <= n4657_1; - Ng3949 <= n4662; - Ng1291 <= n4667_1; - Ng5945 <= n4672_1; - Ng5244 <= n4677_1; - Ng2759 <= n4682; - Ng6741 <= n4687; - Ng785 <= n4692_1; - Ng1259 <= n4697_1; - Ng3484 <= n4702_1; - Ng209 <= n4707_1; - Ng6609 <= n4712_1; - Ng5517 <= n4717_1; - Ng2449 <= n4722_1; - Ng2575 <= n4727_1; - Ng65 <= n4731_1; - Ng2715 <= n4736_1; - Ng936 <= n4741_1; - Ng2098 <= n4746; - Ng4462 <= n4751_1; - Ng604 <= n4756; - Ng6589 <= n4761_1; - Ng1886 <= n4766; - Pg17845 <= n4770_1; - Pg17871 <= n4773_1; - Ng429 <= n4777_1; - Ng1870 <= n4782; - Ng4249 <= n4787_1; - Ng1825 <= n4792_1; - Ng1008 <= n4797; - Ng4392 <= n4802; - Ng3546 <= n4807_1; - Ng5236 <= n4812; - Ng1768 <= n4817; - Ng4854 <= n4822; - Ng3925 <= n4827; - Ng6509 <= n4832_1; - Ng732 <= n4837_1; - Ng2504 <= n4842_1; - Ng1322 <= n4846_1; - Ng4520 <= n4851_1; - Pg8917 <= n4855_1; - Ng2185 <= n4859_1; - Ng37 <= n4864_1; - Ng4031 <= n4868_1; - Ng2070 <= n4873_1; - \[4658] <= n4877; - Ng4176 <= n4882; - Pg11418 <= n4887_1; - Ng4405 <= n4890; - Ng872 <= n4894_1; - Ng6181 <= n4899; - Ng6381 <= n4904; - Ng4765 <= n4909_1; - Ng5563 <= n4914_1; - Ng1395 <= n4919_1; - Ng1913 <= n4924_1; - Ng2331 <= n4929_1; - Ng6263 <= n4934_1; - Ng50 <= n4939; - Ng3945 <= n4944; - Ng347 <= n4948_1; - Ng4473 <= n4953_1; - Ng1266 <= n4958_1; - Ng5489 <= n4963_1; - Ng714 <= n4968_1; - Ng2748 <= n4973; - Ng5471 <= n4978; - Ng4540 <= n4983_1; - Ng6723 <= n4987; - Ng6605 <= n4992; - Ng2445 <= n4997; - Ng2173 <= n5002; - Pg9019 <= n5007; - Ng2491 <= n5011_1; - Ng4849 <= n5016; - Ng2169 <= n5021; - Ng2283 <= n5026; - Ng6585 <= n5031_1; - \[4428] <= n5036; - Ng2407 <= n5041; - Ng2868 <= n5046_1; - Ng2767 <= n5051_1; - Ng1783 <= n5056_1; - Pg16718 <= n5060; - Ng1312 <= n5064; - Ng5212 <= n5069; - Ng4245 <= n5074_1; - Ng645 <= n5079_1; - Ng4291 <= n5083_1; - \[4435] <= n5088_1; - Ng182 <= n5093_1; - Ng1129 <= n5098; - Ng2227 <= n5103; - Pg8788 <= n5107; - Ng2246 <= n5111; - Ng1830 <= n5116; - Ng3590 <= n5121; - Ng392 <= n5126; - Ng1592 <= n5131; - Ng6505 <= n5136_1; - Ng1221 <= n5141; - Ng5921 <= n5146; - \[4431] <= n5151_1; - Ng146 <= n5156; - Ng218 <= n5160_1; - Ng1932 <= n5165_1; - Ng1624 <= n5170_1; - Ng5062 <= n5175_1; - Ng5462 <= n5180_1; - Ng2689 <= n5185_1; - Ng6573 <= n5190_1; - Ng1677 <= n5195_1; - Ng2028 <= n5200_1; - Ng2671 <= n5205_1; - Pg10527 <= n5210_1; - Pg7243 <= n5214_1; - Ng1848 <= n5218_1; - \[4434] <= n5223_1; - Ng5485 <= n5228_1; - Ng2741 <= n5233_1; - Pg11678 <= n5237_1; - Ng2638 <= n5241_1; - Ng4122 <= n5246_1; - Ng4322 <= n5251; - Ng5941 <= n5256_1; - Ng2108 <= n5261; - Pg13068 <= n5265_1; - Ng25 <= n5269_1; - Ng1644 <= n5273; - Ng595 <= n5278_1; - Ng2217 <= n5283_1; - Ng1319 <= n5288_1; - Ng2066 <= n5293_1; - Ng1152 <= n5298; - Ng5252 <= n5303_1; - Ng2165 <= n5308_1; - Ng2571 <= n5313_1; - Ng5176 <= n5318; - Pg14673 <= n5322; - Ng1211 <= n5326_1; - Ng2827 <= n5331_1; - Pg14217 <= n5335_1; - Ng4859 <= n5339_1; - Ng424 <= n5344_1; - Ng1274 <= n5349; - Pg17423 <= n5353_1; - Ng85 <= n5356_1; - Ng2803 <= n5361_1; - Ng1821 <= n5366_1; - Ng2509 <= n5371_1; - Ng5073 <= n5376_1; - Ng1280 <= n5381_1; - \[4651] <= n5385_1; - Pg13085 <= n5389_1; - Ng6633 <= n5393_1; - Ng5124 <= n5398_1; - Pg17400 <= n5402_1; - Ng6303 <= n5406_1; - Ng5069 <= n5411_1; - Ng2994 <= n5416; - Ng650 <= n5421_1; - Ng1636 <= n5426_1; - Ng3921 <= n5431_1; - Ng2093 <= n5436; - Ng6732 <= n5441_1; - Ng1306 <= n5446_1; - Ng1061 <= n5451_1; - Ng3462 <= n5456_1; - Ng2181 <= n5461; - Ng956 <= n5466_1; - Ng1756 <= n5471_1; - Ng5849 <= n5476_1; - Ng4112 <= n5481_1; - Ng2685 <= n5486_1; - Ng2197 <= n5491_1; - Ng2421 <= n5496_1; - Ng1046 <= n5501_1; - Ng482 <= n5506_1; - Ng4401 <= n5511_1; - Ng1514 <= n5516_1; - Ng329 <= n5521_1; - Ng6565 <= n5526_1; - Ng2950 <= n5531_1; - Ng1345 <= n5536_1; - Ng6533 <= n5541_1; - Pg14421 <= n5545_1; - Ng4727 <= n5549_1; - Pg12470 <= n5554_1; - Ng1536 <= n5558_1; - Ng3941 <= n5563_1; - Ng370 <= n5568_1; - Ng5694 <= n5573_1; - Ng1858 <= n5578_1; - Ng446 <= n5583_1; - Ng3219 <= n5588_1; - Ng1811 <= n5593_1; - Ng6601 <= n5598; - Ng2441 <= n5603_1; - Ng1874 <= n5608_1; - Ng4349 <= n5613_1; - Ng6581 <= n5618_1; - Ng6597 <= n5623_1; - Ng3610 <= n5628; - Ng2890 <= n5633; - Ng1978 <= n5638; - Ng1612 <= n5643_1; - Ng112 <= n5648_1; - Ng2856 <= n5653; - Ng1982 <= n5658_1; - Pg17722 <= n5662; - Ng5228 <= n5666_1; - Ng4119 <= n5671; - Ng6390 <= n5676_1; - Ng1542 <= n5681_1; - Ng4258 <= n5686; - Ng4818 <= n5690; - Ng5033 <= n5695; - Ng4717 <= n5700_1; - Ng1554 <= n5705_1; - Ng3849 <= n5710_1; - Pg17778 <= n5714; - Ng3199 <= n5718; - Ng5845 <= n5723_1; - Ng4975 <= n5728; - Ng790 <= n5733_1; - Ng5913 <= n5738_1; - Ng1902 <= n5743_1; - Ng6163 <= n5748; - Ng4125 <= n5753; - Ng4821 <= n5758_1; - Ng4939 <= n5763; - Pg19334 <= n5768; - Ng3207 <= n5772; - Ng4483 <= n5776; - Ng3259 <= n5781_1; - Ng5142 <= n5786; - Ng5248 <= n5791; - Ng2126 <= n5796; - Ng3694 <= n5801; - Ng5481 <= n5806; - Ng1964 <= n5811; - Ng5097 <= n5816_1; - Ng3215 <= n5821_1; - Pg16748 <= n5825_1; - Ng111 <= n5828_1; - Ng4427 <= n5833_1; - Ng2779 <= n5838_1; - Pg8786 <= n5842_1; - Pg7245 <= n5846; - Ng1720 <= n5850_1; - Ng1367 <= n5855_1; - Ng5112 <= n5859; - Ng4145 <= n5864; - Ng2161 <= n5869; - Ng376 <= n5874; - Ng2361 <= n5879_1; - Pg11447 <= n5884; - Ng582 <= n5888_1; - Ng2051 <= n5893_1; - Ng1193 <= n5898; - Ng2327 <= n5903_1; - Ng907 <= n5908_1; - Ng947 <= n5913_1; - Ng1834 <= n5918_1; - Ng3594 <= n5923_1; - Ng2999 <= n5928_1; - Ng2303 <= n5933_1; - Pg17688 <= n5937; - Ng699 <= n5941_1; - Ng723 <= n5946_1; - Ng5703 <= n5951_1; - Ng546 <= n5956; - Ng2472 <= n5961_1; - Ng5953 <= n5966_1; - Pg8277 <= n5971_1; - Ng1740 <= n5975_1; - Ng3550 <= n5980_1; - Ng3845 <= n5985_1; - Ng2116 <= n5990; - Pg14635 <= n5994_1; - Ng3195 <= n5998; - Ng3913 <= n6003_1; - Pg10306 <= n6008; - Ng1687 <= n6012; - Ng2681 <= n6017; - Ng2533 <= n6022_1; - Ng324 <= n6027; - Ng2697 <= n6032_1; - Ng4417 <= n6037_1; - Ng6561 <= n6042; - Ng1141 <= n6047_1; - Pg12923 <= n6052_1; - Ng2413 <= n6056; - Ng1710 <= n6061; - Ng6527 <= n6066_1; - Ng3255 <= n6071_1; - Ng1691 <= n6076_1; - Ng2936 <= n6081; - Ng5644 <= n6086_1; - Ng5152 <= n6091; - Ng5352 <= n6096; - Pg8915 <= n6100_1; - Ng2775 <= n6104; - Ng2922 <= n6109_1; - Ng1111 <= n6114_1; - Ng5893 <= n6119_1; - Pg16603 <= n6123_1; - Ng6617 <= n6127; - Ng2060 <= n6132_1; - Ng4512 <= n6137; - Ng5599 <= n6142; - Ng3401 <= n6147; - Ng4366 <= n6152; - Pg16722 <= n6156; - \[4433] <= n6160; - Ng3129 <= n6165; - Ng3329 <= n6169; - Ng5170 <= n6174_1; - Ng26959 <= n6179; - Ng5821 <= n6183; - Ng6299 <= n6188_1; - Pg8416 <= n6192; - Ng2079 <= n6196; - Ng4698 <= n6201_1; - Ng3703 <= n6206; - Ng1559 <= n6211; - Ng943 <= n6216; - Ng411 <= n6221; - Pg9682 <= n6226; - Ng3953 <= n6230; - Ng2704 <= n6235; - Ng6035 <= n6240; - Ng1300 <= n6245; - Ng4057 <= n6250; - Ng5200 <= n6255; - Ng4843 <= n6260; - Ng5046 <= n6265; - Ng2250 <= n6270; - Ng26885 <= n6275; - Ng4549 <= n6279; - Ng2453 <= n6284; - Ng5841 <= n6289; - Pg14694 <= n6293; - Ng2912 <= n6297; - Ng2357 <= n6302; - Pg8920 <= n6306_1; - Ng164 <= n6310; - Ng4253 <= n6315; - Ng5016 <= n6320; - Ng3119 <= n6325_1; - Ng1351 <= n6330; - Ng1648 <= n6335; - Ng6972 <= n6340; - Ng5115 <= n6344_1; - Ng3352 <= n6349; - Ng6657 <= n6354; - Ng4552 <= n6359; - Ng3893 <= n6364_1; - Ng3211 <= n6369; - Pg13049 <= n6373; - Pg16624 <= n6376; - Ng5595 <= n6380; - Ng3614 <= n6385; - Ng2894 <= n6390; - Ng3125 <= n6395; - Pg16686 <= n6399; - Ng3821 <= n6403; - Ng4141 <= n6408_1; - Ng6974 <= n6413; - Ng5272 <= n6417; - Ng2735 <= n6422; - Ng728 <= n6427; - Ng6295 <= n6432; - Ng2661 <= n6437; - Ng1988 <= n6442; - Ng5128 <= n6447; - Ng1548 <= n6452; - Ng3106 <= n6457; - Ng4659 <= n6462; - Ng4358 <= n6467; - Ng1792 <= n6472; - Ng2084 <= n6477; - Ng3187 <= n6482; - Ng4311 <= n6487; - Ng2583 <= n6492; - Ng3003 <= n6497; - Ng1094 <= n6502; - Ng3841 <= n6507; - Ng4284 <= n6512; - Ng3191 <= n6517; - Ng4239 <= n6522; - Ng4180 <= n6526; - Ng691 <= n6531; - Ng534 <= n6536; - Ng385 <= n6541; - Ng2004 <= n6546; - Ng2527 <= n6551; - Ng5456 <= n6555; - Ng4420 <= n6560; - Ng5148 <= n6565; - Ng4507 <= n6570; - Ng5348 <= n6575; - Ng3223 <= n6580; - Ng2970 <= n6585; - Ng5698 <= n6590; - Ng5260 <= n6595; - Ng1521 <= n6600; - Ng3522 <= n6605; - Ng3115 <= n6610; - Ng3251 <= n6615; - Pg12832 <= n6620; - Ng4628 <= n6624; - Ng1996 <= n6629; - Pg8342 <= n6634; - Ng4515 <= n6638; - Pg8787 <= n6642; - Ng4300 <= n6646; - Ng1724 <= n6651; - Ng1379 <= n6656; - Pg11388 <= n6661; - Ng1878 <= n6665; - Ng5619 <= n6670; - Ng71 <= n6675; - \[4437] <= n6680; - end -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/seq/seq.v b/fpga_flow/benchmarks/Verilog/MCNC/seq/seq.v deleted file mode 100644 index f9b0bf164..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/seq/seq.v +++ /dev/null @@ -1,1127 +0,0 @@ -// Benchmark "TOP" written by ABC on Mon Feb 4 17:33:45 2019 - -module seq ( - i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, - i_11_, i_12_, i_13_, i_14_, i_15_, i_16_, i_17_, i_18_, i_19_, i_20_, - i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, i_30_, - i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_, i_39_, i_40_, - o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, - o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, - o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, - o_31_, o_32_, o_33_, o_34_ ); - input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, - i_10_, i_11_, i_12_, i_13_, i_14_, i_15_, i_16_, i_17_, i_18_, i_19_, - i_20_, i_21_, i_22_, i_23_, i_24_, i_25_, i_26_, i_27_, i_28_, i_29_, - i_30_, i_31_, i_32_, i_33_, i_34_, i_35_, i_36_, i_37_, i_38_, i_39_, - i_40_; - output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, - o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, - o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, - o_31_, o_32_, o_33_, o_34_; - wire n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, - n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, - n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, - n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, - n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, - n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, - n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, - n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, - n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, - n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, - n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, - n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, - n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, - n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, - n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, - n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, - n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, - n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, - n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, - n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, - n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, - n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, - n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, - n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, - n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, - n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, - n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, - n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, - n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, - n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, - n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, - n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, - n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, - n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, - n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, - n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, - n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, - n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, - n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, - n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, - n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, - n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, - n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, - n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, - n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, - n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, - n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, - n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, - n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, - n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, - n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, - n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, - n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, - n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, - n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, - n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781, - n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, - n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805, - n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, - n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, - n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, - n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, - n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, - n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877, - n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, - n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, - n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913, - n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, n925, - n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, n937, - n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, - n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, - n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, - n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, - n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, - n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, - n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, - n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, - n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, - n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, - n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, - n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, - n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, - n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, - n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095; - assign o_0_ = ~n852; - assign o_1_ = ~n754; - assign o_2_ = ~n606; - assign o_3_ = ~n488; - assign o_4_ = ~n426; - assign o_5_ = ~n986 | ~n990 | ~n980 | ~n982 | n191 | n192 | n189 | n190; - assign o_6_ = ~n306; - assign o_7_ = ~n188; - assign o_8_ = ~n111; - assign o_9_ = ~n185; - assign o_10_ = ~n823 | ~n833 | n181 | ~n175 | n180; - assign o_11_ = ~n179; - assign o_12_ = ~n708 & ~n407 & i_8_ & n112; - assign o_13_ = ~n174; - assign o_14_ = ~n173; - assign o_15_ = ~n149; - assign o_16_ = ~n172; - assign o_17_ = ~n1076 | ~n1078 | ~n437 | ~n812 | n165 | n166 | n163 | n164; - assign o_18_ = ~n800; - assign o_19_ = ~n162; - assign o_20_ = ~n728; - assign o_21_ = ~n161; - assign o_22_ = n156 | n157 | n154 | n155 | n160 | ~n662 | n158 | n159; - assign o_23_ = ~n153; - assign o_24_ = ~n146; - assign o_25_ = ~n138; - assign o_26_ = ~n134; - assign o_27_ = ~n131; - assign o_28_ = ~n128; - assign o_29_ = ~n617; - assign o_30_ = ~n1029 | n122 | n123; - assign o_31_ = ~n128 | n116 | n117 | n115 | n113 | n114; - assign o_32_ = ~n1034; - assign o_33_ = ~n576; - assign o_34_ = ~n535; - assign n111 = n223 & n149 & (n224 | n225); - assign n112 = ~n1094 & (~i_37_ | (~n288 & ~n523)); - assign n113 = n200 & (~n715 | (~i_39_ & ~n277)); - assign n114 = ~n610 & n471 & n578; - assign n115 = n579 & ~n222 & ~n257; - assign n116 = n194 & n200; - assign n117 = n385 & (~n387 | ~n715); - assign n118 = ~n909 & ~n410 & ~n877; - assign n119 = ~n906 & ~n410 & ~n877; - assign n120 = ~n909 & ~n414 & ~n877; - assign n121 = ~n906 & ~n414 & ~n877; - assign n122 = ~n946 & (n582 | ~n701 | ~n864); - assign n123 = n118 | n119 | n120 | n121; - assign n124 = n355 | n911; - assign n125 = n577 | n284 | n536; - assign n126 = n515 | n284 | n577; - assign n127 = n899 | n760 | n816; - assign n128 = n127 & n126 & n124 & n125; - assign n129 = ~n117 & n141 & (~n194 | n627); - assign n130 = n954 & n953 & ~n622 & ~n619 & n618 & n328 & n312 & n319; - assign n131 = n129 & n130; - assign n132 = n630 | n476 | n360; - assign n133 = ~n199 & n135 & ~n195; - assign n134 = ~n203 & n132 & n133; - assign n135 = n872 | n893 | ~i_34_ | n611; - assign n136 = n607 & (n608 | n609); - assign n137 = n130 & ~n201; - assign n138 = n137 & n129 & n136 & n128 & n135; - assign n139 = ~n594 & ~i_37_ & i_39_; - assign n140 = ~n902 & (n139 | (~n307 & ~n594)); - assign n141 = n952 & ~n626 & ~n625 & n616 & n315 & ~n140 & ~n113 & ~n123; - assign n142 = n631 & ~n203 & ~n117 & n124; - assign n143 = n577 | n325 | i_39_; - assign n144 = ~n194 | n627; - assign n145 = n1034 & n126 & n127; - assign n146 = n145 & n144 & n143 & n142 & n137 & n133 & n136 & n141; - assign n147 = n407 | n644 | n284 | n462; - assign n148 = i_35_ | i_34_ | n640 | n307; - assign n149 = ~i_7_ | ~i_33_; - assign n150 = n646 | ~i_37_ | n400; - assign n151 = n646 | n515 | n645; - assign n152 = n648 | n519 | n647; - assign n153 = ~n1047 & ~n651 & n152 & n151 & n150 & n149 & n147 & n148; - assign n154 = ~n666 & (~n231 | ~n355 | ~n647); - assign n155 = ~i_40_ & (n667 | (~n338 & n663)); - assign n156 = ~n611 & n663; - assign n157 = n673 & n671 & n672; - assign n158 = ~n685 & (~n669 | (n674 & ~n920)); - assign n159 = n671 & ~i_7_ & i_32_; - assign n160 = ~n708 & n670 & i_37_ & ~n333; - assign n161 = n684 & i_33_ & (i_7_ | n680); - assign n162 = n765 & n766 & (n767 | n267); - assign n163 = n813 & ~n1093 & (~i_29_ | n814); - assign n164 = ~n859 & n649 & n650; - assign n165 = ~n926 & (~n514 | ~n675); - assign n166 = ~n428 & (~n1075 | (n471 & ~n610)); - assign n167 = n338 | n820; - assign n168 = n821 | n514; - assign n169 = n630 | n476 | n815 | n816; - assign n170 = n333 | n307 | n709 | n788; - assign n171 = n451 | n817 | i_40_; - assign n172 = ~n819 & n171 & n170 & n169 & n167 & n168; - assign n173 = n492 & (~i_13_ | n407 | n822); - assign n174 = n492 & (n536 | n333 | n537); - assign n175 = n817 | n549; - assign n176 = n918 | n405 | n917; - assign n177 = n826 | n447 | n825; - assign n178 = n823 & (n225 | n817); - assign n179 = ~n828 & n178 & n177 & n175 & n176; - assign n180 = i_15_ & n834 & i_20_ & i_21_; - assign n181 = n578 & (n830 | (n561 & ~n585)); - assign n182 = n857 | n583 | n456 | n350; - assign n183 = n222 | n221 | n220; - assign n184 = n149 & ~n215 & (n210 | n216); - assign n185 = n184 & n182 & n183; - assign n186 = n240 & n239 & n238 & n182; - assign n187 = n223 & (n869 | (n701 & n242)); - assign n188 = ~n245 & n187 & n184 & n186; - assign n189 = n293 & (n378 | (~i_23_ & ~n377)); - assign n190 = ~n910 & (~n890 | (~i_37_ & ~n307)); - assign n191 = n385 & (n194 | ~n908); - assign n192 = (n194 | n347) & (n384 | ~n951); - assign n193 = i_1_ | i_4_ | i_2_ | i_3_; - assign n194 = i_39_ & n653; - assign n195 = n193 & ~n896 & (n194 | ~n280); - assign n196 = ~n332 & (n628 | (i_0_ & i_4_)); - assign n197 = ~n333 & n629; - assign n198 = ~n225 & ~n933; - assign n199 = (n196 | n197) & (n198 | ~n955); - assign n200 = ~n414 & ~i_24_ & ~n375; - assign n201 = ~n593 & (~n609 | (~n489 & ~n900)); - assign n202 = i_2_ & ~n359; - assign n203 = n202 & ~n333 & (n198 | ~n955); - assign n204 = i_11_ | ~n861; - assign n205 = ~i_17_ | n314; - assign n206 = i_12_ | n413; - assign n207 = (n204 | n205) & (n206 | ~n229); - assign n208 = n211 & (~n729 | (n961 & n962)); - assign n209 = ~i_16_ | n314; - assign n210 = n207 & n208 & (n204 | n209); - assign n211 = i_12_ | ~i_15_ | ~i_17_ | ~n229; - assign n212 = n962 & n961; - assign n213 = n211 & (n212 | ~n729); - assign n214 = n207 & (n204 | n209); - assign n215 = ~n565 & ~n862 & (~n213 | ~n214); - assign n216 = n565 | n318; - assign n217 = ~i_18_ | n428; - assign n218 = n217 & (~i_15_ | ~n963); - assign n219 = n404 | ~n963; - assign n220 = n219 & (~i_19_ | i_21_ | n218); - assign n221 = ~i_23_ | n241; - assign n222 = n864 | n333; - assign n223 = n283 | n677 | n740 | ~n853; - assign n224 = n841 | n500; - assign n225 = ~i_38_ | n771; - assign n226 = i_12_ & n861; - assign n227 = i_22_ & (~n217 | (i_15_ & n226)); - assign n228 = i_15_ & i_22_; - assign n229 = i_11_ & n861; - assign n230 = i_19_ & (n227 | (n228 & n229)); - assign n231 = ~i_40_ | n440; - assign n232 = ~i_38_ | i_39_; - assign n233 = n231 & n232; - assign n234 = n428 | n580 | n265 | n613; - assign n235 = i_35_ | ~i_33_ | ~i_34_; - assign n236 = n779 | i_32_ | n428; - assign n237 = n234 & (~i_21_ | n235 | n236); - assign n238 = n856 | n583 | n225 | n519; - assign n239 = (~i_22_ | n237) & (n866 | ~n964); - assign n240 = n965 & (n864 | n869); - assign n241 = ~i_22_ | ~i_24_; - assign n242 = n870 | n596; - assign n243 = n242 | n241 | n218; - assign n244 = ~n225 | ~n690; - assign n245 = ~n333 & (~n243 | (n244 & ~n537)); - assign n246 = ~n872 & (~n966 | (~n225 & ~n875)); - assign n247 = n657 | n866 | ~n194 | ~n578; - assign n248 = n767 | i_37_ | n350; - assign n249 = n375 | n588 | ~i_24_ | ~n293; - assign n250 = ~n246 & (n536 | n775 | n875); - assign n251 = n250 & n249 & n247 & n248; - assign n252 = ~i_18_ | n253; - assign n253 = n314 & n310; - assign n254 = n252 & (~i_19_ | n253); - assign n255 = ~i_15_ | ~i_18_ | ~i_19_ | ~n293; - assign n256 = ~i_9_ | n323; - assign n257 = n255 & (n254 | n256); - assign n258 = (~i_29_ & n825) | (n366 & (i_29_ | n825)); - assign n259 = i_29_ | n323; - assign n260 = n258 & (~i_30_ | n259); - assign n261 = ~n382 & (~n468 | (~n277 & ~n283)); - assign n262 = n644 | n256 | ~n624; - assign n263 = n907 & n895; - assign n264 = ~n261 & n262 & (n260 | n263); - assign n265 = n859 | n400; - assign n266 = (n476 | n875) & (n400 | n474); - assign n267 = ~i_40_ | n876; - assign n268 = ~i_34_ | n858; - assign n269 = n265 & n266 & (n267 | n268); - assign n270 = i_10_ & i_27_; - assign n271 = n890 | n881 | n322; - assign n272 = (n456 | n887) & (n817 | n338); - assign n273 = n739 | n890 | n721; - assign n274 = n271 & n272 & (~i_11_ | n273); - assign n275 = n283 | n320; - assign n276 = i_36_ | n307; - assign n277 = i_36_ | n647; - assign n278 = n275 & n276 & (~i_39_ | n277); - assign n279 = n396 | ~n653; - assign n280 = i_39_ | n456; - assign n281 = n278 & n279 & n280; - assign n282 = n536 | n500; - assign n283 = ~i_39_ | ~i_40_; - assign n284 = i_37_ | n858; - assign n285 = n282 & (n283 | n284); - assign n286 = (~i_40_ | n325) & (n284 | n440); - assign n287 = n286 & n285; - assign n288 = ~i_38_ | i_40_; - assign n289 = ~n244 & (~i_37_ | n288); - assign n290 = i_12_ | i_11_; - assign n291 = n290 & n228 & ~n256; - assign n292 = i_18_ & n228; - assign n293 = ~n410 | ~n414; - assign n294 = ~n613 & (n291 | (n292 & n293)); - assign n295 = ~i_37_ & ~n558 & (n294 | ~n775); - assign n296 = ~n400 & (n295 | (~n474 & ~n775)); - assign n297 = ~n887 & (n194 | ~n611); - assign n298 = n256 | n504 | ~n624 | n878; - assign n299 = i_32_ | i_13_ | n877 | n382; - assign n300 = n880 | n771 | n875; - assign n301 = n967 & (n263 | n857 | n365); - assign n302 = ~n296 & n970 & (n289 | n337); - assign n303 = (n281 | n889) & (~i_40_ | n274); - assign n304 = n971 & (n269 | n888); - assign n305 = n251 & n973 & (n897 | n702); - assign n306 = n305 & n304 & n303 & n302 & n301 & n300 & n298 & n299; - assign n307 = i_38_ | ~i_40_; - assign n308 = n310 | n901; - assign n309 = n307 | n594; - assign n310 = ~i_11_ | ~i_15_; - assign n311 = n903 | n462 | n881; - assign n312 = (n310 | n311) & (n308 | n309); - assign n313 = ~n835 & ~n881 & (~n451 | ~n690); - assign n314 = ~i_12_ | ~i_15_; - assign n315 = ~n116 & ~n313 & (n311 | n314); - assign n316 = n903 | n253 | n216; - assign n317 = n902 & n308; - assign n318 = n594 | n863; - assign n319 = n316 & (n317 | n318); - assign n320 = i_36_ | i_37_; - assign n321 = n276 & n280 & (~i_39_ | n320); - assign n322 = i_15_ | n323; - assign n323 = i_7_ | i_5_; - assign n324 = n322 & (i_12_ | n323); - assign n325 = i_38_ | n858; - assign n326 = (~i_40_ | n325) & (~i_39_ | n284); - assign n327 = ~n376 & ~n881 & (~n324 | ~n411); - assign n328 = ~n139 | n308; - assign n329 = n974 & (n321 | n889); - assign n330 = (~n194 | n975) & (n318 | ~n1095); - assign n331 = n330 & n329 & n328 & n319 & n315 & n312 & ~n140 & ~n195; - assign n332 = i_7_ | n333; - assign n333 = i_34_ | n407; - assign n334 = (n333 | ~n914) & (n332 | ~n976); - assign n335 = (n334 | n916) & (n273 | ~n290); - assign n336 = n978 & (n821 | (n451 & n549)); - assign n337 = n767 | n463; - assign n338 = ~i_37_ | n232; - assign n339 = n335 & n336 & (n337 | n338); - assign n340 = n835 | ~i_15_ | ~n290; - assign n341 = n340 & (~i_15_ | i_18_ | ~n293); - assign n342 = n314 | n913; - assign n343 = n310 | n913; - assign n344 = i_21_ | n407; - assign n345 = i_19_ | n341; - assign n346 = n342 & n343 & (n344 | n345); - assign n347 = ~i_40_ & ~n908; - assign n348 = n790 | i_34_ | n898; - assign n349 = (n523 | n890) & (n400 | n912); - assign n350 = ~i_39_ | i_40_; - assign n351 = n463 | n645; - assign n352 = n348 & n349 & (n350 | n351); - assign n353 = n322 | n565 | n231; - assign n354 = i_38_ | n577; - assign n355 = ~i_38_ | n396; - assign n356 = n353 & n354 & (n317 | n355); - assign n357 = ~i_25_ & i_26_; - assign n358 = i_4_ & i_1_; - assign n359 = ~i_0_ | i_7_; - assign n360 = ~n914 & (n358 | n359); - assign n361 = n975 | n908; - assign n362 = n915 | n360 | n333; - assign n363 = n519 | n878 | n879 | n549; - assign n364 = n175 & n363 & n361 & n362; - assign n365 = ~i_29_ | n323; - assign n366 = ~i_28_ | n323; - assign n367 = n365 & n366 & (~i_30_ | n323); - assign n368 = n284 | n596; - assign n369 = n368 & n318; - assign n370 = i_14_ | n369 | n314 | n410; - assign n371 = i_34_ | n477; - assign n372 = n370 & (n367 | n350 | n371); - assign n373 = ~i_15_ | i_21_; - assign n374 = n333 | n536 | n439; - assign n375 = n657 | n874; - assign n376 = i_40_ | n859; - assign n377 = (n375 | n376) & (n373 | n374); - assign n378 = ~n235 & ~n779 & (~n906 | ~n909); - assign n379 = n721 | ~i_0_ | n657; - assign n380 = n350 | n379 | i_36_ | ~i_37_; - assign n381 = n279 | n693; - assign n382 = i_12_ | n411; - assign n383 = n381 | n382 | ~i_13_ | i_31_; - assign n384 = ~n909 & ~n410 & ~n657; - assign n385 = ~n410 & ~i_24_ & ~n375; - assign n386 = n260 & (i_30_ | n365); - assign n387 = ~n194 & (i_39_ | n277); - assign n388 = n956 | n919; - assign n389 = n451 | i_40_ | n821; - assign n390 = ~i_13_ | n886; - assign n391 = n388 & n389 & (n387 | n390); - assign n392 = i_13_ | n277 | n283 | ~n853; - assign n393 = n407 | n514 | ~i_40_ | n400; - assign n394 = n235 | n456 | i_32_ | ~i_39_; - assign n395 = n392 & n393 & (~i_13_ | n394); - assign n396 = i_39_ | i_40_; - assign n397 = n267 & (~i_37_ | n396); - assign n398 = n871 | i_34_ | n225; - assign n399 = (n523 | n376) & (n351 | n690); - assign n400 = i_36_ | n868; - assign n401 = n398 & n399 & (n397 | n400); - assign n402 = n322 & (~i_24_ | n323); - assign n403 = n373 | n256 | ~n290; - assign n404 = ~i_18_ | n373; - assign n405 = n403 & (~n293 | n404); - assign n406 = ~i_17_ | n407; - assign n407 = i_32_ | ~i_33_; - assign n408 = n406 & (~i_16_ | n407); - assign n409 = (i_11_ | n314) & (i_12_ | n310); - assign n410 = ~i_11_ | n323; - assign n411 = i_11_ | n323; - assign n412 = (n209 | n411) & (n206 | n410); - assign n413 = ~i_15_ | ~i_16_; - assign n414 = ~i_12_ | n323; - assign n415 = n412 & (i_14_ | n413 | n414); - assign n416 = (n406 | n415) & (n256 | ~n992); - assign n417 = ~n323 & ~n333 & (~n958 | ~n991); - assign n418 = ~i_39_ & (~n892 | ~n979); - assign n419 = ~n1089 & (i_40_ | (n175 & n957)); - assign n420 = n1004 & (n910 | n790); - assign n421 = (n267 | n821) & (n401 | n872); - assign n422 = n1003 & (n695 | n416); - assign n423 = ~n418 & (n474 | (n919 & n1002)); - assign n424 = n1000 & (~i_31_ | (~n417 & n1001)); - assign n425 = n998 & n135 & n176 & n997 & n995 & n996; - assign n426 = n425 & n424 & n423 & n422 & n421 & n420 & n419 & n391; - assign n427 = n929 | n428 | n400; - assign n428 = n854 & (i_5_ | n310); - assign n429 = n427 & (n428 | n400 | n344); - assign n430 = ~i_3_ | n432; - assign n431 = ~i_2_ | n432; - assign n432 = ~i_0_ | i_32_; - assign n433 = n430 & n431 & (n358 | n432); - assign n434 = ~n270 | n396 | n756 | ~n853; - assign n435 = n863 | ~n649 | ~n650; - assign n436 = (n859 | n926) & (n925 | ~n1014); - assign n437 = n436 & n435 & n434 & n149; - assign n438 = n858 | i_5_ | ~i_31_; - assign n439 = ~i_37_ | ~i_35_ | i_36_; - assign n440 = i_38_ | ~i_39_; - assign n441 = (n439 | n440) & (~n314 | n438); - assign n442 = ~i_39_ & n307; - assign n443 = ~i_35_ | n898; - assign n444 = ~i_36_ | n923; - assign n445 = (n283 | n444) & (n396 | n443); - assign n446 = ~n350 & (~n915 | (~n452 & ~n803)); - assign n447 = i_29_ | i_30_; - assign n448 = ~i_5_ & ~n907 & (i_28_ | n447); - assign n449 = n542 | n806 | ~i_15_ | i_17_; - assign n450 = ~n448 & (~i_36_ | n231 | n740); - assign n451 = ~i_37_ | n462; - assign n452 = i_9_ | i_5_; - assign n453 = n449 & n450 & (n451 | n452); - assign n454 = (~i_4_ | n432) & (i_32_ | ~n628); - assign n455 = n454 & n430 & n431; - assign n456 = i_36_ | n477; - assign n457 = n456 & (i_36_ | ~i_39_); - assign n458 = i_11_ & ~n452; - assign n459 = ~n928 & (~n1010 | (n458 & ~n867)); - assign n460 = n932 | i_36_ | ~n863; - assign n461 = ~n459 & n460 & (~i_40_ | ~n1009); - assign n462 = ~i_38_ | ~i_39_; - assign n463 = ~i_0_ | n884; - assign n464 = n288 & n462 & (n463 | n396); - assign n465 = ~i_9_ | ~i_14_ | ~n644 | n737; - assign n466 = ~i_14_ | ~n644; - assign n467 = n465 & (n466 | ~n729); - assign n468 = n456 | n771; - assign n469 = (i_13_ | n468) & (~i_15_ | ~n624); - assign n470 = n150 & (i_5_ | n407 | n371); - assign n471 = ~i_23_ & ~n407; - assign n472 = ~n690 & ~n875 & (~n344 | n471); - assign n473 = n929 & n344; - assign n474 = ~i_37_ | n307; - assign n475 = ~n472 & (n268 | n473 | n474); - assign n476 = i_40_ | n536; - assign n477 = ~i_37_ | i_38_; - assign n478 = n476 & n477; - assign n479 = n928 | n519 | n763; - assign n480 = n479 & (i_18_ | n373 | ~n829); - assign n481 = ~n693 & (~n1008 | (~n467 & ~n702)); - assign n482 = ~n333 & (~n441 | ~n1012 | ~n1013); - assign n483 = (n536 | n926) & (n453 | ~n853); - assign n484 = (n675 | n224) & (n464 | n761); - assign n485 = (n461 | n504) & (n859 | n427); - assign n486 = n1019 & n1020 & (n428 | n475); - assign n487 = n1017 & n1018 & (n927 | ~n1006); - assign n488 = n487 & n486 & n485 & n484 & n483 & ~n482 & n437 & ~n481; - assign n489 = i_31_ | n333; - assign n490 = (n368 | n489) & (n216 | ~n466); - assign n491 = n333 | n870; - assign n492 = n149 & (n491 | (n231 & n355)); - assign n493 = ~n904 & (i_9_ | ~n672); - assign n494 = ~i_31_ & ~n290 & (~n279 | ~n287); - assign n495 = n858 | ~i_5_ | n493; - assign n496 = (n788 | n690) & (n476 | n933); - assign n497 = n496 & ~n494 & n495; - assign n498 = ~i_34_ & ~n320 & (~n462 | ~n536); - assign n499 = (n400 | n675) & (n594 | ~n863); - assign n500 = ~i_37_ | n858; - assign n501 = ~n498 & n499 & (n231 | n500); - assign n502 = n763 | n718; - assign n503 = n504 | n280; - assign n504 = i_35_ | n855; - assign n505 = n502 & n503 & (n278 | n504); - assign n506 = ~n284 & ~i_15_ & i_39_; - assign n507 = ~n690 & ~i_35_ & ~i_37_; - assign n508 = ~n489 & (n506 | (n507 & ~n644)); - assign n509 = n815 | n739 | n935; - assign n510 = i_2_ | ~i_0_ | i_1_; - assign n511 = n657 | n444; - assign n512 = ~n283 | n235 | n277; - assign n513 = n509 & (n510 | (n511 & n512)); - assign n514 = i_37_ | n536; - assign n515 = i_38_ | i_40_; - assign n516 = n514 & (i_37_ | n515); - assign n517 = n511 & (~i_40_ | n338 | n739); - assign n518 = (n504 | n859) & (n690 | n718); - assign n519 = ~i_33_ | n858; - assign n520 = n517 & n518 & (n516 | n519); - assign n521 = n451 | ~i_40_ | n268; - assign n522 = n860 & n882; - assign n523 = ~i_36_ | n868; - assign n524 = n521 & (n522 | n523); - assign n525 = ~n510 & ~i_3_ & ~i_4_; - assign n526 = n525 & (~n706 | (i_39_ & ~n756)); - assign n527 = ~n526 & (~i_5_ | i_36_ | ~n674); - assign n528 = i_9_ & (n508 | (~n490 & ~n904)); - assign n529 = (n490 | n672) & (n497 | n333); - assign n530 = (n505 | n878) & (n224 | n355); - assign n531 = n501 | n936; - assign n532 = (n513 | n925) & (n520 | n648); - assign n533 = (n527 | ~n853) & (n524 | n934); - assign n534 = n749 & (~i_11_ | n550 | n741); - assign n535 = n534 & n533 & n532 & n531 & n530 & n529 & n492 & ~n528; - assign n536 = i_38_ | i_39_; - assign n537 = ~i_35_ | n871; - assign n538 = ~i_17_ | n539; - assign n539 = i_32_ | i_31_; - assign n540 = n538 & (~i_16_ | n539); - assign n541 = ~n540 & (~n503 | (~n504 & ~n542)); - assign n542 = i_36_ | n462; - assign n543 = n503 & (~i_40_ | n504 | n542); - assign n544 = n543 | i_14_ | n540; - assign n545 = (i_12_ | n1022) & (i_15_ | n940); - assign n546 = n462 | n500; - assign n547 = n544 & n545 & (n489 | n546); - assign n548 = n756 | n771 | n333; - assign n549 = i_37_ | n232; - assign n550 = n407 | n894; - assign n551 = n548 & (n270 | n549 | n550); - assign n552 = n1023 & (n218 | n241 | n941); - assign n553 = n1024 & (n350 | n756); - assign n554 = i_31_ | i_15_ | i_5_; - assign n555 = n552 & n553 & (n287 | n554); - assign n556 = n511 & (n235 | n277); - assign n557 = ~n815 & ~n657 & i_36_ & ~n476; - assign n558 = ~i_38_ | ~i_40_; - assign n559 = (n474 | n523) & (n558 | ~n959); - assign n560 = ~i_13_ & ~n407; - assign n561 = ~n231 & ~n268; - assign n562 = n560 & (n561 | (~n476 & ~n875)); - assign n563 = ~n863 | ~n890; - assign n564 = ~n881 & (~n307 | n563 | ~n770); - assign n565 = i_31_ | n407; - assign n566 = n284 | n355; - assign n567 = ~n562 & ~n564 & (n565 | n566); - assign n568 = ~n869 & (~n941 | ~n942); - assign n569 = ~n925 & (n557 | (~n510 & ~n556)); - assign n570 = (n204 | n1022) & (~i_32_ | i_33_); - assign n571 = (n333 | n555) & (n801 | ~n943); - assign n572 = (n381 | n554) & (n547 | ~n861); - assign n573 = ~n568 & (n931 | (n222 & n937)); - assign n574 = n1025 & (~n290 | n550 | n741); - assign n575 = ~n569 & n1026 & (n935 | n939); - assign n576 = n575 & n574 & n573 & n572 & n571 & n570 & n551 & n186; - assign n577 = n899 | n841 | n816; - assign n578 = n293 & n873; - assign n579 = ~i_23_ & n921; - assign n580 = ~i_21_ | ~i_23_; - assign n581 = ~n870 & n580 & ~n690; - assign n582 = ~n462 & ~n870; - assign n583 = i_28_ | i_5_ | i_29_; - assign n584 = n583 & (i_5_ | ~n960); - assign n585 = ~i_25_ | n407; - assign n586 = n585 & (~i_26_ | n407); - assign n587 = n841 | n566; - assign n588 = i_37_ | n771; - assign n589 = n400 | n613; - assign n590 = n587 & (n428 | n588 | n589); - assign n591 = ~i_22_ | n373; - assign n592 = (n217 | ~n921) & (n591 | ~n963); - assign n593 = n500 | n790; - assign n594 = i_34_ | n858; - assign n595 = n593 & (n594 | n225); - assign n596 = ~i_38_ | n283; - assign n597 = n596 & n476; - assign n598 = n1030 & (n771 | n870 | n931); - assign n599 = (n537 | n690) & (n1031 | n933); - assign n600 = n598 & n599 & (n597 | n439); - assign n601 = (n801 | n939) & (n588 | ~n943); - assign n602 = (n586 | n822) & (n600 | n333); - assign n603 = n224 | n790; - assign n604 = n1032 & (n592 | n596 | n589); - assign n605 = n374 | n220 | n221; - assign n606 = n605 & n604 & n603 & n602 & n184 & n601 & n590 & n551; - assign n607 = n900 | n608 | n489; - assign n608 = n771 | n803; - assign n609 = n447 | n366 | n489; - assign n610 = n400 | n376; - assign n611 = i_40_ | n514; - assign n612 = n610 & (n400 | n611); - assign n613 = ~i_24_ | n407; - assign n614 = (n612 | n613) & (n224 | n231); - assign n615 = n614 | ~n293 | n591; - assign n616 = n767 | n895; - assign n617 = n616 & n615 & n136 & ~n201; - assign n618 = i_23_ | n222 | ~n293 | n373; - assign n619 = ~n265 & (~n342 | ~n343); - assign n620 = ~n410 & n905; - assign n621 = ~n414 & n905; - assign n622 = ~n318 & (n620 | n621); - assign n623 = ~n375 & ~i_23_ & n293; - assign n624 = ~n350 & n653; - assign n625 = n624 & (n384 | n623 | ~n951); - assign n626 = ~n950 & (n194 | ~n949); - assign n627 = n906 | n657 | n410; - assign n628 = i_0_ & i_1_; - assign n629 = i_3_ & ~n359; - assign n630 = n333 | n443; - assign n631 = n515 | n630 | n360; - assign n632 = (i_37_ | n690) & (n463 | n923); - assign n633 = n632 & n588 & n514; - assign n634 = n290 & (i_9_ | i_16_); - assign n635 = i_9_ | i_16_ | i_36_ | ~i_39_; - assign n636 = n867 | n290; - assign n637 = n635 & n636 & (n307 | n634); - assign n638 = n1090 & (~i_37_ | n648 | n855); - assign n639 = n1035 & n1036 & (n894 | n646); - assign n640 = i_15_ | n407; - assign n641 = n638 & n639 & (n284 | n640); - assign n642 = i_3_ | n899; - assign n643 = n642 | i_38_; - assign n644 = i_11_ & i_12_; - assign n645 = ~i_37_ | n868; - assign n646 = ~i_0_ | n407; - assign n647 = i_38_ | i_37_; - assign n648 = i_32_ | i_0_ | ~i_5_; - assign n649 = ~n268 & ~n407; - assign n650 = n884 | i_2_ | i_3_; - assign n651 = n649 & (~n643 | (~n477 & n650)); - assign n652 = ~n841 & (~n1037 | (n283 & ~n803)); - assign n653 = i_38_ & ~n320; - assign n654 = ~n693 & (~n1038 | (i_40_ & n653)); - assign n655 = ~n594 & (~n922 | ~n936 | ~n1040); - assign n656 = ~n333 & (~n1043 | ~n1044 | ~n1045); - assign n657 = ~i_35_ | n855; - assign n658 = (n267 | n519) & (~n194 | n657); - assign n659 = ~n708 & (~n1049 | (~n333 & ~n955)); - assign n660 = ~i_5_ | n721; - assign n661 = (n514 | n718) & (n657 | n715); - assign n662 = ~n659 & (n660 | (n658 & n661)); - assign n663 = ~i_7_ & n792; - assign n664 = n663 & (~n1048 | (i_9_ & ~n314)); - assign n665 = ~i_11_ | i_7_ | ~i_9_; - assign n666 = ~n664 & (~i_15_ | n665 | ~n792); - assign n667 = ~n920 & ~n665 & ~n314 & ~i_31_ & ~i_37_; - assign n668 = n923 & ~n904 & n440 & n232 & n288; - assign n669 = n668 | ~i_33_ | n594; - assign n670 = (i_35_ & ~n690) | (~n225 & (~i_35_ | ~n690)); - assign n671 = i_33_ & ~n594; - assign n672 = ~i_16_ | ~i_17_; - assign n673 = ~i_9_ & ~n685; - assign n674 = ~i_15_ | n466; - assign n675 = i_38_ | n771; - assign n676 = (n675 | n443) & (n596 | n537); - assign n677 = ~i_36_ | n647; - assign n678 = n268 & (i_35_ | n677 | n396); - assign n679 = n500 | n596 | i_6_ | ~i_34_; - assign n680 = n679 & ~n1091 & (~i_32_ | n678); - assign n681 = n1050 & (n523 | n923); - assign n682 = (n645 | n690) & (n860 | n894); - assign n683 = n681 & n682 & (n516 | n268); - assign n684 = n323 | i_0_ | n683; - assign n685 = ~i_5_ | i_7_; - assign n686 = i_17_ | n407; - assign n687 = (n685 | n686) & (n407 | ~n673); - assign n688 = (~n673 | n686) & (i_16_ | n687); - assign n689 = ~n408 & (~n318 | (~n594 & ~n859)); - assign n690 = ~i_38_ | n350; - assign n691 = ~n689 & (n284 | n333 | n690); - assign n692 = n456 | n283; - assign n693 = i_35_ | n407; - assign n694 = ~n829 & (n692 | n693); - assign n695 = n318 & n862; - assign n696 = n408 | n695 | i_14_; - assign n697 = i_9_ & (~n696 | (~i_12_ & ~n691)); - assign n698 = ~i_16_ | n406 | ~n466 | n695; - assign n699 = n594 | n922; - assign n700 = ~n697 & n698 & (n493 | n699); - assign n701 = n870 | n476; - assign n702 = n283 | ~n653; - assign n703 = (n440 | n284) & (n771 | n325); - assign n704 = n468 & (~i_13_ | i_36_ | n675); - assign n705 = n704 & n703 & n702 & n701 & n566 & n282; - assign n706 = n771 | n444; - assign n707 = n706 & (i_40_ | n542); - assign n708 = i_0_ | n685; - assign n709 = i_7_ | n290; - assign n710 = (n705 | n709) & (n707 | n708); - assign n711 = n785 & n867 & n780; - assign n712 = n711 & (i_36_ | n288); - assign n713 = ~i_31_ | n721; - assign n714 = (n711 | n660) & (n712 | n713); - assign n715 = ~i_40_ | n908; - assign n716 = n279 & n715 & (~i_39_ | n277); - assign n717 = n1053 & n503 & (n716 | n504); - assign n718 = i_36_ | n855; - assign n719 = n658 & n717 & (n522 | n718); - assign n720 = (~i_13_ | n715) & (~i_9_ | ~n194); - assign n721 = i_7_ | i_32_; - assign n722 = (n719 | n721) & (n720 | n332); - assign n723 = i_11_ | n691 | i_7_ | ~i_9_; - assign n724 = (i_7_ | n700) & (n710 | n333); - assign n725 = n694 | n709; - assign n726 = (n714 | n504) & (i_15_ | n722); - assign n727 = n1054 & n1055 & (n688 | n594); - assign n728 = n727 & n726 & n725 & n724 & n662 & n723; - assign n729 = i_15_ & ~n672; - assign n730 = n729 & ~i_5_ & i_12_; - assign n731 = ~i_14_ & (n730 | (n226 & ~n737)); - assign n732 = ~n282 & (~n213 | ~n214 | n731); - assign n733 = n1058 & (n931 | (n1057 & n285)); - assign n734 = ~n732 & (n439 | (n283 & n355)); - assign n735 = n1030 & (n537 | (n350 & n440)); - assign n736 = n735 & n734 & n733 & n441; - assign n737 = ~i_15_ | n904; - assign n738 = (n428 | n672) & (n737 | ~n963); - assign n739 = ~i_36_ | n855; - assign n740 = i_11_ | ~i_12_; - assign n741 = ~i_40_ | n890; - assign n742 = n741 | n739 | n740; - assign n743 = ~n563 & (i_37_ | ~i_40_ | ~n232); - assign n744 = n560 & n938; - assign n745 = n744 & (~n1056 | (~n594 & ~n743)); - assign n746 = ~n931 & (~n381 | ~n694 | ~n883); - assign n747 = ~n504 & ~n702; - assign n748 = ~i_32_ & (~n742 | (~n738 & n747)); - assign n749 = n368 | n467 | n333; - assign n750 = n1059 & (n586 | n647 | n523); - assign n751 = n1060 & (~n863 | n920 | n932); - assign n752 = (n860 | n939) & (n736 | n333); - assign n753 = ~n746 & (~n943 | (n474 & n956)); - assign n754 = n753 & n752 & n751 & n750 & n749 & ~n748 & n149 & n590; - assign n755 = ~i_36_ | n477; - assign n756 = ~i_38_ | n871; - assign n757 = (~i_40_ | n755) & (n283 | n756); - assign n758 = n924 | n283 | n235; - assign n759 = n758 & (n757 | n657); - assign n760 = ~i_38_ | n630; - assign n761 = n841 | n284; - assign n762 = n760 & (n761 | (n536 & n515)); - assign n763 = i_40_ | n549; - assign n764 = n741 & n763; - assign n765 = (n821 | n935) & (n764 | n944); - assign n766 = n1062 & (n456 | n396 | n897); - assign n767 = n872 | n523; - assign n768 = ~i_15_ | i_40_ | ~n644 | n803; - assign n769 = n546 & n768; - assign n770 = i_37_ | n283; - assign n771 = i_39_ | ~i_40_; - assign n772 = n288 & n770 & (~i_37_ | n771); - assign n773 = (i_11_ | n307) & (n270 | n288); - assign n774 = ~n872 & (~n338 | ~n912); - assign n775 = ~n873 | ~n293 | n613; - assign n776 = ~n774 & (n775 | (n477 & n558)); - assign n777 = ~i_37_ | ~i_39_; - assign n778 = n675 & n690 & n777 & n588; - assign n779 = ~i_40_ | n867; - assign n780 = i_36_ | n232; - assign n781 = n779 & n277 & (i_40_ | n780); - assign n782 = n729 & ~i_7_ & ~n466; - assign n783 = (n253 | n256) & (~n293 | n413); - assign n784 = n333 | n816 | n915 | n815; - assign n785 = n924 & n277; - assign n786 = i_31_ | n504; - assign n787 = n784 & (n785 | n323 | n786); - assign n788 = i_37_ | n893; - assign n789 = (n476 | n788) & (~i_38_ | n351); - assign n790 = i_38_ | n350; - assign n791 = n790 & (i_39_ | i_37_); - assign n792 = ~i_31_ & n671; - assign n793 = ~n386 & n792 & (~n225 | ~n895); - assign n794 = ~n817 & (~n232 | (i_37_ & ~n350)); - assign n795 = n1092 & (~i_36_ | n773 | n891); - assign n796 = n1071 & (n588 | n887); - assign n797 = (n820 | n923) & (n855 | ~n1064); - assign n798 = n1069 & n1070 & (n787 | n396); - assign n799 = n1068 & n1067 & n1066 & n957 & n823 & ~n794 & ~n159 & ~n793; - assign n800 = n799 & n798 & n797 & n796 & n795 & n251; - assign n801 = n882 & n859; - assign n802 = n801 & n611; - assign n803 = ~i_38_ | n858; - assign n804 = n282 & (~i_39_ | n803); - assign n805 = n326 & n804 & (n284 | n288); - assign n806 = ~i_12_ | n452; - assign n807 = ~n458 & n806; - assign n808 = n546 & (n350 | n803); - assign n809 = n804 | n807 | ~i_15_ | i_17_; - assign n810 = n805 | n807 | ~i_15_ | i_16_; - assign n811 = n809 & n810 & (n808 | n452); - assign n812 = n433 | i_40_ | n755 | n657; - assign n813 = ~i_5_ & (~n907 | (~n350 & ~n456)); - assign n814 = n853 & ~i_31_ & ~i_28_ & i_30_; - assign n815 = i_2_ | ~n628; - assign n816 = i_7_ | i_3_ | ~i_4_; - assign n817 = n872 | n268; - assign n818 = ~n332 & n525; - assign n819 = n818 & (~n955 | (~n232 & ~n933)); - assign n820 = (i_40_ & n944) | (n821 & (~i_40_ | n944)); - assign n821 = n872 | n894; - assign n822 = n523 | n514; - assign n823 = n817 | n741; - assign n824 = ~n540 & ~n256 & ~n409; - assign n825 = i_28_ | n323; - assign n826 = n907 | i_31_ | n693; - assign n827 = ~n503 | n747; - assign n828 = n827 & (n824 | (~n412 & ~n538)); - assign n829 = ~n333 & n582; - assign n830 = i_24_ & i_23_ & i_25_ & n829; - assign n831 = n1053 & ~n865 & n917; - assign n832 = ~i_24_ | i_32_; - assign n833 = n831 | ~i_25_ | ~n293 | n832 | ~n873; - assign n834 = n293 & (~n1080 | (~n221 & n829)); - assign n835 = i_9_ | n323; - assign n836 = n252 | n832 | n835 | ~n865; - assign n837 = n863 | n400; - assign n838 = n256 | ~i_40_ | n254 | n613 | n837; - assign n839 = n928 | n786 | n410 | i_12_ | i_17_; - assign n840 = n839 & (~i_21_ | ~n293 | n375); - assign n841 = ~i_34_ | n407; - assign n842 = n325 | n283 | n841; - assign n843 = ~i_18_ & ~n340 & (~n222 | n829); - assign n844 = n293 & ~n927 & (n561 | ~n612); - assign n845 = ~n826 & (~n900 | (~n366 & ~n447)); - assign n846 = n579 & (~n836 | ~n838); - assign n847 = n331 & n1088 & (n350 | n957); - assign n848 = n1087 & n1086 & (n675 | n919); - assign n849 = ~n845 & n1084 & (n842 | n879); - assign n850 = n1083 & n1082 & (n222 | n345); - assign n851 = n1081 & n1054 & n953 & ~n843 & n616 & ~n201 & ~n113 & ~n199; - assign n852 = n851 & n850 & n849 & n848 & n847 & n178 & n142 & n391; - assign n853 = ~i_32_ & ~n504; - assign n854 = i_5_ | n314; - assign n855 = ~i_33_ | i_34_; - assign n856 = i_30_ | n539; - assign n857 = n856 | n504; - assign n858 = i_36_ | i_35_; - assign n859 = i_37_ | n462; - assign n860 = ~i_40_ | n859; - assign n861 = ~i_5_ & i_9_; - assign n862 = n860 | n594; - assign n863 = ~i_37_ | n536; - assign n864 = n439 | n675; - assign n865 = ~n468 & ~n657; - assign n866 = ~i_23_ | n832; - assign n867 = i_36_ | n440; - assign n868 = i_34_ | ~i_35_; - assign n869 = n333 | n428 | ~i_21_ | n241; - assign n870 = ~i_35_ | n320; - assign n871 = ~i_36_ | i_37_; - assign n872 = i_7_ | n407; - assign n873 = n228 & i_21_; - assign n874 = ~i_15_ | i_32_; - assign n875 = i_37_ | n868; - assign n876 = ~i_37_ | n440; - assign n877 = n235 | n692; - assign n878 = i_15_ | n539; - assign n879 = ~i_13_ | n323; - assign n880 = n879 | n640; - assign n881 = n594 | n565; - assign n882 = ~i_40_ | n863; - assign n883 = n333 | n307 | n439; - assign n884 = i_4_ | i_1_; - assign n885 = n489 | ~i_13_ | n382; - assign n886 = n382 | i_32_ | n657; - assign n887 = i_13_ | n886; - assign n888 = n640 | i_13_ | n323; - assign n889 = n879 | n504 | n878; - assign n890 = i_37_ | n440; - assign n891 = i_7_ | ~n853; - assign n892 = n756 | n270 | n891; - assign n893 = i_35_ | ~i_36_; - assign n894 = i_34_ | n893; - assign n895 = i_40_ | n876; - assign n896 = n235 | n721; - assign n897 = n650 | n896; - assign n898 = ~i_36_ | ~i_37_; - assign n899 = ~i_2_ | ~i_0_ | i_1_; - assign n900 = n825 | ~i_29_ | ~i_30_; - assign n901 = n835 | i_16_ | n565; - assign n902 = n314 | n901; - assign n903 = i_17_ | n835; - assign n904 = ~i_16_ & ~i_17_; - assign n905 = n904 & i_15_ & ~n565; - assign n906 = i_22_ | n874; - assign n907 = ~i_40_ | n780; - assign n908 = i_36_ | n536; - assign n909 = i_32_ | n373; - assign n910 = n463 | n817; - assign n911 = n788 | ~n270 | n332; - assign n912 = ~i_37_ | n515; - assign n913 = n344 | i_18_ | n835; - assign n914 = n629 | n202; - assign n915 = ~i_35_ | n477; - assign n916 = ~i_38_ | n893; - assign n917 = n657 | n702; - assign n918 = i_32_ | n241; - assign n919 = n400 | n880; - assign n920 = i_36_ | n504; - assign n921 = ~i_21_ & i_22_; - assign n922 = ~i_31_ | n407; - assign n923 = ~i_37_ | ~i_38_; - assign n924 = i_36_ | n923; - assign n925 = i_32_ | i_3_ | ~i_4_; - assign n926 = i_24_ | n428 | n407 | n400; - assign n927 = ~i_15_ | n407; - assign n928 = i_16_ | n874; - assign n929 = i_22_ | n407; - assign n930 = i_40_ | n235 | n899 | n925; - assign n931 = i_13_ | i_15_ | i_5_; - assign n932 = i_32_ | i_5_ | ~i_31_; - assign n933 = ~i_37_ | n893; - assign n934 = ~i_6_ | n407; - assign n935 = i_40_ | n863; - assign n936 = ~i_5_ | n407; - assign n937 = ~n829 & n842; - assign n938 = ~i_5_ & ~n290; - assign n939 = ~n649 | n650; - assign n940 = n565 | i_34_ | ~n507; - assign n941 = n283 | n870; - assign n942 = n647 | ~i_35_ | n396; - assign n943 = ~n400 & n744; - assign n944 = n400 | n872; - assign n945 = n333 | ~i_15_ | ~i_24_; - assign n946 = n945 | i_22_ | ~n293; - assign n947 = n277 | n396; - assign n948 = n400 | n882; - assign n949 = n947 & n468; - assign n950 = n906 | n657 | n414; - assign n951 = n909 | n657 | n414; - assign n952 = (n949 | n627) & (n947 | n951); - assign n953 = i_37_ | n317 | n594 | n288; - assign n954 = n1033 & (n346 | n948); - assign n955 = n596 | n788; - assign n956 = n514 & n859; - assign n957 = n379 | n924; - assign n958 = (i_38_ & n500) | (n284 & (~i_38_ | n500)); - assign n959 = (~i_37_ & ~n523) | (~n268 & (i_37_ | ~n523)); - assign n960 = (i_28_ & (i_29_ | i_30_)) | (i_29_ & ~i_30_); - assign n961 = i_5_ | n740; - assign n962 = i_12_ | i_5_ | ~i_11_; - assign n963 = n226 | n229; - assign n964 = n865 & (n230 | (n292 & n963)); - assign n965 = (n841 | n608) & (n233 | n761); - assign n966 = (n400 | n876) & (n647 | n523); - assign n967 = ~n578 | n224 | n231; - assign n968 = n882 | n881 | n322; - assign n969 = n968 & (i_31_ | n264 | ~n853); - assign n970 = n969 & (n257 | n221 | n883); - assign n971 = ~n297 & (n885 | (n287 & n566)); - assign n972 = (n821 | n895) & (n396 | n892); - assign n973 = n972 & (n588 | n390); - assign n974 = ~n327 & (n885 | (n282 & n326)); - assign n975 = n950 & n627; - assign n976 = n884 & i_0_; - assign n977 = n539 | n519 | n382 | n890; - assign n978 = n977 & (n400 | n514 | n888); - assign n979 = n357 | n677 | n657 | n721; - assign n980 = n248 & n607 & n127 & n383 & n979 & n380; - assign n981 = n907 | n857 | n259; - assign n982 = n981 & (n771 | n277 | n887); - assign n983 = (n232 | n911) & (n372 | n565); - assign n984 = n983 & (n817 | n770); - assign n985 = (n352 | n872) & (n356 | n284); - assign n986 = n984 & n985 & (n368 | ~n1095); - assign n987 = (n346 | n837) & (n975 | n280); - assign n988 = (~i_40_ & n364) | (n339 & (i_40_ | n364)); - assign n989 = n331 & n988 & (~n200 | n908); - assign n990 = n987 & n989 & (n882 | n821); - assign n991 = (~n283 | n803) & (~i_39_ | n325); - assign n992 = ~n408 & (~n409 | (~i_14_ & ~n314)); - assign n993 = n890 | n594 | n888; - assign n994 = n993 & (n456 | n390); - assign n995 = n447 | n825 | ~n853 | n907; - assign n996 = i_5_ | n713 | ~n904 | n920; - assign n997 = n268 | n876 | n880; - assign n998 = n893 | n332 | n283 | i_38_ | n740; - assign n999 = n491 | n402 | n675; - assign n1000 = n999 & (n386 | n407 | n593); - assign n1001 = i_36_ | ~n672 | n835 | ~n853; - assign n1002 = ~i_23_ | n257 | n589 | ~n921; - assign n1003 = (n395 | n382) & (n324 | n699); - assign n1004 = (n225 | n337) & (n817 | n895); - assign n1005 = ~i_32_ & (~n503 | (~n519 & ~n860)); - assign n1006 = ~n212 & (~n318 | (~n284 & ~n462)); - assign n1007 = n469 | i_12_ | i_5_; - assign n1008 = n1007 & (n931 | (n468 & ~n624)); - assign n1009 = ~n455 & (~n898 | (i_36_ & ~n462)); - assign n1010 = (n807 | n276) & (n457 | n806); - assign n1011 = (n442 | n933) & (n445 | n463); - assign n1012 = ~n446 & n1011 & (i_14_ | n438); - assign n1013 = (n439 | n515) & (~n244 | n537); - assign n1014 = ~n899 & (~n511 | (~n235 & ~n908)); - assign n1015 = i_17_ | n874 | n503 | n806; - assign n1016 = n1015 & (n854 | ~n904 | ~n1005); - assign n1017 = n1016 & (i_25_ | n407 | n822); - assign n1018 = n912 | n433 | n657; - assign n1019 = (n429 | n478) & (n807 | n480); - assign n1020 = (n320 | n930) & (n470 | n350); - assign n1021 = n827 & ~i_5_ & n466; - assign n1022 = ~n541 & n940; - assign n1023 = n931 | n942; - assign n1024 = (n476 | n933) & (n231 | n443); - assign n1025 = n174 & (~i_16_ | n538 | ~n1021); - assign n1026 = (n559 | n934) & (n567 | ~n938); - assign n1027 = n293 & (n581 | (~i_21_ & ~n701)); - assign n1028 = ~i_24_ | i_21_ | i_23_ | n222 | n257; - assign n1029 = n124 & n1028 & (n945 | ~n1027); - assign n1030 = n225 | ~i_35_ | i_37_; - assign n1031 = n307 & n440; - assign n1032 = n565 | n584 | n595; - assign n1033 = (~n384 | n947) & (n862 | ~n1095); - assign n1034 = n944 | i_40_ | n338; - assign n1035 = n936 | i_34_ | i_35_; - assign n1036 = n642 | n407 | n645; - assign n1037 = (n284 | n463) & (n1031 | n500); - assign n1038 = n907 & (n677 | n396); - assign n1039 = n462 | i_9_ | n407; - assign n1040 = n1039 & (n440 | n640); - assign n1041 = (~i_35_ | n633) & (n307 | n893); - assign n1042 = (n232 | n788) & (n350 | n915); - assign n1043 = n1041 & n1042 & (i_40_ | n916); - assign n1044 = (i_38_ | n537) & (n439 | ~n690); - assign n1045 = (~n283 | n456) & (~i_39_ | n933); - assign n1046 = (~i_38_ | n641) & (n637 | ~n853); - assign n1047 = n655 | n652 | n654 | ~n1046 | n656 | ~n937; - assign n1048 = n209 & (~i_16_ | n310); - assign n1049 = n760 & (n277 | ~n283 | n693); - assign n1050 = n898 | i_34_ | n225; - assign n1051 = n443 | i_0_ | n476; - assign n1052 = n1051 & (i_6_ | n676); - assign n1053 = n657 | n947; - assign n1054 = n677 | n891 | ~i_11_ | n283; - assign n1055 = n660 | n376 | n718; - assign n1056 = n566 & (n500 | n231); - assign n1057 = (n536 | n870) & (n1031 | n284); - assign n1058 = n596 | n933; - assign n1059 = n699 | i_5_ | n493; - assign n1060 = ~n745 & (n476 | n788 | n841); - assign n1061 = n759 | ~i_6_ | n721; - assign n1062 = n1061 & (n762 | n816 | n510); - assign n1063 = i_14_ & (~n209 | (i_17_ & ~n314)); - assign n1064 = ~n1074 & (n782 | (~n665 & n1063)); - assign n1065 = i_31_ | n769 | n855 | n256; - assign n1066 = n1065 & (n781 | n783 | n786); - assign n1067 = (n789 | n872) & (n791 | n910); - assign n1068 = n916 | ~i_40_ | ~n818; - assign n1069 = n888 | n771 | n875; - assign n1070 = ~n578 | n842; - assign n1071 = (n776 | n400) & (n778 | n821); - assign n1072 = ~n455 & (~n706 | (~n283 & ~n756)); - assign n1073 = n268 | n473 | n267; - assign n1074 = n282 & n368; - assign n1075 = n1073 & (n489 | ~n904 | n1074); - assign n1076 = (n489 | n811) & (n504 | ~n1072); - assign n1077 = (n277 | n930) & (n429 | n802); - assign n1078 = n1077 & (n630 | n790); - assign n1079 = ~n649 | ~i_22_ | n231; - assign n1080 = n1079 & (n831 | n918); - assign n1081 = n537 | n332 | n536 | i_25_ | i_26_; - assign n1082 = ~n844 & (n556 | n642 | n721); - assign n1083 = n885 | n284 | n288; - assign n1084 = n889 | i_40_ | ~n653; - assign n1085 = (n390 | n715) & (n337 | n923); - assign n1086 = ~n846 & n1085 & (~n194 | n840); - assign n1087 = (n775 | n948) & (n864 | n946); - assign n1088 = (~n621 | n862) & (n647 | n910); - assign n1089 = i_40_ & (~n994 | (~n514 & ~n910)); - assign n1090 = n519 | i_37_ | i_32_ | n634; - assign n1091 = ~i_34_ & (~n1052 | (i_32_ & n858)); - assign n1092 = i_36_ | n772 | n897; - assign n1093 = ~i_29_ & (~i_28_ | n857); - assign n1094 = ~i_37_ & (n268 | n515); - assign n1095 = n620 | n621; -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/spla/spla.v b/fpga_flow/benchmarks/Verilog/MCNC/spla/spla.v deleted file mode 100644 index dad275454..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/spla/spla.v +++ /dev/null @@ -1,2462 +0,0 @@ -// Benchmark "TOP" written by ABC on Mon Feb 4 17:34:12 2019 - -module spla ( - i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, - i_11_, i_12_, i_13_, i_14_, i_15_, - o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, - o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, - o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, - o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_, - o_41_, o_42_, o_43_, o_44_, o_45_ ); - input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, - i_10_, i_11_, i_12_, i_13_, i_14_, i_15_; - output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, - o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, - o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, - o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_, - o_41_, o_42_, o_43_, o_44_, o_45_; - wire n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, - n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, - n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, - n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, - n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, - n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, - n179, n180, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, - n191, n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, - n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, - n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, - n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, - n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, - n251, n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, - n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, - n275, n276, n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, - n287, n288, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, - n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, - n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, - n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, - n335, n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, - n347, n348, n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, - n359, n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, - n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, - n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, - n395, n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, - n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, - n419, n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, - n431, n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, - n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, - n455, n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, - n467, n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, - n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, - n491, n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, - n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, - n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, - n527, n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, - n539, n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, - n551, n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, - n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, - n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, - n587, n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, - n599, n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, - n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, - n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, - n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, - n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, - n659, n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, - n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, - n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, - n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, - n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, - n719, n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, - n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, - n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, - n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, - n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, - n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, - n791, n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, - n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, - n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, - n827, n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, - n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, - n851, n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, - n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, - n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, - n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, - n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, - n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, - n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, - n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, - n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, - n959, n960, n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, - n971, n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, - n983, n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, - n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, - n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, - n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, - n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, - n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, - n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, - n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, - n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, - n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, - n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, - n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, - n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, - n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, - n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, - n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, - n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, - n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, - n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, - n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, - n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, - n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, - n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, - n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, - n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, - n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, - n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, - n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, - n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, - n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, - n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, - n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, - n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, - n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, - n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, - n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, - n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, - n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, - n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, - n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, - n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, - n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, - n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, - n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, - n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, - n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, - n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, - n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, - n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, - n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, - n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, - n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, - n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, - n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, - n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, - n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, - n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, - n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, - n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, - n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, - n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, - n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, - n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, - n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, - n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, - n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, - n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, - n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, - n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, - n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, - n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, - n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, - n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, - n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, - n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, - n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, - n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, - n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, - n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, - n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, - n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, - n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, - n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, - n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, - n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, - n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, - n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, - n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, - n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, - n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, - n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, - n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, - n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, - n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, - n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, - n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, - n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, - n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, - n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, - n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, - n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, - n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, - n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, - n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, - n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, - n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, - n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, - n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, - n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, - n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, - n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, - n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, - n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, - n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, - n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, - n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, - n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, - n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, - n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, - n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, - n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, - n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, - n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, - n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, - n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, - n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, - n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, - n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, - n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, - n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, - n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, - n2296, n2297, n2298; - assign o_0_ = ~n211; - assign o_1_ = ~n125; - assign o_2_ = n184 & ~n1084 & (~n984 | ~n1074); - assign o_3_ = ~n210; - assign o_4_ = ~n206; - assign o_5_ = ~n566; - assign o_6_ = ~n205; - assign o_7_ = ~n514; - assign o_8_ = i_3_ & ~i_0_ & ~i_1_; - assign o_9_ = ~n203; - assign o_10_ = ~n202; - assign o_11_ = ~n201; - assign o_12_ = ~n1064; - assign o_13_ = ~n200; - assign o_14_ = ~n1032; - assign o_15_ = ~n1024; - assign o_16_ = ~n195; - assign o_17_ = ~n1017; - assign o_18_ = ~n186; - assign o_19_ = n184 & i_5_ & i_3_ & ~i_4_ & ~n1074; - assign o_20_ = ~n1074 & n184 & n185; - assign o_21_ = n183 | n181 | n182; - assign o_22_ = ~n180; - assign o_23_ = ~n179; - assign o_24_ = n172 & ~n1083; - assign o_25_ = n172 & n173; - assign o_26_ = n163 | n167 | n171 | n158; - assign o_27_ = n162 | n168 | ~n174 | ~n2250; - assign o_28_ = n167 | n168 | n169 | n170; - assign o_29_ = n164 | n162 | n163 | ~n174 | n165 | n166; - assign o_30_ = n161 | n159 | n160 | n158 | ~n156 | n157; - assign o_31_ = n955 | n956 | ~n1605 | ~n2244; - assign o_32_ = ~n954; - assign o_33_ = ~n952; - assign o_34_ = ~n156; - assign o_35_ = ~n153; - assign o_36_ = ~n937; - assign o_37_ = ~n146; - assign o_38_ = ~n873; - assign o_39_ = ~n788; - assign o_40_ = ~n145; - assign o_41_ = n144 & n142 & n143; - assign o_42_ = ~n141; - assign o_43_ = ~n138; - assign o_44_ = ~n134; - assign o_45_ = ~n126; - assign n108 = ~n469 & (~n497 | ~n1574); - assign n109 = ~n349 & (~n484 | ~n1105); - assign n110 = n555 & n1101; - assign n111 = ~n781 | ~n1224; - assign n112 = n110 & (n111 | ~n463); - assign n113 = ~n796 & (~n845 | ~n849); - assign n114 = n218 | ~n268; - assign n115 = ~n405 & (n114 | ~n779); - assign n116 = ~n225 & (~n377 | ~n636); - assign n117 = n110 & (~n1105 | ~n1202); - assign n118 = ~n1458 | ~n1468; - assign n119 = ~n405 & (n118 | ~n1151 | ~n1231); - assign n120 = n385 | ~n945; - assign n121 = ~n796 & (n120 | ~n1005); - assign n122 = n1084 | ~n1515; - assign n123 = i_7_ | i_6_; - assign n124 = n122 | n123; - assign n125 = n983 & (~n144 | n984 | n985); - assign n126 = n517 & n669 & (n667 | n670); - assign n127 = n743 & n708 & n704 & n742 & n721 & n735 & n744 & n745; - assign n128 = n1649 & n1648 & n1647 & n1645 & n1644 & n409 & ~n701 & n1646; - assign n129 = n1655 & n1654 & n1653 & n1652 & n1650 & n1651 & n700; - assign n130 = n1643 & n749 & n1642 & n1641 & n336 & n1640; - assign n131 = n2160 & (n405 | (n1006 & n1547)); - assign n132 = n675 & n1677 & n698 & n1662 & n1669 & n1674 & n1684; - assign n133 = n2159 & n2158 & n2157 & n2156 & n2155 & n195 & ~n115 & ~n119; - assign n134 = n132 & n131 & n130 & n129 & n127 & n128 & n133 & ~n752; - assign n135 = n1699 & n1698 & n1697 & n1696 & ~n767 & ~n765 & ~n217 & n757; - assign n136 = ~n430 | n1115; - assign n137 = ~n430 | n1200; - assign n138 = n137 & n136 & n127 & n135; - assign n139 = n196 & n240 & (n241 | n242); - assign n140 = n197 & n480 & (n481 | n242); - assign n141 = n139 & n140; - assign n142 = ~i_11_ & ~i_9_ & ~i_10_; - assign n143 = ~i_8_ & n1119; - assign n144 = ~n1084 & n1700; - assign n145 = n768 & n519 & (n769 | n568); - assign n146 = n912 & n911 & n910 & n909 & n708 & n908 & n913 & n914; - assign n147 = ~n948 & (n456 | (n747 & n944)); - assign n148 = n2239 & (n943 | n755); - assign n149 = n2241 & n2242 & (n746 | n405); - assign n150 = n1359 & n1322 & n307 & n1488 & n367 & n420; - assign n151 = n1611 & n585 & n649 & n1779 & n807 & n1761; - assign n152 = n2238 & n2237 & n1909 & n1896 & n1857 & n1258 & ~n121 & ~n947; - assign n153 = ~n950 & n152 & n151 & n150 & n149 & n147 & n148 & ~n949; - assign n154 = n1080 & n1079 & n1078 & n1077 & n1075 & n1076 & n1081 & n1082; - assign n155 = n663 & n661; - assign n156 = n154 & n155; - assign n157 = ~n525 & ~n1787; - assign n158 = n963 | n964 | n965 | n966 | ~n2246 | n967 | n968; - assign n159 = n957 | n958 | n959 | n960 | ~n2247 | n961 | n962; - assign n160 = ~n516 & ~n525; - assign n161 = ~n525 & n1529; - assign n162 = n1521 | n1785 | n1786; - assign n163 = n1522 | n971 | n1783 | n1531; - assign n164 = ~n516 & ~n1214; - assign n165 = ~n1214 & n1529; - assign n166 = ~n1214 & ~n1787; - assign n167 = n1703 | n1784 | n1788 | n1789 | ~n124 | n978 | n1523 | n1532; - assign n168 = n972 | n973 | n974 | n975 | ~n2248 | n976 | n977; - assign n169 = ~n515 & n1529; - assign n170 = ~n515 & (~n516 | ~n1787); - assign n171 = ~n2249 & n185 & ~n1512; - assign n172 = ~n1512 & (n185 | n222); - assign n173 = ~i_6_ & i_7_; - assign n174 = n518 & (n969 | n970); - assign n175 = n774 & (n304 | n516); - assign n176 = n522 & (n516 | (n523 & n524)); - assign n177 = ~n1525 & ~n1534; - assign n178 = n122 & ~n958; - assign n179 = ~n1704 & ~n980 & ~n183 & n178 & n177 & n176 & n174 & n175; - assign n180 = n520 & n981 & (~n979 | n982); - assign n181 = ~n665 & n555 & n556; - assign n182 = ~n1117 & n556 & ~n665; - assign n183 = n1784 | n1783 | n966 | n974 | n1785 | n959; - assign n184 = ~n985 & n1700; - assign n185 = ~i_5_ & i_3_ & i_4_; - assign n186 = n1001 & n1000 & n999 & n998 & n875 & n997 & n1002 & n1003; - assign n187 = n684 | n1354; - assign n188 = n543 | n684; - assign n189 = ~n120 | n684; - assign n190 = n1262 | n684; - assign n191 = n684 | n1309; - assign n192 = n684 | n535; - assign n193 = n684 | n1340; - assign n194 = n686 & n1842 & n1305 & n1633 & n1621 & n908; - assign n195 = n192 & n191 & n190 & n189 & n187 & n188 & n193 & n194; - assign n196 = n1142 & n1140 & n1141; - assign n197 = n1476 & n1475 & n1474 & n479; - assign n198 = n603 & n602 & n600 & n601; - assign n199 = n590 & n1747 & n604; - assign n200 = n155 & n199 & n198 & n196 & n197; - assign n201 = n209 & ~n1704 & (n770 | n771); - assign n202 = n1071 & n1070 & n1069 & n1068 & n440 & n291 & n1072 & n1073; - assign n203 = n392 & n391 & n390 & n389 & n387 & n388 & n393 & n394; - assign n204 = n517 & n521 & n520 & n518 & n519; - assign n205 = n204 & n122 & n176; - assign n206 = ~n1536 & n177 & ~n1520; - assign n207 = n176 & (n770 | n771); - assign n208 = n122 & ~n1704; - assign n209 = n981 & n768 & n777 & n774; - assign n210 = n209 & n204 & n207 & n208; - assign n211 = ~n1515 & (~n144 | n985 | n1074); - assign n212 = n1099 & n1101; - assign n213 = n212 & (~n1118 | ~n1136); - assign n214 = ~n349 & (~n725 | ~n1634); - assign n215 = ~n469 & (~n1208 | ~n1224); - assign n216 = n1086 & n143; - assign n217 = ~n1261 & (n216 | ~n755); - assign n218 = ~n781 | ~n987; - assign n219 = ~n225 & (n218 | ~n570); - assign n220 = n1101 & n143; - assign n221 = n220 & (~n781 | ~n1127); - assign n222 = i_3_ & i_5_ & i_4_; - assign n223 = n225 | n1111; - assign n224 = n225 | n1110; - assign n225 = ~n555 | ~n1093; - assign n226 = n1090 | n1091; - assign n227 = n223 & n224 & (n225 | n226); - assign n228 = n1198 & n1204; - assign n229 = n1118 & n237; - assign n230 = n352 & n374; - assign n231 = n1088 | n1095; - assign n232 = n1095 | n1109; - assign n233 = n824 & n235; - assign n234 = n233 & n232 & n231 & n230 & n228 & n229; - assign n235 = n1109 | n1167; - assign n236 = n1109 | n1163; - assign n237 = n1090 | n1109; - assign n238 = n1103 | n1122; - assign n239 = n238 & n237 & n236 & n235 & n232; - assign n240 = n1747 & n2027 & (n2028 | n265); - assign n241 = i_11_ | ~i_9_ | ~i_10_; - assign n242 = n984 | ~n1138; - assign n243 = n1074 | ~n1086; - assign n244 = n1088 | n1104; - assign n245 = n1104 | n1109; - assign n246 = (n243 | n244) & (~n212 | n245); - assign n247 = n419 & n456; - assign n248 = ~n815 & ~n379 & n247 & ~n250; - assign n249 = ~n1154 & (~n728 | ~n987); - assign n250 = ~n349 | ~n796; - assign n251 = ~n988 & (n250 | ~n488 | ~n1166); - assign n252 = ~n249 & (n1164 | (n780 & n1129)); - assign n253 = ~n219 & (~n277 | (n1111 & n1151)); - assign n254 = ~n251 & n2040 & (n236 | n2012); - assign n255 = n1538 & n588 & n471 & n890 & n1771 & n921 & n639 & n635; - assign n256 = n2043 & n2044 & n2046 & n2045 & n658 & n246 & n2042 & n2041; - assign n257 = n1721 & n848 & n837 & n790 & n455 & n410 & n467 & n631; - assign n258 = n395 & n399 & n2039 & n627 & n641 & n462 & n1691 & n1690; - assign n259 = n719 & n1625 & n404 & n408 & n1641 & n415 & n2035 & n2038; - assign n260 = n257 & n256 & n255 & n254 & n252 & n253 & n258 & n259; - assign n261 = n1120 | ~n1138; - assign n262 = ~n142 | n261; - assign n263 = n478 | n261; - assign n264 = n1131 | n261; - assign n265 = i_11_ | i_9_ | ~i_10_; - assign n266 = n263 & n264 & (n265 | n261); - assign n267 = n225 | n1217; - assign n268 = n1226 & n1224 & n1225; - assign n269 = n1126 | n1196; - assign n270 = n267 & (n225 | (n268 & n269)); - assign n271 = n539 | ~n796; - assign n272 = ~n1210 & (n271 | ~n488); - assign n273 = n220 | ~n456; - assign n274 = n273 & (~n824 | ~n1204 | ~n1232); - assign n275 = ~n377 | ~n1307; - assign n276 = ~n1154 & (~n268 | n275 | ~n1213); - assign n277 = ~n243 | ~n405; - assign n278 = ~n226 | ~n1353; - assign n279 = n277 & (n278 | ~n1203 | ~n1231); - assign n280 = ~n243 | n818; - assign n281 = ~n488 | ~n349 | ~n456; - assign n282 = ~n1200 & (n271 | n280 | n281); - assign n283 = ~n274 & (n1197 | (n469 & n1157)); - assign n284 = ~n272 & (n2010 | (n643 & n1207)); - assign n285 = ~n276 & n2013 & (n1218 | n2014); - assign n286 = n889 & n1078 & n920 & n915 & n1768 & n2009 & n587 & n638; - assign n287 = n2020 & n2018 & n2017 & n2016 & ~n279 & ~n282; - assign n288 = n789 & n411 & n451 & n454 & n458 & n634 & n836 & n847; - assign n289 = n396 & n400 & n626 & n461 & n1722 & n630 & n1688 & n2008; - assign n290 = n2007 & n1591 & n1586 & n1626 & n407 & n403 & n2003 & n2006; - assign n291 = n288 & n287 & n286 & n285 & n283 & n284 & n289 & n290; - assign n292 = n236 | ~n421; - assign n293 = n456 | n1153; - assign n294 = n232 | ~n818; - assign n295 = n456 | n530; - assign n296 = n456 | n1149; - assign n297 = n236 | ~n925; - assign n298 = n1579 & n1566 & n577 & n1726 & n1618 & n591; - assign n299 = n1996 & n1995 & n1689 & n1630 & n1279 & n1267 & ~n217 & n655; - assign n300 = n1989 & n1705 & n1716 & n1694 & n718 & n1990 & n1986 & n1982; - assign n301 = n298 & n297 & n296 & n295 & n293 & n294 & n299 & n300; - assign n302 = n405 & n419; - assign n303 = n238 | n302; - assign n304 = n1089 | n1113; - assign n305 = n1089 | n1128; - assign n306 = n304 & n305; - assign n307 = n1306 & n303 & n1305 & n188 & n1303 & n1304; - assign n308 = n1302 & n1301 & n1300 & n1299 & n1297 & n1298; - assign n309 = n1294 & n1293 & n1292 & n1291 & n1289 & n1290 & n1295 & n1296; - assign n310 = n1287 & n1286 & n1285 & n1284 & n1282 & n1283 & n1288; - assign n311 = n1973 & n1974 & (~n216 | n238); - assign n312 = n1751 & n1686 & n1631 & n1559 & n1772 & n1749 & n1710 & n1972; - assign n313 = n1971 & n812 & n1752 & n1619 & n595 & n1583; - assign n314 = n1968 & n1657 & n1970 & n1969 & n1678 & n1596; - assign n315 = n312 & n311 & n310 & n309 & n307 & n308 & n313 & n314; - assign n316 = n1091 | n1167; - assign n317 = ~n220 | n316; - assign n318 = n456 | n316; - assign n319 = ~n818 | n824; - assign n320 = n456 | n484; - assign n321 = n456 | n1228; - assign n322 = ~n925 | n1227; - assign n323 = n1584 & n594 & n580 & n1565 & n1715; - assign n324 = n1330 & n1337 & n1953 & n1713 & n1767 & n1955 & n1954 & n1322; - assign n325 = n1950 & n786 & n785 & n1706 & n1951 & n1952 & n1949; - assign n326 = n323 & n322 & n321 & n320 & n318 & n319 & n324 & n325; - assign n327 = n1352 & n1351 & n1350 & n1349 & n1347 & n1348; - assign n328 = n1346 & n1345 & n1344 & n1343 & n1341 & n1342; - assign n329 = n1934 & (~n818 | n970); - assign n330 = (n419 | n726) & (~n216 | n1232); - assign n331 = n1933 & (n243 | n1045); - assign n332 = n1931 & n1632 & n1711 & n1628 & n1687 & n1932; - assign n333 = n596 & n1753 & n1545 & n811 & n1620 & n1616 & n582 & n1930; - assign n334 = n1928 & n1654 & n1672 & n1663 & n693 & n1656; - assign n335 = n332 & n331 & n330 & n329 & n327 & n328 & n333 & n334; - assign n336 = n243 | n1212; - assign n337 = n243 | n1097; - assign n338 = n1110 | n405; - assign n339 = n243 | n1225; - assign n340 = n243 | n1135; - assign n341 = n717 & n1595 & n1594 & n1610 & n1682 & n1681; - assign n342 = n1915 & n1575 & n579 & n1568 & n1567 & n1671 & n1651 & n1914; - assign n343 = n1359 & n1368 & n1919 & n1627 & n1922 & n1561 & n1921 & n1918; - assign n344 = n341 & n340 & n339 & n338 & n336 & n337 & n342 & n343; - assign n345 = n1088 | n1102; - assign n346 = n1102 | n1109; - assign n347 = ~n892 & n345 & n346; - assign n348 = n1214 & n780; - assign n349 = ~n555 | ~n1086; - assign n350 = (n348 | n349) & (n347 | ~n430); - assign n351 = n349 | n1127; - assign n352 = n1208 & n1127; - assign n353 = n643 & n1129; - assign n354 = n351 & (~n430 | (n352 & n353)); - assign n355 = ~n879 & n1136; - assign n356 = n355 | ~n421; - assign n357 = n225 | n1339; - assign n358 = n405 | n1340; - assign n359 = n349 | n1339; - assign n360 = n349 | n726; - assign n361 = n225 | n1232; - assign n362 = n469 | n1339; - assign n363 = n1161 | n1340; - assign n364 = n1846 & n1843 & n1845 & n1844 & n193 & n1697; - assign n365 = n362 & n361 & n360 & n359 & n357 & n358 & n363 & n364; - assign n366 = (~n385 | n419) & (n225 | n995); - assign n367 = n366 & n365; - assign n368 = ~n984 & n1101; - assign n369 = n368 & (~n1232 | ~n1340); - assign n370 = ~n110 | n780; - assign n371 = n2298 | n225; - assign n372 = ~n879 & n1215; - assign n373 = n370 & n371 & (~n110 | n372); - assign n374 = n345 & n346; - assign n375 = n1394 & ~n385 & n1280; - assign n376 = n375 & n374 & n231; - assign n377 = n515 & n1215; - assign n378 = n377 & ~n892; - assign n379 = ~n243 | n368; - assign n380 = n379 & (~n233 | ~n374); - assign n381 = n212 | n110; - assign n382 = ~n346 | ~n1281; - assign n383 = n381 & (n382 | n111); - assign n384 = n277 & (~n990 | ~n1133); - assign n385 = ~n1261 | ~n1308; - assign n386 = n368 & (n385 | ~n648); - assign n387 = (~n250 | ~n275) & (n243 | n1606); - assign n388 = (~n385 | n684) & (n302 | n652); - assign n389 = (n352 | n405) & (n355 | n796); - assign n390 = (n1152 | n738) & (n1781 | n1161); - assign n391 = n2069 & n2070 & n373 & n1076 & n418 & n367; - assign n392 = n291 & n260 & n335 & n326 & n301 & n315 & n227 & n2071; - assign n393 = n2058 & n2060 & n2062 & n2065 & n2067 & n2068 & n2056 & n2055; - assign n394 = n2054 & n2053 & n2051 & n2050 & n2049 & n2048 & ~n213 & n2047; - assign n395 = n225 | n1123; - assign n396 = n225 | n231; - assign n397 = n1089 | n1095; - assign n398 = n395 & n396 & (n225 | n397); - assign n399 = n225 | n1124; - assign n400 = n225 | n1204; - assign n401 = n1089 | n1090; - assign n402 = n399 & n400 & (n225 | n401); - assign n403 = n405 | n231; - assign n404 = n405 | n232; - assign n405 = ~n1086 | n1117; - assign n406 = n403 & n404 & (n405 | n397); - assign n407 = n405 | n1204; - assign n408 = n405 | n237; - assign n409 = n407 & n408 & (n405 | n401); - assign n410 = n225 | n1136; - assign n411 = n225 | n1198; - assign n412 = n1089 | n1106; - assign n413 = n410 & n411 & (n225 | n412); - assign n414 = n405 | n1198; - assign n415 = n405 | n1118; - assign n416 = n414 & n415 & (n405 | n412); - assign n417 = n349 | n1261; - assign n418 = n1406 & n190 & n1405 & n1019 & n1403 & n1404; - assign n419 = ~n1093 | n1117; - assign n420 = n417 & n418 & (n419 | n235); - assign n421 = ~n349 | n430; - assign n422 = ~n1136 & (n421 | ~n796); - assign n423 = n1431 & n1430 & n1429 & n1428 & n1426 & n1427 & n1432 & n1433; - assign n424 = n1377 & n2090 & (~n539 | n1124); - assign n425 = (~n815 | n1149) & (n243 | n1153); - assign n426 = (n2088 | n1261) & (n1461 | n346); - assign n427 = n2089 & (n235 | (~n539 & n1461)); - assign n428 = ~n422 & (n1127 | (~n421 & n1459)); - assign n429 = n426 & n425 & n424 & n420 & n301 & n423 & n427 & n428; - assign n430 = n1086 & n1099; - assign n431 = ~n1208 & (n430 | ~n1459); - assign n432 = n469 | n1307; - assign n433 = n469 | n1219; - assign n434 = ~n431 & (n824 | (n1461 & n1462)); - assign n435 = (~n546 | n1309) & (n231 | n2087); - assign n436 = n1517 | n1307; - assign n437 = (n1461 | n345) & (n1463 | n1219); - assign n438 = (n2088 | n1308) & (n2066 | n1228); - assign n439 = n326 & n1075 & (~n212 | n1224); - assign n440 = n437 & n436 & n435 & n434 & n432 & n433 & n438 & n439; - assign n441 = n368 & (~n636 | ~n1467); - assign n442 = n469 | n632; - assign n443 = n469 | n1465; - assign n444 = n469 | n628; - assign n445 = ~n110 | n632; - assign n446 = n2085 & (~n212 | (n463 & n632)); - assign n447 = (~n381 | n642) & (n684 | n1467); - assign n448 = n1473 & n1472 & n1471 & n1470 & ~n441 & n1469; - assign n449 = n2086 & (~n679 | n1481); - assign n450 = n447 & n446 & n445 & n444 & n442 & n443 & n448 & n449; - assign n451 = ~n220 | n231; - assign n452 = n397 & n232; - assign n453 = n451 & (~n220 | n452); - assign n454 = n456 | n1198; - assign n455 = n1118 | n456; - assign n456 = ~n1101 | n1120; - assign n457 = n454 & n455 & (n456 | n412); - assign n458 = ~n220 | n1198; - assign n459 = n412 & n1118; - assign n460 = n458 & (~n220 | n459); - assign n461 = n456 | n1208; - assign n462 = n456 | n1127; - assign n463 = n1089 | n1126; - assign n464 = n461 & n462 & (n456 | n463); - assign n465 = ~n233 | ~n482; - assign n466 = n220 & (n465 | ~n486); - assign n467 = n469 | n1123; - assign n468 = n469 | n231; - assign n469 = ~n1101 | n1114; - assign n470 = n467 & n468 & (n469 | n397); - assign n471 = n469 | n1136; - assign n472 = n469 | n1198; - assign n473 = n471 & n472 & (n469 | n412); - assign n474 = n2076 & (~n1053 | (n945 & n1048)); - assign n475 = ~n368 | n725; - assign n476 = n475 & n474 & n470 & n473; - assign n477 = ~n1099 | ~n1138; - assign n478 = ~i_11_ | i_9_ | i_10_; - assign n479 = n477 | n478; - assign n480 = n2075 & (n2028 | n478); - assign n481 = ~i_11_ | ~i_9_ | i_10_; - assign n482 = n1089 | n1167; - assign n483 = n482 | n349; - assign n484 = n1091 | n1102; - assign n485 = n1481 & n1480 & n589 & n1465 & n1467; - assign n486 = n1108 | n1167; - assign n487 = n486 & n485 & n484 & n226 & n316; - assign n488 = n225 & n302; - assign n489 = ~n421 & ~n818; - assign n490 = ~n1051 & n488 & n489; - assign n491 = n1090 | n1108; - assign n492 = n482 & n401 & n491 & n486; - assign n493 = ~n212 | n2293; - assign n494 = n493 & (~n212 | n491); - assign n495 = n1108 | n1126; - assign n496 = n1108 | n1163; - assign n497 = n1102 | n1108; - assign n498 = n497 & n495 & n496; - assign n499 = n381 & (~n346 | ~n495); - assign n500 = ~n796 & (~n397 | ~n530); - assign n501 = ~n419 | ~n850; - assign n502 = n501 & (~n1123 | ~n1136 | ~n1458); - assign n503 = n501 | ~n1154; - assign n504 = n503 & (~n530 | ~n1219 | ~n1307); - assign n505 = ~n488 & (~n463 | ~n482 | ~n781); - assign n506 = (n397 | n1460) & (~n277 | n1458); - assign n507 = (n1157 | n487) & (n1155 | n482); - assign n508 = (n1483 | n496) & (n1807 | n530); - assign n509 = (n2099 | n1479) & (n2011 | n725); - assign n510 = n2098 & n2097 & n2095 & ~n505 & ~n502 & ~n504; - assign n511 = n2093 & n2094 & n1708 & n896 & n1560 & n1540; - assign n512 = n1617 & n1624 & n1629 & n1647 & n844 & n1707 & n2091 & n1587; - assign n513 = n2104 & n2106 & n2108 & n2112 & n2110 & n2109 & n2114 & n2113; - assign n514 = n511 & n510 & n509 & n508 & n506 & n507 & n512 & n513; - assign n515 = n1106 | n1201; - assign n516 = ~n1099 | n1513; - assign n517 = ~n160 & ~n164 & (n515 | n516); - assign n518 = n970 | n516; - assign n519 = n1514 | n985; - assign n520 = n1514 | n665; - assign n521 = (n1514 | n776) & (n304 | n516); - assign n522 = ~n1119 | n1513; - assign n523 = n652 & n1230; - assign n524 = n1045 & n990; - assign n525 = n1089 | n1107; - assign n526 = n370 & (~n110 | n525); - assign n527 = ~n110 | n1215; - assign n528 = ~n382 & n1392; - assign n529 = n526 & n527 & (~n212 | n528); - assign n530 = n1104 | n1108; - assign n531 = ~n117 & (~n110 | (~n382 & n530)); - assign n532 = n1088 | n1107; - assign n533 = ~n213 & n531 & (~n212 | n532); - assign n534 = n1448 & n1447 & n1446 & n1445 & n1443 & n1444 & n1449 & n1450; - assign n535 = n1103 | n1206; - assign n536 = n534 & (~n368 | n535); - assign n537 = ~n1202 & (~n225 | n430); - assign n538 = ~n532 & (n110 | ~n1517); - assign n539 = ~n984 & n1093; - assign n540 = ~n1110 & (n421 | n539); - assign n541 = ~n1354 & (~n225 | ~n1161); - assign n542 = n1455 & n1454 & n800 & n1453 & n1451 & n1452 & n1456 & n1457; - assign n543 = n1089 | n1122; - assign n544 = n542 & (~n368 | n543); - assign n545 = ~n220 & n302; - assign n546 = ~n225 | n273; - assign n547 = ~n543 & (n546 | ~n1161); - assign n548 = (~n430 | n1129) & (n349 | n780); - assign n549 = (n405 | n990) & (~n220 | n1121); - assign n550 = (n304 | ~n815) & (~n421 | n1111); - assign n551 = (n545 | n1133) & (n1463 | n1046); - assign n552 = ~n547 & (n525 | (~n212 & n1517)); - assign n553 = n2115 & n1388 & n223; - assign n554 = n551 & n550 & n549 & n548 & n544 & n315 & n552 & n553; - assign n555 = i_8_ & ~n1083; - assign n556 = n1092 & ~n1512; - assign n557 = ~n776 & n555 & n556; - assign n558 = n1099 & n556; - assign n559 = n558 & ~n667; - assign n560 = n260 & n429 & (n796 | n235); - assign n561 = n554 & n1528 & n529 & n533; - assign n562 = (~n430 | n530) & (~n539 | n1111); - assign n563 = (~n110 | n781) & (n1225 | n2107); - assign n564 = n2133 & n2134 & (n2010 | n1121); - assign n565 = n2130 & n2120 & n2121 & n2124 & n2123 & n2131 & n2129 & n2128; - assign n566 = ~n1525 & n565 & n564 & n563 & n562 & n560 & n561 & ~n1520; - assign n567 = ~n1117 & n556 & ~n776; - assign n568 = n1074 | ~n1602; - assign n569 = n568 & (~n1099 | ~n1602); - assign n570 = n1109 | n1128; - assign n571 = n495 & n570; - assign n572 = n1087 | n1201; - assign n573 = (n469 | n572) & (~n368 | n571); - assign n574 = ~n368 | n1153; - assign n575 = n1578 & n1577 & n444 & n1575 & n1576; - assign n576 = n574 & n575 & (~n368 | ~n465); - assign n577 = n469 | n1153; - assign n578 = n469 | n824; - assign n579 = n469 | n1134; - assign n580 = n469 | n316; - assign n581 = n469 | n1133; - assign n582 = n469 | n726; - assign n583 = n469 | n727; - assign n584 = n443 & (n469 | n482); - assign n585 = n582 & n581 & n580 & n579 & n577 & n578 & n583 & n584; - assign n586 = ~n368 | n397; - assign n587 = ~n220 | n1200; - assign n588 = ~n220 | n1115; - assign n589 = n1106 | n1108; - assign n590 = n587 & n588 & (~n220 | n589); - assign n591 = n469 | n1124; - assign n592 = n469 | n1204; - assign n593 = n1110 | n469; - assign n594 = n226 | n469; - assign n595 = n1111 | n469; - assign n596 = n469 | n1338; - assign n597 = n469 | n1353; - assign n598 = n442 & (n469 | n401); - assign n599 = n596 & n595 & n594 & n593 & n591 & n592 & n597 & n598; - assign n600 = n456 | n245; - assign n601 = n456 | n613; - assign n602 = n456 | n1216; - assign n603 = (~n220 | n1574) & (~n273 | n747); - assign n604 = ~n220 | n613; - assign n605 = n1132 | n1201; - assign n606 = n604 & (n605 | ~n1053); - assign n607 = n615 & n412 & ~n385 & n401; - assign n608 = n486 & n1573; - assign n609 = n608 & n607 & n374; - assign n610 = n1128 | n1201; - assign n611 = n269 & n610; - assign n612 = (n469 | n495) & (~n368 | n611); - assign n613 = n1107 | n1201; - assign n614 = n613 | n469; - assign n615 = n1096 | n1201; - assign n616 = ~n220 | n615; - assign n617 = ~n220 | n605; - assign n618 = n2291 | n456; - assign n619 = n1932 & n1922 & n1955; - assign n620 = n756 & n1391; - assign n621 = n618 & n619 & (~n220 | n620); - assign n622 = n1209 & n632 & n1130; - assign n623 = n456 | n622; - assign n624 = n1466 & n737; - assign n625 = n456 | n624; - assign n626 = ~n220 | n1207; - assign n627 = ~n220 | n1125; - assign n628 = n1091 | n1096; - assign n629 = n626 & n627 & (~n220 | n628); - assign n630 = ~n220 | n1209; - assign n631 = ~n220 | n1130; - assign n632 = n1087 | n1091; - assign n633 = n630 & n631 & (~n220 | n632); - assign n634 = n456 | n1214; - assign n635 = n456 | n780; - assign n636 = n1091 | n1107; - assign n637 = n634 & n635 & (n456 | n636); - assign n638 = ~n220 | n1214; - assign n639 = ~n220 | n780; - assign n640 = n638 & n639 & (~n220 | n636); - assign n641 = n456 | n1129; - assign n642 = n1091 | n1128; - assign n643 = n1128 | n1196; - assign n644 = n641 & (n456 | (n642 & n643)); - assign n645 = n1339 & n1465 & n1280; - assign n646 = n456 | n645; - assign n647 = n1545 & n1544 & n1543 & n293 & n1542 & n318 & n646; - assign n648 = n535 & n543 & n1309; - assign n649 = n647 & (n648 | n456); - assign n650 = n1005 & n992 & n1006 & n1548 & n792; - assign n651 = n491 & n1546; - assign n652 = n1104 | n1196; - assign n653 = n1133 & n1134; - assign n654 = n653 & n652 & n651 & n650 & ~n385 & n610; - assign n655 = n1273 & n1272 & n1271 & n1270 & n1269 & n1268 & ~n221 & n828; - assign n656 = n1223 & n1241 & n1240 & n1238 & n1239; - assign n657 = (n456 | n1547) & (~n220 | n654); - assign n658 = n1148 & n1175 & n827 & n1173 & n1174; - assign n659 = n2146 & n1764 & n2145 & n1844 & n1405 & n2144; - assign n660 = n2147 & n621 & n1572 & n1570 & n1563 & n1557; - assign n661 = n659 & n658 & n657 & n309 & n655 & n656 & n660; - assign n662 = n993 | n456; - assign n663 = n662 & (~n220 | n572); - assign n664 = n1115 & n589; - assign n665 = n1104 | n1201; - assign n666 = (n469 | n665) & (~n368 | n664); - assign n667 = n1214 & n525 & n515; - assign n668 = ~n558 | n667; - assign n669 = n1605 & ~n1535 & n668 & n663 & n154 & n661; - assign n670 = n771 & n1604; - assign n671 = n405 | n1143; - assign n672 = n405 | n615; - assign n673 = n405 | n1217; - assign n674 = (~n277 | n939) & (n243 | n1573); - assign n675 = n674 & n673 & n671 & n672; - assign n676 = ~n405 & (~n645 | ~n1133 | ~n1210); - assign n677 = ~n243 & (~n233 | ~n1607); - assign n678 = ~n277 | n482; - assign n679 = ~n984 & n1086; - assign n680 = n679 & (~n1228 | ~n1613 | ~n2148); - assign n681 = n679 & (~n874 | ~n1466); - assign n682 = ~n1224 | ~n610 | ~n987; - assign n683 = n679 & (n682 | ~n1537 | ~n1614); - assign n684 = ~n1086 | n1114; - assign n685 = n1467 & n944; - assign n686 = n684 | n685; - assign n687 = ~n243 & (~n688 | ~n1115); - assign n688 = n613 & n1200; - assign n689 = n405 | n688; - assign n690 = n243 | n1204; - assign n691 = n237 | n243; - assign n692 = n243 | n1124; - assign n693 = n243 | n1338; - assign n694 = n1110 | n243; - assign n695 = n243 | n1205; - assign n696 = n1116 | n243; - assign n697 = n2154 & (n1111 | n243); - assign n698 = n695 & n694 & n693 & n692 & n690 & n691 & n696 & n697; - assign n699 = n1089 | n1102; - assign n700 = n699 | n405; - assign n701 = ~n405 & (n278 | ~n1111); - assign n702 = n231 | ~n430; - assign n703 = n845 & n397 & n628; - assign n704 = n702 & (~n430 | n703); - assign n705 = n349 | n1216; - assign n706 = n349 | n245; - assign n707 = (~n430 | n1007) & (~n421 | n747); - assign n708 = n707 & n705 & n706; - assign n709 = n143 & n1138; - assign n710 = n709 & (~n241 | ~n481 | ~n1112); - assign n711 = n636 & n632; - assign n712 = ~n421 | n711; - assign n713 = n349 | n1124; - assign n714 = n349 | n1204; - assign n715 = n2290 | n349; - assign n716 = n349 | n1338; - assign n717 = n349 | n1353; - assign n718 = n349 | n237; - assign n719 = n349 | n1116; - assign n720 = n2005 & (n349 | (n401 & n491)); - assign n721 = n718 & n717 & n716 & n715 & n713 & n714 & n719 & n720; - assign n722 = n653 & n316 & n1465; - assign n723 = n1207 & n1125; - assign n724 = n482 & n723 & n703 & n722; - assign n725 = n1095 | n1108; - assign n726 = n1167 | n1201; - assign n727 = n1103 | n1167; - assign n728 = n1153 & n653; - assign n729 = n728 & n727 & n725 & n645 & n316 & ~n465 & n726; - assign n730 = n349 | n1280; - assign n731 = n232 | ~n430; - assign n732 = (~n430 | n729) & (n349 | n724); - assign n733 = ~n421 | n809; - assign n734 = n1316 & n1948 & n1849 & n360 & n1357 & n1850; - assign n735 = n734 & n733 & n732 & n731 & n359 & n730; - assign n736 = n572 & n491; - assign n737 = n652 & n1281; - assign n738 = n530 & n1105; - assign n739 = n738 & n737 & n736 & n613 & n610 & n401 & ~n114 & ~n385; - assign n740 = n1199 & n994; - assign n741 = ~n918 & n740 & n650 & ~n275 & n412; - assign n742 = n1637 & n1636 & ~n710 & n712; - assign n743 = n1337 & n1279 & n308 & n1416 & n1035 & n1368; - assign n744 = n2152 & n2153 & (n349 | n610); - assign n745 = n2151 & n2150 & n2149 & n2037 & ~n214 & n2004; - assign n746 = n1574 & n990 & n1203; - assign n747 = n665 & n497; - assign n748 = n610 & n589 & n746 & n747; - assign n749 = n397 | n243; - assign n750 = ~n650 | ~n353 | ~n374; - assign n751 = ~n1458 | ~n1045 | ~n1231; - assign n752 = ~n243 & (n750 | n751 | ~n986); - assign n753 = n755 | n970; - assign n754 = n755 | n1121; - assign n755 = ~n1086 | n1120; - assign n756 = n1091 | n1113; - assign n757 = n753 & n754 & (n755 | n756); - assign n758 = n1468 & n1227; - assign n759 = n755 | n758; - assign n760 = n216 & (~n756 | ~n1231 | ~n1685); - assign n761 = n496 & n740; - assign n762 = n755 | n761; - assign n763 = n216 | ~n755; - assign n764 = ~n945 | ~n1467; - assign n765 = n763 & (n764 | ~n1308); - assign n766 = ~n238 | ~n1232; - assign n767 = n216 & (n766 | ~n944); - assign n768 = n985 | n775; - assign n769 = n770 & n1701; - assign n770 = n970 & n667; - assign n771 = n1074 | n1513; - assign n772 = ~n173 | n1513; - assign n773 = n304 & n523; - assign n774 = n772 & (n771 | (n773 & n524)); - assign n775 = n1117 | n1513; - assign n776 = n1113 | n1201; - assign n777 = n775 | n776; - assign n778 = n1215 & n1224; - assign n779 = n463 & n352; - assign n780 = n1103 | n1107; - assign n781 = n1108 | n1128; - assign n782 = n525 & n780 & n491 & n245 & n778 & n779 & n781 & n632; - assign n783 = n1708 & n1707 & n445 & n1705 & n1706; - assign n784 = n1172 & n1267 & (~n110 | n532); - assign n785 = ~n212 | n1204; - assign n786 = ~n110 | n1208; - assign n787 = n493 & n2161 & (~n212 | n782); - assign n788 = n787 & n786 & n785 & n784 & n783 & n533 & ~n112 & n529; - assign n789 = n268 | n419; - assign n790 = ~n218 | n419; - assign n791 = n789 & n790 & (n779 | n419); - assign n792 = n642 & n463; - assign n793 = n225 | n792; - assign n794 = n645 | n796; - assign n795 = n1133 & n1606; - assign n796 = ~n1093 | n1114; - assign n797 = n794 & (n795 | n796); - assign n798 = n605 | n469; - assign n799 = n469 | n643; - assign n800 = n469 | n1129; - assign n801 = ~n215 & (~n110 | n1614); - assign n802 = n2183 & (n456 | n495); - assign n803 = n2184 & n1485 & n644 & n791 & n1714 & n909; - assign n804 = n2182 & n2158 & n2000 & n1875 & n1471 & n1325 & ~n115 & n1292; - assign n805 = n877 & n2021 & n2074 & n2025 & n1792 & n1247 & n1249 & n2181; - assign n806 = n1963 & n1943 & n2136 & n1942 & n1366 & n1980 & n1367 & n2180; - assign n807 = n804 & n803 & n802 & n801 & n799 & n800 & n805 & n806; - assign n808 = n539 & (n465 | ~n1607); - assign n809 = n605 & n608; - assign n810 = (n615 | n796) & (~n271 | n809); - assign n811 = n225 | n1207; - assign n812 = n225 | n1125; - assign n813 = n628 & n1213; - assign n814 = n811 & n812 & (n813 | n225); - assign n815 = ~n225 | n818; - assign n816 = n815 & (~n482 | ~n486); - assign n817 = ~n225 & (~n1401 | ~n1465); - assign n818 = n1093 & n1099; - assign n819 = ~n645 | ~n1573; - assign n820 = n818 & (~n605 | ~n728 | n819); - assign n821 = ~n850 & (n465 | ~n645); - assign n822 = ~n419 & (n465 | ~n615); - assign n823 = ~n501 | n809; - assign n824 = n1088 | n1167; - assign n825 = n482 & n235 & n824 & n653 & n486 & n316; - assign n826 = ~n605 & (~n225 | n368); - assign n827 = ~n220 | n1143; - assign n828 = ~n220 | n1123; - assign n829 = n1634 | n469; - assign n830 = n456 | ~n465; - assign n831 = ~n826 & (n1217 | (~n368 & n469)); - assign n832 = n1240 & (~n1053 | (n486 & n1143)); - assign n833 = n1147 & n1764 & n1975 & n1872 & n2142 & n1347 & n1146 & n1145; - assign n834 = n1736 & n810 & n1677 & n675 & n1000 & n1723 & n1738 & n2179; - assign n835 = n832 & n831 & n830 & n829 & n827 & n828 & n833 & n834; - assign n836 = n1395 | n419; - assign n837 = n1396 | n419; - assign n838 = n836 & n837 & (n622 | n419); - assign n839 = ~n1338 | ~n1353; - assign n840 = ~n225 & (~n632 | ~n651 | n839); - assign n841 = ~n539 | n622; - assign n842 = n1395 & n1396; - assign n843 = n841 & (~n539 | n842); - assign n844 = ~n539 | n849; - assign n845 = n1635 & n1123 & n1213; - assign n846 = n844 & (~n539 | n845); - assign n847 = n2295 | n850; - assign n848 = n2294 | n850; - assign n849 = n231 & n452; - assign n850 = n1074 | ~n1093; - assign n851 = n847 & n848 & (n849 | n850); - assign n852 = n629 & n2167 & (n243 | n1197); - assign n853 = n1881 & n1803 & n2165 & n1835 & n1900 & n2081 & n1802 & n2164; - assign n854 = n1795 & n2163 & n1284 & n1344 & n1834 & n1891 & n1010 & n1793; - assign n855 = n2034 & n2007 & n1961 & n1409 & n1636 & n2151 & n2162 & n1873; - assign n856 = n853 & n852 & n704 & n130 & n846 & n851 & n854 & n855; - assign n857 = (n736 | n1398) & (n243 | ~n278); - assign n858 = (n2171 | n401) & (n2172 | n481); - assign n859 = (~n539 | n1025) & (n1168 | n1546); - assign n860 = n2080 & (n632 | (~n212 & n1152)); - assign n861 = n2173 & n494 & n633 & n843 & n856 & n698; - assign n862 = n1860 & n1446 & n1508 & n1820 & n1452 & n1445 & n1837 & n2170; - assign n863 = n1906 & n1839 & n1289 & n1323 & n1351 & n1435 & n1493 & n2169; - assign n864 = n2004 & n1474 & n1411 & n1301 & n2037 & n1853 & n1266 & n2168; - assign n865 = n862 & n861 & n860 & n859 & n857 & n858 & n863 & n864; - assign n866 = ~n1154 & (~n268 | ~n987); - assign n867 = n212 & (n111 | ~n779 | ~n1614); - assign n868 = n2191 & (~n368 | n463); - assign n869 = n865 & n1621 & n1662 & n807 & n835 & n1746; - assign n870 = n2188 & n2190 & (n1769 | n938); - assign n871 = n2001 & n1911 & n1897 & n1858 & ~n221 & ~n866; - assign n872 = n1310 & n1791 & n1863 & n1346 & n1282 & n1430 & n2185 & n2187; - assign n873 = n870 & n869 & n868 & n573 & n612 & n354 & n871 & n872; - assign n874 = n1574 & n747; - assign n875 = (n225 | n613) & (~n815 | n874); - assign n876 = ~n539 | n2297; - assign n877 = n2166 | n796; - assign n878 = n876 & n877 & (~n275 | ~n539); - assign n879 = ~n525 | ~n532; - assign n880 = n818 & (n275 | ~n636 | n879); - assign n881 = (~n212 | n780) & (~n368 | n636); - assign n882 = (n589 | ~n1051) & (~n430 | n2211); - assign n883 = (n2171 | n412) & (n2172 | n241); - assign n884 = n1674 & n398 & n640 & n878 & n1001 & n199; - assign n885 = n1799 & n1188 & n2210 & n1078 & n1869 & n1314 & n1257 & n2208; - assign n886 = n1181 & n1183 & n1171 & n1862 & n1498 & n1712 & n1426 & n2207; - assign n887 = n1941 & n1960 & n1825 & n1899 & n1274 & n1833 & n1854 & n2205; - assign n888 = n885 & n884 & n883 & n882 & n881 & n460 & n886 & n887; - assign n889 = n419 | ~n892; - assign n890 = n738 | n419; - assign n891 = n889 & n890 & (n624 | n419); - assign n892 = ~n1045 | ~n1203; - assign n893 = ~n225 & (n892 | ~n1548); - assign n894 = n1114 | ~n1138; - assign n895 = n261 & n894; - assign n896 = n2296 | n796; - assign n897 = ~n275 & n355; - assign n898 = n896 & (n897 | n796); - assign n899 = n2297 | n419; - assign n900 = ~n275 | n419; - assign n901 = n419 | n613; - assign n902 = n2196 & n1011 & (n993 | n225); - assign n903 = n1263 & n1907 & n1841 & n2031 & n1489 & n1264; - assign n904 = n898 & n1386 & n2197 & n473 & n457 & n373 & n1669 & n2198; - assign n905 = n662 & n1882 & n1926 & n2083 & n1840 & n1444 & n2195 & n2194; - assign n906 = n904 & n903 & n902 & n901 & n899 & n900 & n905; - assign n907 = ~n243 & (~n530 | ~n1045); - assign n908 = n1626 & n1625 & n1624 & n1623 & ~n681 & n1622; - assign n909 = n1709 & n264 & n798 & n797; - assign n910 = n246 & n350 & n198 & n666; - assign n911 = n906 & n856 & n835 & n875 & n888 & n1761; - assign n912 = n2222 & n2217 & n2218 & n2219 & n2220 & n2221 & n2216 & n2215; - assign n913 = n1326 & n1912 & n1191 & n1254 & n1293 & n1876 & n1379 & n2214; - assign n914 = n1429 & n1311 & n1496 & n2022 & n2213 & n1250 & n267 & n2212; - assign n915 = n1231 | n850; - assign n916 = n2291 | n419; - assign n917 = n915 & n916 & (n620 | n850); - assign n918 = ~n756 | ~n1468; - assign n919 = ~n225 & (n918 | ~n1151); - assign n920 = n1231 | n419; - assign n921 = n1151 | n419; - assign n922 = n920 & n921 & (~n118 | n419); - assign n923 = ~n225 & (~n776 | ~n994); - assign n924 = ~n349 & (~n2223 | ~n2224); - assign n925 = n1093 & n143; - assign n926 = n925 & (~n1231 | ~n1468 | ~n1613); - assign n927 = n236 & n756 & n589 & n725; - assign n928 = ~n496 & (n368 | ~n1769); - assign n929 = (n1156 | n1612) & (n1152 | n1468); - assign n930 = n1231 | n243; - assign n931 = (~n118 | n1460) & (~n368 | n664); - assign n932 = (~n280 | n1638) & (~n430 | n927); - assign n933 = n2079 & n1910 & n1378 & n1241 & n1233 & ~n928 & n1189; - assign n934 = n1022 & n1779 & n1692 & n1719 & n888 & n865 & n917 & n2234; - assign n935 = n1877 & n1291 & n1870 & n1312 & n1271 & n1507 & n1175 & n2232; - assign n936 = n1335 & n1361 & n1334 & n1276 & n1299 & n1360 & n1851 & n2230; - assign n937 = n934 & n933 & n932 & n931 & n929 & n930 & n935 & n936; - assign n938 = n610 & n495; - assign n939 = n605 & n486; - assign n940 = n496 & n944; - assign n941 = n940 & n939 & n938 & ~n764 & n482 & n747; - assign n942 = n985 & n1479; - assign n943 = n942 & ~n764 & ~n385 & n761; - assign n944 = n942 & n1144 & n1218; - assign n945 = n1089 | n1206; - assign n946 = n945 & n495 & n944 & n665; - assign n947 = n250 & (~n809 | ~n1780); - assign n948 = ~n419 & (~n824 | ~n1573); - assign n949 = ~n349 & (~n650 | ~n722 | ~n1127); - assign n950 = ~n225 & (~n1210 | ~n1465 | ~n1574); - assign n951 = n518 & (n769 | n1603); - assign n952 = n951 & n208 & n207 & n175 & ~n183 & n517; - assign n953 = ~n958 & n2243 & (n569 | n769); - assign n954 = n953 & n669 & n177; - assign n955 = n1119 & n556; - assign n956 = n173 & n556; - assign n957 = n1119 & n1530; - assign n958 = n1119 & n1518; - assign n959 = ~n304 & n1782; - assign n960 = n1119 & n1702; - assign n961 = ~n304 & n558; - assign n962 = ~n304 & n1529; - assign n963 = ~n990 & n1529; - assign n964 = ~n1083 & n1530; - assign n965 = ~n1083 & n1518; - assign n966 = ~n990 & n1782; - assign n967 = n558 & ~n990; - assign n968 = ~n1083 & n1702; - assign n969 = n670 & ~n979; - assign n970 = n1113 | n1196; - assign n971 = ~n652 & ~n2245; - assign n972 = n173 & n1530; - assign n973 = n173 & n1518; - assign n974 = ~n1230 & n1782; - assign n975 = n173 & n1702; - assign n976 = n558 & ~n1230; - assign n977 = ~n1230 & n1529; - assign n978 = ~n1045 & ~n2245; - assign n979 = n143 & n1602; - assign n980 = ~n1701 & (n979 | ~n1604); - assign n981 = n665 | n775; - assign n982 = n970 & n1701; - assign n983 = n2288 & (i_0_ | ~i_2_); - assign n984 = i_8_ | ~n173; - assign n985 = n1122 | n1201; - assign n986 = n1639 & n1638 & n736 & n607 & n740 & n737; - assign n987 = n305 & n1135; - assign n988 = n1096 | n1109; - assign n989 = n632 & n1338; - assign n990 = n1089 | n1104; - assign n991 = n988 & n613 & n987 & n268 & n986 & n650 & n989 & n990; - assign n992 = n776 & n1547; - assign n993 = n1200 & n664; - assign n994 = n1109 | n1113; - assign n995 = n648 & n1354 & n1340; - assign n996 = n995 & n993 & n992 & n605 & ~n764 & n994; - assign n997 = n1754 & n1753 & n1752 & n1751 & ~n893 & n1750; - assign n998 = n1768 & ~n919 & n1767; - assign n999 = n1739 & ~n840 & n227 & n402; - assign n1000 = n1727 & n1356 & n1726 & n1725 & n319 & n1724 & n1728 & n1729; - assign n1001 = n1749 & n1748 & ~n880 & n1484; - assign n1002 = n328 & n310 & n1315 & n1714 & n413 & n423; - assign n1003 = n2253 & n2252 & n2251 & n2163 & n2039 & n1237 & ~n116 & n371; - assign n1004 = ~n539 | n572; - assign n1005 = n1262 & n995; - assign n1006 = n1537 & n945 & ~n1027; - assign n1007 = n589 & n1574; - assign n1008 = n1007 & n1006 & n1005 & n688 & n651 & ~n114 & ~n385; - assign n1009 = n620 | n796; - assign n1010 = ~n539 | n2166; - assign n1011 = n993 | n796; - assign n1012 = ~n121 & (~n271 | (n992 & n1780)); - assign n1013 = n1501 & n1500 & n1499 & n1498 & n1496 & n1497 & n1502 & n1503; - assign n1014 = n1251 & n1250 & n1249 & n1248 & n1246 & n1247 & n1252 & n1253; - assign n1015 = n1187 & (~n539 | n1008); - assign n1016 = n1738 & n846 & n843 & n878 & n1798 & n898 & n810 & n797; - assign n1017 = n1014 & n1013 & n1012 & n1011 & n1009 & n1010 & n1015 & n1016; - assign n1018 = n1161 | n1308; - assign n1019 = n1261 | n1161; - assign n1020 = n1161 | n1309; - assign n1021 = n1161 | n535; - assign n1022 = n1772 & n1771 & n1770 & ~n926 & n297 & n322; - assign n1023 = n1845 & n1303 & (n2240 | n1161); - assign n1024 = n1022 & n1021 & n363 & n1020 & n1018 & n1019 & n135 & n1023; - assign n1025 = n572 & n651; - assign n1026 = n1025 & n1007 & ~n750 & n737 & n613 & ~n118 & n352; - assign n1027 = n766 | ~n1467; - assign n1028 = ~n419 & (~n945 | ~n992 | n1027); - assign n1029 = n1802 & n1801 & n899 & n1800 & n1799 & n901 & n1803 & n1804; - assign n1030 = n1723 & n791 & n1495; - assign n1031 = n1260 & n2226 & n2196 & n1709 & n2165 & n1731 & n1195 & n2255; - assign n1032 = n838 & n851 & n891 & n922 & n1029 & n917 & n1030 & n1031; - assign n1033 = n796 & n243; - assign n1034 = ~n456 & (~n1209 | ~n1339); - assign n1035 = n1412 & n1411 & n1410 & n1409 & n1407 & n1408 & n1413 & n1414; - assign n1036 = n1383 & n1382 & n1381 & n1380 & n1379 & n1378 & ~n369 & n799; - assign n1037 = n365 & (~n539 | n1338); - assign n1038 = (~n430 | n643) & (n349 | n1214); - assign n1039 = (n1033 | n726) & (n1463 | n1044); - assign n1040 = ~n1034 & (n225 | (n1045 & n1340)); - assign n1041 = n2256 & (~n220 | n970); - assign n1042 = n1039 & n1038 & n1037 & n335 & n1035 & n1036 & n1040 & n1041; - assign n1043 = ~n1053 & ~n815 & ~n421 & ~n220 & n243; - assign n1044 = n515 & n1211; - assign n1045 = n1102 | n1201; - assign n1046 = n1089 | n1096; - assign n1047 = n1046 & n525 & n1044 & n1045; - assign n1048 = n699 & n1468 & n463; - assign n1049 = n776 & n610 & n1048 & n665; - assign n1050 = ~n2107 & (~n305 | ~n1226); - assign n1051 = ~n243 | ~n850; - assign n1052 = n1051 & (~n353 | ~n1391); - assign n1053 = n368 | ~n469; - assign n1054 = ~n572 & (n1053 | ~n1398); - assign n1055 = ~n1281 & (~n243 | n381 | n501); - assign n1056 = ~n1054 & (n613 | (~n277 & n1166)); - assign n1057 = ~n1052 & (n1159 | (n482 & n1805)); - assign n1058 = n1670 & n2257 & (n2096 | n1049); - assign n1059 = n2258 & n2259 & n2261 & n2260; - assign n1060 = n2154 & n876 & n1571 & n1079 & n1655 & n1665 & n2158 & n1646; - assign n1061 = n1645 & n2150 & n794 & n841 & n1642 & n1739 & n1222 & n1147; - assign n1062 = n1798 & n1029 & n1552 & n606 & n1766 & n742 & n1042 & n2273; - assign n1063 = n2264 & n2265 & n2266 & n2267 & n2269 & n2268 & n2263 & n2262; - assign n1064 = n1061 & n1060 & n1059 & n1058 & n1056 & n1057 & n1062 & n1063; - assign n1065 = ~n532 & (n212 | n503); - assign n1066 = ~n226 & (~n225 | ~n349 | ~n1154); - assign n1067 = n539 & (~n231 | ~n726 | ~n1353); - assign n1068 = n2287 & (n796 | n824); - assign n1069 = ~n1536 & ~n1534 & n1042 & n1528; - assign n1070 = (n1154 | n1219) & (n1164 | n1209); - assign n1071 = n2286 & (~n273 | n1227); - assign n1072 = n2284 & n2285 & (n2010 | n970); - assign n1073 = n2278 & n2279 & n2280 & n2281 & n2283 & n2282 & n2276 & n2275; - assign n1074 = i_8_ | n123; - assign n1075 = n1425 & n1464; - assign n1076 = n1389 & n1386 & n1036 & n1402 & n1377; - assign n1077 = n2140 & (~n368 | (n572 & n874)); - assign n1078 = ~n368 | n1200; - assign n1079 = ~n368 | n613; - assign n1080 = (~n368 | n609) & (n940 | ~n1053); - assign n1081 = n2139 & n2138 & n2137 & n2136 & n2135 & n2034 & ~n108 & n2007; - assign n1082 = n1601 & n576 & n1592 & n198 & n590 & n599 & n573 & n2141; - assign n1083 = ~i_6_ | i_7_; - assign n1084 = ~i_5_ | i_3_ | i_4_; - assign n1085 = ~i_2_ & ~i_0_ & ~i_1_; - assign n1086 = ~n1084 & n1085; - assign n1087 = i_15_ | n481; - assign n1088 = ~i_14_ | i_12_ | ~i_13_; - assign n1089 = ~i_14_ | i_12_ | i_13_; - assign n1090 = ~i_15_ | n481; - assign n1091 = i_14_ | ~i_12_ | ~i_13_; - assign n1092 = ~i_5_ & ~i_3_ & i_4_; - assign n1093 = n1085 & n1092; - assign n1094 = ~i_11_ | ~i_9_ | ~i_10_; - assign n1095 = ~i_15_ | n1094; - assign n1096 = i_15_ | n1094; - assign n1097 = n1088 | n1096; - assign n1098 = n1046 & n1097; - assign n1099 = ~i_8_ & ~n1083; - assign n1100 = i_5_ & ~i_3_ & i_4_; - assign n1101 = n1085 & n1100; - assign n1102 = ~i_15_ | n265; - assign n1103 = i_14_ | ~i_12_ | i_13_; - assign n1104 = i_15_ | n265; - assign n1105 = n990 & n244; - assign n1106 = ~i_15_ | n241; - assign n1107 = i_15_ | n241; - assign n1108 = ~i_14_ | ~i_12_ | ~i_13_; - assign n1109 = ~i_14_ | ~i_12_ | i_13_; - assign n1110 = n1087 | n1088; - assign n1111 = n1087 | n1089; - assign n1112 = i_11_ | ~i_9_ | i_10_; - assign n1113 = i_15_ | n1112; - assign n1114 = ~i_8_ | ~n173; - assign n1115 = n1107 | n1109; - assign n1116 = n1087 | n1109; - assign n1117 = ~i_8_ | n123; - assign n1118 = n1106 | n1109; - assign n1119 = i_6_ & i_7_; - assign n1120 = ~i_8_ | ~n1119; - assign n1121 = n1103 | n1113; - assign n1122 = i_15_ | ~n142; - assign n1123 = n1096 | n1108; - assign n1124 = n1087 | n1108; - assign n1125 = n1096 | n1103; - assign n1126 = ~i_15_ | n478; - assign n1127 = n1109 | n1126; - assign n1128 = i_15_ | n478; - assign n1129 = n1103 | n1128; - assign n1130 = n1087 | n1103; - assign n1131 = ~i_11_ | i_9_ | ~i_10_; - assign n1132 = i_15_ | n1131; - assign n1133 = n1089 | n1132; - assign n1134 = n1088 | n1132; - assign n1135 = n1088 | n1128; - assign n1136 = n1107 | n1108; - assign n1137 = ~i_5_ & ~i_3_ & ~i_4_; - assign n1138 = n1085 & n1137; - assign n1139 = ~n555 | ~n1138; - assign n1140 = n241 | n1139; - assign n1141 = n265 | n477; - assign n1142 = n265 | n1139; - assign n1143 = n1109 | n1132; - assign n1144 = n1109 | n1122; - assign n1145 = n1123 | n456; - assign n1146 = n456 | n1097; - assign n1147 = n456 | n1046; - assign n1148 = n1147 & n1145 & n1146; - assign n1149 = n1108 | n1113; - assign n1150 = n1088 | n1113; - assign n1151 = n304 & n1149 & n1150; - assign n1152 = ~n430 & ~n818; - assign n1153 = n1108 | n1132; - assign n1154 = ~n539 & n1152; - assign n1155 = ~n1051 & n1154; - assign n1156 = ~n250 & n1155; - assign n1157 = n488 & n1156; - assign n1158 = ~n273 & ~n1053; - assign n1159 = n1157 & n1158; - assign n1160 = n684 & n1159; - assign n1161 = ~n1093 | n1120; - assign n1162 = n1161 & n1160; - assign n1163 = ~i_15_ | n1112; - assign n1164 = ~n1051 & ~n271 & n302; - assign n1165 = n850 & n1154; - assign n1166 = n469 & n1165; - assign n1167 = ~i_15_ | n1131; - assign n1168 = ~n220 & n850; - assign n1169 = ~n110 | n1115; - assign n1170 = ~n110 | n245; - assign n1171 = ~n212 | n1115; - assign n1172 = n1171 & n1169 & n1170; - assign n1173 = n1116 | n456; - assign n1174 = n988 | n456; - assign n1175 = ~n220 | n994; - assign n1176 = n1781 | n755; - assign n1177 = n755 | n1144; - assign n1178 = n225 | n1143; - assign n1179 = n456 | n1143; - assign n1180 = n1179 & n1178 & n706 & n671 & n1176 & n1177 & n600; - assign n1181 = n355 | ~n539; - assign n1182 = n245 | n796; - assign n1183 = ~n539 | n1115; - assign n1184 = n1151 | n796; - assign n1185 = ~n539 | n1151; - assign n1186 = n2026 & n2025 & n2024 & n2023 & n2021 & n2022; - assign n1187 = n1186 & n1185 & n1184 & n1183 & n1181 & n1182; - assign n1188 = n1115 | n850; - assign n1189 = n1151 | n850; - assign n1190 = n1781 | n419; - assign n1191 = n738 | n850; - assign n1192 = n355 | n850; - assign n1193 = n419 | n245; - assign n1194 = n2033 & n2032 & n1732 & n2031 & n2029 & n2030; - assign n1195 = n1193 & n1192 & n1191 & n1190 & n1188 & n1189 & n1194; - assign n1196 = i_14_ | i_12_ | ~i_13_; - assign n1197 = n1095 | n1196; - assign n1198 = n1088 | n1106; - assign n1199 = n1163 | n1196; - assign n1200 = n1106 | n1196; - assign n1201 = i_13_ | i_12_ | i_14_; - assign n1202 = n1102 | n1103; - assign n1203 = n1202 & n484; - assign n1204 = n1088 | n1090; - assign n1205 = n1090 | n1196; - assign n1206 = ~i_15_ | ~n142; - assign n1207 = n1096 | n1196; - assign n1208 = n1088 | n1126; - assign n1209 = n1087 | n1196; - assign n1210 = n727 & n316; - assign n1211 = n1095 | n1201; - assign n1212 = n1095 | n1103; - assign n1213 = n1211 & n1212; - assign n1214 = n1107 | n1196; - assign n1215 = n1103 | n1106; - assign n1216 = n1102 | n1196; - assign n1217 = n1167 | n1196; - assign n1218 = n1196 | n1206; - assign n1219 = n1091 | n1095; - assign n1220 = n456 | n1219; - assign n1221 = n456 | n1212; - assign n1222 = n456 | n1211; - assign n1223 = n1222 & n1220 & n1221; - assign n1224 = n1091 | n1126; - assign n1225 = n1103 | n1126; - assign n1226 = n1126 | n1201; - assign n1227 = n1088 | n1163; - assign n1228 = n1091 | n1163; - assign n1229 = n1103 | n1163; - assign n1230 = n1163 | n1201; - assign n1231 = n1230 & n1228 & n1229; - assign n1232 = n1122 | n1196; - assign n1233 = ~n818 | n1231; - assign n1234 = ~n818 | ~n892; - assign n1235 = ~n818 | n1205; - assign n1236 = n225 | n1199; - assign n1237 = n1236 & n1235 & n1233 & n1234; - assign n1238 = n456 | n1205; - assign n1239 = n456 | n1197; - assign n1240 = ~n220 | n1217; - assign n1241 = ~n220 | n1199; - assign n1242 = n1806 | n755; - assign n1243 = n755 | n1218; - assign n1244 = n456 | n1217; - assign n1245 = n602 & n1244 & n705 & n673 & n1242 & n1243 & n262; - assign n1246 = n1395 | n796; - assign n1247 = n268 | n796; - assign n1248 = n796 | n1205; - assign n1249 = n796 | n269; - assign n1250 = ~n539 | ~n892; - assign n1251 = n796 | ~n892; - assign n1252 = n796 | n1216; - assign n1253 = n1997 & n1998; - assign n1254 = n850 | ~n892; - assign n1255 = ~n275 | n850; - assign n1256 = n419 | n1216; - assign n1257 = n850 | n1200; - assign n1258 = n1806 | n419; - assign n1259 = n2002 & n2001 & n1730 & n900 & n1999 & n2000; - assign n1260 = n1259 & n1258 & n1257 & n1256 & n1254 & n1255; - assign n1261 = n1109 | n1206; - assign n1262 = n1108 | n1122; - assign n1263 = ~n110 | n1118; - assign n1264 = ~n110 | n1136; - assign n1265 = ~n110 | n1127; - assign n1266 = ~n212 | n237; - assign n1267 = n1266 & n1265 & n1263 & n1264; - assign n1268 = ~n220 | n346; - assign n1269 = ~n220 | n530; - assign n1270 = ~n220 | n1136; - assign n1271 = ~n220 | n1149; - assign n1272 = n456 | n1136; - assign n1273 = n1977 & n1975 & n1976; - assign n1274 = ~n430 | n1118; - assign n1275 = n349 | n1149; - assign n1276 = ~n430 | n1149; - assign n1277 = n349 | n1118; - assign n1278 = n1981 & n1980 & n1733 & n1756 & n1978 & n1979; - assign n1279 = n1278 & n292 & n1277 & n1276 & n1274 & n1275; - assign n1280 = n1103 | n1132; - assign n1281 = n1103 | n1104; - assign n1282 = ~n818 | n1129; - assign n1283 = ~n818 | n1130; - assign n1284 = ~n818 | n1125; - assign n1285 = n225 | n1130; - assign n1286 = n225 | n780; - assign n1287 = n225 | n1121; - assign n1288 = ~n818 | n1111; - assign n1289 = ~n220 | n1111; - assign n1290 = ~n220 | n1281; - assign n1291 = ~n220 | n304; - assign n1292 = n456 | n305; - assign n1293 = ~n220 | n990; - assign n1294 = ~n220 | n525; - assign n1295 = ~n220 | n1129; - assign n1296 = n1958 & n1956 & n1957; - assign n1297 = n349 | n304; - assign n1298 = n349 | n1121; - assign n1299 = n304 | ~n430; - assign n1300 = ~n430 | n1121; - assign n1301 = ~n430 | n1130; - assign n1302 = n1963 & n1962 & n1961 & n1960 & n1959 & n1757; - assign n1303 = n238 | n1161; - assign n1304 = n755 | n238; - assign n1305 = n238 | n684; - assign n1306 = n1727 & n1966 & n730 & n1965 & n1724 & n1964; - assign n1307 = n1091 | n1106; - assign n1308 = n1088 | n1206; - assign n1309 = n1091 | n1206; - assign n1310 = ~n818 | n1208; - assign n1311 = n345 | ~n818; - assign n1312 = ~n818 | n1227; - assign n1313 = ~n818 | n1204; - assign n1314 = ~n818 | n1198; - assign n1315 = n1314 & n1313 & n1312 & n1310 & n1311; - assign n1316 = n349 | n824; - assign n1317 = n405 | n824; - assign n1318 = n405 | n1308; - assign n1319 = n405 | n1309; - assign n1320 = n225 | n824; - assign n1321 = n1018 & n1935 & n1020 & n191; - assign n1322 = n1321 & n1320 & n1319 & n1318 & n1316 & n1317; - assign n1323 = ~n220 | n226; - assign n1324 = ~n220 | n345; - assign n1325 = n456 | n1224; - assign n1326 = ~n220 | n484; - assign n1327 = ~n220 | n1307; - assign n1328 = ~n220 | n1208; - assign n1329 = n1938 & n1936 & n1937; - assign n1330 = n1327 & n317 & n1326 & n1325 & n1323 & n1324 & n1328 & n1329; - assign n1331 = n349 | n1227; - assign n1332 = n349 | n1228; - assign n1333 = n349 | n1308; - assign n1334 = ~n430 | n1227; - assign n1335 = ~n430 | n1228; - assign n1336 = n1944 & n1943 & n1942 & n1941 & n1939 & n1940; - assign n1337 = n1336 & n1335 & n1334 & n1333 & n1331 & n1332; - assign n1338 = n1090 | n1201; - assign n1339 = n1132 | n1196; - assign n1340 = n1201 | n1206; - assign n1341 = ~n818 | n1209; - assign n1342 = n225 | n1214; - assign n1343 = n225 | n970; - assign n1344 = ~n818 | n1207; - assign n1345 = n225 | n1209; - assign n1346 = n643 | ~n818; - assign n1347 = ~n220 | n726; - assign n1348 = ~n220 | n1226; - assign n1349 = ~n220 | n643; - assign n1350 = n456 | n1226; - assign n1351 = ~n220 | n1338; - assign n1352 = n1926 & n1925 & n1923 & n1924; - assign n1353 = n1090 | n1103; - assign n1354 = n1088 | n1122; - assign n1355 = n405 | n535; - assign n1356 = n225 | n1134; - assign n1357 = n349 | n727; - assign n1358 = n405 | n1354; - assign n1359 = n187 & n1021 & n1358 & n1357 & n1355 & n1356 & n192; - assign n1360 = ~n430 | n1150; - assign n1361 = ~n430 | n1229; - assign n1362 = n349 | n1150; - assign n1363 = n349 | n1229; - assign n1364 = ~n430 | n1353; - assign n1365 = n349 | n1202; - assign n1366 = n349 | n1135; - assign n1367 = n349 | n1225; - assign n1368 = n1365 & n1364 & n1363 & n1362 & n1360 & n1361 & n1366 & n1367; - assign n1369 = n469 | n1118; - assign n1370 = ~n368 | n530; - assign n1371 = n469 | n346; - assign n1372 = ~n368 | n1118; - assign n1373 = ~n368 | n1136; - assign n1374 = n1821 & n1819 & n1820; - assign n1375 = n1822 & (~n368 | (n236 & n1262)); - assign n1376 = n1817 & n1816 & n1815 & n1814 & n1812 & n1813 & n1818 & n1811; - assign n1377 = n1374 & n1373 & n1372 & n1371 & n1369 & n1370 & n1375 & n1376; - assign n1378 = ~n368 | n970; - assign n1379 = ~n368 | n652; - assign n1380 = n469 | n1232; - assign n1381 = n469 | n1045; - assign n1382 = n1841 & n1840 & n1839 & n1838 & n1836 & n1837; - assign n1383 = n1835 & n1834 & n1833 & n1832 & n1830 & n1831 & n1829; - assign n1384 = n469 | n532; - assign n1385 = n469 | n525; - assign n1386 = n432 & n1384 & n1385; - assign n1387 = n469 | n1097; - assign n1388 = n469 | n1046; - assign n1389 = n433 & n1387 & n1388; - assign n1390 = n1281 & n1130; - assign n1391 = n970 & n1121; - assign n1392 = n1202 & n738; - assign n1393 = n419 & n1156; - assign n1394 = n652 & n1339; - assign n1395 = ~n278 & n1338; - assign n1396 = n1111 & n1124 & n1110; - assign n1397 = ~n1051 & n1152; - assign n1398 = ~n220 & n1397; - assign n1399 = ~n1053 & ~n679 & n405 & ~n539; - assign n1400 = n349 & n1398; - assign n1401 = n726 & n1210; - assign n1402 = ~n368 | n2298; - assign n1403 = n225 | n235; - assign n1404 = n225 | n1153; - assign n1405 = n456 | n1262; - assign n1406 = n1850 & n1849 & n1598 & n1848 & n1675 & n1847; - assign n1407 = n349 | n1226; - assign n1408 = n349 | n643; - assign n1409 = ~n430 | n1207; - assign n1410 = n349 | n1209; - assign n1411 = ~n430 | n1338; - assign n1412 = n349 | n1045; - assign n1413 = n349 | n652; - assign n1414 = n1856 & n1855 & n1854 & n1853 & n1851 & n1852; - assign n1415 = ~n430 | n2290; - assign n1416 = n1415 & n417 & n356 & n354 & ~n109 & n350; - assign n1417 = ~n368 | n1228; - assign n1418 = ~n368 | n1208; - assign n1419 = n469 | n1228; - assign n1420 = n469 | n1308; - assign n1421 = ~n368 | n1204; - assign n1422 = ~n368 | n484; - assign n1423 = n469 | n345; - assign n1424 = n1861 & n1860 & n1859 & n1858 & ~n215 & n1857; - assign n1425 = n1422 & n1421 & n1420 & n1419 & n1417 & n1418 & n1423 & n1424; - assign n1426 = ~n818 | n1118; - assign n1427 = n225 | n236; - assign n1428 = n225 | n1118; - assign n1429 = n346 | ~n818; - assign n1430 = n781 | ~n818; - assign n1431 = n225 | n1127; - assign n1432 = n1863 & n1862 & n1741; - assign n1433 = n1869 & n1868 & n1867 & n1866 & n1864 & n1865 & n1870 & n1871; - assign n1434 = ~n220 | n1110; - assign n1435 = ~n220 | n1353; - assign n1436 = ~n220 | n1135; - assign n1437 = n456 | n1225; - assign n1438 = n456 | n1215; - assign n1439 = ~n220 | n1215; - assign n1440 = n1874 & n1872 & n1873; - assign n1441 = n1880 & n1879 & n1878 & n1877 & n1875 & n1876 & n1881 & n1882; - assign n1442 = n1439 & n1438 & n1437 & n1436 & n1434 & n1435 & n1440 & n1441; - assign n1443 = ~n368 | n1225; - assign n1444 = n469 | n1215; - assign n1445 = ~n368 | n1110; - assign n1446 = ~n368 | n1353; - assign n1447 = n469 | n535; - assign n1448 = n1896 & n1894 & n1895; - assign n1449 = n1897 & (~n368 | n1354); - assign n1450 = n1892 & n1891 & n1890 & n1889 & n1887 & n1888 & n1893 & n1886; - assign n1451 = n469 | n1121; - assign n1452 = ~n368 | n1111; - assign n1453 = n469 | n238; - assign n1454 = n469 | n990; - assign n1455 = n1911 & n1909 & n1910; - assign n1456 = n1912 & (n238 | ~n368); - assign n1457 = n1904 & n1908 & n1907 & n1906 & n1742 & n1905; - assign n1458 = n1227 & n236; - assign n1459 = n850 & ~n212 & n302; - assign n1460 = ~n368 & ~n1051; - assign n1461 = ~n430 & n1460; - assign n1462 = n419 & ~n539; - assign n1463 = n225 & ~n250; - assign n1464 = (~n368 | n1309) & (~n1053 | n1227); - assign n1465 = n1091 | n1132; - assign n1466 = n1091 | n1104; - assign n1467 = n1091 | n1122; - assign n1468 = n1089 | n1163; - assign n1469 = n469 | n756; - assign n1470 = n469 | n1467; - assign n1471 = n469 | n642; - assign n1472 = n469 | n1466; - assign n1473 = n2083 & n2082 & n2081 & n2080 & n2078 & n2079; - assign n1474 = n481 | n477; - assign n1475 = n481 | n1139; - assign n1476 = n478 | n1139; - assign n1477 = ~n539 & n1400; - assign n1478 = n225 & n1400; - assign n1479 = n1108 | n1206; - assign n1480 = n628 & n711; - assign n1481 = n1466 & n756 & n642; - assign n1482 = ~n815 & n1164; - assign n1483 = ~n763 & ~n925; - assign n1484 = n225 | n725; - assign n1485 = n1484 & n916 & ~n112 & n618; - assign n1486 = n456 | n486; - assign n1487 = ~n465 | n796; - assign n1488 = n1487 & n189 & n1486 & n483; - assign n1489 = n2296 | n419; - assign n1490 = n1755 | n419; - assign n1491 = n2296 | n850; - assign n1492 = n849 | n419; - assign n1493 = n2291 | n850; - assign n1494 = n419 | n491; - assign n1495 = n1494 & n1493 & n1492 & n1491 & n1489 & n1490; - assign n1496 = ~n539 | n1755; - assign n1497 = n1755 | n796; - assign n1498 = ~n539 | n2296; - assign n1499 = ~n118 | n796; - assign n1500 = ~n118 | ~n539; - assign n1501 = ~n539 | n2291; - assign n1502 = n796 | n491; - assign n1503 = n2074 & n2072 & n2073; - assign n1504 = n456 | n491; - assign n1505 = n456 | n725; - assign n1506 = n849 | n456; - assign n1507 = ~n118 | ~n220; - assign n1508 = ~n220 | n2291; - assign n1509 = ~n120 | n456; - assign n1510 = n2077 & ~n466 & n464 & n460 & n453 & n457; - assign n1511 = n1508 & n1507 & n830 & n1506 & n1504 & n1505 & n1509 & n1510; - assign n1512 = i_2_ | i_0_ | ~i_1_; - assign n1513 = ~n1137 | n1512; - assign n1514 = ~n555 | n1513; - assign n1515 = i_0_ & ~i_1_; - assign n1516 = n1215 & n1212; - assign n1517 = ~n368 & n1463; - assign n1518 = n1100 & n1515; - assign n1519 = ~n271 & ~n679; - assign n1520 = n557 | n559 | n958 | n181; - assign n1521 = n558 & ~n970; - assign n1522 = n558 & ~n652; - assign n1523 = n558 & ~n1045; - assign n1524 = n1788 | n973 | n965; - assign n1525 = n967 | n1521 | n1522 | n976 | n1523 | n955 | n961 | n1524; - assign n1526 = n1384 & (n1463 | (n1516 & n1097)); - assign n1527 = n2116 & n2117 & n2118 & n1442 & n536 & n344; - assign n1528 = n1527 & n1526 & n1387 & ~n541 & ~n540 & ~n538 & n224 & ~n537; - assign n1529 = n556 & ~n1074; - assign n1530 = n1092 & n1515; - assign n1531 = ~n652 & n1529; - assign n1532 = ~n1045 & n1529; - assign n1533 = n962 | n1789 | n1786 | n964 | n957 | n972; - assign n1534 = n963 | n977 | n1531 | n1533 | n1532 | n956; - assign n1535 = n169 | n165 | n161; - assign n1536 = n1535 | n182 | n567; - assign n1537 = n269 & n570; - assign n1538 = ~n220 | n988; - assign n1539 = ~n220 | n1197; - assign n1540 = ~n220 | n725; - assign n1541 = n1540 & n1539 & n1538 & n616; - assign n1542 = n456 | n1133; - assign n1543 = n456 | n1134; - assign n1544 = n456 | n727; - assign n1545 = n456 | n726; - assign n1546 = n1205 & n1116; - assign n1547 = n495 & n940; - assign n1548 = n1466 & n699; - assign n1549 = n456 | ~n1027; - assign n1550 = n456 | n615; - assign n1551 = n2142 & n2143; - assign n1552 = n644 & n1549 & n637 & n640 & n633 & n629 & n1550 & n1551; - assign n1553 = n456 | n990; - assign n1554 = n456 | n244; - assign n1555 = n456 | n1202; - assign n1556 = n456 | n1045; - assign n1557 = n1556 & n1555 & n1554 & n295 & n1553 & n320 & n625; - assign n1558 = n456 | n1150; - assign n1559 = n456 | n304; - assign n1560 = ~n118 | n456; - assign n1561 = n456 | n1229; - assign n1562 = n456 | n1230; - assign n1563 = n1561 & n321 & n296 & n1560 & n1558 & n1559 & n1562; - assign n1564 = n1111 | n456; - assign n1565 = n226 | n456; - assign n1566 = n1124 | n456; - assign n1567 = n1110 | n456; - assign n1568 = n456 | n1353; - assign n1569 = n456 | n1338; - assign n1570 = n1569 & n1568 & n1567 & n1566 & n1564 & n1565 & n623; - assign n1571 = n456 | n605; - assign n1572 = n1244 & n1179 & n1486 & n1541 & n1571 & n617; - assign n1573 = n1217 & n1143; - assign n1574 = n1216 & n245; - assign n1575 = n469 | n1212; - assign n1576 = n469 | n1211; - assign n1577 = n469 | n1125; - assign n1578 = n469 | n1207; - assign n1579 = ~n368 | n1123; - assign n1580 = ~n368 | n1097; - assign n1581 = n232 | ~n368; - assign n1582 = n231 | ~n368; - assign n1583 = ~n368 | n1046; - assign n1584 = ~n368 | n1219; - assign n1585 = n1584 & n1583 & n1582 & n1581 & n1579 & n1580 & n586; - assign n1586 = n469 | n1200; - assign n1587 = n469 | n589; - assign n1588 = n469 | n1115; - assign n1589 = n1588 & n1587 & n1586 & n614; - assign n1590 = n469 | n994; - assign n1591 = n469 | n1199; - assign n1592 = n829 & n1590 & n1591; - assign n1593 = n316 | ~n368; - assign n1594 = ~n368 | n727; - assign n1595 = ~n368 | n1134; - assign n1596 = ~n368 | n1133; - assign n1597 = ~n368 | n726; - assign n1598 = n469 | n235; - assign n1599 = ~n368 | n1280; - assign n1600 = n1964 & n2084 & n1929 & n585 & n362 & n1585; - assign n1601 = n1598 & n1597 & n1596 & n1595 & n1593 & n1594 & n1599 & n1600; - assign n1602 = n1100 & ~n1512; - assign n1603 = n1512 | n1084 | ~n1099; - assign n1604 = n1603 & n569; - assign n1605 = n1512 | n123 | ~n222; - assign n1606 = n1401 & n1153 & n1134; - assign n1607 = n645 & n795; - assign n1608 = n405 | n726; - assign n1609 = n405 | n1153; - assign n1610 = n405 | n1134; - assign n1611 = n1610 & n1609 & ~n676 & n1608; - assign n1612 = n776 & n740; - assign n1613 = n1612 & n756 & n496; - assign n1614 = n495 & n642; - assign n1615 = ~n679 | n1225; - assign n1616 = ~n679 | n1226; - assign n1617 = ~n679 | n779; - assign n1618 = ~n679 | n781; - assign n1619 = ~n679 | n1129; - assign n1620 = n643 | ~n679; - assign n1621 = n1620 & n1619 & n1618 & n1617 & n1616 & ~n683 & n1615; - assign n1622 = ~n679 | n1281; - assign n1623 = n652 | ~n679; - assign n1624 = ~n679 | n1755; - assign n1625 = ~n679 | n738; - assign n1626 = ~n679 | ~n892; - assign n1627 = ~n679 | n1229; - assign n1628 = ~n679 | n1230; - assign n1629 = ~n118 | ~n679; - assign n1630 = ~n679 | n1149; - assign n1631 = ~n679 | n1121; - assign n1632 = ~n679 | n970; - assign n1633 = n1632 & n1631 & n1630 & n1629 & n1628 & ~n680 & n1627; - assign n1634 = n615 & n988 & n1197; - assign n1635 = n1219 & n1098; - assign n1636 = ~n709 | n1094; - assign n1637 = n349 | n572; - assign n1638 = n1151 & n620; - assign n1639 = n1468 & n725 & n530 & n244 & ~n278 & n1197; - assign n1640 = n243 | n1211; - assign n1641 = n988 | n243; - assign n1642 = n1762 | n243; - assign n1643 = n1983 & n1947 & n1984 & n1946 & n337 & n1969; - assign n1644 = n405 | n1205; - assign n1645 = n405 | n572; - assign n1646 = n622 | n405; - assign n1647 = n405 | n491; - assign n1648 = n1116 | n405; - assign n1649 = n1927 & n1985 & n338; - assign n1650 = n405 | n530; - assign n1651 = n405 | n244; - assign n1652 = n405 | n346; - assign n1653 = n405 | n345; - assign n1654 = n405 | n1045; - assign n1655 = n624 | n405; - assign n1656 = n243 | n1226; - assign n1657 = n243 | n305; - assign n1658 = n243 | n1224; - assign n1659 = n243 | n781; - assign n1660 = n243 | n1127; - assign n1661 = n243 | n1208; - assign n1662 = n340 & n1659 & n1658 & n1657 & n339 & n1656 & n1660 & n1661; - assign n1663 = n405 | n515; - assign n1664 = n1115 | n405; - assign n1665 = n2297 | n405; - assign n1666 = n405 | n1307; - assign n1667 = n405 | n1215; - assign n1668 = n1970 & n1988 & n1913; - assign n1669 = n1666 & n416 & n689 & n1665 & n1663 & n1664 & n1667 & n1668; - assign n1670 = n2297 | n243; - assign n1671 = n243 | n1215; - assign n1672 = n243 | n515; - assign n1673 = n1990 & n1952 & n1987 & n1951 & n1915 & n1967; - assign n1674 = n1673 & n1672 & n1671 & n1670 & ~n687 & n136 & n137; - assign n1675 = n405 | n235; - assign n1676 = n1762 | n405; - assign n1677 = n1676 & n1675 & n1611 & n1317 & ~n677 & n678; - assign n1678 = n405 | n1046; - assign n1679 = n405 | n1219; - assign n1680 = n405 | n1123; - assign n1681 = n405 | n1097; - assign n1682 = n405 | n1212; - assign n1683 = n405 | n1211; - assign n1684 = n1683 & n1682 & n1681 & n1680 & n1678 & n1679 & n406; - assign n1685 = n758 & n496 & n776; - assign n1686 = ~n216 | n1121; - assign n1687 = ~n216 | n970; - assign n1688 = ~n216 | n1199; - assign n1689 = ~n216 | n236; - assign n1690 = ~n216 | n1151; - assign n1691 = ~n216 | n994; - assign n1692 = n1691 & n1690 & n1689 & n1688 & n1687 & n1686 & ~n760 & n762; - assign n1693 = n1231 | n755; - assign n1694 = n755 | n236; - assign n1695 = n1151 | n755; - assign n1696 = n1695 & n1694 & n1693 & n759; - assign n1697 = n755 | n1232; - assign n1698 = n1692 & (n942 | n755); - assign n1699 = n1242 & n1176 & n1177 & n1763 & n1243 & n1304 & n2036 & n2008; - assign n1700 = ~i_2_ & i_0_ & i_1_; - assign n1701 = n524 & n773; - assign n1702 = n1137 & n1515; - assign n1703 = ~n123 & n1702; - assign n1704 = n968 | n1703 | n960 | n975; - assign n1705 = ~n110 | n237; - assign n1706 = ~n110 | n1204; - assign n1707 = ~n110 | n491; - assign n1708 = ~n110 | n2293; - assign n1709 = n1607 | n419; - assign n1710 = n225 | n1129; - assign n1711 = n225 | n643; - assign n1712 = n1635 | n225; - assign n1713 = n225 | n1208; - assign n1714 = n1713 & n1712 & n1711 & n1710 & n793 & n398 & ~n219 & n270; - assign n1715 = n231 | ~n818; - assign n1716 = ~n818 | n1123; - assign n1717 = ~n818 | n1635; - assign n1718 = n294 & (n397 | ~n818); - assign n1719 = n1718 & n1717 & n1715 & n1716; - assign n1720 = n1762 | n419; - assign n1721 = n728 | n850; - assign n1722 = n1401 | n850; - assign n1723 = n1722 & n1721 & n1720 & n823 & ~n821 & ~n822; - assign n1724 = n225 | n1280; - assign n1725 = n1634 | n225; - assign n1726 = n235 | ~n818; - assign n1727 = n225 | n1133; - assign n1728 = n1404 & n1403 & n1320; - assign n1729 = n2009 & n1719 & n1178 & ~n820 & ~n817 & ~n816 & n357 & n814; - assign n1730 = n2295 | n419; - assign n1731 = n2166 | n419; - assign n1732 = n2294 | n419; - assign n1733 = n349 | n232; - assign n1734 = n2076 & n1506 & n1808; - assign n1735 = n2156 & n1684 & n1550 & n1389 & n1239 & n1174 & ~n214 & n470; - assign n1736 = n1505 & n1733 & n1732 & n1492 & n1730 & n1731 & n1734 & n1735; - assign n1737 = n1762 | n796; - assign n1738 = n1737 & n1487 & ~n113 & ~n808; - assign n1739 = n225 | n572; - assign n1740 = n796 | n572; - assign n1741 = n225 | n237; - assign n1742 = n469 | n1130; - assign n1743 = n1494 & n1830 & n2029 & n1999; - assign n1744 = n721 & n599 & n783 & n128 & n999 & n838 & n1570 & n2177; - assign n1745 = n1246 & n2024 & n1502 & n1794 & n2026 & n1248 & n2176 & n2175; - assign n1746 = n1743 & n1742 & n1345 & n1285 & n1740 & n1741 & n1744 & n1745; - assign n1747 = n241 | n477; - assign n1748 = ~n818 | n1214; - assign n1749 = n780 | ~n818; - assign n1750 = n225 | n244; - assign n1751 = n225 | n990; - assign n1752 = n225 | n1281; - assign n1753 = n225 | n652; - assign n1754 = n225 | n345; - assign n1755 = n699 & n374; - assign n1756 = n349 | n530; - assign n1757 = n349 | n1281; - assign n1758 = n1979 & n1940 & n1824 & n1423 & ~n108 & n1371; - assign n1759 = n1497 & n1908 & n1252 & n1182 & n1251 & n2200 & n2023 & n2199; - assign n1760 = n2203 & n891 & n997 & n129 & n531 & n1557 & n2204 & n2202; - assign n1761 = n1760 & n1759 & n1758 & n1757 & n1756 & n1412 & ~n109 & n1365; - assign n1762 = n628 & n723; - assign n1763 = n755 | n776; - assign n1764 = n1762 | n456; - assign n1765 = n2225 & n757 & n2144 & n1009 & n2226 & n2159; - assign n1766 = n1676 & n1720 & n672 & n1764 & n1763 & n1737 & n601 & n1765; - assign n1767 = n225 | n1227; - assign n1768 = n1231 | n225; - assign n1769 = ~n220 & n1157; - assign n1770 = ~n925 | n970; - assign n1771 = ~n925 | n1151; - assign n1772 = ~n925 | n1121; - assign n1773 = (n1612 | n419) & (n456 | n496); - assign n1774 = ~n923 & (n469 | (n572 & n1685)); - assign n1775 = n1836 & n1469 & n1451 & n1343 & n1287 & ~n119 & n1236; - assign n1776 = n575 & n1563 & n1223 & n814 & n1592 & n1696; - assign n1777 = n906 & n1746 & n1736 & n998 & n1766 & n922; - assign n1778 = n2229 & n2228 & n1997 & n1725 & n1499 & n1427 & ~n113 & n1184; - assign n1779 = n1778 & n1777 & n1776 & n1775 & n1774 & n1773 & ~n924 & n1148; - assign n1780 = n747 & n610 & n740; - assign n1781 = n543 & n1262 & n1354; - assign n1782 = ~n1512 & n143 & ~n1084; - assign n1783 = ~n652 & n1782; - assign n1784 = ~n1045 & n1782; - assign n1785 = ~n970 & n1782; - assign n1786 = ~n970 & n1529; - assign n1787 = ~n558 & n670; - assign n1788 = ~n123 & n1518; - assign n1789 = ~n123 & n1530; - assign n1790 = ~n173 & ~n1119; - assign n1791 = ~n539 | n2292; - assign n1792 = n2292 | n796; - assign n1793 = ~n539 | n1762; - assign n1794 = n622 | n796; - assign n1795 = ~n539 | n615; - assign n1796 = n2297 | n796; - assign n1797 = n2193 & n2200 & n2213 & n1004 & n2231 & n2236; - assign n1798 = n1740 & n1795 & n1794 & n1793 & n1791 & n1792 & n1796 & n1797; - assign n1799 = n2297 | n850; - assign n1800 = n419 | n572; - assign n1801 = n622 | n850; - assign n1802 = n850 | n615; - assign n1803 = n1762 | n850; - assign n1804 = n2292 | n419; - assign n1805 = n412 & n397 & n401; - assign n1806 = n1340 & n1309 & n535; - assign n1807 = ~n381 & ~n679; - assign n1808 = n469 | n232; - assign n1809 = n469 | n236; - assign n1810 = n469 | n1149; - assign n1811 = n1810 & n1808 & n1809; - assign n1812 = n469 | n237; - assign n1813 = ~n368 | n1127; - assign n1814 = n469 | n1127; - assign n1815 = n469 | n781; - assign n1816 = n237 | ~n368; - assign n1817 = n469 | n1261; - assign n1818 = ~n368 | n1149; - assign n1819 = ~n368 | n781; - assign n1820 = ~n368 | n1124; - assign n1821 = n469 | n1262; - assign n1822 = n469 | n530; - assign n1823 = ~n368 | n1045; - assign n1824 = n469 | n652; - assign n1825 = ~n368 | n515; - assign n1826 = n469 | n1230; - assign n1827 = ~n368 | n1230; - assign n1828 = n469 | n1226; - assign n1829 = n1828 & n1827 & n1826 & n1825 & n1823 & n1824; - assign n1830 = n469 | n1209; - assign n1831 = ~n368 | n1226; - assign n1832 = ~n368 | n643; - assign n1833 = ~n368 | n1214; - assign n1834 = ~n368 | n1211; - assign n1835 = ~n368 | n1207; - assign n1836 = n469 | n970; - assign n1837 = ~n368 | n1338; - assign n1838 = n469 | n1340; - assign n1839 = ~n368 | n1209; - assign n1840 = n469 | n515; - assign n1841 = n469 | n1214; - assign n1842 = n1232 | n684; - assign n1843 = n1842 & (n302 | n1232); - assign n1844 = n456 | n1340; - assign n1845 = n1232 | n1161; - assign n1846 = n225 | n726; - assign n1847 = n405 | n1261; - assign n1848 = n405 | n1262; - assign n1849 = n349 | n235; - assign n1850 = n349 | n1153; - assign n1851 = ~n430 | n1230; - assign n1852 = ~n430 | n970; - assign n1853 = ~n430 | n1209; - assign n1854 = ~n430 | n1214; - assign n1855 = n349 | n1230; - assign n1856 = n349 | n970; - assign n1857 = n469 | n1309; - assign n1858 = ~n368 | n1224; - assign n1859 = ~n368 | n1198; - assign n1860 = n226 | ~n368; - assign n1861 = n469 | n484; - assign n1862 = n225 | n232; - assign n1863 = ~n818 | n1127; - assign n1864 = n225 | n346; - assign n1865 = n225 | n530; - assign n1866 = n225 | n1261; - assign n1867 = n225 | n1262; - assign n1868 = ~n818 | n1124; - assign n1869 = ~n818 | n1136; - assign n1870 = n236 | ~n818; - assign n1871 = n237 | ~n818; - assign n1872 = ~n220 | n727; - assign n1873 = ~n220 | n1212; - assign n1874 = ~n220 | n1225; - assign n1875 = n456 | n1135; - assign n1876 = ~n220 | n244; - assign n1877 = ~n220 | n1150; - assign n1878 = n456 | n1354; - assign n1879 = ~n220 | n1202; - assign n1880 = ~n220 | n532; - assign n1881 = ~n220 | n1097; - assign n1882 = n456 | n532; - assign n1883 = n469 | n1150; - assign n1884 = n469 | n1229; - assign n1885 = ~n368 | n1150; - assign n1886 = n1885 & n1883 & n1884; - assign n1887 = n469 | n1225; - assign n1888 = n244 | ~n368; - assign n1889 = ~n368 | n1202; - assign n1890 = ~n368 | n1215; - assign n1891 = ~n368 | n1212; - assign n1892 = ~n368 | n1229; - assign n1893 = n469 | n1135; - assign n1894 = n469 | n244; - assign n1895 = n469 | n1202; - assign n1896 = n469 | n1354; - assign n1897 = ~n368 | n1135; - assign n1898 = ~n368 | n990; - assign n1899 = ~n368 | n780; - assign n1900 = ~n368 | n1125; - assign n1901 = n469 | n304; - assign n1902 = n304 | ~n368; - assign n1903 = n469 | n305; - assign n1904 = n1903 & n1902 & n1901 & n1900 & n1898 & n1899; - assign n1905 = ~n368 | n1129; - assign n1906 = ~n368 | n1130; - assign n1907 = n469 | n780; - assign n1908 = n469 | n1281; - assign n1909 = n469 | n543; - assign n1910 = ~n368 | n1121; - assign n1911 = n305 | ~n368; - assign n1912 = ~n368 | n1281; - assign n1913 = n405 | n532; - assign n1914 = n1667 & n1913 & n694; - assign n1915 = n243 | n532; - assign n1916 = n593 & n583 & n1580 & n1543 & n1615 & n597; - assign n1917 = ~n818 | n1110; - assign n1918 = n1916 & n1917 & n1558 & n1555 & n1554 & n1544; - assign n1919 = n1750 & (~n679 | (n1135 & n1150)); - assign n1920 = (~n220 | n1354) & (~n815 | n1353); - assign n1921 = n1920 & (~n430 | n727); - assign n1922 = ~n220 | n1229; - assign n1923 = ~n220 | n1045; - assign n1924 = ~n220 | n515; - assign n1925 = ~n220 | n1211; - assign n1926 = n456 | n515; - assign n1927 = n405 | n1338; - assign n1928 = n1683 & n1597 & n716 & n1927 & n1640 & n1608; - assign n1929 = ~n368 | n1339; - assign n1930 = n1929 & n1576 & n1569; - assign n1931 = n1623 & n1556 & n1578 & n1562 & n1770 & n1748; - assign n1932 = ~n220 | n1230; - assign n1933 = (~n815 | n1338) & (n302 | n1339); - assign n1934 = (n349 | n1207) & (~n220 | n1340); - assign n1935 = n225 | n1308; - assign n1936 = ~n220 | n1219; - assign n1937 = ~n220 | n1224; - assign n1938 = n456 | n1307; - assign n1939 = n349 | n1198; - assign n1940 = n349 | n345; - assign n1941 = ~n430 | n1198; - assign n1942 = n349 | n1208; - assign n1943 = n349 | n1224; - assign n1944 = ~n430 | n1204; - assign n1945 = n1582 & n578 & n1593; - assign n1946 = n243 | n1219; - assign n1947 = n243 | n231; - assign n1948 = n349 | n231; - assign n1949 = n1948 & n1947 & n1946 & n1679 & n714 & n702 & n592 & n1945; - assign n1950 = n1666 & n1653 & n690 & n1658 & n1661; - assign n1951 = n243 | n1307; - assign n1952 = n243 | n1198; - assign n1953 = n1754 & (~n763 | (n1227 & n1308)); - assign n1954 = n1315 & (~n679 | (n1224 & n1228)); - assign n1955 = ~n220 | n1228; - assign n1956 = ~n220 | n1046; - assign n1957 = ~n220 | n305; - assign n1958 = n456 | n525; - assign n1959 = n349 | n1129; - assign n1960 = ~n430 | n780; - assign n1961 = ~n430 | n1125; - assign n1962 = n349 | n1130; - assign n1963 = n349 | n305; - assign n1964 = n469 | n1280; - assign n1965 = n225 | n238; - assign n1966 = n405 | n543; - assign n1967 = n243 | n525; - assign n1968 = n1967 & n1564 & n581 & n1599; - assign n1969 = n243 | n1046; - assign n1970 = n405 | n525; - assign n1971 = n1542 & n1553 & n1622 & n1577; - assign n1972 = (n1152 | n1281) & (n306 | ~n679); - assign n1973 = (n302 | n1280) & (~n212 | n780); - assign n1974 = (~n818 | n1121) & (n349 | n1125); - assign n1975 = ~n220 | n1153; - assign n1976 = n456 | n781; - assign n1977 = ~n220 | n1124; - assign n1978 = ~n430 | n1124; - assign n1979 = n349 | n346; - assign n1980 = n349 | n781; - assign n1981 = n237 | ~n430; - assign n1982 = n731 & n574 & n1581 & n1609 & n1680 & n713; - assign n1983 = n243 | n1123; - assign n1984 = n232 | n243; - assign n1985 = n405 | n1124; - assign n1986 = n1660 & n1659 & n1985 & n1983 & n1984; - assign n1987 = n1118 | n243; - assign n1988 = n405 | n1136; - assign n1989 = n1988 & n691 & n692 & n1987 & n1650 & n1652; - assign n1990 = n243 | n1136; - assign n1991 = ~n271 & ~n421; - assign n1992 = n419 & n796; - assign n1993 = (n1991 | n1123) & (n1992 | n1153); - assign n1994 = ~n430 & ~n539; - assign n1995 = n1993 & (n1994 | n781); - assign n1996 = (n243 | n530) & (~n220 | n1262); - assign n1997 = n1231 | n796; - assign n1998 = ~n539 | n1231; - assign n1999 = n419 | n1205; - assign n2000 = n419 | n269; - assign n2001 = n268 | n850; - assign n2002 = n1395 | n850; - assign n2003 = n472 & n468 & n1539; - assign n2004 = ~n430 | n1205; - assign n2005 = n349 | n1205; - assign n2006 = n695 & n2005 & n2004 & n137 & n753 & n1693 & n1644 & n414; - assign n2007 = ~n368 | n1197; - assign n2008 = ~n216 | n1806; - assign n2009 = ~n818 | n1401; - assign n2010 = n456 & n1164; - assign n2011 = n302 & n1156; - assign n2012 = ~n679 & n1164; - assign n2013 = (n2011 | n1199) & (n2012 | n1227); - assign n2014 = ~n216 & n1162; - assign n2015 = n1168 & ~n1053 & n225 & ~n539; - assign n2016 = (n1205 | n2015) & (n226 | ~n381); - assign n2017 = (n268 | n405) & (n316 | ~n421); - assign n2018 = (n1164 | n1214) & (n1156 | n1232); - assign n2019 = ~n430 | n726; - assign n2020 = n1237 & n266 & n656 & n1245 & n1260 & n1014 & n270 & n2019; - assign n2021 = n570 | n796; - assign n2022 = ~n539 | n738; - assign n2023 = n738 | n796; - assign n2024 = n1396 | n796; - assign n2025 = ~n218 | n796; - assign n2026 = n1116 | n796; - assign n2027 = n241 | n894; - assign n2028 = n242 & n894; - assign n2029 = n1116 | n419; - assign n2030 = n419 | n570; - assign n2031 = n355 | n419; - assign n2032 = ~n218 | n850; - assign n2033 = n1396 | n850; - assign n2034 = ~n368 | n988; - assign n2035 = n1588 & n1590 & n2034; - assign n2036 = ~n216 | n1781; - assign n2037 = ~n430 | n1116; - assign n2038 = n1664 & n2037 & n136 & n1695 & n2036 & n754 & n696 & n1648; - assign n2039 = ~n818 | n1116; - assign n2040 = (n248 | n1115) & (n2014 | n1144); - assign n2041 = (n1125 | n2010) & (n239 | ~n273); - assign n2042 = (~n250 | n653) & (n1116 | n2015); - assign n2043 = (n994 | n1157) & (~n381 | n1124); - assign n2044 = (n238 | n1156) & (~n218 | n405); - assign n2045 = n1172 & (~n220 | n1118); - assign n2046 = n1180 & n1187 & n1195 & n139; - assign n2047 = n1717 & n1712 & ~n117 & n715; - assign n2048 = ~n380 & (n2010 | (n1209 & n1390)); - assign n2049 = ~n383 & (~n273 | (n648 & n1391)); - assign n2050 = ~n384 & (~n212 | (n352 & n1392)); - assign n2051 = ~n386 & (~n818 | (n226 & ~n879)); - assign n2052 = ~n1053 & n1393; - assign n2053 = (n378 | n225) & (n1573 | n2052); - assign n2054 = ~n212 | n372; - assign n2055 = (n376 | n456) & (n230 | ~n679); - assign n2056 = (~n539 | n842) & (n1635 | n1991); - assign n2057 = ~n220 & n419; - assign n2058 = (n653 | n2057) & (n1156 | n1005); - assign n2059 = ~n271 & n1398; - assign n2060 = (n1164 | n1391) & (n375 | n2059); - assign n2061 = ~n271 & ~n501; - assign n2062 = (n233 | ~n430) & (n234 | n2061); - assign n2063 = n1399 & n225 & n1398; - assign n2064 = n1400 & n456 & n1399; - assign n2065 = (n1574 | n2063) & (n1537 | n2064); - assign n2066 = ~n216 & ~n925; - assign n2067 = (n1231 | n2066) & (n1463 | n1213); - assign n2068 = n740 | n2132; - assign n2069 = (~n271 | n726) & (~n815 | n1151); - assign n2070 = (~n110 | n530) & (n1158 | n1227); - assign n2071 = n1425 & n423 & n1442 & n534 & n344 & n542 & n1416 & n1035; - assign n2072 = n2291 | n796; - assign n2073 = ~n539 | n779; - assign n2074 = n779 | n796; - assign n2075 = n481 | n894; - assign n2076 = n469 | n725; - assign n2077 = n1755 | n456; - assign n2078 = ~n368 | n1466; - assign n2079 = ~n368 | n756; - assign n2080 = ~n368 | n632; - assign n2081 = ~n368 | n628; - assign n2082 = ~n368 | n642; - assign n2083 = n469 | n636; - assign n2084 = ~n368 | n1465; - assign n2085 = n2084 & (~n764 | (~n763 & n1161)); - assign n2086 = (n1483 | n1468) & (n2066 | n756); - assign n2087 = n850 & n796; - assign n2088 = n419 & ~n271 & ~n368; - assign n2089 = n2087 | n232; - assign n2090 = (~n212 | n781) & (n1161 | n1262); - assign n2091 = n1220 & n1145; - assign n2092 = ~n763 & n1393; - assign n2093 = ~n213 & (n2092 | (n1262 & n1309)); - assign n2094 = ~n499 & (n491 | (n225 & n1477)); - assign n2095 = ~n500 & (n699 | (n405 & n1478)); - assign n2096 = ~n679 & n1159; - assign n2097 = (n1805 | n489) & (n2096 | n498); - assign n2098 = (n492 | ~n1053) & (n490 | n1468); - assign n2099 = ~n763 & n1162; - assign n2100 = ~n501 & n796; - assign n2101 = (n2100 | n1124) & (n2087 | n781); - assign n2102 = n755 & n1482; - assign n2103 = (n1769 | n945) & (n2102 | n1228); - assign n2104 = n2101 & n2103 & (n1165 | n1153); - assign n2105 = n1164 & n1483; - assign n2106 = (~n379 | n412) & (n1149 | n2105); - assign n2107 = n1165 & n796 & n488; - assign n2108 = (~n273 | n485) & (n1224 | n2107); - assign n2109 = (n463 | n1400) & (~n385 | n1398); - assign n2110 = (n243 | n401) & (n484 | ~n679); - assign n2111 = (~n368 | n589) & (n755 | n756); - assign n2112 = n494 & n2111 & (~n539 | n1136); - assign n2113 = n1495 & n1013 & n140 & n476 & n450 & n1511 & n1488 & n1485; - assign n2114 = n416 & n413 & n409 & n406 & n398 & n402 & n429 & n440; - assign n2115 = n1385 & (n456 | (n1390 & n1280)); - assign n2116 = (n1134 | n2057) & (n535 | ~n546); - assign n2117 = (~n815 | n1150) & (n1229 | n2066); - assign n2118 = ~n212 | n1215; - assign n2119 = n1221 & (n1164 | (n1390 & n1353)); - assign n2120 = n2119 & (n243 | (n653 & n990)); - assign n2121 = (n229 | n2061) & (n1482 | n727); - assign n2122 = n247 & n1519; - assign n2123 = (n2122 | n346) & (n2052 | n1143); - assign n2124 = (~n503 | n1516) & (n232 | n1462); - assign n2125 = (n1202 | n2012) & (~n818 | n1392); - assign n2126 = (~n421 | n1105) & (n1280 | n2059); - assign n2127 = n1398 & n456 & n684; - assign n2128 = n2125 & n2126 & (n2127 | n1261); - assign n2129 = (n1519 | n1127) & (n2063 | n245); - assign n2130 = (n2102 | n1229) & (n2064 | n570); - assign n2131 = n1098 | n1154; - assign n2132 = ~n925 & n755 & ~n679 & ~n368 & n456; - assign n2133 = (n994 | n2132) & (~n879 | n1152); - assign n2134 = (n2092 | n535) & (n1156 | n1781); - assign n2135 = ~n368 | n651; - assign n2136 = n2289 | n469; - assign n2137 = n651 | n469; - assign n2138 = ~n368 | n1612; - assign n2139 = n608 | n469; - assign n2140 = n469 | n776; - assign n2141 = n536 & n544 & n666 & n1589 & n606 & n612 & n476 & n448; - assign n2142 = ~n220 | n645; - assign n2143 = n456 | n572; - assign n2144 = n620 | n456; - assign n2145 = n1612 | n456; - assign n2146 = n2289 | n456; - assign n2147 = n1442 & n1330 & n327 & n1552 & n649 & n1511; - assign n2148 = n1150 & n304; - assign n2149 = n993 | n349; - assign n2150 = n349 | n613; - assign n2151 = ~n430 | n1634; - assign n2152 = (~n421 | n741) & (~n430 | n739); - assign n2153 = n266 & (~n142 | n261); - assign n2154 = n622 | n243; - assign n2155 = n1358 & n1848 & n1319 & n1966 & n1355 & n358 & n1847 & n1318; - assign n2156 = n2166 | n405; - assign n2157 = n1612 | n405; - assign n2158 = n2292 | n405; - assign n2159 = n620 | n405; - assign n2160 = ~n277 | n748; - assign n2161 = ~n381 | n1614; - assign n2162 = n1936 & n1956; - assign n2163 = n813 | ~n818; - assign n2164 = n1925 & (n615 | (~n379 & ~n818)); - assign n2165 = n2166 | n850; - assign n2166 = n1197 & n725 & n988; - assign n2167 = (~n379 | n725) & (~n818 | n2166); - assign n2168 = n2135 & n1981 & n1944 & n1978 & n1364 & n1415 & n1421 & n1816; - assign n2169 = n1283 & n1341 & n2039 & n1235 & n1434 & n1977 & n1501 & n785; - assign n2170 = n1801 & n1871 & n1313 & n1868 & n1288 & n1917 & n2002 & n2033; - assign n2171 = ~n379 & n1152; - assign n2172 = n242 & ~n709; - assign n2173 = (~n368 | n572) & (~n818 | n1395); - assign n2174 = n1504 & n1173; - assign n2175 = n1812 & n2143 & n1962 & n2137 & n1410 & n1637 & n1238 & n2174; - assign n2176 = n2072 & n2075 & n1475; - assign n2177 = n1800 & (n349 | n632); - assign n2178 = ~n220 | n825; - assign n2179 = n453 & n647 & n1572 & n1601 & n735 & n576 & n1223 & n2178; - assign n2180 = n1903 & n1887 & n2146 & n1814 & n1893 & n1815 & n1828; - assign n2181 = n1476 & n1265 & n1407 & n1959 & n263 & n1408 & n786; - assign n2182 = n1350 & n1804 & n1862 & n1431 & n1437 & n1976 & n2030; - assign n2183 = (n1537 | n405) & (n469 | n463); - assign n2184 = n464 & (n478 | n894); - assign n2185 = n1874 & n1957 & n1937 & n2073 & n1418 & n1813; - assign n2186 = n1348 & n1328 & n1436 & n1819 & n1349 & n1295; - assign n2187 = n2082 & n1443 & n1831 & n2032 & n1832 & n1905 & n2186; - assign n2188 = ~n867 & (n478 | (n242 & n477)); - assign n2189 = (n1994 | n781) & (n1400 | n792); - assign n2190 = n2189 & (n1537 | n1477); - assign n2191 = (n352 | n850) & (n353 | ~n1051); - assign n2192 = n1438 & n1958 & n1938 & n1277 & n1939 & n1369; - assign n2193 = n796 | n613; - assign n2194 = n1140 & n2150 & n2027 & n2193 & n1796 & n1169 & n2192; - assign n2195 = n2149 & n1428 & n1342 & n1286 & ~n116 & n1272; - assign n2196 = n993 | n419; - assign n2197 = (n405 | n589) & (n349 | n412); - assign n2198 = n1589 & n637 & n413; - assign n2199 = n1170 & n1413 & n1142; - assign n2200 = n624 | n796; - assign n2201 = n1256 & n1490 & n1193; - assign n2202 = n1864 & n1861 & n1454 & n1894 & n2077 & n1822 & n1865 & n2201; - assign n2203 = n1472 & n1895 & n1381; - assign n2204 = (n895 | n265) & (n469 | n699); - assign n2205 = n1859 & n1373 & n1294 & n1327 & n1372 & n1439 & n1890; - assign n2206 = ~n818 | n993; - assign n2207 = n1880 & n2206 & n1270 & n1079 & n1402 & n1924; - assign n2208 = n2054 & n1491 & n1255 & n1192; - assign n2209 = ~n213 & (n613 | (n850 & n1152)); - assign n2210 = n2209 & (~n539 | (n589 & n688)); - assign n2211 = n636 & n897; - assign n2212 = n1889 & n1823 & n1370 & n1888 & n1422 & n1898 & n1141; - assign n2213 = ~n539 | n624; - assign n2214 = n1923 & n1290 & n1268 & n1324 & n1879 & n1269 & n2078; - assign n2215 = n1234 & (n1574 | (~n539 & n850)); - assign n2216 = ~n907 & (~n368 | (n874 & n1755)); - assign n2217 = (n1400 | n1548) & (n1397 | n1281); - assign n2218 = (~n277 | n746) & (~n212 | n528); - assign n2219 = (n1152 | n738) & (n1164 | n747); - assign n2220 = (n374 | ~n1051) & (n652 | n1398); - assign n2221 = n265 | n242; - assign n2222 = n2211 | n349; - assign n2223 = n1136 & n236 & n397 & n1215 & n532 & n1307; - assign n2224 = n1762 & ~n918 & n845 & n780 & n636 & n667; - assign n2225 = (n1992 | n615) & (n225 | n613); - assign n2226 = n620 | n419; - assign n2227 = n2157 & n1948 & n1826 & n1362 & n1331 & n1275; - assign n2228 = n1419 & n1901 & n1809 & n2145 & n1810 & n1883 & n1884 & n2227; - assign n2229 = n1363 & n1332 & n1297 & n1856 & n1855 & n1298; - assign n2230 = n1902 & n1417 & n1892 & n1827 & n731 & n2138 & n1885 & n1818; - assign n2231 = ~n539 | n620; - assign n2232 = n1185 & n1998 & n1300 & n1852 & n1500 & n828 & n2231; - assign n2233 = (~n709 | n1112) & (~n220 | n776); - assign n2234 = n2233 & n453 & n1541 & n1633 & n1585 & n621; - assign n2235 = n1509 & n1867 & n1866 & n1821 & n1878 & n1549; - assign n2236 = n796 | ~n1027; - assign n2237 = n1571 & n1333 & n1817 & n830 & n1420 & n2139 & n2236 & n2235; - assign n2238 = n1470 & n1838 & n1447 & n1190 & n1453 & n1380; - assign n2239 = (n946 | n469) & (n685 | n684); - assign n2240 = n1781 & ~n764 & n944; - assign n2241 = (n2240 | n1161) & (n488 | n941); - assign n2242 = n1180 & n1245 & (n992 | n796); - assign n2243 = ~n979 | n982; - assign n2244 = (~n172 | ~n1119) & (n1513 | n1790); - assign n2245 = n516 & n969; - assign n2246 = (n1083 | n122) & (n2245 | n990); - assign n2247 = (n122 | ~n1119) & (n304 | n2245); - assign n2248 = (n1230 | n2245) & (n122 | ~n173); - assign n2249 = n1083 & n1790; - assign n2250 = ~n159 & (~n222 | n1512 | n2249); - assign n2251 = n1935 & n1917 & n2206; - assign n2252 = n361 & n1965 & (n996 | n225); - assign n2253 = (n610 | ~n815) & (~n818 | n991); - assign n2254 = ~n1028 & (~n501 | (~n385 & n1780)); - assign n2255 = n2254 & (n1026 | n850); - assign n2256 = (n2066 | n1230) & (n247 | n652); - assign n2257 = ~n1050 & (n2092 | (n543 & n1340)); - assign n2258 = ~n1055 & (n990 | (~n381 & n1393)); - assign n2259 = (n1160 | n945) & (n2099 | n985); - assign n2260 = (~n503 | n1047) & (n1478 | n1481); - assign n2261 = (n615 | n1043) & (~n281 | n1465); - assign n2262 = (~n815 | n1480) & (n645 | n1155); - assign n2263 = (n1338 | n2100) & (~n1027 | n1477); - assign n2264 = (n726 | n1165) & (n524 | ~n679); - assign n2265 = (n1769 | n605) & (n2102 | n1230); - assign n2266 = (n2105 | n304) & (n2066 | n776); - assign n2267 = (n247 | n1466) & (n622 | n419); - assign n2268 = (~n381 | n401) & (~n421 | n628); - assign n2269 = (n488 | n1467) & (n1164 | n1111); - assign n2270 = (n1398 | n652) & (n1156 | n1133); - assign n2271 = (n456 | n632) & (~n110 | n463); - assign n2272 = n796 | n1045; - assign n2273 = n2270 & n2271 & n2272 & n450 & n554 & n526; - assign n2274 = n1146 & (n1156 | (n1806 & n1134)); - assign n2275 = n2274 & (n484 | (n225 & ~n421)); - assign n2276 = ~n1065 & (n244 | (n1393 & n1807)); - assign n2277 = (n228 | n2061) & (~n110 | n778); - assign n2278 = n2277 & (n1394 | n2059); - assign n2279 = (n2122 | n345) & (n2052 | n1217); - assign n2280 = ~n1066 & ~n1067 & (n1110 | n2100); - assign n2281 = (n2127 | n1308) & (n1519 | n1208); - assign n2282 = (n2063 | n1216) & (n2105 | n1150); - assign n2283 = (n2064 | n269) & (n247 | n231); - assign n2284 = (n2132 | n1199) & (n1210 | n243); - assign n2285 = (~n503 | n1097) & (n1354 | n2092); - assign n2286 = (n1135 | n2107) & (~n381 | n1202); - assign n2287 = (~n430 | n1045) & (n405 | n652); - assign n2288 = i_2_ | ~i_0_ | i_1_; - assign n2289 = n610 & n1537; - assign n2290 = n226 & n1110 & n1111; - assign n2291 = n401 & n237 & n1204; - assign n2292 = n642 & n353; - assign n2293 = n226 & n401 & n1124; - assign n2294 = n1123 & n1098; - assign n2295 = n1219 & n1213; - assign n2296 = n1198 & n459; - assign n2297 = n636 & n348; - assign n2298 = ~n879 & n1307; -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/MCNC/tseng/tseng.v b/fpga_flow/benchmarks/Verilog/MCNC/tseng/tseng.v deleted file mode 100644 index 6c2cf208b..000000000 --- a/fpga_flow/benchmarks/Verilog/MCNC/tseng/tseng.v +++ /dev/null @@ -1,1648 +0,0 @@ -// Benchmark "top" written by ABC on Tue Mar 5 10:05:48 2019 - -module tseng ( clock, - tin_pv10_4_4_, tin_pv11_4_4_, tin_pv6_7_7_, tin_pv2_0_0_, - tin_pv10_3_3_, tin_pv1_2_2_, tin_pv11_3_3_, tin_pv4_3_3_, - tin_pv10_2_2_, tin_pv11_2_2_, tin_pv6_0_0_, tin_pv2_1_1_, - tin_pv10_1_1_, tin_pv1_3_3_, preset_0_0_, tin_pv11_1_1_, tin_pv4_4_4_, - tin_pready_0_0_, tin_pv10_0_0_, tin_pv11_0_0_, tin_pv6_1_1_, - tin_pv2_2_2_, tin_pv1_4_4_, tin_pv4_5_5_, tin_pv6_2_2_, tin_pv2_3_3_, - tin_pv1_5_5_, tin_pv4_6_6_, tin_pv6_3_3_, tin_pv2_4_4_, tin_pv1_6_6_, - tin_pv4_7_7_, tin_pv6_4_4_, tin_pv2_5_5_, tin_pv1_7_7_, - tin_pv4_0_0_, tin_pv6_5_5_, tin_pv2_6_6_, tin_pv10_7_7_, tin_pv1_0_0_, - tin_pv11_7_7_, tin_pv4_1_1_, tin_pv10_6_6_, tin_pv11_6_6_, - tin_pv6_6_6_, tin_pv2_7_7_, preset, tin_pv10_5_5_, tin_pv1_1_1_, - tin_pv11_5_5_, tin_pv4_2_2_, - pv14_2_2_, pv12_3_3_, pv10_4_4_, pv7_5_5_, pv3_6_6_, pv15_2_2_, - pv13_3_3_, pv11_4_4_, pv6_7_7_, pv2_0_0_, pv14_1_1_, pv12_2_2_, - pv10_3_3_, pv9_0_0_, pv5_1_1_, pv1_2_2_, pv15_1_1_, pv13_2_2_, - pv11_3_3_, pv8_2_2_, pv4_3_3_, pv14_0_0_, pv12_1_1_, pv10_2_2_, - pv7_6_6_, pv3_7_7_, pv15_0_0_, pv13_1_1_, pv11_2_2_, pv6_0_0_, - pv2_1_1_, pv12_0_0_, pv10_1_1_, pv9_1_1_, pv5_2_2_, pv1_3_3_, - pv13_0_0_, pv11_1_1_, pv8_3_3_, pv4_4_4_, pready_0_0_, pv10_0_0_, - pv7_7_7_, pv3_0_0_, pv11_0_0_, pv6_1_1_, pv2_2_2_, pv9_2_2_, pv5_3_3_, - pv1_4_4_, pv8_4_4_, pv4_5_5_, pv7_0_0_, pv3_1_1_, pv6_2_2_, pv2_3_3_, - pv9_3_3_, pv5_4_4_, pv1_5_5_, pv8_5_5_, pv4_6_6_, pv7_1_1_, pv3_2_2_, - pv6_3_3_, pv2_4_4_, pv9_4_4_, pv5_5_5_, pv1_6_6_, pv8_6_6_, pv4_7_7_, - pv7_2_2_, pv3_3_3_, pv6_4_4_, pv2_5_5_, pv14_7_7_, pv9_5_5_, pv5_6_6_, - pv1_7_7_, pv15_7_7_, pv8_7_7_, pv4_0_0_, pv14_6_6_, pv12_7_7_, - pv7_3_3_, pv3_4_4_, pv15_6_6_, pv13_7_7_, pv6_5_5_, pv2_6_6_, pdn, - pv14_5_5_, pv12_6_6_, pv10_7_7_, pv9_6_6_, pv5_7_7_, pv1_0_0_, - pv15_5_5_, pv13_6_6_, pv11_7_7_, pv8_0_0_, pv4_1_1_, pv14_4_4_, - pv12_5_5_, pv10_6_6_, pv7_4_4_, pv3_5_5_, pv15_4_4_, pv13_5_5_, - pv11_6_6_, pv6_6_6_, pv2_7_7_, pv14_3_3_, pv12_4_4_, pv10_5_5_, - pv9_7_7_, pv5_0_0_, pv1_1_1_, pv15_3_3_, pv13_4_4_, pv11_5_5_, - pv8_1_1_, pv4_2_2_ ); - input tin_pv10_4_4_, tin_pv11_4_4_, tin_pv6_7_7_, tin_pv2_0_0_, - tin_pv10_3_3_, tin_pv1_2_2_, tin_pv11_3_3_, tin_pv4_3_3_, - tin_pv10_2_2_, tin_pv11_2_2_, tin_pv6_0_0_, tin_pv2_1_1_, - tin_pv10_1_1_, tin_pv1_3_3_, preset_0_0_, tin_pv11_1_1_, tin_pv4_4_4_, - tin_pready_0_0_, tin_pv10_0_0_, tin_pv11_0_0_, tin_pv6_1_1_, - tin_pv2_2_2_, tin_pv1_4_4_, tin_pv4_5_5_, tin_pv6_2_2_, tin_pv2_3_3_, - tin_pv1_5_5_, tin_pv4_6_6_, tin_pv6_3_3_, tin_pv2_4_4_, tin_pv1_6_6_, - clock, tin_pv4_7_7_, tin_pv6_4_4_, tin_pv2_5_5_, tin_pv1_7_7_, - tin_pv4_0_0_, tin_pv6_5_5_, tin_pv2_6_6_, tin_pv10_7_7_, tin_pv1_0_0_, - tin_pv11_7_7_, tin_pv4_1_1_, tin_pv10_6_6_, tin_pv11_6_6_, - tin_pv6_6_6_, tin_pv2_7_7_, preset, tin_pv10_5_5_, tin_pv1_1_1_, - tin_pv11_5_5_, tin_pv4_2_2_; - output pv14_2_2_, pv12_3_3_, pv10_4_4_, pv7_5_5_, pv3_6_6_, pv15_2_2_, - pv13_3_3_, pv11_4_4_, pv6_7_7_, pv2_0_0_, pv14_1_1_, pv12_2_2_, - pv10_3_3_, pv9_0_0_, pv5_1_1_, pv1_2_2_, pv15_1_1_, pv13_2_2_, - pv11_3_3_, pv8_2_2_, pv4_3_3_, pv14_0_0_, pv12_1_1_, pv10_2_2_, - pv7_6_6_, pv3_7_7_, pv15_0_0_, pv13_1_1_, pv11_2_2_, pv6_0_0_, - pv2_1_1_, pv12_0_0_, pv10_1_1_, pv9_1_1_, pv5_2_2_, pv1_3_3_, - pv13_0_0_, pv11_1_1_, pv8_3_3_, pv4_4_4_, pready_0_0_, pv10_0_0_, - pv7_7_7_, pv3_0_0_, pv11_0_0_, pv6_1_1_, pv2_2_2_, pv9_2_2_, pv5_3_3_, - pv1_4_4_, pv8_4_4_, pv4_5_5_, pv7_0_0_, pv3_1_1_, pv6_2_2_, pv2_3_3_, - pv9_3_3_, pv5_4_4_, pv1_5_5_, pv8_5_5_, pv4_6_6_, pv7_1_1_, pv3_2_2_, - pv6_3_3_, pv2_4_4_, pv9_4_4_, pv5_5_5_, pv1_6_6_, pv8_6_6_, pv4_7_7_, - pv7_2_2_, pv3_3_3_, pv6_4_4_, pv2_5_5_, pv14_7_7_, pv9_5_5_, pv5_6_6_, - pv1_7_7_, pv15_7_7_, pv8_7_7_, pv4_0_0_, pv14_6_6_, pv12_7_7_, - pv7_3_3_, pv3_4_4_, pv15_6_6_, pv13_7_7_, pv6_5_5_, pv2_6_6_, pdn, - pv14_5_5_, pv12_6_6_, pv10_7_7_, pv9_6_6_, pv5_7_7_, pv1_0_0_, - pv15_5_5_, pv13_6_6_, pv11_7_7_, pv8_0_0_, pv4_1_1_, pv14_4_4_, - pv12_5_5_, pv10_6_6_, pv7_4_4_, pv3_5_5_, pv15_4_4_, pv13_5_5_, - pv11_6_6_, pv6_6_6_, pv2_7_7_, pv14_3_3_, pv12_4_4_, pv10_5_5_, - pv9_7_7_, pv5_0_0_, pv1_1_1_, pv15_3_3_, pv13_4_4_, pv11_5_5_, - pv8_1_1_, pv4_2_2_; - reg n_n4142, n_n3936, n_n3574, n_n3008, n_n3726, n_n3604, n_n3144, - n_n3782, n_n3067, n_n4258, n_n3225, n_n3180, n_n3274, n_n3475, n_n3687, - n_n3381, n_n3098, n_n4108, n_n3497, n_n3793, n_n4316, n_n4349, n_n3029, - n_n3619, n_n3264, n_n3780, ndn3_4, n_n4114, n_n3146, n_n3511, n_n3152, - n_n3833, n_n4282, n_n3305, n_n4392, n_n4224, n_n3198, n_n3204, n_n3024, - n_n4139, ndn3_15, n_n3133, n_n4074, n_n3270, n_n3858, n_n3456, n_n3521, - n_n3081, n_n4381, n_n3670, n_n4211, n_n3493, n_n3495, n_n3916, n_n3195, - n_n3525, n_n3729, n_n3876, ndn3_5, n_n3549, n_n3489, n_n3764, n_n3281, - n_n3707, n_n3517, n_n4160, n_n4222, n_n3012, n_n4071, n_n3372, n_n3344, - n_n3688, n_n3079, n_n3313, n_n3411, n_n3231, n_n3396, n_n3432, n_n3606, - n_n3733, n_n3556, n_n4040, n_n3120, n_n3221, n_n3173, n_n3851, n_n3113, - n_n3242, n_n3118, n_n3376, n_n4089, n_n3044, n_n3627, n_n3035, n_n3111, - n_n3321, n_n3443, n_n3215, ndn3_10, n_n4172, nlc1_2, n_n3590, n_n4110, - nlc3_3, n_n3576, n_n4129, n_n4189, n_n4286, n_n4383, pdn, n_n3567, - n_n3892, n_n3075, n_n3354, n_n3465, ndn3_6, n_n3617, n_n4162, n_n3207, - n_n4120, n_n3065, n_n4005, n_n3266, n_n4337, n_n3600, n_n3415, n_n4243, - n_n3872, n_n3648, n_n3358, n_n3350, ndn3_7, n_n3116, n_n3583, n_n3906, - n_n4131, n_n3316, n_n3061, n_n3048, n_n3886, n_n3919, n_n3128, n_n3995, - n_n4213, n_n3761, ndn3_8, n_n3252, n_n4366, n_n3328, n_n3988, n_n3348, - n_n3544, n_n3101, n_n4279, n_n3896, n_n3736, n_n4251, n_n3650, n_n3307, - n_n4294, n_n4334, n_n3955, n_n4164, n_n3155, n_n3749, n_n4233, n_n4347, - n_n3826, n_n3360, n_n3458, n_n3093, n_n3157, n_n3506, n_n3161, n_n3319, - n_n3429, n_n3971, n_n3449, n_n4270, n_n4288, n_n3183, n_n3130, nlak4_2, - n_n4047, n_n3978, n_n3239, n_n4145, n_n3890, n_n4003, n_n3091, n_n3985, - n_n3326, n_n4052, nsr4_2, n_n4099, n_n4375, n_n4067, n_n4290, n_n3898, - n_n4122, n_n3774, n_n3014, n_n4241, n_n3952, n_n3237, n_n3968, n_n3922, - n_n3551, n_n3379, n_n4275, n_n3570, n_n3854, n_n4057, n_n3451, n_n4037, - n_n3408, n_n4229, n_n4201, n_n3339, n_n4362, n_n3483, n_n3557, n_n4185, - n_n3069, n_n3643, n_n3404, n_n3057, n_n3020, n_n3828, n_n3631, n_n3138, - nsr1_2, n_n4065, n_n3679, n_n3287, n_n4351, n_n4059, n_n3436, nen3_10, - n_n3461, n_n4012, n_n3051, n_n3073, n_n3777, n_n3709, n_n3946, n_n3085, - n_n3259, n_n3504, n_n4045, n_n3954, n_n3136, n_n4372, n_n4236, n_n3040, - n_n3874, n_n3999, n_n3223, ndn1_34, n_n3743, n_n3657, n_n3213, n_n3095, - n_n3663, n_n3724, n_n3038, n_n3370, n_n3624, n_n3578, n_n3713, n_n3089, - n_n3211, n_n3367, n_n3434, n_n3126, n_n4192, n_n4136, n_n3053, n_n3938, - n_n3769, n_n4390, nsr3_17, n_n3903, n_n3658, nrq3_11, n_n3818, n_n3533, - n_n3463, n_n3175, n_n3055, n_n3202, n_n3385, n_n4077, n_n3142, n_n3901, - n_n3934, n_n3823, n_n3722, n_n4309, n_n4159, n_n4330, n_n3836, n_n3470, - n_n3331, n_n3883, n_n4299, n_n4157, ndn3_9, n_n3208, n_n3190, n_n4029, - n_n3042, nsr3_14, n_n4151, n_n3188, n_n4303, n_n3250, n_n3170, n_n3758, - n_n3910, n_n3108, n_n3150, n_n4320, n_n4360, n_n4247, n_n4199, n_n3966, - n_n3766, n_n4021, n_n4062, n_n3514, n_n3572, n_n4166, n_n3976, n_n3394, - n_n4095, n_n3863, n_n3720, ngfdn_3, n_n3756, n_n3667, n_n3342, n_n3529, - n_n4209, n_n4324, n_n3337, n_n4227, n_n4153, n_n3831, n_n3233, n_n4263, - n_n3413, n_n4182, n_n3841, n_n3441, n_n4026, n_n4342, n_n4102, n_n3277, - n_n4180, n_n3878, n_n3931, n_n3845, n_n3865, n_n3486, n_n4056, n_n3674, - n_n3959, n_n3608, n_n4080, n_n4018, n_n4354, n_n3797, n_n3739, n_n3646, - n_n3099, n_n3537, n_n3806, n_n3087, n_n4105, n_n3262, n_n4125, n_n3814, - n_n4093, nsr3_3; - wire n1835, n1836, n1837, n1838_1, n1839, n1840, n1841, n1842, n1843_1, - n1844, n1845, n1846, n1847, n1848_1, n1849, n1850, n1851, n1852, - n1853_1, n1854, n1855, n1856, n1857, n1858_1, n1859, n1860, n1861, - n1862, n1863_1, n1864, n1865, n1866, n1867, n1868_1, n1869, n1870, - n1871, n1872, n1873_1, n1874, n1875, n1876, n1877, n1878_1, n1879, - n1880, n1881, n1882, n1883_1, n1884, n1885, n1886, n1887, n1888_1, - n1889, n1890, n1891, n1892, n1893_1, n1894, n1895, n1896, n1897, - n1898_1, n1899, n1900, n1901, n1902, n1903_1, n1904, n1905, n1906, - n1907, n1908_1, n1909, n1910, n1911, n1912, n1913_1, n1914, n1915, - n1916, n1917, n1918_1, n1919, n1920, n1921, n1922, n1923_1, n1924, - n1925, n1926, n1927, n1928_1, n1929, n1930, n1931, n1932, n1933_1, - n1934, n1935, n1936, n1937, n1938_1, n1939, n1940, n1941, n1942, - n1943_1, n1944, n1945, n1946, n1947, n1948_1, n1949, n1950, n1951, - n1952, n1953_1, n1954, n1955, n1956, n1957, n1958_1, n1959, n1960, - n1961, n1962, n1963_1, n1964, n1965, n1966, n1967, n1968_1, n1969, - n1970, n1971, n1972, n1973_1, n1974, n1975, n1976, n1977, n1978_1, - n1979, n1980, n1981, n1982, n1983_1, n1984, n1985, n1986, n1987, - n1988_1, n1989, n1990, n1991, n1992, n1993_1, n1994, n1995, n1996, - n1997, n1998_1, n1999, n2000, n2001, n2002, n2003_1, n2004, n2005, - n2006, n2007, n2008_1, n2009, n2010, n2011, n2012, n2013_1, n2014, - n2015, n2016, n2017, n2018_1, n2019, n2020, n2021, n2022, n2023_1, - n2024, n2025, n2026, n2027, n2028_1, n2029, n2030, n2031, n2032, - n2033_1, n2034, n2035, n2036, n2037, n2038_1, n2039, n2040, n2041, - n2042, n2043_1, n2044, n2045, n2046, n2047, n2048_1, n2049, n2050, - n2051, n2052, n2053_1, n2054, n2055, n2056, n2057, n2058_1, n2059, - n2060, n2061, n2062, n2063_1, n2064, n2065, n2066, n2067, n2068_1, - n2069, n2070, n2071, n2072, n2073_1, n2074, n2075, n2076, n2077, - n2078_1, n2079, n2080, n2081, n2082, n2083_1, n2084, n2085, n2086, - n2087, n2088_1, n2089, n2090, n2091, n2092, n2093_1, n2094, n2095, - n2096, n2097, n2098_1, n2099, n2100, n2101, n2102, n2103_1, n2104, - n2105, n2106, n2107, n2108_1, n2109, n2110, n2111, n2112, n2113_1, - n2114, n2115, n2116, n2117, n2118_1, n2119, n2120, n2121, n2122, - n2123_1, n2124, n2125, n2126, n2127, n2128_1, n2129, n2130, n2131, - n2132, n2133_1, n2134, n2135, n2136, n2137, n2138_1, n2139, n2140, - n2141, n2142, n2143_1, n2144, n2145, n2146, n2147, n2148_1, n2149, - n2150, n2151, n2152, n2153_1, n2154, n2155, n2156, n2157, n2158_1, - n2159, n2160, n2161, n2162, n2163_1, n2164, n2165, n2166, n2167, - n2168_1, n2169, n2170, n2171, n2172, n2173_1, n2174, n2175, n2176, - n2177, n2178_1, n2179, n2180, n2181, n2182, n2183_1, n2184, n2185, - n2186, n2187, n2188_1, n2189, n2190, n2191, n2192, n2193_1, n2194, - n2195, n2196, n2197, n2198_1, n2199, n2200, n2201, n2202, n2203_1, - n2204, n2205, n2206, n2207, n2208_1, n2209, n2210, n2211, n2212, - n2213_1, n2214, n2215, n2216, n2217, n2218_1, n2219, n2220, n2221, - n2222, n2223_1, n2224, n2225, n2226, n2227, n2228_1, n2229, n2230, - n2231, n2232, n2233_1, n2234, n2235, n2236, n2237, n2238_1, n2239, - n2240, n2241, n2242, n2243_1, n2244, n2245, n2246, n2247, n2248_1, - n2249, n2250, n2251, n2252, n2253_1, n2254, n2255, n2256, n2257, - n2258_1, n2259, n2260, n2261, n2262, n2263_1, n2264, n2265, n2266, - n2267, n2268_1, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, - n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, - n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, - n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, - n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, - n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, - n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, - n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, - n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, - n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, - n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n349, n354, - n359, n364, n369, n374, n379, n384, n389, n394, n399, n404, n409, n414, - n419, n424, n429, n434, n439, n444, n449, n454, n459, n464, n469, n474, - n479, n484, n489, n494, n499, n504, n509, n514, n519, n524, n529, n534, - n539, n544, n549, n554, n559, n564, n569, n574, n579, n584, n589, n594, - n599, n604, n609, n614, n619, n624, n629, n634, n639, n644, n649, n654, - n659, n664, n669, n674, n679, n684, n689, n694, n699, n704, n709, n714, - n719, n724, n729, n734, n739, n744, n749, n754, n759, n764, n769, n774, - n779, n784, n789, n794, n799, n804, n809, n814, n819, n824, n829, n834, - n839, n844, n849, n854, n859, n864, n869, n874, n879, n884, n889, n894, - n898, n903, n908, n913, n918, n923, n928, n933, n938, n943, n948, n953, - n958, n963, n968, n973, n978, n983, n988, n993, n998, n1003, n1008, - n1013, n1018, n1023, n1028, n1033, n1038, n1043, n1048, n1053, n1058, - n1063, n1068, n1073, n1078, n1083, n1088, n1093, n1098, n1103, n1108, - n1113, n1118, n1123, n1128, n1133, n1138, n1143, n1148, n1153, n1158, - n1163, n1168, n1173, n1178, n1183, n1188, n1193, n1198, n1203, n1208, - n1213, n1218, n1223, n1228, n1233, n1238, n1243, n1248, n1253, n1258, - n1263, n1268, n1273, n1278, n1283, n1288, n1293, n1298, n1303, n1308, - n1313, n1318, n1323, n1328, n1333, n1338, n1343, n1348, n1353, n1358, - n1363, n1368, n1373, n1378, n1383, n1388, n1393, n1398, n1403, n1408, - n1413, n1418, n1423, n1428, n1433, n1438, n1443, n1448, n1453, n1458, - n1463, n1468, n1473, n1478, n1483, n1488, n1493, n1498, n1503, n1508, - n1513, n1518, n1523, n1528, n1533, n1538, n1543, n1548, n1553, n1558, - n1563, n1568, n1573, n1578, n1583, n1588, n1593, n1598, n1603, n1608, - n1613, n1618, n1623, n1628, n1633, n1638, n1643, n1648, n1653, n1658, - n1663, n1668, n1673, n1678, n1683, n1688, n1693, n1698, n1703, n1708, - n1713, n1718, n1723, n1728, n1733, n1738, n1743, n1748, n1753, n1758, - n1763, n1768, n1773, n1778, n1783, n1788, n1793, n1798, n1803, n1808, - n1813, n1818, n1823, n1828, n1833, n1838, n1843, n1848, n1853, n1858, - n1863, n1868, n1873, n1878, n1883, n1888, n1893, n1898, n1903, n1908, - n1913, n1918, n1923, n1928, n1933, n1938, n1943, n1948, n1953, n1958, - n1963, n1968, n1973, n1978, n1983, n1988, n1993, n1998, n2003, n2008, - n2013, n2018, n2023, n2028, n2033, n2038, n2043, n2048, n2053, n2058, - n2063, n2068, n2073, n2078, n2083, n2088, n2093, n2098, n2103, n2108, - n2113, n2118, n2123, n2128, n2133, n2138, n2143, n2148, n2153, n2158, - n2163, n2168, n2173, n2178, n2183, n2188, n2193, n2198, n2203, n2208, - n2213, n2218, n2223, n2228, n2233, n2238, n2243, n2248, n2253, n2258, - n2263, n2268; - assign pv14_2_2_ = n_n3358 & n_n4153; - assign pv12_3_3_ = n_n3631 & n_n3367; - assign pv10_4_4_ = n_n3042 ? n_n4136 : tin_pv10_4_4_; - assign pv7_5_5_ = n_n3130 & n_n3679; - assign pv3_6_6_ = n_n3252 & n_n3057; - assign pv15_2_2_ = n_n3113 & n_n4037; - assign pv13_3_3_ = n_n3600 & n_n3404; - assign pv11_4_4_ = n_n4120 ? n_n3966 : tin_pv11_4_4_; - assign pv6_7_7_ = n_n4164 ? n_n3370 : tin_pv6_7_7_; - assign pv2_0_0_ = n_n3211 ? n_n3910 : tin_pv2_0_0_; - assign pv14_1_1_ = n_n3012 & n_n3038; - assign pv12_2_2_ = n_n3067 & n_n3576; - assign pv10_3_3_ = n_n4129 ? n_n3213 : tin_pv10_3_3_; - assign pv9_0_0_ = n_n3128 & n_n3890; - assign pv5_1_1_ = n_n3443 & n_n3287; - assign pv1_2_2_ = n_n3470 ? n_n3537 : tin_pv1_2_2_; - assign pv15_1_1_ = n_n3606 & n_n3108; - assign pv13_2_2_ = n_n3379 & n_n3463; - assign pv11_3_3_ = n_n3432 ? n_n3583 : tin_pv11_3_3_; - assign pv8_2_2_ = n_n3456 & n_n3055; - assign pv4_3_3_ = n_n3489 ? n_n4309 : tin_pv4_3_3_; - assign pv14_0_0_ = n_n3761 & n_n3903; - assign pv12_1_1_ = n_n3264 & n_n4390; - assign pv10_2_2_ = n_n3065 ? n_n3549 : tin_pv10_2_2_; - assign pv7_6_6_ = n_n3670 & n_n3617; - assign pv3_7_7_ = n_n3590 & n_n4102; - assign pv15_0_0_ = n_n4003 & n_n3188; - assign pv13_1_1_ = n_n3221 & n_n3150; - assign pv11_2_2_ = n_n3152 ? n_n3823 : tin_pv11_2_2_; - assign pv6_0_0_ = n_n3029 ? n_n3506 : tin_pv6_0_0_; - assign pv2_1_1_ = n_n3999 ? n_n3646 : tin_pv2_1_1_; - assign pv12_0_0_ = n_n3098 & n_n3339; - assign pv10_1_1_ = n_n3872 ? n_n3270 : tin_pv10_1_1_; - assign pv9_1_1_ = n_n3024 & n_n3044; - assign pv5_2_2_ = n_n4286 & n_n3350; - assign pv1_3_3_ = n_n3441 ? n_n4180 : tin_pv1_3_3_; - assign pv13_0_0_ = n_n3061 & n_n3434; - assign pv11_1_1_ = n_n4185 ? n_n4142 : tin_pv11_1_1_; - assign pv8_3_3_ = n_n3146 & n_n3091; - assign pv4_4_4_ = n_n4110 ? n_n3627 : tin_pv4_4_4_; - assign pready_0_0_ = n_n4108 ? n_n3354 : tin_pready_0_0_; - assign pv10_0_0_ = n_n4282 ? n_n4209 : tin_pv10_0_0_; - assign pv7_7_7_ = n_n3136 & n_n4077; - assign pv3_0_0_ = n_n3173 & n_n3828; - assign pv11_0_0_ = n_n3233 ? n_n3514 : tin_pv11_0_0_; - assign pv6_1_1_ = n_n3144 ? n_n3952 : tin_pv6_1_1_; - assign pv2_2_2_ = n_n4354 ? n_n3202 : tin_pv2_2_2_; - assign pv9_2_2_ = n_n3736 & n_n3157; - assign pv5_3_3_ = n_n3321 & n_n4236; - assign pv1_4_4_ = n_n3863 ? n_n3806 : tin_pv1_4_4_; - assign pv8_4_4_ = n_n3344 & n_n3095; - assign pv4_5_5_ = n_n3087 ? n_n3733 : tin_pv4_5_5_; - assign pv7_0_0_ = n_n3161 & n_n3069; - assign pv3_1_1_ = n_n3048 & n_n3461; - assign pv6_2_2_ = n_n3307 ? n_n3138 : tin_pv6_2_2_; - assign pv2_3_3_ = n_n3874 ? n_n3465 : tin_pv2_3_3_; - assign pv9_3_3_ = n_n3906 & n_n3749; - assign pv5_4_4_ = n_n3793 & n_n4213; - assign pv1_5_5_ = n_n3101 ? n_n3313 : tin_pv1_5_5_; - assign pv8_5_5_ = n_n3116 & n_n3331; - assign pv4_6_6_ = n_n3774 ? n_n3413 : tin_pv4_6_6_; - assign pv7_1_1_ = n_n3415 & n_n3971; - assign pv3_2_2_ = n_n3190 & n_n3739; - assign pv6_3_3_ = n_n3204 ? n_n3486 : tin_pv6_3_3_; - assign pv2_4_4_ = n_n3643 ? n_n3133 : tin_pv2_4_4_; - assign pv9_4_4_ = n_n3687 & n_n3650; - assign pv5_5_5_ = n_n3266 & n_n3408; - assign pv1_6_6_ = n_n4018 ? n_n3118 : tin_pv1_6_6_; - assign pv8_6_6_ = n_n3180 & n_n3223; - assign pv4_7_7_ = n_n4114 ? n_n4166 : tin_pv4_7_7_; - assign pv7_2_2_ = n_n3497 & n_n4105; - assign pv3_3_3_ = n_n3274 & n_n4342; - assign pv6_4_4_ = n_n3093 ? n_n4065 : tin_pv6_4_4_; - assign pv2_5_5_ = n_n4059 ? n_n3780 : tin_pv2_5_5_; - assign pv14_7_7_ = n_n3449 & n_n4241; - assign pv9_5_5_ = n_n3985 & n_n4290; - assign pv5_6_6_ = n_n3567 & n_n3237; - assign pv1_7_7_ = n_n3544 ? n_n4199 : tin_pv1_7_7_; - assign pv15_7_7_ = n_n3079 & n_n3648; - assign pv8_7_7_ = n_n3525 & n_n3529; - assign pv4_0_0_ = n_n3826 ? n_n3517 : tin_pv4_0_0_; - assign pv14_6_6_ = n_n3713 & n_n3262; - assign pv12_7_7_ = n_n3764 & n_n3720; - assign pv7_3_3_ = n_n3411 & n_n4303; - assign pv3_4_4_ = n_n3729 & n_n4162; - assign pv15_6_6_ = n_n4375 & n_n3020; - assign pv13_7_7_ = n_n3372 & n_n3394; - assign pv6_5_5_ = n_n3348 ? n_n4189 : tin_pv6_5_5_; - assign pv2_6_6_ = n_n3120 ? n_n3385 : tin_pv2_6_6_; - assign pv14_5_5_ = n_n3008 & n_n3663; - assign pv12_6_6_ = n_n3782 & n_n3896; - assign pv10_7_7_ = n_n3521 ? n_n3225 : tin_pv10_7_7_; - assign pv9_6_6_ = n_n4243 & n_n3239; - assign pv5_7_7_ = n_n3111 & n_n4005; - assign pv1_0_0_ = n_n3551 ? n_n4192 : tin_pv1_0_0_; - assign pv15_5_5_ = n_n3277 & n_n3674; - assign pv13_6_6_ = n_n3155 & n_n3797; - assign pv11_7_7_ = n_n3360 ? n_n3376 : tin_pv11_7_7_; - assign pv8_0_0_ = n_n3014 & n_n4320; - assign pv4_1_1_ = n_n4089 ? n_n3722 : tin_pv4_1_1_; - assign pv14_4_4_ = n_n3326 & n_n3089; - assign pv12_5_5_ = n_n3619 & n_n3337; - assign pv10_6_6_ = n_n3570 ? n_n3342 : tin_pv10_6_6_; - assign pv7_4_4_ = n_n3073 & n_n3053; - assign pv3_5_5_ = n_n3436 & n_n3142; - assign pv15_4_4_ = n_n3305 & n_n3667; - assign pv13_5_5_ = n_n4139 & n_n3777; - assign pv11_6_6_ = n_n3504 ? n_n4279 : tin_pv11_6_6_; - assign pv6_6_6_ = n_n3836 ? n_n3429 : tin_pv6_6_6_; - assign pv2_7_7_ = n_n4131 ? n_n3126 : tin_pv2_7_7_; - assign pv14_3_3_ = n_n3396 & n_n3316; - assign pv12_4_4_ = n_n3231 & n_n3175; - assign pv10_5_5_ = n_n3381 ? n_n4247 : tin_pv10_5_5_; - assign pv9_7_7_ = n_n3319 & n_n3040; - assign pv5_0_0_ = n_n3195 & n_n3572; - assign pv1_1_1_ = n_n3215 ? n_n3183 : tin_pv1_1_1_; - assign pv15_3_3_ = n_n4172 & n_n3051; - assign pv13_4_4_ = n_n3075 & n_n3758; - assign pv11_5_5_ = n_n3081 ? n_n3207 : tin_pv11_5_5_; - assign pv8_1_1_ = n_n3938 & n_n3883; - assign pv4_2_2_ = n_n4347 ? n_n4372 : tin_pv4_2_2_; - assign n349 = n2312 | (n_n3724 & ~n1922 & n2315); - assign n354 = (pv11_1_1_ & n1835) | n2311; - assign n359 = n2309 | n2307 | n2308; - assign n364 = n2306 | (n_n3035 & n_n4157 & n1839); - assign n369 = n2305 | n2303 | n2304; - assign n374 = ~preset & n1837; - assign n379 = ~preset & (n_n3144 | (~pdn & n1870)); - assign n384 = ~preset & (n_n3782 | (~pdn & n1870)); - assign n389 = ~preset & (n_n3067 | (~pdn & n1870)); - assign n394 = (pv10_3_3_ & n1838_1) | n2302; - assign n399 = (n_n4360 & n1839) | n2301; - assign n404 = ~preset & (n_n3180 | (~pdn & n1870)); - assign n409 = ~preset & (n_n3274 | (~pdn & n1870)); - assign n414 = n_n3475 ? (n1841 | (n1840 & n1990)) : (n1840 & ~n1990); - assign n419 = (n_n3458 & n1839) | n2300; - assign n424 = ~preset & (n_n3381 | (~pdn & n1870)); - assign n429 = n2299 | (n_n3688 & n_n3624 & n1839); - assign n434 = ~preset & n1842; - assign n439 = n2298 | (n_n3901 & n1839 & n1890); - assign n444 = n2297 | (n1839 & (~n_n3916 ^ n1930)); - assign n449 = (n1844 & n1845) | n2282; - assign n454 = (pv6_0_0_ & n1846) | n2281; - assign n459 = ~preset & (n_n3029 | (~pdn & n1870)); - assign n464 = ~preset & (n_n3619 | (~pdn & n1870)); - assign n469 = ~preset & (n_n3264 | (~pdn & n1870)); - assign n474 = n2280 | (n1839 & (n_n4288 | n2319)); - assign n479 = n1847 & ~preset & ~ngfdn_3; - assign n484 = ~preset & (n_n4114 | (~pdn & n1870)); - assign n489 = ~preset & (n_n3146 | (~pdn & n1870)); - assign n494 = (pv1_5_5_ & n1848_1) | n2279; - assign n499 = ~preset & (n_n3152 | (~pdn & n1870)); - assign n504 = preset | (n_n3833 & n1850) | (~n1849 & ~n1850); - assign n509 = ~preset & (n_n4282 | (~pdn & n1870)); - assign n514 = ~preset & (n_n3305 | (~pdn & n1870)); - assign n519 = n2278 | (n1851 & (~n1905 ^ n1978_1)); - assign n524 = (pv4_5_5_ & n1852) | n2277; - assign n529 = ~preset & (~n1983_1 | ~n1984) & n2331; - assign n534 = ~preset & (n_n3204 | (~pdn & n1870)); - assign n539 = ~preset & (n_n3024 | (~pdn & n1870)); - assign n544 = ~preset & (n_n4139 | (~pdn & n1870)); - assign n549 = ~ngfdn_3 & ~preset & ndn3_15; - assign n554 = n2274 | (n1839 & (n_n3458 | n2332)); - assign n559 = n2262 | (n2038 & (~n1909 ^ n1974)); - assign n564 = (n_n3743 & n1839) | n2261; - assign n569 = (pv1_2_2_ & n1848_1) | n2260; - assign n574 = ~preset & (n_n3456 | (~pdn & n1870)); - assign n579 = ~preset & (n_n3521 | (~pdn & n1870)); - assign n584 = ~preset & (n_n3081 | (~pdn & n1870)); - assign n589 = n2257 | (n1853_1 & (n2258_1 | n2336)); - assign n594 = n2256 | (n_n3475 & n1839 & n1890); - assign n599 = (pv11_2_2_ & n1835) | n2255; - assign n604 = n_n4045 & n2337 & (n1890 | ~n2335); - assign n609 = (n1844 & n1851) | n2254; - assign n614 = n2253_1 | (n1845 & (~n1909 ^ n1974)); - assign n619 = ~preset & (n_n3195 | (~pdn & n1870)); - assign n624 = (n_n3242 & n1839) | n2252; - assign n629 = (n_n3916 & n1839) | n2251; - assign n634 = (pv10_4_4_ & n1838_1) | n2250; - assign n639 = ~preset & ~ngfdn_3 & (ndn3_4 | ndn3_5); - assign n644 = (n_n3946 & n1839) | n2249; - assign n649 = ~preset & (n_n3489 | (~pdn & n1870)); - assign n654 = n2248_1 | (n_n3242 & n_n3170 & n1839); - assign n659 = (pv2_3_3_ & n1854) | n2247; - assign n664 = n2246 | preset | n1855; - assign n669 = (n_n4159 & n1839) | n2245; - assign n674 = (pv4_1_1_ & n1852) | n2244; - assign n679 = n2243_1 | (n1845 & (~n1905 ^ n1978_1)); - assign n684 = n2242 | (n_n3936 & n_n3099 & n1839); - assign n689 = (pv6_5_5_ & n1846) | n2241; - assign n694 = ~preset & (n_n3372 | (~pdn & n1870)); - assign n699 = (n_n4074 & n1839) | n2240; - assign n704 = n2239 | (n2038 & (n1972 ^ n1973_1)); - assign n709 = n2238_1 | (n1839 & (n_n4233 | n2338)); - assign n714 = n2237 | (n_n3035 & n_n4157 & n1839); - assign n719 = ~preset & (n_n3411 | (~pdn & n1870)); - assign n724 = n2236 | (n_n4074 & n_n3578 & n1839); - assign n729 = ~preset & (n_n3396 | (~pdn & n1870)); - assign n734 = ~preset & (n_n3432 | (~pdn & n1870)); - assign n739 = ~preset & (n_n3606 | (~pdn & n1870)); - assign n744 = (n_n4224 & n1839) | n2235; - assign n749 = (pv11_6_6_ & n1835) | n2234; - assign n754 = n2233_1 | n2231 | n2232; - assign n759 = ~preset & (n_n3120 | (~pdn & n1870)); - assign n764 = (n_n4222 & n1839) | n2230; - assign n769 = (n_n3976 & n1839) | n2229; - assign n774 = ~preset & (n1987 ? n_n3851 : n1953_1); - assign n779 = n2228_1 | (n1839 & (n_n3495 | n2341)); - assign n784 = n2212 | n2213_1; - assign n789 = n2211 | (n_n3556 & n_n4122 & n1839); - assign n794 = n2210 | (n_n3483 & ~n1922 & n2315); - assign n799 = ~preset & (n_n4089 | (~pdn & n1870)); - assign n804 = (n_n4392 & n1839) | n2209; - assign n809 = (n_n4330 & n1839) | n2208_1; - assign n814 = (pv11_5_5_ & n1835) | n2207; - assign n819 = n2206 | (n1839 & (~n_n3841 ^ n1901)); - assign n824 = ~preset & (n_n3321 | (~pdn & n1870)); - assign n829 = ~preset & (n_n3443 | (~pdn & n1870)); - assign n834 = ~preset & (n_n3215 | (~pdn & n1870)); - assign n839 = ~preset & ~ngfdn_3 & (ndn3_10 | nen3_10); - assign n844 = n2205 | (n1839 & (n_n4351 | n2346)); - assign n849 = n1859 & ~preset & ~pdn; - assign n854 = ~preset & (n_n3590 | (~pdn & n1870)); - assign n859 = ~preset & (n_n4110 | (~pdn & n1870)); - assign n864 = ~n1858_1 & (nlc3_3 | (n1956 & n2347)); - assign n869 = n2204 | (n_n4211 & n_n3657 & n1839); - assign n874 = ~preset & (n_n4129 | (~pdn & n1870)); - assign n879 = (n_n4071 & n1839) | n2203_1; - assign n884 = (n1839 & n1860) | n2202; - assign n889 = (pv4_2_2_ & n1852) | n2201; - assign n894 = n1870 & ~preset & ~pdn; - assign n898 = ~preset & (n_n3567 | (~pdn & n1870)); - assign n903 = (pv6_6_6_ & n1846) | n2200; - assign n908 = ~preset & (n_n3075 | (~pdn & n1870)); - assign n913 = n2199 | (~preset & ~pdn & n1870); - assign n918 = n2198_1 | (n1839 & (n_n4351 | n2346)); - assign n923 = ~preset & ~ngfdn_3 & (ndn3_5 | ndn3_6); - assign n928 = ~preset & (n_n3617 | (~pdn & n1870)); - assign n933 = ~preset & (n_n4162 | (~pdn & n1870)); - assign n938 = n2197 | (n_n4012 & ~n1922 & n2315); - assign n943 = ~preset & (n_n4120 | (~pdn & n1870)); - assign n948 = ~preset & (n_n3065 | (~pdn & n1870)); - assign n953 = ~preset & (n_n4005 | (~pdn & n1870)); - assign n958 = ~preset & (n_n3266 | (~pdn & n1870)); - assign n963 = (pv6_7_7_ & n1846) | n2196; - assign n968 = ~preset & (n_n3600 | (~pdn & n1870)); - assign n973 = ~preset & (n_n3415 | (~pdn & n1870)); - assign n978 = (n_n4095 & n1839) | n2195; - assign n983 = ~preset & (n_n3872 | (~pdn & n1870)); - assign n988 = ~preset & (n_n3648 | (~pdn & n1870)); - assign n993 = n2194 | (n_n4211 & n_n3657 & n1839); - assign n998 = ~preset & (n_n3350 | (~pdn & n1870)); - assign n1003 = ~preset & ~ngfdn_3 & (ndn3_6 | ndn3_7); - assign n1008 = ~preset & (n_n3116 | (~pdn & n1870)); - assign n1013 = n2193_1 | (n_n3766 & ~n1922 & n2315); - assign n1018 = (n_n4351 & n1839) | n2192; - assign n1023 = ~preset & (n_n4131 | (~pdn & n1870)); - assign n1028 = n2191 | (n_n3085 & n_n3250 & n1839); - assign n1033 = (n_n3976 & n1839) | n2190; - assign n1038 = (n_n4222 & n1839) | n2189; - assign n1043 = (pv1_4_4_ & n1848_1) | n2188_1; - assign n1048 = (pv1_6_6_ & n1848_1) | n2187; - assign n1053 = (n_n3608 & n1839) | n2186; - assign n1058 = n2185 | n2183_1 | n2184; - assign n1063 = ~preset & (n_n4213 | (~pdn & n1870)); - assign n1068 = n2182 | (n_n3688 & n_n3624 & n1839); - assign n1073 = ~preset & ~ngfdn_3 & (ndn3_7 | ndn3_8); - assign n1078 = ~preset & (n_n3252 | (~pdn & n1870)); - assign n1083 = n_n4366 ? (n1841 | (n1840 & n1991)) : (n1840 & ~n1991); - assign n1088 = (pv2_1_1_ & n1854) | n2181; - assign n1093 = n2180 | n2178_1 | n2179; - assign n1098 = ~preset & (n_n3348 | (~pdn & n1870)); - assign n1103 = ~preset & (n_n3544 | (~pdn & n1870)); - assign n1108 = ~preset & (n_n3101 | (~pdn & n1870)); - assign n1113 = n2177 | (n_n4334 & ~n1922 & n2315); - assign n1118 = n2176 | (n_n3556 & n_n4122 & n1839); - assign n1123 = (n_n3495 & n1839) | n2175; - assign n1128 = (pv4_6_6_ & n1852) | n2174; - assign n1133 = ~preset & (n_n3650 | (~pdn & n1870)); - assign n1138 = ~preset & (n_n3307 | (~pdn & n1870)); - assign n1143 = (pv1_3_3_ & n1848_1) | n2173_1; - assign n1148 = n_n4334 ? (n1872 | n2171) : n1862; - assign n1153 = n2169 | (n1853_1 & (n2170 | n2350)); - assign n1158 = ~preset & (n_n4164 | (~pdn & n1870)); - assign n1163 = (n_n4145 & n1839) | n2168_1; - assign n1168 = ~preset & (n_n3749 | (~pdn & n1870)); - assign n1173 = n2166 | n2167; - assign n1178 = ~preset & (n_n4347 | (~pdn & n1870)); - assign n1183 = ~preset & (n_n3826 | (~pdn & n1870)); - assign n1188 = ~preset & (n_n3360 | (~pdn & n1870)); - assign n1193 = n2165 | (n1851 & (~n1909 ^ n1974)); - assign n1198 = ~preset & (n_n3093 | (~pdn & n1870)); - assign n1203 = ~preset & (n_n3157 | (~pdn & n1870)); - assign n1208 = (n_n4349 & n1839) | n2164; - assign n1213 = ~preset & (n_n3161 | (~pdn & n1870)); - assign n1218 = (n_n4233 & n1839) | n2163_1; - assign n1223 = (n_n3892 & n1839) | n2162; - assign n1228 = n2161 | (n_n4125 & n1839 & n1890); - assign n1233 = n2160 | (n_n3242 & n_n3170 & n1839); - assign n1238 = (pv4_7_7_ & n1852) | n2159; - assign n1243 = (n1851 & n1863_1) | n2158_1; - assign n1248 = n2157 | (n_n3936 & n_n3099 & n1839); - assign n1253 = ~preset & (n_n3130 | (~pdn & n1870)); - assign n1258 = ~n1864 & ~preset & nsr4_2; - assign n1263 = n2156 | (~preset & n_n4047 & ~n1886); - assign n1268 = (pv2_2_2_ & n1854) | n2155; - assign n1273 = ~preset & (n_n3239 | (~pdn & n1870)); - assign n1278 = n2153_1 | n2154; - assign n1283 = ~preset & (n_n3890 | (~pdn & n1870)); - assign n1288 = n2152 | (n1839 & (n_n3608 | n2324)); - assign n1293 = (n_n3085 & n1839) | n2151; - assign n1298 = (n_n4288 & n1839) | n2150; - assign n1303 = ~preset & (n_n3326 | (~pdn & n1870)); - assign n1308 = n2147 | (n1853_1 & (n2149 | n2352)); - assign n1313 = pdn | preset | (nsr4_2 & n1864); - assign n1318 = n2145 | (n1853_1 & (n2146 | n2353)); - assign n1323 = ~preset & (n_n4375 | (~pdn & n1870)); - assign n1328 = n1865 & ~preset & ~n1855; - assign n1333 = ~preset & (n_n4290 | (~pdn & n1870)); - assign n1338 = (n1845 & n1863_1) | n2144; - assign n1343 = n2142 | n2143_1; - assign n1348 = ~preset & (n_n3774 | (~pdn & n1870)); - assign n1353 = ~preset & (n_n3014 | (~pdn & n1870)); - assign n1358 = ~preset & (n_n4241 | (~pdn & n1870)); - assign n1363 = (n_n4201 & n1839) | n2141; - assign n1368 = n2140 | (n1839 & (~n_n4145 ^ n1895)); - assign n1373 = (pv6_2_2_ & n1846) | n2139; - assign n1378 = (pv6_4_4_ & n1846) | n2138_1; - assign n1383 = ~preset & (n_n3551 | (~pdn & n1870)); - assign n1388 = ~preset & (n_n3379 | (~pdn & n1870)); - assign n1393 = (n_n4275 & n1868_1) | n2133_1; - assign n1398 = ~preset & (n_n3570 | (~pdn & n1870)); - assign n1403 = (pv2_5_5_ & n1854) | n2132; - assign n1408 = n2131 | n2358; - assign n1413 = (pv2_7_7_ & n1854) | n2130; - assign n1418 = ~preset & (n_n4037 | (~pdn & n1870)); - assign n1423 = n2129 | (n1839 & (~n_n3898 ^ n1896)); - assign n1428 = n2127 | n2128_1; - assign n1433 = (pv6_1_1_ & n1846) | n2126; - assign n1438 = ~preset & (n_n3339 | (~pdn & n1870)); - assign n1443 = (pv10_5_5_ & n1838_1) | n2125; - assign n1448 = n2123_1 | (n_n4334 & ~n_n3483 & n1862); - assign n1453 = ~preset & n2357 & (n_n4099 ^ n1967); - assign n1458 = ~preset & (n_n4185 | (~pdn & n1870)); - assign n1463 = n2122 | (n_n3934 & n1839 & n1890); - assign n1468 = ~preset & (n_n3643 | (~pdn & n1870)); - assign n1473 = (n_n4229 & n1839) | n2121; - assign n1478 = (n_n4145 & n1839) | n2120; - assign n1483 = n2119 | (n1839 & (n_n4095 | n2345)); - assign n1488 = ~preset & (n_n3828 | (~pdn & n1870)); - assign n1493 = n2118_1 | (n_n3085 & n_n3250 & n1839); - assign n1498 = (n_n3968 & n1839) | n2117; - assign n1503 = pdn | preset | (~ngfdn_3 & ~n1870); - assign n1508 = (n_n3922 & n1839) | n2116; - assign n1513 = n2115 | (n_n4366 & n1839 & n1890); - assign n1518 = (n1839 & n1871) | n2114; - assign n1523 = n2112 | n2113_1; - assign n1528 = ~preset & (n_n4059 | (~pdn & n1870)); - assign n1533 = (n_n3898 & n1839) | n2111; - assign n1538 = ~preset & ~ngfdn_3 & (nen3_10 | ndn3_9); - assign n1543 = ~preset & (n_n3461 | (~pdn & n1870)); - assign n1548 = (n_n4012 & n1872) | n2110; - assign n1553 = ~preset & (n_n3051 | (~pdn & n1870)); - assign n1558 = n2109 | (n_n4047 & n1839 & n1890); - assign n1563 = (n_n3898 & n1839) | n2108_1; - assign n1568 = n2359 & (n2107 | (n1878_1 & n2317)); - assign n1573 = (pv10_2_2_ & n1838_1) | n2106; - assign n1578 = n2104 | n2105; - assign n1583 = (pv1_7_7_ & n1848_1) | n2103_1; - assign n1588 = ~preset & (n_n3504 | (~pdn & n1870)); - assign n1593 = n2362 | (n_n4045 & (n2102 | n2361)); - assign n1598 = ~n2100 & (~n1853_1 | (~n2101 & ~n2363)); - assign n1603 = n2099 | (n_n4324 & n1839 & n1890); - assign n1608 = (n_n4383 & n1839) | n2098_1; - assign n1613 = n2097 | (n1839 & (~n_n4229 ^ n1902)); - assign n1618 = ~preset & (n_n3040 | (~pdn & n1870)); - assign n1623 = ~preset & (n_n3874 | (~pdn & n1870)); - assign n1628 = ~preset & (n_n3999 | (~pdn & n1870)); - assign n1633 = (n_n4122 & n1839) | n2096; - assign n1638 = ndn1_34 & ~preset & ~pdn; - assign n1643 = (pv10_1_1_ & n1838_1) | n2095; - assign n1648 = (n2038 & n1844) | n2094; - assign n1653 = (n_n4258 & n1839) | n2093_1; - assign n1658 = ~preset & (n_n3095 | (~pdn & n1870)); - assign n1663 = ~preset & (n_n3663 | (~pdn & n1870)); - assign n1668 = n_n3724 ? n1874 : (n_n3814 & n1836); - assign n1673 = ~preset & (n_n3038 | (~pdn & n1870)); - assign n1678 = (n_n4337 & n1839) | n2092; - assign n1683 = (pv11_0_0_ & n1835) | n2091; - assign n1688 = (pv11_4_4_ & n1835) | n2090; - assign n1693 = n2089 | (n_n3556 & n_n4122 & n1839); - assign n1698 = n2088_1 | (n_n4074 & n_n3578 & n1839); - assign n1703 = ~preset & (n_n3211 | (~pdn & n1870)); - assign n1708 = ~preset & (n_n3367 | (~pdn & n1870)); - assign n1713 = ~preset & (n_n3434 | (~pdn & n1870)); - assign n1718 = n2087 | (n1839 & (n_n4233 | n2338)); - assign n1723 = n2086 | (n_n3688 & n_n3624 & n1839); - assign n1728 = (n_n3876 & n1839) | n2085; - assign n1733 = ~preset & (n_n3053 | (~pdn & n1870)); - assign n1738 = ~preset & (n_n3938 | (~pdn & n1870)); - assign n1743 = n2084 | (~preset & n_n3769 & ~n1886); - assign n1748 = n2083_1 | (n_n3936 & n_n3099 & n1839); - assign n1753 = n1858_1 | (nsr3_17 & (~nen3_10 | ~n1855)); - assign n1758 = ~preset & (n_n3903 | (~pdn & n1870)); - assign n1763 = n2364 & (n_n3658 | (n1890 & n2322)); - assign n1768 = ~preset & ~ngfdn_3 & (nrq3_11 | ~nsr3_14); - assign n1773 = n2082 | n2080 | n2081; - assign n1778 = (pv6_3_3_ & n1846) | n2079; - assign n1783 = (n_n4316 & n1839) | n2078_1; - assign n1788 = ~preset & (n_n3175 | (~pdn & n1870)); - assign n1793 = (n_n3657 & n1839) | n2077; - assign n1798 = n2076 | (n1839 & (n_n3495 | n2341)); - assign n1803 = n2075 | (n1839 & (n_n4095 | n2345)); - assign n1808 = ~preset & (n_n4077 | (~pdn & n1870)); - assign n1813 = ~preset & (n_n3142 | (~pdn & n1870)); - assign n1818 = n2074 | (~preset & n_n3901 & ~n1886); - assign n1823 = n2072 | (~n_n3934 & n_n3976 & n1840); - assign n1828 = n2071 | (n_n4227 & ~n1922 & n2315); - assign n1833 = (n_n4160 & n1839) | n2070; - assign n1838 = (n_n4182 & n1839) | n2069; - assign n1843 = (pv4_0_0_ & n1852) | n2068_1; - assign n1848 = (pv4_4_4_ & n1852) | n2067; - assign n1853 = ~preset & (n_n3836 | (~pdn & n1870)); - assign n1858 = ~preset & (n_n3470 | (~pdn & n1870)); - assign n1863 = (n_n4157 & n1839) | n2066; - assign n1868 = (n_n3099 & n1839) | n2065; - assign n1873 = (pv10_6_6_ & n1838_1) | n2064; - assign n1878 = (n2038 & n1863_1) | n2063_1; - assign n1883 = ~preset & ~ngfdn_3 & (ndn3_8 | ndn3_9); - assign n1888 = (pv1_1_1_ & n1848_1) | n2062; - assign n1893 = ~preset & (n_n3190 | (~pdn & n1870)); - assign n1898 = n2060 | (n1853_1 & (n2061 | n2365)); - assign n1903 = ~preset & (n_n3042 | (~pdn & n1870)); - assign n1908 = n2059 | preset | pdn; - assign n1913 = n2058_1 | preset | n2057; - assign n1918 = ~preset & (n_n3188 | (~pdn & n1870)); - assign n1923 = n2056 | (n_n3769 & n1839 & n1890); - assign n1928 = (pv11_3_3_ & n1835) | n2055; - assign n1933 = (pv11_7_7_ & n1835) | n2054; - assign n1938 = (n_n3916 & n1839) | n2053_1; - assign n1943 = n2052 | (n1839 & (n_n3608 | n2324)); - assign n1948 = n2051 | (n1839 & (n_n4392 | n2339)); - assign n1953 = ~preset & (n_n3150 | (~pdn & n1870)); - assign n1958 = (n_n3688 & n1839) | n2050; - assign n1963 = (pv10_7_7_ & n1838_1) | n2049; - assign n1968 = (n_n4362 & n1839) | n2048_1; - assign n1973 = n2047 | (n_n3242 & n_n3170 & n1839); - assign n1978 = n2046 | (n_n4275 & ~n1922 & n2315); - assign n1983 = n2045 | (n1836 & n2366); - assign n1988 = (pv2_4_4_ & n1854) | n2044; - assign n1993 = (pv2_6_6_ & n1854) | n2043_1; - assign n1998 = n2042 | (n_n3814 & ~n1922 & n2315); - assign n2003 = n2041 | (n1839 & (~n_n4159 ^ ~n_n3976)); - assign n2008 = (n_n4270 & n1839) | n2040; - assign n2013 = n2039 | (n1845 & (n1972 ^ n1973_1)); - assign n2018 = (n_n3841 & n1839) | n2038_1; - assign n2023 = n2036 | n2037; - assign n2028 = ~preset & (n_n3863 | (~pdn & n1870)); - assign n2033 = ~preset & (n_n3720 | (~pdn & n1870)); - assign n2038 = ~ngfdn_3 & ~preset & nrq3_11; - assign n2043 = (pv10_0_0_ & n1838_1) | n2035; - assign n2048 = n2034 | (n1839 & (n_n3458 | n2332)); - assign n2053 = (n_n4299 & n1839) | n2033_1; - assign n2058 = ~preset & (n_n3529 | (~pdn & n1870)); - assign n2063 = (n_n3756 & n1839) | n2032; - assign n2068 = n_n4324 ? (n1841 | (n1840 & n1994)) : (n1840 & ~n1994); - assign n2073 = n2031 | (n_n3035 & n_n4157 & n1839); - assign n2078 = n2030 | (n_n4227 & (n1874 | n2136)); - assign n2083 = ~preset & (n_n4153 | (~pdn & n1870)); - assign n2088 = n2029 | n2368; - assign n2093 = ~preset & (n_n3233 | (~pdn & n1870)); - assign n2098 = ~preset & n1881; - assign n2103 = (n_n4251 & n1839) | n2028_1; - assign n2108 = (pv4_3_3_ & n1852) | n2027; - assign n2113 = n2025 | n2026; - assign n2118 = ~preset & (n_n3441 | (~pdn & n1870)); - assign n2123 = ~preset & ~n1855 & (n_n4026 | n2024); - assign n2128 = (n_n4229 & n1839) | n2023_1; - assign n2133 = (n_n3841 & n1839) | n2022; - assign n2138 = n2021 | (n1839 & (n_n4288 | n2319)); - assign n2143 = n2020 | (n_n3085 & n_n3250 & n1839); - assign n2148 = (pv1_0_0_ & n1848_1) | n2019; - assign n2153 = (pv2_0_0_ & n1854) | n2018_1; - assign n2158 = n2016 | (n1853_1 & (n2017 | n2369)); - assign n2163 = n2014 | (n1853_1 & (n2015 | n2370)); - assign n2168 = (n_n3533 & n1839) | n2013_1; - assign n2173 = n1882 & ~preset & n_n4057; - assign n2178 = ~preset & (n_n3674 | (~pdn & n1870)); - assign n2183 = n2011 | (n_n3959 & n1884) | n2010; - assign n2188 = n2009 | (n1851 & (n1972 ^ n1973_1)); - assign n2193 = n2008_1 | n2006 | n2007; - assign n2198 = ~preset & (n_n4018 | (~pdn & n1870)); - assign n2203 = ~preset & (n_n4354 | (~pdn & n1870)); - assign n2208 = ~preset & (n_n3797 | (~pdn & n1870)); - assign n2213 = (n_n4316 & n1839) | n2005; - assign n2218 = n2004 | (n1839 & (n_n4392 | n2339)); - assign n2223 = n2003_1 | (n2038 & (~n1905 ^ n1978_1)); - assign n2228 = n2002 | (n_n4211 & n_n3657 & n1839); - assign n2233 = n2001 | (n_n4074 & n_n3578 & n1839); - assign n2238 = ~preset & (n_n3087 | (~pdn & n1870)); - assign n2243 = ~preset & (n_n4105 | (~pdn & n1870)); - assign n2248 = ~preset & (n_n3262 | (~pdn & n1870)); - assign n2253 = (n1886 & n2371) | (~preset & n_n4125 & ~n1886); - assign n2258 = n2000 | (~n_n3814 & n1836); - assign n2263 = ~n2374 | (~n1997 & (~n1878_1 | ~n2372)); - assign n2268 = n1858_1 | (nsr3_3 & (~n1956 | n1996)); - assign n1835 = ~ndn3_9 & ~preset & ndn3_8; - assign n1836 = n_n3709 & n_n3707 & ~preset & ~n_n3198; - assign n1837 = (~n_n3658 & (n1892 ? n2322 : n_n3604)) | (n_n3604 & (n_n3658 | ~n2322)); - assign n1838_1 = ~ndn3_8 & ~preset & ndn3_7; - assign n1839 = ~n1889 & ~nsr1_2 & ~preset & ~pdn; - assign n1840 = n_n4056 & ~n_n3557 & ~preset & n_n4057; - assign n1841 = ~preset & ~n1886; - assign n1842 = n_n4108 | (pdn & ~ndn1_34) | (~pdn & n1870); - assign n1843_1 = ~n_n3916 ^ n1930; - assign n1844 = n1979 ? ((n1906 & ~n1971) | (n1905 & (n1906 | ~n1971))) : ((~n1906 & n1971) | (~n1905 & (~n1906 | n1971))); - assign n1845 = nen3_10 & ~preset & ~ndn3_10; - assign n1846 = ~ndn3_7 & ~preset & ndn3_6; - assign n1847 = ~nsr3_3 | ndn3_4 | (pready_0_0_ & n1956); - assign n1848_1 = n2328 & (~nsr3_3 | (pready_0_0_ & n1956)); - assign n1849 = (n1857 & n1977) | (~n_n4360 & ((n1857 & n1960) | n1977)); - assign n1850 = n1897 | ~n2316 | n_n4067 | (~n_n4067 & n1922); - assign n1851 = ngfdn_3 & ~preset & ~ndn3_15; - assign n1852 = ~ndn3_6 & ~preset & ndn3_5; - assign n1853_1 = ~preset & (n1886 | n1900); - assign n1854 = ~ndn3_5 & ~preset & ndn3_4; - assign n1855 = ~n_n4093 | (n1903_1 & (n1897 | n2310)); - assign n1856 = ((~n_n3916 ^ n_n4040) & (~n1913_1 ^ ~n1930)) | ((~n_n3916 ^ ~n_n4040) & (n1913_1 ^ ~n1930)); - assign n1857 = ~n_n3841 ^ n1901; - assign n1858_1 = preset | pdn; - assign n1859 = nlc1_2 | (~preset_0_0_ & nsr1_2 & (~nlc1_2 | n_n4151)); - assign n1860 = n_n4316 ? (~n1938_1 ^ n1959) : (n1938_1 ^ n1959); - assign n1861 = ((~n_n3988 ^ n_n3898) & (~n1896 ^ ~n1914)) | ((~n_n3988 ^ ~n_n3898) & (n1896 ^ ~n1914)); - assign n1862 = n2349 & n_n4012 & n1836 & n1867; - assign n1863_1 = n1912 ? ((n1910 & n1911) | (n1909 & (n1910 | n1911))) : ((~n1910 & ~n1911) | (~n1909 & (~n1910 | ~n1911))); - assign n1864 = 1'b1; - assign n1865 = n_n4067 | (~n1897 & ~n1922 & n2316); - assign n1866 = ~n_n4145 ^ n1895; - assign n1867 = n_n3724 & n_n4227 & n_n3814; - assign n1868_1 = n1874 | n2134 | n2135 | n2136; - assign n1869 = ~n_n3898 ^ n1896; - assign n1870 = ~nsr1_2 | (preset_0_0_ & ~nlc1_2) | (nlc1_2 & ~n_n4151); - assign n1871 = ((~n_n4160 ^ ~n_n4222) & (~n_n4159 | (n_n4159 & n_n3976))) | (n_n4159 & ~n_n3976 & (~n_n4160 ^ n_n4222)); - assign n1872 = n2172 | (n2318 & (~n1878_1 | ~n2317)); - assign n1873_1 = ~n_n4229 ^ n1902; - assign n1874 = n2137 | (n2318 & (~n1878_1 | ~n2317)); - assign n1875 = ((~n_n4229 ^ n_n3818) & (~n1902 ^ ~n1944)) | ((~n_n4229 ^ ~n_n3818) & (n1902 ^ ~n1944)); - assign n1876 = ~n_n4159 ^ ~n_n3976; - assign n1877 = nrq3_11 & ~ngfdn_3; - assign n1878_1 = n2316 & ~n1897 & ~n2310; - assign n1879 = n_n3831 & ((n_n3851 & (n_n4026 | n1953_1)) | (~n_n4026 & n1953_1)); - assign n1880 = ~n2331 | ~n_n3709 | (n1983_1 & n1984); - assign n1881 = n_n4263 | (~nlc3_3 & n1956 & n2347); - assign n1882 = n1899 | (n_n4056 & (n1950 | ~n2357)); - assign n1883_1 = n_n3959 | (n_n4159 & n_n3976) | (~n_n4159 & ~n_n3976); - assign n1884 = n2012 | (n2318 & (~n1878_1 | ~n2317)); - assign n1885 = ((~n_n4145 ^ n_n4080) & (~n1895 ^ ~n1907)) | ((~n_n4145 ^ ~n_n4080) & (n1895 ^ ~n1907)); - assign n1886 = n_n4056 ? n2323 : (n1890 & n2322); - assign n1887 = (n_n3934 & n_n3976 & (n_n4222 ^ ~n_n4125)) | ((~n_n3934 | ~n_n3976) & (n_n4222 ^ n_n4125)); - assign n1888_1 = n_n4159 | n_n4160 | n_n4383; - assign n1889 = nlc1_2 ? ~n_n4151 : preset_0_0_; - assign n1890 = n_n3658 ? n_n3604 : (n2320 | n2321); - assign n1891 = n_n3955 | ~n_n3954 | n_n4029 | n_n3845; - assign n1892 = n2320 | n2321; - assign n1893_1 = (~n1856 & n1955) | (n1843_1 & (n1955 | (~n1856 & n1942))); - assign n1894 = (n1869 & n1893_1) | (~n1861 & (n1893_1 | (n1869 & n1968_1))); - assign n1895 = n1931 ? ((n_n3898 & (n1932 | n1933_1)) | (n1932 & n1933_1)) : ((~n1932 & ~n1933_1) | (~n_n3898 & (~n1932 | ~n1933_1))); - assign n1896 = n1932 ? ((n_n3916 & (n1962 | n1975)) | (n1962 & n1975)) : ((~n1962 & ~n1975) | (~n_n3916 & (~n1962 | ~n1975))); - assign n1897 = n_n4067 ? ~n_n3833 : n1849; - assign n1898_1 = n_n4056 & n_n4057 & ~n_n3557; - assign n1899 = n2322 & ~n_n4056 & n1890; - assign n1900 = ~n_n3493 & (~n_n4045 | (~n1890 & n2335)); - assign n1901 = n1947 ? ((n1931 & n1934) | (n_n4145 & (n1931 | n1934))) : ((~n1931 & ~n1934) | (~n_n4145 & (~n1931 | ~n1934))); - assign n1902 = n1927 ? ((n_n4316 & (n1938_1 | n1959)) | (n1938_1 & n1959)) : ((~n1938_1 & ~n1959) | (~n_n4316 & (~n1938_1 | ~n1959))); - assign n1903_1 = nen3_10 & nsr3_17; - assign n1904 = ~ndn3_15 & ngfdn_3; - assign n1905 = n2296 | n2294 | n2295; - assign n1906 = n2325 | (nrq3_11 & ~ngfdn_3 & n1871); - assign n1907 = (n_n3988 & n1914) | ((n_n3988 | n1914) & (n_n3898 ^ n1896)); - assign n1908_1 = (n_n4080 & n1907) | ((n_n4080 | n1907) & (~n_n4145 ^ ~n1895)); - assign n1909 = (n1957 & n1958_1) | ((n1957 | n1958_1) & (n2272 | n2273)); - assign n1910 = n2334 | (n1877 & (~n_n3916 ^ n1930)); - assign n1911 = n2265 | n2263_1 | n2264; - assign n1912 = (~n1918_1 & ~n2221 & ~n2222 & ~n2223_1) | (n1918_1 & (n2221 | n2222 | n2223_1)); - assign n1913_1 = (n_n3818 & n1944) | ((n_n3818 | n1944) & (~n_n4229 ^ ~n1902)); - assign n1914 = (n_n4040 & n1913_1) | ((n_n4040 | n1913_1) & (n_n3916 ^ n1930)); - assign n1915 = n2287 | n2285 | n2286; - assign n1916 = n2327 | n1915 | n2284; - assign n1917 = ~n_n3865 ^ n1891; - assign n1918_1 = n2343 | (n1877 & (~n_n3898 ^ n1896)); - assign n1919 = n_n3709 & ~n_n3198 & n_n3707; - assign n1920 = n2342 | (n1877 & (~n_n3841 ^ n1901)); - assign n1921 = n2226 | n2224 | n2225; - assign n1922 = n_n4026 ? ~n_n3851 : ~n1953_1; - assign n1923_1 = (n_n4047 & n1929) | (n_n3916 & (n_n4047 | n1929)); - assign n1924 = (n_n3898 & n1923_1) | (n_n4366 & (n_n3898 | n1923_1)); - assign n1925 = (n1843_1 & n1964) | (~n_n3876 & (n1964 | (n1843_1 & n1981))); - assign n1926 = (n1869 & n1925) | (~n_n4362 & (n1925 | (n1869 & n1965))); - assign n1927 = (~n_n4182 & (n_n4160 | n_n4383 | n_n4159)) | (~n_n4160 & ~n_n4383 & ~n_n4159 & n_n4182); - assign n1928_1 = (~n1940 & ~n2214 & ~n2215 & ~n2216) | (n1940 & (n2214 | n2215 | n2216)); - assign n1929 = (n_n3769 & n1976) | (n_n4229 & (n_n3769 | n1976)); - assign n1930 = n1962 ? ((n1927 & n1982) | (n_n4229 & (n1927 | n1982))) : ((~n1927 & ~n1982) | (~n_n4229 & (~n1927 | ~n1982))); - assign n1931 = (~n_n4251 & (n_n4224 | n1888_1 | ~n2314)) | (~n_n4224 & n_n4251 & ~n1888_1 & n2314); - assign n1932 = (~n_n4224 & (n_n4330 | n_n4182 | n1888_1)) | (n_n4224 & ~n_n4330 & ~n_n4182 & ~n1888_1); - assign n1933_1 = (n_n3916 & n1975) | ((n_n3916 | n1975) & (n_n4330 ^ n1961)); - assign n1934 = (n1932 & n1933_1) | (n_n3898 & (n1932 | n1933_1)); - assign n1935 = (n_n4222 & ((n_n3934 & n_n3976) | n_n4125)) | (n_n3934 & n_n3976 & n_n4125); - assign n1936 = (n_n3574 & (n_n3959 ? ~n1871 : (n1871 & n1876))) | (~n1871 & (~n_n3959 | ~n1876)) | (~n_n3574 & n1871 & ~n1876); - assign n1937 = n1983_1 & (~n1857 | (n1857 & (~n_n3726 ^ ~n1908_1))); - assign n1938_1 = (~n_n4160 & n_n4383 & ~n_n4159) | (~n_n4383 & (n_n4160 | n_n4159)); - assign n1939 = n1918_1 | n2221 | n2222 | n2223_1; - assign n1940 = n2344 | (n1877 & (~n_n4145 ^ n1895)); - assign n1941 = (n_n3995 & (n1860 ? (n1936 & ~n1943_1) : (~n1936 & n1943_1))) | (~n1860 & n1936) | (~n_n3995 & (n1860 ? (n1936 & n1943_1) : (~n1936 & ~n1943_1))); - assign n1942 = (n1875 & n1941) | (~n1873_1 & (n1941 | (n1875 & n1954))); - assign n1943_1 = (~n1871 & n1883_1) | (n_n3574 & (~n1871 | n1883_1)); - assign n1944 = (~n1860 & n1943_1) | (n_n3995 & (~n1860 | n1943_1)); - assign n1945 = (~n_n4381 & ~n_n4052 & ~n_n3865 & ~n1891) | (n_n4381 & (n_n4052 | n_n3865 | n1891)); - assign n1946 = n_n4224 | n_n4251 | n1888_1 | ~n2314; - assign n1947 = ~n_n4270 ^ ~n1946; - assign n1948_1 = (~n_n3955 & n_n3954 & ~n_n4029 & ~n_n3845) | (n_n4029 & (n_n3955 | ~n_n3954 | n_n3845)); - assign n1949 = (~n_n3955 & n_n3954 & ~n_n3845) | (n_n3845 & (n_n3955 | ~n_n3954)); - assign n1950 = ~n_n4099 ^ n1967; - assign n1951 = n_n4052 ^ (n_n3865 | n1891); - assign n1952 = ~n1957 ^ (n2268_1 | n2333); - assign n1953_1 = (~n1857 & n1960) | (n_n4360 & (n1960 | (~n1857 & n1977))); - assign n1954 = (n_n3995 & (n1860 ? (n1936 & n1943_1) : (~n1936 & ~n1943_1))) | (n1860 & ~n1936) | (~n_n3995 & (n1860 ? (n1936 & ~n1943_1) : (~n1936 & n1943_1))); - assign n1955 = (~n1875 & n1954) | (n1873_1 & (n1954 | (~n1875 & n1941))); - assign n1956 = nsr1_2 & ((nlc1_2 & n_n4151) | (~preset_0_0_ & (~nlc1_2 | n_n4151))); - assign n1957 = n2271 | n2269 | n2270; - assign n1958_1 = n2333 | (n1877 & (~n_n4229 ^ n1902)); - assign n1959 = (n_n4159 & ((n_n4222 & n_n3976) | (~n_n4160 & (n_n4222 | n_n3976)))) | (n_n4160 & n_n4222 & ~n_n4159); - assign n1960 = (~n1866 & n1966) | (n_n4299 & (n1966 | (~n1866 & n1926))); - assign n1961 = n_n4160 | n_n4383 | n_n4159 | n_n4182; - assign n1962 = ~n_n4330 ^ ~n1961; - assign n1963_1 = (n1860 & n1985) | (~n_n3946 & (n1985 | (n1860 & ~n1985))); - assign n1964 = (n1873_1 & n1963_1) | (~n_n4258 & (n1963_1 | (n1873_1 & n1980))); - assign n1965 = (~n1843_1 & n1981) | (n_n3876 & (n1981 | (~n1843_1 & n1964))); - assign n1966 = (~n1869 & n1965) | (n_n4362 & (n1965 | (~n1869 & n1925))); - assign n1967 = n_n4381 | n_n4052 | n_n3865 | n1891; - assign n1968_1 = (n1856 & n1942) | (~n1843_1 & (n1942 | (n1856 & n1955))); - assign n1969 = (~n1869 & n1968_1) | (n1861 & (n1968_1 | (~n1869 & n1893_1))); - assign n1970 = n2216 | n2214 | n2215; - assign n1971 = ~n1973_1 | (~n2289 & ~n2290 & ~n2291); - assign n1972 = n2291 | n2289 | n2290; - assign n1973_1 = n2326 | (n_n3934 & n1890 & n1904); - assign n1974 = (~n1910 & ~n2263_1 & ~n2264 & ~n2265) | (n1910 & (n2263_1 | n2264 | n2265)); - assign n1975 = (n1927 & n1982) | (n_n4229 & (n1927 | n1982)); - assign n1976 = (n_n3901 & n1935) | (n_n4316 & (n_n3901 | n1935)); - assign n1977 = (n1866 & n1926) | (~n_n4299 & (n1926 | (n1866 & n1966))); - assign n1978_1 = (n1972 & n1973_1 & (n2293 | n2325)) | (~n2293 & (~n1972 | ~n1973_1) & ~n2325); - assign n1979 = ~n1915 ^ (n2284 | n2327); - assign n1980 = (~n1860 & ~n1985) | (n_n3946 & (~n1985 | (~n1860 & n1985))); - assign n1981 = (~n1873_1 & n1980) | (n_n4258 & (n1980 | (~n1873_1 & n1963_1))); - assign n1982 = (n1938_1 & n1959) | (n_n4316 & (n1938_1 | n1959)); - assign n1983_1 = (n1885 & n1969) | (~n1866 & ((n1885 & n1894) | n1969)); - assign n1984 = (~n_n3841 & n1901) | (n_n3841 & ~n1901) | ((~n_n3841 ^ n1901) & (n_n3726 ^ n1908_1)); - assign n1985 = (n1871 & n2313) | (~n_n3743 & (n1871 | n2313)); - assign n1986 = (~n1970 & ~n2218_1 & ~n2219) | (~n1940 & (~n1970 | (~n2218_1 & ~n2219))); - assign n1987 = n1897 | n2310 | ~n2316 | n2340; - assign n1988_1 = ndn3_4 | (nsr3_3 & (~pready_0_0_ | ~n1956)); - assign n1989 = n1890 & ~n_n3493 & ~n_n4045; - assign n1990 = n_n4145 ? ((n_n4366 & (n_n3898 | n1923_1)) | (n_n3898 & n1923_1)) : ((~n_n3898 & ~n1923_1) | (~n_n4366 & (~n_n3898 | ~n1923_1))); - assign n1991 = n_n3898 ? ((n_n4047 & n1929) | (n_n3916 & (n_n4047 | n1929))) : ((~n_n4047 & ~n1929) | (~n_n3916 & (~n_n4047 | ~n1929))); - assign n1992 = n_n4047 ? ((n_n3769 & n1976) | (n_n4229 & (n_n3769 | n1976))) : ((~n_n3769 & ~n1976) | (~n_n4229 & (~n_n3769 | ~n1976))); - assign n1993_1 = n_n3769 ? ((n_n4316 & (n_n3901 | n1935)) | (n_n3901 & n1935)) : ((~n_n3901 & ~n1935) | (~n_n4316 & (~n_n3901 | ~n1935))); - assign n1994 = n_n3841 ? ((n_n4145 & n1924) | (n_n3475 & (n_n4145 | n1924))) : ((~n_n4145 & ~n1924) | (~n_n3475 & (~n_n4145 | ~n1924))); - assign n1995 = ~n_n3707 | (~n_n4026 & ~n1953_1) | (~n_n3851 & n_n4026); - assign n1996 = nsr4_2 & ((n_n4108 & ~n_n3354) | (~tin_pready_0_0_ & (~n_n4108 | ~n_n3354))); - assign n1997 = ~preset & (~n_n3831 | n1998_1 | n1999); - assign n1998_1 = n2373 & n2316 & ~n1897 & ~n2310; - assign n1999 = n2316 & ~n2310 & ~n1897 & n1995; - assign n2000 = n_n3814 & (~n1878_1 | ~n2317) & n2318; - assign n2001 = ~preset & n_n3806 & (pdn | ~n1870); - assign n2002 = ~preset & n_n3537 & (pdn | ~n1870); - assign n2003_1 = ~preset & n_n3099 & (~nrq3_11 | ngfdn_3); - assign n2004 = ~preset & n_n3646 & (pdn | ~n1870); - assign n2005 = ~preset & n_n3739 & (pdn | ~n1870); - assign n2006 = n2317 & n1878_1 & ~preset & n_n4299; - assign n2007 = n_n4080 & (~n1878_1 | ~n2317) & n2318; - assign n2008_1 = n1836 & (n_n4080 ? (~n1866 ^ ~n1907) : (n1866 ^ ~n1907)); - assign n2009 = ~preset & n_n3608 & (ndn3_15 | ~ngfdn_3); - assign n2010 = n2317 & n1878_1 & ~preset & n_n3756; - assign n2011 = ~n_n3959 & n1836 & (~n_n4159 ^ ~n_n3976); - assign n2012 = n1836 & (~n_n4159 ^ n_n3976); - assign n2013_1 = ~preset & n_n3486 & (pdn | ~n1870); - assign n2014 = ~n1900 & ~n1886 & ~preset & n_n3865; - assign n2015 = n_n3922 & (n1899 | n2259); - assign n2016 = ~n1900 & ~n1886 & ~preset & n_n3845; - assign n2017 = n_n3968 & (n1899 | n2259); - assign n2018_1 = ~preset & n_n3931 & (~ndn3_4 | ndn3_5); - assign n2019 = n1988_1 & ~preset & n_n3878; - assign n2020 = ~preset & n_n4180 & (pdn | ~n1870); - assign n2021 = ~preset & n_n3277 & (pdn | ~n1870); - assign n2022 = ~preset & n_n4102 & (pdn | ~n1870); - assign n2023_1 = ~preset & n_n4342 & (pdn | ~n1870); - assign n2024 = n2316 & ~n2310 & n1879 & ~n1897; - assign n2025 = ~preset & n_n3841 & (ndn3_10 | ~nen3_10); - assign n2026 = n1845 & (n1920 ? (~n1921 ^ ~n1986) : (n1921 ^ ~n1986)); - assign n2027 = ~preset & n_n4182 & (~ndn3_5 | ndn3_6); - assign n2028_1 = ~preset & n_n3413 & (pdn | ~n1870); - assign n2029 = n_n3831 & (n1897 | n2310 | ~n2316); - assign n2030 = n1836 & n_n3814 & n_n3724 & ~n_n4227; - assign n2031 = ~preset & n_n3337 & (pdn | ~n1870); - assign n2032 = ~preset & n_n4209 & (pdn | ~n1870); - assign n2033_1 = ~preset & n_n3342 & (pdn | ~n1870); - assign n2034 = ~preset & n_n3667 & (pdn | ~n1870); - assign n2035 = ~preset & n_n3756 & (~ndn3_7 | ndn3_8); - assign n2036 = ~preset & n_n4095 & (ndn3_15 | ~ngfdn_3); - assign n2037 = n1851 & (n1928_1 ^ (~n2218_1 & ~n2219)); - assign n2038_1 = ~preset & n_n3394 & (pdn | ~n1870); - assign n2039 = ~preset & n_n3976 & (ndn3_10 | ~nen3_10); - assign n2040 = ~preset & n_n4166 & (pdn | ~n1870); - assign n2041 = ~preset & n_n3572 & (pdn | ~n1870); - assign n2042 = ~preset & n_n3514 & (pdn | ~n1870); - assign n2043_1 = ~preset & n_n4062 & (~ndn3_4 | ndn3_5); - assign n2044 = ~preset & n_n4021 & (~ndn3_4 | ndn3_5); - assign n2045 = n_n3766 & (n1874 | n2135 | n2136); - assign n2046 = ~preset & n_n3966 & (pdn | ~n1870); - assign n2047 = ~preset & n_n4199 & (pdn | ~n1870); - assign n2048_1 = ~preset & n_n4247 & (pdn | ~n1870); - assign n2049 = ~preset & n_n4360 & (~ndn3_7 | ndn3_8); - assign n2050 = ~preset & n_n4320 & (pdn | ~n1870); - assign n2051 = ~preset & n_n3108 & (pdn | ~n1870); - assign n2052 = ~preset & n_n3910 & (pdn | ~n1870); - assign n2053_1 = ~preset & n_n3758 & (pdn | ~n1870); - assign n2054 = ~preset & n_n3170 & (~ndn3_8 | ndn3_9); - assign n2055 = ~preset & n_n3250 & (~ndn3_8 | ndn3_9); - assign n2056 = ~preset & n_n4303 & (pdn | ~n1870); - assign n2057 = nsr1_2 & ~preset_0_0_ & ~nlc1_2; - assign n2058_1 = n_n4151 & (nlc1_2 | ~nsr1_2 | (preset_0_0_ & ~nlc1_2)); - assign n2059 = nsr3_14 & (nsr3_17 | (n_n4045 & n1890)); - assign n2060 = ~n1900 & ~n1886 & ~preset & n_n4029; - assign n2061 = n_n3533 & (n1899 | n2259); - assign n2062 = n1988_1 & ~preset & n_n3208; - assign n2063_1 = ~preset & n_n4157 & (~nrq3_11 | ngfdn_3); - assign n2064 = ~preset & n_n4299 & (~ndn3_7 | ndn3_8); - assign n2065 = ~preset & n_n3883 & (pdn | ~n1870); - assign n2066 = ~preset & n_n3331 & (pdn | ~n1870); - assign n2067 = ~preset & n_n4330 & (~ndn3_5 | ndn3_6); - assign n2068_1 = ~preset & n_n4159 & (~ndn3_5 | ndn3_6); - assign n2069 = ~preset & n_n4309 & (pdn | ~n1870); - assign n2070 = ~preset & n_n3722 & (pdn | ~n1870); - assign n2071 = ~preset & n_n3823 & (pdn | ~n1870); - assign n2072 = n_n3934 & (n2073_1 | (~preset & ~n1886)); - assign n2073_1 = ~n_n3976 & n1840; - assign n2074 = n1840 & (n_n4316 ? (~n_n3901 ^ n1935) : (n_n3901 ^ n1935)); - assign n2075 = ~preset & n_n3385 & (pdn | ~n1870); - assign n2076 = ~preset & n_n3202 & (pdn | ~n1870); - assign n2077 = ~preset & n_n3055 & (pdn | ~n1870); - assign n2078_1 = ~preset & n_n3463 & (pdn | ~n1870); - assign n2079 = ~preset & n_n3533 & (~ndn3_6 | ndn3_7); - assign n2080 = n2317 & n1878_1 & ~preset & n_n4258; - assign n2081 = n_n3818 & (~n1878_1 | ~n2317) & n2318; - assign n2082 = n1836 & (n_n3818 ? (~n1873_1 ^ ~n1944) : (n1873_1 ^ ~n1944)); - assign n2083_1 = ~preset & n_n4390 & (pdn | ~n1870); - assign n2084 = n1840 & (~n_n4229 ^ n1993_1); - assign n2085 = ~preset & n_n4136 & (pdn | ~n1870); - assign n2086 = ~preset & n_n4192 & (pdn | ~n1870); - assign n2087 = ~preset & n_n3126 & (pdn | ~n1870); - assign n2088_1 = ~preset & n_n3089 & (pdn | ~n1870); - assign n2089 = ~preset & n_n3713 & (pdn | ~n1870); - assign n2090 = ~preset & n_n3578 & (~ndn3_8 | ndn3_9); - assign n2091 = ~preset & n_n3624 & (~ndn3_8 | ndn3_9); - assign n2092 = ~preset & n_n3370 & (pdn | ~n1870); - assign n2093_1 = ~preset & n_n3213 & (pdn | ~n1870); - assign n2094 = ~preset & n_n3657 & (~nrq3_11 | ngfdn_3); - assign n2095 = ~preset & n_n3743 & (~ndn3_7 | ndn3_8); - assign n2096 = ~preset & n_n3223 & (pdn | ~n1870); - assign n2097 = ~preset & n_n4236 & (pdn | ~n1870); - assign n2098_1 = ~preset & n_n4372 & (pdn | ~n1870); - assign n2099 = ~preset & n_n3136 & (pdn | ~n1870); - assign n2100 = ~n1900 & ~n1886 & ~preset & ~n_n3954; - assign n2101 = n_n4349 & (n1899 | n2259); - assign n2102 = n2360 & (~n_n4056 | n1950 | ~n2357); - assign n2103_1 = n1988_1 & ~preset & n_n3259; - assign n2104 = ~preset & n_n3085 & (~nrq3_11 | ngfdn_3); - assign n2105 = n2038 & (n1952 ^ (~n2272 & ~n2273)); - assign n2106 = ~preset & n_n3946 & (~ndn3_7 | ndn3_8); - assign n2107 = n_n3709 & ((n1983_1 & n1984) | ~n2331); - assign n2108_1 = ~preset & n_n3777 & (pdn | ~n1870); - assign n2109 = ~preset & n_n3073 & (pdn | ~n1870); - assign n2110 = n2349 & n1867 & ~n_n4012 & n1836; - assign n2111 = ~preset & n_n3436 & (pdn | ~n1870); - assign n2112 = ~preset & n_n4351 & (ndn3_15 | ~ngfdn_3); - assign n2113_1 = n1851 & (n1952 ^ (~n2272 & ~n2273)); - assign n2114 = ~preset & n_n3287 & (pdn | ~n1870); - assign n2115 = ~preset & n_n3679 & (pdn | ~n1870); - assign n2116 = ~preset & n_n4065 & (pdn | ~n1870); - assign n2117 = ~preset & n_n3138 & (pdn | ~n1870); - assign n2118_1 = ~preset & n_n3631 & (pdn | ~n1870); - assign n2119 = ~preset & n_n3020 & (pdn | ~n1870); - assign n2120 = ~preset & n_n3057 & (pdn | ~n1870); - assign n2121 = ~preset & n_n3404 & (pdn | ~n1870); - assign n2122 = ~preset & n_n3069 & (pdn | ~n1870); - assign n2123_1 = n_n3483 & (n1872 | n2124 | n2171); - assign n2124 = ~n_n4334 & n1836; - assign n2125 = ~preset & n_n4362 & (~ndn3_7 | ndn3_8); - assign n2126 = ~preset & n_n4201 & (~ndn3_6 | ndn3_7); - assign n2127 = ~preset & n_n4229 & (ndn3_10 | ~nen3_10); - assign n2128_1 = n1845 & (n1952 ^ (~n2272 & ~n2273)); - assign n2129 = ~preset & n_n3408 & (pdn | ~n1870); - assign n2130 = ~preset & n_n3451 & (~ndn3_4 | ndn3_5); - assign n2131 = n_n4057 & (~n_n4056 | n1950 | ~n2357); - assign n2132 = ~preset & n_n3854 & (~ndn3_4 | ndn3_5); - assign n2133_1 = n2354 & (n1919 | (n1878_1 & n2317)); - assign n2134 = ~n_n3766 & n1836; - assign n2135 = ~n_n4227 & n1836; - assign n2136 = ~n_n3724 & n1836; - assign n2137 = ~n_n3814 & n1836; - assign n2138_1 = ~preset & n_n3922 & (~ndn3_6 | ndn3_7); - assign n2139 = ~preset & n_n3968 & (~ndn3_6 | ndn3_7); - assign n2140 = ~preset & n_n3237 & (pdn | ~n1870); - assign n2141 = ~preset & n_n3952 & (pdn | ~n1870); - assign n2142 = ~preset & n_n4122 & (~nrq3_11 | ngfdn_3); - assign n2143_1 = n2038 & (n1928_1 ^ (~n2218_1 & ~n2219)); - assign n2144 = ~preset & n_n3898 & (ndn3_10 | ~nen3_10); - assign n2145 = ~n1900 & ~n1886 & ~preset & n_n4099; - assign n2146 = n_n4337 & (n1899 | n2259); - assign n2147 = ~n1900 & ~n1886 & ~preset & n_n4052; - assign n2148_1 = n1898_1 & (~n_n4052 ^ (n_n3865 | n1891)); - assign n2149 = n_n4071 & (n1899 | n2259); - assign n2150 = ~preset & n_n3985 & (pdn | ~n1870); - assign n2151 = ~preset & n_n3091 & (pdn | ~n1870); - assign n2152 = ~preset & n_n4003 & (pdn | ~n1870); - assign n2153_1 = ~preset & n_n4145 & (ndn3_10 | ~nen3_10); - assign n2154 = n1845 & (n1928_1 ^ (~n2218_1 & ~n2219)); - assign n2155 = ~preset & n_n3978 & (~ndn3_4 | ndn3_5); - assign n2156 = n1840 & (~n_n3916 ^ n1992); - assign n2157 = ~preset & n_n3183 & (pdn | ~n1870); - assign n2158_1 = ~preset & n_n4288 & (ndn3_15 | ~ngfdn_3); - assign n2159 = ~preset & n_n4270 & (~ndn3_5 | ndn3_6); - assign n2160 = ~preset & n_n3449 & (pdn | ~n1870); - assign n2161 = ~preset & n_n3971 & (pdn | ~n1870); - assign n2162 = ~preset & n_n3429 & (pdn | ~n1870); - assign n2163_1 = ~preset & n_n3319 & (pdn | ~n1870); - assign n2164 = ~preset & n_n3506 & (pdn | ~n1870); - assign n2165 = ~preset & n_n3458 & (ndn3_15 | ~ngfdn_3); - assign n2166 = ~preset & n_n4233 & (ndn3_15 | ~ngfdn_3); - assign n2167 = n1851 & (n1920 ? (~n1921 ^ ~n1986) : (n1921 ^ ~n1986)); - assign n2168_1 = ~preset & n_n3155 & (pdn | ~n1870); - assign n2169 = ~n1900 & ~n1886 & ~preset & n_n3955; - assign n2170 = n_n4201 & (n1899 | n2259); - assign n2171 = ~n_n4012 & n1836; - assign n2172 = n1836 & (~n_n4275 | ~n_n3766 | ~n1867); - assign n2173_1 = n1988_1 & ~preset & n_n4294; - assign n2174 = ~preset & n_n4251 & (~ndn3_5 | ndn3_6); - assign n2175 = ~preset & n_n3736 & (pdn | ~n1870); - assign n2176 = ~preset & n_n3896 & (pdn | ~n1870); - assign n2177 = ~preset & n_n4279 & (pdn | ~n1870); - assign n2178_1 = n2317 & n1878_1 & ~preset & n_n4362; - assign n2179 = n_n3988 & (~n1878_1 | ~n2317) & n2318; - assign n2180 = n1836 & (n_n3988 ? (~n1869 ^ ~n1914) : (n1869 ^ ~n1914)); - assign n2181 = ~preset & n_n3328 & (~ndn3_4 | ndn3_5); - assign n2182 = ~preset & n_n3761 & (pdn | ~n1870); - assign n2183_1 = n2317 & n1878_1 & ~preset & n_n3946; - assign n2184 = n_n3995 & (~n1878_1 | ~n2317) & n2318; - assign n2185 = n1836 & (n_n3995 ? (~n1860 ^ ~n1943_1) : (n1860 ^ ~n1943_1)); - assign n2186 = ~preset & n_n3128 & (pdn | ~n1870); - assign n2187 = n1988_1 & ~preset & n_n3919; - assign n2188_1 = n1988_1 & ~preset & n_n3886; - assign n2189 = ~preset & n_n3048 & (pdn | ~n1870); - assign n2190 = ~preset & n_n3061 & (pdn | ~n1870); - assign n2191 = ~preset & n_n3316 & (pdn | ~n1870); - assign n2192 = ~preset & n_n3906 & (pdn | ~n1870); - assign n2193_1 = ~preset & n_n3583 & (pdn | ~n1870); - assign n2194 = ~preset & n_n3358 & (pdn | ~n1870); - assign n2195 = ~preset & n_n4243 & (pdn | ~n1870); - assign n2196 = ~preset & n_n4337 & (~ndn3_6 | ndn3_7); - assign n2197 = ~preset & n_n3207 & (pdn | ~n1870); - assign n2198_1 = ~preset & n_n3465 & (pdn | ~n1870); - assign n2199 = n2348 & ((~pdn & ~n1870) | (ndn1_34 & (pdn | ~n1870))); - assign n2200 = ~preset & n_n3892 & (~ndn3_6 | ndn3_7); - assign n2201 = ~preset & n_n4383 & (~ndn3_5 | ndn3_6); - assign n2202 = ~preset & n_n4286 & (pdn | ~n1870); - assign n2203_1 = ~preset & n_n4189 & (pdn | ~n1870); - assign n2204 = ~preset & n_n3576 & (pdn | ~n1870); - assign n2205 = ~preset & n_n4172 & (pdn | ~n1870); - assign n2206 = ~preset & n_n3111 & (pdn | ~n1870); - assign n2207 = ~preset & n_n3035 & (~ndn3_8 | ndn3_9); - assign n2208_1 = ~preset & n_n3627 & (pdn | ~n1870); - assign n2209 = ~preset & n_n3044 & (pdn | ~n1870); - assign n2210 = ~preset & n_n3376 & (pdn | ~n1870); - assign n2211 = ~preset & n_n3118 & (pdn | ~n1870); - assign n2212 = ~preset & n_n3242 & (~nrq3_11 | ngfdn_3); - assign n2213_1 = n2038 & (n1920 ? (~n1921 ^ ~n1986) : (n1921 ^ ~n1986)); - assign n2214 = ngfdn_3 & n_n4122 & ~ndn3_15 & n_n3556; - assign n2215 = nen3_10 & ~ndn3_10 & n_n3919; - assign n2216 = n_n4145 & nrq3_11 & ~ngfdn_3; - assign n2217 = n_n4062 & ~ndn3_10 & nen3_10; - assign n2218_1 = n1939 & ((n1910 & n1911) | (n1909 & (n1910 | n1911))); - assign n2219 = n1918_1 & (n2221 | n2222 | n2223_1); - assign n2220 = nen3_10 & ~ndn3_10 & n_n3854; - assign n2221 = ngfdn_3 & n_n4157 & ~ndn3_15 & n_n3035; - assign n2222 = nen3_10 & n_n3511 & ~ndn3_10; - assign n2223_1 = n_n3898 & nrq3_11 & ~ngfdn_3; - assign n2224 = ngfdn_3 & n_n3170 & ~ndn3_15 & n_n3242; - assign n2225 = n_n3259 & ~ndn3_10 & nen3_10; - assign n2226 = n_n3841 & nrq3_11 & ~ngfdn_3; - assign n2227 = nen3_10 & ~ndn3_10 & n_n3451; - assign n2228_1 = ~preset & n_n3113 & (pdn | ~n1870); - assign n2229 = ~preset & n_n3173 & (pdn | ~n1870); - assign n2230 = ~preset & n_n3221 & (pdn | ~n1870); - assign n2231 = n2317 & n1878_1 & ~preset & n_n3876; - assign n2232 = n_n4040 & (~n1878_1 | ~n2317) & n2318; - assign n2233_1 = n1836 & (n_n4040 ? (~n1843_1 ^ ~n1913_1) : (n1843_1 ^ ~n1913_1)); - assign n2234 = ~preset & n_n3556 & (~ndn3_8 | ndn3_9); - assign n2235 = ~preset & n_n3733 & (pdn | ~n1870); - assign n2236 = ~preset & n_n3231 & (pdn | ~n1870); - assign n2237 = ~preset & n_n3313 & (pdn | ~n1870); - assign n2238_1 = ~preset & n_n3079 & (pdn | ~n1870); - assign n2239 = ~preset & n_n3688 & (~nrq3_11 | ngfdn_3); - assign n2240 = ~preset & n_n3344 & (pdn | ~n1870); - assign n2241 = ~preset & n_n4071 & (~ndn3_6 | ndn3_7); - assign n2242 = ~preset & n_n3012 & (pdn | ~n1870); - assign n2243_1 = ~preset & n_n4222 & (ndn3_10 | ~nen3_10); - assign n2244 = ~preset & n_n4160 & (~ndn3_5 | ndn3_6); - assign n2245 = ~preset & n_n3517 & (pdn | ~n1870); - assign n2246 = n_n3707 & (~n_n3709 | n1937 | ~n2331); - assign n2247 = ~preset & n_n3281 & (~ndn3_4 | ndn3_5); - assign n2248_1 = ~preset & n_n3764 & (pdn | ~n1870); - assign n2249 = ~preset & n_n3549 & (pdn | ~n1870); - assign n2250 = ~preset & n_n3876 & (~ndn3_7 | ndn3_8); - assign n2251 = ~preset & n_n3729 & (pdn | ~n1870); - assign n2252 = ~preset & n_n3525 & (pdn | ~n1870); - assign n2253_1 = ~preset & n_n3916 & (ndn3_10 | ~nen3_10); - assign n2254 = ~preset & n_n3495 & (ndn3_15 | ~ngfdn_3); - assign n2255 = ~preset & n_n4211 & (~ndn3_8 | ndn3_9); - assign n2256 = ~preset & n_n3670 & (pdn | ~n1870); - assign n2257 = ~n1900 & ~n1886 & ~preset & n_n4381; - assign n2258_1 = n_n3892 & (n1899 | n2259); - assign n2259 = ~n_n3493 & ~n1890 & (~n_n4045 | n2335); - assign n2260 = n1988_1 & ~preset & n_n3858; - assign n2261 = ~preset & n_n3270 & (pdn | ~n1870); - assign n2262 = ~preset & n_n4074 & (~nrq3_11 | ngfdn_3); - assign n2263_1 = ngfdn_3 & n_n3578 & ~ndn3_15 & n_n4074; - assign n2264 = nen3_10 & ~ndn3_10 & n_n3886; - assign n2265 = n_n3916 & nrq3_11 & ~ngfdn_3; - assign n2266 = n_n4021 & ~ndn3_10 & nen3_10; - assign n2267 = nen3_10 & n_n3281 & ~ndn3_10; - assign n2268_1 = nrq3_11 & ~ngfdn_3 & (n_n4229 ^ ~n1902); - assign n2269 = ngfdn_3 & n_n3250 & ~ndn3_15 & n_n3085; - assign n2270 = nen3_10 & ~ndn3_10 & n_n4294; - assign n2271 = n_n4229 & nrq3_11 & ~ngfdn_3; - assign n2272 = n1916 & ((n1906 & ~n1971) | (n1905 & (n1906 | ~n1971))); - assign n2273 = n1915 & (n2284 | n2327); - assign n2274 = ~preset & n_n3133 & (pdn | ~n1870); - assign n2275 = ~n1894 & (~n1969 | n2329); - assign n2276 = (~n_n4145 ^ ~n1895) & (~n_n4080 ^ n1907); - assign n2277 = ~preset & n_n4224 & (~ndn3_5 | ndn3_6); - assign n2278 = ~preset & n_n4392 & (ndn3_15 | ~ngfdn_3); - assign n2279 = n1988_1 & ~preset & n_n3511; - assign n2280 = ~preset & n_n3780 & (pdn | ~n1870); - assign n2281 = ~preset & n_n4349 & (~ndn3_6 | ndn3_7); - assign n2282 = ~preset & n_n4316 & (ndn3_10 | ~nen3_10); - assign n2283 = nen3_10 & ~ndn3_10 & n_n3978; - assign n2284 = n1877 & (n_n4316 ? (n1938_1 ^ ~n1959) : (~n1938_1 ^ ~n1959)); - assign n2285 = ngfdn_3 & n_n3657 & ~ndn3_15 & n_n4211; - assign n2286 = nen3_10 & n_n3858 & ~ndn3_10; - assign n2287 = n_n4316 & nrq3_11 & ~ngfdn_3; - assign n2288 = nrq3_11 & ~ngfdn_3 & (n_n4159 ^ n_n3976); - assign n2289 = ngfdn_3 & n_n3624 & ~ndn3_15 & n_n3688; - assign n2290 = n_n3878 & ~ndn3_10 & nen3_10; - assign n2291 = nrq3_11 & n_n3976 & ~ngfdn_3; - assign n2292 = nen3_10 & ~ndn3_10 & n_n3328; - assign n2293 = n1871 & nrq3_11 & ~ngfdn_3; - assign n2294 = n_n3099 & ngfdn_3 & n_n3936 & ~ndn3_15; - assign n2295 = n_n3208 & ~ndn3_10 & nen3_10; - assign n2296 = n_n4222 & nrq3_11 & ~ngfdn_3; - assign n2297 = ~preset & n_n3793 & (pdn | ~n1870); - assign n2298 = ~preset & n_n3497 & (pdn | ~n1870); - assign n2299 = ~preset & n_n3098 & (pdn | ~n1870); - assign n2300 = ~preset & n_n3687 & (pdn | ~n1870); - assign n2301 = ~preset & n_n3225 & (pdn | ~n1870); - assign n2302 = ~preset & n_n4258 & (~ndn3_7 | ndn3_8); - assign n2303 = n2317 & n1878_1 & ~preset & n_n4360; - assign n2304 = n_n3726 & (~n1878_1 | ~n2317) & n2318; - assign n2305 = n1836 & (n_n3726 ? (~n1857 ^ ~n1908_1) : (n1857 ^ ~n1908_1)); - assign n2306 = ~preset & n_n3008 & (pdn | ~n1870); - assign n2307 = n2317 & n1878_1 & ~preset & n_n3743; - assign n2308 = n_n3574 & (~n1878_1 | ~n2317) & n2318; - assign n2309 = n1836 & (n_n3574 ? (~n1871 ^ ~n1883_1) : (n1871 ^ ~n1883_1)); - assign n2310 = ~n_n4067 & (n_n4026 ? ~n_n3851 : ~n1953_1); - assign n2311 = ~preset & n_n3936 & (~ndn3_8 | ndn3_9); - assign n2312 = ~preset & n_n4142 & (pdn | ~n1870); - assign n2313 = ~n_n3756 & (~n_n4159 ^ ~n_n3976); - assign n2314 = ~n_n4182 & ~n_n4330; - assign n2315 = n1839 & ((~n_n4067 & ~n1849) | (n_n3833 & (n_n4067 | ~n1849))); - assign n2316 = nen3_10 & nsr3_17 & n_n4093; - assign n2317 = n1879 & ~n_n3709; - assign n2318 = ~preset & (n_n3198 | ~n_n3707 | ~n_n3709); - assign n2319 = n_n4157 & n_n3035; - assign n2320 = n_n4349 | n_n4071 | n_n3892 | n_n4337; - assign n2321 = n_n3968 | n_n3922 | n_n4201 | n_n3533; - assign n2322 = nsr3_14 & n_n4045 & ~nsr3_17; - assign n2323 = ~n_n3557 & n_n4057; - assign n2324 = n_n3624 & n_n3688; - assign n2325 = n2292 | (n_n4125 & n1890 & n1904); - assign n2326 = n2288 | (~ndn3_10 & nen3_10 & n_n3931); - assign n2327 = n2283 | (n_n3901 & n1890 & n1904); - assign n2328 = ~ndn3_4 & ~preset; - assign n2329 = (n_n4145 & ~n1895) | (~n_n4145 & n1895) | ((~n_n4145 ^ n1895) & (n_n4080 ^ n1907)); - assign n2330 = n1857 | n2276 | (~n1857 & (~n_n3726 ^ ~n1908_1)); - assign n2331 = n1919 & (n2275 | n2330); - assign n2332 = n_n3578 & n_n4074; - assign n2333 = n2267 | (n_n3769 & n1890 & n1904); - assign n2334 = n2266 | (n_n4047 & n1890 & n1904); - assign n2335 = nsr3_14 & ~nsr3_17; - assign n2336 = (n1898_1 & n1945) | (n_n4381 & n1989); - assign n2337 = n_n3493 & ~preset; - assign n2338 = n_n3170 & n_n3242; - assign n2339 = n_n3099 & n_n3936; - assign n2340 = n_n4026 | ~n_n3831 | (~n_n4026 & ~n1953_1); - assign n2341 = n_n3657 & n_n4211; - assign n2342 = n2227 | (n_n4324 & n1890 & n1904); - assign n2343 = n2220 | (n_n4366 & n1890 & n1904); - assign n2344 = n2217 | (n_n3475 & n1890 & n1904); - assign n2345 = n_n4122 & n_n3556; - assign n2346 = n_n3250 & n_n3085; - assign n2347 = nsr3_3 & ((n_n4108 & ~n_n3354) | (~tin_pready_0_0_ & (~n_n4108 | ~n_n3354))); - assign n2348 = n_n3354 & ~preset; - assign n2349 = n_n3766 & n_n4275; - assign n2350 = n_n3955 ? (n1989 | (~n_n3954 & n1898_1)) : (n_n3954 & n1898_1); - assign n2351 = nlak4_2 | (nlc3_3 & ~n_n4263); - assign n2352 = (n_n4052 & n1989) | n2148_1; - assign n2353 = n_n4099 ? ((n1898_1 & n1967) | n1989) : (n1898_1 & ~n1967); - assign n2354 = n1867 & n1836 & ~n_n4275 & n_n3766; - assign n2355 = ~n_n3954 & ~n_n3955; - assign n2356 = n2355 & ~n1949 & n1898_1 & ~n1948_1; - assign n2357 = n2356 & n1951 & ~n1917 & ~n1945; - assign n2358 = ~n_n4045 | preset | (~n1890 & n2335); - assign n2359 = n_n3707 & ~preset; - assign n2360 = n1890 & n_n4057; - assign n2361 = ~nsr3_14 | nsr3_17; - assign n2362 = ~n_n4045 | preset | (~n1890 & n2335); - assign n2363 = n_n3954 ? n1898_1 : n1989; - assign n2364 = ~preset & n_n4045 & (n1890 | ~n2335); - assign n2365 = (n1898_1 & n1948_1) | (n_n4029 & n1989); - assign n2366 = n_n3814 & n_n4227 & n_n3724 & ~n_n3766; - assign n2367 = n1879 & n_n3707; - assign n2368 = n1855 | preset | (n1880 & n2367); - assign n2369 = (n1898_1 & n1949) | (n_n3845 & n1989); - assign n2370 = n_n3865 ? ((n1891 & n1898_1) | n1989) : (~n1891 & n1898_1); - assign n2371 = n1887 & n1840; - assign n2372 = n2331 & ~n1937 & ~preset & n_n3709; - assign n2373 = n1849 & ~n_n4067; - assign n2374 = ~n2310 & n1903_1 & n_n4093 & ~n1897; - always @ (posedge clock) begin - n_n4142 <= n349; - n_n3936 <= n354; - n_n3574 <= n359; - n_n3008 <= n364; - n_n3726 <= n369; - n_n3604 <= n374; - n_n3144 <= n379; - n_n3782 <= n384; - n_n3067 <= n389; - n_n4258 <= n394; - n_n3225 <= n399; - n_n3180 <= n404; - n_n3274 <= n409; - n_n3475 <= n414; - n_n3687 <= n419; - n_n3381 <= n424; - n_n3098 <= n429; - n_n4108 <= n434; - n_n3497 <= n439; - n_n3793 <= n444; - n_n4316 <= n449; - n_n4349 <= n454; - n_n3029 <= n459; - n_n3619 <= n464; - n_n3264 <= n469; - n_n3780 <= n474; - ndn3_4 <= n479; - n_n4114 <= n484; - n_n3146 <= n489; - n_n3511 <= n494; - n_n3152 <= n499; - n_n3833 <= n504; - n_n4282 <= n509; - n_n3305 <= n514; - n_n4392 <= n519; - n_n4224 <= n524; - n_n3198 <= n529; - n_n3204 <= n534; - n_n3024 <= n539; - n_n4139 <= n544; - ndn3_15 <= n549; - n_n3133 <= n554; - n_n4074 <= n559; - n_n3270 <= n564; - n_n3858 <= n569; - n_n3456 <= n574; - n_n3521 <= n579; - n_n3081 <= n584; - n_n4381 <= n589; - n_n3670 <= n594; - n_n4211 <= n599; - n_n3493 <= n604; - n_n3495 <= n609; - n_n3916 <= n614; - n_n3195 <= n619; - n_n3525 <= n624; - n_n3729 <= n629; - n_n3876 <= n634; - ndn3_5 <= n639; - n_n3549 <= n644; - n_n3489 <= n649; - n_n3764 <= n654; - n_n3281 <= n659; - n_n3707 <= n664; - n_n3517 <= n669; - n_n4160 <= n674; - n_n4222 <= n679; - n_n3012 <= n684; - n_n4071 <= n689; - n_n3372 <= n694; - n_n3344 <= n699; - n_n3688 <= n704; - n_n3079 <= n709; - n_n3313 <= n714; - n_n3411 <= n719; - n_n3231 <= n724; - n_n3396 <= n729; - n_n3432 <= n734; - n_n3606 <= n739; - n_n3733 <= n744; - n_n3556 <= n749; - n_n4040 <= n754; - n_n3120 <= n759; - n_n3221 <= n764; - n_n3173 <= n769; - n_n3851 <= n774; - n_n3113 <= n779; - n_n3242 <= n784; - n_n3118 <= n789; - n_n3376 <= n794; - n_n4089 <= n799; - n_n3044 <= n804; - n_n3627 <= n809; - n_n3035 <= n814; - n_n3111 <= n819; - n_n3321 <= n824; - n_n3443 <= n829; - n_n3215 <= n834; - ndn3_10 <= n839; - n_n4172 <= n844; - nlc1_2 <= n849; - n_n3590 <= n854; - n_n4110 <= n859; - nlc3_3 <= n864; - n_n3576 <= n869; - n_n4129 <= n874; - n_n4189 <= n879; - n_n4286 <= n884; - n_n4383 <= n889; - pdn <= n894; - n_n3567 <= n898; - n_n3892 <= n903; - n_n3075 <= n908; - n_n3354 <= n913; - n_n3465 <= n918; - ndn3_6 <= n923; - n_n3617 <= n928; - n_n4162 <= n933; - n_n3207 <= n938; - n_n4120 <= n943; - n_n3065 <= n948; - n_n4005 <= n953; - n_n3266 <= n958; - n_n4337 <= n963; - n_n3600 <= n968; - n_n3415 <= n973; - n_n4243 <= n978; - n_n3872 <= n983; - n_n3648 <= n988; - n_n3358 <= n993; - n_n3350 <= n998; - ndn3_7 <= n1003; - n_n3116 <= n1008; - n_n3583 <= n1013; - n_n3906 <= n1018; - n_n4131 <= n1023; - n_n3316 <= n1028; - n_n3061 <= n1033; - n_n3048 <= n1038; - n_n3886 <= n1043; - n_n3919 <= n1048; - n_n3128 <= n1053; - n_n3995 <= n1058; - n_n4213 <= n1063; - n_n3761 <= n1068; - ndn3_8 <= n1073; - n_n3252 <= n1078; - n_n4366 <= n1083; - n_n3328 <= n1088; - n_n3988 <= n1093; - n_n3348 <= n1098; - n_n3544 <= n1103; - n_n3101 <= n1108; - n_n4279 <= n1113; - n_n3896 <= n1118; - n_n3736 <= n1123; - n_n4251 <= n1128; - n_n3650 <= n1133; - n_n3307 <= n1138; - n_n4294 <= n1143; - n_n4334 <= n1148; - n_n3955 <= n1153; - n_n4164 <= n1158; - n_n3155 <= n1163; - n_n3749 <= n1168; - n_n4233 <= n1173; - n_n4347 <= n1178; - n_n3826 <= n1183; - n_n3360 <= n1188; - n_n3458 <= n1193; - n_n3093 <= n1198; - n_n3157 <= n1203; - n_n3506 <= n1208; - n_n3161 <= n1213; - n_n3319 <= n1218; - n_n3429 <= n1223; - n_n3971 <= n1228; - n_n3449 <= n1233; - n_n4270 <= n1238; - n_n4288 <= n1243; - n_n3183 <= n1248; - n_n3130 <= n1253; - nlak4_2 <= n1258; - n_n4047 <= n1263; - n_n3978 <= n1268; - n_n3239 <= n1273; - n_n4145 <= n1278; - n_n3890 <= n1283; - n_n4003 <= n1288; - n_n3091 <= n1293; - n_n3985 <= n1298; - n_n3326 <= n1303; - n_n4052 <= n1308; - nsr4_2 <= n1313; - n_n4099 <= n1318; - n_n4375 <= n1323; - n_n4067 <= n1328; - n_n4290 <= n1333; - n_n3898 <= n1338; - n_n4122 <= n1343; - n_n3774 <= n1348; - n_n3014 <= n1353; - n_n4241 <= n1358; - n_n3952 <= n1363; - n_n3237 <= n1368; - n_n3968 <= n1373; - n_n3922 <= n1378; - n_n3551 <= n1383; - n_n3379 <= n1388; - n_n4275 <= n1393; - n_n3570 <= n1398; - n_n3854 <= n1403; - n_n4057 <= n1408; - n_n3451 <= n1413; - n_n4037 <= n1418; - n_n3408 <= n1423; - n_n4229 <= n1428; - n_n4201 <= n1433; - n_n3339 <= n1438; - n_n4362 <= n1443; - n_n3483 <= n1448; - n_n3557 <= n1453; - n_n4185 <= n1458; - n_n3069 <= n1463; - n_n3643 <= n1468; - n_n3404 <= n1473; - n_n3057 <= n1478; - n_n3020 <= n1483; - n_n3828 <= n1488; - n_n3631 <= n1493; - n_n3138 <= n1498; - nsr1_2 <= n1503; - n_n4065 <= n1508; - n_n3679 <= n1513; - n_n3287 <= n1518; - n_n4351 <= n1523; - n_n4059 <= n1528; - n_n3436 <= n1533; - nen3_10 <= n1538; - n_n3461 <= n1543; - n_n4012 <= n1548; - n_n3051 <= n1553; - n_n3073 <= n1558; - n_n3777 <= n1563; - n_n3709 <= n1568; - n_n3946 <= n1573; - n_n3085 <= n1578; - n_n3259 <= n1583; - n_n3504 <= n1588; - n_n4045 <= n1593; - n_n3954 <= n1598; - n_n3136 <= n1603; - n_n4372 <= n1608; - n_n4236 <= n1613; - n_n3040 <= n1618; - n_n3874 <= n1623; - n_n3999 <= n1628; - n_n3223 <= n1633; - ndn1_34 <= n1638; - n_n3743 <= n1643; - n_n3657 <= n1648; - n_n3213 <= n1653; - n_n3095 <= n1658; - n_n3663 <= n1663; - n_n3724 <= n1668; - n_n3038 <= n1673; - n_n3370 <= n1678; - n_n3624 <= n1683; - n_n3578 <= n1688; - n_n3713 <= n1693; - n_n3089 <= n1698; - n_n3211 <= n1703; - n_n3367 <= n1708; - n_n3434 <= n1713; - n_n3126 <= n1718; - n_n4192 <= n1723; - n_n4136 <= n1728; - n_n3053 <= n1733; - n_n3938 <= n1738; - n_n3769 <= n1743; - n_n4390 <= n1748; - nsr3_17 <= n1753; - n_n3903 <= n1758; - n_n3658 <= n1763; - nrq3_11 <= n1768; - n_n3818 <= n1773; - n_n3533 <= n1778; - n_n3463 <= n1783; - n_n3175 <= n1788; - n_n3055 <= n1793; - n_n3202 <= n1798; - n_n3385 <= n1803; - n_n4077 <= n1808; - n_n3142 <= n1813; - n_n3901 <= n1818; - n_n3934 <= n1823; - n_n3823 <= n1828; - n_n3722 <= n1833; - n_n4309 <= n1838; - n_n4159 <= n1843; - n_n4330 <= n1848; - n_n3836 <= n1853; - n_n3470 <= n1858; - n_n3331 <= n1863; - n_n3883 <= n1868; - n_n4299 <= n1873; - n_n4157 <= n1878; - ndn3_9 <= n1883; - n_n3208 <= n1888; - n_n3190 <= n1893; - n_n4029 <= n1898; - n_n3042 <= n1903; - nsr3_14 <= n1908; - n_n4151 <= n1913; - n_n3188 <= n1918; - n_n4303 <= n1923; - n_n3250 <= n1928; - n_n3170 <= n1933; - n_n3758 <= n1938; - n_n3910 <= n1943; - n_n3108 <= n1948; - n_n3150 <= n1953; - n_n4320 <= n1958; - n_n4360 <= n1963; - n_n4247 <= n1968; - n_n4199 <= n1973; - n_n3966 <= n1978; - n_n3766 <= n1983; - n_n4021 <= n1988; - n_n4062 <= n1993; - n_n3514 <= n1998; - n_n3572 <= n2003; - n_n4166 <= n2008; - n_n3976 <= n2013; - n_n3394 <= n2018; - n_n4095 <= n2023; - n_n3863 <= n2028; - n_n3720 <= n2033; - ngfdn_3 <= n2038; - n_n3756 <= n2043; - n_n3667 <= n2048; - n_n3342 <= n2053; - n_n3529 <= n2058; - n_n4209 <= n2063; - n_n4324 <= n2068; - n_n3337 <= n2073; - n_n4227 <= n2078; - n_n4153 <= n2083; - n_n3831 <= n2088; - n_n3233 <= n2093; - n_n4263 <= n2098; - n_n3413 <= n2103; - n_n4182 <= n2108; - n_n3841 <= n2113; - n_n3441 <= n2118; - n_n4026 <= n2123; - n_n4342 <= n2128; - n_n4102 <= n2133; - n_n3277 <= n2138; - n_n4180 <= n2143; - n_n3878 <= n2148; - n_n3931 <= n2153; - n_n3845 <= n2158; - n_n3865 <= n2163; - n_n3486 <= n2168; - n_n4056 <= n2173; - n_n3674 <= n2178; - n_n3959 <= n2183; - n_n3608 <= n2188; - n_n4080 <= n2193; - n_n4018 <= n2198; - n_n4354 <= n2203; - n_n3797 <= n2208; - n_n3739 <= n2213; - n_n3646 <= n2218; - n_n3099 <= n2223; - n_n3537 <= n2228; - n_n3806 <= n2233; - n_n3087 <= n2238; - n_n4105 <= n2243; - n_n3262 <= n2248; - n_n4125 <= n2253; - n_n3814 <= n2258; - n_n4093 <= n2263; - nsr3_3 <= n2268; - end -endmodule - - diff --git a/fpga_flow/benchmarks/Verilog/Test_Modes/test_modes.v b/fpga_flow/benchmarks/Verilog/Test_Modes/test_modes.v deleted file mode 100644 index 8090d2903..000000000 --- a/fpga_flow/benchmarks/Verilog/Test_Modes/test_modes.v +++ /dev/null @@ -1,78 +0,0 @@ -//////////////////////////////////////////////////////// -// // -// Benchmark using all modes of k8 architecture // -// // -//////////////////////////////////////////////////////// - -`timescale 1 ns/ 1 ps - -module test_modes( - clk, - a_0, - a_1, - a_2, - a_3, - b_0, - b_1, - b_2, - b_3, - cin, - e, - f, - g, - sum_0, - sum_1, - sum_2, - sum_3, - cout, - x, - y, - z ); - - input wire clk, a_0, a_1, a_2, a_3, b_0, b_1, b_2, b_3, cin, e, f, g; - output reg sum_0, sum_1, sum_2, sum_3, cout; - output wire x, y, z; - - wire d0; - wire [4:0] n0; - wire [3:0] a, b; - reg reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg_a_0, reg_a_1, reg_a_2, reg_a_3, reg_b_0, reg_b_1, reg_b_2, reg_b_3, reg_cin; - - assign a = {reg_a_3, reg_a_2, reg_a_1, reg_a_0}; - assign b = {reg_b_3, reg_b_2, reg_b_1, reg_b_0}; - assign d0 = (e && g) || !f; - assign n0 = a + b + reg_cin; - assign x = reg3; - assign y = reg7; - assign z = reg11; - - always @(posedge clk) begin - reg0 <= d0; - reg1 <= reg0; - reg2 <= reg1; - reg3 <= reg2; - reg4 <= reg3; - reg5 <= reg4; - reg6 <= reg5; - reg7 <= reg6; - reg8 <= reg7; - reg9 <= reg8; - reg10 <= reg9; - reg11 <= reg10; - reg_a_0 <= a_0; - reg_a_1 <= a_1; - reg_a_2 <= a_2; - reg_a_3 <= a_3; - reg_b_0 <= b_0; - reg_b_1 <= b_1; - reg_b_2 <= b_2; - reg_b_3 <= b_3; - reg_cin <= cin; - sum_0 <= n0[0]; - sum_1 <= n0[1]; - sum_2 <= n0[2]; - sum_3 <= n0[3]; - cout <= n0[4]; - end - -endmodule diff --git a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_FF.conf b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_FF.conf deleted file mode 100644 index e53a2b578..000000000 --- a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_FF.conf +++ /dev/null @@ -1,33 +0,0 @@ -# Standard Configuration Example -[dir_path] -#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog -#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif -#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20 -benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/FPGA_SPICE_bench -odin2_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ODIN_II/odin_II.exe -cirkit_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc -abc_path = /research/ece/lnis/USERS/tang/research/ABC/abc70930/abc -abc_mccl_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc -abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/vtr7_release/abc_with_bb_support/abc -mpack1_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack -m2net_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/scripts/m2net.pl -mpack2_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v2/mpack2 -#vpr_path = /research/ece/lnis/USERS/tang/research/vtr7_release/vpr/vpr -vpr_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr -rpt_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/results -ace_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ace2/ace - -[flow_conf] -flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr -#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr -vpr_arch = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_FF.xml # Use relative path under VPR folder is OK -mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf -mpack2_arch = K6_pattern7_I24.arch -power_tech_xml = /research/ece/lnis/USERS/tang/research/OpenFPGA/fpga_flow/tech/tsmc40nm.xml # Use relative path under VPR folder is OK - -[csv_tags] -mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: -mpack2_tags = BLE Number:|BLE Fill Rate: -vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles: -vpr_power_tags = PB Types|Routing diff --git a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_MC.conf b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_MC.conf deleted file mode 100644 index abdb96b0e..000000000 --- a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_MC.conf +++ /dev/null @@ -1,33 +0,0 @@ -# Standard Configuration Example -[dir_path] -#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog -#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif -#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20 -benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/FPGA_SPICE_bench -odin2_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ODIN_II/odin_II.exe -cirkit_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc -abc_path = /research/ece/lnis/USERS/tang/research/ABC/abc70930/abc -abc_mccl_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc -abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/vtr7_release/abc_with_bb_support/abc -mpack1_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack -m2net_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/scripts/m2net.pl -mpack2_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v2/mpack2 -#vpr_path = /research/ece/lnis/USERS/tang/research/vtr7_release/vpr/vpr -vpr_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr -rpt_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/results -ace_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ace2/ace - -[flow_conf] -flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr -#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr -vpr_arch = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_MC.xml # Use relative path under VPR folder is OK -mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf -mpack2_arch = K6_pattern7_I24.arch -power_tech_xml = /research/ece/lnis/USERS/tang/research/OpenFPGA/fpga_flow/tech/tsmc40nm.xml # Use relative path under VPR folder is OK - -[csv_tags] -mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: -mpack2_tags = BLE Number:|BLE Fill Rate: -vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles: -vpr_power_tags = PB Types|Routing diff --git a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_SS.conf b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_SS.conf deleted file mode 100644 index 3a18fd9c9..000000000 --- a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_SS.conf +++ /dev/null @@ -1,33 +0,0 @@ -# Standard Configuration Example -[dir_path] -#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog -#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif -#benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20 -benchmark_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/FPGA_SPICE_bench -odin2_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ODIN_II/odin_II.exe -cirkit_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc -abc_path = /research/ece/lnis/USERS/tang/research/ABC/abc70930/abc -abc_mccl_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc -abc_with_bb_support_path = /research/ece/lnis/USERS/tang/research/vtr7_release/abc_with_bb_support/abc -mpack1_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack -m2net_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/scripts/m2net.pl -mpack2_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/MPACK_v2/mpack2 -#vpr_path = /research/ece/lnis/USERS/tang/research/vtr7_release/vpr/vpr -vpr_path = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/vpr -rpt_dir = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/results -ace_path = /research/ece/lnis/USERS/tang/research/vtr7_release/ace2/ace - -[flow_conf] -flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr -#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr -vpr_arch = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_SS.xml # Use relative path under VPR folder is OK -mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = /research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf -mpack2_arch = K6_pattern7_I24.arch -power_tech_xml = /research/ece/lnis/USERS/tang/research/OpenFPGA/fpga_flow/tech/tsmc40nm.xml # Use relative path under VPR folder is OK - -[csv_tags] -mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: -mpack2_tags = BLE Number:|BLE Fill Rate: -vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles: -vpr_power_tags = PB Types|Routing diff --git a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf b/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf deleted file mode 100644 index 9d3ab267d..000000000 --- a/fpga_flow/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf +++ /dev/null @@ -1,30 +0,0 @@ -# Standard Configuration Example -[dir_path] -script_base = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/scripts/ -benchmark_dir = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/benchmarks/FPGA_SPICE_bench/ -yosys_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/../yosys/yosys -odin2_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/odin2.exe -cirkit_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/cirkit -abc_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/../yosys/yosys-abc -abc_mccl_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/../abc_with_bb_support/abc -abc_with_bb_support_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/../abc_with_bb_support/abc -mpack1_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/mpack1 -m2net_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/m2net -mpack2_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/mpack2 -vpr_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/../vpr7_x2p/vpr/vpr -rpt_dir = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/results -ace_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/../ace2/ace - -[flow_conf] -flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr -vpr_arch = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml # Use relative path under VPR folder is OK -mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf -mpack2_arch = K6_pattern7_I24.arch -power_tech_xml = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK - -[csv_tags] -mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: -mpack2_tags = BLE Number:|BLE Fill Rate: -vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles: -vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff diff --git a/fpga_flow/configs/sample.conf b/fpga_flow/configs/sample.conf deleted file mode 100644 index e131a5af7..000000000 --- a/fpga_flow/configs/sample.conf +++ /dev/null @@ -1,34 +0,0 @@ -# Standard Configuration Example -[dir_path] -#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_verilog -#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/vtr_benchmarks_blif -#benchmark_dir = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/benchmarks/MCNC_big20 -benchmark_dir = /Users/baudouinchauviere/Documents/Tutorial_OpenFPGA/OpenFPGA/fpga_flow/benchmarks/fpga_spice_test_bench -odin2_path = /home/xitang/research/vtr_release/ODIN_II/odin_II.exe -cirkit_path = /home/xitang/tangxifan-eda-tools/branches/FPGA_MIG/abc_majccmap/abc -abc_path = /home/xitang/research/ABC/abc70930/abc -abc_mccl_path = /home/xitang/tangxifan-eda-tools/branches/FPGA_MIG/abc_vtrccmap/abc -abc_with_bb_support_path = /home/xitang/research/vtr_release/abc_with_bb_support/abc -mpack1_path = /home/xitang/tangxifan-eda-tools/branches/MPACK_v1.5b/mpack -m2net_path = /home/xitang/tangxifan-eda-tools/branches/scripts/m2net.pl -mpack2_path = /home/xitang/tangxifan-eda-tools/branches/MPACK_v2/mpack2 -#vpr_path = /home/xitang/research/vtr_release/vpr/vpr -vpr_path = /Users/baudouinchauviere/Documents/Tutorial_OpenFPGA/OpenFPGA/vpr7_rram/vpr/vpr -rpt_dir = /Users/baudouinchauviere/Documents/Tutorial_OpenFPGA/OpenFPGA/fpga_flow/results -ace_path = /Users/baudouinchauviere/Documents/Tutorial_OpenFPGA/OpenFPGA/ace2/ace - -[flow_conf] -flow_type = standard #standard|mpack2|mpack1|vtr_standard|vtr -#flow_type = vtr #standard|mpack2|mpack1|vtr_standard|vtr -vpr_arch = /Users/baudouinchauviere/Documents/Tutorial_OpenFPGA/OpenFPGA/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm.xml # Use relative path under VPR folder is OK -mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/m2net_conf/m2x2_SiNWFET.conf -mpack2_arch = K6_pattern7_I24.arch -#power_tech_xml = /home/xitang/research/vtr_release/vtr_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK -power_tech_xml = /home/xitang/tangxifan-eda-tools/branches/fpga_flow/power_tech_properties/tsmc40nm.xml # Use relative path under VPR folder is OK - -[csv_tags] -mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: -mpack2_tags = BLE Number:|BLE Fill Rate: -vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles: -vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff diff --git a/fpga_flow/configs/tutorial/tuto.conf b/fpga_flow/configs/tutorial/tuto.conf deleted file mode 100644 index 85104383a..000000000 --- a/fpga_flow/configs/tutorial/tuto.conf +++ /dev/null @@ -1,30 +0,0 @@ -# Standard Configuration Example -[dir_path] -script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/ -benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC -yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys -odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe -cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit -abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc -abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc -abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc -mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1 -m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net -mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2 -vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr -rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial -ace_path = OPENFPGAPATHKEYWORD/ace2/ace - -[flow_conf] -flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr -vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml -mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf -mpack2_arch = K6_pattern7_I24.arch -power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK - -[csv_tags] -mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: -mpack2_tags = BLE Number:|BLE Fill Rate: -vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles: -vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff diff --git a/fpga_flow/regression_fpga_flow.sh b/fpga_flow/regression_fpga_flow.sh deleted file mode 100755 index c0968d9be..000000000 --- a/fpga_flow/regression_fpga_flow.sh +++ /dev/null @@ -1,29 +0,0 @@ -#! /bin/bash -# Exit if error occurs -set -e -# Make sure a clear start -pwd_path="$PWD" -task_name="k6_N10_regression_0" -config_file="$PWD/configs/regression/${task_name}.conf" -bench_txt="$PWD/benchmarks/List/test_modes.txt" -rpt_file="$PWD/csv_rpts/fpga_spice/${task_name}.csv" -task_file="$PWD/vpr_fpga_spice_task_lists/${task_name}" - -verilog_path="${PWD}/regression_MCNC" - -# FPGA-SPICE -rm -rf ${pwd_path}/results_regression -cd ${pwd_path}/scripts - -perl rewrite_path_in_file.pl -i $config_file - -# SRAM FPGA -# TT case -perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -remove_designs -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -end_flow_with_test -power - -rm -rf ${pwd_path}/results -rm -rf $verilog_path -cd ${pwd_path} - -echo "Netlists successfully generated and simulated" -exit 0 diff --git a/fpga_flow/run_benchmark.sh b/fpga_flow/run_benchmark.sh deleted file mode 100644 index c039011b5..000000000 --- a/fpga_flow/run_benchmark.sh +++ /dev/null @@ -1,71 +0,0 @@ -#! /bin/bash -# Exit if error occurs -set -e -# Make sure a clear start -default_task='lattice_benchmark' -pwd_path="$PWD" -task_name=${1:-$default_task} # run task defined in argument else run default task -config_file="$PWD/configs/${task_name}.conf" -bench_txt="$PWD/benchmarks/List/${task_name}.txt" -rpt_file="$PWD/csv_rpts/fpga_spice/${task_name}.csv" -task_file="$PWD/vpr_fpga_spice_task_lists/${task_name}" - -verilog_path="${PWD}/regression_${task_name}" - -config_file_final=$(echo ${config_file/.conf/_final.conf}) - -# List of argument passed to FPGA flow -vpr_config_flags=( - '-N 10' - '-K 6' - '-ace_d 0.5' - '-multi_thread 1' - '-vpr_fpga_x2p_rename_illegal_port' - '-vpr_fpga_verilog' - '-vpr_fpga_bitstream_generator' - '-vpr_fpga_verilog_print_autocheck_top_testbench' - '-vpr_fpga_verilog_include_timing' - '-vpr_fpga_verilog_include_signal_init' - '-vpr_fpga_verilog_formal_verification_top_netlist' - '-fix_route_chan_width' - '-vpr_fpga_verilog_include_icarus_simulator' - '-power' -) -# vpr_config_flags+=("$@") # Append provided arguments - -#=============== Argument Sanity Check ===================== -#Check if script running in correct (OpenFPGA/fpga_flow) folder -if [[ $pwd_path != *"OpenFPGA/fpga_flow"* ]]; then - echo "Error : Execute script from OpenFPGA/fpga_flow project folder" - exitflag=1 -fi - -#Check if fconfig and benchmark_list file exists -for filepath in $config_file $bench_txt; do - if [ ! -f $filepath ]; then - echo "$filepath File not found!" - exitflag=1 - fi -done -if [ -n "$exitflag" ]; then - echo "Terminating script . . . . . . " - exit 1 -fi -#======================================================= -#======== Replace variables in config file ============= - -#Extract OpenFPGA Project Path and Escape -OPENFPGAPATHKEYWORD=$(echo "$(echo $pwd_path | sed 's/.OpenFPGA.*$//')/OpenFPGA" | sed 's/\//\\\//g') - -# Create final config file with replaced keywords replaced variables -sed 's/OPENFPGAPATHKEYWORD/'"${OPENFPGAPATHKEYWORD}"'/g' $config_file >$config_file_final - -#==================Clean result, change directory and execute =============== -cd ${pwd_path}/scripts - -# perl fpga_flow.pl -conf ${config_file_final} -benchmark ${bench_txt} -rpt ${rpt_file} -vpr_fpga_verilog_dir $verilog_path $(echo "${vpr_config_flags[@]}") - -perl fpga_flow.pl -conf ${config_file_final} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power - -echo "Netlists successfully generated and simulated" -exit 0 diff --git a/fpga_flow/run_fpga_spice_testbench_study.sh b/fpga_flow/run_fpga_spice_testbench_study.sh deleted file mode 100755 index d31921d3c..000000000 --- a/fpga_flow/run_fpga_spice_testbench_study.sh +++ /dev/null @@ -1,32 +0,0 @@ -# Make sure a clear start -set output_conf = ${PWD}/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf -set benchmark_list = ${PWD}/benchmarks/fpga_spice_bench.txt -set benchmark_path = ${PWD}/benchmarks/FPGA_SPICE_bench/ -set arch_file = ${PWD}/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml -set flow_type = standard -set power_property_xml = ${PWD}/tech/PTM_45nm/45nm.xml -set csv_prefix = k6_N10_sram_tsmc40nm -set fpga_spice_flow_config_file = ${PWD}/vpr_fpga_spice_conf/sample.conf -set vpr_flow_report_dir = ${PWD}/csv_rpts/fpga_spice/ -set fpga_spice_flow_report_dir = ${PWD}/vpr_fpga_spice_csv_rpts/ -set fpga_spice_task_list_dir = ${PWD}/vpr_fpga_spice_task_lists/ - -# Sweep Corner Cases -set corner_list = (TT) -#set corner_list = (TT FF SS MC) - -foreach j ($corner_list) - #rm -rf ./results - if ($j == MC) then - set mc_opt = (-monte_carlo detail_rpt) - else - set mc_opt = () - endif - - perl scripts/generate_config.pl -output_conf $output_conf -arch $arch_file -benchmark_path $benchmark_path -flow_type $flow_type -power_property_xml $power_property_xml - - perl scripts/fpga_flow.pl -conf $output_conf -benchmark $benchmark_list -rpt ${vpr_flow_report_dir}${csv_prefix}_$j\.csv -N 10 -K 6 -power -remove_designs -multi_thread 1 -vpr_fpga_spice ${fpga_spice_task_list_dir}${csv_prefix} -vpr_fpga_spice_rename_illegal_port -vpr_fpga_spice_sim_mt_num 16 -vpr_fpga_spice_print_top_tb -vpr_fpga_spice_print_component_tb -vpr_fpga_spice_print_grid_tb - - perl scripts/run_fpga_spice.pl -conf ${fpga_spice_flow_config_file} -task ${fpga_spice_task_list_dir}${csv_prefix}_${flow_type}.txt -rpt ${fpga_spice_flow_report_dir}${csv_prefix}_$j\.csv $mc_opt -parse_top_tb -multi_thread 2 -parse_pb_mux_tb -parse_cb_mux_tb -parse_sb_mux_tb -parse_lut_tb -parse_hardlogic_tb -parse_grid_tb -parse_cb_tb -parse_sb_tb - -end diff --git a/fpga_flow/scripts/convert_blif.pl b/fpga_flow/scripts/convert_blif.pl deleted file mode 100755 index 483fd7dea..000000000 --- a/fpga_flow/scripts/convert_blif.pl +++ /dev/null @@ -1,106 +0,0 @@ -#!usr/bin/perl -w -use strict; -#use Shell; -#Use the time -use Time::gmtime; - -#Get Date -my $mydate = gmctime(); - -my ($fname,$frpt); - -sub print_usage() -{ - print "VPR accepts a certain format of blif so this script checks the latches and corrects them if needed\n"; - print "Usage:\n"; - print " perl [-options]\n"; - print " Options:(Mandatory!)\n"; - print " -i \n"; - print " -o \n"; - print "\n"; - return 1; -} - -sub opts_read() -{ - if (-1 == $#ARGV) - { - print "Error: No input argument!\n"; - &print_usage(); - exit(1); - } - else - { - for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++) - { - if ("-i" eq $ARGV[$iargv]) - {$fname = $ARGV[$iargv+1];} - elsif ("-o" eq $ARGV[$iargv]) - {$frpt = $ARGV[$iargv+1];} - } - } - return 1; -} - -sub scan_blif() -{ - my ($line,$lines); - my @tokens; - - # Open src file - open(FIN, "< $fname") or die "Fail to open $fname!\n"; - # Open des file - open(FOUT, "> $frpt") or die "Fail to open $frpt!\n"; - while(defined($line = )) { - chomp $line; - # Replace the < and > with [ and ], VPR does not support... - $line =~ s//]/g; - # Check if this line start with ".latch", which we cares only - if ($line =~ m/\.names/) { - # check the continue line - $lines = $line; # empty the buffer - while($lines =~ m/\\$/) { - $line = ; - chomp $line; - $lines =~ s/\\$//; - $lines = $lines.$line; - } - @tokens = split('\s+',$lines); - if (($#tokens - 1) == 3) { - print FOUT ".gate CARRY a=$tokens[1] b=$tokens[2] c=$tokens[3] O=$tokens[4]\n"; - } elsif (($#tokens - 1) == 2) { - print FOUT ".gate AND a=$tokens[1] b=$tokens[2] O=$tokens[3]\n"; - } elsif (($#tokens - 1) == 1) { - $line = ; - if ($line =~ m/^0/) { - print FOUT ".gate INV a=$tokens[1] O=$tokens[2]\n"; - } else { - print FOUT ".gate BUF a=$tokens[1] O=$tokens[2]\n"; - } - } elsif (($#tokens - 1) == 0) { # constant generator - $line = ; - if ($line =~ m/^0/) { - print FOUT ".gate ZERO O=$tokens[1]\n"; - } else { - print FOUT ".gate ONE O=$tokens[1]\n"; - } - } - } else { - print FOUT "$line\n"; - } - } - close(FIN); - close(FOUT); - return 1; -} - -sub main() -{ - &opts_read(); - &scan_blif(); - return 1; -} - -&main(); -exit(1); diff --git a/fpga_flow/scripts/fpga_arch_gen.pl b/fpga_flow/scripts/fpga_arch_gen.pl deleted file mode 100755 index dbda80108..000000000 --- a/fpga_flow/scripts/fpga_arch_gen.pl +++ /dev/null @@ -1,111 +0,0 @@ -#!usr/bin/perl -w -use strict; -#use Shell; -use Time::gmtime; -use Switch; -use File::Path; -use Cwd; - -my $mydate = gmctime(); -my $cwd = getcwd(); - -sub gen_fpga_arch($ $) -{ - my ($k,$n) = @_; - my ($arch_file) = ("tmp.xml"); - my ($i) = int(0.5+$k*($n+1)/2); - print "K=$k N=$n I=$i\n"; - - my ($seq_out_up) = (2*$n-1); - - my %ble_h; - my $ble_ptr = \%ble_h; - - my @comb; - my @seq; - my ($j); - - for ($j=0; $j<$k*$n; $j++) { - my ($idx) = int($j/$k); - print "idx=$idx"; - my ($input) = $j%$k; - print " input=$input\n"; - $ble_ptr->{"ble_in$j"}->{ble_idx} = $idx; - $ble_ptr->{"ble_in$j"}->{ble_input_idx} = $input; - if ($input < $idx) { - $ble_ptr->{"ble_in$j"}->{comb_in} = $input; - } - else { - $ble_ptr->{"ble_in$j"}->{comb_in} = -1; - } - $ble_ptr->{"ble$idx"}->{"input$input"}->{idx} = $j; - } - - my ($iseq,$icomb) = (0,0); - for (my $ible=0; $ible<$n; $ible++) { - for (my $in=0; $in<$ible; $in++) { - if ($in < $ible) { - $comb[$icomb] = $ble_ptr->{"ble$ible"}->{"input$in"}->{idx}; - $icomb++; - } - } - for (my $in=$ible; $in<$k; $in++) { - if ($in < $k) { - $seq[$iseq] = $ble_ptr->{"ble$ible"}->{"input$in"}->{idx}; - $iseq++; - } - } - } - - open (FARCH," > $arch_file") or die "Fail to create $arch_file"; - print FARCH "\n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH "\n"; - - my ($imux) = (0); - foreach my $tmp(@comb) { - print FARCH " {"ble_in$tmp"}->{comb_in}."]\" output=\"ble.in[$tmp]\">\n"; - print FARCH " \n"; - print FARCH " {\"ble_in$tmp\"}->{comb_in}] \" out_port=\"ble.in[$tmp]\"/>\n"; - print FARCH " \n"; - $imux++; - } - for (my $i=0; $i<$n; $i++) { - my $j = $i + $n; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - $imux++; - } - print FARCH " \n"; - - -} - -sub main() -{ - my ($k,$n) = (6,7); - &gen_fpga_arch($k,$n); -} - -&main(); diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl deleted file mode 100644 index ffe793267..000000000 --- a/fpga_flow/scripts/fpga_flow.pl +++ /dev/null @@ -1,3661 +0,0 @@ -#!usr/bin/perl -w -# use the strict mode -use strict; -# Use the Shell enviornment -#use Shell; -# Use the time -use Time::gmtime; -# Use switch module -#use Switch; -use File::Path; -use Cwd; -use FileHandle; -# Multi-thread support -use threads; -#use threads::shared; - -# Date -my $mydate = gmctime(); -# Current Path -my $cwd = getcwd(); - -# Global Variants -my ($max_route_width_retry) = (1000); -# input Option Hash -my %opt_h; -my $opt_ptr = \%opt_h; -# configurate file hash -my %conf_h; -my $conf_ptr = \%conf_h; -# reports has -my %rpt_h; -my $rpt_ptr = \%rpt_h; - -# Benchmarks -my @benchmark_names; -my %benchmarks; -my $benchmarks_ptr = \%benchmarks; -my $verilog_benchmark; - -# Supported flows -my @supported_flows = ("standard", - "vtr_mccl", - "mccl", - "mig_mccl", - "mpack2", - "mpack1", - "vtr", - "vtr_standard", - "yosys_vpr", - "vpr_only"); -my %selected_flows; - -# Configuration file keywords list -# Category for conf file. -# main category : 1st class -my @mctgy; -# sub category : 2nd class -my @sctgy; -# Initialize these categories -@mctgy = ("dir_path", - "flow_conf", - "csv_tags", - ); -# refer to the keywords of dir_path -@{$sctgy[0]} = ("script_base", - "benchmark_dir", - "yosys_path", - "odin2_path", - "cirkit_path", - "abc_mccl_path", - "abc_path", - "abc_with_bb_support_path", - "mpack1_path", - "m2net_path", - "mpack2_path", - "vpr_path", - "rpt_dir", - "ace_path", - ); -# refer to the keywords of flow_type -@{$sctgy[1]} = ("flow_type", - "vpr_arch", - "mpack2_arch", - "m2net_conf", - "mpack1_abc_stdlib", - "power_tech_xml", - ); -# refer to the keywords of csv_tags -@{$sctgy[2]} = ("mpack1_tags", - "mpack2_tags", - "vpr_tags", - "vpr_power_tags" - ); - -# ----------Subrountines------------# -# Print TABs and strings -sub tab_print($ $ $) -{ - my ($FILE,$str,$num_tab) = @_; - my ($my_tab) = (" "); - - for (my $i = 0; $i < $num_tab; $i++) { - print $FILE "$my_tab"; - } - print $FILE "$str"; -} - -# Create paths if it does not exist. -sub generate_path($) -{ - my ($mypath) = @_; - if (!(-e "$mypath")) - { - mkpath "$mypath"; - print "Path($mypath) does not exist...Create it.\n"; - } - return 0; -} - -# Print the usage -sub print_usage() -{ - print "Usage:\n"; - print " fpga_flow [-options ]\n"; - print " Mandatory options: \n"; - print " -conf : specify the basic configuration files for fpga_flow\n"; - print " -benchmark : the configuration file contains benchmark file names\n"; - print " -rpt : CSV file consists of data\n"; - print " -N : N-LUT/Matrix\n"; - print " Other Options:\n"; - print " [ General ] \n"; - print " \t-matlab_rpt : .m file consists of data compatible to matlab scripts. Specify the data name to be appeared in the script\n"; - print " \t-I : Number of inputs of a CLB, mandatory when mpack1 flow is chosen\n"; - print " \t-K : K-LUT, mandatory when standard flow is chosen\n"; - print " \t-M : M-Matrix, mandatory when mpack1 flow is chosen\n"; - print " \t-power : run power estimation oriented flow\n"; - print " \t-black_box_ace: run activity estimation with black box support. It increase the power.\n"; - print " \t-remove_designs: remove all the old results.\n"; - print " \t-multi_thread : turn on the mutli-thread mode, specify the number of threads\n"; - print " \t-multi_task : turn on the mutli-task mode\n"; - print " \t-parse_results_only : only parse the flow results and write CSV report.\n"; - print " \t-debug : debug mode\n"; - print " \t-help : print usage\n"; - print " [ ODIN II ] \n"; - print " \t-min_hard_adder_size: min. size of hard adder in carry chain defined in Arch XML.(Default:1)\n"; - print " \t-mem_size: size of memory, mandatory when VTR/VTR_MCCL/VTR_MIG_MCCL flow is chosen\n"; - print " \t-odin2_carry_chain_support: turn on the carry_chain support only valid for VTR_MCCL/VTR_MIG_MCCL flow \n"; - print " [ ABC ] \n"; - print " \t-abc_scl : run ABC optimization for sequential circuits, mandatory when VTR flow is selected.\n"; - print " \t-abc_verilog_rewrite : run ABC to convert a blif netlist to a Verilog netlist.\n"; - print " [ ACE ] \n"; - print " \t-ace_p : specify the default signal probablity of PIs in ACE2.\n"; - print " \t-ace_d : specify the default signal density of PIs in ACE2.\n"; - print " [ VPR - Original Version ] \n"; - print " \t-vpr_timing_pack_off : turn off the timing-driven pack for vpr.\n"; - print " \t-vpr_place_clb_pin_remap: turn on place_clb_pin_remap in VPR.\n"; - print " \t-vpr_max_router_iteration : specify the max router iteration in VPR.\n"; - print " \t-vpr_route_breadthfirst : use the breadth-first routing algorithm of VPR.\n"; - print " \t-vpr_use_tileable_route_chan_width: turn on the conversion to tileable_route_chan_width in VPR.\n"; - print " \t-min_route_chan_width : turn on routing with * min_route_chan_width.\n"; - print " \t-fix_route_chan_width : turn on routing with a fixed route_chan_width, defined in benchmark configuration file.\n"; - print " [ VPR - FPGA-X2P Extension ] \n"; - print " \t-vpr_fpga_x2p_rename_illegal_port : turn on renaming illegal ports option of VPR FPGA SPICE\n"; - print " \t-vpr_fpga_x2p_signal_density_weight : specify the option signal_density_weight of VPR FPGA SPICE\n"; - print " \t-vpr_fpga_x2p_sim_window_size : specify the option sim_window_size of VPR FPGA SPICE\n"; - print " \t-vpr_fpga_x2p_compact_routing_hierarchy : allow routing block modularization\n"; - print " [ VPR - FPGA-SPICE Extension ] \n"; - print " \t-vpr_fpga_spice : turn on SPICE netlists print-out in VPR, specify a task file\n"; - print " \t-vpr_fpga_spice_sim_mt_num : specify the option sim_mt_num of VPR FPGA SPICE\n"; - print " \t-vpr_fpga_spice_print_component_tb : print component-level testbenches in VPR FPGA SPICE\n"; - print " \t-vpr_fpga_spice_print_grid_tb : print Grid-level testbenches in VPR FPGA SPICE\n"; - print " \t-vpr_fpga_spice_print_top_tb : print full-chip testbench in VPR FPGA SPICE\n"; - print " \t-vpr_fpga_spice_leakage_only : turn on leakage_only mode in VPR FPGA SPICE\n"; - print " \t-vpr_fpga_spice_parasitic_net_estimation_off : turn off parasitic_net_estimation in VPR FPGA SPICE\n"; - print " \t-vpr_fpga_spice_testbench_load_extraction_off : turn off testbench_load_extraction in VPR FPGA SPICE\n"; - print " \t-vpr_fpga_spice_simulator_path : Specify simulator path\n"; - print " [ VPR - FPGA-Verilog Extension ] \n"; - print " \t-vpr_fpga_verilog : turn on Verilog Generator of VPR FPGA SPICE\n"; - print " \t-vpr_fpga_verilog_dir : provide the path where generated verilog files will be written\n"; - print " \t-vpr_fpga_verilog_include_timing : turn on printing delay specification in Verilog files\n"; - print " \t-vpr_fpga_verilog_include_signal_init : turn on printing signal initialization in Verilog files\n"; - print " \t-vpr_fpga_verilog_print_autocheck_top_testbench: turn on printing autochecked top-level testbench for Verilog Generator of VPR FPGA SPICE\n"; - print " \t-vpr_fpga_verilog_formal_verification_top_netlist : turn on printing formal top Verilog files\n"; - print " \t-vpr_fpga_verilog_include_icarus_simulator : Add syntax and definition required to use Icarus Verilog simulator\n"; - print " \t-vpr_fpga_verilog_print_user_defined_template : \n"; - print " \t-vpr_fpga_verilog_print_report_timing_tcl : Generate tcl script useful for timing report generation\n"; - print " \t-vpr_fpga_verilog_report_timing_rpt_path : Specify path for report timing\n"; - print " \t-vpr_fpga_verilog_print_sdc_pnr : Generate sdc file to constraint Hardware P&R\n"; - print " \t-vpr_fpga_verilog_print_sdc_analysis : Generate sdc file to do STA\n"; - print " \t-vpr_fpga_verilog_print_top_tb : turn on printing top-level testbench for Verilog Generator of VPR FPGA SPICE\n"; - print " \t-vpr_fpga_verilog_print_input_blif_tb : turn on printing testbench for input blif file in Verilog Generator of VPR FPGA SPICE\n"; - print " \t-vpr_fpga_verilog_print_modelsim_autodeck : turn on printing modelsim simulation script\n"; - print " \t-vpr_fpga_verilog_explicit_mapping\n"; - print " [ VPR - FPGA-Bitstream Extension ] \n"; - print " \t-vpr_fpga_bitstream_generator: turn on FPGA-SPICE bitstream generator\n"; - exit(1); - return 1; -} - -sub spot_option($ $) -{ - my ($start,$target) = @_; - my ($arg_no,$flag) = (-1,"unfound"); - for (my $iarg = $start; $iarg < $#ARGV+1; $iarg++) - { - if ($ARGV[$iarg] eq $target) - { - if ("found" eq $flag) - { - print "Error: Repeated Arguments!(IndexA: $arg_no,IndexB: $iarg)\n"; - &print_usage(); - } - else - { - $flag = "found"; - $arg_no = $iarg; - } - } - } - # return the arg_no if target is found - # or return -1 when target is missing - return $arg_no; -} - -# Specify in the input list, -# 1. Option Name -# 2. Whether Option with value. if yes, choose "on" -# 3. Whether Option is mandatory. If yes, choose "on" -sub read_opt_into_hash($ $ $) -{ - my ($opt_name,$opt_with_val,$mandatory) = @_; - # Check the -$opt_name - my ($opt_fact) = ("-".$opt_name); - my ($cur_arg) = (0); - my ($argfd) = (&spot_option($cur_arg,"$opt_fact")); - if ($opt_with_val eq "on") - { - if (-1 != $argfd) - { - if ($ARGV[$argfd+1] =~ m/^-/) - { - print "The next argument cannot start with '-'!\n"; - print "it implies an option!\n"; - } - else - { - $opt_ptr->{"$opt_name\_val"} = $ARGV[$argfd+1]; - $opt_ptr->{"$opt_name"} = "on"; - } - } - else - { - $opt_ptr->{"$opt_name"} = "off"; - if ($mandatory eq "on") - { - print "Mandatory option: $opt_fact is missing!\n"; - &print_usage(); - } - } - } - else - { - if (-1 != $argfd) - { - $opt_ptr->{"$opt_name"} = "on"; - } - else - { - $opt_ptr->{"$opt_name"} = "off"; - if ($mandatory eq "on") - { - print "Mandatory option: $opt_fact is missing!\n"; - &print_usage(); - } - } - } - return 0; -} - -# Read options -sub opts_read() -{ - # if no arguments detected, print the usage. - if (-1 == $#ARGV) { - print "Error : No input arguments!\n"; - print "Help desk:\n"; - &print_usage(); - exit(1); - } - # Read in the options - my ($cur_arg,$arg_found); - $cur_arg = 0; - print "Analyzing your options...\n"; - # Read the options with internal options - my $argfd; - # Check help fist - $argfd = &spot_option($cur_arg,"-help"); - if (-1 != $argfd) { - print "Help desk:\n"; - &print_usage(); - } - # Then Check the debug with highest priority - $argfd = &spot_option($cur_arg,"-debug"); - if (-1 != $argfd) { - $opt_ptr->{"debug"} = "on"; - } else { - $opt_ptr->{"debug"} = "off"; - } - # Check mandatory options - # Check the -conf - # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" - &read_opt_into_hash("conf","on","on"); - &read_opt_into_hash("benchmark","on","on"); - &read_opt_into_hash("rpt","on","on"); - &read_opt_into_hash("matlab_rpt","on","off"); # Add an option to output report file compatible to matlab scripts - &read_opt_into_hash("N","on","on"); - &read_opt_into_hash("K","on","off"); - &read_opt_into_hash("I","on","off"); - &read_opt_into_hash("M","on","off"); - &read_opt_into_hash("power","off","off"); - &read_opt_into_hash("vpr_place_clb_pin_remap","off","off"); - &read_opt_into_hash("black_box_ace","off","off"); - &read_opt_into_hash("remove_designs","off","off"); - &read_opt_into_hash("abc_scl","off","off"); - &read_opt_into_hash("abc_verilog_rewrite","off","off"); - &read_opt_into_hash("ace_p","on","off"); - &read_opt_into_hash("ace_d","on","off"); - &read_opt_into_hash("vpr_timing_pack_off","off","off"); - &read_opt_into_hash("vpr_route_breadthfirst","off","off"); - &read_opt_into_hash("vpr_use_tileable_route_chan_width","off","off"); - &read_opt_into_hash("min_route_chan_width","on","off"); - &read_opt_into_hash("fix_route_chan_width","off","off"); - &read_opt_into_hash("vpr_max_router_iteration","on","off"); - &read_opt_into_hash("multi_task","on","off"); - &read_opt_into_hash("multi_thread","on","off"); - &read_opt_into_hash("parse_results_only","off","off"); - - # VTR/VTR_MCCL/VTR_MIG_MCCL flow options - # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" - &read_opt_into_hash("min_hard_adder_size","on","off"); - &read_opt_into_hash("mem_size","on","off"); - &read_opt_into_hash("odin2_carry_chain_support","off","off"); - - # FPGA-SPICE options - # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" - &read_opt_into_hash("vpr_fpga_spice","on","off"); - &read_opt_into_hash("vpr_fpga_x2p_rename_illegal_port","off","off"); - &read_opt_into_hash("vpr_fpga_x2p_signal_density_weight","on","off"); - &read_opt_into_hash("vpr_fpga_x2p_sim_window_size","on","off"); - &read_opt_into_hash("vpr_fpga_x2p_compact_routing_hierarchy","off","off"); - &read_opt_into_hash("vpr_fpga_spice_sim_mt_num","on","off"); - &read_opt_into_hash("vpr_fpga_spice_print_component_tb","off","off"); - &read_opt_into_hash("vpr_fpga_spice_print_grid_tb","off","off"); - &read_opt_into_hash("vpr_fpga_spice_print_top_tb","off","off"); - &read_opt_into_hash("vpr_fpga_spice_leakage_only","off","off"); - &read_opt_into_hash("vpr_fpga_spice_parasitic_net_estimation_off","off","off"); - &read_opt_into_hash("vpr_fpga_spice_testbench_load_extraction_off","off","off"); - &read_opt_into_hash("vpr_fpga_spice_simulator_path","on","off"); - - # FPGA-Verilog options - # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" - &read_opt_into_hash("vpr_fpga_verilog","off","off"); - &read_opt_into_hash("vpr_fpga_verilog_print_top_tb","off","off"); - &read_opt_into_hash("vpr_fpga_verilog_print_input_blif_tb","off","off"); - &read_opt_into_hash("vpr_fpga_bitstream_generator","off","off"); - &read_opt_into_hash("vpr_fpga_verilog_print_autocheck_top_testbench","off","off"); - &read_opt_into_hash("vpr_fpga_verilog_dir","on","off"); - &read_opt_into_hash("vpr_fpga_verilog_print_modelsim_autodeck","on","off"); - &read_opt_into_hash("vpr_fpga_verilog_include_timing","off","off"); - &read_opt_into_hash("vpr_fpga_verilog_include_signal_init","off","off"); - &read_opt_into_hash("vpr_fpga_verilog_formal_verification_top_netlist","off","off"); - &read_opt_into_hash("vpr_fpga_verilog_include_icarus_simulator","off","off"); - &read_opt_into_hash("vpr_fpga_verilog_print_report_timing_tcl","off","off"); - &read_opt_into_hash("vpr_fpga_verilog_report_timing_rpt_path","on","off"); - &read_opt_into_hash("vpr_fpga_verilog_print_sdc_pnr","off","off"); - &read_opt_into_hash("vpr_fpga_verilog_print_sdc_analysis","off","off"); - &read_opt_into_hash("vpr_fpga_verilog_print_user_defined_template","off","off"); - &read_opt_into_hash("vpr_fpga_verilog_explicit_mapping","off","off"); - - # Regression test option - &read_opt_into_hash("end_flow_with_test","off","off"); - - &print_opts(); - - return 0; -} - -# List the options -sub print_opts() -{ - print "List your options\n"; - - while(my ($key,$value) = each(%opt_h)) - {print "$key : $value\n";} - - return 0; -} - - -# Read each line and ignore the comments which starts with given arg -# return the valid information of line -sub read_line($ $) -{ - my ($line,$com) = @_; - my @chars; - if (defined($line)) - { - @chars = split/$com/,$line; - if (!($line =~ m/[\w\d]/)) - {$chars[0] = undef;} - if ($line =~ m/^\s*$com/) - {$chars[0] = undef;} - } - else - {$chars[0] = undef;} - if (defined($chars[0])) - { - $chars[0] =~ s/^(\s+)//g; - $chars[0] =~ s/(\s+)$//g; - } - return $chars[0]; -} - -# Check each keywords has been defined in configuration file -sub check_keywords_conf() -{ - for (my $imcg = 0; $imcg<$#mctgy+1; $imcg++) - { - for (my $iscg = 0; $iscg<$#{$sctgy[$imcg]}+1; $iscg++) - { - if (defined($conf_ptr->{$mctgy[$imcg]}->{$sctgy[$imcg]->[$iscg]}->{val})) - { - if ("on" eq $opt_ptr->{debug}) - { - print "Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) = "; - print "$conf_ptr->{$mctgy[$imcg]}->{$sctgy[$imcg]->[$iscg]}->{val}"; - print "\n"; - } - } - else - {die "Error: Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) is missing!\n";} - } - } - return 0; -} - -# Read the configuration file -sub read_conf() -{ - # Read in these key words - my ($line,$post_line); - my @equation; - my $cur = "unknown"; - open (CONF, "< $opt_ptr->{conf_val}") or die "Fail to open $opt_ptr->{conf_val}!\n"; - print "Reading $opt_ptr->{conf_val}...\n"; - while(defined($line = )) - { - chomp $line; - $post_line = &read_line($line,"#"); - if (defined($post_line)) - { - if ($post_line =~ m/\[(\w+)\]/) - {$cur = $1;} - elsif ("unknown" eq $cur) - { - die "Error: Unknown tags for this line!\n$post_line\n"; - } - else - { - $post_line =~ s/\s//g; - @equation = split /=/,$post_line; - $conf_ptr->{$cur}->{$equation[0]}->{val} = $equation[1]; - } - } - } - # Check these key words - print "Read complete!\n"; - &check_keywords_conf(); - print "Checking these keywords..."; - print "Successfully\n"; - close(CONF); - return 0; -} - -sub read_benchmarks() -{ - # Read in file names - my ($line,$post_line,$cur); - $cur = 0; - open (FCONF,"< $opt_ptr->{benchmark_val}") or die "Fail to open $opt_ptr->{benchmark_val}!\n"; - print "Reading $opt_ptr->{benchmark_val}...\n"; - while(defined($line = )) - { - chomp $line; - $post_line = &read_line($line,"#"); - if (defined($post_line)) { - $post_line =~ s/\s+//g; - my @tokens = split(",",$post_line); - # first is the benchmark name, - #the second is the channel width, if applicable - if ($tokens[0]) { - $benchmark_names[$cur] = $tokens[0]; - } else { - die "ERROR: invalid definition for benchmarks!\n"; - } - $benchmarks_ptr->{"$benchmark_names[$cur]"}->{fix_route_chan_width} = $tokens[1]; - $cur++; - } - } - print "Benchmarks(total $cur):\n"; - foreach my $temp(@benchmark_names) - {print "$temp\n";} - close(FCONF); - return 0; -} - -# Input program path is like "~/program_dir/program_name" -# We split it from the scalar -sub split_prog_path($) -{ - my ($prog_path) = @_; - my @path_elements = split /\//,$prog_path; - my ($prog_dir,$prog_name); - - $prog_name = $path_elements[$#path_elements]; - $prog_dir = $prog_path; - $prog_dir =~ s/$prog_name$//g; - - return ($prog_dir,$prog_name); -} - -sub check_blif_type($) -{ - my ($blif) = @_; - my ($line); - open (BLIF, "< $blif") or die "Fail to open $blif!\n"; - while(defined($line = )) { - chomp $line; - if ($line =~ /^\.latch/) { - close(BLIF); - return "seq"; - } - } - close(BLIF); - return "comb"; -} - -# Check Options -sub check_opts() { - # Task 1: min_chan_width > 1 - if (("on" eq $opt_ptr->{min_route_chan_width}) - &&(1. > $opt_ptr->{min_route_chan_width_val})) { - die "ERROR: Invalid -min_chan_width, should be at least 1.0!\n"; - } - # Task 2: check mandatory option when flow mpack1 is chosen - if ("on" eq $selected_flows{"mpack1"}->{flow_status}) { - if ("off" eq $opt_ptr->{M}) { - die "ERROR: Option -M should be specified when flow mpack1 is selected!\n"; - } - if ("off" eq $opt_ptr->{I}) { - die "ERROR: Option -I should be specified when flow mpack1 is selected!\n"; - } - } - # Task 3: check mandatory options when flow vtr is chosen - if ("on" eq $selected_flows{"vtr"}->{flow_status}) { - if ("off" eq $opt_ptr->{mem_size}) { - die "ERROR: Option -mem_size should be specified when flow vtr is selected\n"; - } - if ("off" eq $opt_ptr->{K}) { - die "ERROR: Option -K should be specified when flow vtr is selected\n"; - } - if ("off" eq $opt_ptr->{abc_scl}) { - die "ERROR: Option -abc_scl should be specified when flow vtr is selected\n"; - } - } - # Task 3: check mandatory options when flow vtr_standard or standard is chosen - if (("on" eq $selected_flows{"standard"}->{flow_status}) - ||("on" eq $selected_flows{"vtr_standard"}->{flow_status})) { - if ("off" eq $opt_ptr->{K}) { - die "ERROR: Option -K should be specified when flow vtr_standard|standard is selected\n"; - } - } -} - -# Run ABC with standard library mapping -sub run_abc_libmap($ $ $) -{ - my ($bm,$blif_out,$log) = @_; - # Get ABC path - my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_path}->{val}); - - chdir $abc_dir; - my ($mpack1_stdlib) = ($conf_ptr->{flow_conf}->{mpack1_abc_stdlib}->{val}); - # Run MPACK ABC - my ($abc_seq_optimize) = (""); - if (("on" eq $opt_ptr->{abc_scl})&&("seq" eq &check_blif_type($bm))) { - ($abc_seq_optimize) = ("scl -l;"); - } - # !!! For standard library, we cannot use sweep ??? - system("./$abc_name -c \"read_blif $bm; resyn2; read_library $mpack1_stdlib; $abc_seq_optimize map -v; write_blif $blif_out; quit;\" > $log"); - chdir $cwd; -} - -# Rewrite the verilog after optimization -sub run_rewrite_verilog($ $ $ $ $) { - my ($blif, $path, $benchmark, $bm, $log) = @_; - my ($new_verilog) = "$path/$benchmark".".v"; - my ($cmd_log) = ($log); - $cmd_log =~ s/\.log$/_rewrite_verilog\.ys/; - - # Get Yosys path - my ($yosys_dir,$yosys_name) = &split_prog_path($conf_ptr->{dir_path}->{yosys_path}->{val}); - - print "Entering $yosys_dir\n"; - chdir $yosys_dir; - my ($lut_num) = $opt_ptr->{K_val}; - - # Create yosys synthesize script - my ($YOSYS_CMD_FH) = (FileHandle->new); - if ($YOSYS_CMD_FH->open("> $cmd_log")) { - print "INFO: auto generating cmds for Yosys ($cmd_log) ...\n"; - } else { - die "ERROR: fail to auto generating cmds for Yosys ($cmd_log) ...\n"; - } - # Output the standard format (refer to VTR_flow script) - print $YOSYS_CMD_FH "# Yosys rewriting verilog script for $bm\n"; - print $YOSYS_CMD_FH "read_blif $blif\n"; - print $YOSYS_CMD_FH "write_verilog $new_verilog\n"; - - close($YOSYS_CMD_FH); - # - # Create a local copy for the commands - - system("./$yosys_name $cmd_log > $log"); - - if (!(-e $new_verilog)) { - die "ERROR: Yosys fail at rewriting benchmark $bm.\n"; - } - - print "Leaving $yosys_dir\n"; - chdir $cwd; - - return ($new_verilog); -} - -# Run yosys synthesis with ABC LUT mapping -sub run_yosys_fpgamap($ $ $ $) { - my ($bm, $bm_path, $blif_out, $log) = @_; - my ($cmd_log) = ($log); - $cmd_log =~ s/log$/ys/; - - # Get Yosys path - my ($yosys_dir,$yosys_name) = &split_prog_path($conf_ptr->{dir_path}->{yosys_path}->{val}); - - print "Entering $yosys_dir\n"; - chdir $yosys_dir; - my ($lut_num) = $opt_ptr->{K_val}; - - # Create yosys synthesize script - my ($YOSYS_CMD_FH) = (FileHandle->new); - if ($YOSYS_CMD_FH->open("> $cmd_log")) { - print "INFO: auto generating cmds for Yosys ($cmd_log) ...\n"; - } else { - die "ERROR: fail to auto generating cmds for Yosys ($cmd_log) ...\n"; - } - # Output the standard format (refer to VTR_flow script) - print $YOSYS_CMD_FH "# Yosys synthesis script for $bm\n"; - print $YOSYS_CMD_FH "# read Verilog \n"; - print $YOSYS_CMD_FH "read_verilog -nolatches $bm_path\n"; - print $YOSYS_CMD_FH "\n"; - - print $YOSYS_CMD_FH "# Technology mapping\n"; - print $YOSYS_CMD_FH "hierarchy -top $bm\n"; - print $YOSYS_CMD_FH "proc\n"; - print $YOSYS_CMD_FH "techmap -D NO_LUT -map +/adff2dff.v\n"; - print $YOSYS_CMD_FH "\n"; - - print $YOSYS_CMD_FH "# Synthesis\n"; - print $YOSYS_CMD_FH "synth -top $bm -flatten\n"; - print $YOSYS_CMD_FH "clean\n"; - print $YOSYS_CMD_FH "\n"; - - print $YOSYS_CMD_FH "# LUT mapping \n"; - print $YOSYS_CMD_FH "abc -lut $lut_num\n"; - print $YOSYS_CMD_FH "\n"; - - print $YOSYS_CMD_FH "# Check \n"; - print $YOSYS_CMD_FH "synth -run check\n"; - print $YOSYS_CMD_FH "\n"; - - print $YOSYS_CMD_FH "# Clean and output blif \n"; - print $YOSYS_CMD_FH "opt_clean -purge\n"; - print $YOSYS_CMD_FH "write_blif $blif_out\n"; - - close($YOSYS_CMD_FH); - # - # Create a local copy for the commands - - system("./$yosys_name $cmd_log > $log"); - - if (!(-e $blif_out)) { - die "ERROR: Fail Yosys for benchmark $bm.\n"; - } - - print "Leaving $yosys_dir\n"; - chdir $cwd; -} - -# Run ABC by FPGA-oriented synthesis -sub run_abc_fpgamap($ $ $) -{ - my ($bm,$blif_out,$log) = @_; - my ($cmd_log) = ($log."cmd"); - # Get ABC path - my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_path}->{val}); - - my ($lut_num) = $opt_ptr->{K_val}; - # Before we run this blif, identify it is a combinational or sequential - my ($abc_seq_optimize) = (""); - if (("on" eq $opt_ptr->{abc_scl})&&("seq" eq &check_blif_type($bm))) { - ($abc_seq_optimize) = ("scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;"); - } - my ($fpga_synthesis_method) = ("if"); - #my ($fpga_synthesis_method) = ("fpga"); - # - my ($dump_verilog) = (""); - if ("on" eq $opt_ptr->{abc_verilog_rewrite}) { - $dump_verilog = "write_verilog $bm.v"; - } - # Run FPGA ABC - #`csh -cx './$abc_name -c \"read $bm; resyn2; $fpga_synthesis_method -K $lut_num; $abc_seq_optimize $abc_seq_optimize sweep; write_blif $blif_out; quit\" > $log'`; - my ($ABC_CMD_FH) = (FileHandle->new); - if ($ABC_CMD_FH->open("> $cmd_log")) { - print "INFO: auto generating cmds for ABC ($cmd_log) ...\n"; - } else { - die "ERROR: fail to auto generating cmds for ABC ($cmd_log) ...\n"; - } - # Output the standard format (refer to VTR_flow script) - print $ABC_CMD_FH "read $bm; resyn; resyn2; scleanup; $fpga_synthesis_method -K $lut_num; sweep; $abc_seq_optimize write_blif $blif_out; $dump_verilog; quit\n"; - - close($ABC_CMD_FH); - # - # Create a local copy for the commands - # - print "Entering $abc_dir\n"; - chdir $abc_dir; - - system("./$abc_name -F $cmd_log > $log"); - - if (!(-e $blif_out)) { - die "ERROR: Fail ABC for benchmark $bm.\n"; - } - - if (("on" eq $opt_ptr->{abc_verilog_rewrite})&&(!(-e "$bm.v"))) { - die "ERROR: ABC verilog rewrite failed for benchmark $bm!\n"; - } - - print "Leaving $abc_dir\n"; - chdir $cwd; -} - -# Run ABC by FPGA-oriented synthesis -sub run_abc_bb_fpgamap($ $ $) { - my ($bm,$blif_out,$log) = @_; - my ($cmd_log) = ($log."cmd"); - - # Get ABC path - my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_with_bb_support_path}->{val}); - my ($lut_num) = $opt_ptr->{K_val}; - # Before we run this blif, identify it is a combinational or sequential - my ($abc_seq_optimize) = (""); - if (("on" eq $opt_ptr->{abc_scl})&&("seq" eq &check_blif_type($bm))) { - ($abc_seq_optimize) = ("scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;"); - } - my ($fpga_synthesis_method) = ("if"); - #my ($fpga_synthesis_method) = ("fpga"); - # - my ($dump_verilog) = (""); - if ("on" eq $opt_ptr->{abc_verilog_rewrite}) { - $dump_verilog = "write_verilog $bm.v"; - } - - # - # Create a local copy for the commands - # - my ($ABC_CMD_FH) = (FileHandle->new); - if ($ABC_CMD_FH->open("> $cmd_log")) { - print "INFO: auto generating cmds for ABC ($cmd_log) ...\n"; - } else { - die "ERROR: fail to auto generating cmds for ABC ($cmd_log) ...\n"; - } - # Output the standard format (refer to VTR_flow script) - print $ABC_CMD_FH "read $bm; resyn; resyn2; $fpga_synthesis_method -K $lut_num; $abc_seq_optimize sweep; write_hie $bm $blif_out; $dump_verilog; quit;\n"; - - close($ABC_CMD_FH); - - # Go to ABC directory and run FPGA with commands - print "Entering $abc_dir\n"; - chdir $abc_dir; - - # Run FPGA ABC - system("./$abc_name -F $cmd_log > $log"); - - if (!(-e $blif_out)) { - die "ERROR: Fail ABC_with_bb_support for benchmark $bm.\n"; - } - - if (("on" eq $opt_ptr->{abc_verilog_rewrite})&&(!(-e "$bm.v"))) { - die "ERROR: ABC verilog rewrite failed for benchmark $bm!\n"; - } - - print "Leaving $abc_dir\n"; - chdir $cwd; -} - -# Run ABC Carry-chain premapping by FPGA-oriented synthesis -sub run_abc_mccl_fpgamap($ $ $) -{ - my ($bm,$blif_out,$log) = @_; - # Get ABC path - my ($abc_mccl_dir,$abc_mccl_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_mccl_path}->{val}); - my ($abc_bb_dir,$abc_bb_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_with_bb_support_path}->{val}); - my ($lut_num) = $opt_ptr->{K_val}; - # Before we run this blif, identify it is a combinational or sequential - my ($abc_seq_optimize) = (""); - if (("on" eq $opt_ptr->{abc_scl})&&("seq" eq &check_blif_type($bm))) { - ($abc_seq_optimize) = ("scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;"); - } - my ($fpga_synthesis_method) = ("if"); - #my ($fpga_synthesis_method) = ("fpga"); - - # Name the intermediate file - my ($fadds_blif, $interm_blif) = ($blif_out, $blif_out); - $fadds_blif =~ s/\.blif$/_fadds.blif/; - $interm_blif =~ s/\.blif$/_interm.blif/; - - my ($min_chain_length) = (4); - my ($mccl_opt_A, $mccl_opt_B, $mccl_opt_S) = (3, 3, 2); - - chdir $abc_mccl_dir; - print "INFO: entering abc_mccl directory: $abc_mccl_dir \n"; - - # Run ABC three times: - # 1st time: run abc_with_mccl: read the $bm and do carry-chain detection - system("./$abc_mccl_name -c \"read $bm; strash; &get; &fadds -nv -N $min_chain_length; \&getspec; \&put; wfadds $fadds_blif; quit;\" > $log.ccdetect"); - - # Repeat chdir for multi-thread supporting! - chdir $abc_mccl_dir; - print "INFO: entering abc_mccl directory: $abc_mccl_dir \n"; - - # 2nd time: run abc_with_mccl: read the $fadds_blif and do carry-chain LUT premapping - system("./$abc_mccl_name -c \"read $fadds_blif; resyn; resyn2; mccl -A $mccl_opt_A -B $mccl_opt_B -S $mccl_opt_S -K $lut_num -O 1 -r -o $interm_blif; quit;\" > $log.mccl"); - - chdir $abc_bb_dir; - print "INFO: entering abc_with_bb_support directory: $abc_bb_dir \n"; - # 3rd time: run abc_with_bb_support: read the pre-processed blif and do cleanup and recover - system("./$abc_bb_name -c \"read $interm_blif; $abc_seq_optimize sweep; write_hie $interm_blif $blif_out; quit;\" > $log"); - - if (!(-e $blif_out)) { - die "ERROR: Fail ABC_mccl_FPGA_mapping for benchmark $bm.\n"; - } - - chdir $cwd; -} - -# Run ABC MIG Carry-chain premapping by FPGA-oriented synthesis -sub run_abc_mig_mccl_fpgamap($ $ $) -{ - my ($bm,$blif_out,$log) = @_; - # Get ABC path - my ($abc_mig_mccl_dir,$abc_mig_mccl_name) = &split_prog_path($conf_ptr->{dir_path}->{cirkit_path}->{val}); - my ($abc_mccl_dir,$abc_mccl_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_mccl_path}->{val}); - my ($abc_bb_dir,$abc_bb_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_with_bb_support_path}->{val}); - my ($lut_num) = $opt_ptr->{K_val}; - # Before we run this blif, identify it is a combinational or sequential - my ($abc_seq_optimize) = (""); - if (("on" eq $opt_ptr->{abc_scl})&&("seq" eq &check_blif_type($bm))) { - ($abc_seq_optimize) = ("scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;"); - } - my ($fpga_synthesis_method) = ("if"); - #my ($fpga_synthesis_method) = ("fpga"); - - # Name the intermediate file - my ($fadds_blif, $interm_blif) = ($bm, $bm); - $fadds_blif =~ s/\.blif$/_fadds.blif/; - $interm_blif =~ s/\.blif$/_interm.blif/; - - my ($min_chain_length) = (4); - my ($mccl_opt_A, $mccl_opt_B, $mccl_opt_S) = (3, 3, 2); - - chdir $abc_mccl_dir; - print "INFO: entering abc_mig_mccl directory: $abc_mccl_dir \n"; - - # Run ABC three times: - # 1st time: run abc_with_mig_mccl: read the $bm and do carry-chain detection - # TODO: unfinished!!!! - system("./$abc_mig_mccl_name -c \"readv $bm; chains -C ; quit;\" > $log.ccdetect"); - - # Repeat chdir for multi-thread supporting! - chdir $abc_mccl_dir; - print "INFO: entering abc_mccl directory: $abc_mccl_dir \n"; - - # 2nd time: run abc_with_mccl: read the $fadds_blif and do carry-chain LUT premapping - system("./$abc_mccl_name -c \"read $fadds_blif; resyn; resyn2; mccl -A $mccl_opt_A -B $mccl_opt_B -S $mccl_opt_S -K $lut_num -O 1 -r -o $interm_blif; quit;\" > $log.mccl"); - - chdir $abc_bb_dir; - print "INFO: entering abc_with_bb_support directory: $abc_bb_dir \n"; - # 3rd time: run abc_with_bb_support: read the pre-processed blif and do cleanup and recover - system("./$abc_bb_name -c \"read $interm_blif; $abc_seq_optimize sweep; write_hie $interm_blif $blif_out; quit;\" > $log"); - - if (!(-e $blif_out)) { - die "ERROR: Fail ABC_mccl_FPGA_mapping for benchmark $bm.\n"; - } - - chdir $cwd; -} - -sub run_mpack1p5($ $ $ $ $) -{ - my ($blif_in,$blif_prefix,$matrix_size,$cell_size,$log) = @_; - # Get MPACK path - my ($mpack1_dir,$mpack1_name) = &split_prog_path($conf_ptr->{dir_path}->{mpack1_path}->{val}); - chdir $mpack1_dir; - # Run MPACK - system("./$mpack1_name $blif_in $blif_prefix -matrix_depth $matrix_size -matrix_width $matrix_size -cell_size $cell_size > $log"); - chdir $cwd; - -} - -sub run_mpack2($ $ $ $ $ $ $) -{ - my ($blif_in,$blif_out,$mpack2_arch,$net,$stats,$vpr_arch,$log) = @_; - # Get MPACK path - my ($mpack2_dir,$mpack2_name) = &split_prog_path($conf_ptr->{dir_path}->{mpack2_path}->{val}); - chdir $mpack2_dir; - #my ($ble_arch) = ($conf_ptr->{flow_conf}->{mpack_ble_arch}->{val}); - # Run MPACK - system("./$mpack2_name -blif $blif_in -mpack_blif $blif_out -net $net -ble_arch $mpack2_arch -stats $stats -vpr_arch $vpr_arch > $log"); - chdir $cwd; -} - -# Extract Mpack2 stats -sub extract_mpack2_stats($ $ $) -{ - my ($tag,$bm,$mstats) = @_; - my ($line); - my @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack2_tags}->{val}; - open (MSTATS, "< $mstats") or die "ERROR: Fail to open $mstats!\n"; - while(defined($line = )) { - chomp $line; - $line =~ s/\s//g; - foreach my $tmp(@keywords) { - $tmp =~ s/\s//g; - if ($line =~ m/$tmp\s*([0-9E\-\+.]+)/i) { - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$opt_ptr->{K_val}}->{$tmp} = $1; - } - } - } - close(MSTATS); -} - -# Extract Mpack1 stats -sub extract_mpack1_stats($ $ $) -{ - my ($tag,$bm,$mstats) = @_; - my ($line); - my @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack1_tags}->{val}; - open (MSTATS, "< $mstats") or die "ERROR: Fail to open $mstats!\n"; - while(defined($line = )) { - chomp $line; - $line =~ s/\s//g; - foreach my $tmp(@keywords) { - $tmp =~ s/\s//g; - if ($line =~ m/$tmp\s*([0-9E\-\+.]+)/i) { - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$opt_ptr->{M_val}}->{$tmp} = $1; - } - } - } - close(MSTATS); -} - -# Black Box blif for ACE -sub black_box_blif($ $) -{ - my ($blif_in,$blif_out) = @_; - my ($line); - - open (BF, "< $blif_in") or die "Fail to open $blif_in!\n"; - open (NBF, "> $blif_out") or die "Fail to open $blif_out!\n"; - while(defined($line = )) { - chomp $line; - my @components; - if ($line =~ m/^\.names/) { - @components = split /\s+/,$line; - $line = ".subckt CELL "; - for (my $i=1; $i < ($opt_ptr->{K_val}+1); $i++) { - my $i1 = $i - 1; - if ($i < $#components) { - $line = $line."I[$i1]=$components[$i] "; - } - else { - $line = $line."I[$i1]=unconn "; - } - } - $line = $line."O[0]=$components[$#components] "; - } - print NBF "$line\n"; - } - # definition of Black box - print NBF "\n"; - print NBF ".model CELL\n"; - print NBF ".inputs "; - for (my $i=0; $i < $opt_ptr->{K_val}; $i++) { - print NBF "I[$i] "; - } - print NBF "\n"; - print NBF ".outputs O[0]\n"; - print NBF ".blackbox\n"; - print NBF ".end\n"; - close(BF); - close(NBF); -} - -# Extract VPR Power Esti -sub extract_vpr_power_esti($ $ $ $) -{ - my ($tag,$ace_vpr_blif,$bm,$type) = @_; - my ($line,$tmp,$line_num); - my @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; - my ($vpr_power_stats) = $ace_vpr_blif; - - $line_num = 0; - $vpr_power_stats =~ s/blif$/power/; - open (VSTATS, "< $vpr_power_stats") or die "Fail to open $vpr_power_stats!\n"; - while(defined($line = )) { - chomp $line; - $line_num++; - if ($line =~ m/^Total/i) { - my @power_info = split /\s+/,$line; - if ($#power_info < 3) { - print "Error: (vpr_power_stats:$vpr_power_stats)ilegal definition at LINE[$line_num]!\n"; - die "Format should be [tag] [Power] [Proposition] [Dynamic Proposition] [Method](Optional)\n"; - } - if ($power_info[3] > 1) { - die "Error: (vpr_power_stats:$vpr_power_stats)Dynamic Power Proposition should not be greater than 1 at LINE[$line_num]!\n"; - } - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{total} = $power_info[1]; - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{dynamic} = $power_info[1]*$power_info[3]; - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{leakage} = $power_info[1]*(1-$power_info[3]); - next; - } - $line =~ s/\s//g; - foreach my $tmpkw(@keywords) { - $tmp = $tmpkw; - $tmp =~ s/\s//g; - $tmp =~ s/\(/\\\(/g; - $tmp =~ s/\)/\\\)/g; - #print "$tmp\n"; - if ($line =~ m/$tmp\s*([0-9E\-+.]+)/i) { - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{$tmpkw} = $1; - my @tempdata = split /\./,$rpt_ptr->{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{$tmpkw}; - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{$tmpkw} = join('.',$tempdata[0],$tempdata[1]); - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{power}->{$tmpkw} =~ s/0$//; - } - } - } - close(VSTATS); -} - -# Extract AAPack stats -sub extract_aapack_stats($ $ $ $ $) -{ - my ($tag,$bm,$vstats,$type,$keywords) = @_; - my ($line,$tmp); - open (VSTATS, "< $vstats") or die "Fail to open $vstats!\n"; - while(defined($line = )) { - chomp $line; - #$line =~ s/\s//g; - foreach my $tmpkw(@{$keywords}) { - $tmp = $tmpkw; - $tmp =~ s/\(/\\\(/g; - $tmp =~ s/\)/\\\)/g; - if ($line =~ m/\s*([0-9E\-+.]+)\s+of\s+type\s+$tmpkw/i) { - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{$tmpkw} = $1; - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{$tmpkw} =~ s/\.$//; - } - } - } - close(VSTATS); -} - -# Extract min_channel_width VPR stats -sub extract_min_chan_width_vpr_stats($ $ $ $ $ $) -{ - my ($tag,$bm,$vstats,$type,$min_route_chan_width,$parse_results) = @_; - my ($line,$tmp, $min_chan_width, $chan_width_tag); - my @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - - if ("on" eq $min_route_chan_width) { - $tmp = "Best routing used a channel width factor of"; - $chan_width_tag = "min_route_chan_width"; - } else { - $tmp = "Circuit successfully routed with a channel width factor of"; - $chan_width_tag = "fix_route_chan_width"; - } - $tmp =~ s/\s//g; - - open (VSTATS, "< $vstats") or die "ERROR: Fail to open $vstats!\n"; - while(defined($line = )) { - chomp $line; - if (($line =~ m/\s+([0-9]+)\s+of\s+type\s+names/i) - &&(1 == $parse_results)) { - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{LUTs} = $1; - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{LUTs} =~ s/\.$//; - } - $line =~ s/\s//g; - if ($line =~ m/$tmp\s*([0-9E\-+.]+)/i) { - $min_chan_width = $1; - $min_chan_width =~ s/\.$//; - if (1 == $parse_results) { - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{$chan_width_tag} = $min_chan_width; - } - } - } - close(VSTATS); - return $min_chan_width; -} - - -# Extract VPR stats -sub extract_vpr_stats($ $ $ $) -{ - my ($tag,$bm,$vstats,$type) = @_; - my ($line,$tmp); - my @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - open (VSTATS, "< $vstats") or die "Fail to open $vstats!\n"; - while(defined($line = )) { - chomp $line; - if ($line =~ m/\s+([0-9]+)\s+of\s+type\s+names/i) { - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{LUTs} = $1; - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{LUTs} =~ s/\.$//; - } - $line =~ s/\s//g; - foreach my $tmpkw(@keywords) { - $tmp = $tmpkw; - $tmp =~ s/\s//g; - $tmp =~ s/\(/\\\(/g; - $tmp =~ s/\)/\\\)/g; - #print "$tmp\n"; - if ($line =~ m/$tmp\s*([0-9E\-+.]+)/i) { - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{$tmpkw} = $1; - $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{$tmpkw} =~ s/\.$//; - } - } - } - close(VSTATS); -} - -sub gen_odin2_config_xml($ $ $ $ $ $) { - my ($config_xml, $odin2_verilog, $odin2_blif_out, $vpr_arch, $mem_size, $min_hard_adder_size) = @_; - - # Open a filehandle - my ($XMLFH) = (FileHandle->new); - if ($XMLFH->open("> $config_xml")) { - print "INFO: auto generating configuration XML for ODIN_II($config_xml) ...\n"; - } else { - die "ERROR: fail to auto generate configuration XML for ODIN_II($config_xml) ...\n"; - } - # Output the standard format (refer to VTR_flow script) - print $XMLFH "\n"; - print $XMLFH " \n"; - print $XMLFH " $odin2_verilog\n"; - print $XMLFH " \n"; - print $XMLFH " \n"; - print $XMLFH " blif\n"; - print $XMLFH " $odin2_blif_out\n"; - print $XMLFH " \n"; - print $XMLFH " $vpr_arch\n"; - print $XMLFH " \n"; - print $XMLFH " \n"; - print $XMLFH " \n"; - print $XMLFH " \n"; - print $XMLFH " \n"; - print $XMLFH " \n"; - print $XMLFH " \n"; - print $XMLFH " \n"; - print $XMLFH " .\n"; - print $XMLFH " 1\n"; - print $XMLFH " 1\n"; - print $XMLFH " \n"; - print $XMLFH "\n"; - - close($XMLFH); -} - -sub run_odin2($ $ $) { - my ($config_xml, $carry_chain_support, $log) = @_; - my ($odin2_dir, $odin2_name) = &split_prog_path($conf_ptr->{dir_path}->{odin2_path}->{val}); - my ($options) = (""); - - if ("on" eq $carry_chain_support) { - $options = $options." -Z"; - } - - chdir $odin2_dir; - system("./$odin2_name -c $config_xml $options > $log"); - chdir $cwd; -} - -sub run_pro_blif_3arg($ $ $) { - my ($abc_blif_out_bak, $abc_blif_out, $initial_blif) = @_; - my ($pro_blif_path) = ($conf_ptr->{dir_path}->{script_base}->{val}); - - $pro_blif_path =~ s/\/$//g; - $pro_blif_path = $pro_blif_path . "/pro_blif.pl"; - - `perl $pro_blif_path -i $abc_blif_out_bak -o $abc_blif_out -initial_blif $initial_blif`; - - if (!(-e $abc_blif_out)) { - die "ERROR: Fail pro_blif.pl for benchmark $abc_blif_out.\n"; - } - return; -} - -sub run_pro_blif($ $) { - my ($abc_blif_out_bak, $abc_blif_out) = @_; - my ($pro_blif_path) = ($conf_ptr->{dir_path}->{script_base}->{val}); - - $pro_blif_path =~ s/\/$//g; - $pro_blif_path = $pro_blif_path . "/pro_blif.pl"; - - `perl $pro_blif_path -i $abc_blif_out_bak -o $abc_blif_out -add_default_clk`; - - if (!(-e $abc_blif_out)) { - die "ERROR: Fail pro_blif.pl for benchmark $abc_blif_out.\n"; - } - return; -} - -# Run Acitivity Estimation -sub run_ace($ $ $ $) { - my ($mpack_vpr_blif,$act_file,$ace_new_blif,$log) = @_; - my ($ace_dir,$ace_name) = &split_prog_path($conf_ptr->{dir_path}->{ace_path}->{val}); - my ($ace_customized_opts) = (""); - - if ("on" eq $opt_ptr->{ace_d}) { - $ace_customized_opts .= " -d $opt_ptr->{ace_d_val}"; - } - - if ("on" eq $opt_ptr->{ace_p}) { - $ace_customized_opts .= " -p $opt_ptr->{ace_p_val}"; - } - - print "Entering $ace_dir\n"; - chdir $ace_dir; - system("./$ace_name -b $mpack_vpr_blif -o $act_file -n $ace_new_blif -c clk $ace_customized_opts >> $log"); - - if (!(-e $ace_new_blif)) { - die "ERROR: Fail ACE for benchmark $mpack_vpr_blif.\n"; - } - - print "Leaving $ace_dir\n"; - - chdir $cwd; -} - -# Run Icarus Verilog Simulation -sub run_icarus_verilog($ $ $ $ $) -{ - my ($log_file, $compiled_file, $tb_top, $netlists_path, $include_netlists) = @_; - - # Compile and launch simulation - system("iverilog -o $compiled_file $netlists_path$include_netlists -s $tb_top"); - system("vvp $compiled_file >> $log_file"); # no -j option but could be added to speed-up the process - - # Checking simulation results - open(F, $log_file); - my @lines=; - close F; - my $keyword = "Succeed"; - my $results = grep($keyword, @lines); - if($results >= 1){ - print "\nVerification succeed!\n\n"; - } else { - my $keyword = "Failed"; - my $results = grep($keyword, @lines); - if($results >= 1){ - print "\nVerification failed\n\n"; - } else { - die "\nERROR: Simulation didn't start\n\n"; - } - } - return; -} - -# Run netlists verification using Icarus Simulator -sub run_netlists_verification($) -{ - my ($benchmark) = @_; - my $log_file = "$benchmark"."_sim.log"; - my $compiled_file = "compiled_"."$benchmark"; - my $include_netlists = "$benchmark"."_include_netlists.v"; - my $tb_top_formal = "$benchmark"."_top_formal_verification_random_tb"; - my $tb_top_autochecked = "$benchmark"."_autocheck_top_tb"; - my $netlists_path = "$opt_ptr->{vpr_fpga_verilog_dir_val}"."/SRC/"; - - system("rm -f $log_file"); - system("rm -f $compiled_file"); - - if("on" eq $opt_ptr->{vpr_fpga_verilog_include_icarus_simulator}){ - if("on" eq $opt_ptr->{vpr_fpga_verilog_print_autocheck_top_testbench}){ - if("on" eq $opt_ptr->{vpr_fpga_verilog_formal_verification_top_netlist}){ # Preprogramed FPGA netlist chosen if available to speed-up the process - &run_icarus_verilog($log_file, $compiled_file, $tb_top_formal, $netlists_path, $include_netlists); - } else { - &run_icarus_verilog($log_file, $compiled_file, $tb_top_autochecked, $netlists_path, $include_netlists); - } - } else { - die "ERROR: Cannot run netlist verification without \"-vpr_fpga_verilog_print_autocheck_top_testbench\" token.\n"; - } - } else { - die "ERROR: Cannot run netlist verification without \"-vpr_fpga_verilog_include_icarus_simulator\" token.\n"; - } - return; -} - -sub run_std_vpr($ $ $ $ $ $ $ $ $) -{ - my ($blif,$bm,$arch,$net,$place,$route,$fix_chan_width,$log,$act_file) = @_; - my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); - - my ($power_opts); - if ("on" eq $opt_ptr->{power}) { - $power_opts = "--power --activity_file $act_file --tech_properties $conf_ptr->{flow_conf}->{power_tech_xml}->{val}"; - } else { - $power_opts = ""; - } - my ($packer_opts) = (""); - if ("on" eq $opt_ptr->{vpr_timing_pack_off}) { - $packer_opts = "--timing_driven_clustering off"; - } - - my ($chan_width_opt) = (""); - if (($fix_chan_width > 0)||($fix_chan_width == 0)) { - $chan_width_opt = "--route_chan_width $fix_chan_width"; - } - if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) { - $chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width"; - } - - # FPGA SPICE options - my ($vpr_spice_opts) = (""); - if (("on" eq $opt_ptr->{power})&&("on" eq $opt_ptr->{vpr_fpga_spice})) { - $vpr_spice_opts = "--fpga_spice"; - - if ("on" eq $opt_ptr->{vpr_fpga_x2p_signal_density_weight}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_signal_density_weight $opt_ptr->{vpr_fpga_x2p_signal_density_weight_val}"; - } - if ("on" eq $opt_ptr->{vpr_fpga_x2p_sim_window_size}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_sim_window_size $opt_ptr->{vpr_fpga_x2p_sim_window_size_val}"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_simulator_path}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_simulator_path $opt_ptr->{vpr_fpga_spice_simulator_path_val}"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_print_component_tb}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_lut_testbench"; - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_hardlogic_testbench"; - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_pb_mux_testbench"; - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_cb_mux_testbench"; - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_sb_mux_testbench"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_print_grid_tb}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_grid_testbench"; - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_cb_testbench"; - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_sb_testbench"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_print_top_tb}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_top_testbench"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_leakage_only}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_leakage_only"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_parasitic_net_estimation_off}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_parasitic_net_estimation off"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_testbench_load_extraction_off}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_testbench_load_extraction off"; - } - } - - # FPGA Verilog options - if (("on" eq $opt_ptr->{power})&&("on" eq $opt_ptr->{vpr_fpga_verilog})) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog"; - - if ("on" eq $opt_ptr->{vpr_fpga_verilog_dir}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_dir $opt_ptr->{vpr_fpga_verilog_dir_val}"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_top_tb}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_top_testbench"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_input_blif_tb}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_input_blif_testbench"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_autocheck_top_testbench}) { - if($verilog_benchmark eq undef){ - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_autocheck_top_testbench $conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$bm/$bm.v"; - } else { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_autocheck_top_testbench $verilog_benchmark"; - } - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_include_timing}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_include_timing"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_include_signal_init}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_include_signal_init"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_formal_verification_top_netlist}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_formal_verification_top_netlist"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_modelsim_autodeck}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_modelsim_autodeck $opt_ptr->{vpr_fpga_verilog_print_modelsim_autodeck_val}"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_include_icarus_simulator}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_include_icarus_simulator"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_report_timing_tcl}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_report_timing_tcl"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_report_timing_rpt_path}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_report_timing_rpt_path $opt_ptr->{vpr_fpga_verilog_report_timing_rpt_path_val}"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_sdc_pnr}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_sdc_pnr"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_user_defined_template}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_user_defined_template"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_sdc_analysis}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_sdc_analysis"; - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog_explicit_mapping}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_explicit_mapping"; - } - if ("on" eq $opt_ptr->{vpr_fpga_x2p_compact_routing_hierarchy}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_compact_routing_hierarchy"; - } - } - - # FPGA Bitstream Generator Options - if ("on" eq $opt_ptr->{vpr_fpga_bitstream_generator}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_bitstream_generator"; - } - - if (("on" eq $opt_ptr->{vpr_fpga_x2p_rename_illegal_port}) - || ("on" eq $opt_ptr->{vpr_fpga_spice}) - || ("on" eq $opt_ptr->{vpr_fpga_verilog})) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_rename_illegal_port"; - } - - my ($other_opt) = (""); - if ("on" eq $opt_ptr->{vpr_place_clb_pin_remap}) { - $other_opt = "--place_clb_pin_remap "; - } - if ("on" eq $opt_ptr->{vpr_route_breadthfirst}) { - $other_opt .= "--router_algorithm breadth_first "; - } - if ("on" eq $opt_ptr->{vpr_max_router_iteration}) { - $other_opt .= "--max_router_iterations $opt_ptr->{vpr_max_router_iteration_val} "; - } - - chdir $vpr_dir; - print "Entering $vpr_dir\n"; - - print "./$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $packer_opts $chan_width_opt $vpr_spice_opts $other_opt > $log\n"; - system("./$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $packer_opts $chan_width_opt $vpr_spice_opts $other_opt > $log"); - - #open(F, $log); - #my @lines=; - #close F; - #my @results = grep(" ", @lines); - #if($#results >= 1){ - # foreach my $line (0..$#results){ - # print "$results[$line]\n"; - # } - #} - #if ("on" eq $opt_ptr->{vpr_fpga_verilog_dir}) { - # opendir my($dh), $opt_ptr->{vpr_fpga_verilog_dir_val} or die "\nFolder not created!!\n\n"; - # my @files = readdir $dh; - # closedir $dh; - # foreach my $file (0..$#files){ - # print "$files[$file]\t"; - # } - # print "\n"; - #} - chdir $cwd; -} - -sub run_vpr_route($ $ $ $ $ $ $ $ $) -{ - my ($blif,$bm,$arch,$net,$place,$route,$fix_chan_width,$log,$act_file) = @_; - my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); - - my ($power_opts); - if ("on" eq $opt_ptr->{power}) { - $power_opts = "--power --activity_file $act_file --tech_properties $conf_ptr->{flow_conf}->{power_tech_xml}->{val}"; - } else { - $power_opts = ""; - } - - my ($chan_width_opt) = (""); - if (($fix_chan_width > 0)||($fix_chan_width == 0)) { - $chan_width_opt = "--route_chan_width $fix_chan_width"; - } - if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) { - $chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width"; - } - - my ($vpr_spice_opts) = (""); - if (("on" eq $opt_ptr->{power})&&("on" eq $opt_ptr->{vpr_fpga_spice})) { - $vpr_spice_opts = "--fpga_spice"; - if ("on" eq $opt_ptr->{vpr_fpga_spice_print_cbsbtb}) { - $vpr_spice_opts = $vpr_spice_opts." --print_spice_cb_mux_testbench"; - $vpr_spice_opts = $vpr_spice_opts." --print_spice_sb_mux_testbench"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_print_pbtb}) { - $vpr_spice_opts = $vpr_spice_opts." --print_spice_pb_mux_testbench"; - $vpr_spice_opts = $vpr_spice_opts." --print_spice_lut_testbench"; - $vpr_spice_opts = $vpr_spice_opts." --print_spice_hardlogic_testbench"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_print_gridtb}) { - $vpr_spice_opts = $vpr_spice_opts." --print_spice_grid_testbench"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_print_toptb}) { - $vpr_spice_opts = $vpr_spice_opts." --print_spice_top_testbench"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_leakage_only}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_leakage_only"; - } - if ("on" eq $opt_ptr->{vpr_fpga_spice_parasitic_net_estimation_off}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_parasitic_net_estimation_off"; - } - } - if ("on" eq $opt_ptr->{vpr_fpga_verilog}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog"; - if ("on" eq $opt_ptr->{vpr_fpga_x2p_rename_illegal_port}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_rename_illegal_port"; - } - } - - my ($other_opt) = (""); - if ("on" eq $opt_ptr->{vpr_max_router_iteration}) { - $other_opt .= "--max_router_iterations $opt_ptr->{vpr_max_router_iteration_val} "; - } - if ("on" eq $opt_ptr->{vpr_route_breadthfirst}) { - $other_opt .= "--router_algorithm breadth_first "; - } - - chdir $vpr_dir; - print "Entering $vpr_dir\n"; - - print "./$vpr_name $arch $blif --route --blif_file $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $chan_width_opt $vpr_spice_opts $other_opt > $log\n"; - system("./$vpr_name $arch $blif --route --blif_file $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $chan_width_opt $vpr_spice_opts $other_opt > $log"); - print "\n"; - - chdir $cwd; -} - -sub run_mpack1_vpr($ $ $ $ $ $ $) -{ - my ($blif,$arch,$net,$place,$route,$log,$act_file) = @_; - my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); - my ($power_opts) = (""); - if ("on" eq $opt_ptr->{power}) { - $power_opts = "--power --activity_file $act_file --tech_properties $conf_ptr->{flow_conf}->{power_tech_xml}->{val}"; - } - chdir $vpr_dir; - system("./$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --place --route --full_stats --nodisp $power_opts > $log"); - chdir $cwd; -} - -sub run_mpack2_vpr($ $ $ $ $ $ $) -{ - my ($blif,$arch,$net,$place,$route,$min_chan_width,$log) = @_; - my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); - - my ($power_opts) = (""); - if ("on" eq $opt_ptr->{power}) { - # $power_opts = "--power --activity_file $act_file --tech_properties $conf_ptr->{flow_conf}->{power_tech_xml}->{val}"; - } - my ($chan_width_opt) = (""); - if (($min_chan_width > 0)||($min_chan_width == 0)) { - $min_chan_width = int($min_chan_width*1.2); - if (0 != $min_chan_width%2) { - $min_chan_width += 1; - } - $chan_width_opt = "--route_chan_width $min_chan_width"; - } - - chdir $vpr_dir; - system("./$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --place --route --full_stats --nodisp $power_opts $chan_width_opt > $log"); - chdir $cwd; -} - - -sub run_aapack($ $ $ $) -{ - my ($blif,$arch,$net,$aapack_log) = @_; - my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); - - chdir $vpr_dir; - - system("./$vpr_name $arch $blif --net_file $net --pack --timing_analysis off --nodisp > $aapack_log"); - - chdir $cwd; -} - -sub run_m2net_pack_arch($ $ $ $ $ $) -{ - my ($m2net_conf,$mpack1_rpt,$pack_arch,$N,$I,$m2net_pack_arch_log) = @_; - my ($m2net_dir,$m2net_name) = &split_prog_path($conf_ptr->{dir_path}->{m2net_path}->{val}); - - chdir $m2net_dir; - - system("perl $m2net_name -conf $m2net_conf -mpack1_rpt $mpack1_rpt -mode pack_arch -N $N -I $I -arch_file_pack $pack_arch > $m2net_pack_arch_log"); - - chdir $cwd; -} - -sub run_m2net_m2net($ $ $ $ $) -{ - my ($m2net_conf,$mpack1_rpt,$aapack_net,$vpr_net,$vpr_arch,$N,$I,$m2net_m2net_log) = @_; - my ($m2net_dir,$m2net_name) = &split_prog_path($conf_ptr->{dir_path}->{m2net_path}->{val}); - - chdir $m2net_dir; - - my ($power_opt) = (""); - - if ("on" eq $opt_ptr->{power}) { - $power_opt = "-power"; - } - - system("perl $m2net_name -conf $m2net_conf -mpack1_rpt $mpack1_rpt -mode m2net -N $N -I $I -net_file_in $aapack_net -net_file_out $vpr_net -arch_file_vpr $vpr_arch $power_opt > $m2net_m2net_log"); - - chdir $cwd; -} - -sub run_cirkit_mig_mccl_map($ $ $) { - my ($bm,$blif_out,$log) = @_; - my ($bm_aig, $bm_v) = ($blif_out, $blif_out); - my ($abc_cmd_log, $cirkit_cmd_log) = ($blif_out, $blif_out); - - $bm_aig =~ s/blif$/aig/; - $bm_v =~ s/blif$/v/; - $abc_cmd_log =~ s/\.blif$/_abc.cmd/g; - $cirkit_cmd_log =~ s/\.blif$/_cirkit.cmd/g; - - # Get ABC path - my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_path}->{val}); - - # Get Cirkit path - my ($cirkit_dir,$cirkit_name) = &split_prog_path($conf_ptr->{dir_path}->{cirkit_path}->{val}); - my ($lut_num) = $opt_ptr->{K_val}; - - # Before we run this blif, identify it is a combinational or sequential - my ($abc_seq_optimize) = (""); - if (("on" eq $opt_ptr->{abc_scl})&&("seq" eq &check_blif_type($bm))) { - ($abc_seq_optimize) = ("scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;scleanup;"); - } - my ($fpga_synthesis_method) = ("if"); - #my ($fpga_synthesis_method) = ("fpga"); - - my ($ABC_CMD_FH) = (FileHandle->new); - if ($ABC_CMD_FH->open("> $abc_cmd_log")) { - print "INFO: auto generating cmds for ABC ($abc_cmd_log) ...\n"; - } else { - die "ERROR: fail to auto generating cmds for ABC ($abc_cmd_log) ...\n"; - } - # Output the standard format (refer to VTR_flow script) - print $ABC_CMD_FH "read_blif $bm; strash; write $bm_aig; quit;\n"; - close($ABC_CMD_FH); - - # Run ABC to rewrite blif to AIG in verilog format - chdir $abc_dir; - system("./$abc_name -F $abc_cmd_log > $log"); - if (!(-e $bm_aig)) { - die "ERROR: Fail ABC for benchmark $bm.\n"; - } - - my ($CIRKIT_CMD_FH) = (FileHandle->new); - if ($CIRKIT_CMD_FH->open("> $cirkit_cmd_log")) { - print "INFO: auto generating cmds for Cirkit ($cirkit_cmd_log) ...\n"; - } else { - die "ERROR: fail to auto generating cmds for Cirkit ($cirkit_cmd_log) ...\n"; - } - # Output the standard format (refer to VTR_flow script) - print $CIRKIT_CMD_FH "read_aiger $bm_aig; xmglut -k 4; write_verilog -x $bm_v; read_verilog -x --as_mig $bm_v; fpga --blif_name $blif_out; quit;\n"; - close($CIRKIT_CMD_FH); - - chdir $cirkit_dir; - # Run FPGA ABC - system("./$cirkit_name -f $cirkit_cmd_log >> $log"); - - if (!(-e $blif_out)) { - die "ERROR: Fail Cirkit for benchmark $bm.\n"; - } - - chdir $cwd; -} - -sub init_fpga_spice_task($) { - my ($task_file) = @_; - my ($task_dir_path, $task_filename) = &split_prog_path($task_file); - - &generate_path($task_dir_path); - - # Open the task file handler - my ($TASKFH) = (FileHandle->new); - if ($TASKFH->open("> $task_file")) { - print "Initializing FPGA SPICE task file($task_file)...\n"; - } else { - die "ERROR: fail to create task file ($task_file)!\n"; - } - - print $TASKFH "# FPGA SPICE TASKs to run\n"; - print $TASKFH "# Task line format:\n"; - print $TASKFH "# ,,\n"; - - # Close the file handler - close($TASKFH); -} - -# Print a line into task file which contains task info of FPGA SPICE. -sub output_fpga_spice_task($ $ $ $) { - my ($task_file, $benchmark, $blif_name, $rpt_dir) = @_; - my ($blif_path, $blif_prefix, $spice_dir); - - # Open the task file handler - my ($TASKFH) = (FileHandle->new); - if ($TASKFH->open(">> $task_file")) { - } else { - die "ERROR: fail to generate a line for task($benchmark) in task file ($task_file) ...\n"; - } - - ($blif_path,$blif_prefix) = &split_prog_path($blif_name); - $blif_prefix =~ s/\.blif$//; - $spice_dir = $rpt_dir; - $spice_dir =~ s/\/$//; - $spice_dir = $spice_dir."/spice_netlists/"; - # Output a line - print $TASKFH "# TaskInfo: $benchmark\n"; - print $TASKFH "$benchmark,$blif_prefix,$spice_dir\n"; - - # Close the file handler - close($TASKFH); -} - -sub run_ace_in_flow($ $ $ $ $ $ $) { - my ($prefix, $abc_blif_out, $act_file,$ace_new_blif,$ace_log) = @_; - - if ("on" eq $opt_ptr->{power}) { - if ("on" eq $opt_ptr->{black_box_ace}) { - my ($tmp_blif) = ($prefix."_ace_new.blif"); - &black_box_blif($abc_blif_out,$tmp_blif); - &run_ace($tmp_blif,$act_file,$ace_new_blif ,$ace_log); - } else { - &run_ace($abc_blif_out,$act_file,$ace_new_blif,$ace_log); - } - #&run_pro_blif($ace_new_blif, $abc_blif_out); - } - - if (("on" eq $opt_ptr->{power})&&(!(-e $act_file))) { - die "ERROR: Fail ACE2 for benchmark $act_file.\n"; - } -} - -sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { - my ($tag, $benchmark,$benchmark_file, $abc_blif_out, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results) = @_; - - if ("on" eq $opt_ptr->{min_route_chan_width}) { - &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,-1,$vpr_log.".min_chan_width",$act_file); - # Get the Minimum channel width - my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}, $opt_ptr->{min_route_chan_width}, $parse_results)); - $min_chan_width = int($min_chan_width*$opt_ptr->{min_route_chan_width_val}); - if (0 != $min_chan_width%2) { - $min_chan_width += 1; - } - # Remove previous route results - if (-e $vpr_route) { - system("rm $vpr_route"); - } - # Keep increase min_chan_width until route success - # Extract data from VPR stats - #&run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_log,$act_file); - while (1) { - &run_vpr_route($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_reroute_log,$act_file); - # TODO: Only run the routing stage - if (-e $vpr_route) { - print "INFO: try route_chan_width($min_chan_width) success!\n"; - last; #Jump out - } elsif ($max_route_width_retry < $min_chan_width) { - # I set a threshold of 1000 as it is the limit of VPR - die "ERROR: Route Fail for $abc_blif_out with a min_chan_width of $min_chan_width!\n"; - } else { - print "INFO: try route_chan_width($min_chan_width) failed! Retry with +2...\n"; - $min_chan_width += 2; - } - } - if (1 == $parse_results) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}, "off", $parse_results); - &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); - &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); - } - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); - # Remove previous route results - if (-e $vpr_route) { - system("rm $vpr_route"); - } - # Keep increase min_chan_width until route success - &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log,$act_file); - while (1) { - # TODO: Only run the routing stage - if (-e $vpr_route) { - print "INFO: try route_chan_width($fix_chan_width) success!\n"; - last; #Jump out - } elsif ($max_route_width_retry < $fix_chan_width) { - # I set a threshold of 1000 as it is the limit of VPR - die "ERROR: Route Fail for $abc_blif_out with a min_chan_width of $fix_chan_width!\n"; - } else { - print "INFO: try route_chan_width($fix_chan_width) failed! Retry with +2...\n"; - $fix_chan_width += 2; - &run_vpr_route($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_reroute_log,$act_file); - } - } - # Extract data from VPR stats - if (1 == $parse_results) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "off", $parse_results); - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - if (-e $vpr_reroute_log) { - &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); - } - } - } else { - &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,-1,$vpr_log,$act_file); - if (!(-e $vpr_route)) { - die "ERROR: Route Fail for $abc_blif_out!\n"; - } - # Get the Minimum channel width - my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"on",$parse_results)); - if (1 == $parse_results) { - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - } - } - - # Extract data from VPR Power stats - if (("on" eq $opt_ptr->{power}) - &&(1 == $parse_results)) { - &extract_vpr_power_esti($tag,$abc_blif_out,$benchmark,$opt_ptr->{K_val}); - } - - return; -} - - -sub run_mig_mccl_flow($ $ $ $) { - my ($tag,$benchmark_file,$vpr_arch, $parse_results) = @_; - my ($benchmark, $rpt_dir,$prefix); - my ($cirkit_bm,$cirkit_blif_out,$cirkit_log,$cirkit_blif_out_bak); - - $benchmark = $benchmark_file; - $benchmark =~ s/\.blif$//g; - # Run Standard flow - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - $cirkit_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; - $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; - $cirkit_blif_out = "$prefix"."cirkit.blif"; - $cirkit_blif_out_bak = "$prefix"."cirkit_bak.blif"; - $cirkit_log = "$prefix"."cirkit.log"; - - my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); - - my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - - $vpr_net = "$prefix"."vpr.net"; - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - - &run_cirkit_mig_mccl_map($cirkit_bm,$cirkit_blif_out,$cirkit_log); - if (!(-e $cirkit_blif_out)) { - die "ERROR: Fail Cirkit for benchmark $cirkit_blif_out.\n"; - } - - #`perl pro_blif.pl -i $abc_blif_out_bak -o $abc_blif_out`; - #if (!(-e $abc_blif_out)) { - # die "ERROR: Fail pro_blif.pl for benchmark $abc_blif_out.\n"; - #} - - &run_ace_in_flow($prefix, $cirkit_blif_out, $act_file, $ace_new_blif, $ace_log); - - &run_vpr_in_flow($tag, $benchmark, $benchmark_file, $cirkit_blif_out, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results); - - return; -} - -# Run Yosys-VPR flow -sub run_yosys_vpr_flow($ $ $ $ $) -{ - my ($tag,$benchmark_file,$vpr_arch,$flow_enhance, $parse_results) = @_; - - my ($benchmark, $rpt_dir, $prefix); - my ($yosys_bm,$yosys_blif_out,$yosys_log,$yosys_blif_out_bak); - - my @tokens = split('/', $benchmark_file); - $benchmark = $tokens[0]; - - # Prepare for the output folder - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - - # Adapt paths on architecture file - `perl rewrite_path_in_file.pl -i $vpr_arch`; - - # Run Yosys flow - $yosys_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark_file"; - $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; - $yosys_blif_out = "$prefix"."yosys.blif"; - $yosys_log = "$prefix"."yosys.log"; - - &run_yosys_fpgamap($benchmark, $yosys_bm, $yosys_blif_out, $yosys_log); - - # Files for ace - my ($act_file,$ace_new_blif,$ace_log, $corrected_ace_blif) = ("$rpt_dir/$benchmark".".act","$rpt_dir/$benchmark"."ace.blif","$prefix"."ace.log","$rpt_dir/$benchmark".".blif"); - &run_ace_in_flow($prefix, $yosys_blif_out, $act_file, $ace_new_blif, $ace_log); - - &run_pro_blif_3arg($ace_new_blif, $corrected_ace_blif, $yosys_blif_out); - - # Files for VPR - my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - - $vpr_net = "$prefix"."vpr.net"; - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - -# Need to add a regenation of the verilog from the optimized blif -> write verilog from blif + correct the name of the verilog for the testbench - $verilog_benchmark = &run_rewrite_verilog($corrected_ace_blif, $rpt_dir, $benchmark, $benchmark, $yosys_log); - - &run_vpr_in_flow($tag, $benchmark, $benchmark_file, $corrected_ace_blif, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results); - - if("on" eq $opt_ptr->{end_flow_with_test}) { - &run_netlists_verification($benchmark); - } - - return; -} - -# Parse Yosys-VPR flow -sub parse_yosys_vpr_flow_results($ $ $ $) -{ - my ($tag,$benchmark_file,$vpr_arch,$flow_enhance) = @_; - - my ($benchmark, $rpt_dir, $prefix); - my ($yosys_bm,$yosys_blif_out,$yosys_log,$yosys_blif_out_bak); - - my @tokens = split('/', $benchmark_file); - $benchmark = $tokens[0]; - - # Prepare for the output folder - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - - # Run Yosys flow - $yosys_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark_file"; - $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; - $yosys_blif_out = "$rpt_dir/$benchmark".".blif"; - $yosys_log = "$prefix"."yosys.log"; - - # Files for ace - my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); - - # Files for VPR - my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - - $vpr_net = "$prefix"."vpr.net"; - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - - if ("on" eq $opt_ptr->{min_route_chan_width}) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val},"on",1); - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); - &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); - &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"off",1); - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - if (-e $vpr_reroute_log) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); - &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); - } - } else { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"on",1); - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - } - - # Extract data from VPR Power stats - if ("on" eq $opt_ptr->{power}) { - &extract_vpr_power_esti($tag,$yosys_blif_out,$benchmark,$opt_ptr->{K_val}); - } - - # TODO: HOW TO DEAL WITH SPICE NETLISTS??? - # Output a file contain information of SPICE Netlists - if ("on" eq $opt_ptr->{vpr_fpga_spice}) { - &output_fpga_spice_task("$opt_ptr->{vpr_fpga_spice_val}"."_$tag.txt", $benchmark, $yosys_blif_out, $rpt_dir); - } - - - return; -} - -sub run_vpr_only_flow($ $ $ $ $) -{ - my ($tag,$benchmark_file,$vpr_arch, $parse_results) = @_; - my ($benchmark, $rpt_dir,$prefix); - my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - - $benchmark = $benchmark_file; - $benchmark =~ s/\.blif$//g; - # Run Standard flow - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; - - my ($input_blif) = ("$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"); - my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); - - $vpr_net = "$prefix"."vpr.net"; - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - - &run_ace_in_flow($prefix, $input_blif, $act_file, $ace_new_blif, $ace_log); - - &run_vpr_in_flow($tag, $benchmark, $benchmark_file, $input_blif, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results); - - return; -} - -sub run_standard_flow($ $ $ $ $) -{ - my ($tag,$benchmark_file,$vpr_arch,$flow_enhance, $parse_results) = @_; - my ($benchmark, $rpt_dir,$prefix); - my ($abc_bm,$abc_blif_out,$abc_log,$abc_blif_out_bak); - my ($mpack_blif_out,$mpack_stats,$mpack_log); - my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - - $benchmark = $benchmark_file; - $benchmark =~ s/\.blif$//g; - # Run Standard flow - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; - $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; - $abc_blif_out = "$prefix"."abc.blif"; - $abc_blif_out_bak = "$prefix"."abc_bak.blif"; - $abc_log = "$prefix"."abc.log"; - - - my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); - - $vpr_net = "$prefix"."vpr.net"; - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - - - if ("abc_black_box" eq $flow_enhance) { - my ($pre_abc_blif) = ("$prefix"."pre_abc.blif"); - &run_pro_blif($abc_bm, $pre_abc_blif); - &run_abc_bb_fpgamap($pre_abc_blif,$abc_blif_out_bak,$abc_log); - } elsif ("classic" eq $flow_enhance) { - &run_abc_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); - } - - &run_pro_blif($abc_blif_out_bak, $abc_blif_out); - - &run_ace_in_flow($prefix, $abc_blif_out, $act_file, $ace_new_blif, $ace_log); - - &run_vpr_in_flow($tag, $benchmark, $benchmark_file, $abc_blif_out, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results); - - return; -} - -sub parse_standard_flow_results($ $ $ $) -{ - my ($tag,$benchmark_file,$vpr_arch,$flow_enhance) = @_; - my ($rpt_dir,$prefix); - my ($abc_bm,$abc_blif_out,$abc_log); - my ($mpack_blif_out,$mpack_stats,$mpack_log); - my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - - my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.blif$//g; - # Run Standard flow - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; - $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; - $abc_blif_out = "$prefix"."abc.blif"; - $abc_log = "$prefix"."abc.log"; - - if ("abc_black_box" eq $flow_enhance) { - rename $abc_blif_out,"$abc_blif_out".".bak"; - } elsif ("classic" eq $flow_enhance) { - } - - my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); - - $vpr_net = "$prefix"."vpr.net"; - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - - if ("on" eq $opt_ptr->{min_route_chan_width}) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val},"on",1); - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); - &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); - &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"off",1); - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - if (-e $vpr_reroute_log) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); - &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); - } - } else { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"on",1); - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - } - - # Extract data from VPR Power stats - if ("on" eq $opt_ptr->{power}) { - &extract_vpr_power_esti($tag,$abc_blif_out,$benchmark,$opt_ptr->{K_val}); - } - - # TODO: HOW TO DEAL WITH SPICE NETLISTS??? - # Output a file contain information of SPICE Netlists - if ("on" eq $opt_ptr->{vpr_fpga_spice}) { - &output_fpga_spice_task("$opt_ptr->{vpr_fpga_spice_val}"."_standard.txt", $benchmark, $abc_blif_out, $rpt_dir); - } - - return; -} - -sub run_mpack2_flow($ $ $ $) -{ - my ($tag,$benchmark_file,$mpack2_arch,$parse_results) = @_; - my ($rpt_dir,$prefix); - my ($abc_bm,$abc_blif_out,$abc_log,$abc_blif_out_bak); - my ($mpack2_blif_out,$mpack2_vpr_net,$mpack2_stats,$mpack2_log,$mpack2_vpr_arch); - my ($vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log,$act_file); - - # Check necessary options - if (!($opt_ptr->{N_val})) { - die "ERROR: (mpack2_flow) -N should be specified!\n"; - } - if (!($opt_ptr->{K_val})) { - die "ERROR: (mpack2_flow) -K should be specified!\n"; - } - - my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.blif$//g; - # Run MPACK2-oriented flow - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; - $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; - $abc_blif_out = "$prefix"."abc.blif"; - $abc_blif_out_bak = "$prefix"."abc_bak.blif"; - $abc_log = "$prefix"."abc.log"; - - # RUN ABC - #&run_abc_libmap($abc_bm,"$abc_blif_out\.bak",$abc_log); - &run_abc_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); - - # Pre-process the blif netlist - #`perl convert_blif.pl -i $abc_blif_out\.bak -o $abc_blif_out\.conv`; - `perl pro_blif.pl -i $abc_blif_out_bak -o $abc_blif_out`; - - # RUN MPACK2 - $mpack2_blif_out = "$prefix"."mpack2.blif"; - $mpack2_vpr_net = "$prefix"."mpack2.net"; - $mpack2_stats = "$prefix"."mpack2.stats"; - $mpack2_log = "$prefix"."mpack2.log"; - $mpack2_vpr_arch = "$prefix"."mpack2_vpr_arch.xml"; - &run_mpack2($abc_blif_out,$mpack2_blif_out,$mpack2_arch,$mpack2_vpr_net,$mpack2_stats,$mpack2_vpr_arch,$mpack2_log); - # Extract data from MPACK stats - if (1 == $parse_results) { - &extract_mpack2_stats($tag,$benchmark,$mpack2_stats); - } - - # RUN VPR - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - - if ("on" eq $opt_ptr->{min_route_chan_width}) { - &run_mpack2_vpr($mpack2_blif_out,$mpack2_vpr_arch,$mpack2_vpr_net,$vpr_place,$vpr_route,-1,$vpr_log.".min_chan_width"); - # Get the Minimum channel width - my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}, $opt_ptr->{min_route_chan_width}, $parse_results)); - $min_chan_width = int($min_chan_width*$opt_ptr->{min_route_chan_width_val}); - if (0 != $min_chan_width%2) { - $min_chan_width += 1; - } - - # Remove previous route results - system("rm $vpr_route"); - # Keep increase min_chan_width until route success - # Extract data from VPR stats - while (1) { - &run_vpr_route($mpack2_blif_out,$benchmark,$mpack2_vpr_arch,$mpack2_vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_reroute_log,$act_file); - if (-e $vpr_route) { - print "INFO: try route_chan_width($min_chan_width) Success!\n"; - last; #Jump out - } else { - print "INFO: try route_chan_width($min_chan_width) failed! Retry with +2...\n"; - $min_chan_width += 2; - } - } - # Extract data from VPR stats - if (1 == $parse_results) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}, "off", $parse_results); - &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); - &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); - } - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); - # Remove previous route results - if (-e $vpr_route) { - system("rm $vpr_route"); - } - # Keep increase min_chan_width until route success - # Extract data from VPR stats - &run_mpack2_vpr($mpack2_blif_out,$mpack2_vpr_arch,$mpack2_vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log); - while (1) { - if (-e $vpr_route) { - print "INFO: try route_chan_width($fix_chan_width) success!\n"; - last; #Jump out - } else { - print "INFO: try route_chan_width($fix_chan_width) failed! Retry with +2...\n"; - $fix_chan_width += 2; - &run_vpr_route($mpack2_blif_out,$benchmark,$mpack2_vpr_arch,$mpack2_vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_reroute_log,$act_file); - } - } - if (1 == $parse_results) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "off", $parse_results); - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - if (-e $vpr_reroute_log) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}, "off", $parse_results); - &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); - } - } - } else { - &run_mpack2_vpr($mpack2_blif_out,$mpack2_vpr_arch,$mpack2_vpr_net,$vpr_place,$vpr_route,-1,$vpr_log); - if (!(-e $vpr_route)) { - die "ERROR: Route Fail for $mpack2_blif_out!\n"; - } - my ($min_chan_width) = (&extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, $parse_results)); - # Extract data from VPR stats - if (1 == $parse_results) { - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - } - } - return; -} - -sub parse_mpack2_flow_results($ $ $) -{ - my ($tag,$benchmark_file,$mpack2_arch) = @_; - my ($rpt_dir,$prefix); - my ($abc_bm,$abc_blif_out,$abc_log); - my ($mpack2_blif_out,$mpack2_vpr_net,$mpack2_stats,$mpack2_log,$mpack2_vpr_arch); - my ($vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - - # Check necessary options - if (!($opt_ptr->{N_val})) { - die "ERROR: (mpack2_flow) -N should be specified!\n"; - } - if (!($opt_ptr->{K_val})) { - die "ERROR: (mpack2_flow) -K should be specified!\n"; - } - - my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.blif$//g; - # Run MPACK2-oriented flow - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; - $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; - $abc_blif_out = "$prefix"."abc.blif"; - $abc_log = "$prefix"."abc.log"; - - # Pre-process the blif netlist - - # RUN MPACK2 - $mpack2_blif_out = "$prefix"."mpack2.blif"; - $mpack2_vpr_net = "$prefix"."mpack2.net"; - $mpack2_stats = "$prefix"."mpack2.stats"; - $mpack2_log = "$prefix"."mpack2.log"; - $mpack2_vpr_arch = "$prefix"."mpack2_vpr_arch.xml"; - # Extract data from MPACK stats - &extract_mpack2_stats($tag,$benchmark,$mpack2_stats); - - # RUN VPR - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - - if ("on" eq $opt_ptr->{min_route_chan_width}) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val},"on",1); - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); - &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); - &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - if (-e $vpr_reroute_log) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); - &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); - } else { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"off",1); - } - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - } else { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "on", 1); - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - } - - return; -} - -sub run_mpack1_flow($ $ $) -{ - my ($tag,$benchmark_file, $parse_results) = @_; - my ($rpt_dir,$prefix); - my ($abc_bm,$abc_blif_out,$abc_log); - my ($vpr_net,$vpr_place,$vpr_route,$vpr_log); - my ($I_val,$M_val,$N_val) = ($opt_ptr->{I_val},$opt_ptr->{M_val},$opt_ptr->{N_val}); - my ($m2net_conf) = ($conf_ptr->{flow_conf}->{m2net_conf}->{val}); - my ($cell_size) = (2); - - if ($I_val) { - } else { - $I_val = int($cell_size*$M_val*($N_val+1)/2); - print "INFO: I isn't defined. Auto-sized to 2*M*(N+1)/2 = $I_val\n"; - } - - my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.blif$//g; - # Run MPACK1-oriented flow - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; - $prefix = "$rpt_dir/$benchmark\_"."M$M_val\_"."N$N_val\_"; - $abc_blif_out = "$prefix"."abc.blif"; - $abc_log = "$prefix"."abc.log"; - - &run_abc_libmap($abc_bm,"$abc_blif_out\.bak",$abc_log); - `perl pro_blif.pl -i "$abc_blif_out\.bak" -o $abc_blif_out`; - - my ($mpack1_pack_blif_out) = ("$prefix"."_matrix.blif"); - my ($mpack1_vpr_blif_out) = ("$prefix"."_formatted.blif"); - my ($mpack1_rpt) = ("$prefix"."_mapped.net"); - my ($mpack1_log) = ("$prefix"."mpack1p5.log"); - &run_mpack1p5("$abc_blif_out","$prefix",$M_val,$cell_size,$mpack1_log); - - # Extract data from MPACK stats - if (1 == $parse_results) { - &extract_mpack1_stats($tag,$benchmark,$mpack1_log); - } - - # Generate Architecture XML - my ($aapack_arch) = ("$prefix"."aapack_arch.xml"); - my ($m2net_pack_arch_log) = ("$prefix"."m2net_pack_arch.log"); - &run_m2net_pack_arch($m2net_conf,$mpack1_rpt,$aapack_arch,$N_val,$I_val,$m2net_pack_arch_log); - - # Run AAPACK - my ($aapack_log) = ("$prefix"."aapack.log"); - my ($aapack_net) = ("$prefix"."aapack.net"); - &run_aapack($mpack1_pack_blif_out,$aapack_arch,$aapack_net,$aapack_log); - my @aapack_stats = ("MATRIX"); - if (1 == $parse_results) { - &extract_aapack_stats($tag,$benchmark,$aapack_log,$M_val,\@aapack_stats); - } - - $vpr_net = "$prefix"."mpack.net"; - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - - # Run m2net.pl - my ($vpr_arch) = ("$prefix"."vpr_arch.xml"); - my ($m2net_m2net_log) = ("$prefix"."m2net_m2net.log"); - &run_m2net_m2net($m2net_conf,$mpack1_rpt,$aapack_net,$vpr_net,$vpr_arch,$N_val,$I_val,$m2net_m2net_log); - - my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace_new.blif","$prefix"."ace.log"); - # Turn on Power Estimation and Run ace - if ("on" eq $opt_ptr->{power}) { - &run_ace($mpack1_vpr_blif_out,$act_file,$ace_new_blif,$ace_log); - } - - &run_mpack1_vpr($mpack1_vpr_blif_out,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$vpr_log,$act_file); - if (!(-e $vpr_route)) { - die "ERROR: Route Fail for $mpack1_vpr_blif_out!\n"; - } - - # Extract data from VPR stats - if (1 == $parse_results) { - &extract_vpr_stats($tag,$benchmark,$vpr_log,$M_val); - } - - if (("on" eq $opt_ptr->{power}) - &&(1 == $parse_results)) { - &extract_vpr_power_esti($tag,$mpack1_vpr_blif_out,$benchmark,$M_val); - } -} - -sub parse_mpack1_flow_results($ $) { - my ($tag,$benchmark_file) = @_; - my ($rpt_dir,$prefix); - my ($abc_bm,$abc_blif_out,$abc_log); - my ($vpr_net,$vpr_place,$vpr_route,$vpr_log); - my ($I_val,$M_val,$N_val) = ($opt_ptr->{I_val},$opt_ptr->{M_val},$opt_ptr->{N_val}); - my ($m2net_conf) = ($conf_ptr->{flow_conf}->{m2net_conf}->{val}); - my ($cell_size) = (2); - - if ($I_val) { - } else { - $I_val = int($cell_size*$M_val*($N_val+1)/2); - print "INFO: I isn't defined. Auto-sized to 2*M*(N+1)/2 = $I_val\n"; - } - - my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.blif$//g; - # Run MPACK1-oriented flow - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"; - $prefix = "$rpt_dir/$benchmark\_"."M$M_val\_"."N$N_val\_"; - $abc_blif_out = "$prefix"."abc.blif"; - $abc_log = "$prefix"."abc.log"; - - my ($mpack1_pack_blif_out) = ("$prefix"."_matrix.blif"); - my ($mpack1_vpr_blif_out) = ("$prefix"."_formatted.blif"); - my ($mpack1_rpt) = ("$prefix"."_mapped.net"); - my ($mpack1_log) = ("$prefix"."mpack1p5.log"); - - # Extract data from MPACK stats - &extract_mpack1_stats($tag,$benchmark,$mpack1_log); - - # Generate Architecture XML - my ($aapack_arch) = ("$prefix"."aapack_arch.xml"); - my ($m2net_pack_arch_log) = ("$prefix"."m2net_pack_arch.log"); - - # Run AAPACK - my ($aapack_log) = ("$prefix"."aapack.log"); - my ($aapack_net) = ("$prefix"."aapack.net"); - my @aapack_stats = ("MATRIX"); - &extract_aapack_stats($tag,$benchmark,$aapack_log,$M_val,\@aapack_stats); - - $vpr_net = "$prefix"."mpack.net"; - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - - # Run m2net.pl - my ($vpr_arch) = ("$prefix"."vpr_arch.xml"); - my ($m2net_m2net_log) = ("$prefix"."m2net_m2net.log"); - my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace_new.blif","$prefix"."ace.log"); - - # Extract data from VPR stats - &extract_vpr_stats($tag,$benchmark,$vpr_log,$M_val); - - if ("on" eq $opt_ptr->{power}) { - &extract_vpr_power_esti($tag,$mpack1_vpr_blif_out,$benchmark,$M_val); - } -} - - -sub run_vtr_flow($ $ $ $) { - my ($tag,$benchmark_file,$vpr_arch,$parse_results) = @_; - my ($rpt_dir,$prefix); - my ($min_hard_adder_size, $mem_size, $odin2_verilog, $odin2_config, $odin2_log); - my ($abc_bm,$abc_blif_out,$abc_log,$abc_blif_out_bak); - my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - - # The input of VTR flow is verilog file - my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.v$//g; - # Run Verilog To Routiing flow - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - # ODIN II output blif - $odin2_verilog = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".v"; - $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; - # ODIN II config XML - $odin2_config = "$prefix"."odin2_config.xml"; - $odin2_log = "$prefix"."odin2.log"; - # ODIN II output blif - $abc_bm = "$prefix"."odin2.blif"; - # ABC II output blif - $abc_blif_out = "$prefix"."abc.blif"; - $abc_blif_out_bak = "$prefix"."abc_bak.blif"; - $abc_log = "$prefix"."abc.log"; - - # Initialize min_hard_adder_size - $min_hard_adder_size = 1; # Default value - if ("on" eq $opt_ptr->{min_hard_adder_size}) { - if (1 > $opt_ptr->{min_hard_adder_size_val}) { - die "ERROR: Invalid min_hard_adder_size($opt_ptr->{min_hard_adder_size})!Should be no less than 1!"; - } else { - $min_hard_adder_size = $opt_ptr->{min_hard_adder_size_val}; - } - } - # TODO: Initialize the mem_size by parsing the ARCH XML? - if ("on" eq $opt_ptr->{mem_size}) { - $mem_size = $opt_ptr->{mem_size_val}; - } else { - die "ERROR: -mem_size is mandatory when vtr flow is chosen!\n"; - } - # Auto-generate a configuration XML for ODIN2 - &gen_odin2_config_xml($odin2_config, $odin2_verilog, $abc_bm, $vpr_arch, $mem_size, $min_hard_adder_size); - # RUN ODIN II - &run_odin2($odin2_config, "off", $odin2_log); - - if (!(-e $abc_bm)) { - die "ERROR: Fail ODIN II for benchmark $benchmark.\n"; - } - - # RUN ABC - &run_abc_bb_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); - - &run_pro_blif($abc_blif_out_bak, $abc_blif_out); - - # Run ABC - my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); - &run_ace_in_flow($prefix, $abc_blif_out,$act_file,$ace_new_blif,$ace_log); - - $vpr_net = "$prefix"."vpr.net"; - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - - # Run VPR - &run_vpr_in_flow($tag, $benchmark, $benchmark_file, $abc_blif_out, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results); - - return; -} - -sub parse_vtr_flow_results($ $ $) { - my ($tag,$benchmark,$vpr_arch) = @_; - my ($min_hard_adder_size, $mem_size, $odin2_verilog, $odin2_config, $odin2_log); - my ($rpt_dir,$prefix); - my ($abc_bm,$abc_blif_out,$abc_log); - my ($mpack_blif_out,$mpack_stats,$mpack_log); - my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - - $benchmark =~ s/\.v$//g; - # Run Standard flow - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - # ODIN II output blif - $odin2_verilog = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".v"; - $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; - # ODIN II config XML - $odin2_config = "$prefix"."odin2_config.xml"; - $odin2_log = "$prefix"."odin2.log"; - # ODIN II output blif - $abc_bm = "$prefix"."odin2.blif"; - # ABC output blif - $abc_blif_out = "$prefix"."abc.blif"; - $abc_log = "$prefix"."abc.log"; - - rename $abc_blif_out,"$abc_blif_out".".bak"; - - my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); - - $vpr_net = "$prefix"."vpr.net"; - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - - if ("on" eq $opt_ptr->{min_route_chan_width}) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val},"on",1); - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); - &extract_vpr_stats($tag,$benchmark,$vpr_log.".min_chan_width",$opt_ptr->{K_val}); - &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - if (-e $vpr_reroute_log) { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val},"off",1); - &extract_vpr_stats($tag,$benchmark,$vpr_reroute_log,$opt_ptr->{K_val}); - } else { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"off",1); - } - } else { - &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "on", 1); - &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); - } - - # Extract data from VPR Power stats - if ("on" eq $opt_ptr->{power}) { - &extract_vpr_power_esti($tag,$abc_blif_out,$benchmark,$opt_ptr->{K_val}); - } - - # TODO: HOW TO DEAL WITH SPICE NETLISTS??? - # Output a file contain information of SPICE Netlists - if ("on" eq $opt_ptr->{vpr_fpga_spice}) { - &output_fpga_spice_task("$opt_ptr->{vpr_fpga_spice_val}"."_vtr.txt", $benchmark, $abc_blif_out, $rpt_dir); - } - - return; -} - -# VTR_MCCL_flow: -# Differences from vtr_flow: -# 1. Need to turn off the carry-chain support for ODIN II -# 2. Use Carry-chain detection and Carry-chain LUTs pre-mapping in ABC scripts -sub run_vtr_mccl_flow($ $ $ $) { - my ($tag,$benchmark_file,$vpr_arch,$parse_results) = @_; - my ($rpt_dir,$prefix); - my ($min_hard_adder_size, $mem_size, $odin2_verilog, $odin2_config, $odin2_log); - my ($abc_bm,$abc_blif_out,$abc_log,$abc_blif_out_bak); - my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - my ($odin2_carry_chain_support) = ("on"); - - # The input of VTR flow is verilog file - my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.v$//g; - # Run Verilog To Routiing flow - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - # ODIN II output blif - $odin2_verilog = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".v"; - $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; - # ODIN II config XML - $odin2_config = "$prefix"."odin2_config.xml"; - $odin2_log = "$prefix"."odin2.log"; - # ODIN II output blif - $abc_bm = "$prefix"."odin2.blif"; - # ABC II output blif - $abc_blif_out = "$prefix"."abc.blif"; - $abc_blif_out_bak = "$prefix"."abc_bak.blif"; - $abc_log = "$prefix"."abc.log"; - - # Initialize min_hard_adder_size - $min_hard_adder_size = 1; # Default value - if ("on" eq $opt_ptr->{min_hard_adder_size}) { - if (1 > $opt_ptr->{min_hard_adder_size_val}) { - die "ERROR: Invalid min_hard_adder_size($opt_ptr->{min_hard_adder_size})!Should be no less than 1!"; - } else { - $min_hard_adder_size = $opt_ptr->{min_hard_adder_size_val}; - } - } - # TODO: Initialize the mem_size by parsing the ARCH XML? - if ("on" eq $opt_ptr->{mem_size}) { - $mem_size = $opt_ptr->{mem_size_val}; - } else { - die "ERROR: -mem_size is mandatory when vtr flow is chosen!\n"; - } - # Auto-generate a configuration XML for ODIN2 - &gen_odin2_config_xml($odin2_config, $odin2_verilog, $abc_bm, $vpr_arch, $mem_size, $min_hard_adder_size); - - if ("on" eq $opt_ptr->{odin2_carry_chain_support}) { - $odin2_carry_chain_support = ("on"); - } - # RUN ODIN II - &run_odin2($odin2_config, $odin2_carry_chain_support, $odin2_log); - - if (!(-e $abc_bm)) { - die "ERROR: Fail ODIN II for benchmark $benchmark.\n"; - } - - # RUN ABC - &run_abc_mccl_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); - - &run_pro_blif($abc_blif_out_bak, $abc_blif_out); - - # Run ACE - my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); - &run_ace_in_flow($prefix,i $abc_blif_out,$act_file,$ace_new_blif,$ace_log); - - $vpr_net = "$prefix"."vpr.net"; - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - - # Run VPR - &run_vpr_in_flow($tag, $benchmark, $benchmark_file, $abc_blif_out, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results); - - return; -} - -sub run_mccl_flow($ $ $ $ $) -{ - my ($tag,$benchmark_file,$vpr_arch,$flow_enhance, $parse_results) = @_; - my ($benchmark, $rpt_dir,$prefix); - my ($abc_bm,$abc_blif_out,$abc_log,$abc_blif_out_bak); - my ($mpack_blif_out,$mpack_stats,$mpack_log); - my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - - $benchmark = $benchmark_file; - $benchmark =~ s/\.v$//g; # We use verilog format in mccl - # Run Standard flow - $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; - &generate_path($rpt_dir); - $abc_bm = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".v"; - $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; - $abc_blif_out = "$prefix"."abc.blif"; - $abc_blif_out_bak = "$prefix"."abc_bak.blif"; - $abc_log = "$prefix"."abc.log"; - - # RUN ABC - &run_abc_mccl_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); - - &run_pro_blif($abc_blif_out_bak, $abc_blif_out); - - # Run ACE - my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); - &run_ace_in_flow($prefix,i $abc_blif_out,$act_file,$ace_new_blif,$ace_log); - - $vpr_net = "$prefix"."vpr.net"; - $vpr_place = "$prefix"."vpr.place"; - $vpr_route = "$prefix"."vpr.route"; - $vpr_log = "$prefix"."vpr.log"; - $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - - # Run VPR - &run_vpr_in_flow($tag, $benchmark, $benchmark_file, $abc_blif_out, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results); - - return; -} - -sub run_benchmark_selected_flow($ $ $) -{ - my ($flow_type,$benchmark, $parse_results) = @_; - - if ($flow_type eq "standard") { - &run_standard_flow("standard",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"classic", $parse_results); - } elsif ($flow_type eq "mpack2") { - &run_mpack2_flow("mpack2",$benchmark,$conf_ptr->{flow_conf}->{mpack2_arch}->{val}, $parse_results); - } elsif ($flow_type eq "mpack1") { - &run_mpack1_flow("mpack1",$benchmark, $parse_results); - } elsif ($flow_type eq "vtr_standard") { - &run_standard_flow("vtr_standard",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"abc_black_box", $parse_results); - } elsif ($flow_type eq "vtr") { - &run_vtr_flow("vtr",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results); - } elsif ($flow_type eq "vtr_mccl") { - &run_vtr_mccl_flow("vtr_mccl",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results); - } elsif ($flow_type eq "mccl") { - &run_mccl_flow("mccl",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results); - } elsif ($flow_type eq "mig_mccl") { - &run_mig_mccl_flow("mig_mccl",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results); - } elsif ($flow_type eq "yosys_vpr") { - &run_yosys_vpr_flow("yosys_vpr",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, "classic", $parse_results); - } elsif ($flow_type eq "vpr_only") { - &run_vpr_only_flow("vpr_only",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results); - } else { - die "ERROR: unsupported flow type ($flow_type) is chosen!\n"; - } - - return; -} - -sub parse_benchmark_selected_flow($ $) { - my ($flow_type,$benchmark) = @_; - - if ($flow_type eq "standard") { - &parse_standard_flow_results("standard",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"classic"); - } elsif ($flow_type eq "mpack2") { - &parse_mpack2_flow_results("mpack2",$benchmark,$conf_ptr->{flow_conf}->{mpack2_arch}->{val}); - } elsif ($flow_type eq "mpack1") { - &parse_mpack1_flow_results("mpack1",$benchmark); - } elsif ($flow_type eq "vtr_standard") { - &parse_standard_flow_results("vtr_standard",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"abc_black_box"); - } elsif ($flow_type eq "vtr") { - &parse_vtr_flow_results("vtr", $benchmark, $conf_ptr->{flow_conf}->{vpr_arch}->{val}); - } elsif ($flow_type eq "vtr_mccl") { - &parse_vtr_flow_results("vtr_mccl", $benchmark, $conf_ptr->{flow_conf}->{vpr_arch}->{val}); - } elsif ($flow_type eq "mccl") { - &parse_standard_flow_results("mccl", $benchmark, $conf_ptr->{flow_conf}->{vpr_arch}->{val}, "abc_black_box"); - } elsif ($flow_type eq "mig_mccl") { - &parse_standard_flow_results("mig_mccl", $benchmark, $conf_ptr->{flow_conf}->{vpr_arch}->{val}, "abc_black_box"); - } elsif ($flow_type eq "yosys_vpr") { - &parse_yosys_vpr_flow_results("yosys_vpr",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"abc_black_box"); - } elsif ($flow_type eq "vpr_only") { - &parse_standard_flow_results("vpr_only",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, "classic"); - } else { - die "ERROR: unsupported flow type ($flow_type) is chosen!\n"; - } -} - -# Run EDA flow -sub run_flows() { - my @flows = split('\|',$conf_ptr->{flow_conf}->{flow_type}->{val}); - # Run Benchmark one by one - foreach my $benchmark(@benchmark_names) { - foreach my $flow_to_run(@flows) { - if (("off" eq $selected_flows{$flow_to_run}->{flow_status}) - ||("done" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status})) { - next; - } - print "FLOW TO RUN: $flow_to_run, Benchmark: $benchmark\n"; - &run_benchmark_selected_flow($flow_to_run,$benchmark, 0); - # Mark finished benchmarks - $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "done"; - } - } - &parse_flows_benchmarks_results(); -} - -# Run EDA flow with multi task support -sub multitask_run_flows() { - my @flows = split('\|',$conf_ptr->{flow_conf}->{flow_type}->{val}); - # Run Benchmark one by one - foreach my $benchmark(@benchmark_names) { - foreach my $flow_to_run(@flows) { - if (("off" eq $selected_flows{$flow_to_run}->{flow_status}) - ||("running" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status}) - ||("done" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status})) { - next; - } - print "FLOW TO RUN: $flow_to_run, Benchmark: $benchmark\n"; - # Mutli thread push - if ("on" eq $opt_ptr->{multi_task}) { - my $pid = fork(); - if (defined $pid) { - if ($pid) { - $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "running"; - &run_benchmark_selected_flow($flow_to_run,$benchmark, 1); - # Mark finished benchmarks - $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "done"; - } else { - exit; - } - } else { - print "INFO: fail to create a thread for "; - print "FLOW TO RUN: $flow_to_run, Benchmark: $benchmark\n"; - print "Relauch later...\n"; - } - } else { - &run_benchmark_selected_flow($flow_to_run,$benchmark, 1); - # Mark finished benchmarks - $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "done"; - } - } - } - - return; -} - -# Run EDA flow with multi thread support -sub multithread_run_flows($) { - my ($num_threads) = @_; - my @flows = split('\|',$conf_ptr->{flow_conf}->{flow_type}->{val}); - # Evaluate include threads ok - my ($can_use_threads) = (eval 'use threads; 1'); - if (!($can_use_threads)) { - die "ERROR: cannot use threads package in Perl! Please check the installation of package...\n"; - } - - # Lauch threads up to the limited number of threads number - if ($num_threads < 2) { - $num_threads = 2; - } - my ($num_thread_running) = (0); - - # Iterate until all the tasks has been assigned, finished - while (1 != &check_all_flows_all_benchmarks_done()) { - foreach my $benchmark(@benchmark_names) { - foreach my $flow_to_run(@flows) { - # Bypass unselected flows or finished job - if (("off" eq $selected_flows{$flow_to_run}->{flow_status}) - ||("done" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status})) { - next; - } - # Check if the thread is still not start, running, or finished. - my ($thr_id) = ($selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{thread_id}); - if ($thr_id) { - # Check if there is any error - if ($thr_id->error()) { - die "Thread(ID:$thr_id) exit abnormally!\n"; - } - # We have a thread id, check running or finished - if ($thr_id->is_running()) { - # Update status - $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "running"; - } - if ($thr_id->is_joinable()) { - $num_thread_running--; - $thr_id->join(); # Join the thread results - # Update status - $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "done"; - print "FLOW: $flow_to_run, Benchmark: $benchmark, Finished!\n"; - print "INFO: current running thread number = $num_thread_running.\n"; - &print_jobs_status(); - } - } else { - # Not start a thread for this task, - if (($num_thread_running == $num_threads) - ||($num_thread_running > $num_threads)) { - next; - } - #if there are still threads available, we try to start one - # Mutli thread push - my $thr_new = threads->create(\&run_benchmark_selected_flow,$flow_to_run,$benchmark, 0); - # We have a valid thread... - if ($thr_new) { - print "INFO: a new thread is lauched!\n"; - print "FLOW RUNNING: $flow_to_run, Benchmark: $benchmark\n"; - # Check if it is running... - if ($thr_new->is_running()) { - $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "running"; - $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{thread_id} = $thr_new; - $num_thread_running++; - print "INFO: current running thread number = $num_thread_running.\n"; - &print_jobs_status(); - } - # Check if it is detached... - if ($thr_new->is_joinable()) { - # Mark finished benchmarks - $num_thread_running--; - $thr_new->join(); # Join the thread results - $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "done"; - print "FLOW: $flow_to_run, Benchmark: $benchmark, Finished!\n"; - print "INFO: current running thread number = $num_thread_running.\n"; - &print_jobs_status(); - } - } else { - # Fail to create a new thread, wait... - print "INFO: Fail to alloc a new thread, wait...!"; - } - } - } - } - } - &print_jobs_status(); - - &parse_flows_benchmarks_results(); - - return; -} - -sub parse_flows_benchmarks_results() { - # Parse all the results - foreach my $benchmark(@benchmark_names) { - foreach my $flow_to_run(@supported_flows) { - # Bypass unselected flows or finished job - if (("on" eq $selected_flows{$flow_to_run}->{flow_status}) - &&("done" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status})) { - &parse_benchmark_selected_flow($flow_to_run, $benchmark); - } - } - } - - return; -} - -sub print_jobs_status() { - my ($num_jobs_running, $num_jobs_to_run, $num_jobs_finish, $num_jobs) = (0, 0, 0, 0); - - foreach my $benchmark(@benchmark_names) { - foreach my $flow_to_run(@supported_flows) { - if ("on" eq $selected_flows{$flow_to_run}->{flow_status}) { - # Count the number of jobs - $num_jobs++; - # Count to do jobs - if ("off" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status}) { - $num_jobs_to_run++; - next; - } - # Count running jobs - if ("running" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status}) { - $num_jobs_running++; - next; - } - # Count finished jobs - if ("done" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status}) { - $num_jobs_finish++; - next; - } - } - } - } - if ($num_jobs == ($num_jobs_running + $num_jobs_finish + $num_jobs_to_run)) { - print "Jobs Progress: (Finish rate = ".sprintf("%.2f",100*$num_jobs_finish/$num_jobs) ."%)\n"; - print "Total No. of Jobs: $num_jobs.\n"; - print "No. of Running Jobs: $num_jobs_running.\n"; - print "No. of Finished Jobs: $num_jobs_finish.\n"; - print "No. of To Run Jobs: $num_jobs_to_run.\n"; - } else { - print "Internal problem: num_jobs($num_jobs) != num_jobs_running($num_jobs_running)\n"; - print " +num_jobs_finish($num_jobs_finish)\n"; - die " +num_jobs_to_run($num_jobs_to_run)\n"; - } - return; -} - -sub check_all_flows_all_benchmarks_done() { - my ($all_done) = (1); - foreach my $flow_to_run(@supported_flows) { - if ("off" eq $selected_flows{$flow_to_run}->{flow_status}) { - next; - } - if (1 != &check_flow_all_benchmarks_done($flow_to_run)) { - $all_done = 0; - last; - } - } - return $all_done; -} - -sub check_flow_all_benchmarks_done($) { - my ($flow_name) = @_; - my ($all_done) = (0); - # If this flow has not been chosen, return 0 - if ("off" eq $selected_flows{$flow_name}->{flow_status}) { - return $all_done; - } elsif ("on" eq $selected_flows{$flow_name}->{flow_status}) { - $all_done = 1; - } - # Check if every benchmark has finished in this flow. - foreach my $bm(@benchmark_names) { - if ("done" ne $selected_flows{$flow_name}->{benchmarks}->{$bm}->{status}) { - $all_done = 0; - last; - } - } - - return $all_done; -} - -sub gen_csv_rpt_vtr_flow($ $) -{ - my ($tag,$CSVFH) = @_; - my ($tmp,$ikw,$tmpkw); - my @keywords; - my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); - - # adapt to matlab format if the option is enabled - if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name - print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented - print $CSVFH "%"; - } - - # Print out Standard Stats First - print $CSVFH "$tag"; - print $CSVFH ",LUTs"; - if ("on" eq $opt_ptr->{min_route_chan_width}) { - print $CSVFH ",min_route_chan_width"; - print $CSVFH ",fix_route_chan_width"; - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - print $CSVFH ",fix_route_chan_width"; - } else { - print $CSVFH ",min_route_chan_width"; - } - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - #foreach $tmpkw(@keywords) { - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - print $CSVFH ",$keywords[$ikw]"; - } - if ("on" eq $opt_ptr->{power}) { - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; - #foreach $tmpkw(@keywords) { - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - print $CSVFH ",$keywords[$ikw]"; - } - print $CSVFH ",Total Power,Total Dynamic Power,Total Leakage Power"; - } - print $CSVFH "\n"; - # Check log/stats one by one - foreach $tmp(@benchmark_names) { - $tmp =~ s/\.v$//g; - print $CSVFH "$tmp"; - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; - if ("on" eq $opt_ptr->{min_route_chan_width}) { - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; - } else { - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; - } - #foreach $tmpkw(@keywords) { - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; - } - if ("on" eq $opt_ptr->{power}) { - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{$keywords[$ikw]}"; - } - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{total}"; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{dynamic}"; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{leakage}"; - } - # For matlab script, we end with a semicolumn to be compatiable to matlab - if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH ";\n"; - } else { - print $CSVFH "\n"; - } - } - - # For matlab script, we end with ]; - if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH "];\n"; - } -} - -sub gen_csv_rpt_yosys_vpr_flow($ $) -{ - my ($tag,$CSVFH) = @_; - my ($tmp,$ikw,$tmpkw); - my @keywords; - my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); - - # adapt to matlab format if the option is enabled - if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name - print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented - print $CSVFH "%"; - } - - # Print out Standard Stats First - print $CSVFH "$tag"; - print $CSVFH ",LUTs"; - if ("on" eq $opt_ptr->{min_route_chan_width}) { - print $CSVFH ",min_route_chan_width"; - print $CSVFH ",fix_route_chan_width"; - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - print $CSVFH ",fix_route_chan_width"; - } else { - print $CSVFH ",min_route_chan_width"; - } - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - #foreach $tmpkw(@keywords) { - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - print $CSVFH ",$keywords[$ikw]"; - } - if ("on" eq $opt_ptr->{power}) { - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; - #foreach $tmpkw(@keywords) { - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - print $CSVFH ",$keywords[$ikw]"; - } - print $CSVFH ",Total Power,Total Dynamic Power,Total Leakage Power"; - } - print $CSVFH "\n"; - # Check log/stats one by one - foreach $tmp(@benchmark_names) { - my @tokens = split('/', $tmp); - $tmp = $tokens[0]; - - # For matlab script, we use {} for string - if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH "{'$tmp'}"; - } else { - print $CSVFH "$tmp"; - } - - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; - if ("on" eq $opt_ptr->{min_route_chan_width}) { - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; - } else { - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; - } - #foreach $tmpkw(@keywords) { - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; - } - if ("on" eq $opt_ptr->{power}) { - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{$keywords[$ikw]}"; - } - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{total}"; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{dynamic}"; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{leakage}"; - } - # For matlab script, we end with a semicolumn to be compatiable to matlab - if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH ";\n"; - } else { - print $CSVFH "\n"; - } - } - - # For matlab script, we end with ]; - if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH "];\n"; - } -} - -sub gen_csv_rpt_standard_flow($ $) -{ - my ($tag,$CSVFH) = @_; - my ($tmp,$ikw,$tmpkw); - my @keywords; - my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); - - # adapt to matlab format if the option is enabled - if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name - print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented - print $CSVFH "%"; - } - - # Print out Standard Stats First - print $CSVFH "$tag"; - print $CSVFH ",LUTs"; - if ("on" eq $opt_ptr->{min_route_chan_width}) { - print $CSVFH ",min_route_chan_width"; - print $CSVFH ",fix_route_chan_width"; - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - print $CSVFH ",fix_route_chan_width"; - } else { - print $CSVFH ",min_route_chan_width"; - } - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - #foreach $tmpkw(@keywords) { - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - print $CSVFH ",$keywords[$ikw]"; - } - if ("on" eq $opt_ptr->{power}) { - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; - #foreach $tmpkw(@keywords) { - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - print $CSVFH ",$keywords[$ikw]"; - } - print $CSVFH ",Total Power,Total Dynamic Power,Total Leakage Power"; - } - print $CSVFH "\n"; - # Check log/stats one by one - foreach $tmp(@benchmark_names) { - $tmp =~ s/\.blif$//g; - - if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH "{'$tmp'}"; - } else { - print $CSVFH "$tmp"; - } - - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; - if ("on" eq $opt_ptr->{min_route_chan_width}) { - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; - } else { - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; - } - #foreach $tmpkw(@keywords) { - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; - } - if ("on" eq $opt_ptr->{power}) { - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{$keywords[$ikw]}"; - } - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{total}"; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{dynamic}"; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{leakage}"; - } - - # For matlab script, we end with a semicolumn to be compatiable to matlab - if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH ";\n"; - } else { - print $CSVFH "\n"; - } - } - - # For matlab script, we end with ]; - if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH "];\n"; - } -} - -sub gen_csv_rpt_mpack2_flow($ $) -{ - my ($tag,$CSVFH) = @_; - my ($tmp,$ikw,$tmpkw); - my @keywords; - my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); - - # adapt to matlab format if the option is enabled - if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name - print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented - print $CSVFH "%"; - } - - # Print out Mpack stats Second - print $CSVFH "$tag"; - if ("on" eq $opt_ptr->{min_route_chan_width}) { - print $CSVFH ",min_route_chan_width"; - print $CSVFH ",fix_route_chan_width"; - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - print $CSVFH ",fix_route_chan_width"; - } else { - print $CSVFH ",min_route_chan_width"; - } - - @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack2_tags}->{val}; - #foreach $tmpkw(@keywords) { - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - print $CSVFH ",$keywords[$ikw]"; - } - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - #foreach $tmpkw(@keywords) { - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - print $CSVFH ",$keywords[$ikw]"; - } - if ("on" eq $opt_ptr->{power}) { - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; - #foreach $tmpkw(@keywords) { - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - print $CSVFH ",$keywords[$ikw]"; - } - print $CSVFH ",Total Power,Total Dynamic Power,Total Leakage Power"; - } - print $CSVFH "\n"; - # Check log/stats one by one - foreach $tmp(@benchmark_names) { - $tmp =~ s/\.blif$//g; - print $CSVFH "$tmp"; - if ("on" eq $opt_ptr->{min_route_chan_width}) { - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; - } elsif ("on" eq $opt_ptr->{fix_route_chan_width}) { - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; - } else { - print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; - } - #foreach $tmpkw(@keywords) { - @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack2_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; - } - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; - } - if ("on" eq $opt_ptr->{power}) { - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{$keywords[$ikw]}"; - } - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{total}"; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{dynamic}"; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{leakage}"; - } - # For matlab script, we end with a semicolumn to be compatiable to matlab - if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH ";\n"; - } else { - print $CSVFH "\n"; - } - } - - # For matlab script, we end with ]; - if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH "];\n"; - } -} - -sub gen_csv_rpt_mpack1_flow($ $) -{ - my ($tag,$CSVFH) = @_; - my ($tmp,$ikw,$tmpkw); - my @keywords; - my ($N_val,$M_val) = ($opt_ptr->{N_val},$opt_ptr->{M_val}); - - # adapt to matlab format if the option is enabled - if ("on" eq $opt_ptr->{matlab_rpt}) { - # Print the data name - print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; - # We will set the stats line to be commented - print $CSVFH "%"; - } - - # Print out Mpack stats Second - print $CSVFH "$tag"; - print $CSVFH ",MATRIX"; - @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - print $CSVFH ",$keywords[$ikw]"; - } - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - #foreach $tmpkw(@keywords) { - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - print $CSVFH ",$keywords[$ikw]"; - } - # Print Power Tags - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; - #foreach $tmpkw(@keywords) { - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - print $CSVFH ",$keywords[$ikw]"; - } - print $CSVFH ",Total Power,Total Dynamic Power, Total Leakage Power"; - print $CSVFH "\n"; - # Check log/stats one by one - foreach $tmp(@benchmark_names) { - $tmp =~ s/\.blif$//g; - print $CSVFH "$tmp"; - #foreach $tmpkw(@keywords) { - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{MATRIX}"; - @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{$keywords[$ikw]}"; - } - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{$keywords[$ikw]}"; - } - # Print Power Results - @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; - for($ikw=0; $ikw < ($#keywords+1); $ikw++) { - $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{$keywords[$ikw]}"; - } - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{total}"; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{dynamic}"; - print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{leakage}"; - # For matlab script, we end with a semicolumn to be compatiable to matlab - if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH ";\n"; - } else { - print $CSVFH "\n"; - } - } - - # For matlab script, we end with ]; - if ("on" eq $opt_ptr->{matlab_rpt}) { - print $CSVFH "];\n"; - } -} - -sub init_selected_flows() { - # For each flow type, mark the status to off - foreach my $flow_type(@supported_flows) { - $selected_flows{$flow_type}->{flow_status} = "off"; - # For each benchmark, init the status to "off" - foreach my $benchmark(@benchmark_names) { - $selected_flows{$flow_type}->{benchmarks}->{$benchmark}->{status} = "off"; - $selected_flows{$flow_type}->{benchmarks}->{$benchmark}->{thread_id} = undef; - } - } -} - -sub mark_selected_flows() -{ - # Mark what flows are selected - my @flows = split('\|',$conf_ptr->{flow_conf}->{flow_type}->{val}); - foreach my $flow_type(@flows) { - if (exists $selected_flows{$flow_type}->{flow_status}) { - $selected_flows{$flow_type}->{flow_status} = "on"; - print "INFO: FLOW TYPE: $flow_type is turned $selected_flows{$flow_type}->{flow_status}\n"; - # Initial FPGA SPICE TASK FILE - if ("on" eq $opt_ptr->{vpr_fpga_spice}) { - &init_fpga_spice_task($opt_ptr->{vpr_fpga_spice_val}."_$flow_type.txt"); - } - } else { - die "ERROR: flow_type: $flow_type is not supported!\n"; - } - } -} - -sub mark_flows_benchmarks() { - foreach my $flow_type(@supported_flows) { - if ("on" eq $selected_flows{$flow_type}->{flow_status}) { - # For each benchmark, init the status to "off" - foreach my $benchmark(@benchmark_names) { - $selected_flows{$flow_type}->{benchmarks}->{$benchmark}->{status} = "done"; - } - } - } -} - -sub gen_csv_rpt($) -{ - my ($csv_file) = @_; - - my ($csv_dir_path, $csv_filename) = &split_prog_path($csv_file); - &generate_path($csv_dir_path); - - # Open a filehandle - my ($CSVFH) = (FileHandle->new); - if ($CSVFH->open("> $csv_file")) { - print "INFO: writing CSV report ($csv_file) ...\n"; - } else { - die "ERROR: fail to create CSV report ($csv_file) ...\n"; - } - - foreach my $flow_type(@supported_flows) { - if ($selected_flows{$flow_type}->{flow_status} eq "on") { - # Print the report only all the benchmarks in this flow finished - if ($flow_type eq "standard") { - if (1 == &check_flow_all_benchmarks_done("standard")) { - print "INFO: writing standard flow results ...\n"; - &gen_csv_rpt_standard_flow("standard",$CSVFH); - } - } elsif ($flow_type eq "mpack2") { - if (1 == &check_flow_all_benchmarks_done("mpack2")) { - print "INFO: writing mpack2 flow results ...\n"; - &gen_csv_rpt_mpack2_flow("mpack2",$CSVFH); - } - } elsif ($flow_type eq "mpack1") { - if (1 == &check_flow_all_benchmarks_done("mpack1")) { - print "INFO: writing mpack1 flow results ...\n"; - &gen_csv_rpt_mpack1_flow("mpack1",$CSVFH); - } - } elsif ($flow_type eq "vtr_standard") { - if (1 == &check_flow_all_benchmarks_done("vtr")) { - print "INFO: writing vtr flow results ...\n"; - &gen_csv_rpt_standard_flow("vtr_standard",$CSVFH); - } - } elsif ($flow_type eq "vtr") { - if (1 == &check_flow_all_benchmarks_done("vtr")) { - print "INFO: writing vtr flow results ...\n"; - &gen_csv_rpt_vtr_flow("vtr",$CSVFH); - } - } elsif ($flow_type eq "vtr_mccl") { - if (1 == &check_flow_all_benchmarks_done("vtr_mccl")) { - print "INFO: writing vtr_mccl flow results ...\n"; - &gen_csv_rpt_standard_flow("vtr_mccl",$CSVFH); - } - } elsif ($flow_type eq "mccl") { - if (1 == &check_flow_all_benchmarks_done("mccl")) { - print "INFO: writing mccl flow results ...\n"; - &gen_csv_rpt_standard_flow("mccl",$CSVFH); - } - } elsif ($flow_type eq "mig_mccl") { - if (1 == &check_flow_all_benchmarks_done("mig_mccl")) { - print "INFO: writing mig_mccl flow results ...\n"; - &gen_csv_rpt_standard_flow("mig_mccl",$CSVFH); - } - } elsif ($flow_type eq "yosys_vpr") { - if (1 == &check_flow_all_benchmarks_done("yosys_vpr")) { - print "INFO: writing yosys_vpr flow results ...\n"; - &gen_csv_rpt_yosys_vpr_flow("yosys_vpr",$CSVFH); - } - } elsif ($flow_type eq "vpr_only") { - if (1 == &check_flow_all_benchmarks_done("vpr_only")) { - print "INFO: writing vpr_only flow results ...\n"; - &gen_csv_rpt_standard_flow("vpr_only",$CSVFH); - } - } else { - die "ERROR: flow_type: $flow_type is not supported!\n"; - } - } - } - - close($CSVFH); -} - -sub remove_designs() -{ - if ("on" eq $opt_ptr->{remove_designs}) { - system("rm -rf $conf_ptr->{dir_path}->{rpt_dir}->{val}"); - } -} - -sub plan_run_flows() { - - if ("on" eq $opt_ptr->{multi_task}) { - &multitask_run_flows(); - } elsif (("on" eq $opt_ptr->{multi_thread}) - &&($opt_ptr->{multi_thread_val} > 1) - &&(0 < $#benchmark_names)) { - &multithread_run_flows($opt_ptr->{multi_thread_val}); - } else { - if ("on" eq $opt_ptr->{multi_thread}) { - print "INFO: multi_thread is selected but only 1 processor can be used or 1 benchmark to run...\n"; - print "INFO: switch to single thread mode.\n"; - } - &run_flows(); - } -} - -# Main Program -sub main() -{ - &opts_read(); - &read_conf(); - &read_benchmarks(); - &init_selected_flows(); - &mark_selected_flows(); - &check_opts(); - if ("on" eq $opt_ptr->{parse_results_only}) { - &mark_flows_benchmarks(); - &parse_flows_benchmarks_results(); - } else { - &remove_designs(); - &plan_run_flows(); - } - &gen_csv_rpt($opt_ptr->{rpt_val}); -} - -&main(); -exit(0); diff --git a/fpga_flow/scripts/generate_config.pl b/fpga_flow/scripts/generate_config.pl deleted file mode 100644 index df939f716..000000000 --- a/fpga_flow/scripts/generate_config.pl +++ /dev/null @@ -1,250 +0,0 @@ -#!usr/bin/perl -w -use strict; -#use Shell; -#Use the time -use Time::gmtime; - -#Get Date -my $mydate = gmctime(); - -use File::Path; -use Cwd; -use FileHandle; - -# Global Variants -# input Option Hash -my %opt_h; -my $opt_ptr = \%opt_h; - -my $CONF_HANDLE; -my ($SCRIPTS_PATH, $CONFIG_FILEPATH, $FPGA_FLOW_PATH); - -# !!! this script is called in the parent folder: fpga_flow. If you use the script in the scripts folder it is not going to work! !!! -$FPGA_FLOW_PATH = getcwd(); -$SCRIPTS_PATH = "${FPGA_FLOW_PATH}/scripts"; -$CONFIG_FILEPATH = "${FPGA_FLOW_PATH}/configs/fpga_spice/k6_N10_sram_tsmc40nm_TT.conf"; - -sub spot_option($ $) { - my ($start,$target) = @_; - my ($arg_no,$flag) = (-1,"unfound"); - for (my $iarg = $start; $iarg < $#ARGV+1; $iarg++) { - if ($ARGV[$iarg] eq $target) { - if ("found" eq $flag) { - print "Error: Repeated Arguments!(IndexA: $arg_no,IndexB: $iarg)\n"; - &print_usage(); - } else { - $flag = "found"; - $arg_no = $iarg; - } - } - } - # return the arg_no if target is found - # or return -1 when target is missing - return $arg_no; -} - -# Specify in the input list, -# 1. Option Name -# 2. Whether Option with value. if yes, choose "on" -# 3. Whether Option is mandatory. If yes, choose "on" -sub read_opt_into_hash($ $ $) { - my ($opt_name,$opt_with_val,$mandatory) = @_; - # Check the -$opt_name - my ($opt_fact) = ("-".$opt_name); - my ($cur_arg) = (0); - my ($argfd) = (&spot_option($cur_arg,"$opt_fact")); - if ($opt_with_val eq "on") { - if (-1 != $argfd) { - if ($ARGV[$argfd+1] =~ m/^-/) { - print "The next argument cannot start with '-'!\n"; - print "it implies an option!\n"; - } else { - $opt_ptr->{"$opt_name\_val"} = $ARGV[$argfd+1]; - $opt_ptr->{"$opt_name"} = "on"; - } - } else { - $opt_ptr->{"$opt_name"} = "off"; - if ($mandatory eq "on") { - print "Mandatory option: $opt_fact is missing!\n"; - &print_usage(); - } - } - } else { - if (-1 != $argfd) { - $opt_ptr->{"$opt_name"} = "on"; - } - else { - $opt_ptr->{"$opt_name"} = "off"; - if ($mandatory eq "on") { - print "Mandatory option: $opt_fact is missing!\n"; - &print_usage(); - } - } - } - return 1; -} - -# Read options -sub opts_read() { - # if no arguments detected, print the usage. - if (-1 == $#ARGV) { - print "Error : No input arguments!\n"; - print "Help desk:\n"; - &print_usage(); - exit(1); - } - # Read in the options - my ($cur_arg,$arg_found); - $cur_arg = 0; - print "Analyzing your options...\n"; - # Read the options with internal options - my $argfd; - # Check help fist - $argfd = &spot_option($cur_arg,"-help"); - if (-1 != $argfd) { - print "Help desk:\n"; - &print_usage(); - } - # Then Check the debug with highest priority - $argfd = &spot_option($cur_arg,"-debug"); - if (-1 != $argfd) { - $opt_ptr->{"debug"} = "on"; - } - else { - $opt_ptr->{"debug"} = "off"; - } - # Check mandatory options - # Check the -conf - # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" - &read_opt_into_hash("output_conf","on","on"); - &read_opt_into_hash("arch","on","on"); - &read_opt_into_hash("benchmark_path","on","on"); - &read_opt_into_hash("flow_type","on","on"); - &read_opt_into_hash("power_property_xml","on","on"); - - &print_opts(); - - return 1; -} - -# List the options -sub print_opts() { - print "List your options\n"; - - while(my ($key,$value) = each(%opt_h)) { - print "$key : $value\n"; - } - - return 1; -} - -sub print_usage() { - print "generate configuration file for FPGA flow.\n"; - print "Usage: perl generate_config.pl \n"; - print " Mandatory options:\n"; - print " -output_conf : specify the path of configuration file to be outputted\n"; - print " -arch : specify the architecture file\n"; - print " -benchmark_path : specify the path of benchmark files\n"; - print " -flow_type : specify the type of FPGA flow to run\n"; - print " -power_property_xml : specify the XML file containing power property of FPGA architectures\n"; - return 1; -} - -# Create paths if it does not exist. -sub generate_path($) { - my ($mypath) = @_; - if (!(-e "$mypath")) { - mkpath "$mypath"; - print "Path($mypath) does not exist...Create it.\n"; - } - return 1; -} - -# Opens the file in order to write into it -sub open_file($) { - my ($mypath) = @_; - open ($CONF_HANDLE, "> $mypath") or die "Can't open $mypath: $!"; - return 1; -} - -# Generates the content of the configuration file -sub generate_file($) -{ - my ($my_path) = @_; - - print $CONF_HANDLE "# Standard Configuration Example\n"; - print $CONF_HANDLE "[dir_path]\n"; - print $CONF_HANDLE "script_base = $FPGA_FLOW_PATH/scripts/\n"; - print $CONF_HANDLE "benchmark_dir = $opt_ptr->{benchmark_path_val}\n"; - print $CONF_HANDLE "yosys_path = ${FPGA_FLOW_PATH}/../yosys/yosys\n"; - print $CONF_HANDLE "odin2_path = ${FPGA_FLOW_PATH}/not_used_atm/odin2.exe\n"; - print $CONF_HANDLE "cirkit_path = ${FPGA_FLOW_PATH}/not_used_atm/cirkit\n"; - print $CONF_HANDLE "abc_path = ${FPGA_FLOW_PATH}/../yosys/yosys-abc\n"; - print $CONF_HANDLE "abc_mccl_path = ${FPGA_FLOW_PATH}/../abc_with_bb_support/abc\n"; - print $CONF_HANDLE "abc_with_bb_support_path = ${FPGA_FLOW_PATH}/../abc_with_bb_support/abc\n"; - print $CONF_HANDLE "mpack1_path = ${FPGA_FLOW_PATH}/not_used_atm/mpack1\n"; - print $CONF_HANDLE "m2net_path = ${FPGA_FLOW_PATH}/not_used_atm/m2net\n"; - print $CONF_HANDLE "mpack2_path = ${FPGA_FLOW_PATH}/not_used_atm/mpack2\n"; - print $CONF_HANDLE "vpr_path = ${FPGA_FLOW_PATH}/../vpr7_x2p/vpr/vpr\n"; - print $CONF_HANDLE "rpt_dir = ${FPGA_FLOW_PATH}/results\n"; - print $CONF_HANDLE "ace_path = ${FPGA_FLOW_PATH}/../ace2/ace\n"; - print $CONF_HANDLE "\n"; - print $CONF_HANDLE "[flow_conf]\n"; - print $CONF_HANDLE "flow_type = $opt_ptr->{flow_type_val} #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr\n"; - print $CONF_HANDLE "vpr_arch = $opt_ptr->{arch_val} # Use relative path under VPR folder is OK\n"; - print $CONF_HANDLE "mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK\n"; - print $CONF_HANDLE "m2net_conf = ${FPGA_FLOW_PATH}/m2net_conf/m2x2_SiNWFET.conf\n"; - print $CONF_HANDLE "mpack2_arch = K6_pattern7_I24.arch\n"; - print $CONF_HANDLE "power_tech_xml = $opt_ptr->{power_property_xml_val} # Use relative path under VPR folder is OK\n"; - print $CONF_HANDLE "\n"; - print $CONF_HANDLE "[csv_tags]\n"; - print $CONF_HANDLE "mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:\n"; - print $CONF_HANDLE "mpack2_tags = BLE Number:|BLE Fill Rate: \n"; - print $CONF_HANDLE "vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:\n"; - print $CONF_HANDLE "vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff\n"; - return 1; -} - -# Closes the file after being used -sub close_file($) { - close ($CONF_HANDLE) || warn "close failed: $!"; - return 1; -} - -# Input program path is like "~/program_dir/program_name" -# We split it from the scalar -sub split_prog_path($) { - my ($prog_path) = @_; - my @path_elements = split /\//,$prog_path; - my ($prog_dir,$prog_name); - - $prog_name = $path_elements[$#path_elements]; - $prog_dir = $prog_path; - $prog_dir =~ s/$prog_name$//g; - - return ($prog_dir,$prog_name); -} - - -# Main routine -sub main() { - &opts_read(); - - $CONFIG_FILEPATH = $opt_ptr->{output_conf_val}; - - my ($CONFIG_DIR_PATH, $CONFIG_FILENAME) = &split_prog_path($CONFIG_FILEPATH); - - &generate_path($CONFIG_DIR_PATH); - &open_file($CONFIG_FILEPATH); - &generate_file($CONFIG_FILEPATH); - &close_file($CONFIG_FILEPATH); - - print "Configuration file $CONFIG_FILEPATH generated!\n"; - - return 1; -} - -&main(); -exit(0); - - diff --git a/fpga_flow/scripts/m2net.pl b/fpga_flow/scripts/m2net.pl deleted file mode 100755 index 469e78ffc..000000000 --- a/fpga_flow/scripts/m2net.pl +++ /dev/null @@ -1,1354 +0,0 @@ -#!usr/bin/perl -w -# Perl Script to convert MPACK1 netlist for VPR and generate architecture file -# use the strict mode -use strict; -# Use the Shell enviornment -#use Shell; -# Use the time -use Time::gmtime; -# Use switch module -use Switch; -use File::Path; -use Cwd; - -# Date -my $mydate = gmctime(); -# Current Path -my $cwd = getcwd(); - -# Global Variants -# input Option Hash -my %opt_h; -my $opt_ptr = \%opt_h; -# configurate file hash -my %conf_h; -my $conf_ptr = \%conf_h; -# reports has -my %rpt_h; -my $rpt_ptr = \%rpt_h; - -# Matrix informations -my %mclusters; -my ($mclusters_ptr) = (\%mclusters); - -# Configuration file keywords list -# Category for conf file. -# main category : 1st class -my @mctgy; -# sub category : 2nd class -my @sctgy; -# Initialize these categories -@mctgy = ("arch_model", - "arch_device", - "arch_complexblocks", - ); -# refer to the keywords of arch_model -@{$sctgy[0]} = ("matrix_model_name", - "matrix_inport_name", - "matrix_outport_name", - "cell_model_name", - "cell_inport_name", - "cell_outport_name", - ); -# refer to the keywords of arch_device -# Support uni-directional routing architecture and -# single type segment only -@{$sctgy[1]} = ("R_minW_nmos", - "R_minW_pmos", - "ipin_mux_trans_size", - "C_ipin_cblock", - "T_ipin_cblock", - "grid_logic_tile_area", - "mux_R", - "mux_Cin", - "mux_Cout", - "mux_Tdel", - "mux_trans_size", - "mux_buf_size", - "segment_length", - "segment_Rmetal", - "segment_Cmetal", - "local_interconnect_C_wire", - "clock_buffer_size", - "clock_C_wire", - ); -# refer to the keywords of arch_complexblocks -@{$sctgy[2]} = (#"io_capacity", should be automatically optimized as 2*sqrt(N) - "CLB_logic_equivalent", - #"matrix_name", - #"matrix_cell_name", - "matrix_delay", - "cell_delay", - "dff_tsetup", - "dff_tclk2q", - "mux2to1_delay", # Delay of a 2:1 multiplexer, script can estimate N:1 multiplexer - "cell_dynamic_power", - "cell_static_power", - ); - -my ($SiNW_area_ratio) = (1.5); -# ----------Subrountines------------# - -# Print TABs -sub print_tabs($ $) -{ - my ($num_tab,$FILE) = @_; - my ($my_tab) = (" "); - - for (my $i = 0; $i < $num_tab; $i++) { - print $FILE "$my_tab"; - } -} - -# Create paths if it does not exist. -sub generate_path($) -{ - my ($mypath) = @_; - if (!(-e "$mypath")) - { - mkpath "$mypath"; - print "Path($mypath) does not exist...Create it.\n"; - } - return 1; -} - -# Print the usage -sub print_usage() -{ - print "Usage:\n"; - print " perl m2net.pl [-options ]\n"; - print " Mandatory options: \n"; - print " -conf : specify the basic configuration files for m2net\n"; - print " -mpack1_rpt : MPACK1 report file\n"; - print " -mode : select mode\n"; - print " 1. pack_arch : only output XML architecture file for AApack\n"; - print " 2. m2net : output XML architecture file for VPR, convert *.net file for VPR\n"; - print " -N : Number of MCluster inside a CLB\n"; - print " -I : Number of input of a CLB\n"; - #print " -rpt : m2net running log\n"; - print " Mandatory options for -mode pack_arch:\n"; - print " -arch_file_pack : filename of output XML format architecture file for AAPack\n"; - print " Mandatory options for -mode m2net:\n"; - print " -net_file_in : filename of input *.net file from AAPack\n"; - print " -net_file_out : filename of output *.net file for VPR\n"; - print " -arch_file_vpr : filename of output XML format architecture file for VPR\n"; - print " Other Options:\n"; - print " -power : add power estimation information to VPR ARCH XML\n"; - print " -debug : debug mode\n"; - print " -help : print usage\n"; - exit(1); - return 1; -} - -sub spot_option($ $) -{ - my ($start,$target) = @_; - my ($arg_no,$flag) = (-1,"unfound"); - for (my $iarg = $start; $iarg < $#ARGV+1; $iarg++) - { - if ($ARGV[$iarg] eq $target) - { - if ("found" eq $flag) - { - print "Error: Repeated Arguments!(IndexA: $arg_no,IndexB: $iarg)\n"; - &print_usage(); - } - else - { - $flag = "found"; - $arg_no = $iarg; - } - } - } - # return the arg_no if target is found - # or return -1 when target is missing - return $arg_no; -} - -# Specify in the input list, -# 1. Option Name -# 2. Whether Option with value. if yes, choose "on" -# 3. Whether Option is mandatory. If yes, choose "on" -sub read_opt_into_hash($ $ $) -{ - my ($opt_name,$opt_with_val,$mandatory) = @_; - # Check the -$opt_name - my ($opt_fact) = ("-".$opt_name); - my ($cur_arg) = (0); - my ($argfd) = (&spot_option($cur_arg,"$opt_fact")); - if ($opt_with_val eq "on") - { - if (-1 != $argfd) - { - if ($ARGV[$argfd+1] =~ m/^-/) - { - print "The next argument cannot start with '-'!\n"; - print "it implies an option!\n"; - } - else - { - $opt_ptr->{"$opt_name\_val"} = $ARGV[$argfd+1]; - $opt_ptr->{"$opt_name"} = "on"; - } - } - else - { - $opt_ptr->{"$opt_name"} = "off"; - if ($mandatory eq "on") - { - print "Mandatory option: $opt_fact is missing!\n"; - &print_usage(); - } - } - } - else - { - if (-1 != $argfd) - { - $opt_ptr->{"$opt_name"} = "on"; - } - else - { - $opt_ptr->{"$opt_name"} = "off"; - if ($mandatory eq "on") - { - print "Mandatory option: $opt_fact is missing!\n"; - &print_usage(); - } - } - } - return 1; -} - -# Read options -sub opts_read() -{ - # if no arguments detected, print the usage. - if (-1 == $#ARGV) - { - print "Error : No input arguments!\n"; - print "Try: -help for usage.\n"; - exit(1); - } - # Read in the options - my ($cur_arg,$arg_found); - $cur_arg = 0; - print "Analyzing your options...\n"; - # Read the options with internal options - my $argfd; - # Check help fist - $argfd = &spot_option($cur_arg,"-help"); - if (-1 != $argfd) { - print "Help desk:\n"; - &print_usage(); - } - # Then Check the debug with highest priority - $argfd = &spot_option($cur_arg,"-debug"); - if (-1 != $argfd) { - $opt_ptr->{"debug"} = "on"; - } - else { - $opt_ptr->{"debug"} = "off"; - } - - # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" - - # Check mode first - &read_opt_into_hash("mode","on","on"); - - # Check mandatory options - &read_opt_into_hash("conf","on","on"); # Check -conf - &read_opt_into_hash("mpack1_rpt","on","on"); # Check -mpack1_rpt - &read_opt_into_hash("N","on","on"); # Check -N - &read_opt_into_hash("I","on","on"); # Check -I - #&read_opt_into_hash("rpt","on","on"); # Check -rpt - - # Check mandatory options by mode selected - if ("pack_arch" eq $opt_ptr->{"mode_val"}) { - &read_opt_into_hash("arch_file_pack","on","on"); # Check -arch_file_mpack - } - elsif ("m2net" eq $opt_ptr->{"mode_val"}) { - &read_opt_into_hash("arch_file_vpr","on","on"); # Check -arch_file_vpr - &read_opt_into_hash("net_file_in","on","on"); # Check -net_file_in - &read_opt_into_hash("net_file_out","on","on"); # Check -net_file_out - } - else { - print "Error: unknown mode!\n"; - print "Help desk:\n"; - &print_usage(); - } - &read_opt_into_hash("power","off","off"); # Check -power - - &opts_echo(); - - return 1; -} - -# List the options -sub opts_echo() -{ - print "Echo your options:\n"; - - while(my ($key,$value) = each(%opt_h)) - {print "$key : $value\n";} - - return 1; -} - - -# Read each line and ignore the comments which starts with given arg -# return the valid information of line -sub read_line($ $) -{ - my ($line,$com) = @_; - my @chars; - if (defined($line)) - { - @chars = split/$com/,$line; - if (!($line =~ m/[\w\d]/)) - {$chars[0] = undef;} - if ($line =~ m/^\s*$com/) - {$chars[0] = undef;} - } - else - {$chars[0] = undef;} - if (defined($chars[0])) - { - $chars[0] =~ s/^(\s+)//g; - $chars[0] =~ s/(\s+)$//g; - } - return $chars[0]; -} - -# Check each keywords has been defined in configuration file -sub check_keywords_conf() -{ - for (my $imcg = 0; $imcg<$#mctgy+1; $imcg++) - { - for (my $iscg = 0; $iscg<$#{$sctgy[$imcg]}+1; $iscg++) - { - if (defined($conf_ptr->{$mctgy[$imcg]}->{$sctgy[$imcg]->[$iscg]}->{val})) - { - if ("on" eq $opt_ptr->{debug}) - { - print "Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) = "; - print "$conf_ptr->{$mctgy[$imcg]}->{$sctgy[$imcg]->[$iscg]}->{val}"; - print "\n"; - } - } - else - {die "Error: Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) is missing!\n";} - } - } - return 1; -} - -# Read the configuration file -sub read_conf() -{ - # Read in these key words - my ($line,$post_line); - my @equation; - my $cur = "unknown"; - open (CONF, "< $opt_ptr->{conf_val}") or die "Fail to open $opt_ptr->{conf}!\n"; - print "Reading $opt_ptr->{conf_val}..."; - while(defined($line = )) - { - chomp $line; - $post_line = &read_line($line,"#"); - if (defined($post_line)) - { - if ($post_line =~ m/\[(\w+)\]/) - {$cur = $1;} - elsif ("unknown" eq $cur) - { - die "Error: Unknown tags for this line!\n$post_line\n"; - } - else - { - $post_line =~ s/\s//g; - @equation = split /=/,$post_line; - $conf_ptr->{$cur}->{$equation[0]}->{val} = $equation[1]; - } - } - } - # Check these key words - print "complete!\n"; - print "Checking these keywords..."; - &check_keywords_conf(); - print "Successfully\n"; - close(CONF); - return 1; -} - -# Input program path is like "~/program_dir/program_name" -# We split it from the scalar -sub split_prog_path($) -{ - my ($prog_path) = @_; - my @path_elements = split /\//,$prog_path; - my ($prog_dir,$prog_name); - - $prog_name = $path_elements[$#path_elements]; - $prog_dir = $prog_path; - $prog_dir =~ s/$prog_name$//g; - - return ($prog_dir,$prog_name); -} - -# Read MPACK1 Report -# Determine matrix width, matrix height -# Determine matrix internal connections -# Store pack information for each cell -sub read_mpack1_rpt() -{ - # Read in these key words - my ($line,$post_line,$line_no); - my ($layer_line_cnt,$mcluster_line_cnt,$mcluster_cnt); - my ($checking_layer,$checking_mclusters,$expected_layer_line_no,$expected_mcluster_line_no) = (0,0,-1,-1); - my ($x,$y); - my @split_line; - # Define keywords - my ($matrix_width,$matrix_depth,$cell_size,$layer,$layer_matrix,$mcluster,$mcluster_cell,$unconn,$conn,$open_net,$end,$mcluster_num) = ("matrix_width","matrix_depth","cell_size","layer_detailed","X","MCluster","cell","unconn","conn","open","end","mclusters_number"); - - open (MRPT, "< $opt_ptr->{mpack1_rpt_val}") or die "Fail to open mpack1_rpt: $opt_ptr->{mpack1_rpt_val}!\n"; - print "Reading $opt_ptr->{mpack1_rpt_val}..."; - - $line_no = 0; - $mcluster_cnt = 0; - - while(defined($line = )) - { - chomp $line; - $post_line = &read_line($line,"#"); - $line_no = $line_no + 1; - if (defined($post_line)) - { - # Remove all spaces... - $post_line =~ s/\s//g; - # This case should not happen! - if ((1 == $checking_layer)&&(1 == $checking_mclusters)) { - die "Error: checking_layer and checking_mclusters both turn on!\n"; - } - # TODO List: - if ((0 == $checking_layer)&&(0 == $checking_mclusters)) { - # Check Width - if ($post_line =~ m/^$matrix_width/) { - undef @split_line; - @split_line = split /=/,$post_line; - # Double check - if ($matrix_width eq $split_line[0]) { - $mclusters_ptr->{matrix_width} = $split_line[1]; - next; - } - else { - print "Warning:Invalid definition for matrix width at LINE[$line_no]!\n"; - } - } - # Check Depth - if ($post_line =~ m/^$matrix_depth/) { - undef @split_line; - @split_line = split /=/,$post_line; - # Double check - if ($matrix_depth eq $split_line[0]) { - $mclusters_ptr->{matrix_depth} = $split_line[1]; - next; - } - else { - print "Warning:Invalid definition for matrix depth at LINE[$line_no]!\n"; - } - } - # Check cell_size - if ($post_line =~ m/^$cell_size/) { - undef @split_line; - @split_line = split /=/,$post_line; - # Double check - if ($cell_size eq $split_line[0]) { - $mclusters_ptr->{cell_size} = $split_line[1]; - next; - } - else { - print "Warning:Invalid definition for cell size at LINE[$line_no]!\n"; - } - } - # Check defined MCluster Number - if ($post_line =~ m/^$mcluster_num/) { - undef @split_line; - @split_line = split /=/,$post_line; - # Double check - if ($mcluster_num eq $split_line[0]) { - $mclusters_ptr->{MCluster_num} = $split_line[1]; - next; - } - else { - print "Warning:Invalid definition for $mcluster_num at LINE[$line_no]!\n"; - } - } - # Check layer - # TODO: We should check layer should only defined ONCE!!! - if ($post_line =~ m/^$layer/) { - $checking_layer = 1; - # Clear Counter - $layer_line_cnt = 0; - # Check valid expected_layer_line_no - $expected_layer_line_no = $mclusters_ptr->{matrix_width}*($mclusters_ptr->{matrix_depth}-1)*$mclusters_ptr->{cell_size}; - if (($expected_layer_line_no < 1)&&(1 != $mclusters_ptr->{matrix_width}*$mclusters_ptr->{matrix_depth})) { - die "Error: Invalid expected_layer_line_no($expected_layer_line_no)!\nProbably caused by missing definition of $matrix_width, $matrix_depth, $cell_size before defining $layer...\n"; - } - next; - } - # Check MClusters - if ($post_line =~ m/^$mcluster/) { - $checking_mclusters = 1; - # Clear Counter - $mcluster_line_cnt = 0; - # Check valid expected_mcluster_line_no - $expected_mcluster_line_no = $mclusters_ptr->{matrix_width}*$mclusters_ptr->{matrix_depth}; - if ($expected_mcluster_line_no < 1) { - die "Error: Invalid expected_mcluster_line_no($expected_mcluster_line_no)!\nProbably caused by missing definition of $matrix_width, $matrix_depth, $cell_size before defining $mcluster...\n"; - } - next; - } - } - - # Layer FSM - if (1 == $checking_layer) { - # Check expected_layer_line_no - if ($expected_layer_line_no < $layer_line_cnt) { - die "Error: expected_layer_line_no($expected_layer_line_no) unmatch layer_line_cnt($layer_line_cnt)! Missing information for layer definition!\n"; - } - if ($post_line =~ m/^$end/) { - $checking_layer = 0; - # Check expected_layer_line_no - if ($expected_layer_line_no != $layer_line_cnt) { - die "Error: expected_layer_line_no($expected_layer_line_no) unmatch layer_line_cnt($layer_line_cnt)! Missing information for layer definition!\n"; - } - next; - } - if ($post_line =~ m/^$layer_matrix/) { - undef @split_line; - my ($pin) = ("I"); - #@split_line = split /=/,$post_line; - # Get layer x,y, and double check - if ($post_line =~ m/^$layer_matrix\[(\d+)\]\.$pin\[(\d+)\]=(\d+)/) { - # Record des_idx, pin_idx, src_idx - my ($des_idx,$pin_idx,$src_idx) = ($1,$2,$3); - # Record X and Y - my ($des_y,$des_x) = (($des_idx)%($mclusters_ptr->{matrix_width}),int($des_idx/$mclusters_ptr->{matrix_width})); - my ($src_y,$src_x) = (($src_idx)%($mclusters_ptr->{matrix_width}),int($src_idx/$mclusters_ptr->{matrix_width})); - # Check X range. Should be 0 < X < matrix_depth - if (0 == $des_x) { - print "Warning: there is no need to define zero layer at LINE[$line_no]!\n"; - next; - } - if ((0 > $des_x)||($des_x > ($mclusters_ptr->{matrix_depth}-1))) { - die "Error: Invalid des_x($des_x) in LINE[$line_no]!\n"; - } - # Check Y range. Should be 0 <= Y < matrix_width - if ((0 > $des_y)||($des_y > ($mclusters_ptr->{matrix_width}-1))) { - die "Error: Invalid des_y($des_y) in LINE[$line_no]!\n"; - } - # Check X range. Should be 0 < X < matrix_depth - if ((0 > $src_x)||($src_x > ($mclusters_ptr->{matrix_depth}-1))) { - die "Error: Invalid src_x($src_x) in LINE[$line_no]!\n"; - } - # Check Y range. Should be 0 <= Y < matrix_width - if ((0 > $src_y)||($src_y > ($mclusters_ptr->{matrix_width}-1))) { - die "Error: Invalid src_y($src_y) in LINE[$line_no]!\n"; - } - $mclusters_ptr->{"arch"}->{"cell[$des_x][$des_y]"}->{"I[$pin_idx]"} = $src_y; - # Check matrix content, chomp the last "," and length should be matrix_width - #$split_line[1] =~ s/,$//; # Chomp last "," - #my @tmp = split /,/,$split_line[1]; - #if ($#tmp != ($mclusters_ptr->{matrix_width}-1)) { - # die "Error: Invalid length of cross-connectivity matrix!\n"; - #} - #my $j = 0; - #for (my $i=0; $i<$mclusters_ptr->{matrix_width}; $i++) { - # Valid $tmp[$i] is either 0 or 1 - # if ((0 != $tmp[$i])&&(1 != $tmp[$i])) { - # die "Error: Invalid value of cross-connectivity matrix at LINE[$line_no]!\n"; - # } - # if (1 == $tmp[$i]) { - # $mclusters_ptr->{"arch"}->{"cell[$x][$y]"}->{"I[$j]"} = $i; - # $j = $j + 1; - # } - #} - # Check $j (number of input) - #if ($j != $mclusters_ptr->{cell_size}) { - # die "Error: cross-connectivity matrix exceeds cell_size at LINE[$line_no]!\n"; - #} - - $layer_line_cnt = $layer_line_cnt + 1; - } - else { - print "Warning: Invalid definition of $layer_matrix in $layer at LINE($line_no)!\n"; - } - } - next; - } - - # Mcluster FSM - if (1 == $checking_mclusters) { - # Check expected_mcluster_line_no - if ($expected_mcluster_line_no < $mcluster_line_cnt) { - die "Error: expected_mcluster_line_no($expected_mcluster_line_no) unmatch mcluster_line_cnt($mcluster_line_cnt)! Missing information for MCluster definition!\n"; - } - if ($post_line =~ m/^$end/) { - $checking_mclusters = 0; - # Check expected_mcluster_line_no - if ($expected_mcluster_line_no != $mcluster_line_cnt) { - die "Error: expected_mcluster_line_no($expected_mcluster_line_no) unmatch mcluster_line_cnt($mcluster_line_cnt)! Missing information for MCluster definition!\n"; - } - # Incremental Mcluster counter - $mcluster_cnt = $mcluster_cnt + 1; - next; - } - if ($post_line =~ m/^$mcluster_cell/) { - undef @split_line; - @split_line = split /=/,$post_line; - # Get layer x,y, and double check - if ($split_line[0] =~ m/^$mcluster_cell\[(\d+)\]\[(\d+)\]/) { - # Record X and Y - ($x,$y) = ($1,$2); - # Check X range. Should be 0 <= X < matrix_depth - if ((0 > $x)||($x > ($mclusters_ptr->{matrix_depth}-1))) { - die "Error: Invalid x($x) in LINE[$line_no]!\n"; - } - # Check Y range. Should be 0 <= Y < matrix_width - if ((0 > $y)||($y > ($mclusters_ptr->{matrix_width}-1))) { - die "Error: Invalid y($y) in LINE[$line_no]!\n"; - } - # Check matrix content, chomp the last "," and length should be matrix_width - $split_line[1] =~ s/,$//; # Chomp last "," - my @tmp = split /,/,$split_line[1]; - if ($#tmp != ($mclusters_ptr->{cell_size})) { - die "Error: Invalid length of MCluster cell definition at LINE[$line_no]!\n"; - } - for (my $i=0; $i<$mclusters_ptr->{cell_size}; $i++) { - # Valid $tmp[$i] is either $unconn or $conn - if (($unconn ne $tmp[$i])&&($conn ne $tmp[$i])) { - die "Error: Invalid value of MCluster cell definition at LINE[$line_no]!\n"; - } - $mclusters_ptr->{"MCluster$mcluster_cnt"}->{"cell[$x][$y]"}->{"I[$i]"} = $tmp[$i]; - } - $mclusters_ptr->{"MCluster$mcluster_cnt"}->{"cell[$x][$y]"}->{"net"} = $tmp[$mclusters_ptr->{cell_size}]; - - $mcluster_line_cnt = $mcluster_line_cnt + 1; - } - else { - print "Warning: Invalid definition of $mcluster_cell in $mcluster at LINE($line_no)!\n"; - } - } - next; - } - } - } - print "complete!\n"; - - # Check mcluster_number match - if ($mcluster_cnt != $mclusters_ptr->{MCluster_num}) { - die "Error: Mismatch!(Expect $mclusters_ptr->{MCluster_num} MClusters, Actual $mcluster_cnt)\n"; - } - - close(MRPT); - - # Update Number of MClusters - #$mclusters_ptr->{MCluster_num} = $mcluster_cnt; - - print "Number of MCluster: $mclusters_ptr->{MCluster_num}\n"; - - return 1; -} - -# Print models for AApack Architecture -sub gen_arch_models_pack() -{ - my ($minput_num,$moutput_num) = ($mclusters_ptr->{cell_size}*$mclusters_ptr->{matrix_width},$mclusters_ptr->{matrix_width}); - - print FARCH " \n"; - print FARCH " {arch_model}->{matrix_model_name}->{val}\">\n"; - print FARCH " \n"; - print FARCH " {arch_model}->{matrix_inport_name}->{val}\"/>\n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " {arch_model}->{matrix_outport_name}->{val}\"/>\n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; -} - -sub gen_arch_device() -{ - my ($power_buf_size,$power_mux_trans_size); - ($power_buf_size) = ($conf_ptr->{arch_device}->{mux_buf_size}->{val}/$SiNW_area_ratio); - ($power_mux_trans_size) = ($conf_ptr->{arch_device}->{mux_trans_size}->{val}/$SiNW_area_ratio); - - print FARCH " \n"; - print FARCH " \n"; - print FARCH " {arch_device}->{R_minW_nmos}->{val}\" R_minW_pmos=\"$conf_ptr->{arch_device}->{R_minW_pmos}->{val}\" ipin_mux_trans_size=\"$conf_ptr->{arch_device}->{ipin_mux_trans_size}->{val}\"/>\n"; - print FARCH " {arch_device}->{C_ipin_cblock}->{val}\" T_ipin_cblock=\"$conf_ptr->{arch_device}->{T_ipin_cblock}->{val}\"/>\n"; - print FARCH " {arch_device}->{grid_logic_tile_area}->{val}\"/>\n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " {arch_device}->{mux_R}->{val}\" Cin=\"$conf_ptr->{arch_device}->{mux_Cin}->{val}\" Cout=\"$conf_ptr->{arch_device}->{mux_Cout}->{val}\" Tdel=\"$conf_ptr->{arch_device}->{mux_Tdel}->{val}\" mux_trans_size=\"$conf_ptr->{arch_device}->{mux_trans_size}->{val}\" buf_size=\"$conf_ptr->{arch_device}->{mux_buf_size}->{val}\" power_buf_size=\"$power_buf_size\"/>\n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " {arch_device}->{segment_length}->{val}\" type=\"unidir\" Rmetal=\"$conf_ptr->{arch_device}->{segment_Rmetal}->{val}\" Cmetal=\"$conf_ptr->{arch_device}->{segment_Cmetal}->{val}\">\n"; - print FARCH " \n"; - print FARCH " "; - - for (my $i=0; $i<($conf_ptr->{arch_device}->{segment_length}->{val}+1); $i++) { - print FARCH "1 "; - } - - print FARCH "\n"; - - print FARCH " "; - - for (my $i=0; $i<$conf_ptr->{arch_device}->{segment_length}->{val}; $i++) { - print FARCH "1 "; - } - - print FARCH "\n"; - print FARCH " \n"; - print FARCH " \n"; - -} - -sub gen_arch_complexblocks_io() -{ - my ($io_optimal) = int(2*sqrt($opt_ptr->{N_val}*$mclusters_ptr->{matrix_width})+0.5); - - # Print I/O pad first(Constraint of VPR 7) - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " io.outpad io.inpad io.clock\n"; - print FARCH " io.outpad io.inpad io.clock\n"; - print FARCH " io.outpad io.inpad io.clock\n"; - print FARCH " io.outpad io.inpad io.clock\n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - if ("on" eq $opt_ptr->{power}) { - print FARCH " \n"; - } - print FARCH " \n"; - # I/O pad print over - - - print FARCH "\n"; -} - -sub gen_arch_complexblocks_dffs() -{ - # Print DFFs - print FARCH " {matrix_width}\" class=\"flipflop\">\n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " {arch_complexblocks}->{dff_tsetup}->{val}\" port=\"ff.D\" clock=\"clk\"/>\n"; - print FARCH " {arch_complexblocks}->{dff_tclk2q}->{val}\" port=\"ff.Q\" clock=\"clk\"/>\n"; - print FARCH " \n"; - - print FARCH "\n"; -} - -# Print Complex Block for Matrix Marco -sub gen_arch_complexblocks_matrix_marco() -{ - my ($mcluster_input_num,$mcluster_output_num); - $mcluster_input_num = $mclusters_ptr->{matrix_width}*$mclusters_ptr->{cell_size}; - $mcluster_output_num = $mclusters_ptr->{matrix_width}; - - # Print Matrix Marco Pb_type - print FARCH " {arch_model}->{matrix_model_name}->{val}\" num_pb=\"1\">\n"; - print FARCH " {arch_model}->{matrix_inport_name}->{val}\" num_pins=\"$mcluster_input_num\"/>\n"; - print FARCH " {arch_model}->{matrix_outport_name}->{val}\" num_pins=\"$mcluster_output_num\"/>\n"; - print FARCH " {arch_model}->{matrix_inport_name}->{val}\" out_port=\"matrix.$conf_ptr->{arch_model}->{matrix_outport_name}->{val}\">\n"; - - for (my $i=0; $i<$mcluster_input_num; $i++) { - print FARCH " "; - for (my $j=0; $j<$mcluster_output_num; $j++) { - print FARCH "$conf_ptr->{arch_complexblocks}->{matrix_delay}->{val} "; - } - print FARCH "\n"; - } - - print FARCH " \n"; - print FARCH " \n"; - -} - -# Print Complex Blocks for CLB, only for AAPack -sub gen_arch_complexblocks_clb_pack() -{ - my ($clb_input_num,$clb_output_num); - my ($mcluster_input_num,$mcluster_output_num); - - $mcluster_input_num = $mclusters_ptr->{matrix_width}*$mclusters_ptr->{cell_size}; - $mcluster_output_num = $mclusters_ptr->{matrix_width}; - $clb_input_num = $opt_ptr->{I_val}; - $clb_output_num = $opt_ptr->{N_val}*$mclusters_ptr->{matrix_width}; - - # Print CLB general information - print FARCH " \n"; - print FARCH " {arch_complexblocks}->{CLB_logic_equivalent}->{val}\"/>\n"; - print FARCH " \n"; - print FARCH " \n"; - - # Print Sub Complex Block "BLE" - print FARCH " {N_val}\">\n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - - &gen_arch_complexblocks_matrix_marco(); - - &gen_arch_complexblocks_dffs(); - - # Print interconnections for BLE - my ($ff_idx) = ($mcluster_output_num-1); - print FARCH " \n"; - # Clock - print FARCH " \n"; - print FARCH " {arch_model}->{matrix_inport_name}->{val}\"/>\n"; - print FARCH " {arch_model}->{matrix_outport_name}->{val}\" output=\"ff[$ff_idx:0].D\"/>\n"; - - for (my $i=0; $i<$mclusters_ptr->{matrix_width}; $i++) { - print FARCH " {arch_model}->{matrix_outport_name}->{val}\[$i\]\" output=\"mble.O\[$i\]\">\n"; - print FARCH " {arch_complexblocks}->{mux2to1_delay}->{val}\" in_port=\"ff[$i].Q matrix.$conf_ptr->{arch_model}->{matrix_outport_name}->{val}\[$i\]\" out_port=\"mble.O\[$i\]\"/>\n"; - print FARCH " \n"; - } - - print FARCH " \n"; - print FARCH " \n"; - - # Print interconnection for CLB - my ($crossbar_delay) = ($conf_ptr->{arch_complexblocks}->{mux2to1_delay}->{val}*int(log($clb_input_num+$opt_ptr->{N_val}*$mcluster_output_num-1)/log(2)+1)); - my ($mble_idx) = ($opt_ptr->{N_val}-1); - print FARCH " \n"; - # Crossbar - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - # Clock - print FARCH " \n"; - print FARCH " \n"; - - print FARCH " \n"; - - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - - print FARCH "\n"; -} - -# Print Complex Blocks for AAPack usage -sub gen_arch_complexblocks_pack() -{ - print FARCH " \n"; - - # Print I/O pad first - &gen_arch_complexblocks_io(); - - # Print Matrix-based Pb_type - &gen_arch_complexblocks_clb_pack(); - print FARCH " \n"; -} - -sub gen_arch_pack() -{ - my ($line,$post_line,$line_no); - - print "Generating Architecture XML($opt_ptr->{arch_file_pack_val}) for AAPack..."; - - open (FARCH, "> $opt_ptr->{arch_file_pack_val}") or die "Fail to open arch_pack: $opt_ptr->{arch_file_pack_val}!\n"; - - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - - # Write - &gen_arch_models_pack(); - - # Write - &gen_arch_device(); - - # Write - &gen_arch_complexblocks_pack(); - - print FARCH "\n"; - - close(FARCH); - - print "Complete.\n"; -} - -# Print models for VPR Architecture -sub gen_arch_models_vpr() -{ - my ($minput_num,$moutput_num) = ($mclusters_ptr->{cell_size},1); - - print FARCH " \n"; - print FARCH " {arch_model}->{cell_model_name}->{val}\">\n"; - print FARCH " \n"; - print FARCH " {arch_model}->{cell_inport_name}->{val}\"/>\n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " {arch_model}->{cell_outport_name}->{val}\"/>\n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; -} - -# Print Complex Block for Matrix Cells -sub gen_arch_complexblocks_matrix_cells() -{ - my ($num_cell) = ($mclusters_ptr->{matrix_width}*$mclusters_ptr->{matrix_depth}); - # Print Matrix Cell Pb_type - print FARCH " {arch_model}->{cell_model_name}->{val}\" num_pb=\"$num_cell\">\n"; - print FARCH " {arch_model}->{cell_inport_name}->{val}\" num_pins=\"$mclusters_ptr->{cell_size}\"/>\n"; - print FARCH " {arch_model}->{cell_outport_name}->{val}\" num_pins=\"1\"/>\n"; - print FARCH " {arch_model}->{cell_inport_name}->{val}\" out_port=\"cell.$conf_ptr->{arch_model}->{cell_outport_name}->{val}\">\n"; - - for (my $i=0; $i<$mclusters_ptr->{cell_size}; $i++) { - print FARCH " "; - print FARCH "$conf_ptr->{arch_complexblocks}->{cell_delay}->{val} "; - print FARCH "\n"; - } - - print FARCH " \n"; - if ("on" eq $opt_ptr->{power}) { - print FARCH " \n"; - print FARCH " {arch_complexblocks}->{cell_dynamic_power}->{val}\"/>\n"; - print FARCH " {arch_complexblocks}->{cell_static_power}->{val}\"/>\n"; - print FARCH " \n"; - } - print FARCH " \n"; - -} - -# Print Complex Blocks for CLB, only for VPR -sub gen_arch_complexblocks_clb_vpr() -{ - my ($clb_input_num,$clb_output_num); - my ($mcluster_input_num,$mcluster_output_num); - - $mcluster_input_num = $mclusters_ptr->{matrix_width}*$mclusters_ptr->{cell_size}; - $mcluster_output_num = $mclusters_ptr->{matrix_width}; - $clb_input_num = $opt_ptr->{I_val}; - $clb_output_num = $opt_ptr->{N_val}*$mclusters_ptr->{matrix_width}; - - # Print CLB general information - print FARCH " \n"; - print FARCH " {arch_complexblocks}->{CLB_logic_equivalent}->{val}\"/>\n"; - print FARCH " \n"; - print FARCH " \n"; - - # Print Sub Complex Block "BLE" - print FARCH " {N_val}\">\n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " {arch_model}->{matrix_inport_name}->{val}\" num_pins=\"$mcluster_input_num\"/>\n"; - print FARCH " {arch_model}->{matrix_outport_name}->{val}\" num_pins=\"$mcluster_output_num\"/>\n"; - - &gen_arch_complexblocks_matrix_cells(); - - print FARCH " \n"; - # Print Interconnection Scheme(Internal Matrix), cell[$i][$j], $i->row $j->column - for (my $i=0; $i<$mclusters_ptr->{matrix_depth}; $i++) { - for (my $j=0; $j<$mclusters_ptr->{matrix_width}; $j++) { - my ($cell_num) = ($i*$mclusters_ptr->{matrix_width} + $j); - for (my $k=0; $k<$mclusters_ptr->{cell_size}; $k++) { - if (0 == $i) { - my ($input_idx) = ($j*$mclusters_ptr->{cell_size}+$k); - print FARCH " {arch_model}->{matrix_inport_name}->{val}\[$input_idx\]\" output=\"cell[$cell_num].$conf_ptr->{arch_model}->{cell_inport_name}->{val}\[$k\]\"/>\n"; - } - else { - my ($pred_idx) = ($mclusters_ptr->{"arch"}->{"cell[$i][$j]"}->{"I[$k]"}+($i-1)*$mclusters_ptr->{matrix_width}); - print FARCH " {arch_model}->{cell_outport_name}->{val}\" output=\"cell[$cell_num].$conf_ptr->{arch_model}->{cell_inport_name}->{val}\[$k\]\"/>\n"; - } - } - } - } - # Print Output direct interconnections, cells.O -> matrix.O - for (my $j=0; $j<$mclusters_ptr->{matrix_width}; $j++) { - my ($last_layer) = ($mclusters_ptr->{matrix_depth}-1); - my ($pred_idx) = ($mclusters_ptr->{matrix_width}*$last_layer + $j); - print FARCH " {arch_model}->{cell_outport_name}->{val}\" output=\"matrix.$conf_ptr->{arch_model}->{matrix_outport_name}->{val}\[$j\]\"/>\n"; - } - - print FARCH " \n"; - print FARCH " \n"; - - &gen_arch_complexblocks_dffs(); - - # Print interconnections for BLE - my ($ff_idx) = ($mcluster_output_num-1); - print FARCH " \n"; - # Clock - print FARCH " \n"; - print FARCH " {arch_model}->{matrix_inport_name}->{val}\"/>\n"; - print FARCH " {arch_model}->{matrix_outport_name}->{val}\" output=\"ff[$ff_idx:0].D\"/>\n"; - - # Print MUX for DFFs - for (my $i=0; $i<$mclusters_ptr->{matrix_width}; $i++) { - my ($cur_cell_idx) = ($i+$mclusters_ptr->{matrix_width}*($mclusters_ptr->{matrix_depth}-1)); - print FARCH " \n"; - print FARCH " {arch_complexblocks}->{mux2to1_delay}->{val}\" in_port=\"ff[$i].Q matrix.O[$i]\" out_port=\"mble.O[$i]\"/>\n"; - print FARCH " \n"; - } - - print FARCH " \n"; - print FARCH " \n"; - - # Print interconnection for CLB - my ($crossbar_delay) = ($conf_ptr->{arch_complexblocks}->{mux2to1_delay}->{val}*int(log($clb_input_num+$opt_ptr->{N_val}*$mcluster_output_num-1)/log(2)+1)); - my ($mble_idx) = ($opt_ptr->{N_val}-1); - print FARCH " \n"; - # Crossbar - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - # Clock - print FARCH " \n"; - print FARCH " \n"; - - print FARCH " \n"; - - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - #print FARCH " \n"; - #print FARCH " \n"; - print FARCH " \n"; - - print FARCH "\n"; -} - -# Print Complex Blocks for VPR usage -sub gen_arch_complexblocks_vpr() -{ - print FARCH " \n"; - - # Print I/O pad first - &gen_arch_complexblocks_io(); - - # Print Matrix-based Pb_type - &gen_arch_complexblocks_clb_vpr(); - print FARCH " \n"; -} - -sub gen_arch_vpr() -{ - my ($line,$post_line,$line_no); - - print "Generating Architecture XML($opt_ptr->{arch_file_vpr_val}) for VPR 7..."; - - open (FARCH, "> $opt_ptr->{arch_file_vpr_val}") or die "Fail to open arch_vpr: $opt_ptr->{arch_file_vpr_val}!\n"; - - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - print FARCH "\n"; - - # Write - &gen_arch_models_vpr(); - - # Write - &gen_arch_device(); - - # Write - &gen_arch_complexblocks_vpr(); - - if ("on" eq $opt_ptr->{power}) { - my ($power_buf_size,$power_mux_trans_size); - ($power_buf_size) = ($conf_ptr->{arch_device}->{mux_buf_size}->{val}/$SiNW_area_ratio); - ($power_mux_trans_size) = ($conf_ptr->{arch_device}->{mux_trans_size}->{val}/$SiNW_area_ratio); - print FARCH " \n"; - print FARCH " {arch_device}->{local_interconnect_C_wire}->{val}\"/>\n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " \n"; - print FARCH " {arch_device}->{clock_buffer_size}->{val}\" C_wire=\"$conf_ptr->{arch_device}->{clock_C_wire}->{val}\"/>\n"; - print FARCH " \n"; - } - - print FARCH "\n"; - - close(FARCH); - - print "Complete\n"; -} - -sub gen_net_vpr() -{ - my ($mytab) = (" "); - my %net_map; - my ($net_map_ptr) = (\%net_map); - my ($line); - my ($state,$next_state,$mcluster_index) = ("ST_NORMAL","ST_NORMAL",-1); - my ($nets); - - print "Building Hash mapping nets names to MCluster Index...\n"; - - # 1. Build a hash map net names to MCluster index - for (my $i=0; $i<$mclusters_ptr->{MCluster_num}; $i++) { - my (@net_names); - for (my $j=0; $j<$mclusters_ptr->{matrix_width}; $j++) { - my ($last_layer) = ($mclusters_ptr->{matrix_depth}-1); - $net_names[$j] = $mclusters_ptr->{"MCluster$i"}->{"cell[$last_layer][$j]"}->{net}; - } - my ($nets) = join($mytab,@net_names); - - $nets = $nets.$mytab; - #print "DEBUG: NETs($nets)\n"; - $net_map_ptr->{"$nets"}->{"Mcluster_index"} = $i; - } - - print "Generating Net_file_VPR ($opt_ptr->{net_file_out_val}) from Net_file_AAPACK ($opt_ptr->{net_file_in_val})..."; - # 2. Replace Part of *.net format file - # Open net_file_in, read-only - open (FNETI, "< $opt_ptr->{net_file_in_val}") or die "Fail to open input *net formate file: $opt_ptr->{net_file_in_val}!\n"; - # Open net_file_out, write-only - open (FNETO, "> $opt_ptr->{net_file_out_val}") or die "Fail to open output *net formate file: $opt_ptr->{net_file_out_val}!\n"; - - # Copy & Paste from FNETI to FNETO - $state = "ST_NORMAL"; - while (defined($line = )) { - chomp $line; - # States : ST_NORMAL, ST_SKIP_INPUTS, ST_MODIFY_OUTPUTS, ST_SKIP_CLOCK - # ST_NORAML: Try to match instance = "matrix" - # ST_SKIP_INPUTS: We got matched "matrix", skip the - # ST_MODIFT_OUTPUTS: We got matched "matrix and skip the , modify - # ST_SKIP_CLOCK: We got matched matrix, skip and modify , skip and add subblocks - if ("ST_NORMAL" eq $state) { - # Regular expression to match block name="" instance="" - if ($line =~ m/block(\s+)name(\s*)=(\s*)\"([\w\d\[\]\_\-\&\^\;]+)\"(\s+)instance(\s*)=(\s*)\"([\w\d\[\]\_\-\&\^\;]+)\"/) { - my ($name,$instance) = ($4,$8); - # Change state only when name != open - # Replace the outputs of instance = matrix - if (("open" ne $name)&&($instance =~ m/matrix/)) { - # Inside a matrix, skip inputs, switch to state = ST_SKIP_INPUTS - print FNETO " "; - print FNETO "\n"; - $next_state = "ST_SKIP_INPUTS"; - next; - } - } - print FNETO "$line\n"; - } - elsif ("ST_SKIP_INPUTS" eq $state) { - # Match , DEBUG - if (($line =~ m/\/)&&("on" eq $opt_ptr->{debug})) { - print "DEBUG: Match \n"; - } - # Match - if ($line =~ m/\<\/inputs\>/) { - $next_state = "ST_MODIFY_OUTPUTS"; - $mcluster_index = -1; - } - print FNETO "$line\n"; - } - elsif ("ST_MODIFY_OUTPUTS" eq $state) { - my ($line_copy) = ($line); - # Determine the index of MCluster by comparing net_names! - # Match net_names - if ($line_copy =~ m/{arch_model}->{matrix_outport_name}->{val}\">([\d\w\_\s\-\^\&\;\[\]]+)<\/port>/) { - ($nets) = ($4); - } - $line_copy = $line; - # Match and print modified outputs - if ($line_copy =~ m/\<\/outputs\>/) { - my ($format_nets); - $next_state = "ST_SKIP_CLOCK"; - # Check Valid MCluster_index - my @net_names = split /\s+/,$nets; - for (my $i = 0; $i < ($#net_names+1); $i++) { - $format_nets = $format_nets."$net_names[$i]$mytab"; - } - if (exists($net_map_ptr->{"$format_nets"}->{"Mcluster_index"})) { - $mcluster_index = $net_map_ptr->{"$format_nets"}->{"Mcluster_index"}; - } - else { - die "Error: Invalid Net names($format_nets)\n"; - } - - print FNETO " "; - print FNETO "\n"; - my ($last_layer) = ($mclusters_ptr->{matrix_depth}-1); - print FNETO " "; - for (my $i = 0; $i < $mclusters_ptr->{matrix_width}; $i++) { - my ($pred_idx) = ($mclusters_ptr->{matrix_width}*$last_layer + $i); - print FNETO "cell[$pred_idx].$conf_ptr->{arch_model}->{cell_outport_name}->{val}\-\>matrix_output[$i] "; - } - print FNETO "\n"; - print FNETO " "; - print FNETO "\n"; - print FNETO " "; - print FNETO "\n"; - print FNETO " "; - print FNETO "\n"; - } - } - elsif ("ST_SKIP_CLOCK" eq $state) { - # Match and print subblocks - if ($line =~ m/\<\/clocks\>/) { - $next_state = "ST_NORMAL"; - - # Check mcluster_index - if (-1 == $mcluster_index) { - die "Error: Invalid mcluster index: $mcluster_index!\n"; - } - # Print subblocks - my ($num_cell) = ($mclusters_ptr->{matrix_width}*$mclusters_ptr->{matrix_depth}); - for (my $i = 0; $i < $mclusters_ptr->{matrix_depth}; $i++) { - for (my $j = 0; $j < $mclusters_ptr->{matrix_width}; $j++) { - my ($cell_idx) = $i*$mclusters_ptr->{matrix_width} + $j; - # Fill block_name and instance_name - my ($block_name,$instance_name) = ($mclusters_ptr->{"MCluster$mcluster_index"}->{"cell[$i][$j]"}->{net},"cell[$cell_idx]"); - print FNETO " "; - print FNETO "\n"; - # Check if this block has been used. - if ("open" ne $block_name) { - # Print Input Ports, Output Ports, ignore clocks - print FNETO " "; - print FNETO " \n"; - print FNETO " "; - print FNETO " {arch_model}->{cell_inport_name}->{val}\">"; - for (my $k = 0; $k < $mclusters_ptr->{cell_size}; $k++) { - if ("unconn" eq $mclusters_ptr->{"MCluster$mcluster_index"}->{"cell[$i][$j]"}->{"I[$k]"}) { - print FNETO "open "; - } - elsif (0 == $i) { - my ($tmp_idx) = ($j*$mclusters_ptr->{cell_size}+$k); - print FNETO "matrix[0].I[$tmp_idx]\-\>cell[$i][$j]_input[$k] "; - } - else { - my ($pred_idx) = ($mclusters_ptr->{"arch"}->{"cell[$i][$j]"}->{"I[$k]"}+($i-1)*$mclusters_ptr->{matrix_width}); - print FNETO "cell[$pred_idx].$conf_ptr->{arch_model}->{cell_outport_name}->{val}\-\>cell[$i][$j]_input[$k] "; - } - } - print FNETO "\n"; - print FNETO " "; - print FNETO " \n"; - print FNETO " "; - print FNETO " \n"; - print FNETO " "; - print FNETO " {arch_model}->{cell_outport_name}->{val}\">"; - print FNETO "$block_name "; - print FNETO "\n"; - print FNETO " "; - print FNETO " \n"; - print FNETO " "; - print FNETO " \n"; - print FNETO " "; - print FNETO " \n"; - } - print FNETO " "; - print FNETO "\n"; - } - } - } - } - $state = $next_state; - if ("on" eq $opt_ptr->{debug}) { - print "DEBUG: Current State=$state\n"; - } - } - - # Close files - close(FNETI); - close(FNETO); - - #print "Generate Net_file_VPR \($opt_ptr->{net_file_out_val}\) from Net_file_AAPACK \($opt_ptr->{net_file_in_val}\) Complete\n"; - print "Complete\n"; -} - -# Main Program -sub main() -{ - # Read Options. All options stored in opt_ptr - &opts_read(); - - # Read basic configuration file. All confs stored in conf_ptr - &read_conf(); - - # Read mpack report file - &read_mpack1_rpt(); - - # Complete tasks according to selected mode - if ("pack_arch" eq $opt_ptr->{"mode_val"}) { - # Generate Architecture XML for AAPack - &gen_arch_pack(); - } - elsif ("m2net" eq $opt_ptr->{"mode_val"}) { - # Generate Architecture XML for VPR - &gen_arch_vpr(); - # Generate Net for VPR - &gen_net_vpr(); - } - else { - die "Error: Invalid mode selected!\n"; - } - -} - -&main(); -exit(0); diff --git a/fpga_flow/scripts/pro_blif.pl b/fpga_flow/scripts/pro_blif.pl deleted file mode 100755 index 40203e136..000000000 --- a/fpga_flow/scripts/pro_blif.pl +++ /dev/null @@ -1,447 +0,0 @@ -#!usr/bin/perl -w -use strict; -#use Shell; -use FileHandle; -#Use the time -use Time::gmtime; - -#Get Date -my $mydate = gmctime(); -my ($char_per_line) = (80); - -my ($fname,$frpt,$finitial); -my $add_default_clk = "off"; -my $latch_token; -my ($remove_buffers) = (0); -my ($default_clk_name) = ("clk"); -my @buffers_to_remove; -my @buffers_to_rename; - -sub print_usage() -{ - print "Usage:\n"; - print " perl [-options]\n"; - print " Options:(Mandatory!)\n"; - print " -i \n"; - print " -o \n"; - print " Options: (Optional)\n"; - print " -remove_buffers\n"; - print " -add_default_clk\n"; - print " -initial_blif \n"; - print "\n"; - return 0; -} - -sub opts_read() -{ - if (-1 == $#ARGV) { - print "Error: No input argument!\n"; - &print_usage(); - exit(1); - } else { - for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++) { - if ("-i" eq $ARGV[$iargv]) { - $fname = $ARGV[$iargv+1]; - } elsif ("-o" eq $ARGV[$iargv]) { - $frpt = $ARGV[$iargv+1]; - } elsif ("-add_default_clk" eq $ARGV[$iargv]) { - $add_default_clk = "on"; - } elsif ("-initial_blif" eq $ARGV[$iargv]) { - $finitial = $ARGV[$iargv+1]; - } elsif ("-remove_buffers" eq $ARGV[$iargv]) { - $remove_buffers = 1; - } - } - } - return 0; -} - -# Print a line of blif netlist -sub fprint_blifln($ $ $) { - my ($FH, $tokens_ref, $char_per_line) = @_; - my ($cur_line_len) = (0); - my @tokens = @$tokens_ref; - - if ($char_per_line < 1) { - die "ERROR: (fprint_blifln) minimum acceptable number of chars in a line is 1!\n"; - } - # if the length of current line exceed the char_per_line, - # A continue line '\' is added and start a new line - for (my $itok = 0; $itok < ($#tokens+1); $itok++) { - if (!($tokens[$itok])) { - next; - } - # Contain any buffer names to be removed won't show up - if (1 == $remove_buffers) { - for (my $ibuf = 0; $ibuf < $#buffers_to_remove + 1; $ibuf++) { - if ($tokens[$itok] eq $buffers_to_remove[$ibuf]) { - $tokens[$itok] = $buffers_to_rename[$ibuf]; - } - } - } - $cur_line_len += length($tokens[$itok]); - if ($cur_line_len > $char_per_line) { - print $FH "\\"."\n"; - $cur_line_len = 0; - } - print $FH "$tokens[$itok] "; - $cur_line_len += length($tokens[$itok]); - } - print $FH "\n"; - -} - -sub read_blifline($ $) { - my ($FIN, $line_no_ptr) = @_; - my ($lines,$line) = ("",""); - - # Get one line - if (defined($line = <$FIN>)) { - chomp $line; - $lines = $line; - # Replace the < and > with [ and ], VPR does not support... - $lines =~ s//]/g; - while($lines =~ m/\\$/) { - $lines =~ s/\\$//; - if (defined($line = <$FIN>)) { - chomp $line; - $lines = $lines.$line; - $line =~ s//]/g; - } else { - return $lines; - } - } - return $lines; - } else { - return $lines; - } - -} - -sub process_blifmodel($ $) { - my ($FIN,$line_no_ptr) = @_; - my ($blackbox) = (0); - my ($lines); - my ($clk_num,$have_default_clk,$need_default_clk,$clk_recorded) = (0,0,0,0); - my @model_input_tokens; - my ($input_lines); - - while(!eof($FIN)) { - # Get one line - $lines = &read_blifline($FIN,$line_no_ptr); - # Check the tokens - if (!defined($lines)) { - next; - } - my @tokens = split('\s+',$lines); - # .end -> return - if (!defined($tokens[0])) { - next; - } - if (".end" eq $tokens[0]) { - return (\@model_input_tokens,$blackbox,$clk_num,$have_default_clk,$need_default_clk); - } elsif (".inputs" eq $tokens[0]) { - foreach my $temp(@tokens) { - if ($temp eq $default_clk_name) { - $have_default_clk = 1; - $clk_num++; - print "Found 1 clock: $temp in @tokens\n"; - last; - } - } - @model_input_tokens = @tokens; - } elsif (".blackbox" eq $tokens[0]) { - $blackbox = 1; - } elsif (".latch" eq $tokens[0]) { - # illegal definition exit - if ((3 != $#tokens)&&(5 != $#tokens)) { - die "ERROR: [LINE: $$line_no_ptr]illegal definition of latch!\n"; - } elsif (3 == $#tokens) { - # We need a default clock - if ($need_default_clk == 0) { - $need_default_clk = 1; - $clk_num++; - } - } elsif (5 == $#tokens) { - $clk_recorded = 0; - # Check if we have this clk names already - foreach my $tmp(@model_input_tokens) { - if ($tmp eq $tokens[4]) { - $clk_recorded = 1; - last; - } - } - # if have been recorded, we push it into the array - if (0 == $clk_recorded) { - $clk_num++; - push @model_input_tokens,$tokens[4]; - } - } - # Could be subckt or .names - } elsif (".names" eq $tokens[0]) { - if ((3 == ($#tokens + 1))&&(1 == $remove_buffers)) { - # We want to know is this a buffer??? - my $lut_lines = &read_blifline($FIN,$line_no_ptr); - my @lut_lines_tokens = split('\s+',$lut_lines); - if ((2 == ($#lut_lines_tokens + 1))&&("1" eq $lut_lines_tokens[0])&&("1" eq $lut_lines_tokens[1])) { - # push it to the array: buffers_to_remove - push @buffers_to_remove,$tokens[1]; - push @buffers_to_rename,$tokens[2]; - } - } - } - } - # Re-organise the input lines - #print @model_input_tokens; - $input_lines = ".inputs "; - foreach my $temp(@model_input_tokens) { - if (".inputs" ne $temp) { - $input_lines .= $temp." "; - } - } - $input_lines =~ s/\s+$//; - @model_input_tokens = split('\s+',$input_lines); - - return (\@model_input_tokens,$blackbox,$clk_num,$have_default_clk,$need_default_clk); -} - -sub scan_blif() -{ - my ($line,$lines); - my @tokens; - my ($clk_num,$have_default_clk,$need_default_clk,$clk_recorded); - my ($blackbox,$model_clk_num); - my @input_tokens; - my $input_lines; - my (@input_buffer); - my ($line_no) = (0); - - if (!defined($finitial)) { - $latch_token = "re clk"; - } else { - my $latch_token_found = 0; - my $count = 0; - my ($FIN0) = FileHandle->new; - if ($FIN0->open("< $finitial")) { - print "INFO: Parsing $finitial...\n"; - } else { - die "ERROR: Fail to open $finitial!\n"; - } - while((!$latch_token_found)&&(!eof($FIN0))){ - # Get one line - $lines = &read_blifline($FIN0); - if (!defined($lines)) { - next; - } - @tokens = split('\s+',$lines); - if(".latch" eq $tokens[0]) { - if($#tokens == 5){ - $latch_token = "$tokens[3] $tokens[4]"; - $latch_token_found = 1; - } - } - } - close($FIN0); - } - - # Pre-process the netlist - # Open src file first-scan to check if we have clock - my ($FIN) = FileHandle->new; - if ($FIN->open("< $fname")) { - print "INFO: Parsing $fname...\n"; - } else { - die "ERROR: Fail to open $fname!\n"; - } - while(!eof($FIN)) { - # Get one line - $lines = &read_blifline($FIN); - if (!defined($lines)) { - next; - } - @tokens = split('\s+',$lines); - if (!defined($tokens[0])) { - next; - } - # When we found .model we should check it. until .end comes. - # Check if it is a black box - if (".model" eq $tokens[0]) { - ($input_lines,$blackbox,$model_clk_num,$have_default_clk,$need_default_clk) = &process_blifmodel($FIN,\$line_no); - if (0 == $blackbox) { - @input_tokens = @$input_lines; - } - $clk_num += $model_clk_num; - } - } - close($FIN); - - # Add default clock - if ("on" eq $add_default_clk) { - print "INFO: $clk_num clock ports need to be added.\n"; - print "INFO: have_default_clk: $have_default_clk, need_default_clk: $need_default_clk\n"; - if ((0 == $have_default_clk)&&(1 == $need_default_clk)) { - push @input_tokens,$default_clk_name; - } - } - # Bypass some sensitive tokens - for(my $itok = 0; $itok < $#input_tokens+1; $itok++) { - if ("unconn" eq $input_tokens[$itok]) { - delete $input_tokens[$itok]; - } - } - # Print Buffer names to be removed - my $num_buffer_to_remove = $#buffers_to_remove + 1; - print "INFO: $num_buffer_to_remove buffer to be removed:\n"; - for(my $itok = 0; $itok < $#buffers_to_remove+1; $itok++) { - print $buffers_to_remove[$itok]." will be renamed to ".$buffers_to_rename[$itok]."\n"; - } - - - # Second scan - write - my ($inputs_written) = (0); - my ($FIN2) = FileHandle->new; - if ($FIN2->open("< $fname")) { - print "INFO: Parsing $fname the second time...\n"; - } else { - die "ERROR: Fail to open $fname!\n"; - } - # Open des file - my ($FOUT) = (FileHandle->new); - if (!($FOUT->open("> $frpt"))) { - die "Fail to create output file: $frpt!\n"; - } - while(!eof($FIN2)) { - $line = <$FIN2>; - chomp $line; - if ($line eq "") { - print $FOUT "\n"; - next; - } - # Replace the < and > with [ and ], VPR does not support... - $line =~ s//]/g; - # Check if this line start with ".latch", which we cares only - @tokens = split('\s+',$line); - if ((".inputs" eq $tokens[0])&&(0 == $inputs_written)) { - $lines = $line; - while($lines =~ m/\\$/) { - $line = <$FIN2>; - chomp $line; - # Replace the < and > with [ and ], VPR does not support... - $line =~ s//]/g; - $lines =~ s/\\$//; - $lines = $lines.$line; - } - #print @input_tokens."\n"; - &fprint_blifln($FOUT,\@input_tokens,$char_per_line); - $inputs_written = 1; - next; - } - if (".outputs" eq $tokens[0]) { - $lines = $line; - while($lines =~ m/\\$/) { - $line = <$FIN2>; - chomp $line; - # Replace the < and > with [ and ], VPR does not support... - $line =~ s//]/g; - $lines =~ s/\\$//; - $lines = $lines.$line; - } - my @output_tokens = split('\s',$lines); - for(my $itok = 0; $itok < $#output_tokens+1; $itok++) { - if ("unconn" eq $output_tokens[$itok]) { - delete $output_tokens[$itok]; - } - } - &fprint_blifln($FOUT,\@output_tokens,$char_per_line); - next; - - } - if (".latch" eq $tokens[0]) { - # check if we need complete it - if ($#tokens == 3) { - # Complete it - for (my $i=0; $i<3; $i++) { - print $FOUT "$tokens[$i] "; - } - print $FOUT "$latch_token $tokens[3]\n"; - } elsif ($#tokens == 5) { - # replace the clock name with clk - for (my $i=0; $i < ($#tokens+1); $i++) { - # if (4 == $i) { - # print $FOUT "clk "; - # } else { - print $FOUT "$tokens[$i] "; - # } - } - print $FOUT "\n"; - } else { - die "ERROR: [LINE: $line_no]illegal definition of latch!\n"; - } - next; - } elsif (".names" eq $tokens[0]) { - if ((3 == ($#tokens + 1))&&(1 == $remove_buffers)) { - # We want to know is this a buffer??? - my $lut_lines = &read_blifline($FIN2,\$line_no); - my @lut_lines_tokens = split('\s+',$lut_lines); - if ((2 == ($#lut_lines_tokens + 1))&&("1" eq $lut_lines_tokens[0])&&("1" eq $lut_lines_tokens[1])) { - # pass it. - next; - } else { - print $FOUT "$line\n"; - print $FOUT "$lut_lines\n"; - } - } else { - print $FOUT "$line\n"; - } - next; - } elsif ((".subckt" eq $tokens[0])&&(1 == $remove_buffers)) { - $lines = $line; - $lines =~ s/\s+$//; - while($lines =~ m/\\$/) { - $line = <$FIN2>; - chomp $line; - # Replace the < and > with [ and ], VPR does not support... - $line =~ s//]/g; - $lines =~ s/\\$//; - $lines = $lines.$line; - $lines =~ s/\s+$//; #ODIN II has some shit space after \ !!!!! - } - my @subckt_tokens = split('\s+',$lines); - for(my $itok = 0; $itok < $#subckt_tokens+1; $itok++) { - if (($itok > 1)&&("" ne $subckt_tokens[$itok])) { - my @port_tokens = split('=',$subckt_tokens[$itok]); - for (my $ibuf = 0; $ibuf < $#buffers_to_remove + 1; $ibuf++) { - if ($port_tokens[1] eq $buffers_to_remove[$ibuf]) { - $port_tokens[1] = $buffers_to_rename[$ibuf]; - } - } - $subckt_tokens[$itok] = join ('=',$port_tokens[0],$port_tokens[1]); - #print "See:".$subckt_tokens[$itok]."\n"; - } - } - &fprint_blifln($FOUT,\@subckt_tokens,$char_per_line); - - next; - } - - print $FOUT "$line\n"; - } - close($FIN2); - close($FOUT); - return 0; -} - -sub main() -{ - &opts_read(); - &scan_blif(); - return 0; -} - -&main(); -exit(0); diff --git a/fpga_flow/scripts/rewrite_path_in_file.pl b/fpga_flow/scripts/rewrite_path_in_file.pl deleted file mode 100644 index 25fe8173a..000000000 --- a/fpga_flow/scripts/rewrite_path_in_file.pl +++ /dev/null @@ -1,138 +0,0 @@ -#!usr/bin/perl -w -use strict; -use Cwd; -#use Shell; -use FileHandle; -#Use the time -use Time::gmtime; - -my $arch_file; -my $new_arch_file; -my $overwrite = "TRUE"; -my $keyword = "OPENFPGAPATHKEYWORD"; -my $default_keyword = "TRUE"; -my $change_to; -my $folder_top = "OpenFPGA"; - -sub print_usage() -{ - print "Usage:\n"; - print " perl [-options]\n"; - print " Options:(Mandatory!)\n"; - print " -i \n"; - print " Options:(Optional)\n"; - print " -o \n"; - print " -k \n"; - print "\n"; - return; -} - -sub opts_read() -{ - if ($#ARGV == -1){ - print "Error: Not enough input argument!\n"; - &print_usage(); - exit(1); - } else { - for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++){ - if ("-i" eq $ARGV[$iargv]){ - $arch_file = $ARGV[$iargv+1]; - $iargv++; - } elsif ("-o" eq $ARGV[$iargv]){ - $new_arch_file = $ARGV[$iargv+1]; - $overwrite = "FALSE"; - $iargv++; - } elsif ("-k" eq $ARGV[$iargv]){ - $keyword = $ARGV[$iargv+1]; - $change_to = $ARGV[$iargv+2]; - $default_keyword = "FALSE"; - $iargv++; - $iargv++; - } else { - die "WRONG ARGUMENT"; - } - } - } - return; -} - -sub rewriting_required_check($) -{ - my ($arch) = @_; - open(F, $arch); - my @lines=; - close F; - my $grep_result = grep ($keyword, @lines); - if($grep_result >= 1){ - print "Rewrite needed\n"; - return 1; - } else { - print "Rewrite NOT needed\n"; - return 0; - } -} - -sub save_original($) -{ - my ($template) = @_; - my $renamed_template = "$template".".bak"; - rename($template, $renamed_template); - - return $renamed_template; -} - -sub findPath(){ - my $path; - my $dir = cwd; - my @folders = split("/", $dir); - for(my $count = 0; $count < ($#folders -1); $count++){ - if($folders[$count] eq ""){ - } else { - $path = "$path"."/"."$folders[$count]"; - if($folders[$count] eq $folder_top){ - #print "$path\n"; - return $path; - } - } - } - die "ERROR: Script launched from the outside of the $folder_top folder!\n"; -} - -sub rewrite_file($ $) -{ - my ($arch, $template) = @_; - open(IN, '<'.$template); - open(OUT, '>'.$arch); - - if($default_keyword eq "TRUE"){ - my $myPath = &findPath(); - while(){ - $_ =~ s/$keyword/$myPath/g; - print OUT $_; - } - } else { - while(){ - $_ =~ s/$keyword/$change_to/g; - print OUT $_; - } - } - return; -} - -sub main() -{ - &opts_read(); - my $rewrite_needed = &rewriting_required_check($arch_file); - if($rewrite_needed == 1){ - if($overwrite eq "TRUE"){ - my $template_file = &save_original($arch_file); - &rewrite_file($arch_file, $template_file); - } else { - &rewrite_file($new_arch_file, $arch_file); - } - } - return; -} - -&main(); -exit(0); diff --git a/fpga_flow/scripts/run_fpga_spice.pl b/fpga_flow/scripts/run_fpga_spice.pl deleted file mode 100755 index 8fede08da..000000000 --- a/fpga_flow/scripts/run_fpga_spice.pl +++ /dev/null @@ -1,1699 +0,0 @@ -#!usr/bin/perl -w -# use the strict mode -use strict; -# Use the Shell enviornment -#use Shell; -# Use the time -use Time::gmtime; -# Use switch module -#use Switch; -use File::Path; -use Cwd; -use FileHandle; -# Multi-thread support -use threads; -use threads::shared; -# use ceil and floor numeric function -use POSIX; - -# Date -my $mydate = gmctime(); -# Current Path -my $cwd = getcwd(); - -# Global Variants -# input Option Hash -my %opt_h; -my $opt_ptr = \%opt_h; -# configurate file hash -my %conf_h; -my $conf_ptr = \%conf_h; -# reports hash -my %rpt_h; -my $rpt_ptr = \%rpt_h; -# tb_names hash -my %tb_names_h; -my $tb_names_ptr = \%tb_names_h; - -# Benchmarks -my @benchmark_names; -my %benchmarks; -my $benchmarks_ptr = \%benchmarks; -my %task_status; -my $task_status_ptr = \%task_status; - -# Testbench names -my @pb_mux_tb_names; -my @cb_mux_tb_names; -my @sb_mux_tb_names; -my @lut_tb_names; -my @hardlogic_tb_names; -my @grid_tb_names; -my @cb_tb_names; -my @sb_tb_names; -my @top_tb_name; - -# Configuration file keywords list -# Category for conf file. -# main category : 1st class -my @mctgy; -# sub category : 2nd class -my @sctgy; -# Initialize these categories -@mctgy = ("dir_path", - "task_conf", - "csv_tags", - ); -# refer to the keywords of dir_path -@{$sctgy[0]} = ("result_dir", - "shell_script_name", - "top_tb_dir_name", - "grid_tb_dir_name", - "lut_tb_dir_name", - "hardlogic_tb_dir_name", - "pb_mux_tb_dir_name", - "cb_mux_tb_dir_name", - "sb_mux_tb_dir_name", - "cb_tb_dir_name", - "sb_tb_dir_name", - "top_tb_prefix", - "pb_mux_tb_prefix", - "cb_mux_tb_prefix", - "sb_mux_tb_prefix", - "lut_tb_prefix", - "hardlogic_tb_prefix", - "grid_tb_prefix", - "cb_tb_prefix", - "sb_tb_prefix", - "top_tb_postfix", - "pb_mux_tb_postfix", - "cb_mux_tb_postfix", - "sb_mux_tb_postfix", - "lut_tb_postfix", - "hardlogic_tb_postfix", - "grid_tb_postfix", - "cb_tb_postfix", - "sb_tb_postfix", - ); -# refer to the keywords of flow_type -@{$sctgy[1]} = ("auto_check", - "num_pb_mux_tb", - "num_cb_mux_tb", - "num_sb_mux_tb", - "num_lut_mux_tb", - "num_hardlogic_tb", - "num_grid_mux_tb", - "num_top_tb", - "num_cb_tb", - "num_sb_tb", - ); -# refer to the keywords of csv_tags -@{$sctgy[2]} = ("top_tb_leakage_power_tags", - "top_tb_dynamic_power_tags", - "pb_mux_tb_leakage_power_tags", - "pb_mux_tb_dynamic_power_tags", - "cb_mux_tb_leakage_power_tags", - "cb_mux_tb_dynamic_power_tags", - "sb_mux_tb_leakage_power_tags", - "sb_mux_tb_dynamic_power_tags", - "lut_tb_leakage_power_tags", - "lut_tb_dynamic_power_tags", - "hardlogic_tb_leakage_power_tags", - "hardlogic_tb_dynamic_power_tags", - "grid_tb_leakage_power_tags", - "grid_tb_dynamic_power_tags", - "cb_tb_leakage_power_tags", - "cb_tb_dynamic_power_tags", - "sb_tb_leakage_power_tags", - "sb_tb_dynamic_power_tags", - ); - -# ----------Subrountines------------# -# Print TABs and strings -sub tab_print($ $ $) -{ - my ($FILE,$str,$num_tab) = @_; - my ($my_tab) = (" "); - - for (my $i = 0; $i < $num_tab; $i++) { - print $FILE "$my_tab"; - } - print $FILE "$str"; -} - -# Create paths if it does not exist. -sub generate_path($) -{ - my ($mypath) = @_; - if (!(-e "$mypath")) - { - mkpath "$mypath"; - print "Path($mypath) does not exist...Create it.\n"; - } - return 1; -} - -# Print the usage -sub print_usage() -{ - print "Usage:\n"; - print " run_fpga_spice.pl [-options ]\n"; - print " Mandatory options: \n"; - print " -conf : specify the basic configuration files for run_fpga_spice\n"; - print " -task : the configuration file contains benchmark file names\n"; - print " -rpt : CSV file consists of data\n"; - print " Other Options:\n"; - print " -monte_carlo : Specify Monte Carlo simulation is enabled in FPGA-SPICE, specify the type of reports. (Simple: only max/min/avg is reported; Detail: every MC case is reported.\n"; - print " -parse_pb_mux_tb: parse the results in pb_mux_testbench\n"; - print " -parse_cb_mux_tb: parse the results in cb_mux_testbench\n"; - print " -parse_sb_mux_tb: parse the results in sb_mux_testbench\n"; - print " -parse_lut_tb: parse the results in lut_testbench\n"; - print " -parse_hardlogic_tb: parse the results in hardlogic_testbench\n"; - print " -parse_grid_tb: parse the results in grid_testbench\n"; - print " -parse_cb_tb: parse the results in cb_testbench\n"; - print " -parse_sb_tb: parse the results in sb_testbench\n"; - print " -parse_top_tb: parse the results in top_testbench\n"; - print " -multi_thread : turn on multi-thread mode, specify the number of processors could be pushed\n"; - print " -sim_leakage_power_only : simulate leakage power only.\n"; - print " -parse_results_only : only parse HSPICE simulation results\n"; - print " -debug : debug mode\n"; - print " -help : print usage\n"; - exit(1); - return 1; -} - -sub spot_option($ $) { - my ($start,$target) = @_; - my ($arg_no,$flag) = (-1,"unfound"); - for (my $iarg = $start; $iarg < $#ARGV+1; $iarg++) { - if ($ARGV[$iarg] eq $target) { - if ("found" eq $flag) { - print "Error: Repeated Arguments!(IndexA: $arg_no,IndexB: $iarg)\n"; - &print_usage(); - } else { - $flag = "found"; - $arg_no = $iarg; - } - } - } - # return the arg_no if target is found - # or return -1 when target is missing - return $arg_no; -} - -# Specify in the input list, -# 1. Option Name -# 2. Whether Option with value. if yes, choose "on" -# 3. Whether Option is mandatory. If yes, choose "on" -sub read_opt_into_hash($ $ $) { - my ($opt_name,$opt_with_val,$mandatory) = @_; - # Check the -$opt_name - my ($opt_fact) = ("-".$opt_name); - my ($cur_arg) = (0); - my ($argfd) = (&spot_option($cur_arg,"$opt_fact")); - if ($opt_with_val eq "on") { - if (-1 != $argfd) { - if ($ARGV[$argfd+1] =~ m/^-/) { - print "The next argument cannot start with '-'!\n"; - print "it implies an option!\n"; - } else { - $opt_ptr->{"$opt_name\_val"} = $ARGV[$argfd+1]; - $opt_ptr->{"$opt_name"} = "on"; - } - } else { - $opt_ptr->{"$opt_name"} = "off"; - if ($mandatory eq "on") { - print "Mandatory option: $opt_fact is missing!\n"; - &print_usage(); - } - } - } else { - if (-1 != $argfd) { - $opt_ptr->{"$opt_name"} = "on"; - } else { - $opt_ptr->{"$opt_name"} = "off"; - if ($mandatory eq "on") { - print "Mandatory option: $opt_fact is missing!\n"; - &print_usage(); - } - } - } - return 1; -} - -# Read options -sub opts_read() { - # if no arguments detected, print the usage. - if (-1 == $#ARGV) { - print "Error : No input arguments!\n"; - &print_usage(); - exit(1); - } - # Read in the options - my ($cur_arg,$arg_found); - $cur_arg = 0; - print "Analyzing your options...\n"; - # Read the options with internal options - my $argfd; - # Check help fist - $argfd = &spot_option($cur_arg,"-help"); - if (-1 != $argfd) { - print "Help desk:\n"; - &print_usage(); - } - # Then Check the debug with highest priority - $argfd = &spot_option($cur_arg,"-debug"); - if (-1 != $argfd) { - $opt_ptr->{"debug"} = "on"; - } else { - $opt_ptr->{"debug"} = "off"; - } - # Check mandatory options - # Check the -conf - # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" - &read_opt_into_hash("conf","on","on"); - &read_opt_into_hash("task","on","on"); - &read_opt_into_hash("rpt","on","on"); - - # Optional options - &read_opt_into_hash("monte_carlo","on","off"); - &read_opt_into_hash("sim_leakage_power_only","off","off"); - &read_opt_into_hash("parse_results_only","off","off"); - &read_opt_into_hash("multi_thread","on","off"); - &read_opt_into_hash("parse_pb_mux_tb","off","off"); - &read_opt_into_hash("parse_cb_mux_tb","off","off"); - &read_opt_into_hash("parse_sb_mux_tb","off","off"); - &read_opt_into_hash("parse_lut_tb","off","off"); - &read_opt_into_hash("parse_hardlogic_tb","off","off"); - &read_opt_into_hash("parse_grid_tb","off","off"); - &read_opt_into_hash("parse_cb_tb","off","off"); - &read_opt_into_hash("parse_sb_tb","off","off"); - &read_opt_into_hash("parse_top_tb","off","off"); - - &print_opts(); - - return 1; -} - -# List the options -sub print_opts() { - print "List your options\n"; - - while(my ($key,$value) = each(%opt_h)) { - print "$key : $value\n"; - } - - return 1; -} - - -# Read each line and ignore the comments which starts with given arg -# return the valid information of line -sub read_line($ $) { - my ($line,$com) = @_; - my @chars; - if (defined($line)) { - @chars = split/$com/,$line; - if (!($line =~ m/[\w\d]/)) { - $chars[0] = undef; - } - if ($line =~ m/^\s*$com/) { - $chars[0] = undef; - } - } else { - $chars[0] = undef; - } - if (defined($chars[0])) { - $chars[0] =~ s/^(\s+)//g; - $chars[0] =~ s/(\s+)$//g; - } - return $chars[0]; -} - -# Check each keywords has been defined in configuration file -sub check_keywords_conf() { - for (my $imcg = 0; $imcg<$#mctgy+1; $imcg++) { - for (my $iscg = 0; $iscg<$#{$sctgy[$imcg]}+1; $iscg++) { - if (defined($conf_ptr->{$mctgy[$imcg]}->{$sctgy[$imcg]->[$iscg]}->{val})) { - if ("on" eq $opt_ptr->{debug}) { - print "Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) = "; - print "$conf_ptr->{$mctgy[$imcg]}->{$sctgy[$imcg]->[$iscg]}->{val}"; - print "\n"; - } - } else { - die "Error: Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) is missing!\n"; - } - } - } - return 1; -} - -# Read the configuration file -sub read_conf() { - # Read in these key words - my ($line,$post_line); - my @equation; - my $cur = "unknown"; - open (CONF, "< $opt_ptr->{conf_val}") or die "Fail to open $opt_ptr->{conf_val}!\n"; - print "Reading $opt_ptr->{conf_val}...\n"; - while(defined($line = )) { - chomp $line; - $post_line = &read_line($line,"#"); - if (defined($post_line)) { - if ($post_line =~ m/\[(\w+)\]/) { - $cur = $1; - } elsif ("unknown" eq $cur) { - die "Error: Unknown tags for this line!\n$post_line\n"; - } else { - $post_line =~ s/\s//g; - @equation = split /=/,$post_line; - if (!(defined($equation[1]))) { - $equation[1] = ""; - } - $conf_ptr->{$cur}->{$equation[0]}->{val} = $equation[1]; - } - } - } - # Check these key words - print "Read complete!\n"; - &check_keywords_conf(); - print "Checking these keywords..."; - print "Successfully\n"; - close(CONF); - return 1; -} - -sub read_benchmarks() { - # Read in file names - my ($line,$post_line,$cur); - $cur = 0; - open (FCONF,"< $opt_ptr->{task_val}") or die "Fail to open $opt_ptr->{task}!\n"; - print "Reading $opt_ptr->{task_val}...\n"; - while(defined($line = )) { - chomp $line; - $post_line = &read_line($line,"#"); - if (defined($post_line)) { - $post_line =~ s/\s+//g; - my @tokens = split(",",$post_line); - # first is the benchmark name, - #the second is the channel width, if applicable - if ($#tokens < 2) { - die "ERROR: invalid definition for a benchmark! At least include 3 tokens!\n"; - } - if ($tokens[0]) { - $benchmark_names[$cur] = $tokens[0]; - } else { - die "ERROR: invalid definition for benchmarks!\n"; - } - $benchmarks_ptr->{"$benchmark_names[$cur]"}->{spice_netlist_prefix} = $tokens[1]; - $benchmarks_ptr->{"$benchmark_names[$cur]"}->{spice_dir} = $tokens[2]; - $cur++; - } - } - print "Benchmarks(total $cur):\n"; - foreach my $temp(@benchmark_names) { - print "$temp\n"; - } - close(FCONF); - return 1; -} - -# Input program path is like "~/program_dir/program_name" -# We split it from the scalar -sub split_prog_path($) { - my ($prog_path) = @_; - my @path_elements = split /\//,$prog_path; - my ($prog_dir,$prog_name); - - $prog_name = $path_elements[$#path_elements]; - $prog_dir = $prog_path; - $prog_dir =~ s/$prog_name$//g; - - return ($prog_dir,$prog_name); -} - -# Detect and convert unit, NO Case Insentive. -sub process_unit($ $) -{ - my ($unit,$type) = @_; - my ($ret,$coeff) = (0,0); - - # Check type, can be - if ("time" eq $type) { - $unit =~ s/s$//i; - } elsif ("current" eq $type) { - $unit =~ s/A$//; # Special should not mix with "a" = 1e-18 - } elsif ("power" eq $type) { - $unit =~ s/W$//; - } elsif ("voltage" eq $type) { - $unit =~ s/V$//; - } elsif ("capacitance" eq $type) { - $unit =~ s/F$//; # Special should not mix with "f" = 1e-15 - } elsif ("empty" ne $type) { - die "Error: (process_unit)Unknown type!Should be \n"; - } - - # Accepte unit: m = 1e-3, u = 1e-6, n = 1e-9, p = 1e-12, f = 1e-15, a = 1e-18 - if ($unit =~ m/a$/) { - $unit =~ s/a$//; - $coeff = 1e-18; - } elsif ($unit =~ m/f$/) { - $unit =~ s/f$//; - $coeff = 1e-15; - } elsif ($unit =~ m/p$/) { - $unit =~ s/p$//; - $coeff = 1e-12; - } elsif ($unit =~ m/n$/) { - $unit =~ s/n$//; - $coeff = 1e-9; - } elsif ($unit =~ m/u$/) { - $unit =~ s/u$//; - $coeff = 1e-6; - } elsif ($unit =~ m/m$/) { - $unit =~ s/m$//; - $coeff = 1e-3; - } elsif ($unit =~ m/k$/) { - $unit =~ s/k$//; - $coeff = 1e3; - } elsif ($unit =~ m/Meg$/) { - $unit =~ s/Meg$//; - $coeff = 1e6; - } elsif ($unit =~ m/\d$/i) { - $coeff = 1; - } - # Chomp the possible point at the end - $unit =~ s/\.$//; - - # Quick check, there should be only numbers in remaining - if (!($unit =~ m/\d$/)) { - die "Error: (process_unit) Invalid number($unit)!\n"; - } - - return $ret = $unit*$coeff; -} - -# TODO: Check settings -sub check_fpga_spice() { - # Format the dir_path - # Format SPICE prefix -} - -# Initialize the status of all tasks -sub init_tasks_status() { - foreach my $bm(@benchmark_names) { - $task_status_ptr->{$bm}->{status} = "wait"; - $task_status_ptr->{$bm}->{thread_id} = undef; - } -} - -sub check_all_fpga_spice_tasks_done() { - foreach my $bm(@benchmark_names) { - if ("done" ne $task_status_ptr->{$bm}->{status}) { - return 0; - } - } - return 1; -} - -sub mark_all_fpga_spice_tasks_done() { - foreach my $bm(@benchmark_names) { - $task_status_ptr->{$bm}->{status} = "done"; - } - return 1; -} - -sub print_tasks_status() { - my ($num_jobs_running, $num_jobs_to_run, $num_jobs_finish, $num_jobs) = (0, 0, 0, 0); - - foreach my $benchmark(@benchmark_names) { - # Count the number of jobs - $num_jobs++; - # Count to do jobs - if ("wait" eq $task_status_ptr->{$benchmark}->{status}) { - $num_jobs_to_run++; - next; - } - if ("running" eq $task_status_ptr->{$benchmark}->{status}) { - # Count running jobs - $num_jobs_running++; - next; - } - # Count finished jobs - if ("done" eq $task_status_ptr->{$benchmark}->{status}) { - $num_jobs_finish++; - next; - } - } - if ($num_jobs == ($num_jobs_running + $num_jobs_finish + $num_jobs_to_run)) { - print "Jobs Progress: (Finish rate = ".sprintf("%.2f",100*$num_jobs_finish/$num_jobs) ."%)\n"; - print "Thead utilization rate = ".sprintf("%.2f",100*$num_jobs_running/$opt_ptr->{multi_thread_val})."%\n"; - print "Total No. of Jobs: $num_jobs.\n"; - print "No. of Running Jobs: $num_jobs_running.\n"; - print "No. of Finished Jobs: $num_jobs_finish.\n"; - print "No. of To Run Jobs: $num_jobs_to_run.\n"; - } else { - print "Internal problem: num_jobs($num_jobs) != num_jobs_running($num_jobs_running)\n"; - print " +num_jobs_finish($num_jobs_finish)\n"; - die " +num_jobs_to_run($num_jobs_to_run)\n"; - } - return; -} - -sub format_dir_path($) { - my ($dir_path) = @_; - my ($formatted_dir_path) = ($dir_path); - - if (!($formatted_dir_path =~ m/\/$/)) { - $formatted_dir_path = $formatted_dir_path."/"; - } - - return $formatted_dir_path; -} - -sub gen_fpga_spice_netlists_path($ $ $) { - my ($spice_dir, $sp_prefix, $sp_postfix) = @_; - my ($formatted_spice_dir) = &format_dir_path($spice_dir); - - my ($sp_path) = ($formatted_spice_dir.$sp_prefix.$sp_postfix); - - return ($sp_path); -} - -sub determine_fpga_grid_nx_ny($) { - my ($grid_no) = @_; - - my ($nx, $ny) = (ceil(sqrt($grid_no)), ceil(sqrt($grid_no))); - - return ($nx, $ny); -} - -sub gen_fpga_tb_spice_netlist_path($ $ $ $ $ $) { - my ($spice_dir, $sp_prefix, $tb_prefix, $ix, $iy, $sp_postfix) = @_; - my ($formatted_spice_dir) = &format_dir_path($spice_dir); - - my ($sp_path) = ($formatted_spice_dir.$sp_prefix.$tb_prefix.$ix."_".$iy.$sp_postfix); - - return ($sp_path); -} - -sub gen_fpga_spice_measure_results_path($ $ $) { - my ($spice_dir, $sp_prefix, $sp_postfix) = @_; - my ($formatted_spice_dir) = &format_dir_path($spice_dir); - my ($formatted_result_dir) = &format_dir_path($conf_ptr->{dir_path}->{result_dir}->{val}); - - my ($mt_path) = ($formatted_spice_dir.$formatted_result_dir.$sp_prefix.$sp_postfix); - - $mt_path =~ s/\.sp/.mt0/; - - return ($mt_path); -} - -sub gen_fpga_tb_spice_measure_results_path($ $ $ $ $) { - my ($spice_dir, $sp_prefix, $tb_prefix, $no, $sp_postfix) = @_; - my ($formatted_spice_dir) = &format_dir_path($spice_dir); - my ($formatted_result_dir) = &format_dir_path($conf_ptr->{dir_path}->{result_dir}->{val}); - - my ($mt_path) = ($formatted_spice_dir.$formatted_result_dir.$sp_prefix.$tb_prefix.$no.$sp_postfix); - - $mt_path =~ s/\.sp/.mt0/; - - return ($mt_path); -} - -sub convert_fpga_tb_names_to_measure_names($) { - my ($tb_sp_path, $spice_dir) = @_; - my ($mt_path); - - my ($formatted_spice_dir) = &format_dir_path($spice_dir); - my ($formatted_result_dir) = &format_dir_path($conf_ptr->{dir_path}->{result_dir}->{val}); - - # Split tb_sp_path - my @sp_parts = split('/', $tb_sp_path); - my ($mt_name) = ($sp_parts[$#sp_parts]); - $mt_name =~ s/\.sp$/\.mt0/g; - - ($mt_path) = ($formatted_spice_dir.$formatted_result_dir.$mt_name); - - return $mt_path; -} - -sub remove_fpga_spice_results($) { - my ($spice_dir) = @_; - my ($formatted_spice_dir) = &format_dir_path($spice_dir); - my ($formatted_result_dir) = &format_dir_path($conf_ptr->{dir_path}->{result_dir}->{val}); - - my ($result_dir_path) = ($formatted_spice_dir.$formatted_result_dir); - - #rmtree($result_dir_path,1,1); - `rm -rf $result_dir_path/`; - print "INFO: Simulation Results($result_dir_path) are removed...\n"; - - #`rm -rf $spice_dir/`; - #print "INFO: Spice Directory($spice_dir) is removed...\n"; - - return; -} - -sub check_one_spice_lis_error($) { - my ($lis_path) = @_; - my ($line, $line_no, $warn_no, $err_no) = (undef,0,0,0); - my ($LISFH) = FileHandle->new; - - print "INFO: Checking LIS file($lis_path)...\n"; - - if (!(-e $lis_path)) { - die "ERROR: Fail to find SPICE lis file($lis_path)!\n"; - } - if ($LISFH->open("< $lis_path")) { - while(defined($line = <$LISFH>)) { - chomp $line; - $line_no++; - if ($line =~ m/error/i) { - $err_no++; - print "ERROR($err_no),LIS FILE[LINE$line_no]: ".$line."\n"; - } - if ($line =~ m/warning/i) { - $warn_no++; - print "WARNING($warn_no),LIS FILE[LINE$line_no]: ".$line."\n"; - } - } - } else { - die "ERROR: fail to open $lis_path!\n"; - } - # Close the lis file - close($LISFH); - # Print HSPICE ERROR and Warning Stats - print "HSPICE Sim. reports $err_no errors and $warn_no warnings.\n"; - if ($err_no > 0) { - die "ERROR: Terminate due to errors in HSPICE Sim. reports.\n"; - } - - return; -} - -sub check_one_fpga_spice_task_lis($ $ $) { - my ($benchmark, $spice_netlist_prefix, $spice_dir) = @_; - my ($formatted_spice_dir) = &format_dir_path($spice_dir); - my ($shell_script_path) = $formatted_spice_dir.$conf_ptr->{dir_path}->{shell_script_name}->{val}; - my ($itb, $lis_file_path); - - if ("on" eq $opt_ptr->{parse_top_tb}) { - my ($top_lis_path) = &gen_fpga_spice_measure_results_path($formatted_spice_dir, $spice_netlist_prefix,$conf_ptr->{dir_path}->{top_tb_postfix}->{val}); - $top_lis_path =~ s/\.mt0/.lis/; - &check_one_spice_lis_error($top_lis_path); - } - - if ("on" eq $opt_ptr->{parse_pb_mux_tb}) { - # generate measure results paths - @pb_mux_tb_names = split (',', $tb_names_ptr->{$benchmark}->{pb_mux_tb_names}); - foreach my $tb_sp_filename (@pb_mux_tb_names) { - $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path =~ s/\.mt0/.lis/; - &check_one_spice_lis_error($lis_file_path); - } - } - - if ("on" eq $opt_ptr->{parse_cb_mux_tb}) { - # generate measure results paths - @cb_mux_tb_names = split (',', $tb_names_ptr->{$benchmark}->{cb_mux_tb_names}); - foreach my $tb_sp_filename (@cb_mux_tb_names) { - $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path =~ s/\.mt0/.lis/; - &check_one_spice_lis_error($lis_file_path); - } - } - - if ("on" eq $opt_ptr->{parse_sb_mux_tb}) { - # generate measure results paths - @sb_mux_tb_names = split (',', $tb_names_ptr->{$benchmark}->{sb_mux_tb_names}); - foreach my $tb_sp_filename (@sb_mux_tb_names) { - $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path =~ s/\.mt0/.lis/; - &check_one_spice_lis_error($lis_file_path); - } - } - - if ("on" eq $opt_ptr->{parse_lut_tb}) { - # generate measure results paths - @lut_tb_names = split (',', $tb_names_ptr->{$benchmark}->{lut_tb_names}); - foreach my $tb_sp_filename (@lut_tb_names) { - $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path =~ s/\.mt0/.lis/; - &check_one_spice_lis_error($lis_file_path); - } - } - - if (0 == $conf_ptr->{task_conf}->{num_hardlogic_tb}->{val}) { - } elsif ("on" eq $opt_ptr->{parse_hardlogic_tb}) { - # generate measure results paths - @hardlogic_tb_names = split (',', $tb_names_ptr->{$benchmark}->{hardlogic_tb_names}); - foreach my $tb_sp_filename (@hardlogic_tb_names) { - $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path =~ s/\.mt0/.lis/; - &check_one_spice_lis_error($lis_file_path); - } - } - - if ("on" eq $opt_ptr->{parse_grid_tb}) { - # generate measure results paths - @grid_tb_names = split (',', $tb_names_ptr->{$benchmark}->{grid_tb_names}); - foreach my $tb_sp_filename (@grid_tb_names) { - $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path =~ s/\.mt0/.lis/; - &check_one_spice_lis_error($lis_file_path); - } - } - - if ("on" eq $opt_ptr->{parse_cb_tb}) { - # generate measure results paths - @cb_tb_names = split (',', $tb_names_ptr->{$benchmark}->{cb_tb_names}); - foreach my $tb_sp_filename (@cb_tb_names) { - $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path =~ s/\.mt0/.lis/; - &check_one_spice_lis_error($lis_file_path); - } - } - - if ("on" eq $opt_ptr->{parse_sb_tb}) { - # generate measure results paths - @sb_tb_names = split (',', $tb_names_ptr->{$benchmark}->{sb_tb_names}); - foreach my $tb_sp_filename (@sb_tb_names) { - $lis_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path =~ s/\.mt0/.lis/; - &check_one_spice_lis_error($lis_file_path); - } - } - - return; -} - -sub init_one_fpga_spice_task_one_tb_results($ $ $ $) { - my ($benchmark, $tbname_tag, $tb_leakage_tags, $tb_dynamic_tags) = @_; - my (@leakage_tags) = split('\|', $tb_leakage_tags); - my (@dynamic_tags) = split('\|', $tb_dynamic_tags); - my ($temp); - - # Check if there is any conflict to reserved words - foreach my $tag(@leakage_tags) { - if (("peak_mem_used" eq $tag)||("total_elapsed_time" eq $tag)) { - die "ERROR: $tbname_tag leakage_power_tags has a conflict word($tag)!\n"; - } - } - if ("off" eq $opt_ptr->{sim_leakage_power_only}) { - foreach my $tag(@dynamic_tags) { - if (("peak_mem_used" eq $tag)||("total_elapsed_time" eq $tag)) { - die "ERROR: $tbname_tag dynamic_power_tags has a conflict word($tag)!\n"; - } - } - } - - $rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used} = 0; - $rpt_ptr->{$benchmark}->{$tbname_tag}->{total_elapsed_time} = 0; - foreach my $tag(@leakage_tags) { - $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag} = 0; - } - if ("off" eq $opt_ptr->{sim_leakage_power_only}) { - foreach my $tag(@dynamic_tags) { - $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag} = 0; - } - } - - return; -} - -sub parse_one_fpga_spice_task_one_regular_tb_results($ $ $ $ $ $) { - my ($benchmark, $tbname_tag, $tb_lispath, $tb_mtpath, $tb_leakage_tags, $tb_dynamic_tags) = @_; - my (@leakage_tags) = split('\|', $tb_leakage_tags); - my (@dynamic_tags) = split('\|', $tb_dynamic_tags); - my ($line, $found_tran_analysis); - my ($LISFH) = FileHandle->new; - my ($temp); - - # Check if there is any conflict to reserved words - foreach my $tag(@leakage_tags) { - if (("peak_mem_used" eq $tag)||("total_elapsed_time" eq $tag)) { - die "ERROR: $tbname_tag leakage_power_tags has a conflict word($tag)!\n"; - } - } - if ("off" eq $opt_ptr->{sim_leakage_power_only}) { - foreach my $tag(@dynamic_tags) { - if (("peak_mem_used" eq $tag)||("total_elapsed_time" eq $tag)) { - die "ERROR: $tbname_tag dynamic_power_tags has a conflict word($tag)!\n"; - } - } - } - - if (!(-e $tb_lispath)) { - die "ERROR: Fail to find SPICE lis file($tb_lispath)!\n"; - } - if ($LISFH->open("< $tb_lispath")) { - $found_tran_analysis = 0; - while(defined($line = <$LISFH>)) { - chomp $line; - if ((0 == $found_tran_analysis)&&($line =~ m/transient\s+analysis/)) { - $found_tran_analysis = 1; - } - if (0 == $found_tran_analysis) { - next; - } - # Special: get peak memory used and total elapsed time - if ($line =~ m/peak\s+memory\s+used\s+([\d.]+)\s+megabytes/i) { - $temp = $1; - if ((!defined($rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used})) - ||($rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used} < $temp)) { - $rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used} = $temp; - } - next; # We find a match, ignore the rest - } - # Special: get peak memory used and total elapsed time - if ($line =~ m/total\s+elapsed\s+time\s+([\d.]+)\s+seconds/i) { - $temp = $1; - $rpt_ptr->{$benchmark}->{$tbname_tag}->{total_elapsed_time} += $temp; - next; # We find a match, ignore the rest - } - # For leakage power - foreach my $tag(@leakage_tags) { - if ($line =~ m/$tag\s*=\s*([\d.\w\-\+]+)/i) { - $temp = $1; - $temp = &process_unit($temp, "empty"); - $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{avg} += $temp; - next; # We find a match, ignore the rest - } - } - # Bypass dynamic tags if leakage_only is enabled - if ("on" eq $opt_ptr->{sim_leakage_power_only}) { - next; - } - # For dynamic power - foreach my $tag(@dynamic_tags) { - if ($line =~ m/$tag\s*=\s*([\d.\w\-\+]+)/i) { - $temp = $1; - $temp = &process_unit($temp, "empty"); - $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{avg} += $temp; - next; # We find a match, ignore the rest - } - } - } - } else { - die "ERROR: fail to open $tb_lispath!\n"; - } - # Close file - close($LISFH); - - return; -} - - -sub parse_one_fpga_spice_task_one_mc_tb_results($ $ $ $ $ $ $) { - my ($benchmark, $tbname_tag, $tb_lispath, $tb_mtpath, $tb_leakage_tags, $tb_dynamic_tags) = @_; - my (@leakage_tags) = split('\|', $tb_leakage_tags); - my (@dynamic_tags) = split('\|', $tb_dynamic_tags); - my ($line, $found_tran_analysis); - my ($LISFH) = FileHandle->new; - my ($temp, $mc_cnt) = ("", 0); - - # Check if there is any conflict to reserved words - foreach my $tag(@leakage_tags) { - if (("peak_mem_used" eq $tag)||("total_elapsed_time" eq $tag)) { - die "ERROR: $tbname_tag leakage_power_tags has a conflict word($tag)!\n"; - } - # for a clear start - $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{mc_cnt} = 0; - } - if ("off" eq $opt_ptr->{sim_leakage_power_only}) { - foreach my $tag(@dynamic_tags) { - if (("peak_mem_used" eq $tag)||("total_elapsed_time" eq $tag) - ||("mc_min" eq $tag)||("mc_max" eq $tag)||("mc_avg" eq $tag) - ||("mc_total" eq $tag)||("mc_cnt" eq $tag)) { - die "ERROR: $tbname_tag dynamic_power_tags has a conflict word($tag)!\n"; - } - # for a clear start - $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{mc_cnt} = 0; - } - } - - if (!(-e $tb_lispath)) { - die "ERROR: Fail to find SPICE lis file($tb_lispath)!\n"; - } - if ($LISFH->open("< $tb_lispath")) { - $found_tran_analysis = 0; - while(defined($line = <$LISFH>)) { - chomp $line; - if ((0 == $found_tran_analysis)&&($line =~ m/transient\s+analysis/)) { - $found_tran_analysis = 1; - } - if (0 == $found_tran_analysis) { - next; - } - # Special: get peak memory used and total elapsed time - if ($line =~ m/peak\s+memory\s+used\s+([\d.]+)\s+megabytes/i) { - $temp = $1; - if ((!defined($rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used})) - ||($rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used} < $temp)) { - $rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used} = $temp; - } - next; # We find a match, ignore the rest - } - # Special: get peak memory used and total elapsed time - if ($line =~ m/total\s+elapsed\s+time\s+([\d.]+)\s+seconds/i) { - $temp = $1; - $rpt_ptr->{$benchmark}->{$tbname_tag}->{total_elapsed_time} += $temp; - next; # We find a match, ignore the rest - } - # For leakage power - foreach my $tag(@leakage_tags) { - if ($line =~ m/$tag\s*=\s*([\d.\w\-\+]+)/i) { - $temp = $1; - $temp = &process_unit($temp, "empty"); - $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{mc_cnt} += 1; - $mc_cnt = $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{mc_cnt}; - if (defined($rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{"mc".$mc_cnt})) { - $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{"mc".$mc_cnt} += $temp; - } else { - $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{"mc".$mc_cnt} = $temp; - } - next; # We find a match, ignore the rest - } - } - # Bypass dynamic tags if leakage_only is enabled - if ("on" eq $opt_ptr->{sim_leakage_power_only}) { - next; - } - # For dynamic power - foreach my $tag(@dynamic_tags) { - if ($line =~ m/$tag\s*=\s*([\d.\w\-\+]+)/i) { - $temp = $1; - $temp = &process_unit($temp, "empty"); - $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{mc_cnt} += 1; - $mc_cnt = $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{mc_cnt}; - if (defined($rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{"mc".$mc_cnt})) { - $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{"mc".$mc_cnt} += $temp; - } else { - $rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{"mc".$mc_cnt} = $temp; - } - next; # We find a match, ignore the rest - } - } - } - } else { - die "ERROR: fail to open $tb_lispath!\n"; - } - # Close file - close($LISFH); - - return; -} - -sub parse_one_fpga_spice_task_one_tb_results($ $ $ $ $ $) { - my ($benchmark, $tbname_tag, $tb_lispath, $tb_mtpath, $tb_leakage_tags, $tb_dynamic_tags) = @_; - - if ("on" eq $opt_ptr->{monte_carlo}) { - &parse_one_fpga_spice_task_one_mc_tb_results($benchmark, $tbname_tag, $tb_lispath, $tb_mtpath, - $tb_leakage_tags, $tb_dynamic_tags); - } else { - &parse_one_fpga_spice_task_one_regular_tb_results($benchmark, $tbname_tag, $tb_lispath, $tb_mtpath, - $tb_leakage_tags, $tb_dynamic_tags); - } - - return; -} - -sub count_num_tb_one_folder($) { - my ($dir) = @_; - my (@files) = <$dir/*.sp>; - my ($count) = $#files + 1; - return $count; -} - -sub get_tb_file_names($) { - my ($tb_dir) = @_; - my @ret_file_names; - my ($dh); - - # Search all the sp files matching the name - opendir($dh, $tb_dir) || die "Fail to open directory of $tb_dir\n"; - @ret_file_names = grep(/\.sp$/, readdir($dh)); - print "Getting testbench file names for $tb_dir ...\n"; - closedir($dh); - - # join the names together - my ($ret) = join(",", @ret_file_names); - - return $ret; -} - -sub auto_check_tb_num($ $ $) { - my ($benchmark, $spice_netlist_prefix, $spice_dir) = @_; - my ($formatted_spice_dir) = &format_dir_path($spice_dir); - my ($tb_dir); - - print "Autocheck Results:\n"; - - # count pb_mux_tb - $conf_ptr->{task_conf}->{num_pb_mux_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{pb_mux_tb_dir_name}->{val}); - print "INFO: No. of CLB MUXes testbenches = $conf_ptr->{task_conf}->{num_pb_mux_tb}->{val}\n"; - - # count sb_mux_tb - $conf_ptr->{task_conf}->{num_sb_mux_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{sb_mux_tb_dir_name}->{val}); - print "INFO: No. of Switch Box MUXes testbenches = $conf_ptr->{task_conf}->{num_sb_mux_tb}->{val}\n"; - - # count cb_mux_tb - $conf_ptr->{task_conf}->{num_cb_mux_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{cb_mux_tb_dir_name}->{val}); - print "INFO: No. of Connection Box MUXes testbenches = $conf_ptr->{task_conf}->{num_cb_mux_tb}->{val}\n"; - - # count lut_tb - $conf_ptr->{task_conf}->{num_lut_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{lut_tb_dir_name}->{val}); - print "INFO: No. of LUT testbenches = $conf_ptr->{task_conf}->{num_lut_tb}->{val}\n"; - - # count hardlogic_tb - $conf_ptr->{task_conf}->{num_hardlogic_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{hardlogic_tb_dir_name}->{val}); - print "INFO: No. of FF testbenches = $conf_ptr->{task_conf}->{num_hardlogic_tb}->{val}\n"; - - # count grid_tb - $conf_ptr->{task_conf}->{num_grid_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{grid_tb_dir_name}->{val}); - print "INFO: No. of Grid testbenches = $conf_ptr->{task_conf}->{num_grid_tb}->{val}\n"; - - # count cb_tb - $conf_ptr->{task_conf}->{num_cb_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{cb_tb_dir_name}->{val}); - print "INFO: No. of CB testbenches = $conf_ptr->{task_conf}->{num_cb_tb}->{val}\n"; - - # count sb_tb - $conf_ptr->{task_conf}->{num_sb_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{sb_tb_dir_name}->{val}); - print "INFO: No. of SB testbenches = $conf_ptr->{task_conf}->{num_sb_tb}->{val}\n"; - - # count top_tb - $conf_ptr->{task_conf}->{num_top_tb}->{val} = &count_num_tb_one_folder($formatted_spice_dir.$conf_ptr->{dir_path}->{top_tb_dir_name}->{val}); - print "INFO: No. of Top-level testbench = $conf_ptr->{task_conf}->{num_top_tb}->{val}\n"; - - my ($toptb_sp_path) = &gen_fpga_spice_netlists_path($formatted_spice_dir.$conf_ptr->{dir_path}->{top_tb_dir_name}->{val}, $spice_netlist_prefix, $conf_ptr->{dir_path}->{top_tb_postfix}->{val}); - - if (("on" eq $opt_ptr->{parse_top_tb})&&(!(-e $toptb_sp_path))) { - die "ERROR: File($toptb_sp_path) does not exist!"; - } - - if ("on" eq $opt_ptr->{parse_pb_mux_tb}) { - $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{pb_mux_tb_dir_name}->{val}; - $tb_names_ptr->{$benchmark}->{pb_mux_tb_names} = &get_tb_file_names($tb_dir); - } - - if ("on" eq $opt_ptr->{parse_cb_mux_tb}) { - # Search all the sp files matching the name - $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{cb_mux_tb_dir_name}->{val}; - $tb_names_ptr->{$benchmark}->{cb_mux_tb_names} = &get_tb_file_names($tb_dir); - } - - if ("on" eq $opt_ptr->{parse_sb_mux_tb}) { - $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{sb_mux_tb_dir_name}->{val}; - $tb_names_ptr->{$benchmark}->{sb_mux_tb_names} = &get_tb_file_names($tb_dir); - } - - if ("on" eq $opt_ptr->{parse_lut_tb}) { - # Search all the sp files matching the name - $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{lut_tb_dir_name}->{val}; - $tb_names_ptr->{$benchmark}->{lut_tb_names} = &get_tb_file_names($tb_dir); - } - - # Special, if there is no hardlogic, this is comb circuit, we don't collect the information - if (0 == $conf_ptr->{task_conf}->{num_hardlogic_tb}->{val}) { - print "INFO: None DFF testbenches detected... This may caused by a combinational circuit!\n"; - } elsif ("on" eq $opt_ptr->{parse_hardlogic_tb}) { - # Search all the sp files matching the name - $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{hardlogic_tb_dir_name}->{val}; - $tb_names_ptr->{$benchmark}->{hardlogic_tb_names} = &get_tb_file_names($tb_dir); - } - - if ("on" eq $opt_ptr->{parse_grid_tb}) { - # Search all the sp files matching the name - $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{grid_tb_dir_name}->{val}; - $tb_names_ptr->{$benchmark}->{grid_tb_names} = &get_tb_file_names($tb_dir); - } - - if ("on" eq $opt_ptr->{parse_cb_tb}) { - # Search all the sp files matching the name - $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{cb_tb_dir_name}->{val}; - $tb_names_ptr->{$benchmark}->{cb_tb_names} = &get_tb_file_names($tb_dir); - } - - if ("on" eq $opt_ptr->{parse_sb_tb}) { - # Search all the sp files matching the name - $tb_dir = $formatted_spice_dir.$conf_ptr->{dir_path}->{sb_tb_dir_name}->{val}; - $tb_names_ptr->{$benchmark}->{sb_tb_names} = &get_tb_file_names($tb_dir); - } - - - return; -} - -sub parse_one_fpga_spice_task_results($ $ $) { - my ($benchmark, $spice_netlist_prefix, $spice_dir) = @_; - my ($formatted_spice_dir) = &format_dir_path($spice_dir); - my ($shell_script_path) = $formatted_spice_dir.$conf_ptr->{dir_path}->{shell_script_name}->{val}; - my ($itb, $mt_file_path, $lis_file_path); - - &auto_check_tb_num($benchmark, $spice_netlist_prefix, $spice_dir); - - if ("on" eq $opt_ptr->{parse_top_tb}) { - my ($top_mt_path) = &gen_fpga_spice_measure_results_path($spice_dir, $spice_netlist_prefix,$conf_ptr->{dir_path}->{top_tb_postfix}->{val}); - my ($top_lis_path) = ($top_mt_path); - $top_lis_path =~ s/\.mt0$/.lis/; - &parse_one_fpga_spice_task_one_tb_results($benchmark,"top_tb", $top_lis_path, $top_mt_path, $conf_ptr->{csv_tags}->{top_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{top_tb_dynamic_power_tags}->{val}); - } - - if ("on" eq $opt_ptr->{parse_pb_mux_tb}) { - # generate measure results paths - @pb_mux_tb_names = split (',', $tb_names_ptr->{$benchmark}->{pb_mux_tb_names}); - foreach my $tb_sp_filename (@pb_mux_tb_names) { - $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path = $mt_file_path; - $lis_file_path =~ s/\.mt0$/.lis/; - &parse_one_fpga_spice_task_one_tb_results($benchmark,"pb_mux_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{pb_mux_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{pb_mux_tb_dynamic_power_tags}->{val}); - } - } - - if ("on" eq $opt_ptr->{parse_cb_mux_tb}) { - # generate measure results paths - @cb_mux_tb_names = split (',', $tb_names_ptr->{$benchmark}->{cb_mux_tb_names}); - foreach my $tb_sp_filename (@cb_mux_tb_names) { - $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path = $mt_file_path; - $lis_file_path =~ s/\.mt0$/.lis/; - &parse_one_fpga_spice_task_one_tb_results($benchmark,"cb_mux_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{cb_mux_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{cb_mux_tb_dynamic_power_tags}->{val}); - } - } - - if ("on" eq $opt_ptr->{parse_sb_mux_tb}) { - # generate measure results paths - @sb_mux_tb_names = split (',', $tb_names_ptr->{$benchmark}->{sb_mux_tb_names}); - foreach my $tb_sp_filename (@sb_mux_tb_names) { - $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path = $mt_file_path; - $lis_file_path =~ s/\.mt0$/.lis/; - &parse_one_fpga_spice_task_one_tb_results($benchmark,"sb_mux_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{sb_mux_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{sb_mux_tb_dynamic_power_tags}->{val}); - } - } - - if ("on" eq $opt_ptr->{parse_lut_tb}) { - # generate measure results paths - @lut_tb_names = split (',', $tb_names_ptr->{$benchmark}->{lut_tb_names}); - foreach my $tb_sp_filename (@lut_tb_names) { - $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path = $mt_file_path; - $lis_file_path =~ s/\.mt0$/.lis/; - &parse_one_fpga_spice_task_one_tb_results($benchmark,"lut_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{lut_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{lut_tb_dynamic_power_tags}->{val}); - } - } - - if (0 == $conf_ptr->{task_conf}->{num_hardlogic_tb}->{val}) { - &init_one_fpga_spice_task_one_tb_results($benchmark,"hardlogic_tb",$conf_ptr->{csv_tags}->{hardlogic_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{hardlogic_tb_dynamic_power_tags}->{val}); - } elsif ("on" eq $opt_ptr->{parse_hardlogic_tb}) { - # generate measure results paths - @hardlogic_tb_names = split (',', $tb_names_ptr->{$benchmark}->{hardlogic_tb_names}); - foreach my $tb_sp_filename (@hardlogic_tb_names) { - $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path = $mt_file_path; - $lis_file_path =~ s/\.mt0$/.lis/; - &parse_one_fpga_spice_task_one_tb_results($benchmark,"hardlogic_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{hardlogic_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{hardlogic_tb_dynamic_power_tags}->{val}); - } - } - - if ("on" eq $opt_ptr->{parse_grid_tb}) { - # generate measure results paths - @grid_tb_names = split (',', $tb_names_ptr->{$benchmark}->{grid_tb_names}); - foreach my $tb_sp_filename (@grid_tb_names) { - $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path = $mt_file_path; - $lis_file_path =~ s/\.mt0$/.lis/; - &parse_one_fpga_spice_task_one_tb_results($benchmark,"grid_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{grid_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{grid_tb_dynamic_power_tags}->{val}); - } - } - - if ("on" eq $opt_ptr->{parse_cb_tb}) { - # generate measure results paths - @cb_tb_names = split (',', $tb_names_ptr->{$benchmark}->{cb_tb_names}); - foreach my $tb_sp_filename (@cb_tb_names) { - $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path = $mt_file_path; - $lis_file_path =~ s/\.mt0$/.lis/; - &parse_one_fpga_spice_task_one_tb_results($benchmark,"cb_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{cb_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{cb_tb_dynamic_power_tags}->{val}); - } - } - - if ("on" eq $opt_ptr->{parse_sb_tb}) { - # generate measure results paths - @sb_tb_names = split (',', $tb_names_ptr->{$benchmark}->{sb_tb_names}); - foreach my $tb_sp_filename (@sb_tb_names) { - $mt_file_path = &convert_fpga_tb_names_to_measure_names($tb_sp_filename, $spice_dir); - $lis_file_path = $mt_file_path; - $lis_file_path =~ s/\.mt0$/.lis/; - &parse_one_fpga_spice_task_one_tb_results($benchmark,"sb_tb", $lis_file_path, $mt_file_path, $conf_ptr->{csv_tags}->{sb_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{sb_tb_dynamic_power_tags}->{val}); - } - } - - return; -} - -# Run a fpga_spice_task -sub run_one_fpga_spice_task($ $ $) { - my ($benchmark, $spice_netlist_prefix, $spice_dir) = @_; - my ($formatted_spice_dir) = &format_dir_path($spice_dir); - my ($shell_script_path) = $formatted_spice_dir.$conf_ptr->{dir_path}->{shell_script_name}->{val}; - my ($itb, $ix, $iy, $dh, $tb_dir); - - # change to the spice_dir - chdir $spice_dir; - # Check all the SPICE netlists and shell scripts exist - - &auto_check_tb_num($benchmark, $spice_netlist_prefix, $spice_dir); - - if (!(-e $shell_script_path)) { - die "ERROR: File($shell_script_path) does not exist!"; - } - - # Call the shell script - print "INFO: Running shell script ($shell_script_path)...\n"; - `csh -cx 'source $shell_script_path'` - or die "ERROR: fail in executing $shell_script_path!\n"; - - # return to current dir - chdir $cwd; - - &check_one_fpga_spice_task_lis($benchmark, $spice_netlist_prefix, $spice_dir); - print "INFO: Check LIS file finished.\n"; - - return; -} - -sub parse_all_tasks_results() { - print "Parsing all the results...\n"; - foreach my $benchmark(@benchmark_names) { - if ("done" eq $task_status_ptr->{$benchmark}->{status}) { - print "Parsing simulation results for benchmark($benchmark)...\n"; - &parse_one_fpga_spice_task_results($benchmark,$benchmarks_ptr->{$benchmark}->{spice_netlist_prefix},$benchmarks_ptr->{$benchmark}->{spice_dir}); - } else { - die "ERROR: found unfinished tasks when try to parse results!\n"; - } - # Remove results to avoid storage overflow - #&remove_fpga_spice_results($benchmarks_ptr->{$benchmark}->{spice_dir}); - } -} - -# Multi-thread Running FPGA SPICE tasks -sub multi_thread_run_fpga_spice_tasks($) { - my ($num_threads) = @_; - - # Evaluate include threads ok - if (!(eval 'use threads; 1')) { - die "ERROR: cannot use threads package in Perl! Please check the installation of package...\n"; - } - # Lauch threads up to the limited number of threads number - if ($num_threads < 2) { - $num_threads = 2; - } - my ($num_thread_running) = (0); - - # Iterate until all the tasks has been assigned, finished - while (1 != &check_all_fpga_spice_tasks_done()) { - foreach my $benchmark(@benchmark_names) { - # Bypass finished job - if ("done" eq $task_status_ptr->{$benchmark}->{status}) { - next; - } - # Check running job - if ("running" eq $task_status_ptr->{$benchmark}->{status}) { - my ($thr_id) = ($task_status_ptr->{$benchmark}->{thread_id}); - if (!($thr_id)) { - die "INTERNAL ERROR: invalid thread_id for task: $benchmark!\n"; - } - # Check if there is any error - if ($thr_id->error()) { - die "ERROR: Task: $benchmark, Thread(ID:$thr_id) exit abnormally!\n"; - } - if ($thr_id->is_running()) { - $task_status_ptr->{$benchmark}->{status} = "running"; - } - if ($thr_id->is_joinable()) { - $num_thread_running--; - $thr_id->join(); # Join the thread results - # Update task status - $task_status_ptr->{$benchmark}->{status} = "done"; - print "INFO: task: $benchmark finished!\n"; - &print_tasks_status(); - } - next; - } - # If we reach the thread number limit, we have to wait... - if (($num_thread_running == $num_threads) - ||($num_thread_running > $num_threads)) { - next; - } - # Start a new thread for a waiting task - if ("wait" eq $task_status_ptr->{$benchmark}->{status}) { - # We try to start a new thread since there are still threads available - my ($thr_new) = (threads->create(\&run_one_fpga_spice_task, $benchmark,$benchmarks_ptr->{$benchmark}->{spice_netlist_prefix},$benchmarks_ptr->{$benchmark}->{spice_dir})); - if ($thr_new) { - print "INFO: a new thread for task (benchmark: $benchmark) is lauched!\n"; - # Update status - $task_status_ptr->{$benchmark}->{status} = "running"; - $task_status_ptr->{$benchmark}->{thread_id} = $thr_new; - $num_thread_running++; - &print_tasks_status(); - } else { - # Fail to create a new thread, wait... - print "INFO: fail to lauch a new thread for task (benchmark: $benchmark)!\n"; - } - } - } - } - &print_tasks_status(); - - # Parse_results - &parse_all_tasks_results(); -} - -# Single-thread mode Running FPGA SPICE tasks -sub single_thread_run_fpga_spice_tasks() { - # Iterate until all the tasks has been assigned, finished - while (1 != &check_all_fpga_spice_tasks_done()) { - foreach my $benchmark(@benchmark_names) { - # Bypass finished job - if ("done" eq $task_status_ptr->{$benchmark}->{status}) { - next; - } - &run_one_fpga_spice_task($benchmark,$benchmarks_ptr->{$benchmark}->{spice_netlist_prefix},$benchmarks_ptr->{$benchmark}->{spice_dir}); - &parse_one_fpga_spice_task_results($benchmark,$benchmarks_ptr->{$benchmark}->{spice_netlist_prefix},$benchmarks_ptr->{$benchmark}->{spice_dir}); - $task_status_ptr->{$benchmark}->{status} = "done"; - # Remove results to avoid storage overflow - &remove_fpga_spice_results($benchmarks_ptr->{$benchmark}->{spice_dir}); - } - } - # Parse_results - #&parse_all_tasks_results(); - return; -} - -# Plan to run tasks -sub plan_run_tasks() { - &init_tasks_status(); - - if (("on" eq $opt_ptr->{multi_thread}) - &&(1 < $opt_ptr->{multi_thread_val}) - &&(1 < ($#benchmark_names + 1))) { - &multi_thread_run_fpga_spice_tasks($opt_ptr->{multi_thread_val}); - } else { - if ("on" eq $opt_ptr->{multi_thread}) { - print "INFO: multi_thread is selected but only 1 processor can be used or 1 benchmark to run...\n"; - print "INFO: switch to single thread mode.\n"; - } - &single_thread_run_fpga_spice_tasks(); - } -} - -sub gen_csv_rpt_one_tb_one_case($ $ $ $ $) { - my ($RPTFH, $tbname_tag, $tb_leakage_tags, $tb_dynamic_tags, $case_tag) = @_; - my (@leakage_tags) = split('\|', $tb_leakage_tags); - my (@dynamic_tags) = split('\|', $tb_dynamic_tags); - - # Print Title line - print $RPTFH "Benchmark,SimElapseTime,SimPeakMemUsed,"; - foreach my $tag(@leakage_tags) { - print $RPTFH "$tag,"; - } - if ("off" eq $opt_ptr->{sim_leakage_power_only}) { - foreach my $tag(@dynamic_tags) { - print $RPTFH "$tag,"; - } - } - print $RPTFH "\n"; - foreach my $benchmark(@benchmark_names) { - print $RPTFH "$benchmark,"; - print $RPTFH "$rpt_ptr->{$benchmark}->{$tbname_tag}->{total_elapsed_time},"; - print $RPTFH "$rpt_ptr->{$benchmark}->{$tbname_tag}->{peak_mem_used},"; - foreach my $tag(@leakage_tags) { - print $RPTFH "$rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{$case_tag},"; - } - if ("off" eq $opt_ptr->{sim_leakage_power_only}) { - foreach my $tag(@dynamic_tags) { - print $RPTFH "$rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}->{$case_tag},"; - } - } - print $RPTFH "\n"; - } - return; -} - -sub gen_csv_rpt_one_case($ $) { - my ($RPTFH, $case_tag) = @_; - - print $RPTFH "Monte Carlo case tag of the results: $case_tag\n"; - - if ("on" eq $opt_ptr->{parse_pb_mux_tb}) { - print $RPTFH "***** pb_mux_tb Results Table *****\n"; - &gen_csv_rpt_one_tb_one_case($RPTFH, "pb_mux_tb", $conf_ptr->{csv_tags}->{pb_mux_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{pb_mux_tb_dynamic_power_tags}->{val}, $case_tag); - print $RPTFH "\n"; - } - - if ("on" eq $opt_ptr->{parse_cb_mux_tb}) { - print $RPTFH "***** cb_mux_tb Results Table *****\n"; - &gen_csv_rpt_one_tb_one_case($RPTFH, "cb_mux_tb", $conf_ptr->{csv_tags}->{cb_mux_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{cb_mux_tb_dynamic_power_tags}->{val}, $case_tag); - print $RPTFH "\n"; - } - - if ("on" eq $opt_ptr->{parse_sb_mux_tb}) { - print $RPTFH "***** sb_mux_tb Results Table *****\n"; - &gen_csv_rpt_one_tb_one_case($RPTFH, "sb_mux_tb", $conf_ptr->{csv_tags}->{sb_mux_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{sb_mux_tb_dynamic_power_tags}->{val}, $case_tag); - print $RPTFH "\n"; - } - - if ("on" eq $opt_ptr->{parse_lut_tb}) { - print $RPTFH "***** lut_tb Results Table *****\n"; - &gen_csv_rpt_one_tb_one_case($RPTFH, "lut_tb", $conf_ptr->{csv_tags}->{lut_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{lut_tb_dynamic_power_tags}->{val}, $case_tag); - print $RPTFH "\n"; - } - - if ("on" eq $opt_ptr->{parse_hardlogic_tb}) { - print $RPTFH "***** hardlogic_tb Results Table *****\n"; - &gen_csv_rpt_one_tb_one_case($RPTFH, "hardlogic_tb", $conf_ptr->{csv_tags}->{hardlogic_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{hardlogic_tb_dynamic_power_tags}->{val}, $case_tag); - print $RPTFH "\n"; - } - - if ("on" eq $opt_ptr->{parse_grid_tb}) { - print $RPTFH "***** grid_tb Results Table *****\n"; - &gen_csv_rpt_one_tb_one_case($RPTFH, "grid_tb", $conf_ptr->{csv_tags}->{grid_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{grid_tb_dynamic_power_tags}->{val}, $case_tag); - print $RPTFH "\n"; - } - - if ("on" eq $opt_ptr->{parse_cb_tb}) { - print $RPTFH "***** cb_tb Results Table *****\n"; - &gen_csv_rpt_one_tb_one_case($RPTFH, "cb_tb", $conf_ptr->{csv_tags}->{cb_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{cb_tb_dynamic_power_tags}->{val}, $case_tag); - print $RPTFH "\n"; - } - - if ("on" eq $opt_ptr->{parse_sb_tb}) { - print $RPTFH "***** sb_tb Results Table *****\n"; - &gen_csv_rpt_one_tb_one_case($RPTFH, "sb_tb", $conf_ptr->{csv_tags}->{sb_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{sb_tb_dynamic_power_tags}->{val}, $case_tag); - print $RPTFH "\n"; - } - - if ("on" eq $opt_ptr->{parse_top_tb}) { - print $RPTFH "***** top_tb Results Table *****\n"; - &gen_csv_rpt_one_tb_one_case($RPTFH, "top_tb", $conf_ptr->{csv_tags}->{top_tb_leakage_power_tags}->{val}, $conf_ptr->{csv_tags}->{top_tb_dynamic_power_tags}->{val}, $case_tag); - print $RPTFH "\n"; - } - - return; -} - -sub process_mc_data_one_tag($) { - my ($cur_mc_hash_ref) = @_; - - $cur_mc_hash_ref->{mc_total} = 0; - $cur_mc_hash_ref->{mc_avg} = "na"; - $cur_mc_hash_ref->{mc_max} = "na"; - $cur_mc_hash_ref->{mc_min} = "na"; - for (my $i = 1; - $i < $cur_mc_hash_ref->{mc_cnt} + 1; - $i++) { - $cur_mc_hash_ref->{mc_total} += $cur_mc_hash_ref->{"mc".$i}; - # Update max - if (("na" eq $cur_mc_hash_ref->{mc_max}) - ||($cur_mc_hash_ref->{mc_max} < $cur_mc_hash_ref->{"mc".$i})) { - $cur_mc_hash_ref->{mc_max} = $cur_mc_hash_ref->{"mc".$i}; - } - # Update min - if (("na" eq $cur_mc_hash_ref->{mc_min}) - ||($cur_mc_hash_ref->{mc_min} > $cur_mc_hash_ref->{"mc".$i})) { - $cur_mc_hash_ref->{mc_min} = $cur_mc_hash_ref->{"mc".$i}; - } - } - # Get average - if ( 0 < $cur_mc_hash_ref->{mc_cnt}) { - $cur_mc_hash_ref->{mc_avg} = $cur_mc_hash_ref->{mc_total} / $cur_mc_hash_ref->{mc_cnt}; - } - - return $cur_mc_hash_ref->{mc_cnt}; -} - -# Count the number of Monte Carlo simulations, -# and calculate the average, max and min -sub process_mc_data_one_tb($ $ $) { - my ($tbname_tag, $tb_leakage_tags, $tb_dynamic_tags) = @_; - my (@leakage_tags) = split('\|', $tb_leakage_tags); - my (@dynamic_tags) = split('\|', $tb_dynamic_tags); - my ($mc_cnt, $mc_cnt_temp) = (0, 0); - - # Check each benchmark - foreach my $benchmark(@benchmark_names) { - foreach my $tag(@leakage_tags) { - $mc_cnt_temp = &process_mc_data_one_tag($rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}); - if (0 == $mc_cnt_temp) { - print "Warning: zero results found in Monte Carlo simulations for $tag!\n"; - } - if (0 == $mc_cnt) { - $mc_cnt = $mc_cnt_temp; - } elsif ($mc_cnt != $mc_cnt_temp) { - print "Warning: Inconsistent Monte Carlo Counter for (Benchmark:$benchmark; Testbench: $tbname_tag, Tag:$tag)\n"; - } - } - - # Only do the next part when sim_leakage is disabled - if ("on" eq $opt_ptr->{sim_leakage_power_only}) { - next; - } - foreach my $tag(@dynamic_tags) { - $mc_cnt_temp = &process_mc_data_one_tag($rpt_ptr->{$benchmark}->{$tbname_tag}->{$tag}); - if (0 == $mc_cnt) { - $mc_cnt = $mc_cnt_temp; - } elsif ($mc_cnt != $mc_cnt_temp) { - print "Warning: Inconsistent Monte Carlo Counter for (Benchmark:$benchmark; Testbench: $tbname_tag, Tag:$tag)\n"; - } - } - } - return $mc_cnt; -} - - -sub process_mc_results() { - my ($mc_cnt) = (0); - - if ("on" eq $opt_ptr->{parse_pb_mux_tb}) { - $mc_cnt = - &process_mc_data_one_tb("pb_mux_tb", - $conf_ptr->{csv_tags}->{pb_mux_tb_leakage_power_tags}->{val}, - $conf_ptr->{csv_tags}->{pb_mux_tb_dynamic_power_tags}->{val}); - } - - if ("on" eq $opt_ptr->{parse_cb_mux_tb}) { - $mc_cnt = - &process_mc_data_one_tb("cb_mux_tb", - $conf_ptr->{csv_tags}->{cb_mux_tb_leakage_power_tags}->{val}, - $conf_ptr->{csv_tags}->{cb_mux_tb_dynamic_power_tags}->{val}); - } - - if ("on" eq $opt_ptr->{parse_sb_mux_tb}) { - $mc_cnt = - &process_mc_data_one_tb("sb_mux_tb", - $conf_ptr->{csv_tags}->{sb_mux_tb_leakage_power_tags}->{val}, - $conf_ptr->{csv_tags}->{sb_mux_tb_dynamic_power_tags}->{val}); - } - - if ("on" eq $opt_ptr->{parse_lut_tb}) { - $mc_cnt = - &process_mc_data_one_tb("lut_tb", - $conf_ptr->{csv_tags}->{lut_tb_leakage_power_tags}->{val}, - $conf_ptr->{csv_tags}->{lut_tb_dynamic_power_tags}->{val}); - } - - if ("on" eq $opt_ptr->{parse_hardlogic_tb}) { - $mc_cnt = - &process_mc_data_one_tb("hardlogic_tb", - $conf_ptr->{csv_tags}->{hardlogic_tb_leakage_power_tags}->{val}, - $conf_ptr->{csv_tags}->{hardlogic_tb_dynamic_power_tags}->{val}); - } - - if ("on" eq $opt_ptr->{parse_grid_tb}) { - $mc_cnt = - &process_mc_data_one_tb("grid_tb", - $conf_ptr->{csv_tags}->{grid_tb_leakage_power_tags}->{val}, - $conf_ptr->{csv_tags}->{grid_tb_dynamic_power_tags}->{val}); - } - - if ("on" eq $opt_ptr->{parse_cb_tb}) { - $mc_cnt = - &process_mc_data_one_tb("cb_tb", - $conf_ptr->{csv_tags}->{cb_tb_leakage_power_tags}->{val}, - $conf_ptr->{csv_tags}->{cb_tb_dynamic_power_tags}->{val}); - } - - if ("on" eq $opt_ptr->{parse_sb_tb}) { - $mc_cnt = - &process_mc_data_one_tb("sb_tb", - $conf_ptr->{csv_tags}->{sb_tb_leakage_power_tags}->{val}, - $conf_ptr->{csv_tags}->{sb_tb_dynamic_power_tags}->{val}); - } - - if ("on" eq $opt_ptr->{parse_top_tb}) { - $mc_cnt = - &process_mc_data_one_tb("top_tb", - $conf_ptr->{csv_tags}->{top_tb_leakage_power_tags}->{val}, - $conf_ptr->{csv_tags}->{top_tb_dynamic_power_tags}->{val}); - } - - return $mc_cnt; -} - -sub gen_csv_rpt($) { - my ($rpt_file) = @_; - my ($RPTFH) = FileHandle->new; - my ($mc_num) = (0); - - my ($rpt_dir_path, $rpt_filename) = &split_prog_path($rpt_file); - &generate_path($rpt_dir_path); - - if ($RPTFH->open("> $rpt_file")) { - print "INFO: print CVS report($rpt_file)...\n"; - } else { - die "ERROR: fail to create $rpt_file!\n"; - } - - if ("on" eq $opt_ptr->{monte_carlo}) { - # Preprocess the data - $mc_num = &process_mc_results(); - # Output starts - if ("simple_rpt" eq $opt_ptr->{monte_carlo_val}) { - &gen_csv_rpt_one_case($RPTFH, "mc_avg"); - &gen_csv_rpt_one_case($RPTFH, "mc_max"); - &gen_csv_rpt_one_case($RPTFH, "mc_min"); - } else { # Output full report - print $RPTFH "Number of Monte Carlo simulations: $mc_num\n\n"; - &gen_csv_rpt_one_case($RPTFH, "mc_avg"); - &gen_csv_rpt_one_case($RPTFH, "mc_max"); - &gen_csv_rpt_one_case($RPTFH, "mc_min"); - for (my $i = 1; $i < $mc_num + 1; $i++) { - &gen_csv_rpt_one_case($RPTFH, "mc".$i); - } - } - } else { - &gen_csv_rpt_one_case($RPTFH, "avg"); - } - - close($RPTFH); - return; -} - -# Main Program -sub main() { - &opts_read(); - &read_conf(); - &read_benchmarks(); - &check_fpga_spice(); - # Auto check the number tbs - if ("on" eq $opt_ptr->{parse_results_only}) { - &mark_all_fpga_spice_tasks_done(); - &parse_all_tasks_results(); - } else { - &plan_run_tasks(); - } - &gen_csv_rpt($opt_ptr->{rpt_val}); -} -&main(); -exit(0); diff --git a/fpga_flow/scripts/run_multi.pl b/fpga_flow/scripts/run_multi.pl deleted file mode 100755 index 193a449d2..000000000 --- a/fpga_flow/scripts/run_multi.pl +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/perl -w -use strict; -#use Shell; - -my $i; - -sub main{ - for ($i=3;$i<7;$i++) { - my $pid = fork(); - if (0 == $pid) { - my $n = $i + 1; - return `perl fpga_flow.pl -conf ./configs/K$i\_N$n\_22nm_new.conf -benchmark ./benchmarks/circuits.txt -rpt K$i\_N$n\_22nm_new_full.csv -N $n -K $i`; - } - } - #for ($i=3;$i<7;$i++) { - # my $pid = fork(); - # if (0 == $pid) { - # my $n = $i + 1; - # return `perl fpga_flow.pl -conf ./configs/K$i\_N$n\_22nm.conf -benchmark ./benchmarks/circuits.txt -rpt K$i\_N$n\_22nm.csv -N $n -K $i`; - # } - #} - #for ($i=1;$i<7;$i++) { - # my $pid = fork(); - # if (0 == $pid) { - # return `perl fpga_flow.pl -conf ./configs/K3M2_N$i\_22nm.conf -benchmark ./benchmarks/circuits.txt -rpt K3M2_N$i\_22nm.csv -N $i -K 3`; - # } - #} - #for ($i=1;$i<11;$i++) { - # my $pid = fork(); - # if (0 == $pid) { - # return `perl fpga_flow.pl -conf ./configs/K6_N$i\_22nm.conf -benchmark ./benchmarks/circuits.txt -rpt K6_N$i\_22nm.csv -N $i -K 6`; - # } - #} - #wait(-1); -} - -&main(); - diff --git a/fpga_flow/scripts/tags b/fpga_flow/scripts/tags deleted file mode 100644 index 105871474..000000000 --- a/fpga_flow/scripts/tags +++ /dev/null @@ -1,81 +0,0 @@ -!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ -!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ -!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/ -!_TAG_PROGRAM_NAME Exuberant Ctags // -!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ -!_TAG_PROGRAM_VERSION 5.8 // -black_box_blif fpga_flow.pl /^sub black_box_blif($ $) $/;" s -check_all_flows_all_benchmarks_done fpga_flow.pl /^sub check_all_flows_all_benchmarks_done() {$/;" s -check_blif_type fpga_flow.pl /^sub check_blif_type($) $/;" s -check_flow_all_benchmarks_done fpga_flow.pl /^sub check_flow_all_benchmarks_done($) {$/;" s -check_keywords_conf fpga_flow.pl /^sub check_keywords_conf()$/;" s -check_opts fpga_flow.pl /^sub check_opts() {$/;" s -extract_aapack_stats fpga_flow.pl /^sub extract_aapack_stats($ $ $ $ $) $/;" s -extract_min_chan_width_vpr_stats fpga_flow.pl /^sub extract_min_chan_width_vpr_stats($ $ $ $ $ $) $/;" s -extract_mpack1_stats fpga_flow.pl /^sub extract_mpack1_stats($ $ $) $/;" s -extract_mpack2_stats fpga_flow.pl /^sub extract_mpack2_stats($ $ $) $/;" s -extract_vpr_power_esti fpga_flow.pl /^sub extract_vpr_power_esti($ $ $ $) $/;" s -extract_vpr_stats fpga_flow.pl /^sub extract_vpr_stats($ $ $ $) $/;" s -gen_csv_rpt fpga_flow.pl /^sub gen_csv_rpt($) $/;" s -gen_csv_rpt_mpack1_flow fpga_flow.pl /^sub gen_csv_rpt_mpack1_flow($ $) $/;" s -gen_csv_rpt_mpack2_flow fpga_flow.pl /^sub gen_csv_rpt_mpack2_flow($ $) $/;" s -gen_csv_rpt_standard_flow fpga_flow.pl /^sub gen_csv_rpt_standard_flow($ $) $/;" s -gen_csv_rpt_vtr_flow fpga_flow.pl /^sub gen_csv_rpt_vtr_flow($ $) $/;" s -gen_odin2_config_xml fpga_flow.pl /^sub gen_odin2_config_xml($ $ $ $ $ $) {$/;" s -generate_path fpga_flow.pl /^sub generate_path($)$/;" s -init_fpga_spice_task fpga_flow.pl /^sub init_fpga_spice_task($) {$/;" s -init_selected_flows fpga_flow.pl /^sub init_selected_flows() {$/;" s -main fpga_flow.pl /^sub main()$/;" s -mark_flows_benchmarks fpga_flow.pl /^sub mark_flows_benchmarks() {$/;" s -mark_selected_flows fpga_flow.pl /^sub mark_selected_flows()$/;" s -multitask_run_flows fpga_flow.pl /^sub multitask_run_flows() {$/;" s -multithread_run_flows fpga_flow.pl /^sub multithread_run_flows($) {$/;" s -opts_read fpga_flow.pl /^sub opts_read()$/;" s -output_fpga_spice_task fpga_flow.pl /^sub output_fpga_spice_task($ $ $ $) {$/;" s -parse_benchmark_selected_flow fpga_flow.pl /^sub parse_benchmark_selected_flow($ $) {$/;" s -parse_flows_benchmarks_results fpga_flow.pl /^sub parse_flows_benchmarks_results() {$/;" s -parse_mpack1_flow_results fpga_flow.pl /^sub parse_mpack1_flow_results($ $) {$/;" s -parse_mpack2_flow_results fpga_flow.pl /^sub parse_mpack2_flow_results($ $ $) $/;" s -parse_standard_flow_results fpga_flow.pl /^sub parse_standard_flow_results($ $ $ $) $/;" s -parse_vtr_flow_results fpga_flow.pl /^sub parse_vtr_flow_results($ $ $) {$/;" s -plan_run_flows fpga_flow.pl /^sub plan_run_flows() {$/;" s -print_jobs_status fpga_flow.pl /^sub print_jobs_status() {$/;" s -print_opts fpga_flow.pl /^sub print_opts()$/;" s -print_usage fpga_flow.pl /^sub print_usage()$/;" s -read_benchmarks fpga_flow.pl /^sub read_benchmarks()$/;" s -read_conf fpga_flow.pl /^sub read_conf()$/;" s -read_line fpga_flow.pl /^sub read_line($ $)$/;" s -read_opt_into_hash fpga_flow.pl /^sub read_opt_into_hash($ $ $)$/;" s -remove_designs fpga_flow.pl /^sub remove_designs()$/;" s -run_aapack fpga_flow.pl /^sub run_aapack($ $ $ $) $/;" s -run_abc_bb_fpgamap fpga_flow.pl /^sub run_abc_bb_fpgamap($ $ $) {$/;" s -run_abc_fpgamap fpga_flow.pl /^sub run_abc_fpgamap($ $ $) $/;" s -run_abc_libmap fpga_flow.pl /^sub run_abc_libmap($ $ $)$/;" s -run_abc_mccl_fpgamap fpga_flow.pl /^sub run_abc_mccl_fpgamap($ $ $) $/;" s -run_abc_mig_mccl_fpgamap fpga_flow.pl /^sub run_abc_mig_mccl_fpgamap($ $ $) $/;" s -run_ace fpga_flow.pl /^sub run_ace($ $ $ $) {$/;" s -run_ace_in_flow fpga_flow.pl /^sub run_ace_in_flow($ $ $ $ $ $ $) {$/;" s -run_benchmark_selected_flow fpga_flow.pl /^sub run_benchmark_selected_flow($ $ $) $/;" s -run_cirkit_mig_mccl_map fpga_flow.pl /^sub run_cirkit_mig_mccl_map($ $ $) {$/;" s -run_flows fpga_flow.pl /^sub run_flows() {$/;" s -run_m2net_m2net fpga_flow.pl /^sub run_m2net_m2net($ $ $ $ $) $/;" s -run_m2net_pack_arch fpga_flow.pl /^sub run_m2net_pack_arch($ $ $ $ $ $) $/;" s -run_mccl_flow fpga_flow.pl /^sub run_mccl_flow($ $ $ $ $) $/;" s -run_mig_mccl_flow fpga_flow.pl /^sub run_mig_mccl_flow($ $ $ $) {$/;" s -run_mpack1_flow fpga_flow.pl /^sub run_mpack1_flow($ $ $) $/;" s -run_mpack1_vpr fpga_flow.pl /^sub run_mpack1_vpr($ $ $ $ $ $ $) $/;" s -run_mpack1p5 fpga_flow.pl /^sub run_mpack1p5($ $ $ $ $) $/;" s -run_mpack2 fpga_flow.pl /^sub run_mpack2($ $ $ $ $ $ $) $/;" s -run_mpack2_flow fpga_flow.pl /^sub run_mpack2_flow($ $ $ $) $/;" s -run_mpack2_vpr fpga_flow.pl /^sub run_mpack2_vpr($ $ $ $ $ $ $) $/;" s -run_odin2 fpga_flow.pl /^sub run_odin2($ $ $) {$/;" s -run_pro_blif fpga_flow.pl /^sub run_pro_blif($ $) {$/;" s -run_standard_flow fpga_flow.pl /^sub run_standard_flow($ $ $ $ $) $/;" s -run_std_vpr fpga_flow.pl /^sub run_std_vpr($ $ $ $ $ $ $ $ $) $/;" s -run_vpr_in_flow fpga_flow.pl /^sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) {$/;" s -run_vpr_route fpga_flow.pl /^sub run_vpr_route($ $ $ $ $ $ $ $ $) $/;" s -run_vtr_flow fpga_flow.pl /^sub run_vtr_flow($ $ $ $) {$/;" s -run_vtr_mccl_flow fpga_flow.pl /^sub run_vtr_mccl_flow($ $ $ $) {$/;" s -split_prog_path fpga_flow.pl /^sub split_prog_path($)$/;" s -spot_option fpga_flow.pl /^sub spot_option($ $)$/;" s -tab_print fpga_flow.pl /^sub tab_print($ $ $)$/;" s diff --git a/fpga_flow/tech/.gitignore b/fpga_flow/tech/.gitignore deleted file mode 100644 index 4c839bb4c..000000000 --- a/fpga_flow/tech/.gitignore +++ /dev/null @@ -1 +0,0 @@ -winbond90nm diff --git a/fpga_flow/tech/PTM_130nm/130nm.pm b/fpga_flow/tech/PTM_130nm/130nm.pm deleted file mode 100644 index bcb5d7a86..000000000 --- a/fpga_flow/tech/PTM_130nm/130nm.pm +++ /dev/null @@ -1,145 +0,0 @@ -* Beta Version released on 2/22/06 - -* PTM 130nm NMOS - -.model nmos nmos level = 54 - -+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 -+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 -+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 -+permod = 1 acnqsmod= 0 trnqsmod= 0 - -+tnom = 27 toxe = 2.25e-9 toxp = 1.6e-9 toxm = 2.25e-9 -+dtox = 0.65e-9 epsrox = 3.9 wint = 5e-009 lint = 10.5e-009 -+ll = 0 wl = 0 lln = 1 wln = 1 -+lw = 0 ww = 0 lwn = 1 wwn = 1 -+lwl = 0 wwl = 0 xpart = 0 toxref = 2.25e-9 -+xl = -60e-9 -+vth0 = 0.3782 k1 = 0.4 k2 = 0.01 k3 = 0 -+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 -+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 -+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.2e-010 -+dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 3.92e-008 -+ngate = 2e+020 ndep = 1.54e+018 nsd = 2e+020 phin = 0 -+cdsc = 0.0002 cdscb = 0 cdscd = 0 cit = 0 -+voff = -0.13 nfactor = 1.5 eta0 = 0.0092 etab = 0 -+vfb = -0.55 u0 = 0.05928 ua = 6e-010 ub = 1.2e-018 -+uc = 0 vsat = 100370 a0 = 1 ags = 1e-020 -+a1 = 0 a2 = 1 b0 = 0 b1 = 0 -+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.06 -+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 -+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 -+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 -+rsh = 5 rdsw = 200 rsw = 100 rdw = 100 -+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 -+prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 -+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 -+egidl = 0.8 - -+aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 -+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 -+eigbinv = 1.1 nigbinv = 3 aigc = 0.012 bigc = 0.0028 -+cigc = 0.002 aigsd = 0.012 bigsd = 0.0028 cigsd = 0.002 -+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 - -+xrcrg1 = 12 xrcrg2 = 5 -+cgso = 2.4e-010 cgdo = 2.4e-010 cgbo = 2.56e-011 cgdl = 2.653e-10 -+cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 -+moin = 15 noff = 0.9 voffcv = 0.02 - -+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 -+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 -+at = 33000 - -+fnoimod = 1 tnoimod = 0 - -+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 -+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 -+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 -+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 -+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 -+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 -+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 -+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 -+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 -+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 -+xtis = 3 xtid = 3 - -+dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 -+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 - -+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 -+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 - -* PTM 130nm PMOS - -.model pmos pmos level = 54 - -+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 -+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 -+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 -+permod = 1 acnqsmod= 0 trnqsmod= 0 - -+tnom = 27 toxe = 2.35e-009 toxp = 1.6e-009 toxm = 2.35e-009 -+dtox = 0.75e-9 epsrox = 3.9 wint = 5e-009 lint = 10.5e-009 -+ll = 0 wl = 0 lln = 1 wln = 1 -+lw = 0 ww = 0 lwn = 1 wwn = 1 -+lwl = 0 wwl = 0 xpart = 0 toxref = 2.35e-009 -+xl = -60e-9 -+vth0 = -0.321 k1 = 0.4 k2 = -0.01 k3 = 0 -+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 -+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 -+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-009 -+dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 3.92e-008 -+ngate = 2e+020 ndep = 1.14e+018 nsd = 2e+020 phin = 0 -+cdsc = 0.000258 cdscb = 0 cdscd = 6.1e-008 cit = 0 -+voff = -0.126 nfactor = 1.5 eta0 = 0.0092 etab = 0 -+vfb = 0.55 u0 = 0.00835 ua = 2.0e-009 ub = 0.5e-018 -+uc = -3e-011 vsat = 70000 a0 = 1.0 ags = 1e-020 -+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0 -+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 -+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 -+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 -+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 -+rsh = 5 rdsw = 240 rsw = 120 rdw = 120 -+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 3.22e-008 -+prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 -+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 -+egidl = 0.8 - -+aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 -+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 -+eigbinv = 1.1 nigbinv = 3 aigc = 0.69 bigc = 0.0012 -+cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008 -+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 - -+xrcrg1 = 12 xrcrg2 = 5 -+cgso = 2.4e-010 cgdo = 2.4e-010 cgbo = 2.56e-011 cgdl = 2.653e-10 -+cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 -+moin = 15 noff = 0.9 voffcv = 0.02 - -+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 -+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 -+at = 33000 - -+fnoimod = 1 tnoimod = 0 - -+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 -+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 -+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 -+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 -+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 -+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 -+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 -+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 -+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 -+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 -+xtis = 3 xtid = 3 - -+dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 -+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 - -+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 -+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 - - diff --git a/fpga_flow/tech/PTM_130nm/130nm.xml b/fpga_flow/tech/PTM_130nm/130nm.xml deleted file mode 100644 index a4695daa6..000000000 --- a/fpga_flow/tech/PTM_130nm/130nm.xml +++ /dev/null @@ -1,7493 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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technology file was generated using the Nano-CMOS tool from http://ptm.asu.edu/ - -The following default parameters were used: - -NMOS -Leff=49 nm 10% -Vth=0.18 V 30mV -Vdd=1.3 V -Tox=1.6 nm -Rdsw=200 Ohm - -PMOS -Leff=49 nm 10% -Vth=-0.18 V 30mV -Vdd=1.3 V -Tox=1.6 nm -Rdsw=240 Ohm \ No newline at end of file diff --git a/fpga_flow/tech/PTM_22nm/22nm.pm b/fpga_flow/tech/PTM_22nm/22nm.pm deleted file mode 100644 index 6e4cd7b81..000000000 --- a/fpga_flow/tech/PTM_22nm/22nm.pm +++ /dev/null @@ -1,140 +0,0 @@ -* PTM High Performance 22nm Metal Gate / High-K / Strained-Si -* nominal Vdd = 0.8V - -.model nmos nmos level = 54 - -+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 -+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 -+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 -+permod = 1 acnqsmod= 0 trnqsmod= 0 - -+tnom = 27 toxe = 1.05e-009 toxp = 8e-010 toxm = 1.05e-009 -+dtox = 2.5e-010 epsrox = 3.9 wint = 5e-009 lint = 2e-009 -+ll = 0 wl = 0 lln = 1 wln = 1 -+lw = 0 ww = 0 lwn = 1 wwn = 1 -+lwl = 0 wwl = 0 xpart = 0 toxref = 1.05e-009 -+xl = -9e-9 - -+vth0 = 0.50308 k1 = 0.4 k2 = 0 k3 = 0 -+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 -+dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 -+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 -+dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 7.2e-009 -+ngate = 1e+023 ndep = 5.5e+018 nsd = 2e+020 phin = 0 -+cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 -+voff = -0.13 nfactor = 2.3 eta0 = 0.004 etab = 0 -+vfb = -0.55 u0 = 0.04 ua = 6e-010 ub = 1.2e-018 -+uc = 0 vsat = 250000 a0 = 1 ags = 0 -+a1 = 0 a2 = 1 b0 = 0 b1 = 0 -+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 -+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 -+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 -+fprout = 0.2 pdits = 0.01 pditsd = 0.23 pditsl = 2300000 -+rsh = 5 rdsw = 145 rsw = 75 rdw = 75 -+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 -+prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 -+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 -+egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 -+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 -+eigbinv = 1.1 nigbinv = 3 aigc = 0.0213 bigc = 0.0025889 -+cigc = 0.002 aigsd = 0.0213 bigsd = 0.0025889 cigsd = 0.002 -+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 -+xrcrg1 = 12 xrcrg2 = 5 - -+cgso = 6.5e-011 cgdo = 6.5e-011 cgbo = 2.56e-011 cgdl = 2.653e-010 -+cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 -+moin = 15 noff = 0.9 voffcv = 0.02 - -+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 -+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 -+at = 33000 - -+fnoimod = 1 tnoimod = 0 - -+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 -+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 -+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 -+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 -+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 -+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 -+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 -+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 -+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 -+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 -+xtis = 3 xtid = 3 - -+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 -+dwj = 0 xgw = 0 xgl = 0 - -+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 -+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 - - - -.model pmos pmos level = 54 - -+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 -+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 -+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 -+permod = 1 acnqsmod= 0 trnqsmod= 0 - -+tnom = 27 toxe = 1.1e-009 toxp = 8e-010 toxm = 1.1e-009 -+dtox = 3e-010 epsrox = 3.9 wint = 5e-009 lint = 2e-009 -+ll = 0 wl = 0 lln = 1 wln = 1 -+lw = 0 ww = 0 lwn = 1 wwn = 1 -+lwl = 0 wwl = 0 xpart = 0 toxref = 1.1e-009 -+xl = -9e-9 - -+vth0 = -0.4606 k1 = 0.4 k2 = -0.01 k3 = 0 -+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 -+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 -+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 -+dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 7.2e-009 -+ngate = 1e+023 ndep = 4.4e+018 nsd = 2e+020 phin = 0 -+cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 -+voff = -0.126 nfactor = 2.1 eta0 = 0.0038 etab = 0 -+vfb = 0.55 u0 = 0.0095 ua = 2e-009 ub = 5e-019 -+uc = 0 vsat = 210000 a0 = 1 ags = 1e-020 -+a1 = 0 a2 = 1 b0 = 0 b1 = 0 -+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 -+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 -+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 -+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 -+rsh = 5 rdsw = 145 rsw = 72.5 rdw = 72.5 -+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 -+prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 -+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 -+egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 -+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 -+eigbinv = 1.1 nigbinv = 3 aigc = 0.0213 bigc = 0.0025889 -+cigc = 0.002 aigsd = 0.0213 bigsd = 0.0025889 cigsd = 0.002 -+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 -+xrcrg1 = 12 xrcrg2 = 5 - -+cgso = 6.5e-011 cgdo = 6.5e-011 cgbo = 2.56e-011 cgdl = 2.653e-010 -+cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 -+moin = 15 noff = 0.9 voffcv = 0.02 - -+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 -+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 -+at = 33000 - -+fnoimod = 1 tnoimod = 0 - -+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 -+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 -+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 -+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 -+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 -+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 -+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 -+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 -+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 -+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 -+xtis = 3 xtid = 3 - -+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 -+dwj = 0 xgw = 0 xgl = 0 - -+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 -+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 diff --git a/fpga_flow/tech/PTM_22nm/22nm.xml b/fpga_flow/tech/PTM_22nm/22nm.xml deleted file mode 100644 index 11adf783a..000000000 --- a/fpga_flow/tech/PTM_22nm/22nm.xml +++ /dev/null @@ -1,7493 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga_flow/tech/PTM_22nm/readme.txt b/fpga_flow/tech/PTM_22nm/readme.txt deleted file mode 100644 index 85bb26a91..000000000 --- a/fpga_flow/tech/PTM_22nm/readme.txt +++ /dev/null @@ -1,2 +0,0 @@ -This technology file was obtained here: -http://ptm.asu.edu/modelcard/LP/22nm_LP.pm diff --git a/fpga_flow/tech/PTM_45nm/45nm.pm b/fpga_flow/tech/PTM_45nm/45nm.pm deleted file mode 100644 index 21187b41e..000000000 --- a/fpga_flow/tech/PTM_45nm/45nm.pm +++ /dev/null @@ -1,141 +0,0 @@ -* PTM High Performance 45nm Metal Gate / High-K / Strained-Si -* nominal Vdd = 1.0V - -.model nmos nmos level = 54 - -+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 -+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 -+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 -+permod = 1 acnqsmod= 0 trnqsmod= 0 - -+tnom = 27 toxe = 1.25e-009 toxp = 1e-009 toxm = 1.25e-009 -+dtox = 2.5e-010 epsrox = 3.9 wint = 5e-009 lint = 3.75e-009 -+ll = 0 wl = 0 lln = 1 wln = 1 -+lw = 0 ww = 0 lwn = 1 wwn = 1 -+lwl = 0 wwl = 0 xpart = 0 toxref = 1.25e-009 -+xl = -20e-9 - -+vth0 = 0.46893 k1 = 0.4 k2 = 0 k3 = 0 -+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 -+dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 -+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-010 -+dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 1.4e-008 -+ngate = 1e+023 ndep = 3.24e+018 nsd = 2e+020 phin = 0 -+cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 -+voff = -0.13 nfactor = 2.22 eta0 = 0.0055 etab = 0 -+vfb = -0.55 u0 = 0.054 ua = 6e-010 ub = 1.2e-018 -+uc = 0 vsat = 170000 a0 = 1 ags = 0 -+a1 = 0 a2 = 1 b0 = 0 b1 = 0 -+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 -+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 -+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 -+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 -+rsh = 5 rdsw = 155 rsw = 80 rdw = 80 -+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 -+prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 -+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 -+egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 -+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 -+eigbinv = 1.1 nigbinv = 3 aigc = 0.02 bigc = 0.0025 -+cigc = 0.002 aigsd = 0.02 bigsd = 0.0025 cigsd = 0.002 -+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 -+xrcrg1 = 12 xrcrg2 = 5 - -+cgso = 1.1e-010 cgdo = 1.1e-010 cgbo = 2.56e-011 cgdl = 2.653e-010 -+cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 -+moin = 15 noff = 0.9 voffcv = 0.02 - -+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 -+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 -+at = 33000 - -+fnoimod = 1 tnoimod = 0 - -+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 -+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 -+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 -+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 -+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 -+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 -+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 -+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 -+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 -+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 -+xtis = 3 xtid = 3 - -+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 -+dwj = 0 xgw = 0 xgl = 0 - -+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 -+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 - - - -.model pmos pmos level = 54 - -+version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 -+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 -+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 -+permod = 1 acnqsmod= 0 trnqsmod= 0 - -+tnom = 27 toxe = 1.3e-009 toxp = 1e-009 toxm = 1.3e-009 -+dtox = 3e-010 epsrox = 3.9 wint = 5e-009 lint = 3.75e-009 -+ll = 0 wl = 0 lln = 1 wln = 1 -+lw = 0 ww = 0 lwn = 1 wwn = 1 -+lwl = 0 wwl = 0 xpart = 0 toxref = 1.3e-009 -+xl = -20e-9 - -+vth0 = -0.49158 k1 = 0.4 k2 = -0.01 k3 = 0 -+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 -+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 -+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 -+dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 1.4e-008 -+ngate = 1e+023 ndep = 2.44e+018 nsd = 2e+020 phin = 0 -+cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 -+voff = -0.126 nfactor = 2.1 eta0 = 0.0055 etab = 0 -+vfb = 0.55 u0 = 0.02 ua = 2e-009 ub = 5e-019 -+uc = 0 vsat = 150000 a0 = 1 ags = 1e-020 -+a1 = 0 a2 = 1 b0 = 0 b1 = 0 -+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 -+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 -+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 -+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 -+rsh = 5 rdsw = 155 rsw = 75 rdw = 75 -+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 -+prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 -+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 -+egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 -+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 -+eigbinv = 1.1 nigbinv = 3 aigc = 0.010687 bigc = 0.0012607 -+cigc = 0.0008 aigsd = 0.010687 bigsd = 0.0012607 cigsd = 0.0008 -+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 -+xrcrg1 = 12 xrcrg2 = 5 - -+cgso = 1.1e-010 cgdo = 1.1e-010 cgbo = 2.56e-011 cgdl = 2.653e-010 -+cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 -+moin = 15 noff = 0.9 voffcv = 0.02 - -+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 -+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 -+at = 33000 - -+fnoimod = 1 tnoimod = 0 - -+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 -+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 -+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 -+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 -+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 -+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 -+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 -+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 -+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 -+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 -+xtis = 3 xtid = 3 - -+dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 -+dwj = 0 xgw = 0 xgl = 0 - -+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 -+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 - diff --git a/fpga_flow/tech/PTM_45nm/45nm.xml b/fpga_flow/tech/PTM_45nm/45nm.xml deleted file mode 100644 index 570f921ba..000000000 --- a/fpga_flow/tech/PTM_45nm/45nm.xml +++ /dev/null @@ -1,7493 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh deleted file mode 100755 index d60a1e177..000000000 --- a/fpga_flow/tuto_fpga_flow.sh +++ /dev/null @@ -1,36 +0,0 @@ -#! /bin/bash -# Exit if error occurs -set -e -# Make sure a clear start -pwd_path="$PWD" -task_name="tuto" -config_file="$pwd_path/configs/tutorial/${task_name}.conf" -bench_txt="$pwd_path/benchmarks/List/tuto_benchmark.txt" -rpt_file="$pwd_path/csv_rpts/fpga_spice/${task_name}.csv" -verilog_path="${pwd_path}/${task_name}_Verilog" -architecture_generated="${pwd_path}/arch/generated/k6_N10_sram_chain_HC.xml" -architecture_template="${pwd_path}/arch/template/k6_N10_sram_chain_HC_template.xml" - -ff_keyword="FFPATHKEYWORD" -ff_template_path="${pwd_path}/../vpr7_x2p/vpr/VerilogNetlists/ff.v" -ff_path="${pwd_path}/../vpr7_x2p/vpr/VerilogNetlists/ff_${task_name}.v" -dir_keyword="GENERATED_DIR_KEYWORD" - -rm -rf ${pwd_path}/results_OpenPithon - -cd ${pwd_path}/arch -mkdir -p generated # create folder to save rewritten architecture -cd ${pwd_path}/scripts - -# Replace keyword in config and architecture files -perl rewrite_path_in_file.pl -i $config_file # Replace OPENFPGAPATHKEYWORD in the config file -perl rewrite_path_in_file.pl -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file -perl rewrite_path_in_file.pl -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file -echo "perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path" -perl rewrite_path_in_file.pl -i ${ff_template_path} -o ${ff_path} -k $dir_keyword $verilog_path # Set the define path in the ff.v file - -# SRAM FPGA -# TT case -perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test -vpr_fpga_verilog_explicit_mapping - -echo "Netlists successfully generated and tested" diff --git a/fpga_flow/vpr_fpga_spice_conf/sample.conf b/fpga_flow/vpr_fpga_spice_conf/sample.conf deleted file mode 100644 index 92d477f60..000000000 --- a/fpga_flow/vpr_fpga_spice_conf/sample.conf +++ /dev/null @@ -1,68 +0,0 @@ -[dir_path] -result_dir = results -shell_script_name = run_hspice_sim.sh -# dir names -pb_mux_tb_dir_name = pb_mux_tb -cb_mux_tb_dir_name = cb_mux_tb -sb_mux_tb_dir_name = sb_mux_tb -top_tb_dir_name = top_tb -grid_tb_dir_name = grid_tb -lut_tb_dir_name = lut_tb -hardlogic_tb_dir_name = hardlogic_tb -cb_tb_dir_name = cb_tb -sb_tb_dir_name = sb_tb -# Prefix -top_tb_prefix = -pb_mux_tb_prefix = _grid -cb_mux_tb_prefix = _cb -sb_mux_tb_prefix = _sb -lut_tb_prefix = _grid -hardlogic_tb_prefix = _grid -grid_tb_prefix = _grid -cb_tb_prefix = _cb -sb_tb_prefix = _sb -# Postfix -top_tb_postfix = _top.sp -pb_mux_tb_postfix = _pbmux_testbench.sp -cb_mux_tb_postfix = _cbmux_testbench.sp -sb_mux_tb_postfix = _sbmux_testbench.sp -lut_tb_postfix = _lut_testbench.sp -hardlogic_tb_postfix = _hardlogic_testbench.sp -grid_tb_postfix = _grid_testbench.sp -cb_tb_postfix = _cb_testbench.sp -sb_tb_postfix = _sb_testbench.sp - -[task_conf] -auto_check = on -num_pb_mux_tb = -num_cb_mux_tb = -num_sb_mux_tb = -num_lut_mux_tb = -num_hardlogic_tb = -num_grid_mux_tb = -num_top_tb = -num_cb_tb = -num_sb_tb = - -[csv_tags] -#top_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_sram_cbs|leakage_power_sram_sbs|leakage_power_io|leakage_power_local_interc|total_leakage_power_lut5|total_leakage_power_lut6|total_leakage_power_dff|leakage_power_cbs|leakage_power_sbs -top_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_sram_cbs|leakage_power_sram_sbs|leakage_power_local_interc|total_leakage_power_lut6|total_leakage_power_dff|leakage_power_cbs|leakage_power_sbs -#top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing|energy_per_cycle_sram_luts|energy_per_cycle_sram_cbs|energy_per_cycle_sram_sbs|energy_per_cycle_io|energy_per_cycle_local_routing|total_energy_per_cycle_lut5|total_energy_per_cycle_lut6|total_energy_per_cycle_dff|energy_per_cycle_cbs|energy_per_cycle_sbs -top_tb_dynamic_power_tags = energy_per_cycle_sram_local_routing|energy_per_cycle_sram_luts|energy_per_cycle_sram_cbs|energy_per_cycle_sram_sbs|energy_per_cycle_local_routing|total_energy_per_cycle_lut6|total_energy_per_cycle_dff|energy_per_cycle_cbs|energy_per_cycle_sbs #|crit_path_delay -pb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_pb_mux -cb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_cb_mux -sb_mux_tb_leakage_power_tags = total_leakage_srams|total_leakage_power_sb_mux -pb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_pb_mux -cb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_cb_mux -sb_mux_tb_dynamic_power_tags = total_energy_per_cycle_srams|total_energy_per_cycle_sb_mux -lut_tb_leakage_power_tags = leakage_power_sram_luts|total_leakage_power_lut6 -lut_tb_dynamic_power_tags = energy_per_cycle_sram_luts|total_energy_per_cycle_lut6 -hardlogic_tb_leakage_power_tags = total_leakage_power_dff -hardlogic_tb_dynamic_power_tags = total_energy_per_cycle_dff -grid_tb_leakage_power_tags = leakage_power_sram_local_routing|leakage_power_sram_luts|leakage_power_local_routing|total_leakage_power_lut6|total_leakage_power_dff -grid_tb_dynamic_power_tags = total_energy_per_cycle_sram_local_routing|total_energy_per_cycle_sram_luts|total_energy_per_cycle_local_routing|total_energy_per_cycle_lut6|total_energy_per_cycle_dff -cb_tb_leakage_power_tags = leakage_power_cb|leakage_power_sram_cb -cb_tb_dynamic_power_tags = energy_per_cycle_cb|energy_per_cycle_sram_cb -sb_tb_leakage_power_tags = leakage_power_sb|leakage_power_sram_sb -sb_tb_dynamic_power_tags = energy_per_cycle_sb|energy_per_cycle_sram_sb - diff --git a/openfpga/CMakeLists.txt b/openfpga/CMakeLists.txt index 609602e1a..8bae1ddf0 100644 --- a/openfpga/CMakeLists.txt +++ b/openfpga/CMakeLists.txt @@ -26,7 +26,7 @@ target_link_libraries(libopenfpga libfpgabitstream libini libvtrutil - libvpr8) + libvpr) #Create the test executable add_executable(openfpga ${EXEC_SOURCE}) diff --git a/openfpga/src/annotation/check_pb_graph_annotation.cpp b/openfpga/src/annotation/check_pb_graph_annotation.cpp index fdfa1394c..2b86667eb 100644 --- a/openfpga/src/annotation/check_pb_graph_annotation.cpp +++ b/openfpga/src/annotation/check_pb_graph_annotation.cpp @@ -60,7 +60,7 @@ void rec_check_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n t_pb_graph_node* physical_pb_graph_node = vpr_device_annotation.physical_pb_graph_node(pb_graph_node); if (nullptr == physical_pb_graph_node) { VTR_LOG_ERROR("Found a pb_graph_node '%s' missing physical pb_graph_node binding!\n", - physical_pb_graph_node->pb_type->name); + pb_graph_node->pb_type->name); num_err++; return; /* Invalid pointer already, further check is not applicable */ } diff --git a/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml b/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml deleted file mode 100644 index 0c932d704..000000000 --- a/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml +++ /dev/null @@ -1,631 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.I[5:0] clb.O[1:0] - clb.I[11:6] clb.O[3:2] - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml deleted file mode 100644 index 9af75ba69..000000000 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml +++ /dev/null @@ -1,1042 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - 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clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml deleted file mode 100644 index ced8ccda8..000000000 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml +++ /dev/null @@ -1,1155 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - memory_dp.d_in - memory_dp.clk memory_dp.wen memory_dp.waddr - memory_dp.d_out - memory_dp.ren memory_dp.raddr - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255e-12 - 255e-12 - 255e-12 - 255e-12 - 255e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml deleted file mode 100644 index f22464011..000000000 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml +++ /dev/null @@ -1,1042 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255e-12 - 255e-12 - 255e-12 - 255e-12 - 255e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml deleted file mode 100644 index fd4ef33fb..000000000 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml +++ /dev/null @@ -1,1042 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255e-12 - 255e-12 - 255e-12 - 255e-12 - 255e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml deleted file mode 100644 index 7b20e6ff9..000000000 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml +++ /dev/null @@ -1,1040 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255e-12 - 255e-12 - 255e-12 - 255e-12 - 255e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_stdcell_mux2_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_stdcell_mux2_template.xml deleted file mode 100644 index 410edebcf..000000000 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_stdcell_mux2_template.xml +++ /dev/null @@ -1,1030 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255e-12 - 255e-12 - 255e-12 - 255e-12 - 255e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml deleted file mode 100644 index cf2b87542..000000000 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +++ /dev/null @@ -1,1047 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255e-12 - 255e-12 - 255e-12 - 255e-12 - 255e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml deleted file mode 100644 index 912c7701a..000000000 --- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml +++ /dev/null @@ -1,1046 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255e-12 - 255e-12 - 255e-12 - 255e-12 - 255e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml b/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml deleted file mode 100644 index 4ff2c0800..000000000 --- a/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml +++ /dev/null @@ -1,1145 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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b/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml deleted file mode 100644 index c0d607084..000000000 --- a/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml +++ /dev/null @@ -1,524 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2.094e-09 - 2.094e-09 - 2.094e-09 - 2.094e-09 - 2.094e-09 - 2.094e-09 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.I[19:0] clb.O[4:0] - clb.I[39:20] clb.O[9:5] - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90_behavioral.xml b/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90_behavioral.xml deleted file mode 100644 index 0e39ccc08..000000000 --- a/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90_behavioral.xml +++ /dev/null @@ -1,524 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2.094e-09 - 2.094e-09 - 2.094e-09 - 2.094e-09 - 2.094e-09 - 2.094e-09 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.I[19:0] clb.O[4:0] - clb.I[39:20] clb.O[9:5] - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/scripts/run_simulation_task.py b/openfpga_flow/scripts/run_simulation_task.py deleted file mode 100644 index ad1e5f863..000000000 --- a/openfpga_flow/scripts/run_simulation_task.py +++ /dev/null @@ -1,71 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Script Name : regression.py -# Description : This script designed to run: -# openfpga_flow tasks -# run_{simulator}.py -# Args : python3 regression.py --help -# Author : Aurelien Alacchi -# Email : aurelien.alacchi@utah.edu -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -import os -import sys -import shutil -import time -from datetime import timedelta -import shlex -import argparse -from configparser import ConfigParser, ExtendedInterpolation -import logging -import glob -import subprocess -import threading -import csv -from string import Template -import pprint -from importlib import util -from collections import OrderedDict - -modelsim="modelsim" -vcs="vcs" -formality="formality" -modelsim_file="simulation_deck_info.ini" -ini_list="" - -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Parse commandline arguments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -parser = argparse.ArgumentParser() -parser.add_argument('tasks', nargs='+') -parser.add_argument('--maxthreads', type=int, default=2, - help="Number of fpga_flow threads to run default = 2," + - "Typically <= Number of processors on the system") -parser.add_argument('--simulator', type=str, default=modelsim, - help="Simulator to use. Set at \"" + modelsim + "\" by default. Can also be \"" + vcs + "\" or \"" + formality + "\"") -args = parser.parse_args() - - -args.tasks=str(args.tasks).strip('[]') -#print(args.tasks) -#print(args.maxthreads) - -command="python3 openfpga_flow/scripts/run_fpga_task.py " + args.tasks + " --maxthreads " + str(args.maxthreads) + " --debug --show_thread_logs" - -print(command) - -os.system(command) - -if(args.simulator == modelsim): - command="python3 openfpga_flow/scripts/run_modelsim.py" - os.system("grep \"INFO - Run directory :\" openfpga_flow/tasks/" + args.tasks + "/latest/*.log > paths_ini.txt") - arguments = " --skip_prompt --run_sim"; - fp = open("paths_ini.txt") - line = fp.readline() - while line: - ini_list= ini_list + line + modelsim_file - line = fp.readline() - ini_list = ini_list.replace("INFO - Run directory :", "") - ini_list = ini_list.replace("\n", "/") - fp.close() - print(command + ini_list + arguments) - os.system(command + ini_list + arguments) diff --git a/openfpga_flow/tasks/compact_routing/config/task.conf b/openfpga_flow/tasks/compact_routing/config/task.conf deleted file mode 100644 index 44334b6bd..000000000 --- a/openfpga_flow/tasks/compact_routing/config/task.conf +++ /dev/null @@ -1,59 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif - -[SYNTHESIS_PARAM] -bench0_top = test_modes -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v -bench0_chan_width = 300 - -#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -#fix_route_chan_width=300 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -##vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_verilog_explicit_mapping= -vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= - diff --git a/openfpga_flow/tasks/compilation_verification/config/task.conf b/openfpga_flow/tasks/compilation_verification/config/task.conf deleted file mode 100644 index 876783885..000000000 --- a/openfpga_flow/tasks/compilation_verification/config/task.conf +++ /dev/null @@ -1,59 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif - -[SYNTHESIS_PARAM] -bench0_top = K4n4_test -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v -bench0_chan_width = 100 - -#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -#fix_route_chan_width=300 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0] -min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_verilog_explicit_mapping= -vpr_fpga_x2p_compact_routing_hierarchy= -disp= -end_flow_with_test= diff --git a/openfpga_flow/tasks/duplicate_grid_pin/config/task.conf b/openfpga_flow/tasks/duplicate_grid_pin/config/task.conf deleted file mode 100644 index 8f7e56921..000000000 --- a/openfpga_flow/tasks/duplicate_grid_pin/config/task.conf +++ /dev/null @@ -1,59 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif - -[SYNTHESIS_PARAM] -bench0_top = test_modes -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v - -#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -#fix_route_chan_width=300 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -##vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_verilog_explicit_mapping= -#vpr_fpga_x2p_compact_routing_hierarchy= -vpr_fpga_x2p_duplicate_grid_pin= -end_flow_with_test= - diff --git a/openfpga_flow/tasks/epfl/config/task.conf b/openfpga_flow/tasks/epfl/config/task.conf deleted file mode 100644 index 30786dc37..000000000 --- a/openfpga_flow/tasks/epfl/config/task.conf +++ /dev/null @@ -1,101 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 200*60 -fpga_flow=yosys_vpr - -[ARCHITECTURES] -#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml -#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml -arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/adder/adder.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/arbiter/arbiter.v -bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/bar/bar.v -bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/cavlc/cavlc.v -bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/ctrl/ctrl.v -bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/dec/dec.v -bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/div/div.v -# This benchmark is failing -> debug ongoing -#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/hyp/hyp.v -bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/i2c/i2c.v -bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/int2float/int2float.v -bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/log2/log2.v -bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/max/max.v -# This benchmark is commented because of its runtime -#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/mem_ctrl/mem_ctrl.v -bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/multiplier/multiplier.v -bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/priority/priority.v -bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/router/router.v -bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/sin/sin.v -bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/sqrt/sqrt.v -bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/square/square.v -bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/voter/voter.v - -[SYNTHESIS_PARAM] -bench0_top = adder -bench1_top = arbiter -bench2_top = bar -bench3_top = cavlc -bench4_top = ctrl -bench5_top = dec -bench6_top = div -#bench7_top = hyp -bench8_top = i2c -bench9_top = int2float -bench10_top = log2 -bench11_top = max -bench12_top = mem_ctrl -bench13_top = multiplier -bench14_top = priority -bench15_top = router -bench16_top = sin -bench17_top = sqrt -bench18_top = square -bench19_top = voter - -#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -#fix_route_chan_width=300 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -##vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -min_route_chan_width=1.3 -#vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_verilog_explicit_mapping= -vpr_fpga_x2p_compact_routing_hierarchy= -# If you wish to run Modelsim verification in batch, turn on the ini file outputting -vpr_fpga_verilog_print_simulation_ini= -# If you wish to run Modelsim verification in batch, turn off running iVerilog at the end of the flow -#end_flow_with_test= - diff --git a/openfpga_flow/tasks/explicit_verilog/config/task.conf b/openfpga_flow/tasks/explicit_verilog/config/task.conf deleted file mode 100644 index 2a640bfae..000000000 --- a/openfpga_flow/tasks/explicit_verilog/config/task.conf +++ /dev/null @@ -1,43 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml -#arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif - -[SYNTHESIS_PARAM] -bench0_top = test_modes -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v -bench0_chan_width = 300 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT] -min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_x2p_compact_routing_hierarchy= -vpr_fpga_verilog_explicit_mapping= -end_flow_with_test= - diff --git a/openfpga_flow/tasks/heterogeneous_dpram/config/task.conf b/openfpga_flow/tasks/heterogeneous_dpram/config/task.conf deleted file mode 100644 index b567b74e0..000000000 --- a/openfpga_flow/tasks/heterogeneous_dpram/config/task.conf +++ /dev/null @@ -1,43 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif - -[SYNTHESIS_PARAM] -bench0_top = pipelined_8bit_adder -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v -bench0_chan_width = 100 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_verilog_explicit_mapping= -vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= diff --git a/openfpga_flow/tasks/mcnc_big20/config/task.conf b/openfpga_flow/tasks/mcnc_big20/config/task.conf deleted file mode 100644 index da190286e..000000000 --- a/openfpga_flow/tasks/mcnc_big20/config/task.conf +++ /dev/null @@ -1,165 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml -#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml -arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml - -[BENCHMARKS] -# Pass -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif -# Pass, but port does not match, i_15_ is dangling -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif -# Pass -bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif -bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif -# To be tested -bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif -bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif -bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif -bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif -bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif -bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif -bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif -bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif -bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif -bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif -# Pass -bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif -# Multi-mode support fails to repack, skip this now -#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif -bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif -bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif -bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif -bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif - -[SYNTHESIS_PARAM] -# Benchmark alu4 -bench0_top = alu4 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v -# Benchmark apex2 -bench1_top = apex2 -bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act -bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v -# Benchmark apex4 -bench2_top = apex4 -bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.act -bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.v -# Benchmark bigkey -bench3_top = bigkey -bench3_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.act -bench3_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.v -# Benchmark clma -bench4_top = clma -bench4_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.act -bench4_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.v -# Benchmark des -bench5_top = des -bench5_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.act -bench5_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.v -# Benchmark diffeq -bench6_top = diffeq -bench6_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.act -bench6_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.v -# Benchmark dsip -bench7_top = dsip -bench7_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.act -bench7_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.v -# Benchmark elliptic -bench8_top = elliptic -bench8_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.act -bench8_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.v -# Benchmark ex1010 -bench9_top = ex1010 -bench9_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.act -bench9_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.v -# Benchmark ex5p -bench10_top = ex5p -bench10_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.act -bench10_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v -# Benchmark frisc -bench11_top = frisc -bench11_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.act -bench11_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.v -# Benchmark misex3 -bench12_top = misex3 -bench12_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.act -bench12_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.v -# Benchmark pdc -bench13_top = pdc -bench13_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.act -bench13_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v -# Benchmark s298 -bench14_top = s298 -bench14_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act -bench14_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v -# Benchmark s38417 -bench15_top = s38417 -bench15_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.act -bench15_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.v -# Benchmark s38584 -bench16_top = s38584 -bench16_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.act -bench16_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.v -# Benchmark seq -bench17_top = seq -bench17_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.act -bench17_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.v -# Benchmark spla -bench18_top = spla -bench18_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.act -bench18_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.v -# Benchmark tseng -bench19_top = tseng -bench19_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.act -bench19_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.v - -#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -#fix_route_chan_width=300 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -##vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -min_route_chan_width=1.3 -#vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_verilog_explicit_mapping= -vpr_fpga_x2p_compact_routing_hierarchy= -# If you wish to run Modelsim verification in batch, turn on the ini file outputting -vpr_fpga_verilog_print_simulation_ini= -# If you wish to run Modelsim verification in batch, turn off running iVerilog at the end of the flow -#end_flow_with_test= - diff --git a/openfpga_flow/tasks/multi_mode/config/task.conf b/openfpga_flow/tasks/multi_mode/config/task.conf deleted file mode 100644 index 18f471cf7..000000000 --- a/openfpga_flow/tasks/multi_mode/config/task.conf +++ /dev/null @@ -1,65 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml -arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml -arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml -arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml -arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml -arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml -arch6=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_stdcell_mux2_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif - -[SYNTHESIS_PARAM] -bench0_top = test_modes -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v -bench0_chan_width = 300 - -#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -#fix_route_chan_width=300 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -##vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_verilog_explicit_mapping= -#vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= - diff --git a/openfpga_flow/tasks/s298/config/task.conf b/openfpga_flow/tasks/s298/config/task.conf deleted file mode 100644 index dd45f883a..000000000 --- a/openfpga_flow/tasks/s298/config/task.conf +++ /dev/null @@ -1,58 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N6_sram_chain_FC_behavioral_verilog_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif - -[SYNTHESIS_PARAM] -bench0_top = s298 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v -bench0_chan_width = 100 - -#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -#fix_route_chan_width=300 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0] -min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_verilog_explicit_mapping= -vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= diff --git a/openfpga_flow/tasks/single_mode/config/task.conf b/openfpga_flow/tasks/single_mode/config/task.conf deleted file mode 100644 index e3e2d3e8c..000000000 --- a/openfpga_flow/tasks/single_mode/config/task.conf +++ /dev/null @@ -1,59 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif - -[SYNTHESIS_PARAM] -bench0_top = K4n4_test -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v -bench0_chan_width = 100 - -#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -#fix_route_chan_width=300 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0] -min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_verilog_explicit_mapping= -vpr_fpga_x2p_compact_routing_hierarchy= -#vpr_fpga_verilog_print_simulation_ini= -end_flow_with_test= diff --git a/openfpga_flow/tasks/tileable_routing/config/task.conf b/openfpga_flow/tasks/tileable_routing/config/task.conf deleted file mode 100644 index 860a9ba32..000000000 --- a/openfpga_flow/tasks/tileable_routing/config/task.conf +++ /dev/null @@ -1,57 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif - -[SYNTHESIS_PARAM] -bench0_top = test_modes -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v -bench0_chan_width = 300 - -[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -fix_route_chan_width=300 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= - -#[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#min_route_chan_width=1.3 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= diff --git a/vpr/CMakeLists.txt b/vpr/CMakeLists.txt index 9df8703da..57d5ae9d7 100644 --- a/vpr/CMakeLists.txt +++ b/vpr/CMakeLists.txt @@ -1,6 +1,6 @@ cmake_minimum_required(VERSION 3.9) -project("vpr8") +project("vpr") set(VPR_EXECUTION_ENGINE "auto" CACHE STRING "Specify the framework for (potential) parallel execution") set_property(CACHE VPR_EXECUTION_ENGINE PROPERTY STRINGS auto serial tbb) @@ -46,16 +46,16 @@ if(${VTR_ENABLE_CAPNPROTO}) endif() #Create the library -add_library(libvpr8 STATIC +add_library(libvpr STATIC ${LIB_HEADERS} ${LIB_SOURCES} ) -target_include_directories(libvpr8 PUBLIC ${LIB_INCLUDE_DIRS}) -set_target_properties(libvpr8 PROPERTIES PREFIX "") #Avoid extra 'lib' prefix +target_include_directories(libvpr PUBLIC ${LIB_INCLUDE_DIRS}) +set_target_properties(libvpr PROPERTIES PREFIX "") #Avoid extra 'lib' prefix #Specify link-time dependancies -target_link_libraries(libvpr8 +target_link_libraries(libvpr libvtrutil libopenfpgautil libarchfpga @@ -67,7 +67,7 @@ target_link_libraries(libvpr8 #link graphics library only when graphics set to on if (VPR_USE_EZGL STREQUAL "on") - target_link_libraries(libvpr8 + target_link_libraries(libvpr ezgl) compile_gresources( @@ -100,21 +100,21 @@ if (VPR_USE_EZGL STREQUAL "on") endif() -target_compile_definitions(libvpr8 PUBLIC ${GRAPHICS_DEFINES}) +target_compile_definitions(libvpr PUBLIC ${GRAPHICS_DEFINES}) if(${VTR_ENABLE_CAPNPROTO}) - target_link_libraries(libvpr8 libvtrcapnproto) + target_link_libraries(libvpr libvtrcapnproto) endif() -add_executable(vpr8 ${EXEC_SOURCES}) +add_executable(vpr ${EXEC_SOURCES}) -target_link_libraries(vpr8 libvpr8) +target_link_libraries(vpr libvpr) #Supress IPO link warnings if IPO is enabled get_target_property(VPR_USES_IPO vpr INTERPROCEDURAL_OPTIMIZATION) if (VPR_USES_IPO) - set_target_properties(vpr8 PROPERTIES LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS}) + set_target_properties(vpr PROPERTIES LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS}) endif() @@ -145,9 +145,9 @@ if (VPR_PGO_CONFIG STREQUAL "prof_gen") foreach(flag ${PROF_GEN_FLAGS_TO_CHECK}) CHECK_CXX_COMPILER_FLAG(${flag} CXX_COMPILER_SUPPORTS_${flag}) if(CXX_COMPILER_SUPPORTS_${flag}) - target_compile_options(libvpr8 PUBLIC ${flag}) - target_compile_options(vpr8 PUBLIC ${flag}) - target_link_libraries(vpr8 ${flag}) + target_compile_options(libvpr PUBLIC ${flag}) + target_compile_options(vpr PUBLIC ${flag}) + target_link_libraries(vpr ${flag}) endif() endforeach() elseif (VPR_PGO_CONFIG STREQUAL "prof_use") @@ -155,9 +155,9 @@ elseif (VPR_PGO_CONFIG STREQUAL "prof_use") foreach(flag ${PROF_USE_FLAGS_TO_CHECK}) CHECK_CXX_COMPILER_FLAG(${flag} CXX_COMPILER_SUPPORTS_${flag}) if(CXX_COMPILER_SUPPORTS_${flag}) - target_compile_options(libvpr8 PUBLIC ${flag}) - target_compile_options(vpr8 PUBLIC ${flag}) - target_link_libraries(vpr8 ${flag}) + target_compile_options(libvpr PUBLIC ${flag}) + target_compile_options(vpr PUBLIC ${flag}) + target_link_libraries(vpr ${flag}) endif() endforeach() elseif (VPR_PGO_CONFIG STREQUAL "none") @@ -170,9 +170,9 @@ if (VTR_COMPILE_OPTIONS STREQUAL "strict") message(STATUS "VPR: building with strict flags") foreach(flag ${VPR_COMPILE_OPTIONS_FLAGS}) message(STATUS "\tAdding CXX flag: ${flag}") - target_compile_options(libvpr8 PRIVATE ${flag}) - target_compile_options(vpr8 PRIVATE ${flag}) - target_link_libraries(vpr8 ${flag}) + target_compile_options(libvpr PRIVATE ${flag}) + target_compile_options(vpr PRIVATE ${flag}) + target_link_libraries(vpr ${flag}) endforeach() endif() @@ -205,9 +205,9 @@ endif() #Configure the build to use the selected engine if (VPR_USE_EXECUTION_ENGINE STREQUAL "tbb") - target_compile_definitions(libvpr8 PRIVATE VPR_USE_TBB) - target_link_libraries(libvpr8 tbb) - target_link_libraries(libvpr8 tbbmalloc_proxy) #Use the scalable memory allocator + target_compile_definitions(libvpr PRIVATE VPR_USE_TBB) + target_link_libraries(libvpr tbb) + target_link_libraries(libvpr tbbmalloc_proxy) #Use the scalable memory allocator message(STATUS "VPR: will support parallel execution using '${VPR_USE_EXECUTION_ENGINE}'") elseif(VPR_USE_EXECUTION_ENGINE STREQUAL "serial") message(STATUS "VPR: will only support serial execution") @@ -222,29 +222,29 @@ if (VPR_USE_SIGNAL_HANDLER) #Check wheter VPR can use sigaction to handle signals (only supported by POSIX) CHECK_CXX_SYMBOL_EXISTS(sigaction csignal HAVE_SIGACTION) if(HAVE_SIGACTION) - target_compile_definitions(libvpr8 PRIVATE VPR_USE_SIGACTION) + target_compile_definitions(libvpr PRIVATE VPR_USE_SIGACTION) endif() endif() -install(TARGETS vpr8 libvpr8 DESTINATION bin) +install(TARGETS vpr libvpr DESTINATION bin) # # Unit Tests # file(GLOB_RECURSE TEST_SOURCES test/*.cpp) -add_executable(test_vpr8 ${TEST_SOURCES}) -target_link_libraries(test_vpr8 +add_executable(test_vpr ${TEST_SOURCES}) +target_link_libraries(test_vpr libcatch - libvpr8) + libvpr) #Supress IPO link warnings if IPO is enabled -get_target_property(TEST_VPR_USES_IPO vpr8 INTERPROCEDURAL_OPTIMIZATION) +get_target_property(TEST_VPR_USES_IPO vpr INTERPROCEDURAL_OPTIMIZATION) if (TEST_VPR_USES_IPO) - set_target_properties(test_vpr8 PROPERTIES LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS}) + set_target_properties(test_vpr PROPERTIES LINK_FLAGS ${IPO_LINK_WARN_SUPRESS_FLAGS}) endif() -add_test(NAME test_vpr8 +add_test(NAME test_vpr COMMAND test_vpr --use-colour=yes WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/test ) diff --git a/vpr/vpr b/vpr/vpr deleted file mode 120000 index 247bfcdee..000000000 --- a/vpr/vpr +++ /dev/null @@ -1 +0,0 @@ -../build/vpr/vpr \ No newline at end of file diff --git a/vpr/vpr b/vpr/vpr new file mode 100755 index 0000000000000000000000000000000000000000..82bb7e4204151cb0c820cb50e6daa87172cc497e GIT binary patch literal 5336144 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literal 0 HcmV?d00001 diff --git a/vpr7_x2p/CMakeLists.txt b/vpr7_x2p/CMakeLists.txt deleted file mode 100644 index 369716bb9..000000000 --- a/vpr7_x2p/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# VPR7-X2P libraries and VPR -add_subdirectory(libarchfpgavpr7) -add_subdirectory(libpcre) -add_subdirectory(libprinthandler) -add_subdirectory(vpr) diff --git a/vpr7_x2p/libarchfpgavpr7/CMakeLists.txt b/vpr7_x2p/libarchfpgavpr7/CMakeLists.txt deleted file mode 100644 index 0589c645f..000000000 --- a/vpr7_x2p/libarchfpgavpr7/CMakeLists.txt +++ /dev/null @@ -1,47 +0,0 @@ -cmake_minimum_required(VERSION 2.8.12) - -if (${CMAKE_VERSION} VERSION_GREATER "3.8") - #For cmake >= 3.9 INTERPROCEDURAL_OPTIMIZATION behaviour we need to explicitly - #set the cmake policy version number - cmake_policy(VERSION 3.9) - - # If we are using verison < 3.9 then setting INTERPROCEDURAL_OPTIMIZATION - # has no effect unless an Intel compiler is used -endif() - -project("libarchfpgavpr7") - -#Collect the source files -file(GLOB_RECURSE EXEC_SOURCES SRC/main.c) -file(GLOB_RECURSE LIB_SOURCES SRC/*.c SRC/*/*.c SRC/*.cpp SRC/*/*.cpp) -file(GLOB_RECURSE LIB_HEADERS SRC/*.h SRC/*/*.h) -files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS) - -# Use c++ compiler for c source files -set_source_files_properties(${LIB_SOURCES} PROPERTIES LANGUAGE CXX) -set_source_files_properties(${EXEC_SOURCES} PROPERTIES LANGUAGE CXX) -set_source_files_properties(${EXEC_SOURCES_SHELL} PROPERTIES LANGUAGE CXX) - -# Remove test executable from library -list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCES}) - -#Create the library -add_library(libarchfpgavpr7 STATIC - ${LIB_HEADERS} - ${LIB_SOURCES}) -# add header files to be included -target_include_directories(libarchfpgavpr7 PUBLIC ${LIB_INCLUDE_DIRS}) -set_target_properties(libarchfpgavpr7 PROPERTIES PREFIX "") #Avoid extra 'lib' prefix#Create the executable - -# Specify dependency -target_link_libraries(libarchfpgavpr7 - libvtrutil - libpcre - libprinthandler) - -add_executable(read_arch_vpr7 ${EXEC_SOURCES}) -target_link_libraries(read_arch_vpr7 libarchfpgavpr7 libvtrutil) - - -# install: TO BE TESTED -#install(TARGETS libarchfpga_vpr7 read_arch_vpr7 DESTINATION bin) diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/ReadLine.c b/vpr7_x2p/libarchfpgavpr7/SRC/ReadLine.c deleted file mode 100644 index e02444ef8..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/ReadLine.c +++ /dev/null @@ -1,189 +0,0 @@ -#include -#include -#include -#include -#include "util.h" -#include "ReadLine.h" - -/* Pass in a pointer to a token list. Is freed and then set to null */ -void FreeTokens(INOUTP char ***TokensPtr) { - assert(*TokensPtr); - assert(**TokensPtr); - - free(**TokensPtr); /* Free the string data */ - free(*TokensPtr); /* Free token list */ - *TokensPtr = NULL; /* Invalidate pointer since mem is gone */ -} - -/* Returns number of tokens in list. Zero if null list */ -int CountTokens(INP char **Tokens) { - int count = 0; - - if (NULL == Tokens) { - return 0; - }; - while (Tokens[count]) { - ++count; - }; - return count; -} - -/* Reads in a single line from file, splits into tokens and allocates - * a list of tokens. Returns the an array of character arrays with the - * final item being marked by an empty string. - * Returns NULL on EOF - * NB: Token list is does as two allocations, one for pointer list - * and one for character array. Free what pointer points to and then - * free the pointer itself */ -char ** -ReadLineTokens(INOUTP FILE * InFile, INOUTP int *LineNum) { - - enum { - BUFFSIZE = 65536 - }; - /* This is much more than enough */ - char Buffer[BUFFSIZE]; /* Must match BUFFSIZE */ - char *Res; - char *Last; - char *Cur; - char *Dst; - char **Tokens; - int TokenCount; - int Len; - int CurToken; - boolean InToken; - - do { - /* Read the string */ - Res = fgets(Buffer, BUFFSIZE, InFile); - if (NULL == Res) { - if (feof(InFile)) { - return NULL; /* Return NULL on EOF */ - } else { - vpr_printf(TIO_MESSAGE_ERROR, "Unexpected error reading file\n"); - exit(1); - } - } - ++(*LineNum); - - /* Strip newline if any */ - Last = Buffer + strlen(Buffer); - if ((Last > Buffer) && ('\n' == Last[-1])) { - --Last; - } - if ((Last > Buffer) && ('\r' == Last[-1])) { - --Last; - } - - /* Handle continued lines */ - while ((Last > Buffer) && ('\\' == Last[-1])) { - /* Strip off the backslash */ - --Last; - - /* Read next line by giving pointer to null-char as start for next */ - Res = fgets(Last, (BUFFSIZE - (Last - Buffer)), InFile); - if (NULL == Res) { - if (feof(InFile)) { - return NULL; /* Return NULL on EOF */ - } else { - vpr_printf(TIO_MESSAGE_ERROR, - "Unexpected error reading file\n"); - exit(1); - } - } - ++(*LineNum); - - /* Strip newline */ - Last = Buffer + strlen(Buffer); - if ((Last > Buffer) && ('\n' == Last[-1])) { - --Last; - } - if ((Last > Buffer) && ('\r' == Last[-1])) { - --Last; - } - } - - /* Strip comment if any */ - Cur = Buffer; - while (Cur < Last) { - if ('#' == *Cur) { - Last = Cur; - break; - } - ++Cur; - } - - /* Count tokens and find size */ - assert(Last < (Buffer + BUFFSIZE)); - Len = 0; - TokenCount = 0; - Cur = Buffer; - InToken = FALSE; - while (Cur < Last) { - if (InToken) { - if ((' ' == *Cur) || ('\t' == *Cur)) { - InToken = FALSE; - } else { - ++Len; - } - } else { - if ((' ' != *Cur) && ('\t' != *Cur)) { - ++TokenCount; - ++Len; - InToken = TRUE; - } - } - ++Cur; /* Advance pointer */ - } - } while (0 == TokenCount); - - /* Find the size of mem to alloc. Use a contiguous block so is - * easy to deallocate */ - Len = (sizeof(char) * Len) + /* Length of actual data */ - (sizeof(char) * TokenCount); /* Null terminators */ - - /* Alloc the pointer list and data list. Count the final - * empty string we will use as list terminator */ - Tokens = (char **) my_malloc(sizeof(char *) * (TokenCount + 1)); - *Tokens = (char *) my_malloc(sizeof(char) * Len); - - /* Copy tokens to result */ - Cur = Buffer; - Dst = *Tokens; - InToken = FALSE; - CurToken = 0; - while (Cur < Last) { - if (InToken) { - if ((' ' == *Cur) || ('\t' == *Cur)) { - InToken = FALSE; - *Dst = '\0'; /* Null term token */ - ++Dst; - ++CurToken; - } else { - *Dst = *Cur; /* Copy char */ - ++Dst; - } - } else { - if ((' ' != *Cur) && ('\t' != *Cur)) { - Tokens[CurToken] = Dst; /* Set token start pointer */ - *Dst = *Cur; /* Copy char */ - ++Dst; - InToken = TRUE; - } - } - ++Cur; /* Advance pointer */ - } - if (InToken) { - *Dst = '\0'; /* Null term final token */ - ++Dst; - ++CurToken; - } - assert(CurToken == TokenCount); - - /* Set the final empty string entry */ - Tokens[CurToken] = NULL; - - /* Return the string list */ - return Tokens; -} - diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/ReadLine.h b/vpr7_x2p/libarchfpgavpr7/SRC/ReadLine.h deleted file mode 100644 index 2263892cf..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/ReadLine.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef READLINE_H -#define READLINE_H - -#ifdef __cplusplus -extern "C" { -#endif - -char **ReadLineTokens(INOUTP FILE * InFile, INOUTP int *LineNum); -int CountTokens(INP char **Tokens); -void FreeTokens(INOUTP char ***TokensPtr); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/arch_types.h b/vpr7_x2p/libarchfpgavpr7/SRC/arch_types.h deleted file mode 100644 index fea1fed08..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/arch_types.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - Data types describing the FPGA architecture. - - Date: February 19, 2009 - Authors: Jason Luu and Kenneth Kent - */ - -#ifndef ARCH_TYPES_H -#define ARCH_TYPES_H - -#include "logic_types.h" -#include "physical_types.h" -#include "cad_types.h" - -/* Constant describing architecture library version number */ -#define VPR_VERSION "7.0" - -/* Input file parsing. */ -#define TOKENS " \t\n" - -/* Value for UNDEFINED data */ -#define UNDEFINED -1 - -/* Maximum value for mininum channel width to avoid overflows of short data type. */ -#define MAX_CHANNEL_WIDTH 8000 - -#endif - diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/arch_types_mrfpga.h b/vpr7_x2p/libarchfpgavpr7/SRC/arch_types_mrfpga.h deleted file mode 100644 index 44a834501..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/arch_types_mrfpga.h +++ /dev/null @@ -1,49 +0,0 @@ -/*mrFPGA specifications for read_xml_arch: Xifan TANG*/ -/* mrFPGA : Reshaped by Xifan TANG*/ -typedef struct s_buffer_inf t_buffer_inf; -struct s_buffer_inf { - float C; - float R; - float Tdel; -}; - -typedef struct s_memristor_inf t_memristor_inf; -struct s_memristor_inf { - float C; - float R; - float Tdel; -}; - -enum e_tech_comp { - CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM -}; -/* end */ - -typedef struct s_arch_mrfpga t_arch_mrfpga; -struct s_arch_mrfpga { - boolean is_isolation; - boolean is_stack; - boolean is_junction; - boolean is_wire_buffer; - boolean is_mrFPGA; - boolean is_accurate; - t_buffer_inf wire_buffer_inf; - t_memristor_inf memristor_inf; - int max_pins_per_side; - t_linked_int* main_best_buffer_list; - short num_normal_switch; - short start_seg_switch; - - /* show sram and pass transistor uasge*/ - boolean is_show_sram; - boolean is_show_pass_trans; - enum e_tech_comp tech_comp; - float Rseg_global; - float Cseg_global; - float rram_pass_tran_value; - - /* timing info to override the opin_to_wire connection block */ - int is_opin_cblock_defined; - float R_opin_cblock; - float T_opin_cblock; -}; diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/cad_types.h b/vpr7_x2p/libarchfpgavpr7/SRC/cad_types.h deleted file mode 100644 index 570dc84fc..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/cad_types.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - Data types used to give architectural hints for the CAD algorithm - */ -#ifndef CAD_TYPES_H -#define CAD_TYPES_H - -#include "logic_types.h" -#include "physical_types.h" -#include "util.h" - -struct s_pack_pattern_connections; -typedef struct s_pack_pattern_block { - int pattern_index; /* index of pattern that this block is a part of */ - const t_pb_type *pb_type; /* pb_type that this block is an instance of */ - struct s_pack_pattern_connections *connections; /* linked list of connections of logic blocks in pattern */ - int block_id; -} t_pack_pattern_block; - -/* Describes connections of s_pack_pattern_block */ -typedef struct s_pack_pattern_connections { - t_pack_pattern_block *from_block; - t_pb_graph_pin *from_pin; - - t_pack_pattern_block *to_block; - t_pb_graph_pin *to_pin; - - struct s_pack_pattern_connections *next; -} t_pack_pattern_connections; - -typedef struct s_pack_patterns { - char *name; /* name of this logic model pattern */ - int index; /* array index for pattern*/ - t_pack_pattern_block *root_block; /* root block used by this pattern */ - float base_cost; /* base cost of pattern eg. If a group of logical blocks match a pattern of smaller primitives, that is better than the same group using bigger primitives */ - int num_blocks; /* number of blocks in pattern */ - boolean *is_block_optional; /* [0..num_blocks-1] is the block_id in this pattern mandatory or optional to form a molecule */ - - boolean is_chain; /* Does this pattern chain across logic blocks */ - t_pb_graph_pin *chain_root_pin; /* pointer to logic block input pin that drives this chain from the preceding logic block */ -} t_pack_patterns; - -typedef struct s_model_chain_pattern { - char *name; /* name of this chain of logic */ - t_model *model; /* block associated with chain */ - t_model_ports *input_link_port; /* pointer to port of chain input */ - int inport_link_pin; /* applicable pin of chain input port */ - t_model_ports *output_link_port; /* pointer to port of chain output */ - int outport_link_pin; /* applicable pin of chain output port */ - struct s_model_chain_pattern *next; /* next chain (linked list) */ -} t_model_chain_pattern; - -/** - * Keeps track of locations that a primitive can go to during packing - * Linked list for easy insertion/deletion - */ -typedef struct s_cluster_placement_primitive { - t_pb_graph_node *pb_graph_node; - struct s_cluster_placement_primitive *next_primitive; - boolean valid; - float base_cost; /* cost independant of current status of packing */ - float incremental_cost; /* cost dependant on current status of packing */ -} t_cluster_placement_primitive; - -#endif diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpgavpr7/SRC/check_circuit_library.cpp deleted file mode 100644 index f0ed79a1c..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/check_circuit_library.cpp +++ /dev/null @@ -1,600 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: check_circuit_library.cpp - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/08/12 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ - -/************************************************************************ - * Function to perform fundamental checking for the circuit library - * such as - * 1. if default circuit models are defined - * 2. if any circuit models shared the same name or prefix - * 3. if nay circuit model miss mandatory ports - ***********************************************************************/ - -/* Header files should be included in a sequence */ -/* Standard header files required go first */ -#include "vtr_assert.h" - -#include "util.h" - -#include "check_circuit_library.h" - -/************************************************************************ - * Circuit models have unique names, return the number of errors - * If not found, we give an error - ***********************************************************************/ -static -size_t check_circuit_library_unique_names(const CircuitLibrary& circuit_lib) { - size_t num_err = 0; - - for (size_t i = 0; i < circuit_lib.num_models(); ++i) { - /* Skip for the last element, because the inner loop will access it */ - if (i == circuit_lib.num_models() - 1) { - continue; - } - /* Get the name of reference */ - const std::string& i_name = circuit_lib.model_name(CircuitModelId(i)); - for (size_t j = i + 1; j < circuit_lib.num_models(); ++j) { - /* Compare the name of candidate */ - const std::string& j_name = circuit_lib.model_name(CircuitModelId(j)); - /* Compare the name and skip for different names */ - if (0 != i_name.compare(j_name)) { - continue; - } - vpr_printf(TIO_MESSAGE_ERROR, - "Circuit model(index=%d) and (index=%d) share the same name, which is invalid!\n", - i , j, i_name.c_str()); - /* Incremental the counter for errors */ - num_err++; - } - } - - return num_err; -} - - -/************************************************************************ - * Circuit models have unique names, return the number of errors - * If not found, we give an error - ***********************************************************************/ -static -size_t check_circuit_library_unique_prefix(const CircuitLibrary& circuit_lib) { - size_t num_err = 0; - - for (size_t i = 0; i < circuit_lib.num_models(); ++i) { - /* Skip for the last element, because the inner loop will access it */ - if (i == circuit_lib.num_models() - 1) { - continue; - } - /* Get the name of reference */ - const std::string& i_prefix = circuit_lib.model_prefix(CircuitModelId(i)); - for (size_t j = i + 1; j < circuit_lib.num_models(); ++j) { - /* Compare the name of candidate */ - const std::string& j_prefix = circuit_lib.model_prefix(CircuitModelId(j)); - /* Compare the name and skip for different prefix */ - if (0 != i_prefix.compare(j_prefix)) { - continue; - } - vpr_printf(TIO_MESSAGE_ERROR, - "Circuit model(name=%s) and (name=%s) share the same prefix, which is invalid!\n", - circuit_lib.model_name(CircuitModelId(i)).c_str(), - circuit_lib.model_name(CircuitModelId(j)).c_str(), - i_prefix.c_str()); - /* Incremental the counter for errors */ - num_err++; - } - } - - return num_err; -} - -/************************************************************************ - * A generic function to check the port list of a circuit model in a given type - * If not found, we give an error - ***********************************************************************/ -static -size_t check_circuit_model_required(const CircuitLibrary& circuit_lib, - const enum e_spice_model_type& circuit_model_type_to_check) { - size_t num_err = 0; - - /* We must have an IOPAD*/ - if ( 0 == circuit_lib.models_by_type(circuit_model_type_to_check).size()) { - vpr_printf(TIO_MESSAGE_ERROR, - "At least one %s circuit model is required!\n", - CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type_to_check)]); - /* Incremental the counter for errors */ - num_err++; - } - - return num_err; -} - -/************************************************************************ - * A generic function to check the port list of a circuit model in a given type - * If not found, we give an error - ***********************************************************************/ -size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const std::vector& port_types_to_check) { - size_t num_err = 0; - - for (const auto& port_type: port_types_to_check) { - if (0 == circuit_lib.model_ports_by_type(circuit_model, port_type).size()) { - vpr_printf(TIO_MESSAGE_ERROR, - "%s circuit model(name=%s) does not have %s port\n", - CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))], - circuit_lib.model_name(circuit_model).c_str(), - CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type)]); - /* Incremental the counter for errors */ - num_err++; - } - } - - return num_err; -} - -/************************************************************************ - * A generic function to check the port size of a given circuit model - * if the port size does not match, we give an error - ***********************************************************************/ -size_t check_one_circuit_model_port_size_required(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const CircuitPortId& circuit_port, - const size_t& port_size_to_check) { - - size_t num_err = 0; - - if (port_size_to_check != circuit_lib.port_size(circuit_port)) { - vpr_printf(TIO_MESSAGE_ERROR, - "Port of circuit model(name=%s) does not have a port(type=%s) of size=%d.\n", - circuit_lib.model_name(circuit_model).c_str(), - CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(circuit_port))], - port_size_to_check); - /* Incremental the counter for errors */ - num_err++; - } - - return num_err; -} - -/************************************************************************ - * A generic function to check the port size of a given circuit model - * if the number of ports in the given type does not match, we give an error - * for each port, if the port size does not match, we give an error - ***********************************************************************/ -size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const enum e_spice_model_port_type& port_type_to_check, - const size_t& num_ports_to_check, - const size_t& port_size_to_check, - const bool& include_global_ports) { - - size_t num_err = 0; - - std::vector ports = circuit_lib.model_ports_by_type(circuit_model, port_type_to_check, false == include_global_ports); - if (num_ports_to_check != ports.size()) { - vpr_printf(TIO_MESSAGE_ERROR, - "Expect %d %s ports for a %s circuit model, but only have %d %s ports!\n", - num_ports_to_check, - CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)], - CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))], - ports.size(), - CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)]); - num_err++; - } - for (const auto& port : ports) { - num_err += check_one_circuit_model_port_size_required(circuit_lib, - circuit_model, - port, port_size_to_check); - } - - return num_err; -} - -/************************************************************************ - * A generic function to check the port list of circuit models in a given type - * If not found, we give an error - ***********************************************************************/ -static -size_t check_circuit_model_port_required(const CircuitLibrary& circuit_lib, - const enum e_spice_model_type& circuit_model_type_to_check, - const std::vector& port_types_to_check) { - size_t num_err = 0; - - for (const auto& id : circuit_lib.models_by_type(circuit_model_type_to_check)) { - num_err += check_one_circuit_model_port_required(circuit_lib, id, port_types_to_check); - } - - return num_err; -} - -/************************************************************************ - * A generic function to find the default circuit model with a given type - * If not found, we give an error - ***********************************************************************/ -static -size_t check_required_default_circuit_model(const CircuitLibrary& circuit_lib, - const enum e_spice_model_type& circuit_model_type) { - size_t num_err = 0; - - if (CircuitModelId::INVALID() == circuit_lib.default_model(circuit_model_type)) { - vpr_printf(TIO_MESSAGE_ERROR, - "A default circuit model for the type %s! Try to define it in your architecture file!\n", - CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type)]); - exit(1); - } - - return num_err; -} - -/************************************************************************ - * A function to check the port map of FF circuit model - ***********************************************************************/ -size_t check_ff_circuit_model_ports(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - size_t num_err = 0; - - /* Check the type of circuit model */ - VTR_ASSERT(SPICE_MODEL_FF == circuit_lib.model_type(circuit_model)); - /* Check if we have D, Set and Reset */ - num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, - SPICE_MODEL_PORT_INPUT, - 3, 1, false); - /* Check if we have a clock */ - num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, - SPICE_MODEL_PORT_CLOCK, - 1, 1, false); - - - /* Check if we have output */ - num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, - SPICE_MODEL_PORT_OUTPUT, - 1, 1, false); - - return num_err; -} - -/************************************************************************ - * A function to check the port map of CCFF circuit model - ***********************************************************************/ -size_t check_ccff_circuit_model_ports(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - size_t num_err = 0; - - /* Check the type of circuit model */ - VTR_ASSERT(SPICE_MODEL_CCFF == circuit_lib.model_type(circuit_model)); - - /* Check if we have D, Set and Reset */ - num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, - SPICE_MODEL_PORT_INPUT, - 1, 1, false); - /* Check if we have a clock */ - num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, - SPICE_MODEL_PORT_CLOCK, - 1, 1, true); - - - /* Check if we have output */ - num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, - SPICE_MODEL_PORT_OUTPUT, - 2, 1, false); - - return num_err; -} - -/************************************************************************ - * A function to check the port map of SRAM circuit model - ***********************************************************************/ -size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const bool& check_blwl) { - size_t num_err = 0; - - /* Check the type of circuit model */ - VTR_ASSERT(SPICE_MODEL_SRAM == circuit_lib.model_type(circuit_model)); - - /* Check if we has 1 output with size 2 */ - num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, - SPICE_MODEL_PORT_OUTPUT, - 1, 2, false); - /* basic check finished here */ - if (false == check_blwl) { - return num_err; - } - - /* If bl and wl are required, check their existence */ - num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, - SPICE_MODEL_PORT_BL, - 1, 1, false); - - num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, - SPICE_MODEL_PORT_WL, - 1, 1, false); - - return num_err; -} - -/* Check all the ports make sure, they satisfy the restriction */ -static -size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) { - size_t num_err = 0; - - /* Check global ports: make sure all the global ports are input ports */ - for (const auto& port : circuit_lib.ports()) { - if ( (circuit_lib.port_is_global(port)) - && (!circuit_lib.is_input_port(port)) - && (!circuit_lib.is_output_port(port)) ) { - vpr_printf(TIO_MESSAGE_ERROR, - "Circuit port (type=%s) of model (name=%s) is defined as global but not an input/output port!\n", - CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))], - circuit_lib.model_name(port).c_str()); - num_err++; - } - } - - /* Check set/reset/config_enable ports: make sure they are all global ports */ - for (const auto& port : circuit_lib.ports()) { - if ( ( (circuit_lib.port_is_set(port)) - || (circuit_lib.port_is_reset(port)) - || (circuit_lib.port_is_config_enable(port)) ) - && (!circuit_lib.port_is_global(port)) ) { - vpr_printf(TIO_MESSAGE_ERROR, - "Circuit port (type=%s) of model (name=%s) is defined as a set/reset/config_enable port but it is not global!\n", - CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))], - circuit_lib.model_name(port).c_str()); - num_err++; - } - } - - /* Check the tri-state map of ports, the length should match the port size! */ - for (const auto& port : circuit_lib.ports()) { - if (circuit_lib.port_tri_state_map(port).empty()) { - continue; /* No tri-state map is found, go to the next */ - } - if (circuit_lib.port_tri_state_map(port).length() == circuit_lib.port_size(port)) { - continue; /* Sizes match, go to the next */ - } - /* We have a problem here, sizes do not match, leave a message and raise the error flag */ - vpr_printf(TIO_MESSAGE_ERROR, - "Tri-state map (=%s) of circuit port (type=%s) of model (name=%s) does not match the port size (=%lu)!\n", - circuit_lib.port_tri_state_map(port).c_str(), - CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))], - circuit_lib.model_name(port).c_str(), - circuit_lib.port_size(port)); - num_err++; - } - - /* Check all the global ports which sare the same name also share the same attributes: - * default_value, is_config, is_reset, is_set etc. - */ - std::vector global_ports; - - /* Collect all the global ports */ - for (auto port : circuit_lib.ports()) { - /* By pass non-global ports*/ - if (false == circuit_lib.port_is_global(port)) { - continue; - } - global_ports.push_back(port); - } - - for (size_t iport = 0; iport < global_ports.size() - 1; ++iport) { - for (size_t jport = iport + 1; jport < global_ports.size(); ++jport) { - /* Bypass those do not share the same name */ - if (0 != circuit_lib.port_prefix(global_ports[iport]).compare(circuit_lib.port_prefix(global_ports[jport]))) { - continue; - } - - /* Check if a same port share the same attributes */ - CircuitModelId iport_parent_model = circuit_lib.port_parent_model(global_ports[iport]); - CircuitModelId jport_parent_model = circuit_lib.port_parent_model(global_ports[jport]); - - if (circuit_lib.port_default_value(global_ports[iport]) != circuit_lib.port_default_value(global_ports[jport])) { - vpr_printf(TIO_MESSAGE_ERROR, - "Global ports %s from circuit model %s and %s share the same name but have different dfefault values(%lu and %lu)!\n", - circuit_lib.port_prefix(global_ports[iport]).c_str(), - circuit_lib.model_name(iport_parent_model).c_str(), - circuit_lib.model_name(jport_parent_model).c_str(), - circuit_lib.port_default_value(global_ports[iport]), - circuit_lib.port_default_value(global_ports[jport]) - ); - num_err++; - } - - if (circuit_lib.port_is_reset(global_ports[iport]) != circuit_lib.port_is_reset(global_ports[jport])) { - vpr_printf(TIO_MESSAGE_ERROR, - "Global ports %s from circuit model %s and %s share the same name but have different is_reset attributes!\n", - circuit_lib.port_prefix(global_ports[iport]).c_str(), - circuit_lib.model_name(iport_parent_model).c_str(), - circuit_lib.model_name(jport_parent_model).c_str() - ); - num_err++; - } - if (circuit_lib.port_is_set(global_ports[iport]) != circuit_lib.port_is_set(global_ports[jport])) { - vpr_printf(TIO_MESSAGE_ERROR, - "Global ports %s from circuit model %s and %s share the same name but have different is_set attributes!\n", - circuit_lib.port_prefix(global_ports[iport]).c_str(), - circuit_lib.model_name(iport_parent_model).c_str(), - circuit_lib.model_name(jport_parent_model).c_str() - ); - num_err++; - } - if (circuit_lib.port_is_config_enable(global_ports[iport]) != circuit_lib.port_is_config_enable(global_ports[jport])) { - vpr_printf(TIO_MESSAGE_ERROR, - "Global ports %s from circuit model %s and %s share the same name but have different is_config_enable attributes!\n", - circuit_lib.port_prefix(global_ports[iport]).c_str(), - circuit_lib.model_name(iport_parent_model).c_str(), - circuit_lib.model_name(jport_parent_model).c_str() - ); - num_err++; - } - if (circuit_lib.port_is_prog(global_ports[iport]) != circuit_lib.port_is_prog(global_ports[jport])) { - vpr_printf(TIO_MESSAGE_ERROR, - "Global ports %s from circuit model %s and %s share the same name but have different is_prog attributes!\n", - circuit_lib.port_prefix(global_ports[iport]).c_str(), - circuit_lib.model_name(iport_parent_model).c_str(), - circuit_lib.model_name(jport_parent_model).c_str() - ); - num_err++; - } - } - } - - return num_err; -} - -/************************************************************************ - * Check points to make sure we have a valid circuit library - * Detailed checkpoints: - * 1. Circuit models have unique names - * 2. Circuit models have unique prefix - * 3. Check IOPADs have input and output ports - * 4. Check MUXes has been defined and has input and output ports - * 5. We must have at least one SRAM or CCFF - * 6. SRAM must have at least an input and an output ports - * 7. CCFF must have at least a clock, an input and an output ports - * 8. FF must have at least a clock, an input and an output ports - * 9. LUT must have at least an input, an output and a SRAM ports - * 10. We must have default circuit models for these types: MUX, channel wires and wires - ***********************************************************************/ -void check_circuit_library(const CircuitLibrary& circuit_lib) { - size_t num_err = 0; - - vpr_printf(TIO_MESSAGE_INFO, "Checking circuit models...\n"); - - /* 1. Circuit models have unique names - * For each circuit model, we always make sure it does not share any name with any circuit model locating after it - */ - num_err += check_circuit_library_unique_names(circuit_lib); - - /* 2. Circuit models have unique prefix - * For each circuit model, we always make sure it does not share any prefix with any circuit model locating after it - */ - num_err += check_circuit_library_unique_prefix(circuit_lib); - - /* Check global ports */ - num_err += check_circuit_library_ports(circuit_lib); - - /* 3. Check io has been defined and has input and output ports - * [a] We must have an IOPAD! - * [b] For each IOPAD, we must have at least an input, an output, an INOUT and an SRAM port - */ - num_err += check_circuit_model_required(circuit_lib, SPICE_MODEL_IOPAD); - - std::vector iopad_port_types_required; - iopad_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); - iopad_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); - iopad_port_types_required.push_back(SPICE_MODEL_PORT_INOUT); - iopad_port_types_required.push_back(SPICE_MODEL_PORT_SRAM); - - num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_IOPAD, iopad_port_types_required); - - /* 4. Check mux has been defined and has input and output ports - * [a] We must have a MUX! - * [b] For each MUX, we must have at least an input, an output, and an SRAM port - */ - num_err += check_circuit_model_required(circuit_lib, SPICE_MODEL_MUX); - - std::vector mux_port_types_required; - mux_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); - mux_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); - mux_port_types_required.push_back(SPICE_MODEL_PORT_SRAM); - - num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_MUX, mux_port_types_required); - - /* 5. We must have at least one SRAM or CCFF */ - if ( ( 0 == circuit_lib.models_by_type(SPICE_MODEL_SRAM).size()) - && ( 0 == circuit_lib.models_by_type(SPICE_MODEL_CCFF).size()) ) { - vpr_printf(TIO_MESSAGE_ERROR, - "At least one %s or %s circuit model is required!\n", - CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_SRAM)], - CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_CCFF)]); - /* Incremental the counter for errors */ - num_err++; - } - - /* 6. SRAM must have at least an input and an output ports*/ - std::vector sram_port_types_required; - sram_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); - sram_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); - - num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_SRAM, sram_port_types_required); - - /* 7. CCFF must have at least a clock, an input and an output ports*/ - std::vector ccff_port_types_required; - ccff_port_types_required.push_back(SPICE_MODEL_PORT_CLOCK); - ccff_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); - ccff_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); - - num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_CCFF, ccff_port_types_required); - - /* 8. FF must have at least a clock, an input and an output ports*/ - std::vector ff_port_types_required; - ff_port_types_required.push_back(SPICE_MODEL_PORT_CLOCK); - ff_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); - ff_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); - - num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_FF, ff_port_types_required); - - /* 9. LUT must have at least an input, an output and a SRAM ports*/ - std::vector lut_port_types_required; - lut_port_types_required.push_back(SPICE_MODEL_PORT_SRAM); - lut_port_types_required.push_back(SPICE_MODEL_PORT_INPUT); - lut_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT); - - num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_LUT, lut_port_types_required); - - /* 10. We must have default circuit models for these types: MUX, channel wires and wires */ - num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_MUX); - num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_CHAN_WIRE); - num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_WIRE); - - /* If we have any errors, exit */ - - if (0 < num_err) { - vpr_printf(TIO_MESSAGE_INFO, - "Finished checking circuit library with %d errors!\n", - num_err); - exit(1); - } - - vpr_printf(TIO_MESSAGE_INFO, - "Checking circuit library passed.\n"); - - return; -} - -/************************************************************************ - * End of file : check_circuit_library.cpp - ***********************************************************************/ - diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/check_circuit_library.h b/vpr7_x2p/libarchfpgavpr7/SRC/check_circuit_library.h deleted file mode 100644 index dd6114696..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/check_circuit_library.h +++ /dev/null @@ -1,88 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: check_circuit_library.h - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/08/12 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ - -/* IMPORTANT: - * The following preprocessing flags are added to - * avoid compilation error when this headers are included in more than 1 times - */ -#ifndef CHECK_CIRCUIT_LIBRARY_H -#define CHECK_CIRCUIT_LIBRARY_H - -/* - * Notes in include header files in a head file - * Only include the neccessary header files - * that is required by the data types in the function/class declarations! - */ -/* Header files should be included in a sequence */ -/* Standard header files required go first */ -#include -#include "spice_types.h" -#include "circuit_library_fwd.h" - -/* Check points to make sure we have a valid circuit library */ -size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const std::vector& port_types_to_check); - -size_t check_one_circuit_model_port_size_required(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const CircuitPortId& circuit_port, - const size_t& port_size_to_check); - -size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const enum e_spice_model_port_type& port_type_to_check, - const size_t& num_ports_to_check, - const size_t& port_size_to_check, - const bool& include_global_ports); - -size_t check_ff_circuit_model_ports(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model); - -size_t check_ccff_circuit_model_ports(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model); - -size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const bool& check_blwl); - -void check_circuit_library(const CircuitLibrary& circuit_lib); - -#endif - -/************************************************************************ - * End of file : check_circuit_library.h - ***********************************************************************/ - diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.cpp deleted file mode 100644 index 2a5154e44..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.cpp +++ /dev/null @@ -1,2249 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: circuit_library.cpp - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/08/07 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ - -#include -#include - -#include "vtr_assert.h" - -#include "port_parser.h" -#include "circuit_library.h" - -/************************************************************************ - * Member functions for class CircuitLibrary - ***********************************************************************/ - -/************************************************************************ - * Constructors - ***********************************************************************/ -CircuitLibrary::CircuitLibrary() { - return; -} - -/************************************************************************ - * Public Accessors : aggregates - ***********************************************************************/ -CircuitLibrary::circuit_model_range CircuitLibrary::models() const { - return vtr::make_range(model_ids_.begin(), model_ids_.end()); -} - -CircuitLibrary::circuit_port_range CircuitLibrary::ports() const { - return vtr::make_range(port_ids_.begin(), port_ids_.end()); -} - -/* Find circuit models in the same type (defined by users) and return a list of ids */ -std::vector CircuitLibrary::models_by_type(const enum e_spice_model_type& type) const { - std::vector type_ids; - for (auto id : models()) { - /* Skip unmatched types */ - if (type != model_type(id)) { - continue; - } - /* Matched type, update the vector */ - type_ids.push_back(id); - } - return type_ids; -} - -/************************************************************************ - * Public Accessors : Basic data query on Circuit Models - ***********************************************************************/ -/* Get the number of circuit models */ -size_t CircuitLibrary::num_models() const { - return model_ids_.size(); -} - -/* Access the type of a circuit model */ -enum e_spice_model_type CircuitLibrary::model_type(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return model_types_[model_id]; -} - -/* Access the name of a circuit model */ -std::string CircuitLibrary::model_name(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return model_names_[model_id]; -} - -/* Access the prefix of a circuit model */ -std::string CircuitLibrary::model_prefix(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return model_prefix_[model_id]; -} - -/* Access the path + file of user-defined verilog netlist of a circuit model */ -std::string CircuitLibrary::model_verilog_netlist(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return model_verilog_netlists_[model_id]; -} - -/* Access the path + file of user-defined spice netlist of a circuit model */ -std::string CircuitLibrary::model_spice_netlist(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return model_spice_netlists_[model_id]; -} - -/* Access the is_default flag (check if this is the default circuit model in the type) of a circuit model */ -bool CircuitLibrary::model_is_default(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return model_is_default_[model_id]; -} - -/* Access the dump_structural_verilog flag of a circuit model */ -bool CircuitLibrary::dump_structural_verilog(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return dump_structural_verilog_[model_id]; -} - -/* Access the dump_explicit_port_map flag of a circuit model */ -bool CircuitLibrary::dump_explicit_port_map(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return dump_explicit_port_map_[model_id]; -} - -/* Access the design technology type of a circuit model */ -enum e_spice_model_design_tech CircuitLibrary::design_tech_type(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return design_tech_types_[model_id]; -} - -/* Access the is_power_gated flag of a circuit model */ -bool CircuitLibrary::is_power_gated(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return is_power_gated_[model_id]; -} - -/* Return a flag showing if inputs are buffered for a circuit model */ -bool CircuitLibrary::is_input_buffered(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return buffer_existence_[model_id][INPUT]; -} - -/* Return a flag showing if outputs are buffered for a circuit model */ -bool CircuitLibrary::is_output_buffered(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return buffer_existence_[model_id][OUTPUT]; -} - -/* Return a flag showing if intermediate stages of a LUT are buffered for a circuit model */ -bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); - /* LUT inter buffer may not always exist */ - if (LUT_INTER_BUFFER < buffer_existence_[model_id].size()) { - return buffer_existence_[model_id][LUT_INTER_BUFFER]; - } else { - return false; - } -} - -/* Return a flag showing if a LUT circuit model uses fracturable structure */ -bool CircuitLibrary::is_lut_fracturable(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); - return lut_is_fracturable_[model_id]; -} - -/* Return the circuit model of input buffers - * that are inserted between multiplexing structure and LUT inputs - */ -CircuitModelId CircuitLibrary::lut_input_inverter_model(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is BUF */ - VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); - /* We MUST have an input inverter */ - VTR_ASSERT(true == buffer_existence_[model_id][LUT_INPUT_INVERTER]); - return buffer_model_ids_[model_id][LUT_INPUT_INVERTER]; -} - -/* Return the circuit model of input buffers - * that are inserted between multiplexing structure and LUT inputs - */ -CircuitModelId CircuitLibrary::lut_input_buffer_model(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is BUF */ - VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); - /* We MUST have an input buffer */ - VTR_ASSERT(true == buffer_existence_[model_id][LUT_INPUT_BUFFER]); - return buffer_model_ids_[model_id][LUT_INPUT_BUFFER]; -} - -/* Return the circuit model of intermediate buffers - * that are inserted inside LUT multiplexing structures - */ -CircuitModelId CircuitLibrary::lut_intermediate_buffer_model(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is BUF */ - VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); - /* if we have an intermediate buffer, we return something, otherwise return an invalid id */ - if (true == is_lut_intermediate_buffered(model_id)) { - return buffer_model_ids_[model_id][LUT_INTER_BUFFER]; - } else { - return CircuitModelId::INVALID(); - } -} - -/* Return the location map of intermediate buffers - * that are inserted inside LUT multiplexing structures - */ -std::string CircuitLibrary::lut_intermediate_buffer_location_map(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is BUF */ - VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); - /* if we have an intermediate buffer, we return something, otherwise return an empty map */ - if (true == is_lut_intermediate_buffered(model_id)) { - return buffer_location_maps_[model_id][LUT_INTER_BUFFER]; - } else { - return std::string(); - } -} - -/* Find the id of pass-gate circuit model - * Two cases to be considered: - * 1. this is a pass-gate circuit model, just find the data and return - * 2. this circuit model includes a pass-gate, find the link to pass-gate circuit model and go recursively - */ -CircuitModelId CircuitLibrary::pass_gate_logic_model(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - - /* Return the data if this is a pass-gate circuit model */ - if (SPICE_MODEL_PASSGATE == model_type(model_id)) { - return model_ids_[model_id]; - } - - /* Otherwise, we need to make sure this circuit model contains a pass-gate */ - CircuitModelId pgl_model_id = pass_gate_logic_model_ids_[model_id]; - VTR_ASSERT( CircuitModelId::INVALID() != pgl_model_id ); - return pgl_model_id; -} - -/* Return the type of pass gate logic module, only applicable to circuit model whose type is pass-gate logic */ -enum e_spice_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is PASSGATE */ - VTR_ASSERT(SPICE_MODEL_PASSGATE == model_type(model_id)); - return pass_gate_logic_types_[model_id]; -} - -/* Return the type of multiplexing structure of a circuit model */ -enum e_spice_model_structure CircuitLibrary::mux_structure(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) - || (SPICE_MODEL_LUT == model_type(model_id)) ); - return mux_structure_[model_id]; -} - -/* Return the number of levels of multiplexing structure of a circuit model */ -size_t CircuitLibrary::mux_num_levels(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) - || (SPICE_MODEL_LUT == model_type(model_id)) ); - - return mux_num_levels_[model_id]; -} - -/* Return if additional constant inputs are required for a circuit model - * Only applicable for MUX/LUT circuit model - */ -bool CircuitLibrary::mux_add_const_input(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) - || (SPICE_MODEL_LUT == model_type(model_id)) ); - /* A -1 value for the const values means there is no const inputs */ - return ( size_t(-1) != mux_const_input_values_[model_id] ); -} - -/* Return if additional constant inputs are required for a circuit model - * Only applicable for MUX/LUT circuit model - */ -size_t CircuitLibrary::mux_const_input_value(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) - || (SPICE_MODEL_LUT == model_type(model_id)) ); - /* A -1 value for the const values means there is no const inputs */ - /* A 0 value for the const values means it is logic 0 */ - /* A 1 value for the const values means it is logic 1 */ - return mux_const_input_values_[model_id]; -} - -/* Return if local encoders are used for a circuit model - * Only applicable for MUX/LUT circuit model - */ -bool CircuitLibrary::mux_use_local_encoder(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) - || (SPICE_MODEL_LUT == model_type(model_id)) ); - return mux_use_local_encoder_[model_id]; -} - -/* Return the type of gate for a circuit model - * Only applicable for GATE circuit model - */ -enum e_spice_model_gate_type CircuitLibrary::gate_type(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is MUX */ - VTR_ASSERT(SPICE_MODEL_GATE == model_type(model_id)); - return gate_types_[model_id]; -} - -/* Return the type of buffer for a circuit model - * Only applicable for BUF/INV circuit model - */ -enum e_spice_model_buffer_type CircuitLibrary::buffer_type(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is MUX */ - VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); - return buffer_types_[model_id]; -} - -/* Return the number of levels of buffer for a circuit model - * Only applicable for BUF/INV circuit model - */ -size_t CircuitLibrary::buffer_num_levels(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate the circuit model type is BUF */ - VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); - return buffer_num_levels_[model_id]; -} - -/* Find the circuit model id of the input buffer of a circuit model */ -CircuitModelId CircuitLibrary::input_buffer_model(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* INPUT buffer may not always exist */ - if (INPUT < buffer_existence_[model_id].size()) { - return buffer_model_ids_[model_id][INPUT]; - } else { - return CircuitModelId::INVALID(); - } -} - -/* Find the circuit model id of the output buffer of a circuit model */ -CircuitModelId CircuitLibrary::output_buffer_model(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* OUTPUT buffer may not always exist */ - if (OUTPUT < buffer_existence_[model_id].size()) { - return buffer_model_ids_[model_id][OUTPUT]; - } else { - return CircuitModelId::INVALID(); - } -} - -/* Return the number of levels of delay types for a circuit model */ -size_t CircuitLibrary::num_delay_info(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return delay_types_[model_id].size(); -} - -/************************************************************************ - * Public Accessors : Basic data query on Circuit models' Circuit Port - ***********************************************************************/ - -/* Given a name and return the port id */ -CircuitPortId CircuitLibrary::model_port(const CircuitModelId& model_id, const std::string& name) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Walk through the ports and try to find a matched name */ - CircuitPortId ret = CircuitPortId::INVALID(); - size_t num_found = 0; - for (auto model_ports_by_type : model_port_lookup_[model_id]) { - for (auto port_id : model_ports_by_type) { - if (0 != name.compare(port_prefix(port_id))) { - continue; /* Not the one, go to the next*/ - } - ret = port_id; /* Find one */ - num_found++; - } - } - /* Make sure we will not find two ports with the same name */ - VTR_ASSERT( (0 == num_found) || (1 == num_found) ); - return ret; -} - -/* Access the type of a port of a circuit model */ -size_t CircuitLibrary::num_model_ports(const CircuitModelId& model_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Search the port look up and return a list */ - size_t num_of_ports = 0; - for (auto model_ports_by_type : model_port_lookup_[model_id]) { - num_of_ports += model_ports_by_type.size(); - } - return num_of_ports; -} - -/* Access the type of a port of a circuit model - * with an option to include/exclude global ports - * when counting - */ -size_t CircuitLibrary::num_model_ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& port_type, - const bool& include_global_port) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Search the port look up */ - VTR_ASSERT(port_type < model_port_lookup_[model_id].size()); - size_t num_ports = 0; - for (auto port : model_port_lookup_[model_id][port_type]) { - /* By pass non-global ports if required by user */ - if ( (false == include_global_port) - && (true == port_is_global(port)) ) { - continue; - } - num_ports++; - } - - return num_ports; -} - -/* Find all the ports belong to a circuit model */ -std::vector CircuitLibrary::model_ports(const CircuitModelId& model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Search the port look up and return a list */ - std::vector port_ids; - for (auto model_ports_by_type : model_port_lookup_[model_id]) { - for (auto port_id : model_ports_by_type) { - port_ids.push_back(port_id); - } - } - return port_ids; -} - -/* Recursively find all the global ports in the circuit model / sub circuit_model */ -std::vector CircuitLibrary::model_global_ports(const CircuitModelId& model_id, - const bool& recursive) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - - std::vector global_ports; - - /* Search all the ports */ - for (auto port : model_ports(model_id)) { - /* By pass non-global ports*/ - if (false == port_is_global(port)) { - continue; - } - /* This is a global port, update global_ports */ - global_ports.push_back(port); - } - - /* Finish, if we do not need to go recursively */ - if (false == recursive) { - return global_ports; - } - - /* If go recursively, we search all the buffer/pass-gate circuit model ids */ - /* Go search every sub circuit model included the current circuit model */ - for (const auto& sub_model : sub_models_[model_id]) { - std::vector sub_global_ports = model_global_ports(sub_model, recursive); - for (const auto& sub_global_port : sub_global_ports) { - /* Add to global_ports, if it is not already found in the list */ - bool add_to_list = true; - for (const auto& global_port : global_ports) { - if (0 == port_prefix(sub_global_port).compare(port_prefix(global_port))) { - /* Same name, skip list update */ - add_to_list = false; - break; - } - } - if (true == add_to_list) { - /* Add the sub_global_port to the list */ - global_ports.push_back(sub_global_port); - } - } - } - - return global_ports; -} - -/* Recursively find all the global ports in the circuit model / sub circuit_model */ -std::vector CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& type, - const bool& recursive, - const std::vector& ignore_model_types) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - - /* Search all the ports */ - std::vector global_ports; - for (auto port : model_ports(model_id)) { - /* By pass non-global ports*/ - if (false == port_is_global(port)) { - continue; - } - /* We skip unmatched ports */ - if ( type != port_type(port) ) { - continue; - } - /* This is a global port, update global_ports */ - global_ports.push_back(port); - } - - /* Finish, if we do not need to go recursively */ - if (false == recursive) { - return global_ports; - } - - /* If go recursively, we search all the buffer/pass-gate circuit model ids */ - /* Go search every sub circuit model included the current circuit model */ - for (const auto& sub_model : sub_models_[model_id]) { - /* Bypass this sub model if user specified an ignore list */ - bool ignore = false; - for (const auto& ignore_model_type : ignore_model_types) { - if (ignore_model_type != model_type(sub_model)) { - continue; - } - ignore = true; - break; - } - if (true == ignore) { - continue; - } - - /* Now we can add global ports */ - std::vector sub_global_ports = model_global_ports_by_type(sub_model, type, recursive, ignore_model_types); - for (const auto& sub_global_port : sub_global_ports) { - /* Add to global_ports, if it is not already found in the list */ - bool add_to_list = true; - for (const auto& global_port : global_ports) { - if (0 == port_prefix(sub_global_port).compare(port_prefix(global_port))) { - /* Same name, skip list update */ - add_to_list = false; - break; - } - } - if (true == add_to_list) { - /* Add the sub_global_port to the list */ - global_ports.push_back(sub_global_port); - } - } - } - - return global_ports; -} - - -/* Recursively find all the global ports in the circuit model / sub circuit_model - * whose port type matches users' specification - */ -std::vector CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id, - const std::vector& types, - const bool& recursive, - const bool& ignore_config_memories) const { - std::vector global_ports; - std::vector ignore_list; - - for (const auto& port_type : types) { - std::vector global_port_by_type = model_global_ports_by_type(model_id, port_type, recursive, ignore_config_memories); - /* Insert the vector to the final global_ports */ - global_ports.insert(global_ports.begin(), global_port_by_type.begin(), global_port_by_type.end()); - } - return global_ports; -} - -/* Recursively find all the global ports in the circuit model / sub circuit_model - * but ignore all the SRAM and CCFF, which are configuration memories - */ -std::vector CircuitLibrary::model_global_ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& type, - const bool& recursive, - const bool& ignore_config_memories) const { - std::vector ignore_list; - if (true == ignore_config_memories) { - ignore_list.push_back(SPICE_MODEL_SRAM); - ignore_list.push_back(SPICE_MODEL_CCFF); - } - return model_global_ports_by_type(model_id, type, recursive, ignore_list); -} - -/* Find the ports of a circuit model by a given type, return a list of qualified ports */ -std::vector CircuitLibrary::model_ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& type) const { - std::vector port_ids; - for (const auto& port_id : model_ports(model_id)) { - /* We skip unmatched ports */ - if ( type != port_type(port_id) ) { - continue; - } - port_ids.push_back(port_id); - } - return port_ids; -} - -/* Find the ports of a circuit model by a given type, return a list of qualified ports - * with an option to include/exclude global ports - */ -std::vector CircuitLibrary::model_ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& type, - const bool& ignore_global_port) const { - std::vector port_ids; - for (const auto& port_id : model_port_lookup_[model_id][type]) { - /* We skip unmatched ports */ - if ( type != port_type(port_id) ) { - continue; - } - /* We skip global ports if specified */ - if ( (true == ignore_global_port) - && (true == port_is_global(port_id)) ) { - continue; - } - port_ids.push_back(port_id); - } - return port_ids; -} - -/* Create a vector for all the ports whose directionality is input - * This includes all the ports other than whose types are OUPUT or INOUT - */ -std::vector CircuitLibrary::model_input_ports(const CircuitModelId& model_id) const { - std::vector input_ports; - for (const auto& port_id : model_ports(model_id)) { - /* We skip output ports */ - if ( false == is_input_port(port_id) ) { - continue; - } - input_ports.push_back(port_id); - } - return input_ports; -} - -/* Create a vector for all the ports whose directionality is output - * This includes all the ports whose types are OUPUT or INOUT - */ -std::vector CircuitLibrary::model_output_ports(const CircuitModelId& model_id) const { - std::vector output_ports; - for (const auto& port_id : model_ports(model_id)) { - /* We skip input ports */ - if ( false == is_output_port(port_id) ) { - continue; - } - output_ports.push_back(port_id); - } - return output_ports; -} - -/* Create a vector for the pin indices, which is bounded by the size of a port - * Start from 0 and end to port_size - 1 - */ -std::vector CircuitLibrary::pins(const CircuitPortId& circuit_port_id) const { - std::vector pin_range(port_size(circuit_port_id)); - /* Create a vector, with sequentially increasing numbers */ - std::iota(pin_range.begin(), pin_range.end(), 0); - return pin_range; -} - - -/************************************************************************ - * Public Accessors : Basic data query on Circuit Port - ***********************************************************************/ - -/* identify if this port is an input port */ -bool CircuitLibrary::is_input_port(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ - return ( (SPICE_MODEL_PORT_OUTPUT != port_type(circuit_port_id)) - && (SPICE_MODEL_PORT_INOUT != port_type(circuit_port_id)) ); -} - -/* identify if this port is an output port */ -bool CircuitLibrary::is_output_port(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ - return ( (SPICE_MODEL_PORT_OUTPUT == port_type(circuit_port_id)) - || (SPICE_MODEL_PORT_INOUT == port_type(circuit_port_id)) ); -} - -/* Access the type of a port of a circuit model */ -enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_types_[circuit_port_id]; -} - -/* Access the type of a port of a circuit model */ -size_t CircuitLibrary::port_size(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_sizes_[circuit_port_id]; -} - -/* Access the prefix of a port of a circuit model */ -std::string CircuitLibrary::port_prefix(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_prefix_[circuit_port_id]; -} - -/* Access the lib_name of a port of a circuit model */ -std::string CircuitLibrary::port_lib_name(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_lib_names_[circuit_port_id]; -} - -/* Access the inv_prefix of a port of a circuit model */ -std::string CircuitLibrary::port_inv_prefix(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_inv_prefix_[circuit_port_id]; -} - -/* Return the default value of a port of a circuit model */ -size_t CircuitLibrary::port_default_value(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_default_values_[circuit_port_id]; -} - -/* Return a flag if the port is used in mode-selection purpuse of a circuit model */ -bool CircuitLibrary::port_is_io(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_is_io_[circuit_port_id]; -} - -/* Return a flag if the port is used in mode-selection purpuse of a circuit model */ -bool CircuitLibrary::port_is_mode_select(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_is_mode_select_[circuit_port_id]; -} - -/* Return a flag if the port is a global one of a circuit model */ -bool CircuitLibrary::port_is_global(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_is_global_[circuit_port_id]; -} - -/* Return a flag if the port does a reset functionality in a circuit model */ -bool CircuitLibrary::port_is_reset(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_is_reset_[circuit_port_id]; -} - -/* Return a flag if the port does a set functionality in a circuit model */ -bool CircuitLibrary::port_is_set(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_is_set_[circuit_port_id]; -} - -/* Return a flag if the port enables a configuration in a circuit model */ -bool CircuitLibrary::port_is_config_enable(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_is_config_enable_[circuit_port_id]; -} - -/* Return a flag if the port is used during programming a FPGA in a circuit model */ -bool CircuitLibrary::port_is_prog(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_is_prog_[circuit_port_id]; -} - -/* Return which level the output port locates at a LUT multiplexing structure */ -size_t CircuitLibrary::port_lut_frac_level(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_lut_frac_level_[circuit_port_id]; -} - -/* Return indices of internal nodes in a LUT multiplexing structure to which the output port is wired to */ -std::vector CircuitLibrary::port_lut_output_masks(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_lut_output_masks_[circuit_port_id]; -} - -/* Return tri-state map of a port */ -std::string CircuitLibrary::port_tri_state_map(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_tri_state_maps_[circuit_port_id]; -} - -/* Return circuit model id which is used to tri-state a port */ -CircuitModelId CircuitLibrary::port_tri_state_model(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_tri_state_model_ids_[circuit_port_id]; -} - -/* Return circuit model name which is used to tri-state a port */ -std::string CircuitLibrary::port_tri_state_model_name(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_tri_state_model_names_[circuit_port_id]; -} - -/* Return the id of parent circuit model for a circuit port */ -CircuitModelId CircuitLibrary::port_parent_model(const CircuitPortId& circuit_port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return port_model_ids_[circuit_port_id]; -} - -/* Return the name of parent circuit model for a circuit port */ -std::string CircuitLibrary::model_name(const CircuitPortId& port_id) const { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(port_id)); - return model_names_[port_parent_model(port_id)]; -} - -/************************************************************************ - * Public Accessors : Methods to visit timing graphs - ***********************************************************************/ -/* Find all the edges belonging to a circuit model */ -std::vector CircuitLibrary::timing_edges_by_model(const CircuitModelId& model_id) const { - /* Validate the model id */ - VTR_ASSERT_SAFE(valid_model_id(model_id)); - - std::vector model_edges; - for (const auto& edge : edge_ids_) { - /* Bypass edges whose parent is not the model_id */ - if (model_id != edge_parent_model_ids_[edge]) { - continue; - } - /* Update the edge list */ - model_edges.push_back(edge); - } - return model_edges; -} - -/* Get source/sink nodes and delay of edges */ -CircuitPortId CircuitLibrary::timing_edge_src_port(const CircuitEdgeId& edge) const { - /* Validate the edge id */ - VTR_ASSERT_SAFE(valid_edge_id(edge)); - return edge_src_port_ids_[edge]; -} - -size_t CircuitLibrary::timing_edge_src_pin(const CircuitEdgeId& edge) const { - /* Validate the edge id */ - VTR_ASSERT_SAFE(valid_edge_id(edge)); - return edge_src_pin_ids_[edge]; -} - -CircuitPortId CircuitLibrary::timing_edge_sink_port(const CircuitEdgeId& edge) const { - /* Validate the edge id */ - VTR_ASSERT_SAFE(valid_edge_id(edge)); - return edge_sink_port_ids_[edge]; -} - -size_t CircuitLibrary::timing_edge_sink_pin(const CircuitEdgeId& edge) const { - /* Validate the edge id */ - VTR_ASSERT_SAFE(valid_edge_id(edge)); - return edge_sink_pin_ids_[edge]; -} - -float CircuitLibrary::timing_edge_delay(const CircuitEdgeId& edge, const enum spice_model_delay_type& delay_type) const { - /* Validate the edge id */ - VTR_ASSERT_SAFE(valid_edge_id(edge)); - return edge_timing_info_[edge][delay_type]; -} - -/************************************************************************ - * Public Accessors : Methods to find circuit model - ***********************************************************************/ -/* Find a circuit model by a given name and return its id */ -CircuitModelId CircuitLibrary::model(const char* name) const { - std::string name_str(name); - return model(name_str); -} - -/* Find a circuit model by a given name and return its id */ -CircuitModelId CircuitLibrary::model(const std::string& name) const { - CircuitModelId ret = CircuitModelId::INVALID(); - size_t num_found = 0; - for (circuit_model_string_iterator it = model_names_.begin(); - it != model_names_.end(); - it++) { - /* Bypass unmatched names */ - if ( 0 != name.compare(*it) ) { - continue; - } - /* Find one and record it - * FIXME: I feel that we may have a better way in getting the CircuitModelId - */ - ret = CircuitModelId(it - model_names_.begin()); - num_found++; - } - VTR_ASSERT((0 == num_found) || (1 == num_found)); - return ret; -} - -/* Get the CircuitModelId of a default circuit model with a given type */ -CircuitModelId CircuitLibrary::default_model(const enum e_spice_model_type& type) const { - /* Default circuit model id is the first element by type in the fast look-up */ - CircuitModelId default_id = model_lookup_[size_t(type)].front(); - VTR_ASSERT(true == model_is_default(default_id)); - return default_id; -} - -/************************************************************************ - * Public Accessors: Timing graph - ***********************************************************************/ -/* Given the source and sink port information, find the edge connecting the two ports */ -CircuitEdgeId CircuitLibrary::edge(const CircuitPortId& from_port, const size_t from_pin, - const CircuitPortId& to_port, const size_t to_pin) { - /* validate the circuit_pin_id */ - VTR_ASSERT(valid_circuit_pin_id(from_port, from_pin)); - VTR_ASSERT(valid_circuit_pin_id(to_port, to_pin)); - /* Walk through the edge list until we find the one */ - for (auto edge : edge_ids_) { - if ( (from_port == edge_src_port_ids_[edge]) - && (from_pin == edge_src_pin_ids_[edge]) - && (to_port == edge_sink_port_ids_[edge]) - && (to_pin == edge_sink_pin_ids_[edge]) ) { - return edge; - } - } - /* Reach here it means we find nothing! */ - return CircuitEdgeId::INVALID(); -} - -/************************************************************************ - * Public Mutators - ***********************************************************************/ -/* Add a circuit model to the library, and return it Id */ -CircuitModelId CircuitLibrary::add_model(const enum e_spice_model_type& type) { - /* Create a new id*/ - CircuitModelId model_id = CircuitModelId(model_ids_.size()); - /* Update the id list */ - model_ids_.push_back(model_id); - - /* Initialize other attributes */ - /* Fundamental information */ - model_types_.push_back(type); - model_names_.emplace_back(); - model_prefix_.emplace_back(); - model_verilog_netlists_.emplace_back(); - model_spice_netlists_.emplace_back(); - model_is_default_.push_back(false); - sub_models_.emplace_back(); - - /* Verilog generator options */ - dump_structural_verilog_.push_back(false); - dump_explicit_port_map_.push_back(false); - - /* Design technology information */ - design_tech_types_.push_back(NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES); - is_power_gated_.push_back(false); - - /* Buffer existence */ - buffer_existence_.emplace_back(); - buffer_model_names_.emplace_back(); - buffer_model_ids_.emplace_back(); - buffer_location_maps_.emplace_back(); - - /* Pass-gate-related parameters */ - pass_gate_logic_model_names_.emplace_back(); - pass_gate_logic_model_ids_.emplace_back(); - - /* Delay information */ - delay_types_.emplace_back(); - delay_in_port_names_.emplace_back(); - delay_out_port_names_.emplace_back(); - delay_values_.emplace_back(); - - /* Buffer/Inverter-related parameters */ - buffer_types_.push_back(NUM_CIRCUIT_MODEL_BUF_TYPES); - buffer_sizes_.push_back(-1); - buffer_num_levels_.push_back(-1); - buffer_f_per_stage_.push_back(-1); - - /* Pass-gate-related parameters */ - pass_gate_logic_types_.push_back(NUM_CIRCUIT_MODEL_PASS_GATE_TYPES); - pass_gate_logic_sizes_.emplace_back(); - - /* Multiplexer-related parameters */ - mux_structure_.push_back(NUM_CIRCUIT_MODEL_STRUCTURE_TYPES); - mux_num_levels_.push_back(-1); - mux_const_input_values_.push_back(-1); - mux_use_local_encoder_.push_back(false); - mux_use_advanced_rram_design_.push_back(false); - - /* LUT-related parameters */ - lut_is_fracturable_.push_back(false); - - /* Gate-related parameters */ - gate_types_.push_back(NUM_SPICE_MODEL_GATE_TYPES); - - /* RRAM-related design technology information */ - rram_res_.emplace_back(); - wprog_set_.emplace_back(); - wprog_reset_.emplace_back(); - - /* Wire parameters */ - wire_types_.push_back(NUM_WIRE_MODEL_TYPES); - wire_rc_.emplace_back(); - wire_num_levels_.push_back(-1); - - /* Build the fast look-up for circuit models */ - build_model_lookup(); - - return model_id; -} - -/* Set the name of a Circuit Model */ -void CircuitLibrary::set_model_name(const CircuitModelId& model_id, const std::string& name) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - model_names_[model_id] = name; - return; -} - -/* Set the prefix of a Circuit Model */ -void CircuitLibrary::set_model_prefix(const CircuitModelId& model_id, const std::string& prefix) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - model_prefix_[model_id] = prefix; - return; -} - -/* Set the verilog_netlist of a Circuit Model */ -void CircuitLibrary::set_model_verilog_netlist(const CircuitModelId& model_id, const std::string& verilog_netlist) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - model_verilog_netlists_[model_id] = verilog_netlist; - return; -} - -/* Set the spice_netlist of a Circuit Model */ -void CircuitLibrary::set_model_spice_netlist(const CircuitModelId& model_id, const std::string& spice_netlist) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - model_spice_netlists_[model_id] = spice_netlist; - return; -} - -/* Set the is_default of a Circuit Model */ -void CircuitLibrary::set_model_is_default(const CircuitModelId& model_id, const bool& is_default) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - model_is_default_[model_id] = is_default; - return; -} - -/* Set the dump_structural_verilog of a Circuit Model */ -void CircuitLibrary::set_model_dump_structural_verilog(const CircuitModelId& model_id, const bool& dump_structural_verilog) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - dump_structural_verilog_[model_id] = dump_structural_verilog; - return; -} - -/* Set the dump_explicit_port_map of a Circuit Model */ -void CircuitLibrary::set_model_dump_explicit_port_map(const CircuitModelId& model_id, const bool& dump_explicit_port_map) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - dump_explicit_port_map_[model_id] = dump_explicit_port_map; - return; -} - -/* Set the type of design technology of a Circuit Model */ -void CircuitLibrary::set_model_design_tech_type(const CircuitModelId& model_id, const enum e_spice_model_design_tech& design_tech_type) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - design_tech_types_[model_id] = design_tech_type; - return; -} - -/* Set the power-gated flag of a Circuit Model */ -void CircuitLibrary::set_model_is_power_gated(const CircuitModelId& model_id, const bool& is_power_gated) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - is_power_gated_[model_id] = is_power_gated; - return; -} - -/* Set input buffer information for the circuit model */ -void CircuitLibrary::set_model_input_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name) { - /* Just call the base function and give the proper type */ - set_model_buffer(model_id, INPUT, existence, model_name); - return; -} - -/* Set output buffer information for the circuit model */ -void CircuitLibrary::set_model_output_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name) { - /* Just call the base function and give the proper type */ - set_model_buffer(model_id, OUTPUT, existence, model_name); - return; -} - -/* Set input buffer information for the circuit model, only applicable to LUTs! */ -void CircuitLibrary::set_model_lut_input_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Make sure the circuit model is a LUT! */ - VTR_ASSERT(SPICE_MODEL_LUT == model_types_[model_id]); - /* Just call the base function and give the proper type */ - set_model_buffer(model_id, LUT_INPUT_BUFFER, existence, model_name); - return; -} - -/* Set input inverter information for the circuit model, only applicable to LUTs! */ -void CircuitLibrary::set_model_lut_input_inverter(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Make sure the circuit model is a LUT! */ - VTR_ASSERT(SPICE_MODEL_LUT == model_types_[model_id]); - /* Just call the base function and give the proper type */ - set_model_buffer(model_id, LUT_INPUT_INVERTER, existence, model_name); - return; -} - -/* Set intermediate buffer information for the circuit model, only applicable to LUTs! */ -void CircuitLibrary::set_model_lut_intermediate_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Make sure the circuit model is a LUT! */ - VTR_ASSERT(SPICE_MODEL_LUT == model_types_[model_id]); - /* Just call the base function and give the proper type */ - set_model_buffer(model_id, LUT_INTER_BUFFER, existence, model_name); - return; -} - -void CircuitLibrary::set_model_lut_intermediate_buffer_location_map(const CircuitModelId& model_id, - const std::string& location_map) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - buffer_location_maps_[model_id][LUT_INTER_BUFFER] = location_map; - return; -} - - -/* Set pass-gate logic information of a circuit model */ -void CircuitLibrary::set_model_pass_gate_logic(const CircuitModelId& model_id, const std::string& model_name) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - pass_gate_logic_model_names_[model_id] = model_name; - return; -} - -/* Add a port to a circuit model */ -CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id, - const enum e_spice_model_port_type& port_type) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Create a port id */ - CircuitPortId circuit_port_id = CircuitPortId(port_ids_.size()); - /* Update the id list */ - port_ids_.push_back(circuit_port_id); - - /* Initialize other attributes */ - port_model_ids_.push_back(model_id); - port_types_.push_back(port_type); - port_sizes_.push_back(-1); - port_prefix_.emplace_back(); - port_lib_names_.emplace_back(); - port_inv_prefix_.emplace_back(); - port_default_values_.push_back(-1); - port_is_io_.push_back(false); - port_is_mode_select_.push_back(false); - port_is_global_.push_back(false); - port_is_reset_.push_back(false); - port_is_set_.push_back(false); - port_is_config_enable_.push_back(false); - port_is_prog_.push_back(false); - port_tri_state_model_names_.emplace_back(); - port_tri_state_model_ids_.push_back(CircuitModelId::INVALID()); - port_inv_model_names_.emplace_back(); - port_inv_model_ids_.push_back(CircuitModelId::INVALID()); - port_tri_state_maps_.emplace_back(); - port_lut_frac_level_.push_back(-1); - port_lut_output_masks_.emplace_back(); - port_sram_orgz_.push_back(NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES); - - /* For timing graphs */ - port_in_edge_ids_.emplace_back(); - port_out_edge_ids_.emplace_back(); - - /* Build the fast look-up for circuit model ports */ - build_model_port_lookup(); - - return circuit_port_id; -} - -/* Set the size for a port of a circuit model */ -void CircuitLibrary::set_port_size(const CircuitPortId& circuit_port_id, - const size_t& port_size) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_sizes_[circuit_port_id] = port_size; - return; -} - -/* Set the prefix for a port of a circuit model */ -void CircuitLibrary::set_port_prefix(const CircuitPortId& circuit_port_id, - const std::string& port_prefix) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_prefix_[circuit_port_id] = port_prefix; - return; -} - -/* Set the lib_name for a port of a circuit model */ -void CircuitLibrary::set_port_lib_name(const CircuitPortId& circuit_port_id, - const std::string& lib_name) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_lib_names_[circuit_port_id] = lib_name; - return; -} - -/* Set the inv_prefix for a port of a circuit model */ -void CircuitLibrary::set_port_inv_prefix(const CircuitPortId& circuit_port_id, - const std::string& inv_prefix) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_inv_prefix_[circuit_port_id] = inv_prefix; - return; -} - -/* Set the default value for a port of a circuit model */ -void CircuitLibrary::set_port_default_value(const CircuitPortId& circuit_port_id, - const size_t& default_value) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_default_values_[circuit_port_id] = default_value; - return; -} - -/* Set the is_mode_select for a port of a circuit model */ -void CircuitLibrary::set_port_is_io(const CircuitPortId& circuit_port_id, - const bool& is_io) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_is_io_[circuit_port_id] = is_io; - return; -} - -/* Set the is_mode_select for a port of a circuit model */ -void CircuitLibrary::set_port_is_mode_select(const CircuitPortId& circuit_port_id, - const bool& is_mode_select) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_is_mode_select_[circuit_port_id] = is_mode_select; - return; -} - -/* Set the is_global for a port of a circuit model */ -void CircuitLibrary::set_port_is_global(const CircuitPortId& circuit_port_id, - const bool& is_global) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_is_global_[circuit_port_id] = is_global; - return; -} - -/* Set the is_reset for a port of a circuit model */ -void CircuitLibrary::set_port_is_reset(const CircuitPortId& circuit_port_id, - const bool& is_reset) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_is_reset_[circuit_port_id] = is_reset; - return; -} - -/* Set the is_set for a port of a circuit model */ -void CircuitLibrary::set_port_is_set(const CircuitPortId& circuit_port_id, - const bool& is_set) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_is_set_[circuit_port_id] = is_set; - return; -} - -/* Set the is_config_enable for a port of a circuit model */ -void CircuitLibrary::set_port_is_config_enable(const CircuitPortId& circuit_port_id, - const bool& is_config_enable) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_is_config_enable_[circuit_port_id] = is_config_enable; - return; -} - -/* Set the is_prog for a port of a circuit model */ -void CircuitLibrary::set_port_is_prog(const CircuitPortId& circuit_port_id, - const bool& is_prog) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_is_prog_[circuit_port_id] = is_prog; - return; -} - -/* Set the model_name for a port of a circuit model */ -void CircuitLibrary::set_port_tri_state_model_name(const CircuitPortId& circuit_port_id, - const std::string& model_name) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_tri_state_model_names_[circuit_port_id] = model_name; - return; -} - -/* Set the model_id for a port of a circuit model */ -void CircuitLibrary::set_port_tri_state_model_id(const CircuitPortId& circuit_port_id, - const CircuitModelId& port_model_id) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_tri_state_model_ids_[circuit_port_id] = port_model_id; - return; -} - -/* Set the inv_model_name for a port of a circuit model */ -void CircuitLibrary::set_port_inv_model_name(const CircuitPortId& circuit_port_id, - const std::string& inv_model_name) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_inv_model_names_[circuit_port_id] = inv_model_name; - return; -} - -/* Set the inv_model_id for a port of a circuit model */ -void CircuitLibrary::set_port_inv_model_id(const CircuitPortId& circuit_port_id, - const CircuitModelId& inv_model_id) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_inv_model_ids_[circuit_port_id] = inv_model_id; - return; -} - -/* Set the tri-state map for a port of a circuit model */ -void CircuitLibrary::set_port_tri_state_map(const CircuitPortId& circuit_port_id, - const std::string& tri_state_map) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - port_tri_state_maps_[circuit_port_id] = tri_state_map; - return; -} - -/* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */ -void CircuitLibrary::set_port_lut_frac_level(const CircuitPortId& circuit_port_id, - const size_t& lut_frac_level) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - /* Make sure this is a LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == model_type(port_model_ids_[circuit_port_id])); - port_lut_frac_level_[circuit_port_id] = lut_frac_level; - return; -} - -/* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */ -void CircuitLibrary::set_port_lut_output_mask(const CircuitPortId& circuit_port_id, - const std::vector& lut_output_masks) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - /* Make sure this is a LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == model_type(port_model_ids_[circuit_port_id])); - port_lut_output_masks_[circuit_port_id] = lut_output_masks; - return; -} - -/* Set the SRAM organization for a port of a circuit model, only applicable to SRAM ports */ -void CircuitLibrary::set_port_sram_orgz(const CircuitPortId& circuit_port_id, - const enum e_sram_orgz& sram_orgz) { - /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - /* Make sure this is a SRAM port */ - VTR_ASSERT(SPICE_MODEL_PORT_SRAM == port_type(circuit_port_id)); - port_sram_orgz_[circuit_port_id] = sram_orgz; - return; -} - -/* Delay information */ -/* Add a delay info: - * Check if the delay type is in the range of vector - * if yes, assign values - * if no, resize and assign values - */ -void CircuitLibrary::add_delay_info(const CircuitModelId& model_id, - const enum spice_model_delay_type& delay_type) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Check the range of vector */ - if (size_t(delay_type) >= delay_types_[model_id].size()) { - /* Resize */ - delay_types_[model_id].resize(size_t(delay_type) + 1); - delay_in_port_names_[model_id].resize(size_t(delay_type) + 1); - delay_out_port_names_[model_id].resize(size_t(delay_type) + 1); - delay_values_[model_id].resize(size_t(delay_type) + 1); - } - delay_types_[model_id][size_t(delay_type)] = delay_type; - return; -} - -void CircuitLibrary::set_delay_in_port_names(const CircuitModelId& model_id, - const enum spice_model_delay_type& delay_type, - const std::string& in_port_names) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Validate delay_type */ - VTR_ASSERT(valid_delay_type(model_id, delay_type)); - delay_in_port_names_[model_id][size_t(delay_type)] = in_port_names; - return; -} - -void CircuitLibrary::set_delay_out_port_names(const CircuitModelId& model_id, - const enum spice_model_delay_type& delay_type, - const std::string& out_port_names) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Validate delay_type */ - VTR_ASSERT(valid_delay_type(model_id, delay_type)); - delay_out_port_names_[model_id][size_t(delay_type)] = out_port_names; - return; -} - -void CircuitLibrary::set_delay_values(const CircuitModelId& model_id, - const enum spice_model_delay_type& delay_type, - const std::string& delay_values) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Validate delay_type */ - VTR_ASSERT(valid_delay_type(model_id, delay_type)); - delay_values_[model_id][size_t(delay_type)] = delay_values; - return; -} - -/* Buffer/Inverter-related parameters */ -void CircuitLibrary::set_buffer_type(const CircuitModelId& model_id, - const enum e_spice_model_buffer_type& buffer_type) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); - buffer_types_[model_id] = buffer_type; - return; -} - -void CircuitLibrary::set_buffer_size(const CircuitModelId& model_id, - const float& buffer_size) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); - buffer_sizes_[model_id] = buffer_size; - return; -} - -void CircuitLibrary::set_buffer_num_levels(const CircuitModelId& model_id, - const size_t& num_levels) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); - buffer_num_levels_[model_id] = num_levels; - return; -} - -void CircuitLibrary::set_buffer_f_per_stage(const CircuitModelId& model_id, - const size_t& f_per_stage) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); - buffer_f_per_stage_[model_id] = f_per_stage; - return; -} - -/* Pass-gate-related parameters */ -void CircuitLibrary::set_pass_gate_logic_type(const CircuitModelId& model_id, - const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_PASSGATE == model_type(model_id)); - pass_gate_logic_types_[model_id] = pass_gate_logic_type; - return; -} - -void CircuitLibrary::set_pass_gate_logic_nmos_size(const CircuitModelId& model_id, - const float& nmos_size) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_PASSGATE == model_type(model_id)); - pass_gate_logic_sizes_[model_id].set_x(nmos_size); - return; -} - -void CircuitLibrary::set_pass_gate_logic_pmos_size(const CircuitModelId& model_id, - const float& pmos_size) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_PASSGATE == model_type(model_id)); - pass_gate_logic_sizes_[model_id].set_y(pmos_size); - return; -} - -/* Multiplexer-related parameters */ -void CircuitLibrary::set_mux_structure(const CircuitModelId& model_id, - const enum e_spice_model_structure& mux_structure) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) - || (SPICE_MODEL_LUT == model_type(model_id)) ); - mux_structure_[model_id] = mux_structure; - return; -} - -void CircuitLibrary::set_mux_num_levels(const CircuitModelId& model_id, - const size_t& num_levels) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) - || (SPICE_MODEL_LUT == model_type(model_id)) ); - mux_num_levels_[model_id] = num_levels; - return; -} - -void CircuitLibrary::set_mux_const_input_value(const CircuitModelId& model_id, - const size_t& const_input_value) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) - || (SPICE_MODEL_LUT == model_type(model_id)) ); - /* validate the const input values */ - VTR_ASSERT( valid_mux_const_input_value(const_input_value) ); - mux_const_input_values_[model_id] = const_input_value; - return; -} - -void CircuitLibrary::set_mux_use_local_encoder(const CircuitModelId& model_id, - const bool& use_local_encoder) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) - || (SPICE_MODEL_LUT == model_type(model_id)) ); - mux_use_local_encoder_[model_id] = use_local_encoder; - return; -} - -void CircuitLibrary::set_mux_use_advanced_rram_design(const CircuitModelId& model_id, - const bool& use_advanced_rram_design) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) - || (SPICE_MODEL_LUT == model_type(model_id)) ); - mux_use_advanced_rram_design_[model_id] = use_advanced_rram_design; - return; -} - -/* LUT-related parameters */ -void CircuitLibrary::set_lut_is_fracturable(const CircuitModelId& model_id, - const bool& is_fracturable) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); - lut_is_fracturable_[model_id] = is_fracturable; - return; -} - -/* Gate-related parameters */ -void CircuitLibrary::set_gate_type(const CircuitModelId& model_id, - const enum e_spice_model_gate_type& gate_type) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be GATE */ - VTR_ASSERT(SPICE_MODEL_GATE == model_type(model_id)); - gate_types_[model_id] = gate_type; - return; -} - - -/* RRAM-related design technology information */ -void CircuitLibrary::set_rram_rlrs(const CircuitModelId& model_id, - const float& rlrs) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the design_tech of this model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); - rram_res_[model_id].set_x(rlrs); - return; -} - -void CircuitLibrary::set_rram_rhrs(const CircuitModelId& model_id, - const float& rhrs) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the design_tech of this model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); - rram_res_[model_id].set_y(rhrs); - return; -} - -void CircuitLibrary::set_rram_wprog_set_nmos(const CircuitModelId& model_id, - const float& wprog_set_nmos) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the design_tech of this model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); - wprog_set_[model_id].set_x(wprog_set_nmos); - return; -} - -void CircuitLibrary::set_rram_wprog_set_pmos(const CircuitModelId& model_id, - const float& wprog_set_pmos) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the design_tech of this model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); - wprog_set_[model_id].set_y(wprog_set_pmos); - return; -} - -void CircuitLibrary::set_rram_wprog_reset_nmos(const CircuitModelId& model_id, - const float& wprog_reset_nmos) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the design_tech of this model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); - wprog_reset_[model_id].set_x(wprog_reset_nmos); - return; -} - -void CircuitLibrary::set_rram_wprog_reset_pmos(const CircuitModelId& model_id, - const float& wprog_reset_pmos) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the design_tech of this model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); - wprog_reset_[model_id].set_y(wprog_reset_pmos); - return; -} - -/* Wire parameters */ -void CircuitLibrary::set_wire_type(const CircuitModelId& model_id, - const enum e_wire_model_type& wire_type) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be WIRE or CHAN_WIRE */ - VTR_ASSERT( (SPICE_MODEL_WIRE == model_type(model_id)) - || (SPICE_MODEL_CHAN_WIRE == model_type(model_id)) ); - wire_types_[model_id] = wire_type; - return; -} - -void CircuitLibrary::set_wire_r(const CircuitModelId& model_id, - const float& r_val) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be WIRE or CHAN_WIRE */ - VTR_ASSERT( (SPICE_MODEL_WIRE == model_type(model_id)) - || (SPICE_MODEL_CHAN_WIRE == model_type(model_id)) ); - wire_rc_[model_id].set_x(r_val); - return; -} - -void CircuitLibrary::set_wire_c(const CircuitModelId& model_id, - const float& c_val) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be WIRE or CHAN_WIRE */ - VTR_ASSERT( (SPICE_MODEL_WIRE == model_type(model_id)) - || (SPICE_MODEL_CHAN_WIRE == model_type(model_id)) ); - wire_rc_[model_id].set_y(c_val); - return; -} - -void CircuitLibrary::set_wire_num_levels(const CircuitModelId& model_id, - const size_t& num_level) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* validate that the type of this model should be WIRE or CHAN_WIRE */ - VTR_ASSERT( (SPICE_MODEL_WIRE == model_type(model_id)) - || (SPICE_MODEL_CHAN_WIRE == model_type(model_id)) ); - wire_num_levels_[model_id] = num_level; - return; -} - -/************************************************************************ - * Internal Mutators: builders and linkers - ***********************************************************************/ -/* Set the information for a buffer - * For a buffer type, we check if it is in the range of vector - * If yes, just assign values - * If no, resize the vector and then assign values - */ -void CircuitLibrary::set_model_buffer(const CircuitModelId& model_id, const enum e_buffer_type buffer_type, - const bool& existence, const std::string& model_name) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Check the range of vector */ - if (size_t(buffer_type) >= buffer_existence_[model_id].size()) { - /* Resize and assign values */ - buffer_existence_[model_id].resize(size_t(buffer_type) + 1); - buffer_model_names_[model_id].resize(size_t(buffer_type) + 1); - buffer_model_ids_[model_id].resize(size_t(buffer_type) + 1); - buffer_location_maps_[model_id].resize(size_t(buffer_type) + 1); - } - /* Now we are in the range, assign values */ - buffer_existence_[model_id][size_t(buffer_type)] = existence; - buffer_model_names_[model_id][size_t(buffer_type)] = model_name; - buffer_model_ids_[model_id][size_t(buffer_type)] = CircuitModelId::INVALID(); /* Set an OPEN id here, which will be linked later */ - return; -} - -/* Link the model_id for each port of a circuit model. - * We search the inv_model_name in the CircuitLibrary and - * configure the port inv_model_id - */ -void CircuitLibrary::link_port_tri_state_model() { - /* Walk through each ports, get the port id and find the circuit model id by name */ - for (auto& port_id : ports()) { - /* Bypass empty name */ - if (true == port_tri_state_model_names_[port_id].empty()) { - continue; - } - port_tri_state_model_ids_[port_id] = model(port_tri_state_model_names_[port_id]); - } - return; -} - -/* Link the inv_model_id for each port of a circuit model. - * We search the inv_model_name in the CircuitLibrary and - * configure the port inv_model_id - */ -void CircuitLibrary::link_port_inv_model() { - /* Walk through each ports, get the port id and find the circuit model id by name */ - for (auto& port_id : ports()) { - /* Bypass empty name */ - if (true == port_inv_model_names_[port_id].empty()) { - continue; - } - port_inv_model_ids_[port_id] = model(port_inv_model_names_[port_id]); - } - return; -} - -/* Link the buffer_model - * We search the buffer_model_name in the CircuitLibrary and - * configure the buffer_model_id - */ -void CircuitLibrary::link_buffer_model(const CircuitModelId& model_id) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Get the circuit model id by name, skip those with empty names*/ - for (size_t buffer_id = 0; buffer_id < buffer_model_names_[model_id].size(); ++buffer_id) { - if (true == buffer_model_names_[model_id][buffer_id].empty()) { - return; - } - buffer_model_ids_[model_id][buffer_id] = model(buffer_model_names_[model_id][buffer_id]); - } - return; -} - -/* Link the buffer_model - * We search the buffer_model_name in the CircuitLibrary and - * configure the buffer_model_id - */ -void CircuitLibrary::link_pass_gate_logic_model(const CircuitModelId& model_id) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Get the circuit model id by name, skip those with empty names*/ - if (true == pass_gate_logic_model_names_[model_id].empty()) { - return; - } - pass_gate_logic_model_ids_[model_id] = model(pass_gate_logic_model_names_[model_id]); - return; -} - -/* Find if a model is already in the submodel list */ -bool CircuitLibrary::is_unique_submodel(const CircuitModelId& model_id, const CircuitModelId& submodel_id) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - VTR_ASSERT(valid_model_id(submodel_id)); - - std::vector::iterator it = std::find(sub_models_[model_id].begin(), sub_models_[model_id].end(), submodel_id); - if (it == sub_models_[model_id].end()) { - return true; - } - return false; -} - -/* Build the sub module list for each circuit model, - * Find the linked circuit model id in - * pass-gate, buffers, ports */ -void CircuitLibrary::build_submodels() { - for (const auto& model: models()) { - /* Make sure a clean start */ - sub_models_[model].clear(); - - /* build a list of candidates */ - std::vector candidates; - - /* Find buffer models */ - for (const auto& buffer_model : buffer_model_ids_[model]) { - /* Skip any invalid ids */ - if (CircuitModelId::INVALID() == buffer_model) { - continue; - } - candidates.push_back(buffer_model); - } - - /* Find pass-gate models */ - /* Skip any invalid ids */ - if (CircuitModelId::INVALID() != pass_gate_logic_model_ids_[model]) { - candidates.push_back(pass_gate_logic_model_ids_[model]); - } - - /* Find each port circuit models */ - for (const auto& port: model_ports(model)) { - /* Find tri-state circuit models */ - /* Skip any invalid ids */ - if (CircuitModelId::INVALID() != port_tri_state_model_ids_[port]) { - candidates.push_back(port_tri_state_model_ids_[port]); - } - /* Find inv circuit models */ - /* Skip any invalid ids */ - if (CircuitModelId::INVALID() != port_inv_model_ids_[port]) { - candidates.push_back(port_inv_model_ids_[port]); - } - } - - /* Build a unique list */ - for (const auto& cand : candidates) { - /* Make sure the model id is unique in the list */ - if (true == is_unique_submodel(model, cand)) { - sub_models_[model].push_back(cand); - } - } - } -} - -/* Build the timing graph for a circuit models*/ -void CircuitLibrary::build_model_timing_graph(const CircuitModelId& model_id) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - - /* Now we start allocating a timing graph - * Add outgoing edges for each input pin of the circuit model - */ - for (const auto& from_port_id : model_input_ports(model_id)) { - /* Add edges for each input pin */ - for (const auto& from_pin_id : pins(from_port_id)) { - /* We should walk through output pins here */ - for (const auto& to_port_id : model_output_ports(model_id)) { - for (const auto& to_pin_id : pins(to_port_id)) { - /* Skip self-loops */ - if (from_port_id == to_port_id) { - continue; - } - /* Add an edge to bridge the from_pin_id and to_pin_id */ - add_edge(model_id, from_port_id, from_pin_id, to_port_id, to_pin_id); - } - } - } - } - return; -} - -/************************************************************************ - * Public Mutators: builders and linkers - ***********************************************************************/ -/* Build the links for attributes of each model by searching the model_names */ -void CircuitLibrary::build_model_links() { - /* Walk through each circuit model, build links one by one */ - for (auto& model_id : models()) { - /* Build links for buffers, pass-gates model */ - link_buffer_model(model_id); - link_pass_gate_logic_model(model_id); - } - /* Build links for ports */ - link_port_tri_state_model(); - link_port_inv_model(); - - /* Build submodels */ - build_submodels(); - - return; -} - -/* Build the timing graph for a circuit models*/ -void CircuitLibrary::build_timing_graphs() { - /* Free the timing graph if it already exists, we will rebuild one */ - invalidate_model_timing_graph(); - /* Walk through each circuit model, build timing graph one by one */ - for (auto& model_id : models()) { - build_model_timing_graph(model_id); - /* Annotate timing information */ - set_timing_graph_delays(model_id); - } - return; -} - -/************************************************************************ - * Internal mutators: build timing graphs - ***********************************************************************/ -/* Add an edge between two pins of two ports, and assign an default timing value */ -void CircuitLibrary::add_edge(const CircuitModelId& model_id, - const CircuitPortId& from_port, const size_t& from_pin, - const CircuitPortId& to_port, const size_t& to_pin) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - - /* Create an edge in the edge id list */ - CircuitEdgeId edge_id = CircuitEdgeId(edge_ids_.size()); - /* Expand the edge list */ - edge_ids_.push_back(edge_id); - - /* Initialize other attributes */ - edge_parent_model_ids_.push_back(model_id); - - /* Update the list of incoming edges for to_port */ - /* Resize upon need */ - if (to_pin >= port_in_edge_ids_[to_port].size()) { - port_in_edge_ids_[to_port].resize(to_pin + 1); - } - port_in_edge_ids_[to_port][to_pin] = edge_id; - - /* Update the list of outgoing edges for from_port */ - /* Resize upon need */ - if (from_pin >= port_out_edge_ids_[from_port].size()) { - port_out_edge_ids_[from_port].resize(from_pin + 1); - } - port_out_edge_ids_[from_port][from_pin] = edge_id; - - /* Update source ports and pins of the edge */ - edge_src_port_ids_.push_back(from_port); - edge_src_pin_ids_.push_back(from_pin); - - /* Update sink ports and pins of the edge */ - edge_sink_port_ids_.push_back(to_port); - edge_sink_pin_ids_.push_back(to_pin); - - /* Give a default value for timing values */ - std::vector timing_info(NUM_CIRCUIT_MODEL_DELAY_TYPES, 0); - edge_timing_info_.push_back(timing_info); - - return; -} - -void CircuitLibrary::set_edge_delay(const CircuitModelId& model_id, - const CircuitEdgeId& circuit_edge_id, - const enum spice_model_delay_type& delay_type, - const float& delay_value) { - /* validate the circuit_edge_id */ - VTR_ASSERT(valid_circuit_edge_id(circuit_edge_id)); - VTR_ASSERT(valid_delay_type(model_id, delay_type)); - - edge_timing_info_[circuit_edge_id][size_t(delay_type)] = delay_value; - return; -} - -/* Annotate delay values on a timing graph */ -void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& model_id) { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - /* Go one delay_info by another */ - for (const auto& delay_type : delay_types_[model_id]) { - /* Parse the input port names and output names. - * We will store the parsing results in vectors: - * 1. vector for port ids for each port name - * 2. vector for pin ids for each port name - */ - - /* Parse the string for inputs */ - MultiPortParser input_port_parser(delay_in_port_names_[model_id][size_t(delay_type)]); - std::vector input_ports = input_port_parser.ports(); - std::vector input_port_ids; - std::vector input_pin_ids; - /* Check each element */ - for (auto& port_info : input_ports) { - /* Try to find a port by the given name */ - CircuitPortId port_id = model_port(model_id, port_info.get_name()); - /* We must have a valid port and Port width must be 1! */ - VTR_ASSERT(CircuitPortId::INVALID() != port_id); - if (0 == port_info.get_width()) { - /* we need to configure the port width if it is zero. - * This means that parser find some compact port defintion such as - */ - size_t port_width = port_size(port_id); - port_info.set_width(port_width); - } else { - VTR_ASSERT(1 == port_info.get_width()); - } - /* The pin id should be valid! */ - VTR_ASSERT(true == valid_circuit_pin_id(port_id, port_info.get_lsb())); - /* This must be an input port! */ - VTR_ASSERT(true == is_input_port(port_id)); - /* Push to */ - input_port_ids.push_back(port_id); - input_pin_ids.push_back(port_info.get_lsb()); - } - - /* Parse the string for outputs */ - MultiPortParser output_port_parser(delay_out_port_names_[model_id][size_t(delay_type)]); - std::vector output_ports = output_port_parser.ports(); - std::vector output_port_ids; - std::vector output_pin_ids; - /* Check each element */ - for (auto& port_info : output_ports) { - /* Try to find a port by the given name */ - CircuitPortId port_id = model_port(model_id, port_info.get_name()); - /* We must have a valid port and Port width must be 1! */ - VTR_ASSERT(CircuitPortId::INVALID() != port_id); - if (0 == port_info.get_width()) { - /* we need to configure the port width if it is zero. - * This means that parser find some compact port defintion such as - */ - size_t port_width = port_size(port_id); - port_info.set_width(port_width); - } else { - VTR_ASSERT(1 == port_info.get_width()); - } - /* The pin id should be valid! */ - VTR_ASSERT(true == valid_circuit_pin_id(port_id, port_info.get_lsb())); - /* This must be an output port! */ - VTR_ASSERT(true == is_output_port(port_id)); - /* Push to */ - output_port_ids.push_back(port_id); - output_pin_ids.push_back(port_info.get_lsb()); - } - - /* Parse the delay matrix */ - PortDelayParser port_delay_parser(delay_values_[model_id][size_t(delay_type)]); - - /* Make sure the delay matrix size matches */ - VTR_ASSERT(port_delay_parser.height() == output_port_ids.size()); - VTR_ASSERT(port_delay_parser.height() == output_pin_ids.size()); - VTR_ASSERT(port_delay_parser.width() == input_port_ids.size()); - VTR_ASSERT(port_delay_parser.width() == input_pin_ids.size()); - - /* Configure timing graph */ - for (size_t i = 0; i < port_delay_parser.height(); ++i) { - for (size_t j = 0; j < port_delay_parser.width(); ++j) { - float delay_value = port_delay_parser.delay(i, j); - CircuitEdgeId edge_id = edge(input_port_ids[j], input_pin_ids[j], - output_port_ids[i], output_pin_ids[i]); - /* make sure we have an valid edge_id */ - VTR_ASSERT(true == valid_circuit_edge_id(edge_id)); - set_edge_delay(model_id, edge_id, - delay_type, delay_value); - } - } - } - return; -} - -/************************************************************************ - * Internal mutators: build fast look-ups - ***********************************************************************/ -/* Build fast look-up for circuit models */ -void CircuitLibrary::build_model_lookup() { - /* invalidate fast look-up */ - invalidate_model_lookup(); - /* Classify circuit models by type */ - model_lookup_.resize(NUM_CIRCUIT_MODEL_TYPES); - /* Walk through models and categorize */ - for (auto& id : model_ids_) { - model_lookup_[model_types_[id]].push_back(id); - } - /* Make the default model to be the first element for each type */ - for (auto& type : model_lookup_) { - /* Skip zero-length parts of look-up */ - if (true == type.empty()) { - continue; - } - /* if the first element is already a default model, we skip this */ - if (true == model_is_default_[type[0]]) { - continue; - } - /* Check the array, and try to find a default model */ - for (size_t id = 0; id < type.size(); ++id) { - if (false == model_is_default_[type[id]]) { - continue; - } - /* Once we find a default model, swap with the first element and finish the loop */ - std::swap(type[0], type[id]); - break; - } - } - return; -} - -/* Build fast look-up for circuit model ports */ -void CircuitLibrary::build_model_port_lookup() { - /* For all the ports in the list, categorize by model_id and port_type */ - /* invalidate fast look-up */ - invalidate_model_port_lookup(); - /* Classify circuit models by type */ - model_port_lookup_.resize(model_ids_.size()); - for (const auto& model_id : model_ids_) { - model_port_lookup_[model_id].resize(NUM_CIRCUIT_MODEL_PORT_TYPES); - } - /* Walk through models and categorize */ - for (const auto& port : port_ids_) { - CircuitModelId model_id = port_model_ids_[port]; - model_port_lookup_[model_id][port_type(port)].push_back(port); - } - return; -} - -/************************************************************************ - * Internal invalidators/validators - ***********************************************************************/ -/* Validators */ -bool CircuitLibrary::valid_model_id(const CircuitModelId& model_id) const { - return ( size_t(model_id) < model_ids_.size() ) && ( model_id == model_ids_[model_id] ); -} - -bool CircuitLibrary::valid_circuit_port_id(const CircuitPortId& circuit_port_id) const { - return ( size_t(circuit_port_id) < port_ids_.size() ) && ( circuit_port_id == port_ids_[circuit_port_id] ); -} - -bool CircuitLibrary::valid_circuit_pin_id(const CircuitPortId& circuit_port_id, const size_t& pin_id) const { - /* validate the model_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); - return ( size_t(pin_id) < port_size(circuit_port_id) ); -} - -bool CircuitLibrary::valid_edge_id(const CircuitEdgeId& edge_id) const { - /* validate the model_id */ - return ( size_t(edge_id) < edge_ids_.size() ) && ( edge_id == edge_ids_[edge_id] ); -} - -bool CircuitLibrary::valid_delay_type(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) const { - /* validate the model_id */ - VTR_ASSERT(valid_model_id(model_id)); - return ( size_t(delay_type) < delay_types_[model_id].size() ) && ( delay_type == delay_types_[model_id][size_t(delay_type)] ); -} - -bool CircuitLibrary::valid_circuit_edge_id(const CircuitEdgeId& circuit_edge_id) const { - return ( size_t(circuit_edge_id) < edge_ids_.size() ) && ( circuit_edge_id == edge_ids_[circuit_edge_id] ); -} - -/* Validate the value of constant input - * A -1 value for the const values means there is no const inputs - * A 0 value for the const values means it is logic 0 - * A 1 value for the const values means it is logic 1 - * Others are invalid - */ -bool CircuitLibrary::valid_mux_const_input_value(const size_t& const_input_value) const { - return ( (size_t(-1) == const_input_value) - || (0 == const_input_value) - || (1 == const_input_value) ); -} - -/* Invalidators */ -/* Empty fast lookup for models*/ -void CircuitLibrary::invalidate_model_lookup() const { - model_lookup_.clear(); - return; -} - -/* Empty fast lookup for circuit ports for a model */ -void CircuitLibrary::invalidate_model_port_lookup() const { - model_port_lookup_.clear(); - return; -} - -/* Clear all the data structure related to the timing graph */ -void CircuitLibrary::invalidate_model_timing_graph() { - edge_ids_.clear(); - - for (const auto& port_id : ports()) { - port_in_edge_ids_[port_id].clear(); - port_out_edge_ids_[port_id].clear(); - } - - edge_src_port_ids_.clear(); - edge_src_pin_ids_.clear(); - - edge_sink_port_ids_.clear(); - edge_sink_pin_ids_.clear(); - - edge_timing_info_.clear(); - return; -} - -/************************************************************************ - * End of file : circuit_library.cpp - ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.h b/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.h deleted file mode 100644 index b76e2be63..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library.h +++ /dev/null @@ -1,611 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: circuit_library.h - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/08/06 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ - -/* IMPORTANT: - * The following preprocessing flags are added to - * avoid compilation error when this headers are included in more than 1 times - */ -#ifndef CIRCUIT_LIBRARY_H -#define CIRCUIT_LIBRARY_H - -/* - * Notes in include header files in a head file - * Only include the neccessary header files - * that is required by the data types in the function/class declarations! - */ -/* Header files should be included in a sequence */ -/* Standard header files required go first */ -#include - -#include "vtr_geometry.h" - -#include "vtr_vector.h" -#include "vtr_range.h" - -#include "circuit_types.h" - -#include "circuit_library_fwd.h" - -/************************************************************************ - * The class CircuitLibrary is a critical data structure for OpenFPGA - * It stores all the circuit-level details from XML architecture file - * - * It includes the following data: - * - * ------ Fundamental Information ----- - * 1. model_ids_ : unique identifier to find a circuit model - * Use a strong id for search, to avoid illegal type casting - * 2. model_types_: types of the circuit model, see details in the definition of enum e_spice_model_type - * 3. model_names_: unique names for each circuit models. - * It should be the same as user-defined Verilog modules, if it is not auto-generated - * 4. model_prefix_: the prefix of a circuit model when it is instanciated - * 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated - * 6. spice_netlist_: specified path and file name of SPICE netlist if a circuit model is not auto-generated - * 7. is_default_: indicate if the circuit model is the default one among all those in the same type - * 8. sub_models_: the sub circuit models included by a circuit model. It is a collection of unique circuit model ids - * found in the CircuitModelId of pass-gate/buffers/port-related circuit models. - * - * ------ Fast look-ups----- - * 1. model_lookup_: A multi-dimension vector to provide fast look-up on circuit models for users - * It classifies CircuitModelIds by their type and set the default model in the first element for each type. - * 2. model_port_lookup_: A multi-dimension vector to provide fast look-up on ports of circuit models for users - * It classifies Ports by their types - * - * ------ Verilog generation options ----- - * 1. dump_structural_verilog_: if Verilog generator will output structural Verilog syntax for the circuit model - * 2. dump_explicit_port_map_: if Verilog generator will use explicit port mapping when instanciate the circuit model - * - * ------ Design technology information ----- - * 1. design_tech_types_: the design technology [cmos|rram] for each circuit model - * 2. is_power_gated_: specify if the circuit model is power-gated (contain a input to turn on/off VDD and GND) - * - * ------ Buffer existence ----- - * Use vectors to simplify the defition of buffer existence: - * index (low=0 to high) represents INPUT, OUTPUT, LUT_INPUT_BUF, LUT_INPUT_INV, LUT_INTER_BUFFER - * 1. buffer_existence_: specify if this circuit model has an buffer - * 2. buffer_model_name_: specify the name of circuit model for the buffer - * 3. buffer_model_id_: specify the id of circuit model for the buffer - * - * ------ Pass-gate-related parameters ------ - * 1. pass_gate_logic_model_name_: specify the name of circuit model for the pass gate logic - * 2. pass_gate_logic_model_id_: specify the id of circuit model for the pass gate logic - * - * ------ Port information ------ - * 1. port_ids_: unique id of ports belonging to a circuit model - * 1. port_model_ids_: unique id of the parent circuit model for the port - * 2. port_types_: types of ports belonging to a circuit model - * 3. port_sizes_: width of ports belonging to a circuit model - * 4. port_prefix_: prefix of a port when instance of a circuit model - * 5. port_lib_names_: port name in the standard cell library, only used when explicit_port_mapping is enabled - * 6. port_inv_prefix_: the prefix to be added for the inverted port. This is mainly used by SRAM ports, which have an coupled inverterd port - * 7. port_is_mode_select: specify if this port is used to select operating modes of the circuit model - * 8. port_is_global: specify if this port is a global signal shared by other circuit model - * 9. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches - * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches - * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches - * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches - * 13. port_tri_state_model_name: the name of circuit model linked to tri-state the port - * 14. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port - * 15. port_inv_model_names_: the name of inverter circuit model linked to the port - * 16. port_inv_model_ids_: the Id of inverter circuit model linked to the port - * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port - * 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used - * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used - * 20. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains - * - * ------ Delay information ------ - * 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge - * 2. delay_in_port_names_: name of input ports that the pin-to-pin delay is linked to - * 3. delay_in_port_names_: name of output ports that the pin-to-pin delay is linked to - * 4. delay_values_: delay values of the pin-to-pin delay - * - * ------ Timing graph information: TODO: consider using tatum? ------ - * Timing graph is allocated when delay information is made - * 1. edge_ids_ : ids of edges in the timing graph - * 2. port_in_edge_ids_: ids of input edges for each pin of a circuit port - * 3. port_out_edge_ids_: ids of output edges for each pin of a circuit port - * 4. edge_src_port_ids_: ids of source ports that each edge is connected to - * 5. edge_src_pin_ids_: ids of source pin that each edge is connected to - * 6. edge_sink_port_ids_: ids of sink ports that each edge is connected to - * 7. edge_sink_pin_ids_: ids of sink pin that each edge is connected to - * 8. edge_trise_: rising delay of the edge - * 9. edge_tfall_: falling delay of the edge - * - * ------ Buffer/Inverter-related parameters ------ - * Note: only applicable to circuit models whose type is buffer or inverter - * 1. buffer_types_: type of the buffer, either buffer or inverter - * 2. buffer_location_maps_: location of the buffer, only applicable to LUTs - * 3. buffer_sizes_: size of buffer (transistor size for the first stage) - * 4. buffer_is_tapered_: specify if this buffer has multiple stages - * 5. buffer_num_levels: specify the number of levels of this buffer (if this is defined as multi-level buffer) - * 6. buffer_f_per_stage: specify the driving strength of the buffer by stage - * - * ------ Pass-gate-logic-related parameters ------ - * Note: only applicable to circuit models whose type is pass-gate-logic - * 1. pass_gate_logic_types_: types of the pass-gate-logic, either transmission-gate or pass-transistor - * 2. pass_gate_logic_nmos_sizes_: size of NMOS transistor in the pass-gate-logic - * 3. pass_gate_logic_pmos_sizes_: size of PMOS transistor in the pass-gate-logic, only applicable for transmission-gates - * - * ------ Multiplexer-related parameters ------ - * Note: only applicable to circuit models whose type is MUX - * 1. mux_structure_: specify the structure of a multiplexer, one-level, multi-level or tree-like - * 2. mux_num_levels_: specify the number of levels for a multiplexer - * 3. mux_add_const_input_: specify if this multiplexer has a constant input - * 4. mux_const_input_values_: specify the value of the constant input for this multiplexer (valid only when mux_add_const_input is true) - * 5. mux_use_local_encoder_: specify if the mux as a local encoder between SRAMs and multiplexing structure - * 6. mux_advanced_rram_design_: specify if the multiplexer will use advanced RRAM circuit design topology - * - * ------ LUT-related parameters ------ - * Note: only applicable to circuit models whose type is LUT - * 1. lut_is_fracturable_: specify if this LUT is built with fracturable structure - * - * ------ RRAM-related parameters ------ - * Note: only applicable to circuit models whose design technology is RRAM - * 1. rlrs: RRAM resistance in Low-Resistance State (LRS) - * 2. rhrs: RRAM resistance in High-Resistance State (HRS) - * The following transistor sizes are applicable for 4T1R programming structures - * 3. wprog_set_nmos: size of n-type programming transistor used to set a RRAM - * 4. wprog_set_pmos: size of p-type programming transistor used to set a RRAM - * 5. wprog_reset_nmos: size of n-type programming transistor used to reset a RRAM - * 6. wprog_reset_pmos: size of p-type programming transistor used to reset a RRAM - * - * ------ Metal wire-related parameters ------ - * Note: only applicable to circuit models whose type is wires or channel wires - * 1. wire_types_: types of the metal wire for the model - * 2. wire_res_val_: resistance value of the metal wire for the circuit model - * 3. wire_cap_val_: capacitance value of the metal wire for the circuit model - * 4. wire_num_levels_: number of levels of the metal wire model for the circuit model - ***********************************************************************/ -class CircuitLibrary { - public: /* Types */ - typedef vtr::vector::const_iterator circuit_model_iterator; - typedef vtr::vector::const_iterator circuit_model_string_iterator; - typedef vtr::vector::const_iterator circuit_port_iterator; - typedef vtr::vector::const_iterator circuit_edge_iterator; - /* Create range */ - typedef vtr::Range circuit_model_range; - typedef vtr::Range circuit_port_range; - typedef vtr::Range circuit_edge_range; - /* local enumeration for buffer existence */ - enum e_buffer_type: unsigned char{ - INPUT = 0, OUTPUT, LUT_INPUT_BUFFER, LUT_INPUT_INVERTER, LUT_INTER_BUFFER, NUM_BUFFER_TYPE /* Last one is a counter */ - }; - public: /* Constructors */ - CircuitLibrary(); - public: /* Accessors: aggregates */ - circuit_model_range models() const; - circuit_port_range ports() const; - std::vector models_by_type(const enum e_spice_model_type& type) const; - public: /* Public Accessors: Basic data query on Circuit Models*/ - size_t num_models() const; - enum e_spice_model_type model_type(const CircuitModelId& model_id) const; - std::string model_name(const CircuitModelId& model_id) const; - std::string model_prefix(const CircuitModelId& model_id) const; - std::string model_verilog_netlist(const CircuitModelId& model_id) const; - std::string model_spice_netlist(const CircuitModelId& model_id) const; - bool model_is_default(const CircuitModelId& model_id) const; - bool dump_structural_verilog(const CircuitModelId& model_id) const; - bool dump_explicit_port_map(const CircuitModelId& model_id) const; - enum e_spice_model_design_tech design_tech_type(const CircuitModelId& model_id) const; - bool is_power_gated(const CircuitModelId& model_id) const; - /* General buffer information */ - bool is_input_buffered(const CircuitModelId& model_id) const; - bool is_output_buffered(const CircuitModelId& model_id) const; - /* LUT-related information */ - bool is_lut_intermediate_buffered(const CircuitModelId& model_id) const; - bool is_lut_fracturable(const CircuitModelId& model_id) const; - CircuitModelId lut_input_buffer_model(const CircuitModelId& model_id) const; - CircuitModelId lut_input_inverter_model(const CircuitModelId& model_id) const; - CircuitModelId lut_intermediate_buffer_model(const CircuitModelId& model_id) const; - std::string lut_intermediate_buffer_location_map(const CircuitModelId& model_id) const; - /* Pass-gate-logic information */ - CircuitModelId pass_gate_logic_model(const CircuitModelId& model_id) const; - enum e_spice_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& model_id) const; - /* Multiplexer information */ - enum e_spice_model_structure mux_structure(const CircuitModelId& model_id) const; - size_t mux_num_levels(const CircuitModelId& model_id) const; - bool mux_add_const_input(const CircuitModelId& model_id) const; - size_t mux_const_input_value(const CircuitModelId& model_id) const; - bool mux_use_local_encoder(const CircuitModelId& model_id) const; - /* Gate information */ - enum e_spice_model_gate_type gate_type(const CircuitModelId& model_id) const; - /* Buffer information */ - enum e_spice_model_buffer_type buffer_type(const CircuitModelId& model_id) const; - size_t buffer_num_levels(const CircuitModelId& model_id) const; - CircuitModelId input_buffer_model(const CircuitModelId& model_id) const; - CircuitModelId output_buffer_model(const CircuitModelId& model_id) const; - /* Delay information */ - size_t num_delay_info(const CircuitModelId& model_id) const; - public: /* Public Accessors: Basic data query on cirucit models' Circuit Ports*/ - CircuitPortId model_port(const CircuitModelId& model_id, const std::string& name) const; - size_t num_model_ports(const CircuitModelId& model_id) const; - size_t num_model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; - std::vector model_ports(const CircuitModelId& model_id) const; - std::vector model_global_ports(const CircuitModelId& model_id, const bool& recursive) const; - std::vector model_global_ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& type, - const bool& recursive, - const std::vector& ignore_model_types) const; - std::vector model_global_ports_by_type(const CircuitModelId& model_id, - const std::vector& type, - const bool& recursive, - const bool& ignore_config_memories) const; - std::vector model_global_ports_by_type(const CircuitModelId& model_id, - const enum e_spice_model_port_type& type, - const bool& recursive, - const bool& ignore_config_memories) const; - - std::vector model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type) const; - std::vector model_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; - std::vector model_input_ports(const CircuitModelId& model_id) const; - std::vector model_output_ports(const CircuitModelId& model_id) const; - std::vector pins(const CircuitPortId& circuit_port_id) const; - public: /* Public Accessors: Basic data query on Circuit Ports*/ - bool is_input_port(const CircuitPortId& circuit_port_id) const; - bool is_output_port(const CircuitPortId& circuit_port_id) const; - enum e_spice_model_port_type port_type(const CircuitPortId& circuit_port_id) const; - size_t port_size(const CircuitPortId& circuit_port_id) const; - std::string port_prefix(const CircuitPortId& circuit_port_id) const; - std::string port_lib_name(const CircuitPortId& circuit_port_id) const; - std::string port_inv_prefix(const CircuitPortId& circuit_port_id) const; - size_t port_default_value(const CircuitPortId& circuit_port_id) const; - bool port_is_io(const CircuitPortId& circuit_port_id) const; - bool port_is_mode_select(const CircuitPortId& circuit_port_id) const; - bool port_is_global(const CircuitPortId& circuit_port_id) const; - bool port_is_reset(const CircuitPortId& circuit_port_id) const; - bool port_is_set(const CircuitPortId& circuit_port_id) const; - bool port_is_config_enable(const CircuitPortId& circuit_port_id) const; - bool port_is_prog(const CircuitPortId& circuit_port_id) const; - size_t port_lut_frac_level(const CircuitPortId& circuit_port_id) const; - std::vector port_lut_output_masks(const CircuitPortId& circuit_port_id) const; - std::string port_tri_state_map(const CircuitPortId& circuit_port_id) const; - CircuitModelId port_tri_state_model(const CircuitPortId& circuit_port_id) const; - std::string port_tri_state_model_name(const CircuitPortId& circuit_port_id) const; - CircuitModelId port_parent_model(const CircuitPortId& circuit_port_id) const; - std::string model_name(const CircuitPortId& port_id) const; - public: /* Public Accessors: Timing graph */ - /* Get source/sink nodes and delay of edges */ - std::vector timing_edges_by_model(const CircuitModelId& model_id) const; - CircuitPortId timing_edge_src_port(const CircuitEdgeId& edge) const; - size_t timing_edge_src_pin(const CircuitEdgeId& edge) const; - CircuitPortId timing_edge_sink_port(const CircuitEdgeId& edge) const; - size_t timing_edge_sink_pin(const CircuitEdgeId& edge) const; - float timing_edge_delay(const CircuitEdgeId& edge, const enum spice_model_delay_type& delay_type) const; - public: /* Public Accessors: Methods to find circuit model */ - CircuitModelId model(const char* name) const; - CircuitModelId model(const std::string& name) const; - CircuitModelId default_model(const enum e_spice_model_type& type) const; - public: /* Public Accessors: Timing graph */ - CircuitEdgeId edge(const CircuitPortId& from_port, const size_t from_pin, - const CircuitPortId& to_port, const size_t to_pin); - public: /* Public Mutators */ - CircuitModelId add_model(const enum e_spice_model_type& type); - /* Fundamental information */ - void set_model_name(const CircuitModelId& model_id, const std::string& name); - void set_model_prefix(const CircuitModelId& model_id, const std::string& prefix); - void set_model_verilog_netlist(const CircuitModelId& model_id, const std::string& verilog_netlist); - void set_model_spice_netlist(const CircuitModelId& model_id, const std::string& spice_netlist); - void set_model_is_default(const CircuitModelId& model_id, const bool& is_default); - /* Verilog generator options */ - void set_model_dump_structural_verilog(const CircuitModelId& model_id, const bool& dump_structural_verilog); - void set_model_dump_explicit_port_map(const CircuitModelId& model_id, const bool& dump_explicit_port_map); - /* Design technology information */ - void set_model_design_tech_type(const CircuitModelId& model_id, const enum e_spice_model_design_tech& design_tech_type); - void set_model_is_power_gated(const CircuitModelId& model_id, const bool& is_power_gated); - /* Buffer existence */ - void set_model_input_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name); - void set_model_output_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name); - void set_model_lut_input_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name); - void set_model_lut_input_inverter(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name); - void set_model_lut_intermediate_buffer(const CircuitModelId& model_id, - const bool& existence, const std::string& model_name); - void set_model_lut_intermediate_buffer_location_map(const CircuitModelId& model_id, - const std::string& location_map); - /* Pass-gate-related parameters */ - void set_model_pass_gate_logic(const CircuitModelId& model_id, const std::string& model_name); - /* Port information */ - CircuitPortId add_model_port(const CircuitModelId& model_id, - const enum e_spice_model_port_type& port_type); - void set_port_size(const CircuitPortId& circuit_port_id, - const size_t& port_size); - void set_port_prefix(const CircuitPortId& circuit_port_id, - const std::string& port_prefix); - void set_port_lib_name(const CircuitPortId& circuit_port_id, - const std::string& lib_name); - void set_port_inv_prefix(const CircuitPortId& circuit_port_id, - const std::string& inv_prefix); - void set_port_default_value(const CircuitPortId& circuit_port_id, - const size_t& default_val); - void set_port_is_io(const CircuitPortId& circuit_port_id, - const bool& is_io); - void set_port_is_mode_select(const CircuitPortId& circuit_port_id, - const bool& is_mode_select); - void set_port_is_global(const CircuitPortId& circuit_port_id, - const bool& is_global); - void set_port_is_reset(const CircuitPortId& circuit_port_id, - const bool& is_reset); - void set_port_is_set(const CircuitPortId& circuit_port_id, - const bool& is_set); - void set_port_is_config_enable(const CircuitPortId& circuit_port_id, - const bool& is_config_enable); - void set_port_is_prog(const CircuitPortId& circuit_port_id, - const bool& is_prog); - void set_port_tri_state_model_name(const CircuitPortId& circuit_port_id, - const std::string& model_name); - void set_port_tri_state_model_id(const CircuitPortId& circuit_port_id, - const CircuitModelId& port_model_id); - void set_port_inv_model_name(const CircuitPortId& circuit_port_id, - const std::string& inv_model_name); - void set_port_inv_model_id(const CircuitPortId& circuit_port_id, - const CircuitModelId& inv_model_id); - void set_port_tri_state_map(const CircuitPortId& circuit_port_id, - const std::string& tri_state_map); - void set_port_lut_frac_level(const CircuitPortId& circuit_port_id, - const size_t& lut_frac_level); - void set_port_lut_output_mask(const CircuitPortId& circuit_port_id, - const std::vector& lut_output_masks); - void set_port_sram_orgz(const CircuitPortId& circuit_port_id, - const enum e_sram_orgz& sram_orgz); - /* Delay information */ - void add_delay_info(const CircuitModelId& model_id, - const enum spice_model_delay_type& delay_type); - void set_delay_in_port_names(const CircuitModelId& model_id, - const enum spice_model_delay_type& delay_type, - const std::string& in_port_names); - void set_delay_out_port_names(const CircuitModelId& model_id, - const enum spice_model_delay_type& delay_type, - const std::string& out_port_names); - void set_delay_values(const CircuitModelId& model_id, - const enum spice_model_delay_type& delay_type, - const std::string& delay_values); - /* Buffer/Inverter-related parameters */ - void set_buffer_type(const CircuitModelId& model_id, - const enum e_spice_model_buffer_type& buffer_type); - void set_buffer_size(const CircuitModelId& model_id, - const float& buffer_size); - void set_buffer_num_levels(const CircuitModelId& model_id, - const size_t& num_levels); - void set_buffer_f_per_stage(const CircuitModelId& model_id, - const size_t& f_per_stage); - /* Pass-gate-related parameters */ - void set_pass_gate_logic_type(const CircuitModelId& model_id, - const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type); - void set_pass_gate_logic_nmos_size(const CircuitModelId& model_id, - const float& nmos_size); - void set_pass_gate_logic_pmos_size(const CircuitModelId& model_id, - const float& pmos_size); - /* Multiplexer-related parameters */ - void set_mux_structure(const CircuitModelId& model_id, - const enum e_spice_model_structure& mux_structure); - void set_mux_num_levels(const CircuitModelId& model_id, - const size_t& num_levels); - void set_mux_const_input_value(const CircuitModelId& model_id, - const size_t& const_input_value); - void set_mux_use_local_encoder(const CircuitModelId& model_id, - const bool& use_local_encoder); - void set_mux_use_advanced_rram_design(const CircuitModelId& model_id, - const bool& use_advanced_rram_design); - /* LUT-related parameters */ - void set_lut_is_fracturable(const CircuitModelId& model_id, - const bool& is_fracturable); - /* Gate-related parameters */ - void set_gate_type(const CircuitModelId& model_id, - const enum e_spice_model_gate_type& gate_type); - /* RRAM-related design technology information */ - void set_rram_rlrs(const CircuitModelId& model_id, - const float& rlrs); - void set_rram_rhrs(const CircuitModelId& model_id, - const float& rhrs); - void set_rram_wprog_set_nmos(const CircuitModelId& model_id, - const float& wprog_set_nmos); - void set_rram_wprog_set_pmos(const CircuitModelId& model_id, - const float& wprog_set_pmos); - void set_rram_wprog_reset_nmos(const CircuitModelId& model_id, - const float& wprog_reset_nmos); - void set_rram_wprog_reset_pmos(const CircuitModelId& model_id, - const float& wprog_reset_pmos); - /* Wire parameters */ - void set_wire_type(const CircuitModelId& model_id, - const enum e_wire_model_type& wire_type); - void set_wire_r(const CircuitModelId& model_id, - const float& r_val); - void set_wire_c(const CircuitModelId& model_id, - const float& c_val); - void set_wire_num_levels(const CircuitModelId& model_id, - const size_t& num_level); - private: /* Private Mutators: builders */ - void set_model_buffer(const CircuitModelId& model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& model_name); - void link_port_tri_state_model(); - void link_port_inv_model(); - void link_buffer_model(const CircuitModelId& model_id); - void link_pass_gate_logic_model(const CircuitModelId& model_id); - bool is_unique_submodel(const CircuitModelId& model_id, const CircuitModelId& submodel_id); - void build_model_timing_graph(const CircuitModelId& model_id); - void build_submodels(); - public: /* Public Mutators: builders */ - void build_model_links(); - void build_timing_graphs(); - public: /* Internal mutators: build timing graphs */ - void add_edge(const CircuitModelId& model_id, - const CircuitPortId& from_port, const size_t& from_pin, - const CircuitPortId& to_port, const size_t& to_pin); - void set_edge_delay(const CircuitModelId& model_id, - const CircuitEdgeId& circuit_edge_id, - const enum spice_model_delay_type& delay_type, - const float& delay_value); - /* validate the circuit_edge_id */ - void set_timing_graph_delays(const CircuitModelId& model_id); - public: /* Internal mutators: build fast look-ups */ - void build_model_lookup(); - void build_model_port_lookup(); - public: /* Public invalidators/validators */ - bool valid_model_id(const CircuitModelId& model_id) const; - bool valid_circuit_port_id(const CircuitPortId& circuit_port_id) const; - bool valid_circuit_pin_id(const CircuitPortId& circuit_port_id, const size_t& pin_id) const; - private: /* Internal invalidators/validators */ - /* Validators */ - bool valid_edge_id(const CircuitEdgeId& edge_id) const; - bool valid_delay_type(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) const; - bool valid_circuit_edge_id(const CircuitEdgeId& circuit_edge_id) const; - bool valid_mux_const_input_value(const size_t& const_input_value) const; - /* Invalidators */ - void invalidate_model_lookup() const; - void invalidate_model_port_lookup() const; - void invalidate_model_timing_graph(); - private: /* Internal data */ - /* Fundamental information */ - vtr::vector model_ids_; - vtr::vector model_types_; - vtr::vector model_names_; - vtr::vector model_prefix_; - vtr::vector model_verilog_netlists_; - vtr::vector model_spice_netlists_; - vtr::vector model_is_default_; - - /* Submodules that a circuit model contains */ - vtr::vector> sub_models_; - - /* fast look-up for circuit models to categorize by types - * [type][num_ids] - * Important: we force the default circuit model in the first element for each type - */ - typedef std::vector> CircuitModelLookup; - mutable CircuitModelLookup model_lookup_; /* [model_type][model_ids] */ - typedef vtr::vector>> CircuitModelPortLookup; - mutable CircuitModelPortLookup model_port_lookup_; /* [model_id][port_type][port_ids] */ - - /* Verilog generator options */ - vtr::vector dump_structural_verilog_; - vtr::vector dump_explicit_port_map_; - - /* Design technology information */ - vtr::vector design_tech_types_; - vtr::vector is_power_gated_; - - /* Buffer existence */ - vtr::vector> buffer_existence_; - vtr::vector> buffer_model_names_; - vtr::vector> buffer_model_ids_; - vtr::vector> buffer_location_maps_; - - /* Pass-gate-related parameters */ - vtr::vector pass_gate_logic_model_names_; - vtr::vector pass_gate_logic_model_ids_; - - /* Port information */ - vtr::vector port_ids_; - vtr::vector port_model_ids_; - vtr::vector port_types_; - vtr::vector port_sizes_; - vtr::vector port_prefix_; - vtr::vector port_lib_names_; - vtr::vector port_inv_prefix_; - vtr::vector port_default_values_; - vtr::vector port_is_io_; - vtr::vector port_is_mode_select_; - vtr::vector port_is_global_; - vtr::vector port_is_reset_; - vtr::vector port_is_set_; - vtr::vector port_is_config_enable_; - vtr::vector port_is_prog_; - vtr::vector port_tri_state_model_names_; - vtr::vector port_tri_state_model_ids_; - vtr::vector port_inv_model_names_; - vtr::vector port_inv_model_ids_; - vtr::vector port_tri_state_maps_; - vtr::vector port_lut_frac_level_; - vtr::vector> port_lut_output_masks_; - vtr::vector port_sram_orgz_; - - /* Timing graphs */ - vtr::vector edge_ids_; - vtr::vector edge_parent_model_ids_; - vtr::vector> port_in_edge_ids_; - vtr::vector> port_out_edge_ids_; - vtr::vector edge_src_port_ids_; - vtr::vector edge_src_pin_ids_; - vtr::vector edge_sink_port_ids_; - vtr::vector edge_sink_pin_ids_; - vtr::vector> edge_timing_info_; /* x0 => trise, x1 => tfall */ - - /* Delay information */ - vtr::vector> delay_types_; - vtr::vector> delay_in_port_names_; - vtr::vector> delay_out_port_names_; - vtr::vector> delay_values_; - - /* Buffer/Inverter-related parameters */ - vtr::vector buffer_types_; - vtr::vector buffer_sizes_; - vtr::vector buffer_num_levels_; - vtr::vector buffer_f_per_stage_; - - /* Pass-gate-related parameters */ - vtr::vector pass_gate_logic_types_; - vtr::vector> pass_gate_logic_sizes_; /* x=> nmos_size; y => pmos_size */ - - /* Multiplexer-related parameters */ - vtr::vector mux_structure_; - vtr::vector mux_num_levels_; - vtr::vector mux_const_input_values_; - vtr::vector mux_use_local_encoder_; - vtr::vector mux_use_advanced_rram_design_; - - /* LUT-related parameters */ - vtr::vector lut_is_fracturable_; - - /* Gate-related parameters */ - vtr::vector gate_types_; - - /* RRAM-related design technology information */ - vtr::vector> rram_res_; /* x => R_LRS, y => R_HRS */ - vtr::vector> wprog_set_; /* x => wprog_set_nmos, y=> wprog_set_pmos */ - vtr::vector> wprog_reset_; /* x => wprog_reset_nmos, y=> wprog_reset_pmos */ - - /* Wire parameters */ - vtr::vector wire_types_; - vtr::vector> wire_rc_; /* x => wire_res_val, y=> wire_cap_val */ - vtr::vector wire_num_levels_; -}; - -#endif - -/************************************************************************ - * End of file : circuit_library.cpp - ***********************************************************************/ diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library_fwd.h b/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library_fwd.h deleted file mode 100644 index cef4fc4a0..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library_fwd.h +++ /dev/null @@ -1,26 +0,0 @@ -/************************************************************************ - * A header file for CircuitLibrary class, including critical data declaration - * Please include this file only for using any CircuitLibrary data structure - * Refer to circuit_library.h for more details - ***********************************************************************/ - -/************************************************************************ - * Create strong id for Circuit Models/Ports to avoid illegal type casting - ***********************************************************************/ -#ifndef CIRCUIT_LIBRARY_FWD_H -#define CIRCUIT_LIBRARY_FWD_H - -#include "vtr_strong_id.h" - -struct circuit_model_id_tag; -struct circuit_port_id_tag; -struct circuit_edge_id_tag; - -typedef vtr::StrongId CircuitModelId; -typedef vtr::StrongId CircuitPortId; -typedef vtr::StrongId CircuitEdgeId; - -/* Short declaration of class */ -class CircuitLibrary; - -#endif diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library_utils.cpp b/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library_utils.cpp deleted file mode 100644 index 22145b38f..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library_utils.cpp +++ /dev/null @@ -1,265 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: circuit_library_utils.cpp - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/09/27 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ - -/************************************************************************ - * Function to perform fundamental operation for the circuit library - * These functions are not universal methods for the CircuitLibrary class - * They are made to ease the development in some specific purposes - * Please classify such functions in this file - ***********************************************************************/ - -/* Header files should be included in a sequence */ -/* Standard header files required go first */ -#include - -#include "vtr_assert.h" - -#include "util.h" - -#include "circuit_library_utils.h" - -/******************************************************************** - * Get the model id of a SRAM model that is used to configure - * a circuit model - *******************************************************************/ -std::vector find_circuit_sram_models(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - /* SRAM model id is stored in the sram ports of a circuit model */ - std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM); - std::vector sram_models; - - /* Create a list of sram models, but avoid duplicated model ids */ - for (const auto& sram_port : sram_ports) { - CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port); - VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) ); - if (sram_models.end() != std::find(sram_models.begin(), sram_models.end(), sram_model)) { - continue; /* Already in the list, skip the addition */ - } - /* Not in the list, add it */ - sram_models.push_back(sram_model); - } - - return sram_models; -} - -/******************************************************************** - * Find regular (not mode select) sram ports of a circuit model - *******************************************************************/ -std::vector find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true); - std::vector regular_sram_ports; - - for (const auto& port : sram_ports) { - if (true == circuit_lib.port_is_mode_select(port)) { - continue; - } - regular_sram_ports.push_back(port); - } - - return regular_sram_ports; -} - -/******************************************************************** - * Find mode select sram ports of a circuit model - *******************************************************************/ -std::vector find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true); - std::vector mode_select_sram_ports; - - for (const auto& port : sram_ports) { - if (false == circuit_lib.port_is_mode_select(port)) { - continue; - } - mode_select_sram_ports.push_back(port); - } - - return mode_select_sram_ports; -} - - -/******************************************************************** - * Find the number of shared configuration bits for a ReRAM circuit - * TODO: this function is subjected to be changed due to ReRAM-based SRAM cell design!!! - *******************************************************************/ -static -size_t find_rram_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& rram_model, - const e_sram_orgz& sram_orgz_type) { - size_t num_shared_config_bits = 0; - - /* Branch on the organization of configuration protocol */ - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - case SPICE_SRAM_SCAN_CHAIN: - break; - case SPICE_SRAM_MEMORY_BANK: { - /* Find BL/WL ports */ - std::vector blb_ports = circuit_lib.model_ports_by_type(rram_model, SPICE_MODEL_PORT_BLB); - for (auto blb_port : blb_ports) { - num_shared_config_bits = std::max((int)num_shared_config_bits, (int)circuit_lib.port_size(blb_port) - 1); - } - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - - return num_shared_config_bits; -} - -/******************************************************************** - * A generic function to find the number of shared configuration bits - * for circuit model - * It will return 0 for CMOS circuits - * It will return the maximum shared configuration bits across ReRAM models - * - * Note: This function may give WRONG results when all the SRAM ports - * are not properly linked to its circuit models! - * So, it should be called after the SRAM linking is done!!! - * - * IMPORTANT: This function should NOT be used to find the number of shared configuration bits - * for a multiplexer, because the multiplexer size is determined during - * the FPGA architecture generation (NOT during the XML parsing). - *******************************************************************/ -size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const e_sram_orgz& sram_orgz_type) { - size_t num_shared_config_bits = 0; - - std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM); - for (auto sram_port : sram_ports) { - CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port); - VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) ); - - /* Depend on the design technolgy of SRAM model, the number of configuration bits will be different */ - switch (circuit_lib.design_tech_type(sram_model)) { - case SPICE_MODEL_DESIGN_CMOS: - /* CMOS circuit do not need shared configuration bits */ - break; - case SPICE_MODEL_DESIGN_RRAM: - /* RRAM circuit do need shared configuration bits, but it is subjected to the largest one among different SRAM models */ - num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_rram_circuit_num_shared_config_bits(circuit_lib, sram_model, sram_orgz_type)); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid design technology for SRAM model!\n", - __FILE__, __LINE__); - exit(1); - } - } - - return num_shared_config_bits; -} - -/******************************************************************** - * A generic function to find the number of configuration bits - * for circuit model - * It will sum up the sizes of all the sram ports - * - * IMPORTANT: This function should NOT be used to find the number of configuration bits - * for a multiplexer, because the multiplexer size is determined during - * the FPGA architecture generation (NOT during the XML parsing). - *******************************************************************/ -size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - size_t num_config_bits = 0; - - std::vector sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM); - for (auto sram_port : sram_ports) { - num_config_bits += circuit_lib.port_size(sram_port); - } - - return num_config_bits; -} - -/******************************************************************** - * A generic function to find all the global ports in a circuit library - * - * IMPORTANT: This function will uniquify the global ports whose share - * share the same name !!! - *******************************************************************/ -std::vector find_circuit_library_global_ports(const CircuitLibrary& circuit_lib) { - std::vector global_ports; - - for (auto port : circuit_lib.ports()) { - /* By pass non-global ports*/ - if (false == circuit_lib.port_is_global(port)) { - continue; - } - /* Check if a same port with the same name has already been in the list */ - bool add_to_list = true; - for (const auto& global_port : global_ports) { - if (0 == circuit_lib.port_prefix(port).compare(circuit_lib.port_prefix(global_port))) { - /* Same name, skip list update */ - add_to_list = false; - break; - } - } - if (true == add_to_list) { - /* Add the global_port to the list */ - global_ports.push_back(port); - } - } - - return global_ports; -} - -/******************************************************************** - * A generic function to find all the unique user-defined - * Verilog netlists in a circuit library - * Netlists with same names will be considered as one - *******************************************************************/ -std::vector find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib) { - std::vector netlists; - - for (const CircuitModelId& model : circuit_lib.models()) { - /* Skip empty netlist names */ - if (true == circuit_lib.model_verilog_netlist(model).empty()) { - continue; - } - /* See if the netlist name is already in the list */ - std::vector::iterator it = std::find(netlists.begin(), netlists.end(), circuit_lib.model_verilog_netlist(model)); - if (it == netlists.end()) { - netlists.push_back(circuit_lib.model_verilog_netlist(model)); - } - } - - return netlists; -} diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library_utils.h b/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library_utils.h deleted file mode 100644 index 056777c61..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_library_utils.h +++ /dev/null @@ -1,34 +0,0 @@ -/******************************************************************** - * Header file for circuit_library_utils.cpp - *******************************************************************/ -#ifndef CIRCUIT_LIBRARY_UTILS_H -#define CIRCUIT_LIBRARY_UTILS_H - -/* Header files should be included in a sequence */ -/* Standard header files required go first */ - -#include -#include "spice_types.h" -#include "circuit_library.h" - -std::vector find_circuit_sram_models(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model); - -std::vector find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model); - -std::vector find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model); - -size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const e_sram_orgz& sram_orgz_type); - -size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model); - -std::vector find_circuit_library_global_ports(const CircuitLibrary& circuit_lib); - -std::vector find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib); - -#endif diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_types.h b/vpr7_x2p/libarchfpgavpr7/SRC/circuit_types.h deleted file mode 100644 index 9a0e72dda..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/circuit_types.h +++ /dev/null @@ -1,153 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: circuit_types.h - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/08/08 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ - -/* IMPORTANT: - * The following preprocessing flags are added to - * avoid compilation error when this headers are included in more than 1 times - */ -#ifndef CIRCUIT_TYPES_H -#define CIRCUIT_TYPES_H - -/************************************************************************ - * This file includes basic enumeration types for circuit models - ***********************************************************************/ -/* - * Notes in include header files in a head file - * Only include the neccessary header files - * that is required by the data types in the function/class declarations! - */ -/* Header files should be included in a sequence */ -/* Standard header files required go first */ - -enum spice_model_delay_type { - SPICE_MODEL_DELAY_RISE, - SPICE_MODEL_DELAY_FALL, - NUM_CIRCUIT_MODEL_DELAY_TYPES -}; - -/*Struct for a SPICE model of a module*/ -enum e_spice_model_type { - SPICE_MODEL_CHAN_WIRE, - SPICE_MODEL_WIRE, - SPICE_MODEL_MUX, - SPICE_MODEL_LUT, - SPICE_MODEL_FF, - SPICE_MODEL_SRAM, - SPICE_MODEL_HARDLOGIC, - SPICE_MODEL_CCFF, - SPICE_MODEL_IOPAD, - SPICE_MODEL_INVBUF, - SPICE_MODEL_PASSGATE, - SPICE_MODEL_GATE, - NUM_CIRCUIT_MODEL_TYPES -}; -/* Strings correspond to each port type */ -constexpr std::array CIRCUIT_MODEL_TYPE_STRING = {{"CHAN_WIRE", "WIRE", "MUX", "LUT", "FF", "SRAM", "HARDLOGIC", "CCFF", "IOPAD", "INVBUF", "PASSGATE", "GATE"}}; - -enum e_spice_model_design_tech { - SPICE_MODEL_DESIGN_CMOS, - SPICE_MODEL_DESIGN_RRAM, - NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES -}; - -enum e_spice_model_structure { - SPICE_MODEL_STRUCTURE_TREE, - SPICE_MODEL_STRUCTURE_ONELEVEL, - SPICE_MODEL_STRUCTURE_MULTILEVEL, - SPICE_MODEL_STRUCTURE_CROSSBAR, - NUM_CIRCUIT_MODEL_STRUCTURE_TYPES -}; -/* Strings correspond to each type of mux structure */ -constexpr std::array CIRCUIT_MODEL_STRUCTURE_TYPE_STRING = {{"TREE-LIKE", "ONE-LEVEL", "MULTI-LEVEL", "CROSSBAR"}}; - -enum e_spice_model_buffer_type { - SPICE_MODEL_BUF_INV, - SPICE_MODEL_BUF_BUF, - NUM_CIRCUIT_MODEL_BUF_TYPES -}; - -enum e_spice_model_pass_gate_logic_type { - SPICE_MODEL_PASS_GATE_TRANSMISSION, - SPICE_MODEL_PASS_GATE_TRANSISTOR, - SPICE_MODEL_PASS_GATE_RRAM, /* RRAM can be treated as a special type of pass-gate logic */ - SPICE_MODEL_PASS_GATE_STDCELL, /* Standard cell as a special type of pass-gate logic */ - NUM_CIRCUIT_MODEL_PASS_GATE_TYPES -}; - -enum e_spice_model_gate_type { - SPICE_MODEL_GATE_AND, - SPICE_MODEL_GATE_OR, - SPICE_MODEL_GATE_MUX2, - NUM_SPICE_MODEL_GATE_TYPES -}; - -enum e_wire_model_type { - WIRE_MODEL_PIE, - WIRE_MODEL_T, - NUM_WIRE_MODEL_TYPES -}; - -enum e_spice_model_port_type { - SPICE_MODEL_PORT_INPUT, - SPICE_MODEL_PORT_OUTPUT, - SPICE_MODEL_PORT_INOUT, - SPICE_MODEL_PORT_CLOCK, - SPICE_MODEL_PORT_SRAM, - SPICE_MODEL_PORT_BL, - SPICE_MODEL_PORT_BLB, - SPICE_MODEL_PORT_WL, - SPICE_MODEL_PORT_WLB, - NUM_CIRCUIT_MODEL_PORT_TYPES -}; -/* Strings correspond to each port type */ -constexpr std::array CIRCUIT_MODEL_PORT_TYPE_STRING = {{"INPUT", "OUTPUT", "INOUT", "CLOCK", "SRAM", "BL", "BLB", "WL", "WLB"}}; - -/* For SRAM */ -enum e_sram_orgz { - SPICE_SRAM_STANDALONE, /* SRAMs are organized and accessed as standalone elements */ - SPICE_SRAM_SCAN_CHAIN, /* SRAMs are organized and accessed by a scan-chain */ - SPICE_SRAM_MEMORY_BANK, /* SRAMs are organized and accessed by memory bank */ - SPICE_SRAM_LOCAL_ENCODER, /* SRAMs are organized and accessed by a local encoder */ - NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES -}; -constexpr std::array CIRCUIT_MODEL_SRAM_ORGZ_TYPE_STRING = {{"STANDALONE", "SCAN-CHAIN", "MEMORY_BANK", "LOCAL_ENCODER"}}; - - -#endif - -/************************************************************************ - * End of file : circuit_types.h - ***********************************************************************/ - diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/device_port.cpp b/vpr7_x2p/libarchfpgavpr7/SRC/device_port.cpp deleted file mode 100644 index d02229970..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/device_port.cpp +++ /dev/null @@ -1,397 +0,0 @@ -#include -#include -#include - -#include "vtr_assert.h" - -#include "device_port.h" - -/* Basic Port member functions */ -/* Constructor */ -/* Default constructor */ -BasicPort::BasicPort() { - /* By default we set an invalid port, which size is 0 */ - lsb_ = 1; - msb_ = 0; -} - -/* Quick constructor */ -BasicPort::BasicPort(const char* name, const size_t& lsb, const size_t& msb) { - set_name(std::string(name)); - set_width(lsb, msb); -} - -BasicPort::BasicPort(const std::string& name, const size_t& lsb, const size_t& msb) { - set_name(name); - set_width(lsb, msb); -} - -BasicPort::BasicPort(const char* name, const size_t& width) { - set_name(std::string(name)); - set_width(width); -} - -BasicPort::BasicPort(const std::string& name, const size_t& width) { - set_name(name); - set_width(width); -} - -/* Copy constructor */ -BasicPort::BasicPort(const BasicPort& basic_port) { - set(basic_port); -} - -/* Accessors */ -/* get the port width */ -size_t BasicPort::get_width() const { - if (true == is_valid()) { - return msb_ - lsb_ + 1; - } - return 0; /* invalid port has a zero width */ -} - -/* get the LSB */ -size_t BasicPort::get_msb() const { - return msb_; -} - -/* get the LSB */ -size_t BasicPort::get_lsb() const { - return lsb_; -} - -/* get the name */ -std::string BasicPort::get_name() const { - return name_; -} - -/* Make a range of the pin indices */ -std::vector BasicPort::pins() const { - std::vector pin_indices; - - /* Return if the port is invalid */ - if (false == is_valid()) { - return pin_indices; /* Return an empty vector */ - } - /* For valid ports, create a vector whose length is the port width */ - pin_indices.resize(get_width()); - /* Fill in an incremental sequence */ - std::iota(pin_indices.begin(), pin_indices.end(), get_lsb()); - /* Ensure the last one is MSB */ - VTR_ASSERT(get_msb() == pin_indices.back()); - - return pin_indices; -} - -/* Check if a port can be merged with this port: their name should be the same */ -bool BasicPort::mergeable(const BasicPort& portA) const { - return (0 == this->get_name().compare(portA.get_name())); -} - -/* Check if a port is contained by this port: - * this function will check if the (LSB, MSB) of portA - * is contained by the (LSB, MSB) of this port - */ -bool BasicPort::contained(const BasicPort& portA) const { - return ( lsb_ <= portA.get_lsb() && portA.get_msb() <= msb_ ); -} - -/* Overloaded operators */ -/* Two ports are the same only when: - * 1. port names are the same - * 2. LSBs are the same - * 3. MSBs are the same - */ -bool BasicPort::operator== (const BasicPort& portA) const { - if ( (0 == this->get_name().compare(portA.get_name())) - && (this->get_lsb() == portA.get_lsb()) - && (this->get_msb() == portA.get_msb()) ) { - return true; - } - return false; -} - -/* Mutators */ -/* copy */ -void BasicPort::set(const BasicPort& basic_port) { - name_ = basic_port.get_name(); - lsb_ = basic_port.get_lsb(); - msb_ = basic_port.get_msb(); - - return; -} - -/* set the port LSB and MSB */ -void BasicPort::set_name(const std::string& name) { - name_ = name; - return; -} - -/* set the port LSB and MSB */ -void BasicPort::set_width(const size_t& width) { - if (0 == width) { - make_invalid(); - return; - } - lsb_ = 0; - msb_ = width - 1; - return; -} - -/* set the port LSB and MSB */ -void BasicPort::set_width(const size_t& lsb, const size_t& msb) { - /* If lsb and msb is invalid, we make a default port */ - if (lsb > msb) { - make_invalid(); - return; - } - set_lsb(lsb); - set_msb(msb); - return; -} - -void BasicPort::set_lsb(const size_t& lsb) { - lsb_ = lsb; - return; -} - -void BasicPort::set_msb(const size_t& msb) { - msb_ = msb; - return; -} - -/* Increase the port width */ -void BasicPort::expand(const size_t& width) { - if (0 == width) { - return; /* ignore zero-width port */ - } - /* If current port is invalid, we do not combine */ - if (0 == get_width()) { - lsb_ = 0; - msb_ = width; - return; - } - /* Increase MSB */ - msb_ += width; - return; -} - -/* Swap lsb and msb */ -void BasicPort::revert() { - std::swap(lsb_, msb_); - return; -} - -/* rotate: increase both lsb and msb by an offset */ -bool BasicPort::rotate(const size_t& offset) { - /* If offset is 0, we do nothing */ - if (0 == offset) { - return true; - } - - /* If current width is 0, we set a width using the offset! */ - if (0 == get_width()) { - set_width(offset); - return true; - } - /* check if leads to overflow: - * if limits - msb is larger than offset - */ - if ( (std::numeric_limits::max() - msb_ < offset) ) { - return false; - } - /* Increase LSB and MSB */ - lsb_ += offset; - msb_ += offset; - return true; -} - -/* rotate: decrease both lsb and msb by an offset */ -bool BasicPort::counter_rotate(const size_t& offset) { - /* If current port is invalid or offset is 0, - * we do nothing - */ - if ((0 == offset) || (0 == get_width())) { - return true; - } - /* check if leads to overflow: - * if limits is larger than offset - */ - if ( (std::numeric_limits::min() + lsb_ < offset) ) { - return false; - } - /* decrease LSB and MSB */ - lsb_ -= offset; - msb_ -= offset; - return true; -} - -/* Reset to initial port */ -void BasicPort::reset() { - make_invalid(); - return; -} - -/* Combine two ports */ -void BasicPort::combine(const BasicPort& port) { - /* LSB follows the current LSB */ - /* MSB increases */ - VTR_ASSERT(0 < port.get_width() ); /* Make sure port is valid */ - /* If current port is invalid, we do not combine */ - if (0 == get_width()) { - return; - } - /* Increase MSB */ - msb_ += port.get_width(); - return; -} - -/* A restricted combine function for two ports, - * Following conditions will be applied: - * 1. the two ports have the same name - * Note: you must run mergable() function first - * to make sure this assumption is valid - * 2. the new MSB will be the maximum MSB of the two ports - * 3. the new LSB will be the minimum LSB of the two ports - * 4. both ports should be valid!!! - */ -void BasicPort::merge(const BasicPort& portA) { - VTR_ASSERT(true == this->mergeable(portA)); - VTR_ASSERT(true == this->is_valid() && true == portA.is_valid()); - /* We skip merging if the portA is already contained by this port */ - if (true == this->contained(portA)) { - return; - } - /* LSB follows the minium LSB of the two ports */ - lsb_ = std::min((int)lsb_, (int)portA.get_lsb()); - /* MSB follows the minium MSB of the two ports */ - msb_ = std::max((int)msb_, (int)portA.get_msb()); - return; -} - -/* Internal functions */ -/* Make a port to be invalid: msb < lsb */ -void BasicPort::make_invalid() { - /* set a default invalid port */ - lsb_ = 1; - msb_ = 0; - return; -} - -/* check if port size is valid > 0 */ -bool BasicPort::is_valid() const { - /* msb should be equal or greater than lsb, if this is a valid port */ - if ( msb_ < lsb_ ) { - return false; - } - return true; -} - -/* ConfPorts member functions */ -/* Constructor */ -/* Default constructor */ -ConfPorts::ConfPorts() { - /* default port */ - reserved_.reset(); - regular_.reset(); -} - -/* copy */ -ConfPorts::ConfPorts(const ConfPorts& conf_ports) { - set(conf_ports); -} - -/* Accessors */ -size_t ConfPorts::get_reserved_port_width() const { - return reserved_.get_width(); -} - -size_t ConfPorts::get_reserved_port_lsb() const { - return reserved_.get_lsb(); -} - -size_t ConfPorts::get_reserved_port_msb() const { - return reserved_.get_msb(); -} - -size_t ConfPorts::get_regular_port_width() const { - return regular_.get_width(); -} - -size_t ConfPorts::get_regular_port_lsb() const { - return regular_.get_lsb(); -} - -size_t ConfPorts::get_regular_port_msb() const { - return regular_.get_msb(); -} - -/* Mutators */ -void ConfPorts::set(const ConfPorts& conf_ports) { - set_reserved_port(conf_ports.get_reserved_port_width()); - set_regular_port(conf_ports.get_regular_port_lsb(), conf_ports.get_regular_port_msb()); - return; -} - -void ConfPorts::set_reserved_port(size_t width) { - reserved_.set_width(width); - return; -} - -void ConfPorts::set_regular_port(size_t width) { - regular_.set_width(width); - return; -} - -void ConfPorts::set_regular_port(size_t lsb, size_t msb) { - regular_.set_width(lsb, msb); - return; -} - -void ConfPorts::set_regular_port_lsb(size_t lsb) { - regular_.set_lsb(lsb); - return; -} - -void ConfPorts::set_regular_port_msb(size_t msb) { - regular_.set_msb(msb); - return; -} - -/* Increase the port width of reserved port */ -void ConfPorts::expand_reserved_port(size_t width) { - reserved_.expand(width); - return; -} - -/* Increase the port width of regular port */ -void ConfPorts::expand_regular_port(size_t width) { - regular_.expand(width); - return; -} - -/* Increase the port width of both ports */ -void ConfPorts::expand(size_t width) { - expand_reserved_port(width); - expand_regular_port(width); -} - -/* rotate */ -bool ConfPorts::rotate_regular_port(size_t offset) { - return regular_.rotate(offset); -} - -/* counter rotate */ -bool ConfPorts::counter_rotate_regular_port(size_t offset) { - return regular_.counter_rotate(offset); -} - -/* Reset to initial port */ -void ConfPorts::reset() { - reserved_.reset(); - regular_.reset(); - return; -} - - - diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/device_port.h b/vpr7_x2p/libarchfpgavpr7/SRC/device_port.h deleted file mode 100644 index 149a7f78b..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/device_port.h +++ /dev/null @@ -1,89 +0,0 @@ -/* IMPORTANT: - * The following preprocessing flags are added to - * avoid compilation error when this headers are included in more than 1 times - */ -#ifndef DEVICE_PORT_H -#define DEVICE_PORT_H - -#include -#include - -/* A basic port */ -class BasicPort { - public: /* Constructors */ - BasicPort(); - BasicPort(const char* name, const size_t& lsb, const size_t& msb); - BasicPort(const char* name, const size_t& width); - BasicPort(const std::string& name, const size_t& lsb, const size_t& msb); - BasicPort(const std::string& name, const size_t& width); - BasicPort(const BasicPort& basic_port); /* Copy constructor */ - public: /* Overloaded operators */ - bool operator== (const BasicPort& portA) const; - public: /* Accessors */ - size_t get_width() const; /* get the port width */ - size_t get_msb() const; /* get the LSB */ - size_t get_lsb() const; /* get the LSB */ - std::string get_name() const; /* get the name */ - bool is_valid() const; /* check if port size is valid > 0 */ - std::vector pins() const; /* Make a range of the pin indices */ - bool mergeable(const BasicPort& portA) const; /* Check if a port can be merged with this port */ - bool contained(const BasicPort& portA) const; /* Check if a port is contained by this port */ - public: /* Mutators */ - void set(const BasicPort& basic_port); /* copy */ - void set_name(const std::string& name); /* set the port LSB and MSB */ - void set_width(const size_t& width); /* set the port LSB and MSB */ - void set_width(const size_t& lsb, const size_t& msb); /* set the port LSB and MSB */ - void set_lsb(const size_t& lsb); - void set_msb(const size_t& msb); - void expand(const size_t& width); /* Increase the port width */ - void revert(); /* Swap lsb and msb */ - bool rotate(const size_t& offset); /* rotate */ - bool counter_rotate(const size_t& offset); /* counter rotate */ - void reset(); /* Reset to initial port */ - void combine(const BasicPort& port); /* Combine two ports */ - void merge(const BasicPort& portA); - private: /* internal functions */ - void make_invalid(); /* Make a port invalid */ - private: /* Internal Data */ - std::string name_; /* Name of this port */ - size_t msb_; /* Most Significant Bit of this port */ - size_t lsb_; /* Least Significant Bit of this port */ -}; - -/* Configuration ports: - * 1. reserved configuration port, which is used by RRAM FPGA architecture - * 2. regular configuration port, which is used by any FPGA architecture - */ -class ConfPorts { - public: /* Constructors */ - ConfPorts(); /* default port */ - ConfPorts(const ConfPorts& conf_ports); /* copy */ - public: /* Accessors */ - size_t get_reserved_port_width() const; - size_t get_reserved_port_lsb() const; - size_t get_reserved_port_msb() const; - size_t get_regular_port_width() const; - size_t get_regular_port_lsb() const; - size_t get_regular_port_msb() const; - public: /* Mutators */ - void set(const ConfPorts& conf_ports); - void set_reserved_port(size_t width); - void set_regular_port(size_t width); - void set_regular_port(size_t lsb, size_t msb); - void set_regular_port_lsb(size_t lsb); - void set_regular_port_msb(size_t msb); - void expand_reserved_port(size_t width); /* Increase the port width of reserved port */ - void expand_regular_port(size_t width); /* Increase the port width of regular port */ - void expand(size_t width); /* Increase the port width of both ports */ - bool rotate_regular_port(size_t offset); /* rotate */ - bool counter_rotate_regular_port(size_t offset); /* counter rotate */ - void reset(); /* Reset to initial port */ - private: /* Internal Data */ - BasicPort reserved_; - BasicPort regular_; -}; - -/* TODO: create a class for BL and WL ports */ - -#endif - diff --git a/vpr7_x2p/libarchfpgavpr7/SRC/ezxml.c b/vpr7_x2p/libarchfpgavpr7/SRC/ezxml.c deleted file mode 100644 index 46cce5535..000000000 --- a/vpr7_x2p/libarchfpgavpr7/SRC/ezxml.c +++ /dev/null @@ -1,1285 +0,0 @@ -/* ezxml.c - * - * Copyright 2004-2006 Aaron Voisine - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef EZXML_NOMMAP -#define EZXML_NOMMAP -#endif /* EXXML_NOMMAP */ - -/* Ted Campbell, Aug 14 2007 */ -#if defined(WIN32) || defined(_WIN32) -#include -#endif /* WIN32 */ - -#include -#include -#include -#include -#include - -/* Ted Campbell, Aug 14 2007 */ -#if !defined(WIN32) && !defined(_WIN32) -#include -#endif - -#include -#ifndef EZXML_NOMMAP -#include -#endif /* EZXML_NOMMAP */ -#include -#include "ezxml.h" - -/* Ted Campbell, Aug 14, 2007 */ -#include "util.h" - -/* Ted Campbell, Aug 14, 2007 */ -#if defined(WIN32) || defined(_WIN32) -#define snprintf _snprintf -#define open _open -#define read _read -#define write _write -#define close _close -#endif /* WIN32 */ - -#define EZXML_WS "\t\r\n " /* whitespace */ -char *EZXML_NIL[] = { NULL }; /* empty, null terminated array of strings */ - -static ezxml_t ezxml_vget(ezxml_t xml, va_list ap); -static char *ezxml_decode(char *s, char **ent, char t); -static void ezxml_open_tag(ezxml_root_t root, int line, char *name, char **attr); -static void ezxml_char_content(ezxml_root_t root, char *s, - size_t len, char t); -static ezxml_t ezxml_close_tag(ezxml_root_t root, char *name, char *s); -static int ezxml_ent_ok(char *name, char *s, char **ent); -static void ezxml_proc_inst(ezxml_root_t root, char *s, size_t len); -static short ezxml_internal_dtd(ezxml_root_t root, char *s, - size_t len); -static char *ezxml_str2utf8(char **s, size_t * len); -static void ezxml_free_attr(char **attr); -static char *ezxml_ampencode(const char *s, size_t len, char **dst, - size_t * dlen, size_t * max, short a); -static char *ezxml_toxml_r(ezxml_t xml, char **s, size_t * len, size_t * max, - size_t start, char ***attr); - -/* returns the first child tag with the given name or NULL if not found */ -ezxml_t ezxml_child(ezxml_t xml, const char *name) { - xml = (xml) ? xml->child : NULL; - while (xml && strcmp(name, xml->name)) - xml = xml->sibling; - return xml; -} - -/* returns the Nth tag with the same name in the same subsection or NULL if not */ -/* found */ -ezxml_t ezxml_idx(ezxml_t xml, int idx) { - for (; xml && idx; idx--) - xml = xml->next; - return xml; -} - -/* returns the value of the requested tag attribute or NULL if not found */ -const char * -ezxml_attr(ezxml_t xml, const char *attr) { - int i = 0, j = 1; - ezxml_root_t root = (ezxml_root_t) xml; - - if (!xml || !xml->attr) - return NULL; - while (xml->attr[i] && strcmp(attr, xml->attr[i])) - i += 2; - if (xml->attr[i]) - return xml->attr[i + 1]; /* found attribute */ - - while (root->xml.parent) - root = (ezxml_root_t) root->xml.parent; /* root tag */ - for (i = 0; root->attr[i] && strcmp(xml->name, root->attr[i][0]); i++) - ; - if (!root->attr[i]) - return NULL; /* no matching default attributes */ - while (root->attr[i][j] && strcmp(attr, root->attr[i][j])) - j += 3; - return (root->attr[i][j]) ? root->attr[i][j + 1] : NULL; /* found default */ -} - -/* same as ezxml_get but takes an already initialized va_list */ -ezxml_t ezxml_vget(ezxml_t xml, va_list ap) { - char *name = va_arg(ap, char *); - int idx = -1; - - if (name && *name) { - idx = va_arg(ap, int); - - xml = ezxml_child(xml, name); - } - return (idx < 0) ? xml : ezxml_vget(ezxml_idx(xml, idx), ap); -} - -/* Traverses the xml tree to retrieve a specific subtag. Takes a variable */ -/* length list of tag names and indexes. The argument list must be terminated */ -/* by either an index of -1 or an empty string tag name. Example: */ -/* title = ezxml_get(library, "shelf", 0, "book", 2, "title", -1); */ -/* This retrieves the title of the 3rd book on the 1st shelf of library. */ -/* Returns NULL if not found. */ -ezxml_t ezxml_get(ezxml_t xml, ...) { - va_list ap; - ezxml_t r; - - va_start(ap, xml); - r = ezxml_vget(xml, ap); - va_end(ap); - return r; -} - -/* returns a null terminated array of processing instructions for the given */ -/* target */ -char ** -ezxml_pi(ezxml_t xml, const char *target) { - ezxml_root_t root = (ezxml_root_t) xml; - int i = 0; - - if (!root) - return EZXML_NIL; - while (root->xml.parent) - root = (ezxml_root_t) root->xml.parent; /* root tag */ - while (root->pi[i] && strcmp(target, root->pi[i][0])) - i++; /* find target */ - return ((root->pi[i]) ? root->pi[i] + 1 : EZXML_NIL); -} - -/* set an error string and return root */ -static ezxml_t ezxml_err(ezxml_root_t root, char *s, const char *err, ...) { - va_list ap; - int line = 1; - char *t, fmt[EZXML_ERRL]; - - for (t = root->s; t < s; t++) - if (*t == '\n') - line++; - snprintf(fmt, EZXML_ERRL, "[error near line %d]: %s", line, err); - - va_start(ap, err); - vsnprintf(root->err, EZXML_ERRL, fmt, ap); - va_end(ap); - - return &root->xml; -} - -/* Recursively decodes entity and character references and normalizes new lines */ -/* ent is a null terminated array of alternating entity names and values. set t */ -/* to '&' for general entity decoding, '%' for parameter entity decoding, 'c' */ -/* for cdata sections, ' ' for attribute normalization, or '*' for non-cdata */ -/* attribute normalization. Returns s, or if the decoded string is longer than */ -/* s, returns a malloced string that must be freed. */ -/* Jason Luu June 22, 2010, Added line number support */ -static char * -ezxml_decode(char *s, char **ent, char t) { - char *e, *r = s, *m = s; - long b, c, d, l; - - for (; *s; s++) { /* normalize line endings */ - while (*s == '\r') { - *(s++) = '\n'; - if (*s == '\n') { - memmove(s, (s + 1), strlen(s)); - } - } - } - - for (s = r;;) { - while (*s && *s != '&' && (*s != '%' || t != '%') && !isspace(*s)) - s++; - if (!*s) - break; - else if (t != 'c' && !strncmp(s, "&#", 2)) { /* character reference */ - if (s[2] == 'x') - c = strtol(s + 3, &e, 16); /* base 16 */ - else - c = strtol(s + 2, &e, 10); /* base 10 */ - if (!c || *e != ';') { - s++; - continue; - } - /* not a character ref */ - if (c < 0x80) - *(s++) = (char) c; /* US-ASCII subset */ - else { /* multi-byte UTF-8 sequence */ - for (b = 0, d = c; d; d /= 2) - b++; /* number of bits in c */ - b = (b - 2) / 5; /* number of bytes in payload */ - *(s++) = (char)((0xFF << (7 - b)) | (c >> (6 * b))); /* head */ - while (b) - *(s++) = 0x80 | ((c >> (6 * --b)) & 0x3F); /* payload */ - } - - memmove(s, strchr(s, ';') + 1, strlen(strchr(s, ';'))); - } else if ((*s == '&' && (t == '&' || t == ' ' || t == '*')) - || (*s == '%' && t == '%')) { /* entity reference */ - for (b = 0; ent[b] && strncmp(s + 1, ent[b], strlen(ent[b])); b += - 2) - ; /* find entity in entity list */ - - if (ent[b++]) { /* found a match */ - if ((c = strlen(ent[b])) - 1 > (e = strchr(s, ';')) - s) { - l = (d = (s - r)) + c + strlen(e); /* new length */ - r = (r == m) ? strcpy((char*)malloc(l), r) : (char*)realloc(r, l); - e = strchr((s = r + d), ';'); /* fix up pointers */ - } - - memmove(s + c, e + 1, strlen(e)); /* shift rest of string */ - strncpy(s, ent[b], c); /* copy in replacement text */ - } else - s++; /* not a known entity */ - } else if ((t == ' ' || t == '*') && isspace(*s)) - *(s++) = ' '; - else - s++; /* no decoding needed */ - } - - if (t == '*') { /* normalize spaces for non-cdata attributes */ - for (s = r; *s; s++) { - /* Jason Luu, Aug 29, 2007. Removed assignment in conditional statement */ - l = strspn(s, " "); - if (l) - memmove(s, s + l, strlen(s + l) + 1); - while (*s && *s != ' ') - s++; - } - if (--s >= r && *s == ' ') - *s = '\0'; /* trim any trailing space */ - } - return r; -} - -/* called when parser finds start of new tag */ -/* Jason Luu June 22, 2010, Added line number support */ -static void ezxml_open_tag(ezxml_root_t root, int line, char *name, char **attr) { - ezxml_t xml = root->cur; - - if (xml->name) - xml = ezxml_add_child(xml, name, strlen(xml->txt)); - else - xml->name = name; /* first open tag */ - xml->line = line; - xml->attr = attr; - - root->cur = xml; /* update tag insertion point */ -} - -/* called when parser finds character content between open and closing tag */ -/* Jason Luu June 22, 2010, Added line number support */ -static void ezxml_char_content(ezxml_root_t root, char *s, - size_t len, char t) { - ezxml_t xml = root->cur; - char *m = s; - size_t l; - - if (!xml || !xml->name || !len) - return; /* sanity check */ - - s[len] = '\0'; /* null terminate text (calling functions anticipate this) */ - len = strlen(s = ezxml_decode(s, root->ent, t)) + 1; - - if (!*(xml->txt)) - xml->txt = s; /* initial character content */ - else { /* allocate our own memory and make a copy */ - xml->txt = (xml->flags & EZXML_TXTM) /* allocate some space */ - ? (char*)realloc(xml->txt, (l = strlen(xml->txt)) + len) : strcpy((char*)malloc((l = - strlen(xml->txt)) + len), xml->txt); - strcpy(xml->txt + l, s); /* add new char content */ - if (s != m) - free(s); /* free s if it was malloced by ezxml_decode() */ - } - - if (xml->txt != m) - ezxml_set_flag(xml, EZXML_TXTM); -} - -/* called when parser finds closing tag */ -static ezxml_t ezxml_close_tag(ezxml_root_t root, char *name, char *s) { - if (!root->cur || !root->cur->name || strcmp(name, root->cur->name)) - return ezxml_err(root, s, "unexpected closing tag ", name); - - root->cur = root->cur->parent; - return NULL; -} - -/* checks for circular entity references, returns non-zero if no circular */ -/* references are found, zero otherwise */ -static int ezxml_ent_ok(char *name, char *s, char **ent) { - int i; - - for (;; s++) { - while (*s && *s != '&') - s++; /* find next entity reference */ - if (!*s) - return 1; - if (!strncmp(s + 1, name, strlen(name))) - return 0; /* circular ref. */ - for (i = 0; ent[i] && strncmp(ent[i], s + 1, strlen(ent[i])); i += 2) - ; - if (ent[i] && !ezxml_ent_ok(name, ent[i + 1], ent)) - return 0; - } -} - -/* called when the parser finds a processing instruction */ -static void ezxml_proc_inst(ezxml_root_t root, char *s, size_t len) { - int i = 0, j = 1; - char *target = s; - - s[len] = '\0'; /* null terminate instruction */ - if (*(s += strcspn(s, EZXML_WS))) { - *s = '\0'; /* null terminate target */ - s += strspn(s + 1, EZXML_WS) + 1; /* skip whitespace after target */ - } - - if (!strcmp(target, "xml")) { /* */ - /* Jason Luu, Aug 29, 2007. Removed assignment in conditional statement */ - s = strstr(s, "standalone"); - if (s && !strncmp(s + strspn(s + 10, EZXML_WS "='\"") + 10, "yes", 3)) - root->standalone = 1; - return; - } - - if (!root->pi[0]) - *(root->pi = (char***)malloc(sizeof(char **))) = NULL; /*first pi */ - - while (root->pi[i] && strcmp(target, root->pi[i][0])) - i++; /* find target */ - if (!root->pi[i]) { /* new target */ - root->pi = (char***)realloc(root->pi, sizeof(char **) * (i + 2)); - root->pi[i] = (char**)malloc(sizeof(char *) * 3); - root->pi[i][0] = target; - root->pi[i][1] = (char *) (root->pi[i + 1] = NULL); /* terminate pi list */ - /* Ted Campbell, Aug 14, 2007. Changed to use 'my_strdup' */ - root->pi[i][2] = my_strdup(""); /* empty document position list */ - } - - while (root->pi[i][j]) - j++; /* find end of instruction list for this target */ - root->pi[i] = (char**)realloc(root->pi[i], sizeof(char *) * (j + 3)); - root->pi[i][j + 2] = (char*)realloc(root->pi[i][j + 1], j + 1); - strcpy(root->pi[i][j + 2] + j - 1, (root->xml.name) ? ">" : "<"); - root->pi[i][j + 1] = NULL; /* null terminate pi list for this target */ - root->pi[i][j] = s; /* set instruction */ -} - -/* called when the parser finds an internal doctype subset */ -/* Jason Luu June 22, 2010, Added line number support */ -static short ezxml_internal_dtd(ezxml_root_t root, char *s, - size_t len) { - char q, *c, *t, *n = NULL, *v, **ent, **pe; - char temp[] = {'\0','\0','\0'}; - int i, j; - - pe = (char**)memcpy(malloc(sizeof(EZXML_NIL)), EZXML_NIL, sizeof(EZXML_NIL)); - - for (s[len] = '\0'; s;) { - while (*s && *s != '<' && *s != '%') - s++; /* find next declaration */ - - if (!*s) - break; - else if (!strncmp(s, "'); - continue; - } - - for (i = 0, ent = (*c == '%') ? pe : root->ent; ent[i]; i++) - ; - ent = (char**)realloc(ent, (i + 3) * sizeof(char *)); /* space for next ent */ - if (*c == '%') - pe = ent; - else - root->ent = ent; - - *(++s) = '\0'; /* null terminate name */ - /* Jason Luu, Aug 29, 2007. Removed assignment in conditional statement */ - s = strchr(v, q); - if (s) - *(s++) = '\0'; /* null terminate value */ - ent[i + 1] = ezxml_decode(v, pe, '%'); /* set value */ - ent[i + 2] = NULL; /* null terminate entity list */ - if (!ezxml_ent_ok(n, ent[i + 1], ent)) { /* circular reference */ - if (ent[i + 1] != v) - free(ent[i + 1]); - ezxml_err(root, v, "circular entity declaration &%s", n); - break; - } else - ent[i] = n; /* set entity name */ - } else if (!strncmp(s, "")) == '>') - continue; - else - *s = '\0'; /* null terminate tag name */ - for (i = 0; root->attr[i] && strcmp(n, root->attr[i][0]); i++) - ; - - ++s; - while (*(n = s + strspn(s, EZXML_WS)) && *n != '>') { - if (*(s = n + strcspn(n, EZXML_WS))) - *s = '\0'; /* attr name */ - else { - ezxml_err(root, t, "malformed ") - 1; - if (*c == ' ') - continue; /* cdata is default, nothing to do */ - v = NULL; - } else { - /* Jason Luu, Aug 29, 2007. Removed assignment in conditional statement */ - s = strchr(v = s + 1, *s); - if ((*s == '"' || *s == '\'') && /* default value */ - s) - *s = '\0'; - else { - ezxml_err(root, t, "malformed attr[i]) { /* new tag name */ - root->attr = - (!i) ? (char***)malloc(2 * sizeof(char **)) : (char***)realloc( - root->attr, - (i + 2) * sizeof(char **)); - root->attr[i] = (char**)malloc(2 * sizeof(char *)); - root->attr[i][0] = t; /* set tag name */ - root->attr[i][1] = (char *) (root->attr[i + 1] = NULL); - } - - for (j = 1; root->attr[i][j]; j += 3) - ; /* find end of list */ - root->attr[i] = (char**)realloc(root->attr[i], - (j + 4) * sizeof(char *)); - - root->attr[i][j + 3] = NULL; /* null terminate list */ - root->attr[i][j + 2] = c; /* is it cdata? */ - root->attr[i][j + 1] = - (v) ? ezxml_decode(v, root->ent, *c) : NULL; - root->attr[i][j] = n; /* attribute name */ - - ++s; - } - } else if (!strncmp(s, ""); /* comments */ - } - else if (!strncmp(s, ""); - if (s) - ezxml_proc_inst(root, c, s++ - c); - } else if (*s == '<') - s = strchr(s, '>'); /* skip other declarations */ - else if (*(s++) == '%' && !root->standalone) - break; - } - - free(pe); - return !*root->err; -} - -/* Converts a UTF-16 string to UTF-8. Returns a new string that must be freed */ -/* or NULL if no conversion was needed. */ -static char * -ezxml_str2utf8(char **s, size_t * len) { - char *u; - size_t l = 0, sl, max = *len; - long c, d; - int b, be = (**s == '\xFE') ? 1 : (**s == '\xFF') ? 0 : -1; - - if (be == -1) - return NULL; /* not UTF-16 */ - - u = (char*)malloc(max); - for (sl = 2; sl < *len - 1; sl += 2) { - c = (be) ? (((*s)[sl] & 0xFF) << 8) | ((*s)[sl + 1] & 0xFF) /*UTF-16BE */ - : - (((*s)[sl + 1] & 0xFF) << 8) | ((*s)[sl] & 0xFF); /*UTF-16LE */ - if (c >= 0xD800 && c <= 0xDFFF && (sl += 2) < *len - 1) { /* high-half */ - d = (be) ? - (((*s)[sl] & 0xFF) << 8) | ((*s)[sl + 1] & 0xFF) : - (((*s)[sl + 1] & 0xFF) << 8) | ((*s)[sl] & 0xFF); - c = (((c & 0x3FF) << 10) | (d & 0x3FF)) + 0x10000; - } - - while (l + 6 > max) - u = (char*)realloc(u, max += EZXML_BUFSIZE); - if (c < 0x80) - u[l++] = (char)c; /* US-ASCII subset */ - else { /* multi-byte UTF-8 sequence */ - for (b = 0, d = c; d; d /= 2) - b++; /* bits in c */ - b = (b - 2) / 5; /* bytes in payload */ - u[l++] = (char)((0xFF << (7 - b)) | (c >> (6 * b))); /* head */ - while (b) - u[l++] = 0x80 | ((c >> (6 * --b)) & 0x3F); /* payload */ - } - } - return *s = (char*)realloc(u, *len = l); -} - -/* frees a tag attribute list */ -static void ezxml_free_attr(char **attr) { - int i = 0; - char *m; - - if (!attr || attr == EZXML_NIL) - return; /* nothing to free */ - while (attr[i]) - i += 2; /* find end of attribute list */ - m = attr[i + 1]; /* list of which names and values are malloced */ - for (i = 0; m[i]; i++) { - if (m[i] & EZXML_NAMEM) - free(attr[i * 2]); - if (m[i] & EZXML_TXTM) - free(attr[(i * 2) + 1]); - } - free(m); - free(attr); -} - -/* parse the given xml string and return an ezxml structure */ -/* Jason Luu June 22, 2010, Added line number support */ -ezxml_t ezxml_parse_str(char *s, size_t len) { - ezxml_root_t root = (ezxml_root_t) ezxml_new(0); - char q, e, *d, *temp, **attr, **a = NULL; /* initialize a to avoid compile warning */ - int l, i, j; - int line = 1; - - root->m = s; - if (!len) - return ezxml_err(root, NULL, "root tag missing"); - root->u = ezxml_str2utf8(&s, &len); /* convert utf-16 to utf-8 */ - root->e = (root->s = s) + len; /* record start and end of work area */ - - e = s[len - 1]; /* save end char */ - s[len - 1] = '\0'; /* turn end char into null terminator */ - - while (*s && *s != '<') - s++; /* find first tag */ - if (!*s) - return ezxml_err(root, s, "root tag missing"); - - for (;;) { - attr = (char **) EZXML_NIL; - d = ++s; - - if (isalpha(*s) || *s == '_' || *s == ':' || *s < '\0') { /* new tag */ - if (!root->cur) - return ezxml_err(root, d, "markup outside of root element"); - - s += strcspn(s, EZXML_WS "/>"); - while (isspace(*s)) { - if (*s == '\n') - line++; - *(s++) = '\0'; /* null terminate tag name */ - } - - if (*s && *s != '/' && *s != '>') { /* find tag in default attr list */ - /* Jason Luu, Aug 29, 2007. Removed assignment in conditional statement */ - a = root->attr[0]; - for (i = 0; a && strcmp(a[0], d); i++) { - a = root->attr[i]; - } - } - - for (l = 0; *s && *s != '/' && *s != '>'; l += 2) { /* new attrib */ - attr = (l) ? - (char**)realloc(attr, (l + 4) * sizeof(char *)) : - (char**)malloc(4 * sizeof(char *)); /* allocate space */ - attr[l + 3] = - (l) ? (char*)realloc(attr[l + 1], (l / 2) + 2) : (char*)malloc(2); /* mem for list of maloced vals */ - strcpy(attr[l + 3] + (l / 2), " "); /* value is not malloced */ - attr[l + 2] = NULL; /* null terminate list */ - attr[l + 1] = ""; /* temporary attribute value */ - attr[l] = s; /* set attribute name */ - - s += strcspn(s, EZXML_WS "=/>"); - if (*s == '=' || isspace(*s)) { - if (*s == '\n') - line++; - *(s++) = '\0'; /* null terminate tag attribute name */ - q = *(s += strspn(s, EZXML_WS "=")); - if (q == '"' || q == '\'') { /* attribute value */ - attr[l + 1] = ++s; - while (*s && *s != q) - s++; - if (*s) - *(s++) = '\0'; /* null terminate attribute val */ - else { - ezxml_free_attr(attr); - return ezxml_err(root, d, "missing %c", q); - } - - for (j = 1; a && a[j] && strcmp(a[j], attr[l]); j += 3) - ; - attr[l + 1] = ezxml_decode(attr[l + 1], - root->ent, (a && a[j]) ? *a[j + 2] : ' '); - if (attr[l + 1] < d || attr[l + 1] > s) - attr[l + 3][l / 2] = EZXML_TXTM; /* value malloced */ - } - } - while (isspace(*s)) { - if (*s == '\n') - line++; - s++; - } - } - - if (*s == '/') { /* self closing tag */ - *(s++) = '\0'; - if ((*s && *s != '>') || (!*s && e != '>')) { - if (l) - ezxml_free_attr(attr); - return ezxml_err(root, d, "missing >"); - } - ezxml_open_tag(root, line, d, attr); - ezxml_close_tag(root, d, s); - } else if ((q = *s) == '>' || (!*s && e == '>')) { /* open tag */ - *s = '\0'; /* temporarily null terminate tag name */ - ezxml_open_tag(root, line, d, attr); - *s = q; - } else { - if (l) - ezxml_free_attr(attr); - return ezxml_err(root, d, "missing >"); - } - } else if (*s == '/') { /* close tag */ - s += strcspn(d = s + 1, EZXML_WS ">") + 1; - /* Jason Luu, Aug 29, 2007. Removed assignment in conditional statement */ - q = *s; - if (!q && e != '>') - return ezxml_err(root, d, "missing >"); - *s = '\0'; /* temporarily null terminate tag name */ - if (ezxml_close_tag(root, d, s)) - return &root->xml; - if (isspace(*s = q)) { - if (*s == '\n') - line++; - s += strspn(s, EZXML_WS); - } - } else if (!strncmp(s, "!--", 3)) { /* xml comment */ - temp = s; - s = strstr(s + 3, "--"); - if (!s || (*(s += 2) != '>' && *s) || (!*s && e != '>')) - return ezxml_err(root, d, "unclosed - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255e-12 - 255e-12 - 255e-12 - 255e-12 - 255e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/vpr7_x2p/vpr/ARCH/.travis_k6_N10_sram_chain_HC.xml b/vpr7_x2p/vpr/ARCH/.travis_k6_N10_sram_chain_HC.xml deleted file mode 100644 index d157a7f93..000000000 --- a/vpr7_x2p/vpr/ARCH/.travis_k6_N10_sram_chain_HC.xml +++ /dev/null @@ -1,1040 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml b/vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml deleted file mode 100755 index f7cc298a6..000000000 --- a/vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml +++ /dev/null @@ -1,1453 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 0e-12 0e-12 - - - 10e-12 0e-12 0e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 0e-12 0e-12 - - - 10e-12 0e-12 0e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.I[19:0] clb.O[4:0] - clb.I[39:20] clb.O[9:5] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_6Input.xml b/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_6Input.xml deleted file mode 100755 index d0e972fab..000000000 --- a/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_6Input.xml +++ /dev/null @@ -1,1040 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - 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255e-12 - 255e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_template.xml b/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_template.xml deleted file mode 100644 index 3000f66f2..000000000 --- a/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_template.xml +++ /dev/null @@ -1,1011 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 10e-12 10e-12 - - - 10e-12 10e-12 10e-12 - - - - - - - - - - - 10e-12 10e-12 - - - 10e-12 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 255e-12 - 255e-12 - 255e-12 - 255e-12 - 255e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 202e-12 - 202e-12 - 202e-12 - 202e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.cin clb.cin_trick clb.regin clb.clk - clb.I0[9:0] clb.I1[9:0] clb.O[9:0] - clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] - - - - - - - - - - - - - - - - - - diff --git a/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml b/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml deleted file mode 100755 index 426bcdcf6..000000000 --- a/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml +++ /dev/null @@ -1,882 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - - - - - - - - - - - 10e-12 0e-12 0e-12 - - - 10e-12 0e-12 0e-12 - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/vpr7_x2p/vpr/ARCH/k6_N10_sram_ptm45nm_TT.xml b/vpr7_x2p/vpr/ARCH/k6_N10_sram_ptm45nm_TT.xml deleted file mode 100755 index 5b9b4727a..000000000 --- a/vpr7_x2p/vpr/ARCH/k6_N10_sram_ptm45nm_TT.xml +++ /dev/null @@ -1,1452 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 0e-12 0e-12 - - - 10e-12 0e-12 0e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.I[19:0] clb.O[4:0] - clb.I[39:20] clb.O[9:5] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/vpr7_x2p/vpr/CMakeLists.txt b/vpr7_x2p/vpr/CMakeLists.txt deleted file mode 100644 index 1afd484cd..000000000 --- a/vpr7_x2p/vpr/CMakeLists.txt +++ /dev/null @@ -1,88 +0,0 @@ -cmake_minimum_required(VERSION 2.8.12) - -if (${CMAKE_VERSION} VERSION_GREATER "3.8") - #For cmake >= 3.9 INTERPROCEDURAL_OPTIMIZATION behaviour we need to explicitly - #set the cmake policy version number - cmake_policy(VERSION 3.9) - - # If we are using verison < 3.9 then setting INTERPROCEDURAL_OPTIMIZATION - # has no effect unless an Intel compiler is used -endif() - -project("vpr7_x2p" C CXX) - -# idenify if we need graphics -set(ENABLE_VPR_GRAPHIC_CXX_FLAG true) -message(STATUS "Checking VPR graphics option ${ENABLE_VPR_GRAPHICS}") -if (ENABLE_VPR_GRAPHICS) - # check for dependencies - message(STATUS "VPR graphics is turned on, searching for dependencies") - find_package(X11) - - if (NOT X11_FOUND) - message(WARNING "Failed to find required X11 library (on debian/ubuntu try 'sudo apt-get install libx11-dev' to install)") - #Disable - set(ENABLE_VPR_GRAPHIC_CXX_FLAG false) - endif() -else () - set(ENABLE_VPR_GRAPHIC_CXX_FLAG false) -endif() - -if (NOT ENABLE_VPR_GRAPHIC_CXX_FLAG) - # Add a flag to notify compiler not to consider graphic-related source codes - set (DISABLE_GRAPHIC_FLAGS "-DNO_GRAPHICS") - set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${DISABLE_GRAPHIC_FLAGS}") - message(STATUS "Add flags to disable graphics in VPR compilation: ${DISABLE_GRAPHIC_FLAGS}") -endif() - -# We need readline to compile -find_package(Readline REQUIRED) - -#Collect the source files -file(GLOB_RECURSE EXEC_SOURCES SRC/main.c) -file(GLOB_RECURSE EXEC_SOURCES_SHELL SRC/shell_main.c) -file(GLOB_RECURSE LIB_SOURCES SRC/*/*.c SRC/*/*/*.c SRC/*/*.cpp SRC/*/*/*.cpp) -file(GLOB_RECURSE LIB_HEADERS SRC/*/*.h SRC/*/*/*.h) -files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS) - -# Use c++ compiler for c source files -set_source_files_properties(${LIB_SOURCES} PROPERTIES LANGUAGE CXX) -set_source_files_properties(${EXEC_SOURCES} PROPERTIES LANGUAGE CXX) -set_source_files_properties(${EXEC_SOURCES_SHELL} PROPERTIES LANGUAGE CXX) - -#Create the library -add_library(libvpr STATIC - ${LIB_HEADERS} - ${LIB_SOURCES}) - -# add header files to be included -target_include_directories(libvpr PUBLIC ${LIB_INCLUDE_DIRS}) -set_target_properties(libvpr PROPERTIES PREFIX "") #Avoid extra 'lib' prefix#Create the executable - -#Specify link-time dependancies -if (ENABLE_VPR_GRAPHIC_CXX_FLAG) - target_link_libraries(libvpr - libarchfpgavpr7 - X11 - libvtrutil - libini - readline) -else () - target_link_libraries(libvpr - libarchfpgavpr7 - libvtrutil - libini - readline) -endif() - -#Create the executables -# regular vpr interface -add_executable(vpr ${EXEC_SOURCES}) -target_link_libraries(vpr - libvpr) - -# Shell-interface vpr -add_executable(vpr_shell ${EXEC_SOURCES_SHELL}) -target_link_libraries(vpr_shell - libvpr) - diff --git a/vpr7_x2p/vpr/Circuits/test_modes.act b/vpr7_x2p/vpr/Circuits/test_modes.act deleted file mode 100644 index a58956a8e..000000000 --- a/vpr7_x2p/vpr/Circuits/test_modes.act +++ /dev/null @@ -1,67 +0,0 @@ -cint01 0.485400 0.188600 -n01 0.489000 0.213200 -cint02 0.502400 0.203200 -n02 0.509200 0.195200 -cint03 0.507200 0.192200 -n03 0.502400 0.201600 -cint04 0.463200 0.199400 -n04 0.522000 0.191000 -n05 0.486800 0.204800 -reg0 0.463000 0.195400 -reg1 0.487400 0.196600 -reg2 0.506200 0.195000 -reg3 0.492200 0.208200 -reg4 0.507200 0.204800 -reg5 0.500400 0.200600 -reg6 0.500800 0.203400 -reg7 0.509600 0.198800 -reg8 0.492200 0.188000 -reg9 0.504800 0.204400 -reg10 0.507600 0.203200 -reg11 0.494200 0.203600 -clk 0.534600 0.203800 -a_0 0.478200 0.203800 -a_1 0.514800 0.208600 -a_2 0.505800 0.204600 -a_3 0.500000 0.195200 -b_0 0.530800 0.192800 -b_1 0.495800 0.195400 -b_2 0.496600 0.201200 -b_3 0.492000 0.200200 -cin 0.502600 0.202200 -e 0.495200 0.201000 -f 0.504000 0.203400 -g 0.498200 0.202000 -reg_a_0 0.478200 0.203800 -reg_a_1 0.514800 0.208600 -reg_a_2 0.505800 0.204600 -reg_a_3 0.500000 0.195200 -reg_b_0 0.530800 0.192800 -reg_b_1 0.495800 0.195400 -reg_b_2 0.496600 0.201200 -reg_b_3 0.492000 0.200200 -reg_cin 0.502600 0.202200 -sum_0 0.489000 0.213200 -sum_1 0.509200 0.195200 -sum_2 0.502400 0.201600 -sum_3 0.522000 0.191000 -cout 0.486800 0.204800 -ref0 0.000000 0.000000 -n57 0.478200 0.097457 -n62 0.514800 0.107387 -n67 0.505800 0.103487 -n72 0.500000 0.097600 -n77 0.530800 0.102338 -n82 0.495800 0.096879 -n87 0.496600 0.099916 -n92 0.492000 0.098498 -n97 0.502600 0.101626 -d0 0.617800 0.046719 -x 0.492200 0.102476 -y 0.509600 0.101308 -z 0.494200 0.100619 -n102 0.489000 0.104255 -n106 0.509200 0.099396 -n110 0.502400 0.101284 -n114 0.522000 0.099702 -n118 0.486800 0.099697 diff --git a/vpr7_x2p/vpr/Circuits/test_modes.blif b/vpr7_x2p/vpr/Circuits/test_modes.blif deleted file mode 100644 index d63bca69d..000000000 --- a/vpr7_x2p/vpr/Circuits/test_modes.blif +++ /dev/null @@ -1,93 +0,0 @@ -# Benchmark "test" written by ABC on Tue Apr 30 17:17:10 2019 -.model test_modes -.inputs clk a_0 a_1 a_2 a_3 b_0 b_1 b_2 b_3 cin e f g -.outputs sum_0 sum_1 sum_2 sum_3 cout x y z - -.latch n57 reg_a_0 re clk 0 -.latch n62 reg_a_1 re clk 0 -.latch n67 reg_a_2 re clk 0 -.latch n72 reg_a_3 re clk 0 -.latch n77 reg_b_0 re clk 0 -.latch n82 reg_b_1 re clk 0 -.latch n87 reg_b_2 re clk 0 -.latch n92 reg_b_3 re clk 0 -.latch n97 reg_cin re clk 0 -.latch n102 sum_0 re clk 0 -.latch n106 sum_1 re clk 0 -.latch n110 sum_2 re clk 0 -.latch n114 sum_3 re clk 0 -.latch n118 cout re clk 0 - - -.subckt adder a=reg_a_0 b=reg_b_0 cin=reg_cin cout=cint01 sumout=n01 -.subckt adder a=reg_a_1 b=reg_b_1 cin=cint01 cout=cint02 sumout=n02 -.subckt adder a=reg_a_2 b=reg_b_2 cin=cint02 cout=cint03 sumout=n03 -.subckt adder a=reg_a_3 b=reg_b_3 cin=cint03 cout=cint04 sumout=n04 -.subckt adder a=ref0 b=ref0 cin=cint04 cout=unconn sumout=n05 -.subckt shift D=d0 clk=clk Q=reg0 -.subckt shift D=reg0 clk=clk Q=reg1 -.subckt shift D=reg1 clk=clk Q=reg2 -.subckt shift D=reg2 clk=clk Q=reg3 -.subckt shift D=reg3 clk=clk Q=reg4 -.subckt shift D=reg4 clk=clk Q=reg5 -.subckt shift D=reg5 clk=clk Q=reg6 -.subckt shift D=reg6 clk=clk Q=reg7 -.subckt shift D=reg7 clk=clk Q=reg8 -.subckt shift D=reg8 clk=clk Q=reg9 -.subckt shift D=reg9 clk=clk Q=reg10 -.subckt shift D=reg10 clk=clk Q=reg11 - -.names ref0 - 0 -.names a_0 n57 -1 1 -.names a_1 n62 -1 1 -.names a_2 n67 -1 1 -.names a_3 n72 -1 1 -.names b_0 n77 -1 1 -.names b_1 n82 -1 1 -.names b_2 n87 -1 1 -.names b_3 n92 -1 1 -.names cin n97 -1 1 -.names e f g d0 -1-1 1 --0- 1 -.names reg3 x -1 1 -.names reg7 y -1 1 -.names reg11 z -1 1 -.names n01 n102 -1 1 -.names n02 n106 -1 1 -.names n03 n110 -1 1 -.names n04 n114 -1 1 -.names n05 n118 -1 1 -.end - - -.model adder -.inputs a b cin -.outputs cout sumout -.blackbox -.end - - -.model shift -.inputs D clk -.outputs Q -.blackbox -.end diff --git a/vpr7_x2p/vpr/Circuits/test_modes.v b/vpr7_x2p/vpr/Circuits/test_modes.v deleted file mode 100644 index 8090d2903..000000000 --- a/vpr7_x2p/vpr/Circuits/test_modes.v +++ /dev/null @@ -1,78 +0,0 @@ -//////////////////////////////////////////////////////// -// // -// Benchmark using all modes of k8 architecture // -// // -//////////////////////////////////////////////////////// - -`timescale 1 ns/ 1 ps - -module test_modes( - clk, - a_0, - a_1, - a_2, - a_3, - b_0, - b_1, - b_2, - b_3, - cin, - e, - f, - g, - sum_0, - sum_1, - sum_2, - sum_3, - cout, - x, - y, - z ); - - input wire clk, a_0, a_1, a_2, a_3, b_0, b_1, b_2, b_3, cin, e, f, g; - output reg sum_0, sum_1, sum_2, sum_3, cout; - output wire x, y, z; - - wire d0; - wire [4:0] n0; - wire [3:0] a, b; - reg reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg_a_0, reg_a_1, reg_a_2, reg_a_3, reg_b_0, reg_b_1, reg_b_2, reg_b_3, reg_cin; - - assign a = {reg_a_3, reg_a_2, reg_a_1, reg_a_0}; - assign b = {reg_b_3, reg_b_2, reg_b_1, reg_b_0}; - assign d0 = (e && g) || !f; - assign n0 = a + b + reg_cin; - assign x = reg3; - assign y = reg7; - assign z = reg11; - - always @(posedge clk) begin - reg0 <= d0; - reg1 <= reg0; - reg2 <= reg1; - reg3 <= reg2; - reg4 <= reg3; - reg5 <= reg4; - reg6 <= reg5; - reg7 <= reg6; - reg8 <= reg7; - reg9 <= reg8; - reg10 <= reg9; - reg11 <= reg10; - reg_a_0 <= a_0; - reg_a_1 <= a_1; - reg_a_2 <= a_2; - reg_a_3 <= a_3; - reg_b_0 <= b_0; - reg_b_1 <= b_1; - reg_b_2 <= b_2; - reg_b_3 <= b_3; - reg_cin <= cin; - sum_0 <= n0[0]; - sum_1 <= n0[1]; - sum_2 <= n0[2]; - sum_3 <= n0[3]; - cout <= n0[4]; - end - -endmodule diff --git a/vpr7_x2p/vpr/SRC/base/CheckArch.c b/vpr7_x2p/vpr/SRC/base/CheckArch.c deleted file mode 100644 index 278f9d320..000000000 --- a/vpr7_x2p/vpr/SRC/base/CheckArch.c +++ /dev/null @@ -1,63 +0,0 @@ -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "OptionTokens.h" -#include "ReadOptions.h" -#include "read_xml_arch_file.h" -#include "SetupVPR.h" - -/******** Function Prototypes ********/ -static void CheckSwitches(INP t_arch Arch, INP boolean TimingEnabled); - -static void CheckSegments(INP t_arch Arch); - -/******** Function Implementations ********/ - -void CheckArch(INP t_arch Arch, INP boolean TimingEnabled) { - CheckSwitches(Arch, TimingEnabled); - CheckSegments(Arch); -} - -static void CheckSwitches(INP t_arch Arch, INP boolean TimingEnabled) { - struct s_switch_inf *CurSwitch; - int i; - - /* Check transistors in switches won't be less than minimum size */ - CurSwitch = Arch.Switches; - for (i = 0; i < Arch.num_switches; i++) { - /* This assumes all segments have the same directionality */ - if (CurSwitch->buffered - && Arch.Segments[0].directionality == BI_DIRECTIONAL) { - /* Largest resistance tri-state buffer would have a minimum - * width transistor in the buffer pull-down and a min-width - * pass transistoron the output. - * Hence largest R = 2 * largest_transistor_R. */ - if (CurSwitch->R > 2 * Arch.R_minW_nmos) { - vpr_printf(TIO_MESSAGE_ERROR, "Switch %s R value (%g) is greater than 2 * R_minW_nmos (%g).\n", - CurSwitch->name, CurSwitch->R, (2 * Arch.R_minW_nmos)); - exit(1); - } - } else { /* Pass transistor switch */ - if (CurSwitch->R > Arch.R_minW_nmos) { - vpr_printf(TIO_MESSAGE_ERROR, "Switch %s R value (%g) is greater than R_minW_nmos (%g).\n", - CurSwitch->name, CurSwitch->R, Arch.R_minW_nmos); - exit(1); - } - } - } -} - -static void CheckSegments(INP t_arch Arch) { - t_segment_inf *CurSeg; - int i; - - CurSeg = Arch.Segments; - for (i = 0; i < Arch.num_segments; i++) { - if (CurSeg[i].directionality == UNI_DIRECTIONAL - && CurSeg[i].longline == TRUE) { - vpr_printf(TIO_MESSAGE_ERROR, "Long lines not supported for unidirectional architectures.\n"); - exit(1); - } - } -} diff --git a/vpr7_x2p/vpr/SRC/base/CheckOptions.c b/vpr7_x2p/vpr/SRC/base/CheckOptions.c deleted file mode 100644 index aeaeeaff5..000000000 --- a/vpr7_x2p/vpr/SRC/base/CheckOptions.c +++ /dev/null @@ -1,204 +0,0 @@ -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "OptionTokens.h" -#include "ReadOptions.h" -#include "read_xml_arch_file.h" -#include "SetupVPR.h" - -/* Checks that options don't conflict and that - * options aren't specified that may conflict */ -void CheckOptions(INP t_options Options, INP boolean TimingEnabled) { - boolean TimingPlacer; - boolean TimingRouter; - boolean default_flow; - - const struct s_TokenPair *Cur; - enum e_OptionBaseToken Yes; - - default_flow = (boolean) (Options.Count[OT_ROUTE] == 0 - && Options.Count[OT_PLACE] == 0 && Options.Count[OT_PACK] == 0 - && Options.Count[OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY] == 0); - - /* Check that all filenames were given */ - if ((NULL == Options.CircuitName) || (NULL == Options.ArchFile)) { - vpr_printf(TIO_MESSAGE_ERROR, "Not enough args. Need at least 'vpr '.\n"); - exit(1); - } - - /* Check that options aren't over specified */ - Cur = OptionBaseTokenList; - while (Cur->Str) { - if (Options.Count[Cur->Enum] > 1) { - vpr_printf(TIO_MESSAGE_ERROR, "Parameter '%s' was specified more than once on command line.\n", Cur->Str); - exit(1); - } - ++Cur; - } - - /* Todo: Add in checks for packer */ - - /* Check for conflicting parameters and determine if placer and - * router are on. */ - - if (Options.Count[OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY] - && (Options.Count[OT_PACK] || Options.Count[OT_PLACE] - || Options.Count[OT_ROUTE])) { - vpr_printf(TIO_MESSAGE_ERROR, "'cluster'/'route'/'place', and 'timing_analysis_only_with_net_delay' are mutually exclusive flags..\n"); - exit(1); - } - - /* If placing and timing is enabled, default to a timing placer */ - TimingPlacer = (boolean)((Options.Count[OT_PLACE] || default_flow) && TimingEnabled); - if (Options.Count[OT_PLACE_ALGORITHM] > 0) { - if ((PATH_TIMING_DRIVEN_PLACE != Options.PlaceAlgorithm) - && (NET_TIMING_DRIVEN_PLACE != Options.PlaceAlgorithm)) { - /* Turn off the timing placer if they request a different placer */ - TimingPlacer = FALSE; - } - } - - /* If routing and timing is enabled, default to a timing router */ - TimingRouter = (boolean)((Options.Count[OT_ROUTE] || default_flow) && TimingEnabled); - if (Options.Count[OT_ROUTER_ALGORITHM] > 0) { - if (TIMING_DRIVEN != Options.RouterAlgorithm) { - /* Turn off the timing router if they request a different router */ - TimingRouter = FALSE; - } - } - - Yes = OT_BASE_UNKNOWN; - if (Options.Count[OT_SEED] > 0) { - Yes = OT_SEED; - } - if (Options.Count[OT_INNER_NUM] > 0) { - Yes = OT_INNER_NUM; - } - if (Options.Count[OT_INIT_T] > 0) { - Yes = OT_INIT_T; - } - if (Options.Count[OT_ALPHA_T] > 0) { - Yes = OT_ALPHA_T; - } - if (Options.Count[OT_EXIT_T] > 0) { - Yes = OT_EXIT_T; - } - if (Options.Count[OT_FIX_PINS] > 0) { - Yes = OT_FIX_PINS; - } - if (Options.Count[OT_PLACE_ALGORITHM] > 0) { - Yes = OT_PLACE_ALGORITHM; - } - if (Options.Count[OT_PLACE_COST_EXP] > 0) { - Yes = OT_PLACE_COST_EXP; - } - if (Options.Count[OT_PLACE_CHAN_WIDTH] > 0) { - Yes = OT_PLACE_CHAN_WIDTH; - } - if (Options.Count[OT_ENABLE_TIMING_COMPUTATIONS] > 0) { - Yes = OT_ENABLE_TIMING_COMPUTATIONS; - } - if (Options.Count[OT_BLOCK_DIST] > 0) { - Yes = OT_BLOCK_DIST; - } - /* Make sure if place is off none of those options were given */ - if ((Options.Count[OT_PLACE] == 0) && !default_flow - && (Yes < OT_BASE_UNKNOWN)) { - Cur = OptionBaseTokenList; - while (Cur->Str) { - if (Yes == Cur->Enum) { - vpr_printf(TIO_MESSAGE_ERROR, "Option '%s' is not allowed when placement is not run.\n", Cur->Str); - exit(1); - } - ++Cur; - } - } - - Yes = OT_BASE_UNKNOWN; - if (Options.Count[OT_TIMING_TRADEOFF] > 0) { - Yes = OT_TIMING_TRADEOFF; - } - if (Options.Count[OT_RECOMPUTE_CRIT_ITER] > 0) { - Yes = OT_RECOMPUTE_CRIT_ITER; - } - if (Options.Count[OT_INNER_LOOP_RECOMPUTE_DIVIDER] > 0) { - Yes = OT_INNER_LOOP_RECOMPUTE_DIVIDER; - } - if (Options.Count[OT_TD_PLACE_EXP_FIRST] > 0) { - Yes = OT_TD_PLACE_EXP_FIRST; - } - if (Options.Count[OT_TD_PLACE_EXP_LAST] > 0) { - Yes = OT_TD_PLACE_EXP_LAST; - } - /* Make sure if place is off none of those options were given */ - if ((FALSE == TimingPlacer) && (Yes < OT_BASE_UNKNOWN)) { - Cur = OptionBaseTokenList; - while (Cur->Str) { - if (Yes == Cur->Enum) { - vpr_printf(TIO_MESSAGE_ERROR, "Option '%s' is not allowed when timing placement is not used.\n", Cur->Str); - exit(1); - } - ++Cur; - } - } - - Yes = OT_BASE_UNKNOWN; - if (Options.Count[OT_ROUTE_TYPE] > 0) { - Yes = OT_ROUTE_TYPE; - } - if (Options.Count[OT_ROUTE_CHAN_WIDTH] > 0) { - Yes = OT_ROUTE_CHAN_WIDTH; - } - if (Options.Count[OT_ROUTER_ALGORITHM] > 0) { - Yes = OT_ROUTER_ALGORITHM; - } - if (Options.Count[OT_MAX_ROUTER_ITERATIONS] > 0) { - Yes = OT_MAX_ROUTER_ITERATIONS; - } - if (Options.Count[OT_INITIAL_PRES_FAC] > 0) { - Yes = OT_INITIAL_PRES_FAC; - } - if (Options.Count[OT_FIRST_ITER_PRES_FAC] > 0) { - Yes = OT_FIRST_ITER_PRES_FAC; - } - if (Options.Count[OT_PRES_FAC_MULT] > 0) { - Yes = OT_PRES_FAC_MULT; - } - if (Options.Count[OT_ACC_FAC] > 0) { - Yes = OT_ACC_FAC; - } - if (Options.Count[OT_BB_FACTOR] > 0) { - Yes = OT_BB_FACTOR; - } - if (Options.Count[OT_BASE_COST_TYPE] > 0) { - Yes = OT_BASE_COST_TYPE; - } - if (Options.Count[OT_BEND_COST] > 0) { - Yes = OT_BEND_COST; - } - if (Options.Count[OT_BASE_COST_TYPE] > 0) { - Yes = OT_BASE_COST_TYPE; - } - if (Options.Count[OT_ASTAR_FAC] > 0) { - Yes = OT_ASTAR_FAC; - } - Yes = OT_BASE_UNKNOWN; - if (Options.Count[OT_MAX_CRITICALITY] > 0) { - Yes = OT_MAX_CRITICALITY; - } - if (Options.Count[OT_CRITICALITY_EXP] > 0) { - Yes = OT_CRITICALITY_EXP; - } - /* Make sure if timing router is off none of those options were given */ - if ((FALSE == TimingRouter) && (Yes < OT_BASE_UNKNOWN)) { - Cur = OptionBaseTokenList; - while (Cur->Str) { - if (Yes == Cur->Enum) { - vpr_printf(TIO_MESSAGE_ERROR, "Option '%s' is not allowed when timing router is not used.\n", Cur->Str); - exit(1); - } - ++Cur; - } - } -} diff --git a/vpr7_x2p/vpr/SRC/base/CheckSetup.c b/vpr7_x2p/vpr/SRC/base/CheckSetup.c deleted file mode 100644 index e72b3d0db..000000000 --- a/vpr7_x2p/vpr/SRC/base/CheckSetup.c +++ /dev/null @@ -1,98 +0,0 @@ -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "OptionTokens.h" -#include "ReadOptions.h" -#include "read_xml_arch_file.h" -#include "SetupVPR.h" - -void CheckSetup(INP enum e_operation Operation, - INP struct s_placer_opts PlacerOpts, - INP struct s_annealing_sched AnnealSched, - INP struct s_router_opts RouterOpts, - INP struct s_det_routing_arch RoutingArch, INP t_segment_inf * Segments, - INP t_timing_inf Timing, INP t_chan_width_dist Chans) { - int i; - int Tmp; - - if ((GLOBAL == RouterOpts.route_type) - && (TIMING_DRIVEN == RouterOpts.router_algorithm)) { - - vpr_printf(TIO_MESSAGE_ERROR, "The global router does not support timing-drvien routing.\n"); - exit(1); - } - - if ((GLOBAL == RouterOpts.route_type) - && (BOUNDING_BOX_PLACE != PlacerOpts.place_algorithm)) { - - /* Works, but very weird. Can't optimize timing well, since you're - * not doing proper architecture delay modelling. */ - vpr_printf(TIO_MESSAGE_WARNING, "Using global routing with timing-driven placement. " - "This is allowed, but strange, and circuit speed will suffer.\n"); - } - - if ((FALSE == Timing.timing_analysis_enabled) - && ((PlacerOpts.place_algorithm == NET_TIMING_DRIVEN_PLACE) - || (PlacerOpts.place_algorithm == PATH_TIMING_DRIVEN_PLACE))) { - - /* May work, not tested */ - vpr_printf(TIO_MESSAGE_ERROR, "Timing analysis must be enabled for timing-driven placement.\n"); - exit(1); - } - - if (!PlacerOpts.doPlacement && (USER == PlacerOpts.pad_loc_type)) { - vpr_printf(TIO_MESSAGE_ERROR, "A pad location file requires that placement is enabled.\n"); - exit(1); - } - - if (RouterOpts.doRouting) { - if ((TIMING_DRIVEN == RouterOpts.router_algorithm) - && (FALSE == Timing.timing_analysis_enabled)) { - vpr_printf(TIO_MESSAGE_ERROR, "Cannot perform timing-driven routing when timing analysis is disabled.\n"); - exit(1); - } - - if ((FALSE == Timing.timing_analysis_enabled) - && (DEMAND_ONLY != RouterOpts.base_cost_type)) { - vpr_printf(TIO_MESSAGE_ERROR, "base_cost_type must be demand_only when timing analysis is disabled.\n"); - exit(1); - } - } - - if ((TIMING_ANALYSIS_ONLY == Operation) - && (FALSE == Timing.timing_analysis_enabled)) { - vpr_printf(TIO_MESSAGE_ERROR, "-timing_analyze_only_with_net_delay option requires that timing analysis not be disabled.\n"); - exit(1); - } - - if (DETAILED == RouterOpts.route_type) { - if ((Chans.chan_x_dist.type != UNIFORM) - || (Chans.chan_y_dist.type != UNIFORM) - || (Chans.chan_x_dist.peak != Chans.chan_y_dist.peak) - || (Chans.chan_x_dist.peak != Chans.chan_width_io)) { - vpr_printf(TIO_MESSAGE_ERROR, "Detailed routing currently only supported on FPGAs with all channels of equal width.\n"); - exit(1); - } - } - - for (i = 0; i < RoutingArch.num_segment; ++i) { - Tmp = Segments[i].opin_switch; - if (FALSE == switch_inf[Tmp].buffered) { - vpr_printf(TIO_MESSAGE_ERROR, "opin_switch (#%d) of segment type #%d is not buffered.\n", Tmp, i); - exit(1); - } - } - - if (UNI_DIRECTIONAL == RoutingArch.directionality) { - if ((RouterOpts.fixed_channel_width != NO_FIXED_CHANNEL_WIDTH) - && (RouterOpts.fixed_channel_width % 2 > 0)) { - vpr_printf(TIO_MESSAGE_ERROR, "Routing channel width must be even for unidirectional.\n"); - exit(1); - } - if ((PlacerOpts.place_chan_width != NO_FIXED_CHANNEL_WIDTH) - && (PlacerOpts.place_chan_width % 2 > 0)) { - vpr_printf(TIO_MESSAGE_ERROR, "Place channel width must be even for unidirectional.\n"); - exit(1); - } - } -} diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.c b/vpr7_x2p/vpr/SRC/base/OptionTokens.c deleted file mode 100644 index ad1dd1629..000000000 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.c +++ /dev/null @@ -1,132 +0,0 @@ -#include "util.h" -#include "vpr_types.h" -#include "OptionTokens.h" - -/* OptionBaseTokenList is for command line arg tokens. We will track how - * many times each of these things exist in a file */ -struct s_TokenPair OptionBaseTokenList[] = { - { "settings_file", OT_SETTINGS_FILE }, { "nodisp", OT_NODISP }, { - "auto", OT_AUTO }, { "recompute_crit_iter", - OT_RECOMPUTE_CRIT_ITER }, { "inner_loop_recompute_divider", - OT_INNER_LOOP_RECOMPUTE_DIVIDER }, { "fix_pins", OT_FIX_PINS }, - { "full_stats", OT_FULL_STATS }, { "fast", OT_FAST }, { "echo_file", - OT_CREATE_ECHO_FILE }, { "gen_postsynthesis_netlist", - OT_GENERATE_POST_SYNTHESIS_NETLIST }, { "timing_analysis", - OT_TIMING_ANALYSIS }, { "timing_analyze_only_with_net_delay", - OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY }, - { "init_t", OT_INIT_T }, { "alpha_t", OT_ALPHA_T }, { "exit_t", - OT_EXIT_T }, { "inner_num", OT_INNER_NUM }, { "seed", OT_SEED }, - { "place_cost_exp", OT_PLACE_COST_EXP }, { "td_place_exp_first", - OT_TD_PLACE_EXP_FIRST }, { "td_place_exp_last", - OT_TD_PLACE_EXP_LAST }, - { "place_algorithm", OT_PLACE_ALGORITHM }, { "timing_tradeoff", - OT_TIMING_TRADEOFF }, { "enable_timing_computations", - OT_ENABLE_TIMING_COMPUTATIONS }, - { "block_dist", OT_BLOCK_DIST }, { "place_chan_width", - OT_PLACE_CHAN_WIDTH }, { "max_router_iterations", - OT_MAX_ROUTER_ITERATIONS }, { "bb_factor", OT_BB_FACTOR }, { - "router_algorithm", OT_ROUTER_ALGORITHM }, { - "first_iter_pres_fac", OT_FIRST_ITER_PRES_FAC }, { - "initial_pres_fac", OT_INITIAL_PRES_FAC }, { "pres_fac_mult", - OT_PRES_FAC_MULT }, { "acc_fac", OT_ACC_FAC }, { "astar_fac", - OT_ASTAR_FAC }, { "max_criticality", OT_MAX_CRITICALITY }, { - "criticality_exp", OT_CRITICALITY_EXP }, { "base_cost_type", - OT_BASE_COST_TYPE }, { "bend_cost", OT_BEND_COST }, { - "route_type", OT_ROUTE_TYPE }, { "route_chan_width", - OT_ROUTE_CHAN_WIDTH }, { "route", OT_ROUTE }, { "place", - OT_PLACE }, { "verify_binary_search", OT_VERIFY_BINARY_SEARCH }, - { "outfile_prefix", OT_OUTFILE_PREFIX }, { "blif_file", OT_BLIF_FILE }, - { "net_file", OT_NET_FILE }, { "place_file", OT_PLACE_FILE }, { - "route_file", OT_ROUTE_FILE }, { "sdc_file", OT_SDC_FILE }, { - "global_clocks", OT_GLOBAL_CLOCKS }, { "hill_climbing", - OT_HILL_CLIMBING_FLAG }, { "sweep_hanging_nets_and_inputs", - OT_SWEEP_HANGING_NETS_AND_INPUTS }, { "no_clustering", - OT_SKIP_CLUSTERING }, { "allow_unrelated_clustering", - OT_ALLOW_UNRELATED_CLUSTERING }, { "allow_early_exit", - OT_ALLOW_EARLY_EXIT }, { "connection_driven_clustering", - OT_CONNECTION_DRIVEN_CLUSTERING }, { "timing_driven_clustering", - OT_TIMING_DRIVEN_CLUSTERING }, { "cluster_seed_type", - OT_CLUSTER_SEED }, { "alpha_clustering", OT_ALPHA_CLUSTERING }, - { "beta_clustering", OT_BETA_CLUSTERING }, { "recompute_timing_after", - OT_RECOMPUTE_TIMING_AFTER }, { "cluster_block_delay", - OT_CLUSTER_BLOCK_DELAY }, { "intra_cluster_net_delay", - OT_INTRA_CLUSTER_NET_DELAY }, { "inter_cluster_net_delay", - OT_INTER_CLUSTER_NET_DELAY }, { "pack", OT_PACK }, { - "packer_algorithm", OT_PACKER_ALGORITHM }, /**/ - { "activity_file", OT_ACTIVITY_FILE }, /* Activity file */ - { "power_output_file", OT_POWER_OUT_FILE }, /* Output file for power results */ - { "power", OT_POWER }, /* Run power estimation? */ - { "tech_properties", OT_CMOS_TECH_BEHAVIOR_FILE }, /* Technology properties */ - /* Xifan Tang: Tileable routing support !!! */ - { "use_tileable_route_chan_width", OT_USE_TILEABLE_ROUTE_CHAN_WIDTH}, /* Enable adaption to tileable route chan_width */ - /* General FPGA_X2P: FPGA-SPICE/Verilog/Bitstream Options */ - { "fpga_x2p_rename_illegal_port", OT_FPGA_X2P_RENAME_ILLEGAL_PORT }, /* Xifan TANG: rename illegal port names */ - { "fpga_x2p_signal_density_weight", OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT }, /* The weight of signal density */ - { "fpga_x2p_sim_window_size", OT_FPGA_X2P_SIM_WINDOW_SIZE }, /* Window size in determining number of clock cycles in simulation */ - { "fpga_x2p_compact_routing_hierarchy", OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY }, /* use a compact routing hierarchy in SPICE/Verilog generation */ - { "fpga_x2p_output_sb_xml", OT_FPGA_X2P_OUTPUT_SB_XML }, /* use a compact routing hierarchy in SPICE/Verilog generation */ - { "fpga_x2p_duplicate_grid_pin", OT_FPGA_X2P_DUPLICATE_GRID_PIN }, /* Duplicate the pins at each side of a grid when generating SPICE and Verilog netlists */ - /* Xifan TANG: FPGA SPICE Support */ - { "fpga_spice", OT_FPGA_SPICE },/* Xifan TANG: SPICE Model Support, turn on the functionality*/ - { "fpga_spice_dir", OT_FPGA_SPICE_DIR },/* Xifan TANG: SPICE Model Support, directory of spice netlists*/ - { "fpga_spice_print_top_testbench", OT_FPGA_SPICE_PRINT_TOP_TESTBENCH }, /* Print the SPICE TOP Testbench for MUXes */ - { "fpga_spice_print_pb_mux_testbench", OT_FPGA_SPICE_PRINT_PB_MUX_TESTBENCH }, /* Print the SPICE Testbench for MUXes */ - { "fpga_spice_print_cb_mux_testbench", OT_FPGA_SPICE_PRINT_CB_MUX_TESTBENCH }, /* Print the SPICE Testbench for MUXes */ - { "fpga_spice_print_sb_mux_testbench", OT_FPGA_SPICE_PRINT_SB_MUX_TESTBENCH }, /* Print the SPICE Testbench for MUXes */ - { "fpga_spice_print_cb_testbench", OT_FPGA_SPICE_PRINT_CB_TESTBENCH }, /* Print the SPICE Testbench for CBs */ - { "fpga_spice_print_sb_testbench", OT_FPGA_SPICE_PRINT_SB_TESTBENCH }, /* Print the SPICE Testbench for SBs */ - { "fpga_spice_print_grid_testbench", OT_FPGA_SPICE_PRINT_GRID_TESTBENCH }, /* Print the SPICE Testbench for Grids */ - { "fpga_spice_print_lut_testbench", OT_FPGA_SPICE_PRINT_LUT_TESTBENCH }, /* Print the SPICE Testbench for Grids */ - { "fpga_spice_print_hardlogic_testbench", OT_FPGA_SPICE_PRINT_HARDLOGIC_TESTBENCH }, /* Print the SPICE Testbench for Grids */ - { "fpga_spice_print_io_testbench", OT_FPGA_SPICE_PRINT_IO_TESTBENCH }, /* Print the SPICE Testbench for Grids */ - { "fpga_spice_leakage_only", OT_FPGA_SPICE_LEAKAGE_ONLY }, /* Only simulate leakage power in FPGA SPICE */ - { "fpga_spice_parasitic_net_estimation", OT_FPGA_SPICE_PARASITIC_NET_ESTIMATION}, /* Xifan TANG: turn on/off the parasitic net estimation*/ - { "fpga_spice_testbench_load_extraction", OT_FPGA_SPICE_TESTBENCH_LOAD_EXTRACTION}, /* Xifan TANG: turn on/off the parasitic net estimation*/ - { "fpga_spice_simulator_path", OT_FPGA_SPICE_SIMULATOR_PATH}, /* Specify simulator path for SPICE netlists */ - { "fpga_spice_sim_mt_num", OT_FPGA_SPICE_SIM_MT_NUM }, /* number of multi-thread used in simulation */ - /* Xifan TANG: Synthsizable Verilog */ - { "fpga_verilog", OT_FPGA_VERILOG_SYN }, - { "fpga_verilog_dir", OT_FPGA_VERILOG_SYN_DIR }, - { "fpga_verilog_explicit_mapping", OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING }, - { "fpga_verilog_print_top_testbench", OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH }, - { "fpga_verilog_print_autocheck_top_testbench", OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH }, - { "fpga_verilog_print_input_blif_testbench", OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH }, - { "fpga_verilog_print_formal_verification_top_netlist", OT_FPGA_VERILOG_SYN_PRINT_FORMAL_VERIFICATION_TOP_NETLIST }, - { "fpga_verilog_include_timing", OT_FPGA_VERILOG_SYN_INCLUDE_TIMING }, /* Include timing constraints in Verilog netlists */ - { "fpga_verilog_include_signal_init", OT_FPGA_VERILOG_SYN_INCLUDE_SIGNAL_INIT }, /* Include signal initialization in Verilog netlists */ - { "fpga_verilog_include_icarus_simulator", OT_FPGA_VERILOG_SYN_INCLUDE_ICARUS_SIMULATOR }, /* Include/activate Icarus required functions in Verilog netlists */ - { "fpga_verilog_print_modelsim_autodeck", OT_FPGA_VERILOG_SYN_PRINT_MODELSIM_AUTODECK }, /* Generate autodeck scripts for modelsim */ - { "fpga_verilog_print_user_defined_template", OT_FPGA_VERILOG_SYN_PRINT_USER_DEFINED_TEMPLATE }, /* Specify the simulator path for Verilog netlists */ - { "fpga_verilog_print_report_timing_tcl", OT_FPGA_VERILOG_SYN_PRINT_REPORT_TIMING_TCL }, /* Specify the simulator path for Verilog netlists */ - { "fpga_verilog_report_timing_rpt_path", OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH }, /* Specify the simulator path for Verilog netlists */ - { "fpga_verilog_print_sdc_pnr", OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR }, /* Specify the simulator path for Verilog netlists */ - { "fpga_verilog_print_sdc_analysis", OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS }, /* Specify the simulator path for Verilog netlists */ - { "fpga_verilog_print_simulation_ini", OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI }, /* Specify the simulator path for Verilog netlists */ - { "fpga_verilog_simulation_ini_file", OT_FPGA_VERILOG_SYN_SIMULATION_INI_FILE }, /* Specify the simulator path for Verilog netlists */ - /* Xifan Tang: Bitstream generator */ - { "fpga_bitstream_generator", OT_FPGA_BITSTREAM_GENERATOR }, /* turn on bitstream generator, and specify the output file */ - // { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */ // AA: temporarily deprecated - /* mrFPGA: Xifan TANG */ - {"show_sram", OT_SHOW_SRAM}, - {"show_pass_trans", OT_SHOW_PASS_TRANS}, - /* END */ - /* CLB PIN REMAP */ - {"pack_clb_pin_remap", OT_PACK_CLB_PIN_REMAP}, - {"place_clb_pin_remap", OT_PLACE_CLB_PIN_REMAP}, - /* END */ - { NULL, OT_BASE_UNKNOWN } /* End of list marker */ -}; - -struct s_TokenPair OptionArgTokenList[] = { { "on", OT_ON }, { "off", OT_OFF }, - { "random", OT_RANDOM }, { "bounding_box", OT_BOUNDING_BOX }, { - "net_timing_driven", OT_NET_TIMING_DRIVEN }, { - "path_timing_driven", OT_PATH_TIMING_DRIVEN }, { - "breadth_first", OT_BREADTH_FIRST }, { "timing_driven", - OT_TIMING_DRIVEN }, { "NO_TIMING", OT_NO_TIMING }, { - "intrinsic_delay", OT_INTRINSIC_DELAY }, { "delay_normalized", - OT_DELAY_NORMALIZED }, { "demand_only", OT_DEMAND_ONLY }, { - "global", OT_GLOBAL }, { "detailed", OT_DETAILED }, { "timing", - OT_TIMING }, { "max_inputs", OT_MAX_INPUTS }, { "greedy", - OT_GREEDY }, { "lp", OT_LP }, { "brute_force", OT_BRUTE_FORCE }, - { NULL, OT_BASE_UNKNOWN } /* End of list marker */ -}; diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.h b/vpr7_x2p/vpr/SRC/base/OptionTokens.h deleted file mode 100644 index 37d91338d..000000000 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.h +++ /dev/null @@ -1,162 +0,0 @@ -#ifndef OPTIONTOKENS_H -#define OPTIONTOKENS_H - -/* The order of this does NOT matter, but do not give things specific values - * or you will screw up the ability to count things properly */ -enum e_OptionBaseToken { - OT_SETTINGS_FILE, - OT_NODISP, - OT_AUTO, - OT_RECOMPUTE_CRIT_ITER, - OT_INNER_LOOP_RECOMPUTE_DIVIDER, - OT_FIX_PINS, - OT_FULL_STATS, - OT_READ_PLACE_ONLY, - OT_FAST, - OT_CREATE_ECHO_FILE, - OT_TIMING_ANALYSIS, - OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY, - OT_GENERATE_POST_SYNTHESIS_NETLIST, - OT_INIT_T, - OT_ALPHA_T, - OT_EXIT_T, - OT_INNER_NUM, - OT_SEED, - OT_PLACE_COST_EXP, - OT_TD_PLACE_EXP_FIRST, - OT_TD_PLACE_EXP_LAST, - OT_PLACE_ALGORITHM, - OT_TIMING_TRADEOFF, - OT_ENABLE_TIMING_COMPUTATIONS, - OT_BLOCK_DIST, - OT_PLACE_CHAN_WIDTH, - OT_MAX_ROUTER_ITERATIONS, - OT_BB_FACTOR, - OT_ROUTER_ALGORITHM, - OT_FIRST_ITER_PRES_FAC, - OT_INITIAL_PRES_FAC, - OT_PRES_FAC_MULT, - OT_ACC_FAC, - OT_ASTAR_FAC, - OT_MAX_CRITICALITY, - OT_CRITICALITY_EXP, - OT_BASE_COST_TYPE, - OT_BEND_COST, - OT_ROUTE_TYPE, - OT_ROUTE_CHAN_WIDTH, - OT_ROUTE, - OT_PLACE, - OT_VERIFY_BINARY_SEARCH, - OT_OUTFILE_PREFIX, - OT_BLIF_FILE, - OT_NET_FILE, - OT_PLACE_FILE, - OT_ROUTE_FILE, - OT_SDC_FILE, - OT_GLOBAL_CLOCKS, - OT_HILL_CLIMBING_FLAG, - OT_SWEEP_HANGING_NETS_AND_INPUTS, - OT_SKIP_CLUSTERING, - OT_ALLOW_UNRELATED_CLUSTERING, - OT_ALLOW_EARLY_EXIT, - OT_CONNECTION_DRIVEN_CLUSTERING, - OT_TIMING_DRIVEN_CLUSTERING, - OT_CLUSTER_SEED, - OT_ALPHA_CLUSTERING, - OT_BETA_CLUSTERING, - OT_RECOMPUTE_TIMING_AFTER, - OT_CLUSTER_BLOCK_DELAY, - OT_INTRA_CLUSTER_NET_DELAY, - OT_INTER_CLUSTER_NET_DELAY, - OT_PACK, - OT_PACKER_ALGORITHM, - OT_POWER, - OT_ACTIVITY_FILE, - OT_POWER_OUT_FILE, - OT_CMOS_TECH_BEHAVIOR_FILE, - /* Xifan Tang: Tileable routing support !!! */ - OT_USE_TILEABLE_ROUTE_CHAN_WIDTH, - /* General FPGA_X2P: FPGA-SPICE/Verilog/Bitstream Options */ - OT_FPGA_X2P_RENAME_ILLEGAL_PORT, - OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT, /* The weight of signal density in determining number of clock cycles in simulation */ - OT_FPGA_X2P_SIM_WINDOW_SIZE, /* Window size in determining number of clock cycles in simulation */ - OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY, /* use a compact routing hierarchy in SPICE/Verilog generation */ - OT_FPGA_X2P_OUTPUT_SB_XML, /* output switch blocks to XML files */ - OT_FPGA_X2P_DUPLICATE_GRID_PIN, /* Duplicate the pins at each side of a grid when generating SPICE and Verilog netlists */ - /* Xifan TANG: FPGA SPICE Support */ - OT_FPGA_SPICE, /* Xifan TANG: FPGA SPICE Model Support */ - OT_FPGA_SPICE_DIR, /* Xifan TANG: FPGA SPICE Model Support */ - OT_FPGA_SPICE_PRINT_TOP_TESTBENCH, /* Xifan TANG: Print Top-level SPICE Testbench */ - OT_FPGA_SPICE_PRINT_PB_MUX_TESTBENCH, /* Xifan TANG: Print SPICE Testbench for MUXes */ - OT_FPGA_SPICE_PRINT_CB_MUX_TESTBENCH, /* Xifan TANG: Print SPICE Testbench for MUXes */ - OT_FPGA_SPICE_PRINT_SB_MUX_TESTBENCH, /* Xifan TANG: Print SPICE Testbench for MUXes */ - OT_FPGA_SPICE_PRINT_CB_TESTBENCH, /* Xifan TANG: Print SPICE Testbench for CBs */ - OT_FPGA_SPICE_PRINT_SB_TESTBENCH, /* Xifan TANG: Print SPICE Testbench for SBs */ - OT_FPGA_SPICE_PRINT_GRID_TESTBENCH, /* Xifan TANG: Print SPICE Testbench for Grids */ - OT_FPGA_SPICE_PRINT_LUT_TESTBENCH, /* Xifan TANG: Print SPICE Testbench for LUTs */ - OT_FPGA_SPICE_PRINT_HARDLOGIC_TESTBENCH, /* Xifan TANG: Print SPICE Testbench for hard logic s */ - OT_FPGA_SPICE_PRINT_IO_TESTBENCH, /* Xifan TANG: Print SPICE Testbench for hard logic s */ - OT_FPGA_SPICE_LEAKAGE_ONLY, /* Xifan TANG: Print SPICE Testbench for MUXes */ - OT_FPGA_SPICE_PARASITIC_NET_ESTIMATION, /* Xifan TANG: turn on/off the parasitic net estimation*/ - OT_FPGA_SPICE_TESTBENCH_LOAD_EXTRACTION, /* Xifan TANG: turn on/off the testbench load extraction */ - OT_FPGA_SPICE_SIMULATOR_PATH, - OT_FPGA_SPICE_SIM_MT_NUM, /* number of multi-thread used in simulation */ - /* Xifan TANG: Verilog Generation */ - OT_FPGA_VERILOG_SYN, /* Xifan TANG: Synthesizable Verilog Dump */ - OT_FPGA_VERILOG_SYN_DIR, /* Xifan TANG: Synthesizable Verilog Dump */ - OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING, /* Baudouin Chauviere: explicit pin mapping during verilog generation */ - OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist */ - OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist */ - OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for the orignial input blif */ - OT_FPGA_VERILOG_SYN_PRINT_FORMAL_VERIFICATION_TOP_NETLIST, /* Xifan Tang: Synthesizable Verilog, turn on option: output netlists in a compact way */ - OT_FPGA_VERILOG_SYN_INCLUDE_TIMING, /* Xifan TANG: Include timing constraints in Verilog */ - OT_FPGA_VERILOG_SYN_INCLUDE_SIGNAL_INIT, /* Xifan TANG: Include timing constraints in Verilog */ - OT_FPGA_VERILOG_SYN_INCLUDE_ICARUS_SIMULATOR, - OT_FPGA_VERILOG_SYN_PRINT_MODELSIM_AUTODECK, - OT_FPGA_VERILOG_SYN_PRINT_USER_DEFINED_TEMPLATE, - OT_FPGA_VERILOG_SYN_PRINT_REPORT_TIMING_TCL, - OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH, - OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR, - OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS, - OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI, - OT_FPGA_VERILOG_SYN_SIMULATION_INI_FILE, - /* Xifan Tang: Bitstream generator */ - OT_FPGA_BITSTREAM_GENERATOR, - OT_FPGA_BITSTREAM_OUTPUT_FILE, - /* mrFPGA: Xifan TANG */ - OT_SHOW_SRAM, - OT_SHOW_PASS_TRANS, - /* CLB PIN REMAP */ - OT_PACK_CLB_PIN_REMAP, - OT_PLACE_CLB_PIN_REMAP, - /* END */ - OT_BASE_UNKNOWN /* Must be last since used for counting enum items */ -}; - -enum e_OptionArgToken { - OT_ON, - OT_OFF, - OT_RANDOM, - OT_BOUNDING_BOX, - OT_NET_TIMING_DRIVEN, - OT_PATH_TIMING_DRIVEN, - OT_BREADTH_FIRST, - OT_TIMING_DRIVEN, - OT_NO_TIMING, - OT_INTRINSIC_DELAY, - OT_DELAY_NORMALIZED, - OT_DEMAND_ONLY, - OT_GLOBAL, - OT_DETAILED, - OT_TIMING, - OT_MAX_INPUTS, - OT_GREEDY, - OT_LP, - OT_BRUTE_FORCE, - OT_ARG_UNKNOWN /* Must be last since used for counting enum items */ -}; - -extern struct s_TokenPair OptionBaseTokenList[]; -extern struct s_TokenPair OptionArgTokenList[]; - -#endif diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.c b/vpr7_x2p/vpr/SRC/base/ReadOptions.c deleted file mode 100644 index 8ddc4d1bd..000000000 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.c +++ /dev/null @@ -1,1072 +0,0 @@ -#include -#include -#include -#include "util.h" -#include "hash.h" -#include "vpr_types.h" -#include "OptionTokens.h" -#include "ReadOptions.h" -#include "read_settings.h" -#include "globals.h" - -static boolean EchoEnabled; - -static boolean Generate_PostSynthesis_Netlist; - -static boolean *echoFileEnabled = NULL; -static char **echoFileNames = NULL; - -static char **outputFileNames = NULL; - -/******** Function prototypes ********/ - -static char **ReadBaseToken(INP char **Args, OUTP enum e_OptionBaseToken *Token); -static void Error(INP const char *Token); -static char **ProcessOption(INP char **Args, INOUTP t_options * Options); -static void MergeOptions(INOUTP t_options * dest, INP t_options * src, int id); -static char **ReadFloat(INP char **Args, OUTP float *Val); -static char **ReadInt(INP char **Args, OUTP int *Val); -static char **ReadOnOff(INP char **Args, OUTP boolean * Val); -static char **ReadClusterSeed(INP char **Args, OUTP enum e_cluster_seed *Type); -static char **ReadFixPins(INP char **Args, OUTP char **PinFile); -static char **ReadPlaceAlgorithm(INP char **Args, - OUTP enum e_place_algorithm *Algo); -static char **ReadRouterAlgorithm(INP char **Args, - OUTP enum e_router_algorithm *Algo); -static char **ReadPackerAlgorithm(INP char **Args, - OUTP enum e_packer_algorithm *Algo); -static char **ReadBaseCostType(INP char **Args, - OUTP enum e_base_cost_type *BaseCostType); -static char **ReadRouteType(INP char **Args, OUTP enum e_route_type *Type); -static char **ReadString(INP char **Args, OUTP char **Val); - -/******** Globally Accessible Function ********/ -/* Determines whether timing analysis should be on or off. - Unless otherwise specified, always default to timing. - */ -boolean IsTimingEnabled(INP t_options *Options) { - /* First priority to the '--timing_analysis' flag */ - if (Options->Count[OT_TIMING_ANALYSIS]) { - return Options->TimingAnalysis; - } - return TRUE; -} - -/* Determines whether file echo should be on or off. - Unless otherwise specified, always default to on. - */ -boolean IsEchoEnabled(INP t_options *Options) { - /* First priority to the '--echo_file' flag */ - if (Options->Count[OT_CREATE_ECHO_FILE]) { - return Options->CreateEchoFile; - } - return FALSE; -} - - -boolean getEchoEnabled(void) { - return EchoEnabled; -} - -void setEchoEnabled(boolean echo_enabled) { - /* enable echo outputs */ - EchoEnabled = echo_enabled; - if(echoFileEnabled == NULL) { - /* initialize default echo options */ - alloc_and_load_echo_file_info(); - } -} - -boolean GetPostSynthesisOption(void){ - return Generate_PostSynthesis_Netlist; -} - -void SetPostSynthesisOption(boolean post_synthesis_enabled){ - Generate_PostSynthesis_Netlist = post_synthesis_enabled; -} - -boolean IsPostSynthesisEnabled(INP t_options *Options) { - /* First priority to the '--generate_postsynthesis_netlist' flag */ - if (Options->Count[OT_GENERATE_POST_SYNTHESIS_NETLIST]) { - return Options->Generate_Post_Synthesis_Netlist; - } - return FALSE; -} - - -void setAllEchoFileEnabled(boolean value) { - int i; - for(i = 0; i < (int) E_ECHO_END_TOKEN; i++) { - echoFileEnabled[i] = value; - } -} - -void setEchoFileEnabled(enum e_echo_files echo_option, boolean value) { - echoFileEnabled[(int)echo_option] = value; -} - -void setEchoFileName(enum e_echo_files echo_option, const char *name) { - if(echoFileNames[(int)echo_option] != NULL) { - free(echoFileNames[(int)echo_option]); - } - echoFileNames[(int)echo_option] = my_strdup(name); -} - -boolean isEchoFileEnabled(enum e_echo_files echo_option) { - if(echoFileEnabled == NULL) { - return FALSE; - } else { - return echoFileEnabled[(int)echo_option]; - } -} -char *getEchoFileName(enum e_echo_files echo_option) { - return echoFileNames[(int)echo_option]; -} - -void alloc_and_load_echo_file_info() { - echoFileEnabled = (boolean*)my_calloc((int) E_ECHO_END_TOKEN, sizeof(boolean)); - echoFileNames = (char**)my_calloc((int) E_ECHO_END_TOKEN, sizeof(char*)); - - setAllEchoFileEnabled(TRUE); - - setEchoFileName(E_ECHO_INITIAL_CLB_PLACEMENT, "initial_clb_placement.echo"); - setEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH, "initial_placement_timing_graph.echo"); - setEchoFileName(E_ECHO_INITIAL_PLACEMENT_SLACK, "initial_placement_slack.echo"); - setEchoFileName(E_ECHO_INITIAL_PLACEMENT_CRITICALITY, "initial_placement_criticality.echo"); - setEchoFileName(E_ECHO_END_CLB_PLACEMENT, "end_clb_placement.echo"); - setEchoFileName(E_ECHO_PLACEMENT_SINK_DELAYS, "placement_sink_delays.echo"); - setEchoFileName(E_ECHO_FINAL_PLACEMENT_TIMING_GRAPH, "final_placement_timing_graph.echo"); - setEchoFileName(E_ECHO_FINAL_PLACEMENT_SLACK, "final_placement_slack.echo"); - setEchoFileName(E_ECHO_FINAL_PLACEMENT_CRITICALITY, "final_placement_criticality.echo"); - setEchoFileName(E_ECHO_PLACEMENT_CRIT_PATH, "placement_crit_path.echo"); - setEchoFileName(E_ECHO_PB_GRAPH, "pb_graph.echo"); - setEchoFileName(E_ECHO_ARCH, "arch.echo"); - setEchoFileName(E_ECHO_PLACEMENT_CRITICAL_PATH, "placement_critical_path.echo"); - setEchoFileName(E_ECHO_PLACEMENT_LOWER_BOUND_SINK_DELAYS, "placement_lower_bound_sink_delays.echo"); - setEchoFileName(E_ECHO_PLACEMENT_LOGIC_SINK_DELAYS, "placement_logic_sink_delays.echo"); - setEchoFileName(E_ECHO_ROUTING_SINK_DELAYS, "routing_sink_delays.echo"); - setEchoFileName(E_ECHO_POST_FLOW_TIMING_GRAPH, "post_flow_timing_graph.blif"); - setEchoFileName(E_ECHO_POST_PACK_NETLIST, "post_pack_netlist.blif"); - setEchoFileName(E_ECHO_BLIF_INPUT, "blif_input.echo"); - setEchoFileName(E_ECHO_NET_DELAY, "net_delay.echo"); - setEchoFileName(E_ECHO_TIMING_GRAPH, "timing_graph.echo"); - setEchoFileName(E_ECHO_LUT_REMAPPING, "lut_remapping.echo"); - setEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH, "pre_packing_timing_graph.echo"); - setEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH_AS_BLIF, "pre_packing_timing_graph_as_blif.blif"); - setEchoFileName(E_ECHO_CLUSTERING_TIMING_INFO, "clustering_timing_info.echo"); - setEchoFileName(E_ECHO_PRE_PACKING_SLACK, "pre_packing_slack.echo"); - setEchoFileName(E_ECHO_PRE_PACKING_CRITICALITY, "pre_packing_criticality.echo"); - setEchoFileName(E_ECHO_CLUSTERING_BLOCK_CRITICALITIES, "clustering_block_criticalities.echo"); - setEchoFileName(E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS, "pre_packing_molecules_and_patterns.echo"); - setEchoFileName(E_ECHO_MEM, "mem.echo"); - setEchoFileName(E_ECHO_RR_GRAPH, "rr_graph.echo"); - setEchoFileName(E_ECHO_TIMING_CONSTRAINTS, "timing_constraints.echo"); - setEchoFileName(E_ECHO_CRITICAL_PATH, "critical_path.echo"); - setEchoFileName(E_ECHO_SLACK, "slack.echo"); - setEchoFileName(E_ECHO_CRITICALITY, "criticality.echo"); - setEchoFileName(E_ECHO_COMPLETE_NET_TRACE, "complete_net_trace.echo"); - setEchoFileName(E_ECHO_SEG_DETAILS, "seg_details.txt"); -} - -void free_echo_file_info() { - int i; - if(echoFileEnabled != NULL) { - for(i = 0; i < (int) E_ECHO_END_TOKEN; i++) { - if(echoFileNames[i] != NULL) { - free(echoFileNames[i]); - } - } - free(echoFileNames); - free(echoFileEnabled); - echoFileNames = NULL; - echoFileEnabled = NULL; - } -} - -void setOutputFileName(enum e_output_files ename, const char *name, const char *default_name) { - if(outputFileNames == NULL) { - alloc_and_load_output_file_names(default_name); - } - if(outputFileNames[(int)ename] != NULL) { - free(outputFileNames[(int)ename]); - } - outputFileNames[(int)ename] = my_strdup(name); -} - -char *getOutputFileName(enum e_output_files ename) { - return outputFileNames[(int)ename]; -} - -void alloc_and_load_output_file_names(const char *default_name) { - char *name; - - if(outputFileNames == NULL) { - - outputFileNames = (char**)my_calloc((int)E_FILE_END_TOKEN, sizeof(char*)); - - name = (char*)my_malloc((strlen(default_name) + 40) * sizeof(char)); - sprintf(name, "%s.critical_path.out", default_name); - setOutputFileName(E_CRIT_PATH_FILE, name, default_name); - - sprintf(name, "%s.slack.out", default_name); - setOutputFileName(E_SLACK_FILE, name, default_name); - - sprintf(name, "%s.criticality.out", default_name); - setOutputFileName(E_CRITICALITY_FILE, name, default_name); - - free(name); - } -} - -void free_output_file_names() { - int i; - if(outputFileNames != NULL) { - for(i = 0; i < (int)E_FILE_END_TOKEN; i++) { - if(outputFileNames[i] != NULL) { - free(outputFileNames[i]); - outputFileNames[i] = NULL; - } - } - free(outputFileNames); - outputFileNames = NULL; - } -} - - - -/******** Subroutine implementations ********/ - -void ReadOptions(INP int argc, INP char **argv, OUTP t_options * Options) { - char **Args, **head; - int offset; - - /* Clear values and pointers to zero */ - memset(Options, 0, sizeof(t_options)); - - /* Alloc a new pointer list for args with a NULL at end. - * This makes parsing the same as for archfile for consistency. - * Skips the first arg as it is the program image path */ - --argc; - ++argv; - head = Args = (char **) my_malloc(sizeof(char *) * (argc + 1)); - memcpy(Args, argv, (sizeof(char *) * argc)); - Args[argc] = NULL; - - /* Go through the command line args. If they have hyphens they are - * options. Otherwise assume they are part of the four mandatory - * arguments */ - while (*Args) { - if (strncmp("--", *Args, 2) == 0) { - *Args += 2; /* Skip the prefix */ - Args = ProcessOption(Args, Options); - } else if (strncmp("-", *Args, 1) == 0) { - *Args += 1; /* Skip the prefix */ - Args = ProcessOption(Args, Options); - } else if (NULL == Options->ArchFile) { - Options->ArchFile = my_strdup(*Args); - vpr_printf(TIO_MESSAGE_INFO, "Architecture file: %s\n", Options->ArchFile); - ++Args; - } else if (NULL == Options->CircuitName) { - Options->CircuitName = my_strdup(*Args); - /*if the user entered the circuit name with the .blif extension, remove it now*/ - offset = strlen(Options->CircuitName) - 5; - if (offset > 0 && !strcmp(Options->CircuitName + offset, ".blif")) { - Options->CircuitName[offset] = '\0'; - } - vpr_printf(TIO_MESSAGE_INFO, "Circuit name: %s.blif\n", Options->CircuitName); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - ++Args; - } else { - /* Not an option and arch and net already specified so fail */ - Error(*Args); - } - - if (Options->Count[OT_SETTINGS_FILE] != Options->read_settings) - { - int tmp_argc = 0; - char **tmp_argv = NULL; - t_options SettingsFileOptions; - - tmp_argc = read_settings_file(Options->SettingsFile, &tmp_argv); - - ReadOptions(tmp_argc, tmp_argv, &SettingsFileOptions); - - MergeOptions(Options, &SettingsFileOptions, Options->Count[OT_SETTINGS_FILE]); - - Options->read_settings = Options->Count[OT_SETTINGS_FILE]; - - /* clean up local data structures */ - free(tmp_argv); - } - } - free(head); -} - -static char ** -ProcessOption(INP char **Args, INOUTP t_options * Options) { - enum e_OptionBaseToken Token; - char **PrevArgs; - - PrevArgs = Args; - Args = ReadBaseToken(Args, &Token); - - if (Token < OT_BASE_UNKNOWN) { - /* If this was previously set by a lower priority source - * (ie. a settings file), reset the provenance and the - * count */ - if (Options->Provenance[Token]) - { - Options->Provenance[Token] = 0; - Options->Count[Token] = 1; - } - else - ++Options->Count[Token]; - } - - switch (Token) { - /* File naming options */ - case OT_BLIF_FILE: - return ReadString(Args, &Options->BlifFile); - case OT_NET_FILE: - return ReadString(Args, &Options->NetFile); - case OT_PLACE_FILE: - return ReadString(Args, &Options->PlaceFile); - case OT_ROUTE_FILE: - return ReadString(Args, &Options->RouteFile); - case OT_SDC_FILE: - return ReadString(Args, &Options->SDCFile); - case OT_SETTINGS_FILE: - return ReadString(Args, &Options->SettingsFile); - /* General Options */ - case OT_NODISP: - return Args; - case OT_AUTO: - return ReadInt(Args, &Options->GraphPause); - case OT_PACK: - case OT_ROUTE: - case OT_PLACE: - return Args; - case OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY: - return ReadFloat(Args, &Options->constant_net_delay); - case OT_FAST: - case OT_FULL_STATS: - return Args; - case OT_TIMING_ANALYSIS: - return ReadOnOff(Args, &Options->TimingAnalysis); - case OT_OUTFILE_PREFIX: - return ReadString(Args, &Options->out_file_prefix); - case OT_CREATE_ECHO_FILE: - return ReadOnOff(Args, &Options->CreateEchoFile); - case OT_GENERATE_POST_SYNTHESIS_NETLIST: - - return ReadOnOff(Args, &Options->Generate_Post_Synthesis_Netlist); - /* Clustering Options */ - case OT_GLOBAL_CLOCKS: - return ReadOnOff(Args, &Options->global_clocks); - case OT_HILL_CLIMBING_FLAG: - return ReadOnOff(Args, &Options->hill_climbing_flag); - case OT_SWEEP_HANGING_NETS_AND_INPUTS: - return ReadOnOff(Args, &Options->sweep_hanging_nets_and_inputs); - case OT_TIMING_DRIVEN_CLUSTERING: - return ReadOnOff(Args, &Options->timing_driven); - case OT_CLUSTER_SEED: - return ReadClusterSeed(Args, &Options->cluster_seed_type); - case OT_ALPHA_CLUSTERING: - return ReadFloat(Args, &Options->alpha); - case OT_BETA_CLUSTERING: - return ReadFloat(Args, &Options->beta); - case OT_RECOMPUTE_TIMING_AFTER: - return ReadInt(Args, &Options->recompute_timing_after); - case OT_CLUSTER_BLOCK_DELAY: - return ReadFloat(Args, &Options->block_delay); - case OT_ALLOW_UNRELATED_CLUSTERING: - return ReadOnOff(Args, &Options->allow_unrelated_clustering); - case OT_ALLOW_EARLY_EXIT: - return ReadOnOff(Args, &Options->allow_early_exit); - case OT_INTRA_CLUSTER_NET_DELAY: - return ReadFloat(Args, &Options->intra_cluster_net_delay); - case OT_INTER_CLUSTER_NET_DELAY: - return ReadFloat(Args, &Options->inter_cluster_net_delay); - case OT_CONNECTION_DRIVEN_CLUSTERING: - return ReadOnOff(Args, &Options->connection_driven); - case OT_SKIP_CLUSTERING: - return Args; - case OT_PACKER_ALGORITHM: - return ReadPackerAlgorithm(Args, &Options->packer_algorithm); - - /* Placer Options */ - case OT_PLACE_ALGORITHM: - return ReadPlaceAlgorithm(Args, &Options->PlaceAlgorithm); - case OT_INIT_T: - return ReadFloat(Args, &Options->PlaceInitT); - case OT_EXIT_T: - return ReadFloat(Args, &Options->PlaceExitT); - case OT_ALPHA_T: - return ReadFloat(Args, &Options->PlaceAlphaT); - case OT_INNER_NUM: - return ReadFloat(Args, &Options->PlaceInnerNum); - case OT_SEED: - return ReadInt(Args, &Options->Seed); - case OT_PLACE_COST_EXP: - return ReadFloat(Args, &Options->place_cost_exp); - case OT_PLACE_CHAN_WIDTH: - return ReadInt(Args, &Options->PlaceChanWidth); - case OT_FIX_PINS: - return ReadFixPins(Args, &Options->PinFile); - case OT_ENABLE_TIMING_COMPUTATIONS: - return ReadOnOff(Args, &Options->ShowPlaceTiming); - case OT_BLOCK_DIST: - return ReadInt(Args, &Options->block_dist); - - /* Placement Options Valid Only for Timing-Driven Placement */ - case OT_TIMING_TRADEOFF: - return ReadFloat(Args, &Options->PlaceTimingTradeoff); - case OT_RECOMPUTE_CRIT_ITER: - return ReadInt(Args, &Options->RecomputeCritIter); - case OT_INNER_LOOP_RECOMPUTE_DIVIDER: - return ReadInt(Args, &Options->inner_loop_recompute_divider); - case OT_TD_PLACE_EXP_FIRST: - return ReadFloat(Args, &Options->place_exp_first); - case OT_TD_PLACE_EXP_LAST: - return ReadFloat(Args, &Options->place_exp_last); - - /* Router Options */ - case OT_MAX_ROUTER_ITERATIONS: - return ReadInt(Args, &Options->max_router_iterations); - case OT_BB_FACTOR: - return ReadInt(Args, &Options->bb_factor); - case OT_INITIAL_PRES_FAC: - return ReadFloat(Args, &Options->initial_pres_fac); - case OT_PRES_FAC_MULT: - return ReadFloat(Args, &Options->pres_fac_mult); - case OT_ACC_FAC: - return ReadFloat(Args, &Options->acc_fac); - case OT_FIRST_ITER_PRES_FAC: - return ReadFloat(Args, &Options->first_iter_pres_fac); - case OT_BEND_COST: - return ReadFloat(Args, &Options->bend_cost); - case OT_ROUTE_TYPE: - return ReadRouteType(Args, &Options->RouteType); - case OT_VERIFY_BINARY_SEARCH: - return Args; - case OT_ROUTE_CHAN_WIDTH: - return ReadInt(Args, &Options->RouteChanWidth); - case OT_ROUTER_ALGORITHM: - return ReadRouterAlgorithm(Args, &Options->RouterAlgorithm); - case OT_BASE_COST_TYPE: - return ReadBaseCostType(Args, &Options->base_cost_type); - - /* Routing options valid only for timing-driven routing */ - case OT_ASTAR_FAC: - return ReadFloat(Args, &Options->astar_fac); - case OT_MAX_CRITICALITY: - return ReadFloat(Args, &Options->max_criticality); - case OT_CRITICALITY_EXP: - return ReadFloat(Args, &Options->criticality_exp); - - /* Power options */ - case OT_POWER: - return Args; - case OT_ACTIVITY_FILE: - return ReadString(Args, &Options->ActFile); - case OT_POWER_OUT_FILE: - return ReadString(Args, &Options->PowerFile); - case OT_CMOS_TECH_BEHAVIOR_FILE: - return ReadString(Args, &Options->CmosTechFile); - - /* Xifan Tang: Tileable routing support !!! */ - case OT_USE_TILEABLE_ROUTE_CHAN_WIDTH: - return Args; - - /* Xifan Tang: FPGA X2P Options*/ - case OT_FPGA_X2P_RENAME_ILLEGAL_PORT: - return Args; - case OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT: - return ReadFloat(Args, &Options->fpga_spice_signal_density_weight); - case OT_FPGA_X2P_SIM_WINDOW_SIZE: - return ReadFloat(Args, &Options->fpga_spice_sim_window_size); - case OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY: - /* use a compact routing hierarchy in SPICE/Verilog generation */ - return Args; - case OT_FPGA_X2P_OUTPUT_SB_XML: - /* Read the file prefix to output SB XML files */ - return ReadString(Args, &Options->sb_xml_dir); - case OT_FPGA_X2P_DUPLICATE_GRID_PIN: - return Args; - /* Xifan TANG: FPGA SPICE Model Options*/ - case OT_FPGA_SPICE: - return Args; - case OT_FPGA_SPICE_DIR: - return ReadString(Args, &Options->spice_dir); - case OT_FPGA_SPICE_PRINT_TOP_TESTBENCH: - return Args; - case OT_FPGA_SPICE_PRINT_PB_MUX_TESTBENCH: - return Args; - case OT_FPGA_SPICE_PRINT_CB_MUX_TESTBENCH: - return Args; - case OT_FPGA_SPICE_PRINT_SB_MUX_TESTBENCH: - return Args; - case OT_FPGA_SPICE_PRINT_CB_TESTBENCH: - return Args; - case OT_FPGA_SPICE_PRINT_SB_TESTBENCH: - return Args; - case OT_FPGA_SPICE_PRINT_GRID_TESTBENCH: - return Args; - case OT_FPGA_SPICE_PRINT_LUT_TESTBENCH: - return Args; - case OT_FPGA_SPICE_PRINT_HARDLOGIC_TESTBENCH: - return Args; - case OT_FPGA_SPICE_PRINT_IO_TESTBENCH: - return Args; - case OT_FPGA_SPICE_LEAKAGE_ONLY: - return Args; - case OT_FPGA_SPICE_PARASITIC_NET_ESTIMATION: - return ReadOnOff(Args, &Options->fpga_spice_parasitic_net_estimation); - case OT_FPGA_SPICE_TESTBENCH_LOAD_EXTRACTION: - return ReadOnOff(Args, &Options->fpga_spice_testbench_load_extraction); - case OT_FPGA_SPICE_SIM_MT_NUM: - return ReadInt(Args, &Options->fpga_spice_sim_mt_num); - case OT_FPGA_SPICE_SIMULATOR_PATH: - return ReadString(Args, &Options->fpga_spice_simulator_path); - /* Xifan TANG: Synthesizable Verilog */ - case OT_FPGA_VERILOG_SYN: - return Args; - case OT_FPGA_VERILOG_SYN_DIR: - return ReadString(Args, &Options->fpga_syn_verilog_dir); - case OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING: - return Args; - case OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH: - return Args; - case OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH: - return ReadString(Args, &Options->fpga_verilog_reference_benchmark_file); - case OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH: - return Args; - case OT_FPGA_VERILOG_SYN_PRINT_FORMAL_VERIFICATION_TOP_NETLIST: - return Args; - case OT_FPGA_VERILOG_SYN_INCLUDE_TIMING: - return Args; - case OT_FPGA_VERILOG_SYN_INCLUDE_SIGNAL_INIT: - return Args; - case OT_FPGA_VERILOG_SYN_INCLUDE_ICARUS_SIMULATOR: - return Args; - case OT_FPGA_VERILOG_SYN_PRINT_MODELSIM_AUTODECK: - return ReadString(Args, &Options->fpga_verilog_modelsim_ini_path); - case OT_FPGA_VERILOG_SYN_PRINT_USER_DEFINED_TEMPLATE: - return Args; - case OT_FPGA_VERILOG_SYN_PRINT_REPORT_TIMING_TCL: - return Args; - case OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH: - return ReadString(Args, &Options->fpga_verilog_report_timing_path); - case OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR: - return Args; - case OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS: - return Args; - case OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI: - return Args; - case OT_FPGA_VERILOG_SYN_SIMULATION_INI_FILE: - return ReadString(Args, &Options->fpga_verilog_simulation_ini_path); - /* Xifan TANG: Bitstream generator */ - case OT_FPGA_BITSTREAM_GENERATOR: - return Args; -// case OT_FPGA_BITSTREAM_OUTPUT_FILE: // AA: temporarily deprecated -// return ReadString(Args, &Options->fpga_bitstream_file); - /* mrFPGA: Xifan TANG */ - case OT_SHOW_SRAM: - case OT_SHOW_PASS_TRANS: - return Args; - /* Xifan TANG: CLB_PIN_REMAP */ - case OT_PACK_CLB_PIN_REMAP: - case OT_PLACE_CLB_PIN_REMAP: - return Args; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "Unexpected option '%s' on command line.\n", *PrevArgs); - exit(1); - } -} - -/* - * Map options set in the source t_options to a target t_options - * structure. Existing values in the destination have priority - * and will not be overwritten - */ -static void MergeOptions(INOUTP t_options * dest, INP t_options * src, int id) -{ - int Token; - - for (Token = 0; Token < OT_BASE_UNKNOWN; Token++) - { - /* Don't override values already set in the - * target destination. Also do not process - * Tokens that are not present in the source. - */ - if ((dest->Count[Token] || (!src->Count[Token]))) - continue; - - dest->Count[Token] = src->Count[Token]; - dest->Provenance[Token] = id; - - switch (Token) { - /* File naming options */ - case OT_BLIF_FILE: - dest->BlifFile = src->BlifFile; - break; - case OT_NET_FILE: - dest->NetFile = src->NetFile; - break; - case OT_PLACE_FILE: - dest->PlaceFile = src->PlaceFile; - break; - case OT_ROUTE_FILE: - dest->RouteFile = src->RouteFile; - break; - case OT_SETTINGS_FILE: - dest->SettingsFile = src->SettingsFile; - break; - case OT_SDC_FILE: - dest->SDCFile = src->SDCFile; - break; - /* General Options */ - case OT_NODISP: - break; - case OT_AUTO: - dest->GraphPause = src->GraphPause; - break; - case OT_PACK: - case OT_ROUTE: - case OT_PLACE: - break; - case OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY: - dest->constant_net_delay = src->constant_net_delay; - break; - case OT_FAST: - case OT_FULL_STATS: - break; - case OT_TIMING_ANALYSIS: - dest->TimingAnalysis = src->TimingAnalysis; - break; - case OT_OUTFILE_PREFIX: - dest->out_file_prefix = src->out_file_prefix; - break; - case OT_CREATE_ECHO_FILE: - dest->CreateEchoFile = src->CreateEchoFile; - break; - - /* Clustering Options */ - case OT_GLOBAL_CLOCKS: - dest->global_clocks = src->global_clocks; - break; - case OT_HILL_CLIMBING_FLAG: - dest->hill_climbing_flag = src->hill_climbing_flag; - break; - case OT_SWEEP_HANGING_NETS_AND_INPUTS: - dest->sweep_hanging_nets_and_inputs = src->sweep_hanging_nets_and_inputs; - break; - case OT_TIMING_DRIVEN_CLUSTERING: - dest->timing_driven = src->timing_driven; - break; - case OT_CLUSTER_SEED: - dest->cluster_seed_type = src->cluster_seed_type; - break; - case OT_ALPHA_CLUSTERING: - dest->alpha = src->alpha; - break; - case OT_BETA_CLUSTERING: - dest->beta = src->beta; - break; - case OT_RECOMPUTE_TIMING_AFTER: - dest->recompute_timing_after = src->recompute_timing_after; - break; - case OT_CLUSTER_BLOCK_DELAY: - dest->block_delay = src->block_delay; - break; - case OT_ALLOW_UNRELATED_CLUSTERING: - dest->allow_unrelated_clustering = src->allow_unrelated_clustering; - break; - case OT_ALLOW_EARLY_EXIT: - dest->allow_early_exit = src->allow_early_exit; - break; - case OT_INTRA_CLUSTER_NET_DELAY: - dest->intra_cluster_net_delay = src->intra_cluster_net_delay; - break; - case OT_INTER_CLUSTER_NET_DELAY: - dest->inter_cluster_net_delay = src->inter_cluster_net_delay; - break; - case OT_CONNECTION_DRIVEN_CLUSTERING: - dest->connection_driven = src->connection_driven; - break; - case OT_SKIP_CLUSTERING: - break; - case OT_PACKER_ALGORITHM: - dest->packer_algorithm = src->packer_algorithm; - break; - - /* Placer Options */ - case OT_PLACE_ALGORITHM: - dest->PlaceAlgorithm = src->PlaceAlgorithm; - break; - case OT_INIT_T: - dest->PlaceInitT = src->PlaceInitT; - break; - case OT_EXIT_T: - dest->PlaceExitT = src->PlaceExitT; - break; - case OT_ALPHA_T: - dest->PlaceAlphaT = src->PlaceAlphaT; - break; - case OT_INNER_NUM: - dest->PlaceInnerNum = src->PlaceInnerNum; - break; - case OT_SEED: - dest->Seed = src->Seed; - break; - case OT_PLACE_COST_EXP: - dest->place_cost_exp = src->place_cost_exp; - break; - case OT_PLACE_CHAN_WIDTH: - dest->PlaceChanWidth = src->PlaceChanWidth; - break; - case OT_FIX_PINS: - dest->PinFile = src->PinFile; - break; - case OT_ENABLE_TIMING_COMPUTATIONS: - dest->ShowPlaceTiming = src->ShowPlaceTiming; - break; - case OT_BLOCK_DIST: - dest->block_dist = src->block_dist; - break; - - /* Placement Options Valid Only for Timing-Driven Placement */ - case OT_TIMING_TRADEOFF: - dest->PlaceTimingTradeoff = src->PlaceTimingTradeoff; - break; - case OT_RECOMPUTE_CRIT_ITER: - dest->RecomputeCritIter = src->RecomputeCritIter; - break; - case OT_INNER_LOOP_RECOMPUTE_DIVIDER: - dest->inner_loop_recompute_divider = src->inner_loop_recompute_divider; - break; - case OT_TD_PLACE_EXP_FIRST: - dest->place_exp_first = src->place_exp_first; - break; - case OT_TD_PLACE_EXP_LAST: - dest->place_exp_last = src->place_exp_last; - break; - - /* Router Options */ - case OT_MAX_ROUTER_ITERATIONS: - dest->max_router_iterations = src->max_router_iterations; - break; - case OT_BB_FACTOR: - dest->bb_factor = src->bb_factor; - break; - case OT_INITIAL_PRES_FAC: - dest->initial_pres_fac = src->initial_pres_fac; - break; - case OT_PRES_FAC_MULT: - dest->pres_fac_mult = src->pres_fac_mult; - break; - case OT_ACC_FAC: - dest->acc_fac = src->acc_fac; - break; - case OT_FIRST_ITER_PRES_FAC: - dest->first_iter_pres_fac = src->first_iter_pres_fac; - break; - case OT_BEND_COST: - dest->bend_cost = src->bend_cost; - break; - case OT_ROUTE_TYPE: - dest->RouteType = src->RouteType; - break; - case OT_VERIFY_BINARY_SEARCH: - break; - case OT_ROUTE_CHAN_WIDTH: - dest->RouteChanWidth = src->RouteChanWidth; - break; - case OT_ROUTER_ALGORITHM: - dest->RouterAlgorithm = src->RouterAlgorithm; - break; - case OT_BASE_COST_TYPE: - dest->base_cost_type = src->base_cost_type; - break; - - /* Routing options valid only for timing-driven routing */ - case OT_ASTAR_FAC: - dest->astar_fac = src->astar_fac; - break; - case OT_MAX_CRITICALITY: - dest->max_criticality = src->max_criticality; - break; - case OT_CRITICALITY_EXP: - dest->criticality_exp = src->criticality_exp; - break; - default: - break; - } - } -} - -static char ** -ReadBaseToken(INP char **Args, OUTP enum e_OptionBaseToken *Token) { - struct s_TokenPair *Cur; - - /* Empty string is end of tokens marker */ - if (NULL == *Args) - Error(*Args); - - /* Linear search for the pair */ - Cur = OptionBaseTokenList; - while (Cur->Str) { - if (strcmp(*Args, Cur->Str) == 0) { - *Token = (enum e_OptionBaseToken) Cur->Enum; - return ++Args; - } - ++Cur; - } - - *Token = OT_BASE_UNKNOWN; - return ++Args; -} - -static char ** -ReadToken(INP char **Args, OUTP enum e_OptionArgToken *Token) { - struct s_TokenPair *Cur; - - /* Empty string is end of tokens marker */ - if (NULL == *Args) - Error(*Args); - - /* Linear search for the pair */ - Cur = OptionArgTokenList; - while (Cur->Str) { - if (strcmp(*Args, Cur->Str) == 0) { - *Token = (enum e_OptionArgToken)Cur->Enum; - return ++Args; - } - ++Cur; - } - - *Token = OT_ARG_UNKNOWN; - return ++Args; -} - -/* Called for parse errors. Spits out a message and then exits program. */ -static void Error(INP const char *Token) { - if (Token) { - vpr_printf(TIO_MESSAGE_ERROR, "Unexpected token '%s' on command line.\n", Token); - } else { - vpr_printf(TIO_MESSAGE_ERROR, "Missing token at end of command line.\n"); - } - exit(1); -} - -static char ** -ReadClusterSeed(INP char **Args, OUTP enum e_cluster_seed *Type) { - enum e_OptionArgToken Token; - char **PrevArgs; - - PrevArgs = Args; - Args = ReadToken(Args, &Token); - switch (Token) { - case OT_TIMING: - *Type = VPACK_TIMING; - break; - case OT_MAX_INPUTS: - *Type = VPACK_MAX_INPUTS; - break; - default: - Error(*PrevArgs); - } - - return Args; -} - -static char ** -ReadPackerAlgorithm(INP char **Args, OUTP enum e_packer_algorithm *Algo) { - enum e_OptionArgToken Token; - char **PrevArgs; - - PrevArgs = Args; - Args = ReadToken(Args, &Token); - switch (Token) { - case OT_GREEDY: - *Algo = PACK_GREEDY; - break; - case OT_BRUTE_FORCE: - *Algo = PACK_BRUTE_FORCE; - break; - default: - Error(*PrevArgs); - } - - return Args; -} - -static char ** -ReadRouterAlgorithm(INP char **Args, OUTP enum e_router_algorithm *Algo) { - enum e_OptionArgToken Token; - char **PrevArgs; - - PrevArgs = Args; - Args = ReadToken(Args, &Token); - switch (Token) { - case OT_BREADTH_FIRST: - *Algo = BREADTH_FIRST; - break; - case OT_NO_TIMING: - *Algo = NO_TIMING; - break; - case OT_TIMING_DRIVEN: - *Algo = TIMING_DRIVEN; - break; - default: - Error(*PrevArgs); - } - - return Args; -} - -static char ** -ReadBaseCostType(INP char **Args, OUTP enum e_base_cost_type *BaseCostType) { - enum e_OptionArgToken Token; - char **PrevArgs; - - PrevArgs = Args; - Args = ReadToken(Args, &Token); - switch (Token) { - case OT_INTRINSIC_DELAY: - *BaseCostType = INTRINSIC_DELAY; - break; - case OT_DELAY_NORMALIZED: - *BaseCostType = DELAY_NORMALIZED; - break; - case OT_DEMAND_ONLY: - *BaseCostType = DEMAND_ONLY; - break; - default: - Error(*PrevArgs); - } - - return Args; -} - -static char ** -ReadRouteType(INP char **Args, OUTP enum e_route_type *Type) { - enum e_OptionArgToken Token; - char **PrevArgs; - - PrevArgs = Args; - Args = ReadToken(Args, &Token); - switch (Token) { - case OT_GLOBAL: - *Type = GLOBAL; - break; - case OT_DETAILED: - *Type = DETAILED; - break; - default: - Error(*PrevArgs); - } - - return Args; -} - -static char ** -ReadPlaceAlgorithm(INP char **Args, OUTP enum e_place_algorithm *Algo) { - enum e_OptionArgToken Token; - char **PrevArgs; - - PrevArgs = Args; - Args = ReadToken(Args, &Token); - switch (Token) { - case OT_BOUNDING_BOX: - *Algo = BOUNDING_BOX_PLACE; - break; - case OT_NET_TIMING_DRIVEN: - *Algo = NET_TIMING_DRIVEN_PLACE; - break; - case OT_PATH_TIMING_DRIVEN: - *Algo = PATH_TIMING_DRIVEN_PLACE; - break; - default: - Error(*PrevArgs); - } - - return Args; -} - -static char ** -ReadFixPins(INP char **Args, OUTP char **PinFile) { - enum e_OptionArgToken Token; - int Len; - char **PrevArgs = Args; - - Args = ReadToken(Args, &Token); - if (OT_RANDOM != Token) { - Len = 1 + strlen(*PrevArgs); - *PinFile = (char *) my_malloc(Len * sizeof(char)); - memcpy(*PinFile, *PrevArgs, Len); - } - return Args; -} - -static char ** -ReadOnOff(INP char **Args, OUTP boolean * Val) { - enum e_OptionArgToken Token; - char **PrevArgs; - - PrevArgs = Args; - Args = ReadToken(Args, &Token); - switch (Token) { - case OT_ON: - *Val = TRUE; - break; - case OT_OFF: - *Val = FALSE; - break; - default: - Error(*PrevArgs); - } - return Args; -} - -static char ** -ReadInt(INP char **Args, OUTP int *Val) { - if (NULL == *Args) - Error(*Args); - if ((**Args > '9') || (**Args < '0')) - Error(*Args); - - *Val = atoi(*Args); - - return ++Args; -} - -static char ** -ReadFloat(INP char ** Args, OUTP float *Val) { - if (NULL == *Args) { - Error(*Args); - } - - if ((**Args != '-') && (**Args != '.') - && ((**Args > '9') || (**Args < '0'))) { - Error(*Args); - } - - *Val = atof(*Args); - - return ++Args; -} - -static char ** -ReadString(INP char **Args, OUTP char **Val) { - if (NULL == *Args) { - Error(*Args); - } - - *Val = my_strdup(*Args); - - return ++Args; -} - - diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.h b/vpr7_x2p/vpr/SRC/base/ReadOptions.h deleted file mode 100644 index a242ba0b1..000000000 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.h +++ /dev/null @@ -1,194 +0,0 @@ -#ifndef READOPTIONS_H -#define READOPTIONS_H - -#include "OptionTokens.h" - -typedef struct s_options t_options; -struct s_options { - /* File names */ - char *ArchFile; - char *SettingsFile; - char *CircuitName; - char *NetFile; - char *PlaceFile; - char *RouteFile; - char *BlifFile; - char *ActFile; - char *PowerFile; - char *CmosTechFile; - char *out_file_prefix; - char *SDCFile; - - /* General options */ - int GraphPause; - float constant_net_delay; - boolean TimingAnalysis; - boolean CreateEchoFile; - boolean Generate_Post_Synthesis_Netlist; - /* Clustering options */ - boolean global_clocks; - int cluster_size; - int inputs_per_cluster; - int lut_size; - boolean hill_climbing_flag; - boolean sweep_hanging_nets_and_inputs; - boolean timing_driven; - enum e_cluster_seed cluster_seed_type; - float alpha; - float beta; - int recompute_timing_after; - float block_delay; - float intra_cluster_net_delay; - float inter_cluster_net_delay; - boolean skip_clustering; - boolean allow_unrelated_clustering; - boolean allow_early_exit; - boolean connection_driven; - enum e_packer_algorithm packer_algorithm; - - /* Placement options */ - enum e_place_algorithm PlaceAlgorithm; - float PlaceInitT; - float PlaceExitT; - float PlaceAlphaT; - float PlaceInnerNum; - int Seed; - float place_cost_exp; - int PlaceChanWidth; - char *PinFile; - boolean ShowPlaceTiming; - int block_dist; - - /* Timing-driven placement options only */ - float PlaceTimingTradeoff; - int RecomputeCritIter; - int inner_loop_recompute_divider; - float place_exp_first; - float place_exp_last; - - /* Router Options */ - int max_router_iterations; - int bb_factor; - float initial_pres_fac; - float pres_fac_mult; - float acc_fac; - float first_iter_pres_fac; - float bend_cost; - enum e_route_type RouteType; - int RouteChanWidth; - enum e_router_algorithm RouterAlgorithm; - enum e_base_cost_type base_cost_type; - - /* Timing-driven router options only */ - float astar_fac; - float criticality_exp; - float max_criticality; - - /* State and metadata about various settings */ - int Count[OT_BASE_UNKNOWN]; - int Provenance[OT_BASE_UNKNOWN]; - - /* Last read settings file */ - int read_settings; - - /* Xifan TANG: signal weight in FPGA_SPICE simulation */ - float fpga_spice_signal_density_weight; - float fpga_spice_sim_window_size; - char* sb_xml_dir; - - /* Xifan TANG: SPICE Support*/ - char* spice_dir; - boolean fpga_spice_parasitic_net_estimation; - boolean fpga_spice_testbench_load_extraction; - int fpga_spice_sim_mt_num; - char* fpga_spice_simulator_path; - /* Xifan TANG: Synthesizable Verilog */ - char* fpga_syn_verilog_dir; - char* fpga_verilog_reference_benchmark_file; - char* fpga_verilog_modelsim_ini_path; - char* fpga_verilog_report_timing_path; - char* fpga_verilog_simulation_ini_path; - /* Xifan TANG: Bitstream generator */ - char* fpga_bitstream_file; -}; - -enum e_echo_files { - E_ECHO_INITIAL_CLB_PLACEMENT = 0, - E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH, - E_ECHO_INITIAL_PLACEMENT_SLACK, - E_ECHO_INITIAL_PLACEMENT_CRITICALITY, - E_ECHO_END_CLB_PLACEMENT, - E_ECHO_PLACEMENT_SINK_DELAYS, - E_ECHO_FINAL_PLACEMENT_TIMING_GRAPH, - E_ECHO_FINAL_PLACEMENT_SLACK, - E_ECHO_FINAL_PLACEMENT_CRITICALITY, - E_ECHO_PLACEMENT_CRIT_PATH, - E_ECHO_PB_GRAPH, - E_ECHO_ARCH, - E_ECHO_PLACEMENT_CRITICAL_PATH, - E_ECHO_PLACEMENT_LOWER_BOUND_SINK_DELAYS, - E_ECHO_PLACEMENT_LOGIC_SINK_DELAYS, - E_ECHO_ROUTING_SINK_DELAYS, - E_ECHO_POST_FLOW_TIMING_GRAPH, - E_ECHO_POST_PACK_NETLIST, - E_ECHO_BLIF_INPUT, - E_ECHO_NET_DELAY, - E_ECHO_TIMING_GRAPH, - E_ECHO_LUT_REMAPPING, - E_ECHO_PRE_PACKING_TIMING_GRAPH, - E_ECHO_PRE_PACKING_TIMING_GRAPH_AS_BLIF, - E_ECHO_CLUSTERING_TIMING_INFO, - E_ECHO_PRE_PACKING_SLACK, - E_ECHO_PRE_PACKING_CRITICALITY, - E_ECHO_CLUSTERING_BLOCK_CRITICALITIES, - E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS, - E_ECHO_MEM, - E_ECHO_RR_GRAPH, - E_ECHO_TIMING_CONSTRAINTS, - E_ECHO_CRITICAL_PATH, - E_ECHO_SLACK, - E_ECHO_CRITICALITY, - E_ECHO_COMPLETE_NET_TRACE, - E_ECHO_SEG_DETAILS, - E_ECHO_END_TOKEN -}; - - -enum e_output_files { - E_CRIT_PATH_FILE, - E_SLACK_FILE, - E_CRITICALITY_FILE, - E_FILE_END_TOKEN -}; - - -void ReadOptions(INP int argc, - INP char **argv, - OUTP t_options * Options); - -boolean getEchoEnabled(void); -void setEchoEnabled(boolean echo_enabled); - -void setAllEchoFileEnabled(boolean value); -void setEchoFileEnabled(enum e_echo_files echo_option, boolean value); -void setEchoFileName(enum e_echo_files echo_option, const char *name); - -boolean isEchoFileEnabled(enum e_echo_files echo_option); -char *getEchoFileName(enum e_echo_files echo_option); - -void alloc_and_load_echo_file_info(); -void free_echo_file_info(); - -void setOutputFileName(enum e_output_files ename, const char *name, const char* default_name); -char *getOutputFileName(enum e_output_files ename); -void alloc_and_load_output_file_names(const char* default_name); -void free_output_file_names(); - -boolean IsTimingEnabled(INP t_options *Options); -boolean IsEchoEnabled(INP t_options *Options); - -boolean GetPostSynthesisOption(void); -void SetPostSynthesisOption(boolean post_synthesis_enabled); - -boolean IsPostSynthesisEnabled(INP t_options *Options); -#endif diff --git a/vpr7_x2p/vpr/SRC/base/SetupGrid.c b/vpr7_x2p/vpr/SRC/base/SetupGrid.c deleted file mode 100644 index c009b7dca..000000000 --- a/vpr7_x2p/vpr/SRC/base/SetupGrid.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - Author: Jason Luu - Date: October 8, 2008 - - Initializes and allocates the physical logic block grid for VPR. - - */ - -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "SetupGrid.h" -#include "read_xml_arch_file.h" - -static void CheckGrid(void); -static t_type_ptr find_type_col(INP int x); - -/* Create and fill FPGA architecture grid. */ -void alloc_and_load_grid(INOUTP int *num_instances_type) { - - int i, j; - t_type_ptr type; - -#ifdef SHOW_ARCH - FILE *dump; -#endif - - /* To remove this limitation, change ylow etc. in t_rr_node to * - * * be ints instead. Used shorts to save memory. */ - if ((nx > 32766) || (ny > 32766)) { - vpr_printf(TIO_MESSAGE_ERROR, "nx and ny must be less than 32767, since the router uses shorts (16-bit) to store coordinates.\n"); - vpr_printf(TIO_MESSAGE_ERROR, "nx: %d, ny: %d\n", nx, ny); - exit(1); - } - - assert(nx >= 1 && ny >= 1); - - grid = (struct s_grid_tile **) alloc_matrix(0, (nx + 1), 0, (ny + 1), - sizeof(struct s_grid_tile)); - - /* Clear the full grid to have no type (NULL), no capacity, etc */ - for (i = 0; i <= (nx + 1); ++i) { - for (j = 0; j <= (ny + 1); ++j) { - memset(&grid[i][j], 0, (sizeof(struct s_grid_tile))); - } - } - - for (i = 0; i < num_types; i++) { - num_instances_type[i] = 0; - } - - /* Nothing goes in the corners. */ - grid[0][0].type = grid[nx + 1][0].type = EMPTY_TYPE; - grid[0][ny + 1].type = grid[nx + 1][ny + 1].type = EMPTY_TYPE; - num_instances_type[EMPTY_TYPE->index] = 4; - - for (i = 1; i <= nx; i++) { - grid[i][0].blocks = (int *) my_malloc(sizeof(int) * IO_TYPE->capacity); - grid[i][0].type = IO_TYPE; - - grid[i][ny + 1].blocks = (int *) my_malloc( - sizeof(int) * IO_TYPE->capacity); - grid[i][ny + 1].type = IO_TYPE; - - for (j = 0; j < IO_TYPE->capacity; j++) { - grid[i][0].blocks[j] = EMPTY; - grid[i][ny + 1].blocks[j] = EMPTY; - } - } - - for (i = 1; i <= ny; i++) { - grid[0][i].blocks = (int *) my_malloc(sizeof(int) * IO_TYPE->capacity); - grid[0][i].type = IO_TYPE; - - grid[nx + 1][i].blocks = (int *) my_malloc( - sizeof(int) * IO_TYPE->capacity); - grid[nx + 1][i].type = IO_TYPE; - for (j = 0; j < IO_TYPE->capacity; j++) { - grid[0][i].blocks[j] = EMPTY; - grid[nx + 1][i].blocks[j] = EMPTY; - } - } - - num_instances_type[IO_TYPE->index] = 2 * IO_TYPE->capacity * (nx + ny); - - for (i = 1; i <= nx; i++) { /* Interior (LUT) cells */ - type = find_type_col(i); - for (j = 1; j <= ny; j++) { - grid[i][j].type = type; - grid[i][j].offset = (j - 1) % type->height; - if (j + grid[i][j].type->height - 1 - grid[i][j].offset > ny) { - grid[i][j].type = EMPTY_TYPE; - grid[i][j].offset = 0; - } - - if (type->capacity > 1) { - vpr_printf(TIO_MESSAGE_ERROR, "in FillArch(), expected core blocks to have capacity <= 1 but (%d, %d) has type '%s' and capacity %d.\n", - i, j, grid[i][j].type->name, grid[i][j].type->capacity); - exit(1); - } - - grid[i][j].blocks = (int *) my_malloc(sizeof(int)); - grid[i][j].blocks[0] = EMPTY; - if (grid[i][j].offset == 0) { - num_instances_type[grid[i][j].type->index]++; - } - } - } - - CheckGrid(); - -#ifdef SHOW_ARCH - /* DEBUG code */ - dump = my_fopen("grid_type_dump.txt", "w", 0); - for (j = (ny + 1); j >= 0; --j) - { - for (i = 0; i <= (nx + 1); ++i) - { - fprintf(dump, "%c", grid[i][j].type->name[1]); - } - fprintf(dump, "\n"); - } - fclose(dump); -#endif -} - -void freeGrid() { - int i, j; - if (grid == NULL) { - return; - } - - for (i = 0; i <= (nx + 1); ++i) { - for (j = 0; j <= (ny + 1); ++j) { - free(grid[i][j].blocks); - } - } - free_matrix(grid, 0, nx + 1, 0, sizeof(struct s_grid_tile)); - grid = NULL; -} - -static void CheckGrid() { - int i, j; - - /* Check grid is valid */ - for (i = 0; i <= (nx + 1); ++i) { - for (j = 0; j <= (ny + 1); ++j) { - if (NULL == grid[i][j].type) { - vpr_printf(TIO_MESSAGE_ERROR, "grid[%d][%d] has no type.\n", i, j); - exit(1); - } - - if (grid[i][j].usage != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "grid[%d][%d] has non-zero usage (%d) before netlist load.\n", i, j, grid[i][j].usage); - exit(1); - } - - if ((grid[i][j].offset < 0) - || (grid[i][j].offset >= grid[i][j].type->height)) { - vpr_printf(TIO_MESSAGE_ERROR, "grid[%d][%d] has invalid offset (%d).\n", i, j, grid[i][j].offset); - exit(1); - } - - if ((NULL == grid[i][j].blocks) - && (grid[i][j].type->capacity > 0)) { - vpr_printf(TIO_MESSAGE_ERROR, "grid[%d][%d] has no block list allocated.\n", i, j); - exit(1); - } - } - } -} - -static t_type_ptr find_type_col(INP int x) { - int i, j; - int start, repeat; - float rel; - boolean match; - int priority, num_loc; - t_type_ptr column_type; - - priority = FILL_TYPE->grid_loc_def[0].priority; - column_type = FILL_TYPE; - - for (i = 0; i < num_types; i++) { - if (&type_descriptors[i] == IO_TYPE - || &type_descriptors[i] == EMPTY_TYPE - || &type_descriptors[i] == FILL_TYPE) - continue; - num_loc = type_descriptors[i].num_grid_loc_def; - for (j = 0; j < num_loc; j++) { - if (priority < type_descriptors[i].grid_loc_def[j].priority) { - match = FALSE; - if (type_descriptors[i].grid_loc_def[j].grid_loc_type - == COL_REPEAT) { - start = type_descriptors[i].grid_loc_def[j].start_col; - repeat = type_descriptors[i].grid_loc_def[j].repeat; - if (start < 0) { - start += (nx + 1); - } - if (x == start) { - match = TRUE; - } else if (repeat > 0 && x > start && start > 0) { - if ((x - start) % repeat == 0) { - match = TRUE; - } - } - } else if (type_descriptors[i].grid_loc_def[j].grid_loc_type - == COL_REL) { - rel = type_descriptors[i].grid_loc_def[j].col_rel; - if (nint(rel * nx) == x) { - match = TRUE; - } - } - if (match) { - priority = type_descriptors[i].grid_loc_def[j].priority; - column_type = &type_descriptors[i]; - } - } - } - } - return column_type; -} diff --git a/vpr7_x2p/vpr/SRC/base/SetupGrid.h b/vpr7_x2p/vpr/SRC/base/SetupGrid.h deleted file mode 100644 index ba864caa5..000000000 --- a/vpr7_x2p/vpr/SRC/base/SetupGrid.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef SETUPGRAD_H -#define SETUPGRID_H - -/* - Author: Jason Luu - Date: October 8, 2008 - - Initializes and allocates the physical logic block grid for VPR. - - */ - -void alloc_and_load_grid(INOUTP int *num_instances_type); /* [0..num_types-1] */ -void freeGrid(void); - -#endif - diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c deleted file mode 100644 index a591b385e..000000000 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ /dev/null @@ -1,1383 +0,0 @@ -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "OptionTokens.h" -#include "ReadOptions.h" -#include "globals.h" -#include "read_xml_arch_file.h" -#include "SetupVPR.h" -#include "pb_type_graph.h" -#include "ReadOptions.h" -/* mrFPGA: Xifan TANG*/ -#include "mrfpga_api.h" -#include "mrfpga_globals.h" -/* END */ - -/* Xifan Tang: include for supporting Direct Parsing */ -#include "vpr_utils.h" - -static void SetupOperation(INP t_options Options, - OUTP enum e_operation *Operation); -static void SetupPackerOpts(INP t_options Options, INP boolean TimingEnabled, - INP t_arch Arch, INP char *net_file, - OUTP struct s_packer_opts *PackerOpts); -static void SetupPlacerOpts(INP t_options Options, INP boolean TimingEnabled, - OUTP struct s_placer_opts *PlacerOpts); -static void SetupAnnealSched(INP t_options Options, - OUTP struct s_annealing_sched *AnnealSched); -static void SetupRouterOpts(INP t_options Options, INP boolean TimingEnabled, - OUTP struct s_router_opts *RouterOpts); -static void SetupRoutingArch(INP t_arch Arch, - OUTP struct s_det_routing_arch *RoutingArch); -static void SetupTiming(INP t_options Options, INP t_arch Arch, - INP boolean TimingEnabled, INP enum e_operation Operation, - INP struct s_placer_opts PlacerOpts, - INP struct s_router_opts RouterOpts, OUTP t_timing_inf * Timing); -static void SetupSwitches(INP t_arch Arch, - INOUTP struct s_det_routing_arch *RoutingArch, - INP struct s_switch_inf *ArchSwitches, INP int NumArchSwitches); -static void SetupPowerOpts(t_options Options, t_power_opts *power_opts, - t_arch * Arch); -/*Xifan TANG: SPICE Model Support*/ -static void SetupSpiceOpts(t_options Options, - t_spice_opts* spice_opts, - t_arch* arch); -/* end */ -/* Xifan TANG: synthesizable verilog dumping */ -static void SetupSynVerilogOpts(t_options Options, - t_syn_verilog_opts* syn_verilog_opts, - t_arch* arch); - -/* Xifan TANG: Bitstream Generator */ -static void SetupBitstreamGenOpts(t_options Options, - t_bitstream_gen_opts* bitstream_gen_opts, - t_arch* arch); - -/* Xifan TANG: FPGA-SPICE Tool suites Options Setup */ -static void SetupFpgaSpiceOpts(t_options Options, - t_fpga_spice_opts* fpga_spice_opts, - t_arch* arch); -/* end */ -/* Xifan Tang: Parse CLB to CLB direct connections */ - -/* mrFPGA */ -static void SetupSwitches_mrFPGA(INP t_arch Arch, - INOUTP struct s_det_routing_arch *RoutingArch, - INP struct s_switch_inf *ArchSwitches, INP int NumArchSwitches, INP t_segment_inf* segment_inf); -static void setup_junction_switch(struct s_det_routing_arch *det_routing_arch); -static void add_wire_to_switch(struct s_det_routing_arch *det_routing_arch); -static void set_max_pins_per_side(); -static void hack_switch_to_rram(struct s_det_routing_arch *det_routing_arch); -/* end */ - -void VPRSetupArch(t_arch* arch, - t_det_routing_arch* RoutingArch, - t_segment_inf ** Segments, - /*Xifan TANG: Switch Segment Pattern Support*/ - t_swseg_pattern_inf** swseg_patterns, - t_model** user_models, - t_model** library_models) { - int i, j; - - (*user_models) = arch->models; - (*library_models) = arch->model_library; - - /* TODO: this is inelegant, I should be populating this information in XmlReadArch */ - EMPTY_TYPE = NULL; - FILL_TYPE = NULL; - IO_TYPE = NULL; - for (i = 0; i < num_types; i++) { - if (strcmp(type_descriptors[i].name, "") == 0) { - EMPTY_TYPE = &type_descriptors[i]; - } else if (strcmp(type_descriptors[i].name, "io") == 0) { - IO_TYPE = &type_descriptors[i]; - } else { - for (j = 0; j < type_descriptors[i].num_grid_loc_def; j++) { - if (type_descriptors[i].grid_loc_def[j].grid_loc_type == FILL) { - assert(FILL_TYPE == NULL); - FILL_TYPE = &type_descriptors[i]; - } - } - } - } - assert(EMPTY_TYPE != NULL && FILL_TYPE != NULL && IO_TYPE != NULL); - - *Segments = arch->Segments; - RoutingArch->num_segment = arch->num_segments; - /*Xifan TANG: Switch Segment Pattern Support*/ - (*swseg_patterns) = arch->swseg_patterns; - RoutingArch->num_swseg_pattern = arch->num_swseg_pattern; - /* END */ - - /* mrFPGA */ - sync_arch_mrfpga_globals(arch->arch_mrfpga); - if (is_mrFPGA) { - SetupSwitches_mrFPGA(*arch, RoutingArch, - arch->Switches, arch->num_switches, arch->Segments); - /* Xifan TANG: added by bjxiao */ - set_max_pins_per_side(); - hack_switch_to_rram(RoutingArch); - } else { - /* Normal Setup VPR switches */ - // Xifan TANG: Add Connection Blocks Switches - SetupSwitches(*arch, RoutingArch, - arch->Switches, arch->num_switches); - } - /* END */ - - /* end */ - if(!is_mrFPGA && is_stack) { - add_wire_to_switch(RoutingArch); - } - /* end */ - /* Xifan TANG: mrFPGA */ - if (is_junction) { - setup_junction_switch(RoutingArch); - } - /* end */ - - SetupRoutingArch(*arch, RoutingArch); - - return; -} - -/* Sets VPR parameters and defaults. Does not do any error checking - * as this should have been done by the various input checkers */ -void SetupVPR(INP t_options *Options, INP boolean TimingEnabled, - INP boolean readArchFile, OUTP struct s_file_name_opts *FileNameOpts, - INOUTP t_arch * Arch, OUTP enum e_operation *Operation, - OUTP t_model ** user_models, OUTP t_model ** library_models, - OUTP struct s_packer_opts *PackerOpts, - OUTP struct s_placer_opts *PlacerOpts, - OUTP struct s_annealing_sched *AnnealSched, - OUTP struct s_router_opts *RouterOpts, - OUTP struct s_det_routing_arch *RoutingArch, - OUTP t_segment_inf ** Segments, OUTP t_timing_inf * Timing, - OUTP boolean * ShowGraphics, OUTP int *GraphPause, - t_power_opts * PowerOpts, - /*Xifan TANG: Switch Segment Pattern Support*/ - t_swseg_pattern_inf** swseg_patterns, - t_fpga_spice_opts* fpga_spice_opts) { - int len; - - len = strlen(Options->CircuitName) + 6; /* circuit_name.blif/0*/ - if (Options->out_file_prefix != NULL ) { - len += strlen(Options->out_file_prefix); - } - default_output_name = (char*) my_calloc(len, sizeof(char)); - if (Options->out_file_prefix == NULL ) { - sprintf(default_output_name, "%s", Options->CircuitName); - } else { - sprintf(default_output_name, "%s%s", Options->out_file_prefix, - Options->CircuitName); - } - - /* init default filenames */ - if (Options->BlifFile == NULL ) { - len = strlen(Options->CircuitName) + 6; /* circuit_name.blif/0*/ - if (Options->out_file_prefix != NULL ) { - len += strlen(Options->out_file_prefix); - } - Options->BlifFile = (char*) my_calloc(len, sizeof(char)); - if (Options->out_file_prefix == NULL ) { - sprintf(Options->BlifFile, "%s.blif", Options->CircuitName); - } else { - sprintf(Options->BlifFile, "%s%s.blif", Options->out_file_prefix, - Options->CircuitName); - } - } - - if (Options->NetFile == NULL ) { - len = strlen(Options->CircuitName) + 5; /* circuit_name.net/0*/ - if (Options->out_file_prefix != NULL ) { - len += strlen(Options->out_file_prefix); - } - Options->NetFile = (char*) my_calloc(len, sizeof(char)); - if (Options->out_file_prefix == NULL ) { - sprintf(Options->NetFile, "%s.net", Options->CircuitName); - } else { - sprintf(Options->NetFile, "%s%s.net", Options->out_file_prefix, - Options->CircuitName); - } - } - - if (Options->PlaceFile == NULL ) { - len = strlen(Options->CircuitName) + 7; /* circuit_name.place/0*/ - if (Options->out_file_prefix != NULL ) { - len += strlen(Options->out_file_prefix); - } - Options->PlaceFile = (char*) my_calloc(len, sizeof(char)); - if (Options->out_file_prefix == NULL ) { - sprintf(Options->PlaceFile, "%s.place", Options->CircuitName); - } else { - sprintf(Options->PlaceFile, "%s%s.place", Options->out_file_prefix, - Options->CircuitName); - } - } - - if (Options->RouteFile == NULL ) { - len = strlen(Options->CircuitName) + 7; /* circuit_name.route/0*/ - if (Options->out_file_prefix != NULL ) { - len += strlen(Options->out_file_prefix); - } - Options->RouteFile = (char*) my_calloc(len, sizeof(char)); - if (Options->out_file_prefix == NULL ) { - sprintf(Options->RouteFile, "%s.route", Options->CircuitName); - } else { - sprintf(Options->RouteFile, "%s%s.route", Options->out_file_prefix, - Options->CircuitName); - } - } - if (Options->ActFile == NULL ) { - len = strlen(Options->CircuitName) + 7; /* circuit_name.route/0*/ - if (Options->out_file_prefix != NULL ) { - len += strlen(Options->out_file_prefix); - } - Options->ActFile = (char*) my_calloc(len, sizeof(char)); - if (Options->out_file_prefix == NULL ) { - sprintf(Options->ActFile, "%s.act", Options->CircuitName); - } else { - sprintf(Options->ActFile, "%s%s.act", Options->out_file_prefix, - Options->CircuitName); - } - } - - if (Options->PowerFile == NULL ) { - len = strlen(Options->CircuitName) + 7; /* circuit_name.power\0*/ - if (Options->out_file_prefix != NULL ) { - len += strlen(Options->out_file_prefix); - } - Options->PowerFile = (char*) my_calloc(len, sizeof(char)); - if (Options->out_file_prefix == NULL ) { - sprintf(Options->PowerFile, "%s.power", Options->CircuitName); - } else { - sprintf(Options->ActFile, "%s%s.power", Options->out_file_prefix, - Options->CircuitName); - } - } - - alloc_and_load_output_file_names(default_output_name); - - FileNameOpts->CircuitName = Options->CircuitName; - FileNameOpts->ArchFile = Options->ArchFile; - FileNameOpts->BlifFile = Options->BlifFile; - FileNameOpts->NetFile = Options->NetFile; - FileNameOpts->PlaceFile = Options->PlaceFile; - FileNameOpts->RouteFile = Options->RouteFile; - FileNameOpts->ActFile = Options->ActFile; - FileNameOpts->PowerFile = Options->PowerFile; - FileNameOpts->CmosTechFile = Options->CmosTechFile; - FileNameOpts->out_file_prefix = Options->out_file_prefix; - - SetupOperation(*Options, Operation); - SetupPlacerOpts(*Options, TimingEnabled, PlacerOpts); - SetupAnnealSched(*Options, AnnealSched); - SetupRouterOpts(*Options, TimingEnabled, RouterOpts); - SetupPowerOpts(*Options, PowerOpts, Arch); - - /* Xifan TANG: FPGA-SPICE Tool suites Options Setup */ - SetupFpgaSpiceOpts(*Options, fpga_spice_opts, Arch); - /* END */ - - if (readArchFile == TRUE) { - XmlReadArch(Options->ArchFile, TimingEnabled, Arch, &type_descriptors, - &num_types); - } - - VPRSetupArch(Arch, RoutingArch, Segments, swseg_patterns, user_models, library_models); - - SetupTiming(*Options, *Arch, TimingEnabled, *Operation, *PlacerOpts, - *RouterOpts, Timing); - SetupPackerOpts(*Options, TimingEnabled, *Arch, Options->NetFile, - PackerOpts); - - /* init global variables */ - out_file_prefix = Options->out_file_prefix; - grid_logic_tile_area = Arch->grid_logic_tile_area; - ipin_mux_trans_size = Arch->ipin_mux_trans_size; - - /* Set seed for pseudo-random placement, default seed to 1 */ - PlacerOpts->seed = 1; - if (Options->Count[OT_SEED]) { - PlacerOpts->seed = Options->Seed; - } - my_srandom(PlacerOpts->seed); - - /* Build the complex block graph */ - vpr_printf(TIO_MESSAGE_INFO, "Building complex block graph.\n"); - alloc_and_load_all_pb_graphs(PowerOpts->do_power); - - /* Xifan Tang: Initialize the clb to clb directs */ - alloc_and_init_globals_clb_to_clb_directs(Arch->num_directs, Arch->Directs); - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_PB_GRAPH)) { - echo_pb_graph(getEchoFileName(E_ECHO_PB_GRAPH)); - } - - *GraphPause = 1; /* DEFAULT */ - if (Options->Count[OT_AUTO]) { - *GraphPause = Options->GraphPause; - } -#ifdef NO_GRAPHICS - *ShowGraphics = FALSE; /* DEFAULT */ -#else /* NO_GRAPHICS */ - *ShowGraphics = TRUE; /* DEFAULT */ - if (Options->Count[OT_NODISP]) { - *ShowGraphics = FALSE; - } -#endif /* NO_GRAPHICS */ - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_ARCH)) { - EchoArch(getEchoFileName(E_ECHO_ARCH), type_descriptors, num_types, - Arch); - } - -} - -static void SetupTiming(INP t_options Options, INP t_arch Arch, - INP boolean TimingEnabled, INP enum e_operation Operation, - INP struct s_placer_opts PlacerOpts, - INP struct s_router_opts RouterOpts, OUTP t_timing_inf * Timing) { - - /* Don't do anything if they don't want timing */ - if (FALSE == TimingEnabled) { - memset(Timing, 0, sizeof(t_timing_inf)); - Timing->timing_analysis_enabled = FALSE; - return; - } - - Timing->C_ipin_cblock = Arch.C_ipin_cblock; - Timing->T_ipin_cblock = Arch.T_ipin_cblock; - Timing->timing_analysis_enabled = TimingEnabled; - - /* If the user specified an SDC filename on the command line, look for specified_name.sdc, otherwise look for circuit_name.sdc*/ - if (Options.SDCFile == NULL ) { - Timing->SDCFile = (char*) my_calloc(strlen(Options.CircuitName) + 5, - sizeof(char)); /* circuit_name.sdc/0*/ - sprintf(Timing->SDCFile, "%s.sdc", Options.CircuitName); - } else { - Timing->SDCFile = (char*) my_strdup(Options.SDCFile); - } -} - -/* This loads up VPR's switch_inf data by combining the switches from - * the arch file with the special switches that VPR needs. */ -static void SetupSwitches(INP t_arch Arch, - INOUTP struct s_det_routing_arch *RoutingArch, - INP struct s_switch_inf *ArchSwitches, INP int NumArchSwitches) { - - RoutingArch->num_switch = NumArchSwitches; - - /* Depends on RoutingArch->num_switch */ - RoutingArch->wire_to_ipin_switch = RoutingArch->num_switch; - ++RoutingArch->num_switch; - - /* Depends on RoutingArch->num_switch */ - RoutingArch->delayless_switch = RoutingArch->num_switch; - RoutingArch->global_route_switch = RoutingArch->delayless_switch; - ++RoutingArch->num_switch; - - /* Alloc the list now that we know the final num_switch value */ - switch_inf = (struct s_switch_inf *) my_malloc( - sizeof(struct s_switch_inf) * RoutingArch->num_switch); - - /* Copy the switch data from architecture file */ - memcpy(switch_inf, ArchSwitches, - sizeof(struct s_switch_inf) * NumArchSwitches); - - /* Delayless switch for connecting sinks and sources with their pins. */ - switch_inf[RoutingArch->delayless_switch].buffered = TRUE; - switch_inf[RoutingArch->delayless_switch].R = 0.; - switch_inf[RoutingArch->delayless_switch].Cin = 0.; - switch_inf[RoutingArch->delayless_switch].Cout = 0.; - switch_inf[RoutingArch->delayless_switch].Tdel = 0.; - switch_inf[RoutingArch->delayless_switch].power_buffer_type = POWER_BUFFER_TYPE_NONE; - switch_inf[RoutingArch->delayless_switch].mux_trans_size = 0.; - /* Xifan TANG: SPICE model support*/ - switch_inf[RoutingArch->delayless_switch].spice_model_name = NULL; - switch_inf[RoutingArch->delayless_switch].spice_model = NULL; - - /* The wire to ipin switch for all types. Curently all types - * must share ipin switch. Some of the timing code would - * need to be changed otherwise. */ - /* Xifan TANG: Enhancement for connection blocks */ - if (0 == Arch.num_cb_switch) { - switch_inf[RoutingArch->wire_to_ipin_switch].buffered = TRUE; - switch_inf[RoutingArch->wire_to_ipin_switch].R = 0.; - switch_inf[RoutingArch->wire_to_ipin_switch].Cin = Arch.C_ipin_cblock; - switch_inf[RoutingArch->wire_to_ipin_switch].Cout = 0.; - switch_inf[RoutingArch->wire_to_ipin_switch].Tdel = Arch.T_ipin_cblock; - switch_inf[RoutingArch->wire_to_ipin_switch].power_buffer_type = POWER_BUFFER_TYPE_NONE; - switch_inf[RoutingArch->wire_to_ipin_switch].mux_trans_size = 0.; - switch_inf[RoutingArch->wire_to_ipin_switch].spice_model_name = NULL; - switch_inf[RoutingArch->wire_to_ipin_switch].spice_model = NULL; - } else { - /* Xifan TANG: Currently we only support 1 connection blocks switch defined.*/ - assert(1 == Arch.num_cb_switch); - memcpy(&switch_inf[RoutingArch->wire_to_ipin_switch], Arch.cb_switches, - sizeof(struct s_switch_inf) * Arch.num_cb_switch); - } -} - -/* This loads up VPR's switch_inf data by combining the switches from - * the arch file with the special switches that VPR needs. */ -static void SetupSwitches_mrFPGA(INP t_arch Arch, - INOUTP struct s_det_routing_arch *RoutingArch, - INP struct s_switch_inf *ArchSwitches, INP int NumArchSwitches, INP t_segment_inf* segment_inf) { - int i/*, switch_index*/; - - RoutingArch->num_switch = NumArchSwitches; - - /* mrFPGA : Xifan TANG*/ - /* Xifan TANG: only overwrite it when it is defined*/ - num_normal_switch = NumArchSwitches; - if (is_mrFPGA && Arch.arch_mrfpga.is_opin_cblock_defined) { - RoutingArch->opin_to_wire_switch = RoutingArch->num_switch; - ++RoutingArch->num_switch; - } - /* end */ - - /* Depends on RoutingArch->num_switch */ - RoutingArch->wire_to_ipin_switch = RoutingArch->num_switch; - ++RoutingArch->num_switch; - - /* Depends on RoutingArch->num_switch */ - RoutingArch->delayless_switch = RoutingArch->num_switch; - RoutingArch->global_route_switch = RoutingArch->delayless_switch; - ++RoutingArch->num_switch; - - /*mrFPGA: Xifan TANG*/ - start_seg_switch = RoutingArch->num_switch; - /* END */ - - /* Alloc the list now that we know the final num_switch value */ - switch_inf = (struct s_switch_inf *) my_malloc( - sizeof(struct s_switch_inf) * RoutingArch->num_switch); - - /* Copy the switch data from architecture file */ - memcpy(switch_inf, ArchSwitches, - sizeof(struct s_switch_inf) * NumArchSwitches); - - /* Delayless switch for connecting sinks and sources with their pins. */ - switch_inf[RoutingArch->delayless_switch].buffered = TRUE; - switch_inf[RoutingArch->delayless_switch].R = 0.; - switch_inf[RoutingArch->delayless_switch].Cin = 0.; - switch_inf[RoutingArch->delayless_switch].Cout = 0.; - switch_inf[RoutingArch->delayless_switch].Tdel = 0.; - switch_inf[RoutingArch->delayless_switch].power_buffer_type = POWER_BUFFER_TYPE_NONE; - switch_inf[RoutingArch->delayless_switch].mux_trans_size = 0.; - /* Xifan TANG: easy to identify internal built switch*/ - switch_inf[RoutingArch->delayless_switch].type = "buffer"; - switch_inf[RoutingArch->delayless_switch].name = "delayless_switch"; - /* end */ - /* Xifan TANG: SPICE model support*/ - switch_inf[RoutingArch->delayless_switch].spice_model_name = NULL; - switch_inf[RoutingArch->delayless_switch].spice_model = NULL; - /* END */ - - /* The wire to ipin switch for all types. Curently all types - * must share ipin switch. Some of the timing code would - * need to be changed otherwise. */ - /* Xifan TANG: Enhancement for connection blocks */ - if (0 == Arch.num_cb_switch) { - switch_inf[RoutingArch->wire_to_ipin_switch].buffered = TRUE; - switch_inf[RoutingArch->wire_to_ipin_switch].R = 0.; - switch_inf[RoutingArch->wire_to_ipin_switch].Cin = Arch.C_ipin_cblock; - switch_inf[RoutingArch->wire_to_ipin_switch].Cout = 0.; - switch_inf[RoutingArch->wire_to_ipin_switch].Tdel = Arch.T_ipin_cblock; - switch_inf[RoutingArch->wire_to_ipin_switch].power_buffer_type = POWER_BUFFER_TYPE_NONE; - switch_inf[RoutingArch->wire_to_ipin_switch].mux_trans_size = 0.; - /* Xifan TANG: easy to identify internal built switch*/ - switch_inf[RoutingArch->wire_to_ipin_switch].type = "buffer"; - switch_inf[RoutingArch->wire_to_ipin_switch].name = "wire_to_ipin_switch"; - /* end */ - switch_inf[RoutingArch->wire_to_ipin_switch].spice_model_name = NULL; - switch_inf[RoutingArch->wire_to_ipin_switch].spice_model = NULL; - } else { - /* Xifan TANG: Currently we only support 1 connection blocks switch defined.*/ - assert(1 == Arch.num_cb_switch); - memcpy(&switch_inf[RoutingArch->wire_to_ipin_switch], Arch.cb_switches, - sizeof(struct s_switch_inf) * Arch.num_cb_switch); - } - /* END */ - - /* mrFPGA: Xifan TANG */ - if (is_mrFPGA && Arch.arch_mrfpga.is_opin_cblock_defined) { - switch_inf[RoutingArch->opin_to_wire_switch].buffered = TRUE; - switch_inf[RoutingArch->opin_to_wire_switch].R = Arch.arch_mrfpga.R_opin_cblock; - switch_inf[RoutingArch->opin_to_wire_switch].Cin = 0.; - switch_inf[RoutingArch->opin_to_wire_switch].Cout = 0.; - switch_inf[RoutingArch->opin_to_wire_switch].Tdel = Arch.arch_mrfpga.T_opin_cblock; - /* Xifan TANG: name should be specified!!!*/ - switch_inf[RoutingArch->opin_to_wire_switch].power_buffer_type = POWER_BUFFER_TYPE_NONE; - switch_inf[RoutingArch->opin_to_wire_switch].mux_trans_size = 0.; - switch_inf[RoutingArch->opin_to_wire_switch].type = "buffer"; - switch_inf[RoutingArch->opin_to_wire_switch].name = "mrFPGA_opin_switch"; - switch_inf[RoutingArch->opin_to_wire_switch].spice_model_name = NULL; - switch_inf[RoutingArch->opin_to_wire_switch].spice_model = NULL; - } - - for (i = 0; i < RoutingArch->num_segment; i++ ) { - /* Xifan TANG: only overwrite it when it is defined*/ - if (is_mrFPGA && Arch.arch_mrfpga.is_opin_cblock_defined) { - segment_inf[i].opin_switch = RoutingArch->opin_to_wire_switch; - } - } - /* end */ -} - - - - -/* Sets up routing structures. Since checks are already done, this - * just copies values across */ -static void SetupRoutingArch(INP t_arch Arch, - OUTP struct s_det_routing_arch *RoutingArch) { - - RoutingArch->switch_block_type = Arch.SBType; - RoutingArch->switch_block_sub_type = Arch.SBSubType; - RoutingArch->R_minW_nmos = Arch.R_minW_nmos; - RoutingArch->R_minW_pmos = Arch.R_minW_pmos; - RoutingArch->Fs = Arch.Fs; - RoutingArch->sub_Fs = Arch.SubFs; - RoutingArch->wire_opposite_side = Arch.wire_opposite_side; - RoutingArch->directionality = BI_DIRECTIONAL; - if (Arch.Segments) - RoutingArch->directionality = Arch.Segments[0].directionality; - RoutingArch->tileable = Arch.tileable; -} - -static void SetupRouterOpts(INP t_options Options, INP boolean TimingEnabled, - OUTP struct s_router_opts *RouterOpts) { - RouterOpts->astar_fac = 1.2; /* DEFAULT */ - if (Options.Count[OT_ASTAR_FAC]) { - RouterOpts->astar_fac = Options.astar_fac; - } - - RouterOpts->bb_factor = 3; /* DEFAULT */ - if (Options.Count[OT_FAST]) { - RouterOpts->bb_factor = 0; /* DEFAULT */ - } - if (Options.Count[OT_BB_FACTOR]) { - RouterOpts->bb_factor = Options.bb_factor; - } - - RouterOpts->criticality_exp = 1.0; /* DEFAULT */ - if (Options.Count[OT_CRITICALITY_EXP]) { - RouterOpts->criticality_exp = Options.criticality_exp; - } - - RouterOpts->max_criticality = 0.99; /* DEFAULT */ - if (Options.Count[OT_MAX_CRITICALITY]) { - RouterOpts->max_criticality = Options.max_criticality; - } - - RouterOpts->max_router_iterations = 50; /* DEFAULT */ - if (Options.Count[OT_FAST]) { - RouterOpts->max_router_iterations = 10; - } - if (Options.Count[OT_MAX_ROUTER_ITERATIONS]) { - RouterOpts->max_router_iterations = Options.max_router_iterations; - } - - RouterOpts->pres_fac_mult = 1.3; /* DEFAULT */ - if (Options.Count[OT_PRES_FAC_MULT]) { - RouterOpts->pres_fac_mult = Options.pres_fac_mult; - } - - RouterOpts->route_type = DETAILED; /* DEFAULT */ - if (Options.Count[OT_ROUTE_TYPE]) { - RouterOpts->route_type = Options.RouteType; - } - - RouterOpts->full_stats = FALSE; /* DEFAULT */ - if (Options.Count[OT_FULL_STATS]) { - RouterOpts->full_stats = TRUE; - } - - RouterOpts->verify_binary_search = FALSE; /* DEFAULT */ - if (Options.Count[OT_VERIFY_BINARY_SEARCH]) { - RouterOpts->verify_binary_search = TRUE; - } - - /* Depends on RouteOpts->route_type */ - RouterOpts->router_algorithm = NO_TIMING; /* DEFAULT */ - if (TimingEnabled) { - RouterOpts->router_algorithm = TIMING_DRIVEN; /* DEFAULT */ - } - if (GLOBAL == RouterOpts->route_type) { - RouterOpts->router_algorithm = NO_TIMING; /* DEFAULT */ - } - if (Options.Count[OT_ROUTER_ALGORITHM]) { - RouterOpts->router_algorithm = Options.RouterAlgorithm; - } - - RouterOpts->fixed_channel_width = NO_FIXED_CHANNEL_WIDTH; /* DEFAULT */ - if (Options.Count[OT_ROUTE_CHAN_WIDTH]) { - RouterOpts->fixed_channel_width = Options.RouteChanWidth; - } - - /* mrFPGA: Xifan TANG */ - is_show_sram = FALSE; - if (Options.Count[OT_SHOW_SRAM]) { - is_show_sram = TRUE; - } - is_show_pass_trans = FALSE; - if (Options.Count[OT_SHOW_PASS_TRANS]) { - is_show_pass_trans = TRUE; - } - /* END */ - - /* Xifan Tang: Tileable routing support !!! */ - RouterOpts->use_tileable_route_chan_width = FALSE; - if (Options.Count[OT_USE_TILEABLE_ROUTE_CHAN_WIDTH]) { - RouterOpts->use_tileable_route_chan_width = TRUE; - } - /* END */ - - /* Depends on RouterOpts->router_algorithm */ - RouterOpts->initial_pres_fac = 0.5; /* DEFAULT */ - if (NO_TIMING == RouterOpts->router_algorithm || Options.Count[OT_FAST]) { - RouterOpts->initial_pres_fac = 10000.0; /* DEFAULT */ - } - if (Options.Count[OT_INITIAL_PRES_FAC]) { - RouterOpts->initial_pres_fac = Options.initial_pres_fac; - } - - /* Depends on RouterOpts->router_algorithm */ - RouterOpts->base_cost_type = DELAY_NORMALIZED; /* DEFAULT */ - if (BREADTH_FIRST == RouterOpts->router_algorithm) { - RouterOpts->base_cost_type = DEMAND_ONLY; /* DEFAULT */ - } - if (NO_TIMING == RouterOpts->router_algorithm) { - RouterOpts->base_cost_type = DEMAND_ONLY; /* DEFAULT */ - } - if (Options.Count[OT_BASE_COST_TYPE]) { - RouterOpts->base_cost_type = Options.base_cost_type; - } - - /* Depends on RouterOpts->router_algorithm */ - RouterOpts->first_iter_pres_fac = 0.5; /* DEFAULT */ - if (BREADTH_FIRST == RouterOpts->router_algorithm) { - RouterOpts->first_iter_pres_fac = 0.0; /* DEFAULT */ - } - if (NO_TIMING == RouterOpts->router_algorithm || Options.Count[OT_FAST]) { - RouterOpts->first_iter_pres_fac = 10000.0; /* DEFAULT */ - } - if (Options.Count[OT_FIRST_ITER_PRES_FAC]) { - RouterOpts->first_iter_pres_fac = Options.first_iter_pres_fac; - } - - /* Depends on RouterOpts->router_algorithm */ - RouterOpts->acc_fac = 1.0; - if (BREADTH_FIRST == RouterOpts->router_algorithm) { - RouterOpts->acc_fac = 0.2; - } - if (Options.Count[OT_ACC_FAC]) { - RouterOpts->acc_fac = Options.acc_fac; - } - - /* Depends on RouterOpts->route_type */ - RouterOpts->bend_cost = 0.0; /* DEFAULT */ - if (GLOBAL == RouterOpts->route_type) { - RouterOpts->bend_cost = 1.0; /* DEFAULT */ - } - if (Options.Count[OT_BEND_COST]) { - RouterOpts->bend_cost = Options.bend_cost; - } - - RouterOpts->doRouting = FALSE; - if (Options.Count[OT_ROUTE]) { - RouterOpts->doRouting = TRUE; - } else if (!Options.Count[OT_PACK] && !Options.Count[OT_PLACE] - && !Options.Count[OT_ROUTE]) { - if (!Options.Count[OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY]) - RouterOpts->doRouting = TRUE; - } - -} - -static void SetupAnnealSched(INP t_options Options, - OUTP struct s_annealing_sched *AnnealSched) { - AnnealSched->alpha_t = 0.8; /* DEFAULT */ - if (Options.Count[OT_ALPHA_T]) { - AnnealSched->alpha_t = Options.PlaceAlphaT; - } - if (AnnealSched->alpha_t >= 1 || AnnealSched->alpha_t <= 0) { - vpr_printf(TIO_MESSAGE_ERROR, - "alpha_t must be between 0 and 1 exclusive.\n"); - exit(1); - } - AnnealSched->exit_t = 0.01; /* DEFAULT */ - if (Options.Count[OT_EXIT_T]) { - AnnealSched->exit_t = Options.PlaceExitT; - } - if (AnnealSched->exit_t <= 0) { - vpr_printf(TIO_MESSAGE_ERROR, "exit_t must be greater than 0.\n"); - exit(1); - } - AnnealSched->init_t = 100.0; /* DEFAULT */ - if (Options.Count[OT_INIT_T]) { - AnnealSched->init_t = Options.PlaceInitT; - } - if (AnnealSched->init_t <= 0) { - vpr_printf(TIO_MESSAGE_ERROR, "init_t must be greater than 0.\n"); - exit(1); - } - if (AnnealSched->init_t < AnnealSched->exit_t) { - vpr_printf(TIO_MESSAGE_ERROR, - "init_t must be greater or equal to than exit_t.\n"); - exit(1); - } - AnnealSched->inner_num = 1.0; /* DEFAULT */ - if (Options.Count[OT_INNER_NUM]) { - AnnealSched->inner_num = Options.PlaceInnerNum; - } - if (AnnealSched->inner_num <= 0) { - vpr_printf(TIO_MESSAGE_ERROR, "init_t must be greater than 0.\n"); - exit(1); - } - AnnealSched->type = AUTO_SCHED; /* DEFAULT */ - if ((Options.Count[OT_ALPHA_T]) || (Options.Count[OT_EXIT_T]) - || (Options.Count[OT_INIT_T])) { - AnnealSched->type = USER_SCHED; - } -} - -/* Sets up the s_packer_opts structure baesd on users inputs and on the architecture specified. - * Error checking, such as checking for conflicting params is assumed to be done beforehand - */ -void SetupPackerOpts(INP t_options Options, INP boolean TimingEnabled, - INP t_arch Arch, INP char *net_file, - OUTP struct s_packer_opts *PackerOpts) { - - if (Arch.clb_grid.IsAuto) { - PackerOpts->aspect = Arch.clb_grid.Aspect; - } else { - PackerOpts->aspect = (float) Arch.clb_grid.H / (float) Arch.clb_grid.W; - } - PackerOpts->output_file = net_file; - - PackerOpts->blif_file_name = Options.BlifFile; - - PackerOpts->doPacking = FALSE; /* DEFAULT */ - if (Options.Count[OT_PACK]) { - PackerOpts->doPacking = TRUE; - } else if (!Options.Count[OT_PACK] && !Options.Count[OT_PLACE] - && !Options.Count[OT_ROUTE]) { - if (!Options.Count[OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY]) - PackerOpts->doPacking = TRUE; - } - - PackerOpts->global_clocks = TRUE; /* DEFAULT */ - if (Options.Count[OT_GLOBAL_CLOCKS]) { - PackerOpts->global_clocks = Options.global_clocks; - } - - PackerOpts->hill_climbing_flag = FALSE; /* DEFAULT */ - if (Options.Count[OT_HILL_CLIMBING_FLAG]) { - PackerOpts->hill_climbing_flag = Options.hill_climbing_flag; - } - - PackerOpts->sweep_hanging_nets_and_inputs = TRUE; - if (Options.Count[OT_SWEEP_HANGING_NETS_AND_INPUTS]) { - PackerOpts->sweep_hanging_nets_and_inputs = - Options.sweep_hanging_nets_and_inputs; - } - - PackerOpts->skip_clustering = FALSE; /* DEFAULT */ - if (Options.Count[OT_SKIP_CLUSTERING]) { - PackerOpts->skip_clustering = TRUE; - } - PackerOpts->allow_unrelated_clustering = TRUE; /* DEFAULT */ - if (Options.Count[OT_ALLOW_UNRELATED_CLUSTERING]) { - PackerOpts->allow_unrelated_clustering = - Options.allow_unrelated_clustering; - } - PackerOpts->allow_early_exit = FALSE; /* DEFAULT */ - if (Options.Count[OT_ALLOW_EARLY_EXIT]) { - PackerOpts->allow_early_exit = Options.allow_early_exit; - } - PackerOpts->connection_driven = TRUE; /* DEFAULT */ - if (Options.Count[OT_CONNECTION_DRIVEN_CLUSTERING]) { - PackerOpts->connection_driven = Options.connection_driven; - } - - PackerOpts->timing_driven = TimingEnabled; /* DEFAULT */ - if (Options.Count[OT_TIMING_DRIVEN_CLUSTERING]) { - PackerOpts->timing_driven = Options.timing_driven; - } - PackerOpts->cluster_seed_type = ( - TimingEnabled ? VPACK_TIMING : VPACK_MAX_INPUTS); /* DEFAULT */ - if (Options.Count[OT_CLUSTER_SEED]) { - PackerOpts->cluster_seed_type = Options.cluster_seed_type; - } - PackerOpts->alpha = 0.75; /* DEFAULT */ - if (Options.Count[OT_ALPHA_CLUSTERING]) { - PackerOpts->alpha = Options.alpha; - } - PackerOpts->beta = 0.9; /* DEFAULT */ - if (Options.Count[OT_BETA_CLUSTERING]) { - PackerOpts->beta = Options.beta; - } - - /* never recomputer timing */ - PackerOpts->recompute_timing_after = MAX_SHORT; /* DEFAULT */ - if (Options.Count[OT_RECOMPUTE_TIMING_AFTER]) { - PackerOpts->recompute_timing_after = Options.recompute_timing_after; - } - PackerOpts->block_delay = 0; /* DEFAULT */ - if (Options.Count[OT_CLUSTER_BLOCK_DELAY]) { - PackerOpts->block_delay = Options.block_delay; - } - PackerOpts->intra_cluster_net_delay = 0; /* DEFAULT */ - if (Options.Count[OT_INTRA_CLUSTER_NET_DELAY]) { - PackerOpts->intra_cluster_net_delay = Options.intra_cluster_net_delay; - } - PackerOpts->inter_cluster_net_delay = 1.0; /* DEFAULT */ - PackerOpts->auto_compute_inter_cluster_net_delay = TRUE; - if (Options.Count[OT_INTER_CLUSTER_NET_DELAY]) { - PackerOpts->inter_cluster_net_delay = Options.inter_cluster_net_delay; - PackerOpts->auto_compute_inter_cluster_net_delay = FALSE; - } - - PackerOpts->packer_algorithm = PACK_GREEDY; /* DEFAULT */ - if (Options.Count[OT_PACKER_ALGORITHM]) { - PackerOpts->packer_algorithm = Options.packer_algorithm; - } - - /* Xifan TANG: PACK_CLB_PIN_REMAP */ - PackerOpts->pack_clb_pin_remap = FALSE; /* DEFAULT */ - if (Options.Count[OT_PACK_CLB_PIN_REMAP]) { - PackerOpts->pack_clb_pin_remap = TRUE; - } - -} - -/* Sets up the s_placer_opts structure based on users input. Error checking, - * such as checking for conflicting params is assumed to be done beforehand */ -static void SetupPlacerOpts(INP t_options Options, INP boolean TimingEnabled, - OUTP struct s_placer_opts *PlacerOpts) { - PlacerOpts->block_dist = 1; /* DEFAULT */ - if (Options.Count[OT_BLOCK_DIST]) { - PlacerOpts->block_dist = Options.block_dist; - } - - PlacerOpts->inner_loop_recompute_divider = 0; /* DEFAULT */ - if (Options.Count[OT_INNER_LOOP_RECOMPUTE_DIVIDER]) { - PlacerOpts->inner_loop_recompute_divider = - Options.inner_loop_recompute_divider; - } - - PlacerOpts->place_cost_exp = 1.; /* DEFAULT */ - if (Options.Count[OT_PLACE_COST_EXP]) { - PlacerOpts->place_cost_exp = Options.place_cost_exp; - } - - PlacerOpts->td_place_exp_first = 1.; /* DEFAULT */ - if (Options.Count[OT_TD_PLACE_EXP_FIRST]) { - PlacerOpts->td_place_exp_first = Options.place_exp_first; - } - - PlacerOpts->td_place_exp_last = 8.; /* DEFAULT */ - if (Options.Count[OT_TD_PLACE_EXP_LAST]) { - PlacerOpts->td_place_exp_last = Options.place_exp_last; - } - - PlacerOpts->place_algorithm = BOUNDING_BOX_PLACE; /* DEFAULT */ - if (TimingEnabled) { - PlacerOpts->place_algorithm = PATH_TIMING_DRIVEN_PLACE; /* DEFAULT */ - } - if (Options.Count[OT_PLACE_ALGORITHM]) { - PlacerOpts->place_algorithm = Options.PlaceAlgorithm; - } - - PlacerOpts->pad_loc_file = NULL; /* DEFAULT */ - if (Options.Count[OT_FIX_PINS]) { - if (Options.PinFile) { - PlacerOpts->pad_loc_file = my_strdup(Options.PinFile); - } - } - - PlacerOpts->pad_loc_type = FREE; /* DEFAULT */ - if (Options.Count[OT_FIX_PINS]) { - PlacerOpts->pad_loc_type = (Options.PinFile ? USER : RANDOM); - } - - PlacerOpts->place_chan_width = 100; /* DEFAULT */ - if (Options.Count[OT_PLACE_CHAN_WIDTH]) { - PlacerOpts->place_chan_width = Options.PlaceChanWidth; - } - - PlacerOpts->recompute_crit_iter = 1; /* DEFAULT */ - if (Options.Count[OT_RECOMPUTE_CRIT_ITER]) { - PlacerOpts->recompute_crit_iter = Options.RecomputeCritIter; - } - - PlacerOpts->timing_tradeoff = 0.5; /* DEFAULT */ - if (Options.Count[OT_TIMING_TRADEOFF]) { - PlacerOpts->timing_tradeoff = Options.PlaceTimingTradeoff; - } - - /* Xifan TANG : PLACE_CLB_PIN_REMAP */ - PlacerOpts->place_clb_pin_remap = FALSE; /* DEFAULT */ - if (Options.Count[OT_PLACE_CLB_PIN_REMAP]) { - PlacerOpts->place_clb_pin_remap = TRUE; - } - /* END */ - - /* Depends on PlacerOpts->place_algorithm */ - PlacerOpts->enable_timing_computations = FALSE; /* DEFAULT */ - if ((PlacerOpts->place_algorithm == PATH_TIMING_DRIVEN_PLACE) - || (PlacerOpts->place_algorithm == NET_TIMING_DRIVEN_PLACE)) { - PlacerOpts->enable_timing_computations = TRUE; /* DEFAULT */ - } - if (Options.Count[OT_ENABLE_TIMING_COMPUTATIONS]) { - PlacerOpts->enable_timing_computations = Options.ShowPlaceTiming; - } - - PlacerOpts->place_freq = PLACE_ONCE; /* DEFAULT */ - if ((Options.Count[OT_ROUTE_CHAN_WIDTH]) - || (Options.Count[OT_PLACE_CHAN_WIDTH])) { - PlacerOpts->place_freq = PLACE_ONCE; - } - - PlacerOpts->doPlacement = FALSE; /* DEFAULT */ - if (Options.Count[OT_PLACE]) { - PlacerOpts->doPlacement = TRUE; - } else if (!Options.Count[OT_PACK] && !Options.Count[OT_PLACE] - && !Options.Count[OT_ROUTE]) { - if (!Options.Count[OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY]) - PlacerOpts->doPlacement = TRUE; - } - if (PlacerOpts->doPlacement == FALSE) { - PlacerOpts->place_freq = PLACE_NEVER; - } - -} - -static void SetupOperation(INP t_options Options, - OUTP enum e_operation *Operation) { - *Operation = RUN_FLOW; /* DEFAULT */ - if (Options.Count[OT_TIMING_ANALYZE_ONLY_WITH_NET_DELAY]) { - *Operation = TIMING_ANALYSIS_ONLY; - } -} - -static void SetupPowerOpts(t_options Options, t_power_opts *power_opts, - t_arch * Arch) { - - if (Options.Count[OT_POWER]) { - power_opts->do_power = TRUE; - } else { - power_opts->do_power = FALSE; - } - - if (power_opts->do_power) { - Arch->power = (t_power_arch*) my_malloc(sizeof(t_power_arch)); - Arch->clocks = (t_clock_arch*) my_malloc(sizeof(t_clock_arch)); - g_clock_arch = Arch->clocks; - } else { - Arch->power = NULL; - Arch->clocks = NULL; - g_clock_arch = NULL; - } - -} - -/* Setup the SPICE Options:*/ -static void SetupSpiceOpts(t_options Options, - t_spice_opts* spice_opts, - t_arch* arch) { - /* Initialize */ - spice_opts->do_spice = FALSE; - spice_opts->fpga_spice_print_top_testbench = FALSE; - spice_opts->fpga_spice_print_pb_mux_testbench = FALSE; - spice_opts->fpga_spice_print_cb_mux_testbench = FALSE; - spice_opts->fpga_spice_print_sb_mux_testbench = FALSE; - spice_opts->fpga_spice_print_cb_testbench = FALSE; - spice_opts->fpga_spice_print_sb_testbench = FALSE; - spice_opts->fpga_spice_print_lut_testbench = FALSE; - spice_opts->fpga_spice_print_hardlogic_testbench = FALSE; - spice_opts->fpga_spice_print_io_testbench = FALSE; - spice_opts->fpga_spice_print_grid_testbench = FALSE; - spice_opts->fpga_spice_leakage_only = FALSE; - spice_opts->fpga_spice_parasitic_net_estimation = TRUE; - spice_opts->fpga_spice_testbench_load_extraction = TRUE; - - /* Turn on the spice option if it is selected*/ - if (Options.Count[OT_FPGA_SPICE]) { - spice_opts->do_spice = TRUE; - spice_opts->spice_dir = my_strdup(Options.spice_dir); - /* TODO: this could be more flexible*/ - spice_opts->include_dir = "include/"; - spice_opts->subckt_dir = "subckt/"; - if (Options.Count[OT_FPGA_SPICE_PRINT_TOP_TESTBENCH]) { - spice_opts->fpga_spice_print_top_testbench = TRUE; - } - if (Options.Count[OT_FPGA_SPICE_PRINT_PB_MUX_TESTBENCH]) { - spice_opts->fpga_spice_print_pb_mux_testbench = TRUE; - } - if (Options.Count[OT_FPGA_SPICE_PRINT_CB_MUX_TESTBENCH]) { - spice_opts->fpga_spice_print_cb_mux_testbench = TRUE; - } - if (Options.Count[OT_FPGA_SPICE_PRINT_SB_MUX_TESTBENCH]) { - spice_opts->fpga_spice_print_sb_mux_testbench = TRUE; - } - if (Options.Count[OT_FPGA_SPICE_PRINT_CB_TESTBENCH]) { - spice_opts->fpga_spice_print_cb_testbench = TRUE; - } - if (Options.Count[OT_FPGA_SPICE_PRINT_SB_TESTBENCH]) { - spice_opts->fpga_spice_print_sb_testbench = TRUE; - } - if (Options.Count[OT_FPGA_SPICE_PRINT_GRID_TESTBENCH]) { - spice_opts->fpga_spice_print_grid_testbench = TRUE; - } - if (Options.Count[OT_FPGA_SPICE_PRINT_LUT_TESTBENCH]) { - spice_opts->fpga_spice_print_lut_testbench = TRUE; - } - if (Options.Count[OT_FPGA_SPICE_PRINT_HARDLOGIC_TESTBENCH]) { - spice_opts->fpga_spice_print_hardlogic_testbench = TRUE; - } - if (Options.Count[OT_FPGA_SPICE_PRINT_IO_TESTBENCH]) { - spice_opts->fpga_spice_print_io_testbench = TRUE; - } - if (Options.Count[OT_FPGA_SPICE_LEAKAGE_ONLY]) { - spice_opts->fpga_spice_leakage_only = TRUE; - } - if (Options.Count[OT_FPGA_SPICE_PARASITIC_NET_ESTIMATION]) { - spice_opts->fpga_spice_parasitic_net_estimation = Options.fpga_spice_parasitic_net_estimation; - } - if (Options.Count[OT_FPGA_SPICE_TESTBENCH_LOAD_EXTRACTION]) { - spice_opts->fpga_spice_testbench_load_extraction = Options.fpga_spice_testbench_load_extraction; - } - } - /* Set default options */ - if ((TRUE == spice_opts->do_spice) - &&(FALSE == spice_opts->fpga_spice_print_top_testbench) - &&(FALSE == spice_opts->fpga_spice_print_grid_testbench) - &&(FALSE == spice_opts->fpga_spice_print_pb_mux_testbench) - &&(FALSE == spice_opts->fpga_spice_print_cb_mux_testbench) - &&(FALSE == spice_opts->fpga_spice_print_sb_mux_testbench) - &&(FALSE == spice_opts->fpga_spice_print_cb_testbench) - &&(FALSE == spice_opts->fpga_spice_print_sb_testbench) - &&(FALSE == spice_opts->fpga_spice_print_lut_testbench) - &&(FALSE == spice_opts->fpga_spice_print_hardlogic_testbench)) { - spice_opts->fpga_spice_print_pb_mux_testbench = TRUE; - spice_opts->fpga_spice_print_cb_mux_testbench = TRUE; - spice_opts->fpga_spice_print_sb_mux_testbench = TRUE; - spice_opts->fpga_spice_print_lut_testbench = TRUE; - spice_opts->fpga_spice_print_hardlogic_testbench = TRUE; - } - - /* Assign the number of mt in SPICE simulation */ - spice_opts->fpga_spice_sim_multi_thread_num = 8; - if (Options.Count[OT_FPGA_SPICE_SIM_MT_NUM]) { - spice_opts->fpga_spice_sim_multi_thread_num = Options.fpga_spice_sim_mt_num; - } - - /* Assign path of SPICE simulator */ - spice_opts->simulator_path = NULL; - if (Options.Count[OT_FPGA_SPICE_SIMULATOR_PATH]) { - spice_opts->simulator_path = my_strdup(Options.fpga_spice_simulator_path); - } - - /* If spice option is selected*/ - arch->read_xml_spice = spice_opts->do_spice; - arch->spice = (t_spice*)my_malloc(sizeof(t_spice)); - - return; -} - -/*Xifan TANG: Synthesizable Verilog Dumping */ -static void SetupSynVerilogOpts(t_options Options, - t_syn_verilog_opts* syn_verilog_opts, - t_arch* arch) { - - /* Initialize */ - syn_verilog_opts->dump_syn_verilog = FALSE; - syn_verilog_opts->syn_verilog_dump_dir = NULL; - syn_verilog_opts->dump_explicit_verilog = FALSE; - syn_verilog_opts->print_top_testbench = FALSE; - syn_verilog_opts->print_autocheck_top_testbench = FALSE; - syn_verilog_opts->reference_verilog_benchmark_file = NULL; - syn_verilog_opts->print_input_blif_testbench = FALSE; - syn_verilog_opts->include_timing = FALSE; - syn_verilog_opts->include_signal_init = FALSE; - syn_verilog_opts->print_modelsim_autodeck = FALSE; - syn_verilog_opts->print_formal_verification_top_netlist= FALSE; - syn_verilog_opts->modelsim_ini_path = NULL; - syn_verilog_opts->print_user_defined_template = FALSE; - syn_verilog_opts->print_report_timing_tcl = FALSE; - syn_verilog_opts->print_sdc_pnr = FALSE; - syn_verilog_opts->print_sdc_analysis = FALSE; - syn_verilog_opts->include_icarus_simulator = FALSE; - syn_verilog_opts->print_simulation_ini = FALSE; - syn_verilog_opts->simulation_ini_path = NULL; - - /* Turn on Syn_verilog options */ - if (Options.Count[OT_FPGA_VERILOG_SYN]) { - syn_verilog_opts->dump_syn_verilog = TRUE; - } else { - return; - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_DIR]) { - syn_verilog_opts->syn_verilog_dump_dir = my_strdup(Options.fpga_syn_verilog_dir); - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING]) { - syn_verilog_opts->dump_explicit_verilog = TRUE; - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH]) { - syn_verilog_opts->print_top_testbench = TRUE; - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH]) { - syn_verilog_opts->print_autocheck_top_testbench = TRUE; - syn_verilog_opts->reference_verilog_benchmark_file = my_strdup(Options.fpga_verilog_reference_benchmark_file); - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH]) { - syn_verilog_opts->print_input_blif_testbench = TRUE; - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_FORMAL_VERIFICATION_TOP_NETLIST]) { - syn_verilog_opts->print_formal_verification_top_netlist = TRUE; - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_INCLUDE_TIMING]) { - syn_verilog_opts->include_timing = TRUE; - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_INCLUDE_SIGNAL_INIT]) { - syn_verilog_opts->include_signal_init = TRUE; - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_INCLUDE_ICARUS_SIMULATOR]) { - syn_verilog_opts->include_icarus_simulator = TRUE; - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_MODELSIM_AUTODECK]) { - syn_verilog_opts->print_modelsim_autodeck = TRUE; - syn_verilog_opts->modelsim_ini_path = my_strdup(Options.fpga_verilog_modelsim_ini_path); - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_USER_DEFINED_TEMPLATE]) { - syn_verilog_opts->print_user_defined_template = TRUE; - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_REPORT_TIMING_TCL]) { - syn_verilog_opts->print_report_timing_tcl = TRUE; - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_REPORT_TIMING_RPT_PATH]) { - syn_verilog_opts->report_timing_path = my_strdup(Options.fpga_verilog_report_timing_path); - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_SDC_PNR]) { - syn_verilog_opts->print_sdc_pnr = TRUE; - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS]) { - syn_verilog_opts->print_sdc_analysis = TRUE; - } - - if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_SIMULATION_INI]) { - syn_verilog_opts->print_simulation_ini = TRUE; - - if (Options.Count[OT_FPGA_VERILOG_SYN_SIMULATION_INI_FILE]) { - syn_verilog_opts->simulation_ini_path = my_strdup(Options.fpga_verilog_simulation_ini_path); - } - } - - /* SynVerilog needs the input from spice modeling */ - if (FALSE == arch->read_xml_spice) { - arch->read_xml_spice = syn_verilog_opts->dump_syn_verilog; - arch->spice = (t_spice*)my_calloc(1, sizeof(t_spice)); - } - - return; -} - -/*Xifan TANG: Bitstream Generator */ -static void SetupBitstreamGenOpts(t_options Options, - t_bitstream_gen_opts* bitstream_gen_opts, - t_arch* arch) { - - /* Initialize */ - bitstream_gen_opts->gen_bitstream = FALSE; - bitstream_gen_opts->bitstream_output_file = NULL; - - /* Turn on Bitstream Generator options */ - if (Options.Count[OT_FPGA_BITSTREAM_GENERATOR]) { - bitstream_gen_opts->gen_bitstream = TRUE; - } else { - return; - } - - if (Options.Count[OT_FPGA_BITSTREAM_OUTPUT_FILE]) { - bitstream_gen_opts->bitstream_output_file = my_strdup(Options.fpga_bitstream_file); - } - - /* SynVerilog needs the input from spice modeling */ - if (FALSE == arch->read_xml_spice) { - arch->read_xml_spice = bitstream_gen_opts->gen_bitstream; - arch->spice = (t_spice*)my_malloc(sizeof(t_spice)); - } - - return; -} - -static void SetupFpgaSpiceOpts(t_options Options, - t_fpga_spice_opts* fpga_spice_opts, - t_arch* Arch) { - /* Xifan TANG: SPICE Support*/ - SetupSpiceOpts(Options, &(fpga_spice_opts->SpiceOpts), Arch); - - /* Xifan TANG: Synthesizable Verilog Dumping*/ - SetupSynVerilogOpts(Options, &(fpga_spice_opts->SynVerilogOpts), Arch); - - /* Xifan TANG: Bitstream generator */ - SetupBitstreamGenOpts(Options, &(fpga_spice_opts->BitstreamGenOpts), Arch); - - /* Decide if we need to rename illegal port names */ - fpga_spice_opts->rename_illegal_port = FALSE; - if (Options.Count[OT_FPGA_X2P_RENAME_ILLEGAL_PORT]) { - fpga_spice_opts->rename_illegal_port = TRUE; - } - - /* Assign the weight of signal density */ - fpga_spice_opts->signal_density_weight = 1.; - if (Options.Count[OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT]) { - fpga_spice_opts->signal_density_weight = Options.fpga_spice_signal_density_weight; - } - - /* Assign the weight of signal density */ - fpga_spice_opts->sim_window_size = 0.5; - if (Options.Count[OT_FPGA_X2P_SIM_WINDOW_SIZE]) { - fpga_spice_opts->sim_window_size = Options.fpga_spice_sim_window_size; - } - - /* Check if user wants to use a compact routing hierarchy */ - fpga_spice_opts->compact_routing_hierarchy = FALSE; - if (Options.Count[OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY]) { - fpga_spice_opts->compact_routing_hierarchy = TRUE; - } - - /* Check if user wants to use a compact routing hierarchy */ - fpga_spice_opts->output_sb_xml = FALSE; - fpga_spice_opts->sb_xml_dir = NULL; - if (Options.Count[OT_FPGA_X2P_OUTPUT_SB_XML]) { - fpga_spice_opts->output_sb_xml = TRUE; - fpga_spice_opts->sb_xml_dir = Options.sb_xml_dir; - } - - /* Check if user wants to duplicate the pin at each side of grids */ - fpga_spice_opts->duplicate_grid_pin = FALSE; - if (Options.Count[OT_FPGA_X2P_DUPLICATE_GRID_PIN]) { - fpga_spice_opts->duplicate_grid_pin = TRUE; - } - - /* Decide if we need to do FPGA-SPICE */ - fpga_spice_opts->do_fpga_spice = FALSE; - if (( TRUE == fpga_spice_opts->SpiceOpts.do_spice) - ||(TRUE == fpga_spice_opts->SynVerilogOpts.dump_syn_verilog) - ||(TRUE == fpga_spice_opts->BitstreamGenOpts.gen_bitstream)) { - fpga_spice_opts->do_fpga_spice = TRUE; - } - - /* Decide if we need to read activity file */ - fpga_spice_opts->read_act_file = FALSE; - if (( TRUE == fpga_spice_opts->SpiceOpts.do_spice) - ||(TRUE == fpga_spice_opts->SynVerilogOpts.dump_syn_verilog)) { - fpga_spice_opts->read_act_file = TRUE; - } - - return; -} - -/* Initialize the global variables for clb to clb directs */ -void alloc_and_init_globals_clb_to_clb_directs(int num_directs, - t_direct_inf* directs) { - num_clb2clb_directs = num_directs; - clb2clb_direct = alloc_and_load_clb_to_clb_directs(directs, num_directs); - - return; -} - -/* mrFPGA : Reshaped by Xifan TANG */ -static void set_max_pins_per_side() { - int i, j, p, q; - max_pins_per_side = 0; - - for (p = 0; p < num_types; ++p) { - for (q = 0; q < type_descriptors[p].height; ++q) { - /* Xifan TANG: Skip NULL pointor*/ - if (EMPTY_TYPE == &(type_descriptors[p])) { - continue; - } - for (i = 0; i <= 3; i++) { - int sum = 0; - for (j = 0; j < type_descriptors[p].num_pins; j++) { - if (1 == type_descriptors[p].pinloc[q][i][j]) { - type_descriptors[p].pin_index_per_side[j] = sum; - type_descriptors[p].pin_ptc_to_side[j] = i; - sum++; - } - } - if (IO_TYPE != &(type_descriptors[p])) { - max_pins_per_side = std::max(sum, max_pins_per_side); - } - } - } - } - return; -} - -static void setup_junction_switch(struct s_det_routing_arch *det_routing_arch) { - int i; - if (is_wire_buffer) { - wire_buffer_inf.R += memristor_inf.R; - } - for (i = 0; i < num_normal_switch; i++) { - if ( switch_inf[i].buffered ) { - switch_inf[i].R += memristor_inf.R; - } else { - switch_inf[i].R += 2.0 * memristor_inf.R; - } - switch_inf[i].Tdel += memristor_inf.R * (0.5 * memristor_inf.C + switch_inf[i].Cin); - switch_inf[i].Tdel += 2.0 * memristor_inf.Tdel; - } - switch_inf[det_routing_arch->wire_to_ipin_switch].Tdel += memristor_inf.R * (0.5 * memristor_inf.C + switch_inf[i].Cin) + memristor_inf.Tdel; - if ( is_mrFPGA ) { - switch_inf[det_routing_arch->opin_to_wire_switch].R += memristor_inf.R; - switch_inf[det_routing_arch->opin_to_wire_switch].Tdel += memristor_inf.Tdel; - } -} - -static void add_wire_to_switch(struct s_det_routing_arch *det_routing_arch) { - int i; - for (i = 0; i < num_normal_switch; i++) { - switch_inf[i].Tdel += switch_inf[i].R * Cseg_global + 0.5 * Rseg_global * Cseg_global; - switch_inf[i].R += Rseg_global; - } -} - -static void hack_switch_to_rram(struct s_det_routing_arch *det_routing_arch) { - int i; - if(rram_pass_tran_value > 0.01) { - for (i = 0; i < num_normal_switch; i++) { - if(switch_inf[i].buffered) { - switch_inf[i].R = switch_inf[i].R / 2. + rram_pass_tran_value; - } else { - switch_inf[i].R = rram_pass_tran_value; - } - } - } -} - -/* end */ - diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.h b/vpr7_x2p/vpr/SRC/base/SetupVPR.h deleted file mode 100644 index 9ed3c23eb..000000000 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef SETUPVPR_H -#define SETUPVPR_H - - -void VPRSetupArch(t_arch* arch, - t_det_routing_arch* RoutingArch, - t_segment_inf ** Segments, - t_swseg_pattern_inf** swseg_patterns, - t_model** user_models, - t_model** library_models); - -void alloc_and_init_globals_clb_to_clb_directs(int num_directs, - t_direct_inf* directs); - -void SetupVPR(INP t_options *Options, - INP boolean TimingEnabled, - INP boolean readArchFile, - OUTP struct s_file_name_opts *FileNameOpts, - INOUTP t_arch * Arch, - OUTP enum e_operation *Operation, - OUTP t_model ** user_models, - OUTP t_model ** library_models, - OUTP struct s_packer_opts *PackerOpts, - OUTP struct s_placer_opts *PlacerOpts, - OUTP struct s_annealing_sched *AnnealSched, - OUTP struct s_router_opts *RouterOpts, - OUTP struct s_det_routing_arch *RoutingArch, - OUTP t_segment_inf ** Segments, - OUTP t_timing_inf * Timing, - OUTP boolean * ShowGraphics, - OUTP int *GraphPause, - OUTP t_power_opts * power_opts, - /*Xifan TANG: Switch Segment Pattern Support*/ - OUTP t_swseg_pattern_inf** swseg_patterns, - /* Xifan TANG: FPGA-SPICE Support*/ - OUTP t_fpga_spice_opts* fpga_spice_opts); - -void CheckSetup(INP enum e_operation Operation, - INP struct s_placer_opts PlacerOpts, - INP struct s_annealing_sched AnnealSched, - INP struct s_router_opts RouterOpts, - INP struct s_det_routing_arch RoutingArch, - INP t_segment_inf * Segments, - INP t_timing_inf Timing, - INP t_chan_width_dist Chans); - -void CheckArch(INP t_arch Arch, - INP boolean TimingEnabled); - -void CheckOptions(INP t_options Options, - INP boolean TimingEnabled); - -void ShowSetup(INP t_options options, INP t_vpr_setup vpr_setup); -void printClusteredNetlistStats(void); - -#endif - diff --git a/vpr7_x2p/vpr/SRC/base/ShowSetup.c b/vpr7_x2p/vpr/SRC/base/ShowSetup.c deleted file mode 100644 index 6980c1dc3..000000000 --- a/vpr7_x2p/vpr/SRC/base/ShowSetup.c +++ /dev/null @@ -1,403 +0,0 @@ -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "OptionTokens.h" -#include "ReadOptions.h" -#include "read_xml_arch_file.h" -#include "SetupVPR.h" - -/******** Function Prototypes ********/ -static void ShowPackerOpts(INP struct s_packer_opts PackerOpts); -static void ShowPlacerOpts(INP t_options Options, - INP struct s_placer_opts PlacerOpts, - INP struct s_annealing_sched AnnealSched); -static void ShowOperation(INP enum e_operation Operation); -static void ShowRouterOpts(INP struct s_router_opts RouterOpts); -static void ShowAnnealSched(INP struct s_annealing_sched AnnealSched); -static void ShowRoutingArch(INP struct s_det_routing_arch RoutingArch); - -/******** Function Implementations ********/ - -void ShowSetup(INP t_options options, INP t_vpr_setup vpr_setup) { - vpr_printf(TIO_MESSAGE_INFO, "Timing analysis: %s\n", (vpr_setup.TimingEnabled? "ON" : "OFF")); - - vpr_printf(TIO_MESSAGE_INFO, "Circuit netlist file: %s\n", vpr_setup.FileNameOpts.NetFile); - vpr_printf(TIO_MESSAGE_INFO, "Circuit placement file: %s\n", vpr_setup.FileNameOpts.PlaceFile); - vpr_printf(TIO_MESSAGE_INFO, "Circuit routing file: %s\n", vpr_setup.FileNameOpts.RouteFile); - vpr_printf(TIO_MESSAGE_INFO, "Circuit SDC file: %s\n", vpr_setup.Timing.SDCFile); - - ShowOperation(vpr_setup.Operation); - vpr_printf(TIO_MESSAGE_INFO, "Packer: %s\n", (vpr_setup.PackerOpts.doPacking ? "ENABLED" : "DISABLED")); - vpr_printf(TIO_MESSAGE_INFO, "Placer: %s\n", (vpr_setup.PlacerOpts.doPlacement ? "ENABLED" : "DISABLED")); - vpr_printf(TIO_MESSAGE_INFO, "Router: %s\n", (vpr_setup.RouterOpts.doRouting ? "ENABLED" : "DISABLED")); - - if (vpr_setup.PackerOpts.doPacking) { - ShowPackerOpts(vpr_setup.PackerOpts); - } - if (vpr_setup.PlacerOpts.doPlacement) { - ShowPlacerOpts(options, vpr_setup.PlacerOpts, vpr_setup.AnnealSched); - } - if (vpr_setup.RouterOpts.doRouting) { - ShowRouterOpts(vpr_setup.RouterOpts); - } - - if (DETAILED == vpr_setup.RouterOpts.route_type) - ShowRoutingArch(vpr_setup.RoutingArch); - -} - -void printClusteredNetlistStats() { - int i, j, L_num_p_inputs, L_num_p_outputs; - int *num_blocks_type; - num_blocks_type = (int*) my_calloc(num_types, sizeof(int)); - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Netlist num_nets: %d\n", num_nets); - vpr_printf(TIO_MESSAGE_INFO, "Netlist num_blocks: %d\n", num_blocks); - - for (i = 0; i < num_types; i++) { - num_blocks_type[i] = 0; - } - /* Count I/O input and output pads */ - L_num_p_inputs = 0; - L_num_p_outputs = 0; - - for (i = 0; i < num_blocks; i++) { - num_blocks_type[block[i].type->index]++; - if (block[i].type == IO_TYPE) { - for (j = 0; j < IO_TYPE->num_pins; j++) { - if (block[i].nets[j] != OPEN) { - if (IO_TYPE->class_inf[IO_TYPE->pin_class[j]].type - == DRIVER) { - L_num_p_inputs++; - } else { - assert( - IO_TYPE-> class_inf[IO_TYPE-> pin_class[j]]. type == RECEIVER); - L_num_p_outputs++; - } - } - } - } - } - - for (i = 0; i < num_types; i++) { - if (IO_TYPE != &type_descriptors[i]) { - vpr_printf(TIO_MESSAGE_INFO, "Netlist %s blocks: %d.\n", type_descriptors[i].name, num_blocks_type[i]); - } - } - - /* Print out each block separately instead */ - vpr_printf(TIO_MESSAGE_INFO, "Netlist inputs pins: %d\n", L_num_p_inputs); - vpr_printf(TIO_MESSAGE_INFO, "Netlist output pins: %d\n", L_num_p_outputs); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - free(num_blocks_type); -} - -static void ShowRoutingArch(INP struct s_det_routing_arch RoutingArch) { - - vpr_printf(TIO_MESSAGE_INFO, "RoutingArch.directionality: "); - switch (RoutingArch.directionality) { - case BI_DIRECTIONAL: - vpr_printf(TIO_MESSAGE_INFO, "BI_DIRECTIONAL\n"); - break; - case UNI_DIRECTIONAL: - vpr_printf(TIO_MESSAGE_INFO, "UNI_DIRECTIONAL\n"); - break; - default: - vpr_printf(TIO_MESSAGE_INFO, "\n"); - exit(1); - } - - vpr_printf(TIO_MESSAGE_INFO, "RoutingArch.switch_block_type: "); - switch (RoutingArch.switch_block_type) { - case SUBSET: - vpr_printf(TIO_MESSAGE_INFO, "SUBSET\n"); - break; - case WILTON: - vpr_printf(TIO_MESSAGE_INFO, "WILTON\n"); - break; - case UNIVERSAL: - vpr_printf(TIO_MESSAGE_INFO, "UNIVERSAL\n"); - break; - case FULL: - vpr_printf(TIO_MESSAGE_INFO, "FULL\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "switch block type\n"); - } - - vpr_printf(TIO_MESSAGE_INFO, "RoutingArch.Fs: %d\n", RoutingArch.Fs); - - vpr_printf(TIO_MESSAGE_INFO, "\n"); -} - -static void ShowAnnealSched(INP struct s_annealing_sched AnnealSched) { - - vpr_printf(TIO_MESSAGE_INFO, "AnnealSched.type: "); - switch (AnnealSched.type) { - case AUTO_SCHED: - vpr_printf(TIO_MESSAGE_INFO, "AUTO_SCHED\n"); - break; - case USER_SCHED: - vpr_printf(TIO_MESSAGE_INFO, "USER_SCHED\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "Unknown annealing schedule\n"); - } - - vpr_printf(TIO_MESSAGE_INFO, "AnnealSched.inner_num: %f\n", AnnealSched.inner_num); - - if (USER_SCHED == AnnealSched.type) { - vpr_printf(TIO_MESSAGE_INFO, "AnnealSched.init_t: %f\n", AnnealSched.init_t); - vpr_printf(TIO_MESSAGE_INFO, "AnnealSched.alpha_t: %f\n", AnnealSched.alpha_t); - vpr_printf(TIO_MESSAGE_INFO, "AnnealSched.exit_t: %f\n", AnnealSched.exit_t); - } -} - -static void ShowRouterOpts(INP struct s_router_opts RouterOpts) { - - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.route_type: "); - switch (RouterOpts.route_type) { - case GLOBAL: - vpr_printf(TIO_MESSAGE_INFO, "GLOBAL\n"); - break; - case DETAILED: - vpr_printf(TIO_MESSAGE_INFO, "DETAILED\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "Unknown router opt\n"); - } - - if (DETAILED == RouterOpts.route_type) { - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.router_algorithm: "); - switch (RouterOpts.router_algorithm) { - case BREADTH_FIRST: - vpr_printf(TIO_MESSAGE_INFO, "BREADTH_FIRST\n"); - break; - case TIMING_DRIVEN: - vpr_printf(TIO_MESSAGE_INFO, "TIMING_DRIVEN\n"); - break; - case NO_TIMING: - vpr_printf(TIO_MESSAGE_INFO, "NO_TIMING\n"); - break; - default: - vpr_printf(TIO_MESSAGE_INFO, "\n"); - exit(1); - } - - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.base_cost_type: "); - switch (RouterOpts.base_cost_type) { - case INTRINSIC_DELAY: - vpr_printf(TIO_MESSAGE_INFO, "INTRINSIC_DELAY\n"); - break; - case DELAY_NORMALIZED: - vpr_printf(TIO_MESSAGE_INFO, "DELAY_NORMALIZED\n"); - break; - case DEMAND_ONLY: - vpr_printf(TIO_MESSAGE_INFO, "DEMAND_ONLY\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "Unknown base_cost_type\n"); - } - - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.fixed_channel_width: "); - if (NO_FIXED_CHANNEL_WIDTH == RouterOpts.fixed_channel_width) { - vpr_printf(TIO_MESSAGE_INFO, "NO_FIXED_CHANNEL_WIDTH\n"); - } else { - vpr_printf(TIO_MESSAGE_INFO, "%d\n", RouterOpts.fixed_channel_width); - } - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.use_tileable_route_chan_width: %s\n", RouterOpts.use_tileable_route_chan_width ? "TRUE\n" : "FALSE\n"); - - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.acc_fac: %f\n", RouterOpts.acc_fac); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.bb_factor: %d\n", RouterOpts.bb_factor); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.bend_cost: %f\n", RouterOpts.bend_cost); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.first_iter_pres_fac: %f\n", RouterOpts.first_iter_pres_fac); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.initial_pres_fac: %f\n", RouterOpts.initial_pres_fac); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.pres_fac_mult: %f\n", RouterOpts.pres_fac_mult); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.max_router_iterations: %d\n", RouterOpts.max_router_iterations); - - if (TIMING_DRIVEN == RouterOpts.router_algorithm) { - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.astar_fac: %f\n", RouterOpts.astar_fac); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.criticality_exp: %f\n", RouterOpts.criticality_exp); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.max_criticality: %f\n", RouterOpts.max_criticality); - } - } else { - assert(GLOBAL == RouterOpts.route_type); - - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.router_algorithm: "); - switch (RouterOpts.router_algorithm) { - case BREADTH_FIRST: - vpr_printf(TIO_MESSAGE_INFO, "BREADTH_FIRST\n"); - break; - case TIMING_DRIVEN: - vpr_printf(TIO_MESSAGE_INFO, "TIMING_DRIVEN\n"); - break; - case NO_TIMING: - vpr_printf(TIO_MESSAGE_INFO, "NO_TIMING\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "Unknown router algorithm\n"); - } - - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.base_cost_type: "); - switch (RouterOpts.base_cost_type) { - case INTRINSIC_DELAY: - vpr_printf(TIO_MESSAGE_INFO, "INTRINSIC_DELAY\n"); - break; - case DELAY_NORMALIZED: - vpr_printf(TIO_MESSAGE_INFO, "DELAY_NORMALIZED\n"); - break; - case DEMAND_ONLY: - vpr_printf(TIO_MESSAGE_INFO, "DEMAND_ONLY\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "Unknown router base cost type\n"); - } - - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.fixed_channel_width: "); - if (NO_FIXED_CHANNEL_WIDTH == RouterOpts.fixed_channel_width) { - vpr_printf(TIO_MESSAGE_INFO, "NO_FIXED_CHANNEL_WIDTH\n"); - } else { - vpr_printf(TIO_MESSAGE_INFO, "%d\n", RouterOpts.fixed_channel_width); - } - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.use_tileable_route_chan_width: ", RouterOpts.use_tileable_route_chan_width ? "TRUE\n" : "FALSE\n"); - - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.acc_fac: %f\n", RouterOpts.acc_fac); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.bb_factor: %d\n", RouterOpts.bb_factor); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.bend_cost: %f\n", RouterOpts.bend_cost); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.first_iter_pres_fac: %f\n", RouterOpts.first_iter_pres_fac); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.initial_pres_fac: %f\n", RouterOpts.initial_pres_fac); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.pres_fac_mult: %f\n", RouterOpts.pres_fac_mult); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.max_router_iterations: %d\n", RouterOpts.max_router_iterations); - if (TIMING_DRIVEN == RouterOpts.router_algorithm) { - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.astar_fac: %f\n", RouterOpts.astar_fac); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.criticality_exp: %f\n", RouterOpts.criticality_exp); - vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.max_criticality: %f\n", RouterOpts.max_criticality); - } - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); -} - -static void ShowOperation(INP enum e_operation Operation) { - vpr_printf(TIO_MESSAGE_INFO, "Operation: "); - switch (Operation) { - case RUN_FLOW: - vpr_printf(TIO_MESSAGE_INFO, "RUN_FLOW\n"); - break; - case TIMING_ANALYSIS_ONLY: - vpr_printf(TIO_MESSAGE_INFO, "TIMING_ANALYSIS_ONLY\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "Unknown VPR operation\n"); - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); -} - -static void ShowPlacerOpts(INP t_options Options, - INP struct s_placer_opts PlacerOpts, - INP struct s_annealing_sched AnnealSched) { - - vpr_printf(TIO_MESSAGE_INFO, "PlacerOpts.place_freq: "); - switch (PlacerOpts.place_freq) { - case PLACE_ONCE: - vpr_printf(TIO_MESSAGE_INFO, "PLACE_ONCE\n"); - break; - case PLACE_ALWAYS: - vpr_printf(TIO_MESSAGE_INFO, "PLACE_ALWAYS\n"); - break; - case PLACE_NEVER: - vpr_printf(TIO_MESSAGE_INFO, "PLACE_NEVER\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "Unknown Place Freq\n"); - } - if ((PLACE_ONCE == PlacerOpts.place_freq) - || (PLACE_ALWAYS == PlacerOpts.place_freq)) { - - vpr_printf(TIO_MESSAGE_INFO, "PlacerOpts.place_algorithm: "); - switch (PlacerOpts.place_algorithm) { - case BOUNDING_BOX_PLACE: - vpr_printf(TIO_MESSAGE_INFO, "BOUNDING_BOX_PLACE\n"); - break; - case NET_TIMING_DRIVEN_PLACE: - vpr_printf(TIO_MESSAGE_INFO, "NET_TIMING_DRIVEN_PLACE\n"); - break; - case PATH_TIMING_DRIVEN_PLACE: - vpr_printf(TIO_MESSAGE_INFO, "PATH_TIMING_DRIVEN_PLACE\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "Unknown placement algorithm\n"); - } - - vpr_printf(TIO_MESSAGE_INFO, "PlacerOpts.pad_loc_type: "); - switch (PlacerOpts.pad_loc_type) { - case FREE: - vpr_printf(TIO_MESSAGE_INFO, "FREE\n"); - break; - case RANDOM: - vpr_printf(TIO_MESSAGE_INFO, "RANDOM\n"); - break; - case USER: - vpr_printf(TIO_MESSAGE_INFO, "USER '%s'\n", PlacerOpts.pad_loc_file); - break; - default: - vpr_printf(TIO_MESSAGE_INFO, "Unknown I/O pad location type\n"); - exit(1); - } - - vpr_printf(TIO_MESSAGE_INFO, "PlacerOpts.place_cost_exp: %f\n", PlacerOpts.place_cost_exp); - - if (Options.Count[OT_PLACE_CHAN_WIDTH]) { - vpr_printf(TIO_MESSAGE_INFO, "PlacerOpts.place_chan_width: %d\n", PlacerOpts.place_chan_width); - } - - if ((NET_TIMING_DRIVEN_PLACE == PlacerOpts.place_algorithm) - || (PATH_TIMING_DRIVEN_PLACE == PlacerOpts.place_algorithm)) { - vpr_printf(TIO_MESSAGE_INFO, "PlacerOpts.inner_loop_recompute_divider: %d\n", PlacerOpts.inner_loop_recompute_divider); - vpr_printf(TIO_MESSAGE_INFO, "PlacerOpts.recompute_crit_iter: %d\n", PlacerOpts.recompute_crit_iter); - vpr_printf(TIO_MESSAGE_INFO, "PlacerOpts.timing_tradeoff: %f\n", PlacerOpts.timing_tradeoff); - vpr_printf(TIO_MESSAGE_INFO, "PlacerOpts.td_place_exp_first: %f\n", PlacerOpts.td_place_exp_first); - vpr_printf(TIO_MESSAGE_INFO, "PlacerOpts.td_place_exp_last: %f\n", PlacerOpts.td_place_exp_last); - } - - vpr_printf(TIO_MESSAGE_INFO, "PlaceOpts.seed: %d\n", PlacerOpts.seed); - - ShowAnnealSched(AnnealSched); - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - -} - - -static void ShowPackerOpts(INP struct s_packer_opts PackerOpts) { - - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.allow_early_exit: %s", (PackerOpts.allow_early_exit ? "TRUE\n" : "FALSE\n")); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.allow_unrelated_clustering: %s", (PackerOpts.allow_unrelated_clustering ? "TRUE\n" : "FALSE\n")); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.alpha_clustering: %f\n", PackerOpts.alpha); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.aspect: %f\n", PackerOpts.aspect); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.beta_clustering: %f\n", PackerOpts.beta); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.block_delay: %f\n", PackerOpts.block_delay); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.cluster_seed_type: "); - switch (PackerOpts.cluster_seed_type) { - case VPACK_TIMING: - vpr_printf(TIO_MESSAGE_INFO, "TIMING\n"); - break; - case VPACK_MAX_INPUTS: - vpr_printf(TIO_MESSAGE_INFO, "MAX_INPUTS\n"); - break; - default: - vpr_printf(TIO_MESSAGE_INFO, "Unknown packer cluster_seed_type\n"); - exit(1); - } - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.connection_driven: %s", (PackerOpts.connection_driven ? "TRUE\n" : "FALSE\n")); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.global_clocks: %s", (PackerOpts.global_clocks ? "TRUE\n" : "FALSE\n")); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.hill_climbing_flag: %s", (PackerOpts.hill_climbing_flag ? "TRUE\n" : "FALSE\n")); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.inter_cluster_net_delay: %f\n", PackerOpts.inter_cluster_net_delay); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.intra_cluster_net_delay: %f\n", PackerOpts.intra_cluster_net_delay); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.recompute_timing_after: %d\n", PackerOpts.recompute_timing_after); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.sweep_hanging_nets_and_inputs: %s", (PackerOpts.sweep_hanging_nets_and_inputs ? "TRUE\n" : "FALSE\n")); - vpr_printf(TIO_MESSAGE_INFO, "PackerOpts.timing_driven: %s", (PackerOpts.timing_driven ? "TRUE\n" : "FALSE\n")); - vpr_printf(TIO_MESSAGE_INFO, "\n"); -} - diff --git a/vpr7_x2p/vpr/SRC/base/check_netlist.c b/vpr7_x2p/vpr/SRC/base/check_netlist.c deleted file mode 100644 index 964da691a..000000000 --- a/vpr7_x2p/vpr/SRC/base/check_netlist.c +++ /dev/null @@ -1,320 +0,0 @@ -/* TODO: Consider deleting this file altogether. Many netlist checks now done during parsing. Also, the checks here are too strict. For example, we may actually want to allow mixing of local/global signals */ - -#include -#include - -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "hash.h" -#include "vpr_utils.h" -#include "check_netlist.h" -#include "assert.h" -#include "read_xml_arch_file.h" - -#define ERROR_THRESHOLD 100 - -/**************** Subroutines local to this module **************************/ - -static int check_connections_to_global_clb_pins(int inet); - -static int check_for_duplicated_names(void); - -static int check_clb_conn(int iblk, int num_conn); - -static int check_clb_internal_nets(int iblk); - -static int check_subblock_internal_nets(int iblk, int isub); - -static int get_num_conn(int bnum); - -static int check_subblocks(int iblk); - -static int check_primitives(int iblk, int isub); - -/*********************** Subroutine definitions *****************************/ - -void check_netlist() { - int i, error, num_conn; - struct s_hash **net_hash_table, *h_net_ptr; - - /* TODO: Remove the following the function calls after these functions have - been fleshed and are legitimately used in the code!!! They are called here so that - the compiler will not throw an error for an unused function */ - - int unused_var; - unused_var = check_subblock_internal_nets(0, 0); - unused_var = check_primitives(0, 0); - if (unused_var) - vpr_printf(TIO_MESSAGE_INFO, "Please go to the check_netlist() function in check_netlist.c and remove the first section as needed."); - - /* This routine checks that the netlist makes sense */ - - net_hash_table = alloc_hash_table(); - - error = 0; - - /* Check that nets fanout and have a driver. */ - for (i = 0; i < num_nets; i++) { - h_net_ptr = insert_in_hash_table(net_hash_table, clb_net[i].name, i); - if (h_net_ptr->count != 1) { - vpr_printf(TIO_MESSAGE_ERROR, "Net %s has multiple drivers.\n", clb_net[i].name); - error++; - } - error += check_connections_to_global_clb_pins(i); - if (error >= ERROR_THRESHOLD) { - vpr_printf(TIO_MESSAGE_ERROR, "Too many errors in netlist, exiting.\n"); - } - } - free_hash_table(net_hash_table); - - /* Check that each block makes sense. */ - for (i = 0; i < num_blocks; i++) { - num_conn = get_num_conn(i); - error += check_clb_conn(i, num_conn); - error += check_clb_internal_nets(i); - error += check_subblocks(i); - if (error >= ERROR_THRESHOLD) { - vpr_printf(TIO_MESSAGE_ERROR, "Too many errors in netlist, exiting.\n"); - exit(1); - } - } - - error += check_for_duplicated_names(); - - if (error != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "Found %d fatal Errors in the input netlist.\n", error); - exit(1); - } - - /* HACK: Jason Luu January 17, 2011 Do not route common constants gnd and vcc - Todo: Need to make architecture driven. - */ - for (i = 0; i < num_nets; i++) { - if (strcmp(clb_net[i].name, "vcc") == 0) { - clb_net[i].is_global = TRUE; - } else if (strcmp(clb_net[i].name, "gnd") == 0) { - clb_net[i].is_global = TRUE; - } - } -} - -static int check_connections_to_global_clb_pins(int inet) { - - /* Checks that a global net (inet) connects only to global CLB input pins * - * and that non-global nets never connects to a global CLB pin. Either * - * global or non-global nets are allowed to connect to pads. */ - - int ipin, num_pins, iblk, node_block_pin, error; - - num_pins = (clb_net[inet].num_sinks + 1); - error = 0; - - /* For now global signals can be driven by an I/O pad or any CLB output * - * although a CLB output generates a warning. I could make a global CLB * - * output pin type to allow people to make architectures that didn't have * - * this warning. */ - - for (ipin = 0; ipin < num_pins; ipin++) { - iblk = clb_net[inet].node_block[ipin]; - - node_block_pin = clb_net[inet].node_block_pin[ipin]; - - if (block[iblk].type->is_global_pin[node_block_pin] - != clb_net[inet].is_global && block[iblk].type != IO_TYPE) { - - /* Allow a CLB output pin to drive a global net (warning only). */ - - if (ipin == 0 && clb_net[inet].is_global) { - vpr_printf(TIO_MESSAGE_WARNING, "in check_connections_to_global_clb_pins:\n"); - vpr_printf(TIO_MESSAGE_WARNING, "\tnet #%d (%s) is driven by CLB output pin (#%d) on block #%d (%s).\n", - inet, clb_net[inet].name, node_block_pin, iblk, block[iblk].name); - } else { /* Otherwise -> Error */ - vpr_printf(TIO_MESSAGE_ERROR, "in check_connections_to_global_clb_pins:\n"); - vpr_printf(TIO_MESSAGE_ERROR, "\tpin %d on net #%d (%s) connects to CLB input pin (#%d) on block #%d (%s).\n", - ipin, inet, clb_net[inet].name, node_block_pin, iblk, block[iblk].name); - error++; - } - - if (clb_net[inet].is_global) - vpr_printf(TIO_MESSAGE_INFO, "Net is global, but CLB pin is not.\n"); - else - vpr_printf(TIO_MESSAGE_INFO, "CLB pin is global, but net is not.\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - } - } /* End for all pins */ - - return (error); -} - -static int check_clb_conn(int iblk, int num_conn) { - - /* Checks that the connections into and out of the clb make sense. */ - - int iclass, ipin, error; - t_type_ptr type; - - error = 0; - type = block[iblk].type; - - if (type == IO_TYPE) { - /* - //This triggers incorrectly if other blocks (e.g. I/O buffers) are included in the iopads - if (num_conn != 1) { - vpr_printf(TIO_MESSAGE_ERROR, "IO blk #%d (%s) has %d pins.\n", - iblk, block[iblk].name, num_conn); - error++; - } - */ - } else if (num_conn < 2) { - vpr_printf(TIO_MESSAGE_WARNING, "Logic block #%d (%s) has only %d pin.\n", - iblk, block[iblk].name, num_conn); - - /* Allow the case where we have only one OUTPUT pin connected to continue. * - * This is used sometimes as a constant generator for a primary output, * - * but I will still warn the user. If the only pin connected is an input, * - * abort. */ - - if (num_conn == 1) { - for (ipin = 0; ipin < type->num_pins; ipin++) { - if (block[iblk].nets[ipin] != OPEN) { - iclass = type->pin_class[ipin]; - - if (type->class_inf[iclass].type != DRIVER) { - vpr_printf(TIO_MESSAGE_INFO, "Pin is an input -- this whole block is hanging logic that should be swept in logic synthesis.\n"); - vpr_printf(TIO_MESSAGE_INFO, "\tNon-fatal, but check this.\n"); - } else { - vpr_printf(TIO_MESSAGE_INFO, "Pin is an output -- may be a constant generator.\n"); - vpr_printf(TIO_MESSAGE_INFO, "\tNon-fatal, but check this.\n"); - } - - break; - } - } - } - } - - /* This case should already have been flagged as an error -- this is * - * just a redundant double check. */ - - if (num_conn > type->num_pins) { - vpr_printf(TIO_MESSAGE_ERROR, "logic block #%d with output %s has %d pins.\n", - iblk, block[iblk].name, num_conn); - error++; - } - - return (error); -} - -static int check_clb_internal_nets(int iblk) { - /** TODO: - * Check if the internal CLB nets makes sense and are connected properly - * Consists of 3 main loops - * 1. a) Check name uniqueness - b) Check all net connections are to CLB pins or subblock pins and that they match the net examined - * 2. Check all connected CLB pins are connected to valid internal nets - * 3. Check all connected subblock pins are connected to valid internal nets and that these match the net indexes - */ - return 0; -} - -static int check_subblock_internal_nets(int iblk, int isub) { - /** - * TODO - * Check if the internal CLB nets makes sense and are connected properly - * Consists of 3 main checks - * 1. a) Check name uniqueness - b) Check all net connections are to CLB pins or subblock pins and that they match the net examined - * 2. Check all connected CLB pins are connected to valid internal nets - * 3. Check all connected subblock pins are connected to valid internal nets and that these match the net indexes - */ - return 0; -} - -static int check_subblocks(int iblk) { - /* TODO */ - /* This routine checks the subblocks of iblk (which must be a CLB). It * - * returns the number of errors found. */ - return 0; -} - -static int check_primitives(int iblk, int isub) { - - /* TODO: - This routine checks the subblocks of iblk (which must be a CLB). It * - * returns the number of errors found. */ - return 0; - -} - -static int check_for_duplicated_names(void) { -#if 0 - int iblk, isub, iprim, error; - int clb_count, sub_count, prim_count; - struct s_hash **clb_hash_table, *clb_h_ptr; - struct s_hash **sub_hash_table, *sub_h_ptr; - struct s_hash **prim_hash_table, *prim_h_ptr; - - clb_hash_table = alloc_hash_table(); - sub_hash_table = alloc_hash_table(); - prim_hash_table = alloc_hash_table(); - - error = clb_count = sub_count = prim_count = 0; - - for (iblk = 0; iblk < num_blocks; iblk++) - { - clb_h_ptr = insert_in_hash_table(clb_hash_table, block[iblk].name, clb_count); - if (clb_h_ptr->count > 1) { - vpr_printf(TIO_MESSAGE_ERROR, "Block %s has duplicated name.\n", - block[iblk].name); - error++; - } else { - clb_count++; - } - for (isub = 0; isub < block[iblk].num_subblocks; isub++) - { - sub_h_ptr = insert_in_hash_table(sub_hash_table, block[iblk].subblocks[isub].name, sub_count); - if (sub_h_ptr->count > 1) { - vpr_printf(TIO_MESSAGE_ERROR, "Subblock %s has duplicated name.\n", - block[iblk].subblocks[isub].name); - error++; - } else { - sub_count++; - } - for (iprim = 0; iprim < block[iblk].subblocks[isub].num_primitives; iprim++) - { - prim_h_ptr = insert_in_hash_table(prim_hash_table, block[iblk].subblocks[isub].primitives[iprim].name, prim_count); - if (prim_h_ptr->count > 1) { - vpr_printf(TIO_MESSAGE_ERROR, "Primitive %s has duplicated name.\n", - block[iblk].subblocks[isub].primitives[iprim].name); - error++; - } else { - prim_count++; - } - } - } - } - return error; -#endif - return 0; -} - -static int get_num_conn(int bnum) { - - /* This routine returns the number of connections to a block. */ - - int i, num_conn; - t_type_ptr type; - - type = block[bnum].type; - - num_conn = 0; - - for (i = 0; i < type->num_pins; i++) { - if (block[bnum].nets[i] != OPEN) - num_conn++; - } - - return (num_conn); -} - diff --git a/vpr7_x2p/vpr/SRC/base/check_netlist.h b/vpr7_x2p/vpr/SRC/base/check_netlist.h deleted file mode 100644 index 290a12b52..000000000 --- a/vpr7_x2p/vpr/SRC/base/check_netlist.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef CHECK_NETLIST_H -#define CHECK_NETLIST_H - -void check_netlist(void); - -#endif - diff --git a/vpr7_x2p/vpr/SRC/base/draw.c b/vpr7_x2p/vpr/SRC/base/draw.c deleted file mode 100755 index 59ceb1a31..000000000 --- a/vpr7_x2p/vpr/SRC/base/draw.c +++ /dev/null @@ -1,2106 +0,0 @@ -#include -#include -#include -#include -#include "vpr_types.h" -#include "vpr_utils.h" -#include "globals.h" -#include "graphics.h" -#include "path_delay.h" -#include "draw.h" -#include -#include "read_xml_arch_file.h" -#include "util.h" - -#ifdef DEBUG -#include "rr_graph.h" -#endif - - -/*************** Types local to this module *********************************/ -#define MAX_BLOCK_COLOURS 5 - -enum e_draw_rr_toggle { - DRAW_NO_RR = 0, - DRAW_ALL_RR, - DRAW_ALL_BUT_BUFFERS_RR, - DRAW_NODES_AND_SBOX_RR, - DRAW_NODES_RR, - DRAW_RR_TOGGLE_MAX -}; - -enum e_draw_net_type { - ALL_NETS, HIGHLIGHTED -}; - -enum e_edge_dir { - FROM_X_TO_Y, FROM_Y_TO_X -}; -/* Chanx to chany or vice versa? */ - -/****************** Variables local to this module. *************************/ - -static boolean show_nets = FALSE; /* Show nets of placement or routing? */ - -/* Controls drawing of routing resources on screen, if pic_on_screen is * - * ROUTING. */ - -/* Can toggle to DRAW_NO_RR;*/ -static enum e_draw_rr_toggle draw_rr_toggle = DRAW_NO_RR; /* UDSD by AY */ - -static enum e_route_type draw_route_type; - -/* Controls if congestion is shown, when ROUTING is on screen. */ - -static boolean show_congestion = FALSE; - -static boolean show_defects = FALSE; /* Show defective stuff */ - -static boolean show_graphics; /* Graphics enabled or not? */ - -static char default_message[BUFSIZE]; /* Default screen message on screen */ - -static int gr_automode; /* Need user input after: 0: each t, * - * 1: each place, 2: never */ - -static enum pic_type pic_on_screen = NO_PICTURE; /* What do I draw? */ - -static float *tile_x, *tile_y; - -/* The left and bottom coordinates of each grid_tile in the FPGA. * - * tile_x[0..nx+1] and tile_y[0..ny+1]. * - * COORDINATE SYSTEM goes from (0,0) at the lower left corner to * - * (tile_x[nx+1]+tile_width, tile_y[ny+1]+tile_width) in the * - * upper right corner. */ - -static float tile_width, pin_size; - -/* Drawn width (and height) of a grid_tile, and the half-width or half-height of * - * a pin, respectiviely. Set when init_draw_coords is called. */ - -static enum color_types *net_color, *block_color; - -/* Color in which each block and net should be drawn. * - * [0..num_nets-1] and [0..num_blocks-1], respectively. */ - -static float line_fuz = 0.3; -static const char *name_type[] = { "SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY", - "INTRA_CLUSTER_EDGE" }; - -static float *x_rr_node_left = NULL; -static float *x_rr_node_right = NULL; -static float *y_rr_node_top = NULL; -static float *y_rr_node_bottom = NULL; -static enum color_types *rr_node_color = NULL; -static int old_num_rr_nodes = 0; - -/********************** Subroutines local to this module ********************/ - -static void toggle_nets(void (*drawscreen)(void)); -static void toggle_rr(void (*drawscreen)(void)); -static void toggle_defects(void (*drawscreen)(void)); -static void toggle_congestion(void (*drawscreen)(void)); -static void highlight_crit_path(void (*drawscreen_ptr)(void)); - -static void drawscreen(void); -static void redraw_screen(void); -static void drawplace(void); -static void drawnets(void); -static void drawroute(enum e_draw_net_type draw_net_type); -static void draw_congestion(void); - -static void highlight_blocks(float x, float y); -static void get_block_center(int bnum, float *x, float *y); -static void deselect_all(void); - -static void draw_rr(void); -static void draw_rr_edges(int from_node); -static void draw_rr_pin(int inode, enum color_types color); -static void draw_rr_chanx(int inode, int itrack); -static void draw_rr_chany(int inode, int itrack); -static void get_rr_pin_draw_coords(int inode, int iside, int ioff, float *xcen, - float *ycen); -static void draw_pin_to_chan_edge(int pin_node, int chan_node); -static void draw_pin_to_pin(int opin, int ipin); -static void draw_x(float x, float y, float size); -static void draw_chany_to_chany_edge(int from_node, int from_track, int to_node, - int to_track, short switch_type); -static void draw_chanx_to_chanx_edge(int from_node, int from_track, int to_node, - int to_track, short switch_type); -static void draw_chanx_to_chany_edge(int chanx_node, int chanx_track, - int chany_node, int chany_track, enum e_edge_dir edge_dir, - short switch_type); -static int get_track_num(int inode, int **chanx_track, int **chany_track); -static void draw_rr_switch(float from_x, float from_y, float to_x, float to_y, - boolean buffered); -static void draw_triangle_along_line(float xend, float yend, /* UDSD by AY */ - -float x1, float x2, /* UDSD by AY */ - -float y1, float y2); /* UDSD by AY */ - -/********************** Subroutine definitions ******************************/ - -void set_graphics_state(boolean show_graphics_val, int gr_automode_val, - enum e_route_type route_type) { - - /* Sets the static show_graphics and gr_automode variables to the * - * desired values. They control if graphics are enabled and, if so, * - * how often the user is prompted for input. */ - - show_graphics = show_graphics_val; - gr_automode = gr_automode_val; - draw_route_type = route_type; -} - -void update_screen(int priority, char *msg, enum pic_type pic_on_screen_val, - boolean crit_path_button_enabled) { - - /* Updates the screen if the user has requested graphics. The priority * - * value controls whether or not the Proceed button must be clicked to * - * continue. Saves the pic_on_screen_val to allow pan and zoom redraws. */ - - if (!show_graphics) /* Graphics turned off */ - return; - - /* If it's the type of picture displayed has changed, set up the proper * - * buttons. */ - if (pic_on_screen != pic_on_screen_val) { - if (pic_on_screen_val == PLACEMENT && pic_on_screen == NO_PICTURE) { - create_button("Window", "Toggle Nets", toggle_nets); - } else if (pic_on_screen_val == ROUTING && pic_on_screen == PLACEMENT) { - create_button("Toggle Nets", "Toggle RR", toggle_rr); - create_button("Toggle RR", "Tog Defects", toggle_defects); - create_button("Toggle RR", "Congestion", toggle_congestion); - - if (crit_path_button_enabled) { - create_button("Congestion", "Crit. Path", highlight_crit_path); - } - } else if (pic_on_screen_val == PLACEMENT && pic_on_screen == ROUTING) { - destroy_button("Toggle RR"); - destroy_button("Congestion"); - - if (crit_path_button_enabled) { - destroy_button("Crit. Path"); - } - } else if (pic_on_screen_val == ROUTING - && pic_on_screen == NO_PICTURE) { - create_button("Window", "Toggle Nets", toggle_nets); - create_button("Toggle Nets", "Toggle RR", toggle_rr); - create_button("Toggle RR", "Tog Defects", toggle_defects); - create_button("Tog Defects", "Congestion", toggle_congestion); - - if (crit_path_button_enabled) { - create_button("Congestion", "Crit. Path", highlight_crit_path); - } - } - } - /* Save the main message. */ - - my_strncpy(default_message, msg, BUFSIZE); - - pic_on_screen = pic_on_screen_val; - update_message(msg); - drawscreen(); - if (priority >= gr_automode) { - event_loop(highlight_blocks, NULL, NULL, drawscreen); - } else { - flushinput(); - } -} - -static void drawscreen() { - - /* This is the screen redrawing routine that event_loop assumes exists. * - * It erases whatever is on screen, then calls redraw_screen to redraw * - * it. */ - - clearscreen(); - redraw_screen(); -} - -static void redraw_screen() { - - /* The screen redrawing routine called by drawscreen and * - * highlight_blocks. Call this routine instead of drawscreen if * - * you know you don't need to erase the current graphics, and want * - * to avoid a screen "flash". */ - - setfontsize(14); /* UDSD Modification by WMF */ - if (pic_on_screen == PLACEMENT) { - drawplace(); - if (show_nets) { - drawnets(); - } - } else { /* ROUTING on screen */ - drawplace(); - - if (show_nets) { - drawroute(ALL_NETS); - } else { - draw_rr(); - } - - if (show_congestion) { - draw_congestion(); - } - } -} - -static void toggle_nets(void (*drawscreen_ptr)(void)) { - - /* Enables/disables drawing of nets when a the user clicks on a button. * - * Also disables drawing of routing resources. See graphics.c for details * - * of how buttons work. */ - - show_nets = (show_nets == FALSE) ? TRUE : FALSE; - draw_rr_toggle = DRAW_NO_RR; - show_congestion = FALSE; - - update_message(default_message); - drawscreen_ptr(); -} - -static void toggle_rr(void (*drawscreen_ptr)(void)) { - - /* Cycles through the options for viewing the routing resources available * - * in an FPGA. If a routing isn't on screen, the routing graph hasn't been * - * built, and this routine doesn't switch the view. Otherwise, this routine * - * switches to the routing resource view. Clicking on the toggle cycles * - * through the options: DRAW_NO_RR, DRAW_ALL_RR, DRAW_ALL_BUT_BUFFERS_RR, * - * DRAW_NODES_AND_SBOX_RR, and DRAW_NODES_RR. */ - - draw_rr_toggle = (enum e_draw_rr_toggle) (((int)draw_rr_toggle + 1) % ((int)DRAW_RR_TOGGLE_MAX)); - show_nets = FALSE; - show_congestion = FALSE; - - update_message(default_message); - drawscreen_ptr(); -} - -static void toggle_defects(void (*drawscreen_ptr)(void)) { - show_defects = (show_defects == FALSE) ? TRUE : FALSE; - update_message(default_message); - drawscreen_ptr(); -} - -static void toggle_congestion(void (*drawscreen_ptr)(void)) { - - /* Turns the congestion display on and off. */ - char msg[BUFSIZE]; - int inode, num_congested; - - show_nets = FALSE; - draw_rr_toggle = DRAW_NO_RR; - show_congestion = (show_congestion == FALSE) ? TRUE : FALSE; - - if (!show_congestion) { - update_message(default_message); - } else { - num_congested = 0; - for (inode = 0; inode < num_rr_nodes; inode++) { - if (rr_node[inode].occ > rr_node[inode].capacity) { - num_congested++; - } - } - - sprintf(msg, "%d routing resources are overused.", num_congested); - update_message(msg); - } - - drawscreen_ptr(); -} - -static void highlight_crit_path(void (*drawscreen_ptr)(void)) { - - /* Highlights all the blocks and nets on the critical path. */ - - t_linked_int *critical_path_head, *critical_path_node; - int inode, iblk, inet, num_nets_seen; - static int nets_to_highlight = 1; - char msg[BUFSIZE]; - - if (nets_to_highlight == 0) { /* Clear the display of all highlighting. */ - nets_to_highlight = 1; - deselect_all(); - update_message(default_message); - drawscreen_ptr(); - return; - } - - critical_path_head = allocate_and_load_critical_path(); - critical_path_node = critical_path_head; - num_nets_seen = 0; - - while (critical_path_node != NULL) { - inode = critical_path_node->data; - get_tnode_block_and_output_net(inode, &iblk, &inet); - - if (num_nets_seen == nets_to_highlight) { /* Last block */ - block_color[iblk] = MAGENTA; - } else if (num_nets_seen == nets_to_highlight - 1) { /* 2nd last block */ - block_color[iblk] = YELLOW; - } else if (num_nets_seen < nets_to_highlight) { /* Earlier block */ - block_color[iblk] = DARKGREEN; - } - - if (inet != OPEN) { - num_nets_seen++; - - if (num_nets_seen < nets_to_highlight) { /* First nets. */ - net_color[inet] = DARKGREEN; - } else if (num_nets_seen == nets_to_highlight) { - net_color[inet] = CYAN; /* Last (new) net. */ - } - } - - critical_path_node = critical_path_node->next; - } - - if (nets_to_highlight == num_nets_seen) { - nets_to_highlight = 0; - sprintf(msg, "All %d nets on the critical path highlighted.", - num_nets_seen); - } else { - sprintf(msg, "First %d nets on the critical path highlighted.", - nets_to_highlight); - nets_to_highlight++; - } - - free_int_list(&critical_path_head); - - update_message(msg); - drawscreen_ptr(); -} - -void alloc_draw_structs(void) { - - /* Allocate the structures needed to draw the placement and routing. Set * - * up the default colors for blocks and nets. */ - - tile_x = (float *) my_malloc((nx + 2) * sizeof(float)); - tile_y = (float *) my_malloc((ny + 2) * sizeof(float)); - - net_color = (enum color_types *) my_malloc( - num_nets * sizeof(enum color_types)); - - block_color = (enum color_types *) my_malloc( - num_blocks * sizeof(enum color_types)); - - x_rr_node_left = (float *) my_malloc(num_rr_nodes * sizeof(float)); - x_rr_node_right = (float *) my_malloc(num_rr_nodes * sizeof(float)); - y_rr_node_top = (float *) my_malloc(num_rr_nodes * sizeof(float)); - y_rr_node_bottom = (float *) my_malloc(num_rr_nodes * sizeof(float)); - rr_node_color = (enum color_types *) my_malloc( - num_rr_nodes * sizeof(enum color_types)); - - deselect_all(); /* Set initial colors */ -} - -void free_draw_structs(void) { - - /* Free everything allocated by alloc_draw_structs. Called after close_graphics() * - * in vpr_api.c. - * - * For safety, set all the array pointers to NULL in case any data - * structure gets freed twice. */ - - free(tile_x); - tile_x = NULL; - free(tile_y); - tile_y = NULL; - - free(net_color); - net_color = NULL; - free(block_color); - block_color = NULL; - - free(x_rr_node_left); - x_rr_node_left = NULL; - free(x_rr_node_right); - x_rr_node_right = NULL; - free(y_rr_node_top); - y_rr_node_top = NULL; - free(y_rr_node_bottom); - y_rr_node_bottom = NULL; - free(rr_node_color); - rr_node_color = NULL; -} - -void init_draw_coords(float width_val) { - - /* Load the arrays containing the left and bottom coordinates of the clbs * - * forming the FPGA. tile_width_val sets the width and height of a drawn * - * clb. */ - - int i; - int j; - - if (!show_graphics) - return; /* -nodisp was selected. */ - - if (num_rr_nodes != old_num_rr_nodes) { - x_rr_node_left = (float *) my_realloc(x_rr_node_left, - (num_rr_nodes) * sizeof(float)); - x_rr_node_right = (float *) my_realloc(x_rr_node_right, - (num_rr_nodes) * sizeof(float)); - y_rr_node_top = (float *) my_realloc(y_rr_node_top, - (num_rr_nodes) * sizeof(float)); - y_rr_node_bottom = (float *) my_realloc(y_rr_node_bottom, - (num_rr_nodes) * sizeof(float)); - rr_node_color = (enum color_types *) my_realloc(rr_node_color, - (num_rr_nodes) * sizeof(enum color_types)); - for (i = 0; i < num_rr_nodes; i++) { - x_rr_node_left[i] = -1; - x_rr_node_right[i] = -1; - y_rr_node_top[i] = -1; - y_rr_node_bottom[i] = -1; - rr_node_color[i] = BLACK; - } - } - - tile_width = width_val; - pin_size = 0.3; - for (i = 0; i < num_types; ++i) { - pin_size = std::min(pin_size, - (tile_width / (4.0F * type_descriptors[i].num_pins))); - } - - j = 0; - for (i = 0; i < (nx + 1); i++) { - tile_x[i] = (i * tile_width) + j; - j += chan_width_y[i] + 1; /* N wires need N+1 units of space */ - } - tile_x[nx + 1] = ((nx + 1) * tile_width) + j; - - j = 0; - for (i = 0; i < (ny + 1); ++i) { - tile_y[i] = (i * tile_width) + j; - j += chan_width_x[i] + 1; - } - tile_y[ny + 1] = ((ny + 1) * tile_width) + j; - - init_world(0.0, tile_y[ny + 1] + tile_width, tile_x[nx + 1] + tile_width, - 0.0); -} - -static void drawplace(void) { - - /* Draws the blocks placed on the proper clbs. Occupied blocks are darker colours * - * while empty ones are lighter colours and have a dashed border. */ - - float sub_tile_step; - float x1, y1, x2, y2; - int i, j, k, bnum; - int num_sub_tiles; - int height; - - setlinewidth(0); - - for (i = 0; i <= (nx + 1); i++) { - for (j = 0; j <= (ny + 1); j++) { - /* Only the first block of a group should control drawing */ - if (grid[i][j].offset > 0) - continue; - - /* Don't draw corners */ - if (((i < 1) || (i > nx)) && ((j < 1) || (j > ny))) - continue; - - num_sub_tiles = grid[i][j].type->capacity; - sub_tile_step = tile_width / num_sub_tiles; - height = grid[i][j].type->height; - - if (num_sub_tiles < 1) { - setcolor(BLACK); - setlinestyle(DASHED); - drawrect(tile_x[i], tile_y[j], tile_x[i] + tile_width, - tile_y[j] + tile_width); - draw_x(tile_x[i] + (tile_width / 2), - tile_y[j] + (tile_width / 2), (tile_width / 2)); - } - - for (k = 0; k < num_sub_tiles; ++k) { - /* Graphics will look unusual for multiple height and capacity */ - assert(height == 1 || num_sub_tiles == 1); - /* Get coords of current sub_tile */ - if ((i < 1) || (i > nx)) { /* left and right fringes */ - x1 = tile_x[i]; - y1 = tile_y[j] + (k * sub_tile_step); - x2 = x1 + tile_width; - y2 = y1 + sub_tile_step; - } else if ((j < 1) || (j > ny)) { /* top and bottom fringes */ - x1 = tile_x[i] + (k * sub_tile_step); - y1 = tile_y[j]; - x2 = x1 + sub_tile_step; - y2 = y1 + tile_width; - } else { - assert(num_sub_tiles <= 1); - /* Need to change draw code to support */ - - x1 = tile_x[i]; - y1 = tile_y[j]; - x2 = x1 + tile_width; - y2 = tile_y[j + height - 1] + tile_width; - } - - /* Look at the tile at start of large block */ - bnum = grid[i][j].blocks[k]; - - /* Draw background */ - if (bnum != EMPTY) { - setcolor(block_color[bnum]); - fillrect(x1, y1, x2, y2); - } else { - /* colour empty blocks a particular colour depending on type */ - if (grid[i][j].type->index < 3) { - setcolor(WHITE); - } else if (grid[i][j].type->index < 3 + MAX_BLOCK_COLOURS) { - setcolor(BISQUE + grid[i][j].type->index - 3); - } else { - setcolor(BISQUE + MAX_BLOCK_COLOURS - 1); - } - fillrect(x1, y1, x2, y2); - } - - setcolor(BLACK); - - setlinestyle((EMPTY == bnum) ? DASHED : SOLID); - drawrect(x1, y1, x2, y2); - - /* Draw text if the space has parts of the netlist */ - if (bnum != EMPTY) { - drawtext((x1 + x2) / 2.0, (y1 + y2) / 2.0, block[bnum].name, - tile_width); - } - - /* Draw text for block type so that user knows what block */ - if (grid[i][j].offset == 0) { - if (i > 0 && i <= nx && j > 0 && j <= ny) { - drawtext((x1 + x2) / 2.0, y1 + (tile_width / 4.0), - grid[i][j].type->name, tile_width); - } - } - } - } - } -} - -static void drawnets(void) { - - /* This routine draws the nets on the placement. The nets have not * - * yet been routed, so we just draw a chain showing a possible path * - * for each net. This gives some idea of future congestion. */ - - int inet, ipin, b1, b2; - float x1, y1, x2, y2; - - setlinestyle(SOLID); - setlinewidth(0); - - /* Draw the net as a star from the source to each sink. Draw from centers of * - * blocks (or sub blocks in the case of IOs). */ - - for (inet = 0; inet < num_nets; inet++) { - if (clb_net[inet].is_global) - continue; /* Don't draw global nets. */ - - setcolor(net_color[inet]); - b1 = clb_net[inet].node_block[0]; /* The DRIVER */ - get_block_center(b1, &x1, &y1); - - for (ipin = 1; ipin < (clb_net[inet].num_sinks + 1); ipin++) { - b2 = clb_net[inet].node_block[ipin]; - get_block_center(b2, &x2, &y2); - drawline(x1, y1, x2, y2); - - /* Uncomment to draw a chain instead of a star. */ - /* x1 = x2; */ - /* y1 = y2; */ - } - } -} - -static void get_block_center(int bnum, float *x, float *y) { - - /* This routine finds the center of block bnum in the current placement, * - * and returns it in *x and *y. This is used in routine shownets. */ - - int i, j, k; - float sub_tile_step; - - i = block[bnum].x; - j = block[bnum].y; - k = block[bnum].z; - - sub_tile_step = tile_width / block[bnum].type->capacity; - - if ((i < 1) || (i > nx)) { /* Left and right fringe */ - *x = tile_x[i] + (sub_tile_step * (k + 0.5)); - } else { - *x = tile_x[i] + (tile_width / 2.0); - } - - if ((j < 1) || (j > ny)) { /* Top and bottom fringe */ - *y = tile_y[j] + (sub_tile_step * (k + 0.5)); - } else { - *y = tile_y[j] + (tile_width / 2.0); - } -} - -static void draw_congestion(void) { - - /* Draws all the overused routing resources (i.e. congestion) in RED. */ - - int inode, itrack; - - setcolor(RED); - setlinewidth(2); - - for (inode = 0; inode < num_rr_nodes; inode++) { - if (rr_node[inode].occ > rr_node[inode].capacity) { - switch (rr_node[inode].type) { - case CHANX: - itrack = rr_node[inode].ptc_num; - draw_rr_chanx(inode, itrack); - break; - - case CHANY: - itrack = rr_node[inode].ptc_num; - draw_rr_chany(inode, itrack); - break; - - case IPIN: - case OPIN: - draw_rr_pin(inode, RED); - break; - default: - break; - } - } - } -} - -void draw_rr(void) { - - /* Draws the routing resources that exist in the FPGA, if the user wants * - * them drawn. */ - - int inode, itrack; - - if (draw_rr_toggle == DRAW_NO_RR) { - setlinewidth(3); - drawroute(HIGHLIGHTED); - setlinewidth(0); - return; - } - - setlinestyle(SOLID); - setlinewidth(0); - - for (inode = 0; inode < num_rr_nodes; inode++) { - switch (rr_node[inode].type) { - - case SOURCE: - case SINK: - break; /* Don't draw. */ - - case CHANX: - if (show_defects && (rr_node[inode].capacity <= 0)) - setcolor(RED); - else - setcolor(BLACK); - if (show_defects && (rr_node[inode].occ > 0)) - setcolor(CYAN); - itrack = rr_node[inode].ptc_num; - draw_rr_chanx(inode, itrack); - draw_rr_edges(inode); - break; - - case CHANY: - if (show_defects && (rr_node[inode].capacity <= 0)) - setcolor(RED); - else - setcolor(BLACK); - if (show_defects && (rr_node[inode].occ > 0)) - setcolor(CYAN); - itrack = rr_node[inode].ptc_num; - draw_rr_chany(inode, itrack); - draw_rr_edges(inode); - break; - - case IPIN: - if (show_defects) { - if (rr_node[inode].capacity < 0) - draw_rr_pin(inode, RED); - else if (rr_node[inode].occ > 0) - draw_rr_pin(inode, CYAN); - else - draw_rr_pin(inode, BLACK); - } else - draw_rr_pin(inode, BLUE); - break; - - case OPIN: - if (show_defects) { - if (rr_node[inode].capacity < 0) - draw_rr_pin(inode, RED); - else if (rr_node[inode].occ > 0) - draw_rr_pin(inode, CYAN); - else - draw_rr_pin(inode, BLACK); - setcolor(BLACK); - } else { - draw_rr_pin(inode, RED); - setcolor(RED); - } - setcolor(RED); - draw_rr_edges(inode); - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in draw_rr: Unexpected rr_node type: %d.\n", rr_node[inode].type); - exit(1); - } - } - - setlinewidth(3); - drawroute(HIGHLIGHTED); - setlinewidth(0); -} - -static void draw_rr_chanx(int inode, int itrack) { - - /* Draws an x-directed channel segment. */ - - enum { - BUFFSIZE = 80 - }; - float x1, x2, y; - float y1, y2; /* UDSD by AY */ - int k; /* UDSD by AY */ - char str[BUFFSIZE]; - int savecolor; - - /* Track 0 at bottom edge, closest to "owning" clb. */ - - x1 = tile_x[rr_node[inode].xlow]; - x2 = tile_x[rr_node[inode].xhigh] + tile_width; - y = tile_y[rr_node[inode].ylow] + tile_width + 1.0 + itrack; - x_rr_node_left[inode] = x1; - x_rr_node_right[inode] = x2; - y_rr_node_bottom[inode] = y - line_fuz; - y_rr_node_top[inode] = y + line_fuz; - if (rr_node_color[inode] != BLACK) { - savecolor = getcolor(); - setcolor(rr_node_color[inode]); - setlinewidth(3); - drawline(x1, y, x2, y); - setlinewidth(0); - setcolor(savecolor); - } else { - drawline(x1, y, x2, y); - } - /* UDSD by AY Start */ - y1 = y - 0.25; - y2 = y + 0.25; - - if (rr_node[inode].direction == INC_DIRECTION) { - setlinewidth(2); - setcolor(YELLOW); - drawline(x1, y1, x1, y2); /* Draw a line at start of wire to indicate mux */ - - /* Mux balence numbers */ - setcolor(BLACK); - sprintf(str, "%d", rr_node[inode].fan_in); - drawtext(x1, y, str, 5); - - setcolor(BLACK); - setlinewidth(0); - draw_triangle_along_line(x2 - 0.15, y, x1, x2, y, y); - - setcolor(LIGHTGREY); - /* TODO: this looks odd, why does it ignore final block? does this mean nothing appears with L=1 ? */ - for (k = rr_node[inode].xlow; k < rr_node[inode].xhigh; k++) { - x2 = tile_x[k] + tile_width; - draw_triangle_along_line(x2 - 0.15, y, x1, x2, y, y); - x2 = tile_x[k + 1]; - draw_triangle_along_line(x2 + 0.15, y, x1, x2, y, y); - } - setcolor(BLACK); - } else if (rr_node[inode].direction == DEC_DIRECTION) { - setlinewidth(2); - setcolor(YELLOW); - drawline(x2, y1, x2, y2); - - /* Mux balance numbers */ - setcolor(BLACK); - sprintf(str, "%d", rr_node[inode].fan_in); - drawtext(x2, y, str, 5); - - setlinewidth(0); - draw_triangle_along_line(x1 + 0.15, y, x2, x1, y, y); - setcolor(LIGHTGREY); - for (k = rr_node[inode].xhigh; k > rr_node[inode].xlow; k--) { - x1 = tile_x[k]; - draw_triangle_along_line(x1 + 0.15, y, x2, x1, y, y); - x1 = tile_x[k - 1] + tile_width; - draw_triangle_along_line(x1 - 0.15, y, x2, x1, y, y); - } - setcolor(BLACK); - } - /* UDSD by AY End */ -} - -static void draw_rr_chany(int inode, int itrack) { - - /* Draws a y-directed channel segment. */ - enum { - BUFFSIZE = 80 - }; - float x, y1, y2; - float x1, x2; /* UDSD by AY */ - int k; /* UDSD by AY */ - char str[BUFFSIZE]; - int savecolor; - - /* Track 0 at left edge, closest to "owning" clb. */ - - x = tile_x[rr_node[inode].xlow] + tile_width + 1. + itrack; - y1 = tile_y[rr_node[inode].ylow]; - y2 = tile_y[rr_node[inode].yhigh] + tile_width; - x_rr_node_left[inode] = x - line_fuz; - x_rr_node_right[inode] = x + line_fuz; - y_rr_node_bottom[inode] = y1; - y_rr_node_top[inode] = y2; - if (rr_node_color[inode] != BLACK) { - savecolor = getcolor(); - setcolor(rr_node_color[inode]); - setlinewidth(3); - drawline(x, y1, x, y2); - setlinewidth(0); - setcolor(savecolor); - } else { - drawline(x, y1, x, y2); - } - - /* UDSD by AY Start */ - x1 = x - 0.25; - x2 = x + 0.25; - if (rr_node[inode].direction == INC_DIRECTION) { - setlinewidth(2); - setcolor(YELLOW); - drawline(x1, y1, x2, y1); - - /* UDSD Modifications by WMF Begin */ - setcolor(BLACK); - sprintf(str, "%d", rr_node[inode].fan_in); - drawtext(x, y1, str, 5); - setcolor(BLACK); - /* UDSD Modifications by WMF End */ - - setlinewidth(0); - draw_triangle_along_line(x, y2 - 0.15, x, x, y1, y2); - setcolor(LIGHTGREY); - for (k = rr_node[inode].ylow; k < rr_node[inode].yhigh; k++) { - y2 = tile_y[k] + tile_width; - draw_triangle_along_line(x, y2 - 0.15, x, x, y1, y2); - y2 = tile_y[k + 1]; - draw_triangle_along_line(x, y2 + 0.15, x, x, y1, y2); - } - setcolor(BLACK); - } else if (rr_node[inode].direction == DEC_DIRECTION) { - setlinewidth(2); - setcolor(YELLOW); - drawline(x1, y2, x2, y2); - - /* UDSD Modifications by WMF Begin */ - setcolor(BLACK); - sprintf(str, "%d", rr_node[inode].fan_in); - drawtext(x, y2, str, 5); - setcolor(BLACK); - /* UDSD Modifications by WMF End */ - - setlinewidth(0); - draw_triangle_along_line(x, y1 + 0.15, x, x, y2, y1); - setcolor(LIGHTGREY); - for (k = rr_node[inode].yhigh; k > rr_node[inode].ylow; k--) { - y1 = tile_y[k]; - draw_triangle_along_line(x, y1 + 0.15, x, x, y2, y1); - y1 = tile_y[k - 1] + tile_width; - draw_triangle_along_line(x, y1 - 0.15, x, x, y2, y1); - } - setcolor(BLACK); - } - /* UDSD by AY End */ -} - -static void draw_rr_edges(int inode) { - - /* Draws all the edges that the user wants shown between inode and what it * - * connects to. inode is assumed to be a CHANX, CHANY, or OPIN. */ - - t_rr_type from_type, to_type; - int iedge, to_node, from_ptc_num, to_ptc_num; - short switch_type; - boolean defective = FALSE; - - from_type = rr_node[inode].type; - - if ((draw_rr_toggle == DRAW_NODES_RR) - || (draw_rr_toggle == DRAW_NODES_AND_SBOX_RR && from_type == OPIN)) { - return; /* Nothing to draw. */ - } - - from_ptc_num = rr_node[inode].ptc_num; - - for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { - to_node = rr_node[inode].edges[iedge]; - to_type = rr_node[to_node].type; - to_ptc_num = rr_node[to_node].ptc_num; - - if (show_defects) - defective = (boolean)(switch_inf[rr_node[inode].switches[iedge]].R < 0); - switch (from_type) { - - case OPIN: - switch (to_type) { - case CHANX: - case CHANY: - if (show_defects) { - if (defective) - setcolor(RED); - else - setcolor(BLACK); - } else - setcolor(RED); - draw_pin_to_chan_edge(inode, to_node); - break; - case IPIN: - setcolor(RED); - draw_pin_to_pin(inode, to_node); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "in draw_rr_edges: node %d (type: %d) connects to node %d (type: %d).\n", - inode, from_type, to_node, to_type); - exit(1); - break; - } - break; - - case CHANX: /* from_type */ - switch (to_type) { - case IPIN: - if (draw_rr_toggle == DRAW_NODES_AND_SBOX_RR) { - break; - } - - if (show_defects) { - if (defective) - setcolor(RED); - else - setcolor(BLACK); - } else - setcolor(BLUE); - draw_pin_to_chan_edge(to_node, inode); - break; - - case CHANX: - if (show_defects) { - if (defective) - setcolor(RED); - else - setcolor(BLACK); - } else - setcolor(DARKGREEN); - switch_type = rr_node[inode].switches[iedge]; - draw_chanx_to_chanx_edge(inode, from_ptc_num, to_node, - to_ptc_num, switch_type); - break; - - case CHANY: - if (show_defects) { - if (defective) - setcolor(RED); - else - setcolor(BLACK); - } else - setcolor(DARKGREEN); - switch_type = rr_node[inode].switches[iedge]; - draw_chanx_to_chany_edge(inode, from_ptc_num, to_node, - to_ptc_num, FROM_X_TO_Y, switch_type); - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in draw_rr_edges: node %d (type: %d) connects to node %d (type: %d).\n", - inode, from_type, to_node, to_type); - exit(1); - break; - } - break; - - case CHANY: /* from_type */ - switch (to_type) { - case IPIN: - if (draw_rr_toggle == DRAW_NODES_AND_SBOX_RR) { - break; - } - - if (show_defects) { - if (defective) - setcolor(RED); - else - setcolor(BLACK); - } else - setcolor(BLUE); - draw_pin_to_chan_edge(to_node, inode); - break; - - case CHANX: - if (show_defects) { - if (defective) - setcolor(RED); - else - setcolor(BLACK); - } else - setcolor(DARKGREEN); - switch_type = rr_node[inode].switches[iedge]; - draw_chanx_to_chany_edge(to_node, to_ptc_num, inode, - from_ptc_num, FROM_Y_TO_X, switch_type); - break; - - case CHANY: - if (show_defects) { - if (defective) - setcolor(RED); - else - setcolor(BLACK); - } else - setcolor(DARKGREEN); - switch_type = rr_node[inode].switches[iedge]; - draw_chany_to_chany_edge(inode, from_ptc_num, to_node, - to_ptc_num, switch_type); - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in draw_rr_edges: node %d (type: %d) connects to node %d (type: %d).\n", - inode, from_type, to_node, to_type); - exit(1); - break; - } - break; - - default: /* from_type */ - vpr_printf(TIO_MESSAGE_ERROR, "draw_rr_edges called with node %d of type %d.\n", - inode, from_type); - exit(1); - break; - } - } /* End of for each edge loop */ -} - -static void draw_x(float x, float y, float size) { - - /* Draws an X centered at (x,y). The width and height of the X are each * - * 2 * size. */ - - drawline(x - size, y + size, x + size, y - size); - drawline(x - size, y - size, x + size, y + size); -} - -/* UDSD Modifications by WMF: Thank God Andy fixed this. */ -static void draw_chanx_to_chany_edge(int chanx_node, int chanx_track, - int chany_node, int chany_track, enum e_edge_dir edge_dir, - short switch_type) { - - /* Draws an edge (SBOX connection) between an x-directed channel and a * - * y-directed channel. */ - - float x1, y1, x2, y2; - int chanx_y, chany_x, chanx_xlow, chany_ylow; - - chanx_y = rr_node[chanx_node].ylow; - chanx_xlow = rr_node[chanx_node].xlow; - chany_x = rr_node[chany_node].xlow; - chany_ylow = rr_node[chany_node].ylow; - - /* (x1,y1): point on CHANX segment, (x2,y2): point on CHANY segment. */ - - y1 = tile_y[chanx_y] + tile_width + 1. + chanx_track; - x2 = tile_x[chany_x] + tile_width + 1. + chany_track; - - if (chanx_xlow <= chany_x) { /* Can draw connection going right */ - x1 = tile_x[chany_x] + tile_width; - /* UDSD by AY Start */ - if (rr_node[chanx_node].direction != BI_DIRECTION) { - if (edge_dir == FROM_X_TO_Y) { - if ((chanx_track % 2) == 1) { /* UDSD Modifications by WMF: If dec wire, then going left */ - x1 = tile_x[chany_x + 1]; - } - } - } - /* UDSD by AY End */ - } else { /* Must draw connection going left. */ - x1 = tile_x[chanx_xlow]; - } - - if (chany_ylow <= chanx_y) { /* Can draw connection going up. */ - y2 = tile_y[chanx_y] + tile_width; - /* UDSD by AY Start */ - if (rr_node[chany_node].direction != BI_DIRECTION) { - if (edge_dir == FROM_Y_TO_X) { - if ((chany_track % 2) == 1) { /* UDSD Modifications by WMF: If dec wire, then going down */ - y2 = tile_y[chanx_y + 1]; - } - } - } - /* UDSD by AY End */ - } else { /* Must draw connection going down. */ - y2 = tile_y[chany_ylow]; - } - - drawline(x1, y1, x2, y2); - - if (draw_rr_toggle != DRAW_ALL_RR) - return; - - if (edge_dir == FROM_X_TO_Y) - draw_rr_switch(x1, y1, x2, y2, switch_inf[switch_type].buffered); - else - draw_rr_switch(x2, y2, x1, y1, switch_inf[switch_type].buffered); -} - -static void draw_chanx_to_chanx_edge(int from_node, int from_track, int to_node, - int to_track, short switch_type) { - - /* Draws a connection between two x-channel segments. Passing in the track * - * numbers allows this routine to be used for both rr_graph and routing * - * drawing. */ - - float x1, x2, y1, y2; - int from_y, to_y, from_xlow, to_xlow, from_xhigh, to_xhigh; - - from_y = rr_node[from_node].ylow; - from_xlow = rr_node[from_node].xlow; - from_xhigh = rr_node[from_node].xhigh; - to_y = rr_node[to_node].ylow; - to_xlow = rr_node[to_node].xlow; - to_xhigh = rr_node[to_node].xhigh; - - /* (x1, y1) point on from_node, (x2, y2) point on to_node. */ - - y1 = tile_y[from_y] + tile_width + 1 + from_track; - y2 = tile_y[to_y] + tile_width + 1 + to_track; - - if (to_xhigh < from_xlow) { /* From right to left */ - /* UDSD Note by WMF: could never happen for INC wires, unless U-turn. For DEC - * wires this handles well */ - x1 = tile_x[from_xlow]; - x2 = tile_x[to_xhigh] + tile_width; - } else if (to_xlow > from_xhigh) { /* From left to right */ - /* UDSD Note by WMF: could never happen for DEC wires, unless U-turn. For INC - * wires this handles well */ - x1 = tile_x[from_xhigh] + tile_width; - x2 = tile_x[to_xlow]; - } - - /* Segments overlap in the channel. Figure out best way to draw. Have to * - * make sure the drawing is symmetric in the from rr and to rr so the edges * - * will be drawn on top of each other for bidirectional connections. */ - - /* UDSD Modification by WMF Begin */ - else { - if (rr_node[to_node].direction != BI_DIRECTION) { - /* must connect to to_node's wire beginning at x2 */ - if (to_track % 2 == 0) { /* INC wire starts at leftmost edge */ - assert(from_xlow < to_xlow); - x2 = tile_x[to_xlow]; - /* since no U-turns from_track must be INC as well */ - x1 = tile_x[to_xlow - 1] + tile_width; - } else { /* DEC wire starts at rightmost edge */ - assert(from_xhigh > to_xhigh); - x2 = tile_x[to_xhigh] + tile_width; - x1 = tile_x[to_xhigh + 1]; - } - } else { - if (to_xlow < from_xlow) { /* Draw from left edge of one to other */ - x1 = tile_x[from_xlow]; - x2 = tile_x[from_xlow - 1] + tile_width; - } else if (from_xlow < to_xlow) { - x1 = tile_x[to_xlow - 1] + tile_width; - x2 = tile_x[to_xlow]; - } /* The following then is executed when from_xlow == to_xlow */ - else if (to_xhigh > from_xhigh) { /* Draw from right edge of one to other */ - x1 = tile_x[from_xhigh] + tile_width; - x2 = tile_x[from_xhigh + 1]; - } else if (from_xhigh > to_xhigh) { - x1 = tile_x[to_xhigh + 1]; - x2 = tile_x[to_xhigh] + tile_width; - } else { /* Complete overlap: start and end both align. Draw outside the sbox */ - x1 = tile_x[from_xlow]; - x2 = tile_x[from_xlow] + tile_width; - } - } - } - /* UDSD Modification by WMF End */ - drawline(x1, y1, x2, y2); - - if (draw_rr_toggle == DRAW_ALL_RR) - draw_rr_switch(x1, y1, x2, y2, switch_inf[switch_type].buffered); -} - -static void draw_chany_to_chany_edge(int from_node, int from_track, int to_node, - int to_track, short switch_type) { - - /* Draws a connection between two y-channel segments. Passing in the track * - * numbers allows this routine to be used for both rr_graph and routing * - * drawing. */ - - float x1, x2, y1, y2; - int from_x, to_x, from_ylow, to_ylow, from_yhigh, to_yhigh; - - from_x = rr_node[from_node].xlow; - from_ylow = rr_node[from_node].ylow; - from_yhigh = rr_node[from_node].yhigh; - to_x = rr_node[to_node].xlow; - to_ylow = rr_node[to_node].ylow; - to_yhigh = rr_node[to_node].yhigh; - - /* (x1, y1) point on from_node, (x2, y2) point on to_node. */ - - x1 = tile_x[from_x] + tile_width + 1 + from_track; - x2 = tile_x[to_x] + tile_width + 1 + to_track; - - if (to_yhigh < from_ylow) { /* From upper to lower */ - y1 = tile_y[from_ylow]; - y2 = tile_y[to_yhigh] + tile_width; - } else if (to_ylow > from_yhigh) { /* From lower to upper */ - y1 = tile_y[from_yhigh] + tile_width; - y2 = tile_y[to_ylow]; - } - - /* Segments overlap in the channel. Figure out best way to draw. Have to * - * make sure the drawing is symmetric in the from rr and to rr so the edges * - * will be drawn on top of each other for bidirectional connections. */ - - /* UDSD Modification by WMF Begin */ - else { - if (rr_node[to_node].direction != BI_DIRECTION) { - if (to_track % 2 == 0) { /* INC wire starts at bottom edge */ - assert(from_ylow < to_ylow); - y2 = tile_y[to_ylow]; - /* since no U-turns from_track must be INC as well */ - y1 = tile_y[to_ylow - 1] + tile_width; - } else { /* DEC wire starts at top edge */ - if (!(from_yhigh > to_yhigh)) { - vpr_printf(TIO_MESSAGE_INFO, "from_yhigh (%d) !> to_yhigh (%d).\n", - from_yhigh, to_yhigh); - vpr_printf(TIO_MESSAGE_INFO, "from is (%d, %d) to (%d, %d) track %d.\n", - rr_node[from_node].xhigh, rr_node[from_node].yhigh, - rr_node[from_node].xlow, rr_node[from_node].ylow, - rr_node[from_node].ptc_num); - vpr_printf(TIO_MESSAGE_INFO, "to is (%d, %d) to (%d, %d) track %d.\n", - rr_node[to_node].xhigh, rr_node[to_node].yhigh, - rr_node[to_node].xlow, rr_node[to_node].ylow, - rr_node[to_node].ptc_num); - exit(1); - } - y2 = tile_y[to_yhigh] + tile_width; - y1 = tile_y[to_yhigh + 1]; - } - } else { - if (to_ylow < from_ylow) { /* Draw from bottom edge of one to other. */ - y1 = tile_y[from_ylow]; - y2 = tile_y[from_ylow - 1] + tile_width; - } else if (from_ylow < to_ylow) { - y1 = tile_y[to_ylow - 1] + tile_width; - y2 = tile_y[to_ylow]; - } else if (to_yhigh > from_yhigh) { /* Draw from top edge of one to other. */ - y1 = tile_y[from_yhigh] + tile_width; - y2 = tile_y[from_yhigh + 1]; - } else if (from_yhigh > to_yhigh) { - y1 = tile_y[to_yhigh + 1]; - y2 = tile_y[to_yhigh] + tile_width; - } else { /* Complete overlap: start and end both align. Draw outside the sbox */ - y1 = tile_y[from_ylow]; - y2 = tile_y[from_ylow] + tile_width; - } - } - } - /* UDSD Modification by WMF End */ - drawline(x1, y1, x2, y2); - - if (draw_rr_toggle == DRAW_ALL_RR) - draw_rr_switch(x1, y1, x2, y2, switch_inf[switch_type].buffered); -} - -static void draw_rr_switch(float from_x, float from_y, float to_x, float to_y, - boolean buffered) { - - /* Draws a buffer (triangle) or pass transistor (circle) on the edge * - * connecting from to to, depending on the status of buffered. The drawing * - * is closest to the from_node, since it reflects the switch type of from. */ - - const float switch_rad = 0.15; - float magnitude, xcen, ycen, xdelta, ydelta, xbaseline, ybaseline; - float xunit, yunit; - t_point poly[3]; - - xcen = from_x + (to_x - from_x) / 10.; - ycen = from_y + (to_y - from_y) / 10.; - - if (!buffered) { /* Draw a circle for a pass transistor */ - drawarc(xcen, ycen, switch_rad, 0., 360.); - } else { /* Buffer */ - xdelta = to_x - from_x; - ydelta = to_y - from_y; - magnitude = sqrt(xdelta * xdelta + ydelta * ydelta); - xunit = xdelta / magnitude; - yunit = ydelta / magnitude; - poly[0].x = xcen + xunit * switch_rad; - poly[0].y = ycen + yunit * switch_rad; - xbaseline = xcen - xunit * switch_rad; - ybaseline = ycen - yunit * switch_rad; - - /* Recall: perpendicular vector to the unit vector along the switch (xv, yv) * - * is (yv, -xv). */ - - poly[1].x = xbaseline + yunit * switch_rad; - poly[1].y = ybaseline - xunit * switch_rad; - poly[2].x = xbaseline - yunit * switch_rad; - poly[2].y = ybaseline + xunit * switch_rad; - fillpoly(poly, 3); - } -} - -static void draw_rr_pin(int inode, enum color_types color) { - - /* Draws an IPIN or OPIN rr_node. Note that the pin can appear on more * - * than one side of a clb. Also note that this routine can change the * - * current color to BLACK. */ - - int ipin, i, j, iside, ioff; - float xcen, ycen; - char str[BUFSIZE]; - t_type_ptr type; - - i = rr_node[inode].xlow; - j = rr_node[inode].ylow; - ipin = rr_node[inode].ptc_num; - type = grid[i][j].type; - ioff = grid[i][j].offset; - - setcolor(color); - /* TODO: This is where we can hide fringe physical pins and also identify globals (hide, color, show) */ - for (iside = 0; iside < 4; iside++) { - if (type->pinloc[grid[i][j].offset][iside][ipin]) { /* Pin exists on this side. */ - get_rr_pin_draw_coords(inode, iside, ioff, &xcen, &ycen); - fillrect(xcen - pin_size, ycen - pin_size, xcen + pin_size, - ycen + pin_size); - sprintf(str, "%d", ipin); - setcolor(BLACK); - drawtext(xcen, ycen, str, 2 * pin_size); - setcolor(color); - } - } -} - -static void get_rr_pin_draw_coords(int inode, int iside, int ioff, float *xcen, - float *ycen) { - - /* Returns the coordinates at which the center of this pin should be drawn. * - * inode gives the node number, and iside gives the side of the clb or pad * - * the physical pin is on. */ - - int i, j, k, ipin, pins_per_sub_tile; - float offset, xc, yc, step; - t_type_ptr type; - - i = rr_node[inode].xlow; - j = rr_node[inode].ylow + ioff; /* Need correct tile of block */ - - xc = tile_x[i]; - yc = tile_y[j]; - - ipin = rr_node[inode].ptc_num; - type = grid[i][j].type; - pins_per_sub_tile = grid[i][j].type->num_pins / grid[i][j].type->capacity; - k = ipin / pins_per_sub_tile; - - /* Since pins numbers go across all sub_tiles in a block in order - * we can treat as a block box for this step */ - - /* For each sub_tile we need and extra padding space */ - step = (float) (tile_width) / (float) (type->num_pins + type->capacity); - offset = (ipin + k + 1) * step; - - switch (iside) { - case LEFT: - yc += offset; - break; - - case RIGHT: - xc += tile_width; - yc += offset; - break; - - case BOTTOM: - xc += offset; - break; - - case TOP: - xc += offset; - yc += tile_width; - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in get_rr_pin_draw_coords: Unexpected iside %d.\n", iside); - exit(1); - break; - } - - *xcen = xc; - *ycen = yc; -} - -static void drawroute(enum e_draw_net_type draw_net_type) { - - /* Draws the nets in the positions fixed by the router. If draw_net_type is * - * ALL_NETS, draw all the nets. If it is HIGHLIGHTED, draw only the nets * - * that are not coloured black (useful for drawing over the rr_graph). */ - - /* Next free track in each channel segment if routing is GLOBAL */ - - static int **chanx_track = NULL; /* [1..nx][0..ny] */ - static int **chany_track = NULL; /* [0..nx][1..ny] */ - - int inet, i, j, inode, prev_node, prev_track, itrack; - short switch_type; - struct s_trace *tptr; - t_rr_type rr_type, prev_type; - - if (draw_route_type == GLOBAL) { - /* Allocate some temporary storage if it's not already available. */ - if (chanx_track == NULL) { - chanx_track = (int **) alloc_matrix(1, nx, 0, ny, sizeof(int)); - } - - if (chany_track == NULL) { - chany_track = (int **) alloc_matrix(0, nx, 1, ny, sizeof(int)); - } - - for (i = 1; i <= nx; i++) - for (j = 0; j <= ny; j++) - chanx_track[i][j] = (-1); - - for (i = 0; i <= nx; i++) - for (j = 1; j <= ny; j++) - chany_track[i][j] = (-1); - } - - setlinestyle(SOLID); - - /* Now draw each net, one by one. */ - - for (inet = 0; inet < num_nets; inet++) { - if (clb_net[inet].is_global) /* Don't draw global nets. */ - continue; - - if (trace_head[inet] == NULL) /* No routing. Skip. (Allows me to draw */ - continue; /* partially complete routes). */ - - if (draw_net_type == HIGHLIGHTED && net_color[inet] == BLACK) - continue; - - setcolor(net_color[inet]); - tptr = trace_head[inet]; /* SOURCE to start */ - inode = tptr->index; - rr_type = rr_node[inode].type; - - for (;;) { - prev_node = inode; - prev_type = rr_type; - switch_type = tptr->iswitch; - tptr = tptr->next; - inode = tptr->index; - rr_type = rr_node[inode].type; - - switch (rr_type) { - - case OPIN: - draw_rr_pin(inode, net_color[inet]); - break; - - case IPIN: - draw_rr_pin(inode, net_color[inet]); - if(rr_node[prev_node].type == OPIN) { - draw_pin_to_pin(prev_node, inode); - } else { - prev_track = get_track_num(prev_node, chanx_track, chany_track); - draw_pin_to_chan_edge(inode, prev_node); - } - break; - - case CHANX: - if (draw_route_type == GLOBAL) - chanx_track[rr_node[inode].xlow][rr_node[inode].ylow]++; - - itrack = get_track_num(inode, chanx_track, chany_track); - draw_rr_chanx(inode, itrack); - - switch (prev_type) { - - case CHANX: - prev_track = get_track_num(prev_node, chanx_track, - chany_track); - draw_chanx_to_chanx_edge(prev_node, prev_track, inode, - itrack, switch_type); - break; - - case CHANY: - prev_track = get_track_num(prev_node, chanx_track, - chany_track); - draw_chanx_to_chany_edge(inode, itrack, prev_node, - prev_track, FROM_Y_TO_X, switch_type); - break; - - case OPIN: - draw_pin_to_chan_edge(prev_node, inode); - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in drawroute: Unexpected connection from an rr_node of type %d to one of type %d.\n", - prev_type, rr_type); - exit(1); - } - - break; - - case CHANY: - if (draw_route_type == GLOBAL) - chany_track[rr_node[inode].xlow][rr_node[inode].ylow]++; - - itrack = get_track_num(inode, chanx_track, chany_track); - draw_rr_chany(inode, itrack); - - switch (prev_type) { - - case CHANX: - prev_track = get_track_num(prev_node, chanx_track, - chany_track); - draw_chanx_to_chany_edge(prev_node, prev_track, inode, - itrack, FROM_X_TO_Y, switch_type); - break; - - case CHANY: - prev_track = get_track_num(prev_node, chanx_track, - chany_track); - draw_chany_to_chany_edge(prev_node, prev_track, inode, - itrack, switch_type); - break; - - case OPIN: - draw_pin_to_chan_edge(prev_node, inode); - - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in drawroute: Unexpected connection from an rr_node of type %d to one of type %d.\n", - prev_type, rr_type); - exit(1); - } - - break; - - default: - break; - - } - - if (rr_type == SINK) { /* Skip the next segment */ - tptr = tptr->next; - if (tptr == NULL) - break; - inode = tptr->index; - rr_type = rr_node[inode].type; - } - - } /* End loop over traceback. */ - } /* End for (each net) */ -} - -static int get_track_num(int inode, int **chanx_track, int **chany_track) { - - /* Returns the track number of this routing resource node. */ - - int i, j; - t_rr_type rr_type; - - if (draw_route_type == DETAILED) - return (rr_node[inode].ptc_num); - - /* GLOBAL route stuff below. */ - - rr_type = rr_node[inode].type; - i = rr_node[inode].xlow; /* NB: Global rr graphs must have only unit */ - j = rr_node[inode].ylow; /* length channel segments. */ - - switch (rr_type) { - case CHANX: - return (chanx_track[i][j]); - - case CHANY: - return (chany_track[i][j]); - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in get_track_num: Unexpected node type %d for node %d.\n", rr_type, inode); - exit(1); - } -} - -static void highlight_nets(char *message) { - int inet; - struct s_trace *tptr; - - for (inet = 0; inet < num_nets; inet++) { - for (tptr = trace_head[inet]; tptr != NULL; tptr = tptr->next) { - if (rr_node_color[tptr->index] != BLACK) { - net_color[inet] = rr_node_color[tptr->index]; - sprintf(message, "%s || Net:%d %d", message, inet, - trace_head[inet]->index); - break; - } - } - } - update_message(message); -} - -static void highlight_rr_nodes(float x, float y) { - int inode; - int hit = 0; - char message[250] = ""; - int edge; - - if (draw_rr_toggle == DRAW_NO_RR && !show_nets) { - update_message(default_message); - drawscreen(); - return; - } - - for (inode = 0; inode < num_rr_nodes; inode++) { - if (x >= x_rr_node_left[inode] && x <= x_rr_node_right[inode] - && y >= y_rr_node_bottom[inode] && y <= y_rr_node_top[inode]) { - t_rr_type rr_type = rr_node[inode].type; - int xlow = rr_node[inode].xlow; - int xhigh = rr_node[inode].xhigh; - int ylow = rr_node[inode].ylow; - int yhigh = rr_node[inode].yhigh; - int ptc_num = rr_node[inode].ptc_num; - rr_node_color[inode] = MAGENTA; - sprintf(message, "%s%s %d: %s (%d,%d) -> (%d,%d) track: %d", - message, (hit ? " | " : ""), inode, name_type[rr_type], - xlow, ylow, xhigh, yhigh, ptc_num); - -#ifdef DEBUG - print_rr_node(stdout, rr_node, inode); -#endif - for (edge = 0; edge < rr_node[inode].num_edges; edge++) { - if (rr_node_color[rr_node[inode].edges[edge]] == BLACK - && rr_node[rr_node[inode].edges[edge]].capacity - > rr_node[rr_node[inode].edges[edge]].occ) - rr_node_color[rr_node[inode].edges[edge]] = GREEN; - else if (rr_node_color[rr_node[inode].edges[edge]] == BLACK - && rr_node[rr_node[inode].edges[edge]].capacity - == rr_node[rr_node[inode].edges[edge]].occ) - rr_node_color[rr_node[inode].edges[edge]] = BLUE; - - } - hit = 1; - } - } - - if (!hit) { - update_message(default_message); - drawscreen(); - return; - } - - if (show_nets) { - highlight_nets(message); - } else - update_message(message); - drawscreen(); -} - -static void highlight_blocks(float x, float y) { - - /* This routine is called when the user clicks in the graphics area. * - * It determines if a clb was clicked on. If one was, it is * - * highlighted in green, it's fanin nets and clbs are highlighted in * - * blue and it's fanout is highlighted in red. If no clb was * - * clicked on (user clicked on white space) any old highlighting is * - * removed. Note that even though global nets are not drawn, their * - * fanins and fanouts are highlighted when you click on a block * - * attached to them. */ - - int i, j, k, hit, bnum, ipin, netnum, fanblk; - int iclass; - float io_step; - t_type_ptr type; - char msg[BUFSIZE]; - - deselect_all(); - - hit = i = j = k = 0; - - for (i = 0; i <= (nx + 1) && !hit; i++) { - if (x <= tile_x[i] + tile_width) { - if (x >= tile_x[i]) { - for (j = 0; j <= (ny + 1) && !hit; j++) { - if (grid[i][j].offset != 0) - continue; - type = grid[i][j].type; - if (y <= tile_y[j + type->height - 1] + tile_width) { - if (y >= tile_y[j]) - hit = 1; - } - } - - } - } - } - i--; - j--; - - if (!hit) { - highlight_rr_nodes(x, y); - /* update_message(default_message); - drawscreen(); */ - return; - } - type = grid[i][j].type; - hit = 0; - - if (EMPTY_TYPE == type) { - update_message(default_message); - drawscreen(); - return; - } - - /* The user selected the clb at location (i,j). */ - io_step = tile_width / type->capacity; - - if ((i < 1) || (i > nx)) /* Vertical columns of IOs */ - k = (int) ((y - tile_y[j]) / io_step); - else - k = (int) ((x - tile_x[i]) / io_step); - - assert(k < type->capacity); - if (grid[i][j].blocks[k] == EMPTY) { - update_message(default_message); - drawscreen(); - return; - } - bnum = grid[i][j].blocks[k]; - - /* Highlight fanin and fanout. */ - - for (k = 0; k < type->num_pins; k++) { /* Each pin on a CLB */ - netnum = block[bnum].nets[k]; - - if (netnum == OPEN) - continue; - - iclass = type->pin_class[k]; - - if (type->class_inf[iclass].type == DRIVER) { /* Fanout */ - net_color[netnum] = RED; - for (ipin = 1; ipin <= clb_net[netnum].num_sinks; ipin++) { - fanblk = clb_net[netnum].node_block[ipin]; - block_color[fanblk] = RED; - } - } else { /* This net is fanin to the block. */ - net_color[netnum] = BLUE; - fanblk = clb_net[netnum].node_block[0]; /* DRIVER to net */ - block_color[fanblk] = BLUE; - } - } - - block_color[bnum] = GREEN; /* Selected block. */ - - sprintf(msg, "Block %d (%s) at (%d, %d) selected.", bnum, block[bnum].name, - i, j); - update_message(msg); - drawscreen(); /* Need to erase screen. */ -} - -static void deselect_all(void) { - /* Sets the color of all clbs and nets to the default. */ - - int i; - - /* Create some colour highlighting */ - for (i = 0; i < num_blocks; i++) { - if (block[i].type->index < 3) { - block_color[i] = LIGHTGREY; - } else if (block[i].type->index < 3 + MAX_BLOCK_COLOURS) { - block_color[i] = (enum color_types) (BISQUE + MAX_BLOCK_COLOURS + block[i].type->index - - 3); - } else { - block_color[i] = (enum color_types) (BISQUE + 2 * MAX_BLOCK_COLOURS - 1); - } - } - - for (i = 0; i < num_nets; i++) - net_color[i] = BLACK; - - for (i = 0; i < num_rr_nodes; i++) - rr_node_color[i] = BLACK; -} - -/* UDSD by AY Start */ -static void draw_triangle_along_line(float xend, float yend, float x1, float x2, - float y1, float y2) { - float switch_rad = 0.15; - float xdelta, ydelta; - float magnitude; - float xunit, yunit; - float xbaseline, ybaseline; - t_point poly[3]; - - xdelta = x2 - x1; - ydelta = y2 - y1; - magnitude = sqrt(xdelta * xdelta + ydelta * ydelta); - xunit = xdelta / magnitude; - yunit = ydelta / magnitude; - - poly[0].x = xend + xunit * switch_rad; - poly[0].y = yend + yunit * switch_rad; - xbaseline = xend - xunit * switch_rad; - ybaseline = yend - yunit * switch_rad; - poly[1].x = xbaseline + yunit * switch_rad; - poly[1].y = ybaseline - xunit * switch_rad; - poly[2].x = xbaseline - yunit * switch_rad; - poly[2].y = ybaseline + xunit * switch_rad; - - fillpoly(poly, 3); -} - -static void draw_pin_to_chan_edge(int pin_node, int chan_node) { - - /* This routine draws an edge from the pin_node to the chan_node (CHANX or * - * CHANY). The connection is made to the nearest end of the track instead * - * of perpundicular to the track to symbolize a single-drive connection. * - * If mark_conn is TRUE, draw a box where the pin connects to the track * - * (useful for drawing the rr graph) */ - - /* TODO: Fix this for global routing, currently for detailed only */ - - t_rr_type chan_type; - int grid_x, grid_y, pin_num, chan_xlow, chan_ylow, ioff, height; - float x1, x2, y1, y2; - int start, end, i; - int itrack; - float xend, yend; - float draw_pin_off; - enum e_direction direction; - enum e_side iside; - t_type_ptr type; - - direction = rr_node[chan_node].direction; - grid_x = rr_node[pin_node].xlow; - grid_y = rr_node[pin_node].ylow; - pin_num = rr_node[pin_node].ptc_num; - chan_type = rr_node[chan_node].type; - itrack = rr_node[chan_node].ptc_num; - type = grid[grid_x][grid_y].type; - - ioff = grid[grid_x][grid_y].offset; - /* large block begins at primary tile (offset == 0) */ - grid_y = grid_y - ioff; - height = grid[grid_x][grid_y].type->height; - chan_ylow = rr_node[chan_node].ylow; - chan_xlow = rr_node[chan_node].xlow; - start = -1; - end = -1; - - switch (chan_type) { - - case CHANX: - start = rr_node[chan_node].xlow; - end = rr_node[chan_node].xhigh; - if (is_opin(pin_num, type)) { - if (direction == INC_DIRECTION) { - end = rr_node[chan_node].xlow; - } else if (direction == DEC_DIRECTION) { - start = rr_node[chan_node].xhigh; - } - } - - start = std::max(start, grid_x); - end = std::min(end, grid_x); /* Width is 1 always */ - assert(end >= start); - /* Make sure we are nearby */ - - if ((grid_y + height - 1) == chan_ylow) { - iside = TOP; - ioff = height - 1; - draw_pin_off = pin_size; - } else { - assert((grid_y - 1) == chan_ylow); - - iside = BOTTOM; - ioff = 0; - draw_pin_off = -pin_size; - } - assert(grid[grid_x][grid_y].type->pinloc[ioff][iside][pin_num]); - - get_rr_pin_draw_coords(pin_node, iside, ioff, &x1, &y1); - y1 += draw_pin_off; - - y2 = tile_y[rr_node[chan_node].ylow] + tile_width + 1. + itrack; - x2 = x1; - if (is_opin(pin_num, type)) { - if (direction == INC_DIRECTION) { - x2 = tile_x[rr_node[chan_node].xlow]; - } else if (direction == DEC_DIRECTION) { - x2 = tile_x[rr_node[chan_node].xhigh] + tile_width; - } - } - break; - - case CHANY: - start = rr_node[chan_node].ylow; - end = rr_node[chan_node].yhigh; - if (is_opin(pin_num, type)) { - if (direction == INC_DIRECTION) { - end = rr_node[chan_node].ylow; - } else if (direction == DEC_DIRECTION) { - start = rr_node[chan_node].yhigh; - } - } - - start = std::max(start, grid_y); - end = std::min(end, (grid_y + height - 1)); /* Width is 1 always */ - assert(end >= start); - /* Make sure we are nearby */ - - if ((grid_x) == chan_xlow) { - iside = RIGHT; - draw_pin_off = pin_size; - } else { - assert((grid_x - 1) == chan_xlow); - iside = LEFT; - draw_pin_off = -pin_size; - } - for (i = start; i <= end; i++) { - ioff = i - grid_y; - assert(ioff >= 0 && ioff < type->height); - /* Once we find the location, break out, this will leave ioff pointing - * to the correct offset. If an offset is not found, the assertion after - * this will fail. With the correct routing graph, the assertion will not - * be triggered. This also takes care of connecting a wire once to multiple - * physical pins on the same side. */ - if (grid[grid_x][grid_y].type->pinloc[ioff][iside][pin_num]) { - break; - } - } - assert(grid[grid_x][grid_y].type->pinloc[ioff][iside][pin_num]); - - get_rr_pin_draw_coords(pin_node, iside, ioff, &x1, &y1); - x1 += draw_pin_off; - - x2 = tile_x[chan_xlow] + tile_width + 1 + itrack; - y2 = y1; - if (is_opin(pin_num, type)) { - if (direction == INC_DIRECTION) { - y2 = tile_y[rr_node[chan_node].ylow]; - } else if (direction == DEC_DIRECTION) { - y2 = tile_y[rr_node[chan_node].yhigh] + tile_width; - } - } - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in draw_pin_to_chan_edge: Invalid channel node %d.\n", chan_node); - exit(1); - } - - drawline(x1, y1, x2, y2); - if (direction == BI_DIRECTION || !is_opin(pin_num, type)) { - draw_x(x2, y2, 0.7 * pin_size); - } else { - xend = x2 + (x1 - x2) / 10.; - yend = y2 + (y1 - y2) / 10.; - draw_triangle_along_line(xend, yend, x1, x2, y1, y2); - } -} - -static void draw_pin_to_pin(int opin_node, int ipin_node) { - - /* This routine draws an edge from the opin rr node to the ipin rr node */ - int opin_grid_x, opin_grid_y, opin; - int ipin_grid_x, ipin_grid_y, ipin; - int ofs, pin_ofs; - boolean found; - float x1, x2, y1, y2; - float xend, yend; - enum e_side iside, pin_side; - t_type_ptr type; - - assert(rr_node[opin_node].type == OPIN); - assert(rr_node[ipin_node].type == IPIN); - iside = (enum e_side)0; - x1 = y1 = x2 = y2 = 0; - pin_ofs = 0; - pin_side = TOP; - - /* get opin coordinate */ - opin_grid_x = rr_node[opin_node].xlow; - opin_grid_y = rr_node[opin_node].ylow; - opin_grid_y = opin_grid_y - grid[opin_grid_x][opin_grid_y].offset; - opin = rr_node[opin_node].ptc_num; - type = grid[opin_grid_x][opin_grid_y].type; - - found = FALSE; - for (ofs = 0; ofs < type->height && !found; ++ofs) { - for (iside = (enum e_side)0; iside < 4 && !found; iside = (enum e_side)(iside + 1)) { - /* Find first location of pin */ - if (1 == type->pinloc[ofs][iside][opin]) { - pin_ofs = ofs; - pin_side = iside; - found = TRUE; - } - } - } - assert(found); - get_rr_pin_draw_coords(opin_node, pin_side, pin_ofs, &x1, &y1); - - - /* get ipin coordinate */ - ipin_grid_x = rr_node[ipin_node].xlow; - ipin_grid_y = rr_node[ipin_node].ylow; - ipin_grid_y = ipin_grid_y - grid[ipin_grid_x][ipin_grid_y].offset; - ipin = rr_node[ipin_node].ptc_num; - type = grid[ipin_grid_x][ipin_grid_y].type; - - found = FALSE; - for (ofs = 0; ofs < type->height && !found; ++ofs) { - for (iside = (enum e_side)0; iside < 4 && !found; iside = (enum e_side)(iside + 1)) { - /* Find first location of pin */ - if (1 == type->pinloc[ofs][iside][ipin]) { - pin_ofs = ofs; - pin_side = iside; - found = TRUE; - } - } - } - assert(found); - get_rr_pin_draw_coords(ipin_node, pin_side, pin_ofs, &x2, &y2); - drawline(x1, y1, x2, y2); - xend = x2 + (x1 - x2) / 10.; - yend = y2 + (y1 - y2) / 10.; - draw_triangle_along_line(xend, yend, x1, x2, y1, y2); -} - -/* UDSD by AY End */ diff --git a/vpr7_x2p/vpr/SRC/base/draw.h b/vpr7_x2p/vpr/SRC/base/draw.h deleted file mode 100644 index a92fa1aad..000000000 --- a/vpr7_x2p/vpr/SRC/base/draw.h +++ /dev/null @@ -1,11 +0,0 @@ -void update_screen(int priority, char *msg, enum pic_type pic_on_screen_val, - boolean crit_path_button_enabled); - -void alloc_draw_structs(void); - -void init_draw_coords(float clb_width); - -void set_graphics_state(boolean show_graphics_val, int gr_automode_val, - enum e_route_type route_type); - -void free_draw_structs(void); diff --git a/vpr7_x2p/vpr/SRC/base/easygl_constants.h b/vpr7_x2p/vpr/SRC/base/easygl_constants.h deleted file mode 100644 index 8c0d373b7..000000000 --- a/vpr7_x2p/vpr/SRC/base/easygl_constants.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef EASYGL_CONSTANTS_H -#define EASYGL_CONSTANTS_H - -enum color_types {WHITE, BLACK, DARKGREY, LIGHTGREY, BLUE, GREEN, YELLOW, -CYAN, RED, DARKGREEN, MAGENTA, BISQUE, LIGHTBLUE, THISTLE, PLUM, KHAKI, CORAL, -TURQUOISE, MEDIUMPURPLE, DARKSLATEBLUE, DARKKHAKI, NUM_COLOR}; - -enum line_types {SOLID, DASHED}; - -#define MAXPTS 100 /* Maximum number of points drawable by fillpoly */ - -typedef struct { - float x; - float y; -} t_point; /* Used in calls to fillpoly */ - -#endif // EASYGL_CONSTANTS_H diff --git a/vpr7_x2p/vpr/SRC/base/globals.c b/vpr7_x2p/vpr/SRC/base/globals.c deleted file mode 100644 index f0ef6bc6d..000000000 --- a/vpr7_x2p/vpr/SRC/base/globals.c +++ /dev/null @@ -1,112 +0,0 @@ -/* Define global variables here */ - -#include "vpr_types.h" -#include "globals.h" - - -/******** General global variables ********/ -int Fs_seed = -1; - -int W_seed = -1; -int binary_search = -1; - -float grid_logic_tile_area = 0; -float ipin_mux_trans_size = 0; - -int copy_nb_clusters = 0; - -/* User netlist information begin */ -int num_logical_nets = 0, num_logical_blocks = 0; -int num_p_inputs = 0, num_p_outputs = 0; -struct s_net *vpack_net = NULL; -struct s_logical_block *logical_block = NULL; -char *blif_circuit_name = NULL; -char *default_output_name = NULL; -/* User netlist information end */ - -/******** Clustered netlist to be mapped stuff ********/ - -int num_nets = 0; -struct s_net *clb_net = NULL; - -int num_blocks = 0; -struct s_block *block = NULL; - -int *clb_to_vpack_net_mapping = NULL; /* [0..num_clb_nets - 1] */ -int *vpack_to_clb_net_mapping = NULL; /* [0..num_vpack_nets - 1] */ - -/* This identifies the t_type_ptr of an IO block */ -int num_types = 0; -struct s_type_descriptor *type_descriptors = NULL; - -t_type_ptr IO_TYPE = NULL; -t_type_ptr EMPTY_TYPE = NULL; -t_type_ptr FILL_TYPE = NULL; - -/******** Physical architecture stuff ********/ - -int nx = 0; -int ny = 0; - -/* TRUE if this is a global clb pin -- an input pin to which the netlist can * - * connect global signals, but which does not connect into the normal * - * routing via muxes etc. Marking pins like this (only clocks in my work) * - * stops them from screwing up the input switch pattern in the rr_graph * - * generator and from creating extra switches that the area model would * - * count. */ - -int *chan_width_x = NULL; /* [0..ny] */ -int *chan_width_y = NULL; /* [0..nx] */ - -struct s_grid_tile **grid = NULL; /* [0..(nx+1)][0..(ny+1)] Physical block list */ - -/******** Structures defining the routing ********/ - -/* Linked list start pointers. Define the routing. */ -struct s_trace **trace_head = NULL; /* [0..(num_nets-1)] */ -struct s_trace **trace_tail = NULL; /* [0..(num_nets-1)] */ - -/******** Structures defining the FPGA routing architecture ********/ - -int num_rr_nodes = 0; -t_rr_node *rr_node = NULL; /* [0..(num_rr_nodes-1)] */ -t_ivec ***rr_node_indices = NULL; - -int num_rr_indexed_data = 0; -t_rr_indexed_data *rr_indexed_data = NULL; /* [0..(num_rr_indexed_data-1)] */ - -/* Gives the rr_node indices of net terminals. */ - -int **net_rr_terminals = NULL; /* [0..num_nets-1][0..num_pins-1] */ - -/* Gives information about all the switch types * - * (part of routing architecture, but loaded in read_arch.c */ - -struct s_switch_inf *switch_inf = NULL; /* [0..(det_routing_arch.num_switch-1)] */ - -/* Stores the SOURCE and SINK nodes of all CLBs (not valid for pads). */ - -int **rr_blk_source = NULL; /* [0..(num_blocks-1)][0..(num_class-1)] */ - -/* primiary inputs removed from circuit */ -struct s_linked_vptr *circuit_p_io_removed = NULL; - -/********** Structures representing timing graph information */ -float pb_max_internal_delay = UNDEFINED; /* biggest internal delay of physical block */ -const t_pb_type *pbtype_max_internal_delay = NULL; /* physical block type with highest internal delay */ - -/********** Structures representing the global clock network */ -t_clock_arch * g_clock_arch; - -/* Xifan TANG: FPGA-SPICE and Verilog Generator */ -/* Detailed routing information for each SB and CB */ -t_sb** sb_info = NULL; -t_cb** cbx_info = NULL; -t_cb** cby_info = NULL; - -/* Xifan TANG: detailed runtime statistics */ -float pack_route_time = 0.; - -/* Xifan TANG: clb_to_clb_directs*/ -int num_clb2clb_directs = 0; -t_clb_to_clb_directs* clb2clb_direct = NULL; diff --git a/vpr7_x2p/vpr/SRC/base/globals.h b/vpr7_x2p/vpr/SRC/base/globals.h deleted file mode 100644 index 47e993e76..000000000 --- a/vpr7_x2p/vpr/SRC/base/globals.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - Global variables - - Key global variables that are used everywhere in VPR: - clb_net, vpack_net, block, and logical_block - - These variables represent the user netlist in various stages of the CAD flow: - vpack_net and logical_block for the unclustered netlist pre packing - clb_net and block for the clustered netlist post packing - */ - -#ifndef GLOBALS_H -#define GLOBALS_H - -/******************************************************************** -Checking OS System -********************************************************************/ -/*#if defined(__WIN32__) || defined(__WIN32) || defined(_WIN32) || defined(WIN32) || defined(__TOS_WIN__) || defined(__WINDOWS__) - #ifndef __WIN32__ - #define __WIN32__ - #endif -#else - #ifndef __UNIX__ - #define __UNIX__ - #endif - #include -#endif*/ - -/******************************************************************** - User Netlist Globals - ********************************************************************/ - -/* external-to-complex block nets in the user netlist */ -extern int num_nets; -extern struct s_net *clb_net; - -/* blocks in the user netlist */ -extern int num_blocks; -extern struct s_block *block; - -extern int copy_nb_clusters; - -/******************************************************************** - Physical FPGA architecture globals - *********************************************************************/ - -/* x and y dimensions of the FPGA itself, the core of the FPGA is from [1..nx][1..ny], the I/Os form a perimeter surrounding the core */ -extern int nx, ny; -extern struct s_grid_tile **grid; /* FPGA complex blocks grid [0..nx+1][0..ny+1] */ - -/* Special pointers to identify special blocks on an FPGA: I/Os, unused, and default */ -extern t_type_ptr IO_TYPE; -extern t_type_ptr EMPTY_TYPE; -extern t_type_ptr FILL_TYPE; - -/* type_descriptors are blocks that can be moved by the placer - such as: I/Os, CLBs, memories, multipliers, etc - Different types of physical block are contained in type descriptors - */ -extern int num_types; -extern struct s_type_descriptor *type_descriptors; - -/* name of the blif circuit */ -extern char *blif_circuit_name; -/* default output name */ -extern char *default_output_name; - -/* Default area of a 1x1 logic tile (excludes routing) on the FPGA */ -extern float grid_logic_tile_area; - -/* Area of a mux transistor for the input connection block */ -extern float ipin_mux_trans_size; - -/******************************************************************* - Packing related globals - ********************************************************************/ - -/* Netlist description data structures. */ - -/* User netlist information */ -extern int num_logical_nets, num_logical_blocks; -extern int num_p_inputs, num_p_outputs; -extern struct s_net *vpack_net; -extern struct s_logical_block *logical_block; -extern struct s_subckt *subckt; - -/* primiary inputs removed from circuit */ -extern struct s_linked_vptr *circuit_p_io_removed; - -/* Relationship between external-to-complex block nets and internal-to-complex block nets */ -extern int *clb_to_vpack_net_mapping; /* [0..num_clb_nets - 1] */ -extern int *vpack_to_clb_net_mapping; /* [0..num_vpack_nets - 1] */ - - -/******************************************************************* - Routing related globals - ********************************************************************/ - -/* chan_width_x is the x-directed channel; i.e. between rows */ -extern int *chan_width_x, *chan_width_y; /* numerical form */ - -/* [0..num_nets-1] of linked list start pointers. Defines the routing. */ -extern struct s_trace **trace_head, **trace_tail; - -/* Structures to define the routing architecture of the FPGA. */ -extern int num_rr_nodes; -extern t_rr_node *rr_node; /* [0..num_rr_nodes-1] */ -extern int num_rr_indexed_data; -extern t_rr_indexed_data *rr_indexed_data; /* [0 .. num_rr_indexed_data-1] */ -extern t_ivec ***rr_node_indices; -extern int **net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */ -extern struct s_switch_inf *switch_inf; /* [0..det_routing_arch.num_switch-1] */ -extern int **rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */ - -/* the head pointers of structures that are "freed" and used constantly */ -/*struct s_heap *g_heap_free_head; -struct s_trace *g_trace_free_head; -struct s_linked_f_pointer *g_linked_f_pointer_free_head;*/ - -/******************************************************************* - Timing related globals - ********************************************************************/ - -extern float pb_max_internal_delay; /* biggest internal delay of block */ -extern const t_pb_type *pbtype_max_internal_delay; /* block type with highest internal delay */ - -/******************************************************************* - Clock Network - ********************************************************************/ -extern t_clock_arch * g_clock_arch; - -/* Xifan TANG: FPGA-SPICE and Verilog Generator */ -/* Detailed routing information for each SB and CB */ -extern t_sb** sb_info; -extern t_cb** cbx_info; -extern t_cb** cby_info; - -/* Xifan TANG: detailed runtime statistics */ -extern float pack_route_time; - -/* Xifan TANG: clb_to_clb_directs*/ -extern int num_clb2clb_directs; -extern t_clb_to_clb_directs* clb2clb_direct; - -#endif - diff --git a/vpr7_x2p/vpr/SRC/base/globals_declare.h b/vpr7_x2p/vpr/SRC/base/globals_declare.h deleted file mode 100644 index b74d9ccc6..000000000 --- a/vpr7_x2p/vpr/SRC/base/globals_declare.h +++ /dev/null @@ -1,25 +0,0 @@ -/* Netlist to be placed stuff. */ -int num_nets, num_blocks; -struct s_net *net; -struct s_block *block; -boolean *is_global; - -/* Physical FPGA architecture stuff */ -int nx, ny; - -/* chan_width_x is the x-directed channel; i.e. between rows */ -int *chan_width_x, *chan_width_y; /* numerical form */ -struct s_grid_tile **grid; - -/* [0..num_nets-1] of linked list start pointers. Defines the routing. */ -struct s_trace **trace_head, **trace_tail; - -/* Structures to define the routing architecture of the FPGA. */ -int num_rr_nodes; -t_rr_node *rr_node; /* [0..num_rr_nodes-1] */ -t_ivec ***rr_node_indices; -int num_rr_indexed_data; -t_rr_indexed_data *rr_indexed_data; /* [0 .. num_rr_indexed_data-1] */ -int **net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */ -struct s_switch_inf *switch_inf; /* [0..det_routing_arch.num_switch-1] */ -int **rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */ diff --git a/vpr7_x2p/vpr/SRC/base/graphics.c b/vpr7_x2p/vpr/SRC/base/graphics.c deleted file mode 100755 index 264bb03c2..000000000 --- a/vpr7_x2p/vpr/SRC/base/graphics.c +++ /dev/null @@ -1,3991 +0,0 @@ -/* -* Easygl Version 2.0.1 -* Written by Vaughn Betz at the University of Toronto, Department of * -* Electrical and Computer Engineering, with additions by Paul Leventis * -* and William Chow of Altera, and Guy Lemieux of the University of * -* Brish Columbia. * -* All rights reserved by U of T, etc. * -* * -* You may freely use this graphics interface for non-commercial purposes * -* as long as you leave the author info above in it. -* * -* Revision History: * -* * -* V2.0.1 Sept. 2012 (Vaughn Betz) -* - Fixed a bug in Win32 where postscript output would make the graphics -* crash when you redrew. -* - Made a cleaner makefile to simplify platform selection. -* - Commented and reorganized some of the code. Started cleaning up some of the -* win32 code. Win32 looks inefficient; it is saving and updating graphics contexts -* all the time even though we know when the context is valid vs. not-valid. -* TODO: make win32 work more like X11 (minimize gc updates). -* -* V2.0: Nov. 21, 2011 (Vaughn Betz) -* - Updated example code, and some cleanup and bug fixes to win32 code. -* - Removed some win32 code that had no X11 equivalent or wasn't well -* documented. -* - Used const char * where appropriate to get rid of g++ warnings. -* - Made interface to things like xor drawing more consistent, and added to -* example program. -* - Made a simpler (easygl.cpp) interface to the graphics library for -* use by undergraduate students. -* -* V1.06 : July 23, 2003 : (Guy Lemieux) -* - added some typecasts to cleanly compile with g++ and MS c++ tools -* - if WIN32 not defined, it defines X11 automatically -* - fixed X11 compilation; WIN32 broke some things -* -* V1.05 : July 26, 2001 : (William) * -* - changed keyboard detect function to accept an int (virtual key) * -* * -* V1.04 : June 29, 2001 : (William) * -* - added drawcurve(), fillcurve() using Bezier curves * -* (support WIN32 screen / ps) * -* - added pt on object capability : using a memory buffer to draw an * -* graphics objects, then query if a point fall on the object (bear the * -* object's colour) : object_start(), object_end(), pt_on_object() * -* - added drawellipticarc(), fillellipticarc() * -* - added findfontsize() to help find a pointsize of a given height * -* - extended t_report to keep xleft, xright, ytop, ybot * -* - added update_window() to set the window bb * -* * -* V1.03 : June 18, 2001 : (William) * -* - added change_button_text() * -* * -* V1.02 : June 13, 2001 : (William) * -* - extension to mouse click function : can tell if ctrl/shift keys are * -* pressed * -* * -* V1.01 : June 1, 2001 : (William) * -* - add tooltip support * -* * -* V1.0 : May 14, 2001 : (William) * -* - fixed a problem with line styles, initial release on the internet * -* * -* March 27, 2001 : (William) * -* - added setcolor_by_colorref to make more colors available (in Win32) * -* * -* February 16, 2001 : (William) * -* - added quick zoom using right mouse clicks * -* * -* February 11, 2001 : (William) * -* - can define cleanup(), passed in when calling init_graphics(), and * -* called when shutting down * -* * -* February 1, 2001 : (William) * -* - fix xor mode redraw problem * -* * -* September 19, 2000 : (William) * -* - can define mouse_move callback function * -* - can add separators in between buttons * -* * -* September 8, 2000 : (William) * -* - added result_structure(), * -* - can define background color in init_graphics * -* * -* August 10, 2000 : (William Chow, choww@eecg.utoronto.ca) * -* - Finished all Win32 support functions * -* - use XOR mode for window zooming box * -* - added double buffering feature * -* * -* January 12, 1999: (Paul) * -* - Fixed a bunch of stuff with the Win32 support (memory leaks, etc) * -* - Made the clipping function using the update rectangle for Win32 * -* * -* January 9, 1999: (Paul Leventis, leventi@eecg.utoronto.ca) * -* - Added Win32 support. Should work under Windows98/95/NT 4.0/NT 5.0. * -* - Added a check to deselect_all to determine whether the screen needs to * -* be updated or not. Should elminate flicker from mouse clicks * -* - Added invalidate_screen() call to graphics.c that in turn calls * -* update_screen, so this function was made non-static and added to the * -* header file. This is due to differences in the structure of Win32 * -* windowing apps. * -* - Win32 needs clipping (though done automatically, could be faster) * -* * -* Sept. 19, 1997: Incorporated Zoom Fit code of Haneef Mohammed at * -* Cypress. Makes it easy to zoom to a full view of the graphics. * -* * -* Sept. 11, 1997: Added the create_and destroy_button interface to * -* make it easy to add and destroy buttons from user code. Removed the * -* bnum parameter to the button functions, since it wasn't really needed. * -* * -* June 28, 1997: Added filled arc drawing primitive. Minor modifications * -* to PostScript driver to make the PostScript output slightly smaller. * -* * -* April 15, 1997: Added code to init_graphics so it waits for a window * -* to be exposed before returning. This ensures that users of non- * -* interactive graphics can never draw to a window before it is available. * -* * -* Feb. 24, 1997: Added code so the package will allocate a private * -* colormap if the default colormap doesn't have enough free colours. * -* * -* June 28, 1996: Converted all internal functions in graphics.c to have * -* internal (static) linkage to avoid any conflicts with user routines in * -* the rest of the program. * -* * -* June 12, 1996: Added setfontsize and setlinewidth attributes. Added * -* pre-clipping of objects for speed (and compactness of PS output) when * -* graphics are zoomed in. Rewrote PostScript engine to shrink the output * -* and make it easier to read. Made drawscreen a callback function passed * -* in rather than a global. Graphics attribute calls are more efficient -- * -* they check if they have to change anything before doing it. * -* * -* October 27, 1995: Added the message area, a callback function for * -* interacting with user button clicks, and implemented a workaround for a * -* Sun X Server bug that misdisplays extremely highly zoomed graphics. * -* * -* Jan. 13, 1995: Modified to incorporate PostScript Support. */ - -#ifndef NO_GRAPHICS // Strip everything out and just put in stubs if NO_GRAPHICS defined - -/********************************** - * Common Preprocessor Directives * - **********************************/ - -#define TRUE 1 -#define FALSE 0 - -#include -#include -#include -#include -#include -#include -#include "graphics.h" -using namespace std; - - -#if defined(X11) || defined(WIN32) - -/* Macros for translation from world to PostScript coordinates */ -#define XPOST(worldx) (((worldx)-xleft)*ps_xmult + ps_left) -#define YPOST(worldy) (((worldy)-ybot)*ps_ymult + ps_bot) - -/* Macros to convert from X Windows Internal Coordinates to my * -* World Coordinates. (This macro is used only rarely, so * -* the divides don't hurt speed). */ -#define XTOWORLD(x) (((float) x)*xdiv + xleft) -#define YTOWORLD(y) (((float) y)*ydiv + ytop) - -#ifndef max -#define max(a,b) (((a) > (b))? (a) : (b)) -#endif -#ifndef min -#define min(a,b) ((a) > (b)? (b) : (a)) -#endif - -#define MWIDTH 104 /* width of menu window */ -#define T_AREA_HEIGHT 24 /* Height of text window */ -#define MAX_FONT_SIZE 24 /* Largest point size of text. */ - // Some computers only have up to 24 point -#define PI 3.141592654 - -#define BUTTON_TEXT_LEN 100 -#define BUFSIZE 1000 -#endif - -/********************************************* -* X-Windows Specific Preprocessor Directives * -*********************************************/ -#ifdef X11 - -#include -#include -#include -#include - -/* Uncomment the line below if your X11 header files don't define XPointer */ -/* typedef char *XPointer; */ - -// Really large pixel values cna make some X11 implementations draw crazy things -// (internal overflow in the X11 library). Use these constants to clip. -#define MAXPIXEL 15000 -#define MINPIXEL -15000 - -#endif /* X11 Preprocessor Directives */ - - -/************************************************************* - * Microsoft Windows (WIN32) Specific Preprocessor Directives * - *************************************************************/ -#ifdef WIN32 -#pragma warning(disable : 4996) // Turn off annoying warnings about strcmp. - -#include - -// Lines below are for displaying errors in a message box on windows. -#define SELECT_ERROR() { char msg[BUFSIZE]; sprintf (msg, "Error %i: Couldn't select graphics object on line %d of graphics.c\n", GetLastError(), __LINE__); MessageBox(NULL, msg, NULL, MB_OK); exit(-1); } -#define DELETE_ERROR() { char msg[BUFSIZE]; sprintf (msg, "Error %i: Couldn't delete graphics object on line %d of graphics.c\n", GetLastError(), __LINE__); MessageBox(NULL, msg, NULL, MB_OK); exit(-1); } -#define CREATE_ERROR() { char msg[BUFSIZE]; sprintf (msg, "Error %i: Couldn't create graphics object on line %d of graphics.c\n", GetLastError(), __LINE__); MessageBox(NULL, msg, NULL, MB_OK); exit(-1); } -#define DRAW_ERROR() { char msg[BUFSIZE]; sprintf (msg, "Error %i: Couldn't draw graphics object on line %d of graphics.c\n", GetLastError(), __LINE__); MessageBox(NULL, msg, NULL, MB_OK); exit(-1); } - -/* Avoid funny clipping problems under windows that I suspect are caused by round-off - * in the Win32 libraries. - */ -#define MAXPIXEL 3000 -#define MINPIXEL -3000 - -#define DEGTORAD(x) ((x)/180.*PI) -#define FONTMAG 1.3 -#endif /* Win32 preprocessor Directives */ - - -/************************************************************* - * Common Type Definitions * - *************************************************************/ - -/* Used to define where the output of drawscreen (graphics primitives in the user-controlled - * area) currently goes to: the screen or a postscript file. - */ -typedef enum { - SCREEN = 0, - POSTSCRIPT = 1 -} t_display_type; - - -/* Indicates if this button displays text, a polygon or is just a separator. - */ -typedef enum { - BUTTON_TEXT = 0, - BUTTON_POLY, - BUTTON_SEPARATOR -} t_button_type; - - -/* Structure used to define the buttons on the right hand side of the main window (menu region). - * width, height: button size, in pixels. - * xleft, ytop: coordinates, in pixels, of the top-left corner of the button relative to its - * containing (menu) window. - * fcn: a callback function that is called when the button is pressed. This function takes one - * argument, a function pointer to the routine that can draw the graphics area (user routine). - * win, hwnd: X11 and Win32 data pointer to the window, respectively. - * button_type: indicates if this button displays text, a polygon or is just a separator. - * text: the text to display if this is a text button. - * poly: the polygon (up to 3 points right now) to display if this is a polygon button - * is_pressed: has the button been pressed, and is currently executing its callback? - * is_enabled: can you press this button right now? Visually will look "pushed in" when - * not enabled, and won't respond to clicks. - */ -typedef struct { - int width; - int height; - int xleft; - int ytop; - void (*fcn) (void (*drawscreen) (void)); -#ifdef X11 - Window win; -#else - HWND hwnd; -#endif - t_button_type type; - char text[BUTTON_TEXT_LEN]; - int poly[3][2]; - bool ispressed; - bool enabled; -} t_button; - - -/* Structure used to store overall graphics state variables. - * TODO: Gradually move more file scope variables in here. - * initialized: true if the graphics window & state have been - * created and initialized, false otherwise. - * disp_type: Selects SCREEN or POSTSCRIPT - * background_cindex: index of the window (or page for PS) background colour - */ -typedef struct { - bool initialized; - int disp_type; - int background_cindex; -} t_gl_state; - - -/********************************************************************* - * File scope variables. TODO: group in structs * - *********************************************************************/ - -// Need to initialize graphics_loaded to false, since checking it is -// how we avoid multiple construction or destruction of the graphics -// window. -static t_gl_state gl_state = {false, SCREEN, 0}; - -static const int menu_font_size = 12; /* Font for menus and dialog boxes. */ - -static t_button *button = NULL; /* [0..num_buttons-1] */ -static int num_buttons = 0; /* Number of menu buttons */ - -static int display_width, display_height; /* screen size */ -static int top_width, top_height; /* window size */ -static float xleft, xright, ytop, ybot; /* world coordinates */ -static float saved_xleft, saved_xright, saved_ytop, saved_ybot; - -static float ps_left, ps_right, ps_top, ps_bot; /* Figure boundaries for * -* PostScript output, in PostScript coordinates. */ -static float ps_xmult, ps_ymult; /* Transformation for PostScript. */ -static float xmult, ymult; /* Transformation factors */ -static float xdiv, ydiv; - -static int currentcolor; -static int currentlinestyle; -static int currentlinewidth; -static int currentfontsize; -static e_draw_mode current_draw_mode; - -/* For PostScript output */ -static FILE *ps; - -static int ProceedPressed; - -static char statusMessage[BUFSIZE] = ""; /* User message to display */ - -static bool font_is_loaded[MAX_FONT_SIZE + 1]; -static bool get_keypress_input, get_mouse_move_input; -static const char *ps_cnames[NUM_COLOR] = {"white", "black", "grey55", "grey75", - "blue", "green", "yellow", "cyan", "red", "darkgreen", "magenta", - "bisque", "lightblue", "thistle", "plum", "khaki", "coral", - "turquoise", "mediumpurple", "darkslateblue", "darkkhaki"}; - - -/********************************************* - * Common Subroutine Declarations * - *********************************************/ - -static void *my_malloc(int ibytes); -static void *my_realloc(void *memblk, int ibytes); -static int xcoord (float worldx); -static int ycoord (float worldy); -static void force_setcolor(int cindex); -static void force_setlinestyle(int linestyle); -static void force_setlinewidth(int linewidth); -static void force_setfontsize (int pointsize); -static void load_font(int pointsize); - -static void reset_common_state (); -static void build_default_menu (void); - -/* Function declarations for button responses */ -static void translate_up (void (*drawscreen) (void)); -static void translate_left (void (*drawscreen) (void)); -static void translate_right (void (*drawscreen) (void)); -static void translate_down (void (*drawscreen) (void)); -static void zoom_in (void (*drawscreen) (void)); -static void zoom_out (void (*drawscreen) (void)); -static void zoom_fit (void (*drawscreen) (void)); -static void adjustwin (void (*drawscreen) (void)); -static void postscript (void (*drawscreen) (void)); -static void proceed (void (*drawscreen) (void)); -static void quit (void (*drawscreen) (void)); -static void map_button (int bnum); -static void unmap_button (int bnum); - -#ifdef X11 - -/************************************************* -* X-Windows Specific File-scope Variables * -**************************************************/ -static Display *display; -static int screen_num; -static GC gc, gcxor, gc_menus, current_gc; -static XFontStruct *font_info[MAX_FONT_SIZE+1]; /* Data for each size */ -static Window toplevel, menu, textarea; /* various windows */ -static Colormap private_cmap; /* "None" unless a private cmap was allocated. */ - -/* Color indices passed back from X Windows. */ -static int colors[NUM_COLOR]; - - -/**************************************************** -* X-Windows Specific Subroutine Declarations * -*****************************************************/ - -static Bool test_if_exposed (Display *disp, XEvent *event_ptr, - XPointer dummy); -static void build_textarea (void); -static void drawbut (int bnum); -static int which_button (Window win); - -static void turn_on_off (int pressed); -static void drawmenu(void); - -#endif /* X11 Declarations */ - - - -#ifdef WIN32 - -/***************************************************** - * Microsoft Windows (Win32) File Scope Variables * - *****************************************************/ -static const int win32_line_styles[2] = { PS_SOLID, PS_DASH }; - -static const COLORREF win32_colors[NUM_COLOR] = { RGB(255, 255, 255), -RGB(0, 0, 0), RGB(128, 128, 128), RGB(192, 192, 192), RGB(0, 0, 255), -RGB(0, 255, 0), RGB(255, 255, 0), RGB(0, 255, 255), RGB(255, 0, 0), RGB(0, 128, 0), -RGB(255, 0, 255), RGB(255, 228, 196), RGB(173, 216, 230), RGB(216, 191, 216), RGB(221, 160, 221), -RGB(240, 230, 140), RGB(255, 127, 80), RGB(64, 224, 208), RGB(147, 112, 219), RGB(72, 61, 139), -RGB(189, 183, 107)}; - -static TCHAR szAppName[256], -szGraphicsName[] = TEXT("VPR Graphics"), -szStatusName[] = TEXT("VPR Status"), -szButtonsName[] = TEXT("VPR Buttons"); -static HPEN hGraphicsPen; -static HBRUSH hGraphicsBrush, hGrayBrush; -static HDC hGraphicsDC, hForegroundDC, hBackgroundDC, -hCurrentDC, /* WC : double-buffer */ -hObjtestDC, hAllObjtestDC; /* object test */ - -/* WC */ -static HFONT hGraphicsFont; -static LOGFONT *font_info[MAX_FONT_SIZE+1]; /* Data for each size */ - -/* Handles to the top level window and 3 subwindows. */ -static HWND hMainWnd, hGraphicsWnd, hButtonsWnd, hStatusWnd; - -static int cxClient, cyClient; - -/* These are used for the "Window" graphics button. They keep track of whether we're entering - * the window rectangle to zoom to, etc. - */ -static int windowAdjustFlag = 0, adjustButton = -1; -static RECT adjustRect, updateRect; - -static boolean InEventLoop = FALSE; - -//static HBITMAP buttonImages[4]; - - -/******************************************************************* - * Win32-specific subroutine declarations * - *******************************************************************/ - -/* Callback functions for the top-level window and 3 sub-windows. - * Windows uses an odd mix of events and callbacks, so it needs these. - */ -static LRESULT CALLBACK GraphicsWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam); -static LRESULT CALLBACK StatusWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam); -static LRESULT CALLBACK ButtonsWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam); -static LRESULT CALLBACK MainWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam); - - -// For Win32, need to save pointers to these callback functions at file -// scope, since windows has a bizarre event loop structure where you poll -// for events, but then dispatch the event and get called via a callback -// from windows (GraphicsWND, below). I can't figure out why windows -// does things this way, but it is what makes saving these function pointers -// necessary. VB. - -static void (*mouseclick_ptr)(float x, float y); -static void (*mousemove_ptr)(float x, float y); -static void (*keypress_ptr)(char entered_char); -static void (*drawscreen_ptr)(void); - -static void invalidate_screen(); - -static void reset_win32_state (); -static void win32_drain_message_queue (); - -void drawtoscreen(); -void displaybuffer(); - - -#endif /* Win32 Declarations */ - -/********************************************************* - * Common Subroutine Definitions * - *********************************************************/ - - -/* safer malloc */ -static void *my_malloc(int ibytes) { - void *mem; - - mem = (void*)malloc(ibytes); - if (mem == NULL) { - printf("memory allocation failed!"); - exit(-1); - } - - return mem; -} - -/* safer realloc */ -static void *my_realloc(void *memblk, int ibytes) { - void *mem; - - mem = (void*)realloc(memblk, ibytes); - if (mem == NULL) { - printf("memory allocation failed!"); - exit(-1); - } - - return mem; -} - - -/* Translates from my internal coordinates to real-world coordinates * -* in the x direction. Add 0.5 at end for extra half-pixel accuracy. */ -static int xcoord (float worldx) -{ - int winx; - - winx = (int) ((worldx-xleft)*xmult + 0.5); - - /* Avoids overflow in the Window routines. This will allow horizontal * - * and vertical lines to be drawn correctly regardless of zooming, but * - * will cause diagonal lines that go way off screen to change their * - * slope as you zoom in. The only way I can think of to completely fix * - * this problem is to do all the clipping in advance in floating point, * - * then convert to integers and call Windows. This is a lot of extra * - * coding, and means that coordinates will be clipped twice, even though * - * this "Super Zoom" problem won't occur unless users zoom way in on * - * the graphics. */ - - winx = max (winx, MINPIXEL); - winx = min (winx, MAXPIXEL); - - return (winx); -} - - -/* Translates from my internal coordinates to real-world coordinates * -* in the y direction. Add 0.5 at end for extra half-pixel accuracy. */ -static int ycoord (float worldy) -{ - int winy; - - winy = (int) ((worldy-ytop)*ymult + 0.5); - - /* Avoid overflow in the X/Win32 Window routines. */ - winy = max (winy, MINPIXEL); - winy = min (winy, MAXPIXEL); - - return (winy); -} - - -#ifdef WIN32 -static void invalidate_screen(void) -{ -/* Tells the graphics engine to redraw the graphics display since information has changed */ - - if(!InvalidateRect(hGraphicsWnd, NULL, FALSE)) - DRAW_ERROR(); - if(!UpdateWindow(hGraphicsWnd)) - DRAW_ERROR(); -} -#endif - -/* Sets the current graphics context colour to cindex, regardless of whether we think it is - * needed or not. - */ -static void force_setcolor (int cindex) -{ - currentcolor = cindex; - - if (gl_state.disp_type == SCREEN) { -#ifdef X11 - XSetForeground (display, current_gc, colors[cindex]); -#else /* Win32 */ - int win_linestyle; - LOGBRUSH lb; - lb.lbStyle = BS_SOLID; - lb.lbColor = win32_colors[cindex]; - lb.lbHatch = (LONG)NULL; - win_linestyle = win32_line_styles[currentlinestyle]; - - if(!DeleteObject(hGraphicsPen)) - DELETE_ERROR(); - - int linewidth = max (currentlinewidth, 1); // Win32 won't draw 0 width dashed lines. - hGraphicsPen = ExtCreatePen(PS_GEOMETRIC | win_linestyle | - PS_ENDCAP_FLAT, linewidth, &lb, (LONG)NULL, NULL); - if(!hGraphicsPen) - CREATE_ERROR(); - - if(!DeleteObject(hGraphicsBrush)) - DELETE_ERROR(); - hGraphicsBrush = CreateSolidBrush(win32_colors[currentcolor]); - if(!hGraphicsBrush) - CREATE_ERROR(); -#endif - } - else { - fprintf (ps,"%s\n", ps_cnames[cindex]); - } -} - - -/* Sets the current graphics context colour to cindex if it differs from the old colour */ -void setcolor (int cindex) -{ - if (currentcolor != cindex) - force_setcolor (cindex); - -} - - -/* Sets the current graphics context color to the index that corresponds to the - * string name passed in. Slower, but maybe more convenient for simple - * client code. - */ -void setcolor (string cname) { - int icolor = -1; - for (int i = 0; i < NUM_COLOR; i++) { - if (cname == ps_cnames[i]) { - icolor = i; - break; - } - } - if (icolor == -1) { - cout << "Error: unknown color " << cname << endl; - } - else { - setcolor (icolor); - } -} - -int getcolor() { - return currentcolor; -} - -/* Sets the current linestyle to linestyle in the graphics context. - * Note SOLID is 0 and DASHED is 1 for linestyle. - */ -static void force_setlinestyle (int linestyle) -{ - currentlinestyle = linestyle; - - if (gl_state.disp_type == SCREEN) { - -#ifdef X11 - static int x_vals[2] = {LineSolid, LineOnOffDash}; - XSetLineAttributes (display, current_gc, currentlinewidth, x_vals[linestyle], - CapButt, JoinMiter); -#else // Win32 - LOGBRUSH lb; - lb.lbStyle = BS_SOLID; - lb.lbColor = win32_colors[currentcolor]; - lb.lbHatch = (LONG)NULL; - int win_linestyle = win32_line_styles[linestyle]; - - if(!DeleteObject(hGraphicsPen)) - DELETE_ERROR(); - int linewidth = max (currentlinewidth, 1); // Win32 won't draw 0 width dashed lines. - hGraphicsPen = ExtCreatePen(PS_GEOMETRIC | win_linestyle | - PS_ENDCAP_FLAT, linewidth, &lb, (LONG)NULL, NULL); - if(!hGraphicsPen) - CREATE_ERROR(); -#endif - } - - else { - if (linestyle == SOLID) - fprintf (ps,"linesolid\n"); - else if (linestyle == DASHED) - fprintf (ps, "linedashed\n"); - else { - printf ("Error: invalid linestyle: %d\n", linestyle); - exit (1); - } - } -} - - -/* Change the linestyle in the graphics context only if it differs from the current - * linestyle. - */ -void setlinestyle (int linestyle) -{ - if (linestyle != currentlinestyle) - force_setlinestyle (linestyle); -} - - -/* Sets current linewidth in the graphics context. - * linewidth should be greater than or equal to 0 to make any sense. - */ -static void force_setlinewidth (int linewidth) -{ - currentlinewidth = linewidth; - - if (gl_state.disp_type == SCREEN) { - -#ifdef X11 - static int x_vals[2] = {LineSolid, LineOnOffDash}; - XSetLineAttributes (display, current_gc, linewidth, x_vals[currentlinestyle], - CapButt, JoinMiter); -#else /* Win32 */ - LOGBRUSH lb; - lb.lbStyle = BS_SOLID; - lb.lbColor = win32_colors[currentcolor]; - lb.lbHatch = (LONG)NULL; - int win_linestyle = win32_line_styles[currentlinestyle]; - - if(!DeleteObject(hGraphicsPen)) - DELETE_ERROR(); - if (linewidth == 0) - linewidth = 1; // Win32 won't draw dashed 0 width lines. - hGraphicsPen = ExtCreatePen(PS_GEOMETRIC | win_linestyle | - PS_ENDCAP_FLAT, linewidth, &lb, (LONG)NULL, NULL); - if(!hGraphicsPen) - CREATE_ERROR(); -#endif - } - - else { - fprintf(ps,"%d setlinewidth\n", linewidth); - } -} - - -/* Sets the linewidth in the grahpics context, if it differs from the current value. - */ -void setlinewidth (int linewidth) -{ - if (linewidth != currentlinewidth) - force_setlinewidth (linewidth); -} - - -/* Force the selected fontsize to be applied to the graphics context, - * whether or not it appears to match the current fontsize. This is necessary - * when switching between postscript and window out, for example. - * Valid point sizes are between 1 and MAX_FONT_SIZE. - */ -static void force_setfontsize (int pointsize) -{ - - if (pointsize < 1) - pointsize = 1; -#ifdef WIN32 - pointsize = (int)((float)pointsize * FONTMAG); -#endif - if (pointsize > MAX_FONT_SIZE) - pointsize = MAX_FONT_SIZE; - - currentfontsize = pointsize; - - if (gl_state.disp_type == SCREEN) { - load_font (pointsize); -#ifdef X11 - XSetFont(display, current_gc, font_info[pointsize]->fid); -#else /* Win32 */ - if(!DeleteObject(hGraphicsFont)) - DELETE_ERROR(); - hGraphicsFont = CreateFontIndirect(font_info[pointsize]); - if(!hGraphicsFont) - CREATE_ERROR(); - if(!SelectObject(hGraphicsDC, hGraphicsFont) ) - SELECT_ERROR(); - -#endif - } - - else { - /* PostScript: set up font and centering function */ - fprintf(ps,"%d setfontsize\n",pointsize); - } -} - - -/* For efficiency, this routine doesn't do anything if no change is - * implied. If you want to force the graphics context or PS file - * to have font info set, call force_setfontsize (this is necessary - * in initialization and X11 / Postscript switches). - */ -void setfontsize (int pointsize) -{ - - if (pointsize != currentfontsize) - force_setfontsize (pointsize); -} - - -/* Puts a triangle in the poly array for button[bnum]. Haven't made this work for - * win32 yet and instead put "U", "D" excetra on the arrow buttons. - * VB To-do: make work for win32 someday. - */ -#ifdef X11 -static void setpoly (int bnum, int xc, int yc, int r, float theta) -{ - int i; - - button[bnum].type = BUTTON_POLY; - for (i=0;i<3;i++) { - button[bnum].poly[i][0] = (int) (xc + r*cos(theta) + 0.5); - button[bnum].poly[i][1] = (int) (yc + r*sin(theta) + 0.5); - theta += (float)(2*PI/3); - } -} -#endif // X11 - - -/* Maps a button onto the screen and set it up for input, etc. */ -static void map_button (int bnum) -{ - button[bnum].ispressed = 0; - - if (button[bnum].type != BUTTON_SEPARATOR) { -#ifdef X11 - button[bnum].win = XCreateSimpleWindow(display,menu, - button[bnum].xleft, button[bnum].ytop, button[bnum].width, - button[bnum].height, 0, colors[WHITE], colors[LIGHTGREY]); - XMapWindow (display, button[bnum].win); - XSelectInput (display, button[bnum].win, ButtonPressMask); -#else - button[bnum].hwnd = CreateWindow( TEXT("button"), TEXT(button[bnum].text), - WS_CHILD | WS_VISIBLE | BS_PUSHBUTTON, button[bnum].xleft, button[bnum].ytop, - button[bnum].width, button[bnum].height, hButtonsWnd, (HMENU)(200+bnum), - (HINSTANCE) GetWindowLong(hMainWnd, GWL_HINSTANCE), NULL); - if(!InvalidateRect(hButtonsWnd, NULL, TRUE)) - DRAW_ERROR(); - if(!UpdateWindow(hButtonsWnd)) - DRAW_ERROR(); -#endif - } - else { // Separator, not a button. -#ifdef X11 - button[bnum].win = -1; -#else // WIN32 - button[bnum].hwnd = NULL; - if(!InvalidateRect(hButtonsWnd, NULL, TRUE)) - DRAW_ERROR(); - if(!UpdateWindow(hButtonsWnd)) - DRAW_ERROR(); -#endif - } -} - - -static void unmap_button (int bnum) -{ - /* Unmaps (removes) a button from the screen. */ - if (button[bnum].type != BUTTON_SEPARATOR) { -#ifdef X11 - XUnmapWindow (display, button[bnum].win); -#else - if(!DestroyWindow(button[bnum].hwnd)) - DRAW_ERROR(); - if(!InvalidateRect(hButtonsWnd, NULL, TRUE)) - DRAW_ERROR(); - if(!UpdateWindow(hButtonsWnd)) - DRAW_ERROR(); -#endif - } -} - - -/* Creates a new button below the button containing prev_button_text. * -* The text and button function are set according to button_text and * -* button_func, respectively. */ -void create_button (const char *prev_button_text , const char *button_text, - void (*button_func) (void (*drawscreen) (void))) -{ - int i, bnum, space, bheight; - t_button_type button_type = BUTTON_TEXT; - - space = 8; - - /* Only allow new buttons that are text or separator (not poly) types. - * They can also only go after buttons that are text buttons. - */ - - bnum = -1; - - for (i=0; i < num_buttons;i++) { - if (button[i].type == BUTTON_TEXT && - strcmp (button[i].text, prev_button_text) == 0) { - bnum = i + 1; - break; - } - } - - if (bnum == -1) { - printf ("Error in create_button: button with text %s not found.\n", - prev_button_text); - exit (1); - } - - button = (t_button *) my_realloc (button, (num_buttons+1) * sizeof (t_button)); - /* NB: Requirement that you specify the button that this button goes under * - * guarantees that button[num_buttons-2] exists and is a text button. */ - - /* Special string to make a separator. */ - if (!strncmp(button_text, "---", 3)) { - bheight = 2; - button_type = BUTTON_SEPARATOR; - } - else - bheight = 26; - - for (i=num_buttons;i>bnum;i--) { - button[i].xleft = button[i-1].xleft; - button[i].ytop = button[i-1].ytop + bheight + space; - button[i].height = button[i-1].height; - button[i].width = button[i-1].width; - button[i].type = button[i-1].type; - strcpy (button[i].text, button[i-1].text); - button[i].fcn = button[i-1].fcn; - button[i].ispressed = button[i-1].ispressed; - button[i].enabled = button[i-1].enabled; - unmap_button (i-1); - } - - i = bnum; - button[i].xleft = 6; - button[i].ytop = button[i-1].ytop + button[i-1].height + space; - button[i].height = bheight; - button[i].width = 90; - button[i].type = button_type; - strncpy (button[i].text, button_text, BUTTON_TEXT_LEN); - button[i].fcn = button_func; - button[i].ispressed = false; - button[i].enabled = true; - - num_buttons++; - - for (i = 0; i use defaults. */ - current_gc = gc = XCreateGC(display, toplevel, valuemask, &values); - gc_menus = XCreateGC(display, toplevel, valuemask, &values); - - /* Create XOR graphics context for Rubber Banding */ - values.function = GXxor; - values.foreground = colors[cindex]; - gcxor = XCreateGC(display, toplevel, (GCFunction | GCForeground), - &values); - - /* specify font for menus. */ - load_font(menu_font_size); - XSetFont(display, gc_menus, font_info[menu_font_size]->fid); - - /* Set drawing defaults for user-drawable area. Use whatever the * - * initial values of the current stuff was set to. */ - force_setfontsize(currentfontsize); - force_setcolor (currentcolor); - force_setlinestyle (currentlinestyle); - force_setlinewidth (currentlinewidth); - - // Need a non-const name to pass to XStringListTo... - // (even though X11 won't change it). - char *window_name_copy = (char *) my_malloc (BUFSIZE * sizeof (char)); - strncpy (window_name_copy, window_name, BUFSIZE); - XStringListToTextProperty(&window_name_copy, 1, &windowName); - free (window_name_copy); - window_name_copy = NULL; - - XSetWMName (display, toplevel, &windowName); - /* XSetWMIconName (display, toplevel, &windowName); */ - - /* XStringListToTextProperty copies the window_name string into * - * windowName.value. Free this memory now. */ - - free (windowName.value); - - XMapWindow (display, toplevel); - build_textarea (); - build_default_menu (); - - /* The following is completely unnecessary if the user is using the * - * interactive (event_loop) graphics. It waits for the first Expose * - * event before returning so that I can tell the window manager has got * - * the top-level window up and running. Thus the user can start drawing * - * into this window immediately, and there's no danger of the window not * - * being ready and output being lost. */ - XPeekIfEvent (display, &event, test_if_exposed, NULL); - -#else /* WIN32 */ - WNDCLASS wndclass; - HINSTANCE hInstance = GetModuleHandle(NULL); - int x, y; - LOGBRUSH lb; - lb.lbStyle = BS_SOLID; - lb.lbColor = win32_colors[currentcolor]; - lb.lbHatch = (LONG)NULL; - x = 0; - y = 0; - - /* get screen size from display structure macro */ - display_width = GetSystemMetrics( SM_CXSCREEN ); - if (!(display_width)) - CREATE_ERROR(); - display_height = GetSystemMetrics( SM_CYSCREEN ); - if (!(display_height)) - CREATE_ERROR(); - top_width = 2*display_width/3; - top_height = 4*display_height/5; - - /* Grab the Application name */ - wsprintf(szAppName, TEXT(window_name)); - - //hGraphicsPen = CreatePen(win32_line_styles[SOLID], 1, win32_colors[BLACK]); - hGraphicsPen = ExtCreatePen(PS_GEOMETRIC | win32_line_styles[currentlinestyle] | - PS_ENDCAP_FLAT, 1, &lb, (LONG)NULL, NULL); - if(!hGraphicsPen) - CREATE_ERROR(); - hGraphicsBrush = CreateSolidBrush(win32_colors[DARKGREY]); - if(!hGraphicsBrush) - CREATE_ERROR(); - hGrayBrush = CreateSolidBrush(win32_colors[LIGHTGREY]); - if(!hGrayBrush) - CREATE_ERROR(); - - load_font (currentfontsize); - hGraphicsFont = CreateFontIndirect(font_info[currentfontsize]); - if (!hGraphicsFont) - CREATE_ERROR(); - - /* Register the Main Window class */ - wndclass.style = CS_HREDRAW | CS_VREDRAW | CS_OWNDC; - wndclass.lpfnWndProc = MainWND; - wndclass.cbClsExtra = 0; - wndclass.cbWndExtra = 0; - wndclass.hInstance = hInstance; - wndclass.hIcon = LoadIcon (NULL, IDI_APPLICATION); - wndclass.hCursor = LoadCursor( NULL, IDC_ARROW); - wndclass.hbrBackground = (HBRUSH) CreateSolidBrush(win32_colors[cindex]); - wndclass.lpszMenuName = NULL; - wndclass.lpszClassName = szAppName; - - if (!RegisterClass(&wndclass)) { - printf ("Error code: %d\n", GetLastError()); - MessageBox(NULL, TEXT("Initialization of Windows graphics (init_graphics) failed."), - szAppName, MB_ICONERROR); - exit(-1); - } - - /* Register the Graphics Window class */ - wndclass.lpfnWndProc = GraphicsWND; - wndclass.hIcon = NULL; - wndclass.lpszClassName = szGraphicsName; - - if(!RegisterClass(&wndclass)) - DRAW_ERROR(); - - /* Register the Status Window class */ - wndclass.lpfnWndProc = StatusWND; - wndclass.hIcon = NULL; - wndclass.lpszClassName = szStatusName; - wndclass.hbrBackground = hGrayBrush; - - if(!RegisterClass(&wndclass)) - DRAW_ERROR(); - - /* Register the Buttons Window class */ - wndclass.lpfnWndProc = ButtonsWND; - wndclass.hIcon = NULL; - wndclass.lpszClassName = szButtonsName; - wndclass.hbrBackground = hGrayBrush; - - if (!RegisterClass(&wndclass)) - DRAW_ERROR(); - - hMainWnd = CreateWindow(szAppName, TEXT(window_name), - WS_OVERLAPPEDWINDOW, x, y, top_width, top_height, - NULL, NULL, hInstance, NULL); - - if(!hMainWnd) - DRAW_ERROR(); - - /* Set drawing defaults for user-drawable area. Use whatever the * - * initial values of the current stuff was set to. */ - - if (ShowWindow(hMainWnd, SW_SHOWNORMAL)) - DRAW_ERROR(); - build_default_menu(); - if (!UpdateWindow(hMainWnd)) - DRAW_ERROR(); - win32_drain_message_queue (); -#endif - gl_state.initialized = true; -} - - -static void reset_common_state () { - currentcolor = BLACK; - currentlinestyle = SOLID; - currentlinewidth = 0; - currentfontsize = 12; - current_draw_mode = DRAW_NORMAL; - - for (int i=0;i<=MAX_FONT_SIZE;i++) - font_is_loaded[i] = false; /* No fonts loaded yet. */ - - ProceedPressed = false; - get_keypress_input = false; - get_mouse_move_input = false; -} - - -static void -update_transform (void) -{ -/* Set up the factors for transforming from the user world to X Windows * - * coordinates. */ - - float mult, y1, y2, x1, x2; - - /* X Window coordinates go from (0,0) to (width-1,height-1) */ - xmult = (top_width - 1 - MWIDTH) / (xright - xleft); - ymult = (top_height - 1 - T_AREA_HEIGHT)/ (ybot - ytop); - - /* Need to use same scaling factor to preserve aspect ratio */ - if (fabs(xmult) <= fabs(ymult)) { - mult = (float)(fabs(ymult/xmult)); - y1 = ytop - (ybot-ytop)*(mult-1)/2; - y2 = ybot + (ybot-ytop)*(mult-1)/2; - ytop = y1; - ybot = y2; - } - else { - mult = (float)(fabs(xmult/ymult)); - x1 = xleft - (xright-xleft)*(mult-1)/2; - x2 = xright + (xright-xleft)*(mult-1)/2; - xleft = x1; - xright = x2; - } - xmult = (top_width - 1 - MWIDTH) / (xright - xleft); - ymult = (top_height - 1 - T_AREA_HEIGHT)/ (ybot - ytop); - - xdiv = 1/xmult; - ydiv = 1/ymult; -} - - -static void -update_ps_transform (void) -{ - -/* Postscript coordinates start at (0,0) for the lower left hand corner * -* of the page and increase upwards and to the right. For 8.5 x 11 * -* sheet, coordinates go from (0,0) to (612,792). Spacing is 1/72 inch.* -* I'm leaving a minimum of half an inch (36 units) of border around * - * each edge. */ - - float ps_width, ps_height; - - ps_width = 540.; /* 72 * 7.5 */ - ps_height = 720.; /* 72 * 10 */ - - ps_xmult = ps_width / (xright - xleft); - ps_ymult = ps_height / (ytop - ybot); - /* Need to use same scaling factor to preserve aspect ratio. * - * I show exactly as much on paper as the screen window shows, * - * or the user specifies. */ - if (fabs(ps_xmult) <= fabs(ps_ymult)) { - ps_left = 36.; - ps_right = (float)(36. + ps_width); - ps_bot = (float)(396. - fabs(ps_xmult * (ytop - ybot))/2); - ps_top = (float)(396. + fabs(ps_xmult * (ytop - ybot))/2); - /* Maintain aspect ratio but watch signs */ - ps_ymult = (ps_xmult*ps_ymult < 0) ? -ps_xmult : ps_xmult; - } - else { - ps_bot = 36.; - ps_top = (float)(36. + ps_height); - ps_left = (float)(306. - fabs(ps_ymult * (xright - xleft))/2); - ps_right = (float)(306. + fabs(ps_ymult * (xright - xleft))/2); - /* Maintain aspect ratio but watch signs */ - ps_xmult = (ps_xmult*ps_ymult < 0) ? -ps_ymult : ps_ymult; - } -} - - -/* The program's main event loop. Must be passed a user routine -* drawscreen which redraws the screen. It handles all window resizing -* zooming etc. itself. If the user clicks a mousebutton in the graphics -* (toplevel) area, the act_on_mousebutton routine passed in is called. -*/ -void -event_loop (void (*act_on_mousebutton)(float x, float y), - void (*act_on_mousemove)(float x, float y), - void (*act_on_keypress)(char key_pressed), - void (*drawscreen) (void)) -{ -#ifdef X11 - XEvent report; - int bnum; - float x, y; - -#define OFF 1 -#define ON 0 - - turn_on_off (ON); - while (1) { - XNextEvent (display, &report); - switch (report.type) { - case Expose: -#ifdef VERBOSE - printf("Got an expose event.\n"); - printf("Count is: %d.\n",report.xexpose.count); - printf("Window ID is: %d.\n",report.xexpose.window); -#endif - if (report.xexpose.count != 0) - break; - if (report.xexpose.window == menu) - drawmenu(); - else if (report.xexpose.window == toplevel) - drawscreen(); - else if (report.xexpose.window == textarea) - draw_message(); - break; - case ConfigureNotify: - top_width = report.xconfigure.width; - top_height = report.xconfigure.height; - update_transform(); - drawmenu(); - draw_message(); -#ifdef VERBOSE - printf("Got a ConfigureNotify.\n"); - printf("New width: %d New height: %d.\n",top_width,top_height); -#endif - break; - case ButtonPress: -#ifdef VERBOSE - printf("Got a buttonpress.\n"); - printf("Window ID is: %d.\n",report.xbutton.window); -#endif - if (report.xbutton.window == toplevel) { - x = XTOWORLD(report.xbutton.x); - y = YTOWORLD(report.xbutton.y); - act_on_mousebutton (x, y); - } - else { /* A menu button was pressed. */ - bnum = which_button(report.xbutton.window); -#ifdef VERBOSE - printf("Button number is %d\n",bnum); -#endif - if (button[bnum].enabled) { - button[bnum].ispressed = 1; - drawbut(bnum); - XFlush(display); /* Flash the button */ - button[bnum].fcn (drawscreen); - button[bnum].ispressed = 0; - drawbut(bnum); - if (button[bnum].fcn == proceed) { - turn_on_off(OFF); - flushinput (); - return; /* Rather clumsy way of returning * - * control to the simulator */ - } - } - } - break; - case MotionNotify: -#ifdef VERBOSE - printf("Got a MotionNotify Event.\n"); - printf("x: %d y: %d\n",report.xmotion.x,report.xmotion.y); -#endif - if (get_mouse_move_input && - report.xmotion.x <= top_width-MWIDTH && - report.xmotion.y <= top_height-T_AREA_HEIGHT) - act_on_mousemove(XTOWORLD(report.xmotion.x), YTOWORLD(report.xmotion.y)); - break; - case KeyPress: -#ifdef VERBOSE - printf("Got a KeyPress Event.\n"); -#endif - if (get_keypress_input) - { - char keyb_buffer[20]; - XComposeStatus composestatus; - KeySym keysym; - int length, max_bytes; - - max_bytes = 1; - - length = XLookupString( &report.xkey, keyb_buffer, max_bytes, &keysym, - &composestatus ); - - keyb_buffer[length] = '\0'; /* terminating NULL */ - act_on_keypress(keyb_buffer[0]); - } - - break; - } - } -#else /* Win32 */ - MSG msg; - - mouseclick_ptr = act_on_mousebutton; - mousemove_ptr = act_on_mousemove; - keypress_ptr = act_on_keypress; - drawscreen_ptr = drawscreen; - ProceedPressed = FALSE; - InEventLoop = TRUE; - - invalidate_screen(); - - while(!ProceedPressed && GetMessage(&msg, NULL, 0, 0)) { - //TranslateMessage(&msg); - if (msg.message == WM_CHAR) { // only the top window can get keyboard events - msg.hwnd = hMainWnd; - } - DispatchMessage(&msg); - } - InEventLoop = FALSE; -#endif -} - -void -clearscreen (void) -{ - int savecolor; - if (gl_state.disp_type == SCREEN) { -#ifdef X11 - XClearWindow (display, toplevel); -#else /* Win32 */ - savecolor = currentcolor; - setcolor(gl_state.background_cindex); - fillrect (xleft, ytop, xright, ybot); - setcolor(savecolor); -#endif - } - else { // Postscript - /* erases current page. Don't use erasepage, since this will erase * - * everything, (even stuff outside the clipping path) causing * - * problems if this picture is incorporated into a larger document. */ - savecolor = currentcolor; - setcolor (gl_state.background_cindex); - fprintf(ps,"clippath fill\n\n"); - setcolor (savecolor); - } -} - -/* Return 1 if I can quarantee no part of this rectangle will * -* lie within the user drawing area. Otherwise return 0. * -* Note: this routine is only used to help speed (and to shrink ps * -* files) -- it will be highly effective when the graphics are zoomed * -* in and lots are off-screen. I don't have to pre-clip for * -* correctness. */ -static int -rect_off_screen (float x1, float y1, float x2, float y2) -{ - - float xmin, xmax, ymin, ymax; - - xmin = min (xleft, xright); - if (x1 < xmin && x2 < xmin) - return (1); - - xmax = max (xleft, xright); - if (x1 > xmax && x2 > xmax) - return (1); - - ymin = min (ytop, ybot); - if (y1 < ymin && y2 < ymin) - return (1); - - ymax = max (ytop, ybot); - if (y1 > ymax && y2 > ymax) - return (1); - - return (0); -} - -void -drawline (float x1, float y1, float x2, float y2) -{ -/* Draw a line from (x1,y1) to (x2,y2) in the user-drawable area. * - * Coordinates are in world (user) space. */ - -#ifdef WIN32 - HPEN hOldPen; -#endif - - if (rect_off_screen(x1,y1,x2,y2)) - return; - - if (gl_state.disp_type == SCREEN) { -#ifdef X11 - /* Xlib.h prototype has x2 and y1 mixed up. */ - XDrawLine(display, toplevel, current_gc, xcoord(x1), ycoord(y1), xcoord(x2), ycoord(y2)); -#else /* Win32 */ - hOldPen = (HPEN)SelectObject(hGraphicsDC, hGraphicsPen); - if(!(hOldPen)) - SELECT_ERROR(); - if (!BeginPath(hGraphicsDC)) - DRAW_ERROR(); - if(!MoveToEx (hGraphicsDC, xcoord(x1), ycoord(y1), NULL)) - DRAW_ERROR(); - if(!LineTo (hGraphicsDC, xcoord(x2), ycoord(y2))) - DRAW_ERROR(); - if (!EndPath(hGraphicsDC)) - DRAW_ERROR(); - if (!StrokePath(hGraphicsDC)) - DRAW_ERROR(); - if(!SelectObject(hGraphicsDC, hOldPen)) - SELECT_ERROR(); -#endif - } - else { - fprintf(ps,"%.2f %.2f %.2f %.2f drawline\n",XPOST(x1),YPOST(y1), - XPOST(x2),YPOST(y2)); - } -} - -/* (x1,y1) and (x2,y2) are diagonally opposed corners, in world coords. */ -void -drawrect (float x1, float y1, float x2, float y2) -{ - int xw1, yw1, xw2, yw2; -#ifdef WIN32 - HPEN hOldPen; - HBRUSH hOldBrush; -#else - unsigned int width, height; - int xl, yt; -#endif - - if (rect_off_screen(x1,y1,x2,y2)) - return; - - if (gl_state.disp_type == SCREEN) { - /* translate to X Windows calling convention. */ - xw1 = xcoord(x1); - xw2 = xcoord(x2); - yw1 = ycoord(y1); - yw2 = ycoord(y2); -#ifdef X11 - xl = min(xw1,xw2); - yt = min(yw1,yw2); - width = abs (xw1-xw2); - height = abs (yw1-yw2); - XDrawRectangle(display, toplevel, current_gc, xl, yt, width, height); -#else /* Win32 */ - if(xw1 > xw2) { - int temp = xw1; - xw1 = xw2; - xw2 = temp; - } - if(yw1 > yw2) { - int temp = yw1; - yw1 = yw2; - yw2 = temp; - } - - hOldPen = (HPEN)SelectObject(hGraphicsDC, hGraphicsPen); - if(!(hOldPen)) - SELECT_ERROR(); - hOldBrush = (HBRUSH)SelectObject(hGraphicsDC, GetStockObject(NULL_BRUSH)); - if(!(hOldBrush)) - SELECT_ERROR(); - if(!Rectangle(hGraphicsDC, xw1, yw1, xw2, yw2)) - DRAW_ERROR(); - if(!SelectObject(hGraphicsDC, hOldPen)) - SELECT_ERROR(); - if(!SelectObject(hGraphicsDC, hOldBrush)) - SELECT_ERROR(); -#endif - - } - else { - fprintf(ps,"%.2f %.2f %.2f %.2f drawrect\n",XPOST(x1),YPOST(y1), - XPOST(x2),YPOST(y2)); - } -} - - -/* (x1,y1) and (x2,y2) are diagonally opposed corners in world coords. */ -void -fillrect (float x1, float y1, float x2, float y2) -{ - int xw1, yw1, xw2, yw2; -#ifdef WIN32 - HPEN hOldPen; - HBRUSH hOldBrush; -#else - unsigned int width, height; - int xl, yt; -#endif - - if (rect_off_screen(x1,y1,x2,y2)) - return; - - if (gl_state.disp_type == SCREEN) { - /* translate to X Windows calling convention. */ - xw1 = xcoord(x1); - xw2 = xcoord(x2); - yw1 = ycoord(y1); - yw2 = ycoord(y2); -#ifdef X11 - xl = min(xw1,xw2); - yt = min(yw1,yw2); - width = abs (xw1-xw2); - height = abs (yw1-yw2); - XFillRectangle(display, toplevel, current_gc, xl, yt, width, height); -#else /* Win32 */ - if(xw1 > xw2) { - int temp = xw1; - xw1 = xw2; - xw2 = temp; - } - if(yw1 > yw2) { - int temp = yw1; - yw1 = yw2; - yw2 = temp; - } - - hOldPen = (HPEN)SelectObject(hGraphicsDC, hGraphicsPen); - if(!(hOldPen)) - SELECT_ERROR(); - hOldBrush = (HBRUSH)SelectObject(hGraphicsDC, hGraphicsBrush); - if(!(hOldBrush)) - SELECT_ERROR(); - if(!Rectangle(hGraphicsDC, xw1, yw1, xw2, yw2)) - DRAW_ERROR(); - if(!SelectObject(hGraphicsDC, hOldPen)) - SELECT_ERROR(); - if(!SelectObject(hGraphicsDC, hOldBrush)) - SELECT_ERROR(); -#endif - } - else { - fprintf(ps,"%.2f %.2f %.2f %.2f fillrect\n",XPOST(x1),YPOST(y1), - XPOST(x2),YPOST(y2)); - } -} - - -/* Normalizes an angle to be between 0 and 360 degrees. */ -static float -angnorm (float ang) -{ - int scale; - - if (ang < 0) { - scale = (int) (ang / 360. - 1); - } - else { - scale = (int) (ang / 360.); - } - ang = ang - scale * 360; - return (ang); -} - -void -drawellipticarc (float xc, float yc, float radx, float rady, float startang, float angextent) -{ - int xl, yt; - unsigned int width, height; -#ifdef WIN32 - HPEN hOldPen; - int p1, p2, p3, p4; -#endif - - /* Conservative (but fast) clip test -- check containing rectangle of * - * an ellipse. */ - - if (rect_off_screen (xc-radx,yc-rady,xc+radx,yc+rady)) - return; - - /* X Windows has trouble with very large angles. (Over 360). * - * Do following to prevent its inaccurate (overflow?) problems. */ - if (fabs(angextent) > 360.) - angextent = 360.; - - startang = angnorm (startang); - - if (gl_state.disp_type == SCREEN) { - xl = (int) (xcoord(xc) - fabs(xmult*radx)); - yt = (int) (ycoord(yc) - fabs(ymult*rady)); - width = (unsigned int) (2*fabs(xmult*radx)); - height = (unsigned int) (2*fabs(ymult*rady)); -#ifdef X11 - XDrawArc (display, toplevel, current_gc, xl, yt, width, height, - (int) (startang*64), (int) (angextent*64)); -#else // Win32 - /* set arc direction */ - if (angextent > 0) { - p1 = (int)(xcoord(xc) + fabs(xmult*radx)*cos(DEGTORAD(startang))); - p2 = (int)(ycoord(yc) - fabs(ymult*rady)*sin(DEGTORAD(startang))); - p3 = (int)(xcoord(xc) + fabs(xmult*radx)*cos(DEGTORAD(startang+angextent-.001))); - p4 = (int)(ycoord(yc) - fabs(ymult*rady)*sin(DEGTORAD(startang+angextent-.001))); - } - else { - p1 = (int)(xcoord(xc) + fabs(xmult*radx)*cos(DEGTORAD(startang+angextent+.001))); - p2 = (int)(ycoord(yc) - fabs(ymult*rady)*sin(DEGTORAD(startang+angextent+.001))); - p3 = (int)(xcoord(xc) + fabs(xmult*radx)*cos(DEGTORAD(startang))); - p4 = (int)(ycoord(yc) - fabs(ymult*rady)*sin(DEGTORAD(startang))); - } - - hOldPen = (HPEN)SelectObject(hGraphicsDC, hGraphicsPen); - if(!(hOldPen)) - SELECT_ERROR(); - if(!Arc(hGraphicsDC, xl, yt, xl+width, yt+height, p1, p2, p3, p4)) - DRAW_ERROR(); - if(!SelectObject(hGraphicsDC, hOldPen)) - SELECT_ERROR(); -#endif - } - else { - fprintf(ps, "gsave\n"); - fprintf(ps, "%.2f %.2f translate\n", XPOST(xc), YPOST(yc)); - fprintf(ps, "%.2f 1 scale\n", fabs(radx*ps_xmult)/fabs(rady*ps_ymult)); - fprintf(ps, "0 0 %.2f %.2f %.2f %s\n", /*XPOST(xc)*/ - /*YPOST(yc)*/ fabs(rady*ps_xmult), startang, startang+angextent, - (angextent < 0) ? "drawarcn" : "drawarc") ; - fprintf(ps, "grestore\n"); - } -} - -/* Startang is relative to the Window's positive x direction. Angles in degrees. - */ -void -drawarc (float xc, float yc, float rad, float startang, - float angextent) -{ - drawellipticarc(xc, yc, rad, rad, startang, angextent); -} - - -/* Fills a elliptic arc. Startang is relative to the Window's positive x - * direction. Angles in degrees. - */ -void -fillellipticarc (float xc, float yc, float radx, float rady, float startang, - float angextent) -{ - int xl, yt; - unsigned int width, height; -#ifdef WIN32 - HPEN hOldPen; - HBRUSH hOldBrush; - int p1, p2, p3, p4; -#endif - - /* Conservative (but fast) clip test -- check containing rectangle of * - * a circle. */ - - if (rect_off_screen (xc-radx,yc-rady,xc+radx,yc+rady)) - return; - - /* X Windows has trouble with very large angles. (Over 360). * - * Do following to prevent its inaccurate (overflow?) problems. */ - - if (fabs(angextent) > 360.) - angextent = 360.; - - startang = angnorm (startang); - - if (gl_state.disp_type == SCREEN) { - xl = (int) (xcoord(xc) - fabs(xmult*radx)); - yt = (int) (ycoord(yc) - fabs(ymult*rady)); - width = (unsigned int) (2*fabs(xmult*radx)); - height = (unsigned int) (2*fabs(ymult*rady)); -#ifdef X11 - XFillArc (display, toplevel, current_gc, xl, yt, width, height, - (int) (startang*64), (int) (angextent*64)); -#else // Win32 - /* set pie direction */ - if (angextent > 0) { - p1 = (int)(xcoord(xc) + fabs(xmult*radx)*cos(DEGTORAD(startang))); - p2 = (int)(ycoord(yc) - fabs(ymult*rady)*sin(DEGTORAD(startang))); - p3 = (int)(xcoord(xc) + fabs(xmult*radx)*cos(DEGTORAD(startang+angextent-.001))); - p4 = (int)(ycoord(yc) - fabs(ymult*rady)*sin(DEGTORAD(startang+angextent-.001))); - } - else { - p1 = (int)(xcoord(xc) + fabs(xmult*radx)*cos(DEGTORAD(startang+angextent+.001))); - p2 = (int)(ycoord(yc) - fabs(ymult*rady)*sin(DEGTORAD(startang+angextent+.001))); - p3 = (int)(xcoord(xc) + fabs(xmult*radx)*cos(DEGTORAD(startang))); - p4 = (int)(ycoord(yc) - fabs(ymult*rady)*sin(DEGTORAD(startang))); - } - - hOldPen = (HPEN)SelectObject(hGraphicsDC, GetStockObject(NULL_PEN)); - if(!(hOldPen)) - SELECT_ERROR(); - hOldBrush = (HBRUSH)SelectObject(hGraphicsDC, hGraphicsBrush); - if(!(hOldBrush)) - SELECT_ERROR(); -// Win32 API says a zero return value indicates an error, but it seems to always -// return zero. Don't check for an error on Pie. - Pie(hGraphicsDC, xl, yt, xl+width, yt+height, p1, p2, p3, p4); - -// if(!Pie(hGraphicsDC, xl, yt, xl+width, yt+height, p1, p2, p3, p4)); -// DRAW_ERROR(); - if(!SelectObject(hGraphicsDC, hOldPen)) - SELECT_ERROR(); - if(!SelectObject(hGraphicsDC, hOldBrush)) - SELECT_ERROR(); -#endif - } - else { - fprintf(ps, "gsave\n"); - fprintf(ps, "%.2f %.2f translate\n", XPOST(xc), YPOST(yc)); - fprintf(ps, "%.2f 1 scale\n", fabs(radx*ps_xmult)/fabs(rady*ps_ymult)); - fprintf(ps, "%.2f %.2f %.2f 0 0 %s\n", /*XPOST(xc)*/ - /*YPOST(yc)*/ fabs(rady*ps_xmult), startang, startang+angextent, - (angextent < 0) ? "fillarcn" : "fillarc") ; - fprintf(ps, "grestore\n"); - } -} - -void -fillarc (float xc, float yc, float rad, float startang, float angextent) { - fillellipticarc(xc, yc, rad, rad, startang, angextent); -} - -void -fillpoly (t_point *points, int npoints) -{ -#ifdef X11 - XPoint transpoints[MAXPTS]; -#else - POINT transpoints[MAXPTS]; - HPEN hOldPen; - HBRUSH hOldBrush; -#endif - int i; - float xmin, ymin, xmax, ymax; - - if (npoints > MAXPTS) { - printf("Error in fillpoly: Only %d points allowed per polygon.\n", - MAXPTS); - printf("%d points were requested. Polygon is not drawn.\n",npoints); - return; - } - - /* Conservative (but fast) clip test -- check containing rectangle of * - * polygon. */ - - xmin = xmax = points[0].x; - ymin = ymax = points[0].y; - - for (i=1;i=0;i--) - fprintf (ps, "%.2f %.2f\n", XPOST(points[i].x), YPOST(points[i].y)); - - fprintf (ps, "%d fillpoly\n", npoints); - } -} - - -/* Draws text centered on xc,yc if it fits in boundx */ -void -drawtext (float xc, float yc, const char *text, float boundx) -{ - int len, width, xw_off, yw_off, font_ascent, font_descent; - -#ifdef X11 - len = strlen(text); - width = XTextWidth(font_info[currentfontsize], text, len); - font_ascent = font_info[currentfontsize]->ascent; - font_descent = font_info[currentfontsize]->descent; -#else /* WC : WIN32 */ - HFONT hOldFont; - SIZE textsize; - TEXTMETRIC textmetric; - - hOldFont = (HFONT)SelectObject(hGraphicsDC, hGraphicsFont); - if(!(hOldFont)) - SELECT_ERROR(); - if(SetTextColor(hGraphicsDC, win32_colors[currentcolor]) == CLR_INVALID) - DRAW_ERROR(); - - len = strlen(text); - if (!GetTextExtentPoint32(hGraphicsDC, text, len, &textsize)) - DRAW_ERROR(); - width = textsize.cx; - if (!GetTextMetrics(hGraphicsDC, &textmetric)) - DRAW_ERROR(); - font_ascent = textmetric.tmAscent; - font_descent = textmetric.tmDescent; -#endif - if (width > fabs(boundx*xmult)) { -#ifdef WIN32 - if(!SelectObject(hGraphicsDC, hOldFont)) - SELECT_ERROR(); -#endif - return; /* Don't draw if it won't fit */ - } - - xw_off = (int)(width/(2.*xmult)); /* NB: sign doesn't matter. */ - - /* NB: 2 * descent makes this slightly conservative but simplifies code. */ - yw_off = (int)((font_ascent + 2 * font_descent)/(2.*ymult)); - - /* Note: text can be clipped when a little bit of it would be visible * - * right now. Perhaps X doesn't return extremely accurate width and * - * ascent values, etc? Could remove this completely by multiplying * - * xw_off and yw_off by, 1.2 or 1.5. */ - if (rect_off_screen(xc-xw_off, yc-yw_off, xc+xw_off, yc+yw_off)) { -#ifdef WIN32 - if(!SelectObject(hGraphicsDC, hOldFont)) - SELECT_ERROR(); -#endif - return; - } - - if (gl_state.disp_type == SCREEN) { -#ifdef X11 - XDrawString(display, toplevel, current_gc, xcoord(xc)-width/2, ycoord(yc) + - (font_info[currentfontsize]->ascent - font_info[currentfontsize]->descent)/2, - text, len); -#else /* Win32 */ - SetBkMode(hGraphicsDC, TRANSPARENT); - if(!TextOut (hGraphicsDC, xcoord(xc)-width/2, ycoord(yc) - (font_ascent + font_descent)/2, - text, len)) - DRAW_ERROR(); - if(!SelectObject(hGraphicsDC, hOldFont)) - SELECT_ERROR(); -#endif - } - else { - fprintf(ps,"(%s) %.2f %.2f censhow\n",text,XPOST(xc),YPOST(yc)); - } -} - - -void -flushinput (void) -{ - if (gl_state.disp_type != SCREEN) - return; -#ifdef X11 - XFlush(display); -#endif -} - - -void -init_world (float x1, float y1, float x2, float y2) -{ - /* Sets the coordinate system the user wants to draw into. */ - - xleft = x1; - xright = x2; - ytop = y1; - ybot = y2; - - saved_xleft = xleft; /* Save initial world coordinates to allow full */ - saved_xright = xright; /* view button to zoom all the way out. */ - saved_ytop = ytop; - saved_ybot = ybot; - - if (gl_state.disp_type == SCREEN) { - update_transform(); - } - else { - update_ps_transform(); - } -} - - -/* Draw the current message in the text area at the screen bottom. */ -void -draw_message (void) -{ - int savefontsize, savecolor; - float ylow; -#ifdef X11 - int len, width; -#endif - - if (gl_state.disp_type == SCREEN) { -#ifdef X11 - XClearWindow (display, textarea); - len = strlen (statusMessage); - width = XTextWidth(font_info[menu_font_size], statusMessage, len); - XSetForeground(display, gc_menus,colors[WHITE]); - XDrawRectangle(display, textarea, gc_menus, 0, 0, top_width - MWIDTH, T_AREA_HEIGHT); - XSetForeground(display, gc_menus,colors[BLACK]); - XDrawLine(display, textarea, gc_menus, 0, T_AREA_HEIGHT-1, top_width-MWIDTH, T_AREA_HEIGHT-1); - XDrawLine(display, textarea, gc_menus, top_width-MWIDTH-1, 0, top_width-MWIDTH-1, T_AREA_HEIGHT-1); - - XDrawString(display, textarea, gc_menus, - (top_width - MWIDTH - width)/2, - T_AREA_HEIGHT/2 + (font_info[menu_font_size]->ascent - - font_info[menu_font_size]->descent)/2, statusMessage, len); -#else - if(!InvalidateRect(hStatusWnd, NULL, TRUE)) - DRAW_ERROR(); - if(!UpdateWindow(hStatusWnd)) - DRAW_ERROR(); -#endif - } - - else { - /* Draw the message in the bottom margin. Printer's generally can't * - * print on the bottom 1/4" (area with y < 18 in PostScript coords.) */ - - savecolor = currentcolor; - setcolor (BLACK); - savefontsize = currentfontsize; - setfontsize (menu_font_size - 2); /* Smaller OK on paper */ - ylow = ps_bot - 8; - fprintf(ps,"(%s) %.2f %.2f censhow\n",statusMessage,(ps_left+ps_right)/2., - ylow); - setcolor (savecolor); - setfontsize (savefontsize); - } -} - - -/* Changes the message to be displayed on screen. */ -void -update_message (const char *msg) -{ - strncpy (statusMessage, msg, BUFSIZE); - draw_message (); -#ifdef X11 -// Make this appear immediately. Win32 does that automaticaly. - XFlush (display); -#endif // X11 -} - - -/* Zooms in by a factor of 1.666. */ -static void -zoom_in (void (*drawscreen) (void)) -{ - float xdiff, ydiff; - - xdiff = xright - xleft; - ydiff = ybot - ytop; - xleft += xdiff/5; - xright -= xdiff/5; - ytop += ydiff/5; - ybot -= ydiff/5; - - update_transform (); - drawscreen(); -} - - -/* Zooms out by a factor of 1.666. */ -static void -zoom_out (void (*drawscreen) (void)) -{ - float xdiff, ydiff; - - xdiff = xright - xleft; - ydiff = ybot - ytop; - xleft -= xdiff/3; - xright += xdiff/3; - ytop -= ydiff/3; - ybot += ydiff/3; - - update_transform (); - drawscreen(); -} - - -/* Sets the view back to the initial view set by init_world (i.e. a full * -* view) of all the graphics. */ -static void -zoom_fit (void (*drawscreen) (void)) -{ - xleft = saved_xleft; - xright = saved_xright; - ytop = saved_ytop; - ybot = saved_ybot; - - update_transform (); - drawscreen(); -} - - -/* Moves view 1/2 screen up. */ -static void -translate_up (void (*drawscreen) (void)) -{ - float ystep; - - ystep = (ybot - ytop)/2; - ytop -= ystep; - ybot -= ystep; - update_transform(); - drawscreen(); -} - - -/* Moves view 1/2 screen down. */ -static void -translate_down (void (*drawscreen) (void)) -{ - float ystep; - - ystep = (ybot - ytop)/2; - ytop += ystep; - ybot += ystep; - update_transform(); - drawscreen(); -} - - -/* Moves view 1/2 screen left. */ -static void -translate_left (void (*drawscreen) (void)) -{ - - float xstep; - - xstep = (xright - xleft)/2; - xleft -= xstep; - xright -= xstep; - update_transform(); - drawscreen(); -} - - -/* Moves view 1/2 screen right. */ -static void -translate_right (void (*drawscreen) (void)) -{ - float xstep; - - xstep = (xright - xleft)/2; - xleft += xstep; - xright += xstep; - update_transform(); - drawscreen(); -} - - -static void -update_win (int x[2], int y[2], void (*drawscreen)(void)) -{ - float x1, x2, y1, y2; - - x[0] = min(x[0],top_width-MWIDTH); /* Can't go under menu */ - x[1] = min(x[1],top_width-MWIDTH); - y[0] = min(y[0],top_height-T_AREA_HEIGHT); /* Can't go under text area */ - y[1] = min(y[1],top_height-T_AREA_HEIGHT); - - if ((x[0] == x[1]) || (y[0] == y[1])) { - printf("Illegal (zero area) window. Window unchanged.\n"); - return; - } - x1 = XTOWORLD(min(x[0],x[1])); - x2 = XTOWORLD(max(x[0],x[1])); - y1 = YTOWORLD(min(y[0],y[1])); - y2 = YTOWORLD(max(y[0],y[1])); - xleft = x1; - xright = x2; - ytop = y1; - ybot = y2; - update_transform(); - drawscreen(); -} - - -/* The window button was pressed. Let the user click on the two * -* diagonally opposed corners, and zoom in on this area. */ -static void -adjustwin (void (*drawscreen) (void)) -{ -#ifdef X11 - - XEvent report; - int corner, xold, yold, x[2], y[2]; - - corner = 0; - xold = -1; - yold = -1; /* Don't need to init yold, but stops compiler warning. */ - - while (corner<2) { - XNextEvent (display, &report); - switch (report.type) { - case Expose: -#ifdef VERBOSE - printf("Got an expose event.\n"); - printf("Count is: %d.\n",report.xexpose.count); - printf("Window ID is: %d.\n",report.xexpose.window); -#endif - if (report.xexpose.count != 0) - break; - if (report.xexpose.window == menu) - drawmenu(); - else if (report.xexpose.window == toplevel) { - drawscreen(); - xold = -1; /* No rubber band on screen */ - } - else if (report.xexpose.window == textarea) - draw_message(); - break; - case ConfigureNotify: - top_width = report.xconfigure.width; - top_height = report.xconfigure.height; - update_transform(); - drawmenu(); - draw_message(); -#ifdef VERBOSE - printf("Got a ConfigureNotify.\n"); - printf("New width: %d New height: %d.\n",top_width,top_height); -#endif - break; - case ButtonPress: -#ifdef VERBOSE - printf("Got a buttonpress.\n"); - printf("Window ID is: %d.\n",report.xbutton.window); - printf("Location (%d, %d).\n", report.xbutton.x, - report.xbutton.y); -#endif - if (report.xbutton.window != toplevel) break; - x[corner] = report.xbutton.x; - y[corner] = report.xbutton.y; - if (corner == 0) { - /* XSelectInput (display, toplevel, ExposureMask | - StructureNotifyMask | ButtonPressMask | PointerMotionMask); */ - } - else { - update_win(x,y,drawscreen); - } - corner++; - break; - case MotionNotify: - if (corner) { -#ifdef VERBOSE - printf("Got a MotionNotify Event.\n"); - printf("x: %d y: %d\n",report.xmotion.x,report.xmotion.y); -#endif - if (xold >= 0) { /* xold set -ve before we draw first box */ - // Erase prior box. - set_draw_mode(DRAW_XOR); - XDrawRectangle(display,toplevel,gcxor,min(x[0],xold), - min(y[0],yold),abs(x[0]-xold),abs(y[0]-yold)); - set_draw_mode(DRAW_NORMAL); - } - /* Don't allow user to window under menu region */ - xold = min(report.xmotion.x,top_width-1-MWIDTH); - yold = report.xmotion.y; - set_draw_mode(DRAW_XOR); - - // Use forcing versions, as we want these modes to apply - // to the xor drawing context, and the regular versions - // won't update the drawing context if there is no change in line - // width etc. (but they might only be on the normal context) - force_setlinewidth(1); - force_setlinestyle(DASHED); - force_setcolor(gl_state.background_cindex); - - // Draw rubber band box. - XDrawRectangle(display,toplevel,gcxor,min(x[0],xold), - min(y[0],yold),abs(x[0]-xold),abs(y[0]-yold)); - set_draw_mode(DRAW_NORMAL); - } - break; - } - } - /* XSelectInput (display, toplevel, ExposureMask | StructureNotifyMask - | ButtonPressMask); */ -#else /* Win32 */ - /* Implemented as WM_LB... events */ - - /* Begin window adjust */ - if (!windowAdjustFlag) { - windowAdjustFlag = 1; - } -#endif -} - - -static void -postscript (void (*drawscreen) (void)) -{ -/* Takes a snapshot of the screen and stores it in pic?.ps. The * - * first picture goes in pic1.ps, the second in pic2.ps, etc. */ - - static int piccount = 1; - int success; - char fname[BUFSIZE]; - - sprintf(fname,"pic%d.ps",piccount); - printf("Writing postscript output to file %s\n", fname); - success = init_postscript (fname); - - if (success) { - - drawscreen(); - close_postscript (); - piccount++; - } - else { - printf ("Error initializing for postscript output.\n"); -#ifdef WIN32 - MessageBox(hMainWnd, "Error initializing postscript output.", NULL, MB_OK); -#endif - } -} - - -static void -proceed (void (*drawscreen) (void)) -{ - ProceedPressed = TRUE; -} - - -static void -quit (void (*drawscreen) (void)) -{ - close_graphics(); - exit(0); -} - - -/* Release all my drawing structures (through the X server) and * -* close down the connection. */ -void -close_graphics (void) -{ - if (!gl_state.initialized) - return; -#ifdef X11 - int i; - for (i=0;i<=MAX_FONT_SIZE;i++) { - if (font_is_loaded[i]) - XFreeFont(display,font_info[i]); - } - - XFreeGC(display,gc); - XFreeGC(display,gcxor); - XFreeGC(display,gc_menus); - - if (private_cmap != None) - XFreeColormap (display, private_cmap); - - XCloseDisplay(display); -#else /* Win32 */ - int i; - // Free the font data structure for each loaded font. - for (i = 0; i <= MAX_FONT_SIZE; i++) { - if (font_is_loaded[i]) { - free (font_info[i]); - } - } - - // Destroy the window - if(!DestroyWindow(hMainWnd)) - DRAW_ERROR(); - - // free the window class (type information held by MS Windows) - // for each of the four window types we created. Otherwise a - // later call to init_graphics to open the graphics window up again - // will fail. - if (!UnregisterClass (szAppName, GetModuleHandle(NULL)) ) - DRAW_ERROR(); - if (!UnregisterClass (szGraphicsName, GetModuleHandle(NULL)) ) - DRAW_ERROR(); - if (!UnregisterClass (szStatusName, GetModuleHandle(NULL)) ) - DRAW_ERROR(); - if (!UnregisterClass (szButtonsName, GetModuleHandle(NULL)) ) - DRAW_ERROR(); -#endif - - free(button); - button = NULL; - - for (i = 0; i <= MAX_FONT_SIZE; i++) { - font_is_loaded[i] = false; - font_info[i] = NULL; - } - gl_state.initialized = false; -} - - -/* Opens a file for PostScript output. The header information, * -* clipping path, etc. are all dumped out. If the file could * -* not be opened, the routine returns 0; otherwise it returns 1. */ -int init_postscript (const char *fname) -{ - - ps = fopen (fname,"w"); - if (ps == NULL) { - printf("Error: could not open %s for PostScript output.\n",fname); - printf("Drawing to screen instead.\n"); - return (0); - } - gl_state.disp_type = POSTSCRIPT; /* Graphics go to postscript file now. */ - - /* Header for minimal conformance with the Adobe structuring convention */ - fprintf(ps,"%%!PS-Adobe-1.0\n"); - fprintf(ps,"%%%%DocumentFonts: Helvetica\n"); - fprintf(ps,"%%%%Pages: 1\n"); - /* Set up postscript transformation macros and page boundaries */ - update_ps_transform(); - /* Bottom margin is at ps_bot - 15. to leave room for the on-screen message. */ - fprintf(ps,"%%%%HiResBoundingBox: %.2f %.2f %.2f %.2f\n", - ps_left, ps_bot - 15., ps_right, ps_top); - fprintf(ps,"%%%%EndComments\n"); - - fprintf(ps,"/censhow %%draw a centered string\n"); - fprintf(ps," { moveto %% move to proper spot\n"); - fprintf(ps," dup stringwidth pop %% get x length of string\n"); - fprintf(ps," -2 div %% Proper left start\n"); - fprintf(ps," yoff rmoveto %% Move left that much and down half font height\n"); - fprintf(ps," show newpath } def %% show the string\n\n"); - - fprintf(ps,"/setfontsize %% set font to desired size and compute " - "centering yoff\n"); - fprintf(ps," { /Helvetica findfont\n"); - fprintf(ps," 8 scalefont\n"); - fprintf(ps," setfont %% Font size set ...\n\n"); - fprintf(ps," 0 0 moveto %% Get vertical centering offset\n"); - fprintf(ps," (Xg) true charpath\n"); - fprintf(ps," flattenpath pathbbox\n"); - fprintf(ps," /ascent exch def pop -1 mul /descent exch def pop\n"); - fprintf(ps," newpath\n"); - fprintf(ps," descent ascent sub 2 div /yoff exch def } def\n\n"); - - fprintf(ps,"%% Next two lines for debugging only.\n"); - fprintf(ps,"/str 20 string def\n"); - fprintf(ps,"/pnum {str cvs print ( ) print} def\n"); - - fprintf(ps,"/drawline %% draw a line from (x2,y2) to (x1,y1)\n"); - fprintf(ps," { moveto lineto stroke } def\n\n"); - - fprintf(ps,"/rect %% outline a rectangle \n"); - fprintf(ps," { /y2 exch def /x2 exch def /y1 exch def /x1 exch def\n"); - fprintf(ps," x1 y1 moveto\n"); - fprintf(ps," x2 y1 lineto\n"); - fprintf(ps," x2 y2 lineto\n"); - fprintf(ps," x1 y2 lineto\n"); - fprintf(ps," closepath } def\n\n"); - - fprintf(ps,"/drawrect %% draw outline of a rectanagle\n"); - fprintf(ps," { rect stroke } def\n\n"); - - fprintf(ps,"/fillrect %% fill in a rectanagle\n"); - fprintf(ps," { rect fill } def\n\n"); - - fprintf (ps,"/drawarc { arc stroke } def %% draw an arc\n"); - fprintf (ps,"/drawarcn { arcn stroke } def " - " %% draw an arc in the opposite direction\n\n"); - - fprintf (ps,"%%Fill a counterclockwise or clockwise arc sector, " - "respectively.\n"); - fprintf (ps,"/fillarc { moveto currentpoint 5 2 roll arc closepath fill } " - "def\n"); - fprintf (ps,"/fillarcn { moveto currentpoint 5 2 roll arcn closepath fill } " - "def\n\n"); - - fprintf (ps,"/fillpoly { 3 1 roll moveto %% move to first point\n" - " 2 exch 1 exch {pop lineto} for %% line to all other points\n" - " closepath fill } def\n\n"); - - - fprintf(ps,"%%Color Definitions:\n"); - fprintf(ps,"/white { 1 setgray } def\n"); - fprintf(ps,"/black { 0 setgray } def\n"); - fprintf(ps,"/grey55 { .55 setgray } def\n"); - fprintf(ps,"/grey75 { .75 setgray } def\n"); - fprintf(ps,"/blue { 0 0 1 setrgbcolor } def\n"); - fprintf(ps,"/green { 0 1 0 setrgbcolor } def\n"); - fprintf(ps,"/yellow { 1 1 0 setrgbcolor } def\n"); - fprintf(ps,"/cyan { 0 1 1 setrgbcolor } def\n"); - fprintf(ps,"/red { 1 0 0 setrgbcolor } def\n"); - fprintf(ps,"/darkgreen { 0 0.5 0 setrgbcolor } def\n"); - fprintf(ps,"/magenta { 1 0 1 setrgbcolor } def\n"); - fprintf(ps,"/bisque { 1 0.89 0.77 setrgbcolor } def\n"); - fprintf(ps,"/lightblue { 0.68 0.85 0.9 setrgbcolor } def\n"); - fprintf(ps,"/thistle { 0.85 0.75 0.85 setrgbcolor } def\n"); - fprintf(ps,"/plum { 0.87 0.63 0.87 setrgbcolor } def\n"); - fprintf(ps,"/khaki { 0.94 0.9 0.55 setrgbcolor } def\n"); - fprintf(ps,"/coral { 1 0.5 0.31 setrgbcolor } def\n"); - fprintf(ps,"/turquoise { 0.25 0.88 0.82 setrgbcolor } def\n"); - fprintf(ps,"/mediumpurple { 0.58 0.44 0.86 setrgbcolor } def\n"); - fprintf(ps,"/darkslateblue { 0.28 0.24 0.55 setrgbcolor } def\n"); - fprintf(ps,"/darkkhaki { 0.74 0.72 0.42 setrgbcolor } def\n"); - - fprintf(ps,"\n%%Solid and dashed line definitions:\n"); - fprintf(ps,"/linesolid {[] 0 setdash} def\n"); - fprintf(ps,"/linedashed {[3 3] 0 setdash} def\n"); - - fprintf(ps,"\n%%%%EndProlog\n"); - fprintf(ps,"%%%%Page: 1 1\n\n"); - - /* Set up PostScript graphics state to match current one. */ - force_setcolor (currentcolor); - force_setlinestyle (currentlinestyle); - force_setlinewidth (currentlinewidth); - force_setfontsize (currentfontsize); - - /* Draw this in the bottom margin -- must do before the clippath is set */ - draw_message (); - - /* Set clipping on page. */ - fprintf(ps,"%.2f %.2f %.2f %.2f rect ",ps_left, ps_bot,ps_right,ps_top); - fprintf(ps,"clip newpath\n\n"); - - return (1); -} - -/* Properly ends postscript output and redirects output to screen. */ -void close_postscript (void) -{ - - fprintf(ps,"showpage\n"); - fprintf(ps,"\n%%%%Trailer\n"); - fclose (ps); - gl_state.disp_type = SCREEN; - update_transform(); /* Ensure screen world reflects any changes * - * made while printing. */ - - /* Need to make sure that we really set up the graphics context. - * The current font set indicates the last font used in a postscript call, - * etc., *NOT* the font set in the X11 or Win32 graphics context. Force the - * current font, colour etc. to be applied to the graphics context, so - * subsequent drawing commands work properly. - */ - - force_setcolor (currentcolor); - force_setlinestyle (currentlinestyle); - force_setlinewidth (currentlinewidth); - force_setfontsize (currentfontsize); -} - - -/* Sets up the default menu buttons on the right hand side of the window. */ -static void -build_default_menu (void) -{ - int i, xcen, x1, y1, bwid, bheight, space; - const int NUM_ARROW_BUTTONS = 4, NUM_STANDARD_BUTTONS = 12, SEPARATOR_BUTTON_INDEX = 8; - - -#ifdef X11 - unsigned long valuemask; - XSetWindowAttributes menu_attributes; - - menu = XCreateSimpleWindow(display,toplevel, - top_width-MWIDTH, 0, MWIDTH, display_height, 0, - colors[BLACK], colors[LIGHTGREY]); - menu_attributes.event_mask = ExposureMask; - /* Ignore button presses on the menu background. */ - menu_attributes.do_not_propagate_mask = ButtonPressMask; - /* Keep menu on top right */ - menu_attributes.win_gravity = NorthEastGravity; - valuemask = CWWinGravity | CWEventMask | CWDontPropagate; - XChangeWindowAttributes(display, menu, valuemask, &menu_attributes); - XMapWindow (display, menu); -#endif - - button = (t_button *) my_malloc (NUM_STANDARD_BUTTONS * sizeof (t_button)); - - /* Now do the arrow buttons */ - bwid = 28; - space = 3; - y1 = 10; - xcen = 51; - x1 = xcen - bwid/2; - button[0].xleft = x1; - button[0].ytop = y1; -#ifdef X11 - setpoly (0, bwid/2, bwid/2, bwid/3, -PI/2.); /* Up */ -#else - button[0].type = BUTTON_TEXT; - strcpy(button[0].text, "U"); -#endif - button[0].fcn = translate_up; - - y1 += bwid + space; - x1 = xcen - 3*bwid/2 - space; - button[1].xleft = x1; - button[1].ytop = y1; -#ifdef X11 - setpoly (1, bwid/2, bwid/2, bwid/3, PI); /* Left */ -#else - button[1].type = BUTTON_TEXT; - strcpy(button[1].text, "L"); -#endif - button[1].fcn = translate_left; - - x1 = xcen + bwid/2 + space; - button[2].xleft = x1; - button[2].ytop = y1; -#ifdef X11 - setpoly (2, bwid/2, bwid/2, bwid/3, 0); /* Right */ -#else - button[2].type = BUTTON_TEXT; - strcpy(button[2].text, "R"); -#endif - button[2].fcn = translate_right; - - y1 += bwid + space; - x1 = xcen - bwid/2; - button[3].xleft = x1; - button[3].ytop = y1; -#ifdef X11 - setpoly (3, bwid/2, bwid/2, bwid/3, +PI/2.); /* Down */ -#else - button[3].type = BUTTON_TEXT; - strcpy(button[3].text, "D"); -#endif - button[3].fcn = translate_down; - - for (i = 0; i < NUM_ARROW_BUTTONS; i++) { - button[i].width = bwid; - button[i].height = bwid; - button[i].enabled = 1; - } - - /* Rectangular buttons */ - - y1 += bwid + space + 6; - space = 8; - bwid = 90; - bheight = 26; - x1 = xcen - bwid/2; - for (i = NUM_ARROW_BUTTONS; i < NUM_STANDARD_BUTTONS; i++) { - button[i].xleft = x1; - button[i].ytop = y1; - button[i].type = BUTTON_TEXT; - button[i].width = bwid; - button[i].enabled = 1; - if (i != SEPARATOR_BUTTON_INDEX) { - button[i].height = bheight; - y1 += bheight + space; - } - else { - button[i].height = 2; - button[i].type = BUTTON_SEPARATOR; - y1 += 2 + space; - } - } - - strcpy (button[4].text,"Zoom In"); - strcpy (button[5].text,"Zoom Out"); - strcpy (button[6].text,"Zoom Fit"); - strcpy (button[7].text,"Window"); - strcpy (button[8].text,"---1"); - strcpy (button[9].text,"PostScript"); - strcpy (button[10].text,"Proceed"); - strcpy (button[11].text,"Exit"); - - button[4].fcn = zoom_in; - button[5].fcn = zoom_out; - button[6].fcn = zoom_fit; - button[7].fcn = adjustwin; // see 'adjustButton' below in WIN32 section - button[8].fcn = NULL; - button[9].fcn = postscript; - button[10].fcn = proceed; - button[11].fcn = quit; - - for (i = 0; i < NUM_STANDARD_BUTTONS; i++) - map_button (i); - num_buttons = NUM_STANDARD_BUTTONS; - -#ifdef WIN32 - adjustButton = 7; - if(!InvalidateRect(hButtonsWnd, NULL, TRUE)) - DRAW_ERROR(); - if(!UpdateWindow(hButtonsWnd)) - DRAW_ERROR(); -#endif -} - -/* Makes sure the font of the specified size is loaded. Point_size * -* MUST be between 1 and MAX_FONT_SIZE. */ -static void -load_font(int pointsize) -{ - - if (pointsize > MAX_FONT_SIZE || pointsize < 1) { - printf ("Error: font size %d is out of valid range, 1 to %d.\n", - pointsize, MAX_FONT_SIZE); - return; - } - - if (font_is_loaded[pointsize]) // Nothing to do. - return; - -#ifdef X11 - #define NUM_FONT_TYPES 3 - char fontname[NUM_FONT_TYPES][BUFSIZE]; - int ifont; - bool success = false; - - /* Use proper point-size medium-weight upright helvetica font */ - // Exists on most X11 systems. - // Backup font: lucidasans, in the new naming style. - sprintf(fontname[0],"-*-helvetica-medium-r-*--*-%d0-*-*-*-*-*-*", - pointsize); - sprintf(fontname[1], "lucidasans-%d", pointsize); - sprintf(fontname[2],"-schumacher-clean-medium-r-*--*-%d0-*-*-*-*-*-*", - pointsize); - - - - - for (ifont = 0; ifont < NUM_FONT_TYPES; ifont++) { -#ifdef VERBOSE - printf ("Loading font: point size: %d, fontname: %s\n",pointsize, - fontname[ifont]); -#endif - /* Load font and get font information structure. */ - if ((font_info[pointsize] = XLoadQueryFont(display,fontname[ifont])) == NULL) { -#ifdef VERBOSE - fprintf( stderr, "Cannot open font %s\n", fontname[ifont]); -#endif - } - else { - success = true; - break; - } - } - if (!success) { - printf ("Error in load_font: cannot load any font of pointsize %d.\n", - pointsize); - printf ("Use xlsfonts to list available fonts, and modify load_font\n"); - printf ("in graphics.cpp.\n"); - exit (1); - } -#else /* WIN32 */ - LOGFONT *lf = font_info[pointsize] = (LOGFONT*)my_malloc(sizeof(LOGFONT)); - ZeroMemory(lf, sizeof(LOGFONT)); - lf->lfHeight = pointsize; - lf->lfWeight = FW_NORMAL; - lf->lfCharSet = ANSI_CHARSET; - lf->lfOutPrecision = OUT_DEFAULT_PRECIS; - lf->lfClipPrecision = CLIP_DEFAULT_PRECIS; - lf->lfQuality = PROOF_QUALITY; - lf->lfPitchAndFamily = VARIABLE_PITCH | FF_SWISS; - strcpy(lf->lfFaceName, "Arial"); -#endif - - font_is_loaded[pointsize] = true; -} - - -/* Return information useful for debugging. - * Used to return the top-level window object too, but that made graphics.h - * export all windows and X11 headers to the client program, so VB deleted - * that object (mainwnd) from this structure. - */ -void report_structure(t_report *report) { - report->xmult = xmult; - report->ymult = ymult; - report->xleft = xleft; - report->xright = xright; - report->ytop = ytop; - report->ybot = ybot; - report->ps_xmult = ps_xmult; - report->ps_ymult = ps_ymult; - report->top_width = top_width; - report->top_height = top_height; -} - - -void set_mouse_move_input (bool enable) { - get_mouse_move_input = enable; -} - - -void set_keypress_input (bool enable) { - get_keypress_input = enable; -} - - -void enable_or_disable_button (int ibutton, bool enabled) { - - if (button[ibutton].type != BUTTON_SEPARATOR) { - button[ibutton].enabled = enabled; -#ifdef WIN32 - EnableWindow(button[ibutton].hwnd, button[ibutton].enabled); -#else // X11 - drawbut(ibutton); - XFlush(display); -#endif - } -} - - -void set_draw_mode (enum e_draw_mode draw_mode) { -/* Set normal (overwrite) or xor (useful for rubber-banding) - * drawing mode. - */ - - if (draw_mode == DRAW_NORMAL) { -#ifdef X11 - current_gc = gc; -#else - if (!SetROP2(hGraphicsDC, R2_COPYPEN)) - SELECT_ERROR(); -#endif - } - else { // DRAW_XOR -#ifdef X11 - current_gc = gcxor; -#else - if (!SetROP2(hGraphicsDC, R2_XORPEN)) - SELECT_ERROR(); -#endif - } - current_draw_mode = draw_mode; -} - - -void change_button_text(const char *button_name, const char *new_button_text) { -/* Change the text on a button with button_name to new_button_text. - * Not a strictly necessary function, since you could intead just - * destroy button_name and make a new buton. - */ - int i, bnum; - - bnum = -1; - - for (i=4;itype == Expose) { - return (True); - } - - return (False); -} - - -static void menutext(Window win, int xc, int yc, const char *text) -{ - - /* draws text center at xc, yc -- used only by menu drawing stuff */ - - int len, width; - - len = strlen(text); - width = XTextWidth(font_info[menu_font_size], text, len); - XDrawString(display, win, gc_menus, xc-width/2, yc + - (font_info[menu_font_size]->ascent - font_info[menu_font_size]->descent)/2, - text, len); -} - - -static void drawbut (int bnum) -{ - - /* Draws button bnum in either its pressed or unpressed state. */ - - int width, height, thick, i, ispressed; - XPoint mypoly[6]; - - width = button[bnum].width; - height = button[bnum].height; - - if (button[bnum].type == BUTTON_SEPARATOR) { - int x,y; - - x = button[bnum].xleft; - y = button[bnum].ytop; - XSetForeground(display, gc_menus,colors[WHITE]); - XDrawLine(display, menu, gc_menus, x, y+1, x+width, y+1); - XSetForeground(display, gc_menus,colors[BLACK]); - XDrawLine(display, menu, gc_menus, x, y, x+width, y); - return; - } - - ispressed = button[bnum].ispressed; - thick = 2; - /* Draw top and left edges of 3D box. */ - if (ispressed) { - XSetForeground(display, gc_menus,colors[BLACK]); - } - else { - XSetForeground(display, gc_menus,colors[WHITE]); - } - - /* Note: X Windows doesn't appear to draw the bottom pixel of * - * a polygon with XFillPolygon, so I make this 1 pixel thicker * - * to compensate. */ - mypoly[0].x = 0; - mypoly[0].y = height; - mypoly[1].x = 0; - mypoly[1].y = 0; - mypoly[2].x = width; - mypoly[2].y = 0; - mypoly[3].x = width-thick; - mypoly[3].y = thick; - mypoly[4].x = thick; - mypoly[4].y = thick; - mypoly[5].x = thick; - mypoly[5].y = height-thick; - XFillPolygon(display,button[bnum].win,gc_menus,mypoly,6,Convex, - CoordModeOrigin); - - /* Draw bottom and right edges of 3D box. */ - if (ispressed) { - XSetForeground(display, gc_menus,colors[WHITE]); - } - else { - XSetForeground(display, gc_menus,colors[BLACK]); - } - mypoly[0].x = 0; - mypoly[0].y = height; - mypoly[1].x = width; - mypoly[1].y = height; - mypoly[2].x = width; - mypoly[2].y = 0; - mypoly[3].x = width-thick; - mypoly[3].y = thick; - mypoly[4].x = width-thick; - mypoly[4].y = height-thick; - mypoly[5].x = thick; - mypoly[5].y = height-thick; - XFillPolygon(display,button[bnum].win,gc_menus,mypoly,6,Convex, - CoordModeOrigin); - - /* Draw background */ - if (ispressed) { - XSetForeground(display, gc_menus,colors[DARKGREY]); - } - else { - XSetForeground(display, gc_menus,colors[LIGHTGREY]); - } - - /* Give x,y of top corner and width and height */ - XFillRectangle (display,button[bnum].win,gc_menus,thick,thick, - width-2*thick, height-2*thick); - - /* Draw polygon, if there is one */ - if (button[bnum].type == BUTTON_POLY) { - for (i=0;i<3;i++) { - mypoly[i].x = button[bnum].poly[i][0]; - mypoly[i].y = button[bnum].poly[i][1]; - } - XSetForeground(display, gc_menus,colors[BLACK]); - XFillPolygon(display,button[bnum].win,gc_menus,mypoly,3,Convex, - CoordModeOrigin); - } - - /* Draw text, if there is any */ - if (button[bnum].type == BUTTON_TEXT) { - if (button[bnum].enabled) - XSetForeground(display, gc_menus,colors[BLACK]); - else - XSetForeground(display, gc_menus,colors[DARKGREY]); - menutext(button[bnum].win,button[bnum].width/2, - button[bnum].height/2,button[bnum].text); - } -} - - -static int which_button (Window win) -{ - int i; - - for (i=0;iptMinTrackSize.x = display_width / 2; - lpMinMaxInfo->ptMinTrackSize.y = display_height / 2; - - return 0; - - - case WM_DESTROY: - if(!DeleteObject(hGrayBrush)) - DELETE_ERROR(); - PostQuitMessage(0); - return 0; - - case WM_KEYDOWN: - if (get_keypress_input) - keypress_ptr((char) wParam); - return 0; - } - - return DefWindowProc(hwnd, message, wParam, lParam); -} - - -static LRESULT CALLBACK -GraphicsWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) -{ - static TEXTMETRIC tm; - - PAINTSTRUCT ps; - static RECT oldAdjustRect; - static HPEN hDotPen = 0; - static HBITMAP hbmBuffer = 0, hbmObjtest, hbmAllObjtest; - static int X, Y, i; - - switch(message) - { - case WM_CREATE: - - /* Get the text metrics once upon creation (system font cannot change) */ - hCurrentDC = hGraphicsDC = hForegroundDC = GetDC (hwnd); - if(!hGraphicsDC) - DRAW_ERROR(); - - hBackgroundDC = CreateCompatibleDC(hForegroundDC); - if (!hBackgroundDC) - CREATE_ERROR(); - if (!SetMapMode(hBackgroundDC, MM_TEXT)) - CREATE_ERROR(); - hbmBuffer = CreateCompatibleBitmap(hForegroundDC, display_width, display_height); - if (!(hbmBuffer)) - CREATE_ERROR(); - if (!SelectObject(hBackgroundDC, hbmBuffer)) - SELECT_ERROR(); - - // monochrome bitmap - hObjtestDC = CreateCompatibleDC(hForegroundDC); - if (!hObjtestDC) - CREATE_ERROR(); - if (!SetMapMode(hObjtestDC, MM_TEXT)) - CREATE_ERROR(); - hbmObjtest = CreateCompatibleBitmap(hObjtestDC, display_width, display_height); - if (!(hbmObjtest)) - CREATE_ERROR(); - if (!SelectObject(hObjtestDC, hbmObjtest)) - SELECT_ERROR(); - - // monochrome bitmap - hAllObjtestDC = CreateCompatibleDC(hForegroundDC); - if (!hObjtestDC) - CREATE_ERROR(); - if (!SetMapMode(hAllObjtestDC, MM_TEXT)) - CREATE_ERROR(); - hbmAllObjtest = CreateCompatibleBitmap(hAllObjtestDC, display_width, display_height); - if (!(hbmAllObjtest)) - CREATE_ERROR(); - if (!SelectObject(hAllObjtestDC, hbmAllObjtest)) - SELECT_ERROR(); - - //if(!GetTextMetrics (hGraphicsDC, &tm)) - // DRAW_ERROR(); - if(!SetBkMode(hGraphicsDC, TRANSPARENT)) - DRAW_ERROR(); - - /* Setup the pens, etc */ - currentlinestyle = SOLID; - currentcolor = BLACK; - currentlinewidth = 1; - - /* - if(!ReleaseDC (hwnd, hGraphicsDC)) - DRAW_ERROR(); - - hGraphicsDC = 0; - */ currentfontsize = 12; - return 0; - - case WM_PAINT: - // was in xor mode, but got a general redraw. - // switch to normal drawing so we repaint properly. - if (current_draw_mode == DRAW_XOR) { - set_draw_mode(DRAW_NORMAL); - invalidate_screen(); - return 0; - } - hCurrentDC = hGraphicsDC; - drawtoscreen(); - /*hGraphicsDC =*/ BeginPaint(hwnd, &ps); - if(!hGraphicsDC) - DRAW_ERROR(); - - if (InEventLoop) { - if(!GetUpdateRect(hwnd, &updateRect, FALSE)) { - updateRect.left = 0; - updateRect.right = top_width; - updateRect.top = 0; - updateRect.bottom = top_height; - } - - if(windowAdjustFlag > 1) { - hDotPen = CreatePen(PS_DASH, 1, win32_colors[gl_state.background_cindex]); - if(!hDotPen) - CREATE_ERROR(); - if (!SetROP2(hGraphicsDC, R2_XORPEN)) - SELECT_ERROR(); - if(!SelectObject(hGraphicsDC, GetStockObject(NULL_BRUSH))) - SELECT_ERROR(); - if(!SelectObject(hGraphicsDC, hDotPen)) - SELECT_ERROR(); - if(!Rectangle(hGraphicsDC, oldAdjustRect.left, oldAdjustRect.top, - oldAdjustRect.right, oldAdjustRect.bottom)) - DRAW_ERROR(); - if(!Rectangle(hGraphicsDC, adjustRect.left, adjustRect.top, adjustRect.right, - adjustRect.bottom)) - DRAW_ERROR(); - oldAdjustRect = adjustRect; - if (!SetROP2(hGraphicsDC, R2_COPYPEN)) - SELECT_ERROR(); - if(!SelectObject(hGraphicsDC, GetStockObject(NULL_PEN))) - SELECT_ERROR(); - if(!DeleteObject(hDotPen)) - DELETE_ERROR(); - } - else - drawscreen_ptr(); - } - EndPaint(hwnd, &ps); - hGraphicsDC = hCurrentDC; - - /* Crash hard if called at wrong time */ - /* hGraphicsDC = NULL;*/ - return 0; - - case WM_SIZE: - /* Window has been resized. Save the new client dimensions */ - cxClient = LOWORD (lParam); - cyClient = HIWORD (lParam); - update_transform(); - - return 0; - - case WM_DESTROY: - if(!DeleteObject(hGraphicsPen)) - DELETE_ERROR(); - if(!DeleteObject(hGraphicsBrush)) - DELETE_ERROR(); - if(!DeleteObject(hGraphicsFont)) - DELETE_ERROR(); - if (!DeleteObject(hbmBuffer)) - DELETE_ERROR(); - if (!DeleteObject(hbmObjtest)) - DELETE_ERROR(); - if (!DeleteObject(hbmAllObjtest)) - DELETE_ERROR(); - if(!DeleteDC(hBackgroundDC)) - DELETE_ERROR(); - if(!DeleteDC(hObjtestDC)) - DELETE_ERROR(); - if(!DeleteDC(hAllObjtestDC)) - DELETE_ERROR(); - if(!ReleaseDC(hwnd, hForegroundDC)) - DELETE_ERROR(); - PostQuitMessage(0); - return 0; - - case WM_LBUTTONDOWN: - if (!windowAdjustFlag) { - mouseclick_ptr(XTOWORLD(LOWORD(lParam)), YTOWORLD(HIWORD(lParam))); - } - else { - // Special handling for the "Window" command, which takes multiple clicks. - // First you push the button, then you click for one corner, then you click for the other - // corner. - if(windowAdjustFlag == 1) { - windowAdjustFlag ++; - X = adjustRect.left = adjustRect.right = LOWORD(lParam); - Y = adjustRect.top = adjustRect.bottom = HIWORD(lParam); - oldAdjustRect = adjustRect; - } - else { - int i; - int adjustx[2], adjusty[2]; - - windowAdjustFlag = 0; - button[adjustButton].ispressed = 0; - SendMessage(button[adjustButton].hwnd, BM_SETSTATE, 0, 0); - - for (i=0; i= 2) { - if ( X > LOWORD(lParam)) { - adjustRect.left = LOWORD(lParam); - adjustRect.right = X; - } - else { - adjustRect.left = X; - adjustRect.right = LOWORD(lParam); - } - if ( Y > HIWORD(lParam)) { - adjustRect.top = HIWORD(lParam); - adjustRect.bottom = Y; - } - else { - adjustRect.top = Y; - adjustRect.bottom = HIWORD(lParam); - } - if(!InvalidateRect(hGraphicsWnd, &oldAdjustRect, FALSE)) - DRAW_ERROR(); - if(!InvalidateRect(hGraphicsWnd, &adjustRect, FALSE)) - DRAW_ERROR(); - if(!UpdateWindow(hGraphicsWnd)) - DRAW_ERROR(); - - return 0; - } - else if (get_mouse_move_input) - mousemove_ptr(XTOWORLD(LOWORD(lParam)), YTOWORLD(HIWORD(lParam))); - - return 0; - } - - return DefWindowProc(hwnd, message, wParam, lParam); -} - - -static LRESULT CALLBACK -StatusWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) -{ - HDC hdc; - PAINTSTRUCT ps; - RECT rect; - - switch(message) - { - case WM_CREATE: - hdc = GetDC(hwnd); - if(!hdc) - DRAW_ERROR(); - if(!SetBkMode(hdc, TRANSPARENT)) - DRAW_ERROR(); - if(!ReleaseDC(hwnd, hdc)) - DRAW_ERROR(); - return 0; - - case WM_PAINT: - hdc = BeginPaint(hwnd, &ps); - if(!hdc) - DRAW_ERROR(); - - if(!GetClientRect(hwnd, &rect)) - DRAW_ERROR(); - - if(!SelectObject(hdc, GetStockObject(NULL_BRUSH))) - SELECT_ERROR(); - if(!SelectObject(hdc, GetStockObject(WHITE_PEN))) - SELECT_ERROR(); - if(!Rectangle(hdc, rect.left, rect.top, rect.right, rect.bottom)) - DRAW_ERROR(); - if(!SelectObject(hdc, GetStockObject(BLACK_PEN))) - SELECT_ERROR(); - if(!MoveToEx(hdc, rect.left, rect.bottom-1, NULL)) - DRAW_ERROR(); - if(!LineTo(hdc, rect.right-1, rect.bottom-1)) - DRAW_ERROR(); - if(!LineTo(hdc, rect.right-1, rect.top)) - DRAW_ERROR(); - - if(!DrawText(hdc, TEXT(statusMessage), -1, &rect, DT_CENTER | DT_VCENTER | DT_SINGLELINE)) - DRAW_ERROR(); - - if(!EndPaint(hwnd, &ps)) - DRAW_ERROR(); - return 0; - - case WM_SIZE: - return 0; - - case WM_DESTROY: - PostQuitMessage(0); - return 0; - } - - return DefWindowProc(hwnd, message, wParam, lParam); -} - - -static LRESULT CALLBACK -ButtonsWND(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) -{ - HDC hdc; - PAINTSTRUCT ps; - RECT rect; - static HBRUSH hBrush; - int i; - - switch(message) - { - case WM_COMMAND: - if (!windowAdjustFlag) { - button[LOWORD(wParam) - 200].fcn(invalidate_screen); - if (windowAdjustFlag) { - adjustButton = LOWORD(wParam) - 200; - button[adjustButton].ispressed = 1; - for (i=0; i MAXPTS) - DRAW_ERROR(); - - /* Conservative (but fast) clip test -- check containing rectangle of * - * polygon. */ - - xmin = xmax = points[0].x; - ymin = ymax = points[0].y; - - for (i=1;i= ymax * 0.9) { - if (height <= ymax) - ret = 0; - else - ret = 1; - } - else - ret = -1; - - if(!SelectObject(hGraphicsDC, hOldFont)) - SELECT_ERROR(); - - return ret; -} - -int findfontsize(float ymax) { -// find the correct point size which will fit in the specified ymax as the max -// height of the font, using a binary search - int bot = 1; - int top = MAX_FONT_SIZE; - int mid, check; - - while (bot <= top) { - mid = (bot+top)/2; - - check = check_fontsize(mid, ymax); - if (!(check)) - return mid; - else if (check > 0) // too big - top = mid - 1; - else // too small - bot = mid + 1; - } - if (bot > MAX_FONT_SIZE) - return MAX_FONT_SIZE; - - return -1; // can't fit -} - -#endif /******** Win32 Specific Definitions ********************/ - - -#else /***** NO_GRAPHICS *******/ -/* No graphics at all. Stub everything out so calling program doesn't have to change - * but of course graphics won't do anything. - */ - -#include "graphics.h" - -void event_loop (void (*act_on_mousebutton) (float x, float y), - void (*act_on_mousemove) (float x, float y), - void (*act_on_keypress) (char key_pressed), - void (*drawscreen) (void)) { } - -void init_graphics (const char *window_name, int cindex) { } -void close_graphics (void) { } -void update_message (const char *msg) { } -void draw_message (void) { } -void init_world (float xl, float yt, float xr, float yb) { } -void flushinput (void) { } -void setcolor (int cindex) { } -int getcolor (void) { return 0; } -void setlinestyle (int linestyle) { } -void setlinewidth (int linewidth) { } -void setfontsize (int pointsize) { } -void drawline (float x1, float y1, float x2, float y2) { } -void drawrect (float x1, float y1, float x2, float y2) { } -void fillrect (float x1, float y1, float x2, float y2) { } -void fillpoly (t_point *points, int npoints) { } -void drawarc (float xcen, float ycen, float rad, float startang, - float angextent) { } -void drawellipticarc (float xc, float yc, float radx, float rady, float startang, float angextent) { } - -void fillarc (float xcen, float ycen, float rad, float startang, - float angextent) { } -void fillellipticarc (float xc, float yc, float radx, float rady, float startang, float angextent) { } - -void drawtext (float xc, float yc, const char *text, float boundx) { } -void clearscreen (void) { } - -void create_button (const char *prev_button_text , const char *button_text, - void (*button_func) (void (*drawscreen) (void))) { } - -void destroy_button (const char *button_text) { } - -int init_postscript (const char *fname) { - return (1); -} - -void close_postscript (void) { } - -void report_structure(t_report*) { } - -void set_mouse_move_input (bool) { } - -void set_keypress_input (bool) { } - -void set_draw_mode (enum e_draw_mode draw_mode) { } - -void enable_or_disable_button(int ibutton, bool enabled) { } - -void change_button_text(const char *button_text, const char *new_button_text) { } - -#ifdef WIN32 -void drawtobuffer(void) { } - -void drawtoscreen(void) { } - -void displaybuffer(void) { } - -void drawcurve(t_point *points, int npoints) { } - -void fillcurve(t_point *points, int npoints) { } - -void object_start(int all) { } - -void object_end() { } - -int pt_on_object(float x, float y) { } - -int findfontsize(float ymax) { } - - -#endif // WIN32 (subset of commands) - -#endif // NO_GRAPHICS diff --git a/vpr7_x2p/vpr/SRC/base/graphics.h b/vpr7_x2p/vpr/SRC/base/graphics.h deleted file mode 100755 index 250d6b73f..000000000 --- a/vpr7_x2p/vpr/SRC/base/graphics.h +++ /dev/null @@ -1,239 +0,0 @@ -//<<<<<<< .mine -#ifndef GRAPHICS_H -#define GRAPHICS_H -#include -#include -#include "easygl_constants.h" -using namespace std; - -// Set X11 by default, if neither NO_GRAPHICS nor WIN32 are defined -#ifndef NO_GRAPHICS -#ifndef WIN32 - #ifndef X11 - #define X11 - #endif -#endif // !WIN32 -#endif // !NO_GRAPHICS - -/* Graphics.h -* Originally written by Vaughn Betz (vaughn@eecg.utoronto.ca) -* Win32 port by Paul Leventis (leventi@eecg.utoronto.ca) -* Enhanced version by William Chow (chow@eecg.utoronto.ca) -* Minor updates by Guy Lemieux (lemieux@ece.ubc.ca) -* More updates by Vaughn Betz to make win32 cleaner and more robust. -*/ - - -/******* Constants and enums ******************************************/ - -/* Data structure below is for debugging. Lets you get a bunch - * of info about the low-level graphics state. - * xmult, ymult: world to pixel coordinate multiplier for screen - * ps_xmult, ps_ymult: world to pixel coordinate multiplier for postscript - * xleft, xright, ytop, yleft: current world coordinates of user-graphics display corners - * top_width, top_height: size (in pixels) of top-level window - */ -typedef struct { - float xmult, ymult; - float ps_xmult, ps_ymult; - float xleft, xright, ytop, ybot; - int top_width, top_height; -} t_report; - -/************** ESSENTIAL FUNCTIONS ******************/ - -/* This is the main routine for the graphics. When event_loop is -* called, it will continue executing until the Proceed button is -* pressed. -* Whenever the graphics need to be redrawn, drawscreen will be called; -* you must pass in a function pointer to a routine you write that can -* draw the picture you want. -* You can also pass in event handlers for user input if you wish. -* act_on_mouse_button() will be called whenever the user left-clicks -* in the graphics area. -* act_on_keypress() and act_on_mousemove() will be called whenever a -* keyboard key is pressed or the mouse is moved, respectively, in the -* graphics area. You can turn keypress input and mouse_move input -* on or off using the set_mouse_move_input () and set_keypress_input () -* functions (default for both: off). -*/ -void event_loop (void (*act_on_mousebutton) (float x, float y), - void (*act_on_mousemove) (float x, float y), - void (*act_on_keypress) (char key_pressed), - void (*drawscreen) (void)); - -/* Opens up the graphics; the window will have window_name in its - * title bar and the specified background colour. - * Known bug: can't re-open graphics after closing them. - */ -void init_graphics (const char *window_name, int cindex_background); - -/* Sets world coordinates of the graphics window so that the - * upper-left corner has virtual coordinate (xl, yt) and the - * bottom-right corner has virtual coordinate (xr, yb). - * Call this function before you call event_loop. Do not call it - * in your drawscreen () callback function, since it will undo any - * panning or zooming the user has done. - */ -void init_world (float xl, float yt, float xr, float yb); - -/* Closes the graphics */ -void close_graphics (void); - -/* Changes the status bar message to msg. */ -void update_message (const char *msg); - -/* Creates a button on the menu bar below the button with text - * prev_button_text. The button will have text button_text, - * and when clicked will call function button_func. - * button_func is a function that accepts a void function as - * an argument; this argument is set to the drawscreen routine - * as passed into the event loop. - */ -void create_button (const char *prev_button_text , const char *button_text, - void (*button_func) (void (*drawscreen) (void))); - -/* Destroys the button with the given text; i.e. removes it from - * the display. - */ -void destroy_button (const char *button_text); - -/*************** PostScript Routines *****************/ - -/* Opens file for postscript commands and initializes it. All subsequent - * drawing commands go to this file until close_postscript is called. - * You can generate postscript output by explicitly calling - * this routine, and then calling drawscreen. More commonly you'll - * just click on the "PostScript" button though, and that button - * calls this routine and drawscreen to generate a postscript file - * that exactly matches the graphics area display on the screen. - */ -int init_postscript (const char *fname); /* Returns 1 if successful */ - -/* Closes file and directs output to screen again. */ -void close_postscript (void); - - -/*************** DRAWING ROUTINES ******************/ - -/* Clears the screen. Should normally be the first call in your - * screen redrawing function. - */ -void clearscreen (void); - -/* The following routines draw to SCREEN if disp_type = SCREEN - * and to a PostScript file if disp_type = POSTSCRIPT - */ - -/* Set the current draw colour to the supplied colour index from color_types */ -void setcolor (int cindex); - -/* Set the color with a string instead of an enumerated constant */ -void setcolor (string cname); - -/* Get the current color */ -int getcolor(void); - -/* Sets the line style to the specified line_style */ -void setlinestyle (int linestyle); - -/* Sets the line width in pixels (for screen output) or points (1/72 of an inch) - * for PostScript output. A value of 0 means thinnest possible line. - */ -void setlinewidth (int linewidth); - -/* Sets the font size, in points. 72 points is 1 inch high. I allow - * fonts from 1 to 24 points in size; change MAX_FONT_SIZE if you want - * bigger fonts still. - */ -void setfontsize (int pointsize); - -/* Draws a line from (x1, y1) to (x2, y2) in world coordinates */ -void drawline (float x1, float y1, float x2, float y2); - -/* Draws a rectangle from (x1, y1) to (x2, y2) in world coordinates, using - * the current line style, colour and width. - */ -void drawrect (float x1, float y1, float x2, float y2); - -/* Draws a filled rectangle with the specified corners, in world coordinates. */ -void fillrect (float x1, float y1, float x2, float y2); - -/* Draws a filled polygon */ -void fillpoly (t_point *points, int npoints); - -/* Draw or fill a circular arc or elliptical arc. Angles in degrees. - * startang is measured from positive x-axis of Window. - * A positive angextent means a counterclockwise arc; a negative - * angextent means clockwise. - */ -void drawarc (float xcen, float ycen, float rad, float startang, - float angextent); -void fillarc (float xcen, float ycen, float rad, float startang, - float angextent); -void drawellipticarc (float xc, float yc, float radx, float rady, float startang, float angextent); -void fillellipticarc (float xc, float yc, float radx, float rady, float startang, float angextent); - -/* boundx specifies horizontal bounding box. If text won't fit in - * the space specified by boundx (world coordinates) the text isn't drawn. - * That avoids text going everywhere for high zoom levels. - * If you always want the text to display (even if it overwrites lots of - * stuff at high zoom levels), just specify a huge boundx. - */ -void drawtext (float xc, float yc, const char *text, float boundx); - -/* Control what buttons are active (default: all enabled) and - * whether mouse movements and keypresses are sent to callback - * functions (default: disabled). - */ -void set_mouse_move_input (bool turn_on); -void set_keypress_input (bool turn_on); -void enable_or_disable_button (int ibutton, bool enabled); - -/*************** ADVANCED FUNCTIONS *****************/ - -/* Normal users shouldn't have to use draw_message. Should only be - * useful if using non-interactive graphics and you want to redraw - * yourself because of an expose. i - */ -void draw_message (void); - -/* Empties event queue. Can be useful with non-interactive graphics to make - * sure things display. - */ -void flushinput (void); - -/* DRAW_NORMAL is the default mode (overwrite, also known as copy_pen). - * Can use DRAW_XOR for fast rubber-banding. - */ -enum e_draw_mode {DRAW_NORMAL = 0, DRAW_XOR}; -void set_draw_mode (enum e_draw_mode draw_mode); - -/* Change the text on a button. - */ -void change_button_text(const char *button_text, const char *new_button_text); - -/* For debugging only. Get window size etc. */ -void report_structure(t_report*); - - -/**************** Extra functions available only in WIN32. *******/ -#ifdef WIN32 -/* VB: TODO: I should make any generally useful functions below work in - * X11 as well, and probably delete anything else. - */ - -/* Added by William to provide double buffering in Windows */ -void drawtobuffer(void); -void drawtoscreen(void); -void displaybuffer(void); -void drawcurve(t_point *points, int npoints); -void fillcurve(t_point *points, int npoints); -void object_start(int all); -void object_end(); -int pt_on_object(int all, float x, float y); -int findfontsize(float ymax); - -#endif // WIN32 - -#endif // GRAPHICS_H diff --git a/vpr7_x2p/vpr/SRC/base/place_and_route.c b/vpr7_x2p/vpr/SRC/base/place_and_route.c deleted file mode 100644 index 6a73f9cad..000000000 --- a/vpr7_x2p/vpr/SRC/base/place_and_route.c +++ /dev/null @@ -1,869 +0,0 @@ -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "vpr_utils.h" -#include "globals.h" -#include "place_and_route.h" -#include "place.h" -#include "read_place.h" -#include "route_export.h" -#include "draw.h" -#include "stats.h" -#include "check_route.h" -#include "rr_graph.h" -#include "path_delay.h" -#include "net_delay.h" -#include "timing_place.h" -#include "read_xml_arch_file.h" -#include "ReadOptions.h" -#include "route_common.h" -#include "place_macro.h" -#include "verilog_writer.h" -#include "power.h" - -/* CLB PIN REMAP */ -#include "place_clb_pin_remap.h" - -#include "tileable_chan_details_builder.h" - -/******************* Subroutines local to this module ************************/ - -static int binary_search_place_and_route(struct s_placer_opts placer_opts, - char *place_file, char *net_file, char *arch_file, char *route_file, - boolean full_stats, boolean verify_binary_search, - struct s_annealing_sched annealing_sched, - struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, t_chan_width_dist chan_width_dist, - t_model *models, t_direct_inf *directs, int num_directs, float sram_area, - /*Xifan TANG: Switch Segment Pattern Support*/ - t_swseg_pattern_inf* swseg_patterns); - -static float comp_width(t_chan * chan, float x, float separation); - -void post_place_sync(INP int L_num_blocks, - INOUTP const struct s_block block_list[]); - -void free_pb_data(t_pb *pb); - -/************************* Subroutine Definitions ****************************/ - -void place_and_route(enum e_operation operation, - struct s_placer_opts placer_opts, char *place_file, char *net_file, - char *arch_file, char *route_file, - struct s_annealing_sched annealing_sched, - struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, t_chan_width_dist chan_width_dist, - struct s_model *models, - t_direct_inf *directs, int num_directs, float sram_area, - /*Xifan TANG: Switch Segment Pattern Support*/ - t_swseg_pattern_inf* swseg_patterns) { - - /* This routine controls the overall placement and routing of a circuit. */ - char msg[BUFSIZE]; - int width_fac, i; - boolean success, Fc_clipped; - float **net_delay = NULL; - t_slack * slacks = NULL; - t_chunk net_delay_ch = {NULL, 0, NULL}; - - /*struct s_linked_vptr *net_delay_chunk_list_head;*/ - t_ivec **clb_opins_used_locally = NULL; /* [0..num_blocks-1][0..num_class-1] */ - int max_pins_per_clb; - clock_t begin, end; - - Fc_clipped = FALSE; - - max_pins_per_clb = 0; - for (i = 0; i < num_types; i++) { - if (type_descriptors[i].num_pins > max_pins_per_clb) { - max_pins_per_clb = type_descriptors[i].num_pins; - } - } - - if (placer_opts.place_freq == PLACE_NEVER) { - /* Read the placement from a file */ - read_place(place_file, net_file, arch_file, nx, ny, num_blocks, block); - sync_grid_to_blocks(num_blocks, block, nx, ny, grid); - } else { - assert( - (PLACE_ONCE == placer_opts.place_freq) || (PLACE_ALWAYS == placer_opts.place_freq)); - begin = clock(); - try_place(placer_opts, annealing_sched, chan_width_dist, router_opts, - det_routing_arch, segment_inf, timing_inf, directs, num_directs); - print_place(place_file, net_file, arch_file); - end = clock(); -#ifdef CLOCKS_PER_SEC - vpr_printf(TIO_MESSAGE_INFO, "Placement took %g seconds.\n", (float)(end - begin) / CLOCKS_PER_SEC); -#else - vpr_printf(TIO_MESSAGE_INFO, "Placement took %g seconds.\n", (float)(end - begin) / CLK_PER_SEC); -#endif - } - post_place_sync(num_blocks, block); - - /* Xifan TANG: PLACE_CLB_PIN_REMAP */ - if (TRUE == placer_opts.place_clb_pin_remap) { - vpr_printf(TIO_MESSAGE_INFO, "Try remap CLB pins after placement...\n"); - begin = clock(); - try_clb_pin_remap_after_placement(det_routing_arch, - segment_inf, - timing_inf, - num_directs, - directs); - end = clock(); - update_screen(MAJOR, "CLB_PIN_REMAP", PLACEMENT, FALSE); -#ifdef CLOCKS_PER_SEC - vpr_printf(TIO_MESSAGE_INFO, "CLB_PIN_REMAP took %g seconds.\n", (float)(end - begin) / CLOCKS_PER_SEC); -#else - vpr_printf(TIO_MESSAGE_INFO, "CLB_PIN_REMAP took %g seconds.\n", (float)(end - begin) / CLK_PER_SEC); -#endif - } - /* END */ - begin = clock(); - - - fflush(stdout); - - if (!router_opts.doRouting) - return; - - width_fac = router_opts.fixed_channel_width; - - /* If channel width not fixed, use binary search to find min W */ - if (NO_FIXED_CHANNEL_WIDTH == width_fac) { - g_solution_inf.channel_width = binary_search_place_and_route(placer_opts, place_file, net_file, - arch_file, route_file, router_opts.full_stats, - router_opts.verify_binary_search, annealing_sched, router_opts, - det_routing_arch, segment_inf, timing_inf, chan_width_dist, - models, directs, num_directs,sram_area, - /*Xifan TANG: Switch Segment Pattern Support*/ - swseg_patterns); - } else { - g_solution_inf.channel_width = width_fac; - if (det_routing_arch.directionality == UNI_DIRECTIONAL) { - if (width_fac % 2 != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "in pack_place_and_route.c: Given odd chan width (%d) for udsd architecture.\n", - width_fac); - exit(1); - } - } - /* Other constraints can be left to rr_graph to check since this is one pass routing */ - - /* Xifan Tang: W estimation for tileable routing architecture */ - /* Build the segment inf vector */ - std::vector segment_vec; - for (int iseg = 0; iseg < det_routing_arch.num_segment; ++iseg) { - segment_vec.push_back(segment_inf[iseg]); - } - - if (TRUE == router_opts.use_tileable_route_chan_width) { - int adapted_W = adapt_to_tileable_route_chan_width(width_fac, segment_vec); - vpr_printf(TIO_MESSAGE_INFO, - "Adapt routing channel width (%d) to be tileable: %d\n", - width_fac, adapted_W); - width_fac = adapted_W; - } - - /* Allocate the major routing structures. */ - - clb_opins_used_locally = alloc_route_structs(); - - slacks = alloc_and_load_timing_graph(timing_inf); - net_delay = alloc_net_delay(&net_delay_ch, clb_net, - num_nets); - - success = try_route(width_fac, router_opts, det_routing_arch, - segment_inf, timing_inf, net_delay, slacks, chan_width_dist, - clb_opins_used_locally, &Fc_clipped, directs, num_directs, - /*Xifan TANG: Switch Segment Pattern Support*/ - swseg_patterns); - - if (Fc_clipped) { - vpr_printf(TIO_MESSAGE_WARNING, "Fc_output was too high and was clipped to full (maximum) connectivity.\n"); - } - - if (success == FALSE) { - vpr_printf(TIO_MESSAGE_INFO, "Circuit is unrouteable with a channel width factor of %d.\n", width_fac); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - sprintf(msg, "Routing failed with a channel width factor of %d. ILLEGAL routing shown.", width_fac); - } - - else { - check_route(router_opts.route_type, det_routing_arch.num_switch, clb_opins_used_locally); - get_serial_num(); - - vpr_printf(TIO_MESSAGE_INFO, "Circuit successfully routed with a channel width factor of %d.\n", width_fac); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - routing_stats(router_opts.full_stats, router_opts.route_type, - det_routing_arch.num_switch, segment_inf, - det_routing_arch.num_segment, det_routing_arch.R_minW_nmos, - det_routing_arch.R_minW_pmos, - det_routing_arch.directionality, - timing_inf.timing_analysis_enabled, net_delay, slacks, sram_area); - - print_route(route_file); - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_ROUTING_SINK_DELAYS)) { - print_sink_delays(getEchoFileName(E_ECHO_ROUTING_SINK_DELAYS)); - } - - sprintf(msg, "Routing succeeded with a channel width factor of %d.\n\n", - width_fac); - - - } - - init_draw_coords(max_pins_per_clb); - update_screen(MAJOR, msg, ROUTING, timing_inf.timing_analysis_enabled); - - - if (timing_inf.timing_analysis_enabled) { - assert(slacks->slack); - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_POST_FLOW_TIMING_GRAPH)) { - print_timing_graph_as_blif (getEchoFileName(E_ECHO_POST_FLOW_TIMING_GRAPH), - models); - } - - if(GetPostSynthesisOption()) - { - verilog_writer(); - } - - free_timing_graph(slacks); - - assert(net_delay); - free_net_delay(net_delay, &net_delay_ch); - } - - fflush(stdout); - } - - if (clb_opins_used_locally != NULL) { - for (i = 0; i < num_blocks; i++) { - free_ivec_vector(clb_opins_used_locally[i], 0, - block[i].type->num_class - 1); - } - free(clb_opins_used_locally); - clb_opins_used_locally = NULL; - } - - /* Frees up all the data structure used in vpr_utils. */ - free_port_pin_from_blk_pin(); - free_blk_pin_from_port_pin(); - - end = clock(); -#ifdef CLOCKS_PER_SEC - vpr_printf(TIO_MESSAGE_INFO, "Routing took %g seconds.\n", (float) (end - begin) / CLOCKS_PER_SEC); -#else - vpr_printf(TIO_MESSAGE_INFO, "Routing took %g seconds.\n", (float)(end - begin) / CLK_PER_SEC); -#endif - - /*WMF: cleaning up memory usage */ - - /* if (g_heap_free_head) - free(g_heap_free_head); - if (g_trace_free_head) - free(g_trace_free_head); - if (g_linked_f_pointer_free_head) - free(g_linked_f_pointer_free_head);*/ -} - -static int binary_search_place_and_route(struct s_placer_opts placer_opts, - char *place_file, char *net_file, char *arch_file, char *route_file, - boolean full_stats, boolean verify_binary_search, - struct s_annealing_sched annealing_sched, - struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, t_chan_width_dist chan_width_dist, - t_model *models, t_direct_inf *directs, int num_directs, float sram_area, - /*Xifan TANG: Switch Segment Pattern Support*/ - t_swseg_pattern_inf* swseg_patterns) { - - /* This routine performs a binary search to find the minimum number of * - * tracks per channel required to successfully route a circuit, and returns * - * that minimum width_fac. */ - - struct s_trace **best_routing; /* Saves the best routing found so far. */ - int current, low, high, final; - int max_pins_per_clb, i; - boolean success, prev_success, prev2_success, Fc_clipped = FALSE; - char msg[BUFSIZE]; - float **net_delay = NULL; - t_slack * slacks = NULL; - - t_chunk net_delay_ch = {NULL, 0, NULL}; - - /*struct s_linked_vptr *net_delay_chunk_list_head;*/ - t_ivec **clb_opins_used_locally, **saved_clb_opins_used_locally; - - /* [0..num_blocks-1][0..num_class-1] */ - int attempt_count; - int udsd_multiplier; - int warnings; - - t_graph_type graph_type; - - /* Allocate the major routing structures. */ - - if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; - /* Xifan Tang: tileable undirectional rr_graph support */ - } else if (BI_DIRECTIONAL == det_routing_arch.directionality) { - graph_type = GRAPH_BIDIR; - } else if (UNI_DIRECTIONAL == det_routing_arch.directionality) { - if (true == det_routing_arch.tileable) { - graph_type = GRAPH_UNIDIR_TILEABLE; - } else { - graph_type = GRAPH_UNIDIR; - } - } - - max_pins_per_clb = 0; - for (i = 0; i < num_types; i++) { - max_pins_per_clb = std::max(max_pins_per_clb, type_descriptors[i].num_pins); - } - - clb_opins_used_locally = alloc_route_structs(); - best_routing = alloc_saved_routing(clb_opins_used_locally, - &saved_clb_opins_used_locally); - - slacks = alloc_and_load_timing_graph(timing_inf); - net_delay = alloc_net_delay(&net_delay_ch, clb_net, num_nets); - - /* UDSD by AY Start */ - if (det_routing_arch.directionality == BI_DIRECTIONAL) - udsd_multiplier = 1; - else - udsd_multiplier = 2; - /* UDSD by AY End */ - - - if (router_opts.fixed_channel_width != NO_FIXED_CHANNEL_WIDTH) { - current = router_opts.fixed_channel_width + 5 * udsd_multiplier; - low = router_opts.fixed_channel_width - 1 * udsd_multiplier; - } else { - current = max_pins_per_clb + max_pins_per_clb % 2; /* Binary search part */ - /* End */ - low = -1; - } - - /* Build the segment inf vector */ - std::vector segment_vec; - for (int iseg = 0; iseg < det_routing_arch.num_segment; ++iseg) { - segment_vec.push_back(segment_inf[iseg]); - } - - /* Constraints must be checked to not break rr_graph generator */ - if (det_routing_arch.directionality == UNI_DIRECTIONAL) { - if (current % 2 != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "in pack_place_and_route.c: Tried odd chan width (%d) for udsd architecture.\n", - current); - exit(1); - } - } - - else { - if (det_routing_arch.Fs % 3) { - vpr_printf(TIO_MESSAGE_ERROR, "Fs must be three in bidirectional mode.\n"); - exit(1); - } - } - - high = -1; - final = -1; - - attempt_count = 0; - - while (final == -1) { - /* Xifan Tang: W estimation for tileable routing architecture */ - if (TRUE == router_opts.use_tileable_route_chan_width) { - int adapted_W = adapt_to_tileable_route_chan_width(current, segment_vec); - vpr_printf(TIO_MESSAGE_INFO, - "Adapt routing channel width (%d) to be tileable: %d\n", - current, adapted_W); - current = adapted_W; - } - /* Do a early exit when the current equals to high or low, - * This means that the current W has been tried already. We just return a final value (high) - */ - if ( (current == high) || (current == low) ) { - final = high; - break; - } - - vpr_printf(TIO_MESSAGE_INFO, "Using low: %d, high: %d, current: %d\n", low, high, current); - fflush(stdout); - - /* Check if the channel width is huge to avoid overflow. Assume the * - * circuit is unroutable with the current router options if we're * - * going to overflow. */ - if (router_opts.fixed_channel_width != NO_FIXED_CHANNEL_WIDTH) { - if (current > router_opts.fixed_channel_width * 4) { - vpr_printf(TIO_MESSAGE_ERROR, "This circuit appears to be unroutable with the current router options. Last failed at %d.\n", low); - vpr_printf(TIO_MESSAGE_INFO, "Aborting routing procedure.\n"); - exit(1); - } - } else { - if (current > 1000) { - vpr_printf(TIO_MESSAGE_ERROR, "This circuit requires a channel width above 1000, probably is not going to route.\n"); - vpr_printf(TIO_MESSAGE_INFO, "Aborting routing procedure.\n"); - exit(1); - } - } - - if ((current * 3) < det_routing_arch.Fs) { - vpr_printf(TIO_MESSAGE_INFO, "Width factor is now below specified Fs. Stop search.\n"); - final = high; - break; - } - - if (placer_opts.place_freq == PLACE_ALWAYS) { - placer_opts.place_chan_width = current; - try_place(placer_opts, annealing_sched, chan_width_dist, - router_opts, det_routing_arch, segment_inf, timing_inf, - directs, num_directs); - /* Xifan TANG: PLACE_CLB_PIN_REMAP */ - if (TRUE == placer_opts.place_clb_pin_remap) { - vpr_printf(TIO_MESSAGE_INFO, "Try remap CLB pins after placement...\n"); - try_clb_pin_remap_after_placement(det_routing_arch, - segment_inf, - timing_inf, - num_directs, - directs); - } - /* END */ - } - success = try_route(current, router_opts, det_routing_arch, segment_inf, - timing_inf, net_delay, slacks, chan_width_dist, - clb_opins_used_locally, &Fc_clipped, directs, num_directs, - /*Xifan TANG: Switch Segment Pattern Support*/ - swseg_patterns); - attempt_count++; - fflush(stdout); -#if 1 - if (success && (Fc_clipped == FALSE)) { -#else - if (success - && (Fc_clipped == FALSE - || det_routing_arch.Fc_type == FRACTIONAL)) - { -#endif - if (current == high) { - /* Can't go any lower */ - final = current; - } - high = current; - - /* If Fc_output is too high, set to full connectivity but warn the user */ - if (Fc_clipped) { - vpr_printf(TIO_MESSAGE_WARNING, "Fc_output was too high and was clipped to full (maximum) connectivity.\n"); - } - - /* If we're re-placing constantly, save placement in case it is best. */ -#if 0 - if (placer_opts.place_freq == PLACE_ALWAYS) - { - print_place(place_file, net_file, arch_file); - } -#endif - - /* Save routing in case it is best. */ - save_routing(best_routing, clb_opins_used_locally, - saved_clb_opins_used_locally); - - if ((high - low) <= 1 * udsd_multiplier) - final = high; - - if (low != -1) { - current = (high + low) / 2; - - } else { - current = high / 2; /* haven't found lower bound yet */ - } - } else { /* last route not successful */ - if (success && Fc_clipped) { - vpr_printf(TIO_MESSAGE_INFO, "Routing rejected, Fc_output was too high.\n"); - success = FALSE; - } - low = current; - if (high != -1) { - - if ((high - low) <= 1 * udsd_multiplier) - final = high; - - current = (high + low) / 2; - - } else { - if (router_opts.fixed_channel_width != NO_FIXED_CHANNEL_WIDTH) { - /* FOR Wneed = f(Fs) search */ - if (low < router_opts.fixed_channel_width + 30) { - current = low + 5 * udsd_multiplier; - } else { - vpr_printf(TIO_MESSAGE_ERROR, "Aborting: Wneed = f(Fs) search found exceedingly large Wneed (at least %d).\n", low); - exit(1); - } - } else { - current = low * 2; /* Haven't found upper bound yet */ - - } - } - } - current = current + current % udsd_multiplier; - } - - /* The binary search above occassionally does not find the minimum * - * routeable channel width. Sometimes a circuit that will not route * - * in 19 channels will route in 18, due to router flukiness. If * - * verify_binary_search is set, the code below will ensure that FPGAs * - * with channel widths of final-2 and final-3 wil not route * - * successfully. If one does route successfully, the router keeps * - * trying smaller channel widths until two in a row (e.g. 8 and 9) * - * fail. */ - - if (verify_binary_search) { - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Verifying that binary search found min channel width...\n"); - - prev_success = TRUE; /* Actually final - 1 failed, but this makes router */ - /* try final-2 and final-3 even if both fail: safer */ - prev2_success = TRUE; - - current = final - 2; - - while (prev2_success || prev_success) { - if ((router_opts.fixed_channel_width != NO_FIXED_CHANNEL_WIDTH) - && (current < router_opts.fixed_channel_width)) { - break; - } - fflush(stdout); - if (current < 1) - break; - if (placer_opts.place_freq == PLACE_ALWAYS) { - placer_opts.place_chan_width = current; - try_place(placer_opts, annealing_sched, chan_width_dist, - router_opts, det_routing_arch, segment_inf, timing_inf, - directs, num_directs); - /* Xifan TANG: PLACE_CLB_PIN_REMAP */ - if (TRUE == placer_opts.place_clb_pin_remap) { - vpr_printf(TIO_MESSAGE_INFO, "Try remap CLB pins after placement...\n"); - try_clb_pin_remap_after_placement(det_routing_arch, - segment_inf, - timing_inf, - num_directs, - directs); - } - /* END */ - } - success = try_route(current, router_opts, det_routing_arch, - segment_inf, timing_inf, net_delay, slacks, - chan_width_dist, clb_opins_used_locally, &Fc_clipped, directs, num_directs, - /*Xifan TANG: Switch Segment Pattern Support*/ - swseg_patterns); - - if (success && Fc_clipped == FALSE) { - final = current; - save_routing(best_routing, clb_opins_used_locally, - saved_clb_opins_used_locally); - - if (placer_opts.place_freq == PLACE_ALWAYS) { - print_place(place_file, net_file, arch_file); - } - } - - prev2_success = prev_success; - prev_success = success; - current--; - if (det_routing_arch.directionality == UNI_DIRECTIONAL) { - current--; /* width must be even */ - } - } - } - - /* End binary search verification. */ - /* Restore the best placement (if necessary), the best routing, and * - * * the best channel widths for final drawing and statistics output. */ - init_chan(final, chan_width_dist); -#if 0 - if (placer_opts.place_freq == PLACE_ALWAYS) - { - vpr_printf(TIO_MESSAGE_INFO, "Reading best placement back in.\n"); - placer_opts.place_chan_width = final; - read_place(place_file, net_file, arch_file, placer_opts, - router_opts, chan_width_dist, det_routing_arch, - segment_inf, timing_inf); - } -#endif - free_rr_graph(); - - build_rr_graph(graph_type, num_types, type_descriptors, nx, ny, grid, - chan_width_x[0], NULL, - det_routing_arch.switch_block_type, det_routing_arch.Fs, - det_routing_arch.switch_block_sub_type, det_routing_arch.sub_Fs, - det_routing_arch.wire_opposite_side, - det_routing_arch.num_segment, - det_routing_arch.num_switch, segment_inf, - det_routing_arch.global_route_switch, - det_routing_arch.delayless_switch, timing_inf, - det_routing_arch.wire_to_ipin_switch, router_opts.base_cost_type, - directs, num_directs, FALSE, - &warnings, - /*Xifan TANG: Switch Segment Pattern Support*/ - det_routing_arch.num_swseg_pattern, swseg_patterns, TRUE, TRUE); - - restore_routing(best_routing, clb_opins_used_locally, - saved_clb_opins_used_locally); - check_route(router_opts.route_type, det_routing_arch.num_switch, - clb_opins_used_locally); - get_serial_num(); - if (Fc_clipped) { - vpr_printf(TIO_MESSAGE_WARNING, "Best routing Fc_output too high, clipped to full (maximum) connectivity.\n"); - } - vpr_printf(TIO_MESSAGE_INFO, "Best routing used a channel width factor of %d.\n", final); - - routing_stats(full_stats, router_opts.route_type, - det_routing_arch.num_switch, segment_inf, - det_routing_arch.num_segment, det_routing_arch.R_minW_nmos, - det_routing_arch.R_minW_pmos, det_routing_arch.directionality, - timing_inf.timing_analysis_enabled, net_delay, slacks, sram_area); - - print_route(route_file); - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_ROUTING_SINK_DELAYS)) { - print_sink_delays(getEchoFileName(E_ECHO_ROUTING_SINK_DELAYS)); - } - - init_draw_coords(max_pins_per_clb); - sprintf(msg, "Routing succeeded with a channel width factor of %d.", final); - update_screen(MAJOR, msg, ROUTING, timing_inf.timing_analysis_enabled); - - if (timing_inf.timing_analysis_enabled) { - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_POST_FLOW_TIMING_GRAPH)) { - print_timing_graph_as_blif (getEchoFileName(E_ECHO_POST_FLOW_TIMING_GRAPH), models); - } - - if(GetPostSynthesisOption()) - { - verilog_writer(); - } - - free_timing_graph(slacks); - free_net_delay(net_delay, &net_delay_ch); - } - - for (i = 0; i < num_blocks; i++) { - free_ivec_vector(clb_opins_used_locally[i], 0, - block[i].type->num_class - 1); - } - free(clb_opins_used_locally); - clb_opins_used_locally = NULL; - - free_saved_routing(best_routing, saved_clb_opins_used_locally); - fflush(stdout); - - return (final); - -} - -void init_chan(int cfactor, t_chan_width_dist chan_width_dist) { - - /* Assigns widths to channels (in tracks). Minimum one track * - * per channel. io channels are io_rat * maximum in interior * - * tracks wide. The channel distributions read from the architecture * - * file are scaled by cfactor. */ - - float x, separation, chan_width_io; - int nio, i; - t_chan chan_x_dist, chan_y_dist; - - chan_width_io = chan_width_dist.chan_width_io; - chan_x_dist = chan_width_dist.chan_x_dist; - chan_y_dist = chan_width_dist.chan_y_dist; - - /* io channel widths */ - - nio = (int) floor(cfactor * chan_width_io + 0.5); - if (nio == 0) - nio = 1; /* No zero width channels */ - - chan_width_x[0] = chan_width_x[ny] = nio; - chan_width_y[0] = chan_width_y[nx] = nio; - - if (ny > 1) { - separation = 1. / (ny - 2.); /* Norm. distance between two channels. */ - x = 0.; /* This avoids div by zero if ny = 2. */ - chan_width_x[1] = (int) floor( - cfactor * comp_width(&chan_x_dist, x, separation) + 0.5); - - /* No zero width channels */ - chan_width_x[1] = std::max(chan_width_x[1], 1); - - for (i = 1; i < ny - 1; i++) { - x = (float) i / ((float) (ny - 2.)); - chan_width_x[i + 1] = (int) floor( - cfactor * comp_width(&chan_x_dist, x, separation) + 0.5); - chan_width_x[i + 1] = std::max(chan_width_x[i + 1], 1); - } - } - - if (nx > 1) { - separation = 1. / (nx - 2.); /* Norm. distance between two channels. */ - x = 0.; /* Avoids div by zero if nx = 2. */ - chan_width_y[1] = (int) floor( - cfactor * comp_width(&chan_y_dist, x, separation) + 0.5); - - chan_width_y[1] = std::max(chan_width_y[1], 1); - - for (i = 1; i < nx - 1; i++) { - x = (float) i / ((float) (nx - 2.)); - chan_width_y[i + 1] = (int) floor( - cfactor * comp_width(&chan_y_dist, x, separation) + 0.5); - chan_width_y[i + 1] = std::max(chan_width_y[i + 1], 1); - } - } -#ifdef VERBOSE - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "chan_width_x:\n"); - for (i = 0; i <= ny; i++) - vpr_printf(TIO_MESSAGE_INFO, "%d ", chan_width_x[i]); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "chan_width_y:\n"); - for (i = 0; i <= nx; i++) - vpr_printf(TIO_MESSAGE_INFO, "%d ", chan_width_y[i]); - vpr_printf(TIO_MESSAGE_INFO, "\n"); -#endif - -} - -static float comp_width(t_chan * chan, float x, float separation) { - - /* Return the relative channel density. *chan points to a channel * - * functional description data structure, and x is the distance * - * (between 0 and 1) we are across the chip. separation is the * - * distance between two channels, in the 0 to 1 coordinate system. */ - - float val; - - switch (chan->type) { - - case UNIFORM: - val = chan->peak; - break; - - case GAUSSIAN: - val = (x - chan->xpeak) * (x - chan->xpeak) - / (2 * chan->width * chan->width); - val = chan->peak * exp(-val); - val += chan->dc; - break; - - case PULSE: - val = (float) fabs((double) (x - chan->xpeak)); - if (val > chan->width / 2.) { - val = 0; - } else { - val = chan->peak; - } - val += chan->dc; - break; - - case DELTA: - val = x - chan->xpeak; - if (val > -separation / 2. && val <= separation / 2.) - val = chan->peak; - else - val = 0.; - val += chan->dc; - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in comp_width: Unknown channel type %d.\n", chan->type); - exit(1); - break; - } - - return (val); -} - -/* After placement, logical pins for blocks, and nets must be updated to correspond with physical pins of type */ -/* This function should only be called once */ -void post_place_sync(INP int L_num_blocks, - INOUTP const struct s_block block_list[]) { - int iblk, j, k, inet; - t_type_ptr type; - int max_num_block_pins; - - /* Go through each block */ - for (iblk = 0; iblk < L_num_blocks; ++iblk) { - type = block[iblk].type; - assert(type->num_pins % type->capacity == 0); - max_num_block_pins = type->num_pins / type->capacity; - /* Logical location and physical location is offset by z * max_num_block_pins */ - /* Sync blocks and nets */ - for (j = 0; j < max_num_block_pins; j++) { - inet = block[iblk].nets[j]; - if (inet != OPEN && block[iblk].z > 0) { - assert( - block[iblk]. nets[j + block[iblk].z * max_num_block_pins] == OPEN); - block[iblk].nets[j + block[iblk].z * max_num_block_pins] = - block[iblk].nets[j]; - block[iblk].nets[j] = OPEN; - for (k = 0; k <= clb_net[inet].num_sinks; k++) { - if (clb_net[inet].node_block[k] == iblk && clb_net[inet]. node_block_pin[k] == j) { - clb_net[inet].node_block_pin[k] = j - + block[iblk].z * max_num_block_pins; - break; - } - } - assert(k <= clb_net[inet].num_sinks); - } - } - } -} - -void free_pb_data(t_pb *pb) { - int i, j; - const t_pb_type *pb_type; - t_rr_node *temp; - - if (pb == NULL || pb->name == NULL) { - return; - } - - pb_type = pb->pb_graph_node->pb_type; - - /* free existing rr graph for pb */ - if (pb->rr_graph) { - temp = rr_node; - rr_node = pb->rr_graph; - num_rr_nodes = pb->pb_graph_node->total_pb_pins; - free_rr_graph(); - rr_node = temp; - } - - if (pb_type->num_modes > 0) { - /* Free children of pb */ - for (i = 0; i < pb_type->modes[pb->mode].num_pb_type_children; i++) { - for (j = 0; j < pb_type->modes[pb->mode].pb_type_children[i].num_pb; - j++) { - if (pb->child_pbs[i]) { - free_pb_data(&pb->child_pbs[i][j]); - } - } - } - } - - /* Frees all the pb data structures. */ - if (pb->name) { - free(pb->name); - if (pb->child_pbs) { - free(pb->child_pbs); - } - } -} diff --git a/vpr7_x2p/vpr/SRC/base/place_and_route.h b/vpr7_x2p/vpr/SRC/base/place_and_route.h deleted file mode 100644 index 2055bdf46..000000000 --- a/vpr7_x2p/vpr/SRC/base/place_and_route.h +++ /dev/null @@ -1,28 +0,0 @@ -#define INFINITE -1 -#define NOT_FOUND 0 - -#define WNEED 1 -#define WL 2 -#define PROC_TIME 3 - -typedef struct s_fmap_cell { - int fs; /* at this fs */ - int fc; /* at this fc */ - int wneed; /* need wneed to route */ - int wirelength; /* corresponding wirelength of successful routing at wneed */ - int proc_time; - struct s_fmap_cell *next; -} t_fmap_cell; - -void place_and_route(enum e_operation operation, - struct s_placer_opts placer_opts, char *place_file, char *net_file, - char *arch_file, char *route_file, - struct s_annealing_sched annealing_sched, - struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, t_chan_width_dist chan_width_dist, - struct s_model *models, t_direct_inf *directs, int num_directs, float sram_area, - /*Xifan TANG: Switch Segment Pattern Support*/ - t_swseg_pattern_inf* swseg_patterns); - -void init_chan(int cfactor, t_chan_width_dist chan_width_dist); diff --git a/vpr7_x2p/vpr/SRC/base/read_blif.c b/vpr7_x2p/vpr/SRC/base/read_blif.c deleted file mode 100644 index 75008fc3f..000000000 --- a/vpr7_x2p/vpr/SRC/base/read_blif.c +++ /dev/null @@ -1,2019 +0,0 @@ -#include -#include -#include -#include "assert.h" -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "read_blif.h" -#include "arch_types.h" -#include "ReadOptions.h" -#include "hash.h" - -/* PRINT_PIN_NETS */ - -struct s_model_stats { - t_model * model; - int count; -}; - -#define MAX_ATOM_PARSE 200000000 - -/* This source file will read in a FLAT blif netlist consisting * - * of .inputs, .outputs, .names and .latch commands. It currently * - * does not handle hierarchical blif files. Hierarchical * - * blif files can be flattened via the read_blif and write_blif * - * commands of sis. LUT circuits should only have .names commands; * - * there should be no gates. This parser performs limited error * - * checking concerning the consistency of the netlist it obtains. * - * .inputs and .outputs statements must be given; this parser does * - * not infer primary inputs and outputs from non-driven and fanout * - * free nodes. This parser can be extended to do this if necessary, * - * or the sis read_blif and write_blif commands can be used to put a * - * netlist into the standard format. * - * V. Betz, August 25, 1994. * - * Added more error checking, March 30, 1995, V. Betz */ - -static int *num_driver, *temp_num_pins; -static int *logical_block_input_count, *logical_block_output_count; -static int num_blif_models; -static int num_luts = 0, num_latches = 0, num_subckts = 0; - -/* # of .input, .output, .model and .end lines */ -static int ilines, olines, model_lines, endlines; -static struct s_hash **blif_hash; -static char *model = NULL; -static FILE *blif; - -static int add_vpack_net(char *ptr, int type, int bnum, int bport, int bpin, - boolean is_global, int doall); -static void get_blif_tok(char *buffer, int doall, boolean *done, - boolean *add_truth_table, INP t_model* inpad_model, - INP t_model* outpad_model, INP t_model* logic_model, - INP t_model* latch_model, INP t_model* user_models); -static void init_parse(int doall); -static void check_net(boolean sweep_hanging_nets_and_inputs); -static void free_parse(void); -static void io_line(int in_or_out, int doall, t_model *io_model); -static boolean add_lut(int doall, t_model *logic_model); -static void add_latch(int doall, INP t_model *latch_model); -static void add_subckt(int doall, INP t_model *user_models); -static void check_and_count_models(int doall, const char* model_name, - t_model* user_models); -static void load_default_models(INP t_model *library_models, - OUTP t_model** inpad_model, OUTP t_model** outpad_model, - OUTP t_model** logic_model, OUTP t_model** latch_model); -static void read_activity(char * activity_file); -static void read_blif(char *blif_file, boolean sweep_hanging_nets_and_inputs, - t_model *user_models, t_model *library_models, - boolean read_activity_file, char * activity_file); - -static void absorb_buffer_luts(void); -static void compress_netlist(void); -static void show_blif_stats(t_model *user_models, t_model *library_models); -static bool add_activity_to_net(char * net_name, float probability, - float density); - -static void read_blif(char *blif_file, boolean sweep_hanging_nets_and_inputs, - t_model *user_models, t_model *library_models, - boolean read_activity_file, char * activity_file) { - char buffer[BUFSIZE]; - int doall; - boolean done; - boolean add_truth_table; - t_model *inpad_model, *outpad_model, *logic_model, *latch_model; - clock_t begin, end; - - blif = fopen(blif_file, "r"); - if (blif == NULL ) { - vpr_printf(TIO_MESSAGE_ERROR, "Failed to open blif file '%s'.\n", - blif_file); - exit(1); - } - load_default_models(library_models, &inpad_model, &outpad_model, - &logic_model, &latch_model); - - /* doall = 0 means do a counting pass, doall = 1 means allocate and load data structures */ - for (doall = 0; doall <= 1; doall++) { - begin = clock(); - - init_parse(doall); - - end = clock(); -#ifdef CLOCKS_PER_SEC - vpr_printf(TIO_MESSAGE_INFO, - "Loop for doall = %d, init_parse took %g seconds.\n", doall, - (float) (end - begin) / CLOCKS_PER_SEC); -#else - vpr_printf(TIO_MESSAGE_INFO, "Loop for doall = %d, init_parse took %g seconds.\n", doall, (float)(end - begin) / CLK_PER_SEC); -#endif - - begin = clock(); - file_line_number = 0; /* Reset line number. */ - done = FALSE; - add_truth_table = FALSE; - model_lines = 0; - while (my_fgets(buffer, BUFSIZE, blif) != NULL ) { - get_blif_tok(buffer, doall, &done, &add_truth_table, inpad_model, - outpad_model, logic_model, latch_model, user_models); - } - rewind(blif); /* Start at beginning of file again */ - - end = clock(); -#ifdef CLOCKS_PER_SEC - vpr_printf(TIO_MESSAGE_INFO, "Loop for doall = %d took %g seconds.\n", - doall, (float) (end - begin) / CLOCKS_PER_SEC); -#else - vpr_printf(TIO_MESSAGE_INFO, "Loop for doall = %d took %g seconds.\n", doall, (float)(end - begin) / CLK_PER_SEC); -#endif - - } - - /*checks how well the hash function is performing*/ -#ifdef VERBOSE - get_hash_stats(blif_hash, "blif_hash"); -#endif - - fclose(blif); - check_net(sweep_hanging_nets_and_inputs); - - /* Read activity file */ - if (read_activity_file) { - read_activity(activity_file); - } - free_parse(); -} - -static void init_parse(int doall) { - - /* Allocates and initializes the data structures needed for the parse. */ - - int i; - struct s_hash *h_ptr; - - if (!doall) { /* Initialization before first (counting) pass */ - num_logical_nets = 0; - blif_hash = (struct s_hash **) my_calloc(sizeof(struct s_hash *), - HASHSIZE); - } - /* Allocate memory for second (load) pass */ - else { - vpack_net = (struct s_net *) my_calloc(num_logical_nets, - sizeof(struct s_net)); - logical_block = (struct s_logical_block *) my_calloc(num_logical_blocks, - sizeof(struct s_logical_block)); - num_driver = (int *) my_malloc(num_logical_nets * sizeof(int)); - temp_num_pins = (int *) my_malloc(num_logical_nets * sizeof(int)); - - logical_block_input_count = (int *) my_calloc(num_logical_blocks, - sizeof(int)); - logical_block_output_count = (int *) my_calloc(num_logical_blocks, - sizeof(int)); - - for (i = 0; i < num_logical_nets; i++) { - num_driver[i] = 0; - vpack_net[i].num_sinks = 0; - vpack_net[i].name = NULL; - vpack_net[i].node_block = NULL; - vpack_net[i].node_block_port = NULL; - vpack_net[i].node_block_pin = NULL; - vpack_net[i].is_global = FALSE; - } - - for (i = 0; i < num_logical_blocks; i++) { - logical_block[i].index = i; - } - - for (i = 0; i < HASHSIZE; i++) { - h_ptr = blif_hash[i]; - while (h_ptr != NULL ) { - vpack_net[h_ptr->index].node_block = (int *) my_malloc( - h_ptr->count * sizeof(int)); - vpack_net[h_ptr->index].node_block_port = (int *) my_malloc( - h_ptr->count * sizeof(int)); - vpack_net[h_ptr->index].node_block_pin = (int *) my_malloc( - h_ptr->count * sizeof(int)); - - /* For avoiding assigning values beyond end of pins array. */ - temp_num_pins[h_ptr->index] = h_ptr->count; - vpack_net[h_ptr->index].name = my_strdup(h_ptr->name); - h_ptr = h_ptr->next; - } - } -#ifdef PRINT_PIN_NETS - vpr_printf(TIO_MESSAGE_INFO, "i\ttemp_num_pins\n"); - for (i = 0;i < num_logical_nets;i++) { - vpr_printf(TIO_MESSAGE_INFO, "%d\t%d\n",i,temp_num_pins[i]); - } - vpr_printf(TIO_MESSAGE_INFO, "num_logical_nets %d\n", num_logical_nets); -#endif - } - - /* Initializations for both passes. */ - - ilines = 0; - olines = 0; - model_lines = 0; - endlines = 0; - num_p_inputs = 0; - num_p_outputs = 0; - num_luts = 0; - num_latches = 0; - num_logical_blocks = 0; - num_blif_models = 0; - num_subckts = 0; -} - -static void get_blif_tok(char *buffer, int doall, boolean *done, - boolean *add_truth_table, INP t_model* inpad_model, - INP t_model* outpad_model, INP t_model* logic_model, - INP t_model* latch_model, INP t_model* user_models) { - - /* Figures out which, if any token is at the start of this line and * - * takes the appropriate action. */ - -#define BLIF_TOKENS " \t\n" - char *ptr; - char *fn; - struct s_linked_vptr *data; - - ptr = my_strtok(buffer, TOKENS, blif, buffer); - if (ptr == NULL ) - return; - - if (*add_truth_table) { - if (ptr[0] == '0' || ptr[0] == '1' || ptr[0] == '-') { - data = (struct s_linked_vptr*) my_malloc( - sizeof(struct s_linked_vptr)); - fn = ptr; - ptr = my_strtok(NULL, BLIF_TOKENS, blif, buffer); - if (!ptr || strlen(ptr) != 1) { - if (strlen(fn) == 1) { - /* constant generator */ - data->next = - logical_block[num_logical_blocks - 1].truth_table; - data->data_vptr = my_malloc(strlen(fn) + 4); - sprintf((char*) (data->data_vptr), " %s", fn); - logical_block[num_logical_blocks - 1].truth_table = data; - ptr = fn; - } else { - vpr_printf(TIO_MESSAGE_ERROR, - "Unknown truth table data %s %s.\n", fn, ptr); - exit(1); - } - } else { - data->next = logical_block[num_logical_blocks - 1].truth_table; - data->data_vptr = my_malloc(strlen(fn) + 3); - sprintf((char*) data->data_vptr, "%s %s", fn, ptr); - logical_block[num_logical_blocks - 1].truth_table = data; - } - } - } - - if (strcmp(ptr, ".names") == 0) { - *add_truth_table = FALSE; - *add_truth_table = add_lut(doall, logic_model); - return; - } - - if (strcmp(ptr, ".latch") == 0) { - *add_truth_table = FALSE; - add_latch(doall, latch_model); - return; - } - - if (strcmp(ptr, ".model") == 0) { - *add_truth_table = FALSE; - ptr = my_strtok(NULL, TOKENS, blif, buffer); - if (doall) { - if (ptr != NULL ) { - if(model != NULL) { - free(model); - } - model = (char *) my_malloc((strlen(ptr) + 1) * sizeof(char)); - strcpy(model, ptr); - if (blif_circuit_name == NULL ) { - blif_circuit_name = my_strdup(model); - } - } else { - if(model != NULL) { - free(model); - } - model = (char *) my_malloc(sizeof(char)); - model[0] = '\0'; - } - } - - if (model_lines > 0) { - check_and_count_models(doall, ptr, user_models); - } else { - dum_parse(buffer); - } - model_lines++; - return; - } - - if (strcmp(ptr, ".inputs") == 0) { - *add_truth_table = FALSE; - /* packing can only one fully defined model */ - if (model_lines == 1) { - io_line(DRIVER, doall, inpad_model); - *done = (boolean) 1; - } - if (doall) - ilines++; /* Error checking only */ - return; - } - - if (strcmp(ptr, ".outputs") == 0) { - *add_truth_table = FALSE; - /* packing can only one fully defined model */ - if (model_lines == 1) { - io_line(RECEIVER, doall, outpad_model); - *done = (boolean) 1; - } - if (doall) - olines++; /* Make sure only one .output line */ - /* For error checking only */ - return; - } - if (strcmp(ptr, ".end") == 0) { - *add_truth_table = FALSE; - if (doall) { - endlines++; /* Error checking only */ - } - return; - } - - if (strcmp(ptr, ".subckt") == 0) { - *add_truth_table = FALSE; - add_subckt(doall, user_models); - } - - /* Could have numbers following a .names command, so not matching any * - * of the tokens above is not an error. */ - -} - -void dum_parse(char *buf) { - - /* Continue parsing to the end of this (possibly continued) line. */ - - while (my_strtok(NULL, TOKENS, blif, buf) != NULL ) - ; -} - -static boolean add_lut(int doall, t_model *logic_model) { - - /* Adds a LUT as VPACK_COMB from (.names) currently being parsed to the logical_block array. Adds * - * its pins to the nets data structure by calling add_vpack_net. If doall is * - * zero this is a counting pass; if it is 1 this is the final (loading) * - * pass. */ - - char *ptr, **saved_names, buf[BUFSIZE]; - int i, j, output_net_index; - - saved_names = (char**) alloc_matrix(0, logic_model->inputs->size, 0, - BUFSIZE - 1, sizeof(char)); - - num_logical_blocks++; - - /* Count # nets connecting */ - i = 0; - while ((ptr = my_strtok(NULL, TOKENS, blif, buf)) != NULL ) { - if (i > logic_model->inputs->size) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] .names %s ... %s has a LUT size that exceeds the maximum LUT size (%d) of the architecture.\n", - file_line_number, saved_names[0], ptr, - logic_model->inputs->size); - exit(1); - } - strcpy(saved_names[i], ptr); - i++; - } - output_net_index = i - 1; - if (strcmp(saved_names[output_net_index], "unconn") == 0) { - /* unconn is a keyword to pad unused pins, ignore this block */ - free_matrix(saved_names, 0, logic_model->inputs->size, 0, sizeof(char)); - num_logical_blocks--; - return FALSE; - } - - if (!doall) { /* Counting pass only ... */ - for (j = 0; j <= output_net_index; j++) - /* On this pass it doesn't matter if RECEIVER or DRIVER. Just checking if in hash. [0] should be DRIVER */ - add_vpack_net(saved_names[j], RECEIVER, num_logical_blocks - 1, 0, - j, FALSE, doall); - free_matrix(saved_names, 0, logic_model->inputs->size, 0, sizeof(char)); - return FALSE; - } - - logical_block[num_logical_blocks - 1].model = logic_model; - - if (output_net_index > logic_model->inputs->size) { - vpr_printf(TIO_MESSAGE_ERROR, - "LUT size of %d in .blif file is too big for FPGA which has a maximum LUT size of %d.\n", - output_net_index, logic_model->inputs->size); - exit(1); - } - assert(logic_model->inputs->next == NULL); - assert(logic_model->outputs->next == NULL); - assert(logic_model->outputs->size == 1); - - logical_block[num_logical_blocks - 1].input_nets = (int **) my_malloc( - sizeof(int*)); - logical_block[num_logical_blocks - 1].output_nets = (int **) my_malloc( - sizeof(int*)); - logical_block[num_logical_blocks - 1].clock_net = OPEN; - - logical_block[num_logical_blocks - 1].input_nets[0] = (int *) my_malloc( - logic_model->inputs->size * sizeof(int)); - logical_block[num_logical_blocks - 1].output_nets[0] = (int *) my_malloc( - sizeof(int)); - - logical_block[num_logical_blocks - 1].type = VPACK_COMB; - for (i = 0; i < output_net_index; i++) /* Do inputs */ - logical_block[num_logical_blocks - 1].input_nets[0][i] = add_vpack_net( - saved_names[i], RECEIVER, num_logical_blocks - 1, 0, i, FALSE, - doall); - logical_block[num_logical_blocks - 1].output_nets[0][0] = add_vpack_net( - saved_names[output_net_index], DRIVER, num_logical_blocks - 1, 0, 0, - FALSE, doall); - - for (i = output_net_index; i < logic_model->inputs->size; i++) - logical_block[num_logical_blocks - 1].input_nets[0][i] = OPEN; - - logical_block[num_logical_blocks - 1].name = my_strdup( - saved_names[output_net_index]); - logical_block[num_logical_blocks - 1].truth_table = NULL; - num_luts++; - - free_matrix(saved_names, 0, logic_model->inputs->size, 0, sizeof(char)); - return (boolean) doall; -} - -static void add_latch(int doall, INP t_model *latch_model) { - - /* Adds the flipflop (.latch) currently being parsed to the logical_block array. * - * Adds its pins to the nets data structure by calling add_vpack_net. If doall * - * is zero this is a counting pass; if it is 1 this is the final * - * (loading) pass. Blif format for a latch is: * - * .latch * - * The latch pins are in .nets 0 to 2 in the order: Q D CLOCK. */ - - char *ptr, buf[BUFSIZE], saved_names[6][BUFSIZE]; - int i; - - num_logical_blocks++; - - /* Count # parameters, making sure we don't go over 6 (avoids memory corr.) */ - /* Note that we can't rely on the tokens being around unless we copy them. */ - - for (i = 0; i < 6; i++) { - ptr = my_strtok(NULL, TOKENS, blif, buf); - if (ptr == NULL ) - break; - strcpy(saved_names[i], ptr); - } - - if (i != 5) { - vpr_printf(TIO_MESSAGE_ERROR, ".latch does not have 5 parameters.\n"); - vpr_printf(TIO_MESSAGE_ERROR, "Check netlist, line %d.\n", - file_line_number); - exit(1); - } - - if (!doall) { /* If only a counting pass ... */ - add_vpack_net(saved_names[0], RECEIVER, num_logical_blocks - 1, 0, 0, - FALSE, doall); /* D */ - add_vpack_net(saved_names[1], DRIVER, num_logical_blocks - 1, 0, 0, - FALSE, doall); /* Q */ - add_vpack_net(saved_names[3], RECEIVER, num_logical_blocks - 1, 0, 0, - TRUE, doall); /* Clock */ - return; - } - - logical_block[num_logical_blocks - 1].model = latch_model; - logical_block[num_logical_blocks - 1].type = VPACK_LATCH; - - logical_block[num_logical_blocks - 1].input_nets = (int **) my_malloc( - sizeof(int*)); - logical_block[num_logical_blocks - 1].output_nets = (int **) my_malloc( - sizeof(int*)); - - logical_block[num_logical_blocks - 1].input_nets[0] = (int *) my_malloc( - sizeof(int)); - logical_block[num_logical_blocks - 1].output_nets[0] = (int *) my_malloc( - sizeof(int)); - - logical_block[num_logical_blocks - 1].output_nets[0][0] = add_vpack_net( - saved_names[1], DRIVER, num_logical_blocks - 1, 0, 0, FALSE, doall); /* Q */ - logical_block[num_logical_blocks - 1].input_nets[0][0] = add_vpack_net( - saved_names[0], RECEIVER, num_logical_blocks - 1, 0, 0, FALSE, - doall); /* D */ - logical_block[num_logical_blocks - 1].clock_net = add_vpack_net( - saved_names[3], RECEIVER, num_logical_blocks - 1, 0, 0, TRUE, - doall); /* Clock */ - - logical_block[num_logical_blocks - 1].name = my_strdup(saved_names[1]); - logical_block[num_logical_blocks - 1].truth_table = NULL; - - /* Xifan TANG: SPICE Model Support*/ - /* Store the clock trigger type : "re" or "fe"*/ - logical_block[num_logical_blocks - 1].trigger_type = my_strdup(saved_names[2]); - /* Store the initial value */ - logical_block[num_logical_blocks - 1].init_val = my_atoi(saved_names[4]); - /* Add clock identification */ - logical_block[vpack_net[logical_block[num_logical_blocks - 1].clock_net].node_block[0]].is_clock = TRUE; - /*END*/ - - num_latches++; -} - -static void add_subckt(int doall, t_model *user_models) { - char *ptr; - char *close_bracket; - char subckt_name[BUFSIZE]; - char buf[BUFSIZE]; - //fpos_t current_subckt_pos; - int i, j, iparse; - int subckt_index_signals = 0; - char **subckt_signal_name = NULL; - char *port_name, *pin_number; - char **circuit_signal_name = NULL; - char *subckt_logical_block_name = NULL; - short toggle = 0; - int input_net_count, output_net_count, input_port_count, output_port_count; - t_model *cur_model; - t_model_ports *port; - boolean found_subckt_signal; - - num_logical_blocks++; - num_subckts++; - - /* now we have to find the matching subckt */ - /* find the name we are looking for */ - strcpy(subckt_name, my_strtok(NULL, TOKENS, blif, buf)); - /* get all the signals in the form z=r */ - iparse = 0; - while (iparse < MAX_ATOM_PARSE) { - iparse++; - /* Assumption is that it will be "signal1, =, signal1b, spacing, and repeat" */ - ptr = my_strtok(NULL, " \t\n=", blif, buf); - - if (ptr == NULL && toggle == 0) - break; - else if (ptr == NULL && toggle == 1) { - vpr_printf(TIO_MESSAGE_ERROR, - "subckt %s formed incorrectly with signal=signal at %s.\n", - subckt_name, buf); - exit(-1); - } else if (toggle == 0) { - /* ELSE - parse in one or the other */ - /* allocate a new spot for both the circuit_signal name and the subckt_signal name */ - subckt_signal_name = (char**) my_realloc(subckt_signal_name, - (subckt_index_signals + 1) * sizeof(char**)); - circuit_signal_name = (char**) my_realloc(circuit_signal_name, - (subckt_index_signals + 1) * sizeof(char**)); - - /* copy in the subckt_signal name */ - subckt_signal_name[subckt_index_signals] = my_strdup(ptr); - - toggle = 1; - } else if (toggle == 1) { - /* copy in the circuit_signal name */ - circuit_signal_name[subckt_index_signals] = my_strdup(ptr); - if (!doall) { - /* Counting pass, does not matter if driver or receiver and pin number does not matter */ - add_vpack_net(circuit_signal_name[subckt_index_signals], - RECEIVER, num_logical_blocks - 1, 0, 0, FALSE, doall); - } - - toggle = 0; - subckt_index_signals++; - } - } - assert(iparse < MAX_ATOM_PARSE); - /* record the position of the parse so far so when we resume we will move to the next item */ - //if (fgetpos(blif, ¤t_subckt_pos) != 0) { - // vpr_printf(TIO_MESSAGE_ERROR, "In file pointer read - read_blif.c\n"); - // exit(-1); - //} - input_net_count = 0; - output_net_count = 0; - - if (doall) { - /* get the matching model to this subckt */ - - cur_model = user_models; - while (cur_model != NULL ) { - if (strcmp(cur_model->name, subckt_name) == 0) { - break; - } - cur_model = cur_model->next; - } - if (cur_model == NULL ) { - vpr_printf(TIO_MESSAGE_ERROR, - "Did not find matching model to subckt %s.\n", subckt_name); - exit(-1); - } - - /* IF - do all then we need to allocate a string to hold all the subckt info */ - - /* initialize the logical_block structure */ - - /* record model info */ - logical_block[num_logical_blocks - 1].model = cur_model; - - /* allocate space for inputs and initialize all input nets to OPEN */ - input_port_count = 0; - port = cur_model->inputs; - while (port) { - if (!port->is_clock) { - input_port_count++; - } - port = port->next; - } - logical_block[num_logical_blocks - 1].input_nets = (int**) my_malloc( - input_port_count * sizeof(int *)); - - port = cur_model->inputs; - while (port) { - if (port->is_clock) { - /* Clock ports are different from regular input ports, skip */ - port = port->next; - continue; - } - assert(port->size >= 0); - logical_block[num_logical_blocks - 1].input_nets[port->index] = - (int*) my_malloc(port->size * sizeof(int)); - for (j = 0; j < port->size; j++) { - logical_block[num_logical_blocks - 1].input_nets[port->index][j] = - OPEN; - } - port = port->next; - } - assert(port == NULL || (port->is_clock && port->next == NULL)); - - /* allocate space for outputs and initialize all output nets to OPEN */ - output_port_count = 0; - port = cur_model->outputs; - while (port) { - port = port->next; - output_port_count++; - } - logical_block[num_logical_blocks - 1].output_nets = (int**) my_malloc( - output_port_count * sizeof(int *)); - - port = cur_model->outputs; - while (port) { - assert(port->size >= 0); - logical_block[num_logical_blocks - 1].output_nets[port->index] = - (int*) my_malloc(port->size * sizeof(int)); - for (j = 0; j < port->size; j++) { - logical_block[num_logical_blocks - 1].output_nets[port->index][j] = - OPEN; - } - port = port->next; - } - assert(port == NULL); - - /* initialize clock data */ - logical_block[num_logical_blocks - 1].clock_net = OPEN; - - logical_block[num_logical_blocks - 1].type = VPACK_COMB; - logical_block[num_logical_blocks - 1].truth_table = NULL; - logical_block[num_logical_blocks - 1].name = NULL; - - /* setup the index signal if open or not */ - - for (i = 0; i < subckt_index_signals; i++) { - found_subckt_signal = FALSE; - /* determine the port name and the pin_number of the subckt */ - port_name = my_strdup(subckt_signal_name[i]); - pin_number = strrchr(port_name, '['); - if (pin_number == NULL ) { - pin_number = "0"; /* default to 0 */ - } else { - /* The pin numbering is port_name[pin_number] so need to go one to the right of [ then NULL out ] */ - *pin_number = '\0'; - pin_number++; - close_bracket = pin_number; - while (*close_bracket != '\0' && *close_bracket != ']') { - close_bracket++; - } - *close_bracket = '\0'; - } - - port = cur_model->inputs; - while (port) { - if (strcmp(port_name, port->name) == 0) { - if (found_subckt_signal) { - vpr_printf(TIO_MESSAGE_ERROR, - "Two instances of %s subckt signal found in subckt %s.\n", - subckt_signal_name[i], subckt_name); - } - found_subckt_signal = TRUE; - if (port->is_clock) { - assert( - logical_block[num_logical_blocks-1].clock_net == OPEN); - assert(my_atoi(pin_number) == 0); - logical_block[num_logical_blocks - 1].clock_net = - add_vpack_net(circuit_signal_name[i], RECEIVER, - num_logical_blocks - 1, port->index, - my_atoi(pin_number), TRUE, doall); - - /* Add clock identification */ - logical_block[vpack_net[logical_block[num_logical_blocks - 1].clock_net].node_block[0]].is_clock = TRUE; - } else { - logical_block[num_logical_blocks - 1].input_nets[port->index][my_atoi( - pin_number)] = add_vpack_net( - circuit_signal_name[i], RECEIVER, - num_logical_blocks - 1, port->index, - my_atoi(pin_number), FALSE, doall); - input_net_count++; - } - } - port = port->next; - } - - port = cur_model->outputs; - while (port) { - if (strcmp(port_name, port->name) == 0) { - if (found_subckt_signal) { - vpr_printf(TIO_MESSAGE_ERROR, - "Two instances of %s subckt signal found in subckt %s.\n", - subckt_signal_name[i], subckt_name); - } - found_subckt_signal = TRUE; - logical_block[num_logical_blocks - 1].output_nets[port->index][my_atoi( - pin_number)] = add_vpack_net(circuit_signal_name[i], - DRIVER, num_logical_blocks - 1, port->index, - my_atoi(pin_number), FALSE, doall); - if (subckt_logical_block_name == NULL - && circuit_signal_name[i] != NULL ) { - subckt_logical_block_name = circuit_signal_name[i]; - } - output_net_count++; - } - port = port->next; - } - - /* record the name to be first output net parsed */ - if(logical_block[num_logical_blocks - 1].name == NULL) { - /* Xifan TANG: add the index of logical block in its name ! - * Name format is _lb - * If not, there could be two pbs having the same name during packing! - */ - if (NULL == subckt_logical_block_name) { - if (i == (subckt_index_signals - 1)) { - /* If this is the last signal and still there is no name for this subckt - * we give a default name. - * Actually, this should not never happen, elsewhere this is a block with no fan-out - */ - logical_block[num_logical_blocks - 1].name = (char*)my_malloc(sizeof(char)* - (6 + 3 + 5 + 1)); - sprintf(logical_block[num_logical_blocks - 1].name, "noname_lb%d", - num_logical_blocks -1); - } - } else { - logical_block[num_logical_blocks - 1].name = (char*)my_malloc(sizeof(char)* - (strlen(subckt_logical_block_name) + 3 + 5 + 1)); - /* I do lazy job here, assume 5 bits for the index, whose range is [0, 32767] - * This can be improved by using itoa - */ - sprintf(logical_block[num_logical_blocks - 1].name, "%s_lb%d", - subckt_logical_block_name, num_logical_blocks -1); - - } - /* logical_block[num_logical_blocks - 1].name = my_strdup( - subckt_logical_block_name); */ - } - - if (!found_subckt_signal) { - vpr_printf(TIO_MESSAGE_ERROR, "Unknown subckt port %s.\n", - subckt_signal_name[i]); - exit(1); - } - free(port_name); - } - } - - for (i = 0; i < subckt_index_signals; i++) { - free(subckt_signal_name[i]); - free(circuit_signal_name[i]); - } - free(subckt_signal_name); - free(circuit_signal_name); - - /* now that you've done the analysis, move the file pointer back */ - //if (fsetpos(blif, ¤t_subckt_pos) != 0) { - // vpr_printf(TIO_MESSAGE_ERROR, "In moving back file pointer - read_blif.c\n"); - // exit(-1); - //} -} - -static void io_line(int in_or_out, int doall, t_model *io_model) { - - /* Adds an input or output logical_block to the logical_block data structures. * - * in_or_out: DRIVER for input, RECEIVER for output. * - * doall: 1 for final pass when structures are loaded. 0 for * - * first pass when hash table is built and pins, nets, etc. are counted. */ - - char *ptr; - char buf2[BUFSIZE]; - int nindex, len, iparse; - - iparse = 0; - while (iparse < MAX_ATOM_PARSE) { - iparse++; - ptr = my_strtok(NULL, TOKENS, blif, buf2); - if (ptr == NULL ) - return; - num_logical_blocks++; - - nindex = add_vpack_net(ptr, in_or_out, num_logical_blocks - 1, 0, 0, - FALSE, doall); - /* zero offset indexing */ - if (!doall) - continue; /* Just counting things when doall == 0 */ - - logical_block[num_logical_blocks - 1].clock_net = OPEN; - logical_block[num_logical_blocks - 1].input_nets = NULL; - logical_block[num_logical_blocks - 1].output_nets = NULL; - logical_block[num_logical_blocks - 1].model = io_model; - - len = strlen(ptr); - if (in_or_out == RECEIVER) { /* output pads need out: prefix - * to make names unique from LUTs */ - logical_block[num_logical_blocks - 1].name = (char *) my_malloc( - (len + 1 + 4) * sizeof(char)); /* Space for out: at start */ - strcpy(logical_block[num_logical_blocks - 1].name, "out:"); - strcat(logical_block[num_logical_blocks - 1].name, ptr); - logical_block[num_logical_blocks - 1].input_nets = - (int **) my_malloc(sizeof(int*)); - logical_block[num_logical_blocks - 1].input_nets[0] = - (int *) my_malloc(sizeof(int)); - logical_block[num_logical_blocks - 1].input_nets[0][0] = OPEN; - } else { - assert(in_or_out == DRIVER); - logical_block[num_logical_blocks - 1].name = (char *) my_malloc( - (len + 1) * sizeof(char)); - strcpy(logical_block[num_logical_blocks - 1].name, ptr); - logical_block[num_logical_blocks - 1].output_nets = - (int **) my_malloc(sizeof(int*)); - logical_block[num_logical_blocks - 1].output_nets[0] = - (int *) my_malloc(sizeof(int)); - logical_block[num_logical_blocks - 1].output_nets[0][0] = OPEN; - } - - if (in_or_out == DRIVER) { /* processing .inputs line */ - num_p_inputs++; - logical_block[num_logical_blocks - 1].type = VPACK_INPAD; - logical_block[num_logical_blocks - 1].output_nets[0][0] = nindex; - } else { /* processing .outputs line */ - num_p_outputs++; - logical_block[num_logical_blocks - 1].type = VPACK_OUTPAD; - logical_block[num_logical_blocks - 1].input_nets[0][0] = nindex; - } - logical_block[num_logical_blocks - 1].truth_table = NULL; - } - assert(iparse < MAX_ATOM_PARSE); -} - -static void check_and_count_models(int doall, const char* model_name, - t_model *user_models) { - fpos_t start_pos; - t_model *user_model; - - num_blif_models++; - if (doall) { - /* get start position to do two passes on model */ - if (fgetpos(blif, &start_pos) != 0) { - vpr_printf(TIO_MESSAGE_ERROR, - "in file pointer read - read_blif.c\n"); - exit(-1); - } - - /* get corresponding architecture model */ - user_model = user_models; - while (user_model) { - if (0 == strcmp(model_name, user_model->name)) { - break; - } - user_model = user_model->next; - } - if (user_model == NULL ) { - vpr_printf(TIO_MESSAGE_ERROR, - "No corresponding model %s in architecture description.\n", - model_name); - exit(1); - } - - /* check ports */ - } -} - -static int add_vpack_net(char *ptr, int type, int bnum, int bport, int bpin, - boolean is_global, int doall) { - - /* This routine is given a vpack_net name in *ptr, either DRIVER or RECEIVER * - * specifying whether the logical_block number (bnum) and the output pin (bpin) is driving this * - * vpack_net or in the fan-out and doall, which is 0 for the counting pass * - * and 1 for the loading pass. It updates the vpack_net data structure and * - * returns the vpack_net number so the calling routine can update the logical_block * - * data structure. */ - - struct s_hash *h_ptr, *prev_ptr; - int index, j, nindex; - - if (strcmp(ptr, "open") == 0) { - vpr_printf(TIO_MESSAGE_ERROR, - "net name \"open\" is a reserved keyword in VPR."); - exit(1); - } - - if (strcmp(ptr, "unconn") == 0) { - return OPEN; - } - index = hash_value(ptr); - - if (doall) { - if (type == RECEIVER && !is_global) { - logical_block_input_count[bnum]++; - } else if (type == DRIVER) { - logical_block_output_count[bnum]++; - } - } - - h_ptr = blif_hash[index]; - prev_ptr = h_ptr; - - while (h_ptr != NULL ) { - if (strcmp(h_ptr->name, ptr) == 0) { /* Net already in hash table */ - nindex = h_ptr->index; - - if (!doall) { /* Counting pass only */ - (h_ptr->count)++; - return (nindex); - } - - if (type == DRIVER) { - num_driver[nindex]++; - j = 0; /* Driver always in position 0 of pinlist */ - } else { - vpack_net[nindex].num_sinks++; - if ((num_driver[nindex] < 0) || (num_driver[nindex] > 1)) { - vpr_printf(TIO_MESSAGE_ERROR, - "Number of drivers for net #%d (%s) has %d drivers.\n", - nindex, ptr, num_driver[index]); - } - j = vpack_net[nindex].num_sinks; - - /* num_driver is the number of signal drivers of this vpack_net. * - * should always be zero or 1 unless the netlist is bad. */ - if ((vpack_net[nindex].num_sinks - num_driver[nindex]) - >= temp_num_pins[nindex]) { - vpr_printf(TIO_MESSAGE_ERROR, - "Net #%d (%s) has no driver and will cause memory corruption.\n", - nindex, ptr); - exit(1); - } - } - vpack_net[nindex].node_block[j] = bnum; - vpack_net[nindex].node_block_port[j] = bport; - vpack_net[nindex].node_block_pin[j] = bpin; - vpack_net[nindex].is_global = is_global; - return (nindex); - } - prev_ptr = h_ptr; - h_ptr = h_ptr->next; - } - - /* Net was not in the hash table. */ - - if (doall == 1) { - vpr_printf(TIO_MESSAGE_ERROR, - "in add_vpack_net: The second (load) pass could not find vpack_net %s in the symbol table.\n", - ptr); - exit(1); - } - - /* Add the vpack_net (only counting pass will add nets to symbol table). */ - - num_logical_nets++; - h_ptr = (struct s_hash *) my_malloc(sizeof(struct s_hash)); - if (prev_ptr == NULL ) { - blif_hash[index] = h_ptr; - } else { - prev_ptr->next = h_ptr; - } - h_ptr->next = NULL; - h_ptr->index = num_logical_nets - 1; - h_ptr->count = 1; - h_ptr->name = my_strdup(ptr); - return (h_ptr->index); -} - -void echo_input(char *blif_file, char *echo_file, t_model *library_models) { - - /* Echo back the netlist data structures to file input.echo to * - * allow the user to look at the internal state of the program * - * and check the parsing. */ - - int i, j; - FILE *fp; - t_model_ports *port; - t_model *latch_model; - t_model *logic_model; - t_model *cur; - int *lut_distribution; - int num_absorbable_latch; - int inet; - - cur = library_models; - logic_model = latch_model = NULL; - while (cur) { - if (strcmp(cur->name, MODEL_LOGIC) == 0) { - logic_model = cur; - assert(logic_model->inputs->next == NULL); - } else if (strcmp(cur->name, MODEL_LATCH) == 0) { - latch_model = cur; - assert(latch_model->inputs->size == 1); - } - cur = cur->next; - } - - lut_distribution = (int*) my_calloc(logic_model->inputs[0].size + 1, - sizeof(int)); - num_absorbable_latch = 0; - for (i = 0; i < num_logical_blocks; i++) { - if (logical_block[i].model == logic_model) { - if (logic_model == NULL ) - continue; - for (j = 0; j < logic_model->inputs[0].size; j++) { - if (logical_block[i].input_nets[0][j] == OPEN) { - break; - } - } - lut_distribution[j]++; - } else if (logical_block[i].model == latch_model) { - if (latch_model == NULL ) - continue; - inet = logical_block[i].input_nets[0][0]; - if (vpack_net[inet].num_sinks == 1 - && logical_block[vpack_net[inet].node_block[0]].model - == logic_model) { - num_absorbable_latch++; - } - } - } - - vpr_printf(TIO_MESSAGE_INFO, "Input netlist file: '%s', model: %s\n", - blif_file, model); - vpr_printf(TIO_MESSAGE_INFO, "Primary inputs: %d, primary outputs: %d\n", - num_p_inputs, num_p_outputs); - vpr_printf(TIO_MESSAGE_INFO, "LUTs: %d, latches: %d, subckts: %d\n", - num_luts, num_latches, num_subckts); - vpr_printf(TIO_MESSAGE_INFO, "# standard absorbable latches: %d\n", - num_absorbable_latch); - vpr_printf(TIO_MESSAGE_INFO, "\t"); - for (i = 0; i < logic_model->inputs[0].size + 1; i++) { - if (i > 0) - vpr_printf(TIO_MESSAGE_DIRECT, ", "); - vpr_printf(TIO_MESSAGE_DIRECT, "LUT size %d = %d", i, - lut_distribution[i]); - } - vpr_printf(TIO_MESSAGE_DIRECT, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Total blocks: %d, total nets: %d\n", - num_logical_blocks, num_logical_nets); - - fp = my_fopen(echo_file, "w", 0); - - fprintf(fp, "Input netlist file: '%s', model: %s\n", blif_file, model); - fprintf(fp, - "num_p_inputs: %d, num_p_outputs: %d, num_luts: %d, num_latches: %d\n", - num_p_inputs, num_p_outputs, num_luts, num_latches); - fprintf(fp, "num_logical_blocks: %d, num_logical_nets: %d\n", - num_logical_blocks, num_logical_nets); - - fprintf(fp, "\nNet\tName\t\t#Pins\tDriver\tRecvs.\n"); - for (i = 0; i < num_logical_nets; i++) { - fprintf(fp, "\n%d\t%s\t", i, vpack_net[i].name); - if (strlen(vpack_net[i].name) < 8) - fprintf(fp, "\t"); /* Name field is 16 chars wide */ - fprintf(fp, "%d", vpack_net[i].num_sinks + 1); - for (j = 0; j <= vpack_net[i].num_sinks; j++) - fprintf(fp, "\t(%d,%d,%d)", vpack_net[i].node_block[j], - vpack_net[i].node_block_port[j], - vpack_net[i].node_block_pin[j]); - } - - fprintf(fp, "\n\nBlocks\t\tBlock type legend:\n"); - fprintf(fp, "\t\tINPAD = %d\tOUTPAD = %d\n", VPACK_INPAD, VPACK_OUTPAD); - fprintf(fp, "\t\tCOMB = %d\tLATCH = %d\n", VPACK_COMB, VPACK_LATCH); - fprintf(fp, "\t\tEMPTY = %d\n", VPACK_EMPTY); - - for (i = 0; i < num_logical_blocks; i++) { - fprintf(fp, "\nblock %d %s ", i, logical_block[i].name); - fprintf(fp, "\ttype: %d ", logical_block[i].type); - fprintf(fp, "\tmodel name: %s\n", logical_block[i].model->name); - - port = logical_block[i].model->inputs; - - while (port) { - fprintf(fp, "\tinput port: %s \t", port->name); - for (j = 0; j < port->size; j++) { - if (logical_block[i].input_nets[port->index][j] == OPEN) - fprintf(fp, "OPEN "); - else - fprintf(fp, "%d ", - logical_block[i].input_nets[port->index][j]); - } - fprintf(fp, "\n"); - port = port->next; - } - - port = logical_block[i].model->outputs; - while (port) { - fprintf(fp, "\toutput port: %s \t", port->name); - for (j = 0; j < port->size; j++) { - if (logical_block[i].output_nets[port->index][j] == OPEN) { - fprintf(fp, "OPEN "); - } else { - fprintf(fp, "%d ", - logical_block[i].output_nets[port->index][j]); - } - } - fprintf(fp, "\n"); - port = port->next; - } - - fprintf(fp, "\tclock net: %d\n", logical_block[i].clock_net); - } - fclose(fp); -} - -/* load default vpack models (inpad, outpad, logic) */ -static void load_default_models(INP t_model *library_models, - OUTP t_model** inpad_model, OUTP t_model** outpad_model, - OUTP t_model** logic_model, OUTP t_model** latch_model) { - t_model *cur_model; - cur_model = library_models; - *inpad_model = *outpad_model = *logic_model = *latch_model = NULL; - while (cur_model) { - if (strcmp(MODEL_INPUT, cur_model->name) == 0) { - assert(cur_model->inputs == NULL); - assert(cur_model->outputs->next == NULL); - assert(cur_model->outputs->size == 1); - *inpad_model = cur_model; - } else if (strcmp(MODEL_OUTPUT, cur_model->name) == 0) { - assert(cur_model->outputs == NULL); - assert(cur_model->inputs->next == NULL); - assert(cur_model->inputs->size == 1); - *outpad_model = cur_model; - } else if (strcmp(MODEL_LOGIC, cur_model->name) == 0) { - assert(cur_model->inputs->next == NULL); - assert(cur_model->outputs->next == NULL); - assert(cur_model->outputs->size == 1); - *logic_model = cur_model; - } else if (strcmp(MODEL_LATCH, cur_model->name) == 0) { - assert(cur_model->outputs->next == NULL); - assert(cur_model->outputs->size == 1); - *latch_model = cur_model; - } else { - assert(0); - } - cur_model = cur_model->next; - } -} - -static void check_net(boolean sweep_hanging_nets_and_inputs) { - - /* Checks the input netlist for obvious errors. */ - - int i, j, k, error, iblk, ipin, iport, inet, L_check_net; - boolean found; - int count_inputs, count_outputs; - int explicit_vpack_models; - t_model_ports *port; - struct s_linked_vptr *p_io_removed; - int removed_nets; - int count_unconn_blocks; - - explicit_vpack_models = num_blif_models + 1; - - error = 0; - removed_nets = 0; - - if (ilines != explicit_vpack_models) { - vpr_printf(TIO_MESSAGE_ERROR, "Found %d .inputs lines; expected %d.\n", - ilines, explicit_vpack_models); - error++; - } - - if (olines != explicit_vpack_models) { - vpr_printf(TIO_MESSAGE_ERROR, "Found %d .outputs lines; expected %d.\n", - olines, explicit_vpack_models); - error++; - } - - if (model_lines != explicit_vpack_models) { - vpr_printf(TIO_MESSAGE_ERROR, "Found %d .model lines; expected %d.\n", - model_lines, num_blif_models + 1); - error++; - } - - if (endlines != explicit_vpack_models) { - vpr_printf(TIO_MESSAGE_ERROR, "Found %d .end lines; expected %d.\n", - endlines, explicit_vpack_models); - error++; - } - for (i = 0; i < num_logical_nets; i++) { - - if (num_driver[i] != 1) { - vpr_printf(TIO_MESSAGE_ERROR, - "vpack_net %s has %d signals driving it.\n", - vpack_net[i].name, num_driver[i]); - error++; - } - - if (vpack_net[i].num_sinks == 0) { - - /* If this is an input pad, it is unused and I just remove it with * - * a warning message. Lots of the mcnc circuits have this problem. - - Also, subckts from ODIN often have unused driven nets - */ - - iblk = vpack_net[i].node_block[0]; - iport = vpack_net[i].node_block_port[0]; - ipin = vpack_net[i].node_block_pin[0]; - - assert((vpack_net[i].num_sinks - num_driver[i]) == -1); - - /* All nets should connect to inputs of block except output pads */ - if (logical_block[iblk].type != VPACK_OUTPAD) { - if (sweep_hanging_nets_and_inputs) { - removed_nets++; - vpack_net[i].node_block[0] = OPEN; - vpack_net[i].node_block_port[0] = OPEN; - vpack_net[i].node_block_pin[0] = OPEN; - logical_block[iblk].output_nets[iport][ipin] = OPEN; - logical_block_output_count[iblk]--; - } else { - vpr_printf(TIO_MESSAGE_WARNING, - "vpack_net %s has no fanout.\n", vpack_net[i].name); - } - continue; - } - } - - if (strcmp(vpack_net[i].name, "open") == 0 - || strcmp(vpack_net[i].name, "unconn") == 0) { - vpr_printf(TIO_MESSAGE_ERROR, - "vpack_net #%d has the reserved name %s.\n", i, - vpack_net[i].name); - error++; - } - - for (j = 0; j <= vpack_net[i].num_sinks; j++) { - iblk = vpack_net[i].node_block[j]; - iport = vpack_net[i].node_block_port[j]; - ipin = vpack_net[i].node_block_pin[j]; - if (ipin == OPEN) { - /* Clocks are not connected to regular pins on a block hence open */ - L_check_net = logical_block[iblk].clock_net; - if (L_check_net != i) { - vpr_printf(TIO_MESSAGE_ERROR, - "Clock net for block %s #%d is net %s #%d but connecting net is %s #%d.\n", - logical_block[iblk].name, iblk, - vpack_net[L_check_net].name, L_check_net, - vpack_net[i].name, i); - error++; - } - - } else { - if (j == 0) { - L_check_net = logical_block[iblk].output_nets[iport][ipin]; - if (L_check_net != i) { - vpr_printf(TIO_MESSAGE_ERROR, - "Output net for block %s #%d is net %s #%d but connecting net is %s #%d.\n", - logical_block[iblk].name, iblk, - vpack_net[L_check_net].name, L_check_net, - vpack_net[i].name, i); - error++; - } - } else { - if (vpack_net[i].is_global) { - L_check_net = logical_block[iblk].clock_net; - } else { - L_check_net = - logical_block[iblk].input_nets[iport][ipin]; - } - if (L_check_net != i) { - vpr_printf(TIO_MESSAGE_ERROR, - "Input net for block %s #%d is net %s #%d but connecting net is %s #%d.\n", - logical_block[iblk].name, iblk, - vpack_net[L_check_net].name, L_check_net, - vpack_net[i].name, i); - error++; - } - } - } - } - } - vpr_printf(TIO_MESSAGE_INFO, "Swept away %d nets with no fanout.\n", - removed_nets); - count_unconn_blocks = 0; - for (i = 0; i < num_logical_blocks; i++) { - /* This block has no output and is not an output pad so it has no use, hence we remove it */ - if ((logical_block_output_count[i] == 0) - && (logical_block[i].type != VPACK_OUTPAD)) { - vpr_printf(TIO_MESSAGE_WARNING, - "logical_block %s #%d has no fanout.\n", - logical_block[i].name, i); - if (sweep_hanging_nets_and_inputs - && (logical_block[i].type == VPACK_INPAD)) { - logical_block[i].type = VPACK_EMPTY; - vpr_printf(TIO_MESSAGE_INFO, "Removing input.\n"); - p_io_removed = (struct s_linked_vptr*) my_malloc( - sizeof(struct s_linked_vptr)); - p_io_removed->data_vptr = my_strdup(logical_block[i].name); - p_io_removed->next = circuit_p_io_removed; - circuit_p_io_removed = p_io_removed; - continue; - } else { - count_unconn_blocks++; - vpr_printf(TIO_MESSAGE_WARNING, - "Sweep hanging nodes in your logic synthesis tool because VPR can not do this yet.\n"); - } - } - count_inputs = 0; - count_outputs = 0; - port = logical_block[i].model->inputs; - while (port) { - if (port->is_clock) { - port = port->next; - continue; - } - - for (j = 0; j < port->size; j++) { - if (logical_block[i].input_nets[port->index][j] == OPEN) - continue; - count_inputs++; - inet = logical_block[i].input_nets[port->index][j]; - found = FALSE; - for (k = 1; k <= vpack_net[inet].num_sinks; k++) { - if (vpack_net[inet].node_block[k] == i) { - if (vpack_net[inet].node_block_port[k] == port->index) { - if (vpack_net[inet].node_block_pin[k] == j) { - found = TRUE; - } - } - } - } - assert(found == TRUE); - } - port = port->next; - } - assert(count_inputs == logical_block_input_count[i]); - logical_block[i].used_input_pins = count_inputs; - - port = logical_block[i].model->outputs; - while (port) { - for (j = 0; j < port->size; j++) { - if (logical_block[i].output_nets[port->index][j] == OPEN) - continue; - count_outputs++; - inet = logical_block[i].output_nets[port->index][j]; - vpack_net[inet].is_const_gen = FALSE; - if (count_inputs == 0 && logical_block[i].type != VPACK_INPAD - && logical_block[i].type != VPACK_OUTPAD - && logical_block[i].clock_net == OPEN) { - vpr_printf(TIO_MESSAGE_INFO, - "Net is a constant generator: %s.\n", - vpack_net[inet].name); - vpack_net[inet].is_const_gen = TRUE; - } - found = FALSE; - if (vpack_net[inet].node_block[0] == i) { - if (vpack_net[inet].node_block_port[0] == port->index) { - if (vpack_net[inet].node_block_pin[0] == j) { - found = TRUE; - } - } - } - assert(found == TRUE); - } - port = port->next; - } - assert(count_outputs == logical_block_output_count[i]); - - if (logical_block[i].type == VPACK_LATCH) { - if (logical_block_input_count[i] != 1) { - vpr_printf(TIO_MESSAGE_ERROR, - "Latch #%d with output %s has %d input pin(s), expected one (D).\n", - i, logical_block[i].name, logical_block_input_count[i]); - error++; - } - if (logical_block_output_count[i] != 1) { - vpr_printf(TIO_MESSAGE_ERROR, - "Latch #%d with output %s has %d output pin(s), expected one (Q).\n", - i, logical_block[i].name, - logical_block_output_count[i]); - error++; - } - if (logical_block[i].clock_net == OPEN) { - vpr_printf(TIO_MESSAGE_ERROR, - "Latch #%d with output %s has no clock.\n", i, - logical_block[i].name); - error++; - } - } - - else if (logical_block[i].type == VPACK_INPAD) { - if (logical_block_input_count[i] != 0) { - vpr_printf(TIO_MESSAGE_ERROR, - "IO inpad logical_block #%d name %s of type %d" "has %d input pins.\n", - i, logical_block[i].name, logical_block[i].type, - logical_block_input_count[i]); - error++; - } - if (logical_block_output_count[i] != 1) { - vpr_printf(TIO_MESSAGE_ERROR, - "IO inpad logical_block #%d name %s of type %d" "has %d output pins.\n", - i, logical_block[i].name, logical_block[i].type, - logical_block_output_count[i]); - error++; - } - if (logical_block[i].clock_net != OPEN) { - vpr_printf(TIO_MESSAGE_ERROR, - "IO inpad #%d with output %s has clock.\n", i, - logical_block[i].name); - error++; - } - } else if (logical_block[i].type == VPACK_OUTPAD) { - if (logical_block_input_count[i] != 1) { - vpr_printf(TIO_MESSAGE_ERROR, - "io outpad logical_block #%d name %s of type %d" "has %d input pins.\n", - i, logical_block[i].name, logical_block[i].type, - logical_block_input_count[i]); - error++; - } - if (logical_block_output_count[i] != 0) { - vpr_printf(TIO_MESSAGE_ERROR, - "io outpad logical_block #%d name %s of type %d" "has %d output pins.\n", - i, logical_block[i].name, logical_block[i].type, - logical_block_output_count[i]); - error++; - } - if (logical_block[i].clock_net != OPEN) { - vpr_printf(TIO_MESSAGE_ERROR, - "io outpad #%d with name %s has clock.\n", i, - logical_block[i].name); - error++; - } - } else if (logical_block[i].type == VPACK_COMB) { - if (logical_block_input_count[i] <= 0) { - vpr_printf(TIO_MESSAGE_WARNING, - "logical_block #%d with output %s has only %d pin.\n", - i, logical_block[i].name, logical_block_input_count[i]); - - if (logical_block_input_count[i] < 0) { - error++; - } else { - if (logical_block_output_count[i] > 0) { - vpr_printf(TIO_MESSAGE_WARNING, - "Block contains output -- may be a constant generator.\n"); - } else { - vpr_printf(TIO_MESSAGE_WARNING, - "Block contains no output.\n"); - } - } - } - - if (strcmp(logical_block[i].model->name, MODEL_LOGIC) == 0) { - if (logical_block_output_count[i] != 1) { - vpr_printf(TIO_MESSAGE_WARNING, - "Logical_block #%d name %s of model %s has %d output pins instead of 1.\n", - i, logical_block[i].name, - logical_block[i].model->name, - logical_block_output_count[i]); - } - } - } else { - vpr_printf(TIO_MESSAGE_ERROR, - "Unknown type for logical_block #%d %s.\n", i, - logical_block[i].name); - } - } - vpr_printf(TIO_MESSAGE_INFO, "%d unconnected blocks in input netlist.\n", count_unconn_blocks); - - if (error != 0) { - vpr_printf(TIO_MESSAGE_ERROR, - "Found %d fatal errors in the input netlist.\n", error); - exit(1); - } -} - -static void free_parse(void) { - - /* Release memory needed only during blif network parsing. */ - - int i; - struct s_hash *h_ptr, *temp_ptr; - - for (i = 0; i < HASHSIZE; i++) { - h_ptr = blif_hash[i]; - while (h_ptr != NULL ) { - free((void *) h_ptr->name); - temp_ptr = h_ptr->next; - free((void *) h_ptr); - h_ptr = temp_ptr; - } - } - free((void *) num_driver); - free((void *) blif_hash); - free((void *) temp_num_pins); -} - -static void absorb_buffer_luts(void) { - /* This routine uses a simple pattern matching algorithm to remove buffer LUTs where possible (single-input LUTs that are programmed to be a wire) */ - - int bnum, in_blk, out_blk, ipin, out_net, in_net; - int removed = 0; - - /* Pin ordering for the clb blocks (1 VPACK_LUT + 1 FF in each logical_block) is * - * output, n VPACK_LUT inputs, clock input. */ - - for (bnum = 0; bnum < num_logical_blocks; bnum++) { - if (strcmp(logical_block[bnum].model->name, "names") == 0) { - if (logical_block[bnum].truth_table != NULL - && logical_block[bnum].truth_table->data_vptr) { - if (strcmp("0 0", - (char*) logical_block[bnum].truth_table->data_vptr) == 0 - || strcmp("1 1", - (char*) logical_block[bnum].truth_table->data_vptr) - == 0) { - for (ipin = 0; - ipin < logical_block[bnum].model->inputs->size; - ipin++) { - if (logical_block[bnum].input_nets[0][ipin] == OPEN) - break; - } - assert(ipin == 1); - - assert(logical_block[bnum].clock_net == OPEN); - assert(logical_block[bnum].model->inputs->next == NULL); - assert(logical_block[bnum].model->outputs->size == 1); - assert(logical_block[bnum].model->outputs->next == NULL); - - in_net = logical_block[bnum].input_nets[0][0]; /* Net driving the buffer */ - out_net = logical_block[bnum].output_nets[0][0]; /* Net the buffer us driving */ - out_blk = vpack_net[out_net].node_block[1]; - in_blk = vpack_net[in_net].node_block[0]; - - assert(in_net != OPEN); - assert(out_net != OPEN); - assert(out_blk != OPEN); - assert(in_blk != OPEN); - - /* TODO: Make this handle general cases, due to time reasons I can only handle buffers with single outputs */ - if (vpack_net[out_net].num_sinks == 1) { - for (ipin = 1; ipin <= vpack_net[in_net].num_sinks; - ipin++) { - if (vpack_net[in_net].node_block[ipin] == bnum) { - break; - } - } - assert(ipin <= vpack_net[in_net].num_sinks); - - vpack_net[in_net].node_block[ipin] = - vpack_net[out_net].node_block[1]; /* New output */ - vpack_net[in_net].node_block_port[ipin] = - vpack_net[out_net].node_block_port[1]; - vpack_net[in_net].node_block_pin[ipin] = - vpack_net[out_net].node_block_pin[1]; - - assert( - logical_block[out_blk].input_nets[vpack_net[out_net].node_block_port[1]][vpack_net[out_net].node_block_pin[1]] == out_net); - logical_block[out_blk].input_nets[vpack_net[out_net].node_block_port[1]][vpack_net[out_net].node_block_pin[1]] = - in_net; - - vpack_net[out_net].node_block[0] = OPEN; /* This vpack_net disappears; mark. */ - vpack_net[out_net].node_block_pin[0] = OPEN; /* This vpack_net disappears; mark. */ - vpack_net[out_net].node_block_port[0] = OPEN; /* This vpack_net disappears; mark. */ - vpack_net[out_net].num_sinks = 0; /* This vpack_net disappears; mark. */ - - logical_block[bnum].type = VPACK_EMPTY; /* Mark logical_block that had LUT */ - - /* error checking */ - for (ipin = 0; ipin <= vpack_net[out_net].num_sinks; - ipin++) { - assert(vpack_net[out_net].node_block[ipin] != bnum); - } - removed++; - } - } - } - } - } - vpr_printf(TIO_MESSAGE_INFO, "Removed %d LUT buffers.\n", removed); -} - -static void compress_netlist(void) { - - /* This routine removes all the VPACK_EMPTY blocks and OPEN nets that * - * may have been left behind post synthesis. After this * - * routine, all the VPACK blocks that exist in the netlist * - * are in a contiguous list with no unused spots. The same * - * goes for the list of nets. This means that blocks and nets * - * have to be renumbered somewhat. */ - - int inet, iblk, index, ipin, new_num_nets, new_num_blocks, i; - int *net_remap, *block_remap; - int L_num_nets; - t_model_ports *port; - struct s_linked_vptr *tvptr, *next; - - new_num_nets = 0; - new_num_blocks = 0; - net_remap = (int *) my_malloc(num_logical_nets * sizeof(int)); - block_remap = (int *) my_malloc(num_logical_blocks * sizeof(int)); - - for (inet = 0; inet < num_logical_nets; inet++) { - if (vpack_net[inet].node_block[0] != OPEN) { - net_remap[inet] = new_num_nets; - new_num_nets++; - } else { - net_remap[inet] = OPEN; - } - } - - for (iblk = 0; iblk < num_logical_blocks; iblk++) { - if (logical_block[iblk].type != VPACK_EMPTY) { - block_remap[iblk] = new_num_blocks; - new_num_blocks++; - } else { - block_remap[iblk] = OPEN; - } - } - - if (new_num_nets != num_logical_nets - || new_num_blocks != num_logical_blocks) { - - for (inet = 0; inet < num_logical_nets; inet++) { - if (vpack_net[inet].node_block[0] != OPEN) { - index = net_remap[inet]; - vpack_net[index] = vpack_net[inet]; - for (ipin = 0; ipin <= vpack_net[index].num_sinks; ipin++) { - vpack_net[index].node_block[ipin] = - block_remap[vpack_net[index].node_block[ipin]]; - } - } else { - free(vpack_net[inet].name); - free(vpack_net[inet].node_block); - free(vpack_net[inet].node_block_port); - free(vpack_net[inet].node_block_pin); - } - } - - num_logical_nets = new_num_nets; - vpack_net = (struct s_net *) my_realloc(vpack_net, - num_logical_nets * sizeof(struct s_net)); - - for (iblk = 0; iblk < num_logical_blocks; iblk++) { - if (logical_block[iblk].type != VPACK_EMPTY) { - index = block_remap[iblk]; - if (index != iblk) { - logical_block[index] = logical_block[iblk]; - logical_block[index].index = index; /* array index moved */ - } - - L_num_nets = 0; - port = logical_block[index].model->inputs; - while (port) { - for (ipin = 0; ipin < port->size; ipin++) { - if (port->is_clock) { - assert( - port->size == 1 && port->index == 0 && ipin == 0); - if (logical_block[index].clock_net == OPEN) - continue; - logical_block[index].clock_net = - net_remap[logical_block[index].clock_net]; - } else { - if (logical_block[index].input_nets[port->index][ipin] - == OPEN) - continue; - logical_block[index].input_nets[port->index][ipin] = - net_remap[logical_block[index].input_nets[port->index][ipin]]; - } - L_num_nets++; - } - port = port->next; - } - - port = logical_block[index].model->outputs; - while (port) { - for (ipin = 0; ipin < port->size; ipin++) { - if (logical_block[index].output_nets[port->index][ipin] - == OPEN) - continue; - logical_block[index].output_nets[port->index][ipin] = - net_remap[logical_block[index].output_nets[port->index][ipin]]; - L_num_nets++; - } - port = port->next; - } - } - - else { - free(logical_block[iblk].name); - port = logical_block[iblk].model->inputs; - i = 0; - while (port) { - if (!port->is_clock) { - if (logical_block[iblk].input_nets) { - if (logical_block[iblk].input_nets[i]) { - free(logical_block[iblk].input_nets[i]); - logical_block[iblk].input_nets[i] = NULL; - } - } - i++; - } - port = port->next; - } - if (logical_block[iblk].input_nets) - free(logical_block[iblk].input_nets); - port = logical_block[iblk].model->outputs; - i = 0; - while (port) { - if (logical_block[iblk].output_nets) { - if (logical_block[iblk].output_nets[i]) { - free(logical_block[iblk].output_nets[i]); - logical_block[iblk].output_nets[i] = NULL; - } - } - i++; - port = port->next; - } - if (logical_block[iblk].output_nets) - free(logical_block[iblk].output_nets); - tvptr = logical_block[iblk].truth_table; - while (tvptr != NULL ) { - if (tvptr->data_vptr) - free(tvptr->data_vptr); - next = tvptr->next; - free(tvptr); - tvptr = next; - } - } - } - - vpr_printf(TIO_MESSAGE_INFO, "Sweeped away %d nodes.\n", - num_logical_blocks - new_num_blocks); - - num_logical_blocks = new_num_blocks; - logical_block = (struct s_logical_block *) my_realloc(logical_block, - num_logical_blocks * sizeof(struct s_logical_block)); - } - - /* Now I have to recompute the number of primary inputs and outputs, since * - * some inputs may have been unused and been removed. No real need to * - * recount primary outputs -- it's just done as defensive coding. */ - - num_p_inputs = 0; - num_p_outputs = 0; - - for (iblk = 0; iblk < num_logical_blocks; iblk++) { - if (logical_block[iblk].type == VPACK_INPAD) - num_p_inputs++; - else if (logical_block[iblk].type == VPACK_OUTPAD) - num_p_outputs++; - } - - free(net_remap); - free(block_remap); -} - -/* Read blif file and perform basic sweep/accounting on it - * - power_opts: Power options, can be NULL - */ -void read_and_process_blif(char *blif_file, - boolean sweep_hanging_nets_and_inputs, t_model *user_models, - t_model *library_models, boolean read_activity_file, char * activity_file) { - - /* begin parsing blif input file */ - read_blif(blif_file, sweep_hanging_nets_and_inputs, user_models, - library_models, read_activity_file, activity_file); - - /* TODO: Do check blif here - eg. - for (i = 0; i < num_logical_blocks; i++) { - if (logical_block[i].model->num_inputs > max_subblock_inputs) { - vpr_printf(TIO_MESSAGE_ERROR, "logical_block %s of model %s has %d inputs but architecture only supports subblocks up to %d inputs.\n", - logical_block[i].name, logical_block[i].model->name, logical_block[i].model->num_inputs, max_subblock_inputs); - exit(1); - } - } - */ - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_BLIF_INPUT)) { - echo_input(blif_file, getEchoFileName(E_ECHO_BLIF_INPUT), - library_models); - } else - ; - - absorb_buffer_luts(); - compress_netlist(); /* remove unused inputs */ - - /* NB: It's important to mark clocks and such *after* compressing the * - * netlist because the vpack_net numbers, etc. may be changed by removing * - * unused inputs . */ - - show_blif_stats(user_models, library_models); - free(logical_block_input_count); - free(logical_block_output_count); - free(model); - logical_block_input_count = NULL; - logical_block_output_count = NULL; - model = NULL; -} - -/* Output blif statistics */ -static void show_blif_stats(t_model *user_models, t_model *library_models) { - struct s_model_stats *model_stats; - struct s_model_stats *lut_model; - int num_model_stats; - t_model *cur; - int MAX_LUT_INPUTS; - int i, j, iblk, ipin, num_pins; - int *num_lut_of_size; - - /* Store data structure for all models in FPGA */ - num_model_stats = 0; - - cur = library_models; - while (cur) { - num_model_stats++; - cur = cur->next; - } - - cur = user_models; - while (cur) { - num_model_stats++; - cur = cur->next; - } - - model_stats = (struct s_model_stats*) my_calloc(num_model_stats, - sizeof(struct s_model_stats)); - - num_model_stats = 0; - - lut_model = NULL; - cur = library_models; - while (cur) { - model_stats[num_model_stats].model = cur; - if (strcmp(cur->name, "names") == 0) { - lut_model = &model_stats[num_model_stats]; - } - num_model_stats++; - cur = cur->next; - } - - cur = user_models; - while (cur) { - model_stats[num_model_stats].model = cur; - num_model_stats++; - cur = cur->next; - } - - /* Gather statistics from circuit */ - MAX_LUT_INPUTS = 0; - for (iblk = 0; iblk < num_logical_blocks; iblk++) { - if (strcmp(logical_block[iblk].model->name, "names") == 0) { - MAX_LUT_INPUTS = logical_block[iblk].model->inputs->size; - break; - } - } - num_lut_of_size = (int*) my_calloc(MAX_LUT_INPUTS + 1, sizeof(int)); - - for (i = 0; i < num_logical_blocks; i++) { - for (j = 0; j < num_model_stats; j++) { - if (logical_block[i].model == model_stats[j].model) { - break; - } - } - assert(j < num_model_stats); - model_stats[j].count++; - if (&model_stats[j] == lut_model) { - num_pins = 0; - for (ipin = 0; ipin < logical_block[i].model->inputs->size; - ipin++) { - if (logical_block[i].input_nets[0][ipin] != OPEN) { - num_pins++; - } - } - num_lut_of_size[num_pins]++; - } - } - - /* Print blif circuit stats */ - - vpr_printf(TIO_MESSAGE_INFO, "BLIF circuit stats:\n"); - - for (i = 0; i <= MAX_LUT_INPUTS; i++) { - vpr_printf(TIO_MESSAGE_INFO, "\t%d LUTs of size %d\n", - num_lut_of_size[i], i); - } - for (i = 0; i < num_model_stats; i++) { - vpr_printf(TIO_MESSAGE_INFO, "\t%d of type %s\n", model_stats[i].count, - model_stats[i].model->name); - } - - free(model_stats); - free(num_lut_of_size); -} - -static void read_activity(char * activity_file) { - int net_idx; - bool fail; - char buf[BUFSIZE]; - char * ptr; - char * word1; - char * word2; - char * word3; - - FILE * act_file_hdl; - - if (num_logical_nets == 0) { - printf("Error reading activity file. Must read netlist first\n"); - exit(-1); - } - - for (net_idx = 0; net_idx < num_logical_nets; net_idx++) { - if (!vpack_net[net_idx].net_power) { - vpack_net[net_idx].net_power = new t_net_power; - } - vpack_net[net_idx].net_power->probability = -1.0; - vpack_net[net_idx].net_power->density = -1.0; - } - - act_file_hdl = my_fopen(activity_file, "r", FALSE); - if (act_file_hdl == NULL ) { - printf("Error: could not open activity file: %s\n", activity_file); - exit(-1); - } - - fail = FALSE; - ptr = my_fgets(buf, BUFSIZE, act_file_hdl); - while (ptr != NULL ) { - word1 = strtok(buf, TOKENS); - word2 = strtok(NULL, TOKENS); - word3 = strtok(NULL, TOKENS); - //printf("word1:%s|word2:%s|word3:%s\n", word1, word2, word3); - fail |= add_activity_to_net(word1, atof(word2), atof(word3)); - - ptr = my_fgets(buf, BUFSIZE, act_file_hdl); - } - fclose(act_file_hdl); - - /* Make sure all nets have an activity value */ - for (net_idx = 0; net_idx < num_logical_nets; net_idx++) { - if (!vpack_net[net_idx].net_power - || vpack_net[net_idx].net_power->probability < 0.0 - || vpack_net[net_idx].net_power->density < 0.0) { - printf("Error: Activity file does not contain signal %s\n", - vpack_net[net_idx].name); - fail = TRUE; - } - } - - if (fail) { - exit(-1); - } -} - -bool add_activity_to_net(char * net_name, float probability, float density) { - int hash_idx, net_idx; - struct s_hash * h_ptr; - - hash_idx = hash_value(net_name); - h_ptr = blif_hash[hash_idx]; - - while (h_ptr != NULL ) { - if (strcmp(h_ptr->name, net_name) == 0) { - net_idx = h_ptr->index; - vpack_net[net_idx].net_power->probability = probability; - vpack_net[net_idx].net_power->density = density; - return false; - } - h_ptr = h_ptr->next; - } - - printf( - "Error: net %s found in activity file, but it does not exist in the .blif file.\n", - net_name); - return true; -} diff --git a/vpr7_x2p/vpr/SRC/base/read_blif.h b/vpr7_x2p/vpr/SRC/base/read_blif.h deleted file mode 100644 index b9d6643b6..000000000 --- a/vpr7_x2p/vpr/SRC/base/read_blif.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef READ_BLIF_H -#define READ_BLIF_H - -void read_and_process_blif(char *blif_file, - boolean sweep_hanging_nets_and_inputs, t_model *user_models, - t_model *library_models, boolean read_activity_file, - char * activity_file); -void echo_input(char *blif_file, char *echo_file, t_model *library_models); -void dum_parse(char *buf); - -#endif /*READ_BLIF_H*/ diff --git a/vpr7_x2p/vpr/SRC/base/read_netlist.c b/vpr7_x2p/vpr/SRC/base/read_netlist.c deleted file mode 100644 index 3d56ae74d..000000000 --- a/vpr7_x2p/vpr/SRC/base/read_netlist.c +++ /dev/null @@ -1,1381 +0,0 @@ -/** - * Author: Jason Luu - * Date: May 2009 - * - * Read a circuit netlist in XML format and populate the netlist data structures for VPR - */ - -#include -#include -#include -#include "util.h" -#include "hash.h" -#include "vpr_types.h" -#include "vpr_utils.h" -#include "ReadLine.h" -#include "globals.h" -#include "ezxml.h" -#include "read_xml_util.h" -#include "read_netlist.h" -#include "pb_type_graph.h" -#include "cluster_legality.h" -#include "token.h" -#include "rr_graph.h" - -static void processPorts(INOUTP ezxml_t Parent, INOUTP t_pb* pb, - INOUTP t_rr_node *rr_graph, INOUTP t_pb** rr_node_to_pb_mapping, INP struct s_hash **vpack_net_hash); - -static void processPb(INOUTP ezxml_t Parent, INOUTP t_pb* pb, - INOUTP t_rr_node *rr_graph, INOUTP t_pb **rr_node_to_pb_mapping, INOUTP int *num_primitives, - INP struct s_hash **vpack_net_hash, INP struct s_hash **logical_block_hash, INP int cb_index); - -static void processComplexBlock(INOUTP ezxml_t Parent, INOUTP t_block *cb, - INP int index, INOUTP int *num_primitives, INP const t_arch *arch, INP struct s_hash **vpack_net_hash, INP struct s_hash **logical_block_hash); -static struct s_net *alloc_and_init_netlist_from_hash(INP int ncount, - INOUTP struct s_hash **nhash); - -static int add_net_to_hash(INOUTP struct s_hash **nhash, INP char *net_name, - INOUTP int *ncount); - -static void load_external_nets_and_cb(INP int L_num_blocks, - INP struct s_block block_list[], INP int ncount, - INP struct s_net nlist[], OUTP int *ext_ncount, - OUTP struct s_net **ext_nets, INP char **circuit_clocks); - -static void load_internal_cb_nets(INOUTP t_pb *top_level, - INP t_pb_graph_node *pb_graph_node, INOUTP t_rr_node *rr_graph, - INOUTP int * curr_net); - -static void alloc_internal_cb_nets(INOUTP t_pb *top_level, - INP t_pb_graph_node *pb_graph_node, INOUTP t_rr_node *rr_graph, - INP int pass); - -static void load_internal_cb_rr_graph_net_nums(INP t_rr_node * cur_rr_node, - INP t_rr_node * rr_graph, INOUTP struct s_net * nets, - INOUTP int * curr_net, INOUTP int * curr_sink); - -static void mark_constant_generators(INP int L_num_blocks, - INP struct s_block block_list[], INP int ncount, - INOUTP struct s_net nlist[]); - -static void mark_constant_generators_rec(INP t_pb *pb, INP t_rr_node *rr_graph, - INOUTP struct s_net nlist[]); - -/** - * Initializes the block_list with info from a netlist - * net_file - Name of the netlist file to read - * num_blocks - number of CLBs in netlist - * block_list - array of blocks in netlist [0..num_blocks - 1] - * num_nets - number of nets in netlist - * net_list - nets in netlist [0..num_nets - 1] - */ -void read_netlist(INP const char *net_file, INP const t_arch *arch, - OUTP int *L_num_blocks, OUTP struct s_block *block_list[], - OUTP int *L_num_nets, OUTP struct s_net *net_list[]) { - ezxml_t Cur, Prev, Top; - int i; - const char *Prop; - int bcount; - struct s_block *blist; - int ext_ncount; - struct s_net *ext_nlist; - struct s_hash **vpack_net_hash, **logical_block_hash, *temp_hash; - char **circuit_inputs, **circuit_outputs, **circuit_clocks; - int Count, Len; - - int num_primitives = 0; - - /* Parse the file */ - vpr_printf(TIO_MESSAGE_INFO, "Begin parsing packed FPGA netlist file.\n"); - Top = ezxml_parse_file(net_file); - if (NULL == Top) { - vpr_printf(TIO_MESSAGE_ERROR, "Unable to load netlist file '%s'.\n", net_file); - exit(1); - } - vpr_printf(TIO_MESSAGE_INFO, "Finished parsing packed FPGA netlist file.\n"); - - /* Root node should be block */ - CheckElement(Top, "block"); - - /* Check top-level netlist attributes */ - Prop = FindProperty(Top, "name", TRUE); - vpr_printf(TIO_MESSAGE_INFO, "Netlist generated from file '%s'.\n", Prop); - ezxml_set_attr(Top, "name", NULL); - - Prop = FindProperty(Top, "instance", TRUE); - if (strcmp(Prop, "FPGA_packed_netlist[0]") != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Expected instance to be \"FPGA_packed_netlist[0]\", found %s.", - Top->line, Prop); - exit(1); - } - ezxml_set_attr(Top, "instance", NULL); - - /* Parse top-level netlist I/Os */ - Cur = FindElement(Top, "inputs", TRUE); - circuit_inputs = GetNodeTokens(Cur); - FreeNode(Cur); - Cur = FindElement(Top, "outputs", TRUE); - circuit_outputs = GetNodeTokens(Cur); - FreeNode(Cur); - - Cur = FindElement(Top, "clocks", TRUE); - CountTokensInString(Cur->txt, &Count, &Len); - if (Count > 0) { - circuit_clocks = GetNodeTokens(Cur); - } else { - circuit_clocks = NULL; - } - FreeNode(Cur); - - /* Parse all CLB blocks and all nets*/ - bcount = CountChildren(Top, "block", 1); - blist = (struct s_block *) my_calloc(bcount, sizeof(t_block)); - - /* create quick hash look up for vpack_net and logical_block - Also reset logical block data structure for pb - */ - vpack_net_hash = alloc_hash_table(); - logical_block_hash = alloc_hash_table(); - for (i = 0; i < num_logical_nets; i++) { - temp_hash = insert_in_hash_table(vpack_net_hash, vpack_net[i].name, i); - assert(temp_hash->count == 1); - } - for (i = 0; i < num_logical_blocks; i++) { - temp_hash = insert_in_hash_table(logical_block_hash, logical_block[i].name, i); - logical_block[i].pb = NULL; - assert(temp_hash->count == 1); - } - - /* Prcoess netlist */ - - Cur = Top->child; - i = 0; - while (Cur) { - if (0 == strcmp(Cur->name, "block")) { - CheckElement(Cur, "block"); - processComplexBlock(Cur, blist, i, &num_primitives, arch, vpack_net_hash, logical_block_hash); - Prev = Cur; - Cur = Cur->next; - FreeNode(Prev); - i++; - } else { - Cur = Cur->next; - } - } - assert(i == bcount); - assert(num_primitives == num_logical_blocks); - - /* Error check */ - for (i = 0; i < num_logical_blocks; i++) { - if (logical_block[i].pb == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, ".blif file and .net file do not match, .net file missing atom %s.\n", - logical_block[i].name); - exit(1); - } - } - /* TODO: Add additional check to make sure net connections match */ - - - mark_constant_generators(bcount, blist, num_logical_nets, vpack_net); - load_external_nets_and_cb(bcount, blist, num_logical_nets, vpack_net, &ext_ncount, - &ext_nlist, circuit_clocks); - - /* TODO: create this function later - check_top_IO_matches_IO_blocks(circuit_inputs, circuit_outputs, circuit_clocks, blist, bcount); - */ - - FreeTokens(&circuit_inputs); - if (circuit_outputs) - FreeTokens(&circuit_outputs); - if (circuit_clocks) - FreeTokens(&circuit_clocks); - FreeNode(Top); - - /* load mapping between external nets and all nets */ - /* jluu TODO: Should use local variables here then assign to globals later, clean up later */ - clb_to_vpack_net_mapping = (int *) my_malloc(ext_ncount * sizeof(int)); - vpack_to_clb_net_mapping = (int *) my_malloc(num_logical_nets * sizeof(int)); - for (i = 0; i < num_logical_nets; i++) { - vpack_to_clb_net_mapping[i] = OPEN; - } - - for (i = 0; i < ext_ncount; i++) { - temp_hash = get_hash_entry(vpack_net_hash, ext_nlist[i].name); - assert(temp_hash != NULL); - clb_to_vpack_net_mapping[i] = temp_hash->index; - vpack_to_clb_net_mapping[temp_hash->index] = i; - } - - /* Return blocks and nets */ - *L_num_blocks = bcount; - *block_list = blist; - *L_num_nets = ext_ncount; - *net_list = ext_nlist; - - free_hash_table(logical_block_hash); - free_hash_table(vpack_net_hash); -} - -/** - * XML parser to populate CLB info and to update nets with the nets of this CLB - * Parent - XML tag for this CLB - * clb - Array of CLBs in the netlist - * index - index of the CLB to allocate and load information into - * vpack_net_hash - hashtable of all nets in blif netlist - * logical_block_hash - hashtable of all atoms in blif netlist - */ -static void processComplexBlock(INOUTP ezxml_t Parent, INOUTP t_block *cb, - INP int index, INOUTP int *num_primitives, INP const t_arch *arch, INP struct s_hash **vpack_net_hash, INP struct s_hash **logical_block_hash) - { - - const char *Prop; - boolean found; - int num_tokens = 0; - t_token *tokens; - int i; - const t_pb_type * pb_type = NULL; - - /* parse cb attributes */ - cb[index].pb = (t_pb*)my_calloc(1, sizeof(t_pb)); - - Prop = FindProperty(Parent, "name", TRUE); - cb[index].name = my_strdup(Prop); - cb[index].pb->name = my_strdup(Prop); - ezxml_set_attr(Parent, "name", NULL); - - Prop = FindProperty(Parent, "instance", TRUE); - tokens = GetTokensFromString(Prop, &num_tokens); - ezxml_set_attr(Parent, "instance", NULL); - if (num_tokens != 4 || tokens[0].type != TOKEN_STRING - || tokens[1].type != TOKEN_OPEN_SQUARE_BRACKET - || tokens[2].type != TOKEN_INT - || tokens[3].type != TOKEN_CLOSE_SQUARE_BRACKET) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Unknown syntax for instance %s in %s. Expected pb_type[instance_number].\n", - Parent->line, Prop, Parent->name); - exit(1); - } - assert(my_atoi(tokens[2].data) == index); - found = FALSE; - for (i = 0; i < num_types; i++) { - if (strcmp(type_descriptors[i].name, tokens[0].data) == 0) { - cb[index].type = &type_descriptors[i]; - pb_type = cb[index].type->pb_type; - found = TRUE; - break; - } - } - if (!found) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Unknown cb type %s for cb %s #%d.\n", - Parent->line, Prop, cb[index].name, index); - exit(1); - } - - /* Parse all pbs and CB internal nets*/ - cb[index].pb->logical_block = OPEN; - cb[index].pb->pb_graph_node = cb[index].type->pb_graph_head; - num_rr_nodes = cb[index].pb->pb_graph_node->total_pb_pins; - rr_node = (t_rr_node*)my_calloc((num_rr_nodes * 2) + cb[index].type->pb_type->num_input_pins - + cb[index].type->pb_type->num_output_pins + cb[index].type->pb_type->num_clock_pins, - sizeof(t_rr_node)); - alloc_and_load_rr_graph_for_pb_graph_node(cb[index].pb->pb_graph_node, arch, - 0); - cb[index].pb->rr_node_to_pb_mapping = (t_pb **)my_calloc(cb[index].type->pb_graph_head->total_pb_pins, sizeof(t_pb *)); - cb[index].pb->rr_graph = rr_node; - - Prop = FindProperty(Parent, "mode", TRUE); - ezxml_set_attr(Parent, "mode", NULL); - - found = FALSE; - for (i = 0; i < pb_type->num_modes; i++) { - if (strcmp(Prop, pb_type->modes[i].name) == 0) { - cb[index].pb->mode = i; - found = TRUE; - } - } - if (!found) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Unknown mode %s for cb %s #%d.\n", - Parent->line, Prop, cb[index].name, index); - exit(1); - } - - processPb(Parent, cb[index].pb, cb[index].pb->rr_graph, cb[index].pb->rr_node_to_pb_mapping, num_primitives, vpack_net_hash, logical_block_hash, index); - - cb[index].nets = (int *)my_malloc(cb[index].type->num_pins * sizeof(int)); - for (i = 0; i < cb[index].type->num_pins; i++) { - cb[index].nets[i] = OPEN; - } - alloc_internal_cb_nets(cb[index].pb, cb[index].pb->pb_graph_node, - cb[index].pb->rr_graph, 1); - alloc_internal_cb_nets(cb[index].pb, cb[index].pb->pb_graph_node, - cb[index].pb->rr_graph, 2); - i = 0; - load_internal_cb_nets(cb[index].pb, cb[index].pb->pb_graph_node, - cb[index].pb->rr_graph, &i); - freeTokens(tokens, num_tokens); -#if 0 - /* print local nets */ - for (i = 0; i < cb[index].pb->num_local_nets; i++) { - vpr_printf(TIO_MESSAGE_INFO, "local net %s: ", cb[index].pb->name); - for (j = 0; j <= cb[index].pb->local_nets[i].num_sinks; j++) { - vpr_printf(TIO_MESSAGE_INFO, "%d ", cb[index].pb->local_nets[i].node_block[j]); - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - } -#endif -} - -/** - * XML parser to populate pb info and to update internal nets of the parent CLB - * Parent - XML tag for this pb_type - * pb - physical block to use - * vpack_net_hash - hashtable of original blif net names and indices - * logical_block_hash - hashtable of original blif atom names and indices - */ -static void processPb(INOUTP ezxml_t Parent, INOUTP t_pb* pb, - INOUTP t_rr_node *rr_graph, INOUTP t_pb** rr_node_to_pb_mapping, INOUTP int *num_primitives, - INP struct s_hash **vpack_net_hash, INP struct s_hash **logical_block_hash, INP int cb_index) { - ezxml_t Cur, Prev, lookahead; - const char *Prop; - const char *instance_type; - int i, j, pb_index; - boolean found; - const t_pb_type *pb_type; - t_token *tokens; - int num_tokens; - struct s_hash *temp_hash; - - Cur = FindElement(Parent, "inputs", TRUE); - processPorts(Cur, pb, rr_graph, rr_node_to_pb_mapping, vpack_net_hash); - FreeNode(Cur); - Cur = FindElement(Parent, "outputs", TRUE); - processPorts(Cur, pb, rr_graph, rr_node_to_pb_mapping, vpack_net_hash); - FreeNode(Cur); - Cur = FindElement(Parent, "clocks", TRUE); - processPorts(Cur, pb, rr_graph, rr_node_to_pb_mapping, vpack_net_hash); - FreeNode(Cur); - - pb_type = pb->pb_graph_node->pb_type; - if (pb_type->num_modes == 0) { - /* LUT specific optimizations */ - if (strcmp(pb_type->blif_model, ".names") == 0) { - pb->lut_pin_remap = (int*)my_malloc(pb_type->num_input_pins * sizeof(int)); - for (i = 0; i < pb_type->num_input_pins; i++) { - pb->lut_pin_remap[i] = OPEN; - } - } else { - pb->lut_pin_remap = NULL; - } - temp_hash = get_hash_entry(logical_block_hash, pb->name); - if (temp_hash == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, ".net file and .blif file do not match, encountered unknown primitive %s in .net file.\n", pb->name); - exit(1); - } - pb->logical_block = temp_hash->index; - assert(logical_block[temp_hash->index].pb == NULL); - logical_block[temp_hash->index].pb = pb; - logical_block[temp_hash->index].clb_index = cb_index; - (*num_primitives)++; - } else { - /* process children of child if exists */ - - pb->child_pbs = (t_pb **)my_calloc(pb_type->modes[pb->mode].num_pb_type_children, - sizeof(t_pb*)); - for (i = 0; i < pb_type->modes[pb->mode].num_pb_type_children; i++) { - pb->child_pbs[i] = (t_pb *)my_calloc( - pb_type->modes[pb->mode].pb_type_children[i].num_pb, - sizeof(t_pb)); - for (j = 0; j < pb_type->modes[pb->mode].pb_type_children[i].num_pb; j++) { - pb->child_pbs[i][j].logical_block = OPEN; - } - } - - /* Populate info for each physical block */ - Cur = Parent->child; - while (Cur) { - if (0 == strcmp(Cur->name, "block")) { - CheckElement(Cur, "block"); - - instance_type = FindProperty(Cur, "instance", TRUE); - tokens = GetTokensFromString(instance_type, &num_tokens); - ezxml_set_attr(Cur, "instance", NULL); - if (num_tokens != 4 || tokens[0].type != TOKEN_STRING - || tokens[1].type != TOKEN_OPEN_SQUARE_BRACKET - || tokens[2].type != TOKEN_INT - || tokens[3].type != TOKEN_CLOSE_SQUARE_BRACKET) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Unknown syntax for instance %s in %s. Expected pb_type[instance_number].\n", - Cur->line, instance_type, Cur->name); - exit(1); - } - - found = FALSE; - pb_index = OPEN; - for (i = 0; i < pb_type->modes[pb->mode].num_pb_type_children; - i++) { - if (strcmp( - pb_type->modes[pb->mode].pb_type_children[i].name, - tokens[0].data) == 0) { - if (my_atoi(tokens[2].data) - >= pb_type->modes[pb->mode].pb_type_children[i].num_pb) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Instance number exceeds # of pb available for instance %s in %s.\n", - Cur->line, instance_type, Cur->name); - exit(1); - } - pb_index = my_atoi(tokens[2].data); - if (pb->child_pbs[i][pb_index].pb_graph_node != NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] node is used by two different blocks %s and %s.\n", - Cur->line, instance_type, - pb->child_pbs[i][pb_index].name); - exit(1); - } - pb->child_pbs[i][pb_index].pb_graph_node = - &pb->pb_graph_node->child_pb_graph_nodes[pb->mode][i][pb_index]; - found = TRUE; - break; - } - } - if (!found) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Unknown pb type %s.\n", - Cur->line, instance_type); - exit(1); - } - - Prop = FindProperty(Cur, "name", TRUE); - ezxml_set_attr(Cur, "name", NULL); - if (0 != strcmp(Prop, "open")) { - pb->child_pbs[i][pb_index].name = my_strdup(Prop); - - /* Parse all pbs and CB internal nets*/ - pb->child_pbs[i][pb_index].logical_block = OPEN; - - Prop = FindProperty(Cur, "mode", FALSE); - if (Prop) { - ezxml_set_attr(Cur, "mode", NULL); - } - pb->child_pbs[i][pb_index].mode = 0; - found = FALSE; - for (j = 0; - j - < pb->child_pbs[i][pb_index].pb_graph_node->pb_type->num_modes; - j++) { - if (strcmp(Prop, - pb->child_pbs[i][pb_index].pb_graph_node->pb_type->modes[j].name) - == 0) { - pb->child_pbs[i][pb_index].mode = j; - found = TRUE; - } - } - if (!found - && pb->child_pbs[i][pb_index].pb_graph_node->pb_type->num_modes - != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Unknown mode %s for cb %s #%d.\n", - Cur->line, Prop, pb->child_pbs[i][pb_index].name, pb_index); - exit(1); - } - pb->child_pbs[i][pb_index].parent_pb = pb; - pb->child_pbs[i][pb_index].rr_graph = pb->rr_graph; - - processPb(Cur, &pb->child_pbs[i][pb_index], rr_graph, rr_node_to_pb_mapping, num_primitives, vpack_net_hash, logical_block_hash, cb_index); - } else { - /* physical block has no used primitives but it may have used routing */ - pb->child_pbs[i][pb_index].name = NULL; - pb->child_pbs[i][pb_index].logical_block = OPEN; - lookahead = FindElement(Cur, "outputs", FALSE); - if (lookahead != NULL) { - lookahead = FindFirstElement(lookahead, "port", TRUE); - Prop = FindProperty(Cur, "mode", FALSE); - if (Prop) { - ezxml_set_attr(Cur, "mode", NULL); - } - pb->child_pbs[i][pb_index].mode = 0; - found = FALSE; - for (j = 0; - j - < pb->child_pbs[i][pb_index].pb_graph_node->pb_type->num_modes; - j++) { - if (strcmp(Prop, - pb->child_pbs[i][pb_index].pb_graph_node->pb_type->modes[j].name) - == 0) { - pb->child_pbs[i][pb_index].mode = j; - found = TRUE; - } - } - if (!found - && pb->child_pbs[i][pb_index].pb_graph_node->pb_type->num_modes - != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Unknown mode %s for cb %s #%d.\n", - Cur->line, Prop, pb->child_pbs[i][pb_index].name, pb_index); - exit(1); - } - pb->child_pbs[i][pb_index].parent_pb = pb; - pb->child_pbs[i][pb_index].rr_graph = pb->rr_graph; - processPb(Cur, &pb->child_pbs[i][pb_index], rr_graph, rr_node_to_pb_mapping, num_primitives, vpack_net_hash, logical_block_hash, cb_index); - } - } - Prev = Cur; - Cur = Cur->next; - FreeNode(Prev); - freeTokens(tokens, num_tokens); - } else { - Cur = Cur->next; - } - } - } -} - -/** - * Allocates memory for nets and loads the name of the net so that it can be identified and loaded with - * more complete information later - * ncount - number of nets in the hashtable of nets - * nhash - hashtable of nets - * returns array of nets stored in hashtable - */ -static struct s_net *alloc_and_init_netlist_from_hash(INP int ncount, - INOUTP struct s_hash **nhash) { - struct s_net *nlist; - struct s_hash_iterator hash_iter; - struct s_hash *curr_net; - int i; - - nlist = (struct s_net *)my_calloc(ncount, sizeof(struct s_net)); - - hash_iter = start_hash_table_iterator(); - curr_net = get_next_hash(nhash, &hash_iter); - while (curr_net != NULL) { - assert(nlist[curr_net->index].name == NULL); - nlist[curr_net->index].name = my_strdup(curr_net->name); - nlist[curr_net->index].num_sinks = curr_net->count - 1; - - nlist[curr_net->index].node_block = (int *)my_malloc( - curr_net->count * sizeof(int)); - nlist[curr_net->index].node_block_pin = (int *)my_malloc( - curr_net->count * sizeof(int)); - nlist[curr_net->index].is_global = FALSE; - for (i = 0; i < curr_net->count; i++) { - nlist[curr_net->index].node_block[i] = OPEN; - nlist[curr_net->index].node_block_pin[i] = OPEN; - } - curr_net = get_next_hash(nhash, &hash_iter); - } - return nlist; -} - -/** - * Adds net to hashtable of nets. If the net is "open", then this is a keyword so do not add it. - * If the net already exists, increase the count on that net - */ -static int add_net_to_hash(INOUTP struct s_hash **nhash, INP char *net_name, - INOUTP int *ncount) { - struct s_hash *hash_value; - - if (strcmp(net_name, "open") == 0) { - return OPEN; - } - - hash_value = insert_in_hash_table(nhash, net_name, *ncount); - if (hash_value->count == 1) { - assert(*ncount == hash_value->index); - (*ncount)++; - } - return hash_value->index; -} - -static void processPorts(INOUTP ezxml_t Parent, INOUTP t_pb* pb, - t_rr_node *rr_graph, INOUTP t_pb** rr_node_to_pb_mapping, INP struct s_hash **vpack_net_hash) { - - int i, j, in_port, out_port, clock_port, num_tokens; - ezxml_t Cur, Prev; - const char *Prop; - char **pins; - char *port_name, *interconnect_name; - int rr_node_index; - t_pb_graph_pin *** pin_node; - int *num_ptrs, num_sets; - struct s_hash *temp_hash; - boolean found; - - Cur = Parent->child; - while (Cur) { - if (0 == strcmp(Cur->name, "port")) { - CheckElement(Cur, "port"); - - Prop = FindProperty(Cur, "name", TRUE); - ezxml_set_attr(Cur, "name", NULL); - - in_port = out_port = clock_port = 0; - found = FALSE; - for (i = 0; i < pb->pb_graph_node->pb_type->num_ports; i++) { - if (0 - == strcmp(pb->pb_graph_node->pb_type->ports[i].name, - Prop)) { - found = TRUE; - break; - } - if (pb->pb_graph_node->pb_type->ports[i].is_clock - && pb->pb_graph_node->pb_type->ports[i].type - == IN_PORT) { - clock_port++; - } else if (!pb->pb_graph_node->pb_type->ports[i].is_clock - && pb->pb_graph_node->pb_type->ports[i].type - == IN_PORT) { - in_port++; - } else { - assert( - pb->pb_graph_node->pb_type->ports[i].type == OUT_PORT); - out_port++; - } - } - if (!found) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Unknown port %s for pb %s[%d].\n", - Cur->line, Prop, pb->pb_graph_node->pb_type->name, - pb->pb_graph_node->placement_index); - exit(1); - } - - pins = GetNodeTokens(Cur); - num_tokens = CountTokens(pins); - if (0 == strcmp(Parent->name, "inputs")) { - if (num_tokens != pb->pb_graph_node->num_input_pins[in_port]) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Incorrect # pins %d found for port %s for pb %s[%d].\n", - Cur->line, num_tokens, Prop, - pb->pb_graph_node->pb_type->name, - pb->pb_graph_node->placement_index); - exit(1); - } - } else if (0 == strcmp(Parent->name, "outputs")) { - if (num_tokens - != pb->pb_graph_node->num_output_pins[out_port]) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Incorrect # pins %d found for port %s for pb %s[%d].\n", - Cur->line, num_tokens, Prop, - pb->pb_graph_node->pb_type->name, - pb->pb_graph_node->placement_index); - exit(1); - } - } else { - if (num_tokens - != pb->pb_graph_node->num_clock_pins[clock_port]) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Incorrect # pins %d found for port %s for pb %s[%d].\n", - Cur->line, num_tokens, Prop, - pb->pb_graph_node->pb_type->name, - pb->pb_graph_node->placement_index); - exit(1); - } - } - if (0 == strcmp(Parent->name, "inputs") - || 0 == strcmp(Parent->name, "clocks")) { - if (pb->parent_pb == NULL) { - /* top-level, connections are nets to route */ - for (i = 0; i < num_tokens; i++) { - if (0 == strcmp(Parent->name, "inputs")) - rr_node_index = - pb->pb_graph_node->input_pins[in_port][i].pin_count_in_cluster; - else - rr_node_index = - pb->pb_graph_node->clock_pins[clock_port][i].pin_count_in_cluster; - if (strcmp(pins[i], "open") != 0) { - temp_hash = get_hash_entry(vpack_net_hash, pins[i]); - if (temp_hash == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, ".blif and .net do not match, unknown net %s found in .net file.\n.", pins[i]); - } - rr_graph[rr_node_index].net_num = temp_hash->index; - } - rr_node_to_pb_mapping[rr_node_index] = pb; - } - } else { - for (i = 0; i < num_tokens; i++) { - if (0 == strcmp(pins[i], "open")) { - continue; - } - interconnect_name = strstr(pins[i], "->"); - *interconnect_name = '\0'; - interconnect_name += 2; - port_name = pins[i]; - pin_node = - alloc_and_load_port_pin_ptrs_from_string( - pb->pb_graph_node->pb_type->parent_mode->interconnect[0].line_num, - pb->pb_graph_node->parent_pb_graph_node, - pb->pb_graph_node->parent_pb_graph_node->child_pb_graph_nodes[pb->parent_pb->mode], - port_name, &num_ptrs, &num_sets, TRUE, - TRUE); - assert(num_sets == 1 && num_ptrs[0] == 1); - if (0 == strcmp(Parent->name, "inputs")) - rr_node_index = - pb->pb_graph_node->input_pins[in_port][i].pin_count_in_cluster; - else - rr_node_index = - pb->pb_graph_node->clock_pins[clock_port][i].pin_count_in_cluster; - rr_graph[rr_node_index].prev_node = - pin_node[0][0]->pin_count_in_cluster; - rr_node_to_pb_mapping[rr_node_index] = pb; - found = FALSE; - for (j = 0; j < pin_node[0][0]->num_output_edges; j++) { - if (0 - == strcmp(interconnect_name, - pin_node[0][0]->output_edges[j]->interconnect->name)) { - found = TRUE; - break; - } - } - for (j = 0; j < num_sets; j++) { - free(pin_node[j]); - } - free(pin_node); - free(num_ptrs); - if (!found) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Unknown interconnect %s connecting to pin %s.\n", - Cur->line, interconnect_name, port_name); - exit(1); - } - } - } - } - - if (0 == strcmp(Parent->name, "outputs")) { - if (pb->pb_graph_node->pb_type->num_modes == 0) { - /* primitives are drivers of nets */ - for (i = 0; i < num_tokens; i++) { - rr_node_index = - pb->pb_graph_node->output_pins[out_port][i].pin_count_in_cluster; - if (strcmp(pins[i], "open") != 0) { - temp_hash = get_hash_entry(vpack_net_hash, pins[i]); - if (temp_hash == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, ".blif and .net do not match, unknown net %s found in .net file.\n", pins[i]); - } - rr_graph[rr_node_index].net_num = temp_hash->index; - } - rr_node_to_pb_mapping[rr_node_index] = pb; - } - } else { - for (i = 0; i < num_tokens; i++) { - if (0 == strcmp(pins[i], "open")) { - continue; - } - interconnect_name = strstr(pins[i], "->"); - *interconnect_name = '\0'; - interconnect_name += 2; - port_name = pins[i]; - pin_node = - alloc_and_load_port_pin_ptrs_from_string( - pb->pb_graph_node->pb_type->modes[pb->mode].interconnect->line_num, - pb->pb_graph_node, - pb->pb_graph_node->child_pb_graph_nodes[pb->mode], - port_name, &num_ptrs, &num_sets, TRUE, - TRUE); - assert(num_sets == 1 && num_ptrs[0] == 1); - rr_node_index = - pb->pb_graph_node->output_pins[out_port][i].pin_count_in_cluster; - rr_graph[rr_node_index].prev_node = - pin_node[0][0]->pin_count_in_cluster; - rr_node_to_pb_mapping[rr_node_index] = pb; - found = FALSE; - for (j = 0; j < pin_node[0][0]->num_output_edges; j++) { - if (0 - == strcmp(interconnect_name, - pin_node[0][0]->output_edges[j]->interconnect->name)) { - found = TRUE; - break; - } - } - for (j = 0; j < num_sets; j++) { - free(pin_node[j]); - } - free(pin_node); - free(num_ptrs); - if (!found) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Unknown interconnect %s connecting to pin %s.\n", - Cur->line, interconnect_name, port_name); - exit(1); - } - interconnect_name -= 2; - *interconnect_name = '-'; - } - } - } - - FreeTokens(&pins); - - Prev = Cur; - Cur = Cur->next; - FreeNode(Prev); - } else { - Cur = Cur->next; - } - } -} - -/** - * This function updates the nets list and the connections between that list and the complex block - */ -static void load_external_nets_and_cb(INP int L_num_blocks, - INP struct s_block block_list[], INP int ncount, - INP struct s_net nlist[], OUTP int *ext_ncount, - OUTP struct s_net **ext_nets, INP char **circuit_clocks) { - int i, j, k, ipin; - struct s_hash **ext_nhash; - t_rr_node *rr_graph; - t_pb_graph_pin *pb_graph_pin; - int *count; - int netnum, num_tokens; - - *ext_ncount = 0; - ext_nhash = alloc_hash_table(); - - /* Assumes that complex block pins are ordered inputs, outputs, globals */ - - /* Determine the external nets of complex block */ - for (i = 0; i < L_num_blocks; i++) { - ipin = 0; - if (block_list[i].type->pb_type->num_input_pins - + block_list[i].type->pb_type->num_output_pins - + block_list[i].type->pb_type->num_clock_pins - != block_list[i].type->num_pins - / block_list[i].type->capacity) { - - assert(0); - } - - /* First determine nets external to complex blocks */ - assert( - block_list[i].type->pb_type->num_input_pins + block_list[i].type->pb_type->num_output_pins + block_list[i].type->pb_type->num_clock_pins == block_list[i].type->num_pins / block_list[i].type->capacity); - - rr_graph = block_list[i].pb->rr_graph; - for (j = 0; j < block_list[i].pb->pb_graph_node->num_input_ports; j++) { - for (k = 0; k < block_list[i].pb->pb_graph_node->num_input_pins[j]; - k++) { - pb_graph_pin = - &block_list[i].pb->pb_graph_node->input_pins[j][k]; - assert(pb_graph_pin->pin_count_in_cluster == ipin); - if (rr_graph[pb_graph_pin->pin_count_in_cluster].net_num - != OPEN) { - block_list[i].nets[ipin] = - add_net_to_hash(ext_nhash, - nlist[rr_graph[pb_graph_pin->pin_count_in_cluster].net_num].name, - ext_ncount); - } else { - block_list[i].nets[ipin] = OPEN; - } - ipin++; - } - } - for (j = 0; j < block_list[i].pb->pb_graph_node->num_output_ports; - j++) { - for (k = 0; k < block_list[i].pb->pb_graph_node->num_output_pins[j]; - k++) { - pb_graph_pin = - &block_list[i].pb->pb_graph_node->output_pins[j][k]; - assert(pb_graph_pin->pin_count_in_cluster == ipin); - if (rr_graph[pb_graph_pin->pin_count_in_cluster].net_num - != OPEN) { - block_list[i].nets[ipin] = - add_net_to_hash(ext_nhash, - nlist[rr_graph[pb_graph_pin->pin_count_in_cluster].net_num].name, - ext_ncount); - } else { - block_list[i].nets[ipin] = OPEN; - } - ipin++; - } - } - for (j = 0; j < block_list[i].pb->pb_graph_node->num_clock_ports; j++) { - for (k = 0; k < block_list[i].pb->pb_graph_node->num_clock_pins[j]; - k++) { - pb_graph_pin = - &block_list[i].pb->pb_graph_node->clock_pins[j][k]; - assert(pb_graph_pin->pin_count_in_cluster == ipin); - if (rr_graph[pb_graph_pin->pin_count_in_cluster].net_num - != OPEN) { - block_list[i].nets[ipin] = - add_net_to_hash(ext_nhash, - nlist[rr_graph[pb_graph_pin->pin_count_in_cluster].net_num].name, - ext_ncount); - } else { - block_list[i].nets[ipin] = OPEN; - } - ipin++; - } - } - for (j = ipin; j < block_list[i].type->num_pins; j++) { - block_list[i].nets[ipin] = OPEN; - } - } - - /* alloc and partially load the list of external nets */ - (*ext_nets) = alloc_and_init_netlist_from_hash(*ext_ncount, ext_nhash); - /* Load global nets */ - num_tokens = CountTokens(circuit_clocks); - - count = (int *)my_calloc(*ext_ncount, sizeof(int)); - - /* complete load of external nets so that each net points back to the blocks */ - for (i = 0; i < L_num_blocks; i++) { - ipin = 0; - rr_graph = block_list[i].pb->rr_graph; - for (j = 0; j < block_list[i].type->num_pins; j++) { - netnum = block_list[i].nets[j]; - if (netnum != OPEN) { - if (RECEIVER - == block_list[i].type->class_inf[block_list[i].type->pin_class[j]].type) { - count[netnum]++; - if(count[netnum] > (*ext_nets)[netnum].num_sinks) { - vpr_printf(TIO_MESSAGE_ERROR, "net %s #%d inconsistency, expected %d terminals but encountered %d terminals, it is likely net terminal is disconnected in netlist file.\n", - (*ext_nets)[netnum].name, netnum, count[netnum], (*ext_nets)[netnum].num_sinks); - exit(1); - } - - (*ext_nets)[netnum].node_block[count[netnum]] = i; - (*ext_nets)[netnum].node_block_pin[count[netnum]] = j; - - (*ext_nets)[netnum].is_global = block_list[i].type->is_global_pin[j]; /* Error check performed later to ensure no mixing of global and non-global signals */ - } else { - assert( - DRIVER == block_list[i].type->class_inf[block_list[i].type->pin_class[j]].type); - assert((*ext_nets)[netnum].node_block[0] == OPEN); - (*ext_nets)[netnum].node_block[0] = i; - (*ext_nets)[netnum].node_block_pin[0] = j; - } - } - } - } - /* Error check global and non global signals */ - for (i = 0; i < *ext_ncount; i++) { - for (j = 1; j <= (*ext_nets)[i].num_sinks; j++) { - if (block_list[(*ext_nets)[i].node_block[j]].type->is_global_pin[(*ext_nets)[i].node_block_pin[j]] != (*ext_nets)[i].is_global) { - vpr_printf(TIO_MESSAGE_ERROR, "Netlist attempts to connect net %s to both global and non-global pins.\n", - (*ext_nets)[i].name); - exit(1); - } - } - for (j = 0; j < num_tokens; j++) { - if (strcmp(circuit_clocks[j], (*ext_nets)[i].name) == 0) { - assert((*ext_nets)[i].is_global == TRUE); /* above code should have caught this case, if not, then bug in code */ - } - } - } - free(count); - free_hash_table(ext_nhash); -} - -/* Recursive function that fills rr_graph of cb with net numbers starting at the given rr_node */ -static int count_sinks_internal_cb_rr_graph_net_nums( - INP t_rr_node * cur_rr_node, INP t_rr_node * rr_graph) { - int i; - int count = 0; - - for (i = 0; i < cur_rr_node->num_edges; i++) { - if (&rr_graph[rr_graph[cur_rr_node->edges[i]].prev_node] - == cur_rr_node) { - if (!(rr_graph[cur_rr_node->edges[i]].net_num == OPEN || rr_graph[cur_rr_node->edges[i]].net_num == cur_rr_node->net_num)) { - assert( - rr_graph[cur_rr_node->edges[i]].net_num == OPEN || rr_graph[cur_rr_node->edges[i]].net_num == cur_rr_node->net_num); - } - count += count_sinks_internal_cb_rr_graph_net_nums( - &rr_graph[cur_rr_node->edges[i]], rr_graph); - } - } - if (count == 0) { - return 1; /* terminal node */ - } else { - return count; - } -} - -/* Recursive function that fills rr_graph of cb with net numbers starting at the given rr_node */ -static void load_internal_cb_rr_graph_net_nums(INP t_rr_node * cur_rr_node, - INP t_rr_node * rr_graph, INOUTP struct s_net * nets, - INOUTP int * curr_net, INOUTP int * curr_sink) { - int i; - - boolean terminal; - terminal = TRUE; - - for (i = 0; i < cur_rr_node->num_edges; i++) { - if (&rr_graph[rr_graph[cur_rr_node->edges[i]].prev_node] - == cur_rr_node) { - /* TODO: If multiple edges to same node (should not happen in reasonable design) this always - selects the last edge, need to be smart about it in future (ie. select fastest edge */ - assert( - rr_graph[cur_rr_node->edges[i]].net_num == OPEN || rr_graph[cur_rr_node->edges[i]].net_num == cur_rr_node->net_num); - rr_graph[cur_rr_node->edges[i]].net_num = cur_rr_node->net_num; - rr_graph[cur_rr_node->edges[i]].prev_edge = i; - load_internal_cb_rr_graph_net_nums(&rr_graph[cur_rr_node->edges[i]], - rr_graph, nets, curr_net, curr_sink); - terminal = FALSE; - } - } - if (terminal == TRUE) { - /* Since the routing node index is known, assign that instead of the more obscure node block */ - nets[*curr_net].node_block[*curr_sink] = - cur_rr_node->pb_graph_pin->pin_count_in_cluster; - nets[*curr_net].node_block_pin[*curr_sink] = OPEN; - nets[*curr_net].node_block_port[*curr_sink] = OPEN; - (*curr_sink)++; - } -} - -/* Load internal cb nets and fill rr_graph of cb with net numbers */ -static void load_internal_cb_nets(INOUTP t_pb *top_level, - INP t_pb_graph_node *pb_graph_node, INOUTP t_rr_node *rr_graph, - INOUTP int * curr_net) { - int i, j, k; - const t_pb_type *pb_type; - int temp, size; - struct s_net * nets; - - pb_type = pb_graph_node->pb_type; - - nets = top_level->local_nets; - - temp = 0; - - if (pb_graph_node->parent_pb_graph_node == NULL) { /* determine nets driven from inputs at top level */ - *curr_net = 0; - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - if (rr_graph[pb_graph_node->input_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - load_internal_cb_rr_graph_net_nums( - &rr_graph[pb_graph_node->input_pins[i][j].pin_count_in_cluster], - rr_graph, nets, curr_net, &temp); - assert(temp == nets[*curr_net].num_sinks); - temp = 0; - size = - strlen(pb_graph_node->pb_type->name) - + pb_graph_node->placement_index / 10 - + i / 10 + j / 10 - + pb_graph_node->input_pins[i][j].pin_count_in_cluster - / 10 + 26; - nets[*curr_net].name = (char *)my_calloc(size, sizeof(char)); - sprintf(nets[*curr_net].name, - "%s[%d].input[%d][%d].pin[%d]", - pb_graph_node->pb_type->name, - pb_graph_node->placement_index, i, j, - pb_graph_node->input_pins[i][j].pin_count_in_cluster); - (*curr_net)++; - } - } - } - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - if (rr_graph[pb_graph_node->clock_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - load_internal_cb_rr_graph_net_nums( - &rr_graph[pb_graph_node->clock_pins[i][j].pin_count_in_cluster], - rr_graph, nets, curr_net, &temp); - assert(temp == nets[*curr_net].num_sinks); - temp = 0; - nets[*curr_net].is_global = TRUE; - size = - strlen(pb_graph_node->pb_type->name) - + pb_graph_node->placement_index / 10 - + i / 10 + j / 10 - + pb_graph_node->clock_pins[i][j].pin_count_in_cluster - / 10 + 26; - nets[*curr_net].name = (char *)my_calloc(size, sizeof(char)); - sprintf(nets[*curr_net].name, - "%s[%d].clock[%d][%d].pin[%d]", - pb_graph_node->pb_type->name, - pb_graph_node->placement_index, i, j, - pb_graph_node->clock_pins[i][j].pin_count_in_cluster); - (*curr_net)++; - } - } - } - } - - if (pb_type->blif_model != NULL) { - /* This is a terminal node so it might drive nets, find and map the rr_graph path for those nets */ - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - if (rr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - load_internal_cb_rr_graph_net_nums( - &rr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster], - rr_graph, nets, curr_net, &temp); - assert(temp == nets[*curr_net].num_sinks); - temp = 0; - size = - strlen(pb_graph_node->pb_type->name) - + pb_graph_node->placement_index / 10 - + i / 10 + j / 10 - + pb_graph_node->output_pins[i][j].pin_count_in_cluster - / 10 + 26; - nets[*curr_net].name = (char *)my_calloc(size, sizeof(char)); - sprintf(nets[*curr_net].name, - "%s[%d].output[%d][%d].pin[%d]", - pb_graph_node->pb_type->name, - pb_graph_node->placement_index, i, j, - pb_graph_node->output_pins[i][j].pin_count_in_cluster); - (*curr_net)++; - } - } - } - } else { - /* Recurse down to primitives */ - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - load_internal_cb_nets(top_level, - &pb_graph_node->child_pb_graph_nodes[i][j][k], - rr_graph, curr_net); - } - } - } - } - - if (pb_graph_node->parent_pb_graph_node == NULL) { /* at top level */ - assert(*curr_net == top_level->num_local_nets); - } -} - -/* allocate space to store nets internal to cb - two pass algorithm, pass 1 count and allocate # nets, pass 2 determine # sinks - */ -static void alloc_internal_cb_nets(INOUTP t_pb *top_level, - INP t_pb_graph_node *pb_graph_node, INOUTP t_rr_node *rr_graph, - INP int pass) { - int i, j, k; - const t_pb_type *pb_type; - int num_sinks; - - pb_type = pb_graph_node->pb_type; - - if (pb_graph_node->parent_pb_graph_node == NULL) { /* determine nets driven from inputs at top level */ - top_level->num_local_nets = 0; - if (pass == 1) - top_level->local_nets = NULL; - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - if (rr_graph[pb_graph_node->input_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - if (pass == 2) { - num_sinks = - count_sinks_internal_cb_rr_graph_net_nums( - &rr_graph[pb_graph_node->input_pins[i][j].pin_count_in_cluster], - rr_graph); - top_level->local_nets[top_level->num_local_nets].num_sinks = - num_sinks; - top_level->local_nets[top_level->num_local_nets].node_block = (int *) - my_calloc(num_sinks, sizeof(int)); - top_level->local_nets[top_level->num_local_nets].node_block_port = (int *) - my_calloc(num_sinks, sizeof(int)); - top_level->local_nets[top_level->num_local_nets].node_block_pin = (int *) - my_calloc(num_sinks, sizeof(int)); - } - top_level->num_local_nets++; - } - } - } - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - if (rr_graph[pb_graph_node->clock_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - if (pass == 2) { - num_sinks = - count_sinks_internal_cb_rr_graph_net_nums( - &rr_graph[pb_graph_node->clock_pins[i][j].pin_count_in_cluster], - rr_graph); - top_level->local_nets[top_level->num_local_nets].num_sinks = - num_sinks; - top_level->local_nets[top_level->num_local_nets].node_block = (int *) - my_calloc(num_sinks, sizeof(int)); - top_level->local_nets[top_level->num_local_nets].node_block_port = (int *) - my_calloc(num_sinks, sizeof(int)); - top_level->local_nets[top_level->num_local_nets].node_block_pin = (int *) - my_calloc(num_sinks, sizeof(int)); - } - top_level->num_local_nets++; - } - } - } - } - - if (pb_type->blif_model != NULL) { - /* This is a terminal node so it might drive nets, find and map the rr_graph path for those nets */ - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - if (rr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - if (pass == 2) { - num_sinks = - count_sinks_internal_cb_rr_graph_net_nums( - &rr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster], - rr_graph); - top_level->local_nets[top_level->num_local_nets].num_sinks = - num_sinks; - top_level->local_nets[top_level->num_local_nets].node_block = (int *) - my_calloc(num_sinks, sizeof(int)); - top_level->local_nets[top_level->num_local_nets].node_block_port = (int *) - my_calloc(num_sinks, sizeof(int)); - top_level->local_nets[top_level->num_local_nets].node_block_pin = (int *) - my_calloc(num_sinks, sizeof(int)); - } - top_level->num_local_nets++; - } - } - } - } else { - /* Recurse down to primitives */ - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - alloc_internal_cb_nets(top_level, - &pb_graph_node->child_pb_graph_nodes[i][j][k], - rr_graph, pass); - } - } - } - } - - if (pb_graph_node->parent_pb_graph_node == NULL) { /* at top level */ - if (pass == 1) { - top_level->local_nets = (struct s_net *)my_calloc(top_level->num_local_nets, - sizeof(struct s_net)); - } - } -} - -static void mark_constant_generators(INP int L_num_blocks, - INP struct s_block block_list[], INP int ncount, - INOUTP struct s_net nlist[]) { - int i; - for (i = 0; i < L_num_blocks; i++) { - mark_constant_generators_rec(block_list[i].pb, - block_list[i].pb->rr_graph, nlist); - } -} - -static void mark_constant_generators_rec(INP t_pb *pb, INP t_rr_node *rr_graph, - INOUTP struct s_net nlist[]) { - int i, j; - t_pb_type *pb_type; - boolean const_gen; - if (pb->pb_graph_node->pb_type->blif_model == NULL) { - for (i = 0; - i - < pb->pb_graph_node->pb_type->modes[pb->mode].num_pb_type_children; - i++) { - pb_type = - &(pb->pb_graph_node->pb_type->modes[pb->mode].pb_type_children[i]); - for (j = 0; j < pb_type->num_pb; j++) { - if (pb->child_pbs[i][j].name != NULL) { - mark_constant_generators_rec(&(pb->child_pbs[i][j]), - rr_graph, nlist); - } - } - } - } else if (strcmp(pb->pb_graph_node->pb_type->name, "inpad") != 0) { - const_gen = TRUE; - for (i = 0; i < pb->pb_graph_node->num_input_ports && const_gen == TRUE; - i++) { - for (j = 0; - j < pb->pb_graph_node->num_input_pins[i] - && const_gen == TRUE; j++) { - if (rr_graph[pb->pb_graph_node->input_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - const_gen = FALSE; - } - } - } - for (i = 0; i < pb->pb_graph_node->num_clock_ports && const_gen == TRUE; - i++) { - for (j = 0; - j < pb->pb_graph_node->num_clock_pins[i] - && const_gen == TRUE; j++) { - if (rr_graph[pb->pb_graph_node->clock_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - const_gen = FALSE; - } - } - } - if (const_gen == TRUE) { - vpr_printf(TIO_MESSAGE_INFO, "%s is a constant generator.\n", pb->name); - for (i = 0; i < pb->pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb->pb_graph_node->num_output_pins[i]; j++) { - if (rr_graph[pb->pb_graph_node->output_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - nlist[rr_graph[pb->pb_graph_node->output_pins[i][j].pin_count_in_cluster].net_num].is_const_gen = - TRUE; - } - } - } - } - } -} - - -/* Free logical blocks of netlist */ -void free_logical_blocks(void) { - int iblk, i; - t_model_ports *port; - struct s_linked_vptr *tvptr, *next; - - for (iblk = 0; iblk < num_logical_blocks; iblk++) { - port = logical_block[iblk].model->inputs; - i = 0; - while (port) { - if (!port->is_clock) { - free(logical_block[iblk].input_nets[i]); - if (logical_block[iblk].input_net_tnodes) { - if (logical_block[iblk].input_net_tnodes[i]) - free(logical_block[iblk].input_net_tnodes[i]); - } - i++; - } - port = port->next; - } - if (logical_block[iblk].input_net_tnodes) - free(logical_block[iblk].input_net_tnodes); - - tvptr = logical_block[iblk].packed_molecules; - while (tvptr != NULL) { - next = tvptr->next; - free(tvptr); - tvptr = next; - } - - free(logical_block[iblk].input_nets); - port = logical_block[iblk].model->outputs; - i = 0; - while (port) { - free(logical_block[iblk].output_nets[i]); - if (logical_block[iblk].output_net_tnodes) { - if (logical_block[iblk].output_net_tnodes[i]) - free(logical_block[iblk].output_net_tnodes[i]); - } - i++; - port = port->next; - } - if (logical_block[iblk].output_net_tnodes) { - free(logical_block[iblk].output_net_tnodes); - } - free(logical_block[iblk].output_nets); - free(logical_block[iblk].name); - tvptr = logical_block[iblk].truth_table; - while (tvptr != NULL) { - if (tvptr->data_vptr) - free(tvptr->data_vptr); - next = tvptr->next; - free(tvptr); - tvptr = next; - } - } - free(logical_block); - logical_block = NULL; -} - -/* Free logical blocks of netlist */ -void free_logical_nets(void) { - int inet; - - for (inet = 0; inet < num_logical_nets; inet++) { - free(vpack_net[inet].name); - free(vpack_net[inet].node_block); - free(vpack_net[inet].node_block_port); - free(vpack_net[inet].node_block_pin); - } - free(vpack_net); - vpack_net = NULL; -} - - diff --git a/vpr7_x2p/vpr/SRC/base/read_netlist.h b/vpr7_x2p/vpr/SRC/base/read_netlist.h deleted file mode 100644 index 1fef27683..000000000 --- a/vpr7_x2p/vpr/SRC/base/read_netlist.h +++ /dev/null @@ -1,22 +0,0 @@ -/** - * Author: Jason Luu - * Date: May 2009 - * - * Read a circuit netlist in XML format and populate the netlist data structures for VPR - */ - -#ifndef READ_NETLIST_H -#define READ_NETLIST_H - -void read_netlist(INP const char *net_file, - INP const t_arch *arch, - OUTP int *L_num_blocks, - OUTP struct s_block *block_list[], - OUTP int *L_num_nets, - OUTP struct s_net *net_list[]); - -void free_logical_blocks(void); -void free_logical_nets(void); - -#endif - diff --git a/vpr7_x2p/vpr/SRC/base/read_place.c b/vpr7_x2p/vpr/SRC/base/read_place.c deleted file mode 100644 index d8889c5b5..000000000 --- a/vpr7_x2p/vpr/SRC/base/read_place.c +++ /dev/null @@ -1,289 +0,0 @@ -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "hash.h" -#include "read_place.h" -#include "read_xml_arch_file.h" -#include "ReadLine.h" - -/* extern, should be a header */ -char **ReadLineTokens(INOUTP FILE * InFile, INOUTP int *LineNum); - -void read_place(INP const char *place_file, INP const char *arch_file, - INP const char *net_file, INP int L_nx, INP int L_ny, - INP int L_num_blocks, INOUTP struct s_block block_list[]) { - - FILE *infile; - char **tokens; - int line; - int i; - int error; - struct s_block *cur_blk; - - infile = fopen(place_file, "r"); - - /* Check filenames in first line match */ - tokens = ReadLineTokens(infile, &line); - error = 0; - if (NULL == tokens) { - error = 1; - } - for (i = 0; i < 6; ++i) { - if (!error) { - if (NULL == tokens[i]) { - error = 1; - } - } - } - if (!error) { - if ((0 != strcmp(tokens[0], "Netlist")) - || (0 != strcmp(tokens[1], "file:")) - || (0 != strcmp(tokens[3], "Architecture")) - || (0 != strcmp(tokens[4], "file:"))) { - error = 1; - }; - } - if (error) { - vpr_printf(TIO_MESSAGE_ERROR, "'%s' - Bad filename specification line in placement file.\n", place_file); - exit(1); - } - if (0 != strcmp(tokens[2], arch_file)) { - vpr_printf(TIO_MESSAGE_ERROR, "'%s' - Architecture file that generated placement (%s) does not match current architecture file (%s).\n", - place_file, tokens[2], arch_file); - exit(1); - } - if (0 != strcmp(tokens[5], net_file)) { - vpr_printf(TIO_MESSAGE_ERROR, "'%s' - Netlist file that generated placement (%s) does not match current netlist file (%s).\n", - place_file, tokens[5], net_file); - exit(1); - } - free(*tokens); - free(tokens); - - /* Check array size in second line matches */ - tokens = ReadLineTokens(infile, &line); - error = 0; - if (NULL == tokens) { - error = 1; - } - for (i = 0; i < 7; ++i) { - if (!error) { - if (NULL == tokens[i]) { - error = 1; - } - } - } - if (!error) { - if ((0 != strcmp(tokens[0], "Array")) - || (0 != strcmp(tokens[1], "size:")) - || (0 != strcmp(tokens[3], "x")) - || (0 != strcmp(tokens[5], "logic")) - || (0 != strcmp(tokens[6], "blocks"))) { - error = 1; - }; - } - if (error) { - vpr_printf(TIO_MESSAGE_ERROR, "'%s' - Bad FPGA size specification line in placement file.\n", - place_file); - exit(1); - } - if ((my_atoi(tokens[2]) != L_nx) || (my_atoi(tokens[4]) != L_ny)) { - vpr_printf(TIO_MESSAGE_ERROR, "'%s' - Current FPGA size (%d x %d) is different from size when placement generated (%d x %d).\n", - place_file, L_nx, L_ny, my_atoi(tokens[2]), my_atoi(tokens[4])); - exit(1); - } - free(*tokens); - free(tokens); - - tokens = ReadLineTokens(infile, &line); - while (tokens) { - /* Linear search to match pad to netlist */ - cur_blk = NULL; - for (i = 0; i < L_num_blocks; ++i) { - if (0 == strcmp(block_list[i].name, tokens[0])) { - cur_blk = (block_list + i); - break; - } - } - - /* Error if invalid block */ - if (NULL == cur_blk) { - vpr_printf(TIO_MESSAGE_ERROR, "'%s':%d - Block in placement file does not exist in netlist.\n", - place_file, line); - exit(1); - } - - /* Set pad coords */ - cur_blk->x = my_atoi(tokens[1]); - cur_blk->y = my_atoi(tokens[2]); - cur_blk->z = my_atoi(tokens[3]); - - /* Get next line */ - assert(*tokens); - free(*tokens); - free(tokens); - tokens = ReadLineTokens(infile, &line); - } - - fclose(infile); -} - -void read_user_pad_loc(char *pad_loc_file) { - - /* Reads in the locations of the IO pads from a file. */ - - struct s_hash **hash_table, *h_ptr; - int iblk, i, j, xtmp, ytmp, bnum, k; - FILE *fp; - char buf[BUFSIZE], bname[BUFSIZE], *ptr; - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Reading locations of IO pads from '%s'.\n", pad_loc_file); - file_line_number = 0; - fp = fopen(pad_loc_file, "r"); - - hash_table = alloc_hash_table(); - for (iblk = 0; iblk < num_blocks; iblk++) { - if (block[iblk].type == IO_TYPE) { - h_ptr = insert_in_hash_table(hash_table, block[iblk].name, iblk); - block[iblk].x = OPEN; /* Mark as not seen yet. */ - } - } - - for (i = 0; i <= nx + 1; i++) { - for (j = 0; j <= ny + 1; j++) { - if (grid[i][j].type == IO_TYPE) { - for (k = 0; k < IO_TYPE->capacity; k++) - grid[i][j].blocks[k] = OPEN; /* Flag for err. check */ - } - } - } - - ptr = my_fgets(buf, BUFSIZE, fp); - - while (ptr != NULL) { - ptr = my_strtok(buf, TOKENS, fp, buf); - if (ptr == NULL) { - ptr = my_fgets(buf, BUFSIZE, fp); - continue; /* Skip blank or comment lines. */ - } - - strcpy(bname, ptr); - - ptr = my_strtok(NULL, TOKENS, fp, buf); - if (ptr == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Incomplete.\n", file_line_number); - exit(1); - } - sscanf(ptr, "%d", &xtmp); - - ptr = my_strtok(NULL, TOKENS, fp, buf); - if (ptr == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Incomplete.\n", file_line_number); - exit(1); - } - sscanf(ptr, "%d", &ytmp); - - ptr = my_strtok(NULL, TOKENS, fp, buf); - if (ptr == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Incomplete.\n", file_line_number); - exit(1); - } - sscanf(ptr, "%d", &k); - - ptr = my_strtok(NULL, TOKENS, fp, buf); - if (ptr != NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Extra characters at end of line.\n", - file_line_number); - exit(1); - } - - h_ptr = get_hash_entry(hash_table, bname); - if (h_ptr == NULL) { - vpr_printf(TIO_MESSAGE_WARNING, "[Line %d] Block %s invalid, no such IO pad.\n", - file_line_number, bname); - ptr = my_fgets(buf, BUFSIZE, fp); - continue; - } - bnum = h_ptr->index; - i = xtmp; - j = ytmp; - - if (block[bnum].x != OPEN) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Block %s is listed twice in pad file.\n", - file_line_number, bname); - exit(1); - } - - if (i < 0 || i > nx + 1 || j < 0 || j > ny + 1) { - vpr_printf(TIO_MESSAGE_ERROR, "Block #%d (%s) location, (%d,%d) is out of range.\n", - bnum, bname, i, j); - exit(1); - } - - block[bnum].x = i; /* Will be reloaded by initial_placement anyway. */ - block[bnum].y = j; /* I need to set .x only as a done flag. */ - block[bnum].isFixed = TRUE; - - if (grid[i][j].type != IO_TYPE) { - vpr_printf(TIO_MESSAGE_ERROR, "Attempt to place IO block %s at illegal location (%d, %d).\n", - bname, i, j); - exit(1); - } - - if (k >= IO_TYPE->capacity || k < 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[Line %d] Block %s subblock number (%d) is out of range.\n", - file_line_number, bname, k); - exit(1); - } - grid[i][j].blocks[k] = bnum; - grid[i][j].usage++; - - ptr = my_fgets(buf, BUFSIZE, fp); - } - - for (iblk = 0; iblk < num_blocks; iblk++) { - if (block[iblk].type == IO_TYPE && block[iblk].x == OPEN) { - vpr_printf(TIO_MESSAGE_ERROR, "IO block %s location was not specified in the pad file.\n", - block[iblk].name); - exit(1); - } - } - - fclose(fp); - free_hash_table(hash_table); - vpr_printf(TIO_MESSAGE_INFO, "Successfully read %s.\n", pad_loc_file); - vpr_printf(TIO_MESSAGE_INFO, "\n"); -} - -void print_place(char *place_file, char *net_file, char *arch_file) { - - /* Prints out the placement of the circuit. The architecture and * - * netlist files used to generate this placement are recorded in the * - * file to avoid loading a placement with the wrong support files * - * later. */ - - FILE *fp; - int i; - - fp = fopen(place_file, "w"); - - fprintf(fp, "Netlist file: %s Architecture file: %s\n", net_file, - arch_file); - fprintf(fp, "Array size: %d x %d logic blocks\n\n", nx, ny); - fprintf(fp, "#block name\tx\ty\tsubblk\tblock number\n"); - fprintf(fp, "#----------\t--\t--\t------\t------------\n"); - - for (i = 0; i < num_blocks; i++) { - fprintf(fp, "%s\t", block[i].name); - if (strlen(block[i].name) < 8) - fprintf(fp, "\t"); - - fprintf(fp, "%d\t%d\t%d", block[i].x, block[i].y, block[i].z); - fprintf(fp, "\t#%d\n", i); - } - fclose(fp); -} diff --git a/vpr7_x2p/vpr/SRC/base/read_place.h b/vpr7_x2p/vpr/SRC/base/read_place.h deleted file mode 100644 index cb991d4e8..000000000 --- a/vpr7_x2p/vpr/SRC/base/read_place.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef READ_PLACE_H -#define READ_PLACE_H - -void read_place(INP const char *place_file, - INP const char *arch_file, - INP const char *net_file, - INP int L_nx, - INP int L_ny, - INP int L_num_blocks, - INOUTP struct s_block block_list[]); - -void print_place(INP char *place_file, - INP char *net_file, - INP char *arch_file); - -void read_user_pad_loc(INP char *pad_loc_file); - -#endif - diff --git a/vpr7_x2p/vpr/SRC/base/read_settings.c b/vpr7_x2p/vpr/SRC/base/read_settings.c deleted file mode 100644 index 67a49e3b0..000000000 --- a/vpr7_x2p/vpr/SRC/base/read_settings.c +++ /dev/null @@ -1,78 +0,0 @@ -#include -#include -#include "read_xml_util.h" -#include "read_settings.h" - -static int process_settings(ezxml_t Cur, char ** outv) -{ - int count = 0; - - if (!Cur) - return(0); - - while (Cur->attr[count]) - { - if (outv) - { - if (! (count % 2)) - { - outv[count] = (char *)my_malloc(strlen(Cur->attr[count]) + 3); - strcpy(&outv[count][2], Cur->attr[count]); - outv[count][0] = outv[count][1] = '-'; - } - else - outv[count] = Cur->attr[count]; - } - count++; - } - - Cur = Cur->child; - - while (Cur) - { - if (outv) - { - outv[count] = (char *)my_malloc(strlen(Cur->name) + 3); - strcpy(&outv[count][2], Cur->name); - outv[count][0] = outv[count][1] = '-'; - } - count++; - - if (strlen(Cur->txt)) - { - if (outv) outv[count] = Cur->txt; - count++; - } - - Cur = Cur->ordered; - } - - return count; -} - -int read_settings_file(char * file_name, char *** outv) -{ - ezxml_t Cur; - int count; - - Cur = ezxml_parse_file(file_name); - assert(*outv == NULL); - assert(! strcmp("settings",Cur->name)); - Cur = FindElement(Cur, "arguments", FALSE); - - count = process_settings(Cur, *outv); - - /* prepend the settings file name */ - count++; - - *outv = (char **)my_malloc(count * sizeof(char *)); - - (*outv)[0] = my_strdup(file_name); - - if (count) - { - process_settings(Cur, &((*outv)[1])); - } - - return(count); -} diff --git a/vpr7_x2p/vpr/SRC/base/read_settings.h b/vpr7_x2p/vpr/SRC/base/read_settings.h deleted file mode 100644 index 0c7203989..000000000 --- a/vpr7_x2p/vpr/SRC/base/read_settings.h +++ /dev/null @@ -1,5 +0,0 @@ -#ifndef READ_SETTINGS_H -#define READ_SETTINGS_H -int read_settings_file(char * file_name, char *** outv); - -#endif diff --git a/vpr7_x2p/vpr/SRC/base/stats.c b/vpr7_x2p/vpr/SRC/base/stats.c deleted file mode 100644 index f7af4fdcb..000000000 --- a/vpr7_x2p/vpr/SRC/base/stats.c +++ /dev/null @@ -1,533 +0,0 @@ - -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_area.h" -#include "segment_stats.h" -#include "stats.h" -#include "net_delay.h" -#include "path_delay.h" -#include "read_xml_arch_file.h" -#include "ReadOptions.h" -/* mrFPGA: Xifan TANG*/ -#include "mrfpga_globals.h" -#include "buffer_insertion.h" -#include "cal_capacitance.h" -/* end */ -/* Xifan TANG: pb_pin_eq_auto_detect */ -void print_net_opin_occupancy(); -/* end */ - -/********************** Subroutines local to this module *********************/ - -static void load_channel_occupancies(int **chanx_occ, int **chany_occ); - -static void get_length_and_bends_stats(void); - -static void get_channel_occupancy_stats(void); - -/************************* Subroutine definitions ****************************/ - -void routing_stats(boolean full_stats, enum e_route_type route_type, - int num_switch, t_segment_inf * segment_inf, int num_segment, - float R_minW_nmos, float R_minW_pmos, - enum e_directionality directionality, boolean timing_analysis_enabled, - float **net_delay, t_slack * slacks, float sram_area) { - - /* Prints out various statistics about the current routing. Both a routing * - * and an rr_graph must exist when you call this routine. */ - - float area, used_area; - int i, j; - - /* mrFPGA: Xifan TANG */ - static float buffer_size; - /* end */ - - get_length_and_bends_stats(); - get_channel_occupancy_stats(); - - vpr_printf(TIO_MESSAGE_INFO, "Logic area (in minimum width transistor areas, excludes I/Os and empty grid tiles)...\n"); - - area = 0; - for (i = 1; i <= nx; i++) { - for (j = 1; j <= ny; j++) { - if (grid[i][j].offset == 0) { - if (grid[i][j].type->area == UNDEFINED) { - area += grid_logic_tile_area * grid[i][j].type->height; - } else { - area += grid[i][j].type->area; - } - } - } - } - /* Todo: need to add pitch of routing to blocks with height > 3 */ - vpr_printf(TIO_MESSAGE_INFO, "\tTotal logic block area (Warning, need to add pitch of routing to blocks with height > 3): %g\n", area); - - used_area = 0; - for (i = 0; i < num_blocks; i++) { - if (block[i].type != IO_TYPE) { - if (block[i].type->area == UNDEFINED) { - used_area += grid_logic_tile_area * block[i].type->height; - } else { - used_area += block[i].type->area; - } - } - } - vpr_printf(TIO_MESSAGE_INFO, "\tTotal used logic block area: %g\n", used_area); - - if (route_type == DETAILED) { - /* mrFPGA: Xifan TANG */ - if (is_mrFPGA) { - if (is_wire_buffer) { - buffer_size = trans_per_buf(wire_buffer_inf.R - memristor_inf.R, R_minW_nmos, R_minW_pmos); - count_routing_memristor_buffer(print_stat_memristor_buffer("mrFPGA_buffer.echo", buffer_size), - buffer_size); - } else { - vpr_printf(TIO_MESSAGE_INFO, "Tile area: %#g\n", grid_logic_tile_area); - } - } else { - if (!is_mrFPGA && is_stack) { - for (i = 0; i < num_normal_switch; i++) { - switch_inf[i].R -= Rseg_global; - } - } - if (rram_pass_tran_value > 0.01) { - for (i = 0; i < num_normal_switch; i++) { - switch_inf[i].R = (switch_inf[i].R - rram_pass_tran_value)*2; - } - } - /* END */ - count_routing_transistors(directionality, num_switch, segment_inf, - R_minW_nmos, R_minW_pmos, sram_area); - /* mrFPGA : Xifan TANG */ - if (rram_pass_tran_value > 0.01) { - for (i = 0; i < num_normal_switch; i++) { - switch_inf[i].R = (switch_inf[i].R / 2. - rram_pass_tran_value); - } - } - if (!is_mrFPGA && is_stack) { - for (i = 0; i < num_normal_switch; i++) { - switch_inf[i].R += Rseg_global; - } - } - } - /* END */ - get_segment_usage_stats(num_segment, segment_inf); - - if (timing_analysis_enabled) { - load_net_delay_from_routing(net_delay, clb_net, num_nets); - - /* mrFPGA: Xifan TANG */ - cal_capacitance_from_routing(); - /* END */ - load_timing_graph_net_delays(net_delay); - -#ifdef HACK_LUT_PIN_SWAPPING - do_timing_analysis(slacks, FALSE, TRUE, TRUE); -#else - do_timing_analysis(slacks, FALSE, FALSE, TRUE); -#endif - if (getEchoEnabled()) { - if(isEchoFileEnabled(E_ECHO_TIMING_GRAPH)) - print_timing_graph(getEchoFileName(E_ECHO_TIMING_GRAPH)); - if (isEchoFileEnabled(E_ECHO_NET_DELAY)) - print_net_delay(net_delay, getEchoFileName(E_ECHO_NET_DELAY)); - if(isEchoFileEnabled(E_ECHO_LUT_REMAPPING)) - print_lut_remapping(getEchoFileName(E_ECHO_LUT_REMAPPING)); - } - print_slack(slacks->slack, TRUE, getOutputFileName(E_SLACK_FILE)); - print_criticality(slacks, TRUE, getOutputFileName(E_CRITICALITY_FILE)); - print_critical_path(getOutputFileName(E_CRIT_PATH_FILE)); - print_timing_stats(); - } - } - - if (full_stats == TRUE) - print_wirelen_prob_dist(); - - /* Xifan TANG: Statisitcs for each net which has occupied more than 1 OPIN */ - print_net_opin_occupancy(); -} - -void get_length_and_bends_stats(void) { - - /* Figures out maximum, minimum and average number of bends and net length * - * in the routing. */ - - int inet, bends, total_bends, max_bends; - int length, total_length, max_length; - int segments, total_segments, max_segments; - float av_bends, av_length, av_segments; - int num_global_nets, num_clb_opins_reserved; - - max_bends = 0; - total_bends = 0; - max_length = 0; - total_length = 0; - max_segments = 0; - total_segments = 0; - num_global_nets = 0; - num_clb_opins_reserved = 0; - - for (inet = 0; inet < num_nets; inet++) { - if (clb_net[inet].is_global == FALSE && clb_net[inet].num_sinks != 0) { /* Globals don't count. */ - get_num_bends_and_length(inet, &bends, &length, &segments); - - total_bends += bends; - max_bends = std::max(bends, max_bends); - - total_length += length; - max_length = std::max(length, max_length); - - total_segments += segments; - max_segments = std::max(segments, max_segments); - } else if (clb_net[inet].is_global) { - num_global_nets++; - } else { - num_clb_opins_reserved++; - } - } - - av_bends = (float) total_bends / (float) (num_nets - num_global_nets); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Average number of bends per net: %#g Maximum # of bends: %d\n", av_bends, max_bends); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - av_length = (float) total_length / (float) (num_nets - num_global_nets); - vpr_printf(TIO_MESSAGE_INFO, "Number of routed nets (nonglobal): %d\n", num_nets - num_global_nets); - vpr_printf(TIO_MESSAGE_INFO, "Wirelength results (in units of 1 clb segments)...\n"); - vpr_printf(TIO_MESSAGE_INFO, "\tTotal wirelength: %d, average net length: %#g\n", total_length, av_length); - vpr_printf(TIO_MESSAGE_INFO, "\tMaximum net length: %d\n", max_length); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - av_segments = (float) total_segments / (float) (num_nets - num_global_nets); - vpr_printf(TIO_MESSAGE_INFO, "Wirelength results in terms of physical segments...\n"); - vpr_printf(TIO_MESSAGE_INFO, "\tTotal wiring segments used: %d, average wire segments per net: %#g\n", total_segments, av_segments); - vpr_printf(TIO_MESSAGE_INFO, "\tMaximum segments used by a net: %d\n", max_segments); - vpr_printf(TIO_MESSAGE_INFO, "\tTotal local nets with reserved CLB opins: %d\n", num_clb_opins_reserved); -} - -static void get_channel_occupancy_stats(void) { - - /* Determines how many tracks are used in each channel. */ - - int i, j, max_occ, total_x, total_y; - float av_occ; - int **chanx_occ; /* [1..nx][0..ny] */ - int **chany_occ; /* [0..nx][1..ny] */ - - chanx_occ = (int **) alloc_matrix(1, nx, 0, ny, sizeof(int)); - chany_occ = (int **) alloc_matrix(0, nx, 1, ny, sizeof(int)); - load_channel_occupancies(chanx_occ, chany_occ); - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "X - Directed channels: j\tmax occ\tav_occ\t\tcapacity\n"); - - total_x = 0; - - for (j = 0; j <= ny; j++) { - total_x += chan_width_x[j]; - av_occ = 0.; - max_occ = -1; - - for (i = 1; i <= nx; i++) { - max_occ = std::max(chanx_occ[i][j], max_occ); - av_occ += chanx_occ[i][j]; - } - av_occ /= nx; - vpr_printf(TIO_MESSAGE_INFO, "%d\t%d\t%-#9g\t%d\n", j, max_occ, av_occ, chan_width_x[j]); - } - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Y - Directed channels: i\tmax occ\tav_occ\t\tcapacity\n"); - - total_y = 0; - - for (i = 0; i <= nx; i++) { - total_y += chan_width_y[i]; - av_occ = 0.; - max_occ = -1; - - for (j = 1; j <= ny; j++) { - max_occ = std::max(chany_occ[i][j], max_occ); - av_occ += chany_occ[i][j]; - } - av_occ /= ny; - vpr_printf(TIO_MESSAGE_INFO, "%d\t%d\t%-#9g\t%d\n", i, max_occ, av_occ, chan_width_y[i]); - } - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Total tracks in x-direction: %d, in y-direction: %d\n", total_x, total_y); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - free_matrix(chanx_occ, 1, nx, 0, sizeof(int)); - free_matrix(chany_occ, 0, nx, 1, sizeof(int)); -} - -static void load_channel_occupancies(int **chanx_occ, int **chany_occ) { - - /* Loads the two arrays passed in with the total occupancy at each of the * - * channel segments in the FPGA. */ - - int i, j, inode, inet; - struct s_trace *tptr; - t_rr_type rr_type; - - /* First set the occupancy of everything to zero. */ - - for (i = 1; i <= nx; i++) - for (j = 0; j <= ny; j++) - chanx_occ[i][j] = 0; - - for (i = 0; i <= nx; i++) - for (j = 1; j <= ny; j++) - chany_occ[i][j] = 0; - - /* Now go through each net and count the tracks and pins used everywhere */ - - for (inet = 0; inet < num_nets; inet++) { - - if (clb_net[inet].is_global && clb_net[inet].num_sinks != 0) /* Skip global and empty nets. */ - continue; - - tptr = trace_head[inet]; - while (tptr != NULL) { - inode = tptr->index; - rr_type = rr_node[inode].type; - - if (rr_type == SINK) { - tptr = tptr->next; /* Skip next segment. */ - if (tptr == NULL) - break; - } - - else if (rr_type == CHANX) { - j = rr_node[inode].ylow; - for (i = rr_node[inode].xlow; i <= rr_node[inode].xhigh; i++) - chanx_occ[i][j]++; - } - - else if (rr_type == CHANY) { - i = rr_node[inode].xlow; - for (j = rr_node[inode].ylow; j <= rr_node[inode].yhigh; j++) - chany_occ[i][j]++; - } - - tptr = tptr->next; - } - } -} - -void get_num_bends_and_length(int inet, int *bends_ptr, int *len_ptr, - int *segments_ptr) { - - /* Counts and returns the number of bends, wirelength, and number of routing * - * resource segments in net inet's routing. */ - - struct s_trace *tptr, *prevptr; - int inode; - t_rr_type curr_type, prev_type; - int bends, length, segments; - - bends = 0; - length = 0; - segments = 0; - - prevptr = trace_head[inet]; /* Should always be SOURCE. */ - if (prevptr == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "in get_num_bends_and_length: net #%d has no traceback.\n", inet); - exit(1); - } - inode = prevptr->index; - prev_type = rr_node[inode].type; - - tptr = prevptr->next; - - while (tptr != NULL) { - inode = tptr->index; - curr_type = rr_node[inode].type; - - if (curr_type == SINK) { /* Starting a new segment */ - tptr = tptr->next; /* Link to existing path - don't add to len. */ - if (tptr == NULL) - break; - - curr_type = rr_node[tptr->index].type; - } - - else if (curr_type == CHANX || curr_type == CHANY) { - segments++; - length += 1 + rr_node[inode].xhigh - rr_node[inode].xlow - + rr_node[inode].yhigh - rr_node[inode].ylow; - - if (curr_type != prev_type - && (prev_type == CHANX || prev_type == CHANY)) - bends++; - } - - prev_type = curr_type; - tptr = tptr->next; - } - - *bends_ptr = bends; - *len_ptr = length; - *segments_ptr = segments; -} - -void print_wirelen_prob_dist(void) { - - /* Prints out the probability distribution of the wirelength / number * - * input pins on a net -- i.e. simulates 2-point net length probability * - * distribution. */ - - float *prob_dist; - float norm_fac, two_point_length; - int inet, bends, length, segments, index; - float av_length; - int prob_dist_size, i, incr; - - prob_dist_size = nx + ny + 10; - prob_dist = (float *) my_calloc(prob_dist_size, sizeof(float)); - norm_fac = 0.; - - for (inet = 0; inet < num_nets; inet++) { - if (clb_net[inet].is_global == FALSE && clb_net[inet].num_sinks != 0) { - get_num_bends_and_length(inet, &bends, &length, &segments); - - /* Assign probability to two integer lengths proportionately -- i.e. * - * if two_point_length = 1.9, add 0.9 of the pins to prob_dist[2] and * - * only 0.1 to prob_dist[1]. */ - - two_point_length = (float) length - / (float) (clb_net[inet].num_sinks); - index = (int) two_point_length; - if (index >= prob_dist_size) { - - vpr_printf(TIO_MESSAGE_WARNING, "index (%d) to prob_dist exceeds its allocated size (%d).\n", - index, prob_dist_size); - vpr_printf(TIO_MESSAGE_INFO, "Realloc'ing to increase 2-pin wirelen prob distribution array.\n"); - incr = index - prob_dist_size + 2; - prob_dist_size += incr; - prob_dist = (float *)my_realloc(prob_dist, - prob_dist_size * sizeof(float)); - for (i = prob_dist_size - incr; i < prob_dist_size; i++) - prob_dist[i] = 0.0; - } - prob_dist[index] += (clb_net[inet].num_sinks) - * (1 - two_point_length + index); - - index++; - if (index >= prob_dist_size) { - - vpr_printf(TIO_MESSAGE_WARNING, "Warning: index (%d) to prob_dist exceeds its allocated size (%d).\n", - index, prob_dist_size); - vpr_printf(TIO_MESSAGE_INFO, "Realloc'ing to increase 2-pin wirelen prob distribution array.\n"); - incr = index - prob_dist_size + 2; - prob_dist_size += incr; - prob_dist = (float *)my_realloc(prob_dist, - prob_dist_size * sizeof(float)); - for (i = prob_dist_size - incr; i < prob_dist_size; i++) - prob_dist[i] = 0.0; - } - prob_dist[index] += (clb_net[inet].num_sinks) - * (1 - index + two_point_length); - - norm_fac += clb_net[inet].num_sinks; - } - } - - /* Normalize so total probability is 1 and print out. */ - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Probability distribution of 2-pin net lengths:\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Length p(Lenth)\n"); - - av_length = 0; - - for (index = 0; index < prob_dist_size; index++) { - prob_dist[index] /= norm_fac; - vpr_printf(TIO_MESSAGE_INFO, "%6d %10.6f\n", index, prob_dist[index]); - av_length += prob_dist[index] * index; - } - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Number of 2-pin nets: ;%g;\n", norm_fac); - vpr_printf(TIO_MESSAGE_INFO, "Expected value of 2-pin net length (R): ;%g;\n", av_length); - vpr_printf(TIO_MESSAGE_INFO, "Total wire length: ;%g;\n", norm_fac * av_length); - - free(prob_dist); -} - -void print_lambda(void) { - - /* Finds the average number of input pins used per clb. Does not * - * count inputs which are hooked to global nets (i.e. the clock * - * when it is marked global). */ - - int bnum, ipin; - int num_inputs_used = 0; - int iclass, inet; - float lambda; - t_type_ptr type; - - for (bnum = 0; bnum < num_blocks; bnum++) { - type = block[bnum].type; - assert(type != NULL); - if (type != IO_TYPE) { - for (ipin = 0; ipin < type->num_pins; ipin++) { - iclass = type->pin_class[ipin]; - if (type->class_inf[iclass].type == RECEIVER) { - inet = block[bnum].nets[ipin]; - if (inet != OPEN) /* Pin is connected? */ - if (clb_net[inet].is_global == FALSE) /* Not a global clock */ - num_inputs_used++; - } - } - } - } - - lambda = (float) num_inputs_used / (float) num_blocks; - vpr_printf(TIO_MESSAGE_INFO, "Average lambda (input pins used per clb) is: %g\n", lambda); -} - -int count_netlist_clocks(void) { - - /* Count how many clocks are in the netlist. */ - - int iblock, i, clock_net; - char * name; - boolean found; - int num_clocks = 0; - char ** clock_names = NULL; - - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - if (logical_block[iblock].clock_net != OPEN) { - clock_net = logical_block[iblock].clock_net; - assert(clock_net != OPEN); - name = logical_block[clock_net].name; - /* Now that we've found a clock, let's see if we've counted it already */ - found = FALSE; - for (i = 0; !found && i < num_clocks; i++) { - if (strcmp(clock_names[i], name) == 0) { - found = TRUE; - } - } - if (!found) { - /* If we get here, the clock is new and so we dynamically grow the array netlist_clocks by one. */ - clock_names = (char **) my_realloc (clock_names, ++num_clocks * sizeof(char *)); - clock_names[num_clocks - 1] = name; - } - } - } - free (clock_names); - return num_clocks; -} - - - diff --git a/vpr7_x2p/vpr/SRC/base/stats.h b/vpr7_x2p/vpr/SRC/base/stats.h deleted file mode 100644 index 7db3ed6d2..000000000 --- a/vpr7_x2p/vpr/SRC/base/stats.h +++ /dev/null @@ -1,13 +0,0 @@ -void routing_stats(boolean full_stats, enum e_route_type route_type, - int num_switch, t_segment_inf * segment_inf, int num_segment, - float R_minW_nmos, float R_minW_pmos, - enum e_directionality directionality, boolean timing_analysis_enabled, - float **net_delay, t_slack * slacks, float sram_area); - -void print_wirelen_prob_dist(void); - -void print_lambda(void); - -void get_num_bends_and_length(int inet, int *bends, int *length, int *segments); - -int count_netlist_clocks(void); diff --git a/vpr7_x2p/vpr/SRC/base/verilog_writer.c b/vpr7_x2p/vpr/SRC/base/verilog_writer.c deleted file mode 100644 index e1e6e97e5..000000000 --- a/vpr7_x2p/vpr/SRC/base/verilog_writer.c +++ /dev/null @@ -1,1274 +0,0 @@ - -#include "verilog_writer.h" - -/*********************************************************************************************************** - -Author: Miad Nasr; August 30, 2012 - -The code in this file generates the Verilog and SDF files for the post-synthesized circuit. The Verilog file -can be used to perform functional simulation and the SDF file enables timing simulation of the post-synthesized circuit. - -The Verilog file contains instantiated modules of the primitives in the circuit. Currently VPR can generate -Verilog files for circuits that only contain LUTs , Flip Flops , IOs , Multipliers , and BRAMs. The Verilog -description of these primitives are in the primitives.v file. To simulate the post-synthesized circuit, one -must include the generated Verilog file and also the primitives.v Verilog file, in the simulation directory. - -If one wants to generate the post-synthesized Verilog file of a circuit that contains a primitive other than -those mentioned above, he/she should contact the VTR team to have the source code updated. Furthermore to -perform simulation on that circuit the Verilog description of that new primitive must be appended to the -primitives.v file as a separate module. - -The VTR team can be contacted through the VTR website: -http://code.google.com/p/vtr-verilog-to-routing/ - -***********************************************************************************************************/ - -/*The verilog_writer function is the main function that will generate and write to the verilog and SDF files -All the functions declared bellow are called directly or indirectly by verilog_writer() - -Basic Description of how verilog_writer() writes the Verilog and SDF files: - -First - The name of the clock signal in the circuit is stored in clock_name. the find_clock_name() function - searches through all the inputs of the design and returns the name of the clock in the design. The verilog - writer currently works with only single clocked circuits - -Second - instantiate_top_level() module is called. This function will will traverse through all the inputs and - outputs in the circuit and instantiate the list of inputs and inputs in the top level module - -Third - instantiate_SDF_header() is a short function that will just write the top level declarations in the SDF file. - -Fourth - All the wires in the design are instantiated. This is done in the way demonstrated below: - - Traverse through all primitives - - -For each primitive traverse through all input ports - -For each input port traverse through all input pins and then instantiate the wire - - -For each primitive traverse through all output ports - -For each output port traverse through all output pins and then instantiate the wire - -Fifth - Instantiate_input_interconnect() will instantiate the interconnect modules that connect the inputs to the design to the rest of the primitives. - -Sixth - Instantiate_primitive_modules() will instantiate all the primitives in the design. This is how this function works in summary: - - Traverse through all primitives - - -For each primitive instantiate the primitive module and instantiate inputs/outputs by traversing - -For each primitive instantiate the interconnect modules that conect the outputs of that primitive - to other primitives - -Instantiate the SDF block corersponding to this primitive - - -*/ - -void verilog_writer(void) -{ - FILE *verilog; - FILE *SDF; - char * verilog_file_name = (char *)malloc((strlen(blif_circuit_name) + strlen("_post_synthesis.v") + 1) *sizeof(char));/*creating the Verilog file name*/ - char * sdf_file_name = (char *)malloc((strlen(blif_circuit_name) + strlen("_post_synthesis.sdf") + 1) *sizeof(char));/*creating the SDF file name*/ - char *clock_name;/*Will need to store the clock name of the design if any exist*/ - assert(verilog_file_name); - assert(sdf_file_name); - printf("\nWriting the post-synthesized circuit Verilog and SDF.....\n..."); - - sprintf(verilog_file_name, "%s%s", blif_circuit_name, "_post_synthesis.v"); - sprintf(sdf_file_name, "%s%s", blif_circuit_name, "_post_synthesis.sdf"); - - /*Openning the post synthesized netlist files*/ - verilog = fopen(verilog_file_name , "w"); - SDF = fopen(sdf_file_name , "w"); - - clock_name = find_clock_name(); - instantiate_top_level_module(verilog); - instantiate_SDF_header(SDF); - instantiate_wires(verilog); - instantiate_input_interconnect(verilog , SDF , clock_name); - instantiate_primitive_modules(verilog,clock_name,SDF); - - fprintf(verilog , "\nendmodule\n"); - fprintf(SDF , ")\n"); - fclose(verilog); - fclose(SDF); - printf("Done\n\n"); -} - -/*The function instantiate_top_level_module instantiates the top level verilog module of the post-synthesized circuit and the list of inputs and outputs to that module*/ -void instantiate_top_level_module(FILE *verilog) -{ - int i,place_comma; - pb_list *temp=NULL; - pb_list *current; - char *fixed_name = NULL; - - - fprintf(verilog , "module %s(\n" , blif_circuit_name); - place_comma=0; - for(i=0 ; ipb_graph_node->pb_type->name,"io"))/*if this block is an i/o block*/ - { - temp = traverse_clb(block[i].pb , temp);/*find all the primitives in this block*/ - for(current=temp ; current!=NULL ; current=current->next)/*traverse through all the primitives in this block*/ - { - if(place_comma){ /*need this for correct placement of commas and verilog syntax correctness*/ - fprintf(verilog ,"\t,"); - } - else{ - fprintf(verilog ,"\t"); - place_comma=1; - } - fixed_name = fix_name(current->pb->name);/*need to do this, because some names contain characters that cause syntax errors in verilog (e.g. '~' , '^',)*/ - if(!strcmp(logical_block[current->pb->logical_block].model->name,"input")){/*if this primitive is an input pin, declare as input*/ - - fprintf(verilog , "input %s\n",fixed_name);/*declaring the inputs*/ - - - } - else if(!strcmp(logical_block[current->pb->logical_block].model->name,"output")){ - - fprintf(verilog , "output %s\n",fixed_name);/*declaring the outputs*/ - } - free(fixed_name); - } - } - temp = free_linked_list(temp); - } - fprintf(verilog , ");\n\n"); - -} - -void instantiate_SDF_header(FILE *SDF) -{ - fprintf(SDF , "(DELAYFILE\n\t(SDFVERSION \"2.1\")\n\t(DIVIDER /)\n\t(TIMESCALE 1 ps)\n\n "); -} - -/*The instantiate_wires function instantiates all the wire in the post-synthesized design*/ -void instantiate_wires(FILE *verilog) -{ - int i,j,k; - pb_list *primitive_list=NULL; - pb_list *current; - char *fixed_name = NULL; - - for(i=0; inext)/*traverse through all the primitives in this block*/ - { - fixed_name = fix_name(current->pb->name);/*need to do this, because some names contain characters that cause syntax errors in verilog (e.g. '~' , '^',)*/ - for(j=0 ; jpb->pb_graph_node->num_output_ports ; j++)/*go through all the found primitives and instantiate their output wires*/ - { - for(k=0 ; kpb->pb_graph_node->num_output_pins[j] ; k++) - { - - - fprintf(verilog , "wire %s_output_%d_%d;\n" , fixed_name , j , k); - - if(!strcmp(logical_block[current->pb->logical_block].model->name,"input"))/*if that pin is an inpad pin then have to connect the - inputs to the module to this wire*/ - { - fprintf(verilog , "assign %s_output_%d_%d = %s;\n\n",fixed_name , j , k , fixed_name); - } - - - } - } - for(j=0 ; jpb->pb_graph_node->num_input_ports ; j++)/*instantiating the input wire modules for each primitive*/ - { - for(k=0 ; kpb->pb_graph_node->num_input_pins[j] ; k++) - { - fprintf(verilog , "wire %s_input_%d_%d;\n" , fixed_name , j , k); - if(!strcmp(logical_block[current->pb->logical_block].model->name,"output"))/*if that pin is an outpad then have to connect the input to the outputs - of the top level module*/ - { - fprintf(verilog , "assign %s = %s_input_%d_%d;\n\n",fixed_name , fixed_name , j , k); - } - } - } - free(fixed_name); - } - primitive_list = free_linked_list(primitive_list); - } -} - -/* - The function instantiate_input_interconnect will instantiate the interconnect segments from input pins to the rest of the design. - This function is necessary because the inputs to the design are not instantiated as a module in verilog. -*/ -void instantiate_input_interconnect(FILE *verilog , FILE *SDF , char *clock_name) -{ - int blocks; - pb_list *current; - pb_list *primitive_list = NULL; - conn_list *downhill = NULL; - - for(blocks=0 ; blockspb_graph_node->pb_type->name,"io"))/*if this is an io block*/ - { - continue; - } - primitive_list = traverse_clb(block[blocks].pb , primitive_list);/*find all the primitives in that block*/ - for(current=primitive_list ; current!=NULL ; current=current->next)/*traversing through all the found primitives*/ - { - if(strcmp(logical_block[current->pb->logical_block].model->name,"input"))/*if that primitive is an inpad*/ - { - continue; - } - if(clock_name && !strcmp(current->pb->name,clock_name))/*If this is the clock signal, then don't instantiate an interconnect for it*/ - { - continue; - } - downhill = find_connected_primitives_downhill(blocks , current->pb , downhill );/*find all the other primitives that it connects to*/ - - /*traverse_linked_list_conn(downhill);*/ - interconnect_printing(verilog , downhill);/*Print the interconnects modules that connect the inputs to the rest of the design*/ - SDF_interconnect_delay_printing(SDF , downhill);/*Print the Delays of the interconnect module to the SDF file*/ - downhill = free_linked_list_conn(downhill); - break; - } - primitive_list = free_linked_list(primitive_list); - } -} - -/*This function instantiates the primitive verilog modules e.g. LUTs ,Flip Flops, etc.*/ -void instantiate_primitive_modules(FILE *fp, char *clock_name , FILE *SDF) -{ - int i,j,k,h; - pb_list *primitives = NULL; - pb_list *current; - - int place_comma=0; - char *truth_table = NULL; - int inputs_to_lut; - char *fixed_name = NULL; - int power; - for(i=0 ; inext)/*traverse through all the found primitives*/ - { - - fixed_name = fix_name(current->pb->name); - - if(!strcmp(logical_block[current->pb->logical_block].model->name,"names"))/*if this primitive is a lut*/ - { - inputs_to_lut = find_number_of_inputs(current->pb); - assert((inputs_to_lut >= 3) && (inputs_to_lut <= 7));/*currently the primitives.v file only contains the verilog description for 4LUTs and 6LUTs*/ - truth_table=load_truth_table(inputs_to_lut,current->pb);/*load_truth_table will find the truth table corresponding to this lut, and store it in "truth_table"*/ - - /*instantiating the 6 input lut module and passing the truth table as parameter*/ - - power = 1 << inputs_to_lut; - fprintf(fp , "\nLUT_%d #(%d'b%s) lut_%s(", inputs_to_lut , power , truth_table , fixed_name); - - free(truth_table); - - j=0; - for(k=0 ; kpb->pb_graph_node->num_input_ports ; k++)/*traverse through all the input pins of the lut*/ - { - for(h=0 ; hpb->pb_graph_node->num_input_pins[k] ; h++) - { - if(current->pb->rr_graph[current->pb->pb_graph_node->input_pins[k][h].pin_count_in_cluster].net_num != OPEN)/*check if that pin is used*/ - { - if(place_comma)/*need this flag check to properly place the commas*/ - { - fprintf(fp , " , %s_input_%d_%d" , fixed_name , k , j); // j was h - } - else - { - fprintf(fp , "%s_input_%d_%d" , fixed_name , k , j); // j was h - place_comma=1; - } - j++; - } - } - } - while(jpb,SDF);/*this function will instantiate the routing - interconnect from the output of this lut to - the inputs of other luts that it connects to*/ - sdf_LUT_delay_printing(SDF , current->pb);/*This function will instantiate the internal delays of the lut to the SDF file*/ - } - else if(!strcmp(logical_block[current->pb->logical_block].model->name,"latch"))/*If this primitive is a Flip Flop*/ - { - char *fixed_clock_name; - fixed_clock_name = fix_name(clock_name); - fprintf(fp , "\nD_Flip_Flop DFF_%s(%s_output_0_0 , %s_input_0_0 , 1'b1 , 1'b1 , %s_output_0_0 );\n",fixed_name,fixed_clock_name,fixed_name,fixed_name); - instantiate_interconnect(fp , i , current->pb , SDF); - sdf_DFF_delay_printing(SDF , current->pb); - free(fixed_clock_name); - } - else if(!strcmp(logical_block[current->pb->logical_block].model->name,"multiply") || - !strcmp(logical_block[current->pb->logical_block].model->name,"adder")) /*If this primitive is a multiplier or an adder */ - { - /** multipliers and adders are handled quite similarly **/ - - int mult = !strcmp(logical_block[current->pb->logical_block].model->name,"multiply"); - int num_inputs = logical_block[current->pb->logical_block].pb->pb_graph_node->num_input_pins[0];/*what is the data width*/ - int i_port , i_pin ; - place_comma = 0; - if (mult) - fprintf(fp , "\nmult #(%d)%s(" , num_inputs , fixed_name); - else - fprintf(fp , "\nripple_adder #(%d)%s(" , num_inputs , fixed_name); - - /*Traversing through all the input ports of this multiplier*/ - for(i_port=0 ; i_portpb->logical_block].pb->pb_graph_node->num_input_ports ; i_port++) - { - if(i_port == 0)/*This if-else statement will make sure that the signals are concatinated in verilog*/ - { - fprintf(fp , "{"); - } - else{ - fprintf(fp , ",{"); - } - place_comma = 0; - /*Traversing through all the input pins of this input port*/ - for(i_pin=logical_block[current->pb->logical_block].pb->pb_graph_node->num_input_pins[i_port]-1 ; i_pin>=0 ; i_pin--) - { - /*If this input pin is used*/ - if(current->pb->rr_graph[current->pb->pb_graph_node->input_pins[i_port][i_pin].pin_count_in_cluster].net_num != OPEN) - { - if(place_comma)/*need this flag check to properly place the commas*/ - { - fprintf(fp , " , %s_input_%d_%d" , fixed_name , i_port , i_pin); - } - else - { - fprintf(fp , "%s_input_%d_%d" , fixed_name , i_port , i_pin); - place_comma=1; - } - - } - else{/*If this pin was not used, then instantiate logic zero*/ - if(place_comma) - { - fprintf(fp , ", 1'b0"); - } - else{ - fprintf(fp , " 1'b0"); - place_comma = 1; - } - } - } - fprintf(fp , "}");/*End concatination*/ - } - /*Traversing through all the output ports of this multiplier*/ - for(i_port=0 ; i_portpb->logical_block].pb->pb_graph_node->num_output_ports ; i_port++) - { - fprintf(fp , ",{");/*Since there is only a single output port for multipliers we only need to concatinate once*/ - place_comma = 0; - /*Traversing through all the output pins of this output port*/ - for(i_pin=logical_block[current->pb->logical_block].pb->pb_graph_node->num_output_pins[i_port]-1 ; i_pin>=0 ; i_pin--) - { - if(place_comma) - { - fprintf(fp , ", %s_output_%d_%d" , fixed_name , i_port , i_pin); - } - else{ - fprintf(fp , " %s_output_%d_%d" , fixed_name , i_port , i_pin); - place_comma = 1; - } - } - fprintf(fp , "}");/*End concatination*/ - } - fprintf(fp , ");\n\n"); - instantiate_interconnect(fp , i , current->pb , SDF); - if (mult) - SDF_Mult_delay_printing(SDF, current->pb); - else - SDF_Adder_delay_printing(SDF, current->pb); - } - else if(!strcmp(logical_block[current->pb->logical_block].model->name,"single_port_ram")){/*If this primitive is a single port RAM block*/ - - char *fixed_clock_name; - int i_port,i_pin; - int data_width,addr_width; - - data_width = logical_block[current->pb->logical_block].pb->pb_graph_node->num_input_pins[1];/*the data_width (word width) is the number of inputs in the data port*/ - addr_width = logical_block[current->pb->logical_block].pb->pb_graph_node->num_input_pins[0];/*the addr_width (address width) is the number of inputs in the addr port*/ - - fprintf(fp , "\nsingle_port_ram #(%d,%d)%s(" , addr_width , data_width , fixed_name);/*Passing the address width and data width as a verilog parameter*/ - /*Traversign through all the input ports of this single_port_ram*/ - for(i_port=0 ; i_portpb->logical_block].pb->pb_graph_node->num_input_ports ; i_port++) - { - if(i_port == 0)/*This if-else statement will make sure that the signals are concatinated in verilog*/ - { - fprintf(fp , "{"); - } - else{ - fprintf(fp , ",{"); - } - place_comma = 0; - /*Traversing through all the input pins of this input port*/ - for(i_pin=logical_block[current->pb->logical_block].pb->pb_graph_node->num_input_pins[i_port]-1 ; i_pin>=0 ; i_pin--) - { - /*If this input pin is used*/ - if(current->pb->rr_graph[current->pb->pb_graph_node->input_pins[i_port][i_pin].pin_count_in_cluster].net_num != OPEN) - { - if(place_comma)/*need this flag check to properly place the commas*/ - { - fprintf(fp , " , %s_input_%d_%d" , fixed_name , i_port , i_pin); - } - else - { - fprintf(fp , "%s_input_%d_%d" , fixed_name , i_port , i_pin); - place_comma=1; - } - } - else{/*If this input pin is not used then instantiate a logic zero*/ - if(place_comma) - { - fprintf(fp , ", 1'b0"); - } - else{ - fprintf(fp , " 1'b0"); - place_comma = 1; - } - } - } - fprintf(fp , "}");/*End concatination*/ - } - /*Traversign through all the output ports of this single_port_ram*/ - for(i_port=0 ; i_portpb->logical_block].pb->pb_graph_node->num_output_ports ; i_port++) - { - fprintf(fp , ",{");/*Since there is only a single output port for single_port_rams we only need to concatinate once*/ - place_comma = 0; - /*Traverse through all the output pins of this output port*/ - for(i_pin=logical_block[current->pb->logical_block].pb->pb_graph_node->num_output_pins[i_port]-1 ; i_pin>=0 ; i_pin--) - { - if(place_comma) - { - fprintf(fp , ", %s_output_%d_%d" , fixed_name , i_port , i_pin); - } - else{ - fprintf(fp , " %s_output_%d_%d" , fixed_name , i_port , i_pin); - place_comma = 1; - } - } - fprintf(fp , "}");/*End concatination*/ - } - fixed_clock_name = fix_name(clock_name);/*Must also instantiate the clock signal to the RAM block*/ - fprintf(fp , ", %s_output_0_0" , fixed_clock_name); - fprintf(fp , ");\n\n"); - free(fixed_clock_name); - instantiate_interconnect(fp , i , current->pb , SDF); - SDF_ram_single_port_delay_printing(SDF , current->pb); - } - else if(!strcmp(logical_block[current->pb->logical_block].model->name,"dual_port_ram")){/*If this primitive is a dual_port_ram*/ - - int data1_width,data2_width,addr1_width,addr2_width,i_port,i_pin; - char *fixed_clock_name; - - /*The Input ports of dual port rams are in this order: - 0-addr1 - 1-addr2 - 2-data1 - 3-data2 - 4-we1 - 5-we2 - - The verilog primitives module only accepts instatiation in this order else the simulation will give error or give incorrect simulation results*/ - - data1_width = current->pb->pb_graph_node->num_input_pins[2];/*the data_width (word width) for the first port, is the number of inputs in the first data port*/ - addr1_width = current->pb->pb_graph_node->num_input_pins[0];/*the addr_width (address width) for the first port, is the number of inputs in the first addr port*/ - data2_width = current->pb->pb_graph_node->num_input_pins[3];/*the data_width (word width) for the second port, is the number of inputs in the second data port*/ - addr2_width = current->pb->pb_graph_node->num_input_pins[1];/*the addr_width (address width) for the second port is the number of inputs in the second addr port*/ - - fprintf(fp , "\ndual_port_ram #(%d,%d,%d,%d)%s(" , addr1_width , data1_width , addr2_width , data2_width , fixed_name);/*passing the addr_wdith and data_wdith for both ports as verilog parameter*/ - - for(i_port=0 ; i_portpb->logical_block].pb->pb_graph_node->num_input_ports ; i_port++) - { - if(i_port == 0) - { - fprintf(fp , "{"); - } - else{ - fprintf(fp , ",{"); - } - place_comma = 0; - /*Traversign through all the input pins of this input port*/ - for(i_pin=logical_block[current->pb->logical_block].pb->pb_graph_node->num_input_pins[i_port]-1 ; i_pin>=0 ; i_pin--) - { - /*If this pin is used*/ - if(current->pb->rr_graph[current->pb->pb_graph_node->input_pins[i_port][i_pin].pin_count_in_cluster].net_num != OPEN) - { - if(place_comma)/*need this flag check to properly place the commas*/ - { - fprintf(fp , " , %s_input_%d_%d" , fixed_name , i_port , i_pin); - } - else - { - fprintf(fp , "%s_input_%d_%d" , fixed_name , i_port , i_pin); - place_comma=1; - } - } - else{/*If this pin is not used, then instantiate logic zero instead*/ - if(place_comma) - { - fprintf(fp , ", 1'b0"); - } - else{ - fprintf(fp , " 1'b0"); - place_comma = 1; - } - } - } - fprintf(fp , "}");/*End concatination*/ - } - /*Traversign through all the output ports of this dual_port_ram*/ - for(i_port=0 ; i_portpb->logical_block].pb->pb_graph_node->num_output_ports ; i_port++) - { - fprintf(fp , ",{"); - place_comma = 0; - /*Traverse through all the output pins of this output port*/ - for(i_pin=logical_block[current->pb->logical_block].pb->pb_graph_node->num_output_pins[i_port]-1 ; i_pin>=0 ; i_pin--) - { - if(place_comma) - { - fprintf(fp , ", %s_output_%d_%d" , fixed_name , i_port , i_pin); - } - else{ - fprintf(fp , " %s_output_%d_%d" , fixed_name , i_port , i_pin); - place_comma = 1; - } - } - fprintf(fp , "}"); - } - fixed_clock_name = fix_name(clock_name);/*Must also instantiate the clock */ - fprintf(fp , ", %s_output_0_0" , fixed_clock_name); - fprintf(fp , ");\n\n"); - free(fixed_clock_name); - instantiate_interconnect(fp , i , current->pb , SDF); - SDF_ram_dual_port_delay_printing(SDF , current->pb); - - } - else if(strcmp(logical_block[current->pb->logical_block].model->name,"input") && strcmp(logical_block[current->pb->logical_block].model->name,"output")) - /*If this primitive is anything else, but an input or an output*/ - { - printf("Failed to generate post-synthesized verilog and sdf files. Primitive %s is unknown.\n\nAcceptable primitives are: LUTs, Flip Flops, IOs, Adders, Rams, and Multiplier blocks.\n\nTo generate the post synthesized verilog and SDF files successfully, you must append the verilog code for the %s to the primitives.v file, and contact the VPR developers team on the website: http://code.google.com/p/vtr-verilog-to-routing/ to update the VPR source code to handle the new primitive. \n",logical_block[current->pb->logical_block].model->name , logical_block[current->pb->logical_block].model->name); - exit(1); - } - free(fixed_name); - } - primitives = free_linked_list(primitives); - } -} - -/*This function instantiates the interconnect modules that connect from the output pins of the primitive "pb" to whatever it connects to block_num is the block number that the pb resides in*/ -void instantiate_interconnect(FILE *verilog , int block_num , t_pb *pb , FILE *SDF) -{ - conn_list *downhill_connections = NULL; - - downhill_connections = find_connected_primitives_downhill(block_num , pb , downhill_connections);/*find all the other luts that the lut corresponding to "pb", connects to*/ - - interconnect_printing(verilog , downhill_connections); - SDF_interconnect_delay_printing(SDF , downhill_connections); - downhill_connections = free_linked_list_conn(downhill_connections); -} - -/*load_truth_table returns the truth table of the LUT corresponding to "pb" -inputs: total number of inputs that the LUT has. -pb: the t_pb data structure corresponding to the LUT*/ - -char *load_truth_table(int inputs , t_pb *pb) -{ - int number_of_dont_cares=0; - int tries,shift,which_row,i,j; - int possibles = 1 << inputs; - char *tt_row_blif; - char *possible_row = (char *)malloc(inputs+1 * sizeof(char)); - char *tt = (char *)malloc((possibles+1) * sizeof(char)); - struct s_linked_vptr *current; - int number_of_used_inputs_to_lut; - char set_to; - assert(possible_row); - assert(tt); - - if (logical_block[pb->logical_block].truth_table) { // ??? janders ???? how can you have a LUT without a truth table??? - tt_row_blif = (char *)logical_block[pb->logical_block].truth_table->data_vptr; - } - else { // must be producing a GROUND - for (i = 0; i < possibles; i++) - tt[i] = '0'; - tt[possibles] = '\0'; - free(possible_row); - return tt; - } - set_to = tt_row_blif[strlen(tt_row_blif)-1]; - - /*filling the truth table with the state that is opposite to the output state in the blif truth table*/ - if(set_to =='1') - { - for(i=0 ; ilogical_block].truth_table ; current!=NULL ; current=current->next)/*traversing through all the lines of the blif truth table*/ - { - - tt_row_blif=(char *)current->data_vptr;/*tt_row_blif stores the current truth table line*/ - - - /*counting number of don't cares in this line of the blif truth table*/ - number_of_used_inputs_to_lut = strlen(tt_row_blif)-2;/*used*/ - if(number_of_used_inputs_to_lut == 0)/*If this is a constant generator, then the truth table only contains the constant value that it generates.*/ - { - for(i=0 ; i>shift) & 0x1) == 1) - { - possible_row[j] = '1'; - } - else{ - possible_row[j] = '0'; - } - shift--;/*reduce the shift value by one*/ - } - else - { - possible_row[j]=tt_row_blif[j]; - } - } - possible_row[j]=0x0;/*null terminate the temporary truth table row*/ - which_row = find_index(possible_row,inputs);/*find index returns the index of the 64bit truth table that this temporary truth table row corresponds to*/ - tt[possibles-1-which_row] = set_to; - } - } - number_of_dont_cares = 0; - } - free(possible_row); - return(tt); -} - -int find_index(char *row,int inputs)/*returns the index of the 64bit truth table that this temporary truth table row corresponds to*/ -{ - int index=0;/*initially setting index to 0*/ - int or_=0x1; - int i,length; - - for(i=strlen(row)-1 ; i>=0 ; i--)/*traverse through the columns of this truth table row*/ - { - if(row[i] == '1') - { - index |= or_;/*if this column is logic 1, then set this column in index to logic 1.*/ - } - or_ = or_ << 1; - } - length = strlen(row); - if(length57 && (int)new_[i]<65) || ((int)new_[i]>90 && (int)new_[i]<97) || (int)new_[i]>122) - { - new_[i]='_'; - } - } - return(new_); -} - -/*This function finds the number of inputs to a primitive.*/ -int find_number_of_inputs(t_pb *pb) -{ - int i,j,count=0; - for(i=0 ; ipb_graph_node->num_input_ports ; i++) - { - for(j=0 ; jpb_graph_node->num_input_pins[i] ; j++) - { - count++; - } - } - return(count); -} - -/*This function is a utility function called by intantiate_interconnect*/ -void interconnect_printing(FILE *fp , conn_list *downhill) -{ - char *fixed_name1; - char *fixed_name2; - conn_list *connections; - int port_number_out=-1,port_number_in=-1,i; - - for(connections=downhill ; connections!=NULL ; connections=connections->next)/*traverse through all the connected primitives and instantiate a routing interconect module*/ - { - fixed_name1 = fix_name(connections->driver_pb->name); - fixed_name2 = fix_name(connections->load_pb->name); - - for(i=0 ; iload_pin->parent_node->num_input_ports ; i++) - { - if(!strcmp(connections->load_pin->parent_node->input_pins[i][0].port->name,connections->load_pin->port->name)) - { - port_number_out = i; - } - } - for(i=0 ; idriver_pin->parent_node->num_output_ports ; i++) - { - if(!strcmp(connections->driver_pin->parent_node->output_pins[i][0].port->name,connections->driver_pin->port->name)) - { - port_number_in = i; - } - } - assert(port_number_out >= 0 && port_number_in >= 0); - - fprintf(fp , "interconnect routing_segment_%s_output_%d_%d_to_%s_input_%d_%d( %s_output_%d_%d , %s_input_%d_%d );\n", - fixed_name1 , port_number_in/*connections->driver_pin->port->port_index_by_type*/ , connections->driver_pin->pin_number, - fixed_name2 , port_number_out , connections->load_pin->pin_number, - fixed_name1 , port_number_in/*connections->driver_pin->port->port_index_by_type*/ , connections->driver_pin->pin_number, - fixed_name2 , port_number_out , connections->load_pin->pin_number); - - free(fixed_name1); - free(fixed_name2); - } -} - -/*This funciton will instantiate the SDF cell that contains the delay information of the Verilog interconnect modules*/ -void SDF_interconnect_delay_printing(FILE *SDF , conn_list *downhill) -{ - conn_list *connections; - char *fixed_name1; - char *fixed_name2; - float internal_delay; - int del; - int port_number_out=-1,port_number_in=-1,i; - - for(connections=downhill ; connections!=NULL ; connections=connections->next)/*traverse through all the connected primitives and instantiate a routing interconect module*/ - { - fixed_name1 = fix_name(connections->driver_pb->name); - fixed_name2 = fix_name(connections->load_pb->name); - - for(i=0 ; iload_pin->parent_node->num_input_ports ; i++) - { - if(!strcmp(connections->load_pin->parent_node->input_pins[i][0].port->name,connections->load_pin->port->name)) - { - port_number_out = i; - } - } - for(i=0 ; idriver_pin->parent_node->num_output_ports ; i++) - { - if(!strcmp(connections->driver_pin->parent_node->output_pins[i][0].port->name,connections->driver_pin->port->name)) - { - port_number_in = i; - } - } - internal_delay = connections->driver_to_load_delay; - internal_delay = internal_delay * 1000000000000.00; /*converting the delay from seconds to picoseconds*/ - internal_delay = internal_delay + 0.5; /*Rounding the delay to the nearset picosecond*/ - del = (int)internal_delay; - - fprintf(SDF , "\t(CELL\n\t(CELLTYPE \"interconnect\")\n\t(INSTANCE inst/routing_segment_%s_output_%d_%d_to_%s_input_%d_%d)\n" , - fixed_name1 , port_number_in/*connections->driver_pin->port->port_index_by_type*/ , connections->driver_pin->pin_number, - fixed_name2 , port_number_out , connections->load_pin->pin_number); - fprintf(SDF , "\t\t(DELAY\n\t\t(ABSOLUTE\n\t\t\t(IOPATH datain dataout (%d:%d:%d)(%d:%d:%d))\n\t\t)\n\t\t)\n\t)\n" , - del , del , del , del , del , del); - - free(fixed_name1); - free(fixed_name2); - - } -} - -/*This function instantiates the SDF cell that contains the delay information of a LUT*/ -void sdf_LUT_delay_printing(FILE *SDF , t_pb *pb) -{ - char *fixed_name; - int j,pin_count; - float internal_delay; - int del; - int logical_block_index = pb->logical_block; - int record = 0; - - fixed_name = fix_name(pb->name); - - for(j=0 ; j < pb->pb_graph_node->num_input_pins[0] ; j++)/*Assuming that LUTs have a single input port*/ - { - if (logical_block[logical_block_index].input_nets[0][j] != OPEN) - { - - int q; - pin_count = OPEN; - for (q = 0; q < pb->pb_graph_node->num_input_pins[0]; q++) - { - pin_count = pb->pb_graph_node->input_pins[0][q].pin_count_in_cluster; - if (logical_block[logical_block_index].pb->rr_graph[pin_count].net_num == logical_block[logical_block_index].input_nets[0][j]) - break; - } - - assert(q != pb->pb_graph_node->num_input_pins[0]); - - internal_delay = pb->rr_graph[pin_count].tnode->out_edges->Tdel; - internal_delay = internal_delay * 1000000000000.00;/*converting the delay from seconds to picoseconds*/ - internal_delay = internal_delay + 0.5; /*Rounding the delay to the nearset picosecond*/ - del = (int)internal_delay; - - if (!record) { // print the SDF record header - fprintf(SDF , "\t(CELL\n\t(CELLTYPE \"LUT_%d\")\n\t(INSTANCE inst/lut_%s)\n\t\t(DELAY\n\t\t(ABSOLUTE\n" , find_number_of_inputs(pb) , fixed_name); - record = 1; - } - - fprintf(SDF , "\t\t\t(IOPATH inter%d/datain inter%d/dataout (%d:%d:%d)(%d:%d:%d))\n" , j , j , del , del , del , del , del , del); - } - } - if (record) - fprintf(SDF , "\t\t)\n\t\t)\n\t)\n"); - free(fixed_name); -} - -/*This function instantiates the SdF cell that contains the delay information of a Flip Flop*/ -void sdf_DFF_delay_printing(FILE *SDF , t_pb *pb) -{ - char *fixed_name; - float internal_delay; - int del,pin_count; - - fixed_name = fix_name(pb->name); - fprintf(SDF , "\t(CELL\n\t(CELLTYPE \"D_Flip_Flop\")\n\t(INSTANCE inst/DFF_%s)\n\t\t(DELAY\n\t\t(ABSOLUTE\n" , fixed_name); - - pin_count = pb->pb_graph_node->output_pins[0][0].pin_count_in_cluster; // the Q output of the FF (which has only a single output port and pin) - assert(pb->rr_graph[pin_count].tnode); - internal_delay = pb->rr_graph[pin_count].tnode->T_arr * 1.0E12 + 0.5; - del = (int)internal_delay; - - fprintf(SDF , "\t\t\t(IOPATH (posedge clock) Q (%d:%d:%d)(%d:%d:%d))\n" , del , del , del , del , del , del); - fprintf(SDF , "\t\t)\n\t\t)\n\t)\n"); - free(fixed_name); -} - -void SDF_Mult_delay_printing(FILE *SDF , t_pb *pb) -{ - char *fixed_name; - int pin_count; - float internal_delay; - int del; - - fixed_name = fix_name(pb->name); - fprintf(SDF , "\t(CELL\n\t(CELLTYPE \"mult\")\n\t(INSTANCE inst/%s)\n\t\t(DELAY\n\t\t(ABSOLUTE\n" , fixed_name); - - - pin_count = pb->pb_graph_node->input_pins[0][0].pin_count_in_cluster; - assert(pb->rr_graph[pin_count].tnode); - internal_delay = pb->rr_graph[pin_count].tnode->out_edges->Tdel; - internal_delay = internal_delay * 1000000000000.00;/*converting the delay from seconds to picoseconds*/ - internal_delay = internal_delay + 0.5; /*Rounding the delay to the nearset picosecond*/ - del = (int)internal_delay; - fprintf(SDF , "\t\t\t(IOPATH delay/A delay/B (%d:%d:%d)(%d:%d:%d))\n" , del , del , del , del , del , del); - - pin_count = pb->pb_graph_node->input_pins[1][0].pin_count_in_cluster; - assert(pb->rr_graph[pin_count].tnode); - internal_delay = pb->rr_graph[pin_count].tnode->out_edges->Tdel; - internal_delay = internal_delay * 1.0E12;/*converting the delay from seconds to picoseconds*/ - internal_delay = internal_delay + 0.5; /*Rounding the delay to the nearset picosecond*/ - del = (int)internal_delay; - fprintf(SDF , "\t\t\t(IOPATH delay2/A delay2/B (%d:%d:%d)(%d:%d:%d))\n" , del , del , del , del , del , del); - - fprintf(SDF , "\t\t)\n\t\t)\n\t)\n"); - free(fixed_name); - -} - -void SDF_Adder_delay_printing(FILE *SDF , t_pb *pb) -{ - int i, j, k; - int total_input_ports = pb->pb_graph_node->num_input_ports; - int pin_count; - char *fixed_name; - int record = 0; - - fixed_name = fix_name(pb->name); - - for (i = 0; i < total_input_ports; i++) { - - for (j = 0; j < pb->pb_graph_node->num_input_pins[i]; j++) { - - pin_count = pb->pb_graph_node->input_pins[i][j].pin_count_in_cluster; - - t_tnode* tNodeInput = pb->rr_graph[pin_count].tnode; // source pin of timing arc - - if (!tNodeInput) - continue; // no timing information on pin - - for (k = 0; k < tNodeInput->num_edges; k++) { - - t_tnode tNodeOutput = tnode[tNodeInput->out_edges[k].to_node]; // dest pin of timing arc - int del = (tNodeInput->out_edges[k].Tdel * 1.0E12 + 0.5); - - if (!record) { // print the SDF record header - fprintf(SDF , "\t(CELL\n\t(CELLTYPE \"ripple_adder\")\n\t(INSTANCE inst/%s)\n\t\t(DELAY\n\t\t(ABSOLUTE\n" , fixed_name); - record = 1; - } - - fprintf(SDF , "\t\t\t(IOPATH %s %s (%d:%d:%d)(%d:%d:%d))\n" , tNodeInput->pb_graph_pin->port->name, - tNodeOutput.pb_graph_pin->port->name, - del , del , del , del , del , del); - - } - j = pb->pb_graph_node->num_input_pins[i]; // skip to the next port -- JANDERS to fix - // what we really want to do here is find the max delay between any pin of the input port, to any pin of the output port - } - } - - if (record) - fprintf(SDF , "\t\t)\n\t\t)\n\t)\n"); - free(fixed_name); -} - - -void SDF_ram_single_port_delay_printing(FILE *SDF , t_pb *pb) -{ - // int num_inputs; - char *fixed_name; - int pin_count; - float internal_delay; - int del; - - // num_inputs = pb->pb_graph_node->num_input_pins[0]; - fixed_name = fix_name(pb->name); - fprintf(SDF , "\t(CELL\n\t(CELLTYPE \"single_port_ram\")\n\t(INSTANCE inst/%s)\n\t\t(DELAY\n\t\t(ABSOLUTE\n" , fixed_name); - - pin_count = pb->pb_graph_node->output_pins[0][0].pin_count_in_cluster; // an output pin of the RAM - assert(pb->rr_graph[pin_count].tnode); - internal_delay = pb->rr_graph[pin_count].tnode->T_arr * 1.0E12 + 0.5; - del = (int)internal_delay; - - fprintf(SDF , "\t\t\t(IOPATH (posedge clock) out (%d:%d:%d)(%d:%d:%d))" , del , del , del , del , del , del); - - fprintf(SDF , "\t\t)\n\t\t)\n\t)\n"); - free(fixed_name); - -} - -void SDF_ram_dual_port_delay_printing(FILE *SDF , t_pb *pb) -{ - // int num_inputs; - char *fixed_name; - int pin_count; - float internal_delay; - int del; - - // num_inputs = pb->pb_graph_node->num_input_pins[0]; - fixed_name = fix_name(pb->name); - fprintf(SDF , "\t(CELL\n\t(CELLTYPE \"dual_port_ram\")\n\t(INSTANCE inst/%s)\n\t\t(DELAY\n\t\t(ABSOLUTE\n" , fixed_name); - - pin_count = pb->pb_graph_node->output_pins[0][0].pin_count_in_cluster; // an output pin of the RAM - assert(pb->rr_graph[pin_count].tnode); - internal_delay = pb->rr_graph[pin_count].tnode->T_arr * 1.0E12 + 0.5; - del = (int)internal_delay; - - fprintf(SDF , "\t\t\t(IOPATH (posedge clock) out1 (%d:%d:%d)(%d:%d:%d))" , del , del , del , del , del , del); - fprintf(SDF , "\t\t\t(IOPATH (posedge clock) out2 (%d:%d:%d)(%d:%d:%d))" , del , del , del , del , del , del); - - fprintf(SDF , "\t\t)\n\t\t)\n\t)\n"); - free(fixed_name); -} - -char *find_clock_name(void) -{ - int j; - char *clock_in_the_design=NULL; - int clocks = 0; - for(j=0 ; j 1) { - printf("The post-layout netlist generator presently handles single-clock designs only. Your design contains %d clocks. \n" - "Future VTR releases may support post-layout netlist generation for multi-clock designs.\n", clocks); - exit(1); - } - return(clock_in_the_design); -} -/*The traverse_clb function returns a linked list of all the primitives inside a complex block. - - These primitives may be LUTs , FlipFlops , etc. - block_num: the block number for the complex block. - pb: The t_pb data structure corresponding to the complex block. (i.e block[block_num].pb) - prim_list: A pin_list pointer corresponding to the head of the linked list. The function will populate this head pointer.*/ - -pb_list *traverse_clb(t_pb *pb , pb_list *prim_list) -{ - int i,j; - const t_pb_type *pb_type; - if(pb == NULL || pb->name == NULL) { /*Reached a pb with no content*/ - return(prim_list); - } - - pb_type = pb->pb_graph_node->pb_type; - - if(pb->child_pbs == NULL) {/*reached a primitive*/ - prim_list = insert_to_linked_list(pb , prim_list); /*add the primitive to the linked list*/ - } - - if(pb_type->num_modes > 0) { /*Traversing through the children of the pb*/ - for(i = 0; i < pb_type->modes[pb->mode].num_pb_type_children; i++) { - for(j = 0; j < pb_type->modes[pb->mode].pb_type_children[i].num_pb; j++) { - prim_list = traverse_clb(&(pb->child_pbs[i][j]) , prim_list); - } - } - } - - return(prim_list); - -} - -/*The find_connected_primitives_downhill function will return a linked list of all the primitives that a particular primitive connects to. - - block_num: the block number of the complex block that the primitive resides in. - pb: A pointer to the t_pb data structure that represents the primitive (not the complex block). - list: A head pointer to the start of a linked list. This function will populate the linked list. The linked list can be empty (i.e list=NULL) - or contain other primitives.*/ - -conn_list *find_connected_primitives_downhill(int block_num , t_pb *pb , conn_list*list) -{ - int i,j,k,q,r; - int total_output_pins; - int pin_number , port_number_out=-1 , pin_number_out , starting_block , next_block , vpck_net , pin_count; - float delay , start_delay , end_delay; - - char *temp_port_name = (char *)malloc(1000 * sizeof(char)); - int total_output_ports = pb->pb_graph_node->num_output_ports; - int model_port_index; - - assert(temp_port_name); - - /*iterates through all output pins of the primitive "pb", and finds the other primitive and pin they connect to*/ - for(i=0 ; i < total_output_ports ; i++) - { - total_output_pins = pb->pb_graph_node->num_output_pins[i]; - for(j=0 ; j < total_output_pins ; j++) - { - - model_port_index = pb->pb_graph_node->output_pins[i][j].port->model_port->index; - - pin_number = pb->pb_graph_node->output_pins[i][j].pin_count_in_cluster; /*pin count of the output pin*/ - starting_block = pb->logical_block; /*logical block index for the source primitive*/ - - vpck_net = logical_block[starting_block].output_nets[model_port_index][j]; /*The index for the vpack_net struct corresponding to this source to sink(s) connections*/ - - if (pb->rr_graph[pin_number].net_num != OPEN) /* If this output pin is used*/ - { /*Then we will use the logical_block netlist method for finding the connectivity and timing information*/ - if(vpck_net != OPEN) - { - - for(k=1 ; kport->index; - - // because of possible pin swaps, we need to find the physical on load block that - // has the correct attached net - for (q = 0; q < logical_block[next_block].pb->pb_graph_node->num_input_pins[port_number_out]; q++) - { - int physical_pin_pos = logical_block[next_block].pb->pb_graph_node->input_pins[port_number_out][q].pin_count_in_cluster; - if (logical_block[next_block].pb->rr_graph[physical_pin_pos].net_num == vpck_net) - break; - } - - assert(q != logical_block[next_block].pb->pb_graph_node->num_input_pins[port_number_out]); - - pin_number_out = q; -#endif - - port_number_out = pin_number_out = -1; - - for (r = 0; r < logical_block[next_block].pb->pb_graph_node->num_input_ports; r++) { - for (q = 0; q < logical_block[next_block].pb->pb_graph_node->num_input_pins[r]; q++) { - int physical_pin_pos = logical_block[next_block].pb->pb_graph_node->input_pins[r][q].pin_count_in_cluster; - if (logical_block[next_block].pb->rr_graph[physical_pin_pos].net_num == vpck_net) { - port_number_out = r; - pin_number_out = q; - r = logical_block[next_block].pb->pb_graph_node->num_input_ports; - break; - } - } - } - - assert(port_number_out != -1); - assert(pin_number_out != -1); - - int unswapped_pin_number = vpack_net[vpck_net].node_block_pin[k]; - - pin_count = logical_block[next_block].pb->pb_graph_node->input_pins[port_number_out][pin_number_out].pin_count_in_cluster;/*pin count for the sink pin*/ - assert(logical_block[next_block].pb->rr_graph[pin_count].tnode); - - start_delay = pb->rr_graph[pin_number].tnode->T_arr; /*The arrival time of the source pin*/ - end_delay = logical_block[next_block].pb->rr_graph[pin_count].tnode->T_arr;/*The arrival time of the sink pin*/ - delay = end_delay - start_delay; /*The difference of start and end arrival times is the delay for going from the source to sink pin*/ - list=insert_to_linked_list_conn(pb , logical_block[next_block].pb , - &pb->pb_graph_node->output_pins[i][j] , - &logical_block[next_block].pb->pb_graph_node->input_pins[port_number_out][unswapped_pin_number] , - delay , list);/*Insert this sink primitive in the linked list pointer to by "list"*/ - - } - } - } - } - } - free(temp_port_name); - return(list); -} - -pb_list *insert_to_linked_list(t_pb *pb_new , pb_list *list) -{ - pb_list *new_list = (pb_list *)malloc(1 * sizeof(pb_list)); - assert(new_list); - new_list->pb = pb_new; - new_list->next = list; - list = new_list; - return(list); -} - -conn_list *insert_to_linked_list_conn(t_pb *driver_new , t_pb *load_new , t_pb_graph_pin *driver_pin_ , t_pb_graph_pin *load_pin_ , float path_delay , conn_list *list) -{ - conn_list *new_list = (conn_list *)malloc(1 * sizeof(conn_list)); - assert(new_list); - new_list->driver_pb = driver_new; - new_list->load_pb = load_new; - new_list->driver_pin = driver_pin_; - new_list->load_pin = load_pin_; - new_list->driver_to_load_delay = path_delay; - new_list->next = list; - list = new_list; - return(list); -} - -/*traverse_linked_list_conn can be used to print out the found connections of a primitive to the screen */ -void traverse_linked_list_conn(conn_list *list) -{ - conn_list *current; - - for(current=list ; current != NULL ; current=current->next) - { - printf(" driver=> type: %s , name: %s , output: [%d][%d] , load=> type: %s , name: %s input: [%d][%d]\npath delay: %e\n\n",current->driver_pb->pb_graph_node->pb_type->name , - current->driver_pb->name, - current->driver_pin->port->index , current->driver_pin->pin_number , - current->load_pb->pb_graph_node->pb_type->name, - current->load_pb->name, - current->load_pin->port->index , current->load_pin->pin_number, - current->driver_to_load_delay ); - } -} - -/*traverse_linked_list can be used to print out the primitives of a clb to the screen */ -void traverse_linked_list(pb_list *list) -{ - pb_list *current; - - for(current=list ; current!=NULL ; current=current->next) - { - printf("type: %s , name: %s \n", logical_block[current->pb->logical_block].model->name , current->pb->name); - } -} - -pb_list *free_linked_list(pb_list *list) -{ - pb_list *current; - pb_list *temp_free; - - current=list; - while(current!=NULL) - { - temp_free=current; - current=current->next; - free(temp_free); - } - list = NULL; - return(list); -} - -conn_list *free_linked_list_conn(conn_list *list) -{ - conn_list *current; - conn_list *temp_free; - - current=list; - while(current!=NULL) - { - temp_free=current; - current=current->next; - free(temp_free); - } - list = NULL; - return(list); -} - diff --git a/vpr7_x2p/vpr/SRC/base/verilog_writer.h b/vpr7_x2p/vpr/SRC/base/verilog_writer.h deleted file mode 100644 index e1bd38c3d..000000000 --- a/vpr7_x2p/vpr/SRC/base/verilog_writer.h +++ /dev/null @@ -1,182 +0,0 @@ -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "vpr_utils.h" -#include "globals.h" -#include "read_place.h" -#include "draw.h" -#include "stats.h" -#include "check_route.h" -#include "rr_graph.h" -#include "path_delay.h" -#include "net_delay.h" -#include "timing_place.h" -#include "read_xml_arch_file.h" -#include "ReadOptions.h" -#include "physical_types.h" -#include "globals.h" -#include "string.h" -#include "stdlib.h" -#include "math.h" - -/* -verilog_writer.c defines the main functions used to: - - 1) identify the primitives in a design - 2) find the connectivity between primitives - 3) Write the verilog code representing the post-synthesized (packed,placed,routed) design consisting of LUTs, IOs, Flip Flops, Multiplier blocks, and RAM blocks - 4) Write the Standard Delay Format(SDF) file corresponding to the verilog code mentioned in (3). The SDF file contains all the timing information of the design which - allows the user to perform timing simulation -*/ - - - - -/* *************************************************************************************************************** - The pb_list data structure is used in a linked list by the function traverse_clb that will find primitives. - This data structure represents a single primitive. - - pb: A pointer to the t_pb data structure representing the primitive. - pb_graph: A pointer to the t_pb_graph_node representing the primitive. - driver_pin: (Only applicable to "find_connected_primitives_downhill" & "find_connected_primitives_uphill") - A pointer to the t_pb_graph_pin data structure corresponding to the pin that drives the signal on the load_pin of this pb primitive. - The port index and pin number for the pin is accessible through this data structure. - load_pin: (Only applicable to "find_connected_primitives_downhill" & "find_connected_primitives_uphill") - A pointer to the t_pb_graph_pin data structure corresponding to the input pin that receives the signal from the driver_pin. - The port index and pin number for the pin is accessible through this data structure. - next: pointer to the next pb primitive found in the linked list*/ -typedef struct found_pins{ - - t_pb *pb; - - struct found_pins *next; - -}pb_list; - - -/* *************************************************************************************************************** - The conn_list data structure is used in a linked list by functions that will be used by functions that will find the connectivity between primitives. - This data structure represents a single driver to load pair of primitives. - - driver_pb: A pointer to the t_pb data structure representing the driver primitive. - load_pb: A pointer to the t_pb data structure representing the load primitive. - driver_pin: A pointer to the t_pb_graph_pin data structure corresponding to the pin that drives the signal on the load_pin of this pb primitive. - The port index and pin number for the pin is accessible through this data structure. - load_pin: A pointer to the t_pb_graph_pin data structure corresponding to the input pin that receives the signal from the driver_pin. - The port index and pin number for the pin is accessible through this data structure. - driver_to_load_delay: The delay, in seconds, for a signal to propagate from the driver pin to the load pin. - next: pointer to the next driver-load pair found. -*/ -typedef struct found_connectivity{ - - t_pb *driver_pb; - t_pb *load_pb; - - t_pb_graph_pin *driver_pin; - t_pb_graph_pin *load_pin; - - float driver_to_load_delay; - - struct found_connectivity *next; - -}conn_list; - - -/*The verilog_writer function is the main function that will generate and write to the verilog and SDF files - Al the functions declared bellow are called directly or indirectly by verilog_writer.c - net_delay is a float 2D array containing the inter clb delay information.*/ -void verilog_writer(void); - -/*The traverse_clb function returns a linked list of all the primitives inside a complex block. - These primitives may be LUTs , FlipFlops , etc. - block_num: the block number for the complex block. - pb: The t_pb data structure corresponding to the complex block. (i.e block[block_num].pb) - prim_list: A pin_list pointer corresponding to the head of the linked list. The function will populate this head pointer.*/ -pb_list *traverse_clb(t_pb *pb, pb_list *prim_list); - - -/*The find_connected_primitives_downhill function will return a linked list of all the primitives that a particular primitive connects to. - block_num: the block number of the complex block that the primitive resides in. - pb: A pointer to the t_pb data structure that represents the primitive (not the complex block). - list: A head pointer to the start of a linked list. This function will populate the linked list. The linked list can be empty (i.e list=NULL) - or contain other primitives.*/ -conn_list *find_connected_primitives_downhill(int block_num , t_pb *pb , conn_list *list); - -/*The function insert_to_linked_list inserts a new primitive to the pb_list type linked list pointed by "list".*/ -pb_list *insert_to_linked_list(t_pb *pb_new , pb_list *list); - -/*The function insert_to_linked_list_conn inserts a new primitive to the conn_list type linked list pointed by "list".*/ -conn_list *insert_to_linked_list_conn(t_pb *driver_new , t_pb *load_new , t_pb_graph_pin *driver_pin_ , t_pb_graph_pin *load_pin_ , float path_delay , conn_list *list); - -/*The traverse_linked_list function prints the entire pb_list type linked list pointed to by "list"*/ -void traverse_linked_list(pb_list *list); - -/*The traverse_linked_list_conn function prints the entire conn_list type linked list pointed to by "list"*/ -void traverse_linked_list_conn(conn_list *list); - -/*The free_linked_list function frees the memory used by the pb_list type linked list pointed to by "list"*/ -pb_list *free_linked_list(pb_list *list); - -/*The free_linked_list_conn function frees the memory used by the conn_list type linked list pointed to by "list"*/ -conn_list *free_linked_list_conn(conn_list *list); - -/*The function instantiate_top_level_module instantiates the top level verilog module of the post-synthesized circuit and the list of inputs and outputs to that module*/ -void instantiate_top_level_module(FILE *Verilog); - -/*The instantiate_wires function instantiates all the wire in the post-synthesized design*/ -void instantiate_wires(FILE *Verilog); - -/*The function instantiate_input_interconnect will instantiate the interconnect segments from input pins to the rest of the design*/ -void instantiate_input_interconnect(FILE *Verilog , FILE *SDF , char *clock_name); - -/*This function instantiates the interconnect modules that connect from the output pins of the primitive "pb" to whatever it connects to*/ -void instantiate_interconnect(FILE *Verilog , int block_num , t_pb *pb , FILE *SDF); - -/*This function instantiates the primitive verilog modules e.g. LUTs ,Flip Flops, etc.*/ -void instantiate_primitive_modules(FILE *Verilog , char *clock_name , FILE *SDF); - -/*This function returns the truth table corresponding to the LUT primitive represented by "pb"*/ -char *load_truth_table(int inputs , t_pb *pb); - -/*The names of some primitives contain certain characters that would cause syntax errors in Verilog (e.g. '^' , '~' , '[' , etc. ). This function returns a new string - with those illegal characters removed and replaced with '_'*/ -char *fix_name(char *name); - -/*This function finds the number of inputs to a primitive.*/ -int find_number_of_inputs(t_pb *pb); - -/*This function is a utility function used by load_truth_table and load_truth_table_new functions. It will return the index of a particular row in the truth table*/ -int find_index(char *row,int inputs); - -/*This function is a utility function called by intantiate_interconnect*/ -void interconnect_printing(FILE *fp , conn_list *downhill); - -/*This function will instantiate the header of te Standar Delay Format (SDF) file.*/ -void instantiate_SDF_header(FILE *SDF); - -/*This funciton will instantiate the SDF cell that contains the delay information of the Verilog interconnect modules*/ -void SDF_interconnect_delay_printing(FILE *SDF , conn_list *downhill); - -/*This function instantiates the SDF cell that contains the delay information of a LUT*/ -void sdf_LUT_delay_printing(FILE *SDF , t_pb *pb); - -/*This function instantiates the SdF cell that contains the delay information of a Flip Flop*/ -void sdf_DFF_delay_printing(FILE *SDF , t_pb *pb); - -/*This function instantiates the SdF cell that contains the delay information of a Multiplier*/ -void SDF_Mult_delay_printing(FILE *SDF , t_pb *pb); - -/*This function instantiates the SdF cell that contains the delay information of a Adder*/ -void SDF_Adder_delay_printing(FILE *SDF , t_pb *pb); - -/*Finds and returns the name of the clock signal int he circuit*/ -char *find_clock_name(void); - -/*This function instantiates the SdF cell that contains the delay information of a Single_port_RAM*/ -void SDF_ram_single_port_delay_printing(FILE *SDF , t_pb *pb); - -/*This function instantiates the SdF cell that contains the delay information of a Dual_port_RAM*/ -void SDF_ram_dual_port_delay_printing(FILE *SDF , t_pb *pb); diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c deleted file mode 100644 index 6566921e3..000000000 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ /dev/null @@ -1,1616 +0,0 @@ -/** - General API for VPR - Other software tools should generally call just the functions defined here - For advanced/power users, you can call functions defined elsewhere in VPR or modify the data structures directly at your discretion but be aware that doing so can break the correctness of VPR - - Author: Jason Luu - June 21, 2012 - */ - -#include -#include -#include -#include - -#include "util.h" -#include "vpr_types.h" -#include "vpr_utils.h" -#include "globals.h" -#include "graphics.h" -#include "read_netlist.h" -#include "check_netlist.h" -#include "print_netlist.h" -#include "read_blif.h" -#include "draw.h" -#include "place_and_route.h" -#include "pack.h" -#include "SetupGrid.h" -#include "stats.h" -#include "path_delay.h" -#include "OptionTokens.h" -#include "ReadOptions.h" -#include "read_xml_arch_file.h" -#include "SetupVPR.h" -#include "rr_graph.h" -#include "pb_type_graph.h" -#include "ReadOptions.h" -#include "route_common.h" -#include "timing_place_lookup.h" -#include "cluster_legality.h" -#include "route_export.h" -#include "vpr_api.h" -#include "read_sdc.h" -#include "power.h" - -/* Xifan TANG: Add place_macro.h */ -#include "place_macro.h" - -/* Local subroutines */ -static void free_pb_type(t_pb_type *pb_type); -static void free_complex_block_types(void); - -static void free_arch(t_arch* Arch); -static void free_options(t_options *options); -static void free_circuit(void); - -static boolean has_printhandler_pre_vpr = FALSE; - -/* For resync of clustered netlist to the post-route solution. This function adds local nets to cluster */ -static void reload_intra_cluster_nets(t_pb *pb); -static t_trace *alloc_and_load_final_routing_trace(); -static t_trace *expand_routing_trace(t_trace *trace, int ivpack_net); -static void print_complete_net_trace(t_trace* trace, const char *file_name); -static void resync_post_route_netlist(); -static void clay_logical_equivalence_handling(const t_arch *arch); -static void clay_lut_input_rebalancing(int iblock, t_pb *pb); -static void clay_reload_ble_locations(int iblock); -static void resync_pb_graph_nodes_in_pb(t_pb_graph_node *pb_graph_node, - t_pb *pb); - -/* Local subroutines end */ - -/* Display general VPR information */ -void vpr_print_title(void) { - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "VPR FPGA Placement and Routing.\n"); - vpr_printf(TIO_MESSAGE_INFO, "Version: Version " VPR_VERSION "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Compiled: " __DATE__ ".\n"); - vpr_printf(TIO_MESSAGE_INFO, "University of Toronto\n"); - vpr_printf(TIO_MESSAGE_INFO, "vpr@eecg.utoronto.ca\n"); - vpr_printf(TIO_MESSAGE_INFO, "Enhancements: mrFPGA, RRAM, SWSEG, FPGA-SPICE by Xifan TANG, EPFL-LSI, Univ. of Utah-LNIS \n"); - vpr_printf(TIO_MESSAGE_INFO, "Enhancements: Synthesizable Verilog Support by Xifan TANG, EPFL-LSI, Univ. of Utah-LNIS\n"); - vpr_printf(TIO_MESSAGE_INFO, "Enhancements: Bitstream Generator Support by Xifan TANG, EPFL-LSI, Univ. of Utah-LNIS\n"); - vpr_printf(TIO_MESSAGE_INFO, "Enhancements: OPIN_TO_CB, CLB_PIN_REMAP by Xifan TANG, EPFL-LSI, Univ. of Utah-LNIS\n"); - vpr_printf(TIO_MESSAGE_INFO, "xifan.tang@utah.edu\n"); - vpr_printf(TIO_MESSAGE_INFO, "This is free open source code under MIT license.\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); -} - -/* Display help screen */ -void vpr_print_usage(void) { - vpr_printf(TIO_MESSAGE_INFO, - "Usage: vpr fpga_architecture.xml circuit_name [Options ...]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, - "General Options: [--nodisp] [--auto ] [--pack]\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--place] [--route] [--timing_analyze_only_with_net_delay ]\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--fast] [--full_stats] [--timing_analysis on | off] [--outfile_prefix ]\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--blif_file ][--net_file ][--place_file ]\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--route_file ][--sdc_file ][--echo_file on | off]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Packer Options:\n"); - /* vpr_printf(TIO_MESSAGE_INFO, "\t[-global_clocks on|off]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[-hill_climbing on|off]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[-sweep_hanging_nets_and_inputs on|off]\n"); */ - vpr_printf(TIO_MESSAGE_INFO, "\t[--timing_driven_clustering on|off]\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--cluster_seed_type timing|max_inputs] [--alpha_clustering ] [--beta_clustering ]\n"); - /* vpr_printf(TIO_MESSAGE_INFO, "\t[-recompute_timing_after ] [-cluster_block_delay ]\n"); */ - vpr_printf(TIO_MESSAGE_INFO, "\t[--allow_unrelated_clustering on|off]\n"); - /* vpr_printf(TIO_MESSAGE_INFO, "\t[-allow_early_exit on|off]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[-intra_cluster_net_delay ] \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[-inter_cluster_net_delay ] \n"); */ - vpr_printf(TIO_MESSAGE_INFO, - "\t[--connection_driven_clustering on|off] \n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Placer Options:\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--place_algorithm bounding_box | net_timing_driven | path_timing_driven]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--init_t ] [--exit_t ]\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--alpha_t ] [--inner_num ] [--seed ]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--place_cost_exp ]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--place_chan_width ] \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--fix_pins random | ]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--enable_timing_computations on | off]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--block_dist ]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--place_clb_pin_remap]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, - "Placement Options Valid Only for Timing-Driven Placement:\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--timing_tradeoff ]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--recompute_crit_iter ]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--inner_loop_recompute_divider ]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--td_place_exp_first ]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--td_place_exp_last ]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, - "Router Options: [-max_router_iterations ] [-bb_factor ]\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--initial_pres_fac ] [--pres_fac_mult ]\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--acc_fac ] [--first_iter_pres_fac ]\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--bend_cost ] [--route_type global | detailed]\n"); - /* Xifan Tang: Tileable routing support !!! */ - vpr_printf(TIO_MESSAGE_INFO, - "\t[--use_tileable_route_chan_width ]\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--verify_binary_search] [--route_chan_width ]\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--router_algorithm breadth_first | timing_driven]\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--base_cost_type intrinsic_delay | delay_normalized | demand_only]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, - "Routing options valid only for timing-driven routing:\n"); - vpr_printf(TIO_MESSAGE_INFO, - "\t[--astar_fac ] [--max_criticality ]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t[--criticality_exp ]\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Power Options:\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--power\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--power_output_file \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--activity_file \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--tech_properties \n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - /* Xifan TANG: FPGA-SPICE Support*/ - vpr_printf(TIO_MESSAGE_INFO, "FPGA-X2P (from XML to Product/Prototype) tool suite Options:\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_rename_illegal_port\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_signal_density_weight \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_sim_window_size \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_compact_routing_hierarchy\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_output_sb_xml \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_duplicate_grid_pin\n"); - vpr_printf(TIO_MESSAGE_INFO, "SPICE Support Options:\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_dir \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_print_top_testbench\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_print_lut_testbench\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_print_hardlogic_testbench\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_print_io_testbench\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_print_pb_mux_testbench\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_print_cb_mux_testbench\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_print_sb_mux_testbench\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_print_cb_testbench\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_print_sb_testbench\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_print_grid_testbench\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_leakage_only\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_parasitic_net_estimation \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_testbench_load_extraction \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_sim_mt_num \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_simulator_path \n"); - /* Xifan TANG: Synthesizable Verilog Dump*/ - vpr_printf(TIO_MESSAGE_INFO, "Synthesizable Verilog Generator Options:\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_dir \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_explicit_mapping\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_top_testbench\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_autocheck_top_testbench \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_input_blif_testbench\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_formal_verification_top_netlist\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_include_timing\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_include_signal_init\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_include_icarus_simulator\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_modelsim_autodeck \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_user_defined_template\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_report_timing_tcl\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_report_timing_rpt_path \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_pnr\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_analysis\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_simulation_ini\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_simulation_ini_file \n"); - /* Xifan Tang: Bitstream generator */ - vpr_printf(TIO_MESSAGE_INFO, "Bitstream Generator Options:\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator\n"); -// vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_output_file \n"); // AA: temporarily deprecated -} - -void vpr_init_file_handler() { - char* pszLogFileName = "vpr_stdout.log"; - unsigned char enableTimeStamps = 1; - unsigned long maxWarningCount = 100000; - unsigned long maxErrorCount = 1000; - - if (PrintHandlerExists() == 1) { - has_printhandler_pre_vpr = TRUE; - } else { - has_printhandler_pre_vpr = FALSE; - } - if (has_printhandler_pre_vpr == FALSE) { - PrintHandlerNew(pszLogFileName); - PrintHandlerInit(enableTimeStamps, maxWarningCount, maxErrorCount); - } - return; -} - -/* Initialize VPR - 1. Read Options - 2. Read Arch - 3. Read Circuit - 4. Sanity check all three - */ -void vpr_init(INP int argc, INP char **argv, OUTP t_options *options, - OUTP t_vpr_setup *vpr_setup, OUTP t_arch *arch) { - - /* Initialize file handler */ - vpr_init_file_handler(); - - /* Print title message */ - vpr_print_title(); - - /* Print usage message if no args */ - if (argc < 3) { - vpr_print_usage(); - exit(1); - } - - memset(options, 0, sizeof(t_options)); - memset(vpr_setup, 0, sizeof(t_vpr_setup)); - memset(arch, 0, sizeof(t_arch)); - - /* Read in user options */ - ReadOptions(argc, argv, options); - /* Timing option priorities */ - vpr_setup->TimingEnabled = IsTimingEnabled(options); - /* Determine whether echo is on or off */ - setEchoEnabled(IsEchoEnabled(options)); - SetPostSynthesisOption(IsPostSynthesisEnabled(options)); - vpr_setup->constant_net_delay = options->constant_net_delay; - - /* Read in arch and circuit */ - SetupVPR(options, vpr_setup->TimingEnabled, TRUE, &vpr_setup->FileNameOpts, - arch, &vpr_setup->Operation, &vpr_setup->user_models, - &vpr_setup->library_models, &vpr_setup->PackerOpts, - &vpr_setup->PlacerOpts, &vpr_setup->AnnealSched, - &vpr_setup->RouterOpts, &vpr_setup->RoutingArch, - &vpr_setup->Segments, &vpr_setup->Timing, &vpr_setup->ShowGraphics, - &vpr_setup->GraphPause, &vpr_setup->PowerOpts, - /*Xifan TANG: Switch Segment Pattern Support*/ - &vpr_setup->swseg_patterns, &vpr_setup->FPGA_SPICE_Opts); - - /* Check inputs are reasonable */ - CheckOptions(*options, vpr_setup->TimingEnabled); - CheckArch(*arch, vpr_setup->TimingEnabled); - - /* Verify settings don't conflict or otherwise not make sense */ - CheckSetup(vpr_setup->Operation, vpr_setup->PlacerOpts, - vpr_setup->AnnealSched, vpr_setup->RouterOpts, - vpr_setup->RoutingArch, vpr_setup->Segments, vpr_setup->Timing, - arch->Chans); - - /* flush any messages to user still in stdout that hasn't gotten displayed */ - fflush(stdout); - - /* Read blif file and sweep unused components */ - read_and_process_blif(vpr_setup->PackerOpts.blif_file_name, - vpr_setup->PackerOpts.sweep_hanging_nets_and_inputs, - vpr_setup->user_models, vpr_setup->library_models, - /* Xifan TANG: we need activity in spice modeling */ - (boolean)(vpr_setup->PowerOpts.do_power - | vpr_setup->FPGA_SPICE_Opts.read_act_file), - vpr_setup->FileNameOpts.ActFile); - fflush(stdout); - - ShowSetup(*options, *vpr_setup); -} - -/* - * Sets globals: nx, ny - * Allocs globals: chan_width_x, chan_width_y, grid - * Depends on num_clbs, pins_per_clb */ -void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) { - int *num_instances_type, *num_blocks_type; - int i; - int current, high, low; - boolean fit; - - /* Xifan TANG: consider marco length in fitting */ - int imacro, max_len_chain_blocks; - int num_pl_macros; - t_pl_macro* pl_macros; - - /* Read in netlist file for placement and routing */ - if (vpr_setup.FileNameOpts.NetFile) { - read_netlist(vpr_setup.FileNameOpts.NetFile, &Arch, &num_blocks, &block, - &num_nets, &clb_net); - /* This is done so that all blocks have subblocks and can be treated the same */ - check_netlist(); - } - - /* Output the current settings to console. */ - printClusteredNetlistStats(); - - if (vpr_setup.Operation == TIMING_ANALYSIS_ONLY) { - do_constant_net_delay_timing_analysis(vpr_setup.Timing, - vpr_setup.constant_net_delay); - } else { - current = nint((float)sqrt((float)num_blocks)); /* current is the value of the smaller side of the FPGA */ - low = 1; - high = -1; - - num_instances_type = (int*) my_calloc(num_types, sizeof(int)); - num_blocks_type = (int*) my_calloc(num_types, sizeof(int)); - - for (i = 0; i < num_blocks; i++) { - num_blocks_type[block[i].type->index]++; - } - - if (Arch.clb_grid.IsAuto) { - /* Auto-size FPGA, perform a binary search */ - while (high == -1 || low < high) { - /* Generate grid */ - if (Arch.clb_grid.Aspect >= 1.0) { - ny = current; - nx = nint(current * Arch.clb_grid.Aspect); - } else { - nx = current; - ny = nint(current / Arch.clb_grid.Aspect); - } -#if DEBUG - vpr_printf(TIO_MESSAGE_INFO, - "Auto-sizing FPGA at x = %d y = %d\n", nx, ny); -#endif - alloc_and_load_grid(num_instances_type); - freeGrid(); - - /* Xifan TANG: We need consider the length of carry-chain CLBs into account! */ - num_pl_macros = alloc_and_load_placement_macros(Arch.Directs, Arch.num_directs, &pl_macros); - /* find length of longest carry-chain logic blocks */ - max_len_chain_blocks = max_len_pl_macros(num_pl_macros, pl_macros); - /* Free all the allocated structs */ - free_placement_macros_structs(); - for (imacro = 0; imacro < num_pl_macros; imacro ++) { - free(pl_macros[imacro].members); - } - free(pl_macros); - - /* Test if netlist fits in grid */ - fit = TRUE; - for (i = 0; i < num_types; i++) { - if (num_blocks_type[i] > num_instances_type[i]) { - fit = FALSE; - break; - } - } - /* If the length of macros is longer than ny - 2, fitting should fail. - * Note: carry-chain logic blocks are placed only vertically in FPGA. - */ - if ((TRUE == fit)&&(max_len_chain_blocks > (ny))) { - fit = FALSE; - vpr_printf(TIO_MESSAGE_INFO, "Carry-chain logic blocks length (%d) is larger than y (%d)!\n", - max_len_chain_blocks, ny); - } - - /* get next value */ - if (!fit) { - /* increase size of max */ - if (high == -1) { - current = current * 2; - if (current > MAX_SHORT) { - vpr_printf(TIO_MESSAGE_ERROR, - "FPGA required is too large for current architecture settings.\n"); - exit(1); - } - } else { - if (low == current) - current++; - low = current; - current = low + ((high - low) / 2); - } - } else { - high = current; - current = low + ((high - low) / 2); - } - } - /* Generate grid */ - if (Arch.clb_grid.Aspect >= 1.0) { - ny = current; - nx = nint(current * Arch.clb_grid.Aspect); - } else { - nx = current; - ny = nint(current / Arch.clb_grid.Aspect); - } - alloc_and_load_grid(num_instances_type); - vpr_printf(TIO_MESSAGE_INFO, "FPGA auto-sized to x = %d y = %d\n", - nx, ny); - } else { - nx = Arch.clb_grid.W; - ny = Arch.clb_grid.H; - alloc_and_load_grid(num_instances_type); - } - - vpr_printf(TIO_MESSAGE_INFO, - "The circuit will be mapped into a %d x %d array of clbs.\n", - nx, ny); - - /* Xifan TANG: We need consider the length of carry-chain CLBs into account! */ - num_pl_macros = alloc_and_load_placement_macros(Arch.Directs, Arch.num_directs, &pl_macros); - /* find length of longest carry-chain logic blocks */ - max_len_chain_blocks = max_len_pl_macros(num_pl_macros, pl_macros); - /* Free all the allocated structs */ - free_placement_macros_structs(); - for (imacro = 0; imacro < num_pl_macros; imacro ++) { - free(pl_macros[imacro].members); - } - free(pl_macros); - - /* Test if netlist fits in grid */ - fit = TRUE; - for (i = 0; i < num_types; i++) { - if (num_blocks_type[i] > num_instances_type[i]) { - fit = FALSE; - break; - } - } - - /* If the length of macros is longer than ny - 2, fitting should fail. - * Note: carry-chain logic blocks are placed only vertically in FPGA. - */ - if ((TRUE == fit)&&(max_len_chain_blocks > (ny))) { - fit = FALSE; - vpr_printf(TIO_MESSAGE_INFO, "Carry-chain logic blocks length (%d) is larger than y (%d) !\n", - max_len_chain_blocks, ny); - } - - if (!fit) { - vpr_printf(TIO_MESSAGE_ERROR, - "Not enough physical locations for type %s, number of blocks is %d but number of locations is %d.\n", - type_descriptors[i].name, num_blocks_type[i], - num_instances_type[i]); - exit(1); - } - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Resource usage...\n"); - for (i = 0; i < num_types; i++) { - vpr_printf(TIO_MESSAGE_INFO, - "\tNetlist %d\tblocks of type: %s\n", - num_blocks_type[i], type_descriptors[i].name); - vpr_printf(TIO_MESSAGE_INFO, - "\tArchitecture %d\tblocks of type: %s\n", - num_instances_type[i], type_descriptors[i].name); - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - chan_width_x = (int *) my_malloc((ny + 1) * sizeof(int)); - chan_width_y = (int *) my_malloc((nx + 1) * sizeof(int)); - - free(num_blocks_type); - free(num_instances_type); - } -} - -void vpr_pack(INP t_vpr_setup vpr_setup, INP t_arch arch) { - clock_t begin, end; - float inter_cluster_delay = UNDEFINED, Tdel_opin_switch, Tdel_wire_switch, - Tdel_wtoi_switch, R_opin_switch, R_wire_switch, R_wtoi_switch, - Cout_opin_switch, Cout_wire_switch, Cout_wtoi_switch, - opin_switch_del, wire_switch_del, wtoi_switch_del, Rmetal, Cmetal, - first_wire_seg_delay, second_wire_seg_delay; - begin = clock(); - vpr_printf(TIO_MESSAGE_INFO, "Initialize packing.\n"); - - /* If needed, estimate inter-cluster delay. Assume the average routing hop goes out of - a block through an opin switch to a length-4 wire, then through a wire switch to another - length-4 wire, then through a wire-to-ipin-switch into another block. */ - - if (vpr_setup.PackerOpts.timing_driven - && vpr_setup.PackerOpts.auto_compute_inter_cluster_net_delay) { - opin_switch_del = get_switch_info(arch.Segments[0].opin_switch, - Tdel_opin_switch, R_opin_switch, Cout_opin_switch); - wire_switch_del = get_switch_info(arch.Segments[0].wire_switch, - Tdel_wire_switch, R_wire_switch, Cout_wire_switch); - wtoi_switch_del = get_switch_info( - vpr_setup.RoutingArch.wire_to_ipin_switch, Tdel_wtoi_switch, - R_wtoi_switch, Cout_wtoi_switch); /* wire-to-ipin switch */ - Rmetal = arch.Segments[0].Rmetal; - Cmetal = arch.Segments[0].Cmetal; - - /* The delay of a wire with its driving switch is the switch delay plus the - product of the equivalent resistance and capacitance experienced by the wire. */ - -#define WIRE_SEGMENT_LENGTH 4 - first_wire_seg_delay = opin_switch_del - + (R_opin_switch + Rmetal * WIRE_SEGMENT_LENGTH / 2) - * (Cout_opin_switch + Cmetal * WIRE_SEGMENT_LENGTH); - second_wire_seg_delay = wire_switch_del - + (R_wire_switch + Rmetal * WIRE_SEGMENT_LENGTH / 2) - * (Cout_wire_switch + Cmetal * WIRE_SEGMENT_LENGTH); - inter_cluster_delay = 4 - * (first_wire_seg_delay + second_wire_seg_delay - + wtoi_switch_del); /* multiply by 4 to get a more conservative estimate */ - } - - try_pack(&vpr_setup.PackerOpts, &arch, vpr_setup.user_models, - vpr_setup.library_models, vpr_setup.Timing, inter_cluster_delay); - end = clock(); -#ifdef CLOCKS_PER_SEC - vpr_printf(TIO_MESSAGE_INFO, "Packing took %g seconds.\n", - (float) (end - begin) / CLOCKS_PER_SEC); - vpr_printf(TIO_MESSAGE_INFO, "Packing completed.\n"); -#else - vpr_printf(TIO_MESSAGE_INFO, "Packing took %g seconds.\n", (float)(end - begin) / CLK_PER_SEC); -#endif - /* Xifan TANG: print the run time of packing placement */ - vpr_printf(TIO_MESSAGE_INFO, "Packing routing took %g seconds.\n", pack_route_time); - fflush(stdout); -} - -void vpr_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch arch) { - /* Startup X graphics */ - set_graphics_state(vpr_setup.ShowGraphics, vpr_setup.GraphPause, - vpr_setup.RouterOpts.route_type); - if (vpr_setup.ShowGraphics) { - init_graphics("VPR: Versatile Place and Route for FPGAs", WHITE); - alloc_draw_structs(); - } - - /* Do placement and routing */ - place_and_route(vpr_setup.Operation, vpr_setup.PlacerOpts, - vpr_setup.FileNameOpts.PlaceFile, vpr_setup.FileNameOpts.NetFile, - vpr_setup.FileNameOpts.ArchFile, vpr_setup.FileNameOpts.RouteFile, - vpr_setup.AnnealSched, vpr_setup.RouterOpts, vpr_setup.RoutingArch, - vpr_setup.Segments, vpr_setup.Timing, arch.Chans, arch.models, - arch.Directs, arch.num_directs, arch.sram_inf.area, - /*Xifan TANG: Switch Segment Pattern Support*/ - vpr_setup.swseg_patterns); - - fflush(stdout); - - /* Close down X Display */ - /* TODO: DANGEROUS way of coding, clean up */ - if (vpr_setup.ShowGraphics) - close_graphics(); - free_draw_structs(); -} - -/* Free architecture data structures */ -void free_arch(t_arch* Arch) { - int i; - t_model *model, *prev; - t_model_ports *port, *prev_port; - struct s_linked_vptr *vptr, *vptr_prev; - - freeGrid(); - free(chan_width_x); - chan_width_x = NULL; - free(chan_width_y); - chan_width_y = NULL; - - for (i = 0; i < Arch->num_switches; i++) { - if (Arch->Switches->name != NULL) { - free(Arch->Switches[i].name); - } - } - free(Arch->Switches); - free(switch_inf); - for (i = 0; i < Arch->num_segments; i++) { - if (Arch->Segments->cb != NULL) { - free(Arch->Segments[i].cb); - } - if (Arch->Segments->sb != NULL) { - free(Arch->Segments[i].sb); - } - } - free(Arch->Segments); - model = Arch->models; - while (model) { - port = model->inputs; - while (port) { - prev_port = port; - port = port->next; - free(prev_port->name); - free(prev_port); - } - port = model->outputs; - while (port) { - prev_port = port; - port = port->next; - free(prev_port->name); - free(prev_port); - } - vptr = model->pb_types; - while (vptr) { - vptr_prev = vptr; - vptr = vptr->next; - free(vptr_prev); - } - prev = model; - - model = model->next; - if (prev->instances) - free(prev->instances); - free(prev->name); - free(prev); - } - - for (i = 0; i < 4; i++) { - vptr = Arch->model_library[i].pb_types; - while (vptr) { - vptr_prev = vptr; - vptr = vptr->next; - free(vptr_prev); - } - } - - for (i = 0; i < Arch->num_directs; i++) { - free(Arch->Directs[i].name); - free(Arch->Directs[i].from_pin); - free(Arch->Directs[i].to_pin); - } - free(Arch->Directs); - - free(Arch->model_library[0].name); - free(Arch->model_library[0].outputs->name); - free(Arch->model_library[0].outputs); - free(Arch->model_library[1].inputs->name); - free(Arch->model_library[1].inputs); - free(Arch->model_library[1].name); - free(Arch->model_library[2].name); - free(Arch->model_library[2].inputs[0].name); - free(Arch->model_library[2].inputs[1].name); - free(Arch->model_library[2].inputs); - free(Arch->model_library[2].outputs->name); - free(Arch->model_library[2].outputs); - free(Arch->model_library[3].name); - free(Arch->model_library[3].inputs->name); - free(Arch->model_library[3].inputs); - free(Arch->model_library[3].outputs->name); - free(Arch->model_library[3].outputs); - free(Arch->model_library); - - if (Arch->clocks) { - free(Arch->clocks->clock_inf); - } - - free_complex_block_types(); - free_chunk_memory_trace(); -} - -void free_options(t_options *options) { - free(options->ArchFile); - free(options->CircuitName); - if (options->ActFile) - free(options->ActFile); - if (options->BlifFile) - free(options->BlifFile); - if (options->NetFile) - free(options->NetFile); - if (options->PlaceFile) - free(options->PlaceFile); - if (options->PowerFile) - free(options->PowerFile); - if (options->CmosTechFile) - free(options->CmosTechFile); - if (options->RouteFile) - free(options->RouteFile); - if (options->out_file_prefix) - free(options->out_file_prefix); - if (options->PinFile) - free(options->PinFile); -} - -static void free_complex_block_types(void) { - int i, j, k, m; - - free_all_pb_graph_nodes(); - - for (i = 0; i < num_types; i++) { - if (&type_descriptors[i] == EMPTY_TYPE) { - continue; - } - free(type_descriptors[i].name); - for (j = 0; j < type_descriptors[i].height; j++) { - for (k = 0; k < 4; k++) { - for (m = 0; - m < type_descriptors[i].num_pin_loc_assignments[j][k]; - m++) { - if (type_descriptors[i].pin_loc_assignments[j][k][m]) - free(type_descriptors[i].pin_loc_assignments[j][k][m]); - } - free(type_descriptors[i].pinloc[j][k]); - free(type_descriptors[i].pin_loc_assignments[j][k]); - } - free(type_descriptors[i].pinloc[j]); - free(type_descriptors[i].pin_loc_assignments[j]); - free(type_descriptors[i].num_pin_loc_assignments[j]); - } - for (j = 0; j < type_descriptors[i].num_class; j++) { - free(type_descriptors[i].class_inf[j].pinlist); - } - free(type_descriptors[i].pinloc); - free(type_descriptors[i].pin_loc_assignments); - free(type_descriptors[i].num_pin_loc_assignments); - free(type_descriptors[i].pin_height); - free(type_descriptors[i].class_inf); - free(type_descriptors[i].is_global_pin); - free(type_descriptors[i].pin_class); - free(type_descriptors[i].grid_loc_def); - free(type_descriptors[i].is_Fc_frac); - free(type_descriptors[i].is_Fc_full_flex); - free(type_descriptors[i].Fc); - free_pb_type(type_descriptors[i].pb_type); - free(type_descriptors[i].pb_type); - } - free(type_descriptors); -} - -static void free_pb_type(t_pb_type *pb_type) { - int i, j, k, m; - - free(pb_type->name); - if (pb_type->blif_model) - free(pb_type->blif_model); - - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - free_pb_type(&pb_type->modes[i].pb_type_children[j]); - } - free(pb_type->modes[i].pb_type_children); - free(pb_type->modes[i].name); - for (j = 0; j < pb_type->modes[i].num_interconnect; j++) { - free(pb_type->modes[i].interconnect[j].input_string); - free(pb_type->modes[i].interconnect[j].output_string); - free(pb_type->modes[i].interconnect[j].name); - - for (k = 0; k < pb_type->modes[i].interconnect[j].num_annotations; - k++) { - if (pb_type->modes[i].interconnect[j].annotations[k].clock) - free( - pb_type->modes[i].interconnect[j].annotations[k].clock); - if (pb_type->modes[i].interconnect[j].annotations[k].input_pins) { - free( - pb_type->modes[i].interconnect[j].annotations[k].input_pins); - } - if (pb_type->modes[i].interconnect[j].annotations[k].output_pins) { - free( - pb_type->modes[i].interconnect[j].annotations[k].output_pins); - } - for (m = 0; - m - < pb_type->modes[i].interconnect[j].annotations[k].num_value_prop_pairs; - m++) { - free( - pb_type->modes[i].interconnect[j].annotations[k].value[m]); - } - free(pb_type->modes[i].interconnect[j].annotations[k].prop); - free(pb_type->modes[i].interconnect[j].annotations[k].value); - } - free(pb_type->modes[i].interconnect[j].annotations); - if (pb_type->modes[i].interconnect[j].interconnect_power) - free(pb_type->modes[i].interconnect[j].interconnect_power); - } - if (pb_type->modes[i].interconnect) - free(pb_type->modes[i].interconnect); - if (pb_type->modes[i].mode_power) - free(pb_type->modes[i].mode_power); - } - if (pb_type->modes) - free(pb_type->modes); - - for (i = 0; i < pb_type->num_annotations; i++) { - for (j = 0; j < pb_type->annotations[i].num_value_prop_pairs; j++) { - free(pb_type->annotations[i].value[j]); - } - free(pb_type->annotations[i].value); - free(pb_type->annotations[i].prop); - if (pb_type->annotations[i].input_pins) { - free(pb_type->annotations[i].input_pins); - } - if (pb_type->annotations[i].output_pins) { - free(pb_type->annotations[i].output_pins); - } - if (pb_type->annotations[i].clock) { - free(pb_type->annotations[i].clock); - } - } - if (pb_type->num_annotations > 0) { - free(pb_type->annotations); - } - - if (pb_type->pb_type_power) { - free(pb_type->pb_type_power); - } - - for (i = 0; i < pb_type->num_ports; i++) { - free(pb_type->ports[i].name); - if (pb_type->ports[i].port_class) { - free(pb_type->ports[i].port_class); - } - if (pb_type->ports[i].port_power) { - free(pb_type->ports[i].port_power); - } - } - free(pb_type->ports); -} - -void free_circuit() { - int i; - struct s_linked_vptr *p_io_removed; - - /* Free netlist reference tables for nets */ - free(clb_to_vpack_net_mapping); - free(vpack_to_clb_net_mapping); - clb_to_vpack_net_mapping = NULL; - vpack_to_clb_net_mapping = NULL; - - /* Free logical blocks and nets */ - if (logical_block != NULL) { - free_logical_blocks(); - free_logical_nets(); - } - - if (clb_net != NULL) { - for (i = 0; i < num_nets; i++) { - free(clb_net[i].name); - free(clb_net[i].node_block); - free(clb_net[i].node_block_pin); - free(clb_net[i].node_block_port); - } - } - free(clb_net); - clb_net = NULL; - - if (block != NULL) { - for (i = 0; i < num_blocks; i++) { - if (block[i].pb != NULL) { - free_cb(block[i].pb); - free(block[i].pb); - } - free(block[i].nets); - free(block[i].name); - } - } - free(block); - block = NULL; - - free(blif_circuit_name); - free(default_output_name); - blif_circuit_name = NULL; - - p_io_removed = circuit_p_io_removed; - while (p_io_removed != NULL) { - circuit_p_io_removed = p_io_removed->next; - free(p_io_removed->data_vptr); - free(p_io_removed); - p_io_removed = circuit_p_io_removed; - } -} - -void vpr_free_vpr_data_structures(INOUTP t_arch Arch, INOUTP t_options options, - INOUTP t_vpr_setup vpr_setup) { - - if (vpr_setup.Timing.SDCFile != NULL) { - free(vpr_setup.Timing.SDCFile); - vpr_setup.Timing.SDCFile = NULL; - } - - free_options(&options); - free_circuit(); - free_arch(&Arch); - free_echo_file_info(); - free_output_file_names(); - free_timing_stats(); - free_sdc_related_structs(); -} - -void vpr_free_all(INOUTP t_arch Arch, INOUTP t_options options, - INOUTP t_vpr_setup vpr_setup) { - free_rr_graph(); - if (vpr_setup.RouterOpts.doRouting) { - free_route_structs(); - } - free_trace_structs(); - vpr_free_vpr_data_structures(Arch, options, vpr_setup); - if (has_printhandler_pre_vpr == FALSE) { - PrintHandlerDelete(); - } -} - -/**************************************************************************************************** - * Advanced functions - * Used when you need fine-grained control over VPR that the main VPR operations do not enable - ****************************************************************************************************/ -/* Read in user options */ -void vpr_read_options(INP int argc, INP char **argv, OUTP t_options * options) { - ReadOptions(argc, argv, options); -} - -/* Read in arch and circuit */ -void vpr_setup_vpr(INP t_options *Options, INP boolean TimingEnabled, - INP boolean readArchFile, OUTP struct s_file_name_opts *FileNameOpts, - INOUTP t_arch * Arch, OUTP enum e_operation *Operation, - OUTP t_model ** user_models, OUTP t_model ** library_models, - OUTP struct s_packer_opts *PackerOpts, - OUTP struct s_placer_opts *PlacerOpts, - OUTP struct s_annealing_sched *AnnealSched, - OUTP struct s_router_opts *RouterOpts, - OUTP struct s_det_routing_arch *RoutingArch, - OUTP t_segment_inf ** Segments, OUTP t_timing_inf * Timing, - OUTP boolean * ShowGraphics, OUTP int *GraphPause, - t_power_opts * PowerOpts, - /*Xifan TANG: Switch Segment Pattern Support*/ - OUTP t_swseg_pattern_inf** swseg_patterns, - /* Xifan TANG: FPGA-SPICE Tool Suites Support*/ - OUTP t_fpga_spice_opts* FPGA_SPICE_Opts) { - SetupVPR(Options, TimingEnabled, readArchFile, FileNameOpts, Arch, - Operation, user_models, library_models, PackerOpts, PlacerOpts, - AnnealSched, RouterOpts, RoutingArch, Segments, Timing, - ShowGraphics, GraphPause, PowerOpts, swseg_patterns, FPGA_SPICE_Opts); -} -/* Check inputs are reasonable */ -void vpr_check_options(INP t_options Options, INP boolean TimingEnabled) { - CheckOptions(Options, TimingEnabled); -} -void vpr_check_arch(INP t_arch Arch, INP boolean TimingEnabled) { - CheckArch(Arch, TimingEnabled); -} -/* Verify settings don't conflict or otherwise not make sense */ -void vpr_check_setup(INP enum e_operation Operation, - INP struct s_placer_opts PlacerOpts, - INP struct s_annealing_sched AnnealSched, - INP struct s_router_opts RouterOpts, - INP struct s_det_routing_arch RoutingArch, INP t_segment_inf * Segments, - INP t_timing_inf Timing, INP t_chan_width_dist Chans) { - CheckSetup(Operation, PlacerOpts, AnnealSched, RouterOpts, RoutingArch, - Segments, Timing, Chans); -} -/* Read blif file and sweep unused components */ -void vpr_read_and_process_blif(INP char *blif_file, - INP boolean sweep_hanging_nets_and_inputs, INP t_model *user_models, - INP t_model *library_models, boolean read_activity_file, - char * activity_file) { - read_and_process_blif(blif_file, sweep_hanging_nets_and_inputs, user_models, - library_models, read_activity_file, activity_file); -} -/* Show current setup */ -void vpr_show_setup(INP t_options options, INP t_vpr_setup vpr_setup) { - ShowSetup(options, vpr_setup); -} - -/* Output file names management */ -void vpr_alloc_and_load_output_file_names(const char* default_name) { - alloc_and_load_output_file_names(default_name); -} -void vpr_set_output_file_name(enum e_output_files ename, const char *name, - const char* default_name) { - setOutputFileName(ename, name, default_name); -} -char *vpr_get_output_file_name(enum e_output_files ename) { - return getOutputFileName(ename); -} - -/* logical equivalence scrambles the packed netlist indices with the actual indices, need to resync then re-output clustered netlist, this code assumes I'm dealing with a TI CLAY v1 architecture */ -/* Returns a trace array [0..num_logical_nets-1] with the final routing of the circuit from the logical_block netlist, index of the trace array corresponds to the index of a vpack_net */ -t_trace* vpr_resync_post_route_netlist_to_TI_CLAY_v1_architecture( - INP const t_arch *arch) { - t_trace *trace; - - /* Map post-routed traces to clb_nets and block */ - resync_post_route_netlist(); - - /* Resolve logically equivalent inputs */ - clay_logical_equivalence_handling(arch); - - /* Finalize traceback */ - trace = alloc_and_load_final_routing_trace(); - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_COMPLETE_NET_TRACE)) { - print_complete_net_trace(trace, - getEchoFileName(E_ECHO_COMPLETE_NET_TRACE)); - } - return trace; -} - -/* reload intra cluster nets to complex block */ -static void reload_intra_cluster_nets(t_pb *pb) { - int i, j; - const t_pb_type* pb_type; - pb_type = pb->pb_graph_node->pb_type; - if (pb_type->blif_model != NULL) { - setup_intracluster_routing_for_logical_block(pb->logical_block, - pb->pb_graph_node); - } else if (pb->child_pbs != NULL) { - set_pb_graph_mode(pb->pb_graph_node, pb->mode, 1); - for (i = 0; i < pb_type->modes[pb->mode].num_pb_type_children; i++) { - for (j = 0; j < pb_type->modes[pb->mode].pb_type_children[i].num_pb; - j++) { - if (pb->child_pbs[i] != NULL) { - if (pb->child_pbs[i][j].name != NULL) { - reload_intra_cluster_nets(&pb->child_pbs[i][j]); - } - } - } - } - } -} - -/* Determine trace from logical_block output to logical_block inputs - Algorithm traverses intra-block routing, goes to inter-block routing, then returns to intra-block routing - */ -static t_trace *alloc_and_load_final_routing_trace() { - int i; - int iblock; - t_trace* final_routing_trace; - t_pb_graph_pin *pin; - - final_routing_trace = (t_trace*) my_calloc(num_logical_nets, - sizeof(t_trace)); - for (i = 0; i < num_logical_nets; i++) { - iblock = logical_block[vpack_net[i].node_block[0]].clb_index; - - final_routing_trace[i].iblock = iblock; - final_routing_trace[i].iswitch = OPEN; - final_routing_trace[i].index = OPEN; - final_routing_trace[i].next = NULL; - - pin = get_pb_graph_node_pin_from_vpack_net(i, 0); - if (!pin) - continue; - final_routing_trace[i].index = pin->pin_count_in_cluster; - - expand_routing_trace(&final_routing_trace[i], i); - } - - return final_routing_trace; -} - -/* Given a routing trace, expand until full trace is complete - returns pointer to last terminal trace - */ -static t_trace *expand_routing_trace(t_trace *trace, int ivpack_net) { - int i, iblock, inode, ipin, inet; - int gridx, gridy; - t_trace *current, *new_trace, *inter_cb_trace; - t_rr_node *local_rr_graph; - boolean success; - t_pb_graph_pin *pb_graph_pin; - - iblock = trace->iblock; - inode = trace->index; - local_rr_graph = block[iblock].pb->rr_graph; - current = trace; - - if (local_rr_graph[inode].pb_graph_pin->num_output_edges == 0) { - if (local_rr_graph[inode].pb_graph_pin->port->type == OUT_PORT) { - /* connection to outside cb */ - if (vpack_net[ivpack_net].is_global) { - inet = vpack_to_clb_net_mapping[ivpack_net]; - if (inet != OPEN) { - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { - pb_graph_pin = get_pb_graph_node_pin_from_clb_net(inet, - ipin); - new_trace = (t_trace*) my_calloc(1, sizeof(t_trace)); - new_trace->iblock = clb_net[inet].node_block[ipin]; - new_trace->index = pb_graph_pin->pin_count_in_cluster; - new_trace->iswitch = OPEN; - new_trace->num_siblings = 0; - new_trace->next = NULL; - current->next = new_trace; - current = expand_routing_trace(new_trace, ivpack_net); - } - } - } else { - inter_cb_trace = - trace_head[vpack_to_clb_net_mapping[ivpack_net]]; - if (inter_cb_trace != NULL) { - inter_cb_trace = inter_cb_trace->next; /* skip source and go right to opin */ - } - while (inter_cb_trace != NULL) { - /* continue traversing inter cb trace */ - if (rr_node[inter_cb_trace->index].type != SINK) { - new_trace = (t_trace*) my_calloc(1, sizeof(t_trace)); - new_trace->iblock = OPEN; - new_trace->index = inter_cb_trace->index; - new_trace->iswitch = inter_cb_trace->iswitch; - new_trace->num_siblings = 0; - new_trace->next = NULL; - current->next = new_trace; - if (rr_node[inter_cb_trace->index].type == IPIN) { - current = current->next; - gridx = rr_node[new_trace->index].xlow; - gridy = rr_node[new_trace->index].ylow; - gridy = gridy - grid[gridx][gridy].offset; - new_trace = (t_trace*) my_calloc(1, - sizeof(t_trace)); - new_trace->iblock = - grid[gridx][gridy].blocks[rr_node[inter_cb_trace->index].z]; - new_trace->index = - rr_node[inter_cb_trace->index].pb_graph_pin->pin_count_in_cluster; - new_trace->iswitch = OPEN; - new_trace->num_siblings = 0; - new_trace->next = NULL; - current->next = new_trace; - current = expand_routing_trace(new_trace, - ivpack_net); - } else { - current = current->next; - } - } - inter_cb_trace = inter_cb_trace->next; - } - } - } - } else { - /* connection to another intra-cluster pin */ - current = trace; - success = FALSE; - for (i = 0; i < local_rr_graph[inode].num_edges; i++) { - if (local_rr_graph[local_rr_graph[inode].edges[i]].prev_node - == inode) { - if (success == FALSE) { - success = TRUE; - } else { - current->next = (t_trace*) my_calloc(1, sizeof(t_trace)); - current = current->next; - current->iblock = trace->iblock; - current->index = trace->index; - current->iswitch = trace->iswitch; - current->next = NULL; - } - new_trace = (t_trace*) my_calloc(1, sizeof(t_trace)); - new_trace->iblock = trace->iblock; - new_trace->index = local_rr_graph[inode].edges[i]; - new_trace->iswitch = OPEN; - new_trace->num_siblings = 0; - new_trace->next = NULL; - current->next = new_trace; - current = expand_routing_trace(new_trace, ivpack_net); - } - } - assert(success); - } - return current; -} - -static void print_complete_net_trace(t_trace* trace, const char *file_name) { - FILE *fp; - int iblock, inode, iprev_block; - t_trace *current; - t_rr_node *local_rr_graph; - const char *name_type[] = { "SOURCE", "SINK", "IPIN", "OPIN", "CHANX", - "CHANY", "INTRA_CLUSTER_EDGE" }; - int i; - - fp = my_fopen(file_name, "w", 0); - - for (i = 0; i < num_logical_nets; i++) { - current = &trace[i]; - iprev_block = OPEN; - - fprintf(fp, "Net %s (%d)\n\n", vpack_net[i].name, i); - while (current != NULL) { - iblock = current->iblock; - inode = current->index; - if (iblock != OPEN) { - if (iprev_block != iblock) { - iprev_block = iblock; - fprintf(fp, "Block %s (%d) (%d, %d, %d):\n", - block[iblock].name, iblock, block[iblock].x, - block[iblock].y, block[iblock].z); - } - local_rr_graph = block[iblock].pb->rr_graph; - fprintf(fp, "\tNode:\t%d\t%s[%d].%s[%d]", inode, - local_rr_graph[inode].pb_graph_pin->parent_node->pb_type->name, - local_rr_graph[inode].pb_graph_pin->parent_node->placement_index, - local_rr_graph[inode].pb_graph_pin->port->name, - local_rr_graph[inode].pb_graph_pin->pin_number); - } else { - fprintf(fp, "Node:\t%d\t%6s (%d,%d) ", inode, - name_type[(int) rr_node[inode].type], - rr_node[inode].xlow, rr_node[inode].ylow); - - if ((rr_node[inode].xlow != rr_node[inode].xhigh) - || (rr_node[inode].ylow != rr_node[inode].yhigh)) - fprintf(fp, "to (%d,%d) ", rr_node[inode].xhigh, - rr_node[inode].yhigh); - - switch (rr_node[inode].type) { - - case IPIN: - case OPIN: - if (grid[rr_node[inode].xlow][rr_node[inode].ylow].type - == IO_TYPE) { - fprintf(fp, " Pad: "); - } else { /* IO Pad. */ - fprintf(fp, " Pin: "); - } - break; - - case CHANX: - case CHANY: - fprintf(fp, " Track: "); - break; - - case SOURCE: - case SINK: - if (grid[rr_node[inode].xlow][rr_node[inode].ylow].type - == IO_TYPE) { - fprintf(fp, " Pad: "); - } else { /* IO Pad. */ - fprintf(fp, " Class: "); - } - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, - "in print_route: Unexpected traceback element type: %d (%s).\n", - rr_node[inode].type, - name_type[rr_node[inode].type]); - exit(1); - break; - } - - fprintf(fp, "%d ", rr_node[inode].ptc_num); - - /* Uncomment line below if you're debugging and want to see the switch types * - * used in the routing. */ - /* fprintf (fp, "Switch: %d", tptr->iswitch); */ - - fprintf(fp, "\n"); - } - current = current->next; - } - fprintf(fp, "\n"); - } - fclose(fp); -} - -void resync_post_route_netlist() { - int i, j, iblock; - int gridx, gridy; - t_trace *trace; - for (i = 0; i < num_blocks; i++) { - for (j = 0; j < block[i].type->num_pins; j++) { - if (block[i].nets[j] != OPEN - && clb_net[block[i].nets[j]].is_global == FALSE) - block[i].nets[j] = OPEN; - } - } - for (i = 0; i < num_nets; i++) { - if (clb_net[i].is_global == TRUE) - continue; - j = 0; - trace = trace_head[i]; - while (trace != NULL) { - if (rr_node[trace->index].type == OPIN && j == 0) { - gridx = rr_node[trace->index].xlow; - gridy = rr_node[trace->index].ylow; - gridy = gridy - grid[gridx][gridy].offset; - iblock = grid[gridx][gridy].blocks[rr_node[trace->index].z]; - assert(clb_net[i].node_block[j] == iblock); - clb_net[i].node_block_pin[j] = rr_node[trace->index].ptc_num; - block[iblock].nets[rr_node[trace->index].ptc_num] = i; - j++; - } else if (rr_node[trace->index].type == IPIN) { - gridx = rr_node[trace->index].xlow; - gridy = rr_node[trace->index].ylow; - gridy = gridy - grid[gridx][gridy].offset; - iblock = grid[gridx][gridy].blocks[rr_node[trace->index].z]; - clb_net[i].node_block[j] = iblock; - clb_net[i].node_block_pin[j] = rr_node[trace->index].ptc_num; - block[iblock].nets[rr_node[trace->index].ptc_num] = i; - j++; - } - trace = trace->next; - } - assert(j == clb_net[i].num_sinks + 1); - } -} - -static void clay_logical_equivalence_handling(const t_arch *arch) { - t_trace **saved_ext_rr_trace_head, **saved_ext_rr_trace_tail; - t_rr_node *saved_ext_rr_node; - int num_ext_rr_node, num_ext_nets; - int i, j; - - for (i = 0; i < num_blocks; i++) { - clay_reload_ble_locations(i); - } - - /* Resolve logically equivalent inputs */ - saved_ext_rr_trace_head = trace_head; - saved_ext_rr_trace_tail = trace_tail; - saved_ext_rr_node = rr_node; - num_ext_rr_node = num_rr_nodes; - num_ext_nets = num_nets; - num_rr_nodes = 0; - rr_node = NULL; - trace_head = NULL; - trace_tail = NULL; - free_rr_graph(); /* free all data structures associated with rr_graph */ - - alloc_and_load_cluster_legality_checker(); - for (i = 0; i < num_blocks; i++) { - /* Regenerate rr_graph (note, can be more runtime efficient but this allows for more code reuse) - */ - rr_node = block[i].pb->rr_graph; - num_rr_nodes = block[i].pb->pb_graph_node->total_pb_pins; - free_legalizer_for_cluster(&block[i], TRUE); - alloc_and_load_legalizer_for_cluster(&block[i], i, arch); - reload_intra_cluster_nets(block[i].pb); - reload_ext_net_rr_terminal_cluster(); - force_post_place_route_cb_input_pins(i); -#ifdef HACK_LUT_PIN_SWAPPING - /* Resolve rebalancing of LUT inputs */ - clay_lut_input_rebalancing(i, block[i].pb); -#endif - - /* reset rr_graph */ - for (j = 0; j < num_rr_nodes; j++) { - rr_node[j].occ = 0; - rr_node[j].prev_edge = OPEN; - rr_node[j].prev_node = OPEN; - } - if (try_breadth_first_route_cluster() == FALSE) { - vpr_printf(TIO_MESSAGE_ERROR, - "Failed to resync post routed solution with clustered netlist.\n"); - vpr_printf(TIO_MESSAGE_ERROR, "Cannot recover from error.\n"); - exit(1); - } - save_cluster_solution(); - reset_legalizer_for_cluster(&block[i]); - free_legalizer_for_cluster(&block[i], FALSE); - } - free_cluster_legality_checker(); - - trace_head = saved_ext_rr_trace_head; - trace_tail = saved_ext_rr_trace_tail; - rr_node = saved_ext_rr_node; - num_rr_nodes = num_ext_rr_node; - num_nets = num_ext_nets; -} - -/* Force router to use the LUT inputs designated by the timing engine post the LUT input rebalancing optimization */ -static void clay_lut_input_rebalancing(int iblock, t_pb *pb) { - int i, j; - t_rr_node *local_rr_graph; - t_pb_graph_node *lut_wrapper, *lut; - int lut_size; - int *lut_pin_remap; - int snode, input; - t_pb_graph_node *pb_graph_node; - - if (pb->name != NULL) { - pb_graph_node = pb->pb_graph_node; - if (pb_graph_node->pb_type->blif_model != NULL) { - lut_pin_remap = pb->lut_pin_remap; - if (lut_pin_remap != NULL) { - local_rr_graph = block[iblock].pb->rr_graph; - lut = pb->pb_graph_node; - lut_wrapper = lut->parent_pb_graph_node; - - /* Ensure that this is actually a LUT */ - assert( - lut->num_input_ports == 1 && lut_wrapper->num_input_ports == 1); - assert( - lut->num_input_pins[0] == lut_wrapper->num_input_pins[0]); - assert( - lut->num_output_ports == 1 && lut_wrapper->num_output_ports == 1); - assert( - lut->num_output_pins[0] == 1 && lut_wrapper->num_output_pins[0] == 1); - - lut_size = lut->num_input_pins[0]; - for (i = 0; i < lut_size; i++) { - snode = lut_wrapper->input_pins[0][i].pin_count_in_cluster; - free(local_rr_graph[snode].edges); - local_rr_graph[snode].edges = NULL; - local_rr_graph[snode].num_edges = 0; - } - for (i = 0; i < lut_size; i++) { - input = lut_pin_remap[i]; - if (input != OPEN) { - snode = - lut_wrapper->input_pins[0][i].pin_count_in_cluster; - assert(local_rr_graph[snode].num_edges == 0); - local_rr_graph[snode].num_edges = 1; - local_rr_graph[snode].edges = (int*) my_malloc( - sizeof(int)); - local_rr_graph[snode].edges[0] = - lut->input_pins[0][input].pin_count_in_cluster; - } - } - } - } else if (pb->child_pbs != NULL) { - for (i = 0; - i - < pb_graph_node->pb_type->modes[pb->mode].num_pb_type_children; - i++) { - if (pb->child_pbs[i] != NULL) { - for (j = 0; - j - < pb_graph_node->pb_type->modes[pb->mode].pb_type_children[i].num_pb; - j++) { - clay_lut_input_rebalancing(iblock, - &pb->child_pbs[i][j]); - } - } - } - } - } -} - -/* Swaps BLEs to match output logical equivalence solution from routing solution - Assumes classical cluster with full crossbar and BLEs, each BLE is a single LUT+FF pair - */ -static void clay_reload_ble_locations(int iblock) { - int i, mode, ipin, new_loc; - t_pb_graph_node *pb_graph_node; - t_pb_graph_pin *pb_graph_pin; - const t_pb_type *pb_type; - t_trace *trace; - t_rr_node *local_rr_graph; - int inet, ivpack_net; - - if (block[iblock].type == IO_TYPE) { - return; - } - - pb_graph_node = block[iblock].pb->pb_graph_node; - pb_type = pb_graph_node->pb_type; - mode = block[iblock].pb->mode; - local_rr_graph = block[iblock].pb->rr_graph; - - assert(block[iblock].pb->mode == 0); - assert(pb_type->modes[mode].num_pb_type_children == 1); - assert(pb_type->modes[mode].pb_type_children[0].num_output_pins == 1); - - t_pb** temp; - temp = (t_pb**) my_calloc(1, sizeof(t_pb*)); - temp[0] = (t_pb*) my_calloc(pb_type->modes[mode].pb_type_children[0].num_pb, - sizeof(t_pb)); - - /* determine new location for BLEs that route out of cluster */ - for (i = 0; i < pb_type->modes[mode].pb_type_children[0].num_pb; i++) { - if (block[iblock].pb->child_pbs[0][i].name != NULL) { - ivpack_net = - local_rr_graph[pb_graph_node->child_pb_graph_nodes[mode][0][i].output_pins[0][0].pin_count_in_cluster].net_num; - inet = vpack_to_clb_net_mapping[ivpack_net]; - if (inet != OPEN) { - ipin = OPEN; - trace = trace_head[inet]; - while (trace) { - if (rr_node[trace->index].type == OPIN) { - ipin = rr_node[trace->index].ptc_num; - break; - } - trace = trace->next; - } - assert(ipin); - pb_graph_pin = get_pb_graph_node_pin_from_block_pin(iblock, - ipin); - new_loc = pb_graph_pin->pin_number; - assert(temp[0][new_loc].name == NULL); - temp[0][new_loc] = block[iblock].pb->child_pbs[0][i]; - } - } - } - - /* determine new location for BLEs that do not route out of cluster */ - new_loc = 0; - for (i = 0; i < pb_type->modes[mode].pb_type_children[0].num_pb; i++) { - if (block[iblock].pb->child_pbs[0][i].name != NULL) { - ivpack_net = - local_rr_graph[pb_graph_node->child_pb_graph_nodes[mode][0][i].output_pins[0][0].pin_count_in_cluster].net_num; - inet = vpack_to_clb_net_mapping[ivpack_net]; - if (inet == OPEN) { - while (temp[0][new_loc].name != NULL) { - new_loc++; - } - temp[0][new_loc] = block[iblock].pb->child_pbs[0][i]; - } - } - } - - free(block[iblock].pb->child_pbs); - block[iblock].pb->child_pbs = temp; - resync_pb_graph_nodes_in_pb(block[iblock].pb->pb_graph_node, - block[iblock].pb); -} - -static void resync_pb_graph_nodes_in_pb(t_pb_graph_node *pb_graph_node, - t_pb *pb) { - int i, j; - - if (pb->name == NULL) { - return; - } - - assert( - strcmp(pb->pb_graph_node->pb_type->name, pb_graph_node->pb_type->name) == 0); - - pb->pb_graph_node = pb_graph_node; - if (pb->child_pbs != NULL) { - for (i = 0; - i < pb_graph_node->pb_type->modes[pb->mode].num_pb_type_children; - i++) { - if (pb->child_pbs[i] != NULL) { - for (j = 0; - j - < pb_graph_node->pb_type->modes[pb->mode].pb_type_children[i].num_pb; - j++) { - resync_pb_graph_nodes_in_pb( - &pb_graph_node->child_pb_graph_nodes[pb->mode][i][j], - &pb->child_pbs[i][j]); - } - } - } - } -} - -/* This function performs power estimation, and must be called - * after packing, placement AND routing. Currently, this - * will not work when running a partial flow (ex. only routing). - */ -void vpr_power_estimation(t_vpr_setup vpr_setup, t_arch Arch) { - e_power_ret_code power_ret_code; - boolean power_error; - - /* Ensure we are only using 1 clock */ - //assert(count_netlist_clocks() == 1); - - /* Get the critical path of this clock */ - g_solution_inf.T_crit = get_critical_path_delay() / 1e9; - assert(g_solution_inf.T_crit > 0.); - - vpr_printf(TIO_MESSAGE_INFO, "\n\nPower Estimation:\n"); - vpr_printf(TIO_MESSAGE_INFO, "-----------------\n"); - - vpr_printf(TIO_MESSAGE_INFO, "Initializing power module\n"); - - /* Initialize the power module */ - power_error = power_init(vpr_setup.FileNameOpts.PowerFile, - vpr_setup.FileNameOpts.CmosTechFile, &Arch, &vpr_setup.RoutingArch); - if (power_error) { - vpr_printf(TIO_MESSAGE_ERROR, "Power initialization failed.\n"); - } - - if (!power_error) { - float power_runtime_s; - - vpr_printf(TIO_MESSAGE_INFO, "Running power estimation\n"); - - /* Run power estimation */ - power_ret_code = power_total(&power_runtime_s, vpr_setup, &Arch, - &vpr_setup.RoutingArch); - - /* Check for errors/warnings */ - if (power_ret_code == POWER_RET_CODE_ERRORS) { - vpr_printf(TIO_MESSAGE_ERROR, - "Power estimation failed. See power output for error details.\n"); - } else if (power_ret_code == POWER_RET_CODE_WARNINGS) { - vpr_printf(TIO_MESSAGE_WARNING, - "Power estimation completed with warnings. See power output for more details.\n"); - } else if (power_ret_code == POWER_RET_CODE_SUCCESS) { - } - vpr_printf(TIO_MESSAGE_INFO, "Power estimation took %g seconds\n", - power_runtime_s); - } - - /* Uninitialize power module */ - if (!power_error) { - vpr_printf(TIO_MESSAGE_INFO, "Uninitializing power module\n"); - power_error = power_uninit(); - if (power_error) { - vpr_printf(TIO_MESSAGE_ERROR, "Power uninitialization failed.\n"); - } else { - - } - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); -} - - diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.h b/vpr7_x2p/vpr/SRC/base/vpr_api.h deleted file mode 100644 index f81694e49..000000000 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - General API for VPR - - VPR is a CAD tool used to conduct FPGA architecture exploration. It takes, as input, a technology-mapped netlist and a description of the FPGA architecture being investigated. - VPR then generates a packed, placed, and routed FPGA (in .net, .place, and .route files respectively) that implements the input netlist - - Software tools interfacing to VPR should generally call just the functions defined here - For advanced/power users, you can call functions defined elsewhere in VPR or modify the data structures directly at your discretion but be aware that doing so can break the correctness of this tool - - General Usage: - 1. vpr_init - 2. vpr_pack - 3. vpr_init_pre_place_and_route - 4. vpr_place_and_route - 5. vpr_free_all - - If you are a new developer, key files to begin understanding this code base are: - 1. libarchfpga/physical_types.h - Data structures that define the properties of the FPGA architecture - 2. vpr_types.h - Very major file that defines the core data structures used in VPR. This includes detailed architecture information, user netlist data structures, and data structures that describe the mapping between those two. - 3. globals.h - Defines the global variables used by VPR. - - Author: Jason Luu - June 21, 2012 - */ - -#ifndef VPR_API_H -#define VPR_API_H - -#include "physical_types.h" -#include "vpr_types.h" -#include "ReadOptions.h" -#include "OptionTokens.h" -#include "globals.h" -/* mrFPGA: Xifan TANG */ -#include "mrfpga_globals.h" -/* END */ -#include "util.h" -#include "read_xml_arch_file.h" -#include "vpr_utils.h" - -/* Main VPR Operations */ -void vpr_init(INP int argc, INP char **argv, OUTP t_options *options, - OUTP t_vpr_setup *vpr_setup, OUTP t_arch *arch); -void vpr_pack(INP t_vpr_setup vpr_setup, INP t_arch arch); -void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch); -void vpr_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch arch); -void vpr_power_estimation(t_vpr_setup vpr_setup, t_arch Arch); -void vpr_free_vpr_data_structures(INOUTP t_arch Arch, INOUTP t_options options, - INOUTP t_vpr_setup vpr_setup); -void vpr_free_all(INOUTP t_arch Arch, INOUTP t_options options, - INOUTP t_vpr_setup vpr_setup); - -/* Display general info to user */ -void vpr_print_title(void); -void vpr_print_usage(void); - -/**************************************************************************************************** - * Advanced functions - * Used when you need fine-grained control over VPR that the main VPR operations do not enable - ****************************************************************************************************/ -/* Read in user options */ -void vpr_read_options(INP int argc, INP char **argv, OUTP t_options * options); -/* Read in arch and circuit */ -void vpr_setup_vpr(INP t_options *Options, INP boolean TimingEnabled, - INP boolean readArchFile, OUTP struct s_file_name_opts *FileNameOpts, - INOUTP t_arch * Arch, OUTP enum e_operation *Operation, - OUTP t_model ** user_models, OUTP t_model ** library_models, - OUTP struct s_packer_opts *PackerOpts, - OUTP struct s_placer_opts *PlacerOpts, - OUTP struct s_annealing_sched *AnnealSched, - OUTP struct s_router_opts *RouterOpts, - OUTP struct s_det_routing_arch *RoutingArch, - OUTP t_segment_inf ** Segments, OUTP t_timing_inf * Timing, - OUTP boolean * ShowGraphics, OUTP int *GraphPause, - t_power_opts * PowerOpts); -/* Check inputs are reasonable */ -void vpr_check_options(INP t_options Options, INP boolean TimingEnabled); -void vpr_check_arch(INP t_arch Arch, INP boolean TimingEnabled); -/* Verify settings don't conflict or otherwise not make sense */ -void vpr_check_setup(INP enum e_operation Operation, - INP struct s_placer_opts PlacerOpts, - INP struct s_annealing_sched AnnealSched, - INP struct s_router_opts RouterOpts, - INP struct s_det_routing_arch RoutingArch, INP t_segment_inf * Segments, - INP t_timing_inf Timing, INP t_chan_width_dist Chans); -/* Read blif file and sweep unused components */ -void vpr_read_and_process_blif(INP char *blif_file, - INP boolean sweep_hanging_nets_and_inputs, INP t_model *user_models, - INP t_model *library_models, boolean read_activity_file, - char * activity_file); -/* Show current setup */ -void vpr_show_setup(INP t_options options, INP t_vpr_setup vpr_setup); - -/* Output file names management */ -void vpr_alloc_and_load_output_file_names(const char* default_name); -void vpr_set_output_file_name(enum e_output_files ename, const char *name, - const char* default_name); -char *vpr_get_output_file_name(enum e_output_files ename); - -/* resync netlists */ -t_trace* vpr_resync_post_route_netlist_to_TI_CLAY_v1_architecture( - INP const t_arch *arch); - -/* FPGA-SPICE */ -#include "fpga_x2p_api.h" - -/* mrFPGA : Xifan TANG */ -#include "mrfpga_api.h" -/* END */ - -/* APIs to be call by the interactive shell*/ -void vpr_init_file_handler() ; - -#endif diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h deleted file mode 100755 index 733216d9b..000000000 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ /dev/null @@ -1,1349 +0,0 @@ -/* This is a core file that defines the major data types used by VPR - - This file is divided into generally 4 major sections: - - 1. Global data types and constants - 2. Packing specific data types - 3. Placement specific data types - 4. Routing specific data types - - Key background file: - - An understanding of libvpr/physical_types.h is crucial to understanding this file. physical_types.h contains information about the architecture described in the architecture description language - - Key data structures: - - logical_block - One node in the input technology-mapped netlist - net - Connectivity data structure for the user netlist - block - An already clustered logic block - rr_node - The basic building block of the interconnect in the FPGA architecture - - Cluster-specific main data structure: - - t_pb: Stores the mapping between the user netlist and the logic blocks on the FPGA achitecture. For example, if a user design has 10 clusters of 5 LUTs each, you will have 10 t_pb instances of type cluster and within each of those clusters another 5 t_pb instances of type LUT. - The t_pb hierarchy follows what is described by t_pb_graph_node - - Each top-level pb stores the entire routing resource graph (rr_graph). The traceback information is included in this rr_graph so if you needed to determine connectivity down to the wire level, this is the data structure that you would traverse. - The rr_graph is generated based on the pb_graph_node netlist of that pb. Each pb_graph_node has a member variable called pin_count that serves as the index for the rr_node (in retrospect, I should have used rr_node_index instead of pin_count for the member variable to be more descriptive). - This makes it easy to identify which rr_node corresponds to which pb_graph_pin. Additional sources and sinks are generated at the inputs and outputs of the complex logic block to match with what has already been packed into the cluster. - - - */ - -#ifndef VPR_TYPES_H -#define VPR_TYPES_H - -#include "arch_types.h" -#include -#include -#include - -/******************************************************************************* - * Global data types and constants - ******************************************************************************/ -typedef struct s_power_opts t_power_opts; -typedef struct s_net_power t_net_power; - -#ifndef SPEC -#define DEBUG 1 /* Echoes input & checks error conditions */ -/* Only causes about a 1% speed degradation in V 3.10 */ -#endif - -/*#define CREATE_ECHO_FILES*//* prints echo files */ -/*#define DEBUG_FAILED_PACKING_CANDIDATES*//*Displays candidates during packing that failed */ -/*#define PRINT_SINK_DELAYS*//*prints the sink delays to files */ -/*#define PRINT_SLACKS*//*prints out all slacks in the circuit */ -/*#define PRINT_PLACE_CRIT_PATH*//*prints out placement estimated critical path */ -/*#define PRINT_NET_DELAYS*//*prints out delays for all connections */ -/*#define PRINT_TIMING_GRAPH*//*prints out the timing graph */ -/*#define PRINT_REL_POS_DISTR *//*prints out the relative distribution graph for placements */ -/*#define DUMP_BLIF_ECHO*//*dump blif of internal representation of user circuit. Useful for ensuring functional correctness via logical equivalence with input blif*/ -/*#define HACK_LUT_PIN_SWAPPING*//* Hack to enable LUT input pin swapping for delay purposes */ - -#ifdef SPEC -#define NO_GRAPHICS /* Rips out graphics (for non-X11 systems) */ -#define NDEBUG /* Turns off assertion checking for extra speed */ -#endif - -#define TOKENS " \t\n" /* Input file parsing. */ - -/*#define VERBOSE 1*//* Prints all sorts of intermediate data */ - -typedef size_t bitfield; - -#define MINOR 0 /* For update_screen. Denotes importance of update. */ -#define MAJOR 1 - -#define MAX_SHORT 32767 - -/* Values large enough to be way out of range for any data, but small enough - to allow a small number to be added to them without going out of range. */ -#define HUGE_POSITIVE_FLOAT 1.e30 -#define HUGE_NEGATIVE_FLOAT -1.e30 - -/* Used to avoid floating-point errors when comparing values close to 0 */ -#define EPSILON 1.e-15 -#define NEGATIVE_EPSILON -1.e-15 - -#define HIGH_FANOUT_NET_LIM 64 /* All nets with this number of sinks or more are considered high fanout nets */ - -#define FIRST_ITER_WIRELENTH_LIMIT 0.85 /* If used wirelength exceeds this value in first iteration of routing, do not route */ - -#define EMPTY -1 - -/******************************************************************************* - * Packing specific data types and constants - * Packing takes the circuit described in the technology mapped user netlist - * and maps it to the complex logic blocks found in the arhictecture - ******************************************************************************/ - -#define NO_CLUSTER -1 -#define NEVER_CLUSTER -2 -#define NOT_VALID -10000 /* Marks gains that aren't valid */ -/* Ensure no gain can ever be this negative! */ -#ifndef UNDEFINED -#define UNDEFINED -1 -#endif - -/* netlist blocks are assigned one of these types */ -enum logical_block_types { - VPACK_INPAD = -2, VPACK_OUTPAD, VPACK_COMB, VPACK_LATCH, VPACK_EMPTY -}; - -/* Selection algorithm for selecting next seed */ -enum e_cluster_seed { - VPACK_TIMING, VPACK_MAX_INPUTS -}; - -enum e_block_pack_status { - BLK_PASSED, BLK_FAILED_FEASIBLE, BLK_FAILED_ROUTE, BLK_STATUS_UNDEFINED -}; - -struct s_rr_node; -/* defined later, but need to declare here because it is used */ -struct s_pack_molecule; -/* defined later, but need to declare here because it is used */ - -/* Stores statistical information for pb such as cost information */ -typedef struct s_pb_stats { - /* Packing statistics */ - std::map gain; /* Attraction (inverse of cost) function */ - - std::map timinggain; /* [0..num_logical_blocks-1]. The timing criticality score of this logical_block. - Determined by the most critical vpack_net between this logical_block and any logical_block in the current pb */ - std::map connectiongain; /* [0..num_logical_blocks-1] Weighted sum of connections to attraction function */ - std::map prevconnectiongainincr; /* [0..num_logical_blocks-1] Prev sum to weighted sum of connections to attraction function */ - std::map sharinggain; /* [0..num_logical_blocks-1]. How many nets on this logical_block are already in the pb under consideration */ - - /* [0..num_logical_blocks-1]. This is the gain used for hill-climbing. It stores* - * the reduction in the number of pins that adding this logical_block to the the* - * current pb will have. This reflects the fact that sometimes the * - * addition of a logical_block to a pb may reduce the number of inputs * - * required if it shares inputs with all other BLEs and it's output is * - * used by all other child pbs in this parent pb. */ - std::map hillgain; - - /* [0..num_marked_nets] and [0..num_marked_blocks] respectively. List * - * the indices of the nets and blocks that have had their num_pins_of_ * - * net_in_pb and gain entries altered. */ - int *marked_nets, *marked_blocks; - int num_marked_nets, num_marked_blocks; - int num_child_blocks_in_pb; - - int tie_break_high_fanout_net; /* If no marked candidate atoms, use this high fanout net to determine the next candidate atom */ - - /* [0..num_logical_nets-1]. How many pins of each vpack_net are contained in the * - * currently open pb? */ - std::map num_pins_of_net_in_pb; - - /* Record of pins of class used TODO: Jason Luu: Should really be using hash table for this for speed, too lazy to write one now, performance isn't too bad since I'm at most iterating over the number of pins of a pb which is effectively a constant for reasonable architectures */ - int **input_pins_used; /* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of input pins of this class that are used */ - int **output_pins_used; /* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of output pins of this class that are used */ - - int **lookahead_input_pins_used; /* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of input pins of this class that are speculatively used */ - int **lookahead_output_pins_used; /* [0..pb_graph_node->num_pin_classes-1][0..pin_class_size] number of output pins of this class that are speculatively used */ - - /* Array of feasible blocks to select from [0..max_array_size-1] - Sorted in ascending gain order so that the last block is the most desirable (this makes it easy to pop blocks off the list - */ - struct s_pack_molecule **feasible_blocks; - int num_feasible_blocks; /* [0..num_marked_models-1] */ -} t_pb_stats; - -/* An FPGA complex block is represented by a hierarchy of physical blocks. - These include leaf physical blocks that a netlist block can map to (such as LUTs, flip-flops, memory slices, etc), - parent physical blocks that contain children physical blocks (such as a BLE) that may be leaves or parents of other physical blocks, - and the top-level phyiscal block which represents the complex block itself (such as a clustered logic block). - - All physical blocks are represented by this s_pb data structure. - */ -typedef struct s_pb { - char *name; /* Name of this physical block */ - t_pb_graph_node *pb_graph_node; /* pointer to pb_graph_node this pb corresponds to */ - int logical_block; /* If this is a terminating pb, gives the logical (netlist) block that it contains */ - - int mode; /* mode that this pb is set to */ - - struct s_pb **child_pbs; /* children pbs attached to this pb [0..num_child_pb_types - 1][0..child_type->num_pb - 1] */ - struct s_pb *parent_pb; /* pointer to parent node */ - - struct s_rr_node *rr_graph; /* pointer to rr_graph connecting pbs of cluster */ - struct s_pb **rr_node_to_pb_mapping; /* [0..num_local_rr_nodes-1] pointer look-up of which pb this rr_node belongs based on index, NULL if pb does not exist */ - struct s_pb_stats *pb_stats; /* statistics for current pb */ - - struct s_net *local_nets; /* Records post-packing connections, valid only for top-level */ - int num_local_nets; /* Records post-packing connections, valid only for top-level */ - - int clock_net; /* Records clock net driving a flip-flop, valid only for lowest-level, flip-flop PBs */ - - int *lut_pin_remap; /* [0..num_lut_inputs-1] applies only to LUT primitives, stores how LUT inputs were swapped during CAD flow, - LUT inputs can be swapped by changing the logic in the LUT, this is useful because the fastest LUT input compared to the slowest is often significant (2-5x), - so this optimization is crucial for handling LUT based FPGAs. - */ - - /* Xifan TANG: SPICE model support*/ - char* spice_name_tag; - void* phy_pb; - - /* Xifan TANG: FPGA-SPICE and SynVerilog */ - int num_reserved_conf_bits; - int num_conf_bits; - int num_mode_bits; - int num_inpads; - int num_outpads; - int num_iopads; -} t_pb; - -struct s_tnode; - -/* Technology-mapped user netlist block */ -typedef struct s_logical_block { - char *name; /* Taken from the first vpack_net which it drives. */ - enum logical_block_types type; /* I/O, combinational logic, or latch */ - t_model* model; /* Technology-mapped type (eg. LUT, Flip-flop, memory slice, inpad, etc) */ - - int **input_nets; /* [0..num_input_ports-1][0..num_port_pins-1] List of input nets connected to this logical_block. */ - int **output_nets; /* [0..num_output_ports-1][0..num_port_pins-1] List of output nets connected to this logical_block. */ - int clock_net; /* Clock net connected to this logical_block. */ - - int used_input_pins; /* Number of used input pins */ - - int clb_index; /* Complex block index that this logical block got mapped to */ - - int index; /* Index in array that this block can be found */ - t_pb* pb; /* pb primitive that this block is packed into */ - - /* timing information */ - struct s_tnode ***input_net_tnodes; /* [0..num_input_ports-1][0..num_pins -1] correspnding input net tnode */ - struct s_tnode ***output_net_tnodes; /* [0..num_output_ports-1][0..num_pins -1] correspnding output net tnode */ - struct s_tnode *clock_net_tnode; /* correspnding clock net tnode */ - - struct s_linked_vptr *truth_table; /* If this is a LUT (.names), then this is the logic that the LUT implements */ - struct s_linked_vptr *packed_molecules; /* List of t_pack_molecules that this logical block is a part of */ - - t_pb_graph_node *expected_lowest_cost_primitive; /* predicted ideal primitive to use for this logical block */ - - /* Xifan TANG: SPICE model support*/ - /* For mapping */ - CircuitModelId mapped_circuit_model; - t_spice_model* mapped_spice_model; - int mapped_spice_model_index; /* index of spice_model in completed FPGA netlist */ - int temp_used; - /* for Register/flip-flop */ - char* trigger_type; - int init_val; - boolean is_clock; - -} t_logical_block; - -enum e_pack_pattern_molecule_type { - MOLECULE_SINGLE_ATOM, MOLECULE_FORCED_PACK -}; - -/** - * Represents a grouping of logical_blocks that match a pack_pattern, these groups are intended to be placed as a single unit during packing - * Store in linked list - * - * A chain is a special type of pack pattern. A chain can extend across multiple logic blocks. Must segment the chain to fit in a logic block by identifying the actual atom that forms the root of the new chain. - * Assumes that the root of a chain is the primitive that starts the chain or is driven from outside the logic block - */ -typedef struct s_pack_molecule { - enum e_pack_pattern_molecule_type type; /* what kind of molecule is this? */ - t_pack_patterns *pack_pattern; /* If this is a forced_pack molecule, pattern this molecule matches */ - t_model_chain_pattern *chain_pattern; /* If this is a chain molecule, chain that this molecule matches */ - t_logical_block **logical_block_ptrs; /* [0..num_blocks-1] ptrs to logical blocks that implements this molecule, index on pack_pattern_block->index of pack pattern */ - boolean valid; /* Whether or not this molecule is still valid */ - - int num_blocks; /* number of logical blocks of molecule */ - int root; /* root index of molecule, logical_block_ptrs[root] is ptr to root logical block */ - - float base_gain; /* Intrinsic "goodness" score for molecule independant of rest of netlist */ - - int num_ext_inputs; /* number of input pins used by molecule that are not self-contained by pattern molecule matches */ - struct s_pack_molecule *next; -} t_pack_molecule; - -/** - * Stats keeper for placement information during packing - * Contains linked lists to placement locations based on status of primitive - */ -typedef struct s_cluster_placement_stats { - int num_pb_types; /* num primitive pb_types inside complex block */ - t_pack_molecule *curr_molecule; /* current molecule being considered for packing */ - t_cluster_placement_primitive **valid_primitives; /* [0..num_pb_types-1] ptrs to linked list of valid primitives, for convenience, each linked list head is empty */ - t_cluster_placement_primitive *in_flight; /* ptrs to primitives currently being considered */ - t_cluster_placement_primitive *tried; /* ptrs to primitives that are open but current logic block unable to pack to */ - t_cluster_placement_primitive *invalid; /* ptrs to primitives that are invalid */ -} t_cluster_placement_stats; - -/* Built-in library models */ -#define MODEL_LOGIC "names" -#define MODEL_LATCH "latch" -#define MODEL_INPUT "input" -#define MODEL_OUTPUT "output" - -/****************************************************************** - * Timing data types - *******************************************************************/ - -// #define PATH_COUNTING 'P' -/* Uncomment this to turn on path counting. Its value determines how path criticality - is calculated from forward and backward weights. Possible values: - 'S' - sum of forward and backward weights - 'P' - product of forward and backward weights - 'L' - natural log of the product of forward and backward weights - 'R' - product of the natural logs of forward and backward weights - See path_delay.h for further path-counting options. */ - -/* Timing graph information */ - -typedef struct s_tedge { - /* Edge in the timing graph. */ - int to_node; /* index of node at the sink end of this edge */ - float Tdel; /* delay to go to to_node along this edge */ -} t_tedge; - -typedef enum { - /* Types of tnodes (timing graph nodes). */ - TN_INPAD_SOURCE, /* input to an input I/O pad */ - TN_INPAD_OPIN, /* output from an input I/O pad */ - TN_OUTPAD_IPIN, /* input to an output I/O pad */ - TN_OUTPAD_SINK, /* output from an output I/O pad */ - TN_CB_IPIN, /* input pin to complex block */ - TN_CB_OPIN, /* output pin from complex block */ - TN_INTERMEDIATE_NODE, /* Used in post-packed timing graph only: - connection between intra-cluster pins. */ - TN_PRIMITIVE_IPIN, /* input pin to a primitive (e.g. a LUT) */ - TN_PRIMITIVE_OPIN, /* output pin from a primitive (e.g. a LUT) */ - TN_FF_IPIN, /* input pin to a flip-flop - goes to TN_FF_SINK */ - TN_FF_OPIN, /* output pin from a flip-flop - comes from TN_FF_SOURCE */ - TN_FF_SINK, /* sink (D) pin of flip-flop */ - TN_FF_SOURCE, /* source (Q) pin of flip-flop */ - TN_FF_CLOCK, /* clock pin of flip-flop */ - TN_CONSTANT_GEN_SOURCE /* source of a constant logic 1 or 0 */ -} e_tnode_type; - -typedef struct s_prepacked_tnode_data { - /* Data only used by prepacked tnodes. Stored separately so it - doesn't need to be allocated in the post-packed netlist. */ - int model_port, model_pin; /* technology mapped model pin */ - t_model_ports *model_port_ptr; -#ifndef PATH_COUNTING - long num_critical_input_paths, num_critical_output_paths; /* count of critical paths fanning into/out of this tnode */ - float normalized_slack; /* slack (normalized with respect to max slack) */ - float normalized_total_critical_paths; /* critical path count (normalized with respect to max count) */ - float normalized_T_arr; /* arrival time (normalized with respect to max time) */ -#endif -} t_prepacked_tnode_data; - -typedef struct s_tnode { - /* Node in the timing graph. Note: we combine 2 members into a bit field. */ - e_tnode_type type; /* see the above enum */ - t_tedge *out_edges; /* [0..num_edges - 1] array of edges fanning out from this tnode. - Note: there is a correspondence in indexing between out_edges and the - net data structure: out_edges[iedge] = net[inet].node_block[iedge + 1] - There is an offset of 1 because net[inet].node_block includes the driver - node at index 0, while out_edges is part of the driver node and does - not bother to refer to itself. */ - int num_edges; - float T_arr; /* Arrival time of the last input signal to this node. */ - float T_req; /* Required arrival time of the last input signal to this node - if the critical path is not to be lengthened. */ - int block; /* logical block primitive which this tnode is part of */ - -#ifdef PATH_COUNTING - float forward_weight, backward_weight; /* Weightings of the importance of paths - fanning into and out of this node, respectively. */ -#endif - - /* Valid values for TN_FF_SINK, TN_FF_SOURCE, TN_FF_CLOCK, TN_INPAD_SOURCE, and TN_OUTPAD_SINK only: */ - int clock_domain; /* Index of the clock in g_sdc->constrained_clocks which this flip-flop or I/O is constrained on. */ - float clock_delay; /* The time taken for a clock signal to get to the flip-flop or I/O (assumed 0 for I/Os). */ - - /* Used in post-packing timing graph only: */ - t_pb_graph_pin *pb_graph_pin; /* pb_graph_pin that this block is connected to */ - - /* Used in pre-packing timing graph only: */ - t_prepacked_tnode_data * prepacked_data; -} t_tnode; - -/* Other structures storing timing information */ - -typedef struct s_clock { - /* Stores information on clocks given timing constraints. - Used in SDC parsing and timing analysis. */ - char * name; - boolean is_netlist_clock; /* Is this a netlist or virtual (external) clock? */ - int fanout; -} t_clock; - -typedef struct s_io { - /* Stores information on I/Os given timing constraints. - Used in SDC parsing and timing analysis. */ - char * name; /* I/O port name with an SDC constraint */ - char * clock_name; /* Clock it was constrained on */ - float delay; /* Delay through the I/O in this constraint */ - int file_line_number; /* line in the SDC file I/O was constrained on - used for error reporting */ -} t_io; - -typedef struct s_timing_stats { - /* Timing statistics for final reporting for each constraint - (pair of constrained source and sink clock domains). - - cpd holds the critical path delay, the longest path between the - pair of domains, or equivalently the path with the least slack. - - least_slack holds the slack of the connection with the least slack - over all paths in this constraint, even if this connection is part - of another constraint and has a lower slack from that constraint. - - The "critical path" of the entire design is the path with the least - slack in the constraint with the least slack - (see get_critical_path_delay()). */ - - float ** cpd; - float ** least_slack; -} t_timing_stats; - -typedef struct s_slack { - /* Matrices storing slacks and criticalities of each sink pin on each net - [0..num_nets-1][1..num_pins-1] for both pre- and post-packed netlists. */ - float ** slack; - float ** timing_criticality; -#ifdef PATH_COUNTING - float ** path_criticality; -#endif -} t_slack; - -typedef struct s_override_constraint { - /* A special-case constraint to override the default, calculated, timing constraint. Holds data from - set_clock_groups, set_false_path, set_max_delay, and set_multicycle_path commands. Can hold data for - clock-to-clock, clock-to-flip-flop, flip-flop-to-clock or flip-flop-to-flip-flop constraints, each of - which has its own array (g_sdc->cc_constraints, g_sdc->cf_constraints, g_sdc->fc_constraints, and g_sdc->ff_constraints). */ - char ** source_list; /* Array of net names of flip-flops or clocks */ - char ** sink_list; - int num_source; - int num_sink; - float constraint; - int num_multicycles; - int file_line_number; /* line in the SDC file clock was constrained on - used for error reporting */ -} t_override_constraint; - -typedef struct s_timing_constraints { /* Container structure for all SDC timing constraints. - See top-level comment to read_sdc.c for details on members. */ - int num_constrained_clocks; /* number of clocks with timing constraints */ - t_clock * constrained_clocks; /* [0..g_sdc->num_constrained_clocks - 1] array of clocks with timing constraints */ - - float ** domain_constraint; /* [0..num_constrained_clocks - 1 (source)][0..num_constrained_clocks - 1 (destination)] */ - - int num_constrained_inputs; /* number of inputs with timing constraints */ - t_io * constrained_inputs; /* [0..num_constrained_inputs - 1] array of inputs with timing constraints */ - - int num_constrained_outputs; /* number of outputs with timing constraints */ - t_io * constrained_outputs; /* [0..num_constrained_outputs - 1] array of outputs with timing constraints */ - - int num_cc_constraints; /* number of special-case clock-to-clock constraints overriding default, calculated, timing constraints */ - t_override_constraint * cc_constraints; /* [0..num_cc_constraints - 1] array of such constraints */ - - int num_cf_constraints; /* number of special-case clock-to-flipflop constraints */ - t_override_constraint * cf_constraints; /* [0..num_cf_constraints - 1] array of such constraints */ - - int num_fc_constraints; /* number of special-case flipflop-to-clock constraints */ - t_override_constraint * fc_constraints; /* [0..num_fc_constraints - 1] */ - - int num_ff_constraints; /* number of special-case flipflop-to-flipflop constraints */ - t_override_constraint * ff_constraints; /* [0..num_ff_constraints - 1] array of such constraints */ -} t_timing_constraints; - -/*************************************************************************** - * Placement and routing data types - ****************************************************************************/ - -/* Timing data structures end */ -enum sched_type { - AUTO_SCHED, USER_SCHED -}; -/* Annealing schedule */ - -enum pic_type { - NO_PICTURE, PLACEMENT, ROUTING -}; -/* What's on screen? */ - -/* Map netlist to FPGA or timing analyze only */ -enum e_operation { - RUN_FLOW, TIMING_ANALYSIS_ONLY -}; - -enum pfreq { - PLACE_NEVER, PLACE_ONCE, PLACE_ALWAYS -}; - -/* Are the pads free to be moved, locked in a random configuration, or * - * locked in user-specified positions? */ -enum e_pad_loc_type { - FREE, RANDOM, USER -}; - -/* Power data for t_net structure */ -struct s_net_power { - /* Signal probability - long term probability that signal is logic-high*/ - float probability; - - /* Transistion density - average # of transitions per clock cycle - * For example, a clock would have density = 2 - */ - float density; -}; - -/* name: ASCII net name for informative annotations in the output. * - * num_sinks: Number of sinks on this net. * - * node_block: [0..num_sinks]. Contains the blocks to which the nodes of this - * net connect. The source block is node_block[0] and the sink blocks - * are the remaining nodes. - * node_block_port: [0..num_sinks]. Contains port index (on a block) to - * which each net terminal connects. - * node_block_pin: [0..num_sinks]. Contains the index of the pin (on a block) to - * which each net terminal connects. - * is_global: not routed - * is_const_gen: constant generator (does not affect timing) */ -typedef struct s_net { - char *name; - int num_sinks; - int *node_block; - int *node_block_port; - int *node_block_pin; - boolean is_global; - boolean is_const_gen; - t_net_power * net_power; - /* Xifan TANG: SPICE modeling */ - t_spice_net_info* spice_net_info; - /* Xifan TANG: CLB_IPIN_REMAP */ - int** prefer_side; /* [0..num_sinks][0..3] */ - /* Xifan TANG: OPIN occupancy stats */ - int num_mapped_opins; -} t_net; - -/* s_grid_tile is the minimum tile of the fpga - * type: Pointer to type descriptor, NULL for illegal, IO_TYPE for io - * offset: Number of grid tiles above the bottom location of a block - * usage: Number of blocks used in this grid tile - * blocks[]: Array of logical blocks placed in a physical position, EMPTY means - no block at that index */ -typedef struct s_grid_tile { - t_type_ptr type; - int offset; - int usage; - int *blocks; -} t_grid_tile; - -/* Stores the bounding box of a net in terms of the minimum and * - * maximum coordinates of the blocks forming the net, clipped to * - * the region (1..nx, 1..ny). */ -typedef struct s_bb t_bb; -struct s_bb { - int xmin; - int xmax; - int ymin; - int ymax; -}; - -/* capacity: Capacity of this region, in tracks. * - * occupancy: Expected number of tracks that will be occupied. * - * cost: Current cost of this usage. */ -struct s_place_region { - float capacity; - float inv_capacity; - float occupancy; - float cost; -}; - -/* - Represents a clustered logic block of a user circuit that fits into one unit of space in an FPGA grid block - name: identifier for this block - type: the type of physical block this user circuit block can map into - nets: nets that connect to other user circuit blocks - x: x-coordinate - y: y-coordinate - z: occupancy coordinate - pb: Physical block representing the clustering of this CLB - isFixed: TRUE if this block's position is fixed by the user and shouldn't be moved during annealing - */ -struct s_block { - char *name; - t_type_ptr type; - int *nets; - int x; - int y; - int z; - - /* Xifan TANG: CLB_IPIN_REMAP */ - int* nets_sink_index; - int** pin_prefer_side; /* [0..num_pins-1][0..3] */ - - t_pb *pb; - - /* Xifan TANG: FPGA-SPICE - * pb for physical model - */ - void* phy_pb; - - boolean isFixed; - -}; -typedef struct s_block t_block; - -/* Names of various files */ -struct s_file_name_opts { - char *ArchFile; - char *CircuitName; - char *BlifFile; - char *NetFile; - char *PlaceFile; - char *RouteFile; - char *ActFile; - char *PowerFile; - char *CmosTechFile; - char *out_file_prefix; - /* For shell-like interface */ - char *SDCFile; -}; - -/* Options for packing - * TODO: document each packing parameter */ -enum e_packer_algorithm { - PACK_GREEDY, PACK_BRUTE_FORCE -}; - -struct s_packer_opts { - char *blif_file_name; - char *sdc_file_name; - char *output_file; - boolean global_clocks; - boolean hill_climbing_flag; - boolean sweep_hanging_nets_and_inputs; - boolean timing_driven; - enum e_cluster_seed cluster_seed_type; - float alpha; - float beta; - int recompute_timing_after; - float block_delay; - float intra_cluster_net_delay; - float inter_cluster_net_delay; - boolean auto_compute_inter_cluster_net_delay; - boolean skip_clustering; - boolean allow_unrelated_clustering; - boolean allow_early_exit; - boolean connection_driven; - boolean doPacking; - enum e_packer_algorithm packer_algorithm; - float aspect; - /* Xifan TANG: PACK_CLB_PIN_REMAP */ - boolean pack_clb_pin_remap; - /* END */ -}; - -/* Annealing schedule information for the placer. The schedule type * - * is either USER_SCHED or AUTO_SCHED. Inner_num is multiplied by * - * num_blocks^4/3 to find the number of moves per temperature. The * - * remaining information is used only for USER_SCHED, and have the * - * obvious meanings. */ -struct s_annealing_sched { - enum sched_type type; - float inner_num; - float init_t; - float alpha_t; - float exit_t; -}; - -enum e_place_algorithm { - BOUNDING_BOX_PLACE, NET_TIMING_DRIVEN_PLACE, PATH_TIMING_DRIVEN_PLACE -}; - -struct s_placer_opts { - enum e_place_algorithm place_algorithm; - float timing_tradeoff; - int block_dist; - float place_cost_exp; - int place_chan_width; - enum e_pad_loc_type pad_loc_type; - char *pad_loc_file; - enum pfreq place_freq; - int recompute_crit_iter; - boolean enable_timing_computations; - int inner_loop_recompute_divider; - float td_place_exp_first; - int seed; - float td_place_exp_last; - boolean doPlacement; - /* Xifan TANG: CLB_PIN_REMAP */ - boolean place_clb_pin_remap; - /* END */ -}; - -/* Various options for the placer. * - * place_algorithm: BOUNDING_BOX_PLACE or NET_TIMING_DRIVEN_PLACE, or * - * PATH_TIMING_DRIVEN_PLACE * - * timing_tradeoff: When TIMING_DRIVEN_PLACE mode, what is the tradeoff * - * timing driven and BOUNDING_BOX_PLACE. * - * block_dist: Initial guess of how far apart blocks on the critical path * - * This is used to compute the initial slacks and criticalities * - * place_cost_exp: Power to which denominator is raised for linear_cong. * - * place_chan_width: The channel width assumed if only one placement is * - * performed. * - * pad_loc_type: Are pins FREE, fixed randomly, or fixed from a file. * - * pad_loc_file: File to read pin locations form if pad_loc_type * - * is USER. * - * place_freq: Should the placement be skipped, done once, or done for each * - * channel width in the binary search. * - * recompute_crit_iter: how many temperature stages pass before we recompute * - * criticalities based on average point to point delay * - * enable_timing_computations: in bounding_box mode, normally, timing * - * information is not produced, this causes the information * - * to be computed. in *_TIMING_DRIVEN modes, this has no effect* - * inner_loop_crit_divider: (move_lim/inner_loop_crit_divider) determines how* - * many inner_loop iterations pass before a recompute of * - * criticalities is done. * - * td_place_exp_first: exponent that is used on the timing_driven criticlity * - * it is the value that the exponent starts at. * - * td_place_exp_last: value that the criticality exponent will be at the end * - * doPlacement: TRUE if placement is supposed to be done in the CAD flow, FALSE otherwise */ - -enum e_route_type { - GLOBAL, DETAILED -}; -enum e_router_algorithm { - BREADTH_FIRST, TIMING_DRIVEN, NO_TIMING -}; -enum e_base_cost_type { - INTRINSIC_DELAY, DELAY_NORMALIZED, DEMAND_ONLY -}; - -#define NO_FIXED_CHANNEL_WIDTH -1 - -typedef struct s_router_opts t_router_opts; -struct s_router_opts { - float first_iter_pres_fac; - float initial_pres_fac; - float pres_fac_mult; - float acc_fac; - float bend_cost; - int max_router_iterations; - int bb_factor; - enum e_route_type route_type; - int fixed_channel_width; - enum e_router_algorithm router_algorithm; - enum e_base_cost_type base_cost_type; - float astar_fac; - float max_criticality; - float criticality_exp; - boolean verify_binary_search; - boolean full_stats; - boolean doRouting; - /* Xifan Tang: option to enable adaption to tileable route channel width */ - boolean use_tileable_route_chan_width; -}; - -/* All the parameters controlling the router's operation are in this * - * structure. * - * first_iter_pres_fac: Present sharing penalty factor used for the * - * very first (congestion mapping) Pathfinder iteration. * - * initial_pres_fac: Initial present sharing penalty factor for * - * Pathfinder; used to set pres_fac on 2nd iteration. * - * pres_fac_mult: Amount by which pres_fac is multiplied each * - * routing iteration. * - * acc_fac: Historical congestion cost multiplier. Used unchanged * - * for all iterations. * - * bend_cost: Cost of a bend (usually non-zero only for global routing). * - * max_router_iterations: Maximum number of iterations before giving * - * up. * - * bb_factor: Linear distance a route can go outside the net bounding * - * box. * - * route_type: GLOBAL or DETAILED. * - * fixed_channel_width: Only attempt to route the design once, with the * - * channel width given. If this variable is * - * == NO_FIXED_CHANNEL_WIDTH, do a binary search * - * on channel width. * - * router_algorithm: BREADTH_FIRST or TIMING_DRIVEN. Selects the desired * - * routing algorithm. * - * base_cost_type: Specifies how to compute the base cost of each type of * - * rr_node. INTRINSIC_DELAY -> base_cost = intrinsic delay * - * of each node. DELAY_NORMALIZED -> base_cost = "demand" * - * x average delay to route past 1 CLB. DEMAND_ONLY -> * - * expected demand of this node (old breadth-first costs). * - * * - * The following parameters are used only by the timing-driven router. * - * * - * astar_fac: Factor (alpha) used to weight expected future costs to * - * target in the timing_driven router. astar_fac = 0 leads to * - * an essentially breadth-first search, astar_fac = 1 is near * - * the usual astar algorithm and astar_fac > 1 are more * - * aggressive. * - * max_criticality: The maximum criticality factor (from 0 to 1) any sink * - * will ever have (i.e. clip criticality to this number). * - * criticality_exp: Set criticality to (path_length(sink) / longest_path) ^ * - * criticality_exp (then clip to max_criticality). - * doRouting: True if routing is supposed to be done, FALSE otherwise */ - -typedef struct s_det_routing_arch t_det_routing_arch; -struct s_det_routing_arch { - enum e_directionality directionality; /* UDSD by AY */ - int Fs; - enum e_switch_block_type switch_block_type; - int sub_Fs; - boolean wire_opposite_side; - enum e_switch_block_type switch_block_sub_type; - int num_segment; - short num_switch; - short global_route_switch; - short delayless_switch; - short wire_to_ipin_switch; - float R_minW_nmos; - float R_minW_pmos; - int num_swseg_pattern; /*Xifan TANG: Switch Segment Pattern Support*/ - short opin_to_wire_switch; /* mrFPGA: Xifan TANG*/ - bool tileable; /* Xifan Tang: tileable rr_graph support */ -}; - -/* Defines the detailed routing architecture of the FPGA. Only important * - * if the route_type is DETAILED. * - * (UDSD by AY) directionality: Should the tracks be uni-directional or * - * bi-directional? * - * switch_block_type: Pattern of switches at each switch block. I * - * assume Fs is always 3. If the type is SUBSET, I use a * - * Xilinx-like switch block where track i in one channel always * - * connects to track i in other channels. If type is WILTON, * - * I use a switch block where track i does not always connect * - * to track i in other channels. See Steve Wilton, Phd Thesis, * - * University of Toronto, 1996. The UNIVERSAL switch block is * - * from Y. W. Chang et al, TODAES, Jan. 1996, pp. 80 - 101. * - * num_segment: Number of distinct segment types in the FPGA. * - * num_switch: Number of distinct switch types (pass transistors or * - * buffers) in the FPGA. * - * delayless_switch: Index of a zero delay switch (used to connect things * - * that should have no delay). * - * wire_to_ipin_switch: Index of a switch used to connect wire segments * - * to clb or pad input pins (IPINs). * - * R_minW_nmos: Resistance (in Ohms) of a minimum width nmos transistor. * - * Used only in the FPGA area model. * - * R_minW_pmos: Resistance (in Ohms) of a minimum width pmos transistor. */ - -enum e_drivers { - MULTI_BUFFERED, SINGLE -}; -/* legacy routing drivers by Andy Ye (remove or integrate in future) */ - -enum e_direction { - INC_DIRECTION = 0, DEC_DIRECTION = 1, BI_DIRECTION = 2 -}; -/* UDSD by AY */ - -typedef struct s_seg_details { - int length; - int start; - boolean longline; - boolean *sb; - boolean *cb; - short wire_switch; - short opin_switch; - float Rmetal; - float Cmetal; - boolean twisted; - enum e_direction direction; /* UDSD by AY */ - enum e_drivers drivers; /* UDSD by AY */ - int group_start; - int group_size; - int index; - float Cmetal_per_m; /* Used for power */ - /* mrFPGA */ - short seg_switch; - /* end */ -} t_seg_details; - -/* Lists detailed information about segmentation. [0 .. W-1]. * - * length: length of segment. * - * start: index at which a segment starts in channel 0. * - * longline: TRUE if this segment spans the entire channel. * - * sb: [0..length]: TRUE for every channel intersection, relative to the * - * segment start, at which there is a switch box. * - * cb: [0..length-1]: TRUE for every logic block along the segment at * - * which there is a connection box. * - * wire_switch: Index of the switch type that connects other wires *to* * - * this segment. * - * opin_switch: Index of the switch type that connects output pins (OPINs) * - * *to* this segment. * - * Cmetal: Capacitance of a routing track, per unit logic block length. * - * Rmetal: Resistance of a routing track, per unit logic block length. * - * (UDSD by AY) direction: The direction of a routing track. * - * (UDSD by AY) drivers: How do signals driving a routing track connect to * - * the track? * - * index: index of the segment type used for this track. */ -typedef struct s_linked_f_pointer t_linked_f_pointer; -struct s_linked_f_pointer { - struct s_linked_f_pointer *next; - float *fptr; -}; - -/* A linked list of float pointers. Used for keeping track of * - * which pathcosts in the router have been changed. */ - -/* Uncomment lines below to save some memory, at the cost of debugging ease. */ -/*enum e_rr_type {SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}; */ -/* typedef short t_rr_type */ - -typedef enum e_rr_type { - SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES -} t_rr_type; - -constexpr std::array rr_node_typename { { - "SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY", "INTRA_CLUSTER_EDGE", "NUM_RR_TYPES" -} }; - -/* Type of a routing resource node. x-directed channel segment, * - * y-directed channel segment, input pin to a clb to pad, output * - * from a clb or pad (i.e. output pin of a net) and: * - * SOURCE: A dummy node that is a logical output within a block * - * -- i.e., the gate that generates a signal. * - * SINK: A dummy node that is a logical input within a block * - * -- i.e. the gate that needs a signal. */ - -typedef struct s_trace { - int index; - short iswitch; - int iblock; - int num_siblings; - struct s_trace *next; -} t_trace; - -/* Basic element used to store the traceback (routing) of each net. * - * index: Array index (ID) of this routing resource node. * - * iswitch: Index of the switch type used to go from this rr_node to * - * the next one in the routing. OPEN if there is no next node * - * (i.e. this node is the last one (a SINK) in a branch of the * - * net's routing). * - * iblock: Index of block that this trace applies to if applicable, OPEN * - * otherwise * - * num_siblings: Number of traceback sibling nodes (including self). This * - * count is used to help extract individual route paths for * - * each net. A '0' indicates a terminal node, '1' means a * - * single child, '+1' defines branch with 2 or more children.* - * next: Pointer to the next traceback element in this route. */ - -#define NO_PREVIOUS -1 - -typedef struct s_rr_node t_rr_node; -struct s_rr_node { - short xlow; - short xhigh; - short ylow; - short yhigh; - - short ptc_num; - std::vector track_ids; /* Tileable arch support: Track indices in each GSB */ - - short cost_index; - short occ; - short capacity; - short fan_in; - short num_edges; - t_rr_type type; - int *edges; - short *switches; - - short driver_switch; /* Xifan TANG: Switch Segment Pattern Support*/ - int unbuf_switched; /* Xifan TANG: Switch Segment Pattern Support*/ - /* mrFPGA: Xifan TANG */ - int buffered; - /* end */ - float R; - float C; - - enum e_direction direction; /* UDSD by AY */ - enum e_drivers drivers; /* UDSD by AY */ - int num_wire_drivers; /* UDSD by WMF */ - int num_opin_drivers; /* UDSD by WMF (could use "short") */ - /* Xifan TANG: SPICE model support */ - int num_drive_rr_nodes; - t_rr_node** drive_rr_nodes; - int* drive_switches; - /* Xifan TANG: for parasitic net estimation */ - boolean vpack_net_num_changed; - boolean is_parasitic_net; - /* Xifan TANG: pb_pin_eq_auto_detect support */ - boolean is_in_heap; - /* SPECIAL: For switch box muxes */ - int sb_num_drive_rr_nodes; - t_rr_node** sb_drive_rr_nodes; - int* sb_drive_switches; - t_pb* pb; - /* BC: Supports SDC for SBs/CBs. PBs use the one inside of the pb_graph*/ - char* name_mux; - int id_path; - // int seg_index; /* Valid only for CHANX or CHANY*/ - /* END */ - - /* Used by clustering only (TODO, may wish to extend to regular router) */ - int prev_node; - int prev_edge; - int net_num; - int vpack_net_num; - /* Note that prev_node changes after routing!!! - * because logic equivalent pins may swap with each other!!! */ - /* Xifan TANG: I backup the results in packing here, - * and keep prev_node&prev_edge well correspond to routing results!*/ - int prev_node_in_pack; - int prev_edge_in_pack; - int net_num_in_pack; - /* END */ - t_pb_graph_pin *pb_graph_pin; - t_tnode *tnode; - float pack_intrinsic_cost; - - int z; /* For IPIN, source, and sink nodes, helps identify which location this rr_node belongs to */ -}; -/* Main structure describing one routing resource node. Everything in * - * this structure should describe the graph -- information needed only * - * to store algorithm-specific data should be stored in one of the * - * parallel rr_node_?? structures. * - * * - * xlow, xhigh, ylow, yhigh: Integer coordinates (see route.c for * - * coordinate system) of the ends of this routing resource. * - * xlow = xhigh and ylow = yhigh for pins or for segments of * - * length 1. These values are used to decide whether or not this * - * node should be added to the expansion heap, based on things * - * like whether it's outside the net bounding box or is moving * - * further away from the target, etc. * - * type: What is this routing resource? * - * ptc_num: Pin, track or class number, depending on rr_node type. * - * Needed to properly draw. * - * cost_index: An integer index into the table of routing resource indexed * - * data (this indirection allows quick dynamic changes of rr * - * base costs, and some memory storage savings for fields that * - * have only a few distinct values). * - * occ: Current occupancy (usage) of this node. * - * capacity: Capacity of this node (number of routes that can use it). * - * num_edges: Number of edges exiting this node. That is, the number * - * of nodes to which it connects. * - * edges[0..num_edges-1]: Array of indices of the neighbours of this * - * node. * - * switches[0..num_edges-1]: Array of switch indexes for each of the * - * edges leaving this node. * - * * - * The following parameters are only needed for timing analysis. * - * R: Resistance to go through this node. This is only metal * - * resistance (end to end, so conservative) -- it doesn't include the * - * switch that leads to another rr_node. * - * C: Total capacitance of this node. Includes metal capacitance, the * - * input capacitance of all switches hanging off the node, the * - * output capacitance of all switches to the node, and the connection * - * box buffer capacitances hanging off it. * - * (UDSD by AY) direction: if the node represents a track, this field * - * indicates the direction of the track. Otherwise * - * the value contained in the field should be * - * ignored. * - * (UDSD by AY) drivers: if the node represents a track, this field * - * indicates the driving architecture of the track. * - * Otherwise the value contained in the field should * - * be ignored. */ - -typedef struct s_rr_indexed_data { - float base_cost; - float saved_base_cost; - int ortho_cost_index; - int seg_index; - float inv_length; - float T_linear; - float T_quadratic; - float C_load; - - - /* Power Estimation: Wire capacitance in (Farads * tiles / meter) - * This is used to calculate capacitance of this segment, by - * multiplying it by the length per tile (meters/tile). - * This is only the wire capacitance, not including any switches */ - float C_tile_per_m; -} t_rr_indexed_data; - -/* Data that is pointed to by the .cost_index member of t_rr_node. It's * - * purpose is to store the base_cost so that it can be quickly changed * - * and to store fields that have only a few different values (like * - * seg_index) or whose values should be an average over all rr_nodes of a * - * certain type (like T_linear etc., which are used to predict remaining * - * delay in the timing_driven router). * - * * - * base_cost: The basic cost of using an rr_node. * - * ortho_cost_index: The index of the type of rr_node that generally * - * connects to this type of rr_node, but runs in the * - * orthogonal direction (e.g. vertical if the direction * - * of this member is horizontal). * - * seg_index: Index into segment_inf of this segment type if this type of * - * rr_node is an CHANX or CHANY; OPEN (-1) otherwise. * - * inv_length: 1/length of this type of segment. * - * T_linear: Delay through N segments of this type is N * T_linear + N^2 * * - * T_quadratic. For buffered segments all delay is T_linear. * - * T_quadratic: Dominant delay for unbuffered segments, 0 for buffered * - * segments. * - * C_load: Load capacitance seen by the driver for each segment added to * - * the chain driven by the driver. 0 for buffered segments. */ - -enum e_cost_indices { - SOURCE_COST_INDEX = 0, - SINK_COST_INDEX, - OPIN_COST_INDEX, - IPIN_COST_INDEX, - CHANX_COST_INDEX_START -}; - -/* Xifan Tang: Move this struct from rr_graph.c to here - * This is a general representation on clb_to_clb_directs - */ -typedef struct s_clb_to_clb_directs { - t_type_descriptor *from_clb_type; - int from_clb_pin_start_index; - int from_clb_pin_end_index; - t_type_descriptor *to_clb_type; - int to_clb_pin_start_index; - int to_clb_pin_end_index; - /* Aurelien: point to point support in direct connection from directlist */ - enum e_point2point_interconnection_type interconnection_type; - enum e_point2point_interconnection_dir x_dir; - enum e_point2point_interconnection_dir y_dir; - /* Xifan Tang: add useful addition info to this struct */ - int x_offset; - int y_offset; - int z_offset; - t_spice_model* spice_model; - CircuitModelId circuit_model; - char* name; -} t_clb_to_clb_directs; - - -/* Gives the index of the SOURCE, SINK, OPIN, IPIN, etc. member of * - * rr_indexed_data. */ - -/* Xifan TANG: For better modeling of global routing architecture */ -/* Information for each switch block */ -typedef struct s_sb t_sb; -struct s_sb { - /* Coordinators */ - int x; - int y; - /* Directionality */ - enum e_directionality directionality; /* UDSD by AY */ - /* Connectivity parameter */ - int fs; - int fc_out; - /* chan_width at each side */ - int num_sides; /* Should be fixed to 4 */ - /* Input/output rr_nodes at each side, according to chan_width - * Each element is a pointer to a rr_node - */ - /* A list of all the rr_nodes at each side, whatever their directionality */ - int* chan_width; - enum PORTS** chan_rr_node_direction; - t_rr_node*** chan_rr_node; - /* LB inputs/outputs */ - int* num_ipin_rr_nodes; /* Switch block has some inputs that are CLB IPIN*/ - t_rr_node*** ipin_rr_node; - int** ipin_rr_node_grid_side; /* We need to record the side of a IPIN, because a IPIN may locate on more than one sides */ - int* num_opin_rr_nodes; /* Connection block has some outputs that are CLB OPIN */ - t_rr_node*** opin_rr_node; - int** opin_rr_node_grid_side; /* We need to record the side of a OPIN, because a OPIN may locate on more than one sides */ - int num_reserved_conf_bits; /* number of reserved configuration bits */ - int conf_bits_lsb; /* LSB of configuration bits */ - int conf_bits_msb; /* MSB of configuration bits */ - - /* For identical SBs */ - t_sb* mirror; /* an exact mirror of this switch block, with same connection & switches */ - /* an rotatable mirror of this switch block, - * the two switch blocks will be same in terms of connection & switches - * by applying an offset to the connection & switches - */ - t_sb* rotatable; - /* Offset to be applied for each side of nodes */ - int* offset_ipin; /* [0, ..., num_sides-1]*/ - int* offset_opin; /* [0, ..., num_sides-1]*/ - int* offset_chan; /* [0, ..., num_sides-1]*/ -}; - -/* Information for each conneciton block */ -typedef struct s_cb t_cb; -struct s_cb { - /* Type of Connection block, can only be either CHANX or CHANY, - * Corresponding to CB connected CHANX/CHANY to a CLB - */ - t_rr_type type; - /* Coordinators */ - int x; - int y; - /* Directionality */ - enum e_directionality directionality; /* UDSD by AY */ - /* Connectivity parameter */ - int fc_in; - /* chan_width at each side */ - int num_sides; /* Should be fixed to 4 */ - /* Input/output rr_nodes at each side, according to chan_width - * Each element is a pointer to a rr_node - */ - /* A list of all the rr_nodes at each side, whatever their directionality */ - int* chan_width; - enum PORTS** chan_rr_node_direction; - t_rr_node*** chan_rr_node; - /* LB inputs/outputs */ - int* num_ipin_rr_nodes; /* Switch block has some inputs that are CLB IPIN*/ - t_rr_node*** ipin_rr_node; - int** ipin_rr_node_grid_side; /* We need to record the side of a IPIN, because a IPIN may locate on more than one sides */ - int* num_opin_rr_nodes; /* Connection block has some outputs that are CLB OPIN */ - t_rr_node*** opin_rr_node; - int** opin_rr_node_grid_side; /* We need to record the side of a OPIN, because a OPIN may locate on more than one sides */ - int num_reserved_conf_bits; /* number of reserved configuration bits */ - int conf_bits_lsb; /* LSB of configuration bits */ - int conf_bits_msb; /* MSB of configuration bits */ - - /* For identical SBs */ - t_cb* mirror; /* an exact mirror of this connection block, with same connection & switches */ - /* an rotatable mirror of this connection block, - * the two connection blocks will be same in terms of connection & switches - * by applying an offset to the connection & switches - */ - t_cb* rotatable; - /* Offset to be applied for each side of nodes */ - int* offset_ipin; /* [0, ..., num_sides-1]*/ - int* offset_opin; /* [0, ..., num_sides-1]*/ - int* offset_chan; /* [0, ..., num_sides-1]*/ -}; - -/* Xifan TANG: SPICE Support*/ -typedef struct s_spice_opts t_spice_opts; -struct s_spice_opts { - boolean do_spice; - boolean fpga_spice_print_top_testbench; - boolean fpga_spice_print_grid_testbench; - boolean fpga_spice_print_cb_testbench; - boolean fpga_spice_print_sb_testbench; - boolean fpga_spice_print_pb_mux_testbench; - boolean fpga_spice_print_cb_mux_testbench; - boolean fpga_spice_print_sb_mux_testbench; - boolean fpga_spice_print_lut_testbench; - boolean fpga_spice_print_hardlogic_testbench; - boolean fpga_spice_print_io_testbench; - boolean fpga_spice_leakage_only; - boolean fpga_spice_parasitic_net_estimation; - boolean fpga_spice_testbench_load_extraction; - - /*Xifan TANG: FPGA SPICE Model Support*/ - char* spice_dir; - char* include_dir; - char* subckt_dir; - - int fpga_spice_sim_multi_thread_num; - char* simulator_path; -}; - -/* Xifan TANG: synthesizable verilog dumping */ -typedef struct s_syn_verilog_opts t_syn_verilog_opts; -struct s_syn_verilog_opts { - boolean dump_syn_verilog; - boolean dump_explicit_verilog; - char* syn_verilog_dump_dir; - boolean print_top_testbench; - boolean print_input_blif_testbench; - boolean print_formal_verification_top_netlist; - boolean include_timing; - boolean include_signal_init; - boolean include_icarus_simulator; - boolean print_modelsim_autodeck; - char* modelsim_ini_path; - char* report_timing_path; - boolean print_user_defined_template; - boolean print_autocheck_top_testbench; - char* reference_verilog_benchmark_file; - boolean print_report_timing_tcl; - boolean print_sdc_pnr; - boolean print_sdc_analysis; - boolean print_simulation_ini; - char* simulation_ini_path; -}; - -/* Xifan TANG: bitstream generator */ -typedef struct s_bitstream_gen_opts t_bitstream_gen_opts; -struct s_bitstream_gen_opts { - boolean gen_bitstream; - char* bitstream_output_file; -}; - -typedef struct s_fpga_spice_opts t_fpga_spice_opts; -struct s_fpga_spice_opts { - boolean do_fpga_spice; - boolean read_act_file; - boolean rename_illegal_port; /* Rename illegal port names that is not compatible with verilog/SPICE syntax */ - t_spice_opts SpiceOpts; /* Xifan TANG: SPICE Support*/ - t_syn_verilog_opts SynVerilogOpts; /* Xifan TANG: Synthesizable verilog dumping*/ - t_bitstream_gen_opts BitstreamGenOpts; /* Xifan Bitsteam Generator */ - - boolean compact_routing_hierarchy; /* use compact routing hierarchy */ - boolean duplicate_grid_pin; /* Duplicate pins at each side of the grid */ - - /* Signal Density */ - float signal_density_weight; - float sim_window_size; - /* SB XML file prefix */ - boolean output_sb_xml; - char* sb_xml_dir; -}; - -/* Power estimation options */ -struct s_power_opts { - boolean do_power; /* Perform power estimation? */ -}; - -/* Type to store our list of token to enum pairings */ -struct s_TokenPair { - const char *Str; - int Enum; -}; - -/* Store settings for VPR */ -typedef struct s_vpr_setup { - boolean TimingEnabled; /* Is VPR timing enabled */ - struct s_file_name_opts FileNameOpts; /* File names */ - enum e_operation Operation; /* run VPR or do analysis only */ - t_model * user_models; /* blif models defined by the user */ - t_model * library_models; /* blif models in VPR */ - struct s_packer_opts PackerOpts; /* Options for packer */ - struct s_placer_opts PlacerOpts; /* Options for placer */ - struct s_annealing_sched AnnealSched; /* Placement option annealing schedule */ - struct s_router_opts RouterOpts; /* router options */ - struct s_det_routing_arch RoutingArch; /* routing architecture */ - t_segment_inf * Segments; /* wires in routing architecture */ - t_swseg_pattern_inf* swseg_patterns; /* Xifan TANG: Switch Segment Pattern Support */ - t_timing_inf Timing; /* timing information */ - float constant_net_delay; /* timing information when place and route not run */ - boolean ShowGraphics; /* option to show graphics */ - int GraphPause; /* user interactiveness graphics option */ - t_power_opts PowerOpts; - t_fpga_spice_opts FPGA_SPICE_Opts; /* Xifan TANG: FPGA-SPICE support */ -} t_vpr_setup; - -#endif - diff --git a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh deleted file mode 100755 index 8df9df422..000000000 --- a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh +++ /dev/null @@ -1,2 +0,0 @@ -rm tags -ctags -R shell_main.c main.c ./* ../../libarchfpgavpr7/SRC/* ../../libpcre/SRC/*.[ch] ../../../libs/libvtrutil/src/* diff --git a/vpr7_x2p/vpr/SRC/device/decoder_library.cpp b/vpr7_x2p/vpr/SRC/device/decoder_library.cpp deleted file mode 100644 index ba869712f..000000000 --- a/vpr7_x2p/vpr/SRC/device/decoder_library.cpp +++ /dev/null @@ -1,104 +0,0 @@ -/*************************************************************************************** - * This file includes memeber functions for data structure DecoderLibrary - **************************************************************************************/ -#include "vtr_assert.h" -#include "decoder_library.h" - -/*************************************************************************************** - * Public Accessors: Aggregators - **************************************************************************************/ -DecoderLibrary::decoder_range DecoderLibrary::decoders() const { - return vtr::make_range(decoder_ids_.begin(), decoder_ids_.end()); -} - -/*************************************************************************************** - * Public Accessors: Data query - **************************************************************************************/ -/* Get the size of address input of a decoder */ -size_t DecoderLibrary::addr_size(const DecoderId& decoder) const { - VTR_ASSERT_SAFE(valid_decoder_id(decoder)); - return addr_sizes_[decoder]; -} - -/* Get the size of data output of a decoder */ -size_t DecoderLibrary::data_size(const DecoderId& decoder) const { - VTR_ASSERT_SAFE(valid_decoder_id(decoder)); - return data_sizes_[decoder]; -} - -/* Get the flag if a decoder includes an ENABLE signal */ -bool DecoderLibrary::use_enable(const DecoderId& decoder) const { - VTR_ASSERT_SAFE(valid_decoder_id(decoder)); - return use_enable_[decoder]; -} - -/* Get the flag if a decoder includes an DATA_IN signal */ -bool DecoderLibrary::use_data_in(const DecoderId& decoder) const { - VTR_ASSERT_SAFE(valid_decoder_id(decoder)); - return use_data_in_[decoder]; -} - -/* Get the flag if a decoder includes a data_inv port which is an inversion of the regular data output port */ -bool DecoderLibrary::use_data_inv_port(const DecoderId& decoder) const { - VTR_ASSERT_SAFE(valid_decoder_id(decoder)); - return use_data_inv_port_[decoder]; -} - -/* Find a decoder to the library, with the specification. - * If found, return the id of decoder. - * If not found, return an invalid id of decoder - * To avoid duplicated decoders, this function should be used before adding a decoder - * Example: - * DecoderId decoder_id == decoder_lib.find_decoder(); - * if (DecoderId::INVALID() == decoder_id) { - * // Add decoder - * } - */ -DecoderId DecoderLibrary::find_decoder(const size_t& addr_size, - const size_t& data_size, - const bool& use_enable, - const bool& use_data_in, - const bool& use_data_inv_port) const { - for (auto decoder : decoders()) { - if ( (addr_size == addr_sizes_[decoder]) - && (data_size == data_sizes_[decoder]) - && (use_enable == use_enable_[decoder]) - && (use_data_in == use_data_in_[decoder]) - && (use_data_inv_port == use_data_inv_port_[decoder]) ) { - return decoder; - } - } - - /* Not found, return an invalid id by default */ - return DecoderId::INVALID(); -} - -/*************************************************************************************** - * Public Validators - **************************************************************************************/ -/* Validate ids */ -bool DecoderLibrary::valid_decoder_id(const DecoderId& decoder) const { - return size_t(decoder) < decoder_ids_.size() && decoder_ids_[decoder] == decoder; -} - -/*************************************************************************************** - * Public Mutators : Basic Operations - **************************************************************************************/ -/* Add a decoder to the library */ -DecoderId DecoderLibrary::add_decoder(const size_t& addr_size, - const size_t& data_size, - const bool& use_enable, - const bool& use_data_in, - const bool& use_data_inv_port) { - DecoderId decoder = DecoderId(decoder_ids_.size()); - /* Push to the decoder list */ - decoder_ids_.push_back(decoder); - /* Resize the other related vectors */ - addr_sizes_.push_back(addr_size); - data_sizes_.push_back(data_size); - use_enable_.push_back(use_enable); - use_data_in_.push_back(use_data_in); - use_data_inv_port_.push_back(use_data_inv_port); - - return decoder; -} diff --git a/vpr7_x2p/vpr/SRC/device/decoder_library.h b/vpr7_x2p/vpr/SRC/device/decoder_library.h deleted file mode 100644 index c8eb1da7e..000000000 --- a/vpr7_x2p/vpr/SRC/device/decoder_library.h +++ /dev/null @@ -1,88 +0,0 @@ -/*************************************************************************************** - * This file includes key data structures to describe decoders which are used - * in FPGA fabrics - * A decoder is a circuit to convert a binary input to one-hot codes - * The outputs are assumes to be one-hot codes (at most only one '1' exist) - * Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2)) - * All the decoders are assumed to follow the port map : - * - * Inputs - * | | ... | - * v v v - * +-----------+ - * / \ - * / Decoder \ - * +-----------------+ - * | | | ... | | | - * v v v v v v - * Outputs - - ***************************************************************************************/ - -#ifndef DECODER_LIBRARY_H -#define DECODER_LIBRARY_H - -#include "vtr_vector.h" -#include "vtr_range.h" -#include "decoder_library_fwd.h" - -class DecoderLibrary { - public: /* Types and ranges */ - typedef vtr::vector::const_iterator decoder_iterator; - - typedef vtr::Range decoder_range; - - public: /* Public accessors: Aggregates */ - /* Get all the decoders */ - decoder_range decoders() const; - - public: /* Public accessors: Data query */ - /* Get the size of address input of a decoder */ - size_t addr_size(const DecoderId& decoder) const; - /* Get the size of data output of a decoder */ - size_t data_size(const DecoderId& decoder) const; - /* Get the flag if a decoder includes an ENABLE signal */ - bool use_enable(const DecoderId& decoder) const; - /* Get the flag if a decoder includes an DATA_IN signal */ - bool use_data_in(const DecoderId& decoder) const; - /* Get the flag if a decoder includes a data_inv port which is an inversion of the regular data output port */ - bool use_data_inv_port(const DecoderId& decoder) const; - /* Find a decoder to the library, with the specification. - * If found, return the id of decoder. - * If not found, return an invalid id of decoder - * To avoid duplicated decoders, this function should be used before adding a decoder - * Example: - * DecoderId decoder_id == decoder_lib.find_decoder(); - * if (DecoderId::INVALID() == decoder_id) { - * // Add decoder - * } - */ - DecoderId find_decoder(const size_t& addr_size, - const size_t& data_size, - const bool& use_enable, - const bool& use_data_in, - const bool& use_data_inv_port) const; - - public: /* Public validators */ - /* valid ids */ - bool valid_decoder_id(const DecoderId& decoder) const; - - public: /* Private mutators : basic operations */ - /* Add a decoder to the library */ - DecoderId add_decoder(const size_t& addr_size, - const size_t& data_size, - const bool& use_enable, - const bool& use_data_in, - const bool& use_data_inv_port); - - private: /* Internal Data */ - vtr::vector decoder_ids_; - vtr::vector addr_sizes_; - vtr::vector data_sizes_; - vtr::vector use_enable_; - vtr::vector use_data_in_; - vtr::vector use_data_inv_port_; -}; - -#endif - diff --git a/vpr7_x2p/vpr/SRC/device/decoder_library_fwd.h b/vpr7_x2p/vpr/SRC/device/decoder_library_fwd.h deleted file mode 100644 index 1850dc27a..000000000 --- a/vpr7_x2p/vpr/SRC/device/decoder_library_fwd.h +++ /dev/null @@ -1,18 +0,0 @@ -/************************************************** - * This file includes only declarations for - * the data structures to describe decoders - * Please refer to decoder_library.h for more details - *************************************************/ -#ifndef DECODER_LIBRARY_FWD_H -#define DECODER_LIBRARY_FWD_H - -#include "vtr_strong_id.h" - -/* Strong Ids for MUXes */ -struct decoder_id_tag; - -typedef vtr::StrongId DecoderId; - -class DecoderLibrary; - -#endif diff --git a/vpr7_x2p/vpr/SRC/device/decoder_library_utils.cpp b/vpr7_x2p/vpr/SRC/device/decoder_library_utils.cpp deleted file mode 100644 index 47ec9a9a9..000000000 --- a/vpr7_x2p/vpr/SRC/device/decoder_library_utils.cpp +++ /dev/null @@ -1,55 +0,0 @@ -/*************************************************************************************** - * This file includes most utilized functions for the DecoderLibrary data structure - ***************************************************************************************/ -#include - -#include "vtr_assert.h" - -#include "decoder_library_utils.h" - -/*************************************************************************************** - * NOTE: This function is mainly designed for local decoders inside multiplexers - * Find the size of address lines for a decoder with a given data output size - * Addr lines - * | | ... | - * v v v - * +-----------+ - * / Local \ - * / Decoder \ - * +-----------------+ - * | | | ... | | | - * v v v v v v - * Data outputs - * - * The outputs are assumes to be one-hot codes (at most only one '1' exist) - * Considering this fact, there are only num_of_outputs + 1 conditions to be encoded. - * Therefore, the number of inputs is ceil(log(num_of_outputs+1)/log(2)) - * We plus 1, which is all-zero condition for outputs - ***************************************************************************************/ -size_t find_mux_local_decoder_addr_size(const size_t& data_size) { - /* if data size is 1, it is an corner case for the decoder (addr = 1) */ - if (1 == data_size) { - return 1; - } - VTR_ASSERT (2 <= data_size); - return ceil(log(data_size) / log(2)); -} - -/*************************************************************************************** - * Try to find if the decoder already exists in the library, - * If there is no such decoder, add it to the library - ***************************************************************************************/ -DecoderId add_mux_local_decoder_to_library(DecoderLibrary& decoder_lib, - const size_t data_size) { - size_t addr_size = find_mux_local_decoder_addr_size(data_size); - - DecoderId decoder_id = decoder_lib.find_decoder(addr_size, data_size, false, false, true); - - if (DecoderId::INVALID() == decoder_id) { - /* Add the decoder */ - return decoder_lib.add_decoder(addr_size, data_size, false, false, true); - } - - /* There is already a decoder in the library, return the decoder id */ - return decoder_id; -} diff --git a/vpr7_x2p/vpr/SRC/device/decoder_library_utils.h b/vpr7_x2p/vpr/SRC/device/decoder_library_utils.h deleted file mode 100644 index 100f04da7..000000000 --- a/vpr7_x2p/vpr/SRC/device/decoder_library_utils.h +++ /dev/null @@ -1,16 +0,0 @@ -/*************************************************************************************** - * Header file for most utilized functions for the DecoderLibrary data structure - ***************************************************************************************/ -#ifndef DECODER_LIBRARY_UTILS_H -#define DECODER_LIBRARY_UTILS_H - -#include "decoder_library.h" - -bool need_mux_local_decoder(const size_t& data_size); - -size_t find_mux_local_decoder_addr_size(const size_t& data_size); - -DecoderId add_mux_local_decoder_to_library(DecoderLibrary& decoder_lib, - const size_t data_size); - -#endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp deleted file mode 100644 index b54dcd0c2..000000000 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ /dev/null @@ -1,1252 +0,0 @@ -/************************************************** - * This file includes member functions for the - * data structures in mux_graph.h - *************************************************/ -#include -#include -#include -#include - -#include "util.h" -#include "vtr_assert.h" -#include "mux_utils.h" -#include "mux_graph.h" - -/************************************************** - * Member functions for the class MuxGraph - *************************************************/ - -/************************************************** - * Public Constructors - *************************************************/ - -/* Create an object based on a Circuit Model which is MUX */ -MuxGraph::MuxGraph(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size) { - /* Build the graph for a given multiplexer model */ - build_mux_graph(circuit_lib, circuit_model, mux_size); -} - -/************************************************** - * Private Constructors - *************************************************/ -/* Create an empty graph */ -MuxGraph::MuxGraph() { - return; -} - -/************************************************** - * Public Accessors : Aggregates - *************************************************/ -//Accessors -MuxGraph::node_range MuxGraph::nodes() const { - return vtr::make_range(node_ids_.begin(), node_ids_.end()); -} - -/* Find the non-input nodes */ -std::vector MuxGraph::non_input_nodes() const { - /* Must be an valid graph */ - VTR_ASSERT_SAFE(valid_mux_graph()); - std::vector node_list; - - /* Build the node list, level by level */ - for (size_t level = 0; level < num_node_levels(); ++level) { - for (size_t node_type = 0; node_type < size_t(NUM_MUX_NODE_TYPES); ++node_type) { - /* Bypass any nodes which are not OUTPUT and INTERNAL */ - if (size_t(MUX_INPUT_NODE) == node_type) { - continue; - } - /* Reach here, this is either an OUTPUT or INTERNAL node */ - for (auto node : node_lookup_[level][node_type]) { - node_list.push_back(node); - } - } - } - - return node_list; -} - -MuxGraph::edge_range MuxGraph::edges() const { - return vtr::make_range(edge_ids_.begin(), edge_ids_.end()); -} - -MuxGraph::mem_range MuxGraph::memories() const { - return vtr::make_range(mem_ids_.begin(), mem_ids_.end()); -} - -std::vector MuxGraph::levels() const { - std::vector graph_levels; - for (size_t lvl = 0; lvl < num_levels(); ++lvl) { - graph_levels.push_back(lvl); - } - return graph_levels; -} - -std::vector MuxGraph::node_levels() const { - std::vector graph_levels; - for (size_t lvl = 0; lvl < num_node_levels(); ++lvl) { - graph_levels.push_back(lvl); - } - return graph_levels; -} - -/************************************************** - * Public Accessors: Data query - *************************************************/ - -/* Find the number of inputs in the MUX graph */ -size_t MuxGraph::num_inputs() const { - /* need to check if the graph is valid or not */ - VTR_ASSERT_SAFE(valid_mux_graph()); - /* Sum up the number of INPUT nodes in each level */ - size_t num_inputs = 0; - for (auto node_per_level : node_lookup_) { - num_inputs += node_per_level[MUX_INPUT_NODE].size(); - } - return num_inputs; -} - -/* Return the node ids of all the inputs of the multiplexer */ -std::vector MuxGraph::inputs() const { - std::vector input_nodes; - /* need to check if the graph is valid or not */ - VTR_ASSERT_SAFE(valid_mux_graph()); - /* Add the input nodes in each level */ - for (auto node_per_level : node_lookup_) { - input_nodes.insert(input_nodes.end(), node_per_level[MUX_INPUT_NODE].begin(), node_per_level[MUX_INPUT_NODE].end()); - } - return input_nodes; -} - -/* Find the number of outputs in the MUX graph */ -size_t MuxGraph::num_outputs() const { - /* need to check if the graph is valid or not */ - VTR_ASSERT_SAFE(valid_mux_graph()); - /* Sum up the number of INPUT nodes in each level */ - size_t num_outputs = 0; - for (auto node_per_level : node_lookup_) { - num_outputs += node_per_level[MUX_OUTPUT_NODE].size(); - } - return num_outputs; -} - -/* Return the node ids of all the outputs of the multiplexer */ -std::vector MuxGraph::outputs() const { - std::vector output_nodes; - /* need to check if the graph is valid or not */ - VTR_ASSERT_SAFE(valid_mux_graph()); - /* Add the output nodes in each level */ - for (auto node_per_level : node_lookup_) { - output_nodes.insert(output_nodes.end(), node_per_level[MUX_OUTPUT_NODE].begin(), node_per_level[MUX_OUTPUT_NODE].end()); - } - return output_nodes; -} - -/* Find the edge between two MUX nodes */ -std::vector MuxGraph::find_edges(const MuxNodeId& from_node, const MuxNodeId& to_node) const { - std::vector edges; - - VTR_ASSERT(valid_node_id(from_node)); - VTR_ASSERT(valid_node_id(to_node)); - - for (const auto& edge : node_out_edges_[from_node]) { - for (const auto& cand : edge_sink_nodes_[edge]) { - if (cand == to_node) { - /* This is the wanted edge, add to list */ - edges.push_back(edge); - } - } - } - - return edges; -} - -/* Find the number of levels in the MUX graph */ -size_t MuxGraph::num_levels() const { - /* need to check if the graph is valid or not */ - VTR_ASSERT_SAFE(valid_mux_graph()); - /* The num_levels by definition excludes the level for outputs, so a deduection is applied */ - return node_lookup_.size() - 1; -} - -/* Find the actual number of levels in the MUX graph */ -size_t MuxGraph::num_node_levels() const { - /* need to check if the graph is valid or not */ - VTR_ASSERT_SAFE(valid_mux_graph()); - return node_lookup_.size(); -} - -/* Find the number of configuration memories in the MUX graph */ -size_t MuxGraph::num_memory_bits() const { - /* need to check if the graph is valid or not */ - VTR_ASSERT_SAFE(valid_mux_graph()); - return mem_ids_.size(); -} - -/* Find the number of SRAMs at a level in the MUX graph */ -size_t MuxGraph::num_memory_bits_at_level(const size_t& level) const { - /* need to check if the graph is valid or not */ - VTR_ASSERT_SAFE(valid_level(level)); - VTR_ASSERT_SAFE(valid_mux_graph()); - return mem_lookup_[level].size(); -} - -/* Return memory id at level */ -std::vector MuxGraph::memories_at_level(const size_t& level) const { - /* need to check if the graph is valid or not */ - VTR_ASSERT_SAFE(valid_level(level)); - VTR_ASSERT_SAFE(valid_mux_graph()); - return mem_lookup_[level]; -} - -/* Find the number of nodes at a given level in the MUX graph */ -size_t MuxGraph::num_nodes_at_level(const size_t& level) const { - /* validate the level numbers */ - VTR_ASSERT_SAFE(valid_level(level)); - VTR_ASSERT_SAFE(valid_mux_graph()); - - size_t num_nodes = 0; - for (size_t node_type = 0; node_type < size_t(NUM_MUX_NODE_TYPES); ++node_type) { - num_nodes += node_lookup_[level][node_type].size(); - } - return num_nodes; -} - -/* Find the level of a node */ -size_t MuxGraph::node_level(const MuxNodeId& node) const { - /* validate the node */ - VTR_ASSERT(valid_node_id(node)); - return node_levels_[node]; -} - -/* Find the index of a node at its level */ -size_t MuxGraph::node_index_at_level(const MuxNodeId& node) const { - /* validate the node */ - VTR_ASSERT(valid_node_id(node)); - return node_ids_at_level_[node]; -} - -/* Find the input edges for a node */ -std::vector MuxGraph::node_in_edges(const MuxNodeId& node) const { - /* validate the node */ - VTR_ASSERT(valid_node_id(node)); - return node_in_edges_[node]; -} - -/* Find the input nodes for a edge */ -std::vector MuxGraph::edge_src_nodes(const MuxEdgeId& edge) const { - /* validate the edge */ - VTR_ASSERT(valid_edge_id(edge)); - return edge_src_nodes_[edge]; -} - -/* Find the mem that control the edge */ -MuxMemId MuxGraph::find_edge_mem(const MuxEdgeId& edge) const { - /* validate the edge */ - VTR_ASSERT(valid_edge_id(edge)); - return edge_mem_ids_[edge]; -} - -/* Identify if the edge is controlled by the inverted output of a mem */ -bool MuxGraph::is_edge_use_inv_mem(const MuxEdgeId& edge) const { - /* validate the edge */ - VTR_ASSERT(valid_edge_id(edge)); - return edge_inv_mem_[edge]; -} - -/* Find the sizes of each branch of a MUX */ -std::vector MuxGraph::branch_sizes() const { - std::vector branch; - /* Visit each internal nodes/output nodes and find the the number of incoming edges */ - for (auto node : node_ids_ ) { - /* Bypass input nodes */ - if ( (MUX_OUTPUT_NODE != node_types_[node]) - && (MUX_INTERNAL_NODE != node_types_[node]) ) { - continue; - } - - size_t branch_size = node_in_edges_[node].size(); - - /* make sure the branch size is valid */ - VTR_ASSERT_SAFE(valid_mux_implementation_num_inputs(branch_size)); - - /* Nodes with the same number of incoming edges, indicate the same size of branch circuit */ - std::vector::iterator it; - it = std::find(branch.begin(), branch.end(), branch_size); - /* if already exists a branch with the same size, skip updating the vector */ - if (it != branch.end()) { - continue; - } - branch.push_back(branch_size); - } - - /* Sort the branch by size */ - std::sort(branch.begin(), branch.end()); - - return branch; -} - -/* Find the sizes of each branch of a MUX at a given level */ -std::vector MuxGraph::branch_sizes(const size_t& level) const { - std::vector branch; - /* Visit each internal nodes/output nodes and find the the number of incoming edges */ - for (auto node : node_ids_ ) { - /* Bypass input nodes */ - if ( (MUX_OUTPUT_NODE != node_types_[node]) - && (MUX_INTERNAL_NODE != node_types_[node]) ) { - continue; - } - /* Bypass nodes that is not at the level */ - if ( level != node_levels_[node]) { - continue; - } - - size_t branch_size = node_in_edges_[node].size(); - - /* make sure the branch size is valid */ - VTR_ASSERT_SAFE(valid_mux_implementation_num_inputs(branch_size)); - - /* Nodes with the same number of incoming edges, indicate the same size of branch circuit */ - std::vector::iterator it; - it = std::find(branch.begin(), branch.end(), branch_size); - /* if already exists a branch with the same size, skip updating the vector */ - if (it != branch.end()) { - continue; - } - branch.push_back(branch_size); - } - - /* Sort the branch by size */ - std::sort(branch.begin(), branch.end()); - - return branch; -} - - -/* Build a subgraph from the given node - * The strategy is very simple, we just - * extract a 1-level graph from here - */ -MuxGraph MuxGraph::subgraph(const MuxNodeId& root_node) const { - /* Validate the node */ - VTR_ASSERT_SAFE(this->valid_node_id(root_node)); - - /* Generate an empty graph */ - MuxGraph mux_graph; - - /* A map to record node-to-node mapping from origin graph to subgraph */ - std::map node2node_map; - - /* A map to record edge-to-edge mapping from origin graph to subgraph */ - std::map edge2edge_map; - - /* Add output nodes to subgraph */ - MuxNodeId to_node_subgraph = mux_graph.add_node(MUX_OUTPUT_NODE); - mux_graph.node_levels_[to_node_subgraph] = 1; - mux_graph.node_ids_at_level_[to_node_subgraph] = 0; - mux_graph.node_output_ids_[to_node_subgraph] = MuxOutputId(0); - /* Update the node-to-node map */ - node2node_map[root_node] = to_node_subgraph; - - /* Add input nodes and edges to subgraph */ - size_t input_cnt = 0; - for (auto edge_origin : this->node_in_edges_[root_node]) { - VTR_ASSERT_SAFE(1 == edge_src_nodes_[edge_origin].size()); - /* Add nodes */ - MuxNodeId from_node_origin = this->edge_src_nodes_[edge_origin][0]; - MuxNodeId from_node_subgraph = mux_graph.add_node(MUX_INPUT_NODE); - /* Configure the nodes */ - mux_graph.node_levels_[from_node_subgraph] = 0; - mux_graph.node_ids_at_level_[from_node_subgraph] = input_cnt; - mux_graph.node_input_ids_[from_node_subgraph] = MuxInputId(input_cnt); - input_cnt++; - /* Update the node-to-node map */ - node2node_map[from_node_origin] = from_node_subgraph; - - /* Add edges */ - MuxEdgeId edge_subgraph = mux_graph.add_edge(node2node_map[from_node_origin], node2node_map[root_node]); - edge2edge_map[edge_origin] = edge_subgraph; - /* Configure edges */ - mux_graph.edge_models_[edge_subgraph] = this->edge_models_[edge_origin]; - mux_graph.edge_inv_mem_[edge_subgraph] = this->edge_inv_mem_[edge_origin]; - } - - /* A map to record mem-to-mem mapping from origin graph to subgraph */ - std::map mem2mem_map; - - /* Add memory bits and configure edges */ - for (auto edge_origin : this->node_in_edges_[root_node]) { - MuxMemId mem_origin = this->edge_mem_ids_[edge_origin]; - /* Try to find if the mem is already in the list */ - std::map::iterator it = mem2mem_map.find(mem_origin); - if (it != mem2mem_map.end()) { - /* Found, we skip mem addition. But make sure we have a valid one */ - VTR_ASSERT_SAFE(MuxMemId::INVALID() != mem2mem_map[mem_origin]); - /* configure the edge */ - mux_graph.edge_mem_ids_[edge2edge_map[edge_origin]] = mem2mem_map[mem_origin]; - continue; - } - /* Not found, we add a memory bit and record in the mem-to-mem map */ - MuxMemId mem_subgraph = mux_graph.add_mem(); - mux_graph.set_mem_level(mem_subgraph, 0); - mem2mem_map[mem_origin] = mem_subgraph; - /* configure the edge */ - mux_graph.edge_mem_ids_[edge2edge_map[edge_origin]] = mem_subgraph; - } - - /* Since the graph is finalized, it is time to build the fast look-up */ - mux_graph.build_node_lookup(); - mux_graph.build_mem_lookup(); - - return mux_graph; -} - -/* Generate MUX graphs for its branches - * Similar to the branch_sizes() method, - * we search all the internal nodes and - * find out what are the input sizes of - * the branches. - * Then we extract unique subgraphs and return - */ -std::vector MuxGraph::build_mux_branch_graphs() const { - std::map branch_done; /* A map showing the status of graph generation */ - - std::vector branch_graphs; - - /* Visit each internal nodes/output nodes and find the the number of incoming edges */ - for (auto node : node_ids_ ) { - /* Bypass input nodes */ - if ( (MUX_OUTPUT_NODE != node_types_[node]) - && (MUX_INTERNAL_NODE != node_types_[node]) ) { - continue; - } - - size_t branch_size = node_in_edges_[node].size(); - - /* make sure the branch size is valid */ - VTR_ASSERT_SAFE(valid_mux_implementation_num_inputs(branch_size)); - - /* check if the branch have been done in sub-graph extraction! */ - std::map::iterator it = branch_done.find(branch_size); - /* if it is done, we can skip */ - if (it != branch_done.end()) { - VTR_ASSERT(branch_done[branch_size]); - continue; - } - - /* Generate a subgraph and push back */ - branch_graphs.push_back(subgraph(node)); - - /* Mark it is done for this branch size */ - branch_done[branch_size] = true; - } - - return branch_graphs; -} - -/* Get the input id of a given node */ -MuxInputId MuxGraph::input_id(const MuxNodeId& node_id) const { - /* Validate node id */ - VTR_ASSERT(valid_node_id(node_id)); - /* Must be an input */ - VTR_ASSERT(MUX_INPUT_NODE == node_types_[node_id]); - return node_input_ids_[node_id]; -} - -/* Identify if the node is an input of the MUX */ -bool MuxGraph::is_node_input(const MuxNodeId& node_id) const { - /* Validate node id */ - VTR_ASSERT(true == valid_node_id(node_id)); - return (MUX_INPUT_NODE == node_types_[node_id]); -} - -/* Get the output id of a given node */ -MuxOutputId MuxGraph::output_id(const MuxNodeId& node_id) const { - /* Validate node id */ - VTR_ASSERT(valid_node_id(node_id)); - /* Must be an output */ - VTR_ASSERT(MUX_OUTPUT_NODE == node_types_[node_id]); - return node_output_ids_[node_id]; -} - -/* Identify if the node is an output of the MUX */ -bool MuxGraph::is_node_output(const MuxNodeId& node_id) const { - /* Validate node id */ - VTR_ASSERT(true == valid_node_id(node_id)); - return (MUX_OUTPUT_NODE == node_types_[node_id]); -} - -/* Get the node id of a given input */ -MuxNodeId MuxGraph::node_id(const MuxInputId& input_id) const { - /* Use the node_lookup to accelerate the search */ - for (const auto& lvl : node_lookup_) { - for (const auto& cand_node : lvl[MUX_INPUT_NODE]) { - if (input_id == node_input_ids_[cand_node]) { - return cand_node; - } - } - } - - return MuxNodeId::INVALID(); -} - -/* Get the node id of a given output */ -MuxNodeId MuxGraph::node_id(const MuxOutputId& output_id) const { - /* Use the node_lookup to accelerate the search */ - for (const auto& lvl : node_lookup_) { - for (const auto& cand_node : lvl[MUX_OUTPUT_NODE]) { - if (output_id == node_output_ids_[cand_node]) { - return cand_node; - } - } - } - - return MuxNodeId::INVALID(); -} - - -/* Get the node id w.r.t. the node level and node_index at the level - * Return an invalid value if not found - */ -MuxNodeId MuxGraph::node_id(const size_t& node_level, const size_t& node_index_at_level) const { - /* Ensure we have a valid node_look-up */ - VTR_ASSERT_SAFE(valid_node_lookup()); - - MuxNodeId ret_node = MuxNodeId::INVALID(); - - /* Search in the fast look up */ - if (node_level >= node_lookup_.size()) { - return ret_node; - } - - size_t node_cnt = 0; - /* Node level is valid, search in the node list */ - for (const auto& nodes_by_type : node_lookup_[node_level]) { - /* Search the node_index_at_level of each node */ - for (const auto& node : nodes_by_type) { - if (node_index_at_level != node_ids_at_level_[node]) { - continue; - } - /* Find the node, assign value and update the counter */ - ret_node = node; - node_cnt++; - } - } - - /* We should either find a node or nothing */ - VTR_ASSERT((0 == node_cnt) || (1 == node_cnt)); - - return ret_node; -} - -/* Decode memory bits based on an input id and an output id */ -vtr::vector MuxGraph::decode_memory_bits(const MuxInputId& input_id, - const MuxOutputId& output_id) const { - /* initialize the memory bits: TODO: support default value */ - vtr::vector mem_bits(mem_ids_.size(), false); - - /* valid the input and output */ - VTR_ASSERT_SAFE(valid_input_id(input_id)); - VTR_ASSERT_SAFE(valid_output_id(output_id)); - - /* Mark all the nodes as not visited */ - vtr::vector visited(nodes().size(), false); - - /* Create a queue for Breadth-First Search */ - std::list queue; - - /* Mark the input node as visited and enqueue it */ - visited[node_id(input_id)] = true; - queue.push_back(node_id(input_id)); - - /* Create a flag to indicate if the route is success or not */ - bool route_success = false; - - while(!queue.empty()) { - /* Dequeue a mux node from queue, - * we will walk through all the fan-in of this node in this loop - */ - MuxNodeId node_to_expand = queue.front(); - queue.pop_front(); - /* Get all fan-in nodes of the dequeued node - * If the node has not been visited, - * then mark it visited and enqueue it - */ - VTR_ASSERT_SAFE (1 == node_out_edges_[node_to_expand].size()); - MuxEdgeId edge = node_out_edges_[node_to_expand][0]; - - /* Configure the mem bits: - * if inv_mem is enabled, it means 0 to enable this edge - * otherwise, it is 1 to enable this edge - */ - MuxMemId mem = edge_mem_ids_[edge]; - VTR_ASSERT_SAFE (valid_mem_id(mem)); - if (true == edge_inv_mem_[edge]) { - mem_bits[mem] = false; - } else { - mem_bits[mem] = true; - } - - /* each edge must have 1 fan-out */ - VTR_ASSERT_SAFE (1 == edge_sink_nodes_[edge].size()); - - /* Get the fan-out node */ - MuxNodeId next_node = edge_sink_nodes_[edge][0]; - - /* If next node is the output node we want, we can finish here */ - if (next_node == node_id(output_id)) { - route_success = true; - break; - } - - /* Add next node to the queue if not visited yet */ - if (false == visited[next_node]) { - visited[next_node] = true; - queue.push_back(next_node); - } - } - - /* Routing must be success! */ - VTR_ASSERT(true == route_success); - - return mem_bits; -} - -/* Find the input node that the memory bits will route an output node to - * This function backward propagate from the output node to an input node - * assuming the memory bits are applied - */ -MuxInputId MuxGraph::find_input_node_driven_by_output_node(const std::map& memory_bits, - const MuxOutputId& output_id) const { - /* Ensure that the memory bits fit the size of memory bits in this MUX */ - VTR_ASSERT(memory_bits.size() == mem_ids_.size()); - - /* valid the output */ - VTR_ASSERT_SAFE(valid_output_id(output_id)); - - /* Start from the output node */ - /* Mark all the nodes as not visited */ - vtr::vector visited(nodes().size(), false); - - /* Create a queue for Breadth-First Search */ - std::list queue; - - /* Mark the output node as visited and enqueue it */ - visited[node_id(output_id)] = true; - queue.push_back(node_id(output_id)); - - /* Record the destination input id */ - MuxInputId des_input_id = MuxInputId::INVALID(); - - while(!queue.empty()) { - /* Dequeue a mux node from queue, - * we will walk through all the fan-in of this node in this loop - */ - MuxNodeId node_to_expand = queue.front(); - queue.pop_front(); - /* Get all fan-in nodes of the dequeued node - * If the node has not been visited, - * then mark it visited and enqueue it - */ - MuxEdgeId next_edge = MuxEdgeId::INVALID(); - for (const MuxEdgeId& edge : node_in_edges_[node_to_expand]) { - /* Configure the mem bits and find the edge that will propagate the signal - * if inv_mem is enabled, it means false to enable this edge - * otherwise, it is true to enable this edge - */ - MuxMemId mem = edge_mem_ids_[edge]; - VTR_ASSERT_SAFE (valid_mem_id(mem)); - if (edge_inv_mem_[edge] == !memory_bits.at(mem)) { - next_edge = edge; - break; - } - } - /* We must have a valid next edge */ - VTR_ASSERT(MuxEdgeId::INVALID() != next_edge); - - /* each edge must have 1 fan-out */ - VTR_ASSERT_SAFE (1 == edge_src_nodes_[next_edge].size()); - - /* Get the fan-in node */ - MuxNodeId next_node = edge_src_nodes_[next_edge][0]; - - /* If next node is an input node, we can finish here */ - if (true == is_node_input(next_node)) { - des_input_id = input_id(next_node); - break; - } - - /* Add next node to the queue if not visited yet */ - if (false == visited[next_node]) { - visited[next_node] = true; - queue.push_back(next_node); - } - } - - /* Routing must be success! */ - VTR_ASSERT(MuxInputId::INVALID() != des_input_id); - - return des_input_id; -} - -/************************************************** - * Private mutators: basic operations - *************************************************/ -/* Add a unconfigured node to the MuxGraph */ -MuxNodeId MuxGraph::add_node(const enum e_mux_graph_node_type& node_type) { - MuxNodeId node = MuxNodeId(node_ids_.size()); - /* Push to the node list */ - node_ids_.push_back(node); - /* Resize the other node-related vectors */ - node_types_.push_back(node_type); - node_input_ids_.push_back(MuxInputId::INVALID()); - node_output_ids_.push_back(MuxOutputId::INVALID()); - node_levels_.push_back(-1); - node_ids_at_level_.push_back(-1); - node_in_edges_.emplace_back(); - node_out_edges_.emplace_back(); - - return node; -} - -/* Add a edge connecting two nodes */ -MuxEdgeId MuxGraph::add_edge(const MuxNodeId& from_node, const MuxNodeId& to_node) { - MuxEdgeId edge = MuxEdgeId(edge_ids_.size()); - /* Push to the node list */ - edge_ids_.push_back(edge); - /* Resize the other node-related vectors */ - edge_models_.push_back(CircuitModelId::INVALID()); - edge_mem_ids_.push_back(MuxMemId::INVALID()); - edge_inv_mem_.push_back(false); - - /* update the edge-node connections */ - VTR_ASSERT(valid_node_id(from_node)); - edge_src_nodes_.emplace_back(); - edge_src_nodes_[edge].push_back(from_node); - node_out_edges_[from_node].push_back(edge); - - VTR_ASSERT(valid_node_id(to_node)); - edge_sink_nodes_.emplace_back(); - edge_sink_nodes_[edge].push_back(to_node); - node_in_edges_[to_node].push_back(edge); - - return edge; -} - -/* Add a memory bit to the MuxGraph */ -MuxMemId MuxGraph::add_mem() { - MuxMemId mem = MuxMemId(mem_ids_.size()); - /* Push to the node list */ - mem_ids_.push_back(mem); - mem_levels_.push_back(size_t(-1)); - /* Resize the other node-related vectors */ - - return mem; -} - -/* Configure the level of a memory */ -void MuxGraph::set_mem_level(const MuxMemId& mem, const size_t& level) { - /* Make sure we have valid edge and mem */ - VTR_ASSERT( valid_mem_id(mem) ); - - mem_levels_[mem] = level; -} - -/* Link an edge to a memory bit */ -void MuxGraph::set_edge_mem_id(const MuxEdgeId& edge, const MuxMemId& mem) { - /* Make sure we have valid edge and mem */ - VTR_ASSERT( valid_edge_id(edge) && valid_mem_id(mem) ); - - edge_mem_ids_[edge] = mem; -} - -/************************************************** - * Private mutators: graph builders - *************************************************/ - -/* Build a graph for a multi-level multiplexer implementation - * support both generic multi-level and tree-like multiplexers - * - * a N:1 multi-level MUX - * ---------------------- - * - * input_node --->+ - * | - * input_node --->| - * |--->+ - * ... | | - * | | - * input_node --->+ |---> ... - * | - * ... --->+ --->+ - * | - * ... ... |---> output_node - * | - * ... --->+ --->+ - * | - * input_node --->+ |---> ... - * | | - * input_node --->| | - * |--->+ - * ... | - * | - * input_node --->+ - * - * tree-like multiplexer graph will look like: - * -------------------------------------------- - * - * input_node --->+ - * |--->+ - * input_node --->+ |---> ... - * | - * --->+ --->+ - * ... ... ... |----> output_node - * ... --->+ --->+ - * |---> ... - * input_node --->+ | - * |--->+ - * input_node --->+ - * - */ -void MuxGraph::build_multilevel_mux_graph(const size_t& mux_size, - const size_t& num_levels, const size_t& num_inputs_per_branch, - const CircuitModelId& pgl_model) { - /* Make sure mux_size for each branch is valid */ - VTR_ASSERT(valid_mux_implementation_num_inputs(num_inputs_per_branch)); - - /* In regular cases, there is 1 mem bit for each input of a branch */ - size_t num_mems_per_level = num_inputs_per_branch; - /* For 2-input branch, only 1 mem bit is needed for each level! */ - if (2 == num_inputs_per_branch) { - num_mems_per_level = 1; - } - /* Number of memory bits is definite, add them */ - for (size_t ilvl = 0; ilvl < num_levels; ++ilvl) { - for (size_t imem = 0; imem < num_mems_per_level; ++imem) { - MuxMemId mem = add_mem(); - mem_levels_[mem] = ilvl; - } - } - - /* Create a fast node lookup locally. - * Only used for building the graph - * it sorts the nodes by levels and ids at each level - */ - std::vector> node_lookup; /* [num_levels][num_nodes_per_level] */ - node_lookup.resize(num_levels + 1); - - /* Number of outputs is definite, add and configure */ - MuxNodeId output_node = add_node(MUX_OUTPUT_NODE); - node_levels_[output_node] = num_levels; - node_ids_at_level_[output_node] = 0; - node_output_ids_[output_node] = MuxOutputId(0); - /* Update node lookup */ - node_lookup[num_levels].push_back(output_node); - - /* keep a list of node ids which can be candidates for input nodes */ - std::vector input_node_ids; - - /* Add internal nodes level by level, - * we start from the last level, following a strategy like tree growing - */ - for (size_t lvl = num_levels - 1; ; --lvl) { - /* Expand from the existing nodes - * Last level should expand from output_node - * Other levels will expand from internal nodes! - */ - size_t node_cnt_per_level = 0; /* A counter to record node indices at each level */ - for (MuxNodeId seed_node : node_lookup[lvl + 1]) { - /* Add a new node and connect to seed_node, until we reach the num_inputs_per_branch */ - for (size_t i = 0; i < num_inputs_per_branch; ++i) { - /* We deposite a type of INTERNAL_NODE, - * later it will be configured to INPUT if it is in the input list - */ - MuxNodeId expand_node = add_node(MUX_INTERNAL_NODE); - - /* Node level is deterministic */ - node_levels_[expand_node] = lvl; - node_ids_at_level_[expand_node] = node_cnt_per_level; - /* update level node counter */ - node_cnt_per_level++; - - /* Create an edge and connect the two nodes */ - MuxEdgeId edge = add_edge(expand_node, seed_node); - /* Configure the edge */ - edge_models_[edge] = pgl_model; - - /* Memory id depends on the level and offset in the current branch - * if number of inputs per branch is 2, it indicates a tree-like multiplexer, - * every two edges will share one memory bit - * otherwise, each edge corresponds to a memory bit - */ - - if ( 2 == num_inputs_per_branch) { - MuxMemId mem_id = MuxMemId(lvl); - set_edge_mem_id(edge, mem_id); - /* If this is a second edge in the branch, we will assign it to an inverted edge */ - if (0 != i % num_inputs_per_branch) { - edge_inv_mem_[edge] = true; - } - } else { - MuxMemId mem_id = MuxMemId( lvl * num_inputs_per_branch + i ); - set_edge_mem_id(edge, mem_id); - } - - /* Update node lookup */ - node_lookup[lvl].push_back(expand_node); - - /* Push the node to input list, and then remove the seed_node from the list */ - input_node_ids.push_back(expand_node); - /* Remove the node if the seed node is the list */ - std::vector::iterator it = find(input_node_ids.begin(), input_node_ids.end(), seed_node); - if (it != input_node_ids.end()) { - input_node_ids.erase(it); - } - - /* Check the number of input nodes, if already meet the demand, we can finish here */ - if (mux_size != input_node_ids.size()) { - continue; /* We need more inputs, keep looping */ - } - - /* The graph is done, we configure the input nodes and then we can return */ - /* We must be in level 0 !*/ - VTR_ASSERT( 0 == lvl ) ; - for (MuxNodeId input_node : input_node_ids) { - node_types_[input_node] = MUX_INPUT_NODE; - } - - /* Sort the nodes by the levels and offset */ - size_t input_cnt = 0; - for (auto lvl_nodes : node_lookup) { - for (MuxNodeId cand_node : lvl_nodes) { - if (MUX_INPUT_NODE != node_types_[cand_node]) { - continue; - } - /* Update the input node ids */ - node_input_ids_[cand_node] = MuxInputId(input_cnt); - /* Update the counter */ - input_cnt++; - } - } - /* Make sure we visited all the inputs in the cache */ - VTR_ASSERT(input_cnt == input_node_ids.size()); - /* Finish building the graph for a multi-level multiplexer */ - return; - } - } - } - /* Finish building the graph for a multi-level multiplexer */ -} - -/* Build the graph for a given one-level multiplexer implementation - * a N:1 one-level MUX - * - * input_node --->+ - * | - * input_node --->| - * |--> output_node - * ... | - * | - * input_node --->+ - */ -void MuxGraph::build_onelevel_mux_graph(const size_t& mux_size, - const CircuitModelId& pgl_model) { - /* Make sure mux_size is valid */ - VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); - - /* We definitely know how many nodes we need, - * N inputs, 1 output and 0 internal nodes - */ - MuxNodeId output_node = add_node(MUX_OUTPUT_NODE); - node_levels_[output_node] = 1; - node_ids_at_level_[output_node] = 0; - node_output_ids_[output_node] = MuxOutputId(0); - - for (size_t i = 0; i < mux_size; ++i) { - MuxNodeId input_node = add_node(MUX_INPUT_NODE); - /* All the node belong to level 0 (we have only 1 level) */ - node_input_ids_[input_node] = MuxInputId(i); - node_levels_[input_node] = 0; - node_ids_at_level_[input_node] = i; - - /* We definitely know how many edges we need, - * the same as mux_size, add a edge connecting two nodes - */ - MuxEdgeId edge = add_edge(input_node, output_node); - /* Configure the edge */ - edge_models_[edge] = pgl_model; - - /* Create a memory bit*/ - MuxMemId mem = add_mem(); - mem_levels_[mem] = 0; - /* Link the edge to a memory bit */ - set_edge_mem_id(edge, mem); - } - /* Finish building the graph for a one-level multiplexer */ -} - -/* Convert some internal nodes to be additional outputs - * according to the fracturable LUT port definition - * We will iterate over each output port of a circuit model - * and find the frac_level and output_mask - * Then, the internal nodes at the frac_level will be converted - * to output nodes with a given output_mask - */ -void MuxGraph::add_fracturable_outputs(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - /* Iterate over output ports */ - for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true)) { - /* Get the fracturable_level */ - size_t frac_level = circuit_lib.port_lut_frac_level(port); - /* Bypass invalid frac_level */ - if (size_t(-1) == frac_level) { - continue; - } - /* Iterate over output masks */ - for (const auto& output_idx : circuit_lib.port_lut_output_masks(port)) { - size_t num_matched_nodes = 0; - /* Iterate over node and find the internal nodes, which match the frac_level and output_idx */ - for (const auto& node : node_lookup_[frac_level][MUX_INTERNAL_NODE]) { - if (node_ids_at_level_[node] != output_idx) { - /* Bypass condition */ - continue; - } - /* Reach here, this is the node we want - * Convert it to output nodes and update the counter - */ - node_types_[node] = MUX_OUTPUT_NODE; - node_output_ids_[node] = MuxOutputId(num_outputs()); - num_matched_nodes++; - } - /* Either find 1 or 0 matched nodes */ - if (0 != num_matched_nodes) { - /* We should find only one node that matches! */ - VTR_ASSERT(1 == num_matched_nodes); - /* Rebuild the node look-up */ - build_node_lookup(); - continue; /* Finish here, go to next */ - } - /* Sometime the wanted node is already an output, do a double check */ - for (const auto& node : node_lookup_[frac_level][MUX_OUTPUT_NODE]) { - if (node_ids_at_level_[node] != output_idx) { - /* Bypass condition */ - continue; - } - /* Reach here, this is the node we want - * Just update the counter - */ - num_matched_nodes++; - } - /* We should find only one node that matches! */ - VTR_ASSERT(1 == num_matched_nodes); - } - } -} - -/* Build the graph for a given multiplexer model */ -void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size) { - /* Make sure this model is a MUX */ - VTR_ASSERT((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) - || (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) ); - - /* Make sure mux_size is valid */ - VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); - - size_t impl_mux_size = find_mux_implementation_num_inputs(circuit_lib, circuit_model, mux_size); - - /* Depends on the mux size, the implemented multiplexer structure may change! */ - enum e_spice_model_structure impl_structure = find_mux_implementation_structure(circuit_lib, circuit_model, impl_mux_size); - - /* Branch on multiplexer structures, leading to different building strategies */ - switch (impl_structure) { - case SPICE_MODEL_STRUCTURE_TREE: { - /* Find the number of levels */ - size_t num_levels = find_treelike_mux_num_levels(impl_mux_size); - - /* Find the number of inputs per branch, this is not final */ - size_t num_inputs_per_branch = 2; - - /* Build a multilevel mux graph */ - build_multilevel_mux_graph(impl_mux_size, num_levels, num_inputs_per_branch, circuit_lib.pass_gate_logic_model(circuit_model)); - break; - } - case SPICE_MODEL_STRUCTURE_ONELEVEL: { - build_onelevel_mux_graph(impl_mux_size, circuit_lib.pass_gate_logic_model(circuit_model)); - break; - } - case SPICE_MODEL_STRUCTURE_MULTILEVEL: { - /* Find the number of inputs per branch, this is not final */ - size_t num_inputs_per_branch = find_multilevel_mux_branch_num_inputs(impl_mux_size, circuit_lib.mux_num_levels(circuit_model)); - - /* Build a multilevel mux graph */ - build_multilevel_mux_graph(impl_mux_size, circuit_lib.mux_num_levels(circuit_model), - num_inputs_per_branch, - circuit_lib.pass_gate_logic_model(circuit_model)); - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid multiplexer structure for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - - /* Since the graph is finalized, it is time to build the fast look-up */ - build_node_lookup(); - build_mem_lookup(); - - /* For fracturable LUTs, we need to add more outputs to the MUX graph */ - if ( (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) - && (true == circuit_lib.is_lut_fracturable(circuit_model)) ) { - add_fracturable_outputs(circuit_lib, circuit_model); - } -} - -/* Build fast node lookup */ -void MuxGraph::build_node_lookup() { - /* Invalidate the node lookup if necessary */ - invalidate_node_lookup(); - - /* Find the maximum number of levels */ - size_t num_levels = 0; - for (auto node : nodes()) { - num_levels = std::max((int)node_levels_[node], (int)num_levels); - } - - /* Resize node_lookup */ - node_lookup_.resize(num_levels + 1); - for (size_t lvl = 0; lvl < node_lookup_.size(); ++lvl) { - /* Resize by number of node types */ - node_lookup_[lvl].resize(NUM_MUX_NODE_TYPES); - } - - /* Fill the node lookup */ - for (auto node : nodes()) { - node_lookup_[node_levels_[node]][size_t(node_types_[node])].push_back(node); - } -} - -/* Build fast mem lookup */ -void MuxGraph::build_mem_lookup() { - /* Invalidate the mem lookup if necessary */ - invalidate_mem_lookup(); - - /* Find the maximum number of levels */ - size_t num_levels = 0; - for (auto mem : memories()) { - num_levels = std::max((int)mem_levels_[mem], (int)num_levels); - } - - /* Resize mem_lookup */ - mem_lookup_.resize(num_levels + 1); - for (auto mem : memories()) { - /* Categorize mem nodes into mem_lookup */ - mem_lookup_[mem_levels_[mem]].push_back(mem); - } -} - -/* Invalidate (empty) the node fast lookup*/ -void MuxGraph::invalidate_node_lookup() { - node_lookup_.clear(); -} - -/* Invalidate (empty) the mem fast lookup*/ -void MuxGraph::invalidate_mem_lookup() { - mem_lookup_.clear(); -} - -/************************************************** - * Private validators - *************************************************/ - -/* valid ids */ -bool MuxGraph::valid_node_id(const MuxNodeId& node) const { - return size_t(node) < node_ids_.size() && node_ids_[node] == node; -} - -bool MuxGraph::valid_edge_id(const MuxEdgeId& edge) const { - return size_t(edge) < edge_ids_.size() && edge_ids_[edge] == edge; -} - -bool MuxGraph::valid_mem_id(const MuxMemId& mem) const { - return size_t(mem) < mem_ids_.size() && mem_ids_[mem] == mem; -} - -/* validate an input id (from which data path signal will be progagated to the output) */ -bool MuxGraph::valid_input_id(const MuxInputId& input_id) const { - for (const auto& lvl : node_lookup_) { - for (const auto& node : lvl[MUX_INPUT_NODE]) { - if (size_t(input_id) > size_t(node_input_ids_[node])) { - return false; - } - } - } - - return true; -} - -/* validate an output id */ -bool MuxGraph::valid_output_id(const MuxOutputId& output_id) const { - for (const auto& lvl : node_lookup_) { - for (const auto& node : lvl[MUX_OUTPUT_NODE]) { - if (size_t(output_id) > size_t(node_output_ids_[node])) { - return false; - } - } - } - - return true; -} - -bool MuxGraph::valid_level(const size_t& level) const { - return level < num_node_levels(); -} - -bool MuxGraph::valid_node_lookup() const { - return node_lookup_.empty(); -} - -/* validate a mux graph and see if it is valid */ -bool MuxGraph::valid_mux_graph() const { - /* A valid MUX graph should be - * 1. every node has 1 fan-out except output node - * 2. every input can be routed to the output node - */ - for (const auto& node : nodes()) { - /* output node has 0 fan-out*/ - if (MUX_OUTPUT_NODE == node_types_[node]) { - continue; - } - /* other nodes should have 1 fan-out */ - if (1 != node_out_edges_[node].size()) { - return false; - } - } - - /* Try to route to output */ - for (const auto& node : nodes()) { - if (MUX_INPUT_NODE == node_types_[node]) { - MuxNodeId next_node = node; - while ( 0 < node_out_edges_[next_node].size() ) { - MuxEdgeId edge = node_out_edges_[next_node][0]; - /* each edge must have 1 fan-out */ - if (1 != edge_sink_nodes_[edge].size()) { - return false; - } - next_node = edge_sink_nodes_[edge][0]; - } - if (MUX_OUTPUT_NODE != node_types_[next_node]) { - return false; - } - } - } - - return true; -} - -/************************************************** - * End of Member functions for the class MuxGraph - *************************************************/ diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.h b/vpr7_x2p/vpr/SRC/device/mux_graph.h deleted file mode 100644 index 014e0a59b..000000000 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.h +++ /dev/null @@ -1,206 +0,0 @@ -/************************************************** - * This file includes a data structure to describe - * the internal structure of a multiplexer - * using a generic graph representation - * A Branch is a N:1 MUX in the part of MUX graph - * - * branch_input --->+ - * | - * branch_input --->| - * |--> branch_out - * ... | - * | - * branch_input --->+ - * - * A short example of how a two-level MUX is organized by branches - * - * +-----------+ +--------+ - * mux_inputs--->| Branch[0] |--->| | - * +-----------+ | | - * ... | Branch |---> mux_out - * +-----------+ | [N+1] | - * mux_inputs--->| Branch[N] |--->| | - * +-----------+ +--------+ - * - *************************************************/ - -#ifndef MUX_GRAPH_H -#define MUX_GRAPH_H - -#include -#include "vtr_vector.h" -#include "vtr_range.h" -#include "mux_graph_fwd.h" -#include "circuit_library.h" - -class MuxGraph { - private: /* data types used only in this class */ - enum e_mux_graph_node_type { - MUX_INPUT_NODE, - MUX_INTERNAL_NODE, - MUX_OUTPUT_NODE, - NUM_MUX_NODE_TYPES - }; - public: /* Types and ranges */ - typedef vtr::vector::const_iterator node_iterator; - typedef vtr::vector::const_iterator edge_iterator; - typedef vtr::vector::const_iterator mem_iterator; - - typedef vtr::Range node_range; - typedef vtr::Range edge_range; - typedef vtr::Range mem_range; - public: /* Public Constructors */ - /* Create an object based on a Circuit Model which is MUX */ - MuxGraph(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size); - private: /* Private Constructors*/ - /* Create an empty graph */ - MuxGraph(); - public: /* Public accessors: Aggregates */ - node_range nodes() const; - /* Find the non-input nodes */ - std::vector non_input_nodes() const; - edge_range edges() const; - mem_range memories() const; - /* Find the number of levels in terms of the multiplexer */ - std::vector levels() const; - /* Find the actual number of levels in the graph */ - std::vector node_levels() const; - public: /* Public accessors: Data query */ - /* Find the number of inputs in the MUX graph */ - size_t num_inputs() const; - std::vector inputs() const; - /* Find the number of outputs in the MUX graph */ - size_t num_outputs() const; - std::vector outputs() const; - /* Find the edge between two MUX nodes */ - std::vector find_edges(const MuxNodeId& from_node, const MuxNodeId& to_node) const; - /* Find the number of levels in the MUX graph */ - size_t num_levels() const; - size_t num_node_levels() const; - /* Find the number of SRAMs in the MUX graph */ - size_t num_memory_bits() const; - /* Find the number of SRAMs at a level in the MUX graph */ - size_t num_memory_bits_at_level(const size_t& level) const; - /* Return memory id at level */ - std::vector memories_at_level(const size_t& level) const; - /* Find the number of nodes at a given level in the MUX graph */ - size_t num_nodes_at_level(const size_t& level) const; - /* Find the level of a node */ - size_t node_level(const MuxNodeId& node) const; - /* Find the index of a node at its level */ - size_t node_index_at_level(const MuxNodeId& node) const; - /* Find the input edges for a node */ - std::vector node_in_edges(const MuxNodeId& node) const; - /* Find the input nodes for a edge */ - std::vector edge_src_nodes(const MuxEdgeId& edge) const; - /* Find the mem that control the edge */ - MuxMemId find_edge_mem(const MuxEdgeId& edge) const; - /* Identify if the edge is controlled by the inverted output of a mem */ - bool is_edge_use_inv_mem(const MuxEdgeId& edge) const; - /* Find the sizes of each branch of a MUX */ - std::vector branch_sizes() const; - /* Find the sizes of each branch of a MUX at a given level */ - std::vector branch_sizes(const size_t& level) const; - /* Generate MUX graphs for its branches */ - MuxGraph subgraph(const MuxNodeId& node) const; - std::vector build_mux_branch_graphs() const; - /* Get the node id of a given input */ - MuxNodeId node_id(const MuxInputId& input_id) const; - /* Get the node id of a given output */ - MuxNodeId node_id(const MuxOutputId& output_id) const; - /* Get the node id w.r.t. the node level and node_index at the level */ - MuxNodeId node_id(const size_t& node_level, const size_t& node_index_at_level) const; - /* Get the input id of a given node */ - MuxInputId input_id(const MuxNodeId& node_id) const; - /* Identify if the node is an input of the MUX */ - bool is_node_input(const MuxNodeId& node_id) const; - /* Get the output id of a given node */ - MuxOutputId output_id(const MuxNodeId& node_id) const; - /* Identify if the node is an output of the MUX */ - bool is_node_output(const MuxNodeId& node_id) const; - /* Decode memory bits based on an input id and an output id - * This function will start from the input node - * and do a forward propagation until reaching the output node - */ - vtr::vector decode_memory_bits(const MuxInputId& input_id, - const MuxOutputId& output_id) const; - /* Find the input node that the memory bits will route an output node to - * This function backward propagate from the output node to an input node - * assuming the memory bits are applied - * Note: This function is mainly used for decoding LUT MUXes - */ - MuxInputId find_input_node_driven_by_output_node(const std::map& memory_bits, - const MuxOutputId& output_id) const; - private: /* Private mutators : basic operations */ - /* Add a unconfigured node to the MuxGraph */ - MuxNodeId add_node(const enum e_mux_graph_node_type& node_type); - /* Add a edge connecting two nodes */ - MuxEdgeId add_edge(const MuxNodeId& from_node, const MuxNodeId& to_node); - /* Add a memory bit to the MuxGraph */ - MuxMemId add_mem(); - /* Configure the level of a memory */ - void set_mem_level(const MuxMemId& mem, const size_t& level); - /* Link an edge to a mem */ - void set_edge_mem_id(const MuxEdgeId& edge, const MuxMemId& mem); - private: /* Private mutators : graph builders */ - void build_multilevel_mux_graph(const size_t& mux_size, - const size_t& num_levels, const size_t& num_inputs_per_branch, - const CircuitModelId& pgl_model) ; - /* Build the graph for a given one-level multiplexer implementation */ - void build_onelevel_mux_graph(const size_t& mux_size, - const CircuitModelId& pgl_model) ; - /* Build the graph for a given multiplexer model */ - void build_mux_graph(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size); - /* Convert some internal node to outputs according to fracturable LUT circuit design specifications */ - void add_fracturable_outputs(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model); - /* Build fast node lookup */ - void build_node_lookup(); - /* Build fast mem lookup */ - void build_mem_lookup(); - private: /* Private validators */ - /* valid ids */ - bool valid_node_id(const MuxNodeId& node) const; - bool valid_edge_id(const MuxEdgeId& edge) const; - bool valid_mem_id(const MuxMemId& mem) const; - bool valid_input_id(const MuxInputId& input_id) const; - bool valid_output_id(const MuxOutputId& output_id) const; - bool valid_level(const size_t& level) const; - /* validate/invalidate node lookup */ - bool valid_node_lookup() const; - void invalidate_node_lookup(); - void invalidate_mem_lookup(); - /* validate graph */ - bool valid_mux_graph() const; - private: /* Internal data */ - vtr::vector node_ids_; /* Unique ids for each node */ - vtr::vector node_types_; /* type of each node, input/output/internal */ - vtr::vector node_input_ids_; /* Unique ids for each node as an input of the MUX */ - vtr::vector node_output_ids_; /* Unique ids for each node as an input of the MUX */ - vtr::vector node_levels_; /* at which level, each node belongs to */ - vtr::vector node_ids_at_level_; /* the index at the level that each node belongs to */ - vtr::vector> node_in_edges_; /* ids of incoming edges to each node */ - vtr::vector> node_out_edges_; /* ids of outgoing edges from each node */ - - vtr::vector edge_ids_; /* Unique ids for each edge */ - vtr::vector> edge_src_nodes_; /* source nodes drive this edge */ - vtr::vector> edge_sink_nodes_; /* sink nodes this edge drives */ - vtr::vector edge_models_; /* type of each edge: tgate/pass-gate */ - vtr::vector edge_mem_ids_; /* ids of memory bit that control the edge */ - vtr::vector edge_inv_mem_; /* if the edge is controlled by an inverted output of a memory bit */ - - vtr::vector mem_ids_; /* ids of configuration memories */ - vtr::vector mem_levels_; /* ids of configuration memories */ - - /* fast look-up */ - typedef std::vector>> NodeLookup; - mutable NodeLookup node_lookup_; /* [num_levels][num_types][num_nodes_per_level] */ - typedef std::vector> MemLookup; - mutable MemLookup mem_lookup_; /* [num_levels][num_mems_per_level] */ -}; - -#endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h b/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h deleted file mode 100644 index fca07ca2a..000000000 --- a/vpr7_x2p/vpr/SRC/device/mux_graph_fwd.h +++ /dev/null @@ -1,26 +0,0 @@ -/************************************************** - * This file includes only declarations for - * the data structures to describe multiplexer structures - * Please refer to mux_graph.h for more details - *************************************************/ -#ifndef MUX_GRAPH_FWD_H -#define MUX_GRAPH_FWD_H - -#include "vtr_strong_id.h" - -/* Strong Ids for MUXes */ -struct mux_node_id_tag; -struct mux_edge_id_tag; -struct mux_mem_id_tag; -struct mux_input_id_tag; -struct mux_output_id_tag; - -typedef vtr::StrongId MuxNodeId; -typedef vtr::StrongId MuxEdgeId; -typedef vtr::StrongId MuxMemId; -typedef vtr::StrongId MuxInputId; -typedef vtr::StrongId MuxOutputId; - -class MuxGraph; - -#endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_library.cpp b/vpr7_x2p/vpr/SRC/device/mux_library.cpp deleted file mode 100644 index ee51b087b..000000000 --- a/vpr7_x2p/vpr/SRC/device/mux_library.cpp +++ /dev/null @@ -1,124 +0,0 @@ -/************************************************** - * This file includes member functions for the - * data structures in mux_library.h - *************************************************/ - -#include "vtr_assert.h" - -#include "mux_library.h" - -/************************************************** - * Member functions for the class MuxLibrary - *************************************************/ - -/************************************************** - * Public accessors: aggregates - *************************************************/ -MuxLibrary::mux_range MuxLibrary::muxes() const { - return vtr::make_range(mux_ids_.begin(), mux_ids_.end()); -} - -/************************************************** - * Public accessors: data query - *************************************************/ -/* Get a MUX graph (read-only) */ -MuxId MuxLibrary::mux_graph(const CircuitModelId& circuit_model, - const size_t& mux_size) const { - /* Make sure we have a valid mux look-up */ - VTR_ASSERT_SAFE(valid_mux_lookup()); - /* Validate circuit model id and mux_size */ - VTR_ASSERT_SAFE(valid_mux_size(circuit_model, mux_size)); - - return mux_lookup_[circuit_model][mux_size]; -} - -const MuxGraph& MuxLibrary::mux_graph(const MuxId& mux_id) const { - VTR_ASSERT_SAFE(valid_mux_id(mux_id)); - return mux_graphs_[mux_id]; -} - -/* Get a mux circuit model id */ -CircuitModelId MuxLibrary::mux_circuit_model(const MuxId& mux_id) const { - VTR_ASSERT_SAFE(valid_mux_id(mux_id)); - return mux_circuit_models_[mux_id]; -} - -/* Find the maximum mux size among the mux graphs */ -size_t MuxLibrary::max_mux_size() const { - /* Iterate over all the mux graphs and find their sizes */ - size_t max_mux_size = 0; - for (const auto& mux : mux_ids_) { - max_mux_size = std::max(max_mux_size, mux_graphs_[mux].num_inputs()); - } - return max_mux_size; -} - -/************************************************** - * Private mutators: - *************************************************/ -/* Add a mux to the library */ -void MuxLibrary::add_mux(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size) { - /* First, check if there is already an existing graph */ - if (valid_mux_size(circuit_model, mux_size)) { - return; - } - - /* create a new id for the mux */ - MuxId mux = MuxId(mux_ids_.size()); - /* Push to the node list */ - mux_ids_.push_back(mux); - /* Add a mux graph */ - mux_graphs_.push_back(MuxGraph(circuit_lib, circuit_model, mux_size)); - /* Recorde mux cirucit model id */ - mux_circuit_models_.push_back(circuit_model); - - /* update mux_lookup*/ - mux_lookup_[circuit_model][mux_size] = mux; -} - -/************************************************** - * Private accessors: validator and invalidators - *************************************************/ -bool MuxLibrary::valid_mux_id(const MuxId& mux) const { - return size_t(mux) < mux_ids_.size() && mux_ids_[mux] == mux; -} - -bool MuxLibrary::valid_mux_lookup() const { - return mux_lookup_.empty(); -} - -bool MuxLibrary::valid_mux_circuit_model_id(const CircuitModelId& circuit_model) const { - MuxLookup::iterator it = mux_lookup_.find(circuit_model); - return (it != mux_lookup_.end()); -} - -bool MuxLibrary::valid_mux_size(const CircuitModelId& circuit_model, const size_t& mux_size) const { - if (false == valid_mux_circuit_model_id(circuit_model)) { - return false; - } - std::map::iterator it = mux_lookup_[circuit_model].find(mux_size); - return (it != mux_lookup_[circuit_model].end()); -} - -/************************************************** - * Private mutators: validator and invalidators - *************************************************/ - -/* Build fast node lookup */ -void MuxLibrary::build_mux_lookup() { - /* Invalidate the mux lookup if necessary */ - invalidate_mux_lookup(); -} - -/* Invalidate (empty) the mux fast lookup*/ -void MuxLibrary::invalidate_mux_lookup() { - mux_lookup_.clear(); -} - - -/************************************************** - * End of Member functions for the class MuxLibrary - *************************************************/ - - - diff --git a/vpr7_x2p/vpr/SRC/device/mux_library.h b/vpr7_x2p/vpr/SRC/device/mux_library.h deleted file mode 100644 index 7e38f27b1..000000000 --- a/vpr7_x2p/vpr/SRC/device/mux_library.h +++ /dev/null @@ -1,59 +0,0 @@ -/************************************************** - * This file includes a data structure to describe - * the multiplexer implementations in FPGA architectures - * MuxLibrary is a collection of multiplexers - * with various circuit-level description (related to - * the information available in CircuitLibrary - * and the input size of multiplexers) - *************************************************/ - -#ifndef MUX_LIBRARY_H -#define MUX_LIBRARY_H - -#include -#include "mux_graph.h" -#include "mux_library_fwd.h" - -class MuxLibrary { - public: /* Types and ranges */ - typedef vtr::vector::const_iterator mux_iterator; - - typedef vtr::Range mux_range; - public: /* Public accessors: Aggregates */ - mux_range muxes() const; - public: /* Public accessors */ - /* Get a MUX graph (read-only) */ - MuxId mux_graph(const CircuitModelId& circuit_model, const size_t& mux_size) const; - const MuxGraph& mux_graph(const MuxId& mux_id) const; - /* Get a mux circuit model id */ - CircuitModelId mux_circuit_model(const MuxId& mux_id) const; - /* Find the mux sizes */ - size_t max_mux_size() const; - public: /* Public mutators */ - /* Add a mux to the library */ - void add_mux(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size); - public: /* Public validators */ - bool valid_mux_id(const MuxId& mux) const; - private: /* Private accessors */ - bool valid_mux_lookup() const; - bool valid_mux_circuit_model_id(const CircuitModelId& circuit_model) const; - bool valid_mux_size(const CircuitModelId& circuit_model, const size_t& mux_size) const; - private: /* Private mutators: mux_lookup */ - void build_mux_lookup(); - /* Invalidate (empty) the mux fast lookup*/ - void invalidate_mux_lookup(); - private: /* Internal data */ - /* MUX graph-based desription */ - vtr::vector mux_ids_; /* Unique identifier for each mux graph */ - vtr::vector mux_graphs_; /* Graphs describing MUX internal structures */ - vtr::vector mux_circuit_models_; /* circuit model id in circuit library */ - - /* Local encoder description */ - //vtr::vector mux_local_encoders_; /* Graphs describing MUX internal structures */ - - /* a fast look-up to search mux_graphs with given circuit model and mux size */ - typedef std::map> MuxLookup; - mutable MuxLookup mux_lookup_; -}; - -#endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_library_builder.cpp b/vpr7_x2p/vpr/SRC/device/mux_library_builder.cpp deleted file mode 100644 index 9dc462572..000000000 --- a/vpr7_x2p/vpr/SRC/device/mux_library_builder.cpp +++ /dev/null @@ -1,186 +0,0 @@ -/******************************************************************** - * This file includes the functions of builders for MuxLibrary. - *******************************************************************/ -#include -#include -#include "vtr_assert.h" - -/* Device-level header files */ -#include "util.h" -#include "vpr_types.h" -#include "globals.h" - -/* FPGA-X2P context header files */ -#include "fpga_x2p_utils.h" - -#include "spice_types.h" -#include "circuit_library.h" -#include "mux_library.h" -#include "mux_library_builder.h" - -/******************************************************************** - * Update MuxLibrary with the unique multiplexer structures - * found in the global routing architecture - *******************************************************************/ -static -void build_routing_arch_mux_library(MuxLibrary& mux_lib, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_switch_inf* switches, - const CircuitLibrary& circuit_lib, - t_det_routing_arch* routing_arch) { - /* Current Version: Support Uni-directional routing architecture only*/ - if (UNI_DIRECTIONAL != routing_arch->directionality) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s, LINE[%d]) FPGA X2P Only supports uni-directional routing architecture.\n", - __FILE__, __LINE__); - exit(1); - } - - /* The routing path is. - * OPIN ----> CHAN ----> ... ----> CHAN ----> IPIN - * Each edge is a switch, for IPIN, the switch is a connection block, - * for the rest is a switch box - */ - /* Count the sizes of muliplexers in routing architecture */ - for (int inode = 0; inode < LL_num_rr_nodes; inode++) { - t_rr_node& node = LL_rr_node[inode]; - switch (node.type) { - case IPIN: { - /* Have to consider the fan_in only, it is a connection block (multiplexer)*/ - VTR_ASSERT((node.fan_in > 0) || (0 == node.fan_in)); - if ( (0 == node.fan_in) || (1 == node.fan_in)) { - break; - } - /* Find the circuit_model for multiplexers in connection blocks */ - const CircuitModelId& cb_switch_circuit_model = switches[node.driver_switch].circuit_model; - /* we should select a circuit model for the connection box*/ - VTR_ASSERT(CircuitModelId::INVALID() != cb_switch_circuit_model); - /* Add the mux to mux_library */ - mux_lib.add_mux(circuit_lib, cb_switch_circuit_model, node.fan_in); - break; - } - case CHANX: - case CHANY: { - /* Channels are the same, have to consider the fan_in as well, - * it could be a switch box if previous rr_node is a channel - * or it could be a connection box if previous rr_node is a IPIN or OPIN - */ - VTR_ASSERT((node.fan_in > 0) || (0 == node.fan_in)); - if ((0 == node.fan_in) || (1 == node.fan_in)) { - break; - } - /* Find the spice_model for multiplexers in switch blocks*/ - const CircuitModelId& sb_switch_circuit_model = switches[node.driver_switch].circuit_model; - /* we should select a circuit model for the Switch box*/ - VTR_ASSERT(CircuitModelId::INVALID() != sb_switch_circuit_model); - /* Add the mux to mux_library */ - mux_lib.add_mux(circuit_lib, sb_switch_circuit_model, node.fan_in); - break; - } - default: - /* We do not care other types of rr_node */ - break; - } - } -} - -/******************************************************************** - * Update MuxLibrary with the unique multiplexer structures - * found in programmable logic blocks - ********************************************************************/ -static -void build_pb_type_mux_library_rec(MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - t_pb_type* cur_pb_type) { - VTR_ASSERT(nullptr != cur_pb_type); - - /* If there is spice_model_name, this is a leaf node!*/ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - /* What annoys me is VPR create a sub pb_type for each lut which suppose to be a leaf node - * This may bring software convience but ruins circuit modeling - */ - VTR_ASSERT(CircuitModelId::INVALID() != cur_pb_type->phy_pb_type->circuit_model); - return; - } - - /* Traversal the hierarchy, find all the multiplexer from the interconnection part */ - for (int imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* Then we have to statisitic the interconnections*/ - for (int jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { - /* Check the num_mux and fan_in of an interconnection */ - VTR_ASSERT ((0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) - || (0 < cur_pb_type->modes[imode].interconnect[jinterc].num_mux)); - if (0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) { - continue; - } - CircuitModelId& interc_circuit_model = cur_pb_type->modes[imode].interconnect[jinterc].circuit_model; - VTR_ASSERT(CircuitModelId::INVALID() != interc_circuit_model); - /* Add the mux model to library */ - mux_lib.add_mux(circuit_lib, interc_circuit_model, cur_pb_type->modes[imode].interconnect[jinterc].fan_in); - } - } - - /* Go recursively to the lower level */ - for (int imode = 0; imode < cur_pb_type->num_modes; imode++) { - for (int ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ichild++) { - build_pb_type_mux_library_rec(mux_lib, circuit_lib, - &cur_pb_type->modes[imode].pb_type_children[ichild]); - } - } -} - -/******************************************************************** - * Update MuxLibrary with the unique multiplexers required by - * LUTs in the circuit library - ********************************************************************/ -static -void build_lut_mux_library(MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib) { - /* Find all the circuit models which are LUTs in the circuit library */ - for (const auto& circuit_model : circuit_lib.models()) { - /* Bypass non-LUT circuit models */ - if (SPICE_MODEL_LUT != circuit_lib.model_type(circuit_model)) { - continue; - } - /* Find the MUX size required by the LUT */ - /* Get input ports which are not global ports! */ - std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - VTR_ASSERT(1 == input_ports.size()); - /* MUX size = 2^lut_size */ - size_t lut_mux_size = (size_t)pow(2., (double)(circuit_lib.port_size(input_ports[0]))); - /* Add mux to the mux library */ - mux_lib.add_mux(circuit_lib, circuit_model, lut_mux_size); - } -} - -/* Statistic for all the multiplexers in FPGA - * We determine the sizes and its structure (according to spice_model) for each type of multiplexers - * We search multiplexers in Switch Blocks, Connection blocks and Configurable Logic Blocks - * In additional to multiplexers, this function also consider crossbars. - * All the statistics are stored in a linked list, as a return value - */ -MuxLibrary build_device_mux_library(int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_switch_inf* switches, - const CircuitLibrary& circuit_lib, - t_det_routing_arch* routing_arch) { - /* MuxLibrary to store the information of Multiplexers*/ - MuxLibrary mux_lib; - - /* Step 1: We should check the multiplexer spice models defined in routing architecture.*/ - build_routing_arch_mux_library(mux_lib, LL_num_rr_nodes, LL_rr_node, switches, circuit_lib, routing_arch); - - /* Step 2: Count the sizes of multiplexers in complex logic blocks */ - for (int itype = 0; itype < num_types; itype++) { - if (NULL != type_descriptors[itype].pb_type) { - build_pb_type_mux_library_rec(mux_lib, circuit_lib, type_descriptors[itype].pb_type); - } - } - - /* Step 3: count the size of multiplexer that will be used in LUTs*/ - build_lut_mux_library(mux_lib, circuit_lib); - - return mux_lib; -} - - - diff --git a/vpr7_x2p/vpr/SRC/device/mux_library_builder.h b/vpr7_x2p/vpr/SRC/device/mux_library_builder.h deleted file mode 100644 index ed66ad686..000000000 --- a/vpr7_x2p/vpr/SRC/device/mux_library_builder.h +++ /dev/null @@ -1,18 +0,0 @@ -/******************************************************************** - * This file includes the function declaration of builders - * for MuxLibrary. - * See details in mux_library_builder.cpp - *******************************************************************/ -#ifndef MUX_LIBRARY_BUILDER_H -#define MUX_LIBRARY_BUILDER_H - -#include "vpr_types.h" -#include "circuit_library.h" -#include "mux_library.h" - -MuxLibrary build_device_mux_library(int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_switch_inf* switches, - const CircuitLibrary& circuit_lib, - t_det_routing_arch* routing_arch); - -#endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_library_fwd.h b/vpr7_x2p/vpr/SRC/device/mux_library_fwd.h deleted file mode 100644 index 7bc3091eb..000000000 --- a/vpr7_x2p/vpr/SRC/device/mux_library_fwd.h +++ /dev/null @@ -1,20 +0,0 @@ -/************************************************** - * This file includes only declarations for - * the data structures to describe multiplexer structures - * Please refer to mux_library.h for more details - *************************************************/ -#ifndef MUX_LIBRARY_FWD_H -#define MUX_LIBRARY_FWD_H - -#include "vtr_strong_id.h" - -/* Strong Ids for MUXes */ -struct mux_id_tag; -struct mux_local_decoder_id_tag; - -typedef vtr::StrongId MuxId; -typedef vtr::StrongId MuxLocalDecoderId; - -class MuxLibrary; - -#endif diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp deleted file mode 100644 index 6446cfe8e..000000000 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ /dev/null @@ -1,494 +0,0 @@ -/************************************************** - * This file includes a series of most utilized functions - * that are used to implement a multiplexer - *************************************************/ -#include -#include - -#include "spice_types.h" -#include "util.h" -#include "vtr_assert.h" -#include "decoder_library_utils.h" -#include "mux_utils.h" - -/* Validate the number of inputs for a multiplexer implementation, - * the minimum supported size is 2 - * otherwise, there is no need for a MUX - */ -bool valid_mux_implementation_num_inputs(const size_t& mux_size) { - return (2 <= mux_size); -} - -/************************************************** - * Find the actual number of datapath inputs for a multiplexer implementation - * 1. if there are no requirements on constant inputs, mux_size is the actual one - * 2. if there exist constant inputs, mux_size should minus 1 - * This function is mainly used to recover the number of datapath inputs - * for MUXGraphs which is a generic representation without labelling datapath inputs - *************************************************/ -size_t find_mux_num_datapath_inputs(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size) { - /* Should be either MUX or LUT - * LUTs do have an tree-like MUX, but there is no need for a constant input! - */ - VTR_ASSERT ((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) - || (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) ); - - if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { - return mux_size; - } - - if (true == circuit_lib.mux_add_const_input(circuit_model)) { - return mux_size - 1; - } - return mux_size; -} - -/************************************************** - * Find the actual number of inputs for a multiplexer implementation - * 1. if there are no requirements on constant inputs, mux_size is the actual one - * 2. if there exist constant inputs, mux_size should plus 1 - *************************************************/ -size_t find_mux_implementation_num_inputs(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size) { - /* Should be either MUX or LUT - * LUTs do have an tree-like MUX, but there is no need for a constant input! - */ - VTR_ASSERT ((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) - || (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) ); - - if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { - return mux_size; - } - - if (true == circuit_lib.mux_add_const_input(circuit_model)) { - return mux_size + 1; - } - return mux_size; -} - -/************************************************** - * Find the structure for a multiplexer implementation - * 1. In most cases, the structure should follow the - * mux_structure defined by users in the CircuitLibrary - * 2. However, a special case may apply when mux_size is 2 - * In such case, we will force a TREE structure - * regardless of users' specification as this is the - * most efficient structure - *************************************************/ -enum e_spice_model_structure find_mux_implementation_structure(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size) { - /* Ensure the mux size is valid ! */ - VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); - - /* Branch on the mux sizes */ - if (2 == mux_size) { - /* Tree-like is the best structure of CMOS MUX2 */ - if (SPICE_MODEL_DESIGN_CMOS == circuit_lib.design_tech_type(circuit_model)) { - return SPICE_MODEL_STRUCTURE_TREE; - } - VTR_ASSERT_SAFE(SPICE_MODEL_DESIGN_RRAM == circuit_lib.design_tech_type(circuit_model)); - /* One-level is the best structure of RRAM MUX2 */ - return SPICE_MODEL_STRUCTURE_ONELEVEL; - } - - return circuit_lib.mux_structure(circuit_model); -} - -/************************************************** - * Find the number of levels for a tree-like multiplexer implementation - *************************************************/ -size_t find_treelike_mux_num_levels(const size_t& mux_size) { - /* Do log2(mux_size), have a basic number */ - size_t level = (size_t)(log((double)mux_size)/log(2.)); - /* Fix the error, i.e. mux_size=5, level = 2, we have to complete */ - while (mux_size > pow(2.,(double)level)) { - level++; - } - - return level; -} - -/************************************************** - * Find the number of inputs for majority of branches - * in a multi-level multiplexer implementation - *************************************************/ -size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size, - const size_t& mux_level) { - /* Special Case: mux_size = 2 */ - if (2 == mux_size) { - return mux_size; - } - - if (1 == mux_level) { - return mux_size; - } - - if (2 == mux_level) { - size_t num_input_per_unit = (size_t)sqrt(mux_size); - while ( num_input_per_unit * num_input_per_unit < mux_size) { - num_input_per_unit++; - } - return num_input_per_unit; - } - - VTR_ASSERT_SAFE(2 < mux_level); - - size_t num_input_per_unit = 2; - while (pow((double)num_input_per_unit, (double)mux_level) < mux_size) { - num_input_per_unit++; - } - - if (!valid_mux_implementation_num_inputs(num_input_per_unit)) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Number of inputs of each basis should be at least 2!\n", - __FILE__, __LINE__); - exit(1); - } - - return num_input_per_unit; -} - -/************************************************** - * Build a location map for intermediate buffers - * that may appear at the multiplexing structure of a LUT - * Here is a tricky thing: - * By default, the first and last stage should not exist any intermediate buffers - * For example: - * There are 5 stages in a 4-stage multiplexer is available for buffering - * but only 3 stages [1,2,3] are intermedate buffers - * and these are users' specification - * - * +-------+ +-------+ +-------+ +-------+ - * location | stage | location | stage | location | stage | location | stage | location - * [0] | [0] | [1] | [1] | [2] | [2] | [3] | [3] | [5] - * +-------+ +-------+ +-------+ +-------+ - * - * We will check if the length of location map matches the number of - * multiplexer levels. And then complete a location map - * for the given multiplexers - *************************************************/ -std::vector build_mux_intermediate_buffer_location_map(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& num_mux_levels) { - /* Deposite a default location map */ - std::vector location_map(num_mux_levels, false); - std::string location_map_str; - - /* ONLY for LUTs: intermediate buffers may exist if specified */ - if (SPICE_MODEL_LUT != circuit_lib.model_type(circuit_model)) { - return location_map; - } - - /* Get location map when the flag of intermediate buffer is on */ - if (true == circuit_lib.is_lut_intermediate_buffered(circuit_model)) { - location_map_str = circuit_lib.lut_intermediate_buffer_location_map(circuit_model); - } - - /* If no location map is specified, we can return here */ - if (location_map_str.empty()) { - return location_map; - } - - /* Check if the user-defined location map matches the number of mux levels*/ - VTR_ASSERT(num_mux_levels - 2 == location_map_str.length()); - - /* Apply the location_map string to the intermediate stages of multiplexers */ - for (size_t i = 0; i < location_map_str.length(); ++i) { - /* '1' indicates that an intermediate buffer is needed at the location */ - if ('1' == location_map_str[i]) { - location_map[i + 1] = true; - } - } - - return location_map; -} - -/************************************************** - * Convert a linked list of MUX architecture to MuxLibrary - * TODO: this function will be deleted when MUXLibrary fully - * replace legacy data structures - *************************************************/ -MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llist* muxes_head) { - t_llist* temp = muxes_head; - MuxLibrary mux_lib; - - /* Walk through the linked list */ - while(temp) { - VTR_ASSERT_SAFE(NULL != temp->dptr); - t_spice_mux_model* cur_spice_mux_model = (t_spice_mux_model*)(temp->dptr); - - /* Bypass the spice models who has a user-defined subckt */ - if (NULL != cur_spice_mux_model->spice_model->verilog_netlist) { - /* Move on to the next*/ - temp = temp->next; - continue; - } - - /* Build a MUX graph for the model */ - /* Find the circuit model id by the name */ - CircuitModelId circuit_model = circuit_lib.model(cur_spice_mux_model->spice_model->name); - mux_lib.add_mux(circuit_lib, circuit_model, cur_spice_mux_model->size); - - /* Move on to the next*/ - temp = temp->next; - } - - return mux_lib; -} - -/************************************************** - * Find the number of reserved configuration bits for a multiplexer - * The reserved configuration bits is only used by ReRAM-based multiplexers - * It is actually the shared BL/WLs among ReRAMs - *************************************************/ -size_t find_mux_num_reserved_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph) { - if (SPICE_MODEL_DESIGN_RRAM != circuit_lib.design_tech_type(mux_model)) { - return 0; - } - - std::vector mux_branch_sizes = mux_graph.branch_sizes(); - /* For tree-like multiplexers: they have two shared configuration bits */ - if ( (1 == mux_branch_sizes.size()) - && (2 == mux_branch_sizes[0]) ) { - return mux_branch_sizes[0]; - } - /* One-level multiplexer */ - if ( 1 == mux_graph.num_levels() ) { - return mux_graph.num_inputs(); - } - /* Multi-level multiplexers: TODO: This should be better tested and clarified - * Now the multi-level multiplexers are treated as cascaded one-level multiplexers - * Use the maximum branch sizes and multiply it by the number of levels - */ - std::vector::iterator max_mux_branch_size = std::max_element(mux_branch_sizes.begin(), mux_branch_sizes.end()); - return mux_graph.num_levels() * (*max_mux_branch_size); -} - -/************************************************** - * Find the number of configuration bits for a CMOS multiplexer - * In general, the number of configuration bits is - * the number of memory bits for a mux_graph - * However, when local decoders are used, - * the number of configuration bits are reduced to log2(X) - *************************************************/ -static -size_t find_cmos_mux_num_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph, - const e_sram_orgz& sram_orgz_type) { - size_t num_config_bits = 0; - - switch (sram_orgz_type) { - case SPICE_SRAM_MEMORY_BANK: - case SPICE_SRAM_SCAN_CHAIN: - case SPICE_SRAM_STANDALONE: - num_config_bits = mux_graph.num_memory_bits(); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - - if (false == circuit_lib.mux_use_local_encoder(mux_model)) { - return num_config_bits; - } - - num_config_bits = 0; - /* Multiplexer local encoders are applied to memory bits at each stage */ - for (const auto& lvl : mux_graph.levels()) { - num_config_bits += find_mux_local_decoder_addr_size(mux_graph.num_memory_bits_at_level(lvl)); - } - - return num_config_bits; -} - -/************************************************** - * Find the number of configuration bits for a RRAM multiplexer - * In general, the number of configuration bits is - * the number of levels for a mux_graph - * This is due to only the last BL/WL of the multiplexer is - * independent from each other - * However, when local decoders are used, - * the number of configuration bits should be consider all the - * shared(reserved) configuration bits and independent bits - *************************************************/ -static -size_t find_rram_mux_num_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph, - const e_sram_orgz& sram_orgz_type) { - size_t num_config_bits = 0; - switch (sram_orgz_type) { - case SPICE_SRAM_MEMORY_BANK: - /* In memory bank, by intensively share the Bit/Word Lines, - * we only need 1 additional BL and WL for each MUX level. - */ - num_config_bits = mux_graph.num_levels(); - break; - case SPICE_SRAM_SCAN_CHAIN: - case SPICE_SRAM_STANDALONE: - /* Currently we DO NOT SUPPORT THESE, given an invalid number */ - num_config_bits = size_t(-1); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - - if (true == circuit_lib.mux_use_local_encoder(mux_model)) { - /* TODO: this is a to-do work for ReRAM-based multiplexers and FPGAs - * The number of states of a local decoder only depends on how many - * memory bits that the multiplexer will have - * This may NOT be correct!!! - */ - return find_mux_local_decoder_addr_size(mux_graph.num_memory_bits()); - } - - return num_config_bits; -} - -/************************************************** - * Find the number of configuration bits for - * a routing multiplexer - * Two cases are considered here. - * They are placed in different branches (sub-functions) - * in order to be easy in extending to new technology! - *************************************************/ -size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph, - const e_sram_orgz& sram_orgz_type) { - size_t num_config_bits = size_t(-1); - - switch (circuit_lib.design_tech_type(mux_model)) { - case SPICE_MODEL_DESIGN_CMOS: - num_config_bits = find_cmos_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); - break; - case SPICE_MODEL_DESIGN_RRAM: - num_config_bits = find_rram_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", - __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); - exit(1); - } - - return num_config_bits; -} - -/************************************************** - * Find the number of shared configuration bits for a CMOS multiplexer - * Currently, all the supported CMOS multiplexers - * do NOT require any shared configuration bits - *************************************************/ -static -size_t find_cmos_mux_num_shared_config_bits(const e_sram_orgz& sram_orgz_type) { - size_t num_shared_config_bits = 0; - - switch (sram_orgz_type) { - case SPICE_SRAM_MEMORY_BANK: - case SPICE_SRAM_SCAN_CHAIN: - case SPICE_SRAM_STANDALONE: - num_shared_config_bits = 0; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - - return num_shared_config_bits; -} - -/************************************************** - * Find the number of shared configuration bits for a ReRAM multiplexer - *************************************************/ -static -size_t find_rram_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph, - const e_sram_orgz& sram_orgz_type) { - size_t num_shared_config_bits = 0; - switch (sram_orgz_type) { - case SPICE_SRAM_MEMORY_BANK: { - /* In memory bank, the number of shared configuration bits is - * the sum of largest branch size at each level - */ - for (auto lvl : mux_graph.node_levels()) { - /* Find the maximum branch size: - * Note that branch_sizes() returns a sorted vector - * The last one is the maximum - */ - num_shared_config_bits += mux_graph.branch_sizes(lvl).back(); - } - break; - } - case SPICE_SRAM_SCAN_CHAIN: - case SPICE_SRAM_STANDALONE: - /* Currently we DO NOT SUPPORT THESE, given an invalid number */ - num_shared_config_bits = size_t(-1); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - - if (true == circuit_lib.mux_use_local_encoder(mux_model)) { - /* TODO: this is a to-do work for ReRAM-based multiplexers and FPGAs - * The number of states of a local decoder only depends on how many - * memory bits that the multiplexer will have - * This may NOT be correct!!! - * If local encoders are introduced, zero shared configuration bits are required - */ - return 0; - } - - return num_shared_config_bits; -} - -/************************************************** - * Find the number of shared configuration bits for - * a routing multiplexer - * Two cases are considered here. - * They are placed in different branches (sub-functions) - * in order to be easy in extending to new technology! - * - * Note: currently, shared configuration bits are demanded - * by ReRAM-based multiplexers only - *************************************************/ -size_t find_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph, - const e_sram_orgz& sram_orgz_type) { - size_t num_shared_config_bits = size_t(-1); - - switch (circuit_lib.design_tech_type(mux_model)) { - case SPICE_MODEL_DESIGN_CMOS: - num_shared_config_bits = find_cmos_mux_num_shared_config_bits(sram_orgz_type); - break; - case SPICE_MODEL_DESIGN_RRAM: - num_shared_config_bits = find_rram_mux_num_shared_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", - __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); - exit(1); - } - - return num_shared_config_bits; -} diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.h b/vpr7_x2p/vpr/SRC/device/mux_utils.h deleted file mode 100644 index 04d4ad7ff..000000000 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.h +++ /dev/null @@ -1,54 +0,0 @@ -/************************************************** - * This file includes only declaration for the - * functions in mux_utils.c - * Please refer to the source file for more details - *************************************************/ -#ifndef MUX_UTILS_H -#define MUX_UTILS_H - -#include - -#include "linkedlist.h" -#include "circuit_library.h" -#include "mux_library.h" - -bool valid_mux_implementation_num_inputs(const size_t& mux_size); - -size_t find_mux_num_datapath_inputs(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size); - -size_t find_mux_implementation_num_inputs(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size); - -enum e_spice_model_structure find_mux_implementation_structure(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size); - -size_t find_treelike_mux_num_levels(const size_t& mux_size); - -size_t find_multilevel_mux_branch_num_inputs(const size_t& mux_size, - const size_t& mux_level); - -std::vector build_mux_intermediate_buffer_location_map(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& num_mux_levels); - -MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llist* muxes_head); - -size_t find_mux_num_reserved_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph); - -size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph, - const e_sram_orgz& sram_orgz_type); - -size_t find_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph, - const e_sram_orgz& sram_orgz_type); - -#endif diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/chan_node_details.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/chan_node_details.cpp deleted file mode 100644 index a623e0df3..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/chan_node_details.cpp +++ /dev/null @@ -1,324 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: chan_node_details.cpp - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/06/14 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file contains member functions for class ChanNodeDetails - ***********************************************************************/ -#include -#include -#include "chan_node_details.h" - -/************************************************************************ - * Constructors - ***********************************************************************/ -ChanNodeDetails::ChanNodeDetails(const ChanNodeDetails& src) { - /* duplicate */ - size_t chan_width = src.get_chan_width(); - this->reserve(chan_width); - for (size_t itrack = 0; itrack < chan_width; ++itrack) { - track_node_ids_.push_back(src.get_track_node_id(itrack)); - track_direction_.push_back(src.get_track_direction(itrack)); - seg_ids_.push_back(src.get_track_segment_id(itrack)); - seg_length_.push_back(src.get_track_segment_length(itrack)); - track_start_.push_back(src.is_track_start(itrack)); - track_end_.push_back(src.is_track_end(itrack)); - } -} - -ChanNodeDetails::ChanNodeDetails() { - this->clear(); -} - -/************************************************************************ - * Accessors - ***********************************************************************/ -size_t ChanNodeDetails::get_chan_width() const { - assert(validate_chan_width()); - return track_node_ids_.size(); -} - -size_t ChanNodeDetails::get_track_node_id(size_t track_id) const { - assert(validate_track_id(track_id)); - return track_node_ids_[track_id]; -} - -/* Return a copy of vector */ -std::vector ChanNodeDetails::get_track_node_ids() const { - std::vector copy; - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - copy.push_back(track_node_ids_[inode]); - } - return copy; -} - -e_direction ChanNodeDetails::get_track_direction(size_t track_id) const { - assert(validate_track_id(track_id)); - return track_direction_[track_id]; -} - -size_t ChanNodeDetails::get_track_segment_length(size_t track_id) const { - assert(validate_track_id(track_id)); - return seg_length_[track_id]; -} - -size_t ChanNodeDetails::get_track_segment_id(size_t track_id) const { - assert(validate_track_id(track_id)); - return seg_ids_[track_id]; -} - -bool ChanNodeDetails::is_track_start(size_t track_id) const { - assert(validate_track_id(track_id)); - return track_start_[track_id]; -} - -bool ChanNodeDetails::is_track_end(size_t track_id) const { - assert(validate_track_id(track_id)); - return track_end_[track_id]; -} - -/* Track_id is the starting point of group (whose is_start should be true) - * This function will try to find the track_ids with the same directionality as track_id and seg_length - * A group size is the number of such nodes between the starting points (include the 1st starting point) - */ -std::vector ChanNodeDetails::get_seg_group(size_t track_id) const { - assert(validate_chan_width()); - assert(validate_track_id(track_id)); - assert(is_track_start(track_id)); - - std::vector group; - /* Make sure a clean start */ - group.clear(); - - for (size_t itrack = track_id; itrack < get_chan_width(); ++itrack) { - if ( (get_track_direction(itrack) != get_track_direction(track_id) ) - || (get_track_segment_id(itrack) != get_track_segment_id(track_id)) ) { - /* Bypass any nodes in different direction and segment information*/ - continue; - } - if ( (false == is_track_start(itrack)) - || ( (true == is_track_start(itrack)) && (itrack == track_id)) ) { - group.push_back(itrack); - continue; - } - /* Stop if this another starting point */ - if (true == is_track_start(itrack)) { - break; - } - } - return group; -} - -/* Get a list of track_ids with the given list of track indices */ -std::vector ChanNodeDetails::get_seg_group_node_id(std::vector seg_group) const { - std::vector group; - /* Make sure a clean start */ - group.clear(); - - for (size_t id = 0; id < seg_group.size(); ++id) { - assert(validate_track_id(seg_group[id])); - group.push_back(get_track_node_id(seg_group[id])); - } - - return group; -} - -/* Get the number of tracks that starts in this routing channel */ -size_t ChanNodeDetails::get_num_starting_tracks(enum e_direction track_direction) const { - size_t counter = 0; - for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { - /* Bypass unmatched track_direction */ - if (track_direction != get_track_direction(itrack)) { - continue; - } - if (false == is_track_start(itrack)) { - continue; - } - counter++; - } - return counter; -} - -/* Get the number of tracks that ends in this routing channel */ -size_t ChanNodeDetails::get_num_ending_tracks(enum e_direction track_direction) const { - size_t counter = 0; - for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { - /* Bypass unmatched track_direction */ - if (track_direction != get_track_direction(itrack)) { - continue; - } - if (false == is_track_end(itrack)) { - continue; - } - counter++; - } - return counter; -} - - -/************************************************************************ - * Mutators - ***********************************************************************/ -/* Reserve the capacitcy of vectors */ -void ChanNodeDetails::reserve(size_t chan_width) { - track_node_ids_.reserve(chan_width); - track_direction_.reserve(chan_width); - seg_length_.reserve(chan_width); - seg_ids_.reserve(chan_width); - track_start_.reserve(chan_width); - track_end_.reserve(chan_width); -} - -/* Add a track to the channel */ -void ChanNodeDetails::add_track(size_t track_node_id, e_direction track_direction, size_t seg_id, size_t seg_length, size_t is_start, size_t is_end) { - track_node_ids_.push_back(track_node_id); - track_direction_.push_back(track_direction); - seg_ids_.push_back(seg_id); - seg_length_.push_back(seg_length); - track_start_.push_back(is_start); - track_end_.push_back(is_end); -} - -/* Update the node_id of a given track */ -void ChanNodeDetails::set_track_node_id(size_t track_index, size_t track_node_id) { - assert(validate_track_id(track_index)); - track_node_ids_[track_index] = track_node_id; -} - -/* Update the node_ids from a vector */ -void ChanNodeDetails::set_track_node_ids(std::vector track_node_ids) { - /* the size of vector should match chan_width */ - assert ( get_chan_width() == track_node_ids.size() ); - for (size_t inode = 0; inode < track_node_ids.size(); ++inode) { - track_node_ids_[inode] = track_node_ids[inode]; - } -} - -/* Set tracks with a given direction to start */ -void ChanNodeDetails::set_tracks_start(e_direction track_direction) { - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - /* Bypass non-match tracks */ - if (track_direction != get_track_direction(inode)) { - continue; /* Pass condition*/ - } - track_start_[inode] = true; - } -} - -/* Set tracks with a given direction to end */ -void ChanNodeDetails::set_tracks_end(e_direction track_direction) { - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - /* Bypass non-match tracks */ - if (track_direction != get_track_direction(inode)) { - continue; /* Pass condition*/ - } - track_end_[inode] = true; - } -} - -/* rotate the track_node_id by an offset */ -void ChanNodeDetails::rotate_track_node_id(size_t offset, e_direction track_direction, bool counter_rotate) { - /* Direct return if offset = 0*/ - if (0 == offset) { - return; - } - - /* Rotate the node_ids by groups - * A group begins from a track_start and ends before another track_start - */ - assert(validate_chan_width()); - for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { - /* Bypass non-start segment */ - if (false == is_track_start(itrack) ) { - continue; - } - /* Bypass segments do not match track_direction */ - if (track_direction != get_track_direction(itrack) ) { - continue; - } - /* Find the group nodes */ - std::vector track_group = get_seg_group(itrack); - /* Build a vector of the node ids of the tracks */ - std::vector track_group_node_id = get_seg_group_node_id(track_group); - /* adapt offset to the range of track_group_node_id */ - size_t actual_offset = offset % track_group_node_id.size(); - /* Rotate or Counter rotate */ - if (true == counter_rotate) { - std::rotate(track_group_node_id.rbegin(), track_group_node_id.rbegin() + actual_offset, track_group_node_id.rend()); - } else { - std::rotate(track_group_node_id.begin(), track_group_node_id.begin() + actual_offset, track_group_node_id.end()); - } - /* Update the node_ids */ - for (size_t inode = 0; inode < track_group.size(); ++inode) { - track_node_ids_[track_group[inode]] = track_group_node_id[inode]; - } - } - return; -} - -void ChanNodeDetails::clear() { - track_node_ids_.clear(); - track_direction_.clear(); - seg_ids_.clear(); - seg_length_.clear(); - track_start_.clear(); - track_end_.clear(); -} - -/************************************************************************ - * Validators - ***********************************************************************/ -bool ChanNodeDetails::validate_chan_width() const { - size_t chan_width = track_node_ids_.size(); - if ( (chan_width == track_direction_.size()) - &&(chan_width == seg_ids_.size()) - &&(chan_width == seg_length_.size()) - &&(chan_width == track_start_.size()) - &&(chan_width == track_end_.size()) ) { - return true; - } - return false; -} - -bool ChanNodeDetails::validate_track_id(size_t track_id) const { - if ( (track_id < track_node_ids_.size()) - && (track_id < track_direction_.size()) - && (track_id < seg_ids_.size()) - && (track_id < seg_length_.size()) - && (track_id < track_start_.size()) - && (track_id < track_end_.size()) ) { - return true; - } - return false; -} - diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/chan_node_details.h b/vpr7_x2p/vpr/SRC/device/rr_graph/chan_node_details.h deleted file mode 100644 index a5a5da042..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/chan_node_details.h +++ /dev/null @@ -1,110 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: chan_node_details.h - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/06/11 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file contains a class to model the details of routing node - * in a channel: - * 1. segment information: length, frequency etc. - * 2. starting point of segment - * 3. ending point of segment - * 4. potentail track_id(ptc_num) of each segment - ***********************************************************************/ - -/* IMPORTANT: - * The following preprocessing flags are added to - * avoid compilation error when this headers are included in more than 1 times - */ -#ifndef CHAN_NODE_DETAILS_H -#define CHAN_NODE_DETAILS_H - -/* - * Notes in include header files in a head file - * Only include the neccessary header files - * that is required by the data types in the function/class declarations! - */ -/* Header files should be included in a sequence */ -/* Standard header files required go first */ -#include -#include "vpr_types.h" - -/************************************************************************ - * ChanNodeDetails records segment length, directionality and starting of routing tracks - * +---------------------------------+ - * | Index | Direction | Start Point | - * +---------------------------------+ - * | 0 | --------> | Yes | - * +---------------------------------+ - ***********************************************************************/ - - -class ChanNodeDetails { - public : /* Constructor */ - ChanNodeDetails(const ChanNodeDetails&); /* Duplication */ - ChanNodeDetails(); /* Initilization */ - public: /* Accessors */ - size_t get_chan_width() const; - size_t get_track_node_id(size_t track_id) const; - std::vector get_track_node_ids() const; - e_direction get_track_direction(size_t track_id) const; - size_t get_track_segment_length(size_t track_id) const; - size_t get_track_segment_id(size_t track_id) const; - bool is_track_start(size_t track_id) const; - bool is_track_end(size_t track_id) const; - std::vector get_seg_group(size_t track_id) const; - std::vector get_seg_group_node_id(std::vector seg_group) const; - size_t get_num_starting_tracks(enum e_direction track_direction) const; - size_t get_num_ending_tracks(enum e_direction track_direction) const; - public: /* Mutators */ - void reserve(size_t chan_width); /* Reserve the capacitcy of vectors */ - void add_track(size_t track_node_id, e_direction track_direction, size_t seg_id, size_t seg_length, size_t is_start, size_t is_end); - void set_track_node_id(size_t track_index, size_t track_node_id); - void set_track_node_ids(std::vector track_node_ids); - void set_tracks_start(e_direction track_direction); - void set_tracks_end(e_direction track_direction); - void rotate_track_node_id(size_t offset, e_direction track_direction, bool counter_rotate); /* rotate the track_node_id by an offset */ - void clear(); - private: /* validators */ - bool validate_chan_width() const; - bool validate_track_id(size_t track_id) const; - private: /* Internal data */ - std::vector track_node_ids_; /* indices of each track */ - std::vector track_direction_; /* direction of each track */ - std::vector seg_ids_; /* id of segment of each track */ - std::vector seg_length_; /* Length of each segment */ - std::vector track_start_; /* flag to identify if this is the starting point of the track */ - std::vector track_end_; /* flag to identify if this is the ending point of the track */ -}; - -#endif - diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/gsb_graph.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/gsb_graph.cpp deleted file mode 100644 index b7fd40cb8..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/gsb_graph.cpp +++ /dev/null @@ -1,66 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: rr_graph_gsb.cpp - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/06/12 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file constains the member functions for class GSBConn - ************************************************************************/ - -#include "gsb_graph.h" -#include "vtr_vector_map.h" - -/************************************************************************ - * Constructors for class GSBGraph - ************************************************************************/ -/* Duplicate a object */ -GSBGraph::GSBGraph(const GSBGraph& gsb_graph) { - -} - -GSBGraph::GSBGraph() { - coordinator_.clear(); - -} - - -/************************************************************************ - * Aggregators for class GSBGraph - ************************************************************************/ -/* Accessors: Aggregators */ -GSBGraph::node_range GSBGraph::nodes() const { - return vtr::make_range(node_ids_.begin(), node_ids_.end()); -} - -GSBGraph::edge_range GSBGraph::edges() const { - return vtr::make_range(edge_ids_.begin(), edge_ids_.end()); -} diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/gsb_graph.h b/vpr7_x2p/vpr/SRC/device/rr_graph/gsb_graph.h deleted file mode 100644 index b0c1ed1d3..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/gsb_graph.h +++ /dev/null @@ -1,175 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: gsb_graph.h - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/06/12 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file constains a class to model the connection of a - * General Switch Block (GSB), which is a unified block of Connection Blocks - * and Switch Blocks. - * This block contains - * 1. A switch block - * 2. A X-direction Connection block locates at the left side of the switch block - * 2. A Y-direction Connection block locates at the top side of the switch block - * - * +---------------------------------+ - * IPIN_NODES | Y-direction CB | IPIN_NODES - * | [x][y + 1] | - * +---------------------------------+ - * - * IPIN_NODES TOP SIDE - * +-------------+ +---------------------------------+ - * | | | OPIN_NODE CHAN_NODES OPIN_NODES | - * | | | | - * | | | OPIN_NODES OPIN_NODES | - * | X-direction | | | - * | CB | LEFT SIDE | Switch Block | RIGHT SIDE - * | [x][y] | | [x][y] | - * | | | | - * | | | CHAN_NODES CHAN_NODES | - * | | | | - * | | | OPIN_NODES OPIN_NODES | - * | | | | - * | | | OPIN_NODE CHAN_NODES OPIN_NODES | - * +-------------+ +---------------------------------+ - * IPIN_NODES BOTTOM SIDE - * - ***********************************************************************/ - -/* IMPORTANT: - * The following preprocessing flags are added to - * avoid compilation error when this headers are included in more than 1 times - */ -#ifndef GSB_GRAPH_H -#define GSB_GRAPH_H - -/* - * Notes in include header files in a head file - * Only include the neccessary header files - * that is required by the data types in the function/class declarations! - */ -/* Header files should be included in a sequence */ -/* Standard header files required go first */ -#include - -/* External library header files */ -#include "vtr_vector.h" -#include "vtr_range.h" - -#include "device_coordinator.h" -#include "vpr_types.h" -#include "rr_graph_fwd.h" - -/* Define open nodes */ -#define OPEN_NODE_ID RRNodeId(-1) -#define OPEN_EDGE_ID RREdgeId(-1) -#define OPEN_SEGMENT_ID RRSegmentId(-1) - -/*********************************************************************** - * This data structure focuses on modeling the internal pin-to-pin connections. - * It is basically a collection of nodes and edges. - * To make the data structure general, the nodes and edges are not linked to any another data - * structures. - * - * node_ids_: a collection of nodes (basically ids) modelling routing tracks - * which locate at each side of the GSB <0..num_nodes_per_side-1> - * - * node_directions_: Indicate if this node is an input or an output of the GSB - * <0..num_nodes_per_side-1> - * - * node_types_: specify the types of the node, CHANX|CHANY|IPIN|OPIN - * - * node_sides_: specify the sides of the node on a GSB, TOP|RIGHT|BOTTOM|LEFT - * - * node_grid_sides_: specify the side of the node on which side of a GRID - * for CHANX and CHANY, it is an invalid value - * <0..num_nodes_per_side-1> - * - * node_in_edges_: indcies of input edges of a node - * <0..num_nodes><0..num_input_edgess-1> - * - * node_out_edges_: indcies of output edges of a node - * <0..num_nodes><0..num_output_edges-1> - * - * edge_ids_: a collection of indices of edges, <0..num_edges-1>, which connects the nodes - * - * edge_src_nodes_: indcies of input nodes of an edge (driving nodes for each edge) - * <0..num_input_nodes-1> - * - * edge_sink_nodes_: indices of output nodes of an edge (fan-out nodes for each edge) - * <0..num_output_nodes-1> - * - ***********************************************************************/ - -class GSBGraph { - public: /* Types */ - typedef vtr::vector::const_iterator node_iterator; - typedef vtr::vector::const_iterator edge_iterator; - typedef vtr::Range node_range; - typedef vtr::Range edge_range; - public: /* Constructors */ - GSBGraph(const GSBGraph&); /* A constructor to duplicate */ - GSBGraph(); - public: /* Accessors */ - /* Aggregates */ - node_range nodes() const; - edge_range edges() const; - public: /* Coordinator generation */ - public: /* Accessors */ - public: /* Mutators */ - private: /* Internal Data */ - /* Coordinator of this GSB */ - DeviceCoordinator coordinator_; - - /* nodes on each side */ - vtr::vector node_ids_; - vtr::vector node_types_; - vtr::vector node_sides_; - vtr::vector node_directions_; - vtr::vector node_grid_sides_; - vtr::vector node_segment_ids_; - - vtr::vector> node_in_edges; - vtr::vector> node_out_edges; - - /* edges */ - vtr::vector edge_ids_; - vtr::vector edge_src_nodes_; /* each element is a node_id */ - vtr::vector edge_sink_nodes_; /* each element is a node_id */ - - /* fast look-up [node_side][node_type][node_id] */ - typedef std::vector< std::vector< std::vector > > NodeLookup; - mutable NodeLookup node_lookup_; -}; - -#endif - diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp deleted file mode 100644 index 167d6d161..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp +++ /dev/null @@ -1,714 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: rr_graph_builder_utils.cpp - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/06/23 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file contains most utilized functions for rr_graph builders - ***********************************************************************/ - -#include -#include -#include - -#include -#include - -#include "rr_graph_builder_utils.h" -#include "globals.h" - -/************************************************************************ - * Initialize a rr_node - ************************************************************************/ -void tileable_rr_graph_init_rr_node(t_rr_node* cur_rr_node) { - cur_rr_node->xlow = 0; - cur_rr_node->xhigh = 0; - cur_rr_node->ylow = 0; - cur_rr_node->xhigh = 0; - - cur_rr_node->ptc_num = 0; - cur_rr_node->track_ids.clear(); - - cur_rr_node->cost_index = 0; - cur_rr_node->occ = 0; - cur_rr_node->fan_in = 0; - cur_rr_node->num_edges = 0; - cur_rr_node->type = NUM_RR_TYPES; - cur_rr_node->edges = NULL; - cur_rr_node->switches = NULL; - - cur_rr_node->driver_switch = 0; - cur_rr_node->unbuf_switched = 0; - cur_rr_node->buffered = 0; - cur_rr_node->R = 0.; - cur_rr_node->C = 0.; - - cur_rr_node->direction = BI_DIRECTION; /* Give an invalid value, easy to check errors */ - cur_rr_node->drivers = SINGLE; - cur_rr_node->num_wire_drivers = 0; - cur_rr_node->num_opin_drivers = 0; - - cur_rr_node->num_drive_rr_nodes = 0; - cur_rr_node->drive_rr_nodes = NULL; - cur_rr_node->drive_switches = NULL; - - cur_rr_node->vpack_net_num_changed = FALSE; - cur_rr_node->is_parasitic_net = FALSE; - cur_rr_node->is_in_heap = FALSE; - - cur_rr_node->sb_num_drive_rr_nodes = 0; - cur_rr_node->sb_drive_rr_nodes = NULL; - cur_rr_node->sb_drive_switches = NULL; - - cur_rr_node->pb = NULL; - - cur_rr_node->name_mux = NULL; - cur_rr_node->id_path = -1; - - cur_rr_node->prev_node = -1; - cur_rr_node->prev_edge = -1; - cur_rr_node->net_num = -1; - cur_rr_node->vpack_net_num = -1; - - cur_rr_node->prev_node_in_pack = -1; - cur_rr_node->prev_edge_in_pack = -1; - cur_rr_node->net_num_in_pack = -1; - - cur_rr_node->pb_graph_pin = NULL; - cur_rr_node->tnode = NULL; - - cur_rr_node->pack_intrinsic_cost = 0.; - cur_rr_node->z = 0; - - return; -} - - -/************************************************************************ - * Get the class index of a grid pin - ***********************************************************************/ -int get_grid_pin_class_index(const t_grid_tile& cur_grid, - const int pin_index) { - /* check */ - assert ( pin_index < cur_grid.type->num_pins); - return cur_grid.type->pin_class[pin_index]; -} - -/* Deteremine the side of a io grid */ -enum e_side determine_io_grid_pin_side(const DeviceCoordinator& device_size, - const DeviceCoordinator& grid_coordinator) { - /* TOP side IO of FPGA */ - if (device_size.get_y() == grid_coordinator.get_y()) { - return BOTTOM; /* Such I/O has only Bottom side pins */ - } else if (device_size.get_x() == grid_coordinator.get_x()) { /* RIGHT side IO of FPGA */ - return LEFT; /* Such I/O has only Left side pins */ - } else if (0 == grid_coordinator.get_y()) { /* BOTTOM side IO of FPGA */ - return TOP; /* Such I/O has only Top side pins */ - } else if (0 == grid_coordinator.get_x()) { /* LEFT side IO of FPGA */ - return RIGHT; /* Such I/O has only Right side pins */ - } else { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) I/O Grid is in the center part of FPGA! Currently unsupported!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/************************************************************************ - * Get a list of pin_index for a grid (either OPIN or IPIN) - * For IO_TYPE, only one side will be used, we consider one side of pins - * For others, we consider all the sides - ***********************************************************************/ -std::vector get_grid_side_pins(const t_grid_tile& cur_grid, - const enum e_pin_type pin_type, - const enum e_side pin_side, - const int pin_height) { - std::vector pin_list; - /* Make sure a clear start */ - pin_list.clear(); - - for (int ipin = 0; ipin < cur_grid.type->num_pins; ++ipin) { - int class_id = cur_grid.type->pin_class[ipin]; - if ( (1 == cur_grid.type->pinloc[pin_height][pin_side][ipin]) - && (pin_type == cur_grid.type->class_inf[class_id].type) ) { - pin_list.push_back(ipin); - } - } - return pin_list; -} - -/************************************************************************ - * Get the number of pins for a grid (either OPIN or IPIN) - * For IO_TYPE, only one side will be used, we consider one side of pins - * For others, we consider all the sides - ***********************************************************************/ -size_t get_grid_num_pins(const t_grid_tile& cur_grid, - const enum e_pin_type pin_type, - const enum e_side io_side) { - size_t num_pins = 0; - Side io_side_manager(io_side); - - /* For IO_TYPE sides */ - for (size_t side = 0; side < NUM_SIDES; ++side) { - Side side_manager(side); - /* skip unwanted sides */ - if ( (IO_TYPE == cur_grid.type) - && (side != io_side_manager.to_size_t()) ) { - continue; - } - /* Get pin list */ - for (int height = 0; height < cur_grid.type->height; ++height) { - std::vector pin_list = get_grid_side_pins(cur_grid, pin_type, side_manager.get_side(), height); - num_pins += pin_list.size(); - } - } - - return num_pins; -} - -/************************************************************************ - * Get the number of pins for a grid (either OPIN or IPIN) - * For IO_TYPE, only one side will be used, we consider one side of pins - * For others, we consider all the sides - ***********************************************************************/ -size_t get_grid_num_classes(const t_grid_tile& cur_grid, - const enum e_pin_type pin_type) { - size_t num_classes = 0; - - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { - /* Bypass unmatched pin_type */ - if (pin_type != cur_grid.type->class_inf[iclass].type) { - continue; - } - num_classes++; - } - - return num_classes; -} - - - -/************************************************************************ - * Add a edge connecting two rr_nodes - * For src rr_node, update the edge list and update switch_id, - * For des rr_node, update the fan_in - ***********************************************************************/ -void add_one_edge_for_two_rr_nodes(const t_rr_graph* rr_graph, - const int src_rr_node_id, - const int des_rr_node_id, - const short switch_id) { - /* Check */ - assert ( (-1 < src_rr_node_id) && (src_rr_node_id < rr_graph->num_rr_nodes) ); - assert ( (-1 < des_rr_node_id) && (des_rr_node_id < rr_graph->num_rr_nodes) ); - - t_rr_node* src_rr_node = &(rr_graph->rr_node[src_rr_node_id]); - t_rr_node* des_rr_node = &(rr_graph->rr_node[des_rr_node_id]); - - /* Allocate edge and switch to src_rr_node */ - src_rr_node->num_edges++; - if (NULL == src_rr_node->edges) { - /* calloc */ - src_rr_node->edges = (int*) my_calloc( src_rr_node->num_edges, sizeof(int) ); - src_rr_node->switches = (short*) my_calloc( src_rr_node->num_edges, sizeof(short) ); - } else { - /* realloc */ - src_rr_node->edges = (int*) my_realloc(src_rr_node->edges, - src_rr_node->num_edges * sizeof(int)); - src_rr_node->switches = (short*) my_realloc(src_rr_node->switches, - src_rr_node->num_edges * sizeof(short)); - } - /* Fill edge and switch info */ - src_rr_node->edges[src_rr_node->num_edges - 1] = des_rr_node_id; - src_rr_node->switches[src_rr_node->num_edges - 1] = switch_id; - - /* Update the des_rr_node */ - des_rr_node->fan_in++; - - return; -} - - -/************************************************************************ - * Add a set of edges for a source rr_node - * For src rr_node, update the edge list and update switch_id, - * For des rr_node, update the fan_in - ***********************************************************************/ -void add_edges_for_two_rr_nodes(const t_rr_graph* rr_graph, - const int src_rr_node_id, - const std::vector des_rr_node_ids, - const std::vector driver_switches) { - /* Check src_rr_node id is in range */ - assert ( (-1 < src_rr_node_id) && (src_rr_node_id < rr_graph->num_rr_nodes) ); - - t_rr_node* src_rr_node = &(rr_graph->rr_node[src_rr_node_id]); - - /* Check des_rr_node and driver_switches should match in size */ - assert ( des_rr_node_ids.size() == driver_switches.size() ); - - /* Get a stamp of the current num_edges of src_rr_node */ - int start_edge_id = src_rr_node->num_edges; - - /* To avoid adding redundant edges, - * we will search the edge list and - * check if each des_rr_node_id already exists - * We rebuild a vector des_rr_node_ids_to_add where redundancy is removed - */ - std::vector des_rr_node_ids_to_add; - std::vector driver_switches_to_add; - for (size_t inode = 0; inode < des_rr_node_ids.size(); ++inode) { - /* search */ - bool is_redundant = false; - for (int iedge = 0; iedge < src_rr_node->num_edges; ++iedge) { - if (des_rr_node_ids[inode] == src_rr_node->edges[iedge]) { - is_redundant = true; - break; - } - } - /* add or skip */ - if (true == is_redundant) { - continue; /* go to the next */ - } - assert (false == is_redundant); - /* add to the list */ - des_rr_node_ids_to_add.push_back(des_rr_node_ids[inode]); - driver_switches_to_add.push_back(driver_switches[inode]); - } - - /* Allocate edge and switch to src_rr_node */ - src_rr_node->num_edges += des_rr_node_ids_to_add.size(); - if (NULL == src_rr_node->edges) { - /* calloc */ - src_rr_node->edges = (int*) my_calloc( src_rr_node->num_edges, sizeof(int) ); - src_rr_node->switches = (short*) my_calloc( src_rr_node->num_edges, sizeof(short) ); - } else { - /* realloc */ - src_rr_node->edges = (int*) my_realloc(src_rr_node->edges, - src_rr_node->num_edges * sizeof(int)); - src_rr_node->switches = (short*) my_realloc(src_rr_node->switches, - src_rr_node->num_edges * sizeof(short)); - } - - for (size_t inode = 0; inode < des_rr_node_ids_to_add.size(); ++inode) { - /* Check des_rr_node id is in range */ - int des_rr_node_id = des_rr_node_ids_to_add[inode]; - assert ( (-1 < des_rr_node_id) && (des_rr_node_id < rr_graph->num_rr_nodes) ); - - t_rr_node* des_rr_node = &(rr_graph->rr_node[des_rr_node_id]); - - /* Fill edge and switch info */ - src_rr_node->edges[start_edge_id] = des_rr_node_id; - src_rr_node->switches[start_edge_id] = driver_switches_to_add[inode]; - - /* Update the des_rr_node */ - des_rr_node->fan_in++; - /* Increment the start_edge_id */ - start_edge_id++; - } - - /* Check */ - assert( start_edge_id == src_rr_node->num_edges ); - - return; - -} - -/************************************************************************ - * Get the track_id of a routing track w.r.t its coordinator - * In tileable routing architecture, the track_id changes SB by SB. - * Therefore the track_ids are stored in a vector, indexed by the relative coordinator - * based on the starting point of the track - * For routing tracks in INC_DIRECTION - * (xlow, ylow) should be the starting point - * - * (xlow, ylow) (xhigh, yhigh) - * track_id[0] -------------------------------> track_id[xhigh - xlow + yhigh - ylow] - * - * For routing tracks in DEC_DIRECTION - * (xhigh, yhigh) should be the starting point - * - * (xlow, ylow) (xhigh, yhigh) - * track_id[0] <------------------------------- track_id[xhigh - xlow + yhigh - ylow] - * - * - ***********************************************************************/ -short get_rr_node_actual_track_id(const t_rr_node* track_rr_node, - const DeviceCoordinator& coord) { - DeviceCoordinator low_coord(track_rr_node->xlow, track_rr_node->ylow); - size_t offset = (int)abs((int)coord.get_x() - (int)low_coord.get_x() + (int)coord.get_y() - (int)low_coord.get_y()); - return track_rr_node->track_ids[offset]; -} - - -/************************************************************************ - * Get the coordinator of a starting point of a routing track - * For routing tracks in INC_DIRECTION - * (xlow, ylow) should be the starting point - * - * For routing tracks in DEC_DIRECTION - * (xhigh, yhigh) should be the starting point - ***********************************************************************/ -DeviceCoordinator get_track_rr_node_start_coordinator(const t_rr_node* track_rr_node) { - /* Make sure we have CHANX or CHANY */ - assert ( (CHANX == track_rr_node->type) ||(CHANY == track_rr_node->type) ); - - DeviceCoordinator start_coordinator; - - if (INC_DIRECTION == track_rr_node->direction) { - start_coordinator.set(track_rr_node->xlow, track_rr_node->ylow); - } else { - assert (DEC_DIRECTION == track_rr_node->direction); - start_coordinator.set(track_rr_node->xhigh, track_rr_node->yhigh); - } - - return start_coordinator; -} - -/************************************************************************ - * Get the coordinator of a end point of a routing track - * For routing tracks in INC_DIRECTION - * (xhigh, yhigh) should be the starting point - * - * For routing tracks in DEC_DIRECTION - * (xlow, ylow) should be the starting point - ***********************************************************************/ -DeviceCoordinator get_track_rr_node_end_coordinator(const t_rr_node* track_rr_node) { - /* Make sure we have CHANX or CHANY */ - assert ( (CHANX == track_rr_node->type) ||(CHANY == track_rr_node->type) ); - - DeviceCoordinator end_coordinator; - - if (INC_DIRECTION == track_rr_node->direction) { - end_coordinator.set(track_rr_node->xhigh, track_rr_node->yhigh); - } else { - assert (DEC_DIRECTION == track_rr_node->direction); - end_coordinator.set(track_rr_node->xlow, track_rr_node->ylow); - } - - return end_coordinator; -} - -/************************************************************************ - * Get the ptc of a routing track in the channel where it ends - * For routing tracks in INC_DIRECTION - * the ptc is the last of track_ids - * - * For routing tracks in DEC_DIRECTION - * the ptc is the first of track_ids - ***********************************************************************/ -short get_track_rr_node_end_track_id(const t_rr_node* track_rr_node) { - /* Make sure we have CHANX or CHANY */ - assert ( (CHANX == track_rr_node->type) ||(CHANY == track_rr_node->type) ); - - if (INC_DIRECTION == track_rr_node->direction) { - return track_rr_node->track_ids.back(); - } - assert (DEC_DIRECTION == track_rr_node->direction); - return track_rr_node->track_ids.front(); -} - -/************************************************************************ - * Print statistics of a rr_graph - * 1. We print number of nodes by types - * 2. Print the number of edges - ************************************************************************/ -void print_rr_graph_stats(const t_rr_graph& rr_graph) { - - /* Print number of nodes */ - vpr_printf(TIO_MESSAGE_INFO, "Statistics on number of RR nodes (by node type): \n"); - - /* Count the number of nodes */ - std::vector num_nodes_per_type; - num_nodes_per_type.resize(NUM_RR_TYPES); - num_nodes_per_type.assign(NUM_RR_TYPES, 0); - - for (int inode = 0; inode < rr_graph.num_rr_nodes; ++inode) { - num_nodes_per_type[rr_graph.rr_node[inode].type]++; - } - - /* Get the largest string size of rr_node_typename */ - size_t max_str_typename = 0; - for (int type = 0; type < NUM_RR_TYPES; ++type) { - max_str_typename = std::max(max_str_typename, strlen(rr_node_typename[type])); - } - - /* Constant strings */ - char* type_str = " Type "; - char* total_str = " Total "; - char* node_str = " No. of nodes "; - char* edge_str = " No. of edges "; - - /* Count the number of characters per line: - * we check the string length of each node type - * Then we plus two reserved strings "type" and "total" - */ - size_t num_char_per_line = 0; - for (int type = 0; type < NUM_RR_TYPES; ++type) { - num_char_per_line += 6 + max_str_typename; - } - num_char_per_line += strlen(type_str); - num_char_per_line += strlen(total_str); - - /* Print splitter */ - for (size_t ichar = 0; ichar < num_char_per_line; ++ichar) { - vpr_printf(TIO_MESSAGE_INFO, "-"); - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - /* Print node type */ - vpr_printf(TIO_MESSAGE_INFO, "%s", type_str); - for (int type = 0; type < NUM_RR_TYPES; ++type) { - vpr_printf(TIO_MESSAGE_INFO, " %s ", rr_node_typename[type]); - } - vpr_printf(TIO_MESSAGE_INFO, "%s", total_str); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - /* Print node numbers */ - int total_num_nodes = 0; - vpr_printf(TIO_MESSAGE_INFO, "%s", node_str); - for (int type = 0; type < NUM_RR_TYPES; ++type) { - vpr_printf(TIO_MESSAGE_INFO, " %10lu ", num_nodes_per_type[type]); - total_num_nodes += num_nodes_per_type[type]; - } - vpr_printf(TIO_MESSAGE_INFO, " %10lu ", rr_graph.num_rr_nodes); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - /* Check we have the same number as stated in rr_graph */ - assert (total_num_nodes == rr_graph.num_rr_nodes); - - /* Count the number of edges */ - size_t num_edges = 0; - std::vector num_edges_per_type; - num_edges_per_type.resize(NUM_RR_TYPES); - num_edges_per_type.assign(NUM_RR_TYPES, 0); - - for (int inode = 0; inode < rr_graph.num_rr_nodes; ++inode) { - num_edges_per_type[rr_graph.rr_node[inode].type] += rr_graph.rr_node[inode].num_edges; - } - for (int inode = 0; inode < rr_graph.num_rr_nodes; ++inode) { - num_edges += rr_graph.rr_node[inode].num_edges; - } - - /* Print number of edges */ - vpr_printf(TIO_MESSAGE_INFO, "%s", edge_str); - for (int type = 0; type < NUM_RR_TYPES; ++type) { - vpr_printf(TIO_MESSAGE_INFO, " %10lu ", num_edges_per_type[type]); - } - vpr_printf(TIO_MESSAGE_INFO, " %10lu ", num_edges); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - /* Print splitter */ - for (size_t ichar = 0; ichar < num_char_per_line; ++ichar) { - vpr_printf(TIO_MESSAGE_INFO, "-"); - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - return; -} - -/************************************************************************ - * Print statistics of a rr_graph - * 1. We print number of nodes by types - * 2. Print the number of edges - ************************************************************************/ -void print_rr_graph_stats() { - - /* Print number of nodes */ - vpr_printf(TIO_MESSAGE_INFO, "Statistics on number of RR nodes (by node type): \n"); - - /* Count the number of nodes */ - std::vector num_nodes_per_type; - num_nodes_per_type.resize(NUM_RR_TYPES); - num_nodes_per_type.assign(NUM_RR_TYPES, 0); - - for (int inode = 0; inode < num_rr_nodes; ++inode) { - num_nodes_per_type[rr_node[inode].type]++; - } - - /* Get the largest string size of rr_node_typename */ - size_t max_str_typename = 0; - for (int type = 0; type < NUM_RR_TYPES; ++type) { - max_str_typename = std::max(max_str_typename, strlen(rr_node_typename[type])); - } - - /* Constant strings */ - char* type_str = " Type "; - char* total_str = " Total "; - char* node_str = " No. of nodes "; - char* edge_str = " No. of edges "; - - /* Count the number of characters per line: - * we check the string length of each node type - * Then we plus two reserved strings "type" and "total" - */ - size_t num_char_per_line = 0; - for (int type = 0; type < NUM_RR_TYPES; ++type) { - num_char_per_line += 6 + max_str_typename; - } - num_char_per_line += strlen(type_str); - num_char_per_line += strlen(total_str); - - /* Print splitter */ - for (size_t ichar = 0; ichar < num_char_per_line; ++ichar) { - vpr_printf(TIO_MESSAGE_INFO, "-"); - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - /* Print node type */ - vpr_printf(TIO_MESSAGE_INFO, "%s", type_str); - for (int type = 0; type < NUM_RR_TYPES; ++type) { - vpr_printf(TIO_MESSAGE_INFO, " %s ", rr_node_typename[type]); - } - vpr_printf(TIO_MESSAGE_INFO, "%s", total_str); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - /* Print node numbers */ - int total_num_nodes = 0; - vpr_printf(TIO_MESSAGE_INFO, "%s", node_str); - for (int type = 0; type < NUM_RR_TYPES; ++type) { - vpr_printf(TIO_MESSAGE_INFO, " %10lu ", num_nodes_per_type[type]); - total_num_nodes += num_nodes_per_type[type]; - } - vpr_printf(TIO_MESSAGE_INFO, " %10lu ", num_rr_nodes); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - /* Check we have the same number as stated in rr_graph */ - assert (total_num_nodes == num_rr_nodes); - - /* Count the number of edges */ - size_t num_edges = 0; - std::vector num_edges_per_type; - num_edges_per_type.resize(NUM_RR_TYPES); - num_edges_per_type.assign(NUM_RR_TYPES, 0); - - for (int inode = 0; inode < num_rr_nodes; ++inode) { - num_edges_per_type[rr_node[inode].type] += rr_node[inode].num_edges; - } - for (int inode = 0; inode < num_rr_nodes; ++inode) { - num_edges += rr_node[inode].num_edges; - } - - /* Print number of edges */ - vpr_printf(TIO_MESSAGE_INFO, "%s", edge_str); - for (int type = 0; type < NUM_RR_TYPES; ++type) { - vpr_printf(TIO_MESSAGE_INFO, " %10lu ", num_edges_per_type[type]); - } - vpr_printf(TIO_MESSAGE_INFO, " %10lu ", num_edges); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - /* Print splitter */ - for (size_t ichar = 0; ichar < num_char_per_line; ++ichar) { - vpr_printf(TIO_MESSAGE_INFO, "-"); - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - /* Print MUX size distribution */ - /* Get the maximum SB mux size */ - short max_sb_mux_size = 0; - for (int inode = 0; inode < num_rr_nodes; ++inode) { - /* MUX multiplexers for SBs */ - if ( (CHANX == rr_node[inode].type) - || (CHANY == rr_node[inode].type) ) { - max_sb_mux_size = std::max(rr_node[inode].fan_in, max_sb_mux_size); - } - } - /* Get the minimum SB mux size */ - short min_sb_mux_size = max_sb_mux_size; - for (int inode = 0; inode < num_rr_nodes; ++inode) { - /* MUX multiplexers for SBs */ - if ( (CHANX == rr_node[inode].type) - || (CHANY == rr_node[inode].type) ) { - min_sb_mux_size = std::min(rr_node[inode].fan_in, min_sb_mux_size); - } - } - - /* Get the minimum SB mux size */ - int num_sb_mux = 0; - size_t avg_sb_mux_size = 0; - for (int inode = 0; inode < num_rr_nodes; ++inode) { - /* MUX multiplexers for SBs */ - if ( (CHANX == rr_node[inode].type) - || (CHANY == rr_node[inode].type) ) { - avg_sb_mux_size += rr_node[inode].fan_in; - num_sb_mux++; - } - } - avg_sb_mux_size /= num_sb_mux; - /* Print statistics */ - vpr_printf(TIO_MESSAGE_INFO, "------------------------------------------------\n"); - vpr_printf(TIO_MESSAGE_INFO, "Total No. of Switch Block Multiplexer size:%d\n", num_sb_mux); - vpr_printf(TIO_MESSAGE_INFO, "Maximum Switch Block Multiplexer size:%d\n", max_sb_mux_size); - vpr_printf(TIO_MESSAGE_INFO, "Minimum Switch Block Multiplexer size:%d\n", min_sb_mux_size); - vpr_printf(TIO_MESSAGE_INFO, "Average Switch Block Multiplexer size:%lu\n", avg_sb_mux_size); - vpr_printf(TIO_MESSAGE_INFO, "------------------------------------------------\n"); - - /* Get the maximum SB mux size */ - short max_cb_mux_size = 0; - for (int inode = 0; inode < num_rr_nodes; ++inode) { - /* MUX multiplexers for SBs */ - if (IPIN == rr_node[inode].type) { - max_cb_mux_size = std::max(rr_node[inode].fan_in, max_cb_mux_size); - } - } - /* Get the minimum SB mux size */ - short min_cb_mux_size = max_cb_mux_size; - for (int inode = 0; inode < num_rr_nodes; ++inode) { - /* MUX multiplexers for SBs */ - if (IPIN == rr_node[inode].type) { - min_cb_mux_size = std::min(rr_node[inode].fan_in, min_cb_mux_size); - } - } - - /* Get the minimum SB mux size */ - int num_cb_mux = 0; - size_t avg_cb_mux_size = 0; - for (int inode = 0; inode < num_rr_nodes; ++inode) { - /* MUX multiplexers for SBs */ - if (IPIN == rr_node[inode].type) { - avg_cb_mux_size += rr_node[inode].fan_in; - num_cb_mux++; - } - } - avg_cb_mux_size /= num_cb_mux; - vpr_printf(TIO_MESSAGE_INFO, "------------------------------------------------\n"); - vpr_printf(TIO_MESSAGE_INFO, "Total No. of Connection Block Multiplexer size:%d\n", num_cb_mux); - vpr_printf(TIO_MESSAGE_INFO, "Maximum Connection Block Multiplexer size:%d\n", max_cb_mux_size); - vpr_printf(TIO_MESSAGE_INFO, "Minimum Connection Block Multiplexer size:%d\n", min_cb_mux_size); - vpr_printf(TIO_MESSAGE_INFO, "Average Connection Block Multiplexer size:%lu\n", avg_cb_mux_size); - vpr_printf(TIO_MESSAGE_INFO, "------------------------------------------------\n"); - - - return; -} - -/************************************************************************ - * End of file : rr_graph_builder_utils.cpp - ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.h b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.h deleted file mode 100644 index 5ef5382f3..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.h +++ /dev/null @@ -1,52 +0,0 @@ -#ifndef RR_GRAPH_BUILDER_UTILS_H -#define RR_GRAPH_BUILDER_UTILS_H - -#include "vpr_types.h" -#include "fpga_x2p_types.h" -#include "device_coordinator.h" - -void tileable_rr_graph_init_rr_node(t_rr_node* cur_rr_node); - -int get_grid_pin_class_index(const t_grid_tile& cur_grid, - const int pin_index); - -enum e_side determine_io_grid_pin_side(const DeviceCoordinator& device_size, - const DeviceCoordinator& grid_coordinator); - -std::vector get_grid_side_pins(const t_grid_tile& cur_grid, - const enum e_pin_type pin_type, - const enum e_side pin_side, - const int pin_height); - -size_t get_grid_num_pins(const t_grid_tile& cur_grid, - const enum e_pin_type pin_type, - const enum e_side io_side); - -size_t get_grid_num_classes(const t_grid_tile& cur_grid, - const enum e_pin_type pin_type); - -void add_one_edge_for_two_rr_nodes(const t_rr_graph* rr_graph, - const int src_rr_node_id, - const int des_rr_node_id, - const short switch_id); - -void add_edges_for_two_rr_nodes(const t_rr_graph* rr_graph, - const int src_rr_node_id, - const std::vector des_rr_node, - const std::vector driver_switches); - -short get_rr_node_actual_track_id(const t_rr_node* track_rr_node, - const DeviceCoordinator& coord); - -DeviceCoordinator get_track_rr_node_start_coordinator(const t_rr_node* track_rr_node); - -DeviceCoordinator get_track_rr_node_end_coordinator(const t_rr_node* track_rr_node); - -short get_track_rr_node_end_track_id(const t_rr_node* track_rr_node); - -void print_rr_graph_stats(const t_rr_graph& rr_graph); - -void print_rr_graph_stats(); - -#endif - diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_fwd.h b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_fwd.h deleted file mode 100644 index cd4351f34..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_fwd.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef RR_GRAPH_OBJ_FWD_H -#define RR_GRAPH_OBJ_FWD_H - -#include "vtr_strong_id.h" - -class RRGraph; - -struct rr_node_id_tag; -struct rr_edge_id_tag; -struct rr_switch_id_tag; -struct rr_segment_id_tag; - -typedef vtr::StrongId RRNodeId; -typedef vtr::StrongId RREdgeId; -typedef vtr::StrongId RRSwitchId; -typedef vtr::StrongId RRSegmentId; - -#endif diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.cpp deleted file mode 100644 index c1c5ea611..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.cpp +++ /dev/null @@ -1,274 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: tileable_chan_details_builder.cpp - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/06/23 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file contains a builder for the ChanNodeDetails data structure - * Different from VPR rr_graph builders, this builder aims to create a - * highly regular routing channel. Thus, it is called tileable, - * which brings significant advantage in producing large FPGA fabrics. - ***********************************************************************/ - -#include -#include -#include -#include - -#include "tileable_chan_details_builder.h" - -/************************************************************************ - * Generate the number of tracks for each types of routing segments - * w.r.t. the frequency of each of segments and channel width - * Note that if we dertermine the number of tracks per type using - * chan_width * segment_frequency / total_freq may cause - * The total track num may not match the chan_width, - * therefore, we assign tracks one by one until we meet the frequency requirement - * In this way, we can assign the number of tracks with repect to frequency - ***********************************************************************/ -static -std::vector get_num_tracks_per_seg_type(const size_t chan_width, - const std::vector segment_inf, - const bool use_full_seg_groups) { - std::vector result; - std::vector demand; - /* Make sure a clean start */ - result.resize(segment_inf.size()); - demand.resize(segment_inf.size()); - - /* Scale factor so we can divide by any length - * and still use integers */ - /* Get the sum of frequency */ - size_t scale = 1; - size_t freq_sum = 0; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - scale *= segment_inf[iseg].length; - freq_sum += segment_inf[iseg].frequency; - } - size_t reduce = scale * freq_sum; - - /* Init assignments to 0 and set the demand values */ - /* Get the fraction of each segment type considering the frequency: - * num_track_per_seg = chan_width * (freq_of_seg / sum_freq) - */ - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - result[iseg] = 0; - demand[iseg] = scale * chan_width * segment_inf[iseg].frequency; - if (true == use_full_seg_groups) { - demand[iseg] /= segment_inf[iseg].length; - } - } - - /* check if the sum of num_tracks, matches the chan_width */ - /* Keep assigning tracks until we use them up */ - size_t assigned = 0; - size_t size = 0; - size_t imax = 0; - while (assigned < chan_width) { - /* Find current maximum demand */ - double max = 0; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - if (demand[iseg] > max) { - imax = iseg; - } - max = std::max(demand[iseg], max); - } - - /* Assign tracks to the type and reduce the types demand */ - size = (use_full_seg_groups ? segment_inf[imax].length : 1); - demand[imax] -= reduce; - result[imax] += size; - assigned += size; - } - - /* Undo last assignment if we were closer to goal without it */ - if ((assigned - chan_width) > (size / 2)) { - result[imax] -= size; - } - - return result; -} - -/************************************************************************ - * Adapt the number of channel width to a tileable routing architecture - ***********************************************************************/ -int adapt_to_tileable_route_chan_width(int chan_width, - std::vector segment_infs) { - int tileable_chan_width = 0; - - /* Estimate the number of segments per type by the given ChanW*/ - std::vector num_tracks_per_seg_type = get_num_tracks_per_seg_type(chan_width, - segment_infs, - true); /* Force to use the full segment group */ - /* Sum-up the number of tracks */ - for (size_t iseg = 0; iseg < num_tracks_per_seg_type.size(); ++iseg) { - tileable_chan_width += num_tracks_per_seg_type[iseg]; - } - - return tileable_chan_width; -} - -/************************************************************************ - * Build details of routing tracks in a channel - * The function will - * 1. Assign the segments for each routing channel, - * To be specific, for each routing track, we assign a routing segment. - * The assignment is subject to users' specifications, such as - * a. length of each type of segment - * b. frequency of each type of segment. - * c. routing channel width - * - * 2. The starting point of each segment in the channel will be assigned - * For each segment group with same directionality (tracks have the same length), - * every L track will be a starting point (where L denotes the length of segments) - * In this case, if the number of tracks is not a multiple of L, - * indeed we may have some | Yes | No | - * +---------------------------------------+--------------+ - * | 1 | <--------MUX | Yes | No | - * +---------------------------------------+--------------+ - * | 2 | --------> | No | No | - * +---------------------------------------+--------------+ - * | 3 | <-------- | No | No | - * +---------------------------------------+--------------+ - * | 4 | --------> | No | No | - * +---------------------------------------+--------------+ - * | 5 | <-------- | No | No | - * +---------------------------------------+--------------+ - * | 7 | -------->MUX | No | Yes | - * +---------------------------------------+--------------+ - * | 8 | MUX<-------- | No | Yes | - * +---------------------------------------+--------------+ - * | 9 | MUX--------> | Yes | No | - * +---------------------------------------+--------------+ - * | 10 | <--------MUX | Yes | No | - * +---------------------------------------+--------------+ - * | 11 | -------->MUX | No | Yes | - * +------------------------------------------------------+ - * | 12 | <-------- | No | No | - * +------------------------------------------------------+ - * - * 3. SPECIAL for fringes: TOP|RIGHT|BOTTOM|RIGHT - * if device_side is NUM_SIDES, we assume this channel does not locate on borders - * All segments will start and ends with no exception - * - * 4. IMPORTANT: we should be aware that channel width maybe different - * in X-direction and Y-direction channels!!! - * So we will load segment details for different channels - ***********************************************************************/ -ChanNodeDetails build_unidir_chan_node_details(const size_t chan_width, const size_t max_seg_length, - const enum e_side device_side, - const std::vector segment_inf) { - ChanNodeDetails chan_node_details; - size_t actual_chan_width = chan_width; - /* Correct the chan_width: it should be an even number */ - if (0 != actual_chan_width % 2) { - actual_chan_width++; /* increment it to be even */ - } - assert (0 == actual_chan_width % 2); - - /* Reserve channel width */ - chan_node_details.reserve(chan_width); - /* Return if zero width is forced */ - if (0 == actual_chan_width) { - return chan_node_details; - } - - /* Find the number of segments required by each group */ - std::vector num_tracks = get_num_tracks_per_seg_type(actual_chan_width/2, segment_inf, FALSE); - - /* Add node to ChanNodeDetails */ - size_t cur_track = 0; - for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { - /* segment length will be set to maxium segment length if this is a longwire */ - size_t seg_len = segment_inf[iseg].length; - if (TRUE == segment_inf[iseg].longline) { - seg_len = max_seg_length; - } - for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) { - bool seg_start = false; - bool seg_end = false; - /* Every first track of a group of Length-N wires, we set a starting point */ - if (0 == itrack % seg_len) { - seg_start = true; - } - /* Every last track of a group of Length-N wires or this is the last track in this group, we set an ending point */ - if ( (seg_len - 1 == itrack % seg_len) - || (itrack == num_tracks[iseg] - 1) ) { - seg_end = true; - } - /* Since this is a unidirectional routing architecture, - * Add a pair of tracks, 1 INC_DIRECTION track and 1 DEC_DIRECTION track - */ - chan_node_details.add_track(cur_track, INC_DIRECTION, iseg, seg_len, seg_start, seg_end); - cur_track++; - chan_node_details.add_track(cur_track, DEC_DIRECTION, iseg, seg_len, seg_start, seg_end); - cur_track++; - } - } - /* Check if all the tracks have been satisified */ - assert (cur_track == actual_chan_width); - - /* If this is on the border of a device, segments should start */ - switch (device_side) { - case TOP: - case RIGHT: - /* INC_DIRECTION should all end */ - chan_node_details.set_tracks_end(INC_DIRECTION); - /* DEC_DIRECTION should all start */ - chan_node_details.set_tracks_start(DEC_DIRECTION); - break; - case BOTTOM: - case LEFT: - /* INC_DIRECTION should all start */ - chan_node_details.set_tracks_start(INC_DIRECTION); - /* DEC_DIRECTION should all end */ - chan_node_details.set_tracks_end(DEC_DIRECTION); - break; - case NUM_SIDES: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid device_side!\n", - __FILE__, __LINE__); - exit(1); - } - - return chan_node_details; -} - diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.h b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.h deleted file mode 100644 index 66cfa824a..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef TILEABLE_CHAN_DETAILS_BUILDER_H -#define TILEABLE_CHAN_DETAILS_BUILDER_H - -#include "vpr_types.h" -#include "chan_node_details.h" - -int adapt_to_tileable_route_chan_width(int chan_width, std::vector segment_inf); - -ChanNodeDetails build_unidir_chan_node_details(const size_t chan_width, const size_t max_seg_length, - const enum e_side device_side, - const std::vector segment_inf); - -#endif diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp deleted file mode 100644 index 2e520c0d9..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp +++ /dev/null @@ -1,1130 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: rr_graph_tileable_builder.cpp - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/06/11 | Xifan Tang | Created - * +-------------------------------------+ - * | 2019/07/02 | Xifan Tang | Modified to support SB subtype and SubFs - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file contains a builder for the complex rr_graph data structure - * Different from VPR rr_graph builders, this builder aims to create a - * highly regular rr_graph, where each Connection Block (CB), Switch - * Block (SB) is the same (except for those on the borders). Thus, the - * rr_graph is called tileable, which brings significant advantage in - * producing large FPGA fabrics. - ***********************************************************************/ - -#include -#include -#include -#include -#include - -#include "vtr_ndmatrix.h" - -#include "vpr_types.h" -#include "globals.h" -#include "vpr_utils.h" -#include "rr_graph_util.h" -#include "ReadOptions.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "check_rr_graph.h" -#include "route_common.h" -#include "fpga_x2p_types.h" - -#include "rr_blocks.h" -#include "chan_node_details.h" -#include "device_coordinator.h" - -#include "rr_graph_builder_utils.h" -#include "tileable_chan_details_builder.h" -#include "tileable_rr_graph_gsb.h" -#include "tileable_rr_graph_builder.h" - -/************************************************************************ - * Local data stuctures in the file - ***********************************************************************/ - -/************************************************************************ - * Local function in the file - ***********************************************************************/ - -/************************************************************************ - * Estimate the number of rr_nodes per category: - * CHANX, CHANY, IPIN, OPIN, SOURCE, SINK - ***********************************************************************/ -static -std::vector estimate_num_rr_nodes_per_type(const DeviceCoordinator& device_size, - const std::vector> grids, - const std::vector chan_width, - const std::vector segment_infs) { - std::vector num_rr_nodes_per_type; - /* reserve the vector: - * we have the follow type: - * SOURCE = 0, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES - * NUM_RR_TYPES and INTRA_CLUSTER_EDGE will be 0 - */ - num_rr_nodes_per_type.resize(NUM_RR_TYPES); - /* Make sure a clean start */ - for (size_t i = 0; i < NUM_RR_TYPES; ++i) { - num_rr_nodes_per_type[i] = 0; - } - - /************************************************************************ - * 1. Search the grid and find the number OPINs and IPINs per grid - * Note that the number of SOURCE nodes are the same as OPINs - * and the number of SINK nodes are the same as IPINs - ***********************************************************************/ - for (size_t ix = 0; ix < device_size.get_x(); ++ix) { - for (size_t iy = 0; iy < device_size.get_y(); ++iy) { - /* Skip EMPTY tiles */ - if (EMPTY_TYPE == grids[ix][iy].type) { - continue; - } - /* Skip height>1 tiles (mostly heterogeneous blocks) */ - if (0 < grids[ix][iy].offset) { - continue; - } - enum e_side io_side = NUM_SIDES; - /* If this is the block on borders, we consider IO side */ - if (IO_TYPE == grid[ix][iy].type) { - DeviceCoordinator io_device_size(device_size.get_x() - 1, device_size.get_y() - 1); - DeviceCoordinator grid_coordinator(ix, iy); - io_side = determine_io_grid_pin_side(io_device_size, grid_coordinator); - } - /* get the number of OPINs */ - num_rr_nodes_per_type[OPIN] += get_grid_num_pins(grids[ix][iy], DRIVER, io_side); - /* get the number of IPINs */ - num_rr_nodes_per_type[IPIN] += get_grid_num_pins(grids[ix][iy], RECEIVER, io_side); - /* SOURCE: number of classes whose type is DRIVER */ - num_rr_nodes_per_type[SOURCE] += get_grid_num_classes(grid[ix][iy], DRIVER); - /* SINK: number of classes whose type is RECEIVER */ - num_rr_nodes_per_type[SINK] += get_grid_num_classes(grid[ix][iy], RECEIVER); - } - } - - /************************************************************************ - * 2. Assign the segments for each routing channel, - * To be specific, for each routing track, we assign a routing segment. - * The assignment is subject to users' specifications, such as - * a. length of each type of segment - * b. frequency of each type of segment. - * c. routing channel width - * - * SPECIAL for fringes: - * All segments will start and ends with no exception - * - * IMPORTANT: we should be aware that channel width maybe different - * in X-direction and Y-direction channels!!! - * So we will load segment details for different channels - ***********************************************************************/ - /* For X-direction Channel: CHANX */ - for (size_t iy = 0; iy < device_size.get_y() - 1; ++iy) { - for (size_t ix = 1; ix < device_size.get_x() - 1; ++ix) { - enum e_side chan_side = NUM_SIDES; - /* For LEFT side of FPGA */ - if (1 == ix) { - chan_side = LEFT; - } - /* For RIGHT side of FPGA */ - if (device_size.get_x() - 2 == ix) { - chan_side = RIGHT; - } - ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width[0], device_size.get_x() - 2, chan_side, segment_infs); - /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ - num_rr_nodes_per_type[CHANX] += chanx_details.get_num_starting_tracks(INC_DIRECTION); - /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ - num_rr_nodes_per_type[CHANX] += chanx_details.get_num_ending_tracks(DEC_DIRECTION); - } - } - - /* For Y-direction Channel: CHANX */ - for (size_t ix = 0; ix < device_size.get_x() - 1; ++ix) { - for (size_t iy = 1; iy < device_size.get_y() - 1; ++iy) { - enum e_side chan_side = NUM_SIDES; - /* For LEFT side of FPGA */ - if (1 == iy) { - chan_side = BOTTOM; - } - /* For RIGHT side of FPGA */ - if (device_size.get_y() - 2 == iy) { - chan_side = TOP; - } - ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width[1], device_size.get_y() - 2, chan_side, segment_infs); - /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ - num_rr_nodes_per_type[CHANY] += chany_details.get_num_starting_tracks(INC_DIRECTION); - /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ - num_rr_nodes_per_type[CHANY] += chany_details.get_num_ending_tracks(DEC_DIRECTION); - } - } - - return num_rr_nodes_per_type; -} - -/************************************************************************ - * Configure one rr_node to the fast-look up of a rr_graph - ***********************************************************************/ -static -void load_one_node_to_rr_graph_fast_lookup(t_rr_graph* rr_graph, const int node_index, - const t_rr_type node_type, - const int x, const int y, - const int ptc_num) { - /* check the size of ivec (nelem), - * if the ptc_num exceeds the size limit, we realloc the ivec */ - if (ptc_num + 1 > rr_graph->rr_node_indices[node_type][x][y].nelem) { - rr_graph->rr_node_indices[node_type][x][y].nelem = ptc_num + 1; - rr_graph->rr_node_indices[node_type][x][y].list = (int*) my_realloc(rr_graph->rr_node_indices[node_type][x][y].list, sizeof(int) * (ptc_num + 1)); - } - /* fill the lookup table */ - rr_graph->rr_node_indices[node_type][x][y].list[ptc_num] = node_index; - return; -} - -/************************************************************************ - * Configure rr_nodes for this grid - * coordinators: xlow, ylow, xhigh, yhigh, - * features: capacity, ptc_num (pin_num), - ***********************************************************************/ -static -void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator, - const t_grid_tile& cur_grid, - const enum e_side io_side, - t_rr_graph* rr_graph, - size_t* cur_node_id, - const int wire_to_ipin_switch, const int delayless_switch) { - Side io_side_manager(io_side); - - /* Walk through the height of each grid, - * get pins and configure the rr_nodes */ - for (int height = 0; height < cur_grid.type->height; ++height) { - /* Walk through sides */ - for (size_t side = 0; side < NUM_SIDES; ++side) { - Side side_manager(side); - /* skip unwanted sides */ - if ( (IO_TYPE == cur_grid.type) - && (side != io_side_manager.to_size_t()) ) { - continue; - } - /* Find OPINs */ - /* Configure pins by pins */ - std::vector opin_list = get_grid_side_pins(cur_grid, DRIVER, side_manager.get_side(), height); - for (size_t pin = 0; pin < opin_list.size(); ++pin) { - /* Configure the rr_node for the OPIN */ - rr_graph->rr_node[*cur_node_id].type = OPIN; - rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x(); - rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x(); - rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y(); - rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y() + cur_grid.type->height - 1; - rr_graph->rr_node[*cur_node_id].ptc_num = opin_list[pin]; - rr_graph->rr_node[*cur_node_id].capacity = 1; - rr_graph->rr_node[*cur_node_id].occ = 0; - /* cost index is a FIXED value for OPIN */ - rr_graph->rr_node[*cur_node_id].cost_index = OPIN_COST_INDEX; - /* Switch info */ - rr_graph->rr_node[*cur_node_id].driver_switch = delayless_switch; - /* fill fast look-up table */ - /* If height > 1, we will update fast lookup to twice: - * 1. for the x, y + height. This enable fast fast look-up for node collection in rr_gsb - * 2. for the x, y. This enables fast lookup for SOURCE and SINK nodes drive/driven by the node - */ - load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id, - rr_graph->rr_node[*cur_node_id].type, - rr_graph->rr_node[*cur_node_id].xlow, - rr_graph->rr_node[*cur_node_id].ylow + height, - rr_graph->rr_node[*cur_node_id].ptc_num); - load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id, - rr_graph->rr_node[*cur_node_id].type, - rr_graph->rr_node[*cur_node_id].xlow, - rr_graph->rr_node[*cur_node_id].ylow, - rr_graph->rr_node[*cur_node_id].ptc_num); - /* Update node counter */ - (*cur_node_id)++; - } /* End of loading OPIN rr_nodes */ - /* Find IPINs */ - /* Configure pins by pins */ - std::vector ipin_list = get_grid_side_pins(cur_grid, RECEIVER, side_manager.get_side(), height); - for (size_t pin = 0; pin < ipin_list.size(); ++pin) { - rr_graph->rr_node[*cur_node_id].type = IPIN; - rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x(); - rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x(); - rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y(); - rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y() + cur_grid.type->height - 1; - rr_graph->rr_node[*cur_node_id].ptc_num = ipin_list[pin]; - rr_graph->rr_node[*cur_node_id].capacity = 1; - rr_graph->rr_node[*cur_node_id].occ = 0; - /* cost index is a FIXED value for IPIN */ - rr_graph->rr_node[*cur_node_id].cost_index = IPIN_COST_INDEX; - /* Switch info */ - rr_graph->rr_node[*cur_node_id].driver_switch = wire_to_ipin_switch; - /* fill fast look-up table */ - /* If height > 1, we will update fast lookup to twice: - * 1. for the x, y + height. This enable fast fast look-up for node collection in rr_gsb - * 2. for the x, y. This enables fast lookup for SOURCE and SINK nodes drive/driven by the node - */ - load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id, - rr_graph->rr_node[*cur_node_id].type, - rr_graph->rr_node[*cur_node_id].xlow, - rr_graph->rr_node[*cur_node_id].ylow + height, - rr_graph->rr_node[*cur_node_id].ptc_num); - load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id, - rr_graph->rr_node[*cur_node_id].type, - rr_graph->rr_node[*cur_node_id].xlow, - rr_graph->rr_node[*cur_node_id].ylow, - rr_graph->rr_node[*cur_node_id].ptc_num); - /* Update node counter */ - (*cur_node_id)++; - } /* End of loading IPIN rr_nodes */ - } /* End of side enumeration */ - } /* End of height enumeration */ - - /* No need to Walk through the height of each grid, - * get pins and configure the rr_nodes */ - /* Set a SOURCE or a SINK rr_node for each class */ - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { - /* Set a SINK rr_node for the OPIN */ - if ( DRIVER == cur_grid.type->class_inf[iclass].type) { - rr_graph->rr_node[*cur_node_id].type = SOURCE; - } - if ( RECEIVER == cur_grid.type->class_inf[iclass].type) { - rr_graph->rr_node[*cur_node_id].type = SINK; - } - rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x(); - rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x(); - rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y(); - rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y() + cur_grid.type->height - 1; - rr_graph->rr_node[*cur_node_id].ptc_num = iclass; - /* FIXME: need to confirm if the capacity should be the number of pins in this class*/ - rr_graph->rr_node[*cur_node_id].capacity = cur_grid.type->class_inf[iclass].num_pins; - rr_graph->rr_node[*cur_node_id].occ = 0; - /* cost index is a FIXED value for SOURCE and SINK */ - if (SOURCE == rr_graph->rr_node[*cur_node_id].type) { - rr_graph->rr_node[*cur_node_id].cost_index = SOURCE_COST_INDEX; - } - if (SINK == rr_graph->rr_node[*cur_node_id].type) { - rr_graph->rr_node[*cur_node_id].cost_index = SINK_COST_INDEX; - } - /* Switch info */ - rr_graph->rr_node[*cur_node_id].driver_switch = delayless_switch; - /* TODO: should we set pb_graph_pin here? */ - /* fill fast look-up table */ - load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id, - rr_graph->rr_node[*cur_node_id].type, - rr_graph->rr_node[*cur_node_id].xlow, - rr_graph->rr_node[*cur_node_id].ylow, - rr_graph->rr_node[*cur_node_id].ptc_num); - /* Update node counter */ - (*cur_node_id)++; - } /* End of height enumeration */ - - return; -} - -/************************************************************************ - * Initialize the basic information of routing track rr_nodes - * coordinators: xlow, ylow, xhigh, yhigh, - * features: capacity, track_ids, ptc_num, direction - ***********************************************************************/ -static -void load_one_chan_rr_nodes_basic_info(const DeviceCoordinator& chan_coordinator, - const t_rr_type chan_type, - ChanNodeDetails* chan_details, - const std::vector segment_infs, - const int cost_index_offset, - t_rr_graph* rr_graph, - size_t* cur_node_id) { - /* Check each node_id(potential ptc_num) in the channel : - * If this is a starting point, we set a new rr_node with xlow/ylow, ptc_num - * If this is a ending point, we set xhigh/yhigh and track_ids - * For other nodes, we set changes in track_ids - */ - for (size_t itrack = 0; itrack < chan_details->get_chan_width(); ++itrack) { - /* For INC direction, a starting point requires a new chan rr_node */ - if ( ( (true == chan_details->is_track_start(itrack)) - && (INC_DIRECTION == chan_details->get_track_direction(itrack)) ) - /* For DEC direction, an ending point requires a new chan rr_node */ - || - ( (true == chan_details->is_track_end(itrack)) - && (DEC_DIRECTION == chan_details->get_track_direction(itrack)) ) ) { - /* Use a new chan rr_node */ - rr_graph->rr_node[*cur_node_id].type = chan_type; - rr_graph->rr_node[*cur_node_id].xlow = chan_coordinator.get_x(); - rr_graph->rr_node[*cur_node_id].ylow = chan_coordinator.get_y(); - rr_graph->rr_node[*cur_node_id].direction = chan_details->get_track_direction(itrack); - rr_graph->rr_node[*cur_node_id].ptc_num = itrack; - rr_graph->rr_node[*cur_node_id].track_ids.push_back(itrack); - rr_graph->rr_node[*cur_node_id].capacity = 1; - rr_graph->rr_node[*cur_node_id].occ = 0; - /* assign switch id */ - size_t seg_id = chan_details->get_track_segment_id(itrack); - rr_graph->rr_node[*cur_node_id].driver_switch = segment_infs[seg_id].opin_switch; - /* Update chan_details with node_id */ - chan_details->set_track_node_id(itrack, *cur_node_id); - /* cost index depends on the segment index */ - rr_graph->rr_node[*cur_node_id].cost_index = cost_index_offset + seg_id; - - /* Update node counter */ - (*cur_node_id)++; - /* Finish here, go to next */ - } - - /* For INC direction, an ending point requires an update on xhigh and yhigh */ - if ( ( (true == chan_details->is_track_end(itrack)) - && (INC_DIRECTION == chan_details->get_track_direction(itrack)) ) - || - /* For DEC direction, an starting point requires an update on xlow and ylow */ - ( (true == chan_details->is_track_start(itrack)) - && (DEC_DIRECTION == chan_details->get_track_direction(itrack)) ) ) { - /* Get the node_id */ - size_t rr_node_id = chan_details->get_track_node_id(itrack); - /* Do a quick check, make sure we do not mistakenly modify other nodes */ - assert(chan_type == rr_graph->rr_node[rr_node_id].type); - assert(chan_details->get_track_direction(itrack) == rr_graph->rr_node[rr_node_id].direction); - /* set xhigh/yhigh and push changes to track_ids */ - rr_graph->rr_node[rr_node_id].xhigh = chan_coordinator.get_x(); - rr_graph->rr_node[rr_node_id].yhigh = chan_coordinator.get_y(); - /* Do not update track_ids for length-1 wires, they should have only 1 track_id */ - if ( (rr_graph->rr_node[rr_node_id].xhigh > rr_graph->rr_node[rr_node_id].xlow) - || (rr_graph->rr_node[rr_node_id].yhigh > rr_graph->rr_node[rr_node_id].ylow) ) { - rr_graph->rr_node[rr_node_id].track_ids.push_back(itrack); - } - /* Finish here, go to next */ - } - - /* Finish processing starting and ending tracks */ - if ( (true== chan_details->is_track_start(itrack)) - || (true == chan_details->is_track_end(itrack)) ) { - /* Finish here, go to next */ - continue; - } - /* For other nodes, we get the node_id and just update track_ids */ - /* Ensure those nodes are neither starting nor ending points */ - assert( (false == chan_details->is_track_start(itrack)) - && (false == chan_details->is_track_end(itrack)) ); - /* Get the node_id */ - size_t rr_node_id = chan_details->get_track_node_id(itrack); - /* Do a quick check, make sure we do not mistakenly modify other nodes */ - assert(chan_type == rr_graph->rr_node[rr_node_id].type); - assert(chan_details->get_track_direction(itrack) == rr_graph->rr_node[rr_node_id].direction); - /* Update track_ids */ - rr_graph->rr_node[rr_node_id].track_ids.push_back(itrack); - /* Finish here, go to next */ - } - - for (size_t itrack = 0; itrack < chan_details->get_chan_width(); ++itrack) { - /* fill fast look-up table */ - /* Get node_id */ - int track_node_id = chan_details->get_track_node_id(itrack); - /* CHANY requires a reverted (x,y) in the fast look-up table */ - if (CHANX == chan_type) { - load_one_node_to_rr_graph_fast_lookup(rr_graph, track_node_id, - chan_type, - chan_coordinator.get_y(), - chan_coordinator.get_x(), - itrack); - } - /* CHANX follows a regular (x,y) in the fast look-up table */ - if (CHANY == chan_type) { - load_one_node_to_rr_graph_fast_lookup(rr_graph, track_node_id, - chan_type, - chan_coordinator.get_x(), - chan_coordinator.get_y(), - itrack); - } - } - - return; -} - -/************************************************************************ - * Initialize the basic information of rr_nodes: - * coordinators: xlow, ylow, xhigh, yhigh, - * features: capacity, track_ids, ptc_num, direction - * grid_info : pb_graph_pin - ***********************************************************************/ -static -void load_rr_nodes_basic_info(t_rr_graph* rr_graph, - const DeviceCoordinator& device_size, - const std::vector> grids, - const std::vector chan_width, - const std::vector segment_infs, - const int wire_to_ipin_switch, const int delayless_switch) { - /* counter */ - size_t cur_node_id = 0; - /* configure by node type */ - /* SOURCE, SINK, OPIN and IPIN */ - /************************************************************************ - * Search the grid and find the number OPINs and IPINs per grid - * Note that the number of SOURCE nodes are the same as OPINs - * and the number of SINK nodes are the same as IPINs - ***********************************************************************/ - for (size_t ix = 0; ix < device_size.get_x(); ++ix) { - for (size_t iy = 0; iy < device_size.get_y(); ++iy) { - /* Skip EMPTY tiles */ - if (EMPTY_TYPE == grids[ix][iy].type) { - continue; - } - /* We only build rr_nodes for grids with offset=0 */ - if (0 < grids[ix][iy].offset) { - continue; - } - DeviceCoordinator grid_coordinator(ix, iy); - enum e_side io_side = NUM_SIDES; - /* If this is the block on borders, we consider IO side */ - if (IO_TYPE == grid[ix][iy].type) { - DeviceCoordinator io_device_size(device_size.get_x() - 1, device_size.get_y() - 1); - io_side = determine_io_grid_pin_side(io_device_size, grid_coordinator); - } - /* Configure rr_nodes for this grid */ - load_one_grid_rr_nodes_basic_info(grid_coordinator, grid[ix][iy], io_side, - rr_graph, &cur_node_id, - wire_to_ipin_switch, delayless_switch); - } - } - - /* FIXME: DEBUG CODES TO BE REMOVED - std::vector node_cnt; - node_cnt.resize(NUM_RR_TYPES); - for (int inode = 0; inode < rr_graph->num_rr_nodes; ++inode) { - node_cnt[rr_graph->rr_node[inode].type]++; - } - vpr_printf(TIO_MESSAGE_INFO, "Load basic information to %lu SOURCE NODE.\n", node_cnt[SOURCE]); - vpr_printf(TIO_MESSAGE_INFO, "Load basic information to %lu SINK NODE.\n", node_cnt[SINK]); - vpr_printf(TIO_MESSAGE_INFO, "Load basic information to %lu OPIN NODE.\n", node_cnt[OPIN]); - vpr_printf(TIO_MESSAGE_INFO, "Load basic information to %lu IPIN NODE.\n", node_cnt[IPIN]); - */ - - /* For X-direction Channel: CHANX */ - for (size_t iy = 0; iy < device_size.get_y() - 1; ++iy) { - /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ - std::vector track_node_ids; - /* Make sure a clean start */ - track_node_ids.clear(); - for (size_t ix = 1; ix < device_size.get_x() - 1; ++ix) { - DeviceCoordinator chan_coordinator(ix, iy); - enum e_side chan_side = NUM_SIDES; - /* For LEFT side of FPGA */ - if (1 == ix) { - chan_side = LEFT; - } - /* For RIGHT side of FPGA */ - if (device_size.get_x() - 2 == ix) { - chan_side = RIGHT; - } - ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width[0], device_size.get_x() - 2, chan_side, segment_infs); - /* Force node_ids from the previous chanx */ - if (0 < track_node_ids.size()) { - /* Rotate should be done based on a typical case of routing tracks. - * Tracks on the borders are not regularly started and ended, - * which causes the node_rotation malfunction - */ - ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width[0], device_size.get_x() - 2, NUM_SIDES, segment_infs); - chanx_details_tt.set_track_node_ids(track_node_ids); - - /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */ - /* For INC_DIRECTION, we use clockwise rotation - * node_id A ----> -----> node_id D - * node_id B ----> / ----> node_id A - * node_id C ----> / ----> node_id B - * node_id D ----> ----> node_id C - */ - chanx_details_tt.rotate_track_node_id(1, INC_DIRECTION, true); - /* For DEC_DIRECTION, we use clockwise rotation - * node_id A <----- <----- node_id B - * node_id B <----- \ <----- node_id C - * node_id C <----- \ <----- node_id D - * node_id D <----- <----- node_id A - */ - chanx_details_tt.rotate_track_node_id(1, DEC_DIRECTION, false); - - track_node_ids = chanx_details_tt.get_track_node_ids(); - chanx_details.set_track_node_ids(track_node_ids); - } - - /* Configure CHANX in this channel */ - load_one_chan_rr_nodes_basic_info(chan_coordinator, CHANX, - &chanx_details, - segment_infs, - CHANX_COST_INDEX_START, - rr_graph, &cur_node_id); - /* Get a copy of node_ids */ - track_node_ids = chanx_details.get_track_node_ids(); - } - } - - /* For Y-direction Channel: CHANX */ - for (size_t ix = 0; ix < device_size.get_x() - 1; ++ix) { - /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ - std::vector track_node_ids; - /* Make sure a clean start */ - track_node_ids.clear(); - for (size_t iy = 1; iy < device_size.get_y() - 1; ++iy) { - DeviceCoordinator chan_coordinator(ix, iy); - enum e_side chan_side = NUM_SIDES; - /* For BOTTOM side of FPGA */ - if (1 == iy) { - chan_side = BOTTOM; - } - /* For RIGHT side of FPGA */ - if (device_size.get_y() - 2 == iy) { - chan_side = TOP; - } - ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width[1], device_size.get_y() - 2, chan_side, segment_infs); - /* Force node_ids from the previous chanx */ - if (0 < track_node_ids.size()) { - /* Rotate should be done based on a typical case of routing tracks. - * Tracks on the borders are not regularly started and ended, - * which causes the node_rotation malfunction - */ - ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width[1], device_size.get_y() - 2, NUM_SIDES, segment_infs); - - chany_details_tt.set_track_node_ids(track_node_ids); - /* Rotate the chany_details by an offset of 1*/ - /* For INC_DIRECTION, we use clockwise rotation - * node_id A ----> -----> node_id D - * node_id B ----> / ----> node_id A - * node_id C ----> / ----> node_id B - * node_id D ----> ----> node_id C - */ - chany_details_tt.rotate_track_node_id(1, INC_DIRECTION, true); - /* For DEC_DIRECTION, we use clockwise rotation - * node_id A <----- <----- node_id B - * node_id B <----- \ <----- node_id C - * node_id C <----- \ <----- node_id D - * node_id D <----- <----- node_id A - */ - chany_details_tt.rotate_track_node_id(1, DEC_DIRECTION, false); - - track_node_ids = chany_details_tt.get_track_node_ids(); - chany_details.set_track_node_ids(track_node_ids); - } - /* Configure CHANX in this channel */ - load_one_chan_rr_nodes_basic_info(chan_coordinator, CHANY, - &chany_details, - segment_infs, - CHANX_COST_INDEX_START + segment_infs.size(), - rr_graph, &cur_node_id); - /* Get a copy of node_ids */ - track_node_ids = chany_details.get_track_node_ids(); - } - } - - /* A quick check */ - assert ((int)cur_node_id == rr_graph->num_rr_nodes); - for (int inode = 0; inode < rr_graph->num_rr_nodes; ++inode) { - /* Check: we only support straight wires now. - * CHANY: xlow=xhigh CHANY:ylow=yhigh - */ - if (CHANX == rr_graph->rr_node[inode].type) { - assert (rr_graph->rr_node[inode].ylow == rr_graph->rr_node[inode].yhigh); - assert (rr_graph->rr_node[inode].xlow <= rr_graph->rr_node[inode].xhigh); - } else if (CHANY == rr_graph->rr_node[inode].type) { - assert (rr_graph->rr_node[inode].xlow == rr_graph->rr_node[inode].xhigh); - assert (rr_graph->rr_node[inode].ylow <= rr_graph->rr_node[inode].yhigh); - } else { - assert ( (SOURCE == rr_graph->rr_node[inode].type) - || (SINK == rr_graph->rr_node[inode].type) - || (OPIN == rr_graph->rr_node[inode].type) - || (IPIN == rr_graph->rr_node[inode].type)); - assert (rr_graph->rr_node[inode].xlow == rr_graph->rr_node[inode].xhigh); - assert (rr_graph->rr_node[inode].ylow + grids[rr_graph->rr_node[inode].xlow][rr_graph->rr_node[inode].ylow].type->height - 1 == rr_graph->rr_node[inode].yhigh); - } - } - - /* Reverse the track_ids of CHANX and CHANY nodes in DEC_DIRECTION*/ - for (int inode = 0; inode < rr_graph->num_rr_nodes; ++inode) { - /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */ - if ( (CHANX != rr_graph->rr_node[inode].type) - && (CHANY != rr_graph->rr_node[inode].type) ) { - continue; - } - /* Reach here, we must have a node of CHANX or CHANY */ - if (DEC_DIRECTION != rr_graph->rr_node[inode].direction) { - continue; - } - std::reverse(rr_graph->rr_node[inode].track_ids.begin(), - rr_graph->rr_node[inode].track_ids.end() ); - } - - return; -} - -/************************************************************************ - * Build a fast look-up for the rr_nodes - * it is a 4-dimension array to categorize rr_nodes in terms of - * types, coordinators and ptc_num (feature number) - * The results will be stored in rr_node_indices[type][x][y] - ***********************************************************************/ -static -void alloc_rr_graph_fast_lookup(const DeviceCoordinator& device_size, - t_rr_graph* rr_graph) { - /* Allocates and loads all the structures needed for fast lookups of the * - * index of an rr_node. rr_node_indices is a matrix containing the index * - * of the *first* rr_node at a given (i,j) location. */ - - /* Alloc the lookup table */ - rr_graph->rr_node_indices = (t_ivec ***) my_malloc(sizeof(t_ivec **) * NUM_RR_TYPES); - - /* For OPINs, IPINs, SOURCE, SINKs, CHANX and CHANY */ - for (int type = 0; type < NUM_RR_TYPES; ++type) { - /* Skip SOURCE and OPIN, they will share with SOURCE and SINK - * SOURCE and SINK have unique ptc values so their data can be shared. - * IPIN and OPIN have unique ptc values so their data can be shared. - */ - if ((SOURCE == type) || (OPIN == type) ) { - continue; - } - DeviceCoordinator actual_device_size(device_size); - /* Special for CHANX: we use (y,x) in allocation */ - if (CHANX == type) { - actual_device_size.rotate(); - } - rr_graph->rr_node_indices[type] = (t_ivec **) my_malloc(sizeof(t_ivec *) * actual_device_size.get_x()); - for (size_t i = 0; i < actual_device_size.get_x(); ++i) { - rr_graph->rr_node_indices[type][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * actual_device_size.get_y()); - for (size_t j = 0; j < actual_device_size.get_y(); ++j) { - rr_graph->rr_node_indices[type][i][j].nelem = 0; - rr_graph->rr_node_indices[type][i][j].list = NULL; - } - } - } - - /* SOURCE and SINK have unique ptc values so their data can be shared. - * IPIN and OPIN have unique ptc values so their data can be shared. */ - rr_graph->rr_node_indices[SOURCE] = rr_graph->rr_node_indices[SINK]; - rr_graph->rr_node_indices[OPIN] = rr_graph->rr_node_indices[IPIN]; - - return; -} - -/************************************************************************ - * Build the edges for all the SOURCE and SINKs nodes: - * 1. create edges between SOURCE and OPINs - ***********************************************************************/ -static -void build_rr_graph_edges_for_source_nodes(t_rr_graph* rr_graph, - const std::vector< std::vector > grids) { - for (int inode = 0; inode < rr_graph->num_rr_nodes; ++inode) { - /* Bypass all the non OPIN nodes */ - if (OPIN != rr_graph->rr_node[inode].type) { - continue; - } - /* Now, we have an OPIN node, we get the source node index */ - int xlow = rr_graph->rr_node[inode].xlow; - int ylow = rr_graph->rr_node[inode].ylow; - int src_node_ptc_num = get_grid_pin_class_index(grids[xlow][ylow], - rr_graph->rr_node[inode].ptc_num); - /* 1. create edges between SOURCE and OPINs */ - int src_node_id = get_rr_node_index(xlow, ylow, - SOURCE, src_node_ptc_num, - rr_graph->rr_node_indices); - /* add edges to the src_node */ - add_one_edge_for_two_rr_nodes(rr_graph, src_node_id, inode, - rr_graph->rr_node[inode].driver_switch); - } - return; -} - -/************************************************************************ - * Build the edges for all the SINKs nodes: - * 1. create edges between IPINs and SINKs - ***********************************************************************/ -static -void build_rr_graph_edges_for_sink_nodes(t_rr_graph* rr_graph, - const std::vector< std::vector > grids) { - for (int inode = 0; inode < rr_graph->num_rr_nodes; ++inode) { - /* Bypass all the non IPIN nodes */ - if (IPIN != rr_graph->rr_node[inode].type) { - continue; - } - /* Now, we have an OPIN node, we get the source node index */ - int xlow = rr_graph->rr_node[inode].xlow; - int ylow = rr_graph->rr_node[inode].ylow; - int sink_node_ptc_num = get_grid_pin_class_index(grids[xlow][ylow], - rr_graph->rr_node[inode].ptc_num); - /* 1. create edges between IPINs and SINKs */ - int sink_node_id = get_rr_node_index(xlow, ylow, - SINK, sink_node_ptc_num, - rr_graph->rr_node_indices); - /* add edges to connect the IPIN node to SINK nodes */ - add_one_edge_for_two_rr_nodes(rr_graph, inode, sink_node_id, - rr_graph->rr_node[inode].driver_switch); - } - - return; -} - -/************************************************************************ - * Build the edges of each rr_node tile by tile: - * We classify rr_nodes into a general switch block (GSB) data structure - * where we create edges to each rr_nodes in the GSB with respect to - * Fc_in and Fc_out, switch block patterns - * For each GSB: - * 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks) - * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) - * 3. create edges between OPINs and IPINs (direct-connections) - ***********************************************************************/ -static -void build_rr_graph_edges(t_rr_graph* rr_graph, - const DeviceCoordinator& device_size, - const std::vector< std::vector > grids, - const std::vector device_chan_width, - const std::vector segment_inf, - int** Fc_in, int** Fc_out, - const enum e_switch_block_type sb_type, const int Fs, - const enum e_switch_block_type sb_subtype, const int subFs, - const bool wire_opposite_side) { - - /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ - build_rr_graph_edges_for_source_nodes(rr_graph, grids); - build_rr_graph_edges_for_sink_nodes(rr_graph, grids); - - DeviceCoordinator gsb_range(device_size.get_x() - 2, device_size.get_y() - 2); - - /* Go Switch Block by Switch Block */ - for (size_t ix = 0; ix <= gsb_range.get_x(); ++ix) { - for (size_t iy = 0; iy <= gsb_range.get_y(); ++iy) { - //vpr_printf(TIO_MESSAGE_INFO, "Building edges for GSB[%lu][%lu]\n", ix, iy); - - DeviceCoordinator gsb_coordinator(ix, iy); - /* Create a GSB object */ - RRGSB rr_gsb = build_one_tileable_rr_gsb(gsb_range, device_chan_width, segment_inf, gsb_coordinator, rr_graph); - - /* adapt the track_to_ipin_lookup for the GSB nodes */ - t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ - track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); - - /* adapt the opin_to_track_map for the GSB nodes */ - t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ - opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out); - - /* adapt the switch_block_conn for the GSB nodes */ - t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ - sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, - sb_type, Fs, sb_subtype, subFs, wire_opposite_side, - segment_inf); - - /* Build edges for a GSB */ - build_edges_for_one_tileable_rr_gsb(rr_graph, &rr_gsb, - track2ipin_map, opin2track_map, - sb_conn); - /* Finish this GSB, go to the next*/ - } - } - - return; -} - -/************************************************************************ - * Build direct edges for Grids * - ***********************************************************************/ -static -void build_rr_graph_direct_connections(t_rr_graph* rr_graph, - const DeviceCoordinator& device_size, - const std::vector< std::vector > grids, - const int delayless_switch, - const int num_directs, - const t_direct_inf *directs, - const t_clb_to_clb_directs *clb_to_clb_directs) { - for (size_t ix = 0; ix < device_size.get_x(); ++ix) { - for (size_t iy = 0; iy < device_size.get_y(); ++iy) { - /* Skip EMPTY tiles */ - if (EMPTY_TYPE == grids[ix][iy].type) { - continue; - } - /* Skip height>1 tiles (mostly heterogeneous blocks) */ - if (0 < grids[ix][iy].offset) { - continue; - } - DeviceCoordinator from_grid_coordinator(ix, iy); - build_direct_connections_for_one_gsb(rr_graph, device_size, grids, - from_grid_coordinator, - grids[ix][iy], - delayless_switch, - num_directs, directs, clb_to_clb_directs); - } - } - - return; -} - -/************************************************************************ - * Reset driver switch of a rr_graph - ***********************************************************************/ -static -void clear_rr_graph_driver_switch(const t_rr_graph* rr_graph) { - for (int inode = 0; inode < rr_graph->num_rr_nodes; ++inode) { - rr_graph->rr_node[inode].driver_switch = 0; - } - return; -} - -/************************************************************************ - * Main function of this file - * Builder for a detailed uni-directional tileable rr_graph - * Global graph is not supported here, the VPR rr_graph generator can be used - * It follows the procedures to complete the rr_graph generation - * 1. Assign the segments for each routing channel, - * To be specific, for each routing track, we assign a routing segment. - * The assignment is subject to users' specifications, such as - * a. length of each type of segment - * b. frequency of each type of segment. - * c. routing channel width - * 2. Estimate the number of nodes in the rr_graph - * This will estimate the number of - * a. IPINs, input pins of each grid - * b. OPINs, output pins of each grid - * c. SOURCE, virtual node which drives OPINs - * d. SINK, virtual node which is connected to IPINs - * e. CHANX and CHANY, routing segments of each channel - * 3. Create the connectivity of OPINs - * a. Evenly assign connections to OPINs to routing tracks - * b. the connection pattern should be same across the fabric - * 4. Create the connectivity of IPINs - * a. Evenly assign connections from routing tracks to IPINs - * b. the connection pattern should be same across the fabric - * 5. Create the switch block patterns, - * It is based on the type of switch block, the supported patterns are - * a. Disjoint, which connects routing track (i)th from (i)th and (i)th routing segments - * b. Universal, which connects routing track (i)th from (i)th and (M-i)th routing segments - * c. Wilton, which rotates the connection of Disjoint by 1 track - * 6. Allocate rr_graph, fill the node information - * For each node, fill - * a. basic information: coordinator(xlow, xhigh, ylow, yhigh), ptc_num - * b. edges (both incoming and outcoming) - * c. handle direct-connections - * 7. Build fast look-up for the rr_graph - * 8. Allocate external data structures - * a. cost_index - * b. RC tree - ***********************************************************************/ -void build_tileable_unidir_rr_graph(INP const int L_num_types, - INP t_type_ptr types, INP const int L_nx, INP const int L_ny, - INP struct s_grid_tile **L_grid, INP const int chan_width, - INP const enum e_switch_block_type sb_type, INP const int Fs, - INP const enum e_switch_block_type sb_subtype, INP const int subFs, - INP const boolean wire_opposite_side, - INP const int num_seg_types, - INP const t_segment_inf * segment_inf, - INP const int num_switches, INP const int delayless_switch, - INP const t_timing_inf timing_inf, - INP const int wire_to_ipin_switch, - INP const enum e_base_cost_type base_cost_type, - INP const t_direct_inf *directs, - INP const int num_directs, INP const boolean ignore_Fc_0, - OUTP int *Warnings) { - /* Create an empty graph */ - t_rr_graph rr_graph; - rr_graph.rr_node_indices = NULL; - rr_graph.rr_node = NULL; - rr_graph.num_rr_nodes = 0; - - /* Reset warning flag */ - *Warnings = RR_GRAPH_NO_WARN; - - /* Print useful information on screen */ - vpr_printf(TIO_MESSAGE_INFO, - "Creating tileable Routing Resource(RR) graph...\n"); - - /* Create a matrix of grid */ - DeviceCoordinator device_size(L_nx + 2, L_ny + 2); - std::vector< std::vector > grids; - /* reserve vector capacity to be memory efficient */ - grids.resize(L_nx + 2); - for (int ix = 0; ix < (L_nx + 2); ++ix) { - grids[ix].resize(L_ny + 2); - for (int iy = 0; iy < (L_ny + 2); ++iy) { - grids[ix][iy] = L_grid[ix][iy]; - } - } - /* Create a vector of channel width, we support X-direction and Y-direction has different W */ - std::vector device_chan_width; - device_chan_width.push_back(chan_width); - device_chan_width.push_back(chan_width); - - /* Create a vector of segment_inf */ - std::vector segment_infs; - for (int iseg = 0; iseg < num_seg_types; ++iseg) { - segment_infs.push_back(segment_inf[iseg]); - } - - /************************************************************************ - * 2. Estimate the number of nodes in the rr_graph - * This will estimate the number of - * a. IPINs, input pins of each grid - * b. OPINs, output pins of each grid - * c. SOURCE, virtual node which drives OPINs - * d. SINK, virtual node which is connected to IPINs - * e. CHANX and CHANY, routing segments of each channel - ***********************************************************************/ - std::vector num_rr_nodes_per_type = estimate_num_rr_nodes_per_type(device_size, grids, device_chan_width, segment_infs); - - /************************************************************************ - * 3. Allocate the rr_nodes - ***********************************************************************/ - rr_graph.num_rr_nodes = 0; - for (size_t i = 0; i < num_rr_nodes_per_type.size(); ++i) { - rr_graph.num_rr_nodes += num_rr_nodes_per_type[i]; - } - /* use calloc and memset to initialize everything to be zero */ - rr_graph.rr_node = (t_rr_node*)my_calloc(rr_graph.num_rr_nodes, sizeof(t_rr_node)); - for (int i = 0; i < rr_graph.num_rr_nodes; ++i) { - tileable_rr_graph_init_rr_node(&(rr_graph.rr_node[i])); - } - - /************************************************************************ - * 4. Initialize the basic information of rr_nodes: - * coordinators: xlow, ylow, xhigh, yhigh, - * features: capacity, track_ids, ptc_num, direction - * grid_info : pb_graph_pin - ***********************************************************************/ - alloc_rr_graph_fast_lookup(device_size, &rr_graph); - - /* FIXME: DEBUG CODES TO BE REMOVED - vpr_printf(TIO_MESSAGE_INFO, "estimated %lu SOURCE NODE.\n", num_rr_nodes_per_type[SOURCE]); - vpr_printf(TIO_MESSAGE_INFO, "estimated %lu SINK NODE.\n", num_rr_nodes_per_type[SINK]); - vpr_printf(TIO_MESSAGE_INFO, "estimated %lu OPIN NODE.\n", num_rr_nodes_per_type[OPIN]); - vpr_printf(TIO_MESSAGE_INFO, "estimated %lu IPIN NODE.\n", num_rr_nodes_per_type[IPIN]); - */ - - load_rr_nodes_basic_info(&rr_graph, device_size, grids, device_chan_width, segment_infs, - wire_to_ipin_switch, delayless_switch); - - /************************************************************************ - * 5.1 Create the connectivity of OPINs - * a. Evenly assign connections to OPINs to routing tracks - * b. the connection pattern should be same across the fabric - * - * 5.2 Create the connectivity of IPINs - * a. Evenly assign connections from routing tracks to IPINs - * b. the connection pattern should be same across the fabric - ***********************************************************************/ - int **Fc_in = NULL; /* [0..num_types-1][0..num_pins-1] */ - boolean Fc_clipped; - Fc_clipped = FALSE; - Fc_in = alloc_and_load_actual_fc(L_num_types, types, chan_width, - FALSE, UNI_DIRECTIONAL, &Fc_clipped, ignore_Fc_0); - if (Fc_clipped) { - *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; - } - - int **Fc_out = NULL; /* [0..num_types-1][0..num_pins-1] */ - Fc_clipped = FALSE; - Fc_out = alloc_and_load_actual_fc(L_num_types, types, chan_width, - TRUE, UNI_DIRECTIONAL, &Fc_clipped, ignore_Fc_0); - - if (Fc_clipped) { - *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; - } - - /************************************************************************ - * 6.1 Build the connections tile by tile: - * We classify rr_nodes into a general switch block (GSB) data structure - * where we create edges to each rr_nodes in the GSB with respect to - * Fc_in and Fc_out, switch block patterns - * In addition, we will also handle direct-connections: - * Add edges that bridge OPINs and IPINs to the rr_graph - ***********************************************************************/ - /* Create edges for a tileable rr_graph */ - build_rr_graph_edges(&rr_graph, device_size, grids, device_chan_width, segment_infs, - Fc_in, Fc_out, - sb_type, Fs, sb_subtype, subFs, (bool)wire_opposite_side); - - /************************************************************************ - * 6.2 Build direction connection lists - ***********************************************************************/ - /* Create data structure of direct-connections */ - t_clb_to_clb_directs* clb_to_clb_directs = NULL; - if (num_directs > 0) { - clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, num_directs); - } - build_rr_graph_direct_connections(&rr_graph, device_size, grids, delayless_switch, - num_directs, directs, clb_to_clb_directs); - - //print_rr_graph_stats(rr_graph); - - /* Clear driver switches of the rr_graph */ - clear_rr_graph_driver_switch(&rr_graph); - - /************************************************************************ - * 7. Allocate external data structures - * a. cost_index - * b. RC tree - ***********************************************************************/ - /* We set global variables for rr_nodes here, they will be updated by rr_graph_external */ - num_rr_nodes = rr_graph.num_rr_nodes; - rr_node = rr_graph.rr_node; - rr_node_indices = rr_graph.rr_node_indices; - - rr_graph_externals(timing_inf, segment_inf, num_seg_types, chan_width, - wire_to_ipin_switch, base_cost_type); - - /************************************************************************ - * 8. Sanitizer for the rr_graph, check connectivities of rr_nodes - ***********************************************************************/ - - /* Print useful information on screen */ - vpr_printf(TIO_MESSAGE_INFO, - "Create a tileable RR graph with %d nodes\n", - num_rr_nodes); - - check_rr_graph(GRAPH_UNIDIR_TILEABLE, L_nx, L_ny, - num_switches, Fc_in); - - /* Print useful information on screen */ - vpr_printf(TIO_MESSAGE_INFO, - "Tileable Routing Resource(RR) graph pass checking.\n"); - - - /************************************************************************ - * 9. Free all temp stucts - ***********************************************************************/ - - /* Free all temp structs */ - if (Fc_in) { - free_matrix(Fc_in,0, L_num_types, 0, sizeof(int)); - Fc_in = NULL; - } - if (Fc_out) { - free_matrix(Fc_out,0, L_num_types, 0, sizeof(int)); - Fc_out = NULL; - } - if(clb_to_clb_directs != NULL) { - free(clb_to_clb_directs); - } - - return; -} - -/************************************************************************ - * End of file : rr_graph_tileable_builder.c - ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h deleted file mode 100644 index 1494aec13..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef TILEABLE_RR_GRAPH_BUILDER_H -#define TILEABLE_RR_GRAPH_BUILDER_H - -#include - -#include "vpr_types.h" - -int adapt_to_tileable_route_chan_width(int chanW, t_segment_inf* segment_inf); - -void build_tileable_unidir_rr_graph(INP const int L_num_types, - INP t_type_ptr types, INP const int L_nx, INP const int L_ny, - INP struct s_grid_tile **L_grid, INP const int chan_width, - INP const enum e_switch_block_type sb_type, INP const int Fs, - INP const enum e_switch_block_type sb_subtype, INP const int subFs, - INP const boolean wire_opposite_side, - INP const int num_seg_types, - INP const t_segment_inf * segment_inf, - INP const int num_switches, INP const int delayless_switch, - INP const t_timing_inf timing_inf, INP const int wire_to_ipin_switch, - INP const enum e_base_cost_type base_cost_type, - INP const t_direct_inf *directs, - INP const int num_directs, INP const boolean ignore_Fc_0, - OUTP int *Warnings); - -#endif diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp deleted file mode 100755 index aa6fcc2aa..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp +++ /dev/null @@ -1,1458 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: tileable_rr_graph_gsb.cpp - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/06/19 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file contains a builder for track-to-track connections inside a - * tileable General Switch Block (GSB). - ***********************************************************************/ - -#include -#include - -#include -#include - -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph2.h" - -#include "rr_graph_builder_utils.h" -#include "tileable_chan_details_builder.h" -#include "tileable_rr_graph_gsb.h" - -#include "fpga_x2p_backannotate_utils.h" - -#include "my_free_fwd.h" - -/************************************************************************ - * Internal data structures - ***********************************************************************/ -typedef std::vector> t_track_group; - -/************************************************************************ - * A enumeration to list the status of a track inside a GSB - * 1. start; 2. end; 3. passing - * This is used to group tracks which ease the building of - * track-to-track mapping matrix - ***********************************************************************/ -enum e_track_status { - TRACK_START, - TRACK_END, - TRACK_PASS, - NUM_TRACK_STATUS /* just a place holder to get the number of status */ -}; - -/************************************************************************ - * Check if a track starts from this GSB or not - * (xlow, ylow) should be same as the GSB side coordinator - * - * Check if a track ends at this GSB or not - * (xhigh, yhigh) should be same as the GSB side coordinator - ***********************************************************************/ -static -enum e_track_status determine_track_status_of_gsb(const RRGSB& rr_gsb, - const enum e_side gsb_side, - const size_t track_id) { - enum e_track_status track_status = TRACK_PASS; - /* Get the rr_node */ - t_rr_node* track_node = rr_gsb.get_chan_node(gsb_side, track_id); - /* Get the coordinators */ - DeviceCoordinator side_coordinator = rr_gsb.get_side_block_coordinator(gsb_side); - - /* Get the coordinator of where the track starts */ - DeviceCoordinator track_start = get_track_rr_node_start_coordinator(track_node); - - /* INC_DIRECTION start_track: (xlow, ylow) should be same as the GSB side coordinator */ - /* DEC_DIRECTION start_track: (xhigh, yhigh) should be same as the GSB side coordinator */ - if ( (track_start.get_x() == side_coordinator.get_x()) - && (track_start.get_y() == side_coordinator.get_y()) - && (OUT_PORT == rr_gsb.get_chan_node_direction(gsb_side, track_id)) ) { - /* Double check: start track should be an OUTPUT PORT of the GSB */ - track_status = TRACK_START; - } - - /* Get the coordinator of where the track ends */ - DeviceCoordinator track_end = get_track_rr_node_end_coordinator(track_node); - - /* INC_DIRECTION end_track: (xhigh, yhigh) should be same as the GSB side coordinator */ - /* DEC_DIRECTION end_track: (xlow, ylow) should be same as the GSB side coordinator */ - if ( (track_end.get_x() == side_coordinator.get_x()) - && (track_end.get_y() == side_coordinator.get_y()) - && (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, track_id)) ) { - /* Double check: end track should be an INPUT PORT of the GSB */ - track_status = TRACK_END; - } - - return track_status; -} - - -/************************************************************************ - * Check if the GSB is in the Connection Block (CB) population list of the segment - * SB population of a L4 wire: 1 0 0 1 - * - * +----+ +----+ +----+ +----+ - * | CB |--->| CB |--->| CB |--->| CB | - * +----+ +----+ +----+ +----+ - * Engage CB connection Yes No No Yes - * - * We will find the offset between gsb_side_coordinator and (xlow,ylow) of the track - * Use the offset to check if the tracks should engage in this GSB connection - ***********************************************************************/ -static -bool is_gsb_in_track_cb_population(const RRGSB& rr_gsb, - const enum e_side gsb_side, - const int track_id, - const std::vector segment_inf) { - /* Get the rr_node */ - t_rr_node* track_node = rr_gsb.get_chan_node(gsb_side, track_id); - /* Get the coordinators */ - DeviceCoordinator side_coordinator = rr_gsb.get_side_block_coordinator(gsb_side); - - DeviceCoordinator track_start = get_track_rr_node_start_coordinator(track_node); - - /* Get the offset */ - size_t offset = std::abs((int)side_coordinator.get_x() - (int)track_start.get_x()) - + std::abs((int)side_coordinator.get_y() - (int)track_start.get_y()); - - /* Get segment id */ - size_t seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id); - /* validate offset */ - assert (offset < (size_t)segment_inf[seg_id].cb_len); - - /* Get the SB population */ - bool in_cb_population = false; - if (TRUE == segment_inf[seg_id].cb[offset]) { - in_cb_population = true; - } - return in_cb_population; -} - -/************************************************************************ - * Check if the GSB is in the Switch Block (SB) population list of the segment - * SB population of a L3 wire: 1 0 0 1 - * - * +----+ +----+ +----+ +----+ - * | SB |--->| SB |--->| SB |--->| SB | - * +----+ +----+ +----+ +----+ - * Engage SB connection Yes No No Yes - * - * We will find the offset between gsb_side_coordinator and (xlow,ylow) of the track - * Use the offset to check if the tracks should engage in this GSB connection - ***********************************************************************/ -static -bool is_gsb_in_track_sb_population(const RRGSB& rr_gsb, - const enum e_side gsb_side, - const int track_id, - const std::vector segment_inf) { - /* Get the rr_node */ - t_rr_node* track_node = rr_gsb.get_chan_node(gsb_side, track_id); - /* Get the coordinators */ - DeviceCoordinator side_coordinator = rr_gsb.get_side_block_coordinator(gsb_side); - - DeviceCoordinator track_start = get_track_rr_node_start_coordinator(track_node); - - /* Get the offset */ - size_t offset = std::abs((int)side_coordinator.get_x() - (int)track_start.get_x()) - + std::abs((int)side_coordinator.get_y() - (int)track_start.get_y()); - - /* Get segment id */ - size_t seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id); - /* validate offset */ - assert (offset < (size_t)segment_inf[seg_id].sb_len); - - /* Get the SB population */ - bool in_sb_population = false; - if (TRUE == segment_inf[seg_id].sb[offset]) { - in_sb_population = true; - } - return in_sb_population; -} - -/************************************************************************ - * Create a list of track_id based on the to_track and num_to_tracks - * We consider the following list [to_track, to_track + Fs/3 - 1] - * if the [to_track + Fs/3 - 1] exceeds the num_to_tracks, we start over from 0! -***********************************************************************/ -static -std::vector get_to_track_list(const int Fs, const int to_track, const int num_to_tracks) { - std::vector to_tracks; - /* Ensure a clear start */ - to_tracks.clear(); - - for (int i = 0; i < Fs; i = i + 3) { - /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied - * The optimal track selection should be done in a more scientific way!!! - */ - int to_track_i = to_track + i; - /* make sure the track id is still in range */ - if ( to_track_i > num_to_tracks - 1) { - to_track_i = to_track_i % num_to_tracks; - } - /* Ensure we are in the range */ - assert (to_track_i < num_to_tracks); - /* from track must be connected */ - to_tracks.push_back(to_track_i); - } - return to_tracks; -} - -/************************************************************************ - * This function aims to return the track indices that drive the from_track - * in a Switch Block - * The track_ids to return will depend on different topologies of SB - * SUBSET, UNIVERSAL, and WILTON. - ***********************************************************************/ -static -std::vector get_switch_block_to_track_id(const enum e_switch_block_type switch_block_type, - const int Fs, - const enum e_side from_side, - const int from_track, - const enum e_side to_side, - const int num_to_tracks) { - - /* This routine returns the track number to which the from_track should - * connect. It supports any Fs % 3 == 0, switch blocks. - */ - std::vector to_tracks; - /* Ensure a clear start */ - to_tracks.clear(); - - /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied - * The optimal track selection should be done in a more scientific way!!! - */ - - assert (0 == Fs % 3); - - /* Adapt from_track to fit in the range of num_to_tracks */ - size_t actual_from_track = from_track % num_to_tracks; - - switch (switch_block_type) { - case SUBSET: /* NB: Global routing uses SUBSET too */ - to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); - /* Finish, we return */ - return to_tracks; - case UNIVERSAL: - if ( (from_side == LEFT) - || (from_side == RIGHT) ) { - /* For the prev_side, to_track is from_track - * For the next_side, to_track is num_to_tracks - 1 - from_track - * For the opposite_side, to_track is always from_track - */ - Side side_manager(from_side); - if ( (to_side == side_manager.get_opposite()) - || (to_side == side_manager.get_rotate_counterclockwise()) ) { - to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); - } else if (to_side == side_manager.get_rotate_clockwise()) { - to_tracks = get_to_track_list(Fs, num_to_tracks - 1 - actual_from_track, num_to_tracks); - } - } - - if ( (from_side == TOP) - || (from_side == BOTTOM) ) { - /* For the next_side, to_track is from_track - * For the prev_side, to_track is num_to_tracks - 1 - from_track - * For the opposite_side, to_track is always from_track - */ - Side side_manager(from_side); - if ( (to_side == side_manager.get_opposite()) - || (to_side == side_manager.get_rotate_clockwise()) ) { - to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); - } else if (to_side == side_manager.get_rotate_counterclockwise()) { - to_tracks = get_to_track_list(Fs, num_to_tracks - 1 - actual_from_track, num_to_tracks); - } - } - /* Finish, we return */ - return to_tracks; - /* End switch_block_type == UNIVERSAL case. */ - case WILTON: - /* See S. Wilton Phd thesis, U of T, 1996 p. 103 for details on following. */ - if (from_side == LEFT) { - if (to_side == RIGHT) { /* CHANX to CHANX */ - to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); - } else if (to_side == TOP) { /* from CHANX to CHANY */ - to_tracks = get_to_track_list(Fs, (num_to_tracks - actual_from_track ) % num_to_tracks, num_to_tracks); - } else if (to_side == BOTTOM) { - to_tracks = get_to_track_list(Fs, (num_to_tracks + actual_from_track - 1) % num_to_tracks, num_to_tracks); - } - } else if (from_side == RIGHT) { - if (to_side == LEFT) { /* CHANX to CHANX */ - to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); - } else if (to_side == TOP) { /* from CHANX to CHANY */ - to_tracks = get_to_track_list(Fs, (num_to_tracks + actual_from_track - 1) % num_to_tracks, num_to_tracks); - } else if (to_side == BOTTOM) { - to_tracks = get_to_track_list(Fs, (2 * num_to_tracks - 2 - actual_from_track) % num_to_tracks, num_to_tracks); - } - } else if (from_side == BOTTOM) { - if (to_side == TOP) { /* CHANY to CHANY */ - to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); - } else if (to_side == LEFT) { /* from CHANY to CHANX */ - to_tracks = get_to_track_list(Fs, (actual_from_track + 1) % num_to_tracks, num_to_tracks); - } else if (to_side == RIGHT) { - to_tracks = get_to_track_list(Fs, (2 * num_to_tracks - 2 - actual_from_track) % num_to_tracks, num_to_tracks); - } - } else if (from_side == TOP) { - if (to_side == BOTTOM) { /* CHANY to CHANY */ - to_tracks = get_to_track_list(Fs, from_track, num_to_tracks); - } else if (to_side == LEFT) { /* from CHANY to CHANX */ - to_tracks = get_to_track_list(Fs, (num_to_tracks - actual_from_track) % num_to_tracks, num_to_tracks); - } else if (to_side == RIGHT) { - to_tracks = get_to_track_list(Fs, (actual_from_track + 1) % num_to_tracks, num_to_tracks); - } - } - /* Finish, we return */ - return to_tracks; - /* End switch_block_type == WILTON case. */ - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid switch block pattern !\n", - __FILE__, __LINE__); - exit(1); - } - - return to_tracks; -} - - -/************************************************************************ - * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] - * For a group of from_track nodes and to_track nodes - * For each side of from_tracks, we call a routine to get the list of to_tracks - * Then, we fill the track2track_map - ***********************************************************************/ -static -void build_gsb_one_group_track_to_track_map(const t_rr_graph* rr_graph, - const RRGSB& rr_gsb, - const enum e_switch_block_type sb_type, - const int Fs, - const bool wire_opposite_side, - const t_track_group from_tracks, /* [0..gsb_side][track_indices] */ - const t_track_group to_tracks, /* [0..gsb_side][track_indices] */ - t_track2track_map* track2track_map) { - for (size_t side = 0; side < from_tracks.size(); ++side) { - Side side_manager(side); - enum e_side from_side = side_manager.get_side(); - /* Find the other sides where the start tracks will locate */ - std::vector to_track_sides; - /* 0. opposite side */ - to_track_sides.push_back(side_manager.get_opposite()); - /* 1. prev side */ - /* Previous side definition: TOP => LEFT; RIGHT=>TOP; BOTTOM=>RIGHT; LEFT=>BOTTOM */ - to_track_sides.push_back(side_manager.get_rotate_counterclockwise()); - /* 2. next side */ - /* Next side definition: TOP => RIGHT; RIGHT=>BOTTOM; BOTTOM=>LEFT; LEFT=>TOP */ - to_track_sides.push_back(side_manager.get_rotate_clockwise()); - - for (size_t inode = 0; inode < from_tracks[side].size(); ++inode) { - for (size_t to_side_id = 0; to_side_id < to_track_sides.size(); ++to_side_id) { - enum e_side to_side = to_track_sides[to_side_id]; - Side to_side_manager(to_side); - size_t to_side_index = to_side_manager.to_size_t(); - /* Bypass those to_sides have no nodes */ - if (0 == to_tracks[to_side_index].size()) { - continue; - } - /* Bypass those from_side is same as to_side */ - if (from_side == to_side) { - continue; - } - /* Bypass those from_side is opposite to to_side if required */ - if ( (true == wire_opposite_side) - && (to_side_manager.get_opposite() == from_side) ) { - continue; - } - /* Get other track_ids depending on the switch block pattern */ - /* Find the track ids that will start at the other sides */ - std::vector to_track_ids = get_switch_block_to_track_id(sb_type, Fs, from_side, inode, - to_side, - to_tracks[to_side_index].size()); - /* Update the track2track_map: */ - for (size_t to_track_id = 0; to_track_id < to_track_ids.size(); ++to_track_id) { - size_t from_side_index = side_manager.to_size_t(); - size_t from_track_index = from_tracks[side][inode]; - /* Check the id is still in the range !*/ - assert ( to_track_ids[to_track_id] < to_tracks[to_side_index].size() ); - size_t to_track_index = to_tracks[to_side_index][to_track_ids[to_track_id]]; - //printf("from_track(size=%lu): %lu , to_track_ids[%lu]:%lu, to_track_index: %lu in a group of %lu tracks\n", - // from_tracks[side].size(), inode, to_track_id, to_track_ids[to_track_id], - // to_track_index, to_tracks[to_side_index].size()); - t_rr_node* to_track_node = rr_gsb.get_chan_node(to_side, to_track_index); - - /* from_track should be IN_PORT */ - assert( IN_PORT == rr_gsb.get_chan_node_direction(from_side, from_track_index) ); - /* to_track should be OUT_PORT */ - assert( OUT_PORT == rr_gsb.get_chan_node_direction(to_side, to_track_index) ); - - /* Check if the to_track_node is already in the list ! */ - std::vector::iterator it = std::find((*track2track_map)[from_side_index][from_track_index].begin(), - (*track2track_map)[from_side_index][from_track_index].end(), - to_track_node - rr_graph->rr_node); - if (it != (*track2track_map)[from_side_index][from_track_index].end()) { - continue; /* the node_id is already in the list, go for the next */ - } - /* Clear, we should add to the list */ - (*track2track_map)[from_side_index][from_track_index].push_back(to_track_node - rr_graph->rr_node); - } - } - } - } - - return; -} - -/************************************************************************ - * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] - * based on the existing routing resources in the General Switch Block (GSB) - * The track_indices is the indices of tracks that the node at from_side and [0..chan_width-1] will drive - * IMPORTANT: the track_indices are the indicies in the GSB context, but not the rr_graph!!! - * We separate the connections into two groups: - * Group 1: the routing tracks start from this GSB - * We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) - * Group 2: the routing tracks do not start from this GSB (bypassing wires) - * We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) - * but we will check the Switch Block (SB) population of these - * routing segments, and determine which requires connections - * - * CHANY CHANY CHANY CHANY - * [0] [1] [2] [3] - * start yes no yes no - * end +-------------------------+ start Group 1 Group 2 - * no CHANX[0] | TOP | CHANX[0] yes TOP/BOTTOM TOP/BOTTOM - * | | CHANY[0,2] CHANY[1,3] - * yes CHANX[1] | | CHANX[1] no - * | LEFT RIGHT | - * no CHANX[2] | | CHANX[2] yes - * | | - * yes CHANX[3] | BOTTOM | CHANX[3] no - * +-------------------------+ - * CHANY CHANY CHANY CHANY - * [0] [1] [2] [3] - * start yes no yes no - * - * The mapping is done in the following steps: (For each side of the GSB) - * 1. Build a list of tracks that will start from this side - * if a track starts, its xlow/ylow is the same as the x,y of this gsb - * 2. Build a list of tracks on the other sides belonging to Group 1. - * Take the example of RIGHT side, we will collect - * a. tracks that will end at the LEFT side - * b. tracks that will start at the TOP side - * c. tracks that will start at the BOTTOM side - * 3. Apply switch block patterns to Group 1 (SUBSET, UNIVERSAL, WILTON) - * 4. Build a list of tracks on the other sides belonging to Group 1. - * Take the example of RIGHT side, we will collect - * a. tracks that will bypass at the TOP side - * b. tracks that will bypass at the BOTTOM side - * 5. Apply switch block patterns to Group 2 (SUBSET, UNIVERSAL, WILTON) - ***********************************************************************/ -t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph, - const RRGSB& rr_gsb, - const enum e_switch_block_type sb_type, - const int Fs, - const enum e_switch_block_type sb_subtype, - const int subFs, - const bool wire_opposite_side, - const std::vector segment_inf) { - t_track2track_map track2track_map; /* [0..gsb_side][0..chan_width][track_indices] */ - - /* Categorize tracks into 3 groups: - * (1) tracks will start here - * (2) tracks will end here - * (2) tracks will just pass through the SB */ - t_track_group start_tracks; /* [0..gsb_side][track_indices] */ - t_track_group end_tracks; /* [0..gsb_side][track_indices] */ - t_track_group pass_tracks; /* [0..gsb_side][track_indices] */ - - /* resize to the number of sides */ - start_tracks.resize(rr_gsb.get_num_sides()); - end_tracks.resize(rr_gsb.get_num_sides()); - pass_tracks.resize(rr_gsb.get_num_sides()); - - /* Walk through each side */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - enum e_side gsb_side = side_manager.get_side(); - /* Build a list of tracks that will start from this side */ - for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { - /* We need to check Switch block population of this track - * The track node will not be considered if there supposed to be no SB at this position - */ - if (false == is_gsb_in_track_sb_population(rr_gsb, gsb_side, inode, segment_inf)) { - continue; /* skip this node and go to the next */ - } - /* check if this track will start from here */ - enum e_track_status track_status = determine_track_status_of_gsb(rr_gsb, gsb_side, inode); - - switch (track_status) { - case TRACK_START: - /* update starting track list */ - start_tracks[side].push_back(inode); - break; - case TRACK_END: - /* Update end track list */ - end_tracks[side].push_back(inode); - break; - case TRACK_PASS: - /* Update passing track list */ - /* Note that the pass_track should be IN_PORT only !!! */ - if (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, inode)) { - pass_tracks[side].push_back(inode); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid track status!\n", - __FILE__, __LINE__); - exit(1); - } - } - } - - /* Allocate track2track map */ - track2track_map.resize(rr_gsb.get_num_sides()); - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - enum e_side gsb_side = side_manager.get_side(); - /* allocate track2track_map[gsb_side] */ - track2track_map[side].resize(rr_gsb.get_chan_width(gsb_side)); - for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { - /* allocate track2track_map[gsb_side][inode] */ - track2track_map[side][inode].clear(); - } - } - - /* For Group 1: we build connections between end_tracks and start_tracks*/ - build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, - sb_type, Fs, - true, /* End tracks should always to wired to start tracks */ - end_tracks, start_tracks, - &track2track_map); - - /* For Group 2: we build connections between end_tracks and start_tracks*/ - /* Currently, I use the same Switch Block pattern for the passing tracks and end tracks, - * TODO: This can be improved with different patterns! - */ - build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, - sb_subtype, subFs, - wire_opposite_side, /* Pass tracks may not be wired to start tracks */ - pass_tracks, start_tracks, - &track2track_map); - - return track2track_map; -} - -/* Build a RRChan Object with the given channel type and coorindators */ -static -RRChan build_one_tileable_rr_chan(const DeviceCoordinator& chan_coordinator, - const t_rr_type chan_type, - const t_rr_graph* rr_graph, - const ChanNodeDetails& chan_details) { - int chan_width = 0; - t_rr_node** chan_rr_nodes = NULL; - - /* Create a rr_chan object and check if it is unique in the graph */ - RRChan rr_chan; - /* Fill the information */ - rr_chan.set_type(chan_type); - - /* Collect rr_nodes for this channel */ - chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, - chan_coordinator.get_x(), chan_coordinator.get_y(), - rr_graph->num_rr_nodes, rr_graph->rr_node, - rr_graph->rr_node_indices); - - /* Reserve */ - /* rr_chan.reserve_node(size_t(chan_width)); */ - - /* Fill the rr_chan */ - for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { - size_t iseg = chan_details.get_track_segment_id(itrack); - rr_chan.add_node(chan_rr_nodes[itrack], iseg); - } - - /* Free rr_nodes */ - my_free(chan_rr_nodes); - - return rr_chan; -} - -/*********************************************************************** - * Build a General Switch Block (GSB) - * which includes: - * [I] A Switch Box subckt consists of following ports: - * 1. Channel Y [x][y] inputs - * 2. Channel X [x+1][y] inputs - * 3. Channel Y [x][y-1] outputs - * 4. Channel X [x][y] outputs - * 5. Grid[x][y+1] Right side outputs pins - * 6. Grid[x+1][y+1] Left side output pins - * 7. Grid[x+1][y+1] Bottom side output pins - * 8. Grid[x+1][y] Top side output pins - * 9. Grid[x+1][y] Left side output pins - * 10. Grid[x][y] Right side output pins - * 11. Grid[x][y] Top side output pins - * 12. Grid[x][y+1] Bottom side output pins - * - * -------------- -------------- - * | | CBY | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX & CBX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - * For channels chanY with INC_DIRECTION on the top side, they should be marked as outputs - * For channels chanY with DEC_DIRECTION on the top side, they should be marked as inputs - * For channels chanY with INC_DIRECTION on the bottom side, they should be marked as inputs - * For channels chanY with DEC_DIRECTION on the bottom side, they should be marked as outputs - * For channels chanX with INC_DIRECTION on the left side, they should be marked as inputs - * For channels chanX with DEC_DIRECTION on the left side, they should be marked as outputs - * For channels chanX with INC_DIRECTION on the right side, they should be marked as outputs - * For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs - * - * [II] A X-direction Connection Block [x][y] - * The connection block shares the same routing channel[x][y] with the Switch Block - * We just need to fill the ipin nodes at TOP and BOTTOM sides - * as well as properly fill the ipin_grid_side information - * [III] A Y-direction Connection Block [x][y+1] - * The connection block shares the same routing channel[x][y+1] with the Switch Block - * We just need to fill the ipin nodes at LEFT and RIGHT sides - * as well as properly fill the ipin_grid_side information - ***********************************************************************/ -RRGSB build_one_tileable_rr_gsb(const DeviceCoordinator& device_range, - const std::vector device_chan_width, - const std::vector segment_inf, - const DeviceCoordinator& gsb_coordinator, - t_rr_graph* rr_graph) { - /* Create an object to return */ - RRGSB rr_gsb; - - /* Check */ - assert(gsb_coordinator.get_x() <= device_range.get_x()); - assert(gsb_coordinator.get_y() <= device_range.get_y()); - - /* Coordinator initialization */ - rr_gsb.set_coordinator(gsb_coordinator.get_x(), gsb_coordinator.get_y()); - - /* Basic information*/ - rr_gsb.init_num_sides(4); /* Fixed number of sides */ - - /* Find all rr_nodes of channels */ - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - /* Local variables inside this for loop */ - Side side_manager(side); - DeviceCoordinator coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side()); - RRChan rr_chan; - int temp_num_opin_rr_nodes[2] = {0,0}; - t_rr_node** temp_opin_rr_node[2] = {NULL, NULL}; - enum e_side opin_grid_side[2] = {NUM_SIDES, NUM_SIDES}; - enum PORTS chan_dir_to_port_dir_mapping[2] = {OUT_PORT, IN_PORT}; /* 0: INC_DIRECTION => ?; 1: DEC_DIRECTION => ? */ - /* Build a segment details, where we need the segment ids for building rr_chan - * We do not care starting and ending points here, so set chan_side as NUM_SIDES - */ - ChanNodeDetails chanx_details = build_unidir_chan_node_details(device_chan_width[0], device_range.get_x() - 1, - NUM_SIDES, segment_inf); - ChanNodeDetails chany_details = build_unidir_chan_node_details(device_chan_width[1], device_range.get_y() - 1, - NUM_SIDES, segment_inf); - - switch (side) { - case TOP: /* TOP = 0 */ - /* For the bording, we should take special care */ - if (gsb_coordinator.get_y() == device_range.get_y()) { - rr_gsb.clear_one_side(side_manager.get_side()); - break; - } - /* Routing channels*/ - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(coordinator, CHANY, rr_graph, chany_details); - chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ - chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ - - /* Build the Switch block: opin and opin_grid_side */ - /* Include Grid[x][y+1] RIGHT side outputs pins */ - temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], - OPIN, gsb_coordinator.get_x(), gsb_coordinator.get_y() + 1, 1, - rr_graph->num_rr_nodes, rr_graph->rr_node, rr_graph->rr_node_indices); - /* Include Grid[x+1][y+1] Left side output pins */ - temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], - OPIN, gsb_coordinator.get_x() + 1, gsb_coordinator.get_y() + 1, 3, - rr_graph->num_rr_nodes, rr_graph->rr_node, rr_graph->rr_node_indices); - - /* Assign grid side of OPIN */ - /* Grid[x][y+1] RIGHT side outputs pins */ - opin_grid_side[0] = RIGHT; - /* Grid[x+1][y+1] left side outputs pins */ - opin_grid_side[1] = LEFT; - break; - case RIGHT: /* RIGHT = 1 */ - /* For the bording, we should take special care */ - if (gsb_coordinator.get_x() == device_range.get_x()) { - rr_gsb.clear_one_side(side_manager.get_side()); - break; - } - /* Routing channels*/ - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Collect rr_nodes for Tracks for top: chany[x][y+1] */ - /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(coordinator, CHANX, rr_graph, chanx_details); - chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ - chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ - - /* Build the Switch block: opin and opin_grid_side */ - /* include Grid[x+1][y+1] Bottom side output pins */ - temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], - OPIN, gsb_coordinator.get_x() + 1, gsb_coordinator.get_y() + 1, 2, - rr_graph->num_rr_nodes, rr_graph->rr_node, rr_graph->rr_node_indices); - /* include Grid[x+1][y] Top side output pins */ - temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], - OPIN, gsb_coordinator.get_x() + 1, gsb_coordinator.get_y(), 0, - rr_graph->num_rr_nodes, rr_graph->rr_node, rr_graph->rr_node_indices); - /* Assign grid side of OPIN */ - /* Grid[x+1][y+1] BOTTOM side outputs pins */ - opin_grid_side[0] = BOTTOM; - /* Grid[x+1][y] TOP side outputs pins */ - opin_grid_side[1] = TOP; - break; - case BOTTOM: /* BOTTOM = 2*/ - /* For the bording, we should take special care */ - if (gsb_coordinator.get_y() == 0) { - rr_gsb.clear_one_side(side_manager.get_side()); - break; - } - /* Routing channels*/ - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Collect rr_nodes for Tracks for bottom: chany[x][y] */ - /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(coordinator, CHANY, rr_graph, chany_details); - chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ - chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ - - /* Build the Switch block: opin and opin_grid_side */ - /* include Grid[x+1][y] Left side output pins */ - temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], - OPIN, gsb_coordinator.get_x() + 1, gsb_coordinator.get_y(), 3, - rr_graph->num_rr_nodes, rr_graph->rr_node, rr_graph->rr_node_indices); - /* include Grid[x][y] Right side output pins */ - temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], - OPIN, gsb_coordinator.get_x(), gsb_coordinator.get_y(), 1, - rr_graph->num_rr_nodes, rr_graph->rr_node, rr_graph->rr_node_indices); - /* Assign grid side of OPIN */ - /* Grid[x+1][y] LEFT side outputs pins */ - opin_grid_side[0] = LEFT; - /* Grid[x][y] RIGHT side outputs pins */ - opin_grid_side[1] = RIGHT; - break; - case LEFT: /* LEFT = 3 */ - /* For the bording, we should take special care */ - if (gsb_coordinator.get_x() == 0) { - rr_gsb.clear_one_side(side_manager.get_side()); - break; - } - /* Routing channels*/ - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Collect rr_nodes for Tracks for left: chanx[x][y] */ - /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_tileable_rr_chan(coordinator, CHANX, rr_graph, chanx_details); - chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ - chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ - - /* Build the Switch block: opin and opin_grid_side */ - /* include Grid[x][y+1] Bottom side outputs pins */ - temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], - OPIN, gsb_coordinator.get_x(), gsb_coordinator.get_y() + 1, 2, - rr_graph->num_rr_nodes, rr_graph->rr_node, rr_graph->rr_node_indices); - /* include Grid[x][y] Top side output pins */ - temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], - OPIN, gsb_coordinator.get_x(), gsb_coordinator.get_y(), 0, - rr_graph->num_rr_nodes, rr_graph->rr_node, rr_graph->rr_node_indices); - - /* Grid[x][y+1] BOTTOM side outputs pins */ - opin_grid_side[0] = BOTTOM; - /* Grid[x][y] TOP side outputs pins */ - opin_grid_side[1] = TOP; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid side index!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Organize a vector of port direction */ - if (0 < rr_chan.get_chan_width()) { - std::vector rr_chan_dir; - rr_chan_dir.resize(rr_chan.get_chan_width()); - for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { - /* Identify the directionality, record it in rr_node_direction */ - if (INC_DIRECTION == rr_chan.get_node(itrack)->direction) { - rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[0]; - } else { - assert (DEC_DIRECTION == rr_chan.get_node(itrack)->direction); - rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[1]; - } - } - /* Fill chan_rr_nodes */ - rr_gsb.add_chan_node(side_manager.get_side(), rr_chan, rr_chan_dir); - } - - /* Fill opin_rr_nodes */ - /* Copy from temp_opin_rr_node to opin_rr_node */ - for (int inode = 0; inode < temp_num_opin_rr_nodes[0]; ++inode) { - /* Grid[x+1][y+1] Bottom side outputs pins */ - rr_gsb.add_opin_node(temp_opin_rr_node[0][inode], side_manager.get_side(), opin_grid_side[0]); - } - for (int inode = 0; inode < temp_num_opin_rr_nodes[1]; ++inode) { - /* Grid[x+1][y] TOP side outputs pins */ - rr_gsb.add_opin_node(temp_opin_rr_node[1][inode], side_manager.get_side(), opin_grid_side[1]); - } - - /* Clean ipin_rr_nodes */ - /* We do not have any IPIN for a Switch Block */ - rr_gsb.clear_ipin_nodes(side_manager.get_side()); - - /* Free */ - temp_num_opin_rr_nodes[0] = 0; - my_free(temp_opin_rr_node[0]); - temp_num_opin_rr_nodes[1] = 0; - my_free(temp_opin_rr_node[1]); - /* Set them to NULL, avoid double free errors */ - temp_opin_rr_node[0] = NULL; - temp_opin_rr_node[1] = NULL; - opin_grid_side[0] = NUM_SIDES; - opin_grid_side[1] = NUM_SIDES; - } - - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - /* Local variables inside this for loop */ - Side side_manager(side); - size_t ix; - size_t iy; - enum e_side chan_side; - int num_temp_ipin_rr_nodes = 0; - t_rr_node** temp_ipin_rr_node = NULL; - enum e_side ipin_rr_node_grid_side; - - switch (side) { - case TOP: /* TOP = 0 */ - /* For the bording, we should take special care */ - /* Check if left side chan width is 0 or not */ - chan_side = LEFT; - /* Build the connection block: ipin and ipin_grid_side */ - /* BOTTOM side INPUT Pins of Grid[x][y+1] */ - ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y() + 1; - ipin_rr_node_grid_side = BOTTOM; - break; - case RIGHT: /* RIGHT = 1 */ - /* For the bording, we should take special care */ - /* Check if TOP side chan width is 0 or not */ - chan_side = TOP; - /* Build the connection block: ipin and ipin_grid_side */ - /* LEFT side INPUT Pins of Grid[x+1][y+1] */ - ix = rr_gsb.get_sb_x() + 1; - iy = rr_gsb.get_sb_y() + 1; - ipin_rr_node_grid_side = LEFT; - break; - case BOTTOM: /* BOTTOM = 2*/ - /* For the bording, we should take special care */ - /* Check if left side chan width is 0 or not */ - chan_side = LEFT; - /* Build the connection block: ipin and ipin_grid_side */ - /* TOP side INPUT Pins of Grid[x][y] */ - ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y(); - ipin_rr_node_grid_side = TOP; - break; - case LEFT: /* LEFT = 3 */ - /* For the bording, we should take special care */ - /* Check if left side chan width is 0 or not */ - chan_side = TOP; - /* Build the connection block: ipin and ipin_grid_side */ - /* RIGHT side INPUT Pins of Grid[x][y+1] */ - ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y() + 1; - ipin_rr_node_grid_side = RIGHT; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid side index!\n", - __FILE__, __LINE__); - exit(1); - } - - /* If there is no channel at this side, we skip ipin_node annotation */ - if (0 == rr_gsb.get_chan_width(chan_side)) { - continue; - } - /* Collect IPIN rr_nodes*/ - temp_ipin_rr_node = get_grid_side_pin_rr_nodes(&(num_temp_ipin_rr_nodes), - IPIN, ix, iy, ipin_rr_node_grid_side, - rr_graph->num_rr_nodes, rr_graph->rr_node, rr_graph->rr_node_indices); - /* Fill the ipin nodes of RRGSB */ - for (int inode = 0; inode < num_temp_ipin_rr_nodes; ++inode) { - rr_gsb.add_ipin_node(temp_ipin_rr_node[inode], side_manager.get_side(), ipin_rr_node_grid_side); - } - /* Free */ - num_temp_ipin_rr_nodes = 0; - my_free(temp_ipin_rr_node); - } - - return rr_gsb; -} - -/************************************************************************ - * Create edges for each rr_node of a General Switch Blocks (GSB): - * 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks) - * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) - * 3. create edges between OPINs and IPINs (direct-connections) - ***********************************************************************/ -void build_edges_for_one_tileable_rr_gsb(const t_rr_graph* rr_graph, - const RRGSB* rr_gsb, - const t_track2pin_map track2ipin_map, - const t_pin2track_map opin2track_map, - const t_track2track_map track2track_map) { - /* Check rr_gsb */ - assert (NULL != rr_gsb); - - /* Walk through each sides */ - for (size_t side = 0; side < rr_gsb->get_num_sides(); ++side) { - Side side_manager(side); - enum e_side gsb_side = side_manager.get_side(); - - /* Find OPINs */ - for (size_t inode = 0; inode < rr_gsb->get_num_opin_nodes(gsb_side); ++inode) { - t_rr_node* opin_node = rr_gsb->get_opin_node(gsb_side, inode); - - /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ - std::vector driver_switches; - int num_edges = opin2track_map[gsb_side][inode].size(); - for (int iedge = 0; iedge < num_edges; ++iedge) { - int track_node_id = opin2track_map[side_manager.to_size_t()][inode][iedge]; - driver_switches.push_back(rr_graph->rr_node[track_node_id].driver_switch); - } - /* add edges to the opin_node */ - add_edges_for_two_rr_nodes(rr_graph, opin_node - rr_graph->rr_node, - opin2track_map[gsb_side][inode], driver_switches); - } - - /* Find CHANX or CHANY */ - /* For TRACKs to IPINs, we only care LEFT and TOP sides - * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs - */ - if ( (side_manager.get_side() == rr_gsb->get_cb_chan_side(CHANX)) - || (side_manager.get_side() == rr_gsb->get_cb_chan_side(CHANY)) ) { - /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */ - for (size_t inode = 0; inode < rr_gsb->get_chan_width(gsb_side); ++inode) { - t_rr_node* chan_node = rr_gsb->get_chan_node(gsb_side, inode); - std::vector driver_switches; - int num_edges = track2ipin_map[gsb_side][inode].size(); - for (int iedge = 0; iedge < num_edges; ++iedge) { - int ipin_node_id = track2ipin_map[gsb_side][inode][iedge]; - driver_switches.push_back(rr_graph->rr_node[ipin_node_id].driver_switch); - } - /* add edges to the chan_node */ - add_edges_for_two_rr_nodes(rr_graph, chan_node - rr_graph->rr_node, - track2ipin_map[gsb_side][inode], driver_switches); - } - } - - /* 3. create edges between CHANX|CHANY and CHANX|CHANY, using track2track_map */ - for (size_t inode = 0; inode < rr_gsb->get_chan_width(gsb_side); ++inode) { - t_rr_node* chan_node = rr_gsb->get_chan_node(gsb_side, inode); - std::vector driver_switches; - int num_edges = track2track_map[gsb_side][inode].size(); - for (int iedge = 0; iedge < num_edges; ++iedge) { - int track_node_id = track2track_map[gsb_side][inode][iedge]; - driver_switches.push_back(rr_graph->rr_node[track_node_id].driver_switch); - } - /* add edges to the chan_node */ - add_edges_for_two_rr_nodes(rr_graph, chan_node - rr_graph->rr_node, - track2track_map[gsb_side][inode], driver_switches); - } - } - - return; -} - -/************************************************************************ - * Build track2ipin_map for an IPIN - * 1. build a list of routing tracks which are allowed for connections - * We will check the Connection Block (CB) population of each routing track. - * By comparing current chan_y - ylow, we can determine if a CB connection - * is required for each routing track - * 2. Divide the routing tracks by segment types, so that we can balance - * the connections between IPINs and different types of routing tracks. - * 3. Scale the Fc of each pin to the actual number of routing tracks - * actual_Fc = (int) Fc * num_tracks / chan_width - ***********************************************************************/ -static -void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, - const RRGSB& rr_gsb, - const enum e_side ipin_side, - const size_t ipin_node_id, - const size_t Fc, - const size_t offset, - const std::vector segment_inf, - t_track2pin_map* track2ipin_map) { - /* Get a list of segment_ids*/ - enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); - Side chan_side_manager(chan_side); - std::vector seg_list = rr_gsb.get_chan_segment_ids(chan_side); - size_t chan_width = rr_gsb.get_chan_width(chan_side); - Side ipin_side_manager(ipin_side); - t_rr_node* ipin_node = rr_gsb.get_ipin_node(ipin_side, ipin_node_id); - - for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { - /* Get a list of node that have the segment id */ - std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]); - /* Refine the track_list: keep those will have connection blocks in the GSB */ - std::vector actual_track_list; - for (size_t inode = 0; inode < track_list.size(); ++inode) { - /* Check if tracks allow connection blocks in the GSB*/ - if (false == is_gsb_in_track_cb_population(rr_gsb, chan_side, track_list[inode], segment_inf)) { - continue; /* Bypass condition */ - } - /* Push the node to actual_track_list */ - actual_track_list.push_back(track_list[inode]); - } - /* Check the actual track list */ - assert (0 == actual_track_list.size() % 2); - - /* Scale Fc */ - int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width); - /* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */ - actual_Fc = std::max(1, actual_Fc); - /* Compute the step between two connection from this IPIN to tracks: - * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in - */ - size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); - /* Make sure step should be at least 2 */ - track_step = std::max(1, (int)track_step); - /* Adapt offset to the range of actual_track_list */ - size_t actual_offset = offset % actual_track_list.size(); - /* rotate the track list by an offset */ - if (0 < actual_offset) { - std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); - } - - /* Assign tracks: since we assign 2 track per round, we increment itrack by 2* step */ - int track_cnt = 0; - /* Keep assigning until we meet the Fc requirement */ - for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + 2 * track_step) { - /* Update pin2track map */ - size_t chan_side_index = chan_side_manager.to_size_t(); - size_t ipin_index = ipin_node - rr_graph->rr_node; - /* itrack may exceed the size of actual_track_list, adapt it */ - size_t actual_itrack = itrack % actual_track_list.size(); - /* track_index may exceed the chan_width(), adapt it */ - size_t track_index = actual_track_list[actual_itrack] % chan_width; - - (*track2ipin_map)[chan_side_index][track_index].push_back(ipin_index); - - /* track_index may exceed the chan_width(), adapt it */ - track_index = (actual_track_list[actual_itrack] + 1) % chan_width; - - (*track2ipin_map)[chan_side_index][track_index].push_back(ipin_index); - - track_cnt += 2; - } - - /* Ensure the number of tracks is similar to Fc */ - /* Give a warning if Fc is < track_cnt */ - /* - if (actual_Fc != track_cnt) { - vpr_printf(TIO_MESSAGE_INFO, - "IPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", - ipin_node - rr_graph->rr_node, track_cnt, actual_Fc); - } - */ - } - - return; -} - -/************************************************************************ - * Build opin2track_map for an OPIN - * 1. build a list of routing tracks which are allowed for connections - * We will check the Switch Block (SB) population of each routing track. - * By comparing current chan_y - ylow, we can determine if a SB connection - * is required for each routing track - * 2. Divide the routing tracks by segment types, so that we can balance - * the connections between OPINs and different types of routing tracks. - * 3. Scale the Fc of each pin to the actual number of routing tracks - * actual_Fc = (int) Fc * num_tracks / chan_width - ***********************************************************************/ -static -void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, - const RRGSB& rr_gsb, - const enum e_side opin_side, - const size_t opin_node_id, - const size_t Fc, - const size_t offset, - const std::vector segment_inf, - t_pin2track_map* opin2track_map) { - /* Get a list of segment_ids*/ - std::vector seg_list = rr_gsb.get_chan_segment_ids(opin_side); - enum e_side chan_side = opin_side; - size_t chan_width = rr_gsb.get_chan_width(chan_side); - Side opin_side_manager(opin_side); - - for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { - /* Get a list of node that have the segment id */ - std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]); - /* Refine the track_list: keep those will have connection blocks in the GSB */ - std::vector actual_track_list; - for (size_t inode = 0; inode < track_list.size(); ++inode) { - /* Check if tracks allow connection blocks in the GSB*/ - if (false == is_gsb_in_track_sb_population(rr_gsb, chan_side, - track_list[inode], segment_inf)) { - continue; /* Bypass condition */ - } - if (TRACK_START != determine_track_status_of_gsb(rr_gsb, chan_side, track_list[inode])) { - continue; /* Bypass condition */ - } - /* Push the node to actual_track_list */ - actual_track_list.push_back(track_list[inode]); - } - - /* Go the next segment if offset is zero or actual_track_list is empty */ - if (0 == actual_track_list.size()) { - continue; - } - - /* Scale Fc */ - int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width); - /* Minimum Fc should be 1 : ensure we will drive 1 routing track */ - actual_Fc = std::max(1, actual_Fc); - /* Compute the step between two connection from this IPIN to tracks: - * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in - */ - size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); - /* Track step mush be a multiple of 2!!!*/ - /* Make sure step should be at least 1 */ - track_step = std::max(1, (int)track_step); - /* Adapt offset to the range of actual_track_list */ - size_t actual_offset = offset % actual_track_list.size(); - - /* No need to rotate if offset is zero */ - if (0 < actual_offset) { - /* rotate the track list by an offset */ - std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); - } - - /* Assign tracks */ - int track_cnt = 0; - /* Keep assigning until we meet the Fc requirement */ - for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + track_step) { - /* Update pin2track map */ - size_t opin_side_index = opin_side_manager.to_size_t(); - /* itrack may exceed the size of actual_track_list, adapt it */ - size_t actual_itrack = itrack % actual_track_list.size(); - size_t track_index = actual_track_list[actual_itrack]; - size_t track_rr_node_index = rr_gsb.get_chan_node(chan_side, track_index) - rr_graph->rr_node; - (*opin2track_map)[opin_side_index][opin_node_id].push_back(track_rr_node_index); - /* update track counter */ - track_cnt++; - /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. - * So I comment it. And we just make sure its track_cnt >= actual_Fc - if (actual_Fc == track_cnt) { - break; - } - */ - } - - /* Ensure the number of tracks is similar to Fc */ - /* Give a warning if Fc is < track_cnt */ - /* - if (actual_Fc != track_cnt) { - vpr_printf(TIO_MESSAGE_INFO, - "OPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", - opin_node_id, track_cnt, actual_Fc); - } - */ - } - - return; -} - - -/************************************************************************ - * Build the track_to_ipin_map[gsb_side][0..chan_width-1][ipin_indices] - * based on the existing routing resources in the General Switch Block (GSB) - * This function supports both X-directional and Y-directional tracks - * The mapping is done in the following steps: - * 1. Build ipin_to_track_map[gsb_side][0..num_ipin_nodes-1][track_indices] - * For each IPIN, we ensure at least one connection to the tracks. - * Then, we assign IPINs to tracks evenly while satisfying the actual_Fc - * 2. Convert the ipin_to_track_map to track_to_ipin_map - ***********************************************************************/ -t_track2pin_map build_gsb_track_to_ipin_map(t_rr_graph* rr_graph, - const RRGSB& rr_gsb, - const std::vector> grids, - const std::vector segment_inf, - int** Fc_in) { - t_track2pin_map track2ipin_map; - /* Resize the matrix */ - track2ipin_map.resize(rr_gsb.get_num_sides()); - - /* offset counter: it aims to balance the track-to-IPIN for each connection block */ - size_t offset_size = 0; - std::vector offset; - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - enum e_side ipin_side = side_manager.get_side(); - /* Get the chan_side */ - enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); - Side chan_side_manager(chan_side); - /* resize offset to the maximum chan_side*/ - offset_size = std::max(offset_size, chan_side_manager.to_size_t() + 1); - } - /* Initial offset */ - offset.resize(offset_size); - offset.assign(offset.size(), 0); - - /* Walk through each side */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - enum e_side ipin_side = side_manager.get_side(); - /* Get the chan_side */ - enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); - Side chan_side_manager(chan_side); - /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ - /* Get channel width and resize the matrix */ - size_t chan_width = rr_gsb.get_chan_width(chan_side); - track2ipin_map[chan_side_manager.to_size_t()].resize(chan_width); - /* Find the ipin/opin nodes */ - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(ipin_side); ++inode) { - t_rr_node* ipin_node = rr_gsb.get_ipin_node(ipin_side, inode); - /* Skip EMPTY type */ - if (EMPTY_TYPE == grids[ipin_node->xlow][ipin_node->ylow].type) { - continue; - } - int grid_type_index = grids[ipin_node->xlow][ipin_node->ylow].type->index; - /* Get Fc of the ipin */ - int ipin_Fc = Fc_in[grid_type_index][ipin_node->ptc_num]; - /* skip Fc = 0 */ - if ( (-1 == ipin_Fc) - || (0 == ipin_Fc) ) { - continue; - } - /* Build track2ipin_map for this IPIN */ - build_gsb_one_ipin_track2pin_map(rr_graph, rr_gsb, ipin_side, inode, ipin_Fc, - /* Give an offset for the first track that this ipin will connect to */ - offset[chan_side_manager.to_size_t()], - segment_inf, &track2ipin_map); - /* update offset */ - offset[chan_side_manager.to_size_t()] += 2; - //printf("offset[%lu]=%lu\n", chan_side_manager.to_size_t(), offset[chan_side_manager.to_size_t()]); - } - } - - return track2ipin_map; -} - -/************************************************************************ - * Build the opin_to_track_map[gsb_side][0..num_opin_nodes-1][track_indices] - * based on the existing routing resources in the General Switch Block (GSB) - * This function supports both X-directional and Y-directional tracks - * The mapping is done in the following steps: - * 1. Build a list of routing tracks whose starting points locate at this GSB - * (xlow - gsb_x == 0) - * 2. Divide the routing tracks by segment types, so that we can balance - * the connections between OPINs and different types of routing tracks. - * 3. Scale the Fc of each pin to the actual number of routing tracks - * actual_Fc = (int) Fc * num_tracks / chan_width - ***********************************************************************/ -t_pin2track_map build_gsb_opin_to_track_map(t_rr_graph* rr_graph, - const RRGSB& rr_gsb, - const std::vector> grids, - const std::vector segment_inf, - int** Fc_out) { - t_pin2track_map opin2track_map; - /* Resize the matrix */ - opin2track_map.resize(rr_gsb.get_num_sides()); - - /* offset counter: it aims to balance the OPIN-to-track for each switch block */ - std::vector offset; - /* Get the chan_side: which is the same as the opin side */ - offset.resize(rr_gsb.get_num_sides()); - /* Initial offset */ - offset.assign(offset.size(), 0); - - /* Walk through each side */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - enum e_side opin_side = side_manager.get_side(); - /* Get the chan_side */ - /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ - /* Get channel width and resize the matrix */ - size_t num_opin_nodes = rr_gsb.get_num_opin_nodes(opin_side); - opin2track_map[side].resize(num_opin_nodes); - /* Find the ipin/opin nodes */ - for (size_t inode = 0; inode < num_opin_nodes; ++inode) { - t_rr_node* opin_node = rr_gsb.get_opin_node(opin_side, inode); - /* Skip EMPTY type */ - if (EMPTY_TYPE == grids[opin_node->xlow][opin_node->ylow].type) { - continue; - } - int grid_type_index = grids[opin_node->xlow][opin_node->ylow].type->index; - /* Get Fc of the ipin */ - int opin_Fc = Fc_out[grid_type_index][opin_node->ptc_num]; - /* skip Fc = 0 or unintialized, those pins are in the */ - if ( (-1 == opin_Fc) - || (0 == opin_Fc) ) { - continue; - } - /* Build track2ipin_map for this IPIN */ - build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_Fc, - /* Give an offset for the first track that this ipin will connect to */ - offset[side_manager.to_size_t()], - segment_inf, &opin2track_map); - /* update offset: aim to rotate starting tracks by 1*/ - offset[side_manager.to_size_t()] += 1; - } - - /* Check: - * 1. We want to ensure that each OPIN will drive at least one track - * 2. We want to ensure that each track will be driven by at least 1 OPIN */ - } - - return opin2track_map; -} - - -/************************************************************************ - * Add all direct clb-pin-to-clb-pin edges to given opin - ***********************************************************************/ -void build_direct_connections_for_one_gsb(t_rr_graph* rr_graph, - const DeviceCoordinator& device_size, - const std::vector> grids, - const DeviceCoordinator& from_grid_coordinator, - const t_grid_tile& from_grid, - const int delayless_switch, - const int num_directs, - const t_direct_inf *directs, - const t_clb_to_clb_directs *clb_to_clb_directs) { - t_type_ptr grid_type = from_grid.type; - - /* Iterate through all direct connections */ - for (int i = 0; i < num_directs; ++i) { - /* Bypass unmatched direct clb-to-clb connections */ - if (grid_type != clb_to_clb_directs[i].from_clb_type) { - continue; - } - - /* This opin is specified to connect directly to an ipin, - * now compute which ipin to connect to - */ - DeviceCoordinator to_grid_coordinator(from_grid_coordinator.get_x() + directs[i].x_offset, - from_grid_coordinator.get_y() + directs[i].y_offset); - - /* Bypass unmatched direct clb-to-clb connections */ - t_type_ptr to_grid_type = grids[to_grid_coordinator.get_x()][to_grid_coordinator.get_y()].type; - /* Check if to_grid if the same grid */ - if (to_grid_type != clb_to_clb_directs[i].to_clb_type) { - continue; - } - - bool swap; - int max_index, min_index; - /* Compute index of opin with regards to given pins */ - if ( clb_to_clb_directs[i].from_clb_pin_start_index - > clb_to_clb_directs[i].from_clb_pin_end_index) { - swap = true; - max_index = clb_to_clb_directs[i].from_clb_pin_start_index; - min_index = clb_to_clb_directs[i].from_clb_pin_end_index; - } else { - swap = false; - min_index = clb_to_clb_directs[i].from_clb_pin_start_index; - max_index = clb_to_clb_directs[i].from_clb_pin_end_index; - } - - /* get every opin in the range */ - for (int opin = min_index; opin <= max_index; ++opin) { - int offset = opin - min_index; - - if ( (to_grid_coordinator.get_x() < device_size.get_x() - 1) - && (to_grid_coordinator.get_y() < device_size.get_y() - 1) ) { - int ipin = OPEN; - if ( clb_to_clb_directs[i].to_clb_pin_start_index - > clb_to_clb_directs[i].to_clb_pin_end_index) { - if (true == swap) { - ipin = clb_to_clb_directs[i].to_clb_pin_end_index + offset; - } else { - ipin = clb_to_clb_directs[i].to_clb_pin_start_index - offset; - } - } else { - if(true == swap) { - ipin = clb_to_clb_directs[i].to_clb_pin_end_index - offset; - } else { - ipin = clb_to_clb_directs[i].to_clb_pin_start_index + offset; - } - } - - /* Get the pin index in the rr_graph */ - int from_grid_ofs = from_grid.offset; - int to_grid_ofs = grids[to_grid_coordinator.get_x()][to_grid_coordinator.get_y()].offset; - int opin_node_id = get_rr_node_index(from_grid_coordinator.get_x(), - from_grid_coordinator.get_y() - from_grid_ofs, - OPIN, opin, rr_graph->rr_node_indices); - int ipin_node_id = get_rr_node_index(to_grid_coordinator.get_x(), - to_grid_coordinator.get_y() - to_grid_ofs, - IPIN, ipin, rr_graph->rr_node_indices); - /* add edges to the opin_node */ - add_one_edge_for_two_rr_nodes(rr_graph, opin_node_id, ipin_node_id, - delayless_switch); - } - } - } - - return; -} - -/************************************************************************ - * End of file : rr_graph_tileable_gsb.cpp - ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h deleted file mode 100755 index c860c3695..000000000 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h +++ /dev/null @@ -1,68 +0,0 @@ -#ifndef TILEABLE_RR_GRAPH_GSB_H -#define TILEABLE_RR_GRAPH_GSB_H - -#include - -#include "vtr_ndmatrix.h" - -#include "rr_blocks.h" -#include "fpga_x2p_types.h" - - -/************************************************************************ - * Data stuctures related to the functions - ***********************************************************************/ -typedef std::vector>> t_track2track_map; -typedef std::vector>> t_track2pin_map; -typedef std::vector>> t_pin2track_map; - -/************************************************************************ - * Functions - ***********************************************************************/ -t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph, - const RRGSB& rr_gsb, - const enum e_switch_block_type sb_type, - const int Fs, - const enum e_switch_block_type sb_subtype, - const int subFs, - const bool wire_opposite_side, - const std::vector segment_inf); - -RRGSB build_one_tileable_rr_gsb(const DeviceCoordinator& device_range, - const std::vector device_chan_width, - const std::vector segment_inf, - const DeviceCoordinator& gsb_coordinator, - t_rr_graph* rr_graph); - -void build_edges_for_one_tileable_rr_gsb(const t_rr_graph* rr_graph, - const RRGSB* rr_gsb, - const t_track2pin_map track2ipin_map, - const t_pin2track_map opin2track_map, - const t_track2track_map track2track_map); - -t_track2pin_map build_gsb_track_to_ipin_map(t_rr_graph* rr_graph, - const RRGSB& rr_gsb, - const std::vector> grids, - const std::vector segment_inf, - int** Fc_in); - -t_pin2track_map build_gsb_opin_to_track_map(t_rr_graph* rr_graph, - const RRGSB& rr_gsb, - const std::vector> grids, - const std::vector segment_inf, - int** Fc_out); - -void build_direct_connections_for_one_gsb(t_rr_graph* rr_graph, - const DeviceCoordinator& device_size, - const std::vector> grids, - const DeviceCoordinator& from_grid_coordinator, - const t_grid_tile& from_grid, - const int delayless_switch, - const int num_directs, - const t_direct_inf *directs, - const t_clb_to_clb_directs *clb_to_clb_directs); - - - -#endif - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp deleted file mode 100644 index 9eac8c52a..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.cpp +++ /dev/null @@ -1,624 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to write SDC commands - * to disable unused ports of grids, such as Configurable Logic Block - * (CLBs), heterogeneous blocks, etc. - *******************************************************************/ -#include "vtr_assert.h" - -#include "fpga_x2p_reserved_words.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" - -#include "sdc_writer_utils.h" -#include "analysis_sdc_writer_utils.h" -#include "analysis_sdc_grid_writer.h" - -#include "globals.h" - -/******************************************************************** - * Recursively visit all the pb_types in the hierarchy - * and disable all the ports - * - * Note: it is a must to disable all the ports in all the child pb_types! - * This can prohibit timing analyzer to consider any FF-to-FF path or - * combinatinal path inside an unused grid, when finding critical paths!!! - *******************************************************************/ -static -void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& hierarchy_name, - t_pb_graph_node* physical_pb_graph_node, - const e_side& border_side) { - t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; - - /* Validate file stream */ - check_file_handler(fp); - - /* Disable all the ports of current module (parent_module)! - * Hierarchy name already includes the instance name of parent_module - */ - fp << "set_disable_timing "; - fp << hierarchy_name; - fp << "/*"; - fp << std::endl; - - /* Return if this is the primitive pb_type */ - if (TRUE == is_primitive_pb_type(physical_pb_type)) { - return; - } - - /* Go recursively */ - int physical_mode_index = find_pb_type_physical_mode_index(*physical_pb_type); - - /* Disable all the ports by iterating over its instance in the parent module */ - for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { - /* Generate the name of the Verilog module for this child */ - std::string child_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); - std::string child_module_name = generate_physical_block_module_name(child_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild])); - - ModuleId child_module = module_manager.find_module(child_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(child_module)); - - /* Each child may exist multiple times in the hierarchy*/ - for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { - std::string child_instance_name = module_manager.instance_name(parent_module, child_module, module_manager.child_module_instances(parent_module, child_module)[inst]); - /* Must have a valid instance name!!! */ - VTR_ASSERT(false == child_instance_name.empty()); - - std::string updated_hierarchy_name = hierarchy_name + std::string("/") + child_instance_name + std::string("/"); - - rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, module_manager, child_module, hierarchy_name, - &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst]), - border_side); - } - } -} - -/******************************************************************** - * Disable an unused pin of a pb_graph_node (parent_module) - *******************************************************************/ -static -void disable_pb_graph_node_unused_pin(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& hierarchy_name, - const t_pb_graph_pin& pb_graph_pin, - t_phy_pb* block_physical_pb) { - /* Validate file stream */ - check_file_handler(fp); - - int rr_node_index = pb_graph_pin.rr_node_index_physical_pb; - - /* Identify if the net has been used or not */ - if (false == is_rr_node_to_be_disable_for_analysis(&(block_physical_pb->rr_graph->rr_node[rr_node_index]))) { - /* Used pin; Nothing to do */ - return; - } - /* Reach here, it means that this pin is not used. Disable timing analysis for the pin */ - /* Find the module port by name */ - std::string module_port_name = generate_pb_type_port_name(pb_graph_pin.port); - ModulePortId module_port = module_manager.find_module_port(parent_module, module_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(parent_module, module_port)); - BasicPort port_to_disable = module_manager.module_port(parent_module, module_port); - port_to_disable.set_width(pb_graph_pin.pin_number, pb_graph_pin.pin_number); - - fp << "set_disable_timing "; - fp << hierarchy_name; - fp << "/"; - fp << generate_sdc_port(port_to_disable); - fp << std::endl; -} - -/******************************************************************** - * Disable unused input ports and output ports of this pb_graph_node (parent_module) - * This function will iterate over all the input pins, output pins - * of the physical_pb_graph_node, and check if they are mapped - * For unused pins, we will find the port in parent_module - * and then print SDC commands to disable them - *******************************************************************/ -static -void disable_pb_graph_node_unused_pins(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& hierarchy_name, - t_pb_graph_node* physical_pb_graph_node, - t_phy_pb* block_physical_pb) { - - /* Disable unused input pins */ - for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) { - for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) { - disable_pb_graph_node_unused_pin(fp, module_manager, parent_module, - hierarchy_name, - physical_pb_graph_node->input_pins[iport][ipin], - block_physical_pb); - } - } - - /* Disable unused output pins */ - for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) { - for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) { - disable_pb_graph_node_unused_pin(fp, module_manager, parent_module, - hierarchy_name, - physical_pb_graph_node->output_pins[iport][ipin], - block_physical_pb); - } - } - - /* Disable unused clock pins */ - for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) { - for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) { - disable_pb_graph_node_unused_pin(fp, module_manager, parent_module, - hierarchy_name, - physical_pb_graph_node->clock_pins[iport][ipin], - block_physical_pb); - } - } -} - -/******************************************************************** - * Disable unused inputs of routing multiplexers of this pb_graph_node - * This function will first cache the nets for each input and output pins - * and store the results in a mux_name-to-net mapping - *******************************************************************/ -static -void disable_pb_graph_node_unused_mux_inputs(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& hierarchy_name, - t_pb_graph_node* physical_pb_graph_node, - t_phy_pb* block_physical_pb, - const e_side& border_side) { - t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; - - int physical_mode_index = find_pb_type_physical_mode_index(*physical_pb_type); - - std::map mux_instance_to_net_map; - - /* Cache the nets for each input pins of each child pb_graph_node */ - for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { - for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { - - t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst]); - - /* Cache the nets for input pins of the child pb_graph_node */ - for (int iport = 0; iport < child_pb_graph_node->num_input_ports; ++iport) { - for (int ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ++ipin) { - int rr_node_index = child_pb_graph_node->input_pins[iport][ipin].rr_node_index_physical_pb; - /* Generate the mux name */ - std::string mux_instance_name = generate_pb_mux_instance_name(GRID_MUX_INSTANCE_PREFIX, &(child_pb_graph_node->input_pins[iport][ipin]), std::string("")); - /* Cache the net */ - mux_instance_to_net_map[mux_instance_name] = block_physical_pb->rr_graph->rr_node[rr_node_index].vpack_net_num; - } - } - - /* Cache the nets for clock pins of the child pb_graph_node */ - for (int iport = 0; iport < child_pb_graph_node->num_clock_ports; ++iport) { - for (int ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ++ipin) { - int rr_node_index = child_pb_graph_node->clock_pins[iport][ipin].rr_node_index_physical_pb; - /* Generate the mux name */ - std::string mux_instance_name = generate_pb_mux_instance_name(GRID_MUX_INSTANCE_PREFIX, &(child_pb_graph_node->clock_pins[iport][ipin]), std::string("")); - /* Cache the net */ - mux_instance_to_net_map[mux_instance_name] = block_physical_pb->rr_graph->rr_node[rr_node_index].vpack_net_num; - } - } - - } - } - - /* Cache the nets for each output pins of this pb_graph_node */ - for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) { - for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) { - int rr_node_index = physical_pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; - /* Generate the mux name */ - std::string mux_instance_name = generate_pb_mux_instance_name(GRID_MUX_INSTANCE_PREFIX, &(physical_pb_graph_node->output_pins[iport][ipin]), std::string("")); - /* Cache the net */ - mux_instance_to_net_map[mux_instance_name] = block_physical_pb->rr_graph->rr_node[rr_node_index].vpack_net_num; - } - } - - /* Now disable unused inputs of routing multiplexers, by tracing from input pins of the parent_module */ - for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) { - for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) { - /* Find the module port by name */ - std::string module_port_name = generate_pb_type_port_name(physical_pb_graph_node->input_pins[iport][ipin].port); - ModulePortId module_port = module_manager.find_module_port(parent_module, module_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(parent_module, module_port)); - - int rr_node_index = physical_pb_graph_node->input_pins[iport][ipin].rr_node_index_physical_pb; - t_rr_node* input_rr_node = &(block_physical_pb->rr_graph->rr_node[rr_node_index]); - - disable_analysis_module_input_pin_net_sinks(fp, module_manager, parent_module, - hierarchy_name, - module_port, ipin, - input_rr_node, - mux_instance_to_net_map); - } - } - - for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) { - for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) { - /* Find the module port by name */ - std::string module_port_name = generate_pb_type_port_name(physical_pb_graph_node->clock_pins[iport][ipin].port); - ModulePortId module_port = module_manager.find_module_port(parent_module, module_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(parent_module, module_port)); - - int rr_node_index = physical_pb_graph_node->clock_pins[iport][ipin].rr_node_index_physical_pb; - t_rr_node* input_rr_node = &(block_physical_pb->rr_graph->rr_node[rr_node_index]); - - disable_analysis_module_input_pin_net_sinks(fp, module_manager, parent_module, - hierarchy_name, - module_port, ipin, - input_rr_node, - mux_instance_to_net_map); - } - } - - /* Now disable unused inputs of routing multiplexers, by tracing from output pins of the child_module */ - for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { - /* Generate the name of the Verilog module for this child */ - std::string child_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); - std::string child_module_name = generate_physical_block_module_name(child_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild])); - - ModuleId child_module = module_manager.find_module(child_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(child_module)); - - for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { - - t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst]); - - for (int iport = 0; iport < child_pb_graph_node->num_output_ports; ++iport) { - for (int ipin = 0; ipin < child_pb_graph_node->num_output_pins[iport]; ++ipin) { - /* Find the module port by name */ - std::string module_port_name = generate_pb_type_port_name(child_pb_graph_node->output_pins[iport][ipin].port); - ModulePortId module_port = module_manager.find_module_port(child_module, module_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, module_port)); - - int rr_node_index = child_pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; - t_rr_node* output_rr_node = &(block_physical_pb->rr_graph->rr_node[rr_node_index]); - - /* Corner case: if the rr node has no fan-out we will skip this pin */ - if (0 == output_rr_node->num_edges) { - continue; - } - - disable_analysis_module_output_pin_net_sinks(fp, module_manager, parent_module, - hierarchy_name, - child_module, inst, - module_port, ipin, - output_rr_node, - mux_instance_to_net_map); - } - } - } - } -} - -/******************************************************************** - * Recursively visit all the pb_types in the hierarchy - * and disable all the unused resources, including: - * 1. input ports - * 2. output ports - * 3. unused inputs of routing multiplexers - * - * As this function is executed in a recursive way. - * To avoid repeated disable timing for ports, during each run of this function, - * only the unused input ports, output ports of the parent module will be disabled. - * In addition, we will cache all the net ids mapped to the input ports of - * child modules, and the net ids mapped to the output ports of parent module. - * As such, we can trace from - * 1. the input ports of parent module to disable unused inputs of routing multiplexer - * which drives the inputs of child modules - * - * Parent_module - * +--------------------------------------------- - * | MUX child_module - * | +-------------+ +-------- - * input_pin0(netA) --->|-------->| Routing |------>| - * input_pin1(netB) --->|----x--->| Multiplexer | netA | - * | +-------------+ | - * | | - * - * 2. the output ports of child module to disable unused inputs of routing multiplexer - * which drives the outputs of parent modules - * - * Case 1: - * parent_module - * --------------------------------------+ - * child_module | - * -------------+ | - * | +-------------+ | - * output_pin0 (netA) |--->| Routing |----->|----> - * output_pin1 (netB) |-x->| Multiplexer | netA | - * | +-------------+ | - * - * Case 2: - * - * Parent_module - * +--------------------------------------------- - * | - * | +--------------------------------------------+ - * | | MUX child_module | - * | | +-------------+ +-----------+ | - * | +--->| Routing |------>| | | - * input_pin0(netA) --->|----x--->| Multiplexer | netA | output_pin|-----+ - * | +-------------+ | | netA - * | | | - * - * - * Note: it is a must to disable all the ports in all the child pb_types! - * This can prohibit timing analyzer to consider any FF-to-FF path or - * combinatinal path inside an unused grid, when finding critical paths!!! - *******************************************************************/ -static -void rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& hierarchy_name, - t_pb_graph_node* physical_pb_graph_node, - t_phy_pb* block_physical_pb, - const e_side& border_side) { - t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; - - /* Disable unused input ports and output ports of this pb_graph_node (parent_module) */ - disable_pb_graph_node_unused_pins(fp, module_manager, parent_module, - hierarchy_name, physical_pb_graph_node, block_physical_pb); - - /* Return if this is the primitive pb_type - * Note: this must return before we disable any unused inputs of routing multiplexer! - * This is due to that primitive pb_type does NOT contain any routing multiplexers inside!!! - */ - if (TRUE == is_primitive_pb_type(physical_pb_type)) { - return; - } - - /* Disable unused inputs of routing multiplexers of this pb_graph_node */ - disable_pb_graph_node_unused_mux_inputs(fp, module_manager, parent_module, - hierarchy_name, physical_pb_graph_node, block_physical_pb, - border_side); - - - int physical_mode_index = find_pb_type_physical_mode_index(*physical_pb_type); - - /* Disable all the ports by iterating over its instance in the parent module */ - for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { - /* Generate the name of the Verilog module for this child */ - std::string child_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); - std::string child_module_name = generate_physical_block_module_name(child_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild])); - - ModuleId child_module = module_manager.find_module(child_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(child_module)); - - /* Each child may exist multiple times in the hierarchy*/ - for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { - std::string child_instance_name = module_manager.instance_name(parent_module, child_module, module_manager.child_module_instances(parent_module, child_module)[inst]); - /* Must have a valid instance name!!! */ - VTR_ASSERT(false == child_instance_name.empty()); - - std::string updated_hierarchy_name = hierarchy_name + std::string("/") + child_instance_name + std::string("/"); - - rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(fp, module_manager, child_module, hierarchy_name, - &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst]), - block_physical_pb, border_side); - } - } -} - -/******************************************************************** - * This function can work in two differnt modes: - * 1. For partially unused pb blocks - * --------------------------------- - * Disable the timing for only unused resources in a physical block - * We have to walk through pb_graph node, port by port and pin by pin. - * Identify which pins have not been used, and then disable the timing - * for these ports. - * Plus, for input ports, we will trace the routing multiplexers - * and disable the timing for unused inputs. - * - * 2. For fully unused pb_blocks - * ----------------------------- - * Disable the timing for a fully unused grid! - * This is very straightforward! - * Just walk through each pb_type and disable all the ports using wildcards - *******************************************************************/ -static -void print_analysis_sdc_disable_pb_block_unused_resources(std::fstream& fp, - t_type_ptr grid_type, - const vtr::Point& grid_coordinate, - const ModuleManager& module_manager, - const std::string& grid_instance_name, - const size_t& grid_z, - const e_side& border_side, - t_phy_pb* block_physical_pb, - const bool& unused_block) { - /* Check code: if this is an IO block, the border side MUST be valid */ - if (IO_TYPE == grid_type) { - VTR_ASSERT(NUM_SIDES != border_side); - } - - /* If the block is partially unused, we should have a physical pb */ - if (false == unused_block) { - VTR_ASSERT(NULL != block_physical_pb); - } - - /* Find an unique name to the pb instance in this grid - * Note: this must be consistent with the instance name we used in build_grid_module()!!! - */ - /* TODO: validate that the instance name is used in module manager!!! */ - std::string pb_module_name_prefix(GRID_MODULE_NAME_PREFIX); - std::string pb_module_name = generate_grid_physical_block_module_name(pb_module_name_prefix, grid_type->pb_graph_head->pb_type, border_side); - std::string pb_instance_name = generate_grid_physical_block_instance_name(pb_module_name_prefix, grid_type->pb_graph_head->pb_type, border_side, grid_z); - - ModuleId pb_module = module_manager.find_module(pb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); - - /* Print comments */ - fp << "#######################################" << std::endl; - - if (true == unused_block) { - fp << "# Disable Timing for unused grid[" << grid_coordinate.x() << "][" << grid_coordinate.y() << "][" << grid_z << "]" << std::endl; - } else { - VTR_ASSERT_SAFE(false == unused_block); - fp << "# Disable Timing for unused resources in grid[" << grid_coordinate.x() << "][" << grid_coordinate.y() << "][" << grid_z << "]" << std::endl; - } - - fp << "#######################################" << std::endl; - - std::string hierarchy_name = grid_instance_name + std::string("/") + pb_instance_name + std::string("/"); - - /* Go recursively through the pb_graph hierarchy, and disable all the ports level by level */ - if (true == unused_block) { - rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, module_manager, pb_module, hierarchy_name, grid_type->pb_graph_head, border_side); - } else { - VTR_ASSERT_SAFE(false == unused_block); - rec_print_analysis_sdc_disable_pb_graph_node_unused_resources(fp, module_manager, pb_module, hierarchy_name, grid_type->pb_graph_head, block_physical_pb, border_side); - } -} - -/******************************************************************** - * Disable the timing for a fully unused grid! - * This is very straightforward! - * Just walk through each pb_type and disable all the ports using wildcards - *******************************************************************/ -static -void print_analysis_sdc_disable_unused_grid(std::fstream& fp, - const vtr::Point& grid_coordinate, - const std::vector>& L_grids, - const std::vector& L_blocks, - const ModuleManager& module_manager, - const e_side& border_side) { - /* Validate file stream */ - check_file_handler(fp); - - t_type_ptr grid_type = L_grids[grid_coordinate.x()][grid_coordinate.y()].type; - /* Bypass conditions for grids : - * 1. EMPTY type, which is by nature unused - * 2. Offset > 0, which has already been processed when offset = 0 - */ - if ( (NULL == grid_type) - || (EMPTY_TYPE == grid_type) - || (0 < L_grids[grid_coordinate.x()][grid_coordinate.y()].offset) ) { - return; - } - - /* Find an unique name to the grid instane - * Note: this must be consistent with the instance name we used in build_top_module()!!! - */ - /* TODO: validate that the instance name is used in module manager!!! */ - std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); - std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side); - std::string grid_instance_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side, grid_coordinate); - - ModuleId grid_module = module_manager.find_module(grid_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); - - /* Now we need to find the usage of this grid */ - std::vector grid_usage(grid_type->capacity, false); - - /* Print comments */ - fp << "#######################################" << std::endl; - fp << "# Disable Timing for grid[" << grid_coordinate.x() << "][" << grid_coordinate.y() << "]" << std::endl; - fp << "#######################################" << std::endl; - - /* For used grid, find the unused rr_node in the local rr_graph - * and then disable each port which is not used - * as well as the unused inputs of routing multiplexers! - */ - for (int iblk = 0; iblk < L_grids[grid_coordinate.x()][grid_coordinate.y()].usage; ++iblk) { - int blk_id = L_grids[grid_coordinate.x()][grid_coordinate.y()].blocks[iblk]; - VTR_ASSERT( (OPEN < L_blocks[blk_id].z) && (L_blocks[blk_id].z < grid_type->capacity) ); - /* Mark the grid_usage */ - grid_usage[L_blocks[blk_id].z] = true; - /* TODO: - verilog_generate_sdc_disable_one_unused_block(fp, &(L_blocks[blk_id])); - */ - t_phy_pb* block_phy_pb = (t_phy_pb*) L_blocks[blk_id].phy_pb; - print_analysis_sdc_disable_pb_block_unused_resources(fp, grid_type, grid_coordinate, module_manager, grid_instance_name, iblk, border_side, block_phy_pb, false); - } - - /* For unused grid, disable all the pins in the physical_pb_type */ - for (int iblk = 0; iblk < grid_type->capacity; ++iblk) { - /* Bypass used blocks */ - if (true == grid_usage[iblk]) { - continue; - } - print_analysis_sdc_disable_pb_block_unused_resources(fp, grid_type, grid_coordinate, module_manager, grid_instance_name, iblk, border_side, NULL, true); - } -} - -/******************************************************************** - * Top-level function writes SDC commands to disable unused ports - * of grids, such as Configurable Logic Block (CLBs), heterogeneous blocks, etc. - * - * This function will iterate over all the grids available in the FPGA fabric - * It will disable the timing analysis for - * 1. Grids, which are totally not used (no logic has been mapped to) - * 2. Unused part of grids, including the ports, inputs of routing multiplexers - * - * Note that it is a must to disable the unused inputs of routing multiplexers - * because it will cause unexpected paths in timing analysis - * For example: - * +---------------------+ - * inputA (net0) ------->| | - * | Routing multiplexer |----> output (net0) - * inputB (net1) ------->| | - * +---------------------+ - * - * During timing analysis, the path from inputA to output should be considered - * while the path from inputB to output should NOT be considered!!! - * - *******************************************************************/ -void print_analysis_sdc_disable_unused_grids(std::fstream& fp, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const ModuleManager& module_manager) { - - /* Process unused core grids */ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - /* We should not meet any I/O grid */ - VTR_ASSERT(IO_TYPE != L_grids[ix][iy].type); - - print_analysis_sdc_disable_unused_grid(fp, vtr::Point(ix, iy), - L_grids, L_blocks, module_manager, NUM_SIDES); - } - } - - /* Instanciate I/O grids */ - /* Create the coordinate range for each side of FPGA fabric */ - std::vector io_sides{TOP, RIGHT, BOTTOM, LEFT}; - std::map>> io_coordinates; - - /* TOP side*/ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - io_coordinates[TOP].push_back(vtr::Point(ix, device_size.y() - 1)); - } - - /* RIGHT side */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - io_coordinates[RIGHT].push_back(vtr::Point(device_size.x() - 1, iy)); - } - - /* BOTTOM side*/ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - io_coordinates[BOTTOM].push_back(vtr::Point(ix, 0)); - } - - /* LEFT side */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - io_coordinates[LEFT].push_back(vtr::Point(0, iy)); - } - - /* Add instances of I/O grids to top_module */ - for (const e_side& io_side : io_sides) { - for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { - /* We should not meet any I/O grid */ - VTR_ASSERT(IO_TYPE == L_grids[io_coordinate.x()][io_coordinate.y()].type); - - print_analysis_sdc_disable_unused_grid(fp, io_coordinate, - L_grids, L_blocks, module_manager, io_side); - } - } -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.h deleted file mode 100644 index a198cc129..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_grid_writer.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef ANALYSIS_SDC_GRID_WRITER_H -#define ANALYSIS_SDC_GRID_WRITER_H - -#include -#include -#include "vtr_geometry.h" -#include "vpr_types.h" -#include "module_manager.h" - -void print_analysis_sdc_disable_unused_grids(std::fstream& fp, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const ModuleManager& module_manager); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp deleted file mode 100644 index c823b6f69..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.cpp +++ /dev/null @@ -1,540 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to output a SDC file - * that constrain routing modules of a FPGA fabric (P&Red netlist) - * using a benchmark - *******************************************************************/ -#include - -#include "vtr_assert.h" -#include "device_port.h" - -#include "fpga_x2p_reserved_words.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_types.h" - -#include "sdc_writer_utils.h" -#include "analysis_sdc_writer_utils.h" -#include "analysis_sdc_routing_writer.h" - -#include "globals.h" - -/******************************************************************** - * This function will disable - * 1. all the unused port (unmapped by a benchmark) of a connection block - * 2. all the unused inputs (unmapped by a benchmark) of routing multiplexers - * in a connection block - *******************************************************************/ -static -void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const bool& compact_routing_hierarchy) { - /* Validate file stream */ - check_file_handler(fp); - - vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - - std::string cb_instance_name = generate_connection_block_module_name(cb_type, gsb_coordinate); - - /* If we use the compact routing hierarchy, we need to find the module name !*/ - vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - if (true == compact_routing_hierarchy) { - DeviceCoordinator cb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - /* Note: use GSB coordinate when inquire for unique modules!!! */ - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); - cb_coordinate.set_x(unique_mirror.get_cb_x(cb_type)); - cb_coordinate.set_y(unique_mirror.get_cb_y(cb_type)); - } - - std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coordinate); - - ModuleId cb_module = module_manager.find_module(cb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); - - /* Print comments */ - fp << "##################################################" << std::endl; - fp << "# Disable timing for Connection block " << cb_module_name << std::endl; - fp << "##################################################" << std::endl; - - /* Disable all the input port (routing tracks), which are not used by benchmark */ - for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { - t_rr_node* chan_node = rr_gsb.get_chan_node(rr_gsb.get_cb_chan_side(cb_type), itrack); - /* Check if this node is used by benchmark */ - if (false == is_rr_node_to_be_disable_for_analysis(chan_node)) { - continue; - } - - /* Disable both input of the routing track if it is not used! */ - vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - if (true == compact_routing_hierarchy) { - /* Note: use GSB coordinate when inquire for unique modules!!! */ - DeviceCoordinator cb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); - port_coord.set_x(unique_mirror.get_cb_x(cb_type)); - port_coord.set_y(unique_mirror.get_cb_y(cb_type)); - } - std::string port_name = generate_cb_module_track_port_name(cb_type, - itrack, - IN_PORT); - - /* Ensure we have this port in the module! */ - ModulePortId module_port = module_manager.find_module_port(cb_module, port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port)); - - fp << "set_disable_timing "; - fp << cb_instance_name << "/"; - fp << generate_sdc_port(module_manager.module_port(cb_module, module_port)); - fp << std::endl; - } - - /* Disable all the output port (routing tracks), which are not used by benchmark */ - for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { - t_rr_node* chan_node = rr_gsb.get_chan_node(rr_gsb.get_cb_chan_side(cb_type), itrack); - /* Check if this node is used by benchmark */ - if (false == is_rr_node_to_be_disable_for_analysis(chan_node)) { - continue; - } - - /* Disable both input of the routing track if it is not used! */ - vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - if (true == compact_routing_hierarchy) { - /* Note: use GSB coordinate when inquire for unique modules!!! */ - DeviceCoordinator cb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); - port_coord.set_x(unique_mirror.get_cb_x(cb_type)); - port_coord.set_y(unique_mirror.get_cb_y(cb_type)); - } - std::string port_name = generate_cb_module_track_port_name(cb_type, - itrack, - OUT_PORT); - - /* Ensure we have this port in the module! */ - ModulePortId module_port = module_manager.find_module_port(cb_module, port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port)); - - fp << "set_disable_timing "; - fp << cb_instance_name << "/"; - fp << generate_sdc_port(module_manager.module_port(cb_module, module_port)); - fp << std::endl; - } - - /* Build a map between mux_instance name and net_num */ - std::map mux_instance_to_net_map; - - /* Disable all the output port (grid input pins), which are not used by benchmark */ - std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); - - for (size_t side = 0; side < cb_sides.size(); ++side) { - enum e_side cb_ipin_side = cb_sides[side]; - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - t_rr_node* ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); - - /* Find the MUX instance that drives the IPIN! */ - std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), inode, std::string("")); - mux_instance_to_net_map[mux_instance_name] = ipin_node->vpack_net_num; - - if (false == is_rr_node_to_be_disable_for_analysis(ipin_node)) { - continue; - } - if (0 == ipin_node->fan_in) { - continue; - } - - vtr::Point port_coord(ipin_node->xlow, ipin_node->ylow); - std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side, - ipin_node->ptc_num); - - /* Find the port in unique mirror! */ - if (true == compact_routing_hierarchy) { - /* Note: use GSB coordinate when inquire for unique modules!!! */ - DeviceCoordinator cb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); - t_rr_node* unique_mirror_ipin_node = unique_mirror.get_ipin_node(cb_ipin_side, inode); - port_coord.set_x(unique_mirror_ipin_node->xlow); - port_coord.set_y(unique_mirror_ipin_node->ylow); - port_name = generate_cb_module_grid_port_name(cb_ipin_side, - unique_mirror_ipin_node->ptc_num); - } - - /* Ensure we have this port in the module! */ - ModulePortId module_port = module_manager.find_module_port(cb_module, port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port)); - - fp << "set_disable_timing "; - fp << cb_instance_name << "/"; - fp << generate_sdc_port(module_manager.module_port(cb_module, module_port)); - fp << std::endl; - } - } - - /* Disable all the unused inputs of routing multiplexers, which are not used by benchmark - * Here, we start from each input of the Connection Blocks, and traverse forward to the sink - * port of the module net whose source is the input - * We will find the instance name which is the parent of the sink port, and search the - * net id through the instance_name_to_net_map - * The the net id does not match the net id of this input, we will disable the sink port! - * - * cb_module - * +----------------------- - * | MUX instance A - * | +----------- - * input_port--->|--+---x-->| sink port (disable!) - * | | +---------- - * | | MUX instance B - * | | +---------- - * | +------>| sink port (do not disable!) - */ - for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { - t_rr_node* chan_node = rr_gsb.get_chan_node(rr_gsb.get_cb_chan_side(cb_type), itrack); - - /* Disable both input of the routing track if it is not used! */ - vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - if (true == compact_routing_hierarchy) { - /* Note: use GSB coordinate when inquire for unique modules!!! */ - DeviceCoordinator cb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); - port_coord.set_x(unique_mirror.get_cb_x(cb_type)); - port_coord.set_y(unique_mirror.get_cb_y(cb_type)); - } - std::string port_name = generate_cb_module_track_port_name(cb_type, - itrack, - OUT_PORT); - - /* Ensure we have this port in the module! */ - ModulePortId module_port = module_manager.find_module_port(cb_module, port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port)); - - disable_analysis_module_input_port_net_sinks(fp, - module_manager, cb_module, - cb_instance_name, - module_port, - chan_node, - mux_instance_to_net_map); - } -} - -/******************************************************************** - * Iterate over all the connection blocks in a device - * and disable unused ports for each of them - *******************************************************************/ -static -void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const t_rr_type& cb_type, - const bool& compact_routing_hierarchy) { - /* Build unique X-direction connection block modules */ - DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); - - for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { - /* Check if the connection block exists in the device! - * Some of them do NOT exist due to heterogeneous blocks (height > 1) - * We will skip those modules - */ - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - if (false == rr_gsb.is_cb_exist(cb_type)) { - continue; - } - - print_analysis_sdc_disable_cb_unused_resources(fp, - module_manager, - L_device_rr_gsb, - rr_gsb, - cb_type, - compact_routing_hierarchy); - } - } -} - -/******************************************************************** - * Iterate over all the connection blocks in a device - * and disable unused ports for each of them - *******************************************************************/ -void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const bool& compact_routing_hierarchy) { - - print_analysis_sdc_disable_unused_cb_ports(fp, module_manager, - L_device_rr_gsb, - CHANX, compact_routing_hierarchy); - - print_analysis_sdc_disable_unused_cb_ports(fp, module_manager, - L_device_rr_gsb, - CHANY, compact_routing_hierarchy); -} - -/******************************************************************** - * This function will disable - * 1. all the unused port (unmapped by a benchmark) of a switch block - * 2. all the unused inputs (unmapped by a benchmark) of routing multiplexers - * in a switch block - *******************************************************************/ -static -void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const RRGSB& rr_gsb, - const bool& compact_routing_hierarchy) { - /* Validate file stream */ - check_file_handler(fp); - - vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - - std::string sb_instance_name = generate_switch_block_module_name(gsb_coordinate); - - /* If we use the compact routing hierarchy, we need to find the module name !*/ - vtr::Point sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - if (true == compact_routing_hierarchy) { - DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - /* Note: use GSB coordinate when inquire for unique modules!!! */ - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); - sb_coordinate.set_x(unique_mirror.get_sb_x()); - sb_coordinate.set_y(unique_mirror.get_sb_y()); - } - - std::string sb_module_name = generate_switch_block_module_name(sb_coordinate); - - ModuleId sb_module = module_manager.find_module(sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); - - /* Print comments */ - fp << "##################################################" << std::endl; - fp << "# Disable timing for Switch block " << sb_module_name << std::endl; - fp << "##################################################" << std::endl; - - /* Build a map between mux_instance name and net_num */ - std::map mux_instance_to_net_map; - - /* Disable all the input/output port (routing tracks), which are not used by benchmark */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - DeviceCoordinator port_coordinate = rr_gsb.get_side_block_coordinator(side_manager.get_side()); - - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - t_rr_node* chan_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack); - - vtr::Point port_coord(port_coordinate.get_x(), port_coordinate.get_y()); - std::string port_name = generate_sb_module_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, - side_manager.get_side(), itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); - - if (true == compact_routing_hierarchy) { - /* Note: use GSB coordinate when inquire for unique modules!!! */ - DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); - DeviceCoordinator unique_port_coordinate = unique_mirror.get_side_block_coordinator(side_manager.get_side()); - port_coord.set_x(unique_port_coordinate.get_x()); - port_coord.set_y(unique_port_coordinate.get_y()); - port_name = generate_sb_module_track_port_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack)->type, - side_manager.get_side(), itrack, - unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack)); - } - - /* Ensure we have this port in the module! */ - ModulePortId module_port = module_manager.find_module_port(sb_module, port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port)); - - /* Cache the net name for routing tracks which are outputs of the switch block */ - if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - /* Generate the name of mux instance related to this output node */ - std::string mux_instance_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MUX_INSTANCE_PREFIX, side_manager.get_side(), itrack, std::string("")); - mux_instance_to_net_map[mux_instance_name] = chan_node->vpack_net_num; - } - - /* Check if this node is used by benchmark */ - if (false == is_rr_node_to_be_disable_for_analysis(chan_node)) { - continue; - } - - fp << "set_disable_timing "; - fp << sb_instance_name << "/"; - fp << generate_sdc_port(module_manager.module_port(sb_module, module_port)); - fp << std::endl; - } - } - - /* Disable all the input port (grid output pins), which are not used by benchmark */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - - for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - t_rr_node* opin_node = rr_gsb.get_opin_node(side_manager.get_side(), inode); - vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); - - std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(), - rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), - opin_node->ptc_num); - - if (true == compact_routing_hierarchy) { - /* Note: use GSB coordinate when inquire for unique modules!!! */ - DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); - port_coord.set_x(unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow); - port_coord.set_y(unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow); - - port_name = generate_sb_module_grid_port_name(side_manager.get_side(), - unique_mirror.get_opin_node_grid_side(side_manager.get_side(), inode), - unique_mirror.get_opin_node(side_manager.get_side(), inode)->ptc_num); - } - - - /* Ensure we have this port in the module! */ - ModulePortId module_port = module_manager.find_module_port(sb_module, port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port)); - - /* Check if this node is used by benchmark */ - if (false == is_rr_node_to_be_disable_for_analysis(opin_node)) { - continue; - } - - fp << "set_disable_timing "; - fp << sb_instance_name << "/"; - fp << generate_sdc_port(module_manager.module_port(sb_module, module_port)); - fp << std::endl; - } - } - - /* Disable all the unused inputs of routing multiplexers, which are not used by benchmark - * Here, we start from each input of the Switch Blocks, and traverse forward to the sink - * port of the module net whose source is the input - * We will find the instance name which is the parent of the sink port, and search the - * net id through the instance_name_to_net_map - * The the net id does not match the net id of this input, we will disable the sink port! - * - * sb_module - * +----------------------- - * | MUX instance A - * | +----------- - * input_port--->|--+---x-->| sink port (disable! net_id = Y) - * (net_id = X) | | +---------- - * | | MUX instance B - * | | +---------- - * | +------>| sink port (do not disable! net_id = X) - * - * Because the input ports of a SB module come from - * 1. Grid output pins - * 2. routing tracks - * We will walk through these ports and do conditionally disable_timing - */ - - /* Iterate over input ports coming from grid output pins */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - - for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - t_rr_node* opin_node = rr_gsb.get_opin_node(side_manager.get_side(), inode); - vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); - - std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(), - rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), - opin_node->ptc_num); - - if (true == compact_routing_hierarchy) { - /* Note: use GSB coordinate when inquire for unique modules!!! */ - DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); - port_coord.set_x(unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow); - port_coord.set_y(unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow); - - port_name = generate_sb_module_grid_port_name(side_manager.get_side(), - unique_mirror.get_opin_node_grid_side(side_manager.get_side(), inode), - unique_mirror.get_opin_node(side_manager.get_side(), inode)->ptc_num); - } - - - /* Ensure we have this port in the module! */ - ModulePortId module_port = module_manager.find_module_port(sb_module, port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port)); - - disable_analysis_module_input_port_net_sinks(fp, module_manager, - sb_module, - sb_instance_name, - module_port, - opin_node, - mux_instance_to_net_map); - } - } - - /* Iterate over input ports coming from routing tracks */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - DeviceCoordinator port_coordinate = rr_gsb.get_side_block_coordinator(side_manager.get_side()); - - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - /* Skip output ports, they have already been disabled or not */ - if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - continue; - } - - t_rr_node* chan_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack); - - vtr::Point port_coord(port_coordinate.get_x(), port_coordinate.get_y()); - std::string port_name = generate_sb_module_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, - side_manager.get_side(), itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); - - if (true == compact_routing_hierarchy) { - /* Note: use GSB coordinate when inquire for unique modules!!! */ - DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); - DeviceCoordinator unique_port_coordinate = unique_mirror.get_side_block_coordinator(side_manager.get_side()); - port_coord.set_x(unique_port_coordinate.get_x()); - port_coord.set_y(unique_port_coordinate.get_y()); - - port_name = generate_sb_module_track_port_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack)->type, - side_manager.get_side(), itrack, - unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack)); - } - - - /* Ensure we have this port in the module! */ - ModulePortId module_port = module_manager.find_module_port(sb_module, port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port)); - - disable_analysis_module_input_port_net_sinks(fp, module_manager, - sb_module, - sb_instance_name, - module_port, - chan_node, - mux_instance_to_net_map); - } - } -} - - -/******************************************************************** - * Iterate over all the connection blocks in a device - * and disable unused ports for each of them - *******************************************************************/ -void print_analysis_sdc_disable_unused_sbs(std::fstream& fp, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const bool& compact_routing_hierarchy) { - - /* Build unique X-direction connection block modules */ - DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); - - for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - /* Check if the connection block exists in the device! - * Some of them do NOT exist due to heterogeneous blocks (height > 1) - * We will skip those modules - */ - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - - print_analysis_sdc_disable_sb_unused_resources(fp, - module_manager, - L_device_rr_gsb, - rr_gsb, - compact_routing_hierarchy); - } - } -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h deleted file mode 100644 index de9e8e54d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_routing_writer.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef ANALYSIS_SDC_ROUTING_WRITER_H -#define ANALYSIS_SDC_ROUTING_WRITER_H - -#include -#include -#include "module_manager.h" -#include "rr_blocks.h" -#include "vpr_types.h" - -void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const bool& compact_routing_hierarchy); - -void print_analysis_sdc_disable_unused_sbs(std::fstream& fp, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const bool& compact_routing_hierarchy); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp deleted file mode 100644 index 289d2b0e9..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.cpp +++ /dev/null @@ -1,271 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to output a SDC file - * that constrain a FPGA fabric (P&Red netlist) using a benchmark - *******************************************************************/ -#include -#include -#include - -#include "vtr_assert.h" -#include "device_port.h" - -#include "util.h" -#include "mux_utils.h" - -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_benchmark_utils.h" - -#include "sdc_writer_naming.h" -#include "sdc_writer_utils.h" -#include "sdc_memory_utils.h" - -#include "analysis_sdc_grid_writer.h" -#include "analysis_sdc_routing_writer.h" -#include "analysis_sdc_writer.h" - -/******************************************************************** - * Generate SDC constaints for inputs and outputs - * We consider the top module in formal verification purpose here - * which is easier - *******************************************************************/ -static -void print_analysis_sdc_io_delays(std::fstream& fp, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const float& critical_path_delay) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Print comments */ - fp << "##################################################" << std::endl; - fp << "# Create clock " << std::endl; - fp << "##################################################" << std::endl; - - /* Get clock port from the global port */ - std::vector operating_clock_ports; - for (const CircuitPortId& clock_port : global_ports) { - if (SPICE_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) { - continue; - } - /* We only constrain operating clock here! */ - if (true == circuit_lib.port_is_prog(clock_port)) { - continue; - } - - /* Find the module port and Update the operating port list */ - ModulePortId module_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(clock_port)); - operating_clock_ports.push_back(module_manager.module_port(top_module, module_port)); - } - - for (const BasicPort& operating_clock_port : operating_clock_ports) { - /* Reach here, it means a clock port and we need print constraints */ - fp << "create_clock "; - fp << generate_sdc_port(operating_clock_port); - fp << " -period " << std::setprecision(10) << critical_path_delay; - fp << " -waveform {0 " << std::setprecision(10) << critical_path_delay / 2 << "}"; - fp << std::endl; - - /* Add an empty line as a splitter */ - fp << std::endl; - } - - /* There should be only one operating clock! - * TODO: this should be changed when developing multi-clock support!!! - */ - VTR_ASSERT(1 == operating_clock_ports.size()); - - /* In this function, we support only 1 type of I/Os */ - VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size()); - BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0]; - - /* Keep tracking which I/Os have been used */ - std::vector io_used(module_io_port.get_width(), false); - - /* Print comments */ - fp << "##################################################" << std::endl; - fp << "# Create input and output delays for used I/Os " << std::endl; - fp << "##################################################" << std::endl; - - for (const t_logical_block& io_lb : L_logical_blocks) { - /* We only care I/O logical blocks !*/ - if ( (VPACK_INPAD != io_lb.type) && (VPACK_OUTPAD != io_lb.type) ) { - continue; - } - - /* clock net or constant generator should be disabled in timing analysis */ - if (TRUE == io_lb.is_clock) { - continue; - } - - /* Find the index of the mapped GPIO in top-level FPGA fabric */ - size_t io_index = find_benchmark_io_index(io_lb, device_size, L_grids, L_blocks); - - /* Ensure that IO index is in range */ - BasicPort module_mapped_io_port = module_io_port; - /* Set the port pin index */ - VTR_ASSERT(io_index < module_mapped_io_port.get_width()); - module_mapped_io_port.set_width(io_index, io_index); - - /* For input I/O, we set an input delay constraint correlated to the operating clock - * For output I/O, we set an output delay constraint correlated to the operating clock - */ - if (VPACK_INPAD == io_lb.type) { - print_sdc_set_port_input_delay(fp, module_mapped_io_port, - operating_clock_ports[0], critical_path_delay); - } else { - VTR_ASSERT(VPACK_OUTPAD == io_lb.type); - print_sdc_set_port_output_delay(fp, module_mapped_io_port, - operating_clock_ports[0], critical_path_delay); - } - - /* Mark this I/O has been used/wired */ - io_used[io_index] = true; - } - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Print comments */ - fp << "##################################################" << std::endl; - fp << "# Disable timing for unused I/Os " << std::endl; - fp << "##################################################" << std::endl; - - /* Wire the unused iopads to a constant */ - for (size_t io_index = 0; io_index < io_used.size(); ++io_index) { - /* Bypass used iopads */ - if (true == io_used[io_index]) { - continue; - } - - /* Wire to a contant */ - BasicPort module_unused_io_port = module_io_port; - /* Set the port pin index */ - module_unused_io_port.set_width(io_index, io_index); - print_sdc_disable_port_timing(fp, module_unused_io_port); - } - - /* Add an empty line as a splitter */ - fp << std::endl; -} - -/******************************************************************** - * Disable the timing for all the global port except the operating clock ports - *******************************************************************/ -static -void print_analysis_sdc_disable_global_ports(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports) { - /* Validate file stream */ - check_file_handler(fp); - - /* Print comments */ - fp << "##################################################" << std::endl; - fp << "# Disable timing for global ports " << std::endl; - fp << "##################################################" << std::endl; - - for (const CircuitPortId& global_port : global_ports) { - /* Skip operating clock here! */ - if ( (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) - && (false == circuit_lib.port_is_prog(global_port)) ) { - continue; - } - - ModulePortId module_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(global_port)); - BasicPort port_to_disable = module_manager.module_port(top_module, module_port); - - print_sdc_disable_port_timing(fp, port_to_disable); - } -} - -/******************************************************************** - * Top-level function outputs a SDC file - * that constrain a FPGA fabric (P&Red netlist) using a benchmark - *******************************************************************/ -void print_analysis_sdc(const std::string& sdc_dir, - const float& critical_path_delay, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const bool& compact_routing_hierarchy) { - /* Create the file name for Verilog netlist */ - std::string sdc_fname(sdc_dir + std::string(SDC_ANALYSIS_FILE_NAME)); - - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for Timing/Power analysis on the mapped FPGA: %s ...", - sdc_fname.c_str()); - - /* Start time count */ - clock_t t_start = clock(); - - /* Create the file stream */ - std::fstream fp; - fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); - - /* Validate file stream */ - check_file_handler(fp); - - /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("Constrain for Timing/Power analysis on the mapped FPGA")); - - /* Find the top_module */ - ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name()); - VTR_ASSERT(true == module_manager.valid_module_id(top_module)); - - /* Create clock and set I/O ports with input/output delays */ - print_analysis_sdc_io_delays(fp, - L_logical_blocks, device_size, L_grids, L_blocks, - module_manager, top_module, - circuit_lib, global_ports, - critical_path_delay); - - /* Disable the timing for global ports */ - print_analysis_sdc_disable_global_ports(fp, - module_manager, top_module, - circuit_lib, global_ports); - - /* Disable the timing for configuration cells */ - rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, - module_manager, top_module, - format_dir_path(module_manager.module_name(top_module))); - - - /* Disable timing for unused routing resources in connection blocks */ - print_analysis_sdc_disable_unused_cbs(fp, - module_manager, - L_device_rr_gsb, - compact_routing_hierarchy); - - /* Disable timing for unused routing resources in switch blocks */ - print_analysis_sdc_disable_unused_sbs(fp, - module_manager, - L_device_rr_gsb, - compact_routing_hierarchy); - - /* Disable timing for unused routing resources in grids (programmable blocks) */ - print_analysis_sdc_disable_unused_grids(fp, device_size, L_grids, L_blocks, module_manager); - - /* Close file handler */ - fp.close(); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h deleted file mode 100644 index 252c76c71..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef ANALYSIS_SDC_WRITER_H -#define ANALYSIS_SDC_WRITER_H - -#include -#include "vpr_types.h" -#include "rr_blocks.h" -#include "module_manager.h" -#include "bitstream_manager.h" - -void print_analysis_sdc(const std::string& sdc_dir, - const float& critical_path_delay, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const bool& compact_routing_hierarchy); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.cpp deleted file mode 100644 index 3c2885fd3..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.cpp +++ /dev/null @@ -1,235 +0,0 @@ -/******************************************************************** - * This file includes most utilized functions - * that are used to output a SDC file - * in order to constrain a FPGA fabric (P&Red netlist) mapped to a benchmark - *******************************************************************/ -#include "vtr_assert.h" - -#include "fpga_x2p_utils.h" - -#include "sdc_writer_utils.h" -#include "analysis_sdc_writer_utils.h" - -#include "globals.h" - -/******************************************************************** - * Identify if a node should be disabled during analysis SDC generation - *******************************************************************/ -bool is_rr_node_to_be_disable_for_analysis(t_rr_node* cur_rr_node) { - /* Conditions to enable timing analysis for a node - * 1st condition: it have a valid vpack_net_number - * 2nd condition: it is not an parasitic net - * 3rd condition: it is not a global net - */ - if ( (OPEN != cur_rr_node->vpack_net_num) - && (FALSE == cur_rr_node->is_parasitic_net) - && (FALSE == vpack_net[cur_rr_node->vpack_net_num].is_global) - && (FALSE == vpack_net[cur_rr_node->vpack_net_num].is_const_gen) ){ - return false; - } - return true; -} - -/******************************************************************** - * Disable all the unused inputs of routing multiplexers, which are not used by benchmark - * Here, we start from each input of a routing module, and traverse forward to the sink - * port of the module net whose source is the input - * We will find the instance name which is the parent of the sink port, and search the - * net id through the instance_name_to_net_map - * The the net id does not match the net id of this input, we will disable the sink port! - * - * parent_module - * +----------------------- - * | MUX instance A - * | +----------- - * input_port--->|--+---x-->| sink port (disable! net_id = Y) - * (net_id = X) | | +---------- - * | | MUX instance B - * | | +---------- - * | +------>| sink port (do not disable! net_id = X) - * - *******************************************************************/ -void disable_analysis_module_input_pin_net_sinks(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& parent_instance_name, - const ModulePortId& module_input_port, - const size_t& module_input_pin, - t_rr_node* input_rr_node, - const std::map mux_instance_to_net_map) { - /* Validate file stream */ - check_file_handler(fp); - - /* Find the module net which sources from this port! */ - ModuleNetId module_net = module_manager.module_instance_port_net(parent_module, parent_module, 0, module_input_port, module_input_pin); - VTR_ASSERT(true == module_manager.valid_module_net_id(parent_module, module_net)); - - /* Touch each sink of the net! */ - for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(parent_module, module_net)) { - ModuleId sink_module = module_manager.net_sink_modules(parent_module, module_net)[sink_id]; - size_t sink_instance = module_manager.net_sink_instances(parent_module, module_net)[sink_id]; - - /* Skip when sink module is the parent module, - * the output ports of parent modules have been disabled/enabled already! - */ - if (sink_module == parent_module) { - continue; - } - - std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance); - bool disable_timing = false; - /* Check if this node is used by benchmark */ - if (true == is_rr_node_to_be_disable_for_analysis(input_rr_node)) { - /* Disable all the sinks! */ - disable_timing = true; - } else { - std::map::const_iterator it = mux_instance_to_net_map.find(sink_instance_name); - if (it != mux_instance_to_net_map.end()) { - /* See if the net id matches. If does not match, we should disable! */ - if (input_rr_node->vpack_net_num != mux_instance_to_net_map.at(sink_instance_name)) { - disable_timing = true; - } - } - } - - /* Time to write SDC command to disable timing or not */ - if (false == disable_timing) { - continue; - } - - BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]); - sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id], - module_manager.net_sink_pins(parent_module, module_net)[sink_id]); - /* Get the input id that is used! Disable the unused inputs! */ - fp << "set_disable_timing "; - fp << parent_instance_name << "/"; - fp << sink_instance_name << "/"; - fp << generate_sdc_port(sink_port); - fp << std::endl; - } -} - - -/******************************************************************** - * Disable all the unused inputs of routing multiplexers, which are not used by benchmark - * Here, we start from each input of a routing module, and traverse forward to the sink - * port of the module net whose source is the input - * We will find the instance name which is the parent of the sink port, and search the - * net id through the instance_name_to_net_map - * The the net id does not match the net id of this input, we will disable the sink port! - * - * parent_module - * +----------------------- - * | MUX instance A - * | +----------- - * input_port--->|--+---x-->| sink port (disable! net_id = Y) - * (net_id = X) | | +---------- - * | | MUX instance B - * | | +---------- - * | +------>| sink port (do not disable! net_id = X) - * - *******************************************************************/ -void disable_analysis_module_input_port_net_sinks(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& parent_instance_name, - const ModulePortId& module_input_port, - t_rr_node* input_rr_node, - const std::map mux_instance_to_net_map) { - /* Validate file stream */ - check_file_handler(fp); - - /* Find the module net which sources from this port! */ - for (const size_t& pin : module_manager.module_port(parent_module, module_input_port).pins()) { - disable_analysis_module_input_pin_net_sinks(fp, module_manager, parent_module, - parent_instance_name, - module_input_port, pin, - input_rr_node, - mux_instance_to_net_map); - } -} - -/******************************************************************** - * Disable all the unused inputs of routing multiplexers, which are not used by benchmark - * Here, we start from each output of a child module, and traverse forward to the sink - * port of the module net whose source is the input - * We will find the instance name which is the parent of the sink port, and search the - * net id through the instance_name_to_net_map - * The the net id does not match the net id of this input, we will disable the sink port! - * - * Parent_module - * +--------------------------------------------- - * | - * | +--------------------------------------------+ - * | | MUX child_module | - * | | +-------------+ +-----------+ | - * | +--->| Routing |------>| | | - * input_pin0(netA) --->|----x--->| Multiplexer | netA | output_pin|-----+ - * | +-------------+ | | netA - * | | | - * - - * - *******************************************************************/ -void disable_analysis_module_output_pin_net_sinks(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& parent_instance_name, - const ModuleId& child_module, - const size_t& child_instance, - const ModulePortId& child_module_port, - const size_t& child_module_pin, - t_rr_node* output_rr_node, - const std::map mux_instance_to_net_map) { - /* Validate file stream */ - check_file_handler(fp); - - /* Find the module net which sources from this port! */ - ModuleNetId module_net = module_manager.module_instance_port_net(parent_module, child_module, child_instance, child_module_port, child_module_pin); - VTR_ASSERT(true == module_manager.valid_module_net_id(parent_module, module_net)); - - /* Touch each sink of the net! */ - for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(parent_module, module_net)) { - ModuleId sink_module = module_manager.net_sink_modules(parent_module, module_net)[sink_id]; - size_t sink_instance = module_manager.net_sink_instances(parent_module, module_net)[sink_id]; - - /* Skip when sink module is the parent module, - * the output ports of parent modules have been disabled/enabled already! - */ - if (sink_module == parent_module) { - continue; - } - - std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance); - bool disable_timing = false; - /* Check if this node is used by benchmark */ - if (true == is_rr_node_to_be_disable_for_analysis(output_rr_node)) { - /* Disable all the sinks! */ - disable_timing = true; - } else { - std::map::const_iterator it = mux_instance_to_net_map.find(sink_instance_name); - if (it != mux_instance_to_net_map.end()) { - /* See if the net id matches. If does not match, we should disable! */ - if (output_rr_node->vpack_net_num != mux_instance_to_net_map.at(sink_instance_name)) { - disable_timing = true; - } - } - } - - /* Time to write SDC command to disable timing or not */ - if (false == disable_timing) { - continue; - } - - BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]); - sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id], - module_manager.net_sink_pins(parent_module, module_net)[sink_id]); - /* Get the input id that is used! Disable the unused inputs! */ - fp << "set_disable_timing "; - fp << parent_instance_name << "/"; - fp << sink_instance_name << "/"; - fp << generate_sdc_port(sink_port); - fp << std::endl; - } -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.h deleted file mode 100644 index 7b5ff9348..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/analysis_sdc_writer_utils.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef ANALYSIS_SDC_WRITER_UTILS_H -#define ANALYSIS_SDC_WRITER_UTILS_H - -#include -#include -#include -#include "module_manager.h" -#include "vpr_types.h" - -bool is_rr_node_to_be_disable_for_analysis(t_rr_node* cur_rr_node); - -void disable_analysis_module_input_pin_net_sinks(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& parent_instance_name, - const ModulePortId& module_input_port, - const size_t& module_input_pin, - t_rr_node* input_rr_node, - const std::map mux_instance_to_net_map); - -void disable_analysis_module_input_port_net_sinks(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& parent_instance_name, - const ModulePortId& module_input_port, - t_rr_node* input_rr_node, - const std::map mux_instance_to_net_map) ; - -void disable_analysis_module_output_pin_net_sinks(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& parent_instance_name, - const ModuleId& child_module, - const size_t& child_instance, - const ModulePortId& child_module_port, - const size_t& child_module_pin, - t_rr_node* output_rr_node, - const std::map mux_instance_to_net_map); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.cpp deleted file mode 100644 index 8032daca4..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.cpp +++ /dev/null @@ -1,361 +0,0 @@ -/******************************************************************** - * This file includes functions that print SDC (Synopsys Design Constraint) - * files in physical design tools, i.e., Place & Route (PnR) tools - * The SDC files are used to constrain the physical design for each grid - * (CLBs, heterogeneous blocks etc.) - * - * Note that this is different from the SDC to constrain VPR Place&Route - * engine! These SDCs are designed for PnR to generate FPGA layouts!!! - *******************************************************************/ -#include -#include - -#include "vtr_assert.h" -#include "device_port.h" - -#include "util.h" -#include "mux_utils.h" - -#include "fpga_x2p_reserved_words.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" - -#include "sdc_writer_naming.h" -#include "sdc_writer_utils.h" -#include "pnr_sdc_grid_writer.h" - -#include "globals.h" - -/******************************************************************** - * Print pin-to-pin timing constraints for a given interconnection - * at an output port of a pb_graph node - *******************************************************************/ -static -void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const e_side& border_side, - t_pb_graph_pin* des_pb_graph_pin, - t_mode* physical_mode) { - - /* Validate file stream */ - check_file_handler(fp); - - /* 1. identify pin interconnection type, - * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) - * 3. Print SDC timing constraints - */ - int fan_in = 0; - t_interconnect* cur_interc = NULL; - find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, physical_mode, &cur_interc, &fan_in); - if ((NULL == cur_interc) || (0 == fan_in)) { - /* No interconnection matched */ - return; - } - - /* Print pin-to-pin SDC contraint here */ - /* For more than one mode defined, the direct interc has more than one input_edge , - * We need to find which edge is connected the pin we want - */ - for (int iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - if (cur_interc != des_pb_graph_pin->input_edges[iedge]->interconnect) { - continue; - } - - /* Source pin, node, pb_type*/ - t_pb_graph_pin* src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; - t_pb_graph_node* src_pb_graph_node = src_pb_graph_pin->parent_node; - /* Des pin, node, pb_type */ - t_pb_graph_node* des_pb_graph_node = des_pb_graph_pin->parent_node; - - /* Find the src module in module manager */ - std::string src_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); - std::string src_module_name = generate_physical_block_module_name(src_module_name_prefix, src_pb_graph_pin->parent_node->pb_type); - ModuleId src_module = module_manager.find_module(src_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(src_module)); - - ModulePortId src_module_port_id = module_manager.find_module_port(src_module, generate_pb_type_port_name(src_pb_graph_pin->port)); - VTR_ASSERT(true == module_manager.valid_module_port_id(src_module, src_module_port_id)); - - /* Generate the name of the des instance name - * If des module is not the parent module, it is a child module. - * We should find the instance id - */ - std::string src_instance_name = src_module_name; - if (parent_module != src_module) { - src_instance_name = module_manager.module_name(parent_module) + std::string("/"); - /* Instance id is actually the placement index */ - size_t instance_id = src_pb_graph_node->placement_index; - if (true == module_manager.instance_name(parent_module, src_module, instance_id).empty()) { - src_instance_name += src_module_name; - src_instance_name += "_"; - src_instance_name += std::to_string(instance_id); - src_instance_name += "_"; - } else { - src_instance_name += module_manager.instance_name(parent_module, src_module, instance_id); - } - } - - /* Generate src port information */ - BasicPort src_port = module_manager.module_port(src_module, src_module_port_id); - src_port.set_width(src_pb_graph_pin->pin_number, src_pb_graph_pin->pin_number); - - /* Find the des module in module manager */ - std::string des_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); - std::string des_module_name = generate_physical_block_module_name(des_module_name_prefix, des_pb_graph_pin->parent_node->pb_type); - ModuleId des_module = module_manager.find_module(des_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(des_module)); - ModulePortId des_module_port_id = module_manager.find_module_port(des_module, generate_pb_type_port_name(des_pb_graph_pin->port)); - VTR_ASSERT(true == module_manager.valid_module_port_id(des_module, des_module_port_id)); - - /* Generate the name of the des instance name - * If des module is not the parent module, it is a child module. - * We should find the instance id - */ - std::string des_instance_name = des_module_name; - if (parent_module != des_module) { - des_instance_name = module_manager.module_name(parent_module) + std::string("/"); - /* Instance id is actually the placement index */ - size_t instance_id = des_pb_graph_node->placement_index; - if (true == module_manager.instance_name(parent_module, des_module, instance_id).empty()) { - des_instance_name += des_module_name; - des_instance_name += "_"; - des_instance_name += std::to_string(instance_id); - des_instance_name += "_"; - } else { - des_instance_name += module_manager.instance_name(parent_module, des_module, instance_id); - } - } - - /* Generate des port information */ - BasicPort des_port = module_manager.module_port(des_module, des_module_port_id); - des_port.set_width(des_pb_graph_pin->pin_number, des_pb_graph_pin->pin_number); - - /* Print a SDC timing constraint */ - print_pnr_sdc_constrain_max_delay(fp, - src_instance_name, - generate_sdc_port(src_port), - des_instance_name, - generate_sdc_port(des_port), - des_pb_graph_pin->input_edges[iedge]->delay_max); - } -} - -/******************************************************************** - * Print port-to-port timing constraints which source from - * an output port of a pb_graph node - *******************************************************************/ -static -void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const e_side& border_side, - t_pb_graph_node* des_pb_graph_node, - const e_spice_pb_port_type& pb_port_type, - t_mode* physical_mode) { - /* Validate file stream */ - check_file_handler(fp); - - switch (pb_port_type) { - case SPICE_PB_PORT_INPUT: { - for (int iport = 0; iport < des_pb_graph_node->num_input_ports; ++iport) { - for (int ipin = 0; ipin < des_pb_graph_node->num_input_pins[iport]; ++ipin) { - /* If this is a idle block, we set 0 to the selected edge*/ - /* Get the selected edge of current pin*/ - print_pnr_sdc_constrain_pb_pin_interc_timing(fp, module_manager, parent_module, border_side, - &(des_pb_graph_node->input_pins[iport][ipin]), - physical_mode); - } - } - break; - } - case SPICE_PB_PORT_OUTPUT: { - for (int iport = 0; iport < des_pb_graph_node->num_output_ports; ++iport) { - for (int ipin = 0; ipin < des_pb_graph_node->num_output_pins[iport]; ++ipin) { - print_pnr_sdc_constrain_pb_pin_interc_timing(fp, module_manager, parent_module, border_side, - &(des_pb_graph_node->output_pins[iport][ipin]), - physical_mode); - } - } - break; - } - case SPICE_PB_PORT_CLOCK: { - /* Do NOT constrain clock here, it should be handled by Clock Tree Synthesis */ - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid pb port type!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * This function will generate a SDC file for each pb_type, - * constraining the pin-to-pin timing between - * 1. input port of parent_pb_graph_node and input port of child_pb_graph_nodes - * 2. output port of parent_pb_graph_node and output port of child_pb_graph_nodes - * 3. output port of child_pb_graph_node and input port of child_pb_graph_nodes - *******************************************************************/ -static -void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - t_pb_graph_node* parent_pb_graph_node, - const int& physical_mode_index, - const e_side& border_side) { - - /* Get the pb_type definition related to the node */ - t_pb_type* physical_pb_type = parent_pb_graph_node->pb_type; - std::string pb_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); - std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, physical_pb_type); - - /* Find the pb module in module manager */ - ModuleId pb_module = module_manager.find_module(pb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); - - /* Create the file name for SDC */ - std::string sdc_fname(sdc_dir + pb_module_name + std::string(SDC_FILE_NAME_POSTFIX)); - - /* Create the file stream */ - std::fstream fp; - fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("Timing constraints for Grid " + pb_module_name + " in PnR")); - - t_mode* physical_mode = &(parent_pb_graph_node->pb_type->modes[physical_mode_index]); - - /* We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins - * /|\ - * | - * input_pins, edges, output_pins - */ - print_pnr_sdc_constrain_pb_interc_timing(fp, module_manager, pb_module, border_side, - parent_pb_graph_node, - SPICE_PB_PORT_OUTPUT, - physical_mode); - - /* We check input_pins of child_pb_graph_node and its the input_edges - * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node - * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins - * /|\ - * | - * input_pins, edges, output_pins - */ - for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) { - for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; ++jpb) { - t_pb_graph_node* child_pb_graph_node = &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][jpb]); - /* For each child_pb_graph_node input pins*/ - print_pnr_sdc_constrain_pb_interc_timing(fp, module_manager, pb_module, border_side, - child_pb_graph_node, - SPICE_PB_PORT_INPUT, - physical_mode); - /* Do NOT constrain clock here, it should be handled by Clock Tree Synthesis */ - } - } - - /* Close file handler */ - fp.close(); -} - -/******************************************************************** - * Recursively print SDC timing constraints for a pb_type - * This function will generate a SDC file for each pb_type, - * constraining the pin-to-pin timing - *******************************************************************/ -static -void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - t_pb_graph_node* parent_pb_graph_node, - const e_side& border_side) { - /* Validate pb_graph node */ - if (NULL == parent_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid parent_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Get the pb_type */ - t_pb_type* parent_pb_type = parent_pb_graph_node->pb_type; - - /* No need to constrain the primitive node */ - if (TRUE == is_primitive_pb_type(parent_pb_type)) { - return; - } - - /* Note we only go through the graph through the physical modes. - * which we build the modules - */ - int physical_mode_index = find_pb_type_physical_mode_index((*parent_pb_type)); - - /* Write a SDC file for this pb_type */ - print_pnr_sdc_constrain_pb_graph_node_timing(sdc_dir, module_manager, - parent_pb_graph_node, physical_mode_index, - border_side); - - /* Go recursively to the lower level in the pb_graph - * Note that we assume a full hierarchical P&R, we will only visit pb_graph_node of unique pb_type - */ - for (int ipb = 0; ipb < parent_pb_type->modes[physical_mode_index].num_pb_type_children; ++ipb) { - rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, - &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][0]), - border_side); - } -} - -/******************************************************************** - * Top-level function to print timing constraints for pb_types - *******************************************************************/ -void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir, - const ModuleManager& module_manager) { - - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for constraining grid timing for P&R flow..."); - - /* Start time count */ - clock_t t_start = clock(); - - for (int itype = 0; itype < num_types; itype++) { - /* Bypass EMPTY types */ - if (EMPTY_TYPE == &type_descriptors[itype]) { - continue; - } - - /* For IO_TYPE, we have four types of I/Os */ - if (IO_TYPE == &type_descriptors[itype]) { - /* Special for I/O block, generate one module for each border side */ - for (int iside = 0; iside < NUM_SIDES; iside++) { - Side side_manager(iside); - rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, - type_descriptors[itype].pb_graph_head, - side_manager.get_side()); - } - } else if (FILL_TYPE == &type_descriptors[itype]) { - /* For CLB */ - rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, - type_descriptors[itype].pb_graph_head, - NUM_SIDES); - } else { - /* For heterogenenous blocks */ - rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, module_manager, - type_descriptors[itype].pb_graph_head, - NUM_SIDES); - } - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.h deleted file mode 100644 index d27b292ef..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_grid_writer.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef PNR_SDC_GRID_WRITER_H -#define PNR_SDC_GRID_WRITER_H - -#include -#include -#include "vpr_types.h" - -void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir, - const ModuleManager& module_manager); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp deleted file mode 100644 index 6e1a1f89d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp +++ /dev/null @@ -1,440 +0,0 @@ -/******************************************************************** - * This file includes functions that print SDC (Synopsys Design Constraint) - * files in physical design tools, i.e., Place & Route (PnR) tools - * The SDC files are used to constrain the physical design for each routing modules - * in FPGA fabric, such as Switch Blocks (SBs) and Connection Blocks (CBs) - * - * Note that this is different from the SDC to constrain VPR Place&Route - * engine! These SDCs are designed for PnR to generate FPGA layouts!!! - *******************************************************************/ -#include -#include - -#include "vtr_assert.h" -#include "device_port.h" - -#include "util.h" -#include "mux_utils.h" - -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -#include "build_routing_module_utils.h" - -#include "sdc_writer_naming.h" -#include "sdc_writer_utils.h" -#include "pnr_sdc_routing_writer.h" - -/******************************************************************** - * Find the timing constraints between the inputs and outputs of a routing - * multiplexer in a Switch Block - *******************************************************************/ -static -float find_pnr_sdc_switch_tmax(const t_switch_inf& switch_inf) { - return switch_inf.R * switch_inf.Cout + switch_inf.Tdel; -} - -/******************************************************************** - * Set timing constraints between the inputs and outputs of a routing - * multiplexer in a Switch Block - *******************************************************************/ -static -void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const std::vector& switches, - const e_side& output_node_side, - t_rr_node* output_rr_node) { - /* Validate file stream */ - check_file_handler(fp); - - VTR_ASSERT( ( CHANX == output_rr_node->type ) - || ( CHANY == output_rr_node->type )); - - /* Find the module port corresponding to the output rr_node */ - ModulePortId module_output_port = find_switch_block_module_chan_port(module_manager, - sb_module, - rr_gsb, - output_node_side, - output_rr_node, - OUT_PORT); - - /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */ - std::vector input_rr_nodes; - for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { - input_rr_nodes.push_back(output_rr_node->drive_rr_nodes[iedge]); - } - - std::vector module_input_ports = find_switch_block_module_input_ports(module_manager, - sb_module, - rr_gsb, - input_rr_nodes); - - /* Find timing constraints for each path (edge) */ - std::map switch_delays; - for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { - /* Get the switch delay */ - int switch_id = output_rr_node->drive_switches[iedge]; - switch_delays[module_input_ports[iedge]] = find_pnr_sdc_switch_tmax(switches[switch_id]); - } - - /* Find the starting points */ - for (const ModulePortId& module_input_port : module_input_ports) { - /* Constrain a path */ - print_pnr_sdc_constrain_port2port_timing(fp, - module_manager, - sb_module, module_input_port, - sb_module, module_output_port, - switch_delays[module_input_port]); - } -} - -/******************************************************************** - * Set timing constraints between the inputs and outputs of SBs, - * which are connected by routing multiplexers with the given delays - * specified in architectural XML file - * - * To enable block by block timing constraining, we generate the SDC - * file for each unique SB module - *******************************************************************/ -static -void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const std::vector& switches, - const RRGSB& rr_gsb) { - - /* Create the file name for Verilog netlist */ - vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - std::string sdc_fname(sdc_dir + generate_switch_block_module_name(gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX)); - - /* Create the file stream */ - std::fstream fp; - fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); - - /* Validate file stream */ - check_file_handler(fp); - - std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate); - ModuleId sb_module = module_manager.find_module(sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); - - /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("Constrain timing of Switch Block " + sb_module_name + " for PnR")); - - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - t_rr_node* chan_rr_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack); - /* We only care the output port and it should indicate a SB mux */ - if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - continue; - } - /* Constrain thru wires */ - if (false != rr_gsb.is_sb_node_passing_wire(side_manager.get_side(), itrack)) { - continue; - } - /* This is a MUX, constrain all the paths from an input to an output */ - print_pnr_sdc_constrain_sb_mux_timing(fp, - module_manager, sb_module, - rr_gsb, - switches, - side_manager.get_side(), - chan_rr_node); - } - } - - /* Close file handler */ - fp.close(); -} - -/******************************************************************** - * Print SDC timing constraints for Switch blocks - * This function is designed for flatten routing hierarchy - *******************************************************************/ -void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const std::vector& switches, - const DeviceRRGSB& L_device_rr_gsb) { - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for constrain Switch Block timing for P&R flow..."); - - /* Start time count */ - clock_t t_start = clock(); - - /* Get the range of SB array */ - DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); - /* Go for each SB */ - for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - print_pnr_sdc_constrain_sb_timing(sdc_dir, - module_manager, - switches, - rr_gsb); - } - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - -/******************************************************************** - * Print SDC timing constraints for Switch blocks - * This function is designed for compact routing hierarchy - *******************************************************************/ -void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const std::vector& switches, - const DeviceRRGSB& L_device_rr_gsb) { - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for constrain Switch Block timing for P&R flow..."); - - /* Start time count */ - clock_t t_start = clock(); - - for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) { - const RRGSB& rr_gsb = L_device_rr_gsb.get_sb_unique_module(isb); - print_pnr_sdc_constrain_sb_timing(sdc_dir, - module_manager, - switches, - rr_gsb); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - -/******************************************************************** - * Set timing constraints between the inputs and outputs of a routing - * multiplexer in a Connection Block - *******************************************************************/ -static -void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const std::vector& switches, - t_rr_node* output_rr_node) { - /* Validate file stream */ - check_file_handler(fp); - - VTR_ASSERT(IPIN == output_rr_node->type); - - /* We have OPINs since we may have direct connections: - * These connections should be handled by other functions in the compact_netlist.c - * So we just return here for OPINs - */ - if ( (1 == output_rr_node->num_drive_rr_nodes) - && (OPIN == output_rr_node->drive_rr_nodes[0]->type) ) { - return; - } - - /* Find the module port corresponding to the output rr_node */ - ModulePortId module_output_port = find_connection_block_module_ipin_port(module_manager, - cb_module, - rr_gsb, - output_rr_node); - - /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */ - std::vector input_rr_nodes; - for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { - /* Skip OPINs which should be handled in direct connection */ - input_rr_nodes.push_back(output_rr_node->drive_rr_nodes[iedge]); - } - - std::vector module_input_ports = find_connection_block_module_input_ports(module_manager, - cb_module, - rr_gsb, - cb_type, - input_rr_nodes); - - /* Find timing constraints for each path (edge) */ - std::map switch_delays; - for (int iedge = 0; iedge < output_rr_node->num_drive_rr_nodes; iedge++) { - /* Get the switch delay */ - int switch_id = output_rr_node->drive_switches[iedge]; - switch_delays[module_input_ports[iedge]] = find_pnr_sdc_switch_tmax(switches[switch_id]); - } - - /* Find the starting points */ - for (const ModulePortId& module_input_port : module_input_ports) { - /* Constrain a path */ - print_pnr_sdc_constrain_port2port_timing(fp, - module_manager, - cb_module, module_input_port, - cb_module, module_output_port, - switch_delays[module_input_port]); - } -} - - -/******************************************************************** - * Print SDC timing constraints for a Connection block - * This function is designed for compact routing hierarchy - *******************************************************************/ -static -void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const std::vector& switches) { - /* Create the netlist */ - vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - - /* Find the module name and create a SDC file for it */ - std::string sdc_fname(sdc_dir + generate_connection_block_module_name(cb_type, gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX)); - - /* Create the file stream */ - std::fstream fp; - fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); - - /* Validate file stream */ - check_file_handler(fp); - - std::string cb_module_name = generate_connection_block_module_name(cb_type, gsb_coordinate); - ModuleId cb_module = module_manager.find_module(cb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); - - /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("Constrain timing of Connection Block " + cb_module_name + " for PnR")); - - std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); - - for (size_t side = 0; side < cb_sides.size(); ++side) { - enum e_side cb_ipin_side = cb_sides[side]; - Side side_manager(cb_ipin_side); - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - t_rr_node* ipin_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); - print_pnr_sdc_constrain_cb_mux_timing(fp, - module_manager, cb_module, - rr_gsb, cb_type, - switches, - ipin_rr_node); - } - } - - /* Close file handler */ - fp.close(); -} - -/******************************************************************** - * Iterate over all the connection blocks in a device - * and print SDC file for each of them - *******************************************************************/ -static -void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector& switches, - const t_rr_type& cb_type) { - /* Build unique X-direction connection block modules */ - DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); - - for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { - /* Check if the connection block exists in the device! - * Some of them do NOT exist due to heterogeneous blocks (height > 1) - * We will skip those modules - */ - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - if (false == rr_gsb.is_cb_exist(cb_type)) { - continue; - } - print_pnr_sdc_constrain_cb_timing(sdc_dir, - module_manager, - rr_gsb, - cb_type, - switches); - - } - } -} - -/******************************************************************** - * Iterate over all the connection blocks in a device - * and print SDC file for each of them - *******************************************************************/ -void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector& switches) { - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for constrain Connection Block timing for P&R flow..."); - - /* Start time count */ - clock_t t_start = clock(); - - print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, - L_device_rr_gsb, - switches, - CHANX); - - print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, module_manager, - L_device_rr_gsb, - switches, - CHANY); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - -/******************************************************************** - * Print SDC timing constraints for Connection blocks - * This function is designed for compact routing hierarchy - *******************************************************************/ -void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const std::vector& switches, - const DeviceRRGSB& L_device_rr_gsb) { - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for constrain Connection Block timing for P&R flow..."); - - /* Start time count */ - clock_t t_start = clock(); - - /* Print SDC for unique X-direction connection block modules */ - for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANX, icb); - print_pnr_sdc_constrain_cb_timing(sdc_dir, - module_manager, - unique_mirror, - CHANX, - switches); - } - - /* Print SDC for unique Y-direction connection block modules */ - for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANY, icb); - print_pnr_sdc_constrain_cb_timing(sdc_dir, - module_manager, - unique_mirror, - CHANY, - switches); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.h deleted file mode 100644 index 72fdfc3b0..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef PNR_SDC_ROUTING_WRITER_H -#define PNR_SDC_ROUTING_WRITER_H - -#include -#include -#include "module_manager.h" -#include "rr_blocks.h" -#include "vpr_types.h" - -void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const std::vector& switches, - const DeviceRRGSB& L_device_rr_gsb); - -void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const std::vector& switches, - const DeviceRRGSB& L_device_rr_gsb); - -void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector& switches); - -void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir, - const ModuleManager& module_manager, - const std::vector& switches, - const DeviceRRGSB& L_device_rr_gsb); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp deleted file mode 100644 index a333f95ff..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.cpp +++ /dev/null @@ -1,473 +0,0 @@ -/******************************************************************** - * This file includes functions that print SDC (Synopsys Design Constraint) - * files in physical design tools, i.e., Place & Route (PnR) tools - * The SDC files are used to constrain the physical design for each module - * in FPGA fabric, such as Configurable Logic Blocks (CLBs), - * Heterogeneous blocks, Switch Blocks (SBs) and Connection Blocks (CBs) - * - * Note that this is different from the SDC to constrain VPR Place&Route - * engine! These SDCs are designed for PnR to generate FPGA layouts!!! - *******************************************************************/ -#include -#include -#include - -#include "vtr_assert.h" -#include "device_port.h" - -#include "util.h" -#include "mux_utils.h" - -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -#include "sdc_writer_naming.h" -#include "sdc_writer_utils.h" -#include "sdc_memory_utils.h" -#include "pnr_sdc_routing_writer.h" -#include "pnr_sdc_grid_writer.h" -#include "pnr_sdc_writer.h" - -/******************************************************************** - * Local variables - *******************************************************************/ -constexpr float SDC_FIXED_PROG_CLOCK_PERIOD = 100; -constexpr float SDC_FIXED_CLOCK_PERIOD = 10; - -/******************************************************************** - * Print a SDC file to constrain the global ports of FPGA fabric - * in particular clock ports - * - * For programming clock, we give a fixed period, while for operating - * clock, we constrain with critical path delay - *******************************************************************/ -static -void print_pnr_sdc_global_ports(const std::string& sdc_dir, - const float& critical_path_delay, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const bool& constrain_non_clock_ports) { - - /* Create the file name for Verilog netlist */ - std::string sdc_fname(sdc_dir + std::string(SDC_GLOBAL_PORTS_FILE_NAME)); - - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for constraining clocks for P&R flow: %s ...", - sdc_fname.c_str()); - - /* Start time count */ - clock_t t_start = clock(); - - /* Create the file stream */ - std::fstream fp; - fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("Clock contraints for PnR")); - - /* Get clock port from the global port */ - for (const CircuitPortId& clock_port : global_ports) { - if (SPICE_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) { - continue; - } - /* Reach here, it means a clock port and we need print constraints */ - float clock_period = critical_path_delay; - - /* For programming clock, we give a fixed period */ - if (true == circuit_lib.port_is_prog(clock_port)) { - clock_period = SDC_FIXED_PROG_CLOCK_PERIOD; - /* Print comments */ - fp << "##################################################" << std::endl; - fp << "# Create programmable clock " << std::endl; - fp << "##################################################" << std::endl; - } else { - /* Print comments */ - fp << "##################################################" << std::endl; - fp << "# Create clock " << std::endl; - fp << "##################################################" << std::endl; - } - - for (const size_t& pin : circuit_lib.pins(clock_port)) { - BasicPort port_to_constrain(circuit_lib.port_prefix(clock_port), pin, pin); - - fp << "create_clock -name "; - fp << generate_sdc_port(port_to_constrain) << " -period "; - fp << std::setprecision(10) << clock_period; - fp << " -waveform {0 "; - fp << std::setprecision(10) << clock_period / 2; - fp << "}"; - fp << "{get_ports {" << generate_sdc_port(port_to_constrain) << "}]"; - fp << std::endl; - - fp << std::endl; - } - } - - if (true == constrain_non_clock_ports) { - /* For non-clock port from the global port: give a fixed period */ - for (const CircuitPortId& global_port : global_ports) { - if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port)) { - continue; - } - - /* Print comments */ - fp << "##################################################" << std::endl; - fp << "# Constrain other global ports " << std::endl; - fp << "##################################################" << std::endl; - - /* Reach here, it means a non-clock global port and we need print constraints */ - float clock_period = SDC_FIXED_CLOCK_PERIOD; - for (const size_t& pin : circuit_lib.pins(global_port)) { - BasicPort port_to_constrain(circuit_lib.port_prefix(global_port), pin, pin); - fp << "create_clock -name "; - fp << generate_sdc_port(port_to_constrain) << " -period "; - fp << std::setprecision(10) << clock_period; - fp << " -waveform {0 "; - fp << std::setprecision(10) << clock_period / 2; - fp << "} "; - fp << "[get_ports { " << generate_sdc_port(port_to_constrain) << "}]" << std::endl; - - fp << std::endl; - } - } - } - - /* Close file handler */ - fp.close(); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - -/******************************************************************** - * Break combinational loops in FPGA fabric, which mainly come from - * configurable memory cells. - * To handle this, we disable the outputs of memory cells - *******************************************************************/ -static -void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_dir, - const ModuleManager& module_manager, - const ModuleId& top_module) { - - /* Create the file name for Verilog netlist */ - std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME)); - - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for disable configurable memory outputs for P&R flow: %s ...", - sdc_fname.c_str()); - - /* Start time count */ - clock_t t_start = clock(); - - /* Create the file stream */ - std::fstream fp; - fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("Disable configurable memory outputs for PnR")); - - /* Go recursively in the module manager, starting from the top-level module: instance id of the top-level module is 0 by default */ - rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, module_manager, top_module, - format_dir_path(module_manager.module_name(top_module))); - - /* Close file handler */ - fp.close(); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - -/******************************************************************** - * Break combinational loops in FPGA fabric, which mainly come from - * loops of multiplexers. - * To handle this, we disable the timing at outputs of routing multiplexers - *******************************************************************/ -static -void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - const ModuleManager& module_manager) { - /* Create the file name for Verilog netlist */ - std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_MUX_OUTPUTS_FILE_NAME)); - - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for disable routing multiplexer outputs for P&R flow: %s ...", - sdc_fname.c_str()); - - /* Start time count */ - clock_t t_start = clock(); - - /* Create the file stream */ - std::fstream fp; - fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("Disable routing multiplexer outputs for PnR")); - - /* Iterate over the MUX modules */ - for (const MuxId& mux_id : mux_lib.muxes()) { - const CircuitModelId& mux_model = mux_lib.mux_circuit_model(mux_id); - - /* Skip LUTs, we only care about multiplexers here */ - if (SPICE_MODEL_MUX != circuit_lib.model_type(mux_model)) { - continue; - } - - const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); - std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, - find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), - std::string("")); - /* Find the module name in module manager */ - ModuleId mux_module = module_manager.find_module(mux_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); - - /* Disable the timing for the output ports */ - for (const BasicPort& output_port : module_manager.module_ports_by_type(mux_module, ModuleManager::MODULE_OUTPUT_PORT)) { - fp << "set_disable_timing [get_pins -filter \"name =~ " << output_port.get_name() << "*\" "; - fp << "-of [get_cells -hier -filter \"ref_lib_cell_name == " << mux_module_name << "\"]]" << std::endl; - fp << std::endl; - } - } - - /* Close file handler */ - fp.close(); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - -/******************************************************************** - * Break combinational loops in FPGA fabric, which mainly come from - * loops of multiplexers. - * To handle this, we disable the timing at outputs of Switch blocks - * This function is designed for flatten routing hierarchy - *******************************************************************/ -static -void print_pnr_sdc_flatten_routing_disable_switch_block_outputs(const std::string& sdc_dir, - const ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb) { - /* Create the file name for Verilog netlist */ - std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME)); - - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for disable Switch Block outputs for P&R flow: %s ...", - sdc_fname.c_str()); - - /* Start time count */ - clock_t t_start = clock(); - - /* Create the file stream */ - std::fstream fp; - fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR")); - - /* Get the range of SB array */ - DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); - /* Go for each SB */ - for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - std::string sb_instance_name = generate_switch_block_module_name(gsb_coordinate); - - ModuleId sb_module = module_manager.find_module(sb_instance_name); - VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); - - /* Disable the outputs of the module */ - for (const BasicPort& output_port : module_manager.module_ports_by_type(sb_module, ModuleManager::MODULE_OUTPUT_PORT)) { - fp << "set_disable_timing " << sb_instance_name << "/" << output_port.get_name() << std::endl; - fp << std::endl; - } - } - } - - /* Close file handler */ - fp.close(); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - -/******************************************************************** - * Break combinational loops in FPGA fabric, which mainly come from - * loops of multiplexers. - * To handle this, we disable the timing at outputs of Switch blocks - * This function is designed for compact routing hierarchy - *******************************************************************/ -static -void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::string& sdc_dir, - const ModuleManager& module_manager, - const ModuleId& top_module, - const DeviceRRGSB& L_device_rr_gsb) { - /* Create the file name for Verilog netlist */ - std::string sdc_fname(sdc_dir + std::string(SDC_DISABLE_SB_OUTPUTS_FILE_NAME)); - - vpr_printf(TIO_MESSAGE_INFO, - "Generating SDC for disable Switch Block outputs for P&R flow: %s ...", - sdc_fname.c_str()); - - /* Start time count */ - clock_t t_start = clock(); - - /* Create the file stream */ - std::fstream fp; - fp.open(sdc_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Generate the descriptions*/ - print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR")); - - /* Build unique switch block modules */ - for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) { - const RRGSB& rr_gsb = L_device_rr_gsb.get_sb_unique_module(isb); - vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate); - - ModuleId sb_module = module_manager.find_module(sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); - - /* Find all the instances in the top-level module */ - for (const size_t& instance_id : module_manager.child_module_instances(top_module, sb_module)) { - std::string sb_instance_name = module_manager.instance_name(top_module, sb_module, instance_id); - /* Disable the outputs of the module */ - for (const BasicPort& output_port : module_manager.module_ports_by_type(sb_module, ModuleManager::MODULE_OUTPUT_PORT)) { - fp << "set_disable_timing " << sb_instance_name << "/" << output_port.get_name() << std::endl; - fp << std::endl; - } - } - } - - /* Close file handler */ - fp.close(); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - -/******************************************************************** - * Top-level function to print a number of SDC files in different purpose - * This function will generate files upon the options provided by users - * 1. Design constraints for CLBs - * 2. Design constraints for Switch Blocks - * 3. Design constraints for Connection Blocks - * 4. Design constraints for breaking the combinational loops in FPGA fabric - *******************************************************************/ -void print_pnr_sdc(const SdcOption& sdc_options, - const float& critical_path_delay, - const std::vector& switches, - const DeviceRRGSB& L_device_rr_gsb, - const ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const bool& compact_routing_hierarchy) { - - /* Constrain global ports */ - if (true == sdc_options.constrain_global_port()) { - print_pnr_sdc_global_ports(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports, false); - } - - std::string top_module_name = generate_fpga_top_module_name(); - ModuleId top_module = module_manager.find_module(top_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(top_module)); - - /* Output Design Constraints to disable outputs of memory cells */ - if (true == sdc_options.constrain_configurable_memory_outputs()) { - print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(), module_manager, top_module); - } - - /* Break loops from Multiplexer Output */ - if (true == sdc_options.constrain_routing_multiplexer_outputs()) { - print_sdc_disable_routing_multiplexer_outputs(sdc_options.sdc_dir(), - mux_lib, circuit_lib, - module_manager); - } - - /* Break loops from any SB output */ - if (true == sdc_options.constrain_switch_block_outputs()) { - if (true == compact_routing_hierarchy) { - print_pnr_sdc_compact_routing_disable_switch_block_outputs(sdc_options.sdc_dir(), - module_manager, top_module, - L_device_rr_gsb); - } else { - VTR_ASSERT_SAFE (false == compact_routing_hierarchy); - print_pnr_sdc_flatten_routing_disable_switch_block_outputs(sdc_options.sdc_dir(), - module_manager, - L_device_rr_gsb); - } - } - - /* Output routing constraints for Switch Blocks */ - if (true == sdc_options.constrain_sb()) { - if (true == compact_routing_hierarchy) { - print_pnr_sdc_compact_routing_constrain_sb_timing(sdc_options.sdc_dir(), - module_manager, - switches, - L_device_rr_gsb); - } else { - VTR_ASSERT_SAFE (false == compact_routing_hierarchy); - print_pnr_sdc_flatten_routing_constrain_sb_timing(sdc_options.sdc_dir(), - module_manager, - switches, - L_device_rr_gsb); - } - } - - /* Output routing constraints for Connection Blocks */ - if (true == sdc_options.constrain_cb()) { - if (true == compact_routing_hierarchy) { - print_pnr_sdc_compact_routing_constrain_cb_timing(sdc_options.sdc_dir(), - module_manager, - switches, - L_device_rr_gsb); - } else { - VTR_ASSERT_SAFE (false == compact_routing_hierarchy); - print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_options.sdc_dir(), - module_manager, - L_device_rr_gsb, - switches); - } - } - - /* Output Timing constraints for Programmable blocks */ - if (true == sdc_options.constrain_grid()) { - print_pnr_sdc_constrain_grid_timing(sdc_options.sdc_dir(), - module_manager); - } -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h deleted file mode 100644 index 38f0a3793..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_writer.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef PNR_SDC_WRITER_H -#define PNR_SDC_WRITER_H - -#include -#include "vtr_geometry.h" -#include "vpr_types.h" -#include "rr_blocks.h" -#include "module_manager.h" -#include "mux_library.h" -#include "circuit_library.h" -#include "sdc_option.h" - -void print_pnr_sdc(const SdcOption& sdc_options, - const float& critical_path_delay, - const std::vector& switches, - const DeviceRRGSB& L_device_rr_gsb, - const ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const bool& compact_routing_hierarchy); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp deleted file mode 100644 index 509ae72a5..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.cpp +++ /dev/null @@ -1,58 +0,0 @@ -/******************************************************************** - * Useful APIs for SDC generator - *******************************************************************/ -#include -#include "pnr_sdc_writer.h" -#include "analysis_sdc_writer.h" - -#include "sdc_api.h" - -/******************************************************************** - * Top-level function to launch SDC generator - *******************************************************************/ -void fpga_sdc_generator(const SdcOption& sdc_options, - const float& critical_path_delay, - const std::vector& rr_switches, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const bool& compact_routing_hierarchy) { - vpr_printf(TIO_MESSAGE_INFO, - "SDC generator starts...\n"); - - /* Start time count */ - clock_t t_start = clock(); - - if (true == sdc_options.generate_sdc_pnr()) { - print_pnr_sdc(sdc_options, critical_path_delay, - rr_switches, L_device_rr_gsb, - module_manager, mux_lib, - circuit_lib, global_ports, - compact_routing_hierarchy); - } - - if (true == sdc_options.generate_sdc_analysis()) { - print_analysis_sdc(sdc_options.sdc_dir(), - critical_path_delay, - L_device_rr_gsb, - L_logical_blocks, device_size, L_grids, - L_blocks, - module_manager, - circuit_lib, global_ports, - compact_routing_hierarchy); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "SDC generation took %g seconds\n", - run_time_sec); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h deleted file mode 100644 index aa3177443..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_api.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef SDC_API_H -#define SDC_API_H - -#include -#include "sdc_option.h" -#include "circuit_library.h" -#include "mux_library.h" -#include "module_manager.h" - -void fpga_sdc_generator(const SdcOption& sdc_options, - const float& critical_path_delay, - const std::vector& rr_switches, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const bool& compact_routing_hierarchy); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.cpp deleted file mode 100644 index 6df5ede5f..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.cpp +++ /dev/null @@ -1,62 +0,0 @@ -/******************************************************************** - * Most utilized function used to constrain memory cells in FPGA - * fabric using SDC commands - *******************************************************************/ -#include "fpga_x2p_utils.h" -#include "sdc_writer_utils.h" - -#include "sdc_memory_utils.h" - -/******************************************************************** - * Print SDC commands to disable outputs of all the configurable memory modules - * in a given module - * This function will be executed in a recursive way, - * using a Depth-First Search (DFS) strategy - * It will iterate over all the configurable children under each module - * and print a SDC command to disable its outputs - *******************************************************************/ -void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& parent_module_path) { - - /* For each configurable child, we will go one level down in priority */ - for (size_t child_index = 0; child_index < module_manager.configurable_children(parent_module).size(); ++child_index) { - std::string child_module_path = parent_module_path; - ModuleId child_module_id = module_manager.configurable_children(parent_module)[child_index]; - size_t child_instance_id = module_manager.configurable_child_instances(parent_module)[child_index]; - if (true == module_manager.instance_name(parent_module, child_module_id, child_instance_id).empty()) { - /* Give a default name __ */ - child_module_path += module_manager.module_name(child_module_id); - child_module_path += "_"; - child_module_path += std::to_string(child_instance_id); - child_module_path += "_"; - } else { - child_module_path += module_manager.instance_name(parent_module, child_module_id, child_instance_id); - } - child_module_path = format_dir_path(child_module_path); - - rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, module_manager, - child_module_id, - child_module_path); - } - - /* If there is no configurable children any more, this is a leaf module, print a SDC command for disable timing */ - if (0 < module_manager.configurable_children(parent_module).size()) { - return; - } - - /* Validate file stream */ - check_file_handler(fp); - - /* Disable timing for each output port of this module */ - for (const BasicPort& output_port : module_manager.module_ports_by_type(parent_module, ModuleManager::MODULE_OUTPUT_PORT)) { - for (const size_t& pin : output_port.pins()) { - BasicPort output_pin(output_port.get_name(), pin, pin); - fp << "set_disable_timing "; - fp << parent_module_path << generate_sdc_port(output_pin); - fp << std::endl; - } - } -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.h deleted file mode 100644 index 9ce57d6d8..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_memory_utils.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef SDC_MEMORY_UTILS_H -#define SDC_MEMORY_UTILS_H - -#include -#include -#include "module_manager.h" - -void rec_print_pnr_sdc_disable_configurable_memory_module_output(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const std::string& parent_module_path); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.cpp deleted file mode 100644 index 088266337..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.cpp +++ /dev/null @@ -1,121 +0,0 @@ -/******************************************************************** - * Member functions for a data structure which includes all the options for the SDC generator - ********************************************************************/ -#include "sdc_option.h" - -/******************************************************************** - * Public Constructors - ********************************************************************/ -SdcOption::SdcOption(const std::string& sdc_dir) { - sdc_dir_ = sdc_dir; - constrain_global_port_ = false; - constrain_grid_ = false; - constrain_sb_ = false; - constrain_cb_ = false; - constrain_configurable_memory_outputs_ = false; - constrain_routing_multiplexer_outputs_ = false; - constrain_switch_block_outputs_ = false; -} - -/******************************************************************** - * Public accessors - ********************************************************************/ -std::string SdcOption::sdc_dir() const { - return sdc_dir_; -} - -bool SdcOption::generate_sdc() const { - return generate_sdc_pnr() && generate_sdc_analysis_; -} - -bool SdcOption::generate_sdc_pnr() const { - return constrain_global_port_ - || constrain_grid_ - || constrain_sb_ - || constrain_cb_ - || constrain_configurable_memory_outputs_ - || constrain_routing_multiplexer_outputs_ - || constrain_switch_block_outputs_; -} - -bool SdcOption::generate_sdc_analysis() const { - return generate_sdc_analysis_; -} - -bool SdcOption::constrain_global_port() const { - return constrain_global_port_; -} - -bool SdcOption::constrain_grid() const { - return constrain_grid_; -} - -bool SdcOption::constrain_sb() const { - return constrain_sb_; -} - -bool SdcOption::constrain_cb() const { - return constrain_cb_; -} - -bool SdcOption::constrain_configurable_memory_outputs() const { - return constrain_configurable_memory_outputs_; -} - -bool SdcOption::constrain_routing_multiplexer_outputs() const { - return constrain_routing_multiplexer_outputs_; -} - -bool SdcOption::constrain_switch_block_outputs() const { - return constrain_switch_block_outputs_; -} - -/******************************************************************** - * Public mutators - ********************************************************************/ -void SdcOption::set_sdc_dir(const std::string& sdc_dir) { - sdc_dir_ = sdc_dir; -} - -void SdcOption::set_generate_sdc_pnr(const bool& generate_sdc_pnr) { - constrain_global_port_ = generate_sdc_pnr; - constrain_grid_ = generate_sdc_pnr; - constrain_sb_ = generate_sdc_pnr; - constrain_cb_ = generate_sdc_pnr; - constrain_configurable_memory_outputs_ = generate_sdc_pnr; - constrain_routing_multiplexer_outputs_ = generate_sdc_pnr; - constrain_switch_block_outputs_ = generate_sdc_pnr; -} - -void SdcOption::set_generate_sdc_analysis(const bool& generate_sdc_analysis) { - generate_sdc_analysis_ = generate_sdc_analysis; -} - -void SdcOption::set_constrain_global_port(const bool& constrain_global_port) { - constrain_global_port_ = constrain_global_port; -} - -void SdcOption::set_constrain_grid(const bool& constrain_grid) { - constrain_grid_ = constrain_grid; -} - -void SdcOption::set_constrain_sb(const bool& constrain_sb) { - constrain_sb_ = constrain_sb; -} - -void SdcOption::set_constrain_cb(const bool& constrain_cb) { - constrain_cb_ = constrain_cb; -} - -void SdcOption::set_constrain_configurable_memory_outputs(const bool& constrain_config_mem_outputs) { - constrain_configurable_memory_outputs_ = constrain_config_mem_outputs; -} - -void SdcOption::set_constrain_routing_multiplexer_outputs(const bool& constrain_routing_mux_outputs) { - constrain_routing_multiplexer_outputs_ = constrain_routing_mux_outputs; -} - -void SdcOption::set_constrain_switch_block_outputs(const bool& constrain_sb_outputs) { - constrain_switch_block_outputs_ = constrain_sb_outputs; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.h deleted file mode 100644 index ee6192830..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_option.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef SDC_OPTION_H -#define SDC_OPTION_H - -/******************************************************************** - * A data structure to include all the options for the SDC generator - ********************************************************************/ - -#include - -class SdcOption { - public: /* Public Constructors */ - SdcOption(const std::string& sdc_dir); - public: /* Public accessors */ - std::string sdc_dir() const; - bool generate_sdc() const; - bool generate_sdc_pnr() const; - bool generate_sdc_analysis() const; - bool constrain_global_port() const; - bool constrain_grid() const; - bool constrain_sb() const; - bool constrain_cb() const; - bool constrain_configurable_memory_outputs() const; - bool constrain_routing_multiplexer_outputs() const; - bool constrain_switch_block_outputs() const; - public: /* Public mutators */ - void set_sdc_dir(const std::string& sdc_dir); - void set_generate_sdc_pnr(const bool& generate_sdc_pnr); - void set_generate_sdc_analysis(const bool& generate_sdc_analysis); - void set_constrain_global_port(const bool& constrain_global_port); - void set_constrain_grid(const bool& constrain_grid); - void set_constrain_sb(const bool& constrain_sb); - void set_constrain_cb(const bool& constrain_cb); - void set_constrain_configurable_memory_outputs(const bool& constrain_config_mem_outputs); - void set_constrain_routing_multiplexer_outputs(const bool& constrain_routing_mux_outputs); - void set_constrain_switch_block_outputs(const bool& constrain_sb_outputs); - private: /* Internal data */ - std::string sdc_dir_; - bool constrain_global_port_; - bool constrain_grid_; - bool constrain_sb_; - bool constrain_cb_; - bool constrain_configurable_memory_outputs_; - bool constrain_routing_multiplexer_outputs_; - bool constrain_switch_block_outputs_; - bool generate_sdc_analysis_; -}; - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h deleted file mode 100644 index 9a9f3af29..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_naming.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef SDC_WRITER_NAMING_H -#define SDC_WRITER_NAMING_H - -constexpr char* SDC_FILE_NAME_POSTFIX = ".sdc"; - -constexpr char* SDC_GLOBAL_PORTS_FILE_NAME = "global_ports.sdc"; -constexpr char* SDC_BENCHMARK_ANALYSIS_FILE_NAME= "fpga_top_analysis.sdc"; -constexpr char* SDC_DISABLE_CONFIG_MEM_OUTPUTS_FILE_NAME = "disable_configurable_memory_outputs.sdc"; -constexpr char* SDC_DISABLE_MUX_OUTPUTS_FILE_NAME = "disable_routing_multiplexer_outputs.sdc"; -constexpr char* SDC_DISABLE_SB_OUTPUTS_FILE_NAME = "disable_sb_outputs.sdc"; -constexpr char* SDC_CB_FILE_NAME = "cb.sdc"; - -constexpr char* SDC_ANALYSIS_FILE_NAME = "fpga_top_analysis.sdc"; - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp deleted file mode 100644 index b3228d007..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp +++ /dev/null @@ -1,197 +0,0 @@ -/******************************************************************** - * This file include most utilized functions to be used in SDC writers - *******************************************************************/ -#include -#include -#include - -#include "fpga_x2p_utils.h" - -#include "sdc_writer_utils.h" - -/******************************************************************** - * Write a head (description) in SDC file - *******************************************************************/ -void print_sdc_file_header(std::fstream& fp, - const std::string& usage) { - - check_file_handler(fp); - - auto end = std::chrono::system_clock::now(); - std::time_t end_time = std::chrono::system_clock::to_time_t(end); - - fp << "#############################################" << std::endl; - fp << "#\tSynopsys Design Constraints (SDC)" << std::endl; - fp << "#\tFor FPGA fabric " << std::endl; - fp << "#\tDescription: " << usage << std::endl; - fp << "#\tAuthor: Xifan TANG " << std::endl; - fp << "#\tOrganization: University of Utah " << std::endl; - fp << "#\tDate: " << std::ctime(&end_time); - fp << "#############################################" << std::endl; - fp << std::endl; -} - - -/******************************************************************** - * Write a port in SDC format - *******************************************************************/ -std::string generate_sdc_port(const BasicPort& port) { - std::string sdc_line; - - std::string size_str = "[" + std::to_string(port.get_lsb()) + ":" + std::to_string(port.get_msb()) + "]"; - - /* Only connection require a format of [:] - * others require a format of [:] - */ - /* When LSB == MSB, we can use a simplified format []*/ - if ( 1 == port.get_width()) { - size_str = "[" + std::to_string(port.get_lsb()) + "]"; - } - sdc_line = port.get_name() + size_str; - - return sdc_line; -} - -/******************************************************************** - * Constrain a path between two ports of a module with a given maximum timing value - *******************************************************************/ -void print_pnr_sdc_constrain_max_delay(std::fstream& fp, - const std::string& src_instance_name, - const std::string& src_port_name, - const std::string& des_instance_name, - const std::string& des_port_name, - const float& delay) { - /* Validate file stream */ - check_file_handler(fp); - - fp << "set_max_delay"; - - fp << " -from "; - if (!src_instance_name.empty()) { - fp << src_instance_name << "/"; - } - fp << src_port_name; - - fp << " -to "; - - if (!des_instance_name.empty()) { - fp << des_instance_name << "/"; - } - fp << des_port_name; - - fp << " " << std::setprecision(10) << delay; - - fp << std::endl; -} - -/******************************************************************** - * Constrain a path between two ports of a module with a given timing value - * Note: this function uses set_max_delay !!! - *******************************************************************/ -void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& input_parent_module_id, - const ModulePortId& module_input_port_id, - const ModuleId& output_parent_module_id, - const ModulePortId& module_output_port_id, - const float& tmax) { - print_pnr_sdc_constrain_max_delay(fp, - module_manager.module_name(input_parent_module_id), - generate_sdc_port(module_manager.module_port(input_parent_module_id, module_input_port_id)), - module_manager.module_name(output_parent_module_id), - generate_sdc_port(module_manager.module_port(output_parent_module_id, module_output_port_id)), - tmax); - -} - -/******************************************************************** - * Constrain a path between two ports of a module with a given timing value - * This function will NOT output the module name - * Note: this function uses set_max_delay !!! - *******************************************************************/ -void print_pnr_sdc_constrain_port2port_timing(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& input_parent_module_id, - const ModulePortId& module_input_port_id, - const ModuleId& output_parent_module_id, - const ModulePortId& module_output_port_id, - const float& tmax) { - print_pnr_sdc_constrain_max_delay(fp, - std::string(), - generate_sdc_port(module_manager.module_port(input_parent_module_id, module_input_port_id)), - std::string(), - generate_sdc_port(module_manager.module_port(output_parent_module_id, module_output_port_id)), - tmax); - -} - -/******************************************************************** - * Disable timing for a port - *******************************************************************/ -void print_sdc_disable_port_timing(std::fstream& fp, - const BasicPort& port) { - /* Validate file stream */ - check_file_handler(fp); - - fp << "set_disable_timing "; - - fp << generate_sdc_port(port); - - fp << std::endl; -} - -/******************************************************************** - * Set the input delay for a port in SDC format - * Note that the input delay will be bounded by a clock port - *******************************************************************/ -void print_sdc_set_port_input_delay(std::fstream& fp, - const BasicPort& port, - const BasicPort& clock_port, - const float& delay) { - /* Validate file stream */ - check_file_handler(fp); - - fp << "set_input_delay "; - - fp << "-clock "; - - fp << generate_sdc_port(clock_port); - - fp << " -max "; - - fp << std::setprecision(10) << delay; - - fp << " "; - - fp << generate_sdc_port(port); - - fp << std::endl; -} - -/******************************************************************** - * Set the output delay for a port in SDC format - * Note that the output delay will be bounded by a clock port - *******************************************************************/ -void print_sdc_set_port_output_delay(std::fstream& fp, - const BasicPort& port, - const BasicPort& clock_port, - const float& delay) { - /* Validate file stream */ - check_file_handler(fp); - - fp << "set_output_delay "; - - fp << "-clock "; - - fp << generate_sdc_port(clock_port); - - fp << " -max "; - - fp << std::setprecision(10) << delay; - - fp << " "; - - fp << generate_sdc_port(port); - - fp << std::endl; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h deleted file mode 100644 index d5296032d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h +++ /dev/null @@ -1,50 +0,0 @@ -#ifndef SDC_WRITER_UTILS_H -#define SDC_WRITER_UTILS_H - -#include -#include -#include "device_port.h" -#include "module_manager.h" - -void print_sdc_file_header(std::fstream& fp, - const std::string& usage); - -std::string generate_sdc_port(const BasicPort& port); - -void print_pnr_sdc_constrain_max_delay(std::fstream& fp, - const std::string& src_instance_name, - const std::string& src_port_name, - const std::string& des_instance_name, - const std::string& des_port_name, - const float& delay); - -void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& input_parent_module_id, - const ModulePortId& module_input_port_id, - const ModuleId& output_parent_module_id, - const ModulePortId& module_output_port_id, - const float& tmax); - -void print_pnr_sdc_constrain_port2port_timing(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& input_parent_module_id, - const ModulePortId& module_input_port_id, - const ModuleId& output_parent_module_id, - const ModulePortId& module_output_port_id, - const float& tmax); - -void print_sdc_disable_port_timing(std::fstream& fp, - const BasicPort& port); - -void print_sdc_set_port_input_delay(std::fstream& fp, - const BasicPort& port, - const BasicPort& clock_port, - const float& delay); - -void print_sdc_set_port_output_delay(std::fstream& fp, - const BasicPort& port, - const BasicPort& clock_port, - const float& delay); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp deleted file mode 100644 index 9daa919d1..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp +++ /dev/null @@ -1,184 +0,0 @@ -/****************************************************************************** - * This file includes member functions for data structure BitstreamManager - ******************************************************************************/ -#include - -#include "vtr_assert.h" -#include "bitstream_manager.h" - -/************************************************** - * Public Accessors : Aggregates - *************************************************/ -/* Find all the configuration bits */ -BitstreamManager::config_bit_range BitstreamManager::bits() const { - return vtr::make_range(bit_ids_.begin(), bit_ids_.end()); -} - -/* Find all the configuration blocks */ -BitstreamManager::config_block_range BitstreamManager::blocks() const { - return vtr::make_range(block_ids_.begin(), block_ids_.end()); -} - -/****************************************************************************** - * Public Accessors - ******************************************************************************/ -bool BitstreamManager::bit_value(const ConfigBitId& bit_id) const { - /* Ensure a valid id */ - VTR_ASSERT(true == valid_bit_id(bit_id)); - - return bit_values_[bit_id]; -} - -std::string BitstreamManager::block_name(const ConfigBlockId& block_id) const { - /* Ensure the input ids are valid */ - VTR_ASSERT(true == valid_block_id(block_id)); - - return block_names_[block_id]; -} - -ConfigBlockId BitstreamManager::block_parent(const ConfigBlockId& block_id) const { - /* Ensure the input ids are valid */ - VTR_ASSERT(true == valid_block_id(block_id)); - - return parent_block_ids_[block_id]; -} - -std::vector BitstreamManager::block_children(const ConfigBlockId& block_id) const { - /* Ensure the input ids are valid */ - VTR_ASSERT(true == valid_block_id(block_id)); - - return child_block_ids_[block_id]; -} - -std::vector BitstreamManager::block_bits(const ConfigBlockId& block_id) const { - /* Ensure the input ids are valid */ - VTR_ASSERT(true == valid_block_id(block_id)); - - return block_bit_ids_[block_id]; -} - -ConfigBlockId BitstreamManager::bit_parent_block(const ConfigBitId& bit_id) const { - /* Ensure the input ids are valid */ - VTR_ASSERT(true == valid_bit_id(bit_id)); - - return bit_parent_block_ids_[bit_id]; -} - -size_t BitstreamManager::bit_index_in_parent_block(const ConfigBitId& bit_id) const { - /* Ensure the input ids are valid */ - VTR_ASSERT(true == valid_bit_id(bit_id)); - - ConfigBlockId bit_parent_block = bit_parent_block_ids_[bit_id]; - - VTR_ASSERT(true == valid_block_id(bit_parent_block)); - - for (size_t index = 0; index < block_bits(bit_parent_block).size(); ++index) { - if (bit_id == block_bits(bit_parent_block)[index]) { - return index; - } - } - - /* Not found, return in valid value */ - return size_t(-1); -} - -/* Find the child block in a bitstream manager with a given name */ -ConfigBlockId BitstreamManager::find_child_block(const ConfigBlockId& block_id, - const std::string& child_block_name) const { - /* Ensure the input ids are valid */ - VTR_ASSERT(true == valid_block_id(block_id)); - - std::vector candidates; - - for (const ConfigBlockId& child : block_children(block_id)) { - if (0 == child_block_name.compare(block_name(child))) { - candidates.push_back(child); - } - } - - /* We should have 0 or 1 candidate! */ - VTR_ASSERT(0 == candidates.size() || 1 == candidates.size()); - if (0 == candidates.size()) { - /* Not found, return an invalid value */ - return ConfigBlockId::INVALID(); - } - return candidates[0]; -} - -/****************************************************************************** - * Public Mutators - ******************************************************************************/ -ConfigBitId BitstreamManager::add_bit(const bool& bit_value) { - ConfigBitId bit = ConfigBitId(bit_ids_.size()); - /* Add a new bit, and allocate associated data structures */ - bit_ids_.push_back(bit); - bit_values_.push_back(bit_value); - shared_config_bit_values_.emplace_back(); - bit_parent_block_ids_.push_back(ConfigBlockId::INVALID()); - - return bit; -} - -ConfigBlockId BitstreamManager::add_block(const std::string& block_name) { - ConfigBlockId block = ConfigBlockId(block_ids_.size()); - /* Add a new bit, and allocate associated data structures */ - block_ids_.push_back(block); - block_names_.push_back(block_name); - block_bit_ids_.emplace_back(); - parent_block_ids_.push_back(ConfigBlockId::INVALID()); - child_block_ids_.emplace_back(); - - return block; -} - -void BitstreamManager::add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block) { - /* Ensure the input ids are valid */ - VTR_ASSERT(true == valid_block_id(parent_block)); - VTR_ASSERT(true == valid_block_id(child_block)); - - /* We should have only a parent block for each block! */ - VTR_ASSERT(ConfigBlockId::INVALID() == parent_block_ids_[child_block]); - - /* Ensure the child block is not in the list of children of the parent block */ - std::vector::iterator it = std::find(child_block_ids_[parent_block].begin(), child_block_ids_[parent_block].end(), child_block); - VTR_ASSERT(it == child_block_ids_[parent_block].end()); - - /* Add the child_block to the parent_block */ - child_block_ids_[parent_block].push_back(child_block); - /* Register the block in the parent of the block */ - parent_block_ids_[child_block] = parent_block; -} - -void BitstreamManager::add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit) { - /* Ensure the input ids are valid */ - VTR_ASSERT(true == valid_block_id(block)); - VTR_ASSERT(true == valid_bit_id(bit)); - - /* We should have only a parent block for each bit! */ - VTR_ASSERT(ConfigBlockId::INVALID() == bit_parent_block_ids_[bit]); - - /* Add the bit to the block */ - block_bit_ids_[block].push_back(bit); - /* Register the block in the parent of the bit */ - bit_parent_block_ids_[bit] = block; -} - -void BitstreamManager::add_shared_config_bit_values(const ConfigBitId& bit, const std::vector& shared_config_bits) { - /* Ensure the input ids are valid */ - VTR_ASSERT(true == valid_bit_id(bit)); - - shared_config_bit_values_[bit] = shared_config_bits; -} - -/****************************************************************************** - * Public Validators - ******************************************************************************/ -bool BitstreamManager::valid_bit_id(const ConfigBitId& bit_id) const { - return (size_t(bit_id) < bit_ids_.size()) && (bit_id == bit_ids_[bit_id]); -} - -bool BitstreamManager::valid_block_id(const ConfigBlockId& block_id) const { - return (size_t(block_id) < block_ids_.size()) && (block_id == block_ids_[block_id]); -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h deleted file mode 100644 index a5c3a0f02..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.h +++ /dev/null @@ -1,129 +0,0 @@ -/****************************************************************************** - * This file introduces a data structure to store bitstream-related information - * - * General concept - * --------------- - * The idea is to create a unified data structure that stores all the configuration bits - * with proper annotation to which modules in FPGA fabric it belongs to. - * 1. It can be easily organized in fabric-dependent representation - * (generate a sequence of bitstream which exactly fit the configuration protocol of FPGA fabric) - * 2. Or it can be easily organized in fabric-independent representation (think about XML file) - * - * Cross-reference - * --------------- - * May be used only when you want to bind the bitstream to a specific FPGA fabric! - * If you do so, please make sure the block name is exactly same as the instance name - * of a child module in ModuleManager!!! - * The configurable modules/instances in module manager are arranged - * in the sequence to fit different configuration protocol. - * By using the link between ModuleManager and BitstreamManager, - * we can build a sequence of configuration bits to fit different configuration protocols. - * - * +------------------+ +-----------------+ - * | | block_name == instance_name | | - * | BitstreamManager |-------------------------------->| ModuleManager | - * | | | | - * +------------------+ +-----------------+ - * - * Restrictions: - * 1. Each block inside BitstreamManager should have only 1 parent block - * and multiple child block - * 2. Each bit inside BitstreamManager should have only 1 parent block - * - ******************************************************************************/ -#ifndef BITSTREAM_MANAGER_H -#define BITSTREAM_MANAGER_H - -#include -#include -#include "vtr_vector.h" - -#include "bitstream_manager_fwd.h" - -class BitstreamManager { - public: /* Types and ranges */ - typedef vtr::vector::const_iterator config_bit_iterator; - typedef vtr::vector::const_iterator config_block_iterator; - - typedef vtr::Range config_bit_range; - typedef vtr::Range config_block_range; - - public: /* Public aggregators */ - /* Find all the configuration bits */ - config_bit_range bits() const; - - config_block_range blocks() const; - - public: /* Public Accessors */ - /* Find the value of bitstream */ - bool bit_value(const ConfigBitId& bit_id) const; - - /* Find a name of a block */ - std::string block_name(const ConfigBlockId& block_id) const; - - /* Find the parent of a block */ - ConfigBlockId block_parent(const ConfigBlockId& block_id) const; - - /* Find the children of a block */ - std::vector block_children(const ConfigBlockId& block_id) const; - - /* Find all the bits that belong to a block */ - std::vector block_bits(const ConfigBlockId& block_id) const; - - /* Find the parent block of a bit */ - ConfigBlockId bit_parent_block(const ConfigBitId& bit_id) const; - - /* Find the index of a configuration bit in its parent block */ - size_t bit_index_in_parent_block(const ConfigBitId& bit_id) const; - - /* Find the child block in a bitstream manager with a given name */ - ConfigBlockId find_child_block(const ConfigBlockId& block_id, const std::string& child_block_name) const; - - public: /* Public Mutators */ - /* Add a new configuration bit to the bitstream manager */ - ConfigBitId add_bit(const bool& bit_value); - - /* Add a new block of configuration bits to the bitstream manager */ - ConfigBlockId add_block(const std::string& block_name); - - /* Set a block as a child block of another */ - void add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block); - - /* Add a configuration bit to a block */ - void add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit); - - /* Add share configuration bits to a configuration bit */ - void add_shared_config_bit_values(const ConfigBitId& bit, const std::vector& shared_config_bits); - - public: /* Public Validators */ - bool valid_bit_id(const ConfigBitId& bit_id) const; - - bool valid_block_id(const ConfigBlockId& block_id) const; - - private: /* Internal data */ - /* Unique id of a block of bits in the Bitstream */ - vtr::vector block_ids_; - vtr::vector> block_bit_ids_; - - /* Back-annotation for the bits */ - /* Parent block of a bit in the Bitstream - * For each bit, the block name can be designed to be same as the instance name in a module - * to reflect its position in the module tree (ModuleManager) - * Note that the blocks here all unique, unlike ModuleManager where modules can be instanciated - * Therefore, this block graph can be considered as a flattened graph of ModuleGraph - */ - vtr::vector block_names_; - vtr::vector parent_block_ids_; - vtr::vector> child_block_ids_; - - /* Unique id of a bit in the Bitstream */ - vtr::vector bit_ids_; - vtr::vector bit_parent_block_ids_; - /* value of a bit in the Bitstream */ - vtr::vector bit_values_; - /* value of a shared configuration bits in the Bitstream */ - vtr::vector> shared_config_bit_values_; -}; - -#endif - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_fwd.h deleted file mode 100644 index a9cebe55a..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_fwd.h +++ /dev/null @@ -1,20 +0,0 @@ -/************************************************** - * This file includes only declarations for - * the data structures for bitstream database - * Please refer to bitstream_manager.h for more details - *************************************************/ -#ifndef BITSTREAM_MANAGER_FWD_H -#define BITSTREAM_MANAGER_FWD_H - -#include "vtr_strong_id.h" - -/* Strong Ids for BitstreamContext */ -struct config_block_id_tag; -struct config_bit_id_tag; - -typedef vtr::StrongId ConfigBlockId; -typedef vtr::StrongId ConfigBitId; - -class BitstreamManager; - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp deleted file mode 100644 index 9a17662eb..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.cpp +++ /dev/null @@ -1,53 +0,0 @@ -/******************************************************************** - * This file includes most utilized functions for data structure - * BitstreamManager - * - * Note: These functions are not generic enough so that they - * should NOT be a member function! - *******************************************************************/ -#include - -#include "vtr_assert.h" -#include "util.h" - -#include "bitstream_manager_utils.h" - -/******************************************************************** - * Recursively find the hierarchy of a block of bitstream manager - * Return a vector of the block ids, where the top-level block - * locates in the head, while the leaf block locates in the tail - * top, next, ... , block - *******************************************************************/ -std::vector find_bitstream_manager_block_hierarchy(const BitstreamManager& bitstream_manager, - const ConfigBlockId& block) { - std::vector block_hierarchy; - ConfigBlockId temp_block = block; - - /* Generate a tree of parent block */ - while (true == bitstream_manager.valid_block_id(temp_block)) { - block_hierarchy.push_back(temp_block); - /* Go to upper level */ - temp_block = bitstream_manager.block_parent(temp_block); - } - - /* Reverse the vector, so that top block stay in the first */ - std::reverse(block_hierarchy.begin(), block_hierarchy.end()); - - return block_hierarchy; -} - -/******************************************************************** - * Find all the top-level blocks in a bitstream manager, - * which have no parents - *******************************************************************/ -std::vector find_bitstream_manager_top_blocks(const BitstreamManager& bitstream_manager) { - std::vector top_blocks; - for (const ConfigBlockId& blk : bitstream_manager.blocks()) { - if (ConfigBlockId::INVALID() != bitstream_manager.block_parent(blk)) { - continue; - } - top_blocks.push_back(blk); - } - - return top_blocks; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.h deleted file mode 100644 index 196aa0506..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager_utils.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef BITSTREAM_MANAGER_UTILS_H -#define BITSTREAM_MANAGER_UTILS_H - -#include -#include "bitstream_manager.h" - -std::vector find_bitstream_manager_block_hierarchy(const BitstreamManager& bitstream_manager, - const ConfigBlockId& block); - -std::vector find_bitstream_manager_top_blocks(const BitstreamManager& bitstream_manager); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/device_coordinator.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/device_coordinator.cpp deleted file mode 100644 index f600efe6e..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/device_coordinator.cpp +++ /dev/null @@ -1,56 +0,0 @@ -#include -#include "device_coordinator.h" - -/* Member functions for DeviceCoordinator */ -/* Public constructors */ -DeviceCoordinator::DeviceCoordinator(const DeviceCoordinator& coordinator) { - set(coordinator.get_x(), coordinator.get_y()); - return; -} - -DeviceCoordinator::DeviceCoordinator(size_t x, size_t y) { - set(x, y); - return; -} - -DeviceCoordinator::DeviceCoordinator() { - set(0, 0); - return; -} - -/* Public accessors */ - -size_t DeviceCoordinator::get_x() const { - return x_; -} - -size_t DeviceCoordinator::get_y() const { - return y_; -} - -/* Public mutators */ -void DeviceCoordinator::set(size_t x, size_t y) { - set_x(x); - set_y(y); - return; -} - -void DeviceCoordinator::set_x(size_t x) { - x_ = x; - return; -} - -void DeviceCoordinator::set_y(size_t y) { - y_ = y; - return; -} - -void DeviceCoordinator::rotate() { - std::swap(x_, y_); - return; -} - -void DeviceCoordinator::clear() { - set(0, 0); - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/device_coordinator.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/device_coordinator.h deleted file mode 100644 index 54f282232..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/device_coordinator.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef DEVICE_COORDINATOR_H -#define DEVICE_COORDINATOR_H - -#include "sides.h" - -/* Coordinator System for FPGA Device - * It is based on a 3-D (x,y,z) coordinator system - * (x,y) is used for all the routing resources, - * z is used for only grid, which have multiple logic blocks - */ -class DeviceCoordinator { - public: /* Contructors */ - DeviceCoordinator(size_t x, size_t y); - DeviceCoordinator(const DeviceCoordinator&); /* copy constructor*/ - DeviceCoordinator(); - public: /* Accessors */ - size_t get_x() const; - size_t get_y() const; - public: /* Mutators */ - void set(size_t x, size_t y); - void set_x(size_t x); - void set_y(size_t y); - void rotate(); - void clear(); - private: /* Internal Mutators */ - private: /* internal functions */ - private: /* Internal Data */ - size_t x_; - size_t y_; - size_t z_; -}; - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c deleted file mode 100644 index 7a67e96ec..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c +++ /dev/null @@ -1,205 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "vtr_assert.h" -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "path_delay.h" -#include "stats.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "circuit_library_utils.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_backannotate_utils.h" -#include "fpga_x2p_setup.h" -#include "fpga_x2p_naming.h" - -#include "mux_library_builder.h" -#include "build_device_module.h" -#include "build_device_bitstream.h" -#include "build_fabric_bitstream.h" -#include "bitstream_writer.h" - -#include "spice_api.h" -#include "verilog_api.h" -#include "sdc_api.h" -#include "fpga_bitstream.h" - -#include "fpga_x2p_reserved_words.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_api.h" - -/* Top-level API of FPGA-SPICE */ -void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, - t_arch Arch) { - t_sram_orgz_info* sram_bitstream_orgz_info = NULL; - - /* Common initializations and malloc operations */ - /* If FPGA-SPICE is not called, we should initialize the spice_models */ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.do_fpga_spice) { - fpga_x2p_setup(vpr_setup, &Arch); - } - - /* Build multiplexer graphs */ - MuxLibrary mux_lib = build_device_mux_library(num_rr_nodes, rr_node, switch_inf, Arch.spice->circuit_lib, &vpr_setup.RoutingArch); - - /* TODO: Build global routing architecture modules */ - /* Create a vector of switch infs. TODO: this should be replaced switch objects!!! */ - std::vector rr_switches; - for (short i = 0; i < vpr_setup.RoutingArch.num_switch; ++i) { - rr_switches.push_back(switch_inf[i]); - } - - /* TODO: This should be done outside this function!!! */ - vtr::Point device_size(nx + 2, ny + 2); - std::vector> grids; - /* Organize a vector (matrix) of grids to feed the top-level module generation */ - grids.resize(device_size.x()); - for (size_t ix = 0; ix < device_size.x(); ++ix) { - grids[ix].resize(device_size.y()); - for (size_t iy = 0; iy < device_size.y(); ++iy) { - grids[ix][iy] = grid[ix][iy]; - } - } - - /* Organize a vector (matrix) of clb2clb directs to feed the top-level module generation */ - std::vector clb2clb_directs; - for (int i = 0; i < num_clb2clb_directs; ++i) { - clb2clb_directs.push_back(clb2clb_direct[i]); - } - - /* Organize a vector for logical blocks to feed Verilog generator */ - std::vector L_logical_blocks; - for (int i = 0; i < num_logical_blocks; ++i) { - L_logical_blocks.push_back(logical_block[i]); - } - - /* Organize a vector for blocks to feed Verilog generator */ - std::vector L_blocks; - for (int i = 0; i < num_blocks; ++i) { - L_blocks.push_back(block[i]); - } - - /* Build module graphs */ - ModuleManager module_manager = build_device_module_graph(vpr_setup, Arch, mux_lib, - device_size, grids, - rr_switches, clb2clb_directs, device_rr_gsb); - - /* Build bitstream database if needed */ - BitstreamManager bitstream_manager; - std::vector fabric_bitstream; - if ( (TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream) - || (TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) - || (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog)) { - - /* Build fabric independent bitstream */ - bitstream_manager = build_device_bitstream(vpr_setup, Arch, module_manager, - Arch.spice->circuit_lib, mux_lib, - device_size, grids, - rr_switches, rr_node, device_rr_gsb); - - /* Build fabric dependent bitstream */ - fabric_bitstream = build_fabric_dependent_bitstream(bitstream_manager, module_manager); - - /* Write bitstream to files */ - std::string bitstream_file_path; - - if (NULL == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.bitstream_output_file) { - bitstream_file_path = std::string(vpr_setup.FileNameOpts.CircuitName); - bitstream_file_path.append(BITSTREAM_XML_FILE_NAME_POSTFIX); - } else { - bitstream_file_path = vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.bitstream_output_file; - } - - write_arch_independent_bitstream_to_xml_file(bitstream_manager, bitstream_file_path); - } - - /* Xifan TANG: SPICE Modeling, SPICE Netlist Output */ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) { - vpr_fpga_spice(vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName); - } - - /* Xifan TANG: Synthesizable verilog dumping */ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog) { - /* Create a local SRAM organization info - * TODO: This should be deprecated in future */ - VTR_ASSERT(NULL != Arch.sram_inf.verilog_sram_inf_orgz); /* Check !*/ - t_spice_model* sram_verilog_model = Arch.sram_inf.verilog_sram_inf_orgz->spice_model; - /* initialize the SRAM organization information struct */ - t_sram_orgz_info* sram_verilog_orgz_info = alloc_one_sram_orgz_info(); - init_sram_orgz_info(sram_verilog_orgz_info, Arch.sram_inf.verilog_sram_inf_orgz->type, sram_verilog_model, nx + 2, ny + 2); - - vpr_fpga_verilog(module_manager, bitstream_manager, fabric_bitstream, mux_lib, - L_logical_blocks, device_size, grids, L_blocks, device_rr_gsb, - vpr_setup, Arch, std::string(vpr_setup.FileNameOpts.CircuitName), sram_verilog_orgz_info); - } - - - /* Run SDC Generator */ - std::string src_dir = find_path_dir_name(std::string(vpr_setup.FileNameOpts.CircuitName)); - - /* Use current directory if there is not dir path given */ - if (false == src_dir.empty()) { - src_dir = format_dir_path(src_dir); - } - SdcOption sdc_options(format_dir_path(src_dir + std::string(FPGA_X2P_DEFAULT_SDC_DIR))); - sdc_options.set_generate_sdc_pnr(TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_pnr); - sdc_options.set_generate_sdc_analysis(TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_analysis); - - /* Create directory to contain the SDC files */ - create_dir_path(sdc_options.sdc_dir().c_str()); - - if (true == sdc_options.generate_sdc()) { - std::vector global_ports = find_circuit_library_global_ports(Arch.spice->circuit_lib); - /* TODO: the critical path delay unit should be explicit! */ - fpga_sdc_generator(sdc_options, - Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay / 1e-9, - rr_switches, device_rr_gsb, - L_logical_blocks, device_size, grids, L_blocks, - module_manager, mux_lib, - Arch.spice->circuit_lib, global_ports, - TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); - } - - /* Xifan Tang: Bitstream Generator */ - if ((TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream) - &&(FALSE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) - &&(FALSE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog)) { - /* Run bitstream generation here only when other functionalities are disabled; - * bitstream will be run inside SPICE and Verilog Generators - */ - vpr_fpga_bitstream_generator(vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName, &sram_bitstream_orgz_info); - /* Free sram_orgz_info */ - free_sram_orgz_info(sram_bitstream_orgz_info, - sram_bitstream_orgz_info->type); - } - - /* Free */ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.do_fpga_spice) { - /* Free all the backannotation containing post routing information */ - free_backannotate_vpr_post_route_info(); - /* TODO: free other linked lists ! */ - fpga_x2p_free(&Arch); - } - - - return; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.h deleted file mode 100644 index 28d0e65d2..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef FPGA_X2P_API_H -#define FPGA_X2P_API_H - -void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup, - t_arch Arch); - -#endif - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c deleted file mode 100644 index 5b7abd0bb..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c +++ /dev/null @@ -1,3202 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "path_delay.h" -#include "stats.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "read_xml_spice_util.h" -#include "linkedlist.h" -#include "rr_blocks.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_rr_graph_utils.h" -#include "fpga_x2p_lut_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_pb_rr_graph.h" -#include "fpga_x2p_router.h" -#include "fpga_x2p_unique_routing.h" - -#include "fpga_x2p_backannotate_utils.h" - -/* Get initial value of a Latch/FF output*/ -int get_ff_output_init_val(t_logical_block* ff_logical_block) { - assert((0 == ff_logical_block->init_val)||(1 == ff_logical_block->init_val)); - - return ff_logical_block->init_val; -} - -static -int determine_rr_node_default_prev_node(t_rr_node* cur_rr_node) { - int default_prev_node = DEFAULT_PREV_NODE; - - /* Judge if the prev_node should be */ - if ((NULL != switch_inf[cur_rr_node->driver_switch].spice_model) - && (TRUE == switch_inf[cur_rr_node->driver_switch].spice_model->design_tech_info.mux_info->add_const_input)) { - default_prev_node = OPEN; /* The constant input will be the last input!!! */ - } - - return default_prev_node; -} - -/* Get initial value of a mapped LUT output*/ -int get_lut_output_init_val(t_logical_block* lut_logical_block) { - int i; - int* sram_bits = NULL; /* decoded SRAM bits */ - int truth_table_length = 0; - char** truth_table = NULL; - int lut_size = 0; - int input_net_index = OPEN; - int* input_init_val = NULL; - int init_path_id = 0; - int output_init_val = 0; - - t_spice_model* lut_spice_model = NULL; - int num_sram_port = 0; - t_spice_model_port** sram_ports = NULL; - - /* Ensure a valid file handler*/ - if (NULL == lut_logical_block) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid LUT logical block!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Get SPICE model */ - assert((NULL != lut_logical_block->pb) - && ( NULL != lut_logical_block->pb->pb_graph_node) - && ( NULL != lut_logical_block->pb->pb_graph_node->pb_type)); - lut_spice_model = lut_logical_block->pb->pb_graph_node->pb_type->parent_mode->parent_pb_type->phy_pb_type->spice_model; - - assert(SPICE_MODEL_LUT == lut_spice_model->type); - - sram_ports = find_spice_model_ports(lut_spice_model, SPICE_MODEL_PORT_SRAM, - &num_sram_port, TRUE); - assert((1 == num_sram_port) || (2 == num_sram_port)); - - /* Get the truth table */ - truth_table = assign_lut_truth_table(lut_logical_block, &truth_table_length); - lut_size = lut_logical_block->used_input_pins; - assert(!(0 > lut_size)); - /* Special for LUT_size = 0 */ - if (0 == lut_size) { - /* Generate sram bits*/ - sram_bits = generate_lut_sram_bits(truth_table_length, truth_table, - 1, sram_ports[0]->default_val); - /* This is constant generator, SRAM bits should be the same */ - output_init_val = sram_bits[0]; - for (i = 0; i < (int)pow(2.,(double)lut_size); i++) { - assert(sram_bits[i] == output_init_val); - } - } else { - /* Generate sram bits*/ - sram_bits = generate_lut_sram_bits(truth_table_length, truth_table, - lut_size, sram_ports[0]->default_val); - - assert(1 == lut_logical_block->pb->pb_graph_node->num_input_ports); - assert(1 == lut_logical_block->pb->pb_graph_node->num_output_ports); - /* Get the initial path id */ - input_init_val = (int*)my_malloc(sizeof(int)*lut_size); - for (i = 0; i < lut_size; i++) { - input_net_index = lut_logical_block->input_nets[0][i]; - input_init_val[i] = vpack_net[input_net_index].spice_net_info->init_val; - if ((1 != input_init_val[i]) && (0 != input_init_val[i])) { - assert ((1 == input_init_val[i]) || (0 == input_init_val[i])); - } - } - - init_path_id = determine_lut_path_id(lut_size, input_init_val); - /* Check */ - assert((!(0 > init_path_id))&&(init_path_id < (int)pow(2.,(double)lut_size))); - output_init_val = sram_bits[init_path_id]; - } - - /* Check */ - if ((1 != output_init_val) && (0 != output_init_val)) { - assert ((1 == output_init_val) || (0 == output_init_val)); - } - - /*Free*/ - for (i = 0; i < truth_table_length; i++) { - free(truth_table[i]); - } - free(truth_table); - my_free(sram_bits); - my_free(input_init_val); - - return output_init_val; -} - -/* Deteremine the initial value of an output of a logical block - * The logical block could be a LUT, a memory block or a multiplier - */ -int get_logical_block_output_init_val(t_logical_block* cur_logical_block) { - int output_init_val = 0; - t_spice_model* cur_spice_model = NULL; - - /* Get the spice_model of current logical_block */ - assert((NULL != cur_logical_block->pb) - && ( NULL != cur_logical_block->pb->pb_graph_node) - && ( NULL != cur_logical_block->pb->pb_graph_node->pb_type)); - - /* We only care LUT here, for other blocks we cannot force now, for others, we just give zero. */ - if (0 == strcmp(cur_logical_block->model->name, BLIF_LUT_KEYWORD)) { - cur_spice_model = cur_logical_block->pb->pb_graph_node->pb_type->parent_mode->parent_pb_type->phy_pb_type->spice_model; - } else { - return get_ff_output_init_val(cur_logical_block); - } - - /* Switch to specific cases*/ - switch (cur_spice_model->type) { - case SPICE_MODEL_LUT: - /* Determine the initial value from LUT inputs */ - output_init_val = get_lut_output_init_val(cur_logical_block); - break; - case SPICE_MODEL_HARDLOGIC: - /* We have no information, give a default 0 now... - * TODO: find a smarter way! - */ - output_init_val = get_ff_output_init_val(cur_logical_block); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SPICE MODEL (name=%s) in determining the initial output value of logical block(name=%s)!\n", - __FILE__, __LINE__, cur_spice_model->name, cur_logical_block->name); - exit(1); - } - - return output_init_val; -} - - -/* Alloc, initialize and free functions for sb_info & cb_info */ -/* Initialize a SB_info */ -void init_one_sb_info(t_sb* cur_sb) { - cur_sb->x = -1; /* give an invalid value, which means OPEN */ - cur_sb->y = -1; /* give an invalid value, which means OPEN */ - cur_sb->directionality = UNI_DIRECTIONAL; - cur_sb->fs = -1; /* give an invalid value, which means OPEN */ - cur_sb->fc_out = -1; /* give an invalid value, which means OPEN */ - cur_sb->num_sides = 4; /* Should be fixed to 4 */ - cur_sb->chan_width = NULL; - cur_sb->num_ipin_rr_nodes = NULL; - cur_sb->num_opin_rr_nodes = NULL; - cur_sb->chan_rr_node = NULL; - cur_sb->chan_rr_node_direction = NULL; - cur_sb->ipin_rr_node = NULL; - cur_sb->ipin_rr_node_grid_side = NULL; - cur_sb->opin_rr_node = NULL; - cur_sb->opin_rr_node_grid_side = NULL; - cur_sb->num_reserved_conf_bits = 0; - cur_sb->conf_bits_lsb = 0; - cur_sb->conf_bits_msb = 0; - - cur_sb->mirror = NULL; - cur_sb->rotatable = NULL; - cur_sb->offset_ipin = NULL; - cur_sb->offset_opin = NULL; - cur_sb->offset_chan = NULL; - - return; -} - -/* Free everything (lists) inside a sb_info */ -void free_one_sb_info(t_sb* cur_sb) { - int i; - - if ((-1 == cur_sb->x)||(-1 == cur_sb->y)) { - /*NULL struct: bypass free */ - return; - } - - /* Free chan_width, input/output_rr_nodes, rr_nodes */ - my_free(cur_sb->chan_width); - for (i = 0; i < cur_sb->num_sides; i++) { - my_free(cur_sb->chan_rr_node_direction[i]); - my_free(cur_sb->chan_rr_node[i]); - my_free(cur_sb->ipin_rr_node[i]); - my_free(cur_sb->ipin_rr_node_grid_side[i]); - my_free(cur_sb->opin_rr_node[i]); - my_free(cur_sb->opin_rr_node_grid_side[i]); - } - my_free(cur_sb->num_ipin_rr_nodes); - my_free(cur_sb->num_opin_rr_nodes); - my_free(cur_sb->chan_rr_node_direction); - my_free(cur_sb->chan_rr_node); - my_free(cur_sb->ipin_rr_node); - my_free(cur_sb->ipin_rr_node_grid_side); - my_free(cur_sb->opin_rr_node); - my_free(cur_sb->opin_rr_node_grid_side); - - my_free(cur_sb->offset_ipin); - my_free(cur_sb->offset_opin); - my_free(cur_sb->offset_chan); - - return; -} - -/* Alloc sb_info */ -t_sb** alloc_sb_info_array(int LL_nx, int LL_ny) { - int ix, iy; - t_sb** LL_sb_info = NULL; - - /* Allocate a two-dimension array for sb_info */ - LL_sb_info = (t_sb**)my_malloc(sizeof(t_sb*) * (LL_nx+1)); /* [0 ... nx] */ - for (ix = 0; ix < (LL_nx + 1); ix++) { - LL_sb_info[ix] = (t_sb*)my_malloc(sizeof(t_sb) * (LL_ny+1)); /* [0 ... ny] */ - for (iy = 0; iy < (LL_ny + 1); iy++) { - init_one_sb_info(&(LL_sb_info[ix][iy])); /* Initialize to NULL pointer */ - } - } - - return LL_sb_info; -} - -/* Free an sb_info_array */ -void free_sb_info_array(t_sb*** LL_sb_info, int LL_nx, int LL_ny) { - int ix, iy; - - if (NULL == (*LL_sb_info)) { - return; - } - - for (ix = 0; ix < (LL_nx + 1); ix++) { - for (iy = 0; iy < (LL_ny + 1); iy++) { - free_one_sb_info(&((*LL_sb_info)[ix][iy])); - } - my_free((*LL_sb_info)[ix]); - (*LL_sb_info)[ix] = NULL; - } - - (*LL_sb_info) = NULL; - - return; -} - -/* Initialize a CB_info */ -void init_one_cb_info(t_cb* cur_cb) { - cur_cb->x = -1; /* give an invalid value, which means OPEN */ - cur_cb->y = -1; /* give an invalid value, which means OPEN */ - cur_cb->type = NUM_RR_TYPES; - cur_cb->directionality = UNI_DIRECTIONAL; - cur_cb->fc_in = -1; /* give an invalid value, which means OPEN */ - cur_cb->num_sides = 4; /* Should be fixed to 4 */ - cur_cb->chan_width = NULL; - cur_cb->num_ipin_rr_nodes = NULL; - cur_cb->num_opin_rr_nodes = NULL; - cur_cb->chan_rr_node = NULL; - cur_cb->chan_rr_node_direction = NULL; - cur_cb->ipin_rr_node = NULL; - cur_cb->ipin_rr_node_grid_side = NULL; - cur_cb->opin_rr_node = NULL; - cur_cb->opin_rr_node_grid_side = NULL; - cur_cb->num_reserved_conf_bits = 0; - cur_cb->conf_bits_lsb = 0; - cur_cb->conf_bits_msb = 0; - - cur_cb->mirror = NULL; - cur_cb->rotatable = NULL; - cur_cb->offset_ipin = NULL; - cur_cb->offset_opin = NULL; - cur_cb->offset_chan = NULL; - - return; -} - -/* Free everything (lists) inside a sb_info */ -void free_one_cb_info(t_cb* cur_cb) { - int i; - - if ((-1 == cur_cb->x)||(-1 == cur_cb->y)) { - /*NULL struct: bypass free */ - return; - } - - /* Free chan_width, input/output_rr_nodes, rr_nodes */ - my_free(cur_cb->chan_width); - for (i = 0; i < cur_cb->num_sides; i++) { - my_free(cur_cb->chan_rr_node[i]); - my_free(cur_cb->chan_rr_node_direction[i]); - my_free(cur_cb->ipin_rr_node[i]); - my_free(cur_cb->ipin_rr_node_grid_side[i]); - my_free(cur_cb->opin_rr_node[i]); - my_free(cur_cb->opin_rr_node_grid_side[i]); - } - my_free(cur_cb->chan_rr_node); - my_free(cur_cb->num_ipin_rr_nodes); - my_free(cur_cb->num_opin_rr_nodes); - my_free(cur_cb->chan_rr_node_direction); - my_free(cur_cb->ipin_rr_node); - my_free(cur_cb->ipin_rr_node_grid_side); - my_free(cur_cb->opin_rr_node); - my_free(cur_cb->opin_rr_node_grid_side); - - my_free(cur_cb->offset_ipin); - my_free(cur_cb->offset_opin); - my_free(cur_cb->offset_chan); - - return; -} - -/* Alloc cb_info: need to call this function twice for X-channel and Y-channel */ -t_cb** alloc_cb_info_array(int LL_nx, int LL_ny) { - int ix, iy; - t_cb** LL_cb_info = NULL; - - /* Allocate a two-dimension array for cb_info */ - LL_cb_info = (t_cb**)my_malloc(sizeof(t_cb*) * (LL_nx+1)); /* [0 ... nx] */ - for (ix = 0; ix < (LL_nx + 1); ix++) { - LL_cb_info[ix] = (t_cb*)my_malloc(sizeof(t_cb) * (LL_ny+1)); /* [0 ... ny] */ - for (iy = 0; iy < (LL_ny + 1); iy++) { - init_one_cb_info(&(LL_cb_info[ix][iy])); /* Initialize to NULL pointer */ - } - } - - return LL_cb_info; -} - -/* Free an sb_info_array */ -void free_cb_info_array(t_cb*** LL_cb_info, int LL_nx, int LL_ny) { - int ix, iy; - - if (NULL == (*LL_cb_info)) { - return; - } - - for (ix = 0; ix < (LL_nx + 1); ix++) { - for (iy = 0; iy < (LL_ny + 1); iy++) { - free_one_cb_info(&((*LL_cb_info)[ix][iy])); - } - my_free((*LL_cb_info)[ix]); - (*LL_cb_info)[ix] = NULL; - } - - (*LL_cb_info) = NULL; - - return; -} - -/* Get the index of a given rr_node in a SB_info */ -int get_rr_node_index_in_sb_info(t_rr_node* cur_rr_node, - t_sb cur_sb_info, - int chan_side, enum PORTS rr_node_direction) { - int inode, cnt, ret; - - cnt = 0; - ret = OPEN; - - /* Depending on the type of rr_node, we search different arrays */ - switch (cur_rr_node->type) { - case CHANX: - case CHANY: - for (inode = 0; inode < cur_sb_info.chan_width[chan_side]; inode++) { - if ((cur_rr_node == cur_sb_info.chan_rr_node[chan_side][inode]) - /* Check if direction meets specification */ - &&(rr_node_direction == cur_sb_info.chan_rr_node_direction[chan_side][inode])) { - cnt++; - ret = inode; - } - } - break; - case IPIN: - for (inode = 0; inode < cur_sb_info.num_ipin_rr_nodes[chan_side]; inode++) { - if (cur_rr_node == cur_sb_info.ipin_rr_node[chan_side][inode]) { - cnt++; - ret = inode; - } - } - break; - case OPIN: - for (inode = 0; inode < cur_sb_info.num_opin_rr_nodes[chan_side]; inode++) { - if (cur_rr_node == cur_sb_info.opin_rr_node[chan_side][inode]) { - cnt++; - ret = inode; - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid cur_rr_node type! Should be [CHANX|CHANY|IPIN|OPIN]\n", __FILE__, __LINE__); - exit(1); - } - - assert((0 == cnt)||(1 == cnt)); - - return ret; /* Return an invalid value: nonthing is found*/ -} - -/* Check if the src_rr_node is just a wire crossing this switch box - * --------- - * | | - * ------------------> - * | | - * --------- - * Strategy: - * Check each driver rr_node of this src_rr_node, - * see if they are in the opin_rr_node, chan_rr_node lists of sb_rr_info - */ -int is_rr_node_exist_opposite_side_in_sb_info(t_sb cur_sb_info, - t_rr_node* src_rr_node, - int chan_side) { - int oppo_chan_side = -1; - int interc, index; - - assert((CHANX == src_rr_node->type) || (CHANY == src_rr_node->type)); - - oppo_chan_side = get_opposite_side(chan_side); - - /* See if we can find the same src_rr_node in the opposite chan_side - * if there is one, it means a shorted wire across the SB - */ - index = get_rr_node_index_in_sb_info(src_rr_node, cur_sb_info, oppo_chan_side, IN_PORT); - - interc = 0; - if (-1 != index) { - interc = 1; - } - - return interc; -} - - -/* Get the side and index of a given rr_node in a SB_info - * Return cur_rr_node_side & cur_rr_node_index - */ -void get_rr_node_side_and_index_in_sb_info(t_rr_node* cur_rr_node, - t_sb cur_sb_info, - enum PORTS rr_node_direction, - OUTP int* cur_rr_node_side, - OUTP int* cur_rr_node_index) { - int index, side; - - /* Count the number of existence of cur_rr_node in cur_sb_info - * It could happen that same cur_rr_node appears on different sides of a SB - * For example, a routing track go vertically across the SB. - * Then its corresponding rr_node appears on both TOP and BOTTOM sides of this SB. - * We need to ensure that the found rr_node has the same direction as user want. - * By specifying the direction of rr_node, There should be only one rr_node can satisfy! - */ - index = -1; - - for (side = 0; side < cur_sb_info.num_sides; side++) { - index = get_rr_node_index_in_sb_info(cur_rr_node, cur_sb_info, side, rr_node_direction); - if (-1 != index) { - break; - } - } - - if (side == cur_sb_info.num_sides) { - /* we find nothing */ - side = -1; - } - - (*cur_rr_node_side) = side; - (*cur_rr_node_index) = index; - - return; -} - -/* Check if the drivers for cur_rr_node imply a short connection in this Switch block - */ -boolean check_drive_rr_node_imply_short(t_sb cur_sb_info, - t_rr_node* src_rr_node, - int chan_side) { - int inode, index, side; - - assert((CHANX == src_rr_node->type) || (CHANY == src_rr_node->type)); - - for (inode = 0; inode < src_rr_node->num_drive_rr_nodes; inode++) { - get_rr_node_side_and_index_in_sb_info(src_rr_node->drive_rr_nodes[inode], cur_sb_info, IN_PORT, &side, &index); - /* We need to be sure that drive_rr_node is part of the SB */ - if (((-1 == index)||(-1 == side)) - && ((CHANX == src_rr_node->drive_rr_nodes[inode]->type)||(CHANY == src_rr_node->drive_rr_nodes[inode]->type))) { - return TRUE; - } - } - - return FALSE; -} - - -/* Get the index of a given rr_node in a CB_info */ -int get_rr_node_index_in_cb_info(t_rr_node* cur_rr_node, - t_cb cur_cb_info, - int chan_side, enum PORTS rr_node_direction) { - int inode, cnt, ret; - - cnt = 0; - ret = -1; - - /* Depending on the type of rr_node, we search different arrays */ - switch (cur_rr_node->type) { - case CHANX: - case CHANY: - for (inode = 0; inode < cur_cb_info.chan_width[chan_side]; inode++) { - if ((cur_rr_node == cur_cb_info.chan_rr_node[chan_side][inode]) - /* Check if direction meets specification */ - &&(rr_node_direction == cur_cb_info.chan_rr_node_direction[chan_side][inode])) { - cnt++; - ret = inode; - } - } - break; - case IPIN: - for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[chan_side]; inode++) { - if (cur_rr_node == cur_cb_info.ipin_rr_node[chan_side][inode]) { - cnt++; - ret = inode; - } - } - break; - case OPIN: - for (inode = 0; inode < cur_cb_info.num_opin_rr_nodes[chan_side]; inode++) { - if (cur_rr_node == cur_cb_info.opin_rr_node[chan_side][inode]) { - cnt++; - ret = inode; - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid cur_rr_node type! Should be [CHANX|CHANY|IPIN|OPIN]\n", __FILE__, __LINE__); - exit(1); - } - - assert((0 == cnt)||(1 == cnt)); - - return ret; /* Return an invalid value: nonthing is found*/ -} - -/* Determine the coordinate of a chan_rr_node in a SB_info - * Return chan_type & chan_rr_node_x & chan_rr_node_y - */ -void get_chan_rr_node_coordinate_in_sb_info(t_sb cur_sb_info, - int chan_rr_node_side, - t_rr_type* chan_type, - int* chan_rr_node_x, int* chan_rr_node_y) { - int sb_x = cur_sb_info.x; - int sb_y = cur_sb_info.y; - - switch (chan_rr_node_side) { - case 0: /*TOP*/ - (*chan_type) = CHANY; - (*chan_rr_node_x) = sb_x; - (*chan_rr_node_y) = sb_y + 1; - break; - case 1: /*RIGHT*/ - (*chan_type) = CHANX; - (*chan_rr_node_x) = sb_x + 1; - (*chan_rr_node_y) = sb_y; - break; - case 2: /*BOTTOM*/ - (*chan_type) = CHANY; - (*chan_rr_node_x) = sb_x; - (*chan_rr_node_y) = sb_y; - break; - case 3: /*LEFT*/ - (*chan_type) = CHANX; - (*chan_rr_node_x) = sb_x; - (*chan_rr_node_y) = sb_y; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid side!\n", __FILE__, __LINE__); - exit(1); - } - - return; -} - -/* Get the side and index of a given rr_node in a SB_info - * Return cur_rr_node_side & cur_rr_node_index - */ -void get_rr_node_side_and_index_in_cb_info(t_rr_node* cur_rr_node, - t_cb cur_cb_info, - enum PORTS rr_node_direction, - OUTP int* cur_rr_node_side, - OUTP int* cur_rr_node_index) { - int index, side; - - index = -1; - - for (side = 0; side < cur_cb_info.num_sides; side++) { - index = get_rr_node_index_in_cb_info(cur_rr_node, cur_cb_info, side, rr_node_direction); - if (-1 != index) { - break; - } - } - - if (side == cur_cb_info.num_sides) { - /* we find nothing */ - side = -1; - } - - (*cur_rr_node_side) = side; - (*cur_rr_node_index) = index; - - return; -} - - -/***** Recursively Backannotate parasitic_net_num for a rr_node*****/ -static -void rec_backannotate_rr_node_net_num(int LL_num_rr_nodes, - t_rr_node* LL_rr_node, - int src_node_index) { - int iedge, to_node; - - /* Traversal until - * 1. we meet a sink - * 2. None of the edges propagates this net_num - */ - for (iedge = 0; iedge < LL_rr_node[src_node_index].num_edges; iedge++) { - to_node = LL_rr_node[src_node_index].edges[iedge]; - /* assert(OPEN != LL_rr_node[to_node].prev_node); */ - if (src_node_index == LL_rr_node[to_node].prev_node) { - assert(iedge == LL_rr_node[to_node].prev_edge); - /* assert(LL_rr_node[src_node_index].net_num == LL_rr_node[to_node].net_num); */ - /* Label parasitic net */ - if ((OPEN == LL_rr_node[to_node].net_num) - && (OPEN != LL_rr_node[src_node_index].net_num)) { - LL_rr_node[to_node].is_parasitic_net = TRUE; - } - /* Propagate the net_num */ - LL_rr_node[to_node].net_num = LL_rr_node[src_node_index].net_num; - /* Make the flag which indicates a changing has been made */ - if (LL_rr_node[to_node].vpack_net_num != LL_rr_node[src_node_index].vpack_net_num) { - LL_rr_node[to_node].vpack_net_num_changed = TRUE; - } - LL_rr_node[to_node].vpack_net_num = LL_rr_node[src_node_index].vpack_net_num; - /* Go recursively */ - rec_backannotate_rr_node_net_num(LL_num_rr_nodes, LL_rr_node, to_node); - } - } - - return; -} - -/***** Backannotate activity information to nets *****/ -/* Mark mapped rr_nodes with net_num*/ -static -void backannotate_rr_nodes_parasitic_net_info() { - int inode; - - /* Start from all the SOURCEs */ - for (inode = 0; inode < num_rr_nodes; inode++) { - /* We care only OPINs - * or a contant generator */ - if ((OPIN != rr_node[inode].type) - || (!(SOURCE != rr_node[inode].type) - && (0 == rr_node[inode].num_drive_rr_nodes))) { - continue; - } - /* Bypass unmapped pins */ - if (OPEN == rr_node[inode].vpack_net_num) { - continue; - } - /* Forward to all the downstream rr_nodes */ - rec_backannotate_rr_node_net_num(num_rr_nodes, rr_node, inode); - } - - return; -} - -static -void backannotate_clb_nets_init_val() { - int inet, iblk, isink; - int iter_cnt, iter_end; - - /* Analysis init values !!! */ - for (inet = 0; inet < num_logical_nets; inet++) { - assert (NULL != vpack_net[inet].spice_net_info); - /* if the source is a inpad or dff, we update the initial value */ - iblk = vpack_net[inet].node_block[0]; - switch (logical_block[iblk].type) { - case VPACK_INPAD: - logical_block[iblk].init_val = vpack_net[inet].spice_net_info->init_val; - assert((0 == logical_block[iblk].init_val)||(1 == logical_block[iblk].init_val)); - break; - case VPACK_LATCH: - vpack_net[inet].spice_net_info->init_val = 0; - /*TODO:may be more flexible, for ff, set or reset may be used in first cock cycle */ - logical_block[iblk].init_val = vpack_net[inet].spice_net_info->init_val; - assert((0 == logical_block[iblk].init_val)||(1 == logical_block[iblk].init_val)); - break; - case VPACK_OUTPAD: - case VPACK_COMB: - case VPACK_EMPTY: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid logical block type!\n", - __FILE__, __LINE__); - exit(1); - } - } - /* Iteratively Update LUT init_val */ - iter_cnt = 0; - while(1) { - iter_end = 1; - for (inet = 0; inet < num_logical_nets; inet++) { - assert(NULL != vpack_net[inet].spice_net_info); - /* if the source is a inpad or dff, we update the initial value */ - iblk = vpack_net[inet].node_block[0]; - switch (logical_block[iblk].type) { - case VPACK_COMB: - vpack_net[inet].spice_net_info->init_val = get_logical_block_output_init_val(&(logical_block[iblk])); - if (logical_block[iblk].init_val != vpack_net[inet].spice_net_info->init_val) { - iter_end = 0; - } - logical_block[iblk].init_val = vpack_net[inet].spice_net_info->init_val; - break; - case VPACK_INPAD: - case VPACK_LATCH: - case VPACK_OUTPAD: - case VPACK_EMPTY: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid logical block type!\n", - __FILE__, __LINE__); - exit(1); - } - } - iter_cnt++; - if (1 == iter_end) { - break; - } - } - vpr_printf(TIO_MESSAGE_INFO,"Determine LUTs initial outputs ends in %d iterations.\n", iter_cnt); - /* Update OUTPAD init_val */ - for (inet = 0; inet < num_logical_nets; inet++) { - assert(NULL != vpack_net[inet].spice_net_info); - /* if the source is a inpad or dff, we update the initial value */ - for (isink = 0; isink < vpack_net[inet].num_sinks; isink++) { - iblk = vpack_net[inet].node_block[isink]; - switch (logical_block[iblk].type) { - case VPACK_OUTPAD: - logical_block[iblk].init_val = vpack_net[inet].spice_net_info->init_val; - break; - case VPACK_COMB: - case VPACK_INPAD: - case VPACK_LATCH: - case VPACK_EMPTY: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid logical block type!\n", - __FILE__, __LINE__); - exit(1); - } - } - } - - /* Initial values for clb nets !!! */ - for (inet = 0; inet < num_nets; inet++) { - assert (NULL != clb_net[inet].spice_net_info); - /* if the source is a inpad or dff, we update the initial value */ - clb_net[inet].spice_net_info->init_val = vpack_net[clb_to_vpack_net_mapping[inet]].spice_net_info->init_val; - } - - return; -} - -static -void backannotate_clb_nets_act_info() { - int inet; - - /* Free all spice_net_info and reallocate */ - for (inet = 0; inet < num_logical_nets; inet++) { - if (NULL == vpack_net[inet].spice_net_info) { - /* Allocate */ - vpack_net[inet].spice_net_info = (t_spice_net_info*)my_calloc(1, sizeof(t_spice_net_info)); - } - /* Initialize to zero */ - init_spice_net_info(vpack_net[inet].spice_net_info); - /* Load activity info */ - vpack_net[inet].spice_net_info->probability = vpack_net[inet].net_power->probability; - vpack_net[inet].spice_net_info->density = vpack_net[inet].net_power->density; - /* SPECIAL for SPICE simulator: init_value is opposite to probability - * when density is not zero. - */ - /* - if (0. != vpack_net[inet].spice_net_info->density) { - vpack_net[inet].spice_net_info->init_val = 1 - vpack_net[inet].spice_net_info->probability; - } - */ - } - - /* Free all spice_net_info and reallocate */ - for (inet = 0; inet < num_nets; inet++) { - if (NULL == clb_net[inet].spice_net_info) { - /* Allocate */ - clb_net[inet].spice_net_info = (t_spice_net_info*)my_calloc(1, sizeof(t_spice_net_info)); - } - /* Initialize to zero */ - init_spice_net_info(clb_net[inet].spice_net_info); - /* Load activity info */ - clb_net[inet].spice_net_info->probability = vpack_net[clb_to_vpack_net_mapping[inet]].spice_net_info->probability; - clb_net[inet].spice_net_info->density = vpack_net[clb_to_vpack_net_mapping[inet]].spice_net_info->density; - clb_net[inet].spice_net_info->init_val = vpack_net[clb_to_vpack_net_mapping[inet]].spice_net_info->init_val; - } - - return; -} - -void free_clb_nets_spice_net_info() { - int inet; - - /* Free all spice_net_info and reallocate */ - for (inet = 0; inet < num_nets; inet++) { - my_free(clb_net[inet].spice_net_info); - } - - for (inet = 0; inet < num_logical_nets; inet++) { - my_free(vpack_net[inet].spice_net_info); - } - - return; -} - -static -void set_one_pb_rr_node_default_prev_node_edge(t_rr_node* pb_rr_graph, - t_pb_graph_pin* des_pb_graph_pin, - int mode_index) { - int iedge, node_index, prev_node, prev_edge; - - assert(NULL != des_pb_graph_pin); - assert(NULL != pb_rr_graph); - - node_index = des_pb_graph_pin->pin_count_in_cluster; - assert(OPEN == pb_rr_graph[node_index].net_num); - - /* if this pin has 0 driver, return OPEN */ - if (0 == des_pb_graph_pin->num_input_edges) { - pb_rr_graph[node_index].prev_node = OPEN; - pb_rr_graph[node_index].prev_edge = OPEN; - return; - } - - prev_node = OPEN; - prev_edge = OPEN; - - /* Set default prev_node */ - for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - if (mode_index != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode_index) { - continue; - } - prev_node = des_pb_graph_pin->input_edges[iedge]->input_pins[0]->pin_count_in_cluster; - break; - } - - /* prev_node may not exist since some pb_graph_pin is accessible in some mode, we do not need to find a prev_edge */ - if (OPEN == prev_node) { - /* backannotate */ - pb_rr_graph[node_index].prev_node = prev_node; - pb_rr_graph[node_index].prev_edge = prev_edge; - return; - } - - /* Find prev_edge */ - for (iedge = 0; iedge < pb_rr_graph[prev_node].pb_graph_pin->num_output_edges; iedge++) { - check_pb_graph_edge(*(pb_rr_graph[prev_node].pb_graph_pin->output_edges[iedge])); - if (node_index == pb_rr_graph[prev_node].pb_graph_pin->output_edges[iedge]->output_pins[0]->pin_count_in_cluster) { - prev_edge = iedge; - break; - } - } - /* Make sure we succeed */ - assert(OPEN != prev_node); - assert(OPEN != prev_edge); - /* backannotate */ - pb_rr_graph[node_index].prev_node = prev_node; - pb_rr_graph[node_index].prev_edge = prev_edge; - - return; -} - -/* Mark the prev_edge and prev_node of all the rr_nodes in complex blocks */ -static -void back_annotate_one_pb_rr_node_map_info_rec(t_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - t_rr_node* pb_rr_nodes) { - int imode, ipb, jpb, select_mode_index; - int iport, ipin, node_index; - t_pb_graph_node* child_pb_graph_node; - t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; - - /* Return when we meet a null pb */ - if (NULL == cur_pb) { - /* Wired LUT does not has a pb but has a net_num */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - node_index = cur_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; - if (OPEN != pb_rr_nodes[node_index].net_num) { - pb_rr_nodes[node_index].vpack_net_num = pb_rr_nodes[node_index].net_num; - } - } - } - - /* Wired LUT does not has a pb but has a net_num */ - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - node_index = cur_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; - if (OPEN != pb_rr_nodes[node_index].net_num) { - pb_rr_nodes[node_index].vpack_net_num = pb_rr_nodes[node_index].net_num; - } - } - } - /* Return if this is a leaf node */ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - return; - } - - /* Go recusrively */ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[imode].pb_type_children[ipb].num_pb; jpb++) { - /* For wired LUT */ - if (FALSE == is_pb_used_for_wiring(&(cur_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), - &(cur_pb_graph_node->pb_type->modes[imode].pb_type_children[ipb]), - pb_rr_nodes)) { - continue; - } - /* Reach here means that this LUT is in wired mode (a buffer) - * synchronize the net num - */ - back_annotate_one_pb_rr_node_map_info_rec(NULL, - &(cur_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), - pb_rr_nodes); - } - } - } - - return; - } - - /* For all the input/output/clock pins of this pb, - * check the net_num and assign default prev_node, prev_edge - */ - - /* We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins - * /|\ - * | - * input_pins, edges, output_pins - */ - select_mode_index = cur_pb->mode; - for (iport = 0; iport < cur_pb->pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb->pb_graph_node->num_output_pins[iport]; ipin++) { - /* Get the selected edge of current pin*/ - node_index = cur_pb->pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; - /* If we find an OPEN net, try to find the parasitic net_num*/ - if (OPEN == pb_rr_nodes[node_index].net_num) { - set_one_pb_rr_node_default_prev_node_edge(pb_rr_nodes, - &(cur_pb->pb_graph_node->output_pins[iport][ipin]), - select_mode_index); - } else { - pb_rr_nodes[node_index].vpack_net_num = pb_rr_nodes[node_index].net_num; - } - } - } - - /* Reach a leaf, return */ - if ((0 == cur_pb->pb_graph_node->pb_type->num_modes) - ||(NULL == cur_pb->child_pbs)) { - return; - } - - /* We check input_pins of child_pb_graph_node and its the input_edges - * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node - * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins - * /|\ - * | - * input_pins, edges, output_pins - */ - select_mode_index = cur_pb->mode; - for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { - child_pb_graph_node = &(cur_pb->pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]); - /* For each child_pb_graph_node input pins*/ - for (iport = 0; iport < child_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ipin++) { - /* Get the selected edge of current pin*/ - node_index = child_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; - /* If we find an OPEN net, try to find the parasitic net_num*/ - if (OPEN == pb_rr_nodes[node_index].net_num) { - set_one_pb_rr_node_default_prev_node_edge(pb_rr_nodes, - &(child_pb_graph_node->input_pins[iport][ipin]), - select_mode_index); - } else { - pb_rr_nodes[node_index].vpack_net_num = pb_rr_nodes[node_index].net_num; - } - } - } - /* For each child_pb_graph_node clock pins*/ - for (iport = 0; iport < child_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ipin++) { - /* Get the selected edge of current pin*/ - node_index = child_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster; - /* If we find an OPEN net, try to find the parasitic net_num*/ - if (OPEN == pb_rr_nodes[node_index].net_num) { - set_one_pb_rr_node_default_prev_node_edge(pb_rr_nodes, - &(child_pb_graph_node->clock_pins[iport][ipin]), - select_mode_index); - } else { - pb_rr_nodes[node_index].vpack_net_num = pb_rr_nodes[node_index].net_num; - } - } - } - } - } - - /* Go recursively */ - for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - back_annotate_one_pb_rr_node_map_info_rec(&(cur_pb->child_pbs[ipb][jpb]), - &(cur_pb->pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]), - cur_pb->rr_graph); - } else if (TRUE == is_pb_used_for_wiring(&(cur_pb->pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]), - &(cur_pb->pb_graph_node->pb_type->modes[select_mode_index].pb_type_children[ipb]), - cur_pb->rr_graph)) { - /* For wired LUT */ - /* Reach here means that this LUT is in wired mode (a buffer) - * synchronize the net num - */ - back_annotate_one_pb_rr_node_map_info_rec(NULL, - &(cur_pb->pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]), - cur_pb->rr_graph); - } - } - } - - return; -} - -/* Mark all prev_node & prev_edge for pb_rr_nodes */ -static -void back_annotate_pb_rr_node_map_info() { - int iblk; - - /* Foreach grid */ - for (iblk = 0; iblk < num_blocks; iblk++) { - /* By pass IO */ - if (IO_TYPE == block[iblk].type) { - continue; - } - back_annotate_one_pb_rr_node_map_info_rec(block[iblk].pb, - block[iblk].pb->pb_graph_node, - block[iblk].pb->rr_graph); - } - - return; -} - -/* Set the net_num for one pb_rr_node according to prev_node */ -static -void set_one_pb_rr_node_net_num(t_rr_node* pb_rr_graph, - t_pb_graph_pin* des_pb_graph_pin) { - - int node_index, prev_node, prev_edge; - - assert(NULL != des_pb_graph_pin); - assert(NULL != pb_rr_graph); - - node_index = des_pb_graph_pin->rr_node_index_physical_pb; - assert(OPEN == pb_rr_graph[node_index].net_num); - - /* if this pin has 0 driver, return OPEN */ - if (0 == des_pb_graph_pin->num_input_edges) { - pb_rr_graph[node_index].net_num= OPEN; - pb_rr_graph[node_index].vpack_net_num= OPEN; - return; - } - - prev_node = pb_rr_graph[node_index].prev_node; - prev_edge = pb_rr_graph[node_index].prev_edge; - - /* Some node may be disconnected */ - if (OPEN == prev_node) { - pb_rr_graph[node_index].net_num = OPEN; - pb_rr_graph[node_index].vpack_net_num = OPEN; - return; - } - - assert(OPEN != prev_node); - assert(OPEN != prev_edge); - - /* Set default prev_node */ - check_pb_graph_edge(*(pb_rr_graph[prev_node].pb_graph_pin->output_edges[prev_edge])); - assert(node_index == pb_rr_graph[prev_node].pb_graph_pin->output_edges[prev_edge]->output_pins[0]->rr_node_index_physical_pb); - pb_rr_graph[node_index].net_num = pb_rr_graph[prev_node].net_num; - pb_rr_graph[node_index].vpack_net_num = pb_rr_graph[prev_node].net_num; - - return; -} - -/* Mark the net_num of all the rr_nodes in complex blocks */ -static -void backannotate_one_pb_rr_nodes_net_info_rec(t_phy_pb* cur_pb) { - int ipb, jpb, select_mode_index; - int iport, ipin, node_index; - t_rr_node* pb_rr_nodes = NULL; - t_pb_graph_node* child_pb_graph_node = NULL; - - /* Return when we meet a null pb */ - assert (NULL != cur_pb); - - /* Reach a leaf, return */ - if ((0 == cur_pb->pb_graph_node->pb_type->num_modes) - ||(NULL == cur_pb->child_pbs)) { - return; - } - - select_mode_index = cur_pb->mode; - - /* For all the input/output/clock pins of this pb, - * check the net_num and assign default prev_node, prev_edge - */ - - /* We check input_pins of child_pb_graph_node and its the input_edges - * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node - * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins - * /|\ - * | - * input_pins, edges, output_pins - */ - for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { - child_pb_graph_node = &(cur_pb->pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]); - /* For each child_pb_graph_node input pins*/ - for (iport = 0; iport < child_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < child_pb_graph_node->num_input_pins[iport]; ipin++) { - /* Get the selected edge of current pin*/ - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = child_pb_graph_node->input_pins[iport][ipin].rr_node_index_physical_pb; - /* If we find an OPEN net, try to find the parasitic net_num*/ - if (OPEN == pb_rr_nodes[node_index].net_num) { - set_one_pb_rr_node_net_num(pb_rr_nodes, &(child_pb_graph_node->input_pins[iport][ipin])); - /* Label this net as parasitic net */ - pb_rr_nodes[node_index].is_parasitic_net = TRUE; - } - } - } - /* For each child_pb_graph_node clock pins*/ - for (iport = 0; iport < child_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < child_pb_graph_node->num_clock_pins[iport]; ipin++) { - /* Get the selected edge of current pin*/ - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = child_pb_graph_node->clock_pins[iport][ipin].rr_node_index_physical_pb; - /* If we find an OPEN net, try to find the parasitic net_num*/ - if (OPEN == pb_rr_nodes[node_index].net_num) { - set_one_pb_rr_node_net_num(pb_rr_nodes, &(child_pb_graph_node->clock_pins[iport][ipin])); - /* Label this net as parasitic net */ - pb_rr_nodes[node_index].is_parasitic_net = TRUE; - } - } - } - } - } - - /* Go recursively, prior to update the output pins. - * Because output pins are depend on the deepest pbs - */ - for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - backannotate_one_pb_rr_nodes_net_info_rec(&(cur_pb->child_pbs[ipb][jpb])); - } - } - } - - /* We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins - * /|\ - * | - * input_pins, edges, output_pins - */ - for (iport = 0; iport < cur_pb->pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb->pb_graph_node->num_output_pins[iport]; ipin++) { - /* Get the selected edge of current pin*/ - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = cur_pb->pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; - /* If we find an OPEN net, try to find the parasitic net_num*/ - if (OPEN == pb_rr_nodes[node_index].net_num) { - set_one_pb_rr_node_net_num(pb_rr_nodes, &(cur_pb->pb_graph_node->output_pins[iport][ipin])); - /* Label this net as parasitic net */ - pb_rr_nodes[node_index].is_parasitic_net = TRUE; - } - } - } - - return; -} - -static -void backannotate_pb_rr_nodes_net_info() { - int iblk; - - /* Foreach grid */ - for (iblk = 0; iblk < num_blocks; iblk++) { - /* By pass IO */ - if (IO_TYPE == block[iblk].type) { - continue; - } - backannotate_one_pb_rr_nodes_net_info_rec((t_phy_pb*)block[iblk].phy_pb); - } - - return; -} - -/* Mark the prev_edge and prev_node of all the rr_nodes in global routing */ -static -void back_annotate_rr_node_map_info() { - int inode, jnode, inet, default_prev_node; - int next_node, iedge; - t_trace* tptr; - t_rr_type rr_type; - - /* 1st step: Set all the configurations to default. - * rr_nodes select edge[0] - */ - for (inode = 0; inode < num_rr_nodes; inode++) { - rr_node[inode].prev_node = OPEN; - /* set 0 if we want print all unused mux!!!*/ - rr_node[inode].prev_edge = OPEN; - /* Initial all the net_num*/ - rr_node[inode].net_num = OPEN; - rr_node[inode].vpack_net_num = OPEN; - } - for (inode = 0; inode < num_rr_nodes; inode++) { - if (0 == rr_node[inode].num_edges) { - continue; - } - assert(0 < rr_node[inode].num_edges); - for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { - jnode = rr_node[inode].edges[iedge]; - default_prev_node = determine_rr_node_default_prev_node(&rr_node[jnode]); - if (DEFAULT_PREV_NODE == default_prev_node) { - rr_node[jnode].prev_node = default_prev_node; - } else if (&(rr_node[inode]) == rr_node[jnode].drive_rr_nodes[default_prev_node]) { - rr_node[jnode].prev_node = inode; - rr_node[jnode].prev_edge = iedge; - } - } - } - - /* 2nd step: With the help of trace, we back-annotate */ - for (inet = 0; inet < num_nets; inet++) { - if (TRUE == clb_net[inet].is_global) { - continue; - } - tptr = trace_head[inet]; - while (tptr != NULL) { - inode = tptr->index; - rr_type = rr_node[inode].type; - /* Net num */ - rr_node[inode].net_num = inet; - rr_node[inode].vpack_net_num = clb_to_vpack_net_mapping[inet]; - //printf("Mark rr_node net_num for vpack_net(name=%s)..\n", - // vpack_net[rr_node[inode].vpack_net_num].name); - assert(OPEN != rr_node[inode].net_num); - assert(OPEN != rr_node[inode].vpack_net_num); - switch (rr_type) { - case SINK: - /* Nothing should be done. This supposed to the end of a trace*/ - break; - case IPIN: - case CHANX: - case CHANY: - case OPIN: - case SOURCE: - /* SINK(IO/Pad) is the end of a routing path. Should configure its prev_edge and prev_node*/ - /* We care the next rr_node, this one is driving, which we have to configure - */ - assert(NULL != tptr->next); - next_node = tptr->next->index; - assert((!(0 > next_node))&&(next_node < num_rr_nodes)); - /* Prev_node */ - rr_node[next_node].prev_node = inode; - /* Prev_edge */ - rr_node[next_node].prev_edge = OPEN; - for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { - if (next_node == rr_node[inode].edges[iedge]) { - rr_node[next_node].prev_edge = iedge; - break; - } - } - assert(OPEN != rr_node[next_node].prev_edge); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid traceback element type.\n", - __FILE__, __LINE__); - exit(1); - } - tptr = tptr->next; - } - } - - return; -} - -static -void rec_sync_pb_post_routing_vpack_net_num(t_pb* cur_pb) { - int ipb, jpb, select_mode_index; - int iport, ipin, node_index; - t_rr_node* pb_rr_nodes = NULL; - - /* Return when we meet a null pb */ - if (NULL == cur_pb) { - return; - } - - /* For all the input/output/clock pins of this pb, - * check the net_num and assign default prev_node, prev_edge - */ - - /* We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins - * /|\ - * | - * input_pins, edges, output_pins - */ - select_mode_index = cur_pb->mode; - for (iport = 0; iport < cur_pb->pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb->pb_graph_node->num_input_pins[iport]; ipin++) { - /* Get the selected edge of current pin*/ - pb_rr_nodes = cur_pb->rr_graph; - node_index = cur_pb->pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; - pb_rr_nodes[node_index].vpack_net_num = pb_rr_nodes[node_index].net_num; - } - } - - for (iport = 0; iport < cur_pb->pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb->pb_graph_node->num_output_pins[iport]; ipin++) { - /* Get the selected edge of current pin*/ - pb_rr_nodes = cur_pb->rr_graph; - node_index = cur_pb->pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; - pb_rr_nodes[node_index].vpack_net_num = pb_rr_nodes[node_index].net_num; - } - } - - for (iport = 0; iport < cur_pb->pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb->pb_graph_node->num_clock_pins[iport]; ipin++) { - /* Get the selected edge of current pin*/ - pb_rr_nodes = cur_pb->rr_graph; - node_index = cur_pb->pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster; - pb_rr_nodes[node_index].vpack_net_num = pb_rr_nodes[node_index].net_num; - } - } - - /* Reach a leaf, return */ - if ((0 == cur_pb->pb_graph_node->pb_type->num_modes) - ||(NULL == cur_pb->child_pbs)) { - return; - } - - /* Go recursively */ - for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - rec_sync_pb_post_routing_vpack_net_num(&(cur_pb->child_pbs[ipb][jpb])); - } - } - } - return; -} - -/* IO blocks are special: - * each pb only contain 1 pb_graph_node (1 io) - * while the top-level type_descriptor consider 8 io in counting the pins - * so we just update the vpack_net_num and net_num in all the hierachy level - */ -static -void update_one_io_grid_pack_net_num(int x, int y) { - int iblk, blk_id; - t_type_ptr type = NULL; - t_pb* pb = NULL; - - /* Assert */ - assert((!(x < 0))&&(x < (nx + 2))); - assert((!(y < 0))&&(y < (ny + 2))); - - type = grid[x][y].type; - /* check */ - assert (IO_TYPE == type); - - for (iblk = 0; iblk < grid[x][y].usage; iblk++) { - blk_id = grid[x][y].blocks[iblk]; - if ((IO_TYPE != type)) { - assert(block[blk_id].x == x); - assert(block[blk_id].y == y); - assert(OPEN != blk_id); - } - pb = block[blk_id].pb; - assert(NULL != pb); - rec_sync_pb_post_routing_vpack_net_num(pb); - } - - return; -} - - -/* During routing stage, VPR swap logic equivalent pins - * which potentially changes the packing results (net_num and vpack_net_num) in local routing - * The following functions are to update the local routing results to match them with routing results - */ -static -void update_one_grid_pack_net_num(int x, int y) { - int iblk, blk_id, ipin, iedge, jedge, inode; - int pin_global_rr_node_id, vpack_net_id, class_id; - t_type_ptr type = NULL; - t_pb* pb = NULL; - t_rr_node* local_rr_graph = NULL; - - /* Assert */ - assert((!(x < 0))&&(x < (nx + 2))); - assert((!(y < 0))&&(y < (ny + 2))); - - type = grid[x][y].type; - - /* check */ - assert ((NULL != type) - && (EMPTY_TYPE != type) - && (IO_TYPE != type)); - /* Bypass grids whose offset is larger than 0 ! They have been processed! */ - if (0 < grid[x][y].offset) { - return; - } - - for (iblk = 0; iblk < grid[x][y].usage; iblk++) { - blk_id = grid[x][y].blocks[iblk]; - pb = block[blk_id].pb; - assert(NULL != pb); - local_rr_graph = pb->rr_graph; - /* Foreach local rr_node*/ - for (ipin = 0; ipin < type->num_pins; ipin++) { - class_id = type->pin_class[ipin]; - if (DRIVER == type->class_inf[class_id].type) { - /* Find the pb net_num and update OPIN net_num */ - pin_global_rr_node_id = get_rr_node_index(x, y, OPIN, ipin, rr_node_indices); - if (OPEN == rr_node[pin_global_rr_node_id].net_num) { - if ( (OPEN != local_rr_graph[ipin].net_num) - && (TRUE == vpack_net[local_rr_graph[ipin].net_num].is_global)) { - local_rr_graph[ipin].net_num_in_pack = local_rr_graph[ipin].net_num; - local_rr_graph[ipin].vpack_net_num = local_rr_graph[ipin].net_num; - local_rr_graph[ipin].net_num = vpack_to_clb_net_mapping[local_rr_graph[ipin].net_num]; - } else { - local_rr_graph[ipin].net_num_in_pack = local_rr_graph[ipin].net_num; - local_rr_graph[ipin].net_num = OPEN; - local_rr_graph[ipin].vpack_net_num = OPEN; - //local_rr_graph[ipin].prev_node = 0; - //local_rr_graph[ipin].prev_edge = 0; - } - continue; /* bypass non-mapped OPIN */ - } - /* back annotate pb ! */ - rr_node[pin_global_rr_node_id].pb = pb; - vpack_net_id = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; - assert(ipin == local_rr_graph[ipin].pb_graph_pin->pin_count_in_cluster); - /* Update net_num */ - local_rr_graph[ipin].net_num_in_pack = local_rr_graph[ipin].net_num; - local_rr_graph[ipin].net_num = vpack_net_id; - local_rr_graph[ipin].vpack_net_num = vpack_net_id; - /* TODO: this is not so efficient... */ - for (iedge = 0; iedge < local_rr_graph[ipin].pb_graph_pin->num_input_edges; iedge++) { - check_pb_graph_edge(*(local_rr_graph[ipin].pb_graph_pin->input_edges[iedge])); - inode = local_rr_graph[ipin].pb_graph_pin->input_edges[iedge]->input_pins[0]->pin_count_in_cluster; - /* Update prev_node, prev_edge if needed*/ - if (vpack_net_id == local_rr_graph[inode].net_num) { - /* Backup prev_node, prev_edge */ - backup_one_pb_rr_node_pack_prev_node_edge(&(local_rr_graph[ipin])); - local_rr_graph[ipin].prev_node = inode; - for (jedge = 0; jedge < local_rr_graph[inode].pb_graph_pin->num_output_edges; jedge++) { - if (local_rr_graph[ipin].pb_graph_pin == local_rr_graph[inode].pb_graph_pin->output_edges[jedge]->output_pins[0]) { - local_rr_graph[ipin].prev_edge = jedge; - break; - } - } - break; - } - } - } else if (RECEIVER == type->class_inf[class_id].type) { - /* Find the global rr_node net_num and update pb net_num */ - pin_global_rr_node_id = get_rr_node_index(x, y, IPIN, ipin, rr_node_indices); - /* Special for global net, preserve them in the local rr_graph */ - /* Get the index of Vpack net from global rr_node net_num (clb_net index)*/ - if (OPEN == rr_node[pin_global_rr_node_id].net_num) { - if ( (OPEN != local_rr_graph[ipin].net_num) - && (TRUE == vpack_net[local_rr_graph[ipin].net_num].is_global)) { - local_rr_graph[ipin].net_num_in_pack = local_rr_graph[ipin].net_num; - local_rr_graph[ipin].vpack_net_num = local_rr_graph[ipin].net_num; - local_rr_graph[ipin].net_num = vpack_to_clb_net_mapping[local_rr_graph[ipin].net_num]; - } else { - local_rr_graph[ipin].net_num_in_pack = local_rr_graph[ipin].net_num; - local_rr_graph[ipin].net_num = OPEN; - local_rr_graph[ipin].vpack_net_num = OPEN; - //local_rr_graph[ipin].prev_node = 0; - //local_rr_graph[ipin].prev_edge = 0; - } - continue; /* bypass non-mapped IPIN */ - } - /* back annotate pb ! */ - rr_node[pin_global_rr_node_id].pb = pb; - vpack_net_id = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; - assert(ipin == local_rr_graph[ipin].pb_graph_pin->pin_count_in_cluster); - /* Update net_num */ - local_rr_graph[ipin].net_num_in_pack = local_rr_graph[ipin].net_num; - local_rr_graph[ipin].net_num = vpack_net_id; - local_rr_graph[ipin].vpack_net_num = vpack_net_id; - /* TODO: this is not so efficient... */ - for (iedge = 0; iedge < local_rr_graph[ipin].pb_graph_pin->num_output_edges; iedge++) { - check_pb_graph_edge(*(local_rr_graph[ipin].pb_graph_pin->output_edges[iedge])); - inode = local_rr_graph[ipin].pb_graph_pin->output_edges[iedge]->output_pins[0]->pin_count_in_cluster; - /* Update prev_node, prev_edge if needed*/ - if (vpack_net_id == local_rr_graph[inode].net_num) { - /* Backup prev_node, prev_edge */ - backup_one_pb_rr_node_pack_prev_node_edge(&(local_rr_graph[inode])); - local_rr_graph[inode].prev_node = ipin; - local_rr_graph[inode].prev_edge = iedge; - } - } - } else { - continue; /* OPEN PIN */ - } - } - } - - return; -} - -void update_grid_pbs_post_route_rr_graph() { - int ix, iy; - t_type_ptr type = NULL; - - for (ix = 0; ix < (nx + 2); ix++) { - for (iy = 0; iy < (ny + 2); iy++) { - type = grid[ix][iy].type; - /* bypass EMPTY type */ - if ((NULL == type) || (EMPTY_TYPE == type)) { - continue; - } - if (IO_TYPE == type) { - update_one_io_grid_pack_net_num(ix, iy); - } else { - /* Backup the packing prev_node and prev_edge */ - update_one_grid_pack_net_num(ix, iy); - } - } - } - - return; -} - -/* In this function, we update the vpack_net_num in global rr_graph - * from the temp_net_num stored in the top_pb_graph_head - */ -static -void update_one_unused_grid_output_pins_parasitic_nets(int ix, int iy) { - int iport, ipin; - int pin_global_rr_node_id, class_id, type_pin_index; - t_type_ptr type = NULL; - t_pb_graph_node* top_pb_graph_node = NULL; - - /* Assert */ - assert((!(ix < 0))&&(ix < (nx + 2))); - assert((!(iy < 0))&&(iy < (ny + 2))); - - type = grid[ix][iy].type; - /* Bypass IO_TYPE*/ - if ((EMPTY_TYPE == type)||(IO_TYPE == type)) { - return; - } - - /* Use the temp_net_num of each pb_graph_pin at the top-level - * Update the global rr_graph - */ - top_pb_graph_node = type->pb_graph_head; - assert(NULL != top_pb_graph_node); - - /* We only care the outputs, since the inputs are updated in function - * mark_grid_type_pb_graph_node_pins_temp_net_num(ix, iy); - */ - for (iport = 0; iport < top_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ipin++) { - top_pb_graph_node->output_pins[iport][ipin].temp_net_num = OPEN; - type_pin_index = top_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; - class_id = type->pin_class[type_pin_index]; - assert(DRIVER == type->class_inf[class_id].type); - /* Find the pb net_num and update OPIN net_num */ - pin_global_rr_node_id = get_rr_node_index(ix, iy, OPIN, type_pin_index, rr_node_indices); - /* Avoid mistakenly overwrite */ - if (OPEN != rr_node[pin_global_rr_node_id].vpack_net_num) { - continue; - } - rr_node[pin_global_rr_node_id].vpack_net_num = top_pb_graph_node->output_pins[iport][ipin].temp_net_num; - } - } - - return; -} - - -/* SPEICAL: to assign parasitic nets, I modify the net_num in global - * global routing nets to be vpack_net_num. The reason is some vpack nets - * are absorbed into CLBs during packing, therefore they are invisible in - * clb_nets. But indeed, they exist in global routing as parasitic nets. - */ -static -void update_one_used_grid_pb_pins_parasitic_nets(t_phy_pb* cur_pb, - int ix, int iy) { - int ipin, cur_pin; - int pin_global_rr_node_id,class_id; - t_type_ptr type = NULL; - t_rr_node* local_rr_graph = NULL; - - /* Assert */ - assert((!(ix < 0))&&(ix < (nx + 2))); - assert((!(iy < 0))&&(iy < (ny + 2))); - - type = grid[ix][iy].type; - /* Bypass IO_TYPE*/ - if ((EMPTY_TYPE == type)||(IO_TYPE == type)) { - return; - } - - assert(NULL != cur_pb); - local_rr_graph = cur_pb->rr_graph->rr_node; - for (ipin = 0; ipin < type->num_pins; ipin++) { - class_id = type->pin_class[ipin]; - if (DRIVER == type->class_inf[class_id].type) { - /* Find the pb net_num and update OPIN net_num */ - pin_global_rr_node_id = get_rr_node_index(ix, iy, OPIN, ipin, rr_node_indices); - if (OPEN == local_rr_graph[ipin].net_num) { - assert(OPEN == local_rr_graph[ipin].vpack_net_num); - rr_node[pin_global_rr_node_id].net_num = OPEN; - rr_node[pin_global_rr_node_id].vpack_net_num = OPEN; - continue; /* bypass non-mapped OPIN */ - } - cur_pin = local_rr_graph[ipin].pb_graph_pin->rr_node_index_physical_pb; - //rr_node[pin_global_rr_node_id].net_num = vpack_to_clb_net_mapping[local_rr_graph[ipin].net_num]; - rr_node[pin_global_rr_node_id].vpack_net_num = local_rr_graph[cur_pin].vpack_net_num; - if ( (OPEN == rr_node[pin_global_rr_node_id].vpack_net_num) - && (OPEN != local_rr_graph[cur_pin].vpack_net_num)) { - /* Label this net as parasitic net */ - rr_node[pin_global_rr_node_id].is_parasitic_net = TRUE; - } - } else if (RECEIVER == type->class_inf[class_id].type) { - /* Find the global rr_node net_num and update pb net_num */ - pin_global_rr_node_id = get_rr_node_index(ix, iy, IPIN, ipin, rr_node_indices); - /* Get the index of Vpack net from global rr_node net_num (clb_net index)*/ - if (OPEN == rr_node[pin_global_rr_node_id].vpack_net_num) { - local_rr_graph[ipin].net_num = OPEN; - local_rr_graph[ipin].vpack_net_num = OPEN; - continue; /* bypass non-mapped IPIN */ - } - cur_pin = local_rr_graph[ipin].pb_graph_pin->rr_node_index_physical_pb; - local_rr_graph[cur_pin].net_num = rr_node[pin_global_rr_node_id].vpack_net_num; - local_rr_graph[cur_pin].vpack_net_num = rr_node[pin_global_rr_node_id].vpack_net_num; - if ( (OPEN == local_rr_graph[cur_pin].vpack_net_num) - && (OPEN == rr_node[pin_global_rr_node_id].vpack_net_num)) { - /* Label this net as parasitic net */ - local_rr_graph[cur_pin].is_parasitic_net = TRUE; - } - } else { - continue; /* OPEN PIN */ - } - } - - return; -} - - -static -void update_one_grid_pb_pins_parasitic_nets(int ix, int iy) { - int iblk; - - /* Print all the grid */ - if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)) { - return; - } - /* Used blocks */ - for (iblk = 0; iblk < grid[ix][iy].usage; iblk++) { - /* Only for mapped block */ - assert(NULL != block[grid[ix][iy].blocks[iblk]].pb); - /* Mark the temporary net_num for the type pins*/ - mark_one_pb_parasitic_nets((t_phy_pb*)block[grid[ix][iy].blocks[iblk]].phy_pb); - /* Update parasitic nets */ - update_one_used_grid_pb_pins_parasitic_nets((t_phy_pb*)block[grid[ix][iy].blocks[iblk]].phy_pb, - ix, iy); - /* update parasitic nets in each pb */ - backannotate_one_pb_rr_nodes_net_info_rec((t_phy_pb*)block[grid[ix][iy].blocks[iblk]].phy_pb); - } - /* By pass Unused blocks */ - for (iblk = grid[ix][iy].usage; iblk < grid[ix][iy].type->capacity; iblk++) { - /* Mark the temporary net_num for the type pins*/ - mark_grid_type_pb_graph_node_pins_temp_net_num(ix, iy); - /* Update parasitic nets */ - update_one_unused_grid_output_pins_parasitic_nets(ix, iy); - } - - return; -} - -static -void update_grid_pb_pins_parasitic_nets() { - int ix, iy; - t_type_ptr type = NULL; - - for (ix = 0; ix < (nx + 2); ix++) { - for (iy = 0; iy < (ny + 2); iy++) { - type = grid[ix][iy].type; - if ((EMPTY_TYPE == type)||(IO_TYPE == type)) { - continue; - } - /* Backup the packing prev_node and prev_edge */ - update_one_grid_pb_pins_parasitic_nets(ix, iy); - } - } - - return; -} - -/* Update the driver switch for each rr_node*/ -static -void identify_rr_node_driver_switch(t_det_routing_arch RoutingArch, - int LL_num_rr_nodes, - t_rr_node* LL_rr_node) { - int inode, iedge; - - /* Current Version: Support Uni-directional routing architecture only*/ - if (UNI_DIRECTIONAL != RoutingArch.directionality) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Assign rr_node driver switch only support uni-directional routing architecture.\n",__FILE__, __LINE__); - exit(1); - } - - /* I can do a simple job here: - * just assign driver_switch from drive_switches[0] - * which has been done in backannotation_vpr_post_route_info - */ - /* update_rr_nodes_driver_switch(routing_arch->directionality); */ - for (inode = 0; inode < LL_num_rr_nodes; inode++) { - if (0 == LL_rr_node[inode].fan_in) { - assert(0 == LL_rr_node[inode].num_drive_rr_nodes); - assert(NULL == LL_rr_node[inode].drive_switches); - continue; - } - LL_rr_node[inode].driver_switch = LL_rr_node[inode].drive_switches[0]; - for (iedge = 0; iedge < LL_rr_node[inode].num_drive_rr_nodes; iedge++) { - if (LL_rr_node[inode].driver_switch != LL_rr_node[inode].drive_switches[iedge]) - assert (LL_rr_node[inode].driver_switch == LL_rr_node[inode].drive_switches[iedge]); - } - } - - return; -} - -/* Find all the rr_nodes of a channel - * Return an array of rr_node pointers, and length of the array (num_pin_rr_nodes) - */ -t_rr_node** get_chan_rr_nodes(int* num_chan_rr_nodes, - t_rr_type chan_type, - int x, int y, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { - int itrack, inode; - t_rr_node** chan_rr_nodes = NULL; - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - - switch (chan_type) { - case CHANX: - /* Get the channel width */ - (*num_chan_rr_nodes) = chan_width_x[y]; - /* Allocate */ - chan_rr_nodes = (t_rr_node**)my_malloc((*num_chan_rr_nodes)*sizeof(t_rr_node*)); - /* Fill the array */ - for (itrack = 0; itrack < (*num_chan_rr_nodes); itrack++) { - /* CHANX follows a weird way in searching rr_nodes */ - inode = get_rr_node_index(x, y, CHANX, itrack, LL_rr_node_indices); - chan_rr_nodes[itrack] = &(LL_rr_node[inode]); - } - break; - case CHANY: - /* Get the channel width */ - (*num_chan_rr_nodes) = chan_width_y[x]; - /* Allocate */ - chan_rr_nodes = (t_rr_node**)my_malloc((*num_chan_rr_nodes)*sizeof(t_rr_node*)); - /* Fill the array */ - for (itrack = 0; itrack < (*num_chan_rr_nodes); itrack++) { - inode = get_rr_node_index(x, y, CHANY, itrack, LL_rr_node_indices); - chan_rr_nodes[itrack] = &(LL_rr_node[inode]); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - - return chan_rr_nodes; -} - - -/* Find all the rr_nodes at a certain side of a grid - * Return an array of rr_node pointers, and length of the array (num_pin_rr_nodes) - */ -t_rr_node** get_grid_side_pin_rr_nodes(int* num_pin_rr_nodes, - t_rr_type pin_type, - int x, int y, int side, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { - int height, ipin, class_id, inode; - t_type_ptr type = NULL; - t_rr_node** ret = NULL; - enum e_pin_type pin_class_type; - int cur; - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - type = grid[x][y].type; - assert(NULL != type); - /* Assign the type of PIN*/ - switch (pin_type) { - case IPIN: - /* case SINK: */ - pin_class_type = RECEIVER; /* This is the end of a route path*/ - break; - /*case SOURCE:*/ - case OPIN: - pin_class_type = DRIVER; /* This is the start of a route path */ - break; - /* SINK and SOURCE are hypothesis nodes */ - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid pin_type!\n", __FILE__, __LINE__); - exit(1); - } - - /* Output the pins on the side*/ - (*num_pin_rr_nodes) = 0; - height = grid[x][y].offset; - for (ipin = 0; ipin < type->num_pins; ipin++) { - class_id = type->pin_class[ipin]; - if ((1 == type->pinloc[height][side][ipin])&&(pin_class_type == type->class_inf[class_id].type)) { - (*num_pin_rr_nodes)++; - } - } - /* Malloc */ - ret = (t_rr_node**)my_malloc(sizeof(t_rr_node*)*(*num_pin_rr_nodes)); - - /* Fill the return array*/ - cur = 0; - height = grid[x][y].offset; - for (ipin = 0; ipin < type->num_pins; ipin++) { - class_id = type->pin_class[ipin]; - if ((1 == type->pinloc[height][side][ipin])&&(pin_class_type == type->class_inf[class_id].type)) { - inode = get_rr_node_index(x, y, pin_type, ipin, LL_rr_node_indices); - ret[cur] = &(LL_rr_node[inode]); - cur++; - } - } - assert(cur == (*num_pin_rr_nodes)); - - return ret; -} - -/* Build arrays for rr_nodes of each Switch Blocks - * A Switch Box subckt consists of following ports: - * 1. Channel Y [x][y] inputs - * 2. Channel X [x+1][y] inputs - * 3. Channel Y [x][y-1] outputs - * 4. Channel X [x][y] outputs - * 5. Grid[x][y+1] Right side outputs pins - * 6. Grid[x+1][y+1] Left side output pins - * 7. Grid[x+1][y+1] Bottom side output pins - * 8. Grid[x+1][y] Top side output pins - * 9. Grid[x+1][y] Left side output pins - * 10. Grid[x][y] Right side output pins - * 11. Grid[x][y] Top side output pins - * 12. Grid[x][y+1] Bottom side output pins - * - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - * For channels chanY with INC_DIRECTION on the top side, they should be marked as outputs - * For channels chanY with DEC_DIRECTION on the top side, they should be marked as inputs - * For channels chanY with INC_DIRECTION on the bottom side, they should be marked as inputs - * For channels chanY with DEC_DIRECTION on the bottom side, they should be marked as outputs - * For channels chanX with INC_DIRECTION on the left side, they should be marked as inputs - * For channels chanX with DEC_DIRECTION on the left side, they should be marked as outputs - * For channels chanX with INC_DIRECTION on the right side, they should be marked as outputs - * For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs - */ -void build_one_switch_block_info(t_sb* cur_sb, int sb_x, int sb_y, - t_det_routing_arch RoutingArch, - int LL_num_rr_nodes, - t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { - int itrack, inode, side, ix, iy; - int temp_num_opin_rr_nodes[2] = {0,0}; - t_rr_node** temp_opin_rr_node[2] = {NULL, NULL}; - - /* Check */ - assert((!(0 > sb_x))&&(!(sb_x > (nx + 1)))); - assert((!(0 > sb_y))&&(!(sb_y > (ny + 1)))); - - /* Basic information*/ - cur_sb->x = sb_x; - cur_sb->y = sb_y; - cur_sb->directionality = RoutingArch.directionality; /* Could be more flexible, Currently we only support uni-directionalal routing architecture. */ - cur_sb->fs = RoutingArch.Fs; - cur_sb->num_sides = 4; /* Fixed */ - - /* Record the channel width of each side*/ - cur_sb->chan_width = (int*)my_calloc(cur_sb->num_sides, sizeof(int)); /* 4 sides */ - cur_sb->chan_rr_node_direction = (enum PORTS**)my_malloc(sizeof(enum PORTS*)*cur_sb->num_sides); /* 4 sides */ - cur_sb->chan_rr_node = (t_rr_node***)my_malloc(sizeof(t_rr_node**)*cur_sb->num_sides); /* 4 sides*/ - cur_sb->num_ipin_rr_nodes = (int*)my_calloc(cur_sb->num_sides, sizeof(int)); /* 4 sides */ - cur_sb->ipin_rr_node = (t_rr_node***)my_malloc(sizeof(t_rr_node**)*cur_sb->num_sides); /* 4 sides */ - cur_sb->ipin_rr_node_grid_side = (int**)my_malloc(sizeof(int*)*cur_sb->num_sides); /* 4 sides */ - cur_sb->num_opin_rr_nodes = (int*)my_calloc(cur_sb->num_sides, sizeof(int)); /* 4 sides */ - cur_sb->opin_rr_node = (t_rr_node***)my_malloc(sizeof(t_rr_node**)*cur_sb->num_sides); /* 4 sides */ - cur_sb->opin_rr_node_grid_side = (int**)my_malloc(sizeof(int*)*cur_sb->num_sides); /* 4 sides */ - - /* Find all rr_nodes of channels */ - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - for (side = 0; side < 4; side++) { - switch (side) { - case 0: - /* For the bording, we should take special care */ - if (sb_y == ny) { - cur_sb->chan_width[side] = 0; - cur_sb->chan_rr_node[side] = NULL; - cur_sb->chan_rr_node_direction[side] = NULL; - cur_sb->num_ipin_rr_nodes[side] = 0; - cur_sb->ipin_rr_node[side] = NULL; - cur_sb->ipin_rr_node_grid_side[side] = NULL; - cur_sb->num_opin_rr_nodes[side] = 0; - cur_sb->opin_rr_node[side] = NULL; - cur_sb->opin_rr_node_grid_side[side] = NULL; - break; - } - /* Routing channels*/ - ix = sb_x; - iy = sb_y + 1; - /* Channel width */ - cur_sb->chan_width[side] = chan_width_y[ix]; - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - cur_sb->chan_rr_node[side] = get_chan_rr_nodes(&(cur_sb->chan_width[side]), CHANY, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* Alloc */ - cur_sb->chan_rr_node_direction[side] = (enum PORTS*)my_malloc(sizeof(enum PORTS)*cur_sb->chan_width[side]); - /* Collect rr_nodes for Tracks for top: chany[x][y+1] */ - for (itrack = 0; itrack < cur_sb->chan_width[side]; itrack++) { - /* Identify the directionality, record it in rr_node_direction */ - if (INC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction) { - cur_sb->chan_rr_node_direction[side][itrack] = OUT_PORT; - } else { - assert (DEC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction); - cur_sb->chan_rr_node_direction[side][itrack] = IN_PORT; - } - } - /* Include Grid[x][y+1] RIGHT side outputs pins */ - temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], - OPIN, sb_x, sb_y + 1, 1, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* Include Grid[x+1][y+1] Left side output pins */ - temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], - OPIN, sb_x + 1, sb_y + 1, 3, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* Allocate opin_rr_node */ - cur_sb->num_opin_rr_nodes[side] = temp_num_opin_rr_nodes[0] + temp_num_opin_rr_nodes[1]; - cur_sb->opin_rr_node[side] = (t_rr_node**)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(t_rr_node*)); - cur_sb->opin_rr_node_grid_side[side] = (int*)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(int)); - /* Copy from temp_opin_rr_node to opin_rr_node */ - for (inode = 0; inode < temp_num_opin_rr_nodes[0]; inode++) { - cur_sb->opin_rr_node[side][inode] = temp_opin_rr_node[0][inode]; - cur_sb->opin_rr_node_grid_side[side][inode] = 1; /* Grid[x][y+1] RIGHT side outputs pins */ - } - for (inode = 0; inode < temp_num_opin_rr_nodes[1]; inode++) { - cur_sb->opin_rr_node[side][inode + temp_num_opin_rr_nodes[0]] = temp_opin_rr_node[1][inode]; - cur_sb->opin_rr_node_grid_side[side][inode + temp_num_opin_rr_nodes[0]] = 3; /* Grid[x+1][y+1] left side outputs pins */ - } - /* We do not have any IPIN for a Switch Block */ - cur_sb->num_ipin_rr_nodes[side] = 0; - cur_sb->ipin_rr_node[side] = NULL; - cur_sb->ipin_rr_node_grid_side[side] = NULL; - break; - case 1: - /* For the bording, we should take special care */ - if (sb_x == nx) { - cur_sb->chan_width[side] = 0; - cur_sb->chan_rr_node[side] = NULL; - cur_sb->chan_rr_node_direction[side] = NULL; - cur_sb->num_ipin_rr_nodes[side] = 0; - cur_sb->ipin_rr_node[side] = NULL; - cur_sb->ipin_rr_node_grid_side[side] = NULL; - cur_sb->num_opin_rr_nodes[side] = 0; - cur_sb->opin_rr_node[side] = NULL; - cur_sb->opin_rr_node_grid_side[side] = NULL; - break; - } - /* Routing channels*/ - ix = sb_x + 1; - iy = sb_y; - /* Channel width */ - cur_sb->chan_width[side] = chan_width_x[iy]; - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Alloc */ - cur_sb->chan_rr_node[side] = get_chan_rr_nodes(&(cur_sb->chan_width[side]), CHANX, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - cur_sb->chan_rr_node_direction[side] = (enum PORTS*)my_malloc(sizeof(enum PORTS)*cur_sb->chan_width[side]); - /* Collect rr_nodes for Tracks for right: chanX[x+1][y] */ - for (itrack = 0; itrack < cur_sb->chan_width[side]; itrack++) { - /* Identify the directionality, record it in rr_node_direction */ - if (INC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction) { - cur_sb->chan_rr_node_direction[side][itrack] = OUT_PORT; - } else { - assert (DEC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction); - cur_sb->chan_rr_node_direction[side][itrack] = IN_PORT; - } - } - /* include Grid[x+1][y+1] Bottom side output pins */ - temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], - OPIN, sb_x + 1, sb_y + 1, 2, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* include Grid[x+1][y] Top side output pins */ - temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], - OPIN, sb_x + 1, sb_y, 0, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* Allocate opin_rr_node */ - cur_sb->num_opin_rr_nodes[side] = temp_num_opin_rr_nodes[0] + temp_num_opin_rr_nodes[1]; - cur_sb->opin_rr_node[side] = (t_rr_node**)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(t_rr_node*)); - cur_sb->opin_rr_node_grid_side[side] = (int*)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(int)); - /* Copy from temp_opin_rr_node to opin_rr_node */ - for (inode = 0; inode < temp_num_opin_rr_nodes[0]; inode++) { - cur_sb->opin_rr_node[side][inode] = temp_opin_rr_node[0][inode]; - cur_sb->opin_rr_node_grid_side[side][inode] = 2; /* Grid[x+1][y+1] Bottom side outputs pins */ - } - for (inode = 0; inode < temp_num_opin_rr_nodes[1]; inode++) { - cur_sb->opin_rr_node[side][inode + temp_num_opin_rr_nodes[0]] = temp_opin_rr_node[1][inode]; - cur_sb->opin_rr_node_grid_side[side][inode + temp_num_opin_rr_nodes[0]] = 0; /* Grid[x+1][y] TOP side outputs pins */ - } - /* We do not have any IPIN for a Switch Block */ - cur_sb->num_ipin_rr_nodes[side] = 0; - cur_sb->ipin_rr_node[side] = NULL; - cur_sb->ipin_rr_node_grid_side[side] = NULL; - break; - case 2: - /* For the bording, we should take special care */ - if (sb_y == 0) { - cur_sb->chan_width[side] = 0; - cur_sb->chan_rr_node[side] = NULL; - cur_sb->chan_rr_node_direction[side] = NULL; - cur_sb->num_ipin_rr_nodes[side] = 0; - cur_sb->ipin_rr_node[side] = NULL; - cur_sb->ipin_rr_node_grid_side[side] = NULL; - cur_sb->num_opin_rr_nodes[side] = 0; - cur_sb->opin_rr_node[side] = NULL; - cur_sb->opin_rr_node_grid_side[side] = NULL; - break; - } - /* Routing channels*/ - ix = sb_x; - iy = sb_y; - /* Channel width */ - cur_sb->chan_width[side] = chan_width_y[ix]; - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Alloc */ - cur_sb->chan_rr_node[side] = get_chan_rr_nodes(&(cur_sb->chan_width[side]), CHANY, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - cur_sb->chan_rr_node_direction[side] = (enum PORTS*)my_malloc(sizeof(enum PORTS)*cur_sb->chan_width[side]); - /* Collect rr_nodes for Tracks for bottom: chany[x][y] */ - for (itrack = 0; itrack < cur_sb->chan_width[side]; itrack++) { - /* Identify the directionality, record it in rr_node_direction */ - if (DEC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction) { - cur_sb->chan_rr_node_direction[side][itrack] = OUT_PORT; - } else { - assert (INC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction); - cur_sb->chan_rr_node_direction[side][itrack] = IN_PORT; - } - } - /* TODO: include Grid[x+1][y] Left side output pins */ - temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], - OPIN, sb_x + 1, sb_y, 3, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* TODO: include Grid[x][y] Right side output pins */ - temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], - OPIN, sb_x, sb_y, 1, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* Allocate opin_rr_node */ - cur_sb->num_opin_rr_nodes[side] = temp_num_opin_rr_nodes[0] + temp_num_opin_rr_nodes[1]; - cur_sb->opin_rr_node[side] = (t_rr_node**)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(t_rr_node*)); - cur_sb->opin_rr_node_grid_side[side] = (int*)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(int)); - /* Copy from temp_opin_rr_node to opin_rr_node */ - for (inode = 0; inode < temp_num_opin_rr_nodes[0]; inode++) { - cur_sb->opin_rr_node[side][inode] = temp_opin_rr_node[0][inode]; - cur_sb->opin_rr_node_grid_side[side][inode] = 3; /* Grid[x+1][y] LEFT side outputs pins */ - } - for (inode = 0; inode < temp_num_opin_rr_nodes[1]; inode++) { - cur_sb->opin_rr_node[side][inode + temp_num_opin_rr_nodes[0]] = temp_opin_rr_node[1][inode]; - cur_sb->opin_rr_node_grid_side[side][inode + temp_num_opin_rr_nodes[0]] = 1; /* Grid[x][y] RIGHT side outputs pins */ - } - /* We do not have any IPIN for a Switch Block */ - cur_sb->num_ipin_rr_nodes[side] = 0; - cur_sb->ipin_rr_node[side] = NULL; - cur_sb->ipin_rr_node_grid_side[side] = NULL; - break; - case 3: - /* For the bording, we should take special care */ - if (sb_x == 0) { - cur_sb->chan_width[side] = 0; - cur_sb->chan_rr_node[side] = NULL; - cur_sb->chan_rr_node_direction[side] = NULL; - cur_sb->num_ipin_rr_nodes[side] = 0; - cur_sb->ipin_rr_node[side] = NULL; - cur_sb->ipin_rr_node_grid_side[side] = NULL; - cur_sb->num_opin_rr_nodes[side] = 0; - cur_sb->opin_rr_node[side] = NULL; - cur_sb->opin_rr_node_grid_side[side] = NULL; - break; - } - /* Routing channels*/ - ix = sb_x; - iy = sb_y; - /* Channel width */ - cur_sb->chan_width[side] = chan_width_x[iy]; - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Alloc */ - cur_sb->chan_rr_node[side] = get_chan_rr_nodes(&(cur_sb->chan_width[side]), CHANX, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - cur_sb->chan_rr_node_direction[side] = (enum PORTS*)my_malloc(sizeof(enum PORTS)*cur_sb->chan_width[side]); - /* Collect rr_nodes for Tracks for left: chanx[x][y] */ - for (itrack = 0; itrack < cur_sb->chan_width[side]; itrack++) { - /* Identify the directionality, record it in rr_node_direction */ - if (DEC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction) { - cur_sb->chan_rr_node_direction[side][itrack] = OUT_PORT; - } else { - assert (INC_DIRECTION == cur_sb->chan_rr_node[side][itrack]->direction); - cur_sb->chan_rr_node_direction[side][itrack] = IN_PORT; - } - } - /* include Grid[x][y+1] Bottom side outputs pins */ - temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], - OPIN, sb_x, sb_y + 1, 2, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* include Grid[x][y] Top side output pins */ - temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], - OPIN, sb_x, sb_y, 0, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* Allocate opin_rr_node */ - cur_sb->num_opin_rr_nodes[side] = temp_num_opin_rr_nodes[0] + temp_num_opin_rr_nodes[1]; - cur_sb->opin_rr_node[side] = (t_rr_node**)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(t_rr_node*)); - cur_sb->opin_rr_node_grid_side[side] = (int*)my_calloc(cur_sb->num_opin_rr_nodes[side], sizeof(int)); - /* Copy from temp_opin_rr_node to opin_rr_node */ - for (inode = 0; inode < temp_num_opin_rr_nodes[0]; inode++) { - cur_sb->opin_rr_node[side][inode] = temp_opin_rr_node[0][inode]; - cur_sb->opin_rr_node_grid_side[side][inode] = 2; /* Grid[x][y+1] BOTTOM side outputs pins */ - } - for (inode = 0; inode < temp_num_opin_rr_nodes[1]; inode++) { - cur_sb->opin_rr_node[side][inode + temp_num_opin_rr_nodes[0]] = temp_opin_rr_node[1][inode]; - cur_sb->opin_rr_node_grid_side[side][inode + temp_num_opin_rr_nodes[0]] = 0; /* Grid[x][y] TOP side outputs pins */ - } - /* We do not have any IPIN for a Switch Block */ - cur_sb->num_ipin_rr_nodes[side] = 0; - cur_sb->ipin_rr_node[side] = NULL; - cur_sb->ipin_rr_node_grid_side[side] = NULL; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid side index!\n", __FILE__, __LINE__); - exit(1); - } - /* Free */ - temp_num_opin_rr_nodes[0] = 0; - my_free(temp_opin_rr_node[0]); - temp_num_opin_rr_nodes[1] = 0; - my_free(temp_opin_rr_node[1]); - /* Set them to NULL, avoid double free errors */ - temp_opin_rr_node[0] = NULL; - temp_opin_rr_node[1] = NULL; - } - - return; -} - -/* Build arrays for rr_nodes of each Switch Blocks - * Return a two-dimension array (t_rr_node**), - * each element of which is the entry of a two-dimension array of rr_node pointers (t_rr_node***) - * according to their location in a switch block - * Therefore, the return data type is (t_rr_node*****) - */ -static -void alloc_and_build_switch_blocks_info(t_det_routing_arch RoutingArch, - int LL_num_rr_nodes, - t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { - int ix, iy; - - sb_info = alloc_sb_info_array(nx, ny); - - /* For each switch block, determine the size of array */ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 0; iy < (ny + 1); iy++) { - build_one_switch_block_info(&sb_info[ix][iy], ix, iy, RoutingArch, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - } - } - - return; -} - -/* Collect rr_nodes information for a connection box - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y] | [x+1][y+1] | - * | | Connection | | - * -------------- Box_Y[x][y] -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * Connection | [x][y] | Connection - * Box_X[x][y] ---------- Box_X[x+1][y] - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y-1] | [x+1][y] | - * | | Connection | | - * --------------Box_Y[x][y-1]-------------- - */ -void build_one_connection_block_info(t_cb* cur_cb, int cb_x, int cb_y, t_rr_type cb_type, - int LL_num_rr_nodes, - t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { - int itrack, inode, side; - - /* Check */ - assert((!(0 > cb_x))&&(!(cb_x > (nx + 1)))); - assert((!(0 > cb_y))&&(!(cb_y > (ny + 1)))); - - /* Fill basic information */ - cur_cb->x = cb_x; - cur_cb->y = cb_y; - cur_cb->type = cb_type; - - /* Record the channel width of each side*/ - cur_cb->chan_width = (int*)my_calloc(cur_cb->num_sides, sizeof(int)); /* 4 sides */ - cur_cb->chan_rr_node_direction = (enum PORTS**)my_malloc(sizeof(enum PORTS*)*cur_cb->num_sides); /* 4 sides */ - cur_cb->chan_rr_node = (t_rr_node***)my_malloc(sizeof(t_rr_node**)*cur_cb->num_sides); /* 4 sides*/ - cur_cb->num_ipin_rr_nodes = (int*)my_calloc(cur_cb->num_sides, sizeof(int)); /* 4 sides */ - cur_cb->ipin_rr_node = (t_rr_node***)my_malloc(sizeof(t_rr_node**)*cur_cb->num_sides); /* 4 sides*/ - cur_cb->ipin_rr_node_grid_side = (int**)my_calloc(cur_cb->num_sides, sizeof(int*)); /* 4 sides */ - cur_cb->num_opin_rr_nodes = (int*)my_calloc(cur_cb->num_sides, sizeof(int)); /* 4 sides */ - cur_cb->opin_rr_node = (t_rr_node***)my_malloc(sizeof(t_rr_node**)*cur_cb->num_sides); /* 4 sides*/ - cur_cb->opin_rr_node_grid_side = (int**)my_calloc(cur_cb->num_sides, sizeof(int*)); /* 4 sides */ - - /* Identify the type of connection box, the rr_nodes are different depending on the type */ - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - for (side = 0; side < 4; side++) { - switch (side) { - case 0: /* TOP */ - switch(cb_type) { - case CHANX: - /* BOTTOM INPUT Pins of Grid[x][y+1] */ - /* Collect IPIN rr_nodes*/ - cur_cb->ipin_rr_node[side] = get_grid_side_pin_rr_nodes(&(cur_cb->num_ipin_rr_nodes[side]), - IPIN, cb_x, cb_y + 1, 2, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - - cur_cb->ipin_rr_node_grid_side[side] = (int*)my_calloc(cur_cb->num_ipin_rr_nodes[side], sizeof(int)); - for (inode = 0; inode < cur_cb->num_ipin_rr_nodes[side]; inode++) { - cur_cb->ipin_rr_node_grid_side[side][inode] = 2; /* BOTTOM IPINs */ - } - /* Update channel width, num_opin_rr_nodes */ - cur_cb->chan_width[side] = 0; - /* Identify the directionality, record it in rr_node_direction */ - cur_cb->chan_rr_node[side] = NULL; - cur_cb->chan_rr_node_direction[side] = NULL; - /* There is no OPIN nodes at this side */ - cur_cb->num_opin_rr_nodes[side] = 0; - cur_cb->opin_rr_node[side] = NULL; - cur_cb->opin_rr_node_grid_side[side] = NULL; - break; - case CHANY: - /* Collect channel-Y [x][y] rr_nodes*/ - /* Update channel width */ - cur_cb->chan_rr_node[side] = get_chan_rr_nodes(&(cur_cb->chan_width[side]), CHANY, cb_x, cb_y, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* Alloc */ - cur_cb->chan_rr_node_direction[side] = (enum PORTS*)my_malloc(sizeof(enum PORTS)*cur_cb->chan_width[side]); - /* Collect rr_nodes for Tracks for left: chanx[x][y] */ - for (itrack = 0; itrack < cur_cb->chan_width[side]; itrack++) { - /* Identify the directionality, record it in rr_node_direction */ - cur_cb->chan_rr_node_direction[side][itrack] = IN_PORT; - } - /* There is no IPIN nodes at this side */ - cur_cb->num_ipin_rr_nodes[side] = 0; - cur_cb->ipin_rr_node[side] = NULL; - cur_cb->ipin_rr_node_grid_side[side] = NULL; - /* There is no OPIN nodes at this side */ - cur_cb->num_opin_rr_nodes[side] = 0; - cur_cb->opin_rr_node[side] = NULL; - cur_cb->opin_rr_node_grid_side[side] = NULL; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - break; - case 1: /* RIGHT */ - switch(cb_type) { - case CHANX: - /* Collect channel-X [x][y] rr_nodes*/ - /* Update channel width */ - cur_cb->chan_rr_node[side] = get_chan_rr_nodes(&(cur_cb->chan_width[side]), CHANX, cb_x, cb_y, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* Alloc */ - cur_cb->chan_rr_node_direction[side] = (enum PORTS*)my_malloc(sizeof(enum PORTS)*cur_cb->chan_width[side]); - /* Collect rr_nodes for Tracks for left: chanx[x][y] */ - for (itrack = 0; itrack < cur_cb->chan_width[side]; itrack++) { - /* Identify the directionality, record it in rr_node_direction */ - cur_cb->chan_rr_node_direction[side][itrack] = IN_PORT; - } - /* There is no IPIN nodes at this side */ - cur_cb->num_ipin_rr_nodes[side] = 0; - cur_cb->ipin_rr_node[side] = NULL; - cur_cb->ipin_rr_node_grid_side[side] = NULL; - /* There is no OPIN nodes at this side */ - cur_cb->num_opin_rr_nodes[side] = 0; - cur_cb->opin_rr_node[side] = NULL; - cur_cb->opin_rr_node_grid_side[side] = NULL; - break; - case CHANY: - /* LEFT INPUT Pins of Grid[x+1][y] */ - /* Collect IPIN rr_nodes*/ - cur_cb->ipin_rr_node[side] = get_grid_side_pin_rr_nodes(&(cur_cb->num_ipin_rr_nodes[side]), - IPIN, cb_x + 1, cb_y, 3, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - cur_cb->ipin_rr_node_grid_side[side] = (int*)my_calloc(cur_cb->num_ipin_rr_nodes[side], sizeof(int)); - for (inode = 0; inode < cur_cb->num_ipin_rr_nodes[side]; inode++) { - cur_cb->ipin_rr_node_grid_side[side][inode] = 3; /* LEFT IPINs */ - } - /* Update channel width, num_opin_rr_nodes */ - cur_cb->chan_width[side] = 0; - /* Identify the directionality, record it in rr_node_direction */ - cur_cb->chan_rr_node[side] = NULL; - cur_cb->chan_rr_node_direction[side] = NULL; - /* There is no OPIN nodes at this side */ - cur_cb->num_opin_rr_nodes[side] = 0; - cur_cb->opin_rr_node[side] = NULL; - cur_cb->opin_rr_node_grid_side[side] = NULL; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - break; - case 2: /* BOTTOM */ - switch(cb_type) { - case CHANX: - /* TOP INPUT Pins of Grid[x][y] */ - /* Collect IPIN rr_nodes*/ - cur_cb->ipin_rr_node[side] = get_grid_side_pin_rr_nodes(&(cur_cb->num_ipin_rr_nodes[side]), - IPIN, cb_x, cb_y, 0, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - cur_cb->ipin_rr_node_grid_side[side] = (int*)my_calloc(cur_cb->num_ipin_rr_nodes[side], sizeof(int)); - for (inode = 0; inode < cur_cb->num_ipin_rr_nodes[side]; inode++) { - cur_cb->ipin_rr_node_grid_side[side][inode] = 0; /* TOP IPINs */ - } - /* Update channel width, num_opin_rr_nodes */ - cur_cb->chan_width[side] = 0; - /* Identify the directionality, record it in rr_node_direction */ - cur_cb->chan_rr_node[side] = NULL; - cur_cb->chan_rr_node_direction[side] = NULL; - /* There is no OPIN nodes at this side */ - cur_cb->num_opin_rr_nodes[side] = 0; - cur_cb->opin_rr_node[side] = NULL; - cur_cb->opin_rr_node_grid_side[side] = NULL; - break; - case CHANY: - /* Nothing should be done other than setting NULL pointers and zero counter*/ - /* There is no input and output rr_nodes at this side */ - cur_cb->chan_width[side] = 0; - cur_cb->chan_rr_node[side] = NULL; - cur_cb->chan_rr_node_direction[side] = NULL; - cur_cb->num_ipin_rr_nodes[side] = 0; - cur_cb->ipin_rr_node[side] = NULL; - cur_cb->ipin_rr_node_grid_side[side] = NULL; - cur_cb->num_opin_rr_nodes[side] = 0; - cur_cb->opin_rr_node[side] = NULL; - cur_cb->opin_rr_node_grid_side[side] = NULL; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - break; - case 3: /* LEFT */ - switch(cb_type) { - case CHANX: - /* Nothing should be done other than setting NULL pointers and zero counter*/ - /* There is no input and output rr_nodes at this side */ - cur_cb->chan_width[side] = 0; - cur_cb->chan_rr_node[side] = NULL; - cur_cb->chan_rr_node_direction[side] = NULL; - cur_cb->num_ipin_rr_nodes[side] = 0; - cur_cb->ipin_rr_node[side] = NULL; - cur_cb->ipin_rr_node_grid_side[side] = NULL; - cur_cb->num_opin_rr_nodes[side] = 0; - cur_cb->opin_rr_node[side] = NULL; - cur_cb->opin_rr_node_grid_side[side] = NULL; - break; - case CHANY: - /* RIGHT INPUT Pins of Grid[x][y] */ - /* Collect IPIN rr_nodes*/ - cur_cb->ipin_rr_node[side] = get_grid_side_pin_rr_nodes(&(cur_cb->num_ipin_rr_nodes[side]), - IPIN, cur_cb->x, cur_cb->y, 1, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - cur_cb->ipin_rr_node_grid_side[side] = (int*)my_calloc(cur_cb->num_ipin_rr_nodes[side], sizeof(int)); - for (inode = 0; inode < cur_cb->num_ipin_rr_nodes[side]; inode++) { - cur_cb->ipin_rr_node_grid_side[side][inode] = 1; /* RIGHT IPINs */ - } - /* Update channel width, num_opin_rr_nodes */ - cur_cb->chan_width[side] = 0; - /* Identify the directionality, record it in rr_node_direction */ - cur_cb->chan_rr_node[side] = NULL; - cur_cb->chan_rr_node_direction[side] = NULL; - /* There is no OPIN nodes at this side */ - cur_cb->num_opin_rr_nodes[side] = 0; - cur_cb->opin_rr_node[side] = NULL; - cur_cb->opin_rr_node_grid_side[side] = NULL; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid side index!\n", __FILE__, __LINE__); - exit(1); - } - } - - return; -} - - -/* Build arrays for rr_nodes of each Connection Blocks - * Different from Switch blocks, we have two types of Connection blocks: - * 1. Connecting X-channels to CLB inputs - * 2. Connection Y-channels to CLB inputs - */ -static -void alloc_and_build_connection_blocks_info(t_det_routing_arch RoutingArch, - int LL_num_rr_nodes, - t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { - int ix, iy; - - /* alloc CB for X-channels */ - cbx_info = alloc_cb_info_array(nx, ny); - /* Fill information for each CBX*/ - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - build_one_connection_block_info(&(cbx_info[ix][iy]), ix, iy, CHANX, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - } - } - - /* alloc CB for Y-channels */ - cby_info = alloc_cb_info_array(nx, ny); - /* Fill information for each CBX*/ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - build_one_connection_block_info(&(cby_info[ix][iy]), ix, iy, CHANY, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - } - } - - return; -} - -/* Free all the allocated memories by function: - * either spice_backannotate_vpr_post_route_info or backannotate_vpr_post_route_info*/ -void free_backannotate_vpr_post_route_info() { - /* Free spice_net_info */ - free_clb_nets_spice_net_info(); - /* Free CB and SB info */ - free_sb_info_array(&sb_info, nx, ny); - free_cb_info_array(&cbx_info, nx, ny); - free_cb_info_array(&cby_info, nx, ny); -} - -static -boolean ipin_rr_nodes_vpack_net_num_changed(int LL_num_rr_nodes, - t_rr_node* LL_rr_node) { - int inode; - - for (inode = 0; inode < LL_num_rr_nodes; inode++) { - if (IPIN != LL_rr_node[inode].type) { - continue; - } - /* We only care IPINs */ - if (TRUE == LL_rr_node[inode].vpack_net_num_changed) { - return TRUE; - } - } - - return FALSE; -} - -static -void parasitic_net_estimation() { - int iter_cnt = 0; - boolean iter_continue = FALSE; - - - vpr_printf(TIO_MESSAGE_INFO, "Start backannotating global and local routing nets iteratively...\n"); - while(1) { - iter_cnt++; - - init_rr_nodes_vpack_net_num_changed(num_rr_nodes, - rr_node); - - init_rr_nodes_is_parasitic_net(num_rr_nodes, - rr_node); - - /* - * vpr_printf(TIO_MESSAGE_INFO, "Backannotating local routing net...\n"); - backannotate_pb_rr_nodes_net_info(); - */ - - /* Update CLB pins parasitic nets: - * Traverse from inputs of CLBs to outputs. - * Mark parasitics nets propagated from input pins to output pins inside CLBs - */ - update_grid_pb_pins_parasitic_nets(); - - /* Backannoating global routing parasitic net... - * Traverse from OPINs in rr_graph to IPINs. - * Mark parasitic nets in the rr_graph - */ - backannotate_rr_nodes_parasitic_net_info(); - - /* Check vpack_net_num of all the OPINs are consistant */ - /* Consistency means iterations end here */ - iter_continue = ipin_rr_nodes_vpack_net_num_changed(num_rr_nodes, - rr_node); - - if (FALSE == iter_continue) { - break; - } - } - - vpr_printf(TIO_MESSAGE_INFO,"Parasitic net estimation ends in %d iterations.\n", iter_cnt); - - return; -} - -/* Annotate the physical_mode_pin in pb_type ports, - * Go recursively until we reach a primtiive node - */ -void rec_annotate_pb_type_primitive_node_physical_mode_pin(t_pb_type* top_pb_type, - t_pb_type* cur_pb_type) { - int imode, ipb; - - /* See if this is a primitive pb_graph_node */ - if (FALSE == is_primitive_pb_type(cur_pb_type)) { - /* Check each mode*/ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* bypass physical modes only when there are more than 1 modes available ! */ - if ((1 == cur_pb_type->modes[imode].define_physical_mode) - &&(1 < cur_pb_type->num_modes)) { - continue; - } - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - rec_annotate_pb_type_primitive_node_physical_mode_pin(top_pb_type, - &(cur_pb_type->modes[imode].pb_type_children[ipb])); - } - } - return; - } - - /* Reach here, it means a primitive mode */ - assert (TRUE == is_primitive_pb_type(cur_pb_type)); - /* Check the physical pb_type */ - /* Find the physical_pb_type with the name provided */ - cur_pb_type->phy_pb_type = rec_get_pb_type_by_name(top_pb_type, cur_pb_type->physical_pb_type_name); - /* Overwrite class type */ - if (UNKNOWN_CLASS != cur_pb_type->class_type) { - cur_pb_type->phy_pb_type->class_type = cur_pb_type->class_type; - } - vpr_printf(TIO_MESSAGE_INFO, - "Link physical pb_type (name=%s) for pb_type (name=%s)!\n", - cur_pb_type->physical_pb_type_name, cur_pb_type->name); - /* Check: We should find one! */ - if (NULL == cur_pb_type->phy_pb_type) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Fail to find physical pb_type (name=%s) for pb_type (name=%s)!\n", - __FILE__, __LINE__, cur_pb_type->physical_pb_type_name, cur_pb_type->name); - exit(1); - } - /* Check: the one should be linked to a SPICE model ! */ - if (NULL == cur_pb_type->phy_pb_type->spice_model) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Found physical pb_type (name=%s) for pb_type (name=%s) does not have a SPICE model definition!\n", - __FILE__, __LINE__, cur_pb_type->physical_pb_type_name, cur_pb_type->name); - exit(1); - } - /* Check: the one should be in a physical mode! */ - if (FALSE == cur_pb_type->phy_pb_type->parent_mode->define_physical_mode) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Found physical pb_type (name=%s) for pb_type (name=%s) does not belong to a physical mode!\n", - __FILE__, __LINE__, cur_pb_type->physical_pb_type_name, cur_pb_type->name); - exit(1); - } - - /* Now we are sure about the phy_pb_type that is found */ - /* Find matched port one by one */ - annotate_pb_type_port_to_phy_pb_type(cur_pb_type, cur_pb_type->phy_pb_type); - - return; -} - -/* Annotate the physical_mode_pin in pb_type ports, - * Go recursively until we reach a primtiive node - */ -static -void rec_annotate_phy_pb_type_primitive_node_physical_mode_pin(t_pb_type* top_pb_type, - t_pb_type* cur_pb_type) { - int phy_mode_idx, ipb, iport; - boolean is_top_pb_type = (top_pb_type == cur_pb_type) ? TRUE : FALSE; - - /* For top_pb_type: itself is a physical pb_type */ - if ((TRUE == is_top_pb_type) - || (TRUE == is_primitive_pb_type(cur_pb_type))) { - /* Reach here, it means a primitive mode */ - /* Check the physical pb_type */ - /* Find the physical_pb_type with the name provided */ - cur_pb_type->phy_pb_type = cur_pb_type; - /* Overwrite class type */ - if (UNKNOWN_CLASS != cur_pb_type->class_type) { - cur_pb_type->phy_pb_type->class_type = cur_pb_type->class_type; - } - /* Now we are sure about the phy_pb_type that is found */ - /* Find matched port one by one */ - for (iport = 0; iport < cur_pb_type->num_ports; iport++) { - cur_pb_type->ports[iport].phy_pb_type_port = &(cur_pb_type->ports[iport]); - cur_pb_type->ports[iport].phy_pb_type_port_lsb = 0; - cur_pb_type->ports[iport].phy_pb_type_port_msb = cur_pb_type->ports[iport].num_pins - 1; - } - /* return when it is a primitive node */ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - /* ONLY FOR PRIMITIVE NODE: Copy the pb_type_name from the name of cur_pb_type */ - cur_pb_type->physical_pb_type_name = my_strdup(cur_pb_type->name); - /* Copy the name of ports to the physical_mode_pin to the port itself */ - for (iport = 0; iport < cur_pb_type->num_ports; iport++) { - cur_pb_type->ports[iport].physical_mode_pin = my_strdup(cur_pb_type->ports[iport].name); - } - return; - } - } - - /* See if this is a primitive pb_graph_node */ - if (FALSE == is_primitive_pb_type(cur_pb_type)) { - if (FALSE == is_top_pb_type) { - cur_pb_type->phy_pb_type = NULL; /* Special for top_pb_type */ - } - /* we only care physical modes */ - phy_mode_idx = find_pb_type_physical_mode_index((*cur_pb_type)); - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[phy_mode_idx].num_pb_type_children; ipb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - rec_annotate_phy_pb_type_primitive_node_physical_mode_pin(top_pb_type, - &(cur_pb_type->modes[phy_mode_idx].pb_type_children[ipb])); - } - } - - return; -} - -/* Go recursively visiting each primitive node in the pb_graph_node - * Label the primitive node with a placement index which is unique at the top-level node - */ -static -void rec_mark_pb_graph_node_primitive_placement_index_in_top_node(t_pb_graph_node* cur_pb_graph_node) { - int imode, ipb, jpb; - t_pb_type* cur_pb_type = NULL; - - cur_pb_type = cur_pb_graph_node->pb_type; - - /* See if this is a primitive pb_graph_node */ - if (FALSE == is_primitive_pb_type(cur_pb_type)) { - /* Check each mode*/ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[imode].pb_type_children[ipb].num_pb; jpb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb].placement_index); - rec_mark_pb_graph_node_primitive_placement_index_in_top_node(&(cur_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb])); - } - } - } - return; - } - - /* Reach here, it means a primitive mode */ - assert (NULL != cur_pb_type->phy_pb_type ); - /* Label placement_index_in_top_node */ - cur_pb_graph_node->placement_index_in_top_node = cur_pb_type->temp_placement_index; - cur_pb_type->temp_placement_index++; - - return; -} - -/* Recursively go to the primitive pb_graph_node - * create a link from the primitive pb_graph_node to its physical pb_graph_pin */ -void rec_link_primitive_pb_graph_node_pin_to_phy_pb_graph_pin(t_pb_graph_node* top_pb_graph_node, - t_pb_graph_node* cur_pb_graph_node) { - int imode, ipb, jpb; - int physical_pb_graph_node_placement_index = -1; - t_pb_type* cur_pb_type = NULL; - t_pb_graph_node* phy_pb_graph_node = NULL; - boolean is_top_pb_graph_node = (top_pb_graph_node == cur_pb_graph_node) ? TRUE : FALSE; - - cur_pb_type = cur_pb_graph_node->pb_type; - - /* For top_pb_type: itself is a physical pb_type */ - if (TRUE == is_top_pb_graph_node) { - /* Reach here, it means a primitive mode */ - assert (NULL != cur_pb_type->phy_pb_type); - /* Create linkes between pb_graph_pins and pb_graph_nodes */ - cur_pb_graph_node->physical_pb_graph_node = top_pb_graph_node; - link_pb_graph_node_pins_to_phy_pb_graph_pins(top_pb_graph_node, top_pb_graph_node->physical_pb_graph_node); - } - - /* For primitive node */ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - /* Reach here, it means a primitive mode */ - assert (NULL != cur_pb_type->phy_pb_type); - /* Get the physical pb_graph_node with the scaled placement_index! */ - physical_pb_graph_node_placement_index = (int) (cur_pb_type->physical_pb_type_index_factor - * (float) cur_pb_graph_node->placement_index_in_top_node) - + cur_pb_type->physical_pb_type_index_offset; - phy_pb_graph_node = rec_get_pb_graph_node_by_pb_type_and_placement_index_in_top_node(top_pb_graph_node, - cur_pb_type->phy_pb_type, - physical_pb_graph_node_placement_index); - assert(NULL != phy_pb_graph_node); - /* Create linkes between pb_graph_pins and pb_graph_nodes */ - cur_pb_graph_node->physical_pb_graph_node = phy_pb_graph_node; - link_pb_graph_node_pins_to_phy_pb_graph_pins(cur_pb_graph_node, cur_pb_graph_node->physical_pb_graph_node); - return; - } - - /* See if this is a primitive pb_graph_node */ - if (FALSE == is_primitive_pb_type(cur_pb_type)) { - /* Check each mode*/ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* bypass physical modes only when there are more than 1 modes available ! */ - if ((1 == cur_pb_type->modes[imode].define_physical_mode) - &&(1 < cur_pb_type->num_modes)) { - continue; - } - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[imode].pb_type_children[ipb].num_pb; jpb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb].placement_index); - rec_link_primitive_pb_graph_node_pin_to_phy_pb_graph_pin(top_pb_graph_node, - &(cur_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb])); - } - } - } - } - - - return; -} - -/* Back-annotate the physical mode pins defined in pb_type to pb_graph_node - * For each pb_graph_node available in type->pb_graph_head - * 1. Label each primitive nodes with the placement_index_top_node - * 2. find the pb_graph_pin of primitive nodes in the pb_graph_node - * 3. identify the physical mode pin definition (in pb_type) - * 4. create a link to the pb_graph_pin in physical mode - */ -void annotate_physical_mode_pins_in_pb_graph_node() { - int itype; - - for (itype = 0; itype < num_types; itype++) { - /* Bybass NULL/EMPTY_TYPE */ - if (EMPTY_TYPE == &type_descriptors[itype]) { - continue; - } - /* reset phy_pb_type in all the pb_types */ - rec_reset_pb_type_phy_pb_type(type_descriptors[itype].pb_type); - /* reset the rr_node_index_physical_pb of each pb_graph_pin to be OPEN ! */ - rec_reset_pb_graph_node_rr_node_index_physical_pb(type_descriptors[itype].pb_graph_head); - /* annotate the physical mode pins in the physical primitive pb_type*/ - rec_annotate_phy_pb_type_primitive_node_physical_mode_pin(type_descriptors[itype].pb_type, type_descriptors[itype].pb_type); - /* annotate the physical mode pins in the primitive pb_type*/ - rec_annotate_pb_type_primitive_node_physical_mode_pin(type_descriptors[itype].pb_type, type_descriptors[itype].pb_type); - /* reset temp_placement_index in all the pb_types */ - rec_reset_pb_type_temp_placement_index(type_descriptors[itype].pb_type); - /* Recursively find the primitive pb_grpah_nodes */ - rec_mark_pb_graph_node_primitive_placement_index_in_top_node(type_descriptors[itype].pb_graph_head); - /* Recursively link the pb_graph_pin of primitive nodes in operating pb to physical pb */ - rec_link_primitive_pb_graph_node_pin_to_phy_pb_graph_pin(type_descriptors[itype].pb_graph_head, type_descriptors[itype].pb_graph_head); - } - - return; -} - -/* Allocate pb in mapped blocks, corresponding to physical modes */ -void alloc_and_load_phy_pb_for_mapped_block(int num_mapped_blocks, t_block* mapped_block, - int L_num_vpack_nets, t_net* L_vpack_net) { - int iblk; - t_phy_pb* top_phy_pb = NULL; - boolean route_success = FALSE; - - for (iblk = 0; iblk < num_mapped_blocks; iblk++) { - vpr_printf(TIO_MESSAGE_INFO, - "Start backannotate clb (%s) to its physical pb!\n", - mapped_block[iblk].pb->name); - top_phy_pb = (t_phy_pb*) my_calloc(1, sizeof(t_phy_pb)); - /* Create a pristine pb for pb_graph_nodes in the physical modes */ - top_phy_pb->pb_graph_node = mapped_block[iblk].type->pb_graph_head; - /* alloc_and_load_pb_stats(maped_block[iblk].phy_pb, num_models, max_nets_in_pb_type); */ - top_phy_pb->parent_pb = NULL; - top_phy_pb->mode = 0; /* Top-level should have only one mode!!! */ - /* Allocate rr_graph for the phy_pb */ - /* vpr_printf(TIO_MESSAGE_INFO, "Allocating routing resource graph for %d physical pb!\r", iblk); - */ - alloc_and_load_rr_graph_for_phy_pb(mapped_block[iblk].pb, top_phy_pb, L_num_vpack_nets, L_vpack_net); - /* Perform routing for the phy_pb !!! */ - route_success = try_breadth_first_route_pb_rr_graph(top_phy_pb->rr_graph); - if (TRUE == route_success) { - /* vpr_printf(TIO_MESSAGE_INFO, "Route successfully for %d physical pbs!\r", iblk); */ - } else { - assert(FALSE == route_success); - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Route fail for physical pb (x=%d, y=%d, type_name=%s)!\n", - __FILE__, __LINE__, mapped_block[iblk].x, mapped_block[iblk].y, mapped_block[iblk].type->name); - exit(1); - } - /* Backannotate routing results to physical pb_rr_graph */ - backannotate_rr_graph_routing_results_to_net_name(top_phy_pb->rr_graph); - vpr_printf(TIO_MESSAGE_INFO, - "Backannotate routing results successfully for physical pb (%s)!\n", - mapped_block[iblk].pb->name); - /* Allocate and load child_pb graphs */ - alloc_and_load_phy_pb_children_for_one_mapped_block(mapped_block[iblk].pb, top_phy_pb); - /* Give top_phy_pb to grid */ - mapped_block[iblk].phy_pb = (void*)top_phy_pb; - /* Create a link from pb to phy_pb */ - mapped_block[iblk].pb->phy_pb = (void*)top_phy_pb; - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - return; -} - -/* This function does the following tasks: - * 1. Find the wired LUTs in pb recursively(used as buffers) - * 2. Allocate the pb (if not allocated) - * 3. Update the mapping information (net_num) in the rr_graph of pb - * 4. Create the wired LUTs in logical block array - * 5. Create new vpack nets to rewire the logical blocks - */ -static -void rec_backannotate_one_pb_wired_luts_and_adapt_graph(t_pb* cur_pb, - int* L_num_logical_blocks, t_net** L_logical_block, - int* L_num_vpack_nets, t_net** L_vpack_net) { - int mode_index, ipb, jpb; - t_pb_type* cur_pb_type = NULL; - t_pb* lut_child_pb = NULL; - - cur_pb_type = cur_pb->pb_graph_node->pb_type; - mode_index = cur_pb->mode; - - /* Go recursively until we reach a primitive node which is a LUT */ - - /* Return if we reach the primitive */ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - /* We only care the LUTs, that is in wired mode */ - if ((LUT_CLASS != cur_pb_type->class_type) - || (WIRED_LUT_MODE_INDEX != mode_index)) { - return; - } - /* Reach here means that this LUT is in wired mode (a buffer) - * Check if we need to allocate new logical block - */ - lut_child_pb = get_lut_child_pb(cur_pb, mode_index); - assert (NULL != lut_child_pb); - if (OPEN != lut_child_pb->logical_block) { - return; - } - /* We need to - * 1. Add a new logical block - * 2. Add a new vpack_net - * 3. Update pb rr_graph - */ - } - - /* recursive for the child_pbs*/ - assert (FALSE == is_primitive_pb_type(cur_pb_type)); - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Recursive*/ - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - rec_backannotate_one_pb_wired_luts_and_adapt_graph(&(cur_pb->child_pbs[ipb][jpb]), - L_num_logical_blocks, L_logical_block, - L_num_vpack_nets, L_vpack_net); - } else { - if (TRUE == is_pb_wired_lut(&(cur_pb->pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), - &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), - cur_pb->rr_graph)) { - /* Reach here means that this LUT is in wired mode (a buffer) */ - /* 1. Allocate a child pb */ - allocate_wired_lut_pbs(&(cur_pb->child_pbs), - cur_pb_type->modes[mode_index].num_pb_type_children, - cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb, - ipb, jpb); - /* Load the LUT information to the pb */ - /* 2. Add a new logical block */ - /* 3. Add a new vpack_net */ - /* - load_wired_lut_pbs(&(cur_pb->child_pbs[ipb][jpb]), - &(cur_pb->pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), - &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), - cur_pb->rr_graph, - L_num_logical_blocks, L_logical_block, - L_num_vpack_nets, L_vpack_net); - */ - /* 4. Update pb rr_graph */ - } - } - } - } - - return; -} - -/* Back-annotate all the wired LUTs (used as buffers) in pbs - * and adapt BLIF graph and pb graph! - */ -static -void backannotate_pb_wired_luts(int num_mapped_blocks, t_block* mapped_block, - int* L_num_logical_blocks, t_net** L_logical_block, - int* L_num_vpack_nets, t_net** L_vpack_net) { - - int iblk; - - for (iblk = 0; iblk < num_mapped_blocks; iblk++) { - /* Find wired LUTs in each pb recusively */ - rec_backannotate_one_pb_wired_luts_and_adapt_graph(mapped_block[iblk].pb, - L_num_logical_blocks, L_logical_block, - L_num_vpack_nets, L_vpack_net); - } - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - return; -} - -static -int find_matched_block_id_for_one_grid(int x, int y) { - int iblk, jblk, blk_id; - boolean already_exist = FALSE; - - /* We need to find a valid block ID here */ - for (iblk = 0; iblk < num_blocks; iblk++) { - /* We only care the matched x,y coordinate */ - if ( (x != block[iblk].x) - || (y != block[iblk].y)) { - continue; - } - /* Now, we double check if the block is already in the list */ - already_exist = FALSE; - for (jblk = 0; jblk < grid[x][y].usage; jblk++) { - blk_id = grid[x][y].blocks[jblk]; - if (iblk != blk_id) { - continue; - } - /* Already in the list, we do not return the value */ - already_exist = TRUE; - break; - } - /* Return if does not exist */ - if (FALSE == already_exist) { - return iblk; - } - } - - return OPEN; -} - -/* Some IO blocks has an invalid BLOCK ID but with a >0 usage - * We go through the block list and find the missing block ID - */ -static -void annotate_grid_block_info() { - int ix, iy; - t_type_ptr type = NULL; - int iblk, blk_id; - - for (ix = 0; ix < (nx + 2); ix++) { - for (iy = 0; iy < (ny + 2); iy++) { - type = grid[ix][iy].type; - /* bypass EMPTY type */ - if ((NULL == type) || (EMPTY_TYPE == type)) { - continue; - } - if (IO_TYPE != type) { - continue; - } - for (iblk = 0; iblk < grid[ix][iy].usage; iblk++) { - blk_id = grid[ix][iy].blocks[iblk]; - if (OPEN != blk_id) { - continue; - } - vpr_printf(TIO_MESSAGE_INFO, - "Detect an invalid block id for grid[%d][%d] (usage:%d, blk_id:%d), trying to find a matched block from list!\n", - ix, iy, grid[ix][iy].usage, iblk); - /* We detect an invalid blk_id, try to find one in the block list */ - grid[ix][iy].blocks[iblk] = find_matched_block_id_for_one_grid(ix, iy); - if (OPEN == grid[ix][iy].blocks[iblk]) { - vpr_printf(TIO_MESSAGE_WARNING, - "Fail to find a valid block id for grid[%d][%d] (usage:%d, blk_id:%d) in the block list!\n", - ix, iy, grid[ix][iy].usage, iblk); - } else { - vpr_printf(TIO_MESSAGE_INFO, - "Manage to find a valid block id (=%d) for grid[%d][%d]!\n", - grid[ix][iy].blocks[iblk], ix, iy); - } - } - } - } - - return; -} - -/* Back-Annotate post routing results to the VPR routing-resource graphs */ -void spice_backannotate_vpr_post_route_info(t_det_routing_arch RoutingArch, - boolean read_activity_file, - boolean parasitic_net_estimation_on) { - - vpr_printf(TIO_MESSAGE_INFO, "Start backannotating post route information for SPICE modeling...\n"); - - /* Back-annotate the wired LUTs in pbs */ - /* Paused due to difficulties in identify which part of the LUT fan-out is wired.... - vpr_printf(TIO_MESSAGE_INFO, "Back-annotate wired LUTs in pbs...\n"); - backannotate_pb_wired_luts(num_blocks, block, - &num_logical_blocks, &logical_block, - &num_logical_nets, &vpack_net); - */ - - /* Give spice_name_tag for each pb*/ - vpr_printf(TIO_MESSAGE_INFO, "Generate SPICE name tags for pbs...\n"); - gen_spice_name_tags_all_pbs(); - - /* Build previous node lists for each rr_node */ - vpr_printf(TIO_MESSAGE_INFO, "Building previous node list for all Routing Resource Nodes...\n"); - build_prev_node_list_rr_nodes(num_rr_nodes, rr_node); - //sort_rr_graph_drive_rr_nodes(num_rr_nodes, rr_node); - - /* Build driver switches for each rr_node*/ - vpr_printf(TIO_MESSAGE_INFO, "Identifying driver switches for all Routing Resource Nodes...\n"); - identify_rr_node_driver_switch(RoutingArch, num_rr_nodes, rr_node); - - /* Build Array for each Switch block and Connection block */ - vpr_printf(TIO_MESSAGE_INFO, "Collecting detailed information for each Switch block...\n"); - alloc_and_build_switch_blocks_info(RoutingArch, num_rr_nodes, rr_node, rr_node_indices); - - vpr_printf(TIO_MESSAGE_INFO, "Collecting detailed information for each to Connection block...\n"); - alloc_and_build_connection_blocks_info(RoutingArch, num_rr_nodes, rr_node, rr_node_indices); - - /* This function should go very first because it gives all the net_num */ - vpr_printf(TIO_MESSAGE_INFO,"Back annotating mapping information to global routing resource nodes...\n"); - back_annotate_rr_node_map_info(); - - /* Update local_rr_graphs to match post-route results*/ - vpr_printf(TIO_MESSAGE_INFO, "Update CLB local routing graph to match post-route results...\n"); - /* Complete the grid block information */ - annotate_grid_block_info(); - update_grid_pbs_post_route_rr_graph(); - - vpr_printf(TIO_MESSAGE_INFO,"Back annotating mapping information to local routing resource nodes...\n"); - back_annotate_pb_rr_node_map_info(); - - /* Annotate physical mode pins defined in each primitive pb_type/pb_graph_node */ - vpr_printf(TIO_MESSAGE_INFO, "Annotate physical mode pins for pbs ...\n"); - annotate_physical_mode_pins_in_pb_graph_node(); - alloc_and_load_phy_pb_for_mapped_block(num_blocks, block, num_logical_nets, vpack_net); - - vpr_printf(TIO_MESSAGE_INFO, "Generate SPICE name tags for phy_pbs...\n"); - gen_spice_name_tags_all_phy_pbs(); - - /* Backannotate activity information, initialize the waveform information */ - /* Parasitic Net Activity Estimation */ - if (TRUE == parasitic_net_estimation_on) { - vpr_printf(TIO_MESSAGE_INFO, "Parasitic Net Estimation starts...\n"); - parasitic_net_estimation(); - } else { - vpr_printf(TIO_MESSAGE_WARNING, "Parasitic Net Estimation is turned off...Accuracy loss may be expected!\n"); - } - - /* Net activities */ - if (TRUE == read_activity_file) { - vpr_printf(TIO_MESSAGE_INFO, "Backannoating Net activities...\n"); - backannotate_clb_nets_act_info(); - vpr_printf(TIO_MESSAGE_INFO, "Determine Net initial values...\n"); - backannotate_clb_nets_init_val(); - } else { - vpr_printf(TIO_MESSAGE_INFO, "Net activity backannoation is bypassed...\n"); - } - - vpr_printf(TIO_MESSAGE_INFO, "Finish backannotating post route information for SPICE modeling.\n"); - - return; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h deleted file mode 100644 index 466f24bed..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.h +++ /dev/null @@ -1,108 +0,0 @@ -#ifndef FPGA_X2P_BACKANNOTATE_UTILS_H -#define FPGA_X2P_BACKANNOTATE_UTILS_H - -int get_ff_output_init_val(t_logical_block* ff_logical_block); - -int get_lut_output_init_val(t_logical_block* lut_logical_block); - -int get_logical_block_output_init_val(t_logical_block* cur_logical_block); - -void init_one_sb_info(t_sb* cur_sb); - -void free_one_sb_info(t_sb* cur_sb); - -t_sb** alloc_sb_info_array(int LL_nx, int LL_ny); - -void free_sb_info_array(t_sb*** LL_sb_info, int LL_nx, int LL_ny); - -void init_one_cb_info(t_cb* cur_cb); - -void free_one_cb_info(t_cb* cur_cb); - -t_cb** alloc_cb_info_array(int LL_nx, int LL_ny); - -void free_cb_info_array(t_cb*** LL_cb_info, int LL_nx, int LL_ny); - -void free_clb_nets_spice_net_info(); - -int get_rr_node_index_in_sb_info(t_rr_node* cur_rr_node, - t_sb cur_sb_info, - int chan_side, enum PORTS rr_node_direction); - -int is_rr_node_exist_opposite_side_in_sb_info(t_sb cur_sb_info, - t_rr_node* src_rr_node, - int chan_side); - -boolean check_drive_rr_node_imply_short(t_sb cur_sb_info, - t_rr_node* src_rr_node, - int chan_side); - -void get_rr_node_side_and_index_in_sb_info(t_rr_node* cur_rr_node, - t_sb cur_sb_info, - enum PORTS rr_node_direction, - OUTP int* cur_rr_node_side, - OUTP int* cur_rr_node_index); - -void get_chan_rr_node_coordinate_in_sb_info(t_sb cur_sb_info, - int chan_rr_node_side, - t_rr_type* chan_type, - int* chan_rr_node_x, int* chan_rr_node_y); - -int get_rr_node_index_in_cb_info(t_rr_node* cur_rr_node, - t_cb cur_cb_info, - int chan_side, enum PORTS rr_node_direction); - -void get_rr_node_side_and_index_in_cb_info(t_rr_node* cur_rr_node, - t_cb cur_cb_info, - enum PORTS rr_node_direction, - OUTP int* cur_rr_node_side, - OUTP int* cur_rr_node_index); - -t_rr_node** get_chan_rr_nodes(int* num_chan_rr_nodes, - t_rr_type chan_type, - int x, int y, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices); - -t_rr_node** get_grid_side_pin_rr_nodes(int* num_pin_rr_nodes, - t_rr_type pin_type, - int x, int y, int side, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices); - -void build_one_switch_block_info(t_sb* cur_sb, int sb_x, int sb_y, - t_det_routing_arch RoutingArch, - int LL_num_rr_nodes, - t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices); - -void build_one_connection_block_info(t_cb* cur_cb, int cb_x, int cb_y, t_rr_type cb_type, - int LL_num_rr_nodes, - t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices); - -void update_one_grid_pack_prev_node_edge(int x, int y); - -void update_grid_pbs_post_route_rr_graph(); - -void free_backannotate_vpr_post_route_info(); - -void rec_annotate_pb_type_primitive_node_physical_mode_pin(t_pb_type* top_pb_type, - t_pb_type* cur_pb_type); - -void rec_mark_pb_graph_node_primitive_placement_index_in_top_node(t_pb_graph_node* cur_pb_graph_node, - int* start_index); - -void rec_link_primitive_pb_graph_node_pin_to_phy_pb_graph_pin(t_pb_graph_node* top_pb_graph_node, - t_pb_graph_node* cur_pb_graph_node); - -void annotate_physical_mode_pins_in_pb_graph_node(); - -void alloc_and_load_phy_pb_for_mapped_block(int num_mapped_blocks, t_block* mapped_block, - int L_num_vpack_nets, t_net* L_vpack_net); - -void spice_backannotate_vpr_post_route_info(t_det_routing_arch RoutingArch, - boolean read_activity_file, - boolean parasitic_net_estimation); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.cpp deleted file mode 100644 index df748c83a..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.cpp +++ /dev/null @@ -1,146 +0,0 @@ -/******************************************************************** - * This file includes most utilized functions to manipulate data - * structures that are related to the input benchmark circuit - *******************************************************************/ -#include "vtr_assert.h" -#include "sides.h" - -#include "fpga_x2p_benchmark_utils.h" - -/******************************************************************** - * Find the clock port name to be used in this testbench - *******************************************************************/ -std::vector find_benchmark_clock_port_name(const std::vector& L_logical_blocks) { - std::vector clock_port_names; - - for (const t_logical_block& lb : L_logical_blocks) { - /* Bypass non-I/O logical blocks ! */ - if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { - continue; - } - - /* Find the clock signals */ - if ( (VPACK_INPAD == lb.type) && (TRUE == lb.is_clock) ) { - clock_port_names.push_back(std::string(lb.name)); - } - } - - return clock_port_names; -} - -/******************************************************************** - * Find the I/O index in the FPGA top-level module - * that an I/O logical block is mapped to - * Note that this function follows the sequence in I/O grid instanciation - * in build_top_module(), where I/Os are instanciated from - * TOP, RIGHT, BOTTOM to LEFT sides. - * Therefore, the I/O indices will follow this sequence, where 0 starts - * from the TOP side - * - * This function will use the clb_index in each t_logical_block - * to spot a t_block that the I/O is mapped - * Through the t_block, we can find a detailed coordinate (x,y,z), - * based on which we can infer the I/O index in the top-level module - * - * Restrictions: if you change the sequence in I/O grid instanciation - * in the top-level module, this function MUST be changed!!! - *******************************************************************/ -size_t find_benchmark_io_index(const t_logical_block& io_lb, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks) { - /* Ensure this is an I/O logical block */ - VTR_ASSERT(VPACK_INPAD == io_lb.type || VPACK_OUTPAD == io_lb.type); - - /* Ensure the clb index in the range */ - VTR_ASSERT((size_t)io_lb.clb_index < L_blocks.size() ); - - /* Get the block (x, y, z) */ - size_t x = L_blocks[(size_t)io_lb.clb_index].x; - size_t y = L_blocks[(size_t)io_lb.clb_index].y; - size_t z = L_blocks[(size_t)io_lb.clb_index].z; - - /* Ensure the (x,y,z) is in the range of device */ - VTR_ASSERT( x < device_size.x() && y < device_size.y() ); - VTR_ASSERT( z < (size_t)L_grids[x][y].type->capacity ); - - /* Infer the I/O index: - * If the I/O is on the top side, the index will start from 0 - * If the I/O is on the right side, the index will start from capacity * nx - * If the I/O is on the bottom side, the index will start from capacity * (nx + ny) - * If the I/O is on the bottom side, the index will start from capacity * (2 * nx + ny) - */ - std::map io_index_offset; - io_index_offset[TOP] = 0; - - /* For RIGHT side, sum the capacity of TOP side grids */ - io_index_offset[RIGHT] = 0; - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - io_index_offset[RIGHT] += L_grids[ix][device_size.y() - 1].type->capacity; - } - - /* For BOTTOM side, sum the capacity of RIGHT side grids */ - io_index_offset[BOTTOM] = io_index_offset[RIGHT]; - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - io_index_offset[BOTTOM] += L_grids[device_size.x() - 1][iy].type->capacity; - } - - /* For LEFT side, sum the capacity of BOTTOM side grids */ - io_index_offset[LEFT] = io_index_offset[BOTTOM]; - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - io_index_offset[LEFT] += L_grids[ix][0].type->capacity; - } - - /* Find I/O grid side, I do not capasulate this in a function, because it is not so general */ - e_side io_side = NUM_SIDES; - if (0 == y) { - io_side = BOTTOM; - } - if (0 == x) { - io_side = LEFT; - } - if (device_size.x() - 1 == x) { - io_side = RIGHT; - } - if (device_size.y() - 1 == y) { - io_side = TOP; - } - VTR_ASSERT(NUM_SIDES != io_side); - - /* Now generate the io index */ - size_t io_index = size_t(-1); - /* TOP side I/Os */ - if (device_size.y() - 1 == y) { - io_index = io_index_offset[io_side]; - for (size_t ix = 1; ix < x ; ++ix) { - io_index += L_grids[ix][y].type->capacity; - } - io_index += z; - } - /* RIGHT side I/Os */ - if (device_size.x() - 1 == x) { - io_index = io_index_offset[io_side]; - for (size_t iy = 1; iy < y; ++iy) { - io_index += L_grids[x][iy].type->capacity; - } - io_index += z; - } - /* BOTTOM side I/Os */ - if (0 == y) { - io_index = io_index_offset[io_side]; - for (size_t ix = 1; ix < x; ++ix) { - io_index += L_grids[ix][y].type->capacity; - } - io_index += z; - } - /* LEFT side I/Os */ - if (0 == x) { - io_index = io_index_offset[io_side]; - for (size_t iy = 1; iy < y; ++iy) { - io_index += L_grids[x][iy].type->capacity; - } - io_index += z; - } - - return io_index; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.h deleted file mode 100644 index 5cdbd5049..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_benchmark_utils.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef FPGA_X2P_BENCHMARK_UTILS_H -#define FPGA_X2P_BENCHMARK_UTILS_H - -#include -#include -#include "vpr_types.h" -#include "vtr_geometry.h" - -std::vector find_benchmark_clock_port_name(const std::vector& L_logical_blocks); - -size_t find_benchmark_io_index(const t_logical_block& io_lb, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c deleted file mode 100644 index a4c87afa8..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c +++ /dev/null @@ -1,1653 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: fpga_x2p_bitstream_utils.c - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/07/02 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file contains most utilized functions for the bitstream generator - ***********************************************************************/ - -/***********************************/ -/* Synthesizable Verilog Dumping */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" - -/* FPGA-SPICE utils */ -#include "read_xml_spice_util.h" -#include "linkedlist.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_mux_utils.h" -#include "fpga_x2p_globals.h" - -#include "fpga_x2p_bitstream_utils.h" - -/* Determine the size of input address of a decoder */ -int determine_decoder_size(int num_addr_out) { - return ceil(log(num_addr_out)/log(2.)); -} - -static -int count_num_sram_bits_one_lut_spice_model(t_spice_model* cur_spice_model) { - int num_sram_bits = 0; - int iport; - int lut_size; - int num_input_port = 0; - t_spice_model_port** input_ports = NULL; - int num_sram_port = 0; - t_spice_model_port** sram_ports = NULL; - int lut_sram_port = 0; - int mode_sram_port = 0; - - assert(NULL != cur_spice_model); - assert(SPICE_MODEL_LUT == cur_spice_model->type); - - /* Check ports */ - input_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - assert(1 == num_input_port); - - /* Determine size of LUT*/ - lut_size = input_ports[0]->size; - - num_sram_bits = 0; - lut_sram_port = 0; - mode_sram_port = 0; - /* Total SRAM bit count = LUT SRAM bit + Mode bit */ - for (iport = 0; iport < num_sram_port; iport++) { - if (FALSE == sram_ports[iport]->mode_select) { - num_sram_bits += (int)pow(2.,(double)(lut_size)); - assert(num_sram_bits == sram_ports[iport]->size); - lut_sram_port++; - } else { - assert (TRUE == sram_ports[iport]->mode_select); - num_sram_bits += sram_ports[iport]->size; - mode_sram_port++; - } - } - assert (1 == lut_sram_port); - assert ((0 == mode_sram_port) || (1 == mode_sram_port)); - - /* TODO: could be more smart! Use mapped spice_model of SRAM ports! - * Support Non-volatile RRAM-based SRAM */ - switch (cur_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_RRAM: - /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, - * Number of memory bits is still same as CMOS SRAM - */ - break; - case SPICE_MODEL_DESIGN_CMOS: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - - /* Free */ - my_free(input_ports); - my_free(sram_ports); - - return num_sram_bits; -} - -static -int count_num_sram_bits_one_mux_spice_model(t_spice_model* cur_spice_model, - int mux_size) { - int num_sram_bits = 0; - int num_input_size = mux_size; - - assert(SPICE_MODEL_MUX == cur_spice_model->type); - - assert((2 == mux_size)||(2 < mux_size)); - - num_input_size = get_mux_full_input_size (cur_spice_model, mux_size); - - /* Number of configuration bits depends on the MUX structure */ - switch (cur_spice_model->design_tech_info.mux_info->structure) { - case SPICE_MODEL_STRUCTURE_TREE: - num_sram_bits = determine_tree_mux_level(num_input_size); - break; - case SPICE_MODEL_STRUCTURE_ONELEVEL: - num_sram_bits = num_input_size; - break; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - num_sram_bits = cur_spice_model->design_tech_info.mux_info->mux_num_level - * determine_num_input_basis_multilevel_mux(num_input_size, - cur_spice_model->design_tech_info.mux_info->mux_num_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - /* For 2:1 MUX, whatever structure, there is only one level */ - if (2 == num_input_size) { - num_sram_bits = 1; - } - /* Also the number of configuration bits depends on the technology*/ - switch (cur_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_RRAM: - /* 4T1R MUX requires more configuration bits */ - if (SPICE_MODEL_STRUCTURE_TREE == cur_spice_model->design_tech_info.mux_info->structure) { - /* For tree-structure: we need 3 times more config. bits */ - num_sram_bits = 3 * num_sram_bits; - } else if (SPICE_MODEL_STRUCTURE_MULTILEVEL == cur_spice_model->design_tech_info.mux_info->structure) { - /* For multi-level structure: we need 1 more config. bits for each level */ - num_sram_bits += cur_spice_model->design_tech_info.mux_info->mux_num_level; - } else { - num_sram_bits = (num_sram_bits + 1); - } - /* For 2:1 MUX, whatever structure, there is only one level */ - if (2 == num_input_size) { - num_sram_bits = 3; - } - break; - case SPICE_MODEL_DESIGN_CMOS: - /* When a local encoder is added, the number of sram bits will be reduced - * to N * log_2{X}, where N is the number of levels and X is the number of inputs per level - * Note that: we only apply this to one-level and multi-level multiplexers - */ - if ( (TRUE == cur_spice_model->design_tech_info.mux_info->local_encoder) - && (2 < num_input_size) ) { - if (SPICE_MODEL_STRUCTURE_ONELEVEL == cur_spice_model->design_tech_info.mux_info->structure) { - num_sram_bits = determine_mux_local_encoder_num_inputs(num_sram_bits); - } else if (SPICE_MODEL_STRUCTURE_MULTILEVEL == cur_spice_model->design_tech_info.mux_info->structure) { - num_sram_bits = cur_spice_model->design_tech_info.mux_info->mux_num_level * determine_mux_local_encoder_num_inputs(num_sram_bits / cur_spice_model->design_tech_info.mux_info->mux_num_level); - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - - /* Free */ - - return num_sram_bits; -} - -static -int count_num_sram_bits_one_generic_spice_model(t_spice_model* cur_spice_model) { - int iport; - int num_sram_bits = 0; - int num_sram_port = 0; - t_spice_model_port** sram_ports = NULL; - - /* Other block, we just count the number SRAM ports defined by user */ - sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - /* TODO: could be more smart! - * Support Non-volatile RRAM-based SRAM */ - if (0 < num_sram_port) { - assert(NULL != sram_ports); - } - for (iport = 0; iport < num_sram_port; iport++) { - assert(NULL != sram_ports[iport]->spice_model); - num_sram_bits += sram_ports[iport]->size; - /* TODO: could be more smart! - * Support Non-volatile RRAM-based SRAM */ - switch (cur_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_RRAM: - /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, - * Number of memory bits is still same as CMOS SRAM - */ - case SPICE_MODEL_DESIGN_CMOS: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - } - - /* Free */ - my_free(sram_ports); - - return num_sram_bits; -} - -/* Count the number of configuration bits of a spice model */ -int count_num_sram_bits_one_spice_model(t_spice_model* cur_spice_model, - int mux_size) { - assert(NULL != cur_spice_model); - - /* Only LUT and MUX requires configuration bits*/ - switch (cur_spice_model->type) { - case SPICE_MODEL_LUT: - return count_num_sram_bits_one_lut_spice_model(cur_spice_model); - case SPICE_MODEL_MUX: - return count_num_sram_bits_one_mux_spice_model(cur_spice_model, mux_size); - case SPICE_MODEL_WIRE: - case SPICE_MODEL_FF: - case SPICE_MODEL_SRAM: - case SPICE_MODEL_HARDLOGIC: - case SPICE_MODEL_CCFF: - case SPICE_MODEL_IOPAD: - return count_num_sram_bits_one_generic_spice_model(cur_spice_model); - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid spice_model_type!\n", __FILE__, __LINE__); - exit(1); - } - - return -1; -} - -static -int count_num_mode_bits_one_generic_spice_model(t_spice_model* cur_spice_model) { - int iport; - int num_mode_bits = 0; - int num_sram_port = 0; - t_spice_model_port** sram_ports = NULL; - - /* Other block, we just count the number SRAM ports defined by user */ - sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - /* TODO: could be more smart! - * Support Non-volatile RRAM-based SRAM */ - if (0 < num_sram_port) { - assert(NULL != sram_ports); - for (iport = 0; iport < num_sram_port; iport++) { - assert(NULL != sram_ports[iport]->spice_model); - if (FALSE == sram_ports[iport]->mode_select) { - continue; - } - num_mode_bits += sram_ports[iport]->size; - /* TODO: could be more smart! - * Support Non-volatile RRAM-based SRAM */ - switch (cur_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_RRAM: - /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, - * Number of memory bits is still same as CMOS SRAM - */ - case SPICE_MODEL_DESIGN_CMOS: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - } - } - - /* Free */ - my_free(sram_ports); - - return num_mode_bits; -} - - -/* Count the number of configuration bits of a spice model */ -int count_num_mode_bits_one_spice_model(t_spice_model* cur_spice_model) { - assert(NULL != cur_spice_model); - - /* Only LUT and MUX requires configuration bits*/ - switch (cur_spice_model->type) { - case SPICE_MODEL_LUT: - case SPICE_MODEL_MUX: - case SPICE_MODEL_WIRE: - case SPICE_MODEL_FF: - case SPICE_MODEL_SRAM: - case SPICE_MODEL_HARDLOGIC: - case SPICE_MODEL_CCFF: - case SPICE_MODEL_IOPAD: - return count_num_mode_bits_one_generic_spice_model(cur_spice_model); - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid spice_model_type!\n", __FILE__, __LINE__); - exit(1); - } - - return -1; -} - - -/* For a non-volatile SRAM, we determine its number of reserved conf. bits */ -int count_num_reserved_conf_bits_one_rram_sram_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type) { - int num_reserved_conf_bits = 0; - int num_bl_ports, num_wl_ports; - t_spice_model_port** bl_ports = NULL; - t_spice_model_port** wl_ports = NULL; - - /* Check */ - assert(SPICE_MODEL_SRAM == cur_spice_model->type); - - switch (cur_sram_orgz_type) { - case SPICE_SRAM_MEMORY_BANK: - find_bl_wl_ports_spice_model(cur_spice_model, - &num_bl_ports, &bl_ports, - &num_wl_ports, &wl_ports); - assert((1 == num_bl_ports)&&(1 == num_wl_ports)); - assert(bl_ports[0]->size == wl_ports[0]->size); - num_reserved_conf_bits = bl_ports[0]->size - 1; /*TODO: to be more smart: num_bl-1 of SRAM model ?*/ - break; - case SPICE_SRAM_SCAN_CHAIN: - case SPICE_SRAM_STANDALONE: - num_reserved_conf_bits = 0; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Free */ - my_free(bl_ports); - my_free(wl_ports); - - return num_reserved_conf_bits; -} - - -/* For a multiplexer, determine its reserved configuration bits */ -int count_num_reserved_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type) { - int num_reserved_conf_bits = 0; - int num_sram_port = 0; - t_spice_model_port** sram_ports = NULL; - int iport; - - /* Check */ - assert(SPICE_MODEL_LUT == cur_spice_model->type); - - /* Determine size of LUT*/ - sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - /* TODO: could be more smart! Use mapped spice_model of SRAM ports! - * Support Non-volatile RRAM-based SRAM */ - for (iport = 0; iport < num_sram_port; iport++) { - switch (sram_ports[iport]->spice_model->design_tech) { - case SPICE_MODEL_DESIGN_RRAM: - /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, - * In memory bank, by intensively share the Bit/Word Lines, - * we only need 1 additional BL and WL for each memory bit. - * Number of memory bits is still same as CMOS SRAM - */ - num_reserved_conf_bits = - count_num_reserved_conf_bits_one_rram_sram_spice_model(sram_ports[iport]->spice_model, - cur_sram_orgz_type); - break; - case SPICE_MODEL_DESIGN_CMOS: - num_reserved_conf_bits = 0; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - } - - /* Free */ - my_free(sram_ports); - - return num_reserved_conf_bits; -} - -/* For a multiplexer, determine its reserved configuration bits */ -int count_num_reserved_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type, - int mux_size) { - int num_reserved_conf_bits = 0; - int num_input_size = mux_size; - - /* Check */ - assert(SPICE_MODEL_MUX == cur_spice_model->type); - assert((2 == mux_size)||(2 < mux_size)); - - num_input_size = get_mux_full_input_size(cur_spice_model, mux_size); - - /* Number of configuration bits depends on the MUX structure */ - switch (cur_spice_model->design_tech_info.mux_info->structure) { - case SPICE_MODEL_STRUCTURE_TREE: - num_reserved_conf_bits = 2; - break; - case SPICE_MODEL_STRUCTURE_ONELEVEL: - num_reserved_conf_bits = num_input_size; - break; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - num_reserved_conf_bits = cur_spice_model->design_tech_info.mux_info->mux_num_level * - determine_num_input_basis_multilevel_mux(num_input_size, - cur_spice_model->design_tech_info.mux_info->mux_num_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - /* For 2:1 MUX, whatever structure, there is only one level */ - if (2 == num_input_size) { - num_reserved_conf_bits = 2; - } - /* Also the number of configuration bits depends on the technology*/ - switch (cur_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_RRAM: - switch (cur_sram_orgz_type) { - case SPICE_SRAM_MEMORY_BANK: - /* In memory bank, by intensively share the Bit/Word Lines, - * we only need 1 additional BL and WL for each MUX level. - */ - /* For 2:1 MUX, whatever structure, there is only one level */ - if (2 == num_input_size) { - num_reserved_conf_bits = 2; - } - break; - case SPICE_SRAM_SCAN_CHAIN: - case SPICE_SRAM_STANDALONE: - num_reserved_conf_bits = 0; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - break; - case SPICE_MODEL_DESIGN_CMOS: - num_reserved_conf_bits = 0; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - - return num_reserved_conf_bits; -} - - -int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type, - int mux_size) { - int num_reserved_conf_bits = 0; - int temp_num_reserved_conf_bits = 0; - int iport; - int num_sram_port = 0; - t_spice_model_port** sram_ports = NULL; - - assert(NULL != cur_spice_model); - - /* Only LUT and MUX requires configuration bits*/ - switch (cur_spice_model->type) { - case SPICE_MODEL_LUT: - num_reserved_conf_bits = - count_num_reserved_conf_bits_one_lut_spice_model(cur_spice_model, - cur_sram_orgz_type); - break; - case SPICE_MODEL_MUX: - num_reserved_conf_bits = - count_num_reserved_conf_bits_one_mux_spice_model(cur_spice_model, - cur_sram_orgz_type, - mux_size); - break; - case SPICE_MODEL_WIRE: - case SPICE_MODEL_FF: - case SPICE_MODEL_SRAM: - case SPICE_MODEL_HARDLOGIC: - case SPICE_MODEL_CCFF: - case SPICE_MODEL_IOPAD: - /* Other block, we just count the number SRAM ports defined by user */ - num_reserved_conf_bits = 0; - sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - /* TODO: could be more smart! - * Support Non-volatile RRAM-based SRAM */ - if (0 < num_sram_port) { - assert(NULL != sram_ports); - for (iport = 0; iport < num_sram_port; iport++) { - assert(NULL != sram_ports[iport]->spice_model); - /* TODO: could be more smart! - * Support Non-volatile RRAM-based SRAM */ - switch (sram_ports[iport]->spice_model->design_tech) { - case SPICE_MODEL_DESIGN_RRAM: - /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, - * Number of memory bits is still same as CMOS SRAM - */ - temp_num_reserved_conf_bits = - count_num_reserved_conf_bits_one_rram_sram_spice_model(sram_ports[iport]->spice_model, - cur_sram_orgz_type); - if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { - num_reserved_conf_bits = temp_num_reserved_conf_bits; - } - break; - case SPICE_MODEL_DESIGN_CMOS: - num_reserved_conf_bits = 0; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid spice_model_type!\n", __FILE__, __LINE__); - exit(1); - } - - /* Free */ - my_free(sram_ports); - - return num_reserved_conf_bits; -} - -static -int count_num_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type) { - int num_conf_bits = 0; - int iport; - int lut_size; - int num_input_port = 0; - t_spice_model_port** input_ports = NULL; - int num_sram_port = 0; - t_spice_model_port** sram_ports = NULL; - int lut_sram_port = 0; - int mode_sram_port = 0; - - assert(NULL != cur_spice_model); - assert(SPICE_MODEL_LUT == cur_spice_model->type); - - /* Determine size of LUT*/ - input_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - assert(1 == num_input_port); - lut_size = input_ports[0]->size; - - /* Check lut sram bits and mode bits */ - num_conf_bits = 0; - lut_sram_port = 0; - mode_sram_port = 0; - /* Total SRAM bit count = LUT SRAM bit + Mode bit */ - for (iport = 0; iport < num_sram_port; iport++) { - if (FALSE == sram_ports[iport]->mode_select) { - num_conf_bits += (int)pow(2.,(double)(lut_size)); - assert(num_conf_bits == sram_ports[iport]->size); - lut_sram_port++; - } else { - assert (TRUE == sram_ports[iport]->mode_select); - num_conf_bits += sram_ports[iport]->size; - mode_sram_port++; - } - } - assert (1 == lut_sram_port); - assert ((0 == mode_sram_port) || (1 == mode_sram_port)); - - /* TODO: could be more smart! Use mapped spice_model of SRAM ports! - * Support Non-volatile RRAM-based SRAM */ - switch (sram_ports[0]->spice_model->design_tech) { - case SPICE_MODEL_DESIGN_RRAM: - /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, - * In memory bank, by intensively share the Bit/Word Lines, - * we only need 1 additional BL and WL for each memory bit. - * Number of memory bits is still same as CMOS SRAM - */ - switch (cur_sram_orgz_type) { - case SPICE_SRAM_MEMORY_BANK: - break; - case SPICE_SRAM_SCAN_CHAIN: - case SPICE_SRAM_STANDALONE: - num_conf_bits = 2 * num_conf_bits; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - break; - case SPICE_MODEL_DESIGN_CMOS: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - - /* Free */ - my_free(input_ports); - my_free(sram_ports); - - return num_conf_bits; -} - -static -int count_num_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type, - int mux_size) { - int num_conf_bits = 0; - int num_input_size = mux_size; - - assert(NULL != cur_spice_model); - assert(SPICE_MODEL_MUX == cur_spice_model->type); - - assert((2 == mux_size)||(2 < mux_size)); - - num_input_size = get_mux_full_input_size(cur_spice_model, mux_size); - - /* Number of configuration bits depends on the MUX structure */ - switch (cur_spice_model->design_tech_info.mux_info->structure) { - case SPICE_MODEL_STRUCTURE_TREE: - num_conf_bits = determine_tree_mux_level(num_input_size); - break; - case SPICE_MODEL_STRUCTURE_ONELEVEL: - num_conf_bits = num_input_size; - break; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - num_conf_bits = cur_spice_model->design_tech_info.mux_info->mux_num_level - * determine_num_input_basis_multilevel_mux(num_input_size, - cur_spice_model->design_tech_info.mux_info->mux_num_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - /* For 2:1 MUX, whatever structure, there is only one level */ - if (2 == num_input_size) { - num_conf_bits = 1; - } - /* Also the number of configuration bits depends on the technology*/ - switch (cur_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_RRAM: - switch (cur_sram_orgz_type) { - case SPICE_SRAM_MEMORY_BANK: - /* In memory bank, by intensively share the Bit/Word Lines, - * we only need 1 additional BL and WL for each MUX level. - */ - num_conf_bits = cur_spice_model->design_tech_info.mux_info->mux_num_level; - /* For 2:1 MUX, whatever structure, there is only one level */ - if (2 == num_input_size) { - num_conf_bits = 1; - } - break; - case SPICE_SRAM_SCAN_CHAIN: - case SPICE_SRAM_STANDALONE: - /* Currently we keep the same as CMOS MUX */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - break; - case SPICE_MODEL_DESIGN_CMOS: - /* When a local encoder is added, the number of sram bits will be reduced - * to N * log_2{X}, where N is the number of levels and X is the number of inputs per level - * Note that: we only apply this to one-level and multi-level multiplexers - */ - if ( (TRUE == cur_spice_model->design_tech_info.mux_info->local_encoder) - && (2 < num_input_size) ) { - if (SPICE_MODEL_STRUCTURE_ONELEVEL == cur_spice_model->design_tech_info.mux_info->structure) { - num_conf_bits = determine_mux_local_encoder_num_inputs(num_conf_bits); - } else if (SPICE_MODEL_STRUCTURE_MULTILEVEL == cur_spice_model->design_tech_info.mux_info->structure) { - num_conf_bits = cur_spice_model->design_tech_info.mux_info->mux_num_level * determine_mux_local_encoder_num_inputs(num_conf_bits / cur_spice_model->design_tech_info.mux_info->mux_num_level); - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - - /* Free */ - - return num_conf_bits; -} - -static -int count_num_conf_bits_one_generic_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type) { - int num_conf_bits = 0; - int iport; - int num_sram_port = 0; - t_spice_model_port** sram_ports = NULL; - - assert(NULL != cur_spice_model); - - /* Other block, we just count the number SRAM ports defined by user */ - num_conf_bits = 0; - sram_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - /* TODO: could be more smart! - * Support Non-volatile RRAM-based SRAM */ - if (0 < num_sram_port) { - assert(NULL != sram_ports); - for (iport = 0; iport < num_sram_port; iport++) { - assert(NULL != sram_ports[iport]->spice_model); - /* TODO: could be more smart! - * Support Non-volatile RRAM-based SRAM */ - switch (sram_ports[iport]->spice_model->design_tech) { - case SPICE_MODEL_DESIGN_RRAM: - /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, - * Number of memory bits is still same as CMOS SRAM - */ - switch (cur_sram_orgz_type) { - case SPICE_SRAM_MEMORY_BANK: - num_conf_bits += sram_ports[iport]->size; - break; - case SPICE_SRAM_SCAN_CHAIN: - case SPICE_SRAM_STANDALONE: - num_conf_bits += sram_ports[iport]->size; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - break; - case SPICE_MODEL_DESIGN_CMOS: - /* Non-volatile SRAM requires 2 BLs and 2 WLs for each 1 memory bit, - * Number of memory bits is still same as CMOS SRAM - */ - switch (cur_sram_orgz_type) { - case SPICE_SRAM_MEMORY_BANK: - num_conf_bits += sram_ports[iport]->size; - break; - case SPICE_SRAM_SCAN_CHAIN: - case SPICE_SRAM_STANDALONE: - num_conf_bits += sram_ports[iport]->size; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of LUT(name: %s)\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - } - } - - /* Free */ - my_free(sram_ports); - - return num_conf_bits; -} - - - -/* Count the number of configuration bits of a spice model */ -int count_num_conf_bits_one_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type, - int mux_size) { - assert(NULL != cur_spice_model); - - /* Only LUT and MUX requires configuration bits*/ - switch (cur_spice_model->type) { - case SPICE_MODEL_LUT: - return count_num_conf_bits_one_lut_spice_model(cur_spice_model, cur_sram_orgz_type); - case SPICE_MODEL_MUX: - return count_num_conf_bits_one_mux_spice_model(cur_spice_model, cur_sram_orgz_type, mux_size); - case SPICE_MODEL_WIRE: - case SPICE_MODEL_FF: - case SPICE_MODEL_SRAM: - case SPICE_MODEL_HARDLOGIC: - case SPICE_MODEL_CCFF: - case SPICE_MODEL_IOPAD: - return count_num_conf_bits_one_generic_spice_model(cur_spice_model, cur_sram_orgz_type); - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid spice_model_type!\n", __FILE__, __LINE__); - exit(1); - } - return -1; -} - -int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc, - enum e_sram_orgz cur_sram_orgz_type) { - int fan_in = 0; - enum e_interconnect spice_interc_type = DIRECT_INTERC; - - int num_reserved_conf_bits = 0; - int temp_num_reserved_conf_bits = 0; - - /* 1. identify pin interconnection type, - * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) - * 3. Select and print the SPICE netlist - */ - if (NULL == cur_interc) { - return num_reserved_conf_bits; - } else { - fan_in = cur_interc->fan_in; - if (0 == fan_in) { - return num_reserved_conf_bits; - } - } - /* Initialize the interconnection type that will be implemented in SPICE netlist*/ - switch (cur_interc->type) { - case DIRECT_INTERC: - assert(cur_interc->fan_out == fan_in); - spice_interc_type = DIRECT_INTERC; - break; - case COMPLETE_INTERC: - if (1 == fan_in) { - spice_interc_type = DIRECT_INTERC; - } else { - assert((2 == fan_in)||(2 < fan_in)); - spice_interc_type = MUX_INTERC; - } - break; - case MUX_INTERC: - assert((2 == fan_in)||(2 < fan_in)); - spice_interc_type = MUX_INTERC; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", - __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); - exit(1); - } - /* This time, (2nd round), count the number of configuration bits, according to interc type*/ - switch (spice_interc_type) { - case DIRECT_INTERC: - /* Check : - * 1. Direct interc has only one fan-in! - */ - assert((cur_interc->fan_out == fan_in) - ||((COMPLETE_INTERC == cur_interc->type)&&(1 == fan_in))); - break; - case COMPLETE_INTERC: - case MUX_INTERC: - /* Check : - * MUX should have at least 2 fan_in - */ - assert((2 == fan_in)||(2 < fan_in)); - assert((1 == cur_interc->fan_out)||(1 < cur_interc->fan_out)); - /* 2. spice_model is a wire */ - assert(NULL != cur_interc->spice_model); - assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); - temp_num_reserved_conf_bits = count_num_reserved_conf_bits_one_spice_model(cur_interc->spice_model, - cur_sram_orgz_type, fan_in); - /* FOR COMPLETE_INTERC: we should consider fan_out number ! */ - if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { - num_reserved_conf_bits = temp_num_reserved_conf_bits; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", - __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); - exit(1); - } - return num_reserved_conf_bits; -} - -/* add configuration bits of a MUX to linked-list - * when SRAM organization type is scan-chain */ -void -add_mux_ccff_conf_bits_to_llist(int mux_size, - t_sram_orgz_info* cur_sram_orgz_info, - int num_mux_sram_bits, int* mux_sram_bits, - t_spice_model* mux_spice_model) { - int ibit, cur_mem_bit; - t_conf_bit** sram_bit = NULL; - - /* Assert*/ - assert(NULL != cur_sram_orgz_info); - assert(NULL != mux_spice_model); - - cur_mem_bit = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - - /* Depend on the design technology of mux_spice_model - * Fill the conf_bits information */ - switch (mux_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - case SPICE_MODEL_DESIGN_RRAM: - /* Count how many configuration bits need to program - * Scan-chain needs to know each memory bit whatever it is 0 or 1 - */ - /* Allocate the array */ - sram_bit = (t_conf_bit**)my_malloc(num_mux_sram_bits * sizeof(t_conf_bit*)); - for (ibit = 0; ibit < num_mux_sram_bits; ibit++) { - sram_bit[ibit] = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); - } - /* Fill the array: sram_bit */ - for (ibit = 0; ibit < num_mux_sram_bits; ibit++) { - sram_bit[ibit]->addr = cur_mem_bit + ibit; - sram_bit[ibit]->val = mux_sram_bits[ibit]; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid design technology!", - __FILE__, __LINE__ ); - exit(1); - } - - /* Fill the linked list */ - for (ibit = 0; ibit < num_mux_sram_bits; ibit++) { - cur_sram_orgz_info->conf_bit_head = - add_conf_bit_info_to_llist(cur_sram_orgz_info->conf_bit_head, cur_mem_bit + ibit, - sram_bit[ibit], NULL, NULL, - mux_spice_model); - } - - /* Free */ - my_free(sram_bit); - - return; -} - -/* add configuration bits of a MUX to linked-list - * when SRAM organization type is scan-chain */ -void -add_mux_membank_conf_bits_to_llist(int mux_size, - t_sram_orgz_info* cur_sram_orgz_info, - int num_mux_sram_bits, int* mux_sram_bits, - t_spice_model* mux_spice_model) { - int ibit, cur_mem_bit, num_conf_bits, cur_bit, cur_bl, cur_wl; - int ilevel; - int num_bl_enabled, num_wl_enabled; - t_conf_bit** wl_bit = NULL; - t_conf_bit** bl_bit = NULL; - - /* Assert*/ - assert(NULL != cur_sram_orgz_info); - assert(NULL != mux_spice_model); - - cur_mem_bit = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); - - /* Depend on the design technology of mux_spice_model - * Fill the conf_bits information */ - switch (mux_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - /* Count how many configuration bits need to program - * Assume all the SRAMs are zero initially. - * only Configuration to bit 1 requires a programming operation - */ - num_conf_bits = num_mux_sram_bits; - /* Allocate the array */ - bl_bit = (t_conf_bit**)my_malloc(num_mux_sram_bits * sizeof(t_conf_bit*)); - wl_bit = (t_conf_bit**)my_malloc(num_mux_sram_bits * sizeof(t_conf_bit*)); - for (ibit = 0; ibit < num_mux_sram_bits; ibit++) { - bl_bit[ibit] = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); - wl_bit[ibit] = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); - } - /* SRAMs are typically organized in an array where BLs and WLs are efficiently shared - * Actual BL/WL address in the array is hard to predict here, - * they will be handled in the top_netlist and top_testbench generation - */ - for (ibit = 0; ibit < num_mux_sram_bits; ibit++) { - bl_bit[ibit]->addr = cur_mem_bit + ibit; - bl_bit[ibit]->val = mux_sram_bits[ibit]; - wl_bit[ibit]->addr = cur_mem_bit + ibit; - wl_bit[ibit]->val = 1; /* We always assume WL is the write enable signal of a SRAM */ - } - break; - case SPICE_MODEL_DESIGN_RRAM: - /* Count how many configuration bits need to program - * only BL and WL are both 1 requires a programming operation - * Each level of a MUX requires 1 RRAM to be configured. - * Therefore, the number of configuration bits should be num_mux_levels - */ - num_bl_enabled = 0; - /* Check how many Bit lines are 1 */ - for (ibit = 0; ibit < num_mux_sram_bits/2; ibit++) { - if (1 == mux_sram_bits[ibit]) { - num_bl_enabled++; - } - } - num_wl_enabled = 0; - /* Check how many Word lines are 1 */ - for (ibit = 0; ibit < num_mux_sram_bits/2; ibit++) { - if (1 == mux_sram_bits[ibit + num_mux_sram_bits/2]) { - num_wl_enabled++; - } - } - /* The number of enabled Bit and Word lines should be the same */ - assert(num_bl_enabled == num_wl_enabled); - /* Assign num_conf_bits */ - num_conf_bits = num_bl_enabled; - /* Allocate the array */ - bl_bit = (t_conf_bit**)my_malloc(num_conf_bits * sizeof(t_conf_bit*)); - wl_bit = (t_conf_bit**)my_malloc(num_conf_bits * sizeof(t_conf_bit*)); - for (ibit = 0; ibit < num_conf_bits; ibit++) { - bl_bit[ibit] = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); - wl_bit[ibit] = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); - } - /* For one-level RRAM MUX: - * There should be only 1 BL and 1 WL whose value is 1 - * First half of mux_sram_bits are BL, the rest are WL - * For multi-level RRAM MUX: - * There could be more than 1 BL and 1 WL whose value is 1 - * We need to divde the mux_sram_bits into small part, - * each part has only 1 BL and 1 WL whose value is 1 - */ - /* Assign bit lines address and values */ - cur_bit = 0; - /* We slice the BL part of array mux_sram_bits to N=num_conf_bits parts */ - for (ilevel = 0; ilevel < num_conf_bits; ilevel++) { - for (ibit = ilevel * num_mux_sram_bits/(2*num_conf_bits); /* Start address of each slice*/ - ibit < (ilevel + 1) * num_mux_sram_bits/(2*num_conf_bits); /* End address of each slice*/ - ibit++) { - if (0 == mux_sram_bits[ibit]) { - continue; /* Skip non-zero bits */ - } - assert(1 == mux_sram_bits[ibit]); - if (ibit == (ilevel + 1) * num_mux_sram_bits/(2*num_conf_bits) - 1) { - bl_bit[cur_bit]->addr = cur_bl + ilevel; - /* Last conf_bit should use a new BL/WL */ - } else { - /* First part of conf_bit should use reserved BL/WL */ - bl_bit[cur_bit]->addr = ibit; - } - bl_bit[cur_bit]->val = mux_sram_bits[ibit]; - cur_bit++; - } - } - assert(num_conf_bits == cur_bit); - /* Assign Word lines address and values */ - cur_bit = 0; - for (ilevel = 0; ilevel < num_conf_bits; ilevel++) { - for (ibit = num_mux_sram_bits/2 + ilevel * num_mux_sram_bits/(2*num_conf_bits); /* Start address of each slice*/ - ibit < num_mux_sram_bits/2 + (ilevel + 1) * num_mux_sram_bits/(2*num_conf_bits); /* End address of each slice*/ - ibit++) { - if (0 == mux_sram_bits[ibit]) { - continue; /* Skip non-zero bits */ - } - assert(1 == mux_sram_bits[ibit]); - if (ibit == num_mux_sram_bits/2 + (ilevel + 1) * num_mux_sram_bits/(2*num_conf_bits) - 1) { - wl_bit[cur_bit]->addr = cur_wl + ilevel; - /* Last conf_bit should use a new BL/WL */ - } else { - /* First part of conf_bit should use reserved BL/WL */ - wl_bit[cur_bit]->addr = ibit; - } - wl_bit[cur_bit]->val = mux_sram_bits[ibit]; - cur_bit++; - } - } - assert(num_conf_bits == cur_bit); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid design technology!", - __FILE__, __LINE__ ); - exit(1); - } - - /* Fill the linked list */ - for (ibit = 0; ibit < num_conf_bits; ibit++) { - cur_sram_orgz_info->conf_bit_head = - add_conf_bit_info_to_llist(cur_sram_orgz_info->conf_bit_head, cur_mem_bit + ibit, - NULL, bl_bit[ibit], wl_bit[ibit], - mux_spice_model); - } - - /* Free */ - my_free(bl_bit); - my_free(wl_bit); - - return; -} - -/* Should we return a value ? */ -void -add_mux_conf_bits_to_llist(int mux_size, - t_sram_orgz_info* cur_sram_orgz_info, - int num_mux_sram_bits, int* mux_sram_bits, - t_spice_model* mux_spice_model) { - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - case SPICE_SRAM_SCAN_CHAIN: - add_mux_ccff_conf_bits_to_llist(mux_size, cur_sram_orgz_info, - num_mux_sram_bits, mux_sram_bits, - mux_spice_model); - break; - case SPICE_SRAM_MEMORY_BANK: - add_mux_membank_conf_bits_to_llist(mux_size, cur_sram_orgz_info, - num_mux_sram_bits, mux_sram_bits, - mux_spice_model); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -/* Add CCFF configutration bits to a linked list*/ -static -void add_sram_ccff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, - int num_sram_bits, int* sram_bits) { - int ibit, cur_mem_bit; - t_conf_bit** sram_bit = NULL; - t_spice_model* cur_sram_spice_model = NULL; - - /* Assert*/ - assert(NULL != cur_sram_orgz_info); - - cur_mem_bit = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - - /* Get memory model */ - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &cur_sram_spice_model); - assert(NULL != cur_sram_spice_model); - - /* Count how many configuration bits need to program - * Scan-chain needs to know each memory bit whatever it is 0 or 1 - */ - /* Allocate the array */ - sram_bit = (t_conf_bit**)my_malloc(num_sram_bits * sizeof(t_conf_bit*)); - for (ibit = 0; ibit < num_sram_bits; ibit++) { - sram_bit[ibit] = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); - } - /* Fill the array: sram_bit */ - for (ibit = 0; ibit < num_sram_bits; ibit++) { - sram_bit[ibit]->addr = cur_mem_bit + ibit; - sram_bit[ibit]->val = sram_bits[ibit]; - } - - /* Fill the linked list */ - for (ibit = 0; ibit < num_sram_bits; ibit++) { - cur_sram_orgz_info->conf_bit_head = - add_conf_bit_info_to_llist(cur_sram_orgz_info->conf_bit_head, cur_mem_bit + ibit, - sram_bit[ibit], NULL, NULL, - cur_sram_spice_model); - } - - /* Free */ - my_free(sram_bit); - - return; -} - - -/* Add SRAM configuration bits in memory bank organization to a linked list */ -void add_sram_membank_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, - int num_bls, int num_wls, - int* bl_conf_bits, int* wl_conf_bits) { - int ibit, cur_bl, cur_wl; - t_spice_model* cur_sram_spice_model = NULL; - t_conf_bit* bl_bit = NULL; - t_conf_bit* wl_bit = NULL; - int bit_cnt = 0; - - /* Assert*/ - assert(NULL != cur_sram_orgz_info); - - /* Get current counter of sram_spice_model */ - get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); - - /* Get memory model */ - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &cur_sram_spice_model); - assert(NULL != cur_sram_spice_model); - - /* Malloc */ - bl_bit = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); - wl_bit = (t_conf_bit*)my_malloc(sizeof(t_conf_bit)); - - /* Depend on the memory technology, we have different configuration bits */ - switch (cur_sram_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - assert((1 == num_bls)&&(1 == num_wls)); - bl_bit->addr = mem_index; - wl_bit->addr = mem_index; - bl_bit->val = bl_conf_bits[0]; - wl_bit->val = wl_conf_bits[0]; - break; - case SPICE_MODEL_DESIGN_RRAM: - /* Fill information */ - bit_cnt = 0; /* Check counter */ - for (ibit = 0; ibit < num_bls; ibit++) { - /* Bypass zero bit */ - if (0 == bl_conf_bits[ibit]) { - continue; - } - /* Check if this bit is in reserved bls */ - if (ibit == num_bls - 1) { - /* Last bit is always independent */ - bl_bit->addr = mem_index; - bl_bit->val = 1; - } else { - /* Other bits are shared */ - bl_bit->addr = ibit; - bl_bit->val = 1; - } - /* Update check counter */ - bit_cnt++; - } - /* Check */ - assert(1 == bit_cnt); - - bit_cnt = 0; /* Check counter */ - for (ibit = 0; ibit < num_wls; ibit++) { - /* Bypass zero bit */ - if (0 == wl_conf_bits[ibit]) { - continue; - } - /* Check if this bit is in reserved bls */ - if (ibit == num_wls - 1) { - /* Last bit is always independent */ - wl_bit->addr = mem_index; - wl_bit->val = 1; - } else { - /* Other bits are shared */ - wl_bit->addr = ibit; - wl_bit->val = 1; - } - /* Update check counter */ - bit_cnt++; - } - /* Check */ - assert(1 == bit_cnt); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid design technology!", - __FILE__, __LINE__); - exit(1); - } - - /* Fill the linked list */ - cur_sram_orgz_info->conf_bit_head = - add_conf_bit_info_to_llist(cur_sram_orgz_info->conf_bit_head, mem_index, - NULL, bl_bit, wl_bit, - cur_sram_spice_model); - - return; -} - -/* Add SRAM configuration bits to a linked list */ -void -add_sram_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, - int num_sram_bits, int* sram_bits) { - int num_bls, num_wls; - int* bl_conf_bits = NULL; - int* wl_conf_bits = NULL; - - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - case SPICE_SRAM_SCAN_CHAIN: - add_sram_ccff_conf_bits_to_llist(cur_sram_orgz_info, - num_sram_bits, sram_bits); - break; - case SPICE_SRAM_MEMORY_BANK: - /* Initialize parameters */ - /* Number of BLs should be same as WLs */ - num_bls = num_sram_bits/2; - num_wls = num_sram_bits/2; - /* Convention: first part of Array (sram_bits) is BL configuration bits, - * second part is WL configuration bits. - */ - bl_conf_bits = sram_bits; - wl_conf_bits = sram_bits + num_bls; - add_sram_membank_conf_bits_to_llist(cur_sram_orgz_info, mem_index, - num_bls, num_wls, - bl_conf_bits, wl_conf_bits); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__); - exit(1); - } - - return; -} - - -/* Decode BL and WL bits for a SRAM - * SRAM could be - * 1. NV SRAM - * or - * 2. SRAM - */ -void decode_memory_bank_sram(t_spice_model* cur_sram_spice_model, int sram_bit, - int bl_len, int wl_len, int bl_offset, int wl_offset, - int* bl_conf_bits, int* wl_conf_bits) { - int i; - - /* Check */ - assert(NULL != cur_sram_spice_model); - assert(NULL != bl_conf_bits); - assert(NULL != wl_conf_bits); - assert((1 == sram_bit)||(0 == sram_bit)); - - /* All the others should be zero */ - for (i = 0; i < bl_len; i++) { - bl_conf_bits[i] = 0; - } - for (i = 0; i < wl_len; i++) { - wl_conf_bits[i] = 0; - } - - /* Depending on the design technology of SRAM */ - switch (cur_sram_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - /* CMOS SRAM */ - /* Make sure there is only 1 BL and 1 WL */ - assert((1 == bl_len)&&(1 == wl_len)); - /* We always assume that WL is a write-enable signal - * While BL contains what data will be written into SRAM - */ - bl_conf_bits[0] = sram_bit; - wl_conf_bits[0] = 1; - break; - case SPICE_MODEL_DESIGN_RRAM: - /* NV SRAM (RRAM-based) */ - /* We need at least 2 BLs and 2 WLs but no more than 3, See schematic in manual */ - /* Whatever the number of BLs and WLs, (RRAM0) - * when sram bit is 1, last bit of BL should be enabled - * while first bit of WL should be enabled at the same time - * when sram bit is 0, last bit of WL should be enabled - * while first bit of BL should be enabled at the same time - */ - assert((1 < bl_len)&&(bl_len < 4)); - assert((1 < wl_len)&&(wl_len < 4)); - assert((-1 < bl_offset)&&(bl_offset < bl_len)); - assert((-1 < wl_offset)&&(wl_offset < wl_len)); - /* In addition, we will may need two programing cycles. - * The first cycle is dedicated to programming RRAM0 - * The second cycle is dedicated to programming RRAM1 - */ - if (1 == sram_bit) { - bl_conf_bits[bl_len-1] = 1; - wl_conf_bits[0 + wl_offset] = 1; - } else { - assert(0 == sram_bit); - bl_conf_bits[0 + bl_offset] = 1; - wl_conf_bits[wl_len-1] = 1; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for SRAM!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -/* Decode one SRAM bit for memory-bank-style configuration circuit, and add it to linked list */ -void -decode_and_add_sram_membank_conf_bit_to_llist(t_sram_orgz_info* cur_sram_orgz_info, - int mem_index, - int num_bl_per_sram, int num_wl_per_sram, - int cur_sram_bit) { - int j; - int* conf_bits_per_sram = NULL; - t_spice_model* mem_model = NULL; - - /* Check */ - assert( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type ); - - /* Get memory model */ - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); - assert(NULL != mem_model); - - /* Malloc/Calloc */ - conf_bits_per_sram = (int*)my_calloc(num_bl_per_sram + num_wl_per_sram, sizeof(int)); - - /* Depend on the memory technology, we have different configuration bits */ - switch (mem_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - /* Check */ - assert((1 == num_bl_per_sram) && (1 == num_wl_per_sram)); - /* For CMOS SRAM */ - decode_memory_bank_sram(mem_model, cur_sram_bit, - num_bl_per_sram, num_wl_per_sram, 0, 0, - conf_bits_per_sram, conf_bits_per_sram + num_bl_per_sram); - /* Use memory model here! Design technology of memory model determines the decoding strategy, instead of LUT model*/ - add_sram_conf_bits_to_llist(cur_sram_orgz_info, mem_index, - num_bl_per_sram + num_wl_per_sram, conf_bits_per_sram); - break; - case SPICE_MODEL_DESIGN_RRAM: - /* Decode the SRAM bits to BL/WL bits. - * first half part is BL, the other half part is WL - */ - /* Store the configuraion bit to linked-list */ - assert(num_bl_per_sram == num_wl_per_sram); - /* When the number of BL/WL is more than 1, we need multiple programming cycles to configure a SRAM */ - /* ONLY valid for NV SRAM !!!*/ - for (j = 0; j < num_bl_per_sram - 1; j++) { - if (0 == j) { - /* Store the configuraion bit to linked-list */ - decode_memory_bank_sram(mem_model, cur_sram_bit, - num_bl_per_sram, num_wl_per_sram, j, j, - conf_bits_per_sram, conf_bits_per_sram + num_bl_per_sram); - } else { - /* Store the configuraion bit to linked-list */ - decode_memory_bank_sram(mem_model, 1 - cur_sram_bit, - num_bl_per_sram, num_wl_per_sram, j, j, - conf_bits_per_sram, conf_bits_per_sram + num_bl_per_sram); - } - /* Use memory model here! Design technology of memory model determines the decoding strategy, instead of LUT model*/ - add_sram_conf_bits_to_llist(cur_sram_orgz_info, mem_index, - num_bl_per_sram + num_wl_per_sram, conf_bits_per_sram); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid design technology!", - __FILE__, __LINE__); - exit(1); - } - - /* Free */ - my_free(conf_bits_per_sram); - - return; -} - -void determine_blwl_decoder_size(INP t_sram_orgz_info* cur_sram_orgz_info, - OUTP int* num_array_bl, OUTP int* num_array_wl, - OUTP int* bl_decoder_size, OUTP int* wl_decoder_size) { - t_spice_model* mem_model = NULL; - int num_reserved_bl, num_reserved_wl; - - /* Check */ - assert(SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type); - - get_sram_orgz_info_num_blwl(cur_sram_orgz_info, num_array_bl, num_array_wl); - get_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, &num_reserved_bl, &num_reserved_wl); - - /* Sizes of decodes depend on the Memory technology */ - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); - switch (mem_model->design_tech) { - /* CMOS SRAM*/ - case SPICE_MODEL_DESIGN_CMOS: - /* SRAMs can efficiently share BLs and WLs, - * Actual number of BLs and WLs will be sqrt(num_bls) and sqrt(num_wls) - */ - assert(0 == num_reserved_bl); - assert(0 == num_reserved_wl); - (*num_array_bl) = ceil(sqrt(*num_array_bl)); - (*num_array_wl) = ceil(sqrt(*num_array_wl)); - (*bl_decoder_size) = determine_decoder_size(*num_array_bl); - (*wl_decoder_size) = determine_decoder_size(*num_array_wl); - break; - /* RRAM */ - case SPICE_MODEL_DESIGN_RRAM: - /* Currently we do not have more efficient way to share the BLs and WLs as CMOS SRAMs */ - (*bl_decoder_size) = determine_decoder_size(*num_array_bl); - (*wl_decoder_size) = determine_decoder_size(*num_array_wl); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology [CMOS|RRAM] for memory technology!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -void init_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, - int num_switch, - t_switch_inf* switches, - t_spice* spice, - t_det_routing_arch* routing_arch) { - - /* We have linked list whichs stores spice model information of multiplexer*/ - t_llist* muxes_head = NULL; - t_llist* temp = NULL; - t_spice_mux_model* cur_spice_mux_model = NULL; - int max_routing_mux_size = -1; - - /* Alloc the muxes*/ - muxes_head = stats_spice_muxes(num_switch, switches, spice, routing_arch); - - temp = muxes_head; - while(temp) { - assert(NULL != temp->dptr); - cur_spice_mux_model = (t_spice_mux_model*)(temp->dptr); - /* Exclude LUT MUX from this statistics */ - if ((SPICE_MODEL_MUX == cur_spice_mux_model->spice_model->type) - &&((-1 == max_routing_mux_size)||(max_routing_mux_size < cur_spice_mux_model->size))) { - max_routing_mux_size = cur_spice_mux_model->size; - } - /* Move on to the next*/ - temp = temp->next; - } - - try_update_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, - max_routing_mux_size, max_routing_mux_size); - - vpr_printf(TIO_MESSAGE_INFO,"Detected %d reserved BLs and% d reserved WLs...\n", - max_routing_mux_size, max_routing_mux_size); - - /* remember to free the linked list*/ - free_muxes_llist(muxes_head); - - return; -} - -void add_one_conf_bit_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info) { - int cur_num_sram = 0; - int cur_bl, cur_wl; - - /* Get current index of SRAM module */ - cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_MEMORY_BANK: - get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); - /* Update the counter */ - update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, - cur_num_sram + 1); - update_sram_orgz_info_num_blwl(cur_sram_orgz_info, - cur_bl + 1, - cur_wl + 1); - break; - case SPICE_SRAM_STANDALONE: - /* Update the counter */ - update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, - cur_num_sram + 1); - break; - case SPICE_SRAM_SCAN_CHAIN: - /* Update the counter */ - update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, - cur_num_sram + 1); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -void add_sram_conf_bits_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, - t_spice_model* cur_spice_model) { - int i; - int num_sram; - - /* Synchronize the internal counters of sram_orgz_info with generated bitstreams*/ - num_sram = count_num_sram_bits_one_spice_model(cur_spice_model, -1); - for (i = 0; i < num_sram; i++) { - add_one_conf_bit_to_sram_orgz_info(cur_sram_orgz_info); /* use the mem_model in cur_sram_orgz_info */ - } - - return; -} - -void add_mux_conf_bits_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, - t_spice_model* mux_spice_model, int mux_size) { - int i; - int num_mux_sram_bits, num_mux_conf_bits; - int cur_num_sram, cur_bl, cur_wl; - - /* cur_num_sram = sram_verilog_model->cnt; */ - cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); - - /* Get the number of configuration bits required by this MUX */ - num_mux_sram_bits = count_num_sram_bits_one_spice_model(mux_spice_model, mux_size); - - num_mux_conf_bits = count_num_conf_bits_one_spice_model(mux_spice_model, - cur_sram_orgz_info->type, - mux_size); - - /* Synchronize sram_orgz_info by incrementing its internal counters */ - switch (mux_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - /* SRAM-based MUX required dumping SRAMs! */ - for (i = 0; i < num_mux_sram_bits; i++) { - add_one_conf_bit_to_sram_orgz_info(cur_sram_orgz_info); /* use the mem_model in sram_verilog_orgz_info */ - } - break; - case SPICE_MODEL_DESIGN_RRAM: - /* RRAM-based MUX does not need any SRAM dumping - * But we have to get the number of configuration bits required by this MUX - * and update the number of memory bits - */ - update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); - update_sram_orgz_info_num_blwl(cur_sram_orgz_info, - cur_bl + num_mux_conf_bits, - cur_wl + num_mux_conf_bits); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", - __FILE__, __LINE__, mux_spice_model->name); - } - - return; -} - -/************************************************************************ - * End of file : fpga_x2p_bitstream_utils.c - ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h deleted file mode 100644 index e32bb520a..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h +++ /dev/null @@ -1,87 +0,0 @@ -#ifndef FPGA_X2P_BITSTREAM_UTILS_H -#define FPGA_X2P_BITSTREAM_UTILS_H - -int determine_decoder_size(int num_addr_out); - -int count_num_sram_bits_one_spice_model(t_spice_model* cur_spice_model, - int mux_size); - -int count_num_conf_bits_one_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type, - int mux_size); - -int count_num_mode_bits_one_spice_model(t_spice_model* cur_spice_model); - -int count_num_reserved_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type); - -int count_num_reserved_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type, - int mux_size); - -int count_num_reserved_conf_bits_one_rram_sram_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type); - -int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model, - enum e_sram_orgz cur_sram_orgz_type, - int mux_size); - -int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc, - enum e_sram_orgz cur_sram_orgz_type); - -void -add_mux_ccff_conf_bits_to_llist(int mux_size, - t_sram_orgz_info* cur_sram_orgz_info, - int num_mux_sram_bits, int* mux_sram_bits, - t_spice_model* mux_spice_model); - -void -add_mux_membank_conf_bits_to_llist(int mux_size, - t_sram_orgz_info* cur_sram_orgz_info, - int num_mux_sram_bits, int* mux_sram_bits, - t_spice_model* mux_spice_model); - -void -add_mux_conf_bits_to_llist(int mux_size, - t_sram_orgz_info* cur_sram_orgz_info, - int num_mux_sram_bits, int* mux_sram_bits, - t_spice_model* mux_spice_model); - -void add_sram_membank_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, - int num_bls, int num_wls, - int* bl_conf_bits, int* wl_conf_bits); - -void -add_sram_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, int mem_index, - int num_sram_bits, int* sram_bits); - - -void decode_memory_bank_sram(t_spice_model* cur_sram_spice_model, int sram_bit, - int bl_len, int wl_len, int bl_offset, int wl_offset, - int* bl_conf_bits, int* wl_conf_bits); - -void -decode_and_add_sram_membank_conf_bit_to_llist(t_sram_orgz_info* cur_sram_orgz_info, - int mem_index, - int num_bl_per_sram, int num_wl_per_sram, - int cur_sram_bit); - -void determine_blwl_decoder_size(INP t_sram_orgz_info* cur_sram_orgz_info, - OUTP int* num_array_bl, OUTP int* num_array_wl, - OUTP int* bl_decoder_size, OUTP int* wl_decoder_size) ; - -void init_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, - int num_switch, - t_switch_inf* switches, - t_spice* spice, - t_det_routing_arch* routing_arch); - -void add_one_conf_bit_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info) ; - -void add_sram_conf_bits_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, - t_spice_model* cur_spice_model) ; - -void add_mux_conf_bits_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, - t_spice_model* mux_spice_model, int mux_size) ; - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c deleted file mode 100644 index 400be99bc..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c +++ /dev/null @@ -1,49 +0,0 @@ -/***********************************/ -/* FPGA-SPICE for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include "spice_types.h" -#include "linkedlist.h" -#include "fpga_x2p_globals.h" - -/* Global variables to be shared by different tools of FPGA-SPICE */ -/* SRAM SPICE MODEL should be set as global*/ -t_spice_model* fpga_spice_sram_model = NULL; -enum e_sram_orgz fpga_spice_sram_orgz_type = SPICE_SRAM_STANDALONE; -/* Input and Output Pad spice model. should be set as global */ -t_spice_model* fpga_spice_inpad_model = NULL; -t_spice_model* fpga_spice_outpad_model = NULL; -t_spice_model* fpga_spice_iopad_model = NULL; - -/* Prefix of global input, output and inout of a I/O pad */ -char* gio_inout_prefix = "gfpga_pad_"; - -/* Number of configuration bits of each switch block */ -int** num_conf_bits_sb = NULL; -/* Number of configuration bits of each Connection Box CHANX */ -int** num_conf_bits_cbx = NULL; -/* Number of configuration bits of each Connection Box CHANY */ -int** num_conf_bits_cby = NULL; - -/* Linked list for global ports */ -t_llist* global_ports_head = NULL; - -/* Linked list for verilog and spice syntax char */ -t_llist* reserved_syntax_char_head = NULL; - -/* Default value of a signal */ -int default_signal_init_value = 0; - -/* Default do parasitic net estimation !!!*/ -boolean run_parasitic_net_estimation = TRUE; -boolean run_testbench_load_extraction = TRUE; - -char* renaming_report_postfix = "_io_renaming.rpt"; -char* fpga_spice_bitstream_output_file_postfix = ".bitstream"; -char* fpga_spice_bitstream_logic_block_log_file_postfix = "_lb_bitstream.log"; -char* fpga_spice_bitstream_routing_log_file_postfix = "_routing_bitstream.log"; -char* default_sdc_folder = "SDC/"; - -DeviceRRChan device_rr_chan; -DeviceRRGSB device_rr_gsb; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h deleted file mode 100644 index 7c36b917e..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef FPGA_X2P_GLOBALS_H -#define FPGA_X2P_GLOBALS_H - -#include "rr_blocks.h" - -/* global parameters for FPGA-SPICE tool suites */ - -extern t_spice_model* fpga_spice_sram_model; -extern enum e_sram_orgz fpga_spice_sram_orgz_type; - -/* Input and Output Pad spice model. should be set as global */ -extern t_spice_model* fpga_spice_inpad_model; -extern t_spice_model* fpga_spice_outpad_model; -extern t_spice_model* fpga_spice_iopad_model; - -/* Number of configuration bits of each switch block */ -extern int** num_conf_bits_sb; -/* Number of configuration bits of each Connection Box CHANX */ -extern int** num_conf_bits_cbx; -/* Number of configuration bits of each Connection Box CHANY */ -extern int** num_conf_bits_cby; - -/* Prefix of global input, output and inout of a I/O pad */ -extern char* gio_input_prefix; -extern char* gio_output_prefix; -extern char* gio_inout_prefix; - -extern int default_signal_init_value; -extern boolean run_parasitic_net_estimation; -extern boolean run_testbench_load_extraction; - -/* Linked list for global ports */ -extern t_llist* global_ports_head; - -/* Linked list for verilog and spice syntax char */ -extern t_llist* reserved_syntax_char_head; - -extern char* renaming_report_postfix; -extern char* fpga_spice_bitstream_output_file_postfix; -extern char* fpga_spice_bitstream_logic_block_log_file_postfix; -extern char* fpga_spice_bitstream_routing_log_file_postfix; - -extern DeviceRRChan device_rr_chan; -extern DeviceRRGSB device_rr_gsb; - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_lut_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_lut_utils.c deleted file mode 100644 index 2e38bb305..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_lut_utils.c +++ /dev/null @@ -1,758 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include SPICE support headers*/ -#include "quicksort.h" -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_lut_utils.h" - - -char* complete_truth_table_line(int lut_size, - char* input_truth_table_line) { - char* ret = NULL; - int num_token = 0; - char** tokens = NULL; - int cover_len = 0; - int j; - - /* Due to the size of truth table may be less than the lut size. - * i.e. in LUT-6 architecture, there exists LUT1-6 in technology-mapped netlists - * So, in truth table line, there may be 10- 1 - * In this case, we should complete it by --10- 1 - */ - /*Malloc the completed truth table, lut_size + space + truth_val + '\0'*/ - ret = (char*)my_malloc(sizeof(char)*lut_size + 3); - /* Split one line of truth table line*/ - tokens = fpga_spice_strtok(input_truth_table_line, " ", &num_token); - /* Check, only 2 tokens*/ - /* Sometimes, the truth table is ' 0' or ' 1', which corresponds to a constant */ - if (1 == num_token) { - /* restore the token[0]*/ - tokens = (char**)realloc(tokens, 2 * sizeof(char*)); - tokens[1] = tokens[0]; - tokens[0] = my_strdup("-"); - num_token = 2; - } - - /* In Most cases, there should be 2 tokens. */ - assert(2 == num_token); - /* We may have two truth table from two LUTs which contain both 0 and 1*/ - /* - if ((0 != strcmp(tokens[1], "1"))&&(0 != strcmp(tokens[1], "0"))) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Last token of truth table line should be [0|1]!\n", - __FILE__, __LINE__); - exit(1); - } - */ - /* Complete the truth table line*/ - cover_len = strlen(tokens[0]); - assert((cover_len < lut_size)||(cover_len == lut_size)); - - /* Copy the original truth table line */ - for (j = 0; j < cover_len; j++) { - ret[j] = tokens[0][j]; - } - /* Add the number of '-' we should add in the back !!! */ - for (j = cover_len; j < lut_size; j++) { - ret[j] = '-'; - } - - /* Copy the original truth table line */ - sprintf(ret + lut_size, " %s", tokens[1]); - - /* Free */ - for (j = 0; j < num_token; j++) { - my_free(tokens[j]); - } - - return ret; -} - -/* For each lut_bit_lines, we should recover the truth table, - * and then set the sram bits to "1" if the truth table defines so. - * Start_point: the position we start decode recursively - */ -void configure_lut_sram_bits_per_line_rec(int** sram_bits, - int lut_size, - char* truth_table_line, - int start_point) { - int i; - int num_sram_bit = (int)pow(2., (double)(lut_size)); - char* temp_line = my_strdup(truth_table_line); - int do_config = 1; - int sram_id = 0; - - /* Check the length of sram bits and truth table line */ - //assert((sizeof(int)*num_sram_bit) == sizeof(*sram_bits)); /*TODO: fix this assert*/ - if ((unsigned)(lut_size + 1 + 1) != strlen(truth_table_line)){ /* lut_size + space + '1' */ - assert((unsigned)(lut_size + 1 + 1) == strlen(truth_table_line)); /* lut_size + space + '1' */ - } - /* End of truth_table_line should be "space" and "1" */ - assert((0 == strcmp(" 1", truth_table_line + lut_size))||(0 == strcmp(" 0", truth_table_line + lut_size))); - /* Make sure before start point there is no '-' */ - for (i = 0; i < start_point; i++) { - assert('-' != truth_table_line[i]); - } - - /* Configure sram bits recursively */ - for (i = start_point; i < lut_size; i++) { - if ('-' == truth_table_line[i]) { - do_config = 0; - /* if we find a dont_care, we don't do configure now but recursively*/ - /* '0' branch */ - temp_line[i] = '0'; - configure_lut_sram_bits_per_line_rec(sram_bits, lut_size, temp_line, start_point + 1); - /* '1' branch */ - temp_line[i] = '1'; - configure_lut_sram_bits_per_line_rec(sram_bits, lut_size, temp_line, start_point + 1); - break; - } - } - - /* do_config*/ - if (do_config) { - for (i = 0; i < lut_size; i++) { - /* Should be either '0' or '1' */ - switch (truth_table_line[i]) { - case '0': - /* We assume the 1-lut pass sram1 when input = 0 */ - sram_id += (int)pow(2., (double)(i)); - break; - case '1': - /* We assume the 1-lut pass sram0 when input = 1 */ - break; - case '-': - assert('-' != truth_table_line[i]); /* Make sure there is no dont_care */ - default : - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid truth_table bit(%c), should be [0|1|'-]!\n", - __FILE__, __LINE__, truth_table_line[i]); - exit(1); - } - } - /* Set the sram bit to '1'*/ - assert((-1 < sram_id) && (sram_id < num_sram_bit)); - if (0 == strcmp(" 1", truth_table_line + lut_size)) { - (*sram_bits)[sram_id] = 1; /* on set*/ - } else if (0 == strcmp(" 0", truth_table_line + lut_size)) { - (*sram_bits)[sram_id] = 0; /* off set */ - } else { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid truth_table_line ending(=%s)!\n", - __FILE__, __LINE__, truth_table_line + lut_size); - exit(1); - } - } - - /* Free */ - my_free(temp_line); - - return; -} - -/* Determine if the truth table of a LUT is a on-set or a off-set */ -int determine_lut_truth_table_on_set(int truth_table_len, - char** truth_table) { - int on_set = 0; - int off_set = 0; - int i, tt_line_len; - - for (i = 0; i < truth_table_len; i++) { - tt_line_len = strlen(truth_table[i]); - switch (truth_table[i][tt_line_len - 1]) { - case '1': - on_set = 1; - break; - case '0': - off_set = 1; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid truth_table_line ending(=%c)!\n", - __FILE__, __LINE__, truth_table[i][tt_line_len - 1]); - exit(1); - } - } - - /* Prefer on_set if both are true */ - if (2 == (on_set + off_set)) { - on_set = 1; off_set = 0; - } - - return on_set; -} - -/* Generate the LUT SRAM bits for a given truth table - * As truth tables may come from different logic blocks, truth tables could be in on and off sets - * We first build a base SRAM bits, where different parts are set to tbe on/off sets - * Then, we can decode SRAM bits as regular process - */ -int* generate_lut_sram_bits(int truth_table_len, - char** truth_table, - int lut_size, - int default_sram_bit_value) { - int num_sram = (int)pow(2.,(double)(lut_size)); - int* ret = (int*)my_calloc(num_sram, sizeof(int)); - char** completed_truth_table = (char**)my_malloc(sizeof(char*)*truth_table_len); - int on_set = 0; - int off_set = 0; - int i; - - /* if No truth_table, do default*/ - if (0 == truth_table_len) { - switch (default_sram_bit_value) { - case 0: - off_set = 0; - on_set = 1; - break; - case 1: - off_set = 1; - on_set = 0; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid default_signal_init_value(=%d)!\n", - __FILE__, __LINE__, default_sram_bit_value); - exit(1); - } - } else { - on_set = determine_lut_truth_table_on_set(truth_table_len, truth_table); - off_set = 1 - on_set; - } - - /* Read in truth table lines, decode one by one */ - for (i = 0; i < truth_table_len; i++) { - /* Complete the truth table line by line*/ - //printf("truth_table[%d] = %s\n", i, truth_table[i]); - completed_truth_table[i] = complete_truth_table_line(lut_size, truth_table[i]); - //printf("Completed_truth_table[%d] = %s\n", i, completed_truth_table[i]); - } - - if (1 == on_set) { - /* Initial all sram bits to 0*/ - for (i = 0 ; i < num_sram; i++) { - ret[i] = 0; - } - } else if (1 == off_set) { - /* Initial all sram bits to 1*/ - for (i = 0 ; i < num_sram; i++) { - ret[i] = 1; - } - } - - for (i = 0; i < truth_table_len; i++) { - /* Update the truth table, sram_bits */ - configure_lut_sram_bits_per_line_rec(&ret, lut_size, completed_truth_table[i], 0); - } - - /* Free */ - for (i = 0; i < truth_table_len; i++) { - my_free(completed_truth_table[i]); - } - - return ret; -} - -/* Generate the base SRAM bits: - * Check type of truth table of each mapped logical block - * if it is on-set, we give a all 0 base sram-bit - * if it is off-set, we give a all 1 base sram-bit */ -int* generate_frac_lut_sram_bits(t_phy_pb* lut_phy_pb, - int* truth_table_length, - char*** truth_table, - int default_sram_bit_value) { - int num_sram, lut_size; - int* sram_bits = NULL; - int* temp_sram_bits = NULL; - int ilb; - int lut_frac_level, lut_output_mask; - int num_input_port = 0; - t_spice_model_port** input_ports = NULL; - int offset, len_to_cpy; - - /* Find the input ports for LUT size */ - input_ports = find_spice_model_ports(lut_phy_pb->pb_graph_node->pb_type->spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - assert(1 == num_input_port); - lut_size = input_ports[0]->size; - num_sram = (int)pow(2.,(double)(lut_size)); - sram_bits = (int*)my_calloc(num_sram, sizeof(int)); - - /* Initialization */ - for (ilb = 0; ilb < num_sram; ilb++) { - sram_bits[ilb] = default_sram_bit_value; - } - - for (ilb = 0; ilb < lut_phy_pb->num_logical_blocks; ilb++) { - /* find the corresponding SPICE model output port and assoicated lut_output_mask */ - lut_frac_level = get_pb_graph_pin_lut_frac_level(lut_phy_pb->lut_output_pb_graph_pin[ilb]); - lut_output_mask = get_pb_graph_pin_lut_output_mask(lut_phy_pb->lut_output_pb_graph_pin[ilb]); - /* Decode lut sram bits */ - temp_sram_bits = generate_lut_sram_bits(truth_table_length[ilb], truth_table[ilb], lut_size, default_sram_bit_value); - /* Depending on the frac-level, we get the location(starting/end points) of sram bits */ - len_to_cpy = (int)pow(2., (double)(lut_frac_level)); - offset = len_to_cpy * lut_output_mask; - /*TODO: copy to the sram_bits to return: - * Should check if we will overwrite anything! - */ - memcpy(sram_bits + offset, temp_sram_bits + offset, - len_to_cpy * sizeof(int)); - /* Free */ - my_free(temp_sram_bits); - } - - /* Free */ - my_free(input_ports); - - return sram_bits; -} - - -/* Provide the truth table of a mapped logical block - * 1. Reorgainze the truth table to be consistent with the mapped nets of a LUT - * 2. Allocate the truth table in a clean char array and return - */ -char** assign_lut_truth_table(t_logical_block* mapped_logical_block, - int* truth_table_length) { - char** truth_table = NULL; - t_linked_vptr* head = NULL; - int cur = 0; - - if (NULL == mapped_logical_block) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid mapped_logical_block!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Count the lines of truth table*/ - head = mapped_logical_block->truth_table; - while(head) { - (*truth_table_length)++; - head = head->next; - } - /* Allocate truth_tables */ - truth_table = (char**)my_malloc(sizeof(char*)*(*truth_table_length)); - /* Fill truth_tables*/ - cur = 0; - head = mapped_logical_block->truth_table; - while(head) { - truth_table[cur] = my_strdup((char*)(head->data_vptr)); - head = head->next; - cur++; - } - assert(cur == (*truth_table_length)); - - return truth_table; -} - -/* Return the truth table of a wired LUT */ -char** get_wired_lut_truth_table() { - char** tt = (char**) my_malloc(sizeof(char*)); - tt[0] = my_strdup("1 1"); - - return tt; -} - -/* Adapt the truth from the actual connection from the input nets of a LUT, - */ -char** assign_post_routing_wired_lut_truth_table(int lut_output_vpack_net_num, - int lut_size, int* lut_pin_vpack_net_num, - int* truth_table_length) { - int inet; - char** tt = (char**) my_malloc(sizeof(char*)); - - /* truth_table_length will be always 1*/ - (*truth_table_length) = 1; - - /* Malloc */ - tt[0] = (char*)my_malloc((lut_size + 3) * sizeof(char)); - /* Fill the truth table !!! */ - for (inet = 0; inet < lut_size; inet++) { - /* Find the vpack_num in the lut_input_pin, we fix it to be 1 */ - if (lut_output_vpack_net_num == lut_pin_vpack_net_num[inet]) { - tt[0][inet] = '1'; - } else { - /* Otherwise it should be don't care */ - tt[0][inet] = '-'; - } - } - memcpy(tt[0] + lut_size, " 1", 3); - - return tt; -} - -/* Provide the truth table of a mapped logical block - * 1. Reorgainze the truth table to be consistent with the mapped nets of a LUT - * 2. Allocate the truth table in a clean char array and return - */ -char** assign_post_routing_lut_truth_table(t_logical_block* mapped_logical_block, - int lut_size, int* lut_pin_vpack_net_num, - int* truth_table_length) { - char** truth_table = NULL; - t_linked_vptr* head = NULL; - int cur = 0; - int inet, jnet; - int* lut_to_lb_net_mapping = NULL; - int num_lb_pin = 0; - int* lb_pin_vpack_net_num = NULL; - int lb_truth_table_size = 0; - - if (NULL == mapped_logical_block) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid mapped_logical_block!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Allocate */ - lut_to_lb_net_mapping = (int*) my_malloc (sizeof(int) * lut_size); - /* Find nets mapped to a logical block */ - get_lut_logical_block_input_pin_vpack_net_num(mapped_logical_block, - &num_lb_pin, &lb_pin_vpack_net_num); - /* Create a pin-to-pin net_num mapping */ - for (inet = 0; inet < lut_size; inet++) { - lut_to_lb_net_mapping[inet] = OPEN; - /* Bypass open nets */ - if (OPEN == lut_pin_vpack_net_num[inet]) { - continue; - } - assert (OPEN != lut_pin_vpack_net_num[inet]); - /* Find the position (offset) of each vpack_net_num in lb_pins */ - for (jnet = 0; jnet < num_lb_pin; jnet++) { - if (lut_pin_vpack_net_num[inet] == lb_pin_vpack_net_num[jnet]) { - lut_to_lb_net_mapping[inet] = jnet; - break; - } - } - /* Not neccesary to find a one, some luts just share part of their pins */ - } - - /* Initialization */ - (*truth_table_length) = 0; - /* Count the lines of truth table*/ - head = mapped_logical_block->truth_table; - while(head) { - (*truth_table_length)++; - head = head->next; - } - /* Allocate truth_tables */ - truth_table = (char**)my_malloc(sizeof(char*)*(*truth_table_length)); - /* Fill truth_tables*/ - cur = 0; - head = mapped_logical_block->truth_table; - while(head) { - /* Handle the truth table pin remapping */ - truth_table[cur] = (char*) my_malloc((lut_size + 3) * sizeof(char)); - /* Initialize */ - lb_truth_table_size = strlen((char*)(head->data_vptr)); - strcpy(truth_table[cur] + lut_size, (char*)(head->data_vptr) + lb_truth_table_size - 2); - truth_table[cur][lut_size + 2] = '\0'; - /* Add */ - for (inet = 0; inet < lut_size; inet++) { - /* Open net implies a don't care, or some nets are not in the list */ - if ((OPEN == lut_pin_vpack_net_num[inet]) - || (OPEN == lut_to_lb_net_mapping[inet])) { - truth_table[cur][inet] = '-'; - continue; - } - /* Find the desired truth table bit */ - truth_table[cur][inet] = ((char*)(head->data_vptr))[lut_to_lb_net_mapping[inet]]; - } - - head = head->next; - cur++; - } - assert(cur == (*truth_table_length)); - - return truth_table; -} - -/* Find the output port of LUT that this logical block is mapped to */ -t_pb_graph_pin* get_mapped_lut_phy_pb_output_pin(t_phy_pb* lut_phy_pb, - t_logical_block* lut_logical_block) { - int iport, ipin; - int num_lut_output_ports; - int* num_lut_output_pins; - int** lut_output_vpack_net_num; - int pin_rr_node_index; - t_pb_graph_pin* ret_pin = NULL; /* The pin to return */ - int found_num_pins = 0; - - /* Find the vpack_net_num of the output of the lut_logical_block */ - get_logical_block_output_vpack_net_num(lut_logical_block, - &num_lut_output_ports, - &num_lut_output_pins, - &lut_output_vpack_net_num); - - /* Check */ - assert ( 1 == num_lut_output_ports); - assert ( 1 == num_lut_output_pins[0]); - assert ( OPEN != lut_output_vpack_net_num[0][0]); - - /* Search the output pins of lut_phy_pb in rr_graph in find */ - for (iport = 0; iport < lut_phy_pb->pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < lut_phy_pb->pb_graph_node->num_output_pins[iport]; ipin++) { - /* Get the rr_node index of the pin */ - pin_rr_node_index = lut_phy_pb->pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; - /* Get the vpack_net_num in the local rr_graph, see if we have a match */ - if (lut_output_vpack_net_num[0][0] != lut_phy_pb->rr_graph->rr_node[pin_rr_node_index].vpack_net_num) { - continue; - } - /* Reach here, it means we have a match! */ - ret_pin = &(lut_phy_pb->pb_graph_node->output_pins[iport][ipin]); - found_num_pins++; - } - } - - /* We should have only one match! */ - assert (1 == found_num_pins); - - /* Free */ - my_free(num_lut_output_pins); - for (iport = 0; iport < num_lut_output_ports; iport++) { - my_free(lut_output_vpack_net_num); - } - - return ret_pin; -} - -/* Get LUT fracturable level of a pb_graph_pin */ -int get_pb_graph_pin_lut_frac_level(t_pb_graph_pin* out_pb_graph_pin) { - /* search the corresponding spice_model_port */ - return out_pb_graph_pin->port->spice_model_port->lut_frac_level; -} - -/* Get LUT output mask of a pb_graph_pin */ -int get_pb_graph_pin_lut_output_mask(t_pb_graph_pin* out_pb_graph_pin) { - int pin_number = out_pb_graph_pin->pin_number; - /* search the corresponding spice_model_port */ - return out_pb_graph_pin->port->spice_model_port->lut_output_mask[pin_number]; -} - -/* Adapt truth table for a fracturable LUT - * Determine fixed input bits for this truth table: - * 1. input bits within frac_level (all '-' if not specified) - * 2. input bits outside frac_level, decoded to its output mask (0 -> first part -> all '1') - */ -void adapt_truth_table_for_frac_lut(t_pb_graph_pin* lut_out_pb_graph_pin, - int truth_table_length, - char** truth_table) { - int lut_frac_level; - int lut_output_mask; - int i, lut_size, num_mask_bits; - int temp; - char* mask_bits = NULL; - - /* Find the output port of LUT that this logical block is mapped to */ - assert(NULL != lut_out_pb_graph_pin); - /* find the corresponding SPICE model output port and assoicated lut_output_mask */ - lut_frac_level = get_pb_graph_pin_lut_frac_level(lut_out_pb_graph_pin); - - /* No adaption required for when the lut_frac_level is not set */ - if (OPEN == lut_frac_level) { - return; - } - - /* find the corresponding SPICE model output port and assoicated lut_output_mask */ - lut_output_mask = get_pb_graph_pin_lut_output_mask(lut_out_pb_graph_pin); - - /* Apply modification to the truth table */ - for (i = 0; i < truth_table_length; i++) { - /* Last two chars are fixed */ - lut_size = strlen(truth_table[i]) - 2; - /* Get the number of bits to be masked (modified) */ - num_mask_bits = lut_size - lut_frac_level; - /* Check if we need to modify any bits */ - assert (-1 < num_mask_bits); - if ( 0 == num_mask_bits ) { - continue; - } - /* Modify bits starting from lut_frac_level */ - /* decode the lut_output_mask to LUT input codes */ - temp = pow(2., num_mask_bits) - 1 - lut_output_mask; - mask_bits = my_itobin(temp, num_mask_bits); - /* copy the bits to the truth table line */ - memcpy(truth_table[i] + lut_frac_level, mask_bits, num_mask_bits); - /* free */ - my_free(mask_bits); - } - - return; -} - -int determine_lut_path_id(int lut_size, - int* lut_inputs) { - int path_id = 0; - int i; - - for (i = 0; i < lut_size; i++) { - switch (lut_inputs[i]) { - case 0: - path_id += (int)pow(2., (double)(i)); - break; - case 1: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid sram_bits[%d]!\n", - __FILE__, __LINE__, i); - exit(1); - } - } - - return path_id; -} - -/* Identify if this is an unallocated pb that is used as a wired LUT */ -boolean is_pb_wired_lut(t_pb_graph_node* cur_pb_graph_node, - t_pb_type* cur_pb_type, - t_rr_node* pb_rr_graph) { - boolean is_used = FALSE; - - is_used = is_pb_used_for_wiring(cur_pb_graph_node, - cur_pb_type, - pb_rr_graph); - /* Return TRUE if this block is not used and it is a LUT ! */ - if ((TRUE == is_used) - && (LUT_CLASS == cur_pb_type->class_type)) { - return TRUE; - } - - return FALSE; -} - -/* Find and return the net_name that this LUT is wiring*/ -int get_wired_lut_net_name(t_pb_graph_node* lut_pb_graph_node, - t_pb_type* lut_pb_type, - t_rr_node* pb_rr_graph) { - int iport, ipin; - int num_used_lut_input_pins = 0; - int num_used_lut_output_pins = 0; - int temp_rr_node_index; - int wired_lut_net_num = OPEN; - - /* Return if this is not a LUT */ - if ((LUT_CLASS != lut_pb_type->class_type) - || (LUT_CLASS != lut_pb_graph_node->pb_type->class_type)) { - return OPEN; - } - - num_used_lut_input_pins = 0; - /* Find the used input pin of this LUT and rr_node in the graph */ - for (iport = 0; iport < lut_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < lut_pb_graph_node->num_input_pins[iport]; ipin++) { - temp_rr_node_index = lut_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; - if (OPEN != pb_rr_graph[temp_rr_node_index].net_num) { - num_used_lut_input_pins++; - wired_lut_net_num = pb_rr_graph[temp_rr_node_index].net_num; - } - } - } - /* Make sure we only have 1 used input pin */ - assert (1 == num_used_lut_input_pins); - - /* Find the used output*/ - num_used_lut_output_pins = 0; - /* Find the used output pin of this LUT and rr_node in the graph */ - for (iport = 0; iport < lut_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < lut_pb_graph_node->num_output_pins[iport]; ipin++) { - temp_rr_node_index = lut_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; - if (wired_lut_net_num == pb_rr_graph[temp_rr_node_index].net_num) { - num_used_lut_output_pins++; - } - } - } - /* Make sure we only have 1 used output pin */ - assert (1 == num_used_lut_output_pins); - - assert (OPEN != wired_lut_net_num); - - return wired_lut_net_num; -} - -/* This function aims to allocate and load pbs for wired LUTs - * 1. if the pbs are not allocated at all, allocate and load the full array - * Otherwise just allocate the specific pb - * 2. Get the net_name that this LUT is wiring - * and load it to the pb - */ -void allocate_wired_lut_pbs(t_pb*** wired_lut_pbs, - int num_pb_type_children, - int num_pbs, - int wired_lut_child_id, - int wired_lut_pb_id) { - int ipb; - - /* 1. if the pbs are not allocated at all, allocate and load the full array */ - if (NULL == (*wired_lut_pbs)) { - (*wired_lut_pbs) = (t_pb**) my_calloc(num_pb_type_children, sizeof(t_pb*)); - for (ipb = 0 ; ipb < num_pb_type_children; ipb++) { - (*wired_lut_pbs)[ipb] = (t_pb*) my_calloc(num_pbs, sizeof(t_pb)); - } - } else if (NULL == (*wired_lut_pbs)[wired_lut_child_id]) { - /* 2. if the pb row is not allocated, just allocate that row */ - (*wired_lut_pbs)[wired_lut_child_id] = (t_pb*) my_calloc(num_pbs, sizeof(t_pb)); - } else if (NULL == (*wired_lut_pbs)[wired_lut_child_id][wired_lut_pb_id].name) { - /* 3. if this pb is allocated, we do nothing */ - } - - /* Find the net_name this LUT is wiring */ - - return; -} - -/* 1. Find the net_name that this wire LUT is mapped to - * 2. Give a name to the pb - * 3. Update the mapping information (net_num) in the rr_graph of pb - * 4. Create the wired LUTs in logical block array - * 5. Create new vpack & clb nets to rewire the logical blocks - * 6. Update the vpack_to_clb_net_mapping and clb_to_vpack_net_mapping !!! - */ -void load_wired_lut_pbs(t_pb* lut_pb, - t_pb_graph_node* lut_pb_graph_node, - t_pb_type* lut_pb_type, - t_rr_node* pb_rr_graph, - int* L_num_logical_blocks, t_net** L_logical_block, - int* L_num_vpack_nets, t_net** L_vpack_net) { - int lut_wire_net_name = OPEN; - - /* 1. Find the net_name that this wire LUT is mapped to */ - lut_wire_net_name = get_wired_lut_net_name(lut_pb_graph_node, - lut_pb_type, - pb_rr_graph); - assert (OPEN != lut_wire_net_name); - - /* Fill basic information */ - lut_pb->pb_graph_node = lut_pb_graph_node; - lut_pb->rr_graph = pb_rr_graph; - - /* Check and give a new name to this pb */ - - /* Update rr_graph, - * 1. find the downstream logical blocks and their pbs - * 2. Update their rr_nodes with new net_name - * 3. backtrace all the rr_nodes and update net_name - */ - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_lut_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_lut_utils.h deleted file mode 100644 index 3571d3df3..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_lut_utils.h +++ /dev/null @@ -1,59 +0,0 @@ -/* Useful functions for LUT decoding */ -char* complete_truth_table_line(int lut_size, - char* input_truth_table_line); - -void configure_lut_sram_bits_per_line_rec(int** sram_bits, - int lut_size, - char* truth_table_line, - int start_point); - -int* generate_lut_sram_bits(int truth_table_len, - char** truth_table, - int lut_size, - int default_sram_bit_value); - -int* generate_frac_lut_sram_bits(t_phy_pb* lut_phy_pb, - int* truth_table_length, - char*** truth_table, - int default_sram_bit_value); - -char** assign_lut_truth_table(t_logical_block* mapped_logical_block, - int* truth_table_length); - -char** get_wired_lut_truth_table(); - -char** assign_post_routing_wired_lut_truth_table(int lut_output_vpack_net_num, - int lut_size, int* lut_pin_vpack_net_num, - int* truth_table_length); - -char** assign_post_routing_lut_truth_table(t_logical_block* mapped_logical_block, - int num_lut_pins, int* lut_pin_vpack_net_num, - int* truth_table_length); - -t_pb_graph_pin* get_mapped_lut_phy_pb_output_pin(t_phy_pb* lut_phy_pb, - t_logical_block* lut_logical_block); - -int get_pb_graph_pin_lut_frac_level(t_pb_graph_pin* out_pb_graph_pin); - -int get_pb_graph_pin_lut_output_mask(t_pb_graph_pin* out_pb_graph_pin); - -void adapt_truth_table_for_frac_lut(t_pb_graph_pin* lut_out_pb_graph_pin, - int truth_table_length, - char** truth_table); - -int determine_lut_path_id(int lut_size, - int* lut_inputs); - -boolean is_pb_wired_lut(t_pb_graph_node* cur_pb_graph_node, - t_pb_type* cur_pb_type, - t_rr_node* pb_rr_graph); - -int get_wired_lut_net_name(t_pb_graph_node* lut_pb_graph_node, - t_pb_type* lut_pb_type, - t_rr_node* pb_rr_graph); - -void allocate_wired_lut_pbs(t_pb*** wired_lut_pbs, - int num_pb_type_children, - int num_pbs, - int wired_lut_child_id, - int wired_lut_pb_id); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp deleted file mode 100644 index 01e26632a..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.cpp +++ /dev/null @@ -1,398 +0,0 @@ -/********************************************************************* - * This file includes functions that are used for - * generating ports for memory modules - *********************************************************************/ -#include "vtr_assert.h" -#include "util.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_mem_utils.h" - -/********************************************************************* - * Create a port-to-port map for a CMOS memory module - * - * Configuration Chain - * ------------------- - * - * config_bus (head) config_bus (tail) - * | ^ - * v | - * +-------------------------------------+ - * | CMOS-based Memory Module | - * +-------------------------------------+ - * | | - * v v - * sram_out sram_outb - * - * - * Memory bank - * ----------- - * - * config_bus (BL) config_bus (WL) - * | | - * v v - * +-------------------------------------+ - * | CMOS-based Memory Module | - * +-------------------------------------+ - * | | - * v v - * sram_out sram_outb - * - **********************************************************************/ -static -std::map generate_cmos_mem_module_port2port_map(const BasicPort& config_bus, - const std::vector& mem_output_bus_ports, - const e_sram_orgz& sram_orgz_type) { - std::map port2port_name_map; - - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* Nothing to do */ - break; - case SPICE_SRAM_SCAN_CHAIN: { - /* Link the head port of the memory module: - * the LSB of config bus port is the head port index - */ - std::vector config_bus_ports; - config_bus_ports.push_back(BasicPort(generate_local_config_bus_port_name(), config_bus.get_msb(), config_bus.get_msb() + 1)); - BasicPort head_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_lsb(), config_bus_ports[0].get_lsb()); - port2port_name_map[generate_configuration_chain_head_name()] = head_port; - - /* Link the tail port of the memory module: - * the MSB of config bus port is the tail port index - */ - BasicPort tail_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_msb(), config_bus_ports[0].get_msb()); - port2port_name_map[generate_configuration_chain_tail_name()] = tail_port; - - /* Link the SRAM output ports of the memory module */ - VTR_ASSERT( 2 == mem_output_bus_ports.size() ); - port2port_name_map[generate_configuration_chain_data_out_name()] = mem_output_bus_ports[0]; - port2port_name_map[generate_configuration_chain_inverted_data_out_name()] = mem_output_bus_ports[1]; - break; - } - case SPICE_SRAM_MEMORY_BANK: - /* TODO: */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - - return port2port_name_map; -} - -/********************************************************************* - * Create a port-to-port map for a ReRAM-based memory module - * Memory bank - * ----------- - * - * config_bus (BL) config_bus (WL) - * | | - * v v - * +-------------------------------------+ - * | ReRAM-based Memory Module | - * +-------------------------------------+ - * | | - * v v - * Mem_out Mem_outb - **********************************************************************/ -static -std::map generate_rram_mem_module_port2port_map(const BasicPort& config_bus, - const std::vector& mem_output_bus_ports, - const e_sram_orgz& sram_orgz_type) { - std::map port2port_name_map; - - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* Not supported */ - break; - case SPICE_SRAM_SCAN_CHAIN: { - /* Link the head port of the memory module: - * the LSB of config bus port is the head port index - */ - std::vector config_bus_ports; - config_bus_ports.push_back(BasicPort(generate_local_config_bus_port_name(), config_bus.get_msb(), config_bus.get_msb() + 1)); - BasicPort head_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_lsb(), config_bus_ports[0].get_lsb()); - port2port_name_map[generate_configuration_chain_head_name()] = head_port; - - /* Link the tail port of the memory module: - * the MSB of config bus port is the tail port index - */ - BasicPort tail_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_msb(), config_bus_ports[0].get_msb()); - port2port_name_map[generate_configuration_chain_tail_name()] = tail_port; - - /* Link the SRAM output ports of the memory module */ - VTR_ASSERT( 2 == mem_output_bus_ports.size() ); - port2port_name_map[generate_configuration_chain_data_out_name()] = mem_output_bus_ports[0]; - port2port_name_map[generate_configuration_chain_inverted_data_out_name()] = mem_output_bus_ports[1]; - break; - } - case SPICE_SRAM_MEMORY_BANK: - /* TODO: link BL/WL/Reserved Ports to the inputs of a memory module */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - - return port2port_name_map; -} - -/********************************************************************* - * Create a port-to-port map for a memory module - * The content of the port-to-port map will depend not only - * the design technology of the memory cells but also the - * configuration styles of FPGA fabric. - * Here we will branch on the design technology - **********************************************************************/ -std::map generate_mem_module_port2port_map(const BasicPort& config_bus, - const std::vector& mem_output_bus_ports, - const e_spice_model_design_tech& mem_design_tech, - const e_sram_orgz& sram_orgz_type) { - std::map port2port_name_map; - - switch (mem_design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - port2port_name_map = generate_cmos_mem_module_port2port_map(config_bus, mem_output_bus_ports, sram_orgz_type); - break; - case SPICE_MODEL_DESIGN_RRAM: - port2port_name_map = generate_rram_mem_module_port2port_map(config_bus, mem_output_bus_ports, sram_orgz_type); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of memory design technology !\n", - __FILE__, __LINE__); - exit(1); - } - - return port2port_name_map; -} - -/********************************************************************* - * Update the LSB and MSB of a configuration bus based on the number of - * memory bits of a CMOS memory module. - **********************************************************************/ -static -void update_cmos_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, - const size_t& num_config_bits, - BasicPort& config_bus) { - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* Not supported */ - break; - case SPICE_SRAM_SCAN_CHAIN: - /* Scan-chain of a memory module only has a head and a tail. - * LSB and MSB of configuration bus will be shifted to the next head. - */ - VTR_ASSERT(true == config_bus.rotate(1)); - break; - case SPICE_SRAM_MEMORY_BANK: - /* In this case, a memory module has a number of BL/WL and BLB/WLB (possibly). - * LSB and MSB of configuration bus will be shifted by the number of BL/WL/BLB/WLB. - */ - VTR_ASSERT(true == config_bus.rotate(num_config_bits)); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/********************************************************************* - * Update the LSB and MSB of a configuration bus based on the number of - * memory bits of a ReRAM memory module. - **********************************************************************/ -static -void update_rram_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, - BasicPort& config_bus) { - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* Not supported */ - break; - case SPICE_SRAM_SCAN_CHAIN: - /* Scan-chain of a memory module only has a head and a tail. - * LSB and MSB of configuration bus will be shifted to the next head. - * TODO: this may be changed later!!! - */ - VTR_ASSERT(true == config_bus.rotate(1)); - break; - case SPICE_SRAM_MEMORY_BANK: - /* In this case, a memory module contains unique BL/WL or BLB/WLB, - * which are not shared with other modules - * TODO: this may be changed later!!! - */ - VTR_ASSERT(true == config_bus.rotate(1)); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/********************************************************************* - * Update the LSB and MSB of a configuration bus based on the number of - * memory bits of a module. - * Note that this function is designed to do such simple job, in purpose of - * being independent from adding ports or printing ports. - * As such, this function can be re-used in bitstream generation - * when Verilog generation is not needed. - * DO NOT update the configuration bus in the function of adding/printing ports - **********************************************************************/ -void update_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, - const e_spice_model_design_tech& mem_design_tech, - const size_t& num_config_bits, - BasicPort& config_bus) { - switch (mem_design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - update_cmos_mem_module_config_bus(sram_orgz_type, num_config_bits, config_bus); - break; - case SPICE_MODEL_DESIGN_RRAM: - update_rram_mem_module_config_bus(sram_orgz_type, config_bus); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of memory design technology !\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * Check if the MSB of a configuration bus of a switch block - * matches the expected value - ********************************************************************/ -bool check_mem_config_bus(const e_sram_orgz& sram_orgz_type, - const BasicPort& config_bus, - const size_t& local_expected_msb) { - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* Not supported */ - return false; - break; - case SPICE_SRAM_SCAN_CHAIN: - /* TODO: comment on why - */ - return (local_expected_msb == config_bus.get_msb()); - break; - case SPICE_SRAM_MEMORY_BANK: - /* TODO: comment on why - */ - return (local_expected_msb == config_bus.get_msb()); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - /* Reach here, it means something goes wrong, return a false value */ - return false; -} - -/******************************************************************** - * Generate a list of ports that are used for SRAM configuration to a module - * The type and names of added ports strongly depend on the - * organization of SRAMs. - * 1. Standalone SRAMs: - * two ports will be added, which are regular output and inverted output - * 2. Scan-chain Flip-flops: - * two ports will be added, which are the head of scan-chain - * and the tail of scan-chain - * IMPORTANT: the port size will be forced to 1 in this case - * because the head and tail are both 1-bit ports!!! - * 3. Memory decoders: - * 2-4 ports will be added, depending on the ports available in the SRAM - * Among these, two ports are mandatory: BL and WL - * The other two ports are optional: BLB and WLB - * Note that the constraints are correletated to the checking rules - * in check_circuit_library() - ********************************************************************/ -std::vector generate_sram_port_names(const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz sram_orgz_type) { - std::vector sram_port_names; - /* Prepare a list of port types to be added, the port type will be used to create port names */ - std::vector model_port_types; - - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - model_port_types.push_back(SPICE_MODEL_PORT_INPUT); - model_port_types.push_back(SPICE_MODEL_PORT_OUTPUT); - break; - case SPICE_SRAM_SCAN_CHAIN: - model_port_types.push_back(SPICE_MODEL_PORT_INPUT); - model_port_types.push_back(SPICE_MODEL_PORT_OUTPUT); - break; - case SPICE_SRAM_MEMORY_BANK: { - std::vector ports_to_search; - ports_to_search.push_back(SPICE_MODEL_PORT_BL); - ports_to_search.push_back(SPICE_MODEL_PORT_WL); - ports_to_search.push_back(SPICE_MODEL_PORT_BLB); - ports_to_search.push_back(SPICE_MODEL_PORT_WLB); - /* Try to find a BL/WL/BLB/WLB port and update the port types/module port types to be added */ - for (const auto& port_to_search : ports_to_search) { - std::vector found_port = circuit_lib.model_ports_by_type(sram_model, port_to_search); - if (0 == found_port.size()) { - continue; - } - model_port_types.push_back(port_to_search); - } - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization !\n", - __FILE__, __LINE__); - exit(1); - } - - /* Add ports to the module manager */ - for (size_t iport = 0; iport < model_port_types.size(); ++iport) { - /* Create a port */ - std::string port_name = generate_sram_port_name(sram_orgz_type, model_port_types[iport]); - sram_port_names.push_back(port_name); - } - - return sram_port_names; -} - -/******************************************************************** - * Generate a list of ports that are used for SRAM configuration to a module - * 1. Standalone SRAMs: - * use the suggested port_size - * 2. Scan-chain Flip-flops: - * IMPORTANT: the port size will be forced to 1 in this case - * 3. Memory decoders: - * use the suggested port_size - ********************************************************************/ -size_t generate_sram_port_size(const e_sram_orgz sram_orgz_type, - const size_t& num_config_bits) { - size_t sram_port_size = num_config_bits; - - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - break; - case SPICE_SRAM_SCAN_CHAIN: - /* CCFF head/tail are single-bit ports */ - sram_port_size = 1; - break; - case SPICE_SRAM_MEMORY_BANK: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization !\n", - __FILE__, __LINE__); - exit(1); - } - - return sram_port_size; -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h deleted file mode 100644 index 852b14b99..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mem_utils.h +++ /dev/null @@ -1,34 +0,0 @@ -/******************************************************************** - * Header file for fpga_x2p_mem_utils.cpp - **********************************************************************/ -#ifndef FPGA_X2P_MEM_UTILS_H -#define FPGA_X2P_MEM_UTILS_H - -/* Header files are included for the data types appear in the function declaration below */ -#include -#include "device_port.h" -#include "spice_types.h" -#include "module_manager.h" - -std::map generate_mem_module_port2port_map(const BasicPort& config_bus, - const std::vector& mem_output_bus_ports, - const e_spice_model_design_tech& mem_design_tech, - const e_sram_orgz& sram_orgz_type); - -void update_mem_module_config_bus(const e_sram_orgz& sram_orgz_type, - const e_spice_model_design_tech& mem_design_tech, - const size_t& num_config_bits, - BasicPort& config_bus); - -bool check_mem_config_bus(const e_sram_orgz& sram_orgz_type, - const BasicPort& config_bus, - const size_t& local_expected_msb); - -std::vector generate_sram_port_names(const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz sram_orgz_type); - -size_t generate_sram_port_size(const e_sram_orgz sram_orgz_type, - const size_t& num_config_bits); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c deleted file mode 100644 index 40c60d776..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c +++ /dev/null @@ -1,1186 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include SPICE support headers*/ -#include "quicksort.h" -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_bitstream_utils.h" - -#include "fpga_x2p_mux_utils.h" - -/* Determine the number of SRAM bit for a basis subckt of a multiplexer - * In general, the number of SRAM bits should be same as the number of inputs per level - * with one exception: - * When multiplexing structure is tree-like, there should be only 1 SRAM bit - */ -int determine_num_sram_bits_mux_basis_subckt(t_spice_model* mux_spice_model, - int mux_size, - int num_input_per_level, - boolean special_basis) { - int num_sram_bits; - - /* General cases */ - switch (mux_spice_model->design_tech_info.mux_info->structure) { - case SPICE_MODEL_STRUCTURE_TREE: - num_sram_bits = 1; - break; - case SPICE_MODEL_STRUCTURE_ONELEVEL: - num_sram_bits = num_input_per_level; - if (2 == num_input_per_level) { - num_sram_bits = 1; - } - break; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - num_sram_bits = num_input_per_level; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", - __FILE__, __LINE__, mux_spice_model->name); - exit(1); - } - - /* For special cases: overide the results */ - if (TRUE == special_basis) { - num_sram_bits = num_input_per_level; - } - - return num_sram_bits; -} - -/* Determine the level of multiplexer - */ -int determine_tree_mux_level(int mux_size) { - int level = 0; - - /* Do log2(mux_size), have a basic number*/ - level = (int)(log((double)mux_size)/log(2.)); - /* Fix the error, i.e. mux_size=5, level = 2, we have to complete */ - while (mux_size > pow(2.,(double)level)) { - level++; - } - - return level; -} - -int determine_num_input_basis_multilevel_mux(int mux_size, - int mux_level) { - int num_input_per_unit = 2; - - /* Special Case: mux_size = 2 */ - if (2 == mux_size) { - return mux_size; - } - - if (1 == mux_level) { - return mux_size; - } - - if (2 == mux_level) { - num_input_per_unit = (int)sqrt(mux_size); - while (num_input_per_unit*num_input_per_unit < mux_size) { - num_input_per_unit++; - } - return num_input_per_unit; - } - - assert(2 < mux_level); - - - while(pow((double)num_input_per_unit, (double)mux_level) < mux_size) { - num_input_per_unit++; - } - - if (num_input_per_unit < 2) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Number of inputs of each basis should be at least 2!\n", - __FILE__, __LINE__); - exit(1); - } - - return num_input_per_unit; -} - -/*Determine the number inputs required at the last level*/ -int tree_mux_last_level_input_num(int num_level, - int mux_size) { - int ret = 0; - - ret = (int)(pow(2., (double)num_level)) - mux_size; - - if (0 < ret) { - ret = (int)(2.*(mux_size - pow(2., (double)(num_level-1)))); - } else if (0 > ret) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])num_level(%d) is wrong with mux_size(%d)!\n", - __FILE__, __LINE__, num_level, mux_size); - exit(1); - } else { - ret = mux_size; - } - - return ret; -} - -int multilevel_mux_last_level_input_num(int num_level, int num_input_per_unit, - int mux_size) { - int ret = 0; - int num_basis_last_level = (int)(mux_size/num_input_per_unit); - int num_potential_special_inputs = 0; - int num_special_basis = 0; - int num_input_special_basis = 0; - - ret = mux_size - num_basis_last_level * num_input_per_unit; - assert((0 == ret)||(0 < ret)); - - /* Special Case: mux_size = 2 */ - if (2 == mux_size) { - return mux_size; - } - - if (0 < ret) { - /* Check if we need a special basis at last level, - * differ : the number of input of the last-2 level will be used - */ - num_potential_special_inputs = (num_basis_last_level + ret) - pow((double)(num_input_per_unit), (double)(num_level-1)); - /* should be smaller than the num_input_per_unit */ - assert((!(0 > num_potential_special_inputs))&&(num_potential_special_inputs < num_input_per_unit)); - /* We need a speical basis */ - num_special_basis = pow((double)(num_input_per_unit), (double)(num_level - 1)) - num_basis_last_level; - if (ret == num_special_basis) { - num_input_special_basis = 0; - } else if (1 == num_special_basis) { - num_input_special_basis = ret; - } else { - assert ( 1 < num_special_basis ); - num_input_special_basis = ret - 1; - } - ret = num_input_special_basis + num_basis_last_level * num_input_per_unit; - } else { - ret = mux_size; - } - - return ret; -} - -/*************************************************************************************** - * Find the number of inputs for a encoder with a given output size - * Inputs - * | | | | | - * +-----------+ - * / \ - * / Encoder \ - * +-----------------+ - * | | | | | | | | - * Outputs - * - * The outputs are assumes to be one-hot codes (at most only one '1' exist) - * Considering this fact, there are only num_of_outputs + 1 conditions to be encoded. - * Therefore, the number of inputs is ceil(log(num_of_outputs+1)/log(2)) - * We plus 1, which is all-zero condition for outputs - ****************************************************************************************/ -int determine_mux_local_encoder_num_inputs(int num_outputs) { - return ceil(log(num_outputs) / log(2)); -} - -/* Decoding a one-level MUX: - * SPICE/Verilog model declare the sram port sequence as follows: - * sel0, sel1, ... , selN, - * which control the pass-gate logic connected to - * in0, in1, ... , inN - * When decode the SRAM bits, we initialize every bits to zero - * And then set the sel signal corresponding to the input to be 1. - * TODO: previously the decoding is not correct, need to check any bug in SPICE part - */ -int* decode_onelevel_mux_sram_bits(int fan_in, - int mux_level, - int path_id, - boolean use_local_encoder) { - /* Check */ - assert( (!(0 > path_id)) && (path_id < fan_in) ); - - /* If we use local encoder, we have a different number of sram bits! */ - int num_sram_bits = fan_in; - if (TRUE == use_local_encoder) { - num_sram_bits = determine_mux_local_encoder_num_inputs(fan_in); - } - /* Allocate sram_bits array to return */ - int* ret = (int*)my_calloc(num_sram_bits, sizeof(int)); - - if (TRUE == use_local_encoder) { - /* The encoder will convert the path_id to a binary number - * For example: when path_id=3 (use the 4th input), using a 4-input encoder - * the sram_bits will be the 4-digit binary number of 3: 0100 - */ - ret = my_itobin_int(path_id, num_sram_bits); - } else { - ret[path_id] = 1; - } - /* ret[fan_in - 1 - path_id] = 1; */ - return ret; -} - -int* decode_multilevel_mux_sram_bits(int fan_in, - int mux_level, - int path_id, - boolean use_local_encoder) { - int* ret = NULL; - int i, j, path_differ, temp; - int num_last_level_input, active_mux_level, active_path_id, num_input_basis; - - /* Check */ - assert((0 == path_id)||(0 < path_id)); - assert(path_id < fan_in); - - /* determine the number of input of basis */ - switch (mux_level) { - case 1: - /* Special: 1-level should be have special care !!! */ - return decode_onelevel_mux_sram_bits(fan_in, mux_level, path_id, use_local_encoder); - default: - assert(1 < mux_level); - num_input_basis = determine_num_input_basis_multilevel_mux(fan_in, mux_level); - break; - } - - ret = (int*)my_malloc(sizeof(int)*(num_input_basis * mux_level)); - - /* Determine last level input */ - num_last_level_input = multilevel_mux_last_level_input_num(mux_level, num_input_basis, fan_in); - - /* Initialize */ - for (i = 0; i < (num_input_basis*mux_level); i++) { - ret[i] = 0; - } - - /* When last level input number is less than the 2**mux_level, - * There are some input at the level: (mux_level-1) - */ - active_mux_level = mux_level; - active_path_id = path_id; - if (num_last_level_input < fan_in) { - if (path_id > num_last_level_input - 1) { - active_mux_level = mux_level - 1; - active_path_id = (int)pow((double)num_input_basis,(double)(active_mux_level)) - (fan_in - path_id); - } - } else { - assert(num_last_level_input == fan_in); - } - - temp = active_path_id; - for (i = mux_level - 1; i > (mux_level - active_mux_level - 1); i--) { - for (j = 0; j < num_input_basis; j++) { - path_differ = (j + 1) * (int)pow((double)num_input_basis,(double)(i+active_mux_level-mux_level)); - if (temp < path_differ) { - /* This is orignal one for SPICE, but not work for VerilogGen - * I comment it here - ret[i*num_input_basis + j] = 1; - */ - ret[(mux_level - 1 - i)*num_input_basis + j] = 1; - /* Reduce the min. start index of this basis */ - temp -= j * (int)pow((double)num_input_basis,(double)(i+active_mux_level-mux_level)); - break; /* Touch the boundry, stop and move onto the next level */ - } - } - } - - /* Check */ - assert(0 == temp); - - /* If we do not use a local encoder, these are the sram bits we want */ - if (FALSE == use_local_encoder) { - return ret; - } - - /* If we use local encoder, we have a different number of sram bits! */ - int num_bits_per_level = determine_mux_local_encoder_num_inputs(num_input_basis); - int num_sram_bits = mux_level * num_bits_per_level; - /* Allocate sram_bits array to return */ - int* encoded_ret = (int*)my_calloc(num_sram_bits, sizeof(int)); - - /* Walk through each level and find the path_id and encode it */ - for (int ilvl = 0; ilvl < mux_level; ++ilvl) { - int start_idx = num_input_basis * ilvl; - int end_idx = num_input_basis * (ilvl + 1); - int encoded_path_id = -1; - int checker = 0; - for (int idx = start_idx; idx < end_idx; ++idx) { - if (1 == ret[idx]) { - checker++; - encoded_path_id = idx - start_idx; - } - } - /* There should be at most one '1' */ - assert( (0 == checker) || (1 == checker)); - /* If all-zero bits are found, it means that the stage is not used, assign to the last input by default */ - if (0 == checker) { - encoded_path_id = num_input_basis - 1; - } - assert (-1 != encoded_path_id); - /* The encoder will convert the path_id to a binary number - * For example: when path_id=3 (use the 4th input), using a 4-input encoder - * the sram_bits will be the 4-digit binary number of 3: 0100 - */ - int* tmp_bits = my_itobin_int(encoded_path_id, num_bits_per_level); - /* Copy tmp_bits to encoded bits */ - for (int idx = 0; idx < num_bits_per_level; ++idx) { - encoded_ret[idx + ilvl* num_bits_per_level] = tmp_bits[idx]; - } - /* Free */ - my_free(tmp_bits); - } - - /* Free ret */ - my_free(ret); - - return encoded_ret; -} - -/* Decode the configuration to sram_bits - * A path_id is in the range of [0..fan_in-1] - * sram - * input0 -----| - * |----- output - * input1 -----| - * Here, we assume (fix) the mux2to1 pass input0 when sram = 1 (vdd), and pass input1 when sram = 0(gnd) - * To generate the sram bits, we can determine the in each level of MUX, - * the path id is on the upper path(sram = 1) or the lower path (sram = 0), by path_id > 2**mux_level - */ -int* decode_tree_mux_sram_bits(int fan_in, - int mux_level, - int path_id) { - int* ret = (int*)my_malloc(sizeof(int)*mux_level); - int i = 0; - int path_differ = 0; - int temp = 0; - int num_last_level_input = 0; - int active_mux_level = 0; - int active_path_id = 0; - - /* Check */ - assert((0 == path_id)||(0 < path_id)); - assert(path_id < fan_in); - - /* Determine last level input */ - num_last_level_input = tree_mux_last_level_input_num(mux_level, fan_in); - - /* Initialize */ - for (i = 0; i < mux_level; i++) { - ret[i] = 0; - } - - /* When last level input number is less than the 2**mux_level, - * There are some input at the level: (mux_level-1) - */ - active_mux_level = mux_level; - active_path_id = path_id; - if (num_last_level_input < fan_in) { - if (path_id > num_last_level_input) { - active_mux_level = mux_level - 1; - active_path_id = (int)pow(2.,(double)(active_mux_level)) - (fan_in - path_id); - } - } else { - assert(num_last_level_input == fan_in); - } - - temp = active_path_id; - for (i = mux_level - 1; i > (mux_level - active_mux_level - 1); i--) { - path_differ = (int)pow(2.,(double)(i + active_mux_level - mux_level)); - if (temp < path_differ) { - ret[i] = 1; - } else { - temp = temp - path_differ; - ret[i] = 0; - } - } - - /* Check */ - assert(0 == temp); - - return ret; -} - -int get_mux_default_path_id(t_spice_model* mux_spice_model, - int mux_size, int path_id) { - int default_path_id; - - assert(SPICE_MODEL_MUX == mux_spice_model->type); - - if (TRUE == mux_spice_model->design_tech_info.mux_info->add_const_input) { - default_path_id = mux_size; /* When there is a constant input, use the last path */ - } else { - default_path_id = DEFAULT_MUX_PATH_ID; /* When there is no constant input, use the default one */ - } - - return default_path_id; -} - -int get_mux_full_input_size(t_spice_model* mux_spice_model, - int mux_size) { - int full_input_size = mux_size; - - assert ((SPICE_MODEL_MUX == mux_spice_model->type) - || (SPICE_MODEL_LUT == mux_spice_model->type)); - - if (SPICE_MODEL_LUT == mux_spice_model->type) { - return full_input_size; - } - - if (TRUE == mux_spice_model->design_tech_info.mux_info->add_const_input) { - full_input_size = mux_size + 1; - } - - return full_input_size; -} - -void decode_cmos_mux_sram_bits(t_spice_model* mux_spice_model, - int mux_size, int path_id, - int* bit_len, int** conf_bits, int* mux_level) { - int num_mux_input = 0; - int datapath_id = path_id; - - /* Check */ - assert(NULL != mux_level); - assert(NULL != bit_len); - assert(NULL != conf_bits); - assert(SPICE_MODEL_MUX == mux_spice_model->type); - assert(SPICE_MODEL_DESIGN_CMOS == mux_spice_model->design_tech); - - /* Handle DEFAULT PATH ID */ - if (DEFAULT_PATH_ID == path_id) { - datapath_id = get_mux_default_path_id(mux_spice_model, mux_size, path_id); - } else { - assert((DEFAULT_PATH_ID < datapath_id)&&(datapath_id < mux_size)); - } - - /* We have an additional input (last input) connected to a constant */ - num_mux_input = get_mux_full_input_size(mux_spice_model, mux_size); - - /* Initialization */ - (*bit_len) = 0; - (*conf_bits) = NULL; - - /* Special for MUX-2: whatever structure it is, it has always one-level and one configuration bit */ - if (2 == num_mux_input) { - (*bit_len) = 1; - (*mux_level) = 1; - (*conf_bits) = decode_tree_mux_sram_bits(num_mux_input, (*mux_level), datapath_id); - return; - } - /* Other general cases */ - switch (mux_spice_model->design_tech_info.mux_info->structure) { - case SPICE_MODEL_STRUCTURE_TREE: - (*mux_level) = determine_tree_mux_level(num_mux_input); - (*bit_len) = (*mux_level); - (*conf_bits) = decode_tree_mux_sram_bits(num_mux_input, (*mux_level), datapath_id); - break; - case SPICE_MODEL_STRUCTURE_ONELEVEL: - (*mux_level) = 1; - (*bit_len) = num_mux_input; - /* Mux has local encoders are different in the number of bits */ - if (TRUE == mux_spice_model->design_tech_info.mux_info->local_encoder) { - (*bit_len) = determine_mux_local_encoder_num_inputs(*bit_len); - } - (*conf_bits) = decode_onelevel_mux_sram_bits(num_mux_input, (*mux_level), datapath_id, - mux_spice_model->design_tech_info.mux_info->local_encoder); - break; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - (*mux_level) = mux_spice_model->design_tech_info.mux_info->mux_num_level; - /* Mux has local encoders are different in the number of bits */ - if (TRUE == mux_spice_model->design_tech_info.mux_info->local_encoder) { - int num_bits_per_level = determine_mux_local_encoder_num_inputs(determine_num_input_basis_multilevel_mux(num_mux_input, (*mux_level))); - (*bit_len) = (*mux_level) * num_bits_per_level; - } else { - (*bit_len) = (*mux_level) * determine_num_input_basis_multilevel_mux(num_mux_input, (*mux_level)); - } - (*conf_bits) = decode_multilevel_mux_sram_bits(num_mux_input, (*mux_level), datapath_id, - mux_spice_model->design_tech_info.mux_info->local_encoder); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for mux_spice_model (%s)!\n", - __FILE__, __LINE__, mux_spice_model->name); - exit(1); - } - return; -} - -/** Decode 1-level 4T1R MUX - */ -void decode_one_level_4t1r_mux(int path_id, - int bit_len, int* conf_bits) { - int i; - - /* Check */ - assert(0 < bit_len); - assert(NULL != conf_bits); - assert((-1 < path_id)&&((path_id < bit_len/2 - 1)||(path_id == bit_len/2 - 1))); - - /* All the others should be zero */ - for (i = 0; i < bit_len; i++) { - conf_bits[i] = 0; - } - - /* Last bit of WL should be 1 */ - conf_bits[bit_len-1] = 1; - /* determine which BL should be 1*/ - conf_bits[path_id] = 1; - - return; -} - -/** Decode multi-level 4T1R MUX - */ -void decode_multilevel_4t1r_mux(int num_level, int num_input_basis, - int mux_size, int path_id, - int bit_len, int* conf_bits) { - int i, active_basis_path_id; - - /* Check */ - assert(0 < bit_len); - assert(NULL != conf_bits); - /* assert((-1 < path_id)&&(path_id < bit_len/2 - 1)); */ - /* Start from first level to the last level */ - active_basis_path_id = path_id; - for (i = 0; i < num_level; i++) { - /* Treat each basis as a 1-level 4T1R MUX */ - active_basis_path_id = active_basis_path_id % num_input_basis; - /* Last bit of WL should be 1 */ - conf_bits[bit_len/2 + (num_input_basis+1)*(i+1) - 1] = 1; - /* determine which BL should be 1*/ - conf_bits[(num_input_basis+1)*i + active_basis_path_id] = 1; - } - - return; -} - -/** Decode the configuration bits for a 4T1R-based MUX - * Determine the number of configuration bits - * Configuration bits are decoded depending on the MUX structure: - * 1. 1-level; 2. multi-level (tree-like); - */ -void decode_rram_mux(t_spice_model* mux_spice_model, - int mux_size, int path_id, - int* bit_len, int** conf_bits, int* mux_level) { - int num_level, num_input_basis, num_mux_input; - int datapath_id = path_id; - - /* Check */ - assert(NULL != mux_level); - assert(NULL != bit_len); - assert(NULL != conf_bits); - assert(SPICE_MODEL_MUX == mux_spice_model->type); - assert(SPICE_MODEL_DESIGN_RRAM == mux_spice_model->design_tech); - - /* Handle DEFAULT PATH ID */ - if (DEFAULT_PATH_ID == datapath_id) { - datapath_id = get_mux_default_path_id(mux_spice_model, mux_size, path_id); - } else { - assert((DEFAULT_PATH_ID < datapath_id)&&(datapath_id < mux_size)); - } - - /* We have an additional input (last input) connected to a constant */ - num_mux_input = get_mux_full_input_size(mux_spice_model, mux_size); - - /* Initialization */ - (*mux_level) = 0; - (*bit_len) = 0; - (*conf_bits) = NULL; - - (*bit_len) = 2 * count_num_sram_bits_one_spice_model(mux_spice_model, num_mux_input); - - /* Switch cases: MUX structure */ - switch (mux_spice_model->design_tech_info.mux_info->structure) { - case SPICE_MODEL_STRUCTURE_ONELEVEL: - /* Number of configuration bits is 2*(input_size+1) */ - num_level = 1; - break; - case SPICE_MODEL_STRUCTURE_TREE: - /* Number of configuration bits is num_level* 2*(basis+1) */ - num_level = determine_tree_mux_level(num_mux_input); - num_input_basis = 2; - break; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - /* Number of configuration bits is num_level* 2*(basis+1) */ - num_level = mux_spice_model->design_tech_info.mux_info->mux_num_level; - num_input_basis = determine_num_input_basis_multilevel_mux(num_mux_input, num_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid MUX structure!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Malloc configuration bits */ - (*conf_bits) = (int*)my_calloc((*bit_len), sizeof(int)); - - /* Decode configuration bits : BL & WL*/ - /* Switch cases: MUX structure */ - switch (mux_spice_model->design_tech_info.mux_info->structure) { - case SPICE_MODEL_STRUCTURE_ONELEVEL: - decode_one_level_4t1r_mux(datapath_id, (*bit_len), (*conf_bits)); - break; - case SPICE_MODEL_STRUCTURE_TREE: - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - decode_multilevel_4t1r_mux(num_level, num_input_basis, num_mux_input, - datapath_id, (*bit_len), (*conf_bits)); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid MUX structure!\n", - __FILE__, __LINE__); - exit(1); - } - - (*mux_level) = num_level; - - return; -} - -/* Useful functions for MUX architecture */ -void init_spice_mux_arch(t_spice_model* spice_model, - t_spice_mux_arch* spice_mux_arch, - int mux_size) { - int cur; - int i; - /* Make sure we have a valid pointer*/ - if (NULL == spice_mux_arch) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d])Invalid spice_mux_arch!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Basic info*/ - spice_mux_arch->structure = spice_model->design_tech_info.mux_info->structure; - spice_mux_arch->num_data_input = mux_size; - /* We create an additional input for MUX, which is connected to a constant VDD|GND */ - spice_mux_arch->num_input = get_mux_full_input_size(spice_model, mux_size); - - /* For different structure */ - switch (spice_model->design_tech_info.mux_info->structure) { - case SPICE_MODEL_STRUCTURE_TREE: - spice_mux_arch->num_level = determine_tree_mux_level(spice_mux_arch->num_input); - spice_mux_arch->num_input_basis = 2; - /* Determine the level and index of per MUX inputs*/ - spice_mux_arch->num_input_last_level = tree_mux_last_level_input_num(spice_mux_arch->num_level, - spice_mux_arch->num_input); - break; - case SPICE_MODEL_STRUCTURE_ONELEVEL: - spice_mux_arch->num_level = 1; - spice_mux_arch->num_input_basis = spice_mux_arch->num_input; - /* Determine the level and index of per MUX inputs*/ - spice_mux_arch->num_input_last_level = spice_mux_arch->num_input; - break; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - /* Handle speical case: input size is 2 */ - if (2 == spice_mux_arch->num_input) { - spice_mux_arch->num_level = 1; - } else { - spice_mux_arch->num_level = spice_model->design_tech_info.mux_info->mux_num_level; - } - spice_mux_arch->num_input_basis = determine_num_input_basis_multilevel_mux(spice_mux_arch->num_input, - spice_mux_arch->num_level); - /* Determine the level and index of per MUX inputs*/ - spice_mux_arch->num_input_last_level = multilevel_mux_last_level_input_num(spice_mux_arch->num_level, - spice_mux_arch->num_input_basis, - spice_mux_arch->num_input); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", - __FILE__, __LINE__, spice_model->name); - exit(1); - } - - /* Alloc*/ - spice_mux_arch->num_input_per_level = (int*) my_malloc(sizeof(int)*spice_mux_arch->num_level); - spice_mux_arch->input_level = (int*)my_malloc(sizeof(int)*spice_mux_arch->num_input); - spice_mux_arch->input_offset = (int*)my_malloc(sizeof(int)*spice_mux_arch->num_input); - - /* Assign inputs info for the last level first */ - for (i = 0; i < spice_mux_arch->num_input_last_level; i++) { - spice_mux_arch->input_level[i] = spice_mux_arch->num_level; - spice_mux_arch->input_offset[i] = i; - } - /* For the last second level*/ - if (spice_mux_arch->num_input > spice_mux_arch->num_input_last_level) { - cur = ceil((double)spice_mux_arch->num_input_last_level / (double)spice_mux_arch->num_input_basis); - /* Start from the input ports that are not occupied by the last level - * last level has (cur) outputs - */ - /* - printf("size:%d, cur:%d, num_input_last_level=%d, num_input_basis=%d\n", - spice_mux_arch->num_input, cur, - spice_mux_arch->num_input_last_level, spice_mux_arch->num_input_basis); - */ - for (i = spice_mux_arch->num_input_last_level; i < spice_mux_arch->num_input; i++) { - spice_mux_arch->input_level[i] = spice_mux_arch->num_level - 1; - spice_mux_arch->input_offset[i] = cur; - cur++; - } - assert((cur < (int)pow((double)spice_mux_arch->num_input_basis, (double)(spice_mux_arch->num_level-1))) - ||(cur == (int)pow((double)spice_mux_arch->num_input_basis, (double)(spice_mux_arch->num_level-1)))); - } - /* Fill the num_input_per_level*/ - for (i = 0; i < spice_mux_arch->num_level; i++) { - cur = i + 1; - spice_mux_arch->num_input_per_level[i] = (int)pow((double)spice_mux_arch->num_input_basis, (double)cur); - if ((cur == spice_mux_arch->num_level) - &&(spice_mux_arch->num_input_last_level < spice_mux_arch->num_input_per_level[i])) { - spice_mux_arch->num_input_per_level[i] = spice_mux_arch->num_input_last_level; - } - } - - return; -} - -/* Determine if we need a speical basis. - * If we need one, we give the MUX size of this special basis - */ -int find_spice_mux_arch_special_basis_size(t_spice_mux_arch spice_mux_arch) { - int im; - int mux_size = spice_mux_arch.num_input; - int num_input_basis = spice_mux_arch.num_input_basis; - int num_input_special_basis = 0; - int special_basis_start = 0; - - /* For different structure */ - switch (spice_mux_arch.structure) { - case SPICE_MODEL_STRUCTURE_TREE: - break; - case SPICE_MODEL_STRUCTURE_ONELEVEL: - break; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - special_basis_start = mux_size - mux_size % num_input_basis; - for (im = special_basis_start; im < mux_size; im++) { - if (spice_mux_arch.num_level == spice_mux_arch.input_level[im]) { - num_input_special_basis++; - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice_mux_arch!\n", - __FILE__, __LINE__); - exit(1); - } - - return num_input_special_basis; -} - -/* Search the linked list, if we have the same mux size and spice_model - * return 1, if not we return 0 - */ -t_llist* search_mux_linked_list(t_llist* mux_head, - int mux_size, - t_spice_model* spice_model) { - t_llist* temp = mux_head; - t_spice_mux_model* cur_mux = NULL; - /* traversal the linked list*/ - while(temp) { - cur_mux = (t_spice_mux_model*)(temp->dptr); - if ((cur_mux->size == mux_size) - &&(spice_model == cur_mux->spice_model)) { - return temp; - } - /* next */ - temp = temp->next; - } - - return NULL; -} - - -/* Check the linked list if we have a mux stored with same spice model - * if not, we create a new one. - */ -void check_and_add_mux_to_linked_list(t_llist** muxes_head, - int mux_size, - t_spice_model* spice_model) { - t_spice_mux_model* cur_mux = NULL; - t_llist* temp = NULL; - - /* Check code: to avoid mistake, we should check the mux size - * the mux_size should be at least 2 so that we need a mux - */ - if (mux_size < 2) { - printf("Warning:(File:%s,LINE[%d]) ilegal mux size (%d), expect to be at least 2!\n", - __FILE__, __LINE__, mux_size); - return; - } - - /* Search the linked list */ - if (NULL != search_mux_linked_list((*muxes_head),mux_size,spice_model)) { - /* We find one, there is no need to create a new one*/ - return; - } - /*Create a linked list, if head is NULL*/ - if (NULL == (*muxes_head)) { - (*muxes_head) = create_llist(1); - (*muxes_head)->dptr = my_malloc(sizeof(t_spice_mux_model)); - cur_mux = (t_spice_mux_model*)((*muxes_head)->dptr); - } else { - /* We have to create a new elment in linked list*/ - temp = insert_llist_node((*muxes_head)); - temp->dptr = my_malloc(sizeof(t_spice_mux_model)); - cur_mux = (t_spice_mux_model*)(temp->dptr); - } - /* Fill the new SPICE MUX Model*/ - cur_mux->size = mux_size; - cur_mux->spice_model = spice_model; - cur_mux->cnt = 1; /* Initialize the counter*/ - - return; -} - -/* Free muxes linked list - */ -void free_muxes_llist(t_llist* muxes_head) { - t_llist* temp = muxes_head; - while(temp) { - /* Free the mux_spice_model, remember to set the pointer to NULL */ - free(temp->dptr); - temp->dptr = NULL; - /* Move on to the next pointer*/ - temp = temp->next; - } - free_llist(muxes_head); - return; -} - -/* For LUTs without SPICE netlist defined, we can create a SPICE netlist - * In this case, we need a MUX - */ -void stats_lut_spice_mux(t_llist** muxes_head, - t_spice_model* spice_model) { - int lut_mux_size = 0; - int num_input_port = 0; - t_spice_model_port** input_ports = NULL; - - if (NULL == spice_model) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid Spice_model pointer!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert(SPICE_MODEL_LUT == spice_model->type); - - /* Get input ports */ - input_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - assert(1 == num_input_port); - lut_mux_size = (int)pow(2.,(double)(input_ports[0]->size)); - - /* MUX size = 2^lut_size */ - check_and_add_mux_to_linked_list(muxes_head, lut_mux_size, spice_model); - - return; -} - - - -/* Stats the multiplexer sizes and structure in the global routing architecture*/ -void stats_spice_muxes_routing_arch(t_llist** muxes_head, - int num_switch, - t_switch_inf* switches, - t_spice* spice, - t_det_routing_arch* routing_arch) { - int inode; - t_rr_node* node; - t_spice_model* sb_switch_spice_model = NULL; - t_spice_model* cb_switch_spice_model = NULL; - - /* Current Version: Support Uni-directional routing architecture only*/ - if (UNI_DIRECTIONAL != routing_arch->directionality) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Spice Modeling Only support uni-directional routing architecture.\n",__FILE__, __LINE__); - exit(1); - } - - /* The routing path is. - * OPIN ----> CHAN ----> ... ----> CHAN ----> IPIN - * Each edge is a switch, for IPIN, the switch is a connection block, - * for the rest is a switch box - */ - /* Count the sizes of muliplexers in routing architecture */ - /* Visit the global variable : num_rr_nodes, rr_node */ - for (inode = 0; inode < num_rr_nodes; inode++) { - node = &rr_node[inode]; - switch (node->type) { - case IPIN: - /* Have to consider the fan_in only, it is a connection box(multiplexer)*/ - assert((node->fan_in > 0)||(0 == node->fan_in)); - if ((0 == node->fan_in)||(1 == node->fan_in)) { - break; - } - /* Find the spice_model for multiplexers in connection blocks */ - cb_switch_spice_model = switches[node->driver_switch].spice_model; - /* we should select a spice model for the connection box*/ - assert(NULL != cb_switch_spice_model); - check_and_add_mux_to_linked_list(muxes_head, node->fan_in,cb_switch_spice_model); - break; - case CHANX: - case CHANY: - /* Channels are the same, have to consider the fan_in as well, - * it could be a switch box if previous rr_node is a channel - * or it could be a connection box if previous rr_node is a IPIN or OPIN - */ - assert((node->fan_in > 0)||(0 == node->fan_in)); - if ((0 == node->fan_in)||(1 == node->fan_in)) { - break; - } - /* Find the spice_model for multiplexers in switch blocks*/ - sb_switch_spice_model = switches[node->driver_switch].spice_model; - /* we should select a spice model for the Switch box*/ - assert(NULL != sb_switch_spice_model); - check_and_add_mux_to_linked_list(muxes_head, node->fan_in,sb_switch_spice_model); - break; - case OPIN: - /* Actually, in single driver routing architecture, the OPIN, source of a routing path, - * is directly connected to Switch Box multiplexers - */ - break; - default: - break; - } - } - - return; -} - -/* Recursively do statistics for the - * multiplexer spice models inside pb_types - */ -void stats_mux_spice_model_pb_type_rec(t_llist** muxes_head, - t_pb_type* cur_pb_type) { - - int imode, ichild, jinterc; - t_spice_model* interc_spice_model = NULL; - - if (NULL == cur_pb_type) { - vpr_printf(TIO_MESSAGE_WARNING,"(File:%s,LINE[%d])cur_pb_type is null pointor!\n",__FILE__,__LINE__); - return; - } - - /* If there is spice_model_name, this is a leaf node!*/ - if ((NULL != cur_pb_type->spice_model_name) - || (NULL != cur_pb_type->physical_pb_type_name)) { - /* What annoys me is VPR create a sub pb_type for each lut which suppose to be a leaf node - * This may bring software convience but ruins SPICE modeling - */ - assert(NULL != cur_pb_type->phy_pb_type->spice_model); - return; - } - /* Traversal the hierarchy*/ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* Then we have to statisitic the interconnections*/ - for (jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { - /* Check the num_mux and fan_in*/ - assert((0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) - ||(0 < cur_pb_type->modes[imode].interconnect[jinterc].num_mux)); - if (0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) { - continue; - } - interc_spice_model = cur_pb_type->modes[imode].interconnect[jinterc].spice_model; - assert(NULL != interc_spice_model); - check_and_add_mux_to_linked_list(muxes_head, - cur_pb_type->modes[imode].interconnect[jinterc].fan_in, - interc_spice_model); - } - for (ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ichild++) { - stats_mux_spice_model_pb_type_rec(muxes_head, - &cur_pb_type->modes[imode].pb_type_children[ichild]); - } - } - return; -} - -/* Statistics the MUX SPICE MODEL with the help of pb_graph - * Not the most efficient function to finish the job - * Abandon it. But remains a good framework that could be re-used in connecting - * spice components together - */ -void stats_mux_spice_model_pb_node_rec(t_llist** muxes_head, - t_pb_graph_node* cur_pb_node) { - int imode, ipb, ichild, iport, ipin; - t_pb_type* cur_pb_type = cur_pb_node->pb_type; - t_spice_model* interc_spice_model = NULL; - enum e_interconnect pin_interc_type; - - if (NULL == cur_pb_node) { - vpr_printf(TIO_MESSAGE_WARNING,"(File:%s,LINE[%d])cur_pb_node is null pointor!\n",__FILE__,__LINE__); - return; - } - - if (NULL == cur_pb_type) { - vpr_printf(TIO_MESSAGE_WARNING,"(File:%s,LINE[%d])cur_pb_type is null pointor!\n",__FILE__,__LINE__); - return; - } - - /* If there is 0 mode, this is a leaf node!*/ - if (NULL != cur_pb_type->blif_model) { - assert(0 == cur_pb_type->num_modes); - assert(NULL == cur_pb_type->modes); - /* Ensure there is blif_model, and spice_model*/ - assert(NULL != cur_pb_type->model); - assert(NULL != cur_pb_type->spice_model_name); - assert(NULL != cur_pb_type->spice_model); - return; - } - /* Traversal the hierarchy*/ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* Then we have to statisitic the interconnections*/ - /* See the input ports*/ - for (iport = 0; iport < cur_pb_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_node->num_input_pins[iport]; ipin++) { - /* Ensure this is an input port */ - assert(IN_PORT == cur_pb_node->input_pins[iport][ipin].port->type); - /* See the edges, if the interconnetion type infer a MUX, we go next step*/ - pin_interc_type = find_pb_graph_pin_in_edges_interc_type(cur_pb_node->input_pins[iport][ipin]); - if ((COMPLETE_INTERC != pin_interc_type)&&(MUX_INTERC != pin_interc_type)) { - continue; - } - /* We shoule check the size of inputs, in some case of complete, the input_edge is one...*/ - if ((COMPLETE_INTERC == pin_interc_type)&&(1 == cur_pb_node->input_pins[iport][ipin].num_input_edges)) { - continue; - } - /* Note: i do care the input_edges only! They may infer multiplexers*/ - interc_spice_model = find_pb_graph_pin_in_edges_interc_spice_model(cur_pb_node->input_pins[iport][ipin]); - check_and_add_mux_to_linked_list(muxes_head, - cur_pb_node->input_pins[iport][ipin].num_input_edges, - interc_spice_model); - } - } - /* See the output ports*/ - for (iport = 0; iport < cur_pb_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_node->num_output_pins[iport]; ipin++) { - /* Ensure this is an input port */ - assert(OUT_PORT == cur_pb_node->output_pins[iport][ipin].port->type); - /* See the edges, if the interconnetion type infer a MUX, we go next step*/ - pin_interc_type = find_pb_graph_pin_in_edges_interc_type(cur_pb_node->output_pins[iport][ipin]); - if ((COMPLETE_INTERC != pin_interc_type)&&(MUX_INTERC != pin_interc_type)) { - continue; - } - /* We shoule check the size of inputs, in some case of complete, the input_edge is one...*/ - if ((COMPLETE_INTERC == pin_interc_type)&&(1 == cur_pb_node->output_pins[iport][ipin].num_input_edges)) { - continue; - } - /* Note: i do care the input_edges only! They may infer multiplexers*/ - interc_spice_model = find_pb_graph_pin_in_edges_interc_spice_model(cur_pb_node->output_pins[iport][ipin]); - check_and_add_mux_to_linked_list(muxes_head, - cur_pb_node->output_pins[iport][ipin].num_input_edges, - interc_spice_model); - } - } - /* See the clock ports*/ - for (iport = 0; iport < cur_pb_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_node->num_clock_pins[iport]; ipin++) { - /* Ensure this is an input port */ - assert(IN_PORT == cur_pb_node->clock_pins[iport][ipin].port->type); - /* See the edges, if the interconnetion type infer a MUX, we go next step*/ - pin_interc_type = find_pb_graph_pin_in_edges_interc_type(cur_pb_node->clock_pins[iport][ipin]); - if ((COMPLETE_INTERC != pin_interc_type)&&(MUX_INTERC != pin_interc_type)) { - continue; - } - /* We shoule check the size of inputs, in some case of complete, the input_edge is one...*/ - if ((COMPLETE_INTERC == pin_interc_type)&&(1 == cur_pb_node->clock_pins[iport][ipin].num_input_edges)) { - continue; - } - /* Note: i do care the input_edges only! They may infer multiplexers*/ - interc_spice_model = find_pb_graph_pin_in_edges_interc_spice_model(cur_pb_node->clock_pins[iport][ipin]); - check_and_add_mux_to_linked_list(muxes_head, - cur_pb_node->clock_pins[iport][ipin].num_input_edges, - interc_spice_model); - } - } - for (ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ichild++) { - /* num_pb is the number of such pb_type in a mode*/ - for (ipb = 0; ipb < cur_pb_type->modes[imode].pb_type_children[ichild].num_pb; ipb++) { - /* child_pb_grpah_nodes: [0..num_modes-1][0..num_pb_type_in_mode-1][0..num_pb_type-1]*/ - stats_mux_spice_model_pb_node_rec(muxes_head, - &cur_pb_node->child_pb_graph_nodes[imode][ichild][ipb]); - } - } - } - return; -} - - -/* Statistic for all the multiplexers in FPGA - * We determine the sizes and its structure (according to spice_model) for each type of multiplexers - * We search multiplexers in Switch Blocks, Connection blocks and Configurable Logic Blocks - * In additional to multiplexers, this function also consider crossbars. - * All the statistics are stored in a linked list, as a return value - */ -t_llist* stats_spice_muxes(int num_switches, - t_switch_inf* switches, - t_spice* spice, - t_det_routing_arch* routing_arch) { - int itype; - int imodel; - /* Linked-list to store the information of Multiplexers*/ - t_llist* muxes_head = NULL; - - /* Step 1: We should check the multiplexer spice models defined in routing architecture.*/ - stats_spice_muxes_routing_arch(&muxes_head, num_switches, switches, spice, routing_arch); - - /* Statistics after search routing resources */ - /* - temp = muxes_head; - while(temp) { - t_spice_mux_model* spice_mux_model = (t_spice_mux_model*)temp->dptr; - vpr_printf(TIO_MESSAGE_INFO,"Routing multiplexers: size=%d\n",spice_mux_model->size); - temp = temp->next; - } - */ - - /* Step 2: Count the sizes of multiplexers in complex logic blocks */ - for (itype = 0; itype < num_types; itype++) { - if (NULL != type_descriptors[itype].pb_type) { - stats_mux_spice_model_pb_type_rec(&muxes_head,type_descriptors[itype].pb_type); - } - } - - /* Step 3: count the size of multiplexer that will be used in LUTs*/ - for (imodel = 0; imodel < spice->num_spice_model; imodel++) { - /* For those LUTs that netlists are not provided. We create a netlist and thus need a MUX*/ - if ((SPICE_MODEL_LUT == spice->spice_models[imodel].type) - &&(NULL == spice->spice_models[imodel].model_netlist)) { - stats_lut_spice_mux(&muxes_head, &(spice->spice_models[imodel])); - } - } - - /* Statistics after search routing resources */ - /* - temp = muxes_head; - while(temp) { - t_spice_mux_model* spice_mux_model = (t_spice_mux_model*)temp->dptr; - vpr_printf(TIO_MESSAGE_INFO,"Pb_types multiplexers: size=%d\n",spice_mux_model->size); - temp = temp->next; - } - */ - - return muxes_head; -} - - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.h deleted file mode 100644 index 6c8c6a4b8..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.h +++ /dev/null @@ -1,91 +0,0 @@ -#ifndef FPGA_X2P_MUX_UTILS_H -#define FPGA_X2P_MUX_UTILS_H - -int determine_num_sram_bits_mux_basis_subckt(t_spice_model* mux_spice_model, - int mux_size, - int num_input_per_level, - boolean special_basis); - -int determine_tree_mux_level(int mux_size); - -int determine_num_input_basis_multilevel_mux(int mux_size, - int mux_level); - -int tree_mux_last_level_input_num(int num_level, - int mux_size); - -int multilevel_mux_last_level_input_num(int num_level, int num_input_per_unit, - int mux_size); - -int determine_mux_local_encoder_num_inputs(int num_outputs); - -int* decode_onelevel_mux_sram_bits(int fan_in, - int mux_level, - int path_id, - boolean use_local_encoder); - -int* decode_multilevel_mux_sram_bits(int fan_in, - int mux_level, - int path_id, - boolean use_local_encoder); - -int* decode_tree_mux_sram_bits(int fan_in, - int mux_level, - int path_id); - -int get_mux_default_path_id(t_spice_model* mux_spice_model, - int mux_size, int path_id); - -int get_mux_full_input_size(t_spice_model* mux_spice_model, - int mux_size); - -void decode_cmos_mux_sram_bits(t_spice_model* mux_spice_model, - int mux_size, int path_id, - int* bit_len, int** conf_bits, int* mux_level); - -void decode_one_level_4t1r_mux(int path_id, - int bit_len, int* conf_bits); - -void decode_rram_mux(t_spice_model* mux_spice_model, - int mux_size, int path_id, - int* bit_len, int** conf_bits, int* mux_level); - -void init_spice_mux_arch(t_spice_model* spice_model, - t_spice_mux_arch* spice_mux_arch, - int mux_size); - -int find_spice_mux_arch_special_basis_size(t_spice_mux_arch spice_mux_arch); - -t_llist* search_mux_linked_list(t_llist* mux_head, - int mux_size, - t_spice_model* spice_model); - -void check_and_add_mux_to_linked_list(t_llist** muxes_head, - int mux_size, - t_spice_model* spice_model); - -void free_muxes_llist(t_llist* muxes_head); - -void stats_lut_spice_mux(t_llist** muxes_head, - t_spice_model* spice_model); - - -void stats_spice_muxes_routing_arch(t_llist** muxes_head, - int num_switch, - t_switch_inf* switches, - t_spice* spice, - t_det_routing_arch* routing_arch); - -void stats_mux_spice_model_pb_type_rec(t_llist** muxes_head, - t_pb_type* cur_pb_type); - -void stats_mux_spice_model_pb_node_rec(t_llist** muxes_head, - t_pb_graph_node* cur_pb_node); - -t_llist* stats_spice_muxes(int num_switch, - t_switch_inf* switches, - t_spice* spice, - t_det_routing_arch* routing_arch); - - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp deleted file mode 100644 index 7a61ae6c8..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp +++ /dev/null @@ -1,1394 +0,0 @@ -/******************************************************************** - * This file includes functions to generate module/port names for - * Verilog and SPICE netlists - * - * IMPORTANT: keep all the naming functions in this file to be - * generic for both Verilog and SPICE generators - ********************************************************************/ -#include "vtr_assert.h" - -#include "sides.h" -#include "vpr_types.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "circuit_library_utils.h" -#include "fpga_x2p_naming.h" - -/************************************************ - * Generate the node name for a multiplexing structure - * Case 1 : If there is an intermediate buffer followed by, - * the node name will be mux_l_in_buf - * Case 1 : If there is NO intermediate buffer followed by, - * the node name will be mux_l_in - ***********************************************/ -std::string generate_mux_node_name(const size_t& node_level, - const bool& add_buffer_postfix) { - /* Generate the basic node_name */ - std::string node_name = "mux_l" + std::to_string(node_level) + "_in"; - - /* Add a postfix upon requests */ - if (true == add_buffer_postfix) { - /* '1' indicates that the location is needed */ - node_name += "_buf"; - } - - return node_name; -} - - /************************************************ - * Generate the instance name for a branch circuit in multiplexing structure - * Case 1 : If there is an intermediate buffer followed by, - * the node name will be mux_l_in_buf - * Case 1 : If there is NO intermediate buffer followed by, - * the node name will be mux_l_in - ***********************************************/ -std::string generate_mux_branch_instance_name(const size_t& node_level, - const size_t& node_index_at_level, - const bool& add_buffer_postfix) { - return std::string(generate_mux_node_name(node_level, add_buffer_postfix) + "_" + std::to_string(node_index_at_level) + "_"); -} - -/************************************************ - * Generate the module name for a multiplexer in Verilog format - * Different circuit model requires different names: - * 1. LUTs are named as _mux - * 2. MUXes are named as _size - ***********************************************/ -std::string generate_mux_subckt_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size, - const std::string& postfix) { - std::string module_name = circuit_lib.model_name(circuit_model); - /* Check the model type and give different names */ - if (SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) { - module_name += "_size"; - module_name += std::to_string(mux_size); - } else { - VTR_ASSERT(SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)); - module_name += "_mux"; - } - - /* Add postfix if it is not empty */ - if (!postfix.empty()) { - module_name += postfix; - } - - return module_name; -} - -/************************************************ - * Generate the module name of a branch for a - * multiplexer in Verilog format - ***********************************************/ -std::string generate_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size, - const size_t& branch_mux_size, - const std::string& postfix) { - /* If the tgate spice model of this MUX is a MUX2 standard cell, - * the mux_subckt name will be the name of the standard cell - */ - CircuitModelId subckt_model = circuit_lib.pass_gate_logic_model(circuit_model); - if (SPICE_MODEL_GATE == circuit_lib.model_type(subckt_model)) { - VTR_ASSERT (SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(subckt_model)); - return circuit_lib.model_name(subckt_model); - } - std::string branch_postfix = postfix + "_size" + std::to_string(branch_mux_size); - - return generate_mux_subckt_name(circuit_lib, circuit_model, mux_size, branch_postfix); -} - -/************************************************ - * Generate the module name of a local decoder - * for multiplexer - ***********************************************/ -std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size, - const size_t& data_size) { - std::string subckt_name = "decoder"; - subckt_name += std::to_string(addr_size); - subckt_name += "to"; - subckt_name += std::to_string(data_size); - - return subckt_name; -} - -/************************************************ - * Generate the module name of a routing track wire - ***********************************************/ -std::string generate_segment_wire_subckt_name(const std::string& wire_model_name, - const size_t& segment_id) { - std::string segment_wire_subckt_name = wire_model_name + "_seg" + std::to_string(segment_id); - - return segment_wire_subckt_name; -} - -/********************************************************************* - * Generate the port name for the mid-output of a routing track wire - * Mid-output is the output that is wired to a Connection block multiplexer. - * - * | CLB | - * +------------+ - * ^ - * | - * +------------------------------+ - * | Connection block multiplexer | - * +------------------------------+ - * ^ - * | mid-output +-------------- - * +--------------------+ | - * input --->| Routing track wire |--------->| Switch Block - * +--------------------+ output | - * +-------------- - * - ********************************************************************/ -std::string generate_segment_wire_mid_output_name(const std::string& regular_output_name) { - /* TODO: maybe have a postfix? */ - return std::string("mid_" + regular_output_name); -} - -/********************************************************************* - * Generate the module name for a memory sub-circuit - ********************************************************************/ -std::string generate_memory_module_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const CircuitModelId& sram_model, - const std::string& postfix) { - return std::string( circuit_lib.model_name(circuit_model) + "_" + circuit_lib.model_name(sram_model) + postfix ); -} - -/********************************************************************* - * Generate the netlist name for a unique routing block - * It could be - * 1. Routing channel - * 2. Connection block - * 3. Switch block - * A unique block id should be given - *********************************************************************/ -std::string generate_routing_block_netlist_name(const std::string& prefix, - const size_t& block_id, - const std::string& postfix) { - return std::string( prefix + std::to_string(block_id) + postfix ); -} - -/********************************************************************* - * Generate the netlist name for a routing block with a given coordinate - * It could be - * 1. Routing channel - * 2. Connection block - * 3. Switch block - *********************************************************************/ -std::string generate_routing_block_netlist_name(const std::string& prefix, - const vtr::Point& coordinate, - const std::string& postfix) { - return std::string( prefix + std::to_string(coordinate.x()) + std::string("_") + std::to_string(coordinate.y()) + postfix ); -} - -/********************************************************************* - * Generate the netlist name for a connection block with a given coordinate - *********************************************************************/ -std::string generate_connection_block_netlist_name(const t_rr_type& cb_type, - const vtr::Point& coordinate, - const std::string& postfix) { - std::string prefix("cb"); - switch (cb_type) { - case CHANX: - prefix += std::string("x_"); - break; - case CHANY: - prefix += std::string("y_"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } - - return generate_routing_block_netlist_name(prefix, coordinate, postfix); -} - -/********************************************************************* - * Generate the module name for a unique routing channel - *********************************************************************/ -std::string generate_routing_channel_module_name(const t_rr_type& chan_type, - const size_t& block_id) { - /* Channel must be either CHANX or CHANY */ - VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) ); - - /* Create a map between chan_type and module_prefix */ - std::map module_prefix_map; - /* TODO: use a constexpr string to replace the fixed name? */ - module_prefix_map[CHANX] = std::string("chanx"); - module_prefix_map[CHANY] = std::string("chany"); - - return std::string( module_prefix_map[chan_type] + std::string("_") + std::to_string(block_id) + std::string("_") ); -} - -/********************************************************************* - * Generate the module name for a routing channel with a given coordinate - *********************************************************************/ -std::string generate_routing_channel_module_name(const t_rr_type& chan_type, - const vtr::Point& coordinate) { - /* Channel must be either CHANX or CHANY */ - VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) ); - - /* Create a map between chan_type and module_prefix */ - std::map module_prefix_map; - /* TODO: use a constexpr string to replace the fixed name? */ - module_prefix_map[CHANX] = std::string("chanx"); - module_prefix_map[CHANY] = std::string("chany"); - - return std::string( module_prefix_map[chan_type] + std::to_string(coordinate.x()) + std::string("_") + std::to_string(coordinate.y()) + std::string("_") ); -} - -/********************************************************************* - * Generate the port name for a routing track with a given coordinate - * and port direction - * This function is mainly used in naming routing tracks in the top-level netlists - * where we do need unique names (with coordinates) for each routing tracks - *********************************************************************/ -std::string generate_routing_track_port_name(const t_rr_type& chan_type, - const vtr::Point& coordinate, - const size_t& track_id, - const PORTS& port_direction) { - /* Channel must be either CHANX or CHANY */ - VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) ); - - /* Create a map between chan_type and module_prefix */ - std::map module_prefix_map; - /* TODO: use a constexpr string to replace the fixed name? */ - module_prefix_map[CHANX] = std::string("chanx"); - module_prefix_map[CHANY] = std::string("chany"); - - std::string port_name = module_prefix_map[chan_type]; - port_name += std::string("_" + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("__")); - - switch (port_direction) { - case OUT_PORT: - port_name += std::string("out_"); - break; - case IN_PORT: - port_name += std::string("in_"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of chan_rr_node!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Add the track id to the port name */ - port_name += std::to_string(track_id) + std::string("_"); - - return port_name; -} - -/********************************************************************* - * Generate the port name for a routing track in a Switch Block module - * This function is created to ease the PnR for each unique routing module - * So it is mainly used when creating non-top-level modules! - * Note that this function does not include any port coordinate - * Instead, we use the relative location of the pins in the context of routing modules - * so that each module can be instanciated across the fabric - * Even though, port direction must be provided! - *********************************************************************/ -std::string generate_sb_module_track_port_name(const t_rr_type& chan_type, - const e_side& module_side, - const size_t& track_id, - const PORTS& port_direction) { - /* Channel must be either CHANX or CHANY */ - VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) ); - - /* Create a map between chan_type and module_prefix */ - std::map module_prefix_map; - /* TODO: use a constexpr string to replace the fixed name? */ - module_prefix_map[CHANX] = std::string("chanx"); - module_prefix_map[CHANY] = std::string("chany"); - - std::string port_name = module_prefix_map[chan_type]; - port_name += std::string("_"); - - Side side_manager(module_side); - port_name += std::string(side_manager.to_string()); - port_name += std::string("_"); - - switch (port_direction) { - case OUT_PORT: - port_name += std::string("out_"); - break; - case IN_PORT: - port_name += std::string("in_"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of chan_rr_node!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Add the track id to the port name */ - port_name += std::to_string(track_id) + std::string("_"); - - return port_name; -} - -/********************************************************************* - * Generate the port name for a routing track in a Connection Block module - * This function is created to ease the PnR for each unique routing module - * So it is mainly used when creating non-top-level modules! - * Note that this function does not include any port coordinate - * Instead, we use the relative location of the pins in the context of routing modules - * so that each module can be instanciated across the fabric - * Even though, port direction must be provided! - *********************************************************************/ -std::string generate_cb_module_track_port_name(const t_rr_type& chan_type, - const size_t& track_id, - const PORTS& port_direction) { - /* Channel must be either CHANX or CHANY */ - VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) ); - - /* Create a map between chan_type and module_prefix */ - std::map module_prefix_map; - /* TODO: use a constexpr string to replace the fixed name? */ - module_prefix_map[CHANX] = std::string("chanx"); - module_prefix_map[CHANY] = std::string("chany"); - - std::string port_name = module_prefix_map[chan_type]; - port_name += std::string("_"); - - switch (port_direction) { - case OUT_PORT: - port_name += std::string("out_"); - break; - case IN_PORT: - port_name += std::string("in_"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of chan_rr_node!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Add the track id to the port name */ - port_name += std::to_string(track_id) + std::string("_"); - - return port_name; -} - -/********************************************************************* - * Generate the middle output port name for a routing track - * with a given coordinate - *********************************************************************/ -std::string generate_routing_track_middle_output_port_name(const t_rr_type& chan_type, - const vtr::Point& coordinate, - const size_t& track_id) { - /* Channel must be either CHANX or CHANY */ - VTR_ASSERT( (CHANX == chan_type) || (CHANY == chan_type) ); - - /* Create a map between chan_type and module_prefix */ - std::map module_prefix_map; - /* TODO: use a constexpr string to replace the fixed name? */ - module_prefix_map[CHANX] = std::string("chanx"); - module_prefix_map[CHANY] = std::string("chany"); - - std::string port_name = module_prefix_map[chan_type]; - port_name += std::string("_" + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("__")); - - port_name += std::string("midout_"); - - /* Add the track id to the port name */ - port_name += std::to_string(track_id) + std::string("_"); - - return port_name; -} - -/********************************************************************* - * Generate the module name for a switch block with a given coordinate - *********************************************************************/ -std::string generate_switch_block_module_name(const vtr::Point& coordinate) { - return std::string( "sb_" + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("_") ); -} - -/********************************************************************* - * Generate the module name for a connection block with a given coordinate - *********************************************************************/ -std::string generate_connection_block_module_name(const t_rr_type& cb_type, - const vtr::Point& coordinate) { - std::string prefix("cb"); - switch (cb_type) { - case CHANX: - prefix += std::string("x_"); - break; - case CHANY: - prefix += std::string("y_"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } - - return std::string( prefix + std::to_string(coordinate.x()) + std::string("__") + std::to_string(coordinate.y()) + std::string("_") ); -} - -/********************************************************************* - * Generate the port name for a grid in top-level netlists, i.e., full FPGA fabric - * This function will generate a full port name including coordinates - * so that each pin in top-level netlists is unique! - *********************************************************************/ -std::string generate_grid_port_name(const vtr::Point& coordinate, - const size_t& height, - const e_side& side, - const size_t& pin_id, - const bool& for_top_netlist) { - if (true == for_top_netlist) { - std::string port_name = std::string("grid_"); - port_name += std::to_string(coordinate.x()); - port_name += std::string("__"); - port_name += std::to_string(coordinate.y()); - port_name += std::string("__pin_"); - port_name += std::to_string(height); - port_name += std::string("__"); - port_name += std::to_string(size_t(side)); - port_name += std::string("__"); - port_name += std::to_string(pin_id); - port_name += std::string("_"); - return port_name; - } - /* For non-top netlist */ - VTR_ASSERT( false == for_top_netlist ); - Side side_manager(side); - std::string port_name = std::string(side_manager.to_string()); - port_name += std::string("_height_"); - port_name += std::to_string(height); - port_name += std::string("__pin_"); - port_name += std::to_string(pin_id); - port_name += std::string("_"); - return port_name; -} - -/********************************************************************* - * Generate the port name for a grid with duplication - * This function will generate two types of port names. - * One with a postfix of "upper" - * The other with a postfix of "lower" - *********************************************************************/ -std::string generate_grid_duplicated_port_name(const size_t& height, - const e_side& side, - const size_t& pin_id, - const bool& upper_port) { - /* For non-top netlist */ - Side side_manager(side); - std::string port_name = std::string(side_manager.to_string()); - port_name += std::string("_height_"); - port_name += std::to_string(height); - port_name += std::string("__pin_"); - port_name += std::to_string(pin_id); - port_name += std::string("_"); - - if (true == upper_port) { - port_name += std::string("upper"); - } else { - VTR_ASSERT_SAFE(false == upper_port); - port_name += std::string("lower"); - } - - return port_name; -} - - -/********************************************************************* - * Generate the port name for a grid in the context of a module - * To keep a short and simple name, this function will not - * include any grid coorindate information! - *********************************************************************/ -std::string generate_grid_module_port_name(const size_t& pin_id) { - /* For non-top netlist */ - std::string port_name = std::string("grid_"); - port_name += std::string("pin_"); - port_name += std::to_string(pin_id); - port_name += std::string("_"); - return port_name; -} - -/********************************************************************* - * Generate the port name for a Grid - * This is a wrapper function for generate_port_name() - * which can automatically decode the port name by the pin side and height - *********************************************************************/ -std::string generate_grid_side_port_name(const std::vector>& grids, - const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id) { - /* Output the pins on the side*/ - size_t height = find_grid_pin_height(grids, coordinate, pin_id); - if (1 != grids[coordinate.x()][coordinate.y()].type->pinloc[height][side][pin_id]) { - Side side_manager(side); - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Fail to generate a grid pin (x=%lu, y=%lu, height=%lu, side=%s, index=%d)\n", - __FILE__, __LINE__, - coordinate.x(), coordinate.y(), height, side_manager.c_str(), pin_id); - exit(1); - } - return generate_grid_port_name(coordinate, height, side, pin_id, true); -} - -/********************************************************************* - * Generate the port name of a grid pin for a routing module, - * which could be a switch block or a connection block - * Note that to ensure unique grid port name in the context of a routing module, - * we need a prefix which denotes the relative location of the port in the routing module - * - * The prefix is created by considering the the grid coordinate - * and switch block coordinate - * Detailed rules in conversion is as follows: - * - * top_left top_right - * +------------------------+ - * left_top | | right_top - * | Switch Block | - * | [x][y] | - * | | - * | | - * left_right | | right_bottom - * +------------------------+ - * bottom_left bottom_right - * - * +-------------------------------------------------------- - * | Grid Coordinate | Pin side of grid | module side - * +-------------------------------------------------------- - * | [x][y+1] | right | top_left - * +-------------------------------------------------------- - * | [x][y+1] | bottom | left_top - * +-------------------------------------------------------- - * | [x+1][y+1] | left | top_right - * +-------------------------------------------------------- - * | [x+1][y+1] | bottom | right_top - * +-------------------------------------------------------- - * | [x][y] | top | left_right - * +-------------------------------------------------------- - * | [x][y] | right | bottom_left - * +-------------------------------------------------------- - * | [x+1][y] | top | right_bottom - * +-------------------------------------------------------- - * | [x+1][y] | left | bottom_right - * +-------------------------------------------------------- - * - *********************************************************************/ -std::string generate_sb_module_grid_port_name(const e_side& sb_side, - const e_side& grid_side, - const size_t& pin_id) { - Side sb_side_manager(sb_side); - Side grid_side_manager(grid_side); - /* Relative location is opposite to the side in grid context */ - grid_side_manager.set_opposite(); - std::string prefix = sb_side_manager.to_string() + std::string("_") + grid_side_manager.to_string(); - return prefix + std::string("_") + generate_grid_module_port_name(pin_id); -} - -/********************************************************************* - * Generate the port name of a grid pin for a routing module, - * which could be a switch block or a connection block - * Note that to ensure unique grid port name in the context of a routing module, - * we need a prefix which denotes the relative location of the port in the routing module - *********************************************************************/ -std::string generate_cb_module_grid_port_name(const e_side& cb_side, - const size_t& pin_id) { - Side side_manager(cb_side); - std::string prefix = side_manager.to_string(); - return prefix + std::string("_") + generate_grid_module_port_name(pin_id); -} - -/********************************************************************* - * Generate the port name for a reserved sram port, i.e., BLB/WL port - * When port_type is BLB, a string denoting to the reserved BLB port is generated - * When port_type is WL, a string denoting to the reserved WL port is generated - * - * DO NOT put any SRAM organization check codes HERE!!! - * Even though the reserved BLB/WL ports are used by RRAM-based FPGA only, - * try to keep this function does simple job. - * Check codes should be added outside, when print the ports to files!!! - *********************************************************************/ -std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type) { - VTR_ASSERT( (port_type == SPICE_MODEL_PORT_BLB) || (port_type == SPICE_MODEL_PORT_WL) ); - - if (SPICE_MODEL_PORT_BLB == port_type) { - return std::string("reserved_blb"); - } - return std::string("reserved_wl"); -} - -/********************************************************************* - * Generate the port name for a sram port, used for formal verification - * The port name is named after the cell name of SRAM in circuit library - *********************************************************************/ -std::string generate_formal_verification_sram_port_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model) { - std::string port_name = circuit_lib.model_name(sram_model) + std::string("_out_fm"); - - return port_name; -} - -/********************************************************************* - * Generate the head port name of a configuration chain - * TODO: This could be replaced as a constexpr string - *********************************************************************/ -std::string generate_configuration_chain_head_name() { - return std::string("ccff_head"); -} - -/********************************************************************* - * Generate the tail port name of a configuration chain - * TODO: This could be replaced as a constexpr string - *********************************************************************/ -std::string generate_configuration_chain_tail_name() { - return std::string("ccff_tail"); -} - -/********************************************************************* - * Generate the memory output port name of a configuration chain - * TODO: This could be replaced as a constexpr string - *********************************************************************/ -std::string generate_configuration_chain_data_out_name() { - return std::string("mem_out"); -} - -/********************************************************************* - * Generate the inverted memory output port name of a configuration chain - * TODO: This could be replaced as a constexpr string - *********************************************************************/ -std::string generate_configuration_chain_inverted_data_out_name() { - return std::string("mem_outb"); -} - -/********************************************************************* - * Generate the addr port (input) for a local decoder of a multiplexer - * TODO: This could be replaced as a constexpr string - *********************************************************************/ -std::string generate_mux_local_decoder_addr_port_name() { - return std::string("addr"); -} - -/********************************************************************* - * Generate the data port (output) for a local decoder of a multiplexer - * TODO: This could be replaced as a constexpr string - *********************************************************************/ -std::string generate_mux_local_decoder_data_port_name() { - return std::string("data"); -} - -/********************************************************************* - * Generate the inverted data port (output) for a local decoder of a multiplexer - * TODO: This could be replaced as a constexpr string - *********************************************************************/ -std::string generate_mux_local_decoder_data_inv_port_name() { - return std::string("data_inv"); -} - -/********************************************************************* - * Generate the port name of a local configuration bus - * TODO: This could be replaced as a constexpr string - *********************************************************************/ -std::string generate_local_config_bus_port_name() { - return std::string("config_bus"); -} - -/********************************************************************* - * Generate the port name for a regular sram port which appears in the - * port list of a module - * The port name is named after the cell name of SRAM in circuit library - *********************************************************************/ -std::string generate_sram_port_name(const e_sram_orgz& sram_orgz_type, - const e_spice_model_port_type& port_type) { - std::string port_name; - - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: { - /* Two types of ports are available: - * (1) Regular output of a SRAM, enabled by port type of INPUT - * (2) Inverted output of a SRAM, enabled by port type of OUTPUT - */ - if (SPICE_MODEL_PORT_INPUT == port_type) { - port_name = std::string("mem_out"); - } else { - VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); - port_name = std::string("mem_outb"); - } - break; - } - case SPICE_SRAM_SCAN_CHAIN: - /* Two types of ports are available: - * (1) Head of a chain of Configuration-chain Flip-Flops (CCFFs), enabled by port type of INPUT - * (2) Tail of a chian of Configuration-chain Flip-flops (CCFFs), enabled by port type of OUTPUT - * +------+ +------+ +------+ - * Head --->| CCFF |--->| CCFF |--->| CCFF |---> Tail - * +------+ +------+ +------+ - */ - if (SPICE_MODEL_PORT_INPUT == port_type) { - port_name = std::string("ccff_head"); - } else { - VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); - port_name = std::string("ccff_tail"); - } - break; - case SPICE_SRAM_MEMORY_BANK: - /* Four types of ports are available: - * (1) Bit Lines (BLs) of a SRAM cell, enabled by port type of BL - * (2) Word Lines (WLs) of a SRAM cell, enabled by port type of WL - * (3) Inverted Bit Lines (BLBs) of a SRAM cell, enabled by port type of BLB - * (4) Inverted Word Lines (WLBs) of a SRAM cell, enabled by port type of WLB - * - * BL BLB WL WLB BL BLB WL WLB BL BLB WL WLB - * [0] [0] [0] [0] [1] [1] [1] [1] [i] [i] [i] [i] - * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ - * | | | | | | | | | | | | - * +----------+ +----------+ +----------+ - * | SRAM | | SRAM | ... | SRAM | - * +----------+ +----------+ +----------+ - */ - if (SPICE_MODEL_PORT_BL == port_type) { - port_name = std::string("bl"); - } else if (SPICE_MODEL_PORT_WL == port_type) { - port_name = std::string("wl"); - } else if (SPICE_MODEL_PORT_BLB == port_type) { - port_name = std::string("blb"); - } else { - VTR_ASSERT( SPICE_MODEL_PORT_WLB == port_type ); - port_name = std::string("wlb"); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization !\n", - __FILE__, __LINE__); - exit(1); - } - - return port_name; -} - -/********************************************************************* - * Generate the port name for a regular sram port which is an internal - * wire of a module - * The port name is named after the cell name of SRAM in circuit library - *********************************************************************/ -std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz& sram_orgz_type, - const e_spice_model_port_type& port_type) { - std::string port_name = circuit_lib.model_name(sram_model) + std::string("_"); - - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: { - /* Two types of ports are available: - * (1) Regular output of a SRAM, enabled by port type of INPUT - * (2) Inverted output of a SRAM, enabled by port type of OUTPUT - */ - if (SPICE_MODEL_PORT_INPUT == port_type) { - port_name += std::string("out_local_bus"); - } else { - VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); - port_name += std::string("outb_local_bus"); - } - break; - } - case SPICE_SRAM_SCAN_CHAIN: - /* Three types of ports are available: - * (1) Input of Configuration-chain Flip-Flops (CCFFs), enabled by port type of INPUT - * (2) Output of a chian of Configuration-chain Flip-flops (CCFFs), enabled by port type of OUTPUT - * (2) Inverted output of a chian of Configuration-chain Flip-flops (CCFFs), enabled by port type of INOUT - * +------+ +------+ +------+ - * Head --->| CCFF |--->| CCFF |--->| CCFF |---> Tail - * +------+ +------+ +------+ - */ - if (SPICE_MODEL_PORT_INPUT == port_type) { - port_name += std::string("ccff_in_local_bus"); - } else if ( SPICE_MODEL_PORT_OUTPUT == port_type ) { - port_name += std::string("ccff_out_local_bus"); - } else { - VTR_ASSERT( SPICE_MODEL_PORT_INOUT == port_type ); - port_name += std::string("ccff_outb_local_bus"); - } - break; - case SPICE_SRAM_MEMORY_BANK: { - /* Two types of ports are available: - * (1) Regular output of a SRAM, enabled by port type of INPUT - * (2) Inverted output of a SRAM, enabled by port type of OUTPUT - */ - if (SPICE_MODEL_PORT_INPUT == port_type) { - port_name += std::string("out_local_bus"); - } else { - VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); - port_name += std::string("outb_local_bus"); - } - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization !\n", - __FILE__, __LINE__); - exit(1); - } - - return port_name; -} - -/********************************************************************* - * Generate the port name for the input bus of a routing multiplexer - * This is very useful in Verilog code generation where the inputs of - * a routing multiplexer may come from different ports. - * On the other side, the datapath input of a routing multiplexer - * is defined as a bus port. - * Therefore, to interface, a bus port is required, and this function - * give a name to the bus port - * To keep the bus port name unique to each multiplexer we will instance, - * a mux_instance_id should be provided by user - *********************************************************************/ -std::string generate_mux_input_bus_port_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const size_t& mux_size, - const size_t& mux_instance_id) { - std::string postfix = std::string("_") + std::to_string(mux_instance_id) + std::string("_inbus"); - return generate_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); -} - -/********************************************************************* - * Generate the name of a bus port which is wired to the configuration - * ports of a routing multiplexer - * This port is supposed to be used locally inside a Verilog/SPICE module - *********************************************************************/ -std::string generate_mux_config_bus_port_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const size_t& mux_size, - const size_t& bus_id, - const bool& inverted) { - std::string postfix = std::string("_configbus") + std::to_string(bus_id); - /* Add a bar to the end of the name for inverted bus ports */ - if (true == inverted) { - postfix += std::string("_b"); - } - - return generate_mux_subckt_name(circuit_lib, mux_model, mux_size, postfix); -} - -/********************************************************************* - * Generate the port name for a SRAM port of a circuit - * This name is used for local wires that connecting SRAM ports - * of a circuit model inside a Verilog/SPICE module - * Note that the SRAM ports share the same naming - * convention regardless of their configuration style - *********************************************************************/ -std::string generate_local_sram_port_name(const std::string& port_prefix, - const size_t& instance_id, - const e_spice_model_port_type& port_type) { - std::string port_name = port_prefix + std::string("_") + std::to_string(instance_id) + std::string("_"); - - if (SPICE_MODEL_PORT_INPUT == port_type) { - port_name += std::string("out"); - } else { - VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type ); - port_name += std::string("outb"); - } - - return port_name; -} - -/********************************************************************* - * Generate the port name for a SRAM port of a routing multiplexer - * This name is used for local wires that connecting SRAM ports - * of routing multiplexers inside a Verilog/SPICE module - * Note that the SRAM ports of routing multiplexers share the same naming - * convention regardless of their configuration style - **********************************************************************/ -std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const size_t& mux_size, - const size_t& mux_instance_id, - const e_spice_model_port_type& port_type) { - std::string prefix = generate_mux_subckt_name(circuit_lib, mux_model, mux_size, std::string()); - return generate_local_sram_port_name(prefix, mux_instance_id, port_type); -} - -/********************************************************************* - * Generate the prefix for naming a grid block netlist or a grid module - * This function will consider the io side and add it to the prefix - **********************************************************************/ -std::string generate_grid_block_prefix(const std::string& prefix, - const e_side& io_side) { - std::string block_prefix(prefix); - - if (NUM_SIDES != io_side) { - Side side_manager(io_side); - block_prefix += std::string(side_manager.to_string()); - block_prefix += std::string("_"); - } - - return block_prefix; -} - -/********************************************************************* - * Generate the netlist name of a grid block - **********************************************************************/ -std::string generate_grid_block_netlist_name(const std::string& block_name, - const bool& is_block_io, - const e_side& io_side, - const std::string& postfix) { - /* Add the name of physical block */ - std::string module_name(block_name); - - if (true == is_block_io) { - Side side_manager(io_side); - module_name += std::string("_"); - module_name += std::string(side_manager.to_string()); - } - - module_name += postfix; - - return module_name; -} - -/********************************************************************* - * Generate the module name of a grid block - **********************************************************************/ -std::string generate_grid_block_module_name(const std::string& prefix, - const std::string& block_name, - const bool& is_block_io, - const e_side& io_side) { - std::string module_name(prefix); - - module_name += generate_grid_block_netlist_name(block_name, is_block_io, io_side, std::string()); - - return module_name; -} - -/********************************************************************* - * Generate the instance name for a programmable routing multiplexer module - * in a Switch Block - * To keep a unique name in each module and also consider unique routing modules, - * please do NOT include any coordinates in the naming!!! - * Consider only relative coordinate, such as side! - ********************************************************************/ -std::string generate_sb_mux_instance_name(const std::string& prefix, - const e_side& sb_side, - const size_t& track_id, - const std::string& postfix) { - std::string instance_name(prefix); - instance_name += Side(sb_side).to_string(); - instance_name += std::string("_track_") + std::to_string(track_id); - instance_name += postfix; - - return instance_name; -} - -/********************************************************************* - * Generate the instance name for a configurable memory module in a Switch Block - * To keep a unique name in each module and also consider unique routing modules, - * please do NOT include any coordinates in the naming!!! - * Consider only relative coordinate, such as side! - ********************************************************************/ -std::string generate_sb_memory_instance_name(const std::string& prefix, - const e_side& sb_side, - const size_t& track_id, - const std::string& postfix) { - std::string instance_name(prefix); - instance_name += Side(sb_side).to_string(); - instance_name += std::string("_track_") + std::to_string(track_id); - instance_name += postfix; - - return instance_name; -} - -/********************************************************************* - * Generate the instance name for a programmable routing multiplexer module - * in a Connection Block - * To keep a unique name in each module and also consider unique routing modules, - * please do NOT include any coordinates in the naming!!! - * Consider only relative coordinate, such as side! - ********************************************************************/ -std::string generate_cb_mux_instance_name(const std::string& prefix, - const e_side& cb_side, - const size_t& pin_id, - const std::string& postfix) { - std::string instance_name(prefix); - - instance_name += Side(cb_side).to_string(); - instance_name += std::string("_ipin_") + std::to_string(pin_id); - instance_name += postfix; - - return instance_name; -} - -/********************************************************************* - * Generate the instance name for a configurable memory module in a Connection Block - * To keep a unique name in each module and also consider unique routing modules, - * please do NOT include any coordinates in the naming!!! - * Consider only relative coordinate, such as side! - ********************************************************************/ -std::string generate_cb_memory_instance_name(const std::string& prefix, - const e_side& cb_side, - const size_t& pin_id, - const std::string& postfix) { - std::string instance_name(prefix); - - instance_name += Side(cb_side).to_string(); - instance_name += std::string("_ipin_") + std::to_string(pin_id); - instance_name += postfix; - - return instance_name; -} - -/********************************************************************* - * Generate the instance name for a programmable routing multiplexer - * module in a physical block of a grid - * To guarentee a unique name for pb_graph pin, - * the instance name includes the index of parent node - * as well as the port name and pin index of this pin - * - * Exceptions: - * For OUTPUT ports, due to hierarchical module organization, - * their parent nodes will be uniquified - * So, we should not add any index here - ********************************************************************/ -std::string generate_pb_mux_instance_name(const std::string& prefix, - t_pb_graph_pin* pb_graph_pin, - const std::string& postfix) { - std::string instance_name(prefix); - instance_name += std::string(pb_graph_pin->parent_node->pb_type->name); - - if (IN_PORT == pb_graph_pin->port->type) { - instance_name += std::string("_"); - instance_name += std::to_string(pb_graph_pin->parent_node->placement_index); - } - - instance_name += std::string("_"); - instance_name += std::string(pb_graph_pin->port->name); - instance_name += std::string("_"); - instance_name += std::to_string(pb_graph_pin->pin_number); - instance_name += postfix; - - return instance_name; -} - -/********************************************************************* - * Generate the instance name for a configurable memory module in a - * physical block of a grid - * To guarentee a unique name for pb_graph pin, - * the instance name includes the index of parent node - * as well as the port name and pin index of this pin - * - * Exceptions: - * For OUTPUT ports, due to hierarchical module organization, - * their parent nodes will be uniquified - * So, we should not add any index here - ********************************************************************/ -std::string generate_pb_memory_instance_name(const std::string& prefix, - t_pb_graph_pin* pb_graph_pin, - const std::string& postfix) { - std::string instance_name(prefix); - instance_name += std::string(pb_graph_pin->parent_node->pb_type->name); - - if (IN_PORT == pb_graph_pin->port->type) { - instance_name += std::string("_"); - instance_name += std::to_string(pb_graph_pin->parent_node->placement_index); - } - - instance_name += std::string("_"); - instance_name += std::string(pb_graph_pin->port->name); - instance_name += std::string("_"); - instance_name += std::to_string(pb_graph_pin->pin_number); - instance_name += postfix; - - return instance_name; -} - -/********************************************************************* - * Generate the instance name of a grid block - **********************************************************************/ -std::string generate_grid_block_instance_name(const std::string& prefix, - const std::string& block_name, - const bool& is_block_io, - const e_side& io_side, - const vtr::Point& grid_coord) { - std::string module_name(prefix); - - module_name += generate_grid_block_netlist_name(block_name, is_block_io, io_side, std::string()); - module_name += std::string("_"); - module_name += std::to_string(grid_coord.x()); - module_name += std::string("_"); - module_name += std::to_string(grid_coord.y()); - - return module_name; -} - -/********************************************************************* - * Generate the module name of a physical block - * To ensure a unique name for each physical block inside the graph of complex blocks - * (pb_graph_nodes), this function trace backward to the top-level node - * in the graph and add the name of these parents - * The final name will be in the following format: - * __ ... - * - * TODO: to make sure the length of this name does not exceed the size of - * chars in a line of a file!!! - **********************************************************************/ -std::string generate_physical_block_module_name(const std::string& prefix, - t_pb_type* physical_pb_type) { - std::string module_name(physical_pb_type->name); - - t_pb_type* parent_pb_type = physical_pb_type; - - /* Backward trace until we meet the top-level pb_type */ - while (1) { - /* If there is no parent mode, this is a top-level pb_type, quit the loop here */ - t_mode* parent_mode = parent_pb_type->parent_mode; - if (NULL == parent_mode) { - break; - } - - /* Add the mode name to the module name */ - module_name = std::string("mode_") + std::string(parent_mode->name) + std::string("__") + module_name; - - /* Backtrace to the upper level */ - parent_pb_type = parent_mode->parent_pb_type; - - /* If there is no parent pb_type, this is a top-level pb_type, quit the loop here */ - if (NULL == parent_pb_type) { - break; - } - - /* Add the current pb_type name to the module name */ - module_name = std::string(parent_pb_type->name) + std::string("_") + module_name; - } - - /* Exception for top-level pb_type: add an virtual mode name (same name as the pb_type) - * This is to follow the naming convention as non top-level pb_types - * In addition, the name can be really unique, being different than the grid blocks - */ - if (NULL == physical_pb_type->parent_mode) { - module_name += std::string("_mode_") + std::string(physical_pb_type->name) + std::string("_"); - } - - /* Add the prefix */ - module_name = prefix + module_name; - - return module_name; -} - - -/********************************************************************* - * Generate the instance name for physical block with a given index - **********************************************************************/ -std::string generate_physical_block_instance_name(const std::string& prefix, - t_pb_type* pb_type, - const size_t& index) { - std::string instance_name = generate_physical_block_module_name(prefix, pb_type); - /* Add index to the name */ - instance_name += std::string("_"); - instance_name += std::to_string(index); - - return instance_name; -} - -/********************************************************************* - * This function is a wrapper for the function generate_physical_block_module_name() - * which can automatically decode the io_side and add a prefix - **********************************************************************/ -std::string generate_grid_physical_block_module_name(const std::string& prefix, - t_pb_type* pb_type, - const e_side& border_side) { - std::string module_name_prefix = generate_grid_block_prefix(prefix, border_side); - return generate_physical_block_module_name(module_name_prefix, pb_type); -} - -/********************************************************************* - * Generate the instance name for physical block in Grid with a given index - **********************************************************************/ -std::string generate_grid_physical_block_instance_name(const std::string& prefix, - t_pb_type* pb_type, - const e_side& border_side, - const size_t& index) { - std::string module_name_prefix = generate_grid_block_prefix(prefix, border_side); - std::string instance_name = generate_physical_block_module_name(module_name_prefix, pb_type); - /* Add index to the name */ - instance_name += std::string("_"); - instance_name += std::to_string(index); - - return instance_name; -} - -/******************************************************************** - * This function try to infer if a grid locates at the border of a - * FPGA fabric, i.e., TOP/RIGHT/BOTTOM/LEFT sides - * 1. if this grid is on the border, it will return the side it locates, - * 2. if this grid is in the center, it will return an valid value NUM_SIDES - * - * In this function, we assume that the corner grids are actually empty! - * - * +-------+ +----------------------------+ +-------+ - * | EMPTY | | TOP side I/O | | EMPTY | - * +-------+ +----------------------------+ +-------+ - * - * +-------+ +----------------------------+ +-------+ - * | | | | | | - * | | | | | | - * | | | | | | - * | LEFT | | | | RIGHT | - * | side | | Core grids | | side | - * | I/O | | | | I/O | - * | | | | | | - * | | | | | | - * | | | | | | - * | | | | | | - * +-------+ +----------------------------+ +-------+ - * - * +-------+ +----------------------------+ +-------+ - * | EMPTY | | BOTTOM side I/O | | EMPTY | - * +-------+ +----------------------------+ +-------+ - *******************************************************************/ -e_side find_grid_border_side(const vtr::Point& device_size, - const vtr::Point& grid_coordinate) { - e_side grid_side = NUM_SIDES; - - if (device_size.y() - 1 == grid_coordinate.y()) { - return TOP; - } - if (device_size.x() - 1 == grid_coordinate.x()) { - return RIGHT; - } - if (0 == grid_coordinate.y()) { - return BOTTOM; - } - if (0 == grid_coordinate.x()) { - return LEFT; - } - - return grid_side; -} - -/******************************************************************** - * This function try to infer if a grid locates at the border of the - * core FPGA fabric, i.e., TOP/RIGHT/BOTTOM/LEFT sides - * 1. if this grid is on the border and it matches the given side, return true, - * 2. if this grid is in the center, return false - * - * In this function, we assume that the corner grids are actually empty! - * - * +-------+ +----------------------------+ +-------+ - * | EMPTY | | TOP side I/O | | EMPTY | - * +-------+ +----------------------------+ +-------+ - * - * +-------+ +----------------------------+ +-------+ - * | | | TOP | | | - * | | |----------------------------| | | - * | | | | | | | | - * | LEFT | | | | | | RIGHT | - * | side | | LEFT | Core grids | RIGHT| | side | - * | I/O | | | | | | I/O | - * | | | | | | | | - * | | | | | | | | - * | | |---------------------| | | | - * | | | BOTTOM | | | | - * +-------+ +----------------------------+ +-------+ - * - * +-------+ +----------------------------+ +-------+ - * | EMPTY | | BOTTOM side I/O | | EMPTY | - * +-------+ +----------------------------+ +-------+ - * - * Note: for the blocks on the four corners of the core grids - * Please refer to the figure above to infer its border_side - *******************************************************************/ -bool is_core_grid_on_given_border_side(const vtr::Point& device_size, - const vtr::Point& grid_coordinate, - const e_side& border_side) { - - if ( (device_size.y() - 2 == grid_coordinate.y()) - && (TOP == border_side) ) { - return true; - } - if ( (device_size.x() - 2 == grid_coordinate.x()) - && (RIGHT == border_side) ) { - return true; - } - if ( (1 == grid_coordinate.y()) - && (BOTTOM == border_side) ) { - return true; - } - if ( (1 == grid_coordinate.x()) - && (LEFT == border_side) ) { - return true; - } - - return false; -} - - -/********************************************************************* - * Generate the port name of a Verilog module describing a pb_type - * The name convention is - * _ - ********************************************************************/ -std::string generate_pb_type_port_name(t_port* pb_type_port) { - std::string port_name; - - port_name = std::string(pb_type_port->parent_pb_type->name) + std::string("_") + std::string(pb_type_port->name); - - return port_name; -} - -/********************************************************************* - * Generate the global I/O port name of a Verilog module - * This is mainly used by I/O circuit models - ********************************************************************/ -std::string generate_fpga_global_io_port_name(const std::string& prefix, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const CircuitPortId& circuit_port) { - std::string port_name(prefix); - - port_name += circuit_lib.model_name(circuit_model); - port_name += std::string("_"); - port_name += circuit_lib.port_prefix(circuit_port); - - return port_name; -} - -/********************************************************************* - * Generate the module name for the top-level module - * The top-level module is actually the FPGA fabric - * We give a fixed name here, because it is independent from benchmark file - ********************************************************************/ -std::string generate_fpga_top_module_name() { - return std::string("fpga_top"); -} - -/********************************************************************* - * Generate the netlist name for the top-level module - * The top-level module is actually the FPGA fabric - * We give a fixed name here, because it is independent from benchmark file - ********************************************************************/ -std::string generate_fpga_top_netlist_name(const std::string& postfix) { - return std::string("fpga_top" + postfix); -} - -/********************************************************************* - * Generate the module name for a constant generator - * either VDD or GND, depending on the input argument - ********************************************************************/ -std::string generate_const_value_module_name(const size_t& const_val) { - if (0 == const_val) { - return std::string("const0"); - } - - VTR_ASSERT (1 == const_val); - return std::string("const1"); -} - -/********************************************************************* - * Generate the output port name for a constant generator module - * either VDD or GND, depending on the input argument - ********************************************************************/ -std::string generate_const_value_module_output_port_name(const size_t& const_val) { - return generate_const_value_module_name(const_val); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h deleted file mode 100644 index a62523f59..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h +++ /dev/null @@ -1,246 +0,0 @@ -/************************************************ - * Header file for fpga_x2p_naming.cpp - * Include functions to generate module/port names - * for Verilog and SPICE netlists - ***********************************************/ - -#ifndef FPGA_X2P_NAMING_H -#define FPGA_X2P_NAMING_H - -#include - -#include "vtr_geometry.h" -#include "circuit_library.h" -#include "vpr_types.h" - -constexpr char* FPGA_X2P_DEFAULT_SDC_DIR = "SDC"; - -std::string generate_mux_node_name(const size_t& node_level, - const bool& add_buffer_postfix); - -std::string generate_mux_branch_instance_name(const size_t& node_level, - const size_t& node_index_at_level, - const bool& add_buffer_postfix); - -std::string generate_mux_subckt_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size, - const std::string& posfix) ; - -std::string generate_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const size_t& mux_size, - const size_t& branch_mux_size, - const std::string& posfix); - -std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size, - const size_t& data_size); - -std::string generate_segment_wire_subckt_name(const std::string& wire_model_name, - const size_t& segment_id); - -std::string generate_segment_wire_mid_output_name(const std::string& regular_output_name); - -std::string generate_memory_module_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const CircuitModelId& sram_model, - const std::string& postfix); - -std::string generate_routing_block_netlist_name(const std::string& prefix, - const size_t& block_id, - const std::string& postfix); - -std::string generate_routing_block_netlist_name(const std::string& prefix, - const vtr::Point& block_id, - const std::string& postfix); - -std::string generate_connection_block_netlist_name(const t_rr_type& cb_type, - const vtr::Point& coordinate, - const std::string& postfix); - -std::string generate_routing_channel_module_name(const t_rr_type& chan_type, - const size_t& block_id); - -std::string generate_routing_channel_module_name(const t_rr_type& chan_type, - const vtr::Point& coordinate); - -std::string generate_routing_track_port_name(const t_rr_type& chan_type, - const vtr::Point& coordinate, - const size_t& track_id, - const PORTS& port_direction); - -std::string generate_sb_module_track_port_name(const t_rr_type& chan_type, - const e_side& module_side, - const size_t& track_id, - const PORTS& port_direction); - -std::string generate_cb_module_track_port_name(const t_rr_type& chan_type, - const size_t& track_id, - const PORTS& port_direction); - -std::string generate_routing_track_middle_output_port_name(const t_rr_type& chan_type, - const vtr::Point& coordinate, - const size_t& track_id); - -std::string generate_switch_block_module_name(const vtr::Point& coordinate); - -std::string generate_connection_block_module_name(const t_rr_type& cb_type, - const vtr::Point& coordinate); - -std::string generate_sb_mux_instance_name(const std::string& prefix, - const e_side& sb_side, - const size_t& track_id, - const std::string& postfix); - -std::string generate_sb_memory_instance_name(const std::string& prefix, - const e_side& sb_side, - const size_t& track_id, - const std::string& postfix); - -std::string generate_cb_mux_instance_name(const std::string& prefix, - const e_side& cb_side, - const size_t& pin_id, - const std::string& postfix); - -std::string generate_cb_memory_instance_name(const std::string& prefix, - const e_side& cb_side, - const size_t& pin_id, - const std::string& postfix); - -std::string generate_pb_mux_instance_name(const std::string& prefix, - t_pb_graph_pin* pb_graph_pin, - const std::string& postfix); - -std::string generate_pb_memory_instance_name(const std::string& prefix, - t_pb_graph_pin* pb_graph_pin, - const std::string& postfix); - -std::string generate_grid_port_name(const vtr::Point& coordinate, - const size_t& height, - const e_side& side, - const size_t& pin_id, - const bool& for_top_netlist); - -std::string generate_grid_duplicated_port_name(const size_t& height, - const e_side& side, - const size_t& pin_id, - const bool& upper_port); - -std::string generate_grid_module_port_name(const size_t& pin_id); - -std::string generate_sb_module_grid_port_name(const e_side& sb_side, - const e_side& grid_side, - const size_t& pin_id); - -std::string generate_cb_module_grid_port_name(const e_side& cb_side, - const size_t& pin_id); - -std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type); - -std::string generate_formal_verification_sram_port_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model); - -std::string generate_configuration_chain_head_name(); - -std::string generate_configuration_chain_tail_name(); - -std::string generate_configuration_chain_data_out_name(); - -std::string generate_configuration_chain_inverted_data_out_name(); - -std::string generate_mux_local_decoder_addr_port_name(); - -std::string generate_mux_local_decoder_data_port_name(); - -std::string generate_mux_local_decoder_data_inv_port_name(); - -std::string generate_local_config_bus_port_name(); - -std::string generate_sram_port_name(const e_sram_orgz& sram_orgz_type, - const e_spice_model_port_type& port_type); - -std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz& sram_orgz_type, - const e_spice_model_port_type& port_type); - -std::string generate_mux_input_bus_port_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const size_t& mux_size, - const size_t& mux_instance_id); - -std::string generate_mux_config_bus_port_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const size_t& mux_size, - const size_t& bus_id, - const bool& inverted); - -std::string generate_local_sram_port_name(const std::string& port_prefix, - const size_t& instance_id, - const e_spice_model_port_type& port_type); - -std::string generate_mux_sram_port_name(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const size_t& mux_size, - const size_t& mux_instance_id, - const e_spice_model_port_type& port_type); - -std::string generate_grid_block_prefix(const std::string& prefix, - const e_side& io_side); - -std::string generate_grid_block_netlist_name(const std::string& block_name, - const bool& is_block_io, - const e_side& io_side, - const std::string& postfix); - -std::string generate_grid_block_module_name(const std::string& prefix, - const std::string& block_name, - const bool& is_block_io, - const e_side& io_side); - -std::string generate_grid_block_instance_name(const std::string& prefix, - const std::string& block_name, - const bool& is_block_io, - const e_side& io_side, - const vtr::Point& grid_coord); - -std::string generate_physical_block_module_name(const std::string& prefix, - t_pb_type* physical_pb_type); - -std::string generate_physical_block_instance_name(const std::string& prefix, - t_pb_type* pb_type, - const size_t& index); - -std::string generate_grid_physical_block_module_name(const std::string& prefix, - t_pb_type* pb_type, - const e_side& border_side); - -std::string generate_grid_physical_block_instance_name(const std::string& prefix, - t_pb_type* pb_type, - const e_side& border_side, - const size_t& index); - - -e_side find_grid_border_side(const vtr::Point& device_size, - const vtr::Point& grid_coordinate); - -bool is_core_grid_on_given_border_side(const vtr::Point& device_size, - const vtr::Point& grid_coordinate, - const e_side& border_side); - -std::string generate_pb_type_port_name(t_port* pb_type_port); - -std::string generate_fpga_global_io_port_name(const std::string& prefix, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const CircuitPortId& circuit_port); - -std::string generate_fpga_top_module_name(); - -std::string generate_fpga_top_netlist_name(const std::string& postfix); - -std::string generate_const_value_module_name(const size_t& const_val); - -std::string generate_const_value_module_output_port_name(const size_t& const_val); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c deleted file mode 100644 index 45de820d8..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.c +++ /dev/null @@ -1,3386 +0,0 @@ -/******************************************************************** - * This file includes most utilized functions to operate on pb_type - * related data structures, including t_pb_type, t_pb_graph_node, t_pb - * - * Note: - * If you want to classify functions, functions in this file should meet - * at least one of it - * 1. non-generic data query of pb_type - related data structures - * 2. non-generic mutator/copy the pb_type - * - * Generic accessors/mutators should be a method of the data structure - ********************************************************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "vtr_assert.h" -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include SPICE support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_lut_utils.h" -#include "fpga_x2p_bitstream_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_globals.h" - -/* Make sure the edge has only one input pin and output pin*/ -void check_pb_graph_edge(t_pb_graph_edge pb_graph_edge) { - assert(1 == pb_graph_edge.num_input_pins); - assert(1 == pb_graph_edge.num_output_pins); - - return; -} - -/* Check all the edges for a given pb_graph_pin*/ -void check_pb_graph_pin_edges(t_pb_graph_pin pb_graph_pin) { - int iedge; - - for (iedge = 0; iedge < pb_graph_pin.num_input_edges; iedge++) { - check_pb_graph_edge(*(pb_graph_pin.input_edges[iedge])); - } - - for (iedge = 0; iedge < pb_graph_pin.num_output_edges; iedge++) { - check_pb_graph_edge(*(pb_graph_pin.output_edges[iedge])); - } - - return; -} - -void backup_one_pb_rr_node_pack_prev_node_edge(t_rr_node* pb_rr_node) { - - pb_rr_node->prev_node_in_pack = pb_rr_node->prev_node; - pb_rr_node->prev_edge_in_pack = pb_rr_node->prev_edge; - pb_rr_node->net_num_in_pack = pb_rr_node->net_num; - pb_rr_node->prev_node = OPEN; - pb_rr_node->prev_edge = OPEN; - - return; -} - -int find_parent_pb_type_child_index(t_pb_type* parent_pb_type, - int mode_index, - t_pb_type* child_pb_type) { - int i; - - assert(NULL != parent_pb_type); - assert(NULL != child_pb_type); - assert((!(0 > mode_index))&&(mode_index < parent_pb_type->num_modes)); - - for (i = 0; i < parent_pb_type->modes[mode_index].num_pb_type_children; i++) { - if (child_pb_type == &(parent_pb_type->modes[mode_index].pb_type_children[i])) { - assert(0 == strcmp(child_pb_type->name, parent_pb_type->modes[mode_index].pb_type_children[i].name)); - return i; - } - } - - return -1; -} - -/* Rule in generating a unique name: - * name of current pb = _[index] - */ -void gen_spice_name_tag_phy_pb_rec(t_phy_pb* cur_phy_pb, - char* prefix) { - char* prefix_rec = NULL; - int ipb, jpb, mode_index; - - mode_index = cur_phy_pb->mode; - - /* Free previous name_tag if there is */ - /* my_free(cur_pb->spice_name_tag); */ - - /* Generate the name_tag */ - if ((0 < cur_phy_pb->pb_graph_node->pb_type->num_modes) - &&(NULL == cur_phy_pb->pb_graph_node->pb_type->spice_model_name)) { - prefix_rec = (char*)my_malloc(sizeof(char)*(strlen(prefix) + 1 - + strlen(cur_phy_pb->pb_graph_node->pb_type->name) + 1 - + strlen(my_itoa(cur_phy_pb->pb_graph_node->placement_index)) + 7 - + strlen(cur_phy_pb->pb_graph_node->pb_type->modes[mode_index].name) + 2 )); - sprintf(prefix_rec, "%s_%s[%d]_mode[%s]", - prefix, cur_phy_pb->pb_graph_node->pb_type->name, cur_phy_pb->pb_graph_node->placement_index, cur_phy_pb->pb_graph_node->pb_type->modes[mode_index].name); - cur_phy_pb->spice_name_tag = my_strdup(prefix_rec); - } else { - assert((0 == cur_phy_pb->pb_graph_node->pb_type->num_modes) - ||(NULL != cur_phy_pb->pb_graph_node->pb_type->spice_model_name)); - prefix_rec = (char*)my_malloc(sizeof(char)*(strlen(prefix) + 1 - + strlen(cur_phy_pb->pb_graph_node->pb_type->name) + 1 - + strlen(my_itoa(cur_phy_pb->pb_graph_node->placement_index)) + 2 )); - sprintf(prefix_rec, "%s_%s[%d]", - prefix, cur_phy_pb->pb_graph_node->pb_type->name, cur_phy_pb->pb_graph_node->placement_index); - cur_phy_pb->spice_name_tag = my_strdup(prefix_rec); - } - - /* When reach the leaf, we directly return */ - /* Recursive until reach the leaf */ - if ((0 == cur_phy_pb->pb_graph_node->pb_type->num_modes) - ||(NULL == cur_phy_pb->child_pbs)) { - return; - } - for (ipb = 0; ipb < cur_phy_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_phy_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Refer to pack/output_clustering.c [LINE 392] */ - //if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - /* Try to simplify the name tag... to avoid exceeding the length of SPICE name (up to 1024 chars) */ - /* gen_spice_name_tag_pb_rec(&(cur_pb->child_pbs[ipb][jpb]),prefix); */ - gen_spice_name_tag_phy_pb_rec(&(cur_phy_pb->child_pbs[ipb][jpb]),prefix_rec); - //} - } - } - - my_free(prefix_rec); - - return; -} - - -/* Rule in generating a unique name: - * name of current pb = _[index] - */ -void gen_spice_name_tag_pb_rec(t_pb* cur_pb, - char* prefix) { - char* prefix_rec = NULL; - int ipb, jpb, mode_index; - - mode_index = cur_pb->mode; - - /* Free previous name_tag if there is */ - /* my_free(cur_pb->spice_name_tag); */ - - /* Generate the name_tag */ - if ((0 < cur_pb->pb_graph_node->pb_type->num_modes) - &&(NULL == cur_pb->pb_graph_node->pb_type->spice_model_name)) { - prefix_rec = (char*)my_malloc(sizeof(char)*(strlen(prefix) + 1 + strlen(cur_pb->pb_graph_node->pb_type->name) + 1 - + strlen(my_itoa(cur_pb->pb_graph_node->placement_index)) + 7 + strlen(cur_pb->pb_graph_node->pb_type->modes[mode_index].name) + 2 )); - sprintf(prefix_rec, "%s_%s[%d]_mode[%s]", - prefix, cur_pb->pb_graph_node->pb_type->name, cur_pb->pb_graph_node->placement_index, cur_pb->pb_graph_node->pb_type->modes[mode_index].name); - cur_pb->spice_name_tag = my_strdup(prefix_rec); - } else { - assert((0 == cur_pb->pb_graph_node->pb_type->num_modes) - ||(NULL != cur_pb->pb_graph_node->pb_type->spice_model_name)); - prefix_rec = (char*)my_malloc(sizeof(char)*(strlen(prefix) + 1 + strlen(cur_pb->pb_graph_node->pb_type->name) + 1 - + strlen(my_itoa(cur_pb->pb_graph_node->placement_index)) + 2 )); - sprintf(prefix_rec, "%s_%s[%d]", - prefix, cur_pb->pb_graph_node->pb_type->name, cur_pb->pb_graph_node->placement_index); - cur_pb->spice_name_tag = my_strdup(prefix_rec); - } - - /* When reach the leaf, we directly return */ - /* Recursive until reach the leaf */ - if ((0 == cur_pb->pb_graph_node->pb_type->num_modes) - ||(NULL == cur_pb->child_pbs)) { - return; - } - for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Refer to pack/output_clustering.c [LINE 392] */ - //if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - /* Try to simplify the name tag... to avoid exceeding the length of SPICE name (up to 1024 chars) */ - /* gen_spice_name_tag_pb_rec(&(cur_pb->child_pbs[ipb][jpb]),prefix); */ - gen_spice_name_tag_pb_rec(&(cur_pb->child_pbs[ipb][jpb]),prefix_rec); - //} - } - } - - my_free(prefix_rec); - - return; -} - -/* Generate a unique name tag for each pb, - * to identify it in both SPICE netlist and Power Modeling. - */ -void gen_spice_name_tags_all_pbs() { - int iblk; - char* prefix = NULL; - - for (iblk = 0; iblk < num_blocks; iblk++) { - prefix = (char*)my_malloc(sizeof(char)*(5 + strlen(my_itoa(block[iblk].x)) + 2 + strlen(my_itoa(block[iblk].y)) + 2 + strlen(my_itoa(block[iblk].z)) + 2)); - sprintf(prefix, "grid[%d][%d][%d]", block[iblk].x, block[iblk].y, block[iblk].z); - gen_spice_name_tag_pb_rec(block[iblk].pb, prefix); - my_free(prefix); - } - - return; -} - -/* Generate a unique name tag for each pb, - * to identify it in both SPICE netlist and Power Modeling. - */ -void gen_spice_name_tags_all_phy_pbs() { - int iblk; - char* prefix = NULL; - - for (iblk = 0; iblk < num_blocks; iblk++) { - prefix = (char*)my_malloc(sizeof(char)*(5 + strlen(my_itoa(block[iblk].x)) + 2 + strlen(my_itoa(block[iblk].y)) + 2)); - sprintf(prefix, "grid[%d][%d]", block[iblk].x, block[iblk].y); - gen_spice_name_tag_phy_pb_rec((t_phy_pb*)block[iblk].phy_pb, prefix); - my_free(prefix); - } - - return; -} - - -int find_pb_mapped_logical_block_rec(t_pb* cur_pb, - t_spice_model* pb_spice_model, - char* pb_spice_name_tag) { - int logical_block_index = OPEN; - int mode_index, ipb, jpb; - - assert(NULL != cur_pb); - - if ((pb_spice_model == cur_pb->pb_graph_node->pb_type->spice_model) - &&(0 == strcmp(cur_pb->spice_name_tag, pb_spice_name_tag))) { - /* Return the logic block we may find */ - switch (pb_spice_model->type) { - case SPICE_MODEL_LUT : - /* Special for LUT... They have sub modes!!!*/ - assert(NULL != cur_pb->child_pbs); - return cur_pb->child_pbs[0][0].logical_block; - case SPICE_MODEL_FF: - assert(pb_spice_model == logical_block[cur_pb->logical_block].mapped_spice_model); - return cur_pb->logical_block; - case SPICE_MODEL_HARDLOGIC: - if (NULL != cur_pb->child_pbs) { - return cur_pb->child_pbs[0][0].logical_block; - } else { - assert(pb_spice_model == logical_block[cur_pb->logical_block].mapped_spice_model); - return cur_pb->logical_block; - } - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid spice model type!\n", - __FILE__, __LINE__); - exit(1); - } - } - - /* Go recursively ... */ - mode_index = cur_pb->mode; - if (0 == cur_pb->pb_graph_node->pb_type->num_modes) { - return logical_block_index; - } - for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - logical_block_index = - find_pb_mapped_logical_block_rec(&(cur_pb->child_pbs[ipb][jpb]), pb_spice_model, pb_spice_name_tag); - if (OPEN != logical_block_index) { - return logical_block_index; - } - } - } - } - - return logical_block_index; -} - -int find_grid_mapped_logical_block(int x, int y, - t_spice_model* pb_spice_model, - char* pb_spice_name_tag) { - int logical_block_index = OPEN; - int iblk; - - /* Find the grid usage */ - if (0 == grid[x][y].usage) { - return logical_block_index; - } else { - assert(0 < grid[x][y].usage); - /* search each block */ - for (iblk = 0; iblk < grid[x][y].usage; iblk++) { - /* Get the pb */ - logical_block_index = find_pb_mapped_logical_block_rec(block[grid[x][y].blocks[iblk]].pb, - pb_spice_model, pb_spice_name_tag); - if (OPEN != logical_block_index) { - return logical_block_index; - } - } - } - - return logical_block_index; -} - -void stats_pb_graph_node_port_pin_numbers(t_pb_graph_node* cur_pb_graph_node, - int* num_inputs, - int* num_outputs, - int* num_clock_pins) { - int iport; - - assert(NULL != cur_pb_graph_node); - - (*num_inputs) = 0; - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - (*num_inputs) += cur_pb_graph_node->num_input_pins[iport]; - } - (*num_outputs) = 0; - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - (*num_outputs) += cur_pb_graph_node->num_output_pins[iport]; - } - (*num_clock_pins) = 0; - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - (*num_clock_pins) += cur_pb_graph_node->num_clock_pins[iport]; - } - - return; -} - -int find_pb_type_idle_mode_index(t_pb_type cur_pb_type) { - int idle_mode_index = 0; - int imode = 0; - int num_idle_mode = 0; - - /* if we touch the leaf node */ - if (NULL != cur_pb_type.blif_model) { - return 0; - } - - if (0 == cur_pb_type.num_modes) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Intend to find the idle mode while cur_pb_type has 0 modes!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Corner case: - * If there is only 1 mode available, it will be the idle_mode by default! - */ - if (1 == cur_pb_type.num_modes) { - idle_mode_index = 0; - num_idle_mode++; - return idle_mode_index; - } - - /* Normal Condition: */ - for (imode = 0; imode < cur_pb_type.num_modes; imode++) { - if (1 == cur_pb_type.modes[imode].define_idle_mode) { - idle_mode_index = imode; - num_idle_mode++; - } - } - - assert(1 == num_idle_mode); - - return idle_mode_index; -} - -/* Find the physical mode index */ -int find_pb_type_physical_mode_index(t_pb_type cur_pb_type) { - int phy_mode_index = 0; - int imode = 0; - int num_phy_mode = 0; - - /* if we touch the leaf node */ - if (NULL != cur_pb_type.blif_model) { - return 0; - } - - if (0 == cur_pb_type.num_modes) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Intend to find the physical mode while cur_pb_type has 0 modes!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Corner case: - * If there is only 1 mode available, it will be the physical_mode by default! - */ - if (1 == cur_pb_type.num_modes) { - phy_mode_index = 0; - num_phy_mode++; - return phy_mode_index; - } - - /* Normal Condition: */ - for (imode = 0; imode < cur_pb_type.num_modes; imode++) { - if (1 == cur_pb_type.modes[imode].define_physical_mode) { - phy_mode_index = imode; - num_phy_mode++; - } - } - if (1 != num_phy_mode) { - assert(1 == num_phy_mode); - } - - return phy_mode_index; -} - -void mark_grid_type_pb_graph_node_pins_temp_net_num(int x, int y) { - int iport, ipin, type_pin_index, class_id, pin_global_rr_node_id; - t_type_ptr type = NULL; - t_pb_graph_node* top_pb_graph_node = NULL; - int mode_index, ipb, jpb; - - /* Assert */ - assert((!(x < 0))&&(x < (nx + 2))); - assert((!(y < 0))&&(y < (ny + 2))); - - type = grid[x][y].type; - - if (EMPTY_TYPE == type) { - return; /* Bypass empty grid */ - } - - top_pb_graph_node = type->pb_graph_head; - /* Input ports */ - for (iport = 0; iport < top_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ipin++) { - top_pb_graph_node->input_pins[iport][ipin].temp_net_num = OPEN; - type_pin_index = top_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; - class_id = type->pin_class[type_pin_index]; - assert(RECEIVER == type->class_inf[class_id].type); - /* Find the pb net_num and update OPIN net_num */ - pin_global_rr_node_id = get_rr_node_index(x, y, IPIN, type_pin_index, rr_node_indices); - if (OPEN == rr_node[pin_global_rr_node_id].net_num) { - top_pb_graph_node->input_pins[iport][ipin].temp_net_num = OPEN; - continue; - } - top_pb_graph_node->input_pins[iport][ipin].temp_net_num = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; - } - } - /* clock ports */ - for (iport = 0; iport < top_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ipin++) { - top_pb_graph_node->clock_pins[iport][ipin].temp_net_num = OPEN; - type_pin_index = top_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster; - class_id = type->pin_class[type_pin_index]; - assert(RECEIVER == type->class_inf[class_id].type); - /* Find the pb net_num and update OPIN net_num */ - pin_global_rr_node_id = get_rr_node_index(x, y, IPIN, type_pin_index, rr_node_indices); - if (OPEN == rr_node[pin_global_rr_node_id].net_num) { - top_pb_graph_node->clock_pins[iport][ipin].temp_net_num = OPEN; - continue; - } - top_pb_graph_node->clock_pins[iport][ipin].temp_net_num = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; - } - } - - /* Go recursively ... */ - mode_index = find_pb_type_idle_mode_index(*(top_pb_graph_node->pb_type)); - for (ipb = 0; ipb < top_pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < top_pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Mark pb_graph_node temp_net_num */ - rec_mark_pb_graph_node_temp_net_num(&(top_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb])); - } - } - - /* Output ports */ - for (iport = 0; iport < top_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ipin++) { - top_pb_graph_node->output_pins[iport][ipin].temp_net_num = OPEN; - type_pin_index = top_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; - class_id = type->pin_class[type_pin_index]; - assert(DRIVER == type->class_inf[class_id].type); - /* Find the pb net_num and update OPIN net_num */ - pin_global_rr_node_id = get_rr_node_index(x, y, OPIN, type_pin_index, rr_node_indices); - if (OPEN == rr_node[pin_global_rr_node_id].net_num) { - top_pb_graph_node->output_pins[iport][ipin].temp_net_num = OPEN; - continue; - } - top_pb_graph_node->output_pins[iport][ipin].temp_net_num = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; - } - } - - /* Run again to handle feedback loop */ - /* Input ports */ - for (iport = 0; iport < top_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ipin++) { - top_pb_graph_node->input_pins[iport][ipin].temp_net_num = OPEN; - type_pin_index = top_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; - class_id = type->pin_class[type_pin_index]; - assert(RECEIVER == type->class_inf[class_id].type); - /* Find the pb net_num and update OPIN net_num */ - pin_global_rr_node_id = get_rr_node_index(x, y, IPIN, type_pin_index, rr_node_indices); - if (OPEN == rr_node[pin_global_rr_node_id].net_num) { - top_pb_graph_node->input_pins[iport][ipin].temp_net_num = OPEN; - continue; - } - top_pb_graph_node->input_pins[iport][ipin].temp_net_num = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; - } - } - /* clock ports */ - for (iport = 0; iport < top_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ipin++) { - top_pb_graph_node->clock_pins[iport][ipin].temp_net_num = OPEN; - type_pin_index = top_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster; - class_id = type->pin_class[type_pin_index]; - assert(RECEIVER == type->class_inf[class_id].type); - /* Find the pb net_num and update OPIN net_num */ - pin_global_rr_node_id = get_rr_node_index(x, y, IPIN, type_pin_index, rr_node_indices); - if (OPEN == rr_node[pin_global_rr_node_id].net_num) { - top_pb_graph_node->clock_pins[iport][ipin].temp_net_num = OPEN; - continue; - } - top_pb_graph_node->clock_pins[iport][ipin].temp_net_num = clb_to_vpack_net_mapping[rr_node[pin_global_rr_node_id].net_num]; - } - } - - return; -} - -/* Assign the temp_net_num by considering the first incoming edge that belongs to the correct operating mode */ -void assign_pb_graph_node_pin_temp_net_num_by_mode_index(t_pb_graph_pin* cur_pb_graph_pin, - int mode_index) { - int iedge; - - /* IMPORTANT: I assume by default the index of selected edge is 0 - * Make sure this input edge comes from the default mode - */ - for (iedge = 0; iedge < cur_pb_graph_pin->num_input_edges; iedge++) { - if (mode_index != cur_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode_index) { - continue; - } - cur_pb_graph_pin->temp_net_num = cur_pb_graph_pin->input_edges[iedge]->input_pins[0]->temp_net_num; - break; - } - - return; -} - -void mark_pb_graph_node_input_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node, - int mode_index) { - int iport, ipin; - - assert(NULL != cur_pb_graph_node); - - /* Input ports */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - cur_pb_graph_node->input_pins[iport][ipin].temp_net_num = OPEN; - /* IMPORTANT: I assume by default the index of selected edge is 0 - * Make sure this input edge comes from the default mode - */ - assign_pb_graph_node_pin_temp_net_num_by_mode_index(&(cur_pb_graph_node->input_pins[iport][ipin]), mode_index); - } - } - - return; -} - -void mark_pb_graph_node_clock_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node, - int mode_index) { - int iport, ipin; - - assert(NULL != cur_pb_graph_node); - - /* Clock ports */ - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - cur_pb_graph_node->clock_pins[iport][ipin].temp_net_num = OPEN; - assign_pb_graph_node_pin_temp_net_num_by_mode_index(&(cur_pb_graph_node->clock_pins[iport][ipin]), mode_index); - } - } - - return; -} - -void mark_pb_graph_node_output_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node, - int mode_index) { - int iport, ipin; - - assert(NULL != cur_pb_graph_node); - - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - cur_pb_graph_node->output_pins[iport][ipin].temp_net_num = OPEN; - /* IMPORTANT: I assume by default the index of selected edge is 0 - * Make sure this input edge comes from the default mode - */ - assign_pb_graph_node_pin_temp_net_num_by_mode_index(&(cur_pb_graph_node->output_pins[iport][ipin]), mode_index); - } - } - - return; -} - -/* Mark temp_net_num in current pb_graph_node from the parent pb_graph_node */ -void rec_mark_pb_graph_node_temp_net_num(t_pb_graph_node* cur_pb_graph_node) { - int mode_index, ipb, jpb; - - assert(NULL != cur_pb_graph_node); - - /* Find the default mode */ - mode_index = find_pb_type_idle_mode_index(*(cur_pb_graph_node->pb_type)); - - mark_pb_graph_node_input_pins_temp_net_num(cur_pb_graph_node, mode_index); - - mark_pb_graph_node_clock_pins_temp_net_num(cur_pb_graph_node, mode_index); - - if (TRUE == is_primitive_pb_type(cur_pb_graph_node->pb_type)) { - return; - } - - /* Go recursively ... */ - mode_index = find_pb_type_idle_mode_index(*(cur_pb_graph_node->pb_type)); - for (ipb = 0; ipb < cur_pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Mark pb_graph_node temp_net_num */ - rec_mark_pb_graph_node_temp_net_num(&(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb])); - } - } - - /* IMPORTANT: update the temp_net of Output ports after recursion is done! - * the outputs of sub pb_graph_node should be updated first - */ - mark_pb_graph_node_output_pins_temp_net_num(cur_pb_graph_node, mode_index); - - /* Do this again to handle feedback loops ! */ - mark_pb_graph_node_input_pins_temp_net_num(cur_pb_graph_node, mode_index); - - mark_pb_graph_node_clock_pins_temp_net_num(cur_pb_graph_node, mode_index); - - return; -} - -void load_one_pb_graph_pin_temp_net_num_from_pb(t_phy_pb* cur_pb, - t_pb_graph_pin* cur_pb_graph_pin) { - int node_index; - t_rr_node* pb_rr_nodes = NULL; - - assert(NULL != cur_pb); - assert(NULL != cur_pb->pb_graph_node); - - /* Get the selected edge of current pin*/ - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = cur_pb_graph_pin->rr_node_index_physical_pb; - cur_pb_graph_pin->temp_net_num = pb_rr_nodes[node_index].vpack_net_num; - - return; -} - -/* According to the vpack_net_num in cur_pb - * assign it to the corresponding pb_graph_pins - */ -void load_pb_graph_node_temp_net_num_from_pb(t_phy_pb* cur_pb) { - int iport, ipin; - - assert(NULL != cur_pb); - assert(NULL != cur_pb->pb_graph_node); - - /* Input ports */ - for (iport = 0; iport < cur_pb->pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb->pb_graph_node->num_input_pins[iport]; ipin++) { - load_one_pb_graph_pin_temp_net_num_from_pb(cur_pb, - &(cur_pb->pb_graph_node->input_pins[iport][ipin])); - } - } - - /* Clock ports */ - for (iport = 0; iport < cur_pb->pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb->pb_graph_node->num_clock_pins[iport]; ipin++) { - load_one_pb_graph_pin_temp_net_num_from_pb(cur_pb, - &(cur_pb->pb_graph_node->clock_pins[iport][ipin])); - } - } - - /* Output ports */ - for (iport = 0; iport < cur_pb->pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb->pb_graph_node->num_output_pins[iport]; ipin++) { - load_one_pb_graph_pin_temp_net_num_from_pb(cur_pb, - &(cur_pb->pb_graph_node->output_pins[iport][ipin])); - } - } - - return; -} - -/* Recursively traverse the hierachy of a pb, - * store parasitic nets in the temp_net_num of the assoicated pb_graph_node - */ -void rec_mark_one_pb_unused_pb_graph_node_temp_net_num(t_phy_pb* cur_pb) { - int ipb, jpb; - int mode_index; - - /* Check */ - assert(NULL != cur_pb); - - if (TRUE == is_primitive_pb_type(cur_pb->pb_graph_node->pb_type)) { - return; - } - - /* Go recursively ... */ - mode_index = cur_pb->mode; - for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - rec_mark_one_pb_unused_pb_graph_node_temp_net_num(&(cur_pb->child_pbs[ipb][jpb])); - } else { - /* Print idle graph_node muxes */ - load_pb_graph_node_temp_net_num_from_pb(cur_pb); - /* We should update the net_num */ - rec_mark_pb_graph_node_temp_net_num(cur_pb->child_pbs[ipb][jpb].pb_graph_node); - } - } - } - - return; -} - -void update_pb_vpack_net_num_from_temp_net_num(t_phy_pb* cur_pb, - t_pb_graph_pin* cur_pb_graph_pin) { - int node_index; - t_rr_node* pb_rr_nodes = NULL; - - assert(NULL != cur_pb); - assert(NULL != cur_pb->pb_graph_node); - - /* Get the selected edge of current pin*/ - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = cur_pb_graph_pin->rr_node_index_physical_pb; - - /* Avoid mistakenly modification */ - if (OPEN != pb_rr_nodes[node_index].vpack_net_num) { - return; - } - /* Only modify when original vpack_net_num is open!!! */ - pb_rr_nodes[node_index].vpack_net_num = cur_pb_graph_pin->temp_net_num; - - return; -} - -void update_pb_graph_node_temp_net_num_to_pb(t_pb_graph_node* cur_pb_graph_node, - t_phy_pb* cur_pb) { - int iport, ipin; - - assert(NULL != cur_pb->pb_graph_node); - assert(NULL != cur_pb); - - /* Input ports */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - update_pb_vpack_net_num_from_temp_net_num(cur_pb, - &(cur_pb_graph_node->input_pins[iport][ipin])); - } - } - - /* Clock ports */ - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - update_pb_vpack_net_num_from_temp_net_num(cur_pb, - &(cur_pb_graph_node->clock_pins[iport][ipin])); - } - } - - /* Output ports */ - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - update_pb_vpack_net_num_from_temp_net_num(cur_pb, - &(cur_pb_graph_node->output_pins[iport][ipin])); - } - } - - return; -} - -void rec_load_unused_pb_graph_node_temp_net_num_to_pb(t_phy_pb* cur_pb) { - int ipb, jpb; - int mode_index; - - /* Check */ - assert(NULL != cur_pb); - - if (NULL != cur_pb->pb_graph_node->pb_type->spice_model) { - return; - } - /* Go recursively ... */ - mode_index = cur_pb->mode; - if (!(0 < cur_pb->pb_graph_node->pb_type->num_modes)) { - return; - } - for (ipb = 0; ipb < cur_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb->pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - rec_load_unused_pb_graph_node_temp_net_num_to_pb(&(cur_pb->child_pbs[ipb][jpb])); - } else { - update_pb_graph_node_temp_net_num_to_pb(cur_pb->child_pbs[ipb][jpb].pb_graph_node, - cur_pb); - } - } - } - - return; -} - -void mark_one_pb_parasitic_nets(t_phy_pb* cur_pb) { - - /* By go recursively, parasitic net num are stored in the temp_net_num in pb_graph_node */ - rec_mark_one_pb_unused_pb_graph_node_temp_net_num(cur_pb); - - /* Load the temp_net_num to vpack_net_num in the current pb! */ - rec_load_unused_pb_graph_node_temp_net_num_to_pb(cur_pb); - - return; -} - -int count_num_conf_bit_one_interc(t_interconnect* cur_interc, - enum e_sram_orgz cur_sram_orgz_type) { - int fan_in = 0; - enum e_interconnect spice_interc_type = DIRECT_INTERC; - - int num_conf_bits = 0; - - /* 1. identify pin interconnection type, - * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) - * 3. Select and print the SPICE netlist - */ - if (NULL == cur_interc) { - return num_conf_bits; - } else { - fan_in = cur_interc->fan_in; - if (0 == fan_in) { - return num_conf_bits; - } - } - /* Initialize the interconnection type that will be implemented in SPICE netlist*/ - switch (cur_interc->type) { - case DIRECT_INTERC: - assert(cur_interc->fan_out == fan_in); - spice_interc_type = DIRECT_INTERC; - break; - case COMPLETE_INTERC: - if (1 == fan_in) { - spice_interc_type = DIRECT_INTERC; - } else { - assert((2 == fan_in)||(2 < fan_in)); - spice_interc_type = MUX_INTERC; - } - break; - case MUX_INTERC: - assert((2 == fan_in)||(2 < fan_in)); - spice_interc_type = MUX_INTERC; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", - __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); - exit(1); - } - /* This time, (2nd round), count the number of configuration bits, according to interc type*/ - switch (spice_interc_type) { - case DIRECT_INTERC: - /* Check : - * 1. Direct interc has only one fan-in! - */ - assert((cur_interc->fan_out == fan_in) - ||((COMPLETE_INTERC == cur_interc->type)&&(1 == fan_in))); - break; - case COMPLETE_INTERC: - case MUX_INTERC: - /* Check : - * MUX should have at least 2 fan_in - */ - assert((2 == fan_in)||(2 < fan_in)); - assert((1 == cur_interc->fan_out)||(1 < cur_interc->fan_out)); - /* 2. spice_model is a wire */ - assert(NULL != cur_interc->spice_model); - assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); - num_conf_bits = count_num_conf_bits_one_spice_model(cur_interc->spice_model, - cur_sram_orgz_type, fan_in); - /* FOR COMPLETE_INTERC: we should consider fan_out number ! */ - num_conf_bits = num_conf_bits * cur_interc->fan_out; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", - __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); - exit(1); - } - return num_conf_bits; -} - -/* Count the number of configuration bits of interconnection inside a pb_type in its default mode */ -int count_num_conf_bits_pb_type_mode_interc(t_mode* cur_pb_type_mode, - enum e_sram_orgz cur_sram_orgz_type) { - int num_conf_bits = 0; - int jinterc = 0; - - for (jinterc = 0; jinterc < cur_pb_type_mode->num_interconnect; jinterc++) { - num_conf_bits += count_num_conf_bit_one_interc(&(cur_pb_type_mode->interconnect[jinterc]), - cur_sram_orgz_type); - } - - return num_conf_bits; -} - -/* Count the number of configuration bits of interconnection inside a pb_type in its default mode */ -static -int count_num_reserved_conf_bits_pb_type_mode_interc(t_mode* cur_pb_type_mode, - enum e_sram_orgz cur_sram_orgz_type) { - int num_reserved_conf_bits = 0; - int temp_num_reserved_conf_bits = 0; - int jinterc = 0; - - for (jinterc = 0; jinterc < cur_pb_type_mode->num_interconnect; jinterc++) { - /* num of reserved configuration bits is determined by the largest one */ - temp_num_reserved_conf_bits = - count_num_reserved_conf_bit_one_interc(&(cur_pb_type_mode->interconnect[jinterc]), - cur_sram_orgz_type); - if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { - num_reserved_conf_bits = temp_num_reserved_conf_bits; - } - } - - return num_reserved_conf_bits; -} - -/* Count the number of configuration bits of a grid (type_descriptor) in default mode */ -int rec_count_num_conf_bits_pb_type_default_mode(t_pb_type* cur_pb_type, - t_sram_orgz_info* cur_sram_orgz_info) { - int mode_index, ipb, jpb; - int sum_num_conf_bits = 0; - int num_reserved_conf_bits = 0; - int temp_num_reserved_conf_bits = 0; - - cur_pb_type->default_mode_num_conf_bits = 0; - - /* Recursively finish all the child pb_types*/ - if ((NULL == cur_pb_type->spice_model_name) - && (NULL == cur_pb_type->physical_pb_type_name)) { - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - rec_count_num_conf_bits_pb_type_default_mode(&(cur_pb_type->modes[mode_index].pb_type_children[ipb]), cur_sram_orgz_info); - } - } - } - - /* Check if this has defined a spice_model*/ - if ((NULL != cur_pb_type->spice_model_name) - || (NULL != cur_pb_type->physical_pb_type_name)) { - sum_num_conf_bits = count_num_conf_bits_one_spice_model(cur_pb_type->phy_pb_type->spice_model, cur_sram_orgz_info->type, 0); - cur_pb_type->default_mode_num_conf_bits = sum_num_conf_bits; - /* calculate the number of reserved configuration bits */ - cur_pb_type->default_mode_num_reserved_conf_bits = - count_num_reserved_conf_bits_one_spice_model(cur_pb_type->phy_pb_type->spice_model, - cur_sram_orgz_info->type, 0); - } else { /* Count the sum of configuration bits of all the children pb_types */ - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Count in the number of configuration bits of on child pb_type */ - sum_num_conf_bits += cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_conf_bits; - temp_num_reserved_conf_bits = - cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_reserved_conf_bits; - /* number of reserved conf. bits is deteremined by the largest number of reserved conf. bits !*/ - if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { - num_reserved_conf_bits = temp_num_reserved_conf_bits; - } - } - } - /* Count the number of configuration bits of interconnection */ - sum_num_conf_bits += count_num_conf_bits_pb_type_mode_interc(&(cur_pb_type->modes[mode_index]), cur_sram_orgz_info->type); - /* Count the number of reserved_configuration bits of interconnection */ - temp_num_reserved_conf_bits = - count_num_reserved_conf_bits_pb_type_mode_interc(&(cur_pb_type->modes[mode_index]), - cur_sram_orgz_info->type); - /* number of reserved conf. bits is deteremined by the largest number of reserved conf. bits !*/ - if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { - num_reserved_conf_bits = temp_num_reserved_conf_bits; - } - /* Update the info in pb_type */ - cur_pb_type->default_mode_num_reserved_conf_bits = num_reserved_conf_bits; - cur_pb_type->default_mode_num_conf_bits = sum_num_conf_bits; - } - - return sum_num_conf_bits; -} - -/* Count the number of configuration bits of a grid (type_descriptor) in default mode */ -int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type, - t_sram_orgz_info* cur_sram_orgz_info) { - int mode_index, ipb, jpb; - int sum_num_conf_bits = 0; - int num_reserved_conf_bits = 0; - int temp_num_reserved_conf_bits = 0; - - cur_pb_type->physical_mode_num_conf_bits = 0; - - /* Recursively finish all the child pb_types*/ - if ( FALSE == is_primitive_pb_type(cur_pb_type)) { - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - rec_count_num_conf_bits_pb_type_physical_mode(&(cur_pb_type->modes[mode_index].pb_type_children[ipb]), cur_sram_orgz_info); - } - } - } - - /* Check if this has defined a spice_model*/ - if ( TRUE == is_primitive_pb_type(cur_pb_type)) { - sum_num_conf_bits = count_num_conf_bits_one_spice_model(cur_pb_type->phy_pb_type->spice_model, cur_sram_orgz_info->type, 0); - cur_pb_type->physical_mode_num_conf_bits = sum_num_conf_bits; - /* calculate the number of reserved configuration bits */ - cur_pb_type->physical_mode_num_reserved_conf_bits = - count_num_reserved_conf_bits_one_spice_model(cur_pb_type->phy_pb_type->spice_model, - cur_sram_orgz_info->type, 0); - - } else { /* Count the sum of configuration bits of all the children pb_types */ - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Count in the number of configuration bits of on child pb_type */ - sum_num_conf_bits += cur_pb_type->modes[mode_index].pb_type_children[ipb].physical_mode_num_conf_bits; - temp_num_reserved_conf_bits = cur_pb_type->modes[mode_index].pb_type_children[ipb].physical_mode_num_reserved_conf_bits; - - /* number of reserved conf. bits is deteremined by the largest number of reserved conf. bits !*/ - if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { - num_reserved_conf_bits = temp_num_reserved_conf_bits; - } - } - } - /* Count the number of configuration bits of interconnection */ - sum_num_conf_bits += count_num_conf_bits_pb_type_mode_interc(&(cur_pb_type->modes[mode_index]), - cur_sram_orgz_info->type); - /* Count the number of reserved_configuration bits of interconnection */ - temp_num_reserved_conf_bits = - count_num_reserved_conf_bits_pb_type_mode_interc(&(cur_pb_type->modes[mode_index]), - cur_sram_orgz_info->type); - /* number of reserved conf. bits is deteremined by the largest number of reserved conf. bits !*/ - if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { - num_reserved_conf_bits = temp_num_reserved_conf_bits; - } - /* Update the info in pb_type */ - cur_pb_type->physical_mode_num_reserved_conf_bits = num_reserved_conf_bits; - cur_pb_type->physical_mode_num_conf_bits = sum_num_conf_bits; - } - - return sum_num_conf_bits; -} - - -/* Count the number of configuration bits of a pb_graph_node */ -int rec_count_num_conf_bits_pb(t_pb* cur_pb, - t_sram_orgz_info* cur_sram_orgz_info) { - int mode_index, ipb, jpb; - t_pb_type* cur_pb_type = NULL; - t_pb_graph_node* cur_pb_graph_node = NULL; - int sum_num_conf_bits = 0; - int num_reserved_conf_bits = 0; - int temp_num_reserved_conf_bits = 0; - - /* Check cur_pb_graph_node*/ - if (NULL == cur_pb) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb.\n", - __FILE__, __LINE__); - exit(1); - } - cur_pb_graph_node = cur_pb->pb_graph_node; - cur_pb_type = cur_pb_graph_node->pb_type; - mode_index = cur_pb->mode; - - cur_pb->num_conf_bits = 0; - - /* Recursively finish all the child pb_types*/ - if ((NULL == cur_pb_type->spice_model_name) - &&(NULL == cur_pb_type->physical_pb_type_name)) { - /* recursive for the child_pbs*/ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Recursive*/ - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - rec_count_num_conf_bits_pb(&(cur_pb->child_pbs[ipb][jpb]), cur_sram_orgz_info); - } else { - /* Check if this pb has no children, no children mean idle*/ - rec_count_num_conf_bits_pb_type_default_mode(cur_pb->child_pbs[ipb][jpb].pb_graph_node->pb_type, - cur_sram_orgz_info); - } - } - } - } - - /* Check if this has defined a spice_model*/ - if ((NULL != cur_pb_type->spice_model_name) - ||(NULL != cur_pb_type->physical_pb_type_name)) { - sum_num_conf_bits += count_num_conf_bits_one_spice_model(cur_pb_type->phy_pb_type->spice_model, - cur_sram_orgz_info->type, 0); - cur_pb->num_conf_bits = sum_num_conf_bits; - /* calculate the number of reserved configuration bits */ - cur_pb->num_reserved_conf_bits = - count_num_reserved_conf_bits_one_spice_model(cur_pb_type->phy_pb_type->spice_model, - cur_sram_orgz_info->type, 0); - - } else { - /* Definition ends*/ - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - /* Count in the number of configuration bits of on child pb */ - sum_num_conf_bits += cur_pb->child_pbs[ipb][jpb].num_conf_bits; - temp_num_reserved_conf_bits = cur_pb->child_pbs[ipb][jpb].num_reserved_conf_bits; - } else { - /* Count in the number of configuration bits of on child pb_type */ - sum_num_conf_bits += cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_conf_bits; - temp_num_reserved_conf_bits = - cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_reserved_conf_bits; - } - /* number of reserved conf. bits is deteremined by the largest number of reserved conf. bits !*/ - if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { - num_reserved_conf_bits = temp_num_reserved_conf_bits; - } - } - } - /* Count the number of configuration bits of interconnection */ - sum_num_conf_bits += count_num_conf_bits_pb_type_mode_interc(&(cur_pb_type->modes[mode_index]), - cur_sram_orgz_info->type); - /* Count the number of reserved_configuration bits of interconnection */ - temp_num_reserved_conf_bits = - count_num_reserved_conf_bits_pb_type_mode_interc(&(cur_pb_type->modes[mode_index]), - cur_sram_orgz_info->type); - /* number of reserved conf. bits is deteremined by the largest number of reserved conf. bits !*/ - if (temp_num_reserved_conf_bits > num_reserved_conf_bits) { - num_reserved_conf_bits = temp_num_reserved_conf_bits; - } - /* Update the info in pb_type */ - cur_pb->num_reserved_conf_bits = num_reserved_conf_bits; - cur_pb->num_conf_bits = sum_num_conf_bits; - } - - return sum_num_conf_bits; -} - -/* Initialize the number of configuraion bits for one grid */ -void init_one_grid_num_conf_bits(int ix, int iy, - t_sram_orgz_info* cur_sram_orgz_info) { - int iz; - int capacity; - - /* Check */ - assert((!(0 > ix))&&(!(ix > (nx + 1)))); - assert((!(0 > iy))&&(!(iy > (ny + 1)))); - - if ((NULL == grid[ix][iy].type) - ||(EMPTY_TYPE == grid[ix][iy].type) - ||(0 != grid[ix][iy].offset)) { - /* Empty grid, directly return */ - return; - } - capacity= grid[ix][iy].type->capacity; - assert(0 < capacity); - - /* check capacity and if this has been mapped */ - for (iz = 0; iz < capacity; iz++) { - /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ - rec_count_num_conf_bits_pb_type_physical_mode(grid[ix][iy].type->pb_type, cur_sram_orgz_info); - } - - return; -} - -/* Initialize the number of configuraion bits for all grids */ -void init_grids_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info) { - int ix, iy; - - /* Core grid */ - vpr_printf(TIO_MESSAGE_INFO, "INFO: Initializing number of configuration bits of Core grids...\n"); - for (ix = 1; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - init_one_grid_num_conf_bits(ix, iy, cur_sram_orgz_info); - } - } - - /* Consider the IO pads */ - vpr_printf(TIO_MESSAGE_INFO, "INFO: Initializing number of configuration bits of I/O grids...\n"); - /* Top side : x = 1 .. nx + 1, y = nx + 1 */ - iy = ny + 1; - for (ix = 1; ix < (nx + 1); ix++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - init_one_grid_num_conf_bits(ix, iy, cur_sram_orgz_info); - } - - /* Right side : x = nx + 1, y = 1 .. ny*/ - ix = nx + 1; - for (iy = 1; iy < (ny + 1); iy++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - init_one_grid_num_conf_bits(ix, iy, cur_sram_orgz_info); - } - - /* Bottom side : x = 1 .. nx + 1, y = 0 */ - iy = 0; - for (ix = 1; ix < (nx + 1); ix++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - init_one_grid_num_conf_bits(ix, iy, cur_sram_orgz_info); - } - - /* Left side: x = 0, y = 1 .. ny*/ - ix = 0; - for (iy = 1; iy < (ny + 1); iy++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - init_one_grid_num_conf_bits(ix, iy, cur_sram_orgz_info); - } - - return; -} - -/******************************************************************** - * Initialize the number of configuration bits for each pb_type - * in the list of type descriptors - *******************************************************************/ -void init_pb_types_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info) { - for (int itype = 0; itype < num_types; ++itype) { - /* bypass EMPTY_TYPES */ - if (EMPTY_TYPE == &(type_descriptors[itype])) { - continue; - } - int capacity= type_descriptors[itype].capacity; - assert(0 < capacity); - - /* check capacity and if this has been mapped */ - for (int iz = 0; iz < capacity; iz++) { - /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ - rec_count_num_conf_bits_pb_type_physical_mode(type_descriptors[itype].pb_type, cur_sram_orgz_info); - } - } - return; -} - -/* With given spice_model_port, find the pb_type port with same name and type*/ -t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, - t_spice_model_port* spice_model_port) { - int iport; - t_port* ret = NULL; - - /* Search ports */ - for (iport = 0; iport < pb_type->num_ports; iport++) { - /* Match the name and port size*/ - if ((0 == strcmp(pb_type->ports[iport].name, spice_model_port->prefix)) - &&(pb_type->ports[iport].num_pins == spice_model_port->size)) { - /* Match the type*/ - switch (spice_model_port->type) { - case SPICE_MODEL_PORT_INPUT: - if ((IN_PORT == pb_type->ports[iport].type) - &&(0 == pb_type->ports[iport].is_clock)) { - if (NULL != ret) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])More than 1 pb_type(%s) port match spice_model_port(%s)!\n", - __FILE__, __LINE__, pb_type->name, spice_model_port->prefix); - exit(1); - } - ret = &(pb_type->ports[iport]); - } - break; - case SPICE_MODEL_PORT_OUTPUT: - if (OUT_PORT == pb_type->ports[iport].type) { - if (NULL != ret) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])More than 1 pb_type(%s) port match spice_model_port(%s)!\n", - __FILE__, __LINE__, pb_type->name, spice_model_port->prefix); - exit(1); - } - ret = &(pb_type->ports[iport]); - } - break; - case SPICE_MODEL_PORT_CLOCK: - if ((IN_PORT == pb_type->ports[iport].type)&&(1 == pb_type->ports[iport].is_clock)) { - if (NULL != ret) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])More than 1 pb_type(%s) port match spice_model_port(%s)!\n", - __FILE__, __LINE__, pb_type->name, spice_model_port->prefix); - exit(1); - } - ret = &(pb_type->ports[iport]); - } - break; - case SPICE_MODEL_PORT_INOUT : - if ((INOUT_PORT == pb_type->ports[iport].type)&&(0 == pb_type->ports[iport].is_clock)) { - if (NULL != ret) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])More than 1 pb_type(%s) port match spice_model_port(%s)!\n", - __FILE__, __LINE__, pb_type->name, spice_model_port->prefix); - exit(1); - } - ret = &(pb_type->ports[iport]); - } - break; - case SPICE_MODEL_PORT_SRAM: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid type for spice_model_port(%s)!\n", - __FILE__, __LINE__, spice_model_port->prefix); - exit(1); - } - } - } - - return ret; -} - -/******************************************************************** - * Return a list of ports of a pb_type which matches the ports defined - * in its linked circuit model - * This function will only care if the port type matches - *******************************************************************/ -std::vector find_pb_type_ports_match_circuit_model_port_type(t_pb_type* pb_type, - enum e_spice_model_port_type port_type) { - std::vector ports; - - for (int iport = 0; iport < pb_type->num_ports; ++iport) { - /* Check the circuit_port id of the port ? */ - VTR_ASSERT(CircuitPortId::INVALID() != pb_type->ports[iport].circuit_model_port); - switch (port_type) { - case SPICE_MODEL_PORT_INPUT: - if ( (IN_PORT == pb_type->ports[iport].type) - && (0 == pb_type->ports[iport].is_clock) ) { - ports.push_back(&pb_type->ports[iport]); - } - break; - case SPICE_MODEL_PORT_OUTPUT: - if ( (OUT_PORT == pb_type->ports[iport].type) - && (0 == pb_type->ports[iport].is_clock) ) { - ports.push_back(&pb_type->ports[iport]); - } - break; - case SPICE_MODEL_PORT_INOUT: - if ( (INOUT_PORT == pb_type->ports[iport].type) - && (0 == pb_type->ports[iport].is_clock) ) { - ports.push_back(&pb_type->ports[iport]); - } - break; - case SPICE_MODEL_PORT_CLOCK: - if ( (IN_PORT == pb_type->ports[iport].type) - && (1 == pb_type->ports[iport].is_clock) ) { - ports.push_back(&pb_type->ports[iport]); - } - break; - /* Configuration ports are not in pb_type definition */ - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid type for port!\n", - __FILE__, __LINE__); - exit(1); - } - } - - return ports; -} - -t_port** find_pb_type_ports_match_spice_model_port_type(t_pb_type* pb_type, - enum e_spice_model_port_type port_type, - int* port_num) { - int iport, cur; - t_port** ret = NULL; - - /* Check codes*/ - assert(NULL != port_num); - assert(NULL != pb_type); - - /* Count the number of ports that match*/ - (*port_num) = 0; - for (iport = 0; iport < pb_type->num_ports; iport++) { - switch (port_type) { - case SPICE_MODEL_PORT_INPUT: /* TODO: support is_non_clock_global*/ - if ((IN_PORT == pb_type->ports[iport].type) - &&(0 == pb_type->ports[iport].is_clock)) { - (*port_num)++; - } - break; - case SPICE_MODEL_PORT_OUTPUT: - if ((OUT_PORT == pb_type->ports[iport].type) - &&(0 == pb_type->ports[iport].is_clock)) { - (*port_num)++; - } - break; - case SPICE_MODEL_PORT_INOUT: - if ((INOUT_PORT == pb_type->ports[iport].type) - &&(0 == pb_type->ports[iport].is_clock)) { - (*port_num)++; - } - break; - case SPICE_MODEL_PORT_CLOCK: - if ((IN_PORT == pb_type->ports[iport].type) - &&(1 == pb_type->ports[iport].is_clock)) { - (*port_num)++; - } - break; - case SPICE_MODEL_PORT_SRAM: - /* Original VPR don't support this*/ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid type for port!\n", - __FILE__, __LINE__); - exit(1); - } - } - - /* Initial the return pointers*/ - ret = (t_port**)my_malloc(sizeof(t_port*)*(*port_num)); - memset(ret, 0 , sizeof(t_port*)*(*port_num)); - - /* Fill the return pointers*/ - cur = 0; - - for (iport = 0; iport < pb_type->num_ports; iport++) { - switch (port_type) { - case SPICE_MODEL_PORT_INPUT : /* TODO: support is_non_clock_global*/ - if ((IN_PORT == pb_type->ports[iport].type) - &&(0 == pb_type->ports[iport].is_clock)) { - ret[cur] = &(pb_type->ports[iport]); - cur++; - } - break; - case SPICE_MODEL_PORT_OUTPUT: - if ((OUT_PORT == pb_type->ports[iport].type) - &&(0 == pb_type->ports[iport].is_clock)) { - ret[cur] = &(pb_type->ports[iport]); - cur++; - } - break; - case SPICE_MODEL_PORT_INOUT: - if ((INOUT_PORT == pb_type->ports[iport].type) - &&(0 == pb_type->ports[iport].is_clock)) { - ret[cur] = &(pb_type->ports[iport]); - cur++; - } - break; - case SPICE_MODEL_PORT_CLOCK: - if ((IN_PORT == pb_type->ports[iport].type) - &&(1 == pb_type->ports[iport].is_clock)) { - ret[cur] = &(pb_type->ports[iport]); - cur++; - } - break; - case SPICE_MODEL_PORT_SRAM: - /* Original VPR don't support this*/ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid type for port!\n", - __FILE__, __LINE__); - exit(1); - } - } - - /* Check correctness*/ - assert(cur == (*port_num)); - - return ret; -} - - -int find_path_id_between_pb_rr_nodes(t_rr_node* local_rr_graph, - int src_node, - int des_node) { - int path_id = -1; - int prev_edge = -1; - int path_count = 0; - int iedge; - t_interconnect* cur_interc = NULL; - - /* Check */ - assert(NULL != local_rr_graph); - assert((0 == src_node)||(0 < src_node)); - assert((0 == des_node)||(0 < des_node)); - - prev_edge = local_rr_graph[des_node].prev_edge; - check_pb_graph_edge(*(local_rr_graph[src_node].pb_graph_pin->output_edges[prev_edge])); - assert(local_rr_graph[src_node].pb_graph_pin->output_edges[prev_edge]->output_pins[0] == local_rr_graph[des_node].pb_graph_pin); - - cur_interc = local_rr_graph[src_node].pb_graph_pin->output_edges[prev_edge]->interconnect; - /* Search des_node input edges */ - for (iedge = 0; iedge < local_rr_graph[des_node].pb_graph_pin->num_input_edges; iedge++) { - if (local_rr_graph[des_node].pb_graph_pin->input_edges[iedge]->input_pins[0] - == local_rr_graph[src_node].pb_graph_pin) { - /* Strict check */ - assert(local_rr_graph[src_node].pb_graph_pin->output_edges[prev_edge] - == local_rr_graph[des_node].pb_graph_pin->input_edges[iedge]); - path_id = path_count; - break; - } - if (cur_interc == local_rr_graph[des_node].pb_graph_pin->input_edges[iedge]->interconnect) { - path_count++; - } - } - - return path_id; -} - -/* Find the interconnection type of pb_graph_pin edges*/ -enum e_interconnect find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin) { - enum e_interconnect interc_type; - int def_interc_type = 0; - int iedge; - - for (iedge = 0; iedge < pb_graph_pin.num_input_edges; iedge++) { - /* Make sure all edges are legal: 1 input_pin, 1 output_pin*/ - check_pb_graph_edge(*(pb_graph_pin.input_edges[iedge])); - /* Make sure all the edges interconnect type is the same*/ - if (0 == def_interc_type) { - interc_type = pb_graph_pin.input_edges[iedge]->interconnect->type; - } else if (interc_type != pb_graph_pin.input_edges[iedge]->interconnect->type) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d])Interconnection type are not same for port(%s),pin(%d).\n", - __FILE__, __LINE__, pb_graph_pin.port->name,pb_graph_pin.pin_number); - exit(1); - } - } - - return interc_type; -} - -/* Find the interconnection type of pb_graph_pin edges*/ -t_spice_model* find_pb_graph_pin_in_edges_interc_spice_model(t_pb_graph_pin pb_graph_pin) { - t_spice_model* interc_spice_model; - int def_interc_model = 0; - int iedge; - - for (iedge = 0; iedge < pb_graph_pin.num_input_edges; iedge++) { - /* Make sure all edges are legal: 1 input_pin, 1 output_pin*/ - check_pb_graph_edge(*(pb_graph_pin.input_edges[iedge])); - /* Make sure all the edges interconnect type is the same*/ - if (0 == def_interc_model) { - interc_spice_model= pb_graph_pin.input_edges[iedge]->interconnect->spice_model; - } else if (interc_spice_model != pb_graph_pin.input_edges[iedge]->interconnect->spice_model) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d])Interconnection spice_model are not same for port(%s),pin(%d).\n", - __FILE__, __LINE__, pb_graph_pin.port->name, pb_graph_pin.pin_number); - exit(1); - } - } - - return interc_spice_model; -} - -void find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode, - t_interconnect** cur_interc, - int* fan_in) { - int iedge; - - (*cur_interc) = NULL; - (*fan_in) = 0; - - /* Search the input edges only, stats on the size of MUX we may need (fan-in) */ - for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - /* 1. First, we should make sure this interconnect is in the selected mode!!!*/ - if (cur_mode == des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { - /* Check this edge*/ - check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); - /* Record the interconnection*/ - if (NULL == (*cur_interc)) { - (*cur_interc) = des_pb_graph_pin->input_edges[iedge]->interconnect; - } else { /* Make sure the interconnections for this pin is the same!*/ - assert((*cur_interc) == des_pb_graph_pin->input_edges[iedge]->interconnect); - } - /* Search the input_pins of input_edges only*/ - (*fan_in) += des_pb_graph_pin->input_edges[iedge]->num_input_pins; - } - } - - return; -} - -void find_interc_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin, - int cur_mode_index, - t_interconnect** cur_interc) { - int iedge; - - (*cur_interc) = NULL; - - /* Search the input edges only, stats on the size of MUX we may need (fan-in) */ - for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - /* 1. First, we should make sure this interconnect is in the selected mode!!!*/ - if (cur_mode_index == des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode_index) { - /* Check this edge*/ - check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); - /* Record the interconnection*/ - if (NULL == (*cur_interc)) { - (*cur_interc) = des_pb_graph_pin->input_edges[iedge]->interconnect; - } else { /* Make sure the interconnections for this pin is the same!*/ - assert((*cur_interc) == des_pb_graph_pin->input_edges[iedge]->interconnect); - } - } - } - - return; -} - - -/* Return a child_pb if it is mapped.*/ -t_pb* get_child_pb_for_phy_pb_graph_node(t_pb* cur_pb, int ipb, int jpb) { - t_pb* child_pb = NULL; - - /* TODO: more check ? */ - - if (NULL == cur_pb) { - return NULL; - } - - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - child_pb = &(cur_pb->child_pbs[ipb][jpb]); - } - - return child_pb; -} - -/* Return a child_phy_pb if it is mapped.*/ -t_phy_pb* get_phy_child_pb_for_phy_pb_graph_node(t_phy_pb* cur_phy_pb, - int ipb, int jpb) { - t_phy_pb* child_phy_pb = NULL; - - /* TODO: more check ? */ - - if (NULL == cur_phy_pb) { - return NULL; - } - - if ((NULL != cur_phy_pb->child_pbs[ipb])&&(NULL != cur_phy_pb->child_pbs[ipb][jpb].name)) { - child_phy_pb = &(cur_phy_pb->child_pbs[ipb][jpb]); - } - - return child_phy_pb; -} - - -/* Count the number of inpad and outpad of a grid (type_descriptor) in default mode */ -void rec_count_num_iopads_pb_type_physical_mode(t_pb_type* cur_pb_type) { - int mode_index, ipb, jpb; - int sum_num_iopads = 0; - - cur_pb_type->physical_mode_num_iopads = 0; - - /* Recursively finish all the child pb_types*/ - if (FALSE == is_primitive_pb_type(cur_pb_type)) { - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - rec_count_num_iopads_pb_type_physical_mode(&(cur_pb_type->modes[mode_index].pb_type_children[ipb])); - } - } - } - - /* Check if this has defined a spice_model*/ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - if (SPICE_MODEL_IOPAD == cur_pb_type->phy_pb_type->spice_model->type) { - sum_num_iopads = 1; - cur_pb_type->physical_mode_num_iopads = sum_num_iopads; - } - } else { /* Count the sum of configuration bits of all the children pb_types */ - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Count in the number of configuration bits of on child pb_type */ - sum_num_iopads += cur_pb_type->modes[mode_index].pb_type_children[ipb].physical_mode_num_iopads; - } - } - /* Count the number of configuration bits of interconnection */ - /* Update the info in pb_type */ - cur_pb_type->physical_mode_num_iopads = sum_num_iopads; - } - - return; -} - -/* Count the number of inpad and outpad of a grid (type_descriptor) in default mode */ -void rec_count_num_iopads_pb_type_default_mode(t_pb_type* cur_pb_type) { - int mode_index, ipb, jpb; - int sum_num_iopads = 0; - - cur_pb_type->default_mode_num_iopads = 0; - - /* Recursively finish all the child pb_types*/ - if ((NULL == cur_pb_type->spice_model_name) - && (NULL == cur_pb_type->physical_pb_type_name)) { - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - rec_count_num_iopads_pb_type_default_mode(&(cur_pb_type->modes[mode_index].pb_type_children[ipb])); - sum_num_iopads += cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_iopads; - cur_pb_type->default_mode_num_iopads = sum_num_iopads; - } - } - } - - /* Check if this has defined a spice_model*/ - if ((NULL != cur_pb_type->spice_model_name) - && (NULL != cur_pb_type->physical_pb_type_name)) { - if (SPICE_MODEL_IOPAD == cur_pb_type->phy_pb_type->spice_model->type) { - sum_num_iopads = 1; - cur_pb_type->default_mode_num_iopads = sum_num_iopads; - } - } - - return; -} - -/* Count the number of configuration bits of a pb_graph_node */ -void rec_count_num_iopads_pb(t_pb* cur_pb) { - int mode_index, ipb, jpb; - t_pb_type* cur_pb_type = NULL; - t_pb_graph_node* cur_pb_graph_node = NULL; - - int sum_num_iopads = 0; - - /* Check cur_pb_graph_node*/ - if (NULL == cur_pb) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb.\n", - __FILE__, __LINE__); - exit(1); - } - cur_pb_graph_node = cur_pb->pb_graph_node; - cur_pb_type = cur_pb_graph_node->pb_type; - mode_index = cur_pb->mode; - - cur_pb->num_iopads = 0; - - /* Recursively finish all the child pb_types*/ - if ((NULL == cur_pb_type->spice_model_name) - &&(NULL == cur_pb_type->physical_pb_type_name)) { - /* recursive for the child_pbs*/ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Recursive*/ - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - rec_count_num_iopads_pb(&(cur_pb->child_pbs[ipb][jpb])); - } else { - /* Check if this pb has no children, no children mean idle*/ - rec_count_num_iopads_pb_type_default_mode(cur_pb->child_pbs[ipb][jpb].pb_graph_node->pb_type); - } - } - } - } - - /* Check if this has defined a spice_model*/ - if ((NULL != cur_pb_type->spice_model) - ||(NULL != cur_pb_type->physical_pb_type_name)) { - if (SPICE_MODEL_IOPAD == cur_pb_type->phy_pb_type->spice_model->type) { - sum_num_iopads = 1; - cur_pb->num_iopads = sum_num_iopads; - } - } else { - /* Definition ends*/ - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - /* Count in the number of configuration bits of on child pb */ - sum_num_iopads += cur_pb->child_pbs[ipb][jpb].num_iopads; - } else { - /* Count in the number of configuration bits of on child pb_type */ - sum_num_iopads += cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_iopads; - } - } - } - /* Count the number of configuration bits of interconnection */ - /* Update the info in pb_type */ - cur_pb->num_iopads = sum_num_iopads; - } - - return; -} - -/* Initialize the number of configuraion bits for one grid */ -void init_one_grid_num_iopads(int ix, int iy) { - int iz; - int capacity; - - /* Check */ - assert((!(0 > ix))&&(!(ix > (nx + 1)))); - assert((!(0 > iy))&&(!(iy > (ny + 1)))); - - if ((NULL == grid[ix][iy].type) - ||(EMPTY_TYPE == grid[ix][iy].type) - ||(0 != grid[ix][iy].offset)) { - /* Empty grid, directly return */ - return; - } - capacity= grid[ix][iy].type->capacity; - assert(0 < capacity); - - /* check capacity and if this has been mapped */ - for (iz = 0; iz < capacity; iz++) { - /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ - rec_count_num_iopads_pb_type_physical_mode(grid[ix][iy].type->pb_type); - } - - return; -} - -/* Initialize the number of configuraion bits for all grids */ -void init_grids_num_iopads() { - int ix, iy; - - /* Core grid */ - vpr_printf(TIO_MESSAGE_INFO, "INFO: Initializing number of I/O pads in Core grids...\n"); - for (ix = 1; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - init_one_grid_num_iopads(ix, iy); - } - } - - /* Consider the IO pads */ - vpr_printf(TIO_MESSAGE_INFO, "INFO: Initializing number of I/O pads in I/O grids...\n"); - /* Top side : x = 1 .. nx + 1, y = nx + 1 */ - iy = ny + 1; - for (ix = 1; ix < (nx + 1); ix++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - init_one_grid_num_iopads(ix, iy); - } - /* Right side : x = nx + 1, y = 1 .. ny*/ - ix = nx + 1; - for (iy = 1; iy < (ny + 1); iy++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - init_one_grid_num_iopads(ix, iy); - } - /* Bottom side : x = 1 .. nx + 1, y = 0 */ - iy = 0; - for (ix = 1; ix < (nx + 1); ix++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - init_one_grid_num_iopads(ix, iy); - } - /* Left side: x = 0, y = 1 .. ny*/ - ix = 0; - for (iy = 1; iy < (ny + 1); iy++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - init_one_grid_num_iopads(ix, iy); - } - - return; -} - -/******************************************************************** - * Initialize the number of configuration bits for each pb_type - * in the list of type descriptors - *******************************************************************/ -void init_pb_types_num_iopads() { - for (int itype = 0; itype < num_types; ++itype) { - /* bypass EMPTY_TYPES */ - if (EMPTY_TYPE == &(type_descriptors[itype])) { - continue; - } - - int capacity= type_descriptors[itype].capacity; - assert(0 < capacity); - - /* check capacity and if this has been mapped */ - for (int iz = 0; iz < capacity; iz++) { - /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ - rec_count_num_iopads_pb_type_physical_mode(type_descriptors[itype].pb_type); - } - } - return; -} - -/* Count the number of mode configuration bits of a grid (type_descriptor) in default mode */ -void rec_count_num_mode_bits_pb_type_default_mode(t_pb_type* cur_pb_type) { - int mode_index, ipb, jpb; - int sum_num_mode_bits = 0; - - cur_pb_type->default_mode_num_mode_bits = 0; - - /* Recursively finish all the child pb_types*/ - if (NULL == cur_pb_type->spice_model) { - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - rec_count_num_mode_bits_pb_type_default_mode(&(cur_pb_type->modes[mode_index].pb_type_children[ipb])); - } - } - } - - /* Check if this has defined a spice_model*/ - if (NULL != cur_pb_type->spice_model) { - if (SPICE_MODEL_IOPAD == cur_pb_type->spice_model->type) { - sum_num_mode_bits = 1; - cur_pb_type->default_mode_num_mode_bits = sum_num_mode_bits; - } - } else { /* Count the sum of configuration bits of all the children pb_types */ - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Count in the number of configuration bits of on child pb_type */ - sum_num_mode_bits += cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_mode_bits; - } - } - /* Count the number of configuration bits of interconnection */ - /* Update the info in pb_type */ - cur_pb_type->default_mode_num_mode_bits = sum_num_mode_bits; - } - - return; -} - -/* Count the number of configuration bits of a pb_graph_node */ -void rec_count_num_mode_bits_pb(t_pb* cur_pb) { - int mode_index, ipb, jpb; - t_pb_type* cur_pb_type = NULL; - t_pb_graph_node* cur_pb_graph_node = NULL; - - int sum_num_mode_bits = 0; - - /* Check cur_pb_graph_node*/ - if (NULL == cur_pb) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb.\n", - __FILE__, __LINE__); - exit(1); - } - cur_pb_graph_node = cur_pb->pb_graph_node; - cur_pb_type = cur_pb_graph_node->pb_type; - mode_index = cur_pb->mode; - - cur_pb->num_mode_bits = 0; - - /* Recursively finish all the child pb_types*/ - if (NULL == cur_pb_type->spice_model) { - /* recursive for the child_pbs*/ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Recursive*/ - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - rec_count_num_mode_bits_pb(&(cur_pb->child_pbs[ipb][jpb])); - } else { - /* Check if this pb has no children, no children mean idle*/ - rec_count_num_mode_bits_pb_type_default_mode(cur_pb->child_pbs[ipb][jpb].pb_graph_node->pb_type); - } - } - } - } - - /* Check if this has defined a spice_model*/ - if (NULL != cur_pb_type->spice_model) { - if (SPICE_MODEL_IOPAD == cur_pb_type->spice_model->type) { - sum_num_mode_bits = 1; - cur_pb->num_mode_bits = sum_num_mode_bits; - } - } else { - /* Definition ends*/ - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - /* Count in the number of configuration bits of on child pb */ - sum_num_mode_bits += cur_pb->child_pbs[ipb][jpb].num_mode_bits; - } else { - /* Count in the number of configuration bits of on child pb_type */ - sum_num_mode_bits += cur_pb_type->modes[mode_index].pb_type_children[ipb].default_mode_num_mode_bits; - } - } - } - /* Count the number of configuration bits of interconnection */ - /* Update the info in pb_type */ - cur_pb->num_mode_bits = sum_num_mode_bits; - } - - return; -} - -/* Initialize the number of configuraion bits for one grid */ -void init_one_grid_num_mode_bits(int ix, int iy) { - t_block* mapped_block = NULL; - int iz; - int cur_block_index = 0; - int capacity; - - /* Check */ - assert((!(0 > ix))&&(!(ix > (nx + 1)))); - assert((!(0 > iy))&&(!(iy > (ny + 1)))); - - if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)) { - /* Empty grid, directly return */ - return; - } - capacity= grid[ix][iy].type->capacity; - assert(0 < capacity); - - /* check capacity and if this has been mapped */ - for (iz = 0; iz < capacity; iz++) { - /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ - mapped_block = search_mapped_block(ix, iy, iz); - /* Comments: Grid [x][y]*/ - if (NULL == mapped_block) { - /* Print a consider a idle pb_type ...*/ - rec_count_num_mode_bits_pb_type_default_mode(grid[ix][iy].type->pb_type); - } else { - if (iz == mapped_block->z) { - // assert(mapped_block == &(block[grid[ix][iy].blocks[cur_block_index]])); - cur_block_index++; - } - rec_count_num_mode_bits_pb(mapped_block->pb); - } - } - - assert(cur_block_index == grid[ix][iy].usage); - - return; -} - -/* Initialize the number of configuraion bits for all grids */ -void init_grids_num_mode_bits() { - int ix, iy; - - /* Core grid */ - vpr_printf(TIO_MESSAGE_INFO, "INFO: Initializing number of mode configuraiton bits of Core grids...\n"); - for (ix = 1; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - init_one_grid_num_mode_bits(ix, iy); - } - } - - /* Consider the IO pads */ - vpr_printf(TIO_MESSAGE_INFO, "INFO: Initializing number of mode configuration bits of I/O grids...\n"); - /* Left side: x = 0, y = 1 .. ny*/ - ix = 0; - for (iy = 1; iy < (ny + 1); iy++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - init_one_grid_num_mode_bits(ix, iy); - } - /* Right side : x = nx + 1, y = 1 .. ny*/ - ix = nx + 1; - for (iy = 1; iy < (ny + 1); iy++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - init_one_grid_num_mode_bits(ix, iy); - } - /* Bottom side : x = 1 .. nx + 1, y = 0 */ - iy = 0; - for (ix = 1; ix < (nx + 1); ix++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - init_one_grid_num_mode_bits(ix, iy); - } - /* Top side : x = 1 .. nx + 1, y = nx + 1 */ - iy = ny + 1; - for (ix = 1; ix < (nx + 1); ix++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - init_one_grid_num_mode_bits(ix, iy); - } - - return; -} - -/* Return the child_pb of a LUT pb - * Because the mapping information is stored in the child_pb!!! - */ -t_pb* get_lut_child_pb(t_pb* cur_lut_pb, - int mode_index) { - - assert(SPICE_MODEL_LUT == cur_lut_pb->pb_graph_node->pb_type->phy_pb_type->spice_model->type); - - assert(1 == cur_lut_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children); - - return (&(cur_lut_pb->child_pbs[0][0])); -} - -/* Return the child_pb of a LUT pb - * Because the mapping information is stored in the child_pb!!! - */ -t_phy_pb* get_lut_child_phy_pb(t_phy_pb* cur_lut_pb, - int mode_index) { - - assert(SPICE_MODEL_LUT == cur_lut_pb->pb_graph_node->pb_type->spice_model->type); - - assert(1 == cur_lut_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children); - assert(1 == cur_lut_pb->pb_graph_node->pb_type->num_pb); - - return (&(cur_lut_pb->child_pbs[0][0])); -} - - -/* Return the child_pb of a hardlogic pb - * Because the mapping information is stored in the child_pb!!! - */ -t_pb* get_hardlogic_child_pb(t_pb* cur_hardlogic_pb, - int mode_index) { - - assert(SPICE_MODEL_HARDLOGIC == cur_hardlogic_pb->pb_graph_node->pb_type->phy_pb_type->spice_model->type); - - assert(1 == cur_hardlogic_pb->pb_graph_node->pb_type->modes[mode_index].num_pb_type_children); - assert(1 == cur_hardlogic_pb->pb_graph_node->pb_type->num_pb); - - return (&(cur_hardlogic_pb->child_pbs[0][0])); -} - -/******************************************************************** - * Find the height of a pin in a grid definition - * TODO: this should be a method of a grid class!!! - *******************************************************************/ -size_t find_grid_pin_height(const std::vector>& grids, - const vtr::Point& grid_coordinate, - const size_t& pin_index) { - t_type_ptr grid_type = grids[grid_coordinate.x()][grid_coordinate.y()].type; - - /* Return if this is an empty type */ - if ( (NULL == grid_type) - || (EMPTY_TYPE == grid_type)) { - return size_t(-1); - } - - /* Check if the pin index is in the range */ - VTR_ASSERT(pin_index < size_t(grid_type->num_pins)); - - /* Find the pin_height */ - return grid_type->pin_height[pin_index]; -} - -int get_grid_pin_height(int grid_x, int grid_y, int pin_index) { - int pin_height; - t_type_ptr grid_type = NULL; - - /* Get type */ - grid_type = grid[grid_x][grid_y].type; - - /* Return if this is an empty type */ - if ((NULL == grid_type) - ||(EMPTY_TYPE == grid_type)) { - pin_height = 0; - return pin_height; - } - - /* Check if the pin index is in the range */ - assert ( ((0 == pin_index) || (0 < pin_index)) - &&(pin_index < grid_type->num_pins) ); - - /* Find the pin_height */ - pin_height = grid_type->pin_height[pin_index]; - - return pin_height; -} - -/******************************************************************** - * Find the side where a pin locates on a grid - * TODO: this should be a method of a grid class!!! - *******************************************************************/ -e_side find_grid_pin_side(const vtr::Point& device_size, - const std::vector>& grids, - const vtr::Point& grid_coordinate, - const size_t& pin_height, - const size_t& pin_index) { - t_type_ptr grid_type = grids[grid_coordinate.x()][grid_coordinate.y()].type; - - /* Return an invalid side value if this is an empty type */ - if ( (NULL == grid_type) - || (EMPTY_TYPE == grid_type)) { - return NUM_SIDES; - } - - /* Check if the pin index is in the range */ - VTR_ASSERT(pin_index < size_t(grid_type->num_pins)); - - std::vector pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; - /* It could happen that some grids locate on the border of the device, - * In these case, only one side is allowed for the pin - */ - /* TOP side of the device */ - if (grid_coordinate.y() == device_size.y() - 1) { - Side side_manager(TOP); - pin_sides.clear(); - pin_sides.push_back(side_manager.get_opposite()); - } - - /* RIGHT side of the device */ - if (grid_coordinate.x() == device_size.x() - 1) { - Side side_manager(RIGHT); - pin_sides.clear(); - pin_sides.push_back(side_manager.get_opposite()); - } - - /* BOTTOM side of the device */ - if (grid_coordinate.y() == 0) { - Side side_manager(BOTTOM); - pin_sides.clear(); - pin_sides.push_back(side_manager.get_opposite()); - } - - /* LEFT side of the device */ - if (grid_coordinate.x() == 0) { - Side side_manager(LEFT); - pin_sides.clear(); - pin_sides.push_back(side_manager.get_opposite()); - } - - std::vector found_pin_sides; - for (const e_side& pin_side : pin_sides) { - if (1 == grid_type->pinloc[pin_height][pin_side][pin_index]) { - found_pin_sides.push_back(pin_side); - } - } - - /* We should find only one side ! */ - VTR_ASSERT(1 == found_pin_sides.size()); - - return found_pin_sides[0]; -} - - -int get_grid_pin_side(int grid_x, int grid_y, int pin_index) { - int pin_height, side, pin_side; - t_type_ptr grid_type = NULL; - - /* Get type */ - grid_type = grid[grid_x][grid_y].type; - - /* Return if this is an empty type */ - if ((NULL == grid_type) - ||(EMPTY_TYPE == grid_type)) { - return -1; - } - - /* Check if the pin index is in the range */ - assert ( ((0 == pin_index) || (0 < pin_index)) - &&(pin_index < grid_type->num_pins) ); - - /* Find the pin_height */ - pin_height = get_grid_pin_height(grid_x, grid_y, pin_index); - - pin_side = -1; - for (side = 0; side < 4; side++) { - /* Bypass corner cases */ - /* Pin can only locate on BOTTOM side, when grid is on TOP border */ - if ((ny + 1 == grid_y)&&(BOTTOM != side)) { - continue; - } - /* Pin can only locate on LEFT side, when grid is on RIGHT border */ - if ((nx + 1 == grid_x)&&(LEFT != side)) { - continue; - } - /* Pin can only locate on the TOP side, when grid is on BOTTOM border */ - if ((0 == grid_y)&&(TOP != side)) { - continue; - } - /* Pin can only locate on the RIGHT side, when grid is on LEFT border */ - if ((0 == grid_x)&&(RIGHT != side)) { - continue; - } - if (1 == grid_type->pinloc[pin_height][side][pin_index]) { - if (-1 != pin_side) { - vpr_printf(TIO_MESSAGE_ERROR, "(%s, [LINE%d]) Duplicated pin(index:%d) on two sides: %s and %s of type (name=%s)!\n", - __FILE__, __LINE__, - pin_index, - convert_side_index_to_string(pin_side), - convert_side_index_to_string(side), - grid_type->name); - exit(1); - } - pin_side = side; - } - } - - return pin_side; -} - -/* Decode mode bits "01..." to a SRAM bits array */ -int* decode_mode_bits(char* mode_bits, int* num_sram_bits) { - int* sram_bits = NULL; - int i; - - assert(NULL != mode_bits); - (*num_sram_bits) = strlen(mode_bits); - - sram_bits = (int*)my_calloc((*num_sram_bits), sizeof(int)); - - for (i = 0; i < (*num_sram_bits); i++) { - switch(mode_bits[i]) { - case '1': - sram_bits[i] = 1; - break; - case '0': - sram_bits[i] = 0; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid mode_bits(%s)!\n", - __FILE__, __LINE__, mode_bits); - exit(1); - } - } - - return sram_bits; -} - -enum e_interconnect determine_actual_pb_interc_type(t_interconnect* def_interc, - int fan_in) { - enum e_interconnect actual_interc_type = DIRECT_INTERC; - - /* Check */ - assert ((NULL != def_interc) && (0 != fan_in)); - - /* Initialize the interconnection type that will be implemented in SPICE netlist*/ - switch (def_interc->type) { - case DIRECT_INTERC: - assert(1 == fan_in); - actual_interc_type = DIRECT_INTERC; - break; - case COMPLETE_INTERC: - if (1 == fan_in) { - actual_interc_type = DIRECT_INTERC; - } else { - assert((2 == fan_in)||(2 < fan_in)); - actual_interc_type = MUX_INTERC; - } - break; - case MUX_INTERC: - assert((2 == fan_in)||(2 < fan_in)); - actual_interc_type = MUX_INTERC; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", - __FILE__, __LINE__, def_interc->name, def_interc->line_num); - exit(1); - } - - return actual_interc_type; -} - - -/* Count the number of pins in a pb_graph node */ -int count_pin_number_one_port_pb_graph_node(int num_ports, int* num_pins) { - int total_pins = 0; - int iport; - - for (iport = 0; iport < num_ports; iport++) { - total_pins += num_pins[iport]; - } - - return total_pins; -} - -/* Count the number of pins in a pb_graph node */ -int count_pin_number_one_pb_graph_node(t_pb_graph_node* cur_pb_graph_node) { - int total_pins = 0; - - /* INPUT port */ - total_pins += count_pin_number_one_port_pb_graph_node(cur_pb_graph_node->num_input_ports, - cur_pb_graph_node->num_input_pins); - - /* OUTPUT port */ - total_pins += count_pin_number_one_port_pb_graph_node(cur_pb_graph_node->num_output_ports, - cur_pb_graph_node->num_output_pins); - - /* CLOCK port */ - total_pins += count_pin_number_one_port_pb_graph_node(cur_pb_graph_node->num_clock_ports, - cur_pb_graph_node->num_clock_pins); - - - return total_pins; -} - -/* find the number of pb_graph edges with a given physical mode index */ -int count_pb_graph_node_input_edge_in_phy_mode(t_pb_graph_pin* cur_pb_graph_pin, - int phy_mode_index) { - int cnt = 0; - int iedge; - - for (iedge = 0; iedge < cur_pb_graph_pin->num_input_edges; iedge++) { - if (phy_mode_index == cur_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode_index) { - cnt++; - } - } - return cnt; -} - -int count_pb_graph_node_output_edge_in_phy_mode(t_pb_graph_pin* cur_pb_graph_pin, - int phy_mode_index) { - int cnt = 0; - int iedge; - - for (iedge = 0; iedge < cur_pb_graph_pin->num_output_edges; iedge++) { - if (phy_mode_index == cur_pb_graph_pin->output_edges[iedge]->interconnect->parent_mode_index) { - cnt++; - } - } - return cnt; -} - -/* With a given name, find the pb_type by recursively traversing the pb_type_tree */ -t_pb_type* rec_get_pb_type_by_name(t_pb_type* cur_pb_type, - char* pb_type_name) { - int imode, ipb; - t_pb_type* ret_pb_type = NULL; - t_pb_type* found_pb_type = NULL; - - /* Check the name of this pb_type */ - if (0 == strcmp(cur_pb_type->name, pb_type_name)) { - ret_pb_type = cur_pb_type; - } - - /* return when we meet the primitive node */ - if ( (NULL != cur_pb_type->physical_pb_type_name) - || (NULL != cur_pb_type->spice_model_name)) { - return ret_pb_type; - } - - /* We cannot find what we want this level, go recursively */ - /* Check each mode*/ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - found_pb_type = rec_get_pb_type_by_name(&(cur_pb_type->modes[imode].pb_type_children[ipb]), pb_type_name); - if (NULL == found_pb_type) { /* See if we have found anything*/ - continue; - } - /* We find something, check if we have a overlap in naming */ - if (NULL != ret_pb_type) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Duplicated pb_type name(%s) is not allowed in pb_types!\n", - __FILE__, __LINE__, pb_type_name); - exit(1); - } else { /* We are free of naming conflict, assign the return value */ - ret_pb_type = found_pb_type; - } - } - } - - return ret_pb_type; -} - -/* Decode an annotation (a string): [:] */ -void decode_physical_mode_pin_annotation(int phy_pb_type_port_size, - char* phy_mode_pin, - char** port_name, - int* pin_msb, int* pin_lsb) { - int itoken; - int num_tokens = 0; - char** token = NULL; - - token = fpga_spice_strtok(phy_mode_pin, "[:]", &num_tokens); - - /* 1 == num_token */ - switch (num_tokens) { - case 1: - (*port_name) = my_strdup(phy_mode_pin); - (*pin_msb) = phy_pb_type_port_size - 1; - (*pin_lsb) = 0; - break; - case 2: - (*port_name) = my_strdup(token[0]); - (*pin_msb) = my_atoi(token[1]); - (*pin_lsb) = (*pin_msb); - break; - case 3: - (*port_name) = my_strdup(token[0]); - (*pin_msb) = my_atoi(token[1]); - (*pin_lsb) = my_atoi(token[2]); - /* Identify which is larger: pin_msb and pin_lsb */ - (*pin_msb) = ((*pin_msb) > (*pin_lsb)) ? (*pin_msb) : (*pin_lsb); - (*pin_msb) = ((*pin_msb) > (*pin_lsb)) ? (*pin_lsb) : (*pin_msb); - break; - default: - /* Error out! */ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid physical_mode_pin: %s!\n", - __FILE__, __LINE__, phy_mode_pin); - exit(1); - } - - /* Free tokens */ - for (itoken = 0; itoken < num_tokens; itoken++) { - my_free(token[itoken]); - } - my_free(token); - - return; -} - -/* Decode the physical_mode_pin definition in cur_pb_type_port - * Annotate it to the ports of phy_pb_type - */ -void annotate_physical_mode_pin_to_pb_type(t_port* cur_pb_type_port, - t_pb_type* phy_pb_type) { - int iport; - char* phy_port_name = NULL; - int msb, lsb; - int port_matched = 0; - - /* Check */ - assert ( TRUE == phy_pb_type->parent_mode->define_physical_mode ); - - /* Search phy_pb_port ports */ - for (iport = 0; iport < phy_pb_type->num_ports; iport++) { - /* Decode the physical_mode_pin */ - decode_physical_mode_pin_annotation(phy_pb_type->ports[iport].num_pins, - cur_pb_type_port->physical_mode_pin, - &phy_port_name, &msb, &lsb); - if (0 == strcmp(phy_port_name, phy_pb_type->ports[iport].name)) { - /* We got a match! Give the lsb, msb and create a link */ - cur_pb_type_port->phy_pb_type_port = &(phy_pb_type->ports[iport]); - cur_pb_type_port->phy_pb_type_port_msb = msb; - cur_pb_type_port->phy_pb_type_port_lsb = lsb; - port_matched++; - } - /* free */ - my_free(phy_port_name); - } - - /* Check if the port is unique */ - if (0 == port_matched) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Unable to match the port (%s) of %s in its physical pb_type %s!\n", - __FILE__, __LINE__, - cur_pb_type_port->name, cur_pb_type_port->parent_pb_type->name, - phy_pb_type->name); - exit(1); - } - if (1 < port_matched) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])More than 1 port is matched for the port (%s) of %s in its physical pb_type %s!\n", - __FILE__, __LINE__, - cur_pb_type_port->name, cur_pb_type_port->parent_pb_type->name, - phy_pb_type->name); - exit(1); - } - assert (1 == port_matched ); - - /* Check if the pin number match */ - assert(cur_pb_type_port->phy_pb_type_port->num_pins > - (cur_pb_type_port->phy_pb_type_port_msb - cur_pb_type_port->phy_pb_type_port_lsb)); - - return; -} - -/* Annotate the port-to-port definition from cur_pb_type to a physical pb_type */ -void annotate_pb_type_port_to_phy_pb_type(t_pb_type* cur_pb_type, - t_pb_type* phy_pb_type) { - int iport; - - /* Check */ - assert ( TRUE == phy_pb_type->parent_mode->define_physical_mode ); - assert ( NULL != cur_pb_type->phy_pb_type ); - - /* Check each port of cur_pb_type */ - for (iport = 0; iport < cur_pb_type->num_ports; iport++) { - annotate_physical_mode_pin_to_pb_type(&(cur_pb_type->ports[iport]), phy_pb_type); - } - - return; -} - -/* Find a pb_graph_node with a given pb_type_name in placement_index_in_top */ -t_pb_graph_node* rec_get_pb_graph_node_by_pb_type_and_placement_index_in_top_node(t_pb_graph_node* cur_pb_graph_node, - t_pb_type* target_pb_type, - int target_placement_index) { - int imode, ipb, jpb; - t_pb_graph_node* ret_pb_graph_node = NULL; - t_pb_graph_node* found_pb_graph_node = NULL; - t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; - - /* Check if pb_type matches and also the placement_index */ - if (( target_pb_type == cur_pb_graph_node->pb_type ) - &&( target_placement_index == cur_pb_graph_node->placement_index_in_top_node )) { - ret_pb_graph_node = cur_pb_graph_node; - } - - /* We cannot find what we want this level, go recursively */ - /* Check each mode*/ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[imode].pb_type_children[ipb].num_pb; jpb++) { - found_pb_graph_node = rec_get_pb_graph_node_by_pb_type_and_placement_index_in_top_node(&(cur_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), - target_pb_type, target_placement_index); - - if (NULL == found_pb_graph_node) { /* See if we have found anything*/ - continue; - } - /* We find something, check if we have a overlap in naming */ - if (NULL != ret_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Duplicated pb_graph_node name %s[%d] is not allowed in pb_graph_node!\n", - __FILE__, __LINE__, target_pb_type->name, target_placement_index); - exit(1); - } else { /* We are free of naming conflict, assign the return value */ - ret_pb_graph_node = found_pb_graph_node; - } - } - } - } - - return ret_pb_graph_node; -} - -/* Check if the pin_number of cur_pb_graph_pin matches the phycial pb_graph_pin */ -boolean check_pin_number_match_phy_pb_graph_pin(t_pb_graph_pin* cur_pb_graph_pin, - t_pb_graph_pin* phy_pb_graph_pin) { - boolean pin_number_match = FALSE; - - /* Consider the rotation of cur_pb_graph_pin in pin_number */ - if ( (cur_pb_graph_pin->port->phy_pb_type_port == phy_pb_graph_pin->port) - &&(cur_pb_graph_pin->pin_number - + cur_pb_graph_pin->port->phy_pb_type_port_lsb - + cur_pb_graph_pin->port->phy_mode_pin_rotate_offset_acc - == phy_pb_graph_pin->pin_number )) { - pin_number_match = TRUE; - } - return pin_number_match; -} - -/* Link a port in the pb_graph_node to its physical_pb_graph_node port */ -void link_one_pb_graph_node_pin_to_phy_pb_graph_pin(t_pb_graph_pin* cur_pb_graph_pin, - t_pb_graph_node* phy_pb_graph_node) { - t_pb_graph_pin* phy_pb_graph_pin = NULL; - int iport, ipin; - - /* Get the name match pin in the phy_graph_node */ - for (iport = 0; iport < phy_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < phy_pb_graph_node->num_input_pins[iport]; ipin++) { - if (FALSE == check_pin_number_match_phy_pb_graph_pin(cur_pb_graph_pin, &(phy_pb_graph_node->input_pins[iport][ipin]))) { - continue; - } - if (NULL == phy_pb_graph_pin) { - phy_pb_graph_pin = &(phy_pb_graph_node->input_pins[iport][ipin]); - } else { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) More than one matched pin number found for %s[%d] in %s!\n", - __FILE__, __LINE__, cur_pb_graph_pin->port->name, cur_pb_graph_pin->pin_number, phy_pb_graph_node->pb_type->name); - exit(1); - } - } - } - - for (iport = 0; iport < phy_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < phy_pb_graph_node->num_output_pins[iport]; ipin++) { - if (FALSE == check_pin_number_match_phy_pb_graph_pin(cur_pb_graph_pin, &(phy_pb_graph_node->output_pins[iport][ipin]))) { - continue; - } - if (NULL == phy_pb_graph_pin) { - phy_pb_graph_pin = &(phy_pb_graph_node->output_pins[iport][ipin]); - } else { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) More than one matched pin number found for %s[%d] in %s!\n", - __FILE__, __LINE__, cur_pb_graph_pin->port->name, cur_pb_graph_pin->pin_number, phy_pb_graph_node->pb_type->name); - exit(1); - } - - } - } - - for (iport = 0; iport < phy_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < phy_pb_graph_node->num_clock_pins[iport]; ipin++) { - if (FALSE == check_pin_number_match_phy_pb_graph_pin(cur_pb_graph_pin, &(phy_pb_graph_node->clock_pins[iport][ipin]))) { - continue; - } - if (NULL == phy_pb_graph_pin) { - phy_pb_graph_pin = &(phy_pb_graph_node->clock_pins[iport][ipin]); - } else { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) More than one matched pin number found for %s[%d] in %s!\n", - __FILE__, __LINE__, cur_pb_graph_pin->port->name, cur_pb_graph_pin->pin_number, phy_pb_graph_node->pb_type->name); - exit(1); - } - - } - } - - /* We should find one! */ - if (NULL == phy_pb_graph_pin) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) No matched pin number found for %s[%d] in %s!\n", - __FILE__, __LINE__, - cur_pb_graph_pin->port->name, - cur_pb_graph_pin->pin_number, - phy_pb_graph_node->pb_type->name); - exit(1); - } - /* Create the link */ - cur_pb_graph_pin->physical_pb_graph_pin = phy_pb_graph_pin; - /* - vpr_printf (TIO_MESSAGE_INFO, " match pin (%s[%d]->%s[%d]) to (%s[%d]->%s[%d]) rotate_offset_acc=%d\n", - cur_pb_graph_pin->parent_node->pb_type->name, - cur_pb_graph_pin->parent_node->placement_index, - cur_pb_graph_pin->port->name, cur_pb_graph_pin->pin_number, - phy_pb_graph_pin->parent_node->pb_type->name, - phy_pb_graph_pin->parent_node->placement_index, - phy_pb_graph_pin->port->name, phy_pb_graph_pin->pin_number, - cur_pb_graph_pin->port->phy_mode_pin_rotate_offset_acc - ); - */ - /* Accumulate the phy_mode_pin offset when we have a matched */ - if (0 != cur_pb_graph_pin->port->physical_mode_pin_rotate_offset) { - cur_pb_graph_pin->port->phy_mode_pin_rotate_offset_acc += cur_pb_graph_pin->port->physical_mode_pin_rotate_offset; - } - /* Reset to lsb when we exceed the msb */ - /* TODO: this line should be thorougly checked, to avoid any bug */ - if (cur_pb_graph_pin->port->phy_pb_type_port_msb < - cur_pb_graph_pin->pin_number + cur_pb_graph_pin->port->phy_pb_type_port_lsb - + cur_pb_graph_pin->port->phy_mode_pin_rotate_offset_acc) { - cur_pb_graph_pin->port->phy_mode_pin_rotate_offset_acc = 0; - } - - return; -} - -/* Link the pb_graph_pins of a pb_graph_node to its physical pb_graph_node by the annotation in pb_type ports - * pb_graph_node A contains the annotation, while pb_graph_node B is the physical_pb_graph_node */ -void link_pb_graph_node_pins_to_phy_pb_graph_pins(t_pb_graph_node* cur_pb_graph_node, - t_pb_graph_node* phy_pb_graph_node) { - int iport, ipin; - - /* Search each port of cur_pb_graph_node and - * check matched port name in phy_pb_graph_node - */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - link_one_pb_graph_node_pin_to_phy_pb_graph_pin(&(cur_pb_graph_node->input_pins[iport][ipin]), - phy_pb_graph_node); - } - } - - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - link_one_pb_graph_node_pin_to_phy_pb_graph_pin(&(cur_pb_graph_node->output_pins[iport][ipin]), - phy_pb_graph_node); - } - } - - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - link_one_pb_graph_node_pin_to_phy_pb_graph_pin(&(cur_pb_graph_node->clock_pins[iport][ipin]), - phy_pb_graph_node); - } - } - - return; -} - -void rec_reset_pb_graph_node_rr_node_index_physical_pb(t_pb_graph_node* cur_pb_graph_node) { - int imode, iport, ipin, ipb, jpb; - t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; - - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - cur_pb_graph_node->input_pins[iport][ipin].rr_node_index_physical_pb = OPEN; - } - } - - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - cur_pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb = OPEN; - } - } - - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - cur_pb_graph_node->clock_pins[iport][ipin].rr_node_index_physical_pb = OPEN; - } - } - - /* END until primitive node */ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - return; - } - - /* We cannot find what we want this level, go recursively */ - /* Check each mode*/ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[imode].pb_type_children[ipb].num_pb; jpb++) { - rec_reset_pb_graph_node_rr_node_index_physical_pb(&(cur_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb])); - } - } - } - - return; -} - -/* Allocate empty child_phy_pbs according to a pb_graph_node */ -void rec_alloc_phy_pb_children(t_pb_graph_node* cur_pb_graph_node, - t_phy_pb* cur_phy_pb) { - int ipb, jpb; - int phy_mode_index; - t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; - char* phy_pb_name = NULL; - - phy_pb_name = (char*) my_malloc(sizeof(char) * (strlen(cur_pb_graph_node->pb_type->name) - + 1 + strlen(my_itoa(cur_pb_graph_node->placement_index_in_top_node)) - + 2)); - sprintf(phy_pb_name, "%s[%d]", - cur_pb_graph_node->pb_type->name, cur_pb_graph_node->placement_index_in_top_node); - - /* Initialize */ - cur_phy_pb->pb_graph_node = cur_pb_graph_node; - cur_phy_pb->name = phy_pb_name; - cur_phy_pb->num_logical_blocks = 0; - cur_phy_pb->logical_block = NULL; - cur_phy_pb->lut_size = NULL; - cur_phy_pb->lut_pin_remap = NULL; - cur_phy_pb->mode_bits = my_strdup(cur_pb_type->mode_bits); /* copy the default mode_bits */ - - /* Return if we reach the primitive node */ - if (NULL != cur_pb_type->spice_model) { - return; - } - - /* Assign the mode */ - phy_mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); - cur_phy_pb->mode = phy_mode_index; - /* Contine recursively */ - /* Allocate */ - cur_phy_pb->child_pbs = (t_phy_pb**) my_calloc(cur_pb_type->modes[phy_mode_index].num_pb_type_children, sizeof(t_phy_pb*)); - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[phy_mode_index].num_pb_type_children; ipb++) { - /* Allocate */ - cur_phy_pb->child_pbs[ipb] = (t_phy_pb*) my_calloc(cur_pb_type->modes[phy_mode_index].pb_type_children[ipb].num_pb, sizeof(t_phy_pb)); - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[phy_mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Assign parent_pb */ - cur_phy_pb->child_pbs[ipb][jpb].parent_pb = cur_phy_pb; - cur_phy_pb->child_pbs[ipb][jpb].rr_graph = cur_phy_pb->rr_graph; - /* Contine recursively */ - rec_alloc_phy_pb_children(&(cur_pb_graph_node->child_pb_graph_nodes[phy_mode_index][ipb][jpb]), - &(cur_phy_pb->child_pbs[ipb][jpb])); - } - } - - return; -} - -/* With a given name, find the pb_type by recursively traversing the pb_type_tree */ -t_phy_pb* rec_get_phy_pb_by_name(t_phy_pb* cur_phy_pb, - char* phy_pb_name) { - int ipb, jpb; - t_phy_pb* ret_phy_pb = NULL; - t_phy_pb* found_phy_pb = NULL; - - /* Check the name of this pb_type */ - if (0 == strcmp(cur_phy_pb->name, phy_pb_name)) { - ret_phy_pb = cur_phy_pb; - } - - /* return when we meet the primitive node */ - if (NULL != cur_phy_pb->pb_graph_node->pb_type->spice_model) { - return ret_phy_pb; - } - - for (ipb = 0; ipb < cur_phy_pb->pb_graph_node->pb_type->modes[cur_phy_pb->mode].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_phy_pb->pb_graph_node->pb_type->modes[cur_phy_pb->mode].pb_type_children[ipb].num_pb; jpb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - found_phy_pb = rec_get_phy_pb_by_name(&(cur_phy_pb->child_pbs[ipb][jpb]), phy_pb_name); - if (NULL == found_phy_pb) { /* See if we have found anything*/ - continue; - } - /* We find something, check if we have a overlap in naming */ - if (NULL != ret_phy_pb) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Duplicated phy_pb name(%s) is not allowed in phy_pb!\n", - __FILE__, __LINE__, phy_pb_name); - exit(1); - } else { /* We are free of naming conflict, assign the return value */ - ret_phy_pb = found_phy_pb; - } - } - } - - return ret_phy_pb; -} - -int get_pb_graph_node_wired_lut_logical_block_index(t_pb_graph_node* cur_pb_graph_node, - t_rr_node* op_pb_rr_graph) { - int iport, ipin; - int wired_lut_lb_index = OPEN; - int num_used_lut_input_pins = 0; - int num_used_lut_output_pins = 0; - int temp_rr_node_index; - int lut_output_vpack_net_num = OPEN; - - num_used_lut_input_pins = 0; - /* Find the used input pin of this LUT and rr_node in the graph */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - temp_rr_node_index = cur_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; - if (OPEN != op_pb_rr_graph[temp_rr_node_index].vpack_net_num) { - num_used_lut_input_pins++; - lut_output_vpack_net_num = op_pb_rr_graph[temp_rr_node_index].vpack_net_num; - } - } - } - /* Make sure we only have 1 used input pin */ - assert ((1 == num_used_lut_input_pins) - && (OPEN != lut_output_vpack_net_num)); - vpr_printf(TIO_MESSAGE_INFO, "Wired LUT output vpack_net_num is %d\n", lut_output_vpack_net_num); - - /* Find the used output*/ - num_used_lut_output_pins = 0; - /* Find the used output pin of this LUT and rr_node in the graph */ - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - temp_rr_node_index = cur_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster; - if (lut_output_vpack_net_num == op_pb_rr_graph[temp_rr_node_index].vpack_net_num) { /* TODO: Shit... I do not why the vpack_net_num is not synchronized to the net_num !!! */ - num_used_lut_output_pins++; - } - } - } - /* Make sure we only have 1 used output pin */ - vpr_printf(TIO_MESSAGE_INFO, "Wired LUT num_used_lut_output_pins is %d\n", num_used_lut_output_pins); - assert (1 == num_used_lut_output_pins); - - /* The logical block is the driver for this vpack_net( node_block[0] )*/ - wired_lut_lb_index = vpack_net[lut_output_vpack_net_num].node_block[0]; - assert (OPEN != wired_lut_lb_index); - - return wired_lut_lb_index; -} - -static -void rec_sync_wired_lut_to_one_phy_pb(t_pb_graph_node* cur_pb_graph_node, - t_phy_pb* cur_phy_pb, - t_rr_node* op_pb_rr_graph) { - int imode, ipb, jpb; - t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; - char* phy_pb_name = NULL; - t_phy_pb* phy_pb_to_sync = NULL; - - - /* Copy LUT information if this is a leaf node */ - if ((TRUE == is_primitive_pb_type(cur_pb_type)) - && (LUT_CLASS == cur_pb_type->class_type)) { - /* Check */ - assert(NULL != cur_pb_type->phy_pb_type); - assert(NULL != cur_pb_graph_node->physical_pb_graph_node); - /* Generate the name */ - phy_pb_name = (char*) my_malloc(sizeof(char) * (strlen(cur_pb_type->phy_pb_type->name) - + 1 + strlen(my_itoa(cur_pb_graph_node->physical_pb_graph_node->placement_index_in_top_node)) - + 2)); - sprintf(phy_pb_name, "%s[%d]", - cur_pb_type->phy_pb_type->name, cur_pb_graph_node->physical_pb_graph_node->placement_index_in_top_node); - /* find the child_pb in the current physical pb (cur_phy_pb) */ - phy_pb_to_sync = rec_get_phy_pb_by_name(cur_phy_pb, phy_pb_name); - - /* Copy the mode bits */ - if (NULL != phy_pb_to_sync->mode_bits) { /* Free the default mode bits if we have any */ - my_free(phy_pb_to_sync->mode_bits); - } - phy_pb_to_sync->mode_bits = my_strdup(cur_pb_type->mode_bits); - /* Re-allocate logical_block array mapped to this pb */ - phy_pb_to_sync->num_logical_blocks++; - phy_pb_to_sync->logical_block = (int*) my_realloc(phy_pb_to_sync->logical_block, sizeof(int) * phy_pb_to_sync->num_logical_blocks); - phy_pb_to_sync->is_wired_lut = (boolean*) my_realloc(phy_pb_to_sync->is_wired_lut, sizeof(boolean) * phy_pb_to_sync->num_logical_blocks); - phy_pb_to_sync->lut_size = (int*) my_realloc(phy_pb_to_sync->lut_size, sizeof(int) * phy_pb_to_sync->num_logical_blocks); - phy_pb_to_sync->lut_output_pb_graph_pin = (t_pb_graph_pin**) my_realloc(phy_pb_to_sync->lut_output_pb_graph_pin, sizeof(t_pb_graph_pin*) * phy_pb_to_sync->num_logical_blocks); - - /* Synchronize the logic block information */ - assert (LUT_CLASS == cur_pb_type->class_type); - /* check */ - assert (LUT_CLASS == cur_pb_type->phy_pb_type->class_type); - assert ( 1 == cur_pb_graph_node->num_input_ports ); - /* TODO: find the wired LUT logical block! */ - phy_pb_to_sync->logical_block[phy_pb_to_sync->num_logical_blocks - 1] = get_pb_graph_node_wired_lut_logical_block_index(cur_pb_graph_node, op_pb_rr_graph); - phy_pb_to_sync->is_wired_lut[phy_pb_to_sync->num_logical_blocks - 1] = TRUE; - /* Update the actual input size of this LUT */ - phy_pb_to_sync->lut_size[phy_pb_to_sync->num_logical_blocks - 1] = cur_pb_graph_node->num_input_pins[0]; - - /* Find the physical pb_graph_pin that this output is mapped to. - * ease LUT truth table decoding - */ - assert (1 == cur_pb_graph_node->num_output_ports); - assert (1 == cur_pb_graph_node->num_output_pins[0]); - phy_pb_to_sync->lut_output_pb_graph_pin[phy_pb_to_sync->num_logical_blocks - 1] = cur_pb_graph_node->output_pins[0][0].physical_pb_graph_pin; - - /* Finish here */ - return; - } - - /* Go recursively */ - assert (FALSE == is_primitive_pb_type(cur_pb_type)); - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[imode].pb_type_children[ipb].num_pb; jpb++) { - /* We care only those have been used for wiring */ - if (FALSE == is_pb_used_for_wiring(&(cur_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), - &(cur_pb_type->modes[imode].pb_type_children[ipb]), - op_pb_rr_graph)) { - continue; - } - rec_sync_wired_lut_to_one_phy_pb(&(cur_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), - cur_phy_pb, - op_pb_rr_graph); - } - } - } - - return; -} - -/* Synchronize the mapped information from operating pb cur_pb to phy_pb */ -void rec_sync_op_pb_mapping_to_phy_pb_children(t_pb* cur_op_pb, - t_phy_pb* cur_phy_pb) { - int ipb, jpb; - t_pb_graph_node* cur_pb_graph_node = cur_op_pb->pb_graph_node; - t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; - int mode_index = cur_op_pb->mode; - t_pb* child_pb = NULL; - char* phy_pb_name = NULL; - t_phy_pb* phy_pb_to_sync = NULL; - - /* Return if we reach the primitive node */ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - /* Check */ - assert(NULL != cur_pb_type->phy_pb_type); - assert(NULL != cur_pb_graph_node->physical_pb_graph_node); - /* Generate the name */ - phy_pb_name = (char*) my_malloc(sizeof(char) * (strlen(cur_pb_type->phy_pb_type->name) - + 1 + strlen(my_itoa(cur_pb_graph_node->physical_pb_graph_node->placement_index_in_top_node)) - + 2)); - sprintf(phy_pb_name, "%s[%d]", - cur_pb_type->phy_pb_type->name, cur_pb_graph_node->physical_pb_graph_node->placement_index_in_top_node); - /* find the child_pb in the current physical pb (cur_phy_pb) */ - phy_pb_to_sync = rec_get_phy_pb_by_name(cur_phy_pb, phy_pb_name); - /* Check */ - /* Copy the mode bits */ - if (NULL != phy_pb_to_sync->mode_bits) { /* Free the default mode bits if we have any */ - my_free(phy_pb_to_sync->mode_bits); - } - phy_pb_to_sync->mode_bits = my_strdup(cur_pb_type->mode_bits); - /* Re-allocate logical_block array mapped to this pb */ - phy_pb_to_sync->num_logical_blocks++; - phy_pb_to_sync->logical_block = (int*) my_realloc(phy_pb_to_sync->logical_block, sizeof(int) * phy_pb_to_sync->num_logical_blocks); - phy_pb_to_sync->is_wired_lut = (boolean*) my_realloc(phy_pb_to_sync->is_wired_lut, sizeof(boolean) * phy_pb_to_sync->num_logical_blocks); - phy_pb_to_sync->lut_size = (int*) my_realloc(phy_pb_to_sync->lut_size, sizeof(int) * phy_pb_to_sync->num_logical_blocks); - phy_pb_to_sync->lut_output_pb_graph_pin = (t_pb_graph_pin**) my_realloc(phy_pb_to_sync->lut_output_pb_graph_pin, sizeof(t_pb_graph_pin*) * phy_pb_to_sync->num_logical_blocks); - /* Synchronize the logic block information */ - switch (cur_pb_type->class_type) { - case LUT_CLASS: - /* Give phy_pb_type a LUT CLASS */ - child_pb = get_lut_child_pb(cur_op_pb, mode_index); - /* check */ - assert (LUT_CLASS == cur_pb_type->phy_pb_type->class_type); - assert (VPACK_COMB == logical_block[child_pb->logical_block].type); - assert ( 1 == cur_pb_graph_node->num_input_ports ); - /* Find the physical pb_graph_pin that this output is mapped to. - * ease LUT truth table decoding - */ - assert (1 == cur_pb_graph_node->num_output_ports); - assert (1 == cur_pb_graph_node->num_output_pins[0]); - phy_pb_to_sync->lut_output_pb_graph_pin[phy_pb_to_sync->num_logical_blocks - 1] = cur_pb_graph_node->output_pins[0][0].physical_pb_graph_pin; - /* Branch on the operating mode of this LUT - * Mode 0 means this LUT is in wired mode while Mode 1 implies this is a regular LUT - */ - if (WIRED_LUT_MODE_INDEX == mode_index) { - phy_pb_to_sync->logical_block[phy_pb_to_sync->num_logical_blocks - 1] = child_pb->logical_block; - phy_pb_to_sync->is_wired_lut[phy_pb_to_sync->num_logical_blocks - 1] = TRUE; - } else { - assert (NORMAL_LUT_MODE_INDEX == mode_index); - phy_pb_to_sync->logical_block[phy_pb_to_sync->num_logical_blocks - 1] = child_pb->logical_block; - phy_pb_to_sync->is_wired_lut[phy_pb_to_sync->num_logical_blocks - 1] = FALSE; - /* Give the number of LUT inputs of operating pb_graph_node */ - if (OPEN == child_pb->logical_block) { - phy_pb_to_sync->num_logical_blocks--; - } - } - /* Update the actual input size of this LUT */ - phy_pb_to_sync->lut_size[phy_pb_to_sync->num_logical_blocks - 1] = cur_pb_graph_node->num_input_pins[0]; - break; - case LATCH_CLASS: - /* Comment this as FF maybe a black box*/ - /* assert (VPACK_LATCH == logical_block[cur_op_pb->logical_block].type); */ - phy_pb_to_sync->logical_block[phy_pb_to_sync->num_logical_blocks - 1] = cur_op_pb->logical_block; - if (OPEN == cur_op_pb->logical_block) { - phy_pb_to_sync->num_logical_blocks--; - } - break; - case MEMORY_CLASS: - /* TODO: some memory pb has OPEN logical block .... Find out why - * To be safe, we identify if the logical block index is valid here - */ - child_pb = get_hardlogic_child_pb(cur_op_pb, mode_index); - phy_pb_to_sync->logical_block[phy_pb_to_sync->num_logical_blocks - 1] = child_pb->logical_block; - if (OPEN == child_pb->logical_block) { - phy_pb_to_sync->num_logical_blocks--; - } - break; - case UNKNOWN_CLASS: - /* Could be adder/hetergenous block/IOs - assert ((VPACK_INPAD == logical_block[cur_op_pb->logical_block].type) - ||(VPACK_OUTPAD == logical_block[cur_op_pb->logical_block].type)); - */ - phy_pb_to_sync->logical_block[phy_pb_to_sync->num_logical_blocks - 1] = cur_op_pb->logical_block; - if (OPEN == cur_op_pb->logical_block) { - phy_pb_to_sync->num_logical_blocks--; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n", - __FILE__, __LINE__, cur_pb_type->name); - exit(1); - } - - /* Free */ - my_free(phy_pb_name); - return; - } - - /* Recursive*/ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != cur_op_pb->child_pbs[ipb])&&(NULL != cur_op_pb->child_pbs[ipb][jpb].name)) { - rec_sync_op_pb_mapping_to_phy_pb_children(&(cur_op_pb->child_pbs[ipb][jpb]), cur_phy_pb); - } else if (TRUE == is_pb_used_for_wiring(&(cur_op_pb->pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), - &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), - cur_op_pb->rr_graph)) { - /* We need to extend this part: - * Some open op_pb contains wired LUTs - * We need go further into the hierarchy and find out the wired LUTs - */ - rec_sync_wired_lut_to_one_phy_pb(&(cur_op_pb->pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), - cur_phy_pb, - cur_op_pb->rr_graph); - } - } - } - - return; -} - - -/* Allocate pb children for a physical pb, according to the results in cur_pb*/ -void alloc_and_load_phy_pb_children_for_one_mapped_block(t_pb* cur_op_pb, - t_phy_pb* cur_phy_pb) { - - /* allocate empty child pbs according to pb_graph_node */ - rec_alloc_phy_pb_children(cur_phy_pb->pb_graph_node, cur_phy_pb); - - /* Synchronize the cur_pb to cur_phy_pb */ - rec_sync_op_pb_mapping_to_phy_pb_children(cur_op_pb, cur_phy_pb); - - return; -} - -/* Get the vpack_net_num of all the input pins of a LUT physical pb */ -void get_mapped_lut_phy_pb_input_pin_vpack_net_num(t_phy_pb* lut_phy_pb, - int* num_lut_pin, int** lut_pin_net) { - - int ipin, inode; - - /* Check */ - assert (1 == lut_phy_pb->pb_graph_node->num_input_ports); - (*num_lut_pin) = lut_phy_pb->pb_graph_node->num_input_pins[0]; - - /* Allocate */ - (*lut_pin_net) = (int*) my_malloc ((*num_lut_pin) * sizeof(int)); - /* Fill the array */ - for (ipin = 0; ipin < (*num_lut_pin); ipin++) { - inode = lut_phy_pb->pb_graph_node->input_pins[0][ipin].rr_node_index_physical_pb; - (*lut_pin_net)[ipin] = lut_phy_pb->rr_graph->rr_node[inode].vpack_net_num; - } - - return; -} - -/******************************************************************** - * Find the vpack_net_num of all the input pins of a LUT physical pb - *******************************************************************/ -std::vector find_mapped_lut_phy_pb_input_pin_vpack_net_num(t_phy_pb* lut_phy_pb) { - std::vector lut_pin_net; - - /* Check */ - VTR_ASSERT (1 == lut_phy_pb->pb_graph_node->num_input_ports); - lut_pin_net.resize(lut_phy_pb->pb_graph_node->num_input_pins[0]); - - /* Fill the array */ - for (size_t ipin = 0; ipin < lut_pin_net.size(); ++ipin) { - int inode = lut_phy_pb->pb_graph_node->input_pins[0][ipin].rr_node_index_physical_pb; - lut_pin_net[ipin] = lut_phy_pb->rr_graph->rr_node[inode].vpack_net_num; - } - - return lut_pin_net; -} - -/* Get the vpack_net_num of all the input pins of a LUT physical pb */ -void get_mapped_lut_pb_input_pin_vpack_net_num(t_pb* lut_pb, - int* num_lut_pin, int** lut_pin_net) { - int ipin, inode; - - /* Check */ - assert (1 == lut_pb->pb_graph_node->num_input_ports); - (*num_lut_pin) = lut_pb->pb_graph_node->num_input_pins[0]; - - /* Allocate */ - (*lut_pin_net) = (int*) my_malloc ((*num_lut_pin) * sizeof(int)); - /* Fill the array */ - for (ipin = 0; ipin < (*num_lut_pin); ipin++) { - inode = lut_pb->pb_graph_node->input_pins[0][ipin].rr_node_index_physical_pb; - (*lut_pin_net)[ipin] = lut_pb->rr_graph[inode].vpack_net_num; - } - - return; -} - - -/******************************************************************** - * Get the vpack_net_num of all the input pins of a LUT physical pb - *******************************************************************/ -std::vector find_lut_logical_block_input_pin_vpack_net_num(t_logical_block* lut_logical_block) { - /* Ensure there is only one pin in the LUT logical block */ - VTR_ASSERT (NULL == lut_logical_block->model->inputs[0].next); - - std::vector lut_pin_nets(lut_logical_block->model->inputs[0].size); - - /* Fill the array */ - for (size_t ipin = 0; ipin < lut_pin_nets.size(); ++ipin) { - lut_pin_nets[ipin] = lut_logical_block->input_nets[0][ipin]; - } - - return lut_pin_nets; -} - - -/* Get the vpack_net_num of all the input pins of a LUT physical pb */ -void get_lut_logical_block_input_pin_vpack_net_num(t_logical_block* lut_logical_block, - int* num_lut_pin, int** lut_pin_net) { - int ipin; - - /* Check */ - assert (NULL == lut_logical_block->model->inputs[0].next); - (*num_lut_pin) = lut_logical_block->model->inputs[0].size; - - /* Allocate */ - (*lut_pin_net) = (int*) my_malloc ((*num_lut_pin) * sizeof(int)); - /* Fill the array */ - for (ipin = 0; ipin < (*num_lut_pin); ipin++) { - (*lut_pin_net)[ipin] = lut_logical_block->input_nets[0][ipin]; - } - - return; -} - -/* Reset the temp_placement_index in pb_type to be 0 */ -void rec_reset_pb_type_temp_placement_index(t_pb_type* cur_pb_type) { - int imode, ipb; - - cur_pb_type->temp_placement_index = 0; - - /* See when we reach the primitive */ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - return; - } - - /* We cannot find what we want this level, go recursively */ - /* Check each mode*/ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - rec_reset_pb_type_temp_placement_index(&(cur_pb_type->modes[imode].pb_type_children[ipb])); - } - } - - return; -} - -/* Reset the phy_pb_type in pb_type to be 0 */ -void rec_reset_pb_type_phy_pb_type(t_pb_type* cur_pb_type) { - int imode, ipb; - - cur_pb_type->phy_pb_type = NULL; - - /* See when we reach the primitive */ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - return; - } - - /* We cannot find what we want this level, go recursively */ - /* Check each mode*/ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - rec_reset_pb_type_phy_pb_type(&(cur_pb_type->modes[imode].pb_type_children[ipb])); - } - } - - return; -} - -/* Identify if this child_pb is actually used for wiring!!! */ -boolean is_pb_used_for_wiring(t_pb_graph_node* cur_pb_graph_node, - t_pb_type* cur_pb_type, - t_rr_node* pb_rr_graph) { - boolean is_used = FALSE; - int node_index; - int port_index = 0; - int iport, ipin; - - for (iport = 0; iport < cur_pb_type->num_ports && !is_used; iport++) { - if (OUT_PORT == cur_pb_type->ports[iport].type) { - for (ipin = 0; ipin < cur_pb_type->ports[iport].num_pins; ipin++) { - node_index = cur_pb_graph_node->output_pins[port_index][ipin].pin_count_in_cluster; - if ((OPEN != pb_rr_graph[node_index].net_num) - || (OPEN != pb_rr_graph[node_index].vpack_net_num)) { - return TRUE; - } - } - port_index++; - } - } - - return is_used; -} - -char* get_pb_graph_full_name_in_hierarchy(t_pb_graph_node* cur_pb_graph_node) { - char* full_name = NULL; - char* cur_name = NULL; - t_pb_graph_node* temp = cur_pb_graph_node; - - while (NULL != temp) { - cur_name = (char*)my_malloc(1 + strlen(temp->pb_type->name) + 1 - + strlen(my_itoa(temp->placement_index)) + 2); - /* For top node, we do not put a slash at the beginning */ - if (NULL == temp->parent_pb_graph_node) { - sprintf(cur_name, "%s[%d]", - temp->pb_type->name, - temp->placement_index); - } else { - sprintf(cur_name, "/%s[%d]", - temp->pb_type->name, - temp->placement_index); - } - if (NULL != full_name) { - full_name = my_strcat(cur_name, full_name); - } else { - full_name = my_strdup(cur_name); - } - temp = temp->parent_pb_graph_node; - my_free(cur_name); - } - - return full_name; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h deleted file mode 100644 index 27d473508..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ /dev/null @@ -1,270 +0,0 @@ -#ifndef FPGA_X2P_PBTYPES_UTILS_H -#define FPGA_X2P_PBTYPES_UTILS_H - -/* Only include header files those are required by the data types in the following function declaration */ -#include -#include -#include "vtr_geometry.h" -#include "device_port.h" -#include "vpr_types.h" -#include "circuit_library.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_bitstream_utils.h" - -void check_pb_graph_edge(t_pb_graph_edge pb_graph_edge); - -void check_pb_graph_pin_edges(t_pb_graph_pin pb_graph_pin); - -void backup_one_pb_rr_node_pack_prev_node_edge(t_rr_node* pb_rr_node); - -int find_parent_pb_type_child_index(t_pb_type* parent_pb_type, - int mode_index, - t_pb_type* child_pb_type); - -void gen_spice_name_tag_phy_pb_rec(t_phy_pb* cur_phy_pb, - char* prefix); - -void gen_spice_name_tag_pb_rec(t_pb* cur_pb, - char* prefix); - -void gen_spice_name_tags_all_pbs(); - -void gen_spice_name_tags_all_phy_pbs(); - -int find_pb_mapped_logical_block_rec(t_pb* cur_pb, - t_spice_model* pb_spice_model, - char* pb_spice_name_tag); - -int find_grid_mapped_logical_block(int x, int y, - t_spice_model* pb_spice_model, - char* pb_spice_name_tag); - -void stats_pb_graph_node_port_pin_numbers(t_pb_graph_node* cur_pb_graph_node, - int* num_inputs, - int* num_outputs, - int* num_clock_pins); - -int find_pb_type_idle_mode_index(t_pb_type cur_pb_type); - -int find_pb_type_physical_mode_index(t_pb_type cur_pb_type); - -void mark_grid_type_pb_graph_node_pins_temp_net_num(int x, int y); - -void assign_pb_graph_node_pin_temp_net_num_by_mode_index(t_pb_graph_pin* cur_pb_graph_pin, - int mode_index); - -void mark_pb_graph_node_input_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node, - int mode_index); - -void mark_pb_graph_node_clock_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node, - int mode_index); - -void mark_pb_graph_node_output_pins_temp_net_num(t_pb_graph_node* cur_pb_graph_node, - int mode_index); - -void rec_mark_pb_graph_node_temp_net_num(t_pb_graph_node* cur_pb_graph_node); - -void load_one_pb_graph_pin_temp_net_num_from_pb(t_phy_pb* cur_pb, - t_pb_graph_pin* cur_pb_graph_pin); - -void load_pb_graph_node_temp_net_num_from_pb(t_phy_pb* cur_pb); - -void rec_mark_one_pb_unused_pb_graph_node_temp_net_num(t_phy_pb* cur_pb); - -void update_pb_vpack_net_num_from_temp_net_num(t_phy_pb* cur_pb, - t_pb_graph_pin* cur_pb_graph_pin); - -void update_pb_graph_node_temp_net_num_to_pb(t_pb_graph_node* cur_pb_graph_node, - t_phy_pb* cur_pb); - -void rec_load_unused_pb_graph_node_temp_net_num_to_pb(t_phy_pb* cur_pb); - -void mark_one_pb_parasitic_nets(t_phy_pb* cur_pb); - -int count_num_conf_bit_one_interc(t_interconnect* cur_interc, - enum e_sram_orgz cur_sram_orgz_type); - -int count_num_conf_bits_pb_type_mode_interc(t_mode* cur_pb_type_mode, - enum e_sram_orgz cur_sram_orgz_type); - -int rec_count_num_conf_bits_pb_type_default_mode(t_pb_type* cur_pb_type, - t_sram_orgz_info* cur_sram_orgz_info); - -int rec_count_num_conf_bits_pb_type_physical_mode(t_pb_type* cur_pb_type, - t_sram_orgz_info* cur_sram_orgz_info); - -int rec_count_num_conf_bits_pb(t_pb* cur_pb, - t_sram_orgz_info* cur_sram_orgz_info); - -void init_one_grid_num_conf_bits(int ix, int iy, - t_sram_orgz_info* cur_sram_orgz_info); - -void init_grids_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info); - -void init_pb_types_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info); - -void map_clb_pins_to_pb_graph_pins(); - -t_port* find_pb_type_port_match_spice_model_port(t_pb_type* pb_type, - t_spice_model_port* spice_model_port); - -std::vector find_pb_type_ports_match_circuit_model_port_type(t_pb_type* pb_type, - enum e_spice_model_port_type port_type); - -t_port** find_pb_type_ports_match_spice_model_port_type(t_pb_type* pb_type, - enum e_spice_model_port_type port_type, - int* port_num); - -enum e_interconnect find_pb_graph_pin_in_edges_interc_type(t_pb_graph_pin pb_graph_pin); - -t_spice_model* find_pb_graph_pin_in_edges_interc_spice_model(t_pb_graph_pin pb_graph_pin); - -int find_path_id_between_pb_rr_nodes(t_rr_node* local_rr_graph, - int src_node, - int des_node); - -t_pb* get_child_pb_for_phy_pb_graph_node(t_pb* cur_pb, int ipb, int jpb); - -t_phy_pb* get_phy_child_pb_for_phy_pb_graph_node(t_phy_pb* cur_phy_pb, int ipb, int jpb); - -t_spice_model* find_pb_graph_pin_in_edges_interc_model(t_pb_graph_pin pb_graph_pin) ; - -void find_interc_fan_in_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode, - t_interconnect** cur_interc, - int* fan_in) ; - -void find_interc_des_pb_graph_pin(t_pb_graph_pin* des_pb_graph_pin, - int cur_mode, - t_interconnect** cur_interc); - -void rec_count_num_iopads_pb_type_physical_mode(t_pb_type* cur_pb_type); - -void rec_count_num_iopads_pb_type_default_mode(t_pb_type* cur_pb_type); - -void rec_count_num_iopads_pb(t_pb* cur_pb); - -void init_one_grid_num_iopads(int ix, int iy); - -void init_grids_num_iopads(); - -void init_pb_types_num_iopads(); - -void rec_count_num_mode_bits_pb_type_default_mode(t_pb_type* cur_pb_type); - -void rec_count_num_mode_bits_pb(t_pb* cur_pb); - -void init_one_grid_num_mode_bits(int ix, int iy); - -void init_grids_num_mode_bits(); - -t_pb* get_lut_child_pb(t_pb* cur_lut_pb, - int mode_index); - -t_phy_pb* get_lut_child_phy_pb(t_phy_pb* cur_lut_pb, - int mode_index); - -t_pb* get_hardlogic_child_pb(t_pb* cur_hardlogic_pb, - int mode_index); - -size_t find_grid_pin_height(const std::vector>& grids, - const vtr::Point& grid_coordinate, - const size_t& pin_index); - -int get_grid_pin_height(int grid_x, int grid_y, int pin_index); - -int get_grid_pin_side(int grid_x, int grid_y, int pin_index); - -e_side find_grid_pin_side(const vtr::Point& device_size, - const std::vector>& grids, - const vtr::Point& grid_coordinate, - const size_t& pin_height, - const size_t& pin_index); - -int* decode_mode_bits(char* mode_bits, int* num_sram_bits); - -enum e_interconnect determine_actual_pb_interc_type(t_interconnect* def_interc, - int fan_in) ; - -int count_pin_number_one_port_pb_graph_node(int num_ports, int* num_pins); - -int count_pin_number_one_pb_graph_node(t_pb_graph_node* cur_pb_graph_node); - -int count_pb_graph_node_input_edge_in_phy_mode(t_pb_graph_pin* cur_pb_graph_pin, - int phy_mode_index); - -int count_pb_graph_node_output_edge_in_phy_mode(t_pb_graph_pin* cur_pb_graph_pin, - int phy_mode_index); - -t_pb_type* rec_get_pb_type_by_name(t_pb_type* cur_pb_type, - char* pb_type_name); - -void decode_physical_mode_pin_annotation(int phy_pb_type_port_size, - char* phy_mode_pin, - char** port_name, - int* pin_msb, int* pin_lsb); - -void annotate_physical_mode_pin_to_pb_type(t_port* cur_pb_type_port, - t_pb_type* phy_pb_type); - -void annotate_pb_type_port_to_phy_pb_type(t_pb_type* cur_pb_type, - t_pb_type* phy_pb_type); - -t_pb_graph_node* rec_get_pb_graph_node_by_pb_type_and_placement_index_in_top_node(t_pb_graph_node* cur_pb_graph_node, - t_pb_type* target_pb_type, - int target_placement_index); - -boolean check_pin_number_match_phy_pb_graph_pin(t_pb_graph_pin* cur_pb_graph_pin, - t_pb_graph_pin* phy_pb_graph_pin); - -void link_one_pb_graph_node_pin_to_phy_pb_graph_pin(t_pb_graph_pin* cur_pb_graph_pin, - t_pb_graph_node* phy_pb_graph_node); - -void link_pb_graph_node_pins_to_phy_pb_graph_pins(t_pb_graph_node* cur_pb_graph_node, - t_pb_graph_node* phy_pb_graph_node); - -void rec_reset_pb_graph_node_rr_node_index_physical_pb(t_pb_graph_node* cur_pb_graph_node); - -void rec_alloc_phy_pb_children(t_pb_graph_node* cur_pb_graph_node, - t_phy_pb* cur_phy_pb); - -t_phy_pb* rec_get_phy_pb_by_name(t_phy_pb* cur_phy_pb, - char* phy_pb_name); - -int get_pb_graph_node_wired_lut_logical_block_index(t_pb_graph_node* cur_pb_graph_node, - t_rr_node* op_pb_rr_graph); - -void sync_wired_lut_to_one_phy_pb(t_pb_graph_node* cur_pb_graph_node, - t_phy_pb* cur_phy_pb, - t_rr_node* op_pb_rr_graph); - -void rec_sync_op_pb_mapping_to_phy_pb_children(t_pb* cur_op_pb, - t_phy_pb* cur_phy_pb); - -void alloc_and_load_phy_pb_children_for_one_mapped_block(t_pb* cur_pb, - t_phy_pb* cur_phy_pb); - -void get_mapped_lut_phy_pb_input_pin_vpack_net_num(t_phy_pb* lut_phy_pb, - int* num_lut_pin, int** lut_pin_net); - -std::vector find_mapped_lut_phy_pb_input_pin_vpack_net_num(t_phy_pb* lut_phy_pb); - -void get_mapped_lut_pb_input_pin_vpack_net_num(t_pb* lut_pb, - int* num_lut_pin, int** lut_pin_net); - -void get_lut_logical_block_input_pin_vpack_net_num(t_logical_block* lut_logical_block, - int* num_lut_pin, int** lut_pin_net); - -std::vector find_lut_logical_block_input_pin_vpack_net_num(t_logical_block* lut_logical_block); - -void rec_reset_pb_type_temp_placement_index(t_pb_type* cur_pb_type); - -void rec_reset_pb_type_phy_pb_type(t_pb_type* cur_pb_type); - -boolean is_pb_used_for_wiring(t_pb_graph_node* cur_pb_graph_node, - t_pb_type* cur_pb_type, - t_rr_node* pb_rr_graph); - -char* get_pb_graph_full_name_in_hierarchy(t_pb_graph_node* cur_pb_graph_node); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h deleted file mode 100644 index c334feef1..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_reserved_words.h +++ /dev/null @@ -1,27 +0,0 @@ -/******************************************************************** - * This file includes all the reserved words that are used in - * naming module, blocks, instances and cells in FPGA X2P support, - * including: - * Verilog generation, SPICE generation and bitstream generation - *******************************************************************/ -#ifndef FPGA_X2P_RESERVED_WORDS_H -#define FPGA_X2P_RESERVED_WORDS_H - -/* Grid naming constant strings */ -constexpr char* GRID_MODULE_NAME_PREFIX = "grid_"; - -/* Memory naming constant strings */ -constexpr char* GRID_MEM_INSTANCE_PREFIX = "mem_"; -constexpr char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; -constexpr char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_"; -constexpr char* MEMORY_MODULE_POSTFIX = "_mem"; - -/* Multiplexer naming constant strings */ -constexpr char* GRID_MUX_INSTANCE_PREFIX = "mux_"; -constexpr char* SWITCH_BLOCK_MUX_INSTANCE_PREFIX = "mux_"; -constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_"; - -/* Bitstream file strings */ -constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml"; - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_rr_graph_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_rr_graph_utils.c deleted file mode 100644 index d3ed17587..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_rr_graph_utils.c +++ /dev/null @@ -1,1229 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include SPICE support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_rr_graph_utils.h" - -#include "rr_graph_builder_utils.h" - -/* Initial rr_graph */ -void init_rr_graph(INOUTP t_rr_graph* local_rr_graph) { - /* Give zero and NULL to all the contents */ - local_rr_graph->num_rr_nodes = 0; - local_rr_graph->rr_node = NULL; - local_rr_graph->rr_node_indices = NULL; - - local_rr_graph->num_switch_inf = 0; - local_rr_graph->switch_inf = NULL; - local_rr_graph->delayless_switch_index = 0; - - local_rr_graph->num_nets = 0; - local_rr_graph->net = NULL; - local_rr_graph->net_to_vpack_net_mapping = NULL; - local_rr_graph->net_num_sources = NULL; - local_rr_graph->net_num_sinks = NULL; - - local_rr_graph->net_rr_sources = NULL; - local_rr_graph->net_rr_sinks = NULL; - local_rr_graph->net_rr_terminals = NULL; - memset(&(local_rr_graph->rr_mem_ch), 0, sizeof(t_chunk)); - - local_rr_graph->num_rr_indexed_data = 0; - local_rr_graph->rr_indexed_data = NULL; - - local_rr_graph->rr_node_route_inf = NULL; - local_rr_graph->route_bb = NULL; - - local_rr_graph->trace_head = NULL; - local_rr_graph->trace_tail = NULL; - local_rr_graph->trace_free_head = NULL; - memset(&(local_rr_graph->trace_ch), 0, sizeof(t_chunk)); - - local_rr_graph->heap = NULL; - local_rr_graph->heap_size = 0; - local_rr_graph->heap_tail = 0; - - local_rr_graph->heap_free_head = NULL; - memset(&(local_rr_graph->heap_ch), 0, sizeof(t_chunk)); - - local_rr_graph->rr_modified_head = NULL; - local_rr_graph->linked_f_pointer_free_head = NULL; - - //local_rr_graph->linked_f_pointer_ch = {NULL, 0, NULL}; - memset(&(local_rr_graph->linked_f_pointer_ch), 0, sizeof(t_chunk)); - - #ifdef DEBUG - local_rr_graph->num_trace_allocated = 0; - local_rr_graph->num_heap_allocated = 0; - local_rr_graph->num_linked_f_pointer_allocated = 0; - #endif - - return; -} - -void alloc_rr_graph_net_rr_sources_and_sinks(t_rr_graph* local_rr_graph) { - int inet, isrc, isink, inode; - int num_sources_in_rr_graph, num_sinks_in_rr_graph; - - local_rr_graph->net_num_sources = (int *) my_calloc(local_rr_graph->num_nets, sizeof(int)); - local_rr_graph->net_num_sinks = (int *) my_calloc(local_rr_graph->num_nets, sizeof(int)); - - local_rr_graph->net_rr_sources = (int **) my_calloc(local_rr_graph->num_nets, sizeof(int*)); - local_rr_graph->net_rr_sinks = (int **) my_calloc(local_rr_graph->num_nets, sizeof(int*)); - - for (inet = 0; inet < local_rr_graph->num_nets; inet++) { - /* Count how many SINKs we have in the rr_graph that is mapped to this net */ - num_sources_in_rr_graph = 0; - num_sinks_in_rr_graph = 0; - for (inode = 0; inode < local_rr_graph->num_rr_nodes; inode++) { - /* Only care the rr_node mapped to this net */ - if (inet != local_rr_graph->rr_node[inode].net_num) { - continue; - } - if (SOURCE == local_rr_graph->rr_node[inode].type) { - num_sources_in_rr_graph++; - } - if (SINK == local_rr_graph->rr_node[inode].type) { - num_sinks_in_rr_graph++; - } - } - local_rr_graph->net_num_sources[inet] = num_sources_in_rr_graph; - local_rr_graph->net_num_sinks[inet] = num_sinks_in_rr_graph; - /* Consider the SOURCE (index=0), a special SINK */ - local_rr_graph->net_rr_sources[inet] = (int *) my_malloc(num_sources_in_rr_graph * sizeof(int)); - local_rr_graph->net_rr_sinks[inet] = (int *) my_malloc(num_sinks_in_rr_graph * sizeof(int)); - /* Initialize all terminal to be OPEN */ - for (isrc = 0; isrc < local_rr_graph->net_num_sources[inet]; isrc++) { - local_rr_graph->net_rr_sources[inet][isrc] = OPEN; - } - for (isink = 0; isink < local_rr_graph->net_num_sinks[inet]; isink++) { - local_rr_graph->net_rr_sinks[inet][isink] = OPEN; - } - } - - return; -} - -void alloc_rr_graph_net_rr_terminals(t_rr_graph* local_rr_graph) { - int inet, isink, inode, num_sinks_in_rr_graph; - - local_rr_graph->net_rr_terminals = (int **) my_malloc(local_rr_graph->num_nets * sizeof(int *)); - local_rr_graph->net_num_sinks = (int *) my_calloc(local_rr_graph->num_nets, sizeof(int)); - - for (inet = 0; inet < local_rr_graph->num_nets; inet++) { - /* Count how many SINKs we have in the rr_graph that is mapped to this net */ - num_sinks_in_rr_graph = 0; - for (inode = 0; inode < local_rr_graph->num_rr_nodes; inode++) { - if ((SINK == local_rr_graph->rr_node[inode].type) - && (inet == local_rr_graph->rr_node[inode].net_num)) { - num_sinks_in_rr_graph++; - } - } - local_rr_graph->net_num_sinks[inet] = num_sinks_in_rr_graph; - /* Consider the SOURCE (index=0), a special SINK */ - local_rr_graph->net_rr_terminals[inet] = (int *) my_chunk_malloc((num_sinks_in_rr_graph + 1) * sizeof(int), - &local_rr_graph->rr_mem_ch); - /* Initialize all terminal to be OPEN */ - local_rr_graph->net_rr_terminals[inet][0] = OPEN; - for (isink = 1; isink < local_rr_graph->net_num_sinks[inet] + 1; isink++) { - local_rr_graph->net_rr_terminals[inet][isink] = OPEN; - } - } - - return; -} - -void alloc_rr_graph_route_static_structs(t_rr_graph* local_rr_graph, - int heap_size) { - local_rr_graph->trace_head = (t_trace **) my_calloc(local_rr_graph->num_nets, sizeof(t_trace*)); - local_rr_graph->trace_tail = (t_trace **) my_malloc(local_rr_graph->num_nets * sizeof(t_trace*)); - - local_rr_graph->heap_size = heap_size; - local_rr_graph->heap = (t_heap **) my_malloc(local_rr_graph->heap_size * sizeof(t_heap*)); - local_rr_graph->heap--; /* heap stores from [1..heap_size] */ - local_rr_graph->heap_tail = 1; - - local_rr_graph->route_bb = (t_bb *) my_malloc(local_rr_graph->num_nets * sizeof(t_bb)); - - return; -} - -void alloc_and_load_rr_graph_rr_node(INOUTP t_rr_graph* local_rr_graph, - int local_num_rr_nodes) { - local_rr_graph->num_rr_nodes = local_num_rr_nodes; - /* Allocate rr_graph */ - local_rr_graph->rr_node = (t_rr_node*) my_calloc(local_rr_graph->num_rr_nodes, sizeof(t_rr_node)); - - return; -} - -/* Returns the segment number at which the segment this track lies on * - * started. */ -static -int get_rr_graph_seg_start(INP t_seg_details * seg_details, INP int itrack, - INP int chan_num, INP int seg_num) { - - int seg_start, length, start; - - seg_start = 1; - if (FALSE == seg_details[itrack].longline) { - - length = seg_details[itrack].length; - start = seg_details[itrack].start; - - /* Start is guaranteed to be between 1 and length. Hence adding length to * - * the quantity in brackets below guarantees it will be nonnegative. */ - /* Original VPR */ - assert(start > 0); - /* end */ - /* mrFPGA: Xifan TANG */ - /* assert(is_stack ? start >= 0: start > 0); */ - /* end */ - assert(start <= length); - - /* NOTE: Start points are staggered between different channels. - * The start point must stagger backwards as chan_num increases. - * Unidirectional routing expects this to allow the N-to-N - * assumption to be made with respect to ending wires in the core. */ - /* mrFPGA: Xifan TANG */ - /* - seg_start = seg_num - (seg_num - (is_stack ? 1 : 0) + length + chan_num - start) % length; - seg_start = std::max(seg_start, is_stack ? 0 : 1); - */ - /* end */ - /* Original VPR */ - seg_start = seg_num - (seg_num + length + chan_num - start) % length; - if (seg_start < 1) { - seg_start = 1; - } - /* end */ - } - - return seg_start; -} - - -void load_rr_graph_chan_rr_indices(t_rr_graph* local_rr_graph, - INP int nodes_per_chan, INP int chan_len, - INP int num_chans, INP t_rr_type type, INP t_seg_details * seg_details, - INOUTP int *index) { - int chan, seg, track, start, inode; - - local_rr_graph->rr_node_indices[type] = (t_ivec **) my_malloc(sizeof(t_ivec *) * num_chans); - for (chan = 0; chan < num_chans; ++chan) { - local_rr_graph->rr_node_indices[type][chan] = (t_ivec *) my_malloc(sizeof(t_ivec) * chan_len); - - local_rr_graph->rr_node_indices[type][chan][0].nelem = 0; - local_rr_graph->rr_node_indices[type][chan][0].list = NULL; - - for (seg = 1; seg < chan_len; ++seg) { - /* Alloc the track inode lookup list */ - local_rr_graph->rr_node_indices[type][chan][seg].nelem = nodes_per_chan; - local_rr_graph->rr_node_indices[type][chan][seg].list = (int *) my_malloc( - sizeof(int) * nodes_per_chan); - for (track = 0; track < nodes_per_chan; ++track) { - local_rr_graph->rr_node_indices[type][chan][seg].list[track] = OPEN; - } - } - } - - /* Original VPR */ - for (chan = 0; chan < num_chans; ++chan) { - for (seg = 1; seg < chan_len; ++seg) { - /* end */ - /* mrFPGA: Xifan TANG */ - /* - for (chan = (is_stack ? 1 : 0); chan < num_chans; ++chan) { - for (seg = (is_stack ? 0 : 1); seg < chan_len; ++seg) { - */ - /* end */ - /* Assign an inode to the starts of tracks */ - for (track = 0; track < local_rr_graph->rr_node_indices[type][chan][seg].nelem; ++track) { - start = get_rr_graph_seg_start(seg_details, track, chan, seg); - /* Original VPR */ - /* If the start of the wire doesn't have a inode, - * assign one to it. */ - inode = local_rr_graph->rr_node_indices[type][chan][start].list[track]; - if (OPEN == inode) { - inode = *index; - ++(*index); - - local_rr_graph->rr_node_indices[type][chan][start].list[track] = inode; - } - /* end */ - /* Assign inode of start of wire to current position */ - local_rr_graph->rr_node_indices[type][chan][seg].list[track] = inode; - } - } - } - return; -} - - -void alloc_and_load_rr_graph_rr_node_indices(t_rr_graph* local_rr_graph, - INP int nodes_per_chan, - INP int L_nx, INP int L_ny, t_grid_tile** L_grid, - INOUTP int *index, INP t_seg_details * seg_details) { - - /* Allocates and loads all the structures needed for fast lookups of the * - * index of an rr_node. rr_node_indices is a matrix containing the index * - * of the *first* rr_node at a given (i,j) location. */ - - int i, j, k, ofs; - t_ivec tmp; - t_type_ptr type; - - /* Alloc the lookup table */ - local_rr_graph->rr_node_indices = (t_ivec ***) my_malloc(sizeof(t_ivec **) * NUM_RR_TYPES); - local_rr_graph->rr_node_indices[IPIN] = (t_ivec **) my_malloc(sizeof(t_ivec *) * (L_nx + 2)); - local_rr_graph->rr_node_indices[SINK] = (t_ivec **) my_malloc(sizeof(t_ivec *) * (L_nx + 2)); - for (i = 0; i <= (L_nx + 1); ++i) { - local_rr_graph->rr_node_indices[IPIN][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * (L_ny + 2)); - local_rr_graph->rr_node_indices[SINK][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * (L_ny + 2)); - for (j = 0; j <= (L_ny + 1); ++j) { - local_rr_graph->rr_node_indices[IPIN][i][j].nelem = 0; - local_rr_graph->rr_node_indices[IPIN][i][j].list = NULL; - - local_rr_graph->rr_node_indices[SINK][i][j].nelem = 0; - local_rr_graph->rr_node_indices[SINK][i][j].list = NULL; - } - } - - /* Count indices for block nodes */ - for (i = 0; i <= (L_nx + 1); i++) { - for (j = 0; j <= (L_ny + 1); j++) { - ofs = L_grid[i][j].offset; - if (0 == ofs) { - type = L_grid[i][j].type; - - /* Load the pin class lookups. The ptc nums for SINK and SOURCE - * are disjoint so they can share the list. */ - tmp.nelem = type->num_class; - tmp.list = NULL; - if (tmp.nelem > 0) { - tmp.list = (int *) my_malloc(sizeof(int) * tmp.nelem); - for (k = 0; k < tmp.nelem; ++k) { - tmp.list[k] = *index; - ++(*index); - } - } - local_rr_graph->rr_node_indices[SINK][i][j] = tmp; - - /* Load the pin lookups. The ptc nums for IPIN and OPIN - * are disjoint so they can share the list. */ - tmp.nelem = type->num_pins; - tmp.list = NULL; - if (tmp.nelem > 0) { - tmp.list = (int *) my_malloc(sizeof(int) * tmp.nelem); - for (k = 0; k < tmp.nelem; ++k) { - tmp.list[k] = *index; - ++(*index); - } - } - local_rr_graph->rr_node_indices[IPIN][i][j] = tmp; - } - } - } - - /* Point offset blocks of a large block to base block */ - for (i = 0; i <= (L_nx + 1); i++) { - for (j = 0; j <= (L_ny + 1); j++) { - ofs = L_grid[i][j].offset; - if (ofs > 0) { - /* NOTE: this only supports vertical large blocks */ - local_rr_graph->rr_node_indices[SINK][i][j] = local_rr_graph->rr_node_indices[SINK][i][j - ofs]; - local_rr_graph->rr_node_indices[IPIN][i][j] = local_rr_graph->rr_node_indices[IPIN][i][j - ofs]; - } - } - } - - /* SOURCE and SINK have unique ptc values so their data can be shared. - * IPIN and OPIN have unique ptc values so their data can be shared. */ - local_rr_graph->rr_node_indices[SOURCE] = local_rr_graph->rr_node_indices[SINK]; - local_rr_graph->rr_node_indices[OPIN] = local_rr_graph->rr_node_indices[IPIN]; - - /* Original VPR */ - /* Load the data for x and y channels */ - load_rr_graph_chan_rr_indices(local_rr_graph, nodes_per_chan, L_nx + 1, L_ny + 1, CHANX, seg_details, - index); - load_rr_graph_chan_rr_indices(local_rr_graph, nodes_per_chan, L_ny + 1, L_nx + 1, CHANY, seg_details, - index); - /* end */ - /* mrFPGA : Xifan TANG */ - /* - load_rr_graph_chan_rr_indices(local_rr_graph, nodes_per_chan, (is_stack ? L_ny + 1 : L_nx + 1), (is_stack ? L_nx + 1 : L_ny + 1), - CHANX, seg_details, index); - load_rr_graph_chan_rr_indices(local_rr_graph, nodes_per_chan, (is_stack ? L_nx + 1 : L_ny + 1), (is_stack ? L_ny + 1 : L_nx + 1), - CHANY, seg_details, index); - */ - /* end */ - return; -} - - - -void alloc_and_load_rr_graph_switch_inf(INOUTP t_rr_graph* local_rr_graph, - int num_switch_inf, - INP t_switch_inf* switch_inf) { - local_rr_graph->num_switch_inf = num_switch_inf; - /* Allocate memory */ - local_rr_graph->switch_inf = (t_switch_inf*) my_calloc(local_rr_graph->num_switch_inf, sizeof(t_switch_inf)); - /* Create a local copy */ - memcpy(local_rr_graph->switch_inf, switch_inf, sizeof(t_switch_inf)); - - return; -} - -/* Allocate a LL_rr_node route structs for a given rr_graph - * This is function is a copy of alloc_and_load_rr_node_route_structs - * The major difference lies in removing the use of global variables - */ -void alloc_and_load_rr_graph_route_structs(t_rr_graph* local_rr_graph) { - /* Allocates some extra information about each LL_rr_node that is used only * - * during routing. */ - - int inode; - - local_rr_graph->rr_node_route_inf = (t_rr_node_route_inf *) my_calloc(local_rr_graph->num_rr_nodes, sizeof(t_rr_node_route_inf)); - - for (inode = 0; inode < local_rr_graph->num_rr_nodes; inode++) { - local_rr_graph->rr_node_route_inf[inode].prev_node = NO_PREVIOUS; - local_rr_graph->rr_node_route_inf[inode].prev_edge = NO_PREVIOUS; - local_rr_graph->rr_node_route_inf[inode].pres_cost = 1.; - local_rr_graph->rr_node_route_inf[inode].acc_cost = 1.; - local_rr_graph->rr_node_route_inf[inode].path_cost = HUGE_POSITIVE_FLOAT; - local_rr_graph->rr_node_route_inf[inode].target_flag = 0; - } - - return; -} - -t_heap * get_rr_graph_heap_head(t_rr_graph* local_rr_graph) { - - /* Returns a pointer to the smallest element on the heap, or NULL if the * - * heap is empty. Invalid (index == OPEN) entries on the heap are never * - * returned -- they are just skipped over. */ - - int ito, ifrom; - t_heap *heap_head, *temp_ptr; - - do { - if (local_rr_graph->heap_tail == 1) { /* Empty heap. */ - /* - vpr_printf(TIO_MESSAGE_WARNING, "Empty heap occurred in get_heap_head.\n"); - vpr_printf(TIO_MESSAGE_WARNING, "Some blocks are impossible to connect in this architecture.\n"); - */ - return (NULL); - } - - heap_head = local_rr_graph->heap[1]; /* Smallest element. */ - - /* Now fix up the heap */ - - local_rr_graph->heap_tail--; - local_rr_graph->heap[1] = local_rr_graph->heap[local_rr_graph->heap_tail]; - ifrom = 1; - ito = 2 * ifrom; - - while (ito < local_rr_graph->heap_tail) { - if (local_rr_graph->heap[ito + 1]->cost < local_rr_graph->heap[ito]->cost) - ito++; - if (local_rr_graph->heap[ito]->cost > local_rr_graph->heap[ifrom]->cost) - break; - temp_ptr = local_rr_graph->heap[ito]; - local_rr_graph->heap[ito] = local_rr_graph->heap[ifrom]; - local_rr_graph->heap[ifrom] = temp_ptr; - ifrom = ito; - ito = 2 * ifrom; - } - - } while (heap_head->index == OPEN); /* Get another one if invalid entry. */ - - return (heap_head); -} - -t_linked_f_pointer* alloc_rr_graph_linked_f_pointer(t_rr_graph* local_rr_graph) { - - /* This routine returns a linked list element with a float pointer as * - * the node data. */ - - /*int i;*/ - t_linked_f_pointer *temp_ptr; - - if (local_rr_graph->linked_f_pointer_free_head == NULL) { - /* No elements on the free list */ - local_rr_graph->linked_f_pointer_free_head = (t_linked_f_pointer *) my_chunk_malloc(sizeof(t_linked_f_pointer), &local_rr_graph->linked_f_pointer_ch); - local_rr_graph->linked_f_pointer_free_head->next = NULL; - } - - temp_ptr = local_rr_graph->linked_f_pointer_free_head; - local_rr_graph->linked_f_pointer_free_head = local_rr_graph->linked_f_pointer_free_head->next; - -#ifdef DEBUG - local_rr_graph->num_linked_f_pointer_allocated++; -#endif - - return (temp_ptr); -} - - -void add_to_rr_graph_mod_list(t_rr_graph* local_rr_graph, - float *fptr) { - - /* This routine adds the floating point pointer (fptr) into a * - * linked list that indicates all the pathcosts that have been * - * modified thus far. */ - - t_linked_f_pointer *mod_ptr; - - mod_ptr = alloc_rr_graph_linked_f_pointer(local_rr_graph); - - /* Add this element to the start of the modified list. */ - - mod_ptr->next = local_rr_graph->rr_modified_head; - mod_ptr->fptr = fptr; - local_rr_graph->rr_modified_head = mod_ptr; -} - -void free_rr_graph_heap_data(t_rr_graph* local_rr_graph, - t_heap *hptr) { - - hptr->u.next = local_rr_graph->heap_free_head; - local_rr_graph->heap_free_head = hptr; -#ifdef DEBUG - local_rr_graph->num_heap_allocated--; -#endif -} - -t_trace* alloc_rr_graph_trace_data(t_rr_graph* local_rr_graph) { - - t_trace *temp_ptr; - - if (local_rr_graph->trace_free_head == NULL) { /* No elements on the free list */ - local_rr_graph->trace_free_head = (t_trace *) my_chunk_malloc(sizeof(t_trace), &local_rr_graph->trace_ch); - local_rr_graph->trace_free_head->next = NULL; - } - temp_ptr = local_rr_graph->trace_free_head; - local_rr_graph->trace_free_head = local_rr_graph->trace_free_head->next; -#ifdef DEBUG - local_rr_graph->num_trace_allocated++; -#endif - return (temp_ptr); -} - -void empty_rr_graph_heap(t_rr_graph* local_rr_graph) { - - int i; - - for (i = 1; i < local_rr_graph->heap_tail; i++) - free_rr_graph_heap_data(local_rr_graph, local_rr_graph->heap[i]); - - local_rr_graph->heap_tail = 1; - - return; -} - -void reset_rr_graph_rr_node_route_structs(t_rr_graph* local_rr_graph) { - - /* Allocates some extra information about each rr_node that is used only * - * during routing. */ - - int inode; - - assert(local_rr_graph->rr_node_route_inf != NULL); - - for (inode = 0; inode < local_rr_graph->num_rr_nodes; inode++) { - local_rr_graph->rr_node_route_inf[inode].prev_node = NO_PREVIOUS; - local_rr_graph->rr_node_route_inf[inode].prev_edge = NO_PREVIOUS; - local_rr_graph->rr_node_route_inf[inode].pres_cost = 1.; - local_rr_graph->rr_node_route_inf[inode].acc_cost = 1.; - local_rr_graph->rr_node_route_inf[inode].path_cost = HUGE_POSITIVE_FLOAT; - local_rr_graph->rr_node_route_inf[inode].target_flag = 0; - } - - return; -} - - -t_trace* update_rr_graph_traceback(t_rr_graph* local_rr_graph, - t_heap *hptr, int inet) { - - /* This routine adds the most recently finished wire segment to the * - * traceback linked list. The first connection starts with the net SOURCE * - * and begins at the structure pointed to by trace_head[inet]. Each * - * connection ends with a SINK. After each SINK, the next connection * - * begins (if the net has more than 2 pins). The first element after the * - * SINK gives the routing node on a previous piece of the routing, which is * - * the link from the existing net to this new piece of the net. * - * In each traceback I start at the end of a path and trace back through * - * its predecessors to the beginning. I have stored information on the * - * predecesser of each node to make traceback easy -- this sacrificies some * - * memory for easier code maintenance. This routine returns a pointer to * - * the first "new" node in the traceback (node not previously in trace). */ - - struct s_trace *tptr, *prevptr, *temptail, *ret_ptr; - int inode; - short iedge; - -#ifdef DEBUG - t_rr_type rr_type; -#endif - - inode = hptr->index; - -#ifdef DEBUG - rr_type = local_rr_graph->rr_node[inode].type; - if (rr_type != SINK) { - vpr_printf(TIO_MESSAGE_ERROR, "in update_traceback. Expected type = SINK (%d).\n", SINK); - vpr_printf(TIO_MESSAGE_ERROR, "\tGot type = %d while tracing back net %d.\n", rr_type, inet); - exit(1); - } -#endif - - tptr = alloc_rr_graph_trace_data(local_rr_graph); /* SINK on the end of the connection */ - tptr->index = inode; - tptr->iswitch = OPEN; - tptr->next = NULL; - temptail = tptr; /* This will become the new tail at the end */ - /* of the routine. */ - - /* Now do it's predecessor. */ - - inode = hptr->u.prev_node; - iedge = hptr->prev_edge; - - while (inode != NO_PREVIOUS) { - prevptr = alloc_rr_graph_trace_data(local_rr_graph); - prevptr->index = inode; - prevptr->iswitch = local_rr_graph->rr_node[inode].switches[iedge]; - prevptr->next = tptr; - tptr = prevptr; - - iedge = local_rr_graph->rr_node_route_inf[inode].prev_edge; - inode = local_rr_graph->rr_node_route_inf[inode].prev_node; - } - - if (local_rr_graph->trace_tail[inet] != NULL) { - local_rr_graph->trace_tail[inet]->next = tptr; /* Traceback ends with tptr */ - ret_ptr = tptr->next; /* First new segment. */ - } else { /* This was the first "chunk" of the net's routing */ - local_rr_graph->trace_head[inet] = tptr; - ret_ptr = tptr; /* Whole traceback is new. */ - } - - local_rr_graph->trace_tail[inet] = temptail; - return (ret_ptr); -} - - -void reset_rr_graph_path_costs(t_rr_graph* local_rr_graph) { - - /* The routine sets the path_cost to HUGE_POSITIVE_FLOAT for all channel segments * - * touched by previous routing phases. */ - - t_linked_f_pointer *mod_ptr; - -#ifdef DEBUG - int num_mod_ptrs; -#endif - - /* The traversal method below is slightly painful to make it faster. */ - - if (local_rr_graph->rr_modified_head != NULL) { - mod_ptr = local_rr_graph->rr_modified_head; - -#ifdef DEBUG - num_mod_ptrs = 1; -#endif - - while (mod_ptr->next != NULL) { - *(mod_ptr->fptr) = HUGE_POSITIVE_FLOAT; - mod_ptr = mod_ptr->next; -#ifdef DEBUG - num_mod_ptrs++; -#endif - } - *(mod_ptr->fptr) = HUGE_POSITIVE_FLOAT; /* Do last one. */ - - /* Reset the modified list and put all the elements back in the free * - * list. */ - - mod_ptr->next = local_rr_graph->linked_f_pointer_free_head; - local_rr_graph->linked_f_pointer_free_head = local_rr_graph->rr_modified_head; - local_rr_graph->rr_modified_head = NULL; - -#ifdef DEBUG - local_rr_graph->num_linked_f_pointer_allocated -= num_mod_ptrs; -#endif - } - - return; -} - -void alloc_rr_graph_rr_indexed_data(t_rr_graph* local_rr_graph, int L_num_rr_indexed_data) { - local_rr_graph->num_rr_indexed_data = L_num_rr_indexed_data; - local_rr_graph->rr_indexed_data = (t_rr_indexed_data *) my_calloc(L_num_rr_indexed_data, sizeof(t_rr_indexed_data)); - - return; -} - -/* a copy of get_rr_cong_cost, - * I remove all the use of global variables */ -float get_rr_graph_rr_cong_cost(t_rr_graph* local_rr_graph, - int rr_node_index) { - - /* Returns the *congestion* cost of using this rr_node. */ - - short cost_index; - float cost; - - cost_index = local_rr_graph->rr_node[rr_node_index].cost_index; - cost = local_rr_graph->rr_indexed_data[cost_index].base_cost - * local_rr_graph->rr_node_route_inf[rr_node_index].acc_cost - * local_rr_graph->rr_node_route_inf[rr_node_index].pres_cost; - return (cost); -} - -t_heap * alloc_rr_graph_heap_data(t_rr_graph* local_rr_graph) { - - t_heap *temp_ptr; - - if (local_rr_graph->heap_free_head == NULL) { /* No elements on the free list */ - local_rr_graph->heap_free_head = (t_heap *) my_chunk_malloc(sizeof(t_heap), &(local_rr_graph->heap_ch)); - local_rr_graph->heap_free_head->u.next = NULL; - } - - temp_ptr = local_rr_graph->heap_free_head; - local_rr_graph->heap_free_head = local_rr_graph->heap_free_head->u.next; -#ifdef DEBUG - local_rr_graph->num_heap_allocated++; -#endif - return (temp_ptr); -} - -void add_heap_node_to_rr_graph_heap(t_rr_graph* local_rr_graph, - t_heap *hptr) { - - /* Adds an item to the heap, expanding the heap if necessary. */ - - int ito, ifrom; - t_heap *temp_ptr; - - if (local_rr_graph->heap_tail > local_rr_graph->heap_size) { /* Heap is full */ - local_rr_graph->heap_size *= 2; - local_rr_graph->heap = (t_heap **) my_realloc((void *) (local_rr_graph->heap + 1), - local_rr_graph->heap_size * sizeof(t_heap *)); - local_rr_graph->heap--; /* heap goes from [1..heap_size] */ - } - - local_rr_graph->heap[local_rr_graph->heap_tail] = hptr; - ifrom = local_rr_graph->heap_tail; - ito = ifrom / 2; - local_rr_graph->heap_tail++; - - while ((ito >= 1) && (local_rr_graph->heap[ifrom]->cost < local_rr_graph->heap[ito]->cost)) { - temp_ptr = local_rr_graph->heap[ito]; - local_rr_graph->heap[ito] = local_rr_graph->heap[ifrom]; - local_rr_graph->heap[ifrom] = temp_ptr; - ifrom = ito; - ito = ifrom / 2; - } - return; -} - - -void add_node_to_rr_graph_heap(t_rr_graph* local_rr_graph, - int inode, float cost, int prev_node, int prev_edge, - float backward_path_cost, float R_upstream) { - - /* Puts an rr_node on the heap, if the new cost given is lower than the * - * current path_cost to this channel segment. The index of its predecessor * - * is stored to make traceback easy. The index of the edge used to get * - * from its predecessor to it is also stored to make timing analysis, etc. * - * easy. The backward_path_cost and R_upstream values are used only by the * - * timing-driven router -- the breadth-first router ignores them. */ - - struct s_heap *hptr; - - if (cost >= local_rr_graph->rr_node_route_inf[inode].path_cost) { - return; - } - - hptr = alloc_rr_graph_heap_data(local_rr_graph); - hptr->index = inode; - hptr->cost = cost; - hptr->u.prev_node = prev_node; - hptr->prev_edge = prev_edge; - hptr->backward_path_cost = backward_path_cost; - hptr->R_upstream = R_upstream; - add_heap_node_to_rr_graph_heap(local_rr_graph, hptr); - - return; -} - -void mark_rr_graph_sinks(t_rr_graph* local_rr_graph, - int inet, int start_isink, boolean* net_sink_routed) { - - /* Mark all the SINKs of this net as targets by setting their target flags * - * to the number of times the net must connect to each SINK. Note that * - * this number can occassionally be greater than 1 -- think of connecting * - * the same net to two inputs of an and-gate (and-gate inputs are logically * - * equivalent, so both will connect to the same SINK). */ - - int isink, inode; - - for (isink = start_isink; isink < local_rr_graph->net_num_sinks[inet]; isink++) { - /* Bypass routed sinks */ - if (TRUE == net_sink_routed[isink]) { - continue; - } - inode = local_rr_graph->net_rr_sinks[inet][isink]; - if (OPEN == inode) { - continue; - } - local_rr_graph->rr_node_route_inf[inode].target_flag++; - if ( ! ((local_rr_graph->rr_node_route_inf[inode].target_flag > 0) - && (local_rr_graph->rr_node_route_inf[inode].target_flag <= local_rr_graph->rr_node[inode].capacity))) { - assert((local_rr_graph->rr_node_route_inf[inode].target_flag > 0) - && (local_rr_graph->rr_node_route_inf[inode].target_flag <= local_rr_graph->rr_node[inode].capacity)); - } - } - - return; -} - -void mark_rr_graph_ends(t_rr_graph* local_rr_graph, - int inet) { - - /* Mark all the SINKs of this net as targets by setting their target flags * - * to the number of times the net must connect to each SINK. Note that * - * this number can occassionally be greater than 1 -- think of connecting * - * the same net to two inputs of an and-gate (and-gate inputs are logically * - * equivalent, so both will connect to the same SINK). */ - - int ipin, inode; - - for (ipin = 1; ipin < local_rr_graph->net_num_sinks[inet] + 1; ipin++) { - inode = local_rr_graph->net_rr_terminals[inet][ipin]; - if (inode == OPEN) { - continue; - } - local_rr_graph->rr_node_route_inf[inode].target_flag++; - assert((local_rr_graph->rr_node_route_inf[inode].target_flag > 0) - && (local_rr_graph->rr_node_route_inf[inode].target_flag <= local_rr_graph->rr_node[inode].capacity)); - } - - return; -} - -void invalidate_rr_graph_heap_entries(t_rr_graph* local_rr_graph, - int sink_node, int ipin_node) { - - /* Marks all the heap entries consisting of sink_node, where it was reached * - * via ipin_node, as invalid (OPEN). Used only by the breadth_first router * - * and even then only in rare circumstances. */ - - int i; - - for (i = 1; i < local_rr_graph->heap_tail; i++) { - if ((local_rr_graph->heap[i]->index == sink_node) - && (local_rr_graph->heap[i]->u.prev_node == ipin_node)) { - local_rr_graph->heap[i]->index = OPEN; /* Invalid. */ - } - } - - return; -} - -float get_rr_graph_rr_node_pack_intrinsic_cost(t_rr_graph* local_rr_graph, - int inode) { - /* This is a tie breaker to avoid using nodes with more edges whenever possible */ - float value; - value = local_rr_graph->rr_node[inode].pack_intrinsic_cost; - return value; -} - -/* Free rr_graph data structs */ -void free_rr_graph_rr_nodes(t_rr_graph* local_rr_graph) { - int i; - - /* Free edges and switches of all the rr_nodes */ - for (i = 0; i < local_rr_graph->num_rr_nodes; i++) { - my_free(local_rr_graph->rr_node[i].edges); - my_free(local_rr_graph->rr_node[i].switches); - my_free(local_rr_graph->rr_node[i].drive_rr_nodes); - } - /* Free the rr_node list */ - my_free(local_rr_graph->rr_node); - - return; -} - -void free_rr_graph_switch_inf(INOUTP t_rr_graph* local_rr_graph) { - - my_free(local_rr_graph->switch_inf); - - return; -} - -void free_rr_graph_route_structs(t_rr_graph* local_rr_graph) { /* [0..num_rr_nodes-1] */ - - /* Frees the extra information about each LL_rr_node that is needed only * - * during routing. */ - - free(local_rr_graph->rr_node_route_inf); - local_rr_graph->rr_node_route_inf = NULL; /* Mark as free */ - - return; -} - -static -void free_rr_graph_trace_data(t_rr_graph* local_rr_graph, - t_trace *tptr) { - - /* Puts the traceback structure pointed to by tptr on the free list. */ - - tptr->next = local_rr_graph->trace_free_head; - local_rr_graph->trace_free_head = tptr; -#ifdef DEBUG - local_rr_graph->num_trace_allocated--; -#endif -} - -void free_rr_graph_traceback(t_rr_graph* local_rr_graph, - int inet) { - - /* Puts the entire traceback (old routing) for this net on the free list * - * and sets the trace_head pointers etc. for the net to NULL. */ - - t_trace *tptr, *tempptr; - - if( local_rr_graph->trace_head == NULL) { - return; - } - - tptr = local_rr_graph->trace_head[inet]; - - while (tptr != NULL) { - tempptr = tptr->next; - free_rr_graph_trace_data(local_rr_graph, tptr); - tptr = tempptr; - } - - local_rr_graph->trace_head[inet] = NULL; - local_rr_graph->trace_tail[inet] = NULL; -} - -/* TODO: Fully free a rr_graph data struct */ -void free_rr_graph(t_rr_graph* local_rr_graph) { - /* Free the internal data structs one by one */ - free_rr_graph_rr_nodes(local_rr_graph); - free_rr_graph_switch_inf(local_rr_graph); - free_rr_graph_route_structs(local_rr_graph); - - return; -} - -void build_prev_node_list_rr_nodes(int LL_num_rr_nodes, - t_rr_node* LL_rr_node) { - int inode, iedge, to_node, cur; - int* cur_index = (int*)my_malloc(sizeof(int)*LL_num_rr_nodes); - - for (inode = 0; inode < LL_num_rr_nodes; inode++) { - /* Malloc */ - LL_rr_node[inode].num_drive_rr_nodes = LL_rr_node[inode].fan_in; - if (0 == LL_rr_node[inode].fan_in) { - continue; - } - LL_rr_node[inode].drive_rr_nodes = (t_rr_node**)my_malloc(sizeof(t_rr_node*) * LL_rr_node[inode].num_drive_rr_nodes); - LL_rr_node[inode].drive_switches = (int*)my_malloc(sizeof(int) * LL_rr_node[inode].num_drive_rr_nodes); - } - /* Initialize */ - for (inode = 0; inode < LL_num_rr_nodes; inode++) { - cur_index[inode] = 0; - for (iedge = 0; iedge < LL_rr_node[inode].num_drive_rr_nodes; iedge++) { - LL_rr_node[inode].drive_rr_nodes[iedge] = NULL; - LL_rr_node[inode].drive_switches[iedge] = -1; - } - } - /* Fill */ - for (inode = 0; inode < LL_num_rr_nodes; inode++) { - for (iedge = 0; iedge < LL_rr_node[inode].num_edges; iedge++) { - to_node = LL_rr_node[inode].edges[iedge]; - cur = cur_index[to_node]; - LL_rr_node[to_node].drive_rr_nodes[cur] = &(LL_rr_node[inode]); - LL_rr_node[to_node].drive_switches[cur] = LL_rr_node[inode].switches[iedge]; - /* Update cur_index[to_node]*/ - assert(NULL != LL_rr_node[to_node].drive_rr_nodes[cur]); - cur_index[to_node]++; - } - } - /* Check */ - for (inode = 0; inode < LL_num_rr_nodes; inode++) { - assert(cur_index[inode] == LL_rr_node[inode].num_drive_rr_nodes); - } - - return; -} - -/************************************************************************ - * Sort the drive_rr_nodes by node type and ptc_num - * 1. node type priority: (follow the index of t_rr_type - * SOURCE, SINK, IPIN, OPIN, CHANX, CHANY, INTRA_CLUSTER_EDGE, NUM_RR_TYPES - * 2. node ptc_num (feature number): from low to high - * The ptc_num only matters when two nodes have the same type - ***********************************************************************/ -void sort_rr_graph_drive_rr_nodes(int LL_num_rr_nodes, - t_rr_node* LL_rr_node) { - for (int inode = 0; inode < LL_num_rr_nodes; ++inode) { - /* Create a copy of the edges and switches of this node */ - std::vector sorted_drive_nodes; - std::vector sorted_drive_switches; - - /* Ensure a clean start */ - sorted_drive_nodes.clear(); - sorted_drive_switches.clear(); - - /* Build the vectors w.r.t. to the order of node_type and ptc_num */ - for (int i_from_node = 0; i_from_node < LL_rr_node[inode].num_drive_rr_nodes; ++i_from_node) { - /* For blank edges: directly push_back */ - if (0 == sorted_drive_nodes.size()) { - sorted_drive_nodes.push_back(LL_rr_node[inode].drive_rr_nodes[i_from_node]); - sorted_drive_switches.push_back(LL_rr_node[inode].drive_switches[i_from_node]); - continue; - } - - /* Start sorting since the edges are not empty */ - size_t insert_pos = sorted_drive_nodes.size(); /* the pos to insert. By default, it is the last element */ - for (size_t j_from_node = 0; j_from_node < sorted_drive_nodes.size(); ++j_from_node) { - /* Sort by node_type and ptc_num */ - if (LL_rr_node[inode].drive_rr_nodes[i_from_node]->type < sorted_drive_nodes[j_from_node]->type) { - /* iedge should be ahead of jedge */ - insert_pos = j_from_node; - break; /* least type should stay in the front of the vector */ - } else if (LL_rr_node[inode].drive_rr_nodes[i_from_node]->type == sorted_drive_nodes[j_from_node]->type) { - /* Special as track_ids vary, we consider the last track_ids for those node has the same type as inode */ - if (LL_rr_node[i_from_node].type == LL_rr_node[inode].type) { - if (get_track_rr_node_end_track_id(&(LL_rr_node[i_from_node])) - < get_track_rr_node_end_track_id(&(LL_rr_node[j_from_node])) ) { - insert_pos = j_from_node; - break; /* least type should stay in the front of the vector */ - } - /* Now a lower ptc_num will win */ - } else if (LL_rr_node[inode].drive_rr_nodes[i_from_node]->ptc_num < sorted_drive_nodes[j_from_node]->ptc_num) { - insert_pos = j_from_node; - break; /* least type should stay in the front of the vector */ - } - } - } - /* We find the position, inserted to the vector */ - sorted_drive_nodes.insert(sorted_drive_nodes.begin() + insert_pos, LL_rr_node[inode].drive_rr_nodes[i_from_node]); - sorted_drive_switches.insert(sorted_drive_switches.begin() + insert_pos, LL_rr_node[inode].drive_switches[i_from_node]); - } - - /* Overwrite the edges and switches with sorted numbers */ - for (size_t iedge = 0; iedge < sorted_drive_nodes.size(); ++iedge) { - LL_rr_node[inode].drive_rr_nodes[iedge] = sorted_drive_nodes[iedge]; - } - for (size_t iedge = 0; iedge < sorted_drive_switches.size(); ++iedge) { - LL_rr_node[inode].drive_switches[iedge] = sorted_drive_switches[iedge]; - } - } - - return; -} - -void alloc_and_load_prev_node_list_rr_graph_rr_nodes(t_rr_graph* local_rr_graph) { - build_prev_node_list_rr_nodes(local_rr_graph->num_rr_nodes, local_rr_graph->rr_node); - - return; -} - -void backannotate_rr_graph_routing_results_to_net_name(t_rr_graph* local_rr_graph) { - int inode, inet; - int next_node, iedge; - t_trace* tptr; - t_rr_type rr_type; - - /* 1st step: Set all the configurations to default. - * rr_nodes select edge[0] - */ - for (inode = 0; inode < local_rr_graph->num_rr_nodes; inode++) { - local_rr_graph->rr_node[inode].prev_node = OPEN; - /* set 0 if we want print all unused mux!!!*/ - local_rr_graph->rr_node[inode].prev_edge = OPEN; - /* Initial all the net_num*/ - local_rr_graph->rr_node[inode].net_num = OPEN; - local_rr_graph->rr_node[inode].vpack_net_num = OPEN; - } - /* - for (inode = 0; inode < local_rr_graph->num_rr_nodes; inode++) { - if (0 == local_rr_graph->rr_node[inode].num_edges) { - continue; - } - assert(0 < local_rr_graph->rr_node[inode].num_edges); - for (iedge = 0; iedge < local_rr_graph->rr_node[inode].num_edges; iedge++) { - jnode = local_rr_graph->rr_node[inode].edges[iedge]; - if (&(local_rr_graph->rr_node[inode]) == local_rr_graph->rr_node[jnode].drive_rr_nodes[0]) { - local_rr_graph->rr_node[jnode].prev_node = inode; - local_rr_graph->rr_node[jnode].prev_edge = iedge; - } - } - } - */ - /* 2nd step: With the help of trace, we back-annotate */ - for (inet = 0; inet < local_rr_graph->num_nets; inet++) { - /* - if (TRUE == local_rr_graph->net[inet]->is_global) { - continue; - } - */ - tptr = local_rr_graph->trace_head[inet]; - while (tptr != NULL) { - inode = tptr->index; - rr_type = local_rr_graph->rr_node[inode].type; - /* Net num */ - local_rr_graph->rr_node[inode].net_num = inet; - local_rr_graph->rr_node[inode].vpack_net_num = local_rr_graph->net_to_vpack_net_mapping[inet]; - /* assert(OPEN != local_rr_graph->rr_node[inode].net_num); */ - assert(OPEN != local_rr_graph->rr_node[inode].vpack_net_num); - switch (rr_type) { - case SINK: - /* Nothing should be done. This supposed to the end of a trace*/ - break; - case IPIN: - case CHANX: - case CHANY: - case OPIN: - case INTRA_CLUSTER_EDGE: - case SOURCE: - /* SINK(IO/Pad) is the end of a routing path. Should configure its prev_edge and prev_node*/ - /* We care the next rr_node, this one is driving, which we have to configure - */ - assert(NULL != tptr->next); - next_node = tptr->next->index; - assert((!(0 > next_node))&&(next_node < local_rr_graph->num_rr_nodes)); - /* Prev_node */ - local_rr_graph->rr_node[next_node].prev_node = inode; - /* Prev_edge */ - local_rr_graph->rr_node[next_node].prev_edge = OPEN; - for (iedge = 0; iedge < local_rr_graph->rr_node[inode].num_edges; iedge++) { - if (next_node == local_rr_graph->rr_node[inode].edges[iedge]) { - local_rr_graph->rr_node[next_node].prev_edge = iedge; - break; - } - } - assert(OPEN != local_rr_graph->rr_node[next_node].prev_edge); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid traceback element type.\n", - __FILE__, __LINE__); - exit(1); - } - tptr = tptr->next; - } - } - - return; -} - -int get_rr_graph_net_vpack_net_index(t_rr_graph* local_rr_graph, - int net_index) { - return local_rr_graph->net_to_vpack_net_mapping[net_index]; -} - -int get_rr_graph_net_index_with_vpack_net(t_rr_graph* local_rr_graph, - int vpack_net_index) { - int inet, ret; - int num_found = 0; - - for (inet = 0; inet < local_rr_graph->num_nets; inet++) { - if (vpack_net_index == local_rr_graph->net_to_vpack_net_mapping[inet]) { - num_found = 0; - ret = inet; - } - } - /* assert */ - assert ((0 == num_found ) || (1 == num_found)); - - return ret; -} - -void get_chan_rr_node_start_coordinate(t_rr_node* chan_rr_node, - int* x_start, int* y_start) { - assert ( (CHANX == chan_rr_node->type) - ||(CHANY == chan_rr_node->type)); - - switch (chan_rr_node->direction) { - case INC_DIRECTION: - (*x_start) = chan_rr_node->xlow; - (*y_start) = chan_rr_node->ylow; - break; - case DEC_DIRECTION: - (*x_start) = chan_rr_node->xhigh; - (*y_start) = chan_rr_node->yhigh; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of chan_rr_node!\n", - __FILE__, __LINE__); - - exit(1); - } - - return; -} - -void get_chan_rr_node_end_coordinate(t_rr_node* chan_rr_node, - int* x_end, int* y_end) { - assert ( (CHANX == chan_rr_node->type) - ||(CHANY == chan_rr_node->type)); - - switch (chan_rr_node->direction) { - case INC_DIRECTION: - (*x_end) = chan_rr_node->xhigh; - (*y_end) = chan_rr_node->yhigh; - break; - case DEC_DIRECTION: - (*x_end) = chan_rr_node->xlow; - (*y_end) = chan_rr_node->ylow; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of chan_rr_node!\n", - __FILE__, __LINE__); - - exit(1); - } - - return; -} - -int get_rr_node_wire_length(t_rr_node* src_rr_node) { - assert ( (CHANX == src_rr_node->type) - || (CHANY == src_rr_node->type)); - - return (abs(src_rr_node->xlow - src_rr_node->xhigh + src_rr_node->ylow - src_rr_node->yhigh) + 1); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_rr_graph_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_rr_graph_utils.h deleted file mode 100644 index f7326f439..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_rr_graph_utils.h +++ /dev/null @@ -1,115 +0,0 @@ -#ifndef FPGA_X2P_RR_GRAPH_UTILS_H -#define FPGA_X2P_RR_GRAPH_UTILS_H - -void init_rr_graph(INOUTP t_rr_graph* local_rr_graph); - -void alloc_rr_graph_net_rr_sources_and_sinks(t_rr_graph* local_rr_graph); - -void alloc_rr_graph_net_rr_terminals(t_rr_graph* local_rr_graph); - -void alloc_rr_graph_route_static_structs(t_rr_graph* local_rr_graph, - int heap_size); - -void load_rr_graph_chan_rr_indices(t_rr_graph* local_rr_graph, - INP int nodes_per_chan, INP int chan_len, - INP int num_chans, INP t_rr_type type, INP t_seg_details * seg_details, - INOUTP int *index); - -void alloc_and_load_rr_graph_rr_node(INOUTP t_rr_graph* local_rr_graph, - int local_num_rr_nodes); - -void alloc_and_load_rr_graph_rr_node_indices(t_rr_graph* local_rr_graph, - INP int nodes_per_chan, - INP int L_nx, INP int L_ny, t_grid_tile** L_grid, - INOUTP int *index, INP t_seg_details * seg_details); - -void alloc_and_load_rr_graph_switch_inf(INOUTP t_rr_graph* local_rr_graph, - int num_switch_inf, - INP t_switch_inf* switch_inf); - -void alloc_and_load_rr_graph_route_structs(t_rr_graph* local_rr_graph); - -t_trace* alloc_rr_graph_trace_data(t_rr_graph* local_rr_graph); - -t_heap * get_rr_graph_heap_head(t_rr_graph* local_rr_graph); - -t_linked_f_pointer* alloc_rr_graph_linked_f_pointer(t_rr_graph* local_rr_graph); - -t_heap * alloc_rr_graph_heap_data(t_rr_graph* local_rr_graph); - -void add_to_rr_graph_mod_list(t_rr_graph* local_rr_graph, - float *fptr); - -void empty_rr_graph_heap(t_rr_graph* local_rr_graph); - -void reset_rr_graph_rr_node_route_structs(t_rr_graph* local_rr_graph); - -t_trace* update_rr_graph_traceback(t_rr_graph* local_rr_graph, - t_heap *hptr, int inet); - -void reset_rr_graph_path_costs(t_rr_graph* local_rr_graph); - -void alloc_rr_graph_rr_indexed_data(t_rr_graph* local_rr_graph, int L_num_rr_indexed_data); - -float get_rr_graph_rr_cong_cost(t_rr_graph* local_rr_graph, - int rr_node_index); - - -void add_heap_node_to_rr_graph_heap(t_rr_graph* local_rr_graph, - t_heap *hptr); - -void add_node_to_rr_graph_heap(t_rr_graph* local_rr_graph, - int inode, float cost, int prev_node, int prev_edge, - float backward_path_cost, float R_upstream); - -void mark_rr_graph_sinks(t_rr_graph* local_rr_graph, - int inet, int start_isink, boolean* net_sink_routed); - -void mark_rr_graph_ends(t_rr_graph* local_rr_graph, - int inet); - -void invalidate_rr_graph_heap_entries(t_rr_graph* local_rr_graph, - int sink_node, int ipin_node); - -float get_rr_graph_rr_node_pack_intrinsic_cost(t_rr_graph* local_rr_graph, - int inode); - -void free_rr_graph_rr_nodes(t_rr_graph* local_rr_graph); - -void free_rr_graph_switch_inf(INOUTP t_rr_graph* local_rr_graph); - -void free_rr_graph_route_structs(t_rr_graph* local_rr_graph); - -void free_rr_graph(t_rr_graph* local_rr_graph); - -void free_rr_graph_heap_data(t_rr_graph* local_rr_graph, - t_heap *hptr); - -void free_rr_graph_traceback(t_rr_graph* local_rr_graph, - int inet); - -void build_prev_node_list_rr_nodes(int LL_num_rr_nodes, - t_rr_node* LL_rr_node); - -void sort_rr_graph_drive_rr_nodes(int LL_num_rr_nodes, - t_rr_node* LL_rr_node); - -void alloc_and_load_prev_node_list_rr_graph_rr_nodes(t_rr_graph* local_rr_graph); - -void backannotate_rr_graph_routing_results_to_net_name(t_rr_graph* local_rr_graph); - -int get_rr_graph_net_vpack_net_index(t_rr_graph* local_rr_graph, - int net_index); - -int get_rr_graph_net_index_with_vpack_net(t_rr_graph* local_rr_graph, - int vpack_net_index); - -void get_chan_rr_node_start_coordinate(t_rr_node* chan_rr_node, - int* x_start, int* y_start); - -void get_chan_rr_node_end_coordinate(t_rr_node* chan_rr_node, - int* x_end, int* y_end); - -int get_rr_node_wire_length(t_rr_node* src_rr_node); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c deleted file mode 100644 index a94dd1789..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ /dev/null @@ -1,1506 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "path_delay.h" -#include "stats.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_timing_utils.h" -#include "fpga_x2p_backannotate_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "verilog_api.h" -#include "fpga_x2p_unique_routing.h" - -#include "link_arch_circuit_lib.h" -#include "fpga_x2p_setup.h" - -/***** Subroutines Declarations *****/ -static -int map_pb_type_port_to_spice_model_ports(t_pb_type* cur_pb_type, - t_spice_model* cur_spice_model); - -static -void match_pb_types_spice_model_rec(t_pb_type* cur_pb_type, - int num_spice_model, - t_spice_model* spice_models); - -static -void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, - int num_spice_model, - t_spice_model* spice_models); - -static -void init_and_check_sram_inf(t_arch* arch); - -static -t_llist* check_and_add_one_global_port_to_llist(t_llist* old_head, - t_spice_model_port* candidate_port); - -static -void rec_stat_pb_type_keywords(t_pb_type* cur_pb_type, - int* num_keyword); - -static -void rec_add_pb_type_keywords_to_list(t_pb_type* cur_pb_type, - int* cur, - char** keywords, - char* prefix); - -static -int check_conflict_syntax_char_in_string(t_llist* LL_reserved_syntax_char_head, - char* str_to_check); - -static -void check_spice_model_name_conflict_syntax_char(t_arch Arch, - t_llist* LL_reseved_syntax_char_head); - -static -t_llist* init_llist_verilog_and_spice_syntax_char(); - -static -boolean is_verilog_and_spice_syntax_conflict_char(t_llist* LL_reserved_syntax_char_head, - char ref_char); - -static -int check_and_rename_logical_block_and_net_names(t_llist* LL_reserved_syntax_char_head, - char* circuit_name, - boolean rename_illegal_port, - int LL_num_logical_blocks, t_logical_block* LL_logical_block, - int LL_num_clb_nets, t_net* LL_clb_net, - int LL_num_vpack_nets, t_net* LL_vpack_net); - -/***** Subroutines *****/ - -/* Map (synchronize) pb_type ports to SPICE model ports - */ -static -int map_pb_type_port_to_spice_model_ports(t_pb_type* cur_pb_type, - t_spice_model* cur_spice_model) { - int iport; - t_port* cur_pb_type_port = NULL; - - /* Check */ - assert(NULL != cur_pb_type); - - /* Initialize each port */ - for (iport = 0; iport < cur_pb_type->num_ports; iport++) { - cur_pb_type->ports[iport].spice_model_port = NULL; - } - - /* Return if SPICE_MODEL is NULL */ - if (NULL == cur_spice_model) { - return 0; - } - - /* For each port, find a SPICE model port, which has the same name and port size */ - for (iport = 0; iport < cur_spice_model->num_port; iport++) { - cur_pb_type_port = - find_pb_type_port_match_spice_model_port(cur_pb_type, - &(cur_spice_model->ports[iport])); - /* Not every spice_model_port can find a mapped pb_type_port. - * Since a pb_type only includes necessary ports in technology mapping. - * ports for physical designs may be ignored ! - */ - if (NULL != cur_pb_type_port) { - cur_pb_type_port->spice_model_port = &(cur_spice_model->ports[iport]); - } - } - /* Although some spice_model_port may not have a corresponding pb_type_port - * but each pb_type_port should be mapped to a spice_model_port - */ - for (iport = 0; iport < cur_pb_type->num_ports; iport++) { - if (NULL == cur_pb_type->ports[iport].spice_model_port) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Pb_type(%s) Port(%s) cannot find a corresponding port in SPICE model(%s)\n", - __FILE__, __LINE__, cur_pb_type->name, cur_pb_type->ports[iport].name, - cur_spice_model->name); - exit(1); - } - } - - return cur_pb_type->num_ports; -} - -/* Find spice_model_name definition in pb_types - * Try to match the name with defined spice_models - */ -static -void match_pb_types_spice_model_rec(t_pb_type* cur_pb_type, - int num_spice_model, - t_spice_model* spice_models) { - int imode, ipb, jinterc; - - if (NULL == cur_pb_type) { - vpr_printf(TIO_MESSAGE_WARNING,"(File:%s,LINE[%d])cur_pb_type is null pointor!\n",__FILE__,__LINE__); - return; - } - - /* If there is a spice_model_name or refer to a physical pb type , this is a leaf node!*/ - if ((NULL != cur_pb_type->spice_model_name) || (NULL != cur_pb_type->physical_pb_type_name)) { - /* What annoys me is VPR create a sub pb_type for each lut which suppose to be a leaf node - * This may bring software convience but ruins SPICE modeling - */ - /* if this is not a physical pb_type, we do not care the spice model name and associated checking */ - if (NULL != cur_pb_type->physical_pb_type_name) { - vpr_printf(TIO_MESSAGE_INFO, "(File:%s,LINE[%d]) Bypass spice model checking for pb_type(%s)!\n", - __FILE__, __LINE__, cur_pb_type->name); - return; - } - /* Let's find a matched spice model!*/ - printf("INFO: matching cur_pb_type=%s with spice_model_name=%s...\n",cur_pb_type->name, cur_pb_type->spice_model_name); - assert(NULL == cur_pb_type->spice_model); - cur_pb_type->spice_model = find_name_matched_spice_model(cur_pb_type->spice_model_name, num_spice_model, spice_models); - if (NULL == cur_pb_type->spice_model) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Fail to find a defined SPICE model called %s, in pb_type(%s)!\n", - __FILE__, __LINE__, cur_pb_type->spice_model_name, cur_pb_type->name); - exit(1); - } - /* Map pb_type ports to SPICE model ports*/ - map_pb_type_port_to_spice_model_ports(cur_pb_type,cur_pb_type->spice_model); - return; - } - /* Traversal the hierarchy*/ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* Task 1: Find the interconnections and match the spice_model */ - for (jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { - assert(NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model); - /* If the spice_model_name is not defined, we use the default*/ - if (NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name) { - switch (cur_pb_type->modes[imode].interconnect[jinterc].type) { - case DIRECT_INTERC: - cur_pb_type->modes[imode].interconnect[jinterc].spice_model = - get_default_spice_model(SPICE_MODEL_WIRE,num_spice_model,spice_models); - break; - case COMPLETE_INTERC: - /* Special for Completer Interconnection: - * 1. The input number is 1, this infers a direct interconnection. - * 2. The input number is larger than 1, this infers multplexers - * according to interconnect[j].num_mux identify the number of input at this level - */ - if (0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) { - cur_pb_type->modes[imode].interconnect[jinterc].spice_model = - get_default_spice_model(SPICE_MODEL_WIRE,num_spice_model,spice_models); - } else { - cur_pb_type->modes[imode].interconnect[jinterc].spice_model = - get_default_spice_model(SPICE_MODEL_MUX,num_spice_model,spice_models); - if (NULL != cur_pb_type->modes[imode].interconnect[jinterc].loop_breaker_string) { - if (NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model->input_buffer) { - vpr_printf(TIO_MESSAGE_INFO,"Line[%d] Cannot disable an interconnect without input buffering", - cur_pb_type->modes[imode].interconnect[jinterc].line_num); - } - } - } - break; - case MUX_INTERC: - cur_pb_type->modes[imode].interconnect[jinterc].spice_model = - get_default_spice_model(SPICE_MODEL_MUX,num_spice_model,spice_models); - if (NULL != cur_pb_type->modes[imode].interconnect[jinterc].loop_breaker_string) { - if (NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model->input_buffer) { - vpr_printf(TIO_MESSAGE_INFO,"Line[%d] Cannot disable an interconnect without input buffering", - cur_pb_type->modes[imode].interconnect[jinterc].line_num); - } - } - break; - default: - break; - } - vpr_printf(TIO_MESSAGE_INFO,"INFO: Link a SPICE model (%s) for Interconnect (%s)!\n", - cur_pb_type->modes[imode].interconnect[jinterc].spice_model->name, cur_pb_type->modes[imode].interconnect[jinterc].name); - } else { - cur_pb_type->modes[imode].interconnect[jinterc].spice_model = - find_name_matched_spice_model(cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, num_spice_model, spice_models); - vpr_printf(TIO_MESSAGE_INFO,"INFO: Link a SPICE model (%s) for Interconnect (%s)!\n", - cur_pb_type->modes[imode].interconnect[jinterc].spice_model->name, cur_pb_type->modes[imode].interconnect[jinterc].name); - if (NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Fail to find a defined SPICE model called %s, in pb_type(%s)!\n", - __FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); - exit(1); - } - switch (cur_pb_type->modes[imode].interconnect[jinterc].type) { - case DIRECT_INTERC: - if (SPICE_MODEL_WIRE != cur_pb_type->modes[imode].interconnect[jinterc].spice_model->type) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Invalid type of matched SPICE model called %s, in pb_type(%s)! Sould be wire!\n", - __FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); - exit(1); - } - break; - case COMPLETE_INTERC: - if (0 == cur_pb_type->modes[imode].interconnect[jinterc].num_mux) { - if (SPICE_MODEL_WIRE != cur_pb_type->modes[imode].interconnect[jinterc].spice_model->type) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Invalid type of matched SPICE model called %s, in pb_type(%s)! Sould be wire!\n", - __FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); - exit(1); - } - } else { - if (SPICE_MODEL_MUX != cur_pb_type->modes[imode].interconnect[jinterc].spice_model->type) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Invalid type of matched SPICE model called %s, in pb_type(%s)! Sould be MUX!\n", - __FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); - exit(1); - } - } - if (NULL != cur_pb_type->modes[imode].interconnect[jinterc].loop_breaker_string) { - if (NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model->input_buffer) { - vpr_printf(TIO_MESSAGE_INFO,"Line[%d] Cannot disable an interconnect without input buffering", - cur_pb_type->modes[imode].interconnect[jinterc].line_num); - } - } - break; - case MUX_INTERC: - if (SPICE_MODEL_MUX != cur_pb_type->modes[imode].interconnect[jinterc].spice_model->type) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Invalid type of matched SPICE model called %s, in pb_type(%s)! Sould be MUX!\n", - __FILE__, __LINE__, cur_pb_type->modes[imode].interconnect[jinterc].spice_model_name, cur_pb_type->name); - exit(1); - } - if (NULL != cur_pb_type->modes[imode].interconnect[jinterc].loop_breaker_string) { - if (NULL == cur_pb_type->modes[imode].interconnect[jinterc].spice_model->input_buffer) { - vpr_printf(TIO_MESSAGE_INFO,"Line[%d] Cannot disable an interconnect without input buffering", - cur_pb_type->modes[imode].interconnect[jinterc].line_num); - } - } - break; - default: - break; - } - } - } - /* Task 2: Find the child pb_type, do matching recursively */ - //if (1 == cur_pb_type->modes[imode].define_spice_model) { - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - match_pb_types_spice_model_rec(&cur_pb_type->modes[imode].pb_type_children[ipb], - num_spice_model, - spice_models); - } - //} - } - return; -} - -static -void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, - int num_spice_model, - t_spice_model* spice_models) { - /* If cur_sram_inf_orgz is not initialized, do nothing */ - if (NULL == cur_sram_inf_orgz) { - return; - } - - /* For SRAM */ - if (NULL == cur_sram_inf_orgz->spice_model_name) { - cur_sram_inf_orgz->spice_model = get_default_spice_model(SPICE_MODEL_SRAM, - num_spice_model, - spice_models); - } else { - cur_sram_inf_orgz->spice_model = - find_name_matched_spice_model(cur_sram_inf_orgz->spice_model_name, - num_spice_model, - spice_models); - } - - if (NULL == cur_sram_inf_orgz->spice_model) { - if (NULL == cur_sram_inf_orgz->spice_model_name) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) Cannot find any SRAM spice model!\n", - __FILE__ ,__LINE__); - exit(1); - } else { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Invalid SPICE model name(%s) of SRAM is undefined in SPICE models!\n", - __FILE__ ,__LINE__, cur_sram_inf_orgz->spice_model_name); - exit(1); - } - } - - /* Check the type of SRAM_SPICE_MODEL */ - switch (cur_sram_inf_orgz->type) { - case SPICE_SRAM_STANDALONE: - vpr_printf(TIO_MESSAGE_INFO, "INFO: Checking if SRAM spice model fit standalone organization...\n"); - if (SPICE_MODEL_SRAM != cur_sram_inf_orgz->spice_model->type) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Standalone SRAM organization requires a SPICE model(type=sram)!\n", - __FILE__, __LINE__); - exit(1); - } - /* TODO: check SRAM ports */ - check_sram_spice_model_ports(cur_sram_inf_orgz->spice_model, FALSE); - break; - case SPICE_SRAM_SCAN_CHAIN: - vpr_printf(TIO_MESSAGE_INFO, "INFO: Checking if SRAM spice model fit scan-chain organization...\n"); - if (SPICE_MODEL_CCFF != cur_sram_inf_orgz->spice_model->type) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Scan-chain SRAM organization requires a SPICE model(type=sff)!\n", - __FILE__, __LINE__); - exit(1); - } - /* TODO: check Scan-chain Flip-flop ports */ - check_ff_spice_model_ports(cur_sram_inf_orgz->spice_model, TRUE); - /* TODO: RRAM Scan-chain is not supported yet. Now just forbidden this option */ - if (SPICE_MODEL_DESIGN_RRAM == cur_sram_inf_orgz->spice_model->design_tech) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) RRAM-based Scan-chain Flip-flop has not been supported yet!\n", - __FILE__, __LINE__); - exit(1); - } - break; - case SPICE_SRAM_MEMORY_BANK: - vpr_printf(TIO_MESSAGE_INFO, "INFO: Checking if SRAM spice model fit memory-bank organization...\n"); - if (SPICE_MODEL_SRAM != cur_sram_inf_orgz->spice_model->type) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Memory-bank SRAM organization requires a SPICE model(type=sram)!\n", - __FILE__, __LINE__); - exit(1); - } - /* TODO: check if this one has bit lines and word lines */ - check_sram_spice_model_ports(cur_sram_inf_orgz->spice_model, TRUE); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Invalid SRAM organization type!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -static -void init_and_check_sram_inf(t_arch* arch) { - /* We have two branches: - * 1. SPICE SRAM organization information - * 2. Verilog SRAM organization information - */ - init_and_check_one_sram_inf_orgz(arch->sram_inf.spice_sram_inf_orgz, - arch->spice->num_spice_model, - arch->spice->spice_models); - - init_and_check_one_sram_inf_orgz(arch->sram_inf.verilog_sram_inf_orgz, - arch->spice->num_spice_model, - arch->spice->spice_models); - - - return; -} - -/* Initialize and check spice models in architecture - * Tasks: - * 1. Link the spice model defined in pb_types and routing switches - * 2. Add default spice model (MUX) if needed - */ -void init_check_arch_spice_models(t_arch* arch, - t_det_routing_arch* routing_arch) { - int i, iport; - - vpr_printf(TIO_MESSAGE_INFO,"Initializing and checking SPICE models...\n"); - /* Check Spice models first*/ - assert(NULL != arch); - assert(NULL != arch->spice); - if ((0 == arch->spice->num_spice_model)||(0 > arch->spice->num_spice_model)) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])SPICE models are not defined! Miss this part in architecture file.\n",__FILE__,__LINE__); - exit(1); - } - assert(NULL != arch->spice->spice_models); - - /* Find default spice model*/ - /* MUX */ - if (NULL == get_default_spice_model(SPICE_MODEL_MUX, - arch->spice->num_spice_model, - arch->spice->spice_models)) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Fail to find the default MUX SPICE Model! Should define it in architecture file\n",__FILE__,__LINE__); - exit(1); - } - - /* Channel Wire */ - if (NULL == get_default_spice_model(SPICE_MODEL_CHAN_WIRE, - arch->spice->num_spice_model, - arch->spice->spice_models)) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Fail to find the default Channel Wire SPICE Model! Should define it in architecture file\n",__FILE__,__LINE__); - exit(1); - } - - /* Wire */ - if (NULL == get_default_spice_model(SPICE_MODEL_WIRE, - arch->spice->num_spice_model, - arch->spice->spice_models)) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Fail to find the default Wire SPICE Model! Should define it in architecture file\n",__FILE__,__LINE__); - exit(1); - } - - /* Link the input/output buffer spice models to higher level spice models - * Configure (fill information) the input/output buffers of high level spice models */ - config_spice_model_input_output_buffers_pass_gate(arch->spice->num_spice_model, - arch->spice->spice_models); - - /* Find inversion spice_model for ports */ - config_spice_model_port_inv_spice_model(arch->spice->num_spice_model, - arch->spice->spice_models); - - /* 1. Link the spice model defined in pb_types and routing switches */ - /* Step A: Check routing switches, connection blocks*/ - if ((0 == arch->num_cb_switch)||(0 > arch->num_cb_switch)) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) Define Switches for Connection Blocks is mandatory in SPICE model support! Miss this part in architecture file.\n",__FILE__,__LINE__); - exit(1); - } - - for (i = 0; i < arch->num_cb_switch; i++) { - arch->cb_switches[i].spice_model = - find_name_matched_spice_model(arch->cb_switches[i].spice_model_name, - arch->spice->num_spice_model, - arch->spice->spice_models); - if (NULL == arch->cb_switches[i].spice_model) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Invalid SPICE model name(%s) of Switch(%s) is undefined in SPICE models!\n",__FILE__ ,__LINE__, arch->cb_switches[i].spice_model_name, arch->cb_switches[i].name); - exit(1); - } - /* Check the spice model structure is matched with the structure in switch_inf */ - if (FALSE == check_spice_model_structure_match_switch_inf(arch->cb_switches[i])) { - exit(1); - } - } - - /* Step B: Check switch list: Switch Box*/ - if ((0 == arch->num_switches)||(0 > arch->num_switches)) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) Define Switches for Switch Boxes is mandatory in SPICE model support! Miss this part in architecture file.\n",__FILE__,__LINE__); - exit(1); - } - - for (i = 0; i < arch->num_switches; i++) { - arch->Switches[i].spice_model = - find_name_matched_spice_model(arch->Switches[i].spice_model_name, - arch->spice->num_spice_model, - arch->spice->spice_models); - if (NULL == arch->Switches[i].spice_model) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Invalid SPICE model name(%s) of Switch(%s) is undefined in SPICE models!\n",__FILE__ ,__LINE__, arch->Switches[i].spice_model_name, arch->Switches[i].name); - exit(1); - } - /* Check the spice model structure is matched with the structure in switch_inf */ - if (FALSE == check_spice_model_structure_match_switch_inf(arch->Switches[i])) { - exit(1); - } - } - - /* Update the switches in detailed routing architecture settings*/ - for (i = 0; i < routing_arch->num_switch; i++) { - if (NULL == switch_inf[i].spice_model_name) { - switch_inf[i].spice_model = get_default_spice_model(SPICE_MODEL_MUX, - arch->spice->num_spice_model, - arch->spice->spice_models); - continue; - } - switch_inf[i].spice_model = - find_name_matched_spice_model(switch_inf[i].spice_model_name, - arch->spice->num_spice_model, - arch->spice->spice_models); - if (NULL == switch_inf[i].spice_model) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Invalid SPICE model name(%s) of Switch(%s) is undefined in SPICE models!\n",__FILE__ ,__LINE__, switch_inf[i].spice_model_name, switch_inf[i].name); - exit(1); - } - } - - /* Step C: Find SRAM Model*/ - init_and_check_sram_inf(arch); - - /* Step D: Find the segment spice_model*/ - for (i = 0; i < arch->num_segments; i++) { - if (NULL == arch->Segments[i].spice_model_name) { - arch->Segments[i].spice_model = - get_default_spice_model(SPICE_MODEL_CHAN_WIRE, - arch->spice->num_spice_model, - arch->spice->spice_models); - continue; - } else { - arch->Segments[i].spice_model = - find_name_matched_spice_model(arch->Segments[i].spice_model_name, - arch->spice->num_spice_model, - arch->spice->spice_models); - } - if (NULL == arch->Segments[i].spice_model) { - vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid SPICE model name(%s) of Segment(Length:%d) is undefined in SPICE models!\n", - __FILE__ ,__LINE__, - arch->Segments[i].spice_model_name, - arch->Segments[i].length); - exit(1); - } else if (SPICE_MODEL_CHAN_WIRE != arch->Segments[i].spice_model->type) { - vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid SPICE model(%s) type of Segment(Length:%d)! Should be chan_wire!\n", - __FILE__ , __LINE__, - arch->Segments[i].spice_model_name, - arch->Segments[i].length); - exit(1); - } - } - - /* Step E: Direct connections between CLBs */ - for (i = 0; i < arch->num_directs; i++) { - if (NULL == arch->Directs[i].spice_model_name) { - arch->Directs[i].spice_model = - get_default_spice_model(SPICE_MODEL_WIRE, - arch->spice->num_spice_model, - arch->spice->spice_models); - } else { - arch->Directs[i].spice_model = - find_name_matched_spice_model(arch->Directs[i].spice_model_name, - arch->spice->num_spice_model, - arch->spice->spice_models); - } - /* Check SPICE model type */ - if (NULL == arch->Directs[i].spice_model) { - vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid SPICE model name(%s) of CLB to CLB Direct Connection (name=%s) is undefined in SPICE models!\n", - __FILE__ ,__LINE__, - arch->Directs[i].spice_model_name, - arch->Directs[i].name); - exit(1); - } else if (SPICE_MODEL_WIRE != arch->Directs[i].spice_model->type) { - vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid SPICE model(%s) type of CLB to CLB Direct Connection (name=%s)! Should be chan_wire!\n", - __FILE__ , __LINE__, - arch->Directs[i].spice_model_name, - arch->Directs[i].name); - exit(1); - } - /* Copy it to clb2clb_directs */ - clb2clb_direct[i].spice_model = arch->Directs[i].spice_model; - } - - /* 2. Search Complex Blocks (Pb_Types), Link spice_model according to the spice_model_name*/ - for (i = 0; i < num_types; i++) { - if (type_descriptors[i].pb_type) { - match_pb_types_spice_model_rec(type_descriptors[i].pb_type, - arch->spice->num_spice_model, - arch->spice->spice_models); - } - } - - /* 3. Initial grid_index_low/high for each spice_model */ - for (i = 0; i < arch->spice->num_spice_model; i++) { - alloc_spice_model_grid_index_low_high(&(arch->spice->spice_models[i])); - alloc_spice_model_routing_index_low_high(&(arch->spice->spice_models[i])); - } - /* 4. zero the counter of each spice_model */ - zero_spice_models_cnt(arch->spice->num_spice_model, arch->spice->spice_models); - /* 5. zero all index low high */ - /* - zero_spice_model_grid_index_low_high(arch->spice->num_spice_model, arch->spice->spice_models); - zero_spice_models_routing_index_low_high(arch->spice->num_spice_model, arch->spice->spice_models); - */ - - /* 6. Check each port of a spice model and create link to another spice model */ - for (i = 0; i < arch->spice->num_spice_model; i++) { - for (iport = 0; iport < arch->spice->spice_models[i].num_port; iport++) { - /* Set to NULL pointor first */ - arch->spice->spice_models[i].ports[iport].spice_model = NULL; - if (NULL != arch->spice->spice_models[i].ports[iport].spice_model_name) { - arch->spice->spice_models[i].ports[iport].spice_model = - find_name_matched_spice_model(arch->spice->spice_models[i].ports[iport].spice_model_name, - arch->spice->num_spice_model, - arch->spice->spice_models); - } - } - } - - /* 7. Create timing graph for spice models */ - for (i = 0; i < arch->spice->num_spice_model; i++) { - /* See if we need a timing graph */ - if (0 == arch->spice->spice_models[i].num_delay_info) { - continue; - } - annotate_spice_model_timing(&(arch->spice->spice_models[i])); - } - - return; -} - -/* Recursively traverse pb_type graph and mark idle mode - * Only one idle mode is allowed under each pb_type - */ -static -void rec_identify_pb_type_idle_mode(t_pb_type* cur_pb_type) { - int imode, ichild, idle_mode_idx; - - /* Do it only when we have modes */ - if ( 0 < cur_pb_type->num_modes) { - /* Find idle mode index */ - idle_mode_idx = find_pb_type_idle_mode_index(*cur_pb_type); - cur_pb_type->modes[idle_mode_idx].define_idle_mode = TRUE; - return; - } - - /* Traverse all the modes for identifying idle mode */ - for (imode = 0; cur_pb_type->num_modes; imode++) { - /* Check each pb_type_child */ - for (ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ichild++) { - rec_identify_pb_type_idle_mode(&(cur_pb_type->modes[imode].pb_type_children[ichild])); - } - } - - return; -} - - -/* Recursively traverse pb_type graph and mark idle and physical mode - * Only one idle mode and one physical mode is allowed under each pb_type - * In particular, a physical mode should appear only when its parent is a physical mode. - */ -static -void rec_identify_pb_type_phy_mode(t_pb_type* cur_pb_type) { - int imode, ichild, phy_mode_idx; - - /* Only try to find physical mode when parent is a physical mode or this is the top cur_pb_type! */ - if (FALSE == is_primitive_pb_type(cur_pb_type)) { - if ((NULL == cur_pb_type->parent_mode) - || (TRUE == cur_pb_type->parent_mode->define_physical_mode)) { - /* Find physical mode index */ - phy_mode_idx = find_pb_type_physical_mode_index(*cur_pb_type); - cur_pb_type->modes[phy_mode_idx].define_physical_mode = TRUE; - } else { - /* The parent must not be a physical mode*/ - assert (FALSE == cur_pb_type->parent_mode->define_physical_mode); - phy_mode_idx = -1; - /* Traverse all the modes for identifying idle mode */ - for (imode = 0; cur_pb_type->num_modes; imode++) { - cur_pb_type->modes[imode].define_physical_mode = FALSE; - } - } - return; - } - - /* Traverse all the modes for identifying idle mode */ - for (imode = 0; cur_pb_type->num_modes; imode++) { - /* Check each pb_type_child */ - for (ichild = 0; ichild < cur_pb_type->modes[imode].num_pb_type_children; ichild++) { - rec_identify_pb_type_phy_mode(&(cur_pb_type->modes[imode].pb_type_children[ichild])); - } - } - - return; -} - -/* Identify physical mode of pb_types in each defined complex block */ -static -void init_check_arch_pb_type_idle_and_phy_mode() { - int itype; - - for (itype = 0; itype < num_types; itype++) { - if (type_descriptors[itype].pb_type) { - rec_identify_pb_type_idle_mode(type_descriptors[itype].pb_type); - rec_identify_pb_type_phy_mode(type_descriptors[itype].pb_type); - } - } - - return; -} - -/* Statistics reserved names in pb_types to the list*/ -static -void rec_stat_pb_type_keywords(t_pb_type* cur_pb_type, - int* num_keyword) { - int imode, ipb, jpb; - - assert((0 == (*num_keyword))||(0 < (*num_keyword))); - assert(NULL != num_keyword); - assert(NULL != cur_pb_type); - - for (ipb = 0; ipb < cur_pb_type->num_pb; ipb++) { - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* pb_type_name[num_pb]_mode[mode_name]*/ - (*num_keyword) += 1; - for (jpb = 0; jpb < cur_pb_type->modes[imode].num_pb_type_children; jpb++) { - if (NULL == cur_pb_type->modes[imode].pb_type_children[jpb].spice_model) { - rec_stat_pb_type_keywords(&(cur_pb_type->modes[imode].pb_type_children[jpb]), - num_keyword); - } - } - } - } - - return; -} - -/* Add reserved names in pb_types to the list*/ -static -void rec_add_pb_type_keywords_to_list(t_pb_type* cur_pb_type, - int* cur, - char** keywords, - char* prefix) { - int imode, ipb, jpb; - char* formatted_prefix = format_spice_node_prefix(prefix); - char* pass_on_prefix = NULL; - - assert(NULL != cur); - assert((0 == (*cur))||(0 < (*cur))); - assert(NULL != keywords); - assert(NULL != cur_pb_type); - - /* pb_type_name[num_pb]_mode[mode_name]*/ - // num_keyword += cur_pb_type->num_pb * cur_pb_type->num_modes; - for (ipb = 0; ipb < cur_pb_type->num_pb; ipb++) { - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - keywords[(*cur)] = (char*)my_malloc(sizeof(char)* - (strlen(formatted_prefix) + strlen(cur_pb_type->name) + 1 + strlen(my_itoa(ipb)) + 7 - + strlen(cur_pb_type->modes[imode].name) + 2)); - sprintf(keywords[(*cur)], "%s%s[%d]_mode[%s]", formatted_prefix, cur_pb_type->name, ipb, cur_pb_type->modes[imode].name); - pass_on_prefix = my_strdup(keywords[(*cur)]); - (*cur)++; - for (jpb = 0; jpb < cur_pb_type->modes[imode].num_pb_type_children; jpb++) { - if (NULL == cur_pb_type->modes[imode].pb_type_children[jpb].spice_model) { - rec_add_pb_type_keywords_to_list(&(cur_pb_type->modes[imode].pb_type_children[jpb]), - cur, keywords, pass_on_prefix); - } - } - my_free(pass_on_prefix); - } - } - - my_free(formatted_prefix); - - return; -} - -/* This function checks conflicts between - * 1. SPICE model names and reserved sub-circuit names - */ -void check_keywords_conflict(t_arch Arch) { - int num_keyword = 0; - char**keywords; - int conflict = 0; - - int num_keyword_per_grid = 0; - int cur, iseg, imodel, i, iport; - int ix, iy, iz; - t_pb_type* cur_pb_type = NULL; - char* prefix = NULL; - t_llist* temp = NULL; - t_spice_model_port* cur_global_port = NULL; - - /* Generate the list of reserved names */ - num_keyword = 0; - keywords = NULL; - - /* Reserved names: grid names */ - /* Reserved names: pb_type names */ - for (ix = 0; ix < (nx + 2); ix++) { - for (iy = 0; iy < (ny + 2); iy++) { - /* by_pass the empty */ - if (EMPTY_TYPE != grid[ix][iy].type) { - num_keyword += 1; /* plus grid[ix][iy]*/ - for (iz = 0; iz < grid[ix][iy].type->capacity; iz++) { - num_keyword_per_grid = 0; - /* Per grid, type_descriptor.name[i]*/ - /* Go recursive pb_graph_node, until the leaf which defines a spice_model */ - cur_pb_type = grid[ix][iy].type->pb_type; - rec_stat_pb_type_keywords(cur_pb_type, &num_keyword_per_grid); - num_keyword += num_keyword_per_grid; - } - } - } - } - - /* Reserved names: switch boxes, connection boxes, channels */ - /* Channels -X */ - num_keyword += (ny+1) * nx; - /* Channels -Y */ - num_keyword += (nx+1) * ny; - /* Switch Boxes */ - /* sb[ix][iy]*/ - num_keyword += (nx + 1)*(ny + 1); - /* Connection Boxes */ - /* cbx[ix][iy] */ - num_keyword += (ny+1) * nx; - /* cby[ix][iy] */ - num_keyword += (nx+1) * ny; - - /* internal names: inv, buf, cpt, vpr_nmos, vpr_pmos, wire_segments */ - num_keyword += 5 + Arch.num_segments; - - /* Include keywords of global ports */ - temp = global_ports_head; - while (NULL != temp) { - cur_global_port = (t_spice_model_port*)(temp->dptr); - num_keyword += cur_global_port->size; - temp = temp->next; - } - - /* Malloc */ - keywords = (char**)my_malloc(sizeof(char*)*num_keyword); - - /* Add reserved names to the list */ - cur = 0; - for (i = 0; i < num_keyword; i++) { - keywords[i] = NULL; - } - /* Include keywords of global ports */ - temp = global_ports_head; - while (NULL != temp) { - cur_global_port = (t_spice_model_port*)(temp->dptr); - for (iport = 0; iport < cur_global_port->size; iport++) { - keywords[cur] = (char*)my_malloc(sizeof(char)* - (strlen(cur_global_port->prefix) + 2 + strlen(my_itoa(iport)) + 1)); - sprintf(keywords[cur], "%s[%d]", cur_global_port->prefix, iport); - cur++; - } - temp = temp->next; - } - /* internal names: inv, buf, cpt, vpr_nmos, vpr_pmos, wire_segments */ - keywords[cur] = "inv"; cur++; - keywords[cur] = "buf"; cur++; - keywords[cur] = "cpt"; cur++; - keywords[cur] = "vpr_nmos"; cur++; - keywords[cur] = "vpr_pmos"; cur++; - for (iseg = 0; iseg < Arch.num_segments; iseg++) { - keywords[cur] = (char*)my_malloc(sizeof(char)* - (strlen(Arch.Segments[iseg].spice_model->name) + 4 + strlen(my_itoa(iseg)) + 1)); - sprintf(keywords[cur], "%s_seg%d", Arch.Segments[iseg].spice_model->name, iseg); - cur++; - } - /* Reserved names: switch boxes, connection boxes, channels */ - /* Channels -X */ - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - /* chanx[ix][iy]*/ - keywords[cur] = (char*)my_malloc(sizeof(char)* (6 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 2)); - sprintf(keywords[cur], "chanx[%d][%d]", ix, iy); - cur++; - } - } - /* Channels -Y */ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - /* chany[ix][iy]*/ - keywords[cur] = (char*)my_malloc(sizeof(char)* (6 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 2)); - sprintf(keywords[cur], "chany[%d][%d]", ix, iy); - cur++; - } - } - /* Connection Box */ - /* cbx[ix][iy]*/ - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - /* cbx[ix][iy]*/ - keywords[cur] = (char*)my_malloc(sizeof(char)* (4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 2)); - sprintf(keywords[cur], "cbx[%d][%d]", ix, iy); - cur++; - } - } - /* cby[ix][iy]*/ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - /* cby[ix][iy]*/ - keywords[cur] = (char*)my_malloc(sizeof(char)* (4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 2)); - sprintf(keywords[cur], "cby[%d][%d]", ix, iy); - cur++; - } - } - /* Switch Boxes */ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 0; iy < (ny + 1); iy++) { - /* sb[ix][iy]*/ - keywords[cur] = (char*)my_malloc(sizeof(char)* (3 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 2)); - sprintf(keywords[cur], "sb[%d][%d]", ix, iy); - cur++; - } - } - /* Reserved names: grid names */ - /* Reserved names: pb_type names */ - for (ix = 0; ix < (nx + 2); ix++) { - for (iy = 0; iy < (ny + 2); iy++) { - /* by_pass the empty */ - if (EMPTY_TYPE != grid[ix][iy].type) { - prefix = (char*)my_malloc(sizeof(char)* (5 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 2)); - sprintf(prefix, "grid[%d][%d]", ix, iy); - /* plus grid[ix][iy]*/ - keywords[cur] = my_strdup(prefix); - cur++; - for (iz = 0; iz < grid[ix][iy].type->capacity; iz++) { - /* Per grid, type_descriptor.name[i]*/ - /* Go recursive pb_graph_node, until the leaf which defines a spice_model */ - cur_pb_type = grid[ix][iy].type->pb_type; - rec_add_pb_type_keywords_to_list(cur_pb_type, &cur, keywords, prefix); - } - my_free(prefix); - } - } - } - /* assert */ - assert(cur == num_keyword); - - /* Check the keywords conflicted with defined spice_model names */ - for (imodel = 0; imodel < Arch.spice->num_spice_model; imodel++) { - for (i = 0; i < num_keyword; i++) { - if (0 == strcmp(Arch.spice->spice_models[imodel].name, keywords[i])) { - vpr_printf(TIO_MESSAGE_ERROR, "Keyword Conflicted! Spice Model Name: %s\n", keywords[i]); - conflict++; - } - } - } - - assert((0 == conflict)||(0 < conflict)); - if (0 < conflict) { - vpr_printf(TIO_MESSAGE_ERROR, "Found %d conflicted keywords!\n", conflict); - exit(1); - } - - /* Free the memory of the keywords after the checking */ - for (i = 0 ; cur < num_keyword ; i++) { - my_free(keywords[cur]); - } - - return; -} - -/* Need to check if we already a global port with the same name in the list! - * This could happen where two spice models share the same global port - * If this is a new name in the list, we add this global port. - * Otherwise, we do nothing - */ -static -t_llist* check_and_add_one_global_port_to_llist(t_llist* old_head, - t_spice_model_port* candidate_port) { - t_llist* temp = old_head; - t_llist* new_head = NULL; - - while (NULL != temp) { - if (0 == strcmp(candidate_port->prefix, - ((t_spice_model_port*)(temp->dptr))->prefix) ) { - /* Find a same global port name, we do nothing, return directly */ - return old_head; - } - /* Go to the next */ - temp = temp->next; - } - - new_head = insert_llist_node_before_head(old_head); - new_head->dptr = (void*)(candidate_port); - - return new_head; -} - -/* Create and Initialize the global ports - * Search all the ports defined under spice_models - * if a port is defined to be global, we add its pointer to the linked list - */ -static -t_llist* init_llist_global_ports(t_spice* spice) { - int imodel, iport; - t_llist* head = NULL; - - /* Traverse all the spice models */ - for (imodel = 0; imodel < spice->num_spice_model; imodel++) { - for (iport = 0; iport < spice->spice_models[imodel].num_port; iport++) { - if (TRUE == spice->spice_models[imodel].ports[iport].is_global) { - /* Check each global signal has non conflicted flags : - * At most one of the properties: is_config_enable, is_set and is_reset, can be true */ - assert(2 > (spice->spice_models[imodel].ports[iport].is_set - + spice->spice_models[imodel].ports[iport].is_reset - + spice->spice_models[imodel].ports[iport].is_config_enable)); - /* Add to linked list, the organization will be first-in last-out - * First element would be the tail of linked list - */ - head = check_and_add_one_global_port_to_llist(head,&(spice->spice_models[imodel].ports[iport])); - } - } - } - - return head; -} - -/* Check how many conflicts of syntax char in a string */ -static -int check_conflict_syntax_char_in_string(t_llist* LL_reserved_syntax_char_head, - char* str_to_check) { - int num_conflicts = 0; - int len_str_to_check = strlen(str_to_check); - int ichar = 0; - - for (ichar = 0; ichar < len_str_to_check; ichar++) { - if (TRUE == is_verilog_and_spice_syntax_conflict_char(LL_reserved_syntax_char_head, - str_to_check[ichar])) { - /* Print warning */ - vpr_printf(TIO_MESSAGE_ERROR, "String (%s) contains conflicted chars[%c] which is not allowed by Verilog and SPICE!\n", - str_to_check, str_to_check[ichar]); - num_conflicts++; - } - } - - return num_conflicts; -} - -/* Check if each spice_model name contains any syntax char, which is reseved by SPICE or Verilog */ -static -void check_spice_model_name_conflict_syntax_char(t_arch Arch, - t_llist* LL_reserved_syntax_char_head) { - int imodel, iport; - int num_conflicts = 0; - - /* Check spice_model one by one */ - for (imodel = 0; imodel < Arch.spice->num_spice_model; imodel++) { - /* Check spice_model->name */ - num_conflicts += check_conflict_syntax_char_in_string(LL_reserved_syntax_char_head, - Arch.spice->spice_models[imodel].name); - /* Check spice_model->prefix */ - num_conflicts += check_conflict_syntax_char_in_string(LL_reserved_syntax_char_head, - Arch.spice->spice_models[imodel].prefix); - /* Check each port name */ - for (iport = 0; iport < Arch.spice->spice_models[imodel].num_port; iport++) { - num_conflicts += check_conflict_syntax_char_in_string(LL_reserved_syntax_char_head, - Arch.spice->spice_models[imodel].ports[iport].prefix); - } - } - - if (0 < num_conflicts) { - /* Print warning */ - vpr_printf(TIO_MESSAGE_ERROR, "Fail in syntax char checking, conflicts have been detected!\n"); - exit(1); - } - - return; -} - -/* Initialize a linked-list for syntax char of Verilog and SPICE */ -static -t_llist* init_llist_verilog_and_spice_syntax_char() { - t_llist* new_head = NULL; - int num_syntax_chars = 0; - char* syntax_chars = NULL; - t_reserved_syntax_char* new_syntax_char = NULL; - int ichar = 0; - - syntax_chars = my_strdup(".,:;\'\"+-<>()[]{}!@#$%^&*~`?/"); - num_syntax_chars = strlen(syntax_chars); - - /* Create a new element */ - for (ichar = 0; ichar < num_syntax_chars; ichar++) { - new_syntax_char = (t_reserved_syntax_char*)(my_malloc(sizeof(t_reserved_syntax_char))); - new_head = insert_llist_node_before_head(new_head); - new_head->dptr = (void*)new_syntax_char; - init_reserved_syntax_char(new_syntax_char, syntax_chars[ichar], TRUE, TRUE); - } - - return new_head; -} - -/* Check if a char violates the syntax of Verilog and SPICE */ -static -boolean is_verilog_and_spice_syntax_conflict_char(t_llist* LL_reserved_syntax_char_head, - char ref_char) { - boolean syntax_conflict = FALSE; - t_llist* temp = LL_reserved_syntax_char_head; - t_reserved_syntax_char* cur_syntax_char = NULL; - - /* Search the conflict linked list ? */ - while (NULL != temp) { - cur_syntax_char = (t_reserved_syntax_char*)(temp->dptr); - if (ref_char == cur_syntax_char->syntax_char) { - syntax_conflict = TRUE; - break; - } - /* go to the next */ - temp = temp->next; - } - - return syntax_conflict; -} - -/* Check and rename the name of each IO logical block - * if the current name violates syntax of SPICE or Verilog - */ -static -int check_and_rename_logical_block_and_net_names(t_llist* LL_reserved_syntax_char_head, - char* circuit_name, - boolean rename_illegal_port, - int LL_num_logical_blocks, t_logical_block* LL_logical_block, - int LL_num_clb_nets, t_net* LL_clb_net, - int LL_num_vpack_nets, t_net* LL_vpack_net) { - FILE* fp = NULL; - int iblock, inet, ichar, name_str_len, num_violations; - char renamed_char = '_'; - boolean io_renamed = FALSE; - boolean io_violate_syntax = FALSE; - char* temp_io_name = NULL; - char* renaming_report_file_path = NULL; - - vpr_printf(TIO_MESSAGE_INFO, "Check IO pad names, to avoid violate SPICE or Verilog Syntax...\n"); - - num_violations = 0; - - /* Check if the path exists*/ - renaming_report_file_path = my_strcat(circuit_name, renaming_report_postfix); - fp = fopen(renaming_report_file_path,"w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create renaming report %s!", - __FILE__, __LINE__, renaming_report_file_path); - exit(1); - } - - fprintf(fp, "------- Logical block renaming report BEGIN ----------\n"); - for (iblock = 0; iblock < LL_num_logical_blocks; iblock++) { - /* Bypass non-IO logical blocks */ - /* - if ((VPACK_INPAD != logical_block[iblock].type)&&(VPACK_OUTPAD != logical_block[iblock].type)) { - continue; - } - */ - /* initialize the flag */ - io_renamed = FALSE; - io_violate_syntax = FALSE; - /* Keep a copy of previous name */ - temp_io_name = my_strdup(LL_logical_block[iblock].name); - /* Check names character by charcter */ - name_str_len = strlen(LL_logical_block[iblock].name); /* exclude the last character: \0, which does require to be checked */ - for (ichar = 0; ichar < name_str_len; ichar++) { - /* Check syntax senstive list, if violates, rename it to be '_' */ - if (TRUE == is_verilog_and_spice_syntax_conflict_char(LL_reserved_syntax_char_head, LL_logical_block[iblock].name[ichar])) { - num_violations++; - io_violate_syntax = TRUE; - if ( TRUE == rename_illegal_port) { - LL_logical_block[iblock].name[ichar] = renamed_char; - io_renamed = TRUE; - } - } - } - /* Print a warning if */ - if (TRUE == io_renamed) { - fprintf(fp, "[RENAMING%d] Logical block (Name: %s) is renamed to %s\n", - num_violations, - temp_io_name, LL_logical_block[iblock].name); - } else if (TRUE == io_violate_syntax) { - fprintf(fp, "[RENAMING%d] Logical block name %s violates syntax rules \n", - num_violations, - temp_io_name); - } - /* Free */ - my_free(temp_io_name); - } - - fprintf(fp, "-------Logical block renaming report END ----------\n\n"); - - fprintf(fp, "-------CLB_NET renaming report BEGIN ----------\n"); - /* Change the net name in the clb_net and vpack_net info as well !!! */ - for (inet = 0; inet < LL_num_clb_nets; inet++) { - /* initialize the flag */ - io_renamed = FALSE; - io_violate_syntax = FALSE; - /* Keep a copy of previous name */ - temp_io_name = my_strdup(LL_clb_net[inet].name); - /* Check names character by charcter */ - name_str_len = strlen(LL_clb_net[inet].name); /* exclude the last character: \0, which does require to be checked */ - for (ichar = 0; ichar < name_str_len; ichar++) { - /* Check syntax senstive list, if violates, rename it to be '_' */ - if (TRUE == is_verilog_and_spice_syntax_conflict_char(LL_reserved_syntax_char_head, LL_clb_net[inet].name[ichar])) { - num_violations++; - io_violate_syntax = TRUE; - if ( TRUE == rename_illegal_port) { - LL_clb_net[inet].name[ichar] = renamed_char; - io_renamed = TRUE; - } - } - } - /* Print a warning if */ - if (TRUE == io_renamed) { - fprintf(fp, "[RENAMING%d] clb_net (Name: %s) is renamed to %s\n", - num_violations, - temp_io_name, LL_clb_net[inet].name); - } else if (TRUE == io_violate_syntax) { - fprintf(fp, "[RENAMING%d] clb_net name %s violates syntax rules \n", - num_violations, - temp_io_name); - } - /* Free */ - my_free(temp_io_name); - } - - fprintf(fp, "-------CLB_NET renaming report END ----------\n\n"); - - fprintf(fp, "-------VPACK_NET renaming report BEGIN ----------\n"); - - for (inet = 0; inet < LL_num_vpack_nets; inet++) { - /* initialize the flag */ - io_renamed = FALSE; - io_violate_syntax = FALSE; - /* Keep a copy of previous name */ - temp_io_name = my_strdup(LL_vpack_net[inet].name); - /* Check names character by charcter */ - name_str_len = strlen(LL_vpack_net[inet].name); /* exclude the last character: \0, which does require to be checked */ - for (ichar = 0; ichar < name_str_len; ichar++) { - /* Check syntax senstive list, if violates, rename it to be '_' */ - if (TRUE == is_verilog_and_spice_syntax_conflict_char(LL_reserved_syntax_char_head, LL_vpack_net[inet].name[ichar])) { - num_violations++; - io_violate_syntax = TRUE; - if ( TRUE == rename_illegal_port) { - LL_vpack_net[inet].name[ichar] = renamed_char; - io_renamed = TRUE; - } - } - } - /* Print a warning if */ - if (TRUE == io_renamed) { - fprintf(fp, "[RENAMING%d] vpack_net (Name: %s) is renamed to %s\n", - num_violations, - temp_io_name, LL_vpack_net[inet].name); - } else if (TRUE == io_violate_syntax) { - fprintf(fp, "[RENAMING%d] vpack_net name %s violates syntax rules \n", - num_violations, - temp_io_name); - } - /* Free */ - my_free(temp_io_name); - } - - fprintf(fp, "-------VPACK_NET renaming report END ----------\n"); - - if ((0 < num_violations) && ( FALSE == rename_illegal_port )) { - vpr_printf(TIO_MESSAGE_WARNING, "Detect %d port violate syntax rules while renaming port is disabled\n", num_violations); - } - - /* close fp */ - fclose(fp); - - vpr_printf(TIO_MESSAGE_INFO, "Renaming report is generated in %s\n", - renaming_report_file_path); - - return num_violations; -} - - -static -void spice_net_info_add_density_weight(float signal_density_weight) { - int inet; - - /* a weight of 1. means no change. directly return */ - if ( 1. == signal_density_weight ) { - return; - } - - for (inet = 0; inet < num_logical_nets; inet++) { - assert( NULL != vpack_net[inet].spice_net_info ); - /* By pass PIs since their signal density is usually high */ - if ( TRUE == is_net_pi(&(vpack_net[inet])) ) { - continue; - } - vpack_net[inet].spice_net_info->density *= signal_density_weight; - } - - for (inet = 0; inet < num_nets; inet++) { - assert( NULL != clb_net[inet].spice_net_info ); - /* By pass PIs since their signal density is usually high */ - if ( TRUE == is_net_pi(&(vpack_net[clb_to_vpack_net_mapping[inet]])) ) { - continue; - } - clb_net[inet].spice_net_info->density *= signal_density_weight; - } -} - -void fpga_x2p_free(t_arch* Arch) { - /* Free index low and high */ - free_spice_model_grid_index_low_high(Arch->spice->num_spice_model, Arch->spice->spice_models); - free_spice_model_routing_index_low_high(Arch->spice->num_spice_model, Arch->spice->spice_models); -} - -/******************************************************* - * This function will force the flag of - * dump_explicit_port_map to be true - * for all the circuit models in the circuit library - ******************************************************/ -static -void overwrite_circuit_library_dump_explicit_port_map(t_arch* Arch) { - /* Iterate over all the circuit models */ - for (const auto& circuit_model : Arch->spice->circuit_lib.models()) { - Arch->spice->circuit_lib.set_model_dump_explicit_port_map(circuit_model, true); - } -} - -/* Top-level function of FPGA-SPICE setup */ -void fpga_x2p_setup(t_vpr_setup vpr_setup, - t_arch* Arch) { - /* Timer */ - clock_t t_start; - clock_t t_end; - float run_time_sec; - - int num_rename_violation = 0; - int num_clocks = 0; - float vpr_crit_path_delay = 0.; - float vpr_clock_freq = 0.; - float vpr_clock_period = 0.; - - /* Start time count */ - t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, "\nFPGA-X2P Tool suites Initilization begins...\n"); - - /* FIXME: this function is going to be removed when new linking function is working - * Initialize Arch SPICE MODELS - */ - init_check_arch_spice_models(Arch, &(vpr_setup.RoutingArch)); - - /* Link circuit models to architecture */ - link_circuit_library_to_arch(Arch, &(vpr_setup.RoutingArch)); - /* Overwrite explicit_port_map settings if user required */ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog) { - vpr_printf(TIO_MESSAGE_INFO, "Detect explicit Verilog option is enabled. Force all the circuit models to dump explicit Verilog...\n"); - overwrite_circuit_library_dump_explicit_port_map(Arch); - } - - /* Initialize idle mode and physical mode of each pb_type and pb_graph_node */ - init_check_arch_pb_type_idle_and_phy_mode(); - - /* Create and initialize a linked list for global ports */ - global_ports_head = init_llist_global_ports(Arch->spice); - vpr_printf(TIO_MESSAGE_INFO, "Detect %d global ports...\n", - find_length_llist(global_ports_head) ); - - /* Build llist for verilog and spice syntax char */ - vpr_printf(TIO_MESSAGE_INFO, "Initialize reserved Verilog and SPICE syntax chars...\n"); - reserved_syntax_char_head = init_llist_verilog_and_spice_syntax_char(); - - /* Initialize verilog netlist to be included */ - /* Add keyword checking */ - check_keywords_conflict(*Arch); - /* TODO: check spice_model names conflict with SPICE or Verilog syntax */ - vpr_printf(TIO_MESSAGE_INFO, "Checking spice_model compatible with syntax chars...\n"); - check_spice_model_name_conflict_syntax_char(*Arch, - reserved_syntax_char_head); - - - /* Check and rename io names to avoid violating SPICE or Verilog syntax - * Only valid when Verilog generator or SPICE generator is enabled - */ - num_rename_violation = - check_and_rename_logical_block_and_net_names(reserved_syntax_char_head, - vpr_setup.FileNameOpts.CircuitName, - vpr_setup.FPGA_SPICE_Opts.rename_illegal_port, - num_logical_blocks, logical_block, - num_nets, clb_net, - num_logical_nets, vpack_net); - /* Violation is not allowed for SPICE and Verilog Generator! */ - if (((0 < num_rename_violation) && (FALSE == vpr_setup.FPGA_SPICE_Opts.rename_illegal_port)) - && ((TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) - || (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog))) { - vpr_printf(TIO_MESSAGE_ERROR, "Port name syntax violations is not allowed for SPICE and Verilog Generators!\n"); - exit(1); - } - - /* Update global options: - * 1. run_parasitic_net_estimation - * 2. run_testbench_load_extraction - */ - run_parasitic_net_estimation = TRUE; - if (FALSE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_parasitic_net_estimation) { - run_parasitic_net_estimation = FALSE; - } - - run_testbench_load_extraction = TRUE; - if (FALSE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_testbench_load_extraction) { - run_testbench_load_extraction = FALSE; - vpr_printf(TIO_MESSAGE_WARNING, "SPICE testbench load extraction is turned off...Accuracy loss may be expected!\n"); - } - - /* Check Activity file is valid */ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.read_act_file) { - if (1 == try_access_file(vpr_setup.FileNameOpts.ActFile)) { - vpr_printf(TIO_MESSAGE_ERROR,"Activity file (%s) does not exists! Please provide a valid file path!\n", - vpr_setup.FileNameOpts.ActFile); - exit(1); - } else { - vpr_printf(TIO_MESSAGE_INFO,"Check Activity file (%s) is a valid file path!\n", - vpr_setup.FileNameOpts.ActFile); - } - } - - /* Backannotation for post routing information */ - spice_backannotate_vpr_post_route_info(vpr_setup.RoutingArch, - vpr_setup.FPGA_SPICE_Opts.read_act_file, - vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_parasitic_net_estimation); - - /* Try to use mirror SBs/CBs if enabled by user */ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) { - - /* Idenify mirror and rotatable Switch blocks and Connection blocks */ - identify_mirror_switch_blocks(); - identify_mirror_connection_blocks(); - } - - /* Assign Gobal variable: build the Routing Resource Channels */ - device_rr_chan = build_device_rr_chan(num_rr_nodes, rr_node, rr_node_indices, Arch->num_segments, rr_indexed_data); - device_rr_gsb = build_device_rr_gsb(TRUE == vpr_setup.FPGA_SPICE_Opts.output_sb_xml, - TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy, - vpr_setup.FPGA_SPICE_Opts.sb_xml_dir, - num_rr_nodes, rr_node, rr_node_indices, - Arch->num_segments, rr_indexed_data); - - /* Rotatable will be done in the next step - identify_rotatable_switch_blocks(); - identify_rotatable_connection_blocks(); - */ - - /* Not should be done when read_act_file is disabled */ - if (FALSE == vpr_setup.FPGA_SPICE_Opts.read_act_file) { - return; - } - - /* Auto check the density and recommend sim_num_clock_cylce */ - vpr_crit_path_delay = get_critical_path_delay()/1e9; - assert(vpr_crit_path_delay > 0.); - /* if we don't have global clock, clock_freqency should be set to 0.*/ - num_clocks = count_netlist_clocks(); - if (0 == num_clocks) { - /* This could a combinational circuit */ - vpr_clock_freq = 1. / vpr_crit_path_delay; - } else { - assert(1 == num_clocks); - vpr_clock_freq = 1. / vpr_crit_path_delay; - } - Arch->spice->spice_params.stimulate_params.num_clocks = num_clocks; - Arch->spice->spice_params.stimulate_params.vpr_crit_path_delay = vpr_crit_path_delay; - vpr_clock_period = 1./vpr_clock_freq; - auto_select_num_sim_clock_cycle(Arch->spice, vpr_setup.FPGA_SPICE_Opts.sim_window_size); - - /* Determine the clock period */ - if (OPEN == Arch->spice->spice_params.stimulate_params.op_clock_freq) { - /* warning the negative slack ! TODO: move to the general check part??? */ - if (0. > Arch->spice->spice_params.stimulate_params.sim_clock_freq_slack) { - assert(0. < (1 + Arch->spice->spice_params.stimulate_params.sim_clock_freq_slack)); - vpr_printf(TIO_MESSAGE_WARNING, "Slack for clock frequency(=%g) is less than 0! The simulation may fail!\n", - Arch->spice->spice_params.stimulate_params.sim_clock_freq_slack); - } - Arch->spice->spice_params.stimulate_params.op_clock_freq = 1./(vpr_clock_period *(1. + Arch->spice->spice_params.stimulate_params.sim_clock_freq_slack)); - } else { - /* Simulate clock frequency should be larger than 0 !*/ - assert(0. < Arch->spice->spice_params.stimulate_params.op_clock_freq); - } - vpr_printf(TIO_MESSAGE_INFO, "Use Operation Clock freqency %.2f [MHz] in SPICE simulation.\n", - Arch->spice->spice_params.stimulate_params.op_clock_freq / 1e6); - vpr_printf(TIO_MESSAGE_INFO, "Use Programming Clock freqency %.2f [MHz] in SPICE simulation.\n", - Arch->spice->spice_params.stimulate_params.prog_clock_freq / 1e6); - - /* Add weights to spice_net density */ - if (!(0 < vpr_setup.FPGA_SPICE_Opts.signal_density_weight)) { - vpr_printf(TIO_MESSAGE_ERROR, "Signal_density_weight(currently is %.2f) should be a positive number!.\n", - vpr_setup.FPGA_SPICE_Opts.signal_density_weight); - exit(1); - } - if (1 != vpr_setup.FPGA_SPICE_Opts.signal_density_weight) { - vpr_printf(TIO_MESSAGE_INFO, "Add %.2f weight to signal density...\n", - vpr_setup.FPGA_SPICE_Opts.signal_density_weight); - spice_net_info_add_density_weight(vpr_setup.FPGA_SPICE_Opts.signal_density_weight); - } - - /* End time count */ - t_end = clock(); - - run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, "FPGA X2P setup took %g seconds\n", run_time_sec); - - - return; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.h deleted file mode 100644 index 63d6949ea..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.h +++ /dev/null @@ -1,10 +0,0 @@ - -void init_check_arch_spice_models(t_arch* arch, - t_det_routing_arch* routing_arch); - -void check_keywords_conflict(t_arch Arch); - -void fpga_x2p_free(t_arch* Arch); - -void fpga_x2p_setup(t_vpr_setup vpr_setup, - t_arch* Arch); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_timing_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_timing_utils.c deleted file mode 100644 index fbed0d29f..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_timing_utils.c +++ /dev/null @@ -1,314 +0,0 @@ - -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "token.h" - -/* Include SPICE support headers*/ -#include "quicksort.h" -#include "linkedlist.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_utils.h" - -#include "fpga_x2p_timing_utils.h" - -/* Build the list of spice_model_ports provided in the cur_spice_model delay_info */ -t_spice_model_port** get_spice_model_delay_info_ports(t_spice_model* cur_spice_model, - char* port_list, - int* num_port) { - int itok; - int num_token = 0; - char** tokens = NULL; - t_spice_model_port** port = NULL; - - /* Get input ports */ - tokens = fpga_spice_strtok(port_list, " ", &num_token); - /* allocate in_port */ - port = (t_spice_model_port**) my_malloc(sizeof(t_spice_model_port*) * num_token); - /* Find corresponding spice_model_port */ - for (itok = 0; itok < num_token; itok++) { - port[itok] = find_spice_model_port_by_name(cur_spice_model, tokens[itok]); - /* Error out if we cannot find a port */ - if (NULL == port[itok]) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Fail to find a port listed in delay_info (port_name=%s)!\n", - __FILE__, __LINE__, tokens[itok]); - exit(1); - } - /* TODO: Error out if port type does not match */ - } - - /* give return value */ - (*num_port) = num_token; - - return port; -} - -/* Determine the number of tedges (timing edges) for each output pin of a SPICE model - * For each output pin, we need a tedge connected to all the input pins - * The number of tedges per pin is the number of input pins - */ -int get_spice_model_num_tedges_per_pin(t_spice_model* cur_spice_model, - enum PORTS port_type) { - int iport; - int num_tedges = 0; - - /* Get num_edges for each output pin */ - for (iport = 0; iport < cur_spice_model->num_port; iport++) { - switch (port_type) { - case IN_PORT: - if (SPICE_MODEL_PORT_OUTPUT != cur_spice_model->ports[iport].type) { - continue; /* ALL output ports requires a tedge */ - } - num_tedges += cur_spice_model->ports[iport].size; - break; - case OUT_PORT: - if (SPICE_MODEL_PORT_OUTPUT == cur_spice_model->ports[iport].type) { - continue; /* ALL non-output ports requires a tedge */ - } - num_tedges += cur_spice_model->ports[iport].size; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid port type!\n", - __FILE__, __LINE__); - exit(1); - } - } - - return num_tedges; -} - -t_spice_model_tedge* get_unused_spice_model_port_tedge(t_spice_model_port* cur_port, - int pin_index) { - int iedge; - - /* Check the edge array */ - for (iedge = 0; iedge < cur_port->num_tedges[pin_index]; iedge++) { - /* See if this is an unused edge */ - if (NULL == cur_port->tedge[pin_index][iedge]->from_port) { - assert (OPEN == cur_port->tedge[pin_index][iedge]->from_port_pin_number); - return cur_port->tedge[pin_index][iedge]; - } - } - - return NULL; -} - -/* Allocate tedges (timing edges) for a SPICE model - * For each output pin, we need a tedge connected to all the input pins - */ -void alloc_spice_model_num_tedges(t_spice_model* cur_spice_model) { - int iport, ipin, iedge; - int jport, jpin; - int num_out_tedges = 0; - int num_in_tedges = 0; - - /* Get num_edges for each output pin */ - num_out_tedges = get_spice_model_num_tedges_per_pin(cur_spice_model, OUT_PORT); - num_in_tedges = get_spice_model_num_tedges_per_pin(cur_spice_model, IN_PORT); - - /* Allocate tedges for output ports */ - for (iport = 0; iport < cur_spice_model->num_port; iport++) { - if ( (SPICE_MODEL_PORT_OUTPUT != cur_spice_model->ports[iport].type) - && (SPICE_MODEL_PORT_INOUT != cur_spice_model->ports[iport].type)) { - continue; /* We only care OUTPUT and INOUT ports */ - } - /* allocate num_tedges */ - cur_spice_model->ports[iport].num_tedges = (int*) my_malloc(sizeof(int) * cur_spice_model->ports[iport].size); - for (ipin = 0; ipin < cur_spice_model->ports[iport].size; ipin++) { - cur_spice_model->ports[iport].num_tedges[ipin] = num_out_tedges; - } - /* allocate tedges */ - cur_spice_model->ports[iport].tedge = (t_spice_model_tedge***) my_calloc(cur_spice_model->ports[iport].size, sizeof(t_spice_model_tedge**)); - for (ipin = 0; ipin < cur_spice_model->ports[iport].size; ipin++) { - cur_spice_model->ports[iport].tedge[ipin] = (t_spice_model_tedge**) my_calloc(cur_spice_model->ports[iport].num_tedges[ipin], sizeof(t_spice_model_tedge*)); - /* Allocate tedge and fill the pointor array */ - for (iedge = 0; iedge < cur_spice_model->ports[iport].num_tedges[ipin]; iedge++) { - cur_spice_model->ports[iport].tedge[ipin][iedge] = (t_spice_model_tedge*) my_calloc(1, sizeof(t_spice_model_tedge)); - /* Initialize the to_port information of the tedges */ - cur_spice_model->ports[iport].tedge[ipin][iedge]->to_port = &(cur_spice_model->ports[iport]); - cur_spice_model->ports[iport].tedge[ipin][iedge]->to_port_pin_number = ipin; - cur_spice_model->ports[iport].tedge[ipin][iedge]->from_port = NULL; - cur_spice_model->ports[iport].tedge[ipin][iedge]->from_port_pin_number = OPEN; - } - } - } - - /* Allocate tedges for input ports */ - for (iport = 0; iport < cur_spice_model->num_port; iport++) { - if (SPICE_MODEL_PORT_OUTPUT == cur_spice_model->ports[iport].type) { - continue; /* We only care non-OUTPUT ports */ - } - /* allocate num_tedges */ - cur_spice_model->ports[iport].num_tedges = (int*) my_malloc(sizeof(int) * cur_spice_model->ports[iport].size); - for (ipin = 0; ipin < cur_spice_model->ports[iport].size; ipin++) { - cur_spice_model->ports[iport].num_tedges[ipin] = num_in_tedges; - } - /* allocate tedges */ - cur_spice_model->ports[iport].tedge = (t_spice_model_tedge***) my_calloc(cur_spice_model->ports[iport].size, sizeof(t_spice_model_tedge**)); - for (ipin = 0; ipin < cur_spice_model->ports[iport].size; ipin++) { - cur_spice_model->ports[iport].tedge[ipin] = (t_spice_model_tedge**) my_calloc(cur_spice_model->ports[iport].num_tedges[ipin], sizeof(t_spice_model_tedge*)); - } - } - - /* Find tedge and fill the pointor array */ - /* Get the unused edge from each output edge */ - for (iport = 0; iport < cur_spice_model->num_port; iport++) { - if (SPICE_MODEL_PORT_OUTPUT == cur_spice_model->ports[iport].type) { - continue; /* We only care non-OUTPUT ports */ - } - for (ipin = 0; ipin < cur_spice_model->ports[iport].size; ipin++) { - for (iedge = 0; iedge < cur_spice_model->ports[iport].num_tedges[ipin]; iedge++) { - /* Find each output edge */ - for (jport = 0; jport < cur_spice_model->num_port; jport++) { - if ( (SPICE_MODEL_PORT_OUTPUT != cur_spice_model->ports[jport].type) - && (SPICE_MODEL_PORT_INOUT != cur_spice_model->ports[jport].type)) { - continue; /* We only care OUTPUT and INOUT ports */ - } - for (jpin = 0; jpin < cur_spice_model->ports[jport].size; jpin++) { - /* get the first unused edge */ - cur_spice_model->ports[iport].tedge[ipin][iedge] = get_unused_spice_model_port_tedge(&(cur_spice_model->ports[jport]), jpin); - assert(NULL != cur_spice_model->ports[iport].tedge[ipin][iedge]); - /* Configure the tedge */ - cur_spice_model->ports[iport].tedge[ipin][iedge]->from_port = &(cur_spice_model->ports[iport]); - cur_spice_model->ports[iport].tedge[ipin][iedge]->from_port_pin_number = ipin; - } - } - } - } - } - - return; -} - -/* Depend on the type of delay, configure the tedge content */ -void configure_one_tedge_delay(t_spice_model_tedge* cur_tedge, - enum spice_model_delay_type delay_type, - float delay) { - - switch (delay_type) { - case SPICE_MODEL_DELAY_RISE: - cur_tedge->trise = delay; - break; - case SPICE_MODEL_DELAY_FALL: - cur_tedge->tfall = delay; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid delay type!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -void configure_tedges_delay_matrix(enum spice_model_delay_type delay_type, - int num_in_port, t_spice_model_port** in_port, - int num_out_port, t_spice_model_port** out_port, - float** delay_matrix) { - int iedge, iport, ipin; - int jport; - - /* Configure timing edges for this spice_model */ - for (iport = 0; iport < num_in_port; iport++) { - for (ipin = 0; ipin < in_port[iport]->size; ipin++) { - for (iedge = 0; iedge < in_port[iport]->num_tedges[ipin]; iedge++) { - /* check each edge, see if the from_port and to_port match! */ - /* Src should match! */ - assert ( in_port[iport] == in_port[iport]->tedge[ipin][iedge]->from_port ); - for (jport = 0; jport < num_out_port; jport++) { - /* Check if des matches */ - if ( out_port[jport] == in_port[iport]->tedge[ipin][iedge]->to_port ) { - configure_one_tedge_delay(in_port[iport]->tedge[ipin][iedge], delay_type, delay_matrix[iport][jport]); - } - } - } - } - } - - return; -} - -/* allocate and parse delay_matix */ -float** fpga_spice_atof_2D(int num_in_port, int num_out_port, char* str) { - int i; - float** delay_matrix = NULL; - - /* allocate */ - delay_matrix = (float**)my_calloc(num_in_port, sizeof(float*)); - for (i = 0; i < num_in_port; i++) { - delay_matrix[i] = (float*)my_calloc(num_out_port, sizeof(float)); - } - - my_atof_2D(delay_matrix, num_in_port, num_out_port, str); - - return delay_matrix; -} - -void free_2D_matrix(void** delay_matrix, - int num_in_port, int num_out_port) { - int i; - - for (i = 0; i < num_in_port; i++) { - my_free(delay_matrix[i]); - } - - my_free(delay_matrix); - - return; -} - -/* Build timing graph for a spice_model */ -void annotate_spice_model_timing(t_spice_model* cur_spice_model) { - int i; - int num_in_port = 0; - t_spice_model_port** in_port = NULL; - int num_out_port = 0; - t_spice_model_port** out_port = NULL; - float** delay_matrix = NULL; - - /* check */ - assert ( 0 < cur_spice_model->num_delay_info ); - - /* Allocate edges */ - alloc_spice_model_num_tedges(cur_spice_model); - - /* Parse each delay_info */ - for (i = 0; i < cur_spice_model->num_delay_info; i++) { - /* Get input and output ports */ - in_port = get_spice_model_delay_info_ports(cur_spice_model, cur_spice_model->delay_info[i].in_port_name, &num_in_port); - out_port = get_spice_model_delay_info_ports(cur_spice_model, cur_spice_model->delay_info[i].out_port_name, &num_out_port); - /* create fpga_spice atof_2D !!! */ - delay_matrix = fpga_spice_atof_2D(num_in_port, num_out_port, cur_spice_model->delay_info[i].value); - /* create tedges with delay_matrix */ - configure_tedges_delay_matrix(cur_spice_model->delay_info[i].type, - num_in_port, in_port, - num_out_port, out_port, - delay_matrix); - /* Free */ - free_2D_matrix((void**)delay_matrix, num_in_port, num_out_port); - } - - return; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_timing_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_timing_utils.h deleted file mode 100644 index 7923008dd..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_timing_utils.h +++ /dev/null @@ -1,28 +0,0 @@ - -t_spice_model_port** get_spice_model_delay_info_ports(t_spice_model* cur_spice_model, - char* port_list, - int* num_port); - -int get_spice_model_num_tedges_per_pin(t_spice_model* cur_spice_model, - enum PORTS port_type); - -t_spice_model_tedge* get_unused_spice_model_port_tedge(t_spice_model_port* cur_port, - int pin_index); - -void alloc_spice_model_num_tedges(t_spice_model* cur_spice_model); - -void configure_one_tedge_delay(t_spice_model_tedge* cur_tedge, - enum spice_model_delay_type delay_type, - float delay); - -void configure_tedges_delay_matrix(enum spice_model_delay_type delay_type, - int num_in_port, t_spice_model_port** in_port, - int num_out_port, t_spice_model_port** out_port, - float** delay_matrix); - -float** fpga_spice_atof_2D(int num_in_port, int num_out_port, char* str); - -void free_2D_matrix(void** delay_matrix, - int num_in_port, int num_out_port); - -void annotate_spice_model_timing(t_spice_model* cur_spice_model); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_types.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_types.h deleted file mode 100644 index 982377120..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_types.h +++ /dev/null @@ -1,144 +0,0 @@ -#ifndef FPGA_X2P_TYPES_H -#define FPGA_X2P_TYPES_H - -#include "vpr_types.h" -#include "route_common.h" - -/* Define the basic data structures used for FPGA-SPICE */ - -/* Default ID of switch used in rr_node */ -#define DEFAULT_SWITCH_ID 0 - -/* Default prev_node ID of a rr_node */ -#define DEFAULT_PREV_NODE -1 - -/* Default path ID of a unused multiplexer */ -#define DEFAULT_PATH_ID -1 - -/* Default path ID of a unused multiplexer when there are no constant inputs*/ -#define DEFAULT_MUX_PATH_ID 0 - -/* Index of logical block indicating a wired LUT */ -#define WIRED_LUT_LOGICAL_BLOCK_ID -2 - -#define BLIF_LUT_KEYWORD "names" - -/* Mode Index of a LUT: - * 0 indicates a wired mode (a buffer) - * 0 indicates a regular mode (a buffer) - */ -#define WIRED_LUT_MODE_INDEX 0 -#define NORMAL_LUT_MODE_INDEX 1 - -/* Key data structure for router: routing resource graph - * This data structure store the key parameters that - * models a routing resource graph used by router. - * 1. number of routing resource nodes in the graph - * 2. all the routing resource nodes - * 3. router information for each routing resource node - */ -typedef struct fpga_spice_rr_graph t_rr_graph; -struct fpga_spice_rr_graph { - /* Routing Resource nodes */ - int num_rr_nodes; - t_rr_node* rr_node; - t_ivec*** rr_node_indices; - - /* Switches between routing resource nodes */ - int num_switch_inf; - t_switch_inf* switch_inf; - int delayless_switch_index; - - int num_nets; /* number of nets to route */ - t_net** net; /* nets to route, this is pointer to the existing nets */ - int* net_to_vpack_net_mapping; - int* net_num_sources; - int* net_num_sinks; - - /* Gives the rr_node indices of net terminals. */ - int **net_rr_sources; /* [0..num_nets-1][0..num_pins-1] */ - int **net_rr_sinks; /* [0..num_nets-1][0..num_pins-1] */ - int **net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */ - t_chunk rr_mem_ch; - - /* Routing statisitics */ - int num_rr_indexed_data; - t_rr_indexed_data *rr_indexed_data; /* [0..(num_rr_indexed_data-1)] */ - - t_rr_node_route_inf* rr_node_route_inf; - t_bb *route_bb; /* [0..num_nets-1]. Limits area in which each */ - - /* Linked list start pointers. Define the routing. */ - t_trace **trace_head; /* [0..(num_nets-1)] */ - t_trace **trace_tail; /* [0..(num_nets-1)] */ - t_trace *trace_free_head; - t_chunk trace_ch; - - /**************** Static variables local to route_common.c ******************/ - t_heap **heap; /* Indexed from [1..heap_size] */ - int heap_size; /* Number of slots in the heap array */ - int heap_tail; /* Index of first unused slot in the heap array */ - - /* For managing my own list of currently free heap data structures. */ - t_heap *heap_free_head; - /* For keeping track of the sudo malloc memory for the heap*/ - t_chunk heap_ch; - - t_linked_f_pointer *rr_modified_head; - t_linked_f_pointer *linked_f_pointer_free_head; - - t_chunk linked_f_pointer_ch; - - #ifdef DEBUG - int num_trace_allocated; /* To watch for memory leaks. */ - int num_heap_allocated; - int num_linked_f_pointer_allocated; - #endif - -}; - -/* Key data structure for physical pb - * This data structure store the key parameters that - * models a physical_pb. - * This is a simplified copy of original t_pb - * except the rr_graph part - */ -typedef struct fpga_spice_phy_pb t_phy_pb; -struct fpga_spice_phy_pb { - char *name; /* Name of this physical block */ - t_pb_graph_node *pb_graph_node; /* pointer to pb_graph_node this pb corresponds to */ - int num_logical_blocks; - int* logical_block; /* If this is a terminating pb, gives the logical (netlist) block that it contains */ - boolean* is_wired_lut; /* Specify if this is a wired LUT (used as buffer) */ - t_pb_graph_pin** lut_output_pb_graph_pin; - int* lut_size; - - int mode; /* mode that this pb is set to */ - char* mode_bits; /* Mode bits for the logical block */ - - t_phy_pb **child_pbs; /* children pbs attached to this pb [0..num_child_pb_types - 1][0..child_type->num_pb - 1] */ - t_phy_pb *parent_pb; /* pointer to parent node */ - - /* Xifan TANG: FPGA-SPICE*/ - t_rr_graph* rr_graph; - /* END */ - t_phy_pb **rr_node_to_pb_mapping; /* [0..num_local_rr_nodes-1] pointer look-up of which pb this rr_node belongs based on index, NULL if pb does not exist */ - - int *lut_pin_remap; /* [0..num_lut_inputs-1] applies only to LUT primitives, stores how LUT inputs were swapped during CAD flow, - LUT inputs can be swapped by changing the logic in the LUT, this is useful because the fastest LUT input compared to the slowest is often significant (2-5x), - so this optimization is crucial for handling LUT based FPGAs. - */ - - /* Xifan TANG: SPICE model support*/ - char* spice_name_tag; - - /* Xifan TANG: FPGA-SPICE and SynVerilog */ - int num_reserved_conf_bits; - int num_conf_bits; - int num_mode_bits; - int num_inpads; - int num_outpads; - int num_iopads; -}; - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c deleted file mode 100644 index d3f3539e5..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ /dev/null @@ -1,1481 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: fpga_x2p_unique_routing.c - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/06/25 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file contains builders for the data structures - * 1. RRGSB: General Switch Block (GSB). - * 2. RRChan: Generic routing channels - * We also include functions to identify unique modules of - * Switch Blocks and Connection Blocks based on the data structures - * t_sb and t_cb - ***********************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "path_delay.h" -#include "stats.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "read_xml_spice_util.h" -#include "linkedlist.h" -#include "rr_blocks.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_backannotate_utils.h" -#include "write_rr_blocks.h" -#include "fpga_x2p_unique_routing.h" - -/***** subroutines declaration *****/ -void assign_switch_block_mirror(t_sb* src, t_sb* des); - -void assign_connection_block_mirror(t_cb* src, t_cb* des); - -boolean is_two_sb_rr_nodes_mirror(t_sb* src_sb, t_sb* des_sb, int side, - t_rr_node* src_rr_node, t_rr_node* des_rr_node); - -boolean is_two_cb_rr_nodes_mirror(t_cb* src_cb, t_cb* des_cb, - t_rr_node* src_rr_node, t_rr_node* des_rr_node); - -boolean is_two_switch_blocks_mirror(t_sb* src, t_sb* des); - -boolean is_two_connection_blocks_mirror(t_cb* src, t_cb* des); - -void assign_mirror_switch_blocks(); - -void assign_mirror_connection_blocks(); - -boolean validate_one_switch_block_mirror(t_sb* cur_sb); - -boolean validate_one_connection_block_mirror(t_cb* cur_cb); - -void update_one_switch_block_mirror(t_sb* cur_sb); - -void update_one_connection_block_mirror(t_cb* cur_cb); - -boolean validate_mirror_switch_blocks(); - -boolean validate_mirror_connection_blocks(); - -void update_mirror_switch_blocks(); - -void update_mirror_connection_blocks(); - -void print_mirror_switch_block_stats(); - -void print_mirror_connection_block_stats(); - -void print_device_rr_chan_stats(DeviceRRChan& device_rr_chan); - -/***** subroutines *****/ -void assign_switch_block_mirror(t_sb* src, t_sb* des) { - assert ( (NULL != src) && (NULL != des) ); - /* check if the mirror of the first SB is assigned */ - if (NULL != src->mirror) { - /* Assign mirror of the first SB to the second SB */ - /* traceback to the upstream */ - t_sb* temp = src->mirror; - while (NULL != temp->mirror) { - /* go to the next */ - temp = temp->mirror; - } - /* We reach the upstream, ensure its mirror is empty */ - assert(NULL == temp->mirror); - des->mirror = temp; - } else { - /* Assign the first SB as the mirror to the second SB */ - des->mirror = src; - } - - return; -} - -void assign_connection_block_mirror(t_cb* src, t_cb* des) { - assert ( (NULL != src) && (NULL != des) ); - /* check if the mirror of the first SB is assigned */ - if (NULL != src->mirror) { - /* Assign mirror of the first SB to the second SB */ - /* traceback to the upstream */ - t_cb* temp = src->mirror; - while (NULL != temp->mirror) { - /* go to the next */ - temp = temp->mirror; - } - /* We reach the upstream, ensure its mirror is empty */ - assert(NULL == temp->mirror); - des->mirror = temp; - } else { - /* Assign the first SB as the mirror to the second SB */ - des->mirror = src; - } - - return; -} - - -/* check if two rr_nodes have a similar set of drive_rr_nodes - * for each drive_rr_node: - * 1. CHANX or CHANY: should have the same side and index - * 2. OPIN or IPIN: should have the same side and index - * 3. each drive_rr_switch should be the same - */ -boolean is_two_sb_rr_nodes_mirror(t_sb* src_sb, t_sb* des_sb, int side, - t_rr_node* src_rr_node, t_rr_node* des_rr_node) { - - /* Ensure rr_nodes are either the output of short-connection or multiplexer */ - if ( check_drive_rr_node_imply_short(*src_sb, src_rr_node, side) - != check_drive_rr_node_imply_short(*des_sb, des_rr_node, side)) { - return FALSE; - } - /* Find the driving rr_node in this sb */ - if (TRUE == check_drive_rr_node_imply_short(*src_sb, src_rr_node, side)) { - /* Ensure we have the same track id for the driving nodes */ - if ( is_rr_node_exist_opposite_side_in_sb_info(*src_sb, src_rr_node, side) - != is_rr_node_exist_opposite_side_in_sb_info(*des_sb, des_rr_node, side)) { - return FALSE; - } - } else { /* check driving rr_nodes */ - if ( src_rr_node->num_drive_rr_nodes != des_rr_node->num_drive_rr_nodes ) { - return FALSE; - } - for (int inode = 0; inode < src_rr_node->num_drive_rr_nodes; ++inode) { - /* node type should be the same */ - if ( src_rr_node->drive_rr_nodes[inode]->type - != des_rr_node->drive_rr_nodes[inode]->type) { - return FALSE; - } - /* switch type should be the same */ - if ( src_rr_node->drive_switches[inode] - != des_rr_node->drive_switches[inode]) { - return FALSE; - } - int src_node_id, des_node_id; - int src_node_side, des_node_side; - get_rr_node_side_and_index_in_sb_info(src_rr_node->drive_rr_nodes[inode], *src_sb, OUT_PORT, &src_node_side, &src_node_id); - get_rr_node_side_and_index_in_sb_info(des_rr_node->drive_rr_nodes[inode], *des_sb, OUT_PORT, &des_node_side, &des_node_id); - if (src_node_id != des_node_id) { - return FALSE; - } - if (src_node_side != des_node_side) { - return FALSE; - } - } - } - - return TRUE; -} - -/* check if two rr_nodes have a similar set of drive_rr_nodes - * for each drive_rr_node: - * 1. CHANX or CHANY: should have the same side and index - * 2. OPIN or IPIN: should have the same side and index - * 3. each drive_rr_switch should be the same - */ -boolean is_two_cb_rr_nodes_mirror(t_cb* src_cb, t_cb* des_cb, - t_rr_node* src_rr_node, t_rr_node* des_rr_node) { - - /* check driving rr_nodes */ - if ( src_rr_node->num_drive_rr_nodes != des_rr_node->num_drive_rr_nodes ) { - return FALSE; - } - for (int inode = 0; inode < src_rr_node->num_drive_rr_nodes; ++inode) { - /* node type should be the same */ - if ( src_rr_node->drive_rr_nodes[inode]->type - != des_rr_node->drive_rr_nodes[inode]->type) { - return FALSE; - } - /* switch type should be the same */ - if ( src_rr_node->drive_switches[inode] - != des_rr_node->drive_switches[inode]) { - return FALSE; - } - int src_node_id, des_node_id; - int src_node_side, des_node_side; - get_rr_node_side_and_index_in_cb_info(src_rr_node->drive_rr_nodes[inode], *src_cb, IN_PORT, &src_node_side, &src_node_id); - get_rr_node_side_and_index_in_cb_info(des_rr_node->drive_rr_nodes[inode], *des_cb, IN_PORT, &des_node_side, &des_node_id); - if (src_node_id != des_node_id) { - return FALSE; - } - if (src_node_side != des_node_side) { - return FALSE; - } - } - - return TRUE; -} - - -/* Idenify mirror Switch blocks - * Check each two switch blocks: - * 1. Number of channel/opin/ipin rr_nodes are same - * For channel rr_nodes - * 2. check if their track_ids (ptc_num) are same - * 3. Check if the switches (ids) are same - * For opin/ipin rr_nodes, - * 4. check if their parent type_descriptors same, - * 5. check if pin class id and pin id are same - * If all above are satisfied, the two switch blocks are mirrors! - */ -boolean is_two_switch_blocks_mirror(t_sb* src, t_sb* des) { - - /* check the numbers of sides */ - if (src->num_sides != des->num_sides) { - return FALSE; - } - - /* check the numbers/directionality of channel rr_nodes */ - for (int side = 0; side < src->num_sides; ++side) { - /* Ensure we have the same channel width on this side */ - if (src->chan_width[side] != des->chan_width[side]) { - return FALSE; - } - for (int itrack = 0; itrack < src->chan_width[side]; ++itrack) { - /* Check the directionality of each node */ - if (src->chan_rr_node_direction[side][itrack] != des->chan_rr_node_direction[side][itrack]) { - return FALSE; - } - /* Check the track_id of each node */ - if (src->chan_rr_node[side][itrack]->ptc_num != des->chan_rr_node[side][itrack]->ptc_num) { - return FALSE; - } - /* For OUT_PORT rr_node, we need to check fan-in */ - if (OUT_PORT != src->chan_rr_node_direction[side][itrack]) { - continue; /* skip IN_PORT */ - } - - if (FALSE == is_two_sb_rr_nodes_mirror(src, des, side, - src->chan_rr_node[side][itrack], - des->chan_rr_node[side][itrack])) { - return FALSE; - } - } - } - - /* check the numbers of opin_rr_nodes */ - for (int side = 0; side < src->num_sides; ++side) { - if (src->num_opin_rr_nodes[side] != des->num_opin_rr_nodes[side]) { - return FALSE; - } - } - - /* Make sure the number of conf bits are the same - * TODO: the check should be done when conf_bits are initialized when creating SBs - if ( (src->conf_bits_msb - src->conf_bits_lsb) - != (des->conf_bits_msb - des->conf_bits_lsb)) { - return FALSE; - } - */ - - return TRUE; -} - -/* Walk through all the switch blocks, - * Make one-to-one comparison, - * If we have a pair, update the 1st SB to be the base and label the 2nd as a mirror - * If the 1st SB is already a mirror to another, we will trace back to the upstream base and update the 2nd SB - */ -void assign_mirror_switch_blocks() { - /* A vector of coordinators of mirrors */ - std::vector mirror; - - /* Walkthrough each column, and find mirrors */ - for (int ix = 0; ix < (nx + 1); ++ix) { - for (int iy = 0; iy < (ny + 1); ++iy) { - bool is_unique_mirror = true; - for (size_t imirror = 0; imirror < mirror.size(); ++imirror) { - /* Do one-to-one comparison */ - if (TRUE == is_two_switch_blocks_mirror(mirror[imirror], &(sb_info[ix][iy]))) { - /* Find two equivalent switch blocks */ - is_unique_mirror = false; - /* configure the mirror of the second switch block */ - assign_switch_block_mirror(mirror[imirror], &(sb_info[ix][iy])); - break; - } - } - if (true == is_unique_mirror) { - /* add to unique mirror list */ - mirror.push_back(&(sb_info[ix][iy])); - } - } - } - - return; -} - -/* Validate the mirror of a switch block is the upstream - * with NULL mirror - */ -boolean validate_one_switch_block_mirror(t_sb* cur_sb) { - if (NULL == cur_sb->mirror) { - /* This is the upstream */ - return TRUE; - } - /* If the upstream has a mirror, there is a bug */ - if (NULL != cur_sb->mirror->mirror) { - return FALSE; - } - return TRUE; -} - -/* Validate the mirror of a switch block is the upstream - * with NULL mirror - */ -boolean validate_one_connection_block_mirror(t_cb* cur_cb) { - if (NULL == cur_cb->mirror) { - /* This is the upstream */ - return TRUE; - } - /* If the upstream has a mirror, there is a bug */ - if (NULL != cur_cb->mirror->mirror) { - return FALSE; - } - return TRUE; -} - -/* update the mirror of each switch block */ -void update_one_switch_block_mirror(t_sb* cur_sb) { - - if (NULL == cur_sb->mirror) { - /* This is the upstream */ - return; - } - - /* Assign mirror of the first SB to the second SB */ - /* traceback to the upstream */ - t_sb* temp = cur_sb->mirror; - while (NULL != temp->mirror) { - /* go to the next */ - temp = temp->mirror; - } - /* We reach the upstream, ensure its mirror is empty */ - assert(NULL == temp->mirror); - cur_sb->mirror = temp; - - return; -} - -/* update the mirror of each switch block */ -void update_one_connection_block_mirror(t_cb* cur_cb) { - - if (NULL == cur_cb->mirror) { - /* This is the upstream */ - return; - } - - /* Assign mirror of the first SB to the second SB */ - /* traceback to the upstream */ - t_cb* temp = cur_cb->mirror; - while (NULL != temp->mirror) { - /* go to the next */ - temp = temp->mirror; - } - /* We reach the upstream, ensure its mirror is empty */ - assert(NULL == temp->mirror); - cur_cb->mirror = temp; - - return; -} - - -/* Validate the mirror of each switch block is the upstream */ -boolean validate_mirror_switch_blocks() { - boolean ret = TRUE; - - /* Walkthrough each column, and find mirrors */ - for (int ix = 0; ix < (nx + 1); ++ix) { - for (int iy = 0; iy < (ny + 1); ++iy) { - if (FALSE == validate_one_switch_block_mirror(&(sb_info[ix][iy]))) { - ret = FALSE; - } - } - } - - return ret; -} - - -/* Validate the mirror of each connection block is the upstream */ -boolean validate_mirror_connection_blocks() { - boolean ret = TRUE; - - /* X - channels [1...nx][0..ny]*/ - for (int iy = 0; iy < (ny + 1); iy++) { - for (int ix = 1; ix < (nx + 1); ix++) { - if (FALSE == validate_one_connection_block_mirror(&(cbx_info[ix][iy]))) { - ret = FALSE; - } - } - } - - /* Y - channels [1...ny][0..nx]*/ - for (int ix = 0; ix < (nx + 1); ix++) { - for (int iy = 1; iy < (ny + 1); iy++) { - if (FALSE == validate_one_connection_block_mirror(&(cby_info[ix][iy]))) { - ret = FALSE; - } - } - } - - return ret; -} - - -/* Validate the mirror of each switch block is the upstream */ -void update_mirror_switch_blocks() { - - /* Walkthrough each column, and find mirrors */ - for (int ix = 0; ix < (nx + 1); ++ix) { - for (int iy = 0; iy < (ny + 1); ++iy) { - update_one_switch_block_mirror(&(sb_info[ix][iy])); - } - } - - return; -} - -/* Validate the mirror of each connection block is the upstream */ -void update_mirror_connection_blocks() { - - /* X - channels [1...nx][0..ny]*/ - for (int iy = 0; iy < (ny + 1); iy++) { - for (int ix = 1; ix < (nx + 1); ix++) { - update_one_connection_block_mirror(&(cbx_info[ix][iy])); - } - } - - /* Y - channels [1...ny][0..nx]*/ - for (int ix = 0; ix < (nx + 1); ix++) { - for (int iy = 1; iy < (ny + 1); iy++) { - update_one_connection_block_mirror(&(cby_info[ix][iy])); - } - } - - return; -} - - -void print_mirror_switch_block_stats() { - int num_mirror_sb = 0; - - /* Walkthrough each column, and find mirrors */ - for (int ix = 0; ix < (nx + 1); ++ix) { - for (int iy = 0; iy < (ny + 1); ++iy) { - if (NULL == sb_info[ix][iy].mirror) { - num_mirror_sb++; - } - } - } - - /* Print stats */ - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d independent switch blocks from %d switch blocks.\n", - num_mirror_sb, (nx + 1) * (ny + 1) ); - - return; -} - -void print_mirror_connection_block_stats() { - int num_mirror_cbx = 0; - int num_mirror_cby = 0; - - /* X - channels [1...nx][0..ny]*/ - for (int iy = 0; iy < (ny + 1); iy++) { - for (int ix = 1; ix < (nx + 1); ix++) { - if (NULL == cbx_info[ix][iy].mirror) { - num_mirror_cbx++; - } - } - } - - /* Y - channels [1...ny][0..nx]*/ - for (int ix = 0; ix < (nx + 1); ix++) { - for (int iy = 1; iy < (ny + 1); iy++) { - if (NULL == cby_info[ix][iy].mirror) { - num_mirror_cby++; - } - } - } - - /* Print stats */ - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d independent connection blocks from %d X-channel connection blocks.\n", - num_mirror_cbx, (nx + 0) * (ny + 1) ); - - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d independent connection blocks from %d Y-channel connection blocks.\n", - num_mirror_cby, (nx + 1) * (ny + 0) ); - - return; -} - -void identify_mirror_switch_blocks() { - - /* Assign the mirror of each switch block */ - assign_mirror_switch_blocks(); - - /* Ensure all the mirror are the upstream */ - /* update_mirror_switch_blocks(); */ - - /* Validate the mirror of switch blocks, everyone should be the upstream */ - assert(TRUE == validate_mirror_switch_blocks()); - - /* print the stats */ - print_mirror_switch_block_stats(); - - return; -} - -/* Idenify mirror connection blocks - * Check each two connection blocks: - * 1. Number of channel/opin/ipin rr_nodes are same - * For channel rr_nodes - * 2. check if their track_ids (ptc_num) are same - * 3. Check if the switches (ids) are same - * For opin/ipin rr_nodes, - * 4. check if their parent type_descriptors same, - * 5. check if pin class id and pin id are same - * If all above are satisfied, the two switch blocks are mirrors! - */ -boolean is_two_connection_blocks_mirror(t_cb* src, t_cb* des) { - - /* check the numbers of sides */ - if (src->num_sides != des->num_sides) { - return FALSE; - } - - /* check the numbers/directionality of channel rr_nodes */ - for (int side = 0; side < src->num_sides; ++side) { - /* Ensure we have the same channel width on this side */ - if (src->chan_width[side] != des->chan_width[side]) { - return FALSE; - } - for (int itrack = 0; itrack < src->chan_width[side]; ++itrack) { - /* Check the directionality of each node */ - if (src->chan_rr_node_direction[side][itrack] != des->chan_rr_node_direction[side][itrack]) { - return FALSE; - } - /* Check the track_id of each node */ - if (src->chan_rr_node[side][itrack]->ptc_num != des->chan_rr_node[side][itrack]->ptc_num) { - return FALSE; - } - } - } - - /* check the equivalence of ipins */ - for (int side = 0; side < src->num_sides; ++side) { - /* Ensure we have the same number of IPINs on this side */ - if (src->num_ipin_rr_nodes[side] != des->num_ipin_rr_nodes[side]) { - return FALSE; - } - for (int inode = 0; inode < src->num_ipin_rr_nodes[side]; ++inode) { - if (FALSE == is_two_cb_rr_nodes_mirror(src, des, - src->ipin_rr_node[side][inode], - des->ipin_rr_node[side][inode])) { - return FALSE; - } - } - } - - /* Make sure the number of conf bits are the same */ - if ( (src->conf_bits_msb - src->conf_bits_lsb) - != (des->conf_bits_msb - des->conf_bits_lsb)) { - return FALSE; - } - - return TRUE; -} - -void assign_mirror_connection_blocks() { - std::vector cbx_mirror; - std::vector cby_mirror; - - /* Make sure a clean start */ - cbx_mirror.clear(); - - /* X - channels [1...nx][0..ny]*/ - for (int iy = 0; iy < (ny + 1); ++iy) { - for (int ix = 1; ix < (nx + 1); ++ix) { - bool is_unique_mirror = true; - for (size_t id = 0; id < cbx_mirror.size(); ++id) { - /* Do one-to-one comparison */ - if (TRUE == is_two_connection_blocks_mirror(cbx_mirror[id], &(cbx_info[ix][iy]))) { - /* configure the mirror of the second switch block */ - assign_connection_block_mirror(cbx_mirror[id], &(cbx_info[ix][iy])); - /* Raise a flag and later add it to the unique mirror list if the two switch blocks are not equivalent */ - is_unique_mirror = false; - break; - } - } - /* Update the mirror list if necessary */ - if (true == is_unique_mirror) { - cbx_mirror.push_back(&(cbx_info[ix][iy])); - } - } - } - - /* Make sure a clean start */ - cby_mirror.clear(); - - /* Y - channels [1...ny][0..nx]*/ - for (int ix = 0; ix < (nx + 1); ++ix) { - for (int iy = 1; iy < (ny + 1); ++iy) { - bool is_unique_mirror = true; - for (size_t id = 0; id < cby_mirror.size(); ++id) { - /* Do one-to-one comparison */ - if (TRUE == is_two_connection_blocks_mirror(cby_mirror[id], &(cby_info[ix][iy]))) { - /* configure the mirror of the second switch block */ - assign_connection_block_mirror(cby_mirror[id], &(cby_info[ix][iy])); - /* Raise a flag and later add it to the unique mirror list if the two switch blocks are not equivalent */ - is_unique_mirror = false; - break; - } - } - /* Update the mirror list if necessary */ - if (true == is_unique_mirror) { - cby_mirror.push_back(&(cby_info[ix][iy])); - } - } - } - - return; -} - -/* Idenify mirror Connection blocks */ -void identify_mirror_connection_blocks() { - - /* Assign the mirror of each switch block */ - assign_mirror_connection_blocks(); - - /* Ensure all the mirror are the upstream */ - /* - update_mirror_connection_blocks(); - */ - - /* Validate the mirror of switch blocks, everyone should be the upstream */ - assert(TRUE == validate_mirror_connection_blocks()); - - /* print the stats */ - print_mirror_connection_block_stats(); - - return; -} - -/* Build a RRChan Object with the given channel type and coorindators */ -static -RRChan build_one_rr_chan(t_rr_type chan_type, size_t chan_x, size_t chan_y, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, int num_segments, - t_rr_indexed_data* LL_rr_indexed_data) { - int chan_width = 0; - t_rr_node** chan_rr_nodes = NULL; - - /* Create a rr_chan object and check if it is unique in the graph */ - RRChan rr_chan; - /* Fill the information */ - rr_chan.set_type(chan_type); - - /* Collect rr_nodes for this channel */ - chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, chan_x, chan_y, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - - /* Reserve */ - /* rr_chan.reserve_node(size_t(chan_width)); */ - - /* Fill the rr_chan */ - for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { - int cost_index = chan_rr_nodes[itrack]->cost_index; - int iseg = LL_rr_indexed_data[cost_index].seg_index; - /* Check */ - assert((!(iseg < 0))&&(iseg < num_segments)); - - rr_chan.add_node(chan_rr_nodes[itrack], size_t(iseg)); - } - - /* Free rr_nodes */ - my_free(chan_rr_nodes); - - return rr_chan; -} - -void print_device_rr_chan_stats(DeviceRRChan& LL_device_rr_chan) { - /* Print stats */ - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d independent routing channel from %d X-direction routing channels.\n", - LL_device_rr_chan.get_num_modules(CHANX), (nx + 0) * (ny + 1) ); - - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d independent routing channel from %d Y-direction routing channels.\n", - LL_device_rr_chan.get_num_modules(CHANY), (nx + 1) * (ny + 0) ); - -} - -/* Build the list of unique routing channels */ -DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, int num_segments, - t_rr_indexed_data* LL_rr_indexed_data) { - /* Create an object of DeviceRRChan */ - DeviceRRChan LL_device_rr_chan; - - /* Initialize array of rr_chan inside the device */ - LL_device_rr_chan.init_module_ids(nx + 1, ny + 1); - - /* For X-direction routing channel */ - for (size_t iy = 0; iy < size_t(ny + 1); iy++) { - for (size_t ix = 1; ix < size_t(nx + 1); ix++) { - /* Create a rr_chan object and check if it is unique in the graph */ - RRChan rr_chan = build_one_rr_chan(CHANX, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - num_segments, LL_rr_indexed_data); - /* check and add this rr_chan to the mirror list */ - LL_device_rr_chan.add_one_chan_module(CHANX, ix, iy, rr_chan); - } - } - - /* For X-direction routing channel */ - for (size_t ix = 0; ix < size_t(nx + 1); ix++) { - for (size_t iy = 1; iy < size_t(ny + 1); iy++) { - /* Create a rr_chan object and check if it is unique in the graph */ - RRChan rr_chan = build_one_rr_chan(CHANY, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - num_segments, LL_rr_indexed_data); - /* check and add this rr_chan to the mirror list */ - LL_device_rr_chan.add_one_chan_module(CHANY, ix, iy, rr_chan); - } - } - - print_device_rr_chan_stats(LL_device_rr_chan); - - return LL_device_rr_chan; -} - -/* Build a General Switch Block (GSB) - * which includes: - * [I] A Switch Box subckt consists of following ports: - * 1. Channel Y [x][y] inputs - * 2. Channel X [x+1][y] inputs - * 3. Channel Y [x][y-1] outputs - * 4. Channel X [x][y] outputs - * 5. Grid[x][y+1] Right side outputs pins - * 6. Grid[x+1][y+1] Left side output pins - * 7. Grid[x+1][y+1] Bottom side output pins - * 8. Grid[x+1][y] Top side output pins - * 9. Grid[x+1][y] Left side output pins - * 10. Grid[x][y] Right side output pins - * 11. Grid[x][y] Top side output pins - * 12. Grid[x][y+1] Bottom side output pins - * - * -------------- -------------- - * | | CBY | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX & CBX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - * For channels chanY with INC_DIRECTION on the top side, they should be marked as outputs - * For channels chanY with DEC_DIRECTION on the top side, they should be marked as inputs - * For channels chanY with INC_DIRECTION on the bottom side, they should be marked as inputs - * For channels chanY with DEC_DIRECTION on the bottom side, they should be marked as outputs - * For channels chanX with INC_DIRECTION on the left side, they should be marked as inputs - * For channels chanX with DEC_DIRECTION on the left side, they should be marked as outputs - * For channels chanX with INC_DIRECTION on the right side, they should be marked as outputs - * For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs - * - * [II] A X-direction Connection Block [x][y] - * The connection block shares the same routing channel[x][y] with the Switch Block - * We just need to fill the ipin nodes at TOP and BOTTOM sides - * as well as properly fill the ipin_grid_side information - * [III] A Y-direction Connection Block [x][y+1] - * The connection block shares the same routing channel[x][y+1] with the Switch Block - * We just need to fill the ipin nodes at LEFT and RIGHT sides - * as well as properly fill the ipin_grid_side information - */ -static -RRGSB build_rr_gsb(DeviceCoordinator& device_range, - size_t sb_x, size_t sb_y, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, int num_segments, - t_rr_indexed_data* LL_rr_indexed_data) { - /* Create an object to return */ - RRGSB rr_gsb; - - /* Check */ - assert(sb_x <= device_range.get_x()); - assert(sb_y <= device_range.get_y()); - - /* Coordinator initialization */ - rr_gsb.set_coordinator(sb_x, sb_y); - - /* Basic information*/ - rr_gsb.init_num_sides(4); /* Fixed number of sides */ - - /* Find all rr_nodes of channels */ - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - /* Local variables inside this for loop */ - Side side_manager(side); - DeviceCoordinator coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side()); - size_t ix = coordinator.get_x(); - size_t iy = coordinator.get_y(); - RRChan rr_chan; - int temp_num_opin_rr_nodes[2] = {0,0}; - t_rr_node** temp_opin_rr_node[2] = {NULL, NULL}; - enum e_side opin_grid_side[2] = {NUM_SIDES, NUM_SIDES}; - enum PORTS chan_dir_to_port_dir_mapping[2] = {OUT_PORT, IN_PORT}; /* 0: INC_DIRECTION => ?; 1: DEC_DIRECTION => ? */ - - switch (side) { - case TOP: /* TOP = 0 */ - /* For the bording, we should take special care */ - if (sb_y == device_range.get_y()) { - rr_gsb.clear_one_side(side_manager.get_side()); - break; - } - /* Routing channels*/ - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_rr_chan(CHANY, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - num_segments, LL_rr_indexed_data); - chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ - chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ - - /* Build the Switch block: opin and opin_grid_side */ - /* Include Grid[x][y+1] RIGHT side outputs pins */ - temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], - OPIN, sb_x, sb_y + 1, 1, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* Include Grid[x+1][y+1] Left side output pins */ - temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], - OPIN, sb_x + 1, sb_y + 1, 3, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - - /* Assign grid side of OPIN */ - /* Grid[x][y+1] RIGHT side outputs pins */ - opin_grid_side[0] = RIGHT; - /* Grid[x+1][y+1] left side outputs pins */ - opin_grid_side[1] = LEFT; - break; - case RIGHT: /* RIGHT = 1 */ - /* For the bording, we should take special care */ - if (sb_x == device_range.get_x()) { - rr_gsb.clear_one_side(side_manager.get_side()); - break; - } - /* Routing channels*/ - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Collect rr_nodes for Tracks for top: chany[x][y+1] */ - /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_rr_chan(CHANX, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - num_segments, LL_rr_indexed_data); - chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ - chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ - - /* Build the Switch block: opin and opin_grid_side */ - /* include Grid[x+1][y+1] Bottom side output pins */ - temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], - OPIN, sb_x + 1, sb_y + 1, 2, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* include Grid[x+1][y] Top side output pins */ - temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], - OPIN, sb_x + 1, sb_y, 0, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* Assign grid side of OPIN */ - /* Grid[x+1][y+1] BOTTOM side outputs pins */ - opin_grid_side[0] = BOTTOM; - /* Grid[x+1][y] TOP side outputs pins */ - opin_grid_side[1] = TOP; - break; - case BOTTOM: /* BOTTOM = 2*/ - /* For the bording, we should take special care */ - if (sb_y == 0) { - rr_gsb.clear_one_side(side_manager.get_side()); - break; - } - /* Routing channels*/ - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Collect rr_nodes for Tracks for bottom: chany[x][y] */ - /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_rr_chan(CHANY, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - num_segments, LL_rr_indexed_data); - chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ - chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ - - /* Build the Switch block: opin and opin_grid_side */ - /* include Grid[x+1][y] Left side output pins */ - temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], - OPIN, sb_x + 1, sb_y, 3, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* include Grid[x][y] Right side output pins */ - temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], - OPIN, sb_x, sb_y, 1, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* Assign grid side of OPIN */ - /* Grid[x+1][y] LEFT side outputs pins */ - opin_grid_side[0] = LEFT; - /* Grid[x][y] RIGHT side outputs pins */ - opin_grid_side[1] = RIGHT; - break; - case LEFT: /* LEFT = 3 */ - /* For the bording, we should take special care */ - if (sb_x == 0) { - rr_gsb.clear_one_side(side_manager.get_side()); - break; - } - /* Routing channels*/ - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - /* Collect rr_nodes for Tracks for left: chanx[x][y] */ - /* Create a rr_chan object and check if it is unique in the graph */ - rr_chan = build_one_rr_chan(CHANX, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - num_segments, LL_rr_indexed_data); - chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ - chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ - - /* Build the Switch block: opin and opin_grid_side */ - /* include Grid[x][y+1] Bottom side outputs pins */ - temp_opin_rr_node[0] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[0], - OPIN, sb_x, sb_y + 1, 2, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* include Grid[x][y] Top side output pins */ - temp_opin_rr_node[1] = get_grid_side_pin_rr_nodes(&temp_num_opin_rr_nodes[1], - OPIN, sb_x, sb_y, 0, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - - /* Grid[x][y+1] BOTTOM side outputs pins */ - opin_grid_side[0] = BOTTOM; - /* Grid[x][y] TOP side outputs pins */ - opin_grid_side[1] = TOP; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid side index!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Organize a vector of port direction */ - if (0 < rr_chan.get_chan_width()) { - std::vector rr_chan_dir; - rr_chan_dir.resize(rr_chan.get_chan_width()); - for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { - /* Identify the directionality, record it in rr_node_direction */ - if (INC_DIRECTION == rr_chan.get_node(itrack)->direction) { - rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[0]; - } else { - assert (DEC_DIRECTION == rr_chan.get_node(itrack)->direction); - rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[1]; - } - } - /* Fill chan_rr_nodes */ - rr_gsb.add_chan_node(side_manager.get_side(), rr_chan, rr_chan_dir); - } - - /* Fill opin_rr_nodes */ - /* Copy from temp_opin_rr_node to opin_rr_node */ - for (int inode = 0; inode < temp_num_opin_rr_nodes[0]; ++inode) { - /* Skip Fc = 0 pins, they should NOT appear in the GSB connection */ - if (0. == grid[temp_opin_rr_node[0][inode]->xlow][temp_opin_rr_node[0][inode]->ylow].type->Fc[temp_opin_rr_node[0][inode]->ptc_num]) { - continue; - } - /* Grid[x+1][y+1] Bottom side outputs pins */ - rr_gsb.add_opin_node(temp_opin_rr_node[0][inode], side_manager.get_side(), opin_grid_side[0]); - } - for (int inode = 0; inode < temp_num_opin_rr_nodes[1]; ++inode) { - /* Skip Fc = 0 pins, they should NOT appear in the GSB connection */ - if (0. == grid[temp_opin_rr_node[1][inode]->xlow][temp_opin_rr_node[1][inode]->ylow].type->Fc[temp_opin_rr_node[1][inode]->ptc_num]) { - continue; - } - /* Grid[x+1][y] TOP side outputs pins */ - rr_gsb.add_opin_node(temp_opin_rr_node[1][inode], side_manager.get_side(), opin_grid_side[1]); - } - - /* Clean ipin_rr_nodes */ - /* We do not have any IPIN for a Switch Block */ - rr_gsb.clear_ipin_nodes(side_manager.get_side()); - - /* Free */ - temp_num_opin_rr_nodes[0] = 0; - my_free(temp_opin_rr_node[0]); - temp_num_opin_rr_nodes[1] = 0; - my_free(temp_opin_rr_node[1]); - /* Set them to NULL, avoid double free errors */ - temp_opin_rr_node[0] = NULL; - temp_opin_rr_node[1] = NULL; - opin_grid_side[0] = NUM_SIDES; - opin_grid_side[1] = NUM_SIDES; - } - - /* Side: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - /* Local variables inside this for loop */ - Side side_manager(side); - size_t ix; - size_t iy; - enum e_side chan_side; - int num_temp_ipin_rr_nodes = 0; - t_rr_node** temp_ipin_rr_node = NULL; - enum e_side ipin_rr_node_grid_side; - - switch (side) { - case TOP: /* TOP = 0 */ - /* For the bording, we should take special care */ - /* Check if left side chan width is 0 or not */ - chan_side = LEFT; - /* Build the connection block: ipin and ipin_grid_side */ - /* BOTTOM side INPUT Pins of Grid[x][y+1] */ - ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y() + 1; - ipin_rr_node_grid_side = BOTTOM; - break; - case RIGHT: /* RIGHT = 1 */ - /* For the bording, we should take special care */ - /* Check if TOP side chan width is 0 or not */ - chan_side = TOP; - /* Build the connection block: ipin and ipin_grid_side */ - /* LEFT side INPUT Pins of Grid[x+1][y+1] */ - ix = rr_gsb.get_sb_x() + 1; - iy = rr_gsb.get_sb_y() + 1; - ipin_rr_node_grid_side = LEFT; - break; - case BOTTOM: /* BOTTOM = 2*/ - /* For the bording, we should take special care */ - /* Check if left side chan width is 0 or not */ - chan_side = LEFT; - /* Build the connection block: ipin and ipin_grid_side */ - /* TOP side INPUT Pins of Grid[x][y] */ - ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y(); - ipin_rr_node_grid_side = TOP; - break; - case LEFT: /* LEFT = 3 */ - /* For the bording, we should take special care */ - /* Check if left side chan width is 0 or not */ - chan_side = TOP; - /* Build the connection block: ipin and ipin_grid_side */ - /* RIGHT side INPUT Pins of Grid[x][y+1] */ - ix = rr_gsb.get_sb_x(); - iy = rr_gsb.get_sb_y() + 1; - ipin_rr_node_grid_side = RIGHT; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid side index!\n", - __FILE__, __LINE__); - exit(1); - } - - /* If there is no channel at this side, we skip ipin_node annotation */ - if (0 == rr_gsb.get_chan_width(chan_side)) { - continue; - } - /* For bottom side: Skip IPIN collection if the offset of the grid is not zero! - * (it means this CB is in the middle of a grid (whose height > 1) - * - * | | | | - * | | | | - * | Grid | | Grid | - * +------------+ | | - * IPIN nodes IPIN nodes - * exist do NOT exist - */ - if ((BOTTOM == ipin_rr_node_grid_side) && (0 < grid[ix][iy].offset)) { - continue; - } - if ((TOP == ipin_rr_node_grid_side) && (grid[ix][iy].offset != grid[ix][iy].type->height - 1)) { - continue; - } - /* Collect IPIN rr_nodes*/ - temp_ipin_rr_node = get_grid_side_pin_rr_nodes(&(num_temp_ipin_rr_nodes), - IPIN, ix, iy, ipin_rr_node_grid_side, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - /* Fill the ipin nodes of RRGSB */ - for (int inode = 0; inode < num_temp_ipin_rr_nodes; ++inode) { - /* Skip Fc = 0 pins, they should NOT appear in the GSB connection */ - if (0. == grid[temp_ipin_rr_node[inode]->xlow][temp_ipin_rr_node[inode]->ylow].type->Fc[temp_ipin_rr_node[inode]->ptc_num]) { - continue; - } - - rr_gsb.add_ipin_node(temp_ipin_rr_node[inode], side_manager.get_side(), ipin_rr_node_grid_side); - } - /* Free */ - num_temp_ipin_rr_nodes = 0; - my_free(temp_ipin_rr_node); - } - - return rr_gsb; -} - -/* sort drive_rr_nodes of a rr_node inside rr_gsb subject to the index of rr_gsb array */ -static -void sort_rr_gsb_one_ipin_node_drive_rr_nodes(const RRGSB& rr_gsb, - t_rr_node* ipin_node, - enum e_side ipin_chan_side) { - /* Create a copy of the edges and switches of this node */ - std::vector sorted_drive_nodes; - std::vector sorted_drive_switches; - std::vector sorted_drive_nodes_chan_node_index; - - /* Ensure a clean start and avoid frequent realloc */ - sorted_drive_nodes.reserve(ipin_node->num_drive_rr_nodes); - sorted_drive_switches.reserve(ipin_node->num_drive_rr_nodes); - sorted_drive_nodes_chan_node_index.reserve(ipin_node->num_drive_rr_nodes); - - /* Build the vectors w.r.t. to the order of node_type and ptc_num */ - for (int i_from_node = 0; i_from_node < ipin_node->num_drive_rr_nodes; ++i_from_node) { - int i_from_node_track_index = rr_gsb.get_chan_node_index(ipin_chan_side, ipin_node->drive_rr_nodes[i_from_node]); - /* We must have a valide node index for CHANX and CHANY */ - if ( (CHANX == ipin_node->drive_rr_nodes[i_from_node]->type) - || (CHANY == ipin_node->drive_rr_nodes[i_from_node]->type) ) { - assert (-1 != i_from_node_track_index); - } - /* For blank edges: directly push_back */ - if (0 == sorted_drive_nodes.size()) { - sorted_drive_nodes.push_back(ipin_node->drive_rr_nodes[i_from_node]); - sorted_drive_switches.push_back(ipin_node->drive_switches[i_from_node]); - sorted_drive_nodes_chan_node_index.push_back(i_from_node_track_index); - continue; - } - - /* Start sorting since the edges are not empty */ - size_t insert_pos = sorted_drive_nodes.size(); /* the pos to insert. By default, it is the last element */ - for (size_t j_from_node = 0; j_from_node < sorted_drive_nodes.size(); ++j_from_node) { - /* Sort by node_type and ptc_num */ - if (ipin_node->drive_rr_nodes[i_from_node]->type < sorted_drive_nodes[j_from_node]->type) { - /* iedge should be ahead of jedge */ - insert_pos = j_from_node; - break; /* least type should stay in the front of the vector */ - } else if (ipin_node->drive_rr_nodes[i_from_node]->type - == sorted_drive_nodes[j_from_node]->type) { - /* Now a lower ptc_num will win */ - if ( i_from_node_track_index < sorted_drive_nodes_chan_node_index[j_from_node] ) { - insert_pos = j_from_node; - break; /* least type should stay in the front of the vector */ - } - } - } - /* We find the position, inserted to the vector */ - sorted_drive_nodes.insert(sorted_drive_nodes.begin() + insert_pos, ipin_node->drive_rr_nodes[i_from_node]); - sorted_drive_switches.insert(sorted_drive_switches.begin() + insert_pos, ipin_node->drive_switches[i_from_node]); - sorted_drive_nodes_chan_node_index.insert(sorted_drive_nodes_chan_node_index.begin() + insert_pos, i_from_node_track_index); - } - - /* Overwrite the edges and switches with sorted numbers */ - for (size_t iedge = 0; iedge < sorted_drive_nodes.size(); ++iedge) { - ipin_node->drive_rr_nodes[iedge] = sorted_drive_nodes[iedge]; - } - for (size_t iedge = 0; iedge < sorted_drive_switches.size(); ++iedge) { - ipin_node->drive_switches[iedge] = sorted_drive_switches[iedge]; - } - - return; -} - -/* sort drive_rr_nodes of a rr_node inside rr_gsb subject to the index of rr_gsb array */ -static -void sort_rr_gsb_one_chan_node_drive_rr_nodes(const RRGSB& rr_gsb, - enum e_side chan_side, - size_t track_id) { - - /* If this is a passing wire, we return directly. - * The passing wire will be handled in other GSBs - */ - if (true == rr_gsb.is_sb_node_passing_wire(chan_side, track_id)) { - return; - } - - /* Get the chan_node */ - t_rr_node* chan_node = rr_gsb.get_chan_node(chan_side, track_id); - - /* Create a copy of the edges and switches of this node */ - std::vector sorted_drive_nodes; - std::vector sorted_drive_switches; - std::vector sorted_drive_nodes_from_node_index; - - /* Ensure a clean start and avoid frequent realloc */ - sorted_drive_nodes.reserve(chan_node->num_drive_rr_nodes); - sorted_drive_switches.reserve(chan_node->num_drive_rr_nodes); - sorted_drive_nodes_from_node_index.reserve(chan_node->num_drive_rr_nodes); - - /* Build the vectors w.r.t. to the order of node_type and ptc_num */ - for (int i_from_node = 0; i_from_node < chan_node->num_drive_rr_nodes; ++i_from_node) { - enum e_side i_from_node_side = NUM_SIDES; - int i_from_node_index = -1; - rr_gsb.get_node_side_and_index(chan_node->drive_rr_nodes[i_from_node], - IN_PORT, &i_from_node_side, &i_from_node_index); - /* check */ - assert ( (NUM_SIDES != i_from_node_side) && (-1 != i_from_node_index) ); - /* For blank edges: directly push_back */ - if (0 == sorted_drive_nodes.size()) { - sorted_drive_nodes.push_back(chan_node->drive_rr_nodes[i_from_node]); - sorted_drive_switches.push_back(chan_node->drive_switches[i_from_node]); - sorted_drive_nodes_from_node_index.push_back(i_from_node_index); - continue; - } - - /* Start sorting since the edges are not empty */ - size_t insert_pos = sorted_drive_nodes.size(); /* the pos to insert. By default, it is the last element */ - for (size_t j_from_node = 0; j_from_node < sorted_drive_nodes.size(); ++j_from_node) { - /* Sort by node_type and ptc_num */ - if (chan_node->drive_rr_nodes[i_from_node]->type < sorted_drive_nodes[j_from_node]->type) { - /* iedge should be ahead of jedge */ - insert_pos = j_from_node; - break; /* least type should stay in the front of the vector */ - } else if (chan_node->drive_rr_nodes[i_from_node]->type - == sorted_drive_nodes[j_from_node]->type) { - /* For channel node, we do not know the node direction - * But we are pretty sure it is either IN_PORT or OUT_PORT - * So we just try and find what is valid - */ - - /* Now a lower ptc_num will win */ - if ( i_from_node_index < sorted_drive_nodes_from_node_index[j_from_node]) { - insert_pos = j_from_node; - break; /* least type should stay in the front of the vector */ - } - } - } - /* We find the position, inserted to the vector */ - sorted_drive_nodes.insert(sorted_drive_nodes.begin() + insert_pos, chan_node->drive_rr_nodes[i_from_node]); - sorted_drive_switches.insert(sorted_drive_switches.begin() + insert_pos, chan_node->drive_switches[i_from_node]); - sorted_drive_nodes_from_node_index.insert(sorted_drive_nodes_from_node_index.begin() + insert_pos, i_from_node_index); - } - - /* Overwrite the edges and switches with sorted numbers */ - for (size_t iedge = 0; iedge < sorted_drive_nodes.size(); ++iedge) { - chan_node->drive_rr_nodes[iedge] = sorted_drive_nodes[iedge]; - } - for (size_t iedge = 0; iedge < sorted_drive_switches.size(); ++iedge) { - chan_node->drive_switches[iedge] = sorted_drive_switches[iedge]; - } - - return; - -} - -/* sort drive_rr_nodes of each rr_node subject to the index of rr_gsb array */ -static -void sort_rr_gsb_drive_rr_nodes(const RRGSB& rr_gsb) { - /* Sort the drive_rr_nodes for each rr_node */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side gsb_side_manager(side); - enum e_side gsb_side = gsb_side_manager.get_side(); - /* For IPIN node: sort drive_rr_nodes according to the index in the routing channels */ - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(gsb_side); ++inode) { - /* Get the chan side, so we have the routing tracks */ - enum e_side ipin_chan_side = rr_gsb.get_cb_chan_side(gsb_side); - sort_rr_gsb_one_ipin_node_drive_rr_nodes(rr_gsb, - rr_gsb.get_ipin_node(gsb_side, inode), - ipin_chan_side); - } - /* For CHANX | CHANY node: sort drive_rr_nodes according to the index in the routing channels */ - for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { - /* Bypass IN_PORT */ - if (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, inode)) { - continue; - } - /* Get the chan side, so we have the routing tracks */ - sort_rr_gsb_one_chan_node_drive_rr_nodes(rr_gsb, - gsb_side, - inode); - } - } - - return; -} - -/* Build a list of Switch blocks, each of which contains a collection of rr_nodes - * We will maintain a list of unique switch blocks, which will be outputted as a Verilog module - * Each switch block in the FPGA fabric will be an instance of these modules. - * We maintain a map from each instance to each module - */ -DeviceRRGSB build_device_rr_gsb(const bool& output_sb_xml, - const bool& compact_routing_hierarchy, - char* sb_xml_dir, - const int& LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, const int& num_segments, - t_rr_indexed_data* LL_rr_indexed_data) { - /* Timer */ - clock_t t_start; - clock_t t_end; - float run_time_sec; - - clock_t t_start_profiling; - clock_t t_end_profiling; - float run_time_sec_profiling = 0.; - - /* Start time count */ - t_start = clock(); - - /* Create an object */ - DeviceRRGSB LL_device_rr_gsb; - - /* Initialize */ - DeviceCoordinator sb_range((size_t)nx, (size_t)ny); - DeviceCoordinator reserve_range((size_t)nx + 1, (size_t)ny + 1); - LL_device_rr_gsb.reserve(reserve_range); - - size_t gsb_cnt = 0; - /* For each switch block, determine the size of array */ - for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) { - for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) { - gsb_cnt++; /* Update counter */ - const RRGSB& rr_gsb = build_rr_gsb(sb_range, ix, iy, - LL_num_rr_nodes, LL_rr_node, - LL_rr_node_indices, - num_segments, LL_rr_indexed_data); - - /* For profiling */ - t_start_profiling = clock(); - /* sort drive_rr_nodes */ - sort_rr_gsb_drive_rr_nodes(rr_gsb); - /* End time count */ - t_end_profiling = clock(); - run_time_sec_profiling += (float)(t_end_profiling - t_start_profiling) / CLOCKS_PER_SEC; - - /* Add to device_rr_gsb */ - DeviceCoordinator sb_coordinator = rr_gsb.get_sb_coordinator(); - LL_device_rr_gsb.add_rr_gsb(sb_coordinator, rr_gsb); - /* Print info */ - vpr_printf(TIO_MESSAGE_INFO, - "[%lu%] Backannotated GSB[%lu][%lu]\r", - 100 * gsb_cnt / ((sb_range.get_x() + 1)* (sb_range.get_y() + 1)), - ix, iy ); - } - } - /* Report number of unique mirrors */ - vpr_printf(TIO_MESSAGE_INFO, - "Backannotated %d switch blocks.\n", - (nx + 1) * (ny + 1) ); - - /* End time count */ - t_end = clock(); - - run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, "Edge sorting for Switch Block took %g seconds\n", run_time_sec_profiling); - vpr_printf(TIO_MESSAGE_INFO, "Backannotation of Switch Block took %g seconds\n\n", run_time_sec); - - if (true == output_sb_xml) { - create_dir_path(sb_xml_dir); - write_device_rr_gsb_to_xml(sb_xml_dir, LL_device_rr_gsb); - - /* Skip rotating mirror searching */ - vpr_printf(TIO_MESSAGE_INFO, - "Output XML description of Switch Blocks to %s.\n", - sb_xml_dir); - - } - - /* Build a list of unique modules for each Switch Block */ - /* Build a list of unique modules for each side of each Switch Block */ - if (true == compact_routing_hierarchy) { - LL_device_rr_gsb.build_unique_module(); - - vpr_printf(TIO_MESSAGE_INFO, - "Detect %lu routing segments used by switch blocks.\n", - LL_device_rr_gsb.get_num_segments()); - - /* Report number of unique CB Modules */ - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d unique connection blocks from %d X-channel connection blocks.\n", - LL_device_rr_gsb.get_num_cb_unique_module(CHANX), (nx + 0) * (ny + 1) ); - - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d unique connection blocks from %d Y-channel connection blocks.\n", - LL_device_rr_gsb.get_num_cb_unique_module(CHANY), (nx + 1) * (ny + 0) ); - - - /* Report number of unique SB modules */ - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d unique switch blocks from %d switch blocks.\n", - LL_device_rr_gsb.get_num_sb_unique_module(), (nx + 1) * (ny + 1) ); - - /* Report number of unique GSB modules */ - vpr_printf(TIO_MESSAGE_INFO, - "Detect %d unique GSBs from %d GSBs.\n", - LL_device_rr_gsb.get_num_sb_unique_module(), (nx + 1) * (ny + 1) ); - - /* Report number of unique mirrors */ - for (size_t side = 0; side < LL_device_rr_gsb.get_max_num_sides(); ++side) { - Side side_manager(side); - /* get segment ids */ - for (size_t iseg = 0; iseg < LL_device_rr_gsb.get_num_segments(); ++iseg) { - vpr_printf(TIO_MESSAGE_INFO, - "For side %s, segment id %lu: Detect %d independent switch blocks from %d switch blocks.\n", - side_manager.c_str(), LL_device_rr_gsb.get_segment_id(iseg), - LL_device_rr_gsb.get_num_sb_unique_submodule(side_manager.get_side(), iseg), - (nx + 1) * (ny + 1) ); - } - } - } - - /* End time count */ - t_end = clock(); - - run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, "Routing architecture uniquifying took %g seconds\n\n", run_time_sec); - - return LL_device_rr_gsb; -} - -/************************************************************************ - * End of file : fpga_x2p_unique_routing.c - ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h deleted file mode 100644 index ce8b3d999..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.h +++ /dev/null @@ -1,29 +0,0 @@ -/* Avoid repeated header inclusion */ -#ifndef FPGA_X2P_IDENTIFY_ROUTING -#define FPGA_X2P_IDENTIFY_ROUTING - -void identify_mirror_switch_blocks(); -void identify_mirror_connection_blocks(); - -DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, int num_segments, - t_rr_indexed_data* LL_rr_indexed_data); - -/* Build a list of Switch blocks, each of which contains a collection of rr_nodes - * We will maintain a list of unique switch blocks, which will be outputted as a Verilog module - * Each switch block in the FPGA fabric will be an instance of these modules. - * We maintain a map from each instance to each module - */ -DeviceRRGSB build_device_rr_gsb(const bool& output_sb_xml, - const bool& compact_routing_hierarchy, - char* sb_xml_dir, - const int& LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, const int& num_segments, - t_rr_indexed_data* LL_rr_indexed_data); - -/* Rotatable will be done in the next step -identify_rotatable_switch_blocks(); -identify_rotatable_connection_blocks(); -*/ - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c deleted file mode 100644 index e61a4defb..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ /dev/null @@ -1,3580 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "vtr_assert.h" -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" - -/* Include SPICE support headers*/ -#include "quicksort.h" -#include "linkedlist.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_utils.h" - -enum e_dir_err { - E_DIR_NOT_EXIST, - E_EXIST_BUT_NOT_DIR, - E_DIR_EXIST -}; - - -/***** Local Subroutines *****/ -static -enum e_dir_err try_access_dir(char* dir_path); - -/***** Subroutines *****/ -char* my_gettime() { - time_t current_time; - char* c_time_string; - - /* Obtain current time as seconds elapsed since the Epoch*/ - current_time = time(NULL); - - if (current_time == ((time_t)-1)) { - vpr_printf(TIO_MESSAGE_ERROR,"Failure to compute the current time.\n"); - exit(1); - } - - /* Convert to local time format*/ - c_time_string = ctime(¤t_time); - if (NULL == c_time_string) { - vpr_printf(TIO_MESSAGE_ERROR,"Failure to convert the current time.\n"); - exit(1); - } - /* Return it*/ - return c_time_string; -} - - -char* format_dir_path(char* dir_path) { - int len = strlen(dir_path); /* String length without the last "\0"*/ - int i; - char* ret = (char*)my_malloc(sizeof(char)*(len+2)); - - strcpy(ret,dir_path); - /* Replace all the "\" to "/"*/ - for (i=0; i -1; i--) { - if (split_token == local_copy[i]) { - split_pos = i; - break; - } - } - - /* Get the path and prog_name*/ - if (-1 == split_pos) { - /* In this case, the prog_path actually contains only the program name*/ - path = my_strdup("./");; - prog_name = my_strdup(local_copy); - } else if (len == split_pos) { - /* In this case the progrom name is NULL... actually the prog_path is a directory*/ - path = my_strdup(local_copy); - prog_name = NULL; - } else { - /* We have to split it!*/ - local_copy[split_pos] = '\0'; - path = my_strdup(local_copy); - prog_name = my_strdup(local_copy + split_pos + 1); - } - - /*Copy it to the return*/ - (*ret_path) = my_strdup(path); - (*ret_prog_name) = my_strdup(prog_name); - - /* Free useless resources */ - my_free(local_copy); - my_free(path); - my_free(prog_name); - - return 1; -} - -char* chomp_file_name_postfix(char* file_name) { - char* ret = NULL; - char* postfix = NULL; - - split_path_prog_name(file_name, '.', &ret, &postfix); - - my_free(postfix); - - return ret; -} - -/* Print SRAM bits, typically in a comment line */ -void fprint_commented_sram_bits(FILE* fp, - int num_sram_bits, int* sram_bits) { - int i; - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n",__FILE__,__LINE__); - exit(1); - } - - for (i = 0; i < num_sram_bits; i++) { - fprintf(fp, "%d", sram_bits[i]); - } - - return; -} - - -/* With a given spice_model_name, find the spice model and return its pointer - * If we find nothing, return NULL - */ -t_spice_model* find_name_matched_spice_model(char* spice_model_name, - int num_spice_model, - t_spice_model* spice_models) { - t_spice_model* ret = NULL; - int imodel; - int num_found = 0; - - for (imodel = 0; imodel < num_spice_model; imodel++) { - if (0 == strcmp(spice_model_name, spice_models[imodel].name)) { - ret = &(spice_models[imodel]); - num_found++; - } - } - - if (0 == num_found) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d])Fail to find a spice model match name: %s !\n", - __FILE__ ,__LINE__, spice_model_name); - exit(1); - } - - assert(1 == num_found); - - return ret; -} - -/* Get the default spice_model*/ -t_spice_model* get_default_spice_model(enum e_spice_model_type default_spice_model_type, - int num_spice_model, - t_spice_model* spice_models) { - t_spice_model* ret = NULL; - int i; - - for (i = 0; i < num_spice_model; i++) { - /* Find a MUX and it is set as default*/ - if ((default_spice_model_type == spice_models[i].type)&&(1 == spice_models[i].is_default)) { - /* Check if we have multiple default*/ - if (NULL != ret) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d])Both SPICE model(%s and %s) are set as default!\n", - __FILE__, __LINE__, ret->name, spice_models[i].name); - exit(1); - } else { - ret = &(spice_models[i]); - } - } - } - - return ret; -} - -/* Tasks: - * 1. Search the inv_spice_model_name of each ports of a spice_model - * 2. Copy the information from inverter spice model to higher level spice_models - */ -void config_spice_model_port_inv_spice_model(int num_spice_models, - t_spice_model* spice_model) { - int i, iport; - t_spice_model* inv_spice_model = NULL; - - for (i = 0; i < num_spice_models; i++) { - /* By pass inverters and buffers */ - if (SPICE_MODEL_INVBUF == spice_model[i].type) { - continue; - } - for (iport = 0; iport < spice_model[i].num_port; iport++) { - /* Now we bypass non BL/WL ports */ - if ((SPICE_MODEL_PORT_BL != spice_model[i].ports[iport].type) - && (SPICE_MODEL_PORT_BLB != spice_model[i].ports[iport].type) - && (SPICE_MODEL_PORT_WL != spice_model[i].ports[iport].type) - && (SPICE_MODEL_PORT_WLB != spice_model[i].ports[iport].type)) { - continue; - } - if (NULL == spice_model[i].ports[iport].inv_spice_model_name) { - inv_spice_model = get_default_spice_model(SPICE_MODEL_INVBUF, - num_spice_models, spice_model); - } else { - inv_spice_model = find_name_matched_spice_model(spice_model[i].ports[iport].inv_spice_model_name, - num_spice_models, spice_model); - /* We should find a buffer spice_model*/ - if (NULL == inv_spice_model) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Fail to find inv_spice_model to the port(name=%s) of spice_model(name=%s)!\n", - __FILE__, __LINE__, spice_model[i].ports[iport].prefix, spice_model[i].name); - exit(1); - } - } - /* Config */ - spice_model[i].ports[iport].inv_spice_model = inv_spice_model; - } - } - return; -} - -/* Find a spice model port by given name */ -t_spice_model_port* find_spice_model_port_by_name(t_spice_model* cur_spice_model, - char* port_name) { - int iport; - t_spice_model_port* port = NULL; - int cnt = 0; - - for (iport = 0; iport < cur_spice_model->num_port; iport++) { - if (0 == strcmp(cur_spice_model->ports[iport].prefix, port_name)) { - port = &(cur_spice_model->ports[iport]); - cnt++; - } - } - - assert ((0 == cnt) || (1 == cnt)); - - return port; -} - -void config_one_spice_model_buffer(int num_spice_models, - t_spice_model* spice_model, - t_spice_model* cur_spice_model, - t_spice_model_buffer* cur_spice_model_buffer) { - t_spice_model* buf_spice_model = NULL; - char* location_map = NULL; - - /* Check if this spice model has input buffers */ - if (1 == cur_spice_model_buffer->exist) { - buf_spice_model = find_name_matched_spice_model(cur_spice_model_buffer->spice_model_name, - num_spice_models, spice_model); - /* We should find a buffer spice_model*/ - if (NULL == buf_spice_model) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Fail to find inv/buffer spice_model to the input buffer of spice_model(name=%s)!\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - /* Backup location map */ - location_map = cur_spice_model_buffer->location_map; - /* Copy the information from found spice model to current spice model*/ - memcpy(cur_spice_model_buffer, buf_spice_model->design_tech_info.buffer_info, sizeof(t_spice_model_buffer)); - /* Recover the spice_model_name and exist */ - cur_spice_model_buffer->exist = 1; - cur_spice_model_buffer->spice_model_name = my_strdup(buf_spice_model->name); - cur_spice_model_buffer->spice_model = buf_spice_model; - cur_spice_model_buffer->location_map = location_map; - } - - return; -} - -/* Tasks: - * 1. Search the spice_model_name of input and output buffer and link to the spice_model - * 2. Copy the information from input/output buffer spice model to higher level spice_models - */ -void config_spice_model_input_output_buffers_pass_gate(int num_spice_models, - t_spice_model* spice_model) { - int i; - t_spice_model* pgl_spice_model = NULL; - - for (i = 0; i < num_spice_models; i++) { - /* By pass inverters and buffers */ - if (SPICE_MODEL_INVBUF == spice_model[i].type) { - continue; - } - - /* Check if this spice model has input buffers */ - config_one_spice_model_buffer(num_spice_models, spice_model, - &(spice_model[i]), spice_model[i].input_buffer); - - /* Check if this spice model has output buffers */ - config_one_spice_model_buffer(num_spice_models, spice_model, - &(spice_model[i]), spice_model[i].output_buffer); - - /* If this spice_model is a LUT, check the lut_input_buffer */ - if (SPICE_MODEL_LUT == spice_model[i].type) { - assert(1 == spice_model[i].lut_input_buffer->exist); - assert(1 == spice_model[i].lut_input_inverter->exist); - - config_one_spice_model_buffer(num_spice_models, spice_model, - &(spice_model[i]), spice_model[i].lut_input_buffer); - - config_one_spice_model_buffer(num_spice_models, spice_model, - &(spice_model[i]), spice_model[i].lut_input_inverter); - - config_one_spice_model_buffer(num_spice_models, spice_model, - &(spice_model[i]), spice_model[i].lut_intermediate_buffer); - } - - - /* Check pass_gate logic only for LUT and MUX */ - if ((SPICE_MODEL_LUT == spice_model[i].type) - ||(SPICE_MODEL_MUX == spice_model[i].type)) { - pgl_spice_model = find_name_matched_spice_model(spice_model[i].pass_gate_logic->spice_model_name, - num_spice_models, spice_model); - /* We should find a buffer spice_model*/ - if (NULL == pgl_spice_model) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Fail to find pass_gate spice_model to the pass_gate_logic of spice_model(name=%s)!\n", - __FILE__, __LINE__, spice_model[i].name); - exit(1); - } - /* Copy the information from found spice model to current spice model*/ - /* copy gate info if this is a standard cell */ - if (SPICE_MODEL_GATE == pgl_spice_model->type) { - assert ( SPICE_MODEL_GATE_MUX2 == pgl_spice_model->design_tech_info.gate_info->type); - spice_model[i].design_tech_info.gate_info = (t_spice_model_gate*)my_calloc(1, sizeof(t_spice_model_gate)); - memcpy(spice_model[i].design_tech_info.gate_info, pgl_spice_model->design_tech_info.gate_info, sizeof(t_spice_model_gate)); - } else { - assert (SPICE_MODEL_PASSGATE == pgl_spice_model->type); - memcpy(spice_model[i].pass_gate_logic, pgl_spice_model->design_tech_info.pass_gate_info, sizeof(t_spice_model_pass_gate_logic)); - } - /* Recover the spice_model_name */ - spice_model[i].pass_gate_logic->spice_model_name = my_strdup(pgl_spice_model->name); - spice_model[i].pass_gate_logic->spice_model = pgl_spice_model; - } - } - - return; -} - -/* Return the SPICE model ports wanted - * ATTENTION: we use the pointer of spice model here although we don't modify anything of spice_model - * but we have return input ports, whose pointer will be lost if the input is not the pointor of spice_model - * BECAUSE spice_model will be a local copy if it is not a pointer. And it will be set free when this function - * finishes. So the return pointers become invalid ! - */ -t_spice_model_port** find_spice_model_ports(const t_spice_model* spice_model, - enum e_spice_model_port_type port_type, - int* port_num, boolean ignore_global_port) { - int iport, cur; - t_spice_model_port** ret = NULL; - - /* Check codes*/ - assert(NULL != port_num); - assert(NULL != spice_model); - - /* Count the number of ports that match*/ - (*port_num) = 0; - for (iport = 0; iport < spice_model->num_port; iport++) { - /* ignore global port if user specified */ - if ((TRUE == ignore_global_port) - &&(TRUE == spice_model->ports[iport].is_global)) { - continue; - } - if (port_type == spice_model->ports[iport].type) { - (*port_num)++; - } - } - - /* Initial the return pointers*/ - ret = (t_spice_model_port**)my_malloc(sizeof(t_spice_model_port*)*(*port_num)); - memset(ret, 0 , sizeof(t_spice_model_port*)*(*port_num)); - - /* Fill the return pointers*/ - cur = 0; - for (iport = 0; iport < spice_model->num_port; iport++) { - /* ignore global port if user specified */ - if ((TRUE == ignore_global_port) - &&(TRUE == spice_model->ports[iport].is_global)) { - continue; - } - if (port_type == spice_model->ports[iport].type) { - ret[cur] = &(spice_model->ports[iport]); - cur++; - } - } - /* Check correctness*/ - assert(cur == (*port_num)); - - return ret; -} - -/* Find the configure done ports */ -t_spice_model_port** find_spice_model_config_done_ports(t_spice_model* spice_model, - enum e_spice_model_port_type port_type, - int* port_num, boolean ignore_global_port) { - int iport, cur; - t_spice_model_port** ret = NULL; - - /* Check codes*/ - assert(NULL != port_num); - assert(NULL != spice_model); - - /* Count the number of ports that match*/ - (*port_num) = 0; - for (iport = 0; iport < spice_model->num_port; iport++) { - /* ignore global port if user specified */ - if ((TRUE == ignore_global_port) - &&(TRUE == spice_model->ports[iport].is_global)) { - continue; - } - if ((port_type == spice_model->ports[iport].type) - &&(TRUE == spice_model->ports[iport].is_config_enable)) { - (*port_num)++; - } - } - - /* Initial the return pointers*/ - ret = (t_spice_model_port**)my_malloc(sizeof(t_spice_model_port*)*(*port_num)); - memset(ret, 0 , sizeof(t_spice_model_port*)*(*port_num)); - - /* Fill the return pointers*/ - cur = 0; - for (iport = 0; iport < spice_model->num_port; iport++) { - /* ignore global port if user specified */ - if ((TRUE == ignore_global_port) - &&(TRUE == spice_model->ports[iport].is_global)) { - continue; - } - if ((port_type == spice_model->ports[iport].type) - &&(TRUE == spice_model->ports[iport].is_config_enable)) { - ret[cur] = &(spice_model->ports[iport]); - cur++; - } - } - /* Check correctness*/ - assert(cur == (*port_num)); - - return ret; -} - -/* Find the transistor in the tech lib*/ -t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib, - e_spice_trans_type trans_type) { - /* If we did not find return NULL*/ - t_spice_transistor_type* ret = NULL; - int i; - - for (i = 0; i < tech_lib.num_transistor_type; i++) { - if (trans_type == tech_lib.transistor_types[i].type) { - ret = &(tech_lib.transistor_types[i]); - break; - } - } - - return ret; -} - -/* Convert an integer to an one-hot encoding integer array */ -char* my_ito1hot(int in_int, int bin_len) { - char* ret = (char*) my_calloc (bin_len + 1, sizeof(char)); - - /* Make sure we do not have any overflow! */ - if (! ( (-1 < in_int) && (in_int <= bin_len) ) ) - assert ( (-1 < in_int) && (in_int <= bin_len) ); - - /* Initialize */ - for (int i = 0; i < bin_len - 1; i++) { - ret[i] = '0'; - } - sprintf(ret + bin_len - 1, "%s", "0"); - - if (bin_len == in_int) { - return ret; /* all zero case */ - } - ret[in_int] = '1'; /* Keep a good sequence of bits */ - - return ret; -} - - -/* Converter an integer to a binary string */ -int* my_itobin_int(int in_int, int bin_len) { - int* ret = (int*) my_calloc (bin_len, sizeof(int)); - int i, temp; - - /* Make sure we do not have any overflow! */ - if (! ( (-1 < in_int) && (in_int < pow(2., bin_len)) ) ) - assert ( (-1 < in_int) && (in_int < pow(2., bin_len)) ); - - temp = in_int; - for (i = 0; i < bin_len; i++) { - if (1 == temp % 2) { - ret[i] = 1; /* Keep a good sequence of bits */ - } - temp = temp / 2; - } - - return ret; -} - -/* Converter an integer to a binary string */ -char* my_itobin(int in_int, int bin_len) { - char* ret = (char*) my_calloc (bin_len + 1, sizeof(char)); - int i, temp; - - /* Make sure we do not have any overflow! */ - assert ( (-1 < in_int) && (in_int < pow(2., bin_len)) ); - - /* Initialize */ - for (i = 0; i < bin_len - 1; i++) { - ret[i] = '0'; - } - sprintf(ret + bin_len - 1, "%s", "0"); - - temp = in_int; - for (i = 0; i < bin_len; i++) { - if (1 == temp % 2) { - ret[i] = '1'; - } - temp = temp / 2; - } - - return ret; -} - - -/* Convert a integer to a string*/ -char* my_itoa(int input) { - char* ret = NULL; - int sign = 0; - int len = 0; - int temp = input; - int cur; - char end_of_str; - - /* Identify input number is positive or negative*/ - if (input < 0) { - sign = 1; /* sign will be '-'*/ - len = 1; - temp = 0 - input; - } else if (0 == input) { - sign = 0; - len = 2; - /* Alloc*/ - ret = (char*)my_malloc(sizeof(char)*len); - /* Lets get the end_of_str, the char is dependent on OS*/ - sprintf(ret,"%s","0"); - return ret; - } - /* Identify the length of string*/ - while(temp > 0) { - len++; - temp = temp/10; - } - /* Total length of string should include '\0' at the end*/ - len = len + 1; - /* Alloc*/ - ret = (char*)my_malloc(sizeof(char)*len); - - /*Fill it*/ - temp = input; - /* Lets get the end_of_str, the char is dependent on OS*/ - sprintf(ret,"%s","-"); - end_of_str = ret[1]; - ret[len-1] = end_of_str; - cur = len - 2; - /* Print the number reversely*/ - while(temp > 0) { - ret[cur] = temp%10 + '0'; /* ASIC II base is '0'*/ - cur--; - temp = temp/10; - } - /* Print the sign*/ - if (1 == sign) { - assert(0 == cur); - ret[cur] = '-'; - temp = 0 - input; - } else { - assert(-1 == cur); - } - - return ret; -} - -/* Generate a filename (string) for a grid subckt SPICE netlist, - * with given x and y coordinates - */ -char* fpga_spice_create_one_subckt_filename(const char* file_name_prefix, - int subckt_x, int subckt_y, - char* file_name_postfix) { - char* fname = NULL; - - if ( -1 == subckt_y ) { - fname = (char*) my_malloc(sizeof(char) * (strlen(file_name_prefix) - + strlen(my_itoa(subckt_x)) + 1 - + strlen(file_name_postfix) + 1)); - - sprintf(fname, "%s%d_%s", - file_name_prefix, subckt_x, file_name_postfix); - - } else { - fname = (char*) my_malloc(sizeof(char) * (strlen(file_name_prefix) - + strlen(my_itoa(subckt_x)) + 1 + strlen(my_itoa(subckt_y)) - + strlen(file_name_postfix) + 1)); - - sprintf(fname, "%s%d_%d%s", - file_name_prefix, subckt_x, subckt_y, file_name_postfix); - } - - return fname; -} - - -char* chomp_spice_node_prefix(char* spice_node_prefix) { - int len = 0; - char* ret = NULL; - - if (NULL == spice_node_prefix) { - return NULL; - } - - len = strlen(spice_node_prefix); /* String length without the last "\0"*/ - ret = (char*)my_malloc(sizeof(char)*(len+2)); - - /* Don't do anything when input is NULL*/ - if (NULL == spice_node_prefix) { - my_free(ret); - return NULL; - } - - strcpy(ret,spice_node_prefix); - /* If the path end up with "_" we should remove it*/ - if ('_' == ret[len-1]) { - ret[len-1] = ret[len]; - } - - return ret; -} - -char* format_spice_node_prefix(char* spice_node_prefix) { - int len = strlen(spice_node_prefix); /* String length without the last "\0"*/ - char* ret = (char*)my_malloc(sizeof(char)*(len+2)); - - /* Don't do anything when input is NULL*/ - if (NULL == spice_node_prefix) { - my_free(ret); - return NULL; - } - - strcpy(ret,spice_node_prefix); - /* If the path does not end up with "_" we should complete it*/ - if (ret[len-1] != '_') { - strcat(ret, "_"); - } - return ret; -} - -/* Given the co-ordinators of grid, - * Find if there is a block mapped into this grid - */ -t_block* search_mapped_block(int x, int y, int z) { - t_block* ret = NULL; - int iblk = 0; - - /*Valid pointors*/ - assert(NULL != grid); - assert((0 < x)||(0 == x)); - assert((x < (nx + 1))||(x == (nx + 1))); - assert((0 < y)||(0 == y)); - assert((y < (ny + 1))||(y == (ny + 1))); - - /* Search all blocks*/ - for (iblk = 0; iblk < num_blocks; iblk++) { - if ((x == block[iblk].x)&&(y == block[iblk].y)&&(z == block[iblk].z)) { - /* Matched cordinators*/ - ret = &(block[iblk]); - /* Check */ - assert(block[iblk].type == grid[x][y].type); - assert(z < grid[x][y].type->capacity); - assert(0 < grid[x][y].usage); - } - } - - return ret; -} - - - - -/* Change the decimal number to binary - * and return a array of integer*/ -int* my_decimal2binary(int decimal, - int* binary_len) { - int* ret = NULL; - int i = 0; - int code = decimal; - - (*binary_len) = 0; - - while (0 < code) { - (*binary_len)++; - code = code/2; - } - - i = (*binary_len) - 1; - while (0 < code) { - ret[i] = code%2; - i--; - code = code/2; - } - - return ret; -} - -/** - * Split a string with strtok - * Store each token in a char array - * tokens (char**): - * tokens[i] (char*) : pointer to a string split by delims - */ - -char** fpga_spice_strtok(char* str, - char* delims, - int* len) { - char** ret; - char* result; - int cnt=0; - int* lens; - char* tmp; - - if (NULL == str) { - printf("Warning: NULL string found in my_strtok!\n"); - return NULL; - } - - tmp = my_strdup(str); - result = strtok(tmp,delims); - /*First scan to determine the size*/ - while(result != NULL) { - cnt++; - /* strtok split until its buffer is NULL*/ - result = strtok(NULL,delims); - } - //printf("1st scan cnt=%d\n",cnt); - /* Allocate memory*/ - ret = (char**)my_malloc(cnt*sizeof(char*)); - lens = (int*)my_malloc(cnt*sizeof(int)); - /*Second to determine the size of each char*/ - cnt = 0; - memcpy(tmp,str,strlen(str)+1); - result = strtok(tmp,delims); - while(result != NULL) { - lens[cnt] = strlen(result)+1; - //printf("lens[%d]=%d .",cnt,lens[cnt]); - cnt++; - /* strtok split until its buffer is NULL*/ - result = strtok(NULL,delims); - } - //printf("\n"); - /*Third to allocate and copy each char*/ - cnt = 0; - memcpy(tmp,str,strlen(str)+1); - result = strtok(tmp,delims); - while(result != NULL) { - //printf("results[%d] = %s ",cnt,result); - ret[cnt] = my_strdup(result); - cnt++; - /* strtok split until its buffer is NULL*/ - result = strtok(NULL,delims); - } - //printf("\n"); - - (*len) = cnt; - - free(tmp); - - return ret; -} - -int get_opposite_side(int side){ - - switch (side) { - case 0: - return 2; - case 1: - return 3; - case 2: - return 0; - case 3: - return 1; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid side index. Should be [0,3].\n", - __FILE__, __LINE__); - exit(1); - } -} - -char* convert_side_index_to_string(int side) { - switch (side) { - case 0: - return "top"; - case 1: - return "right"; - case 2: - return "bottom"; - case 3: - return "left"; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid side index. Should be [0,3].\n", - __FILE__, __LINE__); - exit(1); - } -} - -char* convert_process_corner_to_string(enum e_process_corner process_corner) { - switch(process_corner) { - case BEST_CORNER: - return "bc"; - case TYPICAL_CORNER: - return "tc"; - case WORST_CORNER: - return "wc"; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid process_corner !\n", - __FILE__, __LINE__); - exit(1); - } -} - -void init_spice_net_info(t_spice_net_info* spice_net_info) { - if (NULL == spice_net_info) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid spice_net_info!\n", __FILE__, __LINE__); - exit(1); - } - - spice_net_info->density = 0.; - spice_net_info->freq = 0.; - - assert((1 == default_signal_init_value)||(0 == default_signal_init_value)); - spice_net_info->init_val = default_signal_init_value; - spice_net_info->probability = (float)default_signal_init_value; - - spice_net_info->pwl = 0.; - spice_net_info->pwh = 0.; - spice_net_info->slew_rise = 0.; - - return; -} - -t_spice_model* find_iopad_spice_model(int num_spice_model, - t_spice_model* spice_models) { - t_spice_model* ret = NULL; - int imodel; - int num_found = 0; - - for (imodel = 0; imodel < num_spice_model; imodel++) { - if (SPICE_MODEL_IOPAD == spice_models[imodel].type) { - ret = &(spice_models[imodel]); - num_found++; - } - } - - assert(1 == num_found); - - return ret; -} - -/* Check if the grid coorindate given is in the range */ -boolean is_grid_coordinate_in_range(int x_min, - int x_max, - int grid_x) { - /* See if x is in the range */ - if ((x_min > grid_x) - ||(x_max < grid_x)) { - return FALSE; - } - - /* Reach here, means all in the range */ - return TRUE; -} - -char* generate_string_spice_model_type(enum e_spice_model_type spice_model_type) { - char* ret = NULL; - - switch (spice_model_type) { - case SPICE_MODEL_WIRE: - ret = "wire"; - break; - case SPICE_MODEL_MUX: - ret = "Multiplexer"; - break; - case SPICE_MODEL_LUT: - ret = "Look-Up Table"; - break; - case SPICE_MODEL_FF: - ret = "Flip-flop"; - break; - case SPICE_MODEL_SRAM: - ret = "SRAM"; - break; - case SPICE_MODEL_HARDLOGIC: - ret = "hard_logic"; - break; - case SPICE_MODEL_IOPAD: - ret = "iopad"; - break; - case SPICE_MODEL_CCFF: - ret = "Scan-chain Flip-flop"; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid spice_model_type!\n", __FILE__, __LINE__); - exit(1); - } - - return ret; -} - -/* Deteremine the side of a io grid */ -int determine_io_grid_side(int x, - int y) { - /* TOP side IO of FPGA */ - if ((ny + 1) == y) { - /* Make sure a valid x, y */ - assert((!(0 > x))&&(x < (nx + 1))); - return BOTTOM; /* Such I/O has only Bottom side pins */ - } else if ((nx + 1) == x) { /* RIGHT side IO of FPGA */ - /* Make sure a valid x, y */ - assert((!(0 > y))&&(y < (ny + 1))); - return LEFT; /* Such I/O has only Left side pins */ - } else if (0 == y) { /* BOTTOM side IO of FPGA */ - /* Make sure a valid x, y */ - assert((!(0 > x))&&(x < (nx + 1))); - return TOP; /* Such I/O has only Top side pins */ - } else if (0 == x) { /* LEFT side IO of FPGA */ - /* Make sure a valid x, y */ - assert((!(0 > y))&&(y < (ny + 1))); - return RIGHT; /* Such I/O has only Right side pins */ - } else { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])I/O Grid is in the center part of FPGA! Currently unsupported!\n", - __FILE__, __LINE__); - exit(1); - } -} - -void find_prev_rr_nodes_with_src(t_rr_node* src_rr_node, - int* num_drive_rr_nodes, - t_rr_node*** drive_rr_nodes, - int** switch_indices) { - int inode, iedge, next_node; - int cur_index, switch_index; - - assert(NULL != src_rr_node); - assert(NULL != num_drive_rr_nodes); - assert(NULL != switch_indices); - - (*num_drive_rr_nodes) = 0; - (*drive_rr_nodes) = NULL; - (*switch_indices) = NULL; - - switch_index = -1; - /* Determine num_drive_rr_node */ - for (inode = 0; inode < num_rr_nodes; inode++) { - for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { - next_node = rr_node[inode].edges[iedge]; - if (src_rr_node == &(rr_node[next_node])) { - /* Get the spice_model */ - if (-1 == switch_index) { - switch_index = rr_node[inode].switches[iedge]; - } else { /* Make sure the switches are the same*/ - assert(switch_index == rr_node[inode].switches[iedge]); - } - (*num_drive_rr_nodes)++; - } - } - } - /* Malloc */ - (*drive_rr_nodes) = (t_rr_node**)my_malloc(sizeof(t_rr_node*)*(*num_drive_rr_nodes)); - (*switch_indices) = (int*)my_malloc(sizeof(int)*(*num_drive_rr_nodes)); - - /* Find all the rr_nodes that drive current_rr_node*/ - cur_index = 0; - for (inode = 0; inode < num_rr_nodes; inode++) { - for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { - next_node = rr_node[inode].edges[iedge]; - if (src_rr_node == &(rr_node[next_node])) { - /* Update drive_rr_nodes list */ - (*drive_rr_nodes)[cur_index] = &(rr_node[inode]); - (*switch_indices)[cur_index] = rr_node[inode].switches[iedge]; - cur_index++; - } - } - } - assert(cur_index == (*num_drive_rr_nodes)); - - return; -} - - -int find_path_id_prev_rr_node(int num_drive_rr_nodes, - t_rr_node** drive_rr_nodes, - t_rr_node* src_rr_node) { - int path_id, inode; - - /* Configuration bits for this MUX*/ - path_id = -1; - for (inode = 0; inode < num_drive_rr_nodes; inode++) { - if (drive_rr_nodes[inode] == &(rr_node[src_rr_node->prev_node])) { - path_id = inode; - break; - } - } - assert((-1 != path_id)&&(path_id < src_rr_node->fan_in)); - - return path_id; -} - -int pb_pin_net_num(t_rr_node* pb_rr_graph, - t_pb_graph_pin* pin) { - int net_num = OPEN; - - if (NULL == pb_rr_graph) { - /* Try the temp_net_num in pb_graph_pin */ - net_num = pin->temp_net_num; - } else { - net_num = pb_rr_graph[pin->rr_node_index_physical_pb].net_num; - } - - return net_num; -} - -float pb_pin_density(t_rr_node* pb_rr_graph, - t_pb_graph_pin* pin) { - float density = 0.; - int net_num; - - if (NULL == pb_rr_graph) { - /* Try the temp_net_num in pb_graph_pin */ - net_num = pin->temp_net_num; - if (OPEN != net_num) { - density = vpack_net[net_num].spice_net_info->density; - } - return density; - } - net_num = pb_rr_graph[pin->rr_node_index_physical_pb].net_num; - - if (OPEN != net_num) { - density = vpack_net[net_num].spice_net_info->density; - } - - return density; -} - -float pb_pin_probability(t_rr_node* pb_rr_graph, - t_pb_graph_pin* pin) { - float probability = (float)(default_signal_init_value); - int net_num; - - if (NULL == pb_rr_graph) { - /* Try the temp_net_num in pb_graph_pin */ - net_num = pin->temp_net_num; - if (OPEN != net_num) { - probability = vpack_net[net_num].spice_net_info->probability; - } - return probability; - } - net_num = pb_rr_graph[pin->rr_node_index_physical_pb].net_num; - - if (OPEN != net_num) { - probability = vpack_net[net_num].spice_net_info->probability; - } - - return probability; -} - -int pb_pin_init_value(t_rr_node* pb_rr_graph, - t_pb_graph_pin* pin) { - float init_val = (float)(default_signal_init_value); - int net_num; - - if (NULL == pb_rr_graph) { - /* TODO: we know initialize to vdd could reduce the leakage power od multiplexers! - * But I can this as an option ! - */ - /* Try the temp_net_num in pb_graph_pin */ - net_num = pin->temp_net_num; - if (OPEN != net_num) { - init_val = vpack_net[net_num].spice_net_info->init_val; - } - return init_val; - } - net_num = pb_rr_graph[pin->rr_node_index_physical_pb].net_num; - - if (OPEN != net_num) { - init_val = vpack_net[net_num].spice_net_info->init_val; - } - - return init_val; -} - -float get_rr_node_net_density(t_rr_node node) { - /* If we found this net is OPEN, we assume it zero-density */ - if (OPEN == node.vpack_net_num) { - return 0.; - } else { - return vpack_net[node.vpack_net_num].spice_net_info->density; - } -} - -float get_rr_node_net_probability(t_rr_node node) { - /* If we found this net is OPEN, we assume it zero-probability */ - if (OPEN == node.vpack_net_num) { - /* TODO: we know initialize to vdd could reduce the leakage power od multiplexers! - * But I can this as an option ! - */ - return (float)(default_signal_init_value); - } else { - return vpack_net[node.vpack_net_num].spice_net_info->probability; - } -} - -int get_rr_node_net_init_value(t_rr_node node) { - /* If we found this net is OPEN, we assume it zero-probability */ - if (OPEN == node.vpack_net_num) { - /* TODO: we know initialize to vdd could reduce the leakage power od multiplexers! - * But I can this as an option ! - */ - return (float)(default_signal_init_value); - } else { - return vpack_net[node.vpack_net_num].spice_net_info->init_val; - } -} - -int recommend_num_sim_clock_cycle(float sim_window_size) { - float avg_density = 0.; - float median_density = 0.; - int recmd_num_sim_clock_cycle = 0; - int inet, jnet; - int net_cnt = 0; - float* density_value = NULL; - int* sort_index = NULL; - int* net_to_sort_index_mapping = NULL; - - float weighted_avg_density = 0.; - float net_weight = 0.; - int weighted_net_cnt = 0; - - /* get the average density of all the nets */ - for (inet = 0; inet < num_logical_nets; inet++) { - assert(NULL != vpack_net[inet].spice_net_info); - if ((FALSE == vpack_net[inet].is_global) - &&(FALSE == vpack_net[inet].is_const_gen) - &&(0. != vpack_net[inet].spice_net_info->density)) { - avg_density += vpack_net[inet].spice_net_info->density; - net_cnt++; - /* Consider the weight of fan-out */ - if (0 == vpack_net[inet].num_sinks) { - net_weight = 1; - } else { - assert( 0 < vpack_net[inet].num_sinks ); - net_weight = vpack_net[inet].num_sinks; - } - weighted_avg_density += vpack_net[inet].spice_net_info->density * net_weight; - weighted_net_cnt += net_weight; - } - } - avg_density = avg_density/net_cnt; - weighted_avg_density = weighted_avg_density/weighted_net_cnt; - - /* Fill the array to be sorted */ - density_value = (float*)my_malloc(sizeof(float)*net_cnt); - sort_index = (int*)my_malloc(sizeof(int)*net_cnt); - net_to_sort_index_mapping = (int*)my_malloc(sizeof(int)*net_cnt); - jnet = 0; - for (inet = 0; inet < num_logical_nets; inet++) { - assert(NULL != vpack_net[inet].spice_net_info); - if ((FALSE == vpack_net[inet].is_global) - &&(FALSE == vpack_net[inet].is_const_gen) - &&(0. != vpack_net[inet].spice_net_info->density)) { - sort_index[jnet] = jnet; - net_to_sort_index_mapping[jnet] = inet; - density_value[jnet] = vpack_net[inet].spice_net_info->density; - jnet++; - } - } - assert(jnet == net_cnt); - /* Sort the density */ - quicksort_float_index(net_cnt, sort_index, density_value); - /* Get the median */ - median_density = vpack_net[sort_index[(int)(0.5*net_cnt)]].spice_net_info->density; - - /* It may be more reasonable to use median - * But, if median density is 0, we use average density - */ - if ((0. == median_density) && (0. == avg_density)) { - recmd_num_sim_clock_cycle = 1; - vpr_printf(TIO_MESSAGE_WARNING, - "All the signal density is zero! No. of clock cycles in simulations are set to be %d!", - recmd_num_sim_clock_cycle); - } else if (0. == avg_density) { - recmd_num_sim_clock_cycle = (int)round(1/median_density); - } else if (0. == median_density) { - recmd_num_sim_clock_cycle = (int)round(1/avg_density); - } else { - /* add a sim window size to balance the weight of average density and median density - * In practice, we find that there could be huge difference between avereage and median values - * For a reasonable number of simulation clock cycles, we do this window size. - */ - recmd_num_sim_clock_cycle = (int)round(1 / (sim_window_size * avg_density + (1 - sim_window_size) * median_density )); - } - - assert( 0 < recmd_num_sim_clock_cycle); - - vpr_printf(TIO_MESSAGE_INFO, "Average net density: %.2f\n", avg_density); - vpr_printf(TIO_MESSAGE_INFO, "Median net density: %.2f\n", median_density); - vpr_printf(TIO_MESSAGE_INFO, "Average net densityi after weighting: %.2f\n", weighted_avg_density); - vpr_printf(TIO_MESSAGE_INFO, "Window size set for Simulation: %.2f\n", sim_window_size); - vpr_printf(TIO_MESSAGE_INFO, "Net density after Window size : %.2f\n", - (sim_window_size * avg_density + (1 - sim_window_size) * median_density)); - vpr_printf(TIO_MESSAGE_INFO, "Recommend no. of clock cycles: %d\n", recmd_num_sim_clock_cycle); - - /* Free */ - my_free(sort_index); - my_free(density_value); - my_free(net_to_sort_index_mapping); - - return recmd_num_sim_clock_cycle; -} - -void auto_select_num_sim_clock_cycle(t_spice* spice, - float sim_window_size) { - int recmd_num_sim_clock_cycle = recommend_num_sim_clock_cycle(sim_window_size); - - /* Auto select number of simulation clock cycles*/ - if (-1 == spice->spice_params.meas_params.sim_num_clock_cycle) { - vpr_printf(TIO_MESSAGE_INFO, "Auto select the no. of clock cycles in simulation: %d\n", recmd_num_sim_clock_cycle); - spice->spice_params.meas_params.sim_num_clock_cycle = recmd_num_sim_clock_cycle; - } else { - vpr_printf(TIO_MESSAGE_INFO, "No. of clock cycles in simulation is forced to be: %d\n", - spice->spice_params.meas_params.sim_num_clock_cycle); - } - - return; -} - -/* Malloc grid_index_low and grid_index_high for a spice_model */ -void alloc_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) { - int ix, iy; - - /* grid_index_low */ - /* x - direction*/ - cur_spice_model->grid_index_low = (int**)my_malloc(sizeof(int*)*(nx + 2)); - /* y - direction*/ - for (ix = 0; ix < (nx + 2); ix++) { - cur_spice_model->grid_index_low[ix] = (int*)my_malloc(sizeof(int)*(ny + 2)); - } - /* Initialize */ - for (ix = 0; ix < (nx + 2); ix++) { - for (iy = 0; iy < (ny + 2); iy++) { - cur_spice_model->grid_index_low[ix][iy] = 0; - } - } - /* grid_index_high */ - /* x - direction*/ - cur_spice_model->grid_index_high = (int**)my_malloc(sizeof(int*)*(nx + 2)); - /* y - direction*/ - for (ix = 0; ix < (nx + 2); ix++) { - cur_spice_model->grid_index_high[ix] = (int*)my_malloc(sizeof(int)*(ny + 2)); - } - /* Initialize */ - for (ix = 0; ix < (nx + 2); ix++) { - for (iy = 0; iy < (ny + 2); iy++) { - cur_spice_model->grid_index_high[ix][iy] = 0; - } - } - - return; -} - -void free_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) { - int ix; - - for (ix = 0; ix < (nx + 2); ix++) { - my_free(cur_spice_model->grid_index_high[ix]); - my_free(cur_spice_model->grid_index_low[ix]); - } - - my_free(cur_spice_model->grid_index_high); - my_free(cur_spice_model->grid_index_low); - - return; -} - -void free_spice_model_grid_index_low_high(int num_spice_models, - t_spice_model* spice_model) { - int i; - - for (i = 0; i < num_spice_models; i++) { - free_one_spice_model_grid_index_low_high(&(spice_model[i])); - } - return; -} - - -void update_one_spice_model_grid_index_low(int x, int y, - t_spice_model* cur_spice_model) { - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - assert(NULL != cur_spice_model); - assert(NULL != cur_spice_model->grid_index_low); - assert(NULL != cur_spice_model->grid_index_low[x]); - - /* Assigne the low */ - cur_spice_model->grid_index_low[x][y] = cur_spice_model->cnt; - - return; -} - -void update_spice_models_grid_index_low(int x, int y, - int num_spice_models, - t_spice_model* spice_model) { - int i; - - for (i = 0; i < num_spice_models; i++) { - update_one_spice_model_grid_index_low(x, y, &(spice_model[i])); - } - - return; -} - -void update_one_spice_model_grid_index_high(int x, int y, - t_spice_model* cur_spice_model) { - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - assert(NULL != cur_spice_model); - assert(NULL != cur_spice_model->grid_index_high); - assert(NULL != cur_spice_model->grid_index_high[x]); - - /* Assigne the low */ - cur_spice_model->grid_index_high[x][y] = cur_spice_model->cnt; - - return; -} - -void update_spice_models_grid_index_high(int x, int y, - int num_spice_models, - t_spice_model* spice_model) { - int i; - - for (i = 0; i < num_spice_models; i++) { - update_one_spice_model_grid_index_high(x, y, &(spice_model[i])); - } - - return; -} - -void zero_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model) { - int ix, iy; - /* Initialize */ - for (ix = 0; ix < (nx + 2); ix++) { - for (iy = 0; iy < (ny + 2); iy++) { - cur_spice_model->grid_index_high[ix][iy] = 0; - cur_spice_model->grid_index_low[ix][iy] = 0; - } - } - return; -} - -void zero_spice_model_grid_index_low_high(int num_spice_models, - t_spice_model* spice_model) { - int i; - - for (i = 0; i < num_spice_models; i++) { - zero_one_spice_model_grid_index_low_high(&(spice_model[i])); - } - - return; -} - -char* gen_str_spice_model_structure(enum e_spice_model_structure spice_model_structure) { - switch (spice_model_structure) { - case SPICE_MODEL_STRUCTURE_TREE: - return "tree-like"; - case SPICE_MODEL_STRUCTURE_ONELEVEL: - return "one-level"; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - return "multi-level"; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid spice model structure!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/* Check if the spice model structure is the same with the switch_inf structure */ -boolean check_spice_model_structure_match_switch_inf(t_switch_inf target_switch_inf) { - assert(NULL != target_switch_inf.spice_model); - if (target_switch_inf.structure != target_switch_inf.spice_model->design_tech_info.mux_info->structure) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure in spice_model(%s) is different from switch_inf[%s]!\n", - __FILE__, __LINE__, target_switch_inf.spice_model->name, target_switch_inf.name); - return FALSE; - } - return TRUE; -} - - -void init_rr_nodes_vpack_net_num_changed(int LL_num_rr_nodes, - t_rr_node* LL_rr_node) { - int inode; - - for (inode = 0; inode < LL_num_rr_nodes; inode++) { - LL_rr_node[inode].vpack_net_num_changed = FALSE; - } - - return; -} - -void init_rr_nodes_is_parasitic_net(int LL_num_rr_nodes, - t_rr_node* LL_rr_node) { - int inode; - - for (inode = 0; inode < LL_num_rr_nodes; inode++) { - LL_rr_node[inode].is_parasitic_net = FALSE; - } - - return; -} - - -/* Check if this net is connected to a PI*/ -boolean is_net_pi(t_net* cur_net) { - int src_blk_idx; - - assert(NULL != cur_net); - - src_blk_idx = cur_net->node_block[0]; - if (VPACK_INPAD == logical_block[src_blk_idx].type) { - return TRUE; - } - return FALSE; -} - -int check_consistency_logical_block_net_num(t_logical_block* lgk_blk, - int num_inputs, int* input_net_num) { - int i, iport, ipin, net_eq; - int consistency = 1; - int* input_net_num_mapped = (int*)my_calloc(num_inputs, sizeof(int)); - - for (iport = 0; iport < lgk_blk->pb->pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < lgk_blk->pb->pb_graph_node->num_input_pins[iport]; ipin++) { - if (OPEN == lgk_blk->input_nets[iport][ipin]) { - continue; /* bypass unused pins */ - } - /* Initial net_eq */ - net_eq = 0; - /* Check if this net can be found in the input net_num */ - for (i = 0; i < num_inputs; i++) { - if (1 == input_net_num_mapped[i]) { - continue; - } - if (input_net_num[i] == lgk_blk->input_nets[iport][ipin]) { - net_eq = 1; - input_net_num_mapped[i] = 1; - break; - } - } - if (0 == net_eq) { - consistency = 0; - break; - } - } - if (0 == consistency) { - break; - } - } - - /* Free */ - my_free(input_net_num_mapped); - - return consistency; -} - -/* Determine if this rr_node is driving this switch box (x,y) - * For more than length-1 wire, the fan-in of a des_rr_node in a switch box - * contain all the drivers in the switch boxes that it passes through. - * This function is to identify if the src_rr_node is the driver in this switch box - */ -int rr_node_drive_switch_box(t_rr_node* src_rr_node, - t_rr_node* des_rr_node, - int switch_box_x, - int switch_box_y, - int chan_side) { - - /* Make sure a valid src_rr_node and des_rr_node */ - assert(NULL != src_rr_node); - assert(NULL != des_rr_node); - /* The src_rr_node should be either CHANX or CHANY */ - assert((CHANX == des_rr_node->type)||(CHANY == des_rr_node->type)); - /* Valid switch_box coordinator */ - assert((!(0 > switch_box_x))&&(!(switch_box_x > (nx + 1)))); - assert((!(0 > switch_box_y))&&(!(switch_box_y > (ny + 1)))); - /* Valid des_rr_node coordinator */ - assert((!(switch_box_x < (des_rr_node->xlow - 1)))&&(!(switch_box_x > (des_rr_node->xhigh + 1)))); - assert((!(switch_box_y < (des_rr_node->ylow - 1)))&&(!(switch_box_y > (des_rr_node->yhigh + 1)))); - - /* Check the src_rr_node coordinator */ - switch (chan_side) { - case TOP: - /* Following cases: - * | - * / | \ - */ - /* The destination rr_node only have one condition!!! */ - assert((INC_DIRECTION == des_rr_node->direction)&&(CHANY == des_rr_node->type)); - /* depend on the type of src_rr_node */ - switch (src_rr_node->type) { - case OPIN: - if (((switch_box_y + 1) == src_rr_node->ylow) - &&((switch_box_x == src_rr_node->xlow)||((switch_box_x + 1) == src_rr_node->xlow))) { - return 1; - } - break; - case CHANX: - assert(src_rr_node->ylow == src_rr_node->yhigh); - if ((switch_box_y == src_rr_node->ylow) - &&(!(switch_box_x < (src_rr_node->xlow - 1))) - &&(!(switch_box_x > (src_rr_node->xhigh + 1)))) { - return 1; - } - break; - case CHANY: - assert(src_rr_node->xlow == src_rr_node->xhigh); - if ((switch_box_x == src_rr_node->xlow) - &&(!(switch_box_y < src_rr_node->ylow)) - &&(!(switch_box_y > src_rr_node->yhigh))) { - return 1; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid src_rr_node type!\n", - __FILE__, __LINE__); - exit(1); - } - break; - case RIGHT: - /* Following cases: - * \ - * --- ---- - * / - */ - /* The destination rr_node only have one condition!!! */ - assert((INC_DIRECTION == des_rr_node->direction)&&(CHANX == des_rr_node->type)); - /* depend on the type of src_rr_node */ - switch (src_rr_node->type) { - case OPIN: - if (((switch_box_x + 1) == src_rr_node->xlow) - &&((switch_box_y == src_rr_node->ylow)||((switch_box_y + 1) == src_rr_node->ylow))) { - return 1; - } - break; - case CHANX: - assert(src_rr_node->ylow == src_rr_node->yhigh); - if ((switch_box_y == src_rr_node->ylow) - &&(!(switch_box_x < src_rr_node->xlow))&&(!(switch_box_x > src_rr_node->xhigh))) { - return 1; - } - break; - case CHANY: - assert(src_rr_node->xlow == src_rr_node->xhigh); - if ((switch_box_x == src_rr_node->xlow) - &&(!(switch_box_y < (src_rr_node->ylow - 1))) - &&(!(switch_box_y > (src_rr_node->yhigh + 1)))) { - return 1; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid src_rr_node type!\n", - __FILE__, __LINE__); - exit(1); - } - break; - case BOTTOM: - /* Following cases: - * | - * \ | / - * | - */ - /* The destination rr_node only have one condition!!! */ - assert((DEC_DIRECTION == des_rr_node->direction)&&(CHANY == des_rr_node->type)); - /* depend on the type of src_rr_node */ - switch (src_rr_node->type) { - case OPIN: - if ((switch_box_y == src_rr_node->ylow) - &&((switch_box_x == src_rr_node->xlow)||((switch_box_x + 1) == src_rr_node->xlow))) { - return 1; - } - break; - case CHANX: - assert(src_rr_node->ylow == src_rr_node->yhigh); - if ((switch_box_y == src_rr_node->ylow) - &&(!(switch_box_x < (src_rr_node->xlow - 1))) - &&(!(switch_box_x > (src_rr_node->xhigh + 1)))) { - return 1; - } - break; - case CHANY: - assert(src_rr_node->xlow == src_rr_node->xhigh); - if ((switch_box_x == src_rr_node->xlow) - &&(!((switch_box_y + 1) < src_rr_node->ylow)) - &&(!((switch_box_y + 1) > src_rr_node->yhigh))) { - return 1; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid src_rr_node type!\n", - __FILE__, __LINE__); - exit(1); - } - break; - case LEFT: - /* Following cases: - * / - * --- ---- - * \ - */ - /* The destination rr_node only have one condition!!! */ - if (!((DEC_DIRECTION == des_rr_node->direction)&&(CHANX == des_rr_node->type))) - assert((DEC_DIRECTION == des_rr_node->direction)&&(CHANX == des_rr_node->type)); - /* depend on the type of src_rr_node */ - switch (src_rr_node->type) { - case OPIN: - if ((switch_box_x == src_rr_node->xlow) - &&((switch_box_y == src_rr_node->ylow)||((switch_box_y + 1) == src_rr_node->ylow))) { - return 1; - } - break; - case CHANX: - assert(src_rr_node->ylow == src_rr_node->yhigh); - if ((switch_box_y == src_rr_node->ylow) - &&(!((switch_box_x + 1) < src_rr_node->xlow)) - &&(!((switch_box_x + 1) > src_rr_node->xhigh))) { - return 1; - } - break; - case CHANY: - assert(src_rr_node->xlow == src_rr_node->xhigh); - if ((switch_box_x == src_rr_node->xlow) - &&(!(switch_box_y < (src_rr_node->ylow - 1))) - &&(!(switch_box_y > (src_rr_node->yhigh + 1)))) { - return 1; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid src_rr_node type!\n", - __FILE__, __LINE__); - exit(1); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s, [LINE%d])Invalid side!\n", __FILE__, __LINE__); - exit(1); - } - - return 0; -} - -void find_drive_rr_nodes_switch_box(int switch_box_x, - int switch_box_y, - t_rr_node* src_rr_node, - int chan_side, - int return_num_only, - int* num_drive_rr_nodes, - t_rr_node*** drive_rr_nodes, - int* switch_index) { - int cur_index = 0; - //int inode, iedge, next_node; - int inode; - - /* I decide to kill the codes that search all the edges, the running time is huge... */ - /* Determine the num_drive_rr_nodes */ - (*num_drive_rr_nodes) = 0; - (*switch_index) = -1; - - for (inode = 0; inode < src_rr_node->num_drive_rr_nodes; inode++) { - if (1 == rr_node_drive_switch_box(src_rr_node->drive_rr_nodes[inode], src_rr_node, - switch_box_x, switch_box_y, chan_side)) { - /* Get the spice_model */ - if (-1 == (*switch_index)) { - (*switch_index) = src_rr_node->drive_switches[inode]; - } else { /* Make sure the switches are the same*/ - assert((*switch_index) == src_rr_node->drive_switches[inode]); - } - (*num_drive_rr_nodes)++; - } - } - - //for (inode = 0; inode < num_rr_nodes; inode++) { - // for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { - // next_node = rr_node[inode].edges[iedge]; - // /* Make sure the coordinator is matched to this switch box*/ - // if ((src_rr_node == &(rr_node[next_node])) - // &&(1 == rr_node_drive_switch_box(&(rr_node[inode]), src_rr_node, switch_box_x, switch_box_y, chan_side))) { - // /* Get the spice_model */ - // if (-1 == (*switch_index)) { - // (*switch_index) = rr_node[inode].switches[iedge]; - // } else { /* Make sure the switches are the same*/ - // assert((*switch_index) == rr_node[inode].switches[iedge]); - // } - // (*num_drive_rr_nodes)++; - // } - // } - //} - - /* Check and malloc*/ - assert((!(0 > (*num_drive_rr_nodes)))&&(!((*num_drive_rr_nodes) > src_rr_node->fan_in))); - if (1 == return_num_only) { - return; - } - (*drive_rr_nodes) = NULL; - if (0 == (*num_drive_rr_nodes)) { - return; - } - (*drive_rr_nodes) = (t_rr_node**)my_malloc(sizeof(t_rr_node*)*(*num_drive_rr_nodes)); - - /* Find all the rr_nodes that drive current_rr_node*/ - cur_index = 0; - (*switch_index) = -1; - - for (inode = 0; inode < src_rr_node->num_drive_rr_nodes; inode++) { - if (1 == rr_node_drive_switch_box(src_rr_node->drive_rr_nodes[inode], src_rr_node, - switch_box_x, switch_box_y, chan_side)) { - /* Update drive_rr_nodes list */ - (*drive_rr_nodes)[cur_index] = src_rr_node->drive_rr_nodes[inode]; - /* Get the spice_model */ - if (-1 == (*switch_index)) { - (*switch_index) = src_rr_node->drive_switches[inode]; - } else { /* Make sure the switches are the same*/ - assert((*switch_index) == src_rr_node->drive_switches[inode]); - } - cur_index++; - } - } - //for (inode = 0; inode < num_rr_nodes; inode++) { - // for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { - // next_node = rr_node[inode].edges[iedge]; - // /* Make sure the coordinator is matched to this switch box*/ - // if ((src_rr_node == &(rr_node[next_node])) - // &&(1 == rr_node_drive_switch_box(&(rr_node[inode]), src_rr_node, switch_box_x, switch_box_y, chan_side))) { - // /* Update drive_rr_nodes list */ - // (*drive_rr_nodes)[cur_index] = &(rr_node[inode]); - // /* Get the spice_model */ - // if (-1 == (*switch_index)) { - // (*switch_index) = rr_node[inode].switches[iedge]; - // } else { /* Make sure the switches are the same*/ - // assert((*switch_index) == rr_node[inode].switches[iedge]); - // } - // cur_index++; - // } - // } - //} - /* Verification */ - assert(cur_index == (*num_drive_rr_nodes)); - - return; -} - -/* Reset the counter of each spice_model to be zero */ -void zero_spice_models_cnt(int num_spice_models, t_spice_model* spice_model) { - int imodel = 0; - - for (imodel = 0; imodel < num_spice_models; imodel++) { - spice_model[imodel].cnt = 0; - } - - return; -} - -void zero_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model) { - int ix, iy; - /* Initialize */ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 0; iy < (ny + 1); iy++) { - cur_spice_model->sb_index_low[ix][iy] = 0; - cur_spice_model->cbx_index_low[ix][iy] = 0; - cur_spice_model->cby_index_low[ix][iy] = 0; - cur_spice_model->sb_index_high[ix][iy] = 0; - cur_spice_model->cbx_index_high[ix][iy] = 0; - cur_spice_model->cby_index_high[ix][iy] = 0; - } - } - return; -} - -void zero_spice_models_routing_index_low_high(int num_spice_models, - t_spice_model* spice_model) { - int i; - - for (i = 0; i < num_spice_models; i++) { - zero_one_spice_model_routing_index_low_high(&(spice_model[i])); - } - - return; -} - -/* Malloc routing_index_low and routing_index_high for a spice_model */ -void alloc_spice_model_routing_index_low_high(t_spice_model* cur_spice_model) { - int ix; - - /* [cbx|cby|sb]_index_low */ - /* x - direction*/ - cur_spice_model->sb_index_low = (int**)my_malloc(sizeof(int*)*(nx + 1)); - cur_spice_model->cbx_index_low = (int**)my_malloc(sizeof(int*)*(nx + 1)); - cur_spice_model->cby_index_low = (int**)my_malloc(sizeof(int*)*(nx + 1)); - /* y - direction*/ - for (ix = 0; ix < (nx + 1); ix++) { - cur_spice_model->sb_index_low[ix] = (int*)my_malloc(sizeof(int)*(ny + 1)); - cur_spice_model->cbx_index_low[ix] = (int*)my_malloc(sizeof(int)*(ny + 1)); - cur_spice_model->cby_index_low[ix] = (int*)my_malloc(sizeof(int)*(ny + 1)); - } - - /* grid_index_high */ - /* x - direction*/ - cur_spice_model->sb_index_high = (int**)my_malloc(sizeof(int*)*(nx + 1)); - cur_spice_model->cbx_index_high = (int**)my_malloc(sizeof(int*)*(nx + 1)); - cur_spice_model->cby_index_high = (int**)my_malloc(sizeof(int*)*(nx + 1)); - /* y - direction*/ - for (ix = 0; ix < (nx + 1); ix++) { - cur_spice_model->sb_index_high[ix] = (int*)my_malloc(sizeof(int)*(ny + 1)); - cur_spice_model->cbx_index_high[ix] = (int*)my_malloc(sizeof(int)*(ny + 1)); - cur_spice_model->cby_index_high[ix] = (int*)my_malloc(sizeof(int)*(ny + 1)); - } - - zero_one_spice_model_routing_index_low_high(cur_spice_model); - - return; -} - -void free_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model) { - int ix; - - /* index_high */ - for (ix = 0; ix < (nx + 1); ix++) { - my_free(cur_spice_model->sb_index_low[ix]); - my_free(cur_spice_model->cbx_index_low[ix]); - my_free(cur_spice_model->cby_index_low[ix]); - - my_free(cur_spice_model->sb_index_high[ix]); - my_free(cur_spice_model->cbx_index_high[ix]); - my_free(cur_spice_model->cby_index_high[ix]); - } - my_free(cur_spice_model->sb_index_low); - my_free(cur_spice_model->cbx_index_low); - my_free(cur_spice_model->cby_index_low); - - my_free(cur_spice_model->sb_index_high); - my_free(cur_spice_model->cbx_index_high); - my_free(cur_spice_model->cby_index_high); - - return; -} - -void free_spice_model_routing_index_low_high(int num_spice_models, - t_spice_model* spice_model) { - int i; - - for (i = 0; i < num_spice_models; i++) { - free_one_spice_model_routing_index_low_high(&(spice_model[i])); - } - - return; -} - -void update_one_spice_model_routing_index_high(int x, int y, t_rr_type chan_type, - t_spice_model* cur_spice_model) { - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - assert(NULL != cur_spice_model); - assert(NULL != cur_spice_model->sb_index_high); - assert(NULL != cur_spice_model->sb_index_high[x]); - assert(NULL != cur_spice_model->cbx_index_high); - assert(NULL != cur_spice_model->cbx_index_high[x]); - assert(NULL != cur_spice_model->cby_index_high); - assert(NULL != cur_spice_model->cby_index_high[x]); - - /* Assigne the low */ - if (CHANX == chan_type) { - cur_spice_model->cbx_index_high[x][y] = cur_spice_model->cnt; - } else if (CHANY == chan_type) { - cur_spice_model->cby_index_high[x][y] = cur_spice_model->cnt; - } else if (SOURCE == chan_type) { - cur_spice_model->sb_index_high[x][y] = cur_spice_model->cnt; - } - - return; -} - -void update_spice_models_routing_index_high(int x, int y, t_rr_type chan_type, - int num_spice_models, - t_spice_model* spice_model) { - int i; - - for (i = 0; i < num_spice_models; i++) { - update_one_spice_model_routing_index_high(x, y, chan_type, &(spice_model[i])); - } - - return; -} - -void update_one_spice_model_routing_index_low(int x, int y, t_rr_type chan_type, - t_spice_model* cur_spice_model) { - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - assert(NULL != cur_spice_model); - assert(NULL != cur_spice_model->sb_index_low); - assert(NULL != cur_spice_model->sb_index_low[x]); - assert(NULL != cur_spice_model->cbx_index_low); - assert(NULL != cur_spice_model->cbx_index_low[x]); - assert(NULL != cur_spice_model->cby_index_low); - assert(NULL != cur_spice_model->cby_index_low[x]); - - /* Assigne the low */ - if (CHANX == chan_type) { - cur_spice_model->cbx_index_low[x][y] = cur_spice_model->cnt; - } else if (CHANY == chan_type) { - cur_spice_model->cby_index_low[x][y] = cur_spice_model->cnt; - } else if (SOURCE == chan_type) { - cur_spice_model->sb_index_low[x][y] = cur_spice_model->cnt; - } - - return; -} - -void update_spice_models_routing_index_low(int x, int y, t_rr_type chan_type, - int num_spice_models, - t_spice_model* spice_model) { - int i; - - for (i = 0; i < num_spice_models; i++) { - update_one_spice_model_routing_index_low(x, y, chan_type, &(spice_model[i])); - } - - return; -} - -/* Check if this SPICE model defined as SRAM - * contain necessary ports for its functionality - */ -void check_sram_spice_model_ports(t_spice_model* cur_spice_model, - boolean include_bl_wl) { - int num_output_ports; - t_spice_model_port** output_ports = NULL; - int num_bl_ports; - t_spice_model_port** bl_ports = NULL; - int num_wl_ports; - t_spice_model_port** wl_ports = NULL; - - int iport; - int num_global_ports = 0; - int num_err = 0; - - /* Check the type of SPICE model */ - assert(SPICE_MODEL_SRAM == cur_spice_model->type); - - /* Check if we has 1 output with size 2 */ - output_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_ports, TRUE); - num_global_ports = 0; - for (iport = 0; iport < num_output_ports; iport++) { - if (TRUE == output_ports[iport]->is_global) { - num_global_ports++; - } - } - if ((1 != (num_output_ports - num_global_ports)) - && (2 != (num_output_ports - num_global_ports))) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL should have only 1 non-global output port!\n", - __FILE__, __LINE__); - num_err++; - if (1 != output_ports[0]->size) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL should have a output port with size 1!\n", - __FILE__, __LINE__); - num_err++; - } - } - if (FALSE == include_bl_wl) { - if (0 == num_err) { - return; - } else { - exit(1); - } - } - /* If bl and wl are required, check their existence */ - bl_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_BL, &num_bl_ports, TRUE); - if (1 != num_bl_ports) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL with BL and WL should have only 1 BL port!\n", - __FILE__, __LINE__); - num_err++; - exit(1); - if (1 != bl_ports[0]->size) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL should have a BL port with size 1!\n", - __FILE__, __LINE__); - num_err++; - } - } - - wl_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_WL, &num_wl_ports, TRUE); - if (1 != num_wl_ports) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL with WL and WL should have only 1 WL port!\n", - __FILE__, __LINE__); - num_err++; - exit(1); - if (1 != wl_ports[0]->size) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) SRAM SPICE MODEL should have a WL port with size 1!\n", - __FILE__, __LINE__); - num_err++; - } - } - - if (0 < num_err) { - exit(1); - } - - /* Free */ - my_free(output_ports); - my_free(bl_ports); - my_free(wl_ports); - - return; -} - -void check_ff_spice_model_ports(t_spice_model* cur_spice_model, - boolean is_ccff) { - int iport; - int num_input_ports; - t_spice_model_port** input_ports = NULL; - int num_output_ports; - t_spice_model_port** output_ports = NULL; - int num_clock_ports; - t_spice_model_port** clock_ports = NULL; - - int num_err = 0; - - /* Check the type of SPICE model */ - if (FALSE == is_ccff) { - assert(SPICE_MODEL_FF == cur_spice_model->type); - } else { - assert(SPICE_MODEL_CCFF == cur_spice_model->type); - } - /* Check if we have D, Set and Reset */ - input_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_ports, FALSE); - if (TRUE == is_ccff) { - if (1 > num_input_ports) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) CCFF SPICE MODEL should at least have an input port!\n", - __FILE__, __LINE__); - num_err++; - } - for (iport = 0; iport < num_input_ports; iport++) { - if (1 != input_ports[iport]->size) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) CCFF SPICE MODEL: each input port with size 1!\n", - __FILE__, __LINE__); - num_err++; - } - } - } else { - if (3 != num_input_ports) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) FF SPICE MODEL should have only 3 input port!\n", - __FILE__, __LINE__); - num_err++; - } - for (iport = 0; iport < num_input_ports; iport++) { - if (1 != input_ports[iport]->size) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) FF SPICE MODEL: each input port with size 1!\n", - __FILE__, __LINE__); - num_err++; - } - } - } - /* Check if we have clock */ - clock_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_CLOCK, &num_clock_ports, FALSE); - if (1 > num_clock_ports) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) [FF|CCFF] SPICE MODEL should have at least 1 clock port!\n", - __FILE__, __LINE__); - num_err++; - } - for (iport = 0; iport < num_clock_ports; iport++) { - if (1 != clock_ports[iport]->size) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) [FF|CCFF] SPICE MODEL: 1 clock port with size 1!\n", - __FILE__, __LINE__); - num_err++; - } - } - /* Check if we have output */ - output_ports = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_ports, TRUE); - if (FALSE == is_ccff) { - if (1 != output_ports[0]->size) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) FF SPICE MODEL: each output port with size 1!\n", - __FILE__, __LINE__); - num_err++; - } - } else { - if (2 != num_output_ports) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) CCFF SPICE MODEL should have 2 output ports!\n", - __FILE__, __LINE__); - num_err++; - for (iport = 0; iport < num_output_ports; iport++) { - if (1 != output_ports[iport]->size) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) CCFF SPICE MODEL: the output port (%s) should have a size of 1!\n", - __FILE__, __LINE__, output_ports[iport]->prefix); - num_err++; - } - } - } - } - /* Error out if required */ - if (0 < num_err) { - exit(1); - } - - /* Free */ - my_free(input_ports); - my_free(output_ports); - my_free(clock_ports); - - return; -} - -/* Free a conf_bit_info */ -void free_conf_bit(t_conf_bit* conf_bit) { - return; -} - -void free_conf_bit_info(t_conf_bit_info* conf_bit_info) { - free_conf_bit(conf_bit_info->sram_bit); - my_free(conf_bit_info->sram_bit); - - free_conf_bit(conf_bit_info->bl); - my_free(conf_bit_info->bl); - - free_conf_bit(conf_bit_info->wl); - my_free(conf_bit_info->wl); - - return; -} - -/* Fill the information into a confbit_info */ -t_conf_bit_info* -alloc_one_conf_bit_info(int index, - t_conf_bit* sram_val, - t_conf_bit* bl_val, t_conf_bit* wl_val, - t_spice_model* parent_spice_model) { - t_conf_bit_info* new_conf_bit_info = (t_conf_bit_info*)my_malloc(sizeof(t_conf_bit_info)); - - /* Check if we have a valid conf_bit_info */ - if (NULL == new_conf_bit_info) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Fail to malloc a new conf_bit_info!\n", - __FILE__, __LINE__); - exit(1); - } - /* Fill the information */ - new_conf_bit_info->index = index; - new_conf_bit_info->sram_bit = sram_val; - new_conf_bit_info->bl = bl_val; - new_conf_bit_info->wl = wl_val; - new_conf_bit_info->parent_spice_model = parent_spice_model; - new_conf_bit_info->parent_spice_model_index = parent_spice_model->cnt; - - return new_conf_bit_info; -} - -/* Add an element to linked-list */ -t_llist* -add_conf_bit_info_to_llist(t_llist* head, int index, - t_conf_bit* sram_val, t_conf_bit* bl_val, t_conf_bit* wl_val, - t_spice_model* parent_spice_model) { - t_llist* temp = NULL; - t_conf_bit_info* new_conf_bit_info = NULL; - - /* if head is NULL, we create a head */ - if (NULL == head) { - temp = create_llist(1); - new_conf_bit_info = alloc_one_conf_bit_info(index, sram_val, bl_val, wl_val, parent_spice_model); - assert(NULL != new_conf_bit_info); - temp->dptr = (void*)new_conf_bit_info; - assert(NULL == temp->next); - return temp; - } else { - /* If head is a valid pointer, we add a new element to the tail of this linked-list */ - temp = insert_llist_node_before_head(head); - new_conf_bit_info = alloc_one_conf_bit_info(index, sram_val, bl_val, wl_val, parent_spice_model); - assert(NULL != new_conf_bit_info); - temp->dptr = (void*)new_conf_bit_info; - return temp; - } -} - -/* Find BL and WL ports for a SRAM model. - * And check if the number of BL/WL satisfy the technology needs - */ -void find_bl_wl_ports_spice_model(t_spice_model* cur_spice_model, - int* num_bl_ports, t_spice_model_port*** bl_ports, - int* num_wl_ports, t_spice_model_port*** wl_ports) { - int i; - - /* Check */ - assert(NULL != cur_spice_model); - - /* Find BL ports */ - (*bl_ports) = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_BL, num_bl_ports, TRUE); - /* Find WL ports */ - (*wl_ports) = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_WL, num_wl_ports, TRUE); - - /* port size of BL/WL should be at least 1 !*/ - assert((*num_bl_ports) == (*num_wl_ports)); - - /* Check the size of BL/WL ports */ - switch (cur_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_RRAM: - /* This check may be too tight */ - for (i = 0; i < (*num_bl_ports); i++) { - assert(0 < (*bl_ports)[i]->size); - } - for (i = 0; i < (*num_wl_ports); i++) { - assert(0 < (*wl_ports)[i]->size); - } - break; - case SPICE_MODEL_DESIGN_CMOS: - for (i = 0; i < (*num_bl_ports); i++) { - assert(0 < (*bl_ports)[i]->size); - } - for (i = 0; i < (*num_wl_ports); i++) { - assert(0 < (*wl_ports)[i]->size); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", - __FILE__, __LINE__, cur_spice_model->name); - exit(1); - } - - return; -} - -/* Find BL and WL ports for a SRAM model. - * And check if the number of BL/WL satisfy the technology needs - */ -void find_blb_wlb_ports_spice_model(t_spice_model* cur_spice_model, - int* num_blb_ports, t_spice_model_port*** blb_ports, - int* num_wlb_ports, t_spice_model_port*** wlb_ports) { - /* Check */ - assert(NULL != cur_spice_model); - - /* Find BL ports */ - (*blb_ports) = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_BLB, num_blb_ports, TRUE); - /* Find WL ports */ - (*wlb_ports) = find_spice_model_ports(cur_spice_model, SPICE_MODEL_PORT_WLB, num_wlb_ports, TRUE); - - return; -} - - -/* Functions to manipulate struct sram_orgz_info */ -t_sram_orgz_info* alloc_one_sram_orgz_info() { - return (t_sram_orgz_info*)my_malloc(sizeof(t_sram_orgz_info)); -} - -t_mem_bank_info* alloc_one_mem_bank_info() { - return (t_mem_bank_info*)my_malloc(sizeof(t_mem_bank_info)); -} - -void free_one_mem_bank_info(t_mem_bank_info* mem_bank_info) { - return; -} - -t_ccff_info* alloc_one_ccff_info() { - return (t_ccff_info*)my_malloc(sizeof(t_ccff_info)); -} - -void free_one_ccff_info(t_ccff_info* ccff_info) { - return; -} - -t_standalone_sram_info* alloc_one_standalone_sram_info() { - return (t_standalone_sram_info*)my_malloc(sizeof(t_standalone_sram_info)); -} - -void free_one_standalone_sram_info(t_standalone_sram_info* standalone_sram_info) { - return; -} - -void init_mem_bank_info(t_mem_bank_info* cur_mem_bank_info, - t_spice_model* cur_mem_model) { - assert(NULL != cur_mem_bank_info); - assert(NULL != cur_mem_model); - cur_mem_bank_info->mem_model = cur_mem_model; - cur_mem_bank_info->num_mem_bit = 0; - cur_mem_bank_info->num_bl = 0; - cur_mem_bank_info->num_wl = 0; - cur_mem_bank_info->reserved_bl = 0; - cur_mem_bank_info->reserved_wl = 0; - - return; -} - -void update_mem_bank_info_num_mem_bit(t_mem_bank_info* cur_mem_bank_info, - int num_mem_bit) { - assert(NULL != cur_mem_bank_info); - - cur_mem_bank_info->num_mem_bit = num_mem_bit; - - return; -} - -void init_ccff_info(t_ccff_info* cur_ccff_info, - t_spice_model* cur_mem_model) { - assert(NULL != cur_ccff_info); - assert(NULL != cur_mem_model); - - cur_ccff_info->mem_model = cur_mem_model; - cur_ccff_info->num_mem_bit = 0; - cur_ccff_info->num_ccff = 0; - - return; -} - -void update_ccff_info_num_mem_bit(t_ccff_info* cur_ccff_info, - int num_mem_bit) { - assert(NULL != cur_ccff_info); - - cur_ccff_info->num_mem_bit = num_mem_bit; - - return; -} - -void init_standalone_sram_info(t_standalone_sram_info* cur_standalone_sram_info, - t_spice_model* cur_mem_model) { - assert(NULL != cur_standalone_sram_info); - assert(NULL != cur_mem_model); - - cur_standalone_sram_info->mem_model = cur_mem_model; - cur_standalone_sram_info->num_mem_bit = 0; - cur_standalone_sram_info->num_sram = 0; - - return; -} - -void update_standalone_sram_info_num_mem_bit(t_standalone_sram_info* cur_standalone_sram_info, - int num_mem_bit) { - assert(NULL != cur_standalone_sram_info); - - cur_standalone_sram_info->num_mem_bit = num_mem_bit; - - return; -} - -void init_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, - enum e_sram_orgz cur_sram_orgz_type, - t_spice_model* cur_mem_model, - int grid_nx, int grid_ny) { - int i, num_bl_per_sram, num_wl_per_sram; - int num_bl_ports; - t_spice_model_port** bl_port = NULL; - int num_wl_ports; - t_spice_model_port** wl_port = NULL; - - assert(NULL != cur_sram_orgz_info); - - cur_sram_orgz_info->type = cur_sram_orgz_type; - cur_sram_orgz_info->conf_bit_head = NULL; /* Configuration bits will be allocated later */ - - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_MEMORY_BANK: - cur_sram_orgz_info->mem_bank_info = alloc_one_mem_bank_info(); - init_mem_bank_info(cur_sram_orgz_info->mem_bank_info, cur_mem_model); - find_bl_wl_ports_spice_model(cur_mem_model, - &num_bl_ports, &bl_port, &num_wl_ports, &wl_port); - assert(1 == num_bl_ports); - assert(1 == num_wl_ports); - num_bl_per_sram = bl_port[0]->size; - num_wl_per_sram = wl_port[0]->size; - try_update_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, - num_bl_per_sram, num_wl_per_sram); - break; - case SPICE_SRAM_SCAN_CHAIN: - cur_sram_orgz_info->ccff_info = alloc_one_ccff_info(); - init_ccff_info(cur_sram_orgz_info->ccff_info, cur_mem_model); - break; - case SPICE_SRAM_STANDALONE: - cur_sram_orgz_info->standalone_sram_info = alloc_one_standalone_sram_info(); - init_standalone_sram_info(cur_sram_orgz_info->standalone_sram_info, cur_mem_model); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - - /* Alloc the configuration bit information per grid */ - cur_sram_orgz_info->grid_nx = grid_nx; - cur_sram_orgz_info->grid_ny = grid_ny; - - cur_sram_orgz_info->grid_reserved_conf_bits = (int**)my_malloc(grid_nx*sizeof(int*)); - for (i = 0; i < grid_nx; i++) { - cur_sram_orgz_info->grid_reserved_conf_bits[i] = (int*)my_calloc(grid_ny, sizeof(int)); - } - - cur_sram_orgz_info->grid_conf_bits_lsb = (int**)my_malloc(grid_nx*sizeof(int*)); - for (i = 0; i < grid_nx; i++) { - cur_sram_orgz_info->grid_conf_bits_lsb[i] = (int*)my_calloc(grid_ny, sizeof(int)); - } - - cur_sram_orgz_info->grid_conf_bits_msb = (int**)my_malloc(grid_nx*sizeof(int*)); - for (i = 0; i < grid_nx; i++) { - cur_sram_orgz_info->grid_conf_bits_msb[i] = (int*)my_calloc(grid_ny, sizeof(int)); - } - - return; -} - - -void free_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, - enum e_sram_orgz cur_sram_orgz_type) { - int i; - t_llist* temp = NULL; - - if (NULL == cur_sram_orgz_info) { - return; - } - - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_MEMORY_BANK: - free_one_mem_bank_info(cur_sram_orgz_info->mem_bank_info); - break; - case SPICE_SRAM_SCAN_CHAIN: - free_one_ccff_info(cur_sram_orgz_info->ccff_info); - break; - case SPICE_SRAM_STANDALONE: - free_one_standalone_sram_info(cur_sram_orgz_info->standalone_sram_info); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - - /* Free configuration bits linked-list */ - temp = cur_sram_orgz_info->conf_bit_head; - while(NULL != temp) { - free_conf_bit_info((t_conf_bit_info*)(temp->dptr)); - /* Set the data pointor to NULL, then we can call linked list free function */ - temp->dptr = NULL; - /* Go the next */ - temp = temp->next; - } - free_llist(cur_sram_orgz_info->conf_bit_head); - - /* Free the configuration bit information per grid */ - for (i = 0; i < cur_sram_orgz_info->grid_nx; i++) { - my_free(cur_sram_orgz_info->grid_reserved_conf_bits[i]); - } - my_free(cur_sram_orgz_info->grid_reserved_conf_bits); - - for (i = 0; i < cur_sram_orgz_info->grid_nx; i++) { - my_free(cur_sram_orgz_info->grid_conf_bits_lsb[i]); - } - my_free(cur_sram_orgz_info->grid_conf_bits_lsb); - - for (i = 0; i < cur_sram_orgz_info->grid_nx; i++) { - my_free(cur_sram_orgz_info->grid_conf_bits_msb[i]); - } - my_free(cur_sram_orgz_info->grid_conf_bits_msb); - - return; -} - -void update_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info, - int updated_reserved_bl, int updated_reserved_wl) { - assert(NULL != cur_mem_bank_info); - - cur_mem_bank_info->reserved_bl = updated_reserved_bl; - cur_mem_bank_info->reserved_wl = updated_reserved_wl; - - return; -} - -void get_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info, - int* num_reserved_bl, int* num_reserved_wl) { - assert(NULL != cur_mem_bank_info); - - (*num_reserved_bl) = cur_mem_bank_info->reserved_bl; - (*num_reserved_wl) = cur_mem_bank_info->reserved_wl; - - return; -} - -void update_mem_bank_info_num_blwl(t_mem_bank_info* cur_mem_bank_info, - int updated_bl, int updated_wl) { - assert(NULL != cur_mem_bank_info); - - cur_mem_bank_info->num_bl = updated_bl; - cur_mem_bank_info->num_wl = updated_wl; - - return; -} - -/* Initialize the number of normal/reserved BLs and WLs, mem_bits in sram_orgz_info - * If the updated_reserved_bl|wl is larger than the existed value, - * we update the reserved_bl|wl - */ -void try_update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, - int updated_reserved_bl, int updated_reserved_wl) { - t_spice_model* mem_model = NULL; - int cur_bl, cur_wl; - - /* Check */ - assert(updated_reserved_bl == updated_reserved_wl); - - /* get memory model */ - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); - - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - break; - case SPICE_SRAM_SCAN_CHAIN: - break; - case SPICE_SRAM_MEMORY_BANK: - /* CMOS technology does not need to update */ - switch (mem_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - break; - case SPICE_MODEL_DESIGN_RRAM: - /* get the current number of reserved bls and wls */ - get_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); - if ((updated_reserved_bl > cur_bl) || (updated_reserved_wl > cur_wl)) { - update_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, - updated_reserved_bl, updated_reserved_wl); - update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, - updated_reserved_bl); - update_sram_orgz_info_num_blwl(cur_sram_orgz_info, - updated_reserved_bl, updated_reserved_wl); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of design technology!", - __FILE__, __LINE__ ); - exit(1); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - -} - -/* Force to update the number of reserved BLs and WLs in sram_orgz_info - * we always update the reserved_bl|wl - */ -void update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, - int updated_reserved_bl, int updated_reserved_wl) { - assert(NULL != cur_sram_orgz_info); - - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - break; - case SPICE_SRAM_SCAN_CHAIN: - break; - case SPICE_SRAM_MEMORY_BANK: - update_mem_bank_info_reserved_blwl(cur_sram_orgz_info->mem_bank_info, - updated_reserved_bl, updated_reserved_wl); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - - return; -} - -void get_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, - int* num_reserved_bl, int* num_reserved_wl) { - assert(NULL != cur_sram_orgz_info); - - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - break; - case SPICE_SRAM_SCAN_CHAIN: - break; - case SPICE_SRAM_MEMORY_BANK: - get_mem_bank_info_reserved_blwl(cur_sram_orgz_info->mem_bank_info, - num_reserved_bl, num_reserved_wl); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - - return; -} - -void get_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info, - int* cur_bl, int* cur_wl) { - assert(NULL != cur_bl); - assert(NULL != cur_wl); - assert(NULL != cur_sram_orgz_info); - - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - case SPICE_SRAM_SCAN_CHAIN: - (*cur_bl) = 0; - (*cur_wl) = 0; - break; - case SPICE_SRAM_MEMORY_BANK: - (*cur_bl) = cur_sram_orgz_info->mem_bank_info->num_bl; - (*cur_wl) = cur_sram_orgz_info->mem_bank_info->num_wl; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - - return; -} - -int get_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info) { - - assert(NULL != cur_sram_orgz_info); - - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - return cur_sram_orgz_info->standalone_sram_info->num_mem_bit; - case SPICE_SRAM_SCAN_CHAIN: - return cur_sram_orgz_info->ccff_info->num_mem_bit; - case SPICE_SRAM_MEMORY_BANK: - return cur_sram_orgz_info->mem_bank_info->num_mem_bit; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - - return 0; -} - -void update_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info, - int new_num_mem_bit) { - - assert(NULL != cur_sram_orgz_info); - - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - update_standalone_sram_info_num_mem_bit(cur_sram_orgz_info->standalone_sram_info, new_num_mem_bit); - break; - case SPICE_SRAM_SCAN_CHAIN: - update_ccff_info_num_mem_bit(cur_sram_orgz_info->ccff_info, new_num_mem_bit); - break; - case SPICE_SRAM_MEMORY_BANK: - update_mem_bank_info_num_mem_bit(cur_sram_orgz_info->mem_bank_info, new_num_mem_bit); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - - return; -} - -void update_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info, - int new_bl, int new_wl) { - - assert(NULL != cur_sram_orgz_info); - - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - break; - case SPICE_SRAM_SCAN_CHAIN: - break; - case SPICE_SRAM_MEMORY_BANK: - update_mem_bank_info_num_blwl(cur_sram_orgz_info->mem_bank_info, new_bl, new_wl); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - - return; -} - -void get_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info, - t_spice_model** mem_model_ptr) { - - assert(NULL != cur_sram_orgz_info); - assert(NULL != mem_model_ptr); - - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - (*mem_model_ptr) = cur_sram_orgz_info->standalone_sram_info->mem_model; - break; - case SPICE_SRAM_SCAN_CHAIN: - (*mem_model_ptr) = cur_sram_orgz_info->ccff_info->mem_model; - break; - case SPICE_SRAM_MEMORY_BANK: - (*mem_model_ptr) = cur_sram_orgz_info->mem_bank_info->mem_model; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - - assert(NULL != (*mem_model_ptr)); - - return; -} - -void update_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info, - t_spice_model* cur_mem_model) { - assert(NULL != cur_sram_orgz_info); - - /* According to the type, we allocate structs */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - cur_sram_orgz_info->standalone_sram_info->mem_model = cur_mem_model; - break; - case SPICE_SRAM_SCAN_CHAIN: - cur_sram_orgz_info->ccff_info->mem_model = cur_mem_model; - break; - case SPICE_SRAM_MEMORY_BANK: - cur_sram_orgz_info->mem_bank_info->mem_model = cur_mem_model; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - - return; -} - - -/* Copy from a src sram_orgz_info to a des sram_orgz_info - * The des_orgz_info must be allocated before!!! - */ -void copy_sram_orgz_info(t_sram_orgz_info* des_sram_orgz_info, - t_sram_orgz_info* src_sram_orgz_info) { - t_spice_model* src_mem_model = NULL; - int src_num_bl, src_num_wl; - int ix, iy; - - get_sram_orgz_info_mem_model(src_sram_orgz_info, &src_mem_model); - - /* Start copying */ - des_sram_orgz_info->type = src_sram_orgz_info->type; - update_sram_orgz_info_mem_model(des_sram_orgz_info, src_mem_model); - update_sram_orgz_info_num_mem_bit(des_sram_orgz_info, - get_sram_orgz_info_num_mem_bit(src_sram_orgz_info)); - /* According to the type, we create the diff. */ - switch (des_sram_orgz_info->type) { - case SPICE_SRAM_MEMORY_BANK: - get_sram_orgz_info_num_blwl(src_sram_orgz_info, &src_num_bl, &src_num_wl); - update_sram_orgz_info_num_blwl(des_sram_orgz_info, src_num_bl, src_num_wl); - break; - case SPICE_SRAM_SCAN_CHAIN: - break; - case SPICE_SRAM_STANDALONE: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - /* Copy conf bits */ - for (ix = 0; ix < des_sram_orgz_info->grid_nx; ix++) { - for (iy = 0; iy < des_sram_orgz_info->grid_ny; iy++) { - des_sram_orgz_info->grid_reserved_conf_bits[ix][iy] = src_sram_orgz_info->grid_reserved_conf_bits[ix][iy]; - des_sram_orgz_info->grid_conf_bits_lsb[ix][iy] = src_sram_orgz_info->grid_conf_bits_lsb[ix][iy]; - des_sram_orgz_info->grid_conf_bits_msb[ix][iy] = src_sram_orgz_info->grid_conf_bits_msb[ix][iy]; - } - } - - return; -} - -/* Create a snapshot on the sram_orgz_info, - * return the snapshot - */ -t_sram_orgz_info* snapshot_sram_orgz_info(t_sram_orgz_info* src_sram_orgz_info) { - t_sram_orgz_info* des_sram_orgz_info = NULL; - t_spice_model* src_mem_model = NULL; - - /* allocate the snapshot */ - des_sram_orgz_info = alloc_one_sram_orgz_info(); - - /* initialize the snapshot */ - get_sram_orgz_info_mem_model(src_sram_orgz_info, &src_mem_model); - init_sram_orgz_info(des_sram_orgz_info, src_sram_orgz_info->type, - src_mem_model, src_sram_orgz_info->grid_nx, src_sram_orgz_info->grid_ny); - - /* Start copying */ - copy_sram_orgz_info( des_sram_orgz_info, - src_sram_orgz_info); - - return des_sram_orgz_info; -} - -/* Compare the two sram_orgz_info and store the difference in the sram_orgz_info to return */ -t_sram_orgz_info* diff_sram_orgz_info(t_sram_orgz_info* des_sram_orgz_info, - t_sram_orgz_info* base_sram_orgz_info) { - t_sram_orgz_info* diff_sram_orgz_info = NULL; - t_spice_model* base_mem_model = NULL; - t_spice_model* des_mem_model = NULL; - int des_num_wl, base_num_wl; - int des_num_bl, base_num_bl; - int ix, iy; - - /* Check: we have the same memory organization type */ - assert ( des_sram_orgz_info->type == base_sram_orgz_info->type ); - get_sram_orgz_info_mem_model(base_sram_orgz_info, &base_mem_model); - get_sram_orgz_info_mem_model(des_sram_orgz_info, &des_mem_model); - assert (des_mem_model == base_mem_model); - assert (des_sram_orgz_info->grid_nx == base_sram_orgz_info->grid_nx); - assert (des_sram_orgz_info->grid_ny == base_sram_orgz_info->grid_ny); - - /* allocate the diff copy */ - diff_sram_orgz_info = alloc_one_sram_orgz_info(); - init_sram_orgz_info(diff_sram_orgz_info, des_sram_orgz_info->type, - des_mem_model, des_sram_orgz_info->grid_nx, des_sram_orgz_info->grid_ny); - - /* initialize the diff_copy */ - update_sram_orgz_info_num_mem_bit(diff_sram_orgz_info, - get_sram_orgz_info_num_mem_bit(des_sram_orgz_info) - get_sram_orgz_info_num_mem_bit(base_sram_orgz_info)); - /* According to the type, we create the diff. */ - switch (des_sram_orgz_info->type) { - case SPICE_SRAM_MEMORY_BANK: - get_sram_orgz_info_num_blwl(des_sram_orgz_info, &des_num_bl, &des_num_wl); - get_sram_orgz_info_num_blwl(base_sram_orgz_info, &base_num_bl, &base_num_wl); - update_sram_orgz_info_num_blwl(diff_sram_orgz_info, des_num_bl - base_num_bl, des_num_wl - base_num_wl); - break; - case SPICE_SRAM_SCAN_CHAIN: - break; - case SPICE_SRAM_STANDALONE: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of SRAM organization!", - __FILE__, __LINE__ ); - exit(1); - } - - /* Copy conf bits */ - for (ix = 0; ix < diff_sram_orgz_info->grid_nx; ix++) { - for (iy = 0; iy < diff_sram_orgz_info->grid_ny; iy++) { - diff_sram_orgz_info->grid_reserved_conf_bits[ix][iy] = des_sram_orgz_info->grid_reserved_conf_bits[ix][iy] - base_sram_orgz_info->grid_reserved_conf_bits[ix][iy]; - diff_sram_orgz_info->grid_conf_bits_lsb[ix][iy] = des_sram_orgz_info->grid_conf_bits_lsb[ix][iy] - base_sram_orgz_info->grid_conf_bits_lsb[ix][iy]; - diff_sram_orgz_info->grid_conf_bits_msb[ix][iy] = des_sram_orgz_info->grid_conf_bits_msb[ix][iy] - base_sram_orgz_info->grid_conf_bits_msb[ix][iy]; - } - } - - return diff_sram_orgz_info; -} - - -/* Manipulating functions for struct t_reserved_syntax_char */ -void init_reserved_syntax_char(t_reserved_syntax_char* cur_reserved_syntax_char, - char cur_syntax_char, boolean cur_verilog_reserved, boolean cur_spice_reserved) { - assert(NULL != cur_reserved_syntax_char); - - cur_reserved_syntax_char->syntax_char = cur_syntax_char; - cur_reserved_syntax_char->verilog_reserved = cur_verilog_reserved; - cur_reserved_syntax_char->spice_reserved = cur_spice_reserved; - - return; -} - -void check_mem_model_blwl_inverted(t_spice_model* cur_mem_model, - enum e_spice_model_port_type blwl_port_type, - boolean* blwl_inverted) { - int num_blwl_ports = 0; - t_spice_model_port** blwl_port = NULL; - - /* Check */ - assert((SPICE_MODEL_PORT_BL == blwl_port_type)||(SPICE_MODEL_PORT_WL == blwl_port_type)); - - /* Find BL and WL ports */ - blwl_port = find_spice_model_ports(cur_mem_model, blwl_port_type, &num_blwl_ports, TRUE); - - /* If we cannot find any return with warnings */ - if (0 == num_blwl_ports) { - (*blwl_inverted) = FALSE; - vpr_printf(TIO_MESSAGE_WARNING, "(FILE:%s,[LINE%d])Unable to find any BL/WL port for memory model(%s)!\n", - __FILE__, __LINE__, cur_mem_model->name); - return; - } - - /* Only 1 port should be found */ - assert(1 == num_blwl_ports); - /* And port size should be at least 1 */ - assert(0 < blwl_port[0]->size); - - /* if default value of a BL/WL port is 0, we do not need an inversion. */ - if (0 == blwl_port[0]->default_val) { - (*blwl_inverted) = FALSE; - } else { - /* if default value of a BL/WL port is 1, we need an inversion! */ - assert(1 == blwl_port[0]->default_val); - (*blwl_inverted) = TRUE; - } - - return; -} - - -/* Check if all the SRAM ports have the correct SPICE MODEL */ -void config_spice_models_sram_port_spice_model(int num_spice_model, - t_spice_model* spice_models, - t_spice_model* default_sram_spice_model) { - int i, iport; - - for (i = 0; i < num_spice_model; i++) { - for (iport = 0; iport < spice_models[i].num_port; iport++) { - /* Bypass non SRAM ports */ - if (SPICE_MODEL_PORT_SRAM != spice_models[i].ports[iport].type) { - continue; - } - /* Write for the default SRAM SPICE model! */ - spice_models[i].ports[iport].spice_model = default_sram_spice_model; - /* Only show warning when we try to override the given spice_model_name ! */ - if (NULL == spice_models[i].ports[iport].spice_model_name) { - continue; - } - /* Give a warning !!! */ - if (0 != strcmp(default_sram_spice_model->name, spice_models[i].ports[iport].spice_model_name)) { - vpr_printf(TIO_MESSAGE_WARNING, - "(FILE:%s, LINE[%d]) Overwrite SRAM SPICE MODEL of SPICE model port (name:%s, port:%s) to be the correct one (name:%s)!\n", - __FILE__ ,__LINE__, - spice_models[i].name, - spice_models[i].ports[iport].prefix, - default_sram_spice_model->name); - } - } - } - - return; -} - -/******************************************************************** - * Link the circuit model of SRAM ports of each circuit model - * to a default SRAM circuit model. - * This function aims to ease the XML writing, allowing users to skip - * the circuit model definition for SRAM ports that are used by default - * TODO: Maybe deprecated as we prefer strict definition - *******************************************************************/ -void config_circuit_models_sram_port_to_default_sram_model(CircuitLibrary& circuit_lib, - const CircuitModelId& default_sram_model) { - for (const auto& model : circuit_lib.models()) { - for (const auto& port : circuit_lib.model_ports(model)) { - /* Bypass non SRAM ports */ - if (SPICE_MODEL_PORT_SRAM != circuit_lib.port_type(port)) { - continue; - } - /* Write for the default SRAM SPICE model! */ - circuit_lib.set_port_tri_state_model_id(port, default_sram_model); - /* Only show warning when we try to override the given spice_model_name ! */ - if (circuit_lib.port_tri_state_model_name(port).empty()) { - continue; - } - /* Give a warning !!! */ - if (0 != circuit_lib.model_name(default_sram_model).compare(circuit_lib.port_tri_state_model_name(port))) { - vpr_printf(TIO_MESSAGE_WARNING, - "Overwrite SRAM circuit model for circuit model port (name:%s, port:%s) to be the correct one (name:%s)!\n", - circuit_lib.model_name(model).c_str(), - circuit_lib.port_prefix(port).c_str(), - circuit_lib.model_name(default_sram_model).c_str()); - } - } - } - /* TODO: this should be done right after XML parsing!!! - * Rebuild the submodels for circuit_library, because we have created links for ports - */ - circuit_lib.build_model_links(); -} - -void determine_sb_port_coordinator(t_sb cur_sb_info, int side, - int* port_x, int* port_y) { - /* Check */ - assert ((-1 < side) && (side < 4)); - /* Initialize */ - (*port_x) = -1; - (*port_y) = -1; - - switch (side) { - case TOP: - /* (0 == side) */ - /* 1. Channel Y [x][y+1] inputs */ - (*port_x) = cur_sb_info.x; - (*port_y) = cur_sb_info.y + 1; - break; - case RIGHT: - /* 1 == side */ - /* 2. Channel X [x+1][y] inputs */ - (*port_x) = cur_sb_info.x + 1; - (*port_y) = cur_sb_info.y; - break; - case BOTTOM: - /* 2 == side */ - /* 3. Channel Y [x][y] inputs */ - (*port_x) = cur_sb_info.x; - (*port_y) = cur_sb_info.y; - break; - case LEFT: - /* 3 == side */ - /* 4. Channel X [x][y] inputs */ - (*port_x) = cur_sb_info.x; - (*port_y) = cur_sb_info.y; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid side of sb[%d][%d]!\n", - __FILE__, __LINE__, cur_sb_info.x, cur_sb_info.y, side); - exit(1); - } - - return; -} - -void init_spice_models_tb_cnt(int num_spice_models, - t_spice_model* spice_model) { - int imodel; - - for (imodel = 0; imodel < num_spice_models; imodel++) { - spice_model[imodel].tb_cnt = 0; - } - - return; -} - -void init_spice_models_grid_tb_cnt(int num_spice_models, - t_spice_model* spice_model, - int grid_x, int grid_y) { - int imodel; - - for (imodel = 0; imodel < num_spice_models; imodel++) { - spice_model[imodel].tb_cnt = spice_model[imodel].grid_index_low[grid_x][grid_y]; - } - - return; -} - -void check_spice_models_grid_tb_cnt(int num_spice_models, - t_spice_model* spice_model, - int grid_x, int grid_y, - enum e_spice_model_type spice_model_type_to_check) { - int imodel; - - for (imodel = 0; imodel < num_spice_models; imodel++) { - if (spice_model_type_to_check != spice_model[imodel].type) { - continue; - } - assert(spice_model[imodel].tb_cnt == spice_model[imodel].grid_index_high[grid_x][grid_y]); - } - - return; -} - -boolean check_negative_variation(float avg_val, - t_spice_mc_variation_params variation_params) { - boolean exist_neg_val = FALSE; - - /* Assume only support gaussian variation now */ - if (avg_val < 0.) { - exist_neg_val = TRUE; - } - - return exist_neg_val; -} - -/* Check if this cby_info exists, it may be covered by a heterogenous block */ -boolean is_cb_exist(t_rr_type cb_type, - int cb_x, int cb_y) { - boolean cb_exist = TRUE; - - /* Check */ - assert((!(0 > cb_x))&&(!(cb_x > (nx + 1)))); - assert((!(0 > cb_y))&&(!(cb_y > (ny + 1)))); - - switch (cb_type) { - case CHANX: - /* Border case */ - /* Check the grid under this CB */ - if ((NULL == grid[cb_x][cb_y].type) - ||(EMPTY_TYPE == grid[cb_x][cb_y].type) - ||!(grid[cb_x][cb_y].offset + 1 == grid[cb_x][cb_y].type->height)) { - cb_exist = FALSE; - } - break; - case CHANY: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid CB type! Should be CHANX or CHANY.\n", - __FILE__, __LINE__); - exit(1); - } - - return cb_exist; -} - -/* Count the number of IPIN rr_nodes in a CB_info struct */ -int count_cb_info_num_ipin_rr_nodes(t_cb cur_cb_info) { - int side; - int cnt = 0; - - for (side = 0; side < cur_cb_info.num_sides; side++) { - cnt += cur_cb_info.num_ipin_rr_nodes[side]; - } - - return cnt; -} - -/* Add a subckt file name to a linked list */ -t_llist* add_one_subckt_file_name_to_llist(t_llist* cur_head, - const char* subckt_file_path) { - t_llist* new_head = NULL; - - if (NULL == cur_head) { - new_head = create_llist(1); - new_head->dptr = (void*) my_strdup(subckt_file_path); - } else { - new_head = insert_llist_node_before_head(cur_head); - new_head->dptr = (void*) my_strdup(subckt_file_path); - } - - return new_head; -} - -/* Check if SPICE subckt is already created - * (if they exist in a given linked-list - */ -boolean check_subckt_file_exist_in_llist(t_llist* subckt_llist_head, - char* subckt_file_name) { - t_llist* temp = NULL; - - temp = subckt_llist_head; - while (temp) { - if (0 == strcmp(subckt_file_name, (char*)(temp->dptr))) { - return TRUE; - } - temp = temp->next; - } - - return FALSE; -} - -/* Identify if this is a primitive pb_type */ -boolean is_primitive_pb_type(t_pb_type* cur_pb_type) { - - if ((NULL != cur_pb_type->spice_model_name) - || (NULL != cur_pb_type->physical_pb_type_name)) { - return TRUE; - } - return FALSE; -} - -/* Recursively find all the global ports in the spice_model / sub spice_model - */ -void rec_stats_spice_model_global_ports(const t_spice_model* cur_spice_model, - boolean recursive, - t_llist** spice_model_head) { - int iport; - t_llist* temp = NULL; - - /* Check */ - assert(NULL != cur_spice_model); - if (0 < cur_spice_model->num_port) { - assert(NULL != cur_spice_model->ports); - } - - for (iport = 0; iport < cur_spice_model->num_port; iport++) { - /* if this spice model requires customized netlist to be included, we do not go recursively */ - if (TRUE == recursive) { - /* GO recursively first, and meanwhile count the number of global ports */ - /* For the port that requires another spice_model, i.e., SRAM - * We need include any global port in that spice model - */ - if (NULL != cur_spice_model->ports[iport].spice_model) { - rec_stats_spice_model_global_ports(cur_spice_model->ports[iport].spice_model, - recursive, spice_model_head); - } - } - /* By pass non-global ports*/ - if (FALSE == cur_spice_model->ports[iport].is_global) { - continue; - } - /* Now we have a global port, add it to linked list */ - assert (TRUE == cur_spice_model->ports[iport].is_global); - if (NULL == (*spice_model_head)) { - (*spice_model_head) = create_llist(1); - /* Configure the data pointer of linked list */ - (*spice_model_head)->dptr = (void*) (&cur_spice_model->ports[iport]); - /* Check if this ports exists in the linked list */ - } else if (FALSE == check_dptr_exist_in_llist((*spice_model_head), - (void*)(&cur_spice_model->ports[iport]))) { - /* Non-exist in the current linked-list, a new node is required - * Go to the tail of the linked-list and add a new node - */ - temp = search_llist_tail(*spice_model_head); - temp = insert_llist_node(temp); - /* Configure the data pointer of linked list */ - temp->dptr = (void*) (&cur_spice_model->ports[iport]); - } - } - - return; -} - -/* Create a snapshot on spice_model counter */ -int* snapshot_spice_model_counter(int num_spice_models, - t_spice_model* spice_model) { - int i; - int* snapshot = (int*) my_calloc(num_spice_models, sizeof(int)); - - for (i = 0; i < num_spice_models; i++) { - snapshot[i] = spice_model[i].cnt; - } - - return snapshot; -} - - -void set_spice_model_counter(int num_spice_models, - t_spice_model* spice_model, - int* spice_model_counter) { - int i; - - for (i = 0; i < num_spice_models; i++) { - spice_model[i].cnt = spice_model_counter[i]; - } - - return; -} - -/* Find the vpack_net_num of the outputs of the logical_block */ -void get_logical_block_output_vpack_net_num(t_logical_block* cur_logical_block, - int* num_lb_output_ports, int** num_lb_output_pins, - int*** lb_output_vpack_net_num) { - int iport, ipin; - int num_output_ports = 0; - int* num_output_pins = NULL; - t_model_ports* head = NULL; - int** output_vpack_net_num = NULL; - - assert (NULL != cur_logical_block); - - /* Count how many outputs we have */ - head = cur_logical_block->model->outputs; - while (NULL != head) { - num_output_ports++; - head = head->next; - } - /* Allocate */ - num_output_pins = (int*) my_calloc(num_output_ports, sizeof(int)); - output_vpack_net_num = (int**) my_calloc(num_output_ports, sizeof(int*)); - /* Fill the array */ - iport = 0; - head = cur_logical_block->model->outputs; - while (NULL != head) { - num_output_pins[iport] = head->size; - output_vpack_net_num[iport] = (int*) my_calloc(num_output_pins[iport], sizeof(int)); - /* Fill the array */ - for (ipin = 0; ipin < num_output_pins[iport]; ipin++) { - output_vpack_net_num[iport][ipin] = cur_logical_block->output_nets[iport][ipin]; - } - /* Go to the next */ - head = head->next; - /* Update counter */ - iport++; - } - - assert (iport == num_output_ports); - - /* Assign return values */ - (*num_lb_output_ports) = num_output_ports; - (*num_lb_output_pins) = num_output_pins; - (*lb_output_vpack_net_num) = output_vpack_net_num; - - return; -} - -int get_lut_logical_block_index_with_output_vpack_net_num(int target_vpack_net_num) { - int iblk, iport; - int matched_lb_index = OPEN; - int matched_count = 0; - int num_lut_output_ports; - int* num_lut_output_pins; - int** lut_output_vpack_net_num; - - for (iblk = 0; iblk < num_logical_blocks; iblk++) { - /* Bypass the non-LUT logical block */ - if (VPACK_COMB != logical_block[iblk].type) { - continue; - } - if (LUT_CLASS != logical_block[iblk].pb->pb_graph_node->pb_type->class_type) { - continue; - } - /* Reach here it should be a LUT */ - get_logical_block_output_vpack_net_num(&logical_block[iblk], - &num_lut_output_ports, &num_lut_output_pins, - &lut_output_vpack_net_num); - /* Check */ - assert ( 1 == num_lut_output_ports); - assert ( 1 == num_lut_output_pins[0]); - assert ( OPEN != lut_output_vpack_net_num[0][0]); - - if (target_vpack_net_num == lut_output_vpack_net_num[0][0]) { - matched_lb_index = iblk; - matched_count++; - } - - /* Free */ - my_free(num_lut_output_pins); - for (iport = 0; iport < num_lut_output_ports; iport++) { - my_free(lut_output_vpack_net_num); - } - } - - assert ((0 == matched_count) - || (1 == matched_count)); - - return matched_lb_index; -} - -/* Get the operational clock port from the global port linked list */ -void get_fpga_x2p_global_op_clock_ports(t_llist* head, - int* num_clock_ports, - t_spice_model_port*** clock_port) { - t_llist* temp = head; - t_spice_model_port* cur_port = NULL; - int cnt = 0; - - /* Get the number of clock ports */ - while (NULL != temp) { - cur_port = (t_spice_model_port*)(temp->dptr); - if ( (SPICE_MODEL_PORT_CLOCK == cur_port->type) - && (FALSE == cur_port->is_prog)) { - cnt++; - } - /* Go to the next */ - temp = temp->next; - } - - /* Initialize the counter */ - (*num_clock_ports) = cnt; - - /* Malloc */ - (*clock_port) = (t_spice_model_port**)my_calloc((*num_clock_ports), sizeof(t_spice_model_port*)); - - /* Reset the counter */ - temp = head; - cnt = 0; - /* Fill the return array */ - while (NULL != temp) { - cur_port = (t_spice_model_port*)(temp->dptr); - if ( (SPICE_MODEL_PORT_CLOCK == cur_port->type) - && (FALSE == cur_port->is_prog)) { - (*clock_port)[cnt] = cur_port; - cnt++; - } - /* Go to the next */ - temp = temp->next; - } - - assert (cnt == (*num_clock_ports)); - - return; -} - -/* Get all the clock ports from the global port linked list */ -void get_fpga_x2p_global_all_clock_ports(t_llist* head, - int* num_clock_ports, - t_spice_model_port*** clock_port) { - t_llist* temp = head; - t_spice_model_port* cur_port = NULL; - int cnt = 0; - - /* Get the number of clock ports */ - while (NULL != temp) { - cur_port = (t_spice_model_port*)(temp->dptr); - if ( (SPICE_MODEL_PORT_CLOCK == cur_port->type)) { - cnt++; - } - /* Go to the next */ - temp = temp->next; - } - - /* Initialize the counter */ - (*num_clock_ports) = cnt; - - /* Malloc */ - (*clock_port) = (t_spice_model_port**)my_calloc((*num_clock_ports), sizeof(t_spice_model_port*)); - - /* Reset the counter */ - temp = head; - cnt = 0; - /* Fill the return array */ - while (NULL != temp) { - cur_port = (t_spice_model_port*)(temp->dptr); - if ( (SPICE_MODEL_PORT_CLOCK == cur_port->type)) { - (*clock_port)[cnt] = cur_port; - cnt++; - } - /* Go to the next */ - temp = temp->next; - } - - assert (cnt == (*num_clock_ports)); - - return; -} - -/* Returns the number of char occupied by the int */ -int my_strlen_int(int input_int) { - - int length_input; - char* input_str; - - input_str = my_itoa(input_int); - length_input = strlen(input_str); - - free(input_str); - - return length_input; -} - -boolean my_bool_to_boolean(bool my_bool) { - - if(true == my_bool) { - return TRUE; - } else { - assert (false == my_bool); - return FALSE; - } -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.cpp deleted file mode 100644 index d158568f7..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.cpp +++ /dev/null @@ -1,176 +0,0 @@ -/******************************************************************** - * Most utilized functions in FPGA X2P framework - *******************************************************************/ -#include -#include -#include - -#include "vtr_assert.h" -#include "fpga_x2p_utils.h" - -/******************************************************************** - * Format a directory path: - * 1. Replace "\" with "/" - * 2. add a "/" if the string does not end with a "/" - *******************************************************************/ -std::string format_dir_path(const std::string& dir_path_to_format) { - std::string formatted_dir_path = dir_path_to_format; - - char illegal_back_slash = '\\'; - char legal_back_slash = '/'; - -#ifdef _WIN32 -/* For windows OS, replace any '/' with '\' */ - char illegal_back_slash = '/'; - char legal_back_slash = '\\'; -#endif - - /* Replace "\" with "/" */ - std::replace(formatted_dir_path.begin(), formatted_dir_path.end(), illegal_back_slash, legal_back_slash); - - /* Add a back slash the string is not ended like this! */ - if (legal_back_slash != formatted_dir_path.back()) { - formatted_dir_path.push_back(legal_back_slash); - } - - return formatted_dir_path; -} - -/******************************************************************** - * Extract full file name from a full path of file - * For example: / - * This function will return - ********************************************************************/ -std::string find_path_file_name(const std::string& file_name) { - - char back_slash = '/'; - -#ifdef _WIN32 -/* For windows OS, replace any '/' with '\' */ - char back_slash = '\\'; -#endif - - /* Find the last '/' in the string and return the left part */ - size_t found = file_name.rfind(back_slash); - if (found != std::string::npos) { - return file_name.substr(found + 1); - } - /* Not found. The input is the file name! Return the original string */ - return file_name; -} - -/******************************************************************** - * Extract full directory path from a full path of file - * For example: / - * This function will return - ********************************************************************/ -std::string find_path_dir_name(const std::string& file_name) { - - char back_slash = '/'; - -#ifdef _WIN32 -/* For windows OS, replace any '/' with '\' */ - char back_slash = '\\'; -#endif - - /* Find the last '/' in the string and return the left part */ - size_t found = file_name.rfind(back_slash); - if (found != std::string::npos) { - return file_name.substr(0, found); - } - /* Not found, return an empty string */ - return std::string(); -} - -/******************************************************************** - * Check if the file stream is valid - ********************************************************************/ -void check_file_handler(std::fstream& fp) { - /* Make sure we have a valid file handler*/ - /* Print out debugging information for if the file is not opened/created properly */ - if (!fp.is_open() || !fp.good()) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create file!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * Convert an integer to an one-hot encoding integer array - ********************************************************************/ -std::vector my_ito1hot_vec(const size_t& in_int, const size_t& bin_len) { - /* Make sure we do not have any overflow! */ - VTR_ASSERT ( (in_int <= bin_len) ); - - /* Initialize */ - std::vector ret(bin_len, 0); - - if (bin_len == in_int) { - return ret; /* all zero case */ - } - ret[in_int] = 1; /* Keep a good sequence of bits */ - - return ret; -} - -/******************************************************************** - * Converter an integer to a binary vector - ********************************************************************/ -std::vector my_itobin_vec(const size_t& in_int, const size_t& bin_len) { - std::vector ret(bin_len, 0); - - /* Make sure we do not have any overflow! */ - VTR_ASSERT ( (in_int < pow(2., bin_len)) ); - - size_t temp = in_int; - for (size_t i = 0; i < bin_len; i++) { - if (1 == temp % 2) { - ret[i] = 1; /* Keep a good sequence of bits */ - } - temp = temp / 2; - } - - return ret; -} - -/******************************************************************** - * Create a directory with a given path - ********************************************************************/ -bool create_dir_path(const char* dir_path) { - /* Give up if the path is empty */ - if (NULL == dir_path) { - vpr_printf(TIO_MESSAGE_INFO, - "dir_path is empty and nothing is created.\n"); - return false; - } - - /* Try to create a directory */ - int ret = mkdir(dir_path, S_IRWXU|S_IRWXG|S_IROTH|S_IXOTH); - - /* Analyze the return flag and output status */ - switch (ret) { - case 0: - vpr_printf(TIO_MESSAGE_INFO, - "Create directory(%s)...successfully.\n", - dir_path); - return true; - case -1: - if (EEXIST == errno) { - vpr_printf(TIO_MESSAGE_WARNING, - "Directory(%s) already exists. Will overwrite contents\n", - dir_path); - return true; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "Create directory(%s)...Failed!\n", - dir_path); - exit(1); - return false; - } - - return false; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h deleted file mode 100644 index 119b68f99..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ /dev/null @@ -1,437 +0,0 @@ -#ifndef FPGA_X2P_UTILS_H -#define FPGA_X2P_UTILS_H - -#include -#include -#include - -#include "my_free_fwd.h" -#include "rr_blocks_naming.h" - -std::string format_dir_path(const std::string& dir_path_to_format); - -void check_file_handler(std::fstream& fp); - -std::vector my_ito1hot_vec(const size_t& in_int, const size_t& bin_len); - -std::string find_path_dir_name(const std::string& file_name); - -std::string find_path_file_name(const std::string& file_name); - -std::vector my_itobin_vec(const size_t& in_int, const size_t& bin_len); - -bool create_dir_path(const char* dir_path); - -/* Old functions */ - -char* my_gettime(); - -char* format_dir_path(char* dir_path); /* TODO: TO BE REMOVED !!! */ - -int try_access_file(char* file_path); - -void my_remove_file(char* file_path); - -int create_dir_path(char* dir_path); - -char* my_strcat(const char* str1, - const char* str2); - -int split_path_prog_name(const char* prog_path, - const char split_token, - char** ret_path, - char** ret_prog_name); - -char* chomp_file_name_postfix(char* file_name); - -void fprint_commented_sram_bits(FILE* fp, - int num_sram_bits, int* sram_bits); - -t_spice_model* find_name_matched_spice_model(char* spice_model_name, - int num_spice_model, - t_spice_model* spice_models); - -t_spice_model* get_default_spice_model(enum e_spice_model_type default_spice_model_type, - int num_spice_model, - t_spice_model* spice_models); - -t_spice_model_port* find_spice_model_port_by_name(t_spice_model* cur_spice_model, - char* port_name); - -void config_one_spice_model_buffer(int num_spice_models, - t_spice_model* spice_model, - t_spice_model* cur_spice_model, - t_spice_model_buffer* cur_spice_model_buffer); - -void config_spice_model_input_output_buffers_pass_gate(int num_spice_models, - t_spice_model* spice_model); - -t_spice_model_port** find_spice_model_ports(const t_spice_model* spice_model, - enum e_spice_model_port_type port_type, - int* port_num, boolean ignore_global_port); - -t_spice_model_port** find_spice_model_config_done_ports(t_spice_model* spice_model, - enum e_spice_model_port_type port_type, - int* port_num, boolean ignore_global_port); - - -t_spice_transistor_type* find_mosfet_tech_lib(t_spice_tech_lib tech_lib, - e_spice_trans_type trans_type); - -char* my_ito1hot(int in_int, int bin_len); - -char* my_itobin(int in_int, int bin_len); - -int* my_itobin_int(int in_int, int bin_len); - -char* my_itoa(int input); - -char* fpga_spice_create_one_subckt_filename(const char* file_name_prefix, - int subckt_x, int subckt_y, - char* file_name_postfix); - -char* chomp_spice_node_prefix(char* spice_node_prefix); - -char* format_spice_node_prefix(char* spice_node_prefix); - -t_block* search_mapped_block(int x, int y, int z); - -int* my_decimal2binary(int decimal, - int* binary_len); - -char** fpga_spice_strtok(char* str, - char* delims, - int* len); - -int get_opposite_side(int side); - -char* convert_side_index_to_string(int side); - -char* convert_process_corner_to_string(enum e_process_corner process_corner); - -void init_spice_net_info(t_spice_net_info* spice_net_info); - -t_spice_model* find_iopad_spice_model(int num_spice_model, - t_spice_model* spice_models); - -boolean is_grid_coordinate_in_range(int x_min, - int x_max, - int grid_x); - -char* generate_string_spice_model_type(enum e_spice_model_type spice_model_type); - -int determine_io_grid_side(int x, - int y); - -void find_prev_rr_nodes_with_src(t_rr_node* src_rr_node, - int* num_drive_rr_nodes, - t_rr_node*** drive_rr_nodes, - int** switch_indices); - -int find_path_id_prev_rr_node(int num_drive_rr_nodes, - t_rr_node** drive_rr_nodes, - t_rr_node* src_rr_node); - -int pb_pin_net_num(t_rr_node* pb_rr_graph, - t_pb_graph_pin* pin); - -float pb_pin_density(t_rr_node* pb_rr_graph, - t_pb_graph_pin* pin); - -float pb_pin_probability(t_rr_node* pb_rr_graph, - t_pb_graph_pin* pin); - -int pb_pin_init_value(t_rr_node* pb_rr_graph, - t_pb_graph_pin* pin); - -float get_rr_node_net_density(t_rr_node node); - -float get_rr_node_net_probability(t_rr_node node); - -int get_rr_node_net_init_value(t_rr_node node); - -int recommend_num_sim_clock_cycle(float sim_window_size); - -void auto_select_num_sim_clock_cycle(t_spice* spice, - float signal_density_weight); - -void alloc_spice_model_grid_index_low_high(t_spice_model* cur_spice_model); - -void free_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model); - -void free_spice_model_grid_index_low_high(int num_spice_models, - t_spice_model* spice_model); - -void update_one_spice_model_grid_index_low(int x, int y, - t_spice_model* cur_spice_model); - -void update_spice_models_grid_index_low(int x, int y, - int num_spice_models, - t_spice_model* spice_model); - -void update_one_spice_model_grid_index_high(int x, int y, - t_spice_model* cur_spice_model); - -void update_spice_models_grid_index_high(int x, int y, - int num_spice_models, - t_spice_model* spice_model); - -void zero_one_spice_model_grid_index_low_high(t_spice_model* cur_spice_model); - -void zero_spice_model_grid_index_low_high(int num_spice_models, - t_spice_model* spice_model); - -char* gen_str_spice_model_structure(enum e_spice_model_structure spice_model_structure); - -boolean check_spice_model_structure_match_switch_inf(t_switch_inf target_switch_inf); - - -void init_rr_nodes_vpack_net_num_changed(int LL_num_rr_nodes, - t_rr_node* LL_rr_node); - -void init_rr_nodes_is_parasitic_net(int LL_num_rr_nodes, - t_rr_node* LL_rr_node); - -boolean is_net_pi(t_net* cur_net); - -int check_consistency_logical_block_net_num(t_logical_block* lgk_blk, - int num_inputs, int* input_net_num); - -int rr_node_drive_switch_box(t_rr_node* src_rr_node, - t_rr_node* des_rr_node, - int switch_box_x, - int switch_box_y, - int chan_side); - -void find_drive_rr_nodes_switch_box(int switch_box_x, - int switch_box_y, - t_rr_node* src_rr_node, - int chan_side, - int return_num_only, - int* num_drive_rr_nodes, - t_rr_node*** drive_rr_nodes, - int* switch_index); - -void zero_spice_models_cnt(int num_spice_models, t_spice_model* spice_model); - -void zero_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model); - -void zero_spice_models_routing_index_low_high(int num_spice_models, - t_spice_model* spice_model); - -void alloc_spice_model_routing_index_low_high(t_spice_model* cur_spice_model); - -void free_one_spice_model_routing_index_low_high(t_spice_model* cur_spice_model); - -void free_spice_model_routing_index_low_high(int num_spice_models, - t_spice_model* spice_model); - -void update_one_spice_model_routing_index_high(int x, int y, t_rr_type chan_type, - t_spice_model* cur_spice_model); - -void update_spice_models_routing_index_high(int x, int y, t_rr_type chan_type, - int num_spice_models, - t_spice_model* spice_model); - -void update_one_spice_model_routing_index_low(int x, int y, t_rr_type chan_type, - t_spice_model* cur_spice_model); - -void update_spice_models_routing_index_low(int x, int y, t_rr_type chan_type, - int num_spice_models, - t_spice_model* spice_model); - - -void check_sram_spice_model_ports(t_spice_model* cur_spice_model, - boolean include_bl_wl); - -void check_ff_spice_model_ports(t_spice_model* cur_spice_model, - boolean is_ccff); - -/* Functions to manipulate t_conf_bit and t_conf_bit_info */ -void free_conf_bit(t_conf_bit* conf_bit); -void free_conf_bit_info(t_conf_bit_info* conf_bit_info); - -t_conf_bit_info* -alloc_one_conf_bit_info(int index, - t_conf_bit* sram_val, - t_conf_bit* bl_val, t_conf_bit* wl_val, - t_spice_model* parent_spice_model); - -t_llist* -add_conf_bit_info_to_llist(t_llist* head, int index, - t_conf_bit* sram_val, t_conf_bit* bl_val, t_conf_bit* wl_val, - t_spice_model* parent_spice_model); - - -void find_bl_wl_ports_spice_model(t_spice_model* cur_spice_model, - int* num_bl_ports, t_spice_model_port*** bl_ports, - int* num_wl_ports, t_spice_model_port*** wl_ports); - -void find_blb_wlb_ports_spice_model(t_spice_model* cur_spice_model, - int* num_blb_ports, t_spice_model_port*** blb_ports, - int* num_wlb_ports, t_spice_model_port*** wlb_ports); - - - -/* Functions to manipulate structs of SRAM orgz */ -t_sram_orgz_info* alloc_one_sram_orgz_info(); - -t_mem_bank_info* alloc_one_mem_bank_info(); - -void free_one_mem_bank_info(t_mem_bank_info* mem_bank_info); - -t_ccff_info* alloc_one_ccff_info(); - -void free_one_ccff_info(t_ccff_info* ccff_info); - -t_standalone_sram_info* alloc_one_standalone_sram_info(); - -void free_one_standalone_sram_info(t_standalone_sram_info* standalone_sram_info); - -void init_mem_bank_info(t_mem_bank_info* cur_mem_bank_info, - t_spice_model* cur_mem_model); - -void try_update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, - int updated_reserved_bl, int updated_reserved_wl); - -void update_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info, - int updated_reserved_bl, int updated_reserved_wl); - -void get_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info, - int* num_reserved_bl, int* num_reserved_wl); - -void update_mem_bank_info_num_blwl(t_mem_bank_info* cur_mem_bank_info, - int updated_bl, int updated_wl); - -void get_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, - int* num_reserved_bl, int* num_reserved_wl); - -void update_mem_bank_info_num_mem_bit(t_mem_bank_info* cur_mem_bank_info, - int num_mem_bit); - -void init_ccff_info(t_ccff_info* cur_ccff_info, - t_spice_model* cur_mem_model); - -void update_ccff_info_num_mem_bit(t_ccff_info* cur_ccff_info, - int num_mem_bit); - -void init_standalone_sram_info(t_standalone_sram_info* cur_standalone_sram_info, - t_spice_model* cur_mem_model); - -void update_standalone_sram_info_num_mem_bit(t_standalone_sram_info* cur_standalone_sram_info, - int num_mem_bit); - -void init_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, - enum e_sram_orgz cur_sram_orgz_type, - t_spice_model* cur_mem_model, - int grid_nx, int grid_ny); - -t_sram_orgz_info* snapshot_sram_orgz_info(t_sram_orgz_info* src_sram_orgz_info); - -t_sram_orgz_info* diff_sram_orgz_info(t_sram_orgz_info* des_sram_orgz_info, - t_sram_orgz_info* base_sram_orgz_info); - -void free_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, - enum e_sram_orgz cur_sram_orgz_type); - -void update_sram_orgz_info_reserved_blwl(t_sram_orgz_info* cur_sram_orgz_info, - int updated_reserved_bl, int updated_reserved_wl); - -int get_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info); - -void get_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info, - int* cur_bl, int* cur_wl); - -void update_sram_orgz_info_num_mem_bit(t_sram_orgz_info* cur_sram_orgz_info, - int new_num_mem_bit); - -void update_sram_orgz_info_num_blwl(t_sram_orgz_info* cur_sram_orgz_info, - int new_bl, int new_wl); - -void get_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info, - t_spice_model** mem_model_ptr); - -void update_sram_orgz_info_mem_model(t_sram_orgz_info* cur_sram_orgz_info, - t_spice_model* cur_mem_model); - -void copy_sram_orgz_info(t_sram_orgz_info* des_sram_orgz_info, - t_sram_orgz_info* src_sram_orgz_info); - -void init_reserved_syntax_char(t_reserved_syntax_char* cur_reserved_syntax_char, - char cur_syntax_char, boolean cur_verilog_reserved, boolean cur_spice_reserved); - -void check_mem_model_blwl_inverted(t_spice_model* cur_mem_model, - enum e_spice_model_port_type blwl_port_type, - boolean* blwl_inverted); - - -void config_spice_model_port_inv_spice_model(int num_spice_models, - t_spice_model* spice_model); - -void config_spice_models_sram_port_spice_model(int num_spice_model, - t_spice_model* spice_models, - t_spice_model* default_sram_spice_model); - -void config_circuit_models_sram_port_to_default_sram_model(CircuitLibrary& circuit_lib, - const CircuitModelId& default_sram_model); - -void determine_sb_port_coordinator(t_sb cur_sb_info, int side, - int* port_x, int* port_y); - -void init_spice_models_tb_cnt(int num_spice_models, - t_spice_model* spice_model); - -void init_spice_models_grid_tb_cnt(int num_spice_models, - t_spice_model* spice_model, - int grid_x, int grid_y); - -void check_spice_models_grid_tb_cnt(int num_spice_models, - t_spice_model* spice_model, - int grid_x, int grid_y, - enum e_spice_model_type spice_model_type_to_check); - -boolean check_negative_variation(float avg_val, - t_spice_mc_variation_params variation_params); - -boolean is_cb_exist(t_rr_type cb_type, - int cb_x, int cb_y); - -int count_cb_info_num_ipin_rr_nodes(t_cb cur_cb_info); - -t_llist* add_one_subckt_file_name_to_llist(t_llist* cur_head, - const char* subckt_file_path); - -boolean check_subckt_file_exist_in_llist(t_llist* subckt_llist_head, - char* subckt_file_name); - -boolean is_primitive_pb_type(t_pb_type* cur_pb_type); - -void rec_stats_spice_model_global_ports(const t_spice_model* cur_spice_model, - boolean recursive, - t_llist** spice_model_head); - -int* snapshot_spice_model_counter(int num_spice_models, - t_spice_model* spice_model); - -void set_spice_model_counter(int num_spice_models, - t_spice_model* spice_model, - int* spice_model_counter); - -void get_logical_block_output_vpack_net_num(INP t_logical_block* cur_logical_block, - OUTP int* num_lb_output_ports, OUTP int** num_lb_output_pins, - OUTP int*** lb_output_vpack_net_num); - -int get_lut_logical_block_index_with_output_vpack_net_num(int target_vpack_net_num); - -void get_fpga_x2p_global_op_clock_ports(t_llist* head, - int* num_clock_ports, - t_spice_model_port*** clock_port); - -void get_fpga_x2p_global_all_clock_ports(t_llist* head, - int* num_clock_ports, - t_spice_model_port*** clock_port); - -int my_strlen_int(int input_int); - -boolean my_bool_to_boolean(bool my_bool); -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp deleted file mode 100644 index 86d3aabee..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp +++ /dev/null @@ -1,592 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: link_arch_circuit_lib.cpp - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/08/12 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file includes key functions to link circuit models to the architecture modules - ***********************************************************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "path_delay.h" -#include "stats.h" -#include "route_common.h" - -/* Include vtr libraries */ -#include "vtr_assert.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_timing_utils.h" -#include "fpga_x2p_backannotate_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "verilog_api.h" - -#include "check_circuit_library.h" -#include "link_arch_circuit_lib.h" - -/************************************************************************ - * Find a circuit model with a given name - * Case 1: if the circuit_model_name is not defined, - * we find a default circuit model and check its type - * Case 2: if the circuit_model_name is defined, - * we find a matched circuit model and check its type - ***********************************************************************/ -CircuitModelId link_circuit_model_by_name_and_type(const char* circuit_model_name, - const CircuitLibrary& circuit_lib, - const enum e_spice_model_type& model_type) { - CircuitModelId circuit_model = CircuitModelId::INVALID(); - /* If the circuit_model_name is not defined, we use the default*/ - if (NULL == circuit_model_name) { - circuit_model = circuit_lib.default_model(model_type); - } else { - circuit_model = circuit_lib.model(circuit_model_name); - } - - /* Check the circuit model, we should have one! */ - if (CircuitModelId::INVALID() == circuit_model) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,LINE[%d]) Fail to find a defined circuit model called %s!\n", - __FILE__, __LINE__, - circuit_lib.model_name(circuit_model).c_str()); - return circuit_model; /* Return here, no need to check the model_type */ - } - - /* Check the type of circuit model, make sure it is the one we want */ - if (model_type != circuit_lib.model_type(circuit_model)) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,LINE[%d]) Invalid type when trying to find circuit model called %s! Expect %s but found %s!\n", - __FILE__, __LINE__, - circuit_model_name, - CIRCUIT_MODEL_TYPE_STRING[size_t(model_type)], - CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))]); - } - - return circuit_model; -} - -/************************************************************************ - * Link circuit model to the SRAM organization - * Case 1: standalone organization required a SRAM circuit model - * Case 1: configuration-chain organization required a CCFF circuit model - * Case 1: memory-bank organization required a SRAM circuit model - ***********************************************************************/ -static -void link_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, - const CircuitLibrary& circuit_lib) { - /* If cur_sram_inf_orgz is not initialized, do nothing */ - if (NULL == cur_sram_inf_orgz) { - return; - } - - /* Check the type of SRAM_Ciruit_MODEL required by different sram organization */ - /* check SRAM ports - * Checker for circuit models used by the SRAM organization - * either SRAMs or CCFFs - * 1. It will check the basic port required for SRAMs and CCFFs - * 2. It will check any special ports required for SRAMs and CCFFs - */ - switch (cur_sram_inf_orgz->type) { - case SPICE_SRAM_STANDALONE: - cur_sram_inf_orgz->circuit_model = link_circuit_model_by_name_and_type(cur_sram_inf_orgz->spice_model_name, circuit_lib, SPICE_MODEL_SRAM); - /* check SRAM ports */ - check_sram_circuit_model_ports(circuit_lib, cur_sram_inf_orgz->circuit_model, false); - break; - case SPICE_SRAM_MEMORY_BANK: - cur_sram_inf_orgz->circuit_model = link_circuit_model_by_name_and_type(cur_sram_inf_orgz->spice_model_name, circuit_lib, SPICE_MODEL_SRAM); - /* check if this one has bit lines and word lines */ - check_sram_circuit_model_ports(circuit_lib, cur_sram_inf_orgz->circuit_model, true); - break; - case SPICE_SRAM_SCAN_CHAIN: - /* check Scan-chain Flip-flop ports */ - cur_sram_inf_orgz->circuit_model = link_circuit_model_by_name_and_type(cur_sram_inf_orgz->spice_model_name, circuit_lib, SPICE_MODEL_CCFF); - check_ccff_circuit_model_ports(circuit_lib, cur_sram_inf_orgz->circuit_model); - break; - case SPICE_SRAM_LOCAL_ENCODER: - /* Wipe out LOCAL ENCODER, it is not supported here ! */ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,LINE[%d]) Local encoder SRAM organization is not supported!\n", - __FILE__, __LINE__); - exit(1); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,LINE[%d]) Invalid SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - - /* RRAM Scan-chain is not supported yet. Now just forbidden this option */ - if ( (SPICE_SRAM_SCAN_CHAIN == cur_sram_inf_orgz->type) - && (SPICE_MODEL_DESIGN_RRAM == circuit_lib.design_tech_type(cur_sram_inf_orgz->circuit_model)) ) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,LINE[%d]) RRAM-based Scan-chain Flip-flop has not been supported yet!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -static -void link_sram_inf(t_sram_inf* cur_sram_inf, - const CircuitLibrary& circuit_lib) { - /* We have two branches: - * 1. SPICE SRAM organization information - * 2. Verilog SRAM organization information - */ - link_one_sram_inf_orgz(cur_sram_inf->spice_sram_inf_orgz, - circuit_lib); - - link_one_sram_inf_orgz(cur_sram_inf->verilog_sram_inf_orgz, - circuit_lib); - - return; -} - - -/************************************************************************** - * With given circuit port, find the pb_type port with same name and type - **************************************************************************/ -t_port* find_pb_type_port_match_circuit_model_port(const t_pb_type* pb_type, - const CircuitLibrary& circuit_lib, - const CircuitPortId& circuit_port) { - t_port* ret = NULL; - size_t num_found = 0; - - /* Search ports */ - for (int iport = 0; iport < pb_type->num_ports; iport++) { - /* Match the name and port size*/ - if ( (0 == circuit_lib.port_prefix(circuit_port).compare(pb_type->ports[iport].name)) - && (size_t(pb_type->ports[iport].num_pins) == circuit_lib.port_size(circuit_port))) { - /* Match the type*/ - switch (circuit_lib.port_type(circuit_port)) { - case SPICE_MODEL_PORT_INPUT: - if ((IN_PORT == pb_type->ports[iport].type) - &&(0 == pb_type->ports[iport].is_clock)) { - ret = &(pb_type->ports[iport]); - num_found++; - } - break; - case SPICE_MODEL_PORT_OUTPUT: - if (OUT_PORT == pb_type->ports[iport].type) { - ret = &(pb_type->ports[iport]); - } - break; - case SPICE_MODEL_PORT_CLOCK: - if ((IN_PORT == pb_type->ports[iport].type)&&(1 == pb_type->ports[iport].is_clock)) { - ret = &(pb_type->ports[iport]); - num_found++; - } - break; - case SPICE_MODEL_PORT_INOUT : - if ((INOUT_PORT == pb_type->ports[iport].type)&&(0 == pb_type->ports[iport].is_clock)) { - ret = &(pb_type->ports[iport]); - num_found++; - } - break; - case SPICE_MODEL_PORT_SRAM: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type for circuit model port(%s)!\n", - __FILE__, __LINE__, circuit_lib.port_prefix(circuit_port).c_str()); - exit(1); - } - } - } - - /* We should find only 1 match */ - if (1 < num_found) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])More than 1 pb_type(%s) port match spice_model_port(%s)!\n", - __FILE__, __LINE__, pb_type->name, circuit_lib.port_prefix(circuit_port).c_str()); - exit(1); - } - - return ret; -} - - -/************************************************************************ - * Map (synchronize) pb_type ports to circuit model ports - ***********************************************************************/ -static -int link_pb_type_port_to_circuit_model_ports(const t_pb_type* cur_pb_type, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - - /* Check */ - assert(NULL != cur_pb_type); - - /* Initialize each port */ - for (int iport = 0; iport < cur_pb_type->num_ports; iport++) { - cur_pb_type->ports[iport].circuit_model_port = CircuitPortId::INVALID(); - } - - /* Return if circuit model is NULL */ - if (CircuitModelId::INVALID() == circuit_model) { - return 0; - } - - /* For each port, find a circuit model port, which has the same name and port size */ - for (auto& port : circuit_lib.model_ports(circuit_model)) { - t_port* cur_pb_type_port = find_pb_type_port_match_circuit_model_port(cur_pb_type, circuit_lib, port); - /* Not every spice_model_port can find a mapped pb_type_port. - * Since a pb_type only includes necessary ports in technology mapping. - * ports for physical designs may be ignored ! - */ - if (NULL != cur_pb_type_port) { - cur_pb_type_port->circuit_model_port = port; - } - } - /* Although some spice_model_port may not have a corresponding pb_type_port - * but each pb_type_port should be mapped to a spice_model_port - */ - for (int iport = 0; iport < cur_pb_type->num_ports; iport++) { - if (CircuitPortId::INVALID() == cur_pb_type->ports[iport].circuit_model_port) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Pb_type(%s) Port(%s) cannot find a corresponding port in SPICE model(%s)\n", - __FILE__, __LINE__, cur_pb_type->name, cur_pb_type->ports[iport].name, - circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - } - - return cur_pb_type->num_ports; -} - -/************************************************************************ - * Find a circuit model for an interconnect in pb_type - * Case 1: if the circuit_model_name is not defined, - * we find a default circuit model and check its type - * Case 2: if the circuit_model_name is defined, - * we find a matched circuit model and check its type - ***********************************************************************/ -static -void link_pb_type_interc_circuit_model_by_type(t_interconnect* cur_interc, - const CircuitLibrary& circuit_lib, - const enum e_spice_model_type& model_type) { - - /* If the circuit_model_name is not defined, we use the default*/ - cur_interc->circuit_model = link_circuit_model_by_name_and_type(cur_interc->spice_model_name, - circuit_lib, - model_type); - /* Check the circuit model, we should have one! */ - if (CircuitModelId::INVALID() == cur_interc->circuit_model) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,LINE[%d]) Error in linking circuit model for interconnect(name %s)! Check [LINE%d] in architecture file)!\n", - __FILE__, __LINE__, - cur_interc->name, - cur_interc->line_num); - exit(1); - } - - /* Special check for MUXes: - * If the multiplexers do not have any input buffers, the loop breaker cannot be disabled - */ - if (SPICE_MODEL_MUX == model_type) { - if (NULL != cur_interc->loop_breaker_string) { - if (false == circuit_lib.is_input_buffered(cur_interc->circuit_model)) { - vpr_printf(TIO_MESSAGE_INFO, - "Line[%d] Cannot disable an interconnect without input buffering.\n", - cur_interc->line_num); - } - } - } - - return; -} - -/************************************************************************ - * Find a circuit model for an interconnect in pb_type - * Case 1: if this is a DIRECT interconnection, - * we will try to find a circuit model whose type is WIRE - * Case 2: if this is a COMPLETE interconnection, we should evaluate - * the number of multiplexer required. - * when it does require multiplexers - * we will try to find a circuit model whose type is MUX - * otherwise, - * we will try to find a circuit model whose type is WIRE - * Case 3: if this is a MUX interconnection, - * we will try to find a circuit model whose type is WIRE - ***********************************************************************/ -static -void link_pb_type_interc_circuit_model(t_interconnect* cur_interc, - const CircuitLibrary& circuit_lib) { - switch (cur_interc->type) { - case DIRECT_INTERC: - link_pb_type_interc_circuit_model_by_type(cur_interc, circuit_lib, SPICE_MODEL_WIRE); - break; - case COMPLETE_INTERC: - /* Special for Completer Interconnection: - * 1. The input number is 1, this infers a direct interconnection. - * 2. The input number is larger than 1, this infers multplexers - * according to interconnect[j].num_mux identify the number of input at this level - */ - if (0 == cur_interc->num_mux) { - link_pb_type_interc_circuit_model_by_type(cur_interc, circuit_lib, SPICE_MODEL_WIRE); - } else { - link_pb_type_interc_circuit_model_by_type(cur_interc, circuit_lib, SPICE_MODEL_MUX); - } - break; - case MUX_INTERC: - link_pb_type_interc_circuit_model_by_type(cur_interc, circuit_lib, SPICE_MODEL_MUX); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,LINE[%d]) Unknown type of interconnection (name=%s) defined in architecture file(LINE%d)!\n", - __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); - exit(1); - } - return; -} - -/************************************************************************ - * Walk through the pb_types in a recursive way - * Find circuit_model_name definition in pb_types - * Try to match the name with defined spice_models - ***********************************************************************/ -static -void link_pb_types_circuit_model_rec(t_pb_type* cur_pb_type, - const CircuitLibrary& circuit_lib) { - if (NULL == cur_pb_type) { - vpr_printf(TIO_MESSAGE_WARNING, - "(File:%s,LINE[%d])cur_pb_type is null pointor!\n", - __FILE__, __LINE__); - return; - } - - /* If there is a circuit_model_name or physical_pb_type_name referring to a physical pb type, - * this is a leaf node! - */ - if ( TRUE == is_primitive_pb_type(cur_pb_type) ) { - /* What annoys me is VPR create a sub pb_type for each lut which suppose to be a leaf node - * This may bring software convience but ruins SPICE modeling - */ - if (NULL != cur_pb_type->physical_pb_type_name) { - /* if this is not a physical pb_type, we do not care its circuit_model_name*/ - return; - } - /* Let's find a matched circuit model!*/ - cur_pb_type->circuit_model = circuit_lib.model(cur_pb_type->spice_model_name); - if (CircuitModelId::INVALID() == cur_pb_type->circuit_model) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,LINE[%d]) Fail to find a defined circuit model called %s, in pb_type(%s)!\n", - __FILE__, __LINE__, cur_pb_type->spice_model_name, cur_pb_type->name); - exit(1); - } - /* Map pb_type ports to SPICE model ports*/ - link_pb_type_port_to_circuit_model_ports(cur_pb_type, circuit_lib, cur_pb_type->circuit_model); - return; - } - - /* Otherwise, initialize it to be OPEN node */ - cur_pb_type->circuit_model = CircuitModelId::INVALID(); - - /* Traversal the hierarchy*/ - for (int imode = 0; imode < cur_pb_type->num_modes; imode++) { - /* Task 1: Find the interconnections and match the spice_model */ - for (int jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { - /* Initialize it to be OPEN node */ - cur_pb_type->modes[imode].interconnect[jinterc].circuit_model = CircuitModelId::INVALID(); - link_pb_type_interc_circuit_model(&(cur_pb_type->modes[imode].interconnect[jinterc]), - circuit_lib); - } - /* Task 2: Find the child pb_type, do matching recursively */ - for (int ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - link_pb_types_circuit_model_rec(&(cur_pb_type->modes[imode].pb_type_children[ipb]), circuit_lib); - } - } - return; -} - -/* Check if the spice model structure is the same with the switch_inf structure */ -static -size_t check_circuit_model_structure_match_switch_inf(const t_switch_inf& target_switch_inf, - const CircuitLibrary& circuit_lib) { - size_t num_err = 0; - - VTR_ASSERT_SAFE(CircuitModelId::INVALID() != target_switch_inf.circuit_model); - if (target_switch_inf.structure != circuit_lib.mux_structure(target_switch_inf.circuit_model)) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Mismatch in MUX structure between circuit model(%s, %s) and switch_inf(%s, %s)!\n", - __FILE__, __LINE__, - circuit_lib.model_name(target_switch_inf.circuit_model).c_str(), - CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[size_t(circuit_lib.mux_structure(target_switch_inf.circuit_model))], - target_switch_inf.name, - CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[size_t(target_switch_inf.structure)]); - num_err++; - } - return num_err; -} - - -/************************************************************************ - * Initialize and check circuit models defined in architecture - * Tasks: - * 1. Link the circuit model defined in pb_types and routing switches - * 2. Add default circuit model for any inexplicit definition - ***********************************************************************/ -void link_circuit_library_to_arch(t_arch* arch, - t_det_routing_arch* routing_arch) { - - vpr_printf(TIO_MESSAGE_INFO, "Linking circuit models to modules in FPGA architecture...\n"); - - /* Check Circuit models first*/ - VTR_ASSERT_SAFE( (NULL != arch) && (NULL != arch->spice) ); - - /* 1. Link the circuit model defined in pb_types and routing switches */ - /* Step A: Check routing switches, connection blocks*/ - if (0 >= arch->num_cb_switch) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s, LINE[%d]) Define Switches for Connection Blocks is mandatory in FPGA X2P support! Miss this part in architecture file.\n", - __FILE__,__LINE__); - exit(1); - } - - for (int i = 0; i < arch->num_cb_switch; i++) { - arch->cb_switches[i].circuit_model = link_circuit_model_by_name_and_type(arch->cb_switches[i].spice_model_name, - arch->spice->circuit_lib, SPICE_MODEL_MUX); - if (CircuitModelId::INVALID() == arch->cb_switches[i].circuit_model) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", - __FILE__, __LINE__, arch->cb_switches[i].spice_model_name, arch->cb_switches[i].name); - exit(1); - } - /* Check the circuit model structure is matched with the structure in switch_inf */ - if (0 < check_circuit_model_structure_match_switch_inf(arch->cb_switches[i], arch->spice->circuit_lib)) { - exit(1); - } - } - - /* Step B: Check switch list: Switch Box*/ - if (0 >= arch->num_switches) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s, LINE[%d]) Define Switches for Switch Boxes is mandatory in FPGA X2P support! Miss this part in architecture file.\n", - __FILE__, __LINE__); - exit(1); - } - - for (int i = 0; i < arch->num_switches; i++) { - arch->Switches[i].circuit_model = link_circuit_model_by_name_and_type(arch->Switches[i].spice_model_name, - arch->spice->circuit_lib, SPICE_MODEL_MUX); - if (CircuitModelId::INVALID() == arch->Switches[i].circuit_model) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", - __FILE__, __LINE__, arch->Switches[i].spice_model_name, arch->Switches[i].name); - exit(1); - } - /* Check the spice model structure is matched with the structure in switch_inf */ - if (0 < check_circuit_model_structure_match_switch_inf(arch->Switches[i], arch->spice->circuit_lib)) { - exit(1); - } - } - - /* Update the switches in detailed routing architecture settings*/ - for (int i = 0; i < routing_arch->num_switch; i++) { - switch_inf[i].circuit_model = link_circuit_model_by_name_and_type(switch_inf[i].spice_model_name, - arch->spice->circuit_lib, SPICE_MODEL_MUX); - if (CircuitModelId::INVALID() == switch_inf[i].circuit_model) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", - __FILE__, __LINE__, switch_inf[i].spice_model_name, switch_inf[i].name); - exit(1); - } - } - - /* Step C: Find SRAM Model*/ - link_sram_inf(&(arch->sram_inf), arch->spice->circuit_lib); - - /* Step D: Find the segment circuit_model*/ - for (int i = 0; i < arch->num_segments; i++) { - arch->Segments[i].circuit_model = link_circuit_model_by_name_and_type(arch->Segments[i].spice_model_name, - arch->spice->circuit_lib, SPICE_MODEL_CHAN_WIRE); - if (CircuitModelId::INVALID() == arch->Segments[i].circuit_model) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Segment(Length:%d) is undefined in circuit models!\n", - __FILE__ ,__LINE__, - arch->Segments[i].spice_model_name, - arch->Segments[i].length); - exit(1); - } - } - - /* Step E: Direct connections between CLBs */ - for (int i = 0; i < arch->num_directs; i++) { - arch->Directs[i].circuit_model = link_circuit_model_by_name_and_type(arch->Directs[i].spice_model_name, - arch->spice->circuit_lib, SPICE_MODEL_WIRE); - /* Check Circuit model type */ - if (CircuitModelId::INVALID() == arch->Directs[i].circuit_model) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of CLB to CLB Direct Connection (name=%s) is undefined in circuit models!\n", - __FILE__ ,__LINE__, - arch->Directs[i].spice_model_name, - arch->Directs[i].name); - exit(1); - } - /* Copy it to clb2clb_directs */ - clb2clb_direct[i].circuit_model = arch->Directs[i].circuit_model; - } - - /* 2. Search Complex Blocks (Pb_Types), Link spice_model according to the spice_model_name*/ - for (int i = 0; i < num_types; i++) { - if (NULL != type_descriptors[i].pb_type) { - link_pb_types_circuit_model_rec(type_descriptors[i].pb_type, arch->spice->circuit_lib); - } - } - - vpr_printf(TIO_MESSAGE_INFO, "Linking circuit models to modules in FPGA architecture...Completed\n"); - - return; -} - -/************************************************************************ - * End of file : link_arch_circuit_lib.cpp - ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.h deleted file mode 100644 index f69314377..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.h +++ /dev/null @@ -1,67 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: link_arch_circuit_lib.h - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/08/12 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ - -/* IMPORTANT: - * The following preprocessing flags are added to - * avoid compilation error when this headers are included in more than 1 times - */ -#ifndef LINK_ARCH_CIRCUIT_LIB_H -#define LINK_ARCH_CIRCUIT_LIB_H - -/* - * Notes in include header files in a head file - * Only include the neccessary header files - * that is required by the data types in the function/class declarations! - */ -/* Header files should be included in a sequence */ -/* Standard header files required go first */ - -CircuitModelId link_circuit_model_by_name_and_type(const char* circuit_model_name, - const CircuitLibrary& circuit_lib, - const enum e_spice_model_type& model_type); - -t_port* find_pb_type_port_match_circuit_model_port(const t_pb_type* pb_type, - const CircuitLibrary& circuit_lib, - const CircuitPortId& circuit_port); - -void link_circuit_library_to_arch(t_arch* arch, - t_det_routing_arch* routing_arch); - -#endif - -/************************************************************************ - * End of file : link_arch_circuit_lib.h - ***********************************************************************/ - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp deleted file mode 100644 index 2cce352a3..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.cpp +++ /dev/null @@ -1,772 +0,0 @@ -/****************************************************************************** - * Memember functions for data structure ModuleManager - ******************************************************************************/ -#include -#include -#include -#include "vtr_assert.h" - -#include "circuit_library.h" -#include "module_manager.h" - -/****************************************************************************** - * Public Constructors - ******************************************************************************/ - -/************************************************** - * Public Accessors : Aggregates - *************************************************/ -/* Find all the modules */ -ModuleManager::module_range ModuleManager::modules() const { - return vtr::make_range(ids_.begin(), ids_.end()); -} - -/* Find all the ports belonging to a module */ -ModuleManager::module_port_range ModuleManager::module_ports(const ModuleId& module) const { - /* Validate the module_id */ - VTR_ASSERT(valid_module_id(module)); - return vtr::make_range(port_ids_[module].begin(), port_ids_[module].end()); -} - -/* Find all the nets belonging to a module */ -ModuleManager::module_net_range ModuleManager::module_nets(const ModuleId& module) const { - /* Validate the module_id */ - VTR_ASSERT(valid_module_id(module)); - return vtr::make_range(net_ids_[module].begin(), net_ids_[module].end()); -} - -/* Find all the child modules under a parent module */ -std::vector ModuleManager::child_modules(const ModuleId& parent_module) const { - /* Validate the module_id */ - VTR_ASSERT(valid_module_id(parent_module)); - return children_[parent_module]; -} - -/* Find all the instances under a parent module */ -std::vector ModuleManager::child_module_instances(const ModuleId& parent_module, const ModuleId& child_module) const { - /* Validate the module_id */ - VTR_ASSERT(valid_module_id(parent_module)); - /* Ensure that the child module is in the child list of parent module */ - size_t child_index = children_[parent_module].size(); - for (size_t i = 0; i < children_[parent_module].size(); ++i) { - if (child_module == children_[parent_module][i]) { - child_index = i; - break; - } - } - VTR_ASSERT(child_index != children_[parent_module].size()); - - /* Create a vector, with sequentially increasing numbers */ - std::vector instance_range(num_child_instances_[parent_module][child_index], 0); - std::iota(instance_range.begin(), instance_range.end(), 0); - - return instance_range; -} - -/* Find all the configurable child modules under a parent module */ -std::vector ModuleManager::configurable_children(const ModuleId& parent_module) const { - /* Validate the module_id */ - VTR_ASSERT(valid_module_id(parent_module)); - - return configurable_children_[parent_module]; -} - -/* Find all the instances of configurable child modules under a parent module */ -std::vector ModuleManager::configurable_child_instances(const ModuleId& parent_module) const { - /* Validate the module_id */ - VTR_ASSERT(valid_module_id(parent_module)); - - return configurable_child_instances_[parent_module]; -} - -/* Find the source ids of modules */ -ModuleManager::module_net_src_range ModuleManager::module_net_sources(const ModuleId& module, const ModuleNetId& net) const { - /* Validate the module_id */ - VTR_ASSERT(valid_module_net_id(module, net)); - return vtr::make_range(net_src_ids_[module][net].begin(), net_src_ids_[module][net].end()); -} - -/* Find the sink ids of modules */ -ModuleManager::module_net_sink_range ModuleManager::module_net_sinks(const ModuleId& module, const ModuleNetId& net) const { - /* Validate the module_id */ - VTR_ASSERT(valid_module_net_id(module, net)); - return vtr::make_range(net_sink_ids_[module][net].begin(), net_sink_ids_[module][net].end()); -} - -/****************************************************************************** - * Public Accessors - ******************************************************************************/ -/* Return number of modules */ -size_t ModuleManager::num_modules() const { - return ids_.size(); -} - -/* Return number of net of a module */ -size_t ModuleManager::num_nets(const ModuleId& module) const { - /* Validate the module_id */ - VTR_ASSERT(valid_module_id(module)); - return net_ids_[module].size(); -} - -/* Find the name of a module */ -std::string ModuleManager::module_name(const ModuleId& module_id) const { - /* Validate the module_id */ - VTR_ASSERT(valid_module_id(module_id)); - return names_[module_id]; -} - -/* Get the string of a module port type */ -std::string ModuleManager::module_port_type_str(const enum e_module_port_type& port_type) const { - std::array MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "GPIN PORTS", "GPOUT PORTS", "GPIO PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}}; - return MODULE_PORT_TYPE_STRING[port_type]; -} - -/* Find a list of ports of a module by a given types */ -std::vector ModuleManager::module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const { - /* Validate the module_id */ - VTR_ASSERT(valid_module_id(module_id)); - - std::vector ports; - for (const auto& port : port_ids_[module_id]) { - /* Skip unmatched ports */ - if (port_type != port_types_[module_id][port]) { - continue; - } - ports.push_back(ports_[module_id][port]); - } - - return ports; -} - -/* Find a list of port ids of a module by a given types */ -std::vector ModuleManager::module_port_ids_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const { - /* Validate the module_id */ - VTR_ASSERT(valid_module_id(module_id)); - - std::vector port_ids; - for (const auto& port : port_ids_[module_id]) { - /* Skip unmatched ports */ - if (port_type != port_types_[module_id][port]) { - continue; - } - port_ids.push_back(port_ids_[module_id][port]); - } - - return port_ids; -} - - -/* Find a port of a module by a given name */ -ModulePortId ModuleManager::find_module_port(const ModuleId& module_id, const std::string& port_name) const { - /* Validate the module id */ - VTR_ASSERT(valid_module_id(module_id)); - - /* Iterate over the ports of the module */ - for (const auto& port : port_ids_[module_id]) { - if (0 == port_name.compare(ports_[module_id][port].get_name())) { - /* Find it, return the id */ - return port; - } - } - /* Not found, return an invalid id */ - return ModulePortId::INVALID(); -} - -/* Find the Port information with a given port id */ -BasicPort ModuleManager::module_port(const ModuleId& module_id, const ModulePortId& port_id) const { - /* Validate the module and port id */ - VTR_ASSERT(valid_module_port_id(module_id, port_id)); - return ports_[module_id][port_id]; -} - -/* Find the module id by a given name, return invalid if not found */ -ModuleId ModuleManager::find_module(const std::string& name) const { - if (name_id_map_.find(name) != name_id_map_.end()) { - /* Find it, return the id */ - return name_id_map_.at(name); - } - /* Not found, return an invalid id */ - return ModuleId::INVALID(); -} - -/* Find the number of instances of a child module in the parent module */ -size_t ModuleManager::num_instance(const ModuleId& parent_module, const ModuleId& child_module) const { - size_t child_index = find_child_module_index_in_parent_module(parent_module, child_module); - if (size_t(-1) == child_index) { - /* Not found, return a zero */ - return 0; - } - - return num_child_instances_[parent_module][child_index]; -} - -/* Find the instance name of a child module */ -std::string ModuleManager::instance_name(const ModuleId& parent_module, const ModuleId& child_module, - const size_t& instance_id) const { - /* Validate the id of both parent and child modules */ - VTR_ASSERT ( valid_module_id(parent_module) ); - VTR_ASSERT ( valid_module_id(child_module) ); - - /* Find the index of child module in the child list of parent module */ - size_t child_index = find_child_module_index_in_parent_module(parent_module, child_module); - VTR_ASSERT (child_index < children_[parent_module].size()); - /* Ensure that instance id is valid */ - VTR_ASSERT (instance_id < num_instance(parent_module, child_module)); - return child_instance_names_[parent_module][child_index][instance_id]; -} - -/* Find the instance id of a given instance name */ -size_t ModuleManager::instance_id(const ModuleId& parent_module, const ModuleId& child_module, - const std::string& instance_name) const { - /* Validate the id of both parent and child modules */ - VTR_ASSERT ( valid_module_id(parent_module) ); - VTR_ASSERT ( valid_module_id(child_module) ); - - /* Find the index of child module in the child list of parent module */ - size_t child_index = find_child_module_index_in_parent_module(parent_module, child_module); - VTR_ASSERT (child_index < children_[parent_module].size()); - - /* Search the instance name list and try to find a match */ - for (size_t name_id = 0; name_id < child_instance_names_[parent_module][child_index].size(); ++name_id) { - const std::string& name = child_instance_names_[parent_module][child_index][name_id]; - if (0 == name.compare(instance_name)) { - return name_id; - } - } - - /* Not found, return an invalid name */ - return size_t(-1); -} - -/* Find if a port is a wire connection */ -bool ModuleManager::port_is_wire(const ModuleId& module, const ModulePortId& port) const { - /* validate both module id and port id*/ - VTR_ASSERT(valid_module_port_id(module, port)); - return port_is_wire_[module][port]; -} - -/* Find if a port is register */ -bool ModuleManager::port_is_register(const ModuleId& module, const ModulePortId& port) const { - /* validate both module id and port id*/ - VTR_ASSERT(valid_module_port_id(module, port)); - return port_is_register_[module][port]; -} - -/* Return the pre-processing flag of a port */ -std::string ModuleManager::port_preproc_flag(const ModuleId& module, const ModulePortId& port) const { - /* validate both module id and port id*/ - VTR_ASSERT(valid_module_port_id(module, port)); - return port_preproc_flags_[module][port]; -} - -/* Find a net from an instance of a module */ -ModuleNetId ModuleManager::module_instance_port_net(const ModuleId& parent_module, - const ModuleId& child_module, const size_t& child_instance, - const ModulePortId& child_port, const size_t& child_pin) const { - /* Validate parent_module */ - VTR_ASSERT(valid_module_id(parent_module)); - - /* Validate child_module */ - VTR_ASSERT(valid_module_id(child_module)); - - /* Validate instance id */ - if (child_module == parent_module) { - /* Assume a default instance id as zero */ - VTR_ASSERT(0 == child_instance); - } else { - VTR_ASSERT(child_instance < num_instance(parent_module, child_module)); - } - - /* Validate child_port */ - VTR_ASSERT(valid_module_port_id(child_module, child_port)); - - /* Validate child_pin */ - VTR_ASSERT(child_pin < module_port(child_module, child_port).get_width()); - - return net_lookup_[parent_module][child_module][child_instance][child_port][child_pin]; -} - -/* Find the name of net */ -std::string ModuleManager::net_name(const ModuleId& module, const ModuleNetId& net) const { - /* Validate module net */ - VTR_ASSERT(valid_module_net_id(module, net)); - - return net_names_[module][net]; -} - -/* Find the source modules of a net */ -vtr::vector ModuleManager::net_source_modules(const ModuleId& module, const ModuleNetId& net) const { - /* Validate module net */ - VTR_ASSERT(valid_module_net_id(module, net)); - - return net_src_module_ids_[module][net]; -} - -/* Find the ids of source instances of a net */ -vtr::vector ModuleManager::net_source_instances(const ModuleId& module, const ModuleNetId& net) const { - /* Validate module net */ - VTR_ASSERT(valid_module_net_id(module, net)); - - return net_src_instance_ids_[module][net]; -} - -/* Find the source ports of a net */ -vtr::vector ModuleManager::net_source_ports(const ModuleId& module, const ModuleNetId& net) const { - /* Validate module net */ - VTR_ASSERT(valid_module_net_id(module, net)); - - return net_src_port_ids_[module][net]; -} - -/* Find the source pin indices of a net */ -vtr::vector ModuleManager::net_source_pins(const ModuleId& module, const ModuleNetId& net) const { - /* Validate module net */ - VTR_ASSERT(valid_module_net_id(module, net)); - - return net_src_pin_ids_[module][net]; -} - -/* Identify if a pin of a port in a module already exists in the net source list*/ -bool ModuleManager::net_source_exist(const ModuleId& module, const ModuleNetId& net, - const ModuleId& src_module, const size_t& instance_id, - const ModulePortId& src_port, const size_t& src_pin) { - /* Validate module net */ - VTR_ASSERT(valid_module_net_id(module, net)); - - /* Iterate over each source of the net. - * If a net source has the same src_module, instance_id, src_port and src_pin, - * we can say that the source has already been added to this net! - */ - for (const ModuleNetSrcId& net_src : module_net_sources(module, net)) { - if ( (src_module == net_source_modules(module, net)[net_src]) - && (instance_id == net_source_instances(module, net)[net_src]) - && (src_port == net_source_ports(module, net)[net_src]) - && (src_pin == net_source_pins(module, net)[net_src]) ) { - return true; - } - } - - /* Reach here, it means nothing has been found. Return false */ - return false; -} - -/* Find the sink modules of a net */ -vtr::vector ModuleManager::net_sink_modules(const ModuleId& module, const ModuleNetId& net) const { - /* Validate module net */ - VTR_ASSERT(valid_module_net_id(module, net)); - - return net_sink_module_ids_[module][net]; -} - -/* Find the ids of sink instances of a net */ -vtr::vector ModuleManager::net_sink_instances(const ModuleId& module, const ModuleNetId& net) const { - /* Validate module net */ - VTR_ASSERT(valid_module_net_id(module, net)); - - return net_sink_instance_ids_[module][net]; -} - -/* Find the sink ports of a net */ -vtr::vector ModuleManager::net_sink_ports(const ModuleId& module, const ModuleNetId& net) const { - /* Validate module net */ - VTR_ASSERT(valid_module_net_id(module, net)); - - return net_sink_port_ids_[module][net]; -} - -/* Find the sink pin indices of a net */ -vtr::vector ModuleManager::net_sink_pins(const ModuleId& module, const ModuleNetId& net) const { - /* Validate module net */ - VTR_ASSERT(valid_module_net_id(module, net)); - - return net_sink_pin_ids_[module][net]; -} - -/* Identify if a pin of a port in a module already exists in the net sink list*/ -bool ModuleManager::net_sink_exist(const ModuleId& module, const ModuleNetId& net, - const ModuleId& sink_module, const size_t& instance_id, - const ModulePortId& sink_port, const size_t& sink_pin) { - /* Validate module net */ - VTR_ASSERT(valid_module_net_id(module, net)); - - /* Iterate over each sink of the net. - * If a net sink has the same sink_module, instance_id, sink_port and sink_pin, - * we can say that the sink has already been added to this net! - */ - for (const ModuleNetSinkId& net_sink : module_net_sinks(module, net)) { - if ( (sink_module == net_sink_modules(module, net)[net_sink]) - && (instance_id == net_sink_instances(module, net)[net_sink]) - && (sink_port == net_sink_ports(module, net)[net_sink]) - && (sink_pin == net_sink_pins(module, net)[net_sink]) ) { - return true; - } - } - - /* Reach here, it means nothing has been found. Return false */ - return false; -} - -/****************************************************************************** - * Private Accessors - ******************************************************************************/ -size_t ModuleManager::find_child_module_index_in_parent_module(const ModuleId& parent_module, const ModuleId& child_module) const { - /* validate both module ids */ - VTR_ASSERT(valid_module_id(parent_module)); - VTR_ASSERT(valid_module_id(child_module)); - /* Try to find the child_module in the children list of parent_module*/ - for (size_t i = 0; i < children_[parent_module].size(); ++i) { - if (child_module == children_[parent_module][i]) { - /* Found, return the number of instances */ - return i; - } - } - /* Not found: return an valid value */ - return size_t(-1); -} - -/****************************************************************************** - * Public Mutators - ******************************************************************************/ -/* Add a module */ -ModuleId ModuleManager::add_module(const std::string& name) { - /* Find if the name has been used. If used, return an invalid Id and report error! */ - std::map::iterator it = name_id_map_.find(name); - if (it != name_id_map_.end()) { - return ModuleId::INVALID(); - } - - /* Create an new id */ - ModuleId module = ModuleId(ids_.size()); - ids_.push_back(module); - - /* Allocate other attributes */ - names_.push_back(name); - parents_.emplace_back(); - children_.emplace_back(); - num_child_instances_.emplace_back(); - child_instance_names_.emplace_back(); - configurable_children_.emplace_back(); - configurable_child_instances_.emplace_back(); - - port_ids_.emplace_back(); - ports_.emplace_back(); - port_types_.emplace_back(); - port_is_wire_.emplace_back(); - port_is_register_.emplace_back(); - port_preproc_flags_.emplace_back(); - - net_ids_.emplace_back(); - net_names_.emplace_back(); - net_src_ids_.emplace_back(); - net_src_module_ids_.emplace_back(); - net_src_instance_ids_.emplace_back(); - net_src_port_ids_.emplace_back(); - net_src_pin_ids_.emplace_back(); - - net_sink_ids_.emplace_back(); - net_sink_module_ids_.emplace_back(); - net_sink_instance_ids_.emplace_back(); - net_sink_port_ids_.emplace_back(); - net_sink_pin_ids_.emplace_back(); - - /* Register in the name-to-id map */ - name_id_map_[name] = module; - - /* Build port lookup */ - port_lookup_.emplace_back(); - port_lookup_[module].resize(NUM_MODULE_PORT_TYPES); - - /* Build fast look-up for nets */ - net_lookup_.emplace_back(); - /* Reserve the instance 0 for the module */ - net_lookup_[module][module].emplace_back(); - - /* Return the new id */ - return module; -} - -/* Add a port to a module */ -ModulePortId ModuleManager::add_port(const ModuleId& module, - const BasicPort& port_info, const enum e_module_port_type& port_type) { - /* Validate the id of module */ - VTR_ASSERT( valid_module_id(module) ); - - /* Add port and fill port attributes */ - ModulePortId port = ModulePortId(port_ids_[module].size()); - port_ids_[module].push_back(port); - ports_[module].push_back(port_info); - port_types_[module].push_back(port_type); - port_is_wire_[module].push_back(false); - port_is_register_[module].push_back(false); - port_preproc_flags_[module].emplace_back(); /* Create an empty string for the pre-processing flags */ - - /* Update fast look-up for port */ - port_lookup_[module][port_type].push_back(port); - - /* Update fast look-up for nets */ - VTR_ASSERT_SAFE(1 == net_lookup_[module][module].size()); - net_lookup_[module][module][0][port].resize(port_info.get_width(), ModuleNetId::INVALID()); - - return port; -} - -/* Set a name for a module port */ -void ModuleManager::set_module_port_name(const ModuleId& module, const ModulePortId& module_port, - const std::string& port_name) { - /* Validate the id of module port */ - VTR_ASSERT( valid_module_port_id(module, module_port) ); - - ports_[module][module_port].set_name(port_name); -} - -/* Set a name for a module */ -void ModuleManager::set_module_name(const ModuleId& module, const std::string& name) { - /* Validate the id of module */ - VTR_ASSERT( valid_module_id(module) ); - names_[module] = name; -} - -/* Set a port to be a wire */ -void ModuleManager::set_port_is_wire(const ModuleId& module, const std::string& port_name, const bool& is_wire) { - /* Find the port */ - ModulePortId port = find_module_port(module, port_name); - /* Must find something, otherwise drop an error */ - VTR_ASSERT(ModulePortId::INVALID() != port); - port_is_wire_[module][port] = is_wire; -} - -/* Set a port to be a register */ -void ModuleManager::set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register) { - /* Find the port */ - ModulePortId port = find_module_port(module, port_name); - /* Must find something, otherwise drop an error */ - VTR_ASSERT(ModulePortId::INVALID() != port); - port_is_register_[module][port] = is_register; -} - -/* Set the preprocessing flag for a port */ -void ModuleManager::set_port_preproc_flag(const ModuleId& module, const ModulePortId& port, const std::string& preproc_flag) { - /* Must find something, otherwise drop an error */ - VTR_ASSERT(valid_module_port_id(module, port)); - port_preproc_flags_[module][port] = preproc_flag; -} - -/* Add a child module to a parent module */ -void ModuleManager::add_child_module(const ModuleId& parent_module, const ModuleId& child_module) { - /* Validate the id of both parent and child modules */ - VTR_ASSERT ( valid_module_id(parent_module) ); - VTR_ASSERT ( valid_module_id(child_module) ); - - /* Try to find if the parent module is already in the list */ - std::vector::iterator parent_it = std::find(parents_[child_module].begin(), parents_[child_module].end(), parent_module); - if (parent_it == parents_[child_module].end()) { - /* Update the parent module of child module */ - parents_[child_module].push_back(parent_module); - } - - std::vector::iterator child_it = std::find(children_[parent_module].begin(), children_[parent_module].end(), child_module); - if (child_it == children_[parent_module].end()) { - /* Update the child module of parent module */ - children_[parent_module].push_back(child_module); - num_child_instances_[parent_module].push_back(1); /* By default give one */ - /* Update the instance name list */ - child_instance_names_[parent_module].emplace_back(); - child_instance_names_[parent_module].back().emplace_back(); - } else { - /* Increase the counter of instances */ - num_child_instances_[parent_module][child_it - children_[parent_module].begin()]++; - child_instance_names_[parent_module][child_it - children_[parent_module].begin()].emplace_back(); - } - - /* Update fast look-up for nets */ - size_t instance_id = net_lookup_[parent_module][child_module].size(); - net_lookup_[parent_module][child_module].emplace_back(); - /* Find the ports for the child module and update the fast look-up */ - for (ModulePortId child_port : port_ids_[child_module]) { - net_lookup_[parent_module][child_module][instance_id][child_port].resize(ports_[child_module][child_port].get_width(), ModuleNetId::INVALID()); - } -} - -/* Set the instance name of a child module */ -void ModuleManager::set_child_instance_name(const ModuleId& parent_module, - const ModuleId& child_module, - const size_t& instance_id, - const std::string& instance_name) { - /* Validate the id of both parent and child modules */ - VTR_ASSERT ( valid_module_id(parent_module) ); - VTR_ASSERT ( valid_module_id(child_module) ); - /* Ensure that the instance id is in range */ - VTR_ASSERT ( instance_id < num_instance(parent_module, child_module)); - /* Try to find the child_module in the children list of parent_module*/ - size_t child_index = find_child_module_index_in_parent_module(parent_module, child_module); - /* We must find something! */ - VTR_ASSERT(size_t(-1) != child_index); - /* Set the name */ - child_instance_names_[parent_module][child_index][instance_id] = instance_name; -} - -/* Add a configurable child module to module - * Note: this function should be called after add_child_module! - * It will check if the child module does exist in the parent module - * And the instance id is in range or not - */ -void ModuleManager::add_configurable_child(const ModuleId& parent_module, - const ModuleId& child_module, - const size_t& child_instance) { - /* Validate the id of both parent and child modules */ - VTR_ASSERT ( valid_module_id(parent_module) ); - VTR_ASSERT ( valid_module_id(child_module) ); - /* Ensure that the instance id is in range */ - VTR_ASSERT ( child_instance < num_instance(parent_module, child_module)); - - configurable_children_[parent_module].push_back(child_module); - configurable_child_instances_[parent_module].push_back(child_instance); -} - -/* Add a net to the connection graph of the module */ -ModuleNetId ModuleManager::create_module_net(const ModuleId& module) { - /* Validate the module id */ - VTR_ASSERT ( valid_module_id(module) ); - - /* Create an new id */ - ModuleNetId net = ModuleNetId(net_ids_[module].size()); - net_ids_[module].push_back(net); - - /* Allocate net-related data structures */ - net_names_[module].emplace_back(); - net_src_ids_[module].emplace_back(); - net_src_module_ids_[module].emplace_back(); - net_src_instance_ids_[module].emplace_back(); - net_src_port_ids_[module].emplace_back(); - net_src_pin_ids_[module].emplace_back(); - - net_sink_ids_[module].emplace_back(); - net_sink_module_ids_[module].emplace_back(); - net_sink_instance_ids_[module].emplace_back(); - net_sink_port_ids_[module].emplace_back(); - net_sink_pin_ids_[module].emplace_back(); - - return net; -} - -/* Set the name of net */ -void ModuleManager::set_net_name(const ModuleId& module, const ModuleNetId& net, - const std::string& name) { - /* Validate module net */ - VTR_ASSERT(valid_module_net_id(module, net)); - - net_names_[module][net] = name; -} - -/* Add a source to a net in the connection graph */ -ModuleNetSrcId ModuleManager::add_module_net_source(const ModuleId& module, const ModuleNetId& net, - const ModuleId& src_module, const size_t& instance_id, - const ModulePortId& src_port, const size_t& src_pin) { - /* Validate the module and net id */ - VTR_ASSERT(valid_module_net_id(module, net)); - - /* Create a new id for src node */ - ModuleNetSrcId net_src = ModuleNetSrcId(net_src_ids_[module][net].size()); - net_src_ids_[module][net].push_back(net_src); - - /* Validate the source module */ - VTR_ASSERT(valid_module_id(src_module)); - net_src_module_ids_[module][net].push_back(src_module); - - /* if it has the same id as module, our instance id will be by default 0 */ - size_t src_instance_id = instance_id; - if (src_module == module) { - src_instance_id = 0; - net_src_instance_ids_[module][net].push_back(src_instance_id); - } else { - /* Check the instance id of the src module */ - VTR_ASSERT (src_instance_id < num_instance(module, src_module)); - net_src_instance_ids_[module][net].push_back(src_instance_id); - } - - /* Validate the port exists in the src module */ - VTR_ASSERT(valid_module_port_id(src_module, src_port)); - net_src_port_ids_[module][net].push_back(src_port); - - /* Validate the pin id is in the range of the port width */ - VTR_ASSERT(src_pin < module_port(src_module, src_port).get_width()); - net_src_pin_ids_[module][net].push_back(src_pin); - - /* Update fast look-up for nets */ - net_lookup_[module][src_module][src_instance_id][src_port][src_pin] = net; - - return net_src; -} - -/* Add a sink to a net in the connection graph */ -ModuleNetSinkId ModuleManager::add_module_net_sink(const ModuleId& module, const ModuleNetId& net, - const ModuleId& sink_module, const size_t& instance_id, - const ModulePortId& sink_port, const size_t& sink_pin) { - /* Validate the module and net id */ - VTR_ASSERT(valid_module_net_id(module, net)); - - /* Create a new id for sink node */ - ModuleNetSinkId net_sink = ModuleNetSinkId(net_sink_ids_[module][net].size()); - net_sink_ids_[module][net].push_back(net_sink); - - /* Validate the source module */ - VTR_ASSERT(valid_module_id(sink_module)); - net_sink_module_ids_[module][net].push_back(sink_module); - - /* if it has the same id as module, our instance id will be by default 0 */ - size_t sink_instance_id = instance_id; - if (sink_module == module) { - sink_instance_id = 0; - net_sink_instance_ids_[module][net].push_back(sink_instance_id); - } else { - /* Check the instance id of the src module */ - VTR_ASSERT (sink_instance_id < num_instance(module, sink_module)); - net_sink_instance_ids_[module][net].push_back(sink_instance_id); - } - - /* Validate the port exists in the sink module */ - VTR_ASSERT(valid_module_port_id(sink_module, sink_port)); - net_sink_port_ids_[module][net].push_back(sink_port); - - /* Validate the pin id is in the range of the port width */ - VTR_ASSERT(sink_pin < module_port(sink_module, sink_port).get_width()); - net_sink_pin_ids_[module][net].push_back(sink_pin); - - /* Update fast look-up for nets */ - net_lookup_[module][sink_module][sink_instance_id][sink_port][sink_pin] = net; - - return net_sink; -} - -/****************************************************************************** - * Private validators/invalidators - ******************************************************************************/ -bool ModuleManager::valid_module_id(const ModuleId& module) const { - return ( size_t(module) < ids_.size() ) && ( module == ids_[module] ); -} - -bool ModuleManager::valid_module_port_id(const ModuleId& module, const ModulePortId& port) const { - if (false == valid_module_id(module)) { - return false; - } - return ( size_t(port) < port_ids_[module].size() ) && ( port == port_ids_[module][port] ); -} - -bool ModuleManager::valid_module_net_id(const ModuleId& module, const ModuleNetId& net) const { - if (false == valid_module_id(module)) { - return false; - } - return ( size_t(net) < net_ids_[module].size() ) && ( net == net_ids_[module][net] ); -} - -void ModuleManager::invalidate_name2id_map() { - name_id_map_.clear(); -} - -void ModuleManager::invalidate_port_lookup() { - port_lookup_.clear(); -} - -void ModuleManager::invalidate_net_lookup() { - net_lookup_.clear(); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h deleted file mode 100644 index 7aaf528f3..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager.h +++ /dev/null @@ -1,236 +0,0 @@ -/****************************************************************************** - * This files includes data structures for module management. - * It keeps a list of modules that have been generated, the port map of the modules, - * parents and children of each modules. This will ease instanciation of modules - * with explicit port map and outputting a hierarchy of modules - * - * Module includes the basic information: - * 1. unique identifier - * 2. module name: which should be unique - * 3. port list: basic information of all the ports belonging to the module - * 4. port types: types of each port, which will matter how we output the ports - * 5. parent modules: ids of parent modules - * 6. children modules: ids of child modules - ******************************************************************************/ - -#ifndef MODULE_MANAGER_H -#define MODULE_MANAGER_H - -#include -#include -#include "vtr_vector.h" -#include "module_manager_fwd.h" -#include "device_port.h" - -class ModuleManager { - public: /* Private data structures */ - enum e_module_port_type { - MODULE_GLOBAL_PORT, /* Global inputs */ - MODULE_GPIN_PORT, /* General-purpose input */ - MODULE_GPOUT_PORT, /* General-purpose outputs, could be used for spypads */ - MODULE_GPIO_PORT, /* General-purpose IOs, which are data IOs of the fabric */ - MODULE_INOUT_PORT, /* Normal (non-global) inout ports */ - MODULE_INPUT_PORT, /* Normal (non-global) input ports */ - MODULE_OUTPUT_PORT, /* Normal (non-global) output ports */ - MODULE_CLOCK_PORT, /* Nromal (non-global) clock ports*/ - NUM_MODULE_PORT_TYPES - }; - - public: /* Public Constructors */ - - public: /* Types and ranges */ - typedef vtr::vector::const_iterator module_iterator; - typedef vtr::vector::const_iterator module_port_iterator; - typedef vtr::vector::const_iterator module_net_iterator; - typedef vtr::vector::const_iterator module_net_src_iterator; - typedef vtr::vector::const_iterator module_net_sink_iterator; - - typedef vtr::Range module_range; - typedef vtr::Range module_port_range; - typedef vtr::Range module_net_range; - typedef vtr::Range module_net_src_range; - typedef vtr::Range module_net_sink_range; - - public: /* Public aggregators */ - /* Find all the modules */ - module_range modules() const; - /* Find all the ports belonging to a module */ - module_port_range module_ports(const ModuleId& module) const; - /* Find all the nets belonging to a module */ - module_net_range module_nets(const ModuleId& module) const; - /* Find all the child modules under a parent module */ - std::vector child_modules(const ModuleId& parent_module) const; - /* Find all the instances under a parent module */ - std::vector child_module_instances(const ModuleId& parent_module, const ModuleId& child_module) const; - /* Find all the configurable child modules under a parent module */ - std::vector configurable_children(const ModuleId& parent_module) const; - /* Find all the instances of configurable child modules under a parent module */ - std::vector configurable_child_instances(const ModuleId& parent_module) const; - /* Find the source ids of modules */ - module_net_src_range module_net_sources(const ModuleId& module, const ModuleNetId& net) const; - /* Find the sink ids of modules */ - module_net_sink_range module_net_sinks(const ModuleId& module, const ModuleNetId& net) const; - - public: /* Public accessors */ - size_t num_modules() const; - size_t num_nets(const ModuleId& module) const; - std::string module_name(const ModuleId& module_id) const; - std::string module_port_type_str(const enum e_module_port_type& port_type) const; - std::vector module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const; - std::vector module_port_ids_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const; - /* Find a port of a module by a given name */ - ModulePortId find_module_port(const ModuleId& module_id, const std::string& port_name) const; - /* Find the Port information with a given port id */ - BasicPort module_port(const ModuleId& module_id, const ModulePortId& port_id) const; - /* Find a module by a given name */ - ModuleId find_module(const std::string& name) const; - /* Find the number of instances of a child module in the parent module */ - size_t num_instance(const ModuleId& parent_module, const ModuleId& child_module) const; - /* Find the instance name of a child module */ - std::string instance_name(const ModuleId& parent_module, const ModuleId& child_module, - const size_t& instance_id) const; - /* Find the instance id of a given instance name */ - size_t instance_id(const ModuleId& parent_module, const ModuleId& child_module, - const std::string& instance_name) const; - /* Find if a port is a wire connection */ - bool port_is_wire(const ModuleId& module, const ModulePortId& port) const; - /* Find if a port is register */ - bool port_is_register(const ModuleId& module, const ModulePortId& port) const; - /* Return the pre-processing flag of a port */ - std::string port_preproc_flag(const ModuleId& module, const ModulePortId& port) const; - /* Find a net from an instance of a module */ - ModuleNetId module_instance_port_net(const ModuleId& parent_module, - const ModuleId& child_module, const size_t& child_instance, - const ModulePortId& child_port, const size_t& child_pin) const; - /* Find the name of net */ - std::string net_name(const ModuleId& module, const ModuleNetId& net) const; - /* Find the source modules of a net */ - vtr::vector net_source_modules(const ModuleId& module, const ModuleNetId& net) const; - /* Find the ids of source instances of a net */ - vtr::vector net_source_instances(const ModuleId& module, const ModuleNetId& net) const; - /* Find the source ports of a net */ - vtr::vector net_source_ports(const ModuleId& module, const ModuleNetId& net) const; - /* Find the source pin indices of a net */ - vtr::vector net_source_pins(const ModuleId& module, const ModuleNetId& net) const; - /* Identify if a pin of a port in a module already exists in the net source list*/ - bool net_source_exist(const ModuleId& module, const ModuleNetId& net, - const ModuleId& src_module, const size_t& instance_id, - const ModulePortId& src_port, const size_t& src_pin); - - /* Find the sink modules of a net */ - vtr::vector net_sink_modules(const ModuleId& module, const ModuleNetId& net) const; - /* Find the ids of sink instances of a net */ - vtr::vector net_sink_instances(const ModuleId& module, const ModuleNetId& net) const; - /* Find the sink ports of a net */ - vtr::vector net_sink_ports(const ModuleId& module, const ModuleNetId& net) const; - /* Find the sink pin indices of a net */ - vtr::vector net_sink_pins(const ModuleId& module, const ModuleNetId& net) const; - /* Identify if a pin of a port in a module already exists in the net sink list*/ - bool net_sink_exist(const ModuleId& module, const ModuleNetId& net, - const ModuleId& sink_module, const size_t& instance_id, - const ModulePortId& sink_port, const size_t& sink_pin); - - private: /* Private accessors */ - size_t find_child_module_index_in_parent_module(const ModuleId& parent_module, const ModuleId& child_module) const; - public: /* Public mutators */ - /* Add a module */ - ModuleId add_module(const std::string& name); - /* Add a port to a module */ - ModulePortId add_port(const ModuleId& module, - const BasicPort& port_info, const enum e_module_port_type& port_type); - /* Set a name for a module port */ - void set_module_port_name(const ModuleId& module, const ModulePortId& module_port, const std::string& port_name); - /* Set a name for a module */ - void set_module_name(const ModuleId& module, const std::string& name); - /* Set a port to be a wire */ - void set_port_is_wire(const ModuleId& module, const std::string& port_name, const bool& is_wire); - /* Set a port to be a register */ - void set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register); - /* Set the preprocessing flag for a port */ - void set_port_preproc_flag(const ModuleId& module, const ModulePortId& port, const std::string& preproc_flag); - /* Add a child module to a parent module */ - void add_child_module(const ModuleId& parent_module, const ModuleId& child_module); - /* Set the instance name of a child module */ - void set_child_instance_name(const ModuleId& parent_module, const ModuleId& child_module, const size_t& instance_id, const std::string& instance_name); - /* Add a configurable child module to module */ - void add_configurable_child(const ModuleId& module, const ModuleId& child_module, const size_t& child_instance); - /* Add a net to the connection graph of the module */ - ModuleNetId create_module_net(const ModuleId& module); - /* Set the name of net */ - void set_net_name(const ModuleId& module, const ModuleNetId& net, - const std::string& name); - /* Add a source to a net in the connection graph */ - ModuleNetSrcId add_module_net_source(const ModuleId& module, const ModuleNetId& net, - const ModuleId& src_module, const size_t& instance_id, - const ModulePortId& src_port, const size_t& src_pin); - /* Add a sink to a net in the connection graph */ - ModuleNetSinkId add_module_net_sink(const ModuleId& module, const ModuleNetId& net, - const ModuleId& sink_module, const size_t& instance_id, - const ModulePortId& sink_port, const size_t& sink_pin); - public: /* Public validators/invalidators */ - bool valid_module_id(const ModuleId& module) const; - bool valid_module_port_id(const ModuleId& module, const ModulePortId& port) const; - bool valid_module_net_id(const ModuleId& module, const ModuleNetId& net) const; - private: /* Private validators/invalidators */ - void invalidate_name2id_map(); - void invalidate_port_lookup(); - void invalidate_net_lookup(); - private: /* Internal data */ - /* Module-level data */ - vtr::vector ids_; /* Unique identifier for each Module */ - vtr::vector names_; /* Unique identifier for each Module */ - vtr::vector> parents_; /* Parent modules that include the module */ - vtr::vector> children_; /* Child modules that this module contain */ - vtr::vector> num_child_instances_; /* Number of children instance in each child module */ - vtr::vector>> child_instance_names_; /* Number of children instance in each child module */ - - /* Configurable child modules are used to record the position of configurable modules in bitstream - * The sequence of children in the list denotes which one is configured first, etc. - * Note that the sequence can be totally different from the children_ list - * This is really dependent how the configuration protocol is organized - * which should be made by users/designers - */ - vtr::vector> configurable_children_; /* Child modules with configurable memory bits that this module contain */ - vtr::vector> configurable_child_instances_; /* Instances of child modules with configurable memory bits that this module contain */ - - /* Port-level data */ - vtr::vector> port_ids_; /* List of ports for each Module */ - vtr::vector> ports_; /* List of ports for each Module */ - vtr::vector> port_types_; /* Type of ports */ - vtr::vector> port_is_wire_; /* If the port is a wire, use for Verilog port definition. If enabled: reg */ - vtr::vector> port_is_register_; /* If the port is a register, use for Verilog port definition. If enabled: reg */ - vtr::vector> port_preproc_flags_; /* If a port is available only when a pre-processing flag is enabled. This is to record the pre-processing flags */ - - /* Graph-level data: - * We use nets to model the connection between pins of modules and instances. - * To avoid large memory footprint, we do NOT create pins, - * To enable fast look-up on pins, we create a fast look-up - */ - vtr::vector> net_ids_; /* List of nets for each Module */ - vtr::vector> net_names_; /* Name of net */ - - vtr::vector>> net_src_ids_; /* Unique id of the source that drive the net */ - vtr::vector>> net_src_module_ids_; /* Pin ids that drive the net */ - vtr::vector>> net_src_instance_ids_; /* Pin ids that drive the net */ - vtr::vector>> net_src_port_ids_; /* Pin ids that drive the net */ - vtr::vector>> net_src_pin_ids_; /* Pin ids that drive the net */ - - - vtr::vector>> net_sink_ids_; /* Unique ids of the sink that the net drives */ - vtr::vector>> net_sink_module_ids_; /* Pin ids that the net drives */ - vtr::vector>> net_sink_instance_ids_; /* Pin ids that drive the net */ - vtr::vector>> net_sink_port_ids_; /* Pin ids that drive the net */ - vtr::vector>> net_sink_pin_ids_; /* Pin ids that drive the net */ - - /* fast look-up for module */ - std::map name_id_map_; - /* fast look-up for ports */ - typedef vtr::vector>> PortLookup; - mutable PortLookup port_lookup_; /* [module_ids][port_types][port_ids] */ - - /* fast look-up for nets */ - typedef vtr::vector>>>> NetLookup; - mutable NetLookup net_lookup_; /* [module_ids][module_ids][instance_ids][port_ids][pin_ids] */ -}; - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h deleted file mode 100644 index 6f85339bc..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_fwd.h +++ /dev/null @@ -1,30 +0,0 @@ -/************************************************** - * This file includes only declarations for - * the data structures for module managers - * Please refer to module_manager.h for more details - *************************************************/ -#ifndef MODULE_MANAGER_FWD_H -#define MODULE_MANAGER_FWD_H - -#include "vtr_strong_id.h" - -/* Strong Ids for ModuleManager */ -struct module_id_tag; -struct instance_id_tag; /* TODO: use instance id in module_manager */ -struct module_port_id_tag; -struct module_pin_id_tag; -struct module_net_id_tag; -struct module_net_src_id_tag; -struct module_net_sink_id_tag; - -typedef vtr::StrongId ModuleId; -typedef vtr::StrongId InstanceId; -typedef vtr::StrongId ModulePortId; -typedef vtr::StrongId ModulePinId; -typedef vtr::StrongId ModuleNetId; -typedef vtr::StrongId ModuleNetSrcId; -typedef vtr::StrongId ModuleNetSinkId; - -class ModuleManager; - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp deleted file mode 100644 index 927506096..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp +++ /dev/null @@ -1,1215 +0,0 @@ -/****************************************************************************** - * This files includes most utilized functions - * for data structures for module management. - ******************************************************************************/ - -#include -#include - -#include "util.h" -#include "vtr_assert.h" - -#include "spice_types.h" - -#include "circuit_library.h" -#include "circuit_library_utils.h" -#include "module_manager.h" - -#include "fpga_x2p_naming.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_mem_utils.h" - -#include "module_manager_utils.h" - -/****************************************************************************** - * Add a module to the module manager based on the circuit-level - * description of a circuit model - * This function add a module with a given customized name - * as well as add the ports of circuit model to the module manager - ******************************************************************************/ -ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, - const std::string& module_name) { - ModuleId module = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != module); - - /* Add ports */ - /* Find global ports and add one by one */ - for (const auto& port : circuit_lib.model_global_ports(circuit_model, false)) { - BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - if ( (SPICE_MODEL_PORT_INPUT == circuit_lib.port_type(port)) - && (false == circuit_lib.port_is_io(port)) ) { - module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT); - } else if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(port)) { - module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT); - } else if ( (SPICE_MODEL_PORT_INPUT == circuit_lib.port_type(port)) - && (true == circuit_lib.port_is_io(port)) ) { - module_manager.add_port(module, port_info, ModuleManager::MODULE_GPIN_PORT); - } else { - VTR_ASSERT(SPICE_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)); - module_manager.add_port(module, port_info, ModuleManager::MODULE_GPOUT_PORT); - } - } - - /* Find other ports and add one by one */ - /* Create a type-to-type map for ports */ - std::map port_type2type_map; - port_type2type_map[SPICE_MODEL_PORT_INOUT] = ModuleManager::MODULE_INOUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_INPUT] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_CLOCK] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_SRAM] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_BL] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_BLB] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_WL] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_WLB] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[SPICE_MODEL_PORT_OUTPUT] = ModuleManager::MODULE_OUTPUT_PORT; - - /* Input ports (ignore all the global ports when searching the circuit_lib */ - for (const auto& kv : port_type2type_map) { - for (const auto& port : circuit_lib.model_ports_by_type(circuit_model, kv.first, true)) { - BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - module_manager.add_port(module, port_info, kv.second); - } - } - - /* Return the new id */ - return module; -} - -/****************************************************************************** - * Add a module to the module manager based on the circuit-level - * description of a circuit model - * This function add a module in the name of the circuit model - * as well as add the ports of circuit model to the module manager - * - * This function is a wrapper of a more customizable function in the same name - ******************************************************************************/ -ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { - - return add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model, circuit_lib.model_name(circuit_model)); -} - -/******************************************************************** - * Add a list of ports that are used for reserved SRAM ports to a module - * in the module manager - * The reserved SRAM ports are mainly designed for RRAM-based FPGA, - * which are shared across modules. - * Note that different modules may require different size of reserved - * SRAM ports but their LSB must all start from 0 - * +---------+ - * reserved_sram_port[0:X] --->| ModuleA | - * +---------+ - * - * +---------+ - * reserved_sram_port[0:Y] --->| ModuleB | - * +---------+ - * - ********************************************************************/ -void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager, - const ModuleId& module_id, - const size_t& port_size) { - /* Add a reserved BLB port to the module */ - std::string blb_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_BLB); - BasicPort blb_module_port(blb_port_name, port_size); - /* Add generated ports to the ModuleManager */ - module_manager.add_port(module_id, blb_module_port, ModuleManager::MODULE_INPUT_PORT); - - /* Add a reserved BLB port to the module */ - std::string wl_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_WL); - BasicPort wl_module_port(wl_port_name, port_size); - /* Add generated ports to the ModuleManager */ - module_manager.add_port(module_id, wl_module_port, ModuleManager::MODULE_INPUT_PORT); -} - -/******************************************************************** - * Add a list of ports that are used for formal verification to a module - * in the module manager - * - * The formal verification port will appear only when a pre-processing flag is defined - * This function will add the pre-processing flag along with the port - ********************************************************************/ -void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_manager, - const ModuleId& module_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const std::string& preproc_flag, - const size_t& port_size) { - /* Create a port */ - std::string port_name = generate_formal_verification_sram_port_name(circuit_lib, sram_model); - BasicPort module_port(port_name, port_size); - /* Add generated ports to the ModuleManager */ - ModulePortId port_id = module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); - /* Add pre-processing flag if defined */ - module_manager.set_port_preproc_flag(module_id, port_id, preproc_flag); -} - - -/******************************************************************** - * Add a list of ports that are used for SRAM configuration to a module - * in the module manager - * The type and names of added ports strongly depend on the - * organization of SRAMs. - * 1. Standalone SRAMs: - * two ports will be added, which are regular output and inverted output - * 2. Scan-chain Flip-flops: - * two ports will be added, which are the head of scan-chain - * and the tail of scan-chain - * IMPORTANT: the port size will be forced to 1 in this case - * because the head and tail are both 1-bit ports!!! - * 3. Memory decoders: - * 2-4 ports will be added, depending on the ports available in the SRAM - * Among these, two ports are mandatory: BL and WL - * The other two ports are optional: BLB and WLB - * Note that the constraints are correletated to the checking rules - * in check_circuit_library() - ********************************************************************/ -void add_sram_ports_to_module_manager(ModuleManager& module_manager, - const ModuleId& module_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz sram_orgz_type, - const size_t& num_config_bits) { - std::vector sram_port_names = generate_sram_port_names(circuit_lib, sram_model, sram_orgz_type); - size_t sram_port_size = generate_sram_port_size(sram_orgz_type, num_config_bits); - - /* Add ports to the module manager */ - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - case SPICE_SRAM_MEMORY_BANK: { - for (const std::string& sram_port_name : sram_port_names) { - /* Add generated ports to the ModuleManager */ - BasicPort sram_port(sram_port_name, sram_port_size); - module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT); - } - break; - } - case SPICE_SRAM_SCAN_CHAIN: { - /* Note that configuration chain tail is an output while head is an input - * IMPORTANT: this is co-designed with function generate_sram_port_names() - * If the return vector is changed, the following codes MUST be adapted! - */ - VTR_ASSERT(2 == sram_port_names.size()); - size_t port_counter = 0; - for (const std::string& sram_port_name : sram_port_names) { - /* Add generated ports to the ModuleManager */ - BasicPort sram_port(sram_port_name, sram_port_size); - if (0 == port_counter) { - module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_INPUT_PORT); - } else { - VTR_ASSERT(1 == port_counter); - module_manager.add_port(module_id, sram_port, ModuleManager::MODULE_OUTPUT_PORT); - } - port_counter++; - } - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid type of SRAM organization !\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * Add ports of a pb_type block to module manager - * Port addition will follow the sequence: inout, input, output, clock - * This will help use to keep a clean module definition when printing out - * To avoid port mismatch between the pb_type and its linked circuit model - * This function will also check that each pb_type port is actually exist - * in the linked circuit model - *******************************************************************/ -void add_primitive_pb_type_ports_to_module_manager(ModuleManager& module_manager, - const ModuleId& module_id, - t_pb_type* cur_pb_type) { - - /* Find the inout ports required by the primitive pb_type, and add them to the module */ - std::vector pb_type_inout_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INOUT); - for (auto port : pb_type_inout_ports) { - BasicPort module_port(generate_pb_type_port_name(port), port->num_pins); - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INOUT_PORT); - /* Set the port to be wire-connection */ - module_manager.set_port_is_wire(module_id, module_port.get_name(), true); - } - - /* Find the input ports required by the primitive pb_type, and add them to the module */ - std::vector pb_type_input_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INPUT); - for (auto port : pb_type_input_ports) { - BasicPort module_port(generate_pb_type_port_name(port), port->num_pins); - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_INPUT_PORT); - /* Set the port to be wire-connection */ - module_manager.set_port_is_wire(module_id, module_port.get_name(), true); - } - - /* Find the output ports required by the primitive pb_type, and add them to the module */ - std::vector pb_type_output_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, SPICE_MODEL_PORT_OUTPUT); - for (auto port : pb_type_output_ports) { - BasicPort module_port(generate_pb_type_port_name(port), port->num_pins); - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_OUTPUT_PORT); - /* Set the port to be wire-connection */ - module_manager.set_port_is_wire(module_id, module_port.get_name(), true); - } - - /* Find the clock ports required by the primitive pb_type, and add them to the module */ - std::vector pb_type_clock_ports = find_pb_type_ports_match_circuit_model_port_type(cur_pb_type, SPICE_MODEL_PORT_CLOCK); - for (auto port : pb_type_clock_ports) { - BasicPort module_port(generate_pb_type_port_name(port), port->num_pins); - module_manager.add_port(module_id, module_port, ModuleManager::MODULE_CLOCK_PORT); - /* Set the port to be wire-connection */ - module_manager.set_port_is_wire(module_id, module_port.get_name(), true); - } -} - -/******************************************************************** - * Add ports of a pb_type block to module manager - * This function is designed for non-primitive pb_types, which are - * NOT linked to any circuit model. - * Actually, this makes things much simpler. - * We just iterate over all the ports and add it to the module - * with the naming convention - *******************************************************************/ -void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, - const ModuleId& module_id, - t_pb_type* cur_pb_type) { - /* Create a type-to-type mapping between module ports and pb_type ports */ - std::map port_type2type_map; - port_type2type_map[IN_PORT] = ModuleManager::MODULE_INPUT_PORT; - port_type2type_map[OUT_PORT] = ModuleManager::MODULE_OUTPUT_PORT; - port_type2type_map[INOUT_PORT] = ModuleManager::MODULE_INOUT_PORT; - - for (int port = 0; port < cur_pb_type->num_ports; ++port) { - t_port* pb_type_port = &(cur_pb_type->ports[port]); - BasicPort module_port(generate_pb_type_port_name(pb_type_port), pb_type_port->num_pins); - module_manager.add_port(module_id, module_port, port_type2type_map[pb_type_port->type]); - /* Set the port to be wire-connection */ - module_manager.set_port_is_wire(module_id, module_port.get_name(), true); - } -} - -/******************************************************************** - * Identify if a net is a local wire inside a module: - * A net is a local wire if it connects between two instances, - * It means that any of its source and sink modules should not include current module_id - *******************************************************************/ -bool module_net_is_local_wire(const ModuleManager& module_manager, - const ModuleId& module_id, const ModuleNetId& module_net) { - /* Check all the sink modules of the net, - * if we have a source module is the current module, this is not local wire - */ - for (ModuleId src_module : module_manager.net_source_modules(module_id, module_net)) { - if (module_id == src_module) { - /* Here, this is not a local wire */ - return false; - } - } - - /* Check all the sink modules of the net */ - for (ModuleId sink_module : module_manager.net_sink_modules(module_id, module_net)) { - if (module_id == sink_module) { - /* Here, this is not a local wire */ - return false; - } - } - - return true; -} - -/******************************************************************** - * Identify if a net is an output short connection inside a module: - * The short connection is defined as the direct connection - * between two outputs port of the module - * - * module - * +-----------------------------+ - * | - * src------>+--------------->|--->outputA - * | | - * | | - * +--------------->|--->outputB - * +-----------------------------+ - - *******************************************************************/ -bool module_net_include_output_short_connection(const ModuleManager& module_manager, - const ModuleId& module_id, const ModuleNetId& module_net) { - /* Check all the sink modules of the net */ - size_t contain_num_module_output = 0; - for (ModuleId sink_module : module_manager.net_sink_modules(module_id, module_net)) { - if (module_id == sink_module) { - contain_num_module_output++; - } - } - - /* If we have found more than 1 module outputs, it indicated output short connection! */ - return (1 < contain_num_module_output); -} - -/******************************************************************** - * Identify if a net is a local short connection inside a module: - * The short connection is defined as the direct connection - * between an input port of the module and an output port of the module - * - * module - * +-----------------------------+ - * | | - * inputA--->|---------------------------->|--->outputB - * | | - * | | - * | | - * +-----------------------------+ - *******************************************************************/ -bool module_net_include_local_short_connection(const ModuleManager& module_manager, - const ModuleId& module_id, const ModuleNetId& module_net) { - /* Check all the sink modules of the net, - * if we have a source module is the current module, this is not local wire - */ - bool contain_module_input = false; - for (ModuleId src_module : module_manager.net_source_modules(module_id, module_net)) { - if (module_id == src_module) { - contain_module_input = true; - break; - } - } - - /* Check all the sink modules of the net */ - bool contain_module_output = false; - for (ModuleId sink_module : module_manager.net_sink_modules(module_id, module_net)) { - if (module_id == sink_module) { - contain_module_output = true; - break; - } - } - - return contain_module_input & contain_module_output; -} - -/******************************************************************** - * Add the port-to-port connection between a pb_type and its linked circuit model - * This function is mainly used to create instance of the module for a pb_type - * - * Note: this function SHOULD be called after the pb_type_module is created - * and its child module is created! - *******************************************************************/ -void add_primitive_pb_type_module_nets(ModuleManager& module_manager, - const ModuleId& pb_type_module, - const ModuleId& child_module, - const size_t& child_instance_id, - const CircuitLibrary& circuit_lib, - t_pb_type* cur_pb_type) { - for (int iport = 0; iport < cur_pb_type->num_ports; ++iport) { - t_port* pb_type_port = &(cur_pb_type->ports[iport]); - /* Must have a linked circuit model port */ - VTR_ASSERT( CircuitPortId::INVALID() != pb_type_port->circuit_model_port); - - /* Find the source port in pb_type module */ - /* Get the src module port id */ - ModulePortId src_module_port_id = module_manager.find_module_port(pb_type_module, generate_pb_type_port_name(pb_type_port)); - VTR_ASSERT(ModulePortId::INVALID() != src_module_port_id); - BasicPort src_port = module_manager.module_port(pb_type_module, src_module_port_id); - - /* Get the des module port id */ - std::string des_module_port_name = circuit_lib.port_prefix(pb_type_port->circuit_model_port); - ModulePortId des_module_port_id = module_manager.find_module_port(child_module, des_module_port_name); - VTR_ASSERT(ModulePortId::INVALID() != des_module_port_id); - BasicPort des_port = module_manager.module_port(child_module, des_module_port_id); - - /* Port size must match */ - if (src_port.get_width() != des_port.get_width()) - VTR_ASSERT(src_port.get_width() == des_port.get_width()); - - /* For each pin, generate the nets. - * For non-output ports (input ports, inout ports and clock ports), - * src_port is the source of the net - * For output ports - * src_port is the sink of the net - */ - switch (pb_type_port->type) { - case IN_PORT: - case INOUT_PORT: - for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(pb_type_module); - /* Add net source */ - module_manager.add_module_net_source(pb_type_module, net, pb_type_module, 0, src_module_port_id, src_port.pins()[pin_id]); - /* Add net sink */ - module_manager.add_module_net_sink(pb_type_module, net, child_module, child_instance_id, des_module_port_id, des_port.pins()[pin_id]); - } - break; - case OUT_PORT: - for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(pb_type_module); - /* Add net source */ - module_manager.add_module_net_sink(pb_type_module, net, pb_type_module, 0, src_module_port_id, src_port.pins()[pin_id]); - /* Add net sink */ - module_manager.add_module_net_source(pb_type_module, net, child_module, child_instance_id, des_module_port_id, des_port.pins()[pin_id]); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid port of pb_type!\n", - __FILE__, __LINE__); - exit(1); - } - } -} - -/******************************************************************** - * Add the port-to-port connection between a logic module - * and a memory module - * Create nets to wire SRAM ports between logic module and memory module - * - * The information about SRAM ports of logic module are stored in the - * mem_output_bus_ports, where element [0] denotes the SRAM port while - * element [1] denotes the SRAMb port - * - * +---------+ +--------+ - * | | regular SRAM port | | - * | Logic |-----------------------+ | Memory | - * | Module | mode-select SRAM port |->| Module | - * | |-----------------------+ | | - * +---------+ +--------+ - * - * There could be multiple SRAM ports of logic module, which are wired to - * the SRAM ports of memory module - * - * Note: this function SHOULD be called after the pb_type_module is created - * and its child module (logic_module and memory_module) is created! - * - * Note: this function only handle either SRAM or SRAMb ports. - * So, this function may be called twice to complete the wiring - *******************************************************************/ -static -void add_module_nets_between_logic_and_memory_sram_ports(ModuleManager& module_manager, - const ModuleId& parent_module, - const ModuleId& logic_module, - const size_t& logic_instance_id, - const ModuleId& memory_module, - const size_t& memory_instance_id, - const std::vector& logic_module_sram_port_ids, - const ModulePortId& mem_module_sram_port_id) { - /* Find mem_output_bus ports in logic module */ - std::vector logic_module_sram_ports; - for (const ModulePortId& logic_module_sram_port_id : logic_module_sram_port_ids) { - logic_module_sram_ports.push_back(module_manager.module_port(logic_module, logic_module_sram_port_id)); - } - - /* Create a list of virtual ports to align with the SRAM port of logic module - * Physical ports: - * - * logic_module_sram_port[0] logic_module_sram_port[1] - * - * LSB[0]------------>MSB[0] LSB------------------>MSB - * - * memory_sram_port - * LSBY---------------------------------------------->MSBY - * - * Virtual ports: - * mem_module_sram_port[0] mem_module_sram_port[1] - * LSBY--------------->MSBX MSBX+1------------------>MSBY - * - */ - BasicPort mem_module_port = module_manager.module_port(memory_module, mem_module_sram_port_id); - std::vector virtual_mem_module_ports; - - /* Create a counter for the LSB of virtual ports */ - size_t port_lsb = 0; - for (const BasicPort& logic_module_sram_port : logic_module_sram_ports) { - BasicPort virtual_port; - virtual_port.set_name(mem_module_port.get_name()); - virtual_port.set_width(port_lsb, port_lsb + logic_module_sram_port.get_width() - 1); - virtual_mem_module_ports.push_back(virtual_port); - port_lsb = virtual_port.get_msb() + 1; - } - /* port_lsb should be aligned with the MSB of memory_sram_port */ - VTR_ASSERT(port_lsb == mem_module_port.get_msb() + 1); - - /* Wire port to port */ - for (size_t port_index = 0; port_index < logic_module_sram_ports.size(); ++port_index) { - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < logic_module_sram_ports[port_index].pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(parent_module); - /* TODO: Give a name to make it clear */ - std::string net_name = module_manager.module_name(logic_module) + std::string("_") + std::to_string(logic_instance_id) + std::string("_") + logic_module_sram_ports[port_index].get_name(); - module_manager.set_net_name(parent_module, net, net_name); - /* Add net source */ - module_manager.add_module_net_source(parent_module, net, logic_module, logic_instance_id, logic_module_sram_port_ids[port_index], logic_module_sram_ports[port_index].pins()[pin_id]); - /* Add net sink */ - module_manager.add_module_net_sink(parent_module, net, memory_module, memory_instance_id, mem_module_sram_port_id, virtual_mem_module_ports[port_index].pins()[pin_id]); - } - } -} - -/******************************************************************** - * Add the port-to-port connection between a logic module - * and a memory module - * Create nets to wire SRAM ports between logic module and memory module - * - * - * +---------+ +--------+ - * | | SRAM ports | | - * | Logic |----------------------->| Memory | - * | Module | SRAMb ports | Module | - * | |----------------------->| | - * +---------+ +--------+ - * - * Note: this function SHOULD be called after the pb_type_module is created - * and its child module (logic_module and memory_module) is created! - * - *******************************************************************/ -void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_manager, - const ModuleId& parent_module, - const ModuleId& logic_module, - const size_t& logic_instance_id, - const ModuleId& memory_module, - const size_t& memory_instance_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& logic_model) { - - /* Connect SRAM port */ - /* Find SRAM ports in the circuit model for logic module */ - std::vector logic_model_sram_port_names; - /* Regular sram port goes first */ - for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) { - logic_model_sram_port_names.push_back(circuit_lib.port_prefix(regular_sram_port)); - } - /* Mode-select sram port goes first */ - for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) { - logic_model_sram_port_names.push_back(circuit_lib.port_prefix(mode_select_sram_port)); - } - /* Find the port ids in the memory */ - std::vector logic_module_sram_port_ids; - for (const std::string& logic_model_sram_port_name : logic_model_sram_port_names) { - /* Skip non-exist ports */ - if (ModulePortId::INVALID() == module_manager.find_module_port(logic_module, logic_model_sram_port_name)) { - continue; - } - logic_module_sram_port_ids.push_back(module_manager.find_module_port(logic_module, logic_model_sram_port_name)); - } - - /* Get the SRAM port name of memory model */ - /* TODO: this should be a constant expression and it should be the same for all the memory module! */ - std::string memory_model_sram_port_name = generate_configuration_chain_data_out_name(); - /* Find the corresponding ports in memory module */ - ModulePortId mem_module_sram_port_id = module_manager.find_module_port(memory_module, memory_model_sram_port_name); - - /* Do wiring only when we have sram ports */ - if ( (false == logic_module_sram_port_ids.empty()) - || (ModulePortId::INVALID() == mem_module_sram_port_id) ) { - add_module_nets_between_logic_and_memory_sram_ports(module_manager, parent_module, - logic_module, logic_instance_id, - memory_module, memory_instance_id, - logic_module_sram_port_ids, mem_module_sram_port_id); - } - - /* Connect SRAMb port */ - /* Find SRAM ports in the circuit model for logic module */ - std::vector logic_model_sramb_port_names; - /* Regular sram port goes first */ - for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) { - logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(regular_sram_port) + std::string("_inv")); - } - /* Mode-select sram port goes first */ - for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) { - logic_model_sramb_port_names.push_back(circuit_lib.port_prefix(mode_select_sram_port) + std::string("_inv")); - } - /* Find the port ids in the memory */ - std::vector logic_module_sramb_port_ids; - for (const std::string& logic_model_sramb_port_name : logic_model_sramb_port_names) { - /* Skip non-exist ports */ - if (ModulePortId::INVALID() == module_manager.find_module_port(logic_module, logic_model_sramb_port_name)) { - continue; - } - logic_module_sramb_port_ids.push_back(module_manager.find_module_port(logic_module, logic_model_sramb_port_name)); - } - - /* Get the SRAM port name of memory model */ - std::string memory_model_sramb_port_name = generate_configuration_chain_inverted_data_out_name(); - /* Find the corresponding ports in memory module */ - ModulePortId mem_module_sramb_port_id = module_manager.find_module_port(memory_module, memory_model_sramb_port_name); - - /* Do wiring only when we have sramb ports */ - if ( (false == logic_module_sramb_port_ids.empty()) - || (ModulePortId::INVALID() == mem_module_sramb_port_id) ) { - add_module_nets_between_logic_and_memory_sram_ports(module_manager, parent_module, - logic_module, logic_instance_id, - memory_module, memory_instance_id, - logic_module_sramb_port_ids, mem_module_sramb_port_id); - } -} - -/******************************************************************** - * Connect all the memory modules under the parent module in a chain - * - * +--------+ +--------+ +--------+ - * ccff_head --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail - * | Module | | Module | | Module | - * | [0] | | [1] | | [N-1] | - * +--------+ +--------+ +--------+ - * For the 1st memory module: - * net source is the configuration chain head of the primitive module - * net sink is the configuration chain head of the next memory module - * - * For the rest of memory modules: - * net source is the configuration chain tail of the previous memory module - * net sink is the configuration chain head of the next memory module - *********************************************************************/ -void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager, - const ModuleId& parent_module, - const e_sram_orgz& sram_orgz_type) { - for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) { - ModuleId net_src_module_id; - size_t net_src_instance_id; - ModulePortId net_src_port_id; - - ModuleId net_sink_module_id; - size_t net_sink_instance_id; - ModulePortId net_sink_port_id; - - if (0 == mem_index) { - /* Find the port name of configuration chain head */ - std::string src_port_name = generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_INPUT); - net_src_module_id = parent_module; - net_src_instance_id = 0; - net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); - - /* Find the port name of next memory module */ - std::string sink_port_name = generate_configuration_chain_head_name(); - net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; - net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; - net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); - } else { - /* Find the port name of previous memory module */ - std::string src_port_name = generate_configuration_chain_tail_name(); - net_src_module_id = module_manager.configurable_children(parent_module)[mem_index - 1]; - net_src_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index - 1]; - net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); - - /* Find the port name of next memory module */ - std::string sink_port_name = generate_configuration_chain_head_name(); - net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; - net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; - net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); - } - - /* Get the pin id for source port */ - BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); - /* Get the pin id for sink port */ - BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); - /* Port sizes of source and sink should match */ - VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { - /* Create a net and add source and sink to it */ - ModuleNetId net = module_manager.create_module_net(parent_module); - /* Add net source */ - module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); - /* Add net sink */ - module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); - } - } - - /* For the last memory module: - * net source is the configuration chain tail of the previous memory module - * net sink is the configuration chain tail of the primitive module - */ - /* Find the port name of previous memory module */ - std::string src_port_name = generate_configuration_chain_tail_name(); - ModuleId net_src_module_id = module_manager.configurable_children(parent_module).back(); - size_t net_src_instance_id = module_manager.configurable_child_instances(parent_module).back(); - ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); - - /* Find the port name of next memory module */ - std::string sink_port_name = generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_OUTPUT); - ModuleId net_sink_module_id = parent_module; - size_t net_sink_instance_id = 0; - ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); - - /* Get the pin id for source port */ - BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); - /* Get the pin id for sink port */ - BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); - /* Port sizes of source and sink should match */ - VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { - /* Create a net and add source and sink to it */ - ModuleNetId net = module_manager.create_module_net(parent_module); - /* Add net source */ - module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); - /* Add net sink */ - module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); - } -} - -/********************************************************************* - * Add the port-to-port connection between all the memory modules - * and their parent module - * - * Create nets to wire the control signals of memory module to - * the configuration ports of primitive module - * - * Configuration Chain - * ------------------- - * - * config_bus (head) config_bus (tail) - * | ^ - * primitive | | - * +---------------------------------------------+ - * | | | | - * | v | | - * | +-------------------------------------+ | - * | | CMOS-based Memory Modules | | - * | +-------------------------------------+ | - * | | | | - * | v v | - * | sram_out sram_outb | - * | | - * +---------------------------------------------+ - * - * Memory bank - * ----------- - * - * config_bus (BL) config_bus (WL) - * | | - * primitive | | - * +---------------------------------------------+ - * | | | | - * | v v | - * | +-------------------------------------+ | - * | | CMOS-based Memory Modules | | - * | +-------------------------------------+ | - * | | | | - * | v v | - * | sram_out sram_outb | - * | | - * +---------------------------------------------+ - * - **********************************************************************/ -static -void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, - const ModuleId& parent_module, - const e_sram_orgz& sram_orgz_type) { - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* Nothing to do */ - break; - case SPICE_SRAM_SCAN_CHAIN: { - add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, sram_orgz_type); - break; - } - case SPICE_SRAM_MEMORY_BANK: - /* TODO: */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/********************************************************************* - * TODO: - * Add the port-to-port connection between a logic module - * and a memory module inside a primitive module - * - * Memory bank - * ----------- - * config_bus (BL) config_bus (WL) shared_config_bugs(shared_BL/WLs) - * | | | | - * primitive | | | | - * +------------------------------------------------------------+ - * | | | | | | - * | v v v v | - * | +----------------------------------------------------+ | - * | | ReRAM-based Memory Module | | - * | +----------------------------------------------------+ | - * | | | | - * | v v | - * | mem_out mem_outb | - * | | - * +------------------------------------------------------------+ - * - **********************************************************************/ - -/******************************************************************** - * TODO: - * Add the port-to-port connection between a memory module - * and the configuration bus of a primitive module - * - * Create nets to wire the control signals of memory module to - * the configuration ports of primitive module - * - * Primitive module - * +----------------------------+ - * | +--------+ | - * config | | | | - * ports --->|--------------->| Memory | | - * | | Module | | - * | | | | - * | +--------+ | - * +----------------------------+ - * The detailed config ports really depend on the type - * of SRAM organization. - * - * The config_bus in the argument is the reserved address of configuration - * bus in the parent_module for this memory module - * - * The configuration bus connection will depend not only - * the design technology of the memory cells but also the - * configuration styles of FPGA fabric. - * Here we will branch on the design technology - * - * Note: this function SHOULD be called after the pb_type_module is created - * and its child module (logic_module and memory_module) is created! - *******************************************************************/ -void add_module_nets_memory_config_bus(ModuleManager& module_manager, - const ModuleId& parent_module, - const e_sram_orgz& sram_orgz_type, - const e_spice_model_design_tech& mem_tech) { - switch (mem_tech) { - case SPICE_MODEL_DESIGN_CMOS: - add_module_nets_cmos_memory_config_bus(module_manager, parent_module, - sram_orgz_type); - break; - case SPICE_MODEL_DESIGN_RRAM: - /* TODO: */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of memory design technology !\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * Find the size of shared(reserved) configuration ports for module - *******************************************************************/ -size_t find_module_num_shared_config_bits(const ModuleManager& module_manager, - const ModuleId& module_id) { - std::vector shared_config_port_names; - shared_config_port_names.push_back(generate_reserved_sram_port_name(SPICE_MODEL_PORT_BLB)); - shared_config_port_names.push_back(generate_reserved_sram_port_name(SPICE_MODEL_PORT_WL)); - size_t num_shared_config_bits = 0; /* By default it has zero configuration bits*/ - - /* Try to find these ports in the module manager */ - for (const std::string& shared_config_port_name : shared_config_port_names) { - ModulePortId module_port_id = module_manager.find_module_port(module_id, shared_config_port_name); - /* If the port does not exist, go to the next */ - if (false == module_manager.valid_module_port_id(module_id, module_port_id)) { - continue; - } - /* The port exist, find the port size and update the num_config_bits if the size is larger */ - BasicPort module_port = module_manager.module_port(module_id, module_port_id); - num_shared_config_bits = std::max((int)num_shared_config_bits, (int)module_port.get_width()); - } - - return num_shared_config_bits; -} - -/******************************************************************** - * Find the size of configuration ports for module - *******************************************************************/ -size_t find_module_num_config_bits(const ModuleManager& module_manager, - const ModuleId& module_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz& sram_orgz_type) { - std::vector config_port_names = generate_sram_port_names(circuit_lib, sram_model, sram_orgz_type); - size_t num_config_bits = 0; /* By default it has zero configuration bits*/ - - /* Try to find these ports in the module manager */ - for (const std::string& config_port_name : config_port_names) { - ModulePortId module_port_id = module_manager.find_module_port(module_id, config_port_name); - /* If the port does not exist, go to the next */ - if (false == module_manager.valid_module_port_id(module_id, module_port_id)) { - continue; - } - /* The port exist, find the port size and update the num_config_bits if the size is larger */ - BasicPort module_port = module_manager.module_port(module_id, module_port_id); - num_config_bits = std::max((int)num_config_bits, (int)module_port.get_width()); - } - - return num_config_bits; -} - -/******************************************************************** - * Add General purpose I/O ports to the module: - * In this function, the following tasks are done: - * 1. find all the I/O ports from the child modules and build a list of it, - * 2. Merge all the I/O ports with the same name - * 3. add the ports to the pb_module - * 4. add module nets to connect to the GPIO ports of each sub module - * - * Module - * ----------------------+ - * | - * child[0] | - * -----------+ | - * |----------+----> outputA[0] - * -----------+ | - * | - * child[1] | - * -----------+ | - * |----------+----> outputA[1] - * -----------+ | - - * - * Note: This function should be call ONLY after all the sub modules (instances) - * have been added to the pb_module! - * Otherwise, some GPIO ports of the sub modules may be missed! - *******************************************************************/ -static -void add_module_io_ports_from_child_modules(ModuleManager& module_manager, - const ModuleId& module_id, - const ModuleManager::e_module_port_type& module_port_type) { - std::vector gpio_ports_to_add; - - /* Iterate over the child modules */ - for (const ModuleId& child : module_manager.child_modules(module_id)) { - /* Iterate over the child instances */ - for (size_t i = 0; i < module_manager.num_instance(module_id, child); ++i) { - /* Find all the global ports, whose port type is special */ - for (BasicPort gpio_port : module_manager.module_ports_by_type(child, module_port_type)) { - /* If this port is not mergeable, we update the list */ - bool is_mergeable = false; - for (BasicPort& gpio_port_to_add : gpio_ports_to_add) { - if (false == gpio_port_to_add.mergeable(gpio_port)) { - continue; - } - is_mergeable = true; - /* For mergeable ports, we combine the port - * Note: do NOT use the merge() method! - * the GPIO ports should be accumulated by the sizes of ports - * not by the LSB/MSB range !!! - */ - gpio_port_to_add.combine(gpio_port); - break; - } - if (false == is_mergeable) { - /* Reach here, this is an unique gpio port, update the list */ - gpio_ports_to_add.push_back(gpio_port); - } - } - } - } - - /* Record the port id for each type of GPIO port */ - std::vector gpio_port_ids; - /* Add the gpio ports for the module */ - for (const BasicPort& gpio_port_to_add : gpio_ports_to_add) { - ModulePortId port_id = module_manager.add_port(module_id, gpio_port_to_add, module_port_type); - gpio_port_ids.push_back(port_id); - } - - /* Set up a counter for each type of GPIO port */ - std::vector gpio_port_lsb(gpio_ports_to_add.size(), 0); - /* Add module nets to connect the GPIOs of the module to the GPIOs of the sub module */ - for (const ModuleId& child : module_manager.child_modules(module_id)) { - /* Iterate over the child instances */ - for (const size_t& child_instance : module_manager.child_module_instances(module_id, child)) { - /* Find all the global ports, whose port type is special */ - for (ModulePortId child_gpio_port_id : module_manager.module_port_ids_by_type(child, module_port_type)) { - BasicPort child_gpio_port = module_manager.module_port(child, child_gpio_port_id); - /* Find the port with the same name! */ - for (size_t iport = 0; iport < gpio_ports_to_add.size(); ++iport) { - if (false == gpio_ports_to_add[iport].mergeable(child_gpio_port)) { - continue; - } - /* For each pin of the child port, create a net and do wiring */ - for (const size_t& pin_id : child_gpio_port.pins()) { - /* Reach here, it means this is the port we want, create a net and configure its source and sink */ - ModuleNetId net = module_manager.create_module_net(module_id); - /* - For GPIO and GPIN ports - * the source of the net is the current module - * the sink of the net is the child module - * - For GPOUT ports - * the source of the net is the child module - * the sink of the net is the current module - */ - if ( (ModuleManager::MODULE_GPIO_PORT == module_port_type) - || (ModuleManager::MODULE_GPIN_PORT == module_port_type) ) { - module_manager.add_module_net_source(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); - module_manager.add_module_net_sink(module_id, net, child, child_instance, child_gpio_port_id, pin_id); - } else { - VTR_ASSERT(ModuleManager::MODULE_GPOUT_PORT == module_port_type); - module_manager.add_module_net_sink(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); - module_manager.add_module_net_source(module_id, net, child, child_instance, child_gpio_port_id, pin_id); - } - /* Update the LSB counter */ - gpio_port_lsb[iport]++; - } - /* We finish for this child gpio port */ - break; - } - } - } - } - - /* Check: all the lsb should now match the size of each GPIO port */ - for (size_t iport = 0; iport < gpio_ports_to_add.size(); ++iport) { - if (gpio_ports_to_add[iport].get_width() != gpio_port_lsb[iport]) - VTR_ASSERT(gpio_ports_to_add[iport].get_width() == gpio_port_lsb[iport]); - } -} - -/******************************************************************** - * Add GPIO ports to the module: - * In this function, the following tasks are done: - * 1. find all the GPIO ports from the child modules and build a list of it, - * 2. Merge all the GPIO ports with the same name - * 3. add the ports to the pb_module - * 4. add module nets to connect to the GPIO ports of each sub module - * - * Note: This function should be call ONLY after all the sub modules (instances) - * have been added to the pb_module! - * Otherwise, some GPIO ports of the sub modules may be missed! - *******************************************************************/ -void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, - const ModuleId& module_id) { - add_module_io_ports_from_child_modules(module_manager, module_id, ModuleManager::MODULE_GPIO_PORT); - - add_module_io_ports_from_child_modules(module_manager, module_id, ModuleManager::MODULE_GPIN_PORT); - - add_module_io_ports_from_child_modules(module_manager, module_id, ModuleManager::MODULE_GPOUT_PORT); -} - -/******************************************************************** - * Add global ports to the module: - * In this function, the following tasks are done: - * 1. find all the global ports from the child modules and build a list of it, - * 2. add the ports to the pb_module - * 3. add the module nets to connect the pb_module global ports to those of child modules - * - * Note: This function should be call ONLY after all the sub modules (instances) - * have been added to the pb_module! - * Otherwise, some global ports of the sub modules may be missed! - *******************************************************************/ -void add_module_global_ports_from_child_modules(ModuleManager& module_manager, - const ModuleId& module_id) { - std::vector global_ports_to_add; - - /* Iterate over the child modules */ - for (const ModuleId& child : module_manager.child_modules(module_id)) { - /* Iterate over the child instances */ - for (size_t i = 0; i < module_manager.num_instance(module_id, child); ++i) { - /* Find all the global ports, whose port type is special */ - for (BasicPort global_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_GLOBAL_PORT)) { - /* Search in the global port list to be added, if this is unique, we update the list */ - std::vector::iterator it = std::find(global_ports_to_add.begin(), global_ports_to_add.end(), global_port); - if (it != global_ports_to_add.end()) { - continue; - } - /* Reach here, this is an unique global port, update the list */ - global_ports_to_add.push_back(global_port); - } - } - } - - /* Record the port id for each type of global port */ - std::vector global_port_ids; - /* Add the global ports for the module */ - for (const BasicPort& global_port_to_add : global_ports_to_add) { - ModulePortId port_id = module_manager.add_port(module_id, global_port_to_add, ModuleManager::MODULE_GLOBAL_PORT); - global_port_ids.push_back(port_id); - } - - /* Add module nets to connect the global ports of the module to the global ports of the sub module */ - /* Iterate over the child modules */ - for (const ModuleId& child : module_manager.child_modules(module_id)) { - /* Iterate over the child instances */ - for (const size_t& child_instance : module_manager.child_module_instances(module_id, child)) { - /* Find all the global ports, whose port type is special */ - for (ModulePortId child_global_port_id : module_manager.module_port_ids_by_type(child, ModuleManager::MODULE_GLOBAL_PORT)) { - BasicPort child_global_port = module_manager.module_port(child, child_global_port_id); - /* Search in the global port list to be added, find the port id */ - std::vector::iterator it = std::find(global_ports_to_add.begin(), global_ports_to_add.end(), child_global_port); - VTR_ASSERT(it != global_ports_to_add.end()); - ModulePortId module_global_port_id = global_port_ids[it - global_ports_to_add.begin()]; - BasicPort module_global_port = module_manager.module_port(module_id, module_global_port_id); - /* The global ports should match in size */ - VTR_ASSERT(module_global_port.get_width() == child_global_port.get_width()); - /* For each pin of the child port, create a net and do wiring */ - for (size_t pin_id = 0; pin_id < child_global_port.pins().size(); ++pin_id) { - /* Reach here, it means this is the port we want, create a net and configure its source and sink */ - ModuleNetId net = module_manager.create_module_net(module_id); - module_manager.add_module_net_source(module_id, net, module_id, 0, module_global_port_id, module_global_port.pins()[pin_id]); - module_manager.add_module_net_sink(module_id, net, child, child_instance, child_global_port_id, child_global_port.pins()[pin_id]); - /* We finish for this child gpio port */ - } - } - } - } -} - -/******************************************************************** - * Find the number of shared configuration bits for a module - * by selected the maximum number of shared configuration bits of child modules - * - * Note: This function should be call ONLY after all the sub modules (instances) - * have been added to the pb_module! - * Otherwise, some global ports of the sub modules may be missed! - *******************************************************************/ -size_t find_module_num_shared_config_bits_from_child_modules(ModuleManager& module_manager, - const ModuleId& module_id) { - size_t num_shared_config_bits = 0; - - /* Iterate over the child modules */ - for (const ModuleId& child : module_manager.child_modules(module_id)) { - num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_module_num_shared_config_bits(module_manager, child)); - } - - return num_shared_config_bits; -} - -/******************************************************************** - * Find the number of configuration bits for a module - * by summing up the number of configuration bits of child modules - * - * Note: This function should be call ONLY after all the sub modules (instances) - * have been added to the pb_module! - * Otherwise, some global ports of the sub modules may be missed! - *******************************************************************/ -size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_manager, - const ModuleId& module_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz& sram_orgz_type) { - size_t num_config_bits = 0; - - /* Iterate over the child modules */ - for (const ModuleId& child : module_manager.child_modules(module_id)) { - num_config_bits += find_module_num_config_bits(module_manager, child, circuit_lib, sram_model, sram_orgz_type); - } - - return num_config_bits; -} - - -/******************************************************************** - * TODO: - * Add the port-to-port connection between a logic module - * and a memory module inside a primitive module - * - * Create nets to wire the formal verification ports of - * primitive module to SRAM ports of logic module - * - * Primitive module - * - * formal_port_sram - * +-----------------------------------------------+ - * | ^ | - * | +---------+ | +--------+ | - * | | | SRAM | | | | - * | | Logic |--------+--->| Memory | | - * | | Module | SRAMb | Module | | - * | | |--------+--->| | | - * | +---------+ | +--------+ | - * | v | - * +-----------------------------------------------+ - * formal_port_sramb - * - *******************************************************************/ - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h deleted file mode 100644 index a44abbfc4..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h +++ /dev/null @@ -1,108 +0,0 @@ -/****************************************************************************** - * This files includes declarations for most utilized functions - * for data structures for module management. - ******************************************************************************/ - -#ifndef MODULE_MANAGER_UTILS_H -#define MODULE_MANAGER_UTILS_H - -/* Include other header files which are dependency on the function declared below */ -#include -#include "device_port.h" -#include "spice_types.h" -#include "vpr_types.h" -#include "circuit_library.h" -#include "module_manager.h" - -ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, - const std::string& module_name); - -ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); - -void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager, - const ModuleId& module_id, - const size_t& port_size); - -void add_formal_verification_sram_ports_to_module_manager(ModuleManager& module_manager, - const ModuleId& module_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const std::string& preproc_flag, - const size_t& port_size); - -void add_sram_ports_to_module_manager(ModuleManager& module_manager, - const ModuleId& module_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz sram_orgz_type, - const size_t& num_config_bits); - -void add_primitive_pb_type_ports_to_module_manager(ModuleManager& module_manager, - const ModuleId& module_id, - t_pb_type* cur_pb_type); - -void add_pb_type_ports_to_module_manager(ModuleManager& module_manager, - const ModuleId& module_id, - t_pb_type* cur_pb_type); - -bool module_net_is_local_wire(const ModuleManager& module_manager, - const ModuleId& module_id, const ModuleNetId& module_net); - -bool module_net_include_output_short_connection(const ModuleManager& module_manager, - const ModuleId& module_id, const ModuleNetId& module_net); - -bool module_net_include_local_short_connection(const ModuleManager& module_manager, - const ModuleId& module_id, const ModuleNetId& module_net); - -void add_primitive_pb_type_module_nets(ModuleManager& module_manager, - const ModuleId& pb_type_module, - const ModuleId& child_module, - const size_t& child_instance_id, - const CircuitLibrary& circuit_lib, - t_pb_type* cur_pb_type); - -void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_manager, - const ModuleId& parent_module, - const ModuleId& logic_module, - const size_t& logic_instance_id, - const ModuleId& memory_module, - const size_t& memory_instance_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& logic_model); - -void add_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager, - const ModuleId& parent_module, - const e_sram_orgz& sram_orgz_type); - -void add_module_nets_memory_config_bus(ModuleManager& module_manager, - const ModuleId& parent_module, - const e_sram_orgz& sram_orgz_type, - const e_spice_model_design_tech& mem_tech); - -size_t find_module_num_shared_config_bits(const ModuleManager& module_manager, - const ModuleId& module_id); - -size_t find_module_num_config_bits(const ModuleManager& module_manager, - const ModuleId& module_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz& sram_orgz_type); - -void add_module_global_ports_from_child_modules(ModuleManager& module_manager, - const ModuleId& module_id); - -void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, - const ModuleId& module_id); - -size_t find_module_num_shared_config_bits_from_child_modules(ModuleManager& module_manager, - const ModuleId& module_id); - -size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_manager, - const ModuleId& module_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz& sram_orgz_type); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.cpp deleted file mode 100644 index 3d9d212ca..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.cpp +++ /dev/null @@ -1,184 +0,0 @@ -/****************************************************************************** - * This files includes memeber functions for data structure NetlistManager - ******************************************************************************/ -#include - -#include "vtr_assert.h" -#include "netlist_manager.h" - -/****************************************************************************** - * Public aggregators - ******************************************************************************/ -/* Find all the netlists */ -NetlistManager::netlist_range NetlistManager::netlists() const { - return vtr::make_range(netlist_ids_.begin(), netlist_ids_.end()); -} - -/* Find all the modules that are included in a netlist */ -std::vector NetlistManager::netlist_modules(const NetlistId& netlist) const { - VTR_ASSERT(true == valid_netlist_id(netlist)); - return included_module_ids_[netlist]; -} - - -/****************************************************************************** - * Public accessors - ******************************************************************************/ -/* Find the name of a netlist */ -std::string NetlistManager::netlist_name(const NetlistId& netlist) const { - VTR_ASSERT(true == valid_netlist_id(netlist)); - return netlist_names_[netlist]; -} - -/* Find a netlist by its name */ -NetlistId NetlistManager::find_netlist(const std::string& netlist_name) const { - if (name_id_map_.find(netlist_name) != name_id_map_.end()) { - /* Found, return the id */ - return name_id_map_.at(netlist_name); - } - /* Not found, return an invalid id */ - return NetlistId::INVALID(); -} - -/* Find if a module belongs to a netlist */ -bool NetlistManager::is_module_in_netlist(const NetlistId& netlist, const ModuleId& module) const { - VTR_ASSERT(true == valid_netlist_id(netlist)); - - for (const ModuleId& included_module : included_module_ids_[netlist]) { - /* Already in the netlist, return true */ - if (module == included_module) { - return true; - } - } - - /* Not in the netlist, return false */ - return false; -} - -/* Find the netlist that a module belongs to */ -NetlistId NetlistManager::find_module_netlist(const ModuleId& module) const { - /* Find if the module has been added to a netlist. If used, return false! */ - /* Not found, return an invalid value */ - if ( module_netlist_map_.end() - != module_netlist_map_.find(module)) { - return NetlistId::INVALID(); - } - return module_netlist_map_.at(module); -} - - -/* Find all the preprocessing flags that are included in a netlist */ -std::vector NetlistManager::netlist_preprocessing_flags(const NetlistId& netlist) const { - VTR_ASSERT(true == valid_netlist_id(netlist)); - - std::vector flags; - - for (const PreprocessingFlagId& flag_id : included_preprocessing_flag_ids_[netlist]) { - VTR_ASSERT(true == valid_preprocessing_flag_id(flag_id)); - flags.push_back(preprocessing_flag_names_[flag_id]); - } - - return flags; -} - -/****************************************************************************** - * Public mutators - ******************************************************************************/ -/* Add a netlist to the library */ -NetlistId NetlistManager::add_netlist(const std::string& name) { - /* Find if the name has been used. If used, return an invalid Id! */ - std::map::iterator it = name_id_map_.find(name); - if (it != name_id_map_.end()) { - return NetlistId::INVALID(); - } - - /* Create a new id */ - NetlistId netlist = NetlistId(netlist_ids_.size()); - netlist_ids_.push_back(netlist); - - /* Allocate related attributes */ - netlist_names_.push_back(name); - included_module_ids_.emplace_back(); - included_preprocessing_flag_ids_.emplace_back(); - - /* Register in the name-to-id map */ - name_id_map_[name] = netlist; - - return netlist; -} - -/* Add a module to a netlist in the library */ -bool NetlistManager::add_netlist_module(const NetlistId& netlist, const ModuleId& module) { - VTR_ASSERT(true == valid_netlist_id(netlist)); - - /* Find if the module already in the netlist */ - std::vector::iterator module_it = std::find(included_module_ids_[netlist].begin(), included_module_ids_[netlist].end(), module); - if (module_it != included_module_ids_[netlist].end()) { - /* Already in the netlist, nothing to do */ - return true; - } - /* Try to register it in module-to-netlist map */ - /* Find if the module has been added to a netlist. If used, return false! */ - std::map::iterator map_it = module_netlist_map_.find(module); - if (map_it != module_netlist_map_.end()) { - return false; - } - - /* Does not exist! Should add it to the list */ - included_module_ids_[netlist].push_back(module); - /* Register it in module-to-netlist map */ - module_netlist_map_[module] = netlist; - return true; -} - -/* Add a pre-processing flag to a netlist */ -void NetlistManager::add_netlist_preprocessing_flag(const NetlistId& netlist, const std::string& preprocessing_flag) { - VTR_ASSERT(true == valid_netlist_id(netlist)); - - PreprocessingFlagId flag = PreprocessingFlagId(preprocessing_flag_ids_.size()); - - /* Find if the module already in the netlist */ - for (const PreprocessingFlagId& id : preprocessing_flag_ids_) { - if (0 != preprocessing_flag.compare(preprocessing_flag_names_[id])) { - continue; - } - /* Already in the list of pre-processing flags, push it ot the */ - flag = id; - break; - } - - /* Update the list if we need */ - if (flag == PreprocessingFlagId(preprocessing_flag_ids_.size())) { - preprocessing_flag_ids_.push_back(flag); - preprocessing_flag_names_.push_back(preprocessing_flag); - } - - /* Check if the flag is already in the netlist */ - std::vector::iterator it = std::find(included_preprocessing_flag_ids_[netlist].begin(), included_preprocessing_flag_ids_[netlist].end(), flag); - if (it == included_preprocessing_flag_ids_[netlist].end()) { - /* Not in the list, we add it */ - included_preprocessing_flag_ids_[netlist].push_back(flag); - } -} - -/****************************************************************************** - * Public validators/invalidators - ******************************************************************************/ -bool NetlistManager::valid_netlist_id(const NetlistId& netlist) const { - return (size_t(netlist) < netlist_ids_.size()) && (netlist == netlist_ids_[netlist]); -} - -/****************************************************************************** - * Private validators/invalidators - ******************************************************************************/ -bool NetlistManager::valid_preprocessing_flag_id(const PreprocessingFlagId& flag) const { - return (size_t(flag) < preprocessing_flag_ids_.size()) && (flag == preprocessing_flag_ids_[flag]); -} - -void NetlistManager::invalidate_name2id_map() { - name_id_map_.clear(); -} - -void NetlistManager::invalidate_module2netlist_map() { - module_netlist_map_.clear(); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.h deleted file mode 100644 index 2e0b4f2c0..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager.h +++ /dev/null @@ -1,86 +0,0 @@ -/****************************************************************************** - * This files includes data structures for netlist management. - * It keeps a list of netlists that have been created - * Each netlist includes a list of ids of modules that are stored in ModuleManager - * - * When we want to dump out a netlist in Verilog/SPICE format, - * the netlist manager can generate the dependency on other netlists - * This can help us tracking the dependency and generate `include` files easily - * - * Cross-reference: - * - * +---------+ +---------+ - * | | ModuleId | | - * | Netlist |-------------->| Module | - * | Manager | | Manager | - * | | | | - * +---------+ +---------+ - * - ******************************************************************************/ -#ifndef NETLIST_MANAGER_H -#define NETLIST_MANAGER_H - -#include -#include -#include -#include "vtr_vector.h" -#include "netlist_manager_fwd.h" -#include "module_manager.h" - -class NetlistManager { - public: /* Types and ranges */ - typedef vtr::vector::const_iterator netlist_iterator; - - typedef vtr::Range netlist_range; - - public: /* Public aggregators */ - /* Find all the netlists */ - netlist_range netlists() const; - /* Find all the modules that are included in a netlist */ - std::vector netlist_modules(const NetlistId& netlist) const; - /* Find all the preprocessing flags that are included in a netlist */ - std::vector netlist_preprocessing_flags(const NetlistId& netlist) const; - - public: /* Public accessors */ - /* Find the name of a netlist */ - std::string netlist_name(const NetlistId& netlist) const; - /* Find a netlist by its name */ - NetlistId find_netlist(const std::string& netlist_name) const; - /* Find if a module belongs to a netlist */ - bool is_module_in_netlist(const NetlistId& netlist, const ModuleId& module) const; - /* Find the netlist that a module belongs to */ - NetlistId find_module_netlist(const ModuleId& module) const; - - public: /* Public mutators */ - /* Add a netlist to the library */ - NetlistId add_netlist(const std::string& name); - /* Add a module to a netlist in the library */ - bool add_netlist_module(const NetlistId& netlist, const ModuleId& module); - /* Add a pre-processing flag to a netlist */ - void add_netlist_preprocessing_flag(const NetlistId& netlist, const std::string& preprocessing_flag); - - public: /* Public validators/invalidators */ - bool valid_netlist_id(const NetlistId& netlist) const; - - private: /* Private validators/invalidators */ - bool valid_preprocessing_flag_id(const PreprocessingFlagId& flag) const; - void invalidate_name2id_map(); - void invalidate_module2netlist_map(); - - private: /* Internal data */ - vtr::vector netlist_ids_; - vtr::vector netlist_names_; - vtr::vector> included_module_ids_; - vtr::vector> included_preprocessing_flag_ids_; - - vtr::vector preprocessing_flag_ids_; - vtr::vector preprocessing_flag_names_; - - /* fast look-up for netlist */ - std::map name_id_map_; - /* fast look-up for modules in netlists */ - std::map module_netlist_map_; -}; - -#endif - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager_fwd.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager_fwd.h deleted file mode 100644 index bdf58f58b..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/netlist_manager_fwd.h +++ /dev/null @@ -1,20 +0,0 @@ -/************************************************** - * This file includes only declarations for - * the data structures for netlist managers - * Please refer to netlist_manager.h for more details - *************************************************/ -#ifndef NETLIST_MANAGER_FWD_H -#define NETLIST_MANAGER_FWD_H - -#include "vtr_strong_id.h" - -/* Strong Ids for ModuleManager */ -struct netlist_id_tag; -struct preprocessing_flag_id_tag; - -typedef vtr::StrongId NetlistId; -typedef vtr::StrongId PreprocessingFlagId; - -class NetlistManager; - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/quicksort.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/quicksort.c deleted file mode 100644 index 629363399..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/quicksort.c +++ /dev/null @@ -1,165 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "quicksort.h" - -void my_free(void* ptr); - -/* Subroutines */ -/* Swap two elements of sort_index */ -static -void swap_int(int* int_a, int* int_b) { - int temp = (*int_a); - - (*int_a) = (*int_b); - (*int_b) = temp; - - return; -} - -static -void swap_float(float* int_a, float* int_b) { - float temp = (*int_a); - - (*int_a) = (*int_b); - (*int_b) = temp; - - return; -} - -/* Partition for quicksort - * Given a array(sort_value) , and the index (sort_index) - * Create two arrays, A and B, whose length is start_index and len-start_index, - * Move all the elements that are less than sort_value[start_index] to arrayA [0:start_index] - * Move all the elements that are larger than sort_value[start_index] to arrayB [0:len-start_index] - */ -static -int partition(int len, float* sort_value, int pivot_index) { - int i; - int small_len = 0; - float pivot_val = sort_value[pivot_index]; - - /* Move the pivot to the last position */ - swap_float(&sort_value[pivot_index], &sort_value[len - 1]); - - /* Move all the elements smaller than sort_value[start_index] to the first partition */ - for (i = 0; i < len-1; i++) { - if ((sort_value[i] < pivot_val) - ||(sort_value[i] == pivot_val)) { - swap_float(&sort_value[i], &sort_value[small_len]); - small_len++; - } - } - /* Move the pivot to the critical position */ - swap_float(&sort_value[small_len], &sort_value[len - 1]); - - return small_len; -} - -/* Partition according to the sort_index, - * In this funciton sort_value is not touched. - */ -static -int partition_index(int len, int* sort_index, - float* sort_value, int pivot_index) { - int i; - int small_len = 0; - float pivot_val = sort_value[sort_index[pivot_index]]; - - /* Move the pivot to the last position */ - swap_int(&sort_index[pivot_index], &sort_index[len - 1]); - - /* Move all the elements smaller than sort_value[start_index] to the first partition */ - for (i = 0; i < len-1; i++) { - if ((sort_value[sort_index[i]] < pivot_val) - ||(sort_value[sort_index[i]] == pivot_val)) { - swap_int(&sort_index[i], &sort_index[small_len]); - small_len++; - } - } - /* Move the pivot to the critical position */ - swap_int(&sort_index[small_len], &sort_index[len - 1]); - - return small_len; -} - -/* Top functions for quicksort */ -/* Sort float numbers by index, sort_value is not changed. - */ -void quicksort_float(int len, - float* sort_value) { - int small_len = 0; - //int pivot_val = 0; - //int pivot_index = 0; - - if ((0 == len)||(1 == len)) { - return; - } - - /* get partition */ - small_len = partition(len, sort_value, 0); - /* Check */ - //assert(pivot_val == sort_value[small_len]); - //assert(pivot_index == sort_index[small_len]); - /* Recursive */ - quicksort_float(small_len, sort_value); - quicksort_float(len - small_len - 1, sort_value+small_len + 1); - - return; -} - -/* Sort float numbers by index, sort_value is not changed. - */ -void do_quicksort_float_index(int len, - int* sort_index, - float* sort_value) { - int small_len = 0; - //int pivot_val = 0; - //int pivot_index = 0; - - if ((0 == len)||(1 == len)) { - return; - } - - /* get partition */ - small_len = partition_index(len, sort_index, sort_value, 0); - /* Check */ - //assert(pivot_val == sort_value[small_len]); - //assert(pivot_index == sort_index[small_len]); - /* Recursive */ - do_quicksort_float_index(small_len, sort_index, sort_value); - do_quicksort_float_index(len - small_len - 1, sort_index + small_len + 1, sort_value); - - return; -} - -/* One of the top functions: sort_index should be meet the specfication */ -void quicksort_float_index(int len, - int* sort_index, - float* sort_value) { - int i; - - /* Check the sort index */ - for (i = 0; i < len; i++) { - assert(i == sort_index[i]); - } - - do_quicksort_float_index(len, sort_index, sort_value); - - return; -} - - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/quicksort.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/quicksort.h deleted file mode 100644 index fc1929d67..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/quicksort.h +++ /dev/null @@ -1,11 +0,0 @@ - -/* QuickSort functions */ -void quicksort_float_index(int len, int* sort_index, - float* sort_value); - -void quicksort_float(int len, - float* sort_value); - -void do_quicksort_float_index(int len, - int* sort_index, - float* sort_value); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp deleted file mode 100644 index e9ca6f818..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ /dev/null @@ -1,3158 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: rr_blocks.cpp - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/06/26 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file contains member function for the data structures defined - * in rr_block.h - ***********************************************************************/ - -#include -#include -#include -#include - -#include "rr_blocks_naming.h" - -#include "rr_blocks.h" - -#include "rr_graph_builder_utils.h" - - -/* Member Functions of Class RRChan */ -/* Constructors */ - -/* Copy Constructor */ -RRChan::RRChan(const RRChan& rr_chan) { - this->set(rr_chan); - return; -} - -/* default constructor */ -RRChan::RRChan() { - type_ = NUM_RR_TYPES; - nodes_.resize(0); - node_segments_.resize(0); -} - -/* Accessors */ -t_rr_type RRChan::get_type() const { - return type_; -} - -/* get the number of tracks in this channel */ -size_t RRChan::get_chan_width() const { - return nodes_.size(); -} - -/* get the track_id of a node */ -int RRChan::get_node_track_id(t_rr_node* node) const { - /* if the given node is NULL, we return an invalid id */ - if (NULL == node) { - return -1; /* FIXME: use a strong id!!! */ - } - /* check each member and return if we find a match in content */ - for (size_t inode = 0; inode < nodes_.size(); ++inode) { - if (node == nodes_[inode]) { - return inode; - } - } - return -1; -} - -/* get the rr_node with the track_id */ -t_rr_node* RRChan::get_node(size_t track_num) const { - if ( false == valid_node_id(track_num) ) { - return NULL; - } - return nodes_[track_num]; -} - -/* get the segment id of a node */ -int RRChan::get_node_segment(t_rr_node* node) const { - int node_id = get_node_track_id(node); - if ( false == valid_node_id(node_id)) { - return -1; - } - return get_node_segment(node_id); -} - -/* get the segment id of a node */ -int RRChan::get_node_segment(size_t track_num) const { - if ( false == valid_node_id(track_num)) { - return -1; - } - return node_segments_[track_num]; -} - -/* evaluate if two RRChan is mirror to each other */ -bool RRChan::is_mirror(const RRChan& cand) const { - /* If any following element does not match, it is not mirror */ - /* 1. type */ - if (this->get_type() != cand.get_type()) { - return false; - } - /* 2. track_width */ - if (this->get_chan_width() != cand.get_chan_width()) { - return false; - } - /* 3. for each node */ - for (size_t inode = 0; inode < this->get_chan_width(); ++inode) { - /* 3.1 check node type */ - if (this->get_node(inode)->type != cand.get_node(inode)->type) { - return false; - } - /* 3.2 check node directionality */ - if (this->get_node(inode)->direction != cand.get_node(inode)->direction) { - return false; - } - /* 3.3 check node segment */ - if (this->get_node_segment(inode) != cand.get_node_segment(inode)) { - return false; - } - } - - return true; -} - -/* Get a list of segments used in this routing channel */ -std::vector RRChan::get_segment_ids() const { - std::vector seg_list; - - /* make sure a clean start */ - seg_list.clear(); - - /* Traverse node_segments */ - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - std::vector::iterator it; - /* Try to find the node_segment id in the list */ - it = find(seg_list.begin(), seg_list.end(), node_segments_[inode]); - if ( it == seg_list.end() ) { - /* Not found, add it to the list */ - seg_list.push_back(node_segments_[inode]); - } - } - - return seg_list; -} - -/* Get a list of nodes whose segment_id is specified */ -std::vector RRChan::get_node_ids_by_segment_ids(size_t seg_id) const { - std::vector node_list; - - /* make sure a clean start */ - node_list.clear(); - - /* Traverse node_segments */ - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - /* Try to find the node_segment id in the list */ - if ( seg_id == node_segments_[inode] ) { - node_list.push_back(inode); - } - } - - return node_list; -} - -/* Mutators */ -void RRChan::set(const RRChan& rr_chan) { - /* Ensure a clean start */ - this->clear(); - /* Assign type of this routing channel */ - this->type_ = rr_chan.get_type(); - /* Copy node and node_segments */ - this->nodes_.resize(rr_chan.get_chan_width()); - this->node_segments_.resize(rr_chan.get_chan_width()); - for (size_t inode = 0; inode < rr_chan.get_chan_width(); ++inode) { - this->nodes_[inode] = rr_chan.get_node(inode); - this->node_segments_[inode] = rr_chan.get_node_segment(inode); - } - return; -} - -/* modify type */ -void RRChan::set_type(t_rr_type type) { - assert(valid_type(type)); - type_ = type; - return; -} - -/* Reserve node list */ -void RRChan::reserve_node(size_t node_size) { - nodes_.reserve(node_size); /* reserve to the maximum */ - node_segments_.reserve(node_size); /* reserve to the maximum */ -} - -/* add a node to the array */ -void RRChan::add_node(t_rr_node* node, size_t node_segment) { - /* fill the dedicated element in the vector */ - nodes_.push_back(node); - node_segments_.push_back(node_segment); - - assert(valid_node_type(node)); - - return; -} - -/* rotate the nodes and node_segments with a given offset */ -void RRChan::rotate(size_t offset) { - std::rotate(nodes_.begin(), nodes_.begin() + offset, nodes_.end()); - std::rotate(node_segments_.begin(), node_segments_.begin() + offset, node_segments_.end()); - return; -} - -/* rotate all the channel nodes by a given offset: - * Routing Channel nodes are divided into different groups using segment ids - * each group is rotated separatedly - */ -void RRChan::rotate(size_t rotate_begin, size_t rotate_end, size_t offset) { - std::rotate(nodes_.begin() + rotate_begin, nodes_.begin() + rotate_begin + offset, nodes_.begin() + rotate_end); - std::rotate(node_segments_.begin() + rotate_begin, node_segments_.begin() + rotate_begin + offset, node_segments_.begin() + rotate_end); - return; -} - -/* rotate all the channel nodes by a given offset: - * Routing Channel nodes are divided into different groups using segment ids - * each group should be rotated separatedly - */ -void RRChan::rotate_by_node_direction(enum e_direction node_direction, size_t offset) { - /* skip if there are no nodes */ - if (0 == get_chan_width()) { - return; - } - - /* get a list of segment_ids existing in the routing channel */ - std::vector seg_ids = get_segment_ids(); - - for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) { - /* Get the channel nodes of a given direction */ - std::vector nodes; - std::vector node_segments; - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - if ( (node_direction == get_node(inode)->direction) - && (seg_ids[iseg] == (size_t)get_node_segment(inode)) ) { - nodes.push_back(get_node(inode)); - node_segments.push_back(get_node_segment(inode)); - } - } - - size_t adapt_offset = offset % nodes.size(); - assert(adapt_offset < nodes.size()); - - /* Rotate the chan_nodes */ - std::rotate(nodes.begin(), nodes.begin() + adapt_offset, nodes.end()); - std::rotate(node_segments.begin(), node_segments.begin() + adapt_offset, node_segments.end()); - - /* back-annotate to to the original chan nodes*/ - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - if ( (node_direction == get_node(inode)->direction) - && (seg_ids[iseg] == (size_t)get_node_segment(inode)) ) { - nodes_[inode] = nodes.front(); - node_segments_[inode] = node_segments.front(); - /* pop up temp vectors */ - nodes.erase(nodes.begin()); - node_segments.erase(node_segments.begin()); - } - } - - /* Make sure temp vectors are all poped out */ - assert ( 0 == nodes.size()); - assert ( 0 == node_segments.size()); - } - - return; -} - -/* rotate all the channel nodes by a given offset: - * Routing Channel nodes are divided into different groups using segment ids - * each group is rotated separatedly - */ -void RRChan::counter_rotate_by_node_direction(enum e_direction node_direction, size_t offset) { - /* skip if there are no nodes */ - if (0 == get_chan_width()) { - return; - } - - /* get a list of segment_ids existing in the routing channel */ - std::vector seg_ids = get_segment_ids(); - - for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) { - /* Get the channel nodes of a given direction */ - std::vector nodes; - std::vector node_segments; - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - if ( (node_direction == get_node(inode)->direction) - && (seg_ids[iseg] == (size_t)get_node_segment(inode)) ) { - nodes.push_back(get_node(inode)); - node_segments.push_back(get_node_segment(inode)); - } - } - - size_t adapt_offset = offset % nodes.size(); - assert(adapt_offset < nodes.size()); - - /* Rotate the chan_nodes */ - std::rotate(nodes.begin(), nodes.begin() + nodes.size() - adapt_offset, nodes.end()); - std::rotate(node_segments.begin(), node_segments.begin() + node_segments.size() - adapt_offset, node_segments.end()); - - /* back-annotate to to the original chan nodes*/ - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - if ( (node_direction == get_node(inode)->direction) - && (seg_ids[iseg] == (size_t)get_node_segment(inode)) ) { - nodes_[inode] = nodes.front(); - node_segments_[inode] = node_segments.front(); - /* pop up temp vectors */ - nodes.erase(nodes.begin()); - node_segments.erase(node_segments.begin()); - } - } - - /* Make sure temp vectors are all poped out */ - assert ( 0 == nodes.size()); - assert ( 0 == node_segments.size()); - } - - return; -} - - -/* Mirror the node direction of routing track nodes on a side */ -void RRChan::mirror_node_direction() { - for (size_t inode = 0; inode < get_chan_width(); ++inode) { - if (INC_DIRECTION == get_node(inode)->direction) { - nodes_[inode]->direction = DEC_DIRECTION; - } else { - assert (DEC_DIRECTION == get_node(inode)->direction); - nodes_[inode]->direction = INC_DIRECTION; - } - } - return; -} - - -/* Clear content */ -void RRChan::clear() { - nodes_.clear(); - node_segments_.clear(); - - return; -} - -/* Internal functions */ - -/* for type, only valid type is CHANX and CHANY */ -bool RRChan::valid_type(t_rr_type type) const { - if ((CHANX == type) || (CHANY == type)) { - return true; - } - return false; -} - -/* Check each node, see if the node type is consistent with the type */ -bool RRChan::valid_node_type(t_rr_node* node) const { - valid_type(node->type); - if (NUM_RR_TYPES == type_) { - return true; - } - valid_type(type_); - if (type_ != node->type) { - return false; - } - return true; -} - -/* check if the node id is valid */ -bool RRChan::valid_node_id(size_t node_id) const { - if (node_id < nodes_.size()) { - return true; - } - - return false; -} - -/* Member Functions of Class DeviceRRChan */ -/* accessors */ -RRChan DeviceRRChan::get_module(t_rr_type chan_type, size_t module_id) const { - assert(valid_module_id(chan_type, module_id)); - - if (CHANX == chan_type) { - return chanx_modules_[module_id]; - } - assert (CHANY == chan_type); - return chany_modules_[module_id]; -} - -RRChan DeviceRRChan::get_module_with_coordinator(t_rr_type chan_type, size_t x, size_t y) const { - assert(valid_coordinator(chan_type, x, y)); - assert(valid_module_id(chan_type, get_module_id(chan_type, x, y))); - return get_module(chan_type, get_module_id(chan_type, x, y)); -} - -/* Get the number of RRChan modules in either X-channel or Y-channel */ -size_t DeviceRRChan::get_num_modules(t_rr_type chan_type) const { - assert(valid_chan_type(chan_type)); - - if (CHANX == chan_type) { - return chanx_modules_.size(); - } - assert (CHANY == chan_type); - return chany_modules_.size(); -} - -size_t DeviceRRChan::get_module_id(t_rr_type chan_type, size_t x, size_t y) const { - assert(valid_coordinator(chan_type, x, y)); - - if (CHANX == chan_type) { - return chanx_module_ids_[x][y]; - } - assert (CHANY == chan_type); - return chany_module_ids_[x][y]; -} - -void DeviceRRChan::init_module_ids(size_t device_width, size_t device_height) { - init_chan_module_ids(CHANX, device_width, device_height); - init_chan_module_ids(CHANY, device_width, device_height); - - return; -} - -void DeviceRRChan::init_chan_module_ids(t_rr_type chan_type, size_t device_width, size_t device_height) { - assert(valid_chan_type(chan_type)); - - if (CHANX == chan_type) { - chanx_module_ids_.resize(device_width); - for (size_t x = 0; x < chanx_module_ids_.size(); ++x) { - chanx_module_ids_[x].resize(device_height); - } - } else if (CHANY == chan_type) { - chany_module_ids_.resize(device_width); - for (size_t x = 0; x < chany_module_ids_.size(); ++x) { - chany_module_ids_[x].resize(device_height); - } - } - return; -} - -void DeviceRRChan::add_one_chan_module(t_rr_type chan_type, size_t x, size_t y, RRChan& rr_chan) { - assert(valid_coordinator(chan_type, x, y)); - - if (CHANX == chan_type) { - /* Find if the module is unique */ - for (size_t i = 0; i < chanx_modules_.size(); ++i) { - if ( true == chanx_modules_[i].is_mirror(rr_chan)) { - /* Find a mirror in the list, assign ids and return */ - chanx_module_ids_[x][y] = i; - return; - } - } - /* Reach here, it means this is a unique module */ - /* add to the module list */ - chanx_modules_.push_back(rr_chan); - chanx_module_ids_[x][y] = chanx_modules_.size() - 1; - } else if (CHANY == chan_type) { - /* Find if the module is unique */ - for (size_t i = 0; i < chany_modules_.size(); ++i) { - if ( true == chany_modules_[i].is_mirror(rr_chan)) { - /* Find a mirror in the list, assign ids and return */ - chany_module_ids_[x][y] = i; - return; - } - } - /* Reach here, it means this is a unique module */ - /* add to the module list */ - chany_modules_.push_back(rr_chan); - chany_module_ids_[x][y] = chany_modules_.size() - 1; - } - - return; -} - -void DeviceRRChan::clear() { - clear_chan(CHANX); - clear_chan(CHANY); -} - -void DeviceRRChan::clear_chan(t_rr_type chan_type) { - assert(valid_chan_type(chan_type)); - - if (CHANX == chan_type) { - chanx_modules_.clear(); - } else if (CHANY == chan_type) { - chany_modules_.clear(); - } - - return; -} - -/* for type, only valid type is CHANX and CHANY */ -bool DeviceRRChan::valid_chan_type(t_rr_type chan_type) const { - if ((CHANX == chan_type) || (CHANY == chan_type)) { - return true; - } - return false; -} - -/* check if the coordinator is in range */ -bool DeviceRRChan::valid_coordinator(t_rr_type chan_type, size_t x, size_t y) const { - assert(valid_chan_type(chan_type)); - - if (CHANX == chan_type) { - if (x > chanx_module_ids_.size() - 1 ) { - return false; - } - if (y > chanx_module_ids_[x].size() - 1) { - return false; - } - } else if (CHANY == chan_type) { - if (x > chany_module_ids_.size() - 1) { - return false; - } - if (y > chany_module_ids_[x].size() - 1) { - return false; - } - } - - return true; -} - -/* check if the node id is valid */ -bool DeviceRRChan::valid_module_id(t_rr_type chan_type, size_t module_id) const { - assert(valid_chan_type(chan_type)); - - if (CHANX == chan_type) { - if (module_id < chanx_modules_.size()) { - return true; - } - } else if (CHANY == chan_type) { - if (module_id < chany_modules_.size()) { - return true; - } - } - - return false; -} - -/* Member Functions of Class RRGSB*/ -/* Constructor for an empty object */ -RRGSB::RRGSB() { - /* Set a clean start! */ - coordinator_.set(0, 0); - chan_node_direction_.clear(); - ipin_node_.clear(); - ipin_node_grid_side_.clear(); - opin_node_.clear(); - opin_node_grid_side_.clear(); - - sb_conf_port_.reset(); - cbx_conf_port_.reset(); - cby_conf_port_.reset(); - - return; -} - -/* Copy constructor */ -RRGSB::RRGSB(const RRGSB& src) { - /* Copy coordinator */ - this->set(src); - return; -} - -/* Accessors */ - -/* Get the number of sides of this SB */ -size_t RRGSB::get_num_sides() const { - assert (validate_num_sides()); - return chan_node_direction_.size(); -} - -/* Get the number of routing tracks on a side */ -size_t RRGSB::get_chan_width(enum e_side side) const { - Side side_manager(side); - assert(side_manager.validate()); - return chan_node_[side_manager.to_size_t()].get_chan_width(); -} - -/* Get the maximum number of routing tracks on all sides */ -size_t RRGSB::get_max_chan_width() const { - size_t max_chan_width = 0; - for (size_t side = 0; side < get_num_sides(); ++side) { - Side side_manager(side); - max_chan_width = std::max(max_chan_width, get_chan_width(side_manager.get_side())); - } - return max_chan_width; -} - -/* Get the number of routing tracks of a X/Y-direction CB */ -size_t RRGSB::get_cb_chan_width(t_rr_type cb_type) const { - return get_chan_width(get_cb_chan_side(cb_type)); -} - -/* Get the sides of ipin_nodes belong to the cb */ -std::vector RRGSB::get_cb_ipin_sides(t_rr_type cb_type) const { - assert (validate_cb_type(cb_type)); - - std::vector ipin_sides; - - /* Make sure a clean start */ - ipin_sides.clear(); - - switch(cb_type) { - case CHANX: - ipin_sides.push_back(TOP); - ipin_sides.push_back(BOTTOM); - break; - case CHANY: - ipin_sides.push_back(RIGHT); - ipin_sides.push_back(LEFT); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } - - return ipin_sides; -} - -/* Get the direction of a rr_node at a given side and track_id */ -enum PORTS RRGSB::get_chan_node_direction(enum e_side side, size_t track_id) const { - Side side_manager(side); - assert(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - assert( validate_side(side) ); - - /* Ensure the track is valid in the context of this switch block at a specific side */ - assert( validate_track_id(side, track_id) ); - - return chan_node_direction_[side_manager.to_size_t()][track_id]; -} - -/* get a RRChan at a given side and track_id */ -RRChan RRGSB::get_chan(enum e_side side) const { - Side side_manager(side); - assert(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - assert( validate_side(side) ); - - return chan_node_[side_manager.to_size_t()]; -} - -/* Get a list of segments used in this routing channel */ -std::vector RRGSB::get_chan_segment_ids(enum e_side side) const { - Side side_manager(side); - assert(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - assert( validate_side(side) ); - - return get_chan(side).get_segment_ids(); -} - -/* Get a list of rr_nodes whose sed_id is specified */ -std::vector RRGSB::get_chan_node_ids_by_segment_ids(enum e_side side, size_t seg_id) const { - return get_chan(side).get_node_ids_by_segment_ids(seg_id); -} - -/* get a rr_node at a given side and track_id */ -t_rr_node* RRGSB::get_chan_node(enum e_side side, size_t track_id) const { - Side side_manager(side); - assert(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - assert( validate_side(side) ); - - /* Ensure the track is valid in the context of this switch block at a specific side */ - assert( validate_track_id(side, track_id) ); - - return chan_node_[side_manager.to_size_t()].get_node(track_id); -} - -/* get the segment id of a channel rr_node */ -size_t RRGSB::get_chan_node_segment(enum e_side side, size_t track_id) const { - Side side_manager(side); - assert(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - assert( validate_side(side) ); - - /* Ensure the track is valid in the context of this switch block at a specific side */ - assert( validate_track_id(side, track_id) ); - - return chan_node_[side_manager.to_size_t()].get_node_segment(track_id); -} - - -/* Get the number of IPIN rr_nodes on a side */ -size_t RRGSB::get_num_ipin_nodes(enum e_side side) const { - Side side_manager(side); - assert(side_manager.validate()); - return ipin_node_[side_manager.to_size_t()].size(); -} - -/* get a opin_node at a given side and track_id */ -t_rr_node* RRGSB::get_ipin_node(enum e_side side, size_t node_id) const { - Side side_manager(side); - assert(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - assert( validate_side(side) ); - - /* Ensure the track is valid in the context of this switch block at a specific side */ - assert( validate_ipin_node_id(side, node_id) ); - - return ipin_node_[side_manager.to_size_t()][node_id]; -} - -/* get the grid_side of a opin_node at a given side and track_id */ -enum e_side RRGSB::get_ipin_node_grid_side(enum e_side side, size_t node_id) const { - Side side_manager(side); - assert(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - assert( validate_side(side) ); - - /* Ensure the track is valid in the context of this switch block at a specific side */ - assert( validate_ipin_node_id(side, node_id) ); - - return ipin_node_grid_side_[side_manager.to_size_t()][node_id]; -} - -/* get the grid side of a opin_rr_node */ -enum e_side RRGSB::get_ipin_node_grid_side(t_rr_node* ipin_node) const { - enum e_side side; - int index; - - /* Find the side and index */ - get_node_side_and_index(ipin_node, OUT_PORT, &side, &index); - assert(-1 != index); - assert(validate_side(side)); - return get_ipin_node_grid_side(side, index); -} - - -/* Get the number of OPIN rr_nodes on a side */ -size_t RRGSB::get_num_opin_nodes(enum e_side side) const { - Side side_manager(side); - assert(side_manager.validate()); - return opin_node_[side_manager.to_size_t()].size(); -} - -/* get a opin_node at a given side and track_id */ -t_rr_node* RRGSB::get_opin_node(enum e_side side, size_t node_id) const { - Side side_manager(side); - assert(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - assert( validate_side(side) ); - - /* Ensure the track is valid in the context of this switch block at a specific side */ - assert( validate_opin_node_id(side, node_id) ); - - return opin_node_[side_manager.to_size_t()][node_id]; -} - -/* get the grid_side of a opin_node at a given side and track_id */ -enum e_side RRGSB::get_opin_node_grid_side(enum e_side side, size_t node_id) const { - Side side_manager(side); - assert(side_manager.validate()); - - /* Ensure the side is valid in the context of this switch block */ - assert( validate_side(side) ); - - /* Ensure the track is valid in the context of this switch block at a specific side */ - assert( validate_opin_node_id(side, node_id) ); - - return opin_node_grid_side_[side_manager.to_size_t()][node_id]; -} - -/* get the grid side of a opin_rr_node */ -enum e_side RRGSB::get_opin_node_grid_side(t_rr_node* opin_node) const { - enum e_side side; - int index; - - /* Find the side and index */ - get_node_side_and_index(opin_node, IN_PORT, &side, &index); - assert(-1 != index); - assert(validate_side(side)); - return get_opin_node_grid_side(side, index); -} - -/* Get the node index of a routing track of a connection block, return -1 if not found */ -int RRGSB::get_cb_chan_node_index(t_rr_type cb_type, t_rr_node* node) const { - enum e_side chan_side = get_cb_chan_side(cb_type); - return get_chan_node_index(chan_side, node); -} - -/* Get the node index in the array, return -1 if not found */ -int RRGSB::get_chan_node_index(enum e_side node_side, t_rr_node* node) const { - assert (validate_side(node_side)); - return get_chan(node_side).get_node_track_id(node); -} - -/* Get the node index in the array, return -1 if not found */ -int RRGSB::get_node_index(t_rr_node* node, - enum e_side node_side, - enum PORTS node_direction) const { - size_t cnt; - int ret; - Side side_manager(node_side); - - cnt = 0; - ret = -1; - - /* Depending on the type of rr_node, we search different arrays */ - switch (node->type) { - case CHANX: - case CHANY: - for (size_t inode = 0; inode < get_chan_width(node_side); ++inode){ - if ((node == chan_node_[side_manager.to_size_t()].get_node(inode)) - /* Check if direction meets specification */ - &&(node_direction == chan_node_direction_[side_manager.to_size_t()][inode])) { - cnt++; - ret = inode; - break; - } - } - break; - case IPIN: - for (size_t inode = 0; inode < get_num_ipin_nodes(node_side); ++inode) { - if (node == ipin_node_[side_manager.to_size_t()][inode]) { - cnt++; - ret = inode; - break; - } - } - break; - case OPIN: - for (size_t inode = 0; inode < get_num_opin_nodes(node_side); ++inode) { - if (node == opin_node_[side_manager.to_size_t()][inode]) { - cnt++; - ret = inode; - break; - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid cur_rr_node type! Should be [CHANX|CHANY|IPIN|OPIN]\n", - __FILE__, __LINE__); - exit(1); - } - - assert((0 == cnt)||(1 == cnt)); - - return ret; /* Return an invalid value: nonthing is found*/ -} - -/* Check if the node exist in the opposite side of this Switch Block */ -bool RRGSB::is_sb_node_exist_opposite_side(t_rr_node* node, - enum e_side node_side) const { - Side side_manager(node_side); - int index; - - assert((CHANX == node->type) || (CHANY == node->type)); - - /* See if we can find the same src_rr_node in the opposite chan_side - * if there is one, it means a shorted wire across the SB - */ - index = get_node_index(node, side_manager.get_opposite(), IN_PORT); - - if (-1 != index) { - return true; - } - - return false; -} - -/* Get the side of a node in this SB */ -void RRGSB::get_node_side_and_index(t_rr_node* node, - enum PORTS node_direction, - enum e_side* node_side, - int* node_index) const { - size_t side; - Side side_manager; - - /* Count the number of existence of cur_rr_node in cur_sb_info - * It could happen that same cur_rr_node appears on different sides of a SB - * For example, a routing track go vertically across the SB. - * Then its corresponding rr_node appears on both TOP and BOTTOM sides of this SB. - * We need to ensure that the found rr_node has the same direction as user want. - * By specifying the direction of rr_node, There should be only one rr_node can satisfy! - */ - for (side = 0; side < get_num_sides(); ++side) { - side_manager.set_side(side); - (*node_index) = get_node_index(node, side_manager.get_side(), node_direction); - if (-1 != (*node_index)) { - break; - } - } - - if (side == get_num_sides()) { - /* we find nothing, return NUM_SIDES, and a OPEN node (-1) */ - (*node_side) = NUM_SIDES; - assert(-1 == (*node_index)); - return; - } - - (*node_side) = side_manager.get_side(); - assert(-1 != (*node_index)); - - return; -} - -/* Get Switch Block configuration port information */ -size_t RRGSB::get_sb_num_reserved_conf_bits() const { - return sb_conf_port_.get_reserved_port_width(); -} - -size_t RRGSB::get_sb_reserved_conf_bits_lsb() const { - return sb_conf_port_.get_reserved_port_lsb(); -} - -size_t RRGSB::get_sb_reserved_conf_bits_msb() const { - return sb_conf_port_.get_reserved_port_msb(); -} - -size_t RRGSB::get_sb_num_conf_bits() const { - return sb_conf_port_.get_regular_port_width(); -} - -size_t RRGSB::get_sb_conf_bits_lsb() const { - return sb_conf_port_.get_regular_port_lsb(); -} - -size_t RRGSB::get_sb_conf_bits_msb() const { - return sb_conf_port_.get_regular_port_msb(); -} - -/* Get X-direction Connection Block configuration port information */ -size_t RRGSB::get_cb_num_reserved_conf_bits(t_rr_type cb_type) const { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return cbx_conf_port_.get_reserved_port_width(); - case CHANY: - return cby_conf_port_.get_reserved_port_width(); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -size_t RRGSB::get_cb_reserved_conf_bits_lsb(t_rr_type cb_type) const { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return cbx_conf_port_.get_reserved_port_lsb(); - case CHANY: - return cby_conf_port_.get_reserved_port_lsb(); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -size_t RRGSB::get_cb_reserved_conf_bits_msb(t_rr_type cb_type) const { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return cbx_conf_port_.get_reserved_port_msb(); - case CHANY: - return cby_conf_port_.get_reserved_port_msb(); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -size_t RRGSB::get_cb_num_conf_bits(t_rr_type cb_type) const { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return cbx_conf_port_.get_regular_port_width(); - case CHANY: - return cby_conf_port_.get_regular_port_width(); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -size_t RRGSB::get_cb_conf_bits_lsb(t_rr_type cb_type) const { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return cbx_conf_port_.get_regular_port_lsb(); - case CHANY: - return cby_conf_port_.get_regular_port_lsb(); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -size_t RRGSB::get_cb_conf_bits_msb(t_rr_type cb_type) const { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return cbx_conf_port_.get_regular_port_msb(); - case CHANY: - return cby_conf_port_.get_regular_port_msb(); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/************************************************************************ - * Check if the node indicates a passing wire across the Switch Block part of the GSB - * Therefore, we actually do the following check - * Check if a track starts from this GSB or not - * For INC_DIRECTION - * (xlow, ylow) should be same as the GSB side coordinator - * For DEC_DIRECTION - * (xhigh, yhigh) should be same as the GSB side coordinator - ***********************************************************************/ -bool RRGSB::is_sb_node_passing_wire(const enum e_side node_side, - const size_t track_id) const { - - /* Get the rr_node */ - t_rr_node* track_node = get_chan_node(node_side, track_id); - /* Get the coordinators */ - DeviceCoordinator side_coordinator = get_side_block_coordinator(node_side); - - /* Get the coordinator of where the track starts */ - DeviceCoordinator track_start = get_track_rr_node_start_coordinator(track_node); - - /* INC_DIRECTION start_track: (xlow, ylow) should be same as the GSB side coordinator */ - /* DEC_DIRECTION start_track: (xhigh, yhigh) should be same as the GSB side coordinator */ - if ( (track_start.get_x() == side_coordinator.get_x()) - && (track_start.get_y() == side_coordinator.get_y()) - && (OUT_PORT == get_chan_node_direction(node_side, track_id)) ) { - /* Double check: start track should be an OUTPUT PORT of the GSB */ - return false; /* This is a starting point */ - } - - /* Get the coordinator of where the track ends */ - DeviceCoordinator track_end = get_track_rr_node_end_coordinator(track_node); - - /* INC_DIRECTION end_track: (xhigh, yhigh) should be same as the GSB side coordinator */ - /* DEC_DIRECTION end_track: (xlow, ylow) should be same as the GSB side coordinator */ - if ( (track_end.get_x() == side_coordinator.get_x()) - && (track_end.get_y() == side_coordinator.get_y()) - && (IN_PORT == get_chan_node_direction(node_side, track_id)) ) { - /* Double check: end track should be an INPUT PORT of the GSB */ - return false; /* This is an ending point */ - } - - /* Reach here it means that this will be a passing wire, - * we should be able to find the node on the opposite side of the GSB! - */ - assert (true == is_sb_node_exist_opposite_side(track_node, node_side)); - - return true; -} - -/* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */ -/* Idenify mirror Switch blocks - * Check each two switch blocks: - * Number of channel/opin/ipin rr_nodes are same - * If all above are satisfied, the two switch blocks may be mirrors ! - */ -bool RRGSB::is_sb_mirrorable(const RRGSB& cand) const { - /* check the numbers of sides */ - if (get_num_sides() != cand.get_num_sides()) { - return false; - } - - /* check the numbers/directionality of channel rr_nodes */ - for (size_t side = 0; side < get_num_sides(); ++side) { - Side side_manager(side); - - /* Ensure we have the same channel width on this side */ - if (get_chan_width(side_manager.get_side()) != cand.get_chan_width(side_manager.get_side())) { - return false; - } - - if ( ((size_t(-1) == get_track_id_first_short_connection(side_manager.get_side())) - && (size_t(-1) != cand.get_track_id_first_short_connection(side_manager.get_side()))) - || ((size_t(-1) != get_track_id_first_short_connection(side_manager.get_side()) ) - && ( size_t(-1) == cand.get_track_id_first_short_connection(side_manager.get_side()))) ) { - return false; - } - } - - /* check the numbers of opin_rr_nodes */ - for (size_t side = 0; side < get_num_sides(); ++side) { - Side side_manager(side); - - if (get_num_opin_nodes(side_manager.get_side()) != cand.get_num_opin_nodes(side_manager.get_side())) { - return false; - } - } - - /* Make sure the number of conf bits are the same */ - if ( ( get_sb_num_conf_bits() != cand.get_sb_num_conf_bits() ) - || ( get_sb_num_reserved_conf_bits() != cand.get_sb_num_reserved_conf_bits() ) ) { - return false; - } - - return true; -} - -/* check if the candidate CB is a mirror of the current one */ -bool RRGSB::is_cb_mirror(const RRGSB& cand, t_rr_type cb_type) const { - /* Check if channel width is the same */ - if ( get_cb_chan_width(cb_type) != cand.get_cb_chan_width(cb_type) ) { - return false; - } - - enum e_side chan_side = get_cb_chan_side(cb_type); - - /* check the numbers/directionality of channel rr_nodes */ - if ( false == get_chan(chan_side).is_mirror(cand.get_chan(chan_side)) ) { - return false; - } - - /* check the equivalence of ipins */ - std::vector ipin_side = get_cb_ipin_sides(cb_type); - for (size_t side = 0; side < ipin_side.size(); ++side) { - /* Ensure we have the same number of IPINs on this side */ - if ( get_num_ipin_nodes(ipin_side[side]) != cand.get_num_ipin_nodes(ipin_side[side]) ) { - return false; - } - for (size_t inode = 0; inode < get_num_ipin_nodes(ipin_side[side]); ++inode) { - if (false == is_cb_node_mirror(cand, cb_type, ipin_side[side], inode)) { - return false; - } - } - } - - /* Make sure the number of conf bits are the same */ - if ( ( get_cb_num_conf_bits(cb_type) != cand.get_cb_num_conf_bits(cb_type) ) - || ( get_cb_num_reserved_conf_bits(cb_type) != cand.get_cb_num_reserved_conf_bits(cb_type) ) ) { - return false; - } - - return true; -} - -/* check if the CB exist in this GSB */ -bool RRGSB::is_cb_exist(t_rr_type cb_type) const { - /* if channel width is zero, there is no CB */ - if ( 0 == get_cb_chan_width(cb_type)) { - return false; - } - return true; -} - -/* Determine an initial offset in rotating the candidate Switch Block to find a mirror matching - * We try to find the offset in track_id where the two Switch Blocks have their first short connections - */ -size_t RRGSB::get_hint_rotate_offset(const RRGSB& cand) const { - size_t offset_hint = size_t(-1); - - assert (get_num_sides() == cand.get_num_sides()); - - /* check the numbers/directionality of channel rr_nodes */ - for (size_t side = 0; side < get_num_sides(); ++side) { - Side side_manager(side); - - /* Ensure we have the same channel width on this side */ - assert (get_chan_width(side_manager.get_side()) == cand.get_chan_width(side_manager.get_side())); - - /* Find the track id of the first short connection */ - size_t src_offset = get_track_id_first_short_connection(side_manager.get_side()); - size_t des_offset = cand.get_track_id_first_short_connection(side_manager.get_side()); - if ( size_t(-1) == src_offset || size_t(-1) == des_offset ) { - return 0; /* default we give zero */ - } - size_t temp_hint = abs( (int)(src_offset - des_offset)); - offset_hint = std::min(temp_hint, offset_hint); - } - return offset_hint; -} - -/* check if all the routing segments of a side of candidate SB is a mirror of the current one */ -bool RRGSB::is_sb_side_segment_mirror(const RRGSB& cand, enum e_side side, size_t seg_id) const { - /* Create a side manager */ - Side side_manager(side); - - /* Make sure both Switch blocks has this side!!! */ - assert ( side_manager.to_size_t() < get_num_sides() ); - assert ( side_manager.to_size_t() < cand.get_num_sides() ); - - - /* check the numbers/directionality of channel rr_nodes */ - /* Ensure we have the same channel width on this side */ - if (get_chan_width(side) != cand.get_chan_width(side)) { - return false; - } - for (size_t itrack = 0; itrack < get_chan_width(side); ++itrack) { - /* Bypass unrelated segments */ - if (seg_id != get_chan_node_segment(side, itrack)) { - continue; - } - /* Check the directionality of each node */ - if (get_chan_node_direction(side, itrack) != cand.get_chan_node_direction(side, itrack)) { - return false; - } - /* Check the track_id of each node - * ptc is not necessary, we care the connectivity! - if (get_chan_node(side_manager.get_side(), itrack)->ptc_num != cand.get_chan_node(side_manager.get_side(), itrack)->ptc_num) { - eturn false; - } - */ - /* For OUT_PORT rr_node, we need to check fan-in */ - if (OUT_PORT != get_chan_node_direction(side, itrack)) { - continue; /* skip IN_PORT */ - } - - if (false == is_sb_node_mirror(cand, side, itrack)) { - return false; - } - } - - /* check the numbers of opin_rr_nodes */ - if (get_num_opin_nodes(side) != cand.get_num_opin_nodes(side)) { - return false; - } - - /* check the numbers of ipin_rr_nodes */ - if (get_num_ipin_nodes(side) != cand.get_num_ipin_nodes(side)) { - return false; - } - - return true; -} - -/* check if a side of candidate SB is a mirror of the current one - * Check the specified side of two switch blocks: - * 1. Number of channel/opin/ipin rr_nodes are same - * For channel rr_nodes - * 2. check if their track_ids (ptc_num) are same - * 3. Check if the switches (ids) are same - * For opin/ipin rr_nodes, - * 4. check if their parent type_descriptors same, - * 5. check if pin class id and pin id are same - * If all above are satisfied, the side of the two switch blocks are mirrors! - */ -bool RRGSB::is_sb_side_mirror(const RRGSB& cand, enum e_side side) const { - - /* get a list of segments */ - std::vector seg_ids = get_chan(side).get_segment_ids(); - - for (size_t iseg = 0; iseg < seg_ids.size(); ++iseg) { - if (false == is_sb_side_segment_mirror(cand, side, seg_ids[iseg])) { - return false; - } - } - - return true; -} - - -/* check if the candidate SB is a mirror of the current one */ -/* Idenify mirror Switch blocks - * Check each two switch blocks: - * 1. Number of channel/opin/ipin rr_nodes are same - * For channel rr_nodes - * 2. check if their track_ids (ptc_num) are same - * 3. Check if the switches (ids) are same - * For opin/ipin rr_nodes, - * 4. check if their parent type_descriptors same, - * 5. check if pin class id and pin id are same - * If all above are satisfied, the two switch blocks are mirrors! - */ -bool RRGSB::is_sb_mirror(const RRGSB& cand) const { - /* check the numbers of sides */ - if (get_num_sides() != cand.get_num_sides()) { - return false; - } - - /* check the numbers/directionality of channel rr_nodes */ - for (size_t side = 0; side < get_num_sides(); ++side) { - Side side_manager(side); - if (false == is_sb_side_mirror(cand, side_manager.get_side())) { - return false; - } - } - - /* Make sure the number of conf bits are the same */ - if ( ( get_sb_num_conf_bits() != cand.get_sb_num_conf_bits() ) - || ( get_sb_num_reserved_conf_bits() != cand.get_sb_num_reserved_conf_bits() ) ) { - return false; - } - - return true; -} - -/* Public Accessors: Cooridinator conversion */ - -/* get the x coordinator of this GSB */ -size_t RRGSB::get_x() const { - return coordinator_.get_x(); -} - -/* get the y coordinator of this GSB */ -size_t RRGSB::get_y() const { - return coordinator_.get_y(); -} - - -/* get the x coordinator of this switch block */ -size_t RRGSB::get_sb_x() const { - return coordinator_.get_x(); -} - -/* get the y coordinator of this switch block */ -size_t RRGSB::get_sb_y() const { - return coordinator_.get_y(); -} - -/* Get the number of sides of this SB */ -DeviceCoordinator RRGSB::get_sb_coordinator() const { - return coordinator_; -} - -/* get the x coordinator of this X/Y-direction block */ -size_t RRGSB::get_cb_x(t_rr_type cb_type) const { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return get_side_block_coordinator(LEFT).get_x(); - case CHANY: - return get_side_block_coordinator(TOP).get_x(); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/* get the y coordinator of this X/Y-direction block */ -size_t RRGSB::get_cb_y(t_rr_type cb_type) const { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return get_side_block_coordinator(LEFT).get_y(); - case CHANY: - return get_side_block_coordinator(TOP).get_y(); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/* Get the coordinator of the X/Y-direction CB */ -DeviceCoordinator RRGSB::get_cb_coordinator(t_rr_type cb_type) const { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return get_side_block_coordinator(LEFT); - case CHANY: - return get_side_block_coordinator(TOP); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -enum e_side RRGSB::get_cb_chan_side(t_rr_type cb_type) const { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return LEFT; - case CHANY: - return TOP; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/* Get the side of routing channel in the GSB according to the side of IPIN */ -enum e_side RRGSB::get_cb_chan_side(enum e_side ipin_side) const { - switch(ipin_side) { - case TOP: - return LEFT; - case RIGHT: - return TOP; - case BOTTOM: - return LEFT; - case LEFT: - return TOP; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of ipin_side!\n", - __FILE__, __LINE__); - exit(1); - } -} - -DeviceCoordinator RRGSB::get_side_block_coordinator(enum e_side side) const { - Side side_manager(side); - assert(side_manager.validate()); - DeviceCoordinator ret(get_sb_x(), get_sb_y()); - - switch (side_manager.get_side()) { - case TOP: - /* (0 == side) */ - /* 1. Channel Y [x][y+1] inputs */ - ret.set_y(ret.get_y() + 1); - break; - case RIGHT: - /* 1 == side */ - /* 2. Channel X [x+1][y] inputs */ - ret.set_x(ret.get_x() + 1); - break; - case BOTTOM: - /* 2 == side */ - /* 3. Channel Y [x][y] inputs */ - break; - case LEFT: - /* 3 == side */ - /* 4. Channel X [x][y] inputs */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid side!\n", - __FILE__, __LINE__); - exit(1); - } - - return ret; -} - -DeviceCoordinator RRGSB::get_grid_coordinator() const { - DeviceCoordinator ret(get_sb_x(), get_sb_y()); - ret.set_y(ret.get_y() + 1); - - return ret; -} - -/* Public Accessors Verilog writer */ -const char* RRGSB::gen_cb_verilog_routing_track_name(t_rr_type cb_type, - size_t track_id) const { - std::string cb_name(convert_chan_type_to_string(cb_type)); - std::string x_str = std::to_string(get_cb_x(cb_type)); - std::string y_str = std::to_string(get_cb_y(cb_type)); - std::string track_id_str = std::to_string(track_id); - - char* ret = (char*)my_malloc(sizeof(char)* - ( cb_name.length() + 1 - + x_str.length() + 2 - + y_str.length() + 9 - + track_id_str.length() + 1 - + 1)); - sprintf (ret, "%s_%s__%s__midout_%s_", - cb_name.c_str(), x_str.c_str(), y_str.c_str(), track_id_str.c_str()); - - return ret; -} - -const char* RRGSB::gen_sb_verilog_module_name() const { - std::string x_str = std::to_string(get_sb_x()); - std::string y_str = std::to_string(get_sb_y()); - - char* ret = (char*)my_malloc(sizeof(char)* - ( 2 + 1 - + x_str.length() + 2 - + y_str.length() + 1 - + 1)); - sprintf (ret, "sb_%s__%s_", - x_str.c_str(), y_str.c_str()); - - return ret; -} - -const char* RRGSB::gen_gsb_verilog_module_name() const { - std::string x_str = std::to_string(get_sb_x()); - std::string y_str = std::to_string(get_sb_y()); - - char* ret = (char*)my_malloc(sizeof(char)* - ( 3 + 1 - + x_str.length() + 2 - + y_str.length() + 1 - + 1)); - sprintf (ret, "gsb_%s__%s_", - x_str.c_str(), y_str.c_str()); - - return ret; -} - -const char* RRGSB::gen_sb_verilog_instance_name() const { - char* ret = (char*)my_malloc(sizeof(char)* - ( strlen(gen_sb_verilog_module_name()) + 3 - + 1)); - sprintf (ret, "%s_0_", - gen_sb_verilog_module_name()); - - return ret; -} - -const char* RRGSB::gen_gsb_verilog_instance_name() const { - char* ret = (char*)my_malloc(sizeof(char)* - ( strlen(gen_gsb_verilog_module_name()) + 3 - + 1)); - sprintf (ret, "%s_0_", - gen_gsb_verilog_module_name()); - - return ret; -} - -/* Public Accessors Verilog writer */ -const char* RRGSB::gen_sb_verilog_side_module_name(enum e_side side, size_t seg_id) const { - Side side_manager(side); - - std::string prefix_str(gen_sb_verilog_module_name()); - std::string seg_id_str(std::to_string(seg_id)); - std::string side_str(side_manager.to_string()); - - char* ret = (char*)my_malloc(sizeof(char)* - ( prefix_str.length() + 1 - + side_str.length() + 5 - + seg_id_str.length() + 1 - + 1)); - sprintf (ret, "%s_%s_seg_%s_", - prefix_str.c_str(), side_str.c_str(), seg_id_str.c_str()); - - return ret; -} - -const char* RRGSB::gen_sb_verilog_side_instance_name(enum e_side side, size_t seg_id) const { - std::string prefix_str = gen_sb_verilog_side_module_name(side, seg_id); - char* ret = (char*)my_malloc(sizeof(char)* - ( prefix_str.length() + 3 - + 1)); - sprintf (ret, "%s_0_", - prefix_str.c_str()); - - return ret; -} - -/* Public Accessors Verilog writer */ -const char* RRGSB::gen_cb_verilog_module_name(t_rr_type cb_type) const { - /* check */ - assert (validate_cb_type(cb_type)); - - std::string prefix_str = convert_cb_type_to_string(cb_type); - std::string x_str = std::to_string(get_cb_x(cb_type)); - std::string y_str = std::to_string(get_cb_y(cb_type)); - - char* ret = (char*)my_malloc(sizeof(char)* - ( prefix_str.length() + 1 - + x_str.length() + 2 - + y_str.length() + 1 - + 1)); - sprintf (ret, "%s_%s__%s_", - prefix_str.c_str(), x_str.c_str(), y_str.c_str()); - - return ret; -} - -const char* RRGSB::gen_cb_verilog_instance_name(t_rr_type cb_type) const { - /* check */ - assert (validate_cb_type(cb_type)); - - std::string prefix_str = gen_cb_verilog_module_name(cb_type); - char* ret = (char*)my_malloc(sizeof(char)* - (prefix_str.length() + 3 - + 1)); - sprintf (ret, "%s_0_", - prefix_str.c_str()); - - return ret; -} - -/* Public mutators */ - -/* get a copy from a source */ -void RRGSB::set(const RRGSB& src) { - /* Copy coordinator */ - this->set_coordinator(src.get_sb_coordinator().get_x(), src.get_sb_coordinator().get_y()); - - /* Initialize sides */ - this->init_num_sides(src.get_num_sides()); - - /* Copy vectors */ - for (size_t side = 0; side < src.get_num_sides(); ++side) { - Side side_manager(side); - /* Copy chan_nodes */ - /* skip if there is no channel width */ - if ( 0 < src.get_chan_width(side_manager.get_side()) ) { - this->chan_node_[side_manager.get_side()].set(src.get_chan(side_manager.get_side())); - /* Copy chan_node_direction_*/ - this->chan_node_direction_[side_manager.get_side()].clear(); - for (size_t inode = 0; inode < src.get_chan_width(side_manager.get_side()); ++inode) { - this->chan_node_direction_[side_manager.get_side()].push_back(src.get_chan_node_direction(side_manager.get_side(), inode)); - } - } - - /* Copy opin_node and opin_node_grid_side_ */ - this->opin_node_[side_manager.get_side()].clear(); - this->opin_node_grid_side_[side_manager.get_side()].clear(); - for (size_t inode = 0; inode < src.get_num_opin_nodes(side_manager.get_side()); ++inode) { - this->opin_node_[side_manager.get_side()].push_back(src.get_opin_node(side_manager.get_side(), inode)); - this->opin_node_grid_side_[side_manager.get_side()].push_back(src.get_opin_node_grid_side(side_manager.get_side(), inode)); - } - - /* Copy ipin_node and ipin_node_grid_side_ */ - this->ipin_node_[side_manager.get_side()].clear(); - this->ipin_node_grid_side_[side_manager.get_side()].clear(); - for (size_t inode = 0; inode < src.get_num_ipin_nodes(side_manager.get_side()); ++inode) { - this->ipin_node_[side_manager.get_side()].push_back(src.get_ipin_node(side_manager.get_side(), inode)); - this->ipin_node_grid_side_[side_manager.get_side()].push_back(src.get_ipin_node_grid_side(side_manager.get_side(), inode)); - } - } - - /* Copy conf_bits - */ - this->set_sb_num_reserved_conf_bits(src.get_sb_num_reserved_conf_bits()); - this->set_sb_conf_bits_lsb(src.get_sb_conf_bits_lsb()); - this->set_sb_conf_bits_msb(src.get_sb_conf_bits_msb()); - - this->set_cb_num_reserved_conf_bits(CHANX, src.get_cb_num_reserved_conf_bits(CHANX)); - this->set_cb_conf_bits_lsb(CHANX, src.get_cb_conf_bits_lsb(CHANX)); - this->set_cb_conf_bits_msb(CHANX, src.get_cb_conf_bits_msb(CHANX)); - - this->set_cb_num_reserved_conf_bits(CHANY, src.get_cb_num_reserved_conf_bits(CHANY)); - this->set_cb_conf_bits_lsb(CHANY, src.get_cb_conf_bits_lsb(CHANY)); - this->set_cb_conf_bits_msb(CHANY, src.get_cb_conf_bits_msb(CHANY)); - - return; -} - -/* Set the coordinator (x,y) for the switch block */ -void RRGSB::set_coordinator(size_t x, size_t y) { - coordinator_.set(x, y); - return; -} - -/* Allocate the vectors with the given number of sides */ -void RRGSB::init_num_sides(size_t num_sides) { - /* Initialize the vectors */ - chan_node_.resize(num_sides); - chan_node_direction_.resize(num_sides); - ipin_node_.resize(num_sides); - ipin_node_grid_side_.resize(num_sides); - opin_node_.resize(num_sides); - opin_node_grid_side_.resize(num_sides); - return; -} - -/* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ -void RRGSB::add_chan_node(enum e_side node_side, RRChan& rr_chan, std::vector rr_chan_dir) { - Side side_manager(node_side); - /* Validate: 1. side is valid, the type of node is valid */ - assert(validate_side(node_side)); - - /* fill the dedicated element in the vector */ - chan_node_[side_manager.to_size_t()].set(rr_chan); - chan_node_direction_[side_manager.to_size_t()].resize(rr_chan_dir.size()); - for (size_t inode = 0; inode < rr_chan_dir.size(); ++inode) { - chan_node_direction_[side_manager.to_size_t()][inode] = rr_chan_dir[inode]; - } - - return; -} - -/* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ -void RRGSB::add_ipin_node(t_rr_node* node, const enum e_side node_side, const enum e_side grid_side) { - Side side_manager(node_side); - assert(validate_side(node_side)); - /* push pack the dedicated element in the vector */ - ipin_node_[side_manager.to_size_t()].push_back(node); - ipin_node_grid_side_[side_manager.to_size_t()].push_back(grid_side); - - return; -} - -/* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ -void RRGSB::add_opin_node(t_rr_node* node, const enum e_side node_side, const enum e_side grid_side) { - Side side_manager(node_side); - assert(validate_side(node_side)); - /* push pack the dedicated element in the vector */ - opin_node_[side_manager.to_size_t()].push_back(node); - opin_node_grid_side_[side_manager.to_size_t()].push_back(grid_side); - - return; -} - -void RRGSB::set_sb_num_reserved_conf_bits(size_t num_reserved_conf_bits) { - return sb_conf_port_.set_reserved_port(num_reserved_conf_bits); -} - -void RRGSB::set_sb_conf_bits_lsb(size_t conf_bits_lsb) { - return sb_conf_port_.set_regular_port_lsb(conf_bits_lsb); -} - -void RRGSB::set_sb_conf_bits_msb(size_t conf_bits_msb) { - return sb_conf_port_.set_regular_port_msb(conf_bits_msb); -} - -void RRGSB::set_cb_num_reserved_conf_bits(t_rr_type cb_type, size_t num_reserved_conf_bits) { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return cbx_conf_port_.set_reserved_port(num_reserved_conf_bits); - case CHANY: - return cby_conf_port_.set_reserved_port(num_reserved_conf_bits); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -void RRGSB::set_cb_conf_bits_lsb(t_rr_type cb_type, size_t conf_bits_lsb) { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return cbx_conf_port_.set_regular_port_lsb(conf_bits_lsb); - case CHANY: - return cby_conf_port_.set_regular_port_lsb(conf_bits_lsb); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -void RRGSB::set_cb_conf_bits_msb(t_rr_type cb_type, size_t conf_bits_msb) { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return cbx_conf_port_.set_regular_port_msb(conf_bits_msb); - case CHANY: - return cby_conf_port_.set_regular_port_msb(conf_bits_msb); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/* rotate the channel nodes with the same direction on one side by a given offset */ -void RRGSB::rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset) { - Side side_manager(side); - assert(validate_side(side)); - - /* Partition the chan nodes on this side, depending on its length */ - /* skip this side if there is no nodes */ - if (0 == get_chan_width(side)) { - return; - } - - /* Rotate the chan_nodes */ - chan_node_[side_manager.to_size_t()].rotate_by_node_direction(chan_dir, offset); - - return; -} - -/* rotate the channel nodes with the same direction on one side by a given offset */ -void RRGSB::counter_rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset) { - Side side_manager(side); - assert(validate_side(side)); - - /* Partition the chan nodes on this side, depending on its length */ - /* skip this side if there is no nodes */ - if (0 == get_chan_width(side)) { - return; - } - - /* Rotate the chan_nodes */ - chan_node_[side_manager.to_size_t()].counter_rotate_by_node_direction(chan_dir, offset); - - return; - -} - - -/* rotate all the channel nodes by a given offset */ -void RRGSB::rotate_side_chan_node(enum e_side side, size_t offset) { - Side side_manager(side); - /* Partition the chan nodes on this side, depending on its length */ - /* skip this side if there is no nodes */ - if (0 == get_chan_width(side)) { - return; - } - size_t adapt_offset = offset % get_chan_width(side); - assert(adapt_offset < get_chan_width(side)); - /* Find a group split, rotate */ - chan_node_[side_manager.to_size_t()].rotate(adapt_offset); - std::rotate(chan_node_direction_[side_manager.to_size_t()].begin(), - chan_node_direction_[side_manager.to_size_t()].begin() + adapt_offset, - chan_node_direction_[side_manager.to_size_t()].end()); - return; -} - - -/* rotate all the channel nodes by a given offset */ -void RRGSB::rotate_chan_node(size_t offset) { - /* Rotate chan nodes on each side */ - for (size_t side = 0; side < get_num_sides(); ++side) { - Side side_manager(side); - rotate_side_chan_node(side_manager.get_side(), offset); - } - - return; -} - -/* rotate all the channel nodes by a given offset: - * Routing Channel nodes are divided into different groups using segment ids - * each group is rotated separatedly - */ -void RRGSB::rotate_chan_node_in_group(size_t offset) { - /* Rotate chan nodes on each side */ - for (size_t side = 0; side < get_num_sides(); ++side) { - Side side_manager(side); - size_t rotate_begin = 0; - size_t rotate_end = 0; - /* Partition the chan nodes on this side, depending on its length */ - /* skip this side if there is no nodes */ - if (0 == get_chan_width(side_manager.get_side())) { - continue; - } - for (size_t inode = 0; inode < get_chan_width(side_manager.get_side()) - 1; ++inode) { - if ( (get_chan_node_segment(side_manager.get_side(), inode) != get_chan_node_segment(side_manager.get_side(), inode + 1)) - || ( inode == get_chan_width(side_manager.get_side()) - 2) ) { - /* Record the upper bound */ - if ( inode == get_chan_width(side_manager.get_side()) - 2) { - rotate_end = get_chan_width(side_manager.get_side()) - 1; - } else { - rotate_end = inode; - } - /* Make sure offset is in range */ - /* skip this side if there is no nodes */ - if (0 >= rotate_end - rotate_begin) { - /* Update the lower bound */ - rotate_begin = inode + 1; - continue; - } - assert(offset < rotate_end - rotate_begin + 1); - /* Find a group split, rotate */ - chan_node_[side].rotate(rotate_begin, rotate_end, offset); - std::rotate(chan_node_direction_[side].begin() + rotate_begin, - chan_node_direction_[side].begin() + rotate_begin + offset, - chan_node_direction_[side].begin() + rotate_end); - /* Update the lower bound */ - rotate_begin = inode + 1; - } - } - - } - - return; -} - -/* rotate one side of the opin nodes by a given offset - * OPIN nodes are divided into different groups depending on their grid - * each group is rotated separatedly - */ -void RRGSB::rotate_side_opin_node_in_group(enum e_side side, size_t offset) { - /* Rotate opin nodes on each side */ - Side side_manager(side); - size_t rotate_begin = 0; - size_t rotate_end = 0; - /* skip this side if there is no nodes */ - if (0 == get_num_opin_nodes(side)) { - return; - } - /* Partition the opin nodes on this side, depending on grids */ - for (size_t inode = 0; inode < get_num_opin_nodes(side) - 1; ++inode) { - if ( ( (opin_node_[side_manager.to_size_t()][inode]->xlow != opin_node_[side_manager.to_size_t()][inode + 1]->xlow) - || (opin_node_[side_manager.to_size_t()][inode]->ylow != opin_node_[side_manager.to_size_t()][inode + 1]->ylow) - || (opin_node_[side_manager.to_size_t()][inode]->xhigh != opin_node_[side_manager.to_size_t()][inode + 1]->xhigh) - || (opin_node_[side_manager.to_size_t()][inode]->yhigh != opin_node_[side_manager.to_size_t()][inode + 1]->yhigh) - || (opin_node_grid_side_[side_manager.to_size_t()][inode] != opin_node_grid_side_[side_manager.to_size_t()][inode + 1])) - || ( inode == get_num_opin_nodes(side) - 2) ) { - /* Record the upper bound */ - if ( inode == get_num_opin_nodes(side) - 2) { - rotate_end = get_num_opin_nodes(side) - 1; - } else { - rotate_end = inode; - } - /* skip this side if there is no nodes */ - if (0 >= rotate_end - rotate_begin) { - /* Update the lower bound */ - rotate_begin = inode + 1; - continue; - } - size_t adapt_offset = offset % (rotate_end - rotate_begin + 1); - /* Make sure offset is in range */ - assert (adapt_offset < rotate_end - rotate_begin + 1); - /* Find a group split, rotate */ - std::rotate(opin_node_[side_manager.to_size_t()].begin() + rotate_begin, - opin_node_[side_manager.to_size_t()].begin() + rotate_begin + adapt_offset, - opin_node_[side_manager.to_size_t()].begin() + rotate_end); - std::rotate(opin_node_grid_side_[side_manager.to_size_t()].begin() + rotate_begin, - opin_node_grid_side_[side_manager.to_size_t()].begin() + rotate_begin + adapt_offset, - opin_node_grid_side_[side_manager.to_size_t()].begin() + rotate_end); - /* Update the lower bound */ - rotate_begin = inode + 1; - } - } - - return; -} - - -/* rotate all the opin nodes by a given offset - * OPIN nodes are divided into different groups depending on their grid - * each group is rotated separatedly - */ -void RRGSB::rotate_opin_node_in_group(size_t offset) { - /* Rotate opin nodes on each side */ - for (size_t side = 0; side < get_num_sides(); ++side) { - Side side_manager(side); - rotate_side_opin_node_in_group(side_manager.get_side(), offset); - } - - return; -} - -/* rotate all the channel and opin nodes by a given offset */ -void RRGSB::rotate(size_t offset) { - rotate_chan_node(offset); - rotate_opin_node_in_group(offset); - return; -} - -/* rotate one side of the channel and opin nodes by a given offset */ -void RRGSB::rotate_side(enum e_side side, size_t offset) { - rotate_side_chan_node(side, offset); - rotate_side_opin_node_in_group(side, offset); - return; -} - -/* Mirror the node direction and port direction of routing track nodes on a side */ -void RRGSB::mirror_side_chan_node_direction(enum e_side side) { - assert(validate_side(side)); - Side side_manager(side); - - chan_node_[side_manager.to_size_t()].mirror_node_direction(); - return; -} - -/* swap the chan rr_nodes on two sides */ -void RRGSB::swap_chan_node(enum e_side src_side, enum e_side des_side) { - Side src_side_manager(src_side); - Side des_side_manager(des_side); - std::swap(chan_node_[src_side_manager.to_size_t()], - chan_node_[des_side_manager.to_size_t()]); - std::swap(chan_node_direction_[src_side_manager.to_size_t()], - chan_node_direction_[des_side_manager.to_size_t()]); - return; -} - -/* swap the OPIN rr_nodes on two sides */ -void RRGSB::swap_opin_node(enum e_side src_side, enum e_side des_side) { - Side src_side_manager(src_side); - Side des_side_manager(des_side); - std::swap(opin_node_[src_side_manager.to_size_t()], - opin_node_[des_side_manager.to_size_t()]); - std::swap(opin_node_grid_side_[src_side_manager.to_size_t()], - opin_node_grid_side_[des_side_manager.to_size_t()]); - return; -} - -/* swap the IPIN rr_nodes on two sides */ -void RRGSB::swap_ipin_node(enum e_side src_side, enum e_side des_side) { - Side src_side_manager(src_side); - Side des_side_manager(des_side); - std::swap(ipin_node_[src_side_manager.to_size_t()], - ipin_node_[des_side_manager.to_size_t()]); - std::swap(ipin_node_grid_side_[src_side_manager.to_size_t()], - ipin_node_grid_side_[des_side_manager.to_size_t()]); - return; -} - -/* Reverse the vector of the OPIN rr_nodes on a side */ -void RRGSB::reverse_opin_node(enum e_side side) { - Side side_manager(side); - std::reverse(opin_node_[side_manager.to_size_t()].begin(), - opin_node_[side_manager.to_size_t()].end()); - std::reverse(opin_node_grid_side_[side_manager.to_size_t()].begin(), - opin_node_grid_side_[side_manager.to_size_t()].end()); - return; -} - -/* Reverse the vector of the OPIN rr_nodes on a side */ -void RRGSB::reverse_ipin_node(enum e_side side) { - Side side_manager(side); - std::reverse(ipin_node_[side_manager.to_size_t()].begin(), - ipin_node_[side_manager.to_size_t()].end()); - std::reverse(ipin_node_grid_side_[side_manager.to_size_t()].begin(), - ipin_node_grid_side_[side_manager.to_size_t()].end()); - return; -} - -/* Reset the RRGSB to pristine state */ -void RRGSB::clear() { - /* Clean all the vectors */ - assert(validate_num_sides()); - /* Clear the inner vector of each matrix */ - for (size_t side = 0; side < get_num_sides(); ++side) { - chan_node_direction_[side].clear(); - chan_node_[side].clear(); - ipin_node_[side].clear(); - ipin_node_grid_side_[side].clear(); - opin_node_[side].clear(); - opin_node_grid_side_[side].clear(); - } - chan_node_direction_.clear(); - chan_node_.clear(); - ipin_node_.clear(); - ipin_node_grid_side_.clear(); - opin_node_.clear(); - opin_node_grid_side_.clear(); - - /* Just to make the lsb and msb invalidate */ - sb_conf_port_.reset(); - cbx_conf_port_.reset(); - cby_conf_port_.reset(); - - return; -} - -/* Clean the chan_width of a side */ -void RRGSB::clear_chan_nodes(enum e_side node_side) { - Side side_manager(node_side); - assert(validate_side(node_side)); - - chan_node_[side_manager.to_size_t()].clear(); - chan_node_direction_[side_manager.to_size_t()].clear(); - return; -} - -/* Clean the number of IPINs of a side */ -void RRGSB::clear_ipin_nodes(enum e_side node_side) { - Side side_manager(node_side); - assert(validate_side(node_side)); - - ipin_node_[side_manager.to_size_t()].clear(); - ipin_node_grid_side_[side_manager.to_size_t()].clear(); - return; -} - -/* Clean the number of OPINs of a side */ -void RRGSB::clear_opin_nodes(enum e_side node_side) { - Side side_manager(node_side); - assert(validate_side(node_side)); - - opin_node_[side_manager.to_size_t()].clear(); - opin_node_grid_side_[side_manager.to_size_t()].clear(); - return; -} - -/* Clean chan/opin/ipin nodes at one side */ -void RRGSB::clear_one_side(enum e_side node_side) { - clear_chan_nodes(node_side); - clear_ipin_nodes(node_side); - clear_opin_nodes(node_side); - - return; -} - - -/* Internal functions for validation */ - -/* check if two rr_nodes have a similar set of drive_rr_nodes - * for each drive_rr_node: - * 1. CHANX or CHANY: should have the same side and index - * 2. OPIN or IPIN: should have the same side and index - * 3. each drive_rr_switch should be the same - */ -bool RRGSB::is_sb_node_mirror(const RRGSB& cand, - enum e_side node_side, - size_t track_id) const { - /* Ensure rr_nodes are either the output of short-connection or multiplexer */ - t_rr_node* node = this->get_chan_node(node_side, track_id); - t_rr_node* cand_node = cand.get_chan_node(node_side, track_id); - bool is_short_conkt = this->is_sb_node_passing_wire(node_side, track_id); - - if (is_short_conkt != cand.is_sb_node_passing_wire(node_side, track_id)) { - return false; - } - - if (true == is_short_conkt) { - /* Since, both are pass wires, - * The two node should be equivalent - * we can return here - */ - return true; - } - - /* For non-passing wires, check driving rr_nodes */ - if ( node->num_drive_rr_nodes != cand_node->num_drive_rr_nodes ) { - return false; - } - for (size_t inode = 0; inode < size_t(node->num_drive_rr_nodes); ++inode) { - /* node type should be the same */ - if ( node->drive_rr_nodes[inode]->type - != cand_node->drive_rr_nodes[inode]->type) { - return false; - } - /* switch type should be the same */ - if ( node->drive_switches[inode] - != cand_node->drive_switches[inode]) { - return false; - } - int src_node_id, des_node_id; - enum e_side src_node_side, des_node_side; - this->get_node_side_and_index(node->drive_rr_nodes[inode], OUT_PORT, &src_node_side, &src_node_id); - cand.get_node_side_and_index(cand_node->drive_rr_nodes[inode], OUT_PORT, &des_node_side, &des_node_id); - if (src_node_id != des_node_id) { - return false; - } - if (src_node_side != des_node_side) { - return false; - } - } - - return true; -} - -/* check if two ipin_nodes have a similar set of drive_rr_nodes - * for each drive_rr_node: - * 1. CHANX or CHANY: should have the same side and index - * 2. each drive_rr_switch should be the same - */ -bool RRGSB::is_cb_node_mirror(const RRGSB& cand, t_rr_type cb_type, - enum e_side node_side, - size_t node_id) const { - /* Ensure rr_nodes are either the output of short-connection or multiplexer */ - t_rr_node* node = this->get_ipin_node(node_side, node_id); - t_rr_node* cand_node = cand.get_ipin_node(node_side, node_id); - - if ( node->num_drive_rr_nodes != cand_node->num_drive_rr_nodes ) { - return false; - } - for (size_t inode = 0; inode < size_t(node->num_drive_rr_nodes); ++inode) { - /* node type should be the same */ - if ( node->drive_rr_nodes[inode]->type - != cand_node->drive_rr_nodes[inode]->type) { - return false; - } - /* switch type should be the same */ - if ( node->drive_switches[inode] - != cand_node->drive_switches[inode]) { - return false; - } - - int src_node_id, des_node_id; - enum e_side src_node_side, des_node_side; - enum e_side chan_side = get_cb_chan_side(cb_type); - switch (node->drive_rr_nodes[inode]->type) { - case CHANX: - case CHANY: - /* if the drive rr_nodes are routing tracks, find index */ - src_node_id = this->get_chan_node_index(chan_side, node->drive_rr_nodes[inode]); - des_node_id = cand.get_chan_node_index(chan_side, cand_node->drive_rr_nodes[inode]); - break; - case OPIN: - this->get_node_side_and_index(node->drive_rr_nodes[inode], OUT_PORT, &src_node_side, &src_node_id); - cand.get_node_side_and_index(cand_node->drive_rr_nodes[inode], OUT_PORT, &des_node_side, &des_node_id); - if (src_node_side != des_node_side) { - return false; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of drive_rr_nodes for ipin_node!\n", - __FILE__, __LINE__); - exit(1); - } - if (src_node_id != des_node_id) { - return false; - } - } - - return true; -} - -size_t RRGSB::get_track_id_first_short_connection(enum e_side node_side) const { - assert(validate_side(node_side)); - - /* Walk through chan_nodes and find the first short connection */ - for (size_t inode = 0; inode < get_chan_width(node_side); ++inode) { - if (true == is_sb_node_passing_wire(node_side, inode)) { - return inode; - } - } - - return size_t(-1); -} - -/* Validate if the number of sides are consistent among internal data arrays ! */ -bool RRGSB::validate_num_sides() const { - size_t num_sides = chan_node_direction_.size(); - - if ( num_sides != chan_node_.size() ) { - return false; - } - - if ( num_sides != ipin_node_.size() ) { - return false; - } - - if ( num_sides != ipin_node_grid_side_.size() ) { - return false; - } - - if ( num_sides != opin_node_.size() ) { - return false; - } - - if ( num_sides != opin_node_grid_side_.size() ) { - return false; - } - - return true; -} - -/* Check if the side valid in the context: does the switch block have the side? */ -bool RRGSB::validate_side(enum e_side side) const { - Side side_manager(side); - if ( side_manager.to_size_t() < get_num_sides() ) { - return true; - } - return false; -} - -/* Check the track_id is valid for chan_node_ and chan_node_direction_ */ -bool RRGSB::validate_track_id(enum e_side side, size_t track_id) const { - Side side_manager(side); - - if (false == validate_side(side)) { - return false; - } - if ( ( track_id < chan_node_[side_manager.to_size_t()].get_chan_width()) - && ( track_id < chan_node_direction_[side_manager.to_size_t()].size()) ) { - return true; - } - - return false; -} - -/* Check the opin_node_id is valid for opin_node_ and opin_node_grid_side_ */ -bool RRGSB::validate_opin_node_id(enum e_side side, size_t node_id) const { - Side side_manager(side); - - if (false == validate_side(side)) { - return false; - } - if ( ( node_id < opin_node_[side_manager.to_size_t()].size()) - &&( node_id < opin_node_grid_side_[side_manager.to_size_t()].size()) ) { - return true; - } - - return false; -} - -/* Check the ipin_node_id is valid for opin_node_ and opin_node_grid_side_ */ -bool RRGSB::validate_ipin_node_id(enum e_side side, size_t node_id) const { - Side side_manager(side); - - if (false == validate_side(side)) { - return false; - } - if ( ( node_id < ipin_node_[side_manager.to_size_t()].size()) - &&( node_id < ipin_node_grid_side_[side_manager.to_size_t()].size()) ) { - return true; - } - - return false; -} - -bool RRGSB::validate_cb_type(t_rr_type cb_type) const { - if ( (CHANX == cb_type) || (CHANY == cb_type) ) { - return true; - } - return false; -} - -/* Member Functions of Class RRChan */ -/* Accessors */ - -/* get the max coordinator of the switch block array */ -DeviceCoordinator DeviceRRGSB::get_gsb_range() const { - size_t max_y = 0; - /* Get the largest size of sub-arrays */ - for (size_t x = 0; x < rr_gsb_.size(); ++x) { - max_y = std::max(max_y, rr_gsb_[x].size()); - } - - DeviceCoordinator coordinator(rr_gsb_.size(), max_y); - return coordinator; -} - -/* Get a rr switch block in the array with a coordinator */ -const RRGSB DeviceRRGSB::get_gsb(const DeviceCoordinator& coordinator) const { - assert(validate_coordinator(coordinator)); - return rr_gsb_[coordinator.get_x()][coordinator.get_y()]; -} - -/* Get a rr switch block in the array with a coordinator */ -const RRGSB DeviceRRGSB::get_gsb(size_t x, size_t y) const { - DeviceCoordinator coordinator(x, y); - return get_gsb(coordinator); -} - -/* get the number of unique side modules of switch blocks */ -size_t DeviceRRGSB::get_num_sb_unique_submodule(enum e_side side, size_t seg_index) const { - Side side_manager(side); - assert(validate_side(side)); - assert(validate_segment_index(seg_index)); - return sb_unique_submodule_[side_manager.to_size_t()][seg_index].size(); -} - -/* get the number of unique mirrors of switch blocks */ -size_t DeviceRRGSB::get_num_cb_unique_module(t_rr_type cb_type) const { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return cbx_unique_module_.size(); - case CHANY: - return cby_unique_module_.size(); - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/* get the number of unique mirrors of switch blocks */ -size_t DeviceRRGSB::get_num_sb_unique_module() const { - return sb_unique_module_.size(); -} - -/* get the number of unique mirrors of switch blocks */ -size_t DeviceRRGSB::get_num_gsb_unique_module() const { - return gsb_unique_module_.size(); -} - - -/* Get the submodule id of a SB */ -size_t DeviceRRGSB::get_sb_unique_submodule_id(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const { - assert (validate_coordinator(coordinator)); - - Side side_manager(side); - assert (validate_side(side)); - assert (validate_segment_index(seg_id)); - - size_t x = coordinator.get_x(); - size_t y = coordinator.get_y(); - return sb_unique_submodule_id_[x][y][side][seg_id]; -} - -/* Get a rr switch block which is a unique module of a side of SB */ -const RRGSB DeviceRRGSB::get_sb_unique_submodule(size_t index, enum e_side side, size_t seg_id) const { - assert (validate_sb_unique_submodule_index(index, side, seg_id)); - - Side side_manager(side); - assert (validate_side(side)); - - size_t x = sb_unique_submodule_[side_manager.to_size_t()][seg_id][index].get_x(); - size_t y = sb_unique_submodule_[side_manager.to_size_t()][seg_id][index].get_y(); - - return rr_gsb_[x][y]; -} - -/* Get a rr switch block which is a unique module of a side of SB */ -const RRGSB DeviceRRGSB::get_sb_unique_submodule(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const { - assert (validate_coordinator(coordinator)); - - Side side_manager(side); - assert (validate_side(side)); - - size_t module_id = get_sb_unique_submodule_id(coordinator, side, seg_id); - - return get_sb_unique_submodule(module_id, side, seg_id); -} - - -/* Get a rr switch block which a unique mirror */ -const RRGSB DeviceRRGSB::get_sb_unique_module(size_t index) const { - assert (validate_sb_unique_module_index(index)); - - return rr_gsb_[sb_unique_module_[index].get_x()][sb_unique_module_[index].get_y()]; -} - -/* Get a rr switch block which a unique mirror */ -const RRGSB& DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, size_t index) const { - assert (validate_cb_unique_module_index(cb_type, index)); - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - return rr_gsb_[cbx_unique_module_[index].get_x()][cbx_unique_module_[index].get_y()]; - case CHANY: - return rr_gsb_[cby_unique_module_[index].get_x()][cby_unique_module_[index].get_y()]; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/* Give a coordinator of a rr switch block, and return its unique mirror */ -const RRGSB& DeviceRRGSB::get_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator) const { - assert (validate_cb_type(cb_type)); - assert(validate_coordinator(coordinator)); - size_t cb_unique_module_id; - - switch(cb_type) { - case CHANX: - cb_unique_module_id = cbx_unique_module_id_[coordinator.get_x()][coordinator.get_y()]; - break; - case CHANY: - cb_unique_module_id = cby_unique_module_id_[coordinator.get_x()][coordinator.get_y()]; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } - - return get_cb_unique_module(cb_type, cb_unique_module_id); -} - -/* Give a coordinator of a rr switch block, and return its unique mirror */ -const RRGSB DeviceRRGSB::get_sb_unique_module(const DeviceCoordinator& coordinator) const { - assert(validate_coordinator(coordinator)); - size_t sb_unique_module_id = sb_unique_module_id_[coordinator.get_x()][coordinator.get_y()]; - return get_sb_unique_module(sb_unique_module_id); -} - -/* Get the maximum number of sides across the switch blocks */ -size_t DeviceRRGSB::get_max_num_sides() const { - size_t max_num_sides = 0; - for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) { - for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) { - max_num_sides = std::max(max_num_sides, rr_gsb_[ix][iy].get_num_sides()); - } - } - return max_num_sides; -} - -/* Get the size of segment_ids */ -size_t DeviceRRGSB::get_num_segments() const { - return segment_ids_.size(); -} - -/* Get a segment id */ -size_t DeviceRRGSB::get_segment_id(size_t index) const { - assert(validate_segment_index(index)); - return segment_ids_[index]; -} - -/* Evaluate if the Switch Blocks of two GSBs share exactly the same submodule */ -bool DeviceRRGSB::is_two_sb_share_same_submodules(DeviceCoordinator& src, DeviceCoordinator& des) const { - - /* check the numbers of sides */ - if (get_gsb(src).get_num_sides() != get_gsb(des).get_num_sides()) { - return false; - } - - /* check the numbers/directionality of channel rr_nodes */ - for (size_t side = 0; side < get_gsb(src).get_num_sides(); ++side) { - Side side_manager(side); - for (size_t iseg = 0; iseg < get_num_segments(); ++iseg) { - if ( get_sb_unique_submodule_id(src, side_manager.get_side(), iseg) - != get_sb_unique_submodule_id(des, side_manager.get_side(), iseg)) { - return false; - } - } - } - return true; -} - -/* Public Mutators */ - -/* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ -void DeviceRRGSB::set_cb_num_reserved_conf_bits(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t num_reserved_conf_bits) { - assert(validate_coordinator(coordinator)); - rr_gsb_[coordinator.get_x()][coordinator.get_y()].set_cb_num_reserved_conf_bits(cb_type, num_reserved_conf_bits); - return; -} - -/* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ -void DeviceRRGSB::set_cb_conf_bits_lsb(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t conf_bits_lsb) { - assert(validate_coordinator(coordinator)); - rr_gsb_[coordinator.get_x()][coordinator.get_y()].set_cb_conf_bits_lsb(cb_type, conf_bits_lsb); - return; -} - -/* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ -void DeviceRRGSB::set_cb_conf_bits_msb(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t conf_bits_msb) { - assert(validate_coordinator(coordinator)); - rr_gsb_[coordinator.get_x()][coordinator.get_y()].set_cb_conf_bits_msb(cb_type, conf_bits_msb); - return; -} - - -/* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ -void DeviceRRGSB::set_sb_num_reserved_conf_bits(DeviceCoordinator& coordinator, size_t num_reserved_conf_bits) { - assert(validate_coordinator(coordinator)); - rr_gsb_[coordinator.get_x()][coordinator.get_y()].set_sb_num_reserved_conf_bits(num_reserved_conf_bits); - return; -} - -/* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ -void DeviceRRGSB::set_sb_conf_bits_lsb(DeviceCoordinator& coordinator, size_t conf_bits_lsb) { - assert(validate_coordinator(coordinator)); - rr_gsb_[coordinator.get_x()][coordinator.get_y()].set_sb_conf_bits_lsb(conf_bits_lsb); - return; -} - -/* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ -void DeviceRRGSB::set_sb_conf_bits_msb(DeviceCoordinator& coordinator, size_t conf_bits_msb) { - assert(validate_coordinator(coordinator)); - rr_gsb_[coordinator.get_x()][coordinator.get_y()].set_sb_conf_bits_msb(conf_bits_msb); - return; -} - -/* Pre-allocate the rr_switch_block array that the device requires */ -void DeviceRRGSB::reserve(DeviceCoordinator& coordinator) { - rr_gsb_.resize(coordinator.get_x()); - - gsb_unique_module_id_.resize(coordinator.get_x()); - - sb_unique_submodule_id_.resize(coordinator.get_x()); - sb_unique_module_id_.resize(coordinator.get_x()); - - cbx_unique_module_id_.resize(coordinator.get_x()); - cby_unique_module_id_.resize(coordinator.get_x()); - - for (size_t x = 0; x < coordinator.get_x(); ++x) { - rr_gsb_[x].resize(coordinator.get_y()); - - gsb_unique_module_id_[x].resize(coordinator.get_y()); - - sb_unique_submodule_id_[x].resize(coordinator.get_y()); - sb_unique_module_id_[x].resize(coordinator.get_y()); - - cbx_unique_module_id_[x].resize(coordinator.get_y()); - cby_unique_module_id_[x].resize(coordinator.get_y()); - } - - return; -} - -/* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ -void DeviceRRGSB::reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator) { - const RRGSB& rr_sb = get_gsb(coordinator); - sb_unique_submodule_id_[coordinator.get_x()][coordinator.get_y()].resize(rr_sb.get_num_sides()); - - for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { - Side side_manager(side); - sb_unique_submodule_id_[coordinator.get_x()][coordinator.get_y()][side_manager.to_size_t()].resize(segment_ids_.size()); - } - - return; -} - -/* Resize rr_switch_block array is needed*/ -void DeviceRRGSB::resize_upon_need(const DeviceCoordinator& coordinator) { - if (coordinator.get_x() + 1 > rr_gsb_.size()) { - rr_gsb_.resize(coordinator.get_x() + 1); - - sb_unique_submodule_id_.resize(coordinator.get_x() + 1); - sb_unique_module_id_.resize(coordinator.get_x() + 1); - - cbx_unique_module_id_.resize(coordinator.get_x() + 1); - cby_unique_module_id_.resize(coordinator.get_x() + 1); - } - - if (coordinator.get_y() + 1 > rr_gsb_[coordinator.get_x()].size()) { - rr_gsb_[coordinator.get_x()].resize(coordinator.get_y() + 1); - sb_unique_submodule_id_[coordinator.get_x()].resize(coordinator.get_y() + 1); - sb_unique_module_id_[coordinator.get_x()].resize(coordinator.get_y() + 1); - - cbx_unique_module_id_[coordinator.get_x()].resize(coordinator.get_y() + 1); - cby_unique_module_id_[coordinator.get_x()].resize(coordinator.get_y() + 1); - } - - return; -} - -/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ -void DeviceRRGSB::add_rr_gsb(const DeviceCoordinator& coordinator, - const RRGSB& rr_gsb) { - /* Resize upon needs*/ - resize_upon_need(coordinator); - - /* Add the switch block into array */ - rr_gsb_[coordinator.get_x()][coordinator.get_y()] = rr_gsb; - - return; -} - -/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ -void DeviceRRGSB::build_cb_unique_module(t_rr_type cb_type) { - /* Make sure a clean start */ - clear_cb_unique_module(cb_type); - - for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) { - for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) { - bool is_unique_module = true; - DeviceCoordinator gsb_coordinator(ix, iy); - - /* Bypass non-exist CB */ - if ( false == rr_gsb_[ix][iy].is_cb_exist(cb_type) ) { - continue; - } - - /* Traverse the unique_mirror list and check it is an mirror of another */ - for (size_t id = 0; id < get_num_cb_unique_module(cb_type); ++id) { - const RRGSB& unique_module = get_cb_unique_module(cb_type, id); - if (true == rr_gsb_[ix][iy].is_cb_mirror(unique_module, cb_type)) { - /* This is a mirror, raise the flag and we finish */ - is_unique_module = false; - /* Record the id of unique mirror */ - set_cb_unique_module_id(cb_type, gsb_coordinator, id); - break; - } - } - /* Add to list if this is a unique mirror*/ - if (true == is_unique_module) { - add_cb_unique_module(cb_type, gsb_coordinator); - /* Record the id of unique mirror */ - set_cb_unique_module_id(cb_type, gsb_coordinator, get_num_cb_unique_module(cb_type) - 1); - } - } - } - return; -} - - -/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ -void DeviceRRGSB::build_sb_unique_module() { - /* Make sure a clean start */ - clear_sb_unique_module(); - - /* Build the unique submodule */ - build_sb_unique_submodule(); - - for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) { - for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) { - bool is_unique_module = true; - DeviceCoordinator sb_coordinator(ix, iy); - - /* Traverse the unique_mirror list and check it is an mirror of another */ - for (size_t id = 0; id < get_num_sb_unique_module(); ++id) { - /* Check if the two modules have the same submodules, - * if so, these two modules are the same, indicating the sb is not unique. - * else the sb is unique - */ - if (true == is_two_sb_share_same_submodules(sb_unique_module_[id], sb_coordinator)) { - /* This is a mirror, raise the flag and we finish */ - is_unique_module = false; - /* Record the id of unique mirror */ - sb_unique_module_id_[ix][iy] = id; - break; - } - } - /* Add to list if this is a unique mirror*/ - if (true == is_unique_module) { - sb_unique_module_.push_back(sb_coordinator); - /* Record the id of unique mirror */ - sb_unique_module_id_[ix][iy] = sb_unique_module_.size() - 1; - } - } - } - return; -} - -/* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ -void DeviceRRGSB::build_sb_unique_submodule() { - /* Make sure a clean start */ - clear_sb_unique_submodule(); - - /* Allocate the unique_side_module_ */ - sb_unique_submodule_.resize(get_max_num_sides()); - for (size_t side = 0; side < sb_unique_submodule_.size(); ++side) { - sb_unique_submodule_[side].resize(segment_ids_.size()); - } - - for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) { - for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) { - DeviceCoordinator coordinator(ix, iy); - const RRGSB& rr_sb = rr_gsb_[ix][iy]; - - /* reserve the rr_sb_unique_module_id */ - reserve_sb_unique_submodule_id(coordinator); - - for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { - Side side_manager(side); - /* Try to add it to the list */ - add_sb_unique_side_submodule(coordinator, rr_sb, side_manager.get_side()); - } - } - } - return; -} - -void DeviceRRGSB::add_sb_unique_side_segment_submodule(DeviceCoordinator& coordinator, - const RRGSB& rr_sb, - enum e_side side, - size_t seg_id) { - bool is_unique_side_module = true; - Side side_manager(side); - - /* add rotatable mirror support */ - for (size_t id = 0; id < get_num_sb_unique_submodule(side, seg_id); ++id) { - /* Skip if these may never match as a mirror (violation in basic requirements */ - if (true == get_gsb(sb_unique_submodule_[side_manager.to_size_t()][seg_id][id]).is_sb_side_segment_mirror(rr_sb, side, segment_ids_[seg_id])) { - /* This is a mirror, raise the flag and we finish */ - is_unique_side_module = false; - /* Record the id of unique mirror */ - sb_unique_submodule_id_[coordinator.get_x()][coordinator.get_y()][side_manager.to_size_t()][seg_id] = id; - break; - } - } - - /* Add to list if this is a unique mirror*/ - if (true == is_unique_side_module) { - sb_unique_submodule_[side_manager.to_size_t()][seg_id].push_back(coordinator); - /* Record the id of unique mirror */ - sb_unique_submodule_id_[coordinator.get_x()][coordinator.get_y()][side_manager.to_size_t()][seg_id] = sb_unique_submodule_[side_manager.to_size_t()][seg_id].size() - 1; - /* - printf("Detect a rotatable mirror: SB[%lu][%lu]\n", coordinator.get_x(), coordinator.get_y()); - */ - } - - return; -} - -/* Find repeatable GSB block in the array */ -void DeviceRRGSB::build_gsb_unique_module() { - /* Make sure a clean start */ - clear_gsb_unique_module(); - - for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) { - for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) { - bool is_unique_module = true; - DeviceCoordinator gsb_coordinator(ix, iy); - - /* Traverse the unique_mirror list and check it is an mirror of another */ - for (size_t id = 0; id < get_num_gsb_unique_module(); ++id) { - /* We have alreay built sb and cb unique module list - * We just need to check if the unique module id of SBs, CBX and CBY are the same or not - */ - const DeviceCoordinator& gsb_unique_module_coordinator = gsb_unique_module_[id]; - if ((sb_unique_module_id_[ix][iy] == sb_unique_module_id_[gsb_unique_module_coordinator.get_x()][gsb_unique_module_coordinator.get_y()]) - && (cbx_unique_module_id_[ix][iy] == cbx_unique_module_id_[gsb_unique_module_coordinator.get_x()][gsb_unique_module_coordinator.get_y()]) - && (cby_unique_module_id_[ix][iy] == cby_unique_module_id_[gsb_unique_module_coordinator.get_x()][gsb_unique_module_coordinator.get_y()])) { - /* This is a mirror, raise the flag and we finish */ - is_unique_module = false; - /* Record the id of unique mirror */ - gsb_unique_module_id_[ix][iy] = id; - break; - } - } - /* Add to list if this is a unique mirror*/ - if (true == is_unique_module) { - add_gsb_unique_module(gsb_coordinator); - /* Record the id of unique mirror */ - gsb_unique_module_id_[ix][iy] = get_num_gsb_unique_module() - 1; - } - } - } - return; -} - - - -void DeviceRRGSB::build_unique_module() { - build_segment_ids(); - - build_sb_unique_module(); - - build_cb_unique_module(CHANX); - build_cb_unique_module(CHANY); - - build_gsb_unique_module(); - - return; -} - -/* Add a unique side module to the list: - * Check if the connections and nodes on the specified side of the rr_sb - * If it is similar to any module[side][i] in the list, we build a link from the rr_sb to the unique_module - * Otherwise, we add the module to the unique_module list - */ -void DeviceRRGSB::add_sb_unique_side_submodule(DeviceCoordinator& coordinator, - const RRGSB& rr_sb, - enum e_side side) { - Side side_manager(side); - - for (size_t iseg = 0; iseg < segment_ids_.size(); ++iseg) { - add_sb_unique_side_segment_submodule(coordinator, rr_sb, side, iseg); - } - - return; -} - -void DeviceRRGSB::add_gsb_unique_module(const DeviceCoordinator& coordinator) { - gsb_unique_module_.push_back(coordinator); - return; -} - -void DeviceRRGSB::add_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator) { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - cbx_unique_module_.push_back(coordinator); - return; - case CHANY: - cby_unique_module_.push_back(coordinator); - return; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -void DeviceRRGSB::set_cb_unique_module_id(t_rr_type cb_type, const DeviceCoordinator& coordinator, size_t id) { - assert (validate_cb_type(cb_type)); - size_t x = coordinator.get_x(); - size_t y = coordinator.get_y(); - switch(cb_type) { - case CHANX: - cbx_unique_module_id_[x][y] = id; - return; - case CHANY: - cby_unique_module_id_[x][y] = id; - return; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/* build a map of segment_ids */ -void DeviceRRGSB::build_segment_ids() { - - /* Make sure a clean start */ - clear_segment_ids(); - - /* go through each rr_sb, each side and find the segment_ids */ - for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) { - for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) { - RRGSB* rr_sb = &(rr_gsb_[ix][iy]); - for (size_t side = 0 ; side < rr_sb->get_num_sides(); ++side) { - Side side_manager(side); - /* get a list of segment_ids in this side */ - std::vector cur_seg_ids = rr_sb->get_chan(side_manager.get_side()).get_segment_ids(); - /* add to the segment_id_ if exist */ - for (size_t iseg = 0; iseg < cur_seg_ids.size(); ++iseg) { - std::vector::iterator it = std::find(segment_ids_.begin(), segment_ids_.end(), cur_seg_ids[iseg]); - /* find if it exists in the list */ - if (it != segment_ids_.end()) { - /* exist: continue */ - continue; - } - /* does not exist, push into the vector */ - segment_ids_.push_back(cur_seg_ids[iseg]); - } - } - } - } - return; -} - -/* clean the content */ -void DeviceRRGSB::clear() { - clear_gsb(); - - clear_gsb_unique_module(); - clear_gsb_unique_module_id(); - - /* clean unique module lists */ - clear_cb_unique_module(CHANX); - clear_cb_unique_module_id(CHANX); - - clear_cb_unique_module(CHANY); - clear_cb_unique_module_id(CHANY); - - clear_sb_unique_module(); - clear_sb_unique_module_id(); - - clear_sb_unique_submodule(); - clear_sb_unique_submodule_id(); - - return; -} - -void DeviceRRGSB::clear_gsb() { - /* clean gsb array */ - for (size_t x = 0; x < rr_gsb_.size(); ++x) { - rr_gsb_[x].clear(); - } - rr_gsb_.clear(); - return; -} - -void DeviceRRGSB::clear_gsb_unique_module_id() { - /* clean rr_switch_block array */ - for (size_t x = 0; x < rr_gsb_.size(); ++x) { - gsb_unique_module_id_[x].clear(); - } - return; -} - - -void DeviceRRGSB::clear_sb_unique_module_id() { - /* clean rr_switch_block array */ - for (size_t x = 0; x < rr_gsb_.size(); ++x) { - sb_unique_module_id_[x].clear(); - } - return; -} - -void DeviceRRGSB::clear_cb_unique_module_id(t_rr_type cb_type) { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - for (size_t x = 0; x < rr_gsb_.size(); ++x) { - cbx_unique_module_id_[x].clear(); - } - return; - case CHANY: - for (size_t x = 0; x < rr_gsb_.size(); ++x) { - cby_unique_module_id_[x].clear(); - } - return; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -void DeviceRRGSB::clear_sb_unique_submodule_id() { - /* clean rr_sb_unique_side_module_id */ - for (size_t x = 0; x < sb_unique_submodule_id_.size(); ++x) { - for (size_t y = 0; y < sb_unique_submodule_id_[x].size(); ++y) { - for (size_t side = 0; side < sb_unique_submodule_.size(); ++side) { - sb_unique_submodule_id_[x][y][side].clear(); - } - sb_unique_submodule_id_[x][y].clear(); - } - sb_unique_submodule_id_[x].clear(); - } - sb_unique_submodule_id_.clear(); - return; -} - -/* clean the content related to unique_mirrors */ -void DeviceRRGSB::clear_sb_unique_submodule() { - /* clean unique_side_module_ */ - for (size_t side = 0; side < sb_unique_submodule_.size(); ++side) { - for (size_t iseg = 0; iseg < segment_ids_.size(); ++iseg) { - sb_unique_submodule_[side][iseg].clear(); - } - sb_unique_submodule_[side].clear(); - } - - return; -} - -/* clean the content related to unique_mirrors */ -void DeviceRRGSB::clear_gsb_unique_module() { - /* clean unique mirror */ - gsb_unique_module_.clear(); - - return; -} - -/* clean the content related to unique_mirrors */ -void DeviceRRGSB::clear_sb_unique_module() { - /* clean unique mirror */ - sb_unique_module_.clear(); - - return; -} - -void DeviceRRGSB::clear_cb_unique_module(t_rr_type cb_type) { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - cbx_unique_module_.clear(); - return; - case CHANY: - cby_unique_module_.clear(); - return; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - - -/* clean the content related to segment_ids */ -void DeviceRRGSB::clear_segment_ids() { - /* clean segment_ids_ */ - segment_ids_.clear(); - - return; -} - - -/* Validate if the (x,y) is the range of this device */ -bool DeviceRRGSB::validate_coordinator(const DeviceCoordinator& coordinator) const { - if (coordinator.get_x() >= rr_gsb_.capacity()) { - return false; - } - if (coordinator.get_y() >= rr_gsb_[coordinator.get_x()].capacity()) { - return false; - } - return true; -} - -/* Validate if the (x,y) is the range of this device, but takes into consideration that edges are 1 off */ -bool DeviceRRGSB::validate_coordinator_edge(DeviceCoordinator& coordinator) const { - if (coordinator.get_x() >= rr_gsb_.capacity() + 1) { - return false; - } - if (coordinator.get_y() >= rr_gsb_[coordinator.get_x()].capacity() + 1) { - return false; - } - return true; -} - - -/* Validate if the index in the range of unique_mirror vector*/ -bool DeviceRRGSB::validate_side(enum e_side side) const { - Side side_manager(side); - if (side_manager.to_size_t() >= sb_unique_submodule_.size()) { - return false; - } - return true; -} - -/* Validate if the index in the range of unique_mirror vector*/ -bool DeviceRRGSB::validate_sb_unique_module_index(size_t index) const { - if (index >= sb_unique_module_.size()) { - return false; - } - return true; -} - -/* Validate if the index in the range of unique_mirror vector*/ -bool DeviceRRGSB::validate_sb_unique_submodule_index(size_t index, enum e_side side, size_t seg_index) const { - assert( validate_side(side)); - assert( validate_segment_index(seg_index)); - Side side_manager(side); - - if (index >= sb_unique_submodule_[side_manager.get_side()][seg_index].size()) { - return false; - } - return true; -} - -bool DeviceRRGSB::validate_cb_unique_module_index(t_rr_type cb_type, size_t index) const { - assert (validate_cb_type(cb_type)); - switch(cb_type) { - case CHANX: - if (index >= cbx_unique_module_.size()) { - return false; - } - return true; - case CHANY: - if (index >= cby_unique_module_.size()) { - return false; - } - return true; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of connection block!\n", - __FILE__, __LINE__); - exit(1); - } -} - -bool DeviceRRGSB::validate_segment_index(size_t index) const { - if (index >= segment_ids_.size()) { - return false; - } - return true; -} - -bool DeviceRRGSB::validate_cb_type(t_rr_type cb_type) const { - if ( (CHANX == cb_type) || (CHANY == cb_type) ) { - return true; - } - return false; -} - -/************************************************************************ - * End of file : rr_blocks.cpp - ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h deleted file mode 100644 index 125975da3..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h +++ /dev/null @@ -1,418 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: rr_blocks.h - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/06/12 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ - -/* IMPORTANT: - * The following preprocessing flags are added to - * avoid compilation error when this headers are included in more than 1 times - */ -#ifndef RR_BLOCKS_H -#define RR_BLOCKS_H - -/* - * Notes in include header files in a head file - * Only include the neccessary header files - * that is required by the data types in the function/class declarations! - */ -/* Header files should be included in a sequence */ -/* Standard header files required go first */ -#include - -#include "device_coordinator.h" -#include "device_port.h" -#include "vpr_types.h" - -/* RRChan coordinator class */ - -/* Object of a routing channel in a routing resource graph - * This is a collection of rr_nodes, which may be replaced with RRNodeId in new RRGraph - * Each routing channel is categorized in terms of directionality, - * being either X-direction or Y-direction - * ------------- ------ - * | | | | - * | | | Y | - * | CLB | | Chan | - * | | | | - * | | | | - * ------------- ------ - * ------------- - * | X | - * | Channel | - * ------------- - */ -class RRChan { - public: /* Constructors */ - RRChan(const RRChan&); /* Copy Constructor */ - RRChan(); - public: /* Accessors */ - t_rr_type get_type() const; - size_t get_chan_width() const; /* get the number of tracks in this channel */ - int get_node_track_id(t_rr_node* node) const; /* get the track_id of a node */ - t_rr_node* get_node(size_t track_num) const; /* get the rr_node with the track_id */ - int get_node_segment(t_rr_node* node) const; - int get_node_segment(size_t track_num) const; - bool is_mirror(const RRChan& cand) const; /* evaluate if two RR_chan is mirror to each other */ - std::vector get_segment_ids() const; /* Get a list of segments used in this routing channel */ - std::vector get_node_ids_by_segment_ids(size_t seg_id) const; /* Get a list of segments used in this routing channel */ - public: /* Mutators */ - void set(const RRChan&); /* copy */ - void set_type(t_rr_type type); /* modify type */ - void reserve_node(size_t node_size); /* reseve a number of nodes to the array */ - void add_node(t_rr_node* node, size_t node_segment); /* add a node to the array */ - void rotate(size_t rotate_begin, size_t rotate_end, size_t offset); /* rotate the nodes and node_segments with a given offset */ - void rotate_by_node_direction(enum e_direction node_direction, size_t offset); - void counter_rotate_by_node_direction(enum e_direction node_direction, size_t offset); - void rotate(size_t offset); /* rotate the nodes and node_segments with a given offset */ - void mirror_node_direction(); /* mirror node direction */ - void clear(); /* clear the content */ - private: /* internal functions */ - bool valid_type(t_rr_type type) const; - bool valid_node_type(t_rr_node* node) const; - bool valid_node_id(size_t node_id) const; - private: /* Internal Data */ - t_rr_type type_; /* channel type: CHANX or CHANY */ - std::vector nodes_; /* rr nodes of each track in the channel */ - std::vector node_segments_; /* segment of each track */ -}; - -/* Object including all the RR channels in a device, - * 1. the RR channels will be in an 2D array - * 2. Unique Module Name for each channel - * 3. Instance name for each channel - * 4. Detailed internal structure of each channel - * Considering RR channels may share the same structure - * To be memory efficient, we build a list of unique structures - * and link each RR channel to - */ -class DeviceRRChan { - public: /* contructor */ - public: /* Accessors */ - RRChan get_module(t_rr_type chan_type, size_t module_id) const; - RRChan get_module_with_coordinator(t_rr_type chan_type, size_t x, size_t y) const; - size_t get_num_modules(t_rr_type chan_type) const; - size_t get_module_id(t_rr_type chan_type, size_t x, size_t y) const; - public: /* Mutators */ - void init_module_ids(size_t device_height, size_t device_width); - void add_one_chan_module(t_rr_type chan_type, size_t x, size_t y, RRChan& rr_chan); /* Add a new unique module of RRChan*/ - void clear(); - private: /* internal functions */ - void clear_chan(t_rr_type chan_type); - void init_chan_module_ids(t_rr_type chan_type, size_t device_width, size_t device_height); - bool valid_chan_type(t_rr_type chan_type) const; - bool valid_coordinator(t_rr_type chan_type, size_t x, size_t y) const; - bool valid_module_id(t_rr_type chan_type, size_t module_id) const; - private: /* Internal Data */ - std::vector< std::vector > chanx_module_ids_; /* Module id in modules_ for each X-direction rr_channel */ - std::vector< std::vector > chany_module_ids_; /* Module id in modules_ for each Y-direction rr_channel */ - std::vector chanx_modules_; /* Detailed internal structure of each unique module */ - std::vector chany_modules_; /* Detailed internal structure of each unique module */ -}; - -/* Object Generic Switch Block - * This block contains - * 1. A switch block - * 2. A X-direction Connection block locates at the left side of the switch block - * 2. A Y-direction Connection block locates at the top side of the switch block - * This is a collection of rr_nodes, which may be replaced with RRNodeId in new RRGraph - * - * +---------------------------------+ - * | Y-direction CB | - * | [x][y + 1] | - * +---------------------------------+ - * - * TOP SIDE - * +-------------+ +---------------------------------+ - * | | | OPIN_NODE CHAN_NODES OPIN_NODES | - * | | | | - * | | | OPIN_NODES OPIN_NODES | - * | X-direction | | | - * | CB | LEFT SIDE | Switch Block | RIGHT SIDE - * | [x][y] | | [x][y] | - * | | | | - * | | | CHAN_NODES CHAN_NODES | - * | | | | - * | | | OPIN_NODES OPIN_NODES | - * | | | | - * | | | OPIN_NODE CHAN_NODES OPIN_NODES | - * +-------------+ +---------------------------------+ - * BOTTOM SIDE - * num_sides: number of sides of this switch block - * chan_rr_node: a collection of rr_nodes as routing tracks locating at each side of the Switch block <0..num_sides-1><0..chan_width-1> - * chan_rr_node_direction: Indicate if this rr_node is an input or an output of the Switch block <0..num_sides-1><0..chan_width-1> - * ipin_rr_node: a collection of rr_nodes as IPIN of a GRID locating at each side of the Switch block <0..num_sides-1><0..num_ipin_rr_nodes-1> - * ipin_rr_node_grid_side: specify the side of the input pins on which side of a GRID <0..num_sides-1><0..num_ipin_rr_nodes-1> - * opin_rr_node: a collection of rr_nodes as OPIN of a GRID locating at each side of the Switch block <0..num_sides-1><0..num_opin_rr_nodes-1> - * opin_rr_node_grid_side: specify the side of the output pins on which side of a GRID <0..num_sides-1><0..num_opin_rr_nodes-1> - * num_reserved_conf_bits: number of reserved configuration bits this switch block requires (mainly due to RRAM-based multiplexers) - * num_conf_bits: number of configuration bits this switch block requires - */ -class RRGSB { - public: /* Contructors */ - RRGSB(const RRGSB&);/* Copy constructor */ - RRGSB();/* Default constructor */ - public: /* Accessors */ - size_t get_num_sides() const; /* Get the number of sides of this SB */ - size_t get_chan_width(enum e_side side) const; /* Get the number of routing tracks on a side */ - size_t get_cb_chan_width(t_rr_type cb_type) const; /* Get the number of routing tracks of a X/Y-direction CB */ - std::vector get_cb_ipin_sides(t_rr_type cb_type) const; /* Get the sides of CB ipins in the array */ - size_t get_max_chan_width() const; /* Get the maximum number of routing tracks on all sides */ - enum PORTS get_chan_node_direction(enum e_side side, size_t track_id) const; /* Get the direction of a rr_node at a given side and track_id */ - RRChan get_chan(enum e_side side) const; /* get a rr_node at a given side and track_id */ - std::vector get_chan_segment_ids(enum e_side side) const; /* Get a list of segments used in this routing channel */ - std::vector get_chan_node_ids_by_segment_ids(enum e_side side, size_t seg_id) const; /* Get a list of segments used in this routing channel */ - t_rr_node* get_chan_node(enum e_side side, size_t track_id) const; /* get a rr_node at a given side and track_id */ - size_t get_chan_node_segment(enum e_side side, size_t track_id) const; /* get the segment id of a channel rr_node */ - size_t get_num_ipin_nodes(enum e_side side) const; /* Get the number of IPIN rr_nodes on a side */ - t_rr_node* get_ipin_node(enum e_side side, size_t node_id) const; /* get a rr_node at a given side and track_id */ - enum e_side get_ipin_node_grid_side(enum e_side side, size_t node_id) const; /* get a rr_node at a given side and track_id */ - enum e_side get_ipin_node_grid_side(t_rr_node* ipin_node) const; /* get a rr_node at a given side and track_id */ - size_t get_num_opin_nodes(enum e_side side) const; /* Get the number of OPIN rr_nodes on a side */ - t_rr_node* get_opin_node(enum e_side side, size_t node_id) const; /* get a rr_node at a given side and track_id */ - enum e_side get_opin_node_grid_side(enum e_side side, size_t node_id) const; /* get a rr_node at a given side and track_id */ - enum e_side get_opin_node_grid_side(t_rr_node* opin_node) const; /* get a rr_node at a given side and track_id */ - int get_cb_chan_node_index(t_rr_type cb_type, t_rr_node* node) const; - int get_chan_node_index(enum e_side node_side, t_rr_node* node) const; - int get_node_index(t_rr_node* node, enum e_side node_side, enum PORTS node_direction) const; /* Get the node index in the array, return -1 if not found */ - void get_node_side_and_index(t_rr_node* node, enum PORTS node_direction, enum e_side* node_side, int* node_index) const; /* Given a rr_node, try to find its side and index in the Switch block */ - bool is_sb_node_exist_opposite_side(t_rr_node* node, enum e_side node_side) const; /* Check if the node exist in the opposite side of this Switch Block */ - public: /* Accessors: get information about configuration ports */ - size_t get_sb_num_reserved_conf_bits() const; - size_t get_sb_reserved_conf_bits_lsb() const; - size_t get_sb_reserved_conf_bits_msb() const; - size_t get_sb_num_conf_bits() const; - size_t get_sb_conf_bits_lsb() const; - size_t get_sb_conf_bits_msb() const; - size_t get_cb_num_reserved_conf_bits(t_rr_type cb_type) const; - size_t get_cb_reserved_conf_bits_lsb(t_rr_type cb_type) const; - size_t get_cb_reserved_conf_bits_msb(t_rr_type cb_type) const; - size_t get_cb_num_conf_bits(t_rr_type cb_type) const; - size_t get_cb_conf_bits_lsb(t_rr_type cb_type) const; - size_t get_cb_conf_bits_msb(t_rr_type cb_type) const; - bool is_sb_node_passing_wire(const enum e_side node_side, const size_t track_id) const; /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */ - bool is_sb_side_mirror(const RRGSB& cand, enum e_side side) const; /* check if a side of candidate SB is a mirror of the current one */ - bool is_sb_side_segment_mirror(const RRGSB& cand, enum e_side side, size_t seg_id) const; /* check if all the routing segments of a side of candidate SB is a mirror of the current one */ - bool is_sb_mirror(const RRGSB& cand) const; /* check if the candidate SB is a mirror of the current one */ - bool is_sb_mirrorable(const RRGSB& cand) const; /* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */ - bool is_cb_mirror(const RRGSB& cand, t_rr_type cb_type) const; /* check if the candidate SB is a mirror of the current one */ - bool is_cb_exist(t_rr_type cb_type) const; /* check if the candidate SB is a mirror of the current one */ - size_t get_hint_rotate_offset(const RRGSB& cand) const; /* Determine an initial offset in rotating the candidate Switch Block to find a mirror matching*/ - public: /* Cooridinator conversion and output */ - size_t get_x() const; /* get the x coordinator of this switch block */ - size_t get_y() const; /* get the y coordinator of this switch block */ - size_t get_sb_x() const; /* get the x coordinator of this switch block */ - size_t get_sb_y() const; /* get the y coordinator of this switch block */ - DeviceCoordinator get_sb_coordinator() const; /* Get the coordinator of the SB */ - size_t get_cb_x(t_rr_type cb_type) const; /* get the x coordinator of this X/Y-direction block */ - size_t get_cb_y(t_rr_type cb_type) const; /* get the y coordinator of this X/Y-direction block */ - DeviceCoordinator get_cb_coordinator(t_rr_type cb_type) const; /* Get the coordinator of the X/Y-direction CB */ - enum e_side get_cb_chan_side(t_rr_type cb_type) const; /* get the side of a Connection block */ - enum e_side get_cb_chan_side(enum e_side ipin_side) const; /* get the side of a Connection block */ - DeviceCoordinator get_side_block_coordinator(enum e_side side) const; - DeviceCoordinator get_grid_coordinator() const; - public: /* Verilog writer */ - const char* gen_gsb_verilog_module_name() const; - const char* gen_gsb_verilog_instance_name() const; - const char* gen_sb_verilog_module_name() const; - const char* gen_sb_verilog_instance_name() const; - const char* gen_sb_verilog_side_module_name(enum e_side side, size_t seg_id) const; - const char* gen_sb_verilog_side_instance_name(enum e_side side, size_t seg_id) const; - const char* gen_cb_verilog_module_name(t_rr_type cb_type) const; - const char* gen_cb_verilog_instance_name(t_rr_type cb_type) const; - const char* gen_cb_verilog_routing_track_name(t_rr_type cb_type, size_t track_id) const; - public: /* Mutators */ - void set(const RRGSB& src); /* get a copy from a source */ - void set_coordinator(size_t x, size_t y); - void init_num_sides(size_t num_sides); /* Allocate the vectors with the given number of sides */ - void add_chan_node(enum e_side node_side, RRChan& rr_chan, std::vector rr_chan_dir); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */ - void add_ipin_node(t_rr_node* node, const enum e_side node_side, const enum e_side grid_side); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */ - void add_opin_node(t_rr_node* node, const enum e_side node_side, const enum e_side grid_side); /* Add a node to the chan_rr_node_ list and also assign its direction in chan_rr_node_direction_ */ - void set_sb_num_reserved_conf_bits(size_t num_reserved_conf_bits); - void set_sb_conf_bits_lsb(size_t conf_bits_lsb); - void set_sb_conf_bits_msb(size_t conf_bits_msb); - void set_cb_num_reserved_conf_bits(t_rr_type cb_type, size_t num_reserved_conf_bits); - void set_cb_conf_bits_lsb(t_rr_type cb_type, size_t conf_bits_lsb); - void set_cb_conf_bits_msb(t_rr_type cb_type, size_t conf_bits_msb); - void rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset); /* rotate all the channel nodes by a given offset */ - void counter_rotate_side_chan_node_by_direction(enum e_side side, enum e_direction chan_dir, size_t offset); /* rotate all the channel nodes by a given offset */ - void rotate_side_chan_node(enum e_side side, size_t offset); /* rotate all the channel nodes by a given offset */ - void rotate_chan_node(size_t offset); /* rotate all the channel nodes by a given offset */ - void rotate_chan_node_in_group(size_t offset); /* rotate all the channel nodes by a given offset */ - void rotate_side_opin_node_in_group(enum e_side side, size_t offset); /* rotate all the opin nodes by a given offset */ - void rotate_opin_node_in_group(size_t offset); /* rotate all the opin nodes by a given offset */ - void rotate_side(enum e_side side, size_t offset); /* rotate all the channel and opin nodes by a given offset */ - void rotate(size_t offset); /* rotate all the channel and opin nodes by a given offset */ - void swap_chan_node(enum e_side src_side, enum e_side des_side); /* swap the chan rr_nodes on two sides */ - void swap_opin_node(enum e_side src_side, enum e_side des_side); /* swap the OPIN rr_nodes on two sides */ - void swap_ipin_node(enum e_side src_side, enum e_side des_side); /* swap the IPIN rr_nodes on two sides */ - void reverse_opin_node(enum e_side side); /* reverse the OPIN rr_nodes on two sides */ - void reverse_ipin_node(enum e_side side); /* reverse the IPIN rr_nodes on two sides */ - public: /* Mutators: cleaners */ - void clear(); - void clear_chan_nodes(enum e_side node_side); /* Clean the chan_width of a side */ - void clear_ipin_nodes(enum e_side node_side); /* Clean the number of IPINs of a side */ - void clear_opin_nodes(enum e_side node_side); /* Clean the number of OPINs of a side */ - void clear_one_side(enum e_side node_side); /* Clean chan/opin/ipin nodes at one side */ - private: /* Internal Mutators */ - void mirror_side_chan_node_direction(enum e_side side); /* Mirror the node direction and port direction of routing track nodes on a side */ - private: /* internal functions */ - bool is_sb_node_mirror (const RRGSB& cand, enum e_side node_side, size_t track_id) const; - bool is_cb_node_mirror (const RRGSB& cand, t_rr_type cb_type, enum e_side node_side, size_t node_id) const; - size_t get_track_id_first_short_connection(enum e_side node_side) const; - bool validate_num_sides() const; - bool validate_side(enum e_side side) const; - bool validate_track_id(enum e_side side, size_t track_id) const; - bool validate_opin_node_id(enum e_side side, size_t node_id) const; - bool validate_ipin_node_id(enum e_side side, size_t node_id) const; - bool validate_cb_type(t_rr_type cb_type) const; - private: /* Internal Data */ - /* Coordinator */ - DeviceCoordinator coordinator_; - /* Routing channel data */ - std::vector chan_node_; - std::vector< std::vector > chan_node_direction_; - - /* Logic Block Inputs data */ - std::vector< std::vector > ipin_node_; - std::vector< std::vector > ipin_node_grid_side_; - - /* Logic Block Outputs data */ - std::vector< std::vector > opin_node_; - std::vector< std::vector > opin_node_grid_side_; - - /* Configuration bits */ - ConfPorts sb_conf_port_; - ConfPorts cbx_conf_port_; - ConfPorts cby_conf_port_; -}; - -/* Object Device Routing Resource Switch Block - * This includes: - * 1. a collection of RRSwitch blocks, each of which can be used to instance Switch blocks in the top-level netlists - * 2. a collection of unique mirrors of RRGSBs, which can be used to output Verilog / SPICE modules - * 3. a colleciton of unique rotatable of RRGSBs, which can be used to output Verilog / SPICE modules - * The rotatable RRGSBs are more generic mirrors, which allow SwitchBlocks to be wired by rotating the pins, - * further reduce the number of Verilog/SPICE modules outputted. This will lead to rapid layout generation - */ -class DeviceRRGSB { - public: /* Contructors */ - public: /* Accessors */ - DeviceCoordinator get_gsb_range() const; /* get the max coordinator of the switch block array */ - const RRGSB get_gsb(const DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */ - const RRGSB get_gsb(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */ - size_t get_num_gsb_unique_module() const; /* get the number of unique mirrors of GSB */ - size_t get_num_sb_unique_submodule(enum e_side side, size_t seg_index) const; /* get the number of unique mirrors of switch blocks */ - size_t get_num_sb_unique_module() const; /* get the number of unique mirrors of switch blocks */ - size_t get_num_cb_unique_module(t_rr_type cb_type) const; /* get the number of unique mirrors of CBs */ - size_t get_sb_unique_submodule_id(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const; - const RRGSB get_sb_unique_submodule(size_t index, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */ - const RRGSB get_sb_unique_submodule(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const; /* Get a rr switch block which a unique mirror */ - const RRGSB get_sb_unique_module(size_t index) const; /* Get a rr switch block which a unique mirror */ - const RRGSB get_sb_unique_module(const DeviceCoordinator& coordinator) const; /* Get a rr switch block which a unique mirror */ - const RRGSB& get_cb_unique_module(t_rr_type cb_type, size_t index) const; /* Get a rr switch block which a unique mirror */ - const RRGSB& get_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator) const; - size_t get_max_num_sides() const; /* Get the maximum number of sides across the switch blocks */ - size_t get_num_segments() const; /* Get the size of segment_ids */ - size_t get_segment_id(size_t index) const; /* Get a segment id */ - bool is_two_sb_share_same_submodules(DeviceCoordinator& src, DeviceCoordinator& des) const; - public: /* Mutators */ - void set_sb_num_reserved_conf_bits(DeviceCoordinator& coordinator, size_t num_reserved_conf_bits); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ - void set_sb_conf_bits_lsb(DeviceCoordinator& coordinator, size_t conf_bits_lsb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ - void set_sb_conf_bits_msb(DeviceCoordinator& coordinator, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ - void set_cb_num_reserved_conf_bits(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t num_reserved_conf_bits); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ - void set_cb_conf_bits_lsb(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t conf_bits_lsb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ - void set_cb_conf_bits_msb(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ - void reserve(DeviceCoordinator& coordinator); /* Pre-allocate the rr_switch_block array that the device requires */ - void reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ - void resize_upon_need(const DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */ - void add_rr_gsb(const DeviceCoordinator& coordinator, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ - void build_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ - void clear(); /* clean the content */ - private: /* Internal cleaners */ - void clear_gsb(); /* clean the content */ - void clear_cb_unique_module(t_rr_type cb_type); /* clean the content */ - void clear_cb_unique_module_id(t_rr_type cb_type); /* clean the content */ - void clear_sb_unique_module(); /* clean the content */ - void clear_sb_unique_module_id(); /* clean the content */ - void clear_sb_unique_submodule(); /* clean the content */ - void clear_sb_unique_submodule_id(); /* clean the content */ - void clear_gsb_unique_module(); /* clean the content */ - void clear_gsb_unique_module_id(); /* clean the content */ - void clear_segment_ids(); - private: /* Validators */ - bool validate_coordinator(const DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device */ - bool validate_coordinator_edge(DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device but takes into consideration the fact that edges are 1 off */ - bool validate_side(enum e_side side) const; /* validate if side is in the range of unique_side_module_ */ - bool validate_sb_unique_module_index(size_t index) const; /* Validate if the index in the range of unique_mirror vector*/ - bool validate_cb_unique_module_index(t_rr_type cb_type, size_t index) const; /* Validate if the index in the range of unique_mirror vector*/ - bool validate_sb_unique_submodule_index(size_t index, enum e_side side, size_t seg_index) const; /* Validate if the index in the range of unique_module vector */ - bool validate_segment_index(size_t index) const; - bool validate_cb_type(t_rr_type cb_type) const; - private: /* Internal builders */ - void build_segment_ids(); /* build a map of segment_ids */ - void add_gsb_unique_module(const DeviceCoordinator& coordinator); - void add_sb_unique_side_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side); - void add_sb_unique_side_segment_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side, size_t seg_id); - void add_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator); - void set_cb_unique_module_id(t_rr_type, const DeviceCoordinator& coordinator, size_t id); - void build_sb_unique_submodule(); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */ - void build_sb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ - void build_cb_unique_module(t_rr_type cb_type); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */ - void build_gsb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ - private: /* Internal Data */ - std::vector< std::vector > rr_gsb_; - - std::vector< std::vector > gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ - std::vector gsb_unique_module_; - - std::vector< std::vector > sb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ - std::vector sb_unique_module_; - - std::vector< std::vector< std::vector< std::vector > > > sb_unique_submodule_id_; /* A map from rr_switch_block to its unique_side_module [0..x][0..y][0..num_sides][num_seg-1]*/ - std::vector< std::vector > > sb_unique_submodule_; /* For each side of switch block, we identify a list of unique modules based on its connection. This is a matrix [0..num_sides-1][0..num_seg-1][0..num_module], num_sides will the max number of sides of all the rr_switch_blocks */ - - std::vector< std::vector > cbx_unique_module_id_; /* A map from rr_gsb to its unique mirror */ - std::vector cbx_unique_module_; /* For each side of connection block, we identify a list of unique modules based on its connection. This is a matrix [0..num_module] */ - - std::vector< std::vector > cby_unique_module_id_; /* A map from rr_gsb to its unique mirror */ - std::vector cby_unique_module_; /* For each side of connection block, we identify a list of unique modules based on its connection. This is a matrix [0..num_module] */ - - std::vector segment_ids_; -}; - -#endif - -/************************************************************************ - * End of file : rr_blocks.h - ***********************************************************************/ - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_naming.cpp deleted file mode 100644 index 2a7f86fb3..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_naming.cpp +++ /dev/null @@ -1,49 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include - -#include "rr_blocks_naming.h" - -char* convert_cb_type_to_string(t_rr_type chan_type) { - switch(chan_type) { - case CHANX: - return "cbx"; - case CHANY: - return "cby"; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of channel!\n", - __FILE__, __LINE__); - exit(1); - } -} - -char* convert_chan_type_to_string(t_rr_type chan_type) { - switch(chan_type) { - case CHANX: - return "chanx"; - case CHANY: - return "chany"; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid type of channel!\n", - __FILE__, __LINE__); - exit(1); - } -} - -char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction) { - switch(chan_rr_node_direction) { - case IN_PORT: - return "in"; - case OUT_PORT: - return "out"; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of port!\n", __FILE__, __LINE__); - exit(1); - } -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_naming.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_naming.h deleted file mode 100644 index 769f9b654..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_naming.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef RR_BLOCKS_NAMING -#define RR_BLOCKS_NAMING - -#include "vpr_types.h" - -char* convert_chan_type_to_string(t_rr_type chan_type); - -char* convert_cb_type_to_string(t_rr_type chan_type); - -char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction); - - -#endif - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp deleted file mode 100644 index 4066c3a63..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp +++ /dev/null @@ -1,358 +0,0 @@ -/******************************************************************** - * This file includes most utilized function for rr_block data structures - *******************************************************************/ -#include -#include - -#include "vtr_assert.h" -#include "vpr_types.h" -#include "mux_utils.h" -#include "fpga_x2p_types.h" -#include "rr_blocks_utils.h" - -/********************************************************************* - * This function will find the global ports required by a Connection Block - * module. It will find all the circuit models in the circuit library - * that may be included in the connection block - * Collect the global ports from the circuit_models and merge with the same name - ********************************************************************/ -std::vector find_connection_block_global_ports(const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const CircuitLibrary& circuit_lib, - const std::vector& switch_lib) { - std::vector sub_models; - /* Walk through the OUTPUT nodes at each side of a GSB, - * get the switch id of incoming edges - * and get the circuit model linked to the switch id - */ - std::vector cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type); - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - /* Find the size of routing multiplexers driving this IPIN node */ - int mux_size = rr_gsb.get_ipin_node(cb_ipin_side, inode)->fan_in; - /* Bypass fan_in == 1 or 0, they are not considered as routing multiplexers */ - if (2 > mux_size) { - continue; - } - /* Find the driver switch of the node */ - short driver_switch = rr_gsb.get_ipin_node(cb_ipin_side, inode)->drive_switches[DEFAULT_SWITCH_ID]; - /* Find the circuit model id of the driver switch */ - VTR_ASSERT( (size_t)driver_switch < switch_lib.size() ); - /* Get the model, and try to add to the sub_model list */ - CircuitModelId switch_circuit_model = switch_lib[driver_switch].circuit_model; - /* Make sure it is a valid id */ - VTR_ASSERT( CircuitModelId::INVALID() != switch_circuit_model ); - /* Get the model, and try to add to the sub_model list */ - if (sub_models.end() == std::find(sub_models.begin(), sub_models.end(), switch_circuit_model)) { - /* Not yet in the list, add it */ - sub_models.push_back(switch_circuit_model); - } - } - } - - std::vector global_ports; - /* Iterate over the model list, and add the global ports*/ - for (const auto& model : sub_models) { - std::vector temp_global_ports = circuit_lib.model_global_ports(model, true); - /* Add the temp_global_ports to the list to be returned, make sure we do not have any duplicated ports */ - for (const auto& port_candidate : temp_global_ports) { - if (global_ports.end() == std::find(global_ports.begin(), global_ports.end(), port_candidate)) { - /* Not yet in the list, add it */ - global_ports.push_back(port_candidate); - } - } - } - - return global_ports; -} - - -/********************************************************************* - * This function will find the global ports required by a Switch Block - * module. It will find all the circuit models in the circuit library - * that may be included in the Switch Block - * Collect the global ports from the circuit_models and merge with the same name - ********************************************************************/ -std::vector find_switch_block_global_ports(const RRGSB& rr_gsb, - const CircuitLibrary& circuit_lib, - const std::vector& switch_lib) { - std::vector sub_models; - /* Walk through the OUTPUT nodes at each side of a GSB, - * get the switch id of incoming edges - * and get the circuit model linked to the switch id - */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - continue; - } - /* Find the driver switch of the node */ - short driver_switch = rr_gsb.get_chan_node(side_manager.get_side(), itrack)->drive_switches[DEFAULT_SWITCH_ID]; - /* Find the circuit model id of the driver switch */ - VTR_ASSERT( (size_t)driver_switch < switch_lib.size() ); - /* Get the model, and try to add to the sub_model list */ - CircuitModelId switch_circuit_model = switch_lib[driver_switch].circuit_model; - /* Make sure it is a valid id */ - VTR_ASSERT( CircuitModelId::INVALID() != switch_circuit_model ); - /* Get the model, and try to add to the sub_model list */ - if (sub_models.end() == std::find(sub_models.begin(), sub_models.end(), switch_circuit_model)) { - /* Not yet in the list, add it */ - sub_models.push_back(switch_circuit_model); - } - } - } - - std::vector global_ports; - /* Iterate over the model list, and add the global ports*/ - for (const auto& model : sub_models) { - std::vector temp_global_ports = circuit_lib.model_global_ports(model, true); - /* Add the temp_global_ports to the list to be returned, make sure we do not have any duplicated ports */ - for (const auto& port_candidate : temp_global_ports) { - if (global_ports.end() == std::find(global_ports.begin(), global_ports.end(), port_candidate)) { - /* Not yet in the list, add it */ - global_ports.push_back(port_candidate); - } - } - } - - return global_ports; -} - -/********************************************************************* - * This function will find the number of multiplexers required by - * a connection Block module. - ********************************************************************/ -size_t find_connection_block_number_of_muxes(const RRGSB& rr_gsb, - const t_rr_type& cb_type) { - size_t num_muxes = 0; - - std::vector cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type); - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - /* Find the size of routing multiplexers driving this IPIN node */ - int mux_size = rr_gsb.get_ipin_node(cb_ipin_side, inode)->fan_in; - /* Bypass fan_in == 1 or 0, they are not considered as routing multiplexers */ - if (2 > mux_size) { - continue; - } - /* This means we need a multiplexer, update the counter */ - num_muxes++; - } - } - - return num_muxes; -} - -/********************************************************************* - * This function will find the number of multiplexers required by - * a Switch Block module. - ********************************************************************/ -size_t find_switch_block_number_of_muxes(const RRGSB& rr_gsb) { - size_t num_muxes = 0; - /* Walk through the OUTPUT nodes at each side of a GSB, - * get the switch id of incoming edges - * and get the circuit model linked to the switch id - */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - continue; - } - /* Check if this node is just a passing wire */ - if (true == rr_gsb.is_sb_node_passing_wire(side_manager.get_side(), itrack)) { - continue; - } - /* Check if this node has more than 2 drivers */ - if (2 > rr_gsb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes) { - continue; - } - /* This means we need a multiplexer, update the counter */ - num_muxes++; - } - } - return num_muxes; -} - -/********************************************************************* - * Find the number of configuration bits of a Connection Block - ********************************************************************/ -size_t find_connection_block_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - const RRGSB& rr_gsb, - const t_rr_type& cb_type) { - size_t num_conf_bits = 0; - - std::vector cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type); - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - /* Find the size of routing multiplexers driving this IPIN node */ - int mux_size = rr_gsb.get_ipin_node(cb_ipin_side, inode)->fan_in; - /* Bypass fan_in == 1 or 0, they are not considered as routing multiplexers */ - if (2 > mux_size) { - continue; - } - - /* Get the circuit model id of the routing multiplexer */ - size_t switch_index = rr_gsb.get_ipin_node(cb_ipin_side, inode)->drive_switches[DEFAULT_SWITCH_ID]; - CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - - /* Find the input size of the implementation of a routing multiplexer */ - size_t datapath_mux_size = rr_gsb.get_ipin_node(cb_ipin_side, inode)->fan_in; - /* Get the multiplexing graph from the Mux Library */ - MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); - const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); - num_conf_bits += find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); - } - } - - return num_conf_bits; -} - - -/********************************************************************* - * Find the number of configuration bits of a Switch Block - ********************************************************************/ -size_t find_switch_block_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - const RRGSB& rr_gsb) { - size_t num_conf_bits = 0; - - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - continue; - } - /* Check if this node is just a passing wire */ - if (true == rr_gsb.is_sb_node_passing_wire(side_manager.get_side(), itrack)) { - continue; - } - /* Check if this node has more than 2 drivers */ - if (2 > rr_gsb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes) { - continue; - } - /* Get the circuit model id of the routing multiplexer */ - size_t switch_index = rr_gsb.get_chan_node(side_manager.get_side(), itrack)->drive_switches[DEFAULT_SWITCH_ID]; - CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - - /* Find the input size of the implementation of a routing multiplexer */ - size_t datapath_mux_size = rr_gsb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes; - /* Get the multiplexing graph from the Mux Library */ - MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); - const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); - num_conf_bits += find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); - } - } - - return num_conf_bits; -} - -/********************************************************************* - * Find the number of shared configuration bits of a Connection Block - ********************************************************************/ -size_t find_connection_block_num_shared_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - const RRGSB& rr_gsb, - const t_rr_type& cb_type) { - size_t num_shared_conf_bits = 0; - - std::vector cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type); - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - /* Find the size of routing multiplexers driving this IPIN node */ - int mux_size = rr_gsb.get_ipin_node(cb_ipin_side, inode)->fan_in; - /* Bypass fan_in == 1 or 0, they are not considered as routing multiplexers */ - if (2 > mux_size) { - continue; - } - - /* Get the circuit model id of the routing multiplexer */ - size_t switch_index = rr_gsb.get_ipin_node(cb_ipin_side, inode)->drive_switches[DEFAULT_SWITCH_ID]; - CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - - /* Find the input size of the implementation of a routing multiplexer */ - size_t datapath_mux_size = rr_gsb.get_ipin_node(cb_ipin_side, inode)->fan_in; - /* Get the multiplexing graph from the Mux Library */ - MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); - const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); - num_shared_conf_bits += find_mux_num_shared_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); - } - } - - return num_shared_conf_bits; -} - -/********************************************************************* - * Find the number of shared configuration bits of a Switch Block - ********************************************************************/ -size_t find_switch_block_num_shared_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - const RRGSB& rr_gsb) { - size_t num_shared_conf_bits = 0; - - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - continue; - } - /* Check if this node is just a passing wire */ - if (true == rr_gsb.is_sb_node_passing_wire(side_manager.get_side(), itrack)) { - continue; - } - /* Check if this node has more than 2 drivers */ - if (2 > rr_gsb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes) { - continue; - } - /* Get the circuit model id of the routing multiplexer */ - size_t switch_index = rr_gsb.get_chan_node(side_manager.get_side(), itrack)->drive_switches[DEFAULT_SWITCH_ID]; - CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - - /* Find the input size of the implementation of a routing multiplexer */ - size_t datapath_mux_size = rr_gsb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes; - /* Get the multiplexing graph from the Mux Library */ - MuxId mux_id = mux_lib.mux_graph(mux_model, datapath_mux_size); - const MuxGraph& mux_graph = mux_lib.mux_graph(mux_id); - num_shared_conf_bits += find_mux_num_shared_config_bits(circuit_lib, mux_model, mux_graph, cur_sram_orgz_info->type); - } - } - - return num_shared_conf_bits; -} - -/******************************************************************** - * Find if a X-direction or Y-direction Connection Block contains - * routing tracks only (zero configuration bits and routing multiplexers) - *******************************************************************/ -bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb, - const t_rr_type& cb_type) { - bool routing_track_only = true; - - /* Find routing multiplexers on the sides of a Connection block where IPIN nodes locate */ - std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); - - for (size_t side = 0; side < cb_sides.size(); ++side) { - enum e_side cb_ipin_side = cb_sides[side]; - Side side_manager(cb_ipin_side); - if (0 < rr_gsb.get_num_ipin_nodes(cb_ipin_side)) { - routing_track_only = false; - break; - } - } - - return routing_track_only; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h deleted file mode 100644 index 59e8639ad..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.h +++ /dev/null @@ -1,57 +0,0 @@ -/******************************************************************** - * Header file for rr_block_utils.cpp - *******************************************************************/ -#ifndef RR_BLOCKS_UTILS_H -#define RR_BLOCKS_UTILS_H - -/* Include other header file required by the function declaration */ -#include -#include "physical_types.h" -#include "circuit_library.h" -#include "rr_blocks.h" -#include "mux_library.h" - -std::vector find_connection_block_global_ports(const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const CircuitLibrary& circuit_lib, - const std::vector& switch_lib); - -std::vector find_switch_block_global_ports(const RRGSB& rr_gsb, - const CircuitLibrary& circuit_lib, - const std::vector& switch_lib); - -size_t find_connection_block_number_of_muxes(const RRGSB& rr_gsb, - const t_rr_type& cb_type); - -size_t find_switch_block_number_of_muxes(const RRGSB& rr_gsb); - -size_t find_connection_block_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - const RRGSB& rr_gsb, - const t_rr_type& cb_type); - -size_t find_switch_block_num_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - const RRGSB& rr_gsb); - -size_t find_connection_block_num_shared_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - const RRGSB& rr_gsb, - const t_rr_type& cb_type); - -size_t find_switch_block_num_shared_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - const RRGSB& rr_gsb); - -bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb, - const t_rr_type& cb_type); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.cpp deleted file mode 100644 index ebc5a2aa9..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.cpp +++ /dev/null @@ -1,42 +0,0 @@ -/******************************************************************** - * This file include most utilized functions in generating simulations - * Note: function placed here MUST be generic enough for both SPICE - * and Verilog simulations! - *******************************************************************/ -#include - -#include "simulation_utils.h" - -/******************************************************************** - * Compute the time period for the simulation - *******************************************************************/ -int find_operating_phase_simulation_time(const int& factor, - const int& num_op_clock_cycles, - const float& op_clock_period, - const float& timescale) { - /* Take into account the prog_reset and reset cycles - * 1e9 is to change the unit to ns rather than second - */ - return (factor * num_op_clock_cycles * op_clock_period) / timescale; -} - -/******************************************************************** - * Find the the full time period of a simulation, including - * both the programming time and operating time - * This is a generic function that can be used to generate simulation - * time period for SPICE/Verilog simulators - *******************************************************************/ -float find_simulation_time_period(const float &time_unit, - const int &num_prog_clock_cycles, - const float &prog_clock_period, - const int &num_op_clock_cycles, - const float &op_clock_period) { - float total_time_period = 0.; - - /* Take into account the prog_reset and reset cycles */ - total_time_period = (num_prog_clock_cycles + 2) * prog_clock_period + num_op_clock_cycles * op_clock_period; - total_time_period = total_time_period / time_unit; - - return total_time_period; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.h deleted file mode 100644 index 545c634ee..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/simulation_utils.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef SIMULATION_UTILS_H -#define SIMULATION_UTILS_H - -int find_operating_phase_simulation_time(const int& factor, - const int& num_op_clock_cycles, - const float& op_clock_period, - const float& timescale); - -float find_simulation_time_period(const float &time_unit, - const int &num_prog_clock_cycles, - const float &prog_clock_period, - const int &num_op_clock_cycles, - const float &op_clock_period); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.cpp deleted file mode 100644 index beeddd6c8..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.cpp +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Output internal structure of classes defined in rr_blocks.h to XML format - */ -#include -#include -#include -#include - -#include "rr_blocks.h" -#include "rr_blocks_naming.h" - -#include "write_rr_blocks.h" - -void write_rr_switch_block_to_xml(std::string fname_prefix, RRGSB& rr_gsb) { - /* Prepare file name */ - std::string fname(fname_prefix); - fname += rr_gsb.gen_gsb_verilog_module_name(); - fname += ".xml"; - - vpr_printf(TIO_MESSAGE_INFO, "Output SB XML: %s\r", fname.c_str()); - - /* Create a file handler*/ - std::fstream fp; - /* Open a file */ - fp.open(fname, std::fstream::out | std::fstream::trunc); - - /* Output location of the Switch Block */ - fp << "" << std::endl; - - /* Output each side */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side gsb_side_manager(side); - enum e_side gsb_side = gsb_side_manager.get_side(); - - /* Output IPIN nodes */ - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(gsb_side); ++inode) { - t_rr_node* cur_rr_node = rr_gsb.get_ipin_node(gsb_side, inode); - /* General information of this IPIN */ - fp << "\t<" << rr_node_typename[cur_rr_node->type] - << " side=\"" << gsb_side_manager.to_string() - << "\" index=\"" << inode - << "\" mux_size=\"" << cur_rr_node->num_drive_rr_nodes - << "\">" - << std::endl; - /* General information of each driving nodes */ - for (int jnode = 0; jnode < cur_rr_node->num_drive_rr_nodes; ++jnode) { - enum e_side chan_side = rr_gsb.get_cb_chan_side(gsb_side); - Side chan_side_manager(chan_side); - - /* For channel node, we do not know the node direction - * But we are pretty sure it is either IN_PORT or OUT_PORT - * So we just try and find what is valid - */ - int drive_node_index = rr_gsb.get_chan_node_index(chan_side, cur_rr_node->drive_rr_nodes[jnode]); - /* We must have a valide node index */ - assert (-1 != drive_node_index); - - size_t des_segment_id = rr_gsb.get_chan_node_segment(chan_side, drive_node_index); - - fp << "\t\tdrive_rr_nodes[jnode]->type] - << "\" side=\"" << chan_side_manager.to_string() - << "\" index=\"" << drive_node_index - << "\" segment_id=\"" << des_segment_id - << "\"/>" - << std::endl; - } - fp << "\ttype] - << ">" - << std::endl; - } - - /* Output chan nodes */ - for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { - /* We only care OUT_PORT */ - if (OUT_PORT != rr_gsb.get_chan_node_direction(gsb_side, inode)) { - continue; - } - /* Output drivers */ - size_t num_drive_rr_nodes = 0; - t_rr_node** drive_rr_nodes = 0; - t_rr_node* cur_rr_node = rr_gsb.get_chan_node(gsb_side, inode); - - /* Output node information: location, index, side */ - size_t src_segment_id = rr_gsb.get_chan_node_segment(gsb_side, inode); - - /* Check if this node is directly connected to the node on the opposite side */ - if (true == rr_gsb.is_sb_node_passing_wire(gsb_side, inode)) { - num_drive_rr_nodes = 0; - drive_rr_nodes = NULL; - } else { - num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes; - drive_rr_nodes = cur_rr_node->drive_rr_nodes; - } - - fp << "\t<" << rr_node_typename[cur_rr_node->type] - << " side=\"" << gsb_side_manager.to_string() - << "\" index=\"" << inode - << "\" segment_id=\"" << src_segment_id - << "\" mux_size=\"" << num_drive_rr_nodes - << "\">" - << std::endl; - - /* Direct connection: output the node on the opposite side */ - if (0 == num_drive_rr_nodes) { - Side oppo_side = gsb_side_manager.get_opposite(); - fp << "\t\ttype] - << "\" side=\"" << oppo_side.to_string() - << "\" index=\"" << rr_gsb.get_node_index(cur_rr_node, oppo_side.get_side(), IN_PORT) - << "\" segment_id=\"" << src_segment_id - << "\"/>" - << std::endl; - } else { - for (size_t jnode = 0; jnode < num_drive_rr_nodes; ++jnode) { - enum e_side drive_node_side = NUM_SIDES; - int drive_node_index = -1; - rr_gsb.get_node_side_and_index(drive_rr_nodes[jnode], IN_PORT, &drive_node_side, &drive_node_index); - if (-1 == drive_node_index) - assert(-1 != drive_node_index); - Side drive_side(drive_node_side); - - if (OPIN == drive_rr_nodes[jnode]->type) { - Side grid_side(rr_gsb.get_opin_node_grid_side(drive_node_side, drive_node_index)); - fp << "\t\t" - << std::endl; - } else { - size_t des_segment_id = rr_gsb.get_chan_node_segment(drive_node_side, drive_node_index); - fp << "\t\ttype] - << "\" side=\"" << drive_side.to_string() - << "\" index=\"" << drive_node_index - << "\" segment_id=\"" << des_segment_id - << "\"/>" - << std::endl; - } - } - } - fp << "\ttype) - << ">" - << std::endl; - } - } - - fp << "" - << std::endl; - - /* close a file */ - fp.close(); - - return; -} - -/* Output each rr_switch_block to a XML file */ -void write_device_rr_gsb_to_xml(char* sb_xml_dir, - DeviceRRGSB& LL_device_rr_gsb) { - std::string fname_prefix(sb_xml_dir); - /* Add slash if needed */ - if ('/' != fname_prefix.back()) { - fname_prefix += '/'; - } - - DeviceCoordinator sb_range = LL_device_rr_gsb.get_gsb_range(); - - /* For each switch block, an XML file will be outputted */ - for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - RRGSB rr_gsb = LL_device_rr_gsb.get_gsb(ix, iy); - write_rr_switch_block_to_xml(fname_prefix, rr_gsb); - } - } - - return; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.h deleted file mode 100644 index 803b9aa5e..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/write_rr_blocks.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef WRITE_RR_BLOCKS_H -#define WRITE_RR_BLOCKS_H - -void write_rr_switch_block_to_xml(std::string fname_prefix, RRGSB& rr_gsb); - -void write_device_rr_gsb_to_xml(char* sb_xml_dir, DeviceRRGSB& LL_device_rr_gsb); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.cpp deleted file mode 100644 index cdcfe164c..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.cpp +++ /dev/null @@ -1,143 +0,0 @@ -/******************************************************************** - * This file includes functions that output bitstream database - * to files in different formats - *******************************************************************/ -#include -#include -#include - -#include "vtr_assert.h" -#include "util.h" - -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -#include "bitstream_manager_utils.h" -#include "bitstream_writer.h" - -/******************************************************************** - * This function write header information to a bitstream file - *******************************************************************/ -static -void write_bitstream_xml_file_head(std::fstream& fp) { - check_file_handler(fp); - - auto end = std::chrono::system_clock::now(); - std::time_t end_time = std::chrono::system_clock::to_time_t(end); - - fp << "" << std::endl; - fp << std::endl; -} - -/******************************************************************** - * Recursively write the bitstream of a block to a xml file - * This function will use a Depth-First Search in outputting bitstream - * for each block - * 1. For block with bits as children, we will output the XML lines - * 2. For block without bits/child blocks, we can return - * 3. For block with child blocks, we visit each child recursively - *******************************************************************/ -static -void rec_write_block_bitstream_to_xml_file(std::fstream& fp, - const BitstreamManager& bitstream_manager, - const ConfigBlockId& block) { - check_file_handler(fp); - - /* Dive to child blocks if this block has any */ - for (const ConfigBlockId& child_block : bitstream_manager.block_children(block)) { - rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, child_block); - } - - if (0 == bitstream_manager.block_bits(block).size()) { - return; - } - - /* Write the bits of this block */ - fp << "" << std::endl; - - std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, block); - - /* Output hierarchy of this parent*/ - fp << "\t" << std::endl; - size_t hierarchy_counter = 0; - for (const ConfigBlockId& temp_block : block_hierarchy) { - fp << "\t\t" << std::endl; - hierarchy_counter++; - } - fp << "\t" << std::endl; - - /* Output child bits under this block */ - size_t bit_counter = 0; - fp << "\t" << std::endl; - for (const ConfigBitId& child_bit : bitstream_manager.block_bits(block)) { - fp << "\t\t" << std::endl; - bit_counter++; - } - fp << "\t" << std::endl; - - fp << "" < top_block = find_bitstream_manager_top_blocks(bitstream_manager); - /* Make sure we have only 1 top block and its name matches the top module */ - VTR_ASSERT(1 == top_block.size()); - VTR_ASSERT(0 == top_block_name.compare(bitstream_manager.block_name(top_block[0]))); - - /* Write bitstream, block by block, in a recursive way */ - rec_write_block_bitstream_to_xml_file(fp, bitstream_manager, top_block[0]); - - /* Close file handler */ - fp.close(); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "Writing bitstream to file took %g seconds...\n", - run_time_sec); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.h deleted file mode 100644 index 5a645990d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/bitstream_writer.h +++ /dev/null @@ -1,13 +0,0 @@ -/******************************************************************** - * Header file for bitstream_writer.cpp - *******************************************************************/ -#ifndef BITSTREAM_WRITER_H -#define BITSTREAM_WRITER_H - -#include -#include "bitstream_manager.h" - -void write_arch_independent_bitstream_to_xml_file(const BitstreamManager& bitstream_manager, - const std::string& fname); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp deleted file mode 100644 index 4720c7bf4..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.cpp +++ /dev/null @@ -1,97 +0,0 @@ -/******************************************************************** - * This file includes functions to build bitstream from a mapped - * FPGA fabric. - * We decode the bitstream from configuration of routing multiplexers - * and Look-Up Tables (LUTs) which locate in CLBs and global routing architecture - *******************************************************************/ -#include -#include - -#include "vtr_assert.h" -#include "util.h" - -#include "fpga_x2p_naming.h" - -#include "build_grid_bitstream.h" -#include "build_routing_bitstream.h" -#include "build_device_bitstream.h" - -/******************************************************************** - * A top-level function to build a bistream from the FPGA device - * 1. It will organize the bitstream w.r.t. the hierarchy of module graphs - * describing the FPGA fabric - * 2. It will decode configuration bits from routing multiplexers used in - * global routing architecture - * 3. It will decode configuration bits from routing multiplexers and LUTs - * used in CLBs - * - * Note: this function create a bitstream which is binding to the module graphs - * of the FPGA fabric that FPGA-X2P generates! - * But it can be used to output a generic bitstream for VPR mapping FPGA - *******************************************************************/ -BitstreamManager build_device_bitstream(const t_vpr_setup& vpr_setup, - const t_arch& arch, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector& rr_switches, - t_rr_node* L_rr_node, - const DeviceRRGSB& L_device_rr_gsb) { - /* Check if the routing architecture we support*/ - if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { - vpr_printf(TIO_MESSAGE_ERROR, - "FPGA X2P only supports uni-directional routing architecture!\n"); - exit(1); - } - - /* We don't support mrFPGA */ -#ifdef MRFPGA_H - if (is_mrFPGA) { - vpr_printf(TIO_MESSAGE_ERROR, - "FPGA X2P does not support mrFPGA!\n"); - exit(1); - } -#endif - - /* Bistream builder formally starts*/ - vpr_printf(TIO_MESSAGE_INFO, "\nStart building fabric-independent bitstream for FPGA...\n"); - - /* Bitstream manager to be built */ - BitstreamManager bitstream_manager; - - /* Start time count */ - clock_t t_start = clock(); - - /* Assign the SRAM model applied to the FPGA fabric */ - VTR_ASSERT(NULL != arch.sram_inf.verilog_sram_inf_orgz); /* Check !*/ - t_spice_model* mem_model = arch.sram_inf.verilog_sram_inf_orgz->spice_model; - /* initialize the SRAM organization information struct */ - CircuitModelId sram_model = arch.spice->circuit_lib.model(mem_model->name); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - - /* Create the top-level block for bitstream - * This is related to the top-level module of fpga - */ - std::string top_block_name = generate_fpga_top_module_name(); - ConfigBlockId top_block = bitstream_manager.add_block(top_block_name); - - /* Create bitstream from grids */ - build_grid_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, device_size, grids); - - /* Create bitstream from routing architectures */ - build_routing_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, L_device_rr_gsb); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "Building bitstream took %g seconds\n", - run_time_sec); - - return bitstream_manager; -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.h deleted file mode 100644 index 58afd42fb..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_device_bitstream.h +++ /dev/null @@ -1,26 +0,0 @@ -/******************************************************************** - * Header file for build_device_bitstream.cpp - *******************************************************************/ -#ifndef BUILD_DEVICE_BITSTREAM_H -#define BUILD_DEVICE_BITSTREAM_H - -#include -#include "bitstream_manager.h" -#include "vpr_types.h" -#include "module_manager.h" -#include "circuit_library.h" -#include "mux_library.h" -#include "rr_blocks.h" - -BitstreamManager build_device_bitstream(const t_vpr_setup& vpr_setup, - const t_arch& arch, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector& rr_switches, - t_rr_node* L_rr_node, - const DeviceRRGSB& L_device_rr_gsb); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.cpp deleted file mode 100644 index b9fc3bbcb..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.cpp +++ /dev/null @@ -1,135 +0,0 @@ -/******************************************************************** - * This file includes functions to build fabric dependent bitstream - *******************************************************************/ -#include -#include -#include - -#include "vtr_assert.h" -#include "util.h" -#include "fpga_x2p_naming.h" - -#include "bitstream_manager_utils.h" -#include "build_fabric_bitstream.h" - -/******************************************************************** - * This function will walk through all the configurable children under a module - * in a recursive way, following a Depth-First Search (DFS) strategy - * For each configuration child, we use its instance name as a key to spot the - * configuration bits in bitstream manager. - * Note that it is guarentee that the instance name in module manager is - * consistent with the block names in bitstream manager - * We use this link to reorganize the bitstream in the sequence of memories as we stored - * in the configurable_children) and configurable_child_instances() of each module of module manager - *******************************************************************/ -static -void rec_build_module_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager, - const ConfigBlockId& parent_block, - const ModuleManager& module_manager, - const ModuleId& parent_module, - std::vector& fabric_bitstream) { - - /* Depth-first search: if we have any children in the parent_block, - * we dive to the next level first! - */ - if (0 < bitstream_manager.block_children(parent_block).size()) { - for (size_t child_id = 0; child_id < module_manager.configurable_children(parent_module).size(); ++child_id) { - ModuleId child_module = module_manager.configurable_children(parent_module)[child_id]; - size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id]; - /* Get the instance name and ensure it is not empty */ - std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance); - - /* Find the child block that matches the instance name! */ - ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name); - /* We must have one valid block id! */ - if (true != bitstream_manager.valid_block_id(child_block)) - VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block)); - - /* Go recursively */ - rec_build_module_fabric_dependent_bitstream(bitstream_manager, child_block, - module_manager, child_module, - fabric_bitstream); - } - /* Ensure that there should be no configuration bits in the parent block */ - VTR_ASSERT(0 == bitstream_manager.block_bits(parent_block).size()); - } - - /* Note that, reach here, it means that this is a leaf node. - * We add the configuration bits to the fabric_bitstream, - * And then, we can return - */ - for (const ConfigBitId& config_bit : bitstream_manager.block_bits(parent_block)) { - fabric_bitstream.push_back(config_bit); - } -} - -/******************************************************************** - * A top-level function re-organizes the bitstream for a specific - * FPGA fabric, where configuration bits are organized in the sequence - * that can be directly loaded to the FPGA configuration protocol. - * Support: - * 1. Configuration chain - * 2. Memory decoders - * This function does NOT modify the bitstream database - * Instead, it builds a vector of ids for configuration bits in bitstream manager - * - * This function can be called ONLY after the function build_device_bitstream() - * Note that this function does NOT decode bitstreams from circuit implementation - * It was done in the function build_device_bitstream() - *******************************************************************/ -std::vector build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager, - const ModuleManager& module_manager) { - std::vector fabric_bitstream; - - vpr_printf(TIO_MESSAGE_INFO, "\nBuilding fabric dependent bitstream...\n"); - - /* Start time count */ - clock_t t_start = clock(); - - /* Get the top module name in module manager, which is our starting point */ - std::string top_module_name = generate_fpga_top_module_name(); - ModuleId top_module = module_manager.find_module(top_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(top_module)); - - /* Find the top block in bitstream manager, which has not parents */ - std::vector top_block = find_bitstream_manager_top_blocks(bitstream_manager); - /* Make sure we have only 1 top block and its name matches the top module */ - VTR_ASSERT(1 == top_block.size()); - VTR_ASSERT(0 == top_module_name.compare(bitstream_manager.block_name(top_block[0]))); - - rec_build_module_fabric_dependent_bitstream(bitstream_manager, top_block[0], - module_manager, top_module, - fabric_bitstream); - - /* Time-consuming sanity check: Uncomment these codes only for debugging!!! - * Check which configuration bits are not touched - */ - /* - for (const ConfigBitId& config_bit : bitstream_manager.bits()) { - std::vector::iterator it = std::find(fabric_bitstream.begin(), fabric_bitstream.end(), config_bit); - if (it == fabric_bitstream.end()) { - std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, bitstream_manager.bit_parent_block(config_bit)); - std::string block_hierarchy_name; - for (const ConfigBlockId& temp_block : block_hierarchy) { - block_hierarchy_name += std::string("/") + bitstream_manager.block_name(temp_block); - } - vpr_printf(TIO_MESSAGE_INFO, - "bit (parent_block = %s) is not touched!\n", - block_hierarchy_name.c_str()); - } - } - */ - - /* Ensure our fabric bitstream is in the same size as device bistream */ - VTR_ASSERT(bitstream_manager.bits().size() == fabric_bitstream.size()); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "Building fabric dependent bitstream took %g seconds\n", - run_time_sec); - - return fabric_bitstream; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.h deleted file mode 100644 index 828b8e2de..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_fabric_bitstream.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef BUILD_FABRIC_BITSTREAM_H -#define BUILD_FABRIC_BITSTREAM_H - -#include -#include "bitstream_manager.h" -#include "module_manager.h" - -std::vector build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager, - const ModuleManager& module_manager); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp deleted file mode 100644 index 41cfa7d8d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.cpp +++ /dev/null @@ -1,753 +0,0 @@ -/******************************************************************** - * This file includes functions that are used for building bitstreams - * for grids (CLBs, heterogenerous blocks, I/Os, etc.) - *******************************************************************/ -#include - -#include "vtr_assert.h" -#include "vtr_vector.h" - -#include "util.h" -#include "mux_utils.h" -#include "vpr_types.h" -#include "globals.h" - -#include "circuit_library_utils.h" - -#include "fpga_x2p_reserved_words.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" - -#include "build_mux_bitstream.h" -#include "build_lut_bitstream.h" -#include "build_grid_bitstream.h" - -/******************************************************************** - * Decode mode bits "01..." to a bitstream vector - *******************************************************************/ -static -std::vector generate_mode_select_bitstream(const std::string& mode_bits) { - std::vector mode_select_bitstream; - - for (size_t i = 0; i < mode_bits.length(); ++i) { - /* Error out for unexpected bits */ - if ( ('0' != mode_bits[i]) && ('1' != mode_bits[i]) ) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid mode_bits(%s)!\n", - __FILE__, __LINE__, mode_bits.c_str()); - exit(1); - } - mode_select_bitstream.push_back('1' == mode_bits[i]); - } - - return mode_select_bitstream; -} - -/******************************************************************** - * Generate bitstream for a primitive node and add it to bitstream manager - *******************************************************************/ -static -void build_primitive_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - t_phy_pb* primitive_pb, - t_pb_type* primitive_pb_type) { - - /* Ensure a valid physical pritimive pb */ - if (NULL == primitive_pb_type) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid primitive_pb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Asserts */ - if (NULL != primitive_pb) { - VTR_ASSERT (primitive_pb->pb_graph_node->pb_type->phy_pb_type == primitive_pb_type); - } - - CircuitModelId primitive_model = primitive_pb_type->circuit_model; - VTR_ASSERT(CircuitModelId::INVALID() != primitive_model); - VTR_ASSERT( (SPICE_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) - || (SPICE_MODEL_HARDLOGIC == circuit_lib.model_type(primitive_model)) - || (SPICE_MODEL_FF == circuit_lib.model_type(primitive_model)) ); - - /* Find SRAM ports for mode-selection */ - std::vector primitive_mode_select_ports = find_circuit_mode_select_sram_ports(circuit_lib, primitive_model); - - /* We may have a port for mode select or not. */ - VTR_ASSERT( (0 == primitive_mode_select_ports.size()) - || (1 == primitive_mode_select_ports.size()) ); - - /* Generate bitstream for mode-select ports */ - if (0 == primitive_mode_select_ports.size()) { - return; /* Nothing to do, return directly */ - } - - std::vector mode_select_bitstream; - if (NULL != primitive_pb) { - mode_select_bitstream = generate_mode_select_bitstream(std::string(primitive_pb->mode_bits)); - } else { /* get default mode_bits */ - mode_select_bitstream = generate_mode_select_bitstream(std::string(primitive_pb_type->mode_bits)); - } - - /* Ensure the length of bitstream matches the side of memory circuits */ - std::vector sram_models = find_circuit_sram_models(circuit_lib, primitive_model); - VTR_ASSERT(1 == sram_models.size()); - std::string mem_block_name = generate_memory_module_name(circuit_lib, primitive_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX)); - ModuleId mem_module = module_manager.find_module(mem_block_name); - VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); - ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configuration_chain_data_out_name()); - VTR_ASSERT(mode_select_bitstream.size() == module_manager.module_port(mem_module, mem_out_port_id).get_width()); - - /* Create a block for the bitstream which corresponds to the memory module associated to the LUT */ - ConfigBlockId mem_block = bitstream_manager.add_block(mem_block_name); - bitstream_manager.add_child_block(parent_configurable_block, mem_block); - - /* Add the bitstream to the bitstream manager */ - for (const bool& bit : mode_select_bitstream) { - ConfigBitId config_bit = bitstream_manager.add_bit(bit); - /* Link the memory bits to the mux mem block */ - bitstream_manager.add_bit_to_block(mem_block, config_bit); - } -} - -/******************************************************************** - * Generate bitstream for a LUT and add it to bitstream manager - * This function supports both single-output and fracturable LUTs - *******************************************************************/ -static -void build_lut_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - t_phy_pb* lut_pb, - t_pb_type* lut_pb_type) { - - /* Ensure a valid physical pritimive pb */ - if (NULL == lut_pb_type) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid lut_pb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Asserts */ - if (NULL != lut_pb) { - VTR_ASSERT (lut_pb->pb_graph_node->pb_type->phy_pb_type == lut_pb_type); - } - - CircuitModelId lut_model = lut_pb_type->circuit_model; - VTR_ASSERT (CircuitModelId::INVALID() != lut_model); - VTR_ASSERT (SPICE_MODEL_LUT == circuit_lib.model_type(lut_model)); - - /* Find the input ports for LUT size, this is used to decode the LUT memory bits! */ - std::vector model_input_ports = circuit_lib.model_ports_by_type(lut_model, SPICE_MODEL_PORT_INPUT, true); - VTR_ASSERT(1 == model_input_ports.size()); - size_t lut_size = circuit_lib.port_size(model_input_ports[0]); - - /* Find SRAM ports for truth tables and mode-selection */ - std::vector lut_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, lut_model); - std::vector lut_mode_select_ports = find_circuit_mode_select_sram_ports(circuit_lib, lut_model); - /* We should always 1 regular sram port, where truth table is loaded to */ - VTR_ASSERT(1 == lut_regular_sram_ports.size()); - /* We may have a port for mode select or not. This depends on if the LUT is fracturable or not */ - VTR_ASSERT( (0 == lut_mode_select_ports.size()) - || (1 == lut_mode_select_ports.size()) ); - - std::vector lut_bitstream; - /* Generate bitstream for the LUT */ - if ( (NULL == lut_pb) - || ((NULL != lut_pb && 0 == lut_pb->num_logical_blocks)) ) { - /* An empty pb means that this is an unused LUT, - * we give an empty truth table, which are full of default values (defined by users) - */ - for (size_t i = 0; i < circuit_lib.port_size(lut_regular_sram_ports[0]); ++i) { - VTR_ASSERT( (0 == circuit_lib.port_default_value(lut_regular_sram_ports[0])) - || (1 == circuit_lib.port_default_value(lut_regular_sram_ports[0])) ); - lut_bitstream.push_back(1 == circuit_lib.port_default_value(lut_regular_sram_ports[0])); - } - } else { - VTR_ASSERT (NULL != lut_pb); - /* Pre-allocate truth tables for a LUT, - * Note: for fracturable LUTs, there could be several truth tables - * since multiple functions are mapped to the same LUT but to different outputs - */ - std::vector truth_tables; - truth_tables.resize(lut_pb->num_logical_blocks); - - /* Find truth tables and decode them one by one - * Fracturable LUT may have multiple truth tables, - * which should be grouped in a unique one - * And then we derive the truth table - */ - for (int i = 0; i < lut_pb->num_logical_blocks; ++i) { - int mapped_logical_block_index = lut_pb->logical_block[i]; - /* For wired LUT we provide a default truth table */ - if (TRUE == lut_pb->is_wired_lut[i]) { - /* Build a post-routing lut truth table */ - std::vector lut_pin_nets = find_mapped_lut_phy_pb_input_pin_vpack_net_num(lut_pb); - truth_tables[i] = build_post_routing_wired_lut_truth_table(lut_pb->rr_graph->rr_node[lut_pb->lut_output_pb_graph_pin[i]->rr_node_index_physical_pb].vpack_net_num, lut_pin_nets.size(), lut_pin_nets); - } else { - /* For regular LUTs, we generate the truth tables */ - VTR_ASSERT (FALSE == lut_pb->is_wired_lut[i]); - VTR_ASSERT (VPACK_COMB == logical_block[mapped_logical_block_index].type); - /* Get the mapped vpack_net_num of this physical LUT pb */ - std::vector lut_pin_nets = find_mapped_lut_phy_pb_input_pin_vpack_net_num(lut_pb); - /* Consider LUT pin remapping when assign lut truth tables */ - /* Match truth table and post-routing results */ - truth_tables[i] = build_post_routing_lut_truth_table(&logical_block[mapped_logical_block_index], - lut_pin_nets.size(), lut_pin_nets); - } - /* Adapt truth table for a fracturable LUT - * TODO: Determine fixed input bits for this truth table: - * 1. input bits within frac_level (all '-' if not specified) - * 2. input bits outside frac_level, decoded to its output mask (0 -> first part -> all '1') - */ - truth_tables[i] = adapt_truth_table_for_frac_lut(circuit_lib, lut_pb->lut_output_pb_graph_pin[i], - truth_tables[i]); - } - /* Find MUX graph correlated to the LUT */ - MuxId lut_mux_id = mux_lib.mux_graph(lut_model, (size_t)pow(2., lut_size)); - const MuxGraph& mux_graph = mux_lib.mux_graph(lut_mux_id); - /* Ensure the LUT MUX has the expected input and SRAM port sizes */ - VTR_ASSERT(mux_graph.num_memory_bits() == lut_size); - VTR_ASSERT(mux_graph.num_inputs() == (size_t)pow(2., lut_size)); - /* Generate LUT bitstream */ - lut_bitstream = build_frac_lut_bitstream(circuit_lib, mux_graph, - lut_pb, truth_tables, - circuit_lib.port_default_value(lut_regular_sram_ports[0])); - } - - /* Generate bitstream for mode-select ports */ - if (0 != lut_mode_select_ports.size()) { - std::vector mode_select_bitstream; - if (NULL != lut_pb) { - mode_select_bitstream = generate_mode_select_bitstream(std::string(lut_pb->mode_bits)); - } else { /* get default mode_bits */ - mode_select_bitstream = generate_mode_select_bitstream(std::string(lut_pb_type->mode_bits)); - } - /* Conjunct the mode-select bitstream to the lut bitstream */ - for (const bool& bit : mode_select_bitstream) { - lut_bitstream.push_back(bit); - } - } - - /* Ensure the length of bitstream matches the side of memory circuits */ - std::vector sram_models = find_circuit_sram_models(circuit_lib, lut_model); - VTR_ASSERT(1 == sram_models.size()); - std::string mem_block_name = generate_memory_module_name(circuit_lib, lut_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX)); - ModuleId mem_module = module_manager.find_module(mem_block_name); - VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); - ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configuration_chain_data_out_name()); - VTR_ASSERT(lut_bitstream.size() == module_manager.module_port(mem_module, mem_out_port_id).get_width()); - - /* Create a block for the bitstream which corresponds to the memory module associated to the LUT */ - ConfigBlockId mem_block = bitstream_manager.add_block(mem_block_name); - bitstream_manager.add_child_block(parent_configurable_block, mem_block); - - /* Add the bitstream to the bitstream manager */ - for (const bool& bit : lut_bitstream) { - ConfigBitId config_bit = bitstream_manager.add_bit(bit); - /* Link the memory bits to the mux mem block */ - bitstream_manager.add_bit_to_block(mem_block, config_bit); - } -} - - -/******************************************************************** - * This function generates bitstream for a programmable routing - * multiplexer which drives an output pin of physical_pb_graph_node and its the input_edges - * - * src_pb_graph_node.[in|out]_pins -----------------> des_pb_graph_node.[in|out]pins - * /|\ - * | - * input_pins, edges, output_pins - *******************************************************************/ -static -void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - t_pb_graph_pin* des_pb_graph_pin, - t_mode* physical_mode, - const int& path_id) { - /* 1. identify pin interconnection type, - * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) - * 3. Select and print the SPICE netlist - */ - int fan_in = 0; - t_interconnect* cur_interc = NULL; - find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, physical_mode, &cur_interc, &fan_in); - - if ((NULL == cur_interc) || (0 == fan_in)) { - /* No interconnection matched */ - return; - } - - enum e_interconnect interc_type = determine_actual_pb_interc_type(cur_interc, fan_in); - switch (interc_type) { - case DIRECT_INTERC: - /* Nothing to do, return */ - break; - case COMPLETE_INTERC: - case MUX_INTERC: { - /* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */ - CircuitModelId mux_model = cur_interc->circuit_model; - VTR_ASSERT(SPICE_MODEL_MUX == circuit_lib.model_type(mux_model)); - - /* Find the input size of the implementation of a routing multiplexer */ - size_t datapath_mux_size = fan_in; - VTR_ASSERT(true == valid_mux_implementation_num_inputs(datapath_mux_size)); - - /* Generate bitstream depend on both technology and structure of this MUX */ - std::vector mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id); - - /* Create the block denoting the memory instances that drives this node in physical_block */ - std::string mem_block_name = generate_pb_memory_instance_name(GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string("")); - ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name); - bitstream_manager.add_child_block(parent_configurable_block, mux_mem_block); - - /* Find the module in module manager and ensure the bitstream size matches! */ - std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); - ModuleId mux_mem_module = module_manager.find_module(mem_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module)); - ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name()); - VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width()); - - /* Add the bistream to the bitstream manager */ - for (const bool& bit : mux_bitstream) { - ConfigBitId config_bit = bitstream_manager.add_bit(bit); - /* Link the memory bits to the mux mem block */ - bitstream_manager.add_bit_to_block(mux_mem_block, config_bit); - } - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", - __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); - exit(1); - } -} - -/******************************************************************** - * This function generates bitstream for the programmable routing - * multiplexers in a pb_graph node - *******************************************************************/ -static -void build_physical_block_interc_port_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - t_pb_graph_node* physical_pb_graph_node, - t_phy_pb* physical_pb, - const e_spice_pb_port_type& pb_port_type, - t_mode* physical_mode) { - switch (pb_port_type) { - case SPICE_PB_PORT_INPUT: - for (int iport = 0; iport < physical_pb_graph_node->num_input_ports; ++iport) { - for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) { - /* If this is a idle block, we set 0 to the selected edge*/ - /* Get the selected edge of current pin*/ - int path_id; - if (NULL == physical_pb) { - path_id = DEFAULT_PATH_ID; - } else { - VTR_ASSERT(NULL != physical_pb); - t_rr_node* pb_rr_nodes = physical_pb->rr_graph->rr_node; - int node_index = physical_pb_graph_node->input_pins[iport][ipin].rr_node_index_physical_pb; - int prev_node = pb_rr_nodes[node_index].prev_node; - /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ - /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ - if (OPEN == prev_node) { - path_id = DEFAULT_PATH_ID; - } else { - /* Find the path_id */ - path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); - VTR_ASSERT(DEFAULT_PATH_ID != path_id); - } - /* TODO: This should be done outside this function! - * Path id for the sdc generation - */ - pb_rr_nodes[node_index].id_path = path_id; - } - build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block, - module_manager, circuit_lib, mux_lib, - &(physical_pb_graph_node->input_pins[iport][ipin]), - physical_mode, - path_id); - } - } - break; - case SPICE_PB_PORT_OUTPUT: - for (int iport = 0; iport < physical_pb_graph_node->num_output_ports; ++iport) { - for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) { - /* If this is a idle block, we set 0 to the selected edge*/ - /* Get the selected edge of current pin*/ - int path_id; - if (NULL == physical_pb) { - path_id = DEFAULT_PATH_ID; - } else { - VTR_ASSERT(NULL != physical_pb); - t_rr_node* pb_rr_nodes = physical_pb->rr_graph->rr_node; - int node_index = physical_pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; - int prev_node = pb_rr_nodes[node_index].prev_node; - /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ - /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ - if (OPEN == prev_node) { - path_id = DEFAULT_PATH_ID; - } else { - /* Find the path_id */ - path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); - VTR_ASSERT(DEFAULT_PATH_ID != path_id); - } - /* TODO: This should be done outside this function! - * Path id for the sdc generation - */ - pb_rr_nodes[node_index].id_path = path_id; - } - build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block, - module_manager, circuit_lib, mux_lib, - &(physical_pb_graph_node->output_pins[iport][ipin]), - physical_mode, - path_id); - } - } - break; - case SPICE_PB_PORT_CLOCK: - for (int iport = 0; iport < physical_pb_graph_node->num_clock_ports; ++iport) { - for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) { - /* If this is a idle block, we set 0 to the selected edge*/ - /* Get the selected edge of current pin*/ - int path_id; - if (NULL == physical_pb) { - path_id = DEFAULT_PATH_ID; - } else { - VTR_ASSERT(NULL != physical_pb); - t_rr_node* pb_rr_nodes = physical_pb->rr_graph->rr_node; - int node_index = physical_pb_graph_node->clock_pins[iport][ipin].rr_node_index_physical_pb; - int prev_node = pb_rr_nodes[node_index].prev_node; - /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ - /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ - if (OPEN == prev_node) { - path_id = DEFAULT_PATH_ID; - } else { - /* Find the path_id */ - path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); - VTR_ASSERT(DEFAULT_PATH_ID != path_id); - } - /* TODO: This should be done outside this function! - * Path id for the sdc generation - */ - pb_rr_nodes[node_index].id_path = path_id; - } - build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block, - module_manager, circuit_lib, mux_lib, - &(physical_pb_graph_node->clock_pins[iport][ipin]), - physical_mode, - path_id); - - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid pb port type!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * This function generates bitstream for the programmable routing - * multiplexers in a pb_graph node - *******************************************************************/ -static -void build_physical_block_interc_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - t_pb_graph_node* physical_pb_graph_node, - t_phy_pb* physical_pb, - const int& physical_mode_index) { - /* Check if the pb_graph node is valid or not */ - if (NULL == physical_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid physical_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Assign current mode */ - t_mode* physical_mode = &(physical_pb_graph_node->pb_type->modes[physical_mode_index]); - - /* We check output_pins of physical_pb_graph_node and its the input_edges - * Iterate over the interconnections between outputs of physical_pb_graph_node - * and outputs of child_pb_graph_node - * child_pb_graph_node.output_pins -----------------> physical_pb_graph_node.outpins - * /|\ - * | - * input_pins, edges, output_pins - */ - build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block, - module_manager, circuit_lib, mux_lib, - physical_pb_graph_node, physical_pb, - SPICE_PB_PORT_OUTPUT, physical_mode); - - /* We check input_pins of child_pb_graph_node and its the input_edges - * Iterate over the interconnections between inputs of physical_pb_graph_node - * and inputs of child_pb_graph_node - * physical_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins - * /|\ - * | - * input_pins, edges, output_pins - */ - for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ipb++) { - for (int jpb = 0; jpb < physical_mode->pb_type_children[ipb].num_pb; jpb++) { - t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][jpb]); - /* branch on empty pb */ - t_phy_pb* child_pb = NULL; - if (NULL != physical_pb) { - child_pb = &(physical_pb->child_pbs[ipb][jpb]); - } - /* For each child_pb_graph_node input pins*/ - build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block, - module_manager, circuit_lib, mux_lib, - child_pb_graph_node, child_pb, - SPICE_PB_PORT_INPUT, physical_mode); - /* For clock pins, we should do the same work */ - build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block, - module_manager, circuit_lib, mux_lib, - child_pb_graph_node, child_pb, - SPICE_PB_PORT_CLOCK, physical_mode); - } - } -} - - -/******************************************************************** - * This function generates bitstream for a physical block, which is - * a child block of a grid - * This function will follow a recursive way in generating bitstreams - * It will follow the same sequence in visiting all the sub blocks - * in a physical as we did during module generation - * - * Note: if you want to bind your bitstream with a FPGA fabric generated by FPGA-X2P - * Please follow the same sequence in visiting pb_graph nodes!!! - * For more details, you may refer to function rec_build_physical_block_modules() - *******************************************************************/ -static -void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const e_side& border_side, - t_phy_pb* physical_pb, - t_pb_graph_node* physical_pb_graph_node, - const size_t& pb_graph_node_index) { - /* Get the physical pb_type that is linked to the pb_graph node */ - t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; - - /* Find the mode that define_idle_mode*/ - int physical_mode_index = find_pb_type_physical_mode_index((*physical_pb_type)); - - /* Create a block for the physical block under the grid block in bitstream manager */ - std::string pb_block_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), border_side); - std::string pb_block_name = generate_physical_block_instance_name(pb_block_name_prefix, physical_pb_type, pb_graph_node_index); - ConfigBlockId pb_configurable_block = bitstream_manager.add_block(pb_block_name); - bitstream_manager.add_child_block(parent_configurable_block, pb_configurable_block); - - /* Recursively finish all the child pb_types*/ - if (false == is_primitive_pb_type(physical_pb_type)) { - for (int ipb = 0; ipb < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ipb) { - for (int jpb = 0; jpb < physical_pb_type->modes[physical_mode_index].pb_type_children[ipb].num_pb; ++jpb) { - t_phy_pb* child_pb = NULL; - /* Find the child pb that is mapped, and the mapping info is not stored in the physical mode ! */ - if (NULL != physical_pb) { - child_pb = get_phy_child_pb_for_phy_pb_graph_node(physical_pb, ipb, jpb); - } - /* Go recursively */ - rec_build_physical_block_bitstream(bitstream_manager, pb_configurable_block, - module_manager, circuit_lib, mux_lib, - border_side, - child_pb, - &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][jpb]), - jpb); - } - } - } - - /* Check if this has defined a spice_model*/ - if (true == is_primitive_pb_type(physical_pb_type)) { - switch (physical_pb_type->class_type) { - case LUT_CLASS: - /* Special case for LUT !!! - * Mapped logical block information is stored in child_pbs of this pb!!! - */ - build_lut_bitstream(bitstream_manager, pb_configurable_block, - module_manager, circuit_lib, mux_lib, - physical_pb, physical_pb_type); - break; - case LATCH_CLASS: - case UNKNOWN_CLASS: - case MEMORY_CLASS: - /* For other types of blocks, we can apply a generic therapy */ - build_primitive_bitstream(bitstream_manager, pb_configurable_block, - module_manager, circuit_lib, - physical_pb, physical_pb_type); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Unknown class type of pb_type(%s)!\n", - __FILE__, __LINE__, physical_pb_type->name); - exit(1); - } - /* Finish for primitive node, return */ - return; - } - - /* Generate the bitstream for the interconnection in this physical block */ - build_physical_block_interc_bitstream(bitstream_manager, pb_configurable_block, - module_manager, circuit_lib, mux_lib, - physical_pb_graph_node, physical_pb, physical_mode_index); -} - -/******************************************************************** - * This function generates bitstream for a grid, which could be a - * CLB, a heterogenerous block, an I/O, etc. - * Note that each grid may contain a number of physical blocks, - * this function will iterate over them - *******************************************************************/ -static -void build_physical_block_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& top_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector>& grids, - const vtr::Point& grid_coordinate, - const e_side& border_side) { - /* Create a block for the grid in bitstream manager */ - t_type_ptr grid_type = grids[grid_coordinate.x()][grid_coordinate.y()].type; - std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); - std::string grid_block_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name), - IO_TYPE == grid_type, border_side, grid_coordinate); - ConfigBlockId grid_configurable_block = bitstream_manager.add_block(grid_block_name); - bitstream_manager.add_child_block(top_block, grid_configurable_block); - - /* Iterate over the capacity of the grid */ - for (int z = 0; z < grids[grid_coordinate.x()][grid_coordinate.y()].type->capacity; ++z) { - /* Get the top-level node of the pb_graph */ - t_pb_graph_node* top_pb_graph_node = grid_type->pb_graph_head; - VTR_ASSERT(NULL != top_pb_graph_node); - - /* Check in all the mapped blocks(clustered logic block), there is a match x,y,z*/ - t_block* mapped_block = search_mapped_block(grid_coordinate.x(), grid_coordinate.y(), z); - t_phy_pb* top_pb = NULL; - if (NULL != mapped_block) { - top_pb = (t_phy_pb*)mapped_block->phy_pb; - VTR_ASSERT(NULL != top_pb); - } - - /* Recursively traverse the pb_graph and generate bitstream */ - rec_build_physical_block_bitstream(bitstream_manager, grid_configurable_block, - module_manager, circuit_lib, mux_lib, - border_side, - top_pb, top_pb_graph_node, z); - } -} - - -/******************************************************************** - * Top-level function of this file: - * Generate bitstreams for all the grids, including - * 1. core grids that sit in the center of the fabric - * 2. side grids (I/O grids) that sit in the borders for the fabric - *******************************************************************/ -void build_grid_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& top_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const vtr::Point& device_size, - const std::vector>& grids) { - - vpr_printf(TIO_MESSAGE_INFO, - "Generating bitstream for core grids...\n"); - - /* Generate bitstream for the core logic block one by one */ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grids[ix][iy].type) { - continue; - } - /* Skip height > 1 tiles (mostly heterogeneous blocks) */ - if (0 < grids[ix][iy].offset) { - continue; - } - /* We should not meet any I/O grid */ - VTR_ASSERT(IO_TYPE != grids[ix][iy].type); - /* Ensure a valid usage */ - VTR_ASSERT((0 == grids[ix][iy].usage)||(0 < grids[ix][iy].usage)); - /* Add a grid module to top_module*/ - vtr::Point grid_coord(ix, iy); - build_physical_block_bitstream(bitstream_manager, top_block, module_manager, - circuit_lib, mux_lib, grids, grid_coord, NUM_SIDES); - } - } - - vpr_printf(TIO_MESSAGE_INFO, - "Generating bitstream for I/O grids...\n"); - - /* Create the coordinate range for each side of FPGA fabric */ - std::vector io_sides{TOP, RIGHT, BOTTOM, LEFT}; - std::map>> io_coordinates; - - /* TOP side*/ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - io_coordinates[TOP].push_back(vtr::Point(ix, device_size.y() - 1)); - } - - /* RIGHT side */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - io_coordinates[RIGHT].push_back(vtr::Point(device_size.x() - 1, iy)); - } - - /* BOTTOM side*/ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - io_coordinates[BOTTOM].push_back(vtr::Point(ix, 0)); - } - - /* LEFT side */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - io_coordinates[LEFT].push_back(vtr::Point(0, iy)); - } - - /* Add instances of I/O grids to top_module */ - for (const e_side& io_side : io_sides) { - for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type) { - continue; - } - /* Skip height > 1 tiles (mostly heterogeneous blocks) */ - if (0 < grids[io_coordinate.x()][io_coordinate.y()].offset) { - continue; - } - /* We should not meet any I/O grid */ - VTR_ASSERT(IO_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type); - build_physical_block_bitstream(bitstream_manager, top_block, module_manager, - circuit_lib, mux_lib, grids, io_coordinate, io_side); - } - } -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.h deleted file mode 100644 index 3568e4f29..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_grid_bitstream.h +++ /dev/null @@ -1,22 +0,0 @@ -/******************************************************************** - * Header file for build_grid_bitstream.cpp - *******************************************************************/ -#ifndef BUILD_GRID_BITSTREAM_H -#define BUILD_GRID_BITSTREAM_H - -#include -#include "vtr_geometry.h" -#include "vpr_types.h" -#include "bitstream_manager.h" -#include "module_manager.h" -#include "circuit_library.h" -#include "mux_library.h" - -void build_grid_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& top_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const vtr::Point& device_size, - const std::vector>& grids); -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp deleted file mode 100644 index 207124c12..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.cpp +++ /dev/null @@ -1,527 +0,0 @@ -/********************************************************************* - * This file includes functions that are used for building bitstreams - * for Look-Up Tables - ********************************************************************/ -#include -#include - -#include "vtr_assert.h" -#include "util.h" -#include "vpr_types.h" -#include "string_token.h" - -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" - -#include "build_lut_bitstream.h" - -/******************************************************************** - * Adapt the truth table from the short-wire connection - * from the input nets of a LUT to an output of a LUT - * - * LUT - * +-------------+ - * lut_input--->|----+ | - * | | | - * | +------->|---> lut_output - * | | - * +-------------+ - * - * In this case, LUT is configured as a wiring module - * This function will generate a truth for the wiring LUT - * - * For example: - * The truth table of the case where the 3rd input of - * a 4-input LUT is wired to output - * - * --1- 1 - * - ********************************************************************/ -LutTruthTable build_post_routing_wired_lut_truth_table(const int& lut_output_vpack_net_num, - const size_t& lut_size, - const std::vector& lut_pin_vpack_net_num) { - LutTruthTable tt; - - /* There is always only one line in this truth table */ - tt.resize(1); - - /* Pre-allocate the truth table: - * Each truth table line is organized in BLIF format: - * |<---LUT size--->| - * < a string of 0 or 1> <0 or 1> - * The first of characters represent the input values of each LUT input - * Here, we add 2 characters, which denote the space and a digit (0|1) - * By default, we set all the inputs as don't care value '-' - * - * For more details, please refer to the BLIF format documentation - */ - tt[0].resize(lut_size, '-'); - /* Fill the truth table !!! */ - for (size_t inet = 0; inet < lut_size; ++inet) { - /* Find the vpack_num in the lut_input_pin, we fix it to be 1 */ - if (lut_output_vpack_net_num == lut_pin_vpack_net_num[inet]) { - tt[0][inet] = '1'; - } - } - tt[0] += std::string(" 1"); - - return tt; -} - -/******************************************************************** - * Provide the truth table of a mapped logical block - * 1. Reorgainze the truth table to be consistent with the mapped nets of a LUT - * 2. Allocate the truth table in a clean string and return - ********************************************************************/ -LutTruthTable build_post_routing_lut_truth_table(t_logical_block* mapped_logical_block, - const size_t& lut_size, - const std::vector& lut_pin_vpack_net_num) { - if (NULL == mapped_logical_block) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid mapped_logical_block!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Create a map between the lut net ids and logical block net ids */ - std::vector lut_to_lb_net_mapping(lut_size, OPEN); - /* Find nets mapped to a logical block */ - std::vector lb_pin_vpack_net_num = find_lut_logical_block_input_pin_vpack_net_num(mapped_logical_block); - /* Create a pin-to-pin net_num mapping */ - for (size_t inet = 0; inet < lut_size; ++inet) { - /* Bypass open nets */ - if (OPEN == lut_pin_vpack_net_num[inet]) { - continue; - } - VTR_ASSERT_SAFE (OPEN != lut_pin_vpack_net_num[inet]); - /* Find the position (offset) of each vpack_net_num in lb_pins */ - for (size_t jnet = 0; jnet < lb_pin_vpack_net_num.size(); ++jnet) { - if (lut_pin_vpack_net_num[inet] == lb_pin_vpack_net_num[jnet]) { - lut_to_lb_net_mapping[inet] = jnet; - break; - } - } - /* Not neccesary to find a one, some luts just share part of their pins */ - } - - /* Count the lines of truth table stored in the mapped logical block */ - struct s_linked_vptr* head = mapped_logical_block->truth_table; - - /* Convert the truth_tables stored in the mapped logical block */ - LutTruthTable truth_table; - - /* Handle the truth table pin remapping - * Note that we cannot simply copy the original truth table from the mapped logical block - * Due to the logic equivalence of LUT pins, the nets are not longer in the sequences - * that are defined in the original truth table - * An illustrative example: - * - * Original Truth Table Post VPR Truth Table - * - * +-------+ +-------+ - * net0 --->| | net1--->| | - * net1 --->| LUT | net0--->| LUT | - * ... | | ... | | - * +-------+ +-------+ - * - * Truth table line Truth table line - * .names net0 net1 out .names net1 net0 out - * 01 1 10 1 - */ - while (head) { - /* Cache a line of truth table */ - std::string tt_line; - - /* Reorganize the original truth table */ - for (size_t inet = 0; inet < lut_size; ++inet) { - /* Open net implies a don't care, or some nets are not in the list */ - if ( (OPEN == lut_pin_vpack_net_num[inet]) - || (OPEN == lut_to_lb_net_mapping[inet])) { - tt_line.push_back('-'); - continue; - } - /* Find the desired truth table bit */ - tt_line.push_back(((char*)(head->data_vptr))[lut_to_lb_net_mapping[inet]]); - } - - /* Copy the last two characters from original truth table, which is not changed even after VPR implementation */ - int lb_truth_table_size = strlen((char*)(head->data_vptr)); - tt_line += std::string((char*)(head->data_vptr) + lb_truth_table_size - 2, 2); - - /* Add the line to truth table */ - truth_table.push_back(tt_line); - - /* Go to next line */ - head = head->next; - } - - return truth_table; -} - - -/******************************************************************** - * Generate the mask bits for a truth table - * This function actually converts an integer to a binary vector - *******************************************************************/ -static -std::string generate_mask_bits(const size_t& mask_code, - const size_t& num_mask_bits) { - std::vector mask_bits(num_mask_bits, 0); - - /* Make sure we do not have any overflow! */ - VTR_ASSERT ( (mask_code < pow(2., num_mask_bits)) ); - - size_t temp = mask_code; - for (size_t i = 0; i < num_mask_bits; ++i) { - if (1 == temp % 2) { - mask_bits[i] = 1; /* Keep a good sequence of bits */ - } - temp = temp / 2; - } - - std::string mask_bits_str; - for (const size_t& mask_bit : mask_bits) { - VTR_ASSERT( 0 == mask_bit || 1 == mask_bit ); - if (0 == mask_bit) { - mask_bits_str.push_back('0'); - continue; - } - mask_bits_str.push_back('1'); - } - - return mask_bits_str; -} - -/******************************************************************** - * Adapt truth table for a fracturable LUT - * Determine fixed input bits for this truth table: - * 1. input bits within frac_level (all '-' if not specified) - * 2. input bits outside frac_level, decoded to its output mask (0 -> first part -> all '1') - * - * For example: - * A 4-input function is mapped to input[0..3] of a 6-input fracturable LUT - * Plus, it uses the 2nd output of the fracturable LUT - * The truth table of the 4-input function is - * 1001 1 - * while truth table of a 6-input LUT requires 6 characters - * Therefore, it must be adapted by adding mask bits, which are - * a number of fixed digits to configure the fracturable LUT to - * operate in a 4-input LUT mode - * The mask bits can be decoded from the index of output used in the fracturable LUT - * For the 2nd output, it will be '01', the binary representation of index '1' - * Now the truth table will be adapt to - * 100101 1 - * where the first 4 digits come from the original truth table - * the 2 following digits are mask bits - * - ********************************************************************/ -LutTruthTable adapt_truth_table_for_frac_lut(const CircuitLibrary& circuit_lib, - t_pb_graph_pin* lut_out_pb_graph_pin, - const LutTruthTable& truth_table) { - LutTruthTable adapt_truth_table; - - /* Find the output port of LUT that this logical block is mapped to */ - VTR_ASSERT(NULL != lut_out_pb_graph_pin); - /* find the corresponding SPICE model output port and assoicated lut_output_mask */ - CircuitPortId lut_model_output_port = lut_out_pb_graph_pin->port->circuit_model_port; - size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port); - - /* No adaption required for when the lut_frac_level is not set */ - if (size_t(OPEN) == lut_frac_level) { - return truth_table; - } - - /* Find the corresponding circuit model output port and assoicated lut_output_mask */ - size_t lut_output_mask = circuit_lib.port_lut_output_masks(lut_model_output_port)[lut_out_pb_graph_pin->pin_number]; - - /* Apply modification to the truth table */ - for (const std::string& tt_line : truth_table) { - /* Last two chars are fixed */ - size_t lut_size = tt_line.length() - 2; - /* Get the number of bits to be masked (modified) */ - int num_mask_bits = lut_size - lut_frac_level; - /* Check if we need to modify any bits */ - VTR_ASSERT(0 <= num_mask_bits); - if ( 0 == num_mask_bits ) { - /* No modification needed, push to adapted truth table */ - adapt_truth_table.push_back(tt_line); - continue; - } - /* Modify bits starting from lut_frac_level */ - /* Decode the lut_output_mask to LUT input codes */ - int temp = pow(2., num_mask_bits) - 1 - lut_output_mask; - std::string mask_bits_str = generate_mask_bits(temp, num_mask_bits); - /* Copy the bits to the truth table line */ - std::string adapt_tt_line = tt_line; - adapt_tt_line.replace(lut_frac_level, mask_bits_str.size(), mask_bits_str); - - /* Push to adapted truth table */ - adapt_truth_table.push_back(adapt_tt_line); - } - - return adapt_truth_table; -} - -/******************************************************************** - * Determine if the truth table of a LUT is a on-set or a off-set - *******************************************************************/ -static -bool lut_truth_table_use_on_set(const LutTruthTable& truth_table) { - bool on_set = false; - bool off_set = false; - - for (const std::string& tt_line : truth_table) { - switch (tt_line.back()) { - case '1': - on_set = true; - break; - case '0': - off_set = true; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid truth_table_line ending(=%c)!\n", - __FILE__, __LINE__, tt_line.back()); - exit(1); - } - } - - /* Prefer on_set if both are true */ - if (true == on_set && true == off_set) { - on_set = true; - off_set = false; - } - VTR_ASSERT(on_set == !off_set); - - return on_set; -} - -/******************************************************************** - * Complete a line in truth table with a given lut size - * Due to the size of truth table may be less than the lut size. - * i.e. in LUT-6 architecture, there exists LUT1-6 in technology-mapped netlists - * So, in truth table line, there may be 10- 1 - * In this case, we should complete it by --10- 1 - *******************************************************************/ -static -std::string complete_truth_table_line(const size_t& lut_size, - const std::string& input_truth_table_line) { - std::string ret; - - /* Split one line of truth table line*/ - StringToken string_tokenizer(input_truth_table_line); - std::vector tokens = string_tokenizer.split(' '); - /* Check, only 2 tokens*/ - /* Sometimes, the truth table is ' 0' or ' 1', which corresponds to a constant */ - if (1 == tokens.size()) { - /* restore the token[0]*/ - tokens.insert(tokens.begin(), std::string("-")); - } - - /* After processing, there should be 2 tokens. */ - VTR_ASSERT(2 == tokens.size()); - - /* Complete the truth table line*/ - size_t cover_len = tokens[0].length(); - VTR_ASSERT( (cover_len < lut_size) || (cover_len == lut_size) ); - - /* Copy the original truth table line */ - ret = tokens[0]; - - /* Add the number of '-' we should add in the back !!! */ - for (size_t j = cover_len; j < lut_size; ++j) { - ret.push_back('-'); - } - - /* Copy the original truth table line */ - ret.push_back(' '); - ret.append(tokens[1]); - - /* Check if the size of ret matches our expectation */ - VTR_ASSERT(lut_size + 2 == ret.size()); - - return ret; -} - -/******************************************************************** - * For each lut_bit_lines, we should recover the truth table, - * and then set the sram bits to "1" if the truth table defines so. - * Start_point: the position we start converting don't care sign '-' - * to explicit '0' or '1' - *******************************************************************/ -static -void rec_build_lut_bitstream_per_line(std::vector& lut_bitstream, - const size_t& lut_size, - const std::string& truth_table_line, - const size_t& start_point) { - std::string temp_line(truth_table_line); - - /* Check the length of sram bits and truth table line */ - VTR_ASSERT(lut_size + 2 == truth_table_line.length()); /* lut_size + space + '1' */ - - /* End of truth_table_line should be "space" and "1" */ - VTR_ASSERT( (0 == truth_table_line.compare(truth_table_line.length() - 2, 2, " 1")) - || (0 == truth_table_line.compare(truth_table_line.length() - 2, 2, " 0")) ); - - /* Make sure before start point there is no '-' */ - VTR_ASSERT(start_point < truth_table_line.length()); - for (size_t i = 0; i < start_point; ++i) { - VTR_ASSERT('-' != truth_table_line[i]); - } - - /* Configure sram bits recursively */ - for (size_t i = start_point; i < lut_size; ++i) { - if ('-' == truth_table_line[i]) { - /* if we find a dont_care, we don't do configure now but recursively*/ - /* '0' branch */ - temp_line[i] = '0'; - rec_build_lut_bitstream_per_line(lut_bitstream, lut_size, temp_line, start_point + 1); - /* '1' branch */ - temp_line[i] = '1'; - rec_build_lut_bitstream_per_line(lut_bitstream, lut_size, temp_line, start_point + 1); - return; - } - } - - /* TODO: Use MuxGraph to decode this!!! */ - /* Decode bitstream only when there are only 0 or 1 in the truth table */ - size_t sram_id = 0; - for (size_t i = 0; i < lut_size; ++i) { - /* Should be either '0' or '1' */ - switch (truth_table_line[i]) { - case '0': - /* We assume the 1-lut pass sram1 when input = 0 */ - sram_id += (size_t)pow(2., (double)(i)); - break; - case '1': - /* We assume the 1-lut pass sram0 when input = 1 */ - break; - case '-': - default : - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid truth_table bit(%c), should be [0|1|]!\n", - __FILE__, __LINE__, truth_table_line[i]); - exit(1); - } - } - /* Set the sram bit to '1'*/ - VTR_ASSERT(sram_id < lut_bitstream.size()); - if (0 == truth_table_line.compare(truth_table_line.length() - 2, 2, " 1")) { - lut_bitstream[sram_id] = true; /* on set*/ - } else if (0 == truth_table_line.compare(truth_table_line.length() - 2, 2, " 0")) { - lut_bitstream[sram_id] = false; /* off set */ - } else { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid truth_table_line ending(=%s)!\n", - __FILE__, __LINE__, truth_table_line.substr(lut_size, 2)); - exit(1); - } -} - - -/******************************************************************** - * Generate the bitstream for a single-output LUT with a given truth table - * As truth tables may come from different logic blocks, truth tables could be in on and off sets - * We first build a base SRAM bits, where different parts are set to tbe on/off sets - * Then, we can decode SRAM bits as regular process - *******************************************************************/ -static -std::vector build_single_output_lut_bitstream(const LutTruthTable& truth_table, - const MuxGraph& lut_mux_graph, - const size_t& default_sram_bit_value) { - size_t lut_size = lut_mux_graph.num_memory_bits(); - size_t bitstream_size = lut_mux_graph.num_inputs(); - std::vector lut_bitstream(bitstream_size, false); - LutTruthTable completed_truth_table; - bool on_set = false; - bool off_set = false; - - /* if No truth_table, do default*/ - if (0 == truth_table.size()) { - switch (default_sram_bit_value) { - case 0: - on_set = true; - off_set = false; - break; - case 1: - on_set = false; - off_set = true; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid default_signal_init_value(=%lu)!\n", - __FILE__, __LINE__, default_sram_bit_value); - exit(1); - } - } else { - on_set = lut_truth_table_use_on_set(truth_table); - off_set = !on_set; - } - - /* Read in truth table lines, decode one by one */ - for (const std::string& tt_line : truth_table) { - /* Complete the truth table line by line*/ - completed_truth_table.push_back(complete_truth_table_line(lut_size, tt_line)); - } - - /* Initial all the bits in the bitstream */ - if (true == off_set) { - /* By default, the lut_bitstream is initialize for on_set - * For off set, it should be flipped - */ - lut_bitstream.clear(); - lut_bitstream.resize(bitstream_size, true); - } - - for (const std::string& tt_line : completed_truth_table) { - /* Update the truth table, sram_bits */ - rec_build_lut_bitstream_per_line(lut_bitstream, lut_size, tt_line, 0); - } - - return lut_bitstream; -} - -/******************************************************************** - * Generate bitstream for a fracturable LUT (also applicable to single-output LUT) - * Check type of truth table of each mapped logical block - * if it is on-set, we give a all 0 base bitstream - * if it is off-set, we give a all 1 base bitstream - *******************************************************************/ -std::vector build_frac_lut_bitstream(const CircuitLibrary& circuit_lib, - const MuxGraph& lut_mux_graph, - t_phy_pb* lut_pb, - const std::vector& truth_tables, - const size_t& default_sram_bit_value) { - /* Initialization */ - std::vector lut_bitstream(lut_mux_graph.num_inputs(), default_sram_bit_value); - - for (int ilb = 0; ilb < lut_pb->num_logical_blocks; ++ilb) { - /* Find the corresponding circuit model output port and assoicated lut_output_mask */ - CircuitPortId lut_model_output_port = lut_pb->lut_output_pb_graph_pin[ilb]->port->circuit_model_port; - size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port); - /* By default, lut_frac_level will be the lut_size, i.e., number of levels of the mux graph */ - if ( size_t(-1) == lut_frac_level ) { - lut_frac_level = lut_mux_graph.num_levels(); - } - - /* Find the corresponding circuit model output port and assoicated lut_output_mask */ - size_t lut_output_mask = circuit_lib.port_lut_output_masks(lut_model_output_port)[lut_pb->lut_output_pb_graph_pin[ilb]->pin_number]; - - /* Decode lut sram bits */ - std::vector temp_bitstream = build_single_output_lut_bitstream(truth_tables[ilb], lut_mux_graph, default_sram_bit_value); - - /* Depending on the frac-level, we get the location(starting/end points) of sram bits */ - size_t length_of_temp_bitstream_to_copy = (size_t)pow(2., (double)(lut_frac_level)); - size_t bitstream_offset = length_of_temp_bitstream_to_copy * lut_output_mask; - /* Ensure the offset is in range */ - VTR_ASSERT(bitstream_offset < lut_bitstream.size()); - VTR_ASSERT(bitstream_offset + length_of_temp_bitstream_to_copy <= lut_bitstream.size()); - - /* Copy to the segment of bitstream */ - for (size_t bit = bitstream_offset; bit < bitstream_offset + length_of_temp_bitstream_to_copy; ++bit) { - lut_bitstream[bit] = temp_bitstream[bit]; - } - } - - return lut_bitstream; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.h deleted file mode 100644 index 09e8ef37a..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_lut_bitstream.h +++ /dev/null @@ -1,34 +0,0 @@ -/******************************************************************** - * Header file for build_lut_bitstream.cpp - ********************************************************************/ -#ifndef BUILD_LUT_BITSTREAM_H -#define BUILD_LUT_BITSTREAM_H - -#include -#include "circuit_library.h" -#include "mux_graph.h" -#include "vpr_types.h" - -/* Alias name for data structure of LUT truth table */ -typedef std::vector LutTruthTable; - -/* Declaration for functions */ -LutTruthTable build_post_routing_wired_lut_truth_table(const int& lut_output_vpack_net_num, - const size_t& lut_size, - const std::vector& lut_pin_vpack_net_num); - -LutTruthTable build_post_routing_lut_truth_table(t_logical_block* mapped_logical_block, - const size_t& lut_size, - const std::vector& lut_pin_vpack_net_num); - -LutTruthTable adapt_truth_table_for_frac_lut(const CircuitLibrary& circuit_lib, - t_pb_graph_pin* lut_out_pb_graph_pin, - const LutTruthTable& truth_table); - -std::vector build_frac_lut_bitstream(const CircuitLibrary& circuit_lib, - const MuxGraph& lut_mux_graph, - t_phy_pb* lut_pb, - const std::vector& truth_tables, - const size_t& default_sram_bit_value); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp deleted file mode 100644 index 9edd25b0b..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.cpp +++ /dev/null @@ -1,164 +0,0 @@ -/******************************************************************** - * This file includes functions to build bitstream from routing multiplexers - * which are based on different technology - *******************************************************************/ -#include "vtr_assert.h" -#include "vtr_vector.h" - -#include "mux_utils.h" -#include "decoder_library_utils.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_utils.h" - -#include "build_mux_bitstream.h" - -/******************************************************************** - * Find the default path id of a MUX - * This is applied when the path id specified is DEFAULT_PATH_ID, - * which is not correlated to the MUX implementation - * This function is binding the default path id to the implemented structure - * 1. If the MUX has a constant input, the default path id will be - * directed to the last input of the MUX, which is the constant input - * 2. If the MUX does not have a constant input, the default path id - * will the first input of the MUX. - * - * Restriction: - * we assume the default path is the first input of the MUX - * Change if this is not what you want - *******************************************************************/ -size_t find_mux_default_path_id(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const size_t& mux_size) { - size_t default_path_id; - - if (TRUE == circuit_lib.mux_add_const_input(mux_model)) { - default_path_id = mux_size - 1; /* When there is a constant input, use the last path */ - } else { - default_path_id = DEFAULT_MUX_PATH_ID; /* When there is no constant input, use the default one */ - } - - return default_path_id; -} - -/******************************************************************** - * This function generates bitstream for a CMOS routing multiplexer - * Thanks to MuxGraph object has already describe the internal multiplexing - * structure, bitstream generation is simply done by routing the signal - * to from a given input to the output - * All the memory bits can be generated by an API of MuxGraph - * - * To be generic, this function only returns a vector bit values - * without touching an bitstream-relate data structure - *******************************************************************/ -static -std::vector build_cmos_mux_bitstream(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxLibrary& mux_lib, - const size_t& mux_size, - const int& path_id) { - /* Note that the size of implemented mux could be different than the mux size we see here, - * due to the constant inputs - * We will find the input size of implemented MUX and fetch the graph-based representation in MUX library - */ - size_t implemented_mux_size = find_mux_implementation_num_inputs(circuit_lib, mux_model, mux_size); - /* Note that the mux graph is indexed using datapath MUX size!!!! */ - MuxId mux_graph_id = mux_lib.mux_graph(mux_model, mux_size); - const MuxGraph mux_graph = mux_lib.mux_graph(mux_graph_id); - - size_t datapath_id = path_id; - - /* Find the path_id related to the implementation */ - if (DEFAULT_PATH_ID == path_id) { - datapath_id = find_mux_default_path_id(circuit_lib, mux_model, implemented_mux_size); - } else { - VTR_ASSERT( datapath_id < mux_size); - } - /* Path id should makes sense */ - VTR_ASSERT(datapath_id < mux_graph.inputs().size()); - /* We should have only one output for this MUX! */ - VTR_ASSERT(1 == mux_graph.outputs().size()); - - /* Generate the memory bits */ - vtr::vector raw_bitstream = mux_graph.decode_memory_bits(MuxInputId(datapath_id), mux_graph.output_id(mux_graph.outputs()[0])); - - std::vector mux_bitstream; - for (const bool& bit : raw_bitstream) { - mux_bitstream.push_back(bit); - } - - /* Consider local encoder support, we need further encode the bitstream */ - if (false == circuit_lib.mux_use_local_encoder(mux_model)) { - return mux_bitstream; - } - - /* Clear the mux_bitstream, we need to apply encoding */ - mux_bitstream.clear(); - - /* Encode the memory bits level by level, - * One local encoder is used for each level of multiplexers - */ - for (const size_t& level : mux_graph.levels()) { - /* The encoder will convert the path_id to a binary number - * For example: when path_id=3 (use the 4th input), using a 2-input encoder - * the sram_bits will be the 2-digit binary number of 3: 10 - */ - std::vector encoder_data; - - /* Exception: there is only 1 memory at this level, bitstream will not be changed!!! */ - if (1 == mux_graph.memories_at_level(level).size()) { - mux_bitstream.push_back(raw_bitstream[mux_graph.memories_at_level(level)[0]]); - continue; - } - - /* Otherwise: we follow a regular recipe */ - for (size_t mem_index = 0; mem_index < mux_graph.memories_at_level(level).size(); ++mem_index) { - /* Conversion rule: true = 1, false = 0 */ - if (true == raw_bitstream[mux_graph.memories_at_level(level)[mem_index]]) { - encoder_data.push_back(mem_index); - } - } - /* There should be at most one '1' */ - VTR_ASSERT( (0 == encoder_data.size()) || (1 == encoder_data.size())); - /* Convert to encoded bits */ - std::vector encoder_addr; - if (0 == encoder_data.size()) { - encoder_addr = my_itobin_vec(0, find_mux_local_decoder_addr_size(mux_graph.memories_at_level(level).size())); - } else { - VTR_ASSERT(1 == encoder_data.size()); - encoder_addr = my_itobin_vec(encoder_data[0], find_mux_local_decoder_addr_size(mux_graph.memories_at_level(level).size())); - } - /* Build final mux bitstream */ - for (const size_t& bit : encoder_addr) { - mux_bitstream.push_back(1 == bit); - } - } - - return mux_bitstream; -} - -/******************************************************************** - * This function generates bitstream for a routing multiplexer - * supporting both CMOS and ReRAM multiplexer designs - *******************************************************************/ -std::vector build_mux_bitstream(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxLibrary& mux_lib, - const size_t& mux_size, - const int& path_id) { - std::vector mux_bitstream; - - switch (circuit_lib.design_tech_type(mux_model)) { - case SPICE_MODEL_DESIGN_CMOS: - mux_bitstream = build_cmos_mux_bitstream(circuit_lib, mux_model, mux_lib, mux_size, path_id); - break; - case SPICE_MODEL_DESIGN_RRAM: - /* TODO: ReRAM MUX needs a different bitstream generation strategy */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid design technology for circuit model (%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); - exit(1); - } - return mux_bitstream; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.h deleted file mode 100644 index 227eabdf9..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_mux_bitstream.h +++ /dev/null @@ -1,21 +0,0 @@ -/******************************************************************** - * Header file for build_mux_bitstream.cpp - *******************************************************************/ -#ifndef BUILD_MUX_BITSTREAM_H -#define BUILD_MUX_BITSTREAM_H - -#include -#include "circuit_library.h" -#include "mux_library.h" - -size_t find_mux_default_path_id(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const size_t& mux_size); - -std::vector build_mux_bitstream(const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const MuxLibrary& mux_lib, - const size_t& mux_size, - const int& path_id); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp deleted file mode 100644 index 48c4a0504..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.cpp +++ /dev/null @@ -1,395 +0,0 @@ -/******************************************************************** - * This file includes functions to build bitstream from global routing - * architecture of a mapped FPGA fabric - * We decode the bitstream from configuration of routing multiplexers - * which locate in global routing architecture - *******************************************************************/ -#include -#include - -#include "vtr_assert.h" -#include "util.h" -#include "mux_utils.h" -#include "rr_blocks_utils.h" -#include "fpga_x2p_reserved_words.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -#include "build_mux_bitstream.h" -#include "build_routing_bitstream.h" - -/******************************************************************** - * This function generates bitstream for a routing multiplexer - * This function will identify if a node indicates a routing multiplexer - * If not a routing multiplexer, no bitstream is needed here - * If yes, we will generate the bitstream for the routing multiplexer - *******************************************************************/ -static -void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& mux_mem_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_rr_node* L_rr_node, - t_rr_node* cur_rr_node, - const std::vector& drive_rr_nodes, - const int& switch_index) { - /* Check current rr_node is CHANX or CHANY*/ - VTR_ASSERT((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); - - /* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */ - CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - - /* Find the input size of the implementation of a routing multiplexer */ - size_t datapath_mux_size = drive_rr_nodes.size(); - - /* Find out which routing path is used in this MUX */ - int path_id = DEFAULT_PATH_ID; - for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) { - if (drive_rr_nodes[inode] == &(L_rr_node[cur_rr_node->prev_node])) { - path_id = (int)inode; - break; - } - } - - /* Ensure that our path id makes sense! */ - VTR_ASSERT( (DEFAULT_PATH_ID == path_id) - || ( (DEFAULT_PATH_ID < path_id) && (path_id < (int)datapath_mux_size) ) - ); - - /* Generate bitstream depend on both technology and structure of this MUX */ - std::vector mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id); - - /* Find the module in module manager and ensure the bitstream size matches! */ - std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); - ModuleId mux_mem_module = module_manager.find_module(mem_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module)); - ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name()); - VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width()); - - /* Add the bistream to the bitstream manager */ - for (const bool& bit : mux_bitstream) { - ConfigBitId config_bit = bitstream_manager.add_bit(bit); - /* Link the memory bits to the mux mem block */ - bitstream_manager.add_bit_to_block(mux_mem_block, config_bit); - } -} - -/******************************************************************** - * This function generates bitstream for an interconnection, - * i.e., a routing multiplexer, in a Switch Block - * This function will identify if a node indicates a routing multiplexer - * If not a routing multiplexer, no bitstream is needed here - * If yes, we will generate the bitstream for the routing multiplexer - *******************************************************************/ -static -void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& sb_configurable_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_rr_node* L_rr_node, - const RRGSB& rr_gsb, - const e_side& chan_side, - const size_t& chan_node_id) { - - std::vector drive_rr_nodes; - - /* Get the node */ - t_rr_node* cur_rr_node = rr_gsb.get_chan_node(chan_side, chan_node_id); - - /* Determine if the interc lies inside a channel wire, that is interc between segments */ - if (false == rr_gsb.is_sb_node_passing_wire(chan_side, chan_node_id)) { - for (int i = 0; i < cur_rr_node->num_drive_rr_nodes; ++i) { - drive_rr_nodes.push_back(cur_rr_node->drive_rr_nodes[i]); - } - /* Special: if there are zero-driver nodes. We skip here */ - if (0 == drive_rr_nodes.size()) { - return; - } - } - - if ( (0 == drive_rr_nodes.size()) - || (0 == drive_rr_nodes.size()) ) { - /* No bitstream generation required by a special direct connection*/ - return; - } else if (1 < drive_rr_nodes.size()) { - /* Create the block denoting the memory instances that drives this node in Switch Block */ - std::string mem_block_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MEM_INSTANCE_PREFIX, chan_side, chan_node_id, std::string("")); - ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name); - bitstream_manager.add_child_block(sb_configurable_block, mux_mem_block); - /* This is a routing multiplexer! Generate bitstream */ - build_switch_block_mux_bitstream(bitstream_manager, mux_mem_block, module_manager, - circuit_lib, mux_lib, rr_switches, L_rr_node, - cur_rr_node, drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]); - } /*Nothing should be done else*/ -} - -/******************************************************************** - * This function generates bitstream for a Switch Block - * and add it to the bitstream manager - * This function will spot all the routing multiplexers in a Switch Block - * using a simple but effective rule: - * The fan-in of each output node. - * If there are more than 2 fan-in, there is a routing multiplexer - * - * Note that the output nodes typically spread over all the sides of a Switch Block - * So, we will iterate over that. - *******************************************************************/ -static -void build_switch_block_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& sb_config_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_rr_node* L_rr_node, - const RRGSB& rr_gsb) { - - /* Iterate over all the multiplexers */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - VTR_ASSERT( (CHANX == rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type) - || (CHANY == rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type)); - /* Only output port indicates a routing multiplexer */ - if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - continue; - } - build_switch_block_interc_bitstream(bitstream_manager, sb_config_block, - module_manager, - circuit_lib, mux_lib, rr_switches, L_rr_node, - rr_gsb, side_manager.get_side(), itrack); - } - } -} - -/******************************************************************** - * This function generates bitstream for a routing multiplexer - * in a Connection block - * This function will identify if a node indicates a routing multiplexer - * If not a routing multiplexer, no bitstream is needed here - * If yes, we will generate the bitstream for the routing multiplexer - *******************************************************************/ -static -void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& mux_mem_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_rr_node* L_rr_node, - t_rr_node* src_rr_node) { - /* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */ - int switch_index = src_rr_node->drive_switches[DEFAULT_SWITCH_ID]; - CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - - /* Find drive_rr_nodes*/ - size_t datapath_mux_size = (size_t)(src_rr_node->num_drive_rr_nodes); - - /* Configuration bits for MUX*/ - int path_id = DEFAULT_PATH_ID; - for (size_t inode = 0; inode < datapath_mux_size; ++inode) { - if (src_rr_node->drive_rr_nodes[inode] == &(L_rr_node[src_rr_node->prev_node])) { - path_id = (int)inode; - break; - } - } - - /* Ensure that our path id makes sense! */ - VTR_ASSERT( (DEFAULT_PATH_ID == path_id) - || ( (DEFAULT_PATH_ID < path_id) && (path_id < (int)datapath_mux_size) ) - ); - - /* Generate bitstream depend on both technology and structure of this MUX */ - std::vector mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id); - - /* Find the module in module manager and ensure the bitstream size matches! */ - std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); - ModuleId mux_mem_module = module_manager.find_module(mem_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module)); - ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name()); - VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width()); - - /* Add the bistream to the bitstream manager */ - for (const bool& bit : mux_bitstream) { - ConfigBitId config_bit = bitstream_manager.add_bit(bit); - /* Link the memory bits to the mux mem block */ - bitstream_manager.add_bit_to_block(mux_mem_block, config_bit); - } -} - - -/******************************************************************** - * This function generates bitstream for an interconnection, - * i.e., a routing multiplexer, in a Connection Block - * This function will identify if a node indicates a routing multiplexer - * If not a routing multiplexer, no bitstream is needed here - * If yes, we will generate the bitstream for the routing multiplexer - *******************************************************************/ -static -void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& cb_configurable_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_rr_node* L_rr_node, - const RRGSB& rr_gsb, - const e_side& cb_ipin_side, - const size_t& ipin_index) { - - t_rr_node* src_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index); - if (1 == src_rr_node->fan_in) { - /* No bitstream generation required by a special direct connection*/ - } else if (1 < src_rr_node->fan_in) { - /* Create the block denoting the memory instances that drives this node in Switch Block */ - std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), ipin_index, std::string("")); - ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name); - bitstream_manager.add_child_block(cb_configurable_block, mux_mem_block); - /* This is a routing multiplexer! Generate bitstream */ - build_connection_block_mux_bitstream(bitstream_manager, mux_mem_block, - module_manager, circuit_lib, mux_lib, rr_switches, - L_rr_node, src_rr_node); - } /*Nothing should be done else*/ -} - -/******************************************************************** - * This function generates bitstream for a Connection Block - * and add it to the bitstream manager - * This function will spot all the routing multiplexers in a Connection Block - * using a simple but effective rule: - * The fan-in of each output node. - * If there are more than 2 fan-in, there is a routing multiplexer - * - * Note that the output nodes are the IPIN rr node in a Connection Block - * So, we will iterate over that. - *******************************************************************/ -static -void build_connection_block_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& cb_configurable_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_rr_node* L_rr_node, - const RRGSB& rr_gsb, - const t_rr_type& cb_type) { - - /* Find routing multiplexers on the sides of a Connection block where IPIN nodes locate */ - std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); - - for (size_t side = 0; side < cb_sides.size(); ++side) { - enum e_side cb_ipin_side = cb_sides[side]; - Side side_manager(cb_ipin_side); - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - build_connection_block_interc_bitstream(bitstream_manager, cb_configurable_block, - module_manager, circuit_lib, mux_lib, - rr_switches, L_rr_node, - rr_gsb, - cb_ipin_side, inode); - } - } -} - -/******************************************************************** - * Create bitstream for a X-direction or Y-direction Connection Blocks - *******************************************************************/ -static -void build_connection_block_bitstreams(BitstreamManager& bitstream_manager, - const ConfigBlockId& top_configurable_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_rr_node* L_rr_node, - const DeviceRRGSB& L_device_rr_gsb, - const t_rr_type& cb_type) { - - DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); - - for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - /* Check if the connection block exists in the device! - * Some of them do NOT exist due to heterogeneous blocks (height > 1) - * We will skip those modules - */ - if (false == rr_gsb.is_cb_exist(cb_type)) { - continue; - } - /* Skip if the cb does not contain any configuration bits! */ - if (true == connection_block_contain_only_routing_tracks(rr_gsb, cb_type)) { - continue; - } - /* Create a block for the bitstream which corresponds to the Switch block */ - vtr::Point cb_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - ConfigBlockId cb_configurable_block = bitstream_manager.add_block(generate_connection_block_module_name(cb_type, cb_coord)); - /* Set switch block as a child of top block */ - bitstream_manager.add_child_block(top_configurable_block, cb_configurable_block); - - build_connection_block_bitstream(bitstream_manager, cb_configurable_block, module_manager, - circuit_lib, mux_lib, rr_switches, L_rr_node, - rr_gsb, cb_type); - } - } -} - -/******************************************************************** - * Top-level function to create bitstream for global routing architecture - * Two major tasks: - * 1. Generate bitstreams for Switch Blocks - * 2. Generate bitstreams for both X-direction and Y-direction Connection Blocks - *******************************************************************/ -void build_routing_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& top_configurable_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_rr_node* L_rr_node, - const DeviceRRGSB& L_device_rr_gsb) { - - /* Generate bitstream for each switch blocks - * To organize the bitstream in blocks, we create a block for each switch block - * and give names which are same as they are in top-level module managers - */ - vpr_printf(TIO_MESSAGE_INFO, - "Generating bitstream for Switch blocks...\n"); - DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); - for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - /* Create a block for the bitstream which corresponds to the Switch block */ - vtr::Point sb_coord(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - ConfigBlockId sb_configurable_block = bitstream_manager.add_block(generate_switch_block_module_name(sb_coord)); - /* Set switch block as a child of top block */ - bitstream_manager.add_child_block(top_configurable_block, sb_configurable_block); - - build_switch_block_bitstream(bitstream_manager, sb_configurable_block, module_manager, - circuit_lib, mux_lib, rr_switches, L_rr_node, - rr_gsb); - } - } - - /* Generate bitstream for each connection blocks - * To organize the bitstream in blocks, we create a block for each connection block - * and give names which are same as they are in top-level module managers - */ - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for X-direction Connection blocks ...\n"); - - build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager, - circuit_lib, mux_lib, rr_switches, L_rr_node, - L_device_rr_gsb, CHANX); - - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Y-direction Connection blocks ...\n"); - - build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager, - circuit_lib, mux_lib, rr_switches, L_rr_node, - L_device_rr_gsb, CHANY); - -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h deleted file mode 100644 index eaf9aec5d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/build_routing_bitstream.h +++ /dev/null @@ -1,24 +0,0 @@ -/******************************************************************** - * Header file for build_routing_bitstream.cpp - *******************************************************************/ -#ifndef BUILD_ROUTING_BITSTREAM_H -#define BUILD_ROUTING_BITSTREAM_H - -#include -#include "bitstream_manager.h" -#include "vpr_types.h" -#include "module_manager.h" -#include "circuit_library.h" -#include "mux_library.h" -#include "rr_blocks.h" - -void build_routing_bitstream(BitstreamManager& bitstream_manager, - const ConfigBlockId& top_configurable_block, - const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const std::vector& rr_switches, - t_rr_node* L_rr_node, - const DeviceRRGSB& L_device_rr_gsb); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.c b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.c deleted file mode 100644 index c2e0a03d2..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.c +++ /dev/null @@ -1,399 +0,0 @@ -/***********************************/ -/* Synthesizable Verilog Dumping */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "path_delay.h" -#include "stats.h" - -/* Include FPGA-SPICE utils */ -#include "read_xml_spice_util.h" -#include "linkedlist.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_backannotate_utils.h" -#include "fpga_x2p_bitstream_utils.h" -#include "fpga_x2p_globals.h" -#include "fpga_bitstream_pbtypes.h" -#include "fpga_bitstream_routing.h" -#include "fpga_bitstream.h" - -/* Global variables only in file */ -static int dumped_num_conf_bits = 0; - -/* Local Subroutines */ -static -void rec_dump_conf_bits_to_bitstream_file(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - t_llist* cur_conf_bit); - -/* USE while LOOP !!! Recursive method causes memory corruptions!*/ -static -void dump_conf_bits_to_bitstream_file(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - t_llist* cur_conf_bit_head); - - -/* Generate a file contain all the configuration bits of the mapped FPGA. - * The configuration bits are loaded to FPGA in a stream, which is called bitstream - * In this file, the property of configuration bits will be shown as comments, - * which is easy for developers to debug - */ -void dump_fpga_spice_bitstream(const char* bitstream_file_name, - const char* circuit_name, - t_sram_orgz_info* cur_sram_orgz_info) { - FILE* fp; - - /* Check if the path exists*/ - fp = fopen(bitstream_file_name,"w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create bitstream %s!",__FILE__, __LINE__, bitstream_file_name); - exit(1); - } - - vpr_printf(TIO_MESSAGE_INFO, "Writing bitstream file (%s) for %s...\n", - bitstream_file_name, circuit_name); - - /* Reset counter */ - dumped_num_conf_bits = 0; - - /* Find the head of bitstream: which is the tail of linked list */ - /* rec_dump_conf_bits_to_bitstream_file(fp, cur_sram_orgz_info, cur_sram_orgz_info->conf_bit_head); */ - dump_conf_bits_to_bitstream_file(fp, cur_sram_orgz_info, cur_sram_orgz_info->conf_bit_head); - - /* close file */ - fclose(fp); - - vpr_printf(TIO_MESSAGE_INFO, "Dumped %d configuration bits into bitstream file...\n", - dumped_num_conf_bits); - - /* Free the linked-list contain configuration bits ? */ - - return; -} - -/* Encode the given input to the address for a decode*/ -void encode_decoder_addr(int input, - int decoder_size, char* addr) { - int temp = input; - int i; - - assert(NULL != addr); - /* Check the length of addr !*/ - // assert((decoder_size + 1) == len_addr); - /* Add the end of a string */ - addr[decoder_size] = '\0'; - - for (i = 0; i < decoder_size; i++) { - addr[i] = '0'; - } - - i = decoder_size - 1; - - /* Actually, we convert a decimal number to its binary format */ - while (0 != temp) { - addr[i] = (temp % 2) + '0'; - temp = temp/2; - i--; - /* Check i is still in the boundary */ - if (i < 0) { - break; /* Quit the loop */ - } - } - /* May be the decoder size is too small */ - if (0 != temp) { - vpr_printf(TIO_MESSAGE_WARNING, "(File:%s,[LINE%d])Decoder size(%d) is too small for input(%d)!\n", - __FILE__, __LINE__, decoder_size, input); - } - - return; -} - -/* Recursively dump configuration bits which are stored in the linked list - * We start dump configuration bit from the tail of the linked list - * until the head of the linked list - */ -static -void rec_dump_conf_bits_to_bitstream_file(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - t_llist* cur_conf_bit) { - t_conf_bit_info* cur_conf_bit_info = (t_conf_bit_info*)(cur_conf_bit->dptr); - int num_bl, num_wl, bl_decoder_size, wl_decoder_size; - char* bl_addr = NULL; - char* wl_addr = NULL; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!",__FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert(NULL != cur_conf_bit_info); - - if (NULL != cur_conf_bit->next) { - /* This is not the tail, keep going */ - rec_dump_conf_bits_to_bitstream_file(fp, cur_sram_orgz_info, cur_conf_bit->next); - } - - /* We alraedy touch the tail, start dump */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - case SPICE_SRAM_SCAN_CHAIN: - /* Scan-chain only loads the SRAM values */ - fprintf(fp, "%d, ", cur_conf_bit_info->sram_bit->val), - fprintf(fp, "// Configuration bit No.: %d, ", cur_conf_bit_info->index); - fprintf(fp, " SRAM value: %d, ", cur_conf_bit_info->sram_bit->val); - fprintf(fp, " SPICE model name: %s, ", cur_conf_bit_info->parent_spice_model->name); - fprintf(fp, " SPICE model index: %d ", cur_conf_bit_info->parent_spice_model_index); - fprintf(fp, "\n"); - /* Update the counter */ - dumped_num_conf_bits++; - break; - case SPICE_SRAM_MEMORY_BANK: - get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &num_bl, &num_wl); - bl_decoder_size = determine_decoder_size(num_bl); - wl_decoder_size = determine_decoder_size(num_wl); - - /* Memory bank requires the address to be given to the decoder*/ - /* Word line address */ - bl_addr = (char*)my_calloc(bl_decoder_size + 1, sizeof(char)); - /* If this WL is selected , we decode its index to address */ - assert(NULL != cur_conf_bit_info->bl); - encode_decoder_addr(cur_conf_bit_info->bl->addr, bl_decoder_size, bl_addr); - fprintf(fp, "bl'%s = %d, ", bl_addr, cur_conf_bit_info->bl->val); - fprintf(fp, "// Configuration bit No.: %d, ", cur_conf_bit_info->index); - fprintf(fp, " Bit Line: %d, ", cur_conf_bit_info->bl->val); - fprintf(fp, " SPICE model name: %s, ", cur_conf_bit_info->parent_spice_model->name); - fprintf(fp, " SPICE model index: %d ", cur_conf_bit_info->parent_spice_model_index); - fprintf(fp, "\n"); - /* Bit line address */ - /* If this WL is selected , we decode its index to address */ - wl_addr = (char*)my_calloc(wl_decoder_size + 1, sizeof(char)); - assert(NULL != cur_conf_bit_info->wl); - encode_decoder_addr(cur_conf_bit_info->wl->addr, wl_decoder_size, wl_addr); - fprintf(fp, "wl'%s = %d, ", wl_addr, cur_conf_bit_info->wl->val); - fprintf(fp, "// Configuration bit No.: %d, ", cur_conf_bit_info->index); - fprintf(fp, " Word Line: %d, ", cur_conf_bit_info->wl->val); - fprintf(fp, " SPICE model name: %s, ", cur_conf_bit_info->parent_spice_model->name); - fprintf(fp, " SPICE model index: %d ", cur_conf_bit_info->parent_spice_model_index); - fprintf(fp, "\n"); - /* Update the counter */ - dumped_num_conf_bits++; - /* Free */ - my_free(wl_addr); - my_free(bl_addr); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", - __FILE__, __LINE__); - exit(1); - } - - - return; -} - -/* Dump a bitstream by using while loop */ -static -void dump_conf_bits_to_bitstream_file(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - t_llist* cur_conf_bit_head) { - t_llist* temp = cur_conf_bit_head; - t_conf_bit_info* cur_conf_bit_info = NULL; - int num_bl, num_wl, bl_decoder_size, wl_decoder_size; - char* bl_addr = NULL; - char* wl_addr = NULL; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!",__FILE__, __LINE__); - exit(1); - } - - get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &num_bl, &num_wl); - bl_decoder_size = determine_decoder_size(num_bl); - wl_decoder_size = determine_decoder_size(num_wl); - - while (NULL != temp) { - cur_conf_bit_info = (t_conf_bit_info*)(temp->dptr); - /* We alraedy touch the tail, start dump */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - case SPICE_SRAM_SCAN_CHAIN: - /* Scan-chain only loads the SRAM values */ - fprintf(fp, "%d, ", cur_conf_bit_info->sram_bit->val), - fprintf(fp, "// Configuration bit No.: %d, ", cur_conf_bit_info->index); - fprintf(fp, " SRAM value: %d, ", cur_conf_bit_info->sram_bit->val); - fprintf(fp, " SPICE model name: %s, ", cur_conf_bit_info->parent_spice_model->name); - fprintf(fp, " SPICE model index: %d ", cur_conf_bit_info->parent_spice_model_index); - fprintf(fp, "\n"); - /* Update the counter */ - dumped_num_conf_bits++; - break; - case SPICE_SRAM_MEMORY_BANK: - /* Memory bank requires the address to be given to the decoder*/ - /* Word line address */ - bl_addr = (char*)my_calloc(bl_decoder_size + 1, sizeof(char)); - /* If this WL is selected , we decode its index to address */ - assert(NULL != cur_conf_bit_info->bl); - encode_decoder_addr(cur_conf_bit_info->bl->addr, bl_decoder_size, bl_addr); - fprintf(fp, "bl'%s = %d, ", bl_addr, cur_conf_bit_info->bl->val); - fprintf(fp, "// Configuration bit No.: %d, ", cur_conf_bit_info->index); - fprintf(fp, " Bit Line: %d, ", cur_conf_bit_info->bl->val); - fprintf(fp, " SPICE model name: %s, ", cur_conf_bit_info->parent_spice_model->name); - fprintf(fp, " SPICE model index: %d ", cur_conf_bit_info->parent_spice_model_index); - fprintf(fp, "\n"); - /* Bit line address */ - /* If this WL is selected , we decode its index to address */ - wl_addr = (char*)my_calloc(wl_decoder_size + 1, sizeof(char)); - assert(NULL != cur_conf_bit_info->wl); - encode_decoder_addr(cur_conf_bit_info->wl->addr, wl_decoder_size, wl_addr); - fprintf(fp, "wl'%s = %d, ", wl_addr, cur_conf_bit_info->wl->val); - fprintf(fp, "// Configuration bit No.: %d, ", cur_conf_bit_info->index); - fprintf(fp, " Word Line: %d, ", cur_conf_bit_info->wl->val); - fprintf(fp, " SPICE model name: %s, ", cur_conf_bit_info->parent_spice_model->name); - fprintf(fp, " SPICE model index: %d ", cur_conf_bit_info->parent_spice_model_index); - fprintf(fp, "\n"); - /* Free */ - my_free(wl_addr); - my_free(bl_addr); - /* Update the counter */ - dumped_num_conf_bits++; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", - __FILE__, __LINE__); - exit(1); - } - /* Go to next */ - temp = temp->next; - } - - return; -} - -/* Top-level function*/ -void vpr_fpga_generate_bitstream(t_vpr_setup vpr_setup, - t_arch Arch, - const char* circuit_name, - const char* bitstream_file_path, - t_sram_orgz_info** cur_sram_orgz_info) { - /* Timer */ - clock_t t_start; - clock_t t_end; - float run_time_sec; - - char* chomped_parent_dir = NULL; - char* chomped_circuit_name = NULL; - - char* routing_bitstream_log_file_path = NULL; - char* lb_bitstream_log_file_path = NULL; - - /* Check if the routing architecture we support*/ - if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { - vpr_printf(TIO_MESSAGE_ERROR, "FPGA Bitstream Generator only support uni-directional routing architecture!\n"); - exit(1); - } - - /* We don't support mrFPGA */ -#ifdef MRFPGA_H - if (is_mrFPGA) { - vpr_printf(TIO_MESSAGE_ERROR, "FPGA Bitstream Generator do not support mrFPGA!\n"); - exit(1); - } -#endif - - assert (TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream); - - /* Format the directory paths */ - split_path_prog_name(circuit_name, '/', &chomped_parent_dir, &chomped_circuit_name); - - /* VerilogGenerator formally starts*/ - vpr_printf(TIO_MESSAGE_INFO, "\nFPGA Bitstream generator starts...\n"); - - /* Start time count */ - t_start = clock(); - - /* assign the global variable of SRAM model */ - assert(NULL != Arch.sram_inf.verilog_sram_inf_orgz); /* Check !*/ - /* initialize the SRAM organization information struct */ - (*cur_sram_orgz_info) = alloc_one_sram_orgz_info(); - init_sram_orgz_info(*cur_sram_orgz_info, Arch.sram_inf.verilog_sram_inf_orgz->type, - Arch.sram_inf.verilog_sram_inf_orgz->spice_model, nx + 2, ny + 2); - /* Check all the SRAM port is using the correct SRAM SPICE MODEL */ - config_spice_models_sram_port_spice_model(Arch.spice->num_spice_model, - Arch.spice->spice_models, - Arch.sram_inf.verilog_sram_inf_orgz->spice_model); - - /* zero the counter of each spice_model */ - zero_spice_models_cnt(Arch.spice->num_spice_model, Arch.spice->spice_models); - - /* Generate Bitstreams - * Bitstream generation must follow the sequence: CB => SB => Grid - * (To be consistent with Verilog Generator !!!) - */ - init_sram_orgz_info_reserved_blwl(*cur_sram_orgz_info, vpr_setup.RoutingArch.num_switch, - switch_inf, Arch.spice, &vpr_setup.RoutingArch); - - /* Routing: Connection Boxes and Switch Boxes */ - routing_bitstream_log_file_path = my_strcat(circuit_name, fpga_spice_bitstream_routing_log_file_postfix); - fpga_spice_generate_bitstream_routing_resources(routing_bitstream_log_file_path, - Arch, &vpr_setup.RoutingArch, *cur_sram_orgz_info, - vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); - - - /* Logic blocks */ - lb_bitstream_log_file_path = my_strcat(circuit_name, fpga_spice_bitstream_logic_block_log_file_postfix); - fpga_spice_generate_bitstream_logic_block(lb_bitstream_log_file_path, - &Arch, *cur_sram_orgz_info); - - - /* Dump bitstream file */ - dump_fpga_spice_bitstream(bitstream_file_path, chomped_circuit_name, *cur_sram_orgz_info); - - /* End time count */ - t_end = clock(); - - run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, "Bitstream Generation took %g seconds\n", run_time_sec); - - /* Free */ - - return; - -} - -/* This is a shell for bitstream generation - * Prepare all the variables required by the core generator - */ -void vpr_fpga_bitstream_generator(t_vpr_setup vpr_setup, - t_arch Arch, - char* circuit_name, - t_sram_orgz_info** cur_sram_orgz_info) { - std::string bitstream_file_path; - - if (NULL == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.bitstream_output_file) { - bitstream_file_path = circuit_name; - bitstream_file_path.append(fpga_spice_bitstream_output_file_postfix); - } else { - bitstream_file_path = vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.bitstream_output_file; - } - - /* Run bitstream generation and dump output file */ - vpr_fpga_generate_bitstream(vpr_setup, Arch, circuit_name, bitstream_file_path.c_str(), cur_sram_orgz_info); -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.h deleted file mode 100644 index 9236b70ee..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream.h +++ /dev/null @@ -1,18 +0,0 @@ - -void encode_decoder_addr(int input, - int decoder_size, char* addr); - -void dump_fpga_spice_bitstream(const char* bitstream_file_name, - const char* circuit_name, - t_sram_orgz_info* cur_sram_orgz_info); - -void vpr_fpga_generate_bitstream(t_vpr_setup vpr_setup, - t_arch Arch, - const char* circuit_name, - const char* bitstream_file_path, - t_sram_orgz_info** cur_sram_orgz_info); - -void vpr_fpga_bitstream_generator(t_vpr_setup vpr_setup, - t_arch Arch, - char* circuit_name, - t_sram_orgz_info** cur_sram_orgz_info); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.c deleted file mode 100644 index 4741521fe..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.c +++ /dev/null @@ -1,686 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include SPICE support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_mux_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_bitstream_utils.h" -#include "fpga_bitstream_primitives.h" - -#include "fpga_bitstream_pbtypes.h" - - -/***** Subroutines *****/ - -/* We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * src_pb_graph_node.[in|out]_pins -----------------> des_pb_graph_node.[in|out]pins - * /|\ - * | - * input_pins, edges, output_pins - */ -void fpga_spice_generate_bitstream_pb_graph_pin_interc(FILE* fp, - enum e_spice_pin2pin_interc_type pin2pin_interc_type, - t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode, - int select_edge, - t_sram_orgz_info* cur_sram_orgz_info) { - int iedge, ilevel; - int fan_in = 0; - t_interconnect* cur_interc = NULL; - enum e_interconnect verilog_interc_type = DIRECT_INTERC; - - int num_mux_sram_bits = 0; - int* mux_sram_bits = NULL; - int mux_level = 0; - int cur_bl, cur_wl; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* 1. identify pin interconnection type, - * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) - * 3. Select and print the SPICE netlist - */ - fan_in = 0; - cur_interc = NULL; - find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, cur_mode, &cur_interc, &fan_in); - if ((NULL == cur_interc)||(0 == fan_in)) { - /* No interconnection matched */ - /* Connect this pin to GND for better convergence */ - /* TODO: find the correct pin name!!!*/ - return; - } - verilog_interc_type = determine_actual_pb_interc_type(cur_interc, fan_in); - /* This time, (2nd round), we print the subckt, according to interc type*/ - switch (verilog_interc_type) { - case DIRECT_INTERC: - /* Check : - * 1. Direct interc has only one fan-in! - */ - assert(1 == fan_in); - //assert(1 == des_pb_graph_pin->num_input_edges); - /* For more than one mode defined, the direct interc has more than one input_edge , - * We need to find which edge is connected the pin we want - */ - for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - if (cur_interc == des_pb_graph_pin->input_edges[iedge]->interconnect) { - break; - } - } - assert(iedge < des_pb_graph_pin->num_input_edges); - /* 2. spice_model is a wire */ - assert(NULL != cur_interc->spice_model); - assert(SPICE_MODEL_WIRE == cur_interc->spice_model->type); - assert(NULL != cur_interc->spice_model->wire_param); - /* Call the subckt that has already been defined before */ - cur_interc->spice_model->cnt++; /* Stats the number of spice_model used*/ - break; - case COMPLETE_INTERC: - case MUX_INTERC: - /* Check : - * MUX should have at least 2 fan_in - */ - assert((2 == fan_in)||(2 < fan_in)); - /* 2. spice_model is a wire */ - assert(NULL != cur_interc->spice_model); - assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); - /* Print SRAMs that configure this MUX */ - get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); - /* SRAMs */ - switch (cur_interc->spice_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - decode_cmos_mux_sram_bits(cur_interc->spice_model, fan_in, select_edge, - &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - case SPICE_MODEL_DESIGN_RRAM: - decode_rram_mux(cur_interc->spice_model, fan_in, select_edge, - &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", - __FILE__, __LINE__, cur_interc->spice_model->name); - } - - /* Print the encoding in SPICE netlist for debugging */ - fprintf(fp, "***** SRAM bits for MUX[%d], mux_size=%d, level=%d, select_path_id=%d. *****\n", - cur_interc->spice_model->cnt, fan_in, mux_level, select_edge); - fprintf(fp, "*****"); - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - fprintf(fp, "%d", mux_sram_bits[ilevel]); - } - fprintf(fp, "*****\n\n"); - - /* Store the configuraion bit to linked-list */ - add_mux_conf_bits_to_llist(fan_in, cur_sram_orgz_info, - num_mux_sram_bits, mux_sram_bits, - cur_interc->spice_model); - /* Synchronize the sram_orgz_info with mem_bits */ - add_mux_conf_bits_to_sram_orgz_info(cur_sram_orgz_info, cur_interc->spice_model, fan_in); - /* update sram counter */ - cur_interc->spice_model->cnt++; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", - __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); - exit(1); - } - - return; -} - -void fpga_spice_generate_bitstream_pb_graph_port_interc(FILE* fp, - t_pb_graph_node* cur_pb_graph_node, - t_phy_pb* cur_pb, - enum e_spice_pb_port_type pb_port_type, - t_mode* cur_mode, - t_sram_orgz_info* cur_sram_orgz_info) { - int iport, ipin; - int node_index = -1; - int prev_node = -1; - int path_id = -1; - t_rr_node* pb_rr_nodes = NULL; - - if (NULL != cur_pb) { - fprintf(fp, "***** Logic block:%s *****\n", - cur_pb->spice_name_tag); - fprintf(fp, "***** Pb_graph_node: %s[%d]*****\n", - cur_pb_graph_node->pb_type->name, cur_pb_graph_node->placement_index); - } - - switch (pb_port_type) { - case SPICE_PB_PORT_INPUT: - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - fprintf(fp, "***** Input Port: %s[%d]*****\n", - cur_pb_graph_node->input_pins[iport][ipin].port->name, - cur_pb_graph_node->input_pins[iport][ipin].pin_number); - /* If this is a idle block, we set 0 to the selected edge*/ - /* Get the selected edge of current pin*/ - if (NULL == cur_pb) { - path_id = DEFAULT_PATH_ID; - } else { - assert(NULL != cur_pb); - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = cur_pb_graph_node->input_pins[iport][ipin].rr_node_index_physical_pb; - prev_node = pb_rr_nodes[node_index].prev_node; - /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ - /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ - if (OPEN == prev_node) { - path_id = DEFAULT_PATH_ID; - } else { - /* Find the path_id */ - path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); - assert(DEFAULT_PATH_ID != path_id); - } - /* Path id for the sdc generation */ - pb_rr_nodes[node_index].id_path = path_id; - - if (OPEN != pb_rr_nodes[node_index].vpack_net_num) { - fprintf(fp, "***** Net name: %s *****\n", - vpack_net[pb_rr_nodes[node_index].vpack_net_num].name); - } - } - fpga_spice_generate_bitstream_pb_graph_pin_interc(fp, INPUT2INPUT_INTERC, - &(cur_pb_graph_node->input_pins[iport][ipin]), - cur_mode, - path_id, cur_sram_orgz_info); - } - } - break; - case SPICE_PB_PORT_OUTPUT: - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - fprintf(fp, "***** Output Port: %s[%d]*****\n", - cur_pb_graph_node->output_pins[iport][ipin].port->name, - cur_pb_graph_node->output_pins[iport][ipin].pin_number); - /* If this is a idle block, we set 0 to the selected edge*/ - /* Get the selected edge of current pin*/ - if (NULL == cur_pb) { - path_id = DEFAULT_PATH_ID; - } else { - assert(NULL != cur_pb); - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = cur_pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; - prev_node = pb_rr_nodes[node_index].prev_node; - /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ - /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ - if (OPEN == prev_node) { - path_id = DEFAULT_PATH_ID; - } else { - /* Find the path_id */ - path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); - assert(DEFAULT_PATH_ID != path_id); - } - // Path id for the sdc generation - pb_rr_nodes[node_index].id_path = path_id; - - if (OPEN != pb_rr_nodes[node_index].vpack_net_num) { - fprintf(fp, "***** Net name: %s *****\n", - vpack_net[pb_rr_nodes[node_index].vpack_net_num].name); - } - } - fpga_spice_generate_bitstream_pb_graph_pin_interc(fp, OUTPUT2OUTPUT_INTERC, - &(cur_pb_graph_node->output_pins[iport][ipin]), - cur_mode, - path_id, cur_sram_orgz_info); - } - } - break; - case SPICE_PB_PORT_CLOCK: - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - fprintf(fp, "***** Clock Port: %s[%d]*****\n", - cur_pb_graph_node->clock_pins[iport][ipin].port->name, - cur_pb_graph_node->clock_pins[iport][ipin].pin_number); - /* If this is a idle block, we set 0 to the selected edge*/ - /* Get the selected edge of current pin*/ - if (NULL == cur_pb) { - path_id = DEFAULT_PATH_ID; - } else { - assert(NULL != cur_pb); - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = cur_pb_graph_node->clock_pins[iport][ipin].rr_node_index_physical_pb; - prev_node = pb_rr_nodes[node_index].prev_node; - /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ - /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ - if (OPEN == prev_node) { - path_id = DEFAULT_PATH_ID; - } else { - /* Find the path_id */ - path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); - assert(DEFAULT_PATH_ID != path_id); - } - // Path id for the sdc generation - pb_rr_nodes[node_index].id_path = path_id; - - if (OPEN != pb_rr_nodes[node_index].vpack_net_num) { - fprintf(fp, "***** Net name: %s *****\n", - vpack_net[pb_rr_nodes[node_index].vpack_net_num].name); - } - } - fpga_spice_generate_bitstream_pb_graph_pin_interc(fp, INPUT2INPUT_INTERC, - &(cur_pb_graph_node->clock_pins[iport][ipin]), - cur_mode, - path_id, cur_sram_orgz_info); - - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pb port type!\n", - __FILE__, __LINE__); - exit(1); - } - - - return; -} - -/* Print the SPICE interconnections according to pb_graph */ -void fpga_spice_generate_bitstream_pb_graph_interc(FILE* fp, - t_pb_graph_node* cur_pb_graph_node, - t_phy_pb* cur_pb, - int select_mode_index, - t_sram_orgz_info* cur_sram_orgz_info) { - int ipb, jpb; - t_mode* cur_mode = NULL; - t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; - t_pb_graph_node* child_pb_graph_node = NULL; - t_phy_pb* child_pb = NULL; - - /* Check cur_pb_type*/ - if (NULL == cur_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Assign current mode */ - cur_mode = &(cur_pb_graph_node->pb_type->modes[select_mode_index]); - - /* We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins - * /|\ - * | - * input_pins, edges, output_pins - */ - fpga_spice_generate_bitstream_pb_graph_port_interc(fp, cur_pb_graph_node, - cur_pb, - SPICE_PB_PORT_OUTPUT, - cur_mode, - cur_sram_orgz_info); - - /* We check input_pins of child_pb_graph_node and its the input_edges - * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node - * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins - * /|\ - * | - * input_pins, edges, output_pins - */ - for (ipb = 0; ipb < cur_pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { - child_pb_graph_node = &(cur_pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]); - /* branch on empty pb */ - if (NULL == cur_pb) { - child_pb = NULL; - } else { - child_pb = &(cur_pb->child_pbs[ipb][jpb]); - } - /* For each child_pb_graph_node input pins*/ - fpga_spice_generate_bitstream_pb_graph_port_interc(fp, child_pb_graph_node, - child_pb, - SPICE_PB_PORT_INPUT, - cur_mode, - cur_sram_orgz_info); - /* TODO: for clock pins, we should do the same work */ - fpga_spice_generate_bitstream_pb_graph_port_interc(fp, child_pb_graph_node, - child_pb, - SPICE_PB_PORT_CLOCK, - cur_mode, - cur_sram_orgz_info); - } - } - - return; -} - -/* Print the subckt of a primitive pb */ -void fpga_spice_generate_bitstream_pb_primitive(FILE* fp, - t_phy_pb* prim_pb, - t_pb_type* prim_pb_type, - t_sram_orgz_info* cur_sram_orgz_info) { - /* Check cur_pb_graph_node*/ - if (NULL == prim_pb_type) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb_type.\n", - __FILE__, __LINE__); - exit(1); - } - assert (TRUE == prim_pb_type->parent_mode->define_physical_mode); - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* According to different type, we print netlist*/ - switch (prim_pb_type->spice_model->type) { - case SPICE_MODEL_LUT: - /* If this is a idle block we should set sram_bits to zero*/ - fpga_spice_generate_bitstream_pb_primitive_lut(fp, prim_pb, prim_pb_type, cur_sram_orgz_info); - break; - case SPICE_MODEL_FF: - assert(NULL != prim_pb_type->spice_model->model_netlist); - /* TODO : We should learn trigger type and initial value!!! and how to apply them!!! */ - fpga_spice_generate_bitstream_pb_generic_primitive(fp, prim_pb, prim_pb_type, cur_sram_orgz_info); - break; - case SPICE_MODEL_IOPAD: - assert(NULL != prim_pb_type->spice_model->model_netlist); - fpga_spice_generate_bitstream_pb_generic_primitive(fp, prim_pb, prim_pb_type, cur_sram_orgz_info); - break; - case SPICE_MODEL_HARDLOGIC: - assert(NULL != prim_pb_type->spice_model->model_netlist); - fpga_spice_generate_bitstream_pb_generic_primitive(fp, prim_pb, prim_pb_type, cur_sram_orgz_info); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of verilog_model(%s), should be [LUT|FF|HARD_LOGIC|IO]!\n", - __FILE__, __LINE__, prim_pb_type->spice_model->name); - exit(1); - } - - return; -} - -/* Print physical mode of pb_types and configure it to the idle pb_types recursively - * search the idle_mode until we reach the leaf node - */ -void fpga_spice_generate_bitstream_phy_pb_graph_node_rec(FILE* fp, - t_phy_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - int pb_type_index, - t_sram_orgz_info* cur_sram_orgz_info) { - int mode_index, ipb, jpb; - t_pb_type* cur_pb_type = NULL; - t_phy_pb* child_pb = NULL; - - /* Check cur_pb_graph_node*/ - if (NULL == cur_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - cur_pb_type = cur_pb_graph_node->pb_type; - - /* Recursively finish all the child pb_types*/ - if (NULL == cur_pb_type->spice_model) { - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Recursive*/ - /* Refer to pack/output_clustering.c [LINE 392] */ - /* Find the child pb that is mapped, and the mapping info is not stored in the physical mode ! */ - if (NULL == cur_pb) { - child_pb = NULL; - } else { - assert (NULL != cur_pb); - child_pb = get_phy_child_pb_for_phy_pb_graph_node(cur_pb, ipb, jpb); - } - fpga_spice_generate_bitstream_phy_pb_graph_node_rec(fp, child_pb, - &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), jpb, - cur_sram_orgz_info); - } - } - } - - /* Check if this has defined a spice_model*/ - if (NULL != cur_pb_type->spice_model) { - switch (cur_pb_type->class_type) { - case LUT_CLASS: - /* Special care for LUT !!! - * Mapped logical block information is stored in child_pbs - */ - fpga_spice_generate_bitstream_pb_primitive( fp, cur_pb, - cur_pb_type, - cur_sram_orgz_info); - break; - case LATCH_CLASS: - assert(0 == cur_pb_type->num_modes); - /* Consider the num_pb, create all the subckts*/ - fpga_spice_generate_bitstream_pb_primitive( fp, cur_pb, - cur_pb_type, - cur_sram_orgz_info); - break; - case UNKNOWN_CLASS: - case MEMORY_CLASS: - /* Consider the num_pb, create all the subckts*/ - fpga_spice_generate_bitstream_pb_primitive( fp, cur_pb, - cur_pb_type, - cur_sram_orgz_info); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n", - __FILE__, __LINE__, cur_pb_type->name); - exit(1); - } - /* Finish for primitive node, return */ - return; - } - - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); - - /* Print interconnections, set is_idle as TRUE*/ - fpga_spice_generate_bitstream_pb_graph_interc(fp, cur_pb_graph_node, cur_pb, mode_index, cur_sram_orgz_info); - - return; -} - - -/* Print an physical logic block - * Find the physical_mode in arch files, - * And print the verilog netlist into file - */ -void fpga_spice_generate_bitstream_one_physical_block(FILE* fp, - int x, int y, int z, - t_type_ptr type_descriptor, - t_sram_orgz_info* cur_sram_orgz_info) { - t_pb_graph_node* top_pb_graph_node = NULL; - t_block* mapped_block = NULL; - t_phy_pb* top_pb = NULL; - - /* Ensure we have a valid type_descriptor*/ - assert(NULL != type_descriptor); - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Go for the pb_types*/ - top_pb_graph_node = type_descriptor->pb_graph_head; - assert(NULL != top_pb_graph_node); - - /* Check in all the mapped blocks(clustered logic block), there is a match x,y,z*/ - mapped_block = search_mapped_block(x, y, z); - if (NULL != mapped_block) { - top_pb = (t_phy_pb*)mapped_block->phy_pb; - assert(NULL != top_pb); - } - - /* Recursively find all idle mode and print netlist*/ - fpga_spice_generate_bitstream_phy_pb_graph_node_rec(fp, top_pb, top_pb_graph_node, - z, cur_sram_orgz_info); - - return; -} - -/* Print the SPICE netlist for a I/O grid blocks */ -void fpga_spice_generate_bitstream_physical_grid_block(FILE* fp, - int ix, int iy, - t_arch* arch, - t_sram_orgz_info* cur_sram_orgz_info) { - int iz; - int capacity; - - /* Check */ - assert((!(0 > ix))&&(!(ix > (nx + 1)))); - assert((!(0 > iy))&&(!(iy > (ny + 1)))); - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* generate_grid_subckt, type_descriptor of each grid defines the capacity, - * for example, each grid may contains more than one top-level pb_types, such as I/O - */ - if ((NULL == grid[ix][iy].type) - ||(EMPTY_TYPE == grid[ix][iy].type) - ||(0 != grid[ix][iy].offset)) { - return; - } - - capacity= grid[ix][iy].type->capacity; - assert(0 < capacity); - - /* check capacity and if this has been mapped */ - for (iz = 0; iz < capacity; iz++) { - /* Print a NULL logic block...*/ - fpga_spice_generate_bitstream_one_physical_block(fp, ix, iy, iz, grid[ix][iy].type, cur_sram_orgz_info); - } - - return; -} - -/* Print all logic blocks SPICE models - * Each logic blocks in the grid that allocated for the FPGA - * will be printed. May have an additional option that only - * output the used logic blocks - */ -void fpga_spice_generate_bitstream_logic_block(char* lb_bitstream_log_file_path, - t_arch* arch, - t_sram_orgz_info* cur_sram_orgz_info) { - int ix, iy; - FILE* fp = NULL; - - /* Create a file handler */ - fp = fopen(lb_bitstream_log_file_path, "w"); - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in creating log file %s", - __FILE__, __LINE__, lb_bitstream_log_file_path); - exit(1); - } - - /* Check the grid*/ - if ((0 == nx)||(0 == ny)) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid grid size (nx=%d, ny=%d)!\n", __FILE__, __LINE__, nx, ny); - return; - } - - assert(NULL != grid); - - /* Print the core logic block one by one - * Note ix=0 and ix = nx + 1 are IO pads. They surround the core logic blocks - */ - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for core grids...\n"); - for (ix = 1; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - /* Ensure this is not a io */ - assert(IO_TYPE != grid[ix][iy].type); - /* Ensure a valid usage */ - assert((0 == grid[ix][iy].usage)||(0 < grid[ix][iy].usage)); - fpga_spice_generate_bitstream_physical_grid_block(fp, ix, iy, arch, cur_sram_orgz_info); - } - } - - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for IO grids...\n"); - /* Print the IO pads */ - /* Top side : x = 1 .. nx + 1, y = nx + 1 */ - iy = ny + 1; - for (ix = 1; ix < (nx + 1); ix++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - fpga_spice_generate_bitstream_physical_grid_block(fp, ix, iy, arch, cur_sram_orgz_info); - } - - /* Right side : x = nx + 1, y = 1 .. ny*/ - ix = nx + 1; - for (iy = 1; iy < (ny + 1); iy++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - fpga_spice_generate_bitstream_physical_grid_block(fp, ix, iy, arch, cur_sram_orgz_info); - } - /* Bottom side : x = 1 .. nx + 1, y = 0 */ - iy = 0; - for (ix = 1; ix < (nx + 1); ix++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - fpga_spice_generate_bitstream_physical_grid_block(fp, ix, iy, arch, cur_sram_orgz_info); - } - /* Left side: x = 0, y = 1 .. ny*/ - ix = 0; - for (iy = 1; iy < (ny + 1); iy++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - fpga_spice_generate_bitstream_physical_grid_block(fp, ix, iy, arch, cur_sram_orgz_info); - } - - /* Close log file */ - fclose(fp); - - /* Free */ - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.h deleted file mode 100644 index af50df3d7..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.h +++ /dev/null @@ -1,6 +0,0 @@ - - - -void fpga_spice_generate_bitstream_logic_block(char* lb_bitstream_log_file_path, - t_arch* arch, - t_sram_orgz_info* cur_sram_orgz_info) ; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_primitives.c deleted file mode 100644 index 112cf5716..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_primitives.c +++ /dev/null @@ -1,483 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "rr_graph_swseg.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_lut_utils.h" -#include "fpga_x2p_mux_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_bitstream_utils.h" - -/* Generate the bitstream of a generic primitive node: - * this node can be HARD LOGIC, IO, FF */ -void fpga_spice_generate_bitstream_pb_generic_primitive(FILE* fp, - t_phy_pb* prim_phy_pb, - t_pb_type* prim_pb_type, - t_sram_orgz_info* cur_sram_orgz_info) { - int num_sram_port = 0; - t_spice_model_port** sram_ports = NULL; - - t_spice_model* verilog_model = NULL; - - int i, mapped_logical_block_index; - int num_sram = 0; - int* sram_bits = NULL; - - /* For each SRAM, we could have multiple BLs/WLs */ - int num_bl_ports = 0; - t_spice_model_port** bl_port = NULL; - int num_wl_ports = 0; - t_spice_model_port** wl_port = NULL; - int num_bl_per_sram = 0; - int num_wl_per_sram = 0; - int expected_num_sram; - - int cur_num_sram = 0; - t_spice_model* mem_model = NULL; - - /* Ensure a valid physical pritimive pb */ - if (NULL == prim_pb_type) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Asserts */ - if (NULL != prim_phy_pb) { - assert (prim_phy_pb->pb_graph_node->pb_type->phy_pb_type == prim_pb_type); - } - assert (NULL != prim_pb_type->spice_model); - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - verilog_model = prim_pb_type->spice_model; - - assert((SPICE_MODEL_IOPAD == verilog_model->type) - || (SPICE_MODEL_HARDLOGIC == verilog_model->type) - || (SPICE_MODEL_FF == verilog_model->type)); - - /* Find ports*/ - sram_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - - /* if there is no SRAM ports, we can return */ - if ( 0 == num_sram_port) { - /* Back-annotate to logical block */ - if (NULL != prim_phy_pb) { - for (i = 0; i < prim_phy_pb->num_logical_blocks; i++) { - mapped_logical_block_index = prim_phy_pb->logical_block[i]; - logical_block[mapped_logical_block_index].mapped_spice_model = verilog_model; - logical_block[mapped_logical_block_index].mapped_spice_model_index = verilog_model->cnt; - } - } - /* Update the verilog_model counter */ - verilog_model->cnt++; - return; - } - - /* Initialize */ - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); - - num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); - - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_MEMORY_BANK: - /* Local wires */ - /* Find the number of BLs/WLs of each SRAM */ - /* Detect the SRAM SPICE model linked to this SRAM port */ - assert(NULL != sram_ports[0]->spice_model); - assert(SPICE_MODEL_SRAM == sram_ports[0]->spice_model->type); - find_bl_wl_ports_spice_model(sram_ports[0]->spice_model, - &num_bl_ports, &bl_port, &num_wl_ports, &wl_port); - assert(1 == num_bl_ports); - assert(1 == num_wl_ports); - num_bl_per_sram = bl_port[0]->size; - num_wl_per_sram = wl_port[0]->size; - break; - case SPICE_SRAM_STANDALONE: - case SPICE_SRAM_SCAN_CHAIN: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - /* what is the SRAM bit of a mode? */ - /* If logical block is not NULL, we need to decode the sram bit */ - if (NULL != prim_phy_pb) { - sram_bits = decode_mode_bits(prim_phy_pb->mode_bits, &expected_num_sram); - } else { /* get default mode_bits */ - sram_bits = decode_mode_bits(prim_pb_type->mode_bits, &expected_num_sram); - } - assert(expected_num_sram == num_sram); - - /* SRAM_bit will be later reconfigured according to operating mode */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_MEMORY_BANK: - cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - for (i = 0; i < num_sram; i++) { - /* Decode the SRAM bits to BL/WL bits. - * first half part is BL, the other half part is WL - */ - decode_and_add_sram_membank_conf_bit_to_llist(cur_sram_orgz_info, cur_num_sram + i, - num_bl_per_sram, num_wl_per_sram, - sram_bits[i]); - } - break; - case SPICE_SRAM_STANDALONE: - case SPICE_SRAM_SCAN_CHAIN: - /* Store the configuraion bit to linked-list */ - add_mux_conf_bits_to_llist(0, cur_sram_orgz_info, - num_sram, sram_bits, - verilog_model); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Back-annotate to logical block */ - if (NULL != prim_phy_pb) { - for (i = 0; i < prim_phy_pb->num_logical_blocks; i++) { - mapped_logical_block_index = prim_phy_pb->logical_block[i]; - logical_block[mapped_logical_block_index].mapped_spice_model = verilog_model; - logical_block[mapped_logical_block_index].mapped_spice_model_index = verilog_model->cnt; - } - } - /* Synchronize the internal counters of sram_orgz_info with generated bitstreams*/ - add_sram_conf_bits_to_sram_orgz_info(cur_sram_orgz_info, verilog_model); - - /* Print the encoding in SPICE netlist for debugging */ - if (NULL != prim_phy_pb) { - fprintf(fp, "***** Logic Block %s *****\n", - prim_phy_pb->spice_name_tag); - } - fprintf(fp, "***** SRAM bits for %s[%d] *****\n", - verilog_model->name, verilog_model->cnt); - fprintf(fp, "*****"); - for (i = 0; i < num_sram; i++) { - fprintf(fp, "%d", sram_bits[i]); - } - fprintf(fp, "*****\n"); - - - /* Update the verilog_model counter */ - verilog_model->cnt++; - - /*Free*/ - my_free(sram_ports); - my_free(sram_bits); - my_free(bl_port); - my_free(wl_port); - - return; -} - -void fpga_spice_generate_bitstream_pb_primitive_lut(FILE* fp, - t_phy_pb* prim_phy_pb, - t_pb_type* prim_pb_type, - t_sram_orgz_info* cur_sram_orgz_info) { - - int i, j; - int* lut_sram_bits = NULL; /* decoded SRAM bits */ - int* mode_sram_bits = NULL; /* decoded SRAM bits */ - int* sram_bits = NULL; /* decoded SRAM bits */ - int* truth_table_length = 0; - char*** truth_table = NULL; - int lut_size = 0; - int num_input_port = 0; - t_spice_model_port** input_ports = NULL; - int num_sram_port = 0; - t_spice_model_port** sram_ports = NULL; - t_spice_model_port* lut_sram_port = NULL; - t_spice_model_port* mode_bit_port = NULL; - int num_lut_pin_nets; - int* lut_pin_net = NULL; - int mapped_logical_block_index; - - int cur_num_sram = 0; - int num_sram = 0; - int num_lut_sram = 0; - int num_mode_sram = 0; - /* For each SRAM, we could have multiple BLs/WLs */ - int num_bl_ports = 0; - t_spice_model_port** bl_port = NULL; - int num_wl_ports = 0; - t_spice_model_port** wl_port = NULL; - int num_bl_per_sram = 0; - int num_wl_per_sram = 0; - t_spice_model* mem_model = NULL; - int expected_num_sram = 0; - t_spice_model* verilog_model = NULL; - - /* Ensure a valid physical pritimive pb */ - if (NULL == prim_pb_type) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid prim_pb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Asserts */ - if (NULL != prim_phy_pb) { - assert (prim_phy_pb->pb_graph_node->pb_type->phy_pb_type == prim_pb_type); - } - assert (NULL != prim_pb_type->spice_model); - - verilog_model = prim_pb_type->spice_model; - assert(SPICE_MODEL_LUT == verilog_model->type); - - /* Find the input ports for LUT size */ - input_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - assert(1 == num_input_port); - lut_size = input_ports[0]->size; - - /* Find SRAM ports for truth tables and mode bits */ - sram_ports = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - assert((1 == num_sram_port) || (2 == num_sram_port)); - for (i = 0; i < num_sram_port; i++) { - if (FALSE == sram_ports[i]->mode_select) { - lut_sram_port = sram_ports[i]; - num_lut_sram = sram_ports[i]->size; - assert (num_lut_sram == (int)pow(2.,(double)(lut_size))); - } else { - assert (TRUE == sram_ports[i]->mode_select); - mode_bit_port = sram_ports[i]; - num_mode_sram = sram_ports[i]->size; - } - } - /* Must have a lut_sram_port, while mode_bit_port is optional */ - assert (NULL != lut_sram_port); - - /* Count the number of configuration bits */ - num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); - /* Get memory model */ - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); - - /* Find the number of BLs/WLs of each SRAM */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_MEMORY_BANK: - /* Detect the SRAM SPICE model linked to this SRAM port */ - assert(NULL != sram_ports[0]->spice_model); - assert(SPICE_MODEL_SRAM == sram_ports[0]->spice_model->type); - find_bl_wl_ports_spice_model(sram_ports[0]->spice_model, - &num_bl_ports, &bl_port, &num_wl_ports, &wl_port); - assert(1 == num_bl_ports); - assert(1 == num_wl_ports); - num_bl_per_sram = bl_port[0]->size; - num_wl_per_sram = wl_port[0]->size; - /* Asserts */ - assert(num_bl_per_sram == num_wl_per_sram); - break; - case SPICE_SRAM_STANDALONE: - case SPICE_SRAM_SCAN_CHAIN: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", - __FILE__, __LINE__); - exit(1); - } - - /* If this is an idle LUT, we give an empty truth table */ - if ((NULL == prim_phy_pb) - || ((NULL != prim_phy_pb && (0 == prim_phy_pb->num_logical_blocks)))) { - lut_sram_bits = (int*) my_calloc ( num_lut_sram, sizeof(int)); - for (i = 0; i < num_lut_sram; i++) { - lut_sram_bits[i] = lut_sram_port->default_val; - } - } else { - assert (NULL != prim_phy_pb); - /* Allocate truth tables */ - truth_table_length = (int*) my_malloc (sizeof(int) * prim_phy_pb->num_logical_blocks); - truth_table = (char***) my_malloc (sizeof(char**) * prim_phy_pb->num_logical_blocks); - - /* Output log for debugging purpose */ - fprintf(fp, "***** Logic Block %s *****\n", - prim_phy_pb->spice_name_tag); - - /* Find truth tables and decode them one by one - * Fracturable LUT may have multiple truth tables, - * which should be grouped in a unique one - */ - for (i = 0; i < prim_phy_pb->num_logical_blocks; i++) { - mapped_logical_block_index = prim_phy_pb->logical_block[i]; - /* For wired LUT we provide a default truth table */ - if (TRUE == prim_phy_pb->is_wired_lut[i]) { - /* TODO: assign post-routing lut truth table!!!*/ - get_mapped_lut_phy_pb_input_pin_vpack_net_num(prim_phy_pb, &num_lut_pin_nets, &lut_pin_net); - truth_table[i] = assign_post_routing_wired_lut_truth_table(prim_phy_pb->rr_graph->rr_node[prim_phy_pb->lut_output_pb_graph_pin[i]->rr_node_index_physical_pb].vpack_net_num, - num_lut_pin_nets, lut_pin_net, &truth_table_length[i]); - } else { - assert (FALSE == prim_phy_pb->is_wired_lut[i]); - assert (VPACK_COMB == logical_block[mapped_logical_block_index].type); - /* Get the mapped vpack_net_num of this physical LUT pb */ - get_mapped_lut_phy_pb_input_pin_vpack_net_num(prim_phy_pb, &num_lut_pin_nets, &lut_pin_net); - /* consider LUT pin remapping when assign lut truth tables */ - /* Match truth table and post-routing results */ - truth_table[i] = assign_post_routing_lut_truth_table(&logical_block[mapped_logical_block_index], - num_lut_pin_nets, lut_pin_net, &truth_table_length[i]); - } - /* Adapt truth table for a fracturable LUT - * TODO: Determine fixed input bits for this truth table: - * 1. input bits within frac_level (all '-' if not specified) - * 2. input bits outside frac_level, decoded to its output mask (0 -> first part -> all '1') - */ - adapt_truth_table_for_frac_lut(prim_phy_pb->lut_output_pb_graph_pin[i], - truth_table_length[i], truth_table[i]); - /* Output log for debugging purpose */ - if (WIRED_LUT_LOGICAL_BLOCK_ID == mapped_logical_block_index) { - fprintf(fp, "***** Wired LUT: mapped to a buffer *****\n"); - } else { - fprintf(fp, "***** Mapped Logic Block[%d] %s *****\n", - i, logical_block[mapped_logical_block_index].name); - } - fprintf(fp, "***** Net map *****\n"); - for (j = 0; j < num_lut_pin_nets; j++) { - if (OPEN == lut_pin_net[j]) { - fprintf(fp, "OPEN, "); - } else { - assert (OPEN != lut_pin_net[j]); - fprintf(fp, "%s, ", vpack_net[lut_pin_net[j]].name); - } - } - fprintf(fp, "\n"); - fprintf(fp, "***** Truth Table *****\n"); - for (j = 0; j < truth_table_length[i]; j++) { - fprintf(fp, "%s\n", truth_table[i][j]); - } - } - /* Generate base sram bits*/ - lut_sram_bits = generate_frac_lut_sram_bits(prim_phy_pb, truth_table_length, truth_table, lut_sram_port->default_val); - } - - /* Add mode bits */ - if (NULL != mode_bit_port) { - if (NULL != prim_phy_pb) { - mode_sram_bits = decode_mode_bits(prim_phy_pb->mode_bits, &expected_num_sram); - } else { /* get default mode_bits */ - mode_sram_bits = decode_mode_bits(prim_pb_type->mode_bits, &expected_num_sram); - } - assert(expected_num_sram == num_mode_sram); - } - - /* Merge the SRAM bits from LUT SRAMs and Mode selection */ - assert ( num_sram == num_lut_sram + num_mode_sram ); - sram_bits = (int*)my_calloc(num_sram, sizeof(int)); - /* LUT SRAMs go first and then mode bits */ - memcpy(sram_bits, lut_sram_bits, num_lut_sram * sizeof(int)); - if (NULL != mode_bit_port) { - memcpy(sram_bits + num_lut_sram, mode_sram_bits, num_mode_sram * sizeof(int)); - } - - /* Decode the SRAM bits to BL/WL bits. */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_MEMORY_BANK: - cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - for (i = 0; i < num_sram; i++) { - /* TODO: should be more structural in coding !!! */ - /* Decode the SRAM bits to BL/WL bits. - * first half part is BL, the other half part is WL - */ - decode_and_add_sram_membank_conf_bit_to_llist(cur_sram_orgz_info, cur_num_sram + i, - num_bl_per_sram, num_wl_per_sram, - sram_bits[i]); - } - /* NUM_SRAM is set to be consistent with number of BL/WLs - * TODO: NUM_SRAM should be the as they are. - * Should use another variable i.e., num_bl - */ - break; - case SPICE_SRAM_STANDALONE: - case SPICE_SRAM_SCAN_CHAIN: - /* Store the configuraion bit to linked-list */ - add_mux_conf_bits_to_llist(0, cur_sram_orgz_info, - num_sram, sram_bits, - verilog_model); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Synchronize the internal counters of sram_orgz_info with generated bitstreams*/ - add_sram_conf_bits_to_sram_orgz_info(cur_sram_orgz_info, verilog_model); - - /* Back-annotate to logical block */ - if (NULL != prim_phy_pb) { - for (i = 0; i < prim_phy_pb->num_logical_blocks; i++) { - mapped_logical_block_index = prim_phy_pb->logical_block[i]; - logical_block[mapped_logical_block_index].mapped_spice_model = verilog_model; - logical_block[mapped_logical_block_index].mapped_spice_model_index = verilog_model->cnt; - } - } - - /* Print the encoding in SPICE netlist for debugging */ - fprintf(fp, "***** LUT SRAM bits for %s[%d] *****\n", - verilog_model->name, verilog_model->cnt); - fprintf(fp, "*****"); - for (i = 0; i < num_lut_sram; i++) { - fprintf(fp, "%d", lut_sram_bits[i]); - } - fprintf(fp, "*****\n"); - if (0 < num_mode_sram) { - fprintf(fp, "***** LUT Mode bits for %s[%d] *****\n", - verilog_model->name, verilog_model->cnt); - fprintf(fp, "*****"); - for (i = 0; i < num_mode_sram; i++) { - fprintf(fp, "%d", mode_sram_bits[i]); - } - fprintf(fp, "*****\n"); - } - - /* Update counter */ - verilog_model->cnt++; - - /*Free*/ - if (NULL != prim_phy_pb) { - my_free(lut_pin_net); - for (i = 0; i < prim_phy_pb->num_logical_blocks; i++) { - for (j = 0; j < truth_table_length[i]; j++) { - my_free(truth_table[i][j]); - } - my_free(truth_table[i]); - } - my_free(truth_table_length); - } - my_free(input_ports); - my_free(sram_ports); - my_free(sram_bits); - my_free(lut_sram_bits); - my_free(mode_sram_bits); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_primitives.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_primitives.h deleted file mode 100644 index 2caf5affa..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_primitives.h +++ /dev/null @@ -1,11 +0,0 @@ - - -void fpga_spice_generate_bitstream_pb_generic_primitive(FILE* fp, - t_phy_pb* prim_phy_pb, - t_pb_type* prim_pb_type, - t_sram_orgz_info* cur_sram_orgz_info); - -void fpga_spice_generate_bitstream_pb_primitive_lut(FILE* fp, - t_phy_pb* prim_phy_pb, - t_pb_type* prim_pb_type, - t_sram_orgz_info* cur_sram_orgz_info); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c deleted file mode 100644 index 5790c1ba4..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c +++ /dev/null @@ -1,925 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include SPICE support headers*/ -#include "linkedlist.h" -#include "rr_blocks.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_backannotate_utils.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_mux_utils.h" -#include "fpga_x2p_bitstream_utils.h" - -#include "fpga_bitstream_routing.h" - -/* Include Verilog support headers*/ - -/* Generate bitstream for a multiplexer of a switch block */ -static -void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp, - const t_arch& arch, - const RRGSB& rr_sb, - t_sram_orgz_info* cur_sram_orgz_info, - t_rr_node* cur_rr_node, - int mux_size, - t_rr_node** drive_rr_nodes, - int switch_index) { - t_spice_model* verilog_model = NULL; - int mux_level, path_id; - int num_mux_sram_bits = 0; - int* mux_sram_bits = NULL; - - /* Check */ - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check current rr_node is CHANX or CHANY*/ - assert((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); - - /* Allocate drive_rr_nodes according to the fan-in*/ - assert((2 == mux_size)||(2 < mux_size)); - - /* Get verilog model*/ - CircuitModelId circuit_model = switch_inf[switch_index].circuit_model; - verilog_model = switch_inf[switch_index].spice_model; - - /* Configuration bits for this MUX*/ - path_id = DEFAULT_PATH_ID; - for (int inode = 0; inode < mux_size; ++inode) { - if (drive_rr_nodes[inode] == &(rr_node[cur_rr_node->prev_node])) { - path_id = inode; - break; - } - } - - assert((DEFAULT_PATH_ID == path_id) || - ((DEFAULT_PATH_ID < path_id) &&(path_id < mux_size))); - - /* Depend on both technology and structure of this MUX*/ - const CircuitLibrary& circuit_lib = arch.spice->circuit_lib; - switch (circuit_lib.design_tech_type(circuit_model)) { - case SPICE_MODEL_DESIGN_CMOS: - decode_cmos_mux_sram_bits(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - case SPICE_MODEL_DESIGN_RRAM: - decode_rram_mux(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", - __FILE__, __LINE__, verilog_model->name); - exit(1); - } - - /* Print the encoding in SPICE netlist for debugging */ - fprintf(fp, "***** Switch Block [%lu][%lu] *****\n", - rr_sb.get_sb_x(), rr_sb.get_sb_y()); - fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n", - verilog_model->cnt, mux_level, path_id); - fprintf(fp, "*****"); - for (int ilevel = 0; ilevel < num_mux_sram_bits; ++ilevel) { - fprintf(fp, "%d", mux_sram_bits[ilevel]); - } - fprintf(fp, "*****\n\n"); - - /* Store the configuraion bit to linked-list */ - add_mux_conf_bits_to_llist(mux_size, cur_sram_orgz_info, - num_mux_sram_bits, mux_sram_bits, - verilog_model); - - /* Synchronize the sram_orgz_info with mem_bits */ - add_mux_conf_bits_to_sram_orgz_info(cur_sram_orgz_info, verilog_model, mux_size); - - /* update sram counter */ - verilog_model->cnt++; - - /* Free */ - my_free(mux_sram_bits); - - return; -} - - -/* Print the SPICE netlist of multiplexer that drive this rr_node */ -static -void fpga_spice_generate_bitstream_switch_box_mux(FILE* fp, - t_sb* cur_sb_info, - t_sram_orgz_info* cur_sram_orgz_info, - t_rr_node* cur_rr_node, - int mux_size, - t_rr_node** drive_rr_nodes, - int switch_index) { - int inode, ilevel; - t_spice_model* verilog_model = NULL; - int mux_level, path_id; - int num_mux_sram_bits = 0; - int* mux_sram_bits = NULL; - - /* Check */ - assert((!(0 > cur_sb_info->x))&&(!(cur_sb_info->x > (nx + 1)))); - assert((!(0 > cur_sb_info->y))&&(!(cur_sb_info->y > (ny + 1)))); - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check current rr_node is CHANX or CHANY*/ - assert((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); - - /* Allocate drive_rr_nodes according to the fan-in*/ - assert((2 == mux_size)||(2 < mux_size)); - - /* Get verilog model*/ - verilog_model = switch_inf[switch_index].spice_model; - - /* Configuration bits for this MUX*/ - path_id = DEFAULT_PATH_ID; - for (inode = 0; inode < mux_size; inode++) { - if (drive_rr_nodes[inode] == &(rr_node[cur_rr_node->prev_node])) { - path_id = inode; - break; - } - } - - assert((DEFAULT_PATH_ID == path_id) || - ((DEFAULT_PATH_ID < path_id) &&(path_id < mux_size))); - - /* Depend on both technology and structure of this MUX*/ - switch (verilog_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - decode_cmos_mux_sram_bits(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - case SPICE_MODEL_DESIGN_RRAM: - decode_rram_mux(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", - __FILE__, __LINE__, verilog_model->name); - exit(1); - } - - /* Print the encoding in SPICE netlist for debugging */ - fprintf(fp, "***** Switch Block [%d][%d] *****\n", - cur_sb_info->x, cur_sb_info->y); - fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n", - verilog_model->cnt, mux_level, path_id); - fprintf(fp, "*****"); - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - fprintf(fp, "%d", mux_sram_bits[ilevel]); - } - fprintf(fp, "*****\n\n"); - - /* Store the configuraion bit to linked-list */ - add_mux_conf_bits_to_llist(mux_size, cur_sram_orgz_info, - num_mux_sram_bits, mux_sram_bits, - verilog_model); - - /* Synchronize the sram_orgz_info with mem_bits */ - add_mux_conf_bits_to_sram_orgz_info(cur_sram_orgz_info, verilog_model, mux_size); - - /* update sram counter */ - verilog_model->cnt++; - - /* Free */ - my_free(mux_sram_bits); - - return; -} - -static -void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp, - const t_arch& arch, - const RRGSB& rr_sb, - t_sram_orgz_info* cur_sram_orgz_info, - enum e_side chan_side, - size_t chan_node_id) { - int num_drive_rr_nodes = 0; - t_rr_node** drive_rr_nodes = NULL; - - /* Check */ - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Get the rr_node */ - t_rr_node* cur_rr_node = rr_sb.get_chan_node(chan_side, chan_node_id); - - /* Determine if the interc lies inside a channel wire, that is interc between segments */ - /* Check each num_drive_rr_nodes, see if they appear in the cur_sb_info */ - if (true == rr_sb.is_sb_node_passing_wire(chan_side, chan_node_id)) { - num_drive_rr_nodes = 0; - drive_rr_nodes = NULL; - } else { - num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes; - drive_rr_nodes = cur_rr_node->drive_rr_nodes; - } - - if ( (0 == num_drive_rr_nodes) - || (1 == num_drive_rr_nodes) ) { - /* No bitstream generation required by a special direct connection*/ - } else if (1 < num_drive_rr_nodes) { - /* Print the multiplexer, fan_in >= 2 */ - fpga_spice_generate_bitstream_switch_box_mux(fp, arch, rr_sb, cur_sram_orgz_info, - cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]); - } /*Nothing should be done else*/ - - /* Free */ - - return; -} - - -static -void fpga_spice_generate_bitstream_switch_box_interc(FILE* fp, - t_sb* cur_sb_info, - t_sram_orgz_info* cur_sram_orgz_info, - int chan_side, - t_rr_node* cur_rr_node) { - int sb_x, sb_y; - int num_drive_rr_nodes = 0; - t_rr_node** drive_rr_nodes = NULL; - - sb_x = cur_sb_info->x; - sb_y = cur_sb_info->y; - - /* Check */ - assert((!(0 > sb_x))&&(!(sb_x > (nx + 1)))); - assert((!(0 > sb_y))&&(!(sb_y > (ny + 1)))); - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Determine if the interc lies inside a channel wire, that is interc between segments */ - /* Check each num_drive_rr_nodes, see if they appear in the cur_sb_info */ - if (TRUE == check_drive_rr_node_imply_short(*cur_sb_info, cur_rr_node, chan_side)) { - /* Double check if the interc lies inside a channel wire, that is interc between segments */ - assert(1 == is_rr_node_exist_opposite_side_in_sb_info(*cur_sb_info, cur_rr_node, chan_side)); - num_drive_rr_nodes = 0; - drive_rr_nodes = NULL; - } else { - num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes; - drive_rr_nodes = cur_rr_node->drive_rr_nodes; - } - - if ( (0 == num_drive_rr_nodes) - || (1 == num_drive_rr_nodes) ) { - /* No bitstream generation required by a special direct connection*/ - } else if (1 < num_drive_rr_nodes) { - /* Print the multiplexer, fan_in >= 2 */ - fpga_spice_generate_bitstream_switch_box_mux(fp, cur_sb_info, cur_sram_orgz_info, - cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]); - } /*Nothing should be done else*/ - - /* Free */ - - return; -} - -/* Task: Generate bitstream for a Switch Box. - * A Switch Box subckt consists of following ports: - * 1. Channel Y [x][y] inputs - * 2. Channel X [x+1][y] inputs - * 3. Channel Y [x][y-1] outputs - * 4. Channel X [x][y] outputs - * 5. Grid[x][y+1] Right side outputs pins - * 6. Grid[x+1][y+1] Left side output pins - * 7. Grid[x+1][y+1] Bottom side output pins - * 8. Grid[x+1][y] Top side output pins - * 9. Grid[x+1][y] Left side output pins - * 10. Grid[x][y] Right side output pins - * 11. Grid[x][y] Top side output pins - * 12. Grid[x][y+1] Bottom side output pins - * - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - */ -static -void fpga_spice_generate_bitstream_routing_switch_box_subckt(FILE* fp, - const t_arch& arch, - const RRGSB& rr_sb, - t_sram_orgz_info* cur_sram_orgz_info) { - /* Check */ - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Put down all the multiplexers */ - for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { - Side side_manager(side); - for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { - assert((CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) - ||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type)); - /* We care INC_DIRECTION tracks at this side*/ - if (OUT_PORT == rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { - fpga_spice_generate_bitstream_switch_box_interc(fp, arch, rr_sb, cur_sram_orgz_info, - side_manager.get_side(), - itrack); - } - } - } - - /* Check */ - - /* Free chan_rr_nodes */ - - return; -} - - -/* Task: Print the subckt of a Switch Box. - * A Switch Box subckt consists of following ports: - * 1. Channel Y [x][y] inputs - * 2. Channel X [x+1][y] inputs - * 3. Channel Y [x][y-1] outputs - * 4. Channel X [x][y] outputs - * 5. Grid[x][y+1] Right side outputs pins - * 6. Grid[x+1][y+1] Left side output pins - * 7. Grid[x+1][y+1] Bottom side output pins - * 8. Grid[x+1][y] Top side output pins - * 9. Grid[x+1][y] Left side output pins - * 10. Grid[x][y] Right side output pins - * 11. Grid[x][y] Top side output pins - * 12. Grid[x][y+1] Bottom side output pins - * - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - */ -static -void fpga_spice_generate_bitstream_routing_switch_box_subckt(FILE* fp, - t_sb* cur_sb_info, - t_sram_orgz_info* cur_sram_orgz_info) { - int itrack, side; - - /* Check */ - assert((!(0 > cur_sb_info->x))&&(!(cur_sb_info->x > (nx + 1)))); - assert((!(0 > cur_sb_info->y))&&(!(cur_sb_info->y > (ny + 1)))); - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Put down all the multiplexers */ - for (side = 0; side < cur_sb_info->num_sides; side++) { - for (itrack = 0; itrack < cur_sb_info->chan_width[side]; itrack++) { - assert((CHANX == cur_sb_info->chan_rr_node[side][itrack]->type) - ||(CHANY == cur_sb_info->chan_rr_node[side][itrack]->type)); - /* We care INC_DIRECTION tracks at this side*/ - if (OUT_PORT == cur_sb_info->chan_rr_node_direction[side][itrack]) { - fpga_spice_generate_bitstream_switch_box_interc(fp, cur_sb_info, cur_sram_orgz_info, - side, cur_sb_info->chan_rr_node[side][itrack]); - } - } - } - - /* Check */ - - /* Free chan_rr_nodes */ - - return; -} - -/* SRC rr_node is the IPIN of a grid.*/ -static -void fpga_spice_generate_bitstream_connection_box_mux(FILE* fp, - const RRGSB& rr_gsb, t_rr_type cb_type, - t_sram_orgz_info* cur_sram_orgz_info, - t_rr_node* src_rr_node) { - int mux_size = 0; - t_rr_node** drive_rr_nodes = NULL; - int inode, mux_level, path_id, switch_index; - t_spice_model* verilog_model = NULL; - int num_mux_sram_bits = 0; - int* mux_sram_bits = NULL; - int ilevel; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Find drive_rr_nodes*/ - mux_size = src_rr_node->num_drive_rr_nodes; - drive_rr_nodes = src_rr_node->drive_rr_nodes; - - /* Configuration bits for MUX*/ - path_id = DEFAULT_PATH_ID; - for (inode = 0; inode < mux_size; inode++) { - if (drive_rr_nodes[inode] == &(rr_node[src_rr_node->prev_node])) { - path_id = inode; - break; - } - } - assert((DEFAULT_PATH_ID == path_id) || - ((DEFAULT_PATH_ID < path_id) &&(path_id < mux_size))); - - switch_index = src_rr_node->drive_switches[DEFAULT_SWITCH_ID]; - - verilog_model = switch_inf[switch_index].spice_model; - - switch (verilog_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - decode_cmos_mux_sram_bits(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - case SPICE_MODEL_DESIGN_RRAM: - decode_rram_mux(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", - __FILE__, __LINE__, verilog_model->name); - } - - /* Print the encoding in SPICE netlist for debugging */ - fprintf(fp, "***** Connection Block %s *****\n", - rr_gsb.gen_cb_verilog_instance_name(cb_type)); - - fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n", - verilog_model->cnt, mux_level, path_id); - fprintf(fp, "*****"); - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - fprintf(fp, "%d", mux_sram_bits[ilevel]); - } - fprintf(fp, "*****\n\n"); - - /* Store the configuraion bit to linked-list */ - add_mux_conf_bits_to_llist(mux_size, cur_sram_orgz_info, - num_mux_sram_bits, mux_sram_bits, - verilog_model); - /* Synchronize the sram_orgz_info with mem_bits */ - add_mux_conf_bits_to_sram_orgz_info(cur_sram_orgz_info, verilog_model, mux_size); - - /* update sram counter */ - verilog_model->cnt++; - - /* Free */ - my_free(mux_sram_bits); - - return; -} - - -/* SRC rr_node is the IPIN of a grid.*/ -static -void fpga_spice_generate_bitstream_connection_box_mux(FILE* fp, - t_cb* cur_cb_info, - t_sram_orgz_info* cur_sram_orgz_info, - t_rr_node* src_rr_node) { - int mux_size = 0; - t_rr_node** drive_rr_nodes = NULL; - int inode, mux_level, path_id, switch_index; - t_spice_model* verilog_model = NULL; - int num_mux_sram_bits = 0; - int* mux_sram_bits = NULL; - int ilevel; - - /* Check */ - assert((!(0 > cur_cb_info->x))&&(!(cur_cb_info->x > (nx + 1)))); - assert((!(0 > cur_cb_info->y))&&(!(cur_cb_info->y > (ny + 1)))); - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Find drive_rr_nodes*/ - mux_size = src_rr_node->num_drive_rr_nodes; - drive_rr_nodes = src_rr_node->drive_rr_nodes; - - /* Configuration bits for MUX*/ - path_id = DEFAULT_PATH_ID; - for (inode = 0; inode < mux_size; inode++) { - if (drive_rr_nodes[inode] == &(rr_node[src_rr_node->prev_node])) { - path_id = inode; - break; - } - } - assert((DEFAULT_PATH_ID == path_id) || - ((DEFAULT_PATH_ID < path_id) &&(path_id < mux_size))); - - switch_index = src_rr_node->drive_switches[DEFAULT_SWITCH_ID]; - - verilog_model = switch_inf[switch_index].spice_model; - - switch (verilog_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - decode_cmos_mux_sram_bits(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - case SPICE_MODEL_DESIGN_RRAM: - decode_rram_mux(verilog_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", - __FILE__, __LINE__, verilog_model->name); - } - - /* Print the encoding in SPICE netlist for debugging */ - switch(cur_cb_info->type) { - case CHANX: - fprintf(fp, "***** Connection Block X-channel [%d][%d] *****\n", - cur_cb_info->x, cur_cb_info->y); - break; - case CHANY: - fprintf(fp, "***** Connection Block Y-channel [%d][%d] *****\n", - cur_cb_info->x, cur_cb_info->y); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n", - verilog_model->cnt, mux_level, path_id); - fprintf(fp, "*****"); - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - fprintf(fp, "%d", mux_sram_bits[ilevel]); - } - fprintf(fp, "*****\n\n"); - - /* Store the configuraion bit to linked-list */ - add_mux_conf_bits_to_llist(mux_size, cur_sram_orgz_info, - num_mux_sram_bits, mux_sram_bits, - verilog_model); - /* Synchronize the sram_orgz_info with mem_bits */ - add_mux_conf_bits_to_sram_orgz_info(cur_sram_orgz_info, verilog_model, mux_size); - - /* update sram counter */ - verilog_model->cnt++; - - /* Free */ - my_free(mux_sram_bits); - - return; -} - -static -void fpga_spice_generate_bitstream_connection_box_interc(FILE* fp, - t_cb* cur_cb_info, - t_sram_orgz_info* cur_sram_orgz_info, - t_rr_node* src_rr_node) { - /* Check */ - assert((!(0 > cur_cb_info->x))&&(!(cur_cb_info->x > (nx + 1)))); - assert((!(0 > cur_cb_info->y))&&(!(cur_cb_info->y > (ny + 1)))); - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - if (1 == src_rr_node->fan_in) { - /* No bitstream generation required by a special direct connection*/ - } else if (1 < src_rr_node->fan_in) { - /* Print the multiplexer, fan_in >= 2 */ - fpga_spice_generate_bitstream_connection_box_mux(fp, cur_cb_info, cur_sram_orgz_info, - src_rr_node); - } /*Nothing should be done else*/ - - return; -} - -static -void fpga_spice_generate_bitstream_connection_box_interc(FILE* fp, - const RRGSB& rr_gsb, t_rr_type cb_type, - t_sram_orgz_info* cur_sram_orgz_info, - t_rr_node* src_rr_node) { - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - if (1 == src_rr_node->fan_in) { - /* No bitstream generation required by a special direct connection*/ - } else if (1 < src_rr_node->fan_in) { - /* Print the multiplexer, fan_in >= 2 */ - fpga_spice_generate_bitstream_connection_box_mux(fp, rr_gsb, cb_type, cur_sram_orgz_info, - src_rr_node); - } /*Nothing should be done else*/ - - return; -} - - -/* Print connection boxes - * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY]) - * Actually it is very similiar to switch box but - * the difference is connection boxes connect Grid INPUT Pins to channels - * TODO: merge direct connections into CB - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y] | [x+1][y+1] | - * | | Connection | | - * -------------- Box_Y[x][y] -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * Connection | [x][y] | Connection - * Box_X[x][y] ---------- Box_X[x+1][y] - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y-1] | [x+1][y] | - * | | Connection | | - * --------------Box_Y[x][y-1]-------------- - */ -static -void fpga_spice_generate_bitstream_routing_connection_box_subckt(FILE* fp, - const RRGSB& rr_gsb, t_rr_type cb_type, - t_sram_orgz_info* cur_sram_orgz_info) { - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Print multiplexers or direct interconnect*/ - std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); - - for (size_t side = 0; side < cb_sides.size(); ++side) { - enum e_side cb_ipin_side = cb_sides[side]; - Side side_manager(cb_ipin_side); - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - fpga_spice_generate_bitstream_connection_box_interc(fp, rr_gsb, cb_type, cur_sram_orgz_info, - rr_gsb.get_ipin_node(cb_ipin_side, inode)); - } - } - - /* Check */ - - /* Free */ - - return; -} - - -/* Print connection boxes - * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY]) - * Actually it is very similiar to switch box but - * the difference is connection boxes connect Grid INPUT Pins to channels - * TODO: merge direct connections into CB - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y] | [x+1][y+1] | - * | | Connection | | - * -------------- Box_Y[x][y] -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * Connection | [x][y] | Connection - * Box_X[x][y] ---------- Box_X[x+1][y] - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y-1] | [x+1][y] | - * | | Connection | | - * --------------Box_Y[x][y-1]-------------- - */ -static -void fpga_spice_generate_bitstream_routing_connection_box_subckt(FILE* fp, - t_cb* cur_cb_info, - t_sram_orgz_info* cur_sram_orgz_info) { - int inode, side; - int side_cnt = 0; - - /* Check */ - assert((!(0 > cur_cb_info->x))&&(!(cur_cb_info->x > (nx + 1)))); - assert((!(0 > cur_cb_info->y))&&(!(cur_cb_info->y > (ny + 1)))); - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Print multiplexers or direct interconnect*/ - side_cnt = 0; - for (side = 0; side < cur_cb_info->num_sides; side++) { - /* Bypass side with zero IPINs*/ - if (0 == cur_cb_info->num_ipin_rr_nodes[side]) { - continue; - } - side_cnt++; - assert(0 < cur_cb_info->num_ipin_rr_nodes[side]); - assert(NULL != cur_cb_info->ipin_rr_node[side]); - for (inode = 0; inode < cur_cb_info->num_ipin_rr_nodes[side]; inode++) { - fpga_spice_generate_bitstream_connection_box_interc(fp, cur_cb_info, cur_sram_orgz_info, - cur_cb_info->ipin_rr_node[side][inode]); - } - } - - /* Check */ - - /* Free */ - - return; -} - -/* Top Function*/ -/* Build the routing resource SPICE sub-circuits*/ -void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log_file_path, - const t_arch& arch, - t_det_routing_arch* routing_arch, - t_sram_orgz_info* cur_sram_orgz_info, - boolean compact_routing_hierarchy) { - FILE* fp = NULL; - - assert(UNI_DIRECTIONAL == routing_arch->directionality); - - /* Create a file handler */ - fp = fopen(routing_bitstream_log_file_path, "w"); - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in creating log file %s", - __FILE__, __LINE__, routing_bitstream_log_file_path); - exit(1); - } - - /* Two major tasks: - * 1. Generate bitstreams for Switch Blocks - * 2. Generate bitstreams for Connection Blocks - */ - /* Now: First task: Routing channels - * Sub-circuits are named as chanx[ix][iy] or chany[ix][iy] for horizontal or vertical channels - * each channels consist of a number of routing tracks. (Actually they are metal wires) - * We only support single-driver routing architecture. - * The direction is defined as INC_DIRECTION ------> and DEC_DIRECTION <-------- for chanx - * The direction is defined as INC_DIRECTION /|\ and DEC_DIRECTION | for chany - * | | - * | | - * | \|/ - * For INC_DIRECTION chanx, the inputs are at the left of channels, the outputs are at the right of channels - * For DEC_DIRECTION chanx, the inputs are at the right of channels, the outputs are at the left of channels - * For INC_DIRECTION chany, the inputs are at the bottom of channels, the outputs are at the top of channels - * For DEC_DIRECTION chany, the inputs are at the top of channels, the outputs are at the bottom of channels - */ - - /* Switch Boxes*/ - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Switch blocks...\n"); - if (TRUE == compact_routing_hierarchy) { - DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range(); - for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy); - fpga_spice_generate_bitstream_routing_switch_box_subckt(fp, arch, - rr_sb, cur_sram_orgz_info); - } - } - } else { - for (int ix = 0; ix < (nx + 1); ++ix) { - for (int iy = 0; iy < (ny + 1); ++iy) { - /* vpr_printf(TIO_MESSAGE_INFO, "Writing Switch Boxes[%d][%d]...\n", ix, iy); */ - update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); - fpga_spice_generate_bitstream_routing_switch_box_subckt(fp, - &(sb_info[ix][iy]), cur_sram_orgz_info); - update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); - } - } - } - - /* Connection Boxes */ - if (TRUE == compact_routing_hierarchy) { - DeviceCoordinator gsb_range = device_rr_gsb.get_gsb_range(); - - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Connection blocks ...\n"); - - for (size_t ix = 0; ix < gsb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < gsb_range.get_y(); ++iy) { - const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); - /* X - channels [1...nx][0..ny]*/ - if ((TRUE == is_cb_exist(CHANX, ix, iy)) - &&(true == rr_gsb.is_cb_exist(CHANX))) { - fpga_spice_generate_bitstream_routing_connection_box_subckt(fp, - rr_gsb, CHANX, - cur_sram_orgz_info); - } - /* Y - channels [1...ny][0..nx]*/ - if ((TRUE == is_cb_exist(CHANY, ix, iy)) - &&(true == rr_gsb.is_cb_exist(CHANY))) { - fpga_spice_generate_bitstream_routing_connection_box_subckt(fp, - rr_gsb, CHANY, - cur_sram_orgz_info); - } - } - } - } else { - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Connection blocks - X direction ...\n"); - /* X - channels [1...nx][0..ny]*/ - for (int iy = 0; iy < (ny + 1); ++iy) { - for (int ix = 1; ix < (nx + 1); ++ix) { - /* vpr_printf(TIO_MESSAGE_INFO, "Writing X-direction Connection Boxes[%d][%d]...\n", ix, iy); */ - update_spice_models_routing_index_low(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); - if ((TRUE == is_cb_exist(CHANX, ix, iy)) - &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { - fpga_spice_generate_bitstream_routing_connection_box_subckt(fp, - &(cbx_info[ix][iy]), cur_sram_orgz_info); - } - update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); - } - } - /* Y - channels [1...ny][0..nx]*/ - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Connection blocks - Y direction ...\n"); - for (int ix = 0; ix < (nx + 1); ++ix) { - for (int iy = 1; iy < (ny + 1); ++iy) { - /* vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Connection Boxes[%d][%d]...\n", ix, iy); */ - update_spice_models_routing_index_low(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); - if ((TRUE == is_cb_exist(CHANY, ix, iy)) - &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { - fpga_spice_generate_bitstream_routing_connection_box_subckt(fp, - &(cby_info[ix][iy]), cur_sram_orgz_info); - } - update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); - } - } - } - - /* Close log file */ - fclose(fp); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.h deleted file mode 100644 index 51df5bdd7..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.h +++ /dev/null @@ -1,7 +0,0 @@ - - -void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log_file_path, - const t_arch& arch, - t_det_routing_arch* routing_arch, - t_sram_orgz_info* cur_sram_orgz_info, - boolean compact_routing_hierarchy); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/clb_pin_remap_util.c b/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/clb_pin_remap_util.c deleted file mode 100644 index 8924029f9..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/clb_pin_remap_util.c +++ /dev/null @@ -1,700 +0,0 @@ -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "heapsort.h" -#include "net_delay.h" -#include "path_delay.h" - -/* CLB PIN REMAP */ -#include "clb_pin_remap_util.h" - -int pin_side_count(int pin_side[]) { - int cnt = 0; - int side = 0; - - for (side = 0; side < 4; side++) { - cnt += pin_side[side]; - } - - return cnt; -} - -/* Malloc pin_side[4] - * If the pin appear at this side, set pin_side[side] to 1 - */ -void find_blk_net_pin_sides(t_block target_blk, - int pin_height, - int pin_index, - int** pin_side) { - int side; - - /* Check */ - assert(NULL != target_blk.type); - assert((!(0 > pin_height))&&(pin_height < target_blk.type->height)); - /* Allocate */ - (*pin_side) = NULL; - (*pin_side) = (int*)my_malloc(sizeof(int)*4); - - for (side = 0; side < 4; side++) { - /* Initialize */ - (*pin_side)[side] = 0; - /* Special care for IO_TYPE */ - if (IO_TYPE == target_blk.type) { - if ((0 == target_blk.x)&&(RIGHT == side)) { - /* LEFT side IO only has RIGHT side ports */ - (*pin_side)[side] = target_blk.type->pinloc[pin_height][side][pin_index]; - } else if (((ny+1) == target_blk.y)&&(BOTTOM == side)) { - /* TOP side IO only has BOTTOM side ports */ - (*pin_side)[side] = target_blk.type->pinloc[pin_height][side][pin_index]; - } else if (((nx+1) == target_blk.x)&&(LEFT == side)) { - /* RIGHT side IO only has LEFT side ports */ - (*pin_side)[side] = target_blk.type->pinloc[pin_height][side][pin_index]; - } else if ((0 == target_blk.y)&&(TOP == side)) { - /* BOTTOM side IO only has TOP side ports */ - (*pin_side)[side] = target_blk.type->pinloc[pin_height][side][pin_index]; - } - } else { - (*pin_side)[side] = target_blk.type->pinloc[pin_height][side][pin_index]; - } - } - - return; -} - -/* Find the pin side of one block net, - * Here the pin is allowed to appear at only one side - */ -int find_blk_net_pin_side(t_block target_blk, - int pin_height, - int pin_index) { - int* pin_sides = NULL; - int i = -1; - - find_blk_net_pin_sides(target_blk, pin_height, - pin_index, &pin_sides); - - assert(1 == pin_side_count(pin_sides)); - - for (i = 0; i < 4; i++) { - if (1 == pin_sides[i]) { - return i; - } - } - - return -1; -} - -void find_blk_net_type_pins(int n_blks, t_block* blk, - int net_index, - int blk_index, - int* num_pins, - enum e_side** pin_side, - int** pin_index) { - t_type_ptr blk_type = NULL; - int jpin, iside = 0; - int net_pin_cnt = 0; - - /* Initialize */ - (*num_pins) = 0; - - /* Check index range */ - assert(blk_index < n_blks); - /* Find the type_descriptor*/ - blk_type = blk[blk_index].type; - assert(NULL != blk_type); - /* Find the port */ - for (jpin = 0; jpin < blk_type->num_pins; jpin++) { - if (net_index == blk[blk_index].nets[jpin]) { - /* Special for IO_TYPE */ - if (IO_TYPE == blk_type) { - /* LEFT side IO only has RIGHT side ports */ - if (0 == blk[blk_index].x) { - assert((0 < blk[blk_index].y)&&(blk[blk_index].y < (ny+1))); - assert(1 == blk_type->pinloc[blk_type->pin_height[jpin]][RIGHT][jpin]); - //(*pin_side) = RIGHT; - (*num_pins)++; - /* TOP side IO only has BOTTOM side ports */ - } else if ((ny+1) == blk[blk_index].y) { - assert((0 < blk[blk_index].x)&&(blk[blk_index].x < (nx+1))); - assert(1 == blk_type->pinloc[blk_type->pin_height[jpin]][BOTTOM][jpin]); - //(*pin_side) = BOTTOM; - (*num_pins)++; - /* RIGHT side IO only has LEFT side ports */ - } else if ((nx+1) == blk[blk_index].x) { - assert((0 < blk[blk_index].y)&&(blk[blk_index].y < (ny+1))); - assert(1 == blk_type->pinloc[blk_type->pin_height[jpin]][LEFT][jpin]); - //(*pin_side) = LEFT; - (*num_pins)++; - /* BOTTOM side IO only has TOP side ports */ - } else if (0 == blk[blk_index].y) { - assert((0 < blk[blk_index].x)&&(blk[blk_index].x < (nx+1))); - assert(1 == blk_type->pinloc[blk_type->pin_height[jpin]][TOP][jpin]); - //(*pin_side) = TOP; - (*num_pins)++; - } - } else { - for (iside = 0; iside < 4; iside++) { - if (1 == blk_type->pinloc[blk[blk_index].z][iside][jpin]) { - (*num_pins)++; - } - } - } - } - } - - /* Allocate */ - if (0 == (*num_pins)) { - return; - } - (*pin_side) = (enum e_side*)my_malloc((*num_pins)*sizeof(enum e_side)); - (*pin_index) = (int*)my_malloc((*num_pins)*sizeof(int)); - - /* Fill the array */ - for (jpin = 0; jpin < blk_type->num_pins; jpin++) { - if (net_index == blk[blk_index].nets[jpin]) { - /* Special for IO_TYPE */ - if (IO_TYPE == blk_type) { - /* LEFT side IO only has RIGHT side ports */ - if (0 == blk[blk_index].x) { - assert((0 < blk[blk_index].y)&&(blk[blk_index].y < (ny+1))); - assert(1 == blk_type->pinloc[blk_type->pin_height[jpin]][RIGHT][jpin]); - (*pin_side)[net_pin_cnt] = RIGHT; - (*pin_index)[net_pin_cnt] = jpin; - net_pin_cnt++; - /* TOP side IO only has BOTTOM side ports */ - } else if ((ny+1) == blk[blk_index].y) { - assert((0 < blk[blk_index].x)&&(blk[blk_index].x < (nx+1))); - assert(1 == blk_type->pinloc[blk_type->pin_height[jpin]][BOTTOM][jpin]); - (*pin_side)[net_pin_cnt] = BOTTOM; - (*pin_index)[net_pin_cnt] = jpin; - net_pin_cnt++; - /* RIGHT side IO only has LEFT side ports */ - } else if ((nx+1) == blk[blk_index].x) { - assert((0 < blk[blk_index].y)&&(blk[blk_index].y < (ny+1))); - assert(1 == blk_type->pinloc[blk_type->pin_height[jpin]][LEFT][jpin]); - (*pin_side)[net_pin_cnt] = LEFT; - (*pin_index)[net_pin_cnt] = jpin; - net_pin_cnt++; - /* BOTTOM side IO only has TOP side ports */ - } else if (0 == blk[blk_index].y) { - assert((0 < blk[blk_index].x)&&(blk[blk_index].x < (nx+1))); - assert(1 == blk_type->pinloc[blk_type->pin_height[jpin]][TOP][jpin]); - (*pin_side)[net_pin_cnt] = TOP; - (*pin_index)[net_pin_cnt] = jpin; - net_pin_cnt++; - } - } else { - for (iside = 0; iside < 4; iside++) { - if (1 == blk_type->pinloc[blk[blk_index].z][iside][jpin]) { - (*pin_side)[net_pin_cnt] = (enum e_side)iside; - (*pin_index)[net_pin_cnt] = jpin; - net_pin_cnt++; - } - } - } - } - } - -} - -int check_src_blk_pin(int n_blks, t_block* blk, - int net_index, - int src_blk_index, - //int src_blk_port_index, - int src_blk_pin_index) { - int ret = 1; - t_type_ptr blk_type = NULL; - int jpin, net_pin_class; - int net_pin_cnt = 0; - - /* Check index range */ - assert(src_blk_index < n_blks); - /* Find the type_descriptor*/ - blk_type = blk[src_blk_index].type; - assert(NULL != blk_type); - /* Find the port */ - for (jpin = 0; jpin < blk_type->num_pins; jpin++) { - if (net_index == blk[src_blk_index].nets[jpin]) { - net_pin_class = blk_type->pin_class[jpin]; - assert(DRIVER == blk_type->class_inf[net_pin_class].type); - /* Special for IO_TYPE */ - if (IO_TYPE == blk_type) { - /* LEFT side IO only has RIGHT side ports */ - if (0 == blk[src_blk_index].x) { - assert((0 < blk[src_blk_index].y)&&(blk[src_blk_index].y < (ny+1))); - assert(1 == blk_type->pinloc[blk_type->pin_height[jpin]][RIGHT][jpin]); - net_pin_cnt++; - /* TOP side IO only has BOTTOM side ports */ - } else if ((ny+1) == blk[src_blk_index].y) { - assert((0 < blk[src_blk_index].x)&&(blk[src_blk_index].x < (nx+1))); - assert(1 == blk_type->pinloc[blk_type->pin_height[jpin]][BOTTOM][jpin]); - net_pin_cnt++; - /* RIGHT side IO only has LEFT side ports */ - } else if ((nx+1) == blk[src_blk_index].x) { - assert((0 < blk[src_blk_index].y)&&(blk[src_blk_index].y < (ny+1))); - assert(1 == blk_type->pinloc[blk_type->pin_height[jpin]][LEFT][jpin]); - net_pin_cnt++; - /* BOTTOM side IO only has TOP side ports */ - } else if (0 == blk[src_blk_index].y) { - assert((0 < blk[src_blk_index].x)&&(blk[src_blk_index].x < (nx+1))); - assert(1 == blk_type->pinloc[blk_type->pin_height[jpin]][TOP][jpin]); - net_pin_cnt++; - } - } else { - net_pin_cnt++; - } - } - } - assert(1 == net_pin_cnt); /* TODO: May conflict with I/O TYPE*/ - /* The port should be an output port */ - //assert(src_blk_port_index < blk[src_blk_index].pb->pb_graph_node->pb_type->num_ports); - //assert(OUT_PORT == blk[src_blk_index].pb->pb_graph_node->pb_type->ports[src_blk_port_index].type); - - return ret; -} - -int check_des_blk_pin(int n_blks, t_block* blk, - int net_index, - int des_blk_index, - //int des_blk_port_index, - int des_blk_pin_index) { - int ret = 1; - t_type_ptr blk_type = NULL; - int jpin, net_pin_class; - int net_pin_cnt = 0; - - /* Check index range */ - assert(des_blk_index < n_blks); - /* Find the type_descriptor*/ - blk_type = blk[des_blk_index].type; - assert(NULL != blk_type); - /* Find the port */ - for (jpin = 0; jpin < blk_type->num_pins; jpin++) { - if (net_index == blk[des_blk_index].nets[jpin]) { - net_pin_class = blk_type->pin_class[jpin]; - assert(RECEIVER == blk_type->class_inf[net_pin_class].type); - net_pin_cnt++; - } - } - assert(1 == net_pin_cnt); /* TODO: May conflict with I/O TYPE*/ - /* The port should be an output port */ - //assert(des_blk_port_index < blk[des_blk_index].pb->pb_graph_node->pb_type->num_ports); - //assert(IN_PORT == blk[des_blk_index].pb->pb_graph_node->pb_type->ports[des_blk_port_index].type); - - return ret; -} - -void esti_pin_chan_coordinate(int* pin_x, int* pin_y, - t_block blk, int pin_side, int pin_index) { - /* Initialize */ - (*pin_x) = blk.x; - (*pin_y) = blk.y; - - /* For hetergenous block, pin_y should be added by offset */ - assert(NULL != blk.type); - (*pin_y) += blk.type->pin_height[pin_index]; - - switch (pin_side) { - case TOP: - (*pin_y)++; - break; - case BOTTOM: - break; - case LEFT: - break; - case RIGHT: - (*pin_x)++; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, LINE[%d])Invalid side!\n", __FILE__, __LINE__); - exit(1); - } -} - -int count_blk_one_class_num_conflict(t_block* target_blk, int class_index, - int* is_pin_conflict) { - int ipin, class_num_pins, blk_pin_index; - int num_conflict = 0; - - assert(NULL != target_blk); - assert(NULL != target_blk->type); - - class_num_pins = target_blk->type->class_inf[class_index].num_pins; - /* Check conflict number */ - num_conflict = 0; - for (ipin = 0; ipin < class_num_pins; ipin++) { - blk_pin_index = target_blk->type->class_inf[class_index].pinlist[ipin]; - if (1 == is_pin_conflict[blk_pin_index]) { - num_conflict++; - } - } - - return num_conflict; -} - -/* Return an array, each element is the index of pin in target_blk */ -int* sort_one_class_conflict_pins_by_low_slack(t_block* target_blk, int class_index, - int* is_pin_conflict, int* num_conflict, - t_slack* slack) { - int* ret_list = NULL; - int ipin, class_num_pins, blk_pin_index; - int net_index, net_sink_index; - int* slack_pin_index = NULL; - int* sorted_slack_pin_index= NULL; - float* slack_values = NULL; - int cur = 0; - - assert(NULL != target_blk); - assert(NULL != target_blk->type); - assert(RECEIVER == target_blk->type->class_inf[class_index].type); - - class_num_pins = target_blk->type->class_inf[class_index].num_pins; - /* Check conflict number */ - (*num_conflict) = count_blk_one_class_num_conflict(target_blk, class_index, is_pin_conflict); - - ret_list = (int*)my_malloc(sizeof(int)*(*num_conflict)); - slack_pin_index = (int*)my_malloc(sizeof(int)*(*num_conflict)); - sorted_slack_pin_index = (int*)my_malloc(sizeof(int)*(*num_conflict)); - slack_values = (float*)my_malloc(sizeof(float)*(*num_conflict)); - - cur = 0; - for (ipin = 0; ipin < class_num_pins; ipin++) { - blk_pin_index = target_blk->type->class_inf[class_index].pinlist[ipin]; - if (1 == is_pin_conflict[blk_pin_index]) { - net_index = target_blk->nets[blk_pin_index]; - net_sink_index = target_blk->nets_sink_index[blk_pin_index]; - slack_pin_index[cur] = blk_pin_index; - slack_values[cur] = slack->slack[net_index][net_sink_index]; - cur++; - } - } - assert(cur == (*num_conflict)); - /* Use heapsort */ - heapsort(sorted_slack_pin_index, slack_values, (*num_conflict), 1); - - /* load ret_list*/ - for (ipin = 0; ipin < (*num_conflict); ipin++) { - ret_list[ipin] = slack_pin_index[sorted_slack_pin_index[(*num_conflict) - 1 - ipin]]; - //ret_list[ipin] = slack_pin_index[sorted_slack_pin_index[ipin]]; - } - - /* Free */ - my_free(slack_pin_index); - my_free(sorted_slack_pin_index); - my_free(slack_values); - - return ret_list; -} - -/* Check if swap the 2 pins, each prefer_side can be satified. - * return 1 if both can be satified. - */ -int is_swap2pins_match_prefer_side(int pin0_cur_side, int* pin0_prefer_side, - int pin1_cur_side, int* pin1_prefer_side) { - /* Check */ - assert((!(0 > pin0_cur_side)&&(pin0_cur_side < 4))); - assert((!(0 > pin1_cur_side)&&(pin1_cur_side < 4))); - /* match?*/ - if ((1 == pin0_prefer_side[pin1_cur_side])&&(1 == pin1_prefer_side[pin0_cur_side])) { - return 1; - } - - return 0; -} - -int is_type_pin_in_class(t_type_ptr type, - int class_index, int pin_index) { - int ipin, blk_pin_index; - int is_pin_in_class = 0; - - assert(NULL != type); - assert((!(0 > class_index))&&(class_index < type->num_class)); - assert((!(0 > pin_index))&&(pin_index < type->num_pins)); - /* Check pin in this class */ - for (ipin = 0; ipin < type->class_inf[class_index].num_pins; ipin++) { - blk_pin_index = type->class_inf[class_index].pinlist[ipin]; - if (pin_index == blk_pin_index) { - is_pin_in_class++; - } - } - - return is_pin_in_class; -} - -/* Find all the to_rr_nodes that connected to src_pb pin */ -void find_src_pb_pin_to_rr_nodes(t_pb* src_pb, - int src_rr_node_index, - int* num_pin_to_rr_nodes, - t_rr_node*** to_rr_node) { - int cur, iedge, to_node, mode_index; - t_rr_node* local_rr_graph = NULL; - - /* Check */ - assert(NULL != src_pb); - /* Load local rr_graph */ - assert(NULL != src_pb->rr_graph); - local_rr_graph = src_pb->rr_graph; - /* Find the selected_mode */ - mode_index = src_pb->mode; - - /* Initialize */ - (*num_pin_to_rr_nodes) = 0; - (*to_rr_node) = NULL; - - /* Return if the net_info infers OPEN */ - if (OPEN == local_rr_graph[src_rr_node_index].net_num) { - return; - } - - /* Count the number */ - for (iedge = 0; iedge < local_rr_graph[src_rr_node_index].num_edges; iedge++) { - to_node = local_rr_graph[src_rr_node_index].edges[iedge]; - /* Check if this infer a connection */ - if ((src_rr_node_index == local_rr_graph[to_node].prev_node) - &&(iedge == local_rr_graph[to_node].prev_edge) - /* Make sure in the same mode */ - &&(mode_index == local_rr_graph[to_node].pb_graph_pin->parent_node->pb_type->parent_mode->index)) { - (*num_pin_to_rr_nodes)++; - } - } - /* Malloc */ - (*to_rr_node) = (t_rr_node**)my_malloc(sizeof(t_rr_node*)*(*num_pin_to_rr_nodes)); - /* Fill the return list */ - cur = 0; - for (iedge = 0; iedge < local_rr_graph[src_rr_node_index].num_edges; iedge++) { - to_node = local_rr_graph[src_rr_node_index].edges[iedge]; - /* Check if this infer a connection */ - if ((src_rr_node_index == local_rr_graph[to_node].prev_node) - &&(iedge == local_rr_graph[to_node].prev_edge) - /* Make sure in the same mode */ - &&(mode_index == local_rr_graph[to_node].pb_graph_pin->parent_node->pb_type->parent_mode->index)) { - (*to_rr_node)[cur] = &(local_rr_graph[to_node]); - cur++; - } - } - assert(cur == (*num_pin_to_rr_nodes)); - - return; -} - -void connect_pb_des_pin_to_src_pin(t_pb* src_pb, - int src_rr_node_index, - int des_rr_node_index) { - int iedge, mode_index, prev_edge, edge_cnt; - t_rr_node* local_rr_graph = NULL; - - /* Check */ - assert(NULL != src_pb); - /* Load local rr_graph */ - assert(NULL != src_pb->rr_graph); - local_rr_graph = src_pb->rr_graph; - /* Find the selected_mode */ - mode_index = src_pb->mode; - /* Make sure in the same mode */ - assert(mode_index == local_rr_graph[des_rr_node_index].pb_graph_pin->parent_node->pb_type->parent_mode->index); - - /* Make sure the src_pin has an edge to des_pin */ - edge_cnt = 0; - for (iedge = 0; iedge < local_rr_graph[src_rr_node_index].num_edges; iedge++) { - if (des_rr_node_index == local_rr_graph[src_rr_node_index].edges[iedge]) { - prev_edge = iedge; - edge_cnt++; - } - } - assert(1 == edge_cnt); - /* Connect: give prev_edge, prev_node */ - local_rr_graph[des_rr_node_index].prev_node = src_rr_node_index; - local_rr_graph[des_rr_node_index].prev_edge = prev_edge; - - return; -} - -/* Swap 2 pins, in the same block*/ -void swap_blk_same_class_2pins(t_block* target_blk, int n_nets, t_net* nets, - int pin0_index, int pin1_index) { - int pin0_class_index, pin1_class_index; - int inode, net_swap, net_index, net_sink_index; - t_rr_node* local_rr_graph = NULL; - t_rr_node* pin0_rr_node = NULL; - t_rr_node* pin1_rr_node = NULL; - int* prefer_side_swap; - /* pin0_to_rr_node is NOT one node, may have a few!!! */ - int num_pin0_to_rr_nodes = 0; - t_rr_node** pin0_to_rr_node = NULL; - /* pin1_to_rr_node is NOT one node, may have a few!!! */ - int num_pin1_to_rr_nodes = 0; - t_rr_node** pin1_to_rr_node = NULL; - - /* Check */ - assert(NULL != target_blk); - assert(NULL != target_blk->type); - assert((!(0 > pin0_index))&&(pin0_index < target_blk->type->num_pins)); - assert((!(0 > pin1_index))&&(pin1_index < target_blk->type->num_pins)); - assert(pin0_index != pin1_index); - - /* If two pins are OPEN Net, return */ - if ((OPEN == target_blk->nets[pin0_index]) - &&(OPEN == target_blk->nets[pin1_index])) { - /* There is no need to swap two OPEN pins*/ - return; - } - - /* Only support INPUT pins */ - pin0_class_index = target_blk->type->pin_class[pin0_index]; - pin1_class_index = target_blk->type->pin_class[pin1_index]; - assert(RECEIVER == target_blk->type->class_inf[pin0_class_index].type); - assert(RECEIVER == target_blk->type->class_inf[pin1_class_index].type); - /* Two pins should be in the same class */ - assert(pin0_class_index == pin1_class_index); - - /* Update pb local routing graph */ - /* load local_rr_graph */ - assert(NULL != target_blk->pb); - local_rr_graph = target_blk->pb->rr_graph; - /* find corresponding rr_node and pb_graph_pin of pin0 & pin1 */ - pin0_rr_node = &(local_rr_graph[pin0_index]); - pin1_rr_node = &(local_rr_graph[pin1_index]); - /* Make sure we find the correct rr_node and pb_graph_pin... */ - assert(pin0_index == pin0_rr_node->pb_graph_pin->pin_count_in_cluster); - assert(pin1_index == pin1_rr_node->pb_graph_pin->pin_count_in_cluster); - assert(pin0_class_index == pin0_rr_node->pb_graph_pin->pin_class); - assert(pin1_class_index == pin1_rr_node->pb_graph_pin->pin_class); - assert(0 == pin0_rr_node->pb_graph_pin->num_input_edges); - assert(0 == pin1_rr_node->pb_graph_pin->num_input_edges); - - /* Find to_rr_nodes for PIN0 */ - find_src_pb_pin_to_rr_nodes(target_blk->pb, pin0_index, &num_pin0_to_rr_nodes, &pin0_to_rr_node); - /* Find to_rr_nodes for PIN1 */ - find_src_pb_pin_to_rr_nodes(target_blk->pb, pin1_index, &num_pin1_to_rr_nodes, &pin1_to_rr_node); - - /* To SWAP: modify prev_node and prev_edge of pin0_to_rr_nodes, switch to pin1_rr_node */ - for (inode = 0; inode < num_pin0_to_rr_nodes; inode++) { - connect_pb_des_pin_to_src_pin(target_blk->pb, pin1_index, pin0_to_rr_node[inode]->pb_graph_pin->pin_count_in_cluster); - } - - /* To SWAP: modify prev_node and prev_edge of pin1_to_rr_node, switch to pin0_rr_node */ - for (inode = 0; inode < num_pin1_to_rr_nodes; inode++) { - connect_pb_des_pin_to_src_pin(target_blk->pb, pin0_index, pin1_to_rr_node[inode]->pb_graph_pin->pin_count_in_cluster); - } - - /* Update nets node_block_pin, should be done before updating blk nets, nets_sink_index !!! */ - /* Update blk nets, nets_sink_index, prefer_sides */ - net_swap = target_blk->nets[pin0_index]; - target_blk->nets[pin0_index] = target_blk->nets[pin1_index]; - target_blk->nets[pin1_index] = net_swap; - - net_swap = target_blk->nets_sink_index[pin0_index]; - target_blk->nets_sink_index[pin0_index] = target_blk->nets_sink_index[pin1_index]; - target_blk->nets_sink_index[pin1_index] = net_swap; - - prefer_side_swap = target_blk->pin_prefer_side[pin0_index]; - target_blk->pin_prefer_side[pin0_index] = target_blk->pin_prefer_side[pin1_index]; - target_blk->pin_prefer_side[pin1_index] = prefer_side_swap; - - /* Configure pin0_index net info */ - net_index = target_blk->nets[pin0_index]; - net_sink_index = target_blk->nets_sink_index[pin0_index]; - /* For OPEN NET */ - if (OPEN != net_index) { - nets[net_index].node_block_pin[net_sink_index] = pin0_index; - } - /* Configure pin1_index net info */ - net_index = target_blk->nets[pin1_index]; - net_sink_index = target_blk->nets_sink_index[pin1_index]; - /* For OPEN NET */ - if (OPEN != net_index) { - nets[net_index].node_block_pin[net_sink_index] = pin1_index; - } - - /* Swap local_rr_graph node net_num */ - /* Net_num in local_rr_graph follows the index of vpack_net !!! */ - net_swap = pin0_rr_node->net_num; - pin0_rr_node->net_num = pin1_rr_node->net_num; - pin1_rr_node->net_num = net_swap; - //pin0_rr_node->net_num = clb_to_vpack_net_mapping[target_blk->nets[pin0_index]]; /* pin0 */ - //pin1_rr_node->net_num = clb_to_vpack_net_mapping[target_blk->nets[pin1_index]]; /* pin1 */ - /* Update all successor rr_nodes net info */ - /* Update net info of pin1_to_rr_node, now it is the rr_node pin0_connected to */ - if (0 != num_pin1_to_rr_nodes) { /* pin1_to_rr_node now connected to pin0_rr_node */ - rec_update_net_info_local_rr_node_tree(target_blk->pb, pin0_rr_node->pb_graph_pin->pin_count_in_cluster); - } - /* Update net info of pin0_to_rr_node, now it is the rr_node pin1_connected to */ - if (0 != num_pin0_to_rr_nodes) { /* pin0_to_rr_node now connected to pin1_rr_node */ - rec_update_net_info_local_rr_node_tree(target_blk->pb, pin1_rr_node->pb_graph_pin->pin_count_in_cluster); - } - - return; -} - -void mark_blk_pins_nets_sink_index(int n_nets, t_net* nets, - int n_blks, t_block* blk) { - int inet, isink; - int iblk, ipin; - - /* Malloc and Initialize all block nets_sink_index */ - for (iblk = 0; iblk < n_blks; iblk++) { - assert(NULL != blk[iblk].type); - blk[iblk].nets_sink_index = (int*)my_malloc(sizeof(int)*blk[iblk].type->num_pins); - for (ipin = 0; ipin < blk[iblk].type->num_pins; ipin++) { - blk[iblk].nets_sink_index[ipin] = -1; - } - } - /* Set sink index for each block pin*/ - for (inet = 0; inet < n_nets; inet++) { - for (isink = 0; isink < (nets[inet].num_sinks + 1); isink++) { - iblk = nets[inet].node_block[isink]; - ipin = nets[inet].node_block_pin[isink]; - assert(inet == blk[iblk].nets[ipin]); - blk[iblk].nets_sink_index[ipin] = isink; - } - } - - return; -} - -void rec_update_net_info_local_rr_node_tree(t_pb* src_pb, - int src_node_index) { - int ipb, jpb, iedge, to_node, mode_index; - t_rr_node* local_rr_graph = NULL; - t_pb_graph_pin* des_pb_graph_pin = NULL; - t_pb_type* src_pb_type = NULL; - - /* Load local rr_graph */ - assert(NULL != src_pb); - local_rr_graph = src_pb->rr_graph; - assert(NULL != local_rr_graph); - mode_index = src_pb->mode; - - /* Find the destination node */ - for (iedge = 0; iedge < local_rr_graph[src_node_index].num_edges; iedge++) { - to_node = local_rr_graph[src_node_index].edges[iedge]; - if ((src_node_index == local_rr_graph[to_node].prev_node)&&(iedge == local_rr_graph[to_node].prev_edge) - /* Make sure in the same mode */ - &&(mode_index == local_rr_graph[to_node].pb_graph_pin->parent_node->pb_type->parent_mode->index)) { - des_pb_graph_pin = local_rr_graph[to_node].pb_graph_pin; - local_rr_graph[to_node].net_num = local_rr_graph[src_node_index].net_num; - /* Update recursively */ - src_pb_type = src_pb->pb_graph_node->pb_type; - /* if reach leaf, stop */ - if (NULL != src_pb_type->blif_model) { - continue; - } - /* recursive for the child_pbs*/ - for (ipb = 0; ipb < src_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < src_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != src_pb->child_pbs[ipb])&&(NULL != src_pb->child_pbs[ipb][jpb].name)) { - rec_update_net_info_local_rr_node_tree(&(src_pb->child_pbs[ipb][jpb]), des_pb_graph_pin->pin_count_in_cluster); - } - } - } - } - } - - return; -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/clb_pin_remap_util.h b/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/clb_pin_remap_util.h deleted file mode 100644 index 200b73ebb..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/clb_pin_remap_util.h +++ /dev/null @@ -1,67 +0,0 @@ - -void my_free(void* ptr); - -int pin_side_count(int pin_side[]); - -void find_blk_net_pin_sides(t_block target_blk, - int pin_height, - int pin_index, - int** pin_side); - -int find_blk_net_pin_side(t_block target_blk, - int pin_height, - int pin_index); - -void find_blk_net_type_pins(int n_blks, t_block* blk, - int net_index, - int blk_index, - int* num_pins, - enum e_side** pin_side, - int** pin_index); - -int check_src_blk_pin(int n_blks, t_block* blk, - int net_index, - int src_blk_index, - //int src_blk_port_index, - int src_blk_pin_index); - -int check_des_blk_pin(int n_blks, t_block* blk, - int net_index, - int des_blk_index, - //int des_blk_port_index, - int des_blk_pin_index); - -void esti_pin_chan_coordinate(int* pin_x, int* pin_y, - t_block blk, int pin_side, int pin_index); - - -int count_blk_one_class_num_conflict(t_block* targert_blk, int class_index, - int* is_pin_conflict); - -int* sort_one_class_conflict_pins_by_low_slack(t_block* target_blk, int class_index, - int* is_pin_conflict, int* num_conflict, - t_slack* slack); - -int is_swap2pins_match_prefer_side(int pin0_cur_side, int* pin0_prefer_side, - int pin1_cur_side, int* pin1_prefer_side); - -int is_type_pin_in_class(t_type_ptr type, - int class_index, int pin_index); - -void find_src_pb_pin_to_rr_nodes(t_pb* src_pb, - int src_rr_node_index, - int* num_pin_to_rr_nodes, - t_rr_node*** to_node); - -void connect_pb_des_pin_to_src_pin(t_pb* src_pb, - int src_rr_node_index, - int des_rr_node_index); - -void swap_blk_same_class_2pins(t_block* target_blk, int n_nets, t_net* nets, - int pin0_index, int pin1_index); - -void mark_blk_pins_nets_sink_index(int n_nets, t_net* nets, - int n_blks, t_block* blk); - -void rec_update_net_info_local_rr_node_tree(t_pb* src_pb, - int src_node_index); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/place_clb_pin_remap.c b/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/place_clb_pin_remap.c deleted file mode 100644 index c1d5ccada..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/place_clb_pin_remap.c +++ /dev/null @@ -1,763 +0,0 @@ -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "net_delay.h" -#include "path_delay.h" - -/* CLB_PIN_REMAP headers */ -#include "clb_pin_remap_util.h" -#include "post_place_timing.h" -#include "place_clb_pin_remap.h" -/* END */ - -/* main function */ -/* Try to remap CLB IPINs that are logic equivalent to optimize their routing delay. - * We should not remap any direct interconnect(carry_chain)! - */ -void try_clb_pin_remap_after_placement(t_det_routing_arch det_routing_arch, - t_segment_inf* segment_inf, - t_timing_inf timing_inf, - int num_directs, - t_direct_inf* directs) { - float** net_delay = NULL; - float** expected_net_delay = NULL; - t_slack* slacks = NULL; - t_chunk net_delay_ch = {NULL, 0, NULL}; - t_chunk expected_net_delay_ch = {NULL, 0, NULL}; - int num_pin_reqr_remap = 0; - int num_unrouted_blk_pins = 0; - int num_pin_remapped = 0; - float critical_path_delay = 0.; - - /* Do much more accurate timing-analysis */ - /* Alloc */ - slacks = alloc_and_load_timing_graph(timing_inf); - net_delay = alloc_net_delay(&net_delay_ch, clb_net, num_nets); - /* estimate and load net delays according to the PIN locations*/ - load_post_place_net_delay(net_delay, num_blocks, block, num_nets, clb_net, - det_routing_arch, segment_inf, - timing_inf, num_directs, directs); - /* Timing analysis*/ - load_timing_graph_net_delays(net_delay); - do_timing_analysis(slacks, FALSE, FALSE, TRUE); - /* Print critical path delay. */ - critical_path_delay = get_critical_path_delay(); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Post-Placement estimated critical path delay: %g ns\n", critical_path_delay); - /* Pre-Remap optimizatioin timing analysis finish*/ - - /* Now we do the remap */ - mark_blk_pins_nets_sink_index(num_nets, clb_net, num_blocks, block); - /* Generate suitable pin location list for each mapped CLB IPIN*/ - num_pin_reqr_remap = generate_nets_sinks_prefer_sides(num_nets, clb_net, num_blocks, block); - vpr_printf(TIO_MESSAGE_INFO, "Detect %d CLB IPINs that need to be remapped.\n", num_pin_reqr_remap); - num_unrouted_blk_pins = set_unroute_blk_pins_prefer_sides(num_blocks, block); - vpr_printf(TIO_MESSAGE_INFO, "Detect %d CLB IPINs are open.\n", num_unrouted_blk_pins); - /* Load expected net_delay */ - expected_net_delay = alloc_net_delay(&expected_net_delay_ch, clb_net, num_nets); - /* Estimate and load expected net delay when all CLB IPINs are in prefer sides */ - load_expected_remapped_net_delay(expected_net_delay, num_blocks, block, num_nets, clb_net, - det_routing_arch, segment_inf, - timing_inf, num_directs, directs); - /* Try to satify all the pins preferred side! */ - num_pin_remapped = sat_blks_pins_prefer_side(num_nets, clb_net, num_blocks, block, - net_delay, expected_net_delay, slacks); - vpr_printf(TIO_MESSAGE_INFO, "Remap %d CLB IPINs.\n", num_pin_remapped); - - /* Post-Remap optimization timing analysis */ - /* estimate and load net delays according to the PIN locations*/ - load_post_place_net_delay(net_delay, num_blocks, block, num_nets, clb_net, - det_routing_arch, segment_inf, - timing_inf, num_directs, directs); - /* Timing analysis*/ - load_timing_graph_net_delays(net_delay); - /* Timing analysis*/ - load_timing_graph_net_delays(net_delay); - do_timing_analysis(slacks, FALSE, FALSE, TRUE); - /* Print critical path delay. */ - critical_path_delay = get_critical_path_delay(); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "After CLB_PIN_REMAP estimated critical path delay: %g ns\n", critical_path_delay); - - /*TODO: free slack, net_delay and expected_net_delay?*/ - free_net_delay(net_delay, &net_delay_ch); - free_net_delay(expected_net_delay, &expected_net_delay_ch); - free_timing_graph(slacks); - - return; -} - -/* For each net sink, we assign its prefer sides */ -int generate_nets_sinks_prefer_sides(int n_nets, t_net* nets, - int n_blks, t_block* blk) { - int inet, isink, iblk; - int src_blk_index; - int src_num_pins; - enum e_side* src_pin_side = NULL; - int* src_pin_index = NULL; - int src_pin_class; - int des_blk_index; - int des_num_pins; - enum e_side* des_pin_side = NULL; - int* des_pin_index = NULL; - int des_pin_class; - - int num_pin_reqr_remap = 0; - int temp = 0; - - for (iblk = 0; iblk < n_blks; iblk++) { - /* Malloc pin_prefer_side for each block */ - assert(NULL != blk[iblk].type); - blk[iblk].pin_prefer_side = (int**)my_malloc(sizeof(int*)*(blk[iblk].type->num_pins)); - } - - for (inet = 0; inet < n_nets; inet++) { - /* Alloc prefer_side */ - nets[inet].prefer_side = (int**)my_malloc(sizeof(int*)*(nets[inet].num_sinks + 1)); - for (isink = 0; isink < (nets[inet].num_sinks + 1); isink++) { - /* Initialize */ - nets[inet].prefer_side[isink] = (int*)my_calloc(4, sizeof(int)); /* 4 sides: TOP, LEFT, BOTTOM, RIGHT */ - } - /* Find source block location, side */ - src_blk_index = nets[inet].node_block[0]; - find_blk_net_type_pins(n_blks, blk, inet, src_blk_index, - &src_num_pins, &src_pin_side, &src_pin_index); - /* Should be only 1 pins mapped! */ - assert(1 == src_num_pins); - nets[inet].prefer_side[0][src_pin_side[0]] = 1; - src_pin_class = blk[src_blk_index].type->pin_class[src_pin_index[0]]; - assert(DRIVER == blk[src_blk_index].type->class_inf[src_pin_class].type); - /* Assign block pin_prefer_side */ - blk[src_blk_index].pin_prefer_side[nets[inet].node_block_pin[0]] = nets[inet].prefer_side[0]; - /* For each sink, find block location, side */ - for (isink = 1; isink < (nets[inet].num_sinks + 1); isink++) { - des_blk_index = nets[inet].node_block[isink]; - /* Find destination block location, side */ - find_blk_net_type_pins(n_blks, blk, inet, des_blk_index, - &des_num_pins, &des_pin_side, &des_pin_index); - assert(1 == des_num_pins); - des_pin_class = blk[des_blk_index].type->pin_class[des_pin_index[0]]; - assert(RECEIVER == blk[des_blk_index].type->class_inf[des_pin_class].type); - /* Decide prefered sides of one sink pin */ - set_blk_net_one_sink_prefer_side(nets[inet].prefer_side[isink], src_pin_side[0], - /* Already allocated, in subroutine, array is writable*/ - blk[src_blk_index], - blk[des_blk_index]); - temp = pin_side_count(nets[inet].prefer_side[isink]); - assert((!(0 > temp))&&(temp < 4)); - /* Assign block pin_prefer_side */ - blk[des_blk_index].pin_prefer_side[nets[inet].node_block_pin[isink]] = nets[inet].prefer_side[isink]; - /* Statistics the pins should be remapped */ - if (0 == nets[inet].prefer_side[isink][des_pin_side[0]]) { - num_pin_reqr_remap++; - } - } - } - - /* Free */ - my_free(src_pin_index); - my_free(src_pin_side); - my_free(des_pin_index); - my_free(des_pin_side); - - return num_pin_reqr_remap; -} - -int set_unroute_blk_pins_prefer_sides(int n_blk, t_block* blk) { - int iblk, ipin, side; - int num_unroute_blk_pins = 0; - - /* For OPEN block pins, we should complete the prefer_side */ - for (iblk = 0; iblk < n_blk; iblk++) { - assert(NULL != blk[iblk].type); - /* By pass I/O type */ - if (IO_TYPE == blk[iblk].type) { - continue; - } - /* Special for global pins or non-routed pins, prefer_side should be all-ones */ - for (ipin = 0; ipin < blk[iblk].type->num_pins; ipin++) { - if (OPEN == blk[iblk].nets[ipin]) { - /* malloc a pin_prefer_side */ - blk[iblk].pin_prefer_side[ipin] = (int*)my_malloc(sizeof(int)*4); - for (side = 0; side < 4; side++) { - blk[iblk].pin_prefer_side[ipin][side] = 1; - } - num_unroute_blk_pins++; - } - } - } - - return num_unroute_blk_pins; -} - -void set_blk_net_one_sink_prefer_side(int* prefer_side, /* [0..3] array, should be allocated before */ - enum e_side src_pin_side, - t_block src_blk, - t_block des_blk) { - switch (src_pin_side) { - case TOP: - set_src_top_side_net_one_sink_prefer_side(prefer_side, src_blk, des_blk); - break; - case RIGHT: - set_src_right_side_net_one_sink_prefer_side(prefer_side, src_blk, des_blk); - break; - case BOTTOM: - set_src_bottom_side_net_one_sink_prefer_side(prefer_side, src_blk, des_blk); - break; - case LEFT: - set_src_left_side_net_one_sink_prefer_side(prefer_side, src_blk, des_blk); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid src_pin_side!\n", __FILE__, __LINE__); - exit(1); - } - - return; -} - -/* Find prefered side for one sink pin when the source pin is on TOP side - * Refer to this graph, src block locates the center - * -------- -------- -------- - * | | | | | | - * | Des0 |<-- | Des1 | -->| Des2 | - * | | | | | | | | - * -------- | -------- | -------- - * /|\ | /|\ | /|\ - * |------------|-------------| - * \|/ | | | \|/ - * -------- | -------- | -------- - * | | | | | | | | - * | Des3 |<-| | SRC | |->| Des4 | - * | | | | | | | | - * -------- | -------- | -------- - * | | - * -------------|-------------- - * \|/ | \|/ | \|/ - * -------- | -------- | -------- - * | | | | | | | | - * | Des5 |<--->| Des6 |<--->| Des7 | - * | | | | | | - * -------- -------- -------- - */ -void set_src_top_side_net_one_sink_prefer_side(int* prefer_side, - t_block src_blk, t_block des_blk) { - /* TODO: for none IO_TYPE, there should be no self connections*/ - assert(!((des_blk.x == src_blk.x)&&(des_blk.y == src_blk.y)&&(des_blk.z == src_blk.z))); - /* Identify which position the des_blk, based on src_blk */ - if ((des_blk.x < src_blk.x)&&(des_blk.y > src_blk.y)) { - /* Des 0 */ - prefer_side[RIGHT] = 1; - prefer_side[BOTTOM] = 1; - } else if ((des_blk.x == src_blk.x)&&(des_blk.y > src_blk.y)) { - /* Des 1 */ - prefer_side[BOTTOM] = 1; - } else if ((des_blk.x > src_blk.x)&&(des_blk.y > src_blk.y)) { - /* Des 2 */ - prefer_side[LEFT] = 1; - prefer_side[BOTTOM] = 1; - } else if ((des_blk.x < src_blk.x)&&(des_blk.y == src_blk.y)) { - /* Des 3 */ - prefer_side[TOP] = 1; - prefer_side[RIGHT] = 1; - } else if ((des_blk.x > src_blk.x)&&(des_blk.y == src_blk.y)) { - /* Des 4 */ - prefer_side[TOP] = 1; - prefer_side[LEFT] = 1; - } else if ((des_blk.x < src_blk.x)&&(des_blk.y < src_blk.y)) { - /* Des 5 */ - prefer_side[TOP] = 1; - prefer_side[RIGHT] = 1; - } else if ((des_blk.x == src_blk.x)&&(des_blk.y < src_blk.y)) { - /* Des 6 */ - prefer_side[TOP] = 1; - //prefer_side[RIGHT] = 1; - //prefer_side[LEFT] = 1; - } else if ((des_blk.x > src_blk.x)&&(des_blk.y < src_blk.y)) { - /* Des 7 */ - prefer_side[TOP] = 1; - prefer_side[LEFT] = 1; - } - - return; -} - -/* Find prefered side for one sink pin when the source pin is on RIGHT side - * Refer to this graph, src block locates the center - * -------- -------- -------- - * | | | | | | - * | Des0 |<-- | Des1 |<--->| Des2 | - * | | | | | | | | - * -------- | -------- | -------- - * /|\ | /|\ | /|\ - * |--------------------------| - * \|/ | | - * -------- | -------- | -------- - * | | | | | | | | - * | Des3 |<-| | SRC |--|->| Des4 | - * | | | | | | | | - * -------- | -------- | -------- - * /|\ | | - * |--------------------------| - * \|/ | \|/ | \|/ - * -------- | -------- | -------- - * | | | | | | | | - * | Des5 |<-- | Des6 |<--->| Des7 | - * | | | | | | - * -------- -------- -------- - */ -void set_src_right_side_net_one_sink_prefer_side(int* prefer_side, - t_block src_blk, t_block des_blk) { - /* TODO: for none IO_TYPE, there should be no self connections*/ - assert(!((des_blk.x == src_blk.x)&&(des_blk.y == src_blk.y)&&(des_blk.z == src_blk.z))); - /* Identify which position the des_blk, based on src_blk */ - if ((des_blk.x < src_blk.x)&&(des_blk.y > src_blk.y)) { - /* Des 0 */ - prefer_side[RIGHT] = 1; - prefer_side[BOTTOM] = 1; - } else if ((des_blk.x == src_blk.x)&&(des_blk.y > src_blk.y)) { - /* Des 1 */ - prefer_side[RIGHT] = 1; - prefer_side[BOTTOM] = 1; - } else if ((des_blk.x > src_blk.x)&&(des_blk.y > src_blk.y)) { - /* Des 2 */ - prefer_side[LEFT] = 1; - prefer_side[BOTTOM] = 1; - } else if ((des_blk.x < src_blk.x)&&(des_blk.y == src_blk.y)) { - /* Des 3 */ - //prefer_side[TOP] = 1; - prefer_side[RIGHT] = 1; - //prefer_side[BOTTOM] = 1; - } else if ((des_blk.x > src_blk.x)&&(des_blk.y == src_blk.y)) { - /* Des 4 */ - prefer_side[LEFT] = 1; - } else if ((des_blk.x < src_blk.x)&&(des_blk.y < src_blk.y)) { - /* Des 5 */ - prefer_side[TOP] = 1; - prefer_side[RIGHT] = 1; - } else if ((des_blk.x == src_blk.x)&&(des_blk.y < src_blk.y)) { - /* Des 6 */ - prefer_side[TOP] = 1; - prefer_side[RIGHT] = 1; - } else if ((des_blk.x > src_blk.x)&&(des_blk.y < src_blk.y)) { - /* Des 7 */ - prefer_side[TOP] = 1; - prefer_side[LEFT] = 1; - } - - return; -} - -/* Find prefered side for one sink pin when the source pin is on BOTTOM side - * Refer to this graph, src block locates the center - * -------- -------- -------- - * | | | | | | - * | Des0 |<-- | Des1 |<--->| Des2 | - * | | | | | | | | - * -------- | -------- | -------- - * /|\ | /|\ | /|\ - * |--------------------------| - * | | - * -------- | -------- | -------- - * | | | | | | | | - * | Des3 |<-| | SRC | |->| Des4 | - * | | | | | | | | - * -------- | -------- | -------- - * /|\ | | | /|\ - * |------------|-------------| - * \|/ | \|/ | \|/ - * -------- | -------- | -------- - * | | | | | | | | - * | Des5 |<-- | Des6 | -->| Des7 | - * | | | | | | - * -------- -------- -------- - */ -void set_src_bottom_side_net_one_sink_prefer_side(int* prefer_side, - t_block src_blk, t_block des_blk) { - /* TODO: for none IO_TYPE, there should be no self connections*/ - assert(!((des_blk.x == src_blk.x)&&(des_blk.y == src_blk.y)&&(des_blk.z == src_blk.z))); - /* Identify which position the des_blk, based on src_blk */ - if ((des_blk.x < src_blk.x)&&(des_blk.y > src_blk.y)) { - /* Des 0 */ - prefer_side[RIGHT] = 1; - prefer_side[BOTTOM] = 1; - } else if ((des_blk.x == src_blk.x)&&(des_blk.y > src_blk.y)) { - /* Des 1 */ - //prefer_side[RIGHT] = 1; - prefer_side[BOTTOM] = 1; - //prefer_side[LEFT] = 1; - } else if ((des_blk.x > src_blk.x)&&(des_blk.y > src_blk.y)) { - /* Des 2 */ - prefer_side[LEFT] = 1; - prefer_side[BOTTOM] = 1; - } else if ((des_blk.x < src_blk.x)&&(des_blk.y == src_blk.y)) { - /* Des 3 */ - prefer_side[RIGHT] = 1; - prefer_side[BOTTOM] = 1; - } else if ((des_blk.x > src_blk.x)&&(des_blk.y == src_blk.y)) { - /* Des 4 */ - prefer_side[LEFT] = 1; - prefer_side[BOTTOM] = 1; - } else if ((des_blk.x < src_blk.x)&&(des_blk.y < src_blk.y)) { - /* Des 5 */ - prefer_side[TOP] = 1; - prefer_side[RIGHT] = 1; - } else if ((des_blk.x == src_blk.x)&&(des_blk.y < src_blk.y)) { - /* Des 6 */ - prefer_side[TOP] = 1; - } else if ((des_blk.x > src_blk.x)&&(des_blk.y < src_blk.y)) { - /* Des 7 */ - prefer_side[TOP] = 1; - prefer_side[LEFT] = 1; - } - - return; -} - -/* Find prefered side for one sink pin when the source pin is on LEFT side - * Refer to this graph, src block locates the center - * -------- -------- -------- - * | | | | | | - * | Des0 |<--->| Des1 | -->| Des2 | - * | | | | | | | | - * -------- | -------- | -------- - * /|\ | /|\ | /|\ - * |--------------------------| - * | | \|/ - * -------- | -------- | -------- - * | | | | | | | | - * | Des3 |<-|--| SRC | |->| Des4 | - * | | | | | | | | - * -------- | -------- | -------- - * | | /|\ - * |--------------------------| - * \|/ | \|/ | \|/ - * -------- | -------- | -------- - * | | | | | | | | - * | Des5 |<--->| Des6 | -->| Des7 | - * | | | | | | - * -------- -------- -------- - */ -void set_src_left_side_net_one_sink_prefer_side(int* prefer_side, - t_block src_blk, t_block des_blk) { - /* TODO: for none IO_TYPE, there should be no self connections*/ - assert(!((des_blk.x == src_blk.x)&&(des_blk.y == src_blk.y)&&(des_blk.z == src_blk.z))); - /* Identify which position the des_blk, based on src_blk */ - if ((des_blk.x < src_blk.x)&&(des_blk.y > src_blk.y)) { - /* Des 0 */ - prefer_side[RIGHT] = 1; - prefer_side[BOTTOM] = 1; - } else if ((des_blk.x == src_blk.x)&&(des_blk.y > src_blk.y)) { - /* Des 1 */ - prefer_side[BOTTOM] = 1; - prefer_side[LEFT] = 1; - } else if ((des_blk.x > src_blk.x)&&(des_blk.y > src_blk.y)) { - /* Des 2 */ - prefer_side[LEFT] = 1; - prefer_side[BOTTOM] = 1; - } else if ((des_blk.x < src_blk.x)&&(des_blk.y == src_blk.y)) { - /* Des 3 */ - prefer_side[RIGHT] = 1; - } else if ((des_blk.x > src_blk.x)&&(des_blk.y == src_blk.y)) { - /* Des 4 */ - //prefer_side[TOP] = 1; - prefer_side[LEFT] = 1; - //prefer_side[BOTTOM] = 1; - } else if ((des_blk.x < src_blk.x)&&(des_blk.y < src_blk.y)) { - /* Des 5 */ - prefer_side[TOP] = 1; - prefer_side[RIGHT] = 1; - } else if ((des_blk.x == src_blk.x)&&(des_blk.y < src_blk.y)) { - /* Des 6 */ - prefer_side[TOP] = 1; - prefer_side[LEFT] = 1; - } else if ((des_blk.x > src_blk.x)&&(des_blk.y < src_blk.y)) { - /* Des 7 */ - prefer_side[TOP] = 1; - prefer_side[LEFT] = 1; - } - - return; -} - -/* Try to satify the prefer side of all the pins of all the blocks */ -int sat_blks_pins_prefer_side(int n_nets, t_net* nets, - int n_blks, t_block* blk, - float** net_delay, float** expected_net_delay, t_slack* slack) { - int num_pin_remapped = 0; - int iblk; - - /* For each block, try to satify the prefer side of each pin */ - for (iblk = 0; iblk < n_blks; iblk++) { - /* Bypass IO_TYPE */ - if (IO_TYPE == blk[iblk].type) { - continue; - } - num_pin_remapped += sat_one_blk_pins_prefer_side(n_nets, nets, &(blk[iblk]), - net_delay, expected_net_delay, slack); - } - - return num_pin_remapped; -} - -/* For one block, try to satify the prefer side of each pin */ -int sat_one_blk_pins_prefer_side(int n_nets, t_net* nets, - t_block* target_blk, - float** net_delay, float** expected_net_delay, t_slack* slack) { - int num_pin_remapped = 0; - int ipin, num_pins; - int iclass; - int* is_pin_conflict = NULL; - int* cur_pin_side = NULL; - - assert(NULL != target_blk); - assert(NULL != target_blk->type); - num_pins = target_blk->type->num_pins; - - /* Bypass IO_TYPE */ - if (IO_TYPE == target_blk->type) { - return 0; - } - - /* Malloc */ - cur_pin_side = (int*)my_malloc(sizeof(int*)*num_pins); - /* Find current pin sides*/ - for (ipin = 0; ipin < num_pins; ipin++) { - /* Make sure each pin appear at only one side!*/ - cur_pin_side[ipin] = find_blk_net_pin_side((*target_blk), target_blk->z, ipin); - } - /* Check the number of conflicts: - * pin_side not in prefer side - */ - /* Malloc and Initialize */ - is_pin_conflict = (int*)my_calloc(num_pins, sizeof(int)); - for (ipin = 0; ipin < num_pins; ipin++) { - if (0 == target_blk->pin_prefer_side[ipin][cur_pin_side[ipin]]) { - is_pin_conflict[ipin] = 1; - } - } - for (iclass = 0; iclass < target_blk->type->num_class; iclass++) { - /* We care RECEIVER class only */ - if (RECEIVER != target_blk->type->class_inf[iclass].type) { - continue; - } - num_pin_remapped += try_sat_one_blk_pin_class_prefer_side(target_blk, n_nets, nets, - iclass, is_pin_conflict, cur_pin_side, - net_delay, expected_net_delay, slack); - } - - /* Free */ - my_free(cur_pin_side); - my_free(is_pin_conflict); - - return num_pin_remapped; -} - -int try_sat_one_blk_pin_class_prefer_side(t_block* target_blk, - int n_nets, t_net* nets, - int class_index, - int* is_pin_conflict, int* cur_pin_side, - float** net_delay, float** expected_net_delay, t_slack* slack) { - int num_pin_remapped = 0; - int ipin, class_num_pins, blk_pin_index; - int net_index, net_sink_index; - int num_conflict = 0; - int sorted_list_len = 0; - int* sorted_conflict_pin_list = NULL; - float* esti_delay_gain = NULL; - - assert(NULL != target_blk); - assert(NULL != target_blk->type); - - /* We care RECEIVER class only */ - if (RECEIVER != target_blk->type->class_inf[class_index].type) { - return num_pin_remapped; - } - - class_num_pins = target_blk->type->class_inf[class_index].num_pins; - /* If there is only one pin in this class, there is no need to remap */ - assert(0 < class_num_pins); - if (2 > class_num_pins) { - return num_pin_remapped; - } - /* Count the number of conflict in this class */ - num_conflict = count_blk_one_class_num_conflict(target_blk, class_index, is_pin_conflict); - /* There is no conflict, directly return */ - if (0 == num_conflict) { - return num_pin_remapped; - } - - /* Now we try to solve all the conflicts */ - /* See the estimated delay gain */ - esti_delay_gain = (float*)my_malloc(sizeof(float)*class_num_pins); - for (ipin = 0; ipin < class_num_pins; ipin++) { - blk_pin_index = target_blk->type->class_inf[class_index].pinlist[ipin]; - /* unroute net, bypass not conflict pins */ - if (0 == is_pin_conflict[blk_pin_index]) { - esti_delay_gain[ipin] = -1.; - continue; - } - /* Estimate delay gain on conflicted pins */ - net_index = target_blk->nets[blk_pin_index]; - net_sink_index = target_blk->nets_sink_index[blk_pin_index]; - assert(OPEN != net_index); - assert(OPEN != net_sink_index); - esti_delay_gain[ipin] = expected_net_delay[net_index][net_sink_index]/net_delay[net_index][net_sink_index] - 1; - assert(!(esti_delay_gain[ipin] > 0)); /* Expected_net_delay should be smaller! */ - } - - /* Sort the conflict pins in the class by lowest slack */ - sorted_conflict_pin_list = sort_one_class_conflict_pins_by_low_slack(target_blk, class_index, - is_pin_conflict, &sorted_list_len, slack); - assert(sorted_list_len == num_conflict); - - /* Try to solve each conflict pin */ - num_pin_remapped = 0; - for (ipin = 0; ipin < num_conflict; ipin++) { - blk_pin_index = target_blk->type->class_inf[class_index].pinlist[sorted_conflict_pin_list[ipin]]; - if (1 == is_pin_conflict[blk_pin_index]) { - num_pin_remapped += try_remap_blk_class_one_conflict_pin(target_blk, class_index, blk_pin_index, - n_nets, nets, cur_pin_side, is_pin_conflict, - esti_delay_gain, slack); - } - } - - /* Free */ - my_free(sorted_conflict_pin_list); - my_free(esti_delay_gain); - - return num_pin_remapped; -} - -/* Successful remap, return 1. Fail, return 0. - * 1. Try to swap with a conflicted pin in the same class - * 2. Try to swap with an unrouted pin in the same class - * 3. Try to swap with a unconflicted pin in the same class - */ -int try_remap_blk_class_one_conflict_pin(t_block* target_blk, int class_index, int pin_index, - int n_nets, t_net* nets, - int* cur_pin_side, int* is_pin_conflict, - float* esti_delay_gain, t_slack* slack) { - int* prefer_sides = NULL; - int num_pins; - int ipin, blk_pin_index, side_swap; - - assert(NULL != target_blk); - assert(NULL != target_blk->type); - assert((!(0 > pin_index))&&(pin_index < target_blk->type->num_pins)); - assert((!(0 > class_index))&&(class_index < target_blk->type->num_class)); - /* ONLY support INPUT PINs */ - assert(RECEIVER == target_blk->type->class_inf[class_index].type); - - prefer_sides = target_blk->pin_prefer_side[pin_index]; - num_pins = target_blk->type->class_inf[class_index].num_pins; - - if (!(1 == is_type_pin_in_class(target_blk->type, class_index, pin_index))) { - printf("num_pin_in_class = %d\n", is_type_pin_in_class(target_blk->type, class_index, pin_index)); - assert(1 == is_type_pin_in_class(target_blk->type, class_index, pin_index)); - } - assert(1 == is_pin_conflict[pin_index]); - - /* Try to swap with conflicted pins */ - for (ipin = 0; ipin < num_pins; ipin++) { - blk_pin_index = target_blk->type->class_inf[class_index].pinlist[ipin]; - assert((!(0 >cur_pin_side[blk_pin_index]))&&(cur_pin_side[blk_pin_index] < 4)); - /* conflicted_pin match prefer_side */ - if ((pin_index != blk_pin_index)&&(1 == is_pin_conflict[blk_pin_index]) - &&(1 == is_swap2pins_match_prefer_side(cur_pin_side[pin_index], prefer_sides, - cur_pin_side[blk_pin_index], target_blk->pin_prefer_side[blk_pin_index]))) { - /* Swap 2 CLB IPIN */ - swap_blk_same_class_2pins(target_blk, n_nets, nets, pin_index, blk_pin_index); - /* Print DEBUG info */ - vpr_printf(TIO_MESSAGE_INFO, - "SwapCase1: PIN(block x=%d, y=%d, z=%d, index=%d, net[%s].sink[%d])\n", - target_blk->x, target_blk->y, target_blk->z, pin_index, - nets[target_blk->nets[pin_index]].name, target_blk->nets_sink_index[pin_index]); - vpr_printf(TIO_MESSAGE_INFO, - " with PIN(block x=%d, y=%d, z=%d, index=%d, net[%s].sink[%d]).\n", - target_blk->x, target_blk->y, target_blk->z, blk_pin_index, - nets[target_blk->nets[blk_pin_index]].name, target_blk->nets_sink_index[blk_pin_index]); - vpr_printf(TIO_MESSAGE_INFO, "ipin=%d\n", ipin); - /* Update is_conflict list */ - is_pin_conflict[blk_pin_index] = 0; - is_pin_conflict[pin_index] = 0; - /* Update cur_pin_side list */ - side_swap = cur_pin_side[blk_pin_index]; - cur_pin_side[blk_pin_index] = cur_pin_side[pin_index]; - cur_pin_side[pin_index] = side_swap; - /* Finish, we can return */ - return 2; - } - } - - /* Find all unrounted pins, try to swap */ - for (ipin = 0; ipin < num_pins; ipin++) { - blk_pin_index = target_blk->type->class_inf[class_index].pinlist[ipin]; - assert((!(0 >cur_pin_side[blk_pin_index]))&&(cur_pin_side[blk_pin_index] < 4)); - /* conflicted_pin match prefer_side */ - if ((pin_index != blk_pin_index)&&(0 == is_pin_conflict[blk_pin_index])&&(OPEN == target_blk->nets[blk_pin_index]) - &&(1 == is_swap2pins_match_prefer_side(cur_pin_side[pin_index], prefer_sides, - cur_pin_side[blk_pin_index], target_blk->pin_prefer_side[blk_pin_index]))) { - /* Swap 2 CLB IPIN */ - swap_blk_same_class_2pins(target_blk, n_nets, nets, pin_index, blk_pin_index); - /* Print DEBUG info */ - vpr_printf(TIO_MESSAGE_INFO, - "SwapCase2: PIN(block x=%d, y=%d, z=%d, index=%d, net[%s].sink[%d])\n", - target_blk->x, target_blk->y, target_blk->z, pin_index, - nets[target_blk->nets[pin_index]].name, target_blk->nets_sink_index[pin_index]); - vpr_printf(TIO_MESSAGE_INFO, - " with PIN(block x=%d, y=%d, z=%d, index=%d, net[%s].sink[%d]).\n", - target_blk->x, target_blk->y, target_blk->z, blk_pin_index, - nets[target_blk->nets[blk_pin_index]].name, target_blk->nets_sink_index[blk_pin_index]); - vpr_printf(TIO_MESSAGE_INFO, "ipin=%d\n", ipin); - /* Update is_conflict list */ - is_pin_conflict[blk_pin_index] = 0; - is_pin_conflict[pin_index] = 0; - /* Update cur_pin_side list */ - side_swap = cur_pin_side[blk_pin_index]; - cur_pin_side[blk_pin_index] = cur_pin_side[pin_index]; - cur_pin_side[pin_index] = side_swap; - /* Finish, we can return */ - return 1; - } - } - - /* Find unconflicted routed pins, try to swap */ - for (ipin = 0; ipin < num_pins; ipin++) { - blk_pin_index = target_blk->type->class_inf[class_index].pinlist[ipin]; - assert((!(0 >cur_pin_side[blk_pin_index]))&&(cur_pin_side[blk_pin_index] < 4)); - /* conflicted_pin match prefer_side */ - if ((pin_index != blk_pin_index)&&(0 == is_pin_conflict[blk_pin_index])&&(OPEN != target_blk->nets[blk_pin_index]) - /* TODO: if pin_index slack overwhelms blk_pin_index, shall we swap??? */ - &&(1 == 0) - &&(1 == is_swap2pins_match_prefer_side(cur_pin_side[pin_index], prefer_sides, - cur_pin_side[blk_pin_index], target_blk->pin_prefer_side[blk_pin_index]))) { - /* Swap 2 CLB IPIN */ - swap_blk_same_class_2pins(target_blk, n_nets, nets, pin_index, blk_pin_index); - /* Print DEBUG info */ - vpr_printf(TIO_MESSAGE_INFO, - "SwapCase3: PIN(block x=%d, y=%d, z=%d, index=%d, net[%s].sink[%d])\n", - target_blk->x, target_blk->y, target_blk->z, pin_index, - nets[target_blk->nets[pin_index]].name, target_blk->nets_sink_index[pin_index]); - vpr_printf(TIO_MESSAGE_INFO, - " with PIN(block x=%d, y=%d, z=%d, index=%d, net[%s].sink[%d]).\n", - target_blk->x, target_blk->y, target_blk->z, blk_pin_index, - nets[target_blk->nets[blk_pin_index]].name, target_blk->nets_sink_index[blk_pin_index]); - vpr_printf(TIO_MESSAGE_INFO, "ipin=%d\n", ipin); - /* Update is_conflict list */ - is_pin_conflict[blk_pin_index] = 0; - is_pin_conflict[pin_index] = 0; - /* Update cur_pin_side list */ - side_swap = cur_pin_side[blk_pin_index]; - cur_pin_side[blk_pin_index] = cur_pin_side[pin_index]; - cur_pin_side[pin_index] = side_swap; - /* Finish, we can return */ - return 2; - } - } - - return 0; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/place_clb_pin_remap.h b/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/place_clb_pin_remap.h deleted file mode 100644 index 9992f65da..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/place_clb_pin_remap.h +++ /dev/null @@ -1,47 +0,0 @@ - -void try_clb_pin_remap_after_placement(t_det_routing_arch det_routing_arch, - t_segment_inf* segment_inf, - t_timing_inf timing_inf, - int num_directs, - t_direct_inf* directs); - -int generate_nets_sinks_prefer_sides(int n_nets, t_net* nets, - int n_blks, t_block* blk); - -int set_unroute_blk_pins_prefer_sides(int n_blk, t_block* blk); - -void set_blk_net_one_sink_prefer_side(int* prefer_side, /* [0..3] array, should be allocated before */ - enum e_side src_pin_side, - t_block src_blk, - t_block des_blk); - -void set_src_top_side_net_one_sink_prefer_side(int* prefer_side, - t_block src_blk, t_block des_blk); - -void set_src_right_side_net_one_sink_prefer_side(int* prefer_side, - t_block src_blk, t_block des_blk); - -void set_src_bottom_side_net_one_sink_prefer_side(int* prefer_side, - t_block src_blk, t_block des_blk); - -void set_src_left_side_net_one_sink_prefer_side(int* prefer_side, - t_block src_blk, t_block des_blk); - -int sat_blks_pins_prefer_side(int n_nets, t_net* nets, - int n_blks, t_block* blk, - float** net_delay, float** expected_net_delay, t_slack* slack); - -int sat_one_blk_pins_prefer_side(int n_nets, t_net* nets, - t_block* target_blk, - float** net_delay, float** expected_net_delay, t_slack* slack); - -int try_sat_one_blk_pin_class_prefer_side(t_block* target_blk, - int n_nets, t_net* nets, - int class_index, - int* is_pin_conflict, int* cur_pin_side, - float** net_delay, float** expected_net_delay, t_slack* slack); - -int try_remap_blk_class_one_conflict_pin(t_block* target_blk, int class_index, int pin_index, - int n_nets, t_net* nets, - int* cur_pin_side, int* is_pin_conflict, - float* esti_delay_gain, t_slack* slack); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/post_place_timing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/post_place_timing.c deleted file mode 100644 index 486f902ea..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/post_place_timing.c +++ /dev/null @@ -1,359 +0,0 @@ -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "net_delay_types.h" -#include "net_delay_local_void.h" -#include "net_delay.h" -#include "path_delay.h" -/* CLB PIN REMAP */ -#include "clb_pin_remap_util.h" -#include "post_place_timing.h" - -/* Xifan TANG: Copied from place.c */ -/* Expected crossing counts for nets with different #'s of pins. From * - * ICCAD 94 pp. 690 - 695 (with linear interpolation applied by me). * - * Multiplied to bounding box of a net to better estimate wire length * - * for higher fanout nets. Each entry is the correction factor for the * - * fanout index-1 */ -static const float local_cross_count[50] = { /* [0..49] */1.0, 1.0, 1.0, 1.0828, 1.1536, 1.2206, 1.2823, 1.3385, 1.3991, 1.4493, 1.4974, - 1.5455, 1.5937, 1.6418, 1.6899, 1.7304, 1.7709, 1.8114, 1.8519, 1.8924, - 1.9288, 1.9652, 2.0015, 2.0379, 2.0743, 2.1061, 2.1379, 2.1698, 2.2016, - 2.2334, 2.2646, 2.2958, 2.3271, 2.3583, 2.3895, 2.4187, 2.4479, 2.4772, - 2.5064, 2.5356, 2.5610, 2.5864, 2.6117, 2.6371, 2.6625, 2.6887, 2.7148, - 2.7410, 2.7671, 2.7933 }; - -/* Load and estimate post-placement net delays according to the PIN locations */ -void load_post_place_net_delay(float** net_delay, - int n_blks, - t_block* blk, - int n_nets, - t_net* nets, - t_det_routing_arch det_routing_arch, - t_segment_inf* segment_inf, - t_timing_inf timing_inf, - int num_directs, - t_direct_inf* directs) { - int inet, isink; - int src_blk_index, /*src_blk_port_index,*/ src_blk_pin_index; - int des_blk_index, /*des_blk_port_index,*/ des_blk_pin_index; - float penalty = 0.; - - /* Search each clb net, find the driver (OPIN) and all the receivers (IPINs) */ - for (inet = 0; inet < n_nets; inet++) { - /* Global nets, we don't optimize */ - if (TRUE == nets[inet].is_global) { - load_one_constant_net_delay(net_delay, inet, nets, 0.); - } else { - penalty = get_crossing_penalty(nets[inet].num_sinks); - /* Spot driver (OPIN) location */ - src_blk_index = nets[inet].node_block[0]; - //src_blk_port_index = nets[inet].node_block_port[0]; - src_blk_pin_index = nets[inet].node_block_pin[0]; - /* Check the driver OPIN */ - check_src_blk_pin(n_blks, blk, inet, - src_blk_index, - //src_blk_port_index, - src_blk_pin_index); - /* Search all the sinks and estimate route delay */ - for (isink = 1; isink < (nets[inet].num_sinks + 1); isink++) { - des_blk_index = nets[inet].node_block[isink]; - //des_blk_port_index = nets[inet].node_block_port[isink]; - des_blk_pin_index = nets[inet].node_block_pin[isink]; - check_des_blk_pin(n_blks, blk, inet, - des_blk_index, - //des_blk_port_index, - des_blk_pin_index); - /* Estimate the net delay */ - net_delay[inet][isink] = penalty * - estimate_post_place_one_net_sink_delay(inet, n_blks, blk, src_blk_index, des_blk_index, - det_routing_arch, segment_inf, timing_inf, - num_directs, directs); - } - } - } - - return; -} - -float estimate_post_place_one_net_sink_delay(int net_index, - int n_blks, - t_block* blk, - int src_blk_index, - int des_blk_index, - t_det_routing_arch det_routing_arch, - t_segment_inf* segment_inf, - t_timing_inf timing_inf, - int num_directs, - t_direct_inf* directs) { - float esti_net_delay = -1.; - int num_src_pins = 0; - enum e_side* src_pin_side = NULL; - int* src_pin_index = NULL; - - int num_des_pins = 0; - enum e_side* des_pin_side; - int* des_pin_index = NULL; - - int isrc, ides; - float pin2pin_net_delay = 0.; - - /* ONLY APPLICABLE TO UNI_DIRECITONAL ROUTING ARCH. !!!*/ - if (UNI_DIRECTIONAL != det_routing_arch.directionality) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d])Estimate post-placement net delay is ONLY applicable to uni-directional routint arch!\n", __FILE__, __LINE__); - exit(1); - } - /* Find the driver OPINs location */ - find_blk_net_type_pins(n_blks, blk, net_index, src_blk_index, - &num_src_pins, &src_pin_side, &src_pin_index); - /* Find the receiver IPINs location */ - find_blk_net_type_pins(n_blks, blk, net_index, des_blk_index, - &num_des_pins, &des_pin_side, &des_pin_index); - /* Search all possible path */ - assert(0 < num_src_pins); - assert(0 < num_des_pins); - /* Should be only 1 destination pin */ - assert(1 == num_des_pins); - for (ides = 0; ides < num_des_pins; ides++) { - /* Should be only 1 source pin */ - assert(1 == num_src_pins); - /* Possible paths from sources */ - for (isrc = 0; isrc < num_src_pins; isrc++) { - pin2pin_net_delay = esti_pin2pin_one_net_delay(blk[src_blk_index], src_pin_side[isrc], src_pin_index[isrc], - blk[des_blk_index], des_pin_side[ides], des_pin_index[ides], - det_routing_arch, segment_inf, timing_inf, num_directs, directs); - /* Consider the worst case src->des pin delay*/ - if ((-1. == esti_net_delay)||(pin2pin_net_delay > esti_net_delay)) { - esti_net_delay = pin2pin_net_delay; - } - } - } - - return esti_net_delay; -} - -float esti_pin2pin_one_net_delay(t_block src_blk, - int src_pin_side, - int src_pin_index, - t_block des_blk, - int des_pin_side, - int des_pin_index, - t_det_routing_arch det_routing_arch, - t_segment_inf* segment_inf, - t_timing_inf timing_inf, - int num_directs, - t_direct_inf* directs) { - int src_pin_x, src_pin_y; - int des_pin_x, des_pin_y; - int delta_x, delta_y; - float horizen_delay, vertical_delay, path_delay; - - /* ONLY APPLICABLE TO UNI_DIRECITONAL ROUTING ARCH. !!!*/ - if (UNI_DIRECTIONAL != det_routing_arch.directionality) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d])Estimate post-placement net delay is ONLY applicable to uni-directional routint arch!\n", __FILE__, __LINE__); - exit(1); - } - - /* Estimate the channel location of src and des pins */ - esti_pin_chan_coordinate(&src_pin_x, &src_pin_y, - src_blk, src_pin_side, src_pin_index); - esti_pin_chan_coordinate(&des_pin_x, &des_pin_y, - des_blk, des_pin_side, des_pin_index); - - /* TODO: Special for direct connection, delayless switch is used !!!*/ - - /* Search a possible path from SRC PIN to DES PIN */ - switch (src_pin_side) { - case TOP: - case BOTTOM: - /* 1st step: go horizentally */ - delta_x = abs(src_pin_x - des_pin_x); - /* Pass through a number of SB MUX */ - horizen_delay = esti_distance_num_seg_delay(delta_x, det_routing_arch.num_segment, segment_inf, 1); - /* 2nd step: go vertically */ - delta_y = abs(src_pin_y - des_pin_y); - /* Pass through a number of SB MUX */ - vertical_delay = esti_distance_num_seg_delay(delta_y, det_routing_arch.num_segment, segment_inf, 1); - /* 3rd step: go through a CB MUX */ - path_delay = horizen_delay + vertical_delay - + switch_inf[det_routing_arch.wire_to_ipin_switch].R * switch_inf[det_routing_arch.wire_to_ipin_switch].Cout + switch_inf[det_routing_arch.wire_to_ipin_switch].Tdel; - break; - case LEFT: - case RIGHT: - /* 1st step: go vertically */ - delta_y = abs(src_pin_y - des_pin_y); - /* Pass through a number of SB MUX */ - vertical_delay = esti_distance_num_seg_delay(delta_y, det_routing_arch.num_segment, segment_inf, 1); - /* 2nd step: go horizentally */ - delta_x = abs(src_pin_x - des_pin_x); - /* Pass through a number of SB MUX */ - horizen_delay = esti_distance_num_seg_delay(delta_x, det_routing_arch.num_segment, segment_inf, 1); - /* 3rd step: go through a CB MUX */ - path_delay = horizen_delay + vertical_delay - + switch_inf[det_routing_arch.wire_to_ipin_switch].R * switch_inf[det_routing_arch.wire_to_ipin_switch].Cout + switch_inf[det_routing_arch.wire_to_ipin_switch].Tdel; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, LINE[%d])Invalid side!\n", __FILE__, __LINE__); - exit(1); - } - - return path_delay; -} - -void load_expected_remapped_net_delay(float** net_delay, - int n_blks, - t_block* blk, - int n_nets, - t_net* nets, - t_det_routing_arch det_routing_arch, - t_segment_inf* segment_inf, - t_timing_inf timing_inf, - int num_directs, - t_direct_inf* directs) { - int inet, isink, i; - int src_blk_index, src_blk_pin_index, src_blk_pin_side; - int des_blk_index, des_blk_pin_index, des_blk_pin_side; - float esti_path_delay = -1.; - float pin2pin_one_sink_delay = 0.; - float penalty = 0.; - - /* Search each clb net, find the driver (OPIN) and all the receivers (IPINs) */ - for (inet = 0; inet < n_nets; inet++) { - /* Global nets, we don't optimize */ - if (TRUE == nets[inet].is_global) { - load_one_constant_net_delay(net_delay, inet, nets, 0.); - } else { - penalty = get_crossing_penalty(nets[inet].num_sinks); - /* Spot driver (OPIN) location */ - src_blk_index = nets[inet].node_block[0]; - src_blk_pin_index = nets[inet].node_block_pin[0]; - assert(NULL != blk[src_blk_index].type); - src_blk_pin_side = find_blk_net_pin_side(blk[src_blk_index], blk[src_blk_index].type->pin_height[src_blk_pin_index], src_blk_pin_index); - /* Search all the sinks and estimate route delay */ - for (isink = 1; isink < (nets[inet].num_sinks + 1); isink++) { - des_blk_index = nets[inet].node_block[isink]; - des_blk_pin_index = nets[inet].node_block_pin[isink]; - assert(NULL != blk[des_blk_index].type); - des_blk_pin_side = find_blk_net_pin_side(blk[des_blk_index], blk[des_blk_index].type->pin_height[des_blk_pin_index], des_blk_pin_index); - for (i = 0; i < 4; i++) { - if (0 == blk[des_blk_index].pin_prefer_side[des_blk_pin_index][i]) { - continue; /* Bypass non-preferred side */ - } - pin2pin_one_sink_delay = penalty * - esti_pin2pin_one_net_delay(blk[src_blk_index], src_blk_pin_side, src_blk_pin_index, - blk[des_blk_index], des_blk_pin_side, des_blk_pin_index, - det_routing_arch, segment_inf, timing_inf, num_directs, directs); - if ((-1. == esti_path_delay)||(esti_path_delay < pin2pin_one_sink_delay)) { - esti_path_delay = pin2pin_one_sink_delay; - } - } - assert(0. < esti_path_delay); - net_delay[inet][isink] = esti_path_delay; - } - } - } - - return; -} - -float esti_distance_num_seg_delay(int distance, - int num_segment, - t_segment_inf* segment_inf, - int allow_long_segment) { - float esti_delay = 0.; - float min_out_range_esti_delay = 0.; - float max_in_range_esti_delay = 0.; - int iseg, min_out_range_seg, max_in_range_seg; - - /* Find the min-length segment whose length is larger than distance */ - min_out_range_seg = -1; - for (iseg = 0; iseg < num_segment; iseg++) { - if (segment_inf[iseg].length > distance) { - if (-1 == min_out_range_seg) { - min_out_range_seg = iseg; - } else if (segment_inf[iseg].length < segment_inf[min_out_range_seg].length) { - min_out_range_seg = iseg; - } - } - } - /* Find the max-length segment whose length is larger than distance */ - max_in_range_seg = -1; - for (iseg = 0; iseg < num_segment; iseg++) { - if ((segment_inf[iseg].length < distance) - ||(segment_inf[iseg].length == distance)) { - if (-1 == max_in_range_seg) { - max_in_range_seg = iseg; - } else if (segment_inf[iseg].length > segment_inf[max_in_range_seg].length) { - max_in_range_seg = iseg; - } - } - } - - /* Estimate the delay */ - if (-1 != max_in_range_seg) { - max_in_range_esti_delay = esti_one_segment_net_delay(distance, segment_inf[max_in_range_seg]); - } - if (-1 != min_out_range_seg) { - min_out_range_esti_delay = esti_one_segment_net_delay(distance, segment_inf[min_out_range_seg]); - } - - /* If allow longer segment, we should consider in making decision */ - if (allow_long_segment) { - if (min_out_range_esti_delay < max_in_range_esti_delay) { - esti_delay = min_out_range_esti_delay; - } - } else { - esti_delay = max_in_range_esti_delay; - } - - return esti_delay; -} - -float esti_one_segment_net_delay(int distance, t_segment_inf segment_inf) { - int num_sb_mux = 0; - int switch_index = segment_inf.opin_switch; - float one_switch_delay = 0.; - float one_segment_delay = 0.; - float total_delay = 0.; - int i; - - /* If segment length >= distance, only 1 SB MUX is required, - * If segment length < distance, then distance/segment_length SB MUX needed - */ - if (segment_inf.length < distance) { - num_sb_mux = distance/segment_inf.length; - if (0 != distance%segment_inf.length) { - num_sb_mux++; - } - } else { - num_sb_mux = 1; - } - /* Find the driver switch */ - one_switch_delay = switch_inf[switch_index].R * switch_inf[switch_index].Cout + switch_inf[switch_index].Tdel; - for (i = 0; i < segment_inf.length; i++) { - one_segment_delay = segment_inf.Rmetal - *((segment_inf.length - i)*(segment_inf.Cmetal + 2*switch_inf[switch_index].Cin) + switch_inf[switch_index].Cin); - } - - total_delay = num_sb_mux * (one_segment_delay + one_switch_delay); - - return total_delay; -} - -float get_crossing_penalty(int num_sinks) { - float crossing; - if (((num_sinks + 1) > 50) - && ((num_sinks + 1) < 85)) { - crossing = 2.7933 + 0.02616 * (num_sinks + 1) - 50; - } else if ((num_sinks + 1) >= 85) { - crossing = 2.7933 + 0.011 * (num_sinks + 1) - - 0.0000018 * (num_sinks + 1) - * (num_sinks + 1); - } else { - crossing = local_cross_count[(num_sinks + 1) - 1]; - } - - return crossing; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/post_place_timing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/post_place_timing.h deleted file mode 100644 index cfae911d0..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/clb_pin_remap/post_place_timing.h +++ /dev/null @@ -1,54 +0,0 @@ - -void load_post_place_net_delay(float** net_delay, - int n_blks, - t_block* blk, - int n_nets, - t_net* nets, - t_det_routing_arch det_routing_arch, - t_segment_inf* segment_inf, - t_timing_inf timing_inf, - int num_directs, - t_direct_inf* directs); - -float estimate_post_place_one_net_sink_delay(int net_index, - int n_blks, - t_block* blk, - int src_blk_index, - int des_blk_index, - t_det_routing_arch det_routing_arch, - t_segment_inf* segment_inf, - t_timing_inf timing_inf, - int num_directs, - t_direct_inf* directs); - -float esti_pin2pin_one_net_delay(t_block src_blk, - int src_pin_side, - int src_pin_index, - t_block des_blk, - int des_pin_side, - int des_pin_index, - t_det_routing_arch det_routing_arch, - t_segment_inf* segment_inf, - t_timing_inf timing_inf, - int num_directs, - t_direct_inf* directs); - -void load_expected_remapped_net_delay(float** net_delay, - int n_blks, - t_block* blk, - int n_nets, - t_net* nets, - t_det_routing_arch det_routing_arch, - t_segment_inf* segment_inf, - t_timing_inf timing_inf, - int num_directs, - t_direct_inf* directs); - -float esti_distance_num_seg_delay(int distance, - int num_segment, - t_segment_inf* segment_inf, - int allow_long_segment); - -float esti_one_segment_net_delay(int distance, t_segment_inf segment_inf); - -float get_crossing_penalty(int num_sinks); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp deleted file mode 100644 index ff9999f64..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp +++ /dev/null @@ -1,146 +0,0 @@ -/*************************************************************************************** - * This file includes functions that are used to build modules for decoders, including: - * 1. Local decoders used by multiplexers ONLY - * 2. Decoders used by grid/routing/top-level module for memory address decoding - ***************************************************************************************/ -#include -#include -#include "util.h" -#include "vtr_assert.h" - -#include "fpga_x2p_naming.h" -#include "decoder_library_utils.h" -#include "module_manager_utils.h" - -#include "build_decoder_modules.h" - -/*************************************************************************************** - * Create a module for a decoder with a given output size - * - * Inputs - * | | ... | - * v v v - * +-----------+ - * / \ - * / Decoder \ - * +-----------------+ - * | | | ... | | | - * v v v v v v - * Outputs - * - * The outputs are assumes to be one-hot codes (at most only one '1' exist) - * Considering this fact, there are only num_of_outputs conditions to be encoded. - * Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2)) - ***************************************************************************************/ -static -void build_mux_local_decoder_module(ModuleManager& module_manager, - const DecoderLibrary& decoder_lib, - const DecoderId& decoder) { - /* Get the number of inputs */ - size_t addr_size = decoder_lib.addr_size(decoder); - size_t data_size = decoder_lib.data_size(decoder); - - /* TODO: create a name for the local encoder */ - std::string module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(module_id)); - /* Add module ports */ - /* Add each input port */ - BasicPort addr_port(generate_mux_local_decoder_addr_port_name(), addr_size); - module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT); - /* Add each output port */ - BasicPort data_port(generate_mux_local_decoder_data_port_name(), data_size); - module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT); - /* Data port is registered. It should be outputted as - * output reg [lsb:msb] data - */ - module_manager.set_port_is_register(module_id, data_port.get_name(), true); - /* Add data_in port */ - BasicPort data_inv_port(generate_mux_local_decoder_data_inv_port_name(), data_size); - VTR_ASSERT(true == decoder_lib.use_data_inv_port(decoder)); - module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT); -} - - -/*************************************************************************************** - * This function will generate all the unique Verilog modules of local decoders for - * the multiplexers used in a FPGA fabric - * It will reach the goal in two steps: - * 1. Find the unique local decoders w.r.t. the number of inputs/outputs - * We will generate the subgraphs from the multiplexing graph of each multiplexers - * The number of memory bits is the number of outputs. - * From that we can infer the number of inputs of each local decoders. - * Here is an illustrative example of how local decoders are interfaced with multi-level MUXes - * - * +---------+ +---------+ - * | Local | | Local | - * | Decoder | | Decoder | - * | A | | B | - * +---------+ +---------+ - * | ... | | ... | - * v v v v - * +--------------+ +--------------+ - * | MUX Level 0 |--->| MUX Level 1 | - * +--------------+ +--------------+ - * 2. Generate local decoder Verilog modules using behavioral description. - * Note that the implementation of local decoders can be dependent on the technology - * and standard cell libraries. - * Therefore, behavioral Verilog is used and the local decoders should be synthesized - * before running the back-end flow for FPGA fabric - * See more details in the function print_verilog_mux_local_decoder() for more details - ***************************************************************************************/ -void build_mux_local_decoder_modules(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib) { - /* Start time count */ - clock_t t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, - "Building local encoder (for multiplexers) modules..."); - - /* Create a library for local encoders with different sizes */ - DecoderLibrary decoder_lib; - - /* Find unique local decoders for unique branches shared by the multiplexers */ - for (auto mux : mux_lib.muxes()) { - /* Local decoders are need only when users specify them */ - CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); - /* If this MUX does not need local decoder, we skip it */ - if (false == circuit_lib.mux_use_local_encoder(mux_circuit_model)) { - continue; - } - - const MuxGraph& mux_graph = mux_lib.mux_graph(mux); - /* Create a mux graph for the branch circuit */ - std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); - /* Add the decoder to the decoder library */ - for (auto branch_mux_graph : branch_mux_graphs) { - /* The decoder size depends on the number of memories of a branch MUX. - * Note that only when there are >=2 memories, a decoder is needed - */ - size_t decoder_data_size = branch_mux_graph.num_memory_bits(); - if (0 == decoder_data_size) { - continue; - } - /* Try to find if the decoder already exists in the library, - * If there is no such decoder, add it to the library - */ - add_mux_local_decoder_to_library(decoder_lib, decoder_data_size); - } - } - - /* Generate Verilog modules for the found unique local encoders */ - for (const auto& decoder : decoder_lib.decoders()) { - build_mux_local_decoder_module(module_manager, decoder_lib, decoder); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %.2g seconds\n", - run_time_sec); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.h deleted file mode 100644 index 888eae41f..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.h +++ /dev/null @@ -1,15 +0,0 @@ -/*************************************************************************************** - * Header file for build_decoder_modules.cpp - ***************************************************************************************/ -#ifndef BUILD_DECODER_MODULES_H -#define BUILD_DECODER_MODULES_H - -#include "module_manager.h" -#include "mux_library.h" -#include "circuit_library.h" - -void build_mux_local_decoder_modules(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp deleted file mode 100644 index 41895c23d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp +++ /dev/null @@ -1,149 +0,0 @@ -/******************************************************************** - * This file includes the main function to build module graphs - * for the FPGA fabric - *******************************************************************/ -#include -#include -#include - -#include "vtr_assert.h" -#include "util.h" -#include "spice_types.h" -#include "fpga_x2p_utils.h" - -#include "build_essential_modules.h" -#include "build_decoder_modules.h" -#include "build_mux_modules.h" -#include "build_lut_modules.h" -#include "build_wire_modules.h" -#include "build_memory_modules.h" -#include "build_grid_modules.h" -#include "build_routing_modules.h" -#include "build_top_module.h" -#include "build_device_module.h" - -/******************************************************************** - * The main function to be called for building module graphs - * for a FPGA fabric - *******************************************************************/ -ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, - const t_arch& arch, - const MuxLibrary& mux_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector& rr_switches, - const std::vector& clb2clb_directs, - const DeviceRRGSB& L_device_rr_gsb) { - /* Check if the routing architecture we support*/ - if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { - vpr_printf(TIO_MESSAGE_ERROR, - "FPGA X2P only supports uni-directional routing architecture!\n"); - exit(1); - } - - /* We don't support mrFPGA */ -#ifdef MRFPGA_H - if (is_mrFPGA) { - vpr_printf(TIO_MESSAGE_ERROR, - "FPGA X2P does not support mrFPGA!\n"); - exit(1); - } -#endif - - /* Module Graph builder formally starts*/ - vpr_printf(TIO_MESSAGE_INFO, - "\nStart building module graphs for FPGA fabric...\n"); - - /* Module manager to be built */ - ModuleManager module_manager; - - /* Start time count */ - clock_t t_start = clock(); - - /* Assign the SRAM model applied to the FPGA fabric */ - VTR_ASSERT(NULL != arch.sram_inf.verilog_sram_inf_orgz); /* Check !*/ - t_spice_model* mem_model = arch.sram_inf.verilog_sram_inf_orgz->spice_model; - /* initialize the SRAM organization information struct */ - CircuitModelId sram_model = arch.spice->circuit_lib.model(mem_model->name); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - - /* TODO: This should be moved to FPGA-X2P setup - * Check all the SRAM port is using the correct SRAM circuit model - */ - config_spice_models_sram_port_spice_model(arch.spice->num_spice_model, - arch.spice->spice_models, - arch.sram_inf.verilog_sram_inf_orgz->spice_model); - config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, sram_model); - - /* Add constant generator modules: VDD and GND */ - build_constant_generator_modules(module_manager); - - /* Register all the user-defined modules in the module manager - * This should be done prior to other steps in this function, - * because they will be instanciated by other primitive modules - */ - build_user_defined_modules(module_manager, arch.spice->circuit_lib); - - /* Build elmentary modules */ - build_essential_modules(module_manager, arch.spice->circuit_lib); - - /* Build local encoders for multiplexers, this MUST be called before multiplexer building */ - build_mux_local_decoder_modules(module_manager, mux_lib, arch.spice->circuit_lib); - - /* Build multiplexer modules */ - build_mux_modules(module_manager, mux_lib, arch.spice->circuit_lib); - - /* Build LUT modules */ - build_lut_modules(module_manager, arch.spice->circuit_lib); - - /* Build wire modules */ - build_wire_modules(module_manager, arch.spice->circuit_lib); - - /* Build memory modules */ - build_memory_modules(module_manager, mux_lib, arch.spice->circuit_lib, - arch.sram_inf.verilog_sram_inf_orgz->type); - - /* Build grid and programmable block modules */ - build_grid_modules(module_manager, arch.spice->circuit_lib, mux_lib, - arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, - TRUE == vpr_setup.FPGA_SPICE_Opts.duplicate_grid_pin); - - if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) { - build_unique_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, - arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, - vpr_setup.RoutingArch, rr_switches); - } else { - VTR_ASSERT(FALSE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); - build_flatten_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, - arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, - vpr_setup.RoutingArch, rr_switches); - } - - - /* Build FPGA fabric top-level module */ - build_top_module(module_manager, arch.spice->circuit_lib, - device_size, grids, L_device_rr_gsb, - clb2clb_directs, - arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, - TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy, - TRUE == vpr_setup.FPGA_SPICE_Opts.duplicate_grid_pin); - - /* Now a critical correction has to be done! - * In the module construction, we always use prefix of ports because they are binded - * to the ports in architecture description (logic blocks etc.) - * To interface with standard cell, we should - * rename the ports of primitive modules using lib_name instead of prefix - * (which have no children and are probably linked to a standard cell!) - */ - rename_primitive_module_port_names(module_manager, arch.spice->circuit_lib); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "Building module graphs took %g seconds\n", - run_time_sec); - - return module_manager; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.h deleted file mode 100644 index 40ce9e9c5..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef BUILD_DEVICE_MODULE_H -#define BUILD_DEVICE_MODULE_H - -#include -#include "vpr_types.h" -#include "rr_blocks.h" -#include "mux_library.h" -#include "module_manager.h" - -ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, - const t_arch& arch, - const MuxLibrary& mux_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector& rr_switches, - const std::vector& clb2clb_directs, - const DeviceRRGSB& L_device_rr_gsb); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp deleted file mode 100644 index 9bb471710..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp +++ /dev/null @@ -1,305 +0,0 @@ -/******************************************************************** - * This function includes the module builders for essential logic gates - * which are the leaf circuit model in the circuit library - *******************************************************************/ -#include -#include -#include "util.h" -#include "vtr_assert.h" - -#include "fpga_x2p_naming.h" -#include "module_manager_utils.h" -#include "build_essential_modules.h" - -/************************************************ - * Build a module of inverter or buffer - * or tapered buffer to a file - ***********************************************/ -static -void build_invbuf_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - /* Find the input port, output port and global inputs*/ - std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); - - /* Make sure: - * There is only 1 input port and 1 output port, - * each size of which is 1 - */ - VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) ); - VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); - - /* TODO: move the check codes to check_circuit_library.h */ - /* If the circuit model is power-gated, we need to find at least one global config_enable signals */ - if (true == circuit_lib.is_power_gated(circuit_model)) { - /* Check all the ports we have are good for a power-gated circuit model */ - size_t num_err = 0; - /* We need at least one global port */ - if (0 == global_ports.size()) { - num_err++; - } - /* All the global ports should be config_enable */ - for (const auto& port : global_ports) { - if (false == circuit_lib.port_is_config_enable(port)) { - num_err++; - } - } - /* Report errors if there are any */ - if (0 < num_err) { - vpr_printf(TIO_MESSAGE_ERROR, - "Inverter/buffer circuit model (name=%s) is power-gated. At least one config-enable global port is required!\n", - circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - } - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); - VTR_ASSERT(true == module_manager.valid_module_id(module_id)); -} - -/************************************************ - * Build a module of a pass-gate, - * either transmission-gate or pass-transistor - ***********************************************/ -static -void build_passgate_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - /* Find the input port, output port*/ - std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); - - switch (circuit_lib.pass_gate_logic_type(circuit_model)) { - case SPICE_MODEL_PASS_GATE_TRANSMISSION: - /* Make sure: - * There is only 3 input port (in, sel, selb), - * each size of which is 1 - */ - VTR_ASSERT( 3 == input_ports.size() ); - for (const auto& input_port : input_ports) { - VTR_ASSERT(1 == circuit_lib.port_size(input_port)); - } - break; - case SPICE_MODEL_PASS_GATE_TRANSISTOR: - /* Make sure: - * There is only 2 input port (in, sel), - * each size of which is 1 - */ - VTR_ASSERT( 2 == input_ports.size() ); - for (const auto& input_port : input_ports) { - VTR_ASSERT(1 == circuit_lib.port_size(input_port)); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - - /* Make sure: - * There is only 1 output port, - * each size of which is 1 - */ - VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); - VTR_ASSERT(true == module_manager.valid_module_id(module_id)); -} - -/************************************************ - * Build a module of a logic gate - * which are standard cells - * Supported gate types: - * 1. N-input AND - * 2. N-input OR - * 3. 2-input MUX - ***********************************************/ -static -void build_gate_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - /* Find the input port, output port*/ - std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); - - /* Make sure: - * There is only 1 output port, - * each size of which is 1 - */ - VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); - VTR_ASSERT(true == module_manager.valid_module_id(module_id)); -} - - -/************************************************ - * Generate the modules for essential gates - * include inverters, buffers, transmission-gates, - * etc. - ***********************************************/ -void build_essential_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib) { - /* Start time count */ - clock_t t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, - "Building essential (inverter/buffer/logic gate) modules..."); - - for (const auto& circuit_model : circuit_lib.models()) { - /* Add essential modules upon on demand: only when it is not yet in the module library */ - ModuleId module = module_manager.find_module(circuit_lib.model_name(circuit_model)); - if (true == module_manager.valid_module_id(module)) { - continue; - } - - if (SPICE_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { - build_invbuf_module(module_manager, circuit_lib, circuit_model); - continue; - } - if (SPICE_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) { - build_passgate_module(module_manager, circuit_lib, circuit_model); - continue; - } - if (SPICE_MODEL_GATE == circuit_lib.model_type(circuit_model)) { - build_gate_module(module_manager, circuit_lib, circuit_model); - continue; - } - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %.2g seconds\n", - run_time_sec); -} - -/********************************************************************* - * Register all the user-defined modules in the module manager - * Walk through the circuit library and add user-defined circuit models - * to the module_manager - ********************************************************************/ -void build_user_defined_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib) { - /* Start time count */ - clock_t t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, - "Building user-defined modules..."); - - /* Iterate over Verilog modules */ - for (const auto& model : circuit_lib.models()) { - /* We only care about user-defined models */ - if ( (true == circuit_lib.model_verilog_netlist(model).empty()) - && (true == circuit_lib.model_spice_netlist(model).empty()) ) { - continue; - } - /* Skip Routing channel wire models because they need a different name. Do it later */ - if (SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) { - continue; - } - /* Reach here, the model requires a user-defined Verilog netlist, - * Register it in the module_manager - */ - add_circuit_model_to_module_manager(module_manager, circuit_lib, model); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %.2g seconds\n", - run_time_sec); -} - -/********************************************************************* - * This function will build a constant generator modules - * and add it to the module manager - * It could be either - * 1. VDD or 2. GND - * Each module will have only one output port - ********************************************************************/ -static -void build_constant_generator_module(ModuleManager& module_manager, - const size_t& const_value) { - ModuleId const_module = module_manager.add_module(generate_const_value_module_name(const_value)); - /* Add one output port */ - BasicPort const_output_port(generate_const_value_module_output_port_name(const_value), 1); - module_manager.add_port(const_module, const_output_port, ModuleManager::MODULE_OUTPUT_PORT); -} - -/********************************************************************* - * This function will add two constant generator modules - * to the module manager - * 1. VDD - * 2. GND - ********************************************************************/ -void build_constant_generator_modules(ModuleManager& module_manager) { - /* Start time count */ - clock_t t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, - "Building constant generator modules..."); - - /* VDD */ - build_constant_generator_module(module_manager, 1); - - /* GND */ - build_constant_generator_module(module_manager, 0); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %.2g seconds\n", - run_time_sec); -} - -/********************************************************************* - * This function will rename the ports of primitive modules - * using lib_name instead of prefix - * Primitive modules are defined as those modules in the module manager - * which have user defined netlists - ********************************************************************/ -void rename_primitive_module_port_names(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib) { - for (const CircuitModelId& model : circuit_lib.models()) { - /* We only care about user-defined models */ - if ( (true == circuit_lib.model_verilog_netlist(model).empty()) - && (true == circuit_lib.model_spice_netlist(model).empty()) ) { - continue; - } - /* Skip Routing channel wire models because they need a different name. Do it later */ - if (SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) { - continue; - } - /* Find the module in module manager */ - ModuleId module = module_manager.find_module(circuit_lib.model_name(model)); - /* We must find one! */ - VTR_ASSERT(true == module_manager.valid_module_id(module)); - - /* Rename all the ports to use lib_name! */ - for (const CircuitPortId& model_port : circuit_lib.model_ports(model)) { - /* Find the module port in module manager. We used prefix when creating the ports */ - ModulePortId module_port = module_manager.find_module_port(module, circuit_lib.port_prefix(model_port)); - /* We must find one! */ - VTR_ASSERT(true == module_manager.valid_module_port_id(module, module_port)); - /* Name it with lib_name */ - module_manager.set_module_port_name(module, module_port, circuit_lib.port_lib_name(model_port)); - } - } -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h deleted file mode 100644 index 703d8a285..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef BUILD_ESSENTIAL_MODULES_H -#define BUILD_ESSENTIAL_MODULES_H - -#include "circuit_library.h" -#include "module_manager.h" - -void build_essential_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib); - -void build_user_defined_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib); - -void build_constant_generator_modules(ModuleManager& module_manager); - -void rename_primitive_module_port_names(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.cpp deleted file mode 100644 index 4b747f77f..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.cpp +++ /dev/null @@ -1,273 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to add duplicated - * pins to each side of a grid - * - * These functions are located in this file, being separated from - * the default functions in build_grid_module.cpp - * This allows us to keep new features easy to be maintained. - * - * Please follow this rules when creating new features! - *******************************************************************/ -/* External library headers */ -#include "vtr_assert.h" - -/* FPGA-X2P headers */ -#include "fpga_x2p_naming.h" - -/* Module builder headers */ -#include "build_grid_module_utils.h" -#include "build_grid_module_duplicated_pins.h" - -/* Global variables should be the last to include */ -#include "globals.h" - -/******************************************************************** - * This function adds pb_type ports to top-level grid module with duplication - * For each pin at each side, we create two pins which are short-wired - * They are driven by the same pin, e.g., pinA in the child module - * But in this top module, we will create two pins, each of which indicates - * the physical location of pin. - * Take the following example: - * One is called pinA_upper which is located close to the top side of this grid - * The other is called pinA_lower which is located close to the bottom side of this grid - * - * Similarly, we duplicate pins at TOP, RIGHT, BOTTOM and LEFT sides. - * For LEFT side, upper and lower pins carry the indication in physical location as RIGHT side. - * For TOP and BOTTOM side, upper pin is located close to the left side of a grid, while lower - * pin is located close to the right side of a grid - * - * pinB_upper pinB_lower - * ^ ^ - * | | - * ---------------+ - * |--->pinA_upper - * | - * Grid | - * | - * |--->pinA_lower - * ---------------+ - *******************************************************************/ -void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, - const ModuleId& grid_module, - t_type_ptr grid_type_descriptor, - const e_side& border_side) { - /* Ensure that we have a valid grid_type_descriptor */ - VTR_ASSERT(NULL != grid_type_descriptor); - - /* Find the pin side for I/O grids*/ - std::vector grid_pin_sides; - /* For I/O grids, we care only one side - * Otherwise, we will iterate all the 4 sides - */ - if (IO_TYPE == grid_type_descriptor) { - grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side)); - } else { - grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; - } - - /* Create a map between pin class type and grid pin direction */ - std::map pin_type2type_map; - pin_type2type_map[RECEIVER] = ModuleManager::MODULE_INPUT_PORT; - pin_type2type_map[DRIVER] = ModuleManager::MODULE_OUTPUT_PORT; - - /* Iterate over sides, height and pins */ - for (const e_side& side : grid_pin_sides) { - for (int iheight = 0; iheight < grid_type_descriptor->height; ++iheight) { - for (int ipin = 0; ipin < grid_type_descriptor->num_pins; ++ipin) { - if (1 != grid_type_descriptor->pinloc[iheight][side][ipin]) { - continue; - } - /* Reach here, it means this pin is on this side */ - int class_id = grid_type_descriptor->pin_class[ipin]; - e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type; - /* Generate the pin name - * For each RECEIVER PIN or DRIVER PIN for direct connection, - * we do not duplicate in these cases */ - if ( (RECEIVER == pin_class_type) - /* Xifan: I assume that each direct connection pin must have Fc=0. */ - || ( (DRIVER == pin_class_type) && (0. == grid_type_descriptor->Fc[ipin]) ) ) { - vtr::Point dummy_coordinate; - std::string port_name = generate_grid_port_name(dummy_coordinate, iheight, side, ipin, false); - BasicPort grid_port(port_name, 0, 0); - /* Add the port to the module */ - module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]); - } else { - /* For each DRIVER pin, we create two copies. - * One with a postfix of upper, indicating it is located on the upper part of a side - * The other with a postfix of lower, indicating it is located on the lower part of a side - */ - VTR_ASSERT(DRIVER == pin_class_type); - std::string upper_port_name = generate_grid_duplicated_port_name(iheight, side, ipin, true); - BasicPort grid_upper_port(upper_port_name, 0, 0); - /* Add the port to the module */ - module_manager.add_port(grid_module, grid_upper_port, pin_type2type_map[pin_class_type]); - - std::string lower_port_name = generate_grid_duplicated_port_name(iheight, side, ipin, false); - BasicPort grid_lower_port(lower_port_name, 0, 0); - /* Add the port to the module */ - module_manager.add_port(grid_module, grid_lower_port, pin_type2type_map[pin_class_type]); - } - } - } - } -} - -/******************************************************************** - * Add module nets to connect a port of child pb_module - * to the duplicated pins of grid module - * Note: This function SHOULD be ONLY applied to pb_graph output pins - * of the child module. - * For each such pin, we connect it to two outputs of the grid module - * one is named after "upper", and the other is named after "lower" - *******************************************************************/ -static -void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_manager, - const ModuleId& grid_module, - const ModuleId& child_module, - const size_t& child_instance, - t_type_ptr grid_type_descriptor, - t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, - const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) { - /* Make sure this is ONLY applied to output pins */ - VTR_ASSERT(OUTPUT2OUTPUT_INTERC == pin2pin_interc_type); - - /* Find the pin side for I/O grids*/ - std::vector grid_pin_sides; - /* For I/O grids, we care only one side - * Otherwise, we will iterate all the 4 sides - */ - if (IO_TYPE == grid_type_descriptor) { - grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side)); - } else { - grid_pin_sides.push_back(TOP); - grid_pin_sides.push_back(RIGHT); - grid_pin_sides.push_back(BOTTOM); - grid_pin_sides.push_back(LEFT); - } - - /* num_pins/capacity = the number of pins that each type_descriptor has. - * Capacity defines the number of type_descriptors in each grid - * so the pin index at grid level = pin_index_in_type_descriptor - * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor - */ - size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster - + child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity; - int pin_height = grid_type_descriptor->pin_height[grid_pin_index]; - for (const e_side& side : grid_pin_sides) { - if (1 != grid_type_descriptor->pinloc[pin_height][side][grid_pin_index]) { - continue; - } - - /* Pins for direct connection are NOT duplicated. - * Follow the traditional recipe when adding nets! - * Xifan: I assume that each direct connection pin must have Fc=0. - */ - if (0. == grid_type_descriptor->Fc[grid_pin_index]) { - /* Create a net to connect the grid pin to child module pin */ - ModuleNetId net = module_manager.create_module_net(grid_module); - /* Find the port in grid_module */ - vtr::Point dummy_coordinate; - std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_height, side, grid_pin_index, false); - ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id)); - - /* Grid port always has only 1 pin, it is assumed when adding these ports to the module - * if you need a change, please also change the port adding codes - */ - size_t grid_module_pin_id = 0; - /* Find the port in child module */ - std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port); - ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id)); - size_t child_module_pin_id = pb_graph_pin->pin_number; - /* Add net sources and sinks: - * For output-to-output connection, net_source is pb_graph_pin, while net_sink is grid pin - */ - module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id); - module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id); - continue; - } - /* Reach here, it means this pin is on this side */ - /* Create a net to connect the grid pin to child module pin */ - ModuleNetId net = module_manager.create_module_net(grid_module); - /* Find the upper port in grid_module */ - std::string grid_upper_port_name = generate_grid_duplicated_port_name(pin_height, side, grid_pin_index, true); - ModulePortId grid_module_upper_port_id = module_manager.find_module_port(grid_module, grid_upper_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_upper_port_id)); - - /* Find the lower port in grid_module */ - std::string grid_lower_port_name = generate_grid_duplicated_port_name(pin_height, side, grid_pin_index, false); - ModulePortId grid_module_lower_port_id = module_manager.find_module_port(grid_module, grid_lower_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_lower_port_id)); - - /* Grid port always has only 1 pin, it is assumed when adding these ports to the module - * if you need a change, please also change the port adding codes - */ - size_t grid_module_pin_id = 0; - /* Find the port in child module */ - std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port); - ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id)); - size_t child_module_pin_id = pb_graph_pin->pin_number; - - /* Add net sources and sinks: - * For output-to-output connection, - * net_source is pb_graph_pin, - * while net_sinks are grid upper pin and grid lower pin - */ - module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id); - module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_upper_port_id, grid_module_pin_id); - module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_lower_port_id, grid_module_pin_id); - } -} - -/******************************************************************** - * Add module nets to connect a port of child pb_module - * to the duplicated ports of grid module - *******************************************************************/ -void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module_manager, - const ModuleId& grid_module, - const ModuleId& child_module, - const size_t& child_instance, - t_type_ptr grid_type_descriptor, - const e_side& border_side) { - /* Ensure that we have a valid grid_type_descriptor */ - VTR_ASSERT(NULL != grid_type_descriptor); - t_pb_graph_node* top_pb_graph_node = grid_type_descriptor->pb_graph_head; - VTR_ASSERT(NULL != top_pb_graph_node); - - for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) { - for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) { - add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, - child_module, child_instance, - grid_type_descriptor, - &(top_pb_graph_node->input_pins[iport][ipin]), - border_side, - INPUT2INPUT_INTERC); - - } - } - - for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) { - for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) { - add_grid_module_net_connect_duplicated_pb_graph_pin(module_manager, grid_module, - child_module, child_instance, - grid_type_descriptor, - &(top_pb_graph_node->output_pins[iport][ipin]), - border_side, - OUTPUT2OUTPUT_INTERC); - } - } - - for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) { - for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) { - add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, - child_module, child_instance, - grid_type_descriptor, - &(top_pb_graph_node->clock_pins[iport][ipin]), - border_side, - INPUT2INPUT_INTERC); - } - } -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.h deleted file mode 100644 index feaca16fd..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef BUILD_GRID_MODULE_DUPLICATED_PINS_H -#define BUILD_GRID_MODULE_DUPLICATED_PINS_H - -#include "module_manager.h" -#include "sides.h" -#include "vpr_types.h" - -void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, - const ModuleId& grid_module, - t_type_ptr grid_type_descriptor, - const e_side& border_side); - -void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module_manager, - const ModuleId& grid_module, - const ModuleId& child_module, - const size_t& child_instance, - t_type_ptr grid_type_descriptor, - const e_side& border_side); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_utils.cpp deleted file mode 100644 index 3c409ebb2..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_utils.cpp +++ /dev/null @@ -1,106 +0,0 @@ -/******************************************************************** - * This file includes most utilized functions for grid module builders - *******************************************************************/ -/* External library headers */ -#include "vtr_assert.h" - -/* FPGA-X2P headers */ -#include "fpga_x2p_naming.h" - -/* Module builder headers */ -#include "build_grid_module_utils.h" - -/* Global variables should be the last to include */ -#include "globals.h" - -/******************************************************************** - * Find the side where I/O pins locate on a grid I/O block - * 1. I/O grids on the top side of FPGA only have ports on its bottom side - * 2. I/O grids on the right side of FPGA only have ports on its left side - * 3. I/O grids on the bottom side of FPGA only have ports on its top side - * 4. I/O grids on the left side of FPGA only have ports on its right side - *******************************************************************/ -e_side find_grid_module_pin_side(t_type_ptr grid_type_descriptor, - const e_side& border_side) { - VTR_ASSERT(IO_TYPE == grid_type_descriptor); - Side side_manager(border_side); - return side_manager.get_opposite(); -} - -/******************************************************************** - * Add module nets to connect a port of child pb_module - * to the grid module - *******************************************************************/ -void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager, - const ModuleId& grid_module, - const ModuleId& child_module, - const size_t& child_instance, - t_type_ptr grid_type_descriptor, - t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, - const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) { - /* Find the pin side for I/O grids*/ - std::vector grid_pin_sides; - /* For I/O grids, we care only one side - * Otherwise, we will iterate all the 4 sides - */ - if (IO_TYPE == grid_type_descriptor) { - grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side)); - } else { - grid_pin_sides.push_back(TOP); - grid_pin_sides.push_back(RIGHT); - grid_pin_sides.push_back(BOTTOM); - grid_pin_sides.push_back(LEFT); - } - - /* num_pins/capacity = the number of pins that each type_descriptor has. - * Capacity defines the number of type_descriptors in each grid - * so the pin index at grid level = pin_index_in_type_descriptor - * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor - */ - size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster - + child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity; - int pin_height = grid_type_descriptor->pin_height[grid_pin_index]; - for (const e_side& side : grid_pin_sides) { - if (1 != grid_type_descriptor->pinloc[pin_height][side][grid_pin_index]) { - continue; - } - /* Reach here, it means this pin is on this side */ - /* Create a net to connect the grid pin to child module pin */ - ModuleNetId net = module_manager.create_module_net(grid_module); - /* Find the port in grid_module */ - vtr::Point dummy_coordinate; - std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_height, side, grid_pin_index, false); - ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id)); - /* Grid port always has only 1 pin, it is assumed when adding these ports to the module - * if you need a change, please also change the port adding codes - */ - size_t grid_module_pin_id = 0; - /* Find the port in child module */ - std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port); - ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id)); - size_t child_module_pin_id = pb_graph_pin->pin_number; - /* Add net sources and sinks: - * For input-to-input connection, net_source is grid pin, while net_sink is pb_graph_pin - * For output-to-output connection, net_source is pb_graph_pin, while net_sink is grid pin - */ - switch (pin2pin_interc_type) { - case INPUT2INPUT_INTERC: - module_manager.add_module_net_source(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id); - module_manager.add_module_net_sink(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id); - break; - case OUTPUT2OUTPUT_INTERC: - module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id); - module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid pin-to-pin interconnection type!\n", - __FILE__, __LINE__); - exit(1); - } - } -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_utils.h deleted file mode 100644 index 25d7abddb..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_utils.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef BUILD_GRID_MODULE_UTILS_H -#define BUILD_GRID_MODULE_UTILS_H - -#include "vpr_types.h" -#include "sides.h" -#include "spice_types.h" -#include "module_manager.h" - -e_side find_grid_module_pin_side(t_type_ptr grid_type_descriptor, - const e_side& border_side); - -void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager, - const ModuleId& grid_module, - const ModuleId& child_module, - const size_t& child_instance, - t_type_ptr grid_type_descriptor, - t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, - const enum e_spice_pin2pin_interc_type& pin2pin_interc_type); - - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp deleted file mode 100644 index 6a98d89c5..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ /dev/null @@ -1,1137 +0,0 @@ -/******************************************************************** - * This file includes functions to print Verilog modules for a Grid - * (CLBs, I/Os, heterogeneous blocks etc.) - *******************************************************************/ -/* System header files */ -#include -#include - -/* Header files from external libs */ -#include "vtr_geometry.h" -#include "util.h" -#include "vtr_assert.h" -#include "circuit_library_utils.h" - -/* Header files for VPR */ -#include "vpr_types.h" -#include "globals.h" - -/* Header files for FPGA X2P tool suite */ -#include "fpga_x2p_reserved_words.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "module_manager_utils.h" -#include "fpga_x2p_globals.h" - -/* Header files for Verilog generator */ -#include "verilog_global.h" -#include "build_grid_module_utils.h" -#include "build_grid_module_duplicated_pins.h" -#include "build_grid_modules.h" - -/******************************************************************** - * Add ports/pins to a grid module - * This function will iterate over all the pins that are defined - * in type_descripter and give a name by its height, side and index - * - * In particular, for I/O grid, only part of the ports on required - * on a specific side. - *******************************************************************/ -static -void add_grid_module_pb_type_ports(ModuleManager& module_manager, - const ModuleId& grid_module, - t_type_ptr grid_type_descriptor, - const e_side& border_side) { - /* Ensure that we have a valid grid_type_descriptor */ - VTR_ASSERT(NULL != grid_type_descriptor); - - /* Find the pin side for I/O grids*/ - std::vector grid_pin_sides; - /* For I/O grids, we care only one side - * Otherwise, we will iterate all the 4 sides - */ - if (IO_TYPE == grid_type_descriptor) { - grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side)); - } else { - grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; - } - - /* Create a map between pin class type and grid pin direction */ - std::map pin_type2type_map; - pin_type2type_map[RECEIVER] = ModuleManager::MODULE_INPUT_PORT; - pin_type2type_map[DRIVER] = ModuleManager::MODULE_OUTPUT_PORT; - - /* Iterate over sides, height and pins */ - for (const e_side& side : grid_pin_sides) { - for (int iheight = 0; iheight < grid_type_descriptor->height; ++iheight) { - for (int ipin = 0; ipin < grid_type_descriptor->num_pins; ++ipin) { - if (1 != grid_type_descriptor->pinloc[iheight][side][ipin]) { - continue; - } - /* Reach here, it means this pin is on this side */ - int class_id = grid_type_descriptor->pin_class[ipin]; - e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type; - /* Generate the pin name, - * we give a empty coordinate but it will not be used (see details in the function - */ - vtr::Point dummy_coordinate; - std::string port_name = generate_grid_port_name(dummy_coordinate, iheight, side, ipin, false); - BasicPort grid_port(port_name, 0, 0); - /* Add the port to the module */ - module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]); - } - } - } -} - -/******************************************************************** - * Add module nets to connect ports/pins of a grid module - * to its child modules - * This function will iterate over all the pins that are defined - * in type_descripter and find the corresponding pin in the top - * pb_graph_node of the grid - *******************************************************************/ -static -void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, - const ModuleId& grid_module, - const ModuleId& child_module, - const size_t& child_instance, - t_type_ptr grid_type_descriptor, - const e_side& border_side) { - /* Ensure that we have a valid grid_type_descriptor */ - VTR_ASSERT(NULL != grid_type_descriptor); - t_pb_graph_node* top_pb_graph_node = grid_type_descriptor->pb_graph_head; - VTR_ASSERT(NULL != top_pb_graph_node); - - for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) { - for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) { - add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, - child_module, child_instance, - grid_type_descriptor, - &(top_pb_graph_node->input_pins[iport][ipin]), - border_side, - INPUT2INPUT_INTERC); - - } - } - - for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) { - for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) { - add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, - child_module, child_instance, - grid_type_descriptor, - &(top_pb_graph_node->output_pins[iport][ipin]), - border_side, - OUTPUT2OUTPUT_INTERC); - } - } - - for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) { - for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) { - add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, - child_module, child_instance, - grid_type_descriptor, - &(top_pb_graph_node->clock_pins[iport][ipin]), - border_side, - INPUT2INPUT_INTERC); - } - } -} - -/******************************************************************** - * Add module nets between primitive module and its internal circuit module - * This is only applicable to the primitive module of a grid - *******************************************************************/ -static -void add_primitive_module_fpga_global_io_port(ModuleManager& module_manager, - const ModuleId& primitive_module, - const ModuleId& logic_module, - const size_t& logic_instance_id, - const ModuleManager::e_module_port_type& module_io_port_type, - const CircuitLibrary& circuit_lib, - const CircuitModelId& primitive_model, - const CircuitPortId& circuit_port) { - BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model, circuit_port), circuit_lib.port_size(circuit_port)); - ModulePortId primitive_io_port_id = module_manager.add_port(primitive_module, module_port, module_io_port_type); - ModulePortId logic_io_port_id = module_manager.find_module_port(logic_module, circuit_lib.port_prefix(circuit_port)); - BasicPort logic_io_port = module_manager.module_port(logic_module, logic_io_port_id); - VTR_ASSERT(logic_io_port.get_width() == module_port.get_width()); - - /* Wire the GPIO port form primitive_module to the logic module!*/ - for (size_t pin_id = 0; pin_id < module_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(primitive_module); - if ( (ModuleManager::MODULE_GPIO_PORT == module_io_port_type) - || (ModuleManager::MODULE_GPIN_PORT == module_io_port_type) ) { - module_manager.add_module_net_source(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]); - module_manager.add_module_net_sink(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]); - } else { - VTR_ASSERT(ModuleManager::MODULE_GPOUT_PORT == module_io_port_type); - module_manager.add_module_net_source(primitive_module, net, logic_module, logic_instance_id, logic_io_port_id, logic_io_port.pins()[pin_id]); - module_manager.add_module_net_sink(primitive_module, net, primitive_module, 0, primitive_io_port_id, module_port.pins()[pin_id]); - } - } -} - - -/******************************************************************** - * Print Verilog modules of a primitive node in the pb_graph_node graph - * This generic function can support all the different types of primitive nodes - * i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders. - * - * The Verilog module will consist of two parts: - * 1. Logic module of the primitive node - * This module performs the logic function of the block - * 2. Memory module of the primitive node - * This module stores the configuration bits for the logic module - * if the logic module is a programmable resource, such as LUT - * - * Verilog module structure: - * - * Primitive block - * +---------------------------------------+ - * | | - * | +---------+ +---------+ | - * in |----->| |--->| |<------|configuration lines - * | | Logic |... | Memory | | - * out|<-----| |--->| | | - * | +---------+ +---------+ | - * | | - * +---------------------------------------+ - * - *******************************************************************/ -static -void build_primitive_block_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - t_pb_graph_node* primitive_pb_graph_node, - const e_side& io_side) { - /* Ensure a valid pb_graph_node */ - if (NULL == primitive_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid primitive_pb_graph_node!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Find the circuit model id linked to the pb_graph_node */ - CircuitModelId& primitive_model = primitive_pb_graph_node->pb_type->circuit_model; - - /* Generate the module name for this primitive pb_graph_node*/ - std::string primitive_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), io_side); - std::string primitive_module_name = generate_physical_block_module_name(primitive_module_name_prefix, primitive_pb_graph_node->pb_type); - - /* Create a module of the primitive LUT and register it to module manager */ - ModuleId primitive_module = module_manager.add_module(primitive_module_name); - /* Ensure that the module has been created and thus unique! */ - VTR_ASSERT(ModuleId::INVALID() != primitive_module); - - /* Note: to cooperate with the pb_type hierarchy and connections, we add the port of primitive pb_type here. - * Since we have linked pb_type ports to circuit models when setting up FPGA-X2P, - * no ports of the circuit model will be missing here - */ - add_primitive_pb_type_ports_to_module_manager(module_manager, primitive_module, primitive_pb_graph_node->pb_type); - - /* Add configuration ports */ - /* Shared SRAM ports*/ - size_t num_shared_config_bits = find_circuit_num_shared_config_bits(circuit_lib, primitive_model, sram_orgz_type); - if (0 < num_shared_config_bits) { - /* Check: this SRAM organization type must be memory-bank ! */ - VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == sram_orgz_type ); - /* Generate a list of ports */ - add_reserved_sram_ports_to_module_manager(module_manager, primitive_module, - num_shared_config_bits); - } - - /* Regular (independent) SRAM ports */ - size_t num_config_bits = find_circuit_num_config_bits(circuit_lib, primitive_model); - if (0 < num_config_bits) { - add_sram_ports_to_module_manager(module_manager, primitive_module, - circuit_lib, sram_model, sram_orgz_type, - num_config_bits); - } - - /* Find the module id in the module manager */ - ModuleId logic_module = module_manager.find_module(circuit_lib.model_name(primitive_model)); - VTR_ASSERT(ModuleId::INVALID() != logic_module); - size_t logic_instance_id = module_manager.num_instance(primitive_module, logic_module); - /* Add the logic module as a child of primitive module */ - module_manager.add_child_module(primitive_module, logic_module); - - /* Add nets to connect the logic model ports to pb_type ports */ - add_primitive_pb_type_module_nets(module_manager, primitive_module, logic_module, logic_instance_id, circuit_lib, primitive_pb_graph_node->pb_type); - - /* Add the associated memory module as a child of primitive module */ - std::string memory_module_name = generate_memory_module_name(circuit_lib, primitive_model, sram_model, std::string(MEMORY_MODULE_POSTFIX)); - ModuleId memory_module = module_manager.find_module(memory_module_name); - - /* Vectors to record all the memory modules have been added - * They are used to add module nets of configuration bus - */ - std::vector memory_modules; - std::vector memory_instances; - - /* If there is no memory module required, we can skip the assocated net addition */ - if (ModuleId::INVALID() != memory_module) { - size_t memory_instance_id = module_manager.num_instance(primitive_module, memory_module); - /* Add the memory module as a child of primitive module */ - module_manager.add_child_module(primitive_module, memory_module); - /* Set an instance name to bind to a block in bitstream generation */ - module_manager.set_child_instance_name(primitive_module, memory_module, memory_instance_id, memory_module_name); - - /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ - add_module_nets_between_logic_and_memory_sram_bus(module_manager, primitive_module, - logic_module, logic_instance_id, - memory_module, memory_instance_id, - circuit_lib, primitive_model); - /* Record memory-related information */ - module_manager.add_configurable_child(primitive_module, memory_module, memory_instance_id); - } - /* Add all the nets to connect configuration ports from memory module to primitive modules - * This is a one-shot addition that covers all the memory modules in this primitive module! - */ - if (0 < module_manager.configurable_children(primitive_module).size()) { - add_module_nets_memory_config_bus(module_manager, primitive_module, - sram_orgz_type, circuit_lib.design_tech_type(sram_model)); - } - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, primitive_module); - - /* Find the inout ports required by the primitive node, and add them to the module - * This is mainly due to the I/O blocks, which have inout ports for the top-level fabric - */ - if (SPICE_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) { - std::vector primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT); - for (auto port : primitive_model_inout_ports) { - add_primitive_module_fpga_global_io_port(module_manager, primitive_module, - logic_module, logic_instance_id, - ModuleManager::MODULE_GPIO_PORT, - circuit_lib, - primitive_model, - port); - } - } - - /* Find the other i/o ports required by the primitive node, and add them to the module */ - for (const auto& port : circuit_lib.model_global_ports(primitive_model, false)) { - if ( (SPICE_MODEL_PORT_INPUT == circuit_lib.port_type(port)) - && (true == circuit_lib.port_is_io(port)) ) { - add_primitive_module_fpga_global_io_port(module_manager, primitive_module, - logic_module, logic_instance_id, - ModuleManager::MODULE_GPIN_PORT, - circuit_lib, - primitive_model, - port); - } else if (SPICE_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)) { - add_primitive_module_fpga_global_io_port(module_manager, primitive_module, - logic_module, logic_instance_id, - ModuleManager::MODULE_GPOUT_PORT, - circuit_lib, - primitive_model, - port); - } - } -} - -/******************************************************************** - * This function add a net for a pin-to-pin connection defined in pb_graph - * It supports two cases for the pin-to-pin connection - * 1. The net source is a pb_graph_pin while the net sink is a pin of an interconnection - * 2. The net source is a pin of an interconnection while the net sink a pb_graph_pin - * The type is enabled by an argument pin2pin_interc_type - *******************************************************************/ -static -void add_module_pb_graph_pin2pin_net(ModuleManager& module_manager, - const ModuleId& pb_module, - const ModuleId& interc_module, - const size_t& interc_instance, - const std::string& interc_port_name, - const size_t& interc_pin_id, - const std::string& module_name_prefix, - t_pb_graph_pin* pb_graph_pin, - const enum e_spice_pin2pin_interc_type& pin2pin_interc_type) { - - ModuleNetId pin2pin_net = module_manager.create_module_net(pb_module); - - /* Find port and pin ids for the module, which is the parent of pb_graph_pin */ - t_pb_type* pin_pb_type = pb_graph_pin->parent_node->pb_type; - /* Find the module contains the source pin */ - ModuleId pin_pb_type_module = module_manager.find_module(generate_physical_block_module_name(module_name_prefix, pin_pb_type)); - VTR_ASSERT(true == module_manager.valid_module_id(pin_pb_type_module)); - size_t pin_pb_type_instance = 0; /* Deposite the instance with a zero, which is the default value is the source module is actually pb_module itself */ - if (pin_pb_type_module != pb_module) { - pin_pb_type_instance = pb_graph_pin->parent_node->placement_index; - /* Ensure this is an valid instance */ - VTR_ASSERT(pin_pb_type_instance < module_manager.num_instance(pb_module, pin_pb_type_module)); - } - ModulePortId pin_module_port_id = module_manager.find_module_port(pin_pb_type_module, generate_pb_type_port_name(pb_graph_pin->port)); - VTR_ASSERT(true == module_manager.valid_module_port_id(pin_pb_type_module, pin_module_port_id)); - size_t pin_module_pin_id = pb_graph_pin->pin_number; - /* Ensure this is an valid pin index */ - VTR_ASSERT(pin_module_pin_id < module_manager.module_port(pin_pb_type_module, pin_module_port_id).get_width()); - - /* Find port and pin ids for the interconnection module */ - ModulePortId interc_port_id = module_manager.find_module_port(interc_module, interc_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(interc_module, interc_port_id)); - /* Ensure this is an valid pin index */ - VTR_ASSERT(interc_pin_id < module_manager.module_port(interc_module, interc_port_id).get_width()); - - /* Add net sources and sinks: - * For input-to-input connection, net_source is pin_graph_pin, while net_sink is interc pin - * For output-to-output connection, net_source is interc pin, while net_sink is pin_graph pin - */ - switch (pin2pin_interc_type) { - case INPUT2INPUT_INTERC: - module_manager.add_module_net_source(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id); - module_manager.add_module_net_sink(pb_module, pin2pin_net, interc_module, interc_instance, interc_port_id, interc_pin_id); - break; - case OUTPUT2OUTPUT_INTERC: - module_manager.add_module_net_source(pb_module, pin2pin_net, interc_module, interc_instance, interc_port_id, interc_pin_id); - module_manager.add_module_net_sink(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid pin-to-pin interconnection type!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * src_pb_graph_node.[in|out]_pins -----------------> des_pb_graph_node.[in|out]pins - * /|\ - * | - * input_pins, edges, output_pins - * - * This function does the following task: - * 1. identify pin interconnection type, - * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) - * 3. Add mux/direct connection as a child module to pb_module - * 4. Add nets related to the mux/direction - *******************************************************************/ -static -void add_module_pb_graph_pin_interc(ModuleManager& module_manager, - const ModuleId& pb_module, - std::vector& memory_modules, - std::vector& memory_instances, - const CircuitLibrary& circuit_lib, - const std::string& module_name_prefix, - t_pb_graph_pin* des_pb_graph_pin, - t_mode* physical_mode) { - /* Find the number of fan-in and detailed interconnection information - * related to the destination pb_graph_pin - */ - int fan_in = 0; - t_interconnect* cur_interc = NULL; - find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, physical_mode, &cur_interc, &fan_in); - - /* If no interconnection is needed, we can return early */ - if ((NULL == cur_interc) || (0 == fan_in)) { - return; - } - - /* Initialize the interconnection type that will be physically implemented in module */ - enum e_interconnect interc_type = determine_actual_pb_interc_type(cur_interc, fan_in); - - /* Find input ports of the wire module */ - std::vector interc_model_inputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_INPUT, true); /* the last argument to guarantee that we ignore any global inputs */ - /* Find output ports of the wire module */ - std::vector interc_model_outputs = circuit_lib.model_ports_by_type(cur_interc->circuit_model, SPICE_MODEL_PORT_OUTPUT, true); /* the last argument to guarantee that we ignore any global ports */ - - /* Ensure that we have only 1 input port and 1 output port, this is valid for both wire and MUX */ - VTR_ASSERT(1 == interc_model_inputs.size()); - VTR_ASSERT(1 == interc_model_outputs.size()); - - /* Branch on the type of physical implementation, - * We add instances of programmable interconnection - */ - switch (interc_type) { - case DIRECT_INTERC: { - /* Ensure direct interc has only one fan-in */ - VTR_ASSERT(1 == fan_in); - - /* For more than one mode defined, the direct interc has more than one input_edge , - * We need to find which edge is connected the pin we want - */ - int iedge = 0; - for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - if (cur_interc == des_pb_graph_pin->input_edges[iedge]->interconnect) { - break; - } - } - t_pb_graph_pin* src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; - - /* Ensure that circuit model is a wire */ - VTR_ASSERT(SPICE_MODEL_WIRE == circuit_lib.model_type(cur_interc->circuit_model)); - /* Find the wire module in the module manager */ - ModuleId wire_module = module_manager.find_module(circuit_lib.model_name(cur_interc->circuit_model)); - VTR_ASSERT(true == module_manager.valid_module_id(wire_module)); - /* Get the instance id and add an instance of wire */ - size_t wire_instance = module_manager.num_instance(pb_module, wire_module); - module_manager.add_child_module(pb_module, wire_module); - - /* Ensure input and output ports of the wire model has only 1 pin respectively */ - VTR_ASSERT(1 == circuit_lib.port_size(interc_model_inputs[0])); - VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0])); - - /* Add nets to connect the wires to ports of pb_module */ - /* First net is to connect input of src_pb_graph_node to input of the wire module */ - add_module_pb_graph_pin2pin_net(module_manager, pb_module, - wire_module, wire_instance, - circuit_lib.port_prefix(interc_model_inputs[0]), - 0, /* wire input port has only 1 pin */ - module_name_prefix, - src_pb_graph_pin, - INPUT2INPUT_INTERC); - - /* Second net is to connect output of the wire module to output of des_pb_graph_pin */ - add_module_pb_graph_pin2pin_net(module_manager, pb_module, - wire_module, wire_instance, - circuit_lib.port_prefix(interc_model_outputs[0]), - 0, /* wire output port has only 1 pin */ - module_name_prefix, - des_pb_graph_pin, - OUTPUT2OUTPUT_INTERC); - break; - } - case COMPLETE_INTERC: - case MUX_INTERC: { - /* Check: MUX should have at least 2 fan_in */ - VTR_ASSERT((2 == fan_in)||(2 < fan_in)); - /* Ensure that circuit model is a MUX */ - VTR_ASSERT(SPICE_MODEL_MUX == circuit_lib.model_type(cur_interc->circuit_model)); - /* Find the wire module in the module manager */ - ModuleId mux_module = module_manager.find_module(generate_mux_subckt_name(circuit_lib, cur_interc->circuit_model, fan_in, std::string())); - VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); - - /* Instanciate the MUX */ - size_t mux_instance = module_manager.num_instance(pb_module, mux_module); - module_manager.add_child_module(pb_module, mux_module); - /* Give an instance name: this name should be consistent with the block name given in SDC generator, - * If you want to bind the SDC generation to modules - */ - std::string mux_instance_name = generate_pb_mux_instance_name(GRID_MUX_INSTANCE_PREFIX, des_pb_graph_pin, std::string("")); - module_manager.set_child_instance_name(pb_module, mux_module, mux_instance, mux_instance_name); - - /* Instanciate a memory module for the MUX */ - std::string mux_mem_module_name = generate_mux_subckt_name(circuit_lib, - cur_interc->circuit_model, - fan_in, - std::string(MEMORY_MODULE_POSTFIX)); - ModuleId mux_mem_module = module_manager.find_module(mux_mem_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(mux_mem_module)); - size_t mux_mem_instance = module_manager.num_instance(pb_module, mux_mem_module); - module_manager.add_child_module(pb_module, mux_mem_module); - /* Give an instance name: this name should be consistent with the block name given in bitstream manager, - * If you want to bind the bitstream generation to modules - */ - std::string mux_mem_instance_name = generate_pb_memory_instance_name(GRID_MEM_INSTANCE_PREFIX, des_pb_graph_pin, std::string("")); - module_manager.set_child_instance_name(pb_module, mux_mem_module, mux_mem_instance, mux_mem_instance_name); - /* Add this MUX as a configurable child to the pb_module */ - module_manager.add_configurable_child(pb_module, mux_mem_module, mux_mem_instance); - - /* Add nets to connect SRAM ports of the MUX to the SRAM port of memory module */ - add_module_nets_between_logic_and_memory_sram_bus(module_manager, pb_module, - mux_module, mux_instance, - mux_mem_module, mux_mem_instance, - circuit_lib, cur_interc->circuit_model); - - /* Update memory modules and memory instance list */ - memory_modules.push_back(mux_mem_module); - memory_instances.push_back(mux_mem_instance); - - /* Ensure output port of the MUX model has only 1 pin, - * while the input port size is dependent on the architecture conext, - * no constaints on the circuit model definition - */ - VTR_ASSERT(1 == circuit_lib.port_size(interc_model_outputs[0])); - - /* Create nets to wire between the MUX and PB module */ - /* Add a net to wire the inputs of the multiplexer to its source pb_graph_pin inside pb_module - * Here is a tricky part. - * Not every input edges from the destination pb_graph_pin is used in the physical_model of pb_type - * So, we will skip these input edges when building nets - */ - int mux_input_pin_id = 0; - for (int iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - if (physical_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { - continue; - } - /* Ensure that the input edge has only 1 input pin! */ - check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); - t_pb_graph_pin* src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; - /* Add a net, set its source and sink */ - add_module_pb_graph_pin2pin_net(module_manager, pb_module, - mux_module, mux_instance, - circuit_lib.port_prefix(interc_model_inputs[0]), - mux_input_pin_id, - module_name_prefix, - src_pb_graph_pin, - INPUT2INPUT_INTERC); - mux_input_pin_id++; - } - /* Ensure all the fan_in has been covered */ - VTR_ASSERT(mux_input_pin_id == fan_in); - - /* Add a net to wire the output of the multiplexer to des_pb_graph_pin */ - add_module_pb_graph_pin2pin_net(module_manager, pb_module, - mux_module, mux_instance, - circuit_lib.port_prefix(interc_model_outputs[0]), - 0, /* MUX should have only 1 pin in its output port */ - module_name_prefix, - des_pb_graph_pin, - OUTPUT2OUTPUT_INTERC); - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid interconnection type for %s [at Architecture XML LINE%d]!\n", - __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); - exit(1); - } -} - -/******************************************************************** - * Add modules and nets for programmable/non-programmable interconnections - * which end to a port of pb_module - * This function will add the following elements to a module - * 1. Instances of direct connections - * 2. Instances of programmable routing multiplexers - * 3. nets to connect direct connections/multiplexer - * - * +-----------------------------------------+ - * | - * | +--------------+ +------------+ - * |--->| |--->| | - * |... | Multiplexers |... | | - * |--->| |--->| | - * | +--------------+ | des_pb_ | - * | | graph_node | - * | +--------------+ | | - * |--->| |--->| | - * | ...| Direct |... | | - * |--->| Connections |--->| | - * | +--------------+ +------------+ - * | - * +----------------------------------------+ - - * - * Note: this function should be run after ALL the child pb_modules - * have been added to the pb_module and ALL the ports defined - * in pb_type have been added to the pb_module!!! - * - ********************************************************************/ -static -void add_module_pb_graph_port_interc(ModuleManager& module_manager, - const ModuleId& pb_module, - std::vector& memory_modules, - std::vector& memory_instances, - const CircuitLibrary& circuit_lib, - t_pb_graph_node* des_pb_graph_node, - const std::string& module_name_prefix, - const e_spice_pb_port_type& pb_port_type, - t_mode* physical_mode) { - switch (pb_port_type) { - case SPICE_PB_PORT_INPUT: { - for (int iport = 0; iport < des_pb_graph_node->num_input_ports; ++iport) { - for (int ipin = 0; ipin < des_pb_graph_node->num_input_pins[iport]; ++ipin) { - /* Get the selected edge of current pin*/ - add_module_pb_graph_pin_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, - module_name_prefix, - &(des_pb_graph_node->input_pins[iport][ipin]), - physical_mode); - } - } - break; - } - case SPICE_PB_PORT_OUTPUT: { - for (int iport = 0; iport < des_pb_graph_node->num_output_ports; ++iport) { - for (int ipin = 0; ipin < des_pb_graph_node->num_output_pins[iport]; ++ipin) { - add_module_pb_graph_pin_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, - module_name_prefix, - &(des_pb_graph_node->output_pins[iport][ipin]), - physical_mode); - } - } - break; - } - case SPICE_PB_PORT_CLOCK: { - for (int iport = 0; iport < des_pb_graph_node->num_clock_ports; ++iport) { - for (int ipin = 0; ipin < des_pb_graph_node->num_clock_pins[iport]; ++ipin) { - add_module_pb_graph_pin_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, - module_name_prefix, - &(des_pb_graph_node->clock_pins[iport][ipin]), - physical_mode); - } - } - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid pb port type!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * TODO: - * Add modules and nets for programmable/non-programmable interconnections - * inside a module of pb_type - * This function will add the following elements to a module - * 1. Instances of direct connections - * 2. Instances of programmable routing multiplexers - * 3. nets to connect direct connections/multiplexer - * - * Pb_module - * +--------------------------------------------------------------+ - * | | - * | +--------------+ +------------+ +--------------+ | - * |--->| |--->| |--->| |--->| - * |... | Multiplexers |... | |... | Multiplexers |... | - * |--->| |--->| |--->| |--->| - * | +--------------+ | Child | +--------------+ | - * | | Pb_modules | | - * | +--------------+ | | +--------------+ | - * |--->| |--->| |--->| |--->| - * | ...| Direct |... | |... | Direct |... | - * |--->| Connections |--->| |--->| Connections |--->| - * | +--------------+ +------------+ +--------------+ | - * | | - * +--------------------------------------------------------------+ - * - * Note: this function should be run after ALL the child pb_modules - * have been added to the pb_module and ALL the ports defined - * in pb_type have been added to the pb_module!!! - * - ********************************************************************/ -static -void add_module_pb_graph_interc(ModuleManager& module_manager, - const ModuleId& pb_module, - std::vector& memory_modules, - std::vector& memory_instances, - const CircuitLibrary& circuit_lib, - t_pb_graph_node* physical_pb_graph_node, - const std::string& module_name_prefix, - const int& physical_mode_index) { - /* Check cur_pb_graph_node*/ - if (NULL == physical_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid cur_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Assign physical mode */ - t_mode* physical_mode = &(physical_pb_graph_node->pb_type->modes[physical_mode_index]); - - /* We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins - * /|\ - * | - * input_pins, edges, output_pins - */ - add_module_pb_graph_port_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, - physical_pb_graph_node, - module_name_prefix, - SPICE_PB_PORT_OUTPUT, - physical_mode); - - /* We check input_pins of child_pb_graph_node and its the input_edges - * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node - * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins - * /|\ - * | - * input_pins, edges, output_pins - */ - for (int child = 0; child < physical_pb_graph_node->pb_type->modes[physical_mode_index].num_pb_type_children; ++child) { - for (int inst = 0; inst < physical_pb_graph_node->pb_type->modes[physical_mode_index].pb_type_children[child].num_pb; ++inst) { - t_pb_graph_node* child_pb_graph_node = &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][child][inst]); - /* For each child_pb_graph_node input pins*/ - add_module_pb_graph_port_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, - child_pb_graph_node, - module_name_prefix, - SPICE_PB_PORT_INPUT, - physical_mode); - - /* For each child_pb_graph_node clock pins*/ - add_module_pb_graph_port_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, - child_pb_graph_node, - module_name_prefix, - SPICE_PB_PORT_CLOCK, - physical_mode); - } - } -} - -/******************************************************************** - * Print Verilog modules of physical blocks inside a grid (CLB, I/O. etc.) - * This function will traverse the graph of complex logic block (t_pb_graph_node) - * in a recursive way, using a Depth First Search (DFS) algorithm. - * As such, primitive physical blocks (LUTs, FFs, etc.), leaf node of the pb_graph - * will be printed out first, while the top-level will be printed out in the last - * - * Note: this function will print a unique Verilog module for each type of - * t_pb_graph_node, i.e., t_pb_type, in the graph, in order to enable highly - * hierarchical Verilog organization as well as simplify the Verilog file sizes. - * - * Note: DFS is the right way. Do NOT use BFS. - * DFS can guarantee that all the sub-modules can be registered properly - * to its parent in module manager - *******************************************************************/ -static -void rec_build_physical_block_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - t_pb_graph_node* physical_pb_graph_node, - const e_side& io_side) { - /* Check cur_pb_graph_node*/ - if (NULL == physical_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid cur_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Get the pb_type definition related to the node */ - t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; - - /* Find the mode that physical implementation of a pb_type */ - int physical_mode_index = find_pb_type_physical_mode_index((*physical_pb_type)); - - /* For non-leaf node in the pb_type graph: - * Recursively Depth-First Generate all the child pb_type at the level - */ - if (FALSE == is_primitive_pb_type(physical_pb_type)) { - for (int ipb = 0; ipb < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ipb) { - /* Go recursive to visit the children */ - rec_build_physical_block_modules(module_manager, circuit_lib, mux_lib, - sram_orgz_type, sram_model, - &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][0]), - io_side); - } - } - - /* For leaf node, a primitive Verilog module will be generated */ - if (TRUE == is_primitive_pb_type(physical_pb_type)) { - build_primitive_block_module(module_manager, circuit_lib, - sram_orgz_type, sram_model, - physical_pb_graph_node, - io_side); - /* Finish for primitive node, return */ - return; - } - - /* Generate the name of the Verilog module for this pb_type */ - std::string pb_module_name_prefix = generate_grid_block_prefix(std::string(GRID_MODULE_NAME_PREFIX), io_side); - std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, physical_pb_type); - - /* Register the Verilog module in module manager */ - ModuleId pb_module = module_manager.add_module(pb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); - - /* Add ports to the Verilog module */ - add_pb_type_ports_to_module_manager(module_manager, pb_module, physical_pb_type); - - /* Vectors to record all the memory modules have been added - * They are used to add module nets of configuration bus - */ - std::vector memory_modules; - std::vector memory_instances; - - /* Add all the child Verilog modules as instances */ - for (int ichild = 0; ichild < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ichild) { - /* Get the name and module id for this child pb_type */ - std::string child_pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild])); - ModuleId child_pb_module = module_manager.find_module(child_pb_module_name); - /* We must have one valid id! */ - VTR_ASSERT(true == module_manager.valid_module_id(child_pb_module)); - - /* Each child may exist multiple times in the hierarchy*/ - for (int inst = 0; inst < physical_pb_type->modes[physical_mode_index].pb_type_children[ichild].num_pb; ++inst) { - size_t child_instance_id = module_manager.num_instance(pb_module, child_pb_module); - /* Ensure the instance of this child module is the same as placement index, - * This check is necessary because placement_index is used to identify instance id for children - * when adding local interconnection for this pb_type - */ - VTR_ASSERT(child_instance_id == (size_t)physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ichild][inst].placement_index); - - /* Add the memory module as a child of primitive module */ - module_manager.add_child_module(pb_module, child_pb_module); - - /* Set an instance name to bind to a block in bitstream generation and SDC generation! */ - std::string child_pb_instance_name = generate_physical_block_instance_name(pb_module_name_prefix, &(physical_pb_type->modes[physical_mode_index].pb_type_children[ichild]), inst); - module_manager.set_child_instance_name(pb_module, child_pb_module, child_instance_id, child_pb_instance_name); - - /* Identify if this sub module includes configuration bits, - * we will update the memory module and instance list - */ - if (0 < find_module_num_config_bits(module_manager, child_pb_module, - circuit_lib, sram_model, - sram_orgz_type)) { - module_manager.add_configurable_child(pb_module, child_pb_module, child_instance_id); - } - } - } - - /* Add modules and nets for programmable/non-programmable interconnections - * inside the Verilog module - */ - add_module_pb_graph_interc(module_manager, pb_module, - memory_modules, memory_instances, - circuit_lib, physical_pb_graph_node, - pb_module_name_prefix, - physical_mode_index); - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, pb_module); - - /* Count GPIO ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - add_module_gpio_ports_from_child_modules(module_manager, pb_module); - - /* Count shared SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, pb_module); - if (0 < module_num_shared_config_bits) { - add_reserved_sram_ports_to_module_manager(module_manager, pb_module, module_num_shared_config_bits); - } - - /* Count SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, pb_module, circuit_lib, sram_model, sram_orgz_type); - if (0 < module_num_config_bits) { - add_sram_ports_to_module_manager(module_manager, pb_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits); - } - - /* Add module nets to connect memory cells inside - * This is a one-shot addition that covers all the memory modules in this pb module! - */ - if (false == memory_modules.empty()) { - add_module_nets_memory_config_bus(module_manager, pb_module, - sram_orgz_type, circuit_lib.design_tech_type(sram_model)); - } -} - -/***************************************************************************** - * This function will create a Verilog file and print out a Verilog netlist - * for a type of physical block - * - * For IO blocks: - * The param 'border_side' is required, which is specify which side of fabric - * the I/O block locates at. - *****************************************************************************/ -static -void build_grid_module(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - t_type_ptr phy_block_type, - const e_side& border_side, - const bool& duplicate_grid_pin) { - /* Check code: if this is an IO block, the border side MUST be valid */ - if (IO_TYPE == phy_block_type) { - VTR_ASSERT(NUM_SIDES != border_side); - } - - /* Build modules for all the pb_types/pb_graph_nodes - * use a Depth-First Search Algorithm to print the sub-modules - * Note: DFS is the right way. Do NOT use BFS. - * DFS can guarantee that all the sub-modules can be registered properly - * to its parent in module manager - */ - /* Build modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */ - rec_build_physical_block_modules(module_manager, circuit_lib, mux_lib, - sram_orgz_type, sram_model, - phy_block_type->pb_graph_head, - border_side); - - /* Create a Verilog Module for the top-level physical block, and add to module manager */ - std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_MODULE_NAME_PREFIX), std::string(phy_block_type->name), IO_TYPE == phy_block_type, border_side); - ModuleId grid_module = module_manager.add_module(grid_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); - - /* Generate the name of the Verilog module for this pb_type */ - std::string pb_module_name_prefix(GRID_MODULE_NAME_PREFIX); - std::string pb_module_name = generate_grid_physical_block_module_name(pb_module_name_prefix, phy_block_type->pb_graph_head->pb_type, border_side); - ModuleId pb_module = module_manager.find_module(pb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); - - /* Add all the sub modules */ - for (int iz = 0; iz < phy_block_type->capacity; ++iz) { - size_t pb_instance_id = module_manager.num_instance(grid_module, pb_module); - module_manager.add_child_module(grid_module, pb_module); - - /* Give the child module with a unique instance name */ - std::string instance_name = generate_grid_physical_block_instance_name(pb_module_name_prefix, phy_block_type->pb_graph_head->pb_type, border_side, iz); - /* Set an instance name to bind to a block in bitstream generation */ - module_manager.set_child_instance_name(grid_module, pb_module, pb_instance_id, instance_name); - - /* Identify if this sub module includes configuration bits, - * we will update the memory module and instance list - */ - if (0 < find_module_num_config_bits(module_manager, pb_module, - circuit_lib, sram_model, - sram_orgz_type)) { - module_manager.add_configurable_child(grid_module, pb_module, pb_instance_id); - } - } - - /* Add grid ports(pins) to the module */ - if (false == duplicate_grid_pin) { - /* Default way to add these ports by following the definition in pb_types */ - add_grid_module_pb_type_ports(module_manager, grid_module, - phy_block_type, border_side); - /* Add module nets to connect the pb_type ports to sub modules */ - for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) { - add_grid_module_nets_connect_pb_type_ports(module_manager, grid_module, - pb_module, child_instance, - phy_block_type, border_side); - } - } else { - VTR_ASSERT_SAFE(true == duplicate_grid_pin); - /* TODO: Add these ports with duplication */ - add_grid_module_duplicated_pb_type_ports(module_manager, grid_module, - phy_block_type, border_side); - - /* TODO: Add module nets to connect the duplicated pb_type ports to sub modules */ - for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) { - add_grid_module_nets_connect_duplicated_pb_type_ports(module_manager, grid_module, - pb_module, child_instance, - phy_block_type, border_side); - } - } - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, grid_module); - - /* Count GPIO ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - add_module_gpio_ports_from_child_modules(module_manager, grid_module); - - /* Count shared SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, grid_module); - if (0 < module_num_shared_config_bits) { - add_reserved_sram_ports_to_module_manager(module_manager, grid_module, module_num_shared_config_bits); - } - - /* Count SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type); - if (0 < module_num_config_bits) { - add_sram_ports_to_module_manager(module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits); - } - - /* Add module nets to connect memory cells inside - * This is a one-shot addition that covers all the memory modules in this pb module! - */ - if (0 < module_manager.configurable_children(grid_module).size()) { - add_module_nets_memory_config_bus(module_manager, grid_module, - sram_orgz_type, circuit_lib.design_tech_type(sram_model)); - } -} - -/***************************************************************************** - * Create logic block modules in a compact way: - * 1. Only one module for each I/O on each border side (IO_TYPE) - * 2. Only one module for each CLB (FILL_TYPE) - * 3. Only one module for each heterogeneous block - ****************************************************************************/ -void build_grid_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const bool& duplicate_grid_pin) { - /* Start time count */ - clock_t t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, - "Building grid modules..."); - - /* Enumerate the types, dump one Verilog module for each */ - for (int itype = 0; itype < num_types; itype++) { - if (EMPTY_TYPE == &type_descriptors[itype]) { - /* Bypass empty type or NULL */ - continue; - } else if (IO_TYPE == &type_descriptors[itype]) { - /* Special for I/O block, generate one module for each border side */ - for (int iside = 0; iside < NUM_SIDES; iside++) { - Side side_manager(iside); - build_grid_module(module_manager, mux_lib, circuit_lib, - sram_orgz_type, sram_model, - &type_descriptors[itype], - side_manager.get_side(), - duplicate_grid_pin); - } - continue; - } else if (FILL_TYPE == &type_descriptors[itype]) { - /* For CLB */ - build_grid_module(module_manager, mux_lib, circuit_lib, - sram_orgz_type, sram_model, - &type_descriptors[itype], - NUM_SIDES, - duplicate_grid_pin); - continue; - } else { - /* For heterogenenous blocks */ - build_grid_module(module_manager, mux_lib, circuit_lib, - sram_orgz_type, sram_model, - &type_descriptors[itype], - NUM_SIDES, - duplicate_grid_pin); - } - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %.2g seconds\n", - run_time_sec); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.h deleted file mode 100644 index b7c6d2ac5..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.h +++ /dev/null @@ -1,19 +0,0 @@ -/******************************************************************** - * Header file for build_grid_modules.cpp - *******************************************************************/ -#ifndef BUILD_GRID_MODULES_H -#define BUILD_GRID_MODULES_H - -/* Only include headers related to the data structures used in the following function declaration */ -#include "vpr_types.h" -#include "module_manager.h" -#include "mux_library.h" - -void build_grid_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const bool& duplicate_grid_pin); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp deleted file mode 100644 index 3122cf178..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp +++ /dev/null @@ -1,416 +0,0 @@ -/******************************************************************** - * This file include functions that create modules for - * the Look-Up Tables (LUTs) - ********************************************************************/ -#include -#include -#include - -#include "vtr_assert.h" -#include "util.h" -#include "spice_types.h" - -#include "fpga_x2p_naming.h" -#include "circuit_library_utils.h" -#include "module_manager.h" -#include "module_manager_utils.h" - -#include "build_module_graph_utils.h" -#include "build_lut_modules.h" - -/******************************************************************** - * Build a module for a LUT circuit model - * This function supports both single-output and fracturable LUTs - * The module will be organized in a connected graph of the following instances: - * 1. Multiplexer used inside LUT - * 2. Input buffers - * 3. Input inverters - * 4. Output buffers. - * 6. AND/OR gates to tri-state LUT inputs - ********************************************************************/ -static -void build_lut_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& lut_model) { - /* Get the global ports required by LUT - * Note that this function will only add global ports from LUT circuit model definition itself - * We should NOT go recursively here. - * The global ports of sub module will be handled by another function !!! - * add_module_global_ports_from_child_modules(module_manager, lut_module); - */ - std::vector lut_global_ports = circuit_lib.model_global_ports_by_type(lut_model, SPICE_MODEL_PORT_INPUT, false, true); - /* Get the input ports from the mux */ - std::vector lut_input_ports = circuit_lib.model_ports_by_type(lut_model, SPICE_MODEL_PORT_INPUT, true); - /* Get the output ports from the mux */ - std::vector lut_output_ports = circuit_lib.model_ports_by_type(lut_model, SPICE_MODEL_PORT_OUTPUT, true); - - /* Classify SRAM ports into two categories: regular (not for mode select) and mode-select */ - std::vector lut_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, lut_model); - std::vector lut_mode_select_sram_ports = find_circuit_mode_select_sram_ports(circuit_lib, lut_model); - - /*********************************************** - * Model Port Sanity Check - ***********************************************/ - /* Make sure that the number of ports and sizes of ports are what we want */ - if (false == circuit_lib.is_lut_fracturable(lut_model)) { - /* Single-output LUTs: - * We should have only 1 input port, 1 output port and 1 SRAM port - */ - VTR_ASSERT (1 == lut_input_ports.size()); - VTR_ASSERT (1 == lut_output_ports.size()); - VTR_ASSERT (1 == lut_regular_sram_ports.size()); - VTR_ASSERT (0 == lut_mode_select_sram_ports.size()); - } else { - VTR_ASSERT (true == circuit_lib.is_lut_fracturable(lut_model)); - /* Fracturable LUT: - * We should have only 1 input port, a few output ports (fracturable outputs) - * and two SRAM ports - */ - VTR_ASSERT (1 == lut_input_ports.size()); - VTR_ASSERT (1 <= lut_output_ports.size()); - VTR_ASSERT (1 == lut_regular_sram_ports.size()); - VTR_ASSERT (1 == lut_mode_select_sram_ports.size()); - } - - /*********************************************** - * Module Port addition - ***********************************************/ - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId lut_module = module_manager.add_module(circuit_lib.model_name(lut_model)); - VTR_ASSERT(true == module_manager.valid_module_id(lut_module)); - /* Add module ports */ - /* Add each global port */ - for (const auto& port : lut_global_ports) { - /* Configure each global port */ - BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - module_manager.add_port(lut_module, global_port, ModuleManager::MODULE_GLOBAL_PORT); - } - /* Add each input port */ - for (const auto& port : lut_input_ports) { - BasicPort input_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - module_manager.add_port(lut_module, input_port, ModuleManager::MODULE_INPUT_PORT); - /* Set the port to be wire-connection */ - module_manager.set_port_is_wire(lut_module, input_port.get_name(), true); - } - /* Add each output port */ - for (const auto& port : lut_output_ports) { - BasicPort output_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - module_manager.add_port(lut_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); - /* Set the port to be wire-connection */ - module_manager.set_port_is_wire(lut_module, output_port.get_name(), true); - } - /* Add each regular (not mode select) SRAM port */ - for (const auto& port : lut_regular_sram_ports) { - BasicPort mem_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), circuit_lib.port_size(port)); - module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); - } - - /* Add each mode-select SRAM port */ - for (const auto& port : lut_mode_select_sram_ports) { - BasicPort mem_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - module_manager.add_port(lut_module, mem_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), circuit_lib.port_size(port)); - module_manager.add_port(lut_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); - } - - /*********************************************** - * Child module addition: Model-select gates - ***********************************************/ - /* Module nets after the mode-selection circuit, this could include LUT inputs */ - std::vector mode_selected_nets; - /* Instanciate mode selecting circuit: AND/OR gate - * By following the tri-state map of LUT input port - * The wiring of input ports will be organized as follows - * - * LUT input - * | - * v - * +----------+ - * | mode | - * | selector | - * +----------+ - * | mode_selected_nets - * v - * +-----------------+------------+ - * | | - * v v - * +----------+ +---------+ - * | Inverter | | Buffer | - * +----------+ +---------+ - * | inverter_output_net | buffered_output_net - * v v - * +--------------------------------------+ - * | LUT Multiplexing Structure | - * +--------------------------------------+ - */ - /* Get the tri-state port map for the input ports*/ - std::string tri_state_map = circuit_lib.port_tri_state_map(lut_input_ports[0]); - size_t mode_select_port_lsb = 0; - for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) { - ModulePortId lut_module_input_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_prefix(lut_input_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(lut_module, lut_module_input_port_id)); - - /* Create a module net for the connection */ - ModuleNetId net = module_manager.create_module_net(lut_module); - /* Set the source of the net to an lut input port */ - module_manager.add_module_net_source(lut_module, net, lut_module, 0, lut_module_input_port_id, pin); - - /* For an empty tri-state map or a '-' sign in tri-state map, we can short-wire mode select_output_ports */ - if (tri_state_map.empty() || ('-' == tri_state_map[pin]) ) { - /* Update the output nets of the mode-select layer */ - mode_selected_nets.push_back(net); - continue; /* Finish here */ - } - - e_spice_model_gate_type required_gate_type = NUM_SPICE_MODEL_GATE_TYPES; - /* Reach here, it means that we need a circuit for mode selection */ - if ('0' == tri_state_map[pin]) { - /* We need a 2-input AND gate, in order to tri-state the input - * Detailed circuit is as follow: - * +---------+ - * SRAM --->| 2-input |----> mode_select_output_port - * LUT input--->| AND | - * +---------+ - * When SRAM is set to logic 0, the LUT input is tri-stated - * When SRAM is set to logic 1, the LUT input is effective to the downstream circuits - */ - required_gate_type = SPICE_MODEL_GATE_AND; - } else { - VTR_ASSERT ('1' == tri_state_map[pin]); - /* We need a 2-input OR gate, in order to tri-state the input - * Detailed circuit is as follow: - * +---------+ - * SRAM --->| 2-input |----> mode_select_output_port - * LUT input--->| OR | - * +---------+ - * When SRAM is set to logic 1, the LUT input is tri-stated - * When SRAM is set to logic 0, the LUT input is effective to the downstream circuits - */ - required_gate_type = SPICE_MODEL_GATE_OR; - } - /* Get the circuit model of the gate */ - CircuitModelId gate_model = circuit_lib.port_tri_state_model(lut_input_ports[0]); - /* Check this is the gate we want ! */ - VTR_ASSERT (required_gate_type == circuit_lib.gate_type(gate_model)); - - /* Prepare for the gate instanciation */ - /* Get the input ports from the gate */ - std::vector gate_input_ports = circuit_lib.model_ports_by_type(gate_model, SPICE_MODEL_PORT_INPUT, true); - /* Get the output ports from the gate */ - std::vector gate_output_ports = circuit_lib.model_ports_by_type(gate_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Check the port sizes and width: - * we should have only 2 input ports, each of which has a size of 1 - * we should have only 1 output port, each of which has a size of 1 - */ - VTR_ASSERT (2 == gate_input_ports.size()); - VTR_ASSERT (1 == gate_output_ports.size()); - /* Find the module id of gate_model in the module manager */ - ModuleId gate_module = module_manager.find_module(circuit_lib.model_name(gate_model)); - /* We must have a valid id */ - VTR_ASSERT (true == module_manager.valid_module_id(gate_module)); - size_t gate_instance = module_manager.num_instance(lut_module, gate_module); - module_manager.add_child_module(lut_module, gate_module); - - /* Create a port-to-port net connection: - * Input[0] of the gate is wired to a SRAM mode-select port - * Input[1] of the gate is wired to the input port of LUT - * Output[0] of the gate is wired to the mode_select_output_port - */ - /* Create a module net for the connection */ - ModuleNetId gate_sram_net = module_manager.create_module_net(lut_module); - - /* Find the module port id of the SRAM port of LUT module */ - ModulePortId lut_module_mode_select_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_prefix(lut_mode_select_sram_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(lut_module, lut_module_mode_select_port_id)); - /* Set the source of the net to an mode-select SRAM port of the LUT module */ - module_manager.add_module_net_source(lut_module, gate_sram_net, lut_module, 0, lut_module_mode_select_port_id, mode_select_port_lsb); - - /* Find the module port id of the SRAM port of LUT module */ - ModulePortId gate_module_input0_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_prefix(gate_input_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(gate_module, gate_module_input0_port_id)); - /* Set the sink of the net to an input[0] port of the gate module */ - VTR_ASSERT(1 == module_manager.module_port(gate_module, gate_module_input0_port_id).get_width()); - for (const size_t& gate_pin : module_manager.module_port(gate_module, gate_module_input0_port_id).pins()) { - module_manager.add_module_net_sink(lut_module, gate_sram_net, gate_module, gate_instance, gate_module_input0_port_id, gate_pin); - } - - /* Use the existing net to connect to the input[1] port of the gate module */ - ModulePortId gate_module_input1_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_prefix(gate_input_ports[1])); - VTR_ASSERT(true == module_manager.valid_module_port_id(gate_module, gate_module_input1_port_id)); - VTR_ASSERT(1 == module_manager.module_port(gate_module, gate_module_input1_port_id).get_width()); - for (const size_t& gate_pin : module_manager.module_port(gate_module, gate_module_input1_port_id).pins()) { - module_manager.add_module_net_sink(lut_module, net, gate_module, gate_instance, gate_module_input1_port_id, gate_pin); - } - - /* Create a module net for the output connection */ - ModuleNetId gate_output_net = module_manager.create_module_net(lut_module); - ModulePortId gate_module_output_port_id = module_manager.find_module_port(gate_module, circuit_lib.port_prefix(gate_output_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(gate_module, gate_module_output_port_id)); - BasicPort gate_module_output_port = module_manager.module_port(gate_module, gate_module_output_port_id); - VTR_ASSERT(1 == gate_module_output_port.get_width()); - module_manager.add_module_net_source(lut_module, gate_output_net, gate_module, gate_instance, gate_module_output_port_id, gate_module_output_port.get_lsb()); - - /* Update the output nets of the mode-select layer */ - mode_selected_nets.push_back(gate_output_net); - - /* update the lsb of mode select port size */ - mode_select_port_lsb++; - } - - /* Sanitity check */ - if ( true == circuit_lib.is_lut_fracturable(lut_model) ) { - if (mode_select_port_lsb != circuit_lib.port_size(lut_mode_select_sram_ports[0])) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d]) Circuit model LUT (name=%s) has a unmatched tri-state map (%s) implied by mode_port size(%d)!\n", - __FILE__, __LINE__, - circuit_lib.model_name(lut_model).c_str(), - tri_state_map.c_str(), - circuit_lib.port_size(lut_mode_select_sram_ports[0])); - exit(1); - } - } - - /*********************************************** - * Child module addition: Input inverters - ***********************************************/ - /* Find the circuit model of the input inverter */ - CircuitModelId input_inverter_model = circuit_lib.lut_input_inverter_model(lut_model); - VTR_ASSERT( CircuitModelId::INVALID() != input_inverter_model ); - - std::vector lut_mux_sram_inv_nets; - /* Now we need to add inverters by instanciating the modules */ - for (size_t pin = 0; pin < circuit_lib.port_size(lut_input_ports[0]); ++pin) { - ModuleNetId lut_mux_sram_inv_net = add_inverter_buffer_child_module_and_nets(module_manager, lut_module, - circuit_lib, input_inverter_model, - mode_selected_nets[pin]); - /* Update the net vector */ - lut_mux_sram_inv_nets.push_back(lut_mux_sram_inv_net); - } - - /*********************************************** - * Child module addition: Input buffers - ***********************************************/ - /* Add buffers to mode_select output ports */ - /* Find the circuit model of the input inverter */ - CircuitModelId input_buffer_model = circuit_lib.lut_input_buffer_model(lut_model); - VTR_ASSERT( CircuitModelId::INVALID() != input_buffer_model ); - - std::vector lut_mux_sram_nets; - /* Now we need to add inverters by instanciating the modules and add module nets */ - for (size_t pin = 0; pin < circuit_lib.port_size(lut_input_ports[0]); ++pin) { - ModuleNetId lut_mux_sram_net = add_inverter_buffer_child_module_and_nets(module_manager, lut_module, - circuit_lib, input_buffer_model, - mode_selected_nets[pin]); - /* Update the net vector */ - lut_mux_sram_nets.push_back(lut_mux_sram_net); - } - - /*********************************************** - * Child module addition: LUT MUX - ***********************************************/ - /* Find the name of LUT MUX: no need to provide a mux size, just give an invalid number (=-1) */ - std::string lut_mux_module_name = generate_mux_subckt_name(circuit_lib, lut_model, size_t(-1), std::string("")); - /* Find the module id of LUT MUX in the module manager */ - ModuleId lut_mux_module = module_manager.find_module(lut_mux_module_name); - /* We must have a valid id */ - VTR_ASSERT (ModuleId::INVALID() != lut_mux_module); - /* Instanciate a LUT MUX as child module */ - size_t lut_mux_instance = module_manager.num_instance(lut_module, lut_mux_module); - module_manager.add_child_module(lut_module, lut_mux_module); - - /* TODO: Build module nets to connect - * 1. SRAM ports of LUT MUX module to output ports of input buffer - * 2. Inverted SRAM ports of LUT MUX module to output ports of input inverters - * 3. Data input of LUT MUX module to SRAM port of LUT - * 4. Data output of LUT MUX module to output ports of LUT - */ - ModulePortId lut_mux_sram_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_prefix(lut_regular_sram_ports[0])); - BasicPort lut_mux_sram_port = module_manager.module_port(lut_mux_module, lut_mux_sram_port_id); - VTR_ASSERT(lut_mux_sram_port.get_width() == lut_mux_sram_nets.size()); - /* Wire the port to lut_mux_sram_net */ - for (const size_t& pin : lut_mux_sram_port.pins()) { - module_manager.add_module_net_sink(lut_module, lut_mux_sram_nets[pin], lut_mux_module, lut_mux_instance, lut_mux_sram_port_id, pin); - } - - ModulePortId lut_mux_sram_inv_port_id = module_manager.find_module_port(lut_mux_module, std::string(circuit_lib.port_prefix(lut_regular_sram_ports[0]) + "_inv")); - BasicPort lut_mux_sram_inv_port = module_manager.module_port(lut_mux_module, lut_mux_sram_inv_port_id); - VTR_ASSERT(lut_mux_sram_inv_port.get_width() == lut_mux_sram_inv_nets.size()); - /* Wire the port to lut_mux_sram_net */ - for (const size_t& pin : lut_mux_sram_inv_port.pins()) { - module_manager.add_module_net_sink(lut_module, lut_mux_sram_inv_nets[pin], lut_mux_module, lut_mux_instance, lut_mux_sram_inv_port_id, pin); - } - - /* lut_module - * +------------ - * | +------ - * sram -->|---->| (lut_mux_input_port) - * | ^ | LUT MUX - * | | | - * | - * net - */ - ModulePortId lut_sram_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_prefix(lut_regular_sram_ports[0])); - BasicPort lut_sram_port = module_manager.module_port(lut_module, lut_sram_port_id); - ModulePortId lut_mux_input_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_prefix(lut_input_ports[0])); - BasicPort lut_mux_input_port = module_manager.module_port(lut_mux_module, lut_mux_input_port_id); - VTR_ASSERT(lut_mux_input_port.get_width() == lut_sram_port.get_width()); - /* Wire the port to lut_mux_sram_net */ - for (size_t pin_id = 0; pin_id < lut_mux_input_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(lut_module); - module_manager.add_module_net_source(lut_module, net, lut_module, 0, lut_sram_port_id, lut_sram_port.pins()[pin_id]); - module_manager.add_module_net_sink(lut_module, net, lut_mux_module, lut_mux_instance, lut_mux_input_port_id, lut_mux_input_port.pins()[pin_id]); - } - - for (const auto& port : lut_output_ports) { - ModulePortId lut_output_port_id = module_manager.find_module_port(lut_module, circuit_lib.port_prefix(port)); - BasicPort lut_output_port = module_manager.module_port(lut_module, lut_output_port_id); - ModulePortId lut_mux_output_port_id = module_manager.find_module_port(lut_mux_module, circuit_lib.port_prefix(port)); - BasicPort lut_mux_output_port = module_manager.module_port(lut_mux_module, lut_mux_output_port_id); - VTR_ASSERT(lut_mux_output_port.get_width() == lut_output_port.get_width()); - /* Wire the port to lut_mux_sram_net */ - for (size_t pin_id = 0; pin_id < lut_output_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(lut_module); - module_manager.add_module_net_source(lut_module, net, lut_mux_module, lut_mux_instance, lut_mux_output_port_id, lut_mux_output_port.pins()[pin_id]); - module_manager.add_module_net_sink(lut_module, net, lut_module, 0, lut_output_port_id, lut_output_port.pins()[pin_id]); - } - } - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, lut_module); -} - -/******************************************************************** - * Print Verilog modules for the Look-Up Tables (LUTs) - * in the circuit library - ********************************************************************/ -void build_lut_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib) { - /* Start time count */ - clock_t t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, - "Building Look-Up Table (LUT) modules..."); - - /* Search for each LUT circuit model */ - for (const auto& lut_model : circuit_lib.models()) { - /* Bypas non-LUT modules */ - if (SPICE_MODEL_LUT != circuit_lib.model_type(lut_model)) { - continue; - } - build_lut_module(module_manager, circuit_lib, lut_model); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %.2g seconds\n", - run_time_sec); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.h deleted file mode 100644 index 68990d2cc..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.h +++ /dev/null @@ -1,13 +0,0 @@ -/******************************************************************** - * Header file for build_lut_modules.cpp - ********************************************************************/ -#ifndef BUILD_LUT_MODULES_H -#define BUILD_LUT_MODULES_H - -#include "circuit_library.h" -#include "module_manager.h" - -void build_lut_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp deleted file mode 100644 index a4a33bed2..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp +++ /dev/null @@ -1,731 +0,0 @@ -/********************************************************************* - * This file includes functions to generate Verilog submodules for - * the memories that are affiliated to multiplexers and other programmable - * circuit models, such as IOPADs, LUTs, etc. - ********************************************************************/ -#include -#include -#include - -#include "util.h" -#include "vtr_assert.h" - -/* Device-level header files */ -#include "mux_graph.h" -#include "module_manager.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "circuit_library_utils.h" -#include "module_manager_utils.h" -#include "mux_utils.h" - -/* FPGA-X2P context header files */ -#include "spice_types.h" -#include "fpga_x2p_reserved_words.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -/* FPGA-Verilog context header files */ -#include "verilog_global.h" -#include "build_memory_modules.h" - -/********************************************************************* - * Add module nets to connect an input port of a memory module to - * an input port of its child module - * Restriction: this function is really designed for memory modules - * 1. It assumes that input port name of child module is the same as memory module - * 2. It assumes exact pin-to-pin mapping: - * j-th pin of input port of the i-th child module is wired to the j + i*W -th - * pin of input port of the memory module, where W is the size of port - ********************************************************************/ -static -void add_module_input_nets_to_mem_modules(ModuleManager& module_manager, - const ModuleId& mem_module, - const CircuitLibrary& circuit_lib, - const std::vector& circuit_ports, - const ModuleId& child_module, - const size_t& child_index, - const size_t& child_instance) { - /* Wire inputs of parent module to inputs of child modules */ - for (const auto& port : circuit_ports) { - ModulePortId src_port_id = module_manager.find_module_port(mem_module, circuit_lib.port_prefix(port)); - ModulePortId sink_port_id = module_manager.find_module_port(child_module, circuit_lib.port_prefix(port)); - for (size_t pin_id = 0; pin_id < module_manager.module_port(mem_module, sink_port_id).pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(mem_module); - /* Source pin is shifted by the number of memories */ - size_t src_pin_id = child_index * circuit_lib.port_size(port) + module_manager.module_port(mem_module, src_port_id).pins()[pin_id]; - /* Source node of the input net is the input of memory module */ - module_manager.add_module_net_source(mem_module, net, mem_module, 0, src_port_id, src_pin_id); - /* Sink node of the input net is the input of sram module */ - size_t sink_pin_id = module_manager.module_port(child_module, sink_port_id).pins()[pin_id]; - module_manager.add_module_net_sink(mem_module, net, child_module, child_instance, sink_port_id, sink_pin_id); - } - } -} - -/********************************************************************* - * Add module nets to connect an output port of a memory module to - * an output port of its child module - * Restriction: this function is really designed for memory modules - * 1. It assumes that output port name of child module is the same as memory module - * 2. It assumes exact pin-to-pin mapping: - * j-th pin of output port of the i-th child module is wired to the j + i*W -th - * pin of output port of the memory module, where W is the size of port - ********************************************************************/ -static -void add_module_output_nets_to_mem_modules(ModuleManager& module_manager, - const ModuleId& mem_module, - const CircuitLibrary& circuit_lib, - const std::vector& circuit_ports, - const ModuleId& child_module, - const size_t& child_index, - const size_t& child_instance) { - /* Wire inputs of parent module to inputs of child modules */ - for (const auto& port : circuit_ports) { - ModulePortId src_port_id = module_manager.find_module_port(child_module, circuit_lib.port_prefix(port)); - ModulePortId sink_port_id = module_manager.find_module_port(mem_module, circuit_lib.port_prefix(port)); - for (size_t pin_id = 0; pin_id < module_manager.module_port(child_module, src_port_id).pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(mem_module); - /* Source pin is shifted by the number of memories */ - size_t src_pin_id = module_manager.module_port(child_module, src_port_id).pins()[pin_id]; - /* Source node of the input net is the input of memory module */ - module_manager.add_module_net_source(mem_module, net, child_module, child_instance, src_port_id, src_pin_id); - /* Sink node of the input net is the input of sram module */ - size_t sink_pin_id = child_index * circuit_lib.port_size(port) + module_manager.module_port(mem_module, sink_port_id).pins()[pin_id]; - module_manager.add_module_net_sink(mem_module, net, mem_module, 0, sink_port_id, sink_pin_id); - } - } -} - -/********************************************************************* - * Add module nets to connect an output port of a configuration-chain - * memory module to an output port of its child module - * Restriction: this function is really designed for memory modules - * 1. It assumes that output port name of child module is the same as memory module - * 2. It assumes exact pin-to-pin mapping: - * j-th pin of output port of the i-th child module is wired to the j + i*W -th - * pin of output port of the memory module, where W is the size of port - * 3. It assumes fixed port name for output ports - * - * We cache the module nets that have been created because they will be used later - ********************************************************************/ -static -std::vector add_module_output_nets_to_chain_mem_modules(ModuleManager& module_manager, - const ModuleId& mem_module, - const std::string& mem_module_output_name, - const CircuitLibrary& circuit_lib, - const CircuitPortId& circuit_port, - const ModuleId& child_module, - const size_t& child_index, - const size_t& child_instance) { - std::vector module_nets; - - /* Wire inputs of parent module to inputs of child modules */ - ModulePortId src_port_id = module_manager.find_module_port(child_module, circuit_lib.port_prefix(circuit_port)); - ModulePortId sink_port_id = module_manager.find_module_port(mem_module, mem_module_output_name); - for (size_t pin_id = 0; pin_id < module_manager.module_port(child_module, src_port_id).pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(mem_module); - /* Source pin is shifted by the number of memories */ - size_t src_pin_id = module_manager.module_port(child_module, src_port_id).pins()[pin_id]; - /* Source node of the input net is the input of memory module */ - module_manager.add_module_net_source(mem_module, net, child_module, child_instance, src_port_id, src_pin_id); - /* Sink node of the input net is the input of sram module */ - size_t sink_pin_id = child_index * circuit_lib.port_size(circuit_port) + module_manager.module_port(mem_module, sink_port_id).pins()[pin_id]; - module_manager.add_module_net_sink(mem_module, net, mem_module, 0, sink_port_id, sink_pin_id); - - /* Cache the nets */ - module_nets.push_back(net); - } - - return module_nets; -} - -/******************************************************************** - * Connect all the memory modules under the parent module in a chain - * - * +--------+ +--------+ +--------+ - * ccff_head --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail - * | Module | | Module | | Module | - * | [0] | | [1] | | [N-1] | - * +--------+ +--------+ +--------+ - * For the 1st memory module: - * net source is the configuration chain head of the primitive module - * net sink is the configuration chain head of the next memory module - * - * For the rest of memory modules: - * net source is the configuration chain tail of the previous memory module - * net sink is the configuration chain head of the next memory module - * - * Note that: - * This function is designed for memory modules ONLY! - * Do not use it to replace the - * add_module_nets_cmos_memory_chain_config_bus() !!! - *********************************************************************/ -static -void add_module_nets_to_cmos_memory_chain_module(ModuleManager& module_manager, - const ModuleId& parent_module, - const std::vector& output_nets, - const CircuitLibrary& circuit_lib, - const CircuitPortId& model_input_port, - const CircuitPortId& model_output_port) { - /* Counter for the nets */ - size_t net_counter = 0; - - for (size_t mem_index = 0; mem_index < module_manager.configurable_children(parent_module).size(); ++mem_index) { - ModuleId net_src_module_id; - size_t net_src_instance_id; - ModulePortId net_src_port_id; - - ModuleId net_sink_module_id; - size_t net_sink_instance_id; - ModulePortId net_sink_port_id; - - if (0 == mem_index) { - /* Find the port name of configuration chain head */ - std::string src_port_name = generate_configuration_chain_head_name(); - net_src_module_id = parent_module; - net_src_instance_id = 0; - net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); - - /* Find the port name of next memory module */ - std::string sink_port_name = circuit_lib.port_prefix(model_input_port); - net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; - net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; - net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); - } else { - /* Find the port name of previous memory module */ - std::string src_port_name = circuit_lib.port_prefix(model_output_port); - net_src_module_id = module_manager.configurable_children(parent_module)[mem_index - 1]; - net_src_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index - 1]; - net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); - - /* Find the port name of next memory module */ - std::string sink_port_name = circuit_lib.port_prefix(model_input_port); - net_sink_module_id = module_manager.configurable_children(parent_module)[mem_index]; - net_sink_instance_id = module_manager.configurable_child_instances(parent_module)[mem_index]; - net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); - } - - /* Get the pin id for source port */ - BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); - /* Get the pin id for sink port */ - BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); - /* Port sizes of source and sink should match */ - VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { - /* Create a net and add source and sink to it */ - ModuleNetId net; - if (0 == mem_index) { - net = module_manager.create_module_net(parent_module); - } else { - net = output_nets[net_counter]; - } - /* Add net source */ - module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); - /* Add net sink */ - module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); - - /* Update net counter */ - if (0 < mem_index) { - net_counter++; - } - } - } - - /* For the last memory module: - * net source is the configuration chain tail of the previous memory module - * net sink is the configuration chain tail of the primitive module - */ - /* Find the port name of previous memory module */ - std::string src_port_name = circuit_lib.port_prefix(model_output_port); - ModuleId net_src_module_id = module_manager.configurable_children(parent_module).back(); - size_t net_src_instance_id = module_manager.configurable_child_instances(parent_module).back(); - ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); - - /* Find the port name of next memory module */ - std::string sink_port_name = generate_configuration_chain_tail_name(); - ModuleId net_sink_module_id = parent_module; - size_t net_sink_instance_id = 0; - ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); - - /* Get the pin id for source port */ - BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); - /* Get the pin id for sink port */ - BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); - /* Port sizes of source and sink should match */ - VTR_ASSERT(net_src_port.get_width() == net_sink_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < net_src_port.pins().size(); ++pin_id) { - /* Create a net and add source and sink to it */ - ModuleNetId net = output_nets[net_counter]; - /* Add net source */ - module_manager.add_module_net_source(parent_module, net, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[pin_id]); - /* Add net sink */ - module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[pin_id]); - - /* Update net counter */ - net_counter++; - } - - VTR_ASSERT(net_counter == output_nets.size()); -} - -/********************************************************************* - * Flat memory modules - * - * in[0] in[1] in[N] - * | | | - * v v v - * +-------+ +-------+ +-------+ - * | SRAM | | SRAM | ... | SRAM | - * | [0] | | [1] | | [N-1] | - * +-------+ +-------+ +-------+ - * | | ... | - * v v v - * +------------------------------------+ - * | Multiplexer Configuration port | - * - ********************************************************************/ -static -void build_memory_standalone_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::string& module_name, - const CircuitModelId& sram_model, - const size_t& num_mems) { - /* Get the global ports required by the SRAM */ - std::vector global_port_types; - global_port_types.push_back(SPICE_MODEL_PORT_CLOCK); - global_port_types.push_back(SPICE_MODEL_PORT_INPUT); - std::vector sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false); - /* Get the input ports from the SRAM */ - std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); - /* Get the output ports from the SRAM */ - std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); - - /* Create a module and add to the module manager */ - ModuleId mem_module = module_manager.add_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); - - /* Add each input port */ - for (const auto& port : sram_input_ports) { - BasicPort input_port(circuit_lib.port_prefix(port), num_mems); - module_manager.add_port(mem_module, input_port, ModuleManager::MODULE_INPUT_PORT); - } - /* Add each output port: port width should match the number of memories */ - for (const auto& port : sram_output_ports) { - BasicPort output_port(circuit_lib.port_prefix(port), num_mems); - module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - /* Find the sram module in the module manager */ - ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model)); - - /* Instanciate each submodule */ - for (size_t i = 0; i < num_mems; ++i) { - size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module); - module_manager.add_child_module(mem_module, sram_mem_module); - module_manager.add_configurable_child(mem_module, sram_mem_module, sram_mem_instance); - - /* Build module nets */ - /* Wire inputs of parent module to inputs of child modules */ - add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_input_ports, sram_mem_module, i, sram_mem_instance); - /* Wire inputs of parent module to outputs of child modules */ - add_module_output_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_output_ports, sram_mem_module, i, sram_mem_instance); - } - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, mem_module); -} - -/********************************************************************* - * Scan-chain organization - * - * +-------+ +-------+ +-------+ - * scan-chain--->| CCFF |--->| CCFF |--->... --->| CCFF |---->scan-chain - * input&clock | [0] | | [1] | | [N-1] | output - * +-------+ +-------+ +-------+ - * | | ... | - * v v v - * +-----------------------------------------+ - * | Multiplexer Configuration port | - * - ********************************************************************/ -static -void build_memory_chain_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::string& module_name, - const CircuitModelId& sram_model, - const size_t& num_mems) { - - /* Get the input ports from the SRAM */ - std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); - /* Should have only 1 input port */ - VTR_ASSERT( 1 == sram_input_ports.size() ); - /* Get the output ports from the SRAM */ - std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Should have only 1 or 2 output port */ - VTR_ASSERT( (1 == sram_output_ports.size()) || ( 2 == sram_output_ports.size()) ); - - /* Create a module and add to the module manager */ - ModuleId mem_module = module_manager.add_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); - - /* Add an input port, which is the head of configuration chain in the module */ - /* TODO: restriction!!! - * consider only the first input of the CCFF model as the D port, - * which will be connected to the head of the chain - */ - BasicPort chain_head_port(generate_configuration_chain_head_name(), - circuit_lib.port_size(sram_input_ports[0])); - module_manager.add_port(mem_module, chain_head_port, ModuleManager::MODULE_INPUT_PORT); - /* Add an output port, which is the tail of configuration chain in the module */ - /* TODO: restriction!!! - * consider only the first output of the CCFF model as the Q port, - * which will be connected to the tail of the chain - */ - BasicPort chain_tail_port(generate_configuration_chain_tail_name(), - circuit_lib.port_size(sram_output_ports[0])); - module_manager.add_port(mem_module, chain_tail_port, ModuleManager::MODULE_OUTPUT_PORT); - - /* Add each output port: port width should match the number of memories */ - for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) { - std::string port_name; - if (0 == iport) { - port_name = generate_configuration_chain_data_out_name(); - } else { - VTR_ASSERT( 1 == iport); - port_name = generate_configuration_chain_inverted_data_out_name(); - } - BasicPort output_port(port_name, num_mems); - module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - /* Find the sram module in the module manager */ - ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model)); - - /* Cache the output nets for non-inverted data output */ - std::vector mem_output_nets; - - /* Instanciate each submodule */ - for (size_t i = 0; i < num_mems; ++i) { - size_t sram_mem_instance = module_manager.num_instance(mem_module, sram_mem_module); - module_manager.add_child_module(mem_module, sram_mem_module); - module_manager.add_configurable_child(mem_module, sram_mem_module, sram_mem_instance); - - /* Build module nets to wire outputs of sram modules to outputs of memory module */ - for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) { - std::string port_name; - if (0 == iport) { - port_name = generate_configuration_chain_data_out_name(); - } else { - VTR_ASSERT( 1 == iport); - port_name = generate_configuration_chain_inverted_data_out_name(); - } - std::vector output_nets = add_module_output_nets_to_chain_mem_modules(module_manager, mem_module, - port_name, circuit_lib, sram_output_ports[iport], - sram_mem_module, i, sram_mem_instance); - /* Cache only for regular data outputs */ - if (0 == iport) { - mem_output_nets.insert(mem_output_nets.end(), output_nets.begin(), output_nets.end()); - } - } - } - - /* Build module nets to wire the configuration chain */ - add_module_nets_to_cmos_memory_chain_module(module_manager, mem_module, mem_output_nets, - circuit_lib, sram_input_ports[0], sram_output_ports[0]); - - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, mem_module); -} - -/********************************************************************* - * Memory bank organization - * - * Bit lines(BL/BLB) Word lines (WL/WLB) - * | | - * v v - * +------------------------------------+ - * | Memory Module Configuration port | - * +------------------------------------+ - * | | | - * v v v - * +-------+ +-------+ +-------+ - * | SRAM | | SRAM | ... | SRAM | - * | [0] | | [1] | | [N-1] | - * +-------+ +-------+ +-------+ - * | | ... | - * v v v - * +------------------------------------+ - * | Multiplexer Configuration port | - * - ********************************************************************/ -static -void build_memory_bank_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::string& module_name, - const CircuitModelId& sram_model, - const size_t& num_mems) { - /* Get the global ports required by the SRAM */ - std::vector global_port_types; - global_port_types.push_back(SPICE_MODEL_PORT_CLOCK); - global_port_types.push_back(SPICE_MODEL_PORT_INPUT); - std::vector sram_global_ports = circuit_lib.model_global_ports_by_type(sram_model, global_port_types, true, false); - /* Get the input ports from the SRAM */ - std::vector sram_input_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_INPUT, true); - /* A SRAM cell with BL/WL should not have any input */ - VTR_ASSERT( 0 == sram_input_ports.size() ); - /* Get the output ports from the SRAM */ - std::vector sram_output_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Get the BL/WL ports from the SRAM */ - std::vector sram_bl_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_BL, true); - std::vector sram_blb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_BLB, true); - std::vector sram_wl_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_WL, true); - std::vector sram_wlb_ports = circuit_lib.model_ports_by_type(sram_model, SPICE_MODEL_PORT_WLB, true); - - /* Create a module and add to the module manager */ - ModuleId mem_module = module_manager.add_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); - - /* Add module ports: the ports come from the SRAM modules */ - /* Add each input port */ - for (const auto& port : sram_input_ports) { - BasicPort input_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port)); - module_manager.add_port(mem_module, input_port, ModuleManager::MODULE_INPUT_PORT); - } - /* Add each output port: port width should match the number of memories */ - for (const auto& port : sram_output_ports) { - BasicPort output_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port)); - module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - /* Add each output port: port width should match the number of memories */ - for (const auto& port : sram_bl_ports) { - BasicPort bl_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port)); - module_manager.add_port(mem_module, bl_port, ModuleManager::MODULE_INPUT_PORT); - } - for (const auto& port : sram_blb_ports) { - BasicPort blb_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port)); - module_manager.add_port(mem_module, blb_port, ModuleManager::MODULE_INPUT_PORT); - } - for (const auto& port : sram_wl_ports) { - BasicPort wl_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port)); - module_manager.add_port(mem_module, wl_port, ModuleManager::MODULE_INPUT_PORT); - } - for (const auto& port : sram_wlb_ports) { - BasicPort wlb_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port)); - module_manager.add_port(mem_module, wlb_port, ModuleManager::MODULE_INPUT_PORT); - } - - /* Find the sram module in the module manager */ - ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model)); - - /* Instanciate each submodule */ - for (size_t i = 0; i < num_mems; ++i) { - /* Memory seed module instanciation */ - size_t sram_instance = module_manager.num_instance(mem_module, sram_mem_module); - module_manager.add_child_module(mem_module, sram_mem_module); - - /* Build module nets */ - /* Wire inputs of parent module to inputs of child modules */ - add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_input_ports, sram_mem_module, i, sram_instance); - /* Wire inputs of parent module to outputs of child modules */ - add_module_output_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_output_ports, sram_mem_module, i, sram_instance); - /* Wire BL/WLs of parent module to BL/WLs of child modules */ - add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_bl_ports, sram_mem_module, i, sram_instance); - add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_blb_ports, sram_mem_module, i, sram_instance); - add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_wl_ports, sram_mem_module, i, sram_instance); - add_module_input_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_wlb_ports, sram_mem_module, i, sram_instance); - } - - /* TODO: if a local memory decoder is required, instanciate it here */ - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, mem_module); -} - - -/********************************************************************* - * Generate Verilog modules for the memories that are used - * by a circuit model - * The organization of memory circuit will depend on the style of - * configuration protocols - * Currently, we support - * 1. Flat SRAM organization - * 2. Configuration chain - * 3. Memory bank (memory decoders) - ********************************************************************/ -static -void build_memory_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - const std::string& module_name, - const CircuitModelId& sram_model, - const size_t& num_mems) { - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - build_memory_standalone_module(module_manager, circuit_lib, - module_name, sram_model, num_mems); - break; - case SPICE_SRAM_SCAN_CHAIN: - build_memory_chain_module(module_manager, circuit_lib, - module_name, sram_model, num_mems); - break; - case SPICE_SRAM_MEMORY_BANK: - build_memory_bank_module(module_manager, circuit_lib, - module_name, sram_model, num_mems); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, LINE%d) Invalid SRAM organization!\n", - __FILE__, __LINE__); - } -} - - -/********************************************************************* - * Generate Verilog modules for the memories that are used - * by multiplexers - * - * +----------------+ - * mem_in --->| Memory Module |---> mem_out - * +----------------+ - * | | ... | | - * v v v v SRAM ports of multiplexer - * +---------------------+ - * in--->| Multiplexer Module |---> out - * +---------------------+ - ********************************************************************/ -static -void build_mux_memory_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph) { - /* Find the actual number of configuration bits, based on the mux graph - * Due to the use of local decoders inside mux, this may be - */ - size_t num_config_bits = find_mux_num_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type); - /* Multiplexers built with different technology is in different organization */ - switch (circuit_lib.design_tech_type(mux_model)) { - case SPICE_MODEL_DESIGN_CMOS: { - /* Generate module name */ - std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, - find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), - std::string(MEMORY_MODULE_POSTFIX)); - - /* Get the sram ports from the mux */ - std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); - VTR_ASSERT( 1 == sram_models.size() ); - - build_memory_module(module_manager, circuit_lib, sram_orgz_type, module_name, sram_models[0], num_config_bits); - break; - } - case SPICE_MODEL_DESIGN_RRAM: - /* We do not need a memory submodule for RRAM MUX, - * RRAM are embedded in the datapath - * TODO: generate local encoders for RRAM-based multiplexers here!!! - */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", - __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); - exit(1); - } -} - -/********************************************************************* - * Build modules for - * the memories that are affiliated to multiplexers and other programmable - * circuit models, such as IOPADs, LUTs, etc. - * - * We keep the memory modules separated from the multiplexers and other - * programmable circuit models, for the sake of supporting - * various configuration schemes. - * By following such organiztion, the Verilog modules of the circuit models - * implements the functionality (circuit logic) only, while the memory Verilog - * modules implements the memory circuits as well as configuration protocols. - * For example, the local decoders of multiplexers are implemented in the - * memory modules. - * Take another example, the memory circuit can implement the scan-chain or - * memory-bank organization for the memories. - ********************************************************************/ -void build_memory_modules(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type) { - /* Start time count */ - clock_t t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, - "Building memory modules..."); - - /* Create the memory circuits for the multiplexer */ - for (auto mux : mux_lib.muxes()) { - const MuxGraph& mux_graph = mux_lib.mux_graph(mux); - CircuitModelId mux_model = mux_lib.mux_circuit_model(mux); - /* Bypass the non-MUX circuit models (i.e., LUTs). - * They should be handled in a different way - * Memory circuits of LUT includes both regular and mode-select ports - */ - if (SPICE_MODEL_MUX != circuit_lib.model_type(mux_model)) { - continue; - } - /* Create a Verilog module for the memories used by the multiplexer */ - build_mux_memory_module(module_manager, circuit_lib, sram_orgz_type, mux_model, mux_graph); - } - - /* Create the memory circuits for non-MUX circuit models. - * In this case, the memory modules are designed to interface - * the mode-select ports - */ - for (const auto& model : circuit_lib.models()) { - /* Bypass MUXes, they have already been considered */ - if (SPICE_MODEL_MUX == circuit_lib.model_type(model)) { - continue; - } - /* Bypass those modules without any SRAM ports */ - std::vector sram_ports = circuit_lib.model_ports_by_type(model, SPICE_MODEL_PORT_SRAM, true); - if (0 == sram_ports.size()) { - continue; - } - /* Find the name of memory module */ - /* Get the total number of SRAMs */ - size_t num_mems = 0; - for (const auto& port : sram_ports) { - num_mems += circuit_lib.port_size(port); - } - /* Get the circuit model for the memory circuit used by the multiplexer */ - std::vector sram_models = find_circuit_sram_models(circuit_lib, model); - /* Should have only 1 SRAM model */ - VTR_ASSERT( 1 == sram_models.size() ); - - /* Create the module name for the memory block */ - std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX)); - - /* Create a Verilog module for the memories used by the circuit model */ - build_memory_module(module_manager, circuit_lib, sram_orgz_type, module_name, sram_models[0], num_mems); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %.2g seconds\n", - run_time_sec); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.h deleted file mode 100644 index 276fa4fad..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.h +++ /dev/null @@ -1,20 +0,0 @@ -/*********************************************** - * Header file for build_memory_modules.cpp - **********************************************/ - -#ifndef BUILD_MEMORY_MODULES_H -#define BUILD_MEMORY_MODULES_H - -/* Include other header files which are dependency on the function declared below */ - -#include "circuit_library.h" -#include "mux_graph.h" -#include "mux_library.h" -#include "module_manager.h" - -void build_memory_modules(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp deleted file mode 100644 index fc710a20d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp +++ /dev/null @@ -1,84 +0,0 @@ -/******************************************************************** - * This file includes most utilized functions that are used to - * build module graphs - ********************************************************************/ -#include -#include "vtr_assert.h" - -#include "fpga_x2p_naming.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "build_module_graph_utils.h" - -/******************************************************************** - * Find input port of a buffer/inverter module - ********************************************************************/ -ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager, - const ModuleId& module_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& model_id, - const e_spice_model_port_type& port_type) { - /* We must have a valid module id */ - VTR_ASSERT(true == module_manager.valid_module_id(module_id)); - /* Check the type of model */ - VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_lib.model_type(model_id)); - - /* Add module nets to wire to the buffer module */ - /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ - std::vector model_ports = circuit_lib.model_ports_by_type(model_id, port_type, true); - VTR_ASSERT(1 == model_ports.size()); - - /* Find the input and output module ports */ - ModulePortId module_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(model_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(module_id, module_port_id)); - - return module_port_id; -} - -/******************************************************************** - * Add inverter/buffer module to a parent module - * and complete the wiring to the input port of inverter/buffer - * This function will return the wire created for the output port of inverter/buffer - * - * parent_module - * +----------------------------------------------------------------- - * | - * | input_net output_net - * | | | - * | v +---------------+ v - * | src_module_port --------->| child_module |--------> - * | +---------------+ - * - ********************************************************************/ -ModuleNetId add_inverter_buffer_child_module_and_nets(ModuleManager& module_manager, - const ModuleId& parent_module, - const CircuitLibrary& circuit_lib, - const CircuitModelId& model_id, - const ModuleNetId& input_net) { - /* We must have a valid module id */ - VTR_ASSERT(true == module_manager.valid_module_id(parent_module)); - - std::string module_name = circuit_lib.model_name(model_id); - ModuleId child_module = module_manager.find_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(child_module)); - - ModulePortId module_input_port_id = find_inverter_buffer_module_port(module_manager, child_module, circuit_lib, model_id, SPICE_MODEL_PORT_INPUT); - ModulePortId module_output_port_id = find_inverter_buffer_module_port(module_manager, child_module, circuit_lib, model_id, SPICE_MODEL_PORT_OUTPUT); - - /* Port size should be 1 ! */ - VTR_ASSERT(1 == module_manager.module_port(child_module, module_input_port_id).get_width()); - VTR_ASSERT(1 == module_manager.module_port(child_module, module_output_port_id).get_width()); - - /* Instanciate a child module */ - size_t child_instance = module_manager.num_instance(parent_module, child_module); - module_manager.add_child_module(parent_module, child_module); - - /* Use the net to connect to the input net of buffer */ - module_manager.add_module_net_sink(parent_module, input_net, child_module, child_instance, module_input_port_id, 0); - - /* Create a net to bridge the input inverter and LUT MUX */ - ModuleNetId output_net = module_manager.create_module_net(parent_module); - module_manager.add_module_net_source(parent_module, output_net, child_module, child_instance, module_output_port_id, 0); - - return output_net; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h deleted file mode 100644 index a1610632b..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h +++ /dev/null @@ -1,28 +0,0 @@ -/******************************************************************** - * Header file for build_module_graph_utils.cpp - ********************************************************************/ -#ifndef BUILD_MODULE_GRAPH_UTILS_H -#define BUILD_MODULE_GRAPH_UTILS_H - -#include -#include -#include "spice_types.h" -#include "sides.h" -#include "vtr_geometry.h" -#include "vpr_types.h" -#include "module_manager.h" -#include "circuit_library.h" - -ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager, - const ModuleId& module_id, - const CircuitLibrary& circuit_lib, - const CircuitModelId& model_id, - const e_spice_model_port_type& port_type); - -ModuleNetId add_inverter_buffer_child_module_and_nets(ModuleManager& module_manager, - const ModuleId& parent_module, - const CircuitLibrary& circuit_lib, - const CircuitModelId& model_id, - const ModuleNetId& input_net); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp deleted file mode 100644 index 3d550d9ee..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp +++ /dev/null @@ -1,1428 +0,0 @@ -/*********************************************** - * This file includes functions to generate - * Verilog submodules for multiplexers. - * including both fundamental submodules - * such as a branch in a multiplexer - * and the full multiplexer - **********************************************/ -#include -#include -#include - -#include "util.h" -#include "vtr_assert.h" - -/* Device-level header files */ -#include "mux_graph.h" -#include "module_manager.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "mux_utils.h" -#include "circuit_library_utils.h" -#include "decoder_library_utils.h" -#include "module_manager_utils.h" -#include "build_module_graph_utils.h" - -/* FPGA-X2P context header files */ -#include "spice_types.h" -/* TODO: we should have a header file for naming constexpr only */ -#include "verilog_global.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -/* FPGA-Verilog context header files */ -#include "build_mux_modules.h" - -/********************************************************************* - * Generate structural Verilog codes (consist of transmission-gates or - * pass-transistor) modeling an branch circuit - * for a multiplexer with the given size - * - * +----------+ - * input[0] --->| tgate[0] |-+ - * +----------+ | - * | - * +----------+ | - * input[1] --->| tgate[1] |-+--->output[0] - * +----------+ | - * | - * ... ... | - * | - * +----------+ | - * input[i] --->| tgate[i] |-+ - * +----------+ - *********************************************************************/ -static -void build_cmos_mux_branch_body(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& tgate_model, - const ModuleId& mux_module, - const ModulePortId& module_input_port, - const ModulePortId& module_output_port, - const ModulePortId& module_mem_port, - const ModulePortId& module_mem_inv_port, - const MuxGraph& mux_graph) { - /* Get the module id of tgate in Module manager */ - ModuleId tgate_module_id = module_manager.find_module(circuit_lib.model_name(tgate_model)); - VTR_ASSERT(ModuleId::INVALID() != tgate_module_id); - - /* Get model ports of tgate */ - std::vector tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true); - std::vector tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(3 == tgate_input_ports.size()); - VTR_ASSERT(1 == tgate_output_ports.size()); - - /* Find the module ports of tgate module */ - /* Input port is the data path input of the tgate, whose size must be 1 ! */ - ModulePortId tgate_module_input = module_manager.find_module_port(tgate_module_id, circuit_lib.port_prefix(tgate_input_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_input)); - BasicPort tgate_module_input_port = module_manager.module_port(tgate_module_id, tgate_module_input); - VTR_ASSERT(1 == tgate_module_input_port.get_width()); - - /* Mem port is the memory of the tgate, whose size must be 1 ! */ - ModulePortId tgate_module_mem = module_manager.find_module_port(tgate_module_id, circuit_lib.port_prefix(tgate_input_ports[1])); - VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_mem)); - BasicPort tgate_module_mem_port = module_manager.module_port(tgate_module_id, tgate_module_mem); - VTR_ASSERT(1 == tgate_module_mem_port.get_width()); - - /* Mem inv port is the inverted memory of the tgate, whose size must be 1 ! */ - ModulePortId tgate_module_mem_inv = module_manager.find_module_port(tgate_module_id, circuit_lib.port_prefix(tgate_input_ports[2])); - VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_mem_inv)); - BasicPort tgate_module_mem_inv_port = module_manager.module_port(tgate_module_id, tgate_module_mem_inv); - VTR_ASSERT(1 == tgate_module_mem_inv_port.get_width()); - - /* Output port is the data path output of the tgate, whose size must be 1 ! */ - ModulePortId tgate_module_output = module_manager.find_module_port(tgate_module_id, circuit_lib.port_prefix(tgate_output_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(tgate_module_id, tgate_module_output)); - BasicPort tgate_module_output_port = module_manager.module_port(tgate_module_id, tgate_module_output); - VTR_ASSERT(1 == tgate_module_output_port.get_width()); - - /* Ensure that input port size does match mux inputs */ - BasicPort input_port = module_manager.module_port(mux_module, module_input_port); - VTR_ASSERT(input_port.get_width() == mux_graph.num_inputs()); - - /* Add module nets for each mux inputs */ - std::vector mux_input_nets; - for (const size_t& pin : input_port.pins()) { - ModuleNetId input_net = module_manager.create_module_net(mux_module); - mux_input_nets.push_back(input_net); - /* Configure the source for each net */ - module_manager.add_module_net_source(mux_module, input_net, mux_module, 0, module_input_port, pin); - } - - /* Ensure that output port size does match mux outputs */ - BasicPort output_port = module_manager.module_port(mux_module, module_output_port); - VTR_ASSERT(output_port.get_width() == mux_graph.num_outputs()); - - /* Add module nets for each mux outputs */ - std::vector mux_output_nets; - for (const size_t& pin : output_port.pins()) { - ModuleNetId output_net = module_manager.create_module_net(mux_module); - mux_output_nets.push_back(output_net); - /* Configure the sink for each net */ - module_manager.add_module_net_sink(mux_module, output_net, mux_module, 0, module_output_port, pin); - } - - /* Ensure that mem port size does match mux outputs */ - BasicPort mem_port = module_manager.module_port(mux_module, module_mem_port); - VTR_ASSERT(mem_port.get_width() == mux_graph.num_memory_bits()); - - /* Add module nets for each mem inputs */ - std::vector mux_mem_nets; - for (const size_t& pin : mem_port.pins()) { - ModuleNetId mem_net = module_manager.create_module_net(mux_module); - mux_mem_nets.push_back(mem_net); - /* Configure the source for each net */ - module_manager.add_module_net_source(mux_module, mem_net, mux_module, 0, module_mem_port, pin); - } - - /* Ensure that mem_inv port size does match mux outputs */ - BasicPort mem_inv_port = module_manager.module_port(mux_module, module_mem_inv_port); - VTR_ASSERT(mem_inv_port.get_width() == mux_graph.num_memory_bits()); - - /* Add module nets for each mem inverted inputs */ - std::vector mux_mem_inv_nets; - for (const size_t& pin : mem_inv_port.pins()) { - ModuleNetId mem_net = module_manager.create_module_net(mux_module); - mux_mem_inv_nets.push_back(mem_net); - /* Configure the source for each net */ - module_manager.add_module_net_source(mux_module, mem_net, mux_module, 0, module_mem_inv_port, pin); - } - - /* Build a module following the connections in mux_graph */ - /* Iterate over the inputs */ - for (const auto& mux_input : mux_graph.inputs()) { - /* Iterate over the outputs */ - for (const auto& mux_output : mux_graph.outputs()) { - /* Add the a tgate to bridge the mux input and output */ - size_t tgate_instance = module_manager.num_instance(mux_module, tgate_module_id); - module_manager.add_child_module(mux_module, tgate_module_id); - - /* Add module nets to connect the mux input and tgate input */ - module_manager.add_module_net_sink(mux_module, mux_input_nets[size_t(mux_graph.input_id(mux_input))], tgate_module_id, tgate_instance, tgate_module_input, tgate_module_input_port.get_lsb()); - - /* if there is a connection between the input and output, a tgate will be outputted */ - std::vector edges = mux_graph.find_edges(mux_input, mux_output); - /* There should be only one edge or no edge*/ - VTR_ASSERT((1 == edges.size()) || (0 == edges.size())); - /* No need to output tgates if there are no edges between two nodes */ - if (0 == edges.size()) { - continue; - } - - /* Add module nets to connect the mux output and tgate output */ - module_manager.add_module_net_source(mux_module, mux_output_nets[size_t(mux_graph.output_id(mux_output))], tgate_module_id, tgate_instance, tgate_module_output, tgate_module_output_port.get_lsb()); - - MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]); - /* Add module nets to connect the mem input and tgate mem input */ - if (false == mux_graph.is_edge_use_inv_mem(edges[0])) { - /* wire mem to mem of module, and wire mem_inv to mem_inv of module */ - module_manager.add_module_net_sink(mux_module, mux_mem_nets[size_t(mux_mem)], tgate_module_id, tgate_instance, tgate_module_mem, tgate_module_mem_port.get_lsb()); - module_manager.add_module_net_sink(mux_module, mux_mem_inv_nets[size_t(mux_mem)], tgate_module_id, tgate_instance, tgate_module_mem_inv, tgate_module_mem_inv_port.get_lsb()); - } else { - /* wire mem_inv to mem of module, wire mem to mem_inv of module */ - module_manager.add_module_net_sink(mux_module, mux_mem_inv_nets[size_t(mux_mem)], tgate_module_id, tgate_instance, tgate_module_mem, tgate_module_mem_port.get_lsb()); - module_manager.add_module_net_sink(mux_module, mux_mem_nets[size_t(mux_mem)], tgate_module_id, tgate_instance, tgate_module_mem_inv, tgate_module_mem_inv_port.get_lsb()); - } - } - } -} - -/********************************************************************* - * Generate Verilog codes modeling an branch circuit - * for a CMOS multiplexer with the given size - * Support structural and behavioral Verilog codes - *********************************************************************/ -static -void build_cmos_mux_branch_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const std::string& module_name, - const MuxGraph& mux_graph) { - /* Get the tgate model */ - CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(mux_model); - - /* Skip output if the tgate model is a MUX2, it is handled by essential-gate generator */ - if (SPICE_MODEL_GATE == circuit_lib.model_type(tgate_model)) { - VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model)); - return; - } - - std::vector tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true, true); - - /* Generate the Verilog netlist according to the mux_graph */ - /* Find out the number of inputs */ - size_t num_inputs = mux_graph.num_inputs(); - /* Find out the number of outputs */ - size_t num_outputs = mux_graph.num_outputs(); - /* Find out the number of memory bits */ - size_t num_mems = mux_graph.num_memory_bits(); - - /* Check codes to ensure the port of Verilog netlists will match */ - /* MUX graph must have only 1 output */ - VTR_ASSERT(1 == num_outputs); - /* MUX graph must have only 1 level*/ - VTR_ASSERT(1 == mux_graph.num_levels()); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId mux_module = module_manager.add_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); - /* Add module ports */ - /* Add each input port */ - BasicPort input_port("in", num_inputs); - ModulePortId module_input_port = module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT); - /* Add each output port */ - BasicPort output_port("out", num_outputs); - ModulePortId module_output_port = module_manager.add_port(mux_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); - /* Add each memory port */ - BasicPort mem_port("mem", num_mems); - ModulePortId module_mem_port = module_manager.add_port(mux_module, mem_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort mem_inv_port("mem_inv", num_mems); - ModulePortId module_mem_inv_port = module_manager.add_port(mux_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); - - /* By default we give a structural description, - * Writers can freely write the module in their styles - * For instance, Verilog writer can ignore the internal structure and write in behavioral codes - */ - build_cmos_mux_branch_body(module_manager, circuit_lib, tgate_model, mux_module, module_input_port, module_output_port, module_mem_port, module_mem_inv_port, mux_graph); - - /* Add global ports to the mux module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, mux_module); -} - -/********************************************************************* - * Generate Verilog codes modeling an branch circuit - * for a RRAM-based multiplexer with the given size - * Support structural and behavioral Verilog codes - *********************************************************************/ -static -void build_rram_mux_branch_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const std::string& module_name, - const MuxGraph& mux_graph) { - /* Get the input ports from the mux */ - std::vector mux_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); - /* Get the output ports from the mux */ - std::vector mux_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Get the BL and WL ports from the mux */ - std::vector mux_blb_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_BLB, true); - std::vector mux_wl_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_WL, true); - - /* Generate the Verilog netlist according to the mux_graph */ - /* Find out the number of inputs */ - size_t num_inputs = mux_graph.num_inputs(); - /* Find out the number of outputs */ - size_t num_outputs = mux_graph.num_outputs(); - /* Find out the number of memory bits */ - size_t num_mems = mux_graph.num_memory_bits(); - - /* Check codes to ensure the port of Verilog netlists will match */ - /* MUX graph must have only 1 output */ - VTR_ASSERT(1 == num_outputs); - /* MUX graph must have only 1 level*/ - VTR_ASSERT(1 == mux_graph.num_levels()); - /* MUX graph must have only 1 input and 1 BLB and 1 WL port */ - VTR_ASSERT(1 == mux_input_ports.size()); - VTR_ASSERT(1 == mux_output_ports.size()); - VTR_ASSERT(1 == mux_blb_ports.size()); - VTR_ASSERT(1 == mux_wl_ports.size()); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId mux_module = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != mux_module); - - /* Add module ports */ - /* Add each global programming enable/disable ports */ - std::vector prog_enable_ports = circuit_lib.model_global_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true, true); - for (const auto& port : prog_enable_ports) { - /* Configure each global port */ - BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - module_manager.add_port(mux_module, global_port, ModuleManager::MODULE_GLOBAL_PORT); - } - - /* Add each input port */ - BasicPort input_port(circuit_lib.port_prefix(mux_input_ports[0]), num_inputs); - module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT); - - /* Add each output port */ - BasicPort output_port(circuit_lib.port_prefix(mux_output_ports[0]), num_outputs); - module_manager.add_port(mux_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); - - /* Add RRAM programming ports, - * RRAM MUXes require one more pair of BLB and WL - * to configure the memories. See schematic for details - */ - BasicPort blb_port(circuit_lib.port_prefix(mux_blb_ports[0]), num_mems + 1); - module_manager.add_port(mux_module, blb_port, ModuleManager::MODULE_INPUT_PORT); - - BasicPort wl_port(circuit_lib.port_prefix(mux_wl_ports[0]), num_mems + 1); - module_manager.add_port(mux_module, wl_port, ModuleManager::MODULE_INPUT_PORT); - - /* Note: we do not generate the internal structure of the ReRAM-based MUX - * circuit as a module graph! - * This is mainly due to that the internal structure could be different - * in Verilog or SPICE netlists - * Leave the writers to customize this - */ -} - -/*********************************************** - * Generate Verilog codes modeling an branch circuit - * for a multiplexer with the given size - **********************************************/ -static -void build_mux_branch_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const size_t& mux_size, - const MuxGraph& mux_graph) { - std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_size, mux_graph.num_inputs(), verilog_mux_basis_posfix); - - /* Multiplexers built with different technology is in different organization */ - switch (circuit_lib.design_tech_type(mux_model)) { - case SPICE_MODEL_DESIGN_CMOS: - build_cmos_mux_branch_module(module_manager, circuit_lib, mux_model, module_name, mux_graph); - break; - case SPICE_MODEL_DESIGN_RRAM: - build_rram_mux_branch_module(module_manager, circuit_lib, mux_model, module_name, mux_graph); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", - __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); - exit(1); - } -} - -/******************************************************************** - * Generate the standard-cell-based internal logic (multiplexing structure) - * for a multiplexer or LUT in Verilog codes - * This function will : - * 1. build a multiplexing structure by instanciating standard cells MUX2 - * 2. add intermediate buffers between multiplexing stages if specified. - *******************************************************************/ -static -void build_cmos_mux_module_mux2_multiplexing_structure(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const ModuleId& mux_module, - const CircuitModelId& mux_model, - const CircuitModelId& std_cell_model, - const vtr::vector& mux_module_input_nets, - const vtr::vector& mux_module_output_nets, - const vtr::vector& mux_module_mem_nets, - const MuxGraph& mux_graph) { - /* Get the regular (non-mode-select) sram ports from the mux */ - std::vector mux_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, mux_model); - VTR_ASSERT(1 == mux_regular_sram_ports.size()); - - /* Find the input ports and output ports of the standard cell */ - std::vector std_cell_input_ports = circuit_lib.model_ports_by_type(std_cell_model, SPICE_MODEL_PORT_INPUT, true); - std::vector std_cell_output_ports = circuit_lib.model_ports_by_type(std_cell_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Quick check the requirements on port map */ - VTR_ASSERT(3 == std_cell_input_ports.size()); - VTR_ASSERT(1 == std_cell_output_ports.size()); - - /* Find module information of the standard cell MUX2 */ - std::string std_cell_module_name = circuit_lib.model_name(std_cell_model); - /* Get the moduleId for the submodule */ - ModuleId std_cell_module_id = module_manager.find_module(std_cell_module_name); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != std_cell_module_id); - - /* Find the module ports of the standard cell MUX2 module */ - std::vector std_cell_module_inputs; - std::vector std_cell_module_input_ports; - /* Input 0 port is the first data path input of the tgate, whose size must be 1 ! */ - for (size_t port_id = 0; port_id < 2; ++port_id) { - std_cell_module_inputs.push_back(module_manager.find_module_port(std_cell_module_id, circuit_lib.port_prefix(std_cell_input_ports[port_id]))); - VTR_ASSERT(true == module_manager.valid_module_port_id(std_cell_module_id, std_cell_module_inputs[port_id])); - std_cell_module_input_ports.push_back(module_manager.module_port(std_cell_module_id, std_cell_module_inputs[port_id])); - VTR_ASSERT(1 == std_cell_module_input_ports[port_id].get_width()); - } - - /* Mem port is the memory of the standard cell MUX2, whose size must be 1 ! */ - ModulePortId std_cell_module_mem = module_manager.find_module_port(std_cell_module_id, circuit_lib.port_prefix(std_cell_input_ports[2])); - VTR_ASSERT(true == module_manager.valid_module_port_id(std_cell_module_id, std_cell_module_mem)); - BasicPort std_cell_module_mem_port = module_manager.module_port(std_cell_module_id, std_cell_module_mem); - VTR_ASSERT(1 == std_cell_module_mem_port.get_width()); - - /* Output port is the data path output of the standard cell MUX2, whose size must be 1 ! */ - ModulePortId std_cell_module_output = module_manager.find_module_port(std_cell_module_id, circuit_lib.port_prefix(std_cell_output_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(std_cell_module_id, std_cell_module_output)); - BasicPort std_cell_module_output_port = module_manager.module_port(std_cell_module_id, std_cell_module_output); - VTR_ASSERT(1 == std_cell_module_output_port.get_width()); - - /* Cache Net ids for each level of the multiplexer */ - std::vector> module_nets_by_level; - module_nets_by_level.resize(mux_graph.num_node_levels()); - for (size_t level = 0; level < mux_graph.num_node_levels(); ++level) { - /* Print the internal wires located at this level */ - module_nets_by_level[level].resize(mux_graph.num_nodes_at_level(level)); - } - - /* Build the location map of intermediate buffers */ - std::vector inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, mux_model, mux_graph.num_node_levels()); - - /* Add all the branch modules and intermediate buffers */ - for (const auto& node : mux_graph.non_input_nodes()) { - /* Get the size of branch circuit - * Instanciate an branch circuit by the size (fan-in) of the node - */ - size_t branch_size = mux_graph.node_in_edges(node).size(); - /* To match the standard cell MUX2: We should have only 2 input_nodes */ - VTR_ASSERT(2 == branch_size); - - /* Find the instance id */ - size_t std_cell_instance_id = module_manager.num_instance(mux_module, std_cell_module_id); - /* Add the module to mux_module */ - module_manager.add_child_module(mux_module, std_cell_module_id); - - /* Get the node level and index in the current level */ - size_t output_node_level = mux_graph.node_level(node); - size_t output_node_index_at_level = mux_graph.node_index_at_level(node); - /* Set a name for the instance */ - std::string std_cell_instance_name = generate_mux_branch_instance_name(output_node_level, output_node_index_at_level, false); - module_manager.set_child_instance_name(mux_module, std_cell_module_id, std_cell_instance_id, std_cell_instance_name); - - /* Add module nets to wire to next stage modules */ - ModuleNetId branch_net; - if (true == mux_graph.is_node_output(node)) { - /* This is an output node, we should use existing output nets */ - MuxOutputId output_id = mux_graph.output_id(node); - branch_net = mux_module_output_nets[output_id]; - } else { - VTR_ASSERT(false == mux_graph.is_node_output(node)); - branch_net = module_manager.create_module_net(mux_module); - } - module_manager.add_module_net_source(mux_module, branch_net, std_cell_module_id, std_cell_instance_id, std_cell_module_output, std_cell_module_output_port.get_lsb()); - - /* Record the module net id in the cache */ - module_nets_by_level[output_node_level][output_node_index_at_level] = branch_net; - - /* Wire the branch module memory ports to the nets of MUX memory ports */ - /* Get the mems in the branch circuits */ - std::vector mems; - for (const auto& edge : mux_graph.node_in_edges(node)) { - /* Get the mem control the edge */ - MuxMemId mem = mux_graph.find_edge_mem(edge); - /* Add the mem if it is not in the list */ - if (mems.end() == std::find(mems.begin(), mems.end(), mem)) { - mems.push_back(mem); - } - } - /* Connect mem to mem net one by one - * Note that standard cell MUX2 only needs mem but NOT mem_inv - */ - for (const MuxMemId& mem : mems) { - module_manager.add_module_net_sink(mux_module, mux_module_mem_nets[mem], std_cell_module_id, std_cell_instance_id, std_cell_module_mem, std_cell_module_mem_port.get_lsb()); - } - - /* Wire the branch module inputs to the nets in previous stage */ - /* Get the nodes which drive the root_node */ - std::vector input_nodes; - for (const auto& edge : mux_graph.node_in_edges(node)) { - /* Get the nodes drive the edge */ - for (const auto& src_node : mux_graph.edge_src_nodes(edge)) { - input_nodes.push_back(src_node); - } - } - /* Number of inputs should match the branch_input_size!!! */ - VTR_ASSERT(input_nodes.size() == branch_size); - /* To match the standard cell MUX2: We should have only 2 input_nodes */ - VTR_ASSERT(2 == input_nodes.size()); - /* build the link between input_node[0] and std_cell_input_port[0] - * build the link between input_node[1] and std_cell_input_port[1] - */ - for (size_t node_id = 0; node_id < input_nodes.size(); ++node_id) { - /* Find the port info of each input node */ - size_t input_node_level = mux_graph.node_level(input_nodes[node_id]); - size_t input_node_index_at_level = mux_graph.node_index_at_level(input_nodes[node_id]); - /* For inputs of mux, the net id is reserved */ - if (true == mux_graph.is_node_input(input_nodes[node_id])) { - /* Get node input id */ - MuxInputId input_id = mux_graph.input_id(input_nodes[node_id]); - module_manager.add_module_net_sink(mux_module, mux_module_input_nets[input_id], std_cell_module_id, std_cell_instance_id, std_cell_module_inputs[node_id], std_cell_module_input_ports[node_id].get_lsb()); - } else { - VTR_ASSERT (false == mux_graph.is_node_input(input_nodes[node_id])); - /* Find the input port of standard cell */ - module_manager.add_module_net_sink(mux_module, module_nets_by_level[input_node_level][input_node_index_at_level], std_cell_module_id, std_cell_instance_id, std_cell_module_inputs[node_id], std_cell_module_input_ports[node_id].get_lsb()); - } - } - - /* Identify if an intermediate buffer is needed */ - if (false == inter_buffer_location_map[output_node_level]) { - continue; - } - /* Add an intermediate buffer to mux_module if needed */ - if (true == mux_graph.is_node_output(node)) { - /* Output node does not need buffer addition here, it is handled outside this function */ - continue; - } - /* Now we need to add intermediate buffers by instanciating the modules */ - CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(mux_model); - /* We must have a valid model id */ - VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - - /* Create a module net which sources from buffer output */ - ModuleNetId buffer_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, branch_net); - - /* Record the module net id in the cache */ - module_nets_by_level[output_node_level][output_node_index_at_level] = buffer_net; - } -} - -/******************************************************************** - * Generate the pass-transistor/transmission-gate -based internal logic - * (multiplexing structure) for a multiplexer or LUT in Verilog codes - * This function will : - * 1. build a multiplexing structure by instanciating the branch circuits - * generated before - * 2. add intermediate buffers between multiplexing stages if specified. - *******************************************************************/ -static -void build_cmos_mux_module_tgate_multiplexing_structure(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const ModuleId& mux_module, - const CircuitModelId& circuit_model, - const vtr::vector& mux_module_input_nets, - const vtr::vector& mux_module_output_nets, - const vtr::vector& mux_module_mem_nets, - const vtr::vector& mux_module_mem_inv_nets, - const MuxGraph& mux_graph) { - /* Find the actual mux size */ - size_t mux_size = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); - - /* Get the regular (non-mode-select) sram ports from the mux */ - std::vector mux_regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, circuit_model); - VTR_ASSERT(1 == mux_regular_sram_ports.size()); - - /* Cache Net ids for each level of the multiplexer */ - std::vector> module_nets_by_level; - module_nets_by_level.resize(mux_graph.num_node_levels()); - for (size_t level = 0; level < mux_graph.num_node_levels(); ++level) { - /* Print the internal wires located at this level */ - module_nets_by_level[level].resize(mux_graph.num_nodes_at_level(level)); - } - - /* Build the location map of intermediate buffers */ - std::vector inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, circuit_model, mux_graph.num_node_levels()); - - /* Add all the branch modules and intermediate buffers */ - for (const auto& node : mux_graph.non_input_nodes()) { - /* Get the size of branch circuit - * Instanciate an branch circuit by the size (fan-in) of the node - */ - size_t branch_size = mux_graph.node_in_edges(node).size(); - - /* Instanciate the branch module which is a tgate-based module - */ - std::string branch_module_name= generate_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix); - /* Get the moduleId for the submodule */ - ModuleId branch_module_id = module_manager.find_module(branch_module_name); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != branch_module_id); - - /* Find the instance id */ - size_t branch_instance_id = module_manager.num_instance(mux_module, branch_module_id); - /* Add the module to mux_module */ - module_manager.add_child_module(mux_module, branch_module_id); - - /* Get the node level and index in the current level */ - size_t output_node_level = mux_graph.node_level(node); - size_t output_node_index_at_level = mux_graph.node_index_at_level(node); - /* Set a name for the instance */ - std::string branch_instance_name = generate_mux_branch_instance_name(output_node_level, output_node_index_at_level, false); - module_manager.set_child_instance_name(mux_module, branch_module_id, branch_instance_id, branch_instance_name); - - /* Get the output port id of branch module */ - ModulePortId branch_module_output_port_id = module_manager.find_module_port(branch_module_id, std::string("out")); - BasicPort branch_module_output_port = module_manager.module_port(branch_module_id, branch_module_output_port_id); - - /* Add module nets to wire to next stage modules */ - ModuleNetId branch_net; - if (true == mux_graph.is_node_output(node)) { - /* This is an output node, we should use existing output nets */ - MuxOutputId output_id = mux_graph.output_id(node); - branch_net = mux_module_output_nets[output_id]; - } else { - VTR_ASSERT(false == mux_graph.is_node_output(node)); - branch_net = module_manager.create_module_net(mux_module); - } - module_manager.add_module_net_source(mux_module, branch_net, branch_module_id, branch_instance_id, branch_module_output_port_id, branch_module_output_port.get_lsb()); - - /* Record the module net id in the cache */ - module_nets_by_level[output_node_level][output_node_index_at_level] = branch_net; - - /* Wire the branch module memory ports to the nets of MUX memory ports */ - /* Get the mems in the branch circuits */ - std::vector mems; - for (const auto& edge : mux_graph.node_in_edges(node)) { - /* Get the mem control the edge */ - MuxMemId mem = mux_graph.find_edge_mem(edge); - /* Add the mem if it is not in the list */ - if (mems.end() == std::find(mems.begin(), mems.end(), mem)) { - mems.push_back(mem); - } - } - - /* Get mem/mem_inv ports of branch module */ - ModulePortId branch_module_mem_port_id = module_manager.find_module_port(branch_module_id, std::string("mem")); - BasicPort branch_module_mem_port = module_manager.module_port(branch_module_id, branch_module_mem_port_id); - ModulePortId branch_module_mem_inv_port_id = module_manager.find_module_port(branch_module_id, std::string("mem_inv")); - BasicPort branch_module_mem_inv_port = module_manager.module_port(branch_module_id, branch_module_mem_inv_port_id); - - /* Note that we do NOT care inverted edge-to-mem connection. - * It is handled in branch module generation!!! - */ - /* Connect mem/mem_inv to mem/mem_inv net one by one */ - for (size_t mem_id = 0; mem_id < mems.size(); ++mem_id) { - module_manager.add_module_net_sink(mux_module, mux_module_mem_nets[mems[mem_id]], branch_module_id, branch_instance_id, branch_module_mem_port_id, branch_module_mem_port.pins()[mem_id]); - module_manager.add_module_net_sink(mux_module, mux_module_mem_inv_nets[mems[mem_id]], branch_module_id, branch_instance_id, branch_module_mem_inv_port_id, branch_module_mem_inv_port.pins()[mem_id]); - } - - /* Wire the branch module inputs to the nets in previous stage */ - /* Get the input port id of branch module */ - ModulePortId branch_module_input_port_id = module_manager.find_module_port(branch_module_id, std::string("in")); - BasicPort branch_module_input_port = module_manager.module_port(branch_module_id, branch_module_input_port_id); - - /* Get the nodes which drive the root_node */ - std::vector input_nodes; - for (const auto& edge : mux_graph.node_in_edges(node)) { - /* Get the nodes drive the edge */ - for (const auto& src_node : mux_graph.edge_src_nodes(edge)) { - input_nodes.push_back(src_node); - } - } - /* Number of inputs should match the branch_input_size!!! */ - VTR_ASSERT(input_nodes.size() == branch_size); - /* build the link between input_node and branch circuit input_port[0] - */ - for (size_t node_id = 0; node_id < input_nodes.size(); ++node_id) { - /* Find the port info of each input node */ - size_t input_node_level = mux_graph.node_level(input_nodes[node_id]); - size_t input_node_index_at_level = mux_graph.node_index_at_level(input_nodes[node_id]); - /* For inputs of mux, the net id is reserved */ - if (true == mux_graph.is_node_input(input_nodes[node_id])) { - /* Get node input id */ - MuxInputId input_id = mux_graph.input_id(input_nodes[node_id]); - module_manager.add_module_net_sink(mux_module, mux_module_input_nets[input_id], branch_module_id, branch_instance_id, branch_module_input_port_id, branch_module_input_port.pins()[node_id]); - } else { - VTR_ASSERT (false == mux_graph.is_node_input(input_nodes[node_id])); - module_manager.add_module_net_sink(mux_module, module_nets_by_level[input_node_level][input_node_index_at_level], branch_module_id, branch_instance_id, branch_module_input_port_id, branch_module_input_port.pins()[node_id]); - } - } - - /* Identify if an intermediate buffer is needed */ - if (false == inter_buffer_location_map[output_node_level]) { - continue; - } - /* Add an intermediate buffer to mux_module if needed */ - if (true == mux_graph.is_node_output(node)) { - /* Output node does not need buffer addition here, it is handled outside this function */ - continue; - } - /* Now we need to add intermediate buffers by instanciating the modules */ - CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model); - /* We must have a valid model id */ - VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - - ModuleNetId buffer_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, branch_net); - - /* Record the module net id in the cache */ - module_nets_by_level[output_node_level][output_node_index_at_level] = buffer_net; - } -} - -/********************************************************************* - * This function will add nets and input buffers (if needed) - * to a mux module - * Module net represents the connections when there are no input buffers - * mux_input_net[0] - * | - * v +------------ - * mux_in[0] ----------->| - * | - * | - * | - * | Multiplexing - * mux_input_net[i] | Structure - * | | - * v | - * mux_in[0] ----------->| - * | - * - * - * Module net represents the connections when there are input buffers - * mux_input_net[0] - * | - * +-----------------+ v +------------ - * mux_in[0] ----->| input_buffer[0] |-----> | - * +-----------------+ | - * | - * ... | - * | Multiplexing - * mux_input_net[i] | Structure - * | | - * +-----------------+ v | - * mux_in[0] ----->| input_buffer[0] |-----> | - * +-----------------+ | - *********************************************************************/ -static -vtr::vector build_mux_module_input_buffers(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const ModuleId& mux_module, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph) { - vtr::vector mux_input_nets(mux_graph.num_inputs(), ModuleNetId::INVALID()); - - /* Get the input ports from the mux */ - std::vector mux_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); - /* We should have only 1 input port! */ - VTR_ASSERT(1 == mux_input_ports.size()); - - /* Get the input port from MUX module */ - ModulePortId module_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_input_ports[0])); - VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); - /* Get the port from module */ - BasicPort module_input_port = module_manager.module_port(mux_module, module_input_port_id); - - /* Iterate over all the inputs in the MUX graph */ - for (const auto& input_node : mux_graph.inputs()) { - /* Fetch fundamental information from MUX graph w.r.t. the input node */ - MuxInputId input_index = mux_graph.input_id(input_node); - VTR_ASSERT(MuxInputId::INVALID() != input_index); - - /* For last input: - * Add a constant value to the last input, if this MUX needs a constant input - */ - if ( (MuxInputId(mux_graph.num_inputs() - 1) == mux_graph.input_id(input_node)) - && (true == circuit_lib.mux_add_const_input(mux_model)) ) { - /* Get the constant input value */ - size_t const_value = circuit_lib.mux_const_input_value(mux_model); - VTR_ASSERT( (0 == const_value) || (1 == const_value) ); - /* Instanciate a VDD module (default module) - * and build a net between VDD and the MUX input - */ - /* Get the moduleId for the buffer module */ - ModuleId const_val_module_id = module_manager.find_module(generate_const_value_module_name(const_value)); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != const_val_module_id); - size_t const_val_instance = module_manager.num_instance(mux_module, const_val_module_id); - module_manager.add_child_module(mux_module, const_val_module_id); - ModulePortId const_port_id = module_manager.find_module_port(const_val_module_id, generate_const_value_module_output_port_name(const_value)); - - ModuleNetId input_net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_source(mux_module, input_net, const_val_module_id, const_val_instance, const_port_id, 0); - mux_input_nets[input_index] = input_net; - continue; - } - - /* When we do not need any buffer, create a net for the input directly */ - if (false == circuit_lib.is_input_buffered(mux_model)) { - ModuleNetId input_net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_source(mux_module, input_net, mux_module, 0, module_input_port_id, size_t(input_index)); - mux_input_nets[input_index] = input_net; - continue; - } - - /* Now we need to add intermediate buffers by instanciating the modules */ - CircuitModelId buffer_model = circuit_lib.input_buffer_model(mux_model); - /* We must have a valid model id */ - VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - - /* Connect the module net from branch output to buffer input */ - ModuleNetId buffer_net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_source(mux_module, buffer_net, mux_module, 0, module_input_port_id, size_t(input_index)); - - /* Create a module net which sources from buffer output */ - ModuleNetId input_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, buffer_net); - mux_input_nets[input_index] = input_net; - } - - return mux_input_nets; -} - -/********************************************************************* - * This function will add nets and input buffers (if needed) - * to a mux module - * Module net represents the connections when there are no output buffers - * - * mux_output_net[0] - * ------------+ | - * | v - * |--------> mux_output[0] - * | - * | - * Multiplexer | ... - * Strcuture | - * |--------> mux_output[i] - * | ^ - * | | - * ------------+ mux_output_net[i] - * - * Module net represents the connections when there are output buffers - * - * mux_output_net[0] - * ------------+ | - * | | - * | v +------------------+ - * |------->| output_buffer[0] |------> mux_output[0] - * | +------------------+ - * | - * Multiplexer | ... - * Strcuture | - * | +------------------+ - * |------->| output_buffer[i] |------> mux_output[i] - * | ^ +------------------+ - * | | - * | | - * ------------+ mux_output_net[i] - - * - *********************************************************************/ -static -vtr::vector build_mux_module_output_buffers(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const ModuleId& mux_module, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph) { - - /* Create module nets for output ports */ - vtr::vector mux_output_nets(mux_graph.num_outputs(), ModuleNetId::INVALID()); - - /* Get the output ports from the mux */ - std::vector mux_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); - - /* Iterate over all the outputs in the MUX module */ - for (const auto& output_port : mux_output_ports) { - /* Get the output port from MUX module */ - ModulePortId module_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(output_port)); - VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); - /* Get the port from module */ - BasicPort module_output_port = module_manager.module_port(mux_module, module_output_port_id); - - /* Iterate over each pin of the output port */ - for (const size_t& pin : circuit_lib.pins(output_port)) { - /* Fetch fundamental information from MUX graph w.r.t. the input node */ - /* Deposite the last level of the graph, which is a default value */ - size_t output_node_level = mux_graph.num_node_levels() - 1; - /* If there is a fracturable level specified for the output, we find the exact level */ - if (size_t(-1) != circuit_lib.port_lut_frac_level(output_port)) { - output_node_level = circuit_lib.port_lut_frac_level(output_port); - } - /* Deposite a zero, which is a default value */ - size_t output_node_index_at_level = 0; - /* If there are output masks, we find the node_index */ - if (!circuit_lib.port_lut_output_masks(output_port).empty()) { - output_node_index_at_level = circuit_lib.port_lut_output_masks(output_port).at(pin); - } - /* Double check the node exists in the Mux Graph */ - MuxNodeId node_id = mux_graph.node_id(output_node_level, output_node_index_at_level); - VTR_ASSERT(MuxNodeId::INVALID() != node_id); - MuxOutputId output_index = mux_graph.output_id(node_id); - - /* Create the port information of the module output at the given pin range, which is the output of buffer instance */ - BasicPort instance_output_port(module_output_port.get_name(), pin, pin); - - /* If the output is not supposed to be buffered, create a net for the input directly */ - if (false == circuit_lib.is_output_buffered(mux_model)) { - ModuleNetId output_net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_sink(mux_module, output_net, mux_module, 0, module_output_port_id, pin); - mux_output_nets[output_index] = output_net; - continue; /* Finish here */ - } - - /* Reach here, we need a buffer, create a port-to-port map and output the buffer instance */ - /* Now we need to add intermediate buffers by instanciating the modules */ - CircuitModelId buffer_model = circuit_lib.output_buffer_model(mux_model); - /* We must have a valid model id */ - VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - - /* Create a module net which sinks at buffer input */ - ModuleNetId input_net = module_manager.create_module_net(mux_module); - ModuleNetId output_net = add_inverter_buffer_child_module_and_nets(module_manager, mux_module, circuit_lib, buffer_model, input_net); - module_manager.add_module_net_sink(mux_module, output_net, mux_module, 0, module_output_port_id, pin); - mux_output_nets[output_index] = input_net; - } - } - - return mux_output_nets; -} - -/********************************************************************* - * This function will - * 1. Build local encoders for a MUX module (if specified) - * 2. Build nets between memory ports of a MUX module and branch circuits - * This happens when local encoders are not needed - * - * MUX module - * +--------------------- - * | mux_mem_nets/mux_mem_inv_nets - * | | - * | v +--------- - * mem-+-------->| - * | | Branch Module - * | | - * - * 3. Build nets between local encoders and memory ports of a MUX module - * This happens when local encoders are needed - * 4. Build nets between local encoders and branch circuits - * This happens when local encoders are needed - * - * MUX module - * +--------------------- - * | - * | +-------+ mux_mem_nets/mux_mem_inv_nets - * | | | | - * mem--+------>| | v +--------- - * | | Local |-------->| - * | |Encoder| | Branch - * | | | | Module - * | | | | - * | | | | - * - *********************************************************************/ -static -void build_mux_module_local_encoders_and_memory_nets(ModuleManager& module_manager, - const ModuleId& mux_module, - const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const std::vector& mux_sram_ports, - const MuxGraph& mux_graph, - vtr::vector& mux_mem_nets, - vtr::vector& mux_mem_inv_nets) { - - /* Create nets here, and we will configure the net source later */ - for (size_t mem = 0; mem < mux_graph.num_memory_bits(); ++mem) { - ModuleNetId mem_net = module_manager.create_module_net(mux_module); - mux_mem_nets.push_back(mem_net); - ModuleNetId mem_inv_net = module_manager.create_module_net(mux_module); - mux_mem_inv_nets.push_back(mem_inv_net); - } - - if (false == circuit_lib.mux_use_local_encoder(mux_model)) { - /* Add mem and mem_inv nets here */ - size_t mem_net_cnt = 0; - for (const auto& port : mux_sram_ports) { - ModulePortId mem_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(port)); - BasicPort mem_port = module_manager.module_port(mux_module, mem_port_id); - for (const size_t& pin : mem_port.pins()) { - MuxMemId mem_id = MuxMemId(mem_net_cnt); - /* Set the module net source */ - module_manager.add_module_net_source(mux_module, mux_mem_nets[mem_id], mux_module, 0, mem_port_id, pin); - /* Update counter */ - mem_net_cnt++; - } - } - VTR_ASSERT(mem_net_cnt == mux_graph.num_memory_bits()); - - /* Add mem and mem_inv nets here */ - size_t mem_inv_net_cnt = 0; - for (const auto& port : mux_sram_ports) { - ModulePortId mem_inv_port_id = module_manager.find_module_port(mux_module, std::string(circuit_lib.port_prefix(port) + "_inv")); - BasicPort mem_inv_port = module_manager.module_port(mux_module, mem_inv_port_id); - for (const size_t& pin : mem_inv_port.pins()) { - MuxMemId mem_id = MuxMemId(mem_inv_net_cnt); - /* Set the module net source */ - module_manager.add_module_net_source(mux_module, mux_mem_inv_nets[mem_id], mux_module, 0, mem_inv_port_id, pin); - /* Update counter */ - mem_inv_net_cnt++; - } - } - VTR_ASSERT(mem_inv_net_cnt == mux_graph.num_memory_bits()); - return; /* Finish here if local encoders are not required */ - } - - /* Add local decoder instance here */ - VTR_ASSERT(true == circuit_lib.mux_use_local_encoder(mux_model)); - BasicPort decoder_data_port(generate_mux_local_decoder_data_port_name(), mux_graph.num_memory_bits()); - BasicPort decoder_data_inv_port(generate_mux_local_decoder_data_inv_port_name(), mux_graph.num_memory_bits()); - - /* Local port to record the LSB and MSB of each level, here, we deposite (0, 0) */ - ModulePortId mux_module_sram_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0])); - ModulePortId mux_module_sram_inv_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_sram_ports[0]) + "_inv"); - BasicPort lvl_addr_port(circuit_lib.port_prefix(mux_sram_ports[0]), 0); - BasicPort lvl_data_port(decoder_data_port.get_name(), 0); - BasicPort lvl_data_inv_port(decoder_data_inv_port.get_name(), 0); - - /* Counter for mem index */ - size_t mem_net_cnt = 0; - size_t mem_inv_net_cnt = 0; - - for (const auto& lvl : mux_graph.levels()) { - size_t addr_size = find_mux_local_decoder_addr_size(mux_graph.num_memory_bits_at_level(lvl)); - size_t data_size = mux_graph.num_memory_bits_at_level(lvl); - /* Update the LSB and MSB of addr and data port for the current level */ - lvl_addr_port.rotate(addr_size); - lvl_data_port.rotate(data_size); - lvl_data_inv_port.rotate(data_size); - - /* Exception: if the data size is one, we just need wires! */ - if (1 == data_size) { - for (size_t pin_id = 0; pin_id < lvl_addr_port.pins().size(); ++pin_id) { - MuxMemId mem_id = MuxMemId(mem_net_cnt); - /* Set the module net source */ - module_manager.add_module_net_source(mux_module, mux_mem_nets[mem_id], mux_module, 0, mux_module_sram_port_id, lvl_addr_port.pins()[pin_id]); - /* Update counter */ - mem_net_cnt++; - - MuxMemId mem_inv_id = MuxMemId(mem_inv_net_cnt); - /* Set the module net source */ - module_manager.add_module_net_source(mux_module, mux_mem_inv_nets[mem_inv_id], mux_module, 0, mux_module_sram_inv_port_id, lvl_addr_port.pins()[pin_id]); - /* Update counter */ - mem_inv_net_cnt++; - } - continue; - } - - std::string decoder_module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size); - ModuleId decoder_module = module_manager.find_module(decoder_module_name); - VTR_ASSERT(ModuleId::INVALID() != decoder_module); - - size_t decoder_instance = module_manager.num_instance(mux_module, decoder_module); - module_manager.add_child_module(mux_module, decoder_module); - - /* Add module nets to connect sram ports of MUX to address port */ - ModulePortId decoder_module_addr_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_addr_port_name()); - BasicPort decoder_module_addr_port = module_manager.module_port(decoder_module, decoder_module_addr_port_id); - VTR_ASSERT(decoder_module_addr_port.get_width() == lvl_addr_port.get_width()); - - /* Build pin-to-pin net connection */ - for (size_t pin_id = 0; pin_id < lvl_addr_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(mux_module); - module_manager.add_module_net_source(mux_module, net, mux_module, 0, mux_module_sram_port_id, lvl_addr_port.pins()[pin_id]); - module_manager.add_module_net_sink(mux_module, net, decoder_module, decoder_instance, decoder_module_addr_port_id, decoder_module_addr_port.pins()[pin_id]); - } - - /* Add module nets to connect data port to MUX mem ports */ - ModulePortId decoder_module_data_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_data_port_name()); - BasicPort decoder_module_data_port = module_manager.module_port(decoder_module, decoder_module_data_port_id); - - /* Build pin-to-pin net connection */ - for (const size_t& pin : decoder_module_data_port.pins()) { - ModuleNetId net = mux_mem_nets[MuxMemId(mem_net_cnt)]; - module_manager.add_module_net_source(mux_module, net, decoder_module, decoder_instance, decoder_module_data_port_id, pin); - /* Add the module nets to mux_mem_nets cache */ - mem_net_cnt++; - } - - ModulePortId decoder_module_data_inv_port_id = module_manager.find_module_port(decoder_module, generate_mux_local_decoder_data_inv_port_name()); - BasicPort decoder_module_data_inv_port = module_manager.module_port(decoder_module, decoder_module_data_inv_port_id); - - /* Build pin-to-pin net connection */ - for (const size_t& pin : decoder_module_data_inv_port.pins()) { - ModuleNetId net = mux_mem_inv_nets[MuxMemId(mem_inv_net_cnt)]; - module_manager.add_module_net_source(mux_module, net, decoder_module, decoder_instance, decoder_module_data_inv_port_id, pin); - /* Add the module nets to mux_mem_inv_nets cache */ - mem_inv_net_cnt++; - } - } - VTR_ASSERT(mem_net_cnt == mux_graph.num_memory_bits()); - VTR_ASSERT(mem_inv_net_cnt == mux_graph.num_memory_bits()); -} - -/********************************************************************* - * Generate module of a CMOS multiplexer with the given size - * The module will consist of three parts: - * 1. instances of the branch circuits of multiplexers which are generated before - * This builds up the multiplexing structure - * 2. Input buffers/inverters - * 3. Output buffers/inverters - *********************************************************************/ -static -void build_cmos_mux_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const std::string& module_name, - const MuxGraph& mux_graph) { - /* Get the global ports required by MUX (and any submodules) */ - std::vector mux_global_ports = circuit_lib.model_global_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true, true); - /* Get the input ports from the mux */ - std::vector mux_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); - /* Get the output ports from the mux */ - std::vector mux_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Get the sram ports from the mux - * Multiplexing structure does not mode_sram_ports, they are handled in LUT modules - * Here we just bypass it. - */ - std::vector mux_sram_ports = find_circuit_regular_sram_ports(circuit_lib, mux_model); - - /* Generate the Verilog netlist according to the mux_graph */ - /* Find out the number of data-path inputs */ - size_t num_inputs = find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()); - /* Find out the number of outputs */ - size_t num_outputs = mux_graph.num_outputs(); - /* Find out the number of memory bits */ - size_t num_mems = mux_graph.num_memory_bits(); - - /* The size of of memory ports depend on - * if a local encoder is used for the mux or not - * Multiplexer local encoders are applied to memory bits at each stage - */ - if (true == circuit_lib.mux_use_local_encoder(mux_model)) { - num_mems = 0; - for (const auto& lvl : mux_graph.levels()) { - size_t data_size = mux_graph.num_memory_bits_at_level(lvl); - num_mems += find_mux_local_decoder_addr_size(data_size); - } - } - - /* Check codes to ensure the port of Verilog netlists will match */ - /* MUX graph must have only 1 output */ - VTR_ASSERT(1 == mux_input_ports.size()); - /* A quick check on the model ports */ - if ((SPICE_MODEL_MUX == circuit_lib.model_type(mux_model)) - || ((SPICE_MODEL_LUT == circuit_lib.model_type(mux_model)) - && (false == circuit_lib.is_lut_fracturable(mux_model))) ) { - VTR_ASSERT(1 == mux_output_ports.size()); - VTR_ASSERT(1 == circuit_lib.port_size(mux_output_ports[0])); - } else { - VTR_ASSERT_SAFE( (SPICE_MODEL_LUT == circuit_lib.model_type(mux_model)) - && (true == circuit_lib.is_lut_fracturable(mux_model)) ); - for (const auto& port : mux_output_ports) { - VTR_ASSERT(0 < circuit_lib.port_size(port)); - } - } - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId mux_module = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != mux_module); - /* Add module ports */ - /* Add each input port - * Treat MUX and LUT differently - * 1. MUXes: we do not have a specific input/output sizes, it is inferred by architecture - * 2. LUTes: we do have specific input/output sizes, - * but the inputs of MUXes are the SRAM ports of LUTs - * and the SRAM ports of MUXes are the inputs of LUTs - */ - size_t input_port_cnt = 0; - for (const auto& port : mux_input_ports) { - BasicPort input_port(circuit_lib.port_prefix(port), num_inputs); - module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT); - /* Update counter */ - input_port_cnt++; - } - /* Double check: We should have only 1 input port generated here! */ - VTR_ASSERT(1 == input_port_cnt); - - /* Add input buffers and update module nets for inputs */ - vtr::vector mux_input_nets = build_mux_module_input_buffers(module_manager, circuit_lib, mux_module, mux_model, mux_graph); - - for (const auto& port : mux_output_ports) { - BasicPort output_port(circuit_lib.port_prefix(port), num_outputs); - if (SPICE_MODEL_LUT == circuit_lib.model_type(mux_model)) { - output_port.set_width(circuit_lib.port_size(port)); - } - module_manager.add_port(mux_module, output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - /* TODO: Add output buffers and update module nets for outputs */ - vtr::vector mux_output_nets = build_mux_module_output_buffers(module_manager, circuit_lib, mux_module, mux_model, mux_graph); - - size_t sram_port_cnt = 0; - for (const auto& port : mux_sram_ports) { - BasicPort mem_port(circuit_lib.port_prefix(port), num_mems); - module_manager.add_port(mux_module, mem_port, ModuleManager::MODULE_INPUT_PORT); - BasicPort mem_inv_port(std::string(circuit_lib.port_prefix(port) + "_inv"), num_mems); - module_manager.add_port(mux_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT); - /* Update counter */ - sram_port_cnt++; - } - VTR_ASSERT(1 == sram_port_cnt); - - /* Create module nets for mem and mem_inv ports */ - vtr::vector mux_mem_nets; - vtr::vector mux_mem_inv_nets; - - build_mux_module_local_encoders_and_memory_nets(module_manager, mux_module, - circuit_lib, mux_model, mux_sram_ports, - mux_graph, - mux_mem_nets, mux_mem_inv_nets); - - /* Print the internal logic in Verilog codes */ - /* Print the Multiplexing structure in Verilog codes - * Separated generation strategy on using standard cell MUX2 or TGATE, - * 1. MUX2 has a fixed port map: input_port[0] and input_port[1] is the data_path input - * 2. Branch TGATE-based module has a fixed port name - * TODO: the naming could be more flexible? - */ - /* Get the tgate model */ - CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(mux_model); - /* Instanciate the branch module: - * Case 1: the branch module is a standard cell MUX2 - * Case 2: the branch module is a tgate-based module - */ - std::string branch_module_name; - if (SPICE_MODEL_GATE == circuit_lib.model_type(tgate_model)) { - VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model)); - build_cmos_mux_module_mux2_multiplexing_structure(module_manager, circuit_lib, mux_module, mux_model, tgate_model, mux_input_nets, mux_output_nets, mux_mem_nets, mux_graph); - } else { - VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_lib.model_type(tgate_model)); - build_cmos_mux_module_tgate_multiplexing_structure(module_manager, circuit_lib, mux_module, mux_model, mux_input_nets, mux_output_nets, mux_mem_nets, mux_mem_inv_nets, mux_graph); - } - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, mux_module); -} - -/********************************************************************* - * Generate a module of a RRAM-based multiplexer with the given size - * The module will consist of three parts: - * 1. instances of the branch circuits of multiplexers which are generated before - * This builds up the 4T1R-based multiplexing structure - * - * BLB WL - * | | ... - * v v - * +--------+ - * in[0]-->| | BLB WL - * ...| Branch |-----+ | | - * in -->| 0 | | v v - * [N-1] +--------+ | +--------+ - * ... -->| | - * BLBs WLs ...| Branch | - * | | ... -->| X | - * v v +--------+ - * +--------+ | - * -->| | | - * ...| Branch |----+ - * -->| i | - * +--------+ - * - * 2. Input buffers/inverters - * 3. Output buffers/inverters - *********************************************************************/ -static -void build_rram_mux_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const std::string& module_name, - const MuxGraph& mux_graph) { - /* Error out for the conditions where we are not yet supported! */ - if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { - /* RRAM LUT is not supported now... */ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])RRAM-based LUT is not supported (Circuit model: %s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - - /* Get the global ports required by MUX (and any submodules) */ - std::vector mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); - /* Get the input ports from the mux */ - std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - /* Get the output ports from the mux */ - std::vector mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Get the BL and WL ports from the mux */ - std::vector mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_BLB, true); - std::vector mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_WL, true); - - /* Generate the Verilog netlist according to the mux_graph */ - /* Find out the number of data-path inputs */ - size_t num_inputs = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); - /* Find out the number of outputs */ - size_t num_outputs = mux_graph.num_outputs(); - /* Find out the number of memory bits */ - size_t num_mems = mux_graph.num_memory_bits(); - - /* Check codes to ensure the port of Verilog netlists will match */ - /* MUX graph must have only 1 input and 1 BLB and 1 WL port */ - VTR_ASSERT(1 == mux_input_ports.size()); - VTR_ASSERT(1 == mux_blb_ports.size()); - VTR_ASSERT(1 == mux_wl_ports.size()); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != module_id); - /* Add module ports */ - /* Add each global port */ - for (const auto& port : mux_global_ports) { - /* Configure each global port */ - BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); - } - /* Add each input port */ - size_t input_port_cnt = 0; - for (const auto& port : mux_input_ports) { - BasicPort input_port(circuit_lib.port_prefix(port), num_inputs); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - /* Update counter */ - input_port_cnt++; - } - /* Double check: We should have only 1 input port generated here! */ - VTR_ASSERT(1 == input_port_cnt); - - for (const auto& port : mux_output_ports) { - BasicPort output_port(circuit_lib.port_prefix(port), num_outputs); - if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { - output_port.set_width(circuit_lib.port_size(port)); - } - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - /* BLB port */ - for (const auto& port : mux_blb_ports) { - /* IMPORTANT: RRAM-based MUX has an additional BLB pin per level - * So, the actual port width of BLB should be added by the number of levels of the MUX graph - */ - BasicPort blb_port(circuit_lib.port_prefix(port), num_mems + mux_graph.num_levels()); - module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT); - } - - /* WL port */ - for (const auto& port : mux_wl_ports) { - /* IMPORTANT: RRAM-based MUX has an additional WL pin per level - * So, the actual port width of WL should be added by the number of levels of the MUX graph - */ - BasicPort wl_port(circuit_lib.port_prefix(port), num_mems + mux_graph.num_levels()); - module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT); - } - - /* TODO: Add the input and output buffers in Verilog codes */ - - /* TODO: Print the internal logic in Verilog codes */ -} - -/*********************************************** - * Generate Verilog codes modeling a multiplexer - * with the given graph-level description - **********************************************/ -static -void build_mux_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const MuxGraph& mux_graph) { - std::string module_name = generate_mux_subckt_name(circuit_lib, circuit_model, - find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()), - std::string("")); - - /* Multiplexers built with different technology is in different organization */ - switch (circuit_lib.design_tech_type(circuit_model)) { - case SPICE_MODEL_DESIGN_CMOS: - /* SRAM-based Multiplexer Verilog module generation */ - build_cmos_mux_module(module_manager, circuit_lib, circuit_model, module_name, mux_graph); - break; - case SPICE_MODEL_DESIGN_RRAM: - /* TODO: RRAM-based Multiplexer Verilog module generation */ - build_rram_mux_module(module_manager, circuit_lib, circuit_model, module_name, mux_graph); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } -} - - -/*********************************************** - * Generate Verilog modules for all the unique - * multiplexers in the FPGA device - **********************************************/ -void build_mux_modules(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib) { - /* Start time count */ - clock_t t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, - "Building multiplexer modules..."); - - /* Generate basis sub-circuit for unique branches shared by the multiplexers */ - for (auto mux : mux_lib.muxes()) { - const MuxGraph& mux_graph = mux_lib.mux_graph(mux); - CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); - /* Create a mux graph for the branch circuit */ - std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); - /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */ - for (auto branch_mux_graph : branch_mux_graphs) { - build_mux_branch_module(module_manager, circuit_lib, mux_circuit_model, - find_mux_num_datapath_inputs(circuit_lib, mux_circuit_model, mux_graph.num_inputs()), - branch_mux_graph); - } - } - - /* Generate unique Verilog modules for the multiplexers */ - for (auto mux : mux_lib.muxes()) { - const MuxGraph& mux_graph = mux_lib.mux_graph(mux); - CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); - /* Create MUX circuits */ - build_mux_module(module_manager, circuit_lib, mux_circuit_model, mux_graph); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %.2g seconds\n", - run_time_sec); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.h deleted file mode 100644 index 7b65b56b9..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.h +++ /dev/null @@ -1,19 +0,0 @@ -/*********************************************** - * Header file for verilog_mux.cpp - **********************************************/ - -#ifndef BUILD_MUX_MODULES_H -#define BUILD_MUX_MODULES_H - -/* Include other header files which are dependency on the function declared below */ -#include "spice_types.h" -#include "circuit_library.h" -#include "mux_graph.h" -#include "mux_library.h" -#include "module_manager.h" - -void build_mux_modules(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.cpp deleted file mode 100644 index 37330d557..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.cpp +++ /dev/null @@ -1,207 +0,0 @@ -/******************************************************************** - * This file includes most utilized functions that are used to build modules - * for global routing architecture of a FPGA fabric - * Covering: - * 1. Connection blocks - * 2. Switch blocks - *******************************************************************/ -#include "vtr_assert.h" -#include "vtr_geometry.h" -#include "device_coordinator.h" - -#include "fpga_x2p_naming.h" - -#include "build_routing_module_utils.h" - -/********************************************************************* - * Generate a port for a routing track of a swtich block - ********************************************************************/ -ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const e_side& chan_side, - t_rr_node* cur_rr_node, - const PORTS& cur_rr_node_direction) { - /* Get the index in sb_info of cur_rr_node */ - int index = rr_gsb.get_node_index(cur_rr_node, chan_side, cur_rr_node_direction); - /* Make sure this node is included in this sb_info */ - VTR_ASSERT((-1 != index)&&(NUM_SIDES != chan_side)); - - DeviceCoordinator chan_rr_node_coordinator = rr_gsb.get_side_block_coordinator(chan_side); - - vtr::Point chan_port_coord(chan_rr_node_coordinator.get_x(), chan_rr_node_coordinator.get_y()); - std::string chan_port_name = generate_sb_module_track_port_name(rr_gsb.get_chan_node(chan_side, index)->type, - chan_side, index, - rr_gsb.get_chan_node_direction(chan_side, index)); - - /* Must find a valid port id in the Switch Block module */ - ModulePortId chan_port_id = module_manager.find_module_port(sb_module, chan_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, chan_port_id)); - return chan_port_id; -} - -/********************************************************************* - * Generate an input port for routing multiplexer inside the switch block - * In addition to give the Routing Resource node of the input - * Users should provide the side of input, which is different case by case: - * 1. When the input is a pin of a CLB/Logic Block, the input_side should - * be the side of the node on its grid! - * For example, the input pin is on the top side of a switch block - * but on the right side of a switch block - * +--------+ - * | | - * | Grid |---+ - * | | | - * +--------+ v input_pin - * +----------------+ - * | Switch Block | - * +----------------+ - * 2. When the input is a routing track, the input_side should be - * the side of the node locating on the switch block - ********************************************************************/ -ModulePortId find_switch_block_module_input_port(const ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const e_side& input_side, - t_rr_node* input_rr_node) { - /* Deposit an invalid value */ - ModulePortId input_port_id = ModulePortId::INVALID(); - /* Generate the input port object */ - switch (input_rr_node->type) { - /* case SOURCE: */ - case OPIN: { - /* Find the coordinator (grid_x and grid_y) for the input port */ - vtr::Point input_port_coord(input_rr_node->xlow, input_rr_node->ylow); - - /* Find the side where the grid pin locates in the grid */ - enum e_side grid_pin_side = rr_gsb.get_opin_node_grid_side(input_rr_node); - VTR_ASSERT(NUM_SIDES != grid_pin_side); - - std::string input_port_name = generate_sb_module_grid_port_name(input_side, - grid_pin_side, - input_rr_node->ptc_num); - /* Must find a valid port id in the Switch Block module */ - input_port_id = module_manager.find_module_port(sb_module, input_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, input_port_id)); - break; - } - case CHANX: - case CHANY: { - input_port_id = find_switch_block_module_chan_port(module_manager, sb_module, - rr_gsb, input_side, input_rr_node, IN_PORT); - break; - } - default: /* SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - - return input_port_id; -} - -/********************************************************************* - * Generate a list of input ports for routing multiplexer inside the switch block - ********************************************************************/ -std::vector find_switch_block_module_input_ports(const ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const std::vector& input_rr_nodes) { - std::vector input_ports; - - for (auto input_rr_node : input_rr_nodes) { - /* Find the side where the input locates in the Switch Block */ - enum e_side input_pin_side = NUM_SIDES; - /* The input could be at any side of the switch block, find it */ - int index = -1; - rr_gsb.get_node_side_and_index(input_rr_node, IN_PORT, &input_pin_side, &index); - VTR_ASSERT(NUM_SIDES != input_pin_side); - VTR_ASSERT(-1 != index); - - input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, rr_gsb, input_pin_side, input_rr_node)); - } - - return input_ports; -} - -/********************************************************************* - * Generate an input port for routing multiplexer inside the connection block - * which is the middle output of a routing track - ********************************************************************/ -ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - t_rr_node* chan_rr_node) { - ModulePortId input_port_id; - /* Generate the input port object */ - switch (chan_rr_node->type) { - case CHANX: - case CHANY: { - /* Create port description for the routing track middle output */ - vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - int chan_node_track_id = rr_gsb.get_cb_chan_node_index(cb_type, chan_rr_node); - /* Create a port description for the middle output */ - std::string input_port_name = generate_cb_module_track_port_name(cb_type, - chan_node_track_id, - IN_PORT); - /* Must find a valid port id in the Switch Block module */ - input_port_id = module_manager.find_module_port(cb_module, input_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, input_port_id)); - break; - } - default: /* OPIN, SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - - return input_port_id; -} - -/********************************************************************* - * Generate a port for a routing track of a swtich block - ********************************************************************/ -ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - t_rr_node* src_rr_node) { - - /* Ensure the src_rr_node is an input pin of a CLB */ - VTR_ASSERT(IPIN == src_rr_node->type); - /* Create port description for input pin of a CLB */ - vtr::Point port_coord(src_rr_node->xlow, src_rr_node->ylow); - /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ - enum e_side cb_ipin_side = NUM_SIDES; - int cb_ipin_index = -1; - rr_gsb.get_node_side_and_index(src_rr_node, OUT_PORT, &cb_ipin_side, &cb_ipin_index); - /* We need to be sure that drive_rr_node is part of the CB */ - VTR_ASSERT((-1 != cb_ipin_index)&&(NUM_SIDES != cb_ipin_side)); - std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side, - rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)->ptc_num); - - /* Must find a valid port id in the Switch Block module */ - ModulePortId ipin_port_id = module_manager.find_module_port(cb_module, port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, ipin_port_id)); - return ipin_port_id; -} - -/********************************************************************* - * Generate a list of routing track middle output ports - * for routing multiplexer inside the connection block - ********************************************************************/ -std::vector find_connection_block_module_input_ports(const ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const std::vector& input_rr_nodes) { - std::vector input_ports; - - for (auto input_rr_node : input_rr_nodes) { - input_ports.push_back(find_connection_block_module_chan_port(module_manager, cb_module, rr_gsb, cb_type, input_rr_node)); - } - - return input_ports; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.h deleted file mode 100644 index 4d7eaafb0..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_module_utils.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef BUILD_ROUTING_MODULE_UTILS_H -#define BUILD_ROUTING_MODULE_UTILS_H - -#include -#include "rr_blocks.h" -#include "module_manager.h" -#include "sides.h" -#include "vpr_types.h" - -ModulePortId find_switch_block_module_chan_port(const ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const e_side& chan_side, - t_rr_node* cur_rr_node, - const PORTS& cur_rr_node_direction); - -ModulePortId find_switch_block_module_input_port(const ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const e_side& input_side, - t_rr_node* input_rr_node); - -std::vector find_switch_block_module_input_ports(const ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const std::vector& input_rr_nodes); - -ModulePortId find_connection_block_module_chan_port(const ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - t_rr_node* chan_rr_node); - -ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - t_rr_node* src_rr_node); - -std::vector find_connection_block_module_input_ports(const ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const std::vector& input_rr_nodes); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp deleted file mode 100644 index e9a61383e..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ /dev/null @@ -1,975 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to build modules - * for global routing architecture of a FPGA fabric - * Covering: - * 1. Connection blocks - * 2. Switch blocks - *******************************************************************/ -#include -#include - -#include "vtr_assert.h" -#include "vtr_geometry.h" -#include "sides.h" -#include "util.h" -#include "device_coordinator.h" - -#include "fpga_x2p_reserved_words.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_naming.h" - -#include "fpga_x2p_utils.h" -#include "module_manager_utils.h" -#include "build_module_graph_utils.h" -#include "build_routing_module_utils.h" - -#include "build_routing_modules.h" -#include "verilog_global.h" - -/********************************************************************* - * Generate a short interconneciton in switch box - * There are two cases should be noticed. - * 1. The actual fan-in of cur_rr_node is 0. In this case, - the cur_rr_node need to be short connected to itself - which is on the opposite side of this switch block - * 2. The actual fan-in of cur_rr_node is 0. In this case, - * The cur_rr_node need to connected to the drive_rr_node - ********************************************************************/ -static -void build_switch_block_module_short_interc(ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const e_side& chan_side, - t_rr_node* cur_rr_node, - t_rr_node* drive_rr_node, - const std::map& input_port_to_module_nets) { - /* Find the name of output port */ - ModulePortId output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_gsb, chan_side, cur_rr_node, OUT_PORT); - enum e_side input_pin_side = chan_side; - int index = -1; - - /* Generate the input port object */ - switch (drive_rr_node->type) { - case OPIN: { - rr_gsb.get_node_side_and_index(drive_rr_node, IN_PORT, &input_pin_side, &index); - break; - } - case CHANX: - case CHANY: { - /* This should be an input in the data structure of RRGSB */ - if (cur_rr_node == drive_rr_node) { - /* To be strict, the input should locate on the opposite side. - * Use the else part if this may change in some architecture. - */ - Side side_manager(chan_side); - input_pin_side = side_manager.get_opposite(); - } else { - /* The input could be at any side of the switch block, find it */ - rr_gsb.get_node_side_and_index(drive_rr_node, IN_PORT, &input_pin_side, &index); - } - break; - } - default: /* SOURCE, IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - /* Find the name of input port */ - ModulePortId input_port_id = find_switch_block_module_input_port(module_manager, sb_module, rr_gsb, input_pin_side, drive_rr_node); - - /* The input port and output port must match in size */ - BasicPort input_port = module_manager.module_port(sb_module, input_port_id); - BasicPort output_port = module_manager.module_port(sb_module, output_port_id); - VTR_ASSERT(input_port.get_width() == output_port.get_width()); - - /* Create a module net for this short-wire connection */ - for (size_t pin_id = 0; pin_id < input_port.pins().size(); ++pin_id) { - ModuleNetId net = input_port_to_module_nets.at(input_port_id); - /* Skip Configuring the net source, it is done before */ - /* Configure the net sink */ - module_manager.add_module_net_sink(sb_module, net, sb_module, 0, output_port_id, output_port.pins()[pin_id]); - } -} - -/********************************************************************* - * Build a instance of a routing multiplexer as well as - * associated memory modules for a connection inside a switch block - ********************************************************************/ -static -void build_switch_block_mux_module(ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const CircuitLibrary& circuit_lib, - const std::vector& rr_switches, - const e_side& chan_side, - const size_t& chan_node_id, - t_rr_node* cur_rr_node, - const std::vector& drive_rr_nodes, - const size_t& switch_index, - const std::map& input_port_to_module_nets) { - /* Check current rr_node is CHANX or CHANY*/ - VTR_ASSERT((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); - - /* Get the circuit model id of the routing multiplexer */ - CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - - /* Find the input size of the implementation of a routing multiplexer */ - size_t datapath_mux_size = drive_rr_nodes.size(); - - /* Find the module name of the multiplexer and try to find it in the module manager */ - std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); - ModuleId mux_module = module_manager.find_module(mux_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); - - /* Get the MUX instance id from the module manager */ - size_t mux_instance_id = module_manager.num_instance(sb_module, mux_module); - /* Instanciate the MUX Module */ - module_manager.add_child_module(sb_module, mux_module); - - /* Give an instance name: this name should be consistent with the block name given in SDC manager, - * If you want to bind the SDC generation to modules - */ - std::string mux_instance_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MUX_INSTANCE_PREFIX, chan_side, chan_node_id, std::string("")); - module_manager.set_child_instance_name(sb_module, mux_module, mux_instance_id, mux_instance_name); - - /* Generate input ports that are wired to the input bus of the routing multiplexer */ - std::vector sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, rr_gsb, drive_rr_nodes); - - /* Link input bus port to Switch Block inputs */ - std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); - VTR_ASSERT(1 == mux_model_input_ports.size()); - /* Find the module port id of the input port */ - ModulePortId mux_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_input_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_input_port_id)); - BasicPort mux_input_port = module_manager.module_port(mux_module, mux_input_port_id); - - /* Check port size should match */ - VTR_ASSERT(mux_input_port.get_width() == sb_input_port_ids.size()); - for (size_t pin_id = 0; pin_id < sb_input_port_ids.size(); ++pin_id) { - /* Use the exising net */ - ModuleNetId net = input_port_to_module_nets.at(sb_input_port_ids[pin_id]); - /* Configure the net source only if it is not yet in the source list */ - if (false == module_manager.net_source_exist(sb_module, net, sb_module, 0, sb_input_port_ids[pin_id], 0)) { - module_manager.add_module_net_source(sb_module, net, sb_module, 0, sb_input_port_ids[pin_id], 0); - } - /* Configure the net sink */ - module_manager.add_module_net_sink(sb_module, net, mux_module, mux_instance_id, mux_input_port_id, mux_input_port.pins()[pin_id]); - } - - /* Link output port to Switch Block outputs */ - std::vector mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == mux_model_output_ports.size()); - /* Use the port name convention in the circuit library */ - ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_output_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id)); - BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id); - ModulePortId sb_output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_gsb, chan_side, cur_rr_node, OUT_PORT); - BasicPort sb_output_port = module_manager.module_port(sb_module, sb_output_port_id); - - /* Check port size should match */ - VTR_ASSERT(sb_output_port.get_width() == mux_output_port.get_width()); - for (size_t pin_id = 0; pin_id < mux_output_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(sb_module); - /* Configuring the net source */ - module_manager.add_module_net_source(sb_module, net, mux_module, mux_instance_id, mux_output_port_id, mux_output_port.pins()[pin_id]); - /* Configure the net sink */ - module_manager.add_module_net_sink(sb_module, net, sb_module, 0, sb_output_port_id, sb_output_port.pins()[pin_id]); - } - - /* Instanciate memory modules */ - /* Find the name and module id of the memory module */ - std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); - ModuleId mem_module = module_manager.find_module(mem_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); - - size_t mem_instance_id = module_manager.num_instance(sb_module, mem_module); - module_manager.add_child_module(sb_module, mem_module); - /* Give an instance name: this name should be consistent with the block name given in bitstream manager, - * If you want to bind the bitstream generation to modules - */ - std::string mem_instance_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MEM_INSTANCE_PREFIX, chan_side, chan_node_id, std::string("")); - module_manager.set_child_instance_name(sb_module, mem_module, mem_instance_id, mem_instance_name); - - /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ - add_module_nets_between_logic_and_memory_sram_bus(module_manager, sb_module, - mux_module, mux_instance_id, - mem_module, mem_instance_id, - circuit_lib, mux_model); - /* Update memory and instance list */ - module_manager.add_configurable_child(sb_module, mem_module, mem_instance_id); -} - -/********************************************************************* - * Generate child modules for a interconnection inside switch block - * The interconnection could be either a wire or a routing multiplexer, - * which depends on the fan-in of the rr_nodes in the switch block - ********************************************************************/ -static -void build_switch_block_interc_modules(ModuleManager& module_manager, - const ModuleId& sb_module, - const RRGSB& rr_gsb, - const CircuitLibrary& circuit_lib, - const std::vector& rr_switches, - const e_side& chan_side, - const size_t& chan_node_id, - const std::map& input_port_to_module_nets) { - std::vector drive_rr_nodes; - - /* Get the node */ - t_rr_node* cur_rr_node = rr_gsb.get_chan_node(chan_side, chan_node_id); - - /* Determine if the interc lies inside a channel wire, that is interc between segments */ - if (false == rr_gsb.is_sb_node_passing_wire(chan_side, chan_node_id)) { - for (int i = 0; i < cur_rr_node->num_drive_rr_nodes; ++i) { - drive_rr_nodes.push_back(cur_rr_node->drive_rr_nodes[i]); - } - /* Special: if there are zero-driver nodes. We skip here */ - if (0 == drive_rr_nodes.size()) { - return; - } - } - - if (0 == drive_rr_nodes.size()) { - /* Print a special direct connection*/ - build_switch_block_module_short_interc(module_manager, sb_module, - rr_gsb, chan_side, cur_rr_node, - cur_rr_node, - input_port_to_module_nets); - } else if (1 == drive_rr_nodes.size()) { - /* Print a direct connection*/ - build_switch_block_module_short_interc(module_manager, sb_module, - rr_gsb, chan_side, cur_rr_node, - drive_rr_nodes[DEFAULT_SWITCH_ID], - input_port_to_module_nets); - } else if (1 < drive_rr_nodes.size()) { - /* Print the multiplexer, fan_in >= 2 */ - build_switch_block_mux_module(module_manager, - sb_module, rr_gsb, circuit_lib, - rr_switches, chan_side, chan_node_id, cur_rr_node, - drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], - input_port_to_module_nets); - } /*Nothing should be done else*/ -} - - -/******************************************************************** - * Build a module for a switch block whose detailed description is - * available in a RRGSB object - * A Switch Box module consists of following ports: - * 1. Channel Y [x][y] inputs - * 2. Channel X [x+1][y] inputs - * 3. Channel Y [x][y-1] outputs - * 4. Channel X [x][y] outputs - * 5. Grid[x][y+1] Right side outputs pins - * 6. Grid[x+1][y+1] Left side output pins - * 7. Grid[x+1][y+1] Bottom side output pins - * 8. Grid[x+1][y] Top side output pins - * 9. Grid[x+1][y] Left side output pins - * 10. Grid[x][y] Right side output pins - * 11. Grid[x][y] Top side output pins - * 12. Grid[x][y+1] Bottom side output pins - * - * Location of a Switch Box in FPGA fabric: - * - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - * - * Switch Block pin location map - * - * Grid[x][y+1] ChanY[x][y+1] Grid[x+1][y+1] - * right_pins inputs/outputs left_pins - * | ^ | - * | | | - * v v v - * +-----------------------------------------------+ - * | | - * Grid[x][y+1] | | Grid[x+1][y+1] - * bottom_pins---->| |<---- bottom_pins - * | | - * ChanX[x][y] | Switch Box [x][y] | ChanX[x+1][y] - * inputs/outputs<--->| |<---> inputs/outputs - * | | - * Grid[x][y+1] | | Grid[x+1][y+1] - * top_pins---->| |<---- top_pins - * | | - * +-----------------------------------------------+ - * ^ ^ ^ - * | | | - * | v | - * Grid[x][y] ChanY[x][y] Grid[x+1][y] - * right_pins inputs/outputs left_pins - * - * - ********************************************************************/ -static -void build_switch_block_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::vector& rr_switches, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const RRGSB& rr_gsb) { - /* Create a Module of Switch Block and add to module manager */ - vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - ModuleId sb_module = module_manager.add_module(generate_switch_block_module_name(gsb_coordinate)); - - /* Create a cache (fast look up) for module nets whose source are input ports */ - std::map input_port_to_module_nets; - - /* Add routing channel ports at each side of the GSB */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - DeviceCoordinator port_coordinator = rr_gsb.get_side_block_coordinator(side_manager.get_side()); - - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - vtr::Point port_coord(port_coordinator.get_x(), port_coordinator.get_y()); - std::string port_name = generate_sb_module_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type, - side_manager.get_side(), itrack, - rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)); - BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ - - switch (rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - case OUT_PORT: - module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); - break; - case IN_PORT: { - ModulePortId input_port_id = module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_INPUT_PORT); - /* Cache the input net */ - ModuleNetId net = module_manager.create_module_net(sb_module); - module_manager.add_module_net_source(sb_module, net, sb_module, 0, input_port_id, 0); - input_port_to_module_nets[input_port_id] = net; - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File: %s [LINE%d]) Invalid direction of chan[%d][%d]_track[%d]!\n", - __FILE__, __LINE__, rr_gsb.get_sb_x(), rr_gsb.get_sb_y(), itrack); - exit(1); - } - } - /* Dump OPINs of adjacent CLBs */ - for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - vtr::Point port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow); - std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(), - rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), - rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num); - BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ - /* Grid outputs are inputs of switch blocks */ - ModulePortId input_port_id = module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_INPUT_PORT); - - /* Cache the input net */ - ModuleNetId net = module_manager.create_module_net(sb_module); - module_manager.add_module_net_source(sb_module, net, sb_module, 0, input_port_id, 0); - input_port_to_module_nets[input_port_id] = net; - } - } - - /* Add routing multiplexers as child modules */ - for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { - Side side_manager(side); - for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) { - /* We care INC_DIRECTION tracks at this side*/ - if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { - build_switch_block_interc_modules(module_manager, - sb_module, rr_gsb, - circuit_lib, rr_switches, - side_manager.get_side(), - itrack, - input_port_to_module_nets); - } - } - } - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, sb_module); - - /* Count shared SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, sb_module); - if (0 < module_num_shared_config_bits) { - add_reserved_sram_ports_to_module_manager(module_manager, sb_module, module_num_shared_config_bits); - } - - /* Count SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, sb_module, circuit_lib, sram_model, sram_orgz_type); - if (0 < module_num_config_bits) { - add_sram_ports_to_module_manager(module_manager, sb_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits); - } - - /* Add all the nets to connect configuration ports from memory module to primitive modules - * This is a one-shot addition that covers all the memory modules in this primitive module! - */ - if (0 < module_manager.configurable_children(sb_module).size()) { - add_module_nets_memory_config_bus(module_manager, sb_module, - sram_orgz_type, circuit_lib.design_tech_type(sram_model)); - } -} - -/********************************************************************* - * Print a short interconneciton in connection - ********************************************************************/ -static -void build_connection_block_module_short_interc(ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - t_rr_node* src_rr_node, - const std::map& input_port_to_module_nets) { - /* Ensure we have only one 1 driver node */ - VTR_ASSERT_SAFE(1 == src_rr_node->fan_in); - - /* Find the driver node */ - t_rr_node* drive_rr_node = src_rr_node->drive_rr_nodes[0]; - - /* We have OPINs since we may have direct connections: - * These connections should be handled by other functions in the compact_netlist.c - * So we just return here for OPINs - */ - if (OPIN == drive_rr_node->type) { - return; - } - - VTR_ASSERT((CHANX == drive_rr_node->type) || (CHANY == drive_rr_node->type)); - - /* Create port description for the routing track middle output */ - ModulePortId input_port_id = find_connection_block_module_chan_port(module_manager, cb_module, rr_gsb, cb_type, drive_rr_node); - - /* Create port description for input pin of a CLB */ - ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_gsb, src_rr_node); - - /* The input port and output port must match in size */ - BasicPort input_port = module_manager.module_port(cb_module, input_port_id); - BasicPort ipin_port = module_manager.module_port(cb_module, ipin_port_id); - VTR_ASSERT(input_port.get_width() == ipin_port.get_width()); - - /* Create a module net for this short-wire connection */ - for (size_t pin_id = 0; pin_id < input_port.pins().size(); ++pin_id) { - ModuleNetId net = input_port_to_module_nets.at(input_port_id); - /* Skip Configuring the net source, it is done before */ - /* Configure the net sink */ - module_manager.add_module_net_sink(cb_module, net, cb_module, 0, ipin_port_id, ipin_port.pins()[pin_id]); - } -} - -/********************************************************************* - * Build a instance of a routing multiplexer as well as - * associated memory modules for a connection inside a connection block - ********************************************************************/ -static -void build_connection_block_mux_module(ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const CircuitLibrary& circuit_lib, - const std::vector& rr_switches, - const e_side& cb_ipin_side, - const size_t& ipin_index, - const std::map& input_port_to_module_nets) { - t_rr_node* cur_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index); - /* Check current rr_node is an input pin of a CLB */ - VTR_ASSERT(IPIN == cur_rr_node->type); - - /* Build a vector of driver rr_nodes */ - std::vector drive_rr_nodes; - for (int inode = 0; inode < cur_rr_node->num_drive_rr_nodes; inode++) { - drive_rr_nodes.push_back(cur_rr_node->drive_rr_nodes[inode]); - } - - int switch_index = cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]; - - /* Get the circuit model id of the routing multiplexer */ - CircuitModelId mux_model = rr_switches[switch_index].circuit_model; - - /* Find the input size of the implementation of a routing multiplexer */ - size_t datapath_mux_size = drive_rr_nodes.size(); - - /* Find the module name of the multiplexer and try to find it in the module manager */ - std::string mux_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string("")); - ModuleId mux_module = module_manager.find_module(mux_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mux_module)); - - /* Get the MUX instance id from the module manager */ - size_t mux_instance_id = module_manager.num_instance(cb_module, mux_module); - module_manager.add_child_module(cb_module, mux_module); - - /* Give an instance name: this name should be consistent with the block name given in SDC manager, - * If you want to bind the SDC generation to modules - */ - std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), ipin_index, std::string("")); - module_manager.set_child_instance_name(cb_module, mux_module, mux_instance_id, mux_instance_name); - - /* TODO: Generate input ports that are wired to the input bus of the routing multiplexer */ - std::vector cb_input_port_ids = find_connection_block_module_input_ports(module_manager, cb_module, rr_gsb, cb_type, drive_rr_nodes); - - /* Link input bus port to Switch Block inputs */ - std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_INPUT, true); - VTR_ASSERT(1 == mux_model_input_ports.size()); - /* Find the module port id of the input port */ - ModulePortId mux_input_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_input_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_input_port_id)); - BasicPort mux_input_port = module_manager.module_port(mux_module, mux_input_port_id); - - /* Check port size should match */ - VTR_ASSERT(mux_input_port.get_width() == cb_input_port_ids.size()); - for (size_t pin_id = 0; pin_id < cb_input_port_ids.size(); ++pin_id) { - /* Use the exising net */ - ModuleNetId net = input_port_to_module_nets.at(cb_input_port_ids[pin_id]); - /* No need to configure the net source since it is already done before */ - /* Configure the net sink */ - module_manager.add_module_net_sink(cb_module, net, mux_module, mux_instance_id, mux_input_port_id, mux_input_port.pins()[pin_id]); - } - - /* Link output port to Switch Block outputs */ - std::vector mux_model_output_ports = circuit_lib.model_ports_by_type(mux_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == mux_model_output_ports.size()); - /* Use the port name convention in the circuit library */ - ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_output_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id)); - BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id); - ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_gsb, cur_rr_node); - BasicPort cb_output_port = module_manager.module_port(cb_module, cb_output_port_id); - - /* Check port size should match */ - VTR_ASSERT(cb_output_port.get_width() == mux_output_port.get_width()); - for (size_t pin_id = 0; pin_id < mux_output_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(cb_module); - /* Configuring the net source */ - module_manager.add_module_net_source(cb_module, net, mux_module, mux_instance_id, mux_output_port_id, mux_output_port.pins()[pin_id]); - /* Configure the net sink */ - module_manager.add_module_net_sink(cb_module, net, cb_module, 0, cb_output_port_id, cb_output_port.pins()[pin_id]); - } - - /* Instanciate memory modules */ - /* Find the name and module id of the memory module */ - std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX)); - ModuleId mem_module = module_manager.find_module(mem_module_name); - VTR_ASSERT (true == module_manager.valid_module_id(mem_module)); - - size_t mem_instance_id = module_manager.num_instance(cb_module, mem_module); - module_manager.add_child_module(cb_module, mem_module); - - /* Give an instance name: this name should be consistent with the block name given in bitstream manager, - * If you want to bind the bitstream generation to modules - */ - std::string mem_instance_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, ipin_index), ipin_index, std::string("")); - module_manager.set_child_instance_name(cb_module, mem_module, mem_instance_id, mem_instance_name); - - /* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */ - add_module_nets_between_logic_and_memory_sram_bus(module_manager, cb_module, - mux_module, mux_instance_id, - mem_module, mem_instance_id, - circuit_lib, mux_model); - /* Update memory and instance list */ - module_manager.add_configurable_child(cb_module, mem_module, mem_instance_id); -} - -/******************************************************************** - * Print internal connections of a connection block - * For a IPIN node that is driven by only 1 fan-in, - * a short wire will be created - * For a IPIN node that is driven by more than two fan-ins, - * a routing multiplexer will be instanciated - ********************************************************************/ -static -void build_connection_block_interc_modules(ModuleManager& module_manager, - const ModuleId& cb_module, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const CircuitLibrary& circuit_lib, - const std::vector& rr_switches, - const e_side& cb_ipin_side, - const size_t& ipin_index, - const std::map& input_port_to_module_nets) { - t_rr_node* src_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index); - if (1 > src_rr_node->fan_in) { - return; /* This port has no driver, skip it */ - } else if (1 == src_rr_node->fan_in) { - /* Print a direct connection */ - build_connection_block_module_short_interc(module_manager, cb_module, rr_gsb, cb_type, src_rr_node, input_port_to_module_nets); - - } else if (1 < src_rr_node->fan_in) { - /* Print the multiplexer, fan_in >= 2 */ - build_connection_block_mux_module(module_manager, - cb_module, rr_gsb, cb_type, - circuit_lib, rr_switches, - cb_ipin_side, ipin_index, - input_port_to_module_nets); - } /*Nothing should be done else*/ -} - -/******************************************************************** - * Generate a module of a connection Box (Type: [CHANX|CHANY]) - * Actually it is very similiar to switch box but - * the difference is connection boxes connect Grid INPUT Pins to channels - * NOTE: direct connection between CLBs should NOT be included inside this - * module! They should be added in the top-level module as their connection - * is not limited to adjacent CLBs!!! - * - * Location of a X- and Y-direction Connection Block in FPGA fabric - * +------------+ +-------------+ - * | |------>| | - * | CLB |<------| Y-direction | - * | | ... | Connection | - * | |------>| Block | - * +------------+ +-------------+ - * | ^ ... | | ^ ... | - * v | v v | v - * +-------------------+ +-------------+ - * --->| |--->| | - * <---| X-direction |<---| Switch | - * ...| Connection block |... | Block | - * --->| |--->| | - * +-------------------+ +-------------+ - * - * Internal structure: - * This is an example of a X-direction connection block - * Note that middle output ports are shorted wire from inputs of routing tracks, - * which are also the inputs of routing multiplexer of the connection block - * - * CLB Input Pins - * (IPINs) - * ^ ^ ^ - * | | ... | - * +--------------------------+ - * | ^ ^ ^ | - * | | | ... | | - * | +--------------------+ | - * | | routing | | - * | | multiplexers | | - * | +--------------------+ | - * | middle outputs | - * | of routing channel | - * | ^ ^ ^ ^ ^ ^ ^ ^ | - * | | | | | ... | | | | | - * in[0] -->|------------------------->|---> out[0] - * out[1] <--|<-------------------------|<--- in[1] - * | ... | - * in[W-2] -->|------------------------->|---> out[W-2] - * out[W-1] <--|<-------------------------|<--- in[W-1] - * +--------------------------+ - * - * W: routing channel width - * - ********************************************************************/ -static -void build_connection_block_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::vector& rr_switches, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const RRGSB& rr_gsb, - const t_rr_type& cb_type) { - /* Create the netlist */ - vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId cb_module = module_manager.add_module(generate_connection_block_module_name(cb_type, gsb_coordinate)); - - /* Add the input and output ports of routing tracks in the channel - * Routing tracks pass through the connection blocks - */ - for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { - vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - std::string port_name = generate_cb_module_track_port_name(cb_type, - itrack, - IN_PORT); - BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ - module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_INPUT_PORT); - } - for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { - vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - std::string port_name = generate_cb_module_track_port_name(cb_type, - itrack, - OUT_PORT); - BasicPort module_port(port_name, 1); /* Every track has a port size of 1 */ - module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - /* Add the input pins of grids, which are output ports of the connection block */ - std::vector cb_ipin_sides = rr_gsb.get_cb_ipin_sides(cb_type); - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - t_rr_node* ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); - vtr::Point port_coord(ipin_node->xlow, ipin_node->ylow); - std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side, - ipin_node->ptc_num); - BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ - /* Grid outputs are inputs of switch blocks */ - module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); - } - } - - /* Create a cache (fast look up) for module nets whose source are input ports */ - std::map input_port_to_module_nets; - - /* Generate short-wire connection for each routing track : - * Each input port is short-wired to its output port and middle output port - * - * in[i] ----------> out[i] - * | - * +-----> mid_out[i] - */ - for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { - vtr::Point port_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - /* Create a port description for the input */ - std::string input_port_name = generate_cb_module_track_port_name(cb_type, - itrack, - IN_PORT); - ModulePortId input_port_id = module_manager.find_module_port(cb_module, input_port_name); - BasicPort input_port = module_manager.module_port(cb_module, input_port_id); - - /* Create a port description for the output */ - std::string output_port_name = generate_cb_module_track_port_name(cb_type, - itrack, - OUT_PORT); - ModulePortId output_port_id = module_manager.find_module_port(cb_module, output_port_name); - BasicPort output_port = module_manager.module_port(cb_module, output_port_id); - - /* Ensure port size matching */ - VTR_ASSERT(1 == input_port.get_width()); - VTR_ASSERT(input_port.get_width() == output_port.get_width()); - - /* Create short-wires: input port ---> output port - * Do short-wires: input port ---> middle output port - */ - for (size_t pin_id = 0; pin_id < input_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(cb_module); - module_manager.add_module_net_source(cb_module, net, cb_module, 0, input_port_id, input_port.pins()[pin_id]); - module_manager.add_module_net_sink(cb_module, net, cb_module, 0, output_port_id, output_port.pins()[pin_id]); - /* Cache the module net */ - input_port_to_module_nets[input_port_id] = net; - } - } - - /* Add sub modules of routing multiplexers or direct interconnect*/ - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - build_connection_block_interc_modules(module_manager, - cb_module, rr_gsb, cb_type, - circuit_lib, rr_switches, - cb_ipin_side, inode, - input_port_to_module_nets); - } - } - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, cb_module); - - /* Count shared SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, cb_module); - if (0 < module_num_shared_config_bits) { - add_reserved_sram_ports_to_module_manager(module_manager, cb_module, module_num_shared_config_bits); - } - - /* Count SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, cb_module, circuit_lib, sram_model, sram_orgz_type); - if (0 < module_num_config_bits) { - add_sram_ports_to_module_manager(module_manager, cb_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits); - } - - /* Add all the nets to connect configuration ports from memory module to primitive modules - * This is a one-shot addition that covers all the memory modules in this primitive module! - */ - if (0 < module_manager.configurable_children(cb_module).size()) { - add_module_nets_memory_config_bus(module_manager, cb_module, - sram_orgz_type, circuit_lib.design_tech_type(sram_model)); - } -} - - -/******************************************************************** - * Iterate over all the connection blocks in a device - * and build a module for each of them - *******************************************************************/ -static -void build_flatten_connection_block_modules(ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const CircuitLibrary& circuit_lib, - const std::vector& rr_switches, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const t_rr_type& cb_type) { - /* Build unique X-direction connection block modules */ - DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); - - for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { - /* Check if the connection block exists in the device! - * Some of them do NOT exist due to heterogeneous blocks (height > 1) - * We will skip those modules - */ - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - if (false == rr_gsb.is_cb_exist(cb_type)) { - continue; - } - build_connection_block_module(module_manager, - circuit_lib, - rr_switches, - sram_orgz_type, sram_model, - rr_gsb, cb_type); - } - } -} - -/******************************************************************** - * A top-level function of this file - * Build all the modules for global routing architecture of a FPGA fabric - * in a flatten way: - * Each connection block and switch block will be generated as a unique module - * Covering: - * 1. Connection blocks - * 2. Switch blocks - *******************************************************************/ -void build_flatten_routing_modules(ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const t_det_routing_arch& routing_arch, - const std::vector& rr_switches) { - /* Start time count */ - clock_t t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, - "Building routing modules..."); - - /* We only support uni-directional routing architecture now */ - VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); - - /* TODO: deprecate DeviceCoordinator, use vtr::Point only! */ - DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); - - /* Build unique switch block modules */ - for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - build_switch_block_module(module_manager, circuit_lib, - rr_switches, - sram_orgz_type, sram_model, - rr_gsb); - } - } - - build_flatten_connection_block_modules(module_manager, L_device_rr_gsb, - circuit_lib, - rr_switches, - sram_orgz_type, sram_model, - CHANX); - - build_flatten_connection_block_modules(module_manager, L_device_rr_gsb, - circuit_lib, - rr_switches, - sram_orgz_type, sram_model, - CHANY); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %.2g seconds\n", - run_time_sec); -} - -/******************************************************************** - * A top-level function of this file - * Build all the unique modules for global routing architecture of a FPGA fabric - * This function will use unique module list built in device_rr_gsb, - * to build only unique modules (in terms of graph connections) of - * 1. Connection blocks - * 2. Switch blocks - * - * Note: this function SHOULD be called only when - * the option compact_routing_hierarchy is turned on!!! - *******************************************************************/ -void build_unique_routing_modules(ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const t_det_routing_arch& routing_arch, - const std::vector& rr_switches) { - /* Start time count */ - clock_t t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, - "Building unique routing modules..."); - - /* We only support uni-directional routing architecture now */ - VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); - - /* Build unique switch block modules */ - for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(isb); - build_switch_block_module(module_manager, circuit_lib, - rr_switches, - sram_orgz_type, sram_model, - unique_mirror); - } - - /* Build unique X-direction connection block modules */ - for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANX, icb); - - build_connection_block_module(module_manager, - circuit_lib, - rr_switches, - sram_orgz_type, sram_model, - unique_mirror, CHANX); - } - - /* Build unique X-direction connection block modules */ - for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANY, icb); - - build_connection_block_module(module_manager, - circuit_lib, - rr_switches, - sram_orgz_type, sram_model, - unique_mirror, CHANY); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %.2g seconds\n", - run_time_sec); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.h deleted file mode 100644 index 49eae0f1e..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.h +++ /dev/null @@ -1,31 +0,0 @@ -/******************************************************************** - * Header file for build_routing_modules.cpp - *******************************************************************/ -#ifndef BUILD_ROUTING_MODULES_H -#define BUILD_ROUTING_MODULES_H - -#include "spice_types.h" -#include "vpr_types.h" -#include "rr_blocks.h" -#include "mux_library.h" -#include "circuit_library.h" -#include "module_manager.h" - -void build_flatten_routing_modules(ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const t_det_routing_arch& routing_arch, - const std::vector& rr_switches); - -void build_unique_routing_modules(ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const t_det_routing_arch& routing_arch, - const std::vector& rr_switches); - - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp deleted file mode 100644 index 98e47f75b..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ /dev/null @@ -1,380 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to print the top-level - * module for the FPGA fabric in Verilog format - *******************************************************************/ -#include -#include -#include - -#include "vtr_assert.h" - -#include "vpr_types.h" -#include "globals.h" - -#include "rr_blocks_utils.h" -#include "fpga_x2p_reserved_words.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "module_manager_utils.h" -#include "build_top_module_utils.h" -#include "build_top_module_connection.h" -#include "build_top_module_memory.h" -#include "build_top_module_directs.h" - -#include "verilog_global.h" -#include "build_module_graph_utils.h" -#include "build_top_module.h" - -/******************************************************************** - * Add a instance of a grid module to the top module - *******************************************************************/ -static -size_t add_top_module_grid_instance(ModuleManager& module_manager, - const ModuleId& top_module, - t_type_ptr grid_type, - const e_side& border_side, - const vtr::Point& grid_coord) { - /* Find the module name for this type of grid */ - std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); - std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side); - ModuleId grid_module = module_manager.find_module(grid_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); - /* Record the instance id */ - size_t grid_instance = module_manager.num_instance(top_module, grid_module); - /* Add the module to top_module */ - module_manager.add_child_module(top_module, grid_module); - /* Set an unique name to the instance - * Note: it is your risk to gurantee the name is unique! - */ - std::string instance_name = generate_grid_block_instance_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, border_side, grid_coord); - module_manager.set_child_instance_name(top_module, grid_module, grid_instance, instance_name); - - return grid_instance; -} - -/******************************************************************** - * Add all the grids as sub-modules across the fabric - * The grid modules are created for each unique type of grid (based - * on the type in data structure data_structure - * Here, we will iterate over the full fabric (coordinates) - * and instanciate the grid modules - * - * Return an 2-D array of instance ids of the grid modules that - * have been added - * - * This function assumes an island-style floorplanning for FPGA fabric - * - * - * +-----------------------------------+ - * | I/O grids | - * | TOP side | - * +-----------------------------------+ - * - * +-----------+ +-----------------------------------+ +------------+ - * | | | | | | - * | I/O grids | | Core grids | | I/O grids | - * | LEFT side | | (CLB, Heterogeneous blocks, etc.) | | RIGHT side | - * | | | | | | - * +-----------+ +-----------------------------------+ +------------+ - * - * +-----------------------------------+ - * | I/O grids | - * | BOTTOM side | - * +-----------------------------------+ - * - *******************************************************************/ -static -std::vector> add_top_module_grid_instances(ModuleManager& module_manager, - const ModuleId& top_module, - const vtr::Point& device_size, - const std::vector>& grids) { - /* Reserve an array for the instance ids */ - std::vector> grid_instance_ids; - grid_instance_ids.resize(grids.size()); - for (size_t x = 0; x < grids.size(); ++x) { - /* Deposite an invalid value */ - grid_instance_ids[x].resize(grids[x].size(), size_t(-1)); - } - - /* Instanciate core grids */ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grids[ix][iy].type) { - continue; - } - /* Skip height > 1 tiles (mostly heterogeneous blocks) */ - if (0 < grids[ix][iy].offset) { - continue; - } - /* We should not meet any I/O grid */ - VTR_ASSERT(IO_TYPE != grids[ix][iy].type); - /* Add a grid module to top_module*/ - vtr::Point grid_coord(ix, iy); - grid_instance_ids[ix][iy] = add_top_module_grid_instance(module_manager, top_module, - grids[ix][iy].type, - NUM_SIDES, grid_coord); - } - } - - /* Instanciate I/O grids */ - /* Create the coordinate range for each side of FPGA fabric */ - std::vector io_sides{TOP, RIGHT, BOTTOM, LEFT}; - std::map>> io_coordinates; - - /* TOP side*/ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - io_coordinates[TOP].push_back(vtr::Point(ix, device_size.y() - 1)); - } - - /* RIGHT side */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - io_coordinates[RIGHT].push_back(vtr::Point(device_size.x() - 1, iy)); - } - - /* BOTTOM side*/ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - io_coordinates[BOTTOM].push_back(vtr::Point(ix, 0)); - } - - /* LEFT side */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - io_coordinates[LEFT].push_back(vtr::Point(0, iy)); - } - - /* Add instances of I/O grids to top_module */ - for (const e_side& io_side : io_sides) { - for (const vtr::Point& io_coordinate : io_coordinates[io_side]) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type) { - continue; - } - /* Skip height > 1 tiles (mostly heterogeneous blocks) */ - if (0 < grids[io_coordinate.x()][io_coordinate.y()].offset) { - continue; - } - /* We should not meet any I/O grid */ - VTR_ASSERT(IO_TYPE == grids[io_coordinate.x()][io_coordinate.y()].type); - /* Add a grid module to top_module*/ - grid_instance_ids[io_coordinate.x()][io_coordinate.y()] = add_top_module_grid_instance(module_manager, top_module, grids[io_coordinate.x()][io_coordinate.y()].type, io_side, io_coordinate); - } - } - - return grid_instance_ids; -} - -/******************************************************************** - * Add switch blocks across the FPGA fabric to the top-level module - * Return an 2-D array of instance ids of the switch blocks that - * have been added - *******************************************************************/ -static -std::vector> add_top_module_switch_block_instances(ModuleManager& module_manager, - const ModuleId& top_module, - const DeviceRRGSB& L_device_rr_gsb, - const bool& compact_routing_hierarchy) { - /* TODO: deprecate DeviceCoordinator, use vtr::Point only! */ - DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); - - /* Reserve an array for the instance ids */ - std::vector> sb_instance_ids; - sb_instance_ids.resize(sb_range.get_x()); - for (size_t x = 0; x < sb_range.get_x(); ++x) { - /* Deposite an invalid value */ - sb_instance_ids[x].resize(sb_range.get_y(), size_t(-1)); - } - - for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - vtr::Point sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - if (true == compact_routing_hierarchy) { - DeviceCoordinator sb_coord(ix, iy); - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord); - sb_coordinate.set_x(unique_mirror.get_sb_x()); - sb_coordinate.set_y(unique_mirror.get_sb_y()); - } - std::string sb_module_name = generate_switch_block_module_name(sb_coordinate); - ModuleId sb_module = module_manager.find_module(sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); - /* Record the instance id */ - sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()] = module_manager.num_instance(top_module, sb_module); - /* Add the module to top_module */ - module_manager.add_child_module(top_module, sb_module); - /* Set an unique name to the instance - * Note: it is your risk to gurantee the name is unique! - */ - module_manager.set_child_instance_name(top_module, sb_module, - sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()], - generate_switch_block_module_name(vtr::Point(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()))); - } - } - - return sb_instance_ids; -} - -/******************************************************************** - * Add switch blocks across the FPGA fabric to the top-level module - *******************************************************************/ -static -std::vector> add_top_module_connection_block_instances(ModuleManager& module_manager, - const ModuleId& top_module, - const DeviceRRGSB& L_device_rr_gsb, - const t_rr_type& cb_type, - const bool& compact_routing_hierarchy) { - DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); - - /* Reserve an array for the instance ids */ - std::vector> cb_instance_ids; - cb_instance_ids.resize(cb_range.get_x()); - for (size_t x = 0; x < cb_range.get_x(); ++x) { - /* Deposite an invalid value */ - cb_instance_ids[x].resize(cb_range.get_y(), size_t(-1)); - } - - for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { - /* Check if the connection block exists in the device! - * Some of them do NOT exist due to heterogeneous blocks (height > 1) - * We will skip those modules - */ - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - vtr::Point cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - if ( false == rr_gsb.is_cb_exist(cb_type) ) { - continue; - } - /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ - if (true == compact_routing_hierarchy) { - DeviceCoordinator cb_coord(ix, iy); - /* Note: use GSB coordinate when inquire for unique modules!!! */ - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); - cb_coordinate.set_x(unique_mirror.get_cb_x(cb_type)); - cb_coordinate.set_y(unique_mirror.get_cb_y(cb_type)); - } - std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coordinate); - ModuleId cb_module = module_manager.find_module(cb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); - /* Record the instance id */ - cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)] = module_manager.num_instance(top_module, cb_module); - /* Add the module to top_module */ - module_manager.add_child_module(top_module, cb_module); - /* Set an unique name to the instance - * Note: it is your risk to gurantee the name is unique! - */ - std::string cb_instance_name = generate_connection_block_module_name(cb_type, vtr::Point(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))); - module_manager.set_child_instance_name(top_module, cb_module, - cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)], - cb_instance_name); - } - } - - return cb_instance_ids; -} - -/******************************************************************** - * Print the top-level module for the FPGA fabric in Verilog format - * This function will - * 1. name the top-level module - * 2. include dependent netlists - * - User defined netlists - * - Auto-generated netlists - * 3. Add the submodules to the top-level graph - * 4. Add module nets to connect datapath ports - * 5. Add module nets/submodules to connect configuration ports - *******************************************************************/ -void build_top_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector& clb2clb_directs, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const bool& compact_routing_hierarchy, - const bool& duplicate_grid_pin) { - /* Start time count */ - clock_t t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, - "Building FPGA fabric module..."); - - /* Create a module as the top-level fabric, and add it to the module manager */ - std::string top_module_name = generate_fpga_top_module_name(); - ModuleId top_module = module_manager.add_module(top_module_name); - - std::map>> cb_instance_ids; - - /* Add sub modules, which are grid, SB and CBX/CBY modules as instances */ - /* Add all the grids across the fabric */ - std::vector> grid_instance_ids = add_top_module_grid_instances(module_manager, top_module, device_size, grids); - /* Add all the SBs across the fabric */ - std::vector> sb_instance_ids = add_top_module_switch_block_instances(module_manager, top_module, L_device_rr_gsb, compact_routing_hierarchy); - /* Add all the CBX and CBYs across the fabric */ - cb_instance_ids[CHANX] = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANX, compact_routing_hierarchy); - cb_instance_ids[CHANY] = add_top_module_connection_block_instances(module_manager, top_module, L_device_rr_gsb, CHANY, compact_routing_hierarchy); - - /* Add module nets to connect the sub modules */ - add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module, - device_size, grids, grid_instance_ids, - L_device_rr_gsb, sb_instance_ids, cb_instance_ids, - compact_routing_hierarchy, duplicate_grid_pin); - /* Add inter-CLB direct connections */ - add_top_module_nets_clb2clb_direct_connections(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - clb2clb_directs); - - /* Add global ports to the pb_module: - * This is a much easier job after adding sub modules (instances), - * we just need to find all the global ports from the child modules and build a list of it - */ - add_module_global_ports_from_child_modules(module_manager, top_module); - - /* Add GPIO ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - add_module_gpio_ports_from_child_modules(module_manager, top_module); - - /* Add shared SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, top_module); - if (0 < module_num_shared_config_bits) { - add_reserved_sram_ports_to_module_manager(module_manager, top_module, module_num_shared_config_bits); - } - - /* Add SRAM ports from the sub-modules under this Verilog module - * This is a much easier job after adding sub modules (instances), - * we just need to find all the I/O ports from the child modules and build a list of it - */ - size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, top_module, circuit_lib, sram_model, sram_orgz_type); - if (0 < module_num_config_bits) { - add_sram_ports_to_module_manager(module_manager, top_module, circuit_lib, sram_model, sram_orgz_type, module_num_config_bits); - } - - /* Organize the list of memory modules and instances */ - organize_top_module_memory_modules(module_manager, top_module, - circuit_lib, sram_orgz_type, sram_model, - device_size, grids, grid_instance_ids, - L_device_rr_gsb, sb_instance_ids, cb_instance_ids, - compact_routing_hierarchy); - - /* Add module nets to connect memory cells inside - * This is a one-shot addition that covers all the memory modules in this pb module! - */ - if (0 < module_manager.configurable_children(top_module).size()) { - add_top_module_nets_memory_config_bus(module_manager, top_module, - sram_orgz_type, circuit_lib.design_tech_type(sram_model)); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %.2g seconds\n", - run_time_sec); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.h deleted file mode 100644 index a97156bf7..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.h +++ /dev/null @@ -1,26 +0,0 @@ -/******************************************************************** - * Header file for build_top_module.cpp - *******************************************************************/ -#ifndef BUILD_TOP_MODULE_H -#define BUILD_TOP_MODULE_H - -#include -#include "vtr_geometry.h" -#include "vpr_types.h" -#include "spice_types.h" -#include "rr_blocks.h" -#include "circuit_library.h" -#include "module_manager.h" - -void build_top_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector& clb2clb_directs, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const bool& compact_routing_hierarchy, - const bool& duplicate_grid_pin); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_connection.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_connection.cpp deleted file mode 100644 index 5c5af2627..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_connection.cpp +++ /dev/null @@ -1,647 +0,0 @@ -/******************************************************************** - * This file include most utilized functions for building connections - * inside the module graph for FPGA fabric - *******************************************************************/ -/* External library headers */ -#include "vtr_assert.h" - -/* FPGA-X2P headers */ -#include "fpga_x2p_reserved_words.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "rr_blocks_utils.h" - -/* Module builder headers */ -#include "build_top_module_utils.h" -#include "build_top_module_connection.h" - -/******************************************************************** - * Add module nets to connect a GSB to adjacent grid ports/pins - * as well as connection blocks - * This function will create nets for the following types of connections - * between grid output pins of Switch block and adjacent grids - * In this case, the net source is the grid pin, while the net sink - * is the switch block pin - * - * +------------+ +------------+ - * | | | | - * | Grid | | Grid | - * | [x][y+1] | | [x+1][y+1] | - * | |----+ +----| | - * +------------+ | | +------------+ - * | v v | - * | +------------+ | - * +------>| |<-----+ - * | Switch | - * | Block | - * +------>| [x][y] |<-----+ - * | +------------+ | - * | ^ ^ | - * | | | | - * +------------+ | | +------------+ - * | |----+ +-----| | - * | Grid | | Grid | - * | [x][y] | | [x+1][y] | - * | | | | - * +------------+ +------------+ - - * - *******************************************************************/ -static -void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, - const ModuleId& top_module, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const DeviceRRGSB& L_device_rr_gsb, - const RRGSB& rr_gsb, - const std::vector>& sb_instance_ids, - const bool& compact_routing_hierarchy) { - - /* We could have two different coordinators, one is the instance, the other is the module */ - vtr::Point instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - DeviceCoordinator module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); - - /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ - if (true == compact_routing_hierarchy) { - DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(gsb_coord); - module_gsb_coordinate.set_x(unique_mirror.get_x()); - module_gsb_coordinate.set_y(unique_mirror.get_y()); - } - - /* This is the source cb that is added to the top module */ - const RRGSB& module_sb = L_device_rr_gsb.get_gsb(module_gsb_coordinate); - vtr::Point module_sb_coordinate(module_sb.get_sb_x(), module_sb.get_sb_y()); - - /* Collect sink-related information */ - std::string sink_sb_module_name = generate_switch_block_module_name(module_sb_coordinate); - ModuleId sink_sb_module = module_manager.find_module(sink_sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sink_sb_module)); - size_t sink_sb_instance = sb_instance_ids[instance_sb_coordinate.x()][instance_sb_coordinate.y()]; - - /* Connect grid output pins (OPIN) to switch block grid pins */ - for (size_t side = 0; side < module_sb.get_num_sides(); ++side) { - Side side_manager(side); - for (size_t inode = 0; inode < module_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - /* Collect source-related information */ - /* Generate the grid module name by considering if it locates on the border */ - vtr::Point grid_coordinate(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, (rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow)); - std::string src_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(GRID_MODULE_NAME_PREFIX), device_size, grids, grid_coordinate); - ModuleId src_grid_module = module_manager.find_module(src_grid_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); - size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; - size_t src_grid_pin_index = rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num; - size_t src_grid_pin_height = find_grid_pin_height(grids, grid_coordinate, src_grid_pin_index); - std::string src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_height, rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index, false); - ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id)); - BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id); - - /* Collect sink-related information */ - vtr::Point sink_sb_port_coord(module_sb.get_opin_node(side_manager.get_side(), inode)->xlow, - module_sb.get_opin_node(side_manager.get_side(), inode)->ylow); - std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(), - module_sb.get_opin_node_grid_side(side_manager.get_side(), inode), - src_grid_pin_index); - ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id)); - BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id); - - /* Source and sink port should match in size */ - VTR_ASSERT(src_grid_port.get_width() == sink_sb_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < src_grid_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(top_module); - /* Configure the net source */ - module_manager.add_module_net_source(top_module, net, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]); - /* Configure the net sink */ - module_manager.add_module_net_sink(top_module, net, sink_sb_module, sink_sb_instance, sink_sb_port_id, sink_sb_port.pins()[pin_id]); - } - } - } -} - -/******************************************************************** - * Add module nets to connect a GSB to adjacent grid ports/pins - * as well as connection blocks - * This function will create nets for the following types of connections - * between grid output pins of Switch block and adjacent grids - * In this case, the net source is the grid pin, while the net sink - * is the switch block pin - * - * In particular, this function considers the duplicated output pins of grids - * when creating the connecting nets. - * The follow figure shows the different pin postfix to be considered when - * connecting the grid pins to SB inputs - * - * +------------+ +------------+ - * | | | | - * | Grid | | Grid | - * | [x][y+1] |lower lower| [x+1][y+1] | - * | |----+ +----| | - * +------------+ | | +------------+ - * |lower v v |upper - * | +------------+ | - * +------>| |<-----+ - * | Switch | - * | Block | - * +------>| [x][y] |<-----+ - * | +------------+ | - * | ^ ^ | - * |lower | | |upper - * +------------+ | | +------------+ - * | |----+ +-----| | - * | Grid |upper upper | Grid | - * | [x][y] | | [x+1][y] | - * | | | | - * +------------+ +------------+ - * - *******************************************************************/ -static -void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager& module_manager, - const ModuleId& top_module, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const DeviceRRGSB& L_device_rr_gsb, - const RRGSB& rr_gsb, - const std::vector>& sb_instance_ids, - const bool& compact_routing_hierarchy) { - - /* We could have two different coordinators, one is the instance, the other is the module */ - vtr::Point instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - DeviceCoordinator module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); - - /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ - if (true == compact_routing_hierarchy) { - DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(gsb_coord); - module_gsb_coordinate.set_x(unique_mirror.get_x()); - module_gsb_coordinate.set_y(unique_mirror.get_y()); - } - - /* This is the source cb that is added to the top module */ - const RRGSB& module_sb = L_device_rr_gsb.get_gsb(module_gsb_coordinate); - vtr::Point module_sb_coordinate(module_sb.get_sb_x(), module_sb.get_sb_y()); - - /* Collect sink-related information */ - std::string sink_sb_module_name = generate_switch_block_module_name(module_sb_coordinate); - ModuleId sink_sb_module = module_manager.find_module(sink_sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sink_sb_module)); - size_t sink_sb_instance = sb_instance_ids[instance_sb_coordinate.x()][instance_sb_coordinate.y()]; - - /* Create a truth table for the postfix to be used regarding to the different side of switch blocks */ - std::map sb_side2postfix_map; - /* Boolean variable "true" indicates the upper postfix in naming functions - * Boolean variable "false" indicates the lower postfix in naming functions - */ - sb_side2postfix_map[TOP] = false; - sb_side2postfix_map[RIGHT] = true; - sb_side2postfix_map[BOTTOM] = true; - sb_side2postfix_map[LEFT] = false; - - /* Connect grid output pins (OPIN) to switch block grid pins */ - for (size_t side = 0; side < module_sb.get_num_sides(); ++side) { - Side side_manager(side); - for (size_t inode = 0; inode < module_sb.get_num_opin_nodes(side_manager.get_side()); ++inode) { - /* Collect source-related information */ - /* Generate the grid module name by considering if it locates on the border */ - vtr::Point grid_coordinate(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, (rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow)); - std::string src_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(GRID_MODULE_NAME_PREFIX), device_size, grids, grid_coordinate); - ModuleId src_grid_module = module_manager.find_module(src_grid_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); - size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; - size_t src_grid_pin_index = rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num; - size_t src_grid_pin_height = find_grid_pin_height(grids, grid_coordinate, src_grid_pin_index); - - /* Pins for direct connection are NOT duplicated. - * Follow the traditional recipe when adding nets! - * Xifan: I assume that each direct connection pin must have Fc=0. - * For other duplicated pins, we follow the new naming - */ - std::string src_grid_port_name; - if (0. == grids[grid_coordinate.x()][grid_coordinate.y()].type->Fc[src_grid_pin_index]) { - src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_height, rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index, false); - } else { - src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_height, rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index, sb_side2postfix_map[side_manager.get_side()]); - } - ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id)); - BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id); - - /* Collect sink-related information */ - vtr::Point sink_sb_port_coord(module_sb.get_opin_node(side_manager.get_side(), inode)->xlow, - module_sb.get_opin_node(side_manager.get_side(), inode)->ylow); - std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(), - module_sb.get_opin_node_grid_side(side_manager.get_side(), inode), - src_grid_pin_index); - ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id)); - BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id); - - /* Source and sink port should match in size */ - VTR_ASSERT(src_grid_port.get_width() == sink_sb_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < src_grid_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(top_module); - /* Configure the net source */ - module_manager.add_module_net_source(top_module, net, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]); - /* Configure the net sink */ - module_manager.add_module_net_sink(top_module, net, sink_sb_module, sink_sb_instance, sink_sb_port_id, sink_sb_port.pins()[pin_id]); - } - } - } -} - -/******************************************************************** - * This function will create nets for the connections - * between grid input pins and connection blocks - * In this case, the net source is the connection block pin, - * while the net sink is the grid input - * - * +------------+ +------------------+ +------------+ - * | | | | | | - * | Grid |<-----| Connection Block |----->| Grid | - * | [x][y+1] | | Y-direction | | [x+1][y+1] | - * | | | [x][y+1] | | | - * +------------+ +------------------+ +------------+ - * ^ - * | - * +------------+ +------------------+ - * | Connection | | | - * | Block | | Switch Block | - * | X-direction| | [x][y] | - * | [x][y] | | | - * +------------+ +------------------+ - * | - * v - * +------------+ - * | | - * | Grid | - * | [x][y] | - * | | - * +------------+ - * - * - * Relationship between source connection block and its unique module - * Take an example of a CBY - * - * grid_pin name should follow unique module of Grid[x][y+1] - * cb_pin name should follow unique module of CBY[x][y+1] - * - * However, instace id should follow the origin Grid and Connection block - * - * - * +------------+ +------------------+ - * | | | | - * | Grid |<------------| Connection Block | - * | [x][y+1] | | Y-direction | - * | | | [x][y+1] | - * +------------+ +------------------+ - * ^ - * || unique mirror - * +------------+ +------------------+ - * | | | | - * | Grid |<------------| Connection Block | - * | [i][j+1] | | Y-direction | - * | | | [i][j+1] | - * +------------+ +------------------+ - * - *******************************************************************/ -static -void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, - const ModuleId& top_module, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const DeviceRRGSB& L_device_rr_gsb, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const std::vector>& cb_instance_ids, - const bool& compact_routing_hierarchy) { - /* We could have two different coordinators, one is the instance, the other is the module */ - vtr::Point instance_cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - DeviceCoordinator module_gsb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); - - /* Skip those Connection blocks that do not exist */ - if (false == rr_gsb.is_cb_exist(cb_type)) { - return; - } - - /* Skip if the cb does not contain any configuration bits! */ - if (true == connection_block_contain_only_routing_tracks(rr_gsb, cb_type)) { - return; - } - - /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ - if (true == compact_routing_hierarchy) { - DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, gsb_coord); - module_gsb_coordinate.set_x(unique_mirror.get_x()); - module_gsb_coordinate.set_y(unique_mirror.get_y()); - } - - /* This is the source cb that is added to the top module */ - const RRGSB& module_cb = L_device_rr_gsb.get_gsb(module_gsb_coordinate); - vtr::Point module_cb_coordinate(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type)); - - /* Collect source-related information */ - std::string src_cb_module_name = generate_connection_block_module_name(cb_type, module_cb_coordinate); - ModuleId src_cb_module = module_manager.find_module(src_cb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(src_cb_module)); - /* Instance id should follow the instance cb coordinate */ - size_t src_cb_instance = cb_instance_ids[instance_cb_coordinate.x()][instance_cb_coordinate.y()]; - - /* Iterate over the output pins of the Connection Block */ - std::vector cb_ipin_sides = module_cb.get_cb_ipin_sides(cb_type); - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < module_cb.get_num_ipin_nodes(cb_ipin_side); ++inode) { - /* Collect source-related information */ - t_rr_node* module_ipin_node = module_cb.get_ipin_node(cb_ipin_side, inode); - vtr::Point cb_src_port_coord(module_ipin_node->xlow, module_ipin_node->ylow); - std::string src_cb_port_name = generate_cb_module_grid_port_name(cb_ipin_side, - module_ipin_node->ptc_num); - ModulePortId src_cb_port_id = module_manager.find_module_port(src_cb_module, src_cb_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, src_cb_port_id)); - BasicPort src_cb_port = module_manager.module_port(src_cb_module, src_cb_port_id); - - /* Collect sink-related information */ - /* Note that we use the instance cb pin here!!! - * because it has the correct coordinator for the grid!!! - */ - t_rr_node* instance_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); - vtr::Point grid_coordinate(instance_ipin_node->xlow, instance_ipin_node->ylow); - std::string sink_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(GRID_MODULE_NAME_PREFIX), device_size, grids, grid_coordinate); - ModuleId sink_grid_module = module_manager.find_module(sink_grid_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); - size_t sink_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; - size_t sink_grid_pin_index = instance_ipin_node->ptc_num; - size_t sink_grid_pin_height = find_grid_pin_height(grids, grid_coordinate, sink_grid_pin_index); - std::string sink_grid_port_name = generate_grid_port_name(grid_coordinate, sink_grid_pin_height, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), sink_grid_pin_index, false); - ModulePortId sink_grid_port_id = module_manager.find_module_port(sink_grid_module, sink_grid_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_grid_port_id)); - BasicPort sink_grid_port = module_manager.module_port(sink_grid_module, sink_grid_port_id); - - /* Source and sink port should match in size */ - VTR_ASSERT(src_cb_port.get_width() == sink_grid_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(top_module); - /* Configure the net source */ - module_manager.add_module_net_source(top_module, net, src_cb_module, src_cb_instance, src_cb_port_id, src_cb_port.pins()[pin_id]); - /* Configure the net sink */ - module_manager.add_module_net_sink(top_module, net, sink_grid_module, sink_grid_instance, sink_grid_port_id, sink_grid_port.pins()[pin_id]); - } - } - } -} - -/******************************************************************** - * This function will create nets for the connections - * between connection block and switch block pins - * Two cases should be considered: - * a. The switch block pin denotes an input of a routing track - * The net source is an output of a routing track of connection block - * while the net sink is an input of a routing track of switch block - * b. The switch block pin denotes an output of a routing track - * The net source is an output of routing track of switch block - * while the net sink is an input of a routing track of connection block - * - * +------------+ +------------------+ +------------+ - * | | | | | | - * | Grid | | Connection Block | | Grid | - * | [x][y+1] | | Y-direction | | [x+1][y+1] | - * | | | [x][y+1] | | | - * +------------+ +------------------+ +------------+ - * | ^ - * v | - * +------------+ +------------------+ +------------+ - * | Connection |----->| |----->| Connection | - * | Block | | Switch Block | | Block | - * | X-direction|<-----| [x][y] |<-----| X-direction| - * | [x][y] | | | | [x+1][y] | - * +------------+ +------------------+ +------------+ - * | ^ - * v | - * +------------+ +------------------+ +------------+ - * | | | | | | - * | Grid | | Connection Block | | Grid | - * | [x][y] | | Y-direction | | [x][y+1] | - * | | | [x][y] | | | - * +------------+ +------------------+ +------------+ - * - * Here, to achieve the purpose, we can simply iterate over the - * four sides of switch block and make connections to adjancent - * connection blocks - * - *******************************************************************/ -static -void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, - const ModuleId& top_module, - const DeviceRRGSB& L_device_rr_gsb, - const RRGSB& rr_gsb, - const std::vector>& sb_instance_ids, - const std::map>>& cb_instance_ids, - const bool& compact_routing_hierarchy) { - /* We could have two different coordinators, one is the instance, the other is the module */ - vtr::Point instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - DeviceCoordinator module_gsb_sb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); - - /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ - if (true == compact_routing_hierarchy) { - DeviceCoordinator gsb_coord(rr_gsb.get_x(), rr_gsb.get_y()); - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(gsb_coord); - module_gsb_sb_coordinate.set_x(unique_mirror.get_x()); - module_gsb_sb_coordinate.set_y(unique_mirror.get_y()); - } - - /* This is the source cb that is added to the top module */ - const RRGSB& module_sb = L_device_rr_gsb.get_gsb(module_gsb_sb_coordinate); - vtr::Point module_sb_coordinate(module_sb.get_sb_x(), module_sb.get_sb_y()); - std::string sb_module_name = generate_switch_block_module_name(module_sb_coordinate); - ModuleId sb_module_id = module_manager.find_module(sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sb_module_id)); - size_t sb_instance = sb_instance_ids[instance_sb_coordinate.x()][instance_sb_coordinate.y()]; - - /* Connect grid output pins (OPIN) to switch block grid pins */ - for (size_t side = 0; side < module_sb.get_num_sides(); ++side) { - Side side_manager(side); - /* Iterate over the routing tracks on this side */ - /* Early skip: if there is no routing tracks at this side */ - if (0 == module_sb.get_chan_width(side_manager.get_side())) { - continue; - } - /* Find the Connection Block module */ - /* We find the original connection block and then spot its unique mirror! - * Do NOT use module_sb here!!! - */ - t_rr_type cb_type = find_top_module_cb_type_by_sb_side(side_manager.get_side()); - DeviceCoordinator instance_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side()); - DeviceCoordinator module_gsb_cb_coordinate = find_top_module_gsb_coordinate_by_sb_side(rr_gsb, side_manager.get_side()); - - /* Skip those Connection blocks that do not exist: - * 1. The CB does not exist in the device level! We should skip! - * 2. The CB does exist but we need to make sure if the GSB includes such CBs - * For TOP and LEFT side, check the existence using RRGSB method is_cb_exist() - * FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then use is_cb_exist() - */ - if ( TOP == side_manager.get_side() || LEFT == side_manager.get_side() ) { - if ( false == rr_gsb.is_cb_exist(cb_type)) { - continue; - } - } - - if ( RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side() ) { - const RRGSB& adjacent_gsb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate); - if ( false == adjacent_gsb.is_cb_exist(cb_type)) { - continue; - } - } - - /* If we use compact routing hierarchy, we should find the unique module of CB, which is added to the top module */ - if (true == compact_routing_hierarchy) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, module_gsb_cb_coordinate); - module_gsb_cb_coordinate.set_x(unique_mirror.get_x()); - module_gsb_cb_coordinate.set_y(unique_mirror.get_y()); - } - - const RRGSB& module_cb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate); - vtr::Point module_cb_coordinate(module_cb.get_cb_x(cb_type), module_cb.get_cb_y(cb_type)); - std::string cb_module_name = generate_connection_block_module_name(cb_type, module_cb_coordinate); - ModuleId cb_module_id = module_manager.find_module(cb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(cb_module_id)); - const RRGSB& instance_cb = L_device_rr_gsb.get_gsb(instance_gsb_cb_coordinate); - vtr::Point instance_cb_coordinate(instance_cb.get_cb_x(cb_type), instance_cb.get_cb_y(cb_type)); - size_t cb_instance = cb_instance_ids.at(cb_type)[instance_cb_coordinate.x()][instance_cb_coordinate.y()]; - - for (size_t itrack = 0; itrack < module_sb.get_chan_width(side_manager.get_side()); ++itrack) { - std::string sb_port_name = generate_sb_module_track_port_name(module_sb.get_chan_node(side_manager.get_side(), itrack)->type, - side_manager.get_side(), itrack, - module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); - /* Prepare SB-related port information */ - ModulePortId sb_port_id = module_manager.find_module_port(sb_module_id, sb_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module_id, sb_port_id)); - BasicPort sb_port = module_manager.module_port(sb_module_id, sb_port_id); - - /* Prepare CB-related port information */ - PORTS cb_port_direction = OUT_PORT; - /* The cb port direction should be opposite to the sb port !!! */ - if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { - cb_port_direction = IN_PORT; - } else { - VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); - } - std::string cb_port_name = generate_cb_module_track_port_name(cb_type, - itrack, - cb_port_direction); - ModulePortId cb_port_id = module_manager.find_module_port(cb_module_id, cb_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module_id, cb_port_id)); - BasicPort cb_port = module_manager.module_port(cb_module_id, cb_port_id); - - /* Source and sink port should match in size */ - VTR_ASSERT(cb_port.get_width() == sb_port.get_width()); - - /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < cb_port.pins().size(); ++pin_id) { - ModuleNetId net = module_manager.create_module_net(top_module); - /* Configure the net source and sink: - * If sb port is an output (source), cb port is an input (sink) - * If sb port is an input (sink), cb port is an output (source) - */ - if (OUT_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { - module_manager.add_module_net_sink(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]); - module_manager.add_module_net_source(top_module, net, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]); - } else { - VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); - module_manager.add_module_net_source(top_module, net, cb_module_id, cb_instance, cb_port_id, cb_port.pins()[pin_id]); - module_manager.add_module_net_sink(top_module, net, sb_module_id, sb_instance, sb_port_id, sb_port.pins()[pin_id]); - } - } - } - } -} - -/******************************************************************** - * Add module nets to connect the grid ports/pins to Connection Blocks - * and Switch Blocks - * To make it easy, this function will iterate over all the General - * Switch Blocks (GSBs), through which we can obtain the coordinates - * of all the grids, connection blocks and switch blocks that are - * supposed to be connected tightly. - * - * As such, we have completed all the connection for each grid. - * There is no need to iterate over the grids - * - * +-------------------------+ +---------------------------------+ - * | | | Y-direction CB | - * | Grid[x][y+1] | | [x][y + 1] | - * | | +---------------------------------+ - * +-------------------------+ - * TOP SIDE - * +-------------+ +---------------------------------+ - * | | | OPIN_NODE CHAN_NODES OPIN_NODES | - * | | | | - * | | | OPIN_NODES OPIN_NODES | - * | X-direction | | | - * | CB | LEFT SIDE | Switch Block | RIGHT SIDE - * | [x][y] | | [x][y] | - * | | | | - * | | | CHAN_NODES CHAN_NODES | - * | | | | - * | | | OPIN_NODES OPIN_NODES | - * | | | | - * | | | OPIN_NODE CHAN_NODES OPIN_NODES | - * +-------------+ +---------------------------------+ - * BOTTOM SIDE - *******************************************************************/ -void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, - const ModuleId& top_module, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector>& sb_instance_ids, - const std::map>>& cb_instance_ids, - const bool& compact_routing_hierarchy, - const bool& duplicate_grid_pin) { - DeviceCoordinator gsb_range = L_device_rr_gsb.get_gsb_range(); - for (size_t ix = 0; ix < gsb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < gsb_range.get_y(); ++iy) { - vtr::Point gsb_coordinate(ix, iy); - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - /* Connect the grid pins of the GSB to adjacent grids */ - if (false == duplicate_grid_pin) { - add_top_module_nets_connect_grids_and_sb(module_manager, top_module, - device_size, grids, grid_instance_ids, - L_device_rr_gsb, rr_gsb, sb_instance_ids, - compact_routing_hierarchy); - } else { - VTR_ASSERT_SAFE(true == duplicate_grid_pin); - add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(module_manager, top_module, - device_size, grids, grid_instance_ids, - L_device_rr_gsb, rr_gsb, sb_instance_ids, - compact_routing_hierarchy); - } - - add_top_module_nets_connect_grids_and_cb(module_manager, top_module, - device_size, grids, grid_instance_ids, - L_device_rr_gsb, rr_gsb, CHANX, cb_instance_ids.at(CHANX), - compact_routing_hierarchy); - - add_top_module_nets_connect_grids_and_cb(module_manager, top_module, - device_size, grids, grid_instance_ids, - L_device_rr_gsb, rr_gsb, CHANY, cb_instance_ids.at(CHANY), - compact_routing_hierarchy); - - add_top_module_nets_connect_sb_and_cb(module_manager, top_module, - L_device_rr_gsb, rr_gsb, sb_instance_ids, cb_instance_ids, - compact_routing_hierarchy); - - } - } -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_connection.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_connection.h deleted file mode 100644 index 2bd75e1a1..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_connection.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef BUILD_TOP_MODULE_CONNECTION_H -#define BUILD_TOP_MODULE_CONNECTION_H - -#include -#include "vtr_geometry.h" -#include "vpr_types.h" -#include "rr_blocks.h" -#include "module_manager.h" - -void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, - const ModuleId& top_module, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector>& sb_instance_ids, - const std::map>>& cb_instance_ids, - const bool& compact_routing_hierarchy, - const bool& duplicate_grid_pin); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp deleted file mode 100644 index 06d3339d1..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.cpp +++ /dev/null @@ -1,563 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to add module nets - * for direct connections between CLBs/heterogeneous blocks - * in the top-level module of a FPGA fabric - *******************************************************************/ -#include - -#include "vtr_assert.h" -#include "util.h" -#include "device_port.h" - -#include "fpga_x2p_naming.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "module_manager_utils.h" - -#include "globals.h" -#include "verilog_global.h" - -#include "build_top_module_directs.h" - -/******************************************************************** - * Check if the grid coorindate given is in the device grid range - *******************************************************************/ -static -bool is_grid_coordinate_exist_in_device(const vtr::Point& device_size, - const vtr::Point& grid_coordinate) { - return (grid_coordinate < device_size); -} - -/******************************************************************** - * Add module net for one direction connection between two CLBs or - * two grids - * This function will - * 1. find the pin id and port id of the source clb port in module manager - * 2. find the pin id and port id of the destination clb port in module manager - * 3. add a direct connection module to the top module - * 4. add a first module net and configure its source and sink, - * in order to connect the source pin to the input of the top module - * 4. add a second module net and configure its source and sink, - * in order to connect the sink pin to the output of the top module - *******************************************************************/ -static -void add_module_nets_clb2clb_direct_connection(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const vtr::Point& src_clb_coord, - const vtr::Point& des_clb_coord, - const t_clb_to_clb_directs& direct) { - /* Find the source port and destination port on the CLBs */ - BasicPort src_clb_port; - BasicPort des_clb_port; - - src_clb_port.set_width(direct.from_clb_pin_start_index, direct.from_clb_pin_end_index); - des_clb_port.set_width(direct.to_clb_pin_start_index, direct.to_clb_pin_end_index); - - /* Check bandwidth match between from_clb and to_clb pins */ - if (src_clb_port.get_width() != des_clb_port.get_width()) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Unmatch pin bandwidth in direct connection (name=%s)!\n", - __FILE__, __LINE__, direct.name); - exit(1); - } - - /* Find the module name of source clb */ - t_type_ptr src_grid_type = grids[src_clb_coord.x()][src_clb_coord.y()].type; - e_side src_grid_border_side = find_grid_border_side(device_size, src_clb_coord); - std::string src_module_name_prefix(grid_verilog_file_name_prefix); - std::string src_module_name = generate_grid_block_module_name(src_module_name_prefix, std::string(src_grid_type->name), IO_TYPE == src_grid_type, src_grid_border_side); - ModuleId src_grid_module = module_manager.find_module(src_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); - /* Record the instance id */ - size_t src_grid_instance = grid_instance_ids[src_clb_coord.x()][src_clb_coord.y()]; - - /* Find the module name of sink clb */ - t_type_ptr sink_grid_type = grids[des_clb_coord.x()][des_clb_coord.y()].type; - e_side sink_grid_border_side = find_grid_border_side(device_size, des_clb_coord); - std::string sink_module_name_prefix(grid_verilog_file_name_prefix); - std::string sink_module_name = generate_grid_block_module_name(sink_module_name_prefix, std::string(sink_grid_type->name), IO_TYPE == sink_grid_type, sink_grid_border_side); - ModuleId sink_grid_module = module_manager.find_module(sink_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); - /* Record the instance id */ - size_t sink_grid_instance = grid_instance_ids[des_clb_coord.x()][des_clb_coord.y()]; - - /* Find the module id of a direct connection module */ - std::string direct_module_name = circuit_lib.model_name(direct.circuit_model); - ModuleId direct_module = module_manager.find_module(direct_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(direct_module)); - - /* Find inputs and outputs of the direct circuit module */ - std::vector direct_input_ports = circuit_lib.model_ports_by_type(direct.circuit_model, SPICE_MODEL_PORT_INPUT, true); - VTR_ASSERT(1 == direct_input_ports.size()); - ModulePortId direct_input_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_prefix(direct_input_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_input_port_id)); - VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_input_port_id).get_width()); - - std::vector direct_output_ports = circuit_lib.model_ports_by_type(direct.circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == direct_output_ports.size()); - ModulePortId direct_output_port_id = module_manager.find_module_port(direct_module, circuit_lib.port_prefix(direct_output_ports[0])); - VTR_ASSERT(true == module_manager.valid_module_port_id(direct_module, direct_output_port_id)); - VTR_ASSERT(1 == module_manager.module_port(direct_module, direct_output_port_id).get_width()); - - for (size_t pin_id = 0; pin_id < src_clb_port.pins().size(); ++pin_id) { - /* Generate the pin name of source port/pin in the grid */ - size_t src_pin_height = find_grid_pin_height(grids, src_clb_coord, src_clb_port.pins()[pin_id]); - e_side src_pin_grid_side = find_grid_pin_side(device_size, grids, src_clb_coord, src_pin_height, src_clb_port.pins()[pin_id]); - std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_height, src_pin_grid_side, src_clb_port.pins()[pin_id], false); - ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_port_id)); - VTR_ASSERT(1 == module_manager.module_port(src_grid_module, src_port_id).get_width()); - - /* Generate the pin name of sink port/pin in the grid */ - size_t sink_pin_height = find_grid_pin_height(grids, des_clb_coord, des_clb_port.pins()[pin_id]); - e_side sink_pin_grid_side = find_grid_pin_side(device_size, grids, des_clb_coord, sink_pin_height, des_clb_port.pins()[pin_id]); - std::string sink_port_name = generate_grid_port_name(des_clb_coord, sink_pin_height, sink_pin_grid_side, des_clb_port.pins()[pin_id], false); - ModulePortId sink_port_id = module_manager.find_module_port(sink_grid_module, sink_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_port_id)); - VTR_ASSERT(1 == module_manager.module_port(sink_grid_module, sink_port_id).get_width()); - - /* Add a submodule of direct connection module to the top-level module */ - size_t direct_instance_id = module_manager.num_instance(top_module, direct_module); - module_manager.add_child_module(top_module, direct_module); - - /* Create the 1st module net */ - ModuleNetId net_direct_src = module_manager.create_module_net(top_module); - /* Connect the wire between src_pin of clb and direct_instance input*/ - module_manager.add_module_net_source(top_module, net_direct_src, src_grid_module, src_grid_instance, src_port_id, 0); - module_manager.add_module_net_sink(top_module, net_direct_src, direct_module, direct_instance_id, direct_input_port_id, 0); - - /* Create the 2nd module net */ - ModuleNetId net_direct_sink = module_manager.create_module_net(top_module); - /* Connect the wire between direct_instance output and sink_pin of clb */ - module_manager.add_module_net_source(top_module, net_direct_sink, direct_module, direct_instance_id, direct_output_port_id, 0); - module_manager.add_module_net_sink(top_module, net_direct_sink, sink_grid_module, sink_grid_instance, sink_port_id, 0); - } -} - - -/******************************************************************** - * Add module net of clb-to-clb direct connections to module manager - * Note that the direct connections are not limited to CLBs only. - * It can be more generic and thus cover all the grid types, - * such as heterogeneous blocks - * - * This function supports the following type of direct connection: - * 1. Direct connection between grids in the same column or row - * +------+ +------+ - * | | | | - * | Grid |----->| Grid | - * | | | | - * +------+ +------+ - * | direction connection - * v - * +------+ - * | | - * | Grid | - * | | - * +------+ - * - *******************************************************************/ -static -void add_top_module_nets_intra_clb2clb_direct_connections(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const std::vector& clb2clb_directs) { - /* Scan the grid, visit each grid and apply direct connections */ - for (size_t ix = 0; ix < device_size.x(); ++ix) { - for (size_t iy = 0; iy < device_size.y(); ++iy) { - /* Bypass EMPTY_TYPE*/ - if ( (NULL == grids[ix][iy].type) - || (EMPTY_TYPE == grids[ix][iy].type)) { - continue; - } - /* Bypass any grid with a non-zero offset! They have been visited in the offset=0 case */ - if (0 != grids[ix][iy].offset) { - continue; - } - /* Check each clb2clb directs by comparing the source and destination clb types - * Direct connections are made only for those matched clbs - */ - for (const t_clb_to_clb_directs& direct : clb2clb_directs) { - /* Bypass unmatched clb type */ - if (grids[ix][iy].type != direct.from_clb_type) { - continue; - } - - /* See if the destination CLB is in the bound */ - vtr::Point src_clb_coord(ix, iy); - vtr::Point des_clb_coord(ix + direct.x_offset, iy + direct.y_offset); - if (false == is_grid_coordinate_exist_in_device(device_size, des_clb_coord)) { - continue; - } - - /* Check if the destination clb_type matches */ - if (grids[des_clb_coord.x()][des_clb_coord.y()].type == direct.to_clb_type) { - /* Add a module net for a direct connection with the two grids in top_model */ - add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - src_clb_coord, des_clb_coord, - direct); - } - } - } - } -} - -/******************************************************************** - * Find the coordinate of a grid in a specific column - * with a given type - * This function will return the coordinate of the grid that satifies - * the type requirement - *******************************************************************/ -static -vtr::Point find_grid_coordinate_given_type(const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& candidate_coords, - t_type_ptr wanted_grid_type) { - for (vtr::Point coord : candidate_coords) { - /* If the next column is not longer in device range, we can return */ - if (false == is_grid_coordinate_exist_in_device(device_size, coord)) { - continue; - } - if (wanted_grid_type == grids[coord.x()][coord.y()].type) { - return coord; - } - } - /* Return an valid coordinate */ - return vtr::Point(size_t(-1), size_t(-1)); -} - -/******************************************************************** - * Find the coordinate of the destination clb/heterogeneous block - * considering intra column/row direct connections in core grids - *******************************************************************/ -static -vtr::Point find_intra_direct_destination_coordinate(const vtr::Point& device_size, - const std::vector>& grids, - const vtr::Point src_coord, - const t_clb_to_clb_directs& direct) { - vtr::Point des_coord(size_t(-1), size_t(-1)); - t_type_ptr src_grid_type = grids[src_coord.x()][src_coord.y()].type; - - std::vector first_search_space; - std::vector second_search_space; - - /* Cross column connection from Bottom to Top on Right - * The next column may NOT have the grid type we want! - * Think about heterogeneous architecture! - * Our search space will start from the next column - * and ends at the RIGHT side of fabric - */ - if (P2P_DIRECT_COLUMN == direct.interconnection_type) { - if (POSITIVE_DIR == direct.x_dir) { - /* Our first search space will be in x-direction: - * - * x ... nx - * +-----+ - * |Grid | -----> - * +-----+ - */ - for (size_t ix = src_coord.x() + 1; ix < device_size.x() - 1; ++ix) { - first_search_space.push_back(ix); - } - } else { - VTR_ASSERT(NEGATIVE_DIR == direct.x_dir); - /* Our first search space will be in x-direction: - * - * 1 ... x - * +-----+ - * < -------|Grid | - * +-----+ - */ - for (size_t ix = src_coord.x() - 1; ix >= 1; --ix) { - first_search_space.push_back(ix); - } - } - - /* Our second search space will be in y-direction: - * - * +------+ - * | Grid | ny - * +------+ - * ^ . - * | . - * | . - * +------+ - * | Grid | 1 - * +------+ - */ - for (size_t iy = 1 ; iy < device_size.y() - 1; ++iy) { - second_search_space.push_back(iy); - } - - /* For negative direction, our second search space will be in y-direction: - * - * +------+ - * | Grid | ny - * +------+ - * | . - * | . - * v . - * +------+ - * | Grid | 1 - * +------+ - */ - if (POSITIVE_DIR == direct.y_dir) { - std::reverse(second_search_space.begin(), second_search_space.end()); - } - } - - - /* Cross row connection from Bottom to Top on Right - * The next column may NOT have the grid type we want! - * Think about heterogeneous architecture! - * Our search space will start from the next column - * and ends at the RIGHT side of fabric - */ - if (P2P_DIRECT_ROW == direct.interconnection_type) { - if (POSITIVE_DIR == direct.y_dir) { - /* Our first search space will be in y-direction: - * - * +------+ - * | Grid | ny - * +------+ - * ^ . - * | . - * | . - * +------+ - * | Grid | y - * +------+ - */ - for (size_t iy = src_coord.y() + 1; iy < device_size.y() - 1; ++iy) { - first_search_space.push_back(iy); - } - } else { - VTR_ASSERT(NEGATIVE_DIR == direct.y_dir); - /* For negative y-direction, - * Our first search space will be in y-direction: - * - * +------+ - * | Grid | ny - * +------+ - * | . - * | . - * v . - * +------+ - * | Grid | y - * +------+ - */ - for (size_t iy = src_coord.y() - 1; iy >= 1; --iy) { - first_search_space.push_back(iy); - } - } - - /* Our second search space will be in x-direction: - * - * 1 ... nx - * +------+ +------+ - * | Grid |<------| Grid | - * +------+ +------+ - */ - for (size_t ix = 1 ; ix < device_size.x() - 1; ++ix) { - second_search_space.push_back(ix); - } - - /* For negative direction, - * our second search space will be in x-direction: - * - * 1 ... nx - * +------+ +------+ - * | Grid |------>| Grid | - * +------+ +------+ - */ - if (POSITIVE_DIR == direct.x_dir) { - std::reverse(second_search_space.begin(), second_search_space.end()); - } - } - - for (size_t ix : first_search_space) { - std::vector> next_col_row_coords; - for (size_t iy : second_search_space) { - if (P2P_DIRECT_COLUMN == direct.interconnection_type) { - next_col_row_coords.push_back(vtr::Point(ix, iy)); - } else { - VTR_ASSERT(P2P_DIRECT_ROW == direct.interconnection_type); - /* For cross-row connection, our search space is flipped */ - next_col_row_coords.push_back(vtr::Point(iy, ix)); - } - } - vtr::Point des_coord_cand = find_grid_coordinate_given_type(device_size, grids, next_col_row_coords, src_grid_type); - /* For a valid coordinate, we can return */ - if ( (size_t(-1) != des_coord_cand.x()) - && (size_t(-1) != des_coord_cand.y()) ) { - return des_coord_cand; - } - } - return des_coord; -} - -/******************************************************************** - * Add module net of clb-to-clb direct connections to module manager - * Note that the direct connections are not limited to CLBs only. - * It can be more generic and thus cover all the grid types, - * such as heterogeneous blocks - * - * This function supports the following type of direct connection: - * - * 1. Direct connections across columns and rows - * +------+ - * | | - * | v - * +------+ | +------+ - * | | | | | - * | Grid | | | Grid | - * | | | | | - * +------+ | +------+ - * | - * +------+ | +------+ - * | | | | | - * | Grid | | | Grid | - * | | | | | - * +------+ | +------+ - * | | - * +------+ - * - * Note that: this will only apply to the core grids! - * I/Os or any blocks on the border of fabric are NOT supported! - * - *******************************************************************/ -static -void add_top_module_nets_inter_clb2clb_direct_connections(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const std::vector& clb2clb_directs) { - - std::vector border_sides = {TOP, RIGHT, BOTTOM, LEFT}; - - /* Go through the direct connection list, see if we need intra-column/row connection here */ - for (const t_clb_to_clb_directs& direct: clb2clb_directs) { - if ( (P2P_DIRECT_COLUMN != direct.interconnection_type) - && (P2P_DIRECT_ROW != direct.interconnection_type)) { - continue; - } - /* For cross-column connection, we will search the first valid grid in each column - * from y = 1 to y = ny - * - * +------+ - * | Grid | y=ny - * +------+ - * ^ - * | search direction (when y_dir is negative) - * ... - * | - * +------+ - * | Grid | y=1 - * +------+ - * - */ - if (P2P_DIRECT_COLUMN == direct.interconnection_type) { - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - std::vector> next_col_src_grid_coords; - /* For negative y- direction, we should start from y = ny */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - next_col_src_grid_coords.push_back(vtr::Point(ix, iy)); - } - /* For positive y- direction, we should start from y = 1 */ - if (NEGATIVE_DIR == direct.y_dir) { - std::reverse(next_col_src_grid_coords.begin(), next_col_src_grid_coords.end()); - } - vtr::Point src_clb_coord = find_grid_coordinate_given_type(device_size, grids, next_col_src_grid_coords, direct.from_clb_type); - /* Skip if we do not have a valid coordinate for source CLB/heterogeneous block */ - if ( (size_t(-1) == src_clb_coord.x()) - || (size_t(-1) == src_clb_coord.y()) ) { - continue; - } - /* For a valid coordinate, we can find the coordinate of the destination clb */ - vtr::Point des_clb_coord = find_intra_direct_destination_coordinate(device_size, grids, src_clb_coord, direct); - /* If destination clb is valid, we should add something */ - if ( (size_t(-1) == des_clb_coord.x()) - || (size_t(-1) == des_clb_coord.y()) ) { - continue; - } - add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - src_clb_coord, des_clb_coord, - direct); - } - continue; /* Go to next direct type */ - } - - /* Reach here, it must be a cross-row connection */ - VTR_ASSERT(P2P_DIRECT_ROW == direct.interconnection_type); - /* For cross-row connection, we will search the first valid grid in each column - * from x = 1 to x = nx - * - * x=1 x=nx - * +------+ +------+ - * | Grid | <--- ... ---- | Grid | - * +------+ +------+ - * - */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - std::vector> next_col_src_grid_coords; - /* For negative x- direction, we should start from x = nx */ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - next_col_src_grid_coords.push_back(vtr::Point(ix, iy)); - } - /* For positive x- direction, we should start from x = 1 */ - if (POSITIVE_DIR == direct.x_dir) { - std::reverse(next_col_src_grid_coords.begin(), next_col_src_grid_coords.end()); - } - vtr::Point src_clb_coord = find_grid_coordinate_given_type(device_size, grids, next_col_src_grid_coords, direct.from_clb_type); - /* Skip if we do not have a valid coordinate for source CLB/heterogeneous block */ - if ( (size_t(-1) == src_clb_coord.x()) - || (size_t(-1) == src_clb_coord.y()) ) { - continue; - } - /* For a valid coordinate, we can find the coordinate of the destination clb */ - vtr::Point des_clb_coord = find_intra_direct_destination_coordinate(device_size, grids, src_clb_coord, direct); - /* If destination clb is valid, we should add something */ - if ( (size_t(-1) == des_clb_coord.x()) - || (size_t(-1) == des_clb_coord.y()) ) { - continue; - } - add_module_nets_clb2clb_direct_connection(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - src_clb_coord, des_clb_coord, - direct); - } - } -} - -/******************************************************************** - * Add module net of clb-to-clb direct connections to module manager - * Note that the direct connections are not limited to CLBs only. - * It can be more generic and thus cover all the grid types, - * such as heterogeneous blocks - *******************************************************************/ -void add_top_module_nets_clb2clb_direct_connections(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const std::vector& clb2clb_directs) { - - add_top_module_nets_intra_clb2clb_direct_connections(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - clb2clb_directs); - - add_top_module_nets_inter_clb2clb_direct_connections(module_manager, top_module, circuit_lib, - device_size, grids, grid_instance_ids, - clb2clb_directs); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.h deleted file mode 100644 index 4c6f759ee..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_directs.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef BUILD_TOP_MODULE_DIRECTS_H -#define BUILD_TOP_MODULE_DIRECTS_H - -#include -#include "vtr_geometry.h" -#include "vpr_types.h" -#include "module_manager.h" -#include "circuit_library.h" - -void add_top_module_nets_clb2clb_direct_connections(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const std::vector& clb2clb_directs); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp deleted file mode 100644 index 4042febd7..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp +++ /dev/null @@ -1,439 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to organize memories - * in the top module of FPGA fabric - *******************************************************************/ -#include "vtr_assert.h" - -#include "rr_blocks_utils.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_naming.h" - -#include "globals.h" -#include "verilog_global.h" - -#include "module_manager_utils.h" -#include "build_top_module_memory.h" - -/******************************************************************** - * This function adds the CBX/CBY of a tile - * to the memory modules and memory instances - * This function is designed for organizing memory modules in top-level - * module - *******************************************************************/ -static -void organize_top_module_tile_cb_modules(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const std::vector>& cb_instance_ids, - const DeviceRRGSB& L_device_rr_gsb, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const bool& compact_routing_hierarchy) { - /* If the CB does not exist, we can skip addition */ - if ( false == rr_gsb.is_cb_exist(cb_type)) { - return; - } - - /* Skip if the cb does not contain any configuration bits! */ - if (true == connection_block_contain_only_routing_tracks(rr_gsb, cb_type)) { - return; - } - - vtr::Point cb_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ - if (true == compact_routing_hierarchy) { - /* Note: use GSB coordinate when inquire for unique modules!!! */ - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(cb_type, DeviceCoordinator(rr_gsb.get_x(), rr_gsb.get_y())); - cb_coord.set_x(unique_mirror.get_cb_x(cb_type)); - cb_coord.set_y(unique_mirror.get_cb_y(cb_type)); - } - - std::string cb_module_name = generate_connection_block_module_name(cb_type, cb_coord); - ModuleId cb_module = module_manager.find_module(cb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); - - /* Identify if this sub module includes configuration bits, - * we will update the memory module and instance list - */ - if (0 < find_module_num_config_bits(module_manager, cb_module, - circuit_lib, sram_model, - sram_orgz_type)) { - /* Note that use the original CB coodinate for instance id searching ! */ - module_manager.add_configurable_child(top_module, cb_module, cb_instance_ids[rr_gsb.get_cb_x(cb_type)][rr_gsb.get_cb_y(cb_type)]); - } -} - -/******************************************************************** - * This function adds the SB, CBX, CBY and Grid of a tile - * to the memory modules and memory instances - * This function is designed for organizing memory modules in top-level - * module - *******************************************************************/ -static -void organize_top_module_tile_memory_modules(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector>& sb_instance_ids, - const std::map>>& cb_instance_ids, - const bool& compact_routing_hierarchy, - const vtr::Point& tile_coord, - const e_side& tile_border_side) { - - vtr::Point gsb_coord_range(L_device_rr_gsb.get_gsb_range().get_x(), L_device_rr_gsb.get_gsb_range().get_y()); - - vtr::Point gsb_coord(tile_coord.x(), tile_coord.y() - 1); - - /* We do NOT consider SB and CBs if the gsb is not in the range! */ - if ( (gsb_coord.x() < gsb_coord_range.x()) - && (gsb_coord.y() < gsb_coord_range.y()) ) { - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(gsb_coord.x(), gsb_coord.y()); - /* Find Switch Block: unique module id and instance id! - * Note that switch block does always exist in a GSB - */ - vtr::Point sb_coord(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - /* If we use compact routing hierarchy, we should instanciate the unique module of SB */ - if (true == compact_routing_hierarchy) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(DeviceCoordinator(sb_coord.x(), sb_coord.y())); - sb_coord.set_x(unique_mirror.get_sb_x()); - sb_coord.set_y(unique_mirror.get_sb_y()); - } - std::string sb_module_name = generate_switch_block_module_name(sb_coord); - ModuleId sb_module = module_manager.find_module(sb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); - - /* Identify if this sub module includes configuration bits, - * we will update the memory module and instance list - */ - if (0 < find_module_num_config_bits(module_manager, sb_module, - circuit_lib, sram_model, - sram_orgz_type)) { - module_manager.add_configurable_child(top_module, sb_module, sb_instance_ids[rr_gsb.get_sb_x()][rr_gsb.get_sb_y()]); - } - - /* Try to find and add CBX and CBY */ - organize_top_module_tile_cb_modules(module_manager, top_module, circuit_lib, - sram_orgz_type, sram_model, - cb_instance_ids.at(CHANX), - L_device_rr_gsb, rr_gsb, CHANX, - compact_routing_hierarchy); - - organize_top_module_tile_cb_modules(module_manager, top_module, circuit_lib, - sram_orgz_type, sram_model, - cb_instance_ids.at(CHANY), - L_device_rr_gsb, rr_gsb, CHANY, - compact_routing_hierarchy); - } - - /* Find the module name for this type of grid */ - t_type_ptr grid_type = grids[tile_coord.x()][tile_coord.y()].type; - - /* Skip EMPTY Grid */ - if (EMPTY_TYPE == grid_type) { - return; - } - /* Skip height>1 Grid, which should already been processed when offset=0 */ - if (0 < grids[tile_coord.x()][tile_coord.y()].offset) { - return; - } - - std::string grid_module_name_prefix(grid_verilog_file_name_prefix); - std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), IO_TYPE == grid_type, tile_border_side); - ModuleId grid_module = module_manager.find_module(grid_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); - - /* Identify if this sub module includes configuration bits, - * we will update the memory module and instance list - */ - if (0 < find_module_num_config_bits(module_manager, grid_module, - circuit_lib, sram_model, - sram_orgz_type)) { - module_manager.add_configurable_child(top_module, grid_module, grid_instance_ids[tile_coord.x()][tile_coord.y()]); - } -} - -/******************************************************************** - * Organize the list of memory modules and instances - * This function will record all the sub modules of the top-level module - * (those have memory ports) to two lists: - * 1. memory_modules records the module ids - * 2. memory_instances records the instance ids - * To keep a clean memory connection between sub modules and top-level module, - * the sequence of memory_modules and memory_instances will follow - * a chain of tiles considering their physical location - * - * Inter tile connection: - * +--------------------------------------------------------+ - * | +------+------+-----+------+ | - * | | I/O | I/O | ... | I/O | | - * | | TOP | TOP | | TOP | | - * | +------+------+-----+------+ | - * | +---------------------------------->tail | - * | +------+ | +------+------+-----+------+ +------+ | - * | | | | | | | | | | | | - * | | I/O | | | Tile | Tile | ... | Tile | | I/O | | - * | | LEFT | | | [h+1]| [h+2]| | [n] | |RIGHT | | - * | +------+ | +------+------+-----+------+ +------+ | - * | +-------------------------------+ | - * | ... ... ... ... ... | ... | - * | +-------------------------------+ | - * | +------+ | +------+------+-----+------+ +------+ | - * | | | | | | | | | | | | - * | | I/O | | | Tile | Tile | ... | Tile | | I/O | | - * | | LEFT | | | [i+1]| [i+2]| | [j] | |RIGHT | | - * | +------+ | +------+------+-----+------+ +------+ | - * | +-------------------------------+ | - * | +------+ +------+------+-----+------+ | +------+ | - * | | | | | | | | | | | | - * | | I/O | | Tile | Tile | ... | Tile | | | I/O | | - * | | LEFT | | [0] | [1] | | [i] | | |RIGHT | | - * | +------+ +------+------+-----+------+ | +------+ | - * +-------------------------------------------+ | - * +------+------+-----+------+ | - * | I/O | I/O | ... | I/O | | - * |BOTTOM|BOTTOM| |BOTTOM| | - * +------+------+-----+------+ | - * head >-----------------------------------------------+ - * - * Inner tile connection - * - * Tile - * +---------------+----------+ - * <-+---------------+ + | - * | | | | - * | CLB | | CBY | - * | +-|-+ | - * | | | | - * +---------------+----------+ - * | +-+----+-----+---<--- - * | CBX | SB | - * | | | - * +---------------+----------+ - * - *******************************************************************/ -void organize_top_module_memory_modules(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector>& sb_instance_ids, - const std::map>>& cb_instance_ids, - const bool& compact_routing_hierarchy) { - /* Ensure clean vectors to return */ - VTR_ASSERT(true == module_manager.configurable_children(top_module).empty()); - - /* First, organize the I/O tiles on the border */ - /* Special for the I/O tileas on RIGHT and BOTTOM, - * which are only I/O blocks, which do NOT contain CBs and SBs - */ - std::vector io_sides{BOTTOM, RIGHT, TOP, LEFT}; - std::map>> io_coords; - - /* BOTTOM side I/Os */ - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - io_coords[BOTTOM].push_back(vtr::Point(ix, 0)); - } - - /* RIGHT side I/Os */ - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - io_coords[RIGHT].push_back(vtr::Point(device_size.x() - 1, iy)); - } - - /* TOP side I/Os - * Special case for TOP side: We need tile at ix = 0, which has a SB!!! - * - * TOP-LEFT CORNER of FPGA fabric - * - * +--------+ +-------+ - * | EMPTY | | EMPTY | - * | Grid | | CBX | - * | [0][x] | | | - * +--------+ +-------+ - * +--------+ +--------+ - * | EMPTY | | SB | - * | CBX | | [0][x] | - * +--------+ +--------+ - * - */ - for (size_t ix = device_size.x() - 2; ix >= 1; --ix) { - io_coords[TOP].push_back(vtr::Point(ix, device_size.y() - 1)); - } - io_coords[TOP].push_back(vtr::Point(0, device_size.y() - 1)); - - /* LEFT side I/Os */ - for (size_t iy = device_size.y() - 2; iy >= 1; --iy) { - io_coords[LEFT].push_back(vtr::Point(0, iy)); - } - - for (const e_side& io_side : io_sides) { - for (const vtr::Point& io_coord : io_coords[io_side]) { - /* Identify the GSB that surrounds the grid */ - organize_top_module_tile_memory_modules(module_manager, top_module, - circuit_lib, sram_orgz_type, sram_model, - grids, grid_instance_ids, - L_device_rr_gsb, sb_instance_ids, cb_instance_ids, - compact_routing_hierarchy, - io_coord, io_side); - } - } - - /* For the core grids */ - std::vector> core_coords; - bool positive_direction = true; - for (size_t iy = 1; iy < device_size.y() - 1; ++iy) { - /* For positive direction: -----> */ - if (true == positive_direction) { - for (size_t ix = 1; ix < device_size.x() - 1; ++ix) { - core_coords.push_back(vtr::Point(ix, iy)); - } - } else { - VTR_ASSERT(false == positive_direction); - /* For negative direction: -----> */ - for (size_t ix = device_size.x() - 2; ix >= 1; --ix) { - core_coords.push_back(vtr::Point(ix, iy)); - } - } - /* Flip the positive direction to be negative */ - positive_direction = !positive_direction; - } - - for (const vtr::Point& core_coord : core_coords) { - organize_top_module_tile_memory_modules(module_manager, top_module, - circuit_lib, sram_orgz_type, sram_model, - grids, grid_instance_ids, - L_device_rr_gsb, sb_instance_ids, cb_instance_ids, - compact_routing_hierarchy, - core_coord, NUM_SIDES); - } -} - - -/********************************************************************* - * Add the port-to-port connection between all the memory modules - * and their parent module - * - * Create nets to wire the control signals of memory module to - * the configuration ports of primitive module - * - * Configuration Chain - * ------------------- - * - * config_bus (head) config_bus (tail) - * | ^ - * primitive | | - * +---------------------------------------------+ - * | | | | - * | v | | - * | +-------------------------------------+ | - * | | CMOS-based Memory Modules | | - * | +-------------------------------------+ | - * | | | | - * | v v | - * | sram_out sram_outb | - * | | - * +---------------------------------------------+ - * - * Memory bank - * ----------- - * - * config_bus (BL) config_bus (WL) - * | | - * primitive | | - * +---------------------------------------------+ - * | | | | - * | v v | - * | +-------------------------------------+ | - * | | CMOS-based Memory Modules | | - * | +-------------------------------------+ | - * | | | | - * | v v | - * | sram_out sram_outb | - * | | - * +---------------------------------------------+ - * - **********************************************************************/ -static -void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, - const ModuleId& parent_module, - const e_sram_orgz& sram_orgz_type) { - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* Nothing to do */ - break; - case SPICE_SRAM_SCAN_CHAIN: { - add_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, SPICE_SRAM_SCAN_CHAIN); - break; - } - case SPICE_SRAM_MEMORY_BANK: - /* TODO: */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } -} - - -/******************************************************************** - * TODO: - * Add the port-to-port connection between a memory module - * and the configuration bus of a primitive module - * - * Create nets to wire the control signals of memory module to - * the configuration ports of primitive module - * - * Primitive module - * +----------------------------+ - * | +--------+ | - * config | | | | - * ports --->|--------------->| Memory | | - * | | Module | | - * | | | | - * | +--------+ | - * +----------------------------+ - * The detailed config ports really depend on the type - * of SRAM organization. - * - * The config_bus in the argument is the reserved address of configuration - * bus in the parent_module for this memory module - * - * The configuration bus connection will depend not only - * the design technology of the memory cells but also the - * configuration styles of FPGA fabric. - * Here we will branch on the design technology - * - * Note: this function SHOULD be called after the pb_type_module is created - * and its child module (logic_module and memory_module) is created! - *******************************************************************/ -void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, - const ModuleId& parent_module, - const e_sram_orgz& sram_orgz_type, - const e_spice_model_design_tech& mem_tech) { - switch (mem_tech) { - case SPICE_MODEL_DESIGN_CMOS: - add_top_module_nets_cmos_memory_config_bus(module_manager, parent_module, - sram_orgz_type); - break; - case SPICE_MODEL_DESIGN_RRAM: - /* TODO: */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of memory design technology !\n", - __FILE__, __LINE__); - exit(1); - } -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h deleted file mode 100644 index 1ccc2b7d1..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef BUILD_TOP_MODULE_MEMORY_H -#define BUILD_TOP_MODULE_MEMORY_H - -#include -#include -#include "module_manager.h" -#include "spice_types.h" -#include "circuit_library.h" -#include "rr_blocks.h" - -void organize_top_module_memory_modules(ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model, - const vtr::Point& device_size, - const std::vector>& grids, - const std::vector>& grid_instance_ids, - const DeviceRRGSB& L_device_rr_gsb, - const std::vector>& sb_instance_ids, - const std::map>>& cb_instance_ids, - const bool& compact_routing_hierarchy); - -void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, - const ModuleId& parent_module, - const e_sram_orgz& sram_orgz_type, - const e_spice_model_design_tech& mem_tech); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_utils.cpp deleted file mode 100644 index 90d956fe6..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_utils.cpp +++ /dev/null @@ -1,86 +0,0 @@ -/******************************************************************** - * This file include most utilized functions for building the module - * graph for FPGA fabric - *******************************************************************/ -/* External library headers */ -#include "vtr_assert.h" - -/* FPGA-X2P headers */ -#include "device_coordinator.h" -#include "fpga_x2p_naming.h" -#include "rr_blocks.h" - -/* Module builder headers */ -#include "build_top_module_utils.h" - -/* Global variables should be the last to include */ -#include "globals.h" - -/******************************************************************** - * Generate the name for a grid block, by considering - * 1. if it locates on the border with given device size - * 2. its type - * - * This function is mainly used in the top-level module generation - *******************************************************************/ -std::string generate_grid_block_module_name_in_top_module(const std::string& prefix, - const vtr::Point& device_size, - const std::vector>& grids, - const vtr::Point& grid_coordinate) { - /* Determine if the grid locates at the border */ - e_side border_side = find_grid_border_side(device_size, grid_coordinate); - - return generate_grid_block_module_name(prefix, std::string(grids[grid_coordinate.x()][grid_coordinate.y()].type->name), - IO_TYPE == grids[grid_coordinate.x()][grid_coordinate.y()].type, border_side); -} - -/******************************************************************** - * Find the cb_type of a GSB in the top-level module - * depending on the side of SB - * TOP/BOTTOM side: CHANY - * RIGHT/LEFT side: CHANX - *******************************************************************/ -t_rr_type find_top_module_cb_type_by_sb_side(const e_side& sb_side) { - VTR_ASSERT(NUM_SIDES != sb_side); - - if ((TOP == sb_side) || (BOTTOM == sb_side)) { - return CHANY; - } - - VTR_ASSERT((RIGHT == sb_side) || (LEFT == sb_side)); - return CHANX; -} - -/******************************************************************** - * Find the GSB coordinate for a CB in the top-level module - * depending on the side of a SB - * TODO: use vtr::Point to replace DeviceCoordinator - *******************************************************************/ -DeviceCoordinator find_top_module_gsb_coordinate_by_sb_side(const RRGSB& rr_gsb, - const e_side& sb_side) { - VTR_ASSERT(NUM_SIDES != sb_side); - - DeviceCoordinator gsb_coordinate; - - if ((TOP == sb_side) || (LEFT == sb_side)) { - gsb_coordinate.set_x(rr_gsb.get_x()); - gsb_coordinate.set_y(rr_gsb.get_y()); - return gsb_coordinate; - } - - VTR_ASSERT((RIGHT == sb_side) || (BOTTOM == sb_side)); - - /* RIGHT side: x + 1 */ - if (RIGHT == sb_side) { - gsb_coordinate.set_x(rr_gsb.get_x() + 1); - gsb_coordinate.set_y(rr_gsb.get_y()); - } - - /* BOTTOM side: y - 1 */ - if (BOTTOM == sb_side) { - gsb_coordinate.set_x(rr_gsb.get_x()); - gsb_coordinate.set_y(rr_gsb.get_y() - 1); - } - - return gsb_coordinate; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_utils.h deleted file mode 100644 index 1901c78f2..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_utils.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef BUILD_TOP_MODULE_UTILS_H -#define BUILD_TOP_MODULE_UTILS_H - -#include -#include -#include "vtr_geometry.h" -#include "vpr_types.h" -#include "sides.h" - -std::string generate_grid_block_module_name_in_top_module(const std::string& prefix, - const vtr::Point& device_size, - const std::vector>& grids, - const vtr::Point& grid_coordinate); - -t_rr_type find_top_module_cb_type_by_sb_side(const e_side& sb_side); - -DeviceCoordinator find_top_module_gsb_coordinate_by_sb_side(const RRGSB& rr_gsb, - const e_side& sb_side); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp deleted file mode 100644 index fd7527b6d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp +++ /dev/null @@ -1,86 +0,0 @@ -/*********************************************** - * This file includes functions to generate - * Verilog submodules for wires. - **********************************************/ -#include -#include -#include - -#include "util.h" -#include "vtr_assert.h" - -/* Device-level header files */ -#include "module_manager.h" -#include "module_manager_utils.h" -#include "physical_types.h" -#include "vpr_types.h" - -/* FPGA-X2P context header files */ -#include "spice_types.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -/* FPGA-Verilog context header files */ -#include "verilog_global.h" -#include "build_wire_modules.h" - -/******************************************************************** - * Print a Verilog module of a regular wire segment - * Regular wire, which is 1-input and 1-output - * This type of wires are used in the local routing architecture - * +------+ - * input --->| wire |---> output - * +------+ - * - *******************************************************************/ -static -void build_wire_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const CircuitModelId& wire_model) { - /* Find the input port, output port*/ - std::vector input_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true); - std::vector output_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true, true); - - /* Makre sure the port size is what we want */ - VTR_ASSERT (1 == input_ports.size()); - VTR_ASSERT (1 == output_ports.size()); - VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0])); - VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - add_circuit_model_to_module_manager(module_manager, circuit_lib, wire_model); -} - -/******************************************************************** - * This function will only create wire modules with a number of - * ports that are defined by users. - * It will NOT insert any internal logic, which should be handled - * by Verilog/SPICE writers - *******************************************************************/ -void build_wire_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib) { - /* Start time count */ - clock_t t_start = clock(); - - vpr_printf(TIO_MESSAGE_INFO, - "Building wire modules..."); - - /* Print Verilog models for regular wires*/ - for (const auto& wire_model : circuit_lib.models_by_type(SPICE_MODEL_WIRE)) { - /* Bypass user-defined circuit models */ - if ( (!circuit_lib.model_spice_netlist(wire_model).empty()) - && (!circuit_lib.model_verilog_netlist(wire_model).empty()) ) { - continue; - } - build_wire_module(module_manager, circuit_lib, wire_model); - } - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %.2g seconds\n", - run_time_sec); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h deleted file mode 100644 index 193071526..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.h +++ /dev/null @@ -1,19 +0,0 @@ -/*********************************************** - * Header file for verilog_wire.cpp - **********************************************/ - -#ifndef BUILD_WIRE_MODULES_H -#define BUILD_WIRE_MODULES_H - -/* Include other header files which are dependency on the function declared below */ -#include -#include "physical_types.h" -#include "vpr_types.h" - -#include "circuit_library.h" -#include "module_manager.h" - -void build_wire_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c deleted file mode 100644 index 04a8dc24e..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c +++ /dev/null @@ -1,1375 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include SPICE support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_lut_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_rr_graph_utils.h" -#include "fpga_x2p_bitstream_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_globals.h" - -#include "fpga_x2p_pb_rr_graph.h" - -/* Count the number of rr_graph nodes that should be allocated - * (a) INPUT pins at the top-level pb_graph_node should be a local_rr_node and plus a SOURCE - * (b) CLOCK pins at the top-level pb_graph_node should be a local_rr_node and plus a SOURCE - * (c) OUTPUT pins at the top-level pb_graph_node should be a local_rr_node and plus a SINK - * (e) INPUT pins at a primitive pb_graph_node should be a local_rr_node and plus a SINK - * (f) CLOCK pins at a primitive pb_graph_node should be a local_rr_node and plus a SINK - * (g) OUTPUT pins at a primitive pb_graph_node should be a local_rr_node and plus a SOURCE - * (h) all the other pins should be a local_rr_node - */ -int rec_count_rr_graph_nodes_for_phy_pb_graph_node(t_pb_graph_node* cur_pb_graph_node) { - boolean is_top_pb_graph_node = (boolean) (NULL == cur_pb_graph_node->parent_pb_graph_node); - boolean is_primitive_pb_graph_node = (boolean) (NULL != cur_pb_graph_node->pb_type->spice_model); - int phy_mode_idx = -1; - int cur_num_rr_nodes = 0; - int ichild, ipb; - - /* Count in INPUT/OUTPUT/CLOCK pins as regular rr_nodes */ - cur_num_rr_nodes = count_pin_number_one_pb_graph_node(cur_pb_graph_node); - - /* check if this is a top pb_graph_node or a primitive node */ - if ((TRUE == is_top_pb_graph_node)||(TRUE == is_primitive_pb_graph_node)) { - /* Count in INPUT/OUTPUT/CLOCK pins as SINK/SOURCE rr_nodes */ - cur_num_rr_nodes += cur_num_rr_nodes; - } - - /* Return when this is a primitive node */ - if (TRUE == is_primitive_pb_graph_node) { - return cur_num_rr_nodes; - } - - /* Go recursively to the lower levels */ - /* Find the physical mode in the next level! */ - phy_mode_idx = find_pb_type_physical_mode_index(*(cur_pb_graph_node->pb_type)); - for (ichild = 0; ichild < cur_pb_graph_node->pb_type->modes[phy_mode_idx].num_pb_type_children; ichild++) { - /* num_pb is the number of such pb_type in a physical mode*/ - for (ipb = 0; ipb < cur_pb_graph_node->pb_type->modes[phy_mode_idx].pb_type_children[ichild].num_pb; ipb++) { - cur_num_rr_nodes += rec_count_rr_graph_nodes_for_phy_pb_graph_node(&cur_pb_graph_node->child_pb_graph_nodes[phy_mode_idx][ichild][ipb]); - } - } - - return cur_num_rr_nodes; -} - -void init_one_rr_node_pack_cost_for_phy_graph_node(INP t_pb_graph_pin* cur_pb_graph_pin, - INOUTP t_rr_graph* local_rr_graph, - int cur_rr_node_index, - enum PORTS port_type) { - switch (port_type) { - case IN_PORT: - /* Routing costs : INPUT pins - * need to normalize better than 5 and 10, bias router to use earlier inputs pins - */ - local_rr_graph->rr_node[cur_rr_node_index].pack_intrinsic_cost = 1 + 1 * (float) local_rr_graph->rr_node[cur_rr_node_index].num_edges / 5 - + 1 * ((float)cur_pb_graph_pin->pin_number / (float)cur_pb_graph_pin->port->num_pins) / (float)10; - break; - case OUT_PORT: - /* Routing costs : OUTPUT pins - * need to normalize better than 5 - */ - local_rr_graph->rr_node[cur_rr_node_index].pack_intrinsic_cost = 1 + 1 * (float) local_rr_graph->rr_node[cur_rr_node_index].num_edges / 5; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid rr_node_type (%d)! \n", - __FILE__, __LINE__, port_type); - exit(1); - } -} - - -/* Override the fan-in and fan-out for a top/primitive pb_graph_node */ -static -void override_one_rr_node_for_top_primitive_phy_pb_graph_node(INP t_pb_graph_pin* cur_pb_graph_pin, - INOUTP t_rr_graph* local_rr_graph, - int cur_rr_node_index, - boolean is_top_pb_graph_node, - boolean is_primitive_pb_graph_node) { - /* check : must be either a top_pb_graph_node or a primitive_pb_graph_node */ - if ((FALSE == is_top_pb_graph_node) && (FALSE == is_primitive_pb_graph_node)) { - return; - } - - /* depends on the port type */ - switch (cur_pb_graph_pin->port->type) { - case IN_PORT: - if (TRUE == is_top_pb_graph_node) { - /* Top-level IN_PORT should only has 1 fan-in */ - local_rr_graph->rr_node[cur_rr_node_index].fan_in = 1; - return; - } - if (TRUE == is_primitive_pb_graph_node) { - /* Primitive-level IN_PORT should only has 1 output edge */ - local_rr_graph->rr_node[cur_rr_node_index].num_edges = 1; - return; - } - break; - case OUT_PORT: - if (TRUE == is_top_pb_graph_node) { - /* Top-level OUT_PORT should only has 1 output edge */ - local_rr_graph->rr_node[cur_rr_node_index].num_edges = 1; - return; - } - if (TRUE == is_primitive_pb_graph_node) { - /* Primitive-level OUT_PORT should only has 1 fan-in */ - local_rr_graph->rr_node[cur_rr_node_index].fan_in = 1; - return; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid rr_node_type (%d)! \n", - __FILE__, __LINE__, cur_pb_graph_pin->port->type); - exit(1); - } - - return; -} - -/* initialize a rr_node in a rr_graph of phyical pb_graph_node */ -static -void init_one_rr_node_for_phy_pb_graph_node(INP t_pb_graph_pin* cur_pb_graph_pin, - INOUTP t_rr_graph* local_rr_graph, - int cur_rr_node_index, - int fan_in_phy_mode_index, - int fan_out_phy_mode_index, - t_rr_type rr_node_type, - boolean is_top_pb_graph_node, - boolean is_primitive_pb_graph_node) { - - switch (rr_node_type) { - case INTRA_CLUSTER_EDGE: - /* Link the rr_node to the pb_graph_pin*/ - cur_pb_graph_pin->rr_node_index_physical_pb = cur_rr_node_index; - local_rr_graph->rr_node[cur_rr_node_index].pb_graph_pin = cur_pb_graph_pin; - /* Get the number of input edges that belong to physical mode only! */ - local_rr_graph->rr_node[cur_rr_node_index].fan_in = count_pb_graph_node_input_edge_in_phy_mode(cur_pb_graph_pin, fan_in_phy_mode_index); - /* Get the number of output edges that belong to physical mode only! */ - local_rr_graph->rr_node[cur_rr_node_index].num_edges = count_pb_graph_node_output_edge_in_phy_mode(cur_pb_graph_pin, fan_out_phy_mode_index); - /* Override for special rr_nodes : at top-level and primitive nodes */ - override_one_rr_node_for_top_primitive_phy_pb_graph_node(cur_pb_graph_pin, local_rr_graph, cur_rr_node_index, - is_top_pb_graph_node, is_primitive_pb_graph_node); - /* Routing costs */ - init_one_rr_node_pack_cost_for_phy_graph_node(cur_pb_graph_pin, local_rr_graph, cur_rr_node_index, cur_pb_graph_pin->port->type); - break; - case SOURCE: - /* SOURCE only has one output and zero inputs */ - local_rr_graph->rr_node[cur_rr_node_index].pb_graph_pin = cur_pb_graph_pin; - local_rr_graph->rr_node[cur_rr_node_index].fan_in = 0; - local_rr_graph->rr_node[cur_rr_node_index].num_edges = 1; - /* Routing costs : SOURCE */ - init_one_rr_node_pack_cost_for_phy_graph_node(cur_pb_graph_pin, local_rr_graph, cur_rr_node_index, OUT_PORT); - break; - case SINK: - /* SINK only has one input and zero outputs */ - local_rr_graph->rr_node[cur_rr_node_index].pb_graph_pin = cur_pb_graph_pin; - local_rr_graph->rr_node[cur_rr_node_index].fan_in = 1; - local_rr_graph->rr_node[cur_rr_node_index].num_edges = 0; - /* Routing costs : SINK */ - local_rr_graph->rr_node[cur_rr_node_index].pack_intrinsic_cost = 1; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid rr_node_type (%d)! \n", - __FILE__, __LINE__, rr_node_type); - exit(1); - } - - /* Routing connectivity */ - local_rr_graph->rr_node[cur_rr_node_index].edges = (int *) my_calloc(local_rr_graph->rr_node[cur_rr_node_index].num_edges, sizeof(int)); - local_rr_graph->rr_node[cur_rr_node_index].switches = (short *) my_calloc(local_rr_graph->rr_node[cur_rr_node_index].num_edges, sizeof(short)); - local_rr_graph->rr_node[cur_rr_node_index].net_num = OPEN; - local_rr_graph->rr_node[cur_rr_node_index].prev_node = OPEN; - local_rr_graph->rr_node[cur_rr_node_index].prev_edge = OPEN; - - local_rr_graph->rr_node[cur_rr_node_index].capacity = 1; - local_rr_graph->rr_node[cur_rr_node_index].occ = 0; - local_rr_graph->rr_node[cur_rr_node_index].type = rr_node_type; - local_rr_graph->rr_node[cur_rr_node_index].cost_index = 0; - - return; -} - -/* Connect a rr_node in a rr_graph of phyical pb_graph_node, - * Assign the edges and switches - */ -void connect_one_rr_node_for_phy_pb_graph_node(INP t_pb_graph_pin* cur_pb_graph_pin, - INOUTP t_rr_graph* local_rr_graph, - int cur_rr_node_index, - int phy_mode_index, - t_rr_type rr_node_type) { - int iedge; - - /* Check: if type matches! */ - assert(rr_node_type == local_rr_graph->rr_node[cur_rr_node_index].type); - - switch (rr_node_type) { - case INTRA_CLUSTER_EDGE: { - /* Check out all the output_edges belonging to the same physical mode */ - int cur_edge = 0; - for (iedge = 0; iedge < cur_pb_graph_pin->num_output_edges; iedge++) { - check_pb_graph_edge(*(cur_pb_graph_pin->output_edges[iedge])); - /* Bypass fan-outs that are not in the physical mode */ - if (phy_mode_index != cur_pb_graph_pin->output_edges[iedge]->interconnect->parent_mode_index) { - continue; - } - assert ( cur_edge < local_rr_graph->rr_node[cur_rr_node_index].num_edges); - local_rr_graph->rr_node[cur_rr_node_index].edges[cur_edge] = cur_pb_graph_pin->output_edges[iedge]->output_pins[0]->rr_node_index_physical_pb; - local_rr_graph->rr_node[cur_rr_node_index].switches[cur_edge] = local_rr_graph->delayless_switch_index; - cur_edge++; - } - break; - } - case SOURCE: - /* Connect the SOURCE nodes to the rr_node of cur_pb_graph_pin */ - assert (0 == local_rr_graph->rr_node[cur_rr_node_index].fan_in); - assert (1 == local_rr_graph->rr_node[cur_rr_node_index].num_edges); - local_rr_graph->rr_node[cur_rr_node_index].edges[0] = cur_pb_graph_pin->rr_node_index_physical_pb; - local_rr_graph->rr_node[cur_rr_node_index].switches[0] = local_rr_graph->delayless_switch_index; - /* Fix the connection */ - local_rr_graph->rr_node[cur_pb_graph_pin->rr_node_index_physical_pb].prev_node = cur_rr_node_index; - local_rr_graph->rr_node[cur_pb_graph_pin->rr_node_index_physical_pb].prev_edge = 0; - break; - case SINK: - /* Connect the rr_node of cur_pb_graph_pin to the SINK */ - assert (1 == local_rr_graph->rr_node[cur_rr_node_index].fan_in); - assert (0 == local_rr_graph->rr_node[cur_rr_node_index].num_edges); - assert (1 == local_rr_graph->rr_node[cur_pb_graph_pin->rr_node_index_physical_pb].num_edges); - local_rr_graph->rr_node[cur_pb_graph_pin->rr_node_index_physical_pb].edges[0] = cur_rr_node_index; - local_rr_graph->rr_node[cur_pb_graph_pin->rr_node_index_physical_pb].switches[0] = local_rr_graph->delayless_switch_index; - /* Fix the connection */ - local_rr_graph->rr_node[cur_rr_node_index].prev_node = cur_pb_graph_pin->rr_node_index_physical_pb; - local_rr_graph->rr_node[cur_rr_node_index].prev_edge = 0; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid rr_node_type (%d)! \n", - __FILE__, __LINE__, rr_node_type); - exit(1); - } - - return; -} - - -/* Recursively configure all the rr_nodes in the rr_graph - * Initialize the routing cost, fan-in rr_nodes and fan-out rr_nodes, and switches - */ -static -void rec_init_rr_graph_for_phy_pb_graph_node(INP t_pb_graph_node* cur_pb_graph_node, - INOUTP t_rr_graph* local_rr_graph, - int* cur_rr_node_index) { - boolean is_top_pb_graph_node = (boolean) (NULL == cur_pb_graph_node->parent_pb_graph_node); - boolean is_primitive_pb_graph_node = (boolean) (NULL != cur_pb_graph_node->pb_type->spice_model); - int phy_mode_idx = -1; - int parent_phy_mode_idx = -1; - int iport, ipin; - int ichild, ipb; - - /* Find the physical mode in the next level! */ - phy_mode_idx = find_pb_type_physical_mode_index(*(cur_pb_graph_node->pb_type)); - /* There is no parent mode index for top-level node */ - if (FALSE == is_top_pb_graph_node) { - parent_phy_mode_idx = find_pb_type_physical_mode_index(*(cur_pb_graph_node->parent_pb_graph_node->pb_type)); - } else { - parent_phy_mode_idx = phy_mode_idx; - } - - /* Configure rr_nodes with the information of pb_graph_pin */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - init_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->input_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, parent_phy_mode_idx, phy_mode_idx, INTRA_CLUSTER_EDGE, - is_top_pb_graph_node, is_primitive_pb_graph_node); - (*cur_rr_node_index)++; - } - } - - /* Importantly, the interconnection for output ports belong to the parent pb_graph_node */ - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - init_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->output_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, phy_mode_idx, parent_phy_mode_idx, INTRA_CLUSTER_EDGE, - is_top_pb_graph_node, is_primitive_pb_graph_node); - (*cur_rr_node_index)++; - } - } - - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - init_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->clock_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, parent_phy_mode_idx, phy_mode_idx, INTRA_CLUSTER_EDGE, - is_top_pb_graph_node, is_primitive_pb_graph_node); - (*cur_rr_node_index)++; - } - } - - /* check if this is a top pb_graph_node */ - if ((TRUE == is_top_pb_graph_node)) { - /* Configure SOURCE and SINK rr_node: - * input_pins should have a SOURCE node - */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - init_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->input_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, phy_mode_idx, phy_mode_idx, SOURCE, - is_top_pb_graph_node, is_primitive_pb_graph_node); - - (*cur_rr_node_index)++; - } - } - /* Configure SOURCE and SINK rr_node: - * clock_pins should have a SOURCE node - */ - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - init_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->clock_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, phy_mode_idx, phy_mode_idx, SOURCE, - is_top_pb_graph_node, is_primitive_pb_graph_node); - - (*cur_rr_node_index)++; - } - } - - /* Configure SOURCE and SINK rr_node: - * output_pins should have a SINK node - */ - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - init_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->output_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, phy_mode_idx, phy_mode_idx, SINK, - is_top_pb_graph_node, is_primitive_pb_graph_node); - - (*cur_rr_node_index)++; - } - } - /* Finish adding SOURCE and SINKs */ - } - - /* Return when this is a primitive node */ - if (TRUE == is_primitive_pb_graph_node) { - /* Configure SOURCE and SINK rr_node: - * output_pins should have a SOURCE node - */ - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - init_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->output_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, phy_mode_idx, parent_phy_mode_idx, SOURCE, - is_top_pb_graph_node, is_primitive_pb_graph_node); - - (*cur_rr_node_index)++; - } - } - /* Configure SOURCE and SINK rr_node: - * input_pins should have a SINK node - */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - init_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->input_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, parent_phy_mode_idx, phy_mode_idx, SINK, - is_top_pb_graph_node, is_primitive_pb_graph_node); - - (*cur_rr_node_index)++; - } - } - /* Configure SOURCE and SINK rr_node: - * clock_pins should have a SINK node - */ - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - init_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->clock_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, parent_phy_mode_idx, phy_mode_idx, SINK, - is_top_pb_graph_node, is_primitive_pb_graph_node); - - (*cur_rr_node_index)++; - } - } - /* Finish adding SOURCE and SINKs */ - - return; - } - - /* Go recursively to the lower levels */ - for (ichild = 0; ichild < cur_pb_graph_node->pb_type->modes[phy_mode_idx].num_pb_type_children; ichild++) { - /* num_pb is the number of such pb_type in a physical mode*/ - for (ipb = 0; ipb < cur_pb_graph_node->pb_type->modes[phy_mode_idx].pb_type_children[ichild].num_pb; ipb++) { - rec_init_rr_graph_for_phy_pb_graph_node(&cur_pb_graph_node->child_pb_graph_nodes[phy_mode_idx][ichild][ipb], - local_rr_graph, cur_rr_node_index); - } - } - - return; -} - -/* Recursively connect all the rr_nodes in the rr_graph - * output_edges, output_switches - */ -static -void rec_connect_rr_graph_for_phy_pb_graph_node(INP t_pb_graph_node* cur_pb_graph_node, - INOUTP t_rr_graph* local_rr_graph, - int* cur_rr_node_index) { - boolean is_top_pb_graph_node = (boolean) (NULL == cur_pb_graph_node->parent_pb_graph_node); - boolean is_primitive_pb_graph_node = (boolean) (NULL != cur_pb_graph_node->pb_type->spice_model); - int phy_mode_idx = -1; - int parent_phy_mode_idx = -1; - int iport, ipin; - int ichild, ipb; - - /* Find the physical mode in the next level! */ - phy_mode_idx = find_pb_type_physical_mode_index(*(cur_pb_graph_node->pb_type)); - /* There is no parent mode index for top-level node */ - if (FALSE == is_top_pb_graph_node) { - parent_phy_mode_idx = find_pb_type_physical_mode_index(*(cur_pb_graph_node->parent_pb_graph_node->pb_type)); - } else { - parent_phy_mode_idx = phy_mode_idx; - } - - /* Configure rr_nodes with the information of pb_graph_pin */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - connect_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->input_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, phy_mode_idx, INTRA_CLUSTER_EDGE); - (*cur_rr_node_index)++; - } - } - - /* Importantly, the interconnection for output ports belong to the parent pb_graph_node */ - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - connect_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->output_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, parent_phy_mode_idx, INTRA_CLUSTER_EDGE); - (*cur_rr_node_index)++; - } - } - - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - connect_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->clock_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, phy_mode_idx, INTRA_CLUSTER_EDGE); - (*cur_rr_node_index)++; - } - } - - /* check if this is a top pb_graph_node */ - if ((TRUE == is_top_pb_graph_node)) { - /* Configure SOURCE and SINK rr_node: - * input_pins should have a SOURCE node - */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - connect_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->input_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, phy_mode_idx, SOURCE); - - (*cur_rr_node_index)++; - } - } - /* Configure SOURCE and SINK rr_node: - * clock_pins should have a SOURCE node - */ - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - connect_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->clock_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, phy_mode_idx, SOURCE); - - (*cur_rr_node_index)++; - } - } - /* Configure SOURCE and SINK rr_node: - * output_pins should have a SINK node - */ - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - connect_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->output_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, parent_phy_mode_idx, SINK); - - (*cur_rr_node_index)++; - } - } - /* Finish adding SOURCE and SINKs */ - } - - /* Return when this is a primitive node */ - if (TRUE == is_primitive_pb_graph_node) { - /* Configure SOURCE and SINK rr_node: - * output_pins should have a SOURCE node - */ - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - connect_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->output_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, parent_phy_mode_idx, SOURCE); - - (*cur_rr_node_index)++; - } - } - /* Configure SOURCE and SINK rr_node: - * input_pins should have a SINK node - */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - connect_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->input_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, phy_mode_idx, SINK); - - (*cur_rr_node_index)++; - } - } - /* Configure SOURCE and SINK rr_node: - * clock_pins should have a SINK node - */ - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - connect_one_rr_node_for_phy_pb_graph_node(&cur_pb_graph_node->clock_pins[iport][ipin], local_rr_graph, - *cur_rr_node_index, phy_mode_idx, SINK); - - (*cur_rr_node_index)++; - } - } - /* Finish adding SOURCE and SINKs */ - - return; - } - - /* Go recursively to the lower levels */ - for (ichild = 0; ichild < cur_pb_graph_node->pb_type->modes[phy_mode_idx].num_pb_type_children; ichild++) { - /* num_pb is the number of such pb_type in a physical mode*/ - for (ipb = 0; ipb < cur_pb_graph_node->pb_type->modes[phy_mode_idx].pb_type_children[ichild].num_pb; ipb++) { - rec_connect_rr_graph_for_phy_pb_graph_node(&cur_pb_graph_node->child_pb_graph_nodes[phy_mode_idx][ichild][ipb], - local_rr_graph, cur_rr_node_index); - } - } - - return; -} - -/* Allocate a rr_graph for a given pb_graph node - * This is function is a copy of alloc_and_load_rr_graph_for_pb_graph_node - * The major difference lies in removing the use of global variables - * This function does the following tasks: - * 1. Count all the pins in pb_graph_node (only those in physical modes) that can be a rr_node in the local rr_graph - * (a) INPUT pins at the top-level pb_graph_node should be a local_rr_node and plus a SOURCE - * (b) CLOCK pins at the top-level pb_graph_node should be a local_rr_node and plus a SOURCE - * (c) OUTPUT pins at the top-level pb_graph_node should be a local_rr_node and plus a SINK - * (e) INPUT pins at a primitive pb_graph_node should be a local_rr_node and plus a SINK - * (f) CLOCK pins at a primitive pb_graph_node should be a local_rr_node and plus a SINK - * (g) OUTPUT pins at a primitive pb_graph_node should be a local_rr_node and plus a SOURCE - * (h) all the other pins should be a local_rr_node - * 2. Allocate the rr_graph and initialize its properties according to the pb_graph_pin interconnections - * capacity, mapped net name, edges, switches, routing cost information - * 3. Synchronize mapped_net_name from a mapped pb: - * (a) give mapped_net_name to INPUT/OUTPUT/CLOCK pins of the top-level pb_graph_node - * (b) give mapped_net_name to INPUT/OUTPUT/CLOCK pins of the primitive pb_graph_nodes - */ -void alloc_and_load_rr_graph_for_phy_pb_graph_node(INP t_pb_graph_node* top_pb_graph_node, - OUTP t_rr_graph* local_rr_graph) { - - int phy_pb_num_rr_nodes, check_point; - - /* Count the number of rr_nodes that are required */ - phy_pb_num_rr_nodes = rec_count_rr_graph_nodes_for_phy_pb_graph_node(top_pb_graph_node); - - /* Allocate rr_graph */ - alloc_and_load_rr_graph_rr_node(local_rr_graph, phy_pb_num_rr_nodes); - - /* Fill basic information for the rr_graph */ - check_point = 0; - rec_init_rr_graph_for_phy_pb_graph_node(top_pb_graph_node, local_rr_graph, &check_point); - assert (check_point == local_rr_graph->num_rr_nodes); - - /* Fill edges and switches for the rr_graph */ - check_point = 0; - rec_connect_rr_graph_for_phy_pb_graph_node(top_pb_graph_node, local_rr_graph, &check_point); - assert (check_point == local_rr_graph->num_rr_nodes); - - return; -} - -/* Check the vpack_net_num of a rr_node mapped to a pb_graph_pin and - * mark the used vpack_net_num in the list - */ -static -void mark_vpack_net_used_in_pb_pin(t_pb* cur_op_pb, t_pb_graph_pin* cur_pb_graph_pin, - int L_num_vpack_nets, boolean* vpack_net_used_in_pb) { - int inode; - - assert (NULL != cur_pb_graph_pin); - - inode = cur_pb_graph_pin->pin_count_in_cluster; - - /* bypass unmapped rr_node */ - if (OPEN == cur_op_pb->rr_graph[inode].vpack_net_num) { - return; - } - /* Reach here, it means this net is used in this pb */ - assert( (-1 < cur_op_pb->rr_graph[inode].vpack_net_num) - && ( cur_op_pb->rr_graph[inode].vpack_net_num < L_num_vpack_nets)); - vpack_net_used_in_pb[cur_op_pb->rr_graph[inode].vpack_net_num] = TRUE; - - return; -} - -/* Recursively visit all the child pbs and - * mark the used vpack_net_num in the list - */ -static -void mark_vpack_net_used_in_pb(t_pb* cur_op_pb, - int L_num_vpack_nets, boolean* vpack_net_used_in_pb) { - int mode_index, ipb, jpb; - int iport, ipin; - t_pb_type* cur_pb_type = NULL; - - cur_pb_type = cur_op_pb->pb_graph_node->pb_type; - mode_index = cur_op_pb->mode; - - /* Mark all the nets at this level */ - for (iport = 0; iport < cur_op_pb->pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_op_pb->pb_graph_node->num_input_pins[iport]; ipin++) { - mark_vpack_net_used_in_pb_pin(cur_op_pb, &(cur_op_pb->pb_graph_node->input_pins[iport][ipin]), - L_num_vpack_nets, vpack_net_used_in_pb); - } - } - - for (iport = 0; iport < cur_op_pb->pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_op_pb->pb_graph_node->num_output_pins[iport]; ipin++) { - mark_vpack_net_used_in_pb_pin(cur_op_pb, &(cur_op_pb->pb_graph_node->output_pins[iport][ipin]), - L_num_vpack_nets, vpack_net_used_in_pb); - } - } - - for (iport = 0; iport < cur_op_pb->pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_op_pb->pb_graph_node->num_clock_pins[iport]; ipin++) { - mark_vpack_net_used_in_pb_pin(cur_op_pb, &(cur_op_pb->pb_graph_node->clock_pins[iport][ipin]), - L_num_vpack_nets, vpack_net_used_in_pb); - } - } - - /* recursive for the child_pbs*/ - if (FALSE == is_primitive_pb_type(cur_pb_type)) { - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Recursive*/ - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != cur_op_pb->child_pbs[ipb])&&(NULL != cur_op_pb->child_pbs[ipb][jpb].name)) { - mark_vpack_net_used_in_pb(&(cur_op_pb->child_pbs[ipb][jpb]), - L_num_vpack_nets, vpack_net_used_in_pb); - } - } - } - } - - return; -} - -/* Find the vpack_nets used by this pb - * And allocate an array for those nets and load it to pb_rr_graph - */ -void alloc_and_load_phy_pb_rr_graph_nets(INP t_pb* cur_op_pb, - t_rr_graph* local_rr_graph, - int L_num_vpack_nets, t_net* L_vpack_net) { - /* Create an array labeling which vpack_net is used in this pb */ - int num_vpack_net_used_in_pb = 0; - boolean* vpack_net_used_in_pb = NULL; - int inet, net_index; - - /* Allocate */ - vpack_net_used_in_pb = (boolean*)my_malloc(sizeof(boolean) * L_num_vpack_nets); - /* Initial to FALSE */ - for (inet = 0; inet < L_num_vpack_nets; inet++) { - vpack_net_used_in_pb[inet] = FALSE; - } - - /* Build vpack_net_used_in_pb */ - mark_vpack_net_used_in_pb(cur_op_pb, L_num_vpack_nets, vpack_net_used_in_pb); - - /* Count the number of vpack_net used in this pb */ - num_vpack_net_used_in_pb = 0; - for (inet = 0; inet < L_num_vpack_nets; inet++) { - if (TRUE == vpack_net_used_in_pb[inet]) { - num_vpack_net_used_in_pb++; - } - } - - /* Allocate net for rr_graph */ - local_rr_graph->num_nets = num_vpack_net_used_in_pb; - local_rr_graph->net = (t_net**) my_malloc(sizeof(t_net*) * local_rr_graph->num_nets); - local_rr_graph->net_to_vpack_net_mapping = (int*) my_malloc(sizeof(int) * local_rr_graph->num_nets); - - /* Fill the net array and net_to_net_mapping */ - net_index = 0; - for (inet = 0; inet < L_num_vpack_nets; inet++) { - if (TRUE == vpack_net_used_in_pb[inet]) { - local_rr_graph->net[net_index] = &L_vpack_net[inet]; - local_rr_graph->net_to_vpack_net_mapping[net_index] = inet; - net_index++; - } - } - assert( net_index == local_rr_graph->num_nets ); - - return; -} - -/* Find the rr_node in the primitive node of a pb_rr_graph*/ -static -void sync_pb_graph_pin_vpack_net_num_to_phy_pb(t_rr_node* cur_op_pb_rr_graph, - t_pb_graph_pin* cur_pb_graph_pin, - t_rr_graph* local_rr_graph) { - int inode, jnode, iedge, next_node; - int rr_node_net_num; - - inode = cur_pb_graph_pin->pin_count_in_cluster; - /* bypass non-exist physical pb_graph_pins */ - if (NULL == cur_pb_graph_pin->physical_pb_graph_pin) { - return; - } - jnode = cur_pb_graph_pin->physical_pb_graph_pin->rr_node_index_physical_pb; - - /* If we have a valid vpack_net_num */ - if (OPEN == cur_op_pb_rr_graph[inode].vpack_net_num) { - /* Do not overwrite because this rr_node may have been updated! */ - /* - local_rr_graph->rr_node[jnode].net_num = OPEN; - local_rr_graph->rr_node[jnode].vpack_net_num = OPEN; - */ - return; - } - - /* Synchronize depending on the rr_node type */ - switch (local_rr_graph->rr_node[jnode].type) { - case SOURCE: - case SINK: - /* SOURCE or SINK: we are done, just synchronize the vpack_net_num and we can return*/ - rr_node_net_num = get_rr_graph_net_index_with_vpack_net(local_rr_graph, cur_op_pb_rr_graph[inode].vpack_net_num); - assert (( -1 < rr_node_net_num ) && (rr_node_net_num < local_rr_graph->num_nets)); - local_rr_graph->rr_node[jnode].net_num = rr_node_net_num; - local_rr_graph->rr_node[jnode].vpack_net_num = cur_op_pb_rr_graph[inode].vpack_net_num; - break; - case INTRA_CLUSTER_EDGE: - /* We need to find a SOURCE or a SINK nodes! */ - /* Check driving rr_nodes */ - for (iedge = 0; iedge < local_rr_graph->rr_node[jnode].num_drive_rr_nodes; iedge++) { - if (SOURCE != local_rr_graph->rr_node[jnode].drive_rr_nodes[iedge]->type) { - continue; - } - /* Give the vpack_net_num to the SOURCE nodes */ - rr_node_net_num = get_rr_graph_net_index_with_vpack_net(local_rr_graph, cur_op_pb_rr_graph[inode].vpack_net_num); - assert (( -1 < rr_node_net_num ) && (rr_node_net_num < local_rr_graph->num_nets)); - local_rr_graph->rr_node[jnode].drive_rr_nodes[iedge]->net_num = rr_node_net_num; - local_rr_graph->rr_node[jnode].drive_rr_nodes[iedge]->vpack_net_num = cur_op_pb_rr_graph[inode].vpack_net_num; - } - /* Check the output rr_nodes */ - for (iedge = 0; iedge < local_rr_graph->rr_node[jnode].num_edges; iedge++) { - next_node = local_rr_graph->rr_node[jnode].edges[iedge]; - if (SINK != local_rr_graph->rr_node[next_node].type) { - continue; - } - /* Give the vpack_net_num to the SOURCE nodes */ - rr_node_net_num = get_rr_graph_net_index_with_vpack_net(local_rr_graph, cur_op_pb_rr_graph[inode].vpack_net_num); - assert (( -1 < rr_node_net_num ) && (rr_node_net_num < local_rr_graph->num_nets)); - local_rr_graph->rr_node[next_node].net_num = rr_node_net_num; - local_rr_graph->rr_node[next_node].vpack_net_num = cur_op_pb_rr_graph[inode].vpack_net_num; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid rr_node_type (%d)! \n", - __FILE__, __LINE__, local_rr_graph->rr_node[jnode].type); - exit(1); - } - - return; -} - -static -void rec_sync_wired_pb_vpack_net_num_to_phy_pb_rr_graph(t_pb_graph_node* cur_pb_graph_node, - t_rr_node* op_pb_rr_graph, - t_rr_graph* local_rr_graph) { - int imode, ipb, jpb; - int ipin, iport; - t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; - - /* Copy LUT information if this is a leaf node */ - if ((TRUE == is_primitive_pb_type(cur_pb_type)) - && (LUT_CLASS == cur_pb_type->class_type)) { - /* Mark all the nets at this level */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - sync_pb_graph_pin_vpack_net_num_to_phy_pb(op_pb_rr_graph, - &(cur_pb_graph_node->input_pins[iport][ipin]), - local_rr_graph); - } - } - - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - sync_pb_graph_pin_vpack_net_num_to_phy_pb(op_pb_rr_graph, - &(cur_pb_graph_node->output_pins[iport][ipin]), - local_rr_graph); - } - } - - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - sync_pb_graph_pin_vpack_net_num_to_phy_pb(op_pb_rr_graph, - &(cur_pb_graph_node->clock_pins[iport][ipin]), - local_rr_graph); - } - } - - /* Finish here */ - return; - } - - /* Go recursively */ - assert (FALSE == is_primitive_pb_type(cur_pb_type)); - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[imode].pb_type_children[ipb].num_pb; jpb++) { - /* We care only those have been used for wiring */ - if (FALSE == is_pb_used_for_wiring(&(cur_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), - &(cur_pb_type->modes[imode].pb_type_children[ipb]), - op_pb_rr_graph)) { - continue; - } - rec_sync_wired_pb_vpack_net_num_to_phy_pb_rr_graph(&(cur_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), - op_pb_rr_graph, - local_rr_graph); - } - } - } - - return; -} - -/* Recursively visit all the child pbs and - * synchronize the vpack_net_num of the top-level/primitive pb_graph_pin - * to the physical pb rr_node nodes - */ -static -void rec_sync_pb_vpack_net_num_to_phy_pb_rr_graph(t_pb* cur_op_pb, - t_rr_graph* local_rr_graph) { - int mode_index, ipb, jpb; - int iport, ipin; - t_pb_type* cur_pb_type = NULL; - - cur_pb_type = cur_op_pb->pb_graph_node->pb_type; - mode_index = cur_op_pb->mode; - - /* Mark all the nets at this level */ - for (iport = 0; iport < cur_op_pb->pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_op_pb->pb_graph_node->num_input_pins[iport]; ipin++) { - sync_pb_graph_pin_vpack_net_num_to_phy_pb(cur_op_pb->rr_graph, - &(cur_op_pb->pb_graph_node->input_pins[iport][ipin]), - local_rr_graph); - } - } - - for (iport = 0; iport < cur_op_pb->pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_op_pb->pb_graph_node->num_output_pins[iport]; ipin++) { - sync_pb_graph_pin_vpack_net_num_to_phy_pb(cur_op_pb->rr_graph, - &(cur_op_pb->pb_graph_node->output_pins[iport][ipin]), - local_rr_graph); - } - } - - for (iport = 0; iport < cur_op_pb->pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_op_pb->pb_graph_node->num_clock_pins[iport]; ipin++) { - sync_pb_graph_pin_vpack_net_num_to_phy_pb(cur_op_pb->rr_graph, - &(cur_op_pb->pb_graph_node->clock_pins[iport][ipin]), - local_rr_graph); - } - } - - /* Return if we reach the primitive */ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - return; - } - - /* recursive for the child_pbs*/ - assert (FALSE == is_primitive_pb_type(cur_pb_type)); - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != cur_op_pb->child_pbs[ipb])&&(NULL != cur_op_pb->child_pbs[ipb][jpb].name)) { - rec_sync_pb_vpack_net_num_to_phy_pb_rr_graph(&(cur_op_pb->child_pbs[ipb][jpb]), - local_rr_graph); - } else if (TRUE == is_pb_used_for_wiring(&(cur_op_pb->pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), - &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), - cur_op_pb->rr_graph)) { - /* Identify pbs and LUTs that are used for wiring purpose */ - rec_sync_wired_pb_vpack_net_num_to_phy_pb_rr_graph(&(cur_op_pb->pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), - cur_op_pb->rr_graph, - local_rr_graph); - } - } - } - - return; -} - - -/* Load mapping information from an op_pb to the net_rr_terminals of a phy_pb rr_graph - * This function should do the following tasks: - * 1. Find mapped pb_graph_pin in the rr_graph of cur_op_pb - * 2. Locate the pin-to-pin annotation in the pb_graph_pin of cur_op_pb - * and find the corresponding pb_graph_pin in local_rr_graph (phy_pb) - * 3. Find the SOURCE and SINK rr_nodes related to the pb_graph_pin - * 4. Configure the net_rr_terminals with the SINK/SOURCE rr_nodes - */ -static -void alloc_and_load_phy_pb_rr_graph_net_rr_terminals(INP t_pb* cur_op_pb, - t_rr_graph* local_rr_graph) { - int inet, inode, rr_node_net_name; - int* net_cur_terminal = (int*) my_calloc(local_rr_graph->num_nets, sizeof(int)); - int* net_cur_source = (int*) my_calloc(local_rr_graph->num_nets, sizeof(int)); - int* net_cur_sink = (int*) my_calloc(local_rr_graph->num_nets, sizeof(int)); - - /* Initialize */ - for (inet = 0; inet < local_rr_graph->num_nets; inet++) { - /* SINK index starts from 1!!!*/ - net_cur_terminal[inet] = 1; - net_cur_source[inet] = 0; - net_cur_sink[inet] = 0; - } - - /* Check each net in the local_rr_graph, - * Find the routing resource node in the pb_rr_graph of the cur_op_pb - * and annotate in the local_rr_graph - * assign the net_rr_terminal with the node index in the local_rr_graph - * Two steps to go: - * 1. synchronize the vpack_net_num of pb_graph_pin (rr_node) in op_pb - * to the local rr_graph (SINK and SOURCE nodes!) - * 2. Annotate the net_rr_terminals by sweeping the rr_node in local_rr_graph - */ - rec_sync_pb_vpack_net_num_to_phy_pb_rr_graph(cur_op_pb, - local_rr_graph); - - /* Allocate net_rr_terminals */ - alloc_rr_graph_net_rr_terminals(local_rr_graph); - /* Some nets may have two sources nodes to route - * We store the sources node in the net_rr_sources list - * We keep a list for the sink nodes - * in the net_rr_sinks list - */ - alloc_rr_graph_net_rr_sources_and_sinks(local_rr_graph); - - for (inode = 0; inode < local_rr_graph->num_rr_nodes; inode++) { - /* We only care the SOURCE and SINK nodes */ - switch (local_rr_graph->rr_node[inode].type) { - case SOURCE: - /* SOURCE is easy: give the rr_node id to first terminal of the vpack_net */ - rr_node_net_name = local_rr_graph->rr_node[inode].net_num; - if (OPEN == rr_node_net_name) { - break; - } - local_rr_graph->net_rr_terminals[rr_node_net_name][0] = inode; - /* Store in the source and sink lists */ - local_rr_graph->net_rr_sources[rr_node_net_name][net_cur_source[rr_node_net_name]] = inode; - /* Update the counter */ - net_cur_source[rr_node_net_name]++; - break; - case SINK: - /* SINK: we need to record the sink we considered */ - rr_node_net_name = local_rr_graph->rr_node[inode].net_num; - if (OPEN == rr_node_net_name) { - break; - } - /* Make sure we do not overwrite on the source */ - assert ( 0 < net_cur_terminal[rr_node_net_name] ); - local_rr_graph->net_rr_terminals[rr_node_net_name][net_cur_terminal[rr_node_net_name]] = inode; - net_cur_terminal[rr_node_net_name]++; - /* Store in the source and sink lists */ - local_rr_graph->net_rr_sinks[rr_node_net_name][net_cur_sink[rr_node_net_name]] = inode; - /* Update the counter */ - net_cur_sink[rr_node_net_name]++; - break; - case INTRA_CLUSTER_EDGE: - /* Nothing to do */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid rr_node_type (%d)! \n", - __FILE__, __LINE__, local_rr_graph->rr_node[inode].type); - exit(1); - } - } - /* Check */ - for (inet = 0; inet < local_rr_graph->num_nets; inet++) { - /* Count in the first node is SOURCE not the SINK */ - assert ( net_cur_terminal[inet] == local_rr_graph->net_num_sinks[inet] + 1); - assert ( net_cur_source[inet] == local_rr_graph->net_num_sources[inet]); - assert ( net_cur_sink[inet] == local_rr_graph->net_num_sinks[inet]); - } - - /* Free */ - my_free(net_cur_terminal); - my_free(net_cur_source); - my_free(net_cur_sink); - - return; -} - -static -void alloc_pb_rr_graph_rr_indexed_data(t_rr_graph* local_rr_graph) { - /* inside a cluster, I do not consider rr_indexed_data cost, set to 1 since other costs are multiplied by it */ - alloc_rr_graph_rr_indexed_data(local_rr_graph, 1); - local_rr_graph->rr_indexed_data[0].base_cost = 1.; - - return; -} - -/* Reach here means that this LUT is in wired mode (a buffer) - * Add an output edge to the rr_node of the used input - * connect it to the rr_node of the used LUT output - */ -static -void add_rr_node_edge_to_one_wired_lut(t_pb_graph_node* cur_pb_graph_node, - t_rr_node* op_pb_rr_graph, - t_rr_graph* local_rr_graph) { - int iport, ipin; - int jport, jpin; - int iedge; - int lut_input_rr_node_index, lut_output_rr_node_index; - int num_used_lut_input_pins = 0; - int num_used_lut_output_pins = 0; - int temp_rr_node_index; - int wired_lut_net_num = OPEN; - boolean exist = FALSE; - int cnt = 0; - - num_used_lut_input_pins = 0; - lut_input_rr_node_index = OPEN; - - /* Find the used input pin of this LUT and rr_node in the graph */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - temp_rr_node_index = cur_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster; - /* Force the vpack_net_num from net_name here */ - if ((OPEN != op_pb_rr_graph[temp_rr_node_index].net_num) - && (OPEN == op_pb_rr_graph[temp_rr_node_index].vpack_net_num)) { - op_pb_rr_graph[temp_rr_node_index].vpack_net_num = op_pb_rr_graph[temp_rr_node_index].net_num; - } - if (OPEN != op_pb_rr_graph[temp_rr_node_index].vpack_net_num) { - num_used_lut_input_pins++; - wired_lut_net_num = op_pb_rr_graph[temp_rr_node_index].vpack_net_num; - lut_input_rr_node_index = cur_pb_graph_node->input_pins[iport][ipin].physical_pb_graph_pin->rr_node_index_physical_pb; - } - /* If we did not find one, finish this round, otherwise set it to zero and edges */ - if (0 == num_used_lut_input_pins) { - continue; - } else { - assert (1 == num_used_lut_input_pins); - num_used_lut_input_pins = 0; - } - - /* Find the used output*/ - num_used_lut_output_pins = 0; - lut_output_rr_node_index = OPEN; - /* Find the used output pin of this LUT and rr_node in the graph */ - for (jport = 0; jport < cur_pb_graph_node->num_output_ports; jport++) { - for (jpin = 0; jpin < cur_pb_graph_node->num_output_pins[jport]; jpin++) { - temp_rr_node_index = cur_pb_graph_node->output_pins[jport][jpin].pin_count_in_cluster; - /* Force the vpack_net_num from net_name here */ - if ((OPEN != op_pb_rr_graph[temp_rr_node_index].net_num) - && (OPEN == op_pb_rr_graph[temp_rr_node_index].vpack_net_num)) { - op_pb_rr_graph[temp_rr_node_index].vpack_net_num = op_pb_rr_graph[temp_rr_node_index].net_num; - } - if (wired_lut_net_num == op_pb_rr_graph[temp_rr_node_index].vpack_net_num) { - num_used_lut_output_pins++; - lut_output_rr_node_index = cur_pb_graph_node->output_pins[jport][jpin].physical_pb_graph_pin->rr_node_index_physical_pb; - } - } - } - /* Make sure we only have 1 used output pin */ - assert ((1 == num_used_lut_output_pins) - && (OPEN != lut_output_rr_node_index)); - - /* Add a special edge between the two rr_nodes */ - /* Check if the lut_output_rr_node is already in the edge list */ - exist = FALSE; - for (iedge = 0; iedge < local_rr_graph->rr_node[lut_input_rr_node_index].num_edges; iedge++) { - if (lut_output_rr_node_index == local_rr_graph->rr_node[lut_input_rr_node_index].edges[iedge]) { - exist = TRUE; - break; - } - } - if (FALSE == exist) { - /* Modify the input(source) node */ - local_rr_graph->rr_node[lut_input_rr_node_index].num_edges++; - local_rr_graph->rr_node[lut_input_rr_node_index].edges = (int*) my_realloc(local_rr_graph->rr_node[lut_input_rr_node_index].edges, - local_rr_graph->rr_node[lut_input_rr_node_index].num_edges * sizeof(int)); - local_rr_graph->rr_node[lut_input_rr_node_index].edges[local_rr_graph->rr_node[lut_input_rr_node_index].num_edges -1] = lut_output_rr_node_index; - local_rr_graph->rr_node[lut_input_rr_node_index].switches = (short*) my_realloc(local_rr_graph->rr_node[lut_input_rr_node_index].switches, - local_rr_graph->rr_node[lut_input_rr_node_index].num_edges * sizeof(short)); - local_rr_graph->rr_node[lut_input_rr_node_index].switches[local_rr_graph->rr_node[lut_input_rr_node_index].num_edges -1] = DEFAULT_SWITCH_ID; - } - - /* Check if the lut_input_rr_node is already in the drive_rr_node list */ - exist = FALSE; - for (iedge = 0; iedge < local_rr_graph->rr_node[lut_output_rr_node_index].num_drive_rr_nodes; iedge++) { - if (&(local_rr_graph->rr_node[lut_input_rr_node_index]) == local_rr_graph->rr_node[lut_output_rr_node_index].drive_rr_nodes[iedge]) { - exist = TRUE; - break; - } - } - if (FALSE == exist) { - /* Modify the output(destination) node */ - local_rr_graph->rr_node[lut_output_rr_node_index].fan_in++; - local_rr_graph->rr_node[lut_output_rr_node_index].num_drive_rr_nodes++; - local_rr_graph->rr_node[lut_output_rr_node_index].drive_rr_nodes = (t_rr_node**) my_realloc(local_rr_graph->rr_node[lut_output_rr_node_index].drive_rr_nodes, - local_rr_graph->rr_node[lut_output_rr_node_index].num_drive_rr_nodes * sizeof(t_rr_node*)); - local_rr_graph->rr_node[lut_output_rr_node_index].drive_rr_nodes[local_rr_graph->rr_node[lut_output_rr_node_index].num_drive_rr_nodes - 1] = &(local_rr_graph->rr_node[lut_input_rr_node_index]); - - local_rr_graph->rr_node[lut_output_rr_node_index].drive_switches = (int*) my_realloc(local_rr_graph->rr_node[lut_output_rr_node_index].drive_switches, - local_rr_graph->rr_node[lut_output_rr_node_index].num_drive_rr_nodes * sizeof(int)); - local_rr_graph->rr_node[lut_output_rr_node_index].drive_switches[local_rr_graph->rr_node[lut_output_rr_node_index].num_drive_rr_nodes - 1] = DEFAULT_SWITCH_ID; - } - /* Update counter */ - cnt++; - } - } - - /* vpr_printf(TIO_MESSAGE_INFO, "Added %d rr_node edge for wired LUT\n", cnt); */ - - return; -} - -/* Add rr edges connecting from an input of a LUT to its output - * IMPORTANT: this is only applied to LUT which operates in wire mode (a buffer) - */ -static -void rec_add_unused_rr_graph_wired_lut_rr_edges(INP t_pb_graph_node* cur_op_pb_graph_node, - INP t_rr_node* cur_op_pb_rr_graph, - INOUTP t_rr_graph* local_rr_graph) { - int imode, ipb, jpb; - t_pb_type* cur_pb_type = NULL; - - cur_pb_type = cur_op_pb_graph_node->pb_type; - - /* Go recursively until we reach a primitive node which is a LUT */ - - /* Return if we reach the primitive */ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - /* We only care the LUTs, that is in wired mode */ - if (TRUE == is_pb_wired_lut(cur_op_pb_graph_node, - cur_pb_type, - cur_op_pb_rr_graph)) { - - /* Reach here means that this LUT is in wired mode (a buffer) - * Add an output edge to the rr_node of the used input - * connect it to the rr_node of the used LUT output - */ - add_rr_node_edge_to_one_wired_lut(cur_op_pb_graph_node, - cur_op_pb_rr_graph, - local_rr_graph); - } - return; - } - - /* recursive for the child_pbs*/ - assert (FALSE == is_primitive_pb_type(cur_pb_type)); - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - for (ipb = 0; ipb < cur_pb_type->modes[imode].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[imode].pb_type_children[ipb].num_pb; jpb++) { - /* We only care those used for wiring */ - if (FALSE == is_pb_used_for_wiring(&(cur_op_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), - &(cur_pb_type->modes[imode].pb_type_children[ipb]), - cur_op_pb_rr_graph)) { - continue; - } - rec_add_unused_rr_graph_wired_lut_rr_edges(&(cur_op_pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), - cur_op_pb_rr_graph, - local_rr_graph); - } - } - } - - return; -} - - -/* Add rr edges connecting from an input of a LUT to its output - * IMPORTANT: this is only applied to LUT which operates in wire mode (a buffer) - */ -static -void rec_add_rr_graph_wired_lut_rr_edges(INP t_pb* cur_op_pb, - INOUTP t_rr_graph* local_rr_graph) { - int mode_index, ipb, jpb, imode; - t_pb_type* cur_pb_type = NULL; - - cur_pb_type = cur_op_pb->pb_graph_node->pb_type; - mode_index = cur_op_pb->mode; - - /* Go recursively until we reach a primitive node which is a LUT */ - - /* Return if we reach the primitive */ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - /* We only care the LUTs, that is in wired mode */ - if ((LUT_CLASS == cur_pb_type->class_type) - && (WIRED_LUT_MODE_INDEX == mode_index)) { - /* Reach here means that this LUT is in wired mode (a buffer) - * Add an output edge to the rr_node of the used input - * connect it to the rr_node of the used LUT output - */ - add_rr_node_edge_to_one_wired_lut(cur_op_pb->pb_graph_node, - cur_op_pb->rr_graph, - local_rr_graph); - } - return; - } - - /* recursive for the child_pbs*/ - assert (FALSE == is_primitive_pb_type(cur_pb_type)); - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Recursive*/ - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != cur_op_pb->child_pbs[ipb])&&(NULL != cur_op_pb->child_pbs[ipb][jpb].name)) { - rec_add_rr_graph_wired_lut_rr_edges(&(cur_op_pb->child_pbs[ipb][jpb]), - local_rr_graph); - } else if (TRUE == is_pb_used_for_wiring(&(cur_op_pb->pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), - &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), - cur_op_pb->rr_graph)) { - /* We need to extend this part: - * Some open op_pb contains wired LUTs - * We need go further into the hierarchy and find out the wired LUTs - */ - for (imode = 0; imode < cur_pb_type->num_modes; imode++) { - rec_add_unused_rr_graph_wired_lut_rr_edges(&(cur_op_pb->pb_graph_node->child_pb_graph_nodes[imode][ipb][jpb]), - cur_op_pb->rr_graph, - local_rr_graph); - } - } - } - } - - return; -} - -/* To avoid a messy multi-source routing that may never converge, - * For each multiple-source net, I add a new source as the unique source in routing purpose - * As so, edges have to be added to the decendents of sources - */ -static -int add_virtual_sources_to_rr_graph_multi_sources(t_rr_graph* local_rr_graph) { - int inet, isrc; - int unique_src_node; - int cnt = 0; - - for (inet = 0; inet < local_rr_graph->num_nets; inet++) { - /* Bypass single-source nets */ - if (1 == local_rr_graph->net_num_sources[inet]) { - continue; - } - /* Add a new source */ - local_rr_graph->num_rr_nodes++; - local_rr_graph->rr_node = (t_rr_node*)my_realloc(local_rr_graph->rr_node, - local_rr_graph->num_rr_nodes * sizeof(t_rr_node)); - /* Configure the unique source node */ - unique_src_node = local_rr_graph->num_rr_nodes - 1; - local_rr_graph->rr_node[unique_src_node].type = SOURCE; - local_rr_graph->rr_node[unique_src_node].capacity = 1; - local_rr_graph->rr_node[unique_src_node].occ = 0; - local_rr_graph->rr_node[unique_src_node].cost_index = 0; - local_rr_graph->rr_node[unique_src_node].fan_in = 0; - local_rr_graph->rr_node[unique_src_node].num_drive_rr_nodes = 0; - local_rr_graph->rr_node[unique_src_node].drive_rr_nodes = NULL; - local_rr_graph->rr_node[unique_src_node].pb_graph_pin = NULL; - local_rr_graph->rr_node[unique_src_node].num_edges = local_rr_graph->net_num_sources[inet]; - local_rr_graph->rr_node[unique_src_node].edges = (int*) my_calloc(local_rr_graph->rr_node[unique_src_node].num_edges, sizeof(int)); - local_rr_graph->rr_node[unique_src_node].switches = (short*) my_calloc(local_rr_graph->rr_node[unique_src_node].num_edges, sizeof(short)); - /* Configure edges */ - for (isrc = 0; isrc < local_rr_graph->net_num_sources[inet]; isrc++) { - /* Connect edges to sources */ - local_rr_graph->rr_node[unique_src_node].edges[isrc] = local_rr_graph->net_rr_sources[inet][isrc]; - local_rr_graph->rr_node[unique_src_node].switches[isrc] = DEFAULT_SWITCH_ID; - } - /* Replace the sources with the new source node */ - local_rr_graph->net_num_sources[inet] = 1; - local_rr_graph->net_rr_sources[inet] = (int*)my_realloc(local_rr_graph->net_rr_sources[inet], - local_rr_graph->net_num_sources[inet] * sizeof(int)); - local_rr_graph->net_rr_sources[inet][0] = unique_src_node; - /* Replace the sources in the net_rr_terminals */ - local_rr_graph->net_rr_terminals[inet][0] = unique_src_node; - /* Update counter */ - cnt++; - } - - vpr_printf(TIO_MESSAGE_INFO, - "Added %d virtual source nodes for routing.\n", - cnt); - - return cnt; -} - -/* Allocate and load a local rr_graph for a pb - * 1. Allocate the rr_graph nodes and configure with pb_graph_node connectivity - * 2. load all the routing statisitics required by the router - * 3. load the net to be routed into the rr_graph - */ -void alloc_and_load_rr_graph_for_phy_pb(INP t_pb* cur_op_pb, - INP t_phy_pb* cur_phy_pb, - int L_num_vpack_nets, t_net* L_vpack_net) { - - /* Allocate rr_graph*/ - cur_phy_pb->rr_graph = (t_rr_graph*) my_calloc(1, sizeof(t_rr_graph)); - - /* Allocate and initialize cost index */ - alloc_pb_rr_graph_rr_indexed_data(cur_phy_pb->rr_graph); - - /* Create rr_graph */ - alloc_and_load_rr_graph_for_phy_pb_graph_node(cur_phy_pb->pb_graph_node, cur_phy_pb->rr_graph); - - /* Build prev nodes list for rr_nodes */ - alloc_and_load_prev_node_list_rr_graph_rr_nodes(cur_phy_pb->rr_graph); - - /* Find the nets inside the pb and initialize the rr_graph */ - alloc_and_load_phy_pb_rr_graph_nets(cur_op_pb, cur_phy_pb->rr_graph, - L_num_vpack_nets, L_vpack_net); - - /* Add edges to connected rr_nodes for a wired LUT */ - /* - rec_add_rr_graph_wired_lut_rr_edges(cur_op_pb, cur_phy_pb->rr_graph); - */ - - /* Allocate trace in rr_graph */ - alloc_rr_graph_route_static_structs(cur_phy_pb->rr_graph, nx * ny); /* TODO: nx * ny should be reduced for pb-only routing */ - - /* Fill the net_rr_terminals with - * 1. pin-to-pin mapping in pb_graph_node in cur_op_pb - * 2. rr_graph in the cur_op_pb - */ - alloc_and_load_phy_pb_rr_graph_net_rr_terminals(cur_op_pb, cur_phy_pb->rr_graph); - - add_virtual_sources_to_rr_graph_multi_sources(cur_phy_pb->rr_graph); - - /* Allocate structs routing information */ - alloc_and_load_rr_graph_route_structs(cur_phy_pb->rr_graph); - - return; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.h b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.h deleted file mode 100644 index 461cd08d4..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.h +++ /dev/null @@ -1,42 +0,0 @@ - - -int rec_count_rr_graph_nodes_for_phy_pb_graph_node(t_pb_graph_node* cur_pb_graph_node); - -void init_one_rr_node_pack_cost_for_phy_graph_node(INP t_pb_graph_pin* cur_pb_graph_pin, - INOUTP t_rr_graph* local_rr_graph, - int cur_rr_node_index, - enum PORTS port_type); - -void init_one_rr_node_for_phy_pb_graph_node(INP t_pb_graph_pin* cur_pb_graph_pin, - INOUTP t_rr_graph* local_rr_graph, - int cur_rr_node_index, - int phy_mode_index, - t_rr_type rr_node_type); - -void connect_one_rr_node_for_phy_pb_graph_node(INP t_pb_graph_pin* cur_pb_graph_pin, - INOUTP t_rr_graph* local_rr_graph, - int cur_rr_node_index, - int phy_mode_index, - t_rr_type rr_node_type); - -int rec_init_rr_graph_for_phy_pb_graph_node(INP t_pb_graph_node* cur_pb_graph_node, - INOUTP t_rr_graph* local_rr_graph, - int cur_rr_node_index); - -int rec_connect_rr_graph_for_phy_pb_graph_node(INP t_pb_graph_node* cur_pb_graph_node, - INOUTP t_rr_graph* local_rr_graph, - int cur_rr_node_index); - -void alloc_and_load_rr_graph_for_phy_pb_graph_node(INP t_pb_graph_node* top_pb_graph_node, - OUTP t_rr_graph* local_rr_graph); - -void alloc_and_load_phy_pb_rr_graph_nets(INP t_pb* cur_op_pb, - t_rr_graph* local_rr_graph, - int L_num_vpack_nets, t_net* L_vpack_net); - -void load_phy_pb_rr_graph_net_rr_terminals(INP t_pb* cur_op_pb, - t_rr_graph* local_rr_graph); - -void alloc_and_load_rr_graph_for_phy_pb(INP t_pb* cur_op_pb, - INP t_phy_pb* cur_phy_pb, - int L_num_vpack_nets, t_net* L_vpack_net); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.c b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.c deleted file mode 100644 index c6de5ced7..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.c +++ /dev/null @@ -1,894 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: fpga_x2p_router.c - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/07/02 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file contains a breadth-first router which is tailored for packer - ***********************************************************************/ - -#include -#include -#include -#include - -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "route_common.h" - -#include "fpga_x2p_types.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_rr_graph_utils.h" -#include "fpga_x2p_pb_rr_graph.h" - -#include "fpga_x2p_router.h" - -void breadth_first_expand_rr_graph_trace_segment(t_rr_graph* local_rr_graph, - t_trace *start_ptr, - int remaining_connections_to_sink) { - - /* Adds all the rr_nodes in the traceback segment starting at tptr (and * - * continuing to the end of the traceback) to the heap with a cost of zero. * - * This allows expansion to begin from the existing wiring. The * - * remaining_connections_to_sink value is 0 if the route segment ending * - * at this location is the last one to connect to the SINK ending the route * - * segment. This is the usual case. If it is not the last connection this * - * net must make to this SINK, I have a hack to ensure the next connection * - * to this SINK goes through a different IPIN. Without this hack, the * - * router would always put all the connections from this net to this SINK * - * through the same IPIN. With LUTs or cluster-based logic blocks, you * - * should never have a net connecting to two logically-equivalent pins on * - * the same logic block, so the hack will never execute. If your logic * - * block is an and-gate, however, nets might connect to two and-inputs on * - * the same logic block, and since the and-inputs are logically-equivalent, * - * this means two connections to the same SINK. */ - - t_trace *tptr, *next_ptr; - int inode, sink_node, last_ipin_node; - - tptr = start_ptr; - - if (remaining_connections_to_sink == 0) { /* Usual case. */ - while (tptr != NULL) { - add_node_to_rr_graph_heap(local_rr_graph, tptr->index, 0., NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); - tptr = tptr->next; - } - } else { /* This case never executes for most logic blocks. */ - /* Weird case. Lots of hacks. The cleanest way to do this would be to empty * - * the heap, update the congestion due to the partially-completed route, put * - * the whole route so far (excluding IPINs and SINKs) on the heap with cost * - * 0., and expand till you hit the next SINK. That would be slow, so I * - * do some hacks to enable incremental wavefront expansion instead. */ - - if (tptr == NULL) - return; /* No route yet */ - - next_ptr = tptr->next; - last_ipin_node = OPEN; /* Stops compiler from complaining. */ - - /* Can't put last SINK on heap with NO_PREVIOUS, etc, since that won't let * - * us reach it again. Instead, leave the last traceback element (SINK) off * - * the heap. */ - - while (next_ptr != NULL) { - inode = tptr->index; - add_node_to_rr_graph_heap(local_rr_graph, inode, 0., NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); - - if (local_rr_graph->rr_node[inode].type == INTRA_CLUSTER_EDGE) { - if ((local_rr_graph->rr_node[inode].pb_graph_pin != NULL) - && (local_rr_graph->rr_node[inode].pb_graph_pin->num_output_edges == 0)) { - last_ipin_node = inode; - } - } - - tptr = next_ptr; - next_ptr = tptr->next; - } - - /* This will stop the IPIN node used to get to this SINK from being * - * reexpanded for the remainder of this net's routing. This will make us * - * hook up more IPINs to this SINK (which is what we want). If IPIN * - * doglegs are allowed in the graph, we won't be able to use this IPIN to * - * do a dogleg, since it won't be re-expanded. Shouldn't be a big problem. */ - assert(last_ipin_node != OPEN); - local_rr_graph->rr_node_route_inf[last_ipin_node].path_cost = -HUGE_POSITIVE_FLOAT; - - /* Also need to mark the SINK as having high cost, so another connection can * - * be made to it. */ - - sink_node = tptr->index; - local_rr_graph->rr_node_route_inf[sink_node].path_cost = HUGE_POSITIVE_FLOAT; - - /* Finally, I need to remove any pending connections to this SINK via the * - * IPIN I just used (since they would result in congestion). Scan through * - * the heap to do this. */ - - invalidate_rr_graph_heap_entries(local_rr_graph, sink_node, last_ipin_node); - } - - return; -} - -void breadth_first_expand_rr_graph_neighbours(t_rr_graph* local_rr_graph, - int inode, float pcost, - int inet, boolean first_time) { - - /* Puts all the rr_nodes adjacent to inode on the heap. rr_nodes outside * - * the expanded bounding box specified in route_bb are not added to the * - * heap. pcost is the path_cost to get to inode. */ - - int iconn, to_node, num_edges; - float tot_cost; - - num_edges = local_rr_graph->rr_node[inode].num_edges; - for (iconn = 0; iconn < num_edges; iconn++) { - to_node = local_rr_graph->rr_node[inode].edges[iconn]; - /*if (first_time) { */ - tot_cost = pcost + get_rr_graph_rr_cong_cost(local_rr_graph, to_node) - * get_rr_graph_rr_node_pack_intrinsic_cost(local_rr_graph, to_node); - /* - } else { - tot_cost = pcost + get_rr_cong_cost(to_node); - }*/ - add_node_to_rr_graph_heap(local_rr_graph, to_node, tot_cost, inode, iconn, OPEN, OPEN); - } -} - -/* A copy of breath_first_add_source_to_heap_cluster - * I remove all the use of global variables - */ -void breadth_first_add_source_to_rr_graph_heap(t_rr_graph* local_rr_graph, - int src_net_index) { - - /* Adds the SOURCE of this net to the heap. Used to start a net's routing. */ - - int inode; - float cost; - - inode = local_rr_graph->net_rr_terminals[src_net_index][0]; /* SOURCE */ - cost = get_rr_graph_rr_cong_cost(local_rr_graph, inode); - - add_node_to_rr_graph_heap(local_rr_graph, inode, cost, NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); -} - -/* A copy of breath_first_add_source_to_heap_cluster - * I remove all the use of global variables - */ -static -void breadth_first_add_one_source_to_rr_graph_heap(t_rr_graph* local_rr_graph, - int src_net_index, - int src_idx) { - - /* Adds the SOURCE of this net to the heap. Used to start a net's routing. */ - int inode; - float cost; - - inode = local_rr_graph->net_rr_sources[src_net_index][src_idx]; /* SOURCE */ - cost = get_rr_graph_rr_cong_cost(local_rr_graph, inode); - - add_node_to_rr_graph_heap(local_rr_graph, inode, cost, NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); - - return; -} - -/* A copy of breath_first_route_net_cluster - * I remove all the use of global variables - */ -boolean breadth_first_route_one_net_pb_rr_graph(t_rr_graph* local_rr_graph, - int inet) { - - /* Uses a maze routing (Dijkstra's) algorithm to route a net. The net * - * begins at the net output, and expands outward until it hits a target * - * pin. The algorithm is then restarted with the entire first wire segment * - * included as part of the source this time. For an n-pin net, the maze * - * router is invoked n-1 times to complete all the connections. Inet is * - * the index of the net to be routed. * - * If this routine finds that a net *cannot* be connected (due to a complete * - * lack of potential paths, rather than congestion), it returns FALSE, as * - * routing is impossible on this architecture. Otherwise it returns TRUE. */ - - int i, inode, prev_node, remaining_connections_to_sink; - float pcost, new_pcost; - struct s_heap *current; - struct s_trace *tptr; - boolean first_time; - - free_rr_graph_traceback(local_rr_graph, inet); - breadth_first_add_source_to_rr_graph_heap(local_rr_graph, inet); - mark_rr_graph_ends(local_rr_graph, inet); - - tptr = NULL; - remaining_connections_to_sink = 0; - - for (i = 1; i < local_rr_graph->net_num_sinks[inet] + 1; i++) { /* Need n-1 wires to connect n pins */ - - /* Do not connect open terminals */ - if (local_rr_graph->net_rr_terminals[inet][i] == OPEN) { - continue; - } - /* Expand and begin routing */ - breadth_first_expand_rr_graph_trace_segment(local_rr_graph, tptr, remaining_connections_to_sink); - current = get_rr_graph_heap_head(local_rr_graph); - - if (current == NULL) { /* Infeasible routing. No possible path for net. */ - reset_rr_graph_path_costs(local_rr_graph); /* Clean up before leaving. */ - return (FALSE); - } - - inode = current->index; - - while (local_rr_graph->rr_node_route_inf[inode].target_flag == 0) { - pcost = local_rr_graph->rr_node_route_inf[inode].path_cost; - new_pcost = current->cost; - if (pcost > new_pcost) { /* New path is lowest cost. */ - local_rr_graph->rr_node_route_inf[inode].path_cost = new_pcost; - prev_node = current->u.prev_node; - local_rr_graph->rr_node_route_inf[inode].prev_node = prev_node; - local_rr_graph->rr_node_route_inf[inode].prev_edge = current->prev_edge; - first_time = FALSE; - - if (pcost > 0.99 * HUGE_POSITIVE_FLOAT) /* First time touched. */{ - add_to_rr_graph_mod_list(local_rr_graph, &local_rr_graph->rr_node_route_inf[inode].path_cost); - first_time = TRUE; - } - - breadth_first_expand_rr_graph_neighbours(local_rr_graph, inode, new_pcost, inet, first_time); - } - - free_rr_graph_heap_data(local_rr_graph, current); - current = get_rr_graph_heap_head(local_rr_graph); - - if (current == NULL) { /* Impossible routing. No path for net. */ - reset_rr_graph_path_costs(local_rr_graph); - return (FALSE); - } - - inode = current->index; - } - - local_rr_graph->rr_node_route_inf[inode].target_flag--; /* Connected to this SINK. */ - remaining_connections_to_sink = local_rr_graph->rr_node_route_inf[inode].target_flag; - tptr = update_rr_graph_traceback(local_rr_graph, current, inet); - free_rr_graph_heap_data(local_rr_graph, current); - } - - empty_rr_graph_heap(local_rr_graph); - reset_rr_graph_path_costs(local_rr_graph); - return (TRUE); -} - -/* Adapt for the multi-source rr_graph routing - */ -static -boolean breadth_first_route_one_single_source_net_pb_rr_graph(t_rr_graph* local_rr_graph, - int inet, int isrc, - int start_isink, - boolean* net_sink_routed) { - - /* Uses a maze routing (Dijkstra's) algorithm to route a net. The net * - * begins at the net output, and expands outward until it hits a target * - * pin. The algorithm is then restarted with the entire first wire segment * - * included as part of the source this time. For an n-pin net, the maze * - * router is invoked n-1 times to complete all the connections. Inet is * - * the index of the net to be routed. * - * If this routine finds that a net *cannot* be connected (due to a complete * - * lack of potential paths, rather than congestion), it returns FALSE, as * - * routing is impossible on this architecture. Otherwise it returns TRUE. */ - - int isink, inode, jsink, prev_node, remaining_connections_to_sink; - float pcost, new_pcost; - struct s_heap *current; - struct s_trace *tptr; - boolean first_time; - - free_rr_graph_traceback(local_rr_graph, inet); - breadth_first_add_one_source_to_rr_graph_heap(local_rr_graph, inet, isrc); - mark_rr_graph_sinks(local_rr_graph, inet, start_isink, net_sink_routed); - - tptr = NULL; - remaining_connections_to_sink = 0; - -#ifdef VERBOSE - printf("Sink nodes for net=%s to try: ", - local_rr_graph->net[inet]->name); - for (isink = start_isink; isink < local_rr_graph->net_num_sinks[inet]; isink++) { - if (OPEN == local_rr_graph->net_rr_sinks[inet][isink]) { - continue; - } - if (TRUE == net_sink_routed[isink]) { - continue; - } - printf("%d,", - isink); - } - printf("\n"); -#endif - - for (isink = start_isink; isink < local_rr_graph->net_num_sinks[inet]; isink++) { /* Need n-1 wires to connect n pins */ - /* Do not connect open terminals */ - if (OPEN == local_rr_graph->net_rr_sinks[inet][isink]) { - continue; - } - - /* Expand and begin routing */ - breadth_first_expand_rr_graph_trace_segment(local_rr_graph, tptr, remaining_connections_to_sink); - current = get_rr_graph_heap_head(local_rr_graph); - - /* Exit only when this is the last source node - * Infeasible routing. No possible path for net. - */ - if (NULL == current) { -#ifdef VERBOSE - printf("1. Fail Routing: net=%s, sink=%d\n", - local_rr_graph->net[inet]->name, - isink); -#endif - reset_rr_graph_path_costs(local_rr_graph); - return FALSE; - } - - inode = current->index; - - while (local_rr_graph->rr_node_route_inf[inode].target_flag == 0) { - pcost = local_rr_graph->rr_node_route_inf[inode].path_cost; - new_pcost = current->cost; - if (pcost > new_pcost) { /* New path is lowest cost. */ - local_rr_graph->rr_node_route_inf[inode].path_cost = new_pcost; - prev_node = current->u.prev_node; - local_rr_graph->rr_node_route_inf[inode].prev_node = prev_node; - local_rr_graph->rr_node_route_inf[inode].prev_edge = current->prev_edge; - first_time = FALSE; - - if (pcost > 0.99 * HUGE_POSITIVE_FLOAT) /* First time touched. */{ - add_to_rr_graph_mod_list(local_rr_graph, &local_rr_graph->rr_node_route_inf[inode].path_cost); - first_time = TRUE; - } - - breadth_first_expand_rr_graph_neighbours(local_rr_graph, inode, new_pcost, inet, first_time); - - if ( (0 == strcmp("_18363_", local_rr_graph->net[inet]->name)) - && (0 == strcmp("fle", local_rr_graph->rr_node[inode].pb_graph_pin->parent_node->pb_type->name)) - && (0 == strcmp("out", local_rr_graph->rr_node[inode].pb_graph_pin->port->name)) - && (2 == local_rr_graph->rr_node[inode].pb_graph_pin->parent_node->placement_index) - && (1 == local_rr_graph->rr_node[inode].pb_graph_pin->pin_number) ) { - vpr_printf(TIO_MESSAGE_INFO, - "Expanding to node: %s/%s[%d], cost=%.5g\n", - get_pb_graph_full_name_in_hierarchy(local_rr_graph->rr_node[inode].pb_graph_pin->parent_node), - local_rr_graph->rr_node[inode].pb_graph_pin->port->name, - local_rr_graph->rr_node[inode].pb_graph_pin->pin_number, - new_pcost); - } - - if ( (0 == strcmp("_18363_", local_rr_graph->net[inet]->name)) - && (0 == strcmp("fle", local_rr_graph->rr_node[inode].pb_graph_pin->parent_node->pb_type->name)) - && (0 == strcmp("out", local_rr_graph->rr_node[inode].pb_graph_pin->port->name)) - && (3 == local_rr_graph->rr_node[inode].pb_graph_pin->parent_node->placement_index) - && (0 == local_rr_graph->rr_node[inode].pb_graph_pin->pin_number) ) { - vpr_printf(TIO_MESSAGE_INFO, - "Expanding to node: %s/%s[%d], cost=%.5g\n", - get_pb_graph_full_name_in_hierarchy(local_rr_graph->rr_node[inode].pb_graph_pin->parent_node), - local_rr_graph->rr_node[inode].pb_graph_pin->port->name, - local_rr_graph->rr_node[inode].pb_graph_pin->pin_number, - new_pcost); - } - - if ( (0 == strcmp("_18363_", local_rr_graph->net[inet]->name)) - && (0 == strcmp("fle", local_rr_graph->rr_node[inode].pb_graph_pin->parent_node->pb_type->name)) - && (0 == strcmp("regout", local_rr_graph->rr_node[inode].pb_graph_pin->port->name)) - && (2 == local_rr_graph->rr_node[inode].pb_graph_pin->parent_node->placement_index) - && (0 == local_rr_graph->rr_node[inode].pb_graph_pin->pin_number) ) { - vpr_printf(TIO_MESSAGE_INFO, - "Expanding to node: %s/%s[%d], cost=%.5g\n", - get_pb_graph_full_name_in_hierarchy(local_rr_graph->rr_node[inode].pb_graph_pin->parent_node), - local_rr_graph->rr_node[inode].pb_graph_pin->port->name, - local_rr_graph->rr_node[inode].pb_graph_pin->pin_number, - new_pcost); - } - } - - free_rr_graph_heap_data(local_rr_graph, current); - current = get_rr_graph_heap_head(local_rr_graph); - - /* Impossible routing. No path for net. - */ - if (NULL == current) { - break; - } - - inode = current->index; - - - } - - /* Impossible routing, try another iteration */ - if (NULL == current) { -#ifdef VERBOSE - printf("2. Fail Routing: net=%s, sink=%d\n", - local_rr_graph->net[inet]->name, - isink); -#endif - reset_rr_graph_path_costs(local_rr_graph); - continue; - } - - local_rr_graph->rr_node_route_inf[inode].target_flag--; /* Connected to this SINK. */ - remaining_connections_to_sink = local_rr_graph->rr_node_route_inf[inode].target_flag; - tptr = update_rr_graph_traceback(local_rr_graph, current, inet); - free_rr_graph_heap_data(local_rr_graph, current); - - /* Update the flag - * BE CAREFUL: the inode is one of the sink - * it is not always the isink node!!! - * In each iteration, the routing algorithm will route a sink with lowest cost, - * This is out of the order of sinks - */ - for (jsink = start_isink; jsink < local_rr_graph->net_num_sinks[inet]; jsink++) { /* Need n-1 wires to connect n pins */ - if (inode != local_rr_graph->net_rr_sinks[inet][jsink]) { - continue; - } - net_sink_routed[jsink] = TRUE; -#ifdef VERBOSE - printf("Round %d, Success Routing: net=%s, sink=%d, port=%s[%d], pb_type=%s\n", - isink, local_rr_graph->net[inet]->name, - jsink, - local_rr_graph->rr_node[inode].pb_graph_pin->port->name, - local_rr_graph->rr_node[inode].pb_graph_pin->pin_number, - get_pb_graph_full_name_in_hierarchy(local_rr_graph->rr_node[inode].pb_graph_pin->parent_node)); -#endif - break; - } - } - - return TRUE; -} - - -/* Adapt for the multi-source rr_graph routing - */ -static -boolean breadth_first_route_one_multi_source_net_pb_rr_graph(t_rr_graph* local_rr_graph, - int inet) { - - /* Uses a maze routing (Dijkstra's) algorithm to route a net. The net * - * begins at the net output, and expands outward until it hits a target * - * pin. The algorithm is then restarted with the entire first wire segment * - * included as part of the source this time. For an n-pin net, the maze * - * router is invoked n-1 times to complete all the connections. Inet is * - * the index of the net to be routed. * - * If this routine finds that a net *cannot* be connected (due to a complete * - * lack of potential paths, rather than congestion), it returns FALSE, as * - * routing is impossible on this architecture. Otherwise it returns TRUE. */ - - int isrc, isink, inode, start_isink; - boolean* net_sink_routed = (boolean*) my_malloc(local_rr_graph->net_num_sinks[inet] * sizeof(boolean)); - boolean route_success = FALSE; - - /* Initialize */ - for (isink = 0; isink < local_rr_graph->net_num_sinks[inet]; isink++) { - net_sink_routed[isink] = FALSE; - /* Exception for OPEN nets */ - if (OPEN == local_rr_graph->net_rr_sinks[inet][isink]) { - net_sink_routed[isink] = TRUE; - } - } - - start_isink = 0; - - /* try each sources */ - for (isrc = 0; isrc < local_rr_graph->net_num_sources[inet]; isrc++) { - /* Get the start sink index, - * when a sink is failed in routing, - * we update flags the net_sink_routed - * Next time, we will start from first sink is - */ -#ifdef VERBOSE - printf("\nnum_src=%d, isrc=%d\n", local_rr_graph->net_num_sources[inet], isrc); -#endif - for (isink = 0; isink < local_rr_graph->net_num_sinks[inet]; isink++) { - if (TRUE == net_sink_routed[isink]) { - continue; - } - start_isink = isink; - break; - } - -#ifdef VERBOSE - printf("\nstart_sink=%d\n", start_isink); -#endif - /* Reset the target_flag for sinks to be routed */ - start_isink = 0; - for (isink = start_isink; isink < local_rr_graph->net_num_sinks[inet]; isink++) { - inode = local_rr_graph->net_rr_sinks[inet][isink]; - if (OPEN != inode) { - local_rr_graph->rr_node_route_inf[inode].target_flag = 0; - } - } - breadth_first_route_one_single_source_net_pb_rr_graph(local_rr_graph, inet, isrc, - start_isink, - net_sink_routed); - /* Clean up routing data */ - empty_rr_graph_heap(local_rr_graph); - reset_rr_graph_path_costs(local_rr_graph); - /* See if we can early exit */ - /* Make sure every sink if routed */ - route_success = TRUE; - for (isink = 0; isink < local_rr_graph->net_num_sinks[inet]; isink++) { - if ( (OPEN != local_rr_graph->net_rr_sinks[inet][isink]) - && (FALSE == net_sink_routed[isink])) { - route_success = FALSE; - } - } - if (TRUE == route_success) { - break; - } - } - - /* Provide more information for users when route fails */ - if (FALSE == route_success) { - for (isink = 0; isink < local_rr_graph->net_num_sinks[inet]; isink++) { - if ( (OPEN != local_rr_graph->net_rr_sinks[inet][isink]) - && (FALSE == net_sink_routed[isink])) { - /* Give informatioin about the starting pin */ - vpr_printf(TIO_MESSAGE_ERROR, "Fail Routing:\n"); - - for (isrc = 0; isrc < local_rr_graph->net_num_sources[inet]; isrc++) { - inode = local_rr_graph->net_rr_sources[inet][isrc]; - vpr_printf(TIO_MESSAGE_INFO, - "Starting points %d: net=%s, source_rr_node=%d, port=%s[%d], pb_type=%s\n", - isrc, - local_rr_graph->net[inet]->name, inode, - local_rr_graph->rr_node[inode].pb_graph_pin->port->name, - local_rr_graph->rr_node[inode].pb_graph_pin->pin_number, - get_pb_graph_full_name_in_hierarchy(local_rr_graph->rr_node[inode].pb_graph_pin->parent_node)); - } - /* Give informatioin about the starting pin */ - inode = local_rr_graph->net_rr_sinks[inet][isink]; - vpr_printf(TIO_MESSAGE_INFO, - "Ending points: net=%s, sink=%d, port=%s[%d], pb_type=%s\n", - local_rr_graph->net[inet]->name, - isink, - local_rr_graph->rr_node[inode].pb_graph_pin->port->name, - local_rr_graph->rr_node[inode].pb_graph_pin->pin_number, - get_pb_graph_full_name_in_hierarchy(local_rr_graph->rr_node[inode].pb_graph_pin->parent_node)); - vpr_printf(TIO_MESSAGE_INFO, - "Please double check your XML about if pins in operating modes are correctedly linked to physical mode!\n"); - } - } - } - - /* Free */ - free(net_sink_routed); - - return route_success; -} - -static -boolean feasible_routing_rr_graph(t_rr_graph* local_rr_graph, - boolean verbose) { - - /* This routine checks to see if this is a resource-feasible routing. * - * That is, are all rr_node capacity limitations respected? It assumes * - * that the occupancy arrays are up to date when it is called. */ - - int inode, inet; - t_trace* tptr; - int* rr_node_net_checker = (int*) my_calloc (local_rr_graph->num_rr_nodes, sizeof(int)); - int* rr_node_occ_checker = (int*) my_calloc (local_rr_graph->num_rr_nodes, sizeof(int)); - boolean feasible = TRUE; - - /* Initialize the checker */ - for (inode = 0; inode < local_rr_graph->num_rr_nodes; inode++) { - rr_node_net_checker[inode] = OPEN; - } - - /* Check the trace: - * We may have the same nets sharing the part of the traces - * We will adapt the occupancy of rr_node to avoid errors in feasibility checking - */ - for (inet = 0; inet < local_rr_graph->num_nets; inet++) { - tptr = local_rr_graph->trace_head[inet]; - while (tptr != NULL) { - inode = tptr->index; - /* Update the checker for net num */ - if (OPEN == rr_node_net_checker[inode]) { - /* First visit, we assign a value */ - rr_node_net_checker[inode] = inet; - /* Initialize occ */ - rr_node_occ_checker[inode] = 1; - } else if (inet != rr_node_net_checker[inode]) { - /* This means two traces share the same node - * This is not a feasible routing, error out - */ - if (TRUE == verbose) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Shared Trace Found for rr_node[%d] (pb pin:%s/%s[%d]) between net(%s) and net (%s)!\n", - __FILE__, __LINE__, - inode, - get_pb_graph_full_name_in_hierarchy(local_rr_graph->rr_node[inode].pb_graph_pin->parent_node), - local_rr_graph->rr_node[inode].pb_graph_pin->port->name, - local_rr_graph->rr_node[inode].pb_graph_pin->pin_number, - local_rr_graph->net[inet]->name, - local_rr_graph->net[rr_node_net_checker[inode]]->name); - } - /* Increase occ */ - rr_node_occ_checker[inode]++; - } else { - assert (inet == rr_node_net_checker[inode]); - /* Try to increase the capacity of rr_node */ - if (TRUE == verbose) { -#ifdef VERBOSE - vpr_printf(TIO_MESSAGE_INFO, - "(File:%s,[LINE%d]) Detect rr_node[%d] (pb pin:%s/%s[%d]) for shared net(%s)!\n", - __FILE__, __LINE__, - inode, - get_pb_graph_full_name_in_hierarchy(local_rr_graph->rr_node[inode].pb_graph_pin->parent_node), - local_rr_graph->rr_node[inode].pb_graph_pin->port->name, - local_rr_graph->rr_node[inode].pb_graph_pin->pin_number, - local_rr_graph->net[inet]->name); -#endif - } - } - tptr = tptr->next; - } - } - - /* Update occ of rr_graph */ - for (inode = 0; inode < local_rr_graph->num_rr_nodes; inode++) { - local_rr_graph->rr_node[inode].occ = rr_node_occ_checker[inode]; - } - /* Free */ - free(rr_node_occ_checker); - free(rr_node_net_checker); - - for (inode = 0; inode < local_rr_graph->num_rr_nodes; inode++) { - if (local_rr_graph->rr_node[inode].occ > local_rr_graph->rr_node[inode].capacity) { - if (TRUE == verbose) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) rr_node[%d] (pin:%s/%s[%d]) occupancy(%d) exceeds its capacity(%d)!\n", - __FILE__, __LINE__, - inode, - get_pb_graph_full_name_in_hierarchy(local_rr_graph->rr_node[inode].pb_graph_pin->parent_node), - local_rr_graph->rr_node[inode].pb_graph_pin->port->name, - local_rr_graph->rr_node[inode].pb_graph_pin->pin_number, - local_rr_graph->rr_node[inode].occ, - local_rr_graph->rr_node[inode].capacity); - } - feasible = FALSE; - } - } - - return feasible; -} - -void pathfinder_update_rr_graph_one_cost(t_rr_graph* local_rr_graph, - t_trace *route_segment_start, - int add_or_sub, float pres_fac) { - - /* This routine updates the occupancy and pres_cost of the rr_nodes that are * - * affected by the portion of the routing of one net that starts at * - * route_segment_start. If route_segment_start is trace_head[inet], the * - * cost of all the nodes in the routing of net inet are updated. If * - * add_or_sub is -1 the net (or net portion) is ripped up, if it is 1 the * - * net is added to the routing. The size of pres_fac determines how severly * - * oversubscribed rr_nodes are penalized. */ - - struct s_trace *tptr; - int inode, occ, capacity; - - tptr = route_segment_start; - if (tptr == NULL) /* No routing yet. */ - return; - - for (;;) { - inode = tptr->index; - - occ = local_rr_graph->rr_node[inode].occ + add_or_sub; - capacity = local_rr_graph->rr_node[inode].capacity; - - local_rr_graph->rr_node[inode].occ = occ; - - /* pres_cost is Pn in the Pathfinder paper. I set my pres_cost according to * - * the overuse that would result from having ONE MORE net use this routing * - * node. */ - - if (occ < capacity) { - local_rr_graph->rr_node_route_inf[inode].pres_cost = 1.; - } else { - local_rr_graph->rr_node_route_inf[inode].pres_cost = 1. + (occ + 1 - capacity) * pres_fac; - } - - if (local_rr_graph->rr_node[inode].type == SINK) { - tptr = tptr->next; /* Skip next segment. */ - if (tptr == NULL) - break; - } - - tptr = tptr->next; - - } /* End while loop -- did an entire traceback. */ - - return; -} - -void pathfinder_update_rr_graph_cost(t_rr_graph* local_rr_graph, - float pres_fac, float acc_fac) { - - /* This routine recomputes the pres_cost and acc_cost of each routing * - * resource for the pathfinder algorithm after all nets have been routed. * - * It updates the accumulated cost to by adding in the number of extra * - * signals sharing a resource right now (i.e. after each complete iteration) * - * times acc_fac. It also updates pres_cost, since pres_fac may have * - * changed. THIS ROUTINE ASSUMES THE OCCUPANCY VALUES IN RR_NODE ARE UP TO * - * DATE. */ - - int inode, occ, capacity; - - for (inode = 0; inode < local_rr_graph->num_rr_nodes; inode++) { - occ = local_rr_graph->rr_node[inode].occ; - capacity = local_rr_graph->rr_node[inode].capacity; - - if (occ > capacity) { - local_rr_graph->rr_node_route_inf[inode].acc_cost += (occ - capacity) * acc_fac; - local_rr_graph->rr_node_route_inf[inode].pres_cost = 1. + (occ + 1 - capacity) * pres_fac; - } else if (occ == capacity) { - /* If occ == capacity, we don't need to increase acc_cost, but a change * - * in pres_fac could have made it necessary to recompute the cost anyway. */ - local_rr_graph->rr_node_route_inf[inode].pres_cost = 1. + pres_fac; - } - } - - return; -} - - -/** - * A Copy of try_breadth_first_route_cluster - * I remove all the use of global variables - * internal_nets: index of nets to route [0..num_internal_nets - 1] - */ -boolean try_breadth_first_route_pb_rr_graph(t_rr_graph* local_rr_graph) { - - /* Iterated maze router ala Pathfinder Negotiated Congestion algorithm, * - * (FPGA 95 p. 111). Returns TRUE if it can route this FPGA, FALSE if * - * it can't. */ - - /* For different modes, when a mode is turned on, I set the max occupancy of all rr_nodes in the mode to 1 and all others to 0 */ - /* TODO: There is a bug for route-throughs where edges in route-throughs do not get turned off because the rr_edge is in a particular mode but the two rr_nodes are outside */ - - boolean success, is_routable; - int itry, inet, net_index; - struct s_router_opts router_opts; - float pres_fac; - - /* Xifan TANG: Count runtime for routing in packing stage */ - clock_t begin, end; - - begin = clock(); - - /* Usually the first iteration uses a very small (or 0) pres_fac to find * - * the shortest path and get a congestion map. For fast compiles, I set * - * pres_fac high even for the first iteration. */ - - /* sets up a fast breadth-first router */ - router_opts.first_iter_pres_fac = 10; - router_opts.max_router_iterations = 20; - router_opts.initial_pres_fac = 10; - router_opts.pres_fac_mult = 2; - router_opts.acc_fac = 1; - - /* Default breath-first router opts */ - /* - router_opts.first_iter_pres_fac = 0; - router_opts.max_router_iterations = 50; - router_opts.initial_pres_fac = 0.5; - router_opts.pres_fac_mult = 1.3; - router_opts.acc_fac = 0.2; - */ - - reset_rr_graph_rr_node_route_structs(local_rr_graph); /* Clear all prior rr_graph history */ - - pres_fac = router_opts.first_iter_pres_fac; - - for (itry = 1; itry <= router_opts.max_router_iterations; itry++) { - for (inet = 0; inet < local_rr_graph->num_nets; inet++) { - net_index = inet; - - pathfinder_update_rr_graph_one_cost(local_rr_graph, local_rr_graph->trace_head[net_index], -1, pres_fac); - - /* - is_routable = breadth_first_route_one_net_pb_rr_graph(local_rr_graph, net_index); - */ - is_routable = breadth_first_route_one_multi_source_net_pb_rr_graph(local_rr_graph, net_index); - - /* Impossible to route? (disconnected rr_graph) */ - - if (!is_routable) { - /* TODO: Inelegant, can be more intelligent */ - vpr_printf(TIO_MESSAGE_INFO, "Failed routing net %s\n", local_rr_graph->net[net_index]->name); - vpr_printf(TIO_MESSAGE_INFO, "Routing failed. Disconnected rr_graph.\n"); - return FALSE; - } else { - /* - vpr_printf(TIO_MESSAGE_INFO, "Succeed routing net %s\n", local_rr_graph->net[net_index]->name); - */ - } - - pathfinder_update_rr_graph_one_cost(local_rr_graph, local_rr_graph->trace_head[net_index], 1, pres_fac); - - } - - success = feasible_routing_rr_graph(local_rr_graph, FALSE); - if (success) { - /* End of packing routing */ - end = clock(); - /* accumulate the runtime for pack routing */ -#ifdef CLOCKS_PER_SEC - pack_route_time += (float)(end - begin)/ CLOCKS_PER_SEC; -#else - pack_route_time += (float)(end - begin)/ CLK_PER_SEC; -#endif - /* vpr_printf(TIO_MESSAGE_INFO, "Updated: Packing routing took %g seconds\n", pack_route_time); */ - return (TRUE); - } - - if (itry == 1) { - pres_fac = router_opts.initial_pres_fac; - } else { - pres_fac *= router_opts.pres_fac_mult; - } - - pres_fac = std::min(pres_fac, static_cast(HUGE_POSITIVE_FLOAT / 1e5)); - - pathfinder_update_rr_graph_cost(local_rr_graph, pres_fac, router_opts.acc_fac); - } - /* End of packing routing */ - end = clock(); - /* accumulate the runtime for pack routing */ -#ifdef CLOCKS_PER_SEC - pack_route_time += (float)(end - begin)/ CLOCKS_PER_SEC; -#else - pack_route_time += (float)(end - begin)/ CLK_PER_SEC; -#endif - vpr_printf(TIO_MESSAGE_INFO, "Packing/Routing Physical Progammable Blocks took %g seconds\n", pack_route_time); - - /* Give error message when routing is failed */ - feasible_routing_rr_graph(local_rr_graph, TRUE); - - return (FALSE); -} - -/************************************************************************ - * End of file : fpga_x2p_router.c - ***********************************************************************/ - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.h b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.h deleted file mode 100644 index 7bb856dca..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.h +++ /dev/null @@ -1,28 +0,0 @@ - -void breadth_first_expand_rr_graph_trace_segment(t_rr_graph* local_rr_graph, - t_trace *start_ptr, - int remaining_connections_to_sink); - -void breadth_first_expand_rr_graph_neighbours(t_rr_graph* local_rr_graph, - int inode, float pcost, - int inet, boolean first_time); - -boolean breadth_first_route_one_net_rr_graph_cluster(t_rr_graph* local_rr_graph, - int inet); - -boolean feasible_routing_rr_graph(t_rr_graph* local_rr_graph); - -void pathfinder_update_rr_graph_one_cost(t_rr_graph* local_rr_graph, - t_trace *route_segment_start, - int add_or_sub, float pres_fac); - -void pathfinder_update_rr_graph_cost(t_rr_graph* local_rr_graph, - float pres_fac, float acc_fac); - -void breadth_first_add_source_to_rr_graph_heap(t_rr_graph* local_rr_graph, - int src_net_index); - -boolean breadth_first_route_one_net_pb_rr_graph(t_rr_graph* local_rr_graph, - int inet); - -boolean try_breadth_first_route_pb_rr_graph(t_rr_graph* local_rr_graph); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_exit.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_exit.c deleted file mode 100644 index 58504c49d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_exit.c +++ /dev/null @@ -1,21 +0,0 @@ - -/* Include vpr structs*/ -#include "util.h" -#include "arch_types.h" -#include "vpr_types.h" - -/* SPICE Support Headers */ -#include "read_xml_spice_util.h" - -#include "read_opt_types.h" -#include "shell_types.h" - -void shell_execute_exit(t_shell_env* env, t_opt_info* opts) { - - char* vpr_shell_name = "VPR7-OpenFPGA"; - - vpr_printf(TIO_MESSAGE_INFO, - "Thank you for using %s!\n", - vpr_shell_name); - exit(1); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_exit.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_exit.h deleted file mode 100644 index 5dc006d15..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_exit.h +++ /dev/null @@ -1,8 +0,0 @@ -/* Command-line options for VPR place_and_route */ -/* Add any option by following the format of t_opt_info */ -t_opt_info exit_opts[] = { - {LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"} -}; - -void shell_execute_exit(t_shell_env* env, t_opt_info* opts); - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_bitstream.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_bitstream.c deleted file mode 100644 index db84a9655..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_bitstream.c +++ /dev/null @@ -1,47 +0,0 @@ - -/* Include vpr structs*/ -#include "util.h" -#include "arch_types.h" -#include "vpr_types.h" - -/* SPICE Support Headers */ -#include "read_xml_spice_util.h" - -#include "read_opt_types.h" -#include "read_opt.h" -#include "shell_types.h" - -#include "linkedlist.h" -#include "fpga_x2p_utils.h" -#include "fpga_bitstream.h" - -boolean shell_setup_fpga_bitstream(t_shell_env* env, t_opt_info* opts) { - /* Setup the PowerOpts */ - env->vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream = TRUE; - env->vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.bitstream_output_file = get_opt_val(opts, "output_file"); - - if (NULL == env->arch.spice) { - vpr_printf(TIO_MESSAGE_ERROR, - "FPGA X2P Information has not been initialized in architecture!\nPlease redo read_arch by enabling read_xml_fpga_x2p option!\n"); - return FALSE; - } - - return TRUE; -} - -void shell_execute_fpga_bitstream(t_shell_env* env, t_opt_info* opts) { - t_sram_orgz_info* sram_bitstream_orgz_info = NULL; - - if (FALSE == shell_setup_fpga_bitstream(env, opts)) { - return; - } - - vpr_fpga_bitstream_generator(env->vpr_setup, env->arch, - env->vpr_setup.FileNameOpts.CircuitName, - &sram_bitstream_orgz_info); - - free_sram_orgz_info(sram_bitstream_orgz_info, - sram_bitstream_orgz_info->type); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_bitstream.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_bitstream.h deleted file mode 100644 index e69e59d67..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_bitstream.h +++ /dev/null @@ -1,10 +0,0 @@ -/* Command-line options for VPR place_and_route */ -/* Add any option by following the format of t_opt_info */ -t_opt_info fpga_bitstream_opts[] = { - {"output_file", "--output_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the output file containing bitstream"}, - {HELP_OPT_TAG, HELP_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"}, - {LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"} -}; - -/* Function to execute the command */ -void shell_execute_fpga_bitstream(t_shell_env* env, t_opt_info* opts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_spice.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_spice.c deleted file mode 100644 index 5a41f0593..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_spice.c +++ /dev/null @@ -1,79 +0,0 @@ -/* Include vpr structs*/ -#include "util.h" -#include "arch_types.h" -#include "vpr_types.h" - -/* SPICE Support Headers */ -#include "read_xml_spice_util.h" - -#include "read_opt_types.h" -#include "read_opt.h" -#include "shell_types.h" - -#include "spice_api.h" - -boolean shell_setup_fpga_spice(t_shell_env* env, t_opt_info* opts) { - /* Setup the PowerOpts */ - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice = TRUE; - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_dir = get_opt_val(opts, "output_dir"); - - /* TODO: this could be more flexible*/ - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.include_dir = "include/"; - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.subckt_dir = "subckt/"; - - - if (NULL == env->arch.spice) { - vpr_printf(TIO_MESSAGE_ERROR, - "FPGA X2P Information has not been initialized in architecture!\nPlease redo read_arch by enabling read_xml_fpga_x2p option!\n"); - return FALSE; - } - - /* Configure FPGA X2P options*/ - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_testbench_load_extraction = is_opt_set(opts, "testbench_load_extraction", TRUE); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_parasitic_net_estimation = is_opt_set(opts, "parasitic_net_estimation", TRUE); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only = is_opt_set(opts, "leakage_only", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_top_testbench = is_opt_set(opts, "print_top_testbench", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_pb_mux_testbench = is_opt_set(opts, "print_pb_mux_testbench", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_cb_mux_testbench = is_opt_set(opts, "print_cb_mux_testbench", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_sb_mux_testbench = is_opt_set(opts, "print_sb_mux_testbench", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_cb_testbench = is_opt_set(opts, "print_cb_testbench", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_sb_testbench = is_opt_set(opts, "print_sb_testbench", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_lut_testbench = is_opt_set(opts, "print_lut_testbench", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_hardlogic_testbench = is_opt_set(opts, "print_hardlogic_testbench", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_io_testbench = is_opt_set(opts, "print_io_testbench", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_grid_testbench = is_opt_set(opts, "print_grid_testbench", FALSE); - - /* Set default options */ - if ((TRUE == env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) - &&(FALSE == env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_top_testbench) - &&(FALSE == env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_grid_testbench) - &&(FALSE == env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_pb_mux_testbench) - &&(FALSE == env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_cb_mux_testbench) - &&(FALSE == env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_sb_mux_testbench) - &&(FALSE == env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_cb_testbench) - &&(FALSE == env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_sb_testbench) - &&(FALSE == env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_lut_testbench) - &&(FALSE == env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_hardlogic_testbench)) { - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_pb_mux_testbench = TRUE; - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_cb_mux_testbench = TRUE; - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_sb_mux_testbench = TRUE; - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_lut_testbench = TRUE; - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_hardlogic_testbench = TRUE; - } - - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_sim_multi_thread_num = get_opt_int_val(opts, "sim_multi_thread_num", 8); - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.simulator_path = get_opt_val(opts, "simulator_path"); - - return TRUE; -} - -void shell_execute_fpga_spice(t_shell_env* env, t_opt_info* opts) { - if (FALSE == shell_setup_fpga_spice(env, opts)) { - return; - } - - vpr_fpga_spice(env->vpr_setup, env->arch, - env->vpr_setup.FileNameOpts.CircuitName); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_spice.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_spice.h deleted file mode 100644 index 648afb22e..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_spice.h +++ /dev/null @@ -1,25 +0,0 @@ -/* Command-line options for VPR place_and_route */ -/* Add any option by following the format of t_opt_info */ -t_opt_info fpga_spice_opts[] = { - {"output_dir", "--output_dir", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the directory path of outputted SPICE netlists"}, - {"testbench_load_extraction", "-tle,--testbench_load_extraction", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable the load extraction when building SPICE testbenches"}, - {"parasitic_net_estimation", "-pne,--parasitic_net_estimation", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable the parasitic net estimation when building SPICE testbenches"}, - {"leakage_only", "--leakage_only", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Only measure leakage power when building SPICE testbenches"}, - {"print_top_testbench", "--print_top_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output top-level testbench for full FPGA fabrics"}, - {"print_pb_mux_testbench", "--print_pb_mux_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output multiplexer testbenches for Configurable Logic Blocks"}, - {"print_cb_mux_testbench", "--print_cb_mux_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output multiplexer testbenches for Connection Blocks"}, - {"print_sb_mux_testbench", "--print_sb_mux_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output multiplexer testbenches for Switch Blocks"}, - {"print_cb_testbench", "--print_cb_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output testbenches for Connection Blocks"}, - {"print_sb_testbench", "--print_sb_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output testbenches for Switch Blocks"}, - {"print_lut_testbench", "--print_lut_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output testbenches for Look-Up Tables"}, - {"print_hardlogic_testbench", "--print_hardlogic_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output testbenches for Hard Logics"}, - {"print_io_testbench", "--print_io_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output testbenches for IO pads"}, - {"print_grid_testbench", "--print_grid_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output testbenches for CLBs and Heterogeneous Blocks"}, - {"sim_multi_thread_num", "--sim_multi_thread_num", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, "Specify the number of threads used by simulator"}, - {"simulator_path", "--simulator_path", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the simulator path"}, - {HELP_OPT_TAG, HELP_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"}, - {LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"} -}; - -/* Function to execute the command */ -void shell_execute_fpga_spice(t_shell_env* env, t_opt_info* opts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c deleted file mode 100644 index e127e66aa..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c +++ /dev/null @@ -1,61 +0,0 @@ - -/* Include vpr structs*/ -#include "util.h" -#include "arch_types.h" -#include "vpr_types.h" - -/* SPICE Support Headers */ -#include "read_xml_spice_util.h" - -#include "read_opt_types.h" -#include "read_opt.h" -#include "shell_types.h" - -#include "linkedlist.h" -#include "fpga_x2p_utils.h" -#include "verilog_api.h" - -boolean shell_setup_fpga_verilog(t_shell_env* env, t_opt_info* opts) { - /* Setup the PowerOpts */ - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog = TRUE; - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.syn_verilog_dump_dir = get_opt_val(opts, "output_dir"); - - if (NULL == env->arch.spice) { - vpr_printf(TIO_MESSAGE_ERROR, - "FPGA X2P Information has not been initialized in architecture!\nPlease redo read_arch by enabling read_xml_fpga_x2p option!\n"); - return FALSE; - } - - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_testbench = is_opt_set(opts, "print_top_testbench", TRUE); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench = is_opt_set(opts, "print_autocheck_top_testbench", TRUE); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file = get_opt_val(opts, "reference_verilog_benchmark_file"); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_input_blif_testbench = is_opt_set(opts, "print_input_blif_testbench", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist = is_opt_set(opts, "print_formal_verification_top_netlist", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.include_timing = is_opt_set(opts, "include_timing", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.include_signal_init = is_opt_set(opts, "include_signal_init", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.include_icarus_simulator = is_opt_set(opts, "include_icarus_simulator", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_modelsim_autodeck = is_opt_set(opts, "print_modelsim_autodeck", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.modelsim_ini_path = get_opt_val(opts, "modelsim_ini_path"); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_user_defined_template = is_opt_set(opts, "print_user_defined_template", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_report_timing_tcl = is_opt_set(opts, "print_report_timing_tcl", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.report_timing_path = get_opt_val(opts, "report_timing_dir_path"); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_pnr = is_opt_set(opts, "print_sdc_pnr", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_sdc_analysis = is_opt_set(opts, "print_sdc_analysis", FALSE); - - return TRUE; -} - -void shell_execute_fpga_verilog(t_shell_env* env, t_opt_info* opts) { - - if (FALSE == shell_setup_fpga_verilog(env, opts)) { - return; - } - - vpr_fpga_verilog(env->module_manager, env->bitstream_manager, env->fabric_bitstream, - env->mux_lib, env->logical_blocks, env->device_size, env->grids, env->blocks, - env->device_rr_gsb, - env->vpr_setup, env->arch, - std::string(env->vpr_setup.FileNameOpts.CircuitName), &(env->sram_orgz_info)); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.h deleted file mode 100644 index 1fe5bebe6..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.h +++ /dev/null @@ -1,25 +0,0 @@ -/* Command-line options for VPR place_and_route */ -/* Add any option by following the format of t_opt_info */ -t_opt_info fpga_verilog_opts[] = { - {"output_dir", "--output_dir", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the output directory containing Verilog netlists"}, - {"print_top_testbench", "--print_top_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output the top-level testbench for full FPGA fabric"}, - {"print_autocheck_top_testbench", "--print_autodeck_top_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output the top-level testbench for full FPGA fabric with autocheck features"}, - {"reference_verilog_benchmark_file", "--reference_verilog_benchmark_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the reference Verilog benchmark file used by the autocheck top-level testbench"}, - {"print_input_blif_testbench", "--print_input_blif_testbench", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output the testbench for the input blif benchmark"}, - {"print_formal_verification_top_netlist", "--print_formal_verification_top_netlist", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output the top-level Verilog netlist for full FPGA fabric adapted to formal verification"}, - {"include_timing", "--include_timing", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Include timing annotation in the outputted Verilog netlists"}, - {"include_signal_init", "--include_signal_init", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Include signal initialization in the outputted Verilog netlists"}, - {"print_modelsim_autodeck", "--print_modelsim_autodeck", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Output the script to launch Modelsim simulation for the autocheck testbench"}, - {"modelsim_ini_path", "--modelsim_ini_path", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the path of modelsim.ini file"}, - {"print_user_defined_template", "--print_user_defined_template", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output the Verilog template for user-defined modules"}, - {"print_report_timing_tcl", "--print_report_timing_tcl", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output the TCL script in report timing purpose"}, - {"report_timing_dir_path", "--report_timing_dir_path", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the directory path of report timing results"}, - {"print_sdc_pnr", "--print_sdc_pnr", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output the SDC file in P&R purpose"}, - {"print_sdc_analysis", "--print_sdc_analysis", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable output the SDC file in Timing/Power analysis purpose"}, - {"include_icarus_simulator", "--include_icarus_simulator", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable Verilog preprocessing flags and features for Icarus simulator"}, - {HELP_OPT_TAG, HELP_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"}, - {LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"} -}; - -/* Function to execute the command */ -void shell_execute_fpga_verilog(t_shell_env* env, t_opt_info* opts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.c deleted file mode 100644 index 0b3a9b449..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.c +++ /dev/null @@ -1,47 +0,0 @@ -/* Include vpr structs*/ -#include "util.h" -#include "arch_types.h" -#include "vpr_types.h" - -/* SPICE Support Headers */ -#include "read_xml_spice_util.h" - -#include "read_opt_types.h" -#include "read_opt.h" -#include "shell_types.h" - -#include "vpr_api.h" -#include "fpga_x2p_setup.h" - -boolean shell_setup_fpga_x2p_setup(t_shell_env* env, t_opt_info* opts) { - /* Setup the PowerOpts */ - env->vpr_setup.FPGA_SPICE_Opts.do_fpga_spice = TRUE; - - if (NULL == env->arch.spice) { - vpr_printf(TIO_MESSAGE_ERROR, - "FPGA X2P Information has not been initialized in architecture!\nPlease redo read_arch by enabling read_xml_fpga_x2p option!\n"); - return FALSE; - } - - /* Configure FPGA X2P options*/ - env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_parasitic_net_estimation = is_opt_set(opts, "parasitic_net_estimation", TRUE); - env->vpr_setup.FPGA_SPICE_Opts.read_act_file = env->vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_parasitic_net_estimation; - - - env->vpr_setup.FPGA_SPICE_Opts.rename_illegal_port = is_opt_set(opts, "rename_illegal_port", FALSE); - env->vpr_setup.FPGA_SPICE_Opts.signal_density_weight = get_opt_float_val(opts, "signal_density_weight", 1.); - env->vpr_setup.FPGA_SPICE_Opts.sim_window_size = get_opt_float_val(opts, "sim_window_size", 0.5); - env->vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy = is_opt_set(opts, "compact_routing_hierarchy", FALSE); - - return TRUE; -} - -void shell_execute_fpga_x2p_setup(t_shell_env* env, t_opt_info* opts) { - if (FALSE == shell_setup_fpga_x2p_setup(env, opts)) { - return; - } - - fpga_x2p_setup(env->vpr_setup, &(env->arch)); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.h deleted file mode 100644 index 23b418dfa..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_x2p_setup.h +++ /dev/null @@ -1,15 +0,0 @@ -/* Command-line options for VPR place_and_route */ -/* Add any option by following the format of t_opt_info */ -t_opt_info fpga_x2p_setup_opts[] = { - {"activity_file", "-a,--activity_file,",0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the activity file"}, - {"parasitic_net_estimation", "-pne,--parasitic_net_estimation", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Enable the parasitic net estimation when building SPICE testbenches"}, - {"rename_illegal_port", "-rip,--rename_illegal_port", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Rename illegal ports that violates Verilog syntax"}, - {"signal_density_weight", "-sdw,--signal_density_weight", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, "Specify the signal density weight when doing the average number"}, - {"sim_window_size", "-sws,--sim_window_size", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, "Specify the size of window when doing simulation"}, - {"compact_routing_hierarchy", "-crh,--compact_routing_hierarchy", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify if use a compact routing hierarchy in SPIC/Verilog generation"}, - {HELP_OPT_TAG, HELP_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"}, - {LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"} -}; - -/* Function to execute the command */ -void shell_execute_fpga_x2p_setup(t_shell_env* env, t_opt_info* opts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_help.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_help.c deleted file mode 100644 index 0ff1f93bd..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_help.c +++ /dev/null @@ -1,19 +0,0 @@ - -/* Include vpr structs*/ -#include "util.h" -#include "arch_types.h" -#include "vpr_types.h" - -/* SPICE Support Headers */ -#include "read_xml_spice_util.h" - -#include "read_opt_types.h" -#include "shell_types.h" -#include "shell_utils.h" - -void shell_execute_help(t_shell_env* env, t_opt_info* opts) { - - shell_print_usage(env); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_help.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_help.h deleted file mode 100644 index d5f15f879..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_help.h +++ /dev/null @@ -1,8 +0,0 @@ -/* Command-line options for VPR place_and_route */ -/* Add any option by following the format of t_opt_info */ -t_opt_info help_opts[] = { - {LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"} -}; - - -void shell_execute_help(t_shell_env* env, t_opt_info* opts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_pack.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_pack.c deleted file mode 100644 index 97466656e..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_pack.c +++ /dev/null @@ -1,135 +0,0 @@ -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "arch_types.h" - -/* SPICE Support Headers */ -#include "read_xml_spice_util.h" - - -#include "vpr_types.h" -#include "vpr_utils.h" -#include "globals.h" -#include "pack.h" -#include "vpr_api.h" - -#include "read_opt_types.h" -#include "read_opt.h" -#include "shell_types.h" - -void shell_execute_vpr_pack(t_shell_env* env, - t_opt_info* opts) { - char* temp = NULL; - - - vpr_printf(TIO_MESSAGE_INFO, - "Setup vpr_packer...\n"); - /* Packer File Names */ - /* Post packing netlist */ - temp = get_opt_val(opts, "net_file"); - if (NULL != temp) { - env->vpr_setup.FileNameOpts.NetFile = temp; - } - - /* SDC constraints */ - temp = get_opt_val(opts, "sdc_file"); - if (NULL != temp) { - env->vpr_setup.Timing.SDCFile = temp; - } - - /* Packer Options */ - if (env->arch.clb_grid.IsAuto) { - env->vpr_setup.PackerOpts.aspect = env->arch.clb_grid.Aspect; - } else { - env->vpr_setup.PackerOpts.aspect = (float) env->arch.clb_grid.H / (float) env->arch.clb_grid.W; - } - env->vpr_setup.PackerOpts.output_file = my_strdup(env->vpr_setup.FileNameOpts.NetFile); - - env->vpr_setup.PackerOpts.blif_file_name = my_strdup(env->vpr_setup.FileNameOpts.BlifFile); - - /* Call this program, it means that we need to do packing */ - env->vpr_setup.PackerOpts.doPacking = TRUE; - - env->vpr_setup.PackerOpts.global_clocks = is_opt_set(opts, "global_clocks", TRUE); - - env->vpr_setup.PackerOpts.hill_climbing_flag = is_opt_set(opts, "hill_climbing", FALSE); - - env->vpr_setup.PackerOpts.sweep_hanging_nets_and_inputs = is_opt_set(opts, "sweep_hanging_nets_and_inputs", TRUE); - - env->vpr_setup.PackerOpts.skip_clustering = is_opt_set(opts, "skip_clustering", FALSE); - - env->vpr_setup.PackerOpts.allow_unrelated_clustering = is_opt_set(opts, "allow_unrelated_clustering", TRUE); - - env->vpr_setup.PackerOpts.allow_early_exit = is_opt_set(opts, "allow_early_exit", FALSE); - - env->vpr_setup.PackerOpts.connection_driven = is_opt_set(opts, "connection_driven", TRUE); - - env->vpr_setup.PackerOpts.timing_driven = is_opt_set(opts, "timing_driven", TRUE); - - env->vpr_setup.PackerOpts.cluster_seed_type = ( - env->vpr_setup.PackerOpts.timing_driven ? VPACK_TIMING : VPACK_MAX_INPUTS); /* DEFAULT */ - /* Get the value if we have any */ - temp = get_opt_val(opts, "cluster_seed_type"); - if (NULL != temp) { - if (0 == strcmp(temp, "timing")) { - env->vpr_setup.PackerOpts.cluster_seed_type = VPACK_TIMING; - } else if (0 == strcmp(temp, "max_inputs")) { - env->vpr_setup.PackerOpts.cluster_seed_type = VPACK_MAX_INPUTS; - } - } - /* Free */ - my_free(temp); - - env->vpr_setup.PackerOpts.alpha = get_opt_float_val(opts, "alpha", 0.75); /* DEFAULT */ - - env->vpr_setup.PackerOpts.beta = get_opt_float_val(opts, "beta", 0.9); /* DEFAULT */ - - - /* never recomputer timing */ - env->vpr_setup.PackerOpts.recompute_timing_after = get_opt_int_val(opts, "recompute_timing_after", MAX_SHORT); /* DEFAULT */ - - vpr_printf(TIO_MESSAGE_INFO, - "Launch pack_algorithm...\n"); - - env->vpr_setup.PackerOpts.block_delay = get_opt_int_val(opts, "block_delay", 0) ; /* DEFAULT */ - - - env->vpr_setup.PackerOpts.intra_cluster_net_delay = get_opt_float_val(opts, "intra_cluster_net_delay", 0.); /* DEFAULT */ - - env->vpr_setup.PackerOpts.inter_cluster_net_delay = get_opt_float_val(opts, "inter_cluster_net_delay", 1.0); /* DEFAULT */ - - - - env->vpr_setup.PackerOpts.auto_compute_inter_cluster_net_delay = is_opt_set(opts, "auto_compute_inter_cluster_net_delay", TRUE); - - - env->vpr_setup.PackerOpts.packer_algorithm = PACK_GREEDY; /* DEFAULT */ - /* Get the value if we have any */ - temp = get_opt_val(opts, "algorithm"); - if (NULL != temp) { - if (0 == strcmp(temp, "greedy")) { - env->vpr_setup.PackerOpts.packer_algorithm = PACK_GREEDY; - } else if (0 == strcmp(temp, "brute_force")) { - env->vpr_setup.PackerOpts.packer_algorithm = PACK_BRUTE_FORCE; - } - } - /* Free */ - my_free(temp); - - /* Xifan TANG: PACK_CLB_PIN_REMAP */ - env->vpr_setup.PackerOpts.pack_clb_pin_remap = is_opt_set(opts, "clb_pin_remap", FALSE); /* DEFAULT */ - - /* TODO: check if we have done read_blif and read_arch !!! */ - - /* Run VPR packer */ - - vpr_printf(TIO_MESSAGE_INFO, - "Launch vpr_packer...\n"); - vpr_pack(env->vpr_setup, env->arch); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_pack.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_pack.h deleted file mode 100644 index b08fcee8b..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_pack.h +++ /dev/null @@ -1,32 +0,0 @@ -/* Command-line options for Packer */ -t_opt_info vpr_pack_opts[] = { - /* Packer Options should be listed here */ - /* Packer File Options */ - {"sdc_file", "--sdc_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "File name of SDC constraints"}, - {"net_file", "--net_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "File name of post-packing netlist"}, - /* Packer Options */ - {"global_clocks", "--global_clocks", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"hill_climb", "--hill_climb", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"sweep_hanging_nets_and_inputs", "-s,--sweep", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"timing_driven", "--timing_driven", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"cluster_seed_type", "--seed_type", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"alpha", "--alpha", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"beta", "--beta", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"recompute_timing_after", "--recompute_timing_after", 0, OPT_WITHVAL, OPT_INT, OPT_OPT, OPT_NONDEF, ""}, - {"block_delay", "--block_delay", 0, OPT_WITHVAL, OPT_INT, OPT_OPT, OPT_NONDEF, ""}, - {"intra_cluster_net_delay", "--intra_cluster_net_delay", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"inter_cluster_net_delay", "--inter_cluster_net_delay", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"auto_compute_inter_cluster_net_delay", "--auto_compute_inter_cluster_net_delay", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"skip_clustering", "--skip_clustering", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"allow_unrelated_clustering", "--allow_unrelated_clustering", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"allow_early_exit", "--allow_early_exit", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"connection_driven", "--connnection_driven", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"aspect", "--aspect", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"algorithm", "--algorithm", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {HELP_OPT_TAG, HELP_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"}, - {LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"} -}; - -/* Function to execute the command */ -void shell_execute_vpr_pack(t_shell_env* env, - t_opt_info* opts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_place_and_route.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_place_and_route.c deleted file mode 100644 index 1639dc785..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_place_and_route.c +++ /dev/null @@ -1,329 +0,0 @@ -#include -/* Include vpr structs*/ -#include "util.h" -#include "arch_types.h" -#include "vpr_types.h" - -/* SPICE Support Headers */ -#include "read_xml_spice_util.h" - -#include "read_opt_types.h" -#include "read_opt.h" -#include "shell_types.h" - -#include "vpr_api.h" - -void shell_init_vpr_placer(t_shell_env* env, t_opt_info* opts) { - char* temp = NULL; - - /* Placer File names */ - /* Post packing netlist */ - temp = get_opt_val(opts, "net_file"); - if (NULL != temp) { - env->vpr_setup.FileNameOpts.NetFile = temp; - } - - /* Post placement netlist */ - temp = get_opt_val(opts, "place_file"); - if (NULL != temp) { - env->vpr_setup.FileNameOpts.PlaceFile = temp; - } - - /* Placer Options */ - env->vpr_setup.TimingEnabled = is_opt_set(opts, "timing_driven", TRUE); /* DEFAULT */ - - /* Set seed for pseudo-random placement, default seed to 1 */ - env->vpr_setup.PlacerOpts.seed = get_opt_int_val(opts, "seed", 1); /* DEFAULT */ - my_srandom(env->vpr_setup.PlacerOpts.seed); - - env->vpr_setup.PlacerOpts.block_dist = get_opt_int_val(opts, "block_dist", 1); /* DEFAULT */ - - env->vpr_setup.PlacerOpts.inner_loop_recompute_divider = get_opt_int_val(opts, "inner_loop_recompute_divider", 0); /* DEFAULT */ - - env->vpr_setup.PlacerOpts.place_cost_exp = get_opt_float_val(opts, "place_cost_exp", 1.); /* DEFAULT */ - - env->vpr_setup.PlacerOpts.td_place_exp_first = get_opt_float_val(opts, "place_exp_first", 1.); /* DEFAULT */ - - env->vpr_setup.PlacerOpts.td_place_exp_last = get_opt_float_val(opts, "td_place_exp_last", 8.); /* DEFAULT */ - - env->vpr_setup.PlacerOpts.place_algorithm = BOUNDING_BOX_PLACE; /* DEFAULT */ - if (TRUE == env->vpr_setup.TimingEnabled) { /* DEFAULT */ - env->vpr_setup.PlacerOpts.place_algorithm = PATH_TIMING_DRIVEN_PLACE; /* DEFAULT */ - } - temp = get_opt_val(opts, "placer_algorithm"); - if (NULL != temp) { - if (0 == strcmp(temp, "bounding_box")) { - env->vpr_setup.PlacerOpts.place_algorithm = BOUNDING_BOX_PLACE; - } else if (0 == strcmp(temp, "net_timing_driven")) { - env->vpr_setup.PlacerOpts.place_algorithm = NET_TIMING_DRIVEN_PLACE; - } else if (0 == strcmp(temp, "path_timing_driven")) { - env->vpr_setup.PlacerOpts.place_algorithm = PATH_TIMING_DRIVEN_PLACE;; - } - } - /* Free */ - my_free(temp); - - env->vpr_setup.PlacerOpts.pad_loc_file = get_opt_val(opts, "pad_loc_file"); - - env->vpr_setup.PlacerOpts.pad_loc_type = FREE; /* DEFAULT */ - temp = get_opt_val(opts, "pad_loc_type"); - if (NULL != temp) { - if (0 == strcmp(temp, "free")) { - env->vpr_setup.PlacerOpts.pad_loc_type = FREE; - } else if (0 == strcmp(temp, "user")) { - env->vpr_setup.PlacerOpts.pad_loc_type = USER; - } else if (0 == strcmp(temp, "random")) { - env->vpr_setup.PlacerOpts.pad_loc_type = RANDOM; - } - } - /* Free */ - my_free(temp); - - /* Check */ - if ( (USER == env->vpr_setup.PlacerOpts.pad_loc_type) - && (NULL == env->vpr_setup.PlacerOpts.pad_loc_file)) { - vpr_printf(TIO_MESSAGE_ERROR, - "VPR placer is configured to user-defined pad location while the location file is missing!\n"); - return; - } - - env->vpr_setup.PlacerOpts.place_chan_width = get_opt_int_val(opts, "place_chan_width", 100); /* DEFAULT */ - - env->vpr_setup.PlacerOpts.recompute_crit_iter = get_opt_int_val(opts, "place_chan_width", 1); /* DEFAULT */ - - env->vpr_setup.PlacerOpts.timing_tradeoff = get_opt_float_val(opts, "timing_tradeoff", 0.5); /* DEFAULT */ - - /* Xifan TANG : PLACE_CLB_PIN_REMAP */ - env->vpr_setup.PlacerOpts.place_clb_pin_remap = is_opt_set(opts, "place_clb_pin_remap", FALSE); /* DEFAULT */ - /* END */ - - /* Depends on env->vpr_setup.PlacerOpts.place_algorithm */ - env->vpr_setup.PlacerOpts.enable_timing_computations = FALSE; /* DEFAULT */ - if ((env->vpr_setup.PlacerOpts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) - || (env->vpr_setup.PlacerOpts.place_algorithm == NET_TIMING_DRIVEN_PLACE)) { - env->vpr_setup.PlacerOpts.enable_timing_computations = TRUE; /* DEFAULT */ - } - - /* Annealing options */ - env->vpr_setup.AnnealSched.alpha_t = get_opt_float_val(opts, "alpha_t", 0.8); /* DEFAULT */ - if (env->vpr_setup.AnnealSched.alpha_t >= 1. || env->vpr_setup.AnnealSched.alpha_t <= 0.) { - vpr_printf(TIO_MESSAGE_ERROR, - "alpha_t(%.2g) must be between 0 and 1 exclusive.\n", - env->vpr_setup.AnnealSched.alpha_t); - return; - } - - env->vpr_setup.AnnealSched.exit_t = get_opt_float_val(opts, "exit_t", 0.01); /* DEFAULT */ - if (env->vpr_setup.AnnealSched.exit_t <= 0.) { - vpr_printf(TIO_MESSAGE_ERROR, "exit_t must be greater than 0.\n"); - return; - } - - env->vpr_setup.AnnealSched.init_t = get_opt_float_val(opts, "init_t", 100.0); /* DEFAULT */ - if (env->vpr_setup.AnnealSched.init_t <= 0.) { - vpr_printf(TIO_MESSAGE_ERROR, "init_t must be greater than 0.\n"); - return; - } - if (env->vpr_setup.AnnealSched.init_t < env->vpr_setup.AnnealSched.exit_t) { - vpr_printf(TIO_MESSAGE_ERROR, - "init_t must be greater or equal to than exit_t.\n"); - return; - } - - env->vpr_setup.AnnealSched.inner_num = get_opt_float_val(opts, "inner_num", 1.0); /* DEFAULT */ - if (env->vpr_setup.AnnealSched.inner_num <= 0) { - vpr_printf(TIO_MESSAGE_ERROR, "init_t must be greater than 0.\n"); - return; - } - - env->vpr_setup.AnnealSched.type = AUTO_SCHED; /* DEFAULT */ - if ( (TRUE == is_opt_set(opts, "alpha_t", FALSE)) - || (TRUE == is_opt_set(opts, "exit_it", FALSE)) - || (TRUE == is_opt_set(opts, "init_it", FALSE))) { - env->vpr_setup.AnnealSched.type = USER_SCHED; - } - - /* Enable Placer*/ - env->vpr_setup.PlacerOpts.doPlacement = TRUE; - - return; -} - -void shell_init_vpr_router(t_shell_env* env, t_opt_info* opts) { - char* temp = NULL; - - /* Router File names */ - /* Post packing netlist */ - temp = get_opt_val(opts, "net_file"); - if (NULL != temp) { - env->vpr_setup.FileNameOpts.NetFile = temp; - } - - /* Post placement netlist */ - temp = get_opt_val(opts, "place_file"); - if (NULL != temp) { - env->vpr_setup.FileNameOpts.PlaceFile = temp; - } - - /* Post placement netlist */ - temp = get_opt_val(opts, "route_file"); - if (NULL != temp) { - env->vpr_setup.FileNameOpts.RouteFile = temp; - } - - /* Router Options */ - env->vpr_setup.TimingEnabled = is_opt_set(opts, "timing_driven", TRUE); /* DEFAULT */ - - env->vpr_setup.RouterOpts.astar_fac = get_opt_float_val(opts, "astar_fac", 1.2); /* DEFAULT */ - - if (TRUE == is_opt_set(opts, "fast", FALSE)) { - env->vpr_setup.RouterOpts.bb_factor = get_opt_int_val(opts, "astar_fac", 0); /* DEFAULT */ - } else { - env->vpr_setup.RouterOpts.bb_factor = get_opt_int_val(opts, "astar_fac", 3); /* DEFAULT */ - } - - env->vpr_setup.RouterOpts.criticality_exp = get_opt_float_val(opts, "criticality_exp", 1.0); /* DEFAULT */ - - env->vpr_setup.RouterOpts.max_criticality = get_opt_float_val(opts, "max_criticality", 0.99); /* DEFAULT */ - - if (TRUE == is_opt_set(opts, "fast", FALSE)) { - env->vpr_setup.RouterOpts.max_router_iterations = get_opt_int_val(opts, "max_router_iterations", 10); /* DEFAULT */ - } else { - env->vpr_setup.RouterOpts.max_router_iterations = get_opt_int_val(opts, "max_router_iterations", 50); /* DEFAULT */ - } - - env->vpr_setup.RouterOpts.pres_fac_mult = get_opt_float_val(opts, "pres_fac_mult", 1.3); /* DEFAULT */ - - env->vpr_setup.RouterOpts.route_type = DETAILED; /* DEFAULT */ - temp = get_opt_val(opts, "router_type"); - if (NULL != temp) { - if ( 0 == strcmp(temp, "detailed") ) { - env->vpr_setup.RouterOpts.route_type = DETAILED; - } else if ( 0 == strcmp(temp, "global") ) { - env->vpr_setup.RouterOpts.route_type = GLOBAL; - } - } - /* Free */ - my_free(temp); - - env->vpr_setup.RouterOpts.full_stats = is_opt_set(opts, "full_stats", FALSE); /* DEFAULT */ - - env->vpr_setup.RouterOpts.verify_binary_search = is_opt_set(opts, "verify_binary_search", FALSE); /* DEFAULT */ - - /* Depends on RouteOpts->route_type */ - env->vpr_setup.RouterOpts.router_algorithm = NO_TIMING; /* DEFAULT */ - if (env->vpr_setup.TimingEnabled) { - env->vpr_setup.RouterOpts.router_algorithm = TIMING_DRIVEN; /* DEFAULT */ - } - if (GLOBAL == env->vpr_setup.RouterOpts.route_type) { - env->vpr_setup.RouterOpts.router_algorithm = NO_TIMING; /* DEFAULT */ - } - temp = get_opt_val(opts, "router_algorithm"); - if (NULL != temp) { - if ( 0 == strcmp(temp, "no_timing") ) { - env->vpr_setup.RouterOpts.router_algorithm = NO_TIMING; - } else if ( 0 == strcmp(temp, "timing_driven") ) { - env->vpr_setup.RouterOpts.router_algorithm = TIMING_DRIVEN; - } else if ( 0 == strcmp(temp, "breadth_first") ) { - env->vpr_setup.RouterOpts.router_algorithm = BREADTH_FIRST; - } - } - /* Free */ - my_free(temp); - - env->vpr_setup.RouterOpts.fixed_channel_width = NO_FIXED_CHANNEL_WIDTH; /* DEFAULT */ - temp = get_opt_val(opts, "route_chan_width"); - if (NULL != temp) { - env->vpr_setup.RouterOpts.fixed_channel_width = process_int_arg(temp); - } - /* Free */ - my_free(temp); - - /* mrFPGA: Xifan TANG */ - is_show_sram = is_opt_set(opts, "show_sram", FALSE); - is_show_pass_trans = is_opt_set(opts, "show_pass_trans", FALSE); - /* END */ - - /* Depends on env->vpr_setup.RouterOpts.router_algorithm */ - if (NO_TIMING == env->vpr_setup.RouterOpts.router_algorithm || is_opt_set(opts, "fast", FALSE)) { - env->vpr_setup.RouterOpts.initial_pres_fac = get_opt_int_val(opts, "initial_pres_fac", 10000.0); /* DEFAULT */ - } else { - env->vpr_setup.RouterOpts.initial_pres_fac = get_opt_int_val(opts, "initial_pres_fac", 0.5); /* DEFAULT */ - } - - /* Depends on env->vpr_setup.RouterOpts.router_algorithm */ - env->vpr_setup.RouterOpts.base_cost_type = DELAY_NORMALIZED; /* DEFAULT */ - if (BREADTH_FIRST == env->vpr_setup.RouterOpts.router_algorithm) { - env->vpr_setup.RouterOpts.base_cost_type = DEMAND_ONLY; /* DEFAULT */ - } - if (NO_TIMING == env->vpr_setup.RouterOpts.router_algorithm) { - env->vpr_setup.RouterOpts.base_cost_type = DEMAND_ONLY; /* DEFAULT */ - } - temp = get_opt_val(opts, "base_cost_type"); - if (NULL != temp) { - if ( 0 == strcmp(temp, "demand_only") ) { - env->vpr_setup.RouterOpts.base_cost_type = DEMAND_ONLY; - } else if ( 0 == strcmp(temp, "intrinsic_delay") ) { - env->vpr_setup.RouterOpts.base_cost_type = INTRINSIC_DELAY; - } else if ( 0 == strcmp(temp, "delay_normalized") ) { - env->vpr_setup.RouterOpts.base_cost_type = DELAY_NORMALIZED; - } - } - /* Free */ - my_free(temp); - - /* Depends on env->vpr_setup.RouterOpts.router_algorithm */ - if (BREADTH_FIRST == env->vpr_setup.RouterOpts.router_algorithm) { - env->vpr_setup.RouterOpts.first_iter_pres_fac = get_opt_float_val(opts, "first_iter_pres_fac", 0.0); /* DEFAULT */ - } else if ( (NO_TIMING == env->vpr_setup.RouterOpts.router_algorithm) - || (TRUE == is_opt_set(opts, "fast", FALSE)) ) { - env->vpr_setup.RouterOpts.first_iter_pres_fac = get_opt_float_val(opts, "first_iter_pres_fac", 10000.0); /* DEFAULT */ - } else { - env->vpr_setup.RouterOpts.first_iter_pres_fac = get_opt_float_val(opts, "first_iter_pres_fac", 0.5); /* DEFAULT */ - } - - /* Depends on env->vpr_setup.RouterOpts.router_algorithm */ - if (BREADTH_FIRST == env->vpr_setup.RouterOpts.router_algorithm) { - env->vpr_setup.RouterOpts.acc_fac = get_opt_float_val(opts, "acc_fac", 0.2); - } else { - env->vpr_setup.RouterOpts.acc_fac = get_opt_float_val(opts, "acc_fac", 1.0); - } - - /* Depends on env->vpr_setup.RouterOpts.route_type */ - if (GLOBAL == env->vpr_setup.RouterOpts.route_type) { - env->vpr_setup.RouterOpts.bend_cost = get_opt_float_val(opts, "bend_cost", 1.0); /* DEFAULT */ - } else { - env->vpr_setup.RouterOpts.bend_cost = get_opt_float_val(opts, "bend_cost", 0.0); /* DEFAULT */ - } - - /* Enable router */ - env->vpr_setup.RouterOpts.doRouting = TRUE; - - return; -} - -void shell_init_vpr_place_and_route(t_shell_env* env, t_opt_info* opts) { - - shell_init_vpr_placer(env, opts); - - shell_init_vpr_router(env, opts); - - env->vpr_setup.PlacerOpts.place_freq = PLACE_ONCE; /* DEFAULT */ - if ( (TRUE == is_opt_set(opts, "place_chan_width", FALSE)) - || (TRUE == is_opt_set(opts, "route_chan_width", FALSE)) ) { - env->vpr_setup.PlacerOpts.place_freq = PLACE_ONCE; - } - - return; -} - -void shell_execute_vpr_place_and_route(t_shell_env* env, t_opt_info* opts) { - - shell_init_vpr_place_and_route(env, opts); - - vpr_init_pre_place_and_route(env->vpr_setup, env->arch); - - vpr_place_and_route(env->vpr_setup, env->arch); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_place_and_route.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_place_and_route.h deleted file mode 100644 index 6ab163275..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_place_and_route.h +++ /dev/null @@ -1,56 +0,0 @@ -/* Command-line options for VPR place_and_route */ -/* Add any option by following the format of t_opt_info */ -t_opt_info vpr_place_and_route_opts[] = { - /* File names */ - {"net_file", "--net_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the post-packing netlist"}, - /* General options */ - {"timing_driven", "--timing_driven", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify if algorithms are timing-driven"}, - /* Placer Options should be listed here */ - {"block_dist", "--block_dist", 0, OPT_WITHVAL, OPT_INT, OPT_OPT, OPT_NONDEF, ""}, - {"inner_loop_recompute_divider", "--inner_loop_recompute_divider", 0, OPT_WITHVAL, OPT_INT, OPT_OPT, OPT_NONDEF, ""}, - {"place_cost_exp", "--place_cost_exp", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"place_exp_first", "--place_exp_first", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"place_exp_last", "--place_exp_last", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"placer_algorithm", "--placer_algorithm", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Available algorithms of Placer: bounding_box|net_timing_driven|path_timing_driven"}, - {"pad_loc_type", "--pad_loc_type", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the location type of IO pads: free|user|random"}, - {"pad_loc_file", "--pad_loc_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the filename to constrain the location of IO pads"}, - {"place_chan_width", "--place_chan_width", 0, OPT_WITHVAL, OPT_INT, OPT_OPT, OPT_NONDEF, "Specify the routing channel width used by placer"}, - {"recompute_crit_iter", "--recompute_crit_iter", 0, OPT_WITHVAL, OPT_INT, OPT_OPT, OPT_NONDEF, ""}, - {"timing_tradeoff", "--timing_tradeoff", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"seed", "--seed", 0, OPT_WITHVAL, OPT_INT, OPT_OPT, OPT_NONDEF, ""}, - {"place_clb_pin_remap", "--place_clb_pin_remap", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"place_freq", "--place_freq", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - /* For annealing */ - {"alpha_t", "--alpha_t", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"exit_t", "--exit_t", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"init_t", "--init_t", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"inner_num", "--inner_num", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - /* Router Options should be listed here */ - {"astar_fac", "--astar_fac", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"fast", "--fast", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"bb_factor", "--bb_factor", 0, OPT_WITHVAL, OPT_INT, OPT_OPT, OPT_NONDEF, ""}, - {"criticality_exp", "--criticality_exp", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"max_criticality", "--max_criticality", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"max_router_iterations", "--max_router_iterations", 0, OPT_WITHVAL, OPT_INT, OPT_OPT, OPT_NONDEF, ""}, - {"pres_fac_mult", "--pres_fac_mult", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"router_type", "--router_type", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"full_stats", "--full_stats", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"verify_binary_search", "--verify_binary_search", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"router_algorithm", "--router_algorithm", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"route_channel_width", "--route_chan_width", 0, OPT_WITHVAL, OPT_INT, OPT_OPT, OPT_NONDEF, ""}, - {"show_sram", "--show_sram", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"show_pass_trans", "--show_pass_trans", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"initial_pres_fac", "--initial_pres_fac", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"base_cost_type", "--base_cost_type", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, ""}, - {"first_iter_pres_fac", "--first_iter_pres_fac", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"acc_fac", "--acc_fac", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {"bend_cost", "--bend_cost", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, ""}, - {HELP_OPT_TAG, HELP_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"}, - {LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"} -}; - -/* Function to execute the command */ -void shell_execute_vpr_place_and_route(t_shell_env* env, t_opt_info* opts); - - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_power.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_power.c deleted file mode 100644 index d4cb8c395..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_power.c +++ /dev/null @@ -1,37 +0,0 @@ -/* Include vpr structs*/ -#include "util.h" -#include "arch_types.h" -#include "vpr_types.h" - -/* SPICE Support Headers */ -#include "read_xml_spice_util.h" - -#include "read_opt_types.h" -#include "read_opt.h" -#include "shell_types.h" - -#include "vpr_api.h" - -boolean shell_setup_vpr_versa_power(t_shell_env* env, t_opt_info* opts) { - /* Setup the PowerOpts */ - env->vpr_setup.PowerOpts.do_power = TRUE; - - if ((NULL == env->arch.power) - || (NULL == env->arch.clocks) - || (NULL == g_clock_arch)) { - vpr_printf(TIO_MESSAGE_ERROR, - "Power Information has not been initialized in architecture!\nPlease redo read_arch by enabling versa_power option!\n"); - return FALSE; - } - - return TRUE; -} - -void shell_execute_vpr_versapower(t_shell_env* env, t_opt_info* opts) { - if (FALSE == shell_setup_vpr_versa_power(env, opts)) { - return; - } - - vpr_power_estimation(env->vpr_setup, env->arch); - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_power.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_power.h deleted file mode 100644 index 9753e57b9..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_power.h +++ /dev/null @@ -1,11 +0,0 @@ -/* Command-line options for VPR place_and_route */ -/* Add any option by following the format of t_opt_info */ -t_opt_info vpr_versapower_opts[] = { - {"activity_file", "--activity_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the activity file"}, - {"power_properties", "--power_properties", 0, OPT_WITHVAL, OPT_CHAR, OPT_REQ, OPT_NONDEF, "Specify the power property XML file"}, - {"power_report_file", "--power_report_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the output power report file name"}, - {LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"} -}; - -/* Function to execute the command */ -void shell_execute_vpr_versapower(t_shell_env* env, t_opt_info* opts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_setup.c deleted file mode 100644 index d040f57b6..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_setup.c +++ /dev/null @@ -1,280 +0,0 @@ -#include -#include -/* Include vpr structs*/ -#include "util.h" -#include "arch_types.h" - -/* SPICE Support Headers */ -#include "read_xml_spice_util.h" - -#include "vpr_types.h" -#include "globals.h" -#include "read_xml_arch_file.h" -#include "ReadOptions.h" -#include "read_blif.h" -#include "SetupVPR.h" -#include "pb_type_graph.h" -#include "ReadOptions.h" -/* mrFPGA: Xifan TANG*/ -#include "mrfpga_api.h" -#include "mrfpga_globals.h" -/* END */ - -/* Xifan Tang: include for supporting Direct Parsing */ -#include "vpr_utils.h" - -#include "read_opt_types.h" -#include "read_opt.h" -#include "shell_types.h" - -#include "shell_file_postfix.h" - -char* shell_vpr_get_circuit_name(char* blif_name) { - int offset; - char* circuit_name = my_strdup(blif_name); - - /*if the user entered the circuit name with the .blif extension, remove it now*/ - offset = strlen(circuit_name) - 5; - if (offset > 0 && !strcmp(circuit_name + offset, BLIF_FILE_POSTFIX)) { - circuit_name[offset] = '\0'; - } - vpr_printf(TIO_MESSAGE_INFO, "Circuit name: %s%s\n", - circuit_name, BLIF_FILE_POSTFIX); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - return circuit_name; -} - -char* shell_vpr_setup_gen_one_file_name(char* circuit_name, - char* cur_out_file_prefix, - char* postfix) { - int len; - char* file_name = NULL; - - len = strlen(circuit_name) + 1; /* circuit_name.net/0*/ - if (NULL != cur_out_file_prefix) { - len += strlen(cur_out_file_prefix); - } - if (NULL != postfix) { - len += strlen(postfix); - } - file_name = (char*) my_calloc(len, sizeof(char)); - if (NULL == cur_out_file_prefix ) { - if (NULL == postfix) { - sprintf(file_name, "%s", - circuit_name); - } else { - sprintf(file_name, "%s%s", - circuit_name, postfix); - } - } else { - if (NULL == postfix) { - sprintf(file_name, "%s%s", - cur_out_file_prefix, - circuit_name); - } else { - sprintf(file_name, "%s%s%s", - cur_out_file_prefix, - circuit_name, postfix); - } - } - - return file_name; -} - -void shell_vpr_setup_default_file_names(t_vpr_setup* vpr_setup, - t_opt_info* opts) { - char* circuit_name = shell_vpr_get_circuit_name(get_opt_val(opts, "blif_file")); - char* cur_out_file_prefix = get_opt_val(opts, "out_file_prefix"); - char* cur_default_output_name = NULL; - - vpr_setup->FileNameOpts.ArchFile = get_opt_val(opts, "arch_file"); - vpr_setup->FileNameOpts.CircuitName = circuit_name; - vpr_setup->FileNameOpts.out_file_prefix = cur_out_file_prefix; - vpr_setup->FileNameOpts.BlifFile = shell_vpr_setup_gen_one_file_name(circuit_name, - cur_out_file_prefix, - BLIF_FILE_POSTFIX); - vpr_setup->FileNameOpts.NetFile = shell_vpr_setup_gen_one_file_name(circuit_name, - cur_out_file_prefix, - NET_FILE_POSTFIX); - vpr_setup->FileNameOpts.PlaceFile = shell_vpr_setup_gen_one_file_name(circuit_name, - cur_out_file_prefix, - PLACE_FILE_POSTFIX); - vpr_setup->FileNameOpts.RouteFile = shell_vpr_setup_gen_one_file_name(circuit_name, - cur_out_file_prefix, - ROUTE_FILE_POSTFIX); - - vpr_setup->FileNameOpts.ActFile = get_opt_val(opts, "activity_file"); - if (NULL == vpr_setup->FileNameOpts.ActFile) { - vpr_setup->FileNameOpts.ActFile = shell_vpr_setup_gen_one_file_name(circuit_name, - cur_out_file_prefix, - ACTIVITY_FILE_POSTFIX); - } - - vpr_setup->FileNameOpts.PowerFile = shell_vpr_setup_gen_one_file_name(circuit_name, - cur_out_file_prefix, - POWER_FILE_POSTFIX); - - vpr_setup->FileNameOpts.CmosTechFile = shell_vpr_setup_gen_one_file_name(vpr_setup->FileNameOpts.ArchFile, - cur_out_file_prefix, - CMOS_TECH_FILE_POSTFIX); - - vpr_setup->FileNameOpts.SDCFile = shell_vpr_setup_gen_one_file_name(circuit_name, - cur_out_file_prefix, - SDC_FILE_POSTFIX); - - cur_default_output_name = shell_vpr_setup_gen_one_file_name(circuit_name, - cur_out_file_prefix, - NULL); - - alloc_and_load_output_file_names(cur_default_output_name); - - return; -} - -/* Setup the read_arch options, allocate data structures */ -void shell_setup_read_arch_opts(t_shell_env* env, t_opt_info* opts) { - /* Set read_xml_spice flag */ - env->arch.read_xml_spice = is_opt_set(opts, "read_xml_fpga_x2p", FALSE); - if (TRUE == env->arch.read_xml_spice) { - vpr_printf(TIO_MESSAGE_INFO, "Enable read_xml_fpga_x2p...\n"); - env->arch.spice = (t_spice*) my_calloc(1, sizeof(t_spice)); - } - - /* Set read_xml_power flag */ - if (TRUE == is_opt_set(opts, "read_xml_versa_power", FALSE)) { - env->arch.power = (t_power_arch*) my_calloc (1, sizeof(t_power_arch)); - env->arch.clocks = (t_clock_arch*) my_calloc (1, sizeof(t_clock_arch)); - g_clock_arch = env->arch.clocks; - } else { - env->arch.power = NULL; - env->arch.clocks = NULL; - g_clock_arch = NULL; - } - - return; -} - -void shell_setup_vpr_arch(t_shell_env* env, t_opt_info* opts) { - /* Setup ReadArch Options */ - shell_setup_read_arch_opts(env, opts); - - vpr_printf(TIO_MESSAGE_INFO, "Parsing XML file(%s)...\n", - env->vpr_setup.FileNameOpts.ArchFile); - XmlReadArch(env->vpr_setup.FileNameOpts.ArchFile, - env->vpr_setup.TimingEnabled, - &(env->arch), &type_descriptors, - &num_types); - - vpr_printf(TIO_MESSAGE_INFO, "Setup Architecture...\n"); - - VPRSetupArch(&(env->arch), &(env->vpr_setup.RoutingArch), - &(env->vpr_setup.Segments), &(env->vpr_setup.swseg_patterns), - &(env->vpr_setup.user_models), &(env->vpr_setup.library_models)); - - /* Build the complex block graph */ - vpr_printf(TIO_MESSAGE_INFO, "Building complex block graph.\n"); - alloc_and_load_all_pb_graphs(env->vpr_setup.PowerOpts.do_power); - - /* Xifan Tang: Initialize the clb to clb directs */ - alloc_and_init_globals_clb_to_clb_directs(env->arch.num_directs, env->arch.Directs); - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_PB_GRAPH)) { - echo_pb_graph(getEchoFileName(E_ECHO_PB_GRAPH)); - } - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_ARCH)) { - EchoArch(getEchoFileName(E_ECHO_ARCH), type_descriptors, num_types, - &(env->arch)); - } - - return; -} - -void shell_setup_vpr_timing(t_shell_env* env) { - /* Don't do anything if they don't want timing */ - if (FALSE == env->vpr_setup.TimingEnabled) { - memset(&(env->vpr_setup.Timing), 0, sizeof(t_timing_inf)); - env->vpr_setup.Timing.timing_analysis_enabled = FALSE; - return; - } - - env->vpr_setup.Timing.C_ipin_cblock = env->arch.C_ipin_cblock; - env->vpr_setup.Timing.T_ipin_cblock = env->arch.T_ipin_cblock; - env->vpr_setup.Timing.timing_analysis_enabled = env->vpr_setup.TimingEnabled; - - /* If the user specified an SDC filename on the command line, look for specified_name.sdc, otherwise look for circuit_name.sdc*/ - env->vpr_setup.Timing.SDCFile = env->vpr_setup.FileNameOpts.SDCFile; - - return; -} - -void shell_setup_graphics(t_shell_env* env, - t_opt_info* opts) { - env->vpr_setup.GraphPause = is_opt_set(opts, "auto", FALSE); -#ifdef NO_GRAPHICS - env->vpr_setup.ShowGraphics = FALSE; /* DEFAULT */ -#else /* NO_GRAPHICS */ - env->vpr_setup.ShowGraphics = (boolean)(!is_opt_set(opts, "nodisp", TRUE)); /* DEFAULT */ -#endif /* NO_GRAPHICS */ - - return; -} - -void shell_execute_vpr_setup(t_shell_env* env, - t_opt_info* opts) { - - /* Timing option priorities */ - vpr_printf(TIO_MESSAGE_INFO, "Setting up timing_analysis...\n"); - env->vpr_setup.TimingEnabled = is_opt_set(opts, "timing_analysis", TRUE); - - vpr_printf(TIO_MESSAGE_INFO, "Setting up echo file...\n"); - setEchoEnabled(is_opt_set(opts, "echo_file", FALSE)); - - vpr_printf(TIO_MESSAGE_INFO, "Setting up post-synthesis netlists...\n"); - SetPostSynthesisOption(is_opt_set(opts, "generate_postsynthesis_netlist", FALSE)); - - vpr_printf(TIO_MESSAGE_INFO, "Setting up constant net delay...\n"); - env->vpr_setup.constant_net_delay = get_opt_float_val(opts, "constant_net_delay", 0.); - - /* Set up default file names - * TODO: to be called with 'read_blif' - */ - vpr_printf(TIO_MESSAGE_INFO, "Setting up default file names...\n"); - shell_vpr_setup_default_file_names(&(env->vpr_setup), opts); - - /* TODO: to be called with 'read_arch' */ - vpr_printf(TIO_MESSAGE_INFO, "Reading Architecture...\n"); - shell_setup_vpr_arch(env, opts); - - /* VPR setup timing */ - vpr_printf(TIO_MESSAGE_INFO, "Setting up timing engine...\n"); - shell_setup_vpr_timing(env); - - /* init global variables */ - vpr_printf(TIO_MESSAGE_INFO, "Setting up some global variables...\n"); - out_file_prefix = env->vpr_setup.FileNameOpts.out_file_prefix; - grid_logic_tile_area = env->arch.grid_logic_tile_area; - ipin_mux_trans_size = env->arch.ipin_mux_trans_size; - - vpr_printf(TIO_MESSAGE_INFO, "Setting up Graphic engine...\n"); - shell_setup_graphics(env, opts); - - /* Read blif file and sweep unused components */ - vpr_printf(TIO_MESSAGE_INFO, "Reading blif...\n"); - if (TRUE == (boolean)(is_opt_set(opts, "read_xml_fpga_x2p", FALSE) || is_opt_set(opts, "read_xml_versa_power", FALSE))) { - vpr_printf(TIO_MESSAGE_INFO, "Reading activity...\n"); - } - read_and_process_blif(env->vpr_setup.FileNameOpts.BlifFile, - env->vpr_setup.PackerOpts.sweep_hanging_nets_and_inputs, - env->vpr_setup.user_models, env->vpr_setup.library_models, - /* Xifan TANG: we need activity in spice modeling */ - (boolean) (is_opt_set(opts, "read_xml_fpga_x2p", FALSE) || is_opt_set(opts, "read_xml_versa_power", FALSE)), - env->vpr_setup.FileNameOpts.ActFile); - fflush(stdout); - - - return; -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_setup.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_setup.h deleted file mode 100644 index 2ffed058a..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_vpr_setup.h +++ /dev/null @@ -1,24 +0,0 @@ -/* Command-line options for VPR setup */ -/* Add any option by following the format of t_opt_info */ -t_opt_info setup_vpr_opts[] = { - /* VPR Setup Options should be listed here */ - {"blif_file", "--blif_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_REQ, OPT_NONDEF, "Specify the blif for input benchmark"}, - {"arch_file", "--arch_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_REQ, OPT_NONDEF, "Specify the XML architecture description file for FPGA"}, - {"activity_file", "--activity_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the activity file for input benchmark in purpose of power estimation"}, - {"power_properties", "--power_properties", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the power property XML for power estimation"}, - {"timing_analysis", "--timing_analysis", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify if timing-driven and timing analysis should be enabled"}, - {"out_file_prefix", "--out_file_prefix", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the prefix of files to be "}, - {"net_file", "--net_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the netlist outputted by packers"}, - {"place_file", "--place_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the netlist outputted by placers"}, - {"route_file", "--route_file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify the netlist outputted by routers"}, - {"echo_file", "--echo_file", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify if echo files will be outputted"}, - {"generate_postsynthesis_netlist", "--generate_postsynthesis_netlist", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify if post synthesis netlists will be outputted"}, - {"constant_net_delay", "--constant_net_delay", 0, OPT_WITHVAL, OPT_FLOAT, OPT_OPT, OPT_NONDEF, "Specify if use constant net delay"}, - {"read_xml_fpga_x2p", "--read_xml_fpga_x2p", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify if read XML syntax for FPGA X2P"}, - {"read_xml_versa_power", "--read_xml_versa_power", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Specify if read XML syntax for VersaPower"}, - {HELP_OPT_TAG, HELP_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch Help Desk"}, - {LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch Help Desk"} -}; - -/* Function to execute the command */ -void shell_execute_vpr_setup(t_shell_env* env, t_opt_info* opts); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/mini_shell.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/mini_shell.c deleted file mode 100644 index 5b1d536c6..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/mini_shell.c +++ /dev/null @@ -1,156 +0,0 @@ -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" - - -/* Include SPICE support headers*/ -#include "quicksort.h" -#include "linkedlist.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_utils.h" -#include "read_opt_types.h" -#include "read_opt.h" -#include "shell_types.h" - -/* Include APIs */ -#include "vpr_api.h" -#include "fpga_x2p_api.h" -#include "cmd_vpr_setup.h" -#include "cmd_vpr_pack.h" -#include "cmd_vpr_place_and_route.h" -#include "cmd_vpr_power.h" -#include "cmd_fpga_x2p_setup.h" -#include "cmd_fpga_spice.h" -#include "cmd_fpga_verilog.h" -#include "cmd_fpga_bitstream.h" -#include "cmd_help.h" -#include "cmd_exit.h" -#include "shell_cmds.h" -#include "shell_utils.h" -#include "mini_shell.h" - -#include -#include - - -t_shell_env shell_env; - -char* vpr_shell_prefix = "VPR7-OpenFPGA> "; - - -void init_shell_env(t_shell_env* env) { - memset(&(env->vpr_setup), 0, sizeof(t_vpr_setup)); - memset(&(env->arch), 0, sizeof(t_arch)); - env->cmd = shell_cmd; - env->cmd_category = cmd_category; - - return; -} - -/* Start the interactive shell */ -void vpr_run_interactive_mode() { - - vpr_printf(TIO_MESSAGE_INFO, "Start interactive mode...\n"); - - vpr_print_title(); - - /* Initialize file handler */ - vpr_init_file_handler(); - - /* Initialize shell_env */ - init_shell_env(&shell_env); - - while (1) { - char * line = readline(vpr_shell_prefix); - process_shell_command(line, &shell_env); - /* Add to history */ - add_history(line); - free (line); - } - - return; -} - -void vpr_run_script_mode(char* script_file_name) { - FILE* fp = NULL; - char buffer[BUFSIZE]; - char str_end = '\0'; - int i; - - vpr_print_title(); - - /* Initialize file handler */ - vpr_init_file_handler(); - - /* Initialize shell_env */ - init_shell_env(&shell_env); - - vpr_printf(TIO_MESSAGE_INFO, "Reading script file %s!\n", script_file_name); - - /* Read the file */ - fp = fopen(script_file_name, "r"); - /* Error out if the File handle is empty */ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "Fail to open the script file: %s.\n", - script_file_name); - exit(1); - } - - /* Read line by line */ - while (NULL != my_fgets(buffer, BUFSIZE, fp)) { - if ((0 == strlen(buffer)) - || (0 == my_strcmp(buffer, ""))) { - continue; - } - /* Chomp the \n of buffer */ - for (i = 0; i < strlen(buffer); i++) { - if ('\n' == buffer[i]) { - buffer[i] = str_end; - } - } - /* Treat each valid line as a command */ - process_shell_command(buffer, &shell_env); - } - - /* Close file */ - fclose(fp); - - return; -} - -void run_shell(int argc, char ** argv) { - - /* Parse the options and decide which interface to go */ - read_options(argc, argv, shell_opts); - - /* Interface 1: run through -i, --interactive - * Or with 0 arguments, we start the interactive shell - */ - if ( (1 == argc) - || (TRUE == is_opt_set(shell_opts, "i", FALSE)) ) { - vpr_run_interactive_mode(); - } else if (TRUE == is_opt_set(shell_opts, "f", FALSE)) { - /* Interface 2: run through -f, --file */ - char* script_file_name = get_opt_val(shell_opts, "f"); - vpr_run_script_mode(script_file_name); - } else { - vpr_printf(TIO_MESSAGE_ERROR, "Invalid command! Launch Help desk:\n"); - print_opt_info_help_desk(shell_opts); - } - - return; -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/mini_shell.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/mini_shell.h deleted file mode 100644 index 0b965e3a4..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/mini_shell.h +++ /dev/null @@ -1,8 +0,0 @@ - -t_opt_info shell_opts[] = { - {"f", "-f,--file", 0, OPT_WITHVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch program with a script file"}, - {"i", "-i,--interactive", 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch program in an interactive mode"}, - {HELP_OPT_TAG, HELP_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"}, - {LAST_OPT_TAG, LAST_OPT_NAME, 0, OPT_NONVAL, OPT_CHAR, OPT_OPT, OPT_NONDEF, "Launch help desk"} -}; - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt.c deleted file mode 100644 index 0fa02abeb..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt.c +++ /dev/null @@ -1,309 +0,0 @@ -#include -#include -#include -#include -#include "util.h" -#include "read_opt_types.h" -#include "read_opt.h" - -/* External function */ -void my_free(void* ptr); -char** fpga_spice_strtok(char* str, - char* delims, - int* len); -int my_strcmp(char* str1, char* str2); - - -/** - * Read the integer in option list - * Do simple check and convert it from char to - * integer - */ -int process_int_arg(INP char* arg) { - /*Check if the pointor of arg is NULL */ - if (NULL == arg) { - vpr_printf(TIO_MESSAGE_ERROR, - "Error: Arg is NULL when processing integer!\n"); - exit(1); - } - - return atoi(arg); -} - -/** - * Read the float in option list - * Do simple check and convert it from char to - * float - */ -float process_float_arg(INP char* arg) { - /*Check if the pointor of arg is NULL */ - if (NULL == arg) { - vpr_printf(TIO_MESSAGE_ERROR, - "Error: Arg is NULL when processing float!\n"); - exit(1); - } - - return atof(arg); -} - -/** - * Process the argument by comparing - * Store the options in struct - */ -boolean process_arg_opt(INP char** argv, - INOUTP int* iarg, - INP char* curarg, - t_opt_info* cur) { - int itok = 0; - int num_tokens = 0; - char** token = NULL; - - while (0 != my_strcmp(LAST_OPT_TAG, cur->tag)) { - /* Tokenize the opt_name*/ - token = fpga_spice_strtok(cur->name, ",", &num_tokens); - /*Process Match Arguments*/ - for (itok = 0; itok < num_tokens; itok++) { - if (0 == my_strcmp(curarg, token[itok])) { - /* Check the defined flag if yes, return with error! */ - if (OPT_DEF == cur->opt_def) { - vpr_printf(TIO_MESSAGE_ERROR, - "Intend to redefine the option(%s) with (%s)!\n", - cur->name, token[itok]); - return FALSE; - } - cur->opt_def = OPT_DEF; - /*A value is stored in next argument*/ - if (OPT_WITHVAL == cur->with_val) { - *(iarg) += 1; - cur->val = my_strdup((argv[*iarg])); - return TRUE; - } else if (OPT_NONVAL == cur->with_val) { - /*Do not need next argument, return*/ - return TRUE; - } else { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s, [LINE%d]) Unknown type of Option with_Val! Abort.\n", - __FILE__, __LINE__); - return FALSE; - } - } - } - cur++; - /* Free */ - for (itok = 0; itok < num_tokens; itok++) { - my_free(token[itok]); - } - my_free(token); - } - - return FALSE; -} - -char* convert_option_mandatory_to_str(enum opt_manda cur) { - switch (cur) { - case OPT_REQ: - return "Required"; - case OPT_OPT: - return "Optional"; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s, [LINE%d]) Unknown type of Option Mandatory! Abort.\n", - __FILE__, __LINE__); - return NULL; - } -} - -void print_opt_info_help_desk(t_opt_info* cur_opt_info) { - int max_str_len = -1; - t_opt_info* cur = cur_opt_info; - char* str_fixed_len = NULL; - char* name_tag = "Option Names"; - char str_end = '\0'; - - /* Get the maximum string length of options - * We can align to the longest string when outputing the help desk - */ - while (0 != my_strcmp(LAST_OPT_TAG, cur->tag)) { - if ( (-1 == max_str_len) - || (max_str_len < strlen(cur->name)) ) { - max_str_len = strlen(cur->name) + 1; - } - cur++; - } - /* Minimum size is 5 */ - if (max_str_len < strlen(name_tag) + 1) { - max_str_len = strlen(name_tag) + 1; - } - /* Malloc */ - str_fixed_len = (char*)my_calloc(max_str_len, sizeof(char)); - - vpr_printf(TIO_MESSAGE_INFO, "Help Desk:\n"); - memset(str_fixed_len, ' ', max_str_len); - strcpy(str_fixed_len, name_tag); - str_fixed_len[strlen(name_tag)] = ' '; - str_fixed_len[max_str_len] = str_end; - vpr_printf(TIO_MESSAGE_INFO, "%s Status Description\n", str_fixed_len); - cur = cur_opt_info; - while (0 != my_strcmp(LAST_OPT_TAG, cur->tag)) { - memset(str_fixed_len, ' ', max_str_len); - strcpy(str_fixed_len, cur->name); - str_fixed_len[strlen(cur->name)] = ' '; - str_fixed_len[max_str_len] = str_end; - vpr_printf(TIO_MESSAGE_INFO, "%s ", str_fixed_len); - vpr_printf(TIO_MESSAGE_INFO, "%s ", convert_option_mandatory_to_str(cur->mandatory)); - vpr_printf(TIO_MESSAGE_INFO, "%s", cur->description); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - cur++; - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - /* Free */ - my_free(str_fixed_len); - - return; -} - - -boolean read_options(INP int argc, - INP char **argv, - INOUTP t_opt_info* cur_opt_info) { - int iarg; - char* curarg = NULL; - boolean arg_processed = FALSE; - t_opt_info* cur = cur_opt_info; - - - vpr_printf(TIO_MESSAGE_INFO, - "Processing Options...\n"); - - /*Start from argv[1], the 1st argv is programme name*/ - for (iarg = 1; iarg < argc;) { - curarg = argv[iarg]; - /*Process the option start with hyphone*/ - if (0 == strncmp("-", curarg, 1)) { - arg_processed = process_arg_opt(argv, &iarg, curarg, cur_opt_info); - if (FALSE == arg_processed) { - vpr_printf(TIO_MESSAGE_WARNING, - "Warning: Unknown Option(%s) detected!\n", - curarg); - print_opt_info_help_desk(cur_opt_info); - return FALSE; - } - iarg += 1; /*Move on to the next argument*/ - } else { - iarg++; - } - } - - /* Search the command help */ - if (TRUE == is_opt_set(cur_opt_info, LAST_OPT_TAG, FALSE)) { - print_opt_info_help_desk(cur_opt_info); - return FALSE; - } - - /* Check if REQUIRED options are processed */ - while (0 != my_strcmp(LAST_OPT_TAG, cur->tag)) { - if ( (NULL == cur->val) - && (OPT_REQ == cur->mandatory)) { - vpr_printf(TIO_MESSAGE_WARNING, - "Warning: Required Option(%s) is missing!\n", - cur->name); - print_opt_info_help_desk(cur_opt_info); - return FALSE; - } - cur++; - } - - /* Confirm options */ - /* - show_opt_list(cur_opt_info); - */ - - return TRUE; -} - - -/** - * Show the options in opt_list after process. - * Only for debug use - */ -int show_opt_list(t_opt_info* cur) { - - vpr_printf(TIO_MESSAGE_INFO, - "List Options:\n"); - while (0 != my_strcmp(LAST_OPT_TAG, cur->tag)) { - vpr_printf(TIO_MESSAGE_INFO, - "Name=%s, Value=%s.\n", - cur->name, cur->val); - cur++; - } - - return 1; -} - -boolean is_opt_set(t_opt_info* opts, char* opt_name, boolean default_val) { - while (0 != my_strcmp(LAST_OPT_TAG, opts->tag)) { - if ( 0 != my_strcmp(opts->tag, opt_name)) { - opts++; - continue; - } - if (OPT_DEF == opts->opt_def) { - return TRUE; - } else { - return default_val; - } - opts++; - } - - return default_val; -} - -char* get_opt_val(t_opt_info* opts, char* opt_name) { - while (0 != my_strcmp(LAST_OPT_TAG, opts->tag)) { - if ( 0 != my_strcmp(opts->tag, opt_name)) { - opts++; - continue; - } - if (OPT_WITHVAL != opts->with_val) { - vpr_printf(TIO_MESSAGE_INFO, - "Try to get the val of an option(%s) which is defined to be without_val!\n", - opt_name); - } - if (NULL == opts->val) { - return NULL; - } else { - return my_strdup(opts->val); - } - opts++; - } - - return NULL; -} - -int get_opt_int_val(t_opt_info* opts, char* opt_name, int default_val) { - char* temp = get_opt_val(opts, opt_name); - int ret = default_val; - - if (NULL != temp) { - ret = process_int_arg(temp); - } - /* Free */ - my_free(temp); - - return ret; -} - -float get_opt_float_val(t_opt_info* opts, char* opt_name, float default_val) { - char* temp = get_opt_val(opts, opt_name); - float ret = default_val; - - if (NULL != temp) { - ret = process_float_arg(temp); - } - /* Free */ - my_free(temp); - - return ret; -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt.h deleted file mode 100644 index 97a33e918..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt.h +++ /dev/null @@ -1,25 +0,0 @@ -/*Subroutines in read_opts.c*/ -boolean read_options(INP int argc, - INP char ** argv, - t_opt_info* cur); - -void print_opt_info_help_desk(t_opt_info* cur_opt_info); - -boolean process_arg_opt(INP char** argv, - INOUTP int* iarg, - INP char* curarg, - t_opt_info* cur); - -int show_opt_list(t_opt_info* cur); - -int process_int_arg(INP char* arg); - -float process_float_arg(INP char* arg); - -boolean is_opt_set(t_opt_info* opts, char* opt_name, boolean default_val); - -char* get_opt_val(t_opt_info* opts, char* opt_name); - -int get_opt_int_val(t_opt_info* opts, char* opt_name, int default_val); - -float get_opt_float_val(t_opt_info* opts, char* opt_name, float default_val); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt_types.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt_types.h deleted file mode 100644 index 2909ff43d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/read_opt_types.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * Filename : Options.h - * Author : Xifan TANG, EPFL - * Description : Header file contains structs and enumeration - * types for option reading purpose. - */ - -/*Determine whether it is a mandatory option*/ -enum opt_manda { - OPT_REQ, - OPT_OPT -}; - -/*The option has been appeared in the command line */ -enum opt_default { - OPT_DEF, - OPT_NONDEF -}; - -/*Determine whether the option contains a value*/ -enum opt_with_val { - OPT_NONVAL, - OPT_WITHVAL -}; - -/*Determine the date type of value*/ -enum opt_val_type { - OPT_INT, - OPT_FLOAT, - OPT_CHAR, - OPT_DOUBLE -}; - -/*Basic struct stores option information*/ -typedef struct s_opt_info t_opt_info; -struct s_opt_info { - char* tag; /* tag of option */ - char* name; /*The name of option*/ - char* val; /*The value*/ - enum opt_with_val with_val; - enum opt_val_type val_type; - enum opt_manda mandatory; - enum opt_default opt_def; - char* description; -}; - -typedef struct s_cmd_info t_cmd_info; -struct s_cmd_info { - char* name; - t_opt_info opts[]; -}; - -#define HELP_OPT_TAG "help" -#define HELP_OPT_NAME "-h,--help" - -#define LAST_OPT_TAG NULL -#define LAST_OPT_NAME NULL - -/* Return flag */ -#define SHELL_SUCCESS 0 -#define SHELL_FAIL 1 -#define SHELL_ERROR 2 - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_api.h deleted file mode 100644 index 70c659083..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_api.h +++ /dev/null @@ -1,2 +0,0 @@ - -void run_shell(int argc, char ** argv); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_cmds.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_cmds.h deleted file mode 100644 index 00980fcaa..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_cmds.h +++ /dev/null @@ -1,27 +0,0 @@ -/* Commands available in the shell */ -t_shell_cmd shell_cmd[] = { - {"vpr_setup", SETUP_CMD, setup_vpr_opts, &shell_execute_vpr_setup }, - {"vpr_pack", PACK_CMD, vpr_pack_opts, &shell_execute_vpr_pack }, - {"vpr_place_and_route", PLACE_CMD, vpr_place_and_route_opts, &shell_execute_vpr_place_and_route }, - {"vpr_versapower", ANALYSIS_CMD, vpr_versapower_opts, &shell_execute_vpr_versapower }, - {"fpga_x2p_setup", SETUP_CMD, fpga_x2p_setup_opts, &shell_execute_fpga_x2p_setup }, - {"fpga_spice", PRODUCTION_CMD, fpga_spice_opts, &shell_execute_fpga_spice }, - {"fpga_verilog", PRODUCTION_CMD, fpga_verilog_opts, &shell_execute_fpga_verilog }, - {"fpga_bitstream", PRODUCTION_CMD, fpga_bitstream_opts, &shell_execute_fpga_bitstream }, - {"help", BASIC_CMD, help_opts, &shell_execute_help }, - {"exit", BASIC_CMD, exit_opts, &shell_execute_exit }, - {"quit", BASIC_CMD, exit_opts, &shell_execute_exit }, - {LAST_CMD_NAME, BASIC_CMD, NULL, NULL} -}; - -/* Command category */ -t_cmd_category cmd_category[] = { - {BASIC_CMD, "Basic Commands"}, - {SETUP_CMD, "Commands to Setup Engines"}, - {PACK_CMD, "Packing Engines"}, - {PLACE_CMD, "Placement Engines"}, - {ROUTE_CMD, "Routing Engines"}, - {ANALYSIS_CMD, "Analysis Commands"}, - {PRODUCTION_CMD, "Production Commmands"}, - {LAST_CMD_CATEGORY, "END"} -}; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_file_postfix.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_file_postfix.h deleted file mode 100644 index ef41348f1..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_file_postfix.h +++ /dev/null @@ -1,9 +0,0 @@ -#define BLIF_FILE_POSTFIX ".blif" -#define NET_FILE_POSTFIX ".net" -#define PLACE_FILE_POSTFIX ".place" -#define ROUTE_FILE_POSTFIX ".route" -#define ACTIVITY_FILE_POSTFIX ".act" -#define POWER_FILE_POSTFIX ".power" -#define CMOS_TECH_FILE_POSTFIX ".xml" -#define SDC_FILE_POSTFIX ".sdc" - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h deleted file mode 100644 index da984faf5..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h +++ /dev/null @@ -1,59 +0,0 @@ -#ifndef SHELL_TYPES_H -#define SHELL_TYPES_H - -#include -#include "vtr_geometry.h" -#include "vpr_types.h" -#include "mux_library.h" -#include "rr_blocks.h" -#include "module_manager.h" -#include "bitstream_manager.h" - -typedef struct s_cmd_category t_cmd_category; -typedef struct s_shell_cmd t_shell_cmd; -typedef struct s_shell_env t_shell_env; - -enum e_cmd_category { - BASIC_CMD, - SETUP_CMD, - PACK_CMD, - PLACE_CMD, - ROUTE_CMD, - ANALYSIS_CMD, - PRODUCTION_CMD, - LAST_CMD_CATEGORY -}; - -struct s_cmd_category { - e_cmd_category name; - char* label; -}; - - -struct s_shell_cmd { - char* name; - e_cmd_category category; - t_opt_info* opts; - void (*execute)(t_shell_env*, t_opt_info*); -}; - -struct s_shell_env { - ModuleManager module_manager; - BitstreamManager bitstream_manager; - std::vector fabric_bitstream; - MuxLibrary mux_lib; - std::vector logical_blocks; - vtr::Point device_size; - std::vector> grids; - std::vector blocks; - DeviceRRGSB device_rr_gsb; - t_sram_orgz_info sram_orgz_info; - t_arch arch; - t_vpr_setup vpr_setup; - t_shell_cmd* cmd; - t_cmd_category* cmd_category; -}; - -#define LAST_CMD_NAME NULL - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_utils.c deleted file mode 100644 index c1dfe566e..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_utils.c +++ /dev/null @@ -1,119 +0,0 @@ -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" - - -/* Include SPICE support headers*/ -#include "quicksort.h" -#include "linkedlist.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_utils.h" -#include "read_opt_types.h" -#include "read_opt.h" -#include "shell_types.h" - -/* Include APIs */ - -#include -#include - -int my_strcmp(char* str1, char* str2) { - if ((NULL == str1) && (NULL == str2)) { - return 0; - } else if ((NULL == str1) || (NULL == str2)) { - return 1; - } else { - return strcmp(str1, str2); - } -} - -void shell_print_usage(t_shell_env* env) { - t_cmd_category* cur_category = env->cmd_category; - - /* Output usage by command categories */ - while (LAST_CMD_CATEGORY != cur_category->name) { - vpr_printf(TIO_MESSAGE_INFO, - "%s:\n", cur_category->label); - t_shell_cmd* cur_cmd = env->cmd; - int cnt = 0; - while (0 != my_strcmp(LAST_CMD_NAME, cur_cmd->name)) { - if (cur_category->name != cur_cmd->category) { - /* Go to next command*/ - cur_cmd++; - continue; - } - /* Print command name */ - vpr_printf(TIO_MESSAGE_INFO, - "%s", - cur_cmd->name); - cnt++; - if (4 == cnt) { - vpr_printf(TIO_MESSAGE_INFO, "\n"); - cnt = 0; - } else { - vpr_printf(TIO_MESSAGE_INFO, "\t"); - } - /* Go to next command*/ - cur_cmd++; - } - vpr_printf(TIO_MESSAGE_INFO, "\n\n"); - /* Go to next */ - cur_category++; - } - - return; -} - -/* Identify the command to launch */ -void process_shell_command(char* line, t_shell_env* env) { - int itok; - int num_tokens = 0; - char** token = NULL; - t_shell_cmd* cur_cmd = env->cmd; - - /* Tokenize the line */ - token = fpga_spice_strtok(line, " ", &num_tokens); - - /* Search the shell command list and execute */ - while (0 != my_strcmp(LAST_CMD_NAME, cur_cmd->name)) { - if (0 == my_strcmp(cur_cmd->name, token[0])) { - /* Read options of read_blif */ - if (FALSE == read_options(num_tokens, token, cur_cmd->opts)) { - return; - } - /* Execute setup_vpr engine*/ - cur_cmd->execute(env, cur_cmd->opts); - /* Return here */ - return; - } - /* Go to next command*/ - cur_cmd++; - } - - /* Invalid command */ - vpr_printf(TIO_MESSAGE_INFO, - "Invalid command!\n"); - shell_print_usage(env); - - /* Free */ - for (itok = 0; itok < num_tokens; itok++) { - my_free(token[itok]); - } - my_free(token); - - return; -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_utils.h deleted file mode 100644 index fbc00c57f..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_utils.h +++ /dev/null @@ -1,6 +0,0 @@ - -int my_strcmp(char* str1, char* str2); - -void shell_print_usage(t_shell_env* env); - -void process_shell_command(char* line, t_shell_env* env); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_api.c deleted file mode 100644 index 0bf2ae089..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_api.c +++ /dev/null @@ -1,446 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "path_delay.h" -#include "stats.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "read_xml_spice_util.h" -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_backannotate_utils.h" -#include "fpga_x2p_globals.h" -#include "fpga_bitstream.h" - - -/* Include SPICE generator headers */ -#include "spice_globals.h" -#include "spice_subckt.h" -#include "spice_pbtypes.h" -#include "spice_heads.h" -#include "spice_lut.h" -#include "spice_top_netlist.h" -#include "spice_mux_testbench.h" -#include "spice_grid_testbench.h" -#include "spice_routing_testbench.h" -#include "spice_primitive_testbench.h" -#include "spice_run_scripts.h" - -/* For mrFPGA */ -#ifdef MRFPGA_H -#include "mrfpga_globals.h" -#endif - -/* RUN HSPICE Shell Script Name */ -static char* default_spice_dir_path = "spice_netlists/"; -static char* spice_top_tb_dir_name = "top_tb/"; -static char* spice_grid_tb_dir_name = "grid_tb/"; -static char* spice_pb_mux_tb_dir_name = "pb_mux_tb/"; -static char* spice_cb_mux_tb_dir_name = "cb_mux_tb/"; -static char* spice_sb_mux_tb_dir_name = "sb_mux_tb/"; -static char* spice_cb_tb_dir_name = "cb_tb/"; -static char* spice_sb_tb_dir_name = "sb_tb/"; -static char* spice_lut_tb_dir_name = "lut_tb/"; -static char* spice_hardlogic_tb_dir_name = "hardlogic_tb/"; -static char* spice_io_tb_dir_name = "io_tb/"; - -/***** Subroutines Declarations *****/ -static -void init_list_include_netlists(t_spice* spice); - -static -void free_spice_tb_llist(); - -/***** Subroutines *****/ - -static -void init_list_include_netlists(t_spice* spice) { - int i, j, cur; - int to_include = 0; - int num_to_include = 0; - - /* Initialize */ - for (i = 0; i < spice->num_include_netlist; i++) { - FreeSpiceModelNetlist(&(spice->include_netlists[i])); - } - my_free(spice->include_netlists); - spice->include_netlists = NULL; - spice->num_include_netlist = 0; - - /* Generate include netlist list */ - vpr_printf(TIO_MESSAGE_INFO, "Listing SPICE Netlist Names to be included...\n"); - for (i = 0; i < spice->num_spice_model; i++) { - if (NULL != spice->spice_models[i].model_netlist) { - /* Check if this netlist name has already existed in the list */ - to_include = 1; - for (j = 0; j < i; j++) { - if (NULL == spice->spice_models[j].model_netlist) { - continue; - } - if (0 == strcmp(spice->spice_models[j].model_netlist, spice->spice_models[i].model_netlist)) { - to_include = 0; - break; - } - } - /* Increamental */ - if (1 == to_include) { - num_to_include++; - } - } - } - - /* realloc */ - spice->include_netlists = (t_spice_model_netlist*)my_realloc(spice->include_netlists, - sizeof(t_spice_model_netlist)*(num_to_include + spice->num_include_netlist)); - - /* Fill the new included netlists */ - cur = spice->num_include_netlist; - for (i = 0; i < spice->num_spice_model; i++) { - if (NULL != spice->spice_models[i].model_netlist) { - /* Check if this netlist name has already existed in the list */ - to_include = 1; - for (j = 0; j < i; j++) { - if (NULL == spice->spice_models[j].model_netlist) { - continue; - } - if (0 == strcmp(spice->spice_models[j].model_netlist, spice->spice_models[i].model_netlist)) { - to_include = 0; - break; - } - } - /* Increamental */ - if (1 == to_include) { - spice->include_netlists[cur].path = my_strdup(spice->spice_models[i].model_netlist); - spice->include_netlists[cur].included = 0; - vpr_printf(TIO_MESSAGE_INFO, "[%d] %s\n", cur+1, spice->include_netlists[cur].path); - cur++; - } - } - } - /* Check */ - assert(cur == (num_to_include + spice->num_include_netlist)); - /* Update */ - spice->num_include_netlist += num_to_include; - - return; -} - - -static -void free_spice_tb_llist() { - t_llist* temp = tb_head; - - while (temp) { - my_free(((t_spicetb_info*)(temp->dptr))->tb_name); - my_free(temp->dptr); - temp->dptr = NULL; - temp = temp->next; - } - free_llist(tb_head); - - return; -} - -/***** Main Function *****/ -void vpr_fpga_spice(t_vpr_setup vpr_setup, - t_arch Arch, - char* circuit_name) { - clock_t t_start; - clock_t t_end; - float run_time_sec; - - int num_clocks = Arch.spice->spice_params.stimulate_params.num_clocks; - int vpr_crit_path_delay = Arch.spice->spice_params.stimulate_params.vpr_crit_path_delay; - - char* spice_dir_formatted = NULL; - char* include_dir_path = NULL; - char* subckt_dir_path = NULL; - char* top_netlist_path = NULL; - char* include_dir_name = vpr_setup.FPGA_SPICE_Opts.SpiceOpts.include_dir; - char* subckt_dir_name = vpr_setup.FPGA_SPICE_Opts.SpiceOpts.subckt_dir; - char* chomped_circuit_name = NULL; - char* chomped_spice_dir = NULL; - char* top_testbench_dir_path = NULL; - char* pb_mux_testbench_dir_path = NULL; - char* cb_mux_testbench_dir_path = NULL; - char* sb_mux_testbench_dir_path = NULL; - char* cb_testbench_dir_path = NULL; - char* sb_testbench_dir_path = NULL; - char* grid_testbench_dir_path = NULL; - char* lut_testbench_dir_path = NULL; - char* hardlogic_testbench_dir_path = NULL; - char* io_testbench_dir_path = NULL; - char* top_testbench_file = NULL; - char* bitstream_file_name = NULL; - char* bitstream_file_path = NULL; - - /* Check if the routing architecture we support*/ - if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { - vpr_printf(TIO_MESSAGE_ERROR, "FPGA SPICE netlists only support uni-directional routing architecture!\n"); - exit(1); - } - - /* We don't support mrFPGA */ -#ifdef MRFPGA_H - if (is_mrFPGA) { - vpr_printf(TIO_MESSAGE_ERROR, "FPGA SPICE netlists do not support mrFPGA!\n"); - exit(1); - } -#endif - - /* assign the global variable of SRAM model */ - assert(NULL != Arch.sram_inf.spice_sram_inf_orgz); /* Check !*/ - sram_spice_model = Arch.sram_inf.spice_sram_inf_orgz->spice_model; - sram_spice_orgz_type = Arch.sram_inf.spice_sram_inf_orgz->type; - /* initialize the SRAM organization information struct */ - sram_spice_orgz_info = alloc_one_sram_orgz_info(); - init_sram_orgz_info(sram_spice_orgz_info, sram_spice_orgz_type, sram_spice_model, nx + 2, ny + 2); - /* Report error: SPICE part only support standalone SRAMs */ - if (SPICE_SRAM_STANDALONE != sram_spice_orgz_info->type) { - vpr_printf(TIO_MESSAGE_ERROR, "Currently FPGA SPICE netlist only support standalone SRAM organization!\n"); - exit(1); - } - /* Check all the SRAM port is using the correct SRAM SPICE MODEL */ - config_spice_models_sram_port_spice_model(Arch.spice->num_spice_model, - Arch.spice->spice_models, - Arch.sram_inf.spice_sram_inf_orgz->spice_model); - - /* Assign global variables of input and output pads */ - iopad_spice_model = find_iopad_spice_model(Arch.spice->num_spice_model, Arch.spice->spice_models); - assert(NULL != iopad_spice_model); - - /* Initial Arch SPICE MODELS*/ - /* zero the counter of each spice_model */ - zero_spice_models_cnt(Arch.spice->num_spice_model, Arch.spice->spice_models); - - /* Move to the top-level function: vpr_fpga_spice_tool_suits */ - /* init_check_arch_spice_models(&Arch, &vpr_setup.RoutingArch); */ - init_list_include_netlists(Arch.spice); - - /* Initialize the number of configuration bits of all the grids */ - init_grids_num_conf_bits(sram_spice_orgz_info); - init_grids_num_iopads(); - - /* Add keyword checking */ - /* Move to the top-level function: vpr_fpga_spice_tool_suits */ - /* check_keywords_conflict(Arch); */ - - /*Process the circuit name*/ - split_path_prog_name(circuit_name,'/',&chomped_spice_dir ,&chomped_circuit_name); - - /* Update the global variable : - * the number of mutli-thread used in SPICE simulator */ - spice_sim_multi_thread_num = vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_sim_multi_thread_num; - - /* FPGA-SPICE formally starts*/ - vpr_printf(TIO_MESSAGE_INFO, "\nFPGA-SPICE starts...\n"); - - /* Start Clocking*/ - t_start = clock(); - - /* Format the directory path */ - if (NULL != vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_dir) { - spice_dir_formatted = format_dir_path(vpr_setup.FPGA_SPICE_Opts.SpiceOpts.spice_dir); - } else { - spice_dir_formatted = format_dir_path(my_strcat(format_dir_path(chomped_spice_dir), - default_spice_dir_path)); - } - - /*Initial directory organization*/ - /* Process include directory */ - (include_dir_path) = my_strcat(spice_dir_formatted,include_dir_name); - /* Process subckt directory */ - (subckt_dir_path) = my_strcat(spice_dir_formatted,subckt_dir_name); - - /* Check the spice folders exists if not we create it.*/ - create_dir_path(spice_dir_formatted); - create_dir_path(include_dir_path); - create_dir_path(subckt_dir_path); - - /* Generate Header files */ - spice_print_headers(include_dir_path, vpr_crit_path_delay, num_clocks, *(Arch.spice)); - - /* Generate sub circuits: Inverter, Buffer, Transmission Gate, LUT, DFF, SRAM, MUX*/ - generate_spice_subckts(subckt_dir_path, &Arch ,&vpr_setup.RoutingArch, vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); - - /* Print MUX testbench if needed */ - if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_pb_mux_testbench) { - pb_mux_testbench_dir_path = my_strcat(spice_dir_formatted, spice_pb_mux_tb_dir_name); - create_dir_path(pb_mux_testbench_dir_path); - spice_print_mux_testbench(pb_mux_testbench_dir_path, chomped_circuit_name, - include_dir_path, subckt_dir_path, - rr_node_indices, num_clocks, Arch, - SPICE_PB_MUX_TB, - vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); - /* Free */ - my_free(pb_mux_testbench_dir_path); - } - - if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_cb_mux_testbench) { - cb_mux_testbench_dir_path = my_strcat(spice_dir_formatted, spice_cb_mux_tb_dir_name); - create_dir_path(cb_mux_testbench_dir_path); - spice_print_mux_testbench(cb_mux_testbench_dir_path, chomped_circuit_name, - include_dir_path, subckt_dir_path, - rr_node_indices, num_clocks, Arch, SPICE_CB_MUX_TB, - vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); - /* Free */ - my_free(cb_mux_testbench_dir_path); - } - - if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_sb_mux_testbench) { - sb_mux_testbench_dir_path = my_strcat(spice_dir_formatted, spice_sb_mux_tb_dir_name); - create_dir_path(sb_mux_testbench_dir_path); - spice_print_mux_testbench(sb_mux_testbench_dir_path, chomped_circuit_name, - include_dir_path, subckt_dir_path, - rr_node_indices, num_clocks, Arch, SPICE_SB_MUX_TB, - vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); - /* Free */ - my_free(sb_mux_testbench_dir_path); - } - - if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_cb_testbench) { - cb_testbench_dir_path = my_strcat(spice_dir_formatted, spice_cb_tb_dir_name); - create_dir_path(cb_testbench_dir_path); - spice_print_cb_testbench(cb_testbench_dir_path, chomped_circuit_name, - include_dir_path, subckt_dir_path, - rr_node_indices, num_clocks, Arch, - vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); - /* Free */ - my_free(cb_testbench_dir_path); - } - - if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_sb_testbench) { - sb_testbench_dir_path = my_strcat(spice_dir_formatted, spice_sb_tb_dir_name); - create_dir_path(sb_testbench_dir_path); - spice_print_sb_testbench(sb_testbench_dir_path, chomped_circuit_name, - include_dir_path, subckt_dir_path, - rr_node_indices, num_clocks, Arch, - vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); - /* Free */ - my_free(sb_testbench_dir_path); - } - - if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_lut_testbench) { - lut_testbench_dir_path = my_strcat(spice_dir_formatted, spice_lut_tb_dir_name); - create_dir_path(lut_testbench_dir_path); - spice_print_primitive_testbench(lut_testbench_dir_path, - chomped_circuit_name, include_dir_path, subckt_dir_path, - rr_node_indices, num_clocks, Arch, - SPICE_LUT_TB, - vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); - /* Free */ - my_free(lut_testbench_dir_path); - } - - /* Print hardlogic testbench file if needed */ - if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_hardlogic_testbench) { - hardlogic_testbench_dir_path = my_strcat(spice_dir_formatted, spice_hardlogic_tb_dir_name); - create_dir_path(hardlogic_testbench_dir_path); - spice_print_primitive_testbench(hardlogic_testbench_dir_path, - chomped_circuit_name, include_dir_path, subckt_dir_path, - rr_node_indices, num_clocks, Arch, - SPICE_HARDLOGIC_TB, - vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); - /* Free */ - my_free(hardlogic_testbench_dir_path); - } - - /* Print IO testbench file if needed */ - if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_io_testbench) { - io_testbench_dir_path = my_strcat(spice_dir_formatted, spice_io_tb_dir_name); - create_dir_path(io_testbench_dir_path); - spice_print_primitive_testbench(io_testbench_dir_path, - chomped_circuit_name, include_dir_path, subckt_dir_path, - rr_node_indices, num_clocks, Arch, - SPICE_IO_TB, - vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); - /* Free */ - my_free(io_testbench_dir_path); - } - - - /* Print Grid testbench if needed */ - if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_grid_testbench) { - grid_testbench_dir_path = my_strcat(spice_dir_formatted, spice_grid_tb_dir_name); - create_dir_path(grid_testbench_dir_path); - spice_print_grid_testbench(grid_testbench_dir_path, chomped_circuit_name, - include_dir_path, subckt_dir_path, - rr_node_indices, num_clocks, Arch, - vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); - /* Free */ - my_free(grid_testbench_dir_path); - } - - /* Print Netlists of the given FPGA*/ - if (vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_print_top_testbench) { - top_testbench_file = my_strcat(chomped_circuit_name, spice_top_testbench_postfix); - /* Process top_netlist_path */ - top_testbench_dir_path = my_strcat(spice_dir_formatted, spice_top_tb_dir_name); - create_dir_path(top_testbench_dir_path); - top_netlist_path = my_strcat(top_testbench_dir_path, top_testbench_file); - spice_print_top_netlist(chomped_circuit_name, top_netlist_path, - include_dir_path, subckt_dir_path, - num_rr_nodes, rr_node, rr_node_indices, num_clocks, *(Arch.spice), - vpr_setup.FPGA_SPICE_Opts.SpiceOpts.fpga_spice_leakage_only); - /* Free */ - my_free(top_testbench_dir_path); - my_free(top_testbench_file); - my_free(top_netlist_path); - } - - if (vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream) { - if (NULL == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.bitstream_output_file) { - bitstream_file_name = my_strcat(chomped_circuit_name, fpga_spice_bitstream_output_file_postfix); - bitstream_file_path = my_strcat(spice_dir_formatted, bitstream_file_name); - } else { - bitstream_file_path = my_strdup(vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.bitstream_output_file); - } - /* Dump bitstream file */ - dump_fpga_spice_bitstream(bitstream_file_path, chomped_circuit_name, sram_spice_orgz_info); - /* Free */ - my_free(bitstream_file_name); - my_free(bitstream_file_path); - } - - /* Generate a shell script for running HSPICE simulations */ - fprint_run_hspice_shell_script(*(Arch.spice), vpr_setup.FPGA_SPICE_Opts.SpiceOpts.simulator_path, - spice_dir_formatted, subckt_dir_path); - - /* END Clocking*/ - t_end = clock(); - - run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, "SPICE netlists dumping took %g seconds\n", run_time_sec); - - /* Free sram_orgz_info */ - free_sram_orgz_info(sram_spice_orgz_info, - sram_spice_orgz_info->type); - /* Free tb_llist */ - free_spice_tb_llist(); - /* Free */ - my_free(spice_dir_formatted); - my_free(include_dir_path); - my_free(subckt_dir_path); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_api.h deleted file mode 100644 index 13a29bf57..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_api.h +++ /dev/null @@ -1,3 +0,0 @@ -void vpr_fpga_spice(t_vpr_setup vpr_setup, - t_arch Arch, - char* circuit_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_globals.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_globals.c deleted file mode 100644 index 48a9b2ce1..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_globals.c +++ /dev/null @@ -1,123 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -/* Include SPICE support headers*/ -#include -#include "spice_types.h" -#include "linkedlist.h" -#include "fpga_x2p_globals.h" -#include "spice_globals.h" - -/* Threshold of max transistor width for each transistor */ -float max_width_per_trans = 5.; - -char* spice_netlist_file_postfix = ".sp"; - -char* nmos_subckt_name = "vpr_nmos"; -char* pmos_subckt_name = "vpr_pmos"; -char* io_nmos_subckt_name = "vpr_io_nmos"; -char* io_pmos_subckt_name = "vpr_io_pmos"; -char* cpt_subckt_name = "cpt"; -char* mux_basis_posfix = "_basis"; -char* mux_special_basis_posfix = "_special_basis"; -char* nmos_pmos_spice_file_name = "nmos_pmos.sp"; -char* basics_spice_file_name = "inv_buf_trans_gate.sp"; -char* muxes_spice_file_name = "muxes.sp"; -char* rram_veriloga_file_name = "rram_behavior.va"; -char* wires_spice_file_name = "wires.sp"; -char* logic_block_spice_file_name = "grid_header.sp"; -char* luts_spice_file_name = "luts.sp"; -char* routing_spice_file_name = "routing_header.sp"; -char* meas_header_file_name = "meas_params.sp"; -char* stimu_header_file_name = "stimulate_params.sp"; -char* design_param_header_file_name = "design_params.sp"; - -/* Prefix for subckt SPICE netlists */ -char* grid_spice_file_name_prefix = "grid_"; -char* chanx_spice_file_name_prefix = "chanx_"; -char* chany_spice_file_name_prefix = "chany_"; -char* sb_spice_file_name_prefix = "sb_"; -char* cbx_spice_file_name_prefix = "cbx_"; -char* cby_spice_file_name_prefix = "cby_"; - -/* Postfix for circuit design parameters */ -char* design_param_postfix_input_buf_size = "_input_buf_size"; -char* design_param_postfix_output_buf_size = "_output_buf_size"; -char* design_param_postfix_pass_gate_logic_pmos_size = "_pgl_pmos_size"; -char* design_param_postfix_pass_gate_logic_nmos_size = "_pgl_nmos_size"; -char* design_param_postfix_wire_param_res_val = "_wire_param_res_val"; -char* design_param_postfix_wire_param_cap_val = "_wire_param_cap_val"; -char* design_param_postfix_rram_ron = "_rram_ron"; -char* design_param_postfix_rram_roff = "_rram_roff"; -char* design_param_postfix_rram_wprog_set_pmos = "_rram_wprog_set_pmos"; -char* design_param_postfix_rram_wprog_set_nmos = "_rram_wprog_set_nmos"; -char* design_param_postfix_rram_wprog_reset_pmos = "_rram_wprog_reset_pmos"; -char* design_param_postfix_rram_wprog_reset_nmos = "_rram_wprog_reset_nmos"; - -/* Testbench names */ -char* spice_top_testbench_postfix = "_top.sp"; -char* spice_grid_testbench_postfix = "_grid_testbench.sp"; -char* spice_pb_mux_testbench_postfix = "_pbmux_testbench.sp"; -char* spice_cb_mux_testbench_postfix = "_cbmux_testbench.sp"; -char* spice_sb_mux_testbench_postfix = "_sbmux_testbench.sp"; -char* spice_cb_testbench_postfix = "_cb_testbench.sp"; -char* spice_sb_testbench_postfix = "_sb_testbench.sp"; -char* spice_lut_testbench_postfix = "_lut_testbench.sp"; -char* spice_dff_testbench_postfix = "_dff_testbench.sp"; -char* spice_hardlogic_testbench_postfix = "_hardlogic_testbench.sp"; -char* spice_io_testbench_postfix = "_io_testbench.sp"; - -/* SRAM SPICE MODEL should be set as global*/ -t_spice_model* sram_spice_model = NULL; -enum e_sram_orgz sram_spice_orgz_type = SPICE_SRAM_STANDALONE; -t_sram_orgz_info* sram_spice_orgz_info = NULL; - -/* Input and Output Pad spice model. should be set as global */ -t_spice_model* iopad_spice_model = NULL; - -/* Global counters */ -int rram_design_tech = 0; -int num_used_grid_mux_tb = 0; -int num_used_grid_tb = 0; -int num_used_cb_tb = 0; -int num_used_sb_tb = 0; -int num_used_cb_mux_tb = 0; -int num_used_sb_mux_tb = 0; -int num_used_lut_tb = 0; -int num_used_hardlogic_tb = 0; -int num_used_io_tb = 0; - -/* linked-list for all the testbenches */ -t_llist* tb_head = NULL; - -/* Linked-list that stores submodule Verilog file mames */ -t_llist* grid_spice_subckt_file_path_head = NULL; -t_llist* routing_spice_subckt_file_path_head = NULL; - -/* linked-list for heads of scan-chain */ -t_llist* scan_chain_heads = NULL; - -/* Name of global ports used in all netlists */ -char* spice_tb_global_vdd_port_name = "gvdd"; -char* spice_tb_global_gnd_port_name = "ggnd"; -char* spice_tb_global_config_done_port_name = "gconfig_done"; -char* spice_tb_global_set_port_name = "gset"; -char* spice_tb_global_reset_port_name = "greset"; -char* spice_tb_global_vdd_localrouting_port_name = "gvdd_local_interc"; -char* spice_tb_global_vdd_direct_port_name = "gvdd_direct_interc"; -char* spice_tb_global_vdd_io_port_name = "gvdd_io"; -char* spice_tb_global_vdd_hardlogic_port_name = "gvdd_hardlogic"; -char* spice_tb_global_vdd_sram_port_name = "gvdd_sram"; -char* spice_tb_global_vdd_lut_sram_port_name = "gvdd_sram_luts"; -char* spice_tb_global_vdd_localrouting_sram_port_name = "gvdd_sram_local_routing"; -char* spice_tb_global_vdd_io_sram_port_name = "gvdd_sram_io"; -char* spice_tb_global_vdd_hardlogic_sram_port_name = "gvdd_sram_hardlogic"; -char* spice_tb_global_vdd_cb_sram_port_name = "gvdd_sram_cbs"; -char* spice_tb_global_vdd_sb_sram_port_name = "gvdd_sram_sbs"; -char* spice_tb_global_clock_port_name = "gclock"; -char* spice_tb_global_vdd_load_port_name = "gvdd_load"; -char* spice_tb_global_port_inv_postfix = "_inv"; - -int spice_sim_multi_thread_num = 8; - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_globals.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_globals.h deleted file mode 100644 index 2b303e7fb..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_globals.h +++ /dev/null @@ -1,121 +0,0 @@ -/* global parameters for SPICE support*/ -extern float max_width_per_trans; - -extern char* spice_netlist_file_postfix; - -extern char* nmos_subckt_name; -extern char* pmos_subckt_name; -extern char* io_nmos_subckt_name; -extern char* io_pmos_subckt_name; -extern char* cpt_subckt_name; -extern char* rram_veriloga_file_name; -extern char* mux_basis_posfix; -extern char* mux_special_basis_posfix; -extern char* nmos_pmos_spice_file_name; -extern char* basics_spice_file_name; -extern char* muxes_spice_file_name; -extern char* wires_spice_file_name; -extern char* logic_block_spice_file_name; -extern char* luts_spice_file_name; -extern char* routing_spice_file_name; -extern char* meas_header_file_name; -extern char* stimu_header_file_name; -extern char* design_param_header_file_name; - -/* Prefix for subckt SPICE netlists */ -extern char* grid_spice_file_name_prefix; -extern char* chanx_spice_file_name_prefix; -extern char* chany_spice_file_name_prefix; -extern char* sb_spice_file_name_prefix; -extern char* cbx_spice_file_name_prefix; -extern char* cby_spice_file_name_prefix; - -/* Postfix for circuit design parameters */ -extern char* design_param_postfix_input_buf_size; -extern char* design_param_postfix_output_buf_size; -extern char* design_param_postfix_pass_gate_logic_pmos_size; -extern char* design_param_postfix_pass_gate_logic_nmos_size; -extern char* design_param_postfix_wire_param_res_val; -extern char* design_param_postfix_wire_param_cap_val; -extern char* design_param_postfix_rram_ron; -extern char* design_param_postfix_rram_roff; -extern char* design_param_postfix_rram_wprog_set_pmos; -extern char* design_param_postfix_rram_wprog_set_nmos; -extern char* design_param_postfix_rram_wprog_reset_pmos; -extern char* design_param_postfix_rram_wprog_reset_nmos; - -/* Testbench names */ -extern char* spice_top_testbench_postfix; -extern char* spice_grid_testbench_postfix; -extern char* spice_pb_mux_testbench_postfix; -extern char* spice_cb_mux_testbench_postfix; -extern char* spice_sb_mux_testbench_postfix; -extern char* spice_cb_testbench_postfix; -extern char* spice_sb_testbench_postfix; -extern char* spice_lut_testbench_postfix; -extern char* spice_dff_testbench_postfix; -extern char* spice_hardlogic_testbench_postfix; -extern char* spice_io_testbench_postfix; -/* RUN HSPICE Shell Script Name */ -/* -extern char* run_hspice_shell_script_name; -extern char* default_spice_dir_path; -extern char* sim_results_dir_name; -extern char* spice_top_tb_dir_name; -extern char* spice_grid_tb_dir_name; -extern char* spice_pb_mux_tb_dir_name; -extern char* spice_cb_mux_tb_dir_name; -extern char* spice_sb_mux_tb_dir_name; -extern char* spice_lut_tb_dir_name; -extern char* spice_dff_tb_dir_name; -*/ - -extern t_spice_model* sram_spice_model; -extern enum e_sram_orgz sram_spice_orgz_type; -extern t_sram_orgz_info* sram_spice_orgz_info; - -extern t_spice_model* iopad_spice_model; - -extern int rram_design_tech; -extern int num_used_grid_mux_tb; -extern int num_used_cb_mux_tb; -extern int num_used_sb_mux_tb; -extern int num_used_grid_tb; -extern int num_used_cb_tb; -extern int num_used_sb_tb; -extern int num_used_lut_tb; -extern int num_used_hardlogic_tb; -extern int num_used_io_tb; - -/* linked-list for all the testbenches */ -extern t_llist* tb_head; - -/* Linked-list that stores submodule Verilog file mames */ -extern t_llist* grid_spice_subckt_file_path_head; -extern t_llist* routing_spice_subckt_file_path_head; - -/* Heads of scan-chain */ -extern t_llist* scan_chain_heads; - -/* Name of global ports used in all netlists */ -extern char* spice_tb_global_vdd_port_name; -extern char* spice_tb_global_gnd_port_name; -extern char* spice_tb_global_config_done_port_name; -extern char* spice_tb_global_set_port_name; -extern char* spice_tb_global_reset_port_name; -extern char* spice_tb_global_vdd_localrouting_port_name; -extern char* spice_tb_global_vdd_direct_port_name; -extern char* spice_tb_global_vdd_io_port_name; -extern char* spice_tb_global_vdd_hardlogic_port_name; -extern char* spice_tb_global_vdd_sram_port_name; -extern char* spice_tb_global_vdd_lut_sram_port_name; -extern char* spice_tb_global_vdd_localrouting_sram_port_name; -extern char* spice_tb_global_vdd_io_sram_port_name; -extern char* spice_tb_global_vdd_hardlogic_sram_port_name; -extern char* spice_tb_global_vdd_cb_sram_port_name; -extern char* spice_tb_global_vdd_sb_sram_port_name; -extern char* spice_tb_global_clock_port_name; -extern char* spice_tb_global_vdd_load_port_name; -extern char* spice_tb_global_port_inv_postfix; - -extern int spice_sim_multi_thread_num; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_grid_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_grid_testbench.c deleted file mode 100644 index 108e62efe..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_grid_testbench.c +++ /dev/null @@ -1,567 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_types.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "spice_utils.h" -#include "spice_pbtypes.h" -#include "spice_subckt.h" -#include "spice_grid_testbench.h" - -/* Global variable inside this C-source file*/ -/* -static int num_inv_load = 0; -static int num_noninv_load = 0; -static int num_grid_load = 0; -*/ -static int testbench_load_cnt = 0; -static int tb_num_grid = 0; -static int max_sim_num_clock_cycles = 2; -static int upbound_sim_num_clock_cycles = 2; -static int auto_select_max_sim_num_clock_cycles = TRUE; - -/* Local subroutines only accessible in this C-source file */ -static -void init_spice_grid_testbench_globals(t_spice spice) { - testbench_load_cnt = 0; - tb_num_grid = 0; - auto_select_max_sim_num_clock_cycles = spice.spice_params.meas_params.auto_select_sim_num_clk_cycle; - upbound_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; - if (FALSE == auto_select_max_sim_num_clock_cycles) { - max_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; - } else { - max_sim_num_clock_cycles = 2; - } -} - -/* Subroutines in this source file*/ -static -void fprint_spice_grid_testbench_global_ports(FILE* fp, int x, int y, - int num_clock, - t_spice spice) { - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* Print generic global ports*/ - fprint_spice_generic_testbench_global_ports(fp, - sram_spice_orgz_info, - global_ports_head); - - fprintf(fp, ".global %s %s %s\n", - spice_tb_global_vdd_localrouting_port_name, - spice_tb_global_vdd_io_port_name, - spice_tb_global_vdd_hardlogic_port_name); - - /* Print the VDD ports of SRAM belonging to other SPICE module */ - fprintf(fp, ".global %s\n", - spice_tb_global_vdd_localrouting_sram_port_name); - fprintf(fp, ".global %s\n", - spice_tb_global_vdd_lut_sram_port_name); - fprintf(fp, ".global %s\n", - spice_tb_global_vdd_io_sram_port_name); - - /*Global Vdds for LUTs*/ - fprint_grid_global_vdds_spice_model(fp, x, y, SPICE_MODEL_LUT, spice); - - /*Global Vdds for FFs*/ - fprint_grid_global_vdds_spice_model(fp, x, y, SPICE_MODEL_FF, spice); - - /*Global Vdds for IOPADs*/ - fprint_grid_global_vdds_spice_model(fp, x, y, SPICE_MODEL_IOPAD, spice); - - /*Global Vdds for Hardlogics*/ - fprint_grid_global_vdds_spice_model(fp, x, y, SPICE_MODEL_HARDLOGIC, spice); - - return; -} - -void fprint_spice_grid_testbench_call_defined_core_grids(FILE* fp) { - int ix, iy; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Normal Grids */ - for (ix = 1; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - assert(IO_TYPE != grid[ix][iy].type); - fprintf(fp, "Xgrid[%d][%d] ", ix, iy); - fprint_grid_pins(fp, ix, iy, 1); - fprintf(fp, "gvdd 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ - } - } - - return; -} - -void fprint_spice_grid_testbench_call_one_defined_grid(FILE* fp, int ix, int iy) { - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* if ((NULL == grid[ix][iy].type)||(0 != grid[ix][iy].offset)||(0 == grid[ix][iy].usage)) { */ - if ((NULL == grid[ix][iy].type) - ||(EMPTY_TYPE == grid[ix][iy].type) - ||(0 != grid[ix][iy].offset)) { - return; - } - - if (IO_TYPE == grid[ix][iy].type) { - fprintf(fp, "Xgrid[%d][%d] \n", ix, iy); - fprint_io_grid_pins(fp, ix, iy, 1); - fprintf(fp, "+ gvdd 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ - tb_num_grid++; - } else { - fprintf(fp, "Xgrid[%d][%d] \n", ix, iy); - fprint_grid_pins(fp, ix, iy, 1); - fprintf(fp, "+ gvdd 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ - tb_num_grid++; - } - - return; -} - -int get_grid_testbench_one_grid_num_sim_clock_cycles(FILE* fp, - t_spice spice, - t_ivec*** LL_rr_node_indices, - int x, int y) { - int ipin, class_id, side, iheight; - t_type_ptr type = NULL; - int ipin_rr_node_index; - float ipin_density = 0.; - float average_density = 0.; - int avg_density_cnt = 0; - int num_sim_clock_cycles = 0; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - type = grid[x][y].type; - assert(NULL != type); - - average_density = 0.; - avg_density_cnt = 0; - /* For each input pin, we give a stimulate*/ - for (side = 0; side < 4; side++) { - for (iheight = 0; iheight < type->height; iheight++) { - for (ipin = 0; ipin < type->num_pins; ipin++) { - if (1 == type->pinloc[iheight][side][ipin]) { - class_id = type->pin_class[ipin]; - if (RECEIVER == type->class_inf[class_id].type) { - /* Print a voltage source according to density and probability */ - ipin_rr_node_index = get_rr_node_index(x, y, IPIN, ipin, LL_rr_node_indices); - /* Get density and probability */ - ipin_density = get_rr_node_net_density(rr_node[ipin_rr_node_index]); - if (0. < ipin_density) { - average_density += ipin_density; - avg_density_cnt++; - } - } - } - } - } - } - - /* Calculate the num_sim_clock_cycle for this MUX, update global max_sim_clock_cycle in this testbench */ - if (0 < avg_density_cnt) { - average_density = average_density/avg_density_cnt; - } else { - assert(0 == avg_density_cnt); - average_density = 0.; - } - if (TRUE == auto_select_max_sim_num_clock_cycles) { - if (0. == average_density) { - num_sim_clock_cycles = 2; - } else { - assert(0. < average_density); - num_sim_clock_cycles = (int)(1/average_density) + 1; - } - /* for idle blocks, 2 clock cycle is well enough... */ - if (2 < num_sim_clock_cycles) { - num_sim_clock_cycles = upbound_sim_num_clock_cycles; - } else { - num_sim_clock_cycles = 2; - } - if (max_sim_num_clock_cycles < num_sim_clock_cycles) { - max_sim_num_clock_cycles = num_sim_clock_cycles; - } - } else { - num_sim_clock_cycles = max_sim_num_clock_cycles; - } - - return num_sim_clock_cycles; -} - - -void fprint_grid_testbench_one_grid_stimulation(FILE* fp, - t_spice spice, - t_ivec*** LL_rr_node_indices, - int x, int y) { - int ipin, class_id, side, iheight; - t_type_ptr type = NULL; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - type = grid[x][y].type; - assert(NULL != type); - - /* For each input pin, we give a stimulate*/ - for (side = 0; side < 4; side++) { - for (iheight = 0; iheight < type->height; iheight++) { - for (ipin = 0; ipin < type->num_pins; ipin++) { - if (1 == type->pinloc[iheight][side][ipin]) { - class_id = type->pin_class[ipin]; - if (RECEIVER == type->class_inf[class_id].type) { - fprint_spice_testbench_one_grid_pin_stimulation(fp, x, y, iheight, side, ipin, LL_rr_node_indices); - } else if (DRIVER == type->class_inf[class_id].type) { - if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ - fprint_spice_testbench_one_grid_pin_loads(fp, x, y, iheight, side, ipin, &testbench_load_cnt, LL_rr_node_indices); - } - } else { - fprint_stimulate_dangling_one_grid_pin(fp, x, y, iheight, side, ipin, LL_rr_node_indices); - } - } - } - } - } - - return; -} - -static -void fprint_spice_grid_testbench_stimulations(FILE* fp, - int num_clock, - t_spice spice, - int grid_x, int grid_y, - t_ivec*** LL_rr_node_indices) { - /* int ix, iy; */ - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Print generic stimuli */ - fprint_spice_testbench_generic_global_ports_stimuli(fp, num_clock); - - /* Generate global ports stimuli */ - fprint_spice_testbench_global_ports_stimuli(fp, global_ports_head); - - /* SRAM ports */ - /* Every SRAM inputs should have a voltage source */ - fprintf(fp, "***** Global Inputs for SRAMs *****\n"); - fprint_spice_testbench_global_sram_inport_stimuli(fp, sram_spice_orgz_info); - - fprintf(fp, "***** Global VDD for SRAMs *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_sram_port_name, - "vsp"); - - /* Global routing Vdds */ - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_localrouting_port_name, - "vsp"); - - /* Global Vdds for SRAMs */ - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_lut_sram_port_name, - "vsp"); - - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_localrouting_sram_port_name, - "vsp"); - - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_io_sram_port_name, - "vsp"); - - fprintf(fp, "***** Global VDD for load inverters *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_load_port_name, - "vsp"); - - /* Every Hardlogic use an independent Voltage source */ - fprintf(fp, "***** Global VDD for Hard Logics *****\n"); - fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, spice); - - /* Every LUT use an independent Voltage source */ - fprintf(fp, "***** Global VDD for Look-Up Tables (LUTs) *****\n"); - fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y,SPICE_MODEL_LUT, spice); - - /* Every FF use an independent Voltage source */ - fprintf(fp, "***** Global VDD for Flip-flops (FFs) *****\n"); - fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, spice); - - /* For each grid input port, we generate the voltage pulses */ - fprint_grid_testbench_one_grid_stimulation(fp, spice, LL_rr_node_indices, - grid_x, grid_y); - - return; -} - -static -void fprint_spice_grid_testbench_measurements(FILE* fp, int grid_x, int grid_y, - t_spice spice, - boolean leakage_only) { - /* First cycle reserved for measuring leakage */ - int num_clock_cycle = max_sim_num_clock_cycles; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - fprint_spice_netlist_transient_setting(fp, spice, num_clock_cycle, leakage_only); - fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); - - /* TODO: Measure the delay of each mapped net and logical block */ - - /* Measure the power */ - /* Leakage ( the first cycle is reserved for leakage measurement) */ - if (TRUE == leakage_only) { - /* Leakage power of SRAMs */ - fprintf(fp, ".measure tran leakage_power_sram_local_routing find p(Vgvdd_sram_local_routing) at=0\n"); - fprintf(fp, ".measure tran leakage_power_sram_luts find p(Vgvdd_sram_luts) at=0\n"); - /* Global power of Local Interconnections*/ - fprintf(fp, ".measure tran leakage_power_local_routing find p(Vgvdd_local_interc) at=0\n"); - } else { - /* Leakage power of SRAMs */ - fprintf(fp, ".measure tran leakage_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from=0 to='clock_period'\n"); - fprintf(fp, ".measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period'\n"); - /* Global power of Local Interconnections*/ - fprintf(fp, ".measure tran leakage_power_local_routing avg p(Vgvdd_local_interc) from=0 to='clock_period'\n"); - } - /* Leakge power of Hard logic */ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); - /* Leakage power of LUTs*/ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_LUT, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); - /* Leakage power of FFs*/ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); - - if (TRUE == leakage_only) { - return; - } - - /* Dynamic power */ - /* Dynamic power of SRAMs */ - fprintf(fp, ".measure tran dynamic_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); - fprintf(fp, ".measure tran total_energy_per_cycle_sram_local_routing param='dynamic_power_sram_local_routing*clock_period'\n"); - fprintf(fp, ".measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); - fprintf(fp, ".measure tran total_energy_per_cycle_sram_luts param='dynamic_power_sram_luts*clock_period'\n"); - /* Dynamic power of Local Interconnections */ - fprintf(fp, ".measure tran dynamic_power_local_interc avg p(Vgvdd_local_interc) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); - fprintf(fp, ".measure tran total_energy_per_cycle_local_routing param='dynamic_power_local_interc*clock_period'\n"); - /* Dynamic power of Hard Logic */ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); - /* Dynamic power of LUTs */ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_LUT, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); - /* Dynamic power of FFs */ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); - - return; -} - -/* Top-level function in this source file */ -int fprint_spice_one_grid_testbench(char* formatted_spice_dir, - char* circuit_name, - char* grid_test_bench_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clock, - t_arch arch, - int grid_x, int grid_y, - boolean leakage_only) { - FILE* fp = NULL; - char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); - char* temp_include_file_path = NULL; - char* title = my_strcat("FPGA Grid Testbench for Design: ", circuit_name); - char* grid_testbench_file_path = my_strcat(formatted_spice_dir, grid_test_bench_name); - int used = 0; - - /* Check if the path exists*/ - fp = fopen(grid_testbench_file_path,"w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create Grid Testbench SPICE netlist %s!",__FILE__, __LINE__, grid_testbench_file_path); - exit(1); - } - - - /* Print the title */ - fprint_spice_head(fp, title); - my_free(title); - - /* print technology library and design parameters*/ - /* fprint_tech_lib(fp, arch.spice->tech_lib); */ - - /* Include parameter header files */ - fprint_spice_include_param_headers(fp, include_dir_path); - - /* Include Key subckts */ - fprint_spice_include_key_subckts(fp, subckt_dir_path); - - /* Include user-defined sub-circuit netlist */ - init_include_user_defined_netlists(*(arch.spice)); - fprint_include_user_defined_netlists(fp, *(arch.spice)); - - /* Special subckts for Top-level SPICE netlist */ - fprintf(fp, "****** Include subckt netlists: Look-Up Tables (LUTs) *****\n"); - spice_print_one_include_subckt_line(fp, formatted_subckt_dir_path, luts_spice_file_name); - - /* Generate filename */ - fprintf(fp, "****** Include subckt netlists: Grid[%d][%d] *****\n", - grid_x, grid_y); - temp_include_file_path = fpga_spice_create_one_subckt_filename(grid_spice_file_name_prefix, grid_x, grid_y, spice_netlist_file_postfix); - /* Check if we include an existing file! */ - if (FALSE == check_subckt_file_exist_in_llist(grid_spice_subckt_file_path_head, - my_strcat(formatted_subckt_dir_path, temp_include_file_path))) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Intend to include a non-existed SPICE netlist %s!\n", - __FILE__, __LINE__, temp_include_file_path); - exit(1); - } - spice_print_one_include_subckt_line(fp, formatted_subckt_dir_path, temp_include_file_path); - - /* Print simulation temperature and other options for SPICE */ - fprint_spice_options(fp, arch.spice->spice_params); - - /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ - fprint_spice_grid_testbench_global_ports(fp, grid_x, grid_y, num_clock, (*arch.spice)); - - /* Quote defined Logic blocks subckts (Grids) */ - init_spice_grid_testbench_globals(*(arch.spice)); - - fprint_spice_grid_testbench_call_one_defined_grid(fp, grid_x, grid_y); - - /* Back-anotate activity information to each routing resource node - * (We should have activity of each Grid port) - */ - - /* Add stimulations */ - max_sim_num_clock_cycles = get_grid_testbench_one_grid_num_sim_clock_cycles(fp, (*arch.spice), LL_rr_node_indices, grid_x, grid_y); - fprint_spice_grid_testbench_stimulations(fp, num_clock, (*arch.spice), grid_x, grid_y, LL_rr_node_indices); - - /* Add measurements */ - fprint_spice_grid_testbench_measurements(fp, grid_x, grid_y, (*arch.spice), leakage_only); - - /* SPICE ends*/ - fprintf(fp, ".end\n"); - - /* Close the file*/ - fclose(fp); - - if (0 < tb_num_grid) { - /* - vpr_printf(TIO_MESSAGE_INFO, "Writing Grid[%d][%d] Testbench for %s...\n", grid_x, grid_y, circuit_name); - */ - /* Push the testbench to the linked list */ - tb_head = add_one_spice_tb_info_to_llist(tb_head, grid_testbench_file_path, - max_sim_num_clock_cycles); - used = 1; - } else { - my_remove_file(grid_testbench_file_path); - used = 0; - } - - return used; -} - - -/* Top-level function in this source file */ -void spice_print_grid_testbench(char* formatted_spice_dir, - char* circuit_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clock, - t_arch arch, - boolean leakage_only) { - char* grid_testbench_name = NULL; - char* temp_include_file_path = NULL; - int ix, iy; - int cnt = 0; - int used; - - vpr_printf(TIO_MESSAGE_INFO,"Generating grid testbench...\n"); - - for (ix = 1; ix < (nx+1); ix++) { - for (iy = 1; iy < (ny+1); iy++) { - /* Check if we include an existing subckt file! */ - temp_include_file_path = fpga_spice_create_one_subckt_filename(grid_spice_file_name_prefix, ix, iy, spice_netlist_file_postfix); - if (FALSE == check_subckt_file_exist_in_llist(grid_spice_subckt_file_path_head, - my_strcat(subckt_dir_path, temp_include_file_path))) { - /* free */ - my_free(temp_include_file_path); - continue; - } - /* Create a testbench for the existing subckt */ - grid_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) - + 6 + strlen(my_itoa(ix)) + 1 - + strlen(my_itoa(iy)) + 1 - + strlen(spice_grid_testbench_postfix) + 1 )); - sprintf(grid_testbench_name, "%s_grid%d_%d%s", - circuit_name, ix, iy, spice_grid_testbench_postfix); - used = fprint_spice_one_grid_testbench(formatted_spice_dir, circuit_name, grid_testbench_name, - include_dir_path, subckt_dir_path, LL_rr_node_indices, - num_clock, arch, ix, iy, - leakage_only); - if (1 == used) { - cnt += used; - } - /* free */ - my_free(grid_testbench_name); - my_free(temp_include_file_path); - } - } - /* Update the global counter */ - num_used_grid_tb = cnt; - vpr_printf(TIO_MESSAGE_INFO,"No. of generated grid testbench = %d\n", num_used_grid_tb); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_grid_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_grid_testbench.h deleted file mode 100644 index e3702e564..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_grid_testbench.h +++ /dev/null @@ -1,9 +0,0 @@ - -void spice_print_grid_testbench(char* formatted_spice_dir, - char* circuit_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clock, - t_arch arch, - boolean leakage_only); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_heads.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_heads.c deleted file mode 100644 index c6301f85b..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_heads.c +++ /dev/null @@ -1,272 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_types.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "spice_utils.h" -#include "spice_mux.h" -#include "spice_pbtypes.h" -#include "spice_subckt.h" - -/* For mrFPGA */ -#ifdef MRFPGA_H -#include "mrfpga_globals.h" -#endif - -/***** Subroutines Declarations *****/ -static -void fprint_spice_meas_header(char* meas_file_name, - t_spice_meas_params spice_meas_params); - -static -void fprint_spice_stimulate_header(char* stimulate_file_name, - t_spice_stimulate_params spice_stimulate_params, - float vpr_clock_period, - int num_clock); - -/***** Subroutines *****/ -/* Print SPICE Netlists header*/ -/* Print parameters for measurements */ -static -void fprint_spice_meas_header(char* meas_file_name, - t_spice_meas_params spice_meas_params) { - FILE* fp = NULL; - - /* Check */ - assert(NULL != meas_file_name); - - /* Create File */ - fp = fopen(meas_file_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Failure in create measure header file %s!\n", - __FILE__, __LINE__, meas_file_name); - exit(1); - } - - /* Print parameters */ - fprint_spice_head(fp, "Parameters for measurement"); - fprintf(fp, "***** Parameters For Slew Measurement *****\n"); - fprintf(fp, "***** Rising Edge *****\n"); - fprintf(fp, ".param slew_upper_thres_pct_rise=%g\n", spice_meas_params.slew_upper_thres_pct_rise); - fprintf(fp, ".param slew_lower_thres_pct_rise=%g\n", spice_meas_params.slew_lower_thres_pct_rise); - fprintf(fp, "***** Falling Edge *****\n"); - fprintf(fp, ".param slew_upper_thres_pct_fall=%g\n", spice_meas_params.slew_upper_thres_pct_fall); - fprintf(fp, ".param slew_lower_thres_pct_fall=%g\n", spice_meas_params.slew_lower_thres_pct_fall); - - fprintf(fp, "***** Parameters For Delay Measurement *****\n"); - fprintf(fp, "***** Rising Edge *****\n"); - fprintf(fp, ".param input_thres_pct_rise=%g\n", spice_meas_params.input_thres_pct_rise); - fprintf(fp, ".param output_thres_pct_rise=%g\n", spice_meas_params.output_thres_pct_rise); - fprintf(fp, "***** Falling Edge *****\n"); - fprintf(fp, ".param input_thres_pct_fall=%g\n", spice_meas_params.input_thres_pct_fall); - fprintf(fp, ".param output_thres_pct_fall=%g\n", spice_meas_params.output_thres_pct_fall); - - /* Close File */ - fclose(fp); - - return; -} - -/* Print parameters for measurements */ -static -void fprint_spice_stimulate_header(char* stimulate_file_name, - t_spice_stimulate_params spice_stimulate_params, - float vpr_clock_period, - int num_clock) { - FILE* fp = NULL; - float sim_clock_freq = 0.; - float sim_clock_period = 0.; - - /* Check */ - assert(NULL != stimulate_file_name); - - /* Create File */ - fp = fopen(stimulate_file_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Failure in create stimulate header file %s!\n", - __FILE__, __LINE__, stimulate_file_name); - exit(1); - } - - fprint_spice_head(fp, "Parameters for Stimulations"); - - /* if estimated clock frequency from VPR is 0. - * this is a combinational circuit, clock frequency will never be used - */ - /* if the clock frequency is not specified in architecture file, - * We define the clock frequency with estimated value and slack - */ - fprintf(fp, "***** Frequency *****\n"); - sim_clock_freq = spice_stimulate_params.op_clock_freq; - /* Simulate clock frequency should be larger than 0 !*/ - assert(0. < sim_clock_freq); /*TODO: check this earlier!!! */ - /* vpr_printf(TIO_MESSAGE_INFO, "Use Clock freqency %.2f [MHz] in SPICE simulation.\n", sim_clock_freq/1e6); */ - fprintf(fp, ".param clock_period=%g\n", 1. / sim_clock_freq); - sim_clock_period = 1./sim_clock_freq; - - /* Print parameters */ - fprintf(fp, "***** Parameters For Input Stimulations *****\n"); - switch (spice_stimulate_params.input_slew_rise_type) { - case SPICE_ABS: - if (sim_clock_period < (spice_stimulate_params.input_slew_rise_time - + spice_stimulate_params.input_slew_fall_time)) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid input_slew_rise_time(%.2g), should be smaller than clock period(%.2g)!\n", - __FILE__, __LINE__, spice_stimulate_params.input_slew_rise_time, sim_clock_period); - exit(1); - } - fprintf(fp, ".param input_slew_pct_rise='%g/clock_period'\n", spice_stimulate_params.input_slew_rise_time); - break; - case SPICE_FRAC: - fprintf(fp, ".param input_slew_pct_rise='%g'\n", spice_stimulate_params.input_slew_rise_time); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid input_slew_rise_type!\n", - __FILE__, __LINE__); - exit(1); - } - - switch (spice_stimulate_params.input_slew_fall_type) { - case SPICE_ABS: - if (sim_clock_period < (spice_stimulate_params.input_slew_rise_time - + spice_stimulate_params.input_slew_fall_time)) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid input_slew_fall_time(%.2g), should be smaller than clock period(%.2g)!\n", - __FILE__, __LINE__, spice_stimulate_params.input_slew_fall_time, sim_clock_period); - exit(1); - } - fprintf(fp, ".param input_slew_pct_fall='%g/clock_period'\n", spice_stimulate_params.input_slew_fall_time); - break; - case SPICE_FRAC: - fprintf(fp, ".param input_slew_pct_fall='%g'\n", spice_stimulate_params.input_slew_fall_time); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid input_slew_fall_type!\n", - __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "***** Parameters For Clock Stimulations *****\n"); - fprintf(fp, "***** Slew *****\n"); - - switch (spice_stimulate_params.clock_slew_rise_type) { - case SPICE_ABS: - if (sim_clock_period < (spice_stimulate_params.clock_slew_rise_time - + spice_stimulate_params.clock_slew_fall_time)) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid clock_slew_rise_time(%.2g)+clock_slew_fall_time(%.2g), should be smaller than clock period(%.2g)!\n", - __FILE__, __LINE__, spice_stimulate_params.clock_slew_rise_time,spice_stimulate_params.clock_slew_fall_time, sim_clock_period); - exit(1); - } - fprintf(fp, ".param clock_slew_pct_rise='%g/clock_period'\n", spice_stimulate_params.clock_slew_rise_time); - break; - case SPICE_FRAC: - fprintf(fp, ".param clock_slew_pct_rise='%g'\n", spice_stimulate_params.clock_slew_rise_time); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid clock_slew_rise_type!\n", - __FILE__, __LINE__); - exit(1); - } - - switch (spice_stimulate_params.clock_slew_fall_type) { - case SPICE_ABS: - if (sim_clock_period < (spice_stimulate_params.clock_slew_rise_time - + spice_stimulate_params.clock_slew_fall_time)) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid clock_slew_rise_time(%.2g)+clock_slew_fall_time(%.2g), should be smaller than clock period(%.2g)!\n", - __FILE__, __LINE__, spice_stimulate_params.clock_slew_rise_time,spice_stimulate_params.clock_slew_fall_time, sim_clock_period); - exit(1); - } - fprintf(fp, ".param clock_slew_pct_fall='%g/clock_period'\n", spice_stimulate_params.clock_slew_fall_time); - break; - case SPICE_FRAC: - fprintf(fp, ".param clock_slew_pct_fall='%g'\n", spice_stimulate_params.clock_slew_fall_time); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid input_slew_fall_type!\n", - __FILE__, __LINE__); - exit(1); - } - - fclose(fp); - - return; -} - -/* Print parameters for circuit designs */ -static -void fprint_spice_design_param_header(char* design_param_file_name, - t_spice spice) { - FILE* fp = NULL; - - /* Check */ - assert(NULL != design_param_file_name); - - /* Create File */ - fp = fopen(design_param_file_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Failure in create design parameter header file %s!\n", - __FILE__, __LINE__, design_param_file_name); - exit(1); - } - - fprint_spice_head(fp, "Parameters for Circuit Designs"); - - fprint_tech_lib(fp, - spice.spice_params.mc_params.cmos_variation, - spice.tech_lib); - - /* For transistors */ - fprint_spice_circuit_param(fp, - spice.spice_params.mc_params, - spice.num_spice_model, - spice.spice_models); - - fclose(fp); - - return; -} - - -void spice_print_headers(char* include_dir_path, - float vpr_clock_period, - int num_clock, - t_spice spice) { - char* formatted_include_dir_path = format_dir_path(include_dir_path); - char* meas_header_file_path = NULL; - char* stimu_header_file_path = NULL; - char* design_param_header_file_path = NULL; - - /* measurement header file */ - meas_header_file_path = my_strcat(formatted_include_dir_path, meas_header_file_name); - fprint_spice_meas_header(meas_header_file_path, spice.spice_params.meas_params); - - /* stimulate header file */ - stimu_header_file_path = my_strcat(formatted_include_dir_path, stimu_header_file_name); - fprint_spice_stimulate_header(stimu_header_file_path, spice.spice_params.stimulate_params, vpr_clock_period, num_clock); - - /* design parameter header file */ - design_param_header_file_path = my_strcat(formatted_include_dir_path, design_param_header_file_name); - fprint_spice_design_param_header(design_param_header_file_path, spice); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_heads.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_heads.h deleted file mode 100644 index 30b4b83cf..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_heads.h +++ /dev/null @@ -1,5 +0,0 @@ - -void spice_print_headers(char* include_dir_path, - float vpr_clock_period, - int num_clock, - t_spice spice); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_lut.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_lut.c deleted file mode 100644 index 8b61248ec..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_lut.c +++ /dev/null @@ -1,673 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "rr_graph_swseg.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_lut_utils.h" -#include "fpga_x2p_bitstream_utils.h" -#include "spice_utils.h" -#include "spice_mux.h" -#include "spice_pbtypes.h" -#include "spice_lut.h" - - -/***** Subroutines *****/ - -void fprint_spice_lut_subckt(FILE* fp, - t_spice_model* spice_model) { - int num_input_port = 0; - t_spice_model_port** input_port = NULL; - int num_output_port = 0; - t_spice_model_port** output_port = NULL; - int num_sram_port = 0; - t_spice_model_port** sram_port = NULL; - - int iport, ipin; - int sram_port_index = OPEN; - int mode_port_index = OPEN; - int mode_lsb = 0; - int num_dumped_port = 0; - char* mode_inport_postfix = "_mode"; - - int jport, jpin, pin_cnt; - int modegate_num_input_port = 0; - int modegate_num_input_pins = 0; - int modegate_num_output_port = 0; - t_spice_model_port** modegate_input_port = NULL; - t_spice_model_port** modegate_output_port = NULL; - char* required_gate_type = NULL; - enum e_spice_model_gate_type required_gate_model_type; - - float total_width; - int width_cnt; - - /* Ensure a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n", - __FILE__, __LINE__); - } - - /* Find input ports, output ports and sram ports*/ - input_port = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - output_port = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - sram_port = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - - /* Check */ - if (FALSE == spice_model->design_tech_info.lut_info->frac_lut) { - /* when fracturable LUT is considered - * More than 1 output is allowed - * Only two SRAM ports are allowed - */ - assert(1 == num_input_port); - assert(1 == num_output_port); - assert(1 == num_sram_port); - } else { - assert (TRUE == spice_model->design_tech_info.lut_info->frac_lut); - /* when fracturable LUT is considered - * More than 1 output is allowed - * Only two SRAM ports are allowed - */ - assert(1 == num_input_port); - for (iport = 0; iport < num_output_port; iport++) { - assert(0 < output_port[iport]->size); - } - assert(2 == num_sram_port); - } - - fprintf(fp, "***** Auto-generated LUT info: spice_model_name = %s, size = %d *****\n", - spice_model->name, input_port[0]->size); - /* Define the subckt*/ - fprintf(fp, ".subckt %s ", spice_model->name); /* Subckt name*/ - /* Input ports*/ - for (iport = 0; iport < num_input_port; iport++) { - for (ipin = 0; ipin < input_port[iport]->size; ipin++) { - fprintf(fp, "%s%d ", input_port[iport]->prefix, ipin); - } - } - /* output ports*/ - for (iport = 0; iport < num_output_port; iport++) { - for (ipin = 0; ipin < output_port[iport]->size; ipin++) { - fprintf(fp, "%s%d ", output_port[iport]->prefix, ipin); - } - } - /* sram ports */ - /* Print configuration ports*/ - num_dumped_port = 0; - for (iport = 0; iport < num_sram_port; iport++) { - /* By pass mode select ports */ - if (TRUE == sram_port[iport]->mode_select) { - continue; - } - assert(FALSE == sram_port[iport]->mode_select); - for (ipin = 0; ipin < sram_port[iport]->size; ipin++) { - fprintf(fp, "%s%d ", sram_port[iport]->prefix, ipin); - } - sram_port_index = iport; - num_dumped_port++; - } - /* Print mode configuration ports*/ - num_dumped_port = 0; - for (iport = 0; iport < num_sram_port; iport++) { - /* By pass mode select ports */ - if (FALSE == sram_port[iport]->mode_select) { - continue; - } - assert(TRUE == sram_port[iport]->mode_select); - for (ipin = 0; ipin < sram_port[iport]->size; ipin++) { - fprintf(fp, "%s_out%d ", sram_port[iport]->prefix, ipin); - } - mode_port_index = iport; - num_dumped_port++; - } - /* Check if all required SRAMs ports*/ - if (TRUE == spice_model->design_tech_info.lut_info->frac_lut) { - if (1 != num_dumped_port) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d]) Fracturable LUT (spice_model_name=%s) must have 1 mode port!\n", - __FILE__, __LINE__, spice_model->name); - exit(1); - } - } - - /* local vdd and gnd*/ - fprintf(fp, "svdd sgnd\n"); - - /* Input buffers */ - assert (1 == num_input_port); - assert (NULL != input_port); - - /* If this is a regular LUT, we give a default tri_state_map */ - if (FALSE == spice_model->design_tech_info.lut_info->frac_lut) { - for (iport = 0; iport < num_input_port; iport++) { - if (NULL == input_port[iport]->tri_state_map) { - input_port[iport]->tri_state_map = (char*)my_calloc(input_port[iport]->size, sizeof(char)); - } else { - vpr_printf(TIO_MESSAGE_WARNING, - "(File:%s, [LINE%d])Overwrite the tri-state map for the LUT inputs (name=%s)!\n", - __FILE__, __LINE__, spice_model->name); - } - for (ipin = 0; ipin < input_port[iport]->size; ipin++) { - input_port[iport]->tri_state_map[ipin] = '-'; - } - } - } - - /* Add AND/OR gates if this is a fracturable LUT */ - for (iport = 0; iport < num_input_port; iport++) { - /* Initialize lsb */ - mode_lsb = 0; - for (ipin = 0; ipin < input_port[iport]->size; ipin++) { - if ('0' == input_port[iport]->tri_state_map[ipin]) { - required_gate_type = "AND"; - required_gate_model_type = SPICE_MODEL_GATE_AND; - } - if ('1' == input_port[iport]->tri_state_map[ipin]) { - required_gate_type = "OR"; - required_gate_model_type = SPICE_MODEL_GATE_OR; - } - /* First check if we have the required gates*/ - switch (input_port[iport]->tri_state_map[ipin]) { - case '-': - break; - case '0': - case '1': - /* Check: we must have an AND2/OR2 gate */ - if (NULL == input_port[iport]->spice_model) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE: %s, [LINE%d]) %s gate for the input port (name=%s) of spice model (name=%s) is not defined!\n", - __FILE__, __LINE__, required_gate_type, - input_port[iport]->prefix, spice_model->name); - exit(1); - } - if ((SPICE_MODEL_GATE != input_port[iport]->spice_model->type) - || (required_gate_model_type != input_port[iport]->spice_model->design_tech_info.gate_info->type)) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE: %s, [LINE%d]) %s gate for the input port (name=%s) of spice model (name=%s) is not defined as a AND logic gate!\n", - __FILE__, __LINE__, required_gate_type, - input_port[iport]->prefix, spice_model->name); - exit(1); - } - /* Check input ports */ - modegate_input_port = find_spice_model_ports(input_port[iport]->spice_model, SPICE_MODEL_PORT_INPUT, &modegate_num_input_port, TRUE); - modegate_num_input_pins = 0; - for (jport = 0; jport < modegate_num_input_port; jport++) { - modegate_num_input_pins += modegate_input_port[jport]->size; - } - if (2 != modegate_num_input_pins) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE: %s, [LINE%d]) %s gate for the input port (name=%s) of spice model (name=%s) should have only 2 input pins!\n", - __FILE__, __LINE__, required_gate_type, - input_port[iport]->prefix, spice_model->name); - exit(1); - } - /* Check output ports */ - modegate_output_port = find_spice_model_ports(input_port[iport]->spice_model, SPICE_MODEL_PORT_OUTPUT, &modegate_num_output_port, TRUE); - if ( (1 != modegate_num_output_port) - || (1 != modegate_output_port[0]->size)) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE: %s, [LINE%d]) %s gate for the input port (name=%s) of spice model (name=%s) should have only 1 output!\n", - __FILE__, __LINE__, required_gate_type, - input_port[iport]->prefix, spice_model->name); - exit(1); - } - /* Instance the AND2/OR2 gate */ - fprintf(fp, "X%s_%s%d ", - input_port[iport]->spice_model->prefix, - input_port[iport]->prefix, ipin); - pin_cnt = 0; - for (jport = 0; jport < modegate_num_input_port; jport++) { - for (jpin = 0; jpin < modegate_input_port[jport]->size; jpin++) { - if (0 == pin_cnt) { - fprintf(fp, "%s%d", - input_port[iport]->prefix, ipin); - } else if (1 == pin_cnt) { - fprintf(fp, " %s_out%d", - sram_port[mode_port_index]->prefix, mode_lsb); - } - pin_cnt++; - } - } - assert(2 == pin_cnt); - fprintf(fp, " %s%s%d", - input_port[0]->prefix, mode_inport_postfix, ipin); - mode_lsb++; - /* local vdd and gnd*/ - fprintf(fp, " svdd sgnd"); - /* Call subckt name */ - fprintf(fp, " %s\n", input_port[iport]->spice_model->name); - /* Free ports */ - my_free(modegate_input_port); - my_free(modegate_output_port); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(file:%s,line[%d]) invalid LUT tri_state_map = %s ", - __FILE__, __LINE__, input_port[iport]->tri_state_map); - exit(1); - } - } - /* Check if we have dumped all the SRAM ports for mode selection */ - if ((OPEN != mode_port_index) - &&(mode_lsb != sram_port[mode_port_index]->size)) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d]) SPICE model LUT (name=%s) has a unmatched tri-state map (%s) implied by mode_port size(%d)!\n", - __FILE__, __LINE__, - spice_model->name, input_port[iport]->tri_state_map[ipin], input_port[iport]->size); - exit(1); - } - - /* Create inverters between input port and its inversion */ - for (ipin = 0; ipin < input_port[iport]->size; ipin++) { - switch (input_port[iport]->tri_state_map[ipin]) { - case '-': - /* For negative input of LUT MUX*/ - /* Output inverter with maximum size allowed - * until the rest of width is smaller than threshold */ - total_width = spice_model->lut_input_buffer->size * spice_model->lut_input_buffer->f_per_stage; - width_cnt = 0; - while (total_width > max_width_per_trans) { - fprintf(fp, "Xinv0_in%d_no%d %s%d lut_mux_in%d_inv svdd sgnd inv size=\'%g\'", - ipin, width_cnt, - input_port[iport]->prefix, ipin, - ipin, max_width_per_trans); - fprintf(fp, "\n"); - /* Update */ - total_width = total_width - max_width_per_trans; - width_cnt++; - } - /* Print if we still have to */ - if (total_width > 0) { - fprintf(fp, "Xinv0_in%d_no%d %s%d lut_mux_in%d_inv svdd sgnd inv size=\'%g\'", - ipin, width_cnt, - input_port[iport]->prefix, ipin, - ipin, total_width); - fprintf(fp, "\n"); - } - /* For postive input of LUT MUX, we use the tapered_buffer subckt directly */ - assert(1 == spice_model->lut_input_buffer->tapered_buf); - fprintf(fp, "X%s_in%d %s%d lut_mux_in%d svdd sgnd tapbuf_level%d_f%d\n", - spice_model->lut_input_buffer->spice_model->prefix, ipin, - input_port[iport]->prefix, ipin, ipin, - spice_model->lut_input_buffer->tap_buf_level, - spice_model->lut_input_buffer->f_per_stage); - fprintf(fp, "\n"); - break; - case '0': - case '1': - /* For negative input of LUT MUX*/ - /* Output inverter with maximum size allowed - * until the rest of width is smaller than threshold */ - total_width = spice_model->lut_input_buffer->size * spice_model->lut_input_buffer->f_per_stage; - width_cnt = 0; - while (total_width > max_width_per_trans) { - fprintf(fp, "Xinv0_in%d_no%d %s%s%d lut_mux_in%d_inv svdd sgnd inv size=\'%g\'", - ipin, width_cnt, - input_port[iport]->prefix, mode_inport_postfix, ipin, - ipin, max_width_per_trans); - fprintf(fp, "\n"); - /* Update */ - total_width = total_width - max_width_per_trans; - width_cnt++; - } - /* Print if we still have to */ - if (total_width > 0) { - fprintf(fp, "Xinv0_in%d_no%d %s%s%d lut_mux_in%d_inv svdd sgnd inv size=\'%g\'", - ipin, width_cnt, - input_port[iport]->prefix, mode_inport_postfix, ipin, - ipin, total_width); - fprintf(fp, "\n"); - } - /* For postive input of LUT MUX, we use the tapered_buffer subckt directly */ - assert(1 == spice_model->lut_input_buffer->tapered_buf); - fprintf(fp, "X%s_in%d %s%s%d lut_mux_in%d svdd sgnd tapbuf_level%d_f%d\n", - spice_model->lut_input_buffer->spice_model->prefix, ipin, - input_port[iport]->prefix, mode_inport_postfix, ipin, ipin, - spice_model->lut_input_buffer->tap_buf_level, - spice_model->lut_input_buffer->f_per_stage); - fprintf(fp, "\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(file:%s,line[%d]) invalid LUT tri_state_map = %s ", - __FILE__, __LINE__, input_port[iport]->tri_state_map); - exit(1); - } - } - } - - - /* Output buffers already included in LUT MUX */ - /* LUT MUX*/ - assert(sram_port[sram_port_index]->size == (int)pow(2.,(double)(input_port[0]->size))); - fprintf(fp, "Xlut_mux "); - /* SRAM ports of LUT, they are inputs of lut_muxes*/ - for (ipin = 0; ipin < sram_port[sram_port_index]->size; ipin++) { - assert(FALSE == sram_port[sram_port_index]->mode_select); - fprintf(fp, "%s%d ", sram_port[sram_port_index]->prefix, ipin); - } - /* Output port, LUT output is LUT MUX output*/ - for (iport = 0; iport < num_output_port; iport++) { - for (ipin = 0; ipin < output_port[iport]->size; ipin++) { - fprintf(fp, "%s%d ", output_port[iport]->prefix, ipin); - } - } - /* Connect MUX configuration port to LUT inputs */ - /* input port, LUT input is LUT MUX sram*/ - for (iport = 0; iport < num_input_port; iport++) { - for (ipin = 0; ipin < input_port[iport]->size; ipin++) { - fprintf(fp, "lut_mux_in%d lut_mux_in%d_inv ", ipin, ipin); - } - } - - /* Local vdd and gnd*/ - fprintf(fp, "svdd sgnd %s_mux_size%d\n", - spice_model->name, sram_port[sram_port_index]->size); - - /* End of LUT subckt*/ - fprintf(fp, ".eom\n"); - - /* Free */ - my_free(input_port); - my_free(output_port); - my_free(sram_port); - - return; -} - -/* Print LUT subckts into a SPICE file*/ -void generate_spice_luts(char* subckt_dir, - int num_spice_model, - t_spice_model* spice_models) { - FILE* fp = NULL; - char* sp_name = my_strcat(subckt_dir, luts_spice_file_name); - int imodel = 0; - - /* Create FILE*/ - fp = fopen(sp_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE netlist %s",__FILE__, __LINE__, wires_spice_file_name); - exit(1); - } - fprint_spice_head(fp,"LUTs"); - - for (imodel = 0; imodel < num_spice_model; imodel++) { - if ((SPICE_MODEL_LUT == spice_models[imodel].type) - &&(NULL == spice_models[imodel].model_netlist)) { - fprint_spice_lut_subckt(fp, &(spice_models[imodel])); - } - } - - /* Close*/ - fclose(fp); - - return; -} - -void fprint_pb_primitive_lut(FILE* fp, - char* subckt_prefix, - t_phy_pb* prim_phy_pb, - t_pb_type* prim_pb_type, - int index, - t_spice_model* spice_model) { - int i, j; - int* lut_sram_bits = NULL; /* decoded SRAM bits */ - int* mode_sram_bits = NULL; /* decoded SRAM bits */ - int* sram_bits = NULL; /* decoded SRAM bits */ - int* truth_table_length = 0; - char*** truth_table = NULL; - - int lut_size = 0; - int num_input_port = 0; - t_spice_model_port** input_ports = NULL; - int num_output_port = 0; - t_spice_model_port** output_ports = NULL; - int num_sram_port = 0; - t_spice_model_port** sram_ports = NULL; - t_spice_model_port* lut_sram_port = NULL; - t_spice_model_port* mode_bit_port = NULL; - int num_lut_pin_nets; - int* lut_pin_net = NULL; - int mapped_logical_block_index; - - char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ - t_pb_type* cur_pb_type = prim_pb_type; - char* port_prefix = NULL; - - int cur_num_sram = 0; - int num_sram = 0; - int num_lut_sram = 0; - int num_mode_sram = 0; - int expected_num_sram = 0; - char* sram_vdd_port_name = NULL; - - /* Ensure a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Asserts */ - assert(SPICE_MODEL_LUT == spice_model->type); - - /* Determine size of LUT*/ - input_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - output_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - sram_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - assert(1 == num_input_port); - lut_size = input_ports[0]->size; - num_sram = (int)pow(2.,(double)(lut_size)); - /* Find SRAM ports for truth tables and mode bits */ - sram_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - assert((1 == num_sram_port) || (2 == num_sram_port)); - for (i = 0; i < num_sram_port; i++) { - if (FALSE == sram_ports[i]->mode_select) { - lut_sram_port = sram_ports[i]; - num_lut_sram = sram_ports[i]->size; - assert (num_lut_sram == (int)pow(2.,(double)(lut_size))); - } else { - assert (TRUE == sram_ports[i]->mode_select); - mode_bit_port = sram_ports[i]; - num_mode_sram = sram_ports[i]->size; - } - } - /* Must have a lut_sram_port, while mode_bit_port is optional */ - assert (NULL != lut_sram_port); - - /* Count the number of configuration bits */ - num_sram = count_num_sram_bits_one_spice_model(spice_model, -1); - - /* Get current counter of mem_bits, bl and wl */ - cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info); - - /* If this is an idle LUT, we give an empty truth table */ - if ((NULL == prim_phy_pb) - || ((NULL != prim_phy_pb && (0 == prim_phy_pb->num_logical_blocks)))) { - lut_sram_bits = (int*) my_calloc ( num_lut_sram, sizeof(int)); - for (i = 0; i < num_lut_sram; i++) { - lut_sram_bits[i] = lut_sram_port->default_val; - } - } else { - assert (NULL != prim_phy_pb); - /* Allocate truth tables */ - truth_table_length = (int*) my_malloc (sizeof(int) * prim_phy_pb->num_logical_blocks); - truth_table = (char***) my_malloc (sizeof(char**) * prim_phy_pb->num_logical_blocks); - - /* Output log for debugging purpose */ - fprintf(fp, "***** Logic Block %s *****\n", - prim_phy_pb->spice_name_tag); - - /* Find truth tables and decode them one by one - * Fracturable LUT may have multiple truth tables, - * which should be grouped in a unique one - */ - for (i = 0; i < prim_phy_pb->num_logical_blocks; i++) { - mapped_logical_block_index = prim_phy_pb->logical_block[i]; - /* For wired LUT we provide a default truth table */ - if (TRUE == prim_phy_pb->is_wired_lut[i]) { - /* TODO: assign post-routing lut truth table!!!*/ - get_mapped_lut_phy_pb_input_pin_vpack_net_num(prim_phy_pb, &num_lut_pin_nets, &lut_pin_net); - truth_table[i] = assign_post_routing_wired_lut_truth_table(prim_phy_pb->rr_graph->rr_node[prim_phy_pb->lut_output_pb_graph_pin[i]->rr_node_index_physical_pb].vpack_net_num, - num_lut_pin_nets, lut_pin_net, &truth_table_length[i]); - } else { - assert (FALSE == prim_phy_pb->is_wired_lut[i]); - assert (VPACK_COMB == logical_block[mapped_logical_block_index].type); - /* Get the mapped vpack_net_num of this physical LUT pb */ - get_mapped_lut_phy_pb_input_pin_vpack_net_num(prim_phy_pb, &num_lut_pin_nets, &lut_pin_net); - /* consider LUT pin remapping when assign lut truth tables */ - /* Match truth table and post-routing results */ - truth_table[i] = assign_post_routing_lut_truth_table(&logical_block[mapped_logical_block_index], - num_lut_pin_nets, lut_pin_net, &truth_table_length[i]); - } - /* Adapt truth table for a fracturable LUT - * TODO: Determine fixed input bits for this truth table: - * 1. input bits within frac_level (all '-' if not specified) - * 2. input bits outside frac_level, decoded to its output mask (0 -> first part -> all '1') - */ - adapt_truth_table_for_frac_lut(prim_phy_pb->lut_output_pb_graph_pin[i], - truth_table_length[i], truth_table[i]); - /* Output log for debugging purpose */ - if (WIRED_LUT_LOGICAL_BLOCK_ID == mapped_logical_block_index) { - fprintf(fp, "***** Wired LUT: mapped to a buffer *****\n"); - } else { - fprintf(fp, "***** Mapped Logic Block[%d] %s *****\n", - i, logical_block[mapped_logical_block_index].name); - } - fprintf(fp, "***** Net map *****\n*"); - for (j = 0; j < num_lut_pin_nets; j++) { - if (OPEN == lut_pin_net[j]) { - fprintf(fp, " OPEN, "); - } else { - assert (OPEN != lut_pin_net[j]); - fprintf(fp, " %s, ", vpack_net[lut_pin_net[j]].name); - } - } - fprintf(fp, "\n"); - fprintf(fp, "***** Truth Table *****\n"); - for (j = 0; j < truth_table_length[i]; j++) { - fprintf(fp, "*%s\n", truth_table[i][j]); - } - } - /* Generate base sram bits*/ - lut_sram_bits = generate_frac_lut_sram_bits(prim_phy_pb, truth_table_length, truth_table, lut_sram_port->default_val); - } - - /* Add mode bits */ - if (NULL != mode_bit_port) { - if (NULL != prim_phy_pb) { - mode_sram_bits = decode_mode_bits(prim_phy_pb->mode_bits, &expected_num_sram); - } else { /* get default mode_bits */ - mode_sram_bits = decode_mode_bits(prim_pb_type->mode_bits, &expected_num_sram); - } - assert(expected_num_sram == num_mode_sram); - } - - /* Merge the SRAM bits from LUT SRAMs and Mode selection */ - assert ( num_sram == num_lut_sram + num_mode_sram ); - sram_bits = (int*)my_calloc(num_sram, sizeof(int)); - /* LUT SRAMs go first and then mode bits */ - memcpy(sram_bits, lut_sram_bits, num_lut_sram * sizeof(int)); - if (NULL != mode_bit_port) { - memcpy(sram_bits + num_lut_sram, mode_sram_bits, num_mode_sram * sizeof(int)); - } - - /* Subckt definition*/ - fprintf(fp, ".subckt %s%s[%d] ", formatted_subckt_prefix, cur_pb_type->name, index); - /* Print inputs, outputs, inouts, clocks, NO SRAMs*/ - /* - port_prefix = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 + - strlen(my_itoa(index)) + 1 + 1)); - sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, cur_pb_type->name, index); - */ - /* Simplify the prefix, make the SPICE netlist readable*/ - port_prefix = (char*)my_malloc(sizeof(char)* - (strlen(cur_pb_type->name) + 1 + - strlen(my_itoa(index)) + 1 + 1)); - sprintf(port_prefix, "%s[%d]", cur_pb_type->name, index); - - /* Only dump the global ports belonging to a spice_model - * Do not go recursive, we can freely define global ports anywhere in SPICE netlist - */ - rec_fprint_spice_model_global_ports(fp, spice_model, FALSE); - - fprint_pb_type_ports(fp, port_prefix, 0, cur_pb_type); - /* SRAM bits are fixed in this subckt, no need to define them here*/ - /* Local Vdd and gnd*/ - fprintf(fp, "svdd sgnd\n"); - /* Definition ends*/ - - /* Call SRAM subckts*/ - /* Give the VDD port name for SRAMs */ - sram_vdd_port_name = (char*)my_malloc(sizeof(char)* - (strlen(spice_tb_global_vdd_lut_sram_port_name) - + 1 )); - sprintf(sram_vdd_port_name, "%s", - spice_tb_global_vdd_lut_sram_port_name); - /* Now Print SRAMs one by one */ - for (i = 0; i < num_sram; i++) { - fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, spice_model, sram_vdd_port_name); - } - - /* Call LUT subckt*/ - fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt); - /* Connect inputs*/ - /* Connect outputs*/ - fprint_pb_type_ports(fp, port_prefix, 0, cur_pb_type); - /* Connect srams*/ - for (i = 0; i < num_sram; i++) { - assert( (0 == sram_bits[i]) || (1 == sram_bits[i]) ); - fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_num_sram + i, sram_bits[i]); - } - - /* vdd should be connected to special global wire gvdd_lut and gnd, - * Every LUT has a special VDD for statistics - */ - fprintf(fp, "gvdd_%s[%d] sgnd %s\n", spice_model->prefix, spice_model->cnt, spice_model->name); - /* TODO: Add a nodeset for convergence */ - - /* End of subckt*/ - fprintf(fp, ".eom\n"); - - /* Store the configuraion bit to linked-list */ - add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_num_sram, - num_sram, sram_bits); - - spice_model->cnt++; - - /*Free*/ - my_free(formatted_subckt_prefix); - my_free(input_ports); - my_free(output_ports); - my_free(sram_ports); - my_free(sram_bits); - my_free(port_prefix); - my_free(sram_vdd_port_name); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_lut.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_lut.h deleted file mode 100644 index ff8636184..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_lut.h +++ /dev/null @@ -1,17 +0,0 @@ - - - -void fprint_spice_lut_subckt(FILE* fp, - t_spice_model* spice_model); - -void generate_spice_luts(char* subckt_dir, - int num_spice_model, - t_spice_model* spice_models); - - -void fprint_pb_primitive_lut(FILE* fp, - char* subckt_prefix, - t_phy_pb* prim_phy_pb, - t_pb_type* prim_pb_type, - int index, - t_spice_model* spice_model); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux.c deleted file mode 100644 index ef6acef6a..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux.c +++ /dev/null @@ -1,1427 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "rr_graph_swseg.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include fpga_spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_mux_utils.h" -#include "fpga_x2p_bitstream_utils.h" - -/* Include spice support headers*/ -#include "spice_utils.h" -#include "spice_lut.h" -#include "spice_pbtypes.h" -#include "spice_mux.h" - -/***** Subroutines *****/ - -static -void fprint_spice_mux_model_basis_cmos_subckt(FILE* fp, char* subckt_name, - int num_input_per_level, - t_spice_model spice_model, - int mux_size, - boolean special_basis) { - char* pgl_name = NULL; - int num_sram_bits = 0; - int i; - - /* Make sure we have a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert(1 < num_input_per_level); - - /* Ensure we have a CMOS MUX*/ - /* Exception: LUT require an auto-generation of netlist can run as well*/ - assert((SPICE_MODEL_MUX == spice_model.type)||(SPICE_MODEL_LUT == spice_model.type)); - assert(SPICE_MODEL_DESIGN_CMOS == spice_model.design_tech); - assert(NULL != spice_model.pass_gate_logic); - - /* Print the subckt */ - fprintf(fp, ".subckt %s ", subckt_name); - for (i = 0; i < num_input_per_level; i++) { - fprintf(fp, "in%d ", i); - } - fprintf(fp, "out "); - - /* General cases */ - num_sram_bits = determine_num_sram_bits_mux_basis_subckt(&spice_model, mux_size, - num_input_per_level, special_basis); - - for (i = 0; i < num_sram_bits; i++) { - fprintf(fp, "sel%d sel_inv%d ", i, i); - } - fprintf(fp, "svdd sgnd\n"); - /* Identify the pass-gate logic*/ - switch (spice_model.pass_gate_logic->type) { - case SPICE_MODEL_PASS_GATE_TRANSMISSION: - pgl_name = cpt_subckt_name; - /* We do not need to know the structure of multiplexer, just follow the number of input - * Identify a special case: input_size = 2 - */ - if (1 == num_sram_bits) { - fprintf(fp,"X%s_0 in0 out sel0 sel_inv0 svdd sgnd %s nmos_size=\'%s%s\' pmos_size=\'%s%s\'\n", - pgl_name, pgl_name, - spice_model.name, design_param_postfix_pass_gate_logic_nmos_size, - spice_model.name, design_param_postfix_pass_gate_logic_pmos_size); - fprintf(fp,"X%s_1 in1 out sel_inv0 sel0 svdd sgnd %s nmos_size=\'%s%s\' pmos_size=\'%s%s\'\n", - pgl_name, pgl_name, - spice_model.name, design_param_postfix_pass_gate_logic_nmos_size, - spice_model.name, design_param_postfix_pass_gate_logic_pmos_size); - } else { - for (i = 0; i < num_input_per_level; i++) { - fprintf(fp,"X%s_%d in%d out sel%d sel_inv%d svdd sgnd %s nmos_size=\'%s%s\' pmos_size=\'%s%s\'\n", - pgl_name, i, i, i, i, pgl_name, - spice_model.name, design_param_postfix_pass_gate_logic_nmos_size, - spice_model.name, design_param_postfix_pass_gate_logic_pmos_size); - } - } - break; - case SPICE_MODEL_PASS_GATE_TRANSISTOR: - pgl_name = nmos_subckt_name; - /* We do not need to know the structure of multiplexer, just follow the number of input - * Identify a special case: input_size = 2 - */ - if (1 == num_sram_bits) { - fprintf(fp,"X%s_0 in0 sel0 out sgnd %s W=\'%s%s*wn\'\n", - pgl_name, pgl_name, - spice_model.name, design_param_postfix_pass_gate_logic_nmos_size); - fprintf(fp,"X%s_1 in1 sel_inv0 out sgnd %s W=\'%s%s*wn\'\n", - pgl_name, pgl_name, - spice_model.name, design_param_postfix_pass_gate_logic_nmos_size); - } else { - for (i = 0; i < num_input_per_level; i++) { - fprintf(fp,"X%s_%d in%d sel%d out sgnd %s W=\'%s%s*wn\'\n", - pgl_name, i, i, i, - pgl_name, - spice_model.name, design_param_postfix_pass_gate_logic_nmos_size); - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File: %s,[LINE%d])Invalid pass gate logic for spice model(name:%s)!\n", - __FILE__, __LINE__, spice_model.name); - exit(1); - } - - fprintf(fp,".eom\n"); - fprintf(fp,"\n"); - - return; -} - -static -void fprint_spice_mux_model_basis_rram_subckt(FILE* fp, char* subckt_name, - int mux_size, - int num_input_per_level, - t_spice_model spice_model, - boolean special_basis) { - int i, num_sram_bits; - char* prog_pmos_subckt_name = NULL; - char* prog_nmos_subckt_name = NULL; - char* prog_wp = NULL; - char* prog_wn = NULL; - - /* Make sure we have a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* assert(SPICE_MODEL_PASS_GATE_TRANSMISSION == spice_model.pass_gate_logic->type); */ - assert(0. < spice_model.design_tech_info.rram_info->wprog_set_pmos); - assert(0. < spice_model.design_tech_info.rram_info->wprog_reset_pmos); - assert(0. < spice_model.design_tech_info.rram_info->wprog_set_nmos); - assert(0. < spice_model.design_tech_info.rram_info->wprog_reset_nmos); - - /* Ensure we have a CMOS MUX*/ - /* Exception: LUT require an auto-generation of netlist can run as well*/ - assert((SPICE_MODEL_MUX == spice_model.type)||(SPICE_MODEL_LUT == spice_model.type)); - assert(SPICE_MODEL_DESIGN_RRAM == spice_model.design_tech); - - /* Check */ - assert(1 < num_input_per_level); - - /* Determine the number of memory bit - * The function considers a special case : - * 2-input basis in tree-like MUX only requires 1 memory bit */ - num_sram_bits = determine_num_sram_bits_mux_basis_subckt(&spice_model, mux_size, num_input_per_level, special_basis); - - /* Consider advanced RRAM multiplexer design - * Advanced design employ normal logic transistors - * Basic design employ IO transistors - */ - if (TRUE == spice_model.design_tech_info.mux_info->advanced_rram_design) { - prog_pmos_subckt_name = pmos_subckt_name; - prog_nmos_subckt_name = nmos_subckt_name; - prog_wp = "wp"; - prog_wn = "wn"; - } else { - prog_pmos_subckt_name = io_pmos_subckt_name; - prog_nmos_subckt_name = io_nmos_subckt_name; - prog_wp = "io_wp"; - prog_wn = "io_wn"; - } - - fprintf(fp, ".subckt %s ", subckt_name); - for (i = 0; i < num_input_per_level; i++) { - fprintf(fp, "in%d ", i); - } - fprintf(fp, "out "); - for (i = 0; i < num_sram_bits; i++) { - fprintf(fp, "sel%d sel_inv%d ", i, i); - } - fprintf(fp, "svdd sgnd "); - fprintf(fp, "ron=\'%s%s\' roff=\'%s%s\' ", - spice_model.name, design_param_postfix_rram_ron, - spice_model.name, design_param_postfix_rram_roff); - fprintf(fp, "wprog_set_nmos=\'%s%s*%s\' wprog_reset_nmos=\'%s%s*%s\' ", - spice_model.name, design_param_postfix_rram_wprog_set_nmos, - prog_wn, - spice_model.name, design_param_postfix_rram_wprog_reset_nmos, - prog_wn); - fprintf(fp, "wprog_set_pmos=\'%s%s*%s\' wprog_reset_pmos=\'%s%s*%s\' \n", - spice_model.name, design_param_postfix_rram_wprog_set_pmos, - prog_wp, - spice_model.name, design_param_postfix_rram_wprog_reset_pmos, - prog_wp); - /* Print the new 2T1R structure */ - /* Switch case: - * when there is only 1 SRAM bit */ - if (1 == num_sram_bits) { - /* RRAMs */ - fprintf(fp, "Xrram_0 in0 out sel0 sel_inv0 rram_behavior switch_thres=vsp ron=ron roff=roff\n"); - /* Programming transistor pairs */ - fprintf(fp, "Xnmos_prog_pair0 in0 sgnd sgnd sgnd %s W=\'wprog_reset_nmos\' \n", - prog_nmos_subckt_name); - fprintf(fp, "Xpmos_prog_pair0 in0 svdd svdd svdd %s W=\'wprog_set_pmos\' \n", - prog_pmos_subckt_name); - /* RRAMs */ - fprintf(fp, "Xrram_1 in1 out sel_inv0 sel0 rram_behavior switch_thres=vsp ron=ron roff=roff\n"); - /* Programming transistor pairs */ - fprintf(fp, "Xnmos_prog_pair_in1 in1 sgnd sgnd sgnd %s W=\'wprog_reset_nmos\' \n", - prog_nmos_subckt_name); - fprintf(fp, "Xpmos_prog_pair_in1 in1 svdd svdd svdd %s W=\'wprog_set_pmos\' \n", - prog_pmos_subckt_name); - } else { - for (i = 0; i < num_input_per_level; i++) { - /* RRAMs */ - fprintf(fp, "Xrram_%d in%d out sel%d sel_inv%d rram_behavior switch_thres=vsp ron=ron roff=roff\n", - i, i, i, i); - /* Programming transistor pairs */ - fprintf(fp, "Xnmos_prog_pair_in%d in%d sgnd sgnd sgnd %s W=\'wprog_reset_nmos\' \n", - i, i, prog_nmos_subckt_name); - fprintf(fp, "Xpmos_prog_pair_in%d in%d svdd svdd svdd %s W=\'wprog_set_pmos\' \n", - i, i, prog_pmos_subckt_name); - } - } - /* Programming transistor pairs shared at the output */ - fprintf(fp, "Xnmos_prog_pair_out out sgnd sgnd sgnd %s W=\'wprog_set_nmos\' \n", - prog_nmos_subckt_name); - fprintf(fp, "Xpmos_prog_pair_out out svdd svdd svdd %s W=\'wprog_reset_pmos\' \n", - prog_pmos_subckt_name); - fprintf(fp,".eom\n"); - fprintf(fp,"\n"); - - return; -} - -/* Print the SPICE model of a 2:1 MUX which is the basis */ -static -void fprint_spice_mux_model_basis_subckt(FILE* fp, - t_spice_mux_model* spice_mux_model) { - char* mux_basis_subckt_name = NULL; - char* mux_special_basis_subckt_name = NULL; - int num_input_basis_subckt = 0; - int num_input_special_basis_subckt = 0; - - /* Make sure we have a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* Try to find a mux in cmos technology, - * if we have, then build CMOS 2:1 MUX, and given cmos_mux2to1_subckt_name - */ - /* Exception: LUT require an auto-generation of netlist can run as well*/ - assert((SPICE_MODEL_MUX == spice_mux_model->spice_model->type) - ||(SPICE_MODEL_LUT == spice_mux_model->spice_model->type)); - - /* Generate the spice_mux_arch */ - spice_mux_model->spice_mux_arch = (t_spice_mux_arch*)my_malloc(sizeof(t_spice_mux_arch)); - init_spice_mux_arch(spice_mux_model->spice_model, spice_mux_model->spice_mux_arch, spice_mux_model->size); - - /* Corner case: Error out MUX_SIZE = 2, automatcially give a one-level structure */ - /* - if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of SPICE model (%s) should be one-level because it is linked to a 2:1 MUX!\n", - __FILE__, __LINE__, spice_mux_model->spice_model->name); - exit(1); - } - */ - - /* Prepare the basis subckt name */ - mux_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_mux_model->spice_model->name) + 5 - + strlen(my_itoa(spice_mux_model->size)) - + strlen(mux_basis_posfix) + 1)); - sprintf(mux_basis_subckt_name, "%s_size%d%s", - spice_mux_model->spice_model->name, spice_mux_model->size, mux_basis_posfix); - - /* deteremine the number of inputs of basis subckt */ - num_input_basis_subckt = spice_mux_model->spice_mux_arch->num_input_basis; - - /* Determine the input size of the spcial basis */ - num_input_special_basis_subckt = find_spice_mux_arch_special_basis_size(*(spice_mux_model->spice_mux_arch)); - - /* Name the special basis subckt */ - mux_special_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_mux_model->spice_model->name) + 5 - + strlen(my_itoa(spice_mux_model->size)) - + strlen(mux_special_basis_posfix) + 1)); - sprintf(mux_special_basis_subckt_name, "%s_size%d%s", - spice_mux_model->spice_model->name, spice_mux_model->size, mux_special_basis_posfix); - - /* Print the basis subckt*/ - switch (spice_mux_model->spice_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - /* Give the subckt name*/ - fprint_spice_mux_model_basis_cmos_subckt(fp, mux_basis_subckt_name, - num_input_basis_subckt, - *(spice_mux_model->spice_model), - spice_mux_model->size, - FALSE); - /* Dump subckt of special basis if required */ - if (0 < num_input_special_basis_subckt) { - fprint_spice_mux_model_basis_cmos_subckt(fp, mux_special_basis_subckt_name, - num_input_special_basis_subckt, - (*spice_mux_model->spice_model), - spice_mux_model->size, - TRUE); - } - break; - case SPICE_MODEL_DESIGN_RRAM: - /* RRAM LUT are not yet supported ! */ - if (SPICE_MODEL_LUT == spice_mux_model->spice_model->type) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])RRAM LUT is not supported!\n", - __FILE__, __LINE__); - exit(1); - } - fprint_spice_mux_model_basis_rram_subckt(fp, mux_basis_subckt_name, - spice_mux_model->size, - num_input_basis_subckt, - *(spice_mux_model->spice_model), - FALSE); - /* Dump subckt of special basis if required */ - if (0 < num_input_special_basis_subckt) { - fprint_spice_mux_model_basis_rram_subckt(fp, mux_special_basis_subckt_name, - spice_mux_model->size, - num_input_special_basis_subckt, - (*spice_mux_model->spice_model), - TRUE); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", - __FILE__, __LINE__, spice_mux_model->spice_model->name); - exit(1); - } - - /* Free */ - my_free(mux_basis_subckt_name); - my_free(mux_special_basis_subckt_name); - - return; -} - -void fprint_spice_cmos_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name, - t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { - int i, j, level, nextlevel; - int nextj, out_idx; - int mux_basis_cnt = 0; - - boolean* inter_buf_loc = NULL; - - /* Make sure we have a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* Intermediate buffer location map */ - inter_buf_loc = (boolean*)my_calloc(spice_mux_arch.num_level + 1, sizeof(boolean)); - for (i = 0; i < spice_mux_arch.num_level + 1; i++) { - inter_buf_loc[i] = FALSE; - } - printf("location_map: %s", spice_model.lut_intermediate_buffer->location_map); - if (NULL != spice_model.lut_intermediate_buffer->location_map) { - assert (spice_mux_arch.num_level - 1 == strlen(spice_model.lut_intermediate_buffer->location_map)); - /* For intermediate buffers */ - for (i = 0; i < spice_mux_arch.num_level - 1; i++) { - if ('1' == spice_model.lut_intermediate_buffer->location_map[i]) { - inter_buf_loc[spice_mux_arch.num_level - i - 1] = TRUE; - } - } - } - - mux_basis_cnt = 0; - for (i = 0; i < spice_mux_arch.num_level; i++) { - level = spice_mux_arch.num_level - i; - nextlevel = spice_mux_arch.num_level - i - 1; - /* Check */ - assert(nextlevel > -1); - /* Print basis mux2to1 for each level*/ - for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j++) { - nextj = j + 1; - out_idx = j/2; - /* Each basis mux2to1: svdd sgnd */ - fprintf(fp, "Xmux_basis_no%d ", mux_basis_cnt); /* given_name */ - /* For intermediate buffers */ - if (TRUE == inter_buf_loc[level]) { - fprintf(fp, "mux2_l%d_in%d_buf mux2_l%d_in%d_buf ", level, j, level, nextj); /* input0 input1 */ - } else { - fprintf(fp, "mux2_l%d_in%d mux2_l%d_in%d ", level, j, level, nextj); /* input0 input1 */ - } - fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ - /* fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, nextlevel, sram_port[0]->prefix, nextlevel);*/ /* sram sram_inv */ - fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, i, sram_port[0]->prefix, i); /* sram sram_inv */ - fprintf(fp, "svdd sgnd %s\n", mux_basis_subckt_name); /* subckt_name */ - /* For intermediate buffers */ - if (TRUE == inter_buf_loc[nextlevel]) { - fprintf(fp, "X%s_%d_%d ", - spice_model.lut_intermediate_buffer->spice_model->name, - nextlevel, out_idx); /* Given name*/ - fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ - fprintf(fp, "mux2_l%d_in%d_buf ", nextlevel, out_idx); /* input0 input1 */ - fprintf(fp, "svdd sgnd %s\n", spice_model.lut_intermediate_buffer->spice_model->name); /* subckt_name */ - } - /* Update the counter */ - j = nextj; - mux_basis_cnt++; - } - } - /* Assert */ - assert(0 == nextlevel); - assert(0 == out_idx); - assert(mux_basis_cnt == spice_mux_arch.num_input - 1); - - /* Free */ - my_free(inter_buf_loc); - - return; -} - -void fprint_spice_cmos_mux_multilevel_structure(FILE* fp, - char* mux_basis_subckt_name, - char* mux_special_basis_subckt_name, - t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { - int i, j, k, level, nextlevel, sram_idx; - int out_idx; - int mux_basis_cnt = 0; - int mux_special_basis_cnt = 0; - int cur_num_input_basis = 0; - - /* Make sure we have a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); - exit(1); - } - - mux_basis_cnt = 0; - assert((2 == spice_mux_arch.num_input_basis)||(2 < spice_mux_arch.num_input_basis)); - for (i = 0; i < spice_mux_arch.num_level; i++) { - level = spice_mux_arch.num_level - i; - nextlevel = spice_mux_arch.num_level - i - 1; - sram_idx = nextlevel * spice_mux_arch.num_input_basis; - /* Check */ - assert(nextlevel > -1); - /* Print basis muxQto1 for each level*/ - for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j = j+cur_num_input_basis) { - /* output index */ - out_idx = j/spice_mux_arch.num_input_basis; - /* Determine the number of input of this basis */ - cur_num_input_basis = spice_mux_arch.num_input_basis; - /* See if we need a special basis */ - if ((j + cur_num_input_basis) > spice_mux_arch.num_input_per_level[nextlevel]) { - cur_num_input_basis = spice_mux_arch.num_input_per_level[nextlevel] - j; - /* Print the special basis subckt */ - /* Each basis muxQto1: svdd sgnd */ - fprintf(fp, "Xmux_special_basis_no%d ", mux_special_basis_cnt); /* given_name */ - for (k = 0; k < cur_num_input_basis; k++) { - fprintf(fp, "mux2_l%d_in%d ", level, j + k); /* input0 input1 */ - } - fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ - /* Print number of sram bits for this basis */ - for (k = sram_idx; k < (sram_idx + cur_num_input_basis); k++) { - fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, k, sram_port[0]->prefix, k); /* sram sram_inv */ - } - fprintf(fp, "svdd sgnd %s\n", mux_special_basis_subckt_name); /* subckt_name */ - /* update counter */ - mux_special_basis_cnt++; - continue; - } - /* Reach here, it means we need a normal basis subckt */ - /* Each basis muxQto1: svdd sgnd */ - fprintf(fp, "Xmux_basis_no%d ", mux_basis_cnt); /* given_name */ - for (k = 0; k < cur_num_input_basis; k++) { - fprintf(fp, "mux2_l%d_in%d ", level, j + k); /* input0 input1 */ - } - fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ - /* Print number of sram bits for this basis */ - for (k = sram_idx; k < (sram_idx + cur_num_input_basis); k++) { - fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, k, sram_port[0]->prefix, k); /* sram sram_inv */ - } - fprintf(fp, "svdd sgnd %s\n", mux_basis_subckt_name); /* subckt_name */ - /* Update the counter */ - mux_basis_cnt++; - } - } - /* Assert */ - assert(0 == nextlevel); - assert(0 == out_idx); - assert((1 == mux_special_basis_cnt)||(0 == mux_special_basis_cnt)); - /* - assert((mux_basis_cnt + mux_special_basis_cnt) - == (int)((spice_mux_arch.num_input - 1)/(spice_mux_arch.num_input_basis - 1)) + 1); - */ - - return; -} - -void fprint_spice_cmos_mux_onelevel_structure(FILE* fp, char* mux_basis_subckt_name, - t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { - int k, mux_basis_cnt; - int level, nextlevel, out_idx; - - /* Make sure we have a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); - exit(1); - } - - assert(SPICE_MODEL_DESIGN_CMOS == spice_model.design_tech); - - /* Initialize */ - mux_basis_cnt = 0; - level = 1; - nextlevel = 0; - out_idx = 0; - - /* Each basis muxQto1: svdd sgnd */ - fprintf(fp, "Xmux_basis_no%d ", mux_basis_cnt); /* given_name */ - for (k = 0; k < spice_mux_arch.num_input; k++) { - fprintf(fp, "mux2_l%d_in%d ", level, k); /* input0 input1 */ - } - fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ - /* Print number of sram bits for this basis */ - for (k = 0; k < spice_mux_arch.num_input; k++) { - fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, k, sram_port[0]->prefix, k); /* sram sram_inv */ - } - fprintf(fp, "svdd sgnd %s\n", mux_basis_subckt_name); /* subckt_name */ - /* Update the counter */ - mux_basis_cnt++; - - /* Check */ - return; -} - -/** This is an old tree-like RRAM MUX, which is not manufacturable - */ -void fprint_spice_rram_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name, - t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { - int i, j, level, nextlevel; - int nextj, out_idx; - int mux_basis_cnt = 0; - - /* Make sure we have a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); - exit(1); - } - - mux_basis_cnt = 0; - for (i = 0; i < spice_mux_arch.num_level; i++) { - level = spice_mux_arch.num_level - i; - nextlevel = spice_mux_arch.num_level - i - 1; - /* Check */ - assert(nextlevel > -1); - /* Print basis mux2to1 for each level*/ - for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j++) { - nextj = j + 1; - out_idx = j/2; - /* Each basis mux2to1: svdd sgnd */ - fprintf(fp, "Xmux_basis_no%d ", mux_basis_cnt); /* given_name */ - fprintf(fp, "mux2_l%d_in%d mux2_l%d_in%d ", level, j, level, nextj); /* input0 input1 */ - fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ - fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, i, sram_port[0]->prefix, i); /* sram sram_inv */ - fprintf(fp, "svdd sgnd %s\n", mux_basis_subckt_name); /* subckt_name */ - /* Update the counter */ - j = nextj; - mux_basis_cnt++; - } - } - /* Assert */ - assert(0 == nextlevel); - assert(0 == out_idx); - assert(mux_basis_cnt == spice_mux_arch.num_input - 1); - - return; -} - -/** This is supposed to be a multi-level 4T1R RRAM MUX - */ -void fprint_spice_rram_mux_multilevel_structure(FILE* fp, char* mux_basis_subckt_name, - char* mux_special_basis_subckt_name, - t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { - int i, j, k, level, nextlevel, sram_idx; - int out_idx; - int mux_basis_cnt = 0; - int mux_special_basis_cnt = 0; - int cur_num_input_basis = 0; - - /* Make sure we have a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); - exit(1); - } - - mux_basis_cnt = 0; - assert((2 == spice_mux_arch.num_input_basis)||(2 < spice_mux_arch.num_input_basis)); - for (i = 0; i < spice_mux_arch.num_level; i++) { - level = spice_mux_arch.num_level - i; - nextlevel = spice_mux_arch.num_level - i - 1; - sram_idx = nextlevel * spice_mux_arch.num_input_basis; - /* Check */ - assert(nextlevel > -1); - /* Print basis muxQto1 for each level*/ - for (j = 0; j < spice_mux_arch.num_input_per_level[nextlevel]; j = j+cur_num_input_basis) { - /* output index */ - out_idx = j/spice_mux_arch.num_input_basis; - /* Determine the number of input of this basis */ - cur_num_input_basis = spice_mux_arch.num_input_basis; - /* See if we need a special basis */ - if ((j + cur_num_input_basis) > spice_mux_arch.num_input_per_level[nextlevel]) { - cur_num_input_basis = spice_mux_arch.num_input_per_level[nextlevel] - j; - /* Print the special basis subckt */ - /* Each basis muxQto1: svdd sgnd */ - fprintf(fp, "Xmux_special_basis_no%d ", mux_special_basis_cnt); /* given_name */ - for (k = 0; k < cur_num_input_basis; k++) { - fprintf(fp, "mux2_l%d_in%d ", level, j + k); /* input0 input1 */ - } - fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ - /* Print number of sram bits for this basis */ - for (k = sram_idx; k < (sram_idx + cur_num_input_basis); k++) { - fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, k, sram_port[0]->prefix, k); /* sram sram_inv */ - } - fprintf(fp, "svdd sgnd %s\n", mux_special_basis_subckt_name); /* subckt_name */ - /* update counter */ - mux_special_basis_cnt++; - continue; - } - /* Reach here, it means we need a normal basis subckt */ - /* Each basis muxQto1: svdd sgnd */ - fprintf(fp, "Xmux_basis_no%d ", mux_basis_cnt); /* given_name */ - for (k = 0; k < cur_num_input_basis; k++) { - fprintf(fp, "mux2_l%d_in%d ", level, j + k); /* input0 input1 */ - } - fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ - /* Print number of sram bits for this basis */ - for (k = sram_idx; k < (sram_idx + cur_num_input_basis); k++) { - fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, k, sram_port[0]->prefix, k); /* sram sram_inv */ - } - fprintf(fp, "svdd sgnd %s\n", mux_basis_subckt_name); /* subckt_name */ - /* Update the counter */ - mux_basis_cnt++; - } - } - /* Assert */ - assert(0 == nextlevel); - assert(0 == out_idx); - assert((1 == mux_special_basis_cnt)||(0 == mux_special_basis_cnt)); - assert((mux_basis_cnt + mux_special_basis_cnt) - == (int)((spice_mux_arch.num_input - 1)/(spice_mux_arch.num_input_basis - 1)) + 1); - - return; -} - -/** Generate the structure of 4T1R-based RRAM MUX structure - * 4T1R-based RRAM MUX is optimal in area, delay and power only when it is built with one-level structure - */ -void fprint_spice_rram_mux_onelevel_structure(FILE* fp, - char* mux_basis_subckt_name, - t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { - int k, mux_basis_cnt; - int level, nextlevel, out_idx, num_sram_bits; - - /* Make sure we have a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); - exit(1); - } - - assert(SPICE_MODEL_DESIGN_RRAM == spice_model.design_tech); - - /* Initialize */ - mux_basis_cnt = 0; - level = 1; - nextlevel = 0; - out_idx = 0; - - /* Each basis muxQto1: svdd sgnd */ - fprintf(fp, "Xmux_basis_no%d ", mux_basis_cnt); /* given_name */ - for (k = 0; k < spice_mux_arch.num_input; k++) { - fprintf(fp, "mux2_l%d_in%d ", level, k); /* input0 input1 */ - } - fprintf(fp, "mux2_l%d_in%d ", nextlevel, out_idx); /* output */ - - /* Print number of sram bits for this basis */ - num_sram_bits = determine_num_sram_bits_mux_basis_subckt(&spice_model, spice_mux_arch.num_input, - spice_mux_arch.num_input, - FALSE); - - for (k = 0; k < num_sram_bits; k++) { - fprintf(fp, "%s%d %s_inv%d ", sram_port[0]->prefix, k, sram_port[0]->prefix, k); /* sram sram_inv */ - } - fprintf(fp, "svdd sgnd %s\n", mux_basis_subckt_name); /* subckt_name */ - /* Update the counter */ - mux_basis_cnt++; - - return; -} - -void fprint_spice_mux_model_cmos_subckt(FILE* fp, - int mux_size, - t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch) { - int iport, ipin; - int num_input_port = 0; - int num_output_port = 0; - int num_sram_port = 0; - t_spice_model_port** input_port = NULL; - t_spice_model_port** output_port = NULL; - t_spice_model_port** sram_port = NULL; - int num_mode_bits = 0; - int num_conf_bits = 0; - - enum e_spice_model_structure cur_mux_structure; - - /* Find the basis subckt*/ - char* mux_basis_subckt_name = NULL; - char* mux_special_basis_subckt_name = NULL; - - /* Basis is always needed */ - mux_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model.name) + 5 - + strlen(my_itoa(mux_size)) - + strlen(mux_basis_posfix) + 1)); - sprintf(mux_basis_subckt_name, "%s_size%d%s", - spice_model.name, mux_size, mux_basis_posfix); - /* Special basis is on request, but anyway we prepare to call it.*/ - mux_special_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model.name) + 5 - + strlen(my_itoa(mux_size)) - + strlen(mux_special_basis_posfix) + 1)); - sprintf(mux_special_basis_subckt_name, "%s_size%d%s", - spice_model.name, mux_size, mux_special_basis_posfix); - - /* Make sure we have a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* Ensure we have a CMOS MUX, - * ATTENTION: support LUT as well - */ - assert((SPICE_MODEL_MUX == spice_model.type)||(SPICE_MODEL_LUT == spice_model.type)); - assert(SPICE_MODEL_DESIGN_CMOS == spice_model.design_tech); - - /* Find the input port, output port, and sram port*/ - input_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - output_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - sram_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - - /* Asserts*/ - if ((SPICE_MODEL_MUX == spice_model.type) - || ((SPICE_MODEL_LUT == spice_model.type) - && (FALSE == spice_model.design_tech_info.lut_info->frac_lut))) { - assert(1 == num_input_port); - assert(1 == num_output_port); - assert(1 == num_sram_port); - assert(1 == output_port[0]->size); - } else { - assert((SPICE_MODEL_LUT == spice_model.type) - && (TRUE == spice_model.design_tech_info.lut_info->frac_lut)); - assert(1 == num_input_port); - assert(2 == num_sram_port); - for (iport = 0; iport < num_output_port; iport++) { - assert(0 < output_port[iport]->size); - } - } - - /* Setup a reasonable frac_out level for the output port*/ - for (iport = 0; iport < num_output_port; iport++) { - /* We always initialize the lut_frac_level when there is only 1 output! - * It should be pointed the last level! - */ - if ((OPEN == output_port[iport]->lut_frac_level) - || (1 == num_output_port)) { - output_port[iport]->lut_frac_level = spice_mux_arch.num_level; - } - } - - /* Add Fracturable LUT outputs */ - - /* We have two types of naming rules in terms of the usage of MUXes: - * 1. MUXes, the naming rule is __size - * 2. LUTs, the naming rule is _mux_size - */ - num_conf_bits = count_num_sram_bits_one_spice_model(&spice_model, - mux_size); - num_mode_bits = count_num_mode_bits_one_spice_model(&spice_model); - /* Knock out the SRAM bits for the mode selection, they are separated dealed */ - num_conf_bits = num_conf_bits - num_mode_bits; - - if (SPICE_MODEL_LUT == spice_model.type) { - /* Special for LUT MUX*/ - fprintf(fp, "***** CMOS MUX info: spice_model_name= %s_MUX, size=%d *****\n", - spice_model.name, mux_size); - fprintf(fp, ".subckt %s_mux_size%d ", spice_model.name, mux_size); - /* Global ports */ - if (0 < rec_fprint_spice_model_global_ports(fp, &spice_model, FALSE)) { - fprintf(fp, "+ "); - } - /* Print input ports*/ - assert(mux_size == num_conf_bits); - for (ipin = 0; ipin < num_conf_bits; ipin++) { - fprintf(fp, "%s%d ", input_port[0]->prefix, ipin); - } - /* Print output ports*/ - for (iport = 0; iport < num_output_port; iport++) { - for (ipin = 0; ipin < output_port[iport]->size; ipin++) { - fprintf(fp, "%s%d ", output_port[iport]->prefix, ipin); - } - } - /* Print sram ports*/ - for (ipin = 0; ipin < input_port[0]->size; ipin++) { - fprintf(fp, "%s%d ", sram_port[0]->prefix, ipin); - fprintf(fp, "%s_inv%d ", sram_port[0]->prefix, ipin); - } - } else { - fprintf(fp, "***** CMOS MUX info: spice_model_name=%s, size=%d, structure: %s *****\n", - spice_model.name, mux_size, gen_str_spice_model_structure(spice_model.design_tech_info.mux_info->structure)); - fprintf(fp, ".subckt %s_size%d ", spice_model.name, mux_size); - /* Global ports */ - if (0 < rec_fprint_spice_model_global_ports(fp, &spice_model, FALSE)) { - fprintf(fp, "+ "); - } - /* Print input ports*/ - for (ipin = 0; ipin < mux_size; ipin++) { - fprintf(fp, "%s%d ", input_port[0]->prefix, ipin); - } - /* Print output ports*/ - fprintf(fp, "%s ", output_port[0]->prefix); - /* Print sram ports*/ - for (ipin = 0; ipin < num_conf_bits; ipin++) { - fprintf(fp, "%s%d ", sram_port[0]->prefix, ipin); - fprintf(fp, "%s_inv%d ", sram_port[0]->prefix, ipin); - } - } - /* Print local vdd and gnd*/ - fprintf(fp, "svdd sgnd"); - fprintf(fp, "\n"); - - /* Handle the corner case: input size = 2 */ - cur_mux_structure = spice_model.design_tech_info.mux_info->structure; - if (2 == spice_mux_arch.num_input) { - cur_mux_structure = SPICE_MODEL_STRUCTURE_ONELEVEL; - } - - /* Print internal architecture*/ - switch (cur_mux_structure) { - case SPICE_MODEL_STRUCTURE_TREE: - fprint_spice_cmos_mux_tree_structure(fp, mux_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); - break; - case SPICE_MODEL_STRUCTURE_ONELEVEL: - fprint_spice_cmos_mux_onelevel_structure(fp, mux_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); - break; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - fprint_spice_cmos_mux_multilevel_structure(fp, mux_basis_subckt_name, mux_special_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", - __FILE__, __LINE__, spice_model.name); - exit(1); - } - - /* To connect the input ports*/ - for (ipin = 0; ipin < mux_size; ipin++) { - if (1 == spice_model.input_buffer->exist) { - switch (spice_model.input_buffer->type) { - case SPICE_MODEL_BUF_INV: - /* Each inv: svdd sgnd size=param*/ - fprintf(fp, "Xinv%d ", ipin); /* Given name*/ - /* Global ports */ - if (0 < rec_fprint_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE)) { - fprintf(fp, "+ "); - } - fprintf(fp, "%s%d ", input_port[0]->prefix, ipin); /* input port */ - fprintf(fp, "mux2_l%d_in%d ", spice_mux_arch.input_level[ipin], spice_mux_arch.input_offset[ipin]); /* output port*/ - fprintf(fp, "svdd sgnd inv size=\'%s%s\'", spice_model.name, design_param_postfix_input_buf_size); /* subckt name */ - fprintf(fp, "\n"); - break; - case SPICE_MODEL_BUF_BUF: - /* TODO: what about tapered buffer, can we support? */ - /* Each buf: svdd sgnd size=param*/ - fprintf(fp, "Xbuf%d ", ipin); /* Given name*/ - /* Global ports */ - if (0 < rec_fprint_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE)) { - fprintf(fp, "+ "); - } - fprintf(fp, "%s%d ", input_port[0]->prefix, ipin); /* input port */ - fprintf(fp, "mux2_l%d_in%d ", spice_mux_arch.input_level[ipin], spice_mux_arch.input_offset[ipin]); /* output port*/ - fprintf(fp, "svdd sgnd buf size=\'%s%s\'", spice_model.name, design_param_postfix_input_buf_size); /* subckt name */ - fprintf(fp, "\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", - __FILE__, __LINE__); - exit(1); - } - } else { - /* There is no buffer, I create a zero resisitance between*/ - /* Resistance R 0*/ - fprintf(fp, "Rin%d %s%d mux2_l%d_in%d 0\n", - ipin, input_port[0]->prefix, ipin, spice_mux_arch.input_level[ipin], - spice_mux_arch.input_offset[ipin]); - } - } - /* Special: for the last inputs, we connect to VDD|GND - * TODO: create an option to select the connection VDD or GND - */ - if ((SPICE_MODEL_MUX == spice_model.type) - && (TRUE == spice_model.design_tech_info.mux_info->add_const_input)) { - assert ( (0 == spice_model.design_tech_info.mux_info->const_input_val) - || (1 == spice_model.design_tech_info.mux_info->const_input_val) ); - fprintf(fp, "Rin%d mux2_l%d_in%d %s 0\n", - spice_mux_arch.num_input - 1, - spice_mux_arch.input_level[spice_mux_arch.num_input - 1], - spice_mux_arch.input_offset[spice_mux_arch.num_input - 1], - convert_const_input_value_to_str(spice_model.design_tech_info.mux_info->const_input_val)); - } - - /* Output buffer*/ - for (iport = 0; iport < num_output_port; iport++) { - for (ipin = 0; ipin < output_port[iport]->size; ipin++) { - if (1 == spice_model.output_buffer->exist) { - /* Tapered buffer support */ - if (TRUE == spice_model.output_buffer->tapered_buf) { - /* Each buf: svdd sgnd size=param*/ - fprintf(fp, "Xbuf_out_%d_%d ", - iport, ipin); /* Given name*/ - /* Global ports */ - if (0 < rec_fprint_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE)) { - fprintf(fp, "+ "); - } - fprintf(fp, "mux2_l%d_in%d ", - spice_mux_arch.num_level - output_port[iport]->lut_frac_level, - output_port[iport]->lut_output_mask[ipin]); /* input port */ - fprintf(fp, "%s%d ", output_port[iport]->prefix, ipin); /* Output port*/ - fprintf(fp, "svdd sgnd tapbuf_level%d_f%d", - spice_model.output_buffer->tap_buf_level, spice_model.output_buffer->f_per_stage); /* subckt name */ - fprintf(fp, "\n"); - continue; - } - switch (spice_model.output_buffer->type) { - case SPICE_MODEL_BUF_INV: - if (TRUE == spice_model.output_buffer->tapered_buf) { - break; - } - /* Each inv: svdd sgnd size=param*/ - fprintf(fp, "Xinv_out_%d_%d ", iport, ipin); /* Given name*/ - /* Global ports */ - if (0 < rec_fprint_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE)) { - fprintf(fp, "+ "); - } - fprintf(fp, "mux2_l%d_in%d ", - spice_mux_arch.num_level - output_port[iport]->lut_frac_level, - output_port[iport]->lut_output_mask[ipin]); /* input port */ - fprintf(fp, "%s%d ", - output_port[iport]->prefix, ipin); /* Output port*/ - fprintf(fp, "svdd sgnd inv size=\'%s%s\'", spice_model.name, design_param_postfix_output_buf_size); /* subckt name */ - fprintf(fp, "\n"); - break; - case SPICE_MODEL_BUF_BUF: - if (TRUE == spice_model.output_buffer->tapered_buf) { - break; - } - /* Each buf: svdd sgnd size=param*/ - fprintf(fp, "Xbuf_out_%d_%d ", iport, ipin); /* Given name*/ - /* Global ports */ - if (0 < rec_fprint_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE)) { - fprintf(fp, "+ "); - } - fprintf(fp, "mux2_l%d_in%d ", - spice_mux_arch.num_level - output_port[iport]->lut_frac_level, - output_port[iport]->lut_output_mask[ipin]); /* input port */ - fprintf(fp, "%s%d ", output_port[iport]->prefix, ipin); /* Output port*/ - fprintf(fp, "svdd sgnd buf size=\'%s%s\'", spice_model.name, design_param_postfix_output_buf_size); /* subckt name */ - fprintf(fp, "\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", - __FILE__, __LINE__); - exit(1); - } - } else { - /* There is no buffer, I create a zero resisitance between*/ - /* Resistance R 0*/ - fprintf(fp, "Rout mux2_l%d_in%d %s%d 0\n", - spice_mux_arch.num_level - output_port[iport]->lut_frac_level, - output_port[iport]->lut_output_mask[ipin], - output_port[0]->prefix, ipin); - } - } - } - - fprintf(fp, ".eom\n"); - fprintf(fp, "***** END CMOS MUX info: spice_model_name=%s, size=%d *****\n", spice_model.name, mux_size); - fprintf(fp, "\n"); - - /* Free */ - my_free(mux_basis_subckt_name); - my_free(mux_special_basis_subckt_name); - my_free(input_port); - my_free(output_port); - my_free(sram_port); - - return; -} - -/* Print the RRAM MUX SPICE model. - * The internal structures of CMOS and RRAM MUXes are similar. - * This one can be merged to CMOS function. - * However I use another function, because in future the internal structure may change. - * We will suffer less software problems. - */ -void fprint_spice_mux_model_rram_subckt(FILE* fp, - int mux_size, - t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch) { - int i; - int num_input_port = 0; - int num_output_port = 0; - int num_sram_port = 0; - t_spice_model_port** input_port = NULL; - t_spice_model_port** output_port = NULL; - t_spice_model_port** sram_port = NULL; - int num_sram_bits = 0; - - enum e_spice_model_structure cur_mux_structure; - - /* Find the basis subckt*/ - char* mux_basis_subckt_name = NULL; - char* mux_special_basis_subckt_name = NULL; - /* Basis is always needed */ - mux_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model.name) + 5 - + strlen(my_itoa(mux_size)) - + strlen(mux_basis_posfix) + 1)); - sprintf(mux_basis_subckt_name, "%s_size%d%s", - spice_model.name, mux_size, mux_basis_posfix); - /* Special basis is on request, but anyway we prepare to call it.*/ - mux_special_basis_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model.name) + 5 - + strlen(my_itoa(mux_size)) - + strlen(mux_special_basis_posfix) + 1)); - sprintf(mux_basis_subckt_name, "%s_size%d%s", - spice_model.name, mux_size, mux_basis_posfix); - - /* Make sure we have a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* Ensure we have a RRAM MUX*/ - assert((SPICE_MODEL_MUX == spice_model.type)||(SPICE_MODEL_LUT == spice_model.type)); - assert(SPICE_MODEL_DESIGN_RRAM == spice_model.design_tech); - - /* Find the input port, output port, and sram port*/ - input_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - output_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - sram_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - - /* Asserts*/ - assert(1 == num_input_port); - assert(1 == num_output_port); - assert(1 == num_sram_port); - assert(1 == output_port[0]->size); - - /* We have two types of naming rules in terms of the usage of MUXes: - * 1. MUXes, the naming rule is __size - * 2. LUTs, the naming rule is _mux_size - */ - num_sram_bits = count_num_conf_bits_one_spice_model(&spice_model, - sram_spice_orgz_info->type, - mux_size); - - /* Print the definition of subckt*/ - if (SPICE_MODEL_LUT == spice_model.type) { - /* RRAM LUT is not supported now... */ - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])RRAM LUT is not supported!\n", - __FILE__, __LINE__); - exit(1); - /* Special for LUT MUX*/ - /* - fprintf(fp, "***** RRAM MUX info: spice_model_name= %s_MUX, size=%d *****\n", spice_model.name, mux_size); - fprintf(fp, ".subckt %s_mux_size%d ", spice_model.name, mux_size); - */ - } else { - fprintf(fp, "***** RRAM MUX info: spice_model_name=%s, size=%d, structure: %s *****\n", - spice_model.name, mux_size, gen_str_spice_model_structure(spice_model.design_tech_info.mux_info->structure)); - fprintf(fp, ".subckt %s_size%d ", spice_model.name, mux_size); - } - - /* Global ports */ - if (0 < rec_fprint_spice_model_global_ports(fp, &spice_model, FALSE)) { - fprintf(fp, "+ "); - } - - /* Print input ports*/ - for (i = 0; i < mux_size; i++) { - fprintf(fp, "%s%d ", input_port[0]->prefix, i); - } - /* Print output ports*/ - fprintf(fp, "%s ", output_port[0]->prefix); - /* Print sram ports*/ - for (i = 0; i < num_sram_bits; i++) { - fprintf(fp, "%s%d ", sram_port[0]->prefix, i); - fprintf(fp, "%s_inv%d ", sram_port[0]->prefix, i); - } - /* Print local vdd and gnd*/ - fprintf(fp, "svdd sgnd "); - fprintf(fp, "ron=\'%s%s\' roff=\'%s%s\' ", - spice_model.name, design_param_postfix_rram_ron, - spice_model.name, design_param_postfix_rram_roff); - fprintf(fp, "\n"); - - /* Print internal architecture*/ - /* Handle the corner case: input size = 2 */ - if (2 == mux_size) { - cur_mux_structure = SPICE_MODEL_STRUCTURE_ONELEVEL; - } else { - cur_mux_structure = spice_model.design_tech_info.mux_info->structure; - } - /* RRAM MUX is optimal in terms of area, delay and power for one-level structure. - * Hence, we do not support the multi-level or tree-like RRAM MUX. - */ - switch (cur_mux_structure) { - case SPICE_MODEL_STRUCTURE_TREE: - fprint_spice_rram_mux_tree_structure(fp, mux_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); - break; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - fprint_spice_rram_mux_multilevel_structure(fp, mux_basis_subckt_name, mux_special_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); - break; - case SPICE_MODEL_STRUCTURE_ONELEVEL: - fprint_spice_rram_mux_onelevel_structure(fp, mux_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", - __FILE__, __LINE__, spice_model.name); - exit(1); - } - - /* To connect the input ports*/ - for (i = 0; i < mux_size; i++) { - if (1 == spice_model.input_buffer->exist) { - switch (spice_model.input_buffer->type) { - case SPICE_MODEL_BUF_INV: - /* Each inv: svdd sgnd size=param*/ - fprintf(fp, "Xinv%d ", i); /* Given name*/ - fprintf(fp, "%s%d ", input_port[0]->prefix, i); /* input port */ - fprintf(fp, "mux2_l%d_in%d ", spice_mux_arch.input_level[i], spice_mux_arch.input_offset[i]); /* output port*/ - fprintf(fp, "svdd sgnd inv size=\'%s%s\'", spice_model.name, design_param_postfix_input_buf_size); /* subckt name */ - fprintf(fp, "\n"); - break; - case SPICE_MODEL_BUF_BUF: - /* TODO: what about tapered buffer, can we support? */ - /* Each buf: svdd sgnd size=param*/ - fprintf(fp, "Xbuf%d ", i); /* Given name*/ - fprintf(fp, "%s%d ", input_port[0]->prefix, i); /* input port */ - fprintf(fp, "mux2_l%d_in%d ", spice_mux_arch.input_level[i], spice_mux_arch.input_offset[i]); /* output port*/ - fprintf(fp, "svdd sgnd buf size=\'%s%s\'", spice_model.name, design_param_postfix_input_buf_size); /* subckt name */ - fprintf(fp, "\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", - __FILE__, __LINE__); - exit(1); - } - } else { - /* There is no buffer, I create a zero resisitance between*/ - /* Resistance R 0*/ - fprintf(fp, "Rin%d %s%d mux2_l%d_in%d 0\n", - i, input_port[0]->prefix, i, spice_mux_arch.input_level[i], - spice_mux_arch.input_offset[i]); - } - } - - /* Output buffer*/ - if (1 == spice_model.output_buffer->exist) { - switch (spice_model.output_buffer->type) { - case SPICE_MODEL_BUF_INV: - if (TRUE == spice_model.output_buffer->tapered_buf) { - break; - } - /* Each inv: svdd sgnd size=param*/ - fprintf(fp, "Xinv_out "); /* Given name*/ - fprintf(fp, "mux2_l%d_in%d ", 0, 0); /* input port */ - fprintf(fp, "%s ", output_port[0]->prefix); /* Output port*/ - fprintf(fp, "svdd sgnd inv size=\'%s%s\'", spice_model.name, design_param_postfix_output_buf_size); /* subckt name */ - fprintf(fp, "\n"); - break; - case SPICE_MODEL_BUF_BUF: - if (TRUE == spice_model.output_buffer->tapered_buf) { - break; - } - /* Each buf: svdd sgnd size=param*/ - fprintf(fp, "Xbuf_out "); /* Given name*/ - fprintf(fp, "mux2_l%d_in%d ", 0, 0); /* input port */ - fprintf(fp, "%s ", output_port[0]->prefix); /* Output port*/ - fprintf(fp, "svdd sgnd buf size=\'%s%s\'", spice_model.name, design_param_postfix_output_buf_size); /* subckt name */ - fprintf(fp, "\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", - __FILE__, __LINE__); - exit(1); - } - /* Tapered buffer support */ - if (TRUE == spice_model.output_buffer->tapered_buf) { - /* Each buf: svdd sgnd size=param*/ - fprintf(fp, "Xbuf_out "); /* Given name*/ - fprintf(fp, "mux2_l%d_in%d ", 0 , 0); /* input port */ - fprintf(fp, "%s ", output_port[0]->prefix); /* Output port*/ - fprintf(fp, "svdd sgnd tapbuf_level%d_f%d", - spice_model.output_buffer->tap_buf_level, spice_model.output_buffer->f_per_stage); /* subckt name */ - fprintf(fp, "\n"); - } - } else { - /* There is no buffer, I create a zero resisitance between*/ - /* Resistance R 0*/ - fprintf(fp, "Rout mux2_l0_in0 %s 0\n",output_port[0]->prefix); - } - - fprintf(fp, ".eom\n"); - fprintf(fp, "***** END RRAM MUX info: spice_model_name=%s, size=%d *****\n", spice_model.name, mux_size); - fprintf(fp, "\n"); - - /* Free */ - my_free(mux_basis_subckt_name); - my_free(input_port); - my_free(output_port); - my_free(sram_port); - - return; -} - -/* Print the SPICE model of a multiplexer subckt with given info */ -static -void fprint_spice_mux_model_subckt(FILE* fp, - t_spice_mux_model* spice_mux_model) { - /* Make sure we have a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); - exit(1); - } - /* Make sure we have a valid spice_model*/ - if (NULL == spice_mux_model) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid spice_mux_model!\n",__FILE__, __LINE__); - exit(1); - } - /* Make sure we have a valid spice_model*/ - if (NULL == spice_mux_model->spice_model) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid spice_model!\n",__FILE__, __LINE__); - exit(1); - } - - /* Check the mux size*/ - if (spice_mux_model->size < 2) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid MUX size(=%d)! Should be at least 2.\n", - __FILE__, __LINE__, spice_mux_model->size); - exit(1); - } - - /* Corner case: Error out MUX_SIZE = 2, automatcially give a one-level structure */ - /* - if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of SPICE model (%s) should be one-level because it is linked to a 2:1 MUX!\n", - __FILE__, __LINE__, spice_mux_model->spice_model->name); - exit(1); - } - */ - - /* Print the definition of subckt*/ - - /* Check the design technology*/ - switch (spice_mux_model->spice_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - fprint_spice_mux_model_cmos_subckt(fp, spice_mux_model->size, - *(spice_mux_model->spice_model), - *(spice_mux_model->spice_mux_arch)); - break; - case SPICE_MODEL_DESIGN_RRAM: - fprint_spice_mux_model_rram_subckt(fp, spice_mux_model->size, - *(spice_mux_model->spice_model), - *(spice_mux_model->spice_mux_arch)); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", - __FILE__, __LINE__, spice_mux_model->spice_model->name); - exit(1); - } - return; -} - - -/* We should count how many multiplexers with different sizes are needed */ -void generate_spice_muxes(char* subckt_dir, - int num_switch, - t_switch_inf* switches, - t_spice* spice, - t_det_routing_arch* routing_arch) { - /* We have linked list whichs stores spice model information of multiplexer*/ - t_llist* muxes_head = NULL; - t_llist* temp = NULL; - int mux_cnt = 0; - int max_mux_size = -1; - int min_mux_size = -1; - FILE* fp = NULL; - char* sp_name = my_strcat(subckt_dir,muxes_spice_file_name); - int num_input_ports = 0; - t_spice_model_port** input_ports = NULL; - int num_sram_ports = 0; - t_spice_model_port** sram_ports = NULL; - - int num_input_basis = 0; - t_spice_mux_model* cur_spice_mux_model = NULL; - - /* Alloc the muxes*/ - muxes_head = stats_spice_muxes(num_switch, switches, spice, routing_arch); - - /* Print the muxes netlist*/ - fp = fopen(sp_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create subckt SPICE netlist %s",__FILE__, __LINE__, sp_name); - exit(1); - } - /* Generate the descriptions*/ - fprint_spice_head(fp,"MUXes used in FPGA"); - - /* Print mux netlist one by one*/ - temp = muxes_head; - while(temp) { - assert(NULL != temp->dptr); - cur_spice_mux_model = (t_spice_mux_model*)(temp->dptr); - /* Bypass the spice models who has a user-defined subckt */ - if (NULL != cur_spice_mux_model->spice_model->model_netlist) { - input_ports = find_spice_model_ports(cur_spice_mux_model->spice_model, SPICE_MODEL_PORT_INPUT, &num_input_ports, TRUE); - sram_ports = find_spice_model_ports(cur_spice_mux_model->spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_ports, TRUE); - assert(0 != num_input_ports); - assert(0 != num_sram_ports); - /* Check the Input port size */ - if (cur_spice_mux_model->size != input_ports[0]->size) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])User-defined MUX SPICE MODEL(%s) size(%d) unmatch with the architecture needs(%d)!\n", - __FILE__, __LINE__, cur_spice_mux_model->spice_model->name, input_ports[0]->size,cur_spice_mux_model->size); - exit(1); - } - /* Check the SRAM port size */ - num_input_basis = determine_num_input_basis_multilevel_mux(cur_spice_mux_model->size, - cur_spice_mux_model->spice_model->design_tech_info.mux_info->mux_num_level); - if ((num_input_basis * cur_spice_mux_model->spice_model->design_tech_info.mux_info->mux_num_level) != sram_ports[0]->size) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])User-defined MUX SPICE MODEL(%s) SRAM size(%d) unmatch with the num of level(%d)!\n", - __FILE__, __LINE__, cur_spice_mux_model->spice_model->name, sram_ports[0]->size, - cur_spice_mux_model->spice_model->design_tech_info.mux_info->mux_num_level * num_input_basis); - exit(1); - } - /* Move on to the next*/ - temp = temp->next; - continue; - } - /* Let's have a N:1 MUX as basis*/ - fprint_spice_mux_model_basis_subckt(fp, cur_spice_mux_model); - /* Print the mux subckt */ - fprint_spice_mux_model_subckt(fp, cur_spice_mux_model); - /* Update the statistics*/ - mux_cnt++; - if ((-1 == max_mux_size)||(max_mux_size < cur_spice_mux_model->size)) { - max_mux_size = cur_spice_mux_model->size; - } - if ((-1 == min_mux_size)||(min_mux_size > cur_spice_mux_model->size)) { - min_mux_size = cur_spice_mux_model->size; - } - /* Move on to the next*/ - temp = temp->next; - } - - vpr_printf(TIO_MESSAGE_INFO,"Generated %d Multiplexer subckts.\n", - mux_cnt); - vpr_printf(TIO_MESSAGE_INFO,"Max. MUX size = %d.\t", - max_mux_size); - vpr_printf(TIO_MESSAGE_INFO,"Min. MUX size = %d.\n", - min_mux_size); - - - /* remember to free the linked list*/ - free_muxes_llist(muxes_head); - /* Free strings */ - free(sp_name); - - /* Close the file*/ - fclose(fp); - - return; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux.h deleted file mode 100644 index 1a4a431b3..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux.h +++ /dev/null @@ -1,10 +0,0 @@ - - - -void generate_spice_muxes(char* subckt_dir, - int num_switch, - t_switch_inf* switches, - t_spice* spice, - t_det_routing_arch* routing_arch); - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux_testbench.c deleted file mode 100644 index f28ba2ae1..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux_testbench.c +++ /dev/null @@ -1,1975 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_mux_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_backannotate_utils.h" -#include "spice_utils.h" -#include "spice_routing.h" -#include "spice_subckt.h" -#include "spice_mux_testbench.h" - -/** In this test bench. - * All the multiplexers (Local routing, Switch Boxes, Connection Blocks) in the FPGA are examined - * All the multiplexers are hanged with equivalent capactive loads in their context. - */ - -/* Global variables in this C-source file */ -static int testbench_mux_cnt = 0; -static int testbench_sram_cnt = 0; -static int testbench_load_cnt = 0; -static int testbench_pb_mux_cnt = 0; -static int testbench_cb_mux_cnt = 0; -static int testbench_sb_mux_cnt = 0; -static int num_segments; -static t_segment_inf* segments; -static t_llist* testbench_muxes_head = NULL; -static int upbound_sim_num_clock_cycles = 2; -static int max_sim_num_clock_cycles = 2; -static int auto_select_max_sim_num_clock_cycles = TRUE; - -static float total_pb_mux_input_density = 0.; -static float total_cb_mux_input_density = 0.; -static float total_sb_mux_input_density = 0.; - -/***** Local Subroutines Declaration *****/ - -/***** Local Subroutines *****/ -static void init_spice_mux_testbench_globals(t_spice spice) { - testbench_mux_cnt = 0; - testbench_sram_cnt = 0; - testbench_load_cnt = 0; - testbench_muxes_head = NULL; - testbench_pb_mux_cnt = 0; - testbench_cb_mux_cnt = 0; - testbench_sb_mux_cnt = 0; - auto_select_max_sim_num_clock_cycles = spice.spice_params.meas_params.auto_select_sim_num_clk_cycle; - upbound_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; - if (FALSE == auto_select_max_sim_num_clock_cycles) { - max_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; - } else { - max_sim_num_clock_cycles = 2; - } -} - -static -void fprint_spice_mux_testbench_global_ports(FILE* fp) { - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* Print generic global ports*/ - fprint_spice_generic_testbench_global_ports(fp, - sram_spice_orgz_info, - global_ports_head); - - return; -} - -static -void fprint_spice_mux_testbench_pb_mux_meas(FILE* fp, - char* meas_tag) { - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - - if (0 == testbench_pb_mux_cnt) { - fprintf(fp, ".meas tran sum_leakage_power_pb_mux[0to%d] \n", testbench_pb_mux_cnt); - fprintf(fp, "+ param=\'leakage_%s\'\n", meas_tag); - fprintf(fp, ".meas tran sum_energy_per_cycle_pb_mux[0to%d] \n", testbench_pb_mux_cnt); - fprintf(fp, "+ param=\'energy_per_cycle_%s\'\n", meas_tag); - } else { - fprintf(fp, ".meas tran sum_leakage_power_pb_mux[0to%d] \n", testbench_pb_mux_cnt); - fprintf(fp, "+ param=\'sum_leakage_power_pb_mux[0to%d]+leakage_%s\'\n", testbench_pb_mux_cnt-1, meas_tag); - fprintf(fp, ".meas tran sum_energy_per_cycle_pb_mux[0to%d] \n", testbench_pb_mux_cnt); - fprintf(fp, "+ param=\'sum_energy_per_cycle_pb_mux[0to%d]+energy_per_cycle_%s\'\n", testbench_pb_mux_cnt-1, meas_tag); - } - - /* Update the counter */ - testbench_pb_mux_cnt++; - - return; -} - -static -void fprint_spice_mux_testbench_cb_mux_meas(FILE* fp, - char* meas_tag) { - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - - if (0 == testbench_cb_mux_cnt) { - fprintf(fp, ".meas tran sum_leakage_power_cb_mux[0to%d] \n", testbench_cb_mux_cnt); - fprintf(fp, "+ param=\'leakage_%s\'\n", meas_tag); - fprintf(fp, ".meas tran sum_energy_per_cycle_cb_mux[0to%d] \n", testbench_cb_mux_cnt); - fprintf(fp, "+ param=\'energy_per_cycle_%s\'\n", meas_tag); - } else { - fprintf(fp, ".meas tran sum_leakage_power_cb_mux[0to%d] \n", testbench_cb_mux_cnt); - fprintf(fp, "+ param=\'sum_leakage_power_cb_mux[0to%d]+leakage_%s\'\n", testbench_cb_mux_cnt-1, meas_tag); - fprintf(fp, ".meas tran sum_energy_per_cycle_cb_mux[0to%d] \n", testbench_cb_mux_cnt); - fprintf(fp, "+ param=\'sum_energy_per_cycle_cb_mux[0to%d]+energy_per_cycle_%s\'\n", testbench_cb_mux_cnt-1, meas_tag); - } - - /* Update the counter */ - testbench_cb_mux_cnt++; - - return; -} - -static -void fprint_spice_mux_testbench_sb_mux_meas(FILE* fp, - char* meas_tag) { - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - - if (0 == testbench_sb_mux_cnt) { - fprintf(fp, ".meas tran sum_leakage_power_sb_mux[0to%d] \n", testbench_sb_mux_cnt); - fprintf(fp, "+ param=\'leakage_%s\'\n", meas_tag); - fprintf(fp, ".meas tran sum_energy_per_cycle_sb_mux[0to%d] \n", testbench_sb_mux_cnt); - fprintf(fp, "+ param=\'energy_per_cycle_%s\'\n", meas_tag); - } else { - fprintf(fp, ".meas tran sum_leakage_power_sb_mux[0to%d] \n", testbench_sb_mux_cnt); - fprintf(fp, "+ param=\'sum_leakage_power_sb_mux[0to%d]+leakage_%s\'\n", testbench_sb_mux_cnt-1, meas_tag); - fprintf(fp, ".meas tran sum_energy_per_cycle_sb_mux[0to%d] \n", testbench_sb_mux_cnt); - fprintf(fp, "+ param=\'sum_energy_per_cycle_sb_mux[0to%d]+energy_per_cycle_%s\'\n", testbench_sb_mux_cnt-1, meas_tag); - } - - /* Update the counter */ - testbench_sb_mux_cnt++; - - return; -} - - -static -void fprint_spice_mux_testbench_one_mux(FILE* fp, - char* meas_tag, - t_spice_model* mux_spice_model, - int mux_size, - int* input_init_value, - float* input_density, - float* input_probability, - int path_id) { - int inode, mux_level, ilevel, cur_num_sram; - int num_mux_sram_bits = 0; - int* mux_sram_bits = NULL; - t_llist* found_mux_node = NULL; - t_spice_mux_model* cur_mux = NULL; - int num_sim_clock_cycles = 0; - float average_density = 0.; - int avg_density_cnt = 0; - char* sram_vdd_port_name = NULL; - - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert(NULL != mux_spice_model); - assert((2 < mux_size)||(2 == mux_size)); - assert(NULL != input_density); - assert(NULL != input_probability); - - /* Add to linked list */ - check_and_add_mux_to_linked_list(&(testbench_muxes_head), mux_size, mux_spice_model); - found_mux_node = search_mux_linked_list(testbench_muxes_head, mux_size, mux_spice_model); - /* Check */ - assert(NULL != found_mux_node); - cur_mux = (t_spice_mux_model*)(found_mux_node->dptr); - assert(mux_spice_model == cur_mux->spice_model); - - /* Call the subckt that has already been defined before */ - fprintf(fp, "X%s_size%d[%d] ", mux_spice_model->prefix, mux_size, testbench_mux_cnt); - /* Global ports */ - if (0 < rec_fprint_spice_model_global_ports(fp, mux_spice_model, FALSE)) { - fprintf(fp, "+ "); - } - /* input port*/ - for (inode = 0; inode < mux_size; inode++) { - fprintf(fp, "%s_size%d[%d]->in[%d] ", - mux_spice_model->prefix, mux_size, testbench_mux_cnt, inode); - } - /* Output port */ - fprintf(fp, "%s_size%d[%d]->out ", - mux_spice_model->prefix, mux_size, testbench_mux_cnt); - - /* SRAMs */ - /* Print SRAM configurations, - * we should have a global SRAM vdd, AND it should be connected to a real sram subckt !!! - */ - /* Configuration bits for MUX*/ - switch (mux_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - decode_cmos_mux_sram_bits(mux_spice_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - case SPICE_MODEL_DESIGN_RRAM: - decode_rram_mux(mux_spice_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for spice model (%s)!\n", - __FILE__, __LINE__, mux_spice_model->name); - } - - /* Print SRAMs that configure this MUX */ - /* Get current counter of mem_bits, bl and wl */ - cur_num_sram = testbench_sram_cnt; - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - assert( (0 == mux_sram_bits[ilevel]) || (1 == mux_sram_bits[ilevel]) ); - fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, - cur_num_sram + ilevel, mux_sram_bits[ilevel]); - fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, - cur_num_sram + ilevel, 1 - mux_sram_bits[ilevel]); - } - - /* End with svdd and sgnd, subckt name*/ - /* Local vdd and gnd, we should have an independent VDD for all local interconnections*/ - fprintf(fp, "gvdd_%s_size%d[%d] 0 ", mux_spice_model->prefix, mux_size, testbench_mux_cnt); - /* End with spice_model name */ - fprintf(fp, "%s_size%d\n", mux_spice_model->name, mux_size); - - - /* Print the encoding in SPICE netlist for debugging */ - fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n", - testbench_mux_cnt, mux_level, path_id); - fprintf(fp, "*****"); - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - fprintf(fp, "%d", mux_sram_bits[ilevel]); - } - fprintf(fp, "*****\n"); - - /* Force SRAM bits */ - /* cur_num_sram = testbench_sram_cnt; */ - /* - for (ilevel = 0; ilevel < mux_level; ilevel++) { - fprintf(fp,"V%s[%d]->in %s[%d]->in 0 ", - sram_spice_model->prefix, cur_num_sram, sram_spice_model->prefix, cur_num_sram); - fprintf(fp, "0\n"); - cur_num_sram++; - } - */ - - /* Call SRAM subckts*/ - /* Give the VDD port name for SRAMs */ - sram_vdd_port_name = (char*)my_malloc(sizeof(char)* - (strlen(spice_tb_global_vdd_sram_port_name) - + 1 )); - sprintf(sram_vdd_port_name, "%s", - spice_tb_global_vdd_sram_port_name); - /* Now Print SRAMs one by one */ - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - fprint_spice_one_specific_sram_subckt(fp, sram_spice_orgz_info, mux_spice_model, - sram_vdd_port_name, testbench_sram_cnt); - testbench_sram_cnt++; - } - - /* Test bench : Add voltage sources */ - for (inode = 0; inode < mux_size; inode++) { - /* Print voltage source */ - fprintf(fp, "***** Signal %s_size%d[%d]->in[%d] density = %g, probability=%g.*****\n", - mux_spice_model->prefix, mux_size, testbench_mux_cnt, inode, input_density[inode], input_probability[inode]); - fprintf(fp, "V%s_size%d[%d]->in[%d] %s_size%d[%d]->in[%d] 0 \n", - mux_spice_model->prefix, mux_size, testbench_mux_cnt, inode, - mux_spice_model->prefix, mux_size, testbench_mux_cnt, inode); - fprint_voltage_pulse_params(fp, input_init_value[inode], input_density[inode], input_probability[inode]); - /* fprint_voltage_pulse_params(fp, input_init_value[inode], 1, 0.5); */ - } - /* global voltage supply */ - fprintf(fp, "Vgvdd_%s_size%d[%d] gvdd_%s_size%d[%d] 0 vsp\n", - mux_spice_model->prefix, mux_size, testbench_mux_cnt, - mux_spice_model->prefix, mux_size, testbench_mux_cnt); - - /* Calculate average density of this MUX */ - average_density = 0.; - avg_density_cnt = 0; - for (inode = 0; inode < mux_size; inode++) { - assert(!(0 > input_density[inode])); - if (0. < input_density[inode]) { - average_density += input_density[inode]; - avg_density_cnt++; - } - } - /* Calculate the num_sim_clock_cycle for this MUX, update global max_sim_clock_cycle in this testbench */ - if (0 < avg_density_cnt) { - average_density = average_density/avg_density_cnt; - num_sim_clock_cycles = (int)(1/average_density) + 1; - } else { - assert(0 == avg_density_cnt); - average_density = 0.; - num_sim_clock_cycles = 2; - } - if (TRUE == auto_select_max_sim_num_clock_cycles) { - /* for idle blocks, 2 clock cycle is well enough... */ - if (2 < num_sim_clock_cycles) { - num_sim_clock_cycles = upbound_sim_num_clock_cycles; - } else { - num_sim_clock_cycles = 2; - } - if (max_sim_num_clock_cycles < num_sim_clock_cycles) { - max_sim_num_clock_cycles = num_sim_clock_cycles; - } - } else { - num_sim_clock_cycles = max_sim_num_clock_cycles; - } - - /* Measurements */ - /* Measure the delay of MUX */ - fprintf(fp, "***** Measurements *****\n"); - /* Rise delay */ - fprintf(fp, "***** Rise delay *****\n"); - fprintf(fp, ".meas tran delay_rise_%s trig v(%s_size%d[%d]->in[%d]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'\n", meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, path_id); - fprintf(fp, "+ targ v(%s_size%d[%d]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'\n", - mux_spice_model->prefix, mux_size, testbench_mux_cnt); - /* Fall delay */ - fprintf(fp, "***** Fall delay *****\n"); - fprintf(fp, ".meas tran delay_fall_%s trig v(%s_size%d[%d]->in[%d]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'\n", meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, path_id); - fprintf(fp, "+ targ v(%s_size%d[%d]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'\n", - mux_spice_model->prefix, mux_size, testbench_mux_cnt); - /* Measure timing period of MUX switching */ - /* Rise */ - fprintf(fp, "***** Rise timing period *****\n"); - fprintf(fp, ".meas start_rise_%s when v(%s_size%d[%d]->in[%d])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'\n", - meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, path_id); - fprintf(fp, ".meas tran switch_rise_%s trig v(%s_size%d[%d]->in[%d]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'\n", meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, path_id); - fprintf(fp, "+ targ v(%s_size%d[%d]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'\n", - mux_spice_model->prefix, mux_size, testbench_mux_cnt); - /* Fall */ - fprintf(fp, "***** Fall timing period *****\n"); - fprintf(fp, ".meas start_fall_%s when v(%s_size%d[%d]->in[%d])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'\n", - meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, path_id); - fprintf(fp, ".meas tran switch_fall_%s trig v(%s_size%d[%d]->in[%d]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'\n", meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, path_id); - fprintf(fp, "+ targ v(%s_size%d[%d]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'\n", - mux_spice_model->prefix, mux_size, testbench_mux_cnt); - /* Measure the leakage power of MUX */ - fprintf(fp, "***** Leakage Power Measurement *****\n"); - fprintf(fp, ".meas tran %s_size%d[%d]_leakage_power avg p(Vgvdd_%s_size%d[%d]) from=0 to='clock_period'\n", - mux_spice_model->prefix, mux_size, testbench_mux_cnt, - mux_spice_model->prefix, mux_size, testbench_mux_cnt); - fprintf(fp, ".meas tran leakage_%s param='%s_size%d[%d]_leakage_power'\n", - meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt); - /* Measure the dynamic power of MUX */ - fprintf(fp, "***** Dynamic Power Measurement *****\n"); - fprintf(fp, ".meas tran %s_size%d[%d]_dynamic_power avg p(Vgvdd_%s_size%d[%d]) from='clock_period' to='%d*clock_period'\n", - mux_spice_model->prefix, mux_size, testbench_mux_cnt, - mux_spice_model->prefix, mux_size, testbench_mux_cnt, num_sim_clock_cycles); - fprintf(fp, ".meas tran %s_size%d[%d]_energy_per_cycle param='%s_size%d[%d]_dynamic_power*clock_period'\n", - mux_spice_model->prefix, mux_size, testbench_mux_cnt, - mux_spice_model->prefix, mux_size, testbench_mux_cnt); - /* Important: to give dynamic power measurement per toggle !!!! - * it is not fair to compare dynamic power when clock_period is different from designs to designs !!! - */ - fprintf(fp, ".meas tran dynamic_power_%s param='%s_size%d[%d]_dynamic_power'\n", - meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt); - fprintf(fp, ".meas tran energy_per_cycle_%s param='dynamic_power_%s*clock_period'\n", - meas_tag, meas_tag); - fprintf(fp, ".meas tran dynamic_rise_%s avg p(Vgvdd_%s_size%d[%d]) from='start_rise_%s' to='start_rise_%s+switch_rise_%s'\n", - meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, meas_tag, meas_tag, meas_tag); - fprintf(fp, ".meas tran dynamic_fall_%s avg p(Vgvdd_%s_size%d[%d]) from='start_fall_%s' to='start_fall_%s+switch_fall_%s'\n", - meas_tag, mux_spice_model->prefix, mux_size, testbench_mux_cnt, meas_tag, meas_tag, meas_tag); - /* - fprintf(fp, ".meas tran %s_size%d[%d]_dynamic_power param='(dynamic_rise_%s)*(%g*%d)'\n", - mux_spice_model->prefix, mux_size, testbench_mux_cnt, - meas_tag, input_density[path_id], sim_num_clock_cycle-1); - fprintf(fp, ".meas tran dynamic_%s param='(dynamic_rise_%s)*(%g*%d)'\n", - meas_tag, meas_tag, input_density[path_id], sim_num_clock_cycle-1); - */ - if (0 == testbench_mux_cnt) { - fprintf(fp, ".meas tran sum_leakage_power_mux[0to%d] \n", testbench_mux_cnt); - fprintf(fp, "+ param=\'leakage_%s\'\n", meas_tag); - fprintf(fp, ".meas tran sum_energy_per_cycle_mux[0to%d] \n", testbench_mux_cnt); - fprintf(fp, "+ param=\'energy_per_cycle_%s\'\n", meas_tag); - } else { - fprintf(fp, ".meas tran sum_leakage_power_mux[0to%d] \n", testbench_mux_cnt); - fprintf(fp, "+ param=\'sum_leakage_power_mux[0to%d]+leakage_%s\'\n", testbench_mux_cnt-1, meas_tag); - fprintf(fp, ".meas tran sum_energy_per_cycle_mux[0to%d] \n", testbench_mux_cnt); - fprintf(fp, "+ param=\'sum_energy_per_cycle_mux[0to%d]+energy_per_cycle_%s\'\n", testbench_mux_cnt-1, meas_tag); - } - - /* Free */ - my_free(mux_sram_bits); - my_free(sram_vdd_port_name); - - return; -} - -/** Print a mulitplexer testbench of a given pb pin - * --|---| - * --| M | - * ..| U |--- des_pb_graph_in - * --| X | - * --|---| - */ -static -void fprint_spice_mux_testbench_pb_graph_node_pin_mux(FILE* fp, - t_mode* cur_mode, - t_pb_graph_pin* des_pb_graph_pin, - t_interconnect* cur_interc, - int fan_in, - int select_edge, - int grid_x, int grid_y, - t_ivec*** LL_rr_node_indices) { - int cur_input = 0; - float* input_density = NULL; - float* input_probability = NULL; - int* input_init_value = NULL; - int iedge; - int* sram_bits = NULL; - char* meas_tag = NULL; - char* outport_name = NULL; - - float average_pb_mux_input_density = 0.; - - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - /* Check : - * MUX should have at least 2 fan_in - */ - assert((2 == fan_in)||(2 < fan_in)); - /* 2. spice_model is a wire */ - assert(NULL != cur_interc->spice_model); - assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); - - /* Test bench : Add voltage sources */ - cur_input = 0; - input_density = (float*)my_malloc(sizeof(float)*fan_in); - input_probability = (float*)my_malloc(sizeof(float)*fan_in); - input_init_value = (int*)my_malloc(sizeof(int)*fan_in); - for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - if (cur_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { - continue; - } - check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); - /* Find activity information */ - input_density[cur_input] = pb_pin_density(NULL, des_pb_graph_pin->input_edges[iedge]->input_pins[0]); - input_probability[cur_input] = pb_pin_probability(NULL, des_pb_graph_pin->input_edges[iedge]->input_pins[0]); - input_init_value[cur_input] = pb_pin_init_value(NULL, des_pb_graph_pin->input_edges[iedge]->input_pins[0]); - average_pb_mux_input_density += input_density[cur_input]; - cur_input++; - } - average_pb_mux_input_density = average_pb_mux_input_density/fan_in; - total_pb_mux_input_density += average_pb_mux_input_density; - /* Check fan-in number is correct */ - assert(fan_in == cur_input); - - /* Build a measurement tag: _[pin_index]_ */ - meas_tag = (char*)my_malloc(sizeof(char)* (10 + strlen(my_itoa(fan_in)) + strlen(my_itoa(testbench_mux_cnt)) + 2 - + strlen(des_pb_graph_pin->port->name) + 1 - + strlen(my_itoa(des_pb_graph_pin->pin_number)) + 2 - + strlen(cur_interc->name) + 1)); /* Add '0'*/ - sprintf(meas_tag, "idle_mux%d[%d]_%s[%d]_%s", - fan_in, testbench_mux_cnt, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number, cur_interc->name); - /* Print the main part of a single MUX testbench */ - fprint_spice_mux_testbench_one_mux(fp, meas_tag, cur_interc->spice_model, - fan_in, input_init_value, input_density, input_probability, select_edge); - - /* Test bench : Capactive load */ - /* TODO: Search all the fan-outs of des_pb_graph_pin */ - outport_name = (char*)my_malloc(sizeof(char)*( strlen(cur_interc->spice_model->prefix) + 5 - + strlen(my_itoa(fan_in)) + 1 + strlen(my_itoa(testbench_mux_cnt)) - + 7 )); - sprintf(outport_name, "%s_size%d[%d]->out", - cur_interc->spice_model->prefix, fan_in, testbench_mux_cnt); - - if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ - fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, - grid_x, grid_y, - des_pb_graph_pin, NULL, - outport_name, TRUE, - LL_rr_node_indices); - } - - fprint_spice_mux_testbench_pb_mux_meas(fp, meas_tag); - /* Update the counter */ - testbench_mux_cnt++; - - /* Free */ - my_free(sram_bits); - my_free(input_init_value); - my_free(input_density); - my_free(input_probability); - my_free(outport_name); - - return; -} - - -/** Print a mulitplexer testbench of a given pb pin - * --|---| - * --| M | - * ..| U |--- des_pb_graph_in - * --| X | - * --|---| - */ -static -void fprint_spice_mux_testbench_pb_pin_mux(FILE* fp, - t_rr_node* pb_rr_graph, - t_phy_pb* des_pb, - t_mode* cur_mode, - t_pb_graph_pin* des_pb_graph_pin, - t_interconnect* cur_interc, - int fan_in, - int select_edge, - int grid_x, int grid_y, - t_ivec*** LL_rr_node_indices) { - int cur_input = 0; - float* input_density = NULL; - float* input_probability = NULL; - int* input_init_value = NULL; - int iedge; - int* sram_bits = NULL; - char* meas_tag = NULL; - char* outport_name = NULL; - float average_pb_mux_input_density = 0.; - - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - /* Check : - * MUX should have at least 2 fan_in - */ - assert((2 == fan_in)||(2 < fan_in)); - /* 2. spice_model is a wire */ - assert(NULL != cur_interc->spice_model); - assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); - - /* Test bench : Add voltage sources */ - cur_input = 0; - input_density = (float*)my_malloc(sizeof(float)*fan_in); - input_probability = (float*)my_malloc(sizeof(float)*fan_in); - input_init_value = (int*)my_malloc(sizeof(int)*fan_in); - for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - if (cur_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { - continue; - } - check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); - /* Find activity information */ - input_density[cur_input] = pb_pin_density(pb_rr_graph, des_pb_graph_pin->input_edges[iedge]->input_pins[0]); - input_probability[cur_input] = pb_pin_probability(pb_rr_graph, des_pb_graph_pin->input_edges[iedge]->input_pins[0]); - input_init_value[cur_input] = pb_pin_init_value(pb_rr_graph, des_pb_graph_pin->input_edges[iedge]->input_pins[0]); - average_pb_mux_input_density += input_density[cur_input]; - cur_input++; - } - average_pb_mux_input_density = average_pb_mux_input_density/fan_in; - total_pb_mux_input_density += average_pb_mux_input_density; - /* Check fan-in number is correct */ - assert(fan_in == cur_input); - - /* Build a measurement tag: _[pin_index]_ */ - meas_tag = (char*)my_malloc(sizeof(char)* (strlen(des_pb->spice_name_tag) + 1 - + strlen(des_pb_graph_pin->port->name) + 1 - + strlen(my_itoa(des_pb_graph_pin->pin_number)) + 2 - + strlen(cur_interc->name) + 1)); /* Add '0'*/ - sprintf(meas_tag, "%s_%s[%d]_%s", - des_pb->spice_name_tag, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number, cur_interc->name); - /* Print the main part of a single MUX testbench */ - fprint_spice_mux_testbench_one_mux(fp, meas_tag, cur_interc->spice_model, - fan_in, input_init_value, input_density, input_probability, select_edge); - - /* Test bench : Capactive load */ - /* Search all the fan-outs of des_pb_graph_pin */ - outport_name = (char*)my_malloc(sizeof(char)*( strlen(cur_interc->spice_model->prefix) + 5 - + strlen(my_itoa(fan_in)) + 1 + strlen(my_itoa(testbench_mux_cnt)) - + 7 )); - sprintf(outport_name, "%s_size%d[%d]->out", - cur_interc->spice_model->prefix, fan_in, testbench_mux_cnt); - - if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ - fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, - grid_x, grid_y, - des_pb_graph_pin, des_pb, - outport_name, TRUE, - LL_rr_node_indices); - } - - fprint_spice_mux_testbench_pb_mux_meas(fp, meas_tag); - - /* Update the counter */ - testbench_mux_cnt++; - - /* Free */ - my_free(sram_bits); - my_free(input_init_value); - my_free(input_density); - my_free(input_probability); - my_free(outport_name); - - return; -} - -static -void fprint_spice_mux_testbench_pb_graph_node_pin_interc(FILE* fp, - t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode, - int select_path_id, - int grid_x, int grid_y, - t_ivec*** LL_rr_node_indices) { - int fan_in; - int iedge; - t_interconnect* cur_interc = NULL; - enum e_interconnect spice_interc_type; - - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* 1. identify pin interconnection type, - * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) - * 3. Select and print the SPICE netlist - */ - fan_in = 0; - cur_interc = NULL; - /* Search the input edges only, stats on the size of MUX we may need (fan-in) */ - for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - /* 1. First, we should make sure this interconnect is in the selected mode!!!*/ - if (cur_mode == des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { - /* Check this edge*/ - check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); - /* Record the interconnection*/ - if (NULL == cur_interc) { - cur_interc = des_pb_graph_pin->input_edges[iedge]->interconnect; - } else { /* Make sure the interconnections for this pin is the same!*/ - assert(cur_interc == des_pb_graph_pin->input_edges[iedge]->interconnect); - } - /* Search the input_pins of input_edges only*/ - fan_in += des_pb_graph_pin->input_edges[iedge]->num_input_pins; - } - } - if (NULL == cur_interc) { - /* No interconnection matched */ - return; - } - /* Initialize the interconnection type that will be implemented in SPICE netlist*/ - switch (cur_interc->type) { - case DIRECT_INTERC: - assert(1 == fan_in); - spice_interc_type = DIRECT_INTERC; - break; - case COMPLETE_INTERC: - if (1 == fan_in) { - spice_interc_type = DIRECT_INTERC; - } else { - assert((2 == fan_in)||(2 < fan_in)); - spice_interc_type = MUX_INTERC; - } - break; - case MUX_INTERC: - assert((2 == fan_in)||(2 < fan_in)); - spice_interc_type = MUX_INTERC; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", - __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); - exit(1); - } - - /* Print all the multiplexers at current level */ - switch (spice_interc_type) { - case DIRECT_INTERC: - break; - case MUX_INTERC: - assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); - fprint_spice_mux_testbench_pb_graph_node_pin_mux(fp, cur_mode, des_pb_graph_pin, - cur_interc, fan_in, - select_path_id, - grid_x, grid_y, - LL_rr_node_indices); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid interconnection type!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - - -static -void fprint_spice_mux_testbench_pb_pin_interc(FILE* fp, - t_rr_node* pb_rr_graph, - t_phy_pb* des_pb, - t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode, - int select_path_id, - int grid_x, int grid_y, - t_ivec*** LL_rr_node_indices) { - int fan_in; - int iedge; - t_interconnect* cur_interc = NULL; - enum e_interconnect spice_interc_type; - - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* 1. identify pin interconnection type, - * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) - * 3. Select and print the SPICE netlist - */ - fan_in = 0; - cur_interc = NULL; - /* Search the input edges only, stats on the size of MUX we may need (fan-in) */ - for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - /* 1. First, we should make sure this interconnect is in the selected mode!!!*/ - if (cur_mode == des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { - /* Check this edge*/ - check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); - /* Record the interconnection*/ - if (NULL == cur_interc) { - cur_interc = des_pb_graph_pin->input_edges[iedge]->interconnect; - } else { /* Make sure the interconnections for this pin is the same!*/ - assert(cur_interc == des_pb_graph_pin->input_edges[iedge]->interconnect); - } - /* Search the input_pins of input_edges only*/ - fan_in += des_pb_graph_pin->input_edges[iedge]->num_input_pins; - } - } - if (NULL == cur_interc) { - /* No interconnection matched */ - return; - } - /* Initialize the interconnection type that will be implemented in SPICE netlist*/ - switch (cur_interc->type) { - case DIRECT_INTERC: - assert(1 == fan_in); - spice_interc_type = DIRECT_INTERC; - break; - case COMPLETE_INTERC: - if (1 == fan_in) { - spice_interc_type = DIRECT_INTERC; - } else { - assert((2 == fan_in)||(2 < fan_in)); - spice_interc_type = MUX_INTERC; - } - break; - case MUX_INTERC: - assert((2 == fan_in)||(2 < fan_in)); - spice_interc_type = MUX_INTERC; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", - __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); - exit(1); - } - - /* Print all the multiplexers at current level */ - switch (spice_interc_type) { - case DIRECT_INTERC: - break; - case MUX_INTERC: - assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); - fprint_spice_mux_testbench_pb_pin_mux(fp, - pb_rr_graph, des_pb, - cur_mode, des_pb_graph_pin, - cur_interc, fan_in, select_path_id, - grid_x, grid_y, - LL_rr_node_indices); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid interconnection type!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -/* Print the SPICE interconnections of a port defined in pb_graph */ -static -void fprintf_spice_mux_testbench_pb_graph_port_interc(FILE* fp, - t_pb_graph_node* cur_pb_graph_node, - t_phy_pb* cur_pb, - enum e_spice_pb_port_type pb_port_type, - t_mode* cur_mode, - int is_idle, - int grid_x, int grid_y, - t_ivec*** LL_rr_node_indices) { - int iport, ipin; - int node_index = -1; - int prev_node = -1; - /* int prev_edge = -1; */ - int path_id = -1; - t_rr_node* pb_rr_nodes = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - switch (pb_port_type) { - case SPICE_PB_PORT_INPUT: - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - /* If this is a idle block, we set 0 to the selected edge*/ - if (is_idle) { - assert(NULL == cur_pb); - path_id = DEFAULT_PATH_ID; - fprint_spice_mux_testbench_pb_graph_node_pin_interc(fp, - &(cur_pb_graph_node->input_pins[iport][ipin]), - cur_mode, - path_id, - grid_x, grid_y, - LL_rr_node_indices); - } else { - /* Get the selected edge of current pin*/ - assert(NULL != cur_pb); - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = cur_pb_graph_node->input_pins[iport][ipin].rr_node_index_physical_pb; - prev_node = pb_rr_nodes[node_index].prev_node; - /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ - /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ - if (OPEN == prev_node) { - path_id = DEFAULT_PATH_ID; // - } else { - /* Find the path_id */ - path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); - assert(DEFAULT_PATH_ID != path_id); - } - fprint_spice_mux_testbench_pb_pin_interc(fp, pb_rr_nodes, cur_pb, /* TODO: find out the child_pb*/ - &(cur_pb_graph_node->input_pins[iport][ipin]), - cur_mode, - path_id, - grid_x, grid_y, - LL_rr_node_indices); - } - } - } - break; - case SPICE_PB_PORT_OUTPUT: - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - /* If this is a idle block, we set 0 to the selected edge*/ - if (is_idle) { - assert(NULL == cur_pb); - path_id = DEFAULT_PATH_ID; - fprint_spice_mux_testbench_pb_graph_node_pin_interc(fp, - &(cur_pb_graph_node->output_pins[iport][ipin]), - cur_mode, - path_id, - grid_x, grid_y, - LL_rr_node_indices); - } else { - /* Get the selected edge of current pin*/ - assert(NULL != cur_pb); - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = cur_pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; - prev_node = pb_rr_nodes[node_index].prev_node; - /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ - /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ - if (OPEN == prev_node) { - path_id = DEFAULT_PATH_ID; // - } else { - /* Find the path_id */ - path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); - assert(DEFAULT_PATH_ID != path_id); - } - fprint_spice_mux_testbench_pb_pin_interc(fp, pb_rr_nodes, cur_pb, /* TODO: find out the child_pb*/ - &(cur_pb_graph_node->output_pins[iport][ipin]), - cur_mode, - path_id, - grid_x, grid_y, - LL_rr_node_indices); - } - } - } - break; - case SPICE_PB_PORT_CLOCK: - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - /* If this is a idle block, we set 0 to the selected edge*/ - if (is_idle) { - assert(NULL == cur_pb); - path_id = DEFAULT_PATH_ID; - fprint_spice_mux_testbench_pb_graph_node_pin_interc(fp, - &(cur_pb_graph_node->clock_pins[iport][ipin]), - cur_mode, - path_id, - grid_x, grid_y, - LL_rr_node_indices); - } else { - /* Get the selected edge of current pin*/ - assert(NULL != cur_pb); - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = cur_pb_graph_node->clock_pins[iport][ipin].rr_node_index_physical_pb; - prev_node = pb_rr_nodes[node_index].prev_node; - /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ - /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ - if (OPEN == prev_node) { - path_id = DEFAULT_PATH_ID; // - } else { - /* Find the path_id */ - path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); - assert(DEFAULT_PATH_ID != path_id); - } - fprint_spice_mux_testbench_pb_pin_interc(fp, pb_rr_nodes, cur_pb, /* TODO: find out the child_pb*/ - &(cur_pb_graph_node->clock_pins[iport][ipin]), - cur_mode, - path_id, - grid_x, grid_y, - LL_rr_node_indices); - } - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pb port type!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -/* For each pb, we search the input pins and output pins for local interconnections */ -static -void fprint_spice_mux_testbench_pb_interc(FILE* fp, - t_phy_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - int grid_x, int grid_y, - t_ivec*** LL_rr_node_indices) { - int ipb, jpb; - t_pb_type* cur_pb_type = NULL; - t_mode* cur_mode = NULL; - t_pb_graph_node* child_pb_graph_node = NULL; - t_phy_pb* child_pb = NULL; - int select_mode_index = -1; - int is_child_pb_idle = -1; - int is_idle = 0; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - if (NULL == cur_pb) { - assert(NULL != cur_pb_graph_node); - select_mode_index = find_pb_type_physical_mode_index(*(cur_pb_graph_node->pb_type)); - is_idle = 1; - } else { - assert (cur_pb_graph_node == cur_pb->pb_graph_node); - select_mode_index = cur_pb->mode; - is_idle = 0; - } - cur_pb_type = cur_pb_graph_node->pb_type; - assert(NULL != cur_pb_type); - cur_mode = &(cur_pb_type->modes[select_mode_index]); - assert(NULL != cur_mode); - - /* We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins - * /|\ - * | - * input_pins, edges, output_pins - */ - fprintf_spice_mux_testbench_pb_graph_port_interc(fp, - cur_pb_graph_node, - cur_pb, - SPICE_PB_PORT_OUTPUT, - cur_mode, - is_idle, - grid_x, grid_y, - LL_rr_node_indices); - - - /* We check input_pins of child_pb_graph_node and its the input_edges - * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node - * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins - * /|\ - * | - * input_pins, edges, output_pins - */ - for (ipb = 0; ipb < cur_pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { - child_pb_graph_node = &(cur_pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]); - if (NULL == cur_pb) { - child_pb = NULL; - } else { - child_pb = &(cur_pb->child_pbs[ipb][jpb]); - /* Check if child_pb is empty */ - if (NULL == child_pb->name) { - is_child_pb_idle = 1; - child_pb = NULL; - } else { - is_child_pb_idle = 0; - } - } - /* For each child_pb_graph_node input pins*/ - fprintf_spice_mux_testbench_pb_graph_port_interc(fp, - child_pb_graph_node, - child_pb, - SPICE_PB_PORT_INPUT, - cur_mode, - is_child_pb_idle, - grid_x, grid_y, - LL_rr_node_indices); - /* TODO: for clock pins, we should do the same work */ - fprintf_spice_mux_testbench_pb_graph_port_interc(fp, - child_pb_graph_node, - child_pb, - SPICE_PB_PORT_CLOCK, - cur_mode, - is_child_pb_idle, - grid_x, grid_y, - LL_rr_node_indices); - } - } - - return; -} - -static -void fprint_spice_mux_testbench_pb_muxes_rec(FILE* fp, - t_phy_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - int grid_x, int grid_y, - t_ivec*** LL_rr_node_indices) { - int ipb, jpb; - int mode_index; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - if (NULL == cur_pb) { - assert(NULL != cur_pb_graph_node); - } else { - assert (cur_pb_graph_node == cur_pb->pb_graph_node); - } - - - /* If we touch the leaf, there is no need print interc*/ - if (FALSE == is_primitive_pb_type(cur_pb_graph_node->pb_type)) { - /* Print MUX interc at current-level pb*/ - fprint_spice_mux_testbench_pb_interc(fp, - cur_pb, - cur_pb_graph_node, - grid_x, grid_y, - LL_rr_node_indices); - } else { - return; - } - - /* Go recursively ... */ - if (NULL == cur_pb) { - mode_index = find_pb_type_physical_mode_index(*(cur_pb_graph_node->pb_type)); - } else { - mode_index = cur_pb->mode; - } - for (ipb = 0; ipb < cur_pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - if (((NULL == cur_pb) - || ((NULL == cur_pb->child_pbs[ipb])||(NULL == cur_pb->child_pbs[ipb][jpb].name)))) { - /* Print idle muxes */ - fprint_spice_mux_testbench_pb_muxes_rec(fp, - NULL, - &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), - grid_x, grid_y, - LL_rr_node_indices); - } else { - /* Refer to pack/output_clustering.c [LINE 392] */ - assert ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)); - fprint_spice_mux_testbench_pb_muxes_rec(fp, - &(cur_pb->child_pbs[ipb][jpb]), - cur_pb->child_pbs[ipb][jpb].pb_graph_node, - grid_x, grid_y, - LL_rr_node_indices); - } - } - } - - return; -} - - -static -void fprint_spice_mux_testbench_cb_one_mux(FILE* fp, - t_cb cur_cb_info, - t_rr_node* src_rr_node, - t_ivec*** LL_rr_node_indices) { - int mux_size, cb_x, cb_y; - int inode, path_id, switch_index; - t_rr_node** drive_rr_nodes = NULL; - t_spice_model* mux_spice_model = NULL; - int* mux_sram_bits = NULL; - float* input_density = NULL; - float* input_probability = NULL; - int* input_init_value = NULL; - char* meas_tag = NULL; - char* outport_name = NULL; - float average_cb_mux_input_density = 0.; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check */ - assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); - assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); - - cb_x = cur_cb_info.x; - cb_y = cur_cb_info.y; - - assert(IPIN == src_rr_node->type); - - /* Find drive_rr_nodes*/ - mux_size = src_rr_node->num_drive_rr_nodes; - assert(mux_size == src_rr_node->fan_in); - drive_rr_nodes = src_rr_node->drive_rr_nodes; - - /* Find path_id */ - path_id = DEFAULT_PATH_ID; - for (inode = 0; inode < mux_size; inode++) { - if (drive_rr_nodes[inode] == &(rr_node[src_rr_node->prev_node])) { - path_id = inode; - break; - } - } - - switch_index = src_rr_node->drive_switches[DEFAULT_SWITCH_ID]; - - mux_spice_model = switch_inf[switch_index].spice_model; - - /* Check : - * MUX should have at least 2 fan_in - */ - assert((2 == mux_size)||(2 < mux_size)); - /* 2. spice_model is a wire */ - assert(SPICE_MODEL_MUX == mux_spice_model->type); - - input_density = (float*)my_malloc(sizeof(float)*mux_size); - input_probability = (float*)my_malloc(sizeof(float)*mux_size); - input_init_value = (int*)my_malloc(sizeof(int)*mux_size); - for (inode = 0; inode < mux_size; inode++) { - /* Find activity information */ - input_density[inode] = get_rr_node_net_density(*(drive_rr_nodes[inode])); - input_probability[inode] = get_rr_node_net_probability(*(drive_rr_nodes[inode])); - input_init_value[inode] = get_rr_node_net_init_value(*(drive_rr_nodes[inode])); - average_cb_mux_input_density += input_density[inode]; - } - average_cb_mux_input_density = average_cb_mux_input_density/mux_size; - total_cb_mux_input_density += average_cb_mux_input_density; - - /* Build meas_tag: cb_mux[cb_x][cb_y]_rrnode[node]*/ - meas_tag = (char*)my_malloc(sizeof(char)*(7 + strlen(my_itoa(cb_x)) + 2 - + strlen(my_itoa(cb_y)) + 9 - + strlen(my_itoa(src_rr_node-rr_node)) + 2)); /* Add '0'*/ - sprintf(meas_tag, "cb_mux[%d][%d]_rrnode[%ld]", cb_x, cb_y, src_rr_node-rr_node); - /* Print the main part of a single MUX testbench */ - fprint_spice_mux_testbench_one_mux(fp, meas_tag, - mux_spice_model, src_rr_node->fan_in, - input_init_value, input_density, - input_probability, path_id); - - /* Generate loads */ - outport_name = (char*)my_malloc(sizeof(char)*( strlen(mux_spice_model->prefix) + 5 - + strlen(my_itoa(mux_size)) + 1 + strlen(my_itoa(testbench_mux_cnt)) - + 7 )); - sprintf(outport_name, "%s_size%d[%d]->out", - mux_spice_model->prefix, - mux_size, - testbench_mux_cnt); - - if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ - fprint_spice_testbench_one_cb_mux_loads(fp, &testbench_load_cnt, src_rr_node, - outport_name, LL_rr_node_indices); - } - - fprint_spice_mux_testbench_cb_mux_meas(fp, meas_tag); - /* Update the counter */ - testbench_mux_cnt++; - - /* Free */ - my_free(mux_sram_bits); - my_free(input_init_value); - my_free(input_density); - my_free(input_probability); - - return; -} - -static -void fprint_spice_mux_testbench_cb_interc(FILE* fp, - t_cb cur_cb_info, - t_rr_node* src_rr_node, - t_ivec*** LL_rr_node_indices) { - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); - assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); - - assert(NULL != src_rr_node); - - /* Skip non-mapped CB MUX */ - if (OPEN == src_rr_node->net_num) { - //return; - } - - assert((0 < src_rr_node->fan_in)||(0 == src_rr_node->fan_in)); - if (1 == src_rr_node->fan_in) { - /* By-pass a direct connection*/ - return; - } else if ((2 < src_rr_node->fan_in)||(2 == src_rr_node->fan_in)) { - /* Print a MUX */ - fprint_spice_mux_testbench_cb_one_mux(fp, - cur_cb_info, - src_rr_node, - LL_rr_node_indices); - } - - return; -} - - -/* Assume each connection box has a regional power-on/off switch */ -static -int fprint_spice_mux_testbench_call_one_grid_cb_muxes(FILE* fp, - t_cb cur_cb_info, - t_ivec*** LL_rr_node_indices) { - int inode, side; - int side_cnt = 0; - int used = 0; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check */ - assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); - assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); - - side_cnt = 0; - used = 0; - /* Print the ports of grids*/ - /* only check ipin_rr_nodes of cur_cb_info */ - for (side = 0; side < cur_cb_info.num_sides; side++) { - /* Bypass side with zero IPINs*/ - if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { - continue; - } - side_cnt++; - assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); - assert(NULL != cur_cb_info.ipin_rr_node[side]); - for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { - /* Print multiplexers */ - /* Check if there is at least one rr_node with a net_name*/ - if (OPEN != cur_cb_info.ipin_rr_node[side][inode]->net_num) { - used = 1; - } - fprint_spice_mux_testbench_cb_interc(fp, cur_cb_info, - cur_cb_info.ipin_rr_node[side][inode], - LL_rr_node_indices); - } - } - /* Make sure only 2 sides of IPINs are printed */ - assert((1 == side_cnt)||(2 == side_cnt)); - - /* Free */ - - return used; -} - -static -int fprint_spice_mux_testbench_sb_one_mux(FILE* fp, - t_sb cur_sb_info, - int chan_side, - t_rr_node* src_rr_node) { - int inode, switch_index, mux_size; - t_spice_model* mux_spice_model = NULL; - float* input_density = NULL; - float* input_probability = NULL; - int* input_init_value = NULL; - int path_id = -1; - char* meas_tag = NULL; - int num_drive_rr_nodes = 0; - t_rr_node** drive_rr_nodes = NULL; - char* outport_name = NULL; - char* rr_node_outport_name = NULL; - int used = 0; - - float average_sb_mux_input_density = 0.; - - int switch_box_x, switch_box_y; - - switch_box_x = cur_sb_info.x; - switch_box_y = cur_sb_info.y; - - /* Check */ - assert((!(0 > switch_box_x))&&(!(switch_box_x > (nx + 1)))); - assert((!(0 > switch_box_y))&&(!(switch_box_y > (ny + 1)))); - - if (NULL == src_rr_node) { - return 0; - } - - /* ignore idle sb mux - if (OPEN == src_rr_node->net_num) { - return used; - } - */ - - /* Determine if the interc lies inside a channel wire, that is interc between segments */ - /* Check each num_drive_rr_nodes, see if they appear in the cur_sb_info */ - if (TRUE == check_drive_rr_node_imply_short(cur_sb_info, src_rr_node, chan_side)) { - /* Double check if the interc lies inside a channel wire, that is interc between segments */ - assert(1 == is_rr_node_exist_opposite_side_in_sb_info(cur_sb_info, src_rr_node, chan_side)); - num_drive_rr_nodes = 0; - drive_rr_nodes = NULL; - } else { - num_drive_rr_nodes = src_rr_node->num_drive_rr_nodes; - drive_rr_nodes = src_rr_node->drive_rr_nodes; - switch_index = src_rr_node->drive_switches[DEFAULT_SWITCH_ID]; - } - - /* Print MUX only when fan-in >= 2 */ - if (2 > num_drive_rr_nodes) { - return used; - } - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Find mux_spice_model, mux_size */ - mux_size = num_drive_rr_nodes; - - mux_spice_model = switch_inf[switch_index].spice_model; - assert(NULL != mux_spice_model); - assert(SPICE_MODEL_MUX == mux_spice_model->type); - - /* input_density, input_probability */ - input_density = (float*)my_malloc(sizeof(float)*mux_size); - input_probability = (float*)my_malloc(sizeof(float)*mux_size); - input_init_value = (int*)my_malloc(sizeof(int)*mux_size); - for (inode = 0; inode < mux_size; inode++) { - input_density[inode] = get_rr_node_net_density(*(drive_rr_nodes[inode])); - input_probability[inode] = get_rr_node_net_probability(*(drive_rr_nodes[inode])); - input_init_value[inode] = get_rr_node_net_init_value(*(drive_rr_nodes[inode])); - average_sb_mux_input_density += input_density[inode]; - } - average_sb_mux_input_density = average_sb_mux_input_density/mux_size; - total_sb_mux_input_density += average_sb_mux_input_density; - - /* Find path_id */ - path_id = DEFAULT_PATH_ID; - for (inode = 0; inode < mux_size; inode++) { - if (drive_rr_nodes[inode] == &(rr_node[src_rr_node->prev_node])) { - path_id = inode; - break; - } - } - - /* Build meas_tag: sb_mux[sb_x][sb_y]_rrnode[node]*/ - meas_tag = (char*)my_malloc(sizeof(char)*(7 + strlen(my_itoa(switch_box_x)) + 2 - + strlen(my_itoa(switch_box_y)) + 9 - + strlen(my_itoa(src_rr_node-rr_node)) + 2)); /* Add '0'*/ - sprintf(meas_tag, "sb_mux[%d][%d]_rrnode[%ld]", switch_box_x, switch_box_y, src_rr_node-rr_node); - /* Print MUX */ - fprint_spice_mux_testbench_one_mux(fp, meas_tag, - mux_spice_model, mux_size, - input_init_value, input_density, - input_probability, path_id); - - /* Print a channel wire !*/ - outport_name = (char*)my_malloc(sizeof(char)*( strlen(mux_spice_model->prefix) - + 5 + strlen(my_itoa(mux_size)) + 1 - + strlen(my_itoa(testbench_mux_cnt)) - + 6 + 1 )); - sprintf(outport_name, "%s_size%d[%d]->out", mux_spice_model->prefix, mux_size, testbench_mux_cnt); - - if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ - fprintf(fp, "***** Load for rr_node[%ld] *****\n", src_rr_node - rr_node); - rr_node_outport_name = fprint_spice_testbench_rr_node_load_version(fp, - &testbench_load_cnt, - num_segments, - segments, - 0, /* load size */ - (*src_rr_node), - outport_name); - } - - fprint_spice_mux_testbench_sb_mux_meas(fp, meas_tag); - - /* Update the counter */ - testbench_mux_cnt++; - - /* Free */ - my_free(input_init_value); - my_free(input_density); - my_free(input_probability); - my_free(rr_node_outport_name); - - return 1; -} - - -static -int fprint_spice_mux_testbench_call_one_grid_sb_muxes(FILE* fp, - t_sb cur_sb_info) { - int itrack, side; - int used = 0; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check */ - assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); - assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); - - - /* print all the rr_nodes in the switch boxes if there is at least one rr_node with a net_num */ - used = 0; - for (side = 0; side < cur_sb_info.num_sides; side++) { - for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { - switch (cur_sb_info.chan_rr_node_direction[side][itrack]) { - case OUT_PORT: - fprint_spice_mux_testbench_sb_one_mux(fp, - cur_sb_info, - side, - cur_sb_info.chan_rr_node[side][itrack]); - used++; - break; - case IN_PORT: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of port sb[%d][%d] Channel node[%d] track[%d]!\n", - __FILE__, __LINE__, cur_sb_info.x, cur_sb_info.y, side, itrack); - exit(1); - } - } - } - - /* Free */ - if (0 < used) { - used = 1; - } - - return used; -} - -static -int fprint_spice_mux_testbench_call_one_grid_pb_muxes(FILE* fp, int ix, int iy, - t_ivec*** LL_rr_node_indices) { - int iblk; - int used = 0; - - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - /* Print all the grid */ - if ((NULL == grid[ix][iy].type) - ||(EMPTY_TYPE == grid[ix][iy].type) - ||(0 != grid[ix][iy].offset)) { - return used; - } - /* Used blocks */ - for (iblk = 0; iblk < grid[ix][iy].usage; iblk++) { - /* Only for mapped block */ - assert(NULL != block[grid[ix][iy].blocks[iblk]].phy_pb); - /* Mark the temporary net_num for the type pins*/ - mark_one_pb_parasitic_nets((t_phy_pb*)block[grid[ix][iy].blocks[iblk]].phy_pb); - fprint_spice_mux_testbench_pb_muxes_rec(fp, - (t_phy_pb*)block[grid[ix][iy].blocks[iblk]].phy_pb, - grid[ix][iy].type->pb_graph_head, - ix, iy, - LL_rr_node_indices); - used = 1; - } - /* By pass Unused blocks */ - for (iblk = grid[ix][iy].usage; iblk < grid[ix][iy].type->capacity; iblk++) { - /* Mark the temporary net_num for the type pins*/ - mark_grid_type_pb_graph_node_pins_temp_net_num(ix, iy); - fprint_spice_mux_testbench_pb_muxes_rec(fp, - NULL, - grid[ix][iy].type->pb_graph_head, - ix, iy, - LL_rr_node_indices); - } - - return used; -} - -static -void fprint_spice_mux_testbench_stimulations(FILE* fp, - int num_clocks) { - /* Voltage sources of Multiplexers are already generated during printing the netlist - * We just need global stimulations Here. - */ - - /* Give global vdd, gnd, voltage sources*/ - /* A valid file handler */ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Print generic stimuli */ - fprint_spice_testbench_generic_global_ports_stimuli(fp, num_clocks); - - /* Generate global ports stimuli */ - fprint_spice_testbench_global_ports_stimuli(fp, global_ports_head); - - /* SRAM ports */ - fprintf(fp, "***** Global Inputs for SRAMs *****\n"); - fprint_spice_testbench_global_sram_inport_stimuli(fp, sram_spice_orgz_info); - - fprintf(fp, "***** Global VDD for SRAMs *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_sram_port_name, - "vsp"); - - fprintf(fp, "***** Global VDD for load inverters *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_load_port_name, - "vsp"); - - return; -} - -static -void fprint_spice_mux_testbench_measurements(FILE* fp, - enum e_spice_tb_type mux_tb_type, - t_spice spice) { - int num_clock_cycle = max_sim_num_clock_cycles; - - /* - int i; - t_llist* head = NULL; - t_spice_mux_model* spice_mux_model = NULL; - */ - - /* Give global vdd, gnd, voltage sources*/ - /* A valid file handler */ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - fprint_spice_netlist_transient_setting(fp, spice, num_clock_cycle, FALSE); - fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); - - /* Measure the leakage and dynamic power of SRAMs*/ - fprintf(fp, ".meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to=\'clock_period\'\n"); - fprintf(fp, ".meas tran total_dynamic_srams avg p(Vgvdd_sram) from=\'clock_period\' to=\'%d*clock_period\'\n", num_clock_cycle); - fprintf(fp, ".meas tran total_energy_per_cycle_srams param=\'total_dynamic_srams*clock_period\'\n"); - - /* Measure the total leakage and dynamic power */ - fprintf(fp, ".meas tran total_leakage_power_mux[0to%d] \n", testbench_mux_cnt - 1); - fprintf(fp, "+ param=\'sum_leakage_power_mux[0to%d]\'\n", testbench_mux_cnt-1); - fprintf(fp, ".meas tran total_energy_per_cycle_mux[0to%d] \n", testbench_mux_cnt - 1); - fprintf(fp, "+ param=\'sum_energy_per_cycle_mux[0to%d]\'\n", testbench_mux_cnt-1); - - switch (mux_tb_type) { - case SPICE_PB_MUX_TB: - /* pb_muxes */ - fprintf(fp, ".meas tran total_leakage_power_pb_mux \n"); - fprintf(fp, "+ param=\'sum_leakage_power_pb_mux[0to%d]\'\n", testbench_pb_mux_cnt-1); - fprintf(fp, ".meas tran total_energy_per_cycle_pb_mux \n"); - fprintf(fp, "+ param=\'sum_energy_per_cycle_pb_mux[0to%d]\'\n", testbench_pb_mux_cnt-1); - break; - case SPICE_CB_MUX_TB: - /* cb_muxes */ - fprintf(fp, ".meas tran total_leakage_power_cb_mux \n"); - fprintf(fp, "+ param=\'sum_leakage_power_cb_mux[0to%d]\'\n", testbench_cb_mux_cnt-1); - fprintf(fp, ".meas tran total_energy_per_cycle_cb_mux \n"); - fprintf(fp, "+ param=\'sum_energy_per_cycle_cb_mux[0to%d]\'\n", testbench_cb_mux_cnt-1); - break; - case SPICE_SB_MUX_TB: - /* sb_muxes */ - fprintf(fp, ".meas tran total_leakage_power_sb_mux \n"); - fprintf(fp, "+ param=\'sum_leakage_power_sb_mux[0to%d]\'\n", testbench_sb_mux_cnt-1); - fprintf(fp, ".meas tran total_energy_per_cycle_sb_mux \n"); - fprintf(fp, "+ param=\'sum_energy_per_cycle_sb_mux[0to%d]\'\n", testbench_sb_mux_cnt-1); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid mux_tb_type!\n", __FILE__, __LINE__); - exit(1); - } - - return; -} - -/* Top-level function in this source file */ -static -int fprint_spice_one_mux_testbench(char* formatted_spice_dir, - char* circuit_name, - char* mux_testbench_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clocks, - t_arch arch, - int grid_x, int grid_y, t_rr_type cb_type, - enum e_spice_tb_type mux_tb_type, - boolean leakage_only) { - FILE* fp = NULL; - char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); - char* title = my_strcat("FPGA SPICE Routing MUX Test Bench for Design: ", circuit_name); - char* mux_testbench_file_path = my_strcat(formatted_spice_dir, mux_testbench_name); - char* mux_tb_name = NULL; - int used = 0; - - switch (mux_tb_type) { - case SPICE_PB_MUX_TB: - mux_tb_name = "CLB MUX"; - break; - case SPICE_CB_MUX_TB: - mux_tb_name = "Connection Box MUX"; - break; - case SPICE_SB_MUX_TB: - mux_tb_name = "Switch Block MUX"; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid mux_tb_type!\n", __FILE__, __LINE__); - exit(1); - } - - /* Check if the path exists*/ - fp = fopen(mux_testbench_file_path,"w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE %s Test bench netlist %s!\n", - __FILE__, __LINE__, mux_tb_name, mux_testbench_file_path); - exit(1); - } - - /* - vpr_printf(TIO_MESSAGE_INFO, "Writing Grid[%d][%d] SPICE %s MUX Test Bench for %s...\n", - grid_x, grid_y, mux_tb_name, circuit_name); - */ - - /* Load global vars in this source file */ - num_segments = arch.num_segments; - segments = arch.Segments; - - /* Print the title */ - fprint_spice_head(fp, title); - my_free(title); - - /* print technology library and design parameters*/ - /*fprint_tech_lib(fp, arch.spice->tech_lib);*/ - - /* Include parameter header files */ - fprint_spice_include_param_headers(fp, include_dir_path); - - /* Include Key subckts */ - fprint_spice_include_key_subckts(fp, formatted_subckt_dir_path); - - /* Include user-defined sub-circuit netlist */ - init_include_user_defined_netlists(*(arch.spice)); - fprint_include_user_defined_netlists(fp, *(arch.spice)); - - /* Print simulation temperature and other options for SPICE */ - fprint_spice_options(fp, arch.spice->spice_params); - - /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ - fprint_spice_mux_testbench_global_ports(fp); - - /* Quote defined Logic blocks subckts (Grids) */ - init_spice_mux_testbench_globals(*(arch.spice)); - - switch (mux_tb_type) { - case SPICE_PB_MUX_TB: - total_pb_mux_input_density = 0.; - /* Output a pb_mux testbench */ - used = fprint_spice_mux_testbench_call_one_grid_pb_muxes(fp, grid_x, grid_y, LL_rr_node_indices); - - /* Check and output info. */ - assert((0 == testbench_pb_mux_cnt)||(0 < testbench_pb_mux_cnt)); - if (0 < testbench_pb_mux_cnt) { - total_pb_mux_input_density = total_pb_mux_input_density/testbench_pb_mux_cnt; - /* Add stimulations */ - fprint_spice_mux_testbench_stimulations(fp, num_clocks); - /* Add measurements */ - fprint_spice_mux_testbench_measurements(fp, mux_tb_type, *(arch.spice)); - } - /* - vpr_printf(TIO_MESSAGE_INFO,"Average density of PB MUX inputs is %.2g.\n", total_pb_mux_input_density); - */ - break; - case SPICE_CB_MUX_TB: - /* one cbx or one cby*/ - total_cb_mux_input_density = 0.; - /* Output a cb_mux testbench */ - switch (cb_type) { - case CHANX: - used = fprint_spice_mux_testbench_call_one_grid_cb_muxes(fp, cbx_info[grid_x][grid_y], LL_rr_node_indices); - break; - case CHANY: - used = fprint_spice_mux_testbench_call_one_grid_cb_muxes(fp, cby_info[grid_x][grid_y], LL_rr_node_indices); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid connection_box_type!\n", __FILE__, __LINE__); - exit(1); - } - /* Check and output info. */ - assert((0 == testbench_cb_mux_cnt)||(0 < testbench_cb_mux_cnt)); - if (0 < testbench_cb_mux_cnt) { - total_cb_mux_input_density = total_cb_mux_input_density/testbench_cb_mux_cnt; - /* Add stimulations */ - fprint_spice_mux_testbench_stimulations(fp, num_clocks); - /* Add measurements */ - fprint_spice_mux_testbench_measurements(fp, mux_tb_type, *(arch.spice)); - } - /* - vpr_printf(TIO_MESSAGE_INFO,"Average density of CB MUX inputs is %.2g.\n", total_cb_mux_input_density); - */ - break; - case SPICE_SB_MUX_TB: - total_sb_mux_input_density = 0.; - /* Output a sb_mux testbench */ - used = fprint_spice_mux_testbench_call_one_grid_sb_muxes(fp, sb_info[grid_x][grid_y]); - /* Check and output info. */ - assert((0 == testbench_sb_mux_cnt)||(0 < testbench_sb_mux_cnt)); - if (0 < testbench_sb_mux_cnt) { - total_sb_mux_input_density = total_sb_mux_input_density/testbench_sb_mux_cnt; - /* Add stimulations */ - fprint_spice_mux_testbench_stimulations(fp, num_clocks); - /* Add measurements */ - fprint_spice_mux_testbench_measurements(fp, mux_tb_type, *(arch.spice)); - } - /* - vpr_printf(TIO_MESSAGE_INFO,"Average density of SB MUX inputs is %.2g.\n", total_sb_mux_input_density); - */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid mux_tb_type!\n", __FILE__, __LINE__); - exit(1); - } - - /* SPICE ends*/ - fprintf(fp, ".end\n"); - - /* Close the file*/ - fclose(fp); - - /* Free */ - //my_free(formatted_subckt_dir_path); - //my_free(mux_testbench_file_path); - //my_free(title); - free_muxes_llist(testbench_muxes_head); - - if (0 < testbench_mux_cnt) { - /* vpr_printf(TIO_MESSAGE_INFO, "Writing Grid[%d][%d] SPICE %s Test Bench for %s...\n", - grid_x, grid_y, mux_tb_name, circuit_name); - */ - /* Push the testbench to the linked list */ - tb_head = add_one_spice_tb_info_to_llist(tb_head, mux_testbench_file_path, max_sim_num_clock_cycles); - used = 1; - } else { - /* Remove the file generated */ - my_remove_file(mux_testbench_file_path); - used = 0; - } - - return used; -} - -void spice_print_mux_testbench(char* formatted_spice_dir, - char* circuit_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clocks, - t_arch arch, - enum e_spice_tb_type mux_tb_type, - boolean leakage_only) { - char* mux_testbench_name = NULL; - int ix, iy; - int cnt = 0; - int used = 0; - int bypass_cnt = 0; - - /* Depend on the type of testbench, we generate the a list of testbenches */ - switch (mux_tb_type) { - case SPICE_PB_MUX_TB: - cnt = 0; - vpr_printf(TIO_MESSAGE_INFO,"Generating Grid multiplexer testbench...\n"); - for (ix = 1; ix < (nx+1); ix++) { - for (iy = 1; iy < (ny+1); iy++) { - mux_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) - + 5 + strlen(my_itoa(ix)) + 1 - + strlen(my_itoa(iy)) + 1 - + strlen(spice_pb_mux_testbench_postfix) + 1 )); - sprintf(mux_testbench_name, "%s_grid%d_%d%s", - circuit_name, ix, iy, spice_pb_mux_testbench_postfix); - used = fprint_spice_one_mux_testbench(formatted_spice_dir, circuit_name, mux_testbench_name, - include_dir_path, subckt_dir_path, LL_rr_node_indices, - num_clocks, arch, ix, iy, NUM_RR_TYPES, SPICE_PB_MUX_TB, - leakage_only); - if (1 == used) { - cnt += used; - } - /* free */ - my_free(mux_testbench_name); - } - } - /* Update the global counter */ - num_used_grid_mux_tb = cnt; - vpr_printf(TIO_MESSAGE_INFO,"No. of generated Grid multiplexer testbench = %d\n", num_used_grid_mux_tb); - break; - case SPICE_CB_MUX_TB: - cnt = 0; - /* X-channel Connection Blocks */ - vpr_printf(TIO_MESSAGE_INFO,"Generating X-channel Connection Block multiplexer testbench...\n"); - for (iy = 0; iy < (ny+1); iy++) { - for (ix = 1; ix < (nx+1); ix++) { - /* Bypass non-exist CBs */ - if ((FALSE == is_cb_exist(CHANX, ix, iy)) - ||(0 == count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { - bypass_cnt++; - continue; - } - mux_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) - + 4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 1 - + strlen(spice_cb_mux_testbench_postfix) + 1 )); - sprintf(mux_testbench_name, "%s_cbx%d_%d%s", - circuit_name, ix, iy, spice_cb_mux_testbench_postfix); - used = fprint_spice_one_mux_testbench(formatted_spice_dir, circuit_name, mux_testbench_name, - include_dir_path, subckt_dir_path, LL_rr_node_indices, - num_clocks, arch, ix, iy, CHANX, SPICE_CB_MUX_TB, - leakage_only); - if (1 == used) { - cnt += used; - } - /* free */ - my_free(mux_testbench_name); - } - } - - /* Y-channel Connection Blocks */ - vpr_printf(TIO_MESSAGE_INFO,"Generating Y-channel Connection Block multiplexer testbench...\n"); - for (ix = 0; ix < (nx+1); ix++) { - for (iy = 1; iy < (ny+1); iy++) { - /* Bypass non-exist CBs */ - if ((FALSE == is_cb_exist(CHANY, ix, iy)) - ||(0 == count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { - bypass_cnt++; - continue; - } - mux_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) - + 4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 1 - + strlen(spice_cb_mux_testbench_postfix) + 1 )); - sprintf(mux_testbench_name, "%s_cby%d_%d%s", - circuit_name, ix, iy, spice_cb_mux_testbench_postfix); - used = fprint_spice_one_mux_testbench(formatted_spice_dir, circuit_name, mux_testbench_name, - include_dir_path, subckt_dir_path, LL_rr_node_indices, - num_clocks, arch, ix, iy, CHANY, SPICE_CB_MUX_TB, - leakage_only); - if (1 == used) { - cnt += used; - } - /* free */ - my_free(mux_testbench_name); - } - } - /* Update the global counter */ - num_used_cb_mux_tb = cnt; - vpr_printf(TIO_MESSAGE_INFO,"No. of generated Connection Block multiplexer testbench = %d\n", num_used_cb_mux_tb); - vpr_printf(TIO_MESSAGE_INFO, "Bypass %d Connection Blocks that does no exist in the architecture.\n", - bypass_cnt); - break; - case SPICE_SB_MUX_TB: - cnt = 0; - vpr_printf(TIO_MESSAGE_INFO,"Generating Switch Block multiplexer testbench...\n"); - for (ix = 0; ix < (nx+1); ix++) { - for (iy = 0; iy < (ny+1); iy++) { - mux_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) - + 4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 1 - + strlen(spice_sb_mux_testbench_postfix) + 1 )); - sprintf(mux_testbench_name, "%s_sb%d_%d%s", - circuit_name, ix, iy, spice_sb_mux_testbench_postfix); - used = fprint_spice_one_mux_testbench(formatted_spice_dir, circuit_name, mux_testbench_name, - include_dir_path, subckt_dir_path, LL_rr_node_indices, - num_clocks, arch, ix, iy, NUM_RR_TYPES, SPICE_SB_MUX_TB, - leakage_only); - if (1 == used) { - cnt += used; - } - /* free */ - my_free(mux_testbench_name); - } - } - /* Update the global counter */ - num_used_sb_mux_tb = cnt; - vpr_printf(TIO_MESSAGE_INFO,"No. of generated Switch Block multiplexer testbench = %d\n", num_used_sb_mux_tb); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid mux_tb_type!\n", __FILE__, __LINE__); - exit(1); - } - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux_testbench.h deleted file mode 100644 index 25dacaec2..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux_testbench.h +++ /dev/null @@ -1,20 +0,0 @@ - -void spice_print_mux_testbench(char* formatted_spice_dir, - char* circuit_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clock, - t_arch arch, - enum e_spice_tb_type mux_tb_type, - boolean leakage_only); - -/* useful subroutines */ -void fprint_spice_mux_testbench_pb_graph_pin_inv_loads_rec(FILE* fp, - int grid_x, int grid_y, - t_pb_graph_pin* src_pb_graph_pin, - t_pb* src_pb, - char* outport_name, - boolean consider_parent_node, - t_ivec*** LL_rr_node_indices); - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_pbtypes.c deleted file mode 100644 index 79b3cf72e..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_pbtypes.c +++ /dev/null @@ -1,2350 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include SPICE support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_mux_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_bitstream_utils.h" - -#include "spice_utils.h" -#include "spice_mux.h" -#include "spice_lut.h" -#include "spice_primitive.h" -#include "spice_pbtypes.h" - -/***** Subroutines *****/ - -/* Print ports of pb_types, - * SRAM ports are not printed here!!! - */ -void fprint_pb_type_ports(FILE* fp, - char* port_prefix, - int use_global_clock, - t_pb_type* cur_pb_type) { - int iport, ipin; - int num_pb_type_input_port = 0; - t_port** pb_type_input_ports = NULL; - - int num_pb_type_output_port = 0; - t_port** pb_type_output_ports = NULL; - - int num_pb_type_inout_port = 0; - t_port** pb_type_inout_ports = NULL; - - int num_pb_type_clk_port = 0; - t_port** pb_type_clk_ports = NULL; - - char* formatted_port_prefix = chomp_spice_node_prefix(port_prefix); - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - } - - /* Inputs */ - /* Find pb_type input ports */ - pb_type_input_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INPUT, &num_pb_type_input_port); - for (iport = 0; iport < num_pb_type_input_port; iport++) { - for (ipin = 0; ipin < pb_type_input_ports[iport]->num_pins; ipin++) { - fprintf(fp, "%s->%s[%d] ", formatted_port_prefix, pb_type_input_ports[iport]->name, ipin); - } - } - /* Outputs */ - /* Find pb_type output ports */ - pb_type_output_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_OUTPUT, &num_pb_type_output_port); - for (iport = 0; iport < num_pb_type_output_port; iport++) { - for (ipin = 0; ipin < pb_type_output_ports[iport]->num_pins; ipin++) { - fprintf(fp, "%s->%s[%d] ", formatted_port_prefix, pb_type_output_ports[iport]->name, ipin); - } - } - /* INOUT ports */ - /* Find pb_type inout ports */ - pb_type_inout_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_INOUT, &num_pb_type_inout_port); - for (iport = 0; iport < num_pb_type_inout_port; iport++) { - for (ipin = 0; ipin < pb_type_inout_ports[iport]->num_pins; ipin++) { - fprintf(fp, "%s->%s[%d] ", formatted_port_prefix, pb_type_inout_ports[iport]->name, ipin); - } - } - /* Clocks */ - /* Identify if the clock port is a global signal */ - /* Find pb_type clock ports */ - pb_type_clk_ports = find_pb_type_ports_match_spice_model_port_type(cur_pb_type, SPICE_MODEL_PORT_CLOCK, &num_pb_type_clk_port); - for (iport = 0; iport < num_pb_type_clk_port; iport++) { - /* only search mapped ports for primitive node */ - if (NULL != cur_pb_type->spice_model) { - /* We need to bypass global ports */ - assert(NULL != pb_type_clk_ports[iport]->spice_model_port); - if (TRUE == pb_type_clk_ports[iport]->spice_model_port->is_global) { - continue; - } - } - for (ipin = 0; ipin < pb_type_clk_ports[iport]->num_pins; ipin++) { - fprintf(fp, "%s->%s[%d] ", formatted_port_prefix, pb_type_clk_ports[iport]->name, ipin); - } - } - - /* Free */ - my_free(formatted_port_prefix); - my_free(pb_type_input_ports); - my_free(pb_type_output_ports); - my_free(pb_type_inout_ports); - my_free(pb_type_clk_ports); - - return; -} - -/* This is a truncated version of generate_spice_src_des_pb_graph_pin_prefix - * Only used to generate prefix for those dangling pin in PB Types - */ -void fprint_spice_dangling_des_pb_graph_pin_interc(FILE* fp, - t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode, - enum e_spice_pin2pin_interc_type pin2pin_interc_type, - char* parent_pin_prefix) { - t_pb_graph_node* des_pb_graph_node = NULL; - t_pb_type* des_pb_type = NULL; - int des_pb_type_index = -1; - int fan_in = 0; - t_interconnect* cur_interc = NULL; - char* des_pin_prefix = NULL; - - /* char* formatted_parent_pin_prefix = format_spice_node_prefix(parent_pin_prefix);*/ /* Complete a "_" at the end if needed*/ - //char* chomped_parent_pin_prefix = chomp_spice_node_prefix(parent_pin_prefix); /* Remove a "_" at the end if needed*/ - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check the pb_graph_nodes*/ - if (NULL == des_pb_graph_pin) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pointer: des_pb_graph_pin.\n", - __FILE__, __LINE__); - exit(1); - } - - find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, cur_mode, &cur_interc, &fan_in); - if ((NULL != cur_interc)&&(0 != fan_in)) { - return; - /* - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Cur_interc not NULL & fan_in not zero!\n", - __FILE__, __LINE__); - exit(1); - */ - } - - /* Initialize */ - des_pb_graph_node = des_pb_graph_pin->parent_node; - des_pb_type = des_pb_graph_node->pb_type; - des_pb_type_index = des_pb_graph_node->placement_index; - - /* generate the pin prefix for src_pb_graph_node and des_pb_graph_node */ - switch (pin2pin_interc_type) { - case INPUT2INPUT_INTERC: - /* src_pb_graph_node.input_pins -----------------> des_pb_graph_node.input_pins - * des_pb_graph_node is a child of src_pb_graph_node - * parent_pin_prefix is the prefix from parent pb_graph_node, in this case, src_pb_graph_node - * src_pin_prefix: we need to handle the feedbacks, they comes from the same-level pb_graph_node - * src_pin_prefix = - * OR - * src_pin_prefix = _[] - * des_pin_prefix = mode[]_[]_ - */ - /* - des_pin_prefix = (char*)my_malloc(sizeof(char)* - (strlen(formatted_parent_pin_prefix) + 5 + strlen(cur_mode->name) - + 2 + strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); - sprintf(des_pin_prefix, "%smode[%s]_%s[%d]", - formatted_parent_pin_prefix, cur_mode->name, des_pb_type->name, des_pb_type_index); - */ - /*Simplify the prefix, make the SPICE netlist readable*/ - des_pin_prefix = (char*)my_malloc(sizeof(char)* - (strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); - sprintf(des_pin_prefix, "%s[%d]", - des_pb_type->name, des_pb_type_index); - /* This is a start point, we connect it to gnd*/ - fprintf(fp, "Vdangling_%s->%s[%d] %s->%s[%d] 0 0\n", - des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number, - des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); - fprintf(fp, ".nodeset V(%s->%s[%d]) 0\n", - des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); - break; - case OUTPUT2OUTPUT_INTERC: - /* src_pb_graph_node.output_pins -----------------> des_pb_graph_node.output_pins - * src_pb_graph_node is a child of des_pb_graph_node - * parent_pin_prefix is the prefix from parent pb_graph_node, in this case, des_pb_graph_node - * src_pin_prefix = mode[]_[]_ - * des_pin_prefix = - */ - /* - des_pin_prefix = (char*)my_malloc(sizeof(char)* - (strlen(formatted_parent_pin_prefix) + 5 + strlen(cur_mode->name) - + 2 + strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); - sprintf(des_pin_prefix, "%smode[%s]_%s[%d]", - formatted_parent_pin_prefix, cur_mode->name, des_pb_type->name, des_pb_type_index); - */ - if (des_pb_type == cur_mode->parent_pb_type) { /* Interconnection from parent pb_type*/ - des_pin_prefix = (char*)my_malloc(sizeof(char)* - (5 + strlen(cur_mode->name) + 2 )); - sprintf(des_pin_prefix, "mode[%s]", cur_mode->name); - } else { - des_pin_prefix = (char*)my_malloc(sizeof(char)* - (strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); - sprintf(des_pin_prefix, "%s[%d]", - des_pb_type->name, des_pb_type_index); - } - /*Simplify the prefix, make the SPICE netlist readable*/ - /* This is a start point, we connect it to gnd*/ - fprintf(fp, "Vdangling_%s->%s[%d] %s->%s[%d] 0 0\n", - des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number, - des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); - fprintf(fp, ".nodeset V(%s->%s[%d]) 0\n", - des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s [LINE%d])Invalid pin to pin interconnection type!\n", - __FILE__, __LINE__); - exit(1); - } - - my_free(des_pin_prefix); - - return; -} - -void generate_spice_src_des_pb_graph_pin_prefix(t_pb_graph_pin* src_pb_graph_pin, - t_pb_graph_pin* des_pb_graph_pin, - enum e_spice_pin2pin_interc_type pin2pin_interc_type, - t_interconnect* pin2pin_interc, - char* parent_pin_prefix, - char** src_pin_prefix, - char** des_pin_prefix) { - t_pb_type* src_pb_type = NULL; - int src_pb_type_index = -1; - - t_pb_type* des_pb_type = NULL; - int des_pb_type_index = -1; - - /* char* formatted_parent_pin_prefix = format_spice_node_prefix(parent_pin_prefix);*/ /* Complete a "_" at the end if needed*/ - /* char* chomped_parent_pin_prefix = chomp_spice_node_prefix(parent_pin_prefix);*/ /* Remove a "_" at the end if needed*/ - - /* t_mode* pin2pin_interc_parent_mode = NULL; */ - - /* Check the pb_graph_nodes*/ - if (NULL == src_pb_graph_pin) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pointer: src_pb_graph_pin.\n", - __FILE__, __LINE__); - exit(1); - } - if (NULL == des_pb_graph_pin) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pointer: des_pb_graph_pin.\n", - __FILE__, __LINE__); - exit(1); - } - if (NULL == pin2pin_interc) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pointer: pin2pin_interc.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Initialize */ - src_pb_type = src_pb_graph_pin->parent_node->pb_type; - src_pb_type_index = src_pb_graph_pin->parent_node->placement_index; - des_pb_type = des_pb_graph_pin->parent_node->pb_type; - des_pb_type_index = des_pb_graph_pin->parent_node->placement_index; - - /* pin2pin_interc_parent_mode = pin2pin_interc->parent_mode;*/ - - assert(NULL == (*src_pin_prefix)); - assert(NULL == (*des_pin_prefix)); - /* generate the pin prefix for src_pb_graph_node and des_pb_graph_node */ - switch (pin2pin_interc_type) { - case INPUT2INPUT_INTERC: - /* src_pb_graph_node.input_pins -----------------> des_pb_graph_node.input_pins - * des_pb_graph_node is a child of src_pb_graph_node - * parent_pin_prefix is the prefix from parent pb_graph_node, in this case, src_pb_graph_node - * src_pin_prefix: we need to handle the feedbacks, they comes from the same-level pb_graph_node - * src_pin_prefix = - * OR - * src_pin_prefix = _[] - * des_pin_prefix = mode[]_[]_ - */ - if (src_pb_type == des_pb_type->parent_mode->parent_pb_type) { /* Interconnection from parent pb_type*/ - /* - (*src_pin_prefix) = my_strdup(chomped_parent_pin_prefix); - */ - /*Simplify the prefix, make the SPICE netlist readable*/ - (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* - (5 + strlen(des_pb_type->parent_mode->name) + 2)); - sprintf((*src_pin_prefix), "mode[%s]", des_pb_type->parent_mode->name); - } else { - /* - (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* - (strlen(formatted_parent_pin_prefix) + 5 + strlen(pin2pin_interc_parent_mode->name) - + 2 + strlen(src_pb_type->name) + 1 + strlen(my_itoa(src_pb_type_index)) + 1 + 1)); - sprintf((*src_pin_prefix), "%smode[%s]_%s[%d]", - formatted_parent_pin_prefix, pin2pin_interc_parent_mode->name, src_pb_type->name, src_pb_type_index); - */ - /*Simplify the prefix, make the SPICE netlist readable*/ - (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* - (strlen(src_pb_type->name) + 1 + strlen(my_itoa(src_pb_type_index)) + 1 + 1)); - sprintf((*src_pin_prefix), "%s[%d]", - src_pb_type->name, src_pb_type_index); - } - /* - (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* - (strlen(formatted_parent_pin_prefix) + 5 + strlen(pin2pin_interc_parent_mode->name) - + 2 + strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); - sprintf((*des_pin_prefix), "%smode[%s]_%s[%d]", - formatted_parent_pin_prefix, pin2pin_interc_parent_mode->name, des_pb_type->name, des_pb_type_index); - */ - (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* - (strlen(des_pb_type->name) + 1 + strlen(my_itoa(des_pb_type_index)) + 1 + 1)); - sprintf((*des_pin_prefix), "%s[%d]", - des_pb_type->name, des_pb_type_index); - break; - case OUTPUT2OUTPUT_INTERC: - /* src_pb_graph_node.output_pins -----------------> des_pb_graph_node.output_pins - * src_pb_graph_node is a child of des_pb_graph_node - * parent_pin_prefix is the prefix from parent pb_graph_node, in this case, des_pb_graph_node - * src_pin_prefix = mode[]_[]_ - * des_pin_prefix = - */ - /* - (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* - (strlen(formatted_parent_pin_prefix) + 5 + strlen(pin2pin_interc_parent_mode->name) - + 2 + strlen(src_pb_type->name) + 1 + strlen(my_itoa(src_pb_type_index)) + 1 + 1)); - sprintf((*src_pin_prefix), "%smode[%s]_%s[%d]", - formatted_parent_pin_prefix, pin2pin_interc_parent_mode->name, src_pb_type->name, src_pb_type_index); - */ - /*Simplify the prefix, make the SPICE netlist readable*/ - if (des_pb_type == src_pb_type) { /* src pin is an input of the parent pb_type*/ - /* - (*src_pin_prefix) = my_strdup(chomped_parent_pin_prefix); - */ - /*Simplify the prefix, make the SPICE netlist readable*/ - (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* - (5 + strlen(pin2pin_interc->parent_mode->name) + 2)); - sprintf((*src_pin_prefix), "mode[%s]", pin2pin_interc->parent_mode->name); - } else { - (*src_pin_prefix) = (char*)my_malloc(sizeof(char)* - (strlen(src_pb_type->name) + 1 + strlen(my_itoa(src_pb_type_index)) + 1 + 1)); - sprintf((*src_pin_prefix), "%s[%d]", - src_pb_type->name, src_pb_type_index); - } - /* - (*des_pin_prefix) = my_strdup(chomped_parent_pin_prefix); - */ - /*Simplify the prefix, make the SPICE netlist readable*/ - (*des_pin_prefix) = (char*)my_malloc(sizeof(char)* - (5 + strlen(pin2pin_interc->parent_mode->name) + 2)); - sprintf((*des_pin_prefix), "mode[%s]", pin2pin_interc->parent_mode->name); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s [LINE%d])Invalid pin to pin interconnection type!\n", - __FILE__, __LINE__); - exit(1); - } - return; -} - -/* We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * src_pb_graph_node.[in|out]_pins -----------------> des_pb_graph_node.[in|out]pins - * /|\ - * | - * input_pins, edges, output_pins - */ -void fprintf_spice_pb_graph_pin_interc(FILE* fp, - char* parent_pin_prefix, - enum e_spice_pin2pin_interc_type pin2pin_interc_type, - t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode, - int select_edge) { - int iedge, ilevel; - int fan_in = 0; - t_interconnect* cur_interc = NULL; - enum e_interconnect spice_interc_type = DIRECT_INTERC; - - t_pb_graph_pin* src_pb_graph_pin = NULL; - t_pb_graph_node* src_pb_graph_node = NULL; - t_pb_type* src_pb_type = NULL; - /* int src_pb_type_index = -1; */ - - /* t_pb_type* des_pb_type = NULL; */ - /* int des_pb_type_index = -1; */ - - char* formatted_parent_pin_prefix = chomp_spice_node_prefix(parent_pin_prefix); /* Complete a "_" at the end if needed*/ - char* src_pin_prefix = NULL; - char* des_pin_prefix = NULL; - char* sram_vdd_port_name = NULL; - - int num_sram_bits = 0; - int* sram_bits = NULL; - /* int num_sram = 0; */ - int cur_sram = 0; - int mux_level = 0; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* 1. identify pin interconnection type, - * 2. Identify the number of fan-in (Consider interconnection edges of only selected mode) - * 3. Select and print the SPICE netlist - */ - fan_in = 0; - cur_interc = NULL; - find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, cur_mode, &cur_interc, &fan_in); - if ((NULL == cur_interc)||(0 == fan_in)) { - /* No interconnection matched */ - /* Connect this pin to GND for better convergence */ - /* TODO: find the correct pin name!!!*/ - fprint_spice_dangling_des_pb_graph_pin_interc(fp, des_pb_graph_pin, cur_mode, pin2pin_interc_type, - formatted_parent_pin_prefix); - return; - } - /* Initialize the interconnection type that will be implemented in SPICE netlist*/ - spice_interc_type = determine_actual_pb_interc_type(cur_interc, fan_in); - /* This time, (2nd round), we print the subckt, according to interc type*/ - switch (spice_interc_type) { - case DIRECT_INTERC: - /* Check : - * 1. Direct interc has only one fan-in! - */ - assert(1 == fan_in); - //assert(1 == des_pb_graph_pin->num_input_edges); - /* For more than one mode defined, the direct interc has more than one input_edge , - * We need to find which edge is connected the pin we want - */ - for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - if (cur_interc == des_pb_graph_pin->input_edges[iedge]->interconnect) { - break; - } - } - assert(iedge < des_pb_graph_pin->num_input_edges); - /* 2. spice_model is a wire */ - assert(NULL != cur_interc->spice_model); - assert(SPICE_MODEL_WIRE == cur_interc->spice_model->type); - assert(NULL != cur_interc->spice_model->wire_param); - /* Initialize*/ - /* Source pin, node, pb_type*/ - src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; - src_pb_graph_node = src_pb_graph_pin->parent_node; - src_pb_type = src_pb_graph_node->pb_type; - /* src_pb_type_index = src_pb_graph_node->placement_index; */ - /* Des pin, node, pb_type */ - /* des_pb_type = des_pb_graph_node->pb_type; */ - /* des_pb_type_index = des_pb_graph_node->placement_index; */ - /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ - generate_spice_src_des_pb_graph_pin_prefix(src_pb_graph_pin, des_pb_graph_pin, pin2pin_interc_type, - cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix); - /* Call the subckt that has already been defined before */ - fprintf(fp, "X%s[%d] ", cur_interc->spice_model->prefix, cur_interc->spice_model->cnt); - cur_interc->spice_model->cnt++; /* Stats the number of spice_model used*/ - /* Print the pin names! Input and output - * Input: port_prefix_->[pin_index] - * Output: port_prefix_[pin_index] - */ - /* Input */ - /* Make sure correctness*/ - assert(src_pb_type == des_pb_graph_pin->input_edges[iedge]->input_pins[0]->port->parent_pb_type); - /* Print */ - fprintf(fp, "%s->%s[%d] ", - src_pin_prefix, src_pb_graph_pin->port->name, src_pb_graph_pin->pin_number); - /* Output */ - fprintf(fp, "%s->%s[%d] ", - des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); - /* Middle output for wires in logic blocks: TODO: Abolish to save simulation time */ - /* fprintf(fp, "gidle_mid_out "); */ - /* Local vdd and gnd, TODO: we should have an independent VDD for all local interconnections*/ - fprintf(fp, "gvdd_local_interc sgnd "); - /* End with spice_model name */ - fprintf(fp, "%s\n", cur_interc->spice_model->name); - /* Free */ - my_free(src_pin_prefix); - my_free(des_pin_prefix); - src_pin_prefix = NULL; - des_pin_prefix = NULL; - break; - case COMPLETE_INTERC: - case MUX_INTERC: - /* Check : - * MUX should have at least 2 fan_in - */ - assert((2 == fan_in)||(2 < fan_in)); - /* 2. spice_model is a wire */ - assert(NULL != cur_interc->spice_model); - assert(SPICE_MODEL_MUX == cur_interc->spice_model->type); - /* Call the subckt that has already been defined before */ - fprintf(fp, "X%s_size%d[%d] ", cur_interc->spice_model->prefix, fan_in, cur_interc->spice_model->cnt); - /* Global ports */ - if (0 < rec_fprint_spice_model_global_ports(fp, cur_interc->spice_model, FALSE)) { - fprintf(fp, "+ "); - } - /* Inputs */ - for (iedge = 0; iedge < des_pb_graph_pin->num_input_edges; iedge++) { - if (cur_mode != des_pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) { - continue; - } - check_pb_graph_edge(*(des_pb_graph_pin->input_edges[iedge])); - /* Initialize*/ - /* Source pin, node, pb_type*/ - src_pb_graph_pin = des_pb_graph_pin->input_edges[iedge]->input_pins[0]; - src_pb_graph_node = src_pb_graph_pin->parent_node; - src_pb_type = src_pb_graph_node->pb_type; - /* src_pb_type_index = src_pb_graph_node->placement_index; */ - /* Des pin, node, pb_type */ - /* des_pb_type = des_pb_graph_node->pb_type; */ - /* des_pb_type_index = des_pb_graph_node->placement_index; */ - /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ - generate_spice_src_des_pb_graph_pin_prefix(src_pb_graph_pin, des_pb_graph_pin, pin2pin_interc_type, - cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix); - /* We need to find out if the des_pb_graph_pin is in the mode we want !*/ - /* Print */ - fprintf(fp, "%s->%s[%d] ", - src_pin_prefix, src_pb_graph_pin->port->name, src_pb_graph_pin->pin_number); - /* Free */ - my_free(src_pin_prefix); - my_free(des_pin_prefix); - src_pin_prefix = NULL; - des_pin_prefix = NULL; - } - /* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/ - generate_spice_src_des_pb_graph_pin_prefix(src_pb_graph_pin, des_pb_graph_pin, pin2pin_interc_type, - cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix); - /* Outputs */ - fprintf(fp, "%s->%s[%d] ", - des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number); - - assert(select_edge < fan_in); - /* SRAMs */ - switch (cur_interc->spice_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - decode_cmos_mux_sram_bits(cur_interc->spice_model, fan_in, select_edge, - &num_sram_bits, &sram_bits, &mux_level); - break; - case SPICE_MODEL_DESIGN_RRAM: - decode_rram_mux(cur_interc->spice_model, fan_in, select_edge, - &num_sram_bits, &sram_bits, &mux_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for verilog model (%s)!\n", - __FILE__, __LINE__, cur_interc->spice_model->name); - } - - cur_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info); - /* Create wires to sram outputs*/ - for (ilevel = 0; ilevel < num_sram_bits; ilevel++) { - assert( (0 == sram_bits[ilevel]) || (1 == sram_bits[ilevel]) ); - fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_sram + ilevel, sram_bits[ilevel]); - fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_sram + ilevel, 1 - sram_bits[ilevel]); - } - /* Local vdd and gnd, TODO: we should have an independent VDD for all local interconnections*/ - fprintf(fp, "gvdd_local_interc sgnd "); - /* End with spice_model name */ - fprintf(fp, "%s_size%d\n", cur_interc->spice_model->name, fan_in); - /* Print the encoding in SPICE netlist for debugging */ - fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n", - cur_interc->spice_model->cnt, mux_level, select_edge); - fprintf(fp, "*****"); - for (ilevel = 0; ilevel < num_sram_bits; ilevel++) { - fprintf(fp, "%d", sram_bits[ilevel]); - } - fprintf(fp, "*****\n"); - /* Print all the srams*/ - cur_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info); - /* Give the VDD port name for SRAMs */ - sram_vdd_port_name = (char*)my_malloc(sizeof(char)* - (strlen(spice_tb_global_vdd_localrouting_sram_port_name) - + 1 )); - sprintf(sram_vdd_port_name, "%s", - spice_tb_global_vdd_localrouting_sram_port_name); - /* Now Print SRAMs one by one */ - for (ilevel = 0; ilevel < num_sram_bits; ilevel++) { - fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, - cur_interc->spice_model, - sram_vdd_port_name); - } - /* Store the configuraion bit to linked-list */ - add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_sram, - num_sram_bits, sram_bits); - /* Update spice_model counter */ - cur_interc->spice_model->cnt++; - /* Free */ - my_free(sram_bits); - my_free(src_pin_prefix); - my_free(des_pin_prefix); - my_free(sram_vdd_port_name); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid interconnection type for %s (Arch[LINE%d])!\n", - __FILE__, __LINE__, cur_interc->name, cur_interc->line_num); - exit(1); - } - return; -} - -/* Print the SPICE interconnections of a port defined in pb_graph */ -void fprintf_spice_pb_graph_port_interc(FILE* fp, - char* formatted_pin_prefix, - t_pb_graph_node* cur_pb_graph_node, - t_phy_pb* cur_pb, - enum e_spice_pb_port_type pb_port_type, - t_mode* cur_mode, - int is_idle) { - int iport, ipin; - int node_index = -1; - int prev_node = -1; - /* int prev_edge = -1; */ - int path_id = -1; - t_rr_node* pb_rr_nodes = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - switch (pb_port_type) { - case SPICE_PB_PORT_INPUT: - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - /* If this is a idle block, we set 0 to the selected edge*/ - if (is_idle) { - assert(NULL == cur_pb); - path_id = DEFAULT_PATH_ID; - } else { - /* Get the selected edge of current pin*/ - assert(NULL != cur_pb); - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = cur_pb_graph_node->input_pins[iport][ipin].rr_node_index_physical_pb; - prev_node = pb_rr_nodes[node_index].prev_node; - /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ - /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ - if (OPEN == prev_node) { - path_id = DEFAULT_PATH_ID; // - } else { - /* Find the path_id */ - path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); - assert(DEFAULT_PATH_ID != path_id); - } - } - fprintf_spice_pb_graph_pin_interc(fp, - formatted_pin_prefix, /* parent_pin_prefix */ - INPUT2INPUT_INTERC, - &(cur_pb_graph_node->input_pins[iport][ipin]), - cur_mode, - path_id); - } - } - break; - case SPICE_PB_PORT_OUTPUT: - for (iport = 0; iport < cur_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_output_pins[iport]; ipin++) { - /* If this is a idle block, we set 0 to the selected edge*/ - if (is_idle) { - assert(NULL == cur_pb); - path_id = DEFAULT_PATH_ID; - } else { - /* Get the selected edge of current pin*/ - assert(NULL != cur_pb); - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = cur_pb_graph_node->output_pins[iport][ipin].rr_node_index_physical_pb; - prev_node = pb_rr_nodes[node_index].prev_node; - /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ - /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ - if (OPEN == prev_node) { - path_id = DEFAULT_PATH_ID; // - } else { - /* Find the path_id */ - path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); - assert(DEFAULT_PATH_ID != path_id); - } - } - fprintf_spice_pb_graph_pin_interc(fp, - formatted_pin_prefix, /* parent_pin_prefix */ - OUTPUT2OUTPUT_INTERC, - &(cur_pb_graph_node->output_pins[iport][ipin]), - cur_mode, - path_id); - } - } - break; - case SPICE_PB_PORT_CLOCK: - for (iport = 0; iport < cur_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_clock_pins[iport]; ipin++) { - /* If this is a idle block, we set 0 to the selected edge*/ - if (is_idle) { - assert(NULL == cur_pb); - path_id = DEFAULT_PATH_ID; - } else { - /* Get the selected edge of current pin*/ - assert(NULL != cur_pb); - pb_rr_nodes = cur_pb->rr_graph->rr_node; - node_index = cur_pb_graph_node->clock_pins[iport][ipin].rr_node_index_physical_pb; - prev_node = pb_rr_nodes[node_index].prev_node; - /* prev_edge = pb_rr_nodes[node_index].prev_edge; */ - /* Make sure this pb_rr_node is not OPEN and is not a primitive output*/ - if (OPEN == prev_node) { - path_id = DEFAULT_PATH_ID; // - } else { - /* Find the path_id */ - path_id = find_path_id_between_pb_rr_nodes(pb_rr_nodes, prev_node, node_index); - assert(DEFAULT_PATH_ID != path_id); - } - } - fprintf_spice_pb_graph_pin_interc(fp, - formatted_pin_prefix, /* parent_pin_prefix */ - INPUT2INPUT_INTERC, - &(cur_pb_graph_node->clock_pins[iport][ipin]), - cur_mode, - path_id); - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid pb port type!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -/* Print the SPICE interconnections according to pb_graph */ -void fprint_spice_pb_graph_interc(FILE* fp, - char* pin_prefix, - t_pb_graph_node* cur_pb_graph_node, - t_phy_pb* cur_pb, - int select_mode_index, - int is_idle) { - int ipb, jpb; - t_mode* cur_mode = NULL; - t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; - t_pb_graph_node* child_pb_graph_node = NULL; - t_phy_pb* child_pb = NULL; - int is_child_pb_idle = 0; - - char* formatted_pin_prefix = format_spice_node_prefix(pin_prefix); /* Complete a "_" at the end if needed*/ - - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check cur_pb_type*/ - if (NULL == cur_pb_type) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_type.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Assign current mode */ - cur_mode = &(cur_pb_graph_node->pb_type->modes[select_mode_index]); - - /* We check output_pins of cur_pb_graph_node and its the input_edges - * Built the interconnections between outputs of cur_pb_graph_node and outputs of child_pb_graph_node - * child_pb_graph_node.output_pins -----------------> cur_pb_graph_node.outpins - * /|\ - * | - * input_pins, edges, output_pins - */ - fprintf_spice_pb_graph_port_interc(fp, formatted_pin_prefix, - cur_pb_graph_node, cur_pb, - SPICE_PB_PORT_OUTPUT, - cur_mode, is_idle); - - /* We check input_pins of child_pb_graph_node and its the input_edges - * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node - * cur_pb_graph_node.input_pins -----------------> child_pb_graph_node.input_pins - * /|\ - * | - * input_pins, edges, output_pins - */ - for (ipb = 0; ipb < cur_pb_type->modes[select_mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[select_mode_index].pb_type_children[ipb].num_pb; jpb++) { - child_pb_graph_node = &(cur_pb_graph_node->child_pb_graph_nodes[select_mode_index][ipb][jpb]); - /* If this is a idle block, we set 0 to the selected edge*/ - if (is_idle) { - assert(NULL == cur_pb); - child_pb = NULL; - is_child_pb_idle = is_idle; - } else { - assert(NULL != cur_pb); - child_pb = &(cur_pb->child_pbs[ipb][jpb]); - /* Check if child_pb is empty */ - if (NULL != child_pb->name) { - is_child_pb_idle = 0; - } else { - is_child_pb_idle = 1; - child_pb = NULL; - } - } - /* For each child_pb_graph_node input pins*/ - fprintf_spice_pb_graph_port_interc(fp, formatted_pin_prefix, - child_pb_graph_node, child_pb, - SPICE_PB_PORT_INPUT, - cur_mode, is_child_pb_idle); - /* TODO: for clock pins, we should do the same work */ - fprintf_spice_pb_graph_port_interc(fp, formatted_pin_prefix, - child_pb_graph_node, child_pb, - SPICE_PB_PORT_CLOCK, - cur_mode, is_child_pb_idle); - } - } - - return; -} - -/* Print the netlist for primitive pb_types*/ -void fprint_spice_pb_graph_primitive_node(FILE* fp, - char* subckt_prefix, - t_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - int pb_type_index) { - int iport, ipin; - t_pb_type* cur_pb_type = NULL; - char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ - t_spice_model* spice_model = NULL; - char* subckt_name = NULL; - char* subckt_port_name = NULL; - - int num_spice_model_sram_port = 0; - t_spice_model_port** spice_model_sram_ports = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check cur_pb_graph_node*/ - if (NULL == cur_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - - spice_model = cur_pb_type->spice_model; - /* If we define a SPICE model for the pb_type, - * We should print the subckt of it. - * 1. If the SPICE model defines an included netlist, we quote the netlist subckt - * 2. If not defined an included netlist, we built one only if this is a LUT - */ - /* Example: []*/ - subckt_name = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) - + strlen(cur_pb_type->name) + 1 - + strlen(my_itoa(pb_type_index)) + 1 + 1)); /* Plus the '0' at the end of string*/ - sprintf(subckt_name, "%s%s[%d]", formatted_subckt_prefix, cur_pb_type->name, pb_type_index); - /* Check if defines an included netlist*/ - if (NULL == spice_model->model_netlist) { - if (LUT_CLASS == cur_pb_type->class_type) { - /* For LUT, we have a built-in netlist, See "spice_lut.c", So we don't do anything here */ - } else { - /* We report an error */ - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Require an included netlist in Pb_type(%s) SPICE_model(%s)!\n", - __FILE__, __LINE__, cur_pb_type->name, spice_model->name); - exit(1); - } - } - /* Print the definition line - * IMPORTANT: NO SRAMs ports are created here, they are fixed when quoting spice_models - */ - fprintf(fp, ".subckt %s ", subckt_name); - subckt_port_name = format_spice_node_prefix(subckt_name); - /* Inputs, outputs, inouts, clocks */ - fprint_pb_type_ports(fp, subckt_port_name, 0, cur_pb_type); - /* Finish with local vdd and gnd */ - fprintf(fp, "svdd sgnd\n"); - /* Include the spice_model*/ - fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt); - spice_model->cnt++; /* Stats the number of spice_model used*/ - /* Make input, output, inout, clocks connected*/ - /* IMPORTANT: (sequence of these ports should be changed!) */ - fprint_pb_type_ports(fp, subckt_name, 0, cur_pb_type); - /* Connected to SRAMs */ - /* Configure the SRAMs to be idle*/ - spice_model_sram_ports = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_spice_model_sram_port, TRUE); - for (iport = 0; iport < num_spice_model_sram_port; iport++) { - for(ipin = 0; ipin < spice_model_sram_ports[iport]->size; ipin++) { - fprintf(fp, "sgnd "); - } - } - /* Print the spice_model name defined */ - fprintf(fp, "%s\n", spice_model->name); - /* Print end of subckt*/ - fprintf(fp, ".eom\n"); - /* Free */ - my_free(subckt_name); - - return; -} - -/* Print the subckt of a primitive pb */ -void fprint_pb_primitive_spice_model(FILE* fp, - char* subckt_prefix, - t_phy_pb* prim_phy_pb, - t_pb_graph_node* prim_pb_graph_node, - int pb_index, - t_spice_model* spice_model, - int is_idle) { - t_pb_type* prim_pb_type = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check cur_pb_graph_node*/ - if (NULL == prim_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - - prim_pb_type = prim_pb_graph_node->pb_type; - - /* Asserts*/ - assert(pb_index == prim_pb_graph_node->placement_index); - assert(0 == strcmp(spice_model->name, prim_pb_type->spice_model->name)); - - /* According to different type, we print netlist*/ - switch (spice_model->type) { - case SPICE_MODEL_LUT: - /* If this is a idle block we should set sram_bits to zero*/ - fprint_pb_primitive_lut(fp, subckt_prefix, prim_phy_pb, prim_pb_type, - pb_index, spice_model); - break; - case SPICE_MODEL_FF: - case SPICE_MODEL_IOPAD: - case SPICE_MODEL_HARDLOGIC: - assert(NULL != spice_model->model_netlist); - fprint_pb_primitive_generic(fp, subckt_prefix, prim_phy_pb, prim_pb_type, - pb_index, spice_model); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of spice_model(%s), should be [LUT|FF|HARD_LOGIC|IO]!\n", - __FILE__, __LINE__, spice_model->name); - exit(1); - break; - } - - return; -} - -/* Print idle pb_types recursively - * search the idle_mode until we reach the leaf node - */ -void fprint_spice_idle_pb_graph_node_rec(FILE* fp, - char* subckt_prefix, - t_pb_graph_node* cur_pb_graph_node, - int pb_type_index) { - int mode_index, ipb, jpb, child_mode_index; - t_pb_type* cur_pb_type = NULL; - char* subckt_name = NULL; - char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ - char* pass_on_prefix = NULL; - char* child_pb_type_prefix = NULL; - char* subckt_port_prefix = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check cur_pb_graph_node*/ - if (NULL == cur_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - cur_pb_type = cur_pb_graph_node->pb_type; - - /* Recursively finish all the child pb_types*/ - if (NULL == cur_pb_type->spice_model) { - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Pass the SPICE mode prefix on, - * mode[]_ - */ - pass_on_prefix = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 - + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1 + 1)); - sprintf(pass_on_prefix, "%s%s[%d]_mode[%s]_", - formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); - /* Recursive*/ - fprint_spice_idle_pb_graph_node_rec(fp, pass_on_prefix, - &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), jpb); - /* Free */ - my_free(pass_on_prefix); - } - } - } - - /* Check if this has defined a spice_model*/ - if (NULL != cur_pb_type->spice_model) { - fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, - NULL, cur_pb_graph_node, - pb_type_index, cur_pb_type->spice_model, 1); - /* Finish the primitive node, we return */ - return; - } - - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_idle_mode_index((*cur_pb_type)); - /* Create a new subckt */ - /* mode[] - */ - subckt_name = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 - + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); - /* Definition*/ - sprintf(subckt_name, "%s%s[%d]_mode[%s]", - formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); - fprintf(fp, ".subckt %s ", subckt_name); - /* Inputs, outputs, inouts, clocks */ - subckt_port_prefix = (char*)my_malloc(sizeof(char)* - (5 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); - sprintf(subckt_port_prefix, "mode[%s]", cur_pb_type->modes[mode_index].name); - /* - fprint_pb_type_ports(fp, subckt_name, 0, cur_pb_type); - */ - /* Simplify the port prefix, make SPICE netlist readable */ - fprint_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type); - /* Finish with local vdd and gnd */ - fprintf(fp, "svdd sgnd\n"); - /* Definition ends*/ - - /* Specify the head of scan-chain */ - if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { - fprintf(fp, "***** Head of scan-chain *****\n"); - fprintf(fp, "R%s_sc_head %s_sc_head %s[%d]->in 0\n", - subckt_name, subckt_name, sram_spice_model->prefix, sram_spice_model->cnt); - } - - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); - /* mode[]_[] - */ - fprintf(fp, "X%s[%d] ", cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); - /* Pass the SPICE mode prefix on, - * mode[]_[] - * [] - */ - /* - child_pb_type_prefix = (char*)my_malloc(sizeof(char)* - (strlen(subckt_name) + 1 - + strlen(cur_pb_type->modes[imode].pb_type_children[ipb].name) + 1 - + strlen(my_itoa(jpb)) + 1 + 1)); - sprintf(child_pb_type_prefix, "%s_%s[%d]", subckt_name, - cur_pb_type->modes[imode].pb_type_children[ipb].name, jpb); - */ - /* Simplify the prefix! */ - child_pb_type_prefix = (char*)my_malloc(sizeof(char)* - (strlen(cur_pb_type->modes[mode_index].pb_type_children[ipb].name) + 1 - + strlen(my_itoa(jpb)) + 1 + 1)); - sprintf(child_pb_type_prefix, "%s[%d]", - cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); - /* Print inputs, outputs, inouts, clocks - * NO SRAMs !!! They have already been fixed in the bottom level - */ - fprint_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb])); - fprintf(fp, "svdd sgnd "); /* Local vdd and gnd*/ - - /* Find the pb_type_children mode */ - if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Find the idle_mode_index, if this is not a leaf node */ - child_mode_index = find_pb_type_idle_mode_index(cur_pb_type->modes[mode_index].pb_type_children[ipb]); - } - /* If the pb_type_children is a leaf node, we don't use the mode to name it, - * else we can use the mode to name it - */ - if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Not a leaf node*/ - fprintf(fp, "%s_%s[%d]_mode[%s]\n", - subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb, - cur_pb_type->modes[mode_index].pb_type_children[ipb].modes[child_mode_index].name); - } else { /* Have a spice model definition, this is a leaf node*/ - fprintf(fp, "%s_%s[%d]\n", - subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); - } - my_free(child_pb_type_prefix); - } - } - /* Print interconnections, set is_idle as TRUE*/ - fprint_spice_pb_graph_interc(fp, subckt_name, cur_pb_graph_node, NULL, mode_index, 1); - /* Check each pins of pb_graph_node */ - - /* Specify the Tail of scan-chain */ - if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { - fprintf(fp, "***** Tail of scan-chain *****\n"); - fprintf(fp, "R%s_sc_tail %s_sc_tail %s[%d]->in 0\n", - subckt_name, subckt_name, sram_spice_model->prefix, sram_spice_model->cnt); - } - - /* End the subckt */ - fprintf(fp, ".eom\n"); - /* Free subckt name*/ - my_free(subckt_name); - - return; -} - -/* Print SPICE netlist for each pb and corresponding pb_graph_node*/ -void fprint_spice_pb_graph_node_rec(FILE* fp, - char* subckt_prefix, - t_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - int pb_type_index) { - int mode_index, ipb, jpb, child_mode_index; - t_pb_type* cur_pb_type = NULL; - char* subckt_name = NULL; - char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ - char* pass_on_prefix = NULL; - char* child_pb_type_prefix = NULL; - - char* subckt_port_prefix = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check cur_pb_graph_node*/ - if (NULL == cur_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - cur_pb_type = cur_pb_graph_node->pb_type; - mode_index = cur_pb->mode; - - /* Recursively finish all the child pb_types*/ - if (NULL == cur_pb_type->spice_model) { - /* recursive for the child_pbs*/ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Pass the SPICE mode prefix on, - * []_mode[]_ - */ - pass_on_prefix = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 - + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1 + 1)); - sprintf(pass_on_prefix, "%s%s[%d]_mode[%s]_", - formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); - /* Recursive*/ - /* Refer to pack/output_clustering.c [LINE 392] */ - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - fprint_spice_pb_graph_node_rec(fp, pass_on_prefix, &(cur_pb->child_pbs[ipb][jpb]), - cur_pb->child_pbs[ipb][jpb].pb_graph_node, jpb); - } else { - /* Check if this pb has no children, no children mean idle*/ - fprint_spice_idle_pb_graph_node_rec(fp, pass_on_prefix, - cur_pb->child_pbs[ipb][jpb].pb_graph_node, jpb); - } - /* Free */ - my_free(pass_on_prefix); - } - } - } - - /* Check if this has defined a spice_model*/ - if (NULL != cur_pb_type->spice_model) { - switch (cur_pb_type->class_type) { - case LUT_CLASS: - /* Special care for LUT !!! - * Mapped logical block information is stored in child_pbs - */ - /* - fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, - child_pb, cur_pb_graph_node, - pb_type_index, cur_pb_type->spice_model, 0); - */ - break; - case LATCH_CLASS: - assert(0 == cur_pb_type->num_modes); - /* Consider the num_pb, create all the subckts*/ - /* - fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, - cur_pb, cur_pb_graph_node, - pb_type_index, cur_pb_type->spice_model, 0); - */ - break; - case MEMORY_CLASS: - /* Consider the num_pb, create all the subckts*/ - /* - fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, - child_pb, cur_pb_graph_node, - pb_type_index, cur_pb_type->spice_model, 0); - */ - break; - case UNKNOWN_CLASS: - /* Consider the num_pb, create all the subckts*/ - /* - fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, - cur_pb, cur_pb_graph_node, - pb_type_index, cur_pb_type->spice_model, 0); - */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n", - __FILE__, __LINE__, cur_pb_type->name); - exit(1); - } - /* Finish for primitive node, return */ - return; - } - - /* Create a new subckt */ - /* mode[] - */ - subckt_name = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 - + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); - /* Definition*/ - sprintf(subckt_name, "%s%s[%d]_mode[%s]", - formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); - fprintf(fp, ".subckt %s ", subckt_name); - /* Inputs, outputs, inouts, clocks */ - subckt_port_prefix = (char*)my_malloc(sizeof(char)* - (5 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); - sprintf(subckt_port_prefix, "mode[%s]", cur_pb_type->modes[mode_index].name); - /* - fprint_pb_type_ports(fp, subckt_name, 0, cur_pb_type); - */ - /* Simplify the prefix! Make the SPICE netlist readable*/ - fprint_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type); - /* Finish with local vdd and gnd */ - fprintf(fp, "svdd sgnd\n"); - /* Definition ends*/ - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); - /* mode[]_[] - */ - fprintf(fp, "X%s[%d] ", cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); - /* Pass the SPICE mode prefix on, - * mode[]_[] - */ - /* - child_pb_type_prefix = (char*)my_malloc(sizeof(char)* - (strlen(subckt_name) + 1 - + strlen(cur_pb_type->modes[mode_index].pb_type_children[ipb].name) + 1 - + strlen(my_itoa(jpb)) + 1 + 1)); - sprintf(child_pb_type_prefix, "%s_%s[%d]", subckt_name, - cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); - */ - /* Simplify the prefix! Make the SPICE netlist readable*/ - child_pb_type_prefix = (char*)my_malloc(sizeof(char)* - (strlen(cur_pb_type->modes[mode_index].pb_type_children[ipb].name) + 1 - + strlen(my_itoa(jpb)) + 1 + 1)); - sprintf(child_pb_type_prefix, "%s[%d]", - cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); - /* Print inputs, outputs, inouts, clocks - * NO SRAMs !!! They have already been fixed in the bottom level - */ - fprint_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb])); - fprintf(fp, "svdd sgnd "); /* Local vdd and gnd*/ - /* Find the pb_type_children mode */ - if ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)) { - child_mode_index = cur_pb->child_pbs[ipb][jpb].mode; - } else if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Find the idle_mode_index, if this is not a leaf node */ - child_mode_index = find_pb_type_idle_mode_index(cur_pb_type->modes[mode_index].pb_type_children[ipb]); - } - /* If the pb_type_children is a leaf node, we don't use the mode to name it, - * else we can use the mode to name it - */ - if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Not a leaf node*/ - fprintf(fp, "%s_%s[%d]_mode[%s]\n", - subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb, - cur_pb_type->modes[mode_index].pb_type_children[ipb].modes[child_mode_index].name); - } else { /* Have a spice model definition, this is a leaf node*/ - fprintf(fp, "%s_%s[%d]\n", - subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); - } - my_free(child_pb_type_prefix); - } - } - /* Print interconnections, set is_idle as TRUE*/ - /* - fprint_spice_pb_graph_interc(fp, subckt_name, cur_pb_graph_node, cur_pb, mode_index, 0); - */ - /* Check each pins of pb_graph_node */ - /* End the subckt */ - fprintf(fp, ".eom\n"); - /* Free subckt name*/ - my_free(subckt_name); - - return; -} - -/* Print SPICE netlist for each pb and corresponding pb_graph_node - * at physical-level implementation */ -void fprint_spice_phy_pb_graph_node_rec(FILE* fp, - char* subckt_prefix, - t_phy_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - int pb_type_index) { - int mode_index, ipb, jpb, child_mode_index, is_idle; - t_pb_type* cur_pb_type = NULL; - char* subckt_name = NULL; - char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ - char* pass_on_prefix = NULL; - char* child_pb_type_prefix = NULL; - - char* subckt_port_prefix = NULL; - t_phy_pb* child_pb = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check cur_pb_graph_node*/ - if (NULL == cur_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid cur_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - cur_pb_type = cur_pb_graph_node->pb_type; - - /* Identify if this is an idle block */ - is_idle = 0; - if (NULL == cur_pb) { - is_idle = 1; - } - - /* Recursively finish all the child pb_types*/ - if (FALSE == is_primitive_pb_type(cur_pb_type)) { - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); - /* recursive for the child_pbs*/ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Pass the SPICE mode prefix on, - * []_mode[]_ - */ - pass_on_prefix = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 - + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1 + 1)); - sprintf(pass_on_prefix, "%s%s[%d]_mode[%s]_", - formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); - /* Recursive*/ - /* Refer to pack/output_clustering.c [LINE 392] */ - /* Find the child pb that is mapped, and the mapping info is not stored in the physical mode ! */ - if (NULL == cur_pb) { - child_pb = NULL; - } else { - assert (NULL != cur_pb); - child_pb = get_phy_child_pb_for_phy_pb_graph_node(cur_pb, ipb, jpb); - } - fprint_spice_phy_pb_graph_node_rec(fp, pass_on_prefix, child_pb, - &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), jpb); - /* Free */ - my_free(pass_on_prefix); - } - } - } - - /* Check if this has defined a spice_model*/ - if (TRUE == is_primitive_pb_type(cur_pb_type)) { - switch (cur_pb_type->class_type) { - case LUT_CLASS: - fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, - cur_pb, cur_pb_graph_node, - pb_type_index, cur_pb_type->spice_model, is_idle); - break; - case LATCH_CLASS: - assert(0 == cur_pb_type->num_modes); - /* Consider the num_pb, create all the subckts*/ - fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, - cur_pb, cur_pb_graph_node, - pb_type_index, cur_pb_type->spice_model, is_idle); - break; - case UNKNOWN_CLASS: - case MEMORY_CLASS: - /* Consider the num_pb, create all the subckts*/ - fprint_pb_primitive_spice_model(fp, formatted_subckt_prefix, - cur_pb, cur_pb_graph_node, - pb_type_index, cur_pb_type->spice_model, is_idle); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n", - __FILE__, __LINE__, cur_pb_type->name); - exit(1); - } - /* Finish for primitive node, return */ - return; - } - - /* Find the mode that define_idle_mode*/ - mode_index = find_pb_type_physical_mode_index((*cur_pb_type)); - /* Create a new subckt */ - /* mode[] - */ - subckt_name = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) + strlen(cur_pb_type->name) + 1 - + strlen(my_itoa(pb_type_index)) + 7 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); - /* Definition*/ - sprintf(subckt_name, "%s%s[%d]_mode[%s]", - formatted_subckt_prefix, cur_pb_type->name, pb_type_index, cur_pb_type->modes[mode_index].name); - fprintf(fp, ".subckt %s ", subckt_name); - /* Inputs, outputs, inouts, clocks */ - subckt_port_prefix = (char*)my_malloc(sizeof(char)* - (5 + strlen(cur_pb_type->modes[mode_index].name) + 1 + 1)); - sprintf(subckt_port_prefix, "mode[%s]", cur_pb_type->modes[mode_index].name); - /* - fprint_pb_type_ports(fp, subckt_name, 0, cur_pb_type); - */ - /* Simplify the prefix! Make the SPICE netlist readable*/ - fprint_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type); - /* Finish with local vdd and gnd */ - fprintf(fp, "svdd sgnd\n"); - /* Definition ends*/ - /* Quote all child pb_types */ - for (ipb = 0; ipb < cur_pb_type->modes[mode_index].num_pb_type_children; ipb++) { - /* Each child may exist multiple times in the hierarchy*/ - for (jpb = 0; jpb < cur_pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* we should make sure this placement index == child_pb_type[jpb]*/ - assert(jpb == cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb].placement_index); - /* If the pb_type_children is a leaf node, we don't use the mode to name it, - * else we can use the mode to name it - */ - fprintf(fp, "X%s[%d] ", cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); - /* Simplify the prefix! Make the SPICE netlist readable*/ - child_pb_type_prefix = (char*)my_malloc(sizeof(char)* - (strlen(cur_pb_type->modes[mode_index].pb_type_children[ipb].name) + 1 - + strlen(my_itoa(jpb)) + 1 + 1)); - sprintf(child_pb_type_prefix, "%s[%d]", - cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); - /* Print inputs, outputs, inouts, clocks - * NO SRAMs !!! They have already been fixed in the bottom level - */ - fprint_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb])); - fprintf(fp, "svdd sgnd "); /* Local vdd and gnd*/ - /* Find the pb_type_children mode */ - /* If the pb_type_children is a leaf node, we don't use the mode to name it, - * else we can use the mode to name it - */ - if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { /* Not a leaf node*/ - child_mode_index = find_pb_type_physical_mode_index(cur_pb_type->modes[mode_index].pb_type_children[ipb]); - fprintf(fp, "%s_%s[%d]_mode[%s]\n", - subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb, - cur_pb_type->modes[mode_index].pb_type_children[ipb].modes[child_mode_index].name); - } else { /* Have a spice model definition, this is a leaf node*/ - fprintf(fp, "%s_%s[%d]\n", - subckt_name, cur_pb_type->modes[mode_index].pb_type_children[ipb].name, jpb); - } - my_free(child_pb_type_prefix); - } - } - /* Print interconnections, set is_idle as TRUE*/ - fprint_spice_pb_graph_interc(fp, subckt_name, cur_pb_graph_node, cur_pb, mode_index, is_idle); - /* Check each pins of pb_graph_node */ - /* End the subckt */ - fprintf(fp, ".eom\n"); - /* Free subckt name*/ - my_free(subckt_name); - - return; -} - - -/* Print the SPICE netlist of a block that has been mapped */ -void fprint_spice_block(FILE* fp, - char* subckt_name, - int x, - int y, - int z, - t_type_ptr type_descriptor, - t_block* mapped_block) { - t_pb* top_pb = NULL; - t_pb_graph_node* top_pb_graph_node = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* check */ - assert(x == mapped_block->x); - assert(y == mapped_block->y); - assert(type_descriptor == mapped_block->type); - assert(NULL != type_descriptor); - - /* Print SPICE netlist according to the hierachy of type descriptor recursively*/ - /* Go for the pb_types*/ - top_pb_graph_node = type_descriptor->pb_graph_head; - assert(NULL != top_pb_graph_node); - top_pb = mapped_block->pb; - assert(NULL != top_pb); - - /* Recursively find all mode and print netlist*/ - /* IMPORTANT: type_descriptor just say we have a block that in global view, how it connects to global routing arch. - * Inside the type_descripor, there is a top_pb_graph_node(pb_graph_head), describe the top pb_type defined. - * The index of such top pb_type is always 0. - */ - fprint_spice_pb_graph_node_rec(fp, subckt_name, top_pb, top_pb_graph_node, z); - - return; -} - - -/* Print an idle logic block - * Find the idle_mode in arch files, - * And print the spice netlist into file - */ -void fprint_spice_idle_block(FILE* fp, - char* subckt_name, - int x, - int y, - int z, - t_type_ptr type_descriptor) { - t_pb_graph_node* top_pb_graph_node = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Ensure we have a valid type_descriptor*/ - assert(NULL != type_descriptor); - - /* Go for the pb_types*/ - top_pb_graph_node = type_descriptor->pb_graph_head; - assert(NULL != top_pb_graph_node); - - /* Recursively find all idle mode and print netlist*/ - fprint_spice_idle_pb_graph_node_rec(fp, subckt_name, top_pb_graph_node, z); - - return; -} - -/* Print the SPICE netlist of a block that has been mapped */ -void fprint_spice_physical_block(FILE* fp, - char* subckt_name, - int x, - int y, - int z, - t_type_ptr type_descriptor) { - t_phy_pb* top_pb = NULL; - t_pb_graph_node* top_pb_graph_node = NULL; - t_block* mapped_block = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* check */ - assert(NULL != type_descriptor); - top_pb_graph_node = type_descriptor->pb_graph_head; - assert(NULL != top_pb_graph_node); - - /* Print SPICE netlist according to the hierachy of type descriptor recursively*/ - - mapped_block = search_mapped_block(x, y, z); - /* Go for the pb_types*/ - if (NULL != mapped_block) { - top_pb = (t_phy_pb*)mapped_block->phy_pb; - assert(NULL != top_pb); - } - - /* Recursively find all mode and print netlist*/ - /* IMPORTANT: type_descriptor just say we have a block that in global view, how it connects to global routing arch. - * Inside the type_descripor, there is a top_pb_graph_node(pb_graph_head), describe the top pb_type defined. - * The index of such top pb_type is always 0. - */ - fprint_spice_phy_pb_graph_node_rec(fp, subckt_name, top_pb, top_pb_graph_node, z); - - return; -} - -/* We print all the pins of a type descriptor in the following sequence - * TOP, RIGHT, BOTTOM, LEFT - */ -void fprint_grid_pins(FILE* fp, - int x, - int y, - int top_level) { - int iheight, side, ipin; - int side_pin_index; - t_type_ptr type_descriptor = grid[x][y].type; - int capacity = grid[x][y].type->capacity; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - assert(NULL != type_descriptor); - assert(0 < capacity); - - for (side = 0; side < 4; side++) { - /* Count the number of pins */ - side_pin_index = 0; - //for (iz = 0; iz < capacity; iz++) { - for (iheight = 0; iheight < type_descriptor->height; iheight++) { - for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { - if (1 == type_descriptor->pinloc[iheight][side][ipin]) { - /* This pin appear at this side! */ - if (1 == top_level) { - fprintf(fp, "+ grid[%d][%d]_pin[%d][%d][%d] \n", x, y, - iheight, side, ipin); - } else { - fprintf(fp, "+ %s_height[%d]_pin[%d] \n", - convert_side_index_to_string(side), iheight, ipin); - } - side_pin_index++; - } - } - } - //} - } - - return; -} - -/* Special for I/O grid, we need only part of the ports - * i.e., grid[0][0..ny] only need the right side ports. - */ -/* We print all the pins of a type descriptor in the following sequence - * TOP, RIGHT, BOTTOM, LEFT - */ -void fprint_io_grid_pins(FILE* fp, - int x, - int y, - int top_level) { - int iheight, side, ipin; - int side_pin_index; - t_type_ptr type_descriptor = grid[x][y].type; - int capacity = grid[x][y].type->capacity; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - assert(NULL != type_descriptor); - assert(0 < capacity); - /* Make sure this is IO */ - assert(IO_TYPE == type_descriptor); - - /* identify the location of IO grid and - * decide which side of ports we need - */ - side = determine_io_grid_side(x,y); - - /* Count the number of pins */ - side_pin_index = 0; - //for (iz = 0; iz < capacity; iz++) { - for (iheight = 0; iheight < type_descriptor->height; iheight++) { - for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { - if (1 == type_descriptor->pinloc[iheight][side][ipin]) { - /* This pin appear at this side! */ - if (1 == top_level) { - fprintf(fp, "+ grid[%d][%d]_pin[%d][%d][%d] \n", x, y, - iheight, side, ipin); - } else { - fprintf(fp, "+ %s_height[%d]_pin[%d] \n", - convert_side_index_to_string(side), iheight, ipin); - } - side_pin_index++; - } - } - } - //} - - return; -} - -char* get_grid_block_subckt_name(int x, - int y, - int z, - char* subckt_prefix, - t_block* mapped_block) { - char* ret = NULL; - int imode; - t_type_ptr type_descriptor = NULL; - char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); - int num_idle_mode = 0; - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - - type_descriptor = grid[x][y].type; - assert(NULL != type_descriptor); - - if (NULL == mapped_block) { - /* This a NULL logic block... Find the idle mode*/ - for (imode = 0; imode < type_descriptor->pb_type->num_modes; imode++) { - if (1 == type_descriptor->pb_type->modes[imode].define_idle_mode) { - num_idle_mode++; - } - } - assert(1 == num_idle_mode); - for (imode = 0; imode < type_descriptor->pb_type->num_modes; imode++) { - if (1 == type_descriptor->pb_type->modes[imode].define_idle_mode) { - ret = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) + strlen(type_descriptor->name) + 1 - + strlen(my_itoa(z)) + 7 + strlen(type_descriptor->pb_type->modes[imode].name) + 1 + 1)); - sprintf(ret, "%s%s[%d]_mode[%s]", formatted_subckt_prefix, - type_descriptor->name, z, type_descriptor->pb_type->modes[imode].name); - break; - } - } - } else { - /* This is a logic block with specific configurations*/ - assert(NULL != mapped_block->pb); - imode = mapped_block->pb->mode; - ret = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) + strlen(type_descriptor->name) + 1 - + strlen(my_itoa(z)) + 7 + strlen(type_descriptor->pb_type->modes[imode].name) + 1 + 1)); - sprintf(ret, "%s%s[%d]_mode[%s]", formatted_subckt_prefix, - type_descriptor->name, z, type_descriptor->pb_type->modes[imode].name); - } - - return ret; -} - -/* Physical mode subckt name */ -char* get_grid_phy_block_subckt_name(int x, int y, int z, - char* subckt_prefix, - t_block* mapped_block) { - char* ret = NULL; - int imode; - t_type_ptr type_descriptor = NULL; - char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); - int num_physical_mode = 0; - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - - type_descriptor = grid[x][y].type; - assert(NULL != type_descriptor); - - if (NULL == mapped_block) { - /* This a NULL logic block... Find the idle mode*/ - for (imode = 0; imode < type_descriptor->pb_type->num_modes; imode++) { - if (1 == type_descriptor->pb_type->modes[imode].define_physical_mode) { - num_physical_mode++; - } - } - assert(1 == num_physical_mode); - for (imode = 0; imode < type_descriptor->pb_type->num_modes; imode++) { - if (1 == type_descriptor->pb_type->modes[imode].define_physical_mode) { - ret = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) + strlen(type_descriptor->name) + 1 - + strlen(my_itoa(z)) + 7 + strlen(type_descriptor->pb_type->modes[imode].name) + 1 + 1)); - sprintf(ret, "%s%s[%d]_mode[%s]", formatted_subckt_prefix, - type_descriptor->name, z, type_descriptor->pb_type->modes[imode].name); - break; - } - } - } else { - /* This is a logic block with specific configurations*/ - assert(NULL != mapped_block->pb); - imode = mapped_block->pb->mode; - ret = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) + strlen(type_descriptor->name) + 1 - + strlen(my_itoa(z)) + 7 + strlen(type_descriptor->pb_type->modes[imode].name) + 1 + 1)); - sprintf(ret, "%s%s[%d]_mode[%s]", formatted_subckt_prefix, - type_descriptor->name, z, type_descriptor->pb_type->modes[imode].name); - } - - return ret; -} - - -/* Print the pins of grid subblocks */ -void fprint_grid_block_subckt_pins(FILE* fp, - int z, - t_type_ptr type_descriptor) { - int iport, ipin, side; - int grid_pin_index, pin_height, side_pin_index; - t_pb_graph_node* top_pb_graph_node = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check */ - assert(NULL != type_descriptor); - top_pb_graph_node = type_descriptor->pb_graph_head; - assert(NULL != top_pb_graph_node); - - for (iport = 0; iport < top_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ipin++) { - grid_pin_index = top_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster - + z * type_descriptor->num_pins / type_descriptor->capacity; - /* num_pins/capacity = the number of pins that each type_descriptor has. - * Capacity defines the number of type_descriptors in each grid - * so the pin index at grid level = pin_index_in_type_descriptor - * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor - */ - pin_height = type_descriptor->pin_height[grid_pin_index]; - for (side = 0; side < 4; side++) { - if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { - /* This pin appear at this side! */ - fprintf(fp, "+ %s_height[%d]_pin[%d] \n", - convert_side_index_to_string(side), pin_height, grid_pin_index); - side_pin_index++; - } - } - } - } - - for (iport = 0; iport < top_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ipin++) { - grid_pin_index = top_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster - + z * type_descriptor->num_pins / type_descriptor->capacity; - /* num_pins/capacity = the number of pins that each type_descriptor has. - * Capacity defines the number of type_descriptors in each grid - * so the pin index at grid level = pin_index_in_type_descriptor - * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor - */ - pin_height = type_descriptor->pin_height[grid_pin_index]; - for (side = 0; side < 4; side++) { - if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { - /* This pin appear at this side! */ - fprintf(fp, "+ %s_height[%d]_pin[%d] \n", - convert_side_index_to_string(side), pin_height, grid_pin_index); - side_pin_index++; - } - } - } - } - - for (iport = 0; iport < top_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ipin++) { - grid_pin_index = top_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster - + z * type_descriptor->num_pins / type_descriptor->capacity; - /* num_pins/capacity = the number of pins that each type_descriptor has. - * Capacity defines the number of type_descriptors in each grid - * so the pin index at grid level = pin_index_in_type_descriptor - * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor - */ - pin_height = type_descriptor->pin_height[grid_pin_index]; - for (side = 0; side < 4; side++) { - if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { - /* This pin appear at this side! */ - fprintf(fp, "+ %s_height[%d]_pin[%d] \n", - convert_side_index_to_string(side), pin_height, grid_pin_index); - side_pin_index++; - } - } - } - } - - return; -} - - -/* Print the pins of grid subblocks */ -void fprint_io_grid_block_subckt_pins(FILE* fp, - int x, - int y, - int z, - t_type_ptr type_descriptor) { - int iport, ipin, side; - int grid_pin_index, pin_height, side_pin_index; - t_pb_graph_node* top_pb_graph_node = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check */ - assert(NULL != type_descriptor); - top_pb_graph_node = type_descriptor->pb_graph_head; - assert(NULL != top_pb_graph_node); - - /* Make sure this is IO */ - assert(IO_TYPE == type_descriptor); - - /* identify the location of IO grid and - * decide which side of ports we need - */ - if (0 == x) { - /* Left side */ - assert((0 < y)&&(y < (ny + 1))); - /* Print Right side ports*/ - side = RIGHT; - } else if ((nx + 1) == x) { - /* Right side */ - assert((0 < y)&&(y < (ny + 1))); - /* Print Left side ports*/ - side = LEFT; - } else if (0 == y) { - /* Bottom Side */ - assert((0 < x)&&(x < (nx + 1))); - /* Print TOP side ports */ - side = TOP; - } else if ((ny + 1) == y) { - /* TOP Side */ - assert((0 < x)&&(x < (nx + 1))); - /* Print BOTTOM side ports */ - side = BOTTOM; - } else { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid co-ordinators(x=%d, y=%d) for I/O grid!\n", - __FILE__, __LINE__, x, y); - exit(1); - } - - for (iport = 0; iport < top_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ipin++) { - grid_pin_index = top_pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster - + z * type_descriptor->num_pins / type_descriptor->capacity; - /* num_pins/capacity = the number of pins that each type_descriptor has. - * Capacity defines the number of type_descriptors in each grid - * so the pin index at grid level = pin_index_in_type_descriptor - * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor - */ - pin_height = type_descriptor->pin_height[grid_pin_index]; - if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { - /* This pin appear at this side! */ - fprintf(fp, "+ %s_height[%d]_pin[%d] \n", - convert_side_index_to_string(side), pin_height, grid_pin_index); - side_pin_index++; - } - } - } - - for (iport = 0; iport < top_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ipin++) { - grid_pin_index = top_pb_graph_node->output_pins[iport][ipin].pin_count_in_cluster - + z * type_descriptor->num_pins / type_descriptor->capacity; - /* num_pins/capacity = the number of pins that each type_descriptor has. - * Capacity defines the number of type_descriptors in each grid - * so the pin index at grid level = pin_index_in_type_descriptor - * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor - */ - pin_height = type_descriptor->pin_height[grid_pin_index]; - if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { - /* This pin appear at this side! */ - fprintf(fp, "+ %s_height[%d]_pin[%d] \n", - convert_side_index_to_string(side), pin_height, grid_pin_index); - side_pin_index++; - } - } - } - - for (iport = 0; iport < top_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ipin++) { - grid_pin_index = top_pb_graph_node->clock_pins[iport][ipin].pin_count_in_cluster - + z * type_descriptor->num_pins / type_descriptor->capacity; - /* num_pins/capacity = the number of pins that each type_descriptor has. - * Capacity defines the number of type_descriptors in each grid - * so the pin index at grid level = pin_index_in_type_descriptor - * + type_descriptor_index_in_capacity * num_pins_per_type_descriptor - */ - pin_height = type_descriptor->pin_height[grid_pin_index]; - if (1 == type_descriptor->pinloc[pin_height][side][grid_pin_index]) { - /* This pin appear at this side! */ - fprintf(fp, "+ %s_height[%d]_pin[%d] \n", - convert_side_index_to_string(side), pin_height, grid_pin_index); - side_pin_index++; - } - } - } - - return; -} - -/* Print the SPICE netlist for a physical grid blocks */ -void fprint_grid_physical_blocks(char* subckt_dir, - int ix, int iy, - t_arch* arch) { - int subckt_name_str_len = 0; - char* subckt_name = NULL; - int iz; - int capacity; - FILE* fp = NULL; - char* fname = NULL; - - /* Check */ - assert((!(0 > ix))&&(!(ix > (nx + 1)))); - assert((!(0 > iy))&&(!(iy > (ny + 1)))); - - /* Update the grid_index_low for each spice_model */ - update_spice_models_grid_index_low(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); - - /* generate_grid_subckt, type_descriptor of each grid defines the capacity, - * for example, each grid may contains more than one top-level pb_types, such as I/O - */ - if ((NULL == grid[ix][iy].type) - ||(EMPTY_TYPE == grid[ix][iy].type) - ||(0 != grid[ix][iy].offset)) { - /* Update the grid_index_high for each spice_model */ - update_spice_models_grid_index_high(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); - return; - } - - /* Create file handler */ - fp = spice_create_one_subckt_file(subckt_dir, "Phyiscal Logic Block ", grid_spice_file_name_prefix, ix, iy, &fname); - - capacity = grid[ix][iy].type->capacity; - assert(0 < capacity); - - /* Make the sub-circuit name*/ - /* Name format: grid[][]_*/ - subckt_name_str_len = 4 + 1 + strlen(my_itoa(ix)) + 2 - + strlen(my_itoa(iy)) + 1 + 1 + 1; /* Plus '0' at the end of string*/ - subckt_name = (char*)my_malloc(sizeof(char)*subckt_name_str_len); - sprintf(subckt_name, "grid[%d][%d]_", ix, iy); - - /* Specify the head of scan-chain */ - if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { - fprintf(fp, "***** Head of scan-chain *****\n"); - fprintf(fp, "Rgrid[%d][%d]_sc_head grid[%d][%d]_sc_head %s[%d]->in 0\n", - ix, iy, ix, iy, sram_spice_model->prefix, sram_spice_model->cnt); - fprintf(fp, ".global grid[%d][%d]_sc_head \n", - ix, iy); - } - - /* check capacity and if this has been mapped */ - for (iz = 0; iz < capacity; iz++) { - /* Comments: Grid [x][y]*/ - fprintf(fp, "***** Grid[%d][%d] type_descriptor: %s[%d] *****\n", ix, iy, grid[ix][iy].type->name, iz); - /* Print a physical logic block with specific configurations*/ - fprint_spice_physical_block(fp, subckt_name, ix, iy, iz, grid[ix][iy].type); - fprintf(fp, "***** END *****\n\n"); - } - - /* Specify the tail of scan-chain */ - if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { - fprintf(fp, "***** Tail of scan-chain *****\n"); - fprintf(fp, "Rgrid[%d][%d]_sc_tail grid[%d][%d]_sc_tail %s[%d]->in 0\n", - ix, iy, ix, iy, sram_spice_model->prefix, sram_spice_model->cnt); - fprintf(fp, ".global grid[%d][%d]_sc_tail \n", - ix, iy); - } - - /* Update the grid_index_high for each spice_model */ - update_spice_models_grid_index_high(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); - - fprintf(fp, "***** Grid[%d][%d], Capactity: %d *****\n", ix, iy, capacity); - fprintf(fp, "***** Top Protocol *****\n"); - /* Definition */ - fprintf(fp, ".subckt grid[%d][%d] \n", ix, iy); - /* Pins */ - /* Special Care for I/O grid */ - if (IO_TYPE == grid[ix][iy].type) { - fprint_io_grid_pins(fp, ix, iy, 0); - } else { - fprint_grid_pins(fp, ix, iy, 0); - } - /* Local Vdd and GND */ - fprintf(fp, "+ svdd sgnd\n"); - - /* Quote all the sub blocks*/ - for (iz = 0; iz < capacity; iz++) { - fprintf(fp, "Xgrid[%d][%d][%d] \n", ix, iy, iz); - /* Print all the pins */ - /* Special Care for I/O grid */ - if (IO_TYPE == grid[ix][iy].type) { - fprint_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type); - } else { - fprint_grid_block_subckt_pins(fp, iz, grid[ix][iy].type); - } - /* Local Vdd and Gnd, subckt name*/ - fprintf(fp, "+ svdd sgnd %s\n", get_grid_phy_block_subckt_name(ix, iy, iz, subckt_name, NULL)); - } - - fprintf(fp, ".eom\n"); - - /* Close the file */ - fclose(fp); - - /* Add fname to the linked list */ - grid_spice_subckt_file_path_head = add_one_subckt_file_name_to_llist(grid_spice_subckt_file_path_head, fname); - - /* Free */ - my_free(subckt_name); - my_free(fname); - - return; -} - - - -/* Print the SPICE netlist for a grid blocks */ -void fprint_grid_blocks(char* subckt_dir, - int ix, int iy, - t_arch* arch) { - int subckt_name_str_len = 0; - char* subckt_name = NULL; - t_block* mapped_block = NULL; - int iz; - int cur_block_index = 0; - int capacity; - FILE* fp = NULL; - char* fname = NULL; - - /* Check */ - assert((!(0 > ix))&&(!(ix > (nx + 1)))); - assert((!(0 > iy))&&(!(iy > (ny + 1)))); - - /* Update the grid_index_low for each spice_model */ - update_spice_models_grid_index_low(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); - - /* generate_grid_subckt, type_descriptor of each grid defines the capacity, - * for example, each grid may contains more than one top-level pb_types, such as I/O - */ - /* Bypass EMPTY_TYPE */ - if ((NULL == grid[ix][iy].type) - ||(EMPTY_TYPE == grid[ix][iy].type) - ||(0 != grid[ix][iy].offset)) { - /* Update the grid_index_high for each spice_model */ - update_spice_models_grid_index_high(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); - return; - } - - /* Create file handler */ - fp = spice_create_one_subckt_file(subckt_dir, "Logic Block", grid_spice_file_name_prefix, ix, iy, &fname); - - capacity= grid[ix][iy].type->capacity; - assert(0 < capacity); - - /* Make the sub-circuit name*/ - /* Name format: grid[][]_*/ - subckt_name_str_len = 4 + 1 + strlen(my_itoa(ix)) + 2 - + strlen(my_itoa(iy)) + 1 + 1 + 1; /* Plus '0' at the end of string*/ - subckt_name = (char*)my_malloc(sizeof(char)*subckt_name_str_len); - sprintf(subckt_name, "grid[%d][%d]_", ix, iy); - - /* Specify the head of scan-chain */ - if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { - fprintf(fp, "***** Head of scan-chain *****\n"); - fprintf(fp, "Rgrid[%d][%d]_sc_head grid[%d][%d]_sc_head %s[%d]->in 0\n", - ix, iy, ix, iy, sram_spice_model->prefix, sram_spice_model->cnt); - fprintf(fp, ".global grid[%d][%d]_sc_head \n", - ix, iy); - } - - cur_block_index = 0; - /* check capacity and if this has been mapped */ - for (iz = 0; iz < capacity; iz++) { - /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ - mapped_block = search_mapped_block(ix, iy, iz); - /* Comments: Grid [x][y]*/ - fprintf(fp, "***** Grid[%d][%d] type_descriptor: %s[%d] *****\n", ix, iy, grid[ix][iy].type->name, iz); - if (NULL == mapped_block) { - /* Print a NULL logic block...*/ - fprint_spice_idle_block(fp, subckt_name, ix, iy, iz, grid[ix][iy].type); - } else { - if (iz == mapped_block->z) { - // assert(mapped_block == &(block[grid[ix][iy].blocks[cur_block_index]])); - cur_block_index++; - } - /* Print a logic block with specific configurations*/ - fprint_spice_block(fp, subckt_name, ix, iy, iz, grid[ix][iy].type, mapped_block); - } - fprintf(fp, "***** END *****\n\n"); - } - - /* Specify the tail of scan-chain */ - if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { - fprintf(fp, "***** Tail of scan-chain *****\n"); - fprintf(fp, "Rgrid[%d][%d]_sc_tail grid[%d][%d]_sc_tail %s[%d]->in 0\n", - ix, iy, ix, iy, sram_spice_model->prefix, sram_spice_model->cnt); - fprintf(fp, ".global grid[%d][%d]_sc_tail \n", - ix, iy); - } - - assert(cur_block_index == grid[ix][iy].usage); - - /* Update the grid_index_high for each spice_model */ - update_spice_models_grid_index_high(ix, iy, arch->spice->num_spice_model, arch->spice->spice_models); - - fprintf(fp, "***** Grid[%d][%d], Capactity: %d *****\n", ix, iy, capacity); - fprintf(fp, "***** Top Protocol *****\n"); - /* Definition */ - fprintf(fp, ".subckt grid[%d][%d] \n", ix, iy); - /* Pins */ - /* Special Care for I/O grid */ - if (IO_TYPE == grid[ix][iy].type) { - fprint_io_grid_pins(fp, ix, iy, 0); - } else { - fprint_grid_pins(fp, ix, iy, 0); - } - /* Local Vdd and GND */ - fprintf(fp, "+ svdd sgnd\n"); - - /* Quote all the sub blocks*/ - for (iz = 0; iz < capacity; iz++) { - fprintf(fp, "Xgrid[%d][%d][%d] \n", ix, iy, iz); - /* Print all the pins */ - /* Special Care for I/O grid */ - if (IO_TYPE == grid[ix][iy].type) { - fprint_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type); - } else { - fprint_grid_block_subckt_pins(fp, iz, grid[ix][iy].type); - } - /* Check in all the blocks(clustered logic block), there is a match x,y,z*/ - mapped_block = search_mapped_block(ix, iy, iz); - /* Local Vdd and Gnd, subckt name*/ - fprintf(fp, "+ svdd sgnd %s\n", get_grid_block_subckt_name(ix, iy, iz, subckt_name, mapped_block)); - } - - fprintf(fp, ".eom\n"); - - /* Close the file */ - fclose(fp); - - /* Add fname to the linked list */ - grid_spice_subckt_file_path_head = add_one_subckt_file_name_to_llist(grid_spice_subckt_file_path_head, fname); - - /* Free */ - my_free(subckt_name); - my_free(fname); - - return; -} - - -/* Print all logic blocks SPICE models - * Each logic blocks in the grid that allocated for the FPGA - * will be printed. May have an additional option that only - * output the used logic blocks - */ -void generate_spice_logic_blocks(char* subckt_dir, - t_arch* arch) { - /* Create file names */ - int ix, iy; - - /* Check the grid*/ - if ((0 == nx)||(0 == ny)) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid grid size (nx=%d, ny=%d)!\n", __FILE__, __LINE__, nx, ny); - return; - } - vpr_printf(TIO_MESSAGE_INFO,"Grid size of FPGA: nx=%d ny=%d\n", nx + 1, ny + 1); - assert(NULL != grid); - - /* Print the core logic block one by one - * Note ix=0 and ix = nx + 1 are IO pads. They surround the core logic blocks - */ - vpr_printf(TIO_MESSAGE_INFO,"Generating core grids...\n"); - for (ix = 1; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - /* Ensure this is not a io */ - assert(IO_TYPE != grid[ix][iy].type); - /* Ensure a valid usage */ - assert((0 == grid[ix][iy].usage)||(0 < grid[ix][iy].usage)); - /* I comment the previous version here in case we want to compare */ - /* fprint_grid_blocks(subckt_dir, ix, iy, arch); */ - fprint_grid_physical_blocks(subckt_dir, ix, iy, arch); - } - } - - vpr_printf(TIO_MESSAGE_INFO,"Generating IO grids...\n"); - /* Print the IO pads */ - /* Top side : x = 1 .. nx + 1, y = nx + 1 */ - iy = ny + 1; - for (ix = 1; ix < (nx + 1); ix++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - /* TODO: replace with physical block generator */ - fprint_grid_physical_blocks(subckt_dir, ix, iy, arch); - } - /* Right side : x = nx + 1, y = 1 .. ny*/ - ix = nx + 1; - for (iy = 1; iy < (ny + 1); iy++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - /* TODO: replace with physical block generator */ - fprint_grid_physical_blocks(subckt_dir, ix, iy, arch); - } - /* Bottom side : x = 1 .. nx + 1, y = 0 */ - iy = 0; - for (ix = 1; ix < (nx + 1); ix++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - /* TODO: replace with physical block generator */ - fprint_grid_physical_blocks(subckt_dir, ix, iy, arch); - } - /* Left side: x = 0, y = 1 .. ny*/ - ix = 0; - for (iy = 1; iy < (ny + 1); iy++) { - /* Ensure this is a io */ - assert(IO_TYPE == grid[ix][iy].type); - /* TODO: replace with physical block generator */ - fprint_grid_physical_blocks(subckt_dir, ix, iy, arch); - } - - /* Output a header file for all the logic blocks */ - vpr_printf(TIO_MESSAGE_INFO,"Generating header file for grid submodules...\n"); - spice_print_subckt_header_file(grid_spice_subckt_file_path_head, - subckt_dir, - logic_block_spice_file_name); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_pbtypes.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_pbtypes.h deleted file mode 100644 index bb6588be4..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_pbtypes.h +++ /dev/null @@ -1,110 +0,0 @@ -#ifndef SPICE_PBTYPES_H -#define SPICE_PBTYPES_H - -void fprint_pb_type_ports(FILE* fp, - char* port_prefix, - int use_global_clock, - t_pb_type* cur_pb_type); - -void fprint_spice_dangling_des_pb_graph_pin_interc(FILE* fp, - t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode, - enum e_spice_pin2pin_interc_type pin2pin_interc_type, - char* parent_pin_prefix); - -void generate_spice_src_des_pb_graph_pin_prefix(t_pb_graph_pin* src_pb_graph_pin, - t_pb_graph_pin* des_pb_graph_pin, - enum e_spice_pin2pin_interc_type pin2pin_interc_type, - t_interconnect* pin2pin_interc, - char* parent_pin_prefix, - char** src_pin_prefix, - char** des_pin_prefix); - -void fprintf_spice_pb_graph_pin_interc(FILE* fp, - char* parent_pin_prefix, - enum e_spice_pin2pin_interc_type pin2pin_interc_type, - t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode, - int is_idle); - -void fprint_spice_pb_graph_interc(FILE* fp, - char* pin_prefix, - t_pb_graph_node* cur_pb_graph_node, - t_phy_pb* cur_pb, - int select_mode_index, - int is_idle); - -void fprint_spice_pb_graph_primitive_node(FILE* fp, - char* subckt_prefix, - t_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - int pb_type_index); - -void fprint_pb_primitive_spice_model(FILE* fp, - char* subckt_prefix, - t_phy_pb* prim_pb, - t_pb_graph_node* prim_pb_graph_node, - int pb_index, - t_spice_model* spice_model, - int is_idle); - -void fprint_spice_idle_pb_graph_node_rec(FILE* fp, - char* subckt_prefix, - t_pb_graph_node* cur_pb_graph_node, - int pb_type_index); - -void fprint_spice_pb_graph_node_rec(FILE* fp, - char* subckt_prefix, - t_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - int pb_type_index); - - -void fprint_spice_block(FILE* fp, - char* subckt_name, - int x, - int y, - int z, - t_type_ptr type_descriptor, - t_block* mapped_block); - -void fprint_grid_pins(FILE* fp, - int x, - int y, - int top_level); - -void fprint_io_grid_pins(FILE* fp, - int x, - int y, - int top_level); - -char* get_grid_block_subckt_name(int x, - int y, - int z, - char* subckt_prefix, - t_block* mapped_block); - -void fprint_grid_block_subckt_pins(FILE* fp, - int z, - t_type_ptr type_descriptor); - -void fprint_io_grid_block_subckt_pins(FILE* fp, - int x, - int y, - int z, - t_type_ptr type_descriptor); - -void fprint_grid_blocks(FILE* fp, - int ix, - int iy); - -void fprint_spice_idle_block(FILE* fp, - char* subckt_name, - int x, - int y, - int z, - t_type_ptr type_descriptor); - -void generate_spice_logic_blocks(char* subckt_dir, t_arch* arch); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive.c deleted file mode 100644 index 60c2c993f..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive.c +++ /dev/null @@ -1,193 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "rr_graph_swseg.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_bitstream_utils.h" -#include "spice_utils.h" -#include "spice_pbtypes.h" -#include "spice_primitive.h" - -void fprint_pb_primitive_generic(FILE* fp, - char* subckt_prefix, - t_phy_pb* prim_phy_pb, - t_pb_type* prim_pb_type, - int index, - t_spice_model* spice_model) { - int num_sram_port = 0; - t_spice_model_port** sram_port = NULL; - int i; - int num_sram = 0; - int expected_num_sram = 0; - int* sram_bits = NULL; - int cur_num_sram = 0; - int mapped_logical_block_index = OPEN; - - char* formatted_subckt_prefix = format_spice_node_prefix(subckt_prefix); /* Complete a "_" at the end if needed*/ - char* port_prefix = NULL; - char* sram_vdd_port_name = NULL; - - /* Ensure a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Asserts */ - assert((SPICE_MODEL_FF == spice_model->type) - ||(SPICE_MODEL_HARDLOGIC == spice_model->type) - ||(SPICE_MODEL_IOPAD == spice_model->type)); - - /* Find mapped logical block */ - if (NULL != prim_phy_pb) { - for (i = 0; i < prim_phy_pb->num_logical_blocks; i++) { - mapped_logical_block_index = prim_phy_pb->logical_block[i]; - /* Back-annotate to logical block */ - logical_block[mapped_logical_block_index].mapped_spice_model = spice_model; - logical_block[mapped_logical_block_index].mapped_spice_model_index = spice_model->cnt; - fprintf(fp, "***** Logical block mapped to this primitive node: %s *****\n", - logical_block[mapped_logical_block_index].name); - } - } - - /* Generate Subckt for pb_type*/ - /* - port_prefix = (char*)my_malloc(sizeof(char)* - (strlen(formatted_subckt_prefix) + strlen(prim_pb_type->name) + 1 - + strlen(my_itoa(index)) + 1 + 1)); - sprintf(port_prefix, "%s%s[%d]", formatted_subckt_prefix, prim_pb_type->name, index); - */ - /* Simplify the port prefix, make SPICE netlist readable */ - port_prefix = (char*)my_malloc(sizeof(char)* - (strlen(prim_pb_type->name) + 1 - + strlen(my_itoa(index)) + 1 + 1)); - sprintf(port_prefix, "%s[%d]", prim_pb_type->name, index); - - /* Decode SRAM bits */ - num_sram = count_num_sram_bits_one_spice_model(spice_model, -1); - sram_port = find_spice_model_ports(spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); - /* what is the SRAM bit of a mode? */ - /* If logical block is not NULL, we need to decode the sram bit */ - if ( 0 < num_sram_port) { - assert (1 == num_sram_port); - if (NULL != prim_phy_pb) { - sram_bits = decode_mode_bits(prim_phy_pb->mode_bits, &expected_num_sram); - } else { /* get default mode_bits */ - sram_bits = decode_mode_bits(prim_pb_type->mode_bits, &expected_num_sram); - } - assert(expected_num_sram == num_sram); - } - - /* Get current counter of mem_bits, bl and wl */ - cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info); - - /* Definition line */ - fprintf(fp, ".subckt %s%s ", formatted_subckt_prefix, port_prefix); - /* print ports*/ - fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type); - /* Local vdd and gnd*/ - fprintf(fp, "svdd sgnd\n"); - /* Definition ends*/ - - /* Call the iopad subckt*/ - fprintf(fp, "X%s[%d] ", spice_model->prefix, spice_model->cnt); - /* Only dump the global ports belonging to a spice_model - * Do not go recursive, we can freely define global ports anywhere in SPICE netlist - */ - if (0 < rec_fprint_spice_model_global_ports(fp, spice_model, FALSE)) { - fprintf(fp, "+ "); - } - /* print regular ports*/ - fprint_pb_type_ports(fp, port_prefix, 0, prim_pb_type); - /* Print inout port */ - if (SPICE_MODEL_IOPAD == spice_model->type) { - fprintf(fp, " %s%s[%d] ", - gio_inout_prefix, - spice_model->prefix, - spice_model->cnt); - } - /* Print SRAM ports */ - for (i = 0; i < num_sram; i++) { - fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_num_sram + i, sram_bits[i]); - /* We need the invertered signal for better convergency */ - fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, cur_num_sram + i, 1 - sram_bits[i]); - } - - /* Local vdd and gnd, spice_model name, - * TODO: Global vdd for i/o pad to split? - */ - fprintf(fp, "%s_%s[%d] sgnd %s\n", - spice_tb_global_vdd_port_name, - spice_model->prefix, - spice_model->cnt, - spice_model->name); - - - /* Print the encoding in SPICE netlist for debugging */ - fprintf(fp, "***** SRAM bits for %s[%d] *****\n", - spice_model->prefix, - spice_model->cnt); - fprintf(fp, "*****"); - for (i = 0; i < num_sram; i++) { - fprintf(fp, "%d", sram_bits[i]); - } - fprintf(fp, "*****\n"); - - /* Call SRAM subckts*/ - /* Give the VDD port name for SRAMs */ - sram_vdd_port_name = (char*)my_malloc(sizeof(char)* - (strlen(spice_tb_global_vdd_io_sram_port_name) - + 1 )); - sprintf(sram_vdd_port_name, "%s", - spice_tb_global_vdd_io_sram_port_name); - /* Now Print SRAMs one by one */ - for (i = 0; i < num_sram; i++) { - fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, spice_model, sram_vdd_port_name); - } - - /* Store the configuraion bit to linked-list */ - add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_num_sram, - num_sram, sram_bits); - - /* End */ - fprintf(fp, ".eom\n"); - - /* Update the spice_model counter */ - spice_model->cnt++; - - /*Free*/ - my_free(formatted_subckt_prefix); - my_free(port_prefix); - my_free(sram_vdd_port_name); - my_free(sram_port); - - return; -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive.h deleted file mode 100644 index 77dd4ee21..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive.h +++ /dev/null @@ -1,8 +0,0 @@ - - -void fprint_pb_primitive_generic(FILE* fp, - char* subckt_prefix, - t_phy_pb* prim_phy_pb, - t_pb_type* prim_pb_type, - int index, - t_spice_model* spice_model); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive_testbench.c deleted file mode 100644 index 07ede11e0..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive_testbench.c +++ /dev/null @@ -1,1106 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "spice_utils.h" -#include "spice_mux.h" -#include "spice_pbtypes.h" -#include "spice_subckt.h" - -/* local global variables */ -static int tb_num_primitive = 0; -static int testbench_load_cnt = 0; -static int upbound_sim_num_clock_cycles = 2; -static int max_sim_num_clock_cycles = 2; -static int auto_select_max_sim_num_clock_cycles = TRUE; - -/* Subroutines in this source file*/ -/* Initialize the global parameters in this source file */ -static -void init_spice_primitive_testbench_globals(t_spice spice) { - tb_num_primitive = 0; - auto_select_max_sim_num_clock_cycles = spice.spice_params.meas_params.auto_select_sim_num_clk_cycle; - upbound_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; - if (FALSE == auto_select_max_sim_num_clock_cycles) { - max_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; - } else { - max_sim_num_clock_cycles = 2; - } -} - -/* Print Common global ports in the testbench */ -static -void fprint_spice_primitive_testbench_global_ports(FILE* fp, int grid_x, int grid_y, - int num_clock, - enum e_spice_tb_type primitive_tb_type, - t_spice spice) { - /* int i; */ - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ - /* Print generic global ports*/ - fprint_spice_generic_testbench_global_ports(fp, - sram_spice_orgz_info, - global_ports_head); - /* VDD Load port name */ - fprintf(fp, ".global %s\n", - spice_tb_global_vdd_load_port_name); - - /*Global Vdds for PRIMITIVEs */ - switch (primitive_tb_type) { - case SPICE_LUT_TB: - fprint_grid_global_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_LUT, spice); - break; - case SPICE_HARDLOGIC_TB: - fprint_grid_global_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, spice); - fprint_grid_global_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, spice); - break; - case SPICE_IO_TB: - fprint_grid_global_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_IOPAD, spice); - /* Global VDDs for SRAMs of IOPADs */ - fprintf(fp, ".global %s\n\n", - spice_tb_global_vdd_io_sram_port_name); - - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid primitive_tb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -/* Dump the subckt of a hardlogic and also the input stimuli */ -void fprint_spice_primitive_testbench_call_one_primitive(FILE* fp, - char* subckt_name, - char* primitive_type, - t_spice_model* primitive_spice_model) { - int iport, ipin; - - int num_input_port = 0; - t_spice_model_port** input_ports = NULL; - int num_output_port = 0; - t_spice_model_port** output_ports = NULL; - t_spice_model_port** inout_ports = NULL; - int num_clk_port = 0; - t_spice_model_port** clk_ports = NULL; - - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert(NULL != primitive_spice_model); - - /* identify the type of spice model */ - /* Call defined subckt */ - fprintf(fp, "X%s_%s[%d] \n+ ", - primitive_type, - primitive_spice_model->prefix, - primitive_spice_model->tb_cnt); - - /* Sequence in dumping ports: - * 1. Global ports - INCLUDED IN THE MODULE, SO WE SKIP THIS - * 2. Input ports - * 3. Output ports - * 4. Inout ports - * 5. Configuration ports - * 6. VDD and GND ports - */ - - /* 2. Input ports (TODO: check the number of inputs matches the spice model definition) */ - /* Find pb_type input ports */ - input_ports = find_spice_model_ports(primitive_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - for (iport = 0; iport < num_input_port; iport++) { - for (ipin = 0; ipin < input_ports[iport]->size; ipin++) { - fprintf(fp, "%s_%s[%d]->%s[%d] ", - primitive_type, - primitive_spice_model->prefix, - primitive_spice_model->tb_cnt, - input_ports[iport]->prefix, ipin); - } - } - if (NULL != input_ports) { - fprintf(fp, "\n"); - fprintf(fp, "+ "); - } - - /* 3. Output ports */ - /* Find pb_type output ports */ - output_ports = find_spice_model_ports(primitive_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - for (iport = 0; iport < num_output_port; iport++) { - for (ipin = 0; ipin < output_ports[iport]->size; ipin++) { - fprintf(fp, "%s_%s[%d]->%s[%d] ", - primitive_type, - primitive_spice_model->prefix, - primitive_spice_model->tb_cnt, - output_ports[iport]->prefix, ipin); - } - } - if (NULL != output_ports) { - fprintf(fp, "\n"); - fprintf(fp, "+ "); - } - - /* 4. Inout ports: INOUTs are currently global ports, so we do not put it here. */ - /* INOUT ports */ - /* Find pb_type inout ports */ - /* - inout_ports = find_spice_model_ports(primitive_spice_model, SPICE_MODEL_PORT_INOUT, &num_inout_port, TRUE); - for (iport = 0; iport < num_inout_port; iport++) { - for (ipin = 0; ipin < inout_ports[iport]->size; ipin++) { - fprintf(fp, "%s_%s[%d]->%s[%d] ", - primitive_type, - primitive_spice_model->prefix, - primitive_spice_model->tb_cnt, - inout_ports[iport]->prefix, ipin); - } - } - if (NULL != inout_ports) { - fprintf(fp, "\n"); - fprintf(fp, "+ "); - } - */ - - /* Clocks */ - /* Identify if the clock port is a global signal */ - /* Find pb_type clock ports */ - clk_ports = find_spice_model_ports(primitive_spice_model, SPICE_MODEL_PORT_CLOCK, &num_clk_port, TRUE); - for (iport = 0; iport < num_clk_port; iport++) { - for (ipin = 0; ipin < clk_ports[iport]->size; ipin++) { - fprintf(fp, "%s_%s[%d]->%s[%d] ", - primitive_type, - primitive_spice_model->prefix, - primitive_spice_model->tb_cnt, - clk_ports[iport]->prefix, ipin); - } - } - if (NULL != clk_ports) { - fprintf(fp, "\n"); - fprintf(fp, "+ "); - } - - /* 5. Configuration ports */ - /* Generate SRAMs? */ - - /* 6. VDD and GND ports */ - fprintf(fp, "%s_%s[%d] %s ", - spice_tb_global_vdd_port_name, - primitive_spice_model->prefix, - primitive_spice_model->tb_cnt, - spice_tb_global_gnd_port_name); - fprintf(fp, "\n"); - fprintf(fp, "+ "); - - /* Call the name of subckt */ - fprintf(fp, "%s\n", subckt_name); - - /* Free */ - my_free(input_ports); - my_free(output_ports); - my_free(inout_ports); - my_free(clk_ports); - - return; -} - -void fprint_spice_primitive_testbench_one_primitive_input_stimuli(FILE* fp, - t_phy_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - char* prefix, - int x, int y, - char* primitive_type, - t_ivec*** LL_rr_node_indices) { - int iport, ipin; - t_spice_model* pb_spice_model = cur_pb_graph_node->pb_type->spice_model; - t_rr_node* local_rr_graph = NULL; - - /* For pb_spice_model */ - int num_input_port; - t_spice_model_port** input_ports; - - /* Two-dimension arrays, corresponding to the port map [port_id][pin_id] */ - float** input_density = NULL; - float** input_probability = NULL; - int** input_init_value = NULL; - int** input_net_num = NULL; - - float average_density = 0.; - int avg_density_cnt = 0; - int num_sim_clock_cycles = 0; - - /* Malloc */ - /* First dimension */ - input_density = (float**)my_malloc(sizeof(float*) * cur_pb_graph_node->num_input_ports); - input_probability = (float**)my_malloc(sizeof(float*) * cur_pb_graph_node->num_input_ports); - input_init_value = (int**)my_malloc(sizeof(int*) * cur_pb_graph_node->num_input_ports); - input_net_num = (int**)my_malloc(sizeof(int*) * cur_pb_graph_node->num_input_ports); - /* Second dimension */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - input_density[iport] = (float*)my_malloc(sizeof(float) * cur_pb_graph_node->num_input_pins[iport]); - input_probability[iport] = (float*)my_malloc(sizeof(float) * cur_pb_graph_node->num_input_pins[iport]); - input_init_value[iport] = (int*)my_malloc(sizeof(int) * cur_pb_graph_node->num_input_pins[iport]); - input_net_num[iport] = (int*)my_malloc(sizeof(int) * cur_pb_graph_node->num_input_pins[iport]); - } - - /* Get activity information */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - /* if we find a mapped logic block */ - if (NULL != cur_pb) { - local_rr_graph = cur_pb->rr_graph->rr_node; - } else { - local_rr_graph = NULL; - } - input_net_num[iport][ipin] = pb_pin_net_num(local_rr_graph, &(cur_pb_graph_node->input_pins[iport][ipin])); - input_density[iport][ipin] = pb_pin_density(local_rr_graph, &(cur_pb_graph_node->input_pins[iport][ipin])); - input_probability[iport][ipin] = pb_pin_probability(local_rr_graph, &(cur_pb_graph_node->input_pins[iport][ipin])); - input_init_value[iport][ipin] = pb_pin_init_value(local_rr_graph, &(cur_pb_graph_node->input_pins[iport][ipin])); - } - } - - /* Add Input stimulates */ - /* Get the input port list of spice model */ - input_ports = find_spice_model_ports(pb_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - /* Check if the port map of current pb_graph_node matches that of the spice model !!!*/ - assert(num_input_port == cur_pb_graph_node->num_input_ports); - for (iport = 0; iport < num_input_port; iport++) { - assert(input_ports[iport]->size == cur_pb_graph_node->num_input_pins[iport]); - for (ipin = 0; ipin < input_ports[iport]->size; ipin++) { - /* Check the port size should match!*/ - fprintf(fp, "V%s_%s[%d]->%s[%d] %s_%s[%d]->%s[%d] 0 \n", - primitive_type, - pb_spice_model->prefix, - pb_spice_model->tb_cnt, - cur_pb_graph_node->input_pins[iport]->port->name, - ipin, - primitive_type, - pb_spice_model->prefix, - pb_spice_model->tb_cnt, - input_ports[iport]->prefix, - ipin); - fprint_voltage_pulse_params(fp, input_init_value[iport][ipin], input_density[iport][ipin], input_probability[iport][ipin]); - } - } - - /* Calculate average density of this hardlogic */ - average_density = 0.; - avg_density_cnt = 0; - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < cur_pb_graph_node->num_input_pins[iport]; ipin++) { - assert(!(0 > input_density[iport][ipin])); - if (0. < input_density[iport][ipin]) { - average_density += input_density[iport][ipin]; - avg_density_cnt++; - } - } - } - /* Calculate the num_sim_clock_cycle for this MUX, update global max_sim_clock_cycle in this testbench */ - if (0 < avg_density_cnt) { - average_density = average_density/avg_density_cnt; - } else { - assert(0 == avg_density_cnt); - average_density = 0.; - } - if (0. == average_density) { - num_sim_clock_cycles = 2; - } else { - assert(0. < average_density); - num_sim_clock_cycles = (int)(1/average_density) + 1; - } - if (TRUE == auto_select_max_sim_num_clock_cycles) { - /* for idle blocks, 2 clock cycle is well enough... */ - if (2 < num_sim_clock_cycles) { - num_sim_clock_cycles = upbound_sim_num_clock_cycles; - } else { - num_sim_clock_cycles = 2; - } - if (max_sim_num_clock_cycles < num_sim_clock_cycles) { - max_sim_num_clock_cycles = num_sim_clock_cycles; - } - } else { - num_sim_clock_cycles = max_sim_num_clock_cycles; - } - - /* Free */ - for (iport = 0; iport < cur_pb_graph_node->num_input_ports; iport++) { - my_free(input_net_num[iport]); - my_free(input_init_value[iport]); - my_free(input_density[iport]); - my_free(input_probability[iport]); - } - my_free(input_net_num); - my_free(input_init_value); - my_free(input_density); - my_free(input_probability); - my_free(input_ports); - - return; -} - -void fprint_spice_primitive_testbench_one_primitive_output_loads(FILE* fp, - t_phy_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - char* prefix, - int x, int y, - char* primitive_type, - t_ivec*** LL_rr_node_indices) { - int iport, ipin; - int num_output_port = 0; - t_spice_model_port** output_ports = NULL; - t_spice_model* pb_spice_model = cur_pb_graph_node->pb_type->spice_model; - char* outport_name = NULL; - - /* Add loads: Recursively */ - /* Get the output port list of spice model */ - output_ports = find_spice_model_ports(pb_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - for (iport = 0; iport < num_output_port; iport++) { - for (ipin = 0; ipin < output_ports[iport]->size; ipin++) { - outport_name = (char*)my_malloc(sizeof(char)*( strlen(primitive_type) + 1 - + strlen(pb_spice_model->prefix) + 1 - + strlen(my_itoa(pb_spice_model->tb_cnt)) - + 3 + strlen(output_ports[iport]->prefix) + 1 - + strlen(my_itoa(ipin)) + 2 )); - sprintf(outport_name, "%s_%s[%d]->%s[%d]", - primitive_type, - pb_spice_model->prefix, - pb_spice_model->tb_cnt, - output_ports[iport]->prefix, - ipin); - if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ - if (NULL != cur_pb) { - fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, - x, y, - &(cur_pb_graph_node->output_pins[0][0]), - cur_pb, - outport_name, - FALSE, - LL_rr_node_indices); - } else { - fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, - x, y, - &(cur_pb_graph_node->output_pins[0][0]), - NULL, - outport_name, - FALSE, - LL_rr_node_indices); - } - } - /* Free outport_name in each iteration */ - my_free(outport_name); - } - } - - /* Free */ - my_free(output_ports); - - return; -} - -/** Core function: print the main body of this testbench - * 1. Print the primitive subckt - * 2. Add input stimuli - * 3. Add loads - */ -void fprint_spice_primitive_testbench_one_pb_primitive(FILE* fp, - t_phy_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - char* prefix, - int x, int y, - enum e_spice_tb_type primitive_tb_type, - t_ivec*** LL_rr_node_indices) { - t_spice_model* pb_spice_model = NULL; - char* primitive_type = NULL; - - assert(NULL != cur_pb_graph_node); - assert(NULL != prefix); - - pb_spice_model = cur_pb_graph_node->pb_type->spice_model; - - /* Name the primitive subckt */ - switch (primitive_tb_type) { - case SPICE_LUT_TB: - primitive_type = "lut"; - /* If the spice model is not the type we want, return here */ - if (SPICE_MODEL_LUT != pb_spice_model->type) { - return; - } - break; - case SPICE_HARDLOGIC_TB: - primitive_type = "hardlogic"; - /* If the spice model is not the type we want, return here */ - if ((SPICE_MODEL_FF != pb_spice_model->type) - && (SPICE_MODEL_HARDLOGIC != pb_spice_model->type)) { - return; - } - break; - case SPICE_IO_TB: - primitive_type = "io"; - /* If the spice model is not the type we want, return here */ - if (SPICE_MODEL_IOPAD != pb_spice_model->type) { - return; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid primitive_tb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Now, we print the SPICE subckt of a hard logic */ - fprint_spice_primitive_testbench_call_one_primitive(fp, - prefix, - primitive_type, - pb_spice_model); - - /* Add input stimuli */ - fprint_spice_primitive_testbench_one_primitive_input_stimuli(fp, - cur_pb, - cur_pb_graph_node, - prefix, - x, y, - primitive_type, - LL_rr_node_indices); - - /* Add loads */ - fprint_spice_primitive_testbench_one_primitive_output_loads(fp, - cur_pb, - cur_pb_graph_node, - prefix, - x, y, - primitive_type, - LL_rr_node_indices); - - /* Increment the counter of the hardlogic spice model */ - pb_spice_model->tb_cnt++; - tb_num_primitive++; - - return; -} - -void fprint_spice_primitive_testbench_rec_pb_primitives(FILE* fp, - t_phy_pb* cur_pb, - t_pb_graph_node* cur_pb_graph_node, - char* prefix, - int x, int y, - enum e_spice_tb_type primitive_tb_type, - t_ivec*** LL_rr_node_indices) { - char* formatted_prefix = format_spice_node_prefix(prefix); - int ipb, jpb; - int mode_index; - char* rec_prefix = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - if (NULL == cur_pb) { - assert(NULL != cur_pb_graph_node); - } else { - assert (cur_pb_graph_node == cur_pb->pb_graph_node); - } - - /* If we touch the leaf, there is no need print interc*/ - if (TRUE == is_primitive_pb_type(cur_pb_graph_node->pb_type)) { - /* Generate rec_prefix */ - rec_prefix = (char*)my_malloc(sizeof(char) * (strlen(formatted_prefix) - + strlen(cur_pb_graph_node->pb_type->name) + 1 - + strlen(my_itoa(cur_pb_graph_node->placement_index)) - + 1 + 1)); - sprintf(rec_prefix, "%s%s[%d]", - formatted_prefix, - cur_pb_graph_node->pb_type->name, - cur_pb_graph_node->placement_index); - /* Print a lut tb: call spice_model, stimulates */ - fprint_spice_primitive_testbench_one_pb_primitive(fp, - cur_pb, - cur_pb_graph_node, - rec_prefix, x, y, - primitive_tb_type, - LL_rr_node_indices); - my_free(rec_prefix); - return; - } - - /* Go recursively ... */ - if (NULL == cur_pb) { - mode_index = find_pb_type_physical_mode_index(*(cur_pb_graph_node->pb_type)); - } else { - mode_index = cur_pb->mode; - } - - if (!(0 < cur_pb_graph_node->pb_type->num_modes)) { - return; - } - for (ipb = 0; ipb < cur_pb_graph_node->pb_type->modes[mode_index].num_pb_type_children; ipb++) { - for (jpb = 0; jpb < cur_pb_graph_node->pb_type->modes[mode_index].pb_type_children[ipb].num_pb; jpb++) { - /* Generate rec_prefix */ - rec_prefix = (char*)my_malloc(sizeof(char) * (strlen(formatted_prefix) - + strlen(cur_pb_graph_node->pb_type->name) + 1 - + strlen(my_itoa(cur_pb_graph_node->placement_index)) + 7 - + strlen(cur_pb_graph_node->pb_type->modes[mode_index].name) + 1 + 1)); - sprintf(rec_prefix, "%s%s[%d]_mode[%s]", - formatted_prefix, cur_pb_graph_node->pb_type->name, - cur_pb_graph_node->placement_index, - cur_pb_graph_node->pb_type->modes[mode_index].name); - if (((NULL == cur_pb) - || ((NULL == cur_pb->child_pbs[ipb])||(NULL == cur_pb->child_pbs[ipb][jpb].name)))) { - /* Then we go on */ - fprint_spice_primitive_testbench_rec_pb_primitives(fp, - NULL, - &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), - rec_prefix, x, y, - primitive_tb_type, - LL_rr_node_indices); - } else { - assert ((NULL != cur_pb->child_pbs[ipb])&&(NULL != cur_pb->child_pbs[ipb][jpb].name)); - /* Refer to pack/output_clustering.c [LINE 392] */ - fprint_spice_primitive_testbench_rec_pb_primitives(fp, - &(cur_pb->child_pbs[ipb][jpb]), - cur_pb->child_pbs[ipb][jpb].pb_graph_node, - rec_prefix, x, y, - primitive_tb_type, - LL_rr_node_indices); - } - } - } - - return; -} - -void fprint_spice_primitive_testbench_call_one_grid_defined_primitives(FILE* fp, - int ix, int iy, - enum e_spice_tb_type primitive_tb_type, - t_ivec*** LL_rr_node_indices) { - int iblk; - char* prefix = NULL; - - if ((NULL == grid[ix][iy].type) - ||(EMPTY_TYPE == grid[ix][iy].type) - ||(0 != grid[ix][iy].offset)) { - return; - } - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d])Invalid File Handler!\n", - __FILE__, __LINE__); - exit(1); - } - - for (iblk = 0; iblk < grid[ix][iy].usage; iblk++) { - prefix = (char*)my_malloc(sizeof(char)* (5 - + strlen(my_itoa(ix)) - + 2 + strlen(my_itoa(iy)) - + 3 )); - sprintf(prefix, "grid[%d][%d]_", - ix, - iy); - /* Only for mapped block */ - assert(NULL != block[grid[ix][iy].blocks[iblk]].phy_pb); - /* It is weird that some used block has an invalid ID */ - if (OPEN == grid[ix][iy].blocks[iblk]) { - /* Mark the temporary net_num for the type pins*/ - mark_grid_type_pb_graph_node_pins_temp_net_num(ix, iy); - /* Go into the hierachy and dump hardlogics */ - fprint_spice_primitive_testbench_rec_pb_primitives(fp, - NULL, - grid[ix][iy].type->pb_graph_head, - prefix, ix, iy, - primitive_tb_type, - LL_rr_node_indices); - continue; - } - /* Mark the temporary net_num for the type pins*/ - mark_one_pb_parasitic_nets((t_phy_pb*)block[grid[ix][iy].blocks[iblk]].phy_pb); - /* Go into the hierachy and dump hardlogics */ - fprint_spice_primitive_testbench_rec_pb_primitives(fp, - (t_phy_pb*)block[grid[ix][iy].blocks[iblk]].phy_pb, - grid[ix][iy].type->pb_graph_head, - prefix, ix, iy, - primitive_tb_type, - LL_rr_node_indices); - /* Free */ - my_free(prefix); - } - /* Bypass unused blocks */ - for (iblk = grid[ix][iy].usage; iblk < grid[ix][iy].type->capacity; iblk++) { - prefix = (char*)my_malloc(sizeof(char)* (5 + strlen(my_itoa(ix)) - + 2 + strlen(my_itoa(iy)) + 3 )); - sprintf(prefix, "grid[%d][%d]_", ix, iy); - assert(NULL != grid[ix][iy].type->pb_graph_head); - /* Mark the temporary net_num for the type pins*/ - mark_grid_type_pb_graph_node_pins_temp_net_num(ix, iy); - /* Go into the hierachy and dump hardlogics */ - fprint_spice_primitive_testbench_rec_pb_primitives(fp, - NULL, - grid[ix][iy].type->pb_graph_head, - prefix, ix, iy, - primitive_tb_type, - LL_rr_node_indices); - /* Free */ - my_free(prefix); - } - - return; -} - -static -void fprint_spice_primitive_testbench_stimulations(FILE* fp, int grid_x, int grid_y, - int num_clocks, - t_spice spice, - enum e_spice_tb_type primitive_tb_type, - t_ivec*** LL_rr_node_indices) { - /* Print generic stimuli */ - fprint_spice_testbench_generic_global_ports_stimuli(fp, num_clocks); - - /* Generate global ports stimuli */ - fprint_spice_testbench_global_ports_stimuli(fp, global_ports_head); - - /* SRAM ports */ - fprintf(fp, "***** Global Inputs for SRAMs *****\n"); - fprint_spice_testbench_global_sram_inport_stimuli(fp, sram_spice_orgz_info); - - fprintf(fp, "***** Global VDD for SRAMs *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_sram_port_name, - "vsp"); - - fprintf(fp, "***** Global VDD for load inverters *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_load_port_name, - "vsp"); - - switch (primitive_tb_type) { - case SPICE_LUT_TB: - /* Every LUT use an independent Voltage source */ - fprintf(fp, "***** Global VDD for LUTs *****\n"); - fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_LUT, spice); - break; - case SPICE_HARDLOGIC_TB: - /* Every Hardlogic use an independent Voltage source */ - fprintf(fp, "***** Global VDD for FFs *****\n"); - fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, spice); - fprintf(fp, "***** Global VDD for Hardlogics *****\n"); - fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, spice); - break; - case SPICE_IO_TB: - /* Every IO use an independent Voltage source */ - fprintf(fp, "***** Global VDD for IOs *****\n"); - fprint_grid_splited_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_IOPAD, spice); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid primitive_tb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -void fprint_spice_primitive_testbench_measurements(FILE* fp, int grid_x, int grid_y, - t_spice spice, - enum e_spice_tb_type primitive_tb_type, - boolean leakage_only) { - - /* int i; */ - /* First cycle reserved for measuring leakage */ - int num_clock_cycle = max_sim_num_clock_cycles; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - fprint_spice_netlist_transient_setting(fp, spice, num_clock_cycle, leakage_only); - fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); - - /* TODO: Measure the delay of each mapped net and logical block */ - - /* Measure the power */ - /* Leakage ( the first cycle is reserved for leakage measurement) */ - switch (primitive_tb_type) { - case SPICE_LUT_TB: - /* Leakage power of LUTs*/ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_LUT, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); - break; - case SPICE_HARDLOGIC_TB: - /* Leakage power of FFs*/ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); - /* Leakage power of Hardlogic */ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); - break; - case SPICE_IO_TB: - /* Leakage power of LUTs*/ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_IOPAD, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid primitive_tb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - if (TRUE == leakage_only) { - return; - } - - /* Dynamic power */ - switch (primitive_tb_type) { - case SPICE_LUT_TB: - /* Dynamic power of FFs */ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_LUT, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); - break; - case SPICE_HARDLOGIC_TB: - /* Dynamic power of FFs */ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_FF, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); - /* Dynamic power of Hardlogics */ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_HARDLOGIC, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); - break; - case SPICE_IO_TB: - /* Dynamic power of FFs */ - fprint_measure_grid_vdds_spice_model(fp, grid_x, grid_y, SPICE_MODEL_IOPAD, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid primitive_tb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -/* Top-level function in this source file */ -int fprint_spice_one_primitive_testbench(char* formatted_spice_dir, - char* circuit_name, - char* primitive_testbench_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clock, - t_arch arch, - int grid_x, int grid_y, - enum e_spice_tb_type primitive_tb_type, - boolean leakage_only) { - FILE* fp = NULL; - char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); - char* temp_include_file_path = NULL; - char* title = NULL; - char* primitive_testbench_file_path = NULL; - int used; - - /* Name the testbench */ - switch (primitive_tb_type) { - case SPICE_LUT_TB: - title = my_strcat("FPGA LUT Testbench for Design: ", circuit_name); - /* vpr_printf(TIO_MESSAGE_INFO, "Writing LUT Testbench for %s...\n", circuit_name); */ - break; - case SPICE_HARDLOGIC_TB: - title = my_strcat("FPGA Hard Logic Testbench for Design: ", circuit_name); - /* vpr_printf(TIO_MESSAGE_INFO, "Writing Hard Logic Testbench for %s...\n", circuit_name); */ - break; - case SPICE_IO_TB: - title = my_strcat("FPGA IO Testbench for Design: ", circuit_name); - /* vpr_printf(TIO_MESSAGE_INFO, "Writing IO Testbench for %s...\n", circuit_name); */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid primitive_tb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - primitive_testbench_file_path = my_strcat(formatted_spice_dir, primitive_testbench_name); - - /* Check if the path exists*/ - fp = fopen(primitive_testbench_file_path,"w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create Primitive Testbench SPICE netlist %s!", - __FILE__, __LINE__, - primitive_testbench_file_path); - exit(1); - } - - /* Reset tb_cnt for all the spice models */ - init_spice_models_grid_tb_cnt(arch.spice->num_spice_model, arch.spice->spice_models, grid_x, grid_y); - - testbench_load_cnt = 0; - - /* Print the title */ - fprint_spice_head(fp, title); - my_free(title); - - /* print technology library and design parameters*/ - /* fprint_tech_lib(fp, arch.spice->tech_lib);*/ - - /* Include parameter header files */ - fprint_spice_include_param_headers(fp, include_dir_path); - - /* Include Key subckts */ - fprint_spice_include_key_subckts(fp, subckt_dir_path); - - /* Include user-defined sub-circuit netlist */ - init_include_user_defined_netlists(*(arch.spice)); - fprint_include_user_defined_netlists(fp, *(arch.spice)); - - fprintf(fp, "****** Include subckt netlists: LUTs *****\n"); - temp_include_file_path = my_strcat(formatted_subckt_dir_path, luts_spice_file_name); - fprintf(fp, ".include \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - - /* Generate filename */ - fprintf(fp, "****** Include subckt netlists: Grid[%d][%d] *****\n", - grid_x, grid_y); - temp_include_file_path = fpga_spice_create_one_subckt_filename(grid_spice_file_name_prefix, grid_x, grid_y, spice_netlist_file_postfix); - /* Check if we include an existing file! */ - if (FALSE == check_subckt_file_exist_in_llist(grid_spice_subckt_file_path_head, - my_strcat(formatted_subckt_dir_path, temp_include_file_path))) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Intend to include a non-existed SPICE netlist %s!\n", - __FILE__, __LINE__, temp_include_file_path); - exit(1); - } - spice_print_one_include_subckt_line(fp, formatted_subckt_dir_path, temp_include_file_path); - - - /* Print simulation temperature and other options for SPICE */ - fprint_spice_options(fp, arch.spice->spice_params); - - /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ - fprint_spice_primitive_testbench_global_ports(fp, - grid_x, grid_y, num_clock, - primitive_tb_type, - (*arch.spice)); - - /* Initialize global variables in this testbench */ - init_spice_primitive_testbench_globals(*(arch.spice)); - - /* Quote defined Logic blocks subckts (Grids) */ - switch (primitive_tb_type) { - case SPICE_LUT_TB: - init_logical_block_spice_model_type_temp_used(arch.spice->num_spice_model, - arch.spice->spice_models, - SPICE_MODEL_LUT); - break; - case SPICE_HARDLOGIC_TB: - init_logical_block_spice_model_type_temp_used(arch.spice->num_spice_model, - arch.spice->spice_models, - SPICE_MODEL_FF); - init_logical_block_spice_model_type_temp_used(arch.spice->num_spice_model, - arch.spice->spice_models, - SPICE_MODEL_HARDLOGIC); - break; - case SPICE_IO_TB: - init_logical_block_spice_model_type_temp_used(arch.spice->num_spice_model, - arch.spice->spice_models, - SPICE_MODEL_IOPAD); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid primitive_tb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Now start our job formally: dump hard logic circuit one by one */ - fprint_spice_primitive_testbench_call_one_grid_defined_primitives(fp, - grid_x, grid_y, - primitive_tb_type, - LL_rr_node_indices); - - /* Back-anotate activity information to each routing resource node - * (We should have activity of each Grid port) - */ - - /* Check if the all hardlogic located in this grid have been printed */ - switch (primitive_tb_type) { - case SPICE_LUT_TB: - check_spice_models_grid_tb_cnt(arch.spice->num_spice_model, arch.spice->spice_models, grid_x, grid_y, SPICE_MODEL_LUT); - break; - case SPICE_HARDLOGIC_TB: - check_spice_models_grid_tb_cnt(arch.spice->num_spice_model, arch.spice->spice_models, grid_x, grid_y, SPICE_MODEL_FF); - check_spice_models_grid_tb_cnt(arch.spice->num_spice_model, arch.spice->spice_models, grid_x, grid_y, SPICE_MODEL_HARDLOGIC); - break; - case SPICE_IO_TB: - check_spice_models_grid_tb_cnt(arch.spice->num_spice_model, arch.spice->spice_models, grid_x, grid_y, SPICE_MODEL_IOPAD); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid primitive_tb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Add stimulations */ - fprint_spice_primitive_testbench_stimulations(fp, grid_x, grid_y, num_clock, (*arch.spice), primitive_tb_type, LL_rr_node_indices); - - /* Add measurements */ - fprint_spice_primitive_testbench_measurements(fp, grid_x, grid_y, (*arch.spice), primitive_tb_type, leakage_only); - - /* SPICE ends*/ - fprintf(fp, ".end\n"); - - /* Close the file*/ - fclose(fp); - - if (0 < tb_num_primitive) { - /* - vpr_printf(TIO_MESSAGE_INFO, "Writing Grid[%d][%d] SPICE Hard Logic Testbench for %s...\n", - grid_x, grid_y, circuit_name); - */ - /* Push the testbench to the linked list */ - tb_head = add_one_spice_tb_info_to_llist(tb_head, primitive_testbench_file_path, - max_sim_num_clock_cycles); - used = 1; - } else { - /* Remove the file generated */ - my_remove_file(primitive_testbench_file_path); - used = 0; - } - - return used; -} - -/* Top-level function in this source file */ -void spice_print_primitive_testbench(char* formatted_spice_dir, - char* circuit_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clock, - t_arch arch, - enum e_spice_tb_type primitive_tb_type, - boolean leakage_only) { - char* primitive_testbench_name = NULL; - char* primitive_testbench_postfix = NULL; - int ix, iy; - int cnt = 0; - int used = 0; - - - /* Other testbenches consider the core logic only */ - for (ix = 0; ix < (nx + 2); ix++) { - for (iy = 0; iy < (ny + 2); iy++) { - /* Bypass EMPTY GRIDs */ - if (EMPTY_TYPE == grid[ix][iy].type) { - continue; - } - /* If this is a block on perimeter, - * bypass the grid unless IO_testbench is required - */ - if ( ( (nx + 1 == ix) || (0 == ix) - || (ny + 1 == iy) || (0 == iy) ) - && (SPICE_IO_TB != primitive_tb_type)) { - continue; - } - /* Name the testbench */ - switch (primitive_tb_type) { - case SPICE_LUT_TB: - primitive_testbench_postfix = spice_lut_testbench_postfix; - break; - case SPICE_HARDLOGIC_TB: - primitive_testbench_postfix = spice_hardlogic_testbench_postfix; - break; - case SPICE_IO_TB: - primitive_testbench_postfix = spice_io_testbench_postfix; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid primitive_tb_type!\n", - __FILE__, __LINE__); - exit(1); - } - primitive_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) - + 6 + strlen(my_itoa(ix)) + 1 - + strlen(my_itoa(iy)) + 1 - + strlen(primitive_testbench_postfix) + 1 )); - sprintf(primitive_testbench_name, "%s_grid%d_%d%s", - circuit_name, ix, iy, primitive_testbench_postfix); - /* Start building one testbench */ - used = fprint_spice_one_primitive_testbench(formatted_spice_dir, - circuit_name, primitive_testbench_name, - include_dir_path, subckt_dir_path, LL_rr_node_indices, - num_clock, arch, ix, iy, - primitive_tb_type, - leakage_only); - if (1 == used) { - cnt += used; - } - /* free */ - my_free(primitive_testbench_name); - } - } - /* Update the global counter */ - switch (primitive_tb_type) { - case SPICE_LUT_TB: - num_used_lut_tb = cnt; - vpr_printf(TIO_MESSAGE_INFO, - "No. of generated LUT testbench = %d\n", - num_used_lut_tb); - break; - case SPICE_HARDLOGIC_TB: - num_used_hardlogic_tb = cnt; - vpr_printf(TIO_MESSAGE_INFO, - "No. of generated hardlogic testbench = %d\n", - num_used_hardlogic_tb); - break; - case SPICE_IO_TB: - num_used_io_tb = cnt; - vpr_printf(TIO_MESSAGE_INFO, - "No. of generated IO testbench = %d\n", - num_used_io_tb); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid primitive_tb_type!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive_testbench.h deleted file mode 100644 index 09d46c206..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_primitive_testbench.h +++ /dev/null @@ -1,10 +0,0 @@ - -void spice_print_primitive_testbench(char* formatted_spice_dir, - char* circuit_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clock, - t_arch arch, - enum e_spice_tb_type primitive_tb_type, - boolean leakage_only); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c deleted file mode 100644 index 73353e59d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c +++ /dev/null @@ -1,1313 +0,0 @@ -/********************************************************** - * MIT License - * - * Copyright (c) 2018 LNIS - The University of Utah - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - ***********************************************************************/ - -/************************************************************************ - * Filename: spice_routing.c - * Created by: Xifan Tang - * Change history: - * +-------------------------------------+ - * | Date | Author | Notes - * +-------------------------------------+ - * | 2019/07/02 | Xifan Tang | Created - * +-------------------------------------+ - ***********************************************************************/ -/************************************************************************ - * This file contains functions to output SPICE netlists of routing resources - * i.e., Switch Block(SB), Connection Block (CB) and routing channels. - * Each module will be placed in an individual subckt, which be called - * through SPICE testbenches - * Note that each subckt is a configured module (SB, CB or Routing channals) - ***********************************************************************/ - -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include FPGA-SPICE support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_mux_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "fpga_x2p_bitstream_utils.h" - -/* Include SPICE support headers*/ -#include "spice_utils.h" -#include "spice_mux.h" -#include "spice_lut.h" -#include "fpga_x2p_backannotate_utils.h" -#include "spice_routing.h" - -static -void fprint_routing_chan_subckt(char* subckt_dir, - int x, int y, t_rr_type chan_type, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - int num_segment, t_segment_inf* segments) { - int itrack, iseg, cost_index; - char* chan_prefix = NULL; - int chan_width = 0; - t_rr_node** chan_rr_nodes = NULL; - FILE* fp = NULL; - char* fname = NULL; - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - assert((CHANX == chan_type)||(CHANY == chan_type)); - - /* Initial chan_prefix*/ - switch (chan_type) { - case CHANX: - /* Create file handler */ - fp = spice_create_one_subckt_file(subckt_dir, "Channel X-direction ", chanx_spice_file_name_prefix, x, y, &fname); - chan_prefix = "chanx"; - fprintf(fp, "***** Subckt for Channel X [%d][%d] *****\n", x, y); - break; - case CHANY: - /* Create file handler */ - fp = spice_create_one_subckt_file(subckt_dir, "Channel Y-direction ", chany_spice_file_name_prefix, x, y, &fname); - chan_prefix = "chany"; - fprintf(fp, "***** Subckt for Channel Y [%d][%d] *****\n", x, y); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid Channel type! Should be CHANX or CHANY.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Collect rr_nodes for Tracks for chanx[ix][iy] */ - chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, x, y, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - - /* Chan subckt definition */ - fprintf(fp, ".subckt %s[%d][%d] \n", chan_prefix, x, y); - /* Inputs and outputs, - * Rules for CHANX: - * print left-hand ports(in) first, then right-hand ports(out) - * Rules for CHANX: - * print bottom ports(in) first, then top ports(out) - */ - fprintf(fp, "+ "); - /* LEFT/BOTTOM side port of CHANX/CHANY */ - for (itrack = 0; itrack < chan_width; itrack++) { - switch (chan_rr_nodes[itrack]->direction) { - case INC_DIRECTION: - fprintf(fp, "in%d ", itrack); /* INC_DIRECTION: input on the left/bottom side */ - break; - case DEC_DIRECTION: - fprintf(fp, "out%d ", itrack); /* DEC_DIRECTION: output on the left/bottom side*/ - break; - case BI_DIRECTION: - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%d]!\n", - __FILE__, __LINE__, chan_prefix, x, y, itrack); - exit(1); - } - } - fprintf(fp, "\n"); - fprintf(fp, "+ "); - /* RIGHT/TOP side port of CHANX/CHANY */ - for (itrack = 0; itrack < chan_width; itrack++) { - switch (chan_rr_nodes[itrack]->direction) { - case INC_DIRECTION: - fprintf(fp, "out%d ", itrack); /* INC_DIRECTION: output on the right/top side*/ - break; - case DEC_DIRECTION: - fprintf(fp, "in%d ", itrack); /* DEC_DIRECTION: input on the right/top side */ - break; - case BI_DIRECTION: - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of rr_node %s[%d][%d]_track[%d]!\n", - __FILE__, __LINE__, chan_prefix, x, y, itrack); - exit(1); - } - } - fprintf(fp, "\n"); - fprintf(fp, "+ "); - /* Middle point output for connection box inputs */ - for (itrack = 0; itrack < chan_width; itrack++) { - fprintf(fp, "mid_out%d ", itrack); - } - fprintf(fp, "\n"); - /* End with svdd and sgnd */ - fprintf(fp, "+ svdd sgnd\n"); - - /* Print segments models*/ - for (itrack = 0; itrack < chan_width; itrack++) { - cost_index = chan_rr_nodes[itrack]->cost_index; - iseg = rr_indexed_data[cost_index].seg_index; - /* Check */ - assert((!(iseg < 0))&&(iseg < num_segment)); - assert(NULL != segments[iseg].spice_model); - assert(SPICE_MODEL_CHAN_WIRE == segments[iseg].spice_model->type); - fprintf(fp, "X%s[%d] ", segments[iseg].spice_model->prefix, segments[iseg].spice_model->cnt); /*Call subckt*/ - /* Update counter of SPICE model*/ - segments[iseg].spice_model->cnt++; - /* Inputs and ouputs*/ - fprintf(fp, "in%d out%d mid_out%d ", itrack, itrack, itrack); - /* End with svdd, sgnd and Subckt name*/ - fprintf(fp, "svdd sgnd %s_seg%d\n", segments[iseg].spice_model->name, iseg); - } - - fprintf(fp, ".eom\n"); - - /* Close the file*/ - fclose(fp); - - /* Add fname to the linked list */ - routing_spice_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_spice_subckt_file_path_head, fname); - - /* Free */ - my_free(chan_rr_nodes); - my_free(fname); - - return; -} - -void fprint_grid_side_pin_with_given_index(FILE* fp, - int pin_index, int side, - int x, int y) { - int height/*, class_id*/; - t_type_ptr type = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - type = grid[x][y].type; - assert(NULL != type); - - assert((!(0 > pin_index))&&(pin_index < type->num_pins)); - assert((!(0 > side))&&(!(side > 3))); - - /* Output the pins on the side*/ - height = get_grid_pin_height(x, y, pin_index); - /* class_id = type->pin_class[pin_index]; */ - if ((1 == type->pinloc[height][side][pin_index])) { - /* Not sure if we need to plus a height */ - /* fprintf(fp, "grid[%d][%d]_pin[%d][%d][%d] ", x, y, height, side, pin_index); */ - fprintf(fp, "grid[%d][%d]_pin[%d][%d][%d] ", x, y, height, side, pin_index); - } else { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Fail to print a grid pin (x=%d, y=%d, height=%d, side=%d, index=%d)\n", - __FILE__, __LINE__, x, y, height, side, pin_index); - exit(1); - } - - return; -} - -void fprint_grid_side_pins(FILE* fp, - t_rr_type pin_type, - int x, - int y, - int side) { - int height, ipin, class_id; - t_type_ptr type = NULL; - enum e_pin_type pin_class_type; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - type = grid[x][y].type; - assert(NULL != type); - - /* Assign the type of PIN*/ - switch (pin_type) { - case IPIN: - /* case SINK: */ - pin_class_type = RECEIVER; /* This is the end of a route path*/ - break; - /* case SOURCE: */ - case OPIN: - pin_class_type = DRIVER; /* This is the start of a route path */ - break; - /* SINK and SOURCE are hypothesis nodes */ - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid pin_type!\n", __FILE__, __LINE__); - exit(1); - } - - /* Output the pins on the side*/ - for (ipin = 0; ipin < type->num_pins; ipin++) { - height = get_grid_pin_height(x, y, ipin); - class_id = type->pin_class[ipin]; - if ((1 == type->pinloc[height][side][ipin])&&(pin_class_type == type->class_inf[class_id].type)) { - /* Not sure if we need to plus a height */ - fprintf(fp, "grid[%d][%d]_pin[%d][%d][%d] ", x, y + height, height, side, ipin); - } - } - - return; -} - -void fprint_switch_box_chan_port(FILE* fp, - t_sb cur_sb_info, - int chan_side, - t_rr_node* cur_rr_node, - enum PORTS cur_rr_node_direction) { - int index = -1; - t_rr_type chan_rr_node_type; - int chan_rr_node_x, chan_rr_node_y; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Get the index in sb_info of cur_rr_node */ - index = get_rr_node_index_in_sb_info(cur_rr_node, cur_sb_info, chan_side, cur_rr_node_direction); - /* Make sure this node is included in this sb_info */ - assert((-1 != index)&&(-1 != chan_side)); - - get_chan_rr_node_coordinate_in_sb_info(cur_sb_info, chan_side, - &chan_rr_node_type, &chan_rr_node_x, &chan_rr_node_y); - - assert(cur_rr_node->type == chan_rr_node_type); - - fprintf(fp, "%s[%d][%d]_%s[%d] ", - convert_chan_type_to_string(chan_rr_node_type), - chan_rr_node_x, chan_rr_node_y, - convert_chan_rr_node_direction_to_string(cur_sb_info.chan_rr_node_direction[chan_side][index]), - cur_rr_node->ptc_num); - - return; -} - -/* Print a short interconneciton in switch box - * There are two cases should be noticed. - * 1. The actual fan-in of cur_rr_node is 0. In this case, - the cur_rr_node need to be short connected to itself which is on the opposite side of this switch - * 2. The actual fan-in of cur_rr_node is 0. In this case, - * The cur_rr_node need to connected to the drive_rr_node - */ -void fprint_switch_box_short_interc(FILE* fp, - t_sb cur_sb_info, - int chan_side, - t_rr_node* cur_rr_node, - int actual_fan_in, - t_rr_node* drive_rr_node) { - int side, index; - int grid_x, grid_y/*, height*/; - char* chan_name = NULL; - char* des_chan_port_name = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); - assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); - assert((0 == actual_fan_in)||(1 == actual_fan_in)); - - chan_name = convert_chan_type_to_string(cur_rr_node->type); - - /* Get the index in sb_info of cur_rr_node */ - index = get_rr_node_index_in_sb_info(cur_rr_node, cur_sb_info, chan_side, OUT_PORT); - des_chan_port_name = "out"; - - fprintf(fp, "R%s[%d][%d]_%s[%d] ", - chan_name, cur_sb_info.x, cur_sb_info.y, des_chan_port_name, cur_rr_node->ptc_num); - - /* Check the driver*/ - if (0 == actual_fan_in) { - assert(drive_rr_node == cur_rr_node); - } else { - /* drive_rr_node = &(rr_node[cur_rr_node->prev_node]); */ - assert(1 == rr_node_drive_switch_box(drive_rr_node, cur_rr_node, cur_sb_info.x, cur_sb_info.y, chan_side)); - } - switch (drive_rr_node->type) { - /* case SOURCE: */ - case OPIN: - /* Indicate a CLB Outpin*/ - /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ - get_rr_node_side_and_index_in_sb_info(drive_rr_node, cur_sb_info, IN_PORT, &side, &index); - /* We need to be sure that drive_rr_node is part of the SB */ - assert((-1 != index)&&(-1 != side)); - /* Find grid_x and grid_y */ - grid_x = drive_rr_node->xlow; - grid_y = drive_rr_node->ylow; /*Plus the offset in function fprint_grid_side_pin_with_given_index */ - /*height = grid[grid_x][grid_y].offset;*/ - /* Print a grid pin */ - fprint_grid_side_pin_with_given_index(fp, drive_rr_node->ptc_num, - cur_sb_info.opin_rr_node_grid_side[side][index], - grid_x, grid_y); - break; - case CHANX: - case CHANY: - /* Should be an input */ - if (cur_rr_node == drive_rr_node) { - /* To be strict, the input should locate on the opposite side. - * Use the else part if this may change in some architecture. - */ - side = get_opposite_side(chan_side); - index = get_rr_node_index_in_sb_info(drive_rr_node, cur_sb_info, side, IN_PORT); - } else { - get_rr_node_side_and_index_in_sb_info(drive_rr_node, cur_sb_info, IN_PORT, &side, &index); - } - /* We need to be sure that drive_rr_node is part of the SB */ - assert((-1 != index)&&(-1 != side)); - fprint_switch_box_chan_port(fp, cur_sb_info, side, drive_rr_node, IN_PORT); - break; - default: /* IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - - /* Output port */ - /* fprint_switch_box_chan_port(fp, switch_box_x, switch_box_y, chan_side, cur_rr_node); */ - fprint_switch_box_chan_port(fp, cur_sb_info, chan_side, cur_rr_node, OUT_PORT); - - /* END */ - fprintf(fp, "0\n"); - - return; -} - -/* Print the SPICE netlist of multiplexer that drive this rr_node */ -void fprint_switch_box_mux(FILE* fp, - t_sb cur_sb_info, - int chan_side, - t_rr_node* cur_rr_node, - int mux_size, - t_rr_node** drive_rr_nodes, - int switch_index) { - int inode, side, index; - int grid_x, grid_y/*, height*/; - t_spice_model* spice_model = NULL; - int mux_level, path_id, cur_num_sram, ilevel; - int num_mux_sram_bits = 0; - int* mux_sram_bits = NULL; - char* sram_vdd_port_name = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); - assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); - - /* Check current rr_node is CHANX or CHANY*/ - assert((CHANX == cur_rr_node->type)||(CHANY == cur_rr_node->type)); - - /* Allocate drive_rr_nodes according to the fan-in*/ - assert((2 == mux_size)||(2 < mux_size)); - - /* Get spice model*/ - spice_model = switch_inf[switch_index].spice_model; - /* Now it is the time print the SPICE netlist of MUX*/ - fprintf(fp, "X%s_size%d[%d] ", spice_model->prefix, mux_size, spice_model->cnt); - /* Global ports */ - if (0 < rec_fprint_spice_model_global_ports(fp, spice_model, FALSE)) { - fprintf(fp, "+ "); - } - /* Input ports*/ - for (inode = 0; inode < mux_size; inode++) { - switch (drive_rr_nodes[inode]->type) { - /* case SOURCE: */ - case OPIN: - /* Indicate a CLB Outpin*/ - /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ - get_rr_node_side_and_index_in_sb_info(drive_rr_nodes[inode], cur_sb_info, IN_PORT, &side, &index); - /* We need to be sure that drive_rr_node is part of the SB */ - assert((-1 != index)&&(-1 != side)); - /* Find grid_x and grid_y */ - grid_x = drive_rr_nodes[inode]->xlow; - grid_y = drive_rr_nodes[inode]->ylow; /*Plus the offset in function fprint_grid_side_pin_with_given_index */ - /* height = grid[grid_x][grid_y].offset; */ - /* Print a grid pin */ - fprint_grid_side_pin_with_given_index(fp, drive_rr_nodes[inode]->ptc_num, - cur_sb_info.opin_rr_node_grid_side[side][index], - grid_x, grid_y); - break; - case CHANX: - case CHANY: - /* Should be an input! */ - get_rr_node_side_and_index_in_sb_info(drive_rr_nodes[inode], cur_sb_info, IN_PORT, &side, &index); - /* We need to be sure that drive_rr_node is part of the SB */ - if (!((-1 != index)&&(-1 != side))) { - assert((-1 != index)&&(-1 != side)); - } - fprint_switch_box_chan_port(fp, cur_sb_info, side, drive_rr_nodes[inode], IN_PORT); - break; - default: /* IPIN, SINK are invalid*/ - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n", - __FILE__, __LINE__); - exit(1); - } - } - - /* Output port */ - fprint_switch_box_chan_port(fp, cur_sb_info, chan_side, cur_rr_node, OUT_PORT); - - /* Configuration bits for this MUX*/ - path_id = DEFAULT_PATH_ID; - for (inode = 0; inode < mux_size; inode++) { - if (drive_rr_nodes[inode] == &(rr_node[cur_rr_node->prev_node])) { - path_id = inode; - break; - } - } - /* Depend on both technology and structure of this MUX*/ - switch (spice_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - decode_cmos_mux_sram_bits(spice_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - case SPICE_MODEL_DESIGN_RRAM: - decode_rram_mux(spice_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for spice model (%s)!\n", - __FILE__, __LINE__, spice_model->name); - exit(1); - } - - /* Print SRAMs that configure this MUX */ - /* Get current counter of mem_bits, bl and wl */ - cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info); - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - assert( (0 == mux_sram_bits[ilevel]) || (1 == mux_sram_bits[ilevel]) ); - fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, - cur_num_sram + ilevel, mux_sram_bits[ilevel]); - fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, - cur_num_sram + ilevel, 1 - mux_sram_bits[ilevel]); - } - - /* End with svdd and sgnd, subckt name*/ - fprintf(fp, "svdd sgnd %s_size%d\n", spice_model->name, mux_size); - - /* Print the encoding in SPICE netlist for debugging */ - fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n", - spice_model->cnt, mux_level, path_id); - fprintf(fp, "*****"); - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - fprintf(fp, "%d", mux_sram_bits[ilevel]); - } - fprintf(fp, "*****\n"); - - /* Call SRAM subckts*/ - /* Give the VDD port name for SRAMs */ - sram_vdd_port_name = (char*)my_malloc(sizeof(char)* - (strlen(spice_tb_global_vdd_sb_sram_port_name) - + 1 )); - sprintf(sram_vdd_port_name, "%s", - spice_tb_global_vdd_sb_sram_port_name); - /* Now Print SRAMs one by one */ - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, - spice_model, sram_vdd_port_name); - } - - /* Store the configuraion bit to linked-list */ - add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_num_sram, - num_mux_sram_bits, mux_sram_bits); - - /* Update spice_model counter */ - spice_model->cnt++; - - /* Free */ - my_free(mux_sram_bits); - my_free(sram_vdd_port_name); - - return; -} - -void fprint_switch_box_interc(FILE* fp, - t_sb cur_sb_info, - int chan_side, - t_rr_node* cur_rr_node) { - int sb_x, sb_y; - int num_drive_rr_nodes = 0; - t_rr_node** drive_rr_nodes = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - sb_x = cur_sb_info.x; - sb_y = cur_sb_info.y; - - /* Check */ - assert((!(0 > sb_x))&&(!(sb_x > (nx + 1)))); - assert((!(0 > sb_y))&&(!(sb_y > (ny + 1)))); - - /* Check each num_drive_rr_nodes, see if they appear in the cur_sb_info */ - if (TRUE == check_drive_rr_node_imply_short(cur_sb_info, cur_rr_node, chan_side)) { - /* Double check if the interc lies inside a channel wire, that is interc between segments */ - assert(1 == is_rr_node_exist_opposite_side_in_sb_info(cur_sb_info, cur_rr_node, chan_side)); - num_drive_rr_nodes = 0; - drive_rr_nodes = NULL; - } else { - num_drive_rr_nodes = cur_rr_node->num_drive_rr_nodes; - drive_rr_nodes = cur_rr_node->drive_rr_nodes; - } - - if (0 == num_drive_rr_nodes) { - /* Print a special direct connection*/ - fprint_switch_box_short_interc(fp, cur_sb_info, chan_side, cur_rr_node, - num_drive_rr_nodes, cur_rr_node); - } else if (1 == num_drive_rr_nodes) { - /* Print a direct connection*/ - fprint_switch_box_short_interc(fp, cur_sb_info, chan_side, cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]); - } else if (1 < num_drive_rr_nodes) { - /* Print the multiplexer, fan_in >= 2 */ - fprint_switch_box_mux(fp, cur_sb_info, chan_side, cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]); - } /*Nothing should be done else*/ - - /* Free */ - - return; -} - -/* Task: Print the subckt of a Switch Box. - * A Switch Box subckt consists of following ports: - * 1. Channel Y [x][y] inputs - * 2. Channel X [x+1][y] inputs - * 3. Channel Y [x][y-1] outputs - * 4. Channel X [x][y] outputs - * 5. Grid[x][y+1] Right side outputs pins - * 6. Grid[x+1][y+1] Left side output pins - * 7. Grid[x+1][y+1] Bottom side output pins - * 8. Grid[x+1][y] Top side output pins - * 9. Grid[x+1][y] Left side output pins - * 10. Grid[x][y] Right side output pins - * 11. Grid[x][y] Top side output pins - * 12. Grid[x][y+1] Bottom side output pins - * - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - * For channels chanY with INC_DIRECTION on the top side, they should be marked as outputs - * For channels chanY with DEC_DIRECTION on the top side, they should be marked as inputs - * For channels chanY with INC_DIRECTION on the bottom side, they should be marked as inputs - * For channels chanY with DEC_DIRECTION on the bottom side, they should be marked as outputs - * For channels chanX with INC_DIRECTION on the left side, they should be marked as inputs - * For channels chanX with DEC_DIRECTION on the left side, they should be marked as outputs - * For channels chanX with INC_DIRECTION on the right side, they should be marked as outputs - * For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs - */ -static -void fprint_routing_switch_box_subckt(char* subckt_dir, - t_sb cur_sb_info) { - int itrack, inode, side, ix, iy, x, y; - FILE* fp = NULL; - char* fname = NULL; - - /* Check */ - assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); - assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); - - /* Create file handler */ - fp = spice_create_one_subckt_file(subckt_dir, "Switch Block ", sb_spice_file_name_prefix, cur_sb_info.x, cur_sb_info.y, &fname); - - x = cur_sb_info.x; - y = cur_sb_info.y; - - /* Print the definition of subckt*/ - fprintf(fp, "***** Switch Box[%d][%d] Sub-Circuit *****\n", cur_sb_info.x, cur_sb_info.y); - fprintf(fp, ".subckt sb[%d][%d] ", cur_sb_info.x, cur_sb_info.y); - fprintf(fp, "\n"); - for (side = 0; side < cur_sb_info.num_sides; side++) { - fprintf(fp, "***** Inputs/outputs of %s side *****\n",convert_side_index_to_string(side)); - determine_sb_port_coordinator(cur_sb_info, side, &ix, &iy); - fprintf(fp, "+ "); - - for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { - switch (cur_sb_info.chan_rr_node_direction[side][itrack]) { - case OUT_PORT: - fprintf(fp, "%s[%d][%d]_out[%d] ", - convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), - ix, iy, itrack); - break; - case IN_PORT: - fprintf(fp, "%s[%d][%d]_in[%d] ", - convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), - ix, iy, itrack); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of port sb[%d][%d] Channel node[%d] track[%d]!\n", - __FILE__, __LINE__, cur_sb_info.x, cur_sb_info.y, side, itrack); - exit(1); - } - } - fprintf(fp, "\n"); - fprintf(fp, "+ "); - /* Dump OPINs of adjacent CLBs */ - for (inode = 0; inode < cur_sb_info.num_opin_rr_nodes[side]; inode++) { - fprint_grid_side_pin_with_given_index(fp, cur_sb_info.opin_rr_node[side][inode]->ptc_num, - cur_sb_info.opin_rr_node_grid_side[side][inode], - cur_sb_info.opin_rr_node[side][inode]->xlow, - cur_sb_info.opin_rr_node[side][inode]->ylow); - } - fprintf(fp, "\n"); - fprintf(fp, "+ "); - } - - /* Local Vdd and Gnd */ - fprintf(fp, "svdd sgnd\n"); - - /* Specify the head of scan-chain */ - if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { - fprintf(fp, "***** Head of scan-chain *****\n"); - fprintf(fp, "Rsb[%d][%d]_sc_head sb[%d][%d]_sc_head %s[%d]->in 0\n", - x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); - } - - /* Put down all the multiplexers */ - for (side = 0; side < cur_sb_info.num_sides; side++) { - fprintf(fp, "***** %s side Multiplexers *****\n", - convert_side_index_to_string(side)); - for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { - assert((CHANX == cur_sb_info.chan_rr_node[side][itrack]->type) - ||(CHANY == cur_sb_info.chan_rr_node[side][itrack]->type)); - /* We care INC_DIRECTION tracks at this side*/ - if (OUT_PORT != cur_sb_info.chan_rr_node_direction[side][itrack]) { - continue; - } - fprint_switch_box_interc(fp, cur_sb_info, side, cur_sb_info.chan_rr_node[side][itrack]); - } - } - - /* Specify the tail of scan-chain */ - if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { - fprintf(fp, "***** Tail of scan-chain *****\n"); - fprintf(fp, "Rsb[%d][%d]_sc_tail sb[%d][%d]_sc_tail %s[%d]->in 0\n", - x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); - } - - fprintf(fp, ".eom\n"); - - /* Close the file*/ - fclose(fp); - - /* Add fname to the linked list */ - routing_spice_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_spice_subckt_file_path_head, fname); - - /* Free */ - my_free(fname); - - return; -} - -/* SRC rr_node is the IPIN of a grid.*/ -void fprint_connection_box_short_interc(FILE* fp, - t_cb cur_cb_info, - t_rr_node* src_rr_node) { - t_rr_node* drive_rr_node = NULL; - int iedge, check_flag; - int xlow, ylow, height, side, index; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); - assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); - assert(1 == src_rr_node->fan_in); - - /* Check the driver*/ - drive_rr_node = src_rr_node->drive_rr_nodes[0]; - /* We have OPINs since we may have direct connections: - * These connections should be handled by other functions in the compact_netlist.c - * So we just return here for OPINs - */ - if (OPIN == drive_rr_node->type) { - return; - } - - assert((CHANX == drive_rr_node->type)||(CHANY == drive_rr_node->type)); - check_flag = 0; - for (iedge = 0; iedge < drive_rr_node->num_edges; iedge++) { - if (src_rr_node == &(rr_node[drive_rr_node->edges[iedge]])) { - check_flag++; - } - } - assert(1 == check_flag); - - xlow = src_rr_node->xlow; - ylow = src_rr_node->ylow; - height = grid[xlow][ylow].offset; - - /* Call the zero-resistance model */ - switch(cur_cb_info.type) { - case CHANX: - fprintf(fp, "Rcbx[%d][%d]_grid[%d][%d]_pin[%d] ", - cur_cb_info.x, cur_cb_info.y, - xlow, ylow + height, src_rr_node->ptc_num); - break; - case CHANY: - fprintf(fp, "Rcby[%d][%d]_grid[%d][%d]_pin[%d] ", - cur_cb_info.x, cur_cb_info.y, - xlow, ylow + height, src_rr_node->ptc_num); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - /* Input port*/ - assert(IPIN == src_rr_node->type); - /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ - get_rr_node_side_and_index_in_cb_info(src_rr_node, cur_cb_info, OUT_PORT, &side, &index); - /* We need to be sure that drive_rr_node is part of the SB */ - assert((-1 != index)&&(-1 != side)); - fprint_grid_side_pin_with_given_index(fp, cur_cb_info.ipin_rr_node[side][index]->ptc_num, - cur_cb_info.ipin_rr_node_grid_side[side][index], - xlow, ylow); - - /* output port -- > connect to the output at middle point of a channel */ - fprintf(fp, "%s[%d][%d]_midout[%d] ", - convert_chan_type_to_string(drive_rr_node->type), - cur_cb_info.x, cur_cb_info.y, drive_rr_node->ptc_num); - - /* End */ - fprintf(fp, "0\n"); - - - return; -} - -void fprint_connection_box_mux(FILE* fp, - t_cb cur_cb_info, - t_rr_node* src_rr_node) { - int mux_size, cur_num_sram, ilevel; - t_rr_node** drive_rr_nodes = NULL; - int inode, mux_level, path_id, switch_index; - t_spice_model* mux_spice_model = NULL; - int num_mux_sram_bits = 0; - int* mux_sram_bits = NULL; - t_rr_type drive_rr_node_type = NUM_RR_TYPES; - int xlow, ylow, /* offset,*/ side, index; - char* sram_vdd_port_name = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); - assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); - - /* Find drive_rr_nodes*/ - mux_size = src_rr_node->num_drive_rr_nodes; - drive_rr_nodes = src_rr_node->drive_rr_nodes; - - /* Configuration bits for MUX*/ - path_id = DEFAULT_PATH_ID; - for (inode = 0; inode < mux_size; inode++) { - if (drive_rr_nodes[inode] == &(rr_node[src_rr_node->prev_node])) { - path_id = inode; - break; - } - } - - switch_index = src_rr_node->drive_switches[DEFAULT_SWITCH_ID]; - - mux_spice_model = switch_inf[switch_index].spice_model; - - /* Call the MUX SPICE model */ - fprintf(fp, "X%s_size%d[%d] ", mux_spice_model->prefix, mux_size, mux_spice_model->cnt); - - /* Global ports */ - if (0 < rec_fprint_spice_model_global_ports(fp, mux_spice_model, FALSE)) { - fprintf(fp, "+ "); - } - - /* Check drive_rr_nodes type, should be the same*/ - for (inode = 0; inode < mux_size; inode++) { - if (NUM_RR_TYPES == drive_rr_node_type) { - drive_rr_node_type = drive_rr_nodes[inode]->type; - } else { - assert(drive_rr_node_type == drive_rr_nodes[inode]->type); - assert((CHANX == drive_rr_nodes[inode]->type)||(CHANY == drive_rr_nodes[inode]->type)); - } - } - - /* input port*/ - for (inode = 0; inode < mux_size; inode++) { - fprintf(fp, "%s[%d][%d]_midout[%d] ", - convert_chan_type_to_string(drive_rr_nodes[inode]->type), - cur_cb_info.x, cur_cb_info.y, drive_rr_nodes[inode]->ptc_num); - } - /* output port*/ - xlow = src_rr_node->xlow; - ylow = src_rr_node->ylow; - /* offset = grid[xlow][ylow].offset; */ - - assert(IPIN == src_rr_node->type); - /* Search all the sides of a CB, see this drive_rr_node is an INPUT of this SB */ - get_rr_node_side_and_index_in_cb_info(src_rr_node, cur_cb_info, OUT_PORT, &side, &index); - /* We need to be sure that drive_rr_node is part of the CB */ - assert((-1 != index)&&(-1 != side)); - fprint_grid_side_pin_with_given_index(fp, cur_cb_info.ipin_rr_node[side][index]->ptc_num, - cur_cb_info.ipin_rr_node_grid_side[side][index], - xlow, ylow); - - switch (mux_spice_model->design_tech) { - case SPICE_MODEL_DESIGN_CMOS: - decode_cmos_mux_sram_bits(mux_spice_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - case SPICE_MODEL_DESIGN_RRAM: - decode_rram_mux(mux_spice_model, mux_size, path_id, &num_mux_sram_bits, &mux_sram_bits, &mux_level); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid design technology for spice model (%s)!\n", - __FILE__, __LINE__, mux_spice_model->name); - } - - /* Print SRAMs that configure this MUX */ - /* Get current counter of mem_bits, bl and wl */ - cur_num_sram = get_sram_orgz_info_num_mem_bit(sram_spice_orgz_info); - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - assert( (0 == mux_sram_bits[ilevel]) || (1 == mux_sram_bits[ilevel]) ); - fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, - cur_num_sram + ilevel, mux_sram_bits[ilevel]); - fprint_spice_sram_one_outport(fp, sram_spice_orgz_info, - cur_num_sram + ilevel, 1 - mux_sram_bits[ilevel]); - } - - /* End with svdd and sgnd, subckt name*/ - fprintf(fp, "svdd sgnd %s_size%d\n", mux_spice_model->name, mux_size); - - /* Print the encoding in SPICE netlist for debugging */ - fprintf(fp, "***** SRAM bits for MUX[%d], level=%d, select_path_id=%d. *****\n", - mux_spice_model->cnt, mux_level, path_id); - fprintf(fp, "*****"); - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - fprintf(fp, "%d", mux_sram_bits[ilevel]); - } - fprintf(fp, "*****\n"); - - /* Call SRAM subckts*/ - /* Give the VDD port name for SRAMs */ - sram_vdd_port_name = (char*)my_malloc(sizeof(char)* - (strlen(spice_tb_global_vdd_cb_sram_port_name) - + 1 )); - sprintf(sram_vdd_port_name, "%s", - spice_tb_global_vdd_cb_sram_port_name); - /* Now Print SRAMs one by one */ - for (ilevel = 0; ilevel < num_mux_sram_bits; ilevel++) { - fprint_spice_one_sram_subckt(fp, sram_spice_orgz_info, - mux_spice_model, sram_vdd_port_name); - } - - /* Store the configuraion bit to linked-list */ - add_sram_conf_bits_to_llist(sram_spice_orgz_info, cur_num_sram, - num_mux_sram_bits, mux_sram_bits); - - /* Update spice_model counter */ - mux_spice_model->cnt++; - - /* Free */ - my_free(mux_sram_bits); - my_free(sram_vdd_port_name); - - return; -} - -void fprint_connection_box_interc(FILE* fp, - t_cb cur_cb_info, - t_rr_node* src_rr_node) { - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); - assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); - - if (1 == src_rr_node->fan_in) { - /* Print a direct connection*/ - fprint_connection_box_short_interc(fp, cur_cb_info, src_rr_node); - } else if (1 < src_rr_node->fan_in) { - /* Print the multiplexer, fan_in >= 2 */ - fprint_connection_box_mux(fp, cur_cb_info, src_rr_node); - } /*Nothing should be done else*/ - - return; -} - -/* Print connection boxes - * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY]) - * Actually it is very similiar to switch box but - * the difference is connection boxes connect Grid INPUT Pins to channels - * TODO: merge direct connections into CB - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y] | [x+1][y+1] | - * | | Connection | | - * -------------- Box_Y[x][y] -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * Connection | [x][y] | Connection - * Box_X[x][y] ---------- Box_X[x+1][y] - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y-1] | [x+1][y] | - * | | Connection | | - * --------------Box_Y[x][y-1]-------------- - */ -static -void fprint_routing_connection_box_subckt(char* subckt_dir, - t_cb cur_cb_info) { - - int itrack, inode, side, x, y; - int side_cnt = 0; - FILE* fp = NULL; - char* fname = NULL; - - /* Identify the type of connection box - * Create file handler - */ - switch(cur_cb_info.type) { - case CHANX: - fp = spice_create_one_subckt_file(subckt_dir, "Connection Block X-channel ", cbx_spice_file_name_prefix, cur_cb_info.x, cur_cb_info.y, &fname); - break; - case CHANY: - fp = spice_create_one_subckt_file(subckt_dir, "Connection Block Y-channel ", cby_spice_file_name_prefix, cur_cb_info.x, cur_cb_info.y, &fname); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of connection box!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); - assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); - - x = cur_cb_info.x; - y = cur_cb_info.y; - - /* Print the definition of subckt*/ - fprintf(fp, ".subckt "); - /* Identify the type of connection box */ - switch(cur_cb_info.type) { - case CHANX: - fprintf(fp, "cbx[%d][%d] ", cur_cb_info.x, cur_cb_info.y); - break; - case CHANY: - fprintf(fp, "cby[%d][%d] ", cur_cb_info.x, cur_cb_info.y); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of connection box!\n", - __FILE__, __LINE__); - exit(1); - } - fprintf(fp, "\n"); - - /* Print the ports of channels*/ - /*connect to the mid point of a track*/ - /* Get the chan_rr_nodes: Only one side of a cb_info has chan_rr_nodes*/ - side_cnt = 0; - for (side = 0; side < cur_cb_info.num_sides; side++) { - /* Bypass side with zero channel width */ - if (0 == cur_cb_info.chan_width[side]) { - continue; - } - assert (0 < cur_cb_info.chan_width[side]); - side_cnt++; - for (itrack = 0; itrack < cur_cb_info.chan_width[side]; itrack++) { - fprintf(fp, "+ "); - fprintf(fp, "%s[%d][%d]_midout[%d] ", - convert_chan_type_to_string(cur_cb_info.type), - cur_cb_info.x, cur_cb_info.y, itrack); - fprintf(fp, "\n"); - } - } - /*check side_cnt */ - assert(1 == side_cnt); - - side_cnt = 0; - /* Print the ports of grids*/ - /* only check ipin_rr_nodes of cur_cb_info */ - for (side = 0; side < cur_cb_info.num_sides; side++) { - /* Bypass side with zero IPINs*/ - if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { - continue; - } - side_cnt++; - assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); - assert(NULL != cur_cb_info.ipin_rr_node[side]); - for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { - fprintf(fp, "+ "); - /* Print each INPUT Pins of a grid */ - fprint_grid_side_pin_with_given_index(fp, cur_cb_info.ipin_rr_node[side][inode]->ptc_num, - cur_cb_info.ipin_rr_node_grid_side[side][inode], - cur_cb_info.ipin_rr_node[side][inode]->xlow, - cur_cb_info.ipin_rr_node[side][inode]->ylow); - fprintf(fp, "\n"); - } - } - /* Make sure only 2 sides of IPINs are printed */ - assert((1 == side_cnt)||(2 == side_cnt)); - - /* subckt definition ends with svdd and sgnd*/ - fprintf(fp, "+ "); - fprintf(fp, "svdd sgnd\n"); - - /* Specify the head of scan-chain */ - if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { - switch(cur_cb_info.type) { - case CHANX: - fprintf(fp, "***** Head of scan-chain *****\n"); - fprintf(fp, "Rcbx[%d][%d]_sc_head cbx[%d][%d]_sc_head %s[%d]->in 0\n", - x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); - break; - case CHANY: - fprintf(fp, "***** Head of scan-chain *****\n"); - fprintf(fp, "Rcby[%d][%d]_sc_head cby[%d][%d]_sc_head %s[%d]->in 0\n", - x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - } - - /* Print multiplexers or direct interconnect, - * According to the rr_node lists in cbx_info or cby_info - */ - side_cnt = 0; - for (side = 0; side < cur_cb_info.num_sides; side++) { - /* Bypass side with zero IPINs*/ - if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { - continue; - } - side_cnt++; - assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); - assert(NULL != cur_cb_info.ipin_rr_node[side]); - for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { - fprint_connection_box_interc(fp, cur_cb_info, cur_cb_info.ipin_rr_node[side][inode]); - } - } - /* Make sure only 2 sides of IPINs are printed */ - assert((1 == side_cnt)||(2 == side_cnt)); - - /* Specify the tail of scan-chain */ - if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { - switch(cur_cb_info.type) { - case CHANX: - fprintf(fp, "***** Tail of scan-chain *****\n"); - fprintf(fp, "Rcbx[%d][%d]_sc_tail cbx[%d][%d]_sc_tail %s[%d]->in 0\n", - x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); - break; - case CHANY: - fprintf(fp, "***** Tail of scan-chain *****\n"); - fprintf(fp, "Rcby[%d][%d]_sc_tail cby[%d][%d]_sc_tail %s[%d]->in 0\n", - x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - } - - fprintf(fp, ".eom\n"); - - /* Close the file*/ - fclose(fp); - - /* Add fname to the linked list */ - routing_spice_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_spice_subckt_file_path_head, fname); - - /* Free */ - my_free(fname); - - return; -} - - -/* Top Function*/ -/* Build the routing resource SPICE sub-circuits*/ -void generate_spice_routing_resources(char* subckt_dir, - t_arch arch, - t_det_routing_arch* routing_arch, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { - int ix, iy; - - assert(UNI_DIRECTIONAL == routing_arch->directionality); - - /* Two major tasks: - * 1. Generate sub-circuits for Routing Channels - * 2. Generate sub-circuits for Switch Boxes - */ - /* Now: First task: Routing channels - * Sub-circuits are named as chanx[ix][iy] or chany[ix][iy] for horizontal or vertical channels - * each channels consist of a number of routing tracks. (Actually they are metal wires) - * We only support single-driver routing architecture. - * The direction is defined as INC_DIRECTION ------> and DEC_DIRECTION <-------- for chanx - * The direction is defined as INC_DIRECTION /|\ and DEC_DIRECTION | for chany - * | | - * | | - * | \|/ - * For INC_DIRECTION chanx, the inputs are at the left of channels, the outputs are at the right of channels - * For DEC_DIRECTION chanx, the inputs are at the right of channels, the outputs are at the left of channels - * For INC_DIRECTION chany, the inputs are at the bottom of channels, the outputs are at the top of channels - * For DEC_DIRECTION chany, the inputs are at the top of channels, the outputs are at the bottom of channels - */ - /* X - channels [1...nx][0..ny]*/ - vpr_printf(TIO_MESSAGE_INFO, "Writing X-direction Channels...\n"); - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - fprint_routing_chan_subckt(subckt_dir, ix, iy, CHANX, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - arch.num_segments, arch.Segments); - } - } - /* Y - channels [1...ny][0..nx]*/ - vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n"); - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - fprint_routing_chan_subckt(subckt_dir, ix, iy, CHANY, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - arch.num_segments, arch.Segments); - } - } - - /* Switch Boxes*/ - vpr_printf(TIO_MESSAGE_INFO, "Writing Switch Boxes...\n"); - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 0; iy < (ny + 1); iy++) { - update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); - fprint_routing_switch_box_subckt(subckt_dir, sb_info[ix][iy]); - update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); - } - } - - /* Connection Boxes */ - vpr_printf(TIO_MESSAGE_INFO, "Writing Connection Boxes...\n"); - /* X - channels [1...nx][0..ny]*/ - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - update_spice_models_routing_index_low(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); - /* Check if this cby_info exists, it may be covered by a heterogenous block */ - if ((TRUE == is_cb_exist(CHANX, ix, iy)) - &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { - fprint_routing_connection_box_subckt(subckt_dir, cbx_info[ix][iy]); - } - update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); - } - } - /* Y - channels [1...ny][0..nx]*/ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - update_spice_models_routing_index_low(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); - /* Check if this cby_info exists, it may be covered by a heterogenous block */ - if ((TRUE == is_cb_exist(CHANY, ix, iy)) - &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { - fprint_routing_connection_box_subckt(subckt_dir, cby_info[ix][iy]); - } - update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); - } - } - - /* Output a header file for all the routing blocks */ - vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n"); - spice_print_subckt_header_file(routing_spice_subckt_file_path_head, - subckt_dir, - routing_spice_file_name); - return; -} - -/************************************************************************ - * End of file : spice_routing.c - ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.h deleted file mode 100644 index bc7df15d4..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.h +++ /dev/null @@ -1,71 +0,0 @@ - -void fprint_routing_chan_subckt(FILE* fp, - int x, int y, t_rr_type chan_type, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - int num_segment, t_segment_inf* segments); - -void fprint_grid_side_pin_with_given_index(FILE* fp, - int pin_index, int side, - int x, int y); - -void fprint_grid_side_pins(FILE* fp, - t_rr_type pin_type, - int x, - int y, - int side); - -void fprint_switch_box_chan_port(FILE* fp, - t_sb cur_sb_info, - int chan_side, - t_rr_node* cur_rr_node, - enum PORTS cur_rr_node_direction); - -void fprint_switch_box_short_interc(FILE* fp, - t_sb cur_sb_info, - int chan_side, - t_rr_node* cur_rr_node, - int actual_fan_in, - t_rr_node* drive_rr_node); - -void fprint_switch_box_mux(FILE* fp, - t_sb cur_sb_info, - int chan_side, - t_rr_node* cur_rr_node, - int mux_size, - t_rr_node** drive_rr_nodes, - int switch_index); - -void fprint_switch_box_interc(FILE* fp, - t_sb cur_sb_info, - int chan_side, - t_rr_node* cur_rr_node); - -void fprint_routing_switch_box_subckt(FILE* fp, t_sb cur_sb_info, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - boolean compact_routing_hierarchy); - -void fprint_connection_box_short_interc(FILE* fp, - t_cb cur_cb_info, - t_rr_node* src_rr_node); - -void fprint_connection_box_mux(FILE* fp, - t_cb cur_cb_info, - t_rr_node* src_rr_node); - -void fprint_connection_box_interc(FILE* fp, - t_cb cur_cb_info, - t_rr_node* src_rr_node); - -void fprint_routing_connection_box_subckt(FILE* fp, t_cb cur_cb_info, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - boolean compact_routing_hierarchy); - -void generate_spice_routing_resources(char* subckt_dir, - t_arch arch, - t_det_routing_arch* routing_arch, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices); - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing_testbench.c deleted file mode 100644 index 00a5bcd15..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing_testbench.c +++ /dev/null @@ -1,867 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "spice_utils.h" -#include "spice_routing.h" -#include "spice_subckt.h" - -/* Global parameters */ -static int num_segments; -static t_segment_inf* segments; -static int testbench_load_cnt = 0; -static int upbound_sim_num_clock_cycles = 2; -static int max_sim_num_clock_cycles = 2; -static int auto_select_max_sim_num_clock_cycles = TRUE; - -static void init_spice_routing_testbench_globals(t_spice spice) { - auto_select_max_sim_num_clock_cycles = spice.spice_params.meas_params.auto_select_sim_num_clk_cycle; - upbound_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; - if (FALSE == auto_select_max_sim_num_clock_cycles) { - max_sim_num_clock_cycles = spice.spice_params.meas_params.sim_num_clock_cycle + 1; - } else { - max_sim_num_clock_cycles = 2; - } -} - -static -void fprint_spice_cb_testbench_global_ports(FILE* fp, - t_spice spice) { - /* Declare the global SRAM ports */ - fprintf(fp, ".global %s\n", - spice_tb_global_vdd_cb_sram_port_name); - - return; -} - -static -void fprint_spice_sb_testbench_global_ports(FILE* fp, - t_spice spice) { - /* Declare the global SRAM ports */ - fprintf(fp, ".global %s\n", - spice_tb_global_vdd_sb_sram_port_name); - - return; -} - - -static -void fprint_spice_routing_testbench_global_ports(FILE* fp, - t_spice spice) { - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - - /* Print generic global ports*/ - fprint_spice_generic_testbench_global_ports(fp, - sram_spice_orgz_info, - global_ports_head); - - return; -} - -static -void fprintf_spice_routing_testbench_generic_stimuli(FILE* fp, - int num_clocks) { - - /* Give global vdd, gnd, voltage sources*/ - /* A valid file handler */ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Print generic stimuli */ - fprint_spice_testbench_generic_global_ports_stimuli(fp, num_clocks); - - /* Generate global ports stimuli */ - fprint_spice_testbench_global_ports_stimuli(fp, global_ports_head); - - /* SRAM ports */ - fprintf(fp, "***** Global Inputs for SRAMs *****\n"); - fprint_spice_testbench_global_sram_inport_stimuli(fp, sram_spice_orgz_info); - - fprintf(fp, "***** Global VDD for SRAMs *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_sram_port_name, - "vsp"); - - fprintf(fp, "***** Global VDD for load inverters *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_load_port_name, - "vsp"); - - - return; -} - -/** In a testbench, we call the subckt of defined connection box (cbx[x][y] or cby[x][y]) - * For each input of connection box (channel track rr_nodes), - * we find their activities and generate input voltage pulses. - * For each output of connection box, we add all the non-inverter downstream components as load. - */ -static -int fprint_spice_routing_testbench_call_one_cb_tb(FILE* fp, - t_spice spice, - t_rr_type chan_type, - int x, int y, - t_ivec*** LL_rr_node_indices) { - int itrack, inode, side, ipin_height; - int side_cnt = 0; - int used = 0; - t_cb cur_cb_info; - - float input_density; - float input_probability; - int input_init_value; - float average_cb_input_density = 0.; - int avg_density_cnt = 0; - - int num_sim_clock_cycles = 0; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - - /* call the defined switch block sb[x][y]*/ - fprintf(fp, "***** Call defined Connection Box[%d][%d] *****\n", x, y); - switch(chan_type) { - case CHANX: - cur_cb_info = cbx_info[x][y]; - break; - case CHANY: - cur_cb_info = cby_info[x][y]; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - fprint_call_defined_one_connection_box(fp, cur_cb_info); - - /* Print input voltage pulses */ - /* connect to the mid point of a track*/ - side_cnt = 0; - for (side = 0; side < cur_cb_info.num_sides; side++) { - /* Bypass side with zero channel width */ - if (0 == cur_cb_info.chan_width[side]) { - continue; - } - assert (0 < cur_cb_info.chan_width[side]); - side_cnt++; - for (itrack = 0; itrack < cur_cb_info.chan_width[side]; itrack++) { - /* Add input voltage pulses*/ - input_density = get_rr_node_net_density(*cur_cb_info.chan_rr_node[side][itrack]); - input_probability = get_rr_node_net_probability(*cur_cb_info.chan_rr_node[side][itrack]); - input_init_value = get_rr_node_net_init_value(*cur_cb_info.chan_rr_node[side][itrack]); - fprintf(fp, "***** Signal %s[%d][%d]_midout[%d] density = %g, probability=%g.*****\n", - convert_chan_type_to_string(cur_cb_info.type), - cur_cb_info.x, cur_cb_info.y, itrack, - input_density, input_probability); - fprintf(fp, "V%s[%d][%d]_midout[%d] %s[%d][%d]_midout[%d] 0 \n", - convert_chan_type_to_string(cur_cb_info.type), - cur_cb_info.x, cur_cb_info.y, itrack, - convert_chan_type_to_string(cur_cb_info.type), - cur_cb_info.x, cur_cb_info.y, itrack); - fprint_voltage_pulse_params(fp, input_init_value, input_density, input_probability); - /* Update statistics */ - average_cb_input_density += input_density; - if (0. < input_density) { - avg_density_cnt++; - } - } - } - /*check side_cnt */ - assert(1 == side_cnt); - - /* Add loads */ - side_cnt = 0; - /* Print the ports of grids*/ - /* only check ipin_rr_nodes of cur_cb_info */ - for (side = 0; side < cur_cb_info.num_sides; side++) { - /* Bypass side with zero IPINs*/ - if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { - continue; - } - side_cnt++; - assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); - assert(NULL != cur_cb_info.ipin_rr_node[side]); - for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { - /* Print each INPUT Pins of a grid */ - ipin_height = get_grid_pin_height(cur_cb_info.ipin_rr_node[side][inode]->xlow, - cur_cb_info.ipin_rr_node[side][inode]->ylow, - cur_cb_info.ipin_rr_node[side][inode]->ptc_num); - - if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ - fprint_spice_testbench_one_grid_pin_loads(fp, - cur_cb_info.ipin_rr_node[side][inode]->xlow, - cur_cb_info.ipin_rr_node[side][inode]->ylow, - ipin_height, - cur_cb_info.ipin_rr_node_grid_side[side][inode], - cur_cb_info.ipin_rr_node[side][inode]->ptc_num, - &testbench_load_cnt, - LL_rr_node_indices); - } - fprintf(fp, "\n"); - /* Get signal activity */ - input_density = get_rr_node_net_density(*cur_cb_info.ipin_rr_node[side][inode]); - input_probability = get_rr_node_net_probability(*cur_cb_info.ipin_rr_node[side][inode]); - input_init_value = get_rr_node_net_init_value(*cur_cb_info.ipin_rr_node[side][inode]); - /* Update statistics */ - average_cb_input_density += input_density; - if (0. < input_density) { - avg_density_cnt++; - } - } - } - /* Make sure only 2 sides of IPINs are printed */ - assert((1== side_cnt)||(2 == side_cnt)); - - /* Voltage stilumli */ - /* Connect to VDD supply */ - fprintf(fp, "***** Voltage supplies *****\n"); - switch(chan_type) { - case CHANX: - /* Connect to VDD supply */ - fprintf(fp, "***** Voltage supplies *****\n"); - fprintf(fp, "Vgvdd_cb[%d][%d] gvdd_cbx[%d][%d] 0 vsp\n", x, y, x, y); - break; - case CHANY: - /* Connect to VDD supply */ - fprintf(fp, "***** Voltage supplies *****\n"); - fprintf(fp, "Vgvdd_cb[%d][%d] gvdd_cby[%d][%d] 0 vsp\n", x, y, x, y); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - /* SRAM Voltage stimulit */ - fprintf(fp, "V%s %s 0 vsp\n", - spice_tb_global_vdd_cb_sram_port_name, - spice_tb_global_vdd_cb_sram_port_name); - - /* Calculate the num_sim_clock_cycle for this MUX, update global max_sim_clock_cycle in this testbench */ - if (0 < avg_density_cnt) { - average_cb_input_density = average_cb_input_density/avg_density_cnt; - num_sim_clock_cycles = (int)(1/average_cb_input_density) + 1; - used = 1; - } else { - assert(0 == avg_density_cnt); - average_cb_input_density = 0.; - num_sim_clock_cycles = 2; - used = 0; - } - if (TRUE == auto_select_max_sim_num_clock_cycles) { - /* for idle blocks, 2 clock cycle is well enough... */ - if (2 < num_sim_clock_cycles) { - num_sim_clock_cycles = upbound_sim_num_clock_cycles; - } else { - num_sim_clock_cycles = 2; - } - if (max_sim_num_clock_cycles < num_sim_clock_cycles) { - max_sim_num_clock_cycles = num_sim_clock_cycles; - } - } else { - num_sim_clock_cycles = max_sim_num_clock_cycles; - } - - /* Measurements */ - fprint_spice_netlist_transient_setting(fp, spice, num_sim_clock_cycles, FALSE); - fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); - /* Measure the delay of MUX */ - fprintf(fp, "***** Measurements *****\n"); - /* Measure the leakage power of MUX */ - fprintf(fp, "***** Leakage Power Measurement *****\n"); - fprintf(fp, ".meas tran leakage_power_cb avg p(Vgvdd_cb[%d][%d]) from=0 to='clock_period'\n", - x, y); - /* Measure the leakage power of SRAMs */ - fprintf(fp, ".meas tran leakage_power_sram_cb avg p(V%s) from=0 to='clock_period'\n", - spice_tb_global_vdd_cb_sram_port_name); - /* Measure the dynamic power of MUX */ - fprintf(fp, "***** Dynamic Power Measurement *****\n"); - fprintf(fp, ".meas tran dynamic_power_cb avg p(Vgvdd_cb[%d][%d]) from='clock_period' to='%d*clock_period'\n", - x, y, num_sim_clock_cycles); - fprintf(fp, ".meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period'\n"); - /* Measure the dynamic power of SRAMs */ - fprintf(fp, ".meas tran dynamic_power_sram_cb avg p(V%s) from='clock_period' to='%d*clock_period'\n", - spice_tb_global_vdd_cb_sram_port_name, - num_sim_clock_cycles); - fprintf(fp, ".meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period'\n"); - - /* print average cb input density */ - switch(chan_type) { - case CHANX: - /* - vpr_printf(TIO_MESSAGE_INFO,"Average density of CBX[%d][%d] inputs is %.2g.\n", x, y, average_cb_input_density); - */ - break; - case CHANY: - /* - vpr_printf(TIO_MESSAGE_INFO,"Average density of CBY[%d][%d] inputs is %.2g.\n", x, y, average_cb_input_density); - */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - - return used; -} - -/** In a testbench, we call the subckt of a defined switch block (sb[x][y]) - * For each input of switch block, we find their activities and generate input voltage pulses. - * For each output of switch block, we add all the non-inverter downstream components as load. - */ -static -int fprint_spice_routing_testbench_call_one_sb_tb(FILE* fp, - t_spice spice, - int x, int y, - t_ivec*** LL_rr_node_indices) { - int itrack, inode, side, ipin_height, ix, iy; - int used = 0; - t_sb cur_sb_info; - - char* outport_name = NULL; - char* rr_node_outport_name = NULL; - - float input_density; - float input_probability; - int input_init_value; - float average_sb_input_density = 0.; - int avg_density_cnt = 0; - - int num_sim_clock_cycles = 0; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - - /* call the defined switch block sb[x][y]*/ - fprintf(fp, "***** Call defined Switch Box[%d][%d] *****\n", x, y); - fprint_call_defined_one_switch_box(fp, sb_info[x][y]); - - cur_sb_info = sb_info[x][y]; - - /* For each input of switch block, we generate a input voltage pulse - * For each output of switch block, we generate downstream loads - */ - /* Find all rr_nodes of channels */ - for (side = 0; side < cur_sb_info.num_sides; side++) { - determine_sb_port_coordinator(cur_sb_info, side, &ix, &iy); - - for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { - /* Print voltage stimuli and loads */ - switch (cur_sb_info.chan_rr_node_direction[side][itrack]) { - case OUT_PORT: - /* Output port requires loads*/ - /* We should not add any loads to those outputs that are driven simply by a wire in this switch box! - if (1 == is_sb_interc_between_segments(cur_sb_info.x, cur_sb_info.y, - cur_sb_info.chan_rr_node[side][itrack], side)) { - break; - } - */ - /* Only consider the outputs that are driven by a multiplexer */ - outport_name = (char*)my_malloc(sizeof(char)*( - strlen(convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type)) - + 1 + strlen(my_itoa(cur_sb_info.x)) + 2 + strlen(my_itoa(cur_sb_info.y)) - + 6 + strlen(my_itoa(itrack)) - + 1 + 1)); - sprintf(outport_name, "%s[%d][%d]_out[%d]", - convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), - ix, iy, itrack); - if (TRUE == run_testbench_load_extraction) { /* Additional switch, default on! */ - fprintf(fp, "**** Load for rr_node[%ld] *****\n", cur_sb_info.chan_rr_node[side][itrack] - rr_node); - rr_node_outport_name = fprint_spice_testbench_rr_node_load_version(fp, &testbench_load_cnt, - num_segments, - segments, - 0, - *cur_sb_info.chan_rr_node[side][itrack], - outport_name); - } - /* Free */ - my_free(rr_node_outport_name); - break; - case IN_PORT: - /* Get signal activity */ - input_density = get_rr_node_net_density(*cur_sb_info.chan_rr_node[side][itrack]); - input_probability = get_rr_node_net_probability(*cur_sb_info.chan_rr_node[side][itrack]); - input_init_value = get_rr_node_net_init_value(*cur_sb_info.chan_rr_node[side][itrack]); - /* Update statistics */ - average_sb_input_density += input_density; - if (0. < input_density) { - avg_density_cnt++; - } - /* Input port requires a voltage stimuli */ - /* Add input voltage pulses*/ - fprintf(fp, "***** Signal %s[%d][%d]_in[%d] density = %g, probability=%g.*****\n", - convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), - ix, iy, itrack, - input_density, input_probability); - fprintf(fp, "V%s[%d][%d]_in[%d] %s[%d][%d]_in[%d] 0 \n", - convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), - ix, iy, itrack, - convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), - ix, iy, itrack); - fprint_voltage_pulse_params(fp, input_init_value, input_density, input_probability); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of sb[%d][%d] side[%d] track[%d]!\n", - __FILE__, __LINE__, cur_sb_info.x, cur_sb_info.y, side, itrack); - exit(1); - } - } - /* OPINs of adjacent CLBs are inputs and requires a voltage stimuli */ - /* Input port requires a voltage stimuli */ - for (inode = 0; inode < cur_sb_info.num_opin_rr_nodes[side]; inode++) { - /* Print voltage stimuli of each OPIN */ - ipin_height = get_grid_pin_height(cur_sb_info.opin_rr_node[side][inode]->xlow, - cur_sb_info.opin_rr_node[side][inode]->ylow, - cur_sb_info.opin_rr_node[side][inode]->ptc_num); - fprint_spice_testbench_one_grid_pin_stimulation(fp, - cur_sb_info.opin_rr_node[side][inode]->xlow, - cur_sb_info.opin_rr_node[side][inode]->ylow, - ipin_height, - cur_sb_info.opin_rr_node_grid_side[side][inode], - cur_sb_info.opin_rr_node[side][inode]->ptc_num, - LL_rr_node_indices); - /* Get signal activity */ - input_density = get_rr_node_net_density(*cur_sb_info.opin_rr_node[side][inode]); - input_probability = get_rr_node_net_probability(*cur_sb_info.opin_rr_node[side][inode]); - input_init_value = get_rr_node_net_init_value(*cur_sb_info.opin_rr_node[side][inode]); - /* Update statistics */ - average_sb_input_density += input_density; - if (0. < input_density) { - avg_density_cnt++; - } - } - fprintf(fp, "\n"); - } - - /* Connect to VDD supply */ - fprintf(fp, "***** Voltage supplies *****\n"); - fprintf(fp, "Vgvdd_sb[%d][%d] gvdd_sb[%d][%d] 0 vsp\n", x, y, x, y); - /* SRAM Voltage stimulit */ - fprintf(fp, "V%s %s 0 vsp\n", - spice_tb_global_vdd_sb_sram_port_name, - spice_tb_global_vdd_sb_sram_port_name); - - /* Calculate the num_sim_clock_cycle for this MUX, update global max_sim_clock_cycle in this testbench */ - if (0 < avg_density_cnt) { - average_sb_input_density = average_sb_input_density/avg_density_cnt; - num_sim_clock_cycles = (int)(1/average_sb_input_density) + 1; - used = 1; - } else { - assert(0 == avg_density_cnt); - average_sb_input_density = 0.; - num_sim_clock_cycles = 2; - used = 0; - } - if (TRUE == auto_select_max_sim_num_clock_cycles) { - /* for idle blocks, 2 clock cycle is well enough... */ - if (2 < num_sim_clock_cycles) { - num_sim_clock_cycles = upbound_sim_num_clock_cycles; - } else { - num_sim_clock_cycles = 2; - } - if (max_sim_num_clock_cycles < num_sim_clock_cycles) { - max_sim_num_clock_cycles = num_sim_clock_cycles; - } - } else { - num_sim_clock_cycles = max_sim_num_clock_cycles; - } - - /* Measurements */ - fprint_spice_netlist_transient_setting(fp, spice, num_sim_clock_cycles, FALSE); - fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); - /* Measure the delay of MUX */ - fprintf(fp, "***** Measurements *****\n"); - /* Measure the leakage power of MUX */ - fprintf(fp, "***** Leakage Power Measurement *****\n"); - fprintf(fp, ".meas tran leakage_power_sb avg p(Vgvdd_sb[%d][%d]) from=0 to='clock_period'\n", - x, y); - /* Measure the leakage power of SRAMs */ - fprintf(fp, ".meas tran leakage_power_sram_sb avg p(V%s) from=0 to='clock_period'\n", - spice_tb_global_vdd_sb_sram_port_name); - /* Measure the dynamic power of MUX */ - fprintf(fp, "***** Dynamic Power Measurement *****\n"); - fprintf(fp, ".meas tran dynamic_power_sb avg p(Vgvdd_sb[%d][%d]) from='clock_period' to='%d*clock_period'\n", - x, y, num_sim_clock_cycles); - fprintf(fp, ".meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period'\n"); - /* Measure the dynamic power of SRAMs */ - fprintf(fp, ".meas tran dynamic_power_sram_sb avg p(V%s) from='clock_period' to='%d*clock_period'\n", - spice_tb_global_vdd_sb_sram_port_name, - num_sim_clock_cycles); - fprintf(fp, ".meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period'\n"); - - /* print average sb input density */ - /* - vpr_printf(TIO_MESSAGE_INFO,"Average density of SB[%d][%d] inputs is %.2g.\n", x, y, average_sb_input_density); - */ - - /* Free */ - - return used; -} - -int fprint_spice_one_cb_testbench(char* formatted_spice_dir, - char* circuit_name, - char* cb_testbench_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clocks, - t_arch arch, - int grid_x, int grid_y, t_rr_type cb_type, - boolean leakage_only) { - FILE* fp = NULL; - char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); - char* title = my_strcat("FPGA SPICE Connection Box Testbench Bench for Design: ", circuit_name); - char* cb_testbench_file_path = my_strcat(formatted_spice_dir, cb_testbench_name); - char* cb_tb_name = NULL; - int used = 0; - char* temp_include_file_path = NULL; - - /* one cbx, one cby*/ - switch (cb_type) { - case CHANX: - cb_tb_name = "Connection Box X-channel "; - temp_include_file_path = fpga_spice_create_one_subckt_filename(cbx_spice_file_name_prefix, grid_x, grid_y, spice_netlist_file_postfix); - break; - case CHANY: - cb_tb_name = "Connection Box Y-channel "; - temp_include_file_path = fpga_spice_create_one_subckt_filename(cby_spice_file_name_prefix, grid_x, grid_y, spice_netlist_file_postfix); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid connection_box_type!\n", __FILE__, __LINE__); - exit(1); - } - - /* Check if the path exists*/ - fp = fopen(cb_testbench_file_path,"w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE %s Test bench netlist %s!\n", - __FILE__, __LINE__, cb_tb_name, cb_testbench_file_path); - exit(1); - } - - /* Load global vars in this source file */ - num_segments = arch.num_segments; - segments = arch.Segments; - testbench_load_cnt = 0; - - /* Print the title */ - fprint_spice_head(fp, title); - my_free(title); - - /* print technology library and design parameters*/ - /* fprint_tech_lib(fp, arch.spice->tech_lib); */ - - /* Include parameter header files */ - fprint_spice_include_param_headers(fp, include_dir_path); - - /* Include Key subckts */ - fprint_spice_include_key_subckts(fp, formatted_subckt_dir_path); - - /* Include user-defined sub-circuit netlist */ - init_include_user_defined_netlists(*(arch.spice)); - fprint_include_user_defined_netlists(fp, *(arch.spice)); - - /* Print simulation temperature and other options for SPICE */ - fprint_spice_options(fp, arch.spice->spice_params); - - /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ - fprint_spice_routing_testbench_global_ports(fp, *(arch.spice)); - fprint_spice_cb_testbench_global_ports(fp, *(arch.spice)); - - /* Quote defined Logic blocks subckts (Grids) */ - init_spice_routing_testbench_globals(*(arch.spice)); - - /* one cbx, one cby*/ - switch (cb_type) { - case CHANX: - case CHANY: - /* Generate filename */ - fprintf(fp, "****** Include subckt netlists: %s [%d][%d] *****\n", - cb_tb_name, grid_x, grid_y); - /* Check if we include an existing file! */ - if (FALSE == check_subckt_file_exist_in_llist(routing_spice_subckt_file_path_head, - my_strcat(formatted_subckt_dir_path, temp_include_file_path))) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Intend to include a non-existed SPICE netlist %s!", - __FILE__, __LINE__, temp_include_file_path); - exit(1); - } - spice_print_one_include_subckt_line(fp, formatted_subckt_dir_path, temp_include_file_path); - used = fprint_spice_routing_testbench_call_one_cb_tb(fp, *(arch.spice), cb_type, grid_x, grid_y, LL_rr_node_indices); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid connection_box_type!\n", __FILE__, __LINE__); - exit(1); - } - - - /* Generate SPICE routing testbench generic stimuli*/ - fprintf_spice_routing_testbench_generic_stimuli(fp, num_clocks); - - /* SPICE ends*/ - fprintf(fp, ".end\n"); - - /* Close the file*/ - fclose(fp); - - /* Push the testbench to the linked list */ - tb_head = add_one_spice_tb_info_to_llist(tb_head, cb_testbench_file_path, - max_sim_num_clock_cycles); - used = 1; - - /* Free */ - my_free(temp_include_file_path); - - return used; -} - -int fprint_spice_one_sb_testbench(char* formatted_spice_dir, - char* circuit_name, - char* sb_testbench_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clocks, - t_arch arch, - int grid_x, int grid_y, - boolean leakage_only) { - FILE* fp = NULL; - char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); - char* title = my_strcat("FPGA SPICE Switch Block Testbench Bench for Design: ", circuit_name); - char* sb_testbench_file_path = my_strcat(formatted_spice_dir, sb_testbench_name); - char* sb_tb_name = NULL; - int used = 0; - char* temp_include_file_path = NULL; - - sb_tb_name = "Switch Block "; - - /* Check if the path exists*/ - fp = fopen(sb_testbench_file_path,"w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE %s Test bench netlist %s!\n", - __FILE__, __LINE__, sb_tb_name, sb_testbench_file_path); - exit(1); - } - - /* Load global vars in this source file */ - num_segments = arch.num_segments; - segments = arch.Segments; - testbench_load_cnt = 0; - - /* Print the title */ - fprint_spice_head(fp, title); - my_free(title); - - /* print technology library and design parameters*/ - - /* Include parameter header files */ - fprint_spice_include_param_headers(fp, include_dir_path); - - /* Include Key subckts */ - fprint_spice_include_key_subckts(fp, formatted_subckt_dir_path); - - /* Include user-defined sub-circuit netlist */ - init_include_user_defined_netlists(*(arch.spice)); - fprint_include_user_defined_netlists(fp, *(arch.spice)); - - /* Print simulation temperature and other options for SPICE */ - fprint_spice_options(fp, arch.spice->spice_params); - - /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ - fprint_spice_routing_testbench_global_ports(fp, *(arch.spice)); - fprint_spice_sb_testbench_global_ports(fp, *(arch.spice)); - - /* Quote defined Logic blocks subckts (Grids) */ - init_spice_routing_testbench_globals(*(arch.spice)); - - /* Generate filename */ - fprintf(fp, "****** Include subckt netlists: Switch Block[%d][%d] *****\n", - grid_x, grid_y); - temp_include_file_path = fpga_spice_create_one_subckt_filename(sb_spice_file_name_prefix, grid_x, grid_y, spice_netlist_file_postfix); - /* Check if we include an existing file! */ - if (FALSE == check_subckt_file_exist_in_llist(routing_spice_subckt_file_path_head, - my_strcat(formatted_subckt_dir_path, temp_include_file_path))) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Intend to include a non-existed SPICE netlist %s!", - __FILE__, __LINE__, temp_include_file_path); - exit(1); - } - spice_print_one_include_subckt_line(fp, formatted_subckt_dir_path, temp_include_file_path); - - used = fprint_spice_routing_testbench_call_one_sb_tb(fp, *(arch.spice), grid_x, grid_y, LL_rr_node_indices); - - - /* Generate SPICE routing testbench generic stimuli*/ - fprintf_spice_routing_testbench_generic_stimuli(fp, num_clocks); - - /* SPICE ends*/ - fprintf(fp, ".end\n"); - - /* Close the file*/ - fclose(fp); - - /* Push the testbench to the linked list */ - tb_head = add_one_spice_tb_info_to_llist(tb_head, sb_testbench_file_path, - max_sim_num_clock_cycles); - used = 1; - - return used; -} - -/* Top function: Generate testbenches for all Connection Boxes */ -void spice_print_cb_testbench(char* formatted_spice_dir, - char* circuit_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clocks, - t_arch arch, - boolean leakage_only) { - char* cb_testbench_name = NULL; - int ix, iy; - int cnt = 0; - int used = 0; - - /* X-channel Connection Blocks */ - vpr_printf(TIO_MESSAGE_INFO,"Generating X-channel Connection Block testbench...\n"); - for (iy = 0; iy < (ny+1); iy++) { - for (ix = 1; ix < (nx+1); ix++) { - /* Bypass non-exist CBs */ - if ((FALSE == is_cb_exist(CHANX, ix, iy)) - ||(0 == count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { - continue; - } - cb_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) - + 4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 1 - + strlen(spice_cb_testbench_postfix) + 1 )); - sprintf(cb_testbench_name, "%s_cbx%d_%d%s", - circuit_name, ix, iy, spice_cb_testbench_postfix); - used = fprint_spice_one_cb_testbench(formatted_spice_dir, circuit_name, cb_testbench_name, - include_dir_path, subckt_dir_path, LL_rr_node_indices, - num_clocks, arch, ix, iy, CHANX, - leakage_only); - if (1 == used) { - cnt += used; - } - /* free */ - my_free(cb_testbench_name); - } - } - - /* Y-channel Connection Blocks */ - vpr_printf(TIO_MESSAGE_INFO,"Generating Y-channel Connection Block testbench...\n"); - for (ix = 0; ix < (nx+1); ix++) { - for (iy = 1; iy < (ny+1); iy++) { - /* Bypass non-exist CBs */ - if ((FALSE == is_cb_exist(CHANY, ix, iy)) - ||(0 == count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { - continue; - } - cb_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) - + 4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 1 - + strlen(spice_cb_testbench_postfix) + 1 )); - sprintf(cb_testbench_name, "%s_cby%d_%d%s", - circuit_name, ix, iy, spice_cb_testbench_postfix); - used = fprint_spice_one_cb_testbench(formatted_spice_dir, circuit_name, cb_testbench_name, - include_dir_path, subckt_dir_path, LL_rr_node_indices, - num_clocks, arch, ix, iy, CHANY, - leakage_only); - if (1 == used) { - cnt += used; - } - /* free */ - my_free(cb_testbench_name); - } - } - /* Update the global counter */ - num_used_cb_tb = cnt; - vpr_printf(TIO_MESSAGE_INFO,"No. of generated Connection Block testbench = %d\n", num_used_cb_tb); - - - return; -} - -/* Top function: Generate testbenches for all Switch Blocks */ -void spice_print_sb_testbench(char* formatted_spice_dir, - char* circuit_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clocks, - t_arch arch, - boolean leakage_only) { - - char* sb_testbench_name = NULL; - int ix, iy; - int cnt = 0; - int used = 0; - - vpr_printf(TIO_MESSAGE_INFO,"Generating Switch Block testbench...\n"); - - for (ix = 0; ix < (nx+1); ix++) { - for (iy = 0; iy < (ny+1); iy++) { - sb_testbench_name = (char*)my_malloc(sizeof(char)*( strlen(circuit_name) - + 4 + strlen(my_itoa(ix)) + 2 + strlen(my_itoa(iy)) + 1 - + strlen(spice_sb_testbench_postfix) + 1 )); - sprintf(sb_testbench_name, "%s_sb%d_%d%s", - circuit_name, ix, iy, spice_sb_testbench_postfix); - used = fprint_spice_one_sb_testbench(formatted_spice_dir, circuit_name, sb_testbench_name, - include_dir_path, subckt_dir_path, LL_rr_node_indices, - num_clocks, arch, ix, iy, - leakage_only); - if (1 == used) { - cnt += used; - } - /* free */ - my_free(sb_testbench_name); - } - } - /* Update the global counter */ - num_used_sb_tb = cnt; - vpr_printf(TIO_MESSAGE_INFO,"No. of generated Switch Block testbench = %d\n", num_used_sb_tb); - - return; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing_testbench.h deleted file mode 100644 index fddafd258..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing_testbench.h +++ /dev/null @@ -1,19 +0,0 @@ - - -void spice_print_cb_testbench(char* formatted_spice_dir, - char* circuit_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clocks, - t_arch arch, - boolean leakage_only); - -void spice_print_sb_testbench(char* formatted_spice_dir, - char* circuit_name, - char* include_dir_path, - char* subckt_dir_path, - t_ivec*** LL_rr_node_indices, - int num_clocks, - t_arch arch, - boolean leakage_only); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_run_scripts.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_run_scripts.c deleted file mode 100644 index fcdb07c61..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_run_scripts.c +++ /dev/null @@ -1,135 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "path_delay.h" -#include "stats.h" - -/* Include spice support headers*/ -#include "read_xml_spice_util.h" -#include "linkedlist.h" -#include "fpga_x2p_globals.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" - -static char* run_hspice_shell_script_name = "run_hspice_sim.sh"; -static char* sim_results_dir_name = "results/"; - -void fprint_run_hspice_shell_script(t_spice spice, - char* spice_simulator_path, - char* spice_dir_path, - char* subckt_dir_path) { - FILE* fp = NULL; - /* Format the directory path */ - char* spice_dir_formatted = format_dir_path(spice_dir_path); - char* shell_script_path = my_strcat(spice_dir_path, run_hspice_shell_script_name); - char* testbench_file = NULL; - char* chomped_testbench_file = NULL; - char* chomped_testbench_path = NULL; - char* chomped_testbench_name = NULL; - char* sim_results_dir_path = my_strcat(spice_dir_formatted, sim_results_dir_name); - t_llist* temp = tb_head; - int progress_cnt = 0; - int total_num_sim = 0; - int num_sim_clock_cycle = 0; - - create_dir_path(sim_results_dir_path); - - /* Check if the path exists*/ - fp = fopen(shell_script_path,"w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create Shell Script for running HSPICE %s!", - __FILE__, __LINE__, shell_script_path); - exit(1); - } - - /* Go to the subckt dir for HSPICE VerilogA sim*/ - - /* For VerilogA initilization */ - if (1 == rram_design_tech) { - fprintf(fp, "cd %s\n", subckt_dir_path); - /* Error out when there is no specified simulator path */ - if (NULL == spice_simulator_path) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])SPICE simulator path must be specified when RRAM tech is used!", - __FILE__, __LINE__); - exit(1); - } - fprintf(fp, "source %s/cshrc.meta\n", spice_simulator_path); - } - - total_num_sim = 0; - temp = tb_head; - while(temp) { - total_num_sim++; - temp = temp->next; - } - - progress_cnt = 0; - temp = tb_head; - /* Run hspice lut testbench netlist */ - while(temp) { - testbench_file = ((t_spicetb_info*)(temp->dptr))->tb_name; - num_sim_clock_cycle = ((t_spicetb_info*)(temp->dptr))->num_sim_clock_cycles; - chomped_testbench_file = chomp_file_name_postfix(testbench_file); - split_path_prog_name(chomped_testbench_file,'/',&chomped_testbench_path ,&chomped_testbench_name); - fprintf(fp, "echo \"Number of clock cycles in simulation: %d\"\n", num_sim_clock_cycle); - fprintf(fp, "echo \"Simulation progress: %d Finish, %d to go, total %d\"\n", - progress_cnt, total_num_sim - progress_cnt, total_num_sim); - progress_cnt++; - - if (NULL != spice_simulator_path) { - fprintf(fp, "%s", spice_simulator_path); - } - fprintf(fp, "hspice64 -mt %d -i %s -o %s%s.lis ", - spice_sim_multi_thread_num, - testbench_file, sim_results_dir_path, chomped_testbench_name); - temp = temp->next; - if (1 == rram_design_tech) { - if (NULL == spice_simulator_path) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])SPICE simulator path must be specified when RRAM tech is used!", - __FILE__, __LINE__); - exit(1); - } - fprintf(fp, "-hdlpath %s/include\n", spice_simulator_path); - } else { - fprintf(fp, "\n"); - } - } - - fprintf(fp, "echo \"Simulation progress: %d Finish, %d to go, total %d\"\n", - progress_cnt, total_num_sim - progress_cnt, total_num_sim); - - if (1 == rram_design_tech) { - fprintf(fp, "cd %s\n", spice_dir_path); - } - - /* close fp */ - fclose(fp); - - vpr_printf(TIO_MESSAGE_INFO,"Shell Script for running HSPICE (%s) has been created successfully!\n", shell_script_path); - - /* Free */ - my_free(spice_dir_formatted); - my_free(shell_script_path); - my_free(chomped_testbench_file); - - return; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_run_scripts.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_run_scripts.h deleted file mode 100644 index 188cdde9d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_run_scripts.h +++ /dev/null @@ -1,5 +0,0 @@ - -void fprint_run_hspice_shell_script(t_spice spice, - char* spice_simulator_path, - char* spice_dir_path, - char* subckt_dir_path); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_subckt.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_subckt.c deleted file mode 100644 index 09ca2854e..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_subckt.c +++ /dev/null @@ -1,749 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_types.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "spice_utils.h" -#include "spice_mux.h" -#include "spice_lut.h" -#include "spice_pbtypes.h" -#include "spice_routing.h" -#include "spice_subckt.h" - -/***** Local Subroutines *****/ -static -int search_tapbuf_llist_same_settings(t_llist* head, - t_spice_model_buffer* output_buf); - -static -int generate_spice_basics(char* subckt_dir, t_spice spice); - -/* Generate the NMOS and PMOS */ -int generate_spice_nmos_pmos(char* subckt_dir, - t_spice_tech_lib tech_lib) { - FILE* fp = NULL; - char* sp_name = my_strcat(subckt_dir,nmos_pmos_spice_file_name); - /* Standard transistors */ - t_spice_transistor_type* nmos_trans = NULL; - t_spice_transistor_type* pmos_trans = NULL; - /* I/O transistors */ - t_spice_transistor_type* io_nmos_trans = NULL; - t_spice_transistor_type* io_pmos_trans = NULL; - - /* Spot NMOS*/ - nmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_NMOS); - if (NULL == nmos_trans) { - vpr_printf(TIO_MESSAGE_ERROR,"NMOS transistor is not defined in architecture XML!\n"); - exit(1); - } - - /* Spot PMOS*/ - pmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_PMOS); - if (NULL == pmos_trans) { - vpr_printf(TIO_MESSAGE_ERROR,"PMOS transistor is not defined in architecture XML!\n"); - exit(1); - } - - fp = fopen(sp_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in SPICE netlist for NMOS and PMOS subckt: %s \n", - __FILE__, __LINE__, nmos_pmos_spice_file_name); - exit(1); - } - fprint_spice_head(fp,"Standard and I/O NMOS and PMOS"); - - /* print sub circuit for PMOS*/ - fprintf(fp,"* Standard NMOS\n"); - fprintf(fp,".subckt %s drain gate source bulk L=nl W=wn\n", nmos_subckt_name); - fprintf(fp,"%s1 drain gate source bulk %s L=L W=W\n", tech_lib.model_ref, nmos_trans->model_name); - fprintf(fp,".eom %s\n", nmos_subckt_name); - - fprintf(fp,"\n"); - /* Print sub circuit for PMOS*/ - fprintf(fp,"* Standard PMOS\n"); - fprintf(fp,".subckt %s drain gate source bulk L=pl W=wp\n", pmos_subckt_name); - fprintf(fp,"%s1 drain gate source bulk %s L=L W=W\n", tech_lib.model_ref, pmos_trans->model_name); - fprintf(fp,".eom %s\n", pmos_subckt_name); - - /* Spot I/O NMOS*/ - io_nmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_IO_NMOS); - - if (NULL == io_nmos_trans) { - vpr_printf(TIO_MESSAGE_WARNING,"I/O NMOS transistor is not defined in architecture XML!\n"); - } else { - /* print sub circuit for NMOS*/ - fprintf(fp,"* I/O NMOS\n"); - fprintf(fp,".subckt %s drain gate source bulk L=io_nl W=io_wn\n", io_nmos_subckt_name); - fprintf(fp,"%s1 drain gate source bulk %s L=L W=W\n", tech_lib.model_ref, io_nmos_trans->model_name); - fprintf(fp,".eom %s\n", io_nmos_subckt_name); - } - - /* Spot I/O PMOS*/ - io_pmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_IO_PMOS); - - if (NULL == io_pmos_trans) { - vpr_printf(TIO_MESSAGE_WARNING,"I/O PMOS transistor is not defined in architecture XML!\n"); - } else { - /* print sub circuit for PMOS*/ - fprintf(fp,"* I/O PMOS\n"); - fprintf(fp,".subckt %s drain gate source bulk L=io_pl W=io_wp\n", io_pmos_subckt_name); - fprintf(fp,"%s1 drain gate source bulk %s L=L W=W\n", tech_lib.model_ref, io_pmos_trans->model_name); - fprintf(fp,".eom %s\n", io_pmos_subckt_name); - } - - fclose(fp); - - return 1; -} - -static -int search_tapbuf_llist_same_settings(t_llist* head, - t_spice_model_buffer* output_buf) { - t_llist* temp = head; - t_spice_model_buffer* cur_out_buf = NULL; - - /* check */ - if ((NULL == output_buf)||(NULL == head)) { - return 0; - } - assert(NULL != output_buf); - assert(TRUE == output_buf->tapered_buf); - - while(temp) { - cur_out_buf = (t_spice_model_buffer*)(temp->dptr); - assert(TRUE == cur_out_buf->tapered_buf); - if ((cur_out_buf->tap_buf_level == output_buf->tap_buf_level) - &&(cur_out_buf->f_per_stage == output_buf->f_per_stage)) { - return 1; - } - temp = temp->next; - } - return 0; -} - -/* Generate the subckt for a normal tapered buffer */ -void generate_spice_subckt_tapbuf(FILE* fp, - t_spice_model_buffer* output_buf) { - int istage, j; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create top SPICE netlist %s",__FILE__, __LINE__, basics_spice_file_name); - exit(1); - } - - assert(NULL != output_buf); - assert(TRUE == output_buf->tapered_buf); - assert(0 < output_buf->tap_buf_level); - assert(0 < output_buf->f_per_stage); - - /* Definition line */ - fprintf(fp, ".subckt tapbuf_level%d_f%d in out svdd sgnd\n", output_buf->tap_buf_level, output_buf->f_per_stage); - /* Main body of tapered buffer */ - fprintf(fp, "Rinv_in in in_lvl0 0\n"); - /* Print each stage */ - for (istage = 0; istage < output_buf->tap_buf_level; istage++) { - for (j = 0; j < output_buf->size * pow(output_buf->f_per_stage,istage); j++) { - fprintf(fp, "Xinv_lvl%d_no%d in_lvl%d in_lvl%d svdd sgnd inv\n", - istage, j, istage, istage + 1); - } - } - fprintf(fp, "Rinv_out in_lvl%d out 0\n", output_buf->tap_buf_level); - /* End of subckt*/ - fprintf(fp, ".eom\n\n"); - - return; -} - -/* Generate the subckt for a power-gated tapered buffer */ -void generate_spice_subckt_powergated_tapbuf(FILE* fp, - t_spice_model_buffer* output_buf) { - int istage, j; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create top SPICE netlist %s",__FILE__, __LINE__, basics_spice_file_name); - exit(1); - } - - assert(NULL != output_buf); - assert(TRUE == output_buf->exist); - assert(TRUE == output_buf->tapered_buf); - assert(0 < output_buf->tap_buf_level); - assert(0 < output_buf->f_per_stage); - - /* Definition line */ - fprintf(fp, ".subckt pg_tapbuf_level%d_f%d en enb in out svdd sgnd\n", output_buf->tap_buf_level, output_buf->f_per_stage); - /* Main body of tapered buffer */ - fprintf(fp, "Rinv_in in in_lvl0 0\n"); - /* Print each stage */ - for (istage = 0; istage < output_buf->tap_buf_level; istage++) { - for (j = 0; j < output_buf->size * pow(output_buf->f_per_stage,istage); j++) { - fprintf(fp, "Xinv_lvl%d_no%d en enb in_lvl%d in_lvl%d svdd sgnd pg_inv size=1 pg_size=1\n", - istage, j, istage, istage + 1); - } - } - fprintf(fp, "Rinv_out in_lvl%d out 0\n", output_buf->tap_buf_level); - /* End of subckt*/ - fprintf(fp, ".eom\n\n"); - - /* Generate a power-gated tap_buf */ - - return; -} - - -static -int generate_spice_basics(char* subckt_dir, t_spice spice) { - FILE* fp = NULL; - char* sp_name = my_strcat(subckt_dir, basics_spice_file_name); - int imodel = 0; - t_llist* tapered_bufs_head = NULL; - t_llist* temp = NULL; - - fp = fopen(sp_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create top SPICE netlist %s",__FILE__, __LINE__, basics_spice_file_name); - exit(1); - } - fprint_spice_head(fp,"Inverter, Buffer, Trans. Gate"); - - /* TODO: support power-gated inverter and buffer ! - * We have two options: - * 1. Add power-gate transistors to each inverter/buffer - * 2. Add huge power-gate transistors to the VDD and GND of inverters - */ - /* Inverter */ - fprintf(fp,"* Inverter\n"); - fprintf(fp,".subckt inv in out svdd sgnd size=1\n"); - fprintf(fp,"Xn0_inv out in sgnd sgnd %s L=nl W=\'size*wn\'\n",nmos_subckt_name); - fprintf(fp,"Xp0_inv out in svdd svdd %s L=pl W=\'size*beta*wp\'\n",pmos_subckt_name); - fprintf(fp,".eom inv\n"); - fprintf(fp,"\n"); - /* Power-gated Inverter */ - fprintf(fp,"* Powergated Inverter\n"); - fprintf(fp,".subckt pg_inv en enb in out svdd sgnd size=1 pg_size=1\n"); - fprintf(fp,"Xn0_inv out in sgnd_pg sgnd %s L=nl W=\'size*wn\'\n",nmos_subckt_name); - fprintf(fp,"Xp0_inv out in svdd_pg svdd %s L=pl W=\'size*beta*wp\'\n",pmos_subckt_name); - fprintf(fp,"Xn0_inv_pg sgnd_pg en sgnd sgnd %s L=nl W=\'pg_size*wn\'\n",nmos_subckt_name); - fprintf(fp,"Xp0_inv_pg svdd_pg enb svdd svdd %s L=pl W=\'pg_size*beta*wp\'\n",pmos_subckt_name); - fprintf(fp,".eom inv\n"); - fprintf(fp,"\n"); - - /* Buffer */ - fprintf(fp,"* Buffer\n"); - fprintf(fp,".subckt buf in out svdd sgnd size=2 base_size=1\n"); - fprintf(fp,"Xinv0 in mid svdd sgnd inv base_size='base_size'\n"); - fprintf(fp,"Xinv1 mid out svdd sgnd inv size='size*base_size'\n"); - fprintf(fp,".eom buf\n"); - fprintf(fp,"\n"); - - /* Power-gated Buffer */ - fprintf(fp,"* Power-gated Buffer\n"); - fprintf(fp,".subckt pg_buf en enb in out svdd sgnd size=2 pg_size=2\n"); - fprintf(fp,"Xinv0 en enb in mid svdd sgnd pg_inv size=1 pg_size=1\n"); - fprintf(fp,"Xinv1 en enb mid out svdd sgnd pg_inv size=size pg_size=size\n"); - fprintf(fp,".eom buf\n"); - fprintf(fp,"\n"); - - /* Transmission Gate*/ - fprintf(fp,"* Transmission Gate (Complementary Pass Transistor)\n"); - fprintf(fp,".subckt cpt in out sel sel_inv svdd sgnd nmos_size=1 pmos_size=1\n"); - fprintf(fp,"Xn0_cpt in sel out sgnd %s L=nl W=\'nmos_size*wn\'\n", nmos_subckt_name); - fprintf(fp,"Xp0_cpt in sel_inv out svdd %s L=pl W=\'pmos_size*wp\'\n", pmos_subckt_name); - fprintf(fp,".eom cpt\n"); - fprintf(fp,"\n"); - - /* Tapered buffered support */ - for (imodel = 0; imodel < spice.num_spice_model; imodel++) { - /* Bypass basic components */ - if (SPICE_MODEL_INVBUF != spice.spice_models[imodel].type) { - continue; - } - /* Bypass un tapered buffers */ - if (TRUE != spice.spice_models[imodel].design_tech_info.buffer_info->tapered_buf) { - continue; - } - if (NULL == tapered_bufs_head) { - tapered_bufs_head = create_llist(1); - tapered_bufs_head->dptr = (void*)spice.spice_models[imodel].design_tech_info.buffer_info; - } else if (FALSE == search_tapbuf_llist_same_settings(tapered_bufs_head, spice.spice_models[imodel].design_tech_info.buffer_info)) { - temp = insert_llist_node(tapered_bufs_head); - temp->dptr = (void*)spice.spice_models[imodel].design_tech_info.buffer_info; - } - } - /* Print all the tapered_buf */ - temp = tapered_bufs_head; - while(temp) { - generate_spice_subckt_tapbuf(fp, (t_spice_model_buffer*)(temp->dptr)); - temp = temp->next; - } - - fclose(fp); - - /* Free */ - temp = tapered_bufs_head; - while(temp) { - temp->dptr = NULL; - temp = temp->next; - } - free_llist(tapered_bufs_head); - - return 1; -} - -void generate_spice_rram_veriloga(char* subckt_dir, - t_spice spice) { - FILE* fp = NULL; - char* sp_name = NULL; - int imodel, write_model; - - /* Check if we need such a verilogA model */ - write_model = 0; - for (imodel = 0; imodel < spice.num_spice_model; imodel++) { - if (SPICE_MODEL_DESIGN_RRAM == spice.spice_models[imodel].design_tech) { - write_model = 1; - break; - } - } - if (0 == write_model) { - return; - } else { - rram_design_tech = 1; - } - - sp_name = my_strcat(subckt_dir, rram_veriloga_file_name); - /* Open a File */ - fp = fopen(sp_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE netlist %s",__FILE__, __LINE__, wires_spice_file_name); - exit(1); - } - fprintf(fp,"// RRAM Behavior VerilogA Mode\n"); - - /* Include the headers of VerilogA */ - fprintf(fp, "`include \"constants.vams\"\n"); - fprintf(fp, "`include \"disciplines.vams\"\n"); - - /* Model */ - fprintf(fp, "\n"); - fprintf(fp, "module rram_behavior(TE, BE, SRAM, SRAM_INV);\n"); - fprintf(fp, "input SRAM, SRAM_INV;\n"); - fprintf(fp, "inout TE, BE;\n"); - fprintf(fp, "electrical TE, BE, SRAM, SRAM_INV;\n"); - fprintf(fp, "// Design Parameters\n"); - fprintf(fp, "parameter integer initial_state = 0 from [0:1];\n"); - fprintf(fp, "parameter real switch_thres = 1.8 from (0:inf);\n"); - fprintf(fp, "parameter real ron = 1e3 from (0:inf);\n"); - fprintf(fp, "parameter real roff = 1e6 from (0:inf);\n"); - fprintf(fp, "// Local Parameters\n"); - fprintf(fp, "real res = roff;\n"); - fprintf(fp, "real voltage_tolerence = 0;\n"); - fprintf(fp, "integer state = 0;\n"); - fprintf(fp, "\n"); - fprintf(fp, "analog begin\n"); - fprintf(fp, " // Initial\n"); - fprintf(fp, " @(initial_step) begin\n"); - fprintf(fp, " state = initial_state;\n"); - fprintf(fp, " end\n"); - fprintf(fp, " // State\n"); - fprintf(fp, " if (V(SRAM,SRAM_INV) < voltage_tolerence*switch_thres) begin\n"); - fprintf(fp, " state = 0;\n"); - fprintf(fp, " end else begin\n"); - fprintf(fp, " state = 1;\n"); - fprintf(fp, " end\n"); - fprintf(fp, " //LRS\n"); - fprintf(fp, " if (1 == state) begin\n"); - fprintf(fp, " res = ron;\n"); - fprintf(fp, " //HRS\n"); - fprintf(fp, " end else begin\n"); - fprintf(fp, " res = roff;\n"); - fprintf(fp, " end\n"); - fprintf(fp, " // Correlated Resistance with TE and BE\n"); - fprintf(fp, " I(TE,BE) <+ V(TE,BE) / res;\n"); - fprintf(fp, "end\n"); - fprintf(fp, "endmodule\n"); - - /* Close File */ - fclose(fp); - - /* Free */ - my_free(sp_name); - - return; -} - -void fprint_spice_wire_model(FILE* fp, - char* wire_subckt_name, - t_spice_model spice_model, - float res_total, - float cap_total) { - float res_per_level = 0.; - float cap_per_level = 0.; - int i; - int num_input_port = 0; - int num_output_port = 0; - t_spice_model_port** input_port = NULL; - t_spice_model_port** output_port = NULL; - - /* Ensure a valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Check the wire model*/ - assert(NULL != spice_model.wire_param); - assert(0 < spice_model.wire_param->level); - /* Find the input port, output port*/ - input_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); - output_port = find_spice_model_ports(&spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); - - /* Asserts*/ - assert(1 == num_input_port); - assert(1 == num_output_port); - assert(1 == input_port[0]->size); - assert(1 == output_port[0]->size); - /* print the spice model*/ - fprintf(fp, "* Wire, spice_model_name=%s\n", spice_model.name); - switch (spice_model.type) { - case SPICE_MODEL_CHAN_WIRE: - /* Add an output at middle point for connecting CB inputs */ - fprintf(fp, ".subckt %s %s %s mid_out svdd sgnd\n", - wire_subckt_name, input_port[0]->prefix, output_port[0]->prefix); - break; - case SPICE_MODEL_WIRE: - /* Add an output at middle point for connecting CB inputs */ - fprintf(fp, ".subckt %s %s %s svdd sgnd\n", - wire_subckt_name, input_port[0]->prefix, output_port[0]->prefix); - /* Direct shortcut */ - if ((0. == cap_per_level)&&(0. == res_per_level) - &&(0 == spice_model.input_buffer->exist) - &&(0 == spice_model.output_buffer->exist)) { - fprintf(fp, "Rshortcut %s %s 0\n", input_port[0]->prefix, output_port[0]->prefix); - /* Finish*/ - fprintf(fp, ".eom\n"); - fprintf(fp, "\n"); - return; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of spice_model! Expect [chan_wire|wire].\n", - __FILE__, __LINE__); - exit(1); - } - - - /* Determine which type of model to print*/ - switch (spice_model.wire_param->type) { - case WIRE_MODEL_PIE : - /* Determine the resistance and capacitance of each level*/ - res_per_level = res_total/((float)(2*spice_model.wire_param->level)); - cap_per_level = cap_total/((float)(spice_model.wire_param->level + 1)); - if ((0. == cap_per_level)&&(0. == res_per_level)) { - /* Special: if R and C are all zeros, we use a zero-voltage source instead */ - fprintf(fp, "Vshortcut pie_wire_in%d pie_wire_in%d 0\n", - 0, spice_model.wire_param->level); - if (SPICE_MODEL_CHAN_WIRE == spice_model.type) { - fprintf(fp, "* Connect the output of middle point\n"); - fprintf(fp, "Vmid_out_ckt pie_wire_in0 mid_out 0\n"); - } - i = spice_model.wire_param->level; - break; - } - if (0. != cap_per_level) { - fprintf(fp, "Clvin pie_wire_in0 sgnd \'%s%s/%d\'\n", - spice_model.name, - design_param_postfix_wire_param_cap_val, - spice_model.wire_param->level + 1); - } - for (i = 0; i < spice_model.wire_param->level; i++) { - fprintf(fp, "Rlv%d_idx0 pie_wire_in%d pie_wire_in%d_inter \'%s%s/%d\'\n", - i, i, i, - spice_model.name, - design_param_postfix_wire_param_res_val, - 2* spice_model.wire_param->level); - fprintf(fp, "Rlv%d_idx1 pie_wire_in%d_inter pie_wire_in%d \'%s%s/%d\'\n", - i, i, i + 1, - spice_model.name, - design_param_postfix_wire_param_res_val, - 2* spice_model.wire_param->level); - if (0. != cap_per_level) { - fprintf(fp, "Clv%d_idx1 pie_wire_in%d sgnd \'%s%s/%d\'\n", - i, i + 1, - spice_model.name, - design_param_postfix_wire_param_cap_val, - spice_model.wire_param->level + 1); - } - } - if (SPICE_MODEL_CHAN_WIRE == spice_model.type) { - /*Connect the middle point */ - fprintf(fp, "* Connect the output of middle point\n"); - if (0 == spice_model.wire_param->level%2) { - fprintf(fp, "Vmid_out_ckt pie_wire_in%d mid_out 0\n", spice_model.wire_param->level/2); - } else if (1 == spice_model.wire_param->level%2) { - fprintf(fp, "Vmid_out_ckt pie_wire_in%d_inter mid_out 0\n", spice_model.wire_param->level/2); - } - } - break; - case WIRE_MODEL_T : - /* Determine the resistance and capacitance of each level*/ - res_per_level = res_total/((float)(2*spice_model.wire_param->level)); - cap_per_level = cap_total/((float)(spice_model.wire_param->level)); - if ((0. == cap_per_level)&&(0. == res_per_level)) { - fprintf(fp, "Vshortcut pie_wire_in%d pie_wire_in%d 0\n", - 0, spice_model.wire_param->level); - if (SPICE_MODEL_CHAN_WIRE == spice_model.type) { - fprintf(fp, "* Connect the output of middle point\n"); - fprintf(fp, "Vmid_out_ckt pie_wire_in0 mid_out 0\n"); - } - i = spice_model.wire_param->level; - break; - } - for (i = 0; i < spice_model.wire_param->level; i++) { - fprintf(fp, "Rlv%d_idx0 pie_wire_in%d pie_wire_in%d_inter \'%s%s/%d\'\n", - i, i, i, - spice_model.name, - design_param_postfix_wire_param_res_val, - 2 * spice_model.wire_param->level); - if (0. != cap_per_level) { - fprintf(fp, "Clv%d_idx1 pie_wire_in%d_inter sgnd \'%s%s/%d\'\n", - i, i, - spice_model.name, - design_param_postfix_wire_param_cap_val, - spice_model.wire_param->level); - } - fprintf(fp, "Rlv%d_idx2 pie_wire_in%d_inter pie_wire_in%d \'%s%s/%d\'\n", - i, i, i + 1, - spice_model.name, - design_param_postfix_wire_param_res_val, - 2 * spice_model.wire_param->level); - } - if (SPICE_MODEL_CHAN_WIRE == spice_model.type) { - /*Connect the middle point */ - fprintf(fp, "* Connect the output of middle point\n"); - if (0 == spice_model.wire_param->level%2) { - fprintf(fp, "Vmid_out_ckt pie_wire_in%d mid_out 0\n", spice_model.wire_param->level/2); - } else if (1 == spice_model.wire_param->level%2) { - fprintf(fp, "Vmid_out_ckt pie_wire_in%d_inter mid_out 0\n", spice_model.wire_param->level/2); - } - } - break; - default: - vpr_printf(TIO_MESSAGE_INFO,"(File:%s,[LINE%d])Invalid SPICE Wire Model type of spice_model(%s).\n", - __FILE__, __LINE__, spice_model.name); - exit(1); - } - assert(i == spice_model.wire_param->level); - - /* Add input, output buffers*/ - assert(NULL != spice_model.input_buffer); - if (spice_model.input_buffer->exist) { - switch (spice_model.input_buffer->type) { - case SPICE_MODEL_BUF_INV: - /* Each inv: svdd sgnd size=param*/ - fprintf(fp, "Xinv_in "); /* Given name*/ - fprintf(fp, "%s ", input_port[0]->prefix); /* input port */ - fprintf(fp, "pie_wire_in0 "); /* output port*/ - fprintf(fp, "svdd sgnd inv size=\'%s%s\'", - spice_model.name, - design_param_postfix_input_buf_size); /* subckt name */ - fprintf(fp, "\n"); - break; - case SPICE_MODEL_BUF_BUF: - /* TODO: what about tapered buffer, can we support? */ - /* Each buf: svdd sgnd size=param*/ - fprintf(fp, "Xbuf_in "); /* Given name*/ - fprintf(fp, "%s ", input_port[0]->prefix); /* input port */ - fprintf(fp, "pie_wire_in0 "); /* output port*/ - fprintf(fp, "svdd sgnd buf size=\'%s%s\'", - spice_model.name, - design_param_postfix_output_buf_size); /* subckt name */ - fprintf(fp, "\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", - __FILE__, __LINE__); - exit(1); - } - } else { - /* There is no buffer, I create a zero voltage source between*/ - /* V 0*/ - fprintf(fp, "Rin %s pie_wire_in0 0\n", - input_port[0]->prefix); - } - - assert(NULL != spice_model.output_buffer); - if (spice_model.output_buffer->exist) { - switch (spice_model.output_buffer->type) { - case SPICE_MODEL_BUF_INV: - /* Each inv: svdd sgnd size=param*/ - fprintf(fp, "Xinv_out "); /* Given name*/ - fprintf(fp, "pie_wire_in%d ", spice_model.wire_param->level); /* input port */ - fprintf(fp, "%s ", output_port[0]->prefix); /* output port*/ - fprintf(fp, "svdd sgnd inv size=\'%s%s\'", - spice_model.name, - design_param_postfix_output_buf_size); /* subckt name */ - fprintf(fp, "\n"); - break; - case SPICE_MODEL_BUF_BUF: - /* TODO: what about tapered buffer, can we support? */ - /* Each buf: svdd sgnd size=param*/ - fprintf(fp, "Xbuf_out "); /* Given name*/ - fprintf(fp, "pie_wire_in%d ", spice_model.wire_param->level); /* input port */ - fprintf(fp, "%s ", output_port[0]->prefix); /* output port*/ - fprintf(fp, "svdd sgnd buf size=\'%s%s\'", - spice_model.name, - design_param_postfix_output_buf_size); /* subckt name */ - fprintf(fp, "\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type for spice_model_buffer.\n", - __FILE__, __LINE__); - exit(1); - } - } else { - /* There is no buffer, I create a zero voltage source between*/ - /* V 0*/ - fprintf(fp, "Rout pie_wire_in%d %s 0\n", - spice_model.wire_param->level, output_port[0]->prefix); - } - - /* Finish*/ - fprintf(fp, ".eom\n"); - fprintf(fp, "\n"); - - return; -} - -void generate_spice_wires(char* subckt_dir, - int num_segments, - t_segment_inf* segments, - int num_spice_model, - t_spice_model* spice_models) { - FILE* fp = NULL; - char* sp_name = my_strcat(subckt_dir, wires_spice_file_name); - char* seg_wire_subckt_name = NULL; - char* seg_index_str = NULL; - int iseg, imodel, len_seg_subckt_name; - - fp = fopen(sp_name, "w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create SPICE netlist %s",__FILE__, __LINE__, wires_spice_file_name); - exit(1); - } - fprint_spice_head(fp,"Wires"); - /* Output wire models*/ - for (imodel = 0; imodel < num_spice_model; imodel++) { - if (SPICE_MODEL_WIRE == spice_models[imodel].type) { - assert(NULL != spice_models[imodel].wire_param); - fprint_spice_wire_model(fp, spice_models[imodel].name, - spice_models[imodel], - spice_models[imodel].wire_param->res_val, - spice_models[imodel].wire_param->cap_val); - } - } - - /* Create wire models for routing segments*/ - fprintf(fp,"* Wire models for segments in routing \n"); - for (iseg = 0; iseg < num_segments; iseg++) { - assert(NULL != segments[iseg].spice_model); - assert(SPICE_MODEL_CHAN_WIRE == segments[iseg].spice_model->type); - assert(NULL != segments[iseg].spice_model->wire_param); - /* Give a unique name for subckt of wire_model of segment, - * spice_model name is unique, and segment name is unique as well - */ - seg_index_str = my_itoa(iseg); - len_seg_subckt_name = strlen(segments[iseg].spice_model->name) - + 4 + strlen(seg_index_str) + 1; /* '\0'*/ - seg_wire_subckt_name = (char*)my_malloc(sizeof(char)*len_seg_subckt_name); - sprintf(seg_wire_subckt_name,"%s_seg%s", - segments[iseg].spice_model->name, seg_index_str); - fprint_spice_wire_model(fp, seg_wire_subckt_name, - *(segments[iseg].spice_model), - segments[iseg].Rmetal, - segments[iseg].Cmetal); - } - - /* Close the file handler */ - fclose(fp); - - /*Free*/ - my_free(seg_index_str); - my_free(seg_wire_subckt_name); - - return; -} - -/* Generate the sub circuits for FPGA SPICE Modeling - * Tasks: - * 1. NMOS and PMOS - * 2. Basics: Inverter and Buffers, transmission gates, rc_segements - * 3. Multiplexers - * 4. Look-Up Tables - * 5. Flip-flops - */ -void generate_spice_subckts(char* subckt_dir, - t_arch* arch, - t_det_routing_arch* routing_arch, - boolean compact_routing_hierarchy) { - /* 1.Generate NMOS, PMOS and transmission gate */ - vpr_printf(TIO_MESSAGE_INFO,"Writing SPICE NMOS and PMOS...\n"); - generate_spice_nmos_pmos(subckt_dir, arch->spice->tech_lib); - - /* 2. Generate Inverter, Buffer, and transmission gates*/ - vpr_printf(TIO_MESSAGE_INFO,"Writing SPICE Basic subckts...\n"); - generate_spice_basics(subckt_dir, *(arch->spice)); - - /* 2.5 Generate RRAM Verilog-A model*/ - vpr_printf(TIO_MESSAGE_INFO, "Writing RRAM Behavior Verilog-A model...\n"); - generate_spice_rram_veriloga(subckt_dir, (*(arch->spice))); - - /* 3. Generate Multiplexers */ - vpr_printf(TIO_MESSAGE_INFO,"Writing SPICE Multiplexers...\n"); - generate_spice_muxes(subckt_dir, routing_arch->num_switch, switch_inf, - arch->spice, routing_arch); - - /* 4. Generate Wires*/ - vpr_printf(TIO_MESSAGE_INFO,"Writing SPICE Wires...\n"); - generate_spice_wires(subckt_dir, arch->num_segments, arch->Segments, - arch->spice->num_spice_model, arch->spice->spice_models); - - /* 5. Generate LUTs */ - vpr_printf(TIO_MESSAGE_INFO,"Writing SPICE LUTs...\n"); - generate_spice_luts(subckt_dir, arch->spice->num_spice_model, arch->spice->spice_models); - - /* 6. Generate Routing architecture*/ - vpr_printf(TIO_MESSAGE_INFO, "Writing Routing Resources....\n"); - generate_spice_routing_resources(subckt_dir, (*arch), routing_arch, - num_rr_nodes, rr_node, rr_node_indices); - - /* 7. Generate Logic Blocks */ - vpr_printf(TIO_MESSAGE_INFO,"Writing Logic Blocks...\n"); - generate_spice_logic_blocks(subckt_dir, arch); - - - return; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_subckt.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_subckt.h deleted file mode 100644 index 309c2634d..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_subckt.h +++ /dev/null @@ -1,14 +0,0 @@ - -int generate_spice_nmos_pmos(char* subckt_dir, - t_spice_tech_lib tech_lib); - -int generate_spice_basics(char* subckt_dir, - t_arch arch); - -void generate_spice_subckt_tapbuf(FILE* fp, - t_spice_model_buffer* output_buf); - -void generate_spice_subckts(char* subckt_dir, - t_arch* arch, - t_det_routing_arch* routing_arch, - boolean compact_routing_hierarchy); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_top_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_top_netlist.c deleted file mode 100644 index 0fc6a42db..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_top_netlist.c +++ /dev/null @@ -1,755 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_globals.h" -#include "fpga_x2p_types.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "spice_mux.h" -#include "spice_pbtypes.h" -#include "spice_routing.h" -#include "spice_subckt.h" -#include "spice_utils.h" -#include "spice_top_netlist.h" - -/* Global variables in this source file*/ - - -/******** Subroutines ***********/ -static -void fprint_top_netlist_global_ports(FILE* fp, - int num_clock, - t_spice spice) { - t_spice_model* mem_model = NULL; - int iblock, iopad_idx; - - /* A valid file handler */ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ - /* Print generic global ports*/ - fprint_spice_generic_testbench_global_ports(fp, - sram_spice_orgz_info, - global_ports_head); - - fprintf(fp, ".global %s %s %s\n", - spice_tb_global_vdd_localrouting_port_name, - spice_tb_global_vdd_io_port_name, - spice_tb_global_vdd_hardlogic_port_name); - - /* Print the VDD ports of SRAM belonging to other SPICE module */ - fprintf(fp, ".global %s\n", - spice_tb_global_vdd_localrouting_sram_port_name); - fprintf(fp, ".global %s\n", - spice_tb_global_vdd_lut_sram_port_name); - fprintf(fp, ".global %s\n", - spice_tb_global_vdd_cb_sram_port_name); - fprintf(fp, ".global %s\n", - spice_tb_global_vdd_sb_sram_port_name); - fprintf(fp, ".global %s\n", - spice_tb_global_vdd_io_sram_port_name); - - /* Get memory spice model */ - get_sram_orgz_info_mem_model(sram_spice_orgz_info, &mem_model); - - /*Global Vdds for LUTs*/ - fprint_global_vdds_spice_model(fp, SPICE_MODEL_LUT, spice); - /*Global Vdds for FFs*/ - fprint_global_vdds_spice_model(fp, SPICE_MODEL_FF, spice); - /*Global Vdds for IOs*/ - fprint_global_vdds_spice_model(fp, SPICE_MODEL_IOPAD, spice); - /*Global Vdds for Hardlogics*/ - fprint_global_vdds_spice_model(fp, SPICE_MODEL_HARDLOGIC, spice); - /* Global Vdds for Switch Boxes */ - fprint_spice_global_vdd_switch_boxes(fp); - - /* Global Vdds for Connection Blocks */ - fprint_spice_global_vdd_connection_boxes(fp); - - /*Global ports for INPUTs of I/O PADS, SRAMs */ - fprint_global_pad_ports_spice_model(fp, spice); - - /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs - * This brings convenience to checking functionality - */ - fprintf(fp, "***** Link Blif Benchmark inputs to FPGA IOPADs *****\n"); - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - /* General INOUT*/ - if (iopad_spice_model == logical_block[iblock].mapped_spice_model) { - iopad_idx = logical_block[iblock].mapped_spice_model_index; - /* Make sure We find the correct logical block !*/ - assert((VPACK_INPAD == logical_block[iblock].type)||(VPACK_OUTPAD == logical_block[iblock].type)); - fprintf(fp, "***** Blif Benchmark inout %s is mapped to FPGA IOPAD %s[%d] *****\n", - logical_block[iblock].name, gio_inout_prefix, iopad_idx); - fprintf(fp, "R%s_%s[%d] %s_%s[%d] %s%s[%d] 0\n", - logical_block[iblock].name, gio_inout_prefix, iopad_idx, - logical_block[iblock].name, gio_inout_prefix, iopad_idx, - gio_inout_prefix, iopad_spice_model->prefix, iopad_idx); - } - } - - return; -} - -/* Print Stimulations for top-level netlist - * Task list: - * 1. For global ggnd: connect to 0(gnd) - * 2. For global vdd ports: connect to nominal voltage source - * 3. For clock signal, we should create voltage waveforms - * 4. For Set/Reset, TODO: should we reset the chip in the first cycle ??? - * 5. For input/output clb nets (mapped to I/O grids), we should create voltage waveforms - */ -static -void fprint_top_netlist_stimulations(FILE* fp, - int num_clock, - t_spice spice) { - int inet, iblock, iopad_idx; - int ix, iy; - int found_mapped_iopad = 0; - /* Find Input Pad Spice model */ - t_spice_net_info* cur_spice_net_info = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - /* Print generic stimuli */ - fprint_spice_testbench_generic_global_ports_stimuli(fp, num_clock); - - /* Generate global ports stimuli */ - fprint_spice_testbench_global_ports_stimuli(fp, global_ports_head); - - /* SRAM ports */ - /* Every SRAM inputs should have a voltage source */ - fprintf(fp, "***** Global Inputs for SRAMs *****\n"); - fprint_spice_testbench_global_sram_inport_stimuli(fp, sram_spice_orgz_info); - - fprintf(fp, "***** Global VDD for SRAMs *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_sram_port_name, - "vsp"); - - /* Global Vdd ports */ - fprintf(fp, "***** Global VDD for I/O pads *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_io_port_name, - "vsp"); - - fprintf(fp, "***** Global VDD for I/O pads SRAMs *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_io_sram_port_name, - "vsp"); - - fprintf(fp, "***** Global VDD for Local Interconnection *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_localrouting_port_name, - "vsp"); - - fprintf(fp, "***** Global VDD for CLB to CLB direct connection *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_direct_port_name, - "vsp"); - - fprintf(fp, "***** Global VDD for local routing SRAMs *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_localrouting_sram_port_name, - "vsp"); - - fprintf(fp, "***** Global VDD for LUTs SRAMs *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_lut_sram_port_name, - "vsp"); - - fprintf(fp, "***** Global VDD for Connection Boxes SRAMs *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_cb_sram_port_name, - "vsp"); - - fprintf(fp, "***** Global VDD for Switch Boxes SRAMs *****\n"); - fprint_spice_testbench_global_vdd_port_stimuli(fp, - spice_tb_global_vdd_sb_sram_port_name, - "vsp"); - - /* Every Hardlogic use an independent Voltage source */ - fprintf(fp, "***** Global VDD for Hard Logics *****\n"); - fprint_splited_vdds_spice_model(fp, SPICE_MODEL_HARDLOGIC, spice); - - /* Every LUT use an independent Voltage source */ - fprintf(fp, "***** Global VDD for Look-Up Tables (LUTs) *****\n"); - fprint_splited_vdds_spice_model(fp, SPICE_MODEL_LUT, spice); - - /* Every FF use an independent Voltage source */ - fprintf(fp, "***** Global VDD for Flip-flops (FFs) *****\n"); - fprint_splited_vdds_spice_model(fp, SPICE_MODEL_FF, spice); - - /* Every FF use an independent Voltage source */ - fprintf(fp, "***** Global VDD for Flip-flops (FFs) *****\n"); - fprint_splited_vdds_spice_model(fp, SPICE_MODEL_IOPAD, spice); - - /* Every Switch Box (SB) use an independent Voltage source */ - fprintf(fp, "***** Global VDD for Switch Boxes(SBs) *****\n"); - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 0; iy < (ny + 1); iy++) { - fprintf(fp, "Vgvdd_sb[%d][%d] gvdd_sb[%d][%d] 0 vsp\n", ix, iy, ix, iy); - } - } - - /* Every Connection Box (CB) use an independent Voltage source */ - fprintf(fp, "***** Global VDD for Connection Boxes(CBs) *****\n"); - /* cbx */ - /* X - channels [1...nx][0..ny]*/ - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - fprintf(fp, "Vgvdd_cbx[%d][%d] gvdd_cbx[%d][%d] 0 vsp\n", ix, iy, ix, iy); - } - } - - /* cby */ - /* Y - channels [1...ny][0..nx]*/ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - fprintf(fp, "Vgvdd_cby[%d][%d] gvdd_cby[%d][%d] 0 vsp\n", ix, iy, ix, iy); - } - } - - - /* For each input_signal - * TODO: this part is low-efficent for run-time concern... Need improve - */ - assert(NULL != iopad_spice_model); - for (iopad_idx = 0; iopad_idx < iopad_spice_model->cnt; iopad_idx++) { - /* Find if this inpad is mapped to a logical block */ - found_mapped_iopad = 0; - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - if ((iopad_spice_model == logical_block[iblock].mapped_spice_model) - &&(iopad_idx == logical_block[iblock].mapped_spice_model_index)) { - /* Make sure We find the correct logical block !*/ - if (VPACK_OUTPAD == logical_block[iblock].type) { - /* Bypass outputs */ - found_mapped_iopad++; - continue; - } - assert(VPACK_INPAD == logical_block[iblock].type); - cur_spice_net_info = NULL; - for (inet = 0; inet < num_nets; inet++) { - if (0 == strcmp(clb_net[inet].name, logical_block[iblock].name)) { - cur_spice_net_info = clb_net[inet].spice_net_info; - break; - } - } - if (NULL == cur_spice_net_info) { - assert(NULL != cur_spice_net_info); - } - assert(!(0 > cur_spice_net_info->density)); - /* assert(!(2 < cur_spice_net_info->density)); */ - assert(!(0 > cur_spice_net_info->probability)); - assert(!(1 < cur_spice_net_info->probability)); - /* Get the net information */ - /* First cycle reserved for measuring leakage */ - fprintf(fp, "V%s%s[%d] %s%s[%d] 0 \n", - gio_inout_prefix, - iopad_spice_model->prefix, iopad_idx, - gio_inout_prefix, - iopad_spice_model->prefix, iopad_idx); - fprint_voltage_pulse_params(fp, cur_spice_net_info->init_val, cur_spice_net_info->density, cur_spice_net_info->probability); - /* Short wire to a another node, it is easier to identify in testbench */ - found_mapped_iopad++; - } - } - assert((0 == found_mapped_iopad)||(1 == found_mapped_iopad)); - /* If we find one iopad already, we finished in this round here */ - if (1 == found_mapped_iopad) { - continue; - } - /* if we cannot find any mapped inpad from tech.-mapped netlist, give a default */ - fprintf(fp, "V%s%s[%d] %s%s[%d] 0 ", - gio_inout_prefix, - iopad_spice_model->prefix, iopad_idx, - gio_inout_prefix, - iopad_spice_model->prefix, iopad_idx); - switch (default_signal_init_value) { - case 0: - fprintf(fp, "0\n"); - break; - case 1: - fprintf(fp, "vsp\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid default_signal_init_value (=%d)!\n", - __FILE__, __LINE__, default_signal_init_value); - exit(1); - } - } - - /* Give the floating ports a GND */ - /* I found there is no difference in performance if we do not fix these floating ports */ - /* fprint_grid_float_port_stimulation(fp); */ - - return; -} - -static -void fprint_measure_vdds_cbs(FILE* fp, - enum e_measure_type meas_type, - int num_clock_cycle, - boolean leakage_only) { - int ix, iy, prev_ix, prev_iy; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - switch (meas_type) { - case SPICE_MEASURE_LEAKAGE_POWER: - /* Leakage power of CBs*/ - fprintf(fp, "***** Measure Leakage Power for Connection Boxes(CBs) *****\n"); - /* cbx */ - /* X - channels [1...nx][0..ny]*/ - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - if (TRUE == leakage_only) { - fprintf(fp, ".measure tran leakage_power_cbx[%d][%d] find p(Vgvdd_cbx[%d][%d]) at=0\n", - ix, iy, ix, iy); - } else { - fprintf(fp, ".measure tran leakage_power_cbx[%d][%d] avg p(Vgvdd_cbx[%d][%d]) from=0 to='clock_period'\n", - ix, iy, ix, iy); - } - } - } - /* cby */ - /* Y - channels [1...ny][0..nx]*/ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - if (TRUE == leakage_only) { - fprintf(fp, ".measure tran leakage_power_cby[%d][%d] find p(Vgvdd_cby[%d][%d]) at=0\n", - ix, iy, ix, iy); - } else { - fprintf(fp, ".measure tran leakage_power_cby[%d][%d] avg p(Vgvdd_cby[%d][%d]) from=0 to='clock_period'\n", - ix, iy, ix, iy); - } - } - } - /* Measure Total Leakage Power of CBs */ - fprintf(fp, "***** Measure Total Leakage Power for Connection Boxes(CBs) *****\n"); - /* X - channels [1...nx][0..ny]*/ - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - fprintf(fp, ".measure tran leakage_power_cbx[1to%d][0to%d] \n", ix, iy); - if ((1 == ix)&&(0 == iy)) { - fprintf(fp, "+ param='leakage_power_cbx[%d][%d]'\n", ix, iy); - } else { - fprintf(fp, "+ param='leakage_power_cbx[%d][%d]+leakage_power_cbx[1to%d][0to%d]'\n", - ix, iy, prev_ix, prev_iy); - } - prev_ix = ix; - prev_iy = iy; - } - } - /* Y - channels [1...ny][0..nx]*/ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - fprintf(fp, ".measure tran leakage_power_cby[0to%d][1to%d] \n", ix, iy); - if ((0 == ix)&&(1 == iy)) { - fprintf(fp, "+ param='leakage_power_cby[%d][%d]'\n", ix, iy); - } else { - fprintf(fp, "+ param='leakage_power_cby[%d][%d]+leakage_power_cby[0to%d][1to%d]'\n", - ix, iy, prev_ix, prev_iy); - } - prev_ix = ix; - prev_iy = iy; - } - } - /* Sum up the leakage power of cbx and cby*/ - fprintf(fp, ".measure tran leakage_power_cbs \n"); - fprintf(fp, "+ param='leakage_power_cbx[1to%d][0to%d]+leakage_power_cby[0to%d][1to%d]' \n", - nx, ny, nx, ny); - break; - case SPICE_MEASURE_DYNAMIC_POWER: - /* Dynamic power of CBs */ - fprintf(fp, "***** Measure Dynamic Power for Connection Boxes(CBs) *****\n"); - /* cbx */ - /* X - channels [1...nx][0..ny]*/ - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - fprintf(fp, ".measure tran dynamic_power_cbx[%d][%d] avg p(Vgvdd_cbx[%d][%d]) from='clock_period' to='%d*clock_period'\n", - ix, iy, ix, iy, num_clock_cycle); - } - } - /* cby */ - /* Y - channels [1...ny][0..nx]*/ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - fprintf(fp, ".measure tran dynamic_power_cby[%d][%d] avg p(Vgvdd_cby[%d][%d]) from='clock_period' to='%d*clock_period'\n", - ix, iy, ix, iy, num_clock_cycle); - } - } - /* Measure Dynamic Power of CBs */ - fprintf(fp, "***** Measure Total Dynamic Power for Connection Boxes(CBs) *****\n"); - /* X - channels [1...nx][0..ny]*/ - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - fprintf(fp, ".measure tran dynamic_power_cbx[1to%d][0to%d] \n", ix, iy); - if ((1 == ix)&&(0 == iy)) { - fprintf(fp, "+ param='dynamic_power_cbx[%d][%d]'\n", ix, iy); - } else { - fprintf(fp, "+ param='dynamic_power_cbx[%d][%d]+dynamic_power_cbx[1to%d][0to%d]'\n", - ix, iy, prev_ix, prev_iy); - } - prev_ix = ix; - prev_iy = iy; - } - } - /* Y - channels [1...ny][0..nx]*/ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - fprintf(fp, ".measure tran dynamic_power_cby[0to%d][1to%d] \n", ix, iy); - if ((0 == ix)&&(1 == iy)) { - fprintf(fp, "+ param='dynamic_power_cby[%d][%d]'\n", ix, iy); - } else { - fprintf(fp, "+ param='dynamic_power_cby[%d][%d]+dynamic_power_cby[0to%d][1to%d]'\n", - ix, iy, prev_ix, prev_iy); - } - prev_ix = ix; - prev_iy = iy; - } - } - /* Sum up the dynamic power of cbx and cby*/ - fprintf(fp, ".measure tran dynamic_power_cbs \n"); - fprintf(fp, "+ param='dynamic_power_cbx[1to%d][0to%d]+dynamic_power_cby[0to%d][1to%d]' \n", - nx, ny, nx, ny); - fprintf(fp, ".measure tran energy_per_cycle_cbs \n "); - fprintf(fp, "+ param='dynamic_power_cbs*clock_period'\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,[LINE%d])Invalid Measure Type! Should be [SPICE_MEASURE_LEAKGE_POWER|SPICE_MEASURE_DYNAMIC_POWER]\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -static -void fprint_measure_vdds_sbs(FILE* fp, - enum e_measure_type meas_type, - int num_clock_cycle, - boolean leakage_only) { - int ix, iy, prev_ix, prev_iy; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - switch (meas_type) { - case SPICE_MEASURE_LEAKAGE_POWER: - /* Leakage power of SBs*/ - fprintf(fp, "***** Measure Leakage Power for Switch Boxes(SBs) *****\n"); - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 0; iy < (ny + 1); iy++) { - if (TRUE == leakage_only) { - fprintf(fp, ".measure tran leakage_power_sb[%d][%d] find p(Vgvdd_sb[%d][%d]) at=0\n", - ix, iy, ix, iy); - } else { - fprintf(fp, ".measure tran leakage_power_sb[%d][%d] avg p(Vgvdd_sb[%d][%d]) from=0 to='clock_period'\n", - ix, iy, ix, iy); - } - } - } - /* Measure Total Leakage Power of SBs */ - fprintf(fp, "***** Measure Total Leakage Power for Switch Boxes(SBs) *****\n"); - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 0; iy < (ny + 1); iy++) { - fprintf(fp, ".measure tran leakage_power_sb[0to%d][0to%d] \n", ix, iy); - if ((0 == ix)&&(0 == iy)) { - fprintf(fp, "+ param='leakage_power_sb[%d][%d]'\n", ix, iy); - } else { - fprintf(fp, "+ param='leakage_power_sb[%d][%d]+leakage_power_sb[0to%d][0to%d]'\n", - ix, iy, prev_ix, prev_iy); - } - prev_ix = ix; - prev_iy = iy; - } - } - /* Sum up the leakage power of sbs*/ - fprintf(fp, ".measure tran leakage_power_sbs \n"); - fprintf(fp, "+ param='leakage_power_sb[0to%d][0to%d]' \n", - nx, ny); - break; - case SPICE_MEASURE_DYNAMIC_POWER: - /* Dynamic power of SBs */ - fprintf(fp, "***** Measure Dynamic Power for Switch Boxes(SBs) *****\n"); - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 0; iy < (ny + 1); iy++) { - fprintf(fp, ".measure tran dynamic_power_sb[%d][%d] avg p(Vgvdd_sb[%d][%d]) from='clock_period' to='%d*clock_period'\n", - ix, iy, ix, iy, num_clock_cycle); - } - } - /* Measure Total Dynamic Power of SBs */ - fprintf(fp, "***** Measure Total Dynamic Power for Switch Boxes(SBs) *****\n"); - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 0; iy < (ny + 1); iy++) { - fprintf(fp, ".measure tran dynamic_power_sb[0to%d][0to%d] \n", ix, iy); - if ((0 == ix)&&(0 == iy)) { - fprintf(fp, "+ param='dynamic_power_sb[%d][%d]'\n", ix, iy); - } else { - fprintf(fp, "+ param='dynamic_power_sb[%d][%d]+dynamic_power_sb[0to%d][0to%d]'\n", - ix, iy, prev_ix, prev_iy); - } - prev_ix = ix; - prev_iy = iy; - } - } - /* Sum up the dynamic power of sbs*/ - fprintf(fp, ".measure tran dynamic_power_sbs \n"); - fprintf(fp, "+ param='dynamic_power_sb[0to%d][0to%d]' \n", - nx, ny); - fprintf(fp, ".measure tran energy_per_cycle_sbs \n "); - fprintf(fp, "+ param='dynamic_power_sbs*clock_period'\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,[LINE%d])Invalid Measure Type! Should be [SPICE_MEASURE_LEAKGE_POWER|SPICE_MEASURE_DYNAMIC_POWER]\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - -static -void fprint_top_netlist_measurements(FILE* fp, - t_spice spice, - boolean leakage_only) { - /* First cycle reserved for measuring leakage */ - int num_clock_cycle = spice.spice_params.meas_params.sim_num_clock_cycle + 1; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - fprint_spice_netlist_transient_setting(fp, spice, num_clock_cycle, leakage_only); - fprint_spice_netlist_generic_measurements(fp, spice.spice_params.mc_params, spice.num_spice_model, spice.spice_models); - - /* TODO: Measure the delay of each mapped net and logical block */ - - /* Measure the power */ - /* Leakage ( the first cycle is reserved for leakage measurement) */ - if (TRUE == leakage_only) { - /* Leakage power of SRAMs */ - fprintf(fp, ".measure tran leakage_power_sram_local_routing find p(Vgvdd_sram_local_routing) at=0\n"); - fprintf(fp, ".measure tran leakage_power_sram_luts find p(Vgvdd_sram_luts) at=0\n"); - fprintf(fp, ".measure tran leakage_power_sram_cbs find p(Vgvdd_sram_cbs) at=0\n"); - fprintf(fp, ".measure tran leakage_power_sram_sbs find p(Vgvdd_sram_sbs) at=0\n"); - /* Leakage power of I/O Pads */ - fprintf(fp, ".measure tran leakage_power_io find p(Vgvdd_io) at=0\n"); - /* Global power of Local Interconnections*/ - fprintf(fp, ".measure tran leakage_power_local_interc find p(Vgvdd_local_interc) at=0\n"); - /* Global power of CLB to CLB direct connections*/ - fprintf(fp, ".measure tran leakage_power_direct_interc find p(Vgvdd_direct_interc) at=0\n"); - } else { - /* Leakage power of SRAMs */ - fprintf(fp, ".measure tran leakage_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from=0 to='clock_period'\n"); - fprintf(fp, ".measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period'\n"); - fprintf(fp, ".measure tran leakage_power_sram_cbs avg p(Vgvdd_sram_cbs) from=0 to='clock_period'\n"); - fprintf(fp, ".measure tran leakage_power_sram_sbs avg p(Vgvdd_sram_sbs) from=0 to='clock_period'\n"); - /* Leakage power of I/O Pads */ - fprintf(fp, ".measure tran leakage_power_io avg p(Vgvdd_io) from=0 to='clock_period'\n"); - /* Global power of Local Interconnections*/ - fprintf(fp, ".measure tran leakage_power_local_interc avg p(Vgvdd_local_interc) from=0 to='clock_period'\n"); - /* Global power of CLB to CLB Direct Interconnections*/ - fprintf(fp, ".measure tran leakage_power_direct_interc avg p(Vgvdd_direct_interc) from=0 to='clock_period'\n"); - } - /* Leakge power of Hard logic */ - fprint_measure_vdds_spice_model(fp, SPICE_MODEL_HARDLOGIC, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); - /* Leakage power of LUTs*/ - fprint_measure_vdds_spice_model(fp, SPICE_MODEL_LUT, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); - /* Leakage power of FFs*/ - fprint_measure_vdds_spice_model(fp, SPICE_MODEL_FF, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); - /* Leakage power of IOPADs */ - fprint_measure_vdds_spice_model(fp, SPICE_MODEL_IOPAD, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, spice, leakage_only); - /* Leakage power of CBs */ - fprint_measure_vdds_cbs(fp, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, leakage_only); - /* Leakage power of SBs */ - fprint_measure_vdds_sbs(fp, SPICE_MEASURE_LEAKAGE_POWER, num_clock_cycle, leakage_only); - - if (TRUE == leakage_only) { - return; - } - - /* Dynamic power */ - /* Dynamic power of SRAMs */ - fprintf(fp, ".measure tran dynamic_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); - fprintf(fp, ".measure tran energy_per_cycle_sram_local_routing \n "); - fprintf(fp, "+ param='dynamic_power_sram_local_routing*clock_period'\n"); - fprintf(fp, ".measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); - fprintf(fp, ".measure tran energy_per_cycle_sram_luts \n "); - fprintf(fp, "+ param='dynamic_power_sram_luts*clock_period'\n"); - fprintf(fp, ".measure tran dynamic_power_sram_cbs avg p(Vgvdd_sram_cbs) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); - fprintf(fp, ".measure tran energy_per_cycle_sram_cbs \n "); - fprintf(fp, "+ param='dynamic_power_sram_cbs*clock_period'\n"); - fprintf(fp, ".measure tran dynamic_power_sram_sbs avg p(Vgvdd_sram_sbs) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); - fprintf(fp, ".measure tran energy_per_cycle_sram_sbs \n "); - fprintf(fp, "+ param='dynamic_power_sram_sbs*clock_period'\n"); - /* Dynamic power of I/O pads */ - fprint_measure_vdds_spice_model(fp, SPICE_MODEL_IOPAD, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); - /* Dynamic power of Local Interconnections */ - fprintf(fp, ".measure tran dynamic_power_local_interc avg p(Vgvdd_local_interc) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); - fprintf(fp, ".measure tran energy_per_cycle_local_routing \n "); - fprintf(fp, "+ param='dynamic_power_local_interc*clock_period'\n"); - /* Dynamic power of Direct connection */ - fprintf(fp, ".measure tran dynamic_power_direct_interc avg p(Vgvdd_direct_interc) from='clock_period' to='%d*clock_period'\n", num_clock_cycle); - fprintf(fp, ".measure tran energy_per_cycle_direct_interc \n "); - fprintf(fp, "+ param='dynamic_power_direct_interc*clock_period'\n"); - /* Dynamic power of Hard Logic */ - fprint_measure_vdds_spice_model(fp, SPICE_MODEL_HARDLOGIC, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); - /* Dynamic power of LUTs */ - fprint_measure_vdds_spice_model(fp, SPICE_MODEL_LUT, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); - /* Dynamic power of FFs */ - fprint_measure_vdds_spice_model(fp, SPICE_MODEL_FF, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, spice, leakage_only); - /* Dynamic power of CBs */ - fprint_measure_vdds_cbs(fp, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, leakage_only); - /* Dynamic power of SBs */ - fprint_measure_vdds_sbs(fp, SPICE_MEASURE_DYNAMIC_POWER, num_clock_cycle, leakage_only); - - return; -} - -/***** Print Top-level SPICE netlist *****/ -void spice_print_top_netlist(char* circuit_name, - char* top_netlist_name, - char* include_dir_path, - char* subckt_dir_path, - int LL_num_rr_nodes, - t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - int num_clock, - t_spice spice, - boolean leakage_only) { - FILE* fp = NULL; - char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); - char* temp_include_file_path = NULL; - char* title = my_strcat("FPGA SPICE Netlist for Design: ", circuit_name); - - /* Check if the path exists*/ - fp = fopen(top_netlist_name,"w"); - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Failure in create top SPICE netlist %s!",__FILE__, __LINE__, top_netlist_name); - exit(1); - } - - vpr_printf(TIO_MESSAGE_INFO, "Writing Top-level FPGA Netlist for %s...\n", circuit_name); - - /* Print the title */ - fprint_spice_head(fp, title); - my_free(title); - - /* print technology library and design parameters*/ - /* fprint_tech_lib(fp, spice.tech_lib); */ - - /* Include parameter header files */ - fprint_spice_include_param_headers(fp, include_dir_path); - - /* Include Key subckts */ - fprint_spice_include_key_subckts(fp, subckt_dir_path); - - /* Include user-defined sub-circuit netlist */ - init_include_user_defined_netlists(spice); - fprint_include_user_defined_netlists(fp, spice); - - /* Special subckts for Top-level SPICE netlist */ - fprintf(fp, "****** Include subckt netlists: Look-Up Tables (LUTs) *****\n"); - temp_include_file_path = my_strcat(formatted_subckt_dir_path, luts_spice_file_name); - fprintf(fp, ".include \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - - fprintf(fp, "****** Include subckt netlists: Logic Blocks *****\n"); - temp_include_file_path = my_strcat(formatted_subckt_dir_path, logic_block_spice_file_name); - fprintf(fp, ".include \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - - fprintf(fp, "****** Include subckt netlists: Routing structures (Switch Boxes, Channels, Connection Boxes) *****\n"); - temp_include_file_path = my_strcat(formatted_subckt_dir_path, routing_spice_file_name); - fprintf(fp, ".include \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - - /* Print all global wires*/ - fprint_top_netlist_global_ports(fp, num_clock, spice); - - /* Print simulation temperature and other options for SPICE */ - fprint_spice_options(fp, spice.spice_params); - - /* Quote defined Logic blocks subckts (Grids) */ - fprint_call_defined_grids(fp); - fprint_stimulate_dangling_grid_pins(fp); - - /* Quote Routing structures: Channels */ - fprint_call_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - - /* Quote Routing structures: Conneciton Boxes */ - fprint_call_defined_connection_boxes(fp); - - /* Quote Routing structures: Switch Boxes */ - fprint_call_defined_switch_boxes(fp); - - /* Apply CLB to CLB direct connections */ - fprint_spice_clb2clb_directs(fp, num_clb2clb_directs, clb2clb_direct); - - /* Add stimulations */ - fprint_top_netlist_stimulations(fp, num_clock, spice); - - /* Add measurements */ - fprint_top_netlist_measurements(fp, spice, leakage_only); - - /* SPICE ends*/ - fprintf(fp, ".end\n"); - - /* Close the file*/ - fclose(fp); - - /* Push the testbench to the linked list */ - tb_head = add_one_spice_tb_info_to_llist(tb_head, top_netlist_name, - spice.spice_params.meas_params.sim_num_clock_cycle + 1); - - /* Free */ - //my_free(title); - //my_free(formatted_subckt_dir_path); - - return; -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_top_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_top_netlist.h deleted file mode 100644 index ed6357d2f..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_top_netlist.h +++ /dev/null @@ -1,10 +0,0 @@ -void spice_print_top_netlist(char* circuit_name, - char* top_netlist_name, - char* include_dir_path, - char* subckt_dir_path, - int LL_num_rr_nodes, - t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - int num_clock, - t_spice spice, - boolean leakage_only); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c deleted file mode 100644 index a75da71a7..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c +++ /dev/null @@ -1,3586 +0,0 @@ -/***********************************/ -/* SPICE Modeling for VPR */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Include vpr structs*/ -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "vpr_utils.h" -#include "route_common.h" - -/* Include spice support headers*/ -#include "linkedlist.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_globals.h" -#include "spice_globals.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "spice_mux.h" -#include "spice_pbtypes.h" -#include "spice_routing.h" -#include "fpga_x2p_backannotate_utils.h" -#include "spice_utils.h" - -/***** Subroutines *****/ -void fprint_spice_head(FILE* fp, - char* usage) { - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n",__FILE__,__LINE__); - exit(1); - } - fprintf(fp,"*****************************\n"); - fprintf(fp,"* FPGA SPICE Netlist *\n"); - fprintf(fp,"* Description: %s *\n",usage); - fprintf(fp,"* Author: Xifan TANG *\n"); - fprintf(fp,"* Organization: EPFL/IC/LSI *\n"); - fprintf(fp,"* Date: %s *\n",my_gettime()); - fprintf(fp,"*****************************\n"); - return; -} - -/* Create a file handler for a subckt SPICE netlist */ -FILE* spice_create_one_subckt_file(char* subckt_dir, - char* subckt_name_prefix, - char* spice_subckt_file_name_prefix, - int grid_x, int grid_y, - char** sp_name) { - FILE* fp = NULL; - char* file_description = NULL; - (*sp_name) = my_strcat(subckt_dir, - fpga_spice_create_one_subckt_filename(spice_subckt_file_name_prefix, grid_x, grid_y, spice_netlist_file_postfix)); - - /* Create a file*/ - fp = fopen((*sp_name), "w"); - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create subckt SPICE netlist %s", - __FILE__, __LINE__, (*sp_name)); - exit(1); - } - - /* Generate the descriptions*/ - file_description = (char*) my_malloc(sizeof(char) * (strlen(subckt_name_prefix) + 2 - + strlen(my_itoa(grid_x)) + 2 + strlen(my_itoa(grid_y)) - + 9)); - sprintf(file_description, "%s [%d][%d] in FPGA", - subckt_name_prefix, grid_x, grid_y); - fprint_spice_head(fp, file_description); - - /* Free */ - my_free(file_description); - - return fp; -} - -/* Include a subckt in SPICE netlist */ -void spice_print_one_include_subckt_line(FILE* fp, - char* subckt_dir, - char* subckt_file_name) { - char* temp_include_file_path = NULL; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Invalid File Handler of subckt SPICE netlist %s", - __FILE__, __LINE__); - exit(1); - } - - temp_include_file_path = my_strcat(subckt_dir, subckt_file_name); - fprintf(fp, ".include \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - - return; -} - -/* Output all the created subckt file names in a header file, - * that can be easily imported in a top-level netlist - */ -void spice_print_subckt_header_file(t_llist* subckt_llist_head, - char* subckt_dir, - char* header_file_name) { - FILE* fp = NULL; - char* spice_fname = NULL; - t_llist* temp = NULL; - - spice_fname = my_strcat(subckt_dir, - header_file_name); - - /* Create a file*/ - fp = fopen(spice_fname, "w"); - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d])Failure in create SPICE netlist %s", - __FILE__, __LINE__, spice_fname); - exit(1); - } - - /* Generate the descriptions*/ - fprint_spice_head(fp, "Header file"); - - /* Output file names */ - temp = subckt_llist_head; - while (temp) { - fprintf(fp, ".include \'%s\'\n", - (char*)(temp->dptr)); - temp = temp->next; - } - - /* Close fp */ - fclose(fp); - - /* Free */ - my_free(spice_fname); - - return; -} - - -/* Print all the global ports that are stored in the linked list - * Return the number of ports that have been dumped - */ -int rec_fprint_spice_model_global_ports(FILE* fp, - t_spice_model* cur_spice_model, - boolean recursive) { - int i, iport, dumped_port_cnt, rec_dumped_port_cnt; - - dumped_port_cnt = 0; - rec_dumped_port_cnt = 0; - - /* Check */ - assert(NULL != cur_spice_model); - if (0 < cur_spice_model->num_port) { - assert(NULL != cur_spice_model->ports); - } - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - } - - for (iport = 0; iport < cur_spice_model->num_port; iport++) { - /* if this spice model requires customized netlist to be included, we do not go recursively */ - if (TRUE == recursive) { - /* GO recursively first, and meanwhile count the number of global ports */ - /* For the port that requires another spice_model, i.e., SRAM - * We need include any global port in that spice model - */ - if (NULL != cur_spice_model->ports[iport].spice_model) { - /* Check if we need to dump a comma */ - rec_dumped_port_cnt += - rec_fprint_spice_model_global_ports(fp, cur_spice_model->ports[iport].spice_model, - recursive); - /* Update counter */ - dumped_port_cnt += rec_dumped_port_cnt; - continue; - } - } - /* By pass non-global ports*/ - if (FALSE == cur_spice_model->ports[iport].is_global) { - continue; - } - /* We have some port to dump ! - * Print a comment line - */ - if (0 == dumped_port_cnt) { - fprintf(fp, "\n"); - fprintf(fp, "***** BEGIN Global ports of SPICE_MODEL(%s) *****\n", - cur_spice_model->name); - fprintf(fp, "+ "); - } - /* Check if we need to dump a comma */ - for (i = 0; i < cur_spice_model->ports[iport].size; i++) { - fprintf(fp, " %s[%d] ", - cur_spice_model->ports[iport].prefix, - i); - } - /* Update counter */ - dumped_port_cnt++; - } - - /* We have dumped some port! - * Print another comment line - */ - if (0 < dumped_port_cnt) { - fprintf(fp, "\n"); - fprintf(fp, "***** END Global ports of SPICE_MODEL(%s) *****\n", - cur_spice_model->name); - } - - return dumped_port_cnt; -} - -/* Print all the global ports that are stored in the linked list */ -int fprint_spice_global_ports(FILE* fp, t_llist* head) { - t_llist* temp = head; - t_spice_model_port* cur_global_port = NULL; - int dumped_port_cnt = 0; - int i; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - } - - fprintf(fp, "\n"); - fprintf(fp, "***** BEGIN Global ports *****\n"); - fprintf(fp, "+ "); - while(NULL != temp) { - cur_global_port = (t_spice_model_port*)(temp->dptr); - for (i = 0; i < cur_global_port->size; i++) { - fprintf(fp, " %s[%d] ", - cur_global_port->prefix, - i); - } - /* Update counter */ - dumped_port_cnt++; - /* Go to the next */ - temp = temp->next; - } - fprintf(fp, "\n"); - fprintf(fp, "***** END Global ports *****\n"); - - return dumped_port_cnt; -} - -void fprint_spice_generic_testbench_global_ports(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - t_llist* head) { - t_spice_model* mem_model = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - } - - fprintf(fp, "***** Generic global ports ***** \n"); - fprintf(fp, "***** VDD, GND ***** \n"); - fprintf(fp, ".global %s\n", - spice_tb_global_vdd_port_name); - fprintf(fp, ".global %s\n", - spice_tb_global_gnd_port_name); - fprintf(fp, "***** Global set ports ***** \n"); - fprintf(fp, ".global %s %s%s \n", - spice_tb_global_set_port_name, - spice_tb_global_set_port_name, - spice_tb_global_port_inv_postfix); - fprintf(fp, "***** Global reset ports ***** \n"); - fprintf(fp, ".global %s %s%s\n", - spice_tb_global_reset_port_name, - spice_tb_global_reset_port_name, - spice_tb_global_port_inv_postfix); - fprintf(fp, "***** Configuration done ports ***** \n"); - fprintf(fp, ".global %s %s%s\n", - spice_tb_global_config_done_port_name, - spice_tb_global_config_done_port_name, - spice_tb_global_port_inv_postfix); - - /* Get memory spice model */ - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); - fprintf(fp, "***** Global SRAM input ***** \n"); - fprintf(fp, ".global %s->in\n", mem_model->prefix); - - /* Print scan-chain global ports */ - if (SPICE_SRAM_SCAN_CHAIN == sram_spice_orgz_type) { - fprintf(fp, "***** Scan-chain FF: head of scan-chain *****\n"); - fprintf(fp, "*.global %s[0]->in\n", sram_spice_model->prefix); - } - - /* Define a global clock port if we need one*/ - fprintf(fp, "***** Global Clock Signals *****\n"); - fprintf(fp, ".global %s\n", - spice_tb_global_clock_port_name); - fprintf(fp, ".global %s%s\n", - spice_tb_global_clock_port_name, - spice_tb_global_port_inv_postfix); - - fprintf(fp, "***** User-defined global ports ****** \n"); - if (NULL != head) { - fprintf(fp, ".global \n"); - } - fprint_spice_global_ports(fp, head); - - return; -} - -/* Print a SRAM output port in SPICE format */ -void fprint_spice_sram_one_outport(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - int cur_sram, - int port_type_index) { - t_spice_model* mem_model = NULL; - char* port_name = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Get memory_model */ - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); - - /* Keep the branch as it is, in case thing may become more complicated*/ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - if (0 == port_type_index) { - port_name = "out"; - } else { - assert(1 == port_type_index); - port_name = "outb"; - } - break; - case SPICE_SRAM_SCAN_CHAIN: - if (0 == port_type_index) { - port_name = "ccff_out"; - } else { - assert(1 == port_type_index); - port_name = "ccff_outb"; - } - break; - case SPICE_SRAM_MEMORY_BANK: - if (0 == port_type_index) { - port_name = "out"; - } else { - assert(1 == port_type_index); - port_name = "outb"; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization !\n", - __FILE__, __LINE__); - exit(1); - } - - /*Malloc and generate the full name of port */ - fprintf(fp, "%s[%d]->%s ", - mem_model->prefix, cur_sram, port_name); /* Outputs */ - - /* Free */ - /* Local variables such as port1_name and port2 name are automatically freed */ - - return; -} - -/* Print a SRAM module in SPICE format */ -void fprint_spice_one_specific_sram_subckt(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - t_spice_model* parent_spice_model, - char* vdd_port_name, - int sram_index) { - t_spice_model* mem_model = NULL; - int cur_sram = 0; - - /* Get memory model */ - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); - - /* Get current index of SRAM module */ - cur_sram = sram_index; - - /* Depend on the type of SRAM organization */ - switch (cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - case SPICE_SRAM_MEMORY_BANK: - fprintf(fp, "X%s[%d] ", mem_model->prefix, cur_sram); /* SRAM subckts*/ - /* fprintf(fp, "%s[%d]->in ", sram_spice_model->prefix, cur_sram);*/ /* Input*/ - /* Global ports : - * Only dump the global ports belonging to a spice_model - * Do not go recursive, we can freely define global ports anywhere in SPICE netlist - */ - rec_fprint_spice_model_global_ports(fp, mem_model, FALSE); - /* Local ports */ - fprintf(fp, "%s->in ", mem_model->prefix); /* Input*/ - fprintf(fp, "%s[%d]->out %s[%d]->outb ", - mem_model->prefix, cur_sram, mem_model->prefix, cur_sram); /* Outputs */ - fprintf(fp, "%s sgnd ", - vdd_port_name); // - fprintf(fp, " %s\n", mem_model->name); // - /* Add nodeset to help convergence */ - fprintf(fp, ".nodeset V(%s[%d]->out) 0\n", mem_model->prefix, cur_sram); - fprintf(fp, ".nodeset V(%s[%d]->outb) vsp\n", mem_model->prefix, cur_sram); - break; - case SPICE_SRAM_SCAN_CHAIN: - fprintf(fp, "X%s[%d] ", mem_model->prefix, cur_sram); /* SRAM subckts*/ - /* Global ports : - * Only dump the global ports belonging to a spice_model - * Do not go recursive, we can freely define global ports anywhere in SPICE netlist - */ - rec_fprint_spice_model_global_ports(fp, mem_model, FALSE); - /* Local ports */ - fprintf(fp, "%s[%d]->in ", mem_model->prefix, cur_sram); /* Input*/ - fprintf(fp, "%s[%d]->out %s[%d]->outb ", - mem_model->prefix, cur_sram, mem_model->prefix, cur_sram); /* Outputs */ - fprintf(fp, "sc_clk sc_rst sc_set \n"); // - fprintf(fp, "%s sgnd ", - vdd_port_name); // - fprintf(fp, " %s\n", mem_model->name); // - /* Add nodeset to help convergence */ - fprintf(fp, ".nodeset V(%s[%d]->out) 0\n", mem_model->prefix, cur_sram); - fprintf(fp, ".nodeset V(%s[%d]->outb) vsp\n", mem_model->prefix, cur_sram); - /* Connect to the tail of previous Scan-chain FF*/ - fprintf(fp,"R%s[%d]_short %s[%d]->out %s[%d]->in 0\n", - mem_model->prefix, cur_sram, - mem_model->prefix, cur_sram, - sram_spice_model->prefix, cur_sram + 1); - /* Specify this is a global signal*/ - fprintf(fp, ".global %s[%d]->in\n", sram_spice_model->prefix, cur_sram); - /* Specify the head and tail of the scan-chain of this LUT */ - fprintf(fp,"R%s[%d]_sc_head %s[%d]_sc_head %s[%d]->in 0\n", - mem_model->prefix, mem_model->cnt, - mem_model->prefix, mem_model->cnt, - mem_model->prefix, mem_model->cnt); - fprintf(fp,"R%s[%d]_sc_tail %s[%d]_sc_tail %s[%d]->in 0\n", - mem_model->prefix, mem_model->cnt, - mem_model->prefix, mem_model->cnt, - mem_model->prefix, cur_sram); - fprintf(fp,".global %s[%d]_sc_head %s[%d]_sc_tail\n", - mem_model->prefix, mem_model->cnt, - mem_model->prefix, mem_model->cnt); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Invalid SRAM organization type!\n", - __FILE__, __LINE__); - exit(1); - } - - return; -} - - -/* Print a SRAM module in SPICE format */ -void fprint_spice_one_sram_subckt(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - t_spice_model* parent_spice_model, - char* vdd_port_name) { - t_spice_model* mem_model = NULL; - int cur_num_sram = 0; - - /* Get memory model */ - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); - - /* Get current index of SRAM module */ - cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - - /* Call a subroutine: fprint_spice_one_specific_sram_subckt */ - fprint_spice_one_specific_sram_subckt(fp, cur_sram_orgz_info, - parent_spice_model, - vdd_port_name, cur_num_sram); - - /* Update the memory counter in sram_orgz_info */ - update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, - cur_num_sram + 1); - /* Update the memory counter */ - mem_model->cnt++; - - return; -} - -/* Include user defined SPICE netlists */ -void init_include_user_defined_netlists(t_spice spice) { - int i; - - /* Include user-defined sub-circuit netlist */ - for (i = 0; i < spice.num_include_netlist; i++) { - spice.include_netlists[i].included = 0; - } - - return; -} - -void fprint_include_user_defined_netlists(FILE* fp, - t_spice spice) { - int i; - - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Include user-defined sub-circuit netlist */ - for (i = 0; i < spice.num_include_netlist; i++) { - if (0 == spice.include_netlists[i].included) { - assert(NULL != spice.include_netlists[i].path); - fprintf(fp, ".include \'%s\'\n", spice.include_netlists[i].path); - spice.include_netlists[i].included = 1; - } else { - assert(1 == spice.include_netlists[i].included); - } - } - - return; -} - -void fprint_splited_vdds_spice_model(FILE* fp, - enum e_spice_model_type spice_model_type, - t_spice spice) { - int imodel, i; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - for (imodel = 0; imodel < spice.num_spice_model; imodel++) { - if (spice_model_type == spice.spice_models[imodel].type) { - for (i = 0; i < spice.spice_models[imodel].cnt; i++) { - fprintf(fp, "V%s_%s[%d] %s_%s[%d] 0 vsp\n", - spice_tb_global_vdd_port_name, - spice.spice_models[imodel].prefix, i, - spice_tb_global_vdd_port_name, - spice.spice_models[imodel].prefix, i); - /* For some gvdd maybe floating, I add a huge resistance to make their leakage power trival - * which does no change to the delay result. - * The resistance value is co-related to the vsp, which produces a trival leakage current (1e-15). - */ - fprintf(fp, "Rgvdd_%s[%d]_huge gvdd_%s[%d] 0 'vsp/10e-15'\n", - spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); - } - } - } - - return; -} - -void fprint_grid_splited_vdds_spice_model(FILE* fp, int grid_x, int grid_y, - enum e_spice_model_type spice_model_type, - t_spice spice) { - int imodel, i; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - for (imodel = 0; imodel < spice.num_spice_model; imodel++) { - if (spice_model_type == spice.spice_models[imodel].type) { - /* Bypass zero-usage spice_model in this grid*/ - if (spice.spice_models[imodel].grid_index_low[grid_x][grid_y] - == spice.spice_models[imodel].grid_index_high[grid_x][grid_y]) { - continue; - } - for (i = spice.spice_models[imodel].grid_index_low[grid_x][grid_y]; - i < spice.spice_models[imodel].grid_index_high[grid_x][grid_y]; - i++) { - fprintf(fp, "Vgvdd_%s[%d] gvdd_%s[%d] 0 vsp\n", - spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); - /* For some gvdd maybe floating, I add a huge resistance to make their leakage power trival - * which does no change to the delay result. - * The resistance value is co-related to the vsp, which produces a trival leakage current (1e-15). - */ - fprintf(fp, "Rgvdd_%s[%d]_huge gvdd_%s[%d] 0 'vsp/10e-15'\n", - spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); - } - } - } - - return; -} - -void fprint_global_vdds_spice_model(FILE* fp, - enum e_spice_model_type spice_model_type, - t_spice spice) { - int imodel, i; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "***** Global VDD ports of %s *****\n", generate_string_spice_model_type(spice_model_type)); - fprintf(fp, ".global \n"); - - for (imodel = 0; imodel < spice.num_spice_model; imodel++) { - if (spice_model_type == spice.spice_models[imodel].type) { - for (i = 0; i < spice.spice_models[imodel].cnt; i++) { - fprintf(fp, "+ %s_%s[%d]\n", - spice_tb_global_vdd_port_name, - spice.spice_models[imodel].prefix, i); - } - } - } - - fprintf(fp, "\n"); - - return; -} - -void fprint_grid_global_vdds_spice_model(FILE* fp, int x, int y, - enum e_spice_model_type spice_model_type, - t_spice spice) { - int imodel, i; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "***** Global VDD ports of %s *****\n", generate_string_spice_model_type(spice_model_type)); - - for (imodel = 0; imodel < spice.num_spice_model; imodel++) { - /* Bypass non-matched SPICE model */ - if (spice_model_type != spice.spice_models[imodel].type) { - continue; - } - /* Bypass zero-usage spice_model in this grid*/ - if (spice.spice_models[imodel].grid_index_low[x][y] - == spice.spice_models[imodel].grid_index_high[x][y]) { - continue; - } - fprintf(fp, ".global \n"); - for (i = spice.spice_models[imodel].grid_index_low[x][y]; - i < spice.spice_models[imodel].grid_index_high[x][y]; - i++) { - fprintf(fp, "+ gvdd_%s[%d]\n", - spice.spice_models[imodel].prefix, i); - } - } - - fprintf(fp, "\n"); - - return; -} - -void fprint_global_pad_ports_spice_model(FILE* fp, - t_spice spice) { - int imodel, i; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "***** Global input/output ports of I/O Pads *****\n"); - fprintf(fp, ".global \n"); - - for (imodel = 0; imodel < spice.num_spice_model; imodel++) { - switch (spice.spice_models[imodel].type) { - /* Handle multiple INPAD/OUTPAD spice models*/ - case SPICE_MODEL_IOPAD: - for (i = 0; i < spice.spice_models[imodel].cnt; i++) { - fprintf(fp, "+ %s%s[%d]\n", gio_inout_prefix, spice.spice_models[imodel].prefix, i); - } - break; - /* SRAM inputs*/ - case SPICE_MODEL_SRAM: - /* - for (i = 0; i < spice.spice_models[imodel].cnt; i++) { - fprintf(fp, "+ %s[%d]->in\n", spice.spice_models[imodel].prefix, i); - } - fprintf(fp, "+ %s->in\n", spice.spice_models[imodel].prefix); - */ - break; - /* Other types we do not care*/ - case SPICE_MODEL_CHAN_WIRE: - case SPICE_MODEL_WIRE: - case SPICE_MODEL_MUX: - case SPICE_MODEL_LUT: - case SPICE_MODEL_FF: - case SPICE_MODEL_HARDLOGIC: - case SPICE_MODEL_CCFF: - case SPICE_MODEL_INVBUF: - case SPICE_MODEL_PASSGATE: - case SPICE_MODEL_GATE: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Unknown type for spice model!\n", - __FILE__, __LINE__); - exit(1); - } - } - - fprintf(fp, "\n"); - - return; -} - -void fprint_spice_global_vdd_switch_boxes(FILE* fp) { - int ix, iy; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "***** Global Vdds for Switch Boxes *****\n"); - fprintf(fp, ".global "); - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 0; iy < (ny + 1); iy++) { - fprintf(fp, "gvdd_sb[%d][%d] ", ix, iy); - } - } - fprintf(fp, "\n"); - - return; -} - -/* Call the sub-circuits for connection boxes */ -void fprint_spice_global_vdd_connection_boxes(FILE* fp) { - int ix, iy; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "***** Global Vdds for Connection Blocks - X channels *****\n"); - fprintf(fp, ".global "); - /* X - channels [1...nx][0..ny]*/ - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - fprintf(fp, "gvdd_cbx[%d][%d] ", ix, iy); - } - } - fprintf(fp, "\n"); - - fprintf(fp, "***** Global Vdds for Connection Blocks - Y channels *****\n"); - fprintf(fp, ".global "); - /* Y - channels [1...ny][0..nx]*/ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - fprintf(fp, "gvdd_cby[%d][%d] ", ix, iy); - } - } - fprintf(fp, "\n"); - - return; -} - -void fprint_measure_vdds_spice_model(FILE* fp, - enum e_spice_model_type spice_model_type, - enum e_measure_type meas_type, - int num_cycle, - t_spice spice, - boolean leakage_only) { - int imodel, i; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - for (imodel = 0; imodel < spice.num_spice_model; imodel++) { - /* Only care the matched SPICE model type */ - if (spice_model_type != spice.spice_models[imodel].type) { - continue; - } - /* Skip if no such spice_model is used in the netlists */ - if (0 == spice.spice_models[imodel].cnt) { - continue; - } - for (i = 0; i < spice.spice_models[imodel].cnt; i++) { - switch (meas_type) { - case SPICE_MEASURE_LEAKAGE_POWER: - if (TRUE == leakage_only) { - fprintf(fp, ".measure tran leakage_power_%s[%d] find p(Vgvdd_%s[%d]) at=0\n", - spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); - } else { - fprintf(fp, ".measure tran leakage_power_%s[%d] avg p(Vgvdd_%s[%d]) from=0 to='clock_period'\n", - spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); - } - break; - case SPICE_MEASURE_DYNAMIC_POWER: - fprintf(fp, ".measure tran dynamic_power_%s[%d] avg p(Vgvdd_%s[%d]) from='clock_period' to='%d*clock_period'\n", - spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i, num_cycle); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid meas_type!\n", __FILE__, __LINE__); - exit(1); - } - } - } - - /* Measure the total power of this kind of spice model */ - for (imodel = 0; imodel < spice.num_spice_model; imodel++) { - /* Only care the matched SPICE model type */ - if (spice_model_type != spice.spice_models[imodel].type) { - continue; - } - /* Skip if no such spice_model is used in the netlists */ - if (0 == spice.spice_models[imodel].cnt) { - continue; - } - switch (meas_type) { - case SPICE_MEASURE_LEAKAGE_POWER: - for (i = 0; i < spice.spice_models[imodel].cnt; i++) { - fprintf(fp, ".measure tran leakage_power_%s[0to%d] \n", spice.spice_models[imodel].prefix, i); - if (0 == i) { - fprintf(fp, "+ param = 'leakage_power_%s[%d]'\n", spice.spice_models[imodel].prefix, i); - } else { - fprintf(fp, "+ param = 'leakage_power_%s[%d]+leakage_power_%s[0to%d]'\n", - spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i-1); - } - } - /* Spot the total leakage power of this spice model */ - fprintf(fp, ".measure tran total_leakage_power_%s \n", spice.spice_models[imodel].prefix); - fprintf(fp, "+ param = 'leakage_power_%s[0to%d]'\n", - spice.spice_models[imodel].prefix, spice.spice_models[imodel].cnt-1); - break; - case SPICE_MEASURE_DYNAMIC_POWER: - for (i = 0; i < spice.spice_models[imodel].cnt; i++) { - fprintf(fp, ".measure tran dynamic_power_%s[0to%d] \n", spice.spice_models[imodel].prefix, i); - if (0 == i) { - fprintf(fp, "+ param = 'dynamic_power_%s[%d]'\n", spice.spice_models[imodel].prefix, i); - } else { - fprintf(fp, "+ param = 'dynamic_power_%s[%d]+dynamic_power_%s[0to%d]'\n", - spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i-1); - } - } - /* Spot the total dynamic power of this spice model */ - fprintf(fp, ".measure tran total_dynamic_power_%s \n", spice.spice_models[imodel].prefix); - fprintf(fp, "+ param = 'dynamic_power_%s[0to%d]'\n", - spice.spice_models[imodel].prefix, spice.spice_models[imodel].cnt-1); - fprintf(fp, ".measure tran total_energy_per_cycle_%s \n", spice.spice_models[imodel].prefix); - fprintf(fp, "+ param = 'dynamic_power_%s[0to%d]*clock_period'\n", - spice.spice_models[imodel].prefix, spice.spice_models[imodel].cnt-1); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid meas_type!\n", __FILE__, __LINE__); - exit(1); - } - } - - - return; -} - -void fprint_measure_grid_vdds_spice_model(FILE* fp, int grid_x, int grid_y, - enum e_spice_model_type spice_model_type, - enum e_measure_type meas_type, - int num_cycle, - t_spice spice, - boolean leakage_only) { - int imodel, i; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - for (imodel = 0; imodel < spice.num_spice_model; imodel++) { - if (spice_model_type == spice.spice_models[imodel].type) { - /* Bypass zero-usage spice_model in this grid*/ - if (spice.spice_models[imodel].grid_index_low[grid_x][grid_y] - == spice.spice_models[imodel].grid_index_high[grid_x][grid_y]) { - continue; - } - for (i = spice.spice_models[imodel].grid_index_low[grid_x][grid_y]; - i < spice.spice_models[imodel].grid_index_high[grid_x][grid_y]; - i++) { - switch (meas_type) { - case SPICE_MEASURE_LEAKAGE_POWER: - if (TRUE == leakage_only) { - fprintf(fp, ".measure tran leakage_power_%s[%d] find p(Vgvdd_%s[%d]) at=0\n", - spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); - } else { - fprintf(fp, ".measure tran leakage_power_%s[%d] avg p(Vgvdd_%s[%d]) from=0 to='clock_period'\n", - spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i); - } - break; - case SPICE_MEASURE_DYNAMIC_POWER: - fprintf(fp, ".measure tran dynamic_power_%s[%d] avg p(Vgvdd_%s[%d]) from='clock_period' to='%d*clock_period'\n", - spice.spice_models[imodel].prefix, i, spice.spice_models[imodel].prefix, i, num_cycle); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid meas_type!\n", __FILE__, __LINE__); - exit(1); - } - } - } - } - - /* Measure the total power of this kind of spice model */ - for (imodel = 0; imodel < spice.num_spice_model; imodel++) { - if (spice_model_type == spice.spice_models[imodel].type) { - switch (meas_type) { - case SPICE_MEASURE_LEAKAGE_POWER: - /* Bypass zero-usage spice_model in this grid*/ - if (spice.spice_models[imodel].grid_index_low[grid_x][grid_y] - == spice.spice_models[imodel].grid_index_high[grid_x][grid_y]) { - continue; - } - for (i = spice.spice_models[imodel].grid_index_low[grid_x][grid_y]; - i < spice.spice_models[imodel].grid_index_high[grid_x][grid_y]; - i++) { - fprintf(fp, ".measure tran leakage_power_%s[%dto%d] \n", - spice.spice_models[imodel].prefix, - spice.spice_models[imodel].grid_index_low[grid_x][grid_y], - i); - if (spice.spice_models[imodel].grid_index_low[grid_x][grid_y] == i) { - fprintf(fp, "+ param = 'leakage_power_%s[%d]'\n", spice.spice_models[imodel].prefix, i); - } else { - fprintf(fp, "+ param = 'leakage_power_%s[%d]+leakage_power_%s[%dto%d]'\n", - spice.spice_models[imodel].prefix, - i, spice.spice_models[imodel].prefix, - spice.spice_models[imodel].grid_index_low[grid_x][grid_y], - i-1); - } - } - /* Spot the total leakage power of this spice model */ - fprintf(fp, ".measure tran total_leakage_power_%s \n", spice.spice_models[imodel].prefix); - fprintf(fp, "+ param = 'leakage_power_%s[%dto%d]'\n", - spice.spice_models[imodel].prefix, - spice.spice_models[imodel].grid_index_low[grid_x][grid_y], - spice.spice_models[imodel].grid_index_high[grid_x][grid_y]-1); - break; - case SPICE_MEASURE_DYNAMIC_POWER: - /* Bypass zero-usage spice_model in this grid*/ - if (spice.spice_models[imodel].grid_index_low[grid_x][grid_y] - == spice.spice_models[imodel].grid_index_high[grid_x][grid_y]) { - continue; - } - for (i = spice.spice_models[imodel].grid_index_low[grid_x][grid_y]; - i < spice.spice_models[imodel].grid_index_high[grid_x][grid_y]; - i++) { - fprintf(fp, ".measure tran dynamic_power_%s[%dto%d] \n", - spice.spice_models[imodel].prefix, - spice.spice_models[imodel].grid_index_low[grid_x][grid_y], - i); - if (spice.spice_models[imodel].grid_index_low[grid_x][grid_y] == i) { - fprintf(fp, "+ param = 'dynamic_power_%s[%d]'\n", spice.spice_models[imodel].prefix, i); - } else { - fprintf(fp, "+ param = 'dynamic_power_%s[%d]+dynamic_power_%s[%dto%d]'\n", - spice.spice_models[imodel].prefix, i, - spice.spice_models[imodel].prefix, - spice.spice_models[imodel].grid_index_low[grid_x][grid_y], - i-1); - } - } - /* Spot the total dynamic power of this spice model */ - fprintf(fp, ".measure tran total_dynamic_power_%s \n", spice.spice_models[imodel].prefix); - fprintf(fp, "+ param = 'dynamic_power_%s[%dto%d]'\n", - spice.spice_models[imodel].prefix, - spice.spice_models[imodel].grid_index_low[grid_x][grid_y], - spice.spice_models[imodel].grid_index_high[grid_x][grid_y]-1); - fprintf(fp, ".measure tran total_energy_per_cycle_%s \n", spice.spice_models[imodel].prefix); - fprintf(fp, "+ param = 'dynamic_power_%s[%dto%d]*clock_period'\n", - spice.spice_models[imodel].prefix, - spice.spice_models[imodel].grid_index_low[grid_x][grid_y], - spice.spice_models[imodel].grid_index_high[grid_x][grid_y]-1); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid meas_type!\n", __FILE__, __LINE__); - exit(1); - } - } - } - - - return; -} - - -/***** Print (call) the defined grids *****/ -void fprint_call_defined_grids(FILE* fp) { - int ix, iy; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Normal Grids */ - for (ix = 1; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grid[ix][iy].type) { - continue; - } - assert(IO_TYPE != grid[ix][iy].type); - fprintf(fp, "Xgrid[%d][%d] ", ix, iy); - fprintf(fp, "\n"); - fprint_grid_pins(fp, ix, iy, 1); - fprintf(fp, "+ "); - fprintf(fp, "gvdd 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ - } - } - - /* IO Grids */ - - /* TOP side */ - iy = ny + 1; - for (ix = 1; ix < (nx + 1); ix++) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grid[ix][iy].type) { - continue; - } - assert(IO_TYPE == grid[ix][iy].type); - fprintf(fp, "Xgrid[%d][%d] ", ix, iy); - fprintf(fp, "\n"); - fprint_io_grid_pins(fp, ix, iy, 1); - fprintf(fp, "+ "); - /* Connect to a speical vdd port for statistics power */ - fprintf(fp, "gvdd_io 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ - } - - /* RIGHT side */ - ix = nx + 1; - for (iy = 1; iy < (ny + 1); iy++) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grid[ix][iy].type) { - continue; - } - assert(IO_TYPE == grid[ix][iy].type); - fprintf(fp, "Xgrid[%d][%d] ", ix, iy); - fprintf(fp, "\n"); - fprint_io_grid_pins(fp, ix, iy, 1); - fprintf(fp, "+ "); - /* Connect to a speical vdd port for statistics power */ - fprintf(fp, "gvdd_io 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ - } - - /* BOTTOM side */ - iy = 0; - for (ix = 1; ix < (nx + 1); ix++) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grid[ix][iy].type) { - continue; - } - assert(IO_TYPE == grid[ix][iy].type); - fprintf(fp, "Xgrid[%d][%d] ", ix, iy); - fprintf(fp, "\n"); - fprint_io_grid_pins(fp, ix, iy, 1); - fprintf(fp, "+ "); - /* Connect to a speical vdd port for statistics power */ - fprintf(fp, "gvdd_io 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ - } - - /* LEFT side */ - ix = 0; - for (iy = 1; iy < (ny + 1); iy++) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grid[ix][iy].type) { - continue; - } - assert(IO_TYPE == grid[ix][iy].type); - fprintf(fp, "Xgrid[%d][%d] ", ix, iy); - fprintf(fp, "\n"); - fprint_io_grid_pins(fp, ix, iy, 1); - fprintf(fp, "+ "); - /* Connect to a speical vdd port for statistics power */ - fprintf(fp, "gvdd_io 0 grid[%d][%d]\n", ix, iy); /* Call the name of subckt */ - } - - return; -} - -/* Call defined channels. - * Ensure the port name here is co-herent to other sub-circuits(SB,CB,grid)!!! - */ -void fprint_call_defined_one_channel(FILE* fp, - t_rr_type chan_type, - int x, int y, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { - int itrack; - int chan_width = 0; - t_rr_node** chan_rr_nodes = NULL; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((CHANX == chan_type)||(CHANY == chan_type)); - /* check x*/ - assert((!(0 > x))&&(x < (nx + 1))); - /* check y*/ - assert((!(0 > y))&&(y < (ny + 1))); - - /* Collect rr_nodes for Tracks for chanx[ix][iy] */ - chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, x, y, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - - /* Call the define sub-circuit */ - fprintf(fp, "X%s[%d][%d] ", - convert_chan_type_to_string(chan_type), - x, y); - fprintf(fp, "\n"); - /* LEFT/BOTTOM side port of CHANX/CHANY */ - /* We apply an opposite port naming rule than function: fprint_routing_chan_subckt - * In top-level netlists, we follow the same port name as switch blocks and connection blocks - * When a track is in INC_DIRECTION, the LEFT/BOTTOM port would be an output of a switch block - * When a track is in DEC_DIRECTION, the LEFT/BOTTOM port would be an input of a switch block - */ - for (itrack = 0; itrack < chan_width; itrack++) { - fprintf(fp, "+ "); - switch (chan_rr_nodes[itrack]->direction) { - case INC_DIRECTION: - fprintf(fp, "%s[%d][%d]_out[%d] ", - convert_chan_type_to_string(chan_type), - x, y, itrack); - fprintf(fp, "\n"); - break; - case DEC_DIRECTION: - fprintf(fp, "%s[%d][%d]_in[%d] ", - convert_chan_type_to_string(chan_type), - x, y, itrack); - fprintf(fp, "\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%d]!\n", - __FILE__, __LINE__, - convert_chan_type_to_string(chan_type), - x, y, itrack); - exit(1); - } - } - /* RIGHT/TOP side port of CHANX/CHANY */ - /* We apply an opposite port naming rule than function: fprint_routing_chan_subckt - * In top-level netlists, we follow the same port name as switch blocks and connection blocks - * When a track is in INC_DIRECTION, the RIGHT/TOP port would be an input of a switch block - * When a track is in DEC_DIRECTION, the RIGHT/TOP port would be an output of a switch block - */ - for (itrack = 0; itrack < chan_width; itrack++) { - fprintf(fp, "+ "); - switch (chan_rr_nodes[itrack]->direction) { - case INC_DIRECTION: - fprintf(fp, "%s[%d][%d]_in[%d] ", - convert_chan_type_to_string(chan_type), - x, y, itrack); - fprintf(fp, "\n"); - break; - case DEC_DIRECTION: - fprintf(fp, "%s[%d][%d]_out[%d] ", - convert_chan_type_to_string(chan_type), - x, y, itrack); - fprintf(fp, "\n"); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%d]!\n", - __FILE__, __LINE__, - convert_chan_type_to_string(chan_type), - x, y, itrack); - exit(1); - } - } - /* output at middle point */ - for (itrack = 0; itrack < chan_width; itrack++) { - fprintf(fp, "+ "); - fprintf(fp, "%s[%d][%d]_midout[%d] ", - convert_chan_type_to_string(chan_type), - x, y, itrack); - fprintf(fp, "\n"); - } - fprintf(fp, "+ gvdd 0 %s[%d][%d]\n", - convert_chan_type_to_string(chan_type), - x, y); - - /* Free */ - my_free(chan_rr_nodes); - - return; -} - -/* Call the sub-circuits for channels : Channel X and Channel Y*/ -void fprint_call_defined_channels(FILE* fp, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { - int ix, iy; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Channel X */ - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - fprint_call_defined_one_channel(fp, CHANX, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - } - } - - /* Channel Y */ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - fprint_call_defined_one_channel(fp, CHANY, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); - } - } - - return; -} - -/* Call the defined sub-circuit of connection box - * TODO: actually most of this function is copied from - * spice_routing.c : fprint_conneciton_box_interc - * Should be more clever to use the original function - */ -void fprint_call_defined_one_connection_box(FILE* fp, - t_cb cur_cb_info) { - int itrack, inode, side; - int side_cnt = 0; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > cur_cb_info.x))&&(!(cur_cb_info.x > (nx + 1)))); - assert((!(0 > cur_cb_info.y))&&(!(cur_cb_info.y > (ny + 1)))); - - /* Print the definition of subckt*/ - /* Identify the type of connection box */ - switch(cur_cb_info.type) { - case CHANX: - fprintf(fp, "Xcbx[%d][%d] ", cur_cb_info.x, cur_cb_info.y); - break; - case CHANY: - fprintf(fp, "Xcby[%d][%d] ", cur_cb_info.x, cur_cb_info.y); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "\n"); - - /* Print the ports of channels*/ - /* connect to the mid point of a track*/ - side_cnt = 0; - for (side = 0; side < cur_cb_info.num_sides; side++) { - /* Bypass side with zero channel width */ - if (0 == cur_cb_info.chan_width[side]) { - continue; - } - assert (0 < cur_cb_info.chan_width[side]); - side_cnt++; - for (itrack = 0; itrack < cur_cb_info.chan_width[side]; itrack++) { - fprintf(fp, "+ "); - fprintf(fp, "%s[%d][%d]_midout[%d] ", - convert_chan_type_to_string(cur_cb_info.type), - cur_cb_info.x, cur_cb_info.y, itrack); - fprintf(fp, "\n"); - } - } - /*check side_cnt */ - assert(1 == side_cnt); - - side_cnt = 0; - /* Print the ports of grids*/ - /* only check ipin_rr_nodes of cur_cb_info */ - for (side = 0; side < cur_cb_info.num_sides; side++) { - /* Bypass side with zero IPINs*/ - if (0 == cur_cb_info.num_ipin_rr_nodes[side]) { - continue; - } - side_cnt++; - assert(0 < cur_cb_info.num_ipin_rr_nodes[side]); - assert(NULL != cur_cb_info.ipin_rr_node[side]); - for (inode = 0; inode < cur_cb_info.num_ipin_rr_nodes[side]; inode++) { - fprintf(fp, "+ "); - /* Print each INPUT Pins of a grid */ - fprint_grid_side_pin_with_given_index(fp, cur_cb_info.ipin_rr_node[side][inode]->ptc_num, - cur_cb_info.ipin_rr_node_grid_side[side][inode], - cur_cb_info.ipin_rr_node[side][inode]->xlow, - cur_cb_info.ipin_rr_node[side][inode]->ylow); - fprintf(fp, "\n"); - } - } - /* Make sure only 2 sides of IPINs are printed */ - assert((1 == side_cnt)||(2 == side_cnt)); - - fprintf(fp, "+ "); - /* Identify the type of connection box */ - switch(cur_cb_info.type) { - case CHANX: - /* Need split vdd port for each Connection Box */ - fprintf(fp, "gvdd_cbx[%d][%d] 0 ", cur_cb_info.x, cur_cb_info.y); - fprintf(fp, "cbx[%d][%d]\n", cur_cb_info.x, cur_cb_info.y); - break; - case CHANY: - /* Need split vdd port for each Connection Box */ - fprintf(fp, "gvdd_cby[%d][%d] 0 ", cur_cb_info.x, cur_cb_info.y); - fprintf(fp, "cby[%d][%d]\n", cur_cb_info.x, cur_cb_info.y); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", __FILE__, __LINE__); - exit(1); - } - - /* Free */ - - return; -} - -/* Call the sub-circuits for connection boxes */ -void fprint_call_defined_connection_boxes(FILE* fp) { - int ix, iy; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* X - channels [1...nx][0..ny]*/ - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - if ((TRUE == is_cb_exist(CHANX, ix, iy)) - &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { - fprint_call_defined_one_connection_box(fp, cbx_info[ix][iy]); - } - } - } - /* Y - channels [1...ny][0..nx]*/ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - if ((TRUE == is_cb_exist(CHANY, ix, iy)) - &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { - fprint_call_defined_one_connection_box(fp, cby_info[ix][iy]); - } - } - } - - return; -} - -/* Call the defined switch box sub-circuit - * Critical difference between this function and - * spice_routing.c : fprint_routing_switch_box_subckt - * Whether a channel node of a Switch block should be input or output depends on it location: - * For example, a channel chanX INC_DIRECTION on the right side of a SB, it is marked as an input - * In fprint_routing_switch_box_subckt: it is marked as an output. - * For channels chanY with INC_DIRECTION on the top/bottom side, they should be marked as inputs - * For channels chanY with DEC_DIRECTION on the top/bottom side, they should be marked as outputs - * For channels chanX with INC_DIRECTION on the left/right side, they should be marked as inputs - * For channels chanX with DEC_DIRECTION on the left/right side, they should be marked as outputs - */ -void fprint_call_defined_one_switch_box(FILE* fp, - t_sb cur_sb_info) { - int ix, iy, side, itrack, inode; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > cur_sb_info.x))&&(!(cur_sb_info.x > (nx + 1)))); - assert((!(0 > cur_sb_info.y))&&(!(cur_sb_info.y > (ny + 1)))); - - fprintf(fp, "Xsb[%d][%d] ", cur_sb_info.x, cur_sb_info.y); - fprintf(fp, "\n"); - - for (side = 0; side < cur_sb_info.num_sides; side++) { - determine_sb_port_coordinator(cur_sb_info, side, &ix, &iy); - - fprintf(fp, "+ "); - for (itrack = 0; itrack < cur_sb_info.chan_width[side]; itrack++) { - switch (cur_sb_info.chan_rr_node_direction[side][itrack]) { - case OUT_PORT: - fprintf(fp, "%s[%d][%d]_out[%d] ", - convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), - ix, iy, itrack); - break; - case IN_PORT: - fprintf(fp, "%s[%d][%d]_in[%d] ", - convert_chan_type_to_string(cur_sb_info.chan_rr_node[side][itrack]->type), - ix, iy, itrack); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of sb[%d][%d] side[%d] track[%d]!\n", - __FILE__, __LINE__, cur_sb_info.x, cur_sb_info.y, side, itrack); - exit(1); - } - } - fprintf(fp, "\n"); - fprintf(fp, "+ "); - /* Dump OPINs of adjacent CLBs */ - for (inode = 0; inode < cur_sb_info.num_opin_rr_nodes[side]; inode++) { - fprint_grid_side_pin_with_given_index(fp, cur_sb_info.opin_rr_node[side][inode]->ptc_num, - cur_sb_info.opin_rr_node_grid_side[side][inode], - cur_sb_info.opin_rr_node[side][inode]->xlow, - cur_sb_info.opin_rr_node[side][inode]->ylow); - } - fprintf(fp, "\n"); - } - - - /* Connect to separate vdd port for each switch box??? */ - fprintf(fp, "+ "); - fprintf(fp, " gvdd_sb[%d][%d] 0 sb[%d][%d]\n", - cur_sb_info.x, cur_sb_info.y, cur_sb_info.x, cur_sb_info.y); - - /* Free */ - - return; -} - -void fprint_call_defined_switch_boxes(FILE* fp) { - int ix, iy; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 0; iy < (ny + 1); iy++) { - fprint_call_defined_one_switch_box(fp, sb_info[ix][iy]); - } - } - - return; -} - -void fprint_spice_toplevel_one_grid_side_pin_with_given_index(FILE* fp, - int pin_index, int side, - int x, int y) { - t_type_ptr type; - int height; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - - type = grid[x][y].type; - assert(NULL != type); - - assert((!(0 > pin_index))&&(pin_index < type->num_pins)); - assert((!(0 > side))&&(!(side > 3))); - - /* Output the pins on the side*/ - height = get_grid_pin_height(x, y, pin_index); - fprintf(fp, " grid[%d][%d]_pin[%d][%d][%d] ", - x, y, height, side, pin_index); - - return; -} - -/* Apply a CLB to CLB direct connection to a SPICE netlist */ -static -void fprint_spice_one_clb2clb_direct(FILE* fp, - int from_grid_x, int from_grid_y, - int to_grid_x, int to_grid_y, - t_clb_to_clb_directs* cur_direct) { - int ipin, cur_from_clb_pin_index, cur_to_clb_pin_index; - int cur_from_clb_pin_side, cur_to_clb_pin_side; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check bandwidth match between from_clb and to_clb pins */ - if (0 != (cur_direct->from_clb_pin_end_index - cur_direct->from_clb_pin_start_index - - (cur_direct->to_clb_pin_end_index - cur_direct->to_clb_pin_start_index))) { - vpr_printf(TIO_MESSAGE_ERROR, "(%s, [LINE%d]) Unmatch pin bandwidth in direct connection (name=%s)!\n", - __FILE__, __LINE__, cur_direct->name); - exit(1); - } - - for (ipin = 0; ipin < cur_direct->from_clb_pin_end_index - cur_direct->from_clb_pin_start_index; ipin++) { - /* Update pin index and get the side of the pins on grids */ - cur_from_clb_pin_index = cur_direct->from_clb_pin_start_index + ipin; - cur_to_clb_pin_index = cur_direct->to_clb_pin_start_index + ipin; - cur_from_clb_pin_side = get_grid_pin_side(from_grid_x, from_grid_y, cur_from_clb_pin_index); - cur_to_clb_pin_side = get_grid_pin_side(to_grid_x, to_grid_y, cur_to_clb_pin_index); - /* Call the subckt that has already been defined before */ - fprintf(fp, "X%s[%d] ", cur_direct->spice_model->prefix, cur_direct->spice_model->cnt); - /* Input: Print the source grid pin */ - fprint_spice_toplevel_one_grid_side_pin_with_given_index(fp, - cur_from_clb_pin_index, - cur_from_clb_pin_side, - from_grid_x, from_grid_y); - /* Output: Print the destination grid pin */ - fprint_spice_toplevel_one_grid_side_pin_with_given_index(fp, - cur_to_clb_pin_index, - cur_to_clb_pin_side, - to_grid_x, from_grid_y); - /* Print Global VDD and GND */ - fprintf(fp, "%s %s ", - spice_tb_global_vdd_direct_port_name, - spice_tb_global_gnd_port_name); - /* End with spice_model name */ - fprintf(fp, "%s\n", cur_direct->spice_model->name); - - /* Stats the number of spice_model used*/ - cur_direct->spice_model->cnt++; - } - - return; -} - -/* Apply CLB to CLB direct connections to a SPICE netlist */ -void fprint_spice_clb2clb_directs(FILE* fp, - int num_directs, - t_clb_to_clb_directs* direct) { - int ix, iy, idirect; - int to_clb_x, to_clb_y; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "***** BEGIN CLB to CLB Direct Connections *****\n"); - - /* Scan the grid, visit each grid and apply direct connections */ - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 0; iy < (ny + 1); iy++) { - /* Bypass EMPTY_TYPE*/ - if ((NULL == grid[ix][iy].type) - || (EMPTY_TYPE == grid[ix][iy].type)) { - continue; - } - /* Check each clb2clb directs, - * see if a match to the type - */ - for (idirect = 0; idirect < num_directs; idirect++) { - /* Bypass unmatch types */ - if (grid[ix][iy].type != direct[idirect].from_clb_type) { - continue; - } - /* Apply x/y_offset */ - to_clb_x = ix + direct[idirect].x_offset; - to_clb_y = iy + direct[idirect].y_offset; - /* see if the destination CLB is in the bound */ - if ((FALSE == is_grid_coordinate_in_range(0, nx, to_clb_x)) - ||(FALSE == is_grid_coordinate_in_range(0, ny, to_clb_y))) { - continue; - } - /* Check if capacity (z_offset) is in the range - if (FALSE == is_grid_coordinate_in_range(0, grid[ix][iy].type->capacity, grid[ix][iy].type->z + direct[idirect].z_offset)) { - continue; - } - */ - /* Check if the to_clb_type matches */ - if (grid[to_clb_x][to_clb_y].type != direct[idirect].to_clb_type) { - continue; - } - /* Bypass x/y_offset = 1 - * since it may be addressed in Connection blocks - if (1 == (x_offset + y_offset)) { - continue; - } - */ - /* Now we can print a direct connection with the spice models */ - fprint_spice_one_clb2clb_direct(fp, - ix, iy, - to_clb_x, to_clb_y, - &direct[idirect]); - } - } - } - - fprintf(fp, "***** END CLB to CLB Direct Connections *****\n"); - - return; -} - -/* Print stimulations for floating ports in Grid - * Some ports of CLB or I/O Pads is floating. - * There are two cases : - * 1. Their corresponding rr_node (SOURE or OPIN) has 0 fan-out. - * 2. Their corresponding rr_node (SINK or IPIN) has 0 fan-in. - * In these cases, we short connect them to global GND. - */ -static -void fprint_grid_float_port_stimulation(FILE* fp) { - int inode; - int num_float_port = 0; - int port_x, port_y, port_height; - int side, class_id, pin_index, pin_written_times; - t_type_ptr type = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Search all rr_nodes */ - for (inode = 0; inode < num_rr_nodes; inode++) { - switch (rr_node[inode].type) { - case SOURCE: - case OPIN: - /* Make sure 0 fan-in, 1 fan-in is connected to SOURCE */ - assert((0 == rr_node[inode].fan_in)||(1 == rr_node[inode].fan_in)); - if (1 == rr_node[inode].fan_in) { - assert(SOURCE == rr_node[rr_node[inode].prev_node].type); - } - /* Check if there is 0 fan-out */ - if (0 == rr_node[inode].num_edges) { - port_x = rr_node[inode].xlow; - port_y = rr_node[inode].ylow; - port_height = grid[port_x][port_y].offset; - port_y = port_y + port_height; - type = grid[port_x][port_y].type; - assert(NULL != type); - /* Get pin information */ - pin_index = rr_node[inode].ptc_num; - class_id = type->pin_class[pin_index]; - assert(DRIVER == type->class_inf[class_id].type); - pin_written_times = 0; - for (side = 0; side < 4; side++) { - /* Special Care for I/O pad */ - if (IO_TYPE == type) { - side = determine_io_grid_side(port_x, port_y); - } - if (1 == type->pinloc[port_height][side][pin_index]) { - fprintf(fp, "Vfloat_port_%d grid[%d][%d]_pin[%d][%d][%d] 0 0\n", - num_float_port, port_x, port_y, port_height, side, pin_index); - pin_written_times++; - num_float_port++; - } - /* Special Care for I/O pad */ - if (IO_TYPE == type) { - break; - } - } - assert(1 == pin_written_times); - } - break; - case SINK: - case IPIN: - /* Make sure 0 fan-out, 1 fan-out is connected to SINK */ - assert((0 == rr_node[inode].num_edges)||(1 == rr_node[inode].num_edges)); - if (1 == rr_node[inode].num_edges) { - assert(SINK == rr_node[rr_node[inode].edges[0]].type); - } - /* Check if there is 0 fan-out */ - if (0 == rr_node[inode].fan_in) { - port_x = rr_node[inode].xlow; - port_y = rr_node[inode].ylow; - port_height = grid[port_x][port_y].offset; - port_y = port_y + port_height; - type = grid[port_x][port_y + port_height].type; - assert(NULL != type); - /* Get pin information */ - pin_index = rr_node[inode].ptc_num; - class_id = type->pin_class[pin_index]; - assert(RECEIVER == type->class_inf[class_id].type); - pin_written_times = 0; - for (side = 0; side < 4; side++) { - /* Special Care for I/O pad */ - if (IO_TYPE == type) { - side = determine_io_grid_side(port_x, port_y); - } - if (1 == type->pinloc[port_height][side][pin_index]) { - fprintf(fp, "Vfloat_port_%d grid[%d][%d]_pin[%d][%d][%d] 0 0\n", - num_float_port, port_x, port_y, port_height, side, pin_index); - pin_written_times++; - num_float_port++; - } - /* Special Care for I/O pad */ - if (IO_TYPE == type) { - break; - } - } - assert(1 == pin_written_times); - } - break; - case CHANX: - case CHANY: - /*TODO: check 0 fan-in, fan-out channel*/ - case INTRA_CLUSTER_EDGE: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid rr_node type!\n", - __FILE__, __LINE__); - exit(1); - } - } - - vpr_printf(TIO_MESSAGE_INFO, "Connect %d floating grid pin to global gnd.\n", num_float_port); - - return; -} - -void fprint_one_design_param_w_wo_variation(FILE* fp, - char* param_name, - float avg_val, - t_spice_mc_variation_params variation_params) { - /* Check */ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n", - __FILE__,__LINE__); - exit(1); - } - - fprintf(fp,".param %s=", param_name); - if (FALSE == variation_params.variation_on) { - fprintf(fp, "%g", avg_val); - /* We do not allow any negative value exist in the variation, - * This could be too tight, could be removed - */ - } else if (TRUE == check_negative_variation(avg_val, variation_params)) { - fprintf(fp, "%g", avg_val); - } else { - fprintf(fp, "agauss(%g, '%g*%g', %d)", - avg_val, - variation_params.abs_variation, avg_val, - variation_params.num_sigma); - } - fprintf(fp, "\n"); - - return; -} - - -/* Print Technology Library and Design Parameters*/ -void fprint_tech_lib(FILE* fp, - t_spice_mc_variation_params cmos_variation_params, - t_spice_tech_lib tech_lib) { - /* Standard transistors*/ - t_spice_transistor_type* nmos_trans = NULL; - t_spice_transistor_type* pmos_trans = NULL; - - /* I/O transistors*/ - t_spice_transistor_type* io_nmos_trans = NULL; - t_spice_transistor_type* io_pmos_trans = NULL; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n", - __FILE__,__LINE__); - exit(1); - } - /* Include Technology Library*/ - fprintf(fp, "****** Include Technology Library ******\n"); - if (SPICE_LIB_INDUSTRY == tech_lib.type) { - fprintf(fp, ".lib \'%s\' %s\n", tech_lib.path, tech_lib.transistor_type); - } else { - fprintf(fp, ".include \'%s\'\n", tech_lib.path); - } - - /* Print Transistor parameters*/ - /* Define the basic transistor parameters: nl, pl, wn, wp, pn_ratio*/ - fprintf(fp, "****** Transistor Parameters ******\n"); - fprintf(fp,".param beta=%g\n",tech_lib.pn_ratio); - /* Make sure we have only 2 transistor*/ - assert((2 == tech_lib.num_transistor_type)||(4 == tech_lib.num_transistor_type)); - /* Find NMOS*/ - nmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_NMOS); - if (NULL == nmos_trans) { - vpr_printf(TIO_MESSAGE_ERROR,"NMOS transistor is not defined in architecture XML!\n"); - exit(1); - } - - fprint_one_design_param_w_wo_variation(fp, "nl", nmos_trans->chan_length, cmos_variation_params); - fprint_one_design_param_w_wo_variation(fp, "wn", nmos_trans->min_width, cmos_variation_params); - - /* Find PMOS*/ - pmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_PMOS); - if (NULL == pmos_trans) { - vpr_printf(TIO_MESSAGE_ERROR,"PMOS transistor is not defined in architecture XML!\n"); - exit(1); - } - - fprint_one_design_param_w_wo_variation(fp, "pl", pmos_trans->chan_length, cmos_variation_params); - fprint_one_design_param_w_wo_variation(fp, "wp", pmos_trans->min_width, cmos_variation_params); - - /* Print I/O NMOS and PMOS */ - io_nmos_trans = find_mosfet_tech_lib(tech_lib, SPICE_TRANS_IO_NMOS); - if ((NULL == io_nmos_trans) && (4 == tech_lib.num_transistor_type)) { - vpr_printf(TIO_MESSAGE_WARNING,"I/O NMOS transistor is not defined in architecture XML!\n"); - exit(1); - } - if (NULL != io_nmos_trans) { - fprint_one_design_param_w_wo_variation(fp, "io_nl", io_nmos_trans->chan_length, cmos_variation_params); - fprint_one_design_param_w_wo_variation(fp, "io_wn", io_nmos_trans->min_width, cmos_variation_params); - } - - io_pmos_trans = find_mosfet_tech_lib(tech_lib,SPICE_TRANS_IO_PMOS); - if ((NULL == io_pmos_trans) && (4 == tech_lib.num_transistor_type)) { - vpr_printf(TIO_MESSAGE_WARNING,"I/O PMOS transistor is not defined in architecture XML!\n"); - exit(1); - } - if (NULL != io_nmos_trans) { - fprint_one_design_param_w_wo_variation(fp, "io_pl", io_pmos_trans->chan_length, cmos_variation_params); - fprint_one_design_param_w_wo_variation(fp, "io_wp", io_pmos_trans->min_width, cmos_variation_params); - } - - /* Print nominal Vdd */ - fprintf(fp, ".param vsp=%g\n", tech_lib.nominal_vdd); - /* Print I/O VDD */ - fprintf(fp, ".param io_vsp=%g\n", tech_lib.io_vdd); - - return; -} - -/* Print all the circuit design parameters */ -void fprint_spice_circuit_param(FILE* fp, - t_spice_mc_params mc_params, - int num_spice_models, - t_spice_model* spice_model) { - int imodel; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!", - __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "***** Parameters for Circuits *****\n"); - for (imodel = 0; imodel < num_spice_models; imodel++) { - fprintf(fp, "***** Parameters for SPICE MODEL: %s *****\n", - spice_model[imodel].name); - /* Regular design parameters: input buf sizes, output buf sizes*/ - if ((NULL != spice_model[imodel].input_buffer) - &&(TRUE == spice_model[imodel].input_buffer->exist)) { - fprint_one_design_param_w_wo_variation(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_input_buf_size), - spice_model[imodel].input_buffer->size, - mc_params.cmos_variation); - } - - if ((NULL != spice_model[imodel].output_buffer) - &&(TRUE == spice_model[imodel].output_buffer->exist)) { - fprint_one_design_param_w_wo_variation(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_output_buf_size), - spice_model[imodel].output_buffer->size, - mc_params.cmos_variation); - } - - if (NULL != spice_model[imodel].pass_gate_logic) { - fprint_one_design_param_w_wo_variation(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_pass_gate_logic_pmos_size), - spice_model[imodel].pass_gate_logic->pmos_size, - mc_params.cmos_variation); - fprint_one_design_param_w_wo_variation(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_pass_gate_logic_nmos_size), - spice_model[imodel].pass_gate_logic->nmos_size, - mc_params.cmos_variation); - } - - /* Exclusive parameters WIREs */ - if ((SPICE_MODEL_CHAN_WIRE == spice_model[imodel].type) - ||(SPICE_MODEL_WIRE == spice_model[imodel].type)) { - fprint_one_design_param_w_wo_variation(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_wire_param_res_val), - spice_model[imodel].wire_param->res_val, - mc_params.wire_variation); - fprint_one_design_param_w_wo_variation(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_wire_param_cap_val), - spice_model[imodel].wire_param->cap_val, - mc_params.wire_variation); - } - - /* We care the spice models built with RRAMs */ - if (SPICE_MODEL_DESIGN_RRAM == spice_model[imodel].design_tech) { - /* Print Ron */ - fprint_one_design_param_w_wo_variation(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_rram_ron), - spice_model[imodel].design_tech_info.rram_info->ron, - mc_params.rram_variation); - /* Print Roff */ - fprint_one_design_param_w_wo_variation(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_rram_roff), - spice_model[imodel].design_tech_info.rram_info->roff, - mc_params.rram_variation); - /* Print Wprog_set_nmos */ - fprint_one_design_param_w_wo_variation(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_set_nmos), - spice_model[imodel].design_tech_info.rram_info->wprog_set_nmos, - mc_params.cmos_variation); - /* Print Wprog_set_pmos */ - fprint_one_design_param_w_wo_variation(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_set_pmos), - spice_model[imodel].design_tech_info.rram_info->wprog_set_pmos, - mc_params.cmos_variation); - /* Print Wprog_reset_nmos */ - fprint_one_design_param_w_wo_variation(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_reset_nmos), - spice_model[imodel].design_tech_info.rram_info->wprog_reset_nmos, - mc_params.cmos_variation); - /* Print Wprog_reset_pmos */ - fprint_one_design_param_w_wo_variation(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_reset_pmos), - spice_model[imodel].design_tech_info.rram_info->wprog_reset_pmos, - mc_params.cmos_variation); - } - } - - return; -} - -void fprint_spice_netlist_measurement_one_design_param(FILE* fp, - char* param_name) { - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!", - __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, ".meas tran actual_%s param='%s'\n", - param_name, param_name); - - return; -} - -void fprint_spice_netlist_generic_measurements(FILE* fp, - t_spice_mc_params mc_params, - int num_spice_models, - t_spice_model* spice_model) { - - int imodel; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!", - __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "***** Generic Measurements for Circuit Parameters *****\n"); - - if ((FALSE == mc_params.cmos_variation.variation_on) - &&(FALSE == mc_params.rram_variation.variation_on)) { - return; - } - - for (imodel = 0; imodel < num_spice_models; imodel++) { - fprintf(fp, "***** Measurements for Parameters for SPICE MODEL: %s *****\n", - spice_model[imodel].name); - /* Regular design parameters: input buf sizes, output buf sizes*/ - if ((NULL != spice_model[imodel].input_buffer) - &&(TRUE == spice_model[imodel].input_buffer->exist)) { - fprint_spice_netlist_measurement_one_design_param(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_input_buf_size)); - } - - if ((NULL != spice_model[imodel].output_buffer) - &&(TRUE == spice_model[imodel].output_buffer->exist)) { - fprint_spice_netlist_measurement_one_design_param(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_output_buf_size)); - } - - if (NULL != spice_model[imodel].pass_gate_logic) { - fprint_spice_netlist_measurement_one_design_param(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_pass_gate_logic_pmos_size)); - fprint_spice_netlist_measurement_one_design_param(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_pass_gate_logic_nmos_size)); - } - - /* Exclusive parameters WIREs */ - if ((SPICE_MODEL_CHAN_WIRE == spice_model[imodel].type) - ||(SPICE_MODEL_WIRE == spice_model[imodel].type)) { - fprint_spice_netlist_measurement_one_design_param(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_wire_param_res_val)); - fprint_spice_netlist_measurement_one_design_param(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_wire_param_cap_val)); - } - - /* We care the spice models built with RRAMs */ - if (SPICE_MODEL_DESIGN_RRAM == spice_model[imodel].design_tech) { - /* Print Ron */ - fprint_spice_netlist_measurement_one_design_param(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_rram_ron)); - /* Print Roff */ - fprint_spice_netlist_measurement_one_design_param(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_rram_roff)); - /* Print Wprog_set_nmos */ - fprint_spice_netlist_measurement_one_design_param(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_set_nmos)); - /* Print Wprog_set_pmos */ - fprint_spice_netlist_measurement_one_design_param(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_set_pmos)); - /* Print Wprog_reset_nmos */ - fprint_spice_netlist_measurement_one_design_param(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_reset_nmos)); - /* Print Wprog_reset_pmos */ - fprint_spice_netlist_measurement_one_design_param(fp, - my_strcat(spice_model[imodel].name, design_param_postfix_rram_wprog_reset_pmos)); - } - } - - - return; -} - -/* This function may expand. - * It prints temperature, and options for a SPICE simulation - */ -void fprint_spice_options(FILE* fp, - t_spice_params spice_params) { - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!",__FILE__, __LINE__); - exit(1); - } - - /* Temperature */ - fprintf(fp, ".temp %d\n", spice_params.sim_temp); - - /* Options: print capacitances of all nodes */ - if (TRUE == spice_params.captab) { - fprintf(fp, ".option captab\n"); - } - /* Add post could make SPICE very slow for large benchmarks!!! Be careful*/ - if (TRUE == spice_params.post) { - fprintf(fp, ".option post\n"); - } - /* Use fast */ - if (TRUE == spice_params.fast) { - fprintf(fp, ".option fast\n"); - } - - return; -} - -/* This function may expand. - * It prints include paramters for SPICE netlists - */ -void fprint_spice_include_param_headers(FILE* fp, - char* include_dir_path) { - char* temp_include_file_path = NULL; - char* formatted_include_dir_path = format_dir_path(include_dir_path); - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!",__FILE__, __LINE__); - exit(1); - } - - /* Include headers for circuit designs, measurements and stimulates */ - - fprintf(fp, "****** Include Header file: circuit design parameters *****\n"); - temp_include_file_path = my_strcat(formatted_include_dir_path, design_param_header_file_name); - fprintf(fp, ".include \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - - fprintf(fp, "****** Include Header file: measurement parameters *****\n"); - temp_include_file_path = my_strcat(formatted_include_dir_path, meas_header_file_name); - fprintf(fp, ".include \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - - fprintf(fp, "****** Include Header file: stimulation parameters *****\n"); - temp_include_file_path = my_strcat(formatted_include_dir_path, stimu_header_file_name); - fprintf(fp, ".include \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - - return; -} - - -/* This function may expand. - * It prints include sub-circuit SPICE netlists - */ -void fprint_spice_include_key_subckts(FILE* fp, - char* subckt_dir_path) { - char* temp_include_file_path = NULL; - char* formatted_subckt_dir_path = format_dir_path(subckt_dir_path); - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!",__FILE__, __LINE__); - exit(1); - } - - /* Include necessary sub-circuits */ - fprintf(fp, "****** Include subckt netlists: NMOS and PMOS *****\n"); - temp_include_file_path = my_strcat(formatted_subckt_dir_path, nmos_pmos_spice_file_name); - fprintf(fp, ".include \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - - if (1 == rram_design_tech) { - fprintf(fp, "****** Include subckt netlists: RRAM behavior VerilogA model *****\n"); - /* This is a HSPICE Bug! When the verilogA file contain a dir_path, the sim results become weired! */ - /* - temp_include_file_path = my_strcat(formatted_subckt_dir_path, rram_veriloga_file_name); - fprintf(fp, ".hdl \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - */ - fprintf(fp, ".hdl \'%s\'\n", rram_veriloga_file_name); - } - - fprintf(fp, "****** Include subckt netlists: Inverters, Buffers *****\n"); - temp_include_file_path = my_strcat(formatted_subckt_dir_path, basics_spice_file_name); - fprintf(fp, ".include \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - - fprintf(fp, "****** Include subckt netlists: Multiplexers *****\n"); - temp_include_file_path = my_strcat(formatted_subckt_dir_path, muxes_spice_file_name); - fprintf(fp, ".include \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - - fprintf(fp, "****** Include subckt netlists: Wires *****\n"); - temp_include_file_path = my_strcat(formatted_subckt_dir_path, wires_spice_file_name); - fprintf(fp, ".include \'%s\'\n", temp_include_file_path); - my_free(temp_include_file_path); - - return; -} - -void fprint_voltage_pulse_params(FILE* fp, - int init_val, - float density, - float probability) { - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!",__FILE__, __LINE__); - exit(1); - } - - /* TODO: check codes for density and probability, init_val */ - /* If density = 0, this is a constant signal */ - if (0. == density) { - if (0. == probability) { - fprintf(fp, "+ 0\n"); - } else { - fprintf(fp, "+ vsp\n"); - } - return; - } - - if (0 == init_val) { - fprintf(fp, "+ pulse(0 vsp 'clock_period' \n"); - } else { - fprintf(fp, "+ pulse(vsp 0 'clock_period' \n"); - } - /* - fprintf(fp, "+ 'input_slew_pct_rise*%g*clock_period' 'input_slew_pct_fall*%g*clock_period'\n", - 2./density, 2./density); - */ - /* TODO: Think about a reasonable slew for signals with diverse density */ - fprintf(fp, "+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'\n"); - fprintf(fp, "+ '%g*%g*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '%g*clock_period')\n", - probability, 2./density, 2./density); - - return; -} - - -void fprint_spice_netlist_transient_setting(FILE* fp, - t_spice spice, - int num_sim_clock_cycles, - boolean leakage_only) { - int num_clock_cycle = spice.spice_params.meas_params.sim_num_clock_cycle + 1; - - /* Overwrite the sim if auto is turned on */ - if ((TRUE == spice.spice_params.meas_params.auto_select_sim_num_clk_cycle) - &&(num_sim_clock_cycles < num_clock_cycle)) { - num_clock_cycle = num_sim_clock_cycles; - } - /* - if (TRUE == spice.spice_params.meas_params.auto_select_sim_num_clk_cycle) { - assert(!(num_sim_clock_cycles > num_clock_cycle)); - } - */ - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!",__FILE__, __LINE__); - exit(1); - } - - /* Leakage power only, use a simplified tran sim*/ - if (TRUE == leakage_only) { - fprintf(fp, "***** Transient simulation only for leakage power *****\n"); - } else { - fprintf(fp, "***** %d Clock Simulation, accuracy=%g *****\n", - num_clock_cycle, spice.spice_params.meas_params.accuracy); - } - - /* Determine the transistion time to simulate */ - switch (spice.spice_params.meas_params.accuracy_type) { - case SPICE_ABS: - fprintf(fp, ".tran %g ", - spice.spice_params.meas_params.accuracy); - break; - case SPICE_FRAC: - fprintf(fp, ".tran '%d*clock_period/%d' ", - num_clock_cycle, (int)spice.spice_params.meas_params.accuracy); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid accuracy type!\n", - __FILE__, __LINE__); - exit(1); - } - - if (TRUE == leakage_only) { - fprintf(fp, " 'clock_period'"); - } else { - fprintf(fp, " '%d*clock_period'", - num_clock_cycle); - } - - if ((TRUE == spice.spice_params.mc_params.cmos_variation.variation_on) - ||(TRUE == spice.spice_params.mc_params.rram_variation.variation_on) - ||(TRUE == spice.spice_params.mc_params.mc_sim)) { - fprintf(fp, " sweep monte=%d ", - spice.spice_params.mc_params.num_mc_points); - } - - fprintf(fp, "\n"); - - return; -} - -void fprint_stimulate_dangling_one_grid_pin(FILE* fp, - int x, int y, - int height, int side, int pin_index, - t_ivec*** LL_rr_node_indices) { - t_type_ptr type_descriptor = grid[x][y].type; - int capacity = grid[x][y].type->capacity; - int class_id; - int rr_node_index; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - assert(NULL != type_descriptor); - assert(0 < capacity); - - class_id = type_descriptor->pin_class[pin_index]; - if (DRIVER == type_descriptor->class_inf[class_id].type) { - rr_node_index = get_rr_node_index(x, y, OPIN, pin_index, LL_rr_node_indices); - /* Zero fan-out OPIN */ - if (0 == rr_node[rr_node_index].num_edges) { - fprintf(fp, "Rdangling_grid[%d][%d]_pin[%d][%d][%d] grid[%d][%d]_pin[%d][%d][%d] 0 1e9\n", - x, y, height, side, pin_index, - x, y, height, side, pin_index); - fprintf(fp, "*.nodeset V(grid[%d][%d]_pin[%d][%d][%d]) 0 \n", - x, y, height, side, pin_index); - } - return; - } - if (RECEIVER == type_descriptor->class_inf[class_id].type) { - rr_node_index = get_rr_node_index(x, y, IPIN, pin_index, LL_rr_node_indices); - /* Zero fan-in IPIN */ - if (0 == rr_node[rr_node_index].fan_in) { - fprintf(fp, "Rdangling_grid[%d][%d]_pin[%d][%d][%d] grid[%d][%d]_pin[%d][%d][%d] 0 0\n", - x, y, height, side, pin_index, - x, y, height, side, pin_index); - fprintf(fp, ".nodeset V(grid[%d][%d]_pin[%d][%d][%d]) 0\n", - x, y, height, side, pin_index); - } - return; - } - - return; -} - -void fprint_stimulate_dangling_io_grid_pins(FILE* fp, - int x, int y) { - int iheight, side, ipin; - t_type_ptr type_descriptor = grid[x][y].type; - int capacity = grid[x][y].type->capacity; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - assert(NULL != type_descriptor); - assert(0 < capacity); - - /* identify the location of IO grid and - * decide which side of ports we need - */ - side = determine_io_grid_side(x,y); - - /* Count the number of pins */ - //for (iz = 0; iz < capacity; iz++) { - for (iheight = 0; iheight < type_descriptor->height; iheight++) { - for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { - if (1 == type_descriptor->pinloc[iheight][side][ipin]) { - fprint_stimulate_dangling_one_grid_pin(fp, x, y, iheight, side, ipin, rr_node_indices); - } - } - } - //} - - return; -} - -void fprint_stimulate_dangling_normal_grid_pins(FILE* fp, - int x, int y) { - int iheight, side, ipin; - t_type_ptr type_descriptor = grid[x][y].type; - int capacity = grid[x][y].type->capacity; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - assert(NULL != type_descriptor); - assert(0 < capacity); - - for (side = 0; side < 4; side++) { - /* Count the number of pins */ - for (iheight = 0; iheight < type_descriptor->height; iheight++) { - for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { - if (1 == type_descriptor->pinloc[iheight][side][ipin]) { - fprint_stimulate_dangling_one_grid_pin(fp, x, y, iheight, side, ipin, rr_node_indices); - } - } - } - } - - return; - -} - -void fprint_stimulate_dangling_grid_pins(FILE* fp) { - int ix, iy; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Normal Grids */ - for (ix = 1; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grid[ix][iy].type) { - continue; - } - assert(IO_TYPE != grid[ix][iy].type); - /* zero-fan-in CLB IPIN*/ - fprint_stimulate_dangling_normal_grid_pins(fp, ix, iy); - } - } - - /* IO Grids */ - /* LEFT side */ - ix = 0; - for (iy = 1; iy < (ny + 1); iy++) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grid[ix][iy].type) { - continue; - } - assert(IO_TYPE == grid[ix][iy].type); - fprint_stimulate_dangling_io_grid_pins(fp, ix, iy); - } - - /* RIGHT side */ - ix = nx + 1; - for (iy = 1; iy < (ny + 1); iy++) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grid[ix][iy].type) { - continue; - } - assert(IO_TYPE == grid[ix][iy].type); - fprint_stimulate_dangling_io_grid_pins(fp, ix, iy); - } - - /* BOTTOM side */ - iy = 0; - for (ix = 1; ix < (nx + 1); ix++) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grid[ix][iy].type) { - continue; - } - assert(IO_TYPE == grid[ix][iy].type); - fprint_stimulate_dangling_io_grid_pins(fp, ix, iy); - } - - /* TOP side */ - iy = ny + 1; - for (ix = 1; ix < (nx + 1); ix++) { - /* Bypass EMPTY grid */ - if (EMPTY_TYPE == grid[ix][iy].type) { - continue; - } - assert(IO_TYPE == grid[ix][iy].type); - fprint_stimulate_dangling_io_grid_pins(fp, ix, iy); - } - - return; -} - -void init_logical_block_spice_model_temp_used(t_spice_model* spice_model) { - int i; - - /* For each logical block, we print a vdd */ - for (i = 0; i < num_logical_blocks; i++) { - if (logical_block[i].mapped_spice_model == spice_model) { - logical_block[i].temp_used = 0; - } - } - - return; -} - -void init_logical_block_spice_model_type_temp_used(int num_spice_models, t_spice_model* spice_model, - enum e_spice_model_type spice_model_type) { - int i; - - /* For each logical block, we print a vdd */ - for (i = 0; i < num_spice_models; i++) { - if (spice_model_type == spice_model[i].type) { - init_logical_block_spice_model_temp_used(&(spice_model[i])); - } - } - - return; -} - -void fprint_global_vdds_logical_block_spice_model(FILE* fp, - t_spice_model* spice_model) { - int i; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* For each logical block, we print a vdd */ - for (i = 0; i < num_logical_blocks; i++) { - if ((logical_block[i].mapped_spice_model == spice_model) - &&(1 == logical_block[i].temp_used)){ - fprintf(fp, ".global gvdd_%s[%d]\n", - spice_model->prefix, logical_block[i].mapped_spice_model_index); - } - } - - return; -} - -void fprint_splited_vdds_logical_block_spice_model(FILE* fp, - t_spice_model* spice_model) { - int i; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* For each logical block, we print a vdd */ - for (i = 0; i < num_logical_blocks; i++) { - if ((logical_block[i].mapped_spice_model == spice_model) - &&(1 == logical_block[i].temp_used)){ - fprintf(fp, "Vgvdd_%s[%d] gvdd_%s[%d] 0 vsp\n", - spice_model->prefix, logical_block[i].mapped_spice_model_index, - spice_model->prefix, logical_block[i].mapped_spice_model_index); - } - } - - return; -} - -void fprint_measure_vdds_logical_block_spice_model(FILE* fp, - t_spice_model* spice_model, - enum e_measure_type meas_type, - int num_clock_cycle, - boolean leakage_only) { - int i, iport, ipin, cur; - float average_output_density = 0.; - int output_cnt = 0; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* For each logical block, we print a vdd */ - for (i = 0; i < num_logical_blocks; i++) { - if ((logical_block[i].mapped_spice_model == spice_model) - &&(1 == logical_block[i].temp_used)) { - /* Get the average output density */ - output_cnt = 0; - for (iport = 0; iport < logical_block[i].pb->pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < logical_block[i].pb->pb_graph_node->num_output_pins[iport]; ipin++) { - average_output_density += vpack_net[logical_block[i].output_nets[iport][ipin]].spice_net_info->density; - output_cnt++; - } - } - average_output_density = average_output_density/output_cnt; - switch (meas_type) { - case SPICE_MEASURE_LEAKAGE_POWER: - if (TRUE == leakage_only) { - fprintf(fp, ".measure tran leakage_power_%s[%d] find p(Vgvdd_%s[%d]) at=0\n", - spice_model->prefix, logical_block[i].mapped_spice_model_index, - spice_model->prefix, logical_block[i].mapped_spice_model_index); - } else { - fprintf(fp, ".measure tran leakage_power_%s[%d] avg p(Vgvdd_%s[%d]) from=0 to='clock_period'\n", - spice_model->prefix, logical_block[i].mapped_spice_model_index, - spice_model->prefix, logical_block[i].mapped_spice_model_index); - } - break; - case SPICE_MEASURE_DYNAMIC_POWER: - fprintf(fp, ".measure tran dynamic_power_%s[%d] avg p(Vgvdd_%s[%d]) from='clock_period' to='%d*clock_period'\n", - spice_model->prefix, logical_block[i].mapped_spice_model_index, - spice_model->prefix, logical_block[i].mapped_spice_model_index, - num_clock_cycle); - fprintf(fp, ".measure tran energy_per_cycle_%s[%d] param='dynamic_power_%s[%d]*clock_period'\n", - spice_model->prefix, logical_block[i].mapped_spice_model_index, - spice_model->prefix, logical_block[i].mapped_spice_model_index); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid meas_type!\n", __FILE__, __LINE__); - exit(1); - } - } - } - - /* Measure the total power of this kind of spice model */ - cur = 0; - switch (meas_type) { - case SPICE_MEASURE_LEAKAGE_POWER: - for (i = 0; i < num_logical_blocks; i++) { - if ((logical_block[i].mapped_spice_model == spice_model) - &&(1 == logical_block[i].temp_used)) { - fprintf(fp, ".measure tran leakage_power_%s[0to%d] \n", - spice_model->prefix, cur); - if (0 == cur) { - fprintf(fp, "+ param = 'leakage_power_%s[%d]'\n", - spice_model->prefix, logical_block[i].mapped_spice_model_index); - } else { - fprintf(fp, "+ param = 'leakage_power_%s[%d]+leakage_power_%s[0to%d]'\n", - spice_model->prefix, logical_block[i].mapped_spice_model_index, - spice_model->prefix, cur-1); - } - cur++; - } - } - if (0 == cur) { - break; - } - /* Spot the total leakage power of this spice model */ - fprintf(fp, ".measure tran total_leakage_power_%s \n", spice_model->prefix); - fprintf(fp, "+ param = 'leakage_power_%s[0to%d]'\n", - spice_model->prefix, cur-1); - break; - case SPICE_MEASURE_DYNAMIC_POWER: - for (i = 0; i < num_logical_blocks; i++) { - if ((logical_block[i].mapped_spice_model == spice_model) - &&(1 == logical_block[i].temp_used)) { - fprintf(fp, ".measure tran energy_per_cycle_%s[0to%d] \n", - spice_model->prefix, cur); - if (0 == cur) { - fprintf(fp, "+ param = 'energy_per_cycle_%s[%d]'\n", - spice_model->prefix, logical_block[i].mapped_spice_model_index); - } else { - fprintf(fp, "+ param = 'energy_per_cycle_%s[%d]+energy_per_cycle_%s[0to%d]'\n", - spice_model->prefix, logical_block[i].mapped_spice_model_index, - spice_model->prefix, cur-1); - } - cur++; - } - } - if (0 == cur) { - break; - } - /* Spot the total dynamic power of this spice model */ - fprintf(fp, ".measure tran total_energy_per_cycle_%s \n", spice_model->prefix); - fprintf(fp, "+ param = 'energy_per_cycle_%s[0to%d]'\n", - spice_model->prefix, cur-1); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid meas_type!\n", __FILE__, __LINE__); - exit(1); - } - - return; -} - -/* Give voltage stimuli of one global port */ -void fprint_spice_testbench_wire_one_global_port_stimuli(FILE* fp, - t_spice_model_port* cur_global_port, - char* voltage_stimuli_port_name) { - int ipin; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - assert(NULL != cur_global_port); - - for (ipin = 0; ipin < cur_global_port->size; ipin++) { - fprintf(fp, "Rshortwire%s[%d] %s[%d] ", - cur_global_port->prefix, ipin, - cur_global_port->prefix, ipin); - assert((0 == cur_global_port->default_val)||(1 == cur_global_port->default_val)); - fprintf(fp, "%s", - voltage_stimuli_port_name); - if (1 == cur_global_port->default_val) { - fprintf(fp, "%s ", - spice_tb_global_port_inv_postfix); - } - fprintf(fp, " 0\n"); - } - - return; - -} - -/* Give voltage stimuli of global ports */ -void fprint_spice_testbench_global_ports_stimuli(FILE* fp, - t_llist* head) { - t_llist* temp = head; - t_spice_model_port* cur_global_port = NULL; - int ipin; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - fprintf(fp, "***** Connecting Global ports *****\n"); - while(NULL != temp) { - cur_global_port = (t_spice_model_port*)(temp->dptr); - /* Make sure this is a global port */ - assert(TRUE == cur_global_port->is_global); - /* If this is a clock signal, connect to op_clock signal */ - if (SPICE_MODEL_PORT_CLOCK == cur_global_port->type) { - /* Special for programming clock */ - if (TRUE == cur_global_port->is_prog) { - /* We do need to program SRAMs/RRAM in spice netlist - * Just wire it to a constant GND/VDD - */ - fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, - spice_tb_global_config_done_port_name); - } else { - assert(FALSE == cur_global_port->is_prog); - fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, - spice_tb_global_clock_port_name); - } - /* If this is a config_enable signal, connect to config_done signal */ - } else if (TRUE == cur_global_port->is_config_enable) { - fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, - spice_tb_global_config_done_port_name); - /* If this is a set/reset signal, connect to global reset and set signals */ - } else if (TRUE == cur_global_port->is_reset) { - /* Special for programming reset */ - if (TRUE == cur_global_port->is_prog) { - fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, - spice_tb_global_reset_port_name); - } else { - assert(FALSE == cur_global_port->is_prog); - fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, - spice_tb_global_reset_port_name); - } - /* If this is a set/reset signal, connect to global reset and set signals */ - } else if (TRUE == cur_global_port->is_set) { - /* Special for programming reset */ - if (TRUE == cur_global_port->is_prog) { - fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, - spice_tb_global_set_port_name); - } else { - assert(FALSE == cur_global_port->is_prog); - fprint_spice_testbench_wire_one_global_port_stimuli(fp, cur_global_port, - spice_tb_global_set_port_name); - } - } else { - /* Other global signals stuck at the default values */ - for (ipin = 0; ipin < cur_global_port->size; ipin++) { - fprintf(fp, "R%s[%d] %s[%d] ", - cur_global_port->prefix, ipin, - cur_global_port->prefix, ipin); - assert( (0 == cur_global_port->default_val)||(1 == cur_global_port->default_val) ); - if ( 0 == cur_global_port->default_val ) { - /* Default value is 0: Connect to the global GND port */ - fprintf(fp, " %s", - spice_tb_global_gnd_port_name); - } else { - /* Default value is 1: Connect to the global VDD port */ - fprintf(fp, " %s", - spice_tb_global_vdd_port_name); - } - fprintf(fp, " 0\n"); - } - } - /* Go to the next */ - temp = temp->next; - } - fprintf(fp, "***** End Connecting Global ports *****\n"); - - return; -} - -void fprint_spice_testbench_global_vdd_port_stimuli(FILE* fp, - char* global_vdd_port_name, - char* voltage_level) { - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Print a Voltage Stimuli */ - fprintf(fp, "V%s %s 0 %s\n", - global_vdd_port_name, - global_vdd_port_name, - voltage_level); - return; -} - -void fprint_spice_testbench_global_sram_inport_stimuli(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info) { - t_spice_model* mem_model = NULL; - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Get memory spice model */ - get_sram_orgz_info_mem_model(cur_sram_orgz_info, &mem_model); - - /* Every SRAM inputs should have a voltage source */ - fprintf(fp, "***** Global Inputs for SRAMs *****\n"); - if (SPICE_SRAM_SCAN_CHAIN == cur_sram_orgz_info->type) { - fprintf(fp, "Vsc_clk sc_clk 0 0\n"); - fprintf(fp, "Vsc_rst sc_rst 0 0\n"); - fprintf(fp, "Vsc_set sc_set 0 0\n"); - fprintf(fp, "V%s[0]->in %s[0]->in 0 0\n", mem_model->prefix, mem_model->prefix); - fprintf(fp, ".nodeset V(%s[0]->in) 0\n", mem_model->prefix); - } else { - fprintf(fp, "V%s->in %s->in 0 0\n", - mem_model->prefix, mem_model->prefix); - fprintf(fp, ".nodeset V(%s->in) 0\n", mem_model->prefix); - } - - return; -} - -void fprint_spice_testbench_generic_global_ports_stimuli(FILE* fp, - int num_clock) { - - /* Check the file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Global GND */ - fprintf(fp, "***** Global VDD port *****\n"); - fprintf(fp, "V%s %s 0 vsp\n", - spice_tb_global_vdd_port_name, - spice_tb_global_vdd_port_name); - fprintf(fp, "***** Global GND port *****\n"); - fprintf(fp, "V%s %s 0 0\n", - spice_tb_global_gnd_port_name, - spice_tb_global_gnd_port_name); - - /* Global set and reset */ - fprintf(fp, "***** Global Net for reset signal *****\n"); - fprintf(fp, "V%s %s 0 0\n", - spice_tb_global_reset_port_name, - spice_tb_global_reset_port_name); - fprintf(fp, "V%s%s %s%s 0 vsp\n", - spice_tb_global_reset_port_name, - spice_tb_global_port_inv_postfix, - spice_tb_global_reset_port_name, - spice_tb_global_port_inv_postfix); - fprintf(fp, "***** Global Net for set signal *****\n"); - fprintf(fp, "V%s %s 0 0\n", - spice_tb_global_set_port_name, - spice_tb_global_set_port_name); - fprintf(fp, "V%s%s %s%s 0 vsp\n", - spice_tb_global_set_port_name, - spice_tb_global_port_inv_postfix, - spice_tb_global_set_port_name, - spice_tb_global_port_inv_postfix); - - /* Global config done */ - fprintf(fp, "***** Global Net for configuration done signal *****\n"); - fprintf(fp, "V%s %s 0 0\n", - spice_tb_global_config_done_port_name, - spice_tb_global_config_done_port_name); - fprintf(fp, "V%s%s %s%s 0 vsp\n", - spice_tb_global_config_done_port_name, - spice_tb_global_port_inv_postfix, - spice_tb_global_config_done_port_name, - spice_tb_global_port_inv_postfix); - - /* Global clock if we need one */ - if (1 == num_clock) { - /* First cycle reserved for measuring leakage */ - fprintf(fp, "***** Global Clock signal *****\n"); - fprintf(fp, "***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****\n"); - fprintf(fp, "V%s %s 0 pulse(0 vsp 'clock_period'\n", - spice_tb_global_clock_port_name, - spice_tb_global_clock_port_name); - fprintf(fp, "+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'\n"); - fprintf(fp, "+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')\n"); - fprintf(fp, "\n"); - fprintf(fp, "***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****\n"); - fprintf(fp, "V%s%s %s%s 0 pulse(0 vsp 'clock_period'\n", - spice_tb_global_clock_port_name, - spice_tb_global_port_inv_postfix, - spice_tb_global_clock_port_name, - spice_tb_global_port_inv_postfix); - fprintf(fp, "+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'\n"); - fprintf(fp, "+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')\n"); - } else { - assert(0 == num_clock); - /* Give constant value */ - fprintf(fp, "V%s %s 0 0\n", - spice_tb_global_clock_port_name, - spice_tb_global_clock_port_name); - fprintf(fp, "V%s%s %s%s 0 vsp\n", - spice_tb_global_clock_port_name, - spice_tb_global_port_inv_postfix, - spice_tb_global_clock_port_name, - spice_tb_global_port_inv_postfix); - } - - return; -} - -/* Find the inverter size of a Programmable Logic Block Pin - * - */ -float find_spice_testbench_pb_pin_mux_load_inv_size(t_spice_model* fan_out_spice_model) { - float load_inv_size = 0; - - /* Check */ - assert(NULL != fan_out_spice_model); - assert(NULL != fan_out_spice_model->input_buffer); - - /* Special: this is a LUT, we should consider more inv size */ - if (SPICE_MODEL_LUT == fan_out_spice_model->type) { - assert(1 == fan_out_spice_model->lut_input_buffer->exist); - assert((SPICE_MODEL_BUF_INV == fan_out_spice_model->lut_input_buffer->type) - ||(SPICE_MODEL_BUF_BUF == fan_out_spice_model->lut_input_buffer->type)); - assert(TRUE == fan_out_spice_model->lut_input_buffer->tapered_buf); - assert(2 == fan_out_spice_model->lut_input_buffer->tap_buf_level); - load_inv_size = fan_out_spice_model->lut_input_buffer->size - + fan_out_spice_model->lut_input_buffer->f_per_stage; - return load_inv_size; - } - - /* depend on the input_buffer type */ - if (1 == fan_out_spice_model->input_buffer->exist) { - switch(fan_out_spice_model->input_buffer->type) { - case SPICE_MODEL_BUF_INV: - load_inv_size = fan_out_spice_model->input_buffer->size; - break; - case SPICE_MODEL_BUF_BUF: - load_inv_size = 1.; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid fanout spice_model input_buffer type!\n", - __FILE__, __LINE__); - exit(1); - } - } else { - /* TODO: If there is no inv/buffer at input, we should traversal until there is one - * However, now we just simply give a minimum sized inverter - */ - load_inv_size = 1.; - } - - return load_inv_size; -} - -float find_spice_testbench_rr_mux_load_inv_size(t_rr_node* load_rr_node, - int switch_index) { - float load_inv_size = 0; - t_spice_model* fan_out_spice_model = NULL; - - fan_out_spice_model = switch_inf[switch_index].spice_model; - - /* Check */ - assert(NULL != fan_out_spice_model); - assert(NULL != fan_out_spice_model->input_buffer); - - /* depend on the input_buffer type */ - if (1 == fan_out_spice_model->input_buffer->exist) { - switch(fan_out_spice_model->input_buffer->type) { - case SPICE_MODEL_BUF_INV: - load_inv_size = fan_out_spice_model->input_buffer->size; - break; - case SPICE_MODEL_BUF_BUF: - load_inv_size = fan_out_spice_model->input_buffer->size; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid fanout spice_model input_buffer type!\n", - __FILE__, __LINE__); - exit(1); - } - } else { - /* TODO: If there is no inv/buffer at input, we should traversal until there is one - * However, now we just simply give a minimum sized inverter - * fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, - x, y, - &(cur_pb_graph_node->output_pins[0][0]), - logical_block[logical_block_index].pb, - outport_name, - FALSE, - LL_rr_node_indices); - - */ - load_inv_size = 1; - } - - return load_inv_size; - -} - -void fprint_spice_testbench_pb_graph_pin_inv_loads_rec(FILE* fp, int* testbench_load_cnt, - int grid_x, int grid_y, - t_pb_graph_pin* src_pb_graph_pin, - t_phy_pb* src_pb, - char* outport_name, - boolean consider_parent_node, - t_ivec*** LL_rr_node_indices) { - int iedge, mode_index, ipb, jpb; - t_interconnect* cur_interc = NULL; - char* rec_outport_name = NULL; - t_phy_pb* des_pb = NULL; - int src_rr_node_index = -1; - float load_inv_size = 0.; - float total_width; - int width_cnt; - - /* A valid file handler*/ - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); - exit(1); - } - - assert(NULL != src_pb_graph_pin); - - if (TRUE == consider_parent_node) { - if (NULL != src_pb_graph_pin->parent_node->pb_type->spice_model) { - load_inv_size = find_spice_testbench_pb_pin_mux_load_inv_size(src_pb_graph_pin->parent_node->pb_type->spice_model); - /* Print inverters by considering maximum width */ - total_width = load_inv_size; - width_cnt = 0; - while (total_width > max_width_per_trans) { - fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[0] gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, outport_name, outport_name, max_width_per_trans); - /* Update counter */ - total_width = total_width - max_width_per_trans; - width_cnt++; - } - if (total_width > 0) { - fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[0] gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, outport_name, outport_name, total_width); - (*testbench_load_cnt)++; - } - return; - } - } - - /* Get the mode_index */ - if (NULL == src_pb) { - mode_index = find_pb_type_physical_mode_index(*(src_pb_graph_pin->parent_node->pb_type)); - } else { - mode_index = src_pb->mode; - } - - /* If this pb belongs to a pb_graph_head, - * the src_pb_graph_pin is a OPIN, we should find the rr_node */ - if ((OUT_PORT == src_pb_graph_pin->port->type) - &&(NULL == src_pb_graph_pin->parent_node->parent_pb_graph_node)) { - /* Find the corresponding rr_node */ - assert(grid[grid_x][grid_y].type->pb_graph_head == src_pb_graph_pin->parent_node); - src_rr_node_index = get_rr_node_index(grid_x, grid_y, OPIN, src_pb_graph_pin->pin_count_in_cluster, LL_rr_node_indices); - for (iedge = 0; iedge < rr_node[src_rr_node_index].num_edges; iedge++) { - /* Detect its input buffers */ - load_inv_size = find_spice_testbench_rr_mux_load_inv_size(&rr_node[rr_node[src_rr_node_index].edges[iedge]], - rr_node[src_rr_node_index].switches[iedge]); - /* Print inverters by considering maximum width */ - total_width = load_inv_size; - width_cnt = 0; - while (total_width > max_width_per_trans) { - fprintf(fp, "Xload_inv[%d]_no%d %s load_inv[%d]_out gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, outport_name, - (*testbench_load_cnt), max_width_per_trans); - /* Update counter */ - total_width = total_width - max_width_per_trans; - width_cnt++; - } - if (total_width > 0) { - fprintf(fp, "Xload_inv[%d]_no%d %s load_inv[%d]_out gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, outport_name, - (*testbench_load_cnt), total_width); - } - (*testbench_load_cnt)++; - } - return; - } - - /* Search output edges */ - for (iedge = 0; iedge < src_pb_graph_pin->num_output_edges; iedge++) { - check_pb_graph_edge(*(src_pb_graph_pin->output_edges[iedge])); - /* We care only the edges in selected mode */ - cur_interc = src_pb_graph_pin->output_edges[iedge]->interconnect; - assert(NULL != cur_interc); - if (mode_index == cur_interc->parent_mode_index) { - rec_outport_name = (char*)my_malloc(sizeof(char)* (strlen(outport_name) + 5 + strlen(my_itoa(iedge)) +2 )); - sprintf(rec_outport_name, "%s_out[%d]", outport_name, iedge); - /* check the interc has spice_model and if it is buffered */ - assert(NULL != cur_interc->spice_model); - if (TRUE == cur_interc->spice_model->input_buffer->exist) { - /* Print a inverter, and we stop this branch */ - load_inv_size = find_spice_testbench_pb_pin_mux_load_inv_size(cur_interc->spice_model); - /* Print inverters by considering maximum width */ - total_width = load_inv_size; - width_cnt = 0; - while (total_width > max_width_per_trans) { - fprintf(fp, "Xload_inv[%d]_no%d %s %s gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, outport_name, rec_outport_name, max_width_per_trans); - /* Update counter */ - total_width = total_width - max_width_per_trans; - width_cnt++; - } - if (total_width > 0) { - fprintf(fp, "Xload_inv[%d]_no%d %s %s gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, outport_name, rec_outport_name, total_width); - } - (*testbench_load_cnt)++; - } else { - /* - fprintf(fp, "R%s_to_%s %s %s 0\n", - outport_name, rec_outport_name, - outport_name, rec_outport_name); - */ - /* Go recursively */ - if (NULL == src_pb) { - des_pb = NULL; - } else { - if (IN_PORT == src_pb_graph_pin->port->type) { - ipb = src_pb_graph_pin->output_edges[iedge]->output_pins[0]->parent_node->pb_type - - src_pb_graph_pin->parent_node->pb_type->modes[mode_index].pb_type_children; - jpb = src_pb_graph_pin->output_edges[iedge]->output_pins[0]->parent_node->placement_index; - if ((NULL != src_pb->child_pbs[ipb])&&(NULL != src_pb->child_pbs[ipb][jpb].name)) { - des_pb = &(src_pb->child_pbs[ipb][jpb]); - } else { - des_pb = NULL; - } - } else if (OUT_PORT == src_pb_graph_pin->port->type) { - des_pb = src_pb->parent_pb; - } else if (INOUT_PORT == src_pb_graph_pin->port->type) { - des_pb = NULL; /* I don't know what to do...*/ - } - } - fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, testbench_load_cnt, grid_x, grid_y, - src_pb_graph_pin->output_edges[iedge]->output_pins[0], - des_pb, outport_name, TRUE, LL_rr_node_indices); - - } - } - } - - return; -} - -char* fprint_spice_testbench_rr_node_load_version(FILE* fp, int* testbench_load_cnt, - int num_segments, - t_segment_inf* segments, - int load_level, - t_rr_node cur_rr_node, - char* outport_name) { - char* ret_outport_name = NULL; - char* mid_outport_name = NULL; - int cost_index; - int iseg, i, iedge, chan_wire_length, cur_x, cur_y; - t_rr_node to_node; - t_spice_model* wire_spice_model = NULL; - float load_inv_size = 0.; - float total_width; - int width_cnt; - - /* We only process CHANX or CHANY*/ - if (!((CHANX == cur_rr_node.type) - ||(CHANY == cur_rr_node.type))) { - ret_outport_name = my_strdup(outport_name); - return ret_outport_name; - } - - /* Important: - * As the cur_rr_node can only be channel wires - * and channel wires can only be driven at the starting point, - * in this function, - * the loads to be added will always starts from the starting point of a channel wire. - * We will consider the length of channel wires when adding the loads. - * For example, a length-4 wire will introduce 4 levels of channel segments to the loads. - * To handle the corner case, we will consider the border when adding channel segments - * If the length of wire exceeds the borderline of FPGA, - * we will adapt the number of channel segments. - */ - cost_index = cur_rr_node.cost_index; - iseg = rr_indexed_data[cost_index].seg_index; - assert((!(iseg < 0))&&(iseg < num_segments)); - wire_spice_model = segments[iseg].spice_model; - assert(SPICE_MODEL_CHAN_WIRE == wire_spice_model->type); - /* Check if the coordinate is correct */ - assert((0 == cur_rr_node.xhigh - cur_rr_node.xlow) - ||(0 == cur_rr_node.yhigh - cur_rr_node.ylow)); - chan_wire_length = cur_rr_node.xhigh - cur_rr_node.xlow - + cur_rr_node.yhigh - cur_rr_node.ylow; - - fprintf(fp, "**** Loads for rr_node: xlow=%d, ylow=%d, xhigh=%d, yhigh=%d, ptc_num=%d, type=%d *****\n", - cur_rr_node.xlow, cur_rr_node.ylow, - cur_rr_node.xhigh, cur_rr_node.yhigh, - cur_rr_node.ptc_num, cur_rr_node.type); - - for (i = 0; i < chan_wire_length + 1; i++) { - ret_outport_name = (char*)my_malloc(sizeof(char)*( strlen(outport_name) - + 9 + strlen(my_itoa(load_level + i)) + 6 - + 1 )); - sprintf(ret_outport_name,"%s_loadlvl[%d]_out", - outport_name, load_level + i); - mid_outport_name = (char*)my_malloc(sizeof(char)*( strlen(outport_name) - + 9 + strlen(my_itoa(load_level + i)) + 9 - + 1 )); - sprintf(mid_outport_name,"%s_loadlvl[%d]_midout", - outport_name, load_level + i); - if (0 == i) { - fprintf(fp, "Xchan_%s %s %s %s gvdd_load 0 %s_seg%d\n", - ret_outport_name, outport_name, ret_outport_name, mid_outport_name, - wire_spice_model->name, iseg); - } else { - fprintf(fp, "Xchan_%s %s_loadlvl[%d]_out %s %s gvdd_load 0 %s_seg%d\n", - ret_outport_name, outport_name, load_level + i -1, ret_outport_name, mid_outport_name, - wire_spice_model->name, iseg); - } - /* Print CB inv loads connected to the mid_out */ - switch (cur_rr_node.type) { - case CHANX: - /* Update the cur_x & cur_y */ - if (INC_DIRECTION == cur_rr_node.direction) { - cur_x = cur_rr_node.xlow + i; - cur_y = cur_rr_node.ylow; - } else { - assert(DEC_DIRECTION == cur_rr_node.direction); - cur_x = cur_rr_node.xhigh - i; - cur_y = cur_rr_node.ylow; - } - for (iedge = 0; iedge < cur_rr_node.num_edges; iedge++) { - /*Identify if the des node is a IPIN and fit the current(x,y)*/ - to_node = rr_node[cur_rr_node.edges[iedge]]; - switch (to_node.type) { - case IPIN: - /* The assert only works for homogeneous blocks - assert(to_node.xhigh == to_node.xlow); - assert(to_node.yhigh == to_node.ylow); - */ - if (((cur_x == to_node.xlow)&&(cur_y == to_node.ylow)) - ||((cur_x == to_node.xlow)&&((cur_y + 1) == to_node.ylow))) { - /* We find a CB! */ - /* Detect its input buffers */ - load_inv_size = find_spice_testbench_rr_mux_load_inv_size(&to_node, - cur_rr_node.switches[iedge]); - /* TODO: Need to find the downsteam inv_loads if it is not bufferred - fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, &testbench_load_cnt, - x, y, - &(cur_pb_graph_node->output_pins[0][0]), - logical_block[logical_block_index].pb, - outport_name, - FALSE, - LL_rr_node_indices); - */ - assert(0. < load_inv_size); - /* Print an inverter */ - total_width = load_inv_size; - width_cnt = 0; - while (total_width > max_width_per_trans) { - fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, mid_outport_name, mid_outport_name, iedge, - max_width_per_trans); - /* Update */ - total_width = total_width - max_width_per_trans; - width_cnt++; - } - if (total_width > 0) { - fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, mid_outport_name, mid_outport_name, iedge, - total_width); - } - (*testbench_load_cnt)++; - } - break; - case CHANX: - case CHANY: - /* We find a SB! */ - /* Detect its input buffers */ - load_inv_size = find_spice_testbench_rr_mux_load_inv_size(&to_node, - cur_rr_node.switches[iedge]); - assert(0. < load_inv_size); - /* Print an inverter */ - total_width = load_inv_size; - width_cnt = 0; - while (total_width > max_width_per_trans) { - fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, ret_outport_name, ret_outport_name, iedge, - max_width_per_trans); - /* Update */ - total_width = total_width - max_width_per_trans; - width_cnt++; - } - if (total_width > 0) { - fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, ret_outport_name, ret_outport_name, iedge, - total_width); - } - (*testbench_load_cnt)++; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid src_rr_node_type!\n", - __FILE__, __LINE__); - exit(1); - } - } - break; - case CHANY: - /* Update the cur_x & cur_y */ - if (INC_DIRECTION == cur_rr_node.direction) { - cur_x = cur_rr_node.xlow; - cur_y = cur_rr_node.ylow + i; - } else { - assert(DEC_DIRECTION == cur_rr_node.direction); - cur_x = cur_rr_node.xlow; - cur_y = cur_rr_node.yhigh - i; - } - for (iedge = 0; iedge < cur_rr_node.num_edges; iedge++) { - /*Identify if the des node is a IPIN and fit the current(x,y)*/ - to_node = rr_node[cur_rr_node.edges[iedge]]; - switch (to_node.type) { - case IPIN: - /* The assert only works for homogeneous blocks - assert(to_node.xhigh == to_node.xlow); - assert(to_node.yhigh == to_node.ylow); - */ - if (((cur_y == to_node.ylow)&&(cur_x == to_node.xlow)) - ||((cur_y == to_node.xlow)&&((cur_x + 1) == to_node.xlow))) { - /* We find a CB! */ - /* Detect its input buffers */ - load_inv_size = find_spice_testbench_rr_mux_load_inv_size(&to_node, - cur_rr_node.switches[iedge]); - assert(0. < load_inv_size); - /* Print an inverter */ - total_width = load_inv_size; - width_cnt = 0; - while (total_width > max_width_per_trans) { - fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, mid_outport_name, mid_outport_name, iedge, - max_width_per_trans); - /* Update */ - total_width = total_width - max_width_per_trans; - width_cnt++; - } - if (total_width > 0) { - fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, mid_outport_name, mid_outport_name, iedge, - total_width); - } - (*testbench_load_cnt)++; - } - break; - case CHANX: - case CHANY: - /* We find a SB! */ - /* Detect its input buffers */ - load_inv_size = find_spice_testbench_rr_mux_load_inv_size(&to_node, - cur_rr_node.switches[iedge]); - assert(0. < load_inv_size); - /* Print an inverter */ - total_width = load_inv_size; - width_cnt = 0; - while (total_width > max_width_per_trans) { - fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, ret_outport_name, ret_outport_name, iedge, - total_width); - /* Update */ - total_width = total_width - max_width_per_trans; - width_cnt++; - } - if (total_width > 0) { - fprintf(fp, "Xload_inv[%d]_no%d %s %s_out[%d] gvdd_load 0 inv size=%g\n", - (*testbench_load_cnt), width_cnt, ret_outport_name, ret_outport_name, iedge, - total_width); - } - (*testbench_load_cnt)++; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid src_rr_node_type!\n", - __FILE__, __LINE__); - exit(1); - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid src_rr_node_type!\n", - __FILE__, __LINE__); - exit(1); - } - } - - return ret_outport_name; -} - -void fprint_spice_testbench_one_cb_mux_loads(FILE* fp, int* testbench_load_cnt, - t_rr_node* src_rr_node, - char* outport_name, - t_ivec*** LL_rr_node_indices) { - t_type_ptr cb_out_grid_type = NULL; - t_pb_graph_pin* cb_out_pb_graph_pin = NULL; - t_phy_pb* cb_out_pb = NULL; - - assert(IPIN == src_rr_node->type); - /* The assert only works for homogeneous blocks - assert(src_rr_node->xlow == src_rr_node->xhigh); - assert(src_rr_node->ylow == src_rr_node->yhigh); - */ - - cb_out_grid_type = grid[src_rr_node->xlow][src_rr_node->ylow].type; - assert(NULL != cb_out_grid_type); - - cb_out_pb_graph_pin = src_rr_node->pb_graph_pin; - assert(NULL != cb_out_pb_graph_pin); - - /* Get the pb ! Get the mode_index */ - if (NULL != src_rr_node->pb) { - cb_out_pb = (t_phy_pb*)(src_rr_node->pb->phy_pb); - } - - if (IO_TYPE == cb_out_grid_type) { - fprintf(fp, "******* IO_TYPE loads *******\n"); - } else { - fprintf(fp, "******* Normal TYPE loads *******\n"); - } - - /* Recursively find all the inv load inside pb_graph_node */ - fprint_spice_testbench_pb_graph_pin_inv_loads_rec(fp, - testbench_load_cnt, - src_rr_node->xlow, - src_rr_node->ylow, - cb_out_pb_graph_pin, - cb_out_pb, - outport_name, - TRUE, - LL_rr_node_indices); - - - fprintf(fp, "******* END loads *******\n"); - return; -} - -void fprint_spice_testbench_one_grid_pin_stimulation(FILE* fp, int x, int y, - int height, int side, - int ipin, - t_ivec*** LL_rr_node_indices) { - int ipin_rr_node_index; - float ipin_density, ipin_probability; - int ipin_init_value; - int class_id; - t_rr_type grid_pin_rr_node_type; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - - /* Identify the type of rr_node */ - class_id = grid[x][y].type->pin_class[ipin]; - if (DRIVER == grid[x][y].type->class_inf[class_id].type) { - grid_pin_rr_node_type = OPIN; - } else if (RECEIVER == grid[x][y].type->class_inf[class_id].type) { - grid_pin_rr_node_type = IPIN; - } else { - /* Error */ - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown pin type for grid(x=%d, y=%d, pin_index=%d)!\n", - __FILE__, __LINE__, - x, y, ipin); - exit(1); - } - - /* Print a voltage source according to density and probability */ - ipin_rr_node_index = get_rr_node_index(x, y, grid_pin_rr_node_type, ipin, LL_rr_node_indices); - /* Get density and probability */ - ipin_density = get_rr_node_net_density(rr_node[ipin_rr_node_index]); - ipin_probability = get_rr_node_net_probability(rr_node[ipin_rr_node_index]); - ipin_init_value = get_rr_node_net_init_value(rr_node[ipin_rr_node_index]); - /* Print voltage source */ - fprintf(fp, "Vgrid[%d][%d]_pin[%d][%d][%d] grid[%d][%d]_pin[%d][%d][%d] 0 \n", - x, y, height, side, ipin, x, y, height, side, ipin); - fprint_voltage_pulse_params(fp, ipin_init_value, ipin_density, ipin_probability); - - return; -} - -void fprint_spice_testbench_one_grid_pin_loads(FILE* fp, int x, int y, - int height, int side, - int ipin, - int* testbench_load_cnt, - t_ivec*** LL_rr_node_indices) { - - int ipin_rr_node_index; - int iedge, iswitch; - char* prefix = NULL; - t_spice_model* switch_spice_model = NULL; - int inv_cnt = 0; - int class_id; - t_rr_type grid_pin_rr_node_type; - - if (NULL == fp) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); - exit(1); - } - - /* Check */ - assert((!(0 > x))&&(!(x > (nx + 1)))); - assert((!(0 > y))&&(!(y > (ny + 1)))); - - /* Identify the type of rr_node */ - class_id = grid[x][y].type->pin_class[ipin]; - if (DRIVER == grid[x][y].type->class_inf[class_id].type) { - grid_pin_rr_node_type = OPIN; - } else if (RECEIVER == grid[x][y].type->class_inf[class_id].type) { - grid_pin_rr_node_type = IPIN; - } else { - /* Error */ - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown pin type for grid(x=%d, y=%d, pin_index=%d)!\n", - __FILE__, __LINE__, - x, y, ipin); - exit(1); - } - - /* Print a voltage source according to density and probability */ - ipin_rr_node_index = get_rr_node_index(x, y, grid_pin_rr_node_type, ipin, LL_rr_node_indices); - /* Generate prefix */ - prefix = (char*)my_malloc(sizeof(char)*(5 + strlen(my_itoa(x)) - + 2 + strlen(my_itoa(y)) + 6 + strlen(my_itoa(height)) - + 2 + strlen(my_itoa(side)) + 2 + strlen(my_itoa(ipin)) - + 2 + 1)); - sprintf(prefix, "grid[%d][%d]_pin[%d][%d][%d]", - x, y, height, side, ipin); - - /* Depending on the type of this pin */ - /* For OPIN, we search the rr_node graph */ - if (OPIN == grid_pin_rr_node_type) { - /* Print all the inverter load now*/ - for (iedge = 0; iedge < rr_node[ipin_rr_node_index].num_edges; iedge++) { - /* Get the switch spice model */ - /* inode = rr_node[ipin_rr_node_index].edges[iedge]; */ - iswitch = rr_node[ipin_rr_node_index].switches[iedge]; - switch_spice_model = switch_inf[iswitch].spice_model; - if (NULL == switch_spice_model) { - continue; - } - /* Add inv/buf here */ - fprintf(fp, "X%s_inv[%d] %s %s_out[%d] gvdd_load 0 inv size=%g\n", - prefix, iedge, - prefix, prefix, iedge, - switch_spice_model->input_buffer->size); - inv_cnt++; - } - /* TODO: go recursively ? */ - /* For IPIN, we should search the internal rr_graph of the grid */ - } else if (IPIN == grid_pin_rr_node_type) { - fprint_spice_testbench_one_cb_mux_loads(fp, testbench_load_cnt, &rr_node[ipin_rr_node_index], - prefix, LL_rr_node_indices); - } else { - /* Error */ - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown pin type for grid(x=%d, y=%d, pin_index=%d)!\n", - __FILE__, __LINE__, - x, y, ipin); - exit(1); - } - /* TODO: Generate loads recursively */ - /*fprint_rr_node_loads_rec(fp, rr_node[ipin_rr_node_index],prefix);*/ - - /*Free */ - my_free(prefix); - - return; -} - - -/* Add one SPICE TB information to linked list */ -t_llist* add_one_spice_tb_info_to_llist(t_llist* cur_head, - char* tb_file_path, - int num_sim_clock_cycles) { - t_llist* new_head = NULL; - - if (NULL == cur_head) { - new_head = create_llist(1); - new_head->dptr = my_malloc(sizeof(t_spicetb_info)); - ((t_spicetb_info*)(new_head->dptr))->tb_name = my_strdup(tb_file_path); - ((t_spicetb_info*)(new_head->dptr))->num_sim_clock_cycles = num_sim_clock_cycles; - } else { - new_head = insert_llist_node_before_head(cur_head); - new_head->dptr = my_malloc(sizeof(t_spicetb_info)); - ((t_spicetb_info*)(new_head->dptr))->tb_name = my_strdup(tb_file_path); - ((t_spicetb_info*)(new_head->dptr))->num_sim_clock_cycles = num_sim_clock_cycles; - } - - return new_head; -} - -char* convert_const_input_value_to_str(int const_input_val) { - switch (const_input_val) { - case 0: - return "sgnd"; - case 1: - return "svdd"; - default: - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid value for constant input (=%d).\n", - __FILE__, __LINE__, const_input_val); - exit(1); - } -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.h deleted file mode 100644 index 8b60f1358..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.h +++ /dev/null @@ -1,253 +0,0 @@ - -/* Enumeration for the types of measurements*/ -enum e_measure_type { - SPICE_MEASURE_LEAKAGE_POWER, SPICE_MEASURE_DYNAMIC_POWER -}; - -/* Subroutines declarations */ - -void fprint_spice_head(FILE* fp, - char* usage); - -FILE* spice_create_one_subckt_file(char* subckt_dir, - char* subckt_name_prefix, - char* spice_subckt_file_name_prefix, - int grid_x, int grid_y, - char** sp_name); - -void spice_print_one_include_subckt_line(FILE* fp, - char* subckt_dir, - char* subckt_file_name); - -int rec_fprint_spice_model_global_ports(FILE* fp, - t_spice_model* cur_spice_model, - boolean recursive); - -void spice_print_subckt_header_file(t_llist* subckt_llist_head, - char* subckt_dir, - char* header_file_name); - -int fprint_spice_global_ports(FILE* fp, t_llist* head); - -void fprint_spice_generic_testbench_global_ports(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - t_llist* head); - -void fprint_spice_sram_one_outport(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - int cur_sram, - int port_type_index); - -void fprint_spice_one_specific_sram_subckt(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - t_spice_model* parent_spice_model, - char* vdd_port_name, - int sram_index); - -void fprint_spice_one_sram_subckt(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info, - t_spice_model* parent_spice_model, - char* vdd_port_name); - -void fprint_voltage_pulse_params(FILE* fp, - int init_val, - float density, - float probability); - - -void init_include_user_defined_netlists(t_spice spice); - -void fprint_include_user_defined_netlists(FILE* fp, - t_spice spice); - -void fprint_splited_vdds_spice_model(FILE* fp, - enum e_spice_model_type spice_model_type, - t_spice spice); - -void fprint_grid_splited_vdds_spice_model(FILE* fp, int grid_x, int grid_y, - enum e_spice_model_type spice_model_type, - t_spice spice); - -void fprint_global_vdds_spice_model(FILE* fp, - enum e_spice_model_type spice_model_type, - t_spice spice); - -void fprint_grid_global_vdds_spice_model(FILE* fp, int x, int y, - enum e_spice_model_type spice_model_type, - t_spice spice); - -void fprint_global_pad_ports_spice_model(FILE* fp, - t_spice spice); - -void fprint_spice_global_vdd_switch_boxes(FILE* fp); - -void fprint_spice_global_vdd_connection_boxes(FILE* fp); - -void fprint_measure_vdds_spice_model(FILE* fp, - enum e_spice_model_type spice_model_type, - enum e_measure_type meas_type, - int num_cycle, - t_spice spice, - boolean leakage_only); - -void fprint_measure_grid_vdds_spice_model(FILE* fp, int grid_x, int grid_y, - enum e_spice_model_type spice_model_type, - enum e_measure_type meas_type, - int num_cycle, - t_spice spice, - boolean leakage_only); - -void fprint_call_defined_grids(FILE* fp); - -void fprint_call_defined_one_channel(FILE* fp, - t_rr_type chan_type, - int x, int y, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices); - -void fprint_call_defined_channels(FILE* fp, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices); - -void fprint_call_defined_one_connection_box(FILE* fp, - t_cb cur_cb_info); - -void fprint_call_defined_connection_boxes(FILE* fp); - -void fprint_call_defined_one_switch_box(FILE* fp, - t_sb cur_sb_info); - -void fprint_call_defined_switch_boxes(FILE* fp); - -void fprint_spice_toplevel_one_grid_side_pin_with_given_index(FILE* fp, - int pin_index, int side, - int x, int y); - -void fprint_spice_clb2clb_directs(FILE* fp, - int num_directs, - t_clb_to_clb_directs* direct); - -void fprint_one_design_param_w_wo_variation(FILE* fp, - char* param_name, - float avg_val, - t_spice_mc_variation_params variation_params); - -void fprint_tech_lib(FILE* fp, - t_spice_mc_variation_params cmos_variation_params, - t_spice_tech_lib tech_lib); - -void fprint_spice_circuit_param(FILE* fp, - t_spice_mc_params mc_params, - int num_spice_models, - t_spice_model* spice_model); - -void fprint_spice_netlist_measurement_one_design_param(FILE* fp, - char* param_name); - -void fprint_spice_netlist_generic_measurements(FILE* fp, - t_spice_mc_params mc_params, - int num_spice_models, - t_spice_model* spice_model); - -void fprint_spice_options(FILE* fp, - t_spice_params spice_params); - -void fprint_spice_include_key_subckts(FILE* fp, - char* subckt_dir_path); - -void fprint_spice_include_param_headers(FILE* fp, - char* include_dir_path); - -void fprint_spice_netlist_transient_setting(FILE* fp, - t_spice spice, - int num_sim_clock_cycles, - boolean leakage_only); - -void fprint_stimulate_dangling_one_grid_pin(FILE* fp, - int x, int y, - int height, int side, int pin_index, - t_ivec*** LL_rr_node_indices); - -void fprint_stimulate_dangling_io_grid_pins(FILE* fp, - int x, int y); - -void fprint_stimulate_dangling_normal_grid_pins(FILE* fp, - int x, int y); - -void fprint_stimulate_dangling_grid_pins(FILE* fp); - -void init_logical_block_spice_model_temp_used(t_spice_model* spice_model); - -void init_logical_block_spice_model_type_temp_used(int num_spice_models, t_spice_model* spice_model, - enum e_spice_model_type spice_model_type); - -void fprint_global_vdds_logical_block_spice_model(FILE* fp, - t_spice_model* spice_model); - -void fprint_splited_vdds_logical_block_spice_model(FILE* fp, - t_spice_model* spice_model); - -void fprint_measure_vdds_logical_block_spice_model(FILE* fp, - t_spice_model* spice_model, - enum e_measure_type meas_type, - int num_clock_cycle, - boolean leakage_only); - -void fprint_spice_testbench_wire_one_global_port_stimuli(FILE* fp, - t_spice_model_port* cur_global_port, - char* voltage_stimuli_port_name); - -void fprint_spice_testbench_global_sram_inport_stimuli(FILE* fp, - t_sram_orgz_info* cur_sram_orgz_info); - -void fprint_spice_testbench_global_vdd_port_stimuli(FILE* fp, - char* global_vdd_port_name, - char* voltage_level); - -void fprint_spice_testbench_global_ports_stimuli(FILE* fp, - t_llist* head); - -void fprint_spice_testbench_generic_global_ports_stimuli(FILE* fp, - int num_clock); - -float find_spice_testbench_pb_pin_mux_load_inv_size(t_spice_model* fan_out_spice_model); - -float find_spice_testbench_rr_mux_load_inv_size(t_rr_node* load_rr_node, - int switch_index); - -void fprint_spice_testbench_pb_graph_pin_inv_loads_rec(FILE* fp, int* testbench_load_cnt, - int grid_x, int grid_y, - t_pb_graph_pin* src_pb_graph_pin, - t_phy_pb* src_pb, - char* outport_name, - boolean consider_parent_node, - t_ivec*** LL_rr_node_indices); - -char* fprint_spice_testbench_rr_node_load_version(FILE* fp, int* testbench_load_cnt, - int num_segments, - t_segment_inf* segments, - int load_level, - t_rr_node cur_rr_node, - char* outport_name); - -void fprint_spice_testbench_one_cb_mux_loads(FILE* fp, int* testbench_load_cnt, - t_rr_node* src_rr_node, - char* outport_name, - t_ivec*** LL_rr_node_indices); - -void fprint_spice_testbench_one_grid_pin_stimulation(FILE* fp, int x, int y, - int height, int side, - int ipin, - t_ivec*** LL_rr_node_indices); - -void fprint_spice_testbench_one_grid_pin_loads(FILE* fp, int x, int y, - int height, int side, - int ipin, - int* testbench_load_cnt, - t_ivec*** LL_rr_node_indices); - -t_llist* add_one_spice_tb_info_to_llist(t_llist* cur_head, - char* tb_file_path, - int num_sim_clock_cycles); - -char* convert_const_input_value_to_str(int const_input_val); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp deleted file mode 100644 index e2b347f84..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.cpp +++ /dev/null @@ -1,84 +0,0 @@ -/********************************************************************* - * This function includes the writer for generating exchangeable - * information, in order to interface different simulators - ********************************************************************/ -#include -#include -#include -#define MINI_CASE_SENSITIVE -#include "ini.h" - -/* Include vpr structs*/ -#include "util.h" - -/* Include FPGA-SPICE utils */ -#include "simulation_utils.h" - -/* Include verilog utils */ -#include "verilog_global.h" -#include "simulation_info_writer.h" - -/********************************************************************* - * Local Variable - ********************************************************************/ -constexpr char* DEFAULT_SIMULATION_INI_FILE_NAME = "simulation_deck_info.ini"; - -/********************************************************************* - * Top-level function to write an ini file which contains exchangeable - * information, in order to interface different Verilog simulators - ********************************************************************/ -void print_verilog_simulation_info(const std::string& simulation_ini_filename, - const std::string& parent_dir, - const std::string& circuit_name, - const std::string& src_dir, - const size_t& num_program_clock_cycles, - const int& num_operating_clock_cycles, - const float& prog_clock_freq, - const float& op_clock_freq) { - - /* Start time count */ - clock_t t_start = clock(); - - /* Use default name if user does not provide one */ - std::string ini_fname; - if (true == simulation_ini_filename.empty()) { - ini_fname = parent_dir + std::string(DEFAULT_SIMULATION_INI_FILE_NAME); - } else { - ini_fname = simulation_ini_filename; - } - - vpr_printf(TIO_MESSAGE_INFO, - "Writing exchangeable file containing simulation information: %s...", - ini_fname.c_str()); - - mINI::INIStructure ini; - // std::map units_map; - // units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6; - // units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15; - - /* Compute simulation time period */ - float simulation_time_period = find_simulation_time_period(1E-3, - num_program_clock_cycles, - 1. / prog_clock_freq, - num_operating_clock_cycles, - 1. / op_clock_freq); - ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject"; - ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name; - ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string("_top_formal_verification_random_tb"); - ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period); - ini["SIMULATION_DECK"]["UNIT "] = "ms"; - ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir); - ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(defines_verilog_file_name); - ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + "_include_netlists.v"); - - mINI::INIFile file(ini_fname); - file.generate(ini, true); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h deleted file mode 100644 index 9644e2a63..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/simulation_info_writer.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef SIMULATION_INFO_WRITER_H -#define SIMULATION_INFO_WRITER_H - -#include - -void print_verilog_simulation_info(const std::string& simulation_ini_filename, - const std::string& parent_dir, - const std::string& circuit_name, - const std::string& src_dir, - const size_t& num_program_clock_cycles, - const int& num_operating_clock_cycles, - const float& prog_clock_freq, - const float& op_clock_freq); -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.cpp deleted file mode 100644 index 3dd850153..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.cpp +++ /dev/null @@ -1,234 +0,0 @@ -/******************************************************************** - * This file include top-level function of FPGA-Verilog - ********************************************************************/ -/* Standard header files */ -#include - -/* External library header files */ -#include "util.h" -#include "vtr_assert.h" -#include "circuit_library_utils.h" - -/* FPGA-X2P header files */ -#include "fpga_x2p_utils.h" -#include "rr_blocks.h" - -/* FPGA-Verilog header files */ -#include "verilog_global.h" -#include "verilog_submodules.h" -#include "verilog_routing.h" -#include "verilog_submodules.h" -#include "verilog_grid.h" -#include "verilog_routing.h" -#include "verilog_top_module.h" -#include "verilog_top_testbench.h" -#include "verilog_formal_random_top_testbench.h" -#include "verilog_preconfig_top_module.h" -#include "simulation_info_writer.h" -#include "verilog_auxiliary_netlists.h" - -/* Header file for this source file */ -#include "verilog_api.h" - -/******************************************************************** - * Top-level function of FPGA-Verilog - * This function will generate - * 1. primitive modules required by the full fabric - * which are LUTs, routing multiplexer, logic gates, transmission-gates etc. - * 2. Routing modules, which are Switch Blocks (SBs) and Connection Blocks (CBs) - * 3. Logic block modules, which are Configuration Logic Blocks (CLBs) - * 4. FPGA module, which are the full FPGA fabric with configuration protocol - * 5. A wrapper module, which encapsulate the FPGA module in a Verilog module which have the same port as the input benchmark - * 6. Testbench, where a FPGA module is configured with a bitstream and then driven by input vectors - * 7. Pre-configured testbench, which can skip the configuration phase and pre-configure the FPGA module. This testbench is created for quick verification and formal verification purpose. - * 8. Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated - ********************************************************************/ -void vpr_fpga_verilog(ModuleManager& module_manager, - const BitstreamManager& bitstream_manager, - const std::vector& fabric_bitstream, - const MuxLibrary& mux_lib, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const DeviceRRGSB& L_device_rr_gsb, - const t_vpr_setup& vpr_setup, - const t_arch& Arch, - const std::string& circuit_name, - t_sram_orgz_info* sram_verilog_orgz_info) { - /* Start time count */ - clock_t t_start = clock(); - - /* 0. basic units: inverter, buffers and pass-gate logics, */ - /* Check if the routing architecture we support*/ - if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) { - vpr_printf(TIO_MESSAGE_ERROR, - "FPGA-Verilog only supports uni-directional routing architecture!\n"); - exit(1); - } - - /* We don't support mrFPGA */ -#ifdef MRFPGA_H - if (is_mrFPGA) { - vpr_printf(TIO_MESSAGE_ERROR, - "FPGA-Verilog does not support mrFPGA!\n"); - exit(1); - } -#endif - - /* Verilog generator formally starts*/ - vpr_printf(TIO_MESSAGE_INFO, - "\nFPGA-Verilog starts...\n"); - - /* Format the directory paths */ - std::string chomped_parent_dir = find_path_dir_name(circuit_name); - std::string chomped_circuit_name = find_path_file_name(circuit_name); - - std::string verilog_dir_formatted; - if (NULL != vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.syn_verilog_dump_dir) { - verilog_dir_formatted = format_dir_path(std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.syn_verilog_dump_dir)); - } else { - verilog_dir_formatted = format_dir_path(format_dir_path(chomped_parent_dir) + std::string(default_verilog_dir_name)); - } - - /* Create directories */ - create_dir_path(verilog_dir_formatted.c_str()); - - /* SRC directory to contain all the netlists */ - std::string src_dir_path = format_dir_path(verilog_dir_formatted + std::string(default_src_dir_name)); - create_dir_path(src_dir_path.c_str()); - - /* Sub directory under SRC directory to contain all the primitive block netlists */ - std::string submodule_dir_path = src_dir_path + std::string(default_submodule_dir_name); - create_dir_path(submodule_dir_path.c_str()); - - /* Sub directory under SRC directory to contain all the logic block netlists */ - std::string lb_dir_path = src_dir_path + std::string(default_lb_dir_name); - create_dir_path(lb_dir_path.c_str()); - - /* Sub directory under SRC directory to contain all the routing block netlists */ - std::string rr_dir_path = src_dir_path + std::string(default_rr_dir_name); - create_dir_path(rr_dir_path.c_str()); - - /* Ensure all the SRAM port is using the correct circuit model */ - config_circuit_models_sram_port_to_default_sram_model(Arch.spice->circuit_lib, Arch.sram_inf.verilog_sram_inf_orgz->circuit_model); - - /* Print Verilog files containing preprocessing flags */ - print_verilog_preprocessing_flags_netlist(std::string(src_dir_path), - vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); - - print_verilog_simulation_preprocessing_flags(std::string(src_dir_path), - vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); - - /* Generate primitive Verilog modules, which are corner stones of FPGA fabric - * Note that this function MUST be called before Verilog generation of - * core logic (i.e., logic blocks and routing resources) !!! - * This is because that this function will add the primitive Verilog modules to - * the module manager. - * Without the modules in the module manager, core logic generation is not possible!!! - */ - print_verilog_submodules(module_manager, mux_lib, sram_verilog_orgz_info, src_dir_path.c_str(), submodule_dir_path.c_str(), - Arch, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts); - - /* Generate routing blocks */ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) { - print_verilog_unique_routing_modules(module_manager, L_device_rr_gsb, - vpr_setup.RoutingArch, - src_dir_path, rr_dir_path, - TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); - } else { - VTR_ASSERT(FALSE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); - print_verilog_flatten_routing_modules(module_manager, L_device_rr_gsb, - vpr_setup.RoutingArch, - src_dir_path, rr_dir_path, - TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); - } - - /* Generate grids */ - print_verilog_grids(module_manager, - src_dir_path, lb_dir_path, - TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); - - /* Generate FPGA fabric */ - print_verilog_top_module(module_manager, - std::string(vpr_setup.FileNameOpts.ArchFile), - src_dir_path, - TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); - - /* Collect global ports from the circuit library - * TODO: move outside this function - */ - std::vector global_ports = find_circuit_library_global_ports(Arch.spice->circuit_lib); - - /* Generate wrapper module for FPGA fabric (mapped by the input benchmark and pre-configured testbench for verification */ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist) { - std::string formal_verification_top_netlist_file_path = src_dir_path + chomped_circuit_name - + std::string(formal_verification_verilog_file_postfix); - print_verilog_preconfig_top_module(module_manager, bitstream_manager, - Arch.spice->circuit_lib, global_ports, L_logical_blocks, - device_size, L_grids, L_blocks, - std::string(chomped_circuit_name), formal_verification_top_netlist_file_path, - std::string(src_dir_path)); - - /* Generate top-level testbench using random vectors */ - std::string random_top_testbench_file_path = src_dir_path + chomped_circuit_name - + std::string(random_top_testbench_verilog_file_postfix); - print_verilog_random_top_testbench(chomped_circuit_name, random_top_testbench_file_path, - src_dir_path, L_logical_blocks, - vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, Arch.spice->spice_params); - } - - /* Generate exchangeable files which contains simulation settings */ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_simulation_ini) { - std::string simulation_ini_file_name; - if (NULL != vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path) { - simulation_ini_file_name = std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.simulation_ini_path); - } - print_verilog_simulation_info(simulation_ini_file_name, - format_dir_path(chomped_parent_dir), - chomped_circuit_name, - src_dir_path, - bitstream_manager.bits().size(), - Arch.spice->spice_params.meas_params.sim_num_clock_cycle, - Arch.spice->spice_params.stimulate_params.prog_clock_freq, - Arch.spice->spice_params.stimulate_params.op_clock_freq); - } - - /* Generate full testbench for verification, including configuration phase and operating phase */ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench) { - std::string autocheck_top_testbench_file_path = src_dir_path + chomped_circuit_name - + std::string(autocheck_top_testbench_verilog_file_postfix); - print_verilog_top_testbench(module_manager, bitstream_manager, fabric_bitstream, - sram_verilog_orgz_info->type, - Arch.spice->circuit_lib, global_ports, - L_logical_blocks, device_size, L_grids, L_blocks, - chomped_circuit_name, - autocheck_top_testbench_file_path, - src_dir_path, - Arch.spice->spice_params); - } - - /* Generate a Verilog file including all the netlists that have been generated */ - std::string ref_verilog_benchmark_file_name; - if (NULL != vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file) { - ref_verilog_benchmark_file_name = std::string(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.reference_verilog_benchmark_file); - } - print_include_netlists(src_dir_path, - chomped_circuit_name, - ref_verilog_benchmark_file_name, - Arch.spice->circuit_lib); - - /* Given a brief stats on how many Verilog modules have been written to files */ - vpr_printf(TIO_MESSAGE_INFO, - "Outputted %lu Verilog modules in total\n", - module_manager.num_modules()); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "FPGA-Verilog took %g seconds\n", - run_time_sec); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h deleted file mode 100644 index 7dd5f4197..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef VERILOG_API_H -#define VERILOG_API_H - -#include -#include -#include "vpr_types.h" -#include "mux_library.h" -#include "rr_blocks.h" -#include "module_manager.h" -#include "bitstream_manager.h" - -void vpr_fpga_verilog(ModuleManager& module_manager, - const BitstreamManager& bitstream_manager, - const std::vector& fabric_bitstream, - const MuxLibrary& mux_lib, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const DeviceRRGSB& L_device_rr_gsb, - const t_vpr_setup& vpr_setup, - const t_arch& Arch, - const std::string& circuit_name, - t_sram_orgz_info* sram_verilog_orgz_info); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp deleted file mode 100644 index 0aa47d8a6..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp +++ /dev/null @@ -1,195 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to generate Verilog files - * or code blocks, with a focus on - * `include user-defined or auto-generated netlists in Verilog format - *******************************************************************/ -#include - -#include "vtr_assert.h" - -#include "circuit_library_utils.h" - -#include "fpga_x2p_utils.h" -#include "fpga_x2p_naming.h" - -#include "verilog_global.h" -#include "verilog_writer_utils.h" -#include "verilog_auxiliary_netlists.h" - -/******************************************************************** - * Local constant variables - *******************************************************************/ -constexpr char* TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v"; - -/******************************************************************** - * Print a file that includes all the netlists that have been generated - * and user-defined. - * Some netlists are open to compile under specific preprocessing flags - *******************************************************************/ -void print_include_netlists(const std::string& src_dir, - const std::string& circuit_name, - const std::string& reference_benchmark_file, - const CircuitLibrary& circuit_lib) { - std::string verilog_fname = src_dir + circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - /* Validate the file stream */ - check_file_handler(fp); - - /* Print the title */ - print_verilog_file_header(fp, std::string("Netlist Summary")); - - /* Print preprocessing flags */ - print_verilog_comment(fp, std::string("------ Include defines: preproc flags -----")); - print_verilog_include_netlist(fp, std::string(src_dir + std::string(defines_verilog_file_name))); - fp << std::endl; - - print_verilog_comment(fp, std::string("------ Include simulation defines -----")); - print_verilog_include_netlist(fp, src_dir + std::string(defines_verilog_simulation_file_name)); - fp << std::endl; - - /* Include all the user-defined netlists */ - for (const std::string& user_defined_netlist : find_circuit_library_unique_verilog_netlists(circuit_lib)) { - print_verilog_include_netlist(fp, user_defined_netlist); - } - - /* Include all the primitive modules */ - print_verilog_include_netlist(fp, src_dir + std::string(default_submodule_dir_name) + std::string(submodule_verilog_file_name)); - fp << std::endl; - - /* Include all the CLB, heterogeneous block modules */ - print_verilog_include_netlist(fp, src_dir + std::string(default_lb_dir_name) + std::string(logic_block_verilog_file_name)); - fp << std::endl; - - /* Include all the routing architecture modules */ - print_verilog_include_netlist(fp, src_dir + std::string(default_rr_dir_name) + std::string(routing_verilog_file_name)); - fp << std::endl; - - /* Include FPGA top module */ - print_verilog_include_netlist(fp, src_dir + generate_fpga_top_netlist_name(std::string(verilog_netlist_file_postfix))); - fp << std::endl; - - /* Include reference benchmark netlist only when auto-check flag is enabled */ - print_verilog_preprocessing_flag(fp, std::string(autochecked_simulation_flag)); - fp << "\t"; - print_verilog_include_netlist(fp, std::string(reference_benchmark_file)); - print_verilog_endif(fp); - fp << std::endl; - - /* Include formal verification netlists only when formal verification flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(verilog_formal_verification_preproc_flag)); - fp << "\t"; - print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(formal_verification_verilog_file_postfix)); - - /* Include formal verification testbench only when formal simulation flag is enabled */ - fp << "\t"; - print_verilog_preprocessing_flag(fp, std::string(formal_simulation_flag)); - fp << "\t\t"; - print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(random_top_testbench_verilog_file_postfix)); - fp << "\t"; - print_verilog_endif(fp); - - print_verilog_endif(fp); - fp << std::endl; - - /* Include top-level testbench only when auto-check flag is enabled */ - print_verilog_preprocessing_flag(fp, std::string(autochecked_simulation_flag)); - fp << "\t"; - print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(autocheck_top_testbench_verilog_file_postfix)); - print_verilog_endif(fp); - fp << std::endl; - - /* Close the file stream */ - fp.close(); -} - -/******************************************************************** - * Print a Verilog file containing preprocessing flags - * which are used enable/disable some features in FPGA Verilog modules - *******************************************************************/ -void print_verilog_preprocessing_flags_netlist(const std::string& src_dir, - const t_syn_verilog_opts& fpga_verilog_opts) { - - std::string verilog_fname = src_dir + std::string(defines_verilog_file_name); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - /* Validate the file stream */ - check_file_handler(fp); - - /* Print the title */ - print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable features in FPGA Verilog modules")); - - /* To enable timing */ - if (TRUE == fpga_verilog_opts.include_timing) { - print_verilog_define_flag(fp, std::string(verilog_timing_preproc_flag), 1); - fp << std::endl; - } - - /* To enable timing */ - if (TRUE == fpga_verilog_opts.include_signal_init) { - print_verilog_define_flag(fp, std::string(verilog_signal_init_preproc_flag), 1); - fp << std::endl; - } - - /* To enable formal verfication flag */ - if (TRUE == fpga_verilog_opts.print_formal_verification_top_netlist) { - print_verilog_define_flag(fp, std::string(verilog_formal_verification_preproc_flag), 1); - fp << std::endl; - } - - /* To enable functional verfication with Icarus */ - if (TRUE == fpga_verilog_opts.include_icarus_simulator) { - print_verilog_define_flag(fp, std::string(icarus_simulator_flag), 1); - fp << std::endl; - } - - /* Close the file stream */ - fp.close(); -} - -/******************************************************************** - * Print a Verilog file containing simulation-related preprocessing flags - *******************************************************************/ -void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, - const t_syn_verilog_opts& fpga_verilog_opts) { - - std::string verilog_fname = src_dir + std::string(defines_verilog_simulation_file_name); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - /* Validate the file stream */ - check_file_handler(fp); - - /* Print the title */ - print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); - - /* To enable manualy checked simulation */ - if (TRUE == fpga_verilog_opts.print_top_testbench) { - print_verilog_define_flag(fp, std::string(initial_simulation_flag), 1); - fp << std::endl; - } - - /* To enable auto-checked simulation */ - if (TRUE == fpga_verilog_opts.print_autocheck_top_testbench) { - print_verilog_define_flag(fp, std::string(autochecked_simulation_flag), 1); - fp << std::endl; - } - - /* To enable pre-configured FPGA simulation */ - if (TRUE == fpga_verilog_opts.print_formal_verification_top_netlist) { - print_verilog_define_flag(fp, std::string(formal_simulation_flag), 1); - fp << std::endl; - } - - - /* Close the file stream */ - fp.close(); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h deleted file mode 100644 index 0a56690cd..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef VERILOG_AUXILIARY_NETLISTS_H -#define VERILOG_AUXILIARY_NETLISTS_H - -#include -#include "circuit_library.h" -#include "vpr_types.h" - -void print_include_netlists(const std::string& src_dir, - const std::string& circuit_name, - const std::string& reference_benchmark_file, - const CircuitLibrary& circuit_lib); - -void print_verilog_preprocessing_flags_netlist(const std::string& src_dir, - const t_syn_verilog_opts& fpga_verilog_opts); - -void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, - const t_syn_verilog_opts& fpga_verilog_opts); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp deleted file mode 100644 index b246c02e1..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp +++ /dev/null @@ -1,377 +0,0 @@ -/*************************************************************************************** - * This file includes functions to generate Verilog modules of decoders - ***************************************************************************************/ -/* TODO: merge verilog_decoder.c to this source file and rename to verilog_decoder.cpp */ -#include - -#include "util.h" -#include "vtr_assert.h" - -/* Device-level header files */ -#include "decoder_library_utils.h" -#include "module_manager.h" - -/* FPGA-X2P context header files */ -#include "spice_types.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -/* FPGA-Verilog context header files */ -#include "verilog_global.h" -#include "verilog_writer_utils.h" -#include "verilog_decoders.h" - -/*************************************************************************************** - * Create a Verilog module for a decoder with a given output size - * - * Inputs - * | | ... | - * v v v - * +-----------+ - * / \ - * / Decoder \ - * +-----------------+ - * | | | ... | | | - * v v v v v v - * Outputs - * - * The outputs are assumes to be one-hot codes (at most only one '1' exist) - * Considering this fact, there are only num_of_outputs conditions to be encoded. - * Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2)) - ***************************************************************************************/ -static -void print_verilog_mux_local_decoder_module(std::fstream& fp, - ModuleManager& module_manager, - const DecoderLibrary& decoder_lib, - const DecoderId& decoder) { - /* Get the number of inputs */ - size_t addr_size = decoder_lib.addr_size(decoder); - size_t data_size = decoder_lib.data_size(decoder); - - /* Validate the FILE handler */ - check_file_handler(fp); - - /* TODO: create a name for the local encoder */ - std::string module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.find_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(module_id)); - /* Add module ports */ - /* Add each input port */ - BasicPort addr_port(generate_mux_local_decoder_addr_port_name(), addr_size); - /* Add each output port */ - BasicPort data_port(generate_mux_local_decoder_data_port_name(), data_size); - /* Data port is registered. It should be outputted as - * output reg [lsb:msb] data - */ - /* Add data_in port */ - BasicPort data_inv_port(generate_mux_local_decoder_data_inv_port_name(), data_size); - VTR_ASSERT(true == decoder_lib.use_data_inv_port(decoder)); - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish dumping ports */ - - print_verilog_comment(fp, std::string("----- BEGIN Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----")); - - /* Print the truth table of this decoder */ - /* Internal logics */ - /* Early exit: Corner case for data size = 1 the logic is very simple: - * data = addr; - * data_inv = ~data_inv - */ - if (1 == data_size) { - print_verilog_wire_connection(fp, data_port, addr_port, false); - print_verilog_wire_connection(fp, data_inv_port, addr_port, true); - print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----")); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); - return; - } - - /* We use a magic number -1 as the addr=1 should be mapped to ...1 - * Otherwise addr will map addr=1 to ..10 - * Note that there should be a range for the shift operators - * We should narrow the encoding to be applied to a given set of data - * This will lead to that any addr which falls out of the op code of data - * will give a all-zero code - * For example: - * data is 5-bit while addr is 3-bit - * data=8'b0_0000 will be encoded to addr=3'b001; - * data=8'b0_0001 will be encoded to addr=3'b010; - * data=8'b0_0010 will be encoded to addr=3'b011; - * data=8'b0_0100 will be encoded to addr=3'b100; - * data=8'b0_1000 will be encoded to addr=3'b101; - * data=8'b1_0000 will be encoded to addr=3'b110; - * The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000; - */ - - fp << "\t" << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl; - fp << "\t" << "case (" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl; - /* Create a string for addr and data */ - for (size_t i = 0; i < data_size; ++i) { - /* TODO: give a namespace to the itobin function */ - fp << "\t\t" << generate_verilog_constant_values(my_itobin_vec(i, addr_size)); - fp << " : "; - fp << generate_verilog_port_constant_values(data_port, my_ito1hot_vec(i, data_size)); - fp << ";" << std::endl; - } - fp << "\t\t" << "default : "; - fp << generate_verilog_port_constant_values(data_port, my_ito1hot_vec(data_size - 1, data_size)); - fp << ";" << std::endl; - fp << "\t" << "endcase" << std::endl; - - print_verilog_wire_connection(fp, data_inv_port, data_port, true); - - print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----")); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); - - return; -} - - -/*************************************************************************************** - * This function will generate all the unique Verilog modules of local decoders for - * the multiplexers used in a FPGA fabric - * It will reach the goal in two steps: - * 1. Find the unique local decoders w.r.t. the number of inputs/outputs - * We will generate the subgraphs from the multiplexing graph of each multiplexers - * The number of memory bits is the number of outputs. - * From that we can infer the number of inputs of each local decoders. - * Here is an illustrative example of how local decoders are interfaced with multi-level MUXes - * - * +---------+ +---------+ - * | Local | | Local | - * | Decoder | | Decoder | - * | A | | B | - * +---------+ +---------+ - * | ... | | ... | - * v v v v - * +--------------+ +--------------+ - * | MUX Level 0 |--->| MUX Level 1 | - * +--------------+ +--------------+ - * 2. Generate local decoder Verilog modules using behavioral description. - * Note that the implementation of local decoders can be dependent on the technology - * and standard cell libraries. - * Therefore, behavioral Verilog is used and the local decoders should be synthesized - * before running the back-end flow for FPGA fabric - * See more details in the function print_verilog_mux_local_decoder() for more details - ***************************************************************************************/ -void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, - std::vector& netlist_names, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, - const std::string& submodule_dir) { - std::string verilog_fname(submodule_dir + local_encoder_verilog_file_name); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Print out debugging information for if the file is not opened/created properly */ - vpr_printf(TIO_MESSAGE_INFO, - "Creating Verilog netlist for local decoders for multiplexers (%s)...\n", - verilog_fname.c_str()); - - print_verilog_file_header(fp, "Local Decoders for Multiplexers"); - - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Create a library for local encoders with different sizes */ - DecoderLibrary decoder_lib; - - /* Find unique local decoders for unique branches shared by the multiplexers */ - for (auto mux : mux_lib.muxes()) { - /* Local decoders are need only when users specify them */ - CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); - /* If this MUX does not need local decoder, we skip it */ - if (false == circuit_lib.mux_use_local_encoder(mux_circuit_model)) { - continue; - } - - const MuxGraph& mux_graph = mux_lib.mux_graph(mux); - /* Create a mux graph for the branch circuit */ - std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); - /* Add the decoder to the decoder library */ - for (auto branch_mux_graph : branch_mux_graphs) { - /* The decoder size depends on the number of memories of a branch MUX. - * Note that only when there are >=2 memories, a decoder is needed - */ - size_t decoder_data_size = branch_mux_graph.num_memory_bits(); - if (0 == decoder_data_size) { - continue; - } - /* Try to find if the decoder already exists in the library, - * If there is no such decoder, add it to the library - */ - add_mux_local_decoder_to_library(decoder_lib, decoder_data_size); - } - } - - /* Generate Verilog modules for the found unique local encoders */ - for (const auto& decoder : decoder_lib.decoders()) { - print_verilog_mux_local_decoder_module(fp, module_manager, decoder_lib, decoder); - } - - /* Close the file stream */ - fp.close(); - - - /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); -} - -/*************************************************************************************** - * For scan-chain configuration organization: - * Generate the Verilog module of configuration module - * which connect configuration ports to SRAMs/CCFFs in a chain: - * - * +------+ +------+ +------+ - * cc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out - * +------+ +------+ +------+ - ***************************************************************************************/ -static -void print_verilog_scan_chain_config_module(ModuleManager& module_manager, - std::fstream& fp, - t_sram_orgz_info* cur_sram_orgz_info) { - /* Validate the FILE handler */ - check_file_handler(fp); - - /* Get the total memory bits */ - int num_mem_bits = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); - - /* Create a module definition for the configuration chain */ - print_verilog_comment(fp, std::string("----- BEGIN Configuration Peripheral for Scan-chain FFs -----")); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(std::string(verilog_config_peripheral_prefix)); - VTR_ASSERT(ModuleId::INVALID() != module_id); - /* Add module ports */ - /* Add the head of scan-chain: a 1-bit input port */ - BasicPort sc_head_port(std::string(top_netlist_scan_chain_head_prefix), 1); - module_manager.add_port(module_id, sc_head_port, ModuleManager::MODULE_INPUT_PORT); - /* Add the inputs of scan-chain FFs, which are the outputs of the module */ - BasicPort cc_input_port(std::string("chain_input"), num_mem_bits); - module_manager.add_port(module_id, cc_input_port, ModuleManager::MODULE_OUTPUT_PORT); - /* Add the outputs of scan-chain FFs, which are inputs of the module */ - BasicPort sc_output_port(std::string("chain_output"), num_mem_bits); - module_manager.add_port(module_id, sc_output_port, ModuleManager::MODULE_INPUT_PORT); - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish dumping ports */ - - /* Declare the sc_output_port is a wire */ - fp << generate_verilog_port(VERILOG_PORT_WIRE, sc_output_port) << ";" << std::endl; - fp << std::endl; - - /* Connect scan-chain input to the first scan-chain input */ - BasicPort sc_first_input_port(cc_input_port.get_name(), 1); - print_verilog_wire_connection(fp, sc_first_input_port, sc_head_port, false); - - /* Connect the head of current ccff to the tail of previous ccff*/ - BasicPort chain_output_port(cc_input_port.get_name(), 1, num_mem_bits - 1); - BasicPort chain_input_port(sc_output_port.get_name(), 0, num_mem_bits - 2); - print_verilog_wire_connection(fp, chain_output_port, chain_input_port, false); - - print_verilog_comment(fp, std::string("----- END Configuration Peripheral for Scan-chain FFs -----")); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_manager.module_name(module_id)); - - return; -} - -/*************************************************************************************** - * Generate the configuration peripheral circuits for the top-level Verilog netlist - * This function will create Verilog modules depending on the configuration scheme: - * 1. Scan-chain: - * It will create a module which connects the Scan-Chain Flip-Flops (CCFFs) - * as a chain: - * - * +------+ +------+ +------+ - * cc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out - * +------+ +------+ +------+ - * - * 2. Memory bank: - * It will create a BL decoder and a WL decoder which will configure the SRAMs - * as a memory bank - * - * +------------------------+ - * | WL Decoder | - * +------------------------+ - * | | | ... | | - * v v v v v - * +---------+ +------------------------+ - * | |--->| | - * | | | | - * | BL |--->| | - * | Decoder | .. | FPGA Core logic | - * | | .. | | - * | |--->| | - * +---------+ +------------------------+ - ***************************************************************************************/ -void print_verilog_config_peripherals(ModuleManager& module_manager, - t_sram_orgz_info* cur_sram_orgz_info, - const std::string& verilog_dir, - const std::string& submodule_dir) { - std::string verilog_fname(submodule_dir + config_peripheral_verilog_file_name); - verilog_fname += ".bak"; - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Print out debugging information for if the file is not opened/created properly */ - vpr_printf(TIO_MESSAGE_INFO, - "Creating Verilog netlist for configuration peripherals (%s)...\n", - verilog_fname.c_str()); - - print_verilog_file_header(fp, "Configuration Peripheral Circuits"); - - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Create a library for decoders */ - DecoderLibrary decoder_lib; - - switch(cur_sram_orgz_info->type) { - case SPICE_SRAM_STANDALONE: - break; - case SPICE_SRAM_SCAN_CHAIN: - print_verilog_scan_chain_config_module(module_manager, fp, cur_sram_orgz_info); - break; - case SPICE_SRAM_MEMORY_BANK: - /* TODO: Finish refactoring this part after the sram_orgz_info ! */ - /* - dump_verilog_decoder(fp, cur_sram_orgz_info); - dump_verilog_membank_config_module(fp, cur_sram_orgz_info); - */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Close the file stream */ - fp.close(); - - /* Add fname to the linked list when debugging is finished */ - /* TODO: uncomment this when it is ready to be plugged-in - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); - */ - - return; -} - - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h deleted file mode 100644 index 418b4a4ae..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h +++ /dev/null @@ -1,32 +0,0 @@ -/*************************************************************************************** - * Header file for verilog_decoders.cpp - ***************************************************************************************/ -/* TODO: merge to verilog_decoder.h */ - -#ifndef VERILOG_DECODERS_H -#define VERILOG_DECODERS_H - -/* Include other header files which are dependency on the function declared below */ -#include -#include -#include - -#include "vpr_types.h" -#include "circuit_library.h" -#include "mux_graph.h" -#include "mux_library.h" -#include "module_manager.h" - -void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, - std::vector& netlist_names, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, - const std::string& submodule_dir); - -void print_verilog_config_peripherals(ModuleManager& module_manager, - t_sram_orgz_info* cur_sram_orgz_info, - const std::string& verilog_dir, - const std::string& submodule_dir); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp deleted file mode 100644 index fc353f725..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ /dev/null @@ -1,581 +0,0 @@ -/************************************************ - * This file includes functions on - * outputting Verilog netlists for essential gates - * which are inverters, buffers, transmission-gates - * logic gates etc. - ***********************************************/ -#include -#include "vtr_assert.h" - -/* Device-level header files */ -#include "spice_types.h" -#include "device_port.h" - -/* FPGA-X2P context header files */ -#include "fpga_x2p_utils.h" -#include "fpga_x2p_naming.h" -#include "module_manager.h" -#include "module_manager_utils.h" - -/* FPGA-Verilog context header files */ -#include "verilog_global.h" -#include "verilog_writer_utils.h" -#include "verilog_submodule_utils.h" -#include "verilog_essential_gates.h" - -/************************************************ - * Print Verilog body codes of a power-gated inverter - * This function does NOT generate any port map ! - ***********************************************/ -static -void print_verilog_power_gated_invbuf_body(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const CircuitPortId& input_port, - const CircuitPortId& output_port, - const std::vector& power_gate_ports) { - /* Ensure a valid file handler*/ - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- Verilog codes of a power-gated inverter -----")); - - /* Create a sensitive list */ - fp << "\treg " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl; - - fp << "\talways @(" << std::endl; - /* Power-gate port first*/ - for (const auto& power_gate_port : power_gate_ports) { - /* Skip first comma to dump*/ - if (0 < &power_gate_port - &power_gate_ports[0]) { - fp << ","; - } - fp << circuit_lib.port_prefix(power_gate_port); - } - fp << circuit_lib.port_prefix(input_port) << ") begin" << std::endl; - - /* Dump the case of power-gated */ - fp << "\t\tif ("; - /* For the first pin, we skip output comma */ - size_t port_cnt = 0; - for (const auto& power_gate_port : power_gate_ports) { - for (const auto& power_gate_pin : circuit_lib.pins(power_gate_port)) { - if (0 < port_cnt) { - fp << std::endl << "\t\t&&"; - } - fp << "("; - - /* Power-gated signal are disable during operating, enabled during configuration, - * Therefore, we need to reverse them here - */ - if (0 == circuit_lib.port_default_value(power_gate_port)) { - fp << "~"; - } - - fp << circuit_lib.port_prefix(power_gate_port) << "[" << power_gate_pin << "])"; - - port_cnt++; /* Update port counter*/ - } - } - - fp << ") begin" << std::endl; - fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = "; - - /* Branch on the type of inverter/buffer: - * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, - * we invert the input to output - * 2. If this is a buffer or an tapere(multi-stage) buffer with even number of stages, - * we wire the input to output - */ - if ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) - || ( (SPICE_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model)) - && (size_t(-1) != circuit_lib.buffer_num_levels(circuit_model)) - && (1 == circuit_lib.buffer_num_levels(circuit_model) % 2 ) ) ) { - fp << "~"; - } - - fp << circuit_lib.port_prefix(input_port) << ";" << std::endl; - fp << "\t\tend else begin" << std::endl; - fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = 1'bz;" << std::endl; - fp << "\t\tend" << std::endl; - fp << "\tend" << std::endl; - fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl; -} - -/************************************************ - * Print Verilog body codes of a regular inverter - * This function does NOT generate any port map ! - ***********************************************/ -static -void print_verilog_invbuf_body(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const CircuitPortId& input_port, - const CircuitPortId& output_port) { - /* Ensure a valid file handler*/ - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- Verilog codes of a regular inverter -----")); - - fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = (" << circuit_lib.port_prefix(input_port) << " === 1'bz)? $random : "; - - /* Branch on the type of inverter/buffer: - * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, - * we invert the input to output - * 2. If this is a buffer or an tapere(multi-stage) buffer with even number of stages, - * we wire the input to output - */ - if ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) - || ( (SPICE_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model)) - && (size_t(-1) != circuit_lib.buffer_num_levels(circuit_model)) - && (1 == circuit_lib.buffer_num_levels(circuit_model) % 2 ) ) ) { - fp << "~"; - } - - fp << circuit_lib.port_prefix(input_port) << ";" << std::endl; -} - -/************************************************ - * Print a Verilog module of inverter or buffer - * or tapered buffer to a file - ***********************************************/ -static -void print_verilog_invbuf_module(ModuleManager& module_manager, - std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - /* Ensure a valid file handler*/ - check_file_handler(fp); - - /* Find the input port, output port and global inputs*/ - std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); - - /* Make sure: - * There is only 1 input port and 1 output port, - * each size of which is 1 - */ - VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) ); - VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); - - /* TODO: move the check codes to check_circuit_library.h */ - /* If the circuit model is power-gated, we need to find at least one global config_enable signals */ - if (true == circuit_lib.is_power_gated(circuit_model)) { - /* Check all the ports we have are good for a power-gated circuit model */ - size_t num_err = 0; - /* We need at least one global port */ - if (0 == global_ports.size()) { - num_err++; - } - /* All the global ports should be config_enable */ - for (const auto& port : global_ports) { - if (false == circuit_lib.port_is_config_enable(port)) { - num_err++; - } - } - /* Report errors if there are any */ - if (0 < num_err) { - vpr_printf(TIO_MESSAGE_ERROR, - "Inverter/buffer circuit model (name=%s) is power-gated. At least one config-enable global port is required!\n", - circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - } - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model)); - VTR_ASSERT(true == module_manager.valid_module_id(module_id)); - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish dumping ports */ - - /* Assign logics : depending on topology */ - /* Error out for unsupported technology */ - if ( ( SPICE_MODEL_BUF_INV != circuit_lib.buffer_type(circuit_model)) - && ( SPICE_MODEL_BUF_BUF != circuit_lib.buffer_type(circuit_model)) ) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - - if (TRUE == circuit_lib.is_power_gated(circuit_model)) { - /* Output Verilog codes for a power-gated inverter */ - print_verilog_power_gated_invbuf_body(fp, circuit_lib, circuit_model, input_ports[0], output_ports[0], global_ports); - } else { - /* Output Verilog codes for a regular inverter */ - print_verilog_invbuf_body(fp, circuit_lib, circuit_model, input_ports[0], output_ports[0]); - } - - /* Print timing info */ - print_verilog_submodule_timing(fp, circuit_lib, circuit_model); - - /* Print signal initialization */ - print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); - - return; -} - -/************************************************ - * Print a Verilog module of a pass-gate, - * either transmission-gate or pass-transistor - ***********************************************/ -static -void print_verilog_passgate_module(ModuleManager& module_manager, - std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - /* Ensure a valid file handler*/ - check_file_handler(fp); - - /* Find the input port, output port*/ - std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); - - switch (circuit_lib.pass_gate_logic_type(circuit_model)) { - case SPICE_MODEL_PASS_GATE_TRANSMISSION: - /* Make sure: - * There is only 3 input port (in, sel, selb), - * each size of which is 1 - */ - VTR_ASSERT( 3 == input_ports.size() ); - for (const auto& input_port : input_ports) { - VTR_ASSERT(1 == circuit_lib.port_size(input_port)); - } - break; - case SPICE_MODEL_PASS_GATE_TRANSISTOR: - /* Make sure: - * There is only 2 input port (in, sel), - * each size of which is 1 - */ - VTR_ASSERT( 2 == input_ports.size() ); - for (const auto& input_port : input_ports) { - VTR_ASSERT(1 == circuit_lib.port_size(input_port)); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - - /* Make sure: - * There is only 1 output port, - * each size of which is 1 - */ - VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model)); - VTR_ASSERT(true == module_manager.valid_module_id(module_id)); - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish dumping ports */ - - /* Dump logics: we propagate input to the output when the gate is '1' - * the input is blocked from output when the gate is '0' - */ - fp << "\tassign " << circuit_lib.port_prefix(output_ports[0]) << " = "; - fp << circuit_lib.port_prefix(input_ports[1]) << " ? " << circuit_lib.port_prefix(input_ports[0]); - fp << " : 1'bz;" << std::endl; - - /* Print timing info */ - print_verilog_submodule_timing(fp, circuit_lib, circuit_model); - - /* Print signal initialization */ - print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); -} - -/************************************************ - * Print Verilog body codes of an N-input AND gate - ***********************************************/ -static -void print_verilog_and_or_gate_body(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const std::vector& input_ports, - const std::vector& output_ports) { - /* Ensure a valid file handler*/ - check_file_handler(fp); - - /* Find the logic operator for the gate */ - std::string gate_verilog_operator; - switch (circuit_lib.gate_type(circuit_model)) { - case SPICE_MODEL_GATE_AND: - gate_verilog_operator = "&"; - break; - case SPICE_MODEL_GATE_OR: - gate_verilog_operator = "|"; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - - /* Output verilog codes */ - print_verilog_comment(fp, std::string("----- Verilog codes of a " + std::to_string(input_ports.size()) + "-input " + std::to_string(output_ports.size()) + "-output AND gate -----")); - - for (const auto& output_port : output_ports) { - for (const auto& output_pin : circuit_lib.pins(output_port)) { - BasicPort output_port_info(circuit_lib.port_prefix(output_port), output_pin, output_pin); - fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, output_port_info); - fp << " = "; - - size_t port_cnt = 0; - for (const auto& input_port : input_ports) { - for (const auto& input_pin : circuit_lib.pins(input_port)) { - /* Do not output AND/OR operator for the first element in the loop */ - if (0 < port_cnt) { - fp << " " << gate_verilog_operator << " "; - } - - BasicPort input_port_info(circuit_lib.port_prefix(input_port), input_pin, input_pin); - fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); - - /* Increment the counter for port */ - port_cnt++; - } - } - fp << ";" << std::endl; - } - } -} - -/************************************************ - * Print Verilog body codes of an 2-input MUX gate - ***********************************************/ -static -void print_verilog_mux2_gate_body(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const std::vector& input_ports, - const std::vector& output_ports) { - /* Ensure a valid file handler*/ - check_file_handler(fp); - - /* TODO: Move the check codes to check_circuit_library.cpp */ - size_t num_err = 0; - /* Check on the port sequence and map */ - /* MUX2 should only have 1 output port with size 1 */ - if (1 != output_ports.size()) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) MUX2 circuit model (%s) must have only 1 output!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - num_err++; - } - for (const auto& output_port : output_ports) { - /* Bypass port size of 1 */ - if (1 == circuit_lib.port_size(output_port)) { - continue; - } - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Output port size of a MUX2 circuit model (%s) must be 1!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - num_err++; - } - /* MUX2 should only have 3 output port, each of which has a port size of 1 */ - if (3 != input_ports.size()) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) MUX2 circuit model (%s) must have only 3 input!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - num_err++; - } - - for (const auto& input_port : input_ports) { - /* Bypass port size of 1 */ - if (1 == circuit_lib.port_size(input_port)) { - continue; - } - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Input size MUX2 circuit model (%s) must be 1!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - num_err++; - } - if (0 < num_err) { - exit(1); - } - - /* Now, we output the logic of MUX2 - * IMPORTANT Restriction: - * We always assum the first two inputs are data inputs - * the third input is the select port - */ - fp << "\tassign "; - BasicPort out_port_info(circuit_lib.port_prefix(output_ports[0]), 0, 0); - BasicPort sel_port_info(circuit_lib.port_prefix(input_ports[2]), 0, 0); - BasicPort in0_port_info(circuit_lib.port_prefix(input_ports[0]), 0, 0); - BasicPort in1_port_info(circuit_lib.port_prefix(input_ports[1]), 0, 0); - - fp << generate_verilog_port(VERILOG_PORT_CONKT, out_port_info); - fp << " = "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, sel_port_info); - fp << " ? "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, in0_port_info); - fp << " : "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, in1_port_info); - fp << ";" << std::endl; -} - -/************************************************ - * Print a Verilog module of a logic gate - * which are standard cells - * Supported gate types: - * 1. N-input AND - * 2. N-input OR - * 3. 2-input MUX - ***********************************************/ -static -void print_verilog_gate_module(ModuleManager& module_manager, - std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - /* Ensure a valid file handler*/ - check_file_handler(fp); - - /* Find the input port, output port*/ - std::vector input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - std::vector output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); - - /* Make sure: - * There is only 1 output port, - * each size of which is 1 - */ - VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) ); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model)); - VTR_ASSERT(true == module_manager.valid_module_id(module_id)); - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - /* Finish dumping ports */ - - /* Dump logics */ - switch (circuit_lib.gate_type(circuit_model)) { - case SPICE_MODEL_GATE_AND: - case SPICE_MODEL_GATE_OR: - print_verilog_and_or_gate_body(fp, circuit_lib, circuit_model, input_ports, output_ports); - break; - case SPICE_MODEL_GATE_MUX2: - print_verilog_mux2_gate_body(fp, circuit_lib, circuit_model, input_ports, output_ports); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - - /* Print timing info */ - print_verilog_submodule_timing(fp, circuit_lib, circuit_model); - - /* Print signal initialization */ - print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); -} - -/************************************************ - * Generate the Verilog netlist for a constant generator, - * i.e., either VDD or GND - ***********************************************/ -static -void print_verilog_constant_generator_module(const ModuleManager& module_manager, - std::fstream& fp, - const size_t& const_value) { - /* Find the module in module manager */ - std::string module_name = generate_const_value_module_name(const_value); - ModuleId const_val_module = module_manager.find_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(const_val_module)); - - /* Ensure a valid file handler*/ - check_file_handler(fp); - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, const_val_module); - /* Finish dumping ports */ - - /* Find the only output*/ - for (const ModulePortId& module_port_id : module_manager.module_ports(const_val_module)) { - BasicPort module_port = module_manager.module_port(const_val_module, module_port_id); - print_verilog_wire_constant_values(fp, module_port, std::vector(1, const_value)); - } - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); -} - -/************************************************ - * Generate the Verilog netlist for essential gates - * include inverters, buffers, transmission-gates, - * etc. - ***********************************************/ -void print_verilog_submodule_essentials(ModuleManager& module_manager, - std::vector& netlist_names, - const std::string& verilog_dir, - const std::string& submodule_dir, - const CircuitLibrary& circuit_lib) { - /* TODO: remove .bak when this part is completed and tested */ - std::string verilog_fname = submodule_dir + essentials_verilog_file_name; - - std::fstream fp; - - /* Create the file stream */ - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - /* Check if the file stream if valid or not */ - check_file_handler(fp); - - /* Create file */ - vpr_printf(TIO_MESSAGE_INFO, - "Generating Verilog netlist (%s) for essential gates...\n", - __FILE__, __LINE__, verilog_fname.c_str()); - - print_verilog_file_header(fp, "Essential gates"); - - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Print constant generators */ - /* VDD */ - print_verilog_constant_generator_module(module_manager, fp, 0); - /* GND */ - print_verilog_constant_generator_module(module_manager, fp, 1); - - for (const auto& circuit_model : circuit_lib.models()) { - /* By pass user-defined modules */ - if (!circuit_lib.model_verilog_netlist(circuit_model).empty()) { - continue; - } - if (SPICE_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { - print_verilog_invbuf_module(module_manager, fp, circuit_lib, circuit_model); - continue; - } - if (SPICE_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) { - print_verilog_passgate_module(module_manager, fp, circuit_lib, circuit_model); - continue; - } - if (SPICE_MODEL_GATE == circuit_lib.model_type(circuit_model)) { - print_verilog_gate_module(module_manager, fp, circuit_lib, circuit_model); - continue; - } - } - - /* Close file handler*/ - fp.close(); - - /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h deleted file mode 100644 index 6431d0390..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h +++ /dev/null @@ -1,21 +0,0 @@ -/************************************************ - * Header file for verilog_submodule_essential.cpp - * Include function declaration on - * outputting Verilog netlists for essential gates - * which are inverters, buffers, transmission-gates - * logic gates etc. - ***********************************************/ - -#ifndef VERILOG_ESSENTIAL_GATES_H -#define VERILOG_ESSENTIAL_GATES_H - -#include -#include "circuit_library.h" - -void print_verilog_submodule_essentials(ModuleManager& module_manager, - std::vector& netlist_names, - const std::string& verilog_dir, - const std::string& submodule_dir, - const CircuitLibrary& circuit_lib); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp deleted file mode 100644 index b52d41d43..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp +++ /dev/null @@ -1,265 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to generate a Verilog - * testbench for the top-level module (FPGA fabric), in purpose of - * running formal verification with random input vectors - *******************************************************************/ -#include -#include -#include -#include -#include - -/* Include external library headers*/ -#include "device_port.h" -#include "vtr_assert.h" -#include "util.h" - -/* Include VPR headers*/ - -/* Include FPGA-X2P headers*/ -#include "simulation_utils.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_benchmark_utils.h" - -/* Include FPGA Verilog headers*/ -#include "verilog_global.h" -#include "verilog_writer_utils.h" -#include "verilog_testbench_utils.h" -#include "verilog_formal_random_top_testbench.h" - -/******************************************************************** - * Local variables used only in this file - *******************************************************************/ -constexpr char* FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX = "_top_formal_verification_random_tb"; -constexpr char* FPGA_PORT_POSTFIX = "_gfpga"; -constexpr char* BENCHMARK_PORT_POSTFIX = "_bench"; -constexpr char* CHECKFLAG_PORT_POSTFIX = "_flag"; -constexpr char* DEFAULT_CLOCK_NAME = "clk"; -constexpr char* BENCHMARK_INSTANCE_NAME = "REF_DUT"; -constexpr char* FPGA_INSTANCE_NAME = "FPGA_DUT"; -constexpr char* ERROR_COUNTER = "nb_error"; -constexpr char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start"; -constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200; - -/******************************************************************** - * Print the module ports for the Verilog testbench - * using random vectors - * This function generates - * 1. the input ports to drive both input benchmark module and FPGA fabric module - * 2. the output ports for input benchmark module - * 3. the output ports for FPGA fabric module - * 4. the error checking ports - *******************************************************************/ -static -void print_verilog_top_random_testbench_ports(std::fstream& fp, - const std::string& circuit_name, - const std::vector& clock_port_names, - const std::vector& L_logical_blocks) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Print the declaration for the module */ - fp << "module " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ";" << std::endl; - - /* Create a clock port if the benchmark does not have one! - * The clock is used for counting and synchronizing input stimulus - */ - BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME)); - print_verilog_comment(fp, std::string("----- Default clock port is added here since benchmark does not contain one -------")); - fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, clock_port) << ";" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; - - print_verilog_testbench_shared_ports(fp, L_logical_blocks, - std::string(BENCHMARK_PORT_POSTFIX), - std::string(FPGA_PORT_POSTFIX), - std::string(CHECKFLAG_PORT_POSTFIX), - std::string(autochecked_simulation_flag)); - - /* Instantiate an integer to count the number of error - * and determine if the simulation succeed or failed - */ - print_verilog_comment(fp, std::string("----- Error counter -------")); - fp << "\tinteger " << ERROR_COUNTER << "= 0;" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Instanciate the input benchmark module - *******************************************************************/ -static -void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, - const std::string& reference_verilog_top_name, - const std::vector& L_logical_blocks) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(autochecked_simulation_flag)); - - print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------")); - - /* Do NOT use explicit port mapping here: - * VPR added a prefix of "out_" to the output ports of input benchmark - */ - print_verilog_testbench_benchmark_instance(fp, reference_verilog_top_name, - std::string(BENCHMARK_INSTANCE_NAME), - std::string(), - std::string(), - std::string(BENCHMARK_PORT_POSTFIX), L_logical_blocks, - false); - - print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Condition ends for the benchmark instanciation */ - print_verilog_endif(fp); - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Instanciate the FPGA fabric module - *******************************************************************/ -static -void print_verilog_random_testbench_fpga_instance(std::fstream& fp, - const std::string& circuit_name, - const std::vector& L_logical_blocks) { - /* Validate the file stream */ - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- FPGA fabric instanciation -------")); - - /* Always use explicit port mapping */ - print_verilog_testbench_benchmark_instance(fp, std::string(circuit_name + std::string(formal_verification_top_postfix)), - std::string(FPGA_INSTANCE_NAME), - std::string(formal_verification_top_module_port_postfix), - std::string(formal_verification_top_module_port_postfix), - std::string(FPGA_PORT_POSTFIX), L_logical_blocks, - true); - - print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------")); - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/********************************************************************* - * Top-level function in this file: - * Create a Verilog testbench using random input vectors - * The testbench consists of two modules, i.e., Design Under Test (DUT) - * 1. top-level module of FPGA fabric - * 2. top-level module of users' benchmark, - * i.e., the input benchmark of VPR flow - * +----------+ - * | FPGA | +------------+ - * +----->| Fabric |------>| | - * | | | | | - * | +----------+ | | - * | | Output | - * random_input_vectors -----+ | Vector |---->Functional correct? - * | | Comparator | - * | +-----------+ | | - * | | Input | | | - * +----->| Benchmark |----->| | - * +-----------+ +------------+ - * - * Same input vectors are given to drive both DUTs. - * The output vectors of the DUTs are compared to verify if they - * have the same functionality. - * A flag will be raised to indicate the result - ********************************************************************/ -void print_verilog_random_top_testbench(const std::string& circuit_name, - const std::string& verilog_fname, - const std::string& verilog_dir, - const std::vector& L_logical_blocks, - const t_syn_verilog_opts& fpga_verilog_opts, - const t_spice_params& simulation_parameters) { - vpr_printf(TIO_MESSAGE_INFO, - "Writing Random Testbench for FPGA Top-level Verilog netlist for %s...", - circuit_name.c_str()); - - /* Start time count */ - clock_t t_start = clock(); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - /* Validate the file stream */ - check_file_handler(fp); - - /* Generate a brief description on the Verilog file*/ - std::string title = std::string("FPGA Verilog Testbench for Formal Top-level netlist of Design: ") + circuit_name; - print_verilog_file_header(fp, title); - - /* Print preprocessing flags and external netlists */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(defines_verilog_simulation_file_name))); - - /* Preparation: find all the clock ports */ - std::vector clock_port_names = find_benchmark_clock_port_name(L_logical_blocks); - - /* Start of testbench */ - print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, L_logical_blocks); - - /* Call defined top-level module */ - print_verilog_random_testbench_fpga_instance(fp, circuit_name, L_logical_blocks); - - /* Call defined benchmark */ - print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, L_logical_blocks); - - /* Find clock port to be used */ - BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME)); - - /* Add stimuli for reset, set, clock and iopad signals */ - print_verilog_testbench_clock_stimuli(fp, simulation_parameters, - clock_port); - print_verilog_testbench_random_stimuli(fp, L_logical_blocks, - std::string(CHECKFLAG_PORT_POSTFIX), clock_port); - - print_verilog_testbench_check(fp, - std::string(autochecked_simulation_flag), - std::string(FORMAL_TB_SIM_START_PORT_NAME), - std::string(BENCHMARK_PORT_POSTFIX), - std::string(FPGA_PORT_POSTFIX), - std::string(CHECKFLAG_PORT_POSTFIX), - std::string(ERROR_COUNTER), - L_logical_blocks, clock_port_names, std::string(DEFAULT_CLOCK_NAME)); - - int simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME, - simulation_parameters.meas_params.sim_num_clock_cycle, - 1./simulation_parameters.stimulate_params.op_clock_freq, - verilog_sim_timescale); - - /* Add Icarus requirement */ - print_verilog_timeout_and_vcd(fp, - std::string(icarus_simulator_flag), - std::string(circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX)), - std::string(circuit_name + std::string("_formal.vcd")), - std::string(FORMAL_TB_SIM_START_PORT_NAME), - std::string(ERROR_COUNTER), - simulation_time); - - /* Testbench ends*/ - print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX)); - - /* Close the file stream */ - fp.close(); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.h deleted file mode 100644 index baab0d1e5..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef VERILOG_FORMAL_RANDOM_TOP_TESTBENCH -#define VERILOG_FORMAL_RANDOM_TOP_TESTBENCH - -#include -#include "vpr_types.h" -#include "spice_types.h" - -void print_verilog_random_top_testbench(const std::string& circuit_name, - const std::string& verilog_fname, - const std::string& verilog_dir, - const std::vector& L_logical_blocks, - const t_syn_verilog_opts& fpga_verilog_opts, - const t_spice_params& simulation_parameters); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c deleted file mode 100644 index c6d563c37..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c +++ /dev/null @@ -1,145 +0,0 @@ -/***********************************/ -/* Synthesizable Verilog Dumping */ -/* Xifan TANG, EPFL/LSI */ -/***********************************/ -#include -#include "spice_types.h" -#include "linkedlist.h" -#include "fpga_x2p_globals.h" -#include "verilog_global.h" - -char* verilog_netlist_file_postfix = ".v"; -float verilog_sim_timescale = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns -char* verilog_timing_preproc_flag = "ENABLE_TIMING"; // the flag to enable timing definition during compilation -char* verilog_signal_init_preproc_flag = "ENABLE_SIGNAL_INITIALIZATION"; // the flag to enable signal initialization during compilation -char* verilog_formal_verification_preproc_flag = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation -char* initial_simulation_flag = "INITIAL_SIMULATION"; // the flag to enable initial functional verification -char* autochecked_simulation_flag = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification -char* formal_simulation_flag = "FORMAL_SIMULATION"; // the flag to enable formal functional verification - -char* default_verilog_dir_name = "syn_verilogs/"; -char* default_src_dir_name = "SRC/"; -char* default_lb_dir_name = "lb/"; -char* default_rr_dir_name = "routing/"; -char* default_submodule_dir_name = "sub_module/"; -char* default_tcl_dir_name = "SCRIPTS/"; -char* default_sdc_dir_name = "SDC/"; -char* default_msim_dir_name = "MSIM/"; -char* default_snpsfm_dir_name = "SNPS_FM/"; -char* default_modelsim_dir_name = "msim_projects/"; -char* default_report_timing_rpt_dir_name = "RPT/"; -char* autocheck_testbench_postfix = "_autocheck"; - -char* modelsim_project_name_postfix = "_fpga_msim"; -char* modelsim_proc_script_name_postfix = "_proc.tcl"; -char* modelsim_top_script_name_postfix = "_runsim.tcl"; -char* modelsim_testbench_module_postfix = "_top_tb"; -char* modelsim_autocheck_testbench_module_postfix = "_autocheck_top_tb"; -char* modelsim_simulation_time_unit = "ms"; - -char* formal_verification_top_module_postfix = "_top_formal_verification"; -char* formal_verification_top_module_port_postfix = "_fm"; -char* formal_verification_top_module_uut_name = "U0_formal_verification"; - -// Formality script generation variables -char* formality_script_name_postfix = "_formality_script.tcl"; -char* formal_verification_top_postfix = "_top_formal_verification"; -// End of Formality script generation variables - -// Icarus variables and flag -char* icarus_simulator_flag = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches -// End of Icarus variables and flag - -char* verilog_top_postfix = "_top.v"; -char* formal_verification_verilog_file_postfix = "_top_formal_verification.v"; -char* top_testbench_verilog_file_postfix = "_top_tb.v"; /* !!! must be consist with the modelsim_testbench_module_postfix */ -char* autocheck_top_testbench_verilog_file_postfix = "_autocheck_top_tb.v"; /* !!! must be consist with the modelsim_autocheck_testbench_module_postfix */ -char* random_top_testbench_verilog_file_postfix = "_formal_random_top_tb.v"; -char* blif_testbench_verilog_file_postfix = "_blif_tb.v"; -char* defines_verilog_file_name = "fpga_defines.v"; -char* defines_verilog_simulation_file_name = "define_simulation.v"; -char* submodule_verilog_file_name = "sub_module.v"; -char* logic_block_verilog_file_name = "logic_blocks.v"; -char* luts_verilog_file_name = "luts.v"; -char* routing_verilog_file_name = "routing.v"; -char* muxes_verilog_file_name = "muxes.v"; -char* local_encoder_verilog_file_name = "local_encoder.v"; -char* memories_verilog_file_name = "memories.v"; -char* wires_verilog_file_name = "wires.v"; -char* essentials_verilog_file_name = "inv_buf_passgate.v"; -char* config_peripheral_verilog_file_name = "config_peripherals.v"; -char* user_defined_template_verilog_file_name = "user_defined_templates.v"; - -/* File names for Report Timing */ -char* trpt_sb_file_name = "report_timing_sb.tcl"; -char* trpt_routing_file_name = "report_timing_routing.tcl"; - -/* File names for SDC*/ -char* sdc_analysis_file_name = "fpga_top_analysis.sdc"; -char* sdc_break_loop_file_name = "break_loop.sdc"; -char* sdc_constrain_routing_chan_file_name = "routing_channels.sdc"; -char* sdc_constrain_cb_file_name = "cb.sdc"; -char* sdc_constrain_sb_file_name = "sb.sdc"; -char* sdc_clock_period_file_name = "clb_clock.sdc"; -char* sdc_constrain_pb_type_file_name = "clb_constraints.sdc"; -char* sdc_break_vertical_sbs_file_name = "break_horizontal_sbs.sdc"; /* We break the vertical to read the horizontal */ -char* sdc_break_horizontal_sbs_file_name = "break_vertical_sbs.sdc"; /* We break the horizontal to read the vertical */ -char* sdc_restore_vertical_sbs_file_name = "restore_horizontal_sbs.sdc"; /* We break the vertical to read the horizontal */ -char* sdc_restore_horizontal_sbs_file_name = "restore_vertical_sbs.sdc"; /* We break the horizontal to read the vertical */ - -char* verilog_mux_basis_posfix = "_basis"; -char* verilog_mux_special_basis_posfix = "_special_basis"; -char* verilog_mem_posfix = "_mem"; -char* verilog_config_peripheral_prefix = "config_peripheral"; - -/* Prefix for subckt Verilog netlists */ -char* grid_verilog_file_name_prefix = "grid_"; -char* chanx_verilog_file_name_prefix = "chanx_"; -char* chany_verilog_file_name_prefix = "chany_"; -char* sb_verilog_file_name_prefix = "sb_"; -char* cbx_verilog_file_name_prefix = "cbx_"; -char* cby_verilog_file_name_prefix = "cby_"; - -/* SRAM SPICE MODEL should be set as global*/ -t_spice_model* sram_verilog_model = NULL; - -/* Input and Output Pad spice model. should be set as global */ -t_spice_model* iopad_verilog_model = NULL; - -/* Linked-list that stores all the configuration bits */ -t_llist* conf_bits_head = NULL; - -/* Linked-list that stores submodule Verilog file mames */ -t_llist* grid_verilog_subckt_file_path_head = NULL; -t_llist* routing_verilog_subckt_file_path_head = NULL; -t_llist* submodule_verilog_subckt_file_path_head = NULL; - -int verilog_default_signal_init_value = 0; - -char* top_netlist_bl_enable_port_name = "en_bl"; -char* top_netlist_wl_enable_port_name = "en_wl"; -char* top_netlist_bl_data_in_port_name = "data_in"; -char* top_netlist_addr_bl_port_name = "addr_bl"; -char* top_netlist_addr_wl_port_name = "addr_wl"; -char* top_netlist_array_bl_port_name = "bl_bus"; -char* top_netlist_array_wl_port_name = "wl_bus"; -char* top_netlist_array_blb_port_name = "blb_bus"; -char* top_netlist_array_wlb_port_name = "wlb_bus"; -char* top_netlist_reserved_bl_port_postfix = "_reserved_bl"; -char* top_netlist_reserved_wl_port_postfix = "_reserved_wl"; -char* top_netlist_normal_bl_port_postfix = "_bl"; -char* top_netlist_normal_wl_port_postfix = "_wl"; -char* top_netlist_normal_blb_port_postfix = "_blb"; -char* top_netlist_normal_wlb_port_postfix = "_wlb"; -char* top_netlist_scan_chain_head_prefix = "cc_in"; - -char* top_tb_reset_port_name = "greset"; -char* top_tb_set_port_name = "gset"; -char* top_tb_prog_reset_port_name = "prog_reset"; -char* top_tb_prog_set_port_name = "prog_set"; -char* top_tb_config_done_port_name = "config_done"; -char* top_tb_op_clock_port_name = "op_clock"; -char* top_tb_prog_clock_port_name = "prog_clock"; -char* top_tb_inout_reg_postfix = "_reg"; -char* top_tb_clock_reg_postfix = "_reg"; - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h deleted file mode 100644 index 81b1b31a6..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.h +++ /dev/null @@ -1,161 +0,0 @@ -#ifndef VERILOG_GLOBAL_H -#define VERILOG_GLOBAL_H -/* global parameters for dumping synthesizable verilog */ - -#include -#include "linkedlist.h" -#include "spice_types.h" - -extern char* verilog_netlist_file_postfix; -extern float verilog_sim_timescale; -extern char* verilog_timing_preproc_flag; // the flag to enable timing definition during compilation -extern char* verilog_signal_init_preproc_flag; // the flag to enable signal initialization during compilation -extern char* verilog_formal_verification_preproc_flag; // the flag to enable formal verification during compilation -extern char* initial_simulation_flag; -extern char* autochecked_simulation_flag; -extern char* formal_simulation_flag; - -extern char* default_verilog_dir_name; -extern char* default_src_dir_name; -extern char* default_lb_dir_name; -extern char* default_rr_dir_name; -extern char* default_submodule_dir_name; -extern char* default_tcl_dir_name; -extern char* default_sdc_dir_name; -extern char* default_msim_dir_name; -extern char* default_snpsfm_dir_name; -extern char* default_modelsim_dir_name; -extern char* default_report_timing_rpt_dir_name; -extern char* autocheck_testbench_postfix; - -extern char* modelsim_project_name_postfix; -extern char* modelsim_proc_script_name_postfix; -extern char* modelsim_top_script_name_postfix; -extern char* modelsim_testbench_module_postfix; -extern char* modelsim_autocheck_testbench_module_postfix; -extern char* modelsim_simulation_time_unit; - -extern char* formal_verification_top_module_postfix; -extern char* formal_verification_top_module_port_postfix; -extern char* formal_verification_top_module_uut_name; - -// Formality script generation variables -extern char* formality_script_name_postfix; -extern char* formal_verification_top_postfix; -// End of Formality script generation variables - -// Icarus variables and flag -extern char* icarus_simulator_flag; -// End of Icarus variables and flag - -extern char* verilog_top_postfix; -extern char* formal_verification_verilog_file_postfix; -extern char* top_testbench_verilog_file_postfix; -extern char* autocheck_top_testbench_verilog_file_postfix; -extern char* random_top_testbench_verilog_file_postfix; -extern char* blif_testbench_verilog_file_postfix; -extern char* defines_verilog_file_name; -extern char* defines_verilog_simulation_file_name; -extern char* submodule_verilog_file_name; -extern char* logic_block_verilog_file_name; -extern char* luts_verilog_file_name; -extern char* routing_verilog_file_name; -extern char* muxes_verilog_file_name; -extern char* local_encoder_verilog_file_name; -extern char* memories_verilog_file_name; -extern char* wires_verilog_file_name; -extern char* essentials_verilog_file_name; -extern char* config_peripheral_verilog_file_name; -extern char* user_defined_template_verilog_file_name; - -extern char* trpt_sb_file_name; -extern char* trpt_routing_file_name; - -extern char* sdc_analysis_file_name; -extern char* sdc_break_loop_file_name; -extern char* sdc_clock_period_file_name; -extern char* sdc_constrain_routing_chan_file_name; -extern char* sdc_constrain_cb_file_name; -extern char* sdc_constrain_sb_file_name; -extern char* sdc_constrain_pb_type_file_name; -extern char* sdc_break_vertical_sbs_file_name; -extern char* sdc_break_horizontal_sbs_file_name; -extern char* sdc_restore_vertical_sbs_file_name; -extern char* sdc_restore_horizontal_sbs_file_name; - -extern char* verilog_mux_basis_posfix; -extern char* verilog_mux_special_basis_posfix; -extern char* verilog_mem_posfix; -extern char* verilog_config_peripheral_prefix; - -/* Prefix for subckt Verilog netlists */ -extern char* grid_verilog_file_name_prefix; -extern char* chanx_verilog_file_name_prefix; -extern char* chany_verilog_file_name_prefix; -extern char* sb_verilog_file_name_prefix; -extern char* cbx_verilog_file_name_prefix; -extern char* cby_verilog_file_name_prefix; - -extern t_spice_model* sram_verilog_model; - -/* Input and Output Pad spice model. should be set as global */ -extern t_spice_model* inpad_verilog_model; -extern t_spice_model* outpad_verilog_model; -extern t_spice_model* iopad_verilog_model; - -/* Linked-list that stores all the configuration bits */ -extern t_llist* conf_bits_head; - -/* Linked-list that stores submodule Verilog file mames */ -extern t_llist* grid_verilog_subckt_file_path_head; -extern t_llist* routing_verilog_subckt_file_path_head; -extern t_llist* submodule_verilog_subckt_file_path_head; - -extern int verilog_default_signal_init_value; - -extern char* top_netlist_bl_enable_port_name; -extern char* top_netlist_wl_enable_port_name; -extern char* top_netlist_bl_data_in_port_name; -extern char* top_netlist_addr_bl_port_name; -extern char* top_netlist_addr_wl_port_name; -extern char* top_netlist_array_bl_port_name; -extern char* top_netlist_array_wl_port_name; -extern char* top_netlist_array_blb_port_name; -extern char* top_netlist_array_wlb_port_name; -extern char* top_netlist_reserved_bl_port_postfix; -extern char* top_netlist_reserved_wl_port_postfix; -extern char* top_netlist_normal_bl_port_postfix; -extern char* top_netlist_normal_wl_port_postfix; -extern char* top_netlist_normal_blb_port_postfix; -extern char* top_netlist_normal_wlb_port_postfix; -extern char* top_netlist_scan_chain_head_prefix; - -extern char* top_tb_reset_port_name; -extern char* top_tb_set_port_name; -extern char* top_tb_prog_reset_port_name; -extern char* top_tb_prog_set_port_name; -extern char* top_tb_config_done_port_name; -extern char* top_tb_op_clock_port_name; -extern char* top_tb_prog_clock_port_name; -extern char* top_tb_inout_reg_postfix; -extern char* top_tb_clock_reg_postfix; - -enum e_dump_verilog_port_type { -VERILOG_PORT_INPUT, -VERILOG_PORT_OUTPUT, -VERILOG_PORT_INOUT, -VERILOG_PORT_WIRE, -VERILOG_PORT_REG, -VERILOG_PORT_CONKT, -NUM_VERILOG_PORT_TYPES -}; -constexpr std::array VERILOG_PORT_TYPE_STRING = {{"input", "output", "inout", "wire", "reg", ""}}; /* string version of enum e_verilog_port_type */ - -enum e_verilog_tb_type { -VERILOG_TB_TOP, -VERILOG_TB_BLIF_TOP, -VERILOG_TB_AUTOCHECK_TOP, -VERILOG_TB_FORMAL_VERIFICATION -}; - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp deleted file mode 100644 index b11731471..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ /dev/null @@ -1,322 +0,0 @@ -/******************************************************************** - * This file includes functions to print Verilog modules for a Grid - * (CLBs, I/Os, heterogeneous blocks etc.) - *******************************************************************/ -/* System header files */ -#include -#include - -/* Header files from external libs */ -#include "vtr_geometry.h" -#include "util.h" -#include "vtr_assert.h" -#include "circuit_library_utils.h" - -/* Header files for VPR */ -#include "vpr_types.h" -#include "globals.h" - -/* Header files for FPGA X2P tool suite */ -#include "fpga_x2p_naming.h" -#include "fpga_x2p_types.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_pbtypes_utils.h" -#include "module_manager_utils.h" -#include "fpga_x2p_globals.h" - -/* Header files for Verilog generator */ -#include "verilog_global.h" -#include "verilog_writer_utils.h" -#include "verilog_module_writer.h" -#include "verilog_grid.h" - -/******************************************************************** - * Print Verilog modules of a primitive node in the pb_graph_node graph - * This generic function can support all the different types of primitive nodes - * i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders. - * - * The Verilog module will consist of two parts: - * 1. Logic module of the primitive node - * This module performs the logic function of the block - * 2. Memory module of the primitive node - * This module stores the configuration bits for the logic module - * if the logic module is a programmable resource, such as LUT - * - * Verilog module structure: - * - * Primitive block - * +---------------------------------------+ - * | | - * | +---------+ +---------+ | - * in |----->| |--->| |<------|configuration lines - * | | Logic |... | Memory | | - * out|<-----| |--->| | | - * | +---------+ +---------+ | - * | | - * +---------------------------------------+ - * - *******************************************************************/ -static -void print_verilog_primitive_block(std::fstream& fp, - ModuleManager& module_manager, - t_pb_graph_node* primitive_pb_graph_node, - const e_side& io_side, - const bool& use_explicit_mapping) { - /* Ensure a valid file handler */ - check_file_handler(fp); - - /* Ensure a valid pb_graph_node */ - if (NULL == primitive_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid primitive_pb_graph_node!\n", - __FILE__, __LINE__); - exit(1); - } - - /* Generate the module name for this primitive pb_graph_node*/ - std::string primitive_module_name_prefix = generate_grid_block_prefix(std::string(grid_verilog_file_name_prefix), io_side); - std::string primitive_module_name = generate_physical_block_module_name(primitive_module_name_prefix, primitive_pb_graph_node->pb_type); - - /* Create a module of the primitive LUT and register it to module manager */ - ModuleId primitive_module = module_manager.find_module(primitive_module_name); - /* Ensure that the module has been created and thus unique! */ - VTR_ASSERT(true == module_manager.valid_module_id(primitive_module)); - - /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, primitive_module, use_explicit_mapping); - - /* Add an empty line as a splitter */ - fp << std::endl; -} - -/******************************************************************** - * Print Verilog modules of physical blocks inside a grid (CLB, I/O. etc.) - * This function will traverse the graph of complex logic block (t_pb_graph_node) - * in a recursive way, using a Depth First Search (DFS) algorithm. - * As such, primitive physical blocks (LUTs, FFs, etc.), leaf node of the pb_graph - * will be printed out first, while the top-level will be printed out in the last - * - * Note: this function will print a unique Verilog module for each type of - * t_pb_graph_node, i.e., t_pb_type, in the graph, in order to enable highly - * hierarchical Verilog organization as well as simplify the Verilog file sizes. - * - * Note: DFS is the right way. Do NOT use BFS. - * DFS can guarantee that all the sub-modules can be registered properly - * to its parent in module manager - *******************************************************************/ -static -void print_verilog_physical_blocks_rec(std::fstream& fp, - ModuleManager& module_manager, - t_pb_graph_node* physical_pb_graph_node, - const e_side& io_side, - const bool& use_explicit_mapping) { - /* Check the file handler*/ - check_file_handler(fp); - - /* Check cur_pb_graph_node*/ - if (NULL == physical_pb_graph_node) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d]) Invalid cur_pb_graph_node.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Get the pb_type definition related to the node */ - t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; - - /* Find the mode that physical implementation of a pb_type */ - int physical_mode_index = find_pb_type_physical_mode_index((*physical_pb_type)); - - /* For non-leaf node in the pb_type graph: - * Recursively Depth-First Generate all the child pb_type at the level - */ - if (FALSE == is_primitive_pb_type(physical_pb_type)) { - for (int ipb = 0; ipb < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ipb) { - /* Go recursive to visit the children */ - print_verilog_physical_blocks_rec(fp, module_manager, - &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][0]), - io_side, - use_explicit_mapping); - } - } - - /* For leaf node, a primitive Verilog module will be generated. - * Note that the primitive may be mapped to a standard cell, we force to use that - */ - if (TRUE == is_primitive_pb_type(physical_pb_type)) { - print_verilog_primitive_block(fp, module_manager, - physical_pb_graph_node, - io_side, - true); - /* Finish for primitive node, return */ - return; - } - - /* Generate the name of the Verilog module for this pb_type */ - std::string pb_module_name_prefix = generate_grid_block_prefix(std::string(grid_verilog_file_name_prefix), io_side); - std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, physical_pb_type); - - /* Register the Verilog module in module manager */ - ModuleId pb_module = module_manager.find_module(pb_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); - - /* Comment lines */ - print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); - - /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, pb_module, use_explicit_mapping); - - print_verilog_comment(fp, std::string("----- END Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----")); - - /* Add an empty line as a splitter */ - fp << std::endl; -} - -/***************************************************************************** - * This function will create a Verilog file and print out a Verilog netlist - * for a type of physical block - * - * For IO blocks: - * The param 'border_side' is required, which is specify which side of fabric - * the I/O block locates at. - *****************************************************************************/ -static -void print_verilog_grid(ModuleManager& module_manager, - std::vector& netlist_names, - const std::string& verilog_dir, - const std::string& subckt_dir, - t_type_ptr phy_block_type, - const e_side& border_side, - const bool& use_explicit_mapping) { - /* Check code: if this is an IO block, the border side MUST be valid */ - if (IO_TYPE == phy_block_type) { - VTR_ASSERT(NUM_SIDES != border_side); - } - - /* Give a name to the Verilog netlist */ - /* Create the file name for Verilog */ - std::string verilog_fname(subckt_dir - + generate_grid_block_netlist_name(std::string(phy_block_type->name), - IO_TYPE == phy_block_type, - border_side, - std::string(verilog_netlist_file_postfix)) - ); - /* TODO: remove the bak file when the file is ready */ - //verilog_fname += ".bak"; - - /* Echo status */ - if (IO_TYPE == phy_block_type) { - Side side_manager(border_side); - vpr_printf(TIO_MESSAGE_INFO, - "Writing FPGA Verilog Netlist (%s) for logic block %s at %s side ...\n", - verilog_fname.c_str(), phy_block_type->name, - side_manager.c_str()); - } else { - vpr_printf(TIO_MESSAGE_INFO, - "Writing FPGA Verilog Netlist (%s) for logic block %s...\n", - verilog_fname.c_str(), phy_block_type->name); - } - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - print_verilog_file_header(fp, std::string("Verilog modules for physical block: " + std::string(phy_block_type->name) + "]")); - - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Print Verilog modules for all the pb_types/pb_graph_nodes - * use a Depth-First Search Algorithm to print the sub-modules - * Note: DFS is the right way. Do NOT use BFS. - * DFS can guarantee that all the sub-modules can be registered properly - * to its parent in module manager - */ - print_verilog_comment(fp, std::string("---- BEGIN Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); - - /* Print Verilog modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */ - print_verilog_physical_blocks_rec(fp, module_manager, - phy_block_type->pb_graph_head, - border_side, - use_explicit_mapping); - - print_verilog_comment(fp, std::string("---- END Sub-module of physical block:" + std::string(phy_block_type->name) + " ----")); - - /* Create a Verilog Module for the top-level physical block, and add to module manager */ - std::string grid_module_name = generate_grid_block_module_name(std::string(grid_verilog_file_name_prefix), std::string(phy_block_type->name), IO_TYPE == phy_block_type, border_side); - ModuleId grid_module = module_manager.find_module(grid_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); - - /* Write the verilog module */ - print_verilog_comment(fp, std::string("----- BEGIN Grid Verilog module: " + module_manager.module_name(grid_module) + " -----")); - write_verilog_module_to_file(fp, module_manager, grid_module, use_explicit_mapping); - - print_verilog_comment(fp, std::string("----- END Grid Verilog module: " + module_manager.module_name(grid_module) + " -----")); - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Close file handler */ - fp.close(); - - /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); -} - -/***************************************************************************** - * Create logic block modules in a compact way: - * 1. Only one module for each I/O on each border side (IO_TYPE) - * 2. Only one module for each CLB (FILL_TYPE) - * 3. Only one module for each heterogeneous block - ****************************************************************************/ -void print_verilog_grids(ModuleManager& module_manager, - const std::string& verilog_dir, - const std::string& subckt_dir, - const bool& use_explicit_mapping) { - /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ - std::vector netlist_names; - - /* Enumerate the types, dump one Verilog module for each */ - for (int itype = 0; itype < num_types; itype++) { - if (EMPTY_TYPE == &type_descriptors[itype]) { - /* Bypass empty type or NULL */ - continue; - } else if (IO_TYPE == &type_descriptors[itype]) { - /* Special for I/O block, generate one module for each border side */ - for (int iside = 0; iside < NUM_SIDES; iside++) { - Side side_manager(iside); - print_verilog_grid(module_manager, netlist_names, - verilog_dir, subckt_dir, - &type_descriptors[itype], - side_manager.get_side(), - use_explicit_mapping); - } - continue; - } else if (FILL_TYPE == &type_descriptors[itype]) { - /* For CLB */ - print_verilog_grid(module_manager, netlist_names, - verilog_dir, subckt_dir, - &type_descriptors[itype], - NUM_SIDES, - use_explicit_mapping); - continue; - } else { - /* For heterogenenous blocks */ - print_verilog_grid(module_manager, netlist_names, - verilog_dir, subckt_dir, - &type_descriptors[itype], - NUM_SIDES, - use_explicit_mapping); - } - } - - /* Output a header file for all the logic blocks */ - vpr_printf(TIO_MESSAGE_INFO, "Generating header file for grid Verilog modules...\n"); - std::string grid_verilog_fname(logic_block_verilog_file_name); - print_verilog_netlist_include_header_file(netlist_names, - subckt_dir.c_str(), - grid_verilog_fname.c_str()); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.h deleted file mode 100644 index d1bc8cdfb..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.h +++ /dev/null @@ -1,18 +0,0 @@ -/******************************************************************** - * Header file for verilog_grid.cpp - *******************************************************************/ -#ifndef VERILOG_GRID_H -#define VERILOG_GRID_H - -/* Only include headers related to the data structures used in the following function declaration */ -#include -#include "vpr_types.h" -#include "module_manager.h" -#include "mux_library.h" - -void print_verilog_grids(ModuleManager& module_manager, - const std::string& verilog_dir, - const std::string& subckt_dir, - const bool& use_explicit_mapping); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp deleted file mode 100644 index 53126cec6..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp +++ /dev/null @@ -1,75 +0,0 @@ -/******************************************************************** - * This file includes functions to generate Verilog submodules for LUTs - ********************************************************************/ -#include -#include - -#include "util.h" -#include "vtr_assert.h" - -/* Device-level header files */ -#include "mux_graph.h" -#include "module_manager.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "mux_utils.h" - -/* FPGA-X2P context header files */ -#include "spice_types.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -/* FPGA-Verilog context header files */ -#include "verilog_writer_utils.h" -#include "verilog_module_writer.h" -#include "verilog_lut.h" - -/******************************************************************** - * Print Verilog modules for the Look-Up Tables (LUTs) - * in the circuit library - ********************************************************************/ -void print_verilog_submodule_luts(ModuleManager& module_manager, - std::vector& netlist_names, - const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, - const std::string& submodule_dir, - const bool& use_explicit_port_map) { - std::string verilog_fname = submodule_dir + luts_verilog_file_name; - - std::fstream fp; - - /* Create the file stream */ - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - /* Check if the file stream if valid or not */ - check_file_handler(fp); - - /* Create file */ - vpr_printf(TIO_MESSAGE_INFO, - "Generating Verilog netlist for LUTs (%s)...\n", - verilog_fname.c_str()); - - print_verilog_file_header(fp, "Look-Up Tables"); - - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Search for each LUT circuit model */ - for (const auto& lut_model : circuit_lib.models()) { - /* Bypass user-defined and non-LUT modules */ - if ( (!circuit_lib.model_verilog_netlist(lut_model).empty()) - || (SPICE_MODEL_LUT != circuit_lib.model_type(lut_model)) ) { - continue; - } - /* Find the module id */ - ModuleId lut_module = module_manager.find_module(circuit_lib.model_name(lut_model)); - VTR_ASSERT(true == module_manager.valid_module_id(lut_module)); - write_verilog_module_to_file(fp, module_manager, lut_module, - use_explicit_port_map || circuit_lib.dump_explicit_port_map(lut_model)); - } - - /* Close the file handler */ - fp.close(); - - /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h deleted file mode 100644 index f546b400f..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h +++ /dev/null @@ -1,22 +0,0 @@ -/*********************************************** - * Header file for verilog_lut.cpp - **********************************************/ - -#ifndef VERILOG_LUT_H -#define VERILOG_LUT_H - -/* Include other header files which are dependency on the function declared below */ -#include -#include - -#include "circuit_library.h" -#include "module_manager.h" - -void print_verilog_submodule_luts(ModuleManager& module_manager, - std::vector& netlist_names, - const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, - const std::string& submodule_dir, - const bool& use_explicit_port_map); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp deleted file mode 100644 index ea7cd8498..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp +++ /dev/null @@ -1,193 +0,0 @@ -/********************************************************************* - * This file includes functions to generate Verilog submodules for - * the memories that are affiliated to multiplexers and other programmable - * circuit models, such as IOPADs, LUTs, etc. - ********************************************************************/ -#include -#include - -#include "util.h" -#include "vtr_assert.h" - -/* Device-level header files */ -#include "mux_graph.h" -#include "module_manager.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "circuit_library_utils.h" -#include "mux_utils.h" - -/* FPGA-X2P context header files */ -#include "spice_types.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -/* FPGA-Verilog context header files */ -#include "verilog_global.h" -#include "verilog_writer_utils.h" -#include "verilog_module_writer.h" -#include "verilog_memory.h" - -/********************************************************************* - * Generate Verilog modules for the memories that are used - * by multiplexers - * - * +----------------+ - * mem_in --->| Memory Module |---> mem_out - * +----------------+ - * | | ... | | - * v v v v SRAM ports of multiplexer - * +---------------------+ - * in--->| Multiplexer Module |---> out - * +---------------------+ - ********************************************************************/ -static -void print_verilog_mux_memory_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph, - const bool& use_explicit_port_map) { - /* Multiplexers built with different technology is in different organization */ - switch (circuit_lib.design_tech_type(mux_model)) { - case SPICE_MODEL_DESIGN_CMOS: { - /* Generate module name */ - std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, - find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), - std::string(verilog_mem_posfix)); - ModuleId mem_module = module_manager.find_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); - /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, mem_module, - use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model)); - - /* Add an empty line as a splitter */ - fp << std::endl; - break; - } - case SPICE_MODEL_DESIGN_RRAM: - /* We do not need a memory submodule for RRAM MUX, - * RRAM are embedded in the datapath - * TODO: generate local encoders for RRAM-based multiplexers here!!! - */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", - __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); - exit(1); - } -} - - -/********************************************************************* - * Generate Verilog modules for - * the memories that are affiliated to multiplexers and other programmable - * circuit models, such as IOPADs, LUTs, etc. - * - * We keep the memory modules separated from the multiplexers and other - * programmable circuit models, for the sake of supporting - * various configuration schemes. - * By following such organiztion, the Verilog modules of the circuit models - * implements the functionality (circuit logic) only, while the memory Verilog - * modules implements the memory circuits as well as configuration protocols. - * For example, the local decoders of multiplexers are implemented in the - * memory modules. - * Take another example, the memory circuit can implement the scan-chain or - * memory-bank organization for the memories. - ********************************************************************/ -void print_verilog_submodule_memories(ModuleManager& module_manager, - std::vector& netlist_names, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, - const std::string& submodule_dir, - const bool& use_explicit_port_map) { - /* Plug in with the mux subckt */ - std::string verilog_fname(submodule_dir + memories_verilog_file_name); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Print out debugging information for if the file is not opened/created properly */ - vpr_printf(TIO_MESSAGE_INFO, - "Creating Verilog netlist for memories (%s) ...\n", - verilog_fname.c_str()); - - print_verilog_file_header(fp, "Memories used in FPGA"); - - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Create the memory circuits for the multiplexer */ - for (auto mux : mux_lib.muxes()) { - const MuxGraph& mux_graph = mux_lib.mux_graph(mux); - CircuitModelId mux_model = mux_lib.mux_circuit_model(mux); - /* Bypass the non-MUX circuit models (i.e., LUTs). - * They should be handled in a different way - * Memory circuits of LUT includes both regular and mode-select ports - */ - if (SPICE_MODEL_MUX != circuit_lib.model_type(mux_model)) { - continue; - } - /* Create a Verilog module for the memories used by the multiplexer */ - print_verilog_mux_memory_module(module_manager, circuit_lib, fp, mux_model, mux_graph, use_explicit_port_map); - } - - /* Create the memory circuits for non-MUX circuit models. - * In this case, the memory modules are designed to interface - * the mode-select ports - */ - for (const auto& model : circuit_lib.models()) { - /* Bypass MUXes, they have already been considered */ - if (SPICE_MODEL_MUX == circuit_lib.model_type(model)) { - continue; - } - /* Bypass those modules without any SRAM ports */ - std::vector sram_ports = circuit_lib.model_ports_by_type(model, SPICE_MODEL_PORT_SRAM, true); - if (0 == sram_ports.size()) { - continue; - } - /* Find the name of memory module */ - /* Get the total number of SRAMs */ - size_t num_mems = 0; - for (const auto& port : sram_ports) { - num_mems += circuit_lib.port_size(port); - } - /* Get the circuit model for the memory circuit used by the multiplexer */ - std::vector sram_models; - for (const auto& port : sram_ports) { - CircuitModelId sram_model = circuit_lib.port_tri_state_model(port); - VTR_ASSERT(CircuitModelId::INVALID() != sram_model); - /* Found in the vector of sram_models, do not update and go to the next */ - if (sram_models.end() != std::find(sram_models.begin(), sram_models.end(), sram_model)) { - continue; - } - /* sram_model not found in the vector, update the sram_models */ - sram_models.push_back(sram_model); - } - /* Should have only 1 SRAM model */ - VTR_ASSERT( 1 == sram_models.size() ); - - /* Create the module name for the memory block */ - std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(verilog_mem_posfix)); - - ModuleId mem_module = module_manager.find_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); - /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, mem_module, - use_explicit_port_map || circuit_lib.dump_explicit_port_map(model)); - - /* Add an empty line as a splitter */ - fp << std::endl; - } - - /* Close the file stream */ - fp.close(); - - /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h deleted file mode 100644 index 29387fccc..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h +++ /dev/null @@ -1,24 +0,0 @@ -/*********************************************** - * Header file for verilog_memory.cpp - **********************************************/ - -#ifndef VERILOG_MEMORY_H -#define VERILOG_MEMORY_H - -/* Include other header files which are dependency on the function declared below */ -#include - -#include "circuit_library.h" -#include "mux_graph.h" -#include "mux_library.h" -#include "module_manager.h" - -void print_verilog_submodule_memories(ModuleManager& module_manager, - std::vector& netlist_names, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, - const std::string& submodule_dir, - const bool& use_explicit_port_map); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp deleted file mode 100644 index a5cf3b59f..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp +++ /dev/null @@ -1,499 +0,0 @@ -/******************************************************************** - * This file includes functions to write a Verilog module - * based on its definition in Module Manager - * - * Note that Verilog writer functions are just an outputter for the - * module definition. - * You should NOT modify any content of the module manager - * Please use const keyword to restrict this! - *******************************************************************/ -#include -#include "vtr_assert.h" -#include "fpga_x2p_utils.h" -#include "module_manager_utils.h" -#include "verilog_writer_utils.h" -#include "verilog_module_writer.h" - -/******************************************************************** - * Generate the name of a local wire for a undriven port inside Verilog - * module - *******************************************************************/ -static -std::string generate_verilog_undriven_local_wire_name(const ModuleManager& module_manager, - const ModuleId& parent, - const ModuleId& child, - const size_t& instance_id, - const ModulePortId& child_port_id) { - std::string wire_name; - if (!module_manager.instance_name(parent, child, instance_id).empty()) { - wire_name = module_manager.instance_name(parent, child, instance_id); - } else { - wire_name = module_manager.module_name(parent) + std::string("_") + std::to_string(instance_id); - wire_name += std::string("_"); - } - - wire_name += module_manager.module_port(child, child_port_id).get_name(); - - return wire_name; -} - -/******************************************************************** - * Name a net for a local wire for a verilog module - * 1. If this is a local wire, name it after the __ - * 2. If this is not a local wire, name it after the port name of parent module - * - * In addition, it will assign the pin index as well - * - * Restriction: this function requires each net has single driver - * which is definitely always true in circuits. - *******************************************************************/ -static -BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manager, - const ModuleId& module_id, - const ModuleNetId& module_net) { - /* Check all the sink modules of the net, - * if we have a source module is the current module, this is not local wire - */ - for (ModuleNetSrcId src_id : module_manager.module_net_sources(module_id, module_net)) { - if (module_id == module_manager.net_source_modules(module_id, module_net)[src_id]) { - /* Here, this is not a local wire, return the port name of the src_port */ - ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[src_id]; - size_t src_pin_index = module_manager.net_source_pins(module_id, module_net)[src_id]; - return BasicPort(module_manager.module_port(module_id, net_src_port).get_name(), src_pin_index, src_pin_index); - } - } - - /* Check all the sink modules of the net */ - for (ModuleNetSinkId sink_id : module_manager.module_net_sinks(module_id, module_net)) { - if (module_id == module_manager.net_sink_modules(module_id, module_net)[sink_id]) { - /* Here, this is not a local wire, return the port name of the sink_port */ - ModulePortId net_sink_port = module_manager.net_sink_ports(module_id, module_net)[sink_id]; - size_t sink_pin_index = module_manager.net_sink_pins(module_id, module_net)[sink_id]; - return BasicPort(module_manager.module_port(module_id, net_sink_port).get_name(), sink_pin_index, sink_pin_index); - } - } - - /* Reach here, this is a local wire */ - std::string net_name; - - /* Each net must only one 1 source */ - VTR_ASSERT(1 == module_manager.net_source_modules(module_id, module_net).size()); - - /* Get the source module */ - ModuleId net_src_module = module_manager.net_source_modules(module_id, module_net)[ModuleNetSrcId(0)]; - /* Get the instance id */ - size_t net_src_instance = module_manager.net_source_instances(module_id, module_net)[ModuleNetSrcId(0)]; - /* Get the port id */ - ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[ModuleNetSrcId(0)]; - /* Get the pin id */ - size_t net_src_pin = module_manager.net_source_pins(module_id, module_net)[ModuleNetSrcId(0)]; - - /* Load user-defined name if we have it */ - if (false == module_manager.net_name(module_id, module_net).empty()) { - net_name = module_manager.net_name(module_id, module_net); - } else { - net_name = module_manager.module_name(net_src_module); - net_name += std::string("_") + std::to_string(net_src_instance) + std::string("_"); - net_name += module_manager.module_port(net_src_module, net_src_port).get_name(); - } - - return BasicPort(net_name, net_src_pin, net_src_pin); -} - -/******************************************************************** - * Find all the nets that are going to be local wires - * And organize it in a vector of ports - * Verilog wire writter function will use the output of this function - * to write up local wire declaration in Verilog format - *******************************************************************/ -static -std::map> find_verilog_module_local_wires(const ModuleManager& module_manager, - const ModuleId& module_id) { - std::map> local_wires; - - /* Local wires come from the child modules */ - for (ModuleNetId module_net : module_manager.module_nets(module_id)) { - /* Bypass dangling nets: - * Xifan Tang: I comment this part because it will shadow our problems in creating module graph - * Indeed this make a robust and a smooth Verilog module writing - * But I do want the module graph create is nice and clean !!! - */ - /* - if ( (0 == module_manager.net_source_modules(module_id, module_net).size()) - && (0 == module_manager.net_source_modules(module_id, module_net).size()) ) { - continue; - } - */ - - /* We only care local wires */ - if (false == module_net_is_local_wire(module_manager, module_id, module_net)) { - continue; - } - /* Find the name for this local wire */ - BasicPort local_wire_candidate = generate_verilog_port_for_module_net(module_manager, module_id, module_net); - /* Cache the net name, try to find it in the cache. - * If you can find one, it means this port may be mergeable, try to do merging. If merge fail, add to the local wire list - * If you cannot find one, it means that this port is not mergeable, add to the local wire list immediately. - */ - std::map>::iterator it = local_wires.find(local_wire_candidate.get_name()); - bool merged = false; - if (it != local_wires.end()) { - /* Try to merge to one the port in the list that can absorb the current local wire */ - for (BasicPort& local_wire : local_wires[local_wire_candidate.get_name()]) { - /* check if the candidate can be combined to an existing local wire */ - if (true == two_verilog_ports_mergeable(local_wire, local_wire_candidate)) { - /* Merge the ports */ - local_wire = merge_two_verilog_ports(local_wire, local_wire_candidate); - merged = true; - break; - } - } - } - - /* If not merged/not found in the cache, push the port to the list */ - if (false == merged) { - local_wires[local_wire_candidate.get_name()].push_back(local_wire_candidate); - } - } - - /* Local wires could also happen for undriven ports of child module */ - for (const ModuleId& child : module_manager.child_modules(module_id)) { - for (size_t instance : module_manager.child_module_instances(module_id, child)) { - for (const ModulePortId& child_port_id : module_manager.module_ports(child)) { - BasicPort child_port = module_manager.module_port(child, child_port_id); - std::vector undriven_pins; - for (size_t child_pin : child_port.pins()) { - /* Find the net linked to the pin */ - ModuleNetId net = module_manager.module_instance_port_net(module_id, child, instance, - child_port_id, child_pin); - /* We only care undriven ports */ - if (ModuleNetId::INVALID() == net) { - undriven_pins.push_back(child_pin); - } - } - if (true == undriven_pins.empty()) { - continue; - } - /* Reach here, we need a local wire, we will create a port only for the undriven pins of the port! */ - BasicPort instance_port; - instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, module_id, child, instance, child_port_id)); - /* We give the same port name as child module, this case happens to global ports */ - instance_port.set_width(*std::min_element(undriven_pins.begin(), undriven_pins.end()), - *std::max_element(undriven_pins.begin(), undriven_pins.end())); - - local_wires[instance_port.get_name()].push_back(instance_port); - } - } - } - - return local_wires; -} - -/******************************************************************** - * Print a Verilog wire connection - * We search all the sinks of the net, - * if we find a module output, we try to find the next module output - * among the sinks of the net - * For each module output (except the first one), we print a wire connection - *******************************************************************/ -static -void print_verilog_module_output_short_connection(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& module_id, - const ModuleNetId& module_net) { - /* Ensure a valid file stream */ - check_file_handler(fp); - - bool first_port = true; - BasicPort src_port; - - /* We have found a module input, now check all the sink modules of the net */ - for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) { - ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink]; - if (module_id != sink_module) { - continue; - } - - /* Find the sink port and pin information */ - ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink]; - size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink]; - BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin); - - /* For the first module output, this is the source port, we do nothing and go to the next */ - if (true == first_port) { - src_port = sink_port; - /* Flip the flag */ - first_port = false; - continue; - } - - /* We need to print a wire connection here */ - print_verilog_wire_connection(fp, sink_port, src_port, false); - } -} - - -/******************************************************************** - * Print a Verilog wire connection - * We search all the sources of the net, - * if we find a module input, we try to find a module output - * among the sinks of the net - * If we find such a pair, we print a wire connection - *******************************************************************/ -static -void print_verilog_module_local_short_connection(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& module_id, - const ModuleNetId& module_net) { - /* Ensure a valid file stream */ - check_file_handler(fp); - - for (ModuleNetSrcId net_src : module_manager.module_net_sources(module_id, module_net)) { - ModuleId src_module = module_manager.net_source_modules(module_id, module_net)[net_src]; - if (module_id != src_module) { - continue; - } - /* Find the source port and pin information */ - print_verilog_comment(fp, std::string("----- Net source id " + std::to_string(size_t(net_src)) + " -----")); - ModulePortId src_port_id = module_manager.net_source_ports(module_id, module_net)[net_src]; - size_t src_pin = module_manager.net_source_pins(module_id, module_net)[net_src]; - BasicPort src_port(module_manager.module_port(module_id, src_port_id).get_name(), src_pin, src_pin); - - /* We have found a module input, now check all the sink modules of the net */ - for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) { - ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink]; - if (module_id != sink_module) { - continue; - } - - /* Find the sink port and pin information */ - print_verilog_comment(fp, std::string("----- Net sink id " + std::to_string(size_t(net_sink)) + " -----")); - ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink]; - size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink]; - BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin); - - /* We need to print a wire connection here */ - print_verilog_wire_connection(fp, sink_port, src_port, false); - } - } -} - -/******************************************************************** - * Print short connections inside a Verilog module - * The short connection is defined as the direct connection - * between an input port of the module and an output port of the module - * This type of connection is not covered when printing Verilog instances - * Therefore, they are covered in this function - * - * module - * +-----------------------------+ - * | | - * inputA--->|---------------------------->|--->outputB - * | | - * | | - * | | - * +-----------------------------+ - *******************************************************************/ -static -void print_verilog_module_local_short_connections(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& module_id) { - /* Local wires come from the child modules */ - for (ModuleNetId module_net : module_manager.module_nets(module_id)) { - /* We only care the nets that indicate short connections */ - if (false == module_net_include_local_short_connection(module_manager, module_id, module_net)) { - continue; - } - print_verilog_comment(fp, std::string("----- Local connection due to Wire " + std::to_string(size_t(module_net)) + " -----")); - print_verilog_module_local_short_connection(fp, module_manager, module_id, module_net); - } -} - -/******************************************************************** - * Print output short connections inside a Verilog module - * The output short connection is defined as the direct connection - * between two output ports of the module - * This type of connection is not covered when printing Verilog instances - * Therefore, they are covered in this function - * - * module - * +-----------------------------+ - * | - * src------>+--------------->|--->outputA - * | | - * | | - * +--------------->|--->outputB - * +-----------------------------+ - *******************************************************************/ -static -void print_verilog_module_output_short_connections(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& module_id) { - /* Local wires come from the child modules */ - for (ModuleNetId module_net : module_manager.module_nets(module_id)) { - /* We only care the nets that indicate short connections */ - if (false == module_net_include_output_short_connection(module_manager, module_id, module_net)) { - continue; - } - print_verilog_module_output_short_connection(fp, module_manager, module_id, module_net); - } -} - -/******************************************************************** - * Write a Verilog instance to a file - * This function will name the input and output connections to - * the inputs/output or local wires available in the parent module - * - * Parent_module - * +-----------------------------+ - * | | - * | +--------------+ | - * | | | | - * | | child_module | | - * | | [instance] | | - * | +--------------+ | - * | | - * +-----------------------------+ - * - *******************************************************************/ -static -void write_verilog_instance_to_file(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module, - const ModuleId& child_module, - const size_t& instance_id, - const bool& use_explicit_port_map) { - /* Ensure a valid file stream */ - check_file_handler(fp); - - /* Print module name */ - fp << "\t" << module_manager.module_name(child_module) << " "; - /* Print instance name: - * if we have an instance name, use it; - * if not, we use a default name _ - */ - if (true == module_manager.instance_name(parent_module, child_module, instance_id).empty()) { - fp << module_manager.module_name(child_module) << "_" << instance_id << "_" << " (" << std::endl; - } else { - fp << module_manager.instance_name(parent_module, child_module, instance_id) << " (" << std::endl; - } - - /* Print each port with/without explicit port map */ - /* port type2type mapping */ - std::map port_type2type_map; - port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_CONKT; - - /* Port sequence: global, inout, input, output and clock ports, */ - size_t port_cnt = 0; - for (const auto& kv : port_type2type_map) { - for (const ModulePortId& child_port_id : module_manager.module_port_ids_by_type(child_module, kv.first)) { - BasicPort child_port = module_manager.module_port(child_module, child_port_id); - if (0 != port_cnt) { - /* Do not dump a comma for the first port */ - fp << "," << std::endl; - } - /* Print port */ - fp << "\t\t"; - /* if explicit port map is required, output the port name */ - if (true == use_explicit_port_map) { - fp << "." << child_port.get_name() << "("; - } - - /* Create the port name and width to be used by the instance */ - std::vector instance_ports; - for (size_t child_pin : child_port.pins()) { - /* Find the net linked to the pin */ - ModuleNetId net = module_manager.module_instance_port_net(parent_module, child_module, instance_id, - child_port_id, child_pin); - BasicPort instance_port; - if (ModuleNetId::INVALID() == net) { - /* We give the same port name as child module, this case happens to global ports */ - instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, parent_module, child_module, instance_id, child_port_id)); - instance_port.set_width(child_pin, child_pin); - } else { - /* Find the name for this child port */ - instance_port = generate_verilog_port_for_module_net(module_manager, parent_module, net); - } - /* Create the port information for the net */ - instance_ports.push_back(instance_port); - } - /* Try to merge the ports */ - std::vector merged_ports = combine_verilog_ports(instance_ports); - - /* Print a verilog port by combining the instance ports */ - fp << generate_verilog_ports(merged_ports); - - /* if explicit port map is required, output the pair of branket */ - if (true == use_explicit_port_map) { - fp << ")"; - } - port_cnt++; - } - } - - /* Print an end to the instance */ - fp << ");" << std::endl; -} - -/******************************************************************** - * Write a Verilog module to a file - * This is a key function, maybe most frequently called in our Verilog writer - * Note that file stream must be valid - *******************************************************************/ -void write_verilog_module_to_file(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& module_id, - const bool& use_explicit_port_map) { - /* Ensure we have a valid module_id */ - VTR_ASSERT(module_manager.valid_module_id(module_id)); - - /* Print module declaration */ - print_verilog_module_declaration(fp, module_manager, module_id); - - /* Print an empty line as splitter */ - fp << std::endl; - - /* Print internal wires */ - std::map> local_wires = find_verilog_module_local_wires(module_manager, module_id); - for (std::pair> port_group : local_wires) { - for (const BasicPort& local_wire : port_group.second) { - fp << generate_verilog_port(VERILOG_PORT_WIRE, local_wire) << ";" << std::endl; - } - } - - /* Print an empty line as splitter */ - fp << std::endl; - - /* Print local connection (from module inputs to output! */ - print_verilog_comment(fp, std::string("----- BEGIN Local short connections -----")); - print_verilog_module_local_short_connections(fp, module_manager, module_id); - print_verilog_comment(fp, std::string("----- END Local short connections -----")); - - print_verilog_comment(fp, std::string("----- BEGIN Local output short connections -----")); - print_verilog_module_output_short_connections(fp, module_manager, module_id); - - print_verilog_comment(fp, std::string("----- END Local output short connections -----")); - /* Print an empty line as splitter */ - fp << std::endl; - - /* Print instances */ - for (ModuleId child_module : module_manager.child_modules(module_id)) { - for (size_t instance : module_manager.child_module_instances(module_id, child_module)) { - /* Print an instance */ - write_verilog_instance_to_file(fp, module_manager, module_id, child_module, instance, use_explicit_port_map); - /* Print an empty line as splitter */ - fp << std::endl; - } - } - - /* Print an end for the module */ - print_verilog_module_end(fp, module_manager.module_name(module_id)); - - /* Print an empty line as splitter */ - fp << std::endl; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.h deleted file mode 100644 index 0846384b7..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.h +++ /dev/null @@ -1,16 +0,0 @@ -/******************************************************************** - * Header file for verilog_module_writer.cpp - *******************************************************************/ - -#ifndef VERILOG_MODULE_WRITER_H -#define VERILOG_MODULE_WRITER_H - -#include -#include "module_manager.h" - -void write_verilog_module_to_file(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& module_id, - const bool& use_explicit_port_map); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp deleted file mode 100644 index f13c82f33..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ /dev/null @@ -1,1286 +0,0 @@ -/*********************************************** - * This file includes functions to generate - * Verilog submodules for multiplexers. - * including both fundamental submodules - * such as a branch in a multiplexer - * and the full multiplexer - **********************************************/ -#include -#include - -#include "util.h" -#include "vtr_assert.h" - -/* Device-level header files */ -#include "mux_graph.h" -#include "module_manager.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "mux_utils.h" -#include "circuit_library_utils.h" -#include "decoder_library_utils.h" - -/* FPGA-X2P context header files */ -#include "spice_types.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -/* FPGA-Verilog context header files */ -#include "verilog_global.h" -#include "verilog_writer_utils.h" -#include "verilog_module_writer.h" -#include "verilog_mux.h" - -/********************************************************************* - * Generate behavior-level Verilog codes modeling an branch circuit - * for a multiplexer with the given size - *********************************************************************/ -static -void generate_verilog_cmos_mux_branch_body_behavioral(std::fstream& fp, - const BasicPort& input_port, - const BasicPort& output_port, - const BasicPort& mem_port, - const MuxGraph& mux_graph, - const size_t& default_mem_val) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Verilog Behavior description for a MUX */ - print_verilog_comment(fp, std::string("---- Behavioral-level description -----")); - - /* Add an internal register for the output */ - BasicPort outreg_port("out_reg", mux_graph.num_outputs()); - /* Print the port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, outreg_port) << ";" << std::endl; - - /* Generate the case-switch table */ - fp << "\talways @(" << generate_verilog_port(VERILOG_PORT_CONKT, input_port) << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_port) << ")" << std::endl; - fp << "\tcase (" << generate_verilog_port(VERILOG_PORT_CONKT, mem_port) << ")" << std::endl; - - /* Output the netlist following the connections in mux_graph */ - /* Iterate over the inputs */ - for (const auto& mux_input : mux_graph.inputs()) { - BasicPort cur_input_port(input_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input))); - /* Iterate over the outputs */ - for (const auto& mux_output : mux_graph.outputs()) { - BasicPort cur_output_port(output_port.get_name(), size_t(mux_graph.output_id(mux_output)), size_t(mux_graph.output_id(mux_output))); - /* if there is a connection between the input and output, a tgate will be outputted */ - std::vector edges = mux_graph.find_edges(mux_input, mux_output); - /* There should be only one edge or no edge*/ - VTR_ASSERT((1 == edges.size()) || (0 == edges.size())); - /* No need to output tgates if there are no edges between two nodes */ - if (0 == edges.size()) { - continue; - } - /* For each case, generate the logic levels for all the inputs */ - /* In each case, only one mem is enabled */ - fp << "\t\t" << mem_port.get_width() << "'b"; - std::string case_code(mem_port.get_width(), default_mem_val); - - /* Find the mem_id controlling the edge */ - MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]); - /* Flip a bit by the mem_id */ - if (false == mux_graph.is_edge_use_inv_mem(edges[0])) { - case_code[size_t(mux_mem)] = '1'; - } else { - case_code[size_t(mux_mem)] = '0'; - } - fp << case_code << ": " << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port) << " <= "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_input_port) << ";" << std::endl; - } - } - - /* Default case: outputs are at high-impedance state 'z' */ - std::string default_case(mux_graph.num_outputs(), 'z'); - fp << "\t\tdefault: " << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port) << " <= "; - fp << mux_graph.num_outputs() << "'b" << default_case << ";" << std::endl; - - /* End the case */ - fp << "\tendcase" << std::endl; - - /* Wire registers to output ports */ - fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " = "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, outreg_port) << ";" << std::endl; -} - -/********************************************************************* - * Generate Verilog codes modeling an branch circuit - * for a CMOS multiplexer with the given size - * Support structural and behavioral Verilog codes - *********************************************************************/ -static -void print_verilog_cmos_mux_branch_module_behavioral(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& mux_model, - const std::string& module_name, - const MuxGraph& mux_graph) { - /* Get the tgate model */ - CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(mux_model); - - /* Skip output if the tgate model is a MUX2, it is handled by essential-gate generator */ - if (SPICE_MODEL_GATE == circuit_lib.model_type(tgate_model)) { - VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model)); - return; - } - - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Generate the Verilog netlist according to the mux_graph */ - /* Find out the number of inputs */ - size_t num_inputs = mux_graph.num_inputs(); - /* Find out the number of outputs */ - size_t num_outputs = mux_graph.num_outputs(); - /* Find out the number of memory bits */ - size_t num_mems = mux_graph.num_memory_bits(); - - /* Check codes to ensure the port of Verilog netlists will match */ - /* MUX graph must have only 1 output */ - VTR_ASSERT(1 == num_outputs); - /* MUX graph must have only 1 level*/ - VTR_ASSERT(1 == mux_graph.num_levels()); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId mux_module = module_manager.find_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); - /* Find module ports */ - /* Find each input port */ - BasicPort input_port("in", num_inputs); - /* Find each output port */ - BasicPort output_port("out", num_outputs); - /* Find each memory port */ - BasicPort mem_port("mem", num_mems); - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, mux_module); - - /* Print the internal logic in behavioral Verilog codes */ - /* Get the default value of SRAM ports */ - std::vector regular_sram_ports = find_circuit_regular_sram_ports(circuit_lib, mux_model); - VTR_ASSERT(1 == regular_sram_ports.size()); - std::string mem_default_val = std::to_string(circuit_lib.port_default_value(regular_sram_ports[0])); - /* Mem string must be only 1-bit! */ - VTR_ASSERT(1 == mem_default_val.length()); - generate_verilog_cmos_mux_branch_body_behavioral(fp, input_port, output_port, mem_port, mux_graph, mem_default_val[0]); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); -} - -/********************************************************************* - * Dump a structural verilog for RRAM MUX basis module - * This is only called when structural verilog dumping option is enabled for this spice model - * IMPORTANT: the structural verilog can NOT be used for functionality verification!!! - * TODO: This part is quite restricted to the way we implemented our RRAM FPGA - * Should be reworked to be more generic !!! - * - * By structural the schematic is splitted into two parts: left part and right part - * The left part includes BLB[0..N-1] and WL[0..N-1] signals as well as RRAMs - * The right part includes BLB[N] and WL[N] - * Corresponding Schematic is as follows: - * - * LEFT PART | RIGHT PART - * - * BLB[0] BLB[N] - * | | - * \|/ \|/ - * in[0] ---->RRAM[0]-----+ - * | - * BLB[1] | - * | | - * \|/ | - * in[1] ---->RRAM[1]-----+ - * |-----> out[0] - * ... - * | - * in[N-1] ---->RRAM[N-1]---+ - * /|\ /|\ - * | | - * BLB[N-1] WL[N] - * - * Working principle: - * 1. Set a RRAM[i]: enable BLB[i] and WL[N] - * 2. Reset a RRAM[i]: enable BLB[N] and WL[i] - * 3. Operation: disable all BLBs and WLs - * - * The structure is done in the way we implement the physical layout of RRAM MUX - * It is NOT the only road to the goal!!! - *********************************************************************/ -static -void generate_verilog_rram_mux_branch_body_structural(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const ModuleId& module_id, - const CircuitModelId& circuit_model, - const BasicPort& input_port, - const BasicPort& output_port, - const BasicPort& blb_port, - const BasicPort& wl_port, - const MuxGraph& mux_graph) { - std::string progTE_module_name("PROG_TE"); - std::string progBE_module_name("PROG_BE"); - - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Verilog Behavior description for a MUX */ - print_verilog_comment(fp, std::string("---- Structure-level description of RRAM MUX -----")); - - /* Print internal structure of 4T1R programming structures - * Written in structural Verilog - * The whole structure-level description is divided into two parts: - * 1. Left part consists of N PROG_TE modules, each of which - * includes a PMOS, a NMOS and a RRAM, which is actually the left - * part of a 4T1R programming structure - * 2. Right part includes only a PROG_BE module, which consists - * of a PMOS and a NMOS, which is actually the right part of a - * 4T1R programming sturcture - */ - /* Create a module for the progTE and register it in the module manager - * Structure of progTE - * - * +----------+ - * in--->| | - * BLB-->| progTE |--> out - * WL--->| | - * +----------+ - */ - ModuleId progTE_module_id = module_manager.add_module(progTE_module_name); - /* If there is already such as module inside, we just ned to find the module id */ - if (ModuleId::INVALID() == progTE_module_id) { - progTE_module_id = module_manager.find_module(progTE_module_name); - /* We should have a valid id! */ - VTR_ASSERT(ModuleId::INVALID() != progTE_module_id); - } - /* Add ports to the module */ - /* input port */ - BasicPort progTE_in_port("A", 1); - module_manager.add_port(progTE_module_id, progTE_in_port, ModuleManager::MODULE_INPUT_PORT); - /* WL port */ - BasicPort progTE_wl_port("WL", 1); - module_manager.add_port(progTE_module_id, progTE_wl_port, ModuleManager::MODULE_INPUT_PORT); - /* BLB port */ - BasicPort progTE_blb_port("BLB", 1); - module_manager.add_port(progTE_module_id, progTE_blb_port, ModuleManager::MODULE_INPUT_PORT); - /* output port */ - BasicPort progTE_out_port("Z", 1); - module_manager.add_port(progTE_module_id, progTE_out_port, ModuleManager::MODULE_INPUT_PORT); - - /* LEFT part: Verilog code generation */ - /* Iterate over the inputs */ - for (const auto& mux_input : mux_graph.inputs()) { - BasicPort cur_input_port(input_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input))); - /* Iterate over the outputs */ - for (const auto& mux_output : mux_graph.outputs()) { - BasicPort cur_output_port(output_port.get_name(), size_t(mux_graph.output_id(mux_output)), size_t(mux_graph.output_id(mux_output))); - /* if there is a connection between the input and output, a tgate will be outputted */ - std::vector edges = mux_graph.find_edges(mux_input, mux_output); - /* There should be only one edge or no edge*/ - VTR_ASSERT((1 == edges.size()) || (0 == edges.size())); - /* No need to output tgates if there are no edges between two nodes */ - if (0 == edges.size()) { - continue; - } - /* Create a port-to-port name map */ - std::map port2port_name_map; - /* input port */ - port2port_name_map[progTE_in_port.get_name()] = cur_input_port; - /* output port */ - port2port_name_map[progTE_out_port.get_name()] = cur_output_port; - /* Find the mem_id controlling the edge */ - MuxMemId mux_mem = mux_graph.find_edge_mem(edges[0]); - BasicPort cur_blb_port(blb_port.get_name(), size_t(mux_mem), size_t(mux_mem)); - BasicPort cur_wl_port(wl_port.get_name(), size_t(mux_mem), size_t(mux_mem)); - /* RRAM configuration port: there should not be any inverted edge in RRAM MUX! */ - VTR_ASSERT( false == mux_graph.is_edge_use_inv_mem(edges[0]) ); - /* wire mem to mem of module, and wire mem_inv to mem_inv of module */ - port2port_name_map[progTE_blb_port.get_name()] = cur_blb_port; - port2port_name_map[progTE_wl_port.get_name()] = cur_wl_port; - /* Output an instance of the module */ - print_verilog_module_instance(fp, module_manager, module_id, progTE_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, progTE_module_id); - } - } - - /* Create a module for the progBE and register it in the module manager - * Structure of progBE - * - * +----------+ - * | | - * BLB-->| progBE |<-> out - * WL--->| | - * +----------+ - */ - ModuleId progBE_module_id = module_manager.add_module(progBE_module_name); - /* If there is already such as module inside, we just ned to find the module id */ - if (ModuleId::INVALID() == progBE_module_id) { - progBE_module_id = module_manager.find_module(progBE_module_name); - /* We should have a valid id! */ - VTR_ASSERT(ModuleId::INVALID() != progBE_module_id); - } - /* Add ports to the module */ - /* inout port */ - BasicPort progBE_inout_port("INOUT", 1); - module_manager.add_port(progBE_module_id, progBE_inout_port, ModuleManager::MODULE_INOUT_PORT); - /* WL port */ - BasicPort progBE_wl_port("WL", 1); - module_manager.add_port(progBE_module_id, progBE_wl_port, ModuleManager::MODULE_INPUT_PORT); - /* BLB port */ - BasicPort progBE_blb_port("BLB", 1); - module_manager.add_port(progBE_module_id, progBE_blb_port, ModuleManager::MODULE_INPUT_PORT); - - /* RIGHT part: Verilog code generation */ - /* Iterate over the outputs */ - for (const auto& mux_output : mux_graph.outputs()) { - BasicPort cur_output_port(output_port.get_name(), size_t(mux_graph.output_id(mux_output)), size_t(mux_graph.output_id(mux_output))); - /* Create a port-to-port name map */ - std::map port2port_name_map; - /* Wire the output port to the INOUT port */ - port2port_name_map[progBE_inout_port.get_name()] = cur_output_port; - /* Find the mem_id controlling the edge */ - BasicPort cur_blb_port(blb_port.get_name(), mux_graph.num_memory_bits(), mux_graph.num_memory_bits()); - BasicPort cur_wl_port(wl_port.get_name(), mux_graph.num_memory_bits(), mux_graph.num_memory_bits()); - port2port_name_map[progBE_blb_port.get_name()] = cur_blb_port; - port2port_name_map[progBE_wl_port.get_name()] = cur_wl_port; - /* Output an instance of the module */ - print_verilog_module_instance(fp, module_manager, module_id, progBE_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, progBE_module_id); - } -} - -/********************************************************************* - * Generate behavior-level Verilog codes modeling an branch circuit - * for a RRAM-based multiplexer with the given size - * Corresponding Schematic is as follows: - * - * BLB[0] BLB[N] - * | | - * \|/ \|/ - * in[0] ---->RRAM[0]-----+ - * | - * BLB[1] | - * | | - * \|/ | - * in[1] ---->RRAM[1]-----+ - * |-----> out[0] - * ... - * | - * in[N-1] ---->RRAM[N-1]---+ - * /|\ /|\ - * | | - * BLB[N-1] WL[N] - * - * Working principle: - * 1. Set a RRAM[i]: enable BLB[i] and WL[N] - * 2. Reset a RRAM[i]: enable BLB[N] and WL[i] - * 3. Operation: disable all BLBs and WLs - * - * TODO: Elaborate the codes to output the circuit logic - * following the mux_graph! - *********************************************************************/ -static -void generate_verilog_rram_mux_branch_body_behavioral(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model, - const BasicPort& input_port, - const BasicPort& output_port, - const BasicPort& blb_port, - const BasicPort& wl_port, - const MuxGraph& mux_graph) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Verilog Behavior description for a MUX */ - print_verilog_comment(fp, std::string("---- Behavioral-level description of RRAM MUX -----")); - - /* Add an internal register for the output */ - BasicPort outreg_port("out_reg", mux_graph.num_inputs()); - /* Print the port */ - fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, outreg_port) << ";" << std::endl; - - /* Print the internal logics */ - fp << "\t" << "always @("; - fp << generate_verilog_port(VERILOG_PORT_CONKT, blb_port); - fp << ", "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_port); - fp << ")"; - fp << " begin" << std::endl; - - /* Only when the last bit of wl is enabled, - * the propagating path can be changed - * (RRAM value can be changed) */ - fp << "\t\t" << "if ("; - BasicPort set_enable_port(wl_port.get_name(), wl_port.get_width() - 1, wl_port.get_width() - 1); - fp << generate_verilog_port(VERILOG_PORT_CONKT, set_enable_port); - /* We need two config-enable ports: prog_EN and prog_ENb */ - bool find_prog_EN = false; - bool find_prog_ENb = false; - for (const auto& port : circuit_lib.model_global_ports(circuit_model, true)) { - /* Bypass non-config-enable ports */ - if (false == circuit_lib.port_is_config_enable(port)) { - continue; - } - /* Reach here, the port should be is_config_enable */ - /* Create a port object */ - fp << " && "; - BasicPort prog_en_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - if ( 0 == circuit_lib.port_default_value(port)) { - /* Default value = 0 means that this is a prog_EN port */ - fp << generate_verilog_port(VERILOG_PORT_CONKT, prog_en_port); - find_prog_EN = true; - } else { - VTR_ASSERT ( 1 == circuit_lib.port_default_value(port)); - /* Default value = 1 means that this is a prog_ENb port, add inversion in the if condition */ - fp << "(~" << generate_verilog_port(VERILOG_PORT_CONKT, prog_en_port) << ")"; - find_prog_ENb = true; - } - } - /* Check if we find any config_enable signals */ - if (false == find_prog_EN) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Unable to find a config_enable signal with default value 0 for a RRAM MUX (%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - if (false == find_prog_ENb) { - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Unable to find a config_enable signal with default value 1 for a RRAM MUX (%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - - /* Finish the if clause */ - fp << ") begin" << std::endl; - - for (const auto& mux_input : mux_graph.inputs()) { - /* First if clause need tabs */ - if ( 0 == size_t(mux_graph.input_id(mux_input)) ) { - fp << "\t\t\t"; - } - fp << "if (1 == "; - /* Create a temp port of a BLB bit */ - BasicPort cur_blb_port(blb_port.get_name(), size_t(mux_graph.input_id(mux_input)), size_t(mux_graph.input_id(mux_input))); - fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_blb_port); - fp << ") begin" << std::endl; - fp << "\t\t\t\t" << "assign "; - fp << outreg_port.get_name(); - fp << " = " << size_t(mux_graph.input_id(mux_input)) << ";" << std::endl; - fp << "\t\t\t" << "end else "; - } - fp << "begin" << std::endl; - fp << "\t\t\t\t" << "assign "; - fp << outreg_port.get_name(); - fp << " = 0;" << std::endl; - fp << "\t\t\t" << "end" << std::endl; - fp << "\t\t" << "end" << std::endl; - fp << "\t" << "end" << std::endl; - - fp << "\t" << "assign "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); - fp << " = "; - fp << input_port.get_name() << "["; - fp << outreg_port.get_name(); - fp << "];" << std::endl; -} - -/********************************************************************* - * Generate Verilog codes modeling an branch circuit - * for a RRAM-based multiplexer with the given size - * Support structural and behavioral Verilog codes - *********************************************************************/ -static -void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& circuit_model, - const std::string& module_name, - const MuxGraph& mux_graph, - const bool& use_structural_verilog) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Get the input ports from the mux */ - std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - /* Get the output ports from the mux */ - std::vector mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Get the BL and WL ports from the mux */ - std::vector mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_BLB, true); - std::vector mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_WL, true); - - /* Generate the Verilog netlist according to the mux_graph */ - /* Find out the number of inputs */ - size_t num_inputs = mux_graph.num_inputs(); - /* Find out the number of outputs */ - size_t num_outputs = mux_graph.num_outputs(); - /* Find out the number of memory bits */ - size_t num_mems = mux_graph.num_memory_bits(); - - /* Check codes to ensure the port of Verilog netlists will match */ - /* MUX graph must have only 1 output */ - VTR_ASSERT(1 == num_outputs); - /* MUX graph must have only 1 level*/ - VTR_ASSERT(1 == mux_graph.num_levels()); - /* MUX graph must have only 1 input and 1 BLB and 1 WL port */ - VTR_ASSERT(1 == mux_input_ports.size()); - VTR_ASSERT(1 == mux_output_ports.size()); - VTR_ASSERT(1 == mux_blb_ports.size()); - VTR_ASSERT(1 == mux_wl_ports.size()); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.find_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(module_id)); - - /* Find each input port */ - BasicPort input_port(circuit_lib.port_prefix(mux_input_ports[0]), num_inputs); - - /* Find each output port */ - BasicPort output_port(circuit_lib.port_prefix(mux_output_ports[0]), num_outputs); - - /* Find RRAM programming ports, - * RRAM MUXes require one more pair of BLB and WL - * to configure the memories. See schematic for details - */ - BasicPort blb_port(circuit_lib.port_prefix(mux_blb_ports[0]), num_mems + 1); - - BasicPort wl_port(circuit_lib.port_prefix(mux_wl_ports[0]), num_mems + 1); - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - - /* Print the internal logic in either structural or behavioral Verilog codes */ - if (true == use_structural_verilog) { - generate_verilog_rram_mux_branch_body_structural(module_manager, circuit_lib, fp, module_id, circuit_model, input_port, output_port, blb_port, wl_port, mux_graph); - } else { - generate_verilog_rram_mux_branch_body_behavioral(fp, circuit_lib, circuit_model, input_port, output_port, blb_port, wl_port, mux_graph); - } - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); -} - -/*********************************************** - * Generate Verilog codes modeling an branch circuit - * for a multiplexer with the given size - **********************************************/ -static -void generate_verilog_mux_branch_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& mux_model, - const size_t& mux_size, - const MuxGraph& mux_graph, - const bool& use_explicit_port_map) { - std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_size, mux_graph.num_inputs(), verilog_mux_basis_posfix); - - /* Multiplexers built with different technology is in different organization */ - switch (circuit_lib.design_tech_type(mux_model)) { - case SPICE_MODEL_DESIGN_CMOS: - /* Skip module writing if the branch subckt is a standard cell! */ - if (true == circuit_lib.valid_model_id(circuit_lib.model(module_name))) { - /* This model must be a MUX2 gate */ - VTR_ASSERT(SPICE_MODEL_GATE == circuit_lib.model_type(circuit_lib.model(module_name))); - VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(circuit_lib.model(module_name))); - break; - } - if (true == circuit_lib.dump_structural_verilog(mux_model)) { - /* Structural verilog can be easily generated by module writer */ - ModuleId mux_module = module_manager.find_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); - write_verilog_module_to_file(fp, module_manager, mux_module, - use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model)); - /* Add an empty line as a splitter */ - fp << std::endl; - } else { - /* Behavioral verilog requires customized generation */ - print_verilog_cmos_mux_branch_module_behavioral(module_manager, circuit_lib, fp, mux_model, module_name, mux_graph); - } - break; - case SPICE_MODEL_DESIGN_RRAM: - generate_verilog_rram_mux_branch_module(module_manager, circuit_lib, fp, mux_model, module_name, mux_graph, - circuit_lib.dump_structural_verilog(mux_model)); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", - __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); - exit(1); - } -} - -/******************************************************************** - * Generate the input bufferes for a multiplexer or LUT in Verilog codes - * 1. If input are required to be buffered (specified by users), - * buffers will be added to all the datapath inputs. - * 2. If input are required to NOT be buffered (specified by users), - * all the datapath inputs will be short wired to MUX inputs. - * - * For those Multiplexers or LUTs require a constant input: - * the last input of multiplexer will be wired to a constant voltage level - *******************************************************************/ -static -void generate_verilog_cmos_mux_module_input_buffers(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const ModuleId& module_id, - const CircuitModelId& circuit_model, - const MuxGraph& mux_graph) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Get the input ports from the mux */ - std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - /* We should have only 1 input port! */ - VTR_ASSERT(1 == mux_input_ports.size()); - - /* Get the input port from MUX module */ - ModulePortId module_input_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(mux_input_ports[0])); - VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); - /* Get the port from module */ - BasicPort module_input_port = module_manager.module_port(module_id, module_input_port_id); - - /* Iterate over all the inputs in the MUX graph */ - for (const auto& input_node : mux_graph.inputs()) { - /* Fetch fundamental information from MUX graph w.r.t. the input node */ - MuxInputId input_index = mux_graph.input_id(input_node); - VTR_ASSERT(MuxInputId::INVALID() != input_index); - - size_t input_node_level = mux_graph.node_level(input_node); - size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node); - - /* Create the port information of the MUX input, which is the input of buffer instance */ - BasicPort instance_input_port(module_input_port.get_name(), size_t(input_index), size_t(input_index)); - - /* Create the port information of the MUX graph input, which is the output of buffer instance */ - BasicPort instance_output_port(generate_mux_node_name(input_node_level, false), input_node_index_at_level, input_node_index_at_level); - - /* For last input: - * Add a constant value to the last input, if this MUX needs a constant input - */ - if ( (MuxInputId(mux_graph.num_inputs() - 1) == mux_graph.input_id(input_node)) - && (true == circuit_lib.mux_add_const_input(circuit_model)) ) { - /* Get the constant input value */ - size_t const_value = circuit_lib.mux_const_input_value(circuit_model); - VTR_ASSERT( (0 == const_value) || (1 == const_value) ); - /* For the output of the buffer instance: - * Get the last inputs from the MUX graph and generate the node name in MUX module. - */ - print_verilog_comment(fp, std::string("---- BEGIN short-wire a multiplexing structure input to a constant value -----")); - print_verilog_wire_constant_values(fp, instance_output_port, std::vector(1, const_value)); - print_verilog_comment(fp, std::string("---- END short-wire a multiplexing structure input to a constant value -----")); - fp << std::endl; - continue; /* Finish here */ - } - - /* If the inputs are not supposed to be buffered */ - if (false == circuit_lib.is_input_buffered(circuit_model)) { - print_verilog_comment(fp, std::string("---- BEGIN short-wire a multiplexing structure input to MUX module input -----")); - - /* Short wire all the datapath inputs to the MUX inputs */ - print_verilog_wire_connection(fp, instance_output_port, instance_input_port, false); - - print_verilog_comment(fp, std::string("---- END short-wire a multiplexing structure input to MUX module input -----")); - fp << std::endl; - continue; /* Finish here */ - } - - /* Reach here, we need a buffer, create a port-to-port map and output the buffer instance */ - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an input buffer module -----")); - - /* Now we need to add intermediate buffers by instanciating the modules */ - CircuitModelId buffer_model = circuit_lib.input_buffer_model(circuit_model); - /* We must have a valid model id */ - VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - - print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, instance_input_port, instance_output_port); - - print_verilog_comment(fp, std::string("---- END Instanciation of an input buffer module -----")); - fp << std::endl; - } -} - -/******************************************************************** - * Generate the output bufferes for a multiplexer or LUT in Verilog codes - * 1. If output are required to be buffered (specified by users), - * buffers will be added to all the outputs. - * 2. If output are required to NOT be buffered (specified by users), - * all the outputs will be short wired to MUX outputs. - *******************************************************************/ -static -void generate_verilog_cmos_mux_module_output_buffers(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const ModuleId& module_id, - const CircuitModelId& circuit_model, - const MuxGraph& mux_graph) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Get the output ports from the mux */ - std::vector mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - - /* Iterate over all the outputs in the MUX module */ - for (const auto& output_port : mux_output_ports) { - /* Get the output port from MUX module */ - ModulePortId module_output_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(output_port)); - VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); - /* Get the port from module */ - BasicPort module_output_port = module_manager.module_port(module_id, module_output_port_id); - - /* Iterate over each pin of the output port */ - for (const auto& pin : circuit_lib.pins(output_port)) { - /* Fetch fundamental information from MUX graph w.r.t. the input node */ - /* Deposite the last level of the graph, which is a default value */ - size_t output_node_level = mux_graph.num_node_levels() - 1; - /* If there is a fracturable level specified for the output, we find the exact level */ - if (size_t(-1) != circuit_lib.port_lut_frac_level(output_port)) { - output_node_level = circuit_lib.port_lut_frac_level(output_port); - } - /* Deposite a zero, which is a default value */ - size_t output_node_index_at_level = 0; - /* If there are output masks, we find the node_index */ - if (!circuit_lib.port_lut_output_masks(output_port).empty()) { - output_node_index_at_level = circuit_lib.port_lut_output_masks(output_port).at(pin); - } - /* Double check the node exists in the Mux Graph */ - VTR_ASSERT(MuxNodeId::INVALID() != mux_graph.node_id(output_node_level, output_node_index_at_level)); - - /* Create the port information of the MUX input, which is the input of buffer instance */ - BasicPort instance_input_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); - - /* Create the port information of the module output at the given pin range, which is the output of buffer instance */ - BasicPort instance_output_port(module_output_port.get_name(), pin, pin); - - /* If the output is not supposed to be buffered */ - if (false == circuit_lib.is_output_buffered(circuit_model)) { - print_verilog_comment(fp, std::string("---- BEGIN short-wire a multiplexing structure output to MUX module output -----")); - - /* Short wire all the datapath inputs to the MUX inputs */ - print_verilog_wire_connection(fp, instance_output_port, instance_input_port, false); - - print_verilog_comment(fp, std::string("---- END short-wire a multiplexing structure output to MUX module output -----")); - fp << std::endl; - continue; /* Finish here */ - } - - /* Reach here, we need a buffer, create a port-to-port map and output the buffer instance */ - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an output buffer module -----")); - - /* Now we need to add intermediate buffers by instanciating the modules */ - CircuitModelId buffer_model = circuit_lib.output_buffer_model(circuit_model); - /* We must have a valid model id */ - VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - - print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, instance_input_port, instance_output_port); - - print_verilog_comment(fp, std::string("---- END Instanciation of an output buffer module -----")); - fp << std::endl; - } - } -} - -/******************************************************************** - * Generate the 4T1R-based internal logic - * (multiplexing structure) for a multiplexer in Verilog codes - * This function will : - * 1. build a multiplexing structure by instanciating the branch circuits - * generated before - * 2. add intermediate buffers between multiplexing stages if specified. - *******************************************************************/ -static -void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const ModuleId& module_id, - const CircuitModelId& circuit_model, - const MuxGraph& mux_graph) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Find the actual mux size */ - size_t mux_size = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); - - /* Get the BL and WL ports from the mux */ - std::vector mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_BLB, true); - std::vector mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_WL, true); - /* MUX graph must have only 1 BLB and 1 WL port */ - VTR_ASSERT(1 == mux_blb_ports.size()); - VTR_ASSERT(1 == mux_wl_ports.size()); - - /* Build the location map of intermediate buffers */ - std::vector inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, circuit_model, mux_graph.num_node_levels()); - - print_verilog_comment(fp, std::string("---- BEGIN Internal Logic of a RRAM-based MUX module -----")); - - print_verilog_comment(fp, std::string("---- BEGIN Internal wires of a RRAM-based MUX module -----")); - /* Print local wires which are the nodes in the mux graph */ - for (size_t level = 0; level < mux_graph.num_levels(); ++level) { - /* Print the internal wires located at this level */ - BasicPort internal_wire_port(generate_mux_node_name(level, false), mux_graph.num_nodes_at_level(level)); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl; - /* Identify if an intermediate buffer is needed */ - if (false == inter_buffer_location_map[level]) { - continue; - } - BasicPort internal_wire_buffered_port(generate_mux_node_name(level, true), mux_graph.num_nodes_at_level(level)); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl; - } - print_verilog_comment(fp, std::string("---- END Internal wires of a RRAM-based MUX module -----")); - fp << std::endl; - - /* Iterate over all the internal nodes and output nodes in the mux graph */ - for (const auto& node : mux_graph.non_input_nodes()) { - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch RRAM-based MUX module -----")); - /* Get the size of branch circuit - * Instanciate an branch circuit by the size (fan-in) of the node - */ - size_t branch_size = mux_graph.node_in_edges(node).size(); - - /* Get the node level and index in the current level */ - size_t output_node_level = mux_graph.node_level(node); - size_t output_node_index_at_level = mux_graph.node_index_at_level(node); - - /* Get the nodes which drive the root_node */ - std::vector input_nodes; - for (const auto& edge : mux_graph.node_in_edges(node)) { - /* Get the nodes drive the edge */ - for (const auto& src_node : mux_graph.edge_src_nodes(edge)) { - input_nodes.push_back(src_node); - } - } - /* Number of inputs should match the branch_input_size!!! */ - VTR_ASSERT(input_nodes.size() == branch_size); - - /* Get the mems in the branch circuits */ - std::vector mems; - for (const auto& edge : mux_graph.node_in_edges(node)) { - /* Get the mem control the edge */ - MuxMemId mem = mux_graph.find_edge_mem(edge); - /* Add the mem if it is not in the list */ - if (mems.end() == std::find(mems.begin(), mems.end(), mem)) { - mems.push_back(mem); - } - } - - /* Instanciate the branch module which is a tgate-based module - */ - std::string branch_module_name= generate_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix); - /* Get the moduleId for the submodule */ - ModuleId branch_module_id = module_manager.find_module(branch_module_name); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != branch_module_id); - - /* Create a port-to-port map */ - std::map port2port_name_map; - /* TODO: the branch module name should NOT be hard-coded. Use the port lib_name given by users! */ - - /* All the input node names organized in bus */ - std::vector branch_node_input_ports; - for (const auto& input_node : input_nodes) { - /* Generate the port info of each input node */ - size_t input_node_level = mux_graph.node_level(input_node); - size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node); - BasicPort branch_node_input_port(generate_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level); - branch_node_input_ports.push_back(branch_node_input_port); - } - - /* Create the port info for the input */ - /* TODO: the naming could be more flexible? */ - BasicPort instance_input_port = generate_verilog_bus_port(branch_node_input_ports, std::string(generate_mux_node_name(output_node_level, false) + "_in")); - /* If we have more than 1 port in the combined instance ports , - * output a local wire */ - if (1 < combine_verilog_ports(branch_node_input_ports).size()) { - /* Print a local wire for the merged ports */ - fp << "\t" << generate_verilog_local_wire(instance_input_port, branch_node_input_ports) << std::endl; - } else { - /* Safety check */ - VTR_ASSERT(1 == combine_verilog_ports(branch_node_input_ports).size()); - } - - /* Link nodes to input ports for the branch module */ - ModulePortId module_input_port_id = module_manager.find_module_port(branch_module_id, "in"); - VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); - /* Get the port from module */ - BasicPort module_input_port = module_manager.module_port(branch_module_id, module_input_port_id); - port2port_name_map[module_input_port.get_name()] = instance_input_port; - - /* Link nodes to output ports for the branch module */ - BasicPort instance_output_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); - ModulePortId module_output_port_id = module_manager.find_module_port(branch_module_id, "out"); - VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); - /* Get the port from module */ - BasicPort module_output_port = module_manager.module_port(branch_module_id, module_output_port_id); - port2port_name_map[module_output_port.get_name()] = instance_output_port; - - /* All the mem node names organized in bus - * RRAM-based MUX uses BLB and WL to control memories - */ - std::vector branch_node_blb_ports; - for (const auto& mem : mems) { - /* Generate the port info of each mem node: - */ - BasicPort branch_node_blb_port(circuit_lib.port_prefix(mux_blb_ports[0]), size_t(mem), size_t(mem)); - branch_node_blb_ports.push_back(branch_node_blb_port); - } - /* Every stage, we have an additonal BLB and WL in controlling purpose - * The additional BLB is arranged at the tail of BLB port - * For example: - * The total port width is BLB[0 ... + - 1] - * The regular BLB used by branches are BLB[0 .. - 1] - * The additional BLB used by branches are BLB[ .. + - 1] - * - * output_node_level is always larger than the mem_level by 1 - */ - branch_node_blb_ports.push_back(BasicPort(circuit_lib.port_prefix(mux_blb_ports[0]), - mux_graph.num_memory_bits() + output_node_level - 1, - mux_graph.num_memory_bits() + output_node_level - 1) - ); - - /* Create the port info for the input */ - /* TODO: the naming could be more flexible? */ - BasicPort instance_blb_port = generate_verilog_bus_port(branch_node_blb_ports, std::string(generate_mux_node_name(output_node_level, false) + "_blb")); - /* If we have more than 1 port in the combined instance ports , - * output a local wire */ - if (1 < combine_verilog_ports(branch_node_blb_ports).size()) { - /* Print a local wire for the merged ports */ - fp << "\t" << generate_verilog_local_wire(instance_blb_port, branch_node_blb_ports) << std::endl; - } else { - /* Safety check */ - VTR_ASSERT(1 == combine_verilog_ports(branch_node_blb_ports).size()); - } - - /* Link nodes to BLB ports for the branch module */ - ModulePortId module_blb_port_id = module_manager.find_module_port(branch_module_id, circuit_lib.port_prefix(mux_blb_ports[0])); - VTR_ASSERT(ModulePortId::INVALID() != module_blb_port_id); - /* Get the port from module */ - BasicPort module_blb_port = module_manager.module_port(branch_module_id, module_blb_port_id); - port2port_name_map[module_blb_port.get_name()] = instance_blb_port; - - std::vector branch_node_wl_ports; - for (const auto& mem : mems) { - /* Generate the port info of each mem node: - */ - BasicPort branch_node_blb_port(circuit_lib.port_prefix(mux_wl_ports[0]), size_t(mem), size_t(mem)); - branch_node_wl_ports.push_back(branch_node_blb_port); - } - /* Every stage, we have an additonal BLB and WL in controlling purpose - * The additional BLB is arranged at the tail of BLB port - * For example: - * The total port width is WL[0 ... + - 1] - * The regular BLB used by branches are WL[0 .. - 1] - * The additional BLB used by branches are WL[ .. + - 1] - * - * output_node_level is always larger than the mem_level by 1 - */ - branch_node_wl_ports.push_back(BasicPort(circuit_lib.port_prefix(mux_wl_ports[0]), - mux_graph.num_memory_bits() + output_node_level - 1, - mux_graph.num_memory_bits() + output_node_level - 1) - ); - - /* Create the port info for the WL */ - /* TODO: the naming could be more flexible? */ - BasicPort instance_wl_port = generate_verilog_bus_port(branch_node_wl_ports, std::string(generate_mux_node_name(output_node_level, false) + "_wl")); - /* If we have more than 1 port in the combined instance ports , - * output a local wire */ - if (1 < combine_verilog_ports(branch_node_wl_ports).size()) { - /* Print a local wire for the merged ports */ - fp << "\t" << generate_verilog_local_wire(instance_wl_port, branch_node_wl_ports) << std::endl; - } else { - /* Safety check */ - VTR_ASSERT(1 == combine_verilog_ports(branch_node_wl_ports).size()); - } - - /* Link nodes to BLB ports for the branch module */ - ModulePortId module_wl_port_id = module_manager.find_module_port(branch_module_id, circuit_lib.port_prefix(mux_wl_ports[0])); - VTR_ASSERT(ModulePortId::INVALID() != module_wl_port_id); - /* Get the port from module */ - BasicPort module_wl_port = module_manager.module_port(branch_module_id, module_wl_port_id); - port2port_name_map[module_wl_port.get_name()] = instance_wl_port; - - /* Output an instance of the module */ - print_verilog_module_instance(fp, module_manager, module_id, branch_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model)); - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(module_id, branch_module_id); - - print_verilog_comment(fp, std::string("---- END Instanciation of a branch RRAM-based MUX module -----")); - fp << std::endl; - - if (false == inter_buffer_location_map[output_node_level]) { - continue; /* No need for intermediate buffers */ - } - - print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an intermediate buffer modules -----")); - - /* Now we need to add intermediate buffers by instanciating the modules */ - CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model); - /* We must have a valid model id */ - VTR_ASSERT(CircuitModelId::INVALID() != buffer_model); - - BasicPort buffer_instance_input_port(generate_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level); - BasicPort buffer_instance_output_port(generate_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level); - - print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, buffer_instance_input_port, buffer_instance_output_port); - - print_verilog_comment(fp, std::string("---- END Instanciation of an intermediate buffer module -----")); - fp << std::endl; - } - - print_verilog_comment(fp, std::string("---- END Internal Logic of a RRAM-based MUX module -----")); - fp << std::endl; -} - -/********************************************************************* - * Generate Verilog codes modeling a RRAM-based multiplexer with the given size - * The Verilog module will consist of three parts: - * 1. instances of the branch circuits of multiplexers which are generated before - * This builds up the 4T1R-based multiplexing structure - * - * BLB WL - * | | ... - * v v - * +--------+ - * in[0]-->| | BLB WL - * ...| Branch |-----+ | | - * in -->| 0 | | v v - * [N-1] +--------+ | +--------+ - * ... -->| | - * BLBs WLs ...| Branch | - * | | ... -->| X | - * v v +--------+ - * +--------+ | - * -->| | | - * ...| Branch |----+ - * -->| i | - * +--------+ - * - * 2. Input buffers/inverters - * 3. Output buffers/inverters - *********************************************************************/ -static -void generate_verilog_rram_mux_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& circuit_model, - const std::string& module_name, - const MuxGraph& mux_graph) { - /* Error out for the conditions where we are not yet supported! */ - if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { - /* RRAM LUT is not supported now... */ - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])RRAM-based LUT is not supported (Circuit model: %s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); - exit(1); - } - - /* Get the global ports required by MUX (and any submodules) */ - std::vector mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true, true); - /* Get the input ports from the mux */ - std::vector mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true); - /* Get the output ports from the mux */ - std::vector mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true); - /* Get the BL and WL ports from the mux */ - std::vector mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_BLB, true); - std::vector mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_WL, true); - - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Generate the Verilog netlist according to the mux_graph */ - /* Find out the number of data-path inputs */ - size_t num_inputs = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()); - /* Find out the number of outputs */ - size_t num_outputs = mux_graph.num_outputs(); - /* Find out the number of memory bits */ - size_t num_mems = mux_graph.num_memory_bits(); - - /* Check codes to ensure the port of Verilog netlists will match */ - /* MUX graph must have only 1 input and 1 BLB and 1 WL port */ - VTR_ASSERT(1 == mux_input_ports.size()); - VTR_ASSERT(1 == mux_blb_ports.size()); - VTR_ASSERT(1 == mux_wl_ports.size()); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId module_id = module_manager.add_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != module_id); - /* Add module ports */ - /* Add each global port */ - for (const auto& port : mux_global_ports) { - /* Configure each global port */ - BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT); - } - /* Add each input port */ - size_t input_port_cnt = 0; - for (const auto& port : mux_input_ports) { - BasicPort input_port(circuit_lib.port_prefix(port), num_inputs); - module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT); - /* Update counter */ - input_port_cnt++; - } - /* Double check: We should have only 1 input port generated here! */ - VTR_ASSERT(1 == input_port_cnt); - - for (const auto& port : mux_output_ports) { - BasicPort output_port(circuit_lib.port_prefix(port), num_outputs); - if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { - output_port.set_width(circuit_lib.port_size(port)); - } - module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT); - } - - /* BLB port */ - for (const auto& port : mux_blb_ports) { - /* IMPORTANT: RRAM-based MUX has an additional BLB pin per level - * So, the actual port width of BLB should be added by the number of levels of the MUX graph - */ - BasicPort blb_port(circuit_lib.port_prefix(port), num_mems + mux_graph.num_levels()); - module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT); - } - - /* WL port */ - for (const auto& port : mux_wl_ports) { - /* IMPORTANT: RRAM-based MUX has an additional WL pin per level - * So, the actual port width of WL should be added by the number of levels of the MUX graph - */ - BasicPort wl_port(circuit_lib.port_prefix(port), num_mems + mux_graph.num_levels()); - module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT); - } - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, module_id); - - /* TODO: Print the internal logic in Verilog codes */ - generate_verilog_rram_mux_module_multiplexing_structure(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); - - /* Print the input and output buffers in Verilog codes */ - /* TODO, we should rename the follow functions to a generic name? Since they are applicable to both MUXes */ - generate_verilog_cmos_mux_module_input_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); - generate_verilog_cmos_mux_module_output_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); -} - - -/*********************************************** - * Generate Verilog codes modeling a multiplexer - * with the given graph-level description - **********************************************/ -static -void generate_verilog_mux_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& mux_model, - const MuxGraph& mux_graph, - const bool& use_explicit_port_map) { - std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, - find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), - std::string("")); - - /* Multiplexers built with different technology is in different organization */ - switch (circuit_lib.design_tech_type(mux_model)) { - case SPICE_MODEL_DESIGN_CMOS: { - /* Use Verilog writer to print the module to file */ - ModuleId mux_module = module_manager.find_module(module_name); - VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); - write_verilog_module_to_file(fp, module_manager, mux_module, - ( use_explicit_port_map - || circuit_lib.dump_explicit_port_map(mux_model) - || circuit_lib.dump_explicit_port_map(circuit_lib.pass_gate_logic_model(mux_model)) ) - ); - /* Add an empty line as a splitter */ - fp << std::endl; - break; - } - case SPICE_MODEL_DESIGN_RRAM: - /* TODO: RRAM-based Multiplexer Verilog module generation */ - generate_verilog_rram_mux_module(module_manager, circuit_lib, fp, mux_model, module_name, mux_graph); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", - __FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str()); - exit(1); - } -} - - -/*********************************************** - * Generate Verilog modules for all the unique - * multiplexers in the FPGA device - **********************************************/ -void print_verilog_submodule_muxes(ModuleManager& module_manager, - std::vector& netlist_names, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - t_sram_orgz_info* cur_sram_orgz_info, - const std::string& verilog_dir, - const std::string& submodule_dir, - const bool& use_explicit_port_map) { - - /* TODO: Generate modules into a .bak file now. Rename after it is verified */ - std::string verilog_fname(submodule_dir + muxes_verilog_file_name); - //verilog_fname += ".bak"; - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Print out debugging information for if the file is not opened/created properly */ - vpr_printf(TIO_MESSAGE_INFO, - "Creating Verilog netlist for Multiplexers (%s) ...\n", - verilog_fname.c_str()); - - print_verilog_file_header(fp, "Multiplexers"); - - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Generate basis sub-circuit for unique branches shared by the multiplexers */ - for (auto mux : mux_lib.muxes()) { - const MuxGraph& mux_graph = mux_lib.mux_graph(mux); - CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); - /* Create a mux graph for the branch circuit */ - std::vector branch_mux_graphs = mux_graph.build_mux_branch_graphs(); - /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */ - for (auto branch_mux_graph : branch_mux_graphs) { - generate_verilog_mux_branch_module(module_manager, circuit_lib, fp, mux_circuit_model, - find_mux_num_datapath_inputs(circuit_lib, mux_circuit_model, mux_graph.num_inputs()), - branch_mux_graph, use_explicit_port_map); - } - } - - /* Generate unique Verilog modules for the multiplexers */ - for (auto mux : mux_lib.muxes()) { - const MuxGraph& mux_graph = mux_lib.mux_graph(mux); - CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); - /* Create MUX circuits */ - generate_verilog_mux_module(module_manager, circuit_lib, fp, mux_circuit_model, mux_graph, use_explicit_port_map); - } - - /* Close the file stream */ - fp.close(); - - /* TODO: - * Scan-chain configuration circuit does not need any BLs/WLs! - * SRAM MUX does not need any reserved BL/WLs! - */ - /* Determine reserved Bit/Word Lines if a memory bank is specified, - * At least 1 BL/WL should be reserved! - */ - try_update_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, - mux_lib.max_mux_size(), mux_lib.max_mux_size()); - - /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h deleted file mode 100644 index 604e246e8..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h +++ /dev/null @@ -1,26 +0,0 @@ -/*********************************************** - * Header file for verilog_mux.cpp - **********************************************/ - -#ifndef VERILOG_MUX_H -#define VERILOG_MUX_H - -/* Include other header files which are dependency on the function declared below */ -#include -#include - -#include "circuit_library.h" -#include "mux_graph.h" -#include "mux_library.h" -#include "module_manager.h" - -void print_verilog_submodule_muxes(ModuleManager& module_manager, - std::vector& netlist_names, - const MuxLibrary& mux_lib, - const CircuitLibrary& circuit_lib, - t_sram_orgz_info* cur_sram_orgz_info, - const std::string& verilog_dir, - const std::string& submodule_dir, - const bool& use_explicit_port_map); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp deleted file mode 100644 index 4e955cc7f..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp +++ /dev/null @@ -1,445 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to generate - * a Verilog module of a pre-configured FPGA fabric - *******************************************************************/ -#include -#include - -#include "vtr_assert.h" -#include "device_port.h" -#include "util.h" - -#include "bitstream_manager_utils.h" - -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" -#include "fpga_x2p_benchmark_utils.h" - -#include "verilog_global.h" -#include "verilog_writer_utils.h" -#include "verilog_testbench_utils.h" -#include "verilog_preconfig_top_module.h" - -/******************************************************************** - * Print module declaration and ports for the pre-configured - * FPGA top module - * The module ports do exactly match the input benchmark - *******************************************************************/ -static -void print_verilog_preconfig_top_module_ports(std::fstream& fp, - const std::string& circuit_name, - const std::vector& L_logical_blocks) { - - /* Validate the file stream */ - check_file_handler(fp); - - /* Module declaration */ - fp << "module " << circuit_name << std::string(formal_verification_top_module_postfix); - fp << " (" << std::endl; - - /* Add module ports */ - size_t port_counter = 0; - - /* Port type-to-type mapping */ - std::map port_type2type_map; - port_type2type_map[VPACK_INPAD] = VERILOG_PORT_INPUT; - port_type2type_map[VPACK_OUTPAD] = VERILOG_PORT_OUTPUT; - - /* Print all the I/Os of the circuit implementation to be tested*/ - for (const t_logical_block& lb : L_logical_blocks) { - /* We only care I/O logical blocks !*/ - if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { - continue; - } - if (0 < port_counter) { - fp << "," << std::endl; - } - /* Both input and output ports have only size of 1 */ - BasicPort module_port(std::string(std::string(lb.name) + std::string(formal_verification_top_module_port_postfix)), 1); - fp << generate_verilog_port(port_type2type_map[lb.type], module_port); - - /* Update port counter */ - port_counter++; - } - - fp << ");" << std::endl; - - /* Add an empty line as a splitter */ - fp << std::endl; -} - -/******************************************************************** - * Print internal wires for the pre-configured FPGA top module - * The internal wires are tailored for the ports of FPGA top module - * which will be different in various configuration protocols - *******************************************************************/ -static -void print_verilog_preconfig_top_module_internal_wires(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Global ports of top-level module */ - print_verilog_comment(fp, std::string("----- Local wires for FPGA fabric -----")); - for (const ModulePortId& module_port_id : module_manager.module_ports(top_module)) { - BasicPort module_port = module_manager.module_port(top_module, module_port_id); - fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl; - } - /* Add an empty line as a splitter */ - fp << std::endl; -} - -/******************************************************************** - * Connect global ports of FPGA top module to constants except: - * 1. operating clock, which should be wired to the clock port of - * this pre-configured FPGA top module - *******************************************************************/ -static -void print_verilog_preconfig_top_module_connect_global_ports(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const std::vector& benchmark_clock_port_names) { - /* Validate the file stream */ - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- Begin Connect Global ports of FPGA top module -----")); - - /* Global ports of the top module in module manager do not carry any attributes, - * such as is_clock, is_set, etc. - * Therefore, for each global port in the top module, we find the circuit port in the circuit library - * which share the same name. We can access to the attributes. - * To gurantee the correct link between global ports in module manager and those in circuit library - * We have performed some critical check in check_circuit_library() for global ports, - * where we guarantee all the global ports share the same name must have the same attributes. - * So that each global port with the same name is unique! - */ - for (const BasicPort& module_global_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) { - CircuitPortId linked_circuit_port_id = CircuitPortId::INVALID(); - /* Find the circuit port with the same name */ - for (const CircuitPortId& circuit_port_id : global_ports) { - if (0 != module_global_port.get_name().compare(circuit_lib.port_prefix(circuit_port_id))) { - continue; - } - linked_circuit_port_id = circuit_port_id; - break; - } - /* Must find one valid circuit port */ - VTR_ASSERT(CircuitPortId::INVALID() != linked_circuit_port_id); - /* Port size should match! */ - VTR_ASSERT(module_global_port.get_width() == circuit_lib.port_size(linked_circuit_port_id)); - /* Now, for operating clock port, we should wire it to the clock of benchmark! */ - if ( (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(linked_circuit_port_id)) - && (false == circuit_lib.port_is_prog(linked_circuit_port_id)) ) { - /* Wiring to each pin of the global port: benchmark clock is always 1-bit */ - for (const size_t& pin : module_global_port.pins()) { - for (const std::string& clock_port_name : benchmark_clock_port_names) { - BasicPort module_clock_pin(module_global_port.get_name(), pin, pin); - BasicPort benchmark_clock_pin(clock_port_name + std::string(formal_verification_top_module_port_postfix), 1); - print_verilog_wire_connection(fp, module_clock_pin, benchmark_clock_pin, false); - } - } - /* Finish, go to the next */ - continue; - } - - /* For other ports, give an default value */ - std::vector default_values(module_global_port.get_width(), circuit_lib.port_default_value(linked_circuit_port_id)); - print_verilog_wire_constant_values(fp, module_global_port, default_values); - } - - print_verilog_comment(fp, std::string("----- End Connect Global ports of FPGA top module -----")); - - /* Add an empty line as a splitter */ - fp << std::endl; -} - -/******************************************************************** - * Impose the bitstream on the configuration memories - * This function uses 'assign' syntax to impost the bitstream at mem port - * while uses 'force' syntax to impost the bitstream at mem_inv port - *******************************************************************/ -static -void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const BitstreamManager& bitstream_manager) { - /* Validate the file stream */ - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- Begin assign bitstream to configuration memories -----")); - - for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) { - /* We only cares blocks with configuration bits */ - if (0 == bitstream_manager.block_bits(config_block_id).size()) { - continue; - } - /* Build the hierarchical path of the configuration bit in modules */ - std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id); - /* Drop the first block, which is the top module, it should be replaced by the instance name here */ - /* Ensure that this is the module we want to drop! */ - VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))); - block_hierarchy.erase(block_hierarchy.begin()); - /* Build the full hierarchy path */ - std::string bit_hierarchy_path(formal_verification_top_module_uut_name); - for (const ConfigBlockId& temp_block : block_hierarchy) { - bit_hierarchy_path += std::string("."); - bit_hierarchy_path += bitstream_manager.block_name(temp_block); - } - bit_hierarchy_path += std::string("."); - - /* Find the bit index in the parent block */ - BasicPort config_data_port(bit_hierarchy_path + generate_configuration_chain_data_out_name(), - bitstream_manager.block_bits(config_block_id).size()); - - /* Wire it to the configuration bit: access both data out and data outb ports */ - std::vector config_data_values; - for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { - config_data_values.push_back(bitstream_manager.bit_value(config_bit)); - } - print_verilog_wire_constant_values(fp, config_data_port, config_data_values); - } - - fp << "initial begin" << std::endl; - - for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) { - /* We only cares blocks with configuration bits */ - if (0 == bitstream_manager.block_bits(config_block_id).size()) { - continue; - } - /* Build the hierarchical path of the configuration bit in modules */ - std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id); - /* Drop the first block, which is the top module, it should be replaced by the instance name here */ - /* Ensure that this is the module we want to drop! */ - VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))); - block_hierarchy.erase(block_hierarchy.begin()); - /* Build the full hierarchy path */ - std::string bit_hierarchy_path(formal_verification_top_module_uut_name); - for (const ConfigBlockId& temp_block : block_hierarchy) { - bit_hierarchy_path += std::string("."); - bit_hierarchy_path += bitstream_manager.block_name(temp_block); - } - bit_hierarchy_path += std::string("."); - - /* Find the bit index in the parent block */ - BasicPort config_datab_port(bit_hierarchy_path + generate_configuration_chain_inverted_data_out_name(), - bitstream_manager.block_bits(config_block_id).size()); - - std::vector config_datab_values; - for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { - config_datab_values.push_back(!bitstream_manager.bit_value(config_bit)); - } - print_verilog_force_wire_constant_values(fp, config_datab_port, config_datab_values); - } - - fp << "end" << std::endl; - - print_verilog_comment(fp, std::string("----- End assign bitstream to configuration memories -----")); -} - -/******************************************************************** - * Impose the bitstream on the configuration memories - * This function uses '$deposit' syntax to do so - *******************************************************************/ -static -void print_verilog_preconfig_top_module_deposit_bitstream(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const BitstreamManager& bitstream_manager) { - /* Validate the file stream */ - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- Begin deposit bitstream to configuration memories -----")); - - fp << "initial begin" << std::endl; - - for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) { - /* We only cares blocks with configuration bits */ - if (0 == bitstream_manager.block_bits(config_block_id).size()) { - continue; - } - /* Build the hierarchical path of the configuration bit in modules */ - std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id); - /* Drop the first block, which is the top module, it should be replaced by the instance name here */ - /* Ensure that this is the module we want to drop! */ - VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))); - block_hierarchy.erase(block_hierarchy.begin()); - /* Build the full hierarchy path */ - std::string bit_hierarchy_path(formal_verification_top_module_uut_name); - for (const ConfigBlockId& temp_block : block_hierarchy) { - bit_hierarchy_path += std::string("."); - bit_hierarchy_path += bitstream_manager.block_name(temp_block); - } - bit_hierarchy_path += std::string("."); - - /* Find the bit index in the parent block */ - BasicPort config_data_port(bit_hierarchy_path + generate_configuration_chain_data_out_name(), - bitstream_manager.block_bits(config_block_id).size()); - - BasicPort config_datab_port(bit_hierarchy_path + generate_configuration_chain_inverted_data_out_name(), - bitstream_manager.block_bits(config_block_id).size()); - - /* Wire it to the configuration bit: access both data out and data outb ports */ - std::vector config_data_values; - for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { - config_data_values.push_back(bitstream_manager.bit_value(config_bit)); - } - print_verilog_deposit_wire_constant_values(fp, config_data_port, config_data_values); - - std::vector config_datab_values; - for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { - config_datab_values.push_back(!bitstream_manager.bit_value(config_bit)); - } - print_verilog_deposit_wire_constant_values(fp, config_datab_port, config_datab_values); - } - - fp << "end" << std::endl; - - print_verilog_comment(fp, std::string("----- End deposit bitstream to configuration memories -----")); -} - -/******************************************************************** - * Impose the bitstream on the configuration memories - * We branch here for different simulators: - * 1. iVerilog Icarus prefers using 'assign' syntax to force the values - * 2. Mentor Modelsim prefers using '$deposit' syntax to do so - *******************************************************************/ -static -void print_verilog_preconfig_top_module_load_bitstream(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const BitstreamManager& bitstream_manager) { - print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----")); - - print_verilog_preprocessing_flag(fp, std::string(icarus_simulator_flag)); - - /* Use assign syntax for Icarus simulator */ - print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module, bitstream_manager); - - fp << "`else" << std::endl; - - /* Use assign syntax for Icarus simulator */ - print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, bitstream_manager); - - print_verilog_endif(fp); - - print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----")); -} - - -/******************************************************************** - * Top-level function to generate a Verilog module of - * a pre-configured FPGA fabric. - * - * Pre-configured FPGA fabric - * +-------------------------------------------- - * | - * | FPGA fabric - * | +-------------------------------+ - * | | | - * | 0/1---->|FPGA global ports | - * | | | - * benchmark_clock----->|--------->|FPGA_clock | - * | | | - * benchmark_inputs---->|--------->|FPGA mapped I/Os | - * | | | - * benchmark_outputs<---|<---------|FPGA mapped I/Os | - * | | | - * | 0/1---->|FPGA unmapped I/Os | - * | | | - * fabric_bitstream---->|--------->|Internal_configuration_ports | - * | +-------------------------------+ - * | - * +------------------------------------------- - * - * Note: we do NOT put this module in the module manager. - * Because, it is not a standard module, where we force configuration signals - * This module is a wrapper for the FPGA fabric to be compatible in - * the port map of input benchmark. - * It includes wires to force constant values to part of FPGA datapath I/Os - * All these are hard to implement as a module in module manager - *******************************************************************/ -void print_verilog_preconfig_top_module(const ModuleManager& module_manager, - const BitstreamManager& bitstream_manager, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const std::string& circuit_name, - const std::string& verilog_fname, - const std::string& verilog_dir) { - vpr_printf(TIO_MESSAGE_INFO, - "Writing pre-configured FPGA top-level Verilog netlist for design %s...", - circuit_name.c_str()); - - /* Start time count */ - clock_t t_start = clock(); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - /* Validate the file stream */ - check_file_handler(fp); - - /* Generate a brief description on the Verilog file*/ - std::string title = std::string("Verilog netlist for pre-configured FPGA fabric by design: ") + circuit_name; - print_verilog_file_header(fp, title); - - /* Print preprocessing flags and external netlists */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(defines_verilog_simulation_file_name))); - - /* Print module declaration and ports */ - print_verilog_preconfig_top_module_ports(fp, circuit_name, L_logical_blocks); - - /* Find the top_module */ - ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name()); - VTR_ASSERT(true == module_manager.valid_module_id(top_module)); - - /* Print internal wires */ - print_verilog_preconfig_top_module_internal_wires(fp, module_manager, top_module); - - /* Instanciate FPGA top-level module */ - print_verilog_testbench_fpga_instance(fp, module_manager, top_module, - std::string(formal_verification_top_module_uut_name)); - - /* Find clock ports in benchmark */ - std::vector benchmark_clock_port_names = find_benchmark_clock_port_name(L_logical_blocks); - - /* Connect FPGA top module global ports to constant or benchmark global signals! */ - print_verilog_preconfig_top_module_connect_global_ports(fp, module_manager, top_module, - circuit_lib, global_ports, - benchmark_clock_port_names); - - /* Connect I/Os to benchmark I/Os or constant driver */ - print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module, - L_logical_blocks, device_size, L_grids, - L_blocks, - std::string(formal_verification_top_module_port_postfix), - std::string(formal_verification_top_module_port_postfix), - (size_t)verilog_default_signal_init_value); - - /* Assign FPGA internal SRAM/Memory ports to bitstream values */ - print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module, - bitstream_manager); - - /* Testbench ends*/ - print_verilog_module_end(fp, std::string(circuit_name) + std::string(formal_verification_top_module_postfix)); - - /* Close the file stream */ - fp.close(); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h deleted file mode 100644 index aae0a5c67..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef VERILOG_PRECONFIG_TOP_MODULE_H -#define VERILOG_PRECONFIG_TOP_MODULE_H - -#include -#include -#include "spice_types.h" -#include "vpr_types.h" -#include "module_manager.h" -#include "bitstream_manager.h" - -void print_verilog_preconfig_top_module(const ModuleManager& module_manager, - const BitstreamManager& bitstream_manager, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const std::string& circuit_name, - const std::string& verilog_fname, - const std::string& verilog_dir); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.cpp deleted file mode 100644 index eacdb2b19..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.cpp +++ /dev/null @@ -1,355 +0,0 @@ -/********************************************************************* - * This file includes functions that are used for - * Verilog generation of FPGA routing architecture (global routing) - *********************************************************************/ -#include -#include "vtr_assert.h" - -/* Include FPGA-X2P header files*/ -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -/* Include FPGA-Verilog header files*/ -#include "verilog_global.h" -#include "verilog_writer_utils.h" -#include "verilog_module_writer.h" -#include "verilog_routing.h" - -/******************************************************************** - * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY]) - * Actually it is very similiar to switch box but - * the difference is connection boxes connect Grid INPUT Pins to channels - * NOTE: direct connection between CLBs should NOT be included inside this - * module! They should be added in the top-level module as their connection - * is not limited to adjacent CLBs!!! - * - * Location of a X- and Y-direction Connection Block in FPGA fabric - * +------------+ +-------------+ - * | |------>| | - * | CLB |<------| Y-direction | - * | | ... | Connection | - * | |------>| Block | - * +------------+ +-------------+ - * | ^ ... | | ^ ... | - * v | v v | v - * +-------------------+ +-------------+ - * --->| |--->| | - * <---| X-direction |<---| Switch | - * ...| Connection block |... | Block | - * --->| |--->| | - * +-------------------+ +-------------+ - * - * Internal structure: - * This is an example of a X-direction connection block - * Note that middle output ports are shorted wire from inputs of routing tracks, - * which are also the inputs of routing multiplexer of the connection block - * - * CLB Input Pins - * (IPINs) - * ^ ^ ^ - * | | ... | - * +--------------------------+ - * | ^ ^ ^ | - * | | | ... | | - * | +--------------------+ | - * | | routing | | - * | | multiplexers | | - * | +--------------------+ | - * | middle outputs | - * | of routing channel | - * | ^ ^ ^ ^ ^ ^ ^ ^ | - * | | | | | ... | | | | | - * in[0] -->|------------------------->|---> out[0] - * out[1] <--|<-------------------------|<--- in[1] - * | ... | - * in[W-2] -->|------------------------->|---> out[W-2] - * out[W-1] <--|<-------------------------|<--- in[W-1] - * +--------------------------+ - * - * W: routing channel width - * - ********************************************************************/ -static -void print_verilog_routing_connection_box_unique_module(ModuleManager& module_manager, - std::vector& netlist_names, - const std::string& verilog_dir, - const std::string& subckt_dir, - const RRGSB& rr_gsb, - const t_rr_type& cb_type, - const bool& use_explicit_port_map) { - /* Create the netlist */ - vtr::Point gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)); - std::string verilog_fname(subckt_dir + generate_connection_block_netlist_name(cb_type, gsb_coordinate, std::string(verilog_netlist_file_postfix))); - /* TODO: remove the bak file when the file is ready */ - //verilog_fname += ".bak"; - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]")); - - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate)); - VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); - - /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, cb_module, use_explicit_port_map); - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Close file handler */ - fp.close(); - - /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); -} - -/********************************************************************* - * Generate the Verilog module for a Switch Box. - * A Switch Box module consists of following ports: - * 1. Channel Y [x][y] inputs - * 2. Channel X [x+1][y] inputs - * 3. Channel Y [x][y-1] outputs - * 4. Channel X [x][y] outputs - * 5. Grid[x][y+1] Right side outputs pins - * 6. Grid[x+1][y+1] Left side output pins - * 7. Grid[x+1][y+1] Bottom side output pins - * 8. Grid[x+1][y] Top side output pins - * 9. Grid[x+1][y] Left side output pins - * 10. Grid[x][y] Right side output pins - * 11. Grid[x][y] Top side output pins - * 12. Grid[x][y+1] Bottom side output pins - * - * Location of a Switch Box in FPGA fabric: - * - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y+1] | [x][y+1] | [x+1][y+1] | - * | | | | - * -------------- -------------- - * ---------- - * ChanX | Switch | ChanX - * [x][y] | Box | [x+1][y] - * | [x][y] | - * ---------- - * -------------- -------------- - * | | | | - * | Grid | ChanY | Grid | - * | [x][y] | [x][y] | [x+1][y] | - * | | | | - * -------------- -------------- - * - * Switch Block pin location map - * - * Grid[x][y+1] ChanY[x][y+1] Grid[x+1][y+1] - * right_pins inputs/outputs left_pins - * | ^ | - * | | | - * v v v - * +-----------------------------------------------+ - * | | - * Grid[x][y+1] | | Grid[x+1][y+1] - * bottom_pins---->| |<---- bottom_pins - * | | - * ChanX[x][y] | Switch Box [x][y] | ChanX[x+1][y] - * inputs/outputs<--->| |<---> inputs/outputs - * | | - * Grid[x][y+1] | | Grid[x+1][y+1] - * top_pins---->| |<---- top_pins - * | | - * +-----------------------------------------------+ - * ^ ^ ^ - * | | | - * | v | - * Grid[x][y] ChanY[x][y] Grid[x+1][y] - * right_pins inputs/outputs left_pins - * - * - ********************************************************************/ -static -void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manager, - std::vector& netlist_names, - const std::string& verilog_dir, - const std::string& subckt_dir, - const RRGSB& rr_gsb, - const bool& use_explicit_port_map) { - /* Create the netlist */ - vtr::Point gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); - std::string verilog_fname(subckt_dir + generate_routing_block_netlist_name(sb_verilog_file_name_prefix, gsb_coordinate, std::string(verilog_netlist_file_postfix))); - /* TODO: remove the bak file when the file is ready */ - //verilog_fname += ".bak"; - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]")); - - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate)); - VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); - - /* Write the verilog module */ - write_verilog_module_to_file(fp, module_manager, sb_module, use_explicit_port_map); - - /* Close file handler */ - fp.close(); - - /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); -} - -/******************************************************************** - * Iterate over all the connection blocks in a device - * and build a module for each of them - *******************************************************************/ -static -void print_verilog_flatten_connection_block_modules(ModuleManager& module_manager, - std::vector& netlist_names, - const DeviceRRGSB& L_device_rr_gsb, - const std::string& verilog_dir, - const std::string& subckt_dir, - const t_rr_type& cb_type, - const bool& use_explicit_port_map) { - /* Build unique X-direction connection block modules */ - DeviceCoordinator cb_range = L_device_rr_gsb.get_gsb_range(); - - for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { - /* Check if the connection block exists in the device! - * Some of them do NOT exist due to heterogeneous blocks (height > 1) - * We will skip those modules - */ - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) - || (true != rr_gsb.is_cb_exist(cb_type))) { - continue; - } - print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, - verilog_dir, - subckt_dir, - rr_gsb, cb_type, - use_explicit_port_map); - } - } -} - -/******************************************************************** - * A top-level function of this file - * Print all the modules for global routing architecture of a FPGA fabric - * in Verilog format in a flatten way: - * Each connection block and switch block will be generated as a unique module - * Covering: - * 1. Connection blocks - * 2. Switch blocks - *******************************************************************/ -void print_verilog_flatten_routing_modules(ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const t_det_routing_arch& routing_arch, - const std::string& verilog_dir, - const std::string& subckt_dir, - const bool& use_explicit_port_map) { - /* We only support uni-directional routing architecture now */ - VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); - - /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ - std::vector netlist_names; - - /* TODO: deprecate DeviceCoordinator, use vtr::Point only! */ - DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); - - /* Build unique switch block modules */ - for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { - const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - print_verilog_routing_switch_box_unique_module(module_manager, netlist_names, - verilog_dir, - subckt_dir, - rr_gsb, - use_explicit_port_map); - } - } - - print_verilog_flatten_connection_block_modules(module_manager, netlist_names, L_device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map); - - print_verilog_flatten_connection_block_modules(module_manager, netlist_names, L_device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map); - - vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n"); - print_verilog_netlist_include_header_file(netlist_names, - subckt_dir.c_str(), - routing_verilog_file_name); -} - - -/******************************************************************** - * A top-level function of this file - * Print all the unique modules for global routing architecture of a FPGA fabric - * in Verilog format, including: - * 1. Connection blocks - * 2. Switch blocks - * - * Note: this function SHOULD be called only when - * the option compact_routing_hierarchy is turned on!!! - *******************************************************************/ -void print_verilog_unique_routing_modules(ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const t_det_routing_arch& routing_arch, - const std::string& verilog_dir, - const std::string& subckt_dir, - const bool& use_explicit_port_map) { - /* We only support uni-directional routing architecture now */ - VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); - - /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ - std::vector netlist_names; - - /* Build unique switch block modules */ - for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(isb); - print_verilog_routing_switch_box_unique_module(module_manager, netlist_names, - verilog_dir, - subckt_dir, - unique_mirror, - use_explicit_port_map); - } - - /* Build unique X-direction connection block modules */ - for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANX, icb); - - print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, - verilog_dir, - subckt_dir, - unique_mirror, CHANX, - use_explicit_port_map); - } - - /* Build unique X-direction connection block modules */ - for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { - const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANY, icb); - - print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, - verilog_dir, - subckt_dir, - unique_mirror, CHANY, - use_explicit_port_map); - } - - vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n"); - print_verilog_netlist_include_header_file(netlist_names, - subckt_dir.c_str(), - routing_verilog_file_name); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h deleted file mode 100644 index 1c09c2ef2..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ /dev/null @@ -1,26 +0,0 @@ -/*********************************************** - * Header file for verilog_routing.cpp - **********************************************/ -#ifndef VERILOG_ROUTING_H -#define VERILOG_ROUTING_H - -/* Include other header files which are dependency on the function declared below */ -#include "mux_library.h" -#include "module_manager.h" -#include "rr_blocks.h" - -void print_verilog_flatten_routing_modules(ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const t_det_routing_arch& routing_arch, - const std::string& verilog_dir, - const std::string& subckt_dir, - const bool& use_explicit_port_map); - -void print_verilog_unique_routing_modules(ModuleManager& module_manager, - const DeviceRRGSB& L_device_rr_gsb, - const t_det_routing_arch& routing_arch, - const std::string& verilog_dir, - const std::string& subckt_dir, - const bool& use_explicit_port_map); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp deleted file mode 100644 index 5a9838b3c..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp +++ /dev/null @@ -1,236 +0,0 @@ -/************************************************ - * This file includes most utilized functions for - * generating Verilog sub-modules - * such as timing matrix and signal initialization - ***********************************************/ -#include -#include -#include -#include "vtr_assert.h" - -/* Device-level header files */ -#include "spice_types.h" -#include "device_port.h" - -/* FPGA-X2P context header files */ -#include "fpga_x2p_utils.h" -#include "module_manager_utils.h" - -/* FPGA-Verilog context header files */ -#include "verilog_global.h" -#include "verilog_writer_utils.h" -#include "verilog_submodule_utils.h" - -/* All values are printed with this precision value. The higher the - * value, the more accurate timing assignment is. Using a number of 6 - * guarentees that a precision of femtosecond which is sufficent for - * electrical simulation (simulation timescale is 10-9 - */ -/* constexpr int FLOAT_PRECISION = std::numeric_limits::max_digits10; */ -constexpr int FLOAT_PRECISION = 6; - -/************************************************ - * Print a timing matrix defined in theecircuit model - * into a Verilog format. - * This function print all the timing edges available - * in the circuit model (any pin-to-pin delay) - ***********************************************/ -void print_verilog_submodule_timing(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - /* return if there is no delay info */ - if ( 0 == circuit_lib.num_delay_info(circuit_model)) { - return; - } - - /* Return if there is no ports */ - if (0 == circuit_lib.num_model_ports(circuit_model)) { - return; - } - - /* Ensure a valid file handler*/ - check_file_handler(fp); - - fp << std::endl; - fp << "`ifdef " << verilog_timing_preproc_flag << std::endl; - print_verilog_comment(fp, std::string("------ BEGIN Pin-to-pin Timing constraints -----")); - fp << "\tspecify" << std::endl; - - /* Read out pin-to-pin delays by finding out all the edges belonging to a circuit model */ - for (const auto& timing_edge : circuit_lib.timing_edges_by_model(circuit_model)) { - CircuitPortId src_port = circuit_lib.timing_edge_src_port(timing_edge); - size_t src_pin = circuit_lib.timing_edge_src_pin(timing_edge); - BasicPort src_port_info(circuit_lib.port_lib_name(src_port), src_pin, src_pin); - - CircuitPortId sink_port = circuit_lib.timing_edge_sink_port(timing_edge); - size_t sink_pin = circuit_lib.timing_edge_sink_pin(timing_edge); - BasicPort sink_port_info(circuit_lib.port_lib_name(sink_port), sink_pin, sink_pin); - - fp << "\t\t"; - fp << "(" << generate_verilog_port(VERILOG_PORT_CONKT, src_port_info); - fp << " => "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, sink_port_info) << ")"; - fp << " = "; - fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE) / verilog_sim_timescale; - fp << ", "; - fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_FALL) / verilog_sim_timescale << ")"; - fp << ";" << std::endl; - } - - fp << "\tendspecify" << std::endl; - print_verilog_comment(fp, std::string("------ END Pin-to-pin Timing constraints -----")); - fp << "`endif" << std::endl; - -} - -void print_verilog_submodule_signal_init(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - /* Ensure a valid file handler*/ - check_file_handler(fp); - - fp << std::endl; - fp << "`ifdef " << verilog_signal_init_preproc_flag << std::endl; - print_verilog_comment(fp, std::string("------ BEGIN driver initialization -----")); - fp << "\tinitial begin" << std::endl; - fp << "\t`ifdef " << verilog_formal_verification_preproc_flag << std::endl; - - /* Only for formal verification: deposite a zero signal values */ - /* Initialize each input port */ - for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) { - BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); - fp << "\t\t$deposit("; - fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); - fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0'); - fp << ");" << std::endl; - } - fp << "\t`else" << std::endl; - - /* Regular case: deposite initial signal values: a random value */ - for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) { - BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); - fp << "\t\t$deposit("; - fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); - fp << ", $random);" << std::endl; - } - - fp << "\t`endif\n" << std::endl; - fp << "\tend" << std::endl; - print_verilog_comment(fp, std::string("------ END driver initialization -----")); - fp << "`endif" << std::endl; -} - -/********************************************************************* - * Register all the user-defined modules in the module manager - * Walk through the circuit library and add user-defined circuit models - * to the module_manager - ********************************************************************/ -void add_user_defined_verilog_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib) { - /* Iterate over Verilog modules */ - for (const auto& model : circuit_lib.models()) { - /* We only care about user-defined models */ - if (true == circuit_lib.model_verilog_netlist(model).empty()) { - continue; - } - /* Skip Routing channel wire models because they need a different name. Do it later */ - if (SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) { - continue; - } - /* Reach here, the model requires a user-defined Verilog netlist, - * Try to find it in the module manager - * If not found, register it in the module_manager - */ - ModuleId module_id = module_manager.find_module(circuit_lib.model_name(model)); - if (ModuleId::INVALID() == module_id) { - add_circuit_model_to_module_manager(module_manager, circuit_lib, model); - } - } -} - -/********************************************************************* - * Print a template for a user-defined circuit model - * The template will include just the port declaration of the Verilog module - * The template aims to help user to write Verilog codes with a guaranteed - * module definition, which can be correctly instanciated (with correct - * port mapping) in the FPGA fabric - ********************************************************************/ -static -void print_one_verilog_template_module(const ModuleManager& module_manager, - std::fstream& fp, - const std::string& module_name) { - /* Ensure a valid file handler*/ - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- Template Verilog module for " + module_name + " -----")); - - /* Find the module in module manager, which should be already registered */ - /* TODO: routing channel wire model may have a different name! */ - ModuleId template_module = module_manager.find_module(module_name); - VTR_ASSERT(ModuleId::INVALID() != template_module); - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, template_module); - /* Finish dumping ports */ - - print_verilog_comment(fp, std::string("----- Internal logic should start here -----")); - - /* Add some empty lines as placeholders for the internal logic*/ - fp << std::endl << std::endl; - - print_verilog_comment(fp, std::string("----- Internal logic should end here -----")); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); - - /* Add an empty line as a splitter */ - fp << std::endl; -} - -/********************************************************************* - * Print a template of all the submodules that are user-defined - * The template will include just the port declaration of the submodule - * The template aims to help user to write Verilog codes with a guaranteed - * module definition, which can be correctly instanciated (with correct - * port mapping) in the FPGA fabric - ********************************************************************/ -void print_verilog_submodule_templates(const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, - const std::string& submodule_dir) { - std::string verilog_fname(submodule_dir + user_defined_template_verilog_file_name); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Print out debugging information for if the file is not opened/created properly */ - vpr_printf(TIO_MESSAGE_INFO, - "Creating template for user-defined Verilog modules (%s)...\n", - verilog_fname.c_str()); - - print_verilog_file_header(fp, "Template for user-defined Verilog modules"); - - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Output essential models*/ - for (const auto& model : circuit_lib.models()) { - /* Focus on user-defined modules, which must have a Verilog netlist defined */ - if (circuit_lib.model_verilog_netlist(model).empty()) { - continue; - } - /* Skip Routing channel wire models because they need a different name. Do it later */ - if (SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) { - continue; - } - /* Print a Verilog template for the circuit model */ - print_one_verilog_template_module(module_manager, fp, circuit_lib.model_name(model)); - } - - /* close file stream */ - fp.close(); - - /* No need to add the template to the subckt include files! */ -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.h deleted file mode 100644 index 91f0828f8..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.h +++ /dev/null @@ -1,32 +0,0 @@ -/************************************************ - * Header file for verilog_submodule_utils.cpp - * Include function declaration on - * most utilized functions for Verilog modules - * such as timing matrix and signal initialization - ***********************************************/ - -#ifndef VERILOG_SUBMODULE_UTILS_H -#define VERILOG_SUBMODULE_UTILS_H - -#include -#include -#include "module_manager.h" -#include "circuit_library.h" - -void print_verilog_submodule_timing(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model); - -void print_verilog_submodule_signal_init(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model); - -void add_user_defined_verilog_modules(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib); - -void print_verilog_submodule_templates(const ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, - const std::string& submodule_dir); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.cpp deleted file mode 100644 index 7169ce491..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.cpp +++ /dev/null @@ -1,102 +0,0 @@ -/********************************************************************* - * This file includes top-level function to generate Verilog primitive modules - * and print them to files - ********************************************************************/ -/* Standard header files */ - -/* External library header files */ -#include "util.h" - -/* FPGA-Verilog header files */ -#include "verilog_submodule_utils.h" -#include "verilog_essential_gates.h" -#include "verilog_decoders.h" -#include "verilog_mux.h" -#include "verilog_lut.h" -#include "verilog_wire.h" -#include "verilog_memory.h" -#include "verilog_writer_utils.h" - -/* Header file for this source file */ -#include "verilog_submodules.h" - -/********************************************************************* - * Top-level function to generate primitive modules: - * 1. Logic gates: AND/OR, inverter, buffer and transmission-gate/pass-transistor - * 2. Routing multiplexers - * 3. Local encoders for routing multiplexers - * 4. Wires - * 5. Configuration memory blocks - * 6. Verilog template - ********************************************************************/ -void print_verilog_submodules(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - t_sram_orgz_info* cur_sram_orgz_info, - const char* verilog_dir, - const char* submodule_dir, - const t_arch& Arch, - const t_syn_verilog_opts& fpga_verilog_opts) { - - /* Register all the user-defined modules in the module manager - * This should be done prior to other steps in this function, - * because they will be instanciated by other primitive modules - */ - vpr_printf(TIO_MESSAGE_INFO, - "Registering user-defined modules...\n"); - - /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ - std::vector netlist_names; - - add_user_defined_verilog_modules(module_manager, Arch.spice->circuit_lib); - - print_verilog_submodule_essentials(module_manager, - netlist_names, - std::string(verilog_dir), - std::string(submodule_dir), - Arch.spice->circuit_lib); - - /* Routing multiplexers */ - vpr_printf(TIO_MESSAGE_INFO, - "Generating modules for routing multiplexers...\n"); - - /* NOTE: local decoders generation must go before the MUX generation!!! - * because local decoders modules will be instanciated in the MUX modules - */ - print_verilog_submodule_mux_local_decoders(module_manager, netlist_names, - mux_lib, Arch.spice->circuit_lib, - std::string(verilog_dir), std::string(submodule_dir)); - print_verilog_submodule_muxes(module_manager, netlist_names, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info, - std::string(verilog_dir), std::string(submodule_dir), - fpga_verilog_opts.dump_explicit_verilog); - - - /* LUTes */ - vpr_printf(TIO_MESSAGE_INFO, - "Generating modules for LUTs...\n"); - print_verilog_submodule_luts(module_manager, netlist_names, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir), - fpga_verilog_opts.dump_explicit_verilog); - - /* Hard wires */ - print_verilog_submodule_wires(module_manager, netlist_names, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); - - /* 4. Memories */ - vpr_printf(TIO_MESSAGE_INFO, - "Generating modules for configuration memory blocks...\n"); - print_verilog_submodule_memories(module_manager, netlist_names, - mux_lib, Arch.spice->circuit_lib, - std::string(verilog_dir), std::string(submodule_dir), - fpga_verilog_opts.dump_explicit_verilog); - - /* 5. Dump template for all the modules */ - if (TRUE == fpga_verilog_opts.print_user_defined_template) { - print_verilog_submodule_templates(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); - } - - /* Create a header file to include all the subckts */ - vpr_printf(TIO_MESSAGE_INFO, - "Generating header file for primitive modules...\n"); - print_verilog_netlist_include_header_file(netlist_names, - submodule_dir, - submodule_verilog_file_name); -} - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h deleted file mode 100644 index a4d57d8c3..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef VERILOG_SUBMODULES_H -#define VERILOG_SUBMODULES_H - -#include "vpr_types.h" -#include "module_manager.h" -#include "mux_library.h" - -void print_verilog_submodules(ModuleManager& module_manager, - const MuxLibrary& mux_lib, - t_sram_orgz_info* cur_sram_orgz_info, - const char* verilog_dir, - const char* submodule_dir, - const t_arch& Arch, - const t_syn_verilog_opts& fpga_verilog_opts); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp deleted file mode 100644 index 9293c7cf6..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp +++ /dev/null @@ -1,563 +0,0 @@ -/******************************************************************** - * This file includes most utilized functions that are used to create - * Verilog testbenches - * - * Note: please try to avoid using global variables in this file - * so that we can make it free to use anywhere - *******************************************************************/ -#include - -#include "vtr_assert.h" -#include "device_port.h" - -#include "fpga_x2p_utils.h" -#include "fpga_x2p_benchmark_utils.h" - -#include "verilog_writer_utils.h" -#include "verilog_testbench_utils.h" - -/******************************************************************** - * Print an instance of the FPGA top-level module - *******************************************************************/ -void print_verilog_testbench_fpga_instance(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const std::string& top_instance_name) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Include defined top-level module */ - print_verilog_comment(fp, std::string("----- FPGA top-level module to be capsulated -----")); - - /* Create an empty port-to-port name mapping, because we use default names */ - std::map port2port_name_map; - - /* Use explicit port mapping for a clean instanciation */ - print_verilog_module_instance(fp, module_manager, top_module, - top_instance_name, - port2port_name_map, true); - - /* Add an empty line as a splitter */ - fp << std::endl; -} - -/******************************************************************** - * Instanciate the input benchmark module - *******************************************************************/ -void print_verilog_testbench_benchmark_instance(std::fstream& fp, - const std::string& module_name, - const std::string& instance_name, - const std::string& module_input_port_postfix, - const std::string& module_output_port_postfix, - const std::string& output_port_postfix, - const std::vector& L_logical_blocks, - const bool& use_explicit_port_map) { - /* Validate the file stream */ - check_file_handler(fp); - - fp << "\t" << module_name << " " << instance_name << "(" << std::endl; - - size_t port_counter = 0; - for (const t_logical_block& lb : L_logical_blocks) { - /* Bypass non-I/O logical blocks ! */ - if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { - continue; - } - /* The first port does not need a comma */ - if(0 < port_counter){ - fp << "," << std::endl; - } - /* Input port follows the logical block name while output port requires a special postfix */ - if (VPACK_INPAD == lb.type){ - fp << "\t\t"; - if (true == use_explicit_port_map) { - fp << "." << std::string(lb.name) << module_input_port_postfix << "("; - } - fp << std::string(lb.name); - if (true == use_explicit_port_map) { - fp << ")"; - } - } else { - VTR_ASSERT_SAFE(VPACK_OUTPAD == lb.type); - fp << "\t\t"; - if (true == use_explicit_port_map) { - fp << "." << std::string(lb.name) << module_output_port_postfix << "("; - } - fp << std::string(lb.name) << output_port_postfix; - if (true == use_explicit_port_map) { - fp << ")"; - } - } - /* Update the counter */ - port_counter++; - } - fp << "\t);" << std::endl; -} - -/******************************************************************** - * This function adds stimuli to I/Os of FPGA fabric - * 1. For mapped I/Os, this function will wire them to the input ports - * of the pre-configured FPGA top module - * 2. For unmapped I/Os, this function will assign a constant value - * by default - *******************************************************************/ -void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const std::string& io_input_port_name_postfix, - const std::string& io_output_port_name_postfix, - const size_t& unused_io_value) { - /* Validate the file stream */ - check_file_handler(fp); - - /* In this function, we support only 1 type of I/Os */ - VTR_ASSERT(1 == module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT).size()); - BasicPort module_io_port = module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)[0]; - - /* Keep tracking which I/Os have been used */ - std::vector io_used(module_io_port.get_width(), false); - - /* See if this I/O should be wired to a benchmark input/output */ - /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs - * This brings convenience to checking functionality - */ - print_verilog_comment(fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----")); - for (const t_logical_block& io_lb : L_logical_blocks) { - /* We only care I/O logical blocks !*/ - if ( (VPACK_INPAD != io_lb.type) && (VPACK_OUTPAD != io_lb.type) ) { - continue; - } - - /* Find the index of the mapped GPIO in top-level FPGA fabric */ - size_t io_index = find_benchmark_io_index(io_lb, device_size, L_grids, L_blocks); - - /* Ensure that IO index is in range */ - BasicPort module_mapped_io_port = module_io_port; - /* Set the port pin index */ - VTR_ASSERT(io_index < module_mapped_io_port.get_width()); - module_mapped_io_port.set_width(io_index, io_index); - - /* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1 - * In addition, the input and output ports may have different postfix in naming - * due to verification context! Here, we give full customization on naming - */ - BasicPort benchmark_io_port; - if (VPACK_INPAD == io_lb.type) { - benchmark_io_port.set_name(std::string(std::string(io_lb.name) + io_input_port_name_postfix)); - benchmark_io_port.set_width(1); - print_verilog_comment(fp, std::string("----- Blif Benchmark input " + std::string(io_lb.name) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----")); - print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false); - } else { - VTR_ASSERT(VPACK_OUTPAD == io_lb.type); - benchmark_io_port.set_name(std::string(std::string(io_lb.name) + io_output_port_name_postfix)); - benchmark_io_port.set_width(1); - print_verilog_comment(fp, std::string("----- Blif Benchmark output " + std::string(io_lb.name) + " is mapped to FPGA IOPAD " + module_mapped_io_port.get_name() + "[" + std::to_string(io_index) + "] -----")); - print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false); - } - - /* Mark this I/O has been used/wired */ - io_used[io_index] = true; - } - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Wire the unused iopads to a constant */ - print_verilog_comment(fp, std::string("----- Wire unused FPGA I/Os to constants -----")); - for (size_t io_index = 0; io_index < io_used.size(); ++io_index) { - /* Bypass used iopads */ - if (true == io_used[io_index]) { - continue; - } - - /* Wire to a contant */ - BasicPort module_unused_io_port = module_io_port; - /* Set the port pin index */ - module_unused_io_port.set_width(io_index, io_index); - - std::vector default_values(module_unused_io_port.get_width(), unused_io_value); - print_verilog_wire_constant_values(fp, module_unused_io_port, default_values); - } - - /* Add an empty line as a splitter */ - fp << std::endl; -} - -/******************************************************************** - * Print Verilog codes to set up a timeout for the simulation - * and dump the waveform to VCD files - * - * Note that: these codes are tuned for Icarus simulator!!! - *******************************************************************/ -void print_verilog_timeout_and_vcd(std::fstream& fp, - const std::string& icarus_preprocessing_flag, - const std::string& module_name, - const std::string& vcd_fname, - const std::string& simulation_start_counter_name, - const std::string& error_counter_name, - const int& simulation_time) { - /* Validate the file stream */ - check_file_handler(fp); - - /* The following verilog codes are tuned for Icarus */ - print_verilog_preprocessing_flag(fp, icarus_preprocessing_flag); - - print_verilog_comment(fp, std::string("----- Begin Icarus requirement -------")); - - fp << "\tinitial begin" << std::endl; - fp << "\t\t$dumpfile(\"" << vcd_fname << "\");" << std::endl; - fp << "\t\t$dumpvars(1, " << module_name << ");" << std::endl; - fp << "\tend" << std::endl; - - /* Condition ends for the Icarus requirement */ - print_verilog_endif(fp); - - print_verilog_comment(fp, std::string("----- END Icarus requirement -------")); - - /* Add an empty line as splitter */ - fp << std::endl; - - BasicPort sim_start_port(simulation_start_counter_name, 1); - - fp << "initial begin" << std::endl; - fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << " <= 1'b1;" << std::endl; - fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl; - fp << "\t$display(\"Simulation start\");" << std::endl; - print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------")); - fp << "\t#" << simulation_time << std::endl; - fp << "\tif(" << error_counter_name << " == 0) begin" << std::endl; - fp << "\t\t$display(\"Simulation Succeed\");" << std::endl; - fp << "\tend else begin" << std::endl; - fp << "\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << error_counter_name << ");" << std::endl; - fp << "\tend" << std::endl; - fp << "\t$finish;" << std::endl; - fp << "end" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Generate the clock port name to be used in this testbench - * - * Restrictions: - * Assume this is a single clock benchmark - *******************************************************************/ -BasicPort generate_verilog_testbench_clock_port(const std::vector& clock_port_names, - const std::string& default_clock_name) { - if (0 == clock_port_names.size()) { - return BasicPort(default_clock_name, 1); - } - - VTR_ASSERT(1 == clock_port_names.size()); - return BasicPort(clock_port_names[0], 1); -} - -/******************************************************************** - * Print Verilog codes to check the equivalence of output vectors - * - * Restriction: this function only supports single clock benchmarks! - *******************************************************************/ -void print_verilog_testbench_check(std::fstream& fp, - const std::string& autochecked_preprocessing_flag, - const std::string& simulation_start_counter_name, - const std::string& benchmark_port_postfix, - const std::string& fpga_port_postfix, - const std::string& check_flag_port_postfix, - const std::string& error_counter_name, - const std::vector& L_logical_blocks, - const std::vector& clock_port_names, - const std::string& default_clock_name) { - - /* Validate the file stream */ - check_file_handler(fp); - - /* Add output autocheck conditionally: only when a preprocessing flag is enable */ - print_verilog_preprocessing_flag(fp, autochecked_preprocessing_flag); - - print_verilog_comment(fp, std::string("----- Begin checking output vectors -------")); - - BasicPort clock_port = generate_verilog_testbench_clock_port(clock_port_names, default_clock_name); - - print_verilog_comment(fp, std::string("----- Skip the first falling edge of clock, it is for initialization -------")); - - BasicPort sim_start_port(simulation_start_counter_name, 1); - - fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, sim_start_port) << ";" << std::endl; - fp << std::endl; - - fp << "\talways@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ") begin" << std::endl; - fp << "\t\tif (1'b1 == " << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << ") begin" << std::endl; - fp << "\t\t"; - print_verilog_register_connection(fp, sim_start_port, sim_start_port, true); - fp << "\t\tend else begin" << std::endl; - - for (const t_logical_block& lb : L_logical_blocks) { - /* Bypass non-I/O logical blocks ! */ - if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { - continue; - } - - if (VPACK_OUTPAD == lb.type){ - fp << "\t\t\tif(!(" << std::string(lb.name) << fpga_port_postfix; - fp << " === " << std::string(lb.name) << benchmark_port_postfix; - fp << ") && !(" << std::string(lb.name) << benchmark_port_postfix; - fp << " === 1'bx)) begin" << std::endl; - fp << "\t\t\t\t" << std::string(lb.name) << check_flag_port_postfix << " <= 1'b1;" << std::endl; - fp << "\t\t\tend else begin" << std::endl; - fp << "\t\t\t\t" << std::string(lb.name) << check_flag_port_postfix << "<= 1'b0;" << std::endl; - fp << "\t\t\tend" << std::endl; - } - } - fp << "\t\tend" << std::endl; - fp << "\tend" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; - - for (const t_logical_block& lb : L_logical_blocks) { - /* Bypass non-I/O logical blocks ! */ - if (VPACK_OUTPAD != lb.type) { - continue; - } - - fp << "\talways@(posedge " << std::string(lb.name) << check_flag_port_postfix << ") begin" << std::endl; - fp << "\t\tif(" << std::string(lb.name) << check_flag_port_postfix << ") begin" << std::endl; - fp << "\t\t\t" << error_counter_name << " = " << error_counter_name << " + 1;" << std::endl; - fp << "\t\t\t$display(\"Mismatch on " << std::string(lb.name) << fpga_port_postfix << " at time = " << std::string("%t") << "\", $realtime);" << std::endl; - fp << "\t\tend" << std::endl; - fp << "\tend" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; - } - - /* Condition ends */ - print_verilog_endif(fp); - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Generate random stimulus for the clock port - * This function is designed to drive the clock port of a benchmark module - * If there is no clock port found, we will give a default clock name - * In such case, this clock will not be wired to the benchmark module - * but be only used as a synchronizer in verification - *******************************************************************/ -void print_verilog_testbench_clock_stimuli(std::fstream& fp, - const t_spice_params& simulation_parameters, - const BasicPort& clock_port) { - /* Validate the file stream */ - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- Clock Initialization -------")); - - fp << "\tinitial begin" << std::endl; - /* Create clock stimuli */ - fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << " <= 1'b0;" << std::endl; - fp << "\t\twhile(1) begin" << std::endl; - fp << "\t\t\t#" << std::setprecision(10) << ((0.5/simulation_parameters.stimulate_params.op_clock_freq)/verilog_sim_timescale) << std::endl; - fp << "\t\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); - fp << " <= !"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, clock_port); - fp << ";" << std::endl; - fp << "\t\tend" << std::endl; - - fp << "\tend" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Generate random stimulus for the input ports (non-clock signals) - * For clock signals, please use print_verilog_testbench_clock_stimuli - *******************************************************************/ -void print_verilog_testbench_random_stimuli(std::fstream& fp, - const std::vector& L_logical_blocks, - const std::string& check_flag_port_postfix, - const BasicPort& clock_port) { - /* Validate the file stream */ - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- Input Initialization -------")); - - fp << "\tinitial begin" << std::endl; - - for (const t_logical_block& lb : L_logical_blocks) { - /* Bypass non-I/O logical blocks ! */ - if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { - continue; - } - - /* Clock ports will be initialized later */ - if ( (VPACK_INPAD == lb.type) && (FALSE == lb.is_clock) ) { - fp << "\t\t" << std::string(lb.name) << " <= 1'b0;" << std::endl; - } - } - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Set 0 to registers for checking flags */ - for (const t_logical_block& lb : L_logical_blocks) { - /* We care only those logic blocks which are input I/Os */ - if (VPACK_OUTPAD != lb.type) { - continue; - } - - /* Each logical block assumes a single-width port */ - BasicPort output_port(std::string(std::string(lb.name) + check_flag_port_postfix), 1); - fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl; - } - - fp << "\tend" << std::endl; - /* Finish initialization */ - - /* Add an empty line as splitter */ - fp << std::endl; - - // Not ready yet to determine if input is reset -/* - fprintf(fp, "//----- Reset Stimulis\n"); - fprintf(fp, " initial begin\n"); - fprintf(fp, " #%.3f\n",(rand() % 10) + 0.001); - fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); - fprintf(fp, " #%.3f\n",(rand() % 10) + 0.001); - fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); - fprintf(fp, " while(1) begin\n"); - fprintf(fp, " #%.3f\n", (rand() % 15) + 0.5); - fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); - fprintf(fp, " #%.3f\n", (rand() % 10000) + 200); - fprintf(fp, " %s <= !%s;\n", reset_input_name, reset_input_name); - fprintf(fp, " end\n"); - fprintf(fp, " end\n\n"); -*/ - - print_verilog_comment(fp, std::string("----- Input Stimulus -------")); - fp << "\talways@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ") begin" << std::endl; - - for (const t_logical_block& lb : L_logical_blocks) { - /* Bypass non-I/O logical blocks ! */ - if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) { - continue; - } - - /* Clock ports will be initialized later */ - if ( (VPACK_INPAD == lb.type) && (FALSE == lb.is_clock) ) { - fp << "\t\t" << std::string(lb.name) << " <= $random;" << std::endl; - } - } - - fp << "\tend" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Print Verilog declaration of shared ports appear in testbenches - * which are - * 1. the shared input ports (registers) to drive both - * FPGA fabric and benchmark instance - * 2. the output ports (wires) for both FPGA fabric and benchmark instance - * 3. the checking flag ports to evaluate if outputs matches under the - * same input vectors - *******************************************************************/ -void print_verilog_testbench_shared_ports(std::fstream& fp, - const std::vector& L_logical_blocks, - const std::string& benchmark_output_port_postfix, - const std::string& fpga_output_port_postfix, - const std::string& check_flag_port_postfix, - const std::string& autocheck_preprocessing_flag) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Instantiate register for inputs stimulis */ - print_verilog_comment(fp, std::string("----- Shared inputs -------")); - for (const t_logical_block& lb : L_logical_blocks) { - /* We care only those logic blocks which are input I/Os */ - if (VPACK_INPAD != lb.type) { - continue; - } - - /* Skip clocks because they are handled in another function */ - if (TRUE == lb.is_clock) { - continue; - } - - /* Each logical block assumes a single-width port */ - BasicPort input_port(std::string(lb.name), 1); - fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl; - } - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Instantiate wires for FPGA fabric outputs */ - print_verilog_comment(fp, std::string("----- FPGA fabric outputs -------")); - - for (const t_logical_block& lb : L_logical_blocks) { - /* We care only those logic blocks which are input I/Os */ - if (VPACK_OUTPAD != lb.type) { - continue; - } - - /* Each logical block assumes a single-width port */ - BasicPort output_port(std::string(std::string(lb.name) + fpga_output_port_postfix), 1); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl; - } - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(autocheck_preprocessing_flag)); - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Instantiate wire for benchmark output */ - print_verilog_comment(fp, std::string("----- Benchmark outputs -------")); - for (const t_logical_block& lb : L_logical_blocks) { - /* We care only those logic blocks which are input I/Os */ - if (VPACK_OUTPAD != lb.type) { - continue; - } - - /* Each logical block assumes a single-width port */ - BasicPort output_port(std::string(std::string(lb.name) + benchmark_output_port_postfix), 1); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl; - } - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Instantiate register for output comparison */ - print_verilog_comment(fp, std::string("----- Output vectors checking flags -------")); - for (const t_logical_block& lb : L_logical_blocks) { - /* We care only those logic blocks which are input I/Os */ - if (VPACK_OUTPAD != lb.type) { - continue; - } - - /* Each logical block assumes a single-width port */ - BasicPort output_port(std::string(std::string(lb.name) + check_flag_port_postfix), 1); - fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, output_port) << ";" << std::endl; - } - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Condition ends for the benchmark instanciation */ - print_verilog_endif(fp); - - /* Add an empty line as splitter */ - fp << std::endl; -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h deleted file mode 100644 index 0bbb1bc53..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.h +++ /dev/null @@ -1,74 +0,0 @@ -#ifndef VERILOG_TESTBENCH_UTILS_H -#define VERILOG_TESTBENCH_UTILS_H - -/* Include header files which are used in the function declaration */ -#include -#include -#include -#include "module_manager.h" -#include "vpr_types.h" - -void print_verilog_testbench_fpga_instance(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const std::string& top_instance_name); - -void print_verilog_testbench_benchmark_instance(std::fstream& fp, - const std::string& module_name, - const std::string& instance_name, - const std::string& module_input_port_postfix, - const std::string& module_output_port_postfix, - const std::string& output_port_postfix, - const std::vector& L_logical_blocks, - const bool& use_explicit_port_map); - -void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const std::string& io_input_port_name_postfix, - const std::string& io_output_port_name_postfix, - const size_t& unused_io_value); - -void print_verilog_timeout_and_vcd(std::fstream& fp, - const std::string& icarus_preprocessing_flag, - const std::string& module_name, - const std::string& vcd_fname, - const std::string& simulation_start_counter_name, - const std::string& error_counter_name, - const int& simulation_time); - -BasicPort generate_verilog_testbench_clock_port(const std::vector& clock_port_names, - const std::string& default_clock_name); - -void print_verilog_testbench_check(std::fstream& fp, - const std::string& autochecked_preprocessing_flag, - const std::string& simulation_start_counter_name, - const std::string& benchmark_port_postfix, - const std::string& fpga_port_postfix, - const std::string& check_flag_port_postfix, - const std::string& error_counter_name, - const std::vector& L_logical_blocks, - const std::vector& clock_port_names, - const std::string& default_clock_name); - -void print_verilog_testbench_clock_stimuli(std::fstream& fp, - const t_spice_params& simulation_parameters, - const BasicPort& clock_port); - -void print_verilog_testbench_random_stimuli(std::fstream& fp, - const std::vector& L_logical_blocks, - const std::string& check_flag_port_postfix, - const BasicPort& clock_port); - -void print_verilog_testbench_shared_ports(std::fstream& fp, - const std::vector& L_logical_blocks, - const std::string& benchmark_output_port_postfix, - const std::string& fpga_output_port_postfix, - const std::string& check_flag_port_postfix, - const std::string& autocheck_preprocessing_flag); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp deleted file mode 100644 index 2cfeecf1b..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp +++ /dev/null @@ -1,70 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to print the top-level - * module for the FPGA fabric in Verilog format - *******************************************************************/ -#include -#include -#include - -#include "vtr_assert.h" - -#include "vpr_types.h" - -#include "fpga_x2p_utils.h" -#include "fpga_x2p_naming.h" - -#include "verilog_global.h" -#include "verilog_writer_utils.h" -#include "verilog_module_writer.h" -#include "verilog_top_module.h" - -/******************************************************************** - * Print the top-level module for the FPGA fabric in Verilog format - * This function will - * 1. name the top-level module - * 2. include dependent netlists - * - User defined netlists - * - Auto-generated netlists - * 3. Add the submodules to the top-level graph - * 4. Add module nets to connect datapath ports - * 5. Add module nets/submodules to connect configuration ports - *******************************************************************/ -void print_verilog_top_module(ModuleManager& module_manager, - const std::string& arch_name, - const std::string& verilog_dir, - const bool& use_explicit_mapping) { - /* Create a module as the top-level fabric, and add it to the module manager */ - std::string top_module_name = generate_fpga_top_module_name(); - ModuleId top_module = module_manager.find_module(top_module_name); - VTR_ASSERT(true == module_manager.valid_module_id(top_module)); - - /* Start printing out Verilog netlists */ - /* Create the file name for Verilog netlist */ - std::string verilog_fname(verilog_dir + generate_fpga_top_netlist_name(std::string(verilog_netlist_file_postfix))); - /* TODO: remove the bak file when the file is ready */ - //verilog_fname += ".bak"; - - vpr_printf(TIO_MESSAGE_INFO, - "Writing Verilog Netlist for top-level module of FPGA fabric (%s)...\n", - verilog_fname.c_str()); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - print_verilog_file_header(fp, std::string("Top-level Verilog module for FPGA architecture: " + std::string(arch_name))); - - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Write the module content in Verilog format */ - write_verilog_module_to_file(fp, module_manager, top_module, use_explicit_mapping); - - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Close file handler */ - fp.close(); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h deleted file mode 100644 index aa26e011a..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.h +++ /dev/null @@ -1,15 +0,0 @@ -/******************************************************************** - * Header file for verilog_top_module.cpp - *******************************************************************/ -#ifndef VERILOG_TOP_MODULE_H -#define VERILOG_TOP_MODULE_H - -#include -#include "module_manager.h" - -void print_verilog_top_module(ModuleManager& module_manager, - const std::string& arch_name, - const std::string& verilog_dir, - const bool& use_explicit_mapping); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp deleted file mode 100644 index 9f801c44a..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.cpp +++ /dev/null @@ -1,881 +0,0 @@ -/******************************************************************** - * This file includes functions that are used to create - * an auto-check top-level testbench for a FPGA fabric - *******************************************************************/ -#include -#include -#include -#include - -#include "vtr_assert.h" -#include "device_port.h" -#include "util.h" - -#include "bitstream_manager_utils.h" - -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" -#include "simulation_utils.h" -#include "fpga_x2p_benchmark_utils.h" - -#include "verilog_global.h" -#include "verilog_writer_utils.h" -#include "verilog_testbench_utils.h" -#include "verilog_top_testbench.h" - -/******************************************************************** - * Local variables used only in this file - *******************************************************************/ -constexpr char* TOP_TESTBENCH_REFERENCE_INSTANCE_NAME = "REF_DUT"; -constexpr char* TOP_TESTBENCH_FPGA_INSTANCE_NAME = "FPGA_DUT"; -constexpr char* TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX = "_benchmark"; -constexpr char* TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX = "_fpga"; - -constexpr char* TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX = "_flag"; - -constexpr char* TOP_TESTBENCH_CC_PROG_TASK_NAME = "prog_cycle_task"; - -constexpr char* TOP_TESTBENCH_SIM_START_PORT_NAME = "sim_start"; - -constexpr int TOP_TESTBENCH_MAGIC_NUMBER_FOR_SIMULATION_TIME = 200; -constexpr char* TOP_TESTBENCH_ERROR_COUNTER = "nb_error"; - -/******************************************************************** - * Print local wires for configuration chain protocols - *******************************************************************/ -static -void print_verilog_top_testbench_config_chain_port(std::fstream& fp) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Print the head of configuraion-chains here */ - print_verilog_comment(fp, std::string("---- Configuration-chain head -----")); - BasicPort config_chain_head_port(generate_configuration_chain_head_name(), 1); - fp << generate_verilog_port(VERILOG_PORT_REG, config_chain_head_port) << ";" << std::endl; - - /* Print the tail of configuration-chains here */ - print_verilog_comment(fp, std::string("---- Configuration-chain tail -----")); - BasicPort config_chain_tail_port(generate_configuration_chain_tail_name(), 1); - fp << generate_verilog_port(VERILOG_PORT_WIRE, config_chain_tail_port) << ";" << std::endl; -} - -/******************************************************************** - * Print local wires for different types of configuration protocols - *******************************************************************/ -static -void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, - const e_sram_orgz& sram_orgz_type) { - switch(sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* TODO */ - break; - case SPICE_SRAM_SCAN_CHAIN: - print_verilog_top_testbench_config_chain_port(fp); - break; - case SPICE_SRAM_MEMORY_BANK: - /* TODO */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * Wire the global ports of FPGA fabric to local wires - *******************************************************************/ -static -void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports) { - /* Validate the file stream */ - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- Begin connecting global ports of FPGA fabric to stimuli -----")); - - /* Connect global clock ports to operating or programming clock signal */ - for (const CircuitPortId& model_global_port : global_ports) { - if (SPICE_MODEL_PORT_CLOCK != circuit_lib.port_type(model_global_port)) { - continue; - } - /* Reach here, it means we have a global clock to deal with: - * 1. if the port is identified as a programming clock, - * connect it to the local wire of programming clock - * 2. if the port is identified as an operating clock - * connect it to the local wire of operating clock - */ - /* Find the module port */ - ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); - VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); - - BasicPort stimuli_clock_port; - if (true == circuit_lib.port_is_prog(model_global_port)) { - stimuli_clock_port.set_name(std::string(top_tb_prog_clock_port_name)); - stimuli_clock_port.set_width(1); - } else { - VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port)); - stimuli_clock_port.set_name(std::string(top_tb_op_clock_port_name)); - stimuli_clock_port.set_width(1); - } - /* Wire the port to the input stimuli: - * The wiring will be inverted if the default value of the global port is 1 - * Otherwise, the wiring will not be inverted! - */ - print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), - stimuli_clock_port, - 1 == circuit_lib.port_default_value(model_global_port)); - } - - /* Connect global configuration done ports to configuration done signal */ - for (const CircuitPortId& model_global_port : global_ports) { - /* Bypass clock signals, they have been processed */ - if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(model_global_port)) { - continue; - } - if (false == circuit_lib.port_is_config_enable(model_global_port)) { - continue; - } - /* Reach here, it means we have a configuration done port to deal with */ - /* Find the module port */ - ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); - VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); - - BasicPort stimuli_config_done_port(std::string(top_tb_config_done_port_name), 1); - /* Wire the port to the input stimuli: - * The wiring will be inverted if the default value of the global port is 1 - * Otherwise, the wiring will not be inverted! - */ - print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), - stimuli_config_done_port, - 1 == circuit_lib.port_default_value(model_global_port)); - } - - /* Connect global reset ports to operating or programming reset signal */ - for (const CircuitPortId& model_global_port : global_ports) { - /* Bypass clock signals, they have been processed */ - if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(model_global_port)) { - continue; - } - /* Bypass config_done signals, they have been processed */ - if (true == circuit_lib.port_is_config_enable(model_global_port)) { - continue; - } - - if (false == circuit_lib.port_is_reset(model_global_port)) { - continue; - } - /* Reach here, it means we have a reset port to deal with */ - /* Find the module port */ - ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); - VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); - - BasicPort stimuli_reset_port; - if (true == circuit_lib.port_is_prog(model_global_port)) { - stimuli_reset_port.set_name(std::string(top_tb_prog_reset_port_name)); - stimuli_reset_port.set_width(1); - } else { - VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port)); - stimuli_reset_port.set_name(std::string(top_tb_reset_port_name)); - stimuli_reset_port.set_width(1); - } - /* Wire the port to the input stimuli: - * The wiring will be inverted if the default value of the global port is 1 - * Otherwise, the wiring will not be inverted! - */ - print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), - stimuli_reset_port, - 1 == circuit_lib.port_default_value(model_global_port)); - } - - /* Connect global set ports to operating or programming set signal */ - for (const CircuitPortId& model_global_port : global_ports) { - /* Bypass clock signals, they have been processed */ - if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(model_global_port)) { - continue; - } - /* Bypass config_done signals, they have been processed */ - if (true == circuit_lib.port_is_config_enable(model_global_port)) { - continue; - } - - /* Bypass reset signals, they have been processed */ - if (true == circuit_lib.port_is_reset(model_global_port)) { - continue; - } - - if (false == circuit_lib.port_is_set(model_global_port)) { - continue; - } - /* Reach here, it means we have a set port to deal with */ - /* Find the module port */ - ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); - VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); - - BasicPort stimuli_set_port; - if (true == circuit_lib.port_is_prog(model_global_port)) { - stimuli_set_port.set_name(std::string(top_tb_prog_set_port_name)); - stimuli_set_port.set_width(1); - } else { - VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port)); - stimuli_set_port.set_name(std::string(top_tb_set_port_name)); - stimuli_set_port.set_width(1); - } - /* Wire the port to the input stimuli: - * The wiring will be inverted if the default value of the global port is 1 - * Otherwise, the wiring will not be inverted! - */ - print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), - stimuli_set_port, - 1 == circuit_lib.port_default_value(model_global_port)); - } - - /* For the rest of global ports, wire them to constant signals */ - for (const CircuitPortId& model_global_port : global_ports) { - /* Bypass clock signals, they have been processed */ - if (SPICE_MODEL_PORT_CLOCK == circuit_lib.port_type(model_global_port)) { - continue; - } - /* Bypass config_done signals, they have been processed */ - if (true == circuit_lib.port_is_config_enable(model_global_port)) { - continue; - } - - /* Bypass reset signals, they have been processed */ - if (true == circuit_lib.port_is_reset(model_global_port)) { - continue; - } - - /* Bypass set signals, they have been processed */ - if (true == circuit_lib.port_is_set(model_global_port)) { - continue; - } - - /* Reach here, it means we have a port to deal with */ - /* Find the module port and wire it to constant values */ - ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); - VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); - - BasicPort module_port = module_manager.module_port(top_module, module_global_port); - std::vector default_values(module_port.get_width(), circuit_lib.port_default_value(model_global_port)); - print_verilog_wire_constant_values(fp, module_port, default_values); - } - - print_verilog_comment(fp, std::string("----- End connecting global ports of FPGA fabric to stimuli -----")); -} - -/******************************************************************** - * This function prints the top testbench module declaration - * and internal wires/port declaration - * Ports can be classified in two categories: - * 1. General-purpose ports, which are datapath I/Os, clock signals - * for the FPGA fabric and input benchmark - * 2. Fabric-featured ports, which are required by configuration - * protocols. - * Due the difference in configuration protocols, the internal - * wires and ports will be different: - * (a) configuration-chain: we will have two ports, - * a head and a tail for the configuration chain, - * in addition to the regular ports. - * (b) memory-decoders: we will have a few ports to drive - * address lines for decoders and a bit input port to feed - * configuration bits - *******************************************************************/ -static -void print_verilog_top_testbench_ports(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const std::vector& L_logical_blocks, - const std::vector& clock_port_names, - const e_sram_orgz& sram_orgz_type, - const std::string& circuit_name){ - /* Validate the file stream */ - check_file_handler(fp); - - /* Print module definition */ - fp << "module " << circuit_name << std::string(modelsim_autocheck_testbench_module_postfix); - fp << ";" << std::endl; - - /* Print regular local wires: - * 1. global ports, i.e., reset, set and clock signals - * 2. datapath I/O signals - */ - /* Global ports of top-level module */ - print_verilog_comment(fp, std::string("----- Local wires for global ports of FPGA fabric -----")); - for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) { - fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl; - } - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Datapath I/Os of top-level module */ - print_verilog_comment(fp, std::string("----- Local wires for I/Os of FPGA fabric -----")); - for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GPIO_PORT)) { - fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";" << std::endl; - } - /* Add an empty line as a splitter */ - fp << std::endl; - - /* Add local wires/registers that drive stimulus - * We create these general purpose ports here, - * and then wire them to the ports of FPGA fabric depending on their usage - */ - /* Configuration done port */ - BasicPort config_done_port(std::string(top_tb_config_done_port_name), 1); - fp << generate_verilog_port(VERILOG_PORT_REG, config_done_port) << ";" << std::endl; - - /* Programming clock */ - BasicPort prog_clock_port(std::string(top_tb_prog_clock_port_name), 1); - fp << generate_verilog_port(VERILOG_PORT_WIRE, prog_clock_port) << ";" << std::endl; - BasicPort prog_clock_register_port(std::string(std::string(top_tb_prog_clock_port_name) + std::string(top_tb_clock_reg_postfix)), 1); - fp << generate_verilog_port(VERILOG_PORT_REG, prog_clock_register_port) << ";" << std::endl; - - /* Operating clock */ - BasicPort op_clock_port(std::string(top_tb_op_clock_port_name), 1); - fp << generate_verilog_port(VERILOG_PORT_WIRE, op_clock_port) << ";" << std::endl; - BasicPort op_clock_register_port(std::string(std::string(top_tb_op_clock_port_name) + std::string(top_tb_clock_reg_postfix)), 1); - fp << generate_verilog_port(VERILOG_PORT_REG, op_clock_register_port) << ";" << std::endl; - - /* Programming set and reset */ - BasicPort prog_reset_port(std::string(top_tb_prog_reset_port_name), 1); - fp << generate_verilog_port(VERILOG_PORT_REG, prog_reset_port) << ";" << std::endl; - BasicPort prog_set_port(std::string(top_tb_prog_set_port_name), 1); - fp << generate_verilog_port(VERILOG_PORT_REG, prog_set_port) << ";" << std::endl; - - /* Global set and reset */ - BasicPort reset_port(std::string(top_tb_reset_port_name), 1); - fp << generate_verilog_port(VERILOG_PORT_REG, reset_port) << ";" << std::endl; - BasicPort set_port(std::string(top_tb_set_port_name), 1); - fp << generate_verilog_port(VERILOG_PORT_REG, set_port) << ";" << std::endl; - - /* Configuration ports depend on the organization of SRAMs */ - print_verilog_top_testbench_config_protocol_port(fp, sram_orgz_type); - - /* Create a clock port if the benchmark have one but not in the default name! - * We will wire the clock directly to the operating clock directly - */ - for (const std::string clock_port_name : clock_port_names) { - if (0 == clock_port_name.compare(op_clock_port.get_name())) { - continue; - } - /* Ensure the clock port name is not a duplication of global ports of the FPGA module */ - bool print_clock_port = true; - for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) { - if (0 == clock_port_name.compare(module_port.get_name())) { - print_clock_port = false; - } - } - if (false == print_clock_port) { - continue; - } - - /* Print the clock and wire it to op_clock */ - print_verilog_comment(fp, std::string("----- Create a clock for benchmark and wire it to op_clock -------")); - BasicPort clock_port(clock_port_name, 1); - fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, clock_port) << ";" << std::endl; - print_verilog_wire_connection(fp, clock_port, op_clock_port, false); - } - - print_verilog_testbench_shared_ports(fp, L_logical_blocks, - std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), - std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), - std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), - std::string(autochecked_simulation_flag)); - - /* Instantiate an integer to count the number of error and - * determine if the simulation succeed or failed - */ - print_verilog_comment(fp, std::string("----- Error counter -----")); - fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 0;" << std::endl; -} - -/******************************************************************** - * Instanciate the input benchmark module - *******************************************************************/ -static -void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, - const std::string& reference_verilog_top_name, - const std::vector& L_logical_blocks) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(autochecked_simulation_flag)); - - print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------")); - - /* Do NOT use explicit port mapping here: - * VPR added a prefix of "out_" to the output ports of input benchmark - */ - print_verilog_testbench_benchmark_instance(fp, reference_verilog_top_name, - std::string(TOP_TESTBENCH_REFERENCE_INSTANCE_NAME), - std::string(), - std::string(), - std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), L_logical_blocks, - false); - - print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Condition ends for the benchmark instanciation */ - print_verilog_endif(fp); - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Print tasks (processes) in Verilog format, - * which is very useful in generating stimuli for each clock cycle - * This function is tuned for configuration-chain manipulation: - * During each programming cycle, we feed the input of scan chain with a memory bit - *******************************************************************/ -static -void print_verilog_top_testbench_load_bitstream_task_configuration_chain(std::fstream& fp) { - - /* Validate the file stream */ - check_file_handler(fp); - - BasicPort prog_clock_port(std::string(top_tb_prog_clock_port_name), 1); - BasicPort cc_head_port(generate_configuration_chain_head_name(), 1); - BasicPort cc_head_value(generate_configuration_chain_head_name() + std::string("_val"), 1); - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Feed the scan-chain input at each falling edge of programming clock - * It aims at avoid racing the programming clock (scan-chain data changes at the rising edge). - */ - print_verilog_comment(fp, std::string("----- Task: input values during a programming clock cycle -----")); - fp << "task " << std::string(TOP_TESTBENCH_CC_PROG_TASK_NAME) << ";" << std::endl; - fp << generate_verilog_port(VERILOG_PORT_INPUT, cc_head_value) << ";" << std::endl; - fp << "\tbegin" << std::endl; - fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; - fp << "\t\t\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, cc_head_port); - fp << " = "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, cc_head_value); - fp << ";" << std::endl; - - fp << "\tend" << std::endl; - fp << "endtask" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Print tasks, which is very useful in generating stimuli for each clock cycle - *******************************************************************/ -static -void print_verilog_top_testbench_load_bitstream_task(std::fstream& fp, - const e_sram_orgz& sram_orgz_type) { - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - break; - case SPICE_SRAM_SCAN_CHAIN: - print_verilog_top_testbench_load_bitstream_task_configuration_chain(fp); - break; - case SPICE_SRAM_MEMORY_BANK: - /* TODO: - dump_verilog_top_testbench_stimuli_serial_version_tasks_memory_bank(cur_sram_orgz_info, fp); - */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid type of SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * Print generatic input stimuli for the top testbench - * include: - * 1. configuration done signal - * 2. programming clock - * 3. operating clock - * 4. programming reset signal - * 5. programming set signal - * 6. reset signal - * 7. set signal - *******************************************************************/ -static -void print_verilog_top_testbench_generic_stimulus(std::fstream& fp, - const size_t& num_config_clock_cycles, - const float& prog_clock_period, - const float& op_clock_period, - const float& timescale) { - /* Validate the file stream */ - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- Number of clock cycles in configuration phase: " + std::to_string(num_config_clock_cycles) + " -----")); - - BasicPort config_done_port(std::string(top_tb_config_done_port_name), 1); - - BasicPort op_clock_port(std::string(top_tb_op_clock_port_name), 1); - BasicPort op_clock_register_port(std::string(std::string(top_tb_op_clock_port_name) + std::string(top_tb_clock_reg_postfix)), 1); - - BasicPort prog_clock_port(std::string(top_tb_prog_clock_port_name), 1); - BasicPort prog_clock_register_port(std::string(std::string(top_tb_prog_clock_port_name) + std::string(top_tb_clock_reg_postfix)), 1); - - BasicPort prog_reset_port(std::string(top_tb_prog_reset_port_name), 1); - BasicPort prog_set_port(std::string(top_tb_prog_set_port_name), 1); - - BasicPort reset_port(std::string(top_tb_reset_port_name), 1); - BasicPort set_port(std::string(top_tb_set_port_name), 1); - - /* Generate stimuli waveform for configuration done signals */ - print_verilog_comment(fp, "----- Begin configuration done signal generation -----"); - print_verilog_pulse_stimuli(fp, config_done_port, - 0, /* Initial value */ - num_config_clock_cycles * prog_clock_period / timescale, 0); - print_verilog_comment(fp, "----- End configuration done signal generation -----"); - fp << std::endl; - - /* Generate stimuli waveform for programming clock signals */ - print_verilog_comment(fp, "----- Begin raw programming clock signal generation -----"); - print_verilog_clock_stimuli(fp, prog_clock_register_port, - 0, /* Initial value */ - 0.5 * prog_clock_period / timescale, - std::string()); - print_verilog_comment(fp, "----- End raw programming clock signal generation -----"); - fp << std::endl; - - /* Programming clock should be only enabled during programming phase. - * When configuration is done (config_done is enabled), programming clock should be always zero. - */ - print_verilog_comment(fp, std::string("----- Actual programming clock is triggered only when " + config_done_port.get_name() + " and " + prog_reset_port.get_name() + " are disabled -----")); - fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port); - fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_register_port); - fp << " & (~" << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port) << ")"; - fp << " & (~" << generate_verilog_port(VERILOG_PORT_CONKT, prog_reset_port) << ")"; - fp << ";" << std::endl; - - fp << std::endl; - - /* Generate stimuli waveform for operating clock signals */ - print_verilog_comment(fp, "----- Begin raw operating clock signal generation -----"); - print_verilog_clock_stimuli(fp, op_clock_register_port, - 0, /* Initial value */ - 0.5 * op_clock_period / timescale, - std::string("~" + reset_port.get_name())); - print_verilog_comment(fp, "----- End raw operating clock signal generation -----"); - - /* Operation clock should be enabled after programming phase finishes. - * Before configuration is done (config_done is enabled), operation clock should be always zero. - */ - print_verilog_comment(fp, std::string("----- Actual operating clock is triggered only when " + config_done_port.get_name() + " is enabled -----")); - fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, op_clock_port); - fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, op_clock_register_port); - fp << " & " << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port); - fp << ";" << std::endl; - - fp << std::endl; - - /* Reset signal for configuration circuit: - * only enable during the first clock cycle in programming phase - */ - print_verilog_comment(fp, "----- Begin programming reset signal generation -----"); - print_verilog_pulse_stimuli(fp, prog_reset_port, - 1, /* Initial value */ - prog_clock_period / timescale, 0); - print_verilog_comment(fp, "----- End programming reset signal generation -----"); - - fp << std::endl; - - /* Programming set signal for configuration circuit : always disabled */ - print_verilog_comment(fp, "----- Begin programming set signal generation: always disabled -----"); - print_verilog_pulse_stimuli(fp, prog_set_port, - 0, /* Initial value */ - prog_clock_period / timescale, 0); - print_verilog_comment(fp, "----- End programming set signal generation: always disabled -----"); - - fp << std::endl; - - /* Operating reset signals: only enabled during the first clock cycle in operation phase */ - std::vector reset_pulse_widths; - reset_pulse_widths.push_back(op_clock_period / timescale); - reset_pulse_widths.push_back(2 * op_clock_period / timescale); - - std::vector reset_flip_values; - reset_flip_values.push_back(1); - reset_flip_values.push_back(0); - - print_verilog_comment(fp, "----- Begin operating reset signal generation -----"); - print_verilog_comment(fp, "----- Reset signal is enabled until the first clock cycle in operation phase -----"); - print_verilog_pulse_stimuli(fp, reset_port, - 1, - reset_pulse_widths, - reset_flip_values, - config_done_port.get_name()); - print_verilog_comment(fp, "----- End operating reset signal generation -----"); - - /* Operating set signal for configuration circuit : always disabled */ - print_verilog_comment(fp, "----- Begin operating set signal generation: always disabled -----"); - print_verilog_pulse_stimuli(fp, set_port, - 0, /* Initial value */ - op_clock_period / timescale, 0); - print_verilog_comment(fp, "----- End operating set signal generation: always disabled -----"); - - fp << std::endl; -} - -/******************************************************************** - * Print stimulus for a FPGA fabric with a configuration chain protocol - * where configuration bits are programming in serial (one by one) - * Task list: - * 1. For clock signal, we should create voltage waveforms for two types of clock signals: - * a. operation clock - * b. programming clock - * 2. For Set/Reset, we reset the chip after programming phase ends - * and before operation phase starts - * 3. For input/output clb nets (mapped to I/O grids), - * we should create voltage waveforms only after programming phase - *******************************************************************/ -static -void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, - const BitstreamManager& bitstream_manager, - const std::vector& fabric_bitstream) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Initial value should be the first configuration bits - * In the rest of programming cycles, - * configuration bits are fed at the falling edge of programming clock. - * We do not care the value of scan_chain head during the first programming cycle - * It is reset anyway - */ - BasicPort config_chain_head_port(generate_configuration_chain_head_name(), 1); - std::vector initial_values(config_chain_head_port.get_width(), 0); - - print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----"); - fp << "initial" << std::endl; - fp << "\tbegin" << std::endl; - print_verilog_comment(fp, "----- Configuration chain default input -----"); - fp << "\t\t"; - fp << generate_verilog_port_constant_values(config_chain_head_port, initial_values); - fp << ";"; - - fp << std::endl; - - /* Attention: the configuration chain protcol requires the last configuration bit is fed first - * We will visit the fabric bitstream in a reverse way - */ - std::vector cc_bitstream = fabric_bitstream; - std::reverse(cc_bitstream.begin(), cc_bitstream.end()); - for (const ConfigBitId& bit_id : cc_bitstream) { - fp << "\t\t" << std::string(TOP_TESTBENCH_CC_PROG_TASK_NAME); - fp << "(1'b" << (size_t)bitstream_manager.bit_value(bit_id) << ");" << std::endl; - } - - /* Raise the flag of configuration done when bitstream loading is complete */ - BasicPort prog_clock_port(std::string(top_tb_prog_clock_port_name), 1); - fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; - - BasicPort config_done_port(std::string(top_tb_config_done_port_name), 1); - fp << "\t\t\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port); - fp << " <= "; - std::vector config_done_enable_values(config_done_port.get_width(), 1); - fp << generate_verilog_constant_values(config_done_enable_values); - fp << ";" << std::endl; - - fp << "\tend" << std::endl; - print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----"); -} - -/******************************************************************** - * Generate the stimuli for the top-level testbench - * The simulation consists of two phases: configuration phase and operation phase - * Configuration bits are loaded serially. - * This is actually what we do for a physical FPGA - *******************************************************************/ -static -void print_verilog_top_testbench_bitstream(std::fstream& fp, - const e_sram_orgz& sram_orgz_type, - const BitstreamManager& bitstream_manager, - const std::vector& fabric_bitstream) { - /* Branch on the type of configuration protocol */ - switch (sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* TODO */ - break; - case SPICE_SRAM_SCAN_CHAIN: - print_verilog_top_testbench_configuration_chain_bitstream(fp, bitstream_manager, fabric_bitstream); - break; - case SPICE_SRAM_MEMORY_BANK: - /* TODO */ - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s, [LINE%d]) Invalid SRAM organization type!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/******************************************************************** - * The top-level function to generate a testbench, in order to verify: - * 1. Configuration phase of the FPGA fabric, where the bitstream is - * loaded to the configuration protocol of the FPGA fabric - * 2. Operating phase of the FPGA fabric, where input stimuli are - * fed to the I/Os of the FPGA fabric - * +----------+ - * | FPGA | +------------+ - * +----->| Fabric |------>| | - * | | | | | - * | +----------+ | | - * | | Output | - * random_input_vectors -----+ | Vector |---->Functional correct? - * | | Comparator | - * | +-----------+ | | - * | | Input | | | - * +----->| Benchmark |----->| | - * +-----------+ +------------+ - * - *******************************************************************/ -void print_verilog_top_testbench(const ModuleManager& module_manager, - const BitstreamManager& bitstream_manager, - const std::vector& fabric_bitstream, - const e_sram_orgz& sram_orgz_type, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const std::string& circuit_name, - const std::string& verilog_fname, - const std::string& verilog_dir, - const t_spice_params& simulation_parameters) { - vpr_printf(TIO_MESSAGE_INFO, - "Writing Autocheck Testbench for FPGA Top-level Verilog netlist for %s...", - circuit_name.c_str()); - - /* Start time count */ - clock_t t_start = clock(); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - /* Validate the file stream */ - check_file_handler(fp); - - /* Generate a brief description on the Verilog file*/ - std::string title = std::string("FPGA Verilog Testbench for Top-level netlist of Design: ") + circuit_name; - print_verilog_file_header(fp, title); - - /* Print preprocessing flags and external netlists */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Find the top_module */ - ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name()); - VTR_ASSERT(true == module_manager.valid_module_id(top_module)); - - /* Preparation: find all the clock ports */ - std::vector clock_port_names = find_benchmark_clock_port_name(L_logical_blocks); - - /* Start of testbench */ - print_verilog_top_testbench_ports(fp, module_manager, top_module, - L_logical_blocks, clock_port_names, - sram_orgz_type, circuit_name); - - /* Find the clock period */ - float prog_clock_period = (1./simulation_parameters.stimulate_params.prog_clock_freq); - float op_clock_period = (1./simulation_parameters.stimulate_params.op_clock_freq); - /* Estimate the number of configuration clock cycles - * by traversing the linked-list and count the number of SRAM=1 or BL=1&WL=1 in it. - * We plus 1 additional config clock cycle here because we need to reset everything during the first clock cycle - */ - size_t num_config_clock_cycles = 1 + fabric_bitstream.size(); - - /* Generate stimuli for general control signals */ - print_verilog_top_testbench_generic_stimulus(fp, - num_config_clock_cycles, - prog_clock_period, - op_clock_period, - verilog_sim_timescale); - - /* Generate stimuli for global ports or connect them to existed signals */ - print_verilog_top_testbench_global_ports_stimuli(fp, - module_manager, top_module, - circuit_lib, global_ports); - - /* Instanciate FPGA top-level module */ - print_verilog_testbench_fpga_instance(fp, module_manager, top_module, - std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME)); - - /* Connect I/Os to benchmark I/Os or constant driver */ - print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module, - L_logical_blocks, device_size, L_grids, - L_blocks, - std::string(), - std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), - (size_t)verilog_default_signal_init_value); - - /* Instanciate input benchmark */ - print_verilog_top_testbench_benchmark_instance(fp, - circuit_name, - L_logical_blocks); - - /* Print tasks used for loading bitstreams */ - print_verilog_top_testbench_load_bitstream_task(fp, sram_orgz_type); - - /* load bitstream to FPGA fabric in a configuration phase */ - print_verilog_top_testbench_bitstream(fp, sram_orgz_type, - bitstream_manager, fabric_bitstream); - - /* Add stimuli for reset, set, clock and iopad signals */ - print_verilog_testbench_random_stimuli(fp, L_logical_blocks, - std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), - BasicPort(std::string(top_tb_op_clock_port_name), 1)); - - /* Add output autocheck */ - print_verilog_testbench_check(fp, - std::string(autochecked_simulation_flag), - std::string(TOP_TESTBENCH_SIM_START_PORT_NAME), - std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), - std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), - std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), - std::string(TOP_TESTBENCH_ERROR_COUNTER), - L_logical_blocks, clock_port_names, std::string(top_tb_op_clock_port_name)); - - /* Find simulation time */ - float simulation_time = find_simulation_time_period(verilog_sim_timescale, - num_config_clock_cycles, - 1./simulation_parameters.stimulate_params.prog_clock_freq, - simulation_parameters.meas_params.sim_num_clock_cycle, - 1./simulation_parameters.stimulate_params.op_clock_freq); - - - /* Add Icarus requirement */ - print_verilog_timeout_and_vcd(fp, - std::string(icarus_simulator_flag), - std::string(circuit_name + std::string(modelsim_autocheck_testbench_module_postfix)), - std::string(circuit_name + std::string("_formal.vcd")), - std::string(TOP_TESTBENCH_SIM_START_PORT_NAME), - std::string(TOP_TESTBENCH_ERROR_COUNTER), - (int)simulation_time); - - - /* Testbench ends*/ - print_verilog_module_end(fp, std::string(circuit_name) + std::string(modelsim_autocheck_testbench_module_postfix)); - - /* Close the file stream */ - fp.close(); - - /* End time count */ - clock_t t_end = clock(); - - float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", - run_time_sec); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h deleted file mode 100644 index ab4a7f955..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h +++ /dev/null @@ -1,50 +0,0 @@ -#ifndef VERILOG_TOP_TESTBENCH -#define VERILOG_TOP_TESTBENCH - -#include -#include -#include "module_manager.h" -#include "bitstream_manager.h" -#include "circuit_library.h" - -void print_verilog_top_testbench(const ModuleManager& module_manager, - const BitstreamManager& bitstream_manager, - const std::vector& fabric_bitstream, - const e_sram_orgz& sram_orgz_type, - const CircuitLibrary& circuit_lib, - const std::vector& global_ports, - const std::vector& L_logical_blocks, - const vtr::Point& device_size, - const std::vector>& L_grids, - const std::vector& L_blocks, - const std::string& circuit_name, - const std::string& verilog_fname, - const std::string& verilog_dir, - const t_spice_params& simulation_parameters); - -void dump_verilog_top_testbench_global_ports(FILE* fp, t_llist* head, - enum e_dump_verilog_port_type dump_port_type); - -void dump_verilog_top_testbench_global_ports_stimuli(FILE* fp, t_llist* head); - -void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp, - char* circuit_name, - bool is_explicit_mapping); - -void dump_verilog_top_testbench_stimuli(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp, - t_spice verilog); - -void dump_verilog_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, - char* circuit_name, - const char* top_netlist_name, - char* verilog_dir_path, - t_spice verilog); - -void dump_verilog_input_blif_testbench(char* circuit_name, - char* top_netlist_name, - char* verilog_dir_path, - t_spice verilog); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp deleted file mode 100644 index 41dc33bcb..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp +++ /dev/null @@ -1,133 +0,0 @@ -/*********************************************** - * This file includes functions to generate - * Verilog submodules for wires. - **********************************************/ -#include -#include - -#include "util.h" -#include "vtr_assert.h" - -/* Device-level header files */ -#include "module_manager.h" -#include "module_manager_utils.h" -#include "physical_types.h" -#include "vpr_types.h" - -/* FPGA-X2P context header files */ -#include "spice_types.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -/* FPGA-Verilog context header files */ -#include "verilog_global.h" -#include "verilog_submodule_utils.h" -#include "verilog_writer_utils.h" -#include "verilog_wire.h" - -/******************************************************************** - * Print a Verilog module of a regular wire segment - * Regular wire, which is 1-input and 1-output - * This type of wires are used in the local routing architecture - * +------+ - * input --->| wire |---> output - * +------+ - * - *******************************************************************/ -static -void print_verilog_wire_module(ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - std::fstream& fp, - const CircuitModelId& wire_model) { - /* Ensure a valid file handler*/ - check_file_handler(fp); - - /* Find the input port, output port*/ - std::vector input_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true); - std::vector output_ports = circuit_lib.model_ports_by_type(wire_model, SPICE_MODEL_PORT_OUTPUT, true); - std::vector global_ports = circuit_lib.model_global_ports_by_type(wire_model, SPICE_MODEL_PORT_INPUT, true, true); - - /* Makre sure the port size is what we want */ - VTR_ASSERT (1 == input_ports.size()); - VTR_ASSERT (1 == output_ports.size()); - VTR_ASSERT (1 == circuit_lib.port_size(input_ports[0])); - VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0])); - - /* Create a Verilog Module based on the circuit model, and add to module manager */ - ModuleId wire_module = module_manager.find_module(circuit_lib.model_name(wire_model)); - VTR_ASSERT(true == module_manager.valid_module_id(wire_module)); - - /* dump module definition + ports */ - print_verilog_module_declaration(fp, module_manager, wire_module); - /* Finish dumping ports */ - - /* Print the internal logic of Verilog module */ - /* Find the input port of the module */ - ModulePortId module_input_port_id = module_manager.find_module_port(wire_module, circuit_lib.port_lib_name(input_ports[0])); - VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id); - BasicPort module_input_port = module_manager.module_port(wire_module, module_input_port_id); - - /* Find the output port of the module */ - ModulePortId module_output_port_id = module_manager.find_module_port(wire_module, circuit_lib.port_lib_name(output_ports[0])); - VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id); - BasicPort module_output_port = module_manager.module_port(wire_module, module_output_port_id); - - /* Print wire declaration for the inputs and outputs */ - fp << generate_verilog_port(VERILOG_PORT_WIRE, module_input_port) << ";" << std::endl; - fp << generate_verilog_port(VERILOG_PORT_WIRE, module_output_port) << ";" << std::endl; - - /* Direct shortcut */ - print_verilog_wire_connection(fp, module_output_port, module_input_port, false); - - /* Print timing info */ - print_verilog_submodule_timing(fp, circuit_lib, wire_model); - - /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(wire_model)); - - /* Add an empty line as a splitter */ - fp << std::endl; -} - -/******************************************************************** - * Top-level function to print wire modules - *******************************************************************/ -void print_verilog_submodule_wires(ModuleManager& module_manager, - std::vector& netlist_names, - const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, - const std::string& submodule_dir) { - std::string verilog_fname(submodule_dir + wires_verilog_file_name); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Print out debugging information for if the file is not opened/created properly */ - vpr_printf(TIO_MESSAGE_INFO, - "Creating Verilog netlist for wires (%s)...\n", - verilog_fname.c_str()); - - print_verilog_file_header(fp, "Wires"); - - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - /* Print Verilog models for regular wires*/ - print_verilog_comment(fp, std::string("----- BEGIN Verilog modules for regular wires -----")); - for (const auto& model : circuit_lib.models_by_type(SPICE_MODEL_WIRE)) { - /* Bypass user-defined circuit models */ - if (!circuit_lib.model_verilog_netlist(model).empty()) { - continue; - } - print_verilog_wire_module(module_manager, circuit_lib, fp, model); - } - print_verilog_comment(fp, std::string("----- END Verilog modules for regular wires -----")); - - /* Close the file stream */ - fp.close(); - - /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h deleted file mode 100644 index a5a29f2be..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h +++ /dev/null @@ -1,23 +0,0 @@ -/*********************************************** - * Header file for verilog_wire.cpp - **********************************************/ - -#ifndef VERILOG_WIRE_H -#define VERILOG_WIRE_H - -/* Include other header files which are dependency on the function declared below */ -#include -#include -#include "physical_types.h" -#include "vpr_types.h" - -#include "circuit_library.h" -#include "module_manager.h" - -void print_verilog_submodule_wires(ModuleManager& module_manager, - std::vector& netlist_names, - const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, - const std::string& submodule_dir); - -#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp deleted file mode 100644 index 19c7e59a4..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ /dev/null @@ -1,1401 +0,0 @@ -/************************************************ - * Include functions for most frequently - * used Verilog writers - ***********************************************/ -#include -#include -#include -#include -#include - -#include "vtr_assert.h" - -/* Device-level header files */ -#include "circuit_library_utils.h" - -/* FPGA-X2P context header files */ -#include "spice_types.h" -#include "fpga_x2p_naming.h" -#include "fpga_x2p_utils.h" - -/* FPGA-Verilog context header files */ -#include "verilog_global.h" -#include "verilog_writer_utils.h" - -/************************************************ - * Generate header comments for a Verilog netlist - * include the description - ***********************************************/ -void print_verilog_file_header(std::fstream& fp, - const std::string& usage) { - check_file_handler(fp); - - auto end = std::chrono::system_clock::now(); - std::time_t end_time = std::chrono::system_clock::to_time_t(end); - - fp << "//-------------------------------------------" << std::endl; - fp << "//\tFPGA Synthesizable Verilog Netlist" << std::endl; - fp << "//\tDescription: " << usage << std::endl; - fp << "//\tAuthor: Xifan TANG" << std::endl; - fp << "//\tOrganization: University of Utah" << std::endl; - fp << "//\tDate: " << std::ctime(&end_time) ; - fp << "//-------------------------------------------" << std::endl; - fp << "//----- Time scale -----" << std::endl; - fp << "`timescale 1ns / 1ps" << std::endl; - fp << std::endl; -} - -/******************************************************************** - * Print Verilog codes to include a netlist - *******************************************************************/ -void print_verilog_include_netlist(std::fstream& fp, - const std::string& netlist_name) { - check_file_handler(fp); - - fp << "`include \"" << netlist_name << "\"" << std::endl; -} - -/******************************************************************** - * Print Verilog codes to define a preprocessing flag - *******************************************************************/ -void print_verilog_define_flag(std::fstream& fp, - const std::string& flag_name, - const int& flag_value) { - check_file_handler(fp); - - fp << "`define " << flag_name << " " << flag_value << std::endl; -} - -/************************************************ - * Generate include files for a Verilog netlist - ***********************************************/ -void print_verilog_include_defines_preproc_file(std::fstream& fp, - const std::string& verilog_dir) { - - /* Generate the file name */ - std::string include_file_path = format_dir_path(verilog_dir); - include_file_path += defines_verilog_file_name; - - print_verilog_include_netlist(fp, include_file_path); -} - -/************************************************ - * Print a Verilog comment line - ***********************************************/ -void print_verilog_comment(std::fstream& fp, - const std::string& comment) { - check_file_handler(fp); - - fp << "// " << comment << std::endl; -} - -/************************************************ - * Print the declaration of a Verilog preprocessing flag - ***********************************************/ -void print_verilog_preprocessing_flag(std::fstream& fp, - const std::string& preproc_flag) { - check_file_handler(fp); - - fp << "`ifdef " << preproc_flag << std::endl; -} - -/************************************************ - * Print the endif of a Verilog preprocessing flag - ***********************************************/ -void print_verilog_endif(std::fstream& fp) { - check_file_handler(fp); - - fp << "`endif" << std::endl; -} - -/************************************************ - * Print a Verilog module definition - * We use the following format: - * module (); - ***********************************************/ -void print_verilog_module_definition(std::fstream& fp, - const ModuleManager& module_manager, const ModuleId& module_id) { - check_file_handler(fp); - - print_verilog_comment(fp, std::string("----- Verilog module for " + module_manager.module_name(module_id) + " -----")); - - std::string module_head_line = "module " + module_manager.module_name(module_id) + "("; - fp << module_head_line; - - /* port type2type mapping */ - std::map port_type2type_map; - port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_CONKT; - - /* Port sequence: global, inout, input, output and clock ports, */ - size_t port_cnt = 0; - bool printed_ifdef = false; /* A flag to tell if an ifdef has been printed for the last port */ - for (const auto& kv : port_type2type_map) { - for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { - if (0 != port_cnt) { - /* Do not dump a comma for the first port */ - fp << "," << std::endl; - } - - if (true == printed_ifdef) { - /* Print an endif to pair the ifdef */ - print_verilog_endif(fp); - /* Reset the flag */ - printed_ifdef = false; - } - - ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name()); - VTR_ASSERT(ModulePortId::INVALID() != port_id); - /* Print pre-processing flag for a port, if defined */ - std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id); - if (false == preproc_flag.empty()) { - /* Print an ifdef Verilog syntax */ - print_verilog_preprocessing_flag(fp, preproc_flag); - /* Raise the flag */ - printed_ifdef = true; - } - - /* Create a space for "module " except the first line! */ - if (0 != port_cnt) { - std::string port_whitespace(module_head_line.length(), ' '); - fp << port_whitespace; - } - /* Print port: only the port name is enough */ - fp << port.get_name(); - - /* Increase the counter */ - port_cnt++; - } - } - fp << ");" << std::endl; -} - -/************************************************ - * Print a Verilog module ports based on the module id - ***********************************************/ -void print_verilog_module_ports(std::fstream& fp, - const ModuleManager& module_manager, const ModuleId& module_id) { - check_file_handler(fp); - - /* port type2type mapping */ - std::map port_type2type_map; - port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_INPUT; - port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_INPUT; - port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_OUTPUT; - port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_INOUT; - port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_INOUT; - port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_INPUT; - port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_OUTPUT; - port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_INPUT; - - /* Port sequence: global, inout, input, output and clock ports, */ - for (const auto& kv : port_type2type_map) { - for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { - ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name()); - VTR_ASSERT(ModulePortId::INVALID() != port_id); - /* Print pre-processing flag for a port, if defined */ - std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id); - if (false == preproc_flag.empty()) { - /* Print an ifdef Verilog syntax */ - print_verilog_preprocessing_flag(fp, preproc_flag); - } - - /* Print port */ - fp << "//----- " << module_manager.module_port_type_str(kv.first) << " -----" << std::endl; - fp << generate_verilog_port(kv.second, port); - fp << ";" << std::endl; - - if (false == preproc_flag.empty()) { - /* Print an endif to pair the ifdef */ - print_verilog_endif(fp); - } - } - } - - /* Output any port that is also wire connection */ - fp << std::endl; - fp << "//----- BEGIN wire-connection ports -----" << std::endl; - for (const auto& kv : port_type2type_map) { - for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { - /* Skip the ports that are not registered */ - ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name()); - VTR_ASSERT(ModulePortId::INVALID() != port_id); - if (false == module_manager.port_is_wire(module_id, port_id)) { - continue; - } - - /* Print pre-processing flag for a port, if defined */ - std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id); - if (false == preproc_flag.empty()) { - /* Print an ifdef Verilog syntax */ - print_verilog_preprocessing_flag(fp, preproc_flag); - } - - /* Print port */ - fp << generate_verilog_port(VERILOG_PORT_WIRE, port); - fp << ";" << std::endl; - - if (false == preproc_flag.empty()) { - /* Print an endif to pair the ifdef */ - print_verilog_endif(fp); - } - } - } - fp << "//----- END wire-connection ports -----" << std::endl; - fp << std::endl; - - - /* Output any port that is registered */ - fp << std::endl; - fp << "//----- BEGIN Registered ports -----" << std::endl; - for (const auto& kv : port_type2type_map) { - for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { - /* Skip the ports that are not registered */ - ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name()); - VTR_ASSERT(ModulePortId::INVALID() != port_id); - if (false == module_manager.port_is_register(module_id, port_id)) { - continue; - } - - /* Print pre-processing flag for a port, if defined */ - std::string preproc_flag = module_manager.port_preproc_flag(module_id, port_id); - if (false == preproc_flag.empty()) { - /* Print an ifdef Verilog syntax */ - print_verilog_preprocessing_flag(fp, preproc_flag); - } - - /* Print port */ - fp << generate_verilog_port(VERILOG_PORT_REG, port); - fp << ";" << std::endl; - - if (false == preproc_flag.empty()) { - /* Print an endif to pair the ifdef */ - print_verilog_endif(fp); - } - } - } - fp << "//----- END Registered ports -----" << std::endl; - fp << std::endl; -} - -/************************************************ - * Print a Verilog module declaration (definition + port list - * We use the following format: - * module (); - * - ***********************************************/ -void print_verilog_module_declaration(std::fstream& fp, - const ModuleManager& module_manager, const ModuleId& module_id) { - check_file_handler(fp); - - print_verilog_module_definition(fp, module_manager, module_id); - - print_verilog_module_ports(fp, module_manager, module_id); -} - - -/******************************************************************** - * Print an instance in Verilog format (a generic version) - * This function will require user to provide an instance name - * - * This function will output the port map by referring to a port-to-port - * mapping: - * -> - * The key of the port-to-port mapping is the port name of the module: - * The value of the port-to-port mapping is the port information of the instance - * With link between module and instance, the function can output a Verilog - * instance easily, supporting both explicit port mapping: - * .() - * and inexplicit port mapping - * - * - * Note that, it is not necessary that the port-to-port mapping - * covers all the module ports. - * Any instance/module port which are not specified in the port-to-port - * mapping will be output by the module port name. - *******************************************************************/ -void print_verilog_module_instance(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& module_id, - const std::string& instance_name, - const std::map& port2port_name_map, - const bool& use_explicit_port_map) { - - check_file_handler(fp); - - /* Check: all the key ports in the port2port_name_map does exist in the child module */ - for (const auto& kv : port2port_name_map) { - ModulePortId module_port_id = module_manager.find_module_port(module_id, kv.first); - VTR_ASSERT(ModulePortId::INVALID() != module_port_id); - } - - /* Print module name */ - fp << "\t" << module_manager.module_name(module_id) << " "; - /* Print instance name */ - fp << instance_name << " (" << std::endl; - - /* Print each port with/without explicit port map */ - /* port type2type mapping */ - std::map port_type2type_map; - port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_CONKT; - - /* Port sequence: global, inout, input, output and clock ports, */ - size_t port_cnt = 0; - for (const auto& kv : port_type2type_map) { - for (const auto& port : module_manager.module_ports_by_type(module_id, kv.first)) { - if (0 != port_cnt) { - /* Do not dump a comma for the first port */ - fp << "," << std::endl; - } - /* Print port */ - fp << "\t\t"; - /* if explicit port map is required, output the port name */ - if (true == use_explicit_port_map) { - fp << "." << port.get_name() << "("; - } - /* Try to find the instanced port name in the name map */ - if (port2port_name_map.find(port.get_name()) != port2port_name_map.end()) { - /* Found it, we assign the port name */ - /* TODO: make sure the port width matches! */ - ModulePortId module_port_id = module_manager.find_module_port(module_id, port.get_name()); - /* Get the port from module */ - BasicPort module_port = module_manager.module_port(module_id, module_port_id); - VTR_ASSERT(module_port.get_width() == port2port_name_map.at(port.get_name()).get_width()); - fp << generate_verilog_port(kv.second, port2port_name_map.at(port.get_name())); - } else { - /* Not found, we give the default port name */ - fp << generate_verilog_port(kv.second, port); - } - /* if explicit port map is required, output the pair of branket */ - if (true == use_explicit_port_map) { - fp << ")"; - } - port_cnt++; - } - } - - /* Print an end to the instance */ - fp << ");" << std::endl; -} - - -/************************************************ - * Print an instance for a Verilog module - * This function is a wrapper for the generic version of - * print_verilog_module_instance() - * This function create an instance name based on the index - * of the child module in its parent module - ***********************************************/ -void print_verilog_module_instance(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module_id, const ModuleId& child_module_id, - const std::map& port2port_name_map, - const bool& use_explicit_port_map) { - - /* Create instance name, _ */ - std::string instance_name = module_manager.module_name(child_module_id) - + "_" - + std::to_string(module_manager.num_instance(parent_module_id, child_module_id)) - + "_"; - - print_verilog_module_instance(fp, module_manager, child_module_id, instance_name, - port2port_name_map, use_explicit_port_map); -} - -/************************************************ - * Print an end line for a Verilog module - ***********************************************/ -void print_verilog_module_end(std::fstream& fp, - const std::string& module_name) { - check_file_handler(fp); - - fp << "endmodule" << std::endl; - print_verilog_comment(fp, std::string("----- END Verilog module for " + module_name + " -----")); - fp << std::endl; -} - -/************************************************ - * Generate a string of a Verilog port - ***********************************************/ -std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_port_type, - const BasicPort& port_info) { - std::string verilog_line; - - /* Ensure the port type is valid */ - VTR_ASSERT(verilog_port_type < NUM_VERILOG_PORT_TYPES); - - std::string size_str = "[" + std::to_string(port_info.get_lsb()) + ":" + std::to_string(port_info.get_msb()) + "]"; - - /* Only connection require a format of [:] - * others require a format of [:] - */ - if (VERILOG_PORT_CONKT == verilog_port_type) { - /* When LSB == MSB, we can use a simplified format []*/ - if ( 1 == port_info.get_width()) { - size_str = "[" + std::to_string(port_info.get_lsb()) + "]"; - } - verilog_line = port_info.get_name() + size_str; - } else { - verilog_line = VERILOG_PORT_TYPE_STRING[verilog_port_type]; - verilog_line += " " + size_str + " " + port_info.get_name(); - } - - return verilog_line; -} - -/******************************************************************** - * Evaluate if two Verilog ports can be merged: - * If the port name is same, it can merged - *******************************************************************/ -bool two_verilog_ports_mergeable(const BasicPort& portA, - const BasicPort& portB) { - if (0 == portA.get_name().compare(portB.get_name())) { - return true; - } - return false; -} - -/******************************************************************** - * Merge two Verilog ports, return the merged port - * The ports should have the same name - * The new LSB will be minimum of the LSBs of the two ports - * The new MSB will the maximum of the MSBs of the two ports - *******************************************************************/ -BasicPort merge_two_verilog_ports(const BasicPort& portA, - const BasicPort& portB) { - BasicPort merged_port; - - VTR_ASSERT(true == two_verilog_ports_mergeable(portA, portB)); - - merged_port.set_name(portA.get_name()); - merged_port.set_lsb((size_t)std::min((int)portA.get_lsb(), (int)portB.get_lsb())); - merged_port.set_msb((size_t)std::max((int)portA.get_msb(), (int)portB.get_msb())); - - return merged_port; -} - -/************************************************ - * This function takes a list of ports and - * combine the port string by comparing the name - * and width of ports. - * For example, two ports A and B share the same name is - * mergable as long as A's MSB + 1 == B's LSB - * Note that the port sequence really matters! - * This function will NOT change the sequence - * of ports in the list port_info - ***********************************************/ -std::vector combine_verilog_ports(const std::vector& ports) { - std::vector merged_ports; - - /* Directly return if there are no ports */ - if (0 == ports.size()) { - return merged_ports; - } - /* Push the first port to the merged ports */ - merged_ports.push_back(ports[0]); - - /* Iterate over ports */ - for (const auto& port : ports) { - /* Bypass the first port, it is already in the list */ - if (&port == &ports[0]) { - continue; - } - /* Identify if the port name can be potentially merged: if the port name is already in the merged port list, it may be merged */ - bool merged = false; - for (auto& merged_port : merged_ports) { - if (false == port.mergeable(merged_port)) { - /* Unable to merge, Go to next */ - continue; - } - /* May be merged, check LSB of port and MSB of merged_port */ - if (merged_port.get_msb() + 1 != port.get_lsb()) { - /* Unable to merge, Go to next */ - continue; - } - /* Reach here, we should merge the ports, - * LSB of merged_port remains the same, - * MSB of merged_port will be updated - * to the MSB of port - */ - merged_port.set_msb(port.get_msb()); - merged = true; - break; - } - if (false == merged) { - /* Unable to merge, add the port to merged port list */ - merged_ports.push_back(port); - } - } - - return merged_ports; -} - -/************************************************ - * Generate the string of a list of verilog ports - ***********************************************/ -std::string generate_verilog_ports(const std::vector& merged_ports) { - - /* Output the string of ports: - * If there is only one port in the merged_port list - * we only output the port. - * If there are more than one port in the merged port list, we output an concatenated port: - * {, , ... } - */ - VTR_ASSERT(0 < merged_ports.size()); - if ( 1 == merged_ports.size()) { - /* Use connection type of verilog port */ - return generate_verilog_port(VERILOG_PORT_CONKT, merged_ports[0]); - } - - std::string verilog_line = "{"; - for (const auto& port : merged_ports) { - /* The first port does not need a comma */ - if (&port != &merged_ports[0]) { - verilog_line += ", "; - } - verilog_line += generate_verilog_port(VERILOG_PORT_CONKT, port); - } - verilog_line += "}"; - - return verilog_line; -} - -/******************************************************************** - * Generate a bus port (could be used to create a local wire) - * for a list of Verilog ports - * The bus port will be created by aggregating the ports in the list - * A bus port name may be need only there are many ports with - * different names. It is hard to name the bus port - *******************************************************************/ -BasicPort generate_verilog_bus_port(const std::vector& input_ports, - const std::string& bus_port_name) { - /* Try to combine the ports */ - std::vector combined_input_ports = combine_verilog_ports(input_ports); - - /* Create a port data structure that is to be returned */ - BasicPort bus_port; - - if (1 == combined_input_ports.size()) { - bus_port = combined_input_ports[0]; - } else { - /* TODO: the naming could be more flexible? */ - bus_port.set_name(bus_port_name); - /* Deposite a [0:0] port */ - bus_port.set_width(1); - for (const auto& port : combined_input_ports) { - bus_port.combine(port); - } - } - - return bus_port; -} - -/******************************************************************** - * Generate a bus wire declaration for a list of Verilog ports - * Output ports: the local_wire name - * Input ports: the driving ports - * When there are more than two ports, a bus wiring will be created - * {, , ... } - *******************************************************************/ -std::string generate_verilog_local_wire(const BasicPort& output_port, - const std::vector& input_ports) { - /* Try to combine the ports */ - std::vector combined_input_ports = combine_verilog_ports(input_ports); - - /* If we have more than 1 port in the combined ports , - * output a local wire */ - VTR_ASSERT(0 < combined_input_ports.size()); - - /* Must check: the port width matches */ - size_t input_ports_width = 0; - for (const auto& port : combined_input_ports) { - /* We must have valid ports! */ - VTR_ASSERT( 0 < port.get_width() ); - input_ports_width += port.get_width(); - } - VTR_ASSERT( input_ports_width == output_port.get_width() ); - - std::string wire_str; - wire_str += generate_verilog_port(VERILOG_PORT_WIRE, output_port); - wire_str += " = "; - wire_str += generate_verilog_ports(combined_input_ports); - wire_str += ";"; - - return wire_str; -} - -/******************************************************************** - * Generate a string for a constant value in Verilog format: - * <#.of bits>'b - *******************************************************************/ -std::string generate_verilog_constant_values(const std::vector& const_values) { - std::string str = std::to_string(const_values.size()); - str += "'b"; - for (const auto& val : const_values) { - str += std::to_string(val); - } - return str; -} - -/******************************************************************** - * Generate a verilog port with a deposite of constant values - ********************************************************************/ -std::string generate_verilog_port_constant_values(const BasicPort& output_port, - const std::vector& const_values) { - std::string port_str; - - /* Must check: the port width matches */ - VTR_ASSERT( const_values.size() == output_port.get_width() ); - - port_str = generate_verilog_port(VERILOG_PORT_CONKT, output_port); - port_str += " = "; - port_str += generate_verilog_constant_values(const_values); - return port_str; -} - -/******************************************************************** - * Generate a wire connection, that assigns constant values to a - * Verilog port - *******************************************************************/ -void print_verilog_wire_constant_values(std::fstream& fp, - const BasicPort& output_port, - const std::vector& const_values) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - fp << "\t"; - fp << "assign "; - fp << generate_verilog_port_constant_values(output_port, const_values); - fp << ";" << std::endl; -} - -/******************************************************************** - * Deposit constant values to a Verilog port - *******************************************************************/ -void print_verilog_deposit_wire_constant_values(std::fstream& fp, - const BasicPort& output_port, - const std::vector& const_values) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - fp << "\t"; - fp << "$deposit("; - fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); - fp << ", "; - fp << generate_verilog_constant_values(const_values); - fp << ");" << std::endl; -} - -/******************************************************************** - * Generate a wire connection, that assigns constant values to a - * Verilog port - *******************************************************************/ -void print_verilog_force_wire_constant_values(std::fstream& fp, - const BasicPort& output_port, - const std::vector& const_values) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - fp << "\t"; - fp << "force "; - fp << generate_verilog_port_constant_values(output_port, const_values); - fp << ";" << std::endl; -} - -/******************************************************************** - * Generate a wire connection for two Verilog ports - * using "assign" syntax - *******************************************************************/ -void print_verilog_wire_connection(std::fstream& fp, - const BasicPort& output_port, - const BasicPort& input_port, - const bool& inverted) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Must check: the port width matches */ - VTR_ASSERT( input_port.get_width() == output_port.get_width() ); - - fp << "\t"; - fp << "assign "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); - fp << " = "; - - if (true == inverted) { - fp << "~"; - } - - fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port); - fp << ";" << std::endl; -} - -/******************************************************************** - * Generate a wire connection for two Verilog ports - * using "assign" syntax - *******************************************************************/ -void print_verilog_register_connection(std::fstream& fp, - const BasicPort& output_port, - const BasicPort& input_port, - const bool& inverted) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Must check: the port width matches */ - VTR_ASSERT( input_port.get_width() == output_port.get_width() ); - - fp << "\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); - fp << " <= "; - - if (true == inverted) { - fp << "~"; - } - - fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port); - fp << ";" << std::endl; -} - - -/******************************************************************** - * Generate an instance of a buffer module - * with given information about the input and output ports of instance - * - * Buffer instance - * +----------------------------------------+ - * instance_input_port --->| buffer_input_port buffer_output_port|----> instance_output_port - * +----------------------------------------+ - * - * Restrictions: - * Buffer must have only 1 input (non-global) port and 1 output (non-global) port - *******************************************************************/ -void print_verilog_buffer_instance(std::fstream& fp, - ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const ModuleId& parent_module_id, - const CircuitModelId& buffer_model, - const BasicPort& instance_input_port, - const BasicPort& instance_output_port) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ - std::vector buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_INPUT, true); - std::vector buffer_model_output_ports = circuit_lib.model_ports_by_type(buffer_model, SPICE_MODEL_PORT_OUTPUT, true); - VTR_ASSERT(1 == buffer_model_input_ports.size()); - VTR_ASSERT(1 == buffer_model_output_ports.size()); - - /* Get the moduleId for the buffer module */ - ModuleId buffer_module_id = module_manager.find_module(circuit_lib.model_name(buffer_model)); - /* We must have one */ - VTR_ASSERT(ModuleId::INVALID() != buffer_module_id); - - /* Create a port-to-port map */ - std::map buffer_port2port_name_map; - - /* Build the link between buffer_input_port[0] and output_node_pre_buffer - * Build the link between buffer_output_port[0] and output_node_bufferred - */ - { /* Create a code block to accommodate the local variables */ - std::string module_input_port_name = circuit_lib.port_lib_name(buffer_model_input_ports[0]); - buffer_port2port_name_map[module_input_port_name] = instance_input_port; - std::string module_output_port_name = circuit_lib.port_lib_name(buffer_model_output_ports[0]); - buffer_port2port_name_map[module_output_port_name] = instance_output_port; - } - - /* Output an instance of the module */ - print_verilog_module_instance(fp, module_manager, parent_module_id, buffer_module_id, buffer_port2port_name_map, circuit_lib.dump_explicit_port_map(buffer_model)); - - /* IMPORTANT: this update MUST be called after the instance outputting!!!! - * update the module manager with the relationship between the parent and child modules - */ - module_manager.add_child_module(parent_module_id, buffer_module_id); -} - -/******************************************************************** - * Print local wires that are used for SRAM configuration - * The local wires are strongly dependent on the organization of SRAMs. - * Standalone SRAMs: - * ----------------- - * No need for local wires, their outputs are port of the module - * - * Module - * +------------------------------+ - * | Sub-module | - * | +---------------------+ | - * | | sram_out|---->|---->sram_out - * | | | | - * | | sram_out|---->|---->sram_out - * | | | | - * | +---------------------+ | - * +------------------------------+ - * - * Configuration chain-style - * ------------------------- - * wire [0:N] config_bus - * - * - * Module - * +--------------------------------------------------------------+ - * | config_bus config_bus config_bus config_bus | - * | [0] [1] [2] [N] | - * | | | | | | - * | v v v v | - * ccff_head| ----------+ +---------+ +------------+ +----------------|-> ccff_tail - * | | ^ | ^ | ^ | - * | head v |tail v | v | | - * | +----------+ +----------+ +----------+ | - * | | Memory | | Memory | | Memory | | - * | | Module | | Module | ... | Module | | - * | | [0] | | [1] | | [N] | | - * | +----------+ +----------+ +----------+ | - * | | | | | - * | v v v | - * | +----------+ +----------+ +----------+ | - * | | MUX | | MUX | | MUX | | - * | | Module | | Module | ... | Module | | - * | | [0] | | [1] | | [N] | | - * | +----------+ +----------+ +----------+ | - * | | - * +--------------------------------------------------------------+ - * - * Memory bank-style - * ----------------- - * two ports will be added, which are regular output and inverted output - * Note that the outputs are the data outputs of SRAMs - * BL/WLs of memory decoders are ports of module but not local wires - * - * Module - * +-------------------------------------------------+ - * | | - BL/WL bus --+--------+------------+-----------------+ | - * | | | | | - * | BL/WL v BL/WL v BL/WL v | - * | +----------+ +----------+ +----------+ | - * | | Memory | | Memory | | Memory | | - * | | Module | | Module | ... | Module | | - * | | [0] | | [1] | | [N] | | - * | +----------+ +----------+ +----------+ | - * | | | | | - * | v v v | - * | +----------+ +----------+ +----------+ | - * | | MUX | | MUX | | MUX | | - * | | Module | | Module | ... | Module | | - * | | [0] | | [1] | | [N] | | - * | +----------+ +----------+ +----------+ | - * | | - * +-------------------------------------------------+ - * - ********************************************************************/ -void print_verilog_local_sram_wires(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz sram_orgz_type, - const size_t& port_size) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - /* Port size must be at least one! */ - if (0 == port_size) { - return; - } - - /* Depend on the configuraion style */ - switch(sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* Nothing to do here */ - break; - case SPICE_SRAM_SCAN_CHAIN: { - /* Generate the name of local wire for the CCFF inputs, CCFF output and inverted output */ - /* [0] => CCFF input */ - BasicPort ccff_config_bus_port(generate_local_config_bus_port_name(), port_size); - fp << generate_verilog_port(VERILOG_PORT_WIRE, ccff_config_bus_port) << ";" << std::endl; - /* Connect first CCFF to the head */ - /* Head is always a 1-bit port */ - BasicPort ccff_head_port(generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_INPUT), 1); - BasicPort ccff_head_local_port(ccff_config_bus_port.get_name(), 1); - print_verilog_wire_connection(fp, ccff_head_local_port, ccff_head_port, false); - /* Connect last CCFF to the tail */ - /* Tail is always a 1-bit port */ - BasicPort ccff_tail_port(generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), 1); - BasicPort ccff_tail_local_port(ccff_config_bus_port.get_name(), ccff_config_bus_port.get_msb(), ccff_config_bus_port.get_msb()); - print_verilog_wire_connection(fp, ccff_tail_local_port, ccff_tail_port, false); - break; - } - case SPICE_SRAM_MEMORY_BANK: { - /* Generate the name of local wire for the SRAM output and inverted output */ - std::vector sram_ports; - /* [0] => SRAM output */ - sram_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INPUT), port_size)); - /* [1] => SRAM inverted output */ - sram_ports.push_back(BasicPort(generate_sram_local_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), port_size)); - /* Print local wire definition */ - for (const auto& sram_port : sram_ports) { - fp << generate_verilog_port(VERILOG_PORT_WIRE, sram_port) << ";" << std::endl; - } - - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/********************************************************************* - * Print a number of bus ports which are wired to the configuration - * ports of a CMOS (SRAM-based) routing multiplexer - * This port is supposed to be used locally inside a Verilog/SPICE module - * - * The following shows a few representative examples: - * - * For standalone configuration style: - * ------------------------------------ - * No bus needed - * - * Configuration chain-style - * ------------------------- - * wire [0:N] config_bus - * - * config_bus config_bus config_bus config_bus - * [0] [1] [2] [N] - * | | | | - * v v v v - * ccff_head ----------+ +---------+ +------------+ +----> ccff_tail - * | ^ | ^ | ^ - * head v |tail v | v | - * +----------+ +----------+ +----------+ - * | Memory | | Memory | | Memory | - * | Module | | Module | ... | Module | - * | [0] | | [1] | | [N] | - * +----------+ +----------+ +----------+ - * | | | - * v v v - * +----------+ +----------+ +----------+ - * | MUX | | MUX | | MUX | - * | Module | | Module | ... | Module | - * | [0] | | [1] | | [N] | - * +----------+ +----------+ +----------+ - * - * Memory bank-style - * ----------------- - * BL/WL bus --+------------+--------------------> - * | | | - * BL/WL v BL/WL v BL/WL v - * +----------+ +----------+ +----------+ - * | Memory | | Memory | | Memory | - * | Module | | Module | ... | Module | - * | [0] | | [1] | | [N] | - * +----------+ +----------+ +----------+ - * | | | - * v v v - * +----------+ +----------+ +----------+ - * | MUX | | MUX | | MUX | - * | Module | | Module | ... | Module | - * | [0] | | [1] | | [N] | - * +----------+ +----------+ +----------+ - * - *********************************************************************/ -void print_verilog_local_config_bus(std::fstream& fp, - const std::string& prefix, - const e_sram_orgz& sram_orgz_type, - const size_t& instance_id, - const size_t& num_conf_bits) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - switch(sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* Not need for configuration bus - * The configuration ports of SRAM are directly wired to the ports of modules - */ - break; - case SPICE_SRAM_SCAN_CHAIN: - case SPICE_SRAM_MEMORY_BANK: { - /* Two configuration buses should be outputted - * One for the regular SRAM ports of a routing multiplexer - * The other for the inverted SRAM ports of a routing multiplexer - */ - BasicPort config_port(generate_local_sram_port_name(prefix, instance_id, SPICE_MODEL_PORT_INPUT), - num_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, config_port) << ";" << std::endl; - BasicPort inverted_config_port(generate_local_sram_port_name(prefix, instance_id, SPICE_MODEL_PORT_OUTPUT), - num_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_config_port) << ";" << std::endl; - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/********************************************************************* - * Print a number of bus ports which are wired to the configuration - * ports of a ReRAM-based routing multiplexer - * This port is supposed to be used locally inside a Verilog/SPICE module - * - * Currently support: - * For memory-bank configuration style: - * ------------------------------------ - * Different than CMOS routing multiplexers, ReRAM multiplexers require - * reserved BL/WLs to be grouped in buses - * - * Module Port - * | - * v - * regular/reserved bus_port --+----------------+----> ... - * | | - * bl/wl/../sram_ports v v - * +-----------+ +-----------+ - * | Memory | | Memory | - * | Module[0] | | Module[1] | ... - * +-----------+ +-----------+ - * | | - * v v - * +-----------+ +-----------+ - * | Routing | | Routing | - * | MUX [0] | | MUX[1] | ... - * +-----------+ +-----------+ - * - *********************************************************************/ -static -void print_verilog_rram_mux_config_bus(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const e_sram_orgz& sram_orgz_type, - const size_t& mux_size, - const size_t& mux_instance_id, - const size_t& num_reserved_conf_bits, - const size_t& num_conf_bits) { - /* Make sure we have a valid file handler*/ - check_file_handler(fp); - - switch(sram_orgz_type) { - case SPICE_SRAM_STANDALONE: - /* Not need for configuration bus - * The configuration ports of SRAM are directly wired to the ports of modules - */ - break; - case SPICE_SRAM_SCAN_CHAIN: { - /* Not supported yet. - * Configuration chain may be only applied to ReRAM-based multiplexers with local decoders - */ - break; - } - case SPICE_SRAM_MEMORY_BANK: { - /* This is currently most used in ReRAM FPGAs */ - /* Print configuration bus to group reserved BL/WLs */ - BasicPort reserved_bl_bus(generate_reserved_sram_port_name(SPICE_MODEL_PORT_BL), - num_reserved_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, reserved_bl_bus) << ";" << std::endl; - BasicPort reserved_wl_bus(generate_reserved_sram_port_name(SPICE_MODEL_PORT_WL), - num_reserved_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, reserved_wl_bus) << ";" << std::endl; - - /* Print configuration bus to group BL/WLs */ - BasicPort bl_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 0, false), - num_conf_bits + num_reserved_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, bl_bus) << ";" << std::endl; - BasicPort wl_bus(generate_mux_config_bus_port_name(circuit_lib, mux_model, mux_size, 1, false), - num_conf_bits + num_reserved_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, wl_bus) << ";" << std::endl; - - /* Print bus to group SRAM outputs, this is to interface memory cells to routing multiplexers */ - BasicPort sram_output_bus(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), - num_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, sram_output_bus) << ";" << std::endl; - BasicPort inverted_sram_output_bus(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_OUTPUT), - num_conf_bits); - fp << generate_verilog_port(VERILOG_PORT_WIRE, inverted_sram_output_bus) << ";" << std::endl; - - /* Get the SRAM model of the mux_model */ - std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); - /* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */ - VTR_ASSERT( 1 == sram_models.size() ); - - /* Wire the reserved configuration bits to part of bl/wl buses */ - BasicPort bl_bus_reserved_bits(bl_bus.get_name(), num_reserved_conf_bits); - print_verilog_wire_connection(fp, bl_bus_reserved_bits, reserved_bl_bus, false); - BasicPort wl_bus_reserved_bits(wl_bus.get_name(), num_reserved_conf_bits); - print_verilog_wire_connection(fp, wl_bus_reserved_bits, reserved_wl_bus, false); - - /* Connect SRAM BL/WLs to bus */ - BasicPort mux_bl_wire(generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_BL), - num_conf_bits); - BasicPort bl_bus_regular_bits(bl_bus.get_name(), num_reserved_conf_bits, num_reserved_conf_bits + num_conf_bits - 1); - print_verilog_wire_connection(fp, bl_bus_regular_bits, mux_bl_wire, false); - BasicPort mux_wl_wire(generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_WL), - num_conf_bits); - BasicPort wl_bus_regular_bits(wl_bus.get_name(), num_reserved_conf_bits, num_reserved_conf_bits + num_conf_bits - 1); - print_verilog_wire_connection(fp, wl_bus_regular_bits, mux_wl_wire, false); - - break; - } - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid SRAM organization!\n", - __FILE__, __LINE__); - exit(1); - } - -} - -/********************************************************************* - * Print a number of bus ports which are wired to the configuration - * ports of a memory module, which consists of a number of configuration - * memory cells, such as SRAMs. - * Note that the configuration bus will only interface the memory - * module, rather than the programming routing multiplexers, LUTs, IOs - * etc. This helps us to keep clean and simple Verilog generation - *********************************************************************/ -void print_verilog_mux_config_bus(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const e_sram_orgz& sram_orgz_type, - const size_t& mux_size, - const size_t& mux_instance_id, - const size_t& num_reserved_conf_bits, - const size_t& num_conf_bits) { - /* Depend on the design technology of this MUX: - * bus connections are different - * SRAM MUX: bus is connected to the output ports of SRAM - * RRAM MUX: bus is connected to the BL/WL of MUX - * TODO: Maybe things will become even more complicated, - * the bus connections may depend on the type of configuration circuit... - * Currently, this is fine. - */ - switch (circuit_lib.design_tech_type(mux_model)) { - case SPICE_MODEL_DESIGN_CMOS: { - std::string prefix = generate_mux_subckt_name(circuit_lib, mux_model, mux_size, std::string()); - print_verilog_local_config_bus(fp, prefix, sram_orgz_type, mux_instance_id, num_conf_bits); - break; - } - case SPICE_MODEL_DESIGN_RRAM: - print_verilog_rram_mux_config_bus(fp, circuit_lib, mux_model, sram_orgz_type, mux_size, mux_instance_id, num_reserved_conf_bits, num_conf_bits); - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "(File:%s,[LINE%d])Invalid design technology for routing multiplexer!\n", - __FILE__, __LINE__); - exit(1); - } -} - -/********************************************************************* - * Print a wire to connect MUX configuration ports - * This function connects the sram ports to the ports of a Verilog module - * used for formal verification - * - * Note: MSB and LSB of formal verification configuration bus MUST be updated - * before running this function !!!! - *********************************************************************/ -void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const size_t& mux_size, - const size_t& mux_instance_id, - const size_t& num_conf_bits, - const BasicPort& fm_config_bus) { - BasicPort mux_sram_output(generate_mux_sram_port_name(circuit_lib, mux_model, mux_size, mux_instance_id, SPICE_MODEL_PORT_INPUT), - num_conf_bits); - /* Get the SRAM model of the mux_model */ - std::vector sram_models = find_circuit_sram_models(circuit_lib, mux_model); - /* TODO: maybe later multiplexers may have mode select ports... This should be relaxed */ - VTR_ASSERT( 1 == sram_models.size() ); - BasicPort formal_verification_port; - formal_verification_port.set_name(generate_formal_verification_sram_port_name(circuit_lib, sram_models[0])); - VTR_ASSERT(num_conf_bits == fm_config_bus.get_width()); - formal_verification_port.set_lsb(fm_config_bus.get_lsb()); - formal_verification_port.set_msb(fm_config_bus.get_msb()); - print_verilog_wire_connection(fp, mux_sram_output, formal_verification_port, false); -} - -/******************************************************************** - * Print stimuli for a pulse generation - * - * |<--- pulse width --->| - * +------ flip_value - * | - * initial_value ----------------------+ - * - *******************************************************************/ -void print_verilog_pulse_stimuli(std::fstream& fp, - const BasicPort& port, - const size_t& initial_value, - const float& pulse_width, - const size_t& flip_value) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Config_done signal: indicate when configuration is finished */ - fp << "initial" << std::endl; - fp << "\tbegin" << std::endl; - fp << "\t"; - std::vector initial_values(port.get_width(), initial_value); - fp << "\t"; - fp << generate_verilog_port_constant_values(port, initial_values); - fp << ";" << std::endl; - - /* if flip_value is the same as initial value, we do not need to flip the signal ! */ - if (flip_value != initial_value) { - fp << "\t" << "#" << std::setprecision(10) << pulse_width; - std::vector port_flip_values(port.get_width(), flip_value); - fp << "\t"; - fp << generate_verilog_port_constant_values(port, port_flip_values); - fp << ";" << std::endl; - } - - fp << "\tend" << std::endl; - - /* Print an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Print stimuli for a pulse generation - * This function supports multiple signal switching under different pulse width - * - * |<-- wait condition -->| - * |<--- pulse width --->| - * +------ flip_values - * | - * initial_value ------- ... --------------------------------+ - * - *******************************************************************/ -void print_verilog_pulse_stimuli(std::fstream& fp, - const BasicPort& port, - const size_t& initial_value, - const std::vector& pulse_widths, - const std::vector& flip_values, - const std::string& wait_condition) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Config_done signal: indicate when configuration is finished */ - fp << "initial" << std::endl; - fp << "\tbegin" << std::endl; - fp << "\t"; - std::vector initial_values(port.get_width(), initial_value); - fp << "\t"; - fp << generate_verilog_port_constant_values(port, initial_values); - fp << ";" << std::endl; - - /* Set a wait condition if specified */ - if (false == wait_condition.empty()) { - fp << "\twait(" << wait_condition << ")" << std::endl; - } - - /* Number of flip conditions and values should match */ - VTR_ASSERT(flip_values.size() == pulse_widths.size()); - for (size_t ipulse = 0; ipulse < pulse_widths.size(); ++ipulse) { - fp << "\t" << "#" << std::setprecision(10) << pulse_widths[ipulse]; - std::vector port_flip_value(port.get_width(), flip_values[ipulse]); - fp << "\t"; - fp << generate_verilog_port_constant_values(port, port_flip_value); - fp << ";" << std::endl; - } - - fp << "\tend" << std::endl; - - /* Print an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Print stimuli for a clock signal - * This function can support if the clock signal should wait for a period - * of time and then start - * pulse width - * |<----->| - * +-------+ +-------+ - * | | | | - * initial_value --- ... ---+ +-------+ +------ ... - * |<--wait_condition-->| - * - *******************************************************************/ -void print_verilog_clock_stimuli(std::fstream& fp, - const BasicPort& port, - const size_t& initial_value, - const float& pulse_width, - const std::string& wait_condition) { - /* Validate the file stream */ - check_file_handler(fp); - - /* Config_done signal: indicate when configuration is finished */ - fp << "initial" << std::endl; - fp << "\tbegin" << std::endl; - - std::vector initial_values(port.get_width(), initial_value); - fp << "\t\t"; - fp << generate_verilog_port_constant_values(port, initial_values); - fp << ";" << std::endl; - - fp << "\tend" << std::endl; - fp << "always"; - - /* Set a wait condition if specified */ - if (true == wait_condition.empty()) { - fp << std::endl; - } else { - fp << " wait(" << wait_condition << ")" << std::endl; - } - - fp << "\tbegin" << std::endl; - fp << "\t\t" << "#" << std::setprecision(10) << pulse_width; - - fp << "\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, port); - fp << " = "; - fp << "~"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, port); - fp << ";" << std::endl; - - fp << "\tend" << std::endl; - - /* Print an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Output a header file that includes a number of Verilog netlists - * so that it can be easily included in a top-level netlist - ********************************************************************/ -void print_verilog_netlist_include_header_file(const std::vector& netlists_to_be_included, - const char* subckt_dir, - const char* header_file_name) { - std::string verilog_fname(std::string(subckt_dir) + std::string(header_file_name)); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - check_file_handler(fp); - - /* Generate the descriptions*/ - print_verilog_file_header(fp, "Header file to include other Verilog netlists"); - - /* Output file names */ - for (const std::string& netlist_name : netlists_to_be_included) { - fp << "`include \"" << netlist_name << "\"" << std::endl; - } - - /* close file stream */ - fp.close(); -} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h deleted file mode 100644 index c2aaf1b38..000000000 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ /dev/null @@ -1,175 +0,0 @@ -/************************************************ - * Header file for verilog_writer_utils.cpp - * Include function declaration for most frequently - * used Verilog writers - ***********************************************/ -#ifndef VERILOG_WRITER_UTILS_H -#define VERILOG_WRITER_UTILS_H - -#include -#include -#include -#include "verilog_global.h" -#include "device_port.h" -#include "module_manager.h" - -/* Tips: for naming your function in this header/source file - * If a function outputs to a file, its name should begin with "print_verilog" - * If a function creates a string without outputting to a file, its name should begin with "generate_verilog" - * Please show respect to this naming convention, in order to keep a clean header/source file - * as well maintain a easy way to identify the functions - */ - -void print_verilog_file_header(std::fstream& fp, - const std::string& usage); - -void print_verilog_include_netlist(std::fstream& fp, - const std::string& netlist_name); - -void print_verilog_define_flag(std::fstream& fp, - const std::string& flag_name, - const int& flag_value); - -void print_verilog_include_defines_preproc_file(std::fstream& fp, - const std::string& verilog_dir); - -void print_verilog_comment(std::fstream& fp, - const std::string& comment); - -void print_verilog_preprocessing_flag(std::fstream& fp, - const std::string& preproc_flag); - -void print_verilog_endif(std::fstream& fp); - -void print_verilog_module_definition(std::fstream& fp, - const ModuleManager& module_manager, const ModuleId& module_id); - -void print_verilog_module_ports(std::fstream& fp, - const ModuleManager& module_manager, const ModuleId& module_id); - -void print_verilog_module_declaration(std::fstream& fp, - const ModuleManager& module_manager, const ModuleId& module_id); - -void print_verilog_module_instance(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& module_id, - const std::string& instance_name, - const std::map& port2port_name_map, - const bool& use_explicit_port_map); - -void print_verilog_module_instance(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& parent_module_id, const ModuleId& child_module_id, - const std::map& port2port_name_map, - const bool& use_explicit_port_map); - -void print_verilog_module_end(std::fstream& fp, - const std::string& module_name); - -std::string generate_verilog_port(const enum e_dump_verilog_port_type& dump_port_type, - const BasicPort& port_info); - -bool two_verilog_ports_mergeable(const BasicPort& portA, - const BasicPort& portB); - -BasicPort merge_two_verilog_ports(const BasicPort& portA, - const BasicPort& portB); - -std::vector combine_verilog_ports(const std::vector& ports); - -std::string generate_verilog_ports(const std::vector& merged_ports); - -BasicPort generate_verilog_bus_port(const std::vector& input_ports, - const std::string& bus_port_name); - -std::string generate_verilog_local_wire(const BasicPort& output_port, - const std::vector& input_ports); - -std::string generate_verilog_constant_values(const std::vector& const_values); - -std::string generate_verilog_port_constant_values(const BasicPort& output_port, - const std::vector& const_values); - -void print_verilog_wire_constant_values(std::fstream& fp, - const BasicPort& output_port, - const std::vector& const_values); - -void print_verilog_deposit_wire_constant_values(std::fstream& fp, - const BasicPort& output_port, - const std::vector& const_values); - -void print_verilog_force_wire_constant_values(std::fstream& fp, - const BasicPort& output_port, - const std::vector& const_values); - -void print_verilog_wire_connection(std::fstream& fp, - const BasicPort& output_port, - const BasicPort& input_port, - const bool& inverted); - -void print_verilog_register_connection(std::fstream& fp, - const BasicPort& output_port, - const BasicPort& input_port, - const bool& inverted); - -void print_verilog_buffer_instance(std::fstream& fp, - ModuleManager& module_manager, - const CircuitLibrary& circuit_lib, - const ModuleId& parent_module_id, - const CircuitModelId& buffer_model, - const BasicPort& instance_input_port, - const BasicPort& instance_output_port); - -void print_verilog_local_sram_wires(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& sram_model, - const e_sram_orgz sram_orgz_type, - const size_t& port_size); - -void print_verilog_local_config_bus(std::fstream& fp, - const std::string& prefix, - const e_sram_orgz& sram_orgz_type, - const size_t& instance_id, - const size_t& num_conf_bits); - -void print_verilog_mux_config_bus(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const e_sram_orgz& sram_orgz_type, - const size_t& mux_size, - const size_t& mux_instance_id, - const size_t& num_reserved_conf_bits, - const size_t& num_conf_bits); - -void print_verilog_formal_verification_mux_sram_ports_wiring(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& mux_model, - const size_t& mux_size, - const size_t& mux_instance_id, - const size_t& num_conf_bits, - const BasicPort& fm_config_bus); - -void print_verilog_pulse_stimuli(std::fstream& fp, - const BasicPort& port, - const size_t& initial_value, - const float& pulse_width, - const size_t& flip_value); - -void print_verilog_pulse_stimuli(std::fstream& fp, - const BasicPort& port, - const size_t& initial_value, - const std::vector& pulse_widths, - const std::vector& flip_values, - const std::string& wait_condition); - -void print_verilog_clock_stimuli(std::fstream& fp, - const BasicPort& port, - const size_t& initial_value, - const float& pulse_width, - const std::string& wait_condition); - -void print_verilog_netlist_include_header_file(const std::vector& netlists_to_be_included, - const char* subckt_dir, - const char* header_file_name); - -#endif diff --git a/vpr7_x2p/vpr/SRC/main.c b/vpr7_x2p/vpr/SRC/main.c deleted file mode 100644 index c6203c82b..000000000 --- a/vpr7_x2p/vpr/SRC/main.c +++ /dev/null @@ -1,91 +0,0 @@ -/** - VPR is a CAD tool used to conduct FPGA architecture exploration. It takes, as input, a technology-mapped netlist and a description of the FPGA architecture being investigated. - VPR then generates a packed, placed, and routed FPGA (in .net, .place, and .route files respectively) that implements the input netlist. - - This file is where VPR starts execution. - - Key files in VPR: - 1. libarchfpga/physical_types.h - Data structures that define the properties of the FPGA architecture - 2. vpr_types.h - Very major file that defines the core data structures used in VPR. This includes detailed architecture information, user netlist data structures, and data structures that describe the mapping between those two. - 3. globals.h - Defines the global variables used by VPR. - */ - - -#include -#include -#include -#include - -#include "vpr_api.h" - -/** - * VPR program - * Generate FPGA architecture given architecture description - * Pack, place, and route circuit into FPGA architecture - * Electrical timing analysis on results - * - * Overall steps - * 1. Initialization - * 2. Pack - * 3. Place-and-route and timing analysis - * 4. Clean up - */ -int main(int argc, char **argv) { - t_options Options; - t_arch Arch; - t_vpr_setup vpr_setup; - clock_t entire_flow_begin,entire_flow_end; - - entire_flow_begin = clock(); - - /* Read options, architecture, and circuit netlist */ - vpr_init(argc, argv, &Options, &vpr_setup, &Arch); - - /* If the user requests packing, do packing */ - if (vpr_setup.PackerOpts.doPacking) { - vpr_pack(vpr_setup, Arch); - } - - if (vpr_setup.PlacerOpts.doPlacement || vpr_setup.RouterOpts.doRouting) { - vpr_init_pre_place_and_route(vpr_setup, Arch); - vpr_place_and_route(vpr_setup, Arch); -#if 0 - if(vpr_setup.RouterOpts.doRouting) { - vpr_resync_post_route_netlist_to_TI_CLAY_v1_architecture(&Arch); - } -#endif - } - - if (vpr_setup.PowerOpts.do_power) { - vpr_power_estimation(vpr_setup, Arch); - } - - /* Run FPGA-SPICE tool suites*/ - if (TRUE == vpr_setup.FPGA_SPICE_Opts.do_fpga_spice) { - vpr_fpga_x2p_tool_suites(vpr_setup, Arch); - } - - entire_flow_end = clock(); - - #ifdef CLOCKS_PER_SEC - vpr_printf(TIO_MESSAGE_INFO, "The entire flow of VPR took %g seconds.\n", (float)(entire_flow_end - entire_flow_begin) / CLOCKS_PER_SEC); - #else - vpr_printf(TIO_MESSAGE_INFO, "The entire flow of VPR took %g seconds.\n", (float)(entire_flow_end - entire_flow_begin) / CLK_PER_SEC); - #endif - - /* free data structures */ - vpr_free_all(Arch, Options, vpr_setup); - - /* Close those file handlers for a clean valgrind */ - fclose(stdin); - fclose(stdout); - fclose(stderr); - - /* Return 0 to single success to scripts */ - return 0; -} - - - - - diff --git a/vpr7_x2p/vpr/SRC/mrfpga/buffer_insertion.c b/vpr7_x2p/vpr/SRC/mrfpga/buffer_insertion.c deleted file mode 100644 index 6fc05be31..000000000 --- a/vpr7_x2p/vpr/SRC/mrfpga/buffer_insertion.c +++ /dev/null @@ -1,570 +0,0 @@ -#include -#include "util.h" -/* Xifan TANG */ -#include "physical_types.h" -/* END */ -#include "vpr_types.h" -#include "globals.h" -#include "buffer_insertion.h" -/* Xifan TANG */ -#include "mrfpga_util.h" -#include "mrfpga_globals.h" -#include "net_delay_types.h" -#include "net_delay_local_void.h" -/* END */ - -/* memristor */ -typedef struct s_buffer_plan {t_linked_int* inode_head; t_linked_int* sink_head; float* sink_delay; float C_downstream; float Tdel;} t_buffer_plan; -typedef struct s_buffer_plan_node { t_buffer_plan value; struct s_buffer_plan_node* next;} t_buffer_plan_node; -typedef struct s_buffer_plan_list { t_buffer_plan_node* front; } t_buffer_plan_list; - -/* memristor */ -static t_buffer_plan_list get_empty_buffer_plan_list( ); -static t_buffer_plan_list join_left_plan_list_into_whole( t_buffer_plan_list left, t_buffer_plan_list* whole, int num_whole, t_buffer_plan_list current, int num_pins ); -static void free_buffer_list( t_buffer_plan_list list ); -static t_buffer_plan_list insert_buffer( t_buffer_plan_list list, int inode, float C, float R, float Tdel, int num_pins ); -static t_buffer_plan insert_wire_to_buffer_plan( t_buffer_plan plan, float C, float R); -static void insert_wire_to_buffer_list( t_buffer_plan_list list, float C,float R); -static void insert_switch_to_buffer_list( t_buffer_plan_list list, struct s_switch_inf switch_inf_local); -static t_buffer_plan insert_switch_to_buffer_plan( t_buffer_plan plan, struct s_switch_inf switch_inf_local); -static t_buffer_plan_list insert_buffer_plan_to_list( t_buffer_plan plan, t_buffer_plan_list list ); -static void save_best_buffer_list( t_linked_int* best_list ); -static void free_best_buffer_list( ); -static int get_int_list_length( t_linked_int* list ); -static void save_best_timing( float* sink_delay, t_linked_int* index, float* net_delay ); -static int alloc_isink_to_inode( int inet, int** isink_to_inode_ptr ); -static t_buffer_plan_list try_buffer_rc_tree (t_rc_node* rc_node, int num_pins, int* isink_to_inode); -static t_buffer_plan get_init_buffer_plan( int inode, int num_pins, int* isink_to_inode ); -static t_buffer_plan_list get_init_buffer_plan_list( int inode, int num_pins, int* isink_to_inode ); -static t_buffer_plan combine_buffer_plan( t_buffer_plan slow_branch, t_buffer_plan* plan_whole, int num_whole, int num_pins ); -static void copy_delay( float* base, float* source, t_linked_int* index ); -static void add_delay_to_array( float* sink_delay, t_linked_int* index, float delay_addition ); -static float* copy_from_float_array( float* source, int num ); - -void try_buffer_for_net( int inet, t_rc_node** rc_node_free_list, t_linked_rc_edge** rc_edge_free_list, t_linked_rc_ptr* rr_node_to_rc_node, float* net_delay ); -/* memristor */ - -void try_buffer_for_routing ( float** net_delay ) { - - t_rc_node *rc_node_free_list; - t_linked_rc_edge *rc_edge_free_list; - int inet; - t_linked_rc_ptr *rr_node_to_rc_node; /* [0..num_rr_nodes-1] */ - - rr_node_to_rc_node = (t_linked_rc_ptr *) my_calloc (num_rr_nodes, - sizeof (t_linked_rc_ptr)); - - rc_node_free_list = NULL; - rc_edge_free_list = NULL; - - free_best_buffer_list( ); - for (inet=0;inetvalue.Tdel < best.Tdel || ( traverse->value.Tdel == best.Tdel && get_int_list_length( traverse->value.inode_head ) < get_int_list_length( best.inode_head ) ) ) - { - best = traverse->value;; - } - traverse = traverse->next; - } - crit_delay = max( crit_delay, best.Tdel ); - save_best_buffer_list( best.inode_head ); - save_best_timing( best.sink_delay, best.sink_head, net_delay ); - free_buffer_list( plan_list ); - free_rc_tree (rc_root, rc_node_free_list, rc_edge_free_list); - reset_rr_node_to_rc_node (rr_node_to_rc_node, inet ); - free( isink_to_inode ); - } -} - -static void save_best_timing( float* sink_delay, t_linked_int* index, float* net_delay ) -{ - t_linked_int* traverse; - traverse = index; - while( traverse != NULL ) - { - net_delay[traverse->data] = sink_delay[traverse->data]; - traverse = traverse->next; - } -} - -static int alloc_isink_to_inode( int inet, int** isink_to_inode_ptr ) -{ - int i; - int num_pins = clb_net[inet].num_sinks + 1; - *isink_to_inode_ptr = (int*)my_malloc( sizeof(int) * num_pins ); - for( i = 1; i < num_pins; i++ ) - { - (*isink_to_inode_ptr)[i] = net_rr_terminals[inet][i]; - } - return num_pins; -} - -static int get_int_list_length( t_linked_int* list ) -{ - t_linked_int* traverse = list; - int counter = 0; - while ( traverse != NULL ) - { - counter++; - traverse = traverse->next; - } - return counter; -} - -static void free_best_buffer_list( ) -{ - t_linked_int* traverse = main_best_buffer_list; - t_linked_int* current; - while ( traverse != NULL ) - { - current = traverse; - traverse = current->next; - free( current ); - } - main_best_buffer_list = NULL; -} - -static void save_best_buffer_list( t_linked_int* best_list ) -{ - t_linked_int* current; - t_linked_int* traverse = best_list; - while ( traverse != NULL ) - { - current = ( t_linked_int* ) my_malloc( sizeof( t_linked_int ) ); - current->data = traverse->data; - current->next = main_best_buffer_list; - main_best_buffer_list = current; - traverse = traverse->next; - } -} - -void load_best_buffer_list( ) -{ - t_linked_int* traverse = main_best_buffer_list; - clear_buffer( ); - while ( traverse != NULL ) - { - rr_node[ traverse->data ].buffered = 1; - traverse = traverse->next; - } -} - -int print_stat_memristor_buffer( char* fname, float buffer_size ) -{ - char fnamex[100]; - char fnamey[100]; - FILE* fpx; - FILE* fpy; - int** freqx; - int** freqy; - int counter; - int i, j; - t_linked_int* traverse; - int max_number; - sprintf( fnamex, "x_%s", fname ); - sprintf( fnamey, "y_%s", fname ); - fpx = my_fopen( fnamex, "w" ,0); - fpy = my_fopen( fnamey, "w" ,0); - freqx = (int**) alloc_matrix( 1, nx, 0, ny, sizeof(int) ); - freqy = (int**) alloc_matrix( 0, nx, 1, ny, sizeof(int) ); - counter = 0; - for( i = 1; i <= nx; i++ ) - { - for( j = 0; j <= ny; j++ ) - { - freqx[i][j]=0; - } - } - for( i = 0; i <= nx; i++ ) - { - for( j = 1; j <= ny; j++ ) - { - freqy[i][j]=0; - } - } - traverse = main_best_buffer_list; - while ( traverse != NULL ) - { - counter++; - if ( rr_node[traverse->data].type == CHANX ) - { - freqx[rr_node[traverse->data].xlow][( rr_node[traverse->data].ylow + rr_node[traverse->data].yhigh ) / 2]++; - } - else if ( rr_node[traverse->data].type == CHANY ) - { - freqy[(rr_node[traverse->data].xlow+rr_node[traverse->data].xhigh)/2][rr_node[traverse->data].ylow]++; - } - traverse = traverse->next; - } - max_number = 0; - for( i = 1; i <= nx; i++ ) - { - for( j = 0; j <= ny; j++ ) - { - max_number = max( max_number, freqx[i][j] ); - fprintf( fpx, "%d ", freqx[i][j] ); - } - fprintf( fpx, "\n" ); - } - for( i = 0; i <= nx; i++ ) - { - for( j = 1; j <= ny; j++ ) - { - max_number = max( max_number, freqy[i][j] ); - fprintf( fpy, "%d ", freqy[i][j] ); - } - fprintf( fpy, "\n" ); - } - free_matrix( freqx, 1, nx, 0, sizeof(int) ); - free_matrix( freqy, 0, nx, 1, sizeof(int) ); - fclose( fpx ); - fclose( fpy ); - printf( "%d buffers ( size: %g ) inserted, total active trans: %g\n", counter, buffer_size, counter*buffer_size ); - printf( "maximum # of buffers in one channel: %d\n", max_number ); - return max_number; -} - -void clear_buffer( ) -{ - int i; - for( i = 0; i < num_rr_nodes; i++ ) - { - rr_node[ i ].buffered = 0; - } -} - -static t_buffer_plan_list try_buffer_rc_tree (t_rc_node *rc_node, int num_pins, int* isink_to_inode) { - t_linked_rc_edge *linked_rc_edge; - t_rc_node *child_node; - short iswitch; - int inode; - int num_whole; - int i; - t_rr_node rrnode; - t_buffer_plan_list result; - t_buffer_plan_list* plan_list_from_branch; - - inode = rc_node->inode; - rrnode = rr_node[ inode ]; - - if ( rrnode.type == SINK ) - { - result = get_init_buffer_plan_list( inode, num_pins, isink_to_inode ); - } - else - { - result = get_empty_buffer_plan_list( ); - num_whole = 0; - linked_rc_edge = rc_node->u.child_list; - while (linked_rc_edge != NULL) { /* For all children */ - num_whole++; - linked_rc_edge = linked_rc_edge->next; - } - plan_list_from_branch = ( t_buffer_plan_list* )my_malloc( num_whole*sizeof(t_buffer_plan_list) ); - - i = 0; - linked_rc_edge = rc_node->u.child_list; - while (linked_rc_edge != NULL) { /* For all children */ - iswitch = linked_rc_edge->iswitch; - child_node = linked_rc_edge->child; - plan_list_from_branch[i] = try_buffer_rc_tree( child_node, num_pins, isink_to_inode ); - insert_switch_to_buffer_list( plan_list_from_branch[i], switch_inf[ iswitch ] ); - linked_rc_edge = linked_rc_edge->next; - i++; - } - if ( num_whole > 1 ) - { - for( i = 0; i < num_whole; i++ ) - { - result = join_left_plan_list_into_whole( plan_list_from_branch[ i ], plan_list_from_branch, num_whole, result, num_pins ); - } - for( i = 0; i < num_whole; i++ ) - { - free_buffer_list( plan_list_from_branch[ i ] ); - } - } - else - { - result = plan_list_from_branch[ 0 ]; - } - free( plan_list_from_branch ); - insert_wire_to_buffer_list( result, rrnode.C, 0.5 * rrnode.R ); - if (rr_node[ inode ].type == CHANX || rr_node[ inode ].type == CHANY) - { - result = insert_buffer( result, inode, wire_buffer_inf.C, wire_buffer_inf.R, wire_buffer_inf.Tdel, num_pins ); - } - } - return result; -} - -static t_buffer_plan_list get_empty_buffer_plan_list( ) -{ - t_buffer_plan_list list; - list.front = NULL; - return list; -} - -static t_buffer_plan get_init_buffer_plan( int inode, int num_pins, int* isink_to_inode ) -{ - t_buffer_plan plan; - int i; - plan.inode_head = NULL; - plan.sink_head = (t_linked_int*) my_malloc( sizeof( t_linked_int ) ); - plan.sink_head->next = 0; - plan.sink_delay = (float*) my_malloc( sizeof(float) * num_pins ); - for( i = 1; i < num_pins; i++ ) - { - if( isink_to_inode[ i ] == inode ) - { - plan.sink_head->data = i; - } - plan.sink_delay[i] = 0; - } - plan.C_downstream = 0.; - plan.Tdel = 0.; - return plan; -} - -static t_buffer_plan_list get_init_buffer_plan_list( int inode, int num_pins, int* isink_to_inode ) -{ - t_buffer_plan_list list; - list.front = ( t_buffer_plan_node* ) my_malloc( sizeof( t_buffer_plan_node ) ); - list.front->value = get_init_buffer_plan( inode, num_pins, isink_to_inode ); - list.front->next = NULL; - return list; -} - -static t_buffer_plan_list join_left_plan_list_into_whole( t_buffer_plan_list left, t_buffer_plan_list* whole, int num_whole, t_buffer_plan_list current, int num_pins ) -{ - int i; - t_buffer_plan_node* left_traverse; - t_buffer_plan_node* whole_traverse; - t_buffer_plan* best_plans = (t_buffer_plan*) my_malloc(num_whole*sizeof(t_buffer_plan)); - left_traverse = left.front; - while( left_traverse != NULL ) - { - for( i=0; i< num_whole; i++ ) - { - best_plans[i].C_downstream = HUGE_VAL; - if ( left.front == whole[ i ].front ) - { - continue; - } - whole_traverse = whole[i].front; - while ( whole_traverse != NULL ) - { - if ( whole_traverse->value.Tdel <= left_traverse->value.Tdel - && whole_traverse->value.C_downstream < best_plans[i].C_downstream ) - { - best_plans[i] = whole_traverse->value; - } - whole_traverse = whole_traverse->next; - } - if ( best_plans[i].C_downstream == HUGE_VAL ) - { - break; - } - } - if ( i == num_whole ) - { - current = insert_buffer_plan_to_list( combine_buffer_plan( left_traverse->value, best_plans, num_whole, num_pins ), current ); - } - left_traverse = left_traverse->next; - } - free( best_plans ); - return current; -} - -static t_buffer_plan combine_buffer_plan( t_buffer_plan slow_branch, t_buffer_plan* plan_whole, int num_whole, int num_pins ) -{ - int i; - t_buffer_plan new_plan = slow_branch; - new_plan.inode_head = NULL; - new_plan.sink_head = NULL; - new_plan.sink_delay = (float*) my_malloc( sizeof(float) * num_pins ); - new_plan.inode_head = copy_from_list( new_plan.inode_head, slow_branch.inode_head ); - new_plan.sink_head = copy_from_list( new_plan.sink_head, slow_branch.sink_head ); - copy_delay( new_plan.sink_delay, slow_branch.sink_delay, slow_branch.sink_head ); - for( i = 0; i < num_whole; i++ ) - { - if ( plan_whole[ i ].C_downstream == HUGE_VAL ) - { - continue; - } - new_plan.C_downstream += plan_whole[i].C_downstream; - new_plan.inode_head = copy_from_list( new_plan.inode_head, plan_whole[i].inode_head ); - new_plan.sink_head = copy_from_list( new_plan.sink_head, plan_whole[i].sink_head ); - copy_delay( new_plan.sink_delay, plan_whole[i].sink_delay, plan_whole[i].sink_head ); - } - return new_plan; -} - -static void copy_delay( float* base, float* source, t_linked_int* index ) -{ - t_linked_int* traverse = index; - while( traverse != NULL ) - { - base[traverse->data] = source[traverse->data]; - traverse = traverse->next; - } -} - -static void free_buffer_list( t_buffer_plan_list list ) -{ - t_buffer_plan_node* traverse = list.front; - t_buffer_plan_node* temp; - while( traverse != NULL ) - { - free_int_list( &( traverse->value.inode_head ) ); - free_int_list( &( traverse->value.sink_head ) ); - free( traverse->value.sink_delay ); - temp = traverse->next; - free( traverse ); - traverse = temp; - } -} - -static t_buffer_plan_list insert_buffer( t_buffer_plan_list list, int inode, float C, float R, float Tdel, int num_pins ) -{ - t_buffer_plan best; - //int i; - float Tdel_temp; - float delay_addition; - float Tdel_best = HUGE_VAL; - t_buffer_plan_node* traverse = list.front; - while ( traverse != NULL ) - { - Tdel_temp = traverse->value.Tdel + traverse->value.C_downstream * R; - if ( Tdel_temp < Tdel_best ) - { - Tdel_best = Tdel_temp; - best = traverse->value; - } - traverse = traverse->next; - } - best.inode_head = copy_from_list( NULL, best.inode_head ); - best.inode_head = insert_in_int_list2( best.inode_head, inode ); - best.sink_head = copy_from_list( NULL, best.sink_head ); - best.sink_delay = copy_from_float_array( best.sink_delay, num_pins ); - best.C_downstream = C; - delay_addition = Tdel_best + Tdel - best.Tdel; - add_delay_to_array( best.sink_delay, best.sink_head, delay_addition ); - best.Tdel += delay_addition; - return insert_buffer_plan_to_list( best, list ); -} - -static float* copy_from_float_array( float* source, int num ) -{ - int i; - float* result = (float*)my_malloc( sizeof(float) * num ); - for( i = 0; i < num; i++ ) - { - result[i] = source[i]; - } - return result; -} - -static t_buffer_plan insert_wire_to_buffer_plan( t_buffer_plan plan, float C, float R ) -{ - float delay_addition; - plan.C_downstream += C; - delay_addition = R * plan.C_downstream; - add_delay_to_array( plan.sink_delay, plan.sink_head, delay_addition ); - plan.Tdel += delay_addition; - return plan; -} - -static void add_delay_to_array( float* sink_delay, t_linked_int* index, float delay_addition ) -{ - t_linked_int* traverse = index; - while( traverse != NULL ) - { - sink_delay[traverse->data] += delay_addition; - traverse = traverse->next; - } -} - -static t_buffer_plan insert_switch_to_buffer_plan( t_buffer_plan plan, struct s_switch_inf switch_inf_local) -{ - float delay_addition; - delay_addition = switch_inf_local.R * plan.C_downstream + switch_inf_local.Tdel; - add_delay_to_array( plan.sink_delay, plan.sink_head, delay_addition ); - plan.Tdel += delay_addition; - if ( switch_inf_local.buffered ) - { - plan.C_downstream = switch_inf_local.Cin; - } - else - { - plan.C_downstream += switch_inf_local.Cout + switch_inf_local.Cin; - } - return plan; -} - -static void insert_switch_to_buffer_list( t_buffer_plan_list list, struct s_switch_inf switch_inf_local) -{ - t_buffer_plan_node* traverse = list.front; - while ( traverse != NULL ) - { - traverse->value = insert_switch_to_buffer_plan( traverse->value, switch_inf_local); - traverse = traverse->next; - } -} - -static void insert_wire_to_buffer_list( t_buffer_plan_list list, float C,float R ) -{ - t_buffer_plan_node* traverse = list.front; - while ( traverse != NULL ) - { - traverse->value = insert_wire_to_buffer_plan( traverse->value, C, R ); - traverse = traverse->next; - } -} - -static t_buffer_plan_list insert_buffer_plan_to_list( t_buffer_plan plan, t_buffer_plan_list list ) { - /* original name : new is a resevered word in C++!!! */ - t_buffer_plan_node* new_buffer_plan_node = ( t_buffer_plan_node* )my_malloc( sizeof( t_buffer_plan_node ) ); - new_buffer_plan_node->value = plan; - new_buffer_plan_node->next = list.front; - list.front = new_buffer_plan_node; - return list; -} - -void count_routing_memristor_buffer( int num_per_channel, float buffer_size ) -{ - float total_area = num_per_channel*((1+nx)*ny+(1+ny)*nx)*buffer_size; - printf("\nRouting area due to inserted buffers: Total: %g Per clb: %g\n", total_area, total_area / nx / ny ); - printf("tile area: %#g\n", total_area / nx / ny + grid_logic_tile_area ); -} - -/* memristor end */ - diff --git a/vpr7_x2p/vpr/SRC/mrfpga/buffer_insertion.h b/vpr7_x2p/vpr/SRC/mrfpga/buffer_insertion.h deleted file mode 100644 index 887cabc96..000000000 --- a/vpr7_x2p/vpr/SRC/mrfpga/buffer_insertion.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef BUFFER_INSERTION_H -#define BUFFER_INSERTION_H - -void try_buffer_for_routing ( float** net_delay ); -void load_best_buffer_list( ); -int print_stat_memristor_buffer( char* fname, float buffer_size ); -void clear_buffer( ); -void count_routing_memristor_buffer( int num_per_channel, float buffer_size ); - -#endif diff --git a/vpr7_x2p/vpr/SRC/mrfpga/cal_capacitance.c b/vpr7_x2p/vpr/SRC/mrfpga/cal_capacitance.c deleted file mode 100644 index 1842383e2..000000000 --- a/vpr7_x2p/vpr/SRC/mrfpga/cal_capacitance.c +++ /dev/null @@ -1,83 +0,0 @@ -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "cal_capacitance.h" -/* Xifan TANG */ -#include "mrfpga_globals.h" -#include "net_delay_types.h" -#include "net_delay_local_void.h" -/* end */ - -static float load_rc_tree_Ctotal (t_rc_node *rc_node); - -void cal_capacitance_from_routing ( ) { - - t_rc_node *rc_node_free_list, *rc_root; - t_linked_rc_edge *rc_edge_free_list; - int inet; - t_linked_rc_ptr *rr_node_to_rc_node; /* [0..num_rr_nodes-1] */ - - float total_capacitance = 0; - - rc_node_free_list = NULL; - rc_edge_free_list = NULL; - - rr_node_to_rc_node = (t_linked_rc_ptr *) my_calloc (num_rr_nodes, - sizeof (t_linked_rc_ptr)); - - for (inet=0;inetu.child_list; - inode = rc_node->inode; - C = rr_node[inode].C; - - if( rr_node[inode].buffered ) - { - C += wire_buffer_inf.C * 3.0; - } - - while (linked_rc_edge != NULL) { /* For all children */ - iswitch = linked_rc_edge->iswitch; - child_node = linked_rc_edge->child; - C += load_rc_tree_Ctotal (child_node); - - if ( is_mrFPGA ) - { - C += switch_inf[iswitch].Cin; - C += switch_inf[iswitch].Cout; - } - else if ( switch_inf[iswitch].buffered ) - { - C += switch_inf[iswitch].Cin * 2.0; - C += switch_inf[iswitch].Cout * 2.0; - } - linked_rc_edge = linked_rc_edge->next; - } - return (C); -} - diff --git a/vpr7_x2p/vpr/SRC/mrfpga/cal_capacitance.h b/vpr7_x2p/vpr/SRC/mrfpga/cal_capacitance.h deleted file mode 100644 index d79864a38..000000000 --- a/vpr7_x2p/vpr/SRC/mrfpga/cal_capacitance.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef CAL_CAPACITANCE_H -#define CAL_CAPACITANCE_H - -void cal_capacitance_from_routing ( ); - -#endif diff --git a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_api.c b/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_api.c deleted file mode 100644 index 9d46026fb..000000000 --- a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_api.c +++ /dev/null @@ -1,142 +0,0 @@ -#include -#include -#include -#include - -/* libarchfpga data structures*/ -#include "util.h" -#include "physical_types.h" -/* END */ - -/* VPR data structures*/ -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -/* END */ - -/* mrFPGA: Xifan TANG*/ -#include "mrfpga_globals.h" -#include "mrfpga_util.h" -#include "buffer_insertion.h" -#include "cal_capacitance.h" -#include "mrfpga_api.h" - -/***** Subroutines *****/ -/* Copy the contents in arch_mrfpga to globals*/ -void sync_arch_mrfpga_globals(t_arch_mrfpga arch_mrfpga) { - /* Booleans */ - is_isolation = arch_mrfpga.is_isolation; - is_stack = arch_mrfpga.is_stack; - is_junction = arch_mrfpga.is_junction; - is_wire_buffer = arch_mrfpga.is_wire_buffer; - is_mrFPGA = arch_mrfpga.is_mrFPGA; - - /* Copy some struct*/ - wire_buffer_inf = arch_mrfpga.wire_buffer_inf; - memristor_inf = arch_mrfpga.memristor_inf; - max_pins_per_side = arch_mrfpga.max_pins_per_side; - main_best_buffer_list = arch_mrfpga.main_best_buffer_list; - num_normal_switch = arch_mrfpga.num_normal_switch; - start_seg_switch = arch_mrfpga.start_seg_switch; - - /* SRAM and Pass Transistor Usage*/ - is_show_sram = arch_mrfpga.is_show_sram; - is_show_pass_trans = arch_mrfpga.is_show_pass_trans; - Rseg_global = arch_mrfpga.Rseg_global; - Cseg_global = arch_mrfpga.Cseg_global; - - return; -} - -/* Get the switch type for mrFPGA: Xifan TANG - * This function is called rr_graph2.c but I move it here - * so that it is easy to see mrFPGA modifications - */ -void get_mrfpga_switch_type(boolean is_from_sbox, - boolean is_to_sbox, - short from_node_switch, - short to_node_switch, - short switch_types[2]) { - /* This routine looks at whether the from_node and to_node want a switch, * - * and what type of switch is used to connect *to* each type of node * - * (from_node_switch and to_node_switch). It decides what type of switch, * - * if any, should be used to go from from_node to to_node. If no switch * - * should be inserted (i.e. no connection), it returns OPEN. Its returned * - * values are in the switch_types array. It needs to return an array * - * because one topology (a buffer in the forward direction and a pass * - * transistor in the backward direction) results in *two* switches. */ - - /* modified by bjxiao to make the pass transistors accepted */ - /* the original version has bugs */ - /* this version is copied from VPR4.3 */ - switch_types[0] = OPEN; /* No switch */ - switch_types[1] = OPEN; - - if (!is_from_sbox && !is_to_sbox) { /* No connection wanted in either dir */ - switch_types[0] = OPEN; - } - - else if (is_from_sbox && !is_to_sbox) { /* Only forward connection wanted */ - switch_types[0] = to_node_switch; /* Type of switch to go *to* to_node */ - } - - else if (!is_from_sbox && is_to_sbox) { - - /* Only backward connection desired. We're deciding whether or not to put * - * in the forward connection. Put it in if the backward connection uses * - * a bidirectional (pass transistor) switch. Remember that the backward * - * connection uses a from_node_switch type of switch. */ - - if ( switch_inf[from_node_switch].buffered == FALSE) { - switch_types[0] = from_node_switch; - } - } else { - /* Both a forward and a backward connection desired. If the switch types * - * desired for the two connection are different, we have to reconcile them. */ - - if (from_node_switch == to_node_switch) { - switch_types[0] = to_node_switch; - } else { /* Different switch types. Reconcile. */ - if (switch_inf[to_node_switch].buffered) { - switch_types[0] = to_node_switch; - if ( switch_inf[from_node_switch].buffered == FALSE) { - /* Buffer in forward direction, pass transistor in backward. Put * - * in *two* edges. */ - switch_types[1] = from_node_switch; - } - } else { /* Forward connection is a pass transistor. */ - if (switch_inf[from_node_switch].buffered) { - switch_types[0] = to_node_switch; - } else { - - /* Both forward and backward connections use pass transistors. * - * use whichever one is larger, since you'll only physically * - * build one switch. */ - - if (switch_inf[to_node_switch].R < - switch_inf[from_node_switch].R) { - switch_types[0] = to_node_switch; - } else if (switch_inf[from_node_switch].R < - switch_inf[to_node_switch].R) { - switch_types[0] = from_node_switch; - } else { - - /* Two pass transistors have the same R, but are have different * - * switch indices. Use the one with lower index (arbitrarily), * - * to ensure both switches are of the same type (since you can * - * only physically build one). I'm being pretty dogmatic here. */ - - if (to_node_switch < from_node_switch) { - switch_types[0] = to_node_switch; - } else { - switch_types[0] = from_node_switch; - } - } - } - } - } /* End switch types are different */ - } /* End both forward and backward connection desired. */ - /* end */ -} - diff --git a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_api.h b/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_api.h deleted file mode 100644 index 0cf0139f8..000000000 --- a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_api.h +++ /dev/null @@ -1,8 +0,0 @@ - -void sync_arch_mrfpga_globals(t_arch_mrfpga arch_mrfpga); - -void get_mrfpga_switch_type(boolean is_from_sbox, - boolean is_to_sbox, - short from_node_switch, - short to_node_switch, - short switch_types[2]); diff --git a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_globals.c b/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_globals.c deleted file mode 100644 index be0a87b03..000000000 --- a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_globals.c +++ /dev/null @@ -1,27 +0,0 @@ -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" - -/* mrFPGA specfications */ -boolean is_isolation = FALSE; -boolean is_stack = FALSE; -boolean is_junction = FALSE; -boolean is_wire_buffer = FALSE; -boolean is_mrFPGA = FALSE; -t_buffer_inf wire_buffer_inf; -t_memristor_inf memristor_inf; -int max_pins_per_side; -t_linked_int* main_best_buffer_list; -short num_normal_switch; -short start_seg_switch; -/* end */ - -/* bjxiao: show sram and pass transistor usage */ -boolean is_show_sram = FALSE, is_show_pass_trans = FALSE; -float Rseg_global, Cseg_global; -float rram_pass_tran_value = 0; -/* end */ - diff --git a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_globals.h b/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_globals.h deleted file mode 100644 index df217944d..000000000 --- a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_globals.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef MRFPGA_H -#define MRFPGA_H - -/* mrFPGA specfications */ -extern boolean is_isolation; -extern boolean is_stack; -extern boolean is_junction; -extern boolean is_wire_buffer; -extern boolean is_mrFPGA; -//extern boolean is_accurate; /* Xifan TANG: Abolish */ -extern t_buffer_inf wire_buffer_inf; -extern t_memristor_inf memristor_inf; -extern int max_pins_per_side; -extern t_linked_int* main_best_buffer_list; -extern short num_normal_switch; -extern short start_seg_switch; -/* end */ - -/* bjxiao: show sram and pass transistor usage */ -extern boolean is_show_sram, is_show_pass_trans; -//extern enum e_tech_comp tech_comp; /* Xifan TANG : abolish */ -extern float Rseg_global, Cseg_global; -extern float rram_pass_tran_value; -/* end */ - -#endif diff --git a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_util.c b/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_util.c deleted file mode 100644 index 74a3f6709..000000000 --- a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_util.c +++ /dev/null @@ -1,27 +0,0 @@ -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "mrfpga_util.h" - -/* mrFPGA */ -t_linked_int* insert_in_int_list2 (t_linked_int *head, int data ) -{ - t_linked_int *linked_int; - linked_int = (t_linked_int *) my_malloc (sizeof (t_linked_int)); - linked_int->data = data; - linked_int->next = head; - return (linked_int); -} - -t_linked_int* copy_from_list( t_linked_int* base, t_linked_int* target ) -{ - while ( target != NULL ) - { - base = insert_in_int_list2( base, target->data ); - target = target->next; - } - return base; -} - -/* end */ diff --git a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_util.h b/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_util.h deleted file mode 100644 index d0970629b..000000000 --- a/vpr7_x2p/vpr/SRC/mrfpga/mrfpga_util.h +++ /dev/null @@ -1,15 +0,0 @@ -/* Xifan TANG : - * Create a local copy of max and min exclusively for mrFPGA - */ - -#ifndef max -#define max(a,b) (((a) > (b))? (a) : (b)) -#endif - -#ifndef min -#define min(a,b) (((a) > (b))? (b) : (a)) -#endif - -t_linked_int* copy_from_list(t_linked_int* base, t_linked_int* target); - -t_linked_int* insert_in_int_list2(t_linked_int *head, int data); diff --git a/vpr7_x2p/vpr/SRC/pack/cluster.c b/vpr7_x2p/vpr/SRC/pack/cluster.c deleted file mode 100755 index 8517568cc..000000000 --- a/vpr7_x2p/vpr/SRC/pack/cluster.c +++ /dev/null @@ -1,2885 +0,0 @@ -/* - * Main clustering algorithm - * Author(s): Vaughn Betz (first revision - VPack), Alexander Marquardt (second revision - T-VPack), Jason Luu (third revision - AAPack) - * June 8, 2011 - */ - -#include -#include -#include -#include -#include -#include - -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "cluster.h" -#include "heapsort.h" -#include "output_clustering.h" -#include "output_blif.h" -#include "SetupGrid.h" -#include "read_xml_arch_file.h" -#include "cluster_legality.h" -#include "path_delay2.h" -#include "path_delay.h" -#include "vpr_utils.h" -#include "cluster_placement.h" -#include "ReadOptions.h" - -/*#define DEBUG_FAILED_PACKING_CANDIDATES*/ - -#define AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC 2 /* Maximum relative number of pins that can exceed input pins before giving up */ -#define AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST 5 /* Maximum constant number of pins that can exceed input pins before giving up */ - -#define AAPACK_MAX_FEASIBLE_BLOCK_ARRAY_SIZE 30 /* This value is used to determine the max size of the priority queue for candidates that pass the early filter legality test but not the more detailed routing test */ -#define AAPACK_MAX_NET_SINKS_IGNORE 256 /* The packer looks at all sinks of a net when deciding what next candidate block to pack, for high-fanout nets, this is too runtime costly for marginal benefit, thus ignore those high fanout nets */ -#define AAPACK_MAX_HIGH_FANOUT_EXPLORE 10 /* For high-fanout nets that are ignored, consider a maximum of this many nets */ - -#define SCALE_NUM_PATHS 1e-2 /*this value is used as a multiplier to assign a * - *slightly higher criticality value to nets that * - *affect a large number of critical paths versus * - *nets that do not have such a broad effect. * - *Note that this multiplier is intentionally very * - *small compared to the total criticality because * - *we want to make sure that vpack_net criticality is * - *primarily determined by slacks, with this acting * - *only as a tie-breaker between otherwise equal nets*/ -#define SCALE_DISTANCE_VAL 1e-4 /*this value is used as a multiplier to assign a * - *slightly higher criticality value to nets that * - *are otherwise equal but one is farther * - *from sources (the farther one being made slightly * - *more critical) */ - -enum e_gain_update { - GAIN, NO_GAIN -}; -enum e_feasibility { - FEASIBLE, INFEASIBLE -}; -enum e_gain_type { - HILL_CLIMBING, NOT_HILL_CLIMBING -}; -enum e_removal_policy { - REMOVE_CLUSTERED, LEAVE_CLUSTERED -}; -/* TODO: REMOVE_CLUSTERED no longer used, remove */ -enum e_net_relation_to_clustered_block { - INPUT, OUTPUT -}; - -enum e_detailed_routing_stages { - E_DETAILED_ROUTE_AT_END_ONLY = 0, E_DETAILED_ROUTE_FOR_EACH_ATOM, E_DETAILED_ROUTE_END -}; - - -/* Linked list structure. Stores one integer (iblk). */ -struct s_molecule_link { - t_pack_molecule *moleculeptr; - struct s_molecule_link *next; -}; - -/* 1/MARKED_FRAC is the fraction of nets or blocks that must be * - * marked in order for the brute force (go through the whole * - * data structure linearly) gain update etc. code to be used. * - * This is done for speed only; make MARKED_FRAC whatever * - * number speeds the code up most. */ -#define MARKED_FRAC 2 - -/* Keeps a linked list of the unclustered blocks to speed up looking for * - * unclustered blocks with a certain number of *external* inputs. * - * [0..lut_size]. Unclustered_list_head[i] points to the head of the * - * list of blocks with i inputs to be hooked up via external interconnect. */ -static struct s_molecule_link *unclustered_list_head; -int unclustered_list_head_size; -static struct s_molecule_link *memory_pool; /*Declared here so I can free easily.*/ - -/* Does the logical_block that drives the output of this vpack_net also appear as a * - * receiver (input) pin of the vpack_net? [0..num_logical_nets-1]. If so, then by how much? This is used * - * in the gain routines to avoid double counting the connections from * - * the current cluster to other blocks (hence yielding better * - * clusterings). The only time a logical_block should connect to the same vpack_net * - * twice is when one connection is an output and the other is an input, * - * so this should take care of all multiple connections. */ -static int *net_output_feeds_driving_block_input; - -/* Timing information for blocks */ - -static float *block_criticality = NULL; -static int *critindexarray = NULL; - -/*****************************************/ -/*local functions*/ -/*****************************************/ - -static void check_clocks(boolean *is_clock); - -#if 0 -static void check_for_duplicate_inputs (); -#endif - -static boolean is_logical_blk_in_pb(int iblk, t_pb *pb); - -static void add_molecule_to_pb_stats_candidates(t_pack_molecule *molecule, - std::map &gain, t_pb *pb); - -static void alloc_and_init_clustering(boolean global_clocks, float alpha, - float beta, int max_cluster_size, int max_molecule_inputs, - int max_pb_depth, int max_models, - t_cluster_placement_stats **cluster_placement_stats, - t_pb_graph_node ***primitives_list, t_pack_molecule *molecules_head, - int num_molecules); -static void free_pb_stats_recursive(t_pb *pb); -static void try_update_lookahead_pins_used(t_pb *cur_pb); -static void reset_lookahead_pins_used(t_pb *cur_pb); -static void compute_and_mark_lookahead_pins_used(int ilogical_block); -static void compute_and_mark_lookahead_pins_used_for_pin( - t_pb_graph_pin *pb_graph_pin, t_pb *primitive_pb, int inet); -static void commit_lookahead_pins_used(t_pb *cur_pb); -static boolean check_lookahead_pins_used(t_pb *cur_pb); -static boolean primitive_feasible(int iblk, t_pb *cur_pb); -static boolean primitive_type_and_memory_feasible(int iblk, - const t_pb_type *cur_pb_type, t_pb *memory_class_pb, - int sibling_memory_blk); - -static t_pack_molecule *get_molecule_by_num_ext_inputs( - INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, - INP int ext_inps, INP enum e_removal_policy remove_flag, - INP t_cluster_placement_stats *cluster_placement_stats_ptr); - -static t_pack_molecule* get_free_molecule_with_most_ext_inputs_for_cluster( - INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, - INP t_cluster_placement_stats *cluster_placement_stats_ptr); - -static t_pack_molecule* get_seed_logical_molecule_with_most_ext_inputs( - int max_molecule_inputs); - -static enum e_block_pack_status try_pack_molecule( - INOUTP t_cluster_placement_stats *cluster_placement_stats_ptr, - INP t_pack_molecule *molecule, INOUTP t_pb_graph_node **primitives_list, - INOUTP t_pb * pb, INP int max_models, INP int max_cluster_size, - INP int clb_index, INP int max_nets_in_pb_type, INP int detailed_routing_stage); -static enum e_block_pack_status try_place_logical_block_rec( - INP t_pb_graph_node *pb_graph_node, INP int ilogical_block, - INP t_pb *cb, OUTP t_pb **parent, INP int max_models, - INP int max_cluster_size, INP int clb_index, - INP int max_nets_in_pb_type, - INP t_cluster_placement_stats *cluster_placement_stats_ptr, - INP boolean is_root_of_chain, INP t_pb_graph_pin *chain_root_pin); -static void revert_place_logical_block(INP int ilogical_block, - INP int max_models); - -static void update_connection_gain_values(int inet, int clustered_block, - t_pb * cur_pb, - enum e_net_relation_to_clustered_block net_relation_to_clustered_block); - -static void update_timing_gain_values(int inet, int clustered_block, - t_pb* cur_pb, - enum e_net_relation_to_clustered_block net_relation_to_clustered_block, - t_slack * slacks); - -static void mark_and_update_partial_gain(int inet, enum e_gain_update gain_flag, - int clustered_block, int port_on_clustered_block, - int pin_on_clustered_block, boolean timing_driven, - boolean connection_driven, - enum e_net_relation_to_clustered_block net_relation_to_clustered_block, - t_slack * slacks); - -static void update_total_gain(float alpha, float beta, boolean timing_driven, - boolean connection_driven, boolean global_clocks, t_pb *pb); - -static void update_cluster_stats( INP t_pack_molecule *molecule, - INP int clb_index, INP boolean *is_clock, INP boolean global_clocks, - INP float alpha, INP float beta, INP boolean timing_driven, - INP boolean connection_driven, INP t_slack * slacks); - -static void start_new_cluster( - INP t_cluster_placement_stats *cluster_placement_stats, - INP t_pb_graph_node **primitives_list, INP const t_arch * arch, - INOUTP t_block *new_cluster, INP int clb_index, - INP t_pack_molecule *molecule, INP float aspect, - INOUTP int *num_used_instances_type, INOUTP int *num_instances_type, - INP int num_models, INP int max_cluster_size, - INP int max_nets_in_pb_type, INP int detailed_routing_stage); - -static t_pack_molecule* get_highest_gain_molecule( - INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, - INP enum e_gain_type gain_mode, - INP t_cluster_placement_stats *cluster_placement_stats_ptr); - -static t_pack_molecule* get_molecule_for_cluster( - INP enum e_packer_algorithm packer_algorithm, INP t_pb *cur_pb, - INP boolean allow_unrelated_clustering, - INOUTP int *num_unrelated_clustering_attempts, - INP t_cluster_placement_stats *cluster_placement_stats_ptr); - -static void alloc_and_load_cluster_info(INP int num_clb, INOUTP t_block *clb); - -static void check_clustering(int num_clb, t_block *clb, boolean *is_clock); - -static void check_cluster_logical_blocks(t_pb *pb, boolean *blocks_checked); - -static t_pack_molecule* get_most_critical_seed_molecule(int * indexofcrit); - -static float get_molecule_gain(t_pack_molecule *molecule, std::map &blk_gain); -static int compare_molecule_gain(const void *a, const void *b); -static int get_net_corresponding_to_pb_graph_pin(t_pb *cur_pb, - t_pb_graph_pin *pb_graph_pin); - -static void print_block_criticalities(const char * fname); - -/*****************************************/ -/*globally accessable function*/ -void do_clustering(const t_arch *arch, t_pack_molecule *molecule_head, - int num_models, boolean global_clocks, boolean *is_clock, - boolean hill_climbing_flag, char *out_fname, boolean timing_driven, - enum e_cluster_seed cluster_seed_type, float alpha, float beta, - int recompute_timing_after, float block_delay, - float intra_cluster_net_delay, float inter_cluster_net_delay, - float aspect, boolean allow_unrelated_clustering, - boolean allow_early_exit, boolean connection_driven, - enum e_packer_algorithm packer_algorithm, t_timing_inf timing_inf) { - - /* Does the actual work of clustering multiple netlist blocks * - * into clusters. */ - - /* Algorithm employed - 1. Find type that can legally hold block and create cluster with pb info - 2. Populate started cluster - 3. Repeat 1 until no more blocks need to be clustered - - */ - - int i, iblk, num_molecules, blocks_since_last_analysis, num_clb, max_nets_in_pb_type, - cur_nets_in_pb_type, num_blocks_hill_added, max_cluster_size, cur_cluster_size, - max_molecule_inputs, max_pb_depth, cur_pb_depth, num_unrelated_clustering_attempts, - indexofcrit, savedindexofcrit /* index of next most timing critical block */, - detailed_routing_stage, *hill_climbing_inputs_avail; - - int *num_used_instances_type, *num_instances_type; - /* [0..num_types] Holds array for total number of each cluster_type available */ - - boolean early_exit, is_cluster_legal; - enum e_block_pack_status block_pack_status; - float crit; - - t_cluster_placement_stats *cluster_placement_stats, *cur_cluster_placement_stats_ptr; - t_pb_graph_node **primitives_list; - t_block *clb; - t_slack * slacks = NULL; - t_pack_molecule *istart, *next_molecule, *prev_molecule, *cur_molecule; - -#ifdef PATH_COUNTING - int inet, ipin; -#else - int inode; - float num_paths_scaling, distance_scaling; -#endif - - /* TODO: This is memory inefficient, fix if causes problems */ - clb = (t_block*)my_calloc(num_logical_blocks, sizeof(t_block)); - num_clb = 0; - istart = NULL; - - /* determine bound on cluster size and primitive input size */ - max_cluster_size = 0; - max_molecule_inputs = 0; - max_pb_depth = 0; - max_nets_in_pb_type = 0; - - indexofcrit = 0; - - cur_molecule = molecule_head; - num_molecules = 0; - while (cur_molecule != NULL) { - cur_molecule->valid = TRUE; - if (cur_molecule->num_ext_inputs > max_molecule_inputs) { - max_molecule_inputs = cur_molecule->num_ext_inputs; - } - num_molecules++; - cur_molecule = cur_molecule->next; - } - - for (i = 0; i < num_types; i++) { - if (EMPTY_TYPE == &type_descriptors[i]) - continue; - cur_cluster_size = get_max_primitives_in_pb_type( - type_descriptors[i].pb_type); - cur_pb_depth = get_max_depth_of_pb_type(type_descriptors[i].pb_type); - cur_nets_in_pb_type = get_max_nets_in_pb_type( - type_descriptors[i].pb_type); - if (cur_cluster_size > max_cluster_size) { - max_cluster_size = cur_cluster_size; - } - if (cur_pb_depth > max_pb_depth) { - max_pb_depth = cur_pb_depth; - } - if (cur_nets_in_pb_type > max_nets_in_pb_type) { - max_nets_in_pb_type = cur_nets_in_pb_type; - } - } - - if (hill_climbing_flag) { - hill_climbing_inputs_avail = (int *) my_calloc(max_cluster_size + 1, - sizeof(int)); - } else { - hill_climbing_inputs_avail = NULL; /* if used, die hard */ - } - - /* TODO: make better estimate for nx and ny */ - nx = ny = 1; - - check_clocks(is_clock); -#if 0 - check_for_duplicate_inputs (); -#endif - alloc_and_init_clustering(global_clocks, alpha, beta, max_cluster_size, - max_molecule_inputs, max_pb_depth, num_models, - &cluster_placement_stats, &primitives_list, molecule_head, - num_molecules); - - blocks_since_last_analysis = 0; - early_exit = FALSE; - num_blocks_hill_added = 0; - num_used_instances_type = (int*) my_calloc(num_types, sizeof(int)); - num_instances_type = (int*) my_calloc(num_types, sizeof(int)); - - assert(max_cluster_size < MAX_SHORT); - /* Limit maximum number of elements for each cluster */ - - if (timing_driven) { - slacks = alloc_and_load_pre_packing_timing_graph(block_delay, - inter_cluster_net_delay, arch->models, timing_inf); - do_timing_analysis(slacks, TRUE, FALSE, FALSE); - - if (getEchoEnabled()) { - if(isEchoFileEnabled(E_ECHO_PRE_PACKING_TIMING_GRAPH)) - print_timing_graph(getEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH)); -#ifndef PATH_COUNTING - if(isEchoFileEnabled(E_ECHO_CLUSTERING_TIMING_INFO)) - print_clustering_timing_info(getEchoFileName(E_ECHO_CLUSTERING_TIMING_INFO)); -#endif - if(isEchoFileEnabled(E_ECHO_PRE_PACKING_SLACK)) - print_slack(slacks->slack, FALSE, getEchoFileName(E_ECHO_PRE_PACKING_SLACK)); - if(isEchoFileEnabled(E_ECHO_PRE_PACKING_CRITICALITY)) - print_criticality(slacks, FALSE, getEchoFileName(E_ECHO_PRE_PACKING_CRITICALITY)); - } - - block_criticality = (float*) my_calloc(num_logical_blocks, sizeof(float)); - - critindexarray = (int*) my_malloc(num_logical_blocks * sizeof(int)); - - for (i = 0; i < num_logical_blocks; i++) { - assert(logical_block[i].index == i); - critindexarray[i] = i; - } - -#ifdef PATH_COUNTING - /* Calculate block criticality from a weighted sum of timing and path criticalities. */ - for (inet = 0; inet < num_logical_nets; inet++) { - for (ipin = 1; ipin <= vpack_net[inet].num_sinks; ipin++) { - - /* Find the logical block iblk which this pin is a sink on. */ - iblk = vpack_net[inet].node_block[ipin]; - - /* The criticality of this pin is a sum of its timing and path criticalities. */ - crit = PACK_PATH_WEIGHT * slacks->path_criticality[inet][ipin] - + (1 - PACK_PATH_WEIGHT) * slacks->timing_criticality[inet][ipin]; - - /* The criticality of each block is the maximum of the criticalities of all its pins. */ - if (block_criticality[iblk] < crit) { - block_criticality[iblk] = crit; - } - } - } - -#else - /* Calculate criticality based on slacks and tie breakers (# paths, distance from source) */ - for (inode = 0; inode < num_tnodes; inode++) { - /* Only calculate for tnodes which have valid normalized values. - Either all values will be accurate or none will, so we only have - to check whether one particular value (normalized_T_arr) is valid - Tnodes that do not have both times valid were not part of the analysis. - Because we calloc-ed the array criticality, such nodes will have criticality 0, the lowest possible value. */ - if (has_valid_normalized_T_arr(inode)) { - iblk = tnode[inode].block; - num_paths_scaling = SCALE_NUM_PATHS - * (float) tnode[inode].prepacked_data->normalized_total_critical_paths; - distance_scaling = SCALE_DISTANCE_VAL - * (float) tnode[inode].prepacked_data->normalized_T_arr; - crit = (1 - tnode[inode].prepacked_data->normalized_slack) + num_paths_scaling - + distance_scaling; - if (block_criticality[iblk] < crit) { - block_criticality[iblk] = crit; - } - } - } -#endif - heapsort(critindexarray, block_criticality, num_logical_blocks, 1); - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_CLUSTERING_BLOCK_CRITICALITIES)) { - print_block_criticalities(getEchoFileName(E_ECHO_CLUSTERING_BLOCK_CRITICALITIES)); - } - - - if (cluster_seed_type == VPACK_TIMING) { - istart = get_most_critical_seed_molecule(&indexofcrit); - } else {/*max input seed*/ - istart = get_seed_logical_molecule_with_most_ext_inputs( - max_molecule_inputs); - } - - } else /*cluster seed is max input (since there is no timing information)*/ { - istart = get_seed_logical_molecule_with_most_ext_inputs( - max_molecule_inputs); - } - - - while (istart != NULL) { - is_cluster_legal = FALSE; - savedindexofcrit = indexofcrit; - for (detailed_routing_stage = (int)E_DETAILED_ROUTE_AT_END_ONLY; !is_cluster_legal && detailed_routing_stage != (int)E_DETAILED_ROUTE_END; detailed_routing_stage++) { - reset_legalizer_for_cluster(&clb[num_clb]); - - /* start a new cluster and reset all stats */ - start_new_cluster(cluster_placement_stats, primitives_list, arch, - &clb[num_clb], num_clb, istart, aspect, num_used_instances_type, - num_instances_type, num_models, max_cluster_size, - max_nets_in_pb_type, detailed_routing_stage); - vpr_printf(TIO_MESSAGE_INFO, "Complex block %d: %s, type: %s\n", - num_clb, clb[num_clb].name, clb[num_clb].type->name); - vpr_printf(TIO_MESSAGE_INFO, "\t"); - fflush(stdout); - update_cluster_stats(istart, num_clb, is_clock, global_clocks, alpha, - beta, timing_driven, connection_driven, slacks); - num_clb++; - - if (timing_driven && !early_exit) { - blocks_since_last_analysis++; - /*it doesn't make sense to do a timing analysis here since there* - *is only one logical_block clustered it would not change anything */ - } - cur_cluster_placement_stats_ptr = &cluster_placement_stats[clb[num_clb - 1].type->index]; - num_unrelated_clustering_attempts = 0; - next_molecule = get_molecule_for_cluster(PACK_BRUTE_FORCE, - clb[num_clb - 1].pb, allow_unrelated_clustering, - &num_unrelated_clustering_attempts, - cur_cluster_placement_stats_ptr); - prev_molecule = istart; - while (next_molecule != NULL && prev_molecule != next_molecule) { - block_pack_status = try_pack_molecule(cur_cluster_placement_stats_ptr, next_molecule, - primitives_list, clb[num_clb - 1].pb, num_models, - max_cluster_size, num_clb - 1, max_nets_in_pb_type, - detailed_routing_stage); - prev_molecule = next_molecule; - if (block_pack_status != BLK_PASSED) { - if (next_molecule != NULL) { - if (block_pack_status == BLK_FAILED_ROUTE) { -#ifdef DEBUG_FAILED_PACKING_CANDIDATES - vpr_printf(TIO_MESSAGE_DIRECT, "\tNO_ROUTE:%s type %s/n", - next_molecule->logical_block_ptrs[next_molecule->root]->name, - next_molecule->logical_block_ptrs[next_molecule->root]->model->name); - fflush(stdout); - #else - vpr_printf(TIO_MESSAGE_DIRECT, "."); - #endif - } else { - #ifdef DEBUG_FAILED_PACKING_CANDIDATES - vpr_printf(TIO_MESSAGE_DIRECT, "\tFAILED_CHECK:%s type %s check %d\n", - next_molecule->logical_block_ptrs[next_molecule->root]->name, - next_molecule->logical_block_ptrs[next_molecule->root]->model->name, - block_pack_status); - fflush(stdout); - #else - vpr_printf(TIO_MESSAGE_DIRECT, "."); - #endif - } - } - - next_molecule = get_molecule_for_cluster(PACK_BRUTE_FORCE, - clb[num_clb - 1].pb, allow_unrelated_clustering, - &num_unrelated_clustering_attempts, - cur_cluster_placement_stats_ptr); - continue; - } else { - /* Continue packing by filling smallest cluster */ - #ifdef DEBUG_FAILED_PACKING_CANDIDATES - vpr_printf(TIO_MESSAGE_DIRECT, "\tPASSED:%s type %s\n", - next_molecule->logical_block_ptrs[next_molecule->root]->name, - next_molecule->logical_block_ptrs[next_molecule->root]->model->name); - fflush(stdout); - #else - vpr_printf(TIO_MESSAGE_DIRECT, "."); - #endif - } - update_cluster_stats(next_molecule, num_clb - 1, is_clock, - global_clocks, alpha, beta, timing_driven, - connection_driven, slacks); - num_unrelated_clustering_attempts = 0; - - if (timing_driven && !early_exit) { - blocks_since_last_analysis++; /* historically, timing slacks were recomputed after X number of blocks were packed, but this doesn't significantly alter results so I (jluu) did not port the code */ - } - next_molecule = get_molecule_for_cluster(PACK_BRUTE_FORCE, - clb[num_clb - 1].pb, allow_unrelated_clustering, - &num_unrelated_clustering_attempts, - cur_cluster_placement_stats_ptr); - } - vpr_printf(TIO_MESSAGE_DIRECT, "\n"); - if (detailed_routing_stage == (int)E_DETAILED_ROUTE_AT_END_ONLY) { - is_cluster_legal = try_breadth_first_route_cluster(); - if (is_cluster_legal == TRUE) { - vpr_printf(TIO_MESSAGE_INFO, "Passed route at end.\n"); - } else { - vpr_printf(TIO_MESSAGE_INFO, "Failed route at end, repack cluster trying detailed routing at each stage.\n"); - } - } else { - is_cluster_legal = TRUE; - } - if (is_cluster_legal == TRUE) { - save_cluster_solution(); - if (timing_driven) { - if (num_blocks_hill_added > 0 && !early_exit) { - blocks_since_last_analysis += num_blocks_hill_added; - } - if (cluster_seed_type == VPACK_TIMING) { - istart = get_most_critical_seed_molecule(&indexofcrit); - } else { /*max input seed*/ - istart = get_seed_logical_molecule_with_most_ext_inputs( - max_molecule_inputs); - } - } else - /*cluster seed is max input (since there is no timing information)*/ - istart = get_seed_logical_molecule_with_most_ext_inputs( - max_molecule_inputs); - - free_pb_stats_recursive(clb[num_clb - 1].pb); - } else { - /* Free up data structures and requeue used molecules */ - num_used_instances_type[clb[num_clb - 1].type->index]--; - free_cb(clb[num_clb - 1].pb); - free(clb[num_clb - 1].pb); - free(clb[num_clb - 1].name); - clb[num_clb - 1].name = NULL; - clb[num_clb - 1].pb = NULL; - num_clb--; - indexofcrit = savedindexofcrit; - } - } - } - - free_cluster_legality_checker(); - - alloc_and_load_cluster_info(num_clb, clb); - - check_clustering(num_clb, clb, is_clock); - - output_clustering(clb, num_clb, global_clocks, is_clock, out_fname, FALSE); - - copy_nb_clusters = num_clb; - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_POST_PACK_NETLIST)) { - output_blif (clb, num_clb, global_clocks, is_clock, - getEchoFileName(E_ECHO_POST_PACK_NETLIST), FALSE); - } - - if (hill_climbing_flag) { - free(hill_climbing_inputs_avail); - } - free_cluster_placement_stats(cluster_placement_stats); - - for (i = 0; i < num_clb; i++) { - free_cb(clb[i].pb); - free(clb[i].name); - free(clb[i].nets); - free(clb[i].pb); - } - free(clb); - - free(num_used_instances_type); - free(num_instances_type); - free(unclustered_list_head); - free(memory_pool); - free(net_output_feeds_driving_block_input); - - if (timing_driven) { - free(block_criticality); - free(critindexarray); - - block_criticality = NULL; - critindexarray = NULL; - } - - if (timing_driven) { - free_timing_graph(slacks); - } - - free (primitives_list); - -} - -/*****************************************/ -static void check_clocks(boolean *is_clock) { - - /* Checks that nets used as clock inputs to latches are never also used * - * as VPACK_LUT inputs. It's electrically questionable, and more importantly * - * would break the clustering code. */ - - int inet, iblk, ipin; - t_model_ports *port; - - for (iblk = 0; iblk < num_logical_blocks; iblk++) { - if (logical_block[iblk].type != VPACK_OUTPAD) { - port = logical_block[iblk].model->inputs; - while (port) { - for (ipin = 0; ipin < port->size; ipin++) { - inet = logical_block[iblk].input_nets[port->index][ipin]; - if (inet != OPEN) { - if (is_clock[inet]) { - vpr_printf(TIO_MESSAGE_ERROR, "Error in check_clocks.\n"); - vpr_printf(TIO_MESSAGE_ERROR, "Net %d (%s) is a clock, but also connects to a logic block input on logical_block %d (%s).\n", - inet, vpack_net[inet].name, iblk, logical_block[iblk].name); - vpr_printf(TIO_MESSAGE_ERROR, "This would break the current clustering implementation and is electrically questionable, so clustering has been aborted.\n"); - exit(1); - } - } - } - port = port->next; - } - } - } -} - -/* Determine if logical block is in pb */ -static boolean is_logical_blk_in_pb(int iblk, t_pb *pb) { - t_pb * cur_pb; - cur_pb = logical_block[iblk].pb; - while (cur_pb) { - if (cur_pb == pb) { - return TRUE; - } - cur_pb = cur_pb->parent_pb; - } - return FALSE; -} - -/* Add blk to list of feasible blocks sorted according to gain */ -static void add_molecule_to_pb_stats_candidates(t_pack_molecule *molecule, - std::map &gain, t_pb *pb) { - int i, j; - - for (i = 0; i < pb->pb_stats->num_feasible_blocks; i++) { - if (pb->pb_stats->feasible_blocks[i] == molecule) { - return; /* already in queue, do nothing */ - } - } - - if (pb->pb_stats->num_feasible_blocks >= AAPACK_MAX_FEASIBLE_BLOCK_ARRAY_SIZE - 1) { - /* maximum size for array, remove smallest gain element and sort */ - if (get_molecule_gain(molecule, gain) > get_molecule_gain(pb->pb_stats->feasible_blocks[0], gain)) { - /* single loop insertion sort */ - for (j = 0; j < pb->pb_stats->num_feasible_blocks - 1; j++) { - if (get_molecule_gain(molecule, gain) <= get_molecule_gain(pb->pb_stats->feasible_blocks[j + 1], gain)) { - pb->pb_stats->feasible_blocks[j] = molecule; - break; - } else { - pb->pb_stats->feasible_blocks[j] = pb->pb_stats->feasible_blocks[j + 1]; - } - } - if (j == pb->pb_stats->num_feasible_blocks - 1) { - pb->pb_stats->feasible_blocks[j] = molecule; - } - } - } else { - /* Expand array and single loop insertion sort */ - for (j = pb->pb_stats->num_feasible_blocks - 1; j >= 0; j--) { - if (get_molecule_gain(pb->pb_stats->feasible_blocks[j], gain) > get_molecule_gain(molecule, gain)) { - pb->pb_stats->feasible_blocks[j + 1] = pb->pb_stats->feasible_blocks[j]; - } else { - pb->pb_stats->feasible_blocks[j + 1] = molecule; - break; - } - } - if (j < 0) { - pb->pb_stats->feasible_blocks[0] = molecule; - } - pb->pb_stats->num_feasible_blocks++; - } -} - -/*****************************************/ -static void alloc_and_init_clustering(boolean global_clocks, float alpha, - float beta, int max_cluster_size, int max_molecule_inputs, - int max_pb_depth, int max_models, - t_cluster_placement_stats **cluster_placement_stats, - t_pb_graph_node ***primitives_list, t_pack_molecule *molecules_head, - int num_molecules) { - - /* Allocates the main data structures used for clustering and properly * - * initializes them. */ - - int i, ext_inps, ipin, driving_blk, inet; - struct s_molecule_link *next_ptr; - t_pack_molecule *cur_molecule; - t_pack_molecule **molecule_array; - int max_molecule_size; - - alloc_and_load_cluster_legality_checker(); - /**cluster_placement_stats = alloc_and_load_cluster_placement_stats();*/ - - for (i = 0; i < num_logical_blocks; i++) { - logical_block[i].clb_index = NO_CLUSTER; - } - - /* alloc and load list of molecules to pack */ - unclustered_list_head = (struct s_molecule_link *) my_calloc( - max_molecule_inputs + 1, sizeof(struct s_molecule_link)); - unclustered_list_head_size = max_molecule_inputs + 1; - - for (i = 0; i <= max_molecule_inputs; i++) { - unclustered_list_head[i].next = NULL; - } - - molecule_array = (t_pack_molecule **) my_malloc( - num_molecules * sizeof(t_pack_molecule*)); - cur_molecule = molecules_head; - for (i = 0; i < num_molecules; i++) { - assert(cur_molecule != NULL); - molecule_array[i] = cur_molecule; - cur_molecule = cur_molecule->next; - } - assert(cur_molecule == NULL); - qsort((void*) molecule_array, num_molecules, sizeof(t_pack_molecule*), - compare_molecule_gain); - - memory_pool = (struct s_molecule_link *) my_malloc( - num_molecules * sizeof(struct s_molecule_link)); - next_ptr = memory_pool; - - for (i = 0; i < num_molecules; i++) { - ext_inps = molecule_array[i]->num_ext_inputs; - next_ptr->moleculeptr = molecule_array[i]; - next_ptr->next = unclustered_list_head[ext_inps].next; - unclustered_list_head[ext_inps].next = next_ptr; - next_ptr++; - } - free(molecule_array); - - /* alloc and load net info */ - net_output_feeds_driving_block_input = (int *) my_malloc( - num_logical_nets * sizeof(int)); - - for (inet = 0; inet < num_logical_nets; inet++) { - net_output_feeds_driving_block_input[inet] = 0; - driving_blk = vpack_net[inet].node_block[0]; - for (ipin = 1; ipin <= vpack_net[inet].num_sinks; ipin++) { - if (vpack_net[inet].node_block[ipin] == driving_blk) { - net_output_feeds_driving_block_input[inet]++; - } - } - } - - /* alloc and load cluster placement info */ - *cluster_placement_stats = alloc_and_load_cluster_placement_stats(); - - /* alloc array that will store primitives that a molecule gets placed to, - primitive_list is referenced by index, for example a logical block in index 2 of a molecule matches to a primitive in index 2 in primitive_list - this array must be the size of the biggest molecule - */ - max_molecule_size = 1; - cur_molecule = molecules_head; - while (cur_molecule != NULL) { - if (cur_molecule->num_blocks > max_molecule_size) { - max_molecule_size = cur_molecule->num_blocks; - } - cur_molecule = cur_molecule->next; - } - *primitives_list = (t_pb_graph_node **)my_calloc(max_molecule_size, sizeof(t_pb_graph_node *)); -} - -/*****************************************/ -static void free_pb_stats_recursive(t_pb *pb) { - - int i, j; - /* Releases all the memory used by clustering data structures. */ - if (pb) { - if (pb->pb_graph_node != NULL) { - if (pb->pb_graph_node->pb_type->num_modes != 0) { - for (i = 0; - i - < pb->pb_graph_node->pb_type->modes[pb->mode].num_pb_type_children; - i++) { - for (j = 0; - j - < pb->pb_graph_node->pb_type->modes[pb->mode].pb_type_children[i].num_pb; - j++) { - if (pb->child_pbs && pb->child_pbs[i]) { - free_pb_stats_recursive(&pb->child_pbs[i][j]); - } - } - } - } - } - free_pb_stats(pb); - } -} - -static boolean primitive_feasible(int iblk, t_pb *cur_pb) { - const t_pb_type *cur_pb_type; - int i; - t_pb *memory_class_pb; /* Used for memory class only, for memories, open pins must be the same among siblings */ - int sibling_memory_blk; - - cur_pb_type = cur_pb->pb_graph_node->pb_type; - memory_class_pb = NULL; - sibling_memory_blk = OPEN; - - assert(cur_pb_type->num_modes == 0); - /* primitive */ - if (cur_pb->logical_block != OPEN && cur_pb->logical_block != iblk) { - /* This pb already has a different logical block */ - return FALSE; - } - - if (cur_pb_type->class_type == MEMORY_CLASS) { - /* memory class is special, all siblings must share all nets, including open nets, with the exception of data nets */ - /* find sibling if one exists */ - memory_class_pb = cur_pb->parent_pb; - for (i = 0; i < cur_pb_type->parent_mode->num_pb_type_children; i++) { - if (memory_class_pb->child_pbs[cur_pb->mode][i].name != NULL - && memory_class_pb->child_pbs[cur_pb->mode][i].logical_block != OPEN) { - sibling_memory_blk = memory_class_pb->child_pbs[cur_pb->mode][i].logical_block; - } - } - if (sibling_memory_blk == OPEN) { - memory_class_pb = NULL; - } - } - - return primitive_type_and_memory_feasible(iblk, cur_pb_type, - memory_class_pb, sibling_memory_blk); -} - -static boolean primitive_type_and_memory_feasible(int iblk, - const t_pb_type *cur_pb_type, t_pb *memory_class_pb, - int sibling_memory_blk) { - t_model_ports *port; - int i, j; - boolean second_pass; - - /* check if ports are big enough */ - /* for memories, also check that pins are the same with existing siblings */ - port = logical_block[iblk].model->inputs; - second_pass = FALSE; - while (port || !second_pass) { - /* TODO: This is slow if the number of ports are large, fix if becomes a problem */ - if (!port) { - second_pass = TRUE; - port = logical_block[iblk].model->outputs; - } - for (i = 0; i < cur_pb_type->num_ports; i++) { - if (cur_pb_type->ports[i].model_port == port) { - /* TODO: This is slow, I only need to check from 0 if it is a memory block, other blocks I can check from port->size onwards */ - for (j = 0; j < port->size; j++) { - if (port->dir == IN_PORT && !port->is_clock) { - if (memory_class_pb) { - if (cur_pb_type->ports[i].port_class == NULL - || strstr(cur_pb_type->ports[i].port_class,"data") != cur_pb_type->ports[i].port_class) { - if (logical_block[iblk].input_nets[port->index][j] != logical_block[sibling_memory_blk].input_nets[port->index][j]) { - return FALSE; - } - } - } - if (logical_block[iblk].input_nets[port->index][j] != OPEN - && j >= cur_pb_type->ports[i].num_pins) { - return FALSE; - } - } else if (port->dir == OUT_PORT) { - if (memory_class_pb) { - if (cur_pb_type->ports[i].port_class == NULL - || strstr(cur_pb_type->ports[i].port_class, "data") != cur_pb_type->ports[i].port_class) { - if (logical_block[iblk].output_nets[port->index][j] != logical_block[sibling_memory_blk].output_nets[port->index][j]) { - return FALSE; - } - } - } - if (logical_block[iblk].output_nets[port->index][j] != OPEN - && j >= cur_pb_type->ports[i].num_pins) { - return FALSE; - } - } else { - assert(port->dir == IN_PORT && port->is_clock); - assert(j == 0); - if (memory_class_pb) { - if (logical_block[iblk].clock_net != logical_block[sibling_memory_blk].clock_net) { - return FALSE; - } - } - if (logical_block[iblk].clock_net != OPEN && j >= cur_pb_type->ports[i].num_pins) { - return FALSE; - } - } - } - break; - } - } - if (i == cur_pb_type->num_ports) { - if (((logical_block[iblk].model->inputs != NULL) && !second_pass) - || (logical_block[iblk].model->outputs != NULL - && second_pass)) { - /* physical port not found */ - return FALSE; - } - } - if (port) { - port = port->next; - } - } - return TRUE; -} - -/*****************************************/ -static t_pack_molecule *get_molecule_by_num_ext_inputs( - INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, - INP int ext_inps, INP enum e_removal_policy remove_flag, - INP t_cluster_placement_stats *cluster_placement_stats_ptr) { - - /* This routine returns a logical_block which has not been clustered, has * - * no connection to the current cluster, satisfies the cluster * - * clock constraints, is a valid subblock inside the cluster, does not exceed the cluster subblock units available, - and has ext_inps external inputs. If * - * there is no such logical_block it returns NO_CLUSTER. Remove_flag * - * controls whether or not blocks that have already been clustered * - * are removed from the unclustered_list data structures. NB: * - * to get a logical_block regardless of clock constraints just set clocks_ * - * avail > 0. */ - - struct s_molecule_link *ptr, *prev_ptr; - int ilogical_blk, i; - boolean success; - - prev_ptr = &unclustered_list_head[ext_inps]; - ptr = unclustered_list_head[ext_inps].next; - while (ptr != NULL) { - /* TODO: Get better candidate logical block in future, eg. return most timing critical or some other smarter metric */ - /* TODO: (Xifan Tang) An alternation is to select the candidate that share the max. number of input/output nets to the other logic block with other primitives in the logic block */ - if (ptr->moleculeptr->valid) { - success = TRUE; - for (i = 0; i < get_array_size_of_molecule(ptr->moleculeptr); i++) { - if (ptr->moleculeptr->logical_block_ptrs[i] != NULL) { - ilogical_blk = ptr->moleculeptr->logical_block_ptrs[i]->index; - if (!exists_free_primitive_for_logical_block(cluster_placement_stats_ptr, ilogical_blk)) { /* TODO: I should be using a better filtering check especially when I'm dealing with multiple clock/multiple global reset signals where the clock/reset packed in matters, need to do later when I have the circuits to check my work */ - success = FALSE; - break; - } - } - } - if (success == TRUE) { - return ptr->moleculeptr; - } - prev_ptr = ptr; - } - - else if (remove_flag == REMOVE_CLUSTERED) { - assert(0); /* this doesn't work right now with 2 the pass packing for each complex block */ - prev_ptr->next = ptr->next; - } - - ptr = ptr->next; - } - - return NULL; -} - -/*****************************************/ -static t_pack_molecule *get_free_molecule_with_most_ext_inputs_for_cluster( - INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, - INP t_cluster_placement_stats *cluster_placement_stats_ptr) { - - /* This routine is used to find new blocks for clustering when there are no feasible * - * blocks with any attraction to the current cluster (i.e. it finds * - * blocks which are unconnected from the current cluster). It returns * - * the logical_block with the largest number of used inputs that satisfies the * - * clocking and number of inputs constraints. If no suitable logical_block is * - * found, the routine returns NO_CLUSTER. - * TODO: Analyze if this function is useful in more detail, also, should probably not include clock in input count - */ - - int ext_inps; - int i, j; - t_pack_molecule *molecule; - - int inputs_avail = 0; - - for (i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) { - for (j = 0; j < cur_pb->pb_graph_node->input_pin_class_size[i]; j++) { - if (cur_pb->pb_stats->input_pins_used[i][j] != OPEN) - inputs_avail++; - } - } - - molecule = NULL; - - if (inputs_avail >= unclustered_list_head_size) { - inputs_avail = unclustered_list_head_size - 1; - } - - for (ext_inps = inputs_avail; ext_inps >= 0; ext_inps--) { - molecule = get_molecule_by_num_ext_inputs(packer_algorithm, cur_pb, - ext_inps, LEAVE_CLUSTERED, cluster_placement_stats_ptr); - if (molecule != NULL) { - break; - } - } - return molecule; -} - -/*****************************************/ -static t_pack_molecule* get_seed_logical_molecule_with_most_ext_inputs( - int max_molecule_inputs) { - - /* This routine is used to find the first seed logical_block for the clustering. It returns * - * the logical_block with the largest number of used inputs that satisfies the * - * clocking and number of inputs constraints. If no suitable logical_block is * - * found, the routine returns NO_CLUSTER. */ - - int ext_inps; - struct s_molecule_link *ptr; - - for (ext_inps = max_molecule_inputs; ext_inps >= 0; ext_inps--) { - ptr = unclustered_list_head[ext_inps].next; - - while (ptr != NULL) { - if (ptr->moleculeptr->valid) { - return ptr->moleculeptr; - } - ptr = ptr->next; - } - } - return NULL; -} - -/*****************************************/ - -/*****************************************/ -static void alloc_and_load_pb_stats(t_pb *pb, int max_models, - int max_nets_in_pb_type) { - - /* Call this routine when starting to fill up a new cluster. It resets * - * the gain vector, etc. */ - - int i, j; - - pb->pb_stats = new t_pb_stats; - - /* If statement below is for speed. If nets are reasonably low-fanout, * - * only a relatively small number of blocks will be marked, and updating * - * only those logical_block structures will be fastest. If almost all blocks * - * have been touched it should be faster to just run through them all * - * in order (less addressing and better cache locality). */ - pb->pb_stats->input_pins_used = (int **) my_malloc( - pb->pb_graph_node->num_input_pin_class * sizeof(int*)); - pb->pb_stats->output_pins_used = (int **) my_malloc( - pb->pb_graph_node->num_output_pin_class * sizeof(int*)); - pb->pb_stats->lookahead_input_pins_used = (int **) my_malloc( - pb->pb_graph_node->num_input_pin_class * sizeof(int*)); - pb->pb_stats->lookahead_output_pins_used = (int **) my_malloc( - pb->pb_graph_node->num_output_pin_class * sizeof(int*)); - pb->pb_stats->num_feasible_blocks = NOT_VALID; - pb->pb_stats->feasible_blocks = (t_pack_molecule**) my_calloc( - AAPACK_MAX_FEASIBLE_BLOCK_ARRAY_SIZE, sizeof(t_pack_molecule *)); - - pb->pb_stats->tie_break_high_fanout_net = OPEN; - for (i = 0; i < pb->pb_graph_node->num_input_pin_class; i++) { - pb->pb_stats->input_pins_used[i] = (int*) my_malloc( - pb->pb_graph_node->input_pin_class_size[i] * sizeof(int)); - for (j = 0; j < pb->pb_graph_node->input_pin_class_size[i]; j++) { - pb->pb_stats->input_pins_used[i][j] = OPEN; - } - } - - for (i = 0; i < pb->pb_graph_node->num_output_pin_class; i++) { - pb->pb_stats->output_pins_used[i] = (int*) my_malloc( - pb->pb_graph_node->output_pin_class_size[i] * sizeof(int)); - for (j = 0; j < pb->pb_graph_node->output_pin_class_size[i]; j++) { - pb->pb_stats->output_pins_used[i][j] = OPEN; - } - } - - for (i = 0; i < pb->pb_graph_node->num_input_pin_class; i++) { - pb->pb_stats->lookahead_input_pins_used[i] = (int*) my_malloc( - (AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST + pb->pb_graph_node->input_pin_class_size[i] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC) * sizeof(int)); - for (j = 0; - j - < pb->pb_graph_node->input_pin_class_size[i] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; j++) { - pb->pb_stats->lookahead_input_pins_used[i][j] = OPEN; - } - } - - for (i = 0; i < pb->pb_graph_node->num_output_pin_class; i++) { - pb->pb_stats->lookahead_output_pins_used[i] = (int*) my_malloc( - (AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST + - pb->pb_graph_node->output_pin_class_size[i] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC) * sizeof(int)); - for (j = 0; - j - < pb->pb_graph_node->output_pin_class_size[i] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; j++) { - pb->pb_stats->lookahead_output_pins_used[i][j] = OPEN; - } - } - - pb->pb_stats->gain.clear(); - pb->pb_stats->timinggain.clear(); - pb->pb_stats->connectiongain.clear(); - pb->pb_stats->sharinggain.clear(); - pb->pb_stats->hillgain.clear(); - - pb->pb_stats->num_pins_of_net_in_pb.clear(); - - pb->pb_stats->marked_nets = (int *) my_malloc( - max_nets_in_pb_type * sizeof(int)); - pb->pb_stats->marked_blocks = (int *) my_malloc( - num_logical_blocks * sizeof(int)); - - pb->pb_stats->num_marked_nets = 0; - pb->pb_stats->num_marked_blocks = 0; - - pb->pb_stats->num_child_blocks_in_pb = 0; -} -/*****************************************/ - -/** - * Try pack molecule into current cluster - */ -static enum e_block_pack_status try_pack_molecule( - INOUTP t_cluster_placement_stats *cluster_placement_stats_ptr, - INP t_pack_molecule *molecule, INOUTP t_pb_graph_node **primitives_list, - INOUTP t_pb * pb, INP int max_models, INP int max_cluster_size, - INP int clb_index, INP int max_nets_in_pb_type, INP int detailed_routing_stage) { - int molecule_size, failed_location; - int i; - enum e_block_pack_status block_pack_status; - struct s_linked_vptr *cur_molecule; - t_pb *parent; - t_pb *cur_pb; - t_logical_block *chain_root_block; - boolean is_root_of_chain; - t_pb_graph_pin *chain_root_pin; - /* Xifan TANG: count the runtime for packing placement*/ - clock_t begin, end; - - parent = NULL; - - block_pack_status = BLK_STATUS_UNDEFINED; - - molecule_size = get_array_size_of_molecule(molecule); - failed_location = 0; - - while (block_pack_status != BLK_PASSED) { - save_and_reset_routing_cluster(); /* save current routing information because speculative packing will change routing*/ - if (get_next_primitive_list(cluster_placement_stats_ptr, molecule, - primitives_list, clb_index)) { - block_pack_status = BLK_PASSED; - - for (i = 0; i < molecule_size && block_pack_status == BLK_PASSED; - i++) { - assert( - (primitives_list[i] == NULL) == (molecule->logical_block_ptrs[i] == NULL)); - failed_location = i + 1; - if (molecule->logical_block_ptrs[i] != NULL) { - if(molecule->type == MOLECULE_FORCED_PACK && molecule->pack_pattern->is_chain && i == molecule->pack_pattern->root_block->block_id) { - chain_root_pin = molecule->pack_pattern->chain_root_pin; - is_root_of_chain = TRUE; - } else { - chain_root_pin = NULL; - is_root_of_chain = FALSE; - } - block_pack_status = try_place_logical_block_rec( - primitives_list[i], - molecule->logical_block_ptrs[i]->index, pb, &parent, - max_models, max_cluster_size, clb_index, - max_nets_in_pb_type, cluster_placement_stats_ptr, is_root_of_chain, chain_root_pin); - } - } - if (block_pack_status == BLK_PASSED) { - /* Check if pin usage is feasible for the current packing assigment */ - reset_lookahead_pins_used(pb); - try_update_lookahead_pins_used(pb); - if (!check_lookahead_pins_used(pb)) { - block_pack_status = BLK_FAILED_FEASIBLE; - } - } - if (block_pack_status == BLK_PASSED) { - /* start of pack placement */ - begin = clock(); - /* Try to route if heuristic is to route for every atom - Skip routing if heuristic is to route at the end of packing complex block - */ - setup_intracluster_routing_for_molecule(molecule, primitives_list); - if (detailed_routing_stage == (int)E_DETAILED_ROUTE_FOR_EACH_ATOM && try_breadth_first_route_cluster() == FALSE) { - /* Cannot pack */ - block_pack_status = BLK_FAILED_ROUTE; - } else { - /* Pack successful, commit - TODO: SW Engineering note - may want to update cluster stats here too instead of doing it outside - */ - assert(block_pack_status == BLK_PASSED); - if(molecule->type == MOLECULE_FORCED_PACK && molecule->pack_pattern->is_chain) { - /* Chained molecules often take up lots of area and are important, if a chain is packed in, want to rename logic block to match chain name */ - chain_root_block = molecule->logical_block_ptrs[molecule->pack_pattern->root_block->block_id]; - cur_pb = chain_root_block->pb->parent_pb; - while(cur_pb != NULL) { - free(cur_pb->name); - cur_pb->name = my_strdup(chain_root_block->name); - cur_pb = cur_pb->parent_pb; - } - } - for (i = 0; i < molecule_size; i++) { - if (molecule->logical_block_ptrs[i] != NULL) { - /* invalidate all molecules that share logical block with current molecule */ - cur_molecule = molecule->logical_block_ptrs[i]->packed_molecules; - while (cur_molecule != NULL) { - ((t_pack_molecule*) cur_molecule->data_vptr)->valid = FALSE; - cur_molecule = cur_molecule->next; - } - commit_primitive(cluster_placement_stats_ptr, primitives_list[i]); - } - } - } - /* end of pack route */ - end = clock(); - /* accumulate the runtime for pack route */ -#ifdef CLOCKS_PER_SEC - pack_route_time += (float)(end - begin)/ CLOCKS_PER_SEC; -#else - pack_route_time += (float)(end - begin)/ CLK_PER_SEC; -#endif - } - if (block_pack_status != BLK_PASSED) { - for (i = 0; i < failed_location; i++) { - if (molecule->logical_block_ptrs[i] != NULL) { - revert_place_logical_block(molecule->logical_block_ptrs[i]->index, max_models); - } - } - restore_routing_cluster(); - } - } else { - block_pack_status = BLK_FAILED_FEASIBLE; - restore_routing_cluster(); - break; /* no more candidate primitives available, this molecule will not pack, return fail */ - } - } - return block_pack_status; -} - -/** - * Try place logical block into current primitive location - */ - -static enum e_block_pack_status try_place_logical_block_rec( - INP t_pb_graph_node *pb_graph_node, INP int ilogical_block, - INP t_pb *cb, OUTP t_pb **parent, INP int max_models, - INP int max_cluster_size, INP int clb_index, - INP int max_nets_in_pb_type, - INP t_cluster_placement_stats *cluster_placement_stats_ptr, - INP boolean is_root_of_chain, INP t_pb_graph_pin *chain_root_pin) { - int i, j; - boolean is_primitive; - enum e_block_pack_status block_pack_status; - - t_pb *my_parent; - t_pb *pb, *parent_pb; - const t_pb_type *pb_type; - - t_model_ports *root_port; - - my_parent = NULL; - - block_pack_status = BLK_PASSED; - - /* Discover parent */ - if (pb_graph_node->parent_pb_graph_node != cb->pb_graph_node) { - block_pack_status = try_place_logical_block_rec( - pb_graph_node->parent_pb_graph_node, ilogical_block, cb, - &my_parent, max_models, max_cluster_size, clb_index, - max_nets_in_pb_type, cluster_placement_stats_ptr, is_root_of_chain, chain_root_pin); - parent_pb = my_parent; - } else { - parent_pb = cb; - } - - /* Create siblings if siblings are not allocated */ - if (parent_pb->child_pbs == NULL) { - assert(parent_pb->name == NULL); - parent_pb->logical_block = OPEN; - parent_pb->name = my_strdup(logical_block[ilogical_block].name); - parent_pb->mode = pb_graph_node->pb_type->parent_mode->index; - /* set_pb_graph_mode(parent_pb->pb_graph_node, 0, 0); */ /* TODO: default mode is to use mode 0, document this! */ - set_pb_graph_mode(parent_pb->pb_graph_node, parent_pb->mode, 1); - parent_pb->child_pbs = (t_pb **) my_calloc(parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].num_pb_type_children, sizeof(t_pb *)); - for (i = 0; i < parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].num_pb_type_children; i++) { - parent_pb->child_pbs[i] = (t_pb *) my_calloc(parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].pb_type_children[i].num_pb, sizeof(t_pb)); - for (j = 0; j < parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].pb_type_children[i].num_pb; j++) { - parent_pb->child_pbs[i][j].parent_pb = parent_pb; - parent_pb->child_pbs[i][j].logical_block = OPEN; - parent_pb->child_pbs[i][j].pb_graph_node = &(parent_pb->pb_graph_node->child_pb_graph_nodes[parent_pb->mode][i][j]); - } - } - } else { - assert(parent_pb->mode == pb_graph_node->pb_type->parent_mode->index); - } - - for (i = 0; i < parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].num_pb_type_children; i++) { - if (pb_graph_node->pb_type == &parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].pb_type_children[i]) { - break; - } - } - assert(i < parent_pb->pb_graph_node->pb_type->modes[parent_pb->mode].num_pb_type_children); - pb = &parent_pb->child_pbs[i][pb_graph_node->placement_index]; - *parent = pb; /* this pb is parent of it's child that called this function */ - assert(pb->pb_graph_node == pb_graph_node); - if (pb->pb_stats == NULL) { - alloc_and_load_pb_stats(pb, max_models, max_nets_in_pb_type); - } - pb_type = pb_graph_node->pb_type; - - /* Xifan Tang: bypass those modes that are specified as unavaible during packing */ - if (TRUE == pb_type->parent_mode->disabled_in_packing) { - return BLK_FAILED_FEASIBLE; - } - /* END */ - - is_primitive = (boolean) (pb_type->num_modes == 0); - - if (is_primitive) { - assert(pb->logical_block == OPEN && logical_block[ilogical_block].pb == NULL && logical_block[ilogical_block].clb_index == NO_CLUSTER); - /* try pack to location */ - pb->name = my_strdup(logical_block[ilogical_block].name); - pb->logical_block = ilogical_block; - logical_block[ilogical_block].clb_index = clb_index; - logical_block[ilogical_block].pb = pb; - - if (!primitive_feasible(ilogical_block, pb)) { - /* failed location feasibility check, revert pack */ - block_pack_status = BLK_FAILED_FEASIBLE; - } - - if (block_pack_status == BLK_PASSED && is_root_of_chain == TRUE) { - /* is carry chain, must check if this carry chain spans multiple logic blocks or not */ - root_port = chain_root_pin->port->model_port; - if(logical_block[ilogical_block].input_nets[root_port->index][chain_root_pin->pin_number] != OPEN) { - /* this carry chain spans multiple logic blocks, must match up correctly with previous chain for this to route */ - if(pb_graph_node != chain_root_pin->parent_node) { - /* this location does not match with the dedicated chain input from outside logic block, therefore not feasible */ - block_pack_status = BLK_FAILED_FEASIBLE; - } - } - } - } - - return block_pack_status; -} - -/* Revert trial logical block iblock and free up memory space accordingly - */ -static void revert_place_logical_block(INP int iblock, INP int max_models) { - t_pb *pb, *next; - - pb = logical_block[iblock].pb; - logical_block[iblock].clb_index = NO_CLUSTER; - logical_block[iblock].pb = NULL; - - if (pb != NULL) { - /* When freeing molecules, the current block might already have been freed by a prior revert - When this happens, no need to do anything beyond basic book keeping at the logical block - */ - - next = pb->parent_pb; - free_pb(pb); - pb = next; - - while (pb != NULL) { - /* If this is pb is created only for the purposes of holding new molecule, remove it - Must check if cluster is already freed (which can be the case) - */ - next = pb->parent_pb; - - if (pb->child_pbs != NULL && pb->pb_stats != NULL - && pb->pb_stats->num_child_blocks_in_pb == 0) { - set_pb_graph_mode(pb->pb_graph_node, pb->mode, 0); /* default mode is to use mode 1 */ - set_pb_graph_mode(pb->pb_graph_node, 0, 1); - if (next != NULL) { - /* If the code gets here, then that means that placing the initial seed molecule failed, don't free the actual complex block itself as the seed needs to find another placement */ - free_pb(pb); - } - } - pb = next; - } - } -} - -static void update_connection_gain_values(int inet, int clustered_block, - t_pb *cur_pb, - enum e_net_relation_to_clustered_block net_relation_to_clustered_block) { - /*This function is called when the connectiongain values on the vpack_net* - *inet require updating. */ - - int iblk, ipin; - int clb_index; - int num_internal_connections, num_open_connections, num_stuck_connections; - - num_internal_connections = num_open_connections = num_stuck_connections = 0; - - clb_index = logical_block[clustered_block].clb_index; - - /* may wish to speed things up by ignoring clock nets since they are high fanout */ - - for (ipin = 0; ipin <= vpack_net[inet].num_sinks; ipin++) { - iblk = vpack_net[inet].node_block[ipin]; - if (logical_block[iblk].clb_index == clb_index - && is_logical_blk_in_pb(iblk, - logical_block[clustered_block].pb)) { - num_internal_connections++; - } else if (logical_block[iblk].clb_index == OPEN) { - num_open_connections++; - } else { - num_stuck_connections++; - } - } - - if (net_relation_to_clustered_block == OUTPUT) { - for (ipin = 1; ipin <= vpack_net[inet].num_sinks; ipin++) { - iblk = vpack_net[inet].node_block[ipin]; - if (logical_block[iblk].clb_index == NO_CLUSTER) { - /* TODO: Gain function accurate only if net has one connection to block, TODO: Should we handle case where net has multi-connection to block? Gain computation is only off by a bit in this case */ - if(cur_pb->pb_stats->connectiongain.count(iblk) == 0) { - cur_pb->pb_stats->connectiongain[iblk] = 0; - } - - if (num_internal_connections > 1) { - cur_pb->pb_stats->connectiongain[iblk] -= 1 - / (float) (vpack_net[inet].num_sinks - - (num_internal_connections - 1) - + 1 * num_stuck_connections); - } - cur_pb->pb_stats->connectiongain[iblk] += 1 - / (float) (vpack_net[inet].num_sinks - - num_internal_connections - + 1 * num_stuck_connections); - } - } - } - - if (net_relation_to_clustered_block == INPUT) { - /*Calculate the connectiongain for the logical_block which is driving * - *the vpack_net that is an input to a logical_block in the cluster */ - - iblk = vpack_net[inet].node_block[0]; - if (logical_block[iblk].clb_index == NO_CLUSTER) { - if(cur_pb->pb_stats->connectiongain.count(iblk) == 0) { - cur_pb->pb_stats->connectiongain[iblk] = 0; - } - if (num_internal_connections > 1) { - cur_pb->pb_stats->connectiongain[iblk] -= 1 - / (float) (vpack_net[inet].num_sinks - - (num_internal_connections - 1) + 1 - + 1 * num_stuck_connections); - } - cur_pb->pb_stats->connectiongain[iblk] += 1 - / (float) (vpack_net[inet].num_sinks - - num_internal_connections + 1 - + 1 * num_stuck_connections); - } - } -} -/*****************************************/ -static void update_timing_gain_values(int inet, int clustered_block, - t_pb *cur_pb, - enum e_net_relation_to_clustered_block net_relation_to_clustered_block, t_slack * slacks) { - - /*This function is called when the timing_gain values on the vpack_net* - *inet requires updating. */ - float timinggain; - int newblk, ifirst; - int iblk, ipin; - - /* Check if this vpack_net lists its driving logical_block twice. If so, avoid * - * double counting this logical_block by skipping the first (driving) pin. */ - if (net_output_feeds_driving_block_input[inet] == FALSE) - ifirst = 0; - else - ifirst = 1; - - if (net_relation_to_clustered_block == OUTPUT - && !vpack_net[inet].is_global) { - for (ipin = ifirst; ipin <= vpack_net[inet].num_sinks; ipin++) { - iblk = vpack_net[inet].node_block[ipin]; - if (logical_block[iblk].clb_index == NO_CLUSTER) { -#ifdef PATH_COUNTING - /* Timing gain is a weighted sum of timing and path criticalities. */ - timinggain = TIMING_GAIN_PATH_WEIGHT * slacks->path_criticality[inet][ipin] - + (1 - TIMING_GAIN_PATH_WEIGHT) * slacks->timing_criticality[inet][ipin]; -#else - /* Timing gain is the timing criticality. */ - timinggain = slacks->timing_criticality[inet][ipin]; -#endif - if(cur_pb->pb_stats->timinggain.count(iblk) == 0) { - cur_pb->pb_stats->timinggain[iblk] = 0; - } - if (timinggain > cur_pb->pb_stats->timinggain[iblk]) - cur_pb->pb_stats->timinggain[iblk] = timinggain; - } - } - } - - if (net_relation_to_clustered_block == INPUT - && !vpack_net[inet].is_global) { - /*Calculate the timing gain for the logical_block which is driving * - *the vpack_net that is an input to a logical_block in the cluster */ - newblk = vpack_net[inet].node_block[0]; - if (logical_block[newblk].clb_index == NO_CLUSTER) { - for (ipin = 1; ipin <= vpack_net[inet].num_sinks; ipin++) { -#ifdef PATH_COUNTING - /* Timing gain is a weighted sum of timing and path criticalities. */ - timinggain = TIMING_GAIN_PATH_WEIGHT * slacks->path_criticality[inet][ipin] - + (1 - TIMING_GAIN_PATH_WEIGHT) * slacks->timing_criticality[inet][ipin]; -#else - /* Timing gain is the timing criticality. */ - timinggain = slacks->timing_criticality[inet][ipin]; -#endif - if(cur_pb->pb_stats->timinggain.count(newblk) == 0) { - cur_pb->pb_stats->timinggain[newblk] = 0; - } - if (timinggain > cur_pb->pb_stats->timinggain[newblk]) - cur_pb->pb_stats->timinggain[newblk] = timinggain; - - } - } - } -} -/*****************************************/ -static void mark_and_update_partial_gain(int inet, enum e_gain_update gain_flag, - int clustered_block, int port_on_clustered_block, - int pin_on_clustered_block, boolean timing_driven, - boolean connection_driven, - enum e_net_relation_to_clustered_block net_relation_to_clustered_block, - t_slack * slacks) { - - /* Updates the marked data structures, and if gain_flag is GAIN, * - * the gain when a logic logical_block is added to a cluster. The * - * sharinggain is the number of inputs that a logical_block shares with * - * blocks that are already in the cluster. Hillgain is the * - * reduction in number of pins-required by adding a logical_block to the * - * cluster. The timinggain is the criticality of the most critical* - * vpack_net between this logical_block and a logical_block in the cluster. */ - - int iblk, ipin, ifirst, stored_net; - t_pb *cur_pb; - - cur_pb = logical_block[clustered_block].pb->parent_pb; - - - if (vpack_net[inet].num_sinks > AAPACK_MAX_NET_SINKS_IGNORE) { - /* Optimization: It can be too runtime costly for marking all sinks for a high fanout-net that probably has no hope of ever getting packed, thus ignore those high fanout nets */ - if(vpack_net[inet].is_global != TRUE) { - /* If no low/medium fanout nets, we may need to consider high fan-out nets for packing, so select one and store it */ - while(cur_pb->parent_pb != NULL) { - cur_pb = cur_pb->parent_pb; - } - stored_net = cur_pb->pb_stats->tie_break_high_fanout_net; - if(stored_net == OPEN || vpack_net[inet].num_sinks < vpack_net[stored_net].num_sinks) { - cur_pb->pb_stats->tie_break_high_fanout_net = inet; - } - } - return; - } - - while (cur_pb) { - /* Mark vpack_net as being visited, if necessary. */ - - if (cur_pb->pb_stats->num_pins_of_net_in_pb.count(inet) == 0) { - cur_pb->pb_stats->marked_nets[cur_pb->pb_stats->num_marked_nets] = - inet; - cur_pb->pb_stats->num_marked_nets++; - } - - /* Update gains of affected blocks. */ - - if (gain_flag == GAIN) { - - /* Check if this vpack_net lists its driving logical_block twice. If so, avoid * - * double counting this logical_block by skipping the first (driving) pin. */ - - if (net_output_feeds_driving_block_input[inet] == 0) - ifirst = 0; - else - ifirst = 1; - - if (cur_pb->pb_stats->num_pins_of_net_in_pb.count(inet) == 0) { - for (ipin = ifirst; ipin <= vpack_net[inet].num_sinks; ipin++) { - iblk = vpack_net[inet].node_block[ipin]; - if (logical_block[iblk].clb_index == NO_CLUSTER) { - - if (cur_pb->pb_stats->sharinggain.count(iblk) == 0) { - cur_pb->pb_stats->marked_blocks[cur_pb->pb_stats->num_marked_blocks] = - iblk; - cur_pb->pb_stats->num_marked_blocks++; - cur_pb->pb_stats->sharinggain[iblk] = 1; - cur_pb->pb_stats->hillgain[iblk] = 1 - - num_ext_inputs_logical_block(iblk); - } else { - cur_pb->pb_stats->sharinggain[iblk]++; - cur_pb->pb_stats->hillgain[iblk]++; - } - } - } - } - - if (connection_driven) { - update_connection_gain_values(inet, clustered_block, cur_pb, - net_relation_to_clustered_block); - } - - if (timing_driven) { - update_timing_gain_values(inet, clustered_block, cur_pb, - net_relation_to_clustered_block, slacks); - } - } - if(cur_pb->pb_stats->num_pins_of_net_in_pb.count(inet) == 0) { - cur_pb->pb_stats->num_pins_of_net_in_pb[inet] = 0; - } - cur_pb->pb_stats->num_pins_of_net_in_pb[inet]++; - cur_pb = cur_pb->parent_pb; - } -} - -/*****************************************/ -static void update_total_gain(float alpha, float beta, boolean timing_driven, - boolean connection_driven, boolean global_clocks, t_pb *pb) { - - /*Updates the total gain array to reflect the desired tradeoff between* - *input sharing (sharinggain) and path_length minimization (timinggain)*/ - - int i, iblk, j, k; - t_pb * cur_pb; - int num_input_pins, num_output_pins; - int num_used_input_pins, num_used_output_pins; - t_model_ports *port; - - cur_pb = pb; - while (cur_pb) { - - for (i = 0; i < cur_pb->pb_stats->num_marked_blocks; i++) { - iblk = cur_pb->pb_stats->marked_blocks[i]; - - if(cur_pb->pb_stats->connectiongain.count(iblk) == 0) { - cur_pb->pb_stats->connectiongain[iblk] = 0; - } - if(cur_pb->pb_stats->sharinggain.count(iblk) == 0) { - cur_pb->pb_stats->connectiongain[iblk] = 0; - } - - /* Todo: This was used to explore different normalization options, can be made more efficient once we decide on which one to use*/ - num_input_pins = 0; - port = logical_block[iblk].model->inputs; - j = 0; - num_used_input_pins = 0; - while (port) { - num_input_pins += port->size; - if (!port->is_clock) { - for (k = 0; k < port->size; k++) { - if (logical_block[iblk].input_nets[j][k] != OPEN) { - num_used_input_pins++; - } - } - j++; - } - port = port->next; - } - if (num_input_pins == 0) { - num_input_pins = 1; - } - - num_used_output_pins = 0; - j = 0; - num_output_pins = 0; - port = logical_block[iblk].model->outputs; - while (port) { - num_output_pins += port->size; - for (k = 0; k < port->size; k++) { - if (logical_block[iblk].output_nets[j][k] != OPEN) { - num_used_output_pins++; - } - } - port = port->next; - j++; - } - /* end todo */ - - /* Calculate area-only cost function */ - if (connection_driven) { - /*try to absorb as many connections as possible*/ - /*cur_pb->pb_stats->gain[iblk] = ((1-beta)*(float)cur_pb->pb_stats->sharinggain[iblk] + beta*(float)cur_pb->pb_stats->connectiongain[iblk])/(num_input_pins + num_output_pins);*/ - cur_pb->pb_stats->gain[iblk] = ((1 - beta) - * (float) cur_pb->pb_stats->sharinggain[iblk] - + beta * (float) cur_pb->pb_stats->connectiongain[iblk]) - / (num_used_input_pins + num_used_output_pins); - } else { - /*cur_pb->pb_stats->gain[iblk] = ((float)cur_pb->pb_stats->sharinggain[iblk])/(num_input_pins + num_output_pins); */ - cur_pb->pb_stats->gain[iblk] = - ((float) cur_pb->pb_stats->sharinggain[iblk]) - / (num_used_input_pins + num_used_output_pins); - - } - - /* Add in timing driven cost into cost function */ - if (timing_driven) { - cur_pb->pb_stats->gain[iblk] = alpha - * cur_pb->pb_stats->timinggain[iblk] - + (1.0 - alpha) * (float) cur_pb->pb_stats->gain[iblk]; - } - } - cur_pb = cur_pb->parent_pb; - } -} - -/*****************************************/ -static void update_cluster_stats( INP t_pack_molecule *molecule, - INP int clb_index, INP boolean *is_clock, INP boolean global_clocks, - INP float alpha, INP float beta, INP boolean timing_driven, - INP boolean connection_driven, INP t_slack * slacks) { - - /* Updates cluster stats such as gain, used pins, and clock structures. */ - - int ipin, inet; - int new_blk, molecule_size; - int iblock; - t_model_ports *port; - t_pb *cur_pb, *cb; - - /* TODO: what a scary comment from Vaughn, we'll have to watch out for this causing problems */ - /* Output can be open so the check is necessary. I don't change * - * the gain for clock outputs when clocks are globally distributed * - * because I assume there is no real need to pack similarly clocked * - * FFs together then. Note that by updating the gain when the * - * clock driver is placed in a cluster implies that the output of * - * LUTs can be connected to clock inputs internally. Probably not * - * true, but it doesn't make much difference, since it will still * - * make local routing of this clock very short, and none of my * - * benchmarks actually generate local clocks (all come from pads). */ - - molecule_size = get_array_size_of_molecule(molecule); - cb = NULL; - - for (iblock = 0; iblock < molecule_size; iblock++) { - if (molecule->logical_block_ptrs[iblock] == NULL) { - continue; - } - new_blk = molecule->logical_block_ptrs[iblock]->index; - - logical_block[new_blk].clb_index = clb_index; - - cur_pb = logical_block[new_blk].pb->parent_pb; - while (cur_pb) { - /* reset list of feasible blocks */ - cur_pb->pb_stats->num_feasible_blocks = NOT_VALID; - cur_pb->pb_stats->num_child_blocks_in_pb++; - if (cur_pb->parent_pb == NULL) { - cb = cur_pb; - } - cur_pb = cur_pb->parent_pb; - } - - port = logical_block[new_blk].model->outputs; - while (port) { - for (ipin = 0; ipin < port->size; ipin++) { - inet = logical_block[new_blk].output_nets[port->index][ipin]; /* Output pin first. */ - if (inet != OPEN) { - if (!is_clock[inet] || !global_clocks) - mark_and_update_partial_gain(inet, GAIN, new_blk, - port->index, ipin, timing_driven, - connection_driven, OUTPUT, slacks); - else - mark_and_update_partial_gain(inet, NO_GAIN, new_blk, - port->index, ipin, timing_driven, - connection_driven, OUTPUT, slacks); - } - } - port = port->next; - } - port = logical_block[new_blk].model->inputs; - while (port) { - if (port->is_clock) { - port = port->next; - continue; - } - for (ipin = 0; ipin < port->size; ipin++) { /* VPACK_BLOCK input pins. */ - - inet = logical_block[new_blk].input_nets[port->index][ipin]; - if (inet != OPEN) { - mark_and_update_partial_gain(inet, GAIN, new_blk, - port->index, ipin, timing_driven, connection_driven, - INPUT, slacks); - } - } - port = port->next; - } - - /* Note: The code below ONLY WORKS when nets that go to clock inputs * - * NEVER go to the input of a VPACK_COMB. It doesn't really make electrical * - * sense for that to happen, and I check this in the check_clocks * - * function. Don't disable that sanity check. */ - inet = logical_block[new_blk].clock_net; /* Clock input pin. */ - if (inet != OPEN) { - if (global_clocks) - mark_and_update_partial_gain(inet, NO_GAIN, new_blk, 0, 0, - timing_driven, connection_driven, INPUT, slacks); - else - mark_and_update_partial_gain(inet, GAIN, new_blk, 0, 0, - timing_driven, connection_driven, INPUT, slacks); - - } - - update_total_gain(alpha, beta, timing_driven, connection_driven, - global_clocks, logical_block[new_blk].pb->parent_pb); - - commit_lookahead_pins_used(cb); - } - -} - -static void start_new_cluster( - INP t_cluster_placement_stats *cluster_placement_stats, - INOUTP t_pb_graph_node **primitives_list, INP const t_arch * arch, - INOUTP t_block *new_cluster, INP int clb_index, - INP t_pack_molecule *molecule, INP float aspect, - INOUTP int *num_used_instances_type, INOUTP int *num_instances_type, - INP int num_models, INP int max_cluster_size, - INP int max_nets_in_pb_type, INP int detailed_routing_stage) { - /* Given a starting seed block, start_new_cluster determines the next cluster type to use - It expands the FPGA if it cannot find a legal cluster for the logical block - */ - int i, j; - boolean success; - int count; - - assert(new_cluster->name == NULL); - /* Check if this cluster is really empty */ - - /* Allocate a dummy initial cluster and load a logical block as a seed and check if it is legal */ - new_cluster->name = (char*) my_malloc( - (strlen(molecule->logical_block_ptrs[molecule->root]->name) + 4) * sizeof(char)); - sprintf(new_cluster->name, "cb.%s", - molecule->logical_block_ptrs[molecule->root]->name); - new_cluster->nets = NULL; - new_cluster->type = NULL; - new_cluster->pb = NULL; - new_cluster->x = UNDEFINED; - new_cluster->y = UNDEFINED; - new_cluster->z = UNDEFINED; - - success = FALSE; - - while (!success) { - count = 0; - for (i = 0; i < num_types; i++) { - if (num_used_instances_type[i] < num_instances_type[i]) { - new_cluster->type = &type_descriptors[i]; - if (new_cluster->type == EMPTY_TYPE) { - continue; - } - new_cluster->pb = (t_pb*)my_calloc(1, sizeof(t_pb)); - new_cluster->pb->pb_graph_node = - new_cluster->type->pb_graph_head; - alloc_and_load_pb_stats(new_cluster->pb, num_models, - max_nets_in_pb_type); - new_cluster->pb->parent_pb = NULL; - - alloc_and_load_legalizer_for_cluster(new_cluster, clb_index, - arch); - for (j = 0; - j < new_cluster->type->pb_graph_head->pb_type->num_modes - && !success; j++) { - new_cluster->pb->mode = j; - reset_cluster_placement_stats(&cluster_placement_stats[i]); - set_mode_cluster_placement_stats( - new_cluster->pb->pb_graph_node, j); - success = (boolean) (BLK_PASSED - == try_pack_molecule(&cluster_placement_stats[i], - molecule, primitives_list, new_cluster->pb, - num_models, max_cluster_size, clb_index, - max_nets_in_pb_type, detailed_routing_stage)); - } - if (success) { - /* TODO: For now, just grab any working cluster, in the future, heuristic needed to grab best complex block based on supply and demand */ - break; - } else { - free_legalizer_for_cluster(new_cluster, TRUE); - free_pb_stats(new_cluster->pb); - free(new_cluster->pb); - } - count++; - } - } - if (count == num_types - 1) { - vpr_printf(TIO_MESSAGE_ERROR, "Can not find any logic block that can implement molecule.\n"); - if (molecule->type == MOLECULE_FORCED_PACK) { - vpr_printf(TIO_MESSAGE_ERROR, "\tPattern %s %s\n", - molecule->pack_pattern->name, - molecule->logical_block_ptrs[molecule->root]->name); - } else { - vpr_printf(TIO_MESSAGE_ERROR, "\tAtom %s\n", - molecule->logical_block_ptrs[molecule->root]->name); - } - exit(1); - } - - /* Expand FPGA size and recalculate number of available cluster types*/ - if (!success) { - if (aspect >= 1.0) { - ny++; - nx = nint(ny * aspect); - } else { - nx++; - ny = nint(nx / aspect); - } - vpr_printf(TIO_MESSAGE_INFO, "Not enough resources expand FPGA size to x = %d y = %d.\n", - nx, ny); - if ((nx > MAX_SHORT) || (ny > MAX_SHORT)) { - vpr_printf(TIO_MESSAGE_ERROR, "Circuit cannot pack into architecture, architecture size (nx = %d, ny = %d) exceeds packer range.\n", - nx, ny); - exit(1); - } - alloc_and_load_grid(num_instances_type); - freeGrid(); - } - } - num_used_instances_type[new_cluster->type->index]++; -} - -/*****************************************/ -static t_pack_molecule *get_highest_gain_molecule( - INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, - INP enum e_gain_type gain_mode, - INP t_cluster_placement_stats *cluster_placement_stats_ptr) { - - /* This routine populates a list of feasible blocks outside the cluster then returns the best one for the list * - * not currently in a cluster and satisfies the feasibility * - * function passed in as is_feasible. If there are no feasible * - * blocks it returns NO_CLUSTER. */ - - int i, j, iblk, index, inet, count; - boolean success; - struct s_linked_vptr *cur; - - t_pack_molecule *molecule; - molecule = NULL; - - if (gain_mode == HILL_CLIMBING) { - vpr_printf(TIO_MESSAGE_ERROR, "Hill climbing not supported yet, error out.\n"); - exit(1); - } - - if (cur_pb->pb_stats->num_feasible_blocks == NOT_VALID) { - /* Divide into two cases for speed only. */ - /* Typical case: not too many blocks have been marked. */ - - cur_pb->pb_stats->num_feasible_blocks = 0; - - if (cur_pb->pb_stats->num_marked_blocks < num_logical_blocks / MARKED_FRAC) { - for (i = 0; i < cur_pb->pb_stats->num_marked_blocks; i++) { - iblk = cur_pb->pb_stats->marked_blocks[i]; - if (logical_block[iblk].clb_index == NO_CLUSTER) { - cur = logical_block[iblk].packed_molecules; - while (cur != NULL) { - molecule = (t_pack_molecule *) cur->data_vptr; - if (molecule->valid) { - success = TRUE; - for (j = 0; j < get_array_size_of_molecule(molecule); j++) { - if (molecule->logical_block_ptrs[j] != NULL) { - assert(molecule->logical_block_ptrs[j]->clb_index == NO_CLUSTER); - if (!exists_free_primitive_for_logical_block(cluster_placement_stats_ptr,iblk)) { /* TODO: debating whether to check if placement exists for molecule (more robust) or individual logical blocks (faster) */ - success = FALSE; - break; - } - } - } - if (success) { - add_molecule_to_pb_stats_candidates(molecule, - cur_pb->pb_stats->gain, cur_pb); - } - } - cur = cur->next; - } - } - } - } else { /* Some high fanout nets marked lots of blocks. */ - for (iblk = 0; iblk < num_logical_blocks; iblk++) { - if (logical_block[iblk].clb_index == NO_CLUSTER) { - cur = logical_block[iblk].packed_molecules; - while (cur != NULL) { - molecule = (t_pack_molecule *) cur->data_vptr; - if (molecule->valid) { - success = TRUE; - for (j = 0; j < get_array_size_of_molecule(molecule);j++) { - if (molecule->logical_block_ptrs[j] != NULL) { - assert(molecule->logical_block_ptrs[j]->clb_index == NO_CLUSTER); - if (!exists_free_primitive_for_logical_block( - cluster_placement_stats_ptr, - iblk)) { - success = FALSE; - break; - } - } - } - if (success) { - add_molecule_to_pb_stats_candidates(molecule, cur_pb->pb_stats->gain, cur_pb); - } - } - cur = cur->next; - } - } - } - } - } - if(cur_pb->pb_stats->num_feasible_blocks == 0 && cur_pb->pb_stats->tie_break_high_fanout_net != OPEN) { - /* Because the packer ignores high fanout nets when marking what blocks to consider, use one of the ignored high fanout net to fill up lightly related blocks */ - reset_tried_but_unused_cluster_placements(cluster_placement_stats_ptr); - inet = cur_pb->pb_stats->tie_break_high_fanout_net; - count = 0; - for (i = 0; i <= vpack_net[inet].num_sinks && count < AAPACK_MAX_HIGH_FANOUT_EXPLORE; i++) { - iblk = vpack_net[inet].node_block[i]; - if (logical_block[iblk].clb_index == NO_CLUSTER) { - cur = logical_block[iblk].packed_molecules; - while (cur != NULL) { - molecule = (t_pack_molecule *) cur->data_vptr; - if (molecule->valid) { - success = TRUE; - for (j = 0; - j < get_array_size_of_molecule(molecule); - j++) { - if (molecule->logical_block_ptrs[j] != NULL) { - assert(molecule->logical_block_ptrs[j]->clb_index == NO_CLUSTER); - if (!exists_free_primitive_for_logical_block(cluster_placement_stats_ptr,iblk)) { /* TODO: debating whether to check if placement exists for molecule (more robust) or individual logical blocks (faster) */ - success = FALSE; - break; - } - } - } - if (success) { - add_molecule_to_pb_stats_candidates(molecule, - cur_pb->pb_stats->gain, cur_pb); - count++; - } - } - cur = cur->next; - } - } - } - cur_pb->pb_stats->tie_break_high_fanout_net = OPEN; /* Mark off that this high fanout net has been considered */ - } - molecule = NULL; - for (j = 0; j < cur_pb->pb_stats->num_feasible_blocks; j++) { - if (cur_pb->pb_stats->num_feasible_blocks != 0) { - cur_pb->pb_stats->num_feasible_blocks--; - index = cur_pb->pb_stats->num_feasible_blocks; - molecule = cur_pb->pb_stats->feasible_blocks[index]; - assert(molecule->valid == TRUE); - return molecule; - } - } - - return molecule; -} - -/*****************************************/ -static t_pack_molecule *get_molecule_for_cluster( - INP enum e_packer_algorithm packer_algorithm, INOUTP t_pb *cur_pb, - INP boolean allow_unrelated_clustering, - INOUTP int *num_unrelated_clustering_attempts, - INP t_cluster_placement_stats *cluster_placement_stats_ptr) { - - /* Finds the vpack block with the the greatest gain that satisifies the * - * input, clock and capacity constraints of a cluster that are * - * passed in. If no suitable vpack block is found it returns NO_CLUSTER. - */ - - t_pack_molecule *best_molecule; - - /* If cannot pack into primitive, try packing into cluster */ - - best_molecule = get_highest_gain_molecule(packer_algorithm, cur_pb, - NOT_HILL_CLIMBING, cluster_placement_stats_ptr); - - /* If no blocks have any gain to the current cluster, the code above * - * will not find anything. However, another logical_block with no inputs in * - * common with the cluster may still be inserted into the cluster. */ - - if (allow_unrelated_clustering) { - if (best_molecule == NULL) { - if (*num_unrelated_clustering_attempts == 0) { - best_molecule = get_free_molecule_with_most_ext_inputs_for_cluster( - packer_algorithm, cur_pb, - cluster_placement_stats_ptr); - (*num_unrelated_clustering_attempts)++; - } - } else { - *num_unrelated_clustering_attempts = 0; - } - } - - return best_molecule; -} - -/*****************************************/ -static void alloc_and_load_cluster_info(INP int num_clb, INOUTP t_block *clb) { - - /* Loads all missing clustering info necessary to complete clustering. */ - int i, j, i_clb, node_index, ipin, iclass; - int inport, outport, clockport; - - const t_pb_type * pb_type; - t_pb *pb; - - for (i_clb = 0; i_clb < num_clb; i_clb++) { - rr_node = clb[i_clb].pb->rr_graph; - pb_type = clb[i_clb].pb->pb_graph_node->pb_type; - pb = clb[i_clb].pb; - - clb[i_clb].nets = (int*)my_malloc(clb[i_clb].type->num_pins * sizeof(int)); - for (i = 0; i < clb[i_clb].type->num_pins; i++) { - clb[i_clb].nets[i] = OPEN; - } - - inport = outport = clockport = 0; - ipin = 0; - /* Assume top-level pb and clb share a one-to-one connection */ - for (i = 0; i < pb_type->num_ports; i++) { - if (!pb_type->ports[i].is_clock - && pb_type->ports[i].type == IN_PORT) { - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - iclass = clb[i_clb].type->pin_class[ipin]; - assert(clb[i_clb].type->class_inf[iclass].type == RECEIVER); - assert(clb[i_clb].type->is_global_pin[ipin] == pb->pb_graph_node->input_pins[inport][j].port->is_non_clock_global); - node_index = - pb->pb_graph_node->input_pins[inport][j].pin_count_in_cluster; - clb[i_clb].nets[ipin] = rr_node[node_index].net_num; - ipin++; - } - inport++; - } else if (pb_type->ports[i].type == OUT_PORT) { - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - iclass = clb[i_clb].type->pin_class[ipin]; - assert(clb[i_clb].type->class_inf[iclass].type == DRIVER); - node_index = - pb->pb_graph_node->output_pins[outport][j].pin_count_in_cluster; - clb[i_clb].nets[ipin] = rr_node[node_index].net_num; - ipin++; - } - outport++; - } else { - assert( - pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT); - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - iclass = clb[i_clb].type->pin_class[ipin]; - assert(clb[i_clb].type->class_inf[iclass].type == RECEIVER); - assert(clb[i_clb].type->is_global_pin[ipin]); - node_index = - pb->pb_graph_node->clock_pins[clockport][j].pin_count_in_cluster; - clb[i_clb].nets[ipin] = rr_node[node_index].net_num; - ipin++; - } - clockport++; - } - } - } -} - -/* TODO: Add more error checking, too light */ -/*****************************************/ -static void check_clustering(int num_clb, t_block *clb, boolean *is_clock) { - int i; - t_pb * cur_pb; - boolean * blocks_checked; - - blocks_checked = (boolean*)my_calloc(num_logical_blocks, sizeof(boolean)); - - /* - * Check that each logical block connects to one primitive and that the primitive links up to the parent clb - */ - for (i = 0; i < num_blocks; i++) { - if (logical_block[i].pb->logical_block != i) { - vpr_printf(TIO_MESSAGE_ERROR, "pb %s does not contain logical block %s but logical block %s #%d links to pb.\n", - logical_block[i].pb->name, logical_block[i].name, logical_block[i].name, i); - exit(1); - } - cur_pb = logical_block[i].pb; - assert(strcmp(cur_pb->name, logical_block[i].name) == 0); - while (cur_pb->parent_pb) { - cur_pb = cur_pb->parent_pb; - assert(cur_pb->name); - } - if (cur_pb != clb[num_clb].pb) { - vpr_printf(TIO_MESSAGE_ERROR, "CLB %s does not match CLB contained by pb %s.\n", - cur_pb->name, logical_block[i].pb->name); - exit(1); - } - } - - /* Check that I do not have spurious links in children pbs */ - for (i = 0; i < num_clb; i++) { - check_cluster_logical_blocks(clb[i].pb, blocks_checked); - } - - for (i = 0; i < num_logical_blocks; i++) { - if (blocks_checked[i] == FALSE) { - vpr_printf(TIO_MESSAGE_ERROR, "Logical block %s #%d not found in any cluster.\n", - logical_block[i].name, i); - exit(1); - } - } - - free(blocks_checked); -} - -/* TODO: May want to check that all logical blocks are actually reached (low priority, nice to have) */ -static void check_cluster_logical_blocks(t_pb *pb, boolean *blocks_checked) { - int i, j; - const t_pb_type *pb_type; - boolean has_child; - - has_child = FALSE; - pb_type = pb->pb_graph_node->pb_type; - if (pb_type->num_modes == 0) { - /* primitive */ - if (pb->logical_block != OPEN) { - if (blocks_checked[pb->logical_block] != FALSE) { - vpr_printf(TIO_MESSAGE_ERROR, "pb %s contains logical block %s #%d but logical block is already contained in another pb.\n", - pb->name, logical_block[pb->logical_block].name, pb->logical_block); - exit(1); - } - blocks_checked[pb->logical_block] = TRUE; - if (pb != logical_block[pb->logical_block].pb) { - vpr_printf(TIO_MESSAGE_ERROR, "pb %s contains logical block %s #%d but logical block does not link to pb.\n", - pb->name, logical_block[pb->logical_block].name, pb->logical_block); - exit(1); - } - } - } else { - /* this is a container pb, all container pbs must contain children */ - for (i = 0; i < pb_type->modes[pb->mode].num_pb_type_children; i++) { - for (j = 0; j < pb_type->modes[pb->mode].pb_type_children[i].num_pb; - j++) { - if (pb->child_pbs[i] != NULL) { - if (pb->child_pbs[i][j].name != NULL) { - has_child = TRUE; - check_cluster_logical_blocks(&pb->child_pbs[i][j], - blocks_checked); - } - } - } - } - assert(has_child); - } -} - -static t_pack_molecule* get_most_critical_seed_molecule(int * indexofcrit) { - /* Do_timing_analysis must be called before this, or this function - * will return garbage. Returns molecule with most critical block; - * if block belongs to multiple molecules, return the biggest molecule. */ - - int blkidx; - t_pack_molecule *molecule, *best; - struct s_linked_vptr *cur; - - while (*indexofcrit < num_logical_blocks) { - - blkidx = critindexarray[(*indexofcrit)++]; - - if (logical_block[blkidx].clb_index == NO_CLUSTER) { - cur = logical_block[blkidx].packed_molecules; - best = NULL; - while (cur != NULL) { - molecule = (t_pack_molecule *) cur->data_vptr; - if (molecule->valid) { - if (best == NULL - || (best->base_gain) < (molecule->base_gain)) { - best = molecule; - } - } - cur = cur->next; - } - assert(best != NULL); - return best; - } - } - - /*if it makes it to here , there are no more blocks available*/ - return NULL; -} - -/* get gain of packing molecule into current cluster - gain is equal to total_block_gain + molecule_base_gain*some_factor - introduced_input_nets_of_unrelated_blocks_pulled_in_by_molecule*some_other_factor - - */ -static float get_molecule_gain(t_pack_molecule *molecule, std::map &blk_gain) { - float gain; - int i, ipin, iport, inet, iblk; - int num_introduced_inputs_of_indirectly_related_block; - t_model_ports *cur; - - gain = 0; - num_introduced_inputs_of_indirectly_related_block = 0; - for (i = 0; i < get_array_size_of_molecule(molecule); i++) { - if (molecule->logical_block_ptrs[i] != NULL) { - if(blk_gain.count(molecule->logical_block_ptrs[i]->index) > 0) { - gain += blk_gain[molecule->logical_block_ptrs[i]->index]; - } else { - /* This block has no connection with current cluster, penalize molecule for having this block - */ - cur = molecule->logical_block_ptrs[i]->model->inputs; - iport = 0; - while (cur != NULL) { - if (cur->is_clock != TRUE) { - for (ipin = 0; ipin < cur->size; ipin++) { - inet = molecule->logical_block_ptrs[i]->input_nets[iport][ipin]; - if (inet != OPEN) { - num_introduced_inputs_of_indirectly_related_block++; - for (iblk = 0; iblk < get_array_size_of_molecule(molecule); iblk++) { - if (molecule->logical_block_ptrs[iblk] != NULL - && vpack_net[inet].node_block[0] == molecule->logical_block_ptrs[iblk]->index) { - num_introduced_inputs_of_indirectly_related_block--; - break; - } - } - } - } - iport++; - } - cur = cur->next; - } - } - } - } - - gain += molecule->base_gain * 0.0001; /* Use base gain as tie breaker TODO: need to sweep this value and perhaps normalize */ - gain -= num_introduced_inputs_of_indirectly_related_block * (0.001); - - return gain; -} - -static int compare_molecule_gain(const void *a, const void *b) { - float base_gain_a, base_gain_b, diff; - const t_pack_molecule *molecule_a, *molecule_b; - molecule_a = (*(const t_pack_molecule * const *) a); - molecule_b = (*(const t_pack_molecule * const *) b); - - base_gain_a = molecule_a->base_gain; - base_gain_b = molecule_b->base_gain; - diff = base_gain_a - base_gain_b; - if (diff > 0) { - return 1; - } - if (diff < 0) { - return -1; - } - return 0; -} - -/* Determine if speculatively packed cur_pb is pin feasible - * Runtime is actually not that bad for this. It's worst case O(k^2) where k is the number of pb_graph pins. Can use hash tables or make incremental if becomes an issue. - */ -static void try_update_lookahead_pins_used(t_pb *cur_pb) { - int i, j; - const t_pb_type *pb_type = cur_pb->pb_graph_node->pb_type; - - if (pb_type->num_modes > 0 && cur_pb->name != NULL) { - if (cur_pb->child_pbs != NULL) { - for (i = 0; i < pb_type->modes[cur_pb->mode].num_pb_type_children; - i++) { - if (cur_pb->child_pbs[i] != NULL) { - for (j = 0; - j - < pb_type->modes[cur_pb->mode].pb_type_children[i].num_pb; - j++) { - try_update_lookahead_pins_used( - &cur_pb->child_pbs[i][j]); - } - } - } - } - } else { - if (pb_type->blif_model != NULL && cur_pb->logical_block != OPEN) { - compute_and_mark_lookahead_pins_used(cur_pb->logical_block); - } - } -} - -/* Resets nets used at different pin classes for determining pin feasibility */ -static void reset_lookahead_pins_used(t_pb *cur_pb) { - int i, j; - const t_pb_type *pb_type = cur_pb->pb_graph_node->pb_type; - if (cur_pb->pb_stats == NULL) { - return; /* No pins used, no need to continue */ - } - - if (pb_type->num_modes > 0 && cur_pb->name != NULL) { - for (i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) { - for (j = 0; - j - < cur_pb->pb_graph_node->input_pin_class_size[i] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; - j++) { - cur_pb->pb_stats->lookahead_input_pins_used[i][j] = OPEN; - } - } - - for (i = 0; i < cur_pb->pb_graph_node->num_output_pin_class; i++) { - for (j = 0; - j - < cur_pb->pb_graph_node->output_pin_class_size[i] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; - j++) { - cur_pb->pb_stats->lookahead_output_pins_used[i][j] = OPEN; - } - } - - if (cur_pb->child_pbs != NULL) { - for (i = 0; i < pb_type->modes[cur_pb->mode].num_pb_type_children; - i++) { - if (cur_pb->child_pbs[i] != NULL) { - for (j = 0; - j - < pb_type->modes[cur_pb->mode].pb_type_children[i].num_pb; - j++) { - reset_lookahead_pins_used(&cur_pb->child_pbs[i][j]); - } - } - } - } - } -} - -/* Determine if pins of speculatively packed pb are legal */ -static void compute_and_mark_lookahead_pins_used(int ilogical_block) { - int i, j; - t_pb *cur_pb; - t_pb_graph_node *pb_graph_node; - const t_pb_type *pb_type; - t_port *prim_port; - - int input_port; - int output_port; - int clock_port; - - assert(logical_block[ilogical_block].pb != NULL); - - cur_pb = logical_block[ilogical_block].pb; - pb_graph_node = cur_pb->pb_graph_node; - pb_type = pb_graph_node->pb_type; - - /* Walk through inputs, outputs, and clocks marking pins off of the same class */ - /* TODO: This is inelegant design, I should change the primitive ports in pb_type to be input, output, or clock instead of this lookup */ - input_port = output_port = clock_port = 0; - for (i = 0; i < pb_type->num_ports; i++) { - prim_port = &pb_type->ports[i]; - if (prim_port->is_clock) { - assert(prim_port->type == IN_PORT); - assert(prim_port->num_pins == 1 && clock_port == 0); - /* currently support only one clock for primitives */ - if (logical_block[ilogical_block].clock_net != OPEN) { - compute_and_mark_lookahead_pins_used_for_pin( - &pb_graph_node->clock_pins[0][0], cur_pb, - logical_block[ilogical_block].clock_net); - } - clock_port++; - } else if (prim_port->type == IN_PORT) { - for (j = 0; j < prim_port->num_pins; j++) { - if (logical_block[ilogical_block].input_nets[prim_port->model_port->index][j] - != OPEN) { - compute_and_mark_lookahead_pins_used_for_pin( - &pb_graph_node->input_pins[input_port][j], cur_pb, - logical_block[ilogical_block].input_nets[prim_port->model_port->index][j]); - } - } - input_port++; - } else if (prim_port->type == OUT_PORT) { - for (j = 0; j < prim_port->num_pins; j++) { - if (logical_block[ilogical_block].output_nets[prim_port->model_port->index][j] - != OPEN) { - compute_and_mark_lookahead_pins_used_for_pin( - &pb_graph_node->output_pins[output_port][j], cur_pb, - logical_block[ilogical_block].output_nets[prim_port->model_port->index][j]); - } - } - output_port++; - } else { - assert(0); - } - } -} - -/* Given a pin and its assigned net, mark all pin classes that are affected */ -static void compute_and_mark_lookahead_pins_used_for_pin( - t_pb_graph_pin *pb_graph_pin, t_pb *primitive_pb, int inet) { - int depth, i; - int pin_class, output_port; - t_pb * cur_pb; - t_pb * check_pb; - const t_pb_type *pb_type; - t_port *prim_port; - t_pb_graph_pin *output_pb_graph_pin; - int count; - - boolean skip, found; - - cur_pb = primitive_pb->parent_pb; - - while (cur_pb) { - depth = cur_pb->pb_graph_node->pb_type->depth; - pin_class = pb_graph_pin->parent_pin_class[depth]; - assert(pin_class != OPEN); - - if (pb_graph_pin->port->type == IN_PORT) { - /* find location of net driver if exist in clb, NULL otherwise */ - output_pb_graph_pin = NULL; - if (logical_block[vpack_net[inet].node_block[0]].clb_index - == logical_block[primitive_pb->logical_block].clb_index) { - pb_type = - logical_block[vpack_net[inet].node_block[0]].pb->pb_graph_node->pb_type; - output_port = 0; - found = FALSE; - for (i = 0; i < pb_type->num_ports && !found; i++) { - prim_port = &pb_type->ports[i]; - if (prim_port->type == OUT_PORT) { - if (pb_type->ports[i].model_port->index - == vpack_net[inet].node_block_port[0]) { - found = TRUE; - break; - } - output_port++; - } - } - assert(found); - output_pb_graph_pin = - &(logical_block[vpack_net[inet].node_block[0]].pb->pb_graph_node->output_pins[output_port][vpack_net[inet].node_block_pin[0]]); - } - - skip = FALSE; - - /* check if driving pin for input is contained within the currently investigated cluster, if yes, do nothing since no input needs to be used */ - if (output_pb_graph_pin != NULL) { - check_pb = logical_block[vpack_net[inet].node_block[0]].pb; - while (check_pb != NULL && check_pb != cur_pb) { - check_pb = check_pb->parent_pb; - } - if (check_pb != NULL) { - for (i = 0; - skip == FALSE - && i - < output_pb_graph_pin->num_connectable_primtive_input_pins[depth]; - i++) { - if (pb_graph_pin - == output_pb_graph_pin->list_of_connectable_input_pin_ptrs[depth][i]) { - skip = TRUE; - } - } - } - } - - /* Must use input pin */ - if (!skip) { - /* Check if already in pin class, if yes, skip */ - skip = FALSE; - for (i = 0; - i - < cur_pb->pb_graph_node->input_pin_class_size[pin_class] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; - i++) { - if (cur_pb->pb_stats->lookahead_input_pins_used[pin_class][i] - == inet) { - skip = TRUE; - } - } - if (!skip) { - /* Net must take up a slot */ - for (i = 0; - i - < cur_pb->pb_graph_node->input_pin_class_size[pin_class] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; - i++) { - if (cur_pb->pb_stats->lookahead_input_pins_used[pin_class][i] - == OPEN) { - cur_pb->pb_stats->lookahead_input_pins_used[pin_class][i] = - inet; - break; - } - } - } - } - } else { - assert(pb_graph_pin->port->type == OUT_PORT); - - skip = FALSE; - if (pb_graph_pin->num_connectable_primtive_input_pins[depth] - >= vpack_net[inet].num_sinks) { - /* Important: This runtime penalty looks a lot scarier than it really is. For high fan-out nets, I at most look at the number of pins within the cluster which limits runtime. - DO NOT REMOVE THIS INITIAL FILTER WITHOUT CAREFUL ANALYSIS ON RUNTIME!!! - - Key Observation: - For LUT-based designs it is impossible for the average fanout to exceed the number of LUT inputs so it's usually around 4-5 (pigeon-hole argument, if the average fanout is greater than the - number of LUT inputs, where do the extra connections go? Therefore, average fanout must be capped to a small constant where the constant is equal to the number of LUT inputs). The real danger to runtime - is when the number of sinks of a net gets doubled - - */ - for (i = 1; i <= vpack_net[inet].num_sinks; i++) { - if (logical_block[vpack_net[inet].node_block[i]].clb_index - != logical_block[vpack_net[inet].node_block[0]].clb_index) { - break; - } - } - if (i == vpack_net[inet].num_sinks + 1) { - count = 0; - /* TODO: I should cache the absorbed outputs, once net is absorbed, net is forever absorbed, no point in rechecking every time */ - for (i = 0; - i - < pb_graph_pin->num_connectable_primtive_input_pins[depth]; - i++) { - if (get_net_corresponding_to_pb_graph_pin(cur_pb, - pb_graph_pin->list_of_connectable_input_pin_ptrs[depth][i]) - == inet) { - count++; - } - } - if (count == vpack_net[inet].num_sinks) { - skip = TRUE; - } - } - } - - if (!skip) { - /* This output must exit this cluster */ - for (i = 0; - i - < cur_pb->pb_graph_node->output_pin_class_size[pin_class] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; - i++) { - assert( - cur_pb->pb_stats->lookahead_output_pins_used[pin_class][i] != inet); - if (cur_pb->pb_stats->lookahead_output_pins_used[pin_class][i] - == OPEN) { - cur_pb->pb_stats->lookahead_output_pins_used[pin_class][i] = - inet; - break; - } - } - } - } - - cur_pb = cur_pb->parent_pb; - } -} - -/* Check if the number of available inputs/outputs for a pin class is sufficient for speculatively packed blocks */ -static boolean check_lookahead_pins_used(t_pb *cur_pb) { - int i, j; - int ipin; - const t_pb_type *pb_type = cur_pb->pb_graph_node->pb_type; - boolean success; - - success = TRUE; - - if (pb_type->num_modes > 0 && cur_pb->name != NULL) { - for (i = 0; i < cur_pb->pb_graph_node->num_input_pin_class && success; - i++) { - ipin = 0; - for (j = 0; - j - < cur_pb->pb_graph_node->input_pin_class_size[i] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; - j++) { - if (cur_pb->pb_stats->lookahead_input_pins_used[i][j] != OPEN) { - ipin++; - } - } - if (ipin > cur_pb->pb_graph_node->input_pin_class_size[i]) { - success = FALSE; - } - } - - for (i = 0; i < cur_pb->pb_graph_node->num_output_pin_class && success; - i++) { - ipin = 0; - for (j = 0; - j - < cur_pb->pb_graph_node->output_pin_class_size[i] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; - j++) { - if (cur_pb->pb_stats->lookahead_output_pins_used[i][j] != OPEN) { - ipin++; - } - } - if (ipin > cur_pb->pb_graph_node->output_pin_class_size[i]) { - success = FALSE; - } - } - - if (success && cur_pb->child_pbs != NULL) { - for (i = 0; - success - && i - < pb_type->modes[cur_pb->mode].num_pb_type_children; - i++) { - if (cur_pb->child_pbs[i] != NULL) { - for (j = 0; - success - && j - < pb_type->modes[cur_pb->mode].pb_type_children[i].num_pb; - j++) { - success = check_lookahead_pins_used( - &cur_pb->child_pbs[i][j]); - } - } - } - } - } - return success; -} - -/* Speculation successful, commit input/output pins used */ -static void commit_lookahead_pins_used(t_pb *cur_pb) { - int i, j; - int ipin; - const t_pb_type *pb_type = cur_pb->pb_graph_node->pb_type; - - if (pb_type->num_modes > 0 && cur_pb->name != NULL) { - for (i = 0; i < cur_pb->pb_graph_node->num_input_pin_class; i++) { - ipin = 0; - for (j = 0; - j - < cur_pb->pb_graph_node->input_pin_class_size[i] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; - j++) { - if (cur_pb->pb_stats->lookahead_input_pins_used[i][j] != OPEN) { - cur_pb->pb_stats->input_pins_used[i][ipin] = - cur_pb->pb_stats->lookahead_input_pins_used[i][j]; - ipin++; - } - assert(ipin <= cur_pb->pb_graph_node->input_pin_class_size[i]); - } - } - - for (i = 0; i < cur_pb->pb_graph_node->num_output_pin_class; i++) { - ipin = 0; - for (j = 0; - j - < cur_pb->pb_graph_node->output_pin_class_size[i] - * AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_FAC + AAPACK_MAX_OVERUSE_LOOKAHEAD_PINS_CONST; - j++) { - if (cur_pb->pb_stats->lookahead_output_pins_used[i][j] != OPEN) { - cur_pb->pb_stats->output_pins_used[i][ipin] = - cur_pb->pb_stats->lookahead_output_pins_used[i][j]; - ipin++; - } - assert(ipin <= cur_pb->pb_graph_node->output_pin_class_size[i]); - } - } - - if (cur_pb->child_pbs != NULL) { - for (i = 0; i < pb_type->modes[cur_pb->mode].num_pb_type_children; - i++) { - if (cur_pb->child_pbs[i] != NULL) { - for (j = 0; - j - < pb_type->modes[cur_pb->mode].pb_type_children[i].num_pb; - j++) { - commit_lookahead_pins_used(&cur_pb->child_pbs[i][j]); - } - } - } - } - } -} - -/* determine net at given pin location for cluster, return OPEN if none exists */ -static int get_net_corresponding_to_pb_graph_pin(t_pb *cur_pb, - t_pb_graph_pin *pb_graph_pin) { - t_pb_graph_node *pb_graph_node; - int i; - t_model_ports *model_port; - int ilogical_block; - - if (cur_pb->name == NULL) { - return OPEN; - } - if (cur_pb->pb_graph_node->pb_type->num_modes != 0) { - pb_graph_node = pb_graph_pin->parent_node; - while (pb_graph_node->parent_pb_graph_node->pb_type->depth - > cur_pb->pb_graph_node->pb_type->depth) { - pb_graph_node = pb_graph_node->parent_pb_graph_node; - } - if (pb_graph_node->parent_pb_graph_node == cur_pb->pb_graph_node) { - if (cur_pb->mode != pb_graph_node->pb_type->parent_mode->index) { - return OPEN; - } - for (i = 0; - i - < cur_pb->pb_graph_node->pb_type->modes[cur_pb->mode].num_pb_type_children; - i++) { - if (pb_graph_node - == &cur_pb->pb_graph_node->child_pb_graph_nodes[cur_pb->mode][i][pb_graph_node->placement_index]) { - break; - } - } - assert( - i < cur_pb->pb_graph_node->pb_type->modes[cur_pb->mode].num_pb_type_children); - return get_net_corresponding_to_pb_graph_pin( - &cur_pb->child_pbs[i][pb_graph_node->placement_index], - pb_graph_pin); - } else { - return OPEN; - } - } else { - ilogical_block = cur_pb->logical_block; - if (ilogical_block == OPEN) { - return OPEN; - } else { - model_port = pb_graph_pin->port->model_port; - if (model_port->is_clock) { - assert(model_port->dir == IN_PORT); - return logical_block[ilogical_block].clock_net; - } else if (model_port->dir == IN_PORT) { - return logical_block[ilogical_block].input_nets[model_port->index][pb_graph_pin->pin_number]; - } else { - assert(model_port->dir == OUT_PORT); - return logical_block[ilogical_block].output_nets[model_port->index][pb_graph_pin->pin_number]; - } - } - } -} - -static void print_block_criticalities(const char * fname) { - /* Prints criticality and critindexarray for each logical block to a file. */ - - int iblock, len; - FILE * fp; - char * name; - - fp = my_fopen(fname, "w", 0); - fprintf(fp, "Index \tLogical block name \tCriticality \tCritindexarray\n\n"); - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - name = logical_block[iblock].name; - len = strlen(name); - fprintf(fp, "%d\t%s\t", logical_block[iblock].index, name); - if (len < 8) { - fprintf(fp, "\t\t"); - } else if (len < 16) { - fprintf(fp, "\t"); - } - fprintf(fp, "%f\t%d\n", block_criticality[iblock], critindexarray[iblock]); - } - fclose(fp); -} diff --git a/vpr7_x2p/vpr/SRC/pack/cluster.h b/vpr7_x2p/vpr/SRC/pack/cluster.h deleted file mode 100644 index c717040f6..000000000 --- a/vpr7_x2p/vpr/SRC/pack/cluster.h +++ /dev/null @@ -1,10 +0,0 @@ -void do_clustering(const t_arch *arch, t_pack_molecule *molecule_head, - int num_models, boolean global_clocks, boolean *is_clock, - boolean hill_climbing_flag, char *out_fname, boolean timing_driven, - enum e_cluster_seed cluster_seed_type, float alpha, float beta, - int recompute_timing_after, float block_delay, - float intra_cluster_net_delay, float inter_cluster_net_delay, - float aspect, boolean allow_unrelated_clustering, - boolean allow_early_exit, boolean connection_driven, - enum e_packer_algorithm packer_algorithm, t_timing_inf timing_inf); -int get_cluster_of_block(int blkidx); diff --git a/vpr7_x2p/vpr/SRC/pack/cluster_feasibility_filter.c b/vpr7_x2p/vpr/SRC/pack/cluster_feasibility_filter.c deleted file mode 100644 index 3510df5ca..000000000 --- a/vpr7_x2p/vpr/SRC/pack/cluster_feasibility_filter.c +++ /dev/null @@ -1,590 +0,0 @@ -/* - Feasibility filter used during packing that determines if various necessary conditions for legality are met - - Important for 2 reasons: - 1) Quickly reject cases that are bad so that we don't waste time exploring useless cases in packing - 2) Robustness issue. During packing, we have a limited size queue to store candidates to try to pack. A good filter helps keep that queue filled with candidates likely to pass. - - 1st major filter: Pin counting based on pin classes - Rationale: If the number of a particular gruop of pins supplied by the pb_graph_node in the architecture is insufficient to meet a candidate packing solution's demand for that group of pins, then that - candidate solution is for sure invalid without any further legalization checks. For example, if a candidate solution requires 2 clock pins but the architecture only has one clock, then that solution - can't be legal. - - Implementation details: - a) Definition of a pin class - If there exists a path (ignoring directionality of connections) from pin A to pin B and pin A and pin B are of the same type (input, output, or clock), then pin A and pin B are in the same pin class. Otherwise, pin A and pin B are in different pin classes. - b) Code Identifies pin classes. Given a candidate solution - - TODO: May 30, 2012 Jason Luu - Must take into consideration modes when doing pin counting. For fracturable LUTs FI = 5, the soft logic block sees 6 pins instead of 5 pins for the dual LUT mode messing up the pin counter. The packer still produces correct results but runs slower than its best (experiment on a modified architecture file that forces correct pin counting shows 40x speedup vs VPR 6.0 as opposed to 3x speedup at the time) - - Author: Jason Luu - Date: May 16, 2012 - - - */ -#include - -#include "read_xml_arch_file.h" -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "hash.h" -#include "cluster_feasibility_filter.h" -#include "vpr_utils.h" -#include "ReadOptions.h" - -/* header functions that identify pin classes */ -static void alloc_pin_classes_in_pb_graph_node( - INOUTP t_pb_graph_node *pb_graph_node); -static int get_max_depth_of_pb_graph_node(INP t_pb_graph_node *pb_graph_node); -static void load_pin_class_by_depth(INOUTP t_pb_graph_node *pb_graph_node, - INP int depth, OUTP int *input_count, OUTP int *output_count); -static void load_list_of_connectable_input_pin_ptrs( - INOUTP t_pb_graph_node *pb_graph_node); -static void expand_pb_graph_node_and_load_output_to_input_connections( - INOUTP t_pb_graph_pin *current_pb_graph_pin, - INOUTP t_pb_graph_pin *reference_pin, INP int depth); -static void unmark_fanout_intermediate_nodes( - INOUTP t_pb_graph_pin *current_pb_graph_pin); -static void reset_pin_class_scratch_pad_rec( - INOUTP t_pb_graph_node *pb_graph_node); -static void expand_pb_graph_node_and_load_pin_class_by_depth( - INOUTP t_pb_graph_pin *current_pb_graph_pin, - INP t_pb_graph_pin *reference_pb_graph_pin, INP int depth, - OUTP int *input_count, OUTP int *output_count); -static void sum_pin_class(INOUTP t_pb_graph_node *pb_graph_node); - -static void discover_all_forced_connections(INOUTP t_pb_graph_node *pb_graph_node); -static boolean is_forced_connection(INP t_pb_graph_pin *pb_graph_pin); - - -/* Identify all pin class information for complex block - */ -void load_pin_classes_in_pb_graph_head(INOUTP t_pb_graph_node *pb_graph_node) { - int i, depth, input_count, output_count; - - /* Allocate memory for primitives */ - alloc_pin_classes_in_pb_graph_node(pb_graph_node); - - /* Load pin classes */ - depth = get_max_depth_of_pb_graph_node(pb_graph_node); - for (i = 0; i < depth; i++) { - input_count = output_count = 0; - reset_pin_class_scratch_pad_rec(pb_graph_node); - load_pin_class_by_depth(pb_graph_node, i, &input_count, &output_count); - } - - /* Load internal output-to-input connections within each cluster */ - reset_pin_class_scratch_pad_rec(pb_graph_node); - load_list_of_connectable_input_pin_ptrs(pb_graph_node); - discover_all_forced_connections(pb_graph_node); -} - -/** - * Recursive function to allocate memory space for pin classes in primitives - */ -static void alloc_pin_classes_in_pb_graph_node( - INOUTP t_pb_graph_node *pb_graph_node) { - int i, j, k; - - /* If primitive, allocate space, else go to primitive */ - if (pb_graph_node->pb_type->num_modes == 0) { - /* allocate space */ - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - pb_graph_node->input_pins[i][j].parent_pin_class = - (int *) my_calloc(pb_graph_node->pb_type->depth, - sizeof(int*)); - for (k = 0; k < pb_graph_node->pb_type->depth; k++) { - pb_graph_node->input_pins[i][j].parent_pin_class[k] = OPEN; - } - } - } - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - pb_graph_node->output_pins[i][j].parent_pin_class = - (int *) my_calloc(pb_graph_node->pb_type->depth, - sizeof(int*)); - pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs = - (t_pb_graph_pin ***) my_calloc( - pb_graph_node->pb_type->depth, - sizeof(t_pb_graph_pin**)); - pb_graph_node->output_pins[i][j].num_connectable_primtive_input_pins = - (int*) my_calloc(pb_graph_node->pb_type->depth, - sizeof(int)); - for (k = 0; k < pb_graph_node->pb_type->depth; k++) { - pb_graph_node->output_pins[i][j].parent_pin_class[k] = OPEN; - } - } - } - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - pb_graph_node->clock_pins[i][j].parent_pin_class = - (int *) my_calloc(pb_graph_node->pb_type->depth, - sizeof(int*)); - for (k = 0; k < pb_graph_node->pb_type->depth; k++) { - pb_graph_node->clock_pins[i][j].parent_pin_class[k] = OPEN; - } - } - } - } else { - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; - j < pb_graph_node->pb_type->modes[i].num_pb_type_children; - j++) { - for (k = 0; - k - < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - alloc_pin_classes_in_pb_graph_node( - &pb_graph_node->child_pb_graph_nodes[i][j][k]); - } - } - } - } -} - -/* determine maximum depth of pb_graph_node */ -static int get_max_depth_of_pb_graph_node(INP t_pb_graph_node *pb_graph_node) { - int i, j, k; - int max_depth, depth; - - max_depth = 0; - - /* If primitive, allocate space, else go to primitive */ - if (pb_graph_node->pb_type->num_modes == 0) { - return pb_graph_node->pb_type->depth; - } else { - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; - j < pb_graph_node->pb_type->modes[i].num_pb_type_children; - j++) { - for (k = 0; - k - < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - depth = get_max_depth_of_pb_graph_node( - &pb_graph_node->child_pb_graph_nodes[i][j][k]); - if (depth > max_depth) { - max_depth = depth; - } - } - } - } - } - - return max_depth; -} - -static void reset_pin_class_scratch_pad_rec( - INOUTP t_pb_graph_node *pb_graph_node) { - int i, j, k; - - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - pb_graph_node->input_pins[i][j].scratch_pad = OPEN; - } - } - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - pb_graph_node->output_pins[i][j].scratch_pad = OPEN; - } - } - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - pb_graph_node->clock_pins[i][j].scratch_pad = OPEN; - } - } - - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; - j++) { - for (k = 0; - k - < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - reset_pin_class_scratch_pad_rec( - &pb_graph_node->child_pb_graph_nodes[i][j][k]); - } - } - } -} - -/* load pin class based on limited depth */ -static void load_pin_class_by_depth(INOUTP t_pb_graph_node *pb_graph_node, - INP int depth, OUTP int *input_count, OUTP int *output_count) { - int i, j, k; - - if (pb_graph_node->pb_type->num_modes == 0) { - if (pb_graph_node->pb_type->depth > depth) { - /* At primitive, determine which pin class each of its pins belong to */ - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - if (pb_graph_node->input_pins[i][j].parent_pin_class[depth] - == OPEN) { - expand_pb_graph_node_and_load_pin_class_by_depth( - &pb_graph_node->input_pins[i][j], - &pb_graph_node->input_pins[i][j], depth, - input_count, output_count); - (*input_count)++; - } - } - } - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - if (pb_graph_node->output_pins[i][j].parent_pin_class[depth] - == OPEN) { - expand_pb_graph_node_and_load_pin_class_by_depth( - &pb_graph_node->output_pins[i][j], - &pb_graph_node->output_pins[i][j], depth, - input_count, output_count); - (*output_count)++; - } - } - } - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - if (pb_graph_node->clock_pins[i][j].parent_pin_class[depth] - == OPEN) { - expand_pb_graph_node_and_load_pin_class_by_depth( - &pb_graph_node->clock_pins[i][j], - &pb_graph_node->clock_pins[i][j], depth, - input_count, output_count); - (*input_count)++; - } - } - } - } - } - - if (pb_graph_node->pb_type->depth == depth) { - /* Load pin classes for all pb_graph_nodes of this depth, therefore, at a particular pb_graph_node of this depth, set # of pin classes to be 0 */ - *input_count = 0; - *output_count = 0; - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - pb_graph_node->input_pins[i][j].pin_class = OPEN; - } - } - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - pb_graph_node->output_pins[i][j].pin_class = OPEN; - } - } - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - pb_graph_node->clock_pins[i][j].pin_class = OPEN; - } - } - } - - /* Expand down to primitives */ - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; - j++) { - for (k = 0; - k - < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - load_pin_class_by_depth( - &pb_graph_node->child_pb_graph_nodes[i][j][k], depth, - input_count, output_count); - } - } - } - - if (pb_graph_node->pb_type->depth == depth - && pb_graph_node->pb_type->num_modes != 0) { - /* Record pin class information for cluster */ - pb_graph_node->num_input_pin_class = *input_count + 1; /* number of input pin classes discovered + 1 for primitive inputs not reachable from cluster input pins */ - pb_graph_node->input_pin_class_size = (int*) my_calloc(*input_count + 1, - sizeof(int)); - pb_graph_node->num_output_pin_class = *output_count + 1; /* number of output pin classes discovered + 1 for primitive inputs not reachable from cluster input pins */ - pb_graph_node->output_pin_class_size = (int*) my_calloc(*output_count + 1, - sizeof(int)); - sum_pin_class(pb_graph_node); - } - -} - -/** - * Load internal output-to-input connections within each cluster - */ -static void load_list_of_connectable_input_pin_ptrs( - INOUTP t_pb_graph_node *pb_graph_node) { - int i, j, k; - - if (pb_graph_node->pb_type->num_modes == 0) { - /* If this is a primitive, discover what input pins the output pins can connect to */ - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - for (k = 0; k < pb_graph_node->pb_type->depth; k++) { - expand_pb_graph_node_and_load_output_to_input_connections( - &pb_graph_node->output_pins[i][j], - &pb_graph_node->output_pins[i][j], k); - unmark_fanout_intermediate_nodes( - &pb_graph_node->output_pins[i][j]); - } - } - } - } - /* Expand down to primitives */ - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; - j++) { - for (k = 0;k < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - load_list_of_connectable_input_pin_ptrs( - &pb_graph_node->child_pb_graph_nodes[i][j][k]); - } - } - } -} - -/* Traverse outputs of output pin or primitive to see what input pins it reaches - Record list of input pins based on depth - */ -static void expand_pb_graph_node_and_load_output_to_input_connections( - INOUTP t_pb_graph_pin *current_pb_graph_pin, - INOUTP t_pb_graph_pin *reference_pin, INP int depth) { - int i; - - if (current_pb_graph_pin->scratch_pad == OPEN - && current_pb_graph_pin->parent_node->pb_type->depth > depth) { - current_pb_graph_pin->scratch_pad = 1; - for (i = 0; i < current_pb_graph_pin->num_output_edges; i++) { - assert(current_pb_graph_pin->output_edges[i]->num_output_pins == 1); - expand_pb_graph_node_and_load_output_to_input_connections( - current_pb_graph_pin->output_edges[i]->output_pins[0], - reference_pin, depth); - } - if (current_pb_graph_pin->parent_node->pb_type->num_modes == 0 - && current_pb_graph_pin->port->type == IN_PORT) { - reference_pin->num_connectable_primtive_input_pins[depth]++; - reference_pin->list_of_connectable_input_pin_ptrs[depth] = - (t_pb_graph_pin**) my_realloc( - reference_pin->list_of_connectable_input_pin_ptrs[depth], - reference_pin->num_connectable_primtive_input_pins[depth] - * sizeof(t_pb_graph_pin*)); - reference_pin->list_of_connectable_input_pin_ptrs[depth][reference_pin->num_connectable_primtive_input_pins[depth] - - 1] = current_pb_graph_pin; - } - } -} - -/** - * Clear scratch_pad for all fanout of pin - */ -static void unmark_fanout_intermediate_nodes( - INOUTP t_pb_graph_pin *current_pb_graph_pin) { - int i; - if (current_pb_graph_pin->scratch_pad != OPEN) { - current_pb_graph_pin->scratch_pad = OPEN; - for (i = 0; i < current_pb_graph_pin->num_output_edges; i++) { - assert(current_pb_graph_pin->output_edges[i]->num_output_pins == 1); - unmark_fanout_intermediate_nodes( - current_pb_graph_pin->output_edges[i]->output_pins[0]); - } - } -} - -/** - * Determine other primitive pins that belong to the same pin class as reference pin - */ -static void expand_pb_graph_node_and_load_pin_class_by_depth( - INOUTP t_pb_graph_pin *current_pb_graph_pin, - INP t_pb_graph_pin *reference_pb_graph_pin, INP int depth, - OUTP int *input_count, OUTP int *output_count) { - int i; - int marker; - int active_pin_class; - - if (reference_pb_graph_pin->port->type == IN_PORT) { - marker = *input_count + 10; - active_pin_class = *input_count; - } else { - marker = -10 - *output_count; - active_pin_class = *output_count; - } - assert(reference_pb_graph_pin->parent_node->pb_type->num_modes == 0); - assert(current_pb_graph_pin->parent_node->pb_type->depth >= depth); - assert(current_pb_graph_pin->port->type != INOUT_PORT); - if (current_pb_graph_pin->scratch_pad != marker) { - if (current_pb_graph_pin->parent_node->pb_type->num_modes == 0) { - current_pb_graph_pin->scratch_pad = marker; - /* This is a primitive, determine what pins cans share the same pin class as the reference pin */ - if (current_pb_graph_pin->parent_pin_class[depth] == OPEN - && reference_pb_graph_pin->port->is_clock - == current_pb_graph_pin->port->is_clock - && reference_pb_graph_pin->port->type - == current_pb_graph_pin->port->type) { - current_pb_graph_pin->parent_pin_class[depth] = - active_pin_class; - } - for (i = 0; i < current_pb_graph_pin->num_input_edges; i++) { - assert( - current_pb_graph_pin->input_edges[i]->num_input_pins == 1); - expand_pb_graph_node_and_load_pin_class_by_depth( - current_pb_graph_pin->input_edges[i]->input_pins[0], - reference_pb_graph_pin, depth, input_count, - output_count); - } - for (i = 0; i < current_pb_graph_pin->num_output_edges; i++) { - assert( - current_pb_graph_pin->output_edges[i]->num_output_pins == 1); - expand_pb_graph_node_and_load_pin_class_by_depth( - current_pb_graph_pin->output_edges[i]->output_pins[0], - reference_pb_graph_pin, depth, input_count, - output_count); - } - } else if (current_pb_graph_pin->parent_node->pb_type->depth == depth) { - current_pb_graph_pin->scratch_pad = marker; - if (current_pb_graph_pin->port->type == OUT_PORT) { - if (reference_pb_graph_pin->port->type == OUT_PORT) { - /* This cluster's output pin can be driven by primitive outputs belonging to this pin class */ - current_pb_graph_pin->pin_class = active_pin_class; - } - for (i = 0; i < current_pb_graph_pin->num_input_edges; i++) { - assert( - current_pb_graph_pin->input_edges[i]->num_input_pins == 1); - expand_pb_graph_node_and_load_pin_class_by_depth( - current_pb_graph_pin->input_edges[i]->input_pins[0], - reference_pb_graph_pin, depth, input_count, - output_count); - } - } - if (current_pb_graph_pin->port->type == IN_PORT) { - if (reference_pb_graph_pin->port->type == IN_PORT) { - /* This cluster's input pin can drive the primitive input pins belonging to this pin class */ - current_pb_graph_pin->pin_class = active_pin_class; - } - for (i = 0; i < current_pb_graph_pin->num_output_edges; i++) { - assert( - current_pb_graph_pin->output_edges[i]->num_output_pins == 1); - expand_pb_graph_node_and_load_pin_class_by_depth( - current_pb_graph_pin->output_edges[i]->output_pins[0], - reference_pb_graph_pin, depth, input_count, - output_count); - } - } - } else if (current_pb_graph_pin->parent_node->pb_type->depth > depth) { - /* Inside an intermediate cluster, traverse to either a primitive or to the cluster we're interested in populating */ - current_pb_graph_pin->scratch_pad = marker; - for (i = 0; i < current_pb_graph_pin->num_input_edges; i++) { - assert( - current_pb_graph_pin->input_edges[i]->num_input_pins == 1); - expand_pb_graph_node_and_load_pin_class_by_depth( - current_pb_graph_pin->input_edges[i]->input_pins[0], - reference_pb_graph_pin, depth, input_count, - output_count); - } - for (i = 0; i < current_pb_graph_pin->num_output_edges; i++) { - assert( - current_pb_graph_pin->output_edges[i]->num_output_pins == 1); - expand_pb_graph_node_and_load_pin_class_by_depth( - current_pb_graph_pin->output_edges[i]->output_pins[0], - reference_pb_graph_pin, depth, input_count, - output_count); - } - } - } -} - -/* count up pin classes of the same number for the given cluster */ -static void sum_pin_class(INOUTP t_pb_graph_node *pb_graph_node) { - int i, j; - - /* This is a primitive, for each pin in primitive, sum appropriate pin class */ - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - assert( - pb_graph_node->input_pins[i][j].pin_class < pb_graph_node->num_input_pin_class); - if (pb_graph_node->input_pins[i][j].pin_class == OPEN) { - vpr_printf(TIO_MESSAGE_WARNING, "%s[%d].%s[%d] unconnected pin in architecture.\n", - pb_graph_node->pb_type->name, - pb_graph_node->placement_index, - pb_graph_node->input_pins[i][j].port->name, - pb_graph_node->input_pins[i][j].pin_number); - continue; - } - pb_graph_node->input_pin_class_size[pb_graph_node->input_pins[i][j].pin_class]++; - } - } - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - assert( - pb_graph_node->output_pins[i][j].pin_class < pb_graph_node->num_output_pin_class); - if (pb_graph_node->output_pins[i][j].pin_class == OPEN) { - vpr_printf(TIO_MESSAGE_WARNING, "%s[%d].%s[%d] unconnected pin in architecture.\n", - pb_graph_node->pb_type->name, - pb_graph_node->placement_index, - pb_graph_node->output_pins[i][j].port->name, - pb_graph_node->output_pins[i][j].pin_number); - continue; - } - pb_graph_node->output_pin_class_size[pb_graph_node->output_pins[i][j].pin_class]++; - } - } - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - assert( - pb_graph_node->clock_pins[i][j].pin_class < pb_graph_node->num_input_pin_class); - if (pb_graph_node->clock_pins[i][j].pin_class == OPEN) { - vpr_printf(TIO_MESSAGE_WARNING, "%s[%d].%s[%d] unconnected pin in architecture.\n", - pb_graph_node->pb_type->name, - pb_graph_node->placement_index, - pb_graph_node->clock_pins[i][j].port->name, - pb_graph_node->clock_pins[i][j].pin_number); - continue; - } - pb_graph_node->input_pin_class_size[pb_graph_node->clock_pins[i][j].pin_class]++; - } - } -} - -/* Recursively visit all pb_graph_pins and determine primitive output pins that connect to nothing else than one primitive input pin. If a net maps to this output pin, then the primitive corresponding to that input must be used */ -static void discover_all_forced_connections(INOUTP t_pb_graph_node *pb_graph_node) { - int i, j, k; - - /* If primitive, allocate space, else go to primitive */ - if (pb_graph_node->pb_type->num_modes == 0) { - for(i = 0; i < pb_graph_node->num_output_ports; i++) { - for(j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - pb_graph_node->output_pins[i][j].is_forced_connection = is_forced_connection(&pb_graph_node->output_pins[i][j]); - } - } - } else { - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; - j < pb_graph_node->pb_type->modes[i].num_pb_type_children; - j++) { - for (k = 0; - k < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - discover_all_forced_connections(&pb_graph_node->child_pb_graph_nodes[i][j][k]); - } - } - } - } -} - -/** - * Given an output pin, determine if it connects to only one input pin and nothing else. - */ -static boolean is_forced_connection(INP t_pb_graph_pin *pb_graph_pin) { - if(pb_graph_pin->num_output_edges > 1) { - return FALSE; - } - if(pb_graph_pin->num_output_edges == 0) { - if(pb_graph_pin->parent_node->pb_type->num_modes == 0) { - /* Check that this pin belongs to a primitive */ - return TRUE; - } else { - return FALSE; - } - } - return is_forced_connection(pb_graph_pin->output_edges[0]->output_pins[0]); -} - - - - diff --git a/vpr7_x2p/vpr/SRC/pack/cluster_feasibility_filter.h b/vpr7_x2p/vpr/SRC/pack/cluster_feasibility_filter.h deleted file mode 100644 index 095df09e0..000000000 --- a/vpr7_x2p/vpr/SRC/pack/cluster_feasibility_filter.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - Feasibility filter used during packing that determines if various necessary conditions for legality are met - - Important for 2 reasons: - 1) Quickly reject cases that are bad so that we don't waste time exploring useless cases in packing - 2) Robustness issue. During packing, we have a limited size queue to store candidates to try to pack. A good filter helps keep that queue filled with candidates likely to pass. - - 1st major filter: Pin counting based on pin classes - Rationale: If the number of a particular gruop of pins supplied by the pb_graph_node in the architecture is insufficient to meet a candidate packing solution's demand for that group of pins, then that - candidate solution is for sure invalid without any further legalization checks. For example, if a candidate solution requires 2 clock pins but the architecture only has one clock, then that solution - can't be legal. - - Implementation details: - a) Definition of a pin class - If there exists a path (ignoring directionality of connections) from pin A to pin B and pin A and pin B are of the same type (input, output, or clock), then pin A and pin B are in the same pin class. Otherwise, pin A and pin B are in different pin classes. - b) Code Identifies pin classes. Given a candidate solution - - Author: Jason Luu - Date: May 16, 2012 - - */ - -#ifndef CLUSTER_FEASIBILITY_CHECK_H -#define CLUSTER_FEASIBILITY_CHECK_H -#include "arch_types.h" -#include "util.h" - -void load_pin_classes_in_pb_graph_head(INOUTP t_pb_graph_node *pb_graph_node); - -#endif diff --git a/vpr7_x2p/vpr/SRC/pack/cluster_legality.c b/vpr7_x2p/vpr/SRC/pack/cluster_legality.c deleted file mode 100755 index df85e0c10..000000000 --- a/vpr7_x2p/vpr/SRC/pack/cluster_legality.c +++ /dev/null @@ -1,1318 +0,0 @@ -#include -#include -#include -#include - -#include "util.h" -#include "physical_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "route_export.h" -#include "route_common.h" -#include "cluster_legality.h" -#include "cluster_placement.h" -#include "rr_graph.h" - -static t_chunk rr_mem_ch = {NULL, 0, NULL}; - -/*static struct s_linked_vptr *rr_mem_chunk_list_head = NULL; -static int chunk_bytes_avail = 0; -static char *chunk_next_avail_mem = NULL;*/ -static struct s_trace **best_routing; - -/* nets_in_cluster: array of all nets contained in the cluster */ -static int *nets_in_cluster; /* [0..num_nets_in_cluster-1] */ -static int num_nets_in_cluster; -static int saved_num_nets_in_cluster; -static int curr_cluster_index; - -static int ext_input_rr_node_index, ext_output_rr_node_index, - ext_clock_rr_node_index, max_ext_index; -static int **saved_net_rr_terminals; -static float pres_fac; - -/********************* Subroutines local to this module *********************/ -static boolean is_net_in_cluster(INP int inet); - -static void add_net_rr_terminal_cluster(int iblk_net, - t_pb_graph_node * primitive, int ilogical_block, - t_model_ports * model_port, int ipin); - -static boolean breadth_first_route_net_cluster(int inet); - -static void breadth_first_expand_trace_segment_cluster( - struct s_trace *start_ptr, int remaining_connections_to_sink); - -static void breadth_first_expand_neighbours_cluster(int inode, float pcost, - int inet, boolean first_time); - -static void breadth_first_add_source_to_heap_cluster(int inet); - -static void alloc_net_rr_terminals_cluster(void); - -static void mark_ends_cluster(int inet); - -static float rr_node_intrinsic_cost(int inode); - -/************************ Subroutine definitions ****************************/ - -static boolean is_net_in_cluster(INP int inet) { - int i; - for (i = 0; i < num_nets_in_cluster; i++) { - if (nets_in_cluster[i] == inet) { - return TRUE; - } - } - return FALSE; -} - -/* load rr_node for source and sinks of net if exists, return FALSE otherwise */ -/* Todo: Note this is an inefficient way to determine port, better to use a lookup, worry about this if runtime becomes an issue */ -static void add_net_rr_terminal_cluster(int iblk_net, - t_pb_graph_node * primitive, int ilogical_block, - t_model_ports * model_port, int ipin) { - /* Ensure at most one external input/clock source and one external output sink for net */ - int i, net_pin; - t_port *prim_port; - const t_pb_type *pb_type; - boolean found; - - int input_port; - int output_port; - int clock_port; - - input_port = output_port = clock_port = 0; - - pb_type = primitive->pb_type; - prim_port = NULL; - - assert(pb_type->num_modes == 0); - - found = FALSE; - /* TODO: This is inelegant design, I should change the primitive ports in pb_type to be input, output, or clock instead of this lookup */ - for (i = 0; i < pb_type->num_ports && !found; i++) { - prim_port = &pb_type->ports[i]; - if (pb_type->ports[i].model_port == model_port) { - found = TRUE; - } else { - if (prim_port->is_clock) { - clock_port++; - assert(prim_port->type == IN_PORT); - } else if (prim_port->type == IN_PORT) { - input_port++; - } else if (prim_port->type == OUT_PORT) { - output_port++; - } else { - assert(0); - } - } - } - assert(found); - assert(ipin < prim_port->num_pins); - net_pin = OPEN; - if (prim_port->is_clock) { - for (i = 1; i <= vpack_net[iblk_net].num_sinks; i++) { - if (vpack_net[iblk_net].node_block[i] == ilogical_block - && vpack_net[iblk_net].node_block_port[i] - == model_port->index - && vpack_net[iblk_net].node_block_pin[i] == ipin) { - net_pin = i; - break; - } - } - assert(net_pin != OPEN); - assert(rr_node[primitive->clock_pins[clock_port][ipin].pin_count_in_cluster].num_edges == 1); - net_rr_terminals[iblk_net][net_pin] = rr_node[primitive->clock_pins[clock_port][ipin].pin_count_in_cluster].edges[0]; - } else if (prim_port->type == IN_PORT) { - for (i = 1; i <= vpack_net[iblk_net].num_sinks; i++) { - if (vpack_net[iblk_net].node_block[i] == ilogical_block - && vpack_net[iblk_net].node_block_port[i] - == model_port->index - && vpack_net[iblk_net].node_block_pin[i] == ipin) { - net_pin = i; - break; - } - } - assert(net_pin != OPEN); - assert(rr_node[primitive->input_pins[input_port][ipin].pin_count_in_cluster].num_edges == 1); - net_rr_terminals[iblk_net][net_pin] = rr_node[primitive->input_pins[input_port][ipin].pin_count_in_cluster].edges[0]; - } else if (prim_port->type == OUT_PORT) { - i = 0; - if (vpack_net[iblk_net].node_block[i] == ilogical_block - && vpack_net[iblk_net].node_block_port[i] == model_port->index - && vpack_net[iblk_net].node_block_pin[i] == ipin) { - net_pin = i; - } - assert(net_pin != OPEN); - net_rr_terminals[iblk_net][net_pin] = - primitive->output_pins[output_port][ipin].pin_count_in_cluster; - } else { - assert(0); - } -} - -void reload_ext_net_rr_terminal_cluster(void) { - int i, j, net_index; - boolean has_ext_sink, has_ext_source; - int curr_ext_output, curr_ext_input, curr_ext_clock; - - curr_ext_input = ext_input_rr_node_index; - curr_ext_output = ext_output_rr_node_index; - curr_ext_clock = ext_clock_rr_node_index; - - for (i = 0; i < num_nets_in_cluster; i++) { - net_index = nets_in_cluster[i]; - has_ext_sink = FALSE; - has_ext_source = (boolean) - (logical_block[vpack_net[net_index].node_block[0]].clb_index - != curr_cluster_index); - if (has_ext_source) { - /* Instantiate a source of this net */ - if (vpack_net[net_index].is_global) { - net_rr_terminals[net_index][0] = curr_ext_clock; - curr_ext_clock++; - } else { - net_rr_terminals[net_index][0] = curr_ext_input; - curr_ext_input++; - } - } - for (j = 1; j <= vpack_net[net_index].num_sinks; j++) { - if (logical_block[vpack_net[net_index].node_block[j]].clb_index - != curr_cluster_index) { - if (has_ext_sink || has_ext_source) { - /* Only need one node driving external routing, either this cluster drives external routing or another cluster does it */ - net_rr_terminals[net_index][j] = OPEN; - } else { - /* External sink, only need to route once, externally routing will take care of the rest */ - net_rr_terminals[net_index][j] = curr_ext_output; - curr_ext_output++; - has_ext_sink = TRUE; - } - } - } - - if (curr_ext_input > ext_output_rr_node_index - || curr_ext_output > ext_clock_rr_node_index - || curr_ext_clock > max_ext_index) { - /* failed, not enough pins of proper type, overran index */ - assert(0); - } - } -} - -void alloc_and_load_cluster_legality_checker(void) { - best_routing = (struct s_trace **) my_calloc(num_logical_nets, - sizeof(struct s_trace *)); - nets_in_cluster = (int *) my_malloc(num_logical_nets * sizeof(int)); - num_nets_in_cluster = 0; - num_nets = num_logical_nets; - - /* inside a cluster, I do not consider rr_indexed_data cost, set to 1 since other costs are multiplied by it */ - num_rr_indexed_data = 1; - rr_indexed_data = (t_rr_indexed_data *) my_calloc(1, sizeof(t_rr_indexed_data)); - rr_indexed_data[0].base_cost = 1; - - /* alloc routing structures */ - alloc_route_static_structs(); - alloc_net_rr_terminals_cluster(); -} - -void free_cluster_legality_checker(void) { - int inet; - free(best_routing); - free(rr_indexed_data); - free_rr_node_route_structs(); - free_route_structs(); - free_trace_structs(); - - free_chunk_memory(&rr_mem_ch); - - for (inet = 0; inet < num_logical_nets; inet++) { - free(saved_net_rr_terminals[inet]); - } - free(net_rr_terminals); - free(nets_in_cluster); - free(saved_net_rr_terminals); -} - -void alloc_and_load_rr_graph_for_pb_graph_node( - INP t_pb_graph_node *pb_graph_node, INP const t_arch* arch, int mode) { - - int i, j, k, index; - boolean is_primitive; - - is_primitive = (boolean) (pb_graph_node->pb_type->num_modes == 0); - - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - index = pb_graph_node->input_pins[i][j].pin_count_in_cluster; - rr_node[index].pb_graph_pin = &pb_graph_node->input_pins[i][j]; - rr_node[index].fan_in = - pb_graph_node->input_pins[i][j].num_input_edges; - rr_node[index].num_edges = - pb_graph_node->input_pins[i][j].num_output_edges; - rr_node[index].pack_intrinsic_cost = 1 - + (float) rr_node[index].num_edges / 5 + ((float)j/(float)pb_graph_node->num_input_pins[i])/(float)10; /* need to normalize better than 5 and 10, bias router to use earlier inputs pins */ - rr_node[index].edges = (int *) my_malloc( - rr_node[index].num_edges * sizeof(int)); - rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, - sizeof(short)); - rr_node[index].net_num = OPEN; - rr_node[index].vpack_net_num = OPEN; /* Xifan TANG: ensure a clear initialization */ - rr_node[index].prev_node = OPEN; - rr_node[index].prev_edge = OPEN; - if (mode == 0) { /* default mode is the first mode */ - rr_node[index].capacity = 1; - } else { - rr_node[index].capacity = 0; - } - for (k = 0; k < pb_graph_node->input_pins[i][j].num_output_edges; - k++) { - /* TODO: Intention was to do bus-based implementation here */ - rr_node[index].edges[k] = - pb_graph_node->input_pins[i][j].output_edges[k]->output_pins[0]->pin_count_in_cluster; - rr_node[index].switches[k] = arch->num_switches - 1; /* last switch in arch switch properties is a delayless switch */ - assert( - pb_graph_node->input_pins[i][j].output_edges[k]->num_output_pins == 1); - } - rr_node[index].type = INTRA_CLUSTER_EDGE; - if (is_primitive) { - /* This is a terminating pin, add SINK node */ - assert(rr_node[index].num_edges == 0); - rr_node[index].num_edges = 1; - rr_node[index].edges = (int *) my_calloc(rr_node[index].num_edges, sizeof(int)); - rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, sizeof(short)); - rr_node[index].edges[0] = num_rr_nodes; - - /* Create SINK node */ - rr_node[num_rr_nodes].pb_graph_pin = NULL; - rr_node[num_rr_nodes].fan_in = 1; - rr_node[num_rr_nodes].num_edges = 0; - rr_node[num_rr_nodes].pack_intrinsic_cost = 1; - rr_node[num_rr_nodes].edges = NULL; - rr_node[num_rr_nodes].switches = NULL; - rr_node[num_rr_nodes].net_num = OPEN; - rr_node[num_rr_nodes].vpack_net_num = OPEN; /* Xifan TANG: ensure a clear initialization */ - rr_node[num_rr_nodes].prev_node = OPEN; - rr_node[num_rr_nodes].prev_edge = OPEN; - rr_node[num_rr_nodes].capacity = 1; - rr_node[num_rr_nodes].type = SINK; - num_rr_nodes++; - - if(pb_graph_node->pb_type->class_type == LUT_CLASS) { - /* LUTs are special, they have logical equivalence at inputs, logical equivalence is represented by a single high capacity sink instead of multiple single capacity sinks */ - rr_node[num_rr_nodes - 1].capacity = pb_graph_node->num_input_pins[i]; - if(j != 0) { - num_rr_nodes--; - rr_node[index].edges[0] = num_rr_nodes - 1; - } - } - } - } - } - - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - index = pb_graph_node->output_pins[i][j].pin_count_in_cluster; - rr_node[index].pb_graph_pin = &pb_graph_node->output_pins[i][j]; - rr_node[index].fan_in = - pb_graph_node->output_pins[i][j].num_input_edges; - rr_node[index].num_edges = - pb_graph_node->output_pins[i][j].num_output_edges; - rr_node[index].pack_intrinsic_cost = 1 - + (float) rr_node[index].num_edges / 5; /* need to normalize better than 5 */ - rr_node[index].edges = (int *) my_malloc( - rr_node[index].num_edges * sizeof(int)); - rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, - sizeof(short)); - rr_node[index].net_num = OPEN; - rr_node[index].vpack_net_num = OPEN; /* Xifan TANG: ensure a clear initialization */ - rr_node[index].prev_node = OPEN; - rr_node[index].prev_edge = OPEN; - if (mode == 0) { /* Default mode is the first mode */ - rr_node[index].capacity = 1; - } else { - rr_node[index].capacity = 0; - } - for (k = 0; k < pb_graph_node->output_pins[i][j].num_output_edges; - k++) { - /* TODO: Intention was to do bus-based implementation here */ - rr_node[index].edges[k] = - pb_graph_node->output_pins[i][j].output_edges[k]->output_pins[0]->pin_count_in_cluster; - rr_node[index].switches[k] = arch->num_switches - 1; - assert( - pb_graph_node->output_pins[i][j].output_edges[k]->num_output_pins == 1); - } - rr_node[index].type = INTRA_CLUSTER_EDGE; - if (is_primitive) { - rr_node[index].type = SOURCE; - } - } - } - - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - index = pb_graph_node->clock_pins[i][j].pin_count_in_cluster; - rr_node[index].pb_graph_pin = &pb_graph_node->clock_pins[i][j]; - rr_node[index].fan_in = - pb_graph_node->clock_pins[i][j].num_input_edges; - rr_node[index].num_edges = - pb_graph_node->clock_pins[i][j].num_output_edges; - rr_node[index].pack_intrinsic_cost = 1 - + (float) rr_node[index].num_edges / 5; /* need to normalize better than 5 */ - rr_node[index].edges = (int *) my_malloc( - rr_node[index].num_edges * sizeof(int)); - rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, - sizeof(short)); - rr_node[index].net_num = OPEN; - rr_node[index].vpack_net_num = OPEN; /* Xifan TANG: ensure a clear initialization */ - rr_node[index].prev_node = OPEN; - rr_node[index].prev_edge = OPEN; - if (mode == 0) { /* default mode is the first mode (useful for routing */ - rr_node[index].capacity = 1; - } else { - rr_node[index].capacity = 0; - } - for (k = 0; k < pb_graph_node->clock_pins[i][j].num_output_edges; - k++) { - /* TODO: Intention was to do bus-based implementation here */ - rr_node[index].edges[k] = - pb_graph_node->clock_pins[i][j].output_edges[k]->output_pins[0]->pin_count_in_cluster; - rr_node[index].switches[k] = arch->num_switches - 1; - assert( - pb_graph_node->clock_pins[i][j].output_edges[k]->num_output_pins == 1); - } - rr_node[index].type = INTRA_CLUSTER_EDGE; - if (is_primitive) { - /* This is a terminating pin, add SINK node */ - assert(rr_node[index].num_edges == 0); - rr_node[index].num_edges = 1; - rr_node[index].edges = (int *) my_calloc(rr_node[index].num_edges, sizeof(int)); - rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, sizeof(short)); - rr_node[index].edges[0] = num_rr_nodes; - - /* Create SINK node */ - rr_node[num_rr_nodes].pb_graph_pin = NULL; - rr_node[num_rr_nodes].fan_in = 1; - rr_node[num_rr_nodes].num_edges = 0; - rr_node[num_rr_nodes].pack_intrinsic_cost = 1; - rr_node[num_rr_nodes].edges = NULL; - rr_node[num_rr_nodes].switches = NULL; - rr_node[num_rr_nodes].net_num = OPEN; - rr_node[num_rr_nodes].vpack_net_num = OPEN; /* Xifan TANG: ensure a clear initialization */ - rr_node[num_rr_nodes].prev_node = OPEN; - rr_node[num_rr_nodes].prev_edge = OPEN; - rr_node[num_rr_nodes].capacity = 1; - rr_node[num_rr_nodes].type = SINK; - num_rr_nodes++; - } - } - } - - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - /* Xifan Tang: we DO NOT build the rr_graph for those modes are disabled in packing */ - /* - if (TRUE == pb_graph_node->pb_type->modes[i].disabled_in_packing) { - continue; - } - */ - for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; - j++) { - for (k = 0; - k - < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - alloc_and_load_rr_graph_for_pb_graph_node( - &pb_graph_node->child_pb_graph_nodes[i][j][k], arch, i); - } - } - } - -} - -void alloc_and_load_legalizer_for_cluster(INP t_block* clb, INP int clb_index, - INP const t_arch *arch) { - - /** - * Structure: Model external routing and internal routing - * - * 1. Model external routing - * num input pins == num external sources for input pins, fully connect them to input pins (simulates external routing) - * num output pins == num external sinks for output pins, fully connect them to output pins (simulates external routing) - * num clock pins == num external sources for clock pins, fully connect them to clock pins (simulates external routing) - * 2. Model internal routing - * - */ - /* make each rr_node one correspond with pin and correspond with pin's index pin_count_in_cluster */ - int i, j, k, m, index, pb_graph_rr_index; - int count_pins; - t_pb_type * pb_type; - t_pb_graph_node *pb_graph_node; - int ipin; - - /* Create rr_graph */ - pb_type = clb->type->pb_type; - pb_graph_node = clb->type->pb_graph_head; - num_rr_nodes = pb_graph_node->total_pb_pins + pb_type->num_input_pins - + pb_type->num_output_pins + pb_type->num_clock_pins; - - /* allocate memory for rr_node resources + additional memory for any additional sources/sinks, 2x is an overallocation but guarantees that there will be enough sources/sinks available */ - rr_node = (t_rr_node *) my_calloc(num_rr_nodes * 2, sizeof(t_rr_node)); - clb->pb->rr_graph = rr_node; - - alloc_and_load_rr_graph_for_pb_graph_node(pb_graph_node, arch, 0); - - curr_cluster_index = clb_index; - - /* Alloc and load rr_graph external sources and sinks */ - ext_input_rr_node_index = pb_graph_node->total_pb_pins; - ext_output_rr_node_index = pb_type->num_input_pins - + pb_graph_node->total_pb_pins; - ext_clock_rr_node_index = pb_type->num_input_pins + pb_type->num_output_pins - + pb_graph_node->total_pb_pins; - max_ext_index = pb_type->num_input_pins + pb_type->num_output_pins - + pb_type->num_clock_pins + pb_graph_node->total_pb_pins; - - for (i = 0; i < pb_type->num_input_pins; i++) { - index = i + pb_graph_node->total_pb_pins; - rr_node[index].type = SOURCE; - rr_node[index].fan_in = 0; - rr_node[index].num_edges = pb_type->num_input_pins; - rr_node[index].pack_intrinsic_cost = 1 - + (float) rr_node[index].num_edges / 5; /* need to normalize better than 5 */ - rr_node[index].edges = (int *) my_malloc( - rr_node[index].num_edges * sizeof(int)); - rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, - sizeof(int)); - rr_node[index].capacity = 1; - } - - for (i = 0; i < pb_type->num_output_pins; i++) { - index = i + pb_type->num_input_pins + pb_graph_node->total_pb_pins; - rr_node[index].type = SINK; - rr_node[index].fan_in = pb_type->num_output_pins; - rr_node[index].num_edges = 0; - rr_node[index].pack_intrinsic_cost = 1 - + (float) rr_node[index].num_edges / 5; /* need to normalize better than 5 */ - rr_node[index].capacity = 1; - } - - for (i = 0; i < pb_type->num_clock_pins; i++) { - index = i + pb_type->num_input_pins + pb_type->num_output_pins - + pb_graph_node->total_pb_pins; - rr_node[index].type = SOURCE; - rr_node[index].fan_in = 0; - rr_node[index].num_edges = pb_type->num_clock_pins; - rr_node[index].pack_intrinsic_cost = 1 - + (float) rr_node[index].num_edges / 5; /* need to normalize better than 5 */ - rr_node[index].edges = (int *) my_malloc( - rr_node[index].num_edges * sizeof(int)); - rr_node[index].switches = (short *) my_calloc(rr_node[index].num_edges, - sizeof(int)); - rr_node[index].capacity = 1; - } - - ipin = 0; - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - pb_graph_rr_index = - pb_graph_node->input_pins[i][j].pin_count_in_cluster; - for (k = 0; k < pb_type->num_input_pins; k++) { - index = k + pb_graph_node->total_pb_pins; - rr_node[index].edges[ipin] = pb_graph_rr_index; - rr_node[index].switches[ipin] = arch->num_switches - 1; - } - rr_node[pb_graph_rr_index].pack_intrinsic_cost = MAX_SHORT; /* using an input pin should be made costly */ - ipin++; - } - } - - /* Must attach output pins to input pins because if a connection cannot fit using intra-cluster routing, it can also use external routing */ - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - count_pins = pb_graph_node->output_pins[i][j].num_output_edges - + pb_type->num_output_pins + pb_type->num_input_pins; - pb_graph_rr_index = - pb_graph_node->output_pins[i][j].pin_count_in_cluster; - rr_node[pb_graph_rr_index].edges = (int *) my_realloc( - rr_node[pb_graph_rr_index].edges, - (count_pins) * sizeof(int)); - rr_node[pb_graph_rr_index].switches = (short *) my_realloc( - rr_node[pb_graph_rr_index].switches, - (count_pins) * sizeof(int)); - - ipin = 0; - for (k = 0; k < pb_graph_node->num_input_ports; k++) { - for (m = 0; m < pb_graph_node->num_input_pins[k]; m++) { - index = - pb_graph_node->input_pins[k][m].pin_count_in_cluster; - rr_node[pb_graph_rr_index].edges[ipin - + pb_graph_node->output_pins[i][j].num_output_edges] = - index; - rr_node[pb_graph_rr_index].switches[ipin - + pb_graph_node->output_pins[i][j].num_output_edges] = - arch->num_switches - 1; - ipin++; - } - } - for (k = 0; k < pb_type->num_output_pins; k++) { - index = k + pb_type->num_input_pins - + pb_graph_node->total_pb_pins; - rr_node[pb_graph_rr_index].edges[k + pb_type->num_input_pins - + pb_graph_node->output_pins[i][j].num_output_edges] = - index; - rr_node[pb_graph_rr_index].switches[k + pb_type->num_input_pins - + pb_graph_node->output_pins[i][j].num_output_edges] = - arch->num_switches - 1; - } - rr_node[pb_graph_rr_index].num_edges += pb_type->num_output_pins - + pb_type->num_input_pins; - rr_node[pb_graph_rr_index].pack_intrinsic_cost = 1 - + (float) rr_node[pb_graph_rr_index].num_edges / 5; /* need to normalize better than 5 */ - } - } - - ipin = 0; - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - for (k = 0; k < pb_type->num_clock_pins; k++) { - index = k + pb_type->num_input_pins + pb_type->num_output_pins - + pb_graph_node->total_pb_pins; - pb_graph_rr_index = - pb_graph_node->clock_pins[i][j].pin_count_in_cluster; - rr_node[index].edges[ipin] = pb_graph_rr_index; - rr_node[index].switches[ipin] = arch->num_switches - 1; - } - ipin++; - } - } - - alloc_and_load_rr_node_route_structs(); - num_nets_in_cluster = 0; - -} - -void free_legalizer_for_cluster(INP t_block* clb, boolean free_local_rr_graph) { - int i; - - free_rr_node_route_structs(); - if(free_local_rr_graph == TRUE) { - for (i = 0; i < num_rr_nodes; i++) { - if (clb->pb->rr_graph[i].edges != NULL) { - free(clb->pb->rr_graph[i].edges); - } - if (clb->pb->rr_graph[i].switches != NULL) { - free(clb->pb->rr_graph[i].switches); - } - } - free(clb->pb->rr_graph); - } -} - -void reset_legalizer_for_cluster(t_block *clb) { - int i; - for (i = 0; i < num_nets_in_cluster; i++) { - free_traceback(nets_in_cluster[i]); - trace_head[nets_in_cluster[i]] = best_routing[nets_in_cluster[i]]; - free_traceback(nets_in_cluster[i]); - best_routing[nets_in_cluster[i]] = NULL; - } - - free_rr_node_route_structs(); - num_nets_in_cluster = 0; - saved_num_nets_in_cluster = 0; -} - -/** - * - * internal_nets: index of nets to route [0..num_internal_nets - 1] - */ -boolean try_breadth_first_route_cluster(void) { - - /* Iterated maze router ala Pathfinder Negotiated Congestion algorithm, * - * (FPGA 95 p. 111). Returns TRUE if it can route this FPGA, FALSE if * - * it can't. */ - - /* For different modes, when a mode is turned on, I set the max occupancy of all rr_nodes in the mode to 1 and all others to 0 */ - /* TODO: There is a bug for route-throughs where edges in route-throughs do not get turned off because the rr_edge is in a particular mode but the two rr_nodes are outside */ - - boolean success, is_routable; - int itry, inet, net_index; - struct s_router_opts router_opts; - - /* Xifan TANG: Count runtime for routing in packing stage */ - clock_t begin, end; - - begin = clock(); - - /* Usually the first iteration uses a very small (or 0) pres_fac to find * - * the shortest path and get a congestion map. For fast compiles, I set * - * pres_fac high even for the first iteration. */ - - /* sets up a fast breadth-first router */ - router_opts.first_iter_pres_fac = 10; - router_opts.max_router_iterations = 20; - router_opts.initial_pres_fac = 10; - router_opts.pres_fac_mult = 2; - router_opts.acc_fac = 1; - - reset_rr_node_route_structs(); /* Clear all prior rr_graph history */ - - pres_fac = router_opts.first_iter_pres_fac; - - for (itry = 1; itry <= router_opts.max_router_iterations; itry++) { - for (inet = 0; inet < num_nets_in_cluster; inet++) { - net_index = nets_in_cluster[inet]; - - pathfinder_update_one_cost(trace_head[net_index], -1, pres_fac); - - is_routable = breadth_first_route_net_cluster(net_index); - - /* Impossible to route? (disconnected rr_graph) */ - - if (!is_routable) { - /* TODO: Inelegant, can be more intelligent */ - vpr_printf(TIO_MESSAGE_INFO, "Failed routing net %s\n", vpack_net[net_index].name); - vpr_printf(TIO_MESSAGE_INFO, "Routing failed. Disconnected rr_graph.\n"); - return FALSE; - } - - pathfinder_update_one_cost(trace_head[net_index], 1, pres_fac); - - } - - success = feasible_routing(); - if (success) { - /* End of packing routing */ - end = clock(); - /* accumulate the runtime for pack routing */ -#ifdef CLOCKS_PER_SEC - pack_route_time += (float)(end - begin)/ CLOCKS_PER_SEC; -#else - pack_route_time += (float)(end - begin)/ CLK_PER_SEC; -#endif - /* vpr_printf(TIO_MESSAGE_INFO, "Updated: Packing routing took %g seconds\n", pack_route_time); */ - return (TRUE); - } - - if (itry == 1) - pres_fac = router_opts.initial_pres_fac; - else - pres_fac *= router_opts.pres_fac_mult; - - pres_fac = std::min(pres_fac, static_cast(HUGE_POSITIVE_FLOAT / 1e5)); - - pathfinder_update_cost(pres_fac, router_opts.acc_fac); - } - /* End of packing routing */ - end = clock(); - /* accumulate the runtime for pack routing */ -#ifdef CLOCKS_PER_SEC - pack_route_time += (float)(end - begin)/ CLOCKS_PER_SEC; -#else - pack_route_time += (float)(end - begin)/ CLK_PER_SEC; -#endif - /* vpr_printf(TIO_MESSAGE_INFO, "Updated: Packing routing took %g seconds\n", pack_route_time); */ - - return (FALSE); -} - -static boolean breadth_first_route_net_cluster(int inet) { - - /* Uses a maze routing (Dijkstra's) algorithm to route a net. The net * - * begins at the net output, and expands outward until it hits a target * - * pin. The algorithm is then restarted with the entire first wire segment * - * included as part of the source this time. For an n-pin net, the maze * - * router is invoked n-1 times to complete all the connections. Inet is * - * the index of the net to be routed. * - * If this routine finds that a net *cannot* be connected (due to a complete * - * lack of potential paths, rather than congestion), it returns FALSE, as * - * routing is impossible on this architecture. Otherwise it returns TRUE. */ - - int i, inode, prev_node, remaining_connections_to_sink; - float pcost, new_pcost; - struct s_heap *current; - struct s_trace *tptr; - boolean first_time; - - free_traceback(inet); - breadth_first_add_source_to_heap_cluster(inet); - mark_ends_cluster(inet); - - tptr = NULL; - remaining_connections_to_sink = 0; - - for (i = 1; i <= vpack_net[inet].num_sinks; i++) { /* Need n-1 wires to connect n pins */ - - /* Do not connect open terminals */ - if (net_rr_terminals[inet][i] == OPEN) - continue; - /* Expand and begin routing */ - breadth_first_expand_trace_segment_cluster(tptr, - remaining_connections_to_sink); - current = get_heap_head(); - - if (current == NULL) { /* Infeasible routing. No possible path for net. */ - reset_path_costs(); /* Clean up before leaving. */ - return (FALSE); - } - - inode = current->index; - - while (rr_node_route_inf[inode].target_flag == 0) { - pcost = rr_node_route_inf[inode].path_cost; - new_pcost = current->cost; - if (pcost > new_pcost) { /* New path is lowest cost. */ - rr_node_route_inf[inode].path_cost = new_pcost; - prev_node = current->u.prev_node; - rr_node_route_inf[inode].prev_node = prev_node; - rr_node_route_inf[inode].prev_edge = current->prev_edge; - first_time = FALSE; - - if (pcost > 0.99 * HUGE_POSITIVE_FLOAT) /* First time touched. */{ - add_to_mod_list(&rr_node_route_inf[inode].path_cost); - first_time = TRUE; - } - - breadth_first_expand_neighbours_cluster(inode, new_pcost, inet, - first_time); - } - - free_heap_data(current); - current = get_heap_head(); - - if (current == NULL) { /* Impossible routing. No path for net. */ - reset_path_costs(); - return (FALSE); - } - - inode = current->index; - } - - rr_node_route_inf[inode].target_flag--; /* Connected to this SINK. */ - remaining_connections_to_sink = rr_node_route_inf[inode].target_flag; - tptr = update_traceback(current, inet); - free_heap_data(current); - } - - empty_heap(); - reset_path_costs(); - return (TRUE); -} - -static void breadth_first_expand_trace_segment_cluster( - struct s_trace *start_ptr, int remaining_connections_to_sink) { - - /* Adds all the rr_nodes in the traceback segment starting at tptr (and * - * continuing to the end of the traceback) to the heap with a cost of zero. * - * This allows expansion to begin from the existing wiring. The * - * remaining_connections_to_sink value is 0 if the route segment ending * - * at this location is the last one to connect to the SINK ending the route * - * segment. This is the usual case. If it is not the last connection this * - * net must make to this SINK, I have a hack to ensure the next connection * - * to this SINK goes through a different IPIN. Without this hack, the * - * router would always put all the connections from this net to this SINK * - * through the same IPIN. With LUTs or cluster-based logic blocks, you * - * should never have a net connecting to two logically-equivalent pins on * - * the same logic block, so the hack will never execute. If your logic * - * block is an and-gate, however, nets might connect to two and-inputs on * - * the same logic block, and since the and-inputs are logically-equivalent, * - * this means two connections to the same SINK. */ - - struct s_trace *tptr, *next_ptr; - int inode, sink_node, last_ipin_node; - - tptr = start_ptr; - - if (remaining_connections_to_sink == 0) { /* Usual case. */ - while (tptr != NULL) { - node_to_heap(tptr->index, 0., NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); - tptr = tptr->next; - } - } - - else { /* This case never executes for most logic blocks. */ - - /* Weird case. Lots of hacks. The cleanest way to do this would be to empty * - * the heap, update the congestion due to the partially-completed route, put * - * the whole route so far (excluding IPINs and SINKs) on the heap with cost * - * 0., and expand till you hit the next SINK. That would be slow, so I * - * do some hacks to enable incremental wavefront expansion instead. */ - - if (tptr == NULL) - return; /* No route yet */ - - next_ptr = tptr->next; - last_ipin_node = OPEN; /* Stops compiler from complaining. */ - - /* Can't put last SINK on heap with NO_PREVIOUS, etc, since that won't let * - * us reach it again. Instead, leave the last traceback element (SINK) off * - * the heap. */ - - while (next_ptr != NULL) { - inode = tptr->index; - node_to_heap(inode, 0., NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); - - if (rr_node[inode].type == INTRA_CLUSTER_EDGE) - { - if(rr_node[inode].pb_graph_pin != NULL && rr_node[inode].pb_graph_pin->num_output_edges == 0) - { - last_ipin_node = inode; - } - } - - tptr = next_ptr; - next_ptr = tptr->next; - } - - /* This will stop the IPIN node used to get to this SINK from being * - * reexpanded for the remainder of this net's routing. This will make us * - * hook up more IPINs to this SINK (which is what we want). If IPIN * - * doglegs are allowed in the graph, we won't be able to use this IPIN to * - * do a dogleg, since it won't be re-expanded. Shouldn't be a big problem. */ - assert(last_ipin_node != OPEN); - rr_node_route_inf[last_ipin_node].path_cost = -HUGE_POSITIVE_FLOAT; - - /* Also need to mark the SINK as having high cost, so another connection can * - * be made to it. */ - - sink_node = tptr->index; - rr_node_route_inf[sink_node].path_cost = HUGE_POSITIVE_FLOAT; - - /* Finally, I need to remove any pending connections to this SINK via the * - * IPIN I just used (since they would result in congestion). Scan through * - * the heap to do this. */ - - invalidate_heap_entries(sink_node, last_ipin_node); - } -} - -static void breadth_first_expand_neighbours_cluster(int inode, float pcost, - int inet, boolean first_time) { - - /* Puts all the rr_nodes adjacent to inode on the heap. rr_nodes outside * - * the expanded bounding box specified in route_bb are not added to the * - * heap. pcost is the path_cost to get to inode. */ - - int iconn, to_node, num_edges; - float tot_cost; - - num_edges = rr_node[inode].num_edges; - for (iconn = 0; iconn < num_edges; iconn++) { - to_node = rr_node[inode].edges[iconn]; - /* Xifan Tang: SHOULD BE FIXED THOROUGHLY!!! - * Here, I just bypass all the edges that belongs a mode that is disabled in packing - */ - if ( (NULL != rr_node[to_node].pb_graph_pin) - && (NULL != rr_node[to_node].pb_graph_pin->parent_node->pb_type->parent_mode) - && (TRUE == rr_node[to_node].pb_graph_pin->parent_node->pb_type->parent_mode->disabled_in_packing)) { - continue; - } - /*if (first_time) { */ - tot_cost = pcost - + get_rr_cong_cost(to_node) * rr_node_intrinsic_cost(to_node); - /* - } else { - tot_cost = pcost + get_rr_cong_cost(to_node); - }*/ - node_to_heap(to_node, tot_cost, inode, iconn, OPEN, OPEN); - } -} - -static void breadth_first_add_source_to_heap_cluster(int inet) { - - /* Adds the SOURCE of this net to the heap. Used to start a net's routing. */ - - int inode; - float cost; - - inode = net_rr_terminals[inet][0]; /* SOURCE */ - cost = get_rr_cong_cost(inode); - - node_to_heap(inode, cost, NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); -} - -static void mark_ends_cluster(int inet) { - - /* Mark all the SINKs of this net as targets by setting their target flags * - * to the number of times the net must connect to each SINK. Note that * - * this number can occassionally be greater than 1 -- think of connecting * - * the same net to two inputs of an and-gate (and-gate inputs are logically * - * equivalent, so both will connect to the same SINK). */ - - int ipin, inode; - - for (ipin = 1; ipin <= vpack_net[inet].num_sinks; ipin++) { - inode = net_rr_terminals[inet][ipin]; - if (inode == OPEN) - continue; - rr_node_route_inf[inode].target_flag++; - assert(rr_node_route_inf[inode].target_flag > 0 && rr_node_route_inf[inode].target_flag <= rr_node[inode].capacity); - } -} - -static void alloc_net_rr_terminals_cluster(void) { - int inet; - - net_rr_terminals = (int **) my_malloc(num_logical_nets * sizeof(int *)); - saved_net_rr_terminals = (int **) my_malloc( - num_logical_nets * sizeof(int *)); - saved_num_nets_in_cluster = 0; - - for (inet = 0; inet < num_logical_nets; inet++) { - net_rr_terminals[inet] = (int *) my_chunk_malloc( - (vpack_net[inet].num_sinks + 1) * sizeof(int), - &rr_mem_ch); - - saved_net_rr_terminals[inet] = (int *) my_malloc( - (vpack_net[inet].num_sinks + 1) * sizeof(int)); - } -} - -void setup_intracluster_routing_for_molecule(INP t_pack_molecule *molecule, - INP t_pb_graph_node **primitive_list) { - - /* Allocates and loads the net_rr_terminals data structure. For each net * - * it stores the rr_node index of the SOURCE of the net and all the SINKs * - * of the net. [0..num_logical_nets-1][0..num_pins-1]. */ - int i; - - for (i = 0; i < get_array_size_of_molecule(molecule); i++) { - if (molecule->logical_block_ptrs[i] != NULL) { - setup_intracluster_routing_for_logical_block( - molecule->logical_block_ptrs[i]->index, primitive_list[i]); - } - } - - reload_ext_net_rr_terminal_cluster(); -} - -void setup_intracluster_routing_for_logical_block(INP int iblock, - INP t_pb_graph_node *primitive) { - - /* Allocates and loads the net_rr_terminals data structure. For each net * - * it stores the rr_node index of the SOURCE of the net and all the SINKs * - * of the net. [0..num_logical_nets-1][0..num_pins-1]. */ - int ipin, iblk_net; - t_model_ports *port; - - assert(primitive->pb_type->num_modes == 0); - /* check if primitive */ - assert(logical_block[iblock].clb_index != NO_CLUSTER); - /* check if primitive and block is open */ - - /* check if block type matches primitive type */ - if (logical_block[iblock].model != primitive->pb_type->model) { - /* End early, model is incompatible */ - assert(0); - } - - /* for each net of logical block, check if it is in cluster, if not add it */ - /* also check if pins on primitive can fit logical block */ - - port = logical_block[iblock].model->inputs; - - while (port) { - for (ipin = 0; ipin < port->size; ipin++) { - if (port->is_clock) { - assert(port->size == 1); - iblk_net = logical_block[iblock].clock_net; - } else { - iblk_net = logical_block[iblock].input_nets[port->index][ipin]; - } - if (iblk_net == OPEN) { - continue; - } - if (!is_net_in_cluster(iblk_net)) { - nets_in_cluster[num_nets_in_cluster] = iblk_net; - num_nets_in_cluster++; - } - add_net_rr_terminal_cluster(iblk_net, primitive, iblock, port, - ipin); - } - port = port->next; - } - - port = logical_block[iblock].model->outputs; - while (port) { - for (ipin = 0; ipin < port->size; ipin++) { - iblk_net = logical_block[iblock].output_nets[port->index][ipin]; - if (iblk_net == OPEN) { - continue; - } - if (!is_net_in_cluster(iblk_net)) { - nets_in_cluster[num_nets_in_cluster] = iblk_net; - num_nets_in_cluster++; - } - add_net_rr_terminal_cluster(iblk_net, primitive, iblock, port, - ipin); - } - port = port->next; - } -} - -void save_and_reset_routing_cluster(void) { - - /* This routing frees any routing currently held in best routing, * - * then copies over the current routing (held in trace_head), and * - * finally sets trace_head and trace_tail to all NULLs so that the * - * connection to the saved routing is broken. This is necessary so * - * that the next iteration of the router does not free the saved * - * routing elements. Also, the routing path costs and net_rr_terminals is stripped from the - * existing rr_graph so that the saved routing does not affect the graph */ - - int inet, i, j; - struct s_trace *tempptr; - saved_num_nets_in_cluster = num_nets_in_cluster; - - for (i = 0; i < num_nets_in_cluster; i++) { - inet = nets_in_cluster[i]; - for (j = 0; j <= vpack_net[inet].num_sinks; j++) { - saved_net_rr_terminals[inet][j] = net_rr_terminals[inet][j]; - } - - /* Free any previously saved routing. It is no longer best. */ - /* Also Save a pointer to the current routing in best_routing. */ - - pathfinder_update_one_cost(trace_head[inet], -1, pres_fac); - tempptr = trace_head[inet]; - trace_head[inet] = best_routing[inet]; - free_traceback(inet); - best_routing[inet] = tempptr; - - /* Set the current (working) routing to NULL so the current trace * - * elements won't be reused by the memory allocator. */ - - trace_head[inet] = NULL; - trace_tail[inet] = NULL; - } -} - -void restore_routing_cluster(void) { - - /* Deallocates any current routing in trace_head, and replaces it with * - * the routing in best_routing. Best_routing is set to NULL to show that * - * it no longer points to a valid routing. NOTE: trace_tail is not * - * restored -- it is set to all NULLs since it is only used in * - * update_traceback. If you need trace_tail restored, modify this * - * routine. Also restores the locally used opin data. */ - - int inet, i, j; - - for (i = 0; i < num_nets_in_cluster; i++) { - inet = nets_in_cluster[i]; - - pathfinder_update_one_cost(trace_head[inet], -1, pres_fac); - - /* Free any current routing. */ - free_traceback(inet); - - /* Set the current routing to the saved one. */ - trace_head[inet] = best_routing[inet]; - best_routing[inet] = NULL; /* No stored routing. */ - - /* restore net terminals */ - for (j = 0; j <= vpack_net[inet].num_sinks; j++) { - net_rr_terminals[inet][j] = saved_net_rr_terminals[inet][j]; - } - - /* restore old routing */ - pathfinder_update_one_cost(trace_head[inet], 1, pres_fac); - } - num_nets_in_cluster = saved_num_nets_in_cluster; -} - -void save_cluster_solution(void) { - - /* This routine updates the occupancy and pres_cost of the rr_nodes that are * - * affected by the portion of the routing of one net that starts at * - * route_segment_start. If route_segment_start is trace_head[inet], the * - * cost of all the nodes in the routing of net inet are updated. If * - * add_or_sub is -1 the net (or net portion) is ripped up, if it is 1 the * - * net is added to the routing. The size of pres_fac determines how severly * - * oversubscribed rr_nodes are penalized. */ - - int i, j, net_index; - struct s_trace *tptr, *prev; - int inode; - for (i = 0; i < max_ext_index; i++) { - rr_node[i].net_num = OPEN; - rr_node[i].vpack_net_num = OPEN; /* Xifan TANG: ensure a clear initialization */ - rr_node[i].prev_edge = OPEN; - rr_node[i].prev_node = OPEN; - } - for (i = 0; i < num_nets_in_cluster; i++) { - prev = NULL; - net_index = nets_in_cluster[i]; - tptr = trace_head[net_index]; - if (tptr == NULL) /* No routing yet. */ - return; - - for (;;) { - inode = tptr->index; - rr_node[inode].net_num = net_index; - if (prev != NULL) { - rr_node[inode].prev_node = prev->index; - for (j = 0; j < rr_node[prev->index].num_edges; j++) { - if (rr_node[prev->index].edges[j] == inode) { - rr_node[inode].prev_edge = j; - break; - } - } - assert(j != rr_node[prev->index].num_edges); - } else { - rr_node[inode].prev_node = OPEN; - rr_node[inode].prev_edge = OPEN; - } - - if (rr_node[inode].type == SINK) { - tptr = tptr->next; /* Skip next segment. */ - if (tptr == NULL) - break; - } - - prev = tptr; - tptr = tptr->next; - - } /* End while loop -- did an entire traceback. */ - } -} - -boolean is_pin_open(int i) { - return (boolean) (rr_node[i].occ == 0); -} - -static float rr_node_intrinsic_cost(int inode) { - /* This is a tie breaker to avoid using nodes with more edges whenever possible */ - float value; - value = rr_node[inode].pack_intrinsic_cost; - return value; -} - -/* turns on mode for a pb by setting capacity of its rr_nodes to 1 */ -void set_pb_graph_mode(t_pb_graph_node *pb_graph_node, int mode, int isOn) { - int i, j, index; - int i_pb_type, i_pb_inst; - const t_pb_type *pb_type; - - pb_type = pb_graph_node->pb_type; - for (i_pb_type = 0; i_pb_type < pb_type->modes[mode].num_pb_type_children; - i_pb_type++) { - for (i_pb_inst = 0; - i_pb_inst - < pb_type->modes[mode].pb_type_children[i_pb_type].num_pb; - i_pb_inst++) { - for (i = 0; - i - < pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].num_input_ports; - i++) { - for (j = 0; - j - < pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].num_input_pins[i]; - j++) { - index = - pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].input_pins[i][j].pin_count_in_cluster; - rr_node[index].capacity = isOn; - } - } - - for (i = 0; - i - < pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].num_output_ports; - i++) { - for (j = 0; - j - < pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].num_output_pins[i]; - j++) { - index = - pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].output_pins[i][j].pin_count_in_cluster; - rr_node[index].capacity = isOn; - } - } - - for (i = 0; - i - < pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].num_clock_ports; - i++) { - for (j = 0; - j - < pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].num_clock_pins[i]; - j++) { - index = - pb_graph_node->child_pb_graph_nodes[mode][i_pb_type][i_pb_inst].clock_pins[i][j].pin_count_in_cluster; - rr_node[index].capacity = isOn; - } - } - } - } -} - -/* If this is done post place and route, use the cb pins determined by place-and-route rather than letting the legalizer freely determine */ -void force_post_place_route_cb_input_pins(int iblock) { - int i, j, k, ipin, net_index, ext_net; - int pin_offset; - boolean has_ext_source, success; - int curr_ext_input, curr_ext_clock; - t_pb_graph_node *pb_graph_node; - - pb_graph_node = block[iblock].pb->pb_graph_node; - pin_offset = block[iblock].z * (pb_graph_node->pb_type->num_input_pins + pb_graph_node->pb_type->num_output_pins + pb_graph_node->pb_type->num_clock_pins); - - curr_ext_input = ext_input_rr_node_index; - curr_ext_clock = ext_clock_rr_node_index; - - for (i = 0; i < num_nets_in_cluster; i++) { - net_index = nets_in_cluster[i]; - has_ext_source = (boolean) - (logical_block[vpack_net[net_index].node_block[0]].clb_index - != curr_cluster_index); - if(has_ext_source) { - ext_net = vpack_to_clb_net_mapping[net_index]; - assert(ext_net != OPEN); - if (vpack_net[net_index].is_global) { - free(rr_node[curr_ext_clock].edges); - rr_node[curr_ext_clock].edges = NULL; - rr_node[curr_ext_clock].num_edges = 0; - - success = FALSE; - ipin = 0; - /* force intra-cluster net to use pins from ext route */ - for(j = 0; j < pb_graph_node->num_clock_ports; j++) { - for(k = 0; k < pb_graph_node->num_clock_pins[j]; k++) { - if(ext_net == block[iblock].nets[ipin + pb_graph_node->pb_type->num_input_pins + pb_graph_node->pb_type->num_output_pins + pin_offset]) { - success = TRUE; - rr_node[curr_ext_clock].num_edges++; - rr_node[curr_ext_clock].edges = (int*)my_realloc(rr_node[curr_ext_clock].edges, rr_node[curr_ext_clock].num_edges * sizeof(int)); - rr_node[curr_ext_clock].edges[rr_node[curr_ext_clock].num_edges - 1] = pb_graph_node->clock_pins[j][k].pin_count_in_cluster; - } - ipin++; - } - } - assert(success); - curr_ext_clock++; - } else { - free(rr_node[curr_ext_input].edges); - rr_node[curr_ext_input].edges = NULL; - rr_node[curr_ext_input].num_edges = 0; - - success = FALSE; - ipin = 0; - /* force intra-cluster net to use pins from ext route */ - for(j = 0; j < pb_graph_node->num_input_ports; j++) { - for(k = 0; k < pb_graph_node->num_input_pins[j]; k++) { - if(ext_net == block[iblock].nets[ipin + pin_offset]) { - success = TRUE; - rr_node[curr_ext_input].num_edges++; - rr_node[curr_ext_input].edges = (int*)my_realloc(rr_node[curr_ext_input].edges, rr_node[curr_ext_input].num_edges * sizeof(int)); - rr_node[curr_ext_input].edges[rr_node[curr_ext_input].num_edges - 1] = pb_graph_node->input_pins[j][k].pin_count_in_cluster; - } - ipin++; - } - } - curr_ext_input++; - assert(success); - } - } - } -} - diff --git a/vpr7_x2p/vpr/SRC/pack/cluster_legality.h b/vpr7_x2p/vpr/SRC/pack/cluster_legality.h deleted file mode 100644 index 4e6e8f4fa..000000000 --- a/vpr7_x2p/vpr/SRC/pack/cluster_legality.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef CLUSTER_LEGALITY_H -#define CLUSTER_LEGALITY_H - -/* Legalizes routing for a cluster - */ -void alloc_and_load_cluster_legality_checker(void); - -void alloc_and_load_legalizer_for_cluster(INP t_block* clb, INP int clb_index, INP const t_arch *arch); - -void free_legalizer_for_cluster(INP t_block* clb, boolean free_local_rr_graph); - -void free_cluster_legality_checker(void); - -void reset_legalizer_for_cluster(t_block *clb); - -/* order of use: 1. save cluster 2. Add blocks. 3. route 4. save if successful, undo if not successful */ -void save_and_reset_routing_cluster(void); -void setup_intracluster_routing_for_molecule(INP t_pack_molecule *molecule, INOUTP t_pb_graph_node **primitives_list); -boolean try_breadth_first_route_cluster(void); -void restore_routing_cluster(void); -void save_cluster_solution(void); - -boolean is_pin_open(int i); - -void set_pb_graph_mode(t_pb_graph_node *pb_graph_node, int mode, int isOn); - -void alloc_and_load_rr_graph_for_pb_graph_node(INP t_pb_graph_node *pb_graph_node, INP const t_arch* arch, int mode); - - -/* Power user options */ -void reload_ext_net_rr_terminal_cluster(void); -void force_post_place_route_cb_input_pins(int iblock); -void setup_intracluster_routing_for_logical_block(INP int iblock, - INP t_pb_graph_node *primitive); - -#endif diff --git a/vpr7_x2p/vpr/SRC/pack/cluster_placement.c b/vpr7_x2p/vpr/SRC/pack/cluster_placement.c deleted file mode 100644 index f85a955d0..000000000 --- a/vpr7_x2p/vpr/SRC/pack/cluster_placement.c +++ /dev/null @@ -1,802 +0,0 @@ -/* - Given a group of logical blocks and a partially-packed complex block, find placement for group of logical blocks in complex block - To use, keep "cluster_placement_stats" data structure throughout packing - cluster_placement_stats undergoes these major states: - Initialization - performed once at beginning of packing - Reset - reset state in between packing of clusters - In flight - Speculatively place - Finalized - Commit or revert placements - Freed - performed once at end of packing - - Author: Jason Luu - March 12, 2012 - */ -#include -#include -#include - -#include "read_xml_arch_file.h" -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "vpr_utils.h" -#include "hash.h" -#include "cluster_placement.h" - -/****************************************/ -/*Local Function Declaration */ -/****************************************/ -static void load_cluster_placement_stats_for_pb_graph_node( - INOUTP t_cluster_placement_stats *cluster_placement_stats, - INOUTP t_pb_graph_node *pb_graph_node); -static void requeue_primitive( - INOUTP t_cluster_placement_stats *cluster_placement_stats, - t_cluster_placement_primitive *cluster_placement_primitive); -static void update_primitive_cost_or_status(INP t_pb_graph_node *pb_graph_node, - INP float incremental_cost, INP boolean valid); -static float try_place_molecule(INP t_pack_molecule *molecule, - INP t_pb_graph_node *root, INOUTP t_pb_graph_node **primitives_list, INP int clb_index); -static boolean expand_forced_pack_molecule_placement( - INP t_pack_molecule *molecule, - INP t_pack_pattern_block *pack_pattern_block, - INOUTP t_pb_graph_node **primitives_list, INOUTP float *cost); -static t_pb_graph_pin *expand_pack_molecule_pin_edge(INP int pattern_id, - INP t_pb_graph_pin *cur_pin, INP boolean forward); -static void flush_intermediate_queues( - INOUTP t_cluster_placement_stats *cluster_placement_stats); -static boolean root_passes_early_filter(INP t_pb_graph_node *root, INP t_pack_molecule *molecule, INP int clb_index); - -/****************************************/ -/*Function Definitions */ -/****************************************/ - -/** - * [0..num_pb_types-1] array of cluster placement stats, one for each type_descriptors - */ -t_cluster_placement_stats *alloc_and_load_cluster_placement_stats(void) { - t_cluster_placement_stats *cluster_placement_stats_list; - int i; - - cluster_placement_stats_list = (t_cluster_placement_stats *) my_calloc(num_types, - sizeof(t_cluster_placement_stats)); - for (i = 0; i < num_types; i++) { - if (EMPTY_TYPE != &type_descriptors[i]) { - cluster_placement_stats_list[i].valid_primitives = (t_cluster_placement_primitive **) my_calloc( - get_max_primitives_in_pb_type(type_descriptors[i].pb_type) - + 1, sizeof(t_cluster_placement_primitive*)); /* too much memory allocated but shouldn't be a problem */ - cluster_placement_stats_list[i].curr_molecule = NULL; - load_cluster_placement_stats_for_pb_graph_node( - &cluster_placement_stats_list[i], - type_descriptors[i].pb_graph_head); - } - } - return cluster_placement_stats_list; -} - -/** - * get next list of primitives for list of logical blocks - * primitives is the list of ptrs to primitives that matches with the list of logical_blocks (by index), assumes memory is preallocated - * - if this is a new block, requeue tried primitives and return a in-flight primitive list to try - * - if this is an old block, put root primitive to tried queue, requeue rest of primitives. try another set of primitives - * - * return TRUE if can find next primitive, FALSE otherwise - * - * cluster_placement_stats - ptr to the current cluster_placement_stats of open complex block - * molecule - molecule to pack into open complex block - * primitives_list - a list of primitives indexed to match logical_block_ptrs of molecule. Expects an allocated array of primitives ptrs as inputs. This function loads the array with the lowest cost primitives that implement molecule - */ -boolean get_next_primitive_list( - INOUTP t_cluster_placement_stats *cluster_placement_stats, - INP t_pack_molecule *molecule, INOUTP t_pb_graph_node **primitives_list, INP int clb_index) { - t_cluster_placement_primitive *cur, *next, *best, *before_best, *prev; - int i; - float cost, lowest_cost; - best = NULL; - before_best = NULL; - - if (cluster_placement_stats->curr_molecule != molecule) { - /* New block, requeue tried primitives and in-flight primitives */ - flush_intermediate_queues(cluster_placement_stats); - - cluster_placement_stats->curr_molecule = molecule; - } else { - /* Hack! Same failed molecule may re-enter if upper stream functions suck, I'm going to make the molecule selector more intelligent, TODO: Remove later */ - if (cluster_placement_stats->in_flight != NULL) { - /* Hack end */ - - /* old block, put root primitive currently inflight to tried queue */ - cur = cluster_placement_stats->in_flight; - next = cur->next_primitive; - cur->next_primitive = cluster_placement_stats->tried; - cluster_placement_stats->tried = cur; - /* should have only one block in flight at any point in time */ - assert(next == NULL); - cluster_placement_stats->in_flight = NULL; - } - } - - /* find next set of blocks - 1. Remove invalid blocks to invalid queue - 2. Find lowest cost array of primitives that implements blocks - 3. When found, move current blocks to in-flight, return lowest cost array of primitives - 4. Return NULL if not found - */ - lowest_cost = HUGE_POSITIVE_FLOAT; - for (i = 0; i < cluster_placement_stats->num_pb_types; i++) { - if (cluster_placement_stats->valid_primitives[i]->next_primitive == NULL) { - continue; /* no more primitives of this type available */ - } - if (primitive_type_feasible( - molecule->logical_block_ptrs[molecule->root]->index, - cluster_placement_stats->valid_primitives[i]->next_primitive->pb_graph_node->pb_type)) { - prev = cluster_placement_stats->valid_primitives[i]; - cur = cluster_placement_stats->valid_primitives[i]->next_primitive; - while (cur) { - /* remove invalid nodes lazily when encountered */ - while (cur && cur->valid == FALSE) { - prev->next_primitive = cur->next_primitive; - cur->next_primitive = cluster_placement_stats->invalid; - cluster_placement_stats->invalid = cur; - cur = prev->next_primitive; - } - if (cur == NULL) { - break; - } - /* try place molecule at root location cur */ - cost = try_place_molecule(molecule, cur->pb_graph_node, - primitives_list, clb_index); - if (cost < lowest_cost) { - lowest_cost = cost; - best = cur; - before_best = prev; - } - prev = cur; - cur = cur->next_primitive; - } - } - } - if (best == NULL) { - /* failed to find a placement */ - for (i = 0; i < molecule->num_blocks; i++) { - primitives_list[i] = NULL; - } - } else { - /* populate primitive list with best */ - cost = try_place_molecule(molecule, best->pb_graph_node, primitives_list, clb_index); - assert(cost == lowest_cost); - - /* take out best node and put it in flight */ - cluster_placement_stats->in_flight = best; - before_best->next_primitive = best->next_primitive; - best->next_primitive = NULL; - } - - if (best == NULL) { - return FALSE; - } - return TRUE; -} - -/** - * Resets one cluster placement stats by clearing incremental costs and returning all primitives to valid queue - */ -void reset_cluster_placement_stats( - INOUTP t_cluster_placement_stats *cluster_placement_stats) { - t_cluster_placement_primitive *cur, *next; - int i; - - /* Requeue primitives */ - flush_intermediate_queues(cluster_placement_stats); - cur = cluster_placement_stats->invalid; - while (cur != NULL) { - next = cur->next_primitive; - requeue_primitive(cluster_placement_stats, cur); - cur = next; - } - cur = cluster_placement_stats->invalid = NULL; - /* reset flags and cost */ - for (i = 0; i < cluster_placement_stats->num_pb_types; i++) { - assert( - cluster_placement_stats->valid_primitives[i] != NULL && cluster_placement_stats->valid_primitives[i]->next_primitive != NULL); - cur = cluster_placement_stats->valid_primitives[i]->next_primitive; - while (cur != NULL) { - cur->incremental_cost = 0; - cur->valid = TRUE; - cur = cur->next_primitive; - } - } - cluster_placement_stats->curr_molecule = NULL; -} - -/** - * Free linked lists found in cluster_placement_stats_list - */ -void free_cluster_placement_stats( - INOUTP t_cluster_placement_stats *cluster_placement_stats_list) { - t_cluster_placement_primitive *cur, *next; - int i, j; - for (i = 0; i < num_types; i++) { - cur = cluster_placement_stats_list[i].tried; - while (cur != NULL) { - next = cur->next_primitive; - free(cur); - cur = next; - } - cur = cluster_placement_stats_list[i].in_flight; - while (cur != NULL) { - next = cur->next_primitive; - free(cur); - cur = next; - } - cur = cluster_placement_stats_list[i].invalid; - while (cur != NULL) { - next = cur->next_primitive; - free(cur); - cur = next; - } - for (j = 0; j < cluster_placement_stats_list[i].num_pb_types; j++) { - cur = - cluster_placement_stats_list[i].valid_primitives[j]->next_primitive; - while (cur != NULL) { - next = cur->next_primitive; - free(cur); - cur = next; - } - free(cluster_placement_stats_list[i].valid_primitives[j]); - } - free(cluster_placement_stats_list[i].valid_primitives); - } - free(cluster_placement_stats_list); -} - -/** - * Put primitive back on queue of valid primitives - * Note that valid status is not changed because if the primitive is not valid, it will get properly collected later - */ -static void requeue_primitive( - INOUTP t_cluster_placement_stats *cluster_placement_stats, - t_cluster_placement_primitive *cluster_placement_primitive) { - int i; - int null_index; - boolean success; - null_index = OPEN; - - success = FALSE; - for (i = 0; i < cluster_placement_stats->num_pb_types; i++) { - if (cluster_placement_stats->valid_primitives[i]->next_primitive == NULL) { - null_index = i; - continue; - } - if (cluster_placement_primitive->pb_graph_node->pb_type - == cluster_placement_stats->valid_primitives[i]->next_primitive->pb_graph_node->pb_type) { - success = TRUE; - cluster_placement_primitive->next_primitive = - cluster_placement_stats->valid_primitives[i]->next_primitive; - cluster_placement_stats->valid_primitives[i]->next_primitive = - cluster_placement_primitive; - } - } - if (success == FALSE) { - assert(null_index != OPEN); - cluster_placement_primitive->next_primitive = - cluster_placement_stats->valid_primitives[null_index]->next_primitive; - cluster_placement_stats->valid_primitives[null_index]->next_primitive = - cluster_placement_primitive; - } -} - -/** - * Add any primitives found in pb_graph_nodes to cluster_placement_stats - * Adds backward link from pb_graph_node to cluster_placement_primitive - */ -static void load_cluster_placement_stats_for_pb_graph_node( - INOUTP t_cluster_placement_stats *cluster_placement_stats, - INOUTP t_pb_graph_node *pb_graph_node) { - int i, j, k; - t_cluster_placement_primitive *placement_primitive; - const t_pb_type *pb_type = pb_graph_node->pb_type; - boolean success; - if (pb_type->modes == 0) { - placement_primitive = (t_cluster_placement_primitive *) my_calloc(1, - sizeof(t_cluster_placement_primitive)); - placement_primitive->pb_graph_node = pb_graph_node; - placement_primitive->valid = TRUE; - pb_graph_node->cluster_placement_primitive = placement_primitive; - placement_primitive->base_cost = compute_primitive_base_cost( - pb_graph_node); - success = FALSE; - i = 0; - while (success == FALSE) { - if (cluster_placement_stats->valid_primitives[i] == NULL - || cluster_placement_stats->valid_primitives[i]->next_primitive->pb_graph_node->pb_type - == pb_graph_node->pb_type) { - if (cluster_placement_stats->valid_primitives[i] == NULL) { - cluster_placement_stats->valid_primitives[i] = (t_cluster_placement_primitive *) my_calloc(1, - sizeof(t_cluster_placement_primitive)); /* head of linked list is empty, makes it easier to remove nodes later */ - cluster_placement_stats->num_pb_types++; - } - success = TRUE; - placement_primitive->next_primitive = - cluster_placement_stats->valid_primitives[i]->next_primitive; - cluster_placement_stats->valid_primitives[i]->next_primitive = - placement_primitive; - } - i++; - } - } else { - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - load_cluster_placement_stats_for_pb_graph_node( - cluster_placement_stats, - &pb_graph_node->child_pb_graph_nodes[i][j][k]); - } - } - } - } -} - -/** - * Commit primitive, invalidate primitives blocked by mode assignment and update costs for primitives in same cluster as current - * Costing is done to try to pack blocks closer to existing primitives - * actual value based on closest common ancestor to committed placement, the farther the ancestor, the less reduction in cost there is - * Side effects: All cluster_placement_primitives may be invalidated/costed in this algorithm - * Al intermediate queues are requeued - */ -void commit_primitive(INOUTP t_cluster_placement_stats *cluster_placement_stats, - INP t_pb_graph_node *primitive) { - t_pb_graph_node *pb_graph_node, *skip; - float incr_cost; - int i, j, k; - int valid_mode; - t_cluster_placement_primitive *cur; - - /* Clear out intermediate queues */ - flush_intermediate_queues(cluster_placement_stats); - - /* commit primitive as used, invalidate it */ - cur = primitive->cluster_placement_primitive; - assert(cur->valid == TRUE); - - cur->valid = FALSE; - incr_cost = -0.01; /* cost of using a node drops as its neighbours are used, this drop should be small compared to scarcity values */ - - pb_graph_node = cur->pb_graph_node; - /* walk up pb_graph_node and update primitives of children */ - while (pb_graph_node->parent_pb_graph_node != NULL) { - skip = pb_graph_node; /* do not traverse stuff that's already traversed */ - valid_mode = pb_graph_node->pb_type->parent_mode->index; - pb_graph_node = pb_graph_node->parent_pb_graph_node; - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; - j < pb_graph_node->pb_type->modes[i].num_pb_type_children; - j++) { - for (k = 0; - k - < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - if (&pb_graph_node->child_pb_graph_nodes[i][j][k] != skip) { - update_primitive_cost_or_status( - &pb_graph_node->child_pb_graph_nodes[i][j][k], - incr_cost, (boolean)(i == valid_mode)); - } - } - } - } - incr_cost /= 10; /* blocks whose ancestor is further away in tree should be affected less than blocks closer in tree */ - } -} - -/** - * Set mode of cluster - */ -void set_mode_cluster_placement_stats(INP t_pb_graph_node *pb_graph_node, - int mode) { - int i, j, k; - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - if (i != mode) { - for (j = 0; - j < pb_graph_node->pb_type->modes[i].num_pb_type_children; - j++) { - for (k = 0; - k - < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - update_primitive_cost_or_status( - &pb_graph_node->child_pb_graph_nodes[i][j][k], 0, - FALSE); - } - } - } - } -} - -/** - * For sibling primitives of pb_graph node, decrease cost - * For modes invalidated by pb_graph_node, invalidate primitive - * int distance is the distance of current pb_graph_node from original - */ -static void update_primitive_cost_or_status(INP t_pb_graph_node *pb_graph_node, - INP float incremental_cost, INP boolean valid) { - int i, j, k; - t_cluster_placement_primitive *placement_primitive; - if (pb_graph_node->pb_type->num_modes == 0) { - /* is primitive */ - placement_primitive = - (t_cluster_placement_primitive*) pb_graph_node->cluster_placement_primitive; - if (valid) { - placement_primitive->incremental_cost += incremental_cost; - } else { - placement_primitive->valid = FALSE; - } - } else { - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; - j < pb_graph_node->pb_type->modes[i].num_pb_type_children; - j++) { - for (k = 0; - k - < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - update_primitive_cost_or_status( - &pb_graph_node->child_pb_graph_nodes[i][j][k], - incremental_cost, valid); - } - } - } - } -} - -/** - * Try place molecule at root location, populate primitives list with locations of placement if successful - */ -static float try_place_molecule(INP t_pack_molecule *molecule, - INP t_pb_graph_node *root, INOUTP t_pb_graph_node **primitives_list, INP int clb_index) { - int list_size, i; - float cost = HUGE_POSITIVE_FLOAT; - list_size = get_array_size_of_molecule(molecule); - - if (primitive_type_feasible( - molecule->logical_block_ptrs[molecule->root]->index, - root->pb_type)) { - if (root->cluster_placement_primitive->valid == TRUE) { - if(root_passes_early_filter(root, molecule, clb_index)) { - for (i = 0; i < list_size; i++) { - primitives_list[i] = NULL; - } - cost = root->cluster_placement_primitive->base_cost - + root->cluster_placement_primitive->incremental_cost; - primitives_list[molecule->root] = root; - if (molecule->type == MOLECULE_FORCED_PACK) { - if (!expand_forced_pack_molecule_placement(molecule, - molecule->pack_pattern->root_block, primitives_list, - &cost)) { - return HUGE_POSITIVE_FLOAT; - } - } - for (i = 0; i < list_size; i++) { - assert( - (primitives_list[i] == NULL) == (molecule->logical_block_ptrs[i] == NULL)); - } - } - } - } - return cost; -} - -/** - * Expand molecule at pb_graph_node - * Assumes molecule and pack pattern connections have fan-out 1 - */ -static boolean expand_forced_pack_molecule_placement( - INP t_pack_molecule *molecule, - INP t_pack_pattern_block *pack_pattern_block, - INOUTP t_pb_graph_node **primitives_list, INOUTP float *cost) { - t_pb_graph_node *pb_graph_node = - primitives_list[pack_pattern_block->block_id]; - t_pb_graph_node *next_primitive; - t_pack_pattern_connections *cur; - int from_pin, from_port; - t_pb_graph_pin *cur_pin, *next_pin; - t_pack_pattern_block *next_block; - - cur = pack_pattern_block->connections; - while (cur) { - if (cur->from_block == pack_pattern_block) { - next_block = cur->to_block; - } else { - next_block = cur->from_block; - } - if (primitives_list[next_block->block_id] == NULL && molecule->logical_block_ptrs[next_block->block_id] != NULL) { - /* first time visiting location */ - - /* find next primitive based on pattern connections, expand next primitive if not visited */ - from_pin = cur->from_pin->pin_number; - from_port = cur->from_pin->port->port_index_by_type; - if (cur->from_block == pack_pattern_block) { - /* forward expand to find next block */ - cur_pin = &pb_graph_node->output_pins[from_port][from_pin]; - next_pin = expand_pack_molecule_pin_edge( - pack_pattern_block->pattern_index, cur_pin, TRUE); - } else { - /* backward expand to find next block */ - assert(cur->to_block == pack_pattern_block); - if (cur->from_pin->port->is_clock) { - cur_pin = &pb_graph_node->clock_pins[from_port][from_pin]; - } else { - cur_pin = &pb_graph_node->input_pins[from_port][from_pin]; - } - next_pin = expand_pack_molecule_pin_edge( - pack_pattern_block->pattern_index, cur_pin, FALSE); - } - /* found next primitive */ - if (next_pin != NULL) { - next_primitive = next_pin->parent_node; - /* Check for legality of placement, if legal, expand from legal placement, if not, return FALSE */ - if (molecule->logical_block_ptrs[next_block->block_id] != NULL - && primitives_list[next_block->block_id] == NULL) { - if (next_primitive->cluster_placement_primitive->valid - == TRUE - && primitive_type_feasible( - molecule->logical_block_ptrs[next_block->block_id]->index, - next_primitive->pb_type)) { - primitives_list[next_block->block_id] = next_primitive; - *cost += - next_primitive->cluster_placement_primitive->base_cost - + next_primitive->cluster_placement_primitive->incremental_cost; - if (!expand_forced_pack_molecule_placement(molecule, - next_block, primitives_list, cost)) { - return FALSE; - } - } else { - return FALSE; - } - } - } else { - return FALSE; - } - } - cur = cur->next; - } - - return TRUE; -} - -/** - * Find next primitive pb_graph_pin - */ -static t_pb_graph_pin *expand_pack_molecule_pin_edge(INP int pattern_id, - INP t_pb_graph_pin *cur_pin, INP boolean forward) { - int i, j, k; - t_pb_graph_pin *temp_pin, *dest_pin; - temp_pin = NULL; - dest_pin = NULL; - if (forward) { - for (i = 0; i < cur_pin->num_output_edges; i++) { - /* one fanout assumption */ - if (cur_pin->output_edges[i]->infer_pattern) { - for (k = 0; k < cur_pin->output_edges[i]->num_output_pins; - k++) { - if (cur_pin->output_edges[i]->output_pins[k]->parent_node->pb_type->num_modes - == 0) { - temp_pin = cur_pin->output_edges[i]->output_pins[k]; - } else { - temp_pin = expand_pack_molecule_pin_edge(pattern_id, - cur_pin->output_edges[i]->output_pins[k], - forward); - } - } - if (temp_pin != NULL) { - assert(dest_pin == NULL || dest_pin == temp_pin); - dest_pin = temp_pin; - } - } else { - for (j = 0; j < cur_pin->output_edges[i]->num_pack_patterns; - j++) { - if (cur_pin->output_edges[i]->pack_pattern_indices[j] - == pattern_id) { - for (k = 0; - k < cur_pin->output_edges[i]->num_output_pins; - k++) { - if (cur_pin->output_edges[i]->output_pins[k]->parent_node->pb_type->num_modes - == 0) { - temp_pin = - cur_pin->output_edges[i]->output_pins[k]; - } else { - temp_pin = - expand_pack_molecule_pin_edge( - pattern_id, - cur_pin->output_edges[i]->output_pins[k], - forward); - } - } - if (temp_pin != NULL) { - assert(dest_pin == NULL || dest_pin == temp_pin); - dest_pin = temp_pin; - } - } - } - } - } - } else { - for (i = 0; i < cur_pin->num_input_edges; i++) { - /* one fanout assumption */ - if (cur_pin->input_edges[i]->infer_pattern) { - for (k = 0; k < cur_pin->input_edges[i]->num_input_pins; k++) { - if (cur_pin->input_edges[i]->input_pins[k]->parent_node->pb_type->num_modes - == 0) { - temp_pin = cur_pin->input_edges[i]->input_pins[k]; - } else { - temp_pin = expand_pack_molecule_pin_edge(pattern_id, - cur_pin->input_edges[i]->input_pins[k], - forward); - } - } - if (temp_pin != NULL) { - assert(dest_pin == NULL || dest_pin == temp_pin); - dest_pin = temp_pin; - } - } else { - for (j = 0; j < cur_pin->input_edges[i]->num_pack_patterns; - j++) { - if (cur_pin->input_edges[i]->pack_pattern_indices[j] - == pattern_id) { - for (k = 0; k < cur_pin->input_edges[i]->num_input_pins; - k++) { - if (cur_pin->input_edges[i]->input_pins[k]->parent_node->pb_type->num_modes - == 0) { - temp_pin = - cur_pin->input_edges[i]->input_pins[k]; - } else { - temp_pin = expand_pack_molecule_pin_edge( - pattern_id, - cur_pin->input_edges[i]->input_pins[k], - forward); - } - } - if (temp_pin != NULL) { - assert(dest_pin == NULL || dest_pin == temp_pin); - dest_pin = temp_pin; - } - } - } - } - } - } - return dest_pin; -} - -static void flush_intermediate_queues( - INOUTP t_cluster_placement_stats *cluster_placement_stats) { - t_cluster_placement_primitive *cur, *next; - cur = cluster_placement_stats->tried; - while (cur != NULL) { - next = cur->next_primitive; - requeue_primitive(cluster_placement_stats, cur); - cur = next; - } - cluster_placement_stats->tried = NULL; - - cur = cluster_placement_stats->in_flight; - if (cur != NULL) { - next = cur->next_primitive; - requeue_primitive(cluster_placement_stats, cur); - /* should have at most one block in flight at any point in time */ - assert(next == NULL); - } - cluster_placement_stats->in_flight = NULL; -} - -/* Determine max index + 1 of molecule */ -int get_array_size_of_molecule(t_pack_molecule *molecule) { - if (molecule->type == MOLECULE_FORCED_PACK) { - return molecule->pack_pattern->num_blocks; - } else { - return molecule->num_blocks; - } -} - -/* Given logical block, determines if a free primitive exists for it */ -boolean exists_free_primitive_for_logical_block( - INOUTP t_cluster_placement_stats *cluster_placement_stats, - INP int ilogical_block) { - int i; - t_cluster_placement_primitive *cur, *prev; - - /* might have a primitive in flight that's still valid */ - if (cluster_placement_stats->in_flight) { - if (primitive_type_feasible(ilogical_block, - cluster_placement_stats->in_flight->pb_graph_node->pb_type)) { - return TRUE; - } - } - - /* Look through list of available primitives to see if any valid */ - for (i = 0; i < cluster_placement_stats->num_pb_types; i++) { - if (cluster_placement_stats->valid_primitives[i]->next_primitive == NULL) { - continue; /* no more primitives of this type available */ - } - if (primitive_type_feasible(ilogical_block, - cluster_placement_stats->valid_primitives[i]->next_primitive->pb_graph_node->pb_type)) { - prev = cluster_placement_stats->valid_primitives[i]; - cur = cluster_placement_stats->valid_primitives[i]->next_primitive; - while (cur) { - /* remove invalid nodes lazily when encountered */ - while (cur && cur->valid == FALSE) { - prev->next_primitive = cur->next_primitive; - cur->next_primitive = cluster_placement_stats->invalid; - cluster_placement_stats->invalid = cur; - cur = prev->next_primitive; - } - if (cur == NULL) { - break; - } - return TRUE; - } - } - } - - return FALSE; -} - - -void reset_tried_but_unused_cluster_placements( - INOUTP t_cluster_placement_stats *cluster_placement_stats) { - flush_intermediate_queues(cluster_placement_stats); -} - - -/* Quick, additional filter to see if root is feasible for molecule - - Limitation: This code can absorb a single atom by a "forced connection". A forced connection is one where there is no interconnect flexibility connecting - two primitives so if one primitive is used, then the other must also be used. - - TODO: jluu - Many ways to make this either more efficient or more robust. - 1. For forced connections, I can get the packer to try forced connections first thus avoid trying out other locations that - I know are bad thus saving runtime and potentially improving robustness because the placement cost function is not always 100%. - 2. I need to extend this so that molecules can be pulled in instead of just atoms. -*/ -static boolean root_passes_early_filter(INP t_pb_graph_node *root, INP t_pack_molecule *molecule, INP int clb_index) { - int i, j; - boolean feasible; - t_logical_block *root_block; - t_model_ports *model_port; - int inet; - int isink; - t_pb_graph_pin *sink_pb_graph_pin; - - feasible = TRUE; - root_block = molecule->logical_block_ptrs[molecule->root]; - for(i = 0; feasible && i < root->num_output_ports; i++) { - for(j = 0; feasible && j < root->num_output_pins[i]; j++) { - if(root->output_pins[i][j].is_forced_connection) { - model_port = root->output_pins[i][j].port->model_port; - inet = root_block->output_nets[model_port->index][j]; - if(inet != OPEN) { - /* This output pin has a dedicated connection to one output, make sure that molecule works */ - if(molecule->type == MOLECULE_SINGLE_ATOM) { - feasible = FALSE; /* There is only one case where an atom can fit in here, so by default, feasibility is false unless proven otherwise */ - if(vpack_net[inet].num_sinks == 1) { - isink = vpack_net[inet].node_block[1]; - if(logical_block[isink].clb_index == clb_index) { - sink_pb_graph_pin = &root->output_pins[i][j]; - while(sink_pb_graph_pin->num_output_edges != 0) { - assert(sink_pb_graph_pin->num_output_edges == 1); - assert(sink_pb_graph_pin->output_edges[0]->num_output_pins == 1); - sink_pb_graph_pin = sink_pb_graph_pin->output_edges[0]->output_pins[0]; - } - if(sink_pb_graph_pin->parent_node == logical_block[isink].pb->pb_graph_node) { - /* There is a logical block mapped to the physical position that pulls in the atom in question */ - feasible = TRUE; - } - } - } - } - } - } - } - } - return feasible; -} - diff --git a/vpr7_x2p/vpr/SRC/pack/cluster_placement.h b/vpr7_x2p/vpr/SRC/pack/cluster_placement.h deleted file mode 100644 index 92265d3e3..000000000 --- a/vpr7_x2p/vpr/SRC/pack/cluster_placement.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - Find placement for group of logical blocks in complex block - Author: Jason Luu - */ - -#ifndef CLUSTER_PLACEMENT_H -#define CLUSTER_PLACEMENT_H -#include "arch_types.h" -#include "util.h" - -t_cluster_placement_stats *alloc_and_load_cluster_placement_stats(void); -boolean get_next_primitive_list( - INOUTP t_cluster_placement_stats *cluster_placement_stats, - INP t_pack_molecule *molecule, - INOUTP t_pb_graph_node **primitives_list, - INP int clb_index); -void commit_primitive(INOUTP t_cluster_placement_stats *cluster_placement_stats, - INP t_pb_graph_node *primitive); -void set_mode_cluster_placement_stats(INP t_pb_graph_node *complex_block, - int mode); -void reset_cluster_placement_stats( - INOUTP t_cluster_placement_stats *cluster_placement_stats); -void free_cluster_placement_stats( - INOUTP t_cluster_placement_stats *cluster_placement_stats); - -int get_array_size_of_molecule(t_pack_molecule *molecule); -boolean exists_free_primitive_for_logical_block( - INOUTP t_cluster_placement_stats *cluster_placement_stats, - INP int ilogical_block); - -void reset_tried_but_unused_cluster_placements( - INOUTP t_cluster_placement_stats *cluster_placement_stats); - - -#endif diff --git a/vpr7_x2p/vpr/SRC/pack/output_blif.c b/vpr7_x2p/vpr/SRC/pack/output_blif.c deleted file mode 100644 index a11affe38..000000000 --- a/vpr7_x2p/vpr/SRC/pack/output_blif.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - Jason Luu 2008 - Print blif representation of circuit - Assumptions: Assumes first valid rr input to node is the correct rr input - Assumes clocks are routed globally - */ - -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "output_blif.h" -#include "ReadOptions.h" - -#define LINELENGTH 1024 -#define TABLENGTH 1 - -/****************** Subroutines local to this module ************************/ - -/**************** Subroutine definitions ************************************/ - -static void print_string(const char *str_ptr, int *column, FILE * fpout) { - - /* Prints string without making any lines longer than LINELENGTH. Column * - * points to the column in which the next character will go (both used and * - * updated), and fpout points to the output file. */ - - int len; - - len = strlen(str_ptr); - if (len + 3 > LINELENGTH) { - vpr_printf(TIO_MESSAGE_ERROR, "in print_string: String %s is too long for desired maximum line length.\n", str_ptr); - exit(1); - } - - if (*column + len + 2 > LINELENGTH) { - fprintf(fpout, "\\ \n"); - *column = TABLENGTH; - } - - fprintf(fpout, "%s ", str_ptr); - *column += len + 1; -} - -static void print_net_name(int inet, int *column, FILE * fpout) { - - /* This routine prints out the vpack_net name (or open) and limits the * - * length of a line to LINELENGTH characters by using \ to continue * - * lines. net_num is the index of the vpack_net to be printed, while * - * column points to the current printing column (column is both * - * used and updated by this routine). fpout is the output file * - * pointer. */ - - const char *str_ptr; - - if (inet == OPEN) - str_ptr = "open"; - else - str_ptr = vpack_net[inet].name; - - print_string(str_ptr, column, fpout); -} - -static int find_fanin_rr_node(t_pb *cur_pb, enum PORTS type, int rr_node_index) { - /* finds first fanin rr_node */ - t_pb *parent, *sibling, *child; - int net_num, irr_node; - int i, j, k, ichild_type, ichild_inst; - int hack_empty_route_through; - t_pb_graph_node *hack_empty_pb_graph_node; - - hack_empty_route_through = OPEN; - - net_num = rr_node[rr_node_index].net_num; - - parent = cur_pb->parent_pb; - - if (net_num == OPEN) { - return OPEN; - } - - if (type == IN_PORT) { - /* check parent inputs for valid connection */ - for (i = 0; i < parent->pb_graph_node->num_input_ports; i++) { - for (j = 0; j < parent->pb_graph_node->num_input_pins[i]; j++) { - irr_node = - parent->pb_graph_node->input_pins[i][j].pin_count_in_cluster; - if (rr_node[irr_node].net_num == net_num) { - if (cur_pb->pb_graph_node->pb_type->model - && strcmp( - cur_pb->pb_graph_node->pb_type->model->name, - MODEL_LATCH) == 0) { - /* HACK: latches are special becuase LUTs can be set to route-through mode for them - I will assume that the input to a LATCH can always come from a parent input pin - this only works for hierarchical soft logic structures that follow LUT -> LATCH design - must do it better later - */ - return irr_node; - } - hack_empty_route_through = irr_node; - for (k = 0; k < rr_node[irr_node].num_edges; k++) { - if (rr_node[irr_node].edges[k] == rr_node_index) { - return irr_node; - } - } - } - } - } - /* check parent clocks for valid connection */ - for (i = 0; i < parent->pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < parent->pb_graph_node->num_clock_pins[i]; j++) { - irr_node = - parent->pb_graph_node->clock_pins[i][j].pin_count_in_cluster; - if (rr_node[irr_node].net_num == net_num) { - for (k = 0; k < rr_node[irr_node].num_edges; k++) { - if (rr_node[irr_node].edges[k] == rr_node_index) { - return irr_node; - } - } - } - } - } - /* check siblings for connection */ - if (parent) { - for (ichild_type = 0; - ichild_type - < parent->pb_graph_node->pb_type->modes[parent->mode].num_pb_type_children; - ichild_type++) { - for (ichild_inst = 0; - ichild_inst - < parent->pb_graph_node->pb_type->modes[parent->mode].pb_type_children[ichild_type].num_pb; - ichild_inst++) { - if (parent->child_pbs[ichild_type] - && parent->child_pbs[ichild_type][ichild_inst].name - != NULL) { - sibling = &parent->child_pbs[ichild_type][ichild_inst]; - for (i = 0; - i < sibling->pb_graph_node->num_output_ports; - i++) { - for (j = 0; - j - < sibling->pb_graph_node->num_output_pins[i]; - j++) { - irr_node = - sibling->pb_graph_node->output_pins[i][j].pin_count_in_cluster; - if (rr_node[irr_node].net_num == net_num) { - for (k = 0; k < rr_node[irr_node].num_edges; - k++) { - if (rr_node[irr_node].edges[k] - == rr_node_index) { - return irr_node; - } - } - } - } - } - } else { - /* hack just in case routing is down through an empty cluster */ - hack_empty_pb_graph_node = - &parent->pb_graph_node->child_pb_graph_nodes[ichild_type][0][ichild_inst]; - for (i = 0; - i < hack_empty_pb_graph_node->num_output_ports; - i++) { - for (j = 0; - j - < hack_empty_pb_graph_node->num_output_pins[i]; - j++) { - irr_node = - hack_empty_pb_graph_node->output_pins[i][j].pin_count_in_cluster; - if (rr_node[irr_node].net_num == net_num) { - for (k = 0; k < rr_node[irr_node].num_edges; - k++) { - if (rr_node[irr_node].edges[k] - == rr_node_index) { - return irr_node; - } - } - } - } - } - } - } - } - } - } else { - assert(type == OUT_PORT); - - /* check children for connection */ - for (ichild_type = 0; - ichild_type - < cur_pb->pb_graph_node->pb_type->modes[cur_pb->mode].num_pb_type_children; - ichild_type++) { - for (ichild_inst = 0; - ichild_inst - < cur_pb->pb_graph_node->pb_type->modes[cur_pb->mode].pb_type_children[ichild_type].num_pb; - ichild_inst++) { - if (cur_pb->child_pbs[ichild_type] - && cur_pb->child_pbs[ichild_type][ichild_inst].name - != NULL) { - child = &cur_pb->child_pbs[ichild_type][ichild_inst]; - for (i = 0; i < child->pb_graph_node->num_output_ports; - i++) { - for (j = 0; - j < child->pb_graph_node->num_output_pins[i]; - j++) { - irr_node = - child->pb_graph_node->output_pins[i][j].pin_count_in_cluster; - if (rr_node[irr_node].net_num == net_num) { - for (k = 0; k < rr_node[irr_node].num_edges; - k++) { - if (rr_node[irr_node].edges[k] - == rr_node_index) { - return irr_node; - } - } - hack_empty_route_through = irr_node; - } - } - } - } - } - } - - /* If not in children, check current pb inputs for valid connection */ - for (i = 0; i < cur_pb->pb_graph_node->num_input_ports; i++) { - for (j = 0; j < cur_pb->pb_graph_node->num_input_pins[i]; j++) { - irr_node = - cur_pb->pb_graph_node->input_pins[i][j].pin_count_in_cluster; - if (rr_node[irr_node].net_num == net_num) { - hack_empty_route_through = irr_node; - for (k = 0; k < rr_node[irr_node].num_edges; k++) { - if (rr_node[irr_node].edges[k] == rr_node_index) { - return irr_node; - } - } - } - } - } - } - - /* TODO: Once I find a way to output routing in empty blocks then code should never reach here, for now, return OPEN */ - vpr_printf(TIO_MESSAGE_INFO, "Use hack in blif dumper (do properly later): connecting net %s #%d for pb %s type %s\n", - vpack_net[net_num].name, net_num, cur_pb->name, - cur_pb->pb_graph_node->pb_type->name); - - assert(hack_empty_route_through != OPEN); - return hack_empty_route_through; -} - -static void print_primitive(FILE *fpout, int iblk) { - t_pb *pb; - int clb_index; - int i, j, k, node_index; - int in_port_index, out_port_index, clock_port_index; - struct s_linked_vptr *truth_table; - const t_pb_type *pb_type; - - pb = logical_block[iblk].pb; - pb_type = pb->pb_graph_node->pb_type; - clb_index = logical_block[iblk].clb_index; - - if (logical_block[iblk].type == VPACK_INPAD - || logical_block[iblk].type == VPACK_OUTPAD) { - /* do nothing */ - } else if (logical_block[iblk].type == VPACK_LATCH) { - fprintf(fpout, ".latch "); - - in_port_index = 0; - out_port_index = 0; - clock_port_index = 0; - for (i = 0; i < pb_type->num_ports; i++) { - if (pb_type->ports[i].type == IN_PORT - && pb_type->ports[i].is_clock == FALSE) { - assert(pb_type->ports[i].num_pins == 1); - assert(logical_block[iblk].input_nets[i][0] != OPEN); - node_index = - pb->pb_graph_node->input_pins[in_port_index][0].pin_count_in_cluster; - fprintf(fpout, "clb_%d_rr_node_%d ", clb_index, - find_fanin_rr_node(pb, pb_type->ports[i].type, - node_index)); - in_port_index++; - } - } - for (i = 0; i < pb_type->num_ports; i++) { - if (pb_type->ports[i].type == OUT_PORT) { - assert(pb_type->ports[i].num_pins == 1 && out_port_index == 0); - node_index = - pb->pb_graph_node->output_pins[out_port_index][0].pin_count_in_cluster; - fprintf(fpout, "clb_%d_rr_node_%d re ", clb_index, node_index); - out_port_index++; - } - } - for (i = 0; i < pb_type->num_ports; i++) { - if (pb_type->ports[i].type == IN_PORT - && pb_type->ports[i].is_clock == TRUE) { - assert(logical_block[iblk].clock_net != OPEN); - node_index = - pb->pb_graph_node->clock_pins[clock_port_index][0].pin_count_in_cluster; - fprintf(fpout, "clb_%d_rr_node_%d 2", clb_index, - find_fanin_rr_node(pb, pb_type->ports[i].type, - node_index)); - clock_port_index++; - } - } - fprintf(fpout, "\n"); - } else if (logical_block[iblk].type == VPACK_COMB) { - if (strcmp(logical_block[iblk].model->name, "names") == 0) { - fprintf(fpout, ".names "); - in_port_index = 0; - out_port_index = 0; - for (i = 0; i < pb_type->num_ports; i++) { - if (pb_type->ports[i].type == IN_PORT - && pb_type->ports[i].is_clock == FALSE) { - /* This is a LUT - LUTs receive special handling because a LUT has logically equivalent inputs. - The intra-logic block router may have taken advantage of logical equivalence so we need to unscramble the inputs when we output the LUT logic. - */ - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - if (logical_block[iblk].input_nets[in_port_index][j] != OPEN) { - for (k = 0; k < pb_type->ports[i].num_pins; k++) { - node_index = pb->pb_graph_node->input_pins[in_port_index][k].pin_count_in_cluster; - if(rr_node[node_index].net_num != OPEN) { - if(rr_node[node_index].net_num == logical_block[iblk].input_nets[in_port_index][j]) { - fprintf(fpout, "clb_%d_rr_node_%d ", clb_index, - find_fanin_rr_node(pb, - pb_type->ports[i].type, - node_index)); - break; - } - } - } - if(k == pb_type->ports[i].num_pins) { - /* Failed to find LUT input, a netlist error has occurred */ - vpr_printf(TIO_MESSAGE_ERROR, "LUT %s missing input %s post packing. This is a VPR internal error, report to vpr@eecg.utoronto.ca\n", - logical_block[iblk].name, vpack_net[logical_block[iblk].input_nets[in_port_index][j]].name); - exit(1); - } - } - } - in_port_index++; - } - } - for (i = 0; i < pb_type->num_ports; i++) { - if (pb_type->ports[i].type == OUT_PORT) { - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - node_index = - pb->pb_graph_node->output_pins[out_port_index][j].pin_count_in_cluster; - fprintf(fpout, "clb_%d_rr_node_%d\n", clb_index, - node_index); - } - out_port_index++; - } - } - truth_table = logical_block[iblk].truth_table; - while (truth_table) { - fprintf(fpout, "%s\n", (char *) truth_table->data_vptr); - truth_table = truth_table->next; - } - } else { - vpr_printf(TIO_MESSAGE_WARNING, "TODO: Implement blif dumper for subckt %s model %s", logical_block[iblk].name, logical_block[iblk].model->name); - } - } -} - -static void print_pb(FILE *fpout, t_pb * pb, int clb_index) { - - int column; - int i, j, k; - const t_pb_type *pb_type; - t_mode *mode; - int in_port_index, out_port_index, node_index; - - pb_type = pb->pb_graph_node->pb_type; - mode = &pb_type->modes[pb->mode]; - column = 0; - if (pb_type->num_modes == 0) { - print_primitive(fpout, pb->logical_block); - } else { - in_port_index = 0; - out_port_index = 0; - for (i = 0; i < pb_type->num_ports; i++) { - if (!pb_type->ports[i].is_clock) { - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - /* print .blif buffer to represent routing */ - column = 0; - if (pb_type->ports[i].type == OUT_PORT) { - node_index = - pb->pb_graph_node->output_pins[out_port_index][j].pin_count_in_cluster; - if (rr_node[node_index].net_num != OPEN) { - fprintf(fpout, ".names clb_%d_rr_node_%d ", - clb_index, - find_fanin_rr_node(pb, - pb_type->ports[i].type, - node_index)); - if (pb->parent_pb) { - fprintf(fpout, "clb_%d_rr_node_%d ", clb_index, - node_index); - } else { - print_net_name(rr_node[node_index].net_num, - &column, fpout); - } - fprintf(fpout, "\n1 1\n"); - if (pb->parent_pb == NULL) { - for (k = 1; - k - <= vpack_net[rr_node[node_index].net_num].num_sinks; - k++) { - /* output pads pre-pended with "out:", must remove */ - if (logical_block[vpack_net[rr_node[node_index].net_num].node_block[k]].type - == VPACK_OUTPAD - && strcmp( - logical_block[vpack_net[rr_node[node_index].net_num].node_block[k]].name - + 4, - vpack_net[rr_node[node_index].net_num].name) - != 0) { - fprintf(fpout, - ".names clb_%d_rr_node_%d %s", - clb_index, - find_fanin_rr_node(pb, - pb_type->ports[i].type, - node_index), - logical_block[vpack_net[rr_node[node_index].net_num].node_block[k]].name - + 4); - fprintf(fpout, "\n1 1\n"); - } - } - } - } - - } else { - node_index = - pb->pb_graph_node->input_pins[in_port_index][j].pin_count_in_cluster; - if (rr_node[node_index].net_num != OPEN) { - - fprintf(fpout, ".names "); - if (pb->parent_pb) { - fprintf(fpout, "clb_%d_rr_node_%d ", clb_index, - find_fanin_rr_node(pb, - pb_type->ports[i].type, - node_index)); - } else { - print_net_name(rr_node[node_index].net_num, - &column, fpout); - } - fprintf(fpout, "clb_%d_rr_node_%d", clb_index, - node_index); - fprintf(fpout, "\n1 1\n"); - } - } - } - } - if (pb_type->ports[i].type == OUT_PORT) { - out_port_index++; - } else { - in_port_index++; - } - } - for (i = 0; i < mode->num_pb_type_children; i++) { - for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { - /* If child pb is not used but routing is used, I must print things differently */ - if ((pb->child_pbs[i] != NULL) - && (pb->child_pbs[i][j].name != NULL)) { - print_pb(fpout, &pb->child_pbs[i][j], clb_index); - } else { - /* do nothing for now, we'll print something later if needed */ - } - } - } - } -} - -static void print_clusters(t_block *clb, int num_clusters, FILE * fpout) { - - /* Prints out one cluster (clb). Both the external pins and the * - * internal connections are printed out. */ - - int icluster; - - for (icluster = 0; icluster < num_clusters; icluster++) { - rr_node = clb[icluster].pb->rr_graph; - if (clb[icluster].type != IO_TYPE) - print_pb(fpout, clb[icluster].pb, icluster); - } -} - -void output_blif (t_block *clb, int num_clusters, boolean global_clocks, - boolean * is_clock, const char *out_fname, boolean skip_clustering) { - - /* - * This routine dumps out the output netlist in a format suitable for * - * input to vpr. This routine also dumps out the internal structure of * - * the cluster, in essentially a graph based format. */ - - FILE *fpout; - int bnum, column; - struct s_linked_vptr *p_io_removed; - int i; - - fpout = my_fopen(out_fname, "w", 0); - - column = 0; - fprintf(fpout, ".model %s\n", blif_circuit_name); - - /* Print out all input and output pads. */ - fprintf(fpout, "\n.inputs "); - for (bnum = 0; bnum < num_logical_blocks; bnum++) { - if (logical_block[bnum].type == VPACK_INPAD) { - print_string(logical_block[bnum].name, &column, fpout); - } - } - p_io_removed = circuit_p_io_removed; - while (p_io_removed) { - print_string((char*) p_io_removed->data_vptr, &column, fpout); - p_io_removed = p_io_removed->next; - } - - column = 0; - fprintf(fpout, "\n.outputs "); - for (bnum = 0; bnum < num_logical_blocks; bnum++) { - if (logical_block[bnum].type == VPACK_OUTPAD) { - /* remove output prefix "out:" */ - print_string(logical_block[bnum].name + 4, &column, fpout); - } - } - - column = 0; - - fprintf(fpout, "\n\n"); - - /* print logic of clusters */ - print_clusters(clb, num_clusters, fpout); - - /* handle special case: input goes straight to output without going through any logic */ - for (bnum = 0; bnum < num_logical_blocks; bnum++) { - if (logical_block[bnum].type == VPACK_INPAD) { - for (i = 1; - i - <= vpack_net[logical_block[bnum].output_nets[0][0]].num_sinks; - i++) { - if (logical_block[vpack_net[logical_block[bnum].output_nets[0][0]].node_block[i]].type - == VPACK_OUTPAD) { - fprintf(fpout, ".names "); - print_string(logical_block[bnum].name, &column, fpout); - print_string( - logical_block[vpack_net[logical_block[bnum].output_nets[0][0]].node_block[i]].name - + 4, &column, fpout); - fprintf(fpout, "\n1 1\n"); - } - } - } - } - - fprintf(fpout, "\n.end\n"); - - fclose(fpout); -} diff --git a/vpr7_x2p/vpr/SRC/pack/output_blif.h b/vpr7_x2p/vpr/SRC/pack/output_blif.h deleted file mode 100644 index 38463de61..000000000 --- a/vpr7_x2p/vpr/SRC/pack/output_blif.h +++ /dev/null @@ -1,3 +0,0 @@ -void output_blif (t_block *clb, int num_clusters, boolean global_clocks, - boolean * is_clock, const char *out_fname, boolean skip_clustering); - diff --git a/vpr7_x2p/vpr/SRC/pack/output_clustering.c b/vpr7_x2p/vpr/SRC/pack/output_clustering.c deleted file mode 100755 index 9d08e66a0..000000000 --- a/vpr7_x2p/vpr/SRC/pack/output_clustering.c +++ /dev/null @@ -1,615 +0,0 @@ -/* - Jason Luu 2008 - Print complex block information to a file - */ - -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "output_clustering.h" -#include "read_xml_arch_file.h" - -#define LINELENGTH 1024 -#define TAB_LENGTH 4 - -/****************** Subroutines local to this module ************************/ - -/**************** Subroutine definitions ************************************/ - -static void print_tabs(FILE *fpout, int num_tabs) { - int i; - for (i = 0; i < num_tabs; i++) { - fprintf(fpout, "\t"); - } -} - -static void print_string(const char *str_ptr, int *column, int num_tabs, FILE * fpout) { - - /* Prints string without making any lines longer than LINELENGTH. Column * - * points to the column in which the next character will go (both used and * - * updated), and fpout points to the output file. */ - - int len; - - len = strlen(str_ptr); - if (len + 3 > LINELENGTH) { - vpr_printf(TIO_MESSAGE_ERROR, "in print_string: String %s is too long for desired maximum line length.\n", str_ptr); - exit(1); - } - - if (*column + len + 2 > LINELENGTH) { - fprintf(fpout, "\n"); - print_tabs(fpout, num_tabs); - *column = num_tabs * TAB_LENGTH; - } - - fprintf(fpout, "%s ", str_ptr); - *column += len + 1; -} - -static void print_net_name(int inet, int *column, int num_tabs, FILE * fpout) { - - /* This routine prints out the vpack_net name (or open) and limits the * - * length of a line to LINELENGTH characters by using \ to continue * - * lines. net_num is the index of the vpack_net to be printed, while * - * column points to the current printing column (column is both * - * used and updated by this routine). fpout is the output file * - * pointer. */ - - const char *str_ptr; - - if (inet == OPEN) - str_ptr = "open"; - else - str_ptr = vpack_net[inet].name; - - print_string(str_ptr, column, num_tabs, fpout); -} - -static void print_interconnect(int inode, int *column, int num_tabs, - FILE * fpout) { - - /* This routine prints out the vpack_net name (or open) and limits the * - * length of a line to LINELENGTH characters by using \ to continue * - * lines. net_num is the index of the vpack_net to be printed, while * - * column points to the current printing column (column is both * - * used and updated by this routine). fpout is the output file * - * pointer. */ - - char *str_ptr, *name; - int prev_node, prev_edge; - int len; - - if (rr_node[inode].net_num == OPEN) { - print_string("open", column, num_tabs, fpout); - } else { - str_ptr = NULL; - prev_node = rr_node[inode].prev_node; - prev_edge = rr_node[inode].prev_edge; - - if (prev_node == OPEN - && rr_node[inode].pb_graph_pin->port->parent_pb_type->num_modes - == 0 - && rr_node[inode].pb_graph_pin->port->type == OUT_PORT) { /* This is a primitive output */ - print_net_name(rr_node[inode].net_num, column, num_tabs, fpout); - } else { - name = - rr_node[prev_node].pb_graph_pin->output_edges[prev_edge]->interconnect->name; - if (rr_node[prev_node].pb_graph_pin->port->parent_pb_type->depth - >= rr_node[inode].pb_graph_pin->port->parent_pb_type->depth) { - /* Connections from siblings or children should have an explicit index, connections from parent does not need an explicit index */ - len = - strlen( - rr_node[prev_node].pb_graph_pin->parent_node->pb_type->name) - + rr_node[prev_node].pb_graph_pin->parent_node->placement_index - / 10 - + strlen( - rr_node[prev_node].pb_graph_pin->port->name) - + rr_node[prev_node].pb_graph_pin->pin_number - / 10 + strlen(name) + 11; - str_ptr = (char*)my_malloc(len * sizeof(char)); - sprintf(str_ptr, "%s[%d].%s[%d]->%s ", - rr_node[prev_node].pb_graph_pin->parent_node->pb_type->name, - rr_node[prev_node].pb_graph_pin->parent_node->placement_index, - rr_node[prev_node].pb_graph_pin->port->name, - rr_node[prev_node].pb_graph_pin->pin_number, name); - /* For debug - if (0 == strcmp("fle_phy", - rr_node[prev_node].pb_graph_pin->parent_node->pb_type->name)) { - printf("debugging point reached!\n"); - } - */ - } else { - len = - strlen( - rr_node[prev_node].pb_graph_pin->parent_node->pb_type->name) - + strlen( - rr_node[prev_node].pb_graph_pin->port->name) - + rr_node[prev_node].pb_graph_pin->pin_number - / 10 + strlen(name) + 8; - str_ptr = (char*)my_malloc(len * sizeof(char)); - sprintf(str_ptr, "%s.%s[%d]->%s ", - rr_node[prev_node].pb_graph_pin->parent_node->pb_type->name, - rr_node[prev_node].pb_graph_pin->port->name, - rr_node[prev_node].pb_graph_pin->pin_number, name); - } - print_string(str_ptr, column, num_tabs, fpout); - } - if (str_ptr) - free(str_ptr); - } -} - -static void print_open_pb_graph_node(t_pb_graph_node * pb_graph_node, - int pb_index, boolean is_used, int tab_depth, FILE * fpout) { - int column = 0; - int i, j, k, m; - const t_pb_type * pb_type, *child_pb_type; - t_mode * mode = NULL; - int prev_edge, prev_node; - t_pb_graph_pin *pb_graph_pin; - int mode_of_edge, port_index, node_index; - - mode_of_edge = UNDEFINED; - - pb_type = pb_graph_node->pb_type; - - print_tabs(fpout, tab_depth); - - if (is_used) { - /* Determine mode if applicable */ - port_index = 0; - for (i = 0; i < pb_type->num_ports; i++) { - if (pb_type->ports[i].type == OUT_PORT) { - assert(!pb_type->ports[i].is_clock); - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - node_index = - pb_graph_node->output_pins[port_index][j].pin_count_in_cluster; - if (pb_type->num_modes > 0 - && rr_node[node_index].net_num != OPEN) { - prev_edge = rr_node[node_index].prev_edge; - prev_node = rr_node[node_index].prev_node; - pb_graph_pin = rr_node[prev_node].pb_graph_pin; - mode_of_edge = - pb_graph_pin->output_edges[prev_edge]->interconnect->parent_mode_index; - assert( - mode == NULL || &pb_type->modes[mode_of_edge] == mode); - mode = &pb_type->modes[mode_of_edge]; - } - } - port_index++; - } - } - - assert(mode != NULL && mode_of_edge != UNDEFINED); - fprintf(fpout, - "\n", - pb_graph_node->pb_type->name, pb_index, mode->name); - - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\n"); - port_index = 0; - for (i = 0; i < pb_type->num_ports; i++) { - if (!pb_type->ports[i].is_clock - && pb_type->ports[i].type == IN_PORT) { - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\t", - pb_graph_node->pb_type->ports[i].name); - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - node_index = - pb_graph_node->input_pins[port_index][j].pin_count_in_cluster; - print_interconnect(node_index, &column, tab_depth + 2, - fpout); - } - fprintf(fpout, "\n"); - port_index++; - } - } - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\n"); - - column = tab_depth * TAB_LENGTH + 8; /* Next column I will write to. */ - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\n"); - port_index = 0; - for (i = 0; i < pb_type->num_ports; i++) { - if (pb_type->ports[i].type == OUT_PORT) { - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\t", - pb_graph_node->pb_type->ports[i].name); - assert(!pb_type->ports[i].is_clock); - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - node_index = - pb_graph_node->output_pins[port_index][j].pin_count_in_cluster; - print_interconnect(node_index, &column, tab_depth + 2, - fpout); - } - fprintf(fpout, "\n"); - port_index++; - } - } - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\n"); - - column = tab_depth * TAB_LENGTH + 8; /* Next column I will write to. */ - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\n"); - port_index = 0; - for (i = 0; i < pb_type->num_ports; i++) { - if (pb_type->ports[i].is_clock - && pb_type->ports[i].type == IN_PORT) { - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\t", - pb_graph_node->pb_type->ports[i].name); - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - node_index = - pb_graph_node->clock_pins[port_index][j].pin_count_in_cluster; - print_interconnect(node_index, &column, tab_depth + 2, - fpout); - } - fprintf(fpout, "\n"); - port_index++; - } - } - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\n"); - - if (pb_type->num_modes > 0) { - for (i = 0; i < mode->num_pb_type_children; i++) { - child_pb_type = &mode->pb_type_children[i]; - for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { - port_index = 0; - is_used = FALSE; - for (k = 0; k < child_pb_type->num_ports && !is_used; k++) { - if (child_pb_type->ports[k].type == OUT_PORT) { - for (m = 0; m < child_pb_type->ports[k].num_pins; - m++) { - node_index = - pb_graph_node->child_pb_graph_nodes[mode_of_edge][i][j].output_pins[port_index][m].pin_count_in_cluster; - if (rr_node[node_index].net_num != OPEN) { - is_used = TRUE; - break; - } - } - port_index++; - } - } - print_open_pb_graph_node( - &pb_graph_node->child_pb_graph_nodes[mode_of_edge][i][j], - j, is_used, tab_depth + 1, fpout); - } - } - } - - print_tabs(fpout, tab_depth); - fprintf(fpout, "\n"); - } else { - fprintf(fpout, "\n", - pb_graph_node->pb_type->name, pb_index); - } -} - -static void print_pb(FILE *fpout, t_pb * pb, int pb_index, int tab_depth) { - - int column; - int i, j, k, m; - const t_pb_type *pb_type, *child_pb_type; - t_pb_graph_node *pb_graph_node; - t_mode *mode; - int port_index, node_index; - boolean is_used; - - pb_type = pb->pb_graph_node->pb_type; - pb_graph_node = pb->pb_graph_node; - mode = &pb_type->modes[pb->mode]; - column = tab_depth * TAB_LENGTH + 8; /* Next column I will write to. */ - print_tabs(fpout, tab_depth); - if (pb_type->num_modes == 0) { - fprintf(fpout, "\n", pb->name, - pb_type->name, pb_index); - } else { - fprintf(fpout, "\n", - pb->name, pb_type->name, pb_index, mode->name); - } - - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\n"); - port_index = 0; - for (i = 0; i < pb_type->num_ports; i++) { - if (!pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT) { - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\t", - pb_graph_node->pb_type->ports[i].name); - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - node_index = - pb->pb_graph_node->input_pins[port_index][j].pin_count_in_cluster; - if (pb_type->parent_mode == NULL) { - print_net_name(rr_node[node_index].net_num, &column, - tab_depth, fpout); - } else { - print_interconnect(node_index, &column, tab_depth + 2, - fpout); - } - } - fprintf(fpout, "\n"); - port_index++; - } - } - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\n"); - - column = tab_depth * TAB_LENGTH + 8; /* Next column I will write to. */ - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\n"); - port_index = 0; - for (i = 0; i < pb_type->num_ports; i++) { - if (pb_type->ports[i].type == OUT_PORT) { - assert(!pb_type->ports[i].is_clock); - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\t", - pb_graph_node->pb_type->ports[i].name); - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - node_index = - pb->pb_graph_node->output_pins[port_index][j].pin_count_in_cluster; - print_interconnect(node_index, &column, tab_depth + 2, fpout); - } - fprintf(fpout, "\n"); - port_index++; - } - } - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\n"); - - column = tab_depth * TAB_LENGTH + 8; /* Next column I will write to. */ - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\n"); - port_index = 0; - for (i = 0; i < pb_type->num_ports; i++) { - if (pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT) { - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\t", - pb_graph_node->pb_type->ports[i].name); - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - node_index = - pb->pb_graph_node->clock_pins[port_index][j].pin_count_in_cluster; - if (pb_type->parent_mode == NULL) { - print_net_name(rr_node[node_index].net_num, &column, - tab_depth, fpout); - } else { - print_interconnect(node_index, &column, tab_depth + 2, - fpout); - } - } - fprintf(fpout, "\n"); - port_index++; - } - } - print_tabs(fpout, tab_depth); - fprintf(fpout, "\t\n"); - - if (pb_type->num_modes > 0) { - for (i = 0; i < mode->num_pb_type_children; i++) { - for (j = 0; j < mode->pb_type_children[i].num_pb; j++) { - /* If child pb is not used but routing is used, I must print things differently */ - if ((pb->child_pbs[i] != NULL) - && (pb->child_pbs[i][j].name != NULL)) { - print_pb(fpout, &pb->child_pbs[i][j], j, tab_depth + 1); - } else { - is_used = FALSE; - child_pb_type = &mode->pb_type_children[i]; - port_index = 0; - - for (k = 0; k < child_pb_type->num_ports && !is_used; k++) { - if (child_pb_type->ports[k].type == OUT_PORT) { - for (m = 0; m < child_pb_type->ports[k].num_pins; - m++) { - node_index = - pb_graph_node->child_pb_graph_nodes[pb->mode][i][j].output_pins[port_index][m].pin_count_in_cluster; - if (rr_node[node_index].net_num != OPEN) { - is_used = TRUE; - break; - } - } - port_index++; - } - } - print_open_pb_graph_node( - &pb_graph_node->child_pb_graph_nodes[pb->mode][i][j], - j, is_used, tab_depth + 1, fpout); - } - } - } - } - print_tabs(fpout, tab_depth); - fprintf(fpout, "\n"); -} - -static void print_clusters(t_block *clb, int num_clusters, FILE * fpout) { - - /* Prints out one cluster (clb). Both the external pins and the * - * internal connections are printed out. */ - - int icluster; - - for (icluster = 0; icluster < num_clusters; icluster++) { - rr_node = clb[icluster].pb->rr_graph; - - /* TODO: Must do check that total CLB pins match top-level pb pins, perhaps check this earlier? */ - - print_pb(fpout, clb[icluster].pb, icluster, 1); - } -} - -static void print_stats(t_block *clb, int num_clusters) { - - /* Prints out one cluster (clb). Both the external pins and the * - * internal connections are printed out. */ - - int ipin, icluster, itype, inet;/*, iblk;*/ - /*int unabsorbable_ffs;*/ - int total_nets_absorbed; - boolean * nets_absorbed; - - int *num_clb_types, *num_clb_inputs_used, *num_clb_outputs_used; - - nets_absorbed = NULL; - num_clb_types = num_clb_inputs_used = num_clb_outputs_used = NULL; - - num_clb_types = (int*) my_calloc(num_types, sizeof(int)); - num_clb_inputs_used = (int*) my_calloc(num_types, sizeof(int)); - num_clb_outputs_used = (int*) my_calloc(num_types, sizeof(int)); - - - nets_absorbed = (boolean *) my_calloc(num_logical_nets, sizeof(boolean)); - for (inet = 0; inet < num_logical_nets; inet++) { - nets_absorbed[inet] = TRUE; - } - -#if 0 - -/*counting number of flipflops which cannot be absorbed to check the optimality of the packer wrt CLB density*/ - - unabsorbable_ffs = 0; - for (iblk = 0; iblk < num_logical_blocks; iblk++) { - if (strcmp(logical_block[iblk].model->name, "latch") == 0) { - if (vpack_net[logical_block[iblk].input_nets[0][0]].num_sinks > 1 - || strcmp( - logical_block[vpack_net[logical_block[iblk].input_nets[0][0]].node_block[0]].model->name, - "names") != 0) { - unabsorbable_ffs++; - } - } - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "%d FFs in input netlist not absorbable (ie. impossible to form BLE).\n", unabsorbable_ffs); -#endif - - /* Counters used only for statistics purposes. */ - - for (icluster = 0; icluster < num_clusters; icluster++) { - for (ipin = 0; ipin < clb[icluster].type->num_pins; ipin++) { - if (clb[icluster].nets[ipin] != OPEN) { - nets_absorbed[clb[icluster].nets[ipin]] = FALSE; - if (clb[icluster].type->class_inf[clb[icluster].type->pin_class[ipin]].type - == RECEIVER) { - num_clb_inputs_used[clb[icluster].type->index]++; - } else if (clb[icluster].type->class_inf[clb[icluster].type->pin_class[ipin]].type - == DRIVER) { - num_clb_outputs_used[clb[icluster].type->index]++; - } - } - } - num_clb_types[clb[icluster].type->index]++; - } - - for (itype = 0; itype < num_types; itype++) { - if (num_clb_types[itype] == 0) { - vpr_printf(TIO_MESSAGE_INFO, "\t%s: # blocks: %d, average # input + clock pins used: %g, average # output pins used: %g\n", - type_descriptors[itype].name, num_clb_types[itype], 0.0, 0.0); - } else { - vpr_printf(TIO_MESSAGE_INFO, "\t%s: # blocks: %d, average # input + clock pins used: %g, average # output pins used: %g\n", - type_descriptors[itype].name, num_clb_types[itype], - (float) num_clb_inputs_used[itype] / (float) num_clb_types[itype], - (float) num_clb_outputs_used[itype] / (float) num_clb_types[itype]); - } - } - - total_nets_absorbed = 0; - for (inet = 0; inet < num_logical_nets; inet++) { - if (nets_absorbed[inet] == TRUE) { - total_nets_absorbed++; - } - } - vpr_printf(TIO_MESSAGE_INFO, "Absorbed logical nets %d out of %d nets, %d nets not absorbed.\n", - total_nets_absorbed, num_logical_nets, num_logical_nets - total_nets_absorbed); - free(nets_absorbed); - free(num_clb_types); - free(num_clb_inputs_used); - free(num_clb_outputs_used); - /* TODO: print more stats */ -} - -void output_clustering(t_block *clb, int num_clusters, boolean global_clocks, - boolean * is_clock, char *out_fname, boolean skip_clustering) { - - /* - * This routine dumps out the output netlist in a format suitable for * - * input to vpr. This routine also dumps out the internal structure of * - * the cluster, in essentially a graph based format. */ - - FILE *fpout; - int bnum, netnum, column; - - fpout = fopen(out_fname, "w"); - - fprintf(fpout, "\n", - out_fname); - fprintf(fpout, "\t\n\t\t"); - - column = 2 * TAB_LENGTH; /* Organize whitespace to ident data inside block */ - for (bnum = 0; bnum < num_logical_blocks; bnum++) { - if (logical_block[bnum].type == VPACK_INPAD) { - print_string(logical_block[bnum].name, &column, 2, fpout); - } - } - fprintf(fpout, "\n\t\n"); - fprintf(fpout, "\n\t\n\t\t"); - - column = 2 * TAB_LENGTH; - for (bnum = 0; bnum < num_logical_blocks; bnum++) { - if (logical_block[bnum].type == VPACK_OUTPAD) { - print_string(logical_block[bnum].name, &column, 2, fpout); - } - } - fprintf(fpout, "\n\t\n"); - - column = 2 * TAB_LENGTH; - if (global_clocks) { - fprintf(fpout, "\n\t\n\t\t"); - - for (netnum = 0; netnum < num_logical_nets; netnum++) { - if (is_clock[netnum]) { - print_string(vpack_net[netnum].name, &column, 2, fpout); - } - } - fprintf(fpout, "\n\t\n\n"); - } - - /* Print out all input and output pads. */ - - for (bnum = 0; bnum < num_logical_blocks; bnum++) { - switch (logical_block[bnum].type) { - case VPACK_INPAD: - case VPACK_OUTPAD: - case VPACK_COMB: - case VPACK_LATCH: - if (skip_clustering) { - assert(0); - } - break; - - case VPACK_EMPTY: - vpr_printf(TIO_MESSAGE_ERROR, "in output_netlist: logical_block %d is VPACK_EMPTY.\n", - bnum); - exit(1); - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in output_netlist: Unexpected type %d for logical_block %d.\n", - logical_block[bnum].type, bnum); - } - } - - if (skip_clustering == FALSE) - print_clusters(clb, num_clusters, fpout); - - fprintf(fpout, "\n\n"); - - fclose(fpout); - - print_stats(clb, num_clusters); -} diff --git a/vpr7_x2p/vpr/SRC/pack/output_clustering.h b/vpr7_x2p/vpr/SRC/pack/output_clustering.h deleted file mode 100644 index 935c5b06a..000000000 --- a/vpr7_x2p/vpr/SRC/pack/output_clustering.h +++ /dev/null @@ -1,3 +0,0 @@ -void output_clustering(t_block *clb, int num_clusters, boolean global_clocks, - boolean * is_clock, char *out_fname, boolean skip_clustering); - diff --git a/vpr7_x2p/vpr/SRC/pack/pack.c b/vpr7_x2p/vpr/SRC/pack/pack.c deleted file mode 100644 index 3d73aec90..000000000 --- a/vpr7_x2p/vpr/SRC/pack/pack.c +++ /dev/null @@ -1,165 +0,0 @@ -#include -#include -#include -#include "read_xml_arch_file.h" -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "prepack.h" -#include "pack.h" -#include "read_blif.h" -#include "cluster.h" -#include "output_clustering.h" -#include "ReadOptions.h" - -/* #define DUMP_PB_GRAPH 1 */ -/* #define DUMP_BLIF_INPUT 1 */ - -static boolean *alloc_and_load_is_clock(boolean global_clocks); - -void try_pack(INP struct s_packer_opts *packer_opts, INP const t_arch * arch, - INP t_model *user_models, INP t_model *library_models, t_timing_inf timing_inf, float interc_delay) { - boolean *is_clock; - int num_models; - t_model *cur_model; - t_pack_patterns *list_of_packing_patterns; - int num_packing_patterns; - t_pack_molecule *list_of_pack_molecules, * cur_pack_molecule; - int num_pack_molecules; - - vpr_printf(TIO_MESSAGE_INFO, "Begin packing '%s'.\n", packer_opts->blif_file_name); - - /* determine number of models in the architecture */ - num_models = 0; - cur_model = user_models; - while (cur_model) { - num_models++; - cur_model = cur_model->next; - } - cur_model = library_models; - while (cur_model) { - num_models++; - cur_model = cur_model->next; - } - - - is_clock = alloc_and_load_is_clock(packer_opts->global_clocks); - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "After removing unused inputs...\n"); - vpr_printf(TIO_MESSAGE_INFO, "\ttotal blocks: %d, total nets: %d, total inputs: %d, total outputs: %d\n", - num_logical_blocks, num_logical_nets, num_p_inputs, num_p_outputs); - - vpr_printf(TIO_MESSAGE_INFO, "Begin prepacking.\n"); - list_of_packing_patterns = alloc_and_load_pack_patterns( - &num_packing_patterns); - list_of_pack_molecules = alloc_and_load_pack_molecules( - list_of_packing_patterns, num_packing_patterns, - &num_pack_molecules); - vpr_printf(TIO_MESSAGE_INFO, "Finish prepacking.\n"); - - if(packer_opts->auto_compute_inter_cluster_net_delay) { - packer_opts->inter_cluster_net_delay = interc_delay; - vpr_printf(TIO_MESSAGE_INFO, "Using inter-cluster delay: %g\n", packer_opts->inter_cluster_net_delay); - } - - /* Uncomment line below if you want a dump of compressed netlist. */ - /* if (getEchoEnabled()){ - echo_input (packer_opts->blif_file_name, packer_opts->lut_size, "packed.echo"); - }else; */ - - if (packer_opts->skip_clustering == FALSE) { - do_clustering(arch, list_of_pack_molecules, num_models, - packer_opts->global_clocks, is_clock, - packer_opts->hill_climbing_flag, packer_opts->output_file, - packer_opts->timing_driven, packer_opts->cluster_seed_type, - packer_opts->alpha, packer_opts->beta, - packer_opts->recompute_timing_after, packer_opts->block_delay, - packer_opts->intra_cluster_net_delay, - packer_opts->inter_cluster_net_delay, packer_opts->aspect, - packer_opts->allow_unrelated_clustering, - packer_opts->allow_early_exit, packer_opts->connection_driven, - packer_opts->packer_algorithm, timing_inf); - } else { - vpr_printf(TIO_MESSAGE_ERROR, "Skip clustering no longer supported.\n"); - exit(1); - } - - free(is_clock); - - /*free list_of_pack_molecules*/ - free_list_of_pack_patterns(list_of_packing_patterns, num_packing_patterns); - - cur_pack_molecule = list_of_pack_molecules; - while (cur_pack_molecule != NULL){ - if (cur_pack_molecule->logical_block_ptrs != NULL) - free(cur_pack_molecule->logical_block_ptrs); - cur_pack_molecule = list_of_pack_molecules->next; - free(list_of_pack_molecules); - list_of_pack_molecules = cur_pack_molecule; - } - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Netlist conversion complete.\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); -} - -float get_switch_info(short switch_index, float &Tdel_switch, float &R_switch, float &Cout_switch) { - /* Fetches delay, resistance and output capacitance of the switch at switch_index. - Returns the total delay through the switch. Used to calculate inter-cluster net delay. */ - - Tdel_switch = switch_inf[switch_index].Tdel; /* Delay when unloaded */ - R_switch = switch_inf[switch_index].R; - Cout_switch = switch_inf[switch_index].Cout; - - /* The delay through a loaded switch is its intrinsic (unloaded) - delay plus the product of its resistance and output capacitance. */ - return Tdel_switch + R_switch * Cout_switch; -} - -boolean *alloc_and_load_is_clock(boolean global_clocks) { - - /* Looks through all the logical_block to find and mark all the clocks, by setting * - * the corresponding entry in is_clock to true. global_clocks is used * - * only for an error check. */ - - int num_clocks, bnum, clock_net; - boolean * is_clock; - - num_clocks = 0; - - is_clock = (boolean *) my_calloc(num_logical_nets, sizeof(boolean)); - - /* Want to identify all the clock nets. */ - - for (bnum = 0; bnum < num_logical_blocks; bnum++) { - if (logical_block[bnum].type == VPACK_LATCH) { - clock_net = logical_block[bnum].clock_net; - assert(clock_net != OPEN); - if (is_clock[clock_net] == FALSE) { - is_clock[clock_net] = TRUE; - num_clocks++; - } - } else { - if (logical_block[bnum].clock_net != OPEN) { - clock_net = logical_block[bnum].clock_net; - if (is_clock[clock_net] == FALSE) { - is_clock[clock_net] = TRUE; - num_clocks++; - } - } - } - } - - /* If we have multiple clocks and we're supposed to declare them global, * - * print a warning message, since it looks like this circuit may have * - * locally generated clocks. */ - - if (num_clocks > 1 && global_clocks) { - vpr_printf(TIO_MESSAGE_WARNING, "Circuit contains %d clocks. All clocks will be marked global.\n", num_clocks); - } - - return (is_clock); -} - - diff --git a/vpr7_x2p/vpr/SRC/pack/pack.h b/vpr7_x2p/vpr/SRC/pack/pack.h deleted file mode 100644 index 31f0b8364..000000000 --- a/vpr7_x2p/vpr/SRC/pack/pack.h +++ /dev/null @@ -1,2 +0,0 @@ -void try_pack(INP struct s_packer_opts *packer_opts, INP const t_arch * arch, INP t_model *user_models, INP t_model *library_models, t_timing_inf timing_inf, float interc_delay); -float get_switch_info(short switch_index, float &Tdel_switch, float &R_switch, float &Cout_switch); diff --git a/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c b/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c deleted file mode 100755 index 40838f6b8..000000000 --- a/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c +++ /dev/null @@ -1,2155 +0,0 @@ -/** - * Jason Luu - * July 17, 2009 - * pb_graph creates the internal routing edges that join together the different - * pb_types modes within a pb_type - */ - -#include -#include -#include - -#include "util.h" -#include "token.h" -#include "arch_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "vpr_utils.h" -#include "pb_type_graph.h" -#include "pb_type_graph_annotations.h" -#include "cluster_feasibility_filter.h" -#include "power.h" -#include "read_xml_spice_util.h" - -/* variable global to this section that indexes each pb graph pin within a cluster */ -static int pin_count_in_cluster; -static struct s_linked_vptr *edges_head; -static struct s_linked_vptr *num_edges_head; - -/* TODO: Software engineering decision needed: Move this file to libarch? - - */ - -static int check_pb_graph(void); -static void alloc_and_load_pb_graph(INOUTP t_pb_graph_node *pb_graph_node, - INP t_pb_graph_node *parent_pb_graph_node, INP t_pb_type *pb_type, - INP int index, boolean load_power_structures); - -static void alloc_and_load_mode_interconnect( - INOUTP t_pb_graph_node *pb_graph_parent_node, - INOUTP t_pb_graph_node **pb_graph_children_nodes, - INP const t_mode * mode, boolean load_power_structures, - INP int index_mode); - -static boolean realloc_and_load_pb_graph_pin_ptrs_at_var(INP int line_num, - INP const t_pb_graph_node *pb_graph_parent_node, - INP t_pb_graph_node **pb_graph_children_nodes, - INP boolean interconnect_error_check, INP boolean is_input_to_interc, - INP const t_token *tokens, INOUTP int *token_index, - INOUTP int *num_pins, OUTP t_pb_graph_pin ***pb_graph_pins); - -static t_pb_graph_pin * get_pb_graph_pin_from_name(INP const char * port_name, - INP const t_pb_graph_node * pb, INP int pin); - -static void alloc_and_load_complete_interc_edges( - INP t_interconnect * interconnect, - INOUTP t_pb_graph_pin *** input_pb_graph_node_pin_ptrs, - INP int num_input_sets, INP int *num_input_ptrs, - INOUTP t_pb_graph_pin *** output_pb_graph_node_pin_ptrs, - INP int num_output_sets, INP int *num_output_ptrs); - -static void alloc_and_load_direct_interc_edges( - INP t_interconnect * interconnect, - INOUTP t_pb_graph_pin *** input_pb_graph_node_pin_ptrs, - INP int num_input_sets, INP int *num_input_ptrs, - INOUTP t_pb_graph_pin *** output_pb_graph_node_pin_ptrs, - INP int num_output_sets, INP int *num_output_ptrs); - -static void alloc_and_load_mux_interc_edges(INP t_interconnect * interconnect, - INOUTP t_pb_graph_pin *** input_pb_graph_node_pin_ptrs, - INP int num_input_sets, INP int *num_input_ptrs, - INOUTP t_pb_graph_pin *** output_pb_graph_node_pin_ptrs, - INP int num_output_sets, INP int *num_output_ptrs); - -static void alloc_and_load_pin_locations_from_pb_graph(t_type_descriptor *type); - -static void echo_pb_rec(INP const t_pb_graph_node *pb, INP int level, - INP FILE * fp); -static void echo_pb_pins(INP t_pb_graph_pin **pb_graph_pins, INP int num_ports, - INP int level, INP FILE * fp); -static void free_pb_graph(INOUTP t_pb_graph_node *pb_graph_node); - -static void alloc_and_load_interconnect_pins(t_interconnect_pins * interc_pins, - t_interconnect * interconnect, t_pb_graph_pin *** input_pins, - int num_input_sets, int * num_input_pins, - t_pb_graph_pin *** output_pins, int num_output_sets, - int * num_output_pins); - -static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num, - int index_mode, - t_pb_graph_pin*** input_pins, - int num_input_ports, - int* num_input_pins, - t_interconnect* cur_interc); - -/** - * Allocate memory into types and load the pb graph with interconnect edges - */ -void alloc_and_load_all_pb_graphs(boolean load_power_structures) { - int i, errors; - edges_head = NULL; - num_edges_head = NULL; - for (i = 0; i < num_types; i++) { - if (type_descriptors[i].pb_type) { - pin_count_in_cluster = 0; - type_descriptors[i].pb_graph_head = (t_pb_graph_node*) my_calloc(1, - sizeof(t_pb_graph_node)); - alloc_and_load_pb_graph(type_descriptors[i].pb_graph_head, NULL, - type_descriptors[i].pb_type, 0, load_power_structures); - type_descriptors[i].pb_graph_head->total_pb_pins = - pin_count_in_cluster; - alloc_and_load_pin_locations_from_pb_graph(&type_descriptors[i]); - load_pin_classes_in_pb_graph_head( - type_descriptors[i].pb_graph_head); - } else { - type_descriptors[i].pb_graph_head = NULL; - assert(&type_descriptors[i] == EMPTY_TYPE); - } - } - - errors = check_pb_graph(); - if (errors > 0) { - vpr_printf(TIO_MESSAGE_ERROR, "in pb graph"); - exit(1); - } - for (i = 0; i < num_types; i++) { - if (type_descriptors[i].pb_type) { - load_pb_graph_pin_to_pin_annotations( - type_descriptors[i].pb_graph_head); - } - } -} - -/** - * Free pb graph - */ -void free_all_pb_graph_nodes(void) { - int i; - for (i = 0; i < num_types; i++) { - if (type_descriptors[i].pb_type) { - pin_count_in_cluster = 0; - if (type_descriptors[i].pb_graph_head) { - free_pb_graph(type_descriptors[i].pb_graph_head); - free(type_descriptors[i].pb_graph_head); - } - } - } -} - -/** - * Print out the pb_type graph - */ -void echo_pb_graph(char * filename) { - FILE *fp; - int i; - - fp = my_fopen(filename, "w", 0); - - fprintf(fp, "Physical Blocks Graph\n"); - fprintf(fp, "--------------------------------------------\n\n"); - - for (i = 0; i < num_types; i++) { - fprintf(fp, "type %s\n", type_descriptors[i].name); - if (type_descriptors[i].pb_graph_head) - echo_pb_rec(type_descriptors[i].pb_graph_head, 1, fp); - } - - fclose(fp); -} - -/** - * check pb_type graph and return the number of errors - */ -static int check_pb_graph(void) { - int num_errors; - /* TODO: Error checks to do - 1. All pin and edge connections are bidirectional and match each other - 2. All pb_type names are unique in a namespace - 3. All ports are unique in a pb_type - 4. Number of pb of a pb_type in graph is the same as requested number - 5. All pins are connected to edges - */ - num_errors = 0; - - return num_errors; -} - -static void alloc_and_load_pb_graph(INOUTP t_pb_graph_node *pb_graph_node, - INP t_pb_graph_node *parent_pb_graph_node, INP t_pb_type *pb_type, - INP int index, boolean load_power_structures) { - int i, j, k, i_input, i_output, i_clockport; - - pb_graph_node->placement_index = index; - pb_graph_node->pb_type = pb_type; - pb_graph_node->parent_pb_graph_node = parent_pb_graph_node; - - pb_graph_node->num_input_ports = 0; - pb_graph_node->num_output_ports = 0; - pb_graph_node->num_clock_ports = 0; - - /* Generate ports for pb graph node */ - for (i = 0; i < pb_type->num_ports; i++) { - if (pb_type->ports[i].type == IN_PORT && !pb_type->ports[i].is_clock) { - pb_graph_node->num_input_ports++; - } else if (pb_type->ports[i].type == OUT_PORT) { - assert(!pb_type->ports[i].is_clock); - pb_graph_node->num_output_ports++; - } else { - assert( - pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT); - pb_graph_node->num_clock_ports++; - } - } - - pb_graph_node->num_input_pins = (int*) my_calloc( - pb_graph_node->num_input_ports, sizeof(int)); - pb_graph_node->num_output_pins = (int*) my_calloc( - pb_graph_node->num_output_ports, sizeof(int)); - pb_graph_node->num_clock_pins = (int*) my_calloc( - pb_graph_node->num_clock_ports, sizeof(int)); - - pb_graph_node->input_pins = (t_pb_graph_pin**) my_calloc( - pb_graph_node->num_input_ports, sizeof(t_pb_graph_pin*)); - pb_graph_node->output_pins = (t_pb_graph_pin**) my_calloc( - pb_graph_node->num_output_ports, sizeof(t_pb_graph_pin*)); - pb_graph_node->clock_pins = (t_pb_graph_pin**) my_calloc( - pb_graph_node->num_clock_ports, sizeof(t_pb_graph_pin*)); - - i_input = i_output = i_clockport = 0; - for (i = 0; i < pb_type->num_ports; i++) { - if (pb_type->ports[i].model_port) { - assert(pb_type->num_modes == 0); - } else { - assert(pb_type->num_modes != 0 || pb_type->ports[i].is_clock); - } - if (pb_type->ports[i].type == IN_PORT && !pb_type->ports[i].is_clock) { - pb_graph_node->input_pins[i_input] = (t_pb_graph_pin*) my_calloc( - pb_type->ports[i].num_pins, sizeof(t_pb_graph_pin)); - pb_graph_node->num_input_pins[i_input] = pb_type->ports[i].num_pins; - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - pb_graph_node->input_pins[i_input][j].input_edges = NULL; - pb_graph_node->input_pins[i_input][j].num_input_edges = 0; - pb_graph_node->input_pins[i_input][j].output_edges = NULL; - pb_graph_node->input_pins[i_input][j].num_output_edges = 0; - pb_graph_node->input_pins[i_input][j].pin_number = j; - pb_graph_node->input_pins[i_input][j].port = &pb_type->ports[i]; - pb_graph_node->input_pins[i_input][j].parent_node = - pb_graph_node; - pb_graph_node->input_pins[i_input][j].pin_count_in_cluster = - pin_count_in_cluster; - pb_graph_node->input_pins[i_input][j].type = PB_PIN_NORMAL; - if (pb_graph_node->pb_type->blif_model != NULL) { - if (strcmp(pb_graph_node->pb_type->blif_model, ".output") - == 0) { - pb_graph_node->input_pins[i_input][j].type = - PB_PIN_OUTPAD; - } else if (pb_graph_node->num_clock_ports != 0) { - pb_graph_node->input_pins[i_input][j].type = - PB_PIN_SEQUENTIAL; - } else { - pb_graph_node->input_pins[i_input][j].type = - PB_PIN_TERMINAL; - } - } - pin_count_in_cluster++; - } - i_input++; - } else if (pb_type->ports[i].type == OUT_PORT) { - pb_graph_node->output_pins[i_output] = (t_pb_graph_pin*) my_calloc( - pb_type->ports[i].num_pins, sizeof(t_pb_graph_pin)); - pb_graph_node->num_output_pins[i_output] = - pb_type->ports[i].num_pins; - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - pb_graph_node->output_pins[i_output][j].input_edges = NULL; - pb_graph_node->output_pins[i_output][j].num_input_edges = 0; - pb_graph_node->output_pins[i_output][j].output_edges = NULL; - pb_graph_node->output_pins[i_output][j].num_output_edges = 0; - pb_graph_node->output_pins[i_output][j].pin_number = j; - pb_graph_node->output_pins[i_output][j].port = - &pb_type->ports[i]; - pb_graph_node->output_pins[i_output][j].parent_node = - pb_graph_node; - pb_graph_node->output_pins[i_output][j].pin_count_in_cluster = - pin_count_in_cluster; - pb_graph_node->output_pins[i_output][j].type = PB_PIN_NORMAL; - if (pb_graph_node->pb_type->blif_model != NULL) { - if (strcmp(pb_graph_node->pb_type->blif_model, ".input") - == 0) { - pb_graph_node->output_pins[i_output][j].type = - PB_PIN_INPAD; - } else if (pb_graph_node->num_clock_ports != 0) { - pb_graph_node->output_pins[i_output][j].type = - PB_PIN_SEQUENTIAL; - } else { - pb_graph_node->output_pins[i_output][j].type = - PB_PIN_TERMINAL; - } - } - pin_count_in_cluster++; - } - i_output++; - } else { - assert( - pb_type->ports[i].is_clock && pb_type->ports[i].type == IN_PORT); - pb_graph_node->clock_pins[i_clockport] = - (t_pb_graph_pin*) my_calloc(pb_type->ports[i].num_pins, - sizeof(t_pb_graph_pin)); - pb_graph_node->num_clock_pins[i_clockport] = - pb_type->ports[i].num_pins; - for (j = 0; j < pb_type->ports[i].num_pins; j++) { - pb_graph_node->clock_pins[i_clockport][j].input_edges = NULL; - pb_graph_node->clock_pins[i_clockport][j].num_input_edges = 0; - pb_graph_node->clock_pins[i_clockport][j].output_edges = NULL; - pb_graph_node->clock_pins[i_clockport][j].num_output_edges = 0; - pb_graph_node->clock_pins[i_clockport][j].pin_number = j; - pb_graph_node->clock_pins[i_clockport][j].port = - &pb_type->ports[i]; - pb_graph_node->clock_pins[i_clockport][j].parent_node = - pb_graph_node; - pb_graph_node->clock_pins[i_clockport][j].pin_count_in_cluster = - pin_count_in_cluster; - pb_graph_node->clock_pins[i_clockport][j].type = PB_PIN_NORMAL; - if (pb_graph_node->pb_type->blif_model != NULL) { - pb_graph_node->clock_pins[i_clockport][j].type = - PB_PIN_CLOCK; - } - pin_count_in_cluster++; - } - i_clockport++; - } - } - - /* Power */ - if (load_power_structures) { - pb_graph_node->pb_node_power = (t_pb_graph_node_power*) my_calloc(1, - sizeof(t_pb_graph_node_power)); - pb_graph_node->pb_node_power->transistor_cnt_buffers = 0.; - pb_graph_node->pb_node_power->transistor_cnt_interc = 0.; - pb_graph_node->pb_node_power->transistor_cnt_pb_children = 0.; - } - - /* Allocate and load child nodes for each mode and create interconnect in each mode */ - pb_graph_node->child_pb_graph_nodes = (t_pb_graph_node***) my_calloc( - pb_type->num_modes, sizeof(t_pb_graph_node **)); - for (i = 0; i < pb_type->num_modes; i++) { - pb_graph_node->child_pb_graph_nodes[i] = (t_pb_graph_node**) my_calloc( - pb_type->modes[i].num_pb_type_children, - sizeof(t_pb_graph_node *)); - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - pb_graph_node->child_pb_graph_nodes[i][j] = - (t_pb_graph_node*) my_calloc( - pb_type->modes[i].pb_type_children[j].num_pb, - sizeof(t_pb_graph_node)); - for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) { - alloc_and_load_pb_graph( - &pb_graph_node->child_pb_graph_nodes[i][j][k], - pb_graph_node, &pb_type->modes[i].pb_type_children[j], - k, load_power_structures); - } - } - } - - pb_graph_node->interconnect_pins = (t_interconnect_pins**) my_calloc( - pb_type->num_modes, sizeof(t_interconnect_pins *)); - for (i = 0; i < pb_type->num_modes; i++) { - /* Create interconnect for mode */ - alloc_and_load_mode_interconnect(pb_graph_node, - pb_graph_node->child_pb_graph_nodes[i], &pb_type->modes[i], - load_power_structures, i); - } -} - -static void free_pb_graph(INOUTP t_pb_graph_node *pb_graph_node) { - int i, j, k; - const t_pb_type *pb_type; - struct s_linked_vptr *cur, *cur_num; - t_pb_graph_edge *edges; - - pb_type = pb_graph_node->pb_type; - - /*free all lists of connectable input pin pointer of pb_graph_node and it's children*/ - /*free_list_of_connectable_input_pin_ptrs (pb_graph_node);*/ - - /* Free ports for pb graph node */ - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - if (pb_graph_node->input_pins[i][j].pin_timing) - free(pb_graph_node->input_pins[i][j].pin_timing); - if (pb_graph_node->input_pins[i][j].pin_timing_del_max) - free(pb_graph_node->input_pins[i][j].pin_timing_del_max); - if (pb_graph_node->input_pins[i][j].input_edges) - free(pb_graph_node->input_pins[i][j].input_edges); - if (pb_graph_node->input_pins[i][j].output_edges) - free(pb_graph_node->input_pins[i][j].output_edges); - if (pb_graph_node->input_pins[i][j].parent_pin_class) - free(pb_graph_node->input_pins[i][j].parent_pin_class); - } - free(pb_graph_node->input_pins[i]); - } - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - if (pb_graph_node->output_pins[i][j].pin_timing) - free(pb_graph_node->output_pins[i][j].pin_timing); - if (pb_graph_node->output_pins[i][j].pin_timing_del_max) - free(pb_graph_node->output_pins[i][j].pin_timing_del_max); - if (pb_graph_node->output_pins[i][j].input_edges) - free(pb_graph_node->output_pins[i][j].input_edges); - if (pb_graph_node->output_pins[i][j].output_edges) - free(pb_graph_node->output_pins[i][j].output_edges); - if (pb_graph_node->output_pins[i][j].parent_pin_class) - free(pb_graph_node->output_pins[i][j].parent_pin_class); - - if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs) { - for (k = 0; k < pb_graph_node->pb_type->depth; k++) { - if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]) { - free( - pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]); - } - } - free( - pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs); - } - - if (pb_graph_node->output_pins[i][j].num_connectable_primtive_input_pins) - free( - pb_graph_node->output_pins[i][j].num_connectable_primtive_input_pins); - } - free(pb_graph_node->output_pins[i]); - } - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - if (pb_graph_node->clock_pins[i][j].pin_timing) - free(pb_graph_node->clock_pins[i][j].pin_timing); - if (pb_graph_node->clock_pins[i][j].pin_timing_del_max) - free(pb_graph_node->clock_pins[i][j].pin_timing_del_max); - if (pb_graph_node->clock_pins[i][j].input_edges) - free(pb_graph_node->clock_pins[i][j].input_edges); - if (pb_graph_node->clock_pins[i][j].output_edges) - free(pb_graph_node->clock_pins[i][j].output_edges); - if (pb_graph_node->clock_pins[i][j].parent_pin_class) - free(pb_graph_node->clock_pins[i][j].parent_pin_class); - } - free(pb_graph_node->clock_pins[i]); - } - - - for(i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - free(pb_graph_node->interconnect_pins[i]); - } - free(pb_graph_node->interconnect_pins); - - free(pb_graph_node->input_pins); - free(pb_graph_node->output_pins); - free(pb_graph_node->clock_pins); - - free(pb_graph_node->num_input_pins); - free(pb_graph_node->num_output_pins); - free(pb_graph_node->num_clock_pins); - - free(pb_graph_node->input_pin_class_size); - free(pb_graph_node->output_pin_class_size); - - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) { - free_pb_graph(&pb_graph_node->child_pb_graph_nodes[i][j][k]); - } - free(pb_graph_node->child_pb_graph_nodes[i][j]); - } - free(pb_graph_node->child_pb_graph_nodes[i]); - } - free(pb_graph_node->child_pb_graph_nodes); - - while (edges_head != NULL) { - cur = edges_head; - cur_num = num_edges_head; - edges = (t_pb_graph_edge*) cur->data_vptr; - for (i = 0; i < (long) cur_num->data_vptr; i++) { - free(edges[i].input_pins); - free(edges[i].output_pins); - if (edges[i].pack_pattern_indices) { - free(edges[i].pack_pattern_indices); - } - if (edges[i].pack_pattern_names) { - free(edges[i].pack_pattern_names); - } - } - edges_head = edges_head->next; - num_edges_head = num_edges_head->next; - free(edges); - free(cur_num); - free(cur); - } -} - -static void alloc_and_load_interconnect_pins(t_interconnect_pins * interc_pins, - t_interconnect * interconnect, t_pb_graph_pin *** input_pins, - int num_input_sets, int * num_input_pins, - t_pb_graph_pin *** output_pins, int num_output_sets, - int * num_output_pins) { - int set_idx; - int pin_idx; - int port_idx; - int num_ports; - - interc_pins->interconnect = interconnect; - - switch (interconnect->type) { - case DIRECT_INTERC: - assert(num_output_sets == 1); - /* Fall through here */ - - case MUX_INTERC: - if (!interconnect->interconnect_power->port_info_initialized) { - for (set_idx = 0; set_idx < num_input_sets; set_idx++) { - if (num_input_pins[set_idx] != num_output_pins[0]) { - assert(num_input_pins[set_idx] == num_output_pins[0]); - } - } - interconnect->interconnect_power->num_pins_per_port = - num_input_pins[0]; - interconnect->interconnect_power->num_input_ports = num_input_sets; - interconnect->interconnect_power->num_output_ports = 1; - - /* No longer used - mux architectures are not configurable, the - * default is always assumed - if (interconnect->mux_arch) { - interconnect->mux_arch->num_inputs = - interconnect->num_input_ports; - - mux_arch_fix_levels(interconnect->mux_arch); - - interconnect->mux_arch->mux_graph_head = - alloc_and_load_mux_graph(interconnect->num_input_ports, - interconnect->mux_arch->levels); - } - */ - - interconnect->interconnect_power->port_info_initialized = TRUE; - } - - interc_pins->input_pins = (t_pb_graph_pin***) my_calloc(num_input_sets, - sizeof(t_pb_graph_pin**)); - for (set_idx = 0; set_idx < num_input_sets; set_idx++) { - interc_pins->input_pins[set_idx] = (t_pb_graph_pin**) my_calloc( - interconnect->interconnect_power->num_pins_per_port, - sizeof(t_pb_graph_pin*)); - } - - interc_pins->output_pins = (t_pb_graph_pin***) my_calloc(1, - sizeof(t_pb_graph_pin**)); - interc_pins->output_pins[0] = (t_pb_graph_pin**) my_calloc( - interconnect->interconnect_power->num_pins_per_port, - sizeof(t_pb_graph_pin*)); - - for (pin_idx = 0; - pin_idx < interconnect->interconnect_power->num_pins_per_port; - pin_idx++) { - for (set_idx = 0; set_idx < num_input_sets; set_idx++) { - interc_pins->input_pins[set_idx][pin_idx] = - input_pins[set_idx][pin_idx]; - } - interc_pins->output_pins[0][pin_idx] = output_pins[0][pin_idx]; - } - - break; - case COMPLETE_INTERC: - - if (!interconnect->interconnect_power->port_info_initialized) { - /* The code does not support bus-based crossbars, so all pins from all input sets - * connect to all pins from all output sets */ - interconnect->interconnect_power->num_pins_per_port = 1; - - num_ports = 0; - for (set_idx = 0; set_idx < num_input_sets; set_idx++) { - num_ports += num_input_pins[set_idx]; - } - interconnect->interconnect_power->num_input_ports = num_ports; - - num_ports = 0; - for (set_idx = 0; set_idx < num_output_sets; set_idx++) { - num_ports += num_output_pins[set_idx]; - } - interconnect->interconnect_power->num_output_ports = num_ports; - - /* - if (interconnect->mux_arch) { - interconnect->mux_arch->num_inputs = - interconnect->num_input_ports; - - mux_arch_fix_levels(interconnect->mux_arch); - - interconnect->mux_arch->mux_graph_head = - alloc_and_load_mux_graph(interconnect->num_input_ports, - interconnect->mux_arch->levels); - }*/ - - interconnect->interconnect_power->port_info_initialized = TRUE; - } - - /* Input Pins */ - interc_pins->input_pins = (t_pb_graph_pin ***) my_calloc( - interconnect->interconnect_power->num_input_ports, - sizeof(t_pb_graph_pin**)); - for (port_idx = 0; - port_idx < interconnect->interconnect_power->num_input_ports; - port_idx++) { - interc_pins->input_pins[port_idx] = (t_pb_graph_pin**) my_calloc( - interconnect->interconnect_power->num_pins_per_port, - sizeof(t_pb_graph_pin*)); - } - num_ports = 0; - for (set_idx = 0; set_idx < num_input_sets; set_idx++) { - for (pin_idx = 0; pin_idx < num_input_pins[set_idx]; pin_idx++) { - interc_pins->input_pins[num_ports++][0] = - input_pins[set_idx][pin_idx]; - } - } - - /* Output Pins */ - interc_pins->output_pins = (t_pb_graph_pin ***) my_calloc( - interconnect->interconnect_power->num_output_ports, - sizeof(t_pb_graph_pin**)); - for (port_idx = 0; - port_idx < interconnect->interconnect_power->num_output_ports; - port_idx++) { - interc_pins->output_pins[port_idx] = (t_pb_graph_pin **) my_calloc( - interconnect->interconnect_power->num_pins_per_port, - sizeof(t_pb_graph_pin*)); - } - num_ports = 0; - for (set_idx = 0; set_idx < num_output_sets; set_idx++) { - for (pin_idx = 0; pin_idx < num_output_pins[set_idx]; pin_idx++) { - interc_pins->output_pins[num_ports++][0]= - output_pins[set_idx][pin_idx]; - } - } - - break; - } - -} - -/** - * Generate interconnect associated with a mode of operation - * pb_graph_parent_node: parent node of pb in mode - * pb_graph_children_nodes: [0..num_pb_type_in_mode-1][0..num_pb] - * mode: mode of operation - */ -static void alloc_and_load_mode_interconnect( - INOUTP t_pb_graph_node *pb_graph_parent_node, - INOUTP t_pb_graph_node **pb_graph_children_nodes, - INP const t_mode * mode, boolean load_power_structures, - INP int index_mode) { - int i, j; - int *num_input_pb_graph_node_pins, *num_output_pb_graph_node_pins; /* number of pins in a set [0..num_sets-1] */ - int num_input_pb_graph_node_sets, num_output_pb_graph_node_sets; - t_pb_graph_pin *** input_pb_graph_node_pins, ***output_pb_graph_node_pins; - - /* Xifan TANG: Spice Model Support, count the fan-in and fan-out, num_mux in the interconnection*/ - int fan_in, fan_out, num_mux; - /* END */ - - if (load_power_structures) { - assert(pb_graph_parent_node->interconnect_pins[mode->index] == NULL); - pb_graph_parent_node->interconnect_pins[mode->index] = - (t_interconnect_pins*) my_calloc(mode->num_interconnect, - sizeof(t_interconnect_pins)); - } - - for (i = 0; i < mode->num_interconnect; i++) { - /* determine the interconnect input and output pins */ - input_pb_graph_node_pins = alloc_and_load_port_pin_ptrs_from_string( - mode->interconnect[i].line_num, pb_graph_parent_node, - pb_graph_children_nodes, mode->interconnect[i].input_string, - &num_input_pb_graph_node_pins, &num_input_pb_graph_node_sets, - TRUE, TRUE); - - output_pb_graph_node_pins = alloc_and_load_port_pin_ptrs_from_string( - mode->interconnect[i].line_num, pb_graph_parent_node, - pb_graph_children_nodes, mode->interconnect[i].output_string, - &num_output_pb_graph_node_pins, &num_output_pb_graph_node_sets, - FALSE, TRUE); - - if (load_power_structures) { - alloc_and_load_interconnect_pins( - &pb_graph_parent_node->interconnect_pins[mode->index][i], - &mode->interconnect[i], input_pb_graph_node_pins, - num_input_pb_graph_node_sets, num_input_pb_graph_node_pins, - output_pb_graph_node_pins, num_output_pb_graph_node_sets, - num_output_pb_graph_node_pins); - } - - /* process the interconnect based on its type */ - switch (mode->interconnect[i].type) { - - case COMPLETE_INTERC: - alloc_and_load_complete_interc_edges(&mode->interconnect[i], - input_pb_graph_node_pins, num_input_pb_graph_node_sets, - num_input_pb_graph_node_pins, output_pb_graph_node_pins, - num_output_pb_graph_node_sets, - num_output_pb_graph_node_pins); - - break; - - case DIRECT_INTERC: - alloc_and_load_direct_interc_edges(&mode->interconnect[i], - input_pb_graph_node_pins, num_input_pb_graph_node_sets, - num_input_pb_graph_node_pins, output_pb_graph_node_pins, - num_output_pb_graph_node_sets, - num_output_pb_graph_node_pins); - break; - - case MUX_INTERC: - alloc_and_load_mux_interc_edges(&mode->interconnect[i], - input_pb_graph_node_pins, num_input_pb_graph_node_sets, - num_input_pb_graph_node_pins, output_pb_graph_node_pins, - num_output_pb_graph_node_sets, - num_output_pb_graph_node_pins); - - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] Unknown interconnect %d for mode %s in pb_type %s, input %s, output %s\n", - mode->interconnect[i].line_num, mode->interconnect[i].type, - mode->name, pb_graph_parent_node->pb_type->name, - mode->interconnect[i].input_string, - mode->interconnect[i].output_string); - exit(1); - } - /* Xifan TANG: count the fan-in and fan-out of this interconnect, - * And infer the number of multiplexer - */ - fan_in = 0; - /* Count fan-in */ - for (j = 0; j < num_input_pb_graph_node_sets; j++) { - fan_in += num_input_pb_graph_node_pins[j]; - } - mode->interconnect[i].fan_in = fan_in; - /* Count fan-out */ - fan_out = 0; - for (j = 0; j < num_output_pb_graph_node_sets; j++) { - fan_out += num_output_pb_graph_node_pins[j]; - } - mode->interconnect[i].fan_out = fan_out; - /* Check if this is a legal interconnect*/ - if (1 > mode->interconnect[i].fan_in) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] fan_in is 0!(Interconnect %d for mode %s in pb_type %s, input %s, output %s)\n", - mode->interconnect[i].line_num, mode->interconnect[i].type, - mode->name, pb_graph_parent_node->pb_type->name, - mode->interconnect[i].input_string, - mode->interconnect[i].output_string); - exit(1); - } - /* infer the number of mux*/ - num_mux = 0; - switch (mode->interconnect[i].type) { - case COMPLETE_INTERC: - if (1 == mode->interconnect[i].fan_in) { - num_mux = 0; - } else { - num_mux = mode->interconnect[i].fan_out; - } - break; - case MUX_INTERC: - num_mux = mode->interconnect[i].fan_out; - break; - case DIRECT_INTERC: - num_mux = 0; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] Unknown interconnect %d for mode %s in pb_type %s, input %s, output %s\n", - mode->interconnect[i].line_num, mode->interconnect[i].type, - mode->name, pb_graph_parent_node->pb_type->name, - mode->interconnect[i].input_string, - mode->interconnect[i].output_string); - exit(1); - } - mode->interconnect[i].num_mux = num_mux; - /* END */ - - /* Baudouin Chauviere SDC generation: loop breaker */ - if (mode->interconnect[i].loop_breaker_string) { - map_loop_breaker_onto_edges(mode->interconnect[i].loop_breaker_string, - mode->interconnect[i].line_num, - index_mode, - input_pb_graph_node_pins, - num_input_pb_graph_node_sets, - num_input_pb_graph_node_pins, - &(mode->interconnect[i])); - } - /* END */ - - for (j = 0; j < num_input_pb_graph_node_sets; j++) { - free(input_pb_graph_node_pins[j]); - } - free(input_pb_graph_node_pins); - for (j = 0; j < num_output_pb_graph_node_sets; j++) { - free(output_pb_graph_node_pins[j]); - } - free(output_pb_graph_node_pins); - free(num_input_pb_graph_node_pins); - free(num_output_pb_graph_node_pins); - } -} - -/** - * creates an array of pointers to the pb graph node pins in order from the port string - * returns t_pb_graph_pin ptr indexed by [0..num_sets_in_port - 1][0..num_ptrs - 1] - */ -t_pb_graph_pin *** alloc_and_load_port_pin_ptrs_from_string(INP int line_num, - INP const t_pb_graph_node *pb_graph_parent_node, - INP t_pb_graph_node **pb_graph_children_nodes, - INP const char * port_string, OUTP int ** num_ptrs, OUTP int * num_sets, - INP boolean is_input_to_interc, INP boolean interconnect_error_check) { - t_token * tokens; - int num_tokens, curr_set; - int i; - boolean in_squig_bracket, success; - - t_pb_graph_pin ***pb_graph_pins; - - num_tokens = 0; - tokens = GetTokensFromString(port_string, &num_tokens); - *num_sets = 0; - in_squig_bracket = FALSE; - - /* count the number of sets available */ - for (i = 0; i < num_tokens; i++) { - assert(tokens[i].type != TOKEN_NULL); - if (tokens[i].type == TOKEN_OPEN_SQUIG_BRACKET) { - if (in_squig_bracket) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] { inside { in port %s\n", line_num, - port_string); - exit(1); - } - in_squig_bracket = TRUE; - } else if (tokens[i].type == TOKEN_CLOSE_SQUIG_BRACKET) { - if (!in_squig_bracket) { - (*num_sets)++; - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] No matching '{' for '}' in port %s\n", - line_num, port_string); - exit(1); - } - in_squig_bracket = FALSE; - } else if (tokens[i].type == TOKEN_DOT) { - if (!in_squig_bracket) { - (*num_sets)++; - } - } - } - - if (in_squig_bracket) { - (*num_sets)++; - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] No matching '{' for '}' in port %s\n", line_num, - port_string); - exit(1); - } - - pb_graph_pins = (t_pb_graph_pin***) my_calloc(*num_sets, - sizeof(t_pb_graph_pin**)); - *num_ptrs = (int*) my_calloc(*num_sets, sizeof(int)); - - curr_set = 0; - for (i = 0; i < num_tokens; i++) { - assert(tokens[i].type != TOKEN_NULL); - if (tokens[i].type == TOKEN_OPEN_SQUIG_BRACKET) { - if (in_squig_bracket) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] { inside { in port %s\n", line_num, - port_string); - exit(1); - } - in_squig_bracket = TRUE; - } else if (tokens[i].type == TOKEN_CLOSE_SQUIG_BRACKET) { - if ((*num_ptrs)[curr_set] == 0) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] No data contained in {} in port %s\n", - line_num, port_string); - exit(1); - } - if (!in_squig_bracket) { - curr_set++; - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] No matching '{' for '}' in port %s\n", - line_num, port_string); - exit(1); - } - in_squig_bracket = FALSE; - } else if (tokens[i].type == TOKEN_STRING) { - - success = realloc_and_load_pb_graph_pin_ptrs_at_var(line_num, - pb_graph_parent_node, pb_graph_children_nodes, - interconnect_error_check, is_input_to_interc, tokens, &i, - &((*num_ptrs)[curr_set]), &pb_graph_pins[curr_set]); - - if (!success) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] syntax error processing port string %s\n", - line_num, port_string); - exit(1); - } - - if (!in_squig_bracket) { - curr_set++; - } - } - } - assert(curr_set == *num_sets); - freeTokens(tokens, num_tokens); - return pb_graph_pins; -} - -/** - * Creates edges to connect all input pins to output pins - */ -static void alloc_and_load_complete_interc_edges( - INP t_interconnect *interconnect, - INOUTP t_pb_graph_pin *** input_pb_graph_node_pin_ptrs, - INP int num_input_sets, INP int *num_input_ptrs, - INOUTP t_pb_graph_pin *** output_pb_graph_node_pin_ptrs, - INP int num_output_sets, INP int *num_output_ptrs) { - int i_inset, i_outset, i_inpin, i_outpin; - int in_count, out_count; - t_pb_graph_edge *edges; - int i_edge; - struct s_linked_vptr *cur; - - assert(interconnect->infer_annotations == FALSE); - - /* Allocate memory for edges, and reallocate more memory for pins connecting to those edges */ - in_count = out_count = 0; - - for (i_inset = 0; i_inset < num_input_sets; i_inset++) { - in_count += num_input_ptrs[i_inset]; - } - for (i_outset = 0; i_outset < num_output_sets; i_outset++) { - out_count += num_output_ptrs[i_outset]; - } - - edges = (t_pb_graph_edge*) my_calloc(in_count * out_count, - sizeof(t_pb_graph_edge)); - cur = (struct s_linked_vptr*) my_malloc(sizeof(struct s_linked_vptr)); - cur->next = edges_head; - edges_head = cur; - cur->data_vptr = (void *) edges; - cur = (struct s_linked_vptr*) my_malloc(sizeof(struct s_linked_vptr)); - cur->next = num_edges_head; - num_edges_head = cur; - cur->data_vptr = (void *) ((long) in_count * out_count); - - for (i_inset = 0; i_inset < num_input_sets; i_inset++) { - for (i_inpin = 0; i_inpin < num_input_ptrs[i_inset]; i_inpin++) { - input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->output_edges = - (t_pb_graph_edge **) my_realloc( - input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->output_edges, - (input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->num_output_edges - + out_count) * sizeof(t_pb_graph_edge *)); - } - } - - for (i_outset = 0; i_outset < num_output_sets; i_outset++) { - for (i_outpin = 0; i_outpin < num_output_ptrs[i_outset]; i_outpin++) { - output_pb_graph_node_pin_ptrs[i_outset][i_outpin]->input_edges = - (t_pb_graph_edge **) my_realloc( - output_pb_graph_node_pin_ptrs[i_outset][i_outpin]->input_edges, - (output_pb_graph_node_pin_ptrs[i_outset][i_outpin]->num_input_edges - + in_count) * sizeof(t_pb_graph_edge *)); - } - } - - i_edge = 0; - - /* Load connections between pins and record these updates in the edges */ - for (i_inset = 0; i_inset < num_input_sets; i_inset++) { - for (i_inpin = 0; i_inpin < num_input_ptrs[i_inset]; i_inpin++) { - for (i_outset = 0; i_outset < num_output_sets; i_outset++) { - for (i_outpin = 0; i_outpin < num_output_ptrs[i_outset]; - i_outpin++) { - - input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->output_edges[input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->num_output_edges] = - &edges[i_edge]; - input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->num_output_edges++; - output_pb_graph_node_pin_ptrs[i_outset][i_outpin]->input_edges[output_pb_graph_node_pin_ptrs[i_outset][i_outpin]->num_input_edges] = - &edges[i_edge]; - output_pb_graph_node_pin_ptrs[i_outset][i_outpin]->num_input_edges++; - - edges[i_edge].num_input_pins = 1; - edges[i_edge].input_pins = (t_pb_graph_pin **) my_malloc( - sizeof(t_pb_graph_pin *)); - edges[i_edge].input_pins[0] = - input_pb_graph_node_pin_ptrs[i_inset][i_inpin]; - edges[i_edge].num_output_pins = 1; - edges[i_edge].output_pins = (t_pb_graph_pin **) my_malloc( - sizeof(t_pb_graph_pin *)); - edges[i_edge].output_pins[0] = - output_pb_graph_node_pin_ptrs[i_outset][i_outpin]; - - edges[i_edge].interconnect = interconnect; - edges[i_edge].driver_set = i_inset; - edges[i_edge].driver_pin = i_inpin; - - i_edge++; - } - } - } - } - assert(i_edge == in_count * out_count); -} - -static void alloc_and_load_direct_interc_edges( - INP t_interconnect *interconnect, - INOUTP t_pb_graph_pin *** input_pb_graph_node_pin_ptrs, - INP int num_input_sets, INP int *num_input_ptrs, - INOUTP t_pb_graph_pin *** output_pb_graph_node_pin_ptrs, - INP int num_output_sets, INP int *num_output_ptrs) { - - int i; - t_pb_graph_edge *edges; - struct s_linked_vptr *cur; - - /* Allocate memory for edges */ - if (!(num_input_sets == 1 && num_output_sets == 1)) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] Direct interconnect allows connections from one set of pins to one other set\n", - interconnect->line_num); - exit(1); - } - if (!(num_input_ptrs[0] == num_output_ptrs[0])) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] Direct interconnect must use an equal number of pins\n", - interconnect->line_num); - exit(1); - } - - edges = (t_pb_graph_edge*) my_calloc(num_input_ptrs[0], - sizeof(t_pb_graph_edge)); - cur = (struct s_linked_vptr*) my_malloc(sizeof(struct s_linked_vptr)); - cur->next = edges_head; - edges_head = cur; - cur->data_vptr = (void *) edges; - cur = (struct s_linked_vptr*) my_malloc(sizeof(struct s_linked_vptr)); - cur->next = num_edges_head; - num_edges_head = cur; - cur->data_vptr = (void *) ((long) num_input_ptrs[0]); - - /* Reallocate memory for pins and load connections between pins and record these updates in the edges */ - for (i = 0; i < num_input_ptrs[0]; i++) { - input_pb_graph_node_pin_ptrs[0][i]->output_edges = - (t_pb_graph_edge **) my_realloc( - input_pb_graph_node_pin_ptrs[0][i]->output_edges, - (input_pb_graph_node_pin_ptrs[0][i]->num_output_edges - + 1) * sizeof(t_pb_graph_edge *)); - input_pb_graph_node_pin_ptrs[0][i]->output_edges[input_pb_graph_node_pin_ptrs[0][i]->num_output_edges] = - &edges[i]; - input_pb_graph_node_pin_ptrs[0][i]->num_output_edges++; - - output_pb_graph_node_pin_ptrs[0][i]->input_edges = - (t_pb_graph_edge **) my_realloc( - output_pb_graph_node_pin_ptrs[0][i]->input_edges, - (output_pb_graph_node_pin_ptrs[0][i]->num_input_edges - + 1) * sizeof(t_pb_graph_edge *)); - output_pb_graph_node_pin_ptrs[0][i]->input_edges[output_pb_graph_node_pin_ptrs[0][i]->num_input_edges] = - &edges[i]; - output_pb_graph_node_pin_ptrs[0][i]->num_input_edges++; - - edges[i].num_input_pins = 1; - edges[i].input_pins = (t_pb_graph_pin **) my_malloc( - sizeof(t_pb_graph_pin *)); - edges[i].input_pins[0] = input_pb_graph_node_pin_ptrs[0][i]; - edges[i].num_output_pins = 1; - edges[i].output_pins = (t_pb_graph_pin **) my_malloc( - sizeof(t_pb_graph_pin *)); - edges[i].output_pins[0] = output_pb_graph_node_pin_ptrs[0][i]; - - edges[i].interconnect = interconnect; - edges[i].driver_set = 0; - edges[i].driver_pin = i; - edges[i].infer_pattern = interconnect->infer_annotations; - } -} - -static void alloc_and_load_mux_interc_edges( INP t_interconnect * interconnect, - INOUTP t_pb_graph_pin *** input_pb_graph_node_pin_ptrs, - INP int num_input_sets, INP int *num_input_ptrs, - INOUTP t_pb_graph_pin *** output_pb_graph_node_pin_ptrs, - INP int num_output_sets, INP int *num_output_ptrs) { - int i_inset, i_inpin, i_outpin; - t_pb_graph_edge *edges; - struct s_linked_vptr *cur; - - assert(interconnect->infer_annotations == FALSE); - - /* Allocate memory for edges, and reallocate more memory for pins connecting to those edges */ - if (num_output_sets != 1) { - vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Mux must have one output\n", - interconnect->line_num); - exit(1); - } - - edges = (t_pb_graph_edge*) my_calloc(num_input_sets, - sizeof(t_pb_graph_edge)); - cur = (struct s_linked_vptr*) my_malloc(sizeof(struct s_linked_vptr)); - cur->next = edges_head; - edges_head = cur; - cur->data_vptr = (void *) edges; - cur = (struct s_linked_vptr*) my_malloc(sizeof(struct s_linked_vptr)); - cur->next = num_edges_head; - num_edges_head = cur; - cur->data_vptr = (void *) ((long) num_input_sets); - - for (i_inset = 0; i_inset < num_input_sets; i_inset++) { - for (i_inpin = 0; i_inpin < num_input_ptrs[i_inset]; i_inpin++) { - input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->output_edges = - (t_pb_graph_edge**) my_realloc( - input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->output_edges, - (input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->num_output_edges - + 1) * sizeof(t_pb_graph_edge *)); - } - } - - for (i_outpin = 0; i_outpin < num_output_ptrs[0]; i_outpin++) { - output_pb_graph_node_pin_ptrs[0][i_outpin]->input_edges = - (t_pb_graph_edge**) my_realloc( - output_pb_graph_node_pin_ptrs[0][i_outpin]->input_edges, - (output_pb_graph_node_pin_ptrs[0][i_outpin]->num_input_edges - + num_input_sets) * sizeof(t_pb_graph_edge *)); - } - - /* Load connections between pins and record these updates in the edges */ - for (i_inset = 0; i_inset < num_input_sets; i_inset++) { - if (num_output_ptrs[0] != num_input_ptrs[i_inset]) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] # of pins for a particular data line of a mux must equal number of pins at output of mux\n", - interconnect->line_num); - exit(1); - } - edges[i_inset].input_pins = (t_pb_graph_pin**) my_calloc( - num_output_ptrs[0], sizeof(t_pb_graph_pin *)); - edges[i_inset].output_pins = (t_pb_graph_pin**) my_calloc( - num_output_ptrs[0], sizeof(t_pb_graph_pin *)); - edges[i_inset].num_input_pins = num_output_ptrs[0]; - edges[i_inset].num_output_pins = num_output_ptrs[0]; - for (i_inpin = 0; i_inpin < num_input_ptrs[i_inset]; i_inpin++) { - input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->output_edges[input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->num_output_edges] = - &edges[i_inset]; - input_pb_graph_node_pin_ptrs[i_inset][i_inpin]->num_output_edges++; - output_pb_graph_node_pin_ptrs[0][i_inpin]->input_edges[output_pb_graph_node_pin_ptrs[0][i_inpin]->num_input_edges] = - &edges[i_inset]; - output_pb_graph_node_pin_ptrs[0][i_inpin]->num_input_edges++; - - edges[i_inset].input_pins[i_inpin] = - input_pb_graph_node_pin_ptrs[i_inset][i_inpin]; - edges[i_inset].output_pins[i_inpin] = - output_pb_graph_node_pin_ptrs[0][i_inpin]; - - if (i_inpin != 0) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] Bus-based mux not yet supported, will consider for future work\n", - interconnect->line_num); - exit(1); - } - edges[i_inset].interconnect = interconnect; - edges[i_inset].driver_set = i_inset; - edges[i_inset].driver_pin = i_inpin; - } - } -} - -/** - * populate array of pb graph pins for a single variable of type pb_type[int:int].port[int:int] - * pb_graph_pins: pointer to array from [0..num_port_pins] of pb_graph_pin pointers - * tokens: array of tokens to scan - * num_pins: current number of pins in pb_graph_pin array - */ -static boolean realloc_and_load_pb_graph_pin_ptrs_at_var(INP int line_num, - INP const t_pb_graph_node *pb_graph_parent_node, - INP t_pb_graph_node **pb_graph_children_nodes, - INP boolean interconnect_error_check, INP boolean is_input_to_interc, - INP const t_token *tokens, INOUTP int *token_index, - INOUTP int *num_pins, OUTP t_pb_graph_pin ***pb_graph_pins) { - - int i, j, ipin, ipb; - int pb_msb, pb_lsb; - int pin_msb, pin_lsb; - int max_pb_node_array; - const t_pb_graph_node *pb_node_array; - char *port_name; - t_port *iport; - int add_or_subtract_pb, add_or_subtract_pin; - boolean found; - t_mode *mode = NULL; - - assert(tokens[*token_index].type == TOKEN_STRING); - pb_node_array = NULL; - max_pb_node_array = 0; - - if (pb_graph_children_nodes) - mode = pb_graph_children_nodes[0][0].pb_type->parent_mode; - - pb_msb = pb_lsb = OPEN; - pin_msb = pin_lsb = OPEN; - - /* parse pb */ - found = FALSE; - if (0 - == strcmp(pb_graph_parent_node->pb_type->name, - tokens[*token_index].data)) { - pb_node_array = pb_graph_parent_node; - max_pb_node_array = 1; - pb_msb = pb_lsb = 0; - found = TRUE; - (*token_index)++; - if (tokens[*token_index].type == TOKEN_OPEN_SQUARE_BRACKET) { - (*token_index)++; - if (!checkTokenType(tokens[*token_index], TOKEN_INT)) { - return FALSE; - } - pb_msb = my_atoi(tokens[*token_index].data); - (*token_index)++; - if (!checkTokenType(tokens[*token_index], TOKEN_COLON)) { - if (!checkTokenType(tokens[*token_index], - TOKEN_CLOSE_SQUARE_BRACKET)) { - return FALSE; - } - pb_lsb = pb_msb; - (*token_index)++; - } else { - (*token_index)++; - if (!checkTokenType(tokens[*token_index], TOKEN_INT)) { - return FALSE; - } - pb_lsb = my_atoi(tokens[*token_index].data); - (*token_index)++; - if (!checkTokenType(tokens[*token_index], - TOKEN_CLOSE_SQUARE_BRACKET)) { - return FALSE; - } - (*token_index)++; - } - /* Check to make sure indices from user match internal data structures for the indices of the parent */ - if ((pb_lsb != pb_msb) - && (pb_lsb != pb_graph_parent_node->placement_index)) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] Incorrect placement index for %s, expected index %d\n", - line_num, tokens[0].data, - pb_graph_parent_node->placement_index); - return FALSE; - } - pb_lsb = pb_msb = 0; /* Internal representation of parent is always 0 */ - } - } else { - if (mode == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] pb_graph_parent_node %s failed\n", line_num, - pb_graph_parent_node->pb_type->name); - exit(1); - } - for (i = 0; i < mode->num_pb_type_children; i++) { - assert( - &mode->pb_type_children[i] == pb_graph_children_nodes[i][0].pb_type); - if (0 - == strcmp(mode->pb_type_children[i].name, - tokens[*token_index].data)) { - pb_node_array = pb_graph_children_nodes[i]; - max_pb_node_array = mode->pb_type_children[i].num_pb; - found = TRUE; - (*token_index)++; - - if (tokens[*token_index].type == TOKEN_OPEN_SQUARE_BRACKET) { - (*token_index)++; - if (!checkTokenType(tokens[*token_index], TOKEN_INT)) { - return FALSE; - } - pb_msb = my_atoi(tokens[*token_index].data); - (*token_index)++; - if (!checkTokenType(tokens[*token_index], TOKEN_COLON)) { - if (!checkTokenType(tokens[*token_index], - TOKEN_CLOSE_SQUARE_BRACKET)) { - return FALSE; - } - pb_lsb = pb_msb; - (*token_index)++; - } else { - (*token_index)++; - if (!checkTokenType(tokens[*token_index], TOKEN_INT)) { - return FALSE; - } - pb_lsb = my_atoi(tokens[*token_index].data); - (*token_index)++; - if (!checkTokenType(tokens[*token_index], - TOKEN_CLOSE_SQUARE_BRACKET)) { - return FALSE; - } - (*token_index)++; - } - } else { - pb_msb = pb_node_array[0].pb_type->num_pb - 1; - pb_lsb = 0; - } - break; - } - } - } - - if (!found) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] Unknown pb_type name %s, not defined in namespace of mode %s\n", - line_num, tokens[*token_index].data, mode->name); - return FALSE; - } - - found = FALSE; - - if (!checkTokenType(tokens[*token_index], TOKEN_DOT)) { - return FALSE; - } - (*token_index)++; - if (!checkTokenType(tokens[*token_index], TOKEN_STRING)) { - return FALSE; - } - - /* parse ports and port pins of pb */ - port_name = tokens[*token_index].data; - - (*token_index)++; - if (tokens[*token_index].type == TOKEN_OPEN_SQUARE_BRACKET) { - (*token_index)++; - if (!checkTokenType(tokens[*token_index], TOKEN_INT)) { - return FALSE; - } - pin_msb = my_atoi(tokens[*token_index].data); - (*token_index)++; - if (!checkTokenType(tokens[*token_index], TOKEN_COLON)) { - if (!checkTokenType(tokens[*token_index], - TOKEN_CLOSE_SQUARE_BRACKET)) { - return FALSE; - } - pin_lsb = pin_msb; - (*token_index)++; - } else { - (*token_index)++; - if (!checkTokenType(tokens[*token_index], TOKEN_INT)) { - return FALSE; - } - pin_lsb = my_atoi(tokens[*token_index].data); - (*token_index)++; - if (!checkTokenType(tokens[*token_index], - TOKEN_CLOSE_SQUARE_BRACKET)) { - return FALSE; - } - (*token_index)++; - } - } else { - if (pb_lsb < 0 || pb_lsb >= max_pb_node_array) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] pb %d out of range [%d,%d]\n", line_num, pb_lsb, - max_pb_node_array - 1, 0); - exit(1); - } - if (get_pb_graph_pin_from_name(port_name, &pb_node_array[pb_lsb], - 0) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] failed to find port name %s\n", line_num, - port_name); - exit(1); - } - iport = - get_pb_graph_pin_from_name(port_name, &pb_node_array[pb_lsb], 0)->port; - pin_msb = iport->num_pins - 1; - pin_lsb = 0; - } - (*token_index)--; - - if (pb_msb < pb_lsb) { - add_or_subtract_pb = -1; - } else { - add_or_subtract_pb = 1; - } - - if (pin_msb < pin_lsb) { - add_or_subtract_pin = -1; - } else { - add_or_subtract_pin = 1; - } - *num_pins += (abs(pb_msb - pb_lsb) + 1) * (abs(pin_msb - pin_lsb) + 1); - *pb_graph_pins = (t_pb_graph_pin**) my_calloc(*num_pins, - sizeof(t_pb_graph_pin *)); - i = j = 0; - - ipb = pb_lsb; - - while (ipb != pb_msb + add_or_subtract_pin) { - ipin = pin_lsb; - j = 0; - while (ipin != pin_msb + add_or_subtract_pin) { - if (ipb < 0 || ipb >= max_pb_node_array) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] pb %d out of range [%d,%d]\n", line_num, ipb, - max_pb_node_array - 1, 0); - exit(1); - } - (*pb_graph_pins)[i * (abs(pin_msb - pin_lsb) + 1) + j] = - get_pb_graph_pin_from_name(port_name, &pb_node_array[ipb], - ipin); - if ((*pb_graph_pins)[i * (abs(pin_msb - pin_lsb) + 1) + j] == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] Pin %s.%s[%d] cannot be found\n", line_num, - pb_node_array[ipb].pb_type->name, port_name, ipin); - exit(1); - } - iport = - (*pb_graph_pins)[i * (abs(pin_msb - pin_lsb) + 1) + j]->port; - if (!iport) { - return FALSE; - } - - /* Error checking before assignment */ - if (interconnect_error_check) { - if (pb_node_array == pb_graph_parent_node) { - if (is_input_to_interc) { - if (iport->type != IN_PORT) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] input to interconnect from parent is not an input or clock pin\n", - line_num); - return FALSE; - } - } else { - if (iport->type != OUT_PORT) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] output from interconnect from parent is not an input or clock pin\n", - line_num); - return FALSE; - } - } - } else { - if (is_input_to_interc) { - if (iport->type != OUT_PORT) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] output from interconnect from parent is not an input or clock pin\n", - line_num); - return FALSE; - } - } else { - if (iport->type != IN_PORT) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] input to interconnect from parent is not an input or clock pin\n", - line_num); - return FALSE; - } - } - } - } - - /* load pb_graph_pin for pin */ - - ipin += add_or_subtract_pin; - j++; - } - i++; - ipb += add_or_subtract_pb; - } - - assert((abs(pb_msb - pb_lsb) + 1) * (abs(pin_msb - pin_lsb) + 1) == i * j); - - return TRUE; -} - -static t_pb_graph_pin * get_pb_graph_pin_from_name(INP const char * port_name, - INP const t_pb_graph_node * pb, INP int pin) { - int i; - - for (i = 0; i < pb->num_input_ports; i++) { - if (0 == strcmp(port_name, pb->input_pins[i][0].port->name)) { - if (pin < pb->input_pins[i][0].port->num_pins) { - return &pb->input_pins[i][pin]; - } else { - return NULL ; - } - } - } - for (i = 0; i < pb->num_output_ports; i++) { - if (0 == strcmp(port_name, pb->output_pins[i][0].port->name)) { - if (pin < pb->output_pins[i][0].port->num_pins) { - return &pb->output_pins[i][pin]; - } else { - return NULL ; - } - } - } - for (i = 0; i < pb->num_clock_ports; i++) { - if (0 == strcmp(port_name, pb->clock_pins[i][0].port->name)) { - if (pin < pb->clock_pins[i][0].port->num_pins) { - return &pb->clock_pins[i][pin]; - } else { - return NULL ; - } - } - } - return NULL ; -} - -static void alloc_and_load_pin_locations_from_pb_graph(t_type_descriptor *type) { - int i, j, k, m, icapacity; - int num_sides; - int side_index; - int pin_num; - int count; - - int *num_pb_graph_node_pins; /* number of pins in a set [0..num_sets-1] */ - int num_pb_graph_node_sets; - t_pb_graph_pin*** pb_graph_node_pins; - - num_sides = 2 * (type->height + 1); - side_index = 0; - count = 0; - - if (type->pin_location_distribution == E_SPREAD_PIN_DISTR) { - pin_num = 0; - /* evenly distribute pins starting at bottom left corner */ - for (j = 0; j < 4; j++) { - for (i = 0; i < type->height; i++) { - if (j == TOP && i != type->height - 1) { - continue; - } - if (j == BOTTOM && i != 0) { - continue; - } - for (k = 0; k < (type->num_pins / num_sides) + 1; k++) { - pin_num = side_index + k * num_sides; - if (pin_num < type->num_pins) { - type->pinloc[i][j][pin_num] = 1; - type->pin_height[pin_num] = i; - count++; - } - } - side_index++; - } - } - assert(side_index == num_sides); - assert(count == type->num_pins); - } else { - assert(type->pin_location_distribution == E_CUSTOM_PIN_DISTR); - for (i = 0; i < type->height; i++) { - for (j = 0; j < 4; j++) { - if (j == TOP && i != type->height - 1) { - continue; - } - if (j == BOTTOM && i != 0) { - continue; - } - for (k = 0; k < type->num_pin_loc_assignments[i][j]; k++) { - pb_graph_node_pins = - alloc_and_load_port_pin_ptrs_from_string( - type->pb_type->modes[0].interconnect[0].line_num, - type->pb_graph_head, - type->pb_graph_head->child_pb_graph_nodes[0], - type->pin_loc_assignments[i][j][k], - &num_pb_graph_node_pins, - &num_pb_graph_node_sets, FALSE, FALSE); - assert(num_pb_graph_node_sets == 1); - - for (m = 0; m < num_pb_graph_node_pins[0]; m++) { - pin_num = - pb_graph_node_pins[0][m]->pin_count_in_cluster; - assert(pin_num < type->num_pins / type->capacity); - for (icapacity = 0; icapacity < type->capacity; - icapacity++) { - type->pinloc[i][j][pin_num - + icapacity * type->num_pins - / type->capacity] = 1; - type->pin_height[pin_num] = i; - assert(count < type->num_pins); - } - } - free(pb_graph_node_pins[0]); - free(pb_graph_node_pins); - free(num_pb_graph_node_pins); - } - } - } - } -} - -static void echo_pb_rec(const INP t_pb_graph_node *pb_graph_node, INP int level, - INP FILE *fp) { - int i, j, k; - - print_tabs(fp, level); - fprintf(fp, "Physical Block: type \"%s\" index %d num_children %d\n", - pb_graph_node->pb_type->name, pb_graph_node->placement_index, - pb_graph_node->pb_type->num_pb); - - if (pb_graph_node->parent_pb_graph_node) { - print_tabs(fp, level + 1); - fprintf(fp, "Parent Block: type \"%s\" index %d \n", - pb_graph_node->parent_pb_graph_node->pb_type->name, - pb_graph_node->parent_pb_graph_node->placement_index); - } - - print_tabs(fp, level); - fprintf(fp, "Input Ports: total ports %d\n", - pb_graph_node->num_input_ports); - echo_pb_pins(pb_graph_node->input_pins, pb_graph_node->num_input_ports, - level, fp); - print_tabs(fp, level); - fprintf(fp, "Output Ports: total ports %d\n", - pb_graph_node->num_output_ports); - echo_pb_pins(pb_graph_node->output_pins, pb_graph_node->num_output_ports, - level, fp); - print_tabs(fp, level); - fprintf(fp, "Clock Ports: total ports %d\n", - pb_graph_node->num_clock_ports); - echo_pb_pins(pb_graph_node->clock_pins, pb_graph_node->num_clock_ports, - level, fp); - print_tabs(fp, level); - for (i = 0; i < pb_graph_node->num_input_pin_class; i++) { - fprintf(fp, "Input class %d: %d pins, ", i, - pb_graph_node->input_pin_class_size[i]); - } - fprintf(fp, "\n"); - print_tabs(fp, level); - for (i = 0; i < pb_graph_node->num_output_pin_class; i++) { - fprintf(fp, "Output class %d: %d pins, ", i, - pb_graph_node->output_pin_class_size[i]); - } - fprintf(fp, "\n"); - - if (pb_graph_node->pb_type->num_modes > 0) { - print_tabs(fp, level); - fprintf(fp, "Children:\n"); - } - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; - j++) { - for (k = 0; - k - < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; - k++) { - echo_pb_rec(&pb_graph_node->child_pb_graph_nodes[i][j][k], - level + 1, fp); - } - } - } -} - -static void echo_pb_pins(INP t_pb_graph_pin **pb_graph_pins, INP int num_ports, - INP int level, INP FILE * fp) { - int i, j, k, m; - t_port *port; - - print_tabs(fp, level); - - for (i = 0; i < num_ports; i++) { - port = pb_graph_pins[i][0].port; - print_tabs(fp, level); - fprintf(fp, "Port \"%s\": num_pins %d type %d parent name \"%s\"\n", - port->name, port->num_pins, port->type, - port->parent_pb_type->name); - - for (j = 0; j < port->num_pins; j++) { - print_tabs(fp, level + 1); - assert(j == pb_graph_pins[i][j].pin_number); - assert(pb_graph_pins[i][j].port == port); - fprintf(fp, - "Pin %d port name \"%s\" num input edges %d num output edges %d parent type \"%s\" parent index %d\n", - pb_graph_pins[i][j].pin_number, - pb_graph_pins[i][j].port->name, - pb_graph_pins[i][j].num_input_edges, - pb_graph_pins[i][j].num_output_edges, - pb_graph_pins[i][j].parent_node->pb_type->name, - pb_graph_pins[i][j].parent_node->placement_index); - print_tabs(fp, level + 2); - if (pb_graph_pins[i][j].parent_node->pb_type->num_modes == 0) { - fprintf(fp, "pin class (depth, pin class): "); - for (k = 0; k < pb_graph_pins[i][j].parent_node->pb_type->depth; - k++) { - fprintf(fp, "(%d %d), ", k, - pb_graph_pins[i][j].parent_pin_class[k]); - } - fprintf(fp, "\n"); - if (pb_graph_pins[i][j].port->type == OUT_PORT) { - for (k = 0; - k < pb_graph_pins[i][j].parent_node->pb_type->depth; - k++) { - print_tabs(fp, level + 2); - fprintf(fp, - "connectable input pins within depth %d: %d\n", - k, - pb_graph_pins[i][j].num_connectable_primtive_input_pins[k]); - for (m = 0; - m - < pb_graph_pins[i][j].num_connectable_primtive_input_pins[k]; - m++) { - print_tabs(fp, level + 3); - fprintf(fp, "pb_graph_node %s[%d].%s[%d] \n", - pb_graph_pins[i][j].list_of_connectable_input_pin_ptrs[k][m]->parent_node->pb_type->name, - pb_graph_pins[i][j].list_of_connectable_input_pin_ptrs[k][m]->parent_node->placement_index, - pb_graph_pins[i][j].list_of_connectable_input_pin_ptrs[k][m]->port->name, - pb_graph_pins[i][j].list_of_connectable_input_pin_ptrs[k][m]->pin_number); - } - } - } - } else { - fprintf(fp, "pin class %d \n", pb_graph_pins[i][j].pin_class); - } - for (k = 0; k < pb_graph_pins[i][j].num_input_edges; k++) { - print_tabs(fp, level + 2); - fprintf(fp, "Input edge %d num inputs %d num outputs %d\n", k, - pb_graph_pins[i][j].input_edges[k]->num_input_pins, - pb_graph_pins[i][j].input_edges[k]->num_output_pins); - print_tabs(fp, level + 3); - fprintf(fp, "Input edge inputs\n"); - for (m = 0; - m < pb_graph_pins[i][j].input_edges[k]->num_input_pins; - m++) { - print_tabs(fp, level + 3); - fprintf(fp, "pin number %d port_name \"%s\"\n", - pb_graph_pins[i][j].input_edges[k]->input_pins[m]->pin_number, - pb_graph_pins[i][j].input_edges[k]->input_pins[m]->port->name); - } - print_tabs(fp, level + 3); - fprintf(fp, "Input edge outputs\n"); - for (m = 0; - m < pb_graph_pins[i][j].input_edges[k]->num_output_pins; - m++) { - print_tabs(fp, level + 3); - fprintf(fp, - "pin number %d port_name \"%s\" parent type \"%s\" parent index %d\n", - pb_graph_pins[i][j].input_edges[k]->output_pins[m]->pin_number, - pb_graph_pins[i][j].input_edges[k]->output_pins[m]->port->name, - pb_graph_pins[i][j].input_edges[k]->output_pins[m]->parent_node->pb_type->name, - pb_graph_pins[i][j].input_edges[k]->output_pins[m]->parent_node->placement_index); - } - } - for (k = 0; k < pb_graph_pins[i][j].num_output_edges; k++) { - print_tabs(fp, level + 2); - fprintf(fp, "Output edge %d num inputs %d num outputs %d\n", k, - pb_graph_pins[i][j].output_edges[k]->num_input_pins, - pb_graph_pins[i][j].output_edges[k]->num_output_pins); - print_tabs(fp, level + 3); - fprintf(fp, "Output edge inputs\n"); - for (m = 0; - m < pb_graph_pins[i][j].output_edges[k]->num_input_pins; - m++) { - print_tabs(fp, level + 3); - fprintf(fp, "pin number %d port_name \"%s\"\n", - pb_graph_pins[i][j].output_edges[k]->input_pins[m]->pin_number, - pb_graph_pins[i][j].output_edges[k]->input_pins[m]->port->name); - } - print_tabs(fp, level + 3); - fprintf(fp, "Output edge outputs\n"); - for (m = 0; - m < pb_graph_pins[i][j].output_edges[k]->num_output_pins; - m++) { - print_tabs(fp, level + 3); - fprintf(fp, - "pin number %d port_name \"%s\" parent type \"%s\" parent index %d\n", - pb_graph_pins[i][j].output_edges[k]->output_pins[m]->pin_number, - pb_graph_pins[i][j].output_edges[k]->output_pins[m]->port->name, - pb_graph_pins[i][j].output_edges[k]->output_pins[m]->parent_node->pb_type->name, - pb_graph_pins[i][j].output_edges[k]->output_pins[m]->parent_node->placement_index); - } - } - } - } -} - -static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num, - int index_mode, - t_pb_graph_pin*** input_pins, - int num_input_ports, - int* num_input_pins, - t_interconnect* cur_interc) { - t_token * tokens; - int num_tokens; - int i_tokens, cur_port_index, cur_pin_index; - t_pb_graph_node** cur_node; - int index_cur_node, i_index_cur_node; - t_pb_graph_node* tmp_node; - char* cur_pb_name; - char* cur_pin_name; - e_pb_graph_pin_type pin_type; - int lsb_pb, msb_pb; - int i_lsb_pb; - int lsb_pin, msb_pin, msb_pin_max; - int pb_name_found, pin_name_found; - int full_bus = 0; - int i_num_input_ports; - int i_num_output_edges; - int i_pb_type_in_mode, index_pb_type; - - // Get the tokens from the loop_breaker_string - num_tokens = 0; - tokens = GetTokensFromString(loop_breaker_string, &num_tokens); - - i_tokens = 0; - tmp_node = (t_pb_graph_node*) my_malloc(sizeof(t_pb_graph_node)); - while (i_tokens < num_tokens) { - // *cur_node = (t_pb_graph_node*) my_malloc(sizeof(t_pb_graph_node)); - pb_name_found = 0; - pin_name_found = 0; - msb_pin = lsb_pin = msb_pb = lsb_pb = 0; - if (tokens[i_tokens].type != TOKEN_STRING) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: first element of a pair pb+pin should be a string\n", - line_num); - exit(1); - } - cur_pb_name = tokens[i_tokens].data; - /* no distinction is made between children and parent nodes */ - for (i_num_input_ports = 0 ; i_num_input_ports < num_input_ports ; i_num_input_ports ++) { - if (0 == strcmp(cur_pb_name, input_pins[i_num_input_ports][0]->parent_node->pb_type->name)) { - pb_name_found = 1; - // cur_node[0] = input_pins[i_num_input_ports][0]->parent_node; - tmp_node = input_pins[i_num_input_ports][0]->parent_node; - break; - } - } - if (0 == pb_name_found) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Pb name not found in current interconnection\n", - line_num); - exit(1); - } - i_tokens++; - /* We deal with three cases: nothing, a wire, a bus */ - /* First, the bus/wire */ - //tmp_node = cur_node[0]; - if( tokens[i_tokens].type == TOKEN_OPEN_SQUARE_BRACKET) { - i_tokens++; - if( tokens[i_tokens].type != TOKEN_INT) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Int expected inside of the pb bracket\n", - line_num); - exit(1); - } - msb_pb = my_atoi(tokens[i_tokens].data); - if (msb_pb > tmp_node->pb_type->num_pb) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: MSB pb larger than the number of pb\n", - line_num); - exit(1); - } - i_tokens++; - /* bus */ - if( tokens[i_tokens].type == TOKEN_COLON) { - i_tokens++; - if (tokens[i_tokens].type != TOKEN_INT) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Int expected inside of the pb bracket for LSB\n", - line_num); - exit(1); - } - lsb_pb = my_atoi(tokens[i_tokens].data); - if (lsb_pb > msb_pb) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: MSB supposed to be superior to LSB\n", - line_num); - exit(1); - } - i_tokens++; - if (tokens[i_tokens].type != TOKEN_CLOSE_SQUARE_BRACKET) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Expect closing bracket after the bus\n", - line_num); - exit(1); - } - i_tokens++; - } - /* wire */ - else if (tokens[i_tokens].type == TOKEN_CLOSE_SQUARE_BRACKET) { - lsb_pb = msb_pb; - } - else { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Expect closing bracket or colon after pin number\n", - line_num); - exit(1); - } - } - /* If no bracket was used, we use need to apply the loop breaker to all the pbs with that name */ - else { - //msb_pb = cur_node[0]->pb_type->num_pb - 1; - msb_pb = tmp_node->pb_type->num_pb - 1; - lsb_pb = 0; - } - index_cur_node = 0; - if (tmp_node->parent_pb_graph_node == NULL) {/* if pb_graph_head */ - cur_node = (t_pb_graph_node**) my_malloc(sizeof(t_pb_graph_node*)); - cur_node[0] = tmp_node; - index_cur_node = 1; - } - else { - cur_node = (t_pb_graph_node**) my_malloc(sizeof(t_pb_graph_node*) * (msb_pb + 1)); - for (i_pb_type_in_mode = 0 ; - i_pb_type_in_mode < tmp_node->parent_pb_graph_node->pb_type->modes[index_mode].num_pb_type_children ; - i_pb_type_in_mode ++) { - if (0 == strcmp(cur_pb_name, - tmp_node->parent_pb_graph_node->child_pb_graph_nodes[index_mode][i_pb_type_in_mode][0].pb_type->name)) { - index_pb_type = i_pb_type_in_mode; - break; - } - } - /* if previous conditions are respected, we should always find the index of the pb type */ - assert (index_pb_type != tmp_node->parent_pb_graph_node->pb_type->modes[index_mode].num_pb_type_children); - for ( i_lsb_pb = lsb_pb ; i_lsb_pb < msb_pb + 1 ; i_lsb_pb ++) { - cur_node[index_cur_node] = - &(tmp_node->parent_pb_graph_node->child_pb_graph_nodes[index_mode][index_pb_type][i_lsb_pb]); - index_cur_node++; - } - } - if (tokens[i_tokens].type != TOKEN_DOT) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Pb name should be followed by a dot\n", - line_num); - exit(1); - } - i_tokens++; - - /* Pin definition */ - if (tokens[i_tokens].type != TOKEN_STRING) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Pin name expected after dot\n", - line_num); - exit(1); - } - cur_pin_name = tokens[i_tokens].data; - i_tokens++; - /* We deal with three cases: nothing, a wire, a bus */ - /* First, the bus/wire */ - if( tokens[i_tokens].type == TOKEN_OPEN_SQUARE_BRACKET) { - i_tokens++; - if( tokens[i_tokens].type != TOKEN_INT) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Int expected inside of the pin bracket\n", - line_num); - exit(1); - } - msb_pin = my_atoi(tokens[i_tokens].data); - i_tokens++; - /* bus */ - if( tokens[i_tokens].type == TOKEN_COLON) { - i_tokens++; - if (tokens[i_tokens].type != TOKEN_INT) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Int expected inside of the bracket for LSB\n", - line_num); - exit(1); - } - lsb_pin = my_atoi(tokens[i_tokens].data); - if (lsb_pin > msb_pin) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: MSB supposed to be superior to LSB\n", - line_num); - exit(1); - } - i_tokens++; - if (tokens[i_tokens].type != TOKEN_CLOSE_SQUARE_BRACKET) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Expect closing bracket after the bus\n", - line_num); - exit(1); - } - i_tokens++; - } - /* wire */ - else if (tokens[i_tokens].type == TOKEN_CLOSE_SQUARE_BRACKET) { - lsb_pin = msb_pin; - } - else { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Expect closing bracket or colon after pin number\n", - line_num); - exit(1); - } - } - else { - /* With no bus/wire given, we take the full bus of the pin given*/ - full_bus =1; - } - /* Since we have the pin name, we find the right position of the pin - * in the associated node and check that msb is not superior to the - * number of pins we have. */ - /* Check inputs */ - for (cur_port_index = 0 ; cur_port_index < cur_node[0]->num_input_ports ; cur_port_index ++) { - if (0 == strcmp(cur_pin_name,cur_node[0]->input_pins[cur_port_index][0].port->name)) { - pin_name_found = 1; - pin_type = PB_PIN_INPUT; - msb_pin_max = cur_node[0]->num_input_pins[cur_port_index] - 1; - break; - } - } - /* Check outputs if not input */ - if (0 == pin_name_found) { - for (cur_port_index = 0 ; cur_port_index < cur_node[0]->num_output_ports ; cur_port_index ++) { - if (0 == strcmp(cur_pin_name,cur_node[0]->output_pins[cur_port_index][0].port->name)) { - pin_name_found = 1; - pin_type = PB_PIN_OUTPUT; - msb_pin_max = cur_node[0]->num_output_pins[cur_port_index] - 1; - break; - } - } - } - /* Check clocks */ - if (0 == pin_name_found) { - for (cur_port_index = 0 ; cur_port_index < cur_node[0]->num_clock_ports ; cur_port_index ++) { - if (0 == strcmp(cur_pin_name,cur_node[0]->clock_pins[cur_port_index][0].port->name)) { - pin_name_found = 1; - pin_type = PB_PIN_CLOCK; - msb_pin_max = cur_node[0]->num_clock_pins[cur_port_index] - 1; - break; - } - } - } - if (0 == pin_name_found) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Pin name not found in given pb\n", - line_num); - exit(1); - } - - if (1 == full_bus) { - switch(pin_type) { - case PB_PIN_INPUT: - msb_pin = cur_node[0]->num_input_pins[cur_port_index] - 1; - break; - case PB_PIN_OUTPUT: - msb_pin = cur_node[0]->num_output_pins[cur_port_index] - 1; - break; - case PB_PIN_CLOCK: - msb_pin = cur_node[0]->num_clock_pins[cur_port_index] - 1; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] I) Pin was not found and this message should never be accessed in theory." - " Report it for a fix if it happens\n", - line_num); - exit(1); - } - msb_pin_max = msb_pin; - lsb_pin = 0; - } - /* Check that the pin number found in the string is valid */ - if (msb_pin < 0 || msb_pin > msb_pin_max) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Issue with MSB\n", - line_num); - exit(1); - } - if (lsb_pin < 0 || lsb_pin > msb_pin) { - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] loop_breaker: Issue with LSB\n", - line_num); - exit(1); - } - for (i_index_cur_node = 0 ; i_index_cur_node < index_cur_node ; i_index_cur_node ++) { - for (cur_pin_index = lsb_pin ; cur_pin_index < (msb_pin + 1) ; cur_pin_index++) { - switch(pin_type) { - case PB_PIN_INPUT: - for (i_num_output_edges = 0 ; - i_num_output_edges < cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].num_output_edges ; - i_num_output_edges ++) { - if (cur_interc == cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) { - cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE; - - if (NULL != cur_interc->loop_breaker_delay_before_min) { - cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_min - = cur_interc->loop_breaker_delay_before_min; - } - if (NULL != cur_interc->loop_breaker_delay_before_max) { - cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_max - = cur_interc->loop_breaker_delay_before_max; - } - if (NULL != cur_interc->loop_breaker_delay_after_min) { - cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_min - = cur_interc->loop_breaker_delay_after_min; - } - if (NULL != cur_interc->loop_breaker_delay_after_max) { - cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_max - = cur_interc->loop_breaker_delay_after_max; - } - } - } - break; - case PB_PIN_OUTPUT: - for (i_num_output_edges = 0 ; - i_num_output_edges < cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].num_output_edges ; - i_num_output_edges ++) { - if (cur_interc == cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) { - cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE; - - if (NULL != cur_interc->loop_breaker_delay_before_min) { - cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_min - = cur_interc->loop_breaker_delay_before_min; - } - if (NULL != cur_interc->loop_breaker_delay_before_max) { - cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_max - = cur_interc->loop_breaker_delay_before_max; - } - if (NULL != cur_interc->loop_breaker_delay_after_min) { - cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_min - = cur_interc->loop_breaker_delay_after_min; - } - if (NULL != cur_interc->loop_breaker_delay_after_max) { - cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_max - = cur_interc->loop_breaker_delay_after_max; - } - } - } - break; - case PB_PIN_CLOCK: - for (i_num_output_edges = 0 ; - i_num_output_edges < cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].num_output_edges ; - i_num_output_edges ++) { - if (cur_interc == cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) { - cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE; - - if (NULL != cur_interc->loop_breaker_delay_before_min) { - cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_min - = cur_interc->loop_breaker_delay_before_min; - } - if (NULL != cur_interc->loop_breaker_delay_before_max) { - cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_before_max - = cur_interc->loop_breaker_delay_before_max; - } - if (NULL != cur_interc->loop_breaker_delay_after_min) { - cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_min - = cur_interc->loop_breaker_delay_after_min; - } - if (NULL != cur_interc->loop_breaker_delay_after_max) { - cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->loop_breaker_delay_after_max - = cur_interc->loop_breaker_delay_after_max; - } - } - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, - "[LINE %d] II) Pin was not found and this message should never be accessed in theory." - " Report it for a fix if it happens\n", - line_num); - exit(1); - } - } - } - } - my_free(cur_node); - return; -} diff --git a/vpr7_x2p/vpr/SRC/pack/pb_type_graph.h b/vpr7_x2p/vpr/SRC/pack/pb_type_graph.h deleted file mode 100644 index e4605df9c..000000000 --- a/vpr7_x2p/vpr/SRC/pack/pb_type_graph.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef PB_TYPE_GRAPH_H -#define PB_TYPE_GRAPH_H - -void alloc_and_load_all_pb_graphs(boolean load_power_structures); -void echo_pb_graph(char * filename); -void free_all_pb_graph_nodes(void); -t_pb_graph_pin *** alloc_and_load_port_pin_ptrs_from_string(INP int line_num, - INP const t_pb_graph_node *pb_graph_parent_node, - INP t_pb_graph_node **pb_graph_children_nodes, - INP const char * port_string, - OUTP int ** num_ptrs, - OUTP int * num_sets, - INP boolean is_input_to_interc, - INP boolean interconnect_error_check); -#endif - diff --git a/vpr7_x2p/vpr/SRC/pack/pb_type_graph_annotations.c b/vpr7_x2p/vpr/SRC/pack/pb_type_graph_annotations.c deleted file mode 100755 index 090995f89..000000000 --- a/vpr7_x2p/vpr/SRC/pack/pb_type_graph_annotations.c +++ /dev/null @@ -1,384 +0,0 @@ -/* Jason Luu - April 15, 2011 - Loads statistical information (min/max delays, power) onto the pb_graph. */ - -#include -#include -#include -#include - -#include "util.h" -#include "arch_types.h" -#include "vpr_types.h" -#include "globals.h" -#include "vpr_utils.h" -#include "pb_type_graph.h" -#include "token.h" -#include "pb_type_graph_annotations.h" - -static void load_pack_pattern_annotations(INP int line_num, INOUTP t_pb_graph_node *pb_graph_node, - INP int mode, INP char *annot_in_pins, INP char *annot_out_pins, - INP char *value); - -static void load_critical_path_annotations(INP int line_num, - INOUTP t_pb_graph_node *pb_graph_node, INP int mode, - INP enum e_pin_to_pin_annotation_format input_format, - INP enum e_pin_to_pin_delay_annotations delay_type, - INP char *annot_in_pins, INP char *annot_out_pins, INP char* value); - -void load_pb_graph_pin_to_pin_annotations(INOUTP t_pb_graph_node *pb_graph_node) { - int i, j, k, m; - const t_pb_type *pb_type; - t_pin_to_pin_annotation *annotations; - - pb_type = pb_graph_node->pb_type; - - /* Load primitive critical path delays */ - if (pb_type->num_modes == 0) { - annotations = pb_type->annotations; - for (i = 0; i < pb_type->num_annotations; i++) { - if (annotations[i].type == E_ANNOT_PIN_TO_PIN_DELAY) { - for (j = 0; j < annotations[i].num_value_prop_pairs; j++) { - if (annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_MAX - || annotations[i].prop[j] - == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX - || annotations[i].prop[j] - == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) { - load_critical_path_annotations(annotations[i].line_num, pb_graph_node, OPEN, - annotations[i].format, (enum e_pin_to_pin_delay_annotations)annotations[i].prop[j], - annotations[i].input_pins, - annotations[i].output_pins, - annotations[i].value[j]); - } else { - assert( - annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_MIN || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN || annotations[i].prop[j] == E_ANNOT_PIN_TO_PIN_DELAY_THOLD); - } - } - } else { - /* Todo: - load_hold_time_constraints_annotations(pb_graph_node); - load_power_annotations(pb_graph_node); - */ - } - } - } else { - /* Load interconnect delays */ - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_interconnect; j++) { - annotations = pb_type->modes[i].interconnect[j].annotations; - for (k = 0; - k < pb_type->modes[i].interconnect[j].num_annotations; - k++) { - if (annotations[k].type == E_ANNOT_PIN_TO_PIN_DELAY) { - for (m = 0; m < annotations[k].num_value_prop_pairs; - m++) { - if (annotations[k].prop[m] - == E_ANNOT_PIN_TO_PIN_DELAY_MAX - || annotations[k].prop[m] - == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX - || annotations[k].prop[m] - == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) { - load_critical_path_annotations(annotations[k].line_num, pb_graph_node, i, - annotations[k].format, - (enum e_pin_to_pin_delay_annotations)annotations[k].prop[m], - annotations[k].input_pins, - annotations[k].output_pins, - annotations[k].value[m]); - } else { - assert( - annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_MIN || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN || annotations[k].prop[m] == E_ANNOT_PIN_TO_PIN_DELAY_THOLD); - } - } - } else if (annotations[k].type - == E_ANNOT_PIN_TO_PIN_PACK_PATTERN) { - assert(annotations[k].num_value_prop_pairs == 1); - load_pack_pattern_annotations(annotations[k].line_num, pb_graph_node, i, - annotations[k].input_pins, - annotations[k].output_pins, - annotations[k].value[0]); - } else { - /* Todo: - load_hold_time_constraints_annotations(pb_graph_node); - load_power_annotations(pb_graph_node); - */ - } - } - } - } - } - - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - for (k = 0; k < pb_type->modes[i].pb_type_children[j].num_pb; k++) { - load_pb_graph_pin_to_pin_annotations( - &pb_graph_node->child_pb_graph_nodes[i][j][k]); - } - } - } -} - -/* - Add the pattern name to the pack_pattern field for each pb_graph_edge that is used in a pack pattern - */ -static void load_pack_pattern_annotations(INP int line_num, INOUTP t_pb_graph_node *pb_graph_node, - INP int mode, INP char *annot_in_pins, INP char *annot_out_pins, - INP char *value) { - int i, j, k, m, n, p, iedge; - t_pb_graph_pin ***in_port, ***out_port; - int *num_in_ptrs, *num_out_ptrs, num_in_sets, num_out_sets; - t_pb_graph_node **children = NULL; - - children = pb_graph_node->child_pb_graph_nodes[mode]; - in_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, children, - annot_in_pins, &num_in_ptrs, &num_in_sets, FALSE, FALSE); - out_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, children, - annot_out_pins, &num_out_ptrs, &num_out_sets, FALSE, FALSE); - - /* Discover edge then annotate edge with name of pack pattern */ - k = 0; - for (i = 0; i < num_in_sets; i++) { - for (j = 0; j < num_in_ptrs[i]; j++) { - p = 0; - for (m = 0; m < num_out_sets; m++) { - for (n = 0; n < num_out_ptrs[m]; n++) { - for (iedge = 0; iedge < in_port[i][j]->num_output_edges; - iedge++) { - if (in_port[i][j]->output_edges[iedge]->output_pins[0] - == out_port[m][n]) { - break; - } - } - /* Xifan Tang: bypass the edges that are disabled in packing */ - /* - if ((iedge != in_port[i][j]->num_output_edges) - && (TRUE == in_port[i][j]->output_edges[iedge]->interconnect->parent_mode->disabled_in_packing)) { - continue; - } - */ - /* END */ - /* jluu Todo: This is inefficient, I know the interconnect so I know what edges exist - can use this info to only annotate existing edges */ - if (iedge != in_port[i][j]->num_output_edges) { - in_port[i][j]->output_edges[iedge]->num_pack_patterns++; - in_port[i][j]->output_edges[iedge]->pack_pattern_names = (char**) - my_realloc( - in_port[i][j]->output_edges[iedge]->pack_pattern_names, - sizeof(char*) - * in_port[i][j]->output_edges[iedge]->num_pack_patterns); - in_port[i][j]->output_edges[iedge]->pack_pattern_names[in_port[i][j]->output_edges[iedge]->num_pack_patterns - - 1] = value; - } - p++; - } - } - k++; - } - } - - if (in_port != NULL) { - for (i = 0; i < num_in_sets; i++) { - free(in_port[i]); - } - free(in_port); - free(num_in_ptrs); - } - if (out_port != NULL) { - for (i = 0; i < num_out_sets; i++) { - free(out_port[i]); - } - free(out_port); - free(num_out_ptrs); - } -} - -static void load_critical_path_annotations(INP int line_num, - INOUTP t_pb_graph_node *pb_graph_node, INP int mode, - INP enum e_pin_to_pin_annotation_format input_format, - INP enum e_pin_to_pin_delay_annotations delay_type, - INP char *annot_in_pins, INP char *annot_out_pins, INP char* value) { - - int i, j, k, m, n, p, iedge; - t_pb_graph_pin ***in_port, ***out_port; - int *num_in_ptrs, *num_out_ptrs, num_in_sets, num_out_sets; - float **delay_matrix; - t_pb_graph_node **children = NULL; - - int count, prior_offset; - int num_inputs, num_outputs; - - in_port = out_port = NULL; - num_out_sets = num_in_sets = 0; - num_out_ptrs = num_in_ptrs = NULL; - - /* Primarily 3 kinds of delays that affect critical path: - 1. Intrablock interconnect delays - 2. Combinational primitives (pin-to-pin delays of primitive) - 3. Sequential primitives (setup and clock-to-q times) - - Note: Proper I/O modelling requires knowledge of the extra-chip world (eg. the load that pin is driving, drive strength, etc) - For now, I/O delays are modelled as a constant in the architecture file by setting the pad-I/O block interconnect delay to be a constant I/O delay - - Algorithm: Intrablock and combinational primitive delays apply to edges - Sequential delays apply to pins - 1. Determine if delay applies to pin or edge - 2. Format the delay information - 3. Load delay information - */ - - /* Determine what pins to read based on delay type */ - num_inputs = num_outputs = 0; - if (mode == OPEN) { - children = NULL; - } else { - children = pb_graph_node->child_pb_graph_nodes[mode]; - } - if (delay_type == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP) { - assert(pb_graph_node->pb_type->blif_model != NULL); - in_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, - children, annot_in_pins, &num_in_ptrs, &num_in_sets, FALSE, - FALSE); - } else if (delay_type == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX) { - assert(pb_graph_node->pb_type->blif_model != NULL); - in_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, - children, annot_in_pins, &num_in_ptrs, &num_in_sets, FALSE, - FALSE); - } else { - assert(delay_type == E_ANNOT_PIN_TO_PIN_DELAY_MAX); - in_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, - children, annot_in_pins, &num_in_ptrs, &num_in_sets, FALSE, - FALSE); - out_port = alloc_and_load_port_pin_ptrs_from_string(line_num, pb_graph_node, - children, annot_out_pins, &num_out_ptrs, &num_out_sets, FALSE, - FALSE); - } - - num_inputs = 0; - for (i = 0; i < num_in_sets; i++) { - num_inputs += num_in_ptrs[i]; - } - - if (out_port != NULL) { - num_outputs = 0; - for (i = 0; i < num_out_sets; i++) { - num_outputs += num_out_ptrs[i]; - } - } else { - num_outputs = 1; - } - - delay_matrix = (float**)my_malloc(sizeof(float*) * num_inputs); - for (i = 0; i < num_inputs; i++) { - delay_matrix[i] = (float*)my_malloc(sizeof(float) * num_outputs); - } - - if (input_format == E_ANNOT_PIN_TO_PIN_MATRIX) { - my_atof_2D(delay_matrix, num_inputs, num_outputs, value); - } else { - assert(input_format == E_ANNOT_PIN_TO_PIN_CONSTANT); - for (i = 0; i < num_inputs; i++) { - for (j = 0; j < num_outputs; j++) { - delay_matrix[i][j] = atof(value); - } - } - } - - if (delay_type == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP - || delay_type == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX) { - k = 0; - for (i = 0; i < num_in_sets; i++) { - for (j = 0; j < num_in_ptrs[i]; j++) { - in_port[i][j]->tsu_tco = delay_matrix[k][0]; - k++; - } - } - } else { - if (pb_graph_node->pb_type->num_modes != 0) { - /* Not a primitive, find pb_graph_edge */ - k = 0; - for (i = 0; i < num_in_sets; i++) { - for (j = 0; j < num_in_ptrs[i]; j++) { - p = 0; - for (m = 0; m < num_out_sets; m++) { - for (n = 0; n < num_out_ptrs[m]; n++) { - for (iedge = 0; - iedge < in_port[i][j]->num_output_edges; - iedge++) { - if (in_port[i][j]->output_edges[iedge]->output_pins[0] - == out_port[m][n]) { - assert( - in_port[i][j]->output_edges[iedge]->delay_max == 0); - break; - } - } - /* jluu Todo: This is inefficient, I know the interconnect so I know what edges exist - can use this info to only annotate existing edges */ - if (iedge != in_port[i][j]->num_output_edges) { - in_port[i][j]->output_edges[iedge]->delay_max = - delay_matrix[k][p]; - } - p++; - } - } - k++; - } - } - } else { - /* Primitive, allocate appropriate nodes */ - k = 0; - for (i = 0; i < num_in_sets; i++) { - for (j = 0; j < num_in_ptrs[i]; j++) { - count = p = 0; - for (m = 0; m < num_out_sets; m++) { - for (n = 0; n < num_out_ptrs[m]; n++) { - /* OPEN indicates that connection does not exist */ - if (delay_matrix[k][p] != OPEN) { - count++; - } - p++; - } - } - prior_offset = in_port[i][j]->num_pin_timing; - in_port[i][j]->num_pin_timing = prior_offset + count; - in_port[i][j]->pin_timing_del_max = (float*) my_realloc(in_port[i][j]->pin_timing_del_max, - sizeof(float) * in_port[i][j]->num_pin_timing); - in_port[i][j]->pin_timing = (t_pb_graph_pin**)my_realloc(in_port[i][j]->pin_timing, - sizeof(t_pb_graph_pin*) * in_port[i][j]->num_pin_timing); - p = 0; - count = 0; - for (m = 0; m < num_out_sets; m++) { - for (n = 0; n < num_out_ptrs[m]; n++) { - if (delay_matrix[k][p] != OPEN) { - in_port[i][j]->pin_timing_del_max[prior_offset + count] = - delay_matrix[k][p]; - in_port[i][j]->pin_timing[prior_offset + count] = - out_port[m][n]; - count++; - } - p++; - } - } - assert(in_port[i][j]->num_pin_timing == prior_offset + count); - k++; - } - } - } - } - if (in_port != NULL) { - for (i = 0; i < num_in_sets; i++) { - free(in_port[i]); - } - free(in_port); - free(num_in_ptrs); - } - if (out_port != NULL) { - for (i = 0; i < num_out_sets; i++) { - free(out_port[i]); - } - free(out_port); - free(num_out_ptrs); - } - for (i = 0; i < num_inputs; i++) { - free(delay_matrix[i]); - } - free(delay_matrix); -} diff --git a/vpr7_x2p/vpr/SRC/pack/pb_type_graph_annotations.h b/vpr7_x2p/vpr/SRC/pack/pb_type_graph_annotations.h deleted file mode 100755 index 425f02bd9..000000000 --- a/vpr7_x2p/vpr/SRC/pack/pb_type_graph_annotations.h +++ /dev/null @@ -1,12 +0,0 @@ -/** - * Jason Luu - * April 15, 2011 - * pb_type_graph_annotations loads statistical information onto the different nodes/edges of a pb_type_graph. These statistical informations include delays, capacitance, etc. - */ - -#ifndef PB_TYPE_GRAPH_ANNOTATIONS_H -#define PB_TYPE_GRAPH_ANNOTATIONS_H - -void load_pb_graph_pin_to_pin_annotations(INOUTP t_pb_graph_node *pb_graph_node); - -#endif diff --git a/vpr7_x2p/vpr/SRC/pack/prepack.c b/vpr7_x2p/vpr/SRC/pack/prepack.c deleted file mode 100644 index f4f43ad13..000000000 --- a/vpr7_x2p/vpr/SRC/pack/prepack.c +++ /dev/null @@ -1,1099 +0,0 @@ -/* - Prepacking: Group together technology-mapped netlist blocks before packing. This gives hints to the packer on what groups of blocks to keep together during packing. - Primary purpose 1) "Forced" packs (eg LUT+FF pair) - 2) Carry-chains - - - Duties: Find pack patterns in architecture, find pack patterns in netlist. - - Author: Jason Luu - March 12, 2012 - */ -#include -#include -#include - -#include "read_xml_arch_file.h" -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "hash.h" -#include "prepack.h" -#include "vpr_utils.h" -#include "ReadOptions.h" - -/*****************************************/ -/*Local Function Declaration */ -/*****************************************/ -static int add_pattern_name_to_hash(INOUTP struct s_hash **nhash, - INP char *pattern_name, INOUTP int *ncount); -static void discover_pattern_names_in_pb_graph_node( - INOUTP t_pb_graph_node *pb_graph_node, INOUTP struct s_hash **nhash, - INOUTP int *ncount); -static void forward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin); -static void backward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin); -static t_pack_patterns *alloc_and_init_pattern_list_from_hash(INP int ncount, - INOUTP struct s_hash **nhash); -static t_pb_graph_edge * find_expansion_edge_of_pattern(INP int pattern_index, - INP t_pb_graph_node *pb_graph_node); -static void forward_expand_pack_pattern_from_edge( - INP t_pb_graph_edge *expansion_edge, - INOUTP t_pack_patterns *list_of_packing_patterns, - INP int curr_pattern_index, INP int *L_num_blocks, INP boolean make_root_of_chain); -static void backward_expand_pack_pattern_from_edge( - INP t_pb_graph_edge* expansion_edge, - INOUTP t_pack_patterns *list_of_packing_patterns, - INP int curr_pattern_index, INP t_pb_graph_pin *destination_pin, - INP t_pack_pattern_block *destination_block, INP int *L_num_blocks); -static int compare_pack_pattern(const t_pack_patterns *pattern_a, const t_pack_patterns *pattern_b); -static void free_pack_pattern(INOUTP t_pack_pattern_block *pattern_block, INOUTP t_pack_pattern_block **pattern_block_list); -static t_pack_molecule *try_create_molecule( - INP t_pack_patterns *list_of_pack_patterns, INP int pack_pattern_index, - INP int block_index); -static boolean try_expand_molecule(INOUTP t_pack_molecule *molecule, - INP int logical_block_index, - INP t_pack_pattern_block *current_pattern_block); -static void print_pack_molecules(INP const char *fname, - INP t_pack_patterns *list_of_pack_patterns, INP int num_pack_patterns, - INP t_pack_molecule *list_of_molecules); -static t_pb_graph_node *get_expected_lowest_cost_primitive_for_logical_block(INP int ilogical_block); -static t_pb_graph_node *get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node(INP int ilogical_block, INP t_pb_graph_node *curr_pb_graph_node, OUTP float *cost); -static int find_new_root_atom_for_chain(INP int block_index, INP t_pack_patterns *list_of_pack_pattern); - -/*****************************************/ -/*Function Definitions */ -/*****************************************/ - -/** - * Find all packing patterns in architecture - * [0..num_packing_patterns-1] - * - * Limitations: Currently assumes that forced pack nets must be single-fanout as this covers all the reasonable architectures we wanted. - More complicated structures should probably be handled either downstream (general packing) or upstream (in tech mapping) - * If this limitation is too constraining, code is designed so that this limitation can be removed - */ -t_pack_patterns *alloc_and_load_pack_patterns(OUTP int *num_packing_patterns) { - int i, j, ncount, k; - int L_num_blocks; - struct s_hash **nhash; - t_pack_patterns *list_of_packing_patterns; - t_pb_graph_edge *expansion_edge; - - /* alloc and initialize array of packing patterns based on architecture complex blocks */ - nhash = alloc_hash_table(); - ncount = 0; - for (i = 0; i < num_types; i++) { - discover_pattern_names_in_pb_graph_node(type_descriptors[i].pb_graph_head, nhash, &ncount); - } - - list_of_packing_patterns = alloc_and_init_pattern_list_from_hash(ncount, - nhash); - - /* load packing patterns by traversing the edges to find edges belonging to pattern */ - for (i = 0; i < ncount; i++) { - for (j = 0; j < num_types; j++) { - expansion_edge = find_expansion_edge_of_pattern(i, type_descriptors[j].pb_graph_head); - if (expansion_edge == NULL) { - continue; - } - L_num_blocks = 0; - list_of_packing_patterns[i].base_cost = 0; - backward_expand_pack_pattern_from_edge(expansion_edge, list_of_packing_patterns, i, NULL, NULL, &L_num_blocks); - list_of_packing_patterns[i].num_blocks = L_num_blocks; - - /* Default settings: A section of a netlist must match all blocks in a pack pattern before it can be made a molecule except for carry-chains. For carry-chains, since carry-chains are typically - quite flexible in terms of size, it is optional whether or not an atom in a netlist matches any particular block inside the chain */ - list_of_packing_patterns[i].is_block_optional = (boolean*) my_malloc(L_num_blocks * sizeof(boolean)); - for(k = 0; k < L_num_blocks; k++) { - list_of_packing_patterns[i].is_block_optional[k] = FALSE; - if(list_of_packing_patterns[i].is_chain && list_of_packing_patterns[i].root_block->block_id != k) { - list_of_packing_patterns[i].is_block_optional[k] = TRUE; - } - } - break; - } - } - - free_hash_table(nhash); - - *num_packing_patterns = ncount; - - return list_of_packing_patterns; -} - -/** - * Adds pack pattern name to hashtable of pack pattern names. - */ -static int add_pattern_name_to_hash(INOUTP struct s_hash **nhash, - INP char *pattern_name, INOUTP int *ncount) { - struct s_hash *hash_value; - - hash_value = insert_in_hash_table(nhash, pattern_name, *ncount); - if (hash_value->count == 1) { - assert(*ncount == hash_value->index); - (*ncount)++; - } - return hash_value->index; -} - -/** - * Locate all pattern names - * Side-effect: set all pb_graph_node temp_scratch_pad field to NULL - * For cases where a pattern inference is "obvious", mark it as obvious. - */ -static void discover_pattern_names_in_pb_graph_node( - INOUTP t_pb_graph_node *pb_graph_node, INOUTP struct s_hash **nhash, - INOUTP int *ncount) { - int i, j, k, m; - int index; - boolean hasPattern; - /* Iterate over all edges to discover if an edge in current physical block belongs to a pattern - If edge does, then record the name of the pattern in a hash table - */ - - if (pb_graph_node == NULL) { - return; - } - - pb_graph_node->temp_scratch_pad = NULL; - - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - hasPattern = FALSE; - for (k = 0; k < pb_graph_node->input_pins[i][j].num_output_edges; k++) { - /* Xifan Tang: bypass pack_patterns whose parent mode is disabled_in_packing*/ - /* - if (TRUE == pb_graph_node->input_pins[i][j].output_edges[k]->interconnect->parent_mode->disabled_in_packing) { - continue; - } - */ - /* END */ - for (m = 0; m < pb_graph_node->input_pins[i][j].output_edges[k]->num_pack_patterns; m++) { - hasPattern = TRUE; - index = add_pattern_name_to_hash(nhash, - pb_graph_node->input_pins[i][j].output_edges[k]->pack_pattern_names[m], - ncount); - if (pb_graph_node->input_pins[i][j].output_edges[k]->pack_pattern_indices == NULL) { - pb_graph_node->input_pins[i][j].output_edges[k]->pack_pattern_indices = (int*) my_malloc(pb_graph_node->input_pins[i][j].output_edges[k]->num_pack_patterns * sizeof(int)); - } - pb_graph_node->input_pins[i][j].output_edges[k]->pack_pattern_indices[m] = index; - } - } - if (hasPattern == TRUE) { - forward_infer_pattern(&pb_graph_node->input_pins[i][j]); - backward_infer_pattern(&pb_graph_node->input_pins[i][j]); - } - } - } - - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - hasPattern = FALSE; - for (k = 0; k < pb_graph_node->output_pins[i][j].num_output_edges; k++) { - /* Xifan Tang: bypass pack_patterns whose parent mode is disabled_in_packing*/ - /* - if (TRUE == pb_graph_node->output_pins[i][j].output_edges[k]->interconnect->parent_mode->disabled_in_packing) { - continue; - } - */ - /* END */ - for (m = 0; m < pb_graph_node->output_pins[i][j].output_edges[k]->num_pack_patterns; m++) { - hasPattern = TRUE; - index = add_pattern_name_to_hash(nhash, - pb_graph_node->output_pins[i][j].output_edges[k]->pack_pattern_names[m], - ncount); - if (pb_graph_node->output_pins[i][j].output_edges[k]->pack_pattern_indices == NULL) { - pb_graph_node->output_pins[i][j].output_edges[k]->pack_pattern_indices = (int*) my_malloc(pb_graph_node->output_pins[i][j].output_edges[k]->num_pack_patterns* sizeof(int)); - } - pb_graph_node->output_pins[i][j].output_edges[k]->pack_pattern_indices[m] = index; - } - } - if (hasPattern == TRUE) { - forward_infer_pattern(&pb_graph_node->output_pins[i][j]); - backward_infer_pattern(&pb_graph_node->output_pins[i][j]); - } - } - } - - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - hasPattern = FALSE; - for (k = 0; k < pb_graph_node->clock_pins[i][j].num_output_edges; k++) { - /* Xifan Tang: bypass pack_patterns whose parent mode is disabled_in_packing*/ - /* - if (TRUE == pb_graph_node->clock_pins[i][j].output_edges[k]->interconnect->parent_mode->disabled_in_packing) { - continue; - } - */ - /* END */ - for (m = 0; m < pb_graph_node->clock_pins[i][j].output_edges[k]->num_pack_patterns; m++) { - hasPattern = TRUE; - index = add_pattern_name_to_hash(nhash, - pb_graph_node->clock_pins[i][j].output_edges[k]->pack_pattern_names[m], - ncount); - if (pb_graph_node->clock_pins[i][j].output_edges[k]->pack_pattern_indices == NULL) { - pb_graph_node->clock_pins[i][j].output_edges[k]->pack_pattern_indices = (int*) my_malloc(pb_graph_node->clock_pins[i][j].output_edges[k]->num_pack_patterns * sizeof(int)); - } - pb_graph_node->clock_pins[i][j].output_edges[k]->pack_pattern_indices[m] = index; - } - } - if (hasPattern == TRUE) { - forward_infer_pattern(&pb_graph_node->clock_pins[i][j]); - backward_infer_pattern(&pb_graph_node->clock_pins[i][j]); - } - } - } - - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) { - for (k = 0; k < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; k++) { - discover_pattern_names_in_pb_graph_node(&pb_graph_node->child_pb_graph_nodes[i][j][k], nhash, ncount); - } - } - } -} - -/** - * In obvious cases where a pattern edge has only one path to go, set that path to be inferred - */ -static void forward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin) { - if (pb_graph_pin->num_output_edges == 1 && pb_graph_pin->output_edges[0]->num_pack_patterns == 0 && pb_graph_pin->output_edges[0]->infer_pattern == FALSE) { - pb_graph_pin->output_edges[0]->infer_pattern = TRUE; - if (pb_graph_pin->output_edges[0]->num_output_pins == 1) { - forward_infer_pattern(pb_graph_pin->output_edges[0]->output_pins[0]); - } - } -} -static void backward_infer_pattern(INOUTP t_pb_graph_pin *pb_graph_pin) { - if (pb_graph_pin->num_input_edges == 1 && pb_graph_pin->input_edges[0]->num_pack_patterns == 0 && pb_graph_pin->input_edges[0]->infer_pattern == FALSE) { - pb_graph_pin->input_edges[0]->infer_pattern = TRUE; - if (pb_graph_pin->input_edges[0]->num_input_pins == 1) { - backward_infer_pattern(pb_graph_pin->input_edges[0]->input_pins[0]); - } - } -} - -/** - * Allocates memory for models and loads the name of the packing pattern so that it can be identified and loaded with - * more complete information later - */ -static t_pack_patterns *alloc_and_init_pattern_list_from_hash(INP int ncount, - INOUTP struct s_hash **nhash) { - t_pack_patterns *nlist; - struct s_hash_iterator hash_iter; - struct s_hash *curr_pattern; - - nlist = (t_pack_patterns*)my_calloc(ncount, sizeof(t_pack_patterns)); - - hash_iter = start_hash_table_iterator(); - curr_pattern = get_next_hash(nhash, &hash_iter); - while (curr_pattern != NULL) { - assert(nlist[curr_pattern->index].name == NULL); - nlist[curr_pattern->index].name = my_strdup(curr_pattern->name); - nlist[curr_pattern->index].root_block = NULL; - nlist[curr_pattern->index].is_chain = FALSE; - nlist[curr_pattern->index].index = curr_pattern->index; - curr_pattern = get_next_hash(nhash, &hash_iter); - } - return nlist; -} - -void free_list_of_pack_patterns(INP t_pack_patterns *list_of_pack_patterns, INP int num_packing_patterns) { - int i, j, num_pack_pattern_blocks; - t_pack_pattern_block **pattern_block_list; - if (list_of_pack_patterns != NULL) { - for (i = 0; i < num_packing_patterns; i++) { - num_pack_pattern_blocks = list_of_pack_patterns[i].num_blocks; - pattern_block_list = (t_pack_pattern_block **)my_calloc(num_pack_pattern_blocks, sizeof(t_pack_pattern_block *)); - free(list_of_pack_patterns[i].name); - free(list_of_pack_patterns[i].is_block_optional); - free_pack_pattern(list_of_pack_patterns[i].root_block, pattern_block_list); - for (j = 0; j < num_pack_pattern_blocks; j++) { - free(pattern_block_list[j]); - } - free(pattern_block_list); - } - free(list_of_pack_patterns); - } -} - -/** - * Locate first edge that belongs to pattern index - */ -static t_pb_graph_edge * find_expansion_edge_of_pattern(INP int pattern_index, - INP t_pb_graph_node *pb_graph_node) { - int i, j, k, m; - t_pb_graph_edge * edge; - /* Iterate over all edges to discover if an edge in current physical block belongs to a pattern - If edge does, then return that edge - */ - - if (pb_graph_node == NULL) { - return NULL; - } - - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - for (k = 0; k < pb_graph_node->input_pins[i][j].num_output_edges; k++) { - for (m = 0; m < pb_graph_node->input_pins[i][j].output_edges[k]->num_pack_patterns; m++) { - if (pb_graph_node->input_pins[i][j].output_edges[k]->pack_pattern_indices[m] == pattern_index) { - return pb_graph_node->input_pins[i][j].output_edges[k]; - } - } - } - } - } - - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - for (k = 0; k < pb_graph_node->output_pins[i][j].num_output_edges; k++) { - for (m = 0; m < pb_graph_node->output_pins[i][j].output_edges[k]->num_pack_patterns; m++) { - if (pb_graph_node->output_pins[i][j].output_edges[k]->pack_pattern_indices[m] == pattern_index) { - return pb_graph_node->output_pins[i][j].output_edges[k]; - } - } - } - } - } - - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - for (k = 0; k < pb_graph_node->clock_pins[i][j].num_output_edges; k++) { - for (m = 0; m < pb_graph_node->clock_pins[i][j].output_edges[k]->num_pack_patterns; m++) { - if (pb_graph_node->clock_pins[i][j].output_edges[k]->pack_pattern_indices[m] == pattern_index) { - return pb_graph_node->clock_pins[i][j].output_edges[k]; - } - } - } - } - } - /* Xifan TANG's note: Go recursively downto the children pb_graph_node*/ - for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) { - for (j = 0; j < pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) { - for (k = 0; k < pb_graph_node->pb_type->modes[i].pb_type_children[j].num_pb; k++) { - edge = find_expansion_edge_of_pattern(pattern_index, &pb_graph_node->child_pb_graph_nodes[i][j][k]); - if (edge != NULL) { - return edge; - } - } - } - } - return NULL; -} - -/** - * Find if receiver of edge is in the same pattern, if yes, add to pattern - * Convention: Connections are made on backward expansion only (to make future multi-fanout support easier) so this function will not update connections - */ -static void forward_expand_pack_pattern_from_edge( - INP t_pb_graph_edge* expansion_edge, - INOUTP t_pack_patterns *list_of_packing_patterns, - INP int curr_pattern_index, INP int *L_num_blocks, INOUTP boolean make_root_of_chain) { - int i, j, k; - int iport, ipin, iedge; - boolean found; /* Error checking, ensure only one fan-out for each pattern net */ - t_pack_pattern_block *destination_block = NULL; - t_pb_graph_node *destination_pb_graph_node = NULL; - - found = expansion_edge->infer_pattern; - for (i = 0; !found && i < expansion_edge->num_pack_patterns; i++) { - if (expansion_edge->pack_pattern_indices[i] == curr_pattern_index) { - found = TRUE; - } - } - if (!found) { - return; - } - - found = FALSE; - for (i = 0; i < expansion_edge->num_output_pins; i++) { - if (expansion_edge->output_pins[i]->parent_node->pb_type->num_modes == 0) { - destination_pb_graph_node = expansion_edge->output_pins[i]->parent_node; - assert(found == FALSE); - /* Check assumption that each forced net has only one fan-out */ - /* This is the destination node */ - found = TRUE; - - /* If this pb_graph_node is part not of the current pattern index, put it in and expand all its edges */ - if (destination_pb_graph_node->temp_scratch_pad == NULL - || ((t_pack_pattern_block*) destination_pb_graph_node->temp_scratch_pad)->pattern_index != curr_pattern_index) { - destination_block = (t_pack_pattern_block*)my_calloc(1, sizeof(t_pack_pattern_block)); - list_of_packing_patterns[curr_pattern_index].base_cost += compute_primitive_base_cost(destination_pb_graph_node); - destination_block->block_id = *L_num_blocks; - (*L_num_blocks)++; - destination_pb_graph_node->temp_scratch_pad = (void *) destination_block; - destination_block->pattern_index = curr_pattern_index; - destination_block->pb_type = destination_pb_graph_node->pb_type; - for (iport = 0; iport < destination_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < destination_pb_graph_node->num_input_pins[iport]; ipin++) { - for (iedge = 0; iedge < destination_pb_graph_node->input_pins[iport][ipin].num_input_edges; iedge++) { - backward_expand_pack_pattern_from_edge( - destination_pb_graph_node->input_pins[iport][ipin].input_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, - &destination_pb_graph_node->input_pins[iport][ipin], - destination_block, L_num_blocks); - } - } - } - for (iport = 0; iport < destination_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < destination_pb_graph_node->num_output_pins[iport]; ipin++) { - for (iedge = 0; iedge < destination_pb_graph_node->output_pins[iport][ipin].num_output_edges; iedge++) { - forward_expand_pack_pattern_from_edge( - destination_pb_graph_node->output_pins[iport][ipin].output_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, L_num_blocks, FALSE); - } - } - } - for (iport = 0; iport < destination_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0;ipin < destination_pb_graph_node->num_clock_pins[iport]; ipin++) { - for (iedge = 0; iedge < destination_pb_graph_node->clock_pins[iport][ipin].num_input_edges; iedge++) { - backward_expand_pack_pattern_from_edge( - destination_pb_graph_node->clock_pins[iport][ipin].input_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, - &destination_pb_graph_node->clock_pins[iport][ipin], - destination_block, L_num_blocks); - } - } - } - } - if (((t_pack_pattern_block*) destination_pb_graph_node->temp_scratch_pad)->pattern_index == curr_pattern_index) { - if(make_root_of_chain == TRUE) { - list_of_packing_patterns[curr_pattern_index].chain_root_pin = expansion_edge->output_pins[i]; - list_of_packing_patterns[curr_pattern_index].root_block = destination_block; - } - } - } else { - for (j = 0; j < expansion_edge->output_pins[i]->num_output_edges; j++) { - if (expansion_edge->output_pins[i]->output_edges[j]->infer_pattern == TRUE) { - forward_expand_pack_pattern_from_edge( - expansion_edge->output_pins[i]->output_edges[j], - list_of_packing_patterns, curr_pattern_index, - L_num_blocks, make_root_of_chain); - } else { - for (k = 0; k < expansion_edge->output_pins[i]->output_edges[j]->num_pack_patterns; k++) { - if (expansion_edge->output_pins[i]->output_edges[j]->pack_pattern_indices[k] == curr_pattern_index) { - if (found == FALSE) { - assert(found == FALSE); - } - /* Check assumption that each forced net has only one fan-out */ - found = TRUE; - forward_expand_pack_pattern_from_edge( - expansion_edge->output_pins[i]->output_edges[j], - list_of_packing_patterns, - curr_pattern_index, L_num_blocks, make_root_of_chain); - } - } - } - } - } - } - -} - -/** - * Find if driver of edge is in the same pattern, if yes, add to pattern - * Convention: Connections are made on backward expansion only (to make future multi-fanout support easier) so this function must update both source and destination blocks - */ -static void backward_expand_pack_pattern_from_edge( - INP t_pb_graph_edge* expansion_edge, - INOUTP t_pack_patterns *list_of_packing_patterns, - INP int curr_pattern_index, INP t_pb_graph_pin *destination_pin, - INP t_pack_pattern_block *destination_block, INP int *L_num_blocks) { - int i, j, k; - int iport, ipin, iedge; - boolean found; /* Error checking, ensure only one fan-out for each pattern net */ - t_pack_pattern_block *source_block = NULL; - t_pb_graph_node *source_pb_graph_node = NULL; - t_pack_pattern_connections *pack_pattern_connection = NULL; - - found = expansion_edge->infer_pattern; - for (i = 0; !found && i < expansion_edge->num_pack_patterns; i++) { - if (expansion_edge->pack_pattern_indices[i] == curr_pattern_index) { - found = TRUE; - } - } - if (!found) { - return; - } - - found = FALSE; - for (i = 0; i < expansion_edge->num_input_pins; i++) { - if (expansion_edge->input_pins[i]->parent_node->pb_type->num_modes == 0) { - source_pb_graph_node = expansion_edge->input_pins[i]->parent_node; - assert(found == FALSE); - /* Check assumption that each forced net has only one fan-out */ - /* This is the source node for destination */ - found = TRUE; - - /* If this pb_graph_node is part not of the current pattern index, put it in and expand all its edges */ - source_block = (t_pack_pattern_block*) source_pb_graph_node->temp_scratch_pad; - if (source_block == NULL - || source_block->pattern_index != curr_pattern_index) { - source_block = (t_pack_pattern_block *)my_calloc(1, sizeof(t_pack_pattern_block)); - source_block->block_id = *L_num_blocks; - (*L_num_blocks)++; - list_of_packing_patterns[curr_pattern_index].base_cost += compute_primitive_base_cost(source_pb_graph_node); - source_pb_graph_node->temp_scratch_pad = (void *) source_block; - source_block->pattern_index = curr_pattern_index; - source_block->pb_type = source_pb_graph_node->pb_type; - - if (list_of_packing_patterns[curr_pattern_index].root_block == NULL) { - list_of_packing_patterns[curr_pattern_index].root_block = source_block; - } - - for (iport = 0; iport < source_pb_graph_node->num_input_ports; iport++) { - for (ipin = 0; ipin < source_pb_graph_node->num_input_pins[iport]; ipin++) { - for (iedge = 0; iedge < source_pb_graph_node->input_pins[iport][ipin].num_input_edges; iedge++) { - backward_expand_pack_pattern_from_edge( - source_pb_graph_node->input_pins[iport][ipin].input_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, - &source_pb_graph_node->input_pins[iport][ipin], - source_block, L_num_blocks); - } - } - } - for (iport = 0; iport < source_pb_graph_node->num_output_ports; iport++) { - for (ipin = 0; ipin < source_pb_graph_node->num_output_pins[iport]; ipin++) { - for (iedge = 0; iedge < source_pb_graph_node->output_pins[iport][ipin].num_output_edges; iedge++) { - forward_expand_pack_pattern_from_edge( - source_pb_graph_node->output_pins[iport][ipin].output_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, L_num_blocks, FALSE); - } - } - } - for (iport = 0; iport < source_pb_graph_node->num_clock_ports; iport++) { - for (ipin = 0; ipin < source_pb_graph_node->num_clock_pins[iport]; ipin++) { - for (iedge = 0; iedge < source_pb_graph_node->clock_pins[iport][ipin].num_input_edges; iedge++) { - backward_expand_pack_pattern_from_edge( - source_pb_graph_node->clock_pins[iport][ipin].input_edges[iedge], - list_of_packing_patterns, - curr_pattern_index, - &source_pb_graph_node->clock_pins[iport][ipin], - source_block, L_num_blocks); - } - } - } - } - if (destination_pin != NULL) { - assert(((t_pack_pattern_block*)source_pb_graph_node->temp_scratch_pad)->pattern_index == curr_pattern_index); - source_block = (t_pack_pattern_block*) source_pb_graph_node->temp_scratch_pad; - pack_pattern_connection = (t_pack_pattern_connections *)my_calloc(1, sizeof(t_pack_pattern_connections)); - pack_pattern_connection->from_block = source_block; - pack_pattern_connection->from_pin = expansion_edge->input_pins[i]; - pack_pattern_connection->to_block = destination_block; - pack_pattern_connection->to_pin = destination_pin; - pack_pattern_connection->next = source_block->connections; - source_block->connections = pack_pattern_connection; - - pack_pattern_connection = (t_pack_pattern_connections *)my_calloc(1, sizeof(t_pack_pattern_connections)); - pack_pattern_connection->from_block = source_block; - pack_pattern_connection->from_pin = expansion_edge->input_pins[i]; - pack_pattern_connection->to_block = destination_block; - pack_pattern_connection->to_pin = destination_pin; - pack_pattern_connection->next = destination_block->connections; - destination_block->connections = pack_pattern_connection; - - if (source_block == destination_block) { - vpr_printf(TIO_MESSAGE_ERROR, "Invalid packing pattern defined. Source and destination block are the same (%s).\n", - source_block->pb_type->name); - } - } - } else { - if(expansion_edge->input_pins[i]->num_input_edges == 0) { - if(expansion_edge->input_pins[i]->parent_node->pb_type->parent_mode == NULL) { - /* This pack pattern extends to CLB input pin, thus it extends across multiple logic blocks, treat as a chain */ - list_of_packing_patterns[curr_pattern_index].is_chain = TRUE; - forward_expand_pack_pattern_from_edge( - expansion_edge, - list_of_packing_patterns, - curr_pattern_index, L_num_blocks, TRUE); - } - } else { - for (j = 0; j < expansion_edge->input_pins[i]->num_input_edges; j++) { - if (expansion_edge->input_pins[i]->input_edges[j]->infer_pattern == TRUE) { - backward_expand_pack_pattern_from_edge( - expansion_edge->input_pins[i]->input_edges[j], - list_of_packing_patterns, curr_pattern_index, - destination_pin, destination_block, L_num_blocks); - } else { - for (k = 0; k < expansion_edge->input_pins[i]->input_edges[j]->num_pack_patterns; k++) { - if (expansion_edge->input_pins[i]->input_edges[j]->pack_pattern_indices[k] == curr_pattern_index) { - if (found == FALSE) { - assert(found == FALSE); - } - /* Check assumption that each forced net has only one fan-out */ - found = TRUE; - backward_expand_pack_pattern_from_edge( - expansion_edge->input_pins[i]->input_edges[j], - list_of_packing_patterns, - curr_pattern_index, destination_pin, - destination_block, L_num_blocks); - } - } - } - } - } - } - } -} - -/** - * Pre-pack atoms in netlist to molecules - * 1. Single atoms are by definition a molecule. - * 2. Forced pack molecules are groupings of atoms that matches a t_pack_pattern definition. - * 3. Chained molecules are molecules that follow a carry-chain style pattern: ie. a single linear chain that can be split across multiple complex blocks - */ -t_pack_molecule *alloc_and_load_pack_molecules( - INP t_pack_patterns *list_of_pack_patterns, - INP int num_packing_patterns, OUTP int *num_pack_molecule) { - int i, j, best_pattern; - t_pack_molecule *list_of_molecules_head; - t_pack_molecule *cur_molecule; - boolean *is_used; - - is_used = (boolean*)my_calloc(num_packing_patterns, sizeof(boolean)); - - /* Xifan Tang: initialize the pattern usage ! Mark used for patterns that belongs to modes disabled_in_packing*/ - for (i = 0; i < num_packing_patterns; i++) { - if (TRUE == list_of_pack_patterns[i].root_block->pb_type->parent_mode->disabled_in_packing) { - is_used[i] = TRUE; - } - } - /* END */ - - cur_molecule = list_of_molecules_head = NULL; - - /* Find forced pack patterns */ - /* Simplifying assumptions: Each atom can map to at most one molecule, use first-fit mapping based on priority of pattern */ - /* TODO: Need to investigate better mapping strategies than first-fit */ - for (i = 0; i < num_packing_patterns; i++) { - best_pattern = 0; - for(j = 1; j < num_packing_patterns; j++) { - if(is_used[best_pattern]) { - best_pattern = j; - } else if (is_used[j] == FALSE && compare_pack_pattern(&list_of_pack_patterns[j], &list_of_pack_patterns[best_pattern]) == 1) { - best_pattern = j; - } - } - /* Xifan Tang: we may not found an usused pattern */ - if (TRUE == is_used[best_pattern]) { - continue; - } - /* END */ - assert(is_used[best_pattern] == FALSE); - is_used[best_pattern] = TRUE; - for (j = 0; j < num_logical_blocks; j++) { - cur_molecule = try_create_molecule(list_of_pack_patterns, best_pattern, j); - if (cur_molecule != NULL) { - cur_molecule->next = list_of_molecules_head; - /* In the event of multiple molecules with the same logical block pattern, bias to use the molecule with less costly physical resources first */ - /* TODO: Need to normalize magical number 100 */ - cur_molecule->base_gain = cur_molecule->num_blocks - (cur_molecule->pack_pattern->base_cost / 100); - list_of_molecules_head = cur_molecule; - if(logical_block[j].packed_molecules == NULL || logical_block[j].packed_molecules->data_vptr != cur_molecule) { - /* molecule did not cover current atom (possibly because molecule created is part of a long chain that extends past multiple logic blocks), try again */ - j--; - } - } - } - } - free(is_used); - - /* List all logical blocks as a molecule for blocks that do not belong to any molecules. - This allows the packer to be consistent as it now packs molecules only instead of atoms and molecules - - If a block belongs to a molecule, then carrying the single atoms around can make the packing problem - more difficult because now it needs to consider splitting molecules. - */ - for (i = 0; i < num_logical_blocks; i++) { - logical_block[i].expected_lowest_cost_primitive = get_expected_lowest_cost_primitive_for_logical_block(i); - if (logical_block[i].packed_molecules == NULL) { - cur_molecule = (t_pack_molecule*) my_calloc(1, - sizeof(t_pack_molecule)); - cur_molecule->valid = TRUE; - cur_molecule->type = MOLECULE_SINGLE_ATOM; - cur_molecule->num_blocks = 1; - cur_molecule->root = 0; - cur_molecule->num_ext_inputs = logical_block[i].used_input_pins; - cur_molecule->chain_pattern = NULL; - cur_molecule->pack_pattern = NULL; - cur_molecule->logical_block_ptrs = (t_logical_block**) my_malloc(1 * sizeof(t_logical_block*)); - cur_molecule->logical_block_ptrs[0] = &logical_block[i]; - cur_molecule->next = list_of_molecules_head; - cur_molecule->base_gain = 1; - list_of_molecules_head = cur_molecule; - - logical_block[i].packed_molecules = (struct s_linked_vptr*) my_calloc(1, - sizeof(struct s_linked_vptr)); - logical_block[i].packed_molecules->data_vptr = (void*) cur_molecule; - } - } - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS)) { - print_pack_molecules(getEchoFileName(E_ECHO_PRE_PACKING_MOLECULES_AND_PATTERNS), - list_of_pack_patterns, num_packing_patterns, - list_of_molecules_head); - } - - return list_of_molecules_head; -} - - -static void free_pack_pattern(INOUTP t_pack_pattern_block *pattern_block, INOUTP t_pack_pattern_block **pattern_block_list) { - t_pack_pattern_connections *connection, *next; - if (pattern_block->block_id == OPEN) { - /* already traversed, return */ - return; - } - pattern_block_list[pattern_block->block_id] = pattern_block; - pattern_block->block_id = OPEN; - connection = pattern_block->connections; - while (connection) { - free_pack_pattern(connection->from_block, pattern_block_list); - free_pack_pattern(connection->to_block, pattern_block_list); - next = connection->next; - free(connection); - connection = next; - } -} - -/** - * Given a pattern and a logical block to serve as the root block, determine if the candidate logical block serving as the root node matches the pattern - * If yes, return the molecule with this logical block as the root, if not, return NULL - * Limitations: Currently assumes that forced pack nets must be single-fanout as this covers all the reasonable architectures we wanted - More complicated structures should probably be handled either downstream (general packing) or upstream (in tech mapping) - * If this limitation is too constraining, code is designed so that this limitation can be removed - * Side Effect: If successful, link atom to molecule - */ -static t_pack_molecule *try_create_molecule( - INP t_pack_patterns *list_of_pack_patterns, INP int pack_pattern_index, - INP int block_index) { - int i; - t_pack_molecule *molecule; - struct s_linked_vptr *molecule_linked_list; - - molecule = (t_pack_molecule*)my_calloc(1, sizeof(t_pack_molecule)); - molecule->valid = TRUE; - molecule->type = MOLECULE_FORCED_PACK; - molecule->pack_pattern = &list_of_pack_patterns[pack_pattern_index]; - molecule->logical_block_ptrs = (t_logical_block **)my_calloc(molecule->pack_pattern->num_blocks, - sizeof(t_logical_block *)); - molecule->num_blocks = list_of_pack_patterns[pack_pattern_index].num_blocks; - molecule->root = list_of_pack_patterns[pack_pattern_index].root_block->block_id; - molecule->num_ext_inputs = 0; - - if(list_of_pack_patterns[pack_pattern_index].is_chain == TRUE) { - /* A chain pattern extends beyond a single logic block so we must find the block_index that matches with the portion of a chain for this particular logic block */ - block_index = find_new_root_atom_for_chain(block_index, &list_of_pack_patterns[pack_pattern_index]); - } - - if (block_index != OPEN && try_expand_molecule(molecule, block_index, molecule->pack_pattern->root_block) == TRUE) { - /* Success! commit module */ - for (i = 0; i < molecule->pack_pattern->num_blocks; i++) { - if(molecule->logical_block_ptrs[i] == NULL) { - assert(list_of_pack_patterns[pack_pattern_index].is_block_optional[i] == TRUE); - continue; - } - molecule_linked_list = (struct s_linked_vptr*) my_calloc(1, sizeof(struct s_linked_vptr)); - molecule_linked_list->data_vptr = (void *) molecule; - molecule_linked_list->next = molecule->logical_block_ptrs[i]->packed_molecules; - molecule->logical_block_ptrs[i]->packed_molecules = molecule_linked_list; - } - } else { - /* Does not match pattern, free molecule */ - free(molecule->logical_block_ptrs); - free(molecule); - molecule = NULL; - } - - return molecule; -} - -/** - * Determine if logical block can match with the pattern to form a molecule - * return TRUE if it matches, return FALSE otherwise - */ -static boolean try_expand_molecule(INOUTP t_pack_molecule *molecule, - INP int logical_block_index, - INP t_pack_pattern_block *current_pattern_block) { - int iport, ipin, inet; - boolean success; - boolean is_optional; - boolean *is_block_optional; - t_pack_pattern_connections *cur_pack_pattern_connection; - is_block_optional = molecule->pack_pattern->is_block_optional; - is_optional = is_block_optional[current_pattern_block->block_id]; - - /* If the block in the pattern has already been visited, then there is no need to revisit it */ - if (molecule->logical_block_ptrs[current_pattern_block->block_id] != NULL) { - if (molecule->logical_block_ptrs[current_pattern_block->block_id] - != &logical_block[logical_block_index]) { - /* Mismatch between the visited block and the current block implies that the current netlist structure does not match the expected pattern, return whether or not this matters */ - return is_optional; - } else { - molecule->num_ext_inputs--; /* This block is revisited, implies net is entirely internal to molecule, reduce count */ - return TRUE; - } - } - - /* This node has never been visited */ - /* Simplifying assumption: An atom can only map to one molecule */ - if(logical_block[logical_block_index].packed_molecules != NULL) { - /* This block is already in a molecule, return whether or not this matters */ - return is_optional; - } - - if (primitive_type_feasible(logical_block_index, - current_pattern_block->pb_type)) { - - success = TRUE; - /* If the primitive types match, store it, expand it and explore neighbouring nodes */ - molecule->logical_block_ptrs[current_pattern_block->block_id] = - &logical_block[logical_block_index]; /* store that this node has been visited */ - molecule->num_ext_inputs += - logical_block[logical_block_index].used_input_pins; - - cur_pack_pattern_connection = current_pattern_block->connections; - while (cur_pack_pattern_connection != NULL && success == TRUE) { - if (cur_pack_pattern_connection->from_block - == current_pattern_block) { - /* find net corresponding to pattern */ - iport = - cur_pack_pattern_connection->from_pin->port->model_port->index; - ipin = cur_pack_pattern_connection->from_pin->pin_number; - inet = - logical_block[logical_block_index].output_nets[iport][ipin]; - - /* Check if net is valid */ - if (inet == OPEN || vpack_net[inet].num_sinks != 1) { /* One fanout assumption */ - success = is_block_optional[cur_pack_pattern_connection->to_block->block_id]; - } else { - success = try_expand_molecule(molecule, - vpack_net[inet].node_block[1], - cur_pack_pattern_connection->to_block); - } - } else { - assert( - cur_pack_pattern_connection->to_block == current_pattern_block); - /* find net corresponding to pattern */ - iport = - cur_pack_pattern_connection->to_pin->port->model_port->index; - ipin = cur_pack_pattern_connection->to_pin->pin_number; - if (cur_pack_pattern_connection->to_pin->port->model_port->is_clock) { - inet = logical_block[logical_block_index].clock_net; - } else { - inet = - logical_block[logical_block_index].input_nets[iport][ipin]; - } - /* Check if net is valid */ - if (inet == OPEN || vpack_net[inet].num_sinks != 1) { /* One fanout assumption */ - success = is_block_optional[cur_pack_pattern_connection->from_block->block_id]; - } else { - success = try_expand_molecule(molecule, - vpack_net[inet].node_block[0], - cur_pack_pattern_connection->from_block); - } - } - cur_pack_pattern_connection = cur_pack_pattern_connection->next; - } - } else { - success = is_optional; - } - - return success; -} - -static void print_pack_molecules(INP const char *fname, - INP t_pack_patterns *list_of_pack_patterns, INP int num_pack_patterns, - INP t_pack_molecule *list_of_molecules) { - int i; - FILE *fp; - t_pack_molecule *list_of_molecules_current; - - fp = my_fopen(fname, "w", 0); - fprintf(fp, "# of pack patterns %d\n", num_pack_patterns); - - for (i = 0; i < num_pack_patterns; i++) { - fprintf(fp, "pack pattern index %d block count %d name %s root %s\n", - list_of_pack_patterns[i].index, - list_of_pack_patterns[i].num_blocks, - list_of_pack_patterns[i].name, - list_of_pack_patterns[i].root_block->pb_type->name); - } - - list_of_molecules_current = list_of_molecules; - while (list_of_molecules_current != NULL) { - if (list_of_molecules_current->type == MOLECULE_SINGLE_ATOM) { - fprintf(fp, "\nmolecule type: atom\n"); - fprintf(fp, "\tpattern index %d: logical block [%d] name %s\n", i, - list_of_molecules_current->logical_block_ptrs[0]->index, - list_of_molecules_current->logical_block_ptrs[0]->name); - } else if (list_of_molecules_current->type == MOLECULE_FORCED_PACK) { - fprintf(fp, "\nmolecule type: %s\n", - list_of_molecules_current->pack_pattern->name); - for (i = 0; i < list_of_molecules_current->pack_pattern->num_blocks; - i++) { - if(list_of_molecules_current->logical_block_ptrs[i] == NULL) { - fprintf(fp, "\tpattern index %d: empty \n", i); - } else { - fprintf(fp, "\tpattern index %d: logical block [%d] name %s", - i, - list_of_molecules_current->logical_block_ptrs[i]->index, - list_of_molecules_current->logical_block_ptrs[i]->name); - if(list_of_molecules_current->pack_pattern->root_block->block_id == i) { - fprintf(fp, " root node\n"); - } else { - fprintf(fp, "\n"); - } - } - } - } else { - assert(0); - } - list_of_molecules_current = list_of_molecules_current->next; - } - - fclose(fp); -} - -/* Search through all primitives and return the lowest cost primitive that fits this logical block */ -static t_pb_graph_node *get_expected_lowest_cost_primitive_for_logical_block(INP int ilogical_block) { - int i; - float cost, best_cost; - t_pb_graph_node *current, *best; - - best_cost = UNDEFINED; - best = NULL; - current = NULL; - for(i = 0; i < num_types; i++) { - cost = UNDEFINED; - current = get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node(ilogical_block, type_descriptors[i].pb_graph_head, &cost); - if(cost != UNDEFINED) { - if(best_cost == UNDEFINED || best_cost > cost) { - best_cost = cost; - best = current; - } - } - } - return best; -} - -static t_pb_graph_node *get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node(INP int ilogical_block, INP t_pb_graph_node *curr_pb_graph_node, OUTP float *cost) { - t_pb_graph_node *best, *cur; - float cur_cost, best_cost; - int i, j; - - best = NULL; - best_cost = UNDEFINED; - if(curr_pb_graph_node == NULL) { - return NULL; - } - - if(curr_pb_graph_node->pb_type->blif_model != NULL) { - if(primitive_type_feasible(ilogical_block, curr_pb_graph_node->pb_type)) { - cur_cost = compute_primitive_base_cost(curr_pb_graph_node); - if(best_cost == UNDEFINED || best_cost > cur_cost) { - best_cost = cur_cost; - best = curr_pb_graph_node; - } - } - } else { - for(i = 0; i < curr_pb_graph_node->pb_type->num_modes; i++) { - for(j = 0; j < curr_pb_graph_node->pb_type->modes[i].num_pb_type_children; j++) { - *cost = UNDEFINED; - cur = get_expected_lowest_cost_primitive_for_logical_block_in_pb_graph_node(ilogical_block, &curr_pb_graph_node->child_pb_graph_nodes[i][j][0], cost); - if(cur != NULL) { - if(best == NULL || best_cost > *cost) { - best = cur; - best_cost = *cost; - } - } - } - } - } - - *cost = best_cost; - return best; -} - - -/* Determine which of two pack pattern should take priority */ -static int compare_pack_pattern(const t_pack_patterns *pattern_a, const t_pack_patterns *pattern_b) { - float base_gain_a, base_gain_b, diff; - - /* Bigger patterns should take higher priority than smaller patterns because they are harder to fit */ - if (pattern_a->num_blocks > pattern_b->num_blocks) { - return 1; - } else if (pattern_a->num_blocks < pattern_b->num_blocks) { - return -1; - } - - base_gain_a = pattern_a->base_cost; - base_gain_b = pattern_b->base_cost; - diff = base_gain_a - base_gain_b; - - /* Less costly patterns should be used before more costly patterns */ - if (diff < 0) { - return 1; - } - if (diff > 0) { - return -1; - } - return 0; -} - -/* A chain can extend across multiple logic blocks. Must segment the chain to fit in a logic block by identifying the actual atom that forms the root of the new chain. - * Returns OPEN if this block_index doesn't match up with any chain - * - * Assumes that the root of a chain is the primitive that starts the chain or is driven from outside the logic block - * block_index: index of current atom - * list_of_pack_pattern: ptr to current chain pattern - */ -static int find_new_root_atom_for_chain(INP int block_index, INP t_pack_patterns *list_of_pack_pattern) { - int new_index = OPEN; - t_pb_graph_pin *root_ipin; - t_pb_graph_node *root_pb_graph_node; - t_model_ports *model_port; - int driver_net, driver_block; - - assert(list_of_pack_pattern->is_chain == TRUE); - root_ipin = list_of_pack_pattern->chain_root_pin; - root_pb_graph_node = root_ipin->parent_node; - - if(primitive_type_feasible(block_index, root_pb_graph_node->pb_type) == FALSE) { - return OPEN; - } - - /* Xifan TANG: this is trying to find the root logical_block which is the head of a carry chain */ - /* Assign driver furthest up the chain that matches the root node and is unassigned to a molecule as the root */ - model_port = root_ipin->port->model_port; - driver_net = logical_block[block_index].input_nets[model_port->index][root_ipin->pin_number]; - if(driver_net == OPEN) { - /* The current block is the furthest up the chain, return it */ - return block_index; - } - - /* Xifan TANG: this is trying to find a possible starting logical block, whose preceding block is already assigned - * to another molecule - */ - driver_block = vpack_net[driver_net].node_block[0]; - if(logical_block[driver_block].packed_molecules != NULL) { - /* Driver is used/invalid, so current block is the furthest up the chain, return it */ - return block_index; - } - - new_index = find_new_root_atom_for_chain(driver_block, list_of_pack_pattern); - if(new_index == OPEN) { - return block_index; - } else { - return new_index; - } -} - - - diff --git a/vpr7_x2p/vpr/SRC/pack/prepack.h b/vpr7_x2p/vpr/SRC/pack/prepack.h deleted file mode 100644 index bcb0d06c8..000000000 --- a/vpr7_x2p/vpr/SRC/pack/prepack.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - Prepacking: Group together technology-mapped netlist blocks before packing. This gives hints to the packer on what groups of blocks to keep together during packing. - Primary use 1) "Forced" packs (eg LUT+FF pair) - 2) Carry-chains - */ - -#ifndef PREPACK_H -#define PREPACK_H -#include "arch_types.h" -#include "util.h" - -t_pack_patterns *alloc_and_load_pack_patterns(OUTP int *num_packing_patterns); -void free_list_of_pack_patterns(INP t_pack_patterns *list_of_pack_patterns, INP int num_packing_patterns); - -t_pack_molecule *alloc_and_load_pack_molecules( - INP t_pack_patterns *list_of_pack_patterns, - INP int num_packing_patterns, OUTP int *num_pack_molecule); - -#endif diff --git a/vpr7_x2p/vpr/SRC/pack/print_netlist.c b/vpr7_x2p/vpr/SRC/pack/print_netlist.c deleted file mode 100644 index 2ce39550e..000000000 --- a/vpr7_x2p/vpr/SRC/pack/print_netlist.c +++ /dev/null @@ -1,103 +0,0 @@ -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "print_netlist.h" -#include "read_xml_arch_file.h" - -/******************** Subroutines local to this module ***********************/ - -static void print_pinnum(FILE * fp, int pinnum); - -/********************* Subroutine definitions ********************************/ - -void print_netlist(char *foutput, char *net_file) { - - /* Prints out the netlist related data structures into the file * - * fname. */ - - int i, j, max_pin; - int num_global_nets; - int L_num_p_inputs, L_num_p_outputs; - FILE *fp; - - num_global_nets = 0; - L_num_p_inputs = 0; - L_num_p_outputs = 0; - - /* Count number of global nets */ - for (i = 0; i < num_nets; i++) { - if (clb_net[i].is_global) { - num_global_nets++; - } - } - - /* Count I/O input and output pads */ - for (i = 0; i < num_blocks; i++) { - if (block[i].type == IO_TYPE) { - for (j = 0; j < IO_TYPE->num_pins; j++) { - if (block[i].nets[j] != OPEN) { - if (IO_TYPE->class_inf[IO_TYPE->pin_class[j]].type - == DRIVER) { - L_num_p_inputs++; - } else { - assert( - IO_TYPE-> class_inf[IO_TYPE-> pin_class[j]]. type == RECEIVER); - L_num_p_outputs++; - } - } - } - } - } - - fp = my_fopen(foutput, "w", 0); - - fprintf(fp, "Input netlist file: %s\n", net_file); - fprintf(fp, "L_num_p_inputs: %d, L_num_p_outputs: %d, num_clbs: %d\n", - L_num_p_inputs, L_num_p_outputs, num_blocks); - fprintf(fp, "num_blocks: %d, num_nets: %d, num_globals: %d\n", num_blocks, - num_nets, num_global_nets); - fprintf(fp, "\nNet\tName\t\t#Pins\tDriver\t\tRecvs. (block, pin)\n"); - - for (i = 0; i < num_nets; i++) { - fprintf(fp, "\n%d\t%s\t", i, clb_net[i].name); - if (strlen(clb_net[i].name) < 8) - fprintf(fp, "\t"); /* Name field is 16 chars wide */ - fprintf(fp, "%d", clb_net[i].num_sinks + 1); - for (j = 0; j <= clb_net[i].num_sinks; j++) - fprintf(fp, "\t(%4d,%4d)", clb_net[i].node_block[j], - clb_net[i].node_block_pin[j]); - } - - fprintf(fp, "\nBlock\tName\t\tType\tPin Connections\n\n"); - - for (i = 0; i < num_blocks; i++) { - fprintf(fp, "\n%d\t%s\t", i, block[i].name); - if (strlen(block[i].name) < 8) - fprintf(fp, "\t"); /* Name field is 16 chars wide */ - fprintf(fp, "%s", block[i].type->name); - - max_pin = block[i].type->num_pins; - - for (j = 0; j < max_pin; j++) - print_pinnum(fp, block[i].nets[j]); - } - - fprintf(fp, "\n"); - - /* TODO: Print out pb info */ - - fclose(fp); -} - -static void print_pinnum(FILE * fp, int pinnum) { - - /* This routine prints out either OPEN or the pin number, to file fp. */ - - if (pinnum == OPEN) - fprintf(fp, "\tOPEN"); - else - fprintf(fp, "\t%d", pinnum); -} diff --git a/vpr7_x2p/vpr/SRC/pack/print_netlist.h b/vpr7_x2p/vpr/SRC/pack/print_netlist.h deleted file mode 100644 index 9d42a380b..000000000 --- a/vpr7_x2p/vpr/SRC/pack/print_netlist.h +++ /dev/null @@ -1 +0,0 @@ -void print_netlist(char *foutput, char *net_file); diff --git a/vpr7_x2p/vpr/SRC/place/place.c b/vpr7_x2p/vpr/SRC/place/place.c deleted file mode 100755 index c3f97863e..000000000 --- a/vpr7_x2p/vpr/SRC/place/place.c +++ /dev/null @@ -1,3185 +0,0 @@ -/*#include */ -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "place.h" -#include "read_place.h" -#include "draw.h" -#include "place_and_route.h" -#include "net_delay.h" -#include "path_delay.h" -#include "timing_place_lookup.h" -#include "timing_place.h" -#include "place_stats.h" -#include "read_xml_arch_file.h" -#include "ReadOptions.h" -#include "vpr_utils.h" -#include "place_macro.h" - -/************** Types and defines local to place.c ***************************/ - -/* Cut off for incremental bounding box updates. * - * 4 is fastest -- I checked. */ -/* To turn off incremental bounding box updates, set this to a huge value */ -#define SMALL_NET 4 - -/* This defines the error tolerance for floating points variables used in * - * cost computation. 0.01 means that there is a 1% error tolerance. */ -#define ERROR_TOL .01 - -/* This defines the maximum number of swap attempts before invoking the * - * once-in-a-while placement legality check as well as floating point * - * variables round-offs check. */ -#define MAX_MOVES_BEFORE_RECOMPUTE 50000 - -/* The maximum number of tries when trying to place a carry chain at a * - * random location before trying exhaustive placement - find the fist * - * legal position and place it during initial placement. */ -#define MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY 4 - -/* Flags for the states of the bounding box. * - * Stored as char for memory efficiency. */ -#define NOT_UPDATED_YET 'N' -#define UPDATED_ONCE 'U' -#define GOT_FROM_SCRATCH 'S' - -/* For comp_cost. NORMAL means use the method that generates updateable * - * bounding boxes for speed. CHECK means compute all bounding boxes from * - * scratch using a very simple routine to allow checks of the other * - * costs. */ -enum cost_methods { - NORMAL, CHECK -}; - -/* This is for the placement swap routines. A swap attempt could be * - * rejected, accepted or aborted (due to the limitations placed on the * - * carry chain support at this point). */ -enum swap_result { - REJECTED, ACCEPTED, ABORTED -}; - -#define MAX_INV_TIMING_COST 1.e9 -/* Stops inverse timing cost from going to infinity with very lax timing constraints, -which avoids multiplying by a gigantic inverse_prev_timing_cost when auto-normalizing. -The exact value of this cost has relatively little impact, but should not be -large enough to be on the order of timing costs for normal constraints. */ - -/********************** Data Sturcture Definition ***************************/ -/* Stores the information of the move for a block that is * - * moved during placement * - * block_num: the index of the moved block * - * xold: the x_coord that the block is moved from * - * xnew: the x_coord that the block is moved to * - * yold: the y_coord that the block is moved from * - * xnew: the x_coord that the block is moved to * - */ -typedef struct s_pl_moved_block { - int block_num; - int xold; - int xnew; - int yold; - int ynew; - int zold; - int znew; - int swapped_to_empty; -}t_pl_moved_block; - -/* Stores the list of blocks to be moved in a swap during * - * placement. * - * num_moved_blocks: total number of blocks moved when * - * swapping two blocks. * - * moved blocks: a list of moved blocks data structure with * - * information on the move. * - * [0...num_moved_blocks-1] * - */ -typedef struct s_pl_blocks_to_be_moved { - int num_moved_blocks; - t_pl_moved_block * moved_blocks; -}t_pl_blocks_to_be_moved; - - -/********************** Variables local to place.c ***************************/ - -/* Cost of a net, and a temporary cost of a net used during move assessment. */ -static float *net_cost = NULL, *temp_net_cost = NULL; /* [0..num_nets-1] */ - -/* legal positions for type */ -typedef struct s_legal_pos { - int x; - int y; - int z; -}t_legal_pos; - -static t_legal_pos **legal_pos = NULL; /* [0..num_types-1][0..type_tsize - 1] */ -static int *num_legal_pos = NULL; /* [0..num_legal_pos-1] */ - -/* [0...num_nets-1] * - * A flag array to indicate whether the specific bounding box has been updated * - * in this particular swap or not. If it has been updated before, the code * - * must use the updated data, instead of the out-of-date data passed into the * - * subroutine, particularly used in try_swap(). The value NOT_UPDATED_YET * - * indicates that the net has not been updated before, UPDATED_ONCE indicated * - * that the net has been updated once, if it is going to be updated again, the * - * values from the previous update must be used. GOT_FROM_SCRATCH is only * - * applicable for nets larger than SMALL_NETS and it indicates that the * - * particular bounding box cannot be updated incrementally before, hence the * - * bounding box is got from scratch, so the bounding box would definitely be * - * right, DO NOT update again. * - * [0...num_nets-1] */ -static char * bb_updated_before = NULL; - -/* [0..num_nets-1][1..num_pins-1]. What is the value of the timing */ -/* driven portion of the cost function. These arrays will be set to */ -/* (criticality * delay) for each point to point connection. */ -static float **point_to_point_timing_cost = NULL; -static float **temp_point_to_point_timing_cost = NULL; - -/* [0..num_nets-1][1..num_pins-1]. What is the value of the delay */ -/* for each connection in the circuit */ -static float **point_to_point_delay_cost = NULL; -static float **temp_point_to_point_delay_cost = NULL; - -/* [0..num_blocks-1][0..pins_per_clb-1]. Indicates which pin on the net */ -/* this block corresponds to, this is only required during timing-driven */ -/* placement. It is used to allow us to update individual connections on */ -/* each net */ -static int **net_pin_index = NULL; - -/* [0..num_nets-1]. Store the bounding box coordinates and the number of * - * blocks on each of a net's bounding box (to allow efficient updates), * - * respectively. */ - -static struct s_bb *bb_coords = NULL, *bb_num_on_edges = NULL; - -/* Store the information on the blocks to be moved in a swap during * - * placement, in the form of array of structs instead of struct with * - * arrays for cache effifiency * - */ -static t_pl_blocks_to_be_moved blocks_affected; - -/* The arrays below are used to precompute the inverse of the average * - * number of tracks per channel between [subhigh] and [sublow]. Access * - * them as chan?_place_cost_fac[subhigh][sublow]. They are used to * - * speed up the computation of the cost function that takes the length * - * of the net bounding box in each dimension, divided by the average * - * number of tracks in that direction; for other cost functions they * - * will never be used. * - * [0...ny] [0...nx] */ -static float **chanx_place_cost_fac, **chany_place_cost_fac; - -/* The following arrays are used by the try_swap function for speed. */ -/* [0...num_nets-1] */ -static struct s_bb *ts_bb_coord_new = NULL; -static struct s_bb *ts_bb_edge_new = NULL; -static int *ts_nets_to_update = NULL; - -/* The pl_macros array stores all the carry chains placement macros. * - * [0...num_pl_macros-1] */ -static t_pl_macro * pl_macros = NULL; -static int num_pl_macros; - -/* These file-scoped variables keep track of the number of swaps * - * rejected, accepted or aborted. The total number of swap attempts * - * is the sum of the three number. */ -static int num_swap_rejected = 0; -static int num_swap_accepted = 0; -static int num_swap_aborted = 0; -static int num_ts_called = 0; - -/* Expected crossing counts for nets with different #'s of pins. From * - * ICCAD 94 pp. 690 - 695 (with linear interpolation applied by me). * - * Multiplied to bounding box of a net to better estimate wire length * - * for higher fanout nets. Each entry is the correction factor for the * - * fanout index-1 */ -static const float cross_count[50] = { /* [0..49] */1.0, 1.0, 1.0, 1.0828, 1.1536, 1.2206, 1.2823, 1.3385, 1.3991, 1.4493, 1.4974, - 1.5455, 1.5937, 1.6418, 1.6899, 1.7304, 1.7709, 1.8114, 1.8519, 1.8924, - 1.9288, 1.9652, 2.0015, 2.0379, 2.0743, 2.1061, 2.1379, 2.1698, 2.2016, - 2.2334, 2.2646, 2.2958, 2.3271, 2.3583, 2.3895, 2.4187, 2.4479, 2.4772, - 2.5064, 2.5356, 2.5610, 2.5864, 2.6117, 2.6371, 2.6625, 2.6887, 2.7148, - 2.7410, 2.7671, 2.7933 }; - -/********************* Static subroutines local to place.c *******************/ -#ifdef VERBOSE - static void print_clb_placement(const char *fname); -#endif - -static void alloc_and_load_placement_structs( - float place_cost_exp, float ***old_region_occ_x, - float ***old_region_occ_y, struct s_placer_opts placer_opts, - t_direct_inf *directs, int num_directs); - -static void alloc_and_load_try_swap_structs(); - -static void free_placement_structs( - float **old_region_occ_x, float **old_region_occ_y, - struct s_placer_opts placer_opts); - -static void alloc_and_load_for_fast_cost_update(float place_cost_exp); - -static void free_fast_cost_update(void); - -static void alloc_legal_placements(); -static void load_legal_placements(); - -static void free_legal_placements(); - -static int check_macro_can_be_placed(int imacro, int itype, int x, int y, int z); - -static int try_place_macro(int itype, int ichoice, int imacro, int * free_locations); - -static void initial_placement_pl_macros(int macros_max_num_tries, int * free_locations); - -static void initial_placement_blocks(int * free_locations, enum e_pad_loc_type pad_loc_type); - -static void initial_placement(enum e_pad_loc_type pad_loc_type, - char *pad_loc_file); - -static float comp_bb_cost(enum cost_methods method); - -static int setup_blocks_affected(int b_from, int x_to, int y_to, int z_to); - -static int find_affected_blocks(int b_from, int x_to, int y_to, int z_to); - -static enum swap_result try_swap(float t, float *cost, float *bb_cost, float *timing_cost, - float rlim, float **old_region_occ_x, - float **old_region_occ_y, - enum e_place_algorithm place_algorithm, float timing_tradeoff, - float inverse_prev_bb_cost, float inverse_prev_timing_cost, - float *delay_cost); - -static void check_place(float bb_cost, float timing_cost, - enum e_place_algorithm place_algorithm, - float delay_cost); - -static float starting_t(float *cost_ptr, float *bb_cost_ptr, - float *timing_cost_ptr, float **old_region_occ_x, - float **old_region_occ_y, - struct s_annealing_sched annealing_sched, int max_moves, float rlim, - enum e_place_algorithm place_algorithm, float timing_tradeoff, - float inverse_prev_bb_cost, float inverse_prev_timing_cost, - float *delay_cost_ptr); - -static void update_t(float *t, float std_dev, float rlim, float success_rat, - struct s_annealing_sched annealing_sched); - -static void update_rlim(float *rlim, float success_rat); - -static int exit_crit(float t, float cost, - struct s_annealing_sched annealing_sched); - -static int count_connections(void); - -static double get_std_dev(int n, double sum_x_squared, double av_x); - -static float recompute_bb_cost(void); - -static float comp_td_point_to_point_delay(int inet, int ipin); - -static void update_td_cost(void); - -static void comp_delta_td_cost(float *delta_timing, float *delta_delay); - -static void comp_td_costs(float *timing_cost, float *connection_delay_sum); - -static enum swap_result assess_swap(float delta_c, float t); - -static boolean find_to(int x_from, int y_from, t_type_ptr type, float rlim, int *x_to, int *y_to); - -static void get_non_updateable_bb(int inet, struct s_bb *bb_coord_new); - -static void update_bb(int inet, struct s_bb *bb_coord_new, - struct s_bb *bb_edge_new, int xold, int yold, int xnew, int ynew); - -static int find_affected_nets(int *nets_to_update); - -static float get_net_cost(int inet, struct s_bb *bb_ptr); - -static void get_bb_from_scratch(int inet, struct s_bb *coords, - struct s_bb *num_on_edges); - -static double get_net_wirelength_estimate(int inet, struct s_bb *bbptr); - -static void free_try_swap_arrays(void); - - -/*****************************************************************************/ -/* RESEARCH TODO: Bounding Box and rlim need to be redone for heterogeneous to prevent a QoR penalty */ -void try_place(struct s_placer_opts placer_opts, - struct s_annealing_sched annealing_sched, - t_chan_width_dist chan_width_dist, struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, t_direct_inf *directs, int num_directs) { - - /* Does almost all the work of placing a circuit. Width_fac gives the * - * width of the widest channel. Place_cost_exp says what exponent the * - * width should be taken to when calculating costs. This allows a * - * greater bias for anisotropic architectures. */ - - int tot_iter, inner_iter, success_sum, move_lim, moves_since_cost_recompute, width_fac, - num_connections, inet, ipin, outer_crit_iter_count, inner_crit_iter_count, - inner_recompute_limit, swap_result; - float t, success_rat, rlim, cost, timing_cost, bb_cost, new_bb_cost, new_timing_cost, - delay_cost, new_delay_cost, place_delay_value, inverse_prev_bb_cost, inverse_prev_timing_cost, - oldt, **old_region_occ_x, **old_region_occ_y, **net_delay = NULL, crit_exponent, - first_rlim, final_rlim, inverse_delta_rlim, critical_path_delay = UNDEFINED, - **remember_net_delay_original_ptr; /*used to free net_delay if it is re-assigned */ - double av_cost, av_bb_cost, av_timing_cost, av_delay_cost, sum_of_squares, std_dev; - int total_swap_attempts; - float reject_rate; - float accept_rate; - float abort_rate; - char msg[BUFSIZE]; - t_slack * slacks = NULL; - - /* Allocated here because it goes into timing critical code where each memory allocation is expensive */ - - remember_net_delay_original_ptr = NULL; /*prevents compiler warning */ - - /* init file scope variables */ - num_swap_rejected = 0; - num_swap_accepted = 0; - num_swap_aborted = 0; - num_ts_called = 0; - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE - || placer_opts.enable_timing_computations) { - /*do this before the initial placement to avoid messing up the initial placement */ - slacks = alloc_lookups_and_criticalities(chan_width_dist, router_opts, - det_routing_arch, segment_inf, timing_inf, &net_delay, directs, num_directs); - - remember_net_delay_original_ptr = net_delay; - - /*#define PRINT_LOWER_BOUND */ -#ifdef PRINT_LOWER_BOUND - /*print the crit_path, assuming delay between blocks that are* - *block_dist apart*/ - - if (placer_opts.block_dist <= nx) - place_delay_value = - delta_clb_to_clb[placer_opts.block_dist][0]; - else if (placer_opts.block_dist <= ny) - place_delay_value = - delta_clb_to_clb[0][placer_opts.block_dist]; - else - place_delay_value = delta_clb_to_clb[nx][ny]; - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Lower bound assuming delay of %g\n", place_delay_value); - - load_constant_net_delay(net_delay, place_delay_value); - load_timing_graph_net_delays(net_delay); - do_timing_analysis(slacks, FALSE, FALSE, TRUE); - - if (getEchoEnabled()) { - if(isEchoFileEnabled(E_ECHO_PLACEMENT_CRITICAL_PATH)) - print_critical_path(getEchoFileName(E_ECHO_PLACEMENT_CRITICAL_PATH)); - if(isEchoFileEnabled(E_ECHO_PLACEMENT_LOWER_BOUND_SINK_DELAYS)) - print_sink_delays(getEchoFileName(E_ECHO_PLACEMENT_LOWER_BOUND_SINK_DELAYS)); - if(isEchoFileEnabled(E_ECHO_PLACEMENT_LOGIC_SINK_DELAYS)) - print_sink_delays(getEchoFileName(E_ECHO_PLACEMENT_LOGIC_SINK_DELAYS)); - } - - /*also print sink delays assuming 0 delay between blocks, - * this tells us how much logic delay is on each path */ - - load_constant_net_delay(net_delay, 0); - load_timing_graph_net_delays(net_delay); - do_timing_analysis(slacks, FALSE, FALSE, TRUE); - -#endif - - } - - width_fac = placer_opts.place_chan_width; - - init_chan(width_fac, chan_width_dist); - - alloc_and_load_placement_structs( - placer_opts.place_cost_exp, - &old_region_occ_x, &old_region_occ_y, placer_opts, - directs, num_directs); - - initial_placement(placer_opts.pad_loc_type, placer_opts.pad_loc_file); - init_draw_coords((float) width_fac); - - /* Storing the number of pins on each type of block makes the swap routine * - * slightly more efficient. */ - - /* Gets initial cost and loads bounding boxes. */ - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) { - bb_cost = comp_bb_cost(NORMAL); - - crit_exponent = placer_opts.td_place_exp_first; /*this will be modified when rlim starts to change */ - - num_connections = count_connections(); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "There are %d point to point connections in this circuit.\n", num_connections); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE) { - for (inet = 0; inet < num_nets; inet++) - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) - timing_place_crit[inet][ipin] = 0; /*dummy crit values */ - - comp_td_costs(&timing_cost, &delay_cost); /*first pass gets delay_cost, which is used - * in criticality computations in the next call - * to comp_td_costs. */ - place_delay_value = delay_cost / num_connections; /*used for computing criticalities */ - load_constant_net_delay(net_delay, place_delay_value, clb_net, - num_nets); - - } else - place_delay_value = 0; - - if (placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) { - net_delay = point_to_point_delay_cost; /*this keeps net_delay up to date with * - * *the same values that the placer is using * - * *point_to_point_delay_cost is computed each* - * *time that comp_td_costs is called, and is * - * *also updated after any swap is accepted */ - } - - load_timing_graph_net_delays(net_delay); - do_timing_analysis(slacks, FALSE, FALSE, FALSE); - load_criticalities(slacks, crit_exponent); - if (getEchoEnabled()) { - if(isEchoFileEnabled(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH)) - print_timing_graph(getEchoFileName(E_ECHO_INITIAL_PLACEMENT_TIMING_GRAPH)); - if(isEchoFileEnabled(E_ECHO_INITIAL_PLACEMENT_SLACK)) - print_slack(slacks->slack, FALSE, getEchoFileName(E_ECHO_INITIAL_PLACEMENT_SLACK)); - if(isEchoFileEnabled(E_ECHO_INITIAL_PLACEMENT_CRITICALITY)) - print_criticality(slacks, FALSE, getEchoFileName(E_ECHO_INITIAL_PLACEMENT_CRITICALITY)); - } - outer_crit_iter_count = 1; - - /*now we can properly compute costs */ - comp_td_costs(&timing_cost, &delay_cost); /*also vpr_printf proper values into point_to_point_delay_cost */ - - inverse_prev_timing_cost = 1 / timing_cost; - inverse_prev_bb_cost = 1 / bb_cost; - cost = 1; /*our new cost function uses normalized values of */ - /*bb_cost and timing_cost, the value of cost will be reset */ - /*to 1 at each temperature when *_TIMING_DRIVEN_PLACE is true */ - } else { /*BOUNDING_BOX_PLACE */ - cost = bb_cost = comp_bb_cost(NORMAL); - timing_cost = 0; - delay_cost = 0; - place_delay_value = 0; - outer_crit_iter_count = 0; - num_connections = 0; - crit_exponent = 0; - - inverse_prev_timing_cost = 0; /*inverses not used */ - inverse_prev_bb_cost = 0; - } - - move_lim = (int) (annealing_sched.inner_num * pow(num_blocks, 1.3333)); - - if (placer_opts.inner_loop_recompute_divider != 0) - inner_recompute_limit = (int) (0.5 - + (float) move_lim - / (float) placer_opts.inner_loop_recompute_divider); - else - /*don't do an inner recompute */ - inner_recompute_limit = move_lim + 1; - - /* Sometimes I want to run the router with a random placement. Avoid * - * using 0 moves to stop division by 0 and 0 length vector problems, * - * by setting move_lim to 1 (which is still too small to do any * - * significant optimization). */ - - if (move_lim <= 0) - move_lim = 1; - - rlim = (float) std::max(nx + 1, ny + 1); - - first_rlim = rlim; /*used in timing-driven placement for exponent computation */ - final_rlim = 1; - inverse_delta_rlim = 1 / (first_rlim - final_rlim); - - t = starting_t(&cost, &bb_cost, &timing_cost, - old_region_occ_x, old_region_occ_y, - annealing_sched, move_lim, rlim, - placer_opts.place_algorithm, placer_opts.timing_tradeoff, - inverse_prev_bb_cost, inverse_prev_timing_cost, &delay_cost); - tot_iter = 0; - moves_since_cost_recompute = 0; - vpr_printf(TIO_MESSAGE_INFO, "Initial placement cost: %g bb_cost: %g td_cost: %g delay_cost: %g\n", - cost, bb_cost, timing_cost, delay_cost); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - -#ifndef SPEC - vpr_printf(TIO_MESSAGE_INFO, "%9s %9s %11s %11s %11s %11s %8s %8s %7s %7s %7s %9s %7s\n", - "---------", "---------", "-----------", "-----------", "-----------", "-----------", - "--------", "--------", "-------", "-------", "-------", "---------", "-------"); - vpr_printf(TIO_MESSAGE_INFO, "%9s %9s %11s %11s %11s %11s %8s %8s %7s %7s %7s %9s %7s\n", - "T", "Cost", "Av BB Cost", "Av TD Cost", "Av Tot Del", - "P to P Del", "d_max", "Ac Rate", "Std Dev", "R limit", "Exp", - "Tot Moves", "Alpha"); - vpr_printf(TIO_MESSAGE_INFO, "%9s %9s %11s %11s %11s %11s %8s %8s %7s %7s %7s %9s %7s\n", - "---------", "---------", "-----------", "-----------", "-----------", "-----------", - "--------", "--------", "-------", "-------", "-------", "---------", "-------"); -#endif - - sprintf(msg, "Initial Placement. Cost: %g BB Cost: %g TD Cost %g Delay Cost: %g \t Channel Factor: %d", - cost, bb_cost, timing_cost, delay_cost, width_fac); - update_screen(MAJOR, msg, PLACEMENT, FALSE); - - while (exit_crit(t, cost, annealing_sched) == 0) { - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) { - cost = 1; - } - - av_cost = 0.; - av_bb_cost = 0.; - av_delay_cost = 0.; - av_timing_cost = 0.; - sum_of_squares = 0.; - success_sum = 0; - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) { - - if (outer_crit_iter_count >= placer_opts.recompute_crit_iter - || placer_opts.inner_loop_recompute_divider != 0) { -#ifdef VERBOSE - vpr_printf(TIO_MESSAGE_INFO, "Outer loop recompute criticalities\n"); -#endif - place_delay_value = delay_cost / num_connections; - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE) - load_constant_net_delay(net_delay, place_delay_value, - clb_net, num_nets); - /*note, for path_based, the net delay is not updated since it is current, - *because it accesses point_to_point_delay array */ - - load_timing_graph_net_delays(net_delay); - do_timing_analysis(slacks, FALSE, FALSE, FALSE); - load_criticalities(slacks, crit_exponent); - /*recompute costs from scratch, based on new criticalities */ - comp_td_costs(&timing_cost, &delay_cost); - outer_crit_iter_count = 0; - } - outer_crit_iter_count++; - - /*at each temperature change we update these values to be used */ - /*for normalizing the tradeoff between timing and wirelength (bb) */ - inverse_prev_bb_cost = 1 / bb_cost; - /*Prevent inverse timing cost from going to infinity */ - inverse_prev_timing_cost = std::min(1 / timing_cost, (float)MAX_INV_TIMING_COST); - } - - inner_crit_iter_count = 1; - - for (inner_iter = 0; inner_iter < move_lim; inner_iter++) { - swap_result = try_swap(t, &cost, &bb_cost, &timing_cost, rlim, - old_region_occ_x, - old_region_occ_y, - placer_opts.place_algorithm, placer_opts.timing_tradeoff, - inverse_prev_bb_cost, inverse_prev_timing_cost, &delay_cost); - if (swap_result == ACCEPTED) { - - /* Move was accepted. Update statistics that are useful for the annealing schedule. */ - success_sum++; - av_cost += cost; - av_bb_cost += bb_cost; - av_timing_cost += timing_cost; - av_delay_cost += delay_cost; - sum_of_squares += cost * cost; - num_swap_accepted++; - } else if (swap_result == ABORTED) { - num_swap_aborted++; - } else { // swap_result == REJECTED - num_swap_rejected++; - } - - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm - == PATH_TIMING_DRIVEN_PLACE) { - - /* Do we want to re-timing analyze the circuit to get updated slack and criticality values? - * We do this only once in a while, since it is expensive. - */ - if (inner_crit_iter_count >= inner_recompute_limit - && inner_iter != move_lim - 1) { /*on last iteration don't recompute */ - - inner_crit_iter_count = 0; -#ifdef VERBOSE - vpr_printf(TIO_MESSAGE_TRACE, "Inner loop recompute criticalities\n"); -#endif - if (placer_opts.place_algorithm - == NET_TIMING_DRIVEN_PLACE) { - /* Use a constant delay per connection as the delay estimate, rather than - * estimating based on the current placement. Not a great idea, but not the - * default. - */ - place_delay_value = delay_cost / num_connections; - load_constant_net_delay(net_delay, place_delay_value, - clb_net, num_nets); - } - - /* Using the delays in net_delay, do a timing analysis to update slacks and - * criticalities; then update the timing cost since it will change. - */ - load_timing_graph_net_delays(net_delay); - do_timing_analysis(slacks, FALSE, FALSE, FALSE); - load_criticalities(slacks, crit_exponent); - comp_td_costs(&timing_cost, &delay_cost); - } - inner_crit_iter_count++; - } -#ifdef VERBOSE - vpr_printf(TIO_MESSAGE_TRACE, "t = %g cost = %g bb_cost = %g timing_cost = %g move = %d dmax = %g\n", - t, cost, bb_cost, timing_cost, inner_iter, delay_cost); - if (fabs(bb_cost - comp_bb_cost(CHECK)) > bb_cost * ERROR_TOL) - exit(1); -#endif - } - - /* Lines below prevent too much round-off error from accumulating * - * in the cost over many iterations. This round-off can lead to * - * error checks failing because the cost is different from what * - * you get when you recompute from scratch. */ - - moves_since_cost_recompute += move_lim; - if (moves_since_cost_recompute > MAX_MOVES_BEFORE_RECOMPUTE) { - new_bb_cost = recompute_bb_cost(); - if (fabs(new_bb_cost - bb_cost) > bb_cost * ERROR_TOL) { - vpr_printf(TIO_MESSAGE_ERROR, "in try_place: new_bb_cost = %g, old bb_cost = %g\n", - new_bb_cost, bb_cost); - exit(1); - } - bb_cost = new_bb_cost; - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm - == PATH_TIMING_DRIVEN_PLACE) { - comp_td_costs(&new_timing_cost, &new_delay_cost); - if (fabs(new_timing_cost - timing_cost) > timing_cost * ERROR_TOL) { - vpr_printf(TIO_MESSAGE_ERROR, "in try_place: new_timing_cost = %g, old timing_cost = %g\n", - new_timing_cost, timing_cost); - exit(1); - } - if (fabs(new_delay_cost - delay_cost) > delay_cost * ERROR_TOL) { - vpr_printf(TIO_MESSAGE_ERROR, "in try_place: new_delay_cost = %g, old delay_cost = %g\n", - new_delay_cost, delay_cost); - exit(1); - } - timing_cost = new_timing_cost; - } - - if (placer_opts.place_algorithm == BOUNDING_BOX_PLACE) { - cost = new_bb_cost; - } - moves_since_cost_recompute = 0; - } - - tot_iter += move_lim; - success_rat = ((float) success_sum) / move_lim; - if (success_sum == 0) { - av_cost = cost; - av_bb_cost = bb_cost; - av_timing_cost = timing_cost; - av_delay_cost = delay_cost; - } else { - av_cost /= success_sum; - av_bb_cost /= success_sum; - av_timing_cost /= success_sum; - av_delay_cost /= success_sum; - } - std_dev = get_std_dev(success_sum, sum_of_squares, av_cost); - - oldt = t; /* for finding and printing alpha. */ - update_t(&t, std_dev, rlim, success_rat, annealing_sched); - -#ifndef SPEC - critical_path_delay = get_critical_path_delay(); - vpr_printf(TIO_MESSAGE_INFO, "%9.5f %9.5g %11.6g %11.6g %11.6g %11.6g %8.4f %8.4f %7.4f %7.4f %7.4f %9d %7.4f\n", - oldt, av_cost, av_bb_cost, av_timing_cost, av_delay_cost, place_delay_value, - critical_path_delay, success_rat, std_dev, rlim, crit_exponent, tot_iter, t / oldt); -#endif - - sprintf(msg, "Cost: %g BB Cost %g TD Cost %g Temperature: %g", - cost, bb_cost, timing_cost, t); - update_screen(MINOR, msg, PLACEMENT, FALSE); - update_rlim(&rlim, success_rat); - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) { - crit_exponent = (1 - (rlim - final_rlim) * inverse_delta_rlim) - * (placer_opts.td_place_exp_last - - placer_opts.td_place_exp_first) - + placer_opts.td_place_exp_first; - } -#ifdef VERBOSE - if (getEchoEnabled()) { - print_clb_placement("first_iteration_clb_placement.echo"); - } -#endif - } - - t = 0; /* freeze out */ - av_cost = 0.; - av_bb_cost = 0.; - av_timing_cost = 0.; - sum_of_squares = 0.; - av_delay_cost = 0.; - success_sum = 0; - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE) { - /*at each temperature change we update these values to be used */ - /*for normalizing the tradeoff between timing and wirelength (bb) */ - if (outer_crit_iter_count >= placer_opts.recompute_crit_iter - || placer_opts.inner_loop_recompute_divider != 0) { - -#ifdef VERBOSE - vpr_printf(TIO_MESSAGE_INFO, "Outer loop recompute criticalities\n"); -#endif - place_delay_value = delay_cost / num_connections; - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE) - load_constant_net_delay(net_delay, place_delay_value, clb_net, - num_nets); - - load_timing_graph_net_delays(net_delay); - do_timing_analysis(slacks, FALSE, FALSE, FALSE); - load_criticalities(slacks, crit_exponent); - /*recompute criticaliies */ - comp_td_costs(&timing_cost, &delay_cost); - outer_crit_iter_count = 0; - } - outer_crit_iter_count++; - - inverse_prev_bb_cost = 1 / (bb_cost); - /*Prevent inverse timing cost from going to infinity */ - inverse_prev_timing_cost = std::min(1 / timing_cost, (float)MAX_INV_TIMING_COST); - } - - inner_crit_iter_count = 1; - - for (inner_iter = 0; inner_iter < move_lim; inner_iter++) { - swap_result = try_swap(t, &cost, &bb_cost, &timing_cost, rlim, - old_region_occ_x, old_region_occ_y, - placer_opts.place_algorithm, placer_opts.timing_tradeoff, - inverse_prev_bb_cost, inverse_prev_timing_cost, &delay_cost); - - if (swap_result == ACCEPTED) { - success_sum++; - av_cost += cost; - av_bb_cost += bb_cost; - av_delay_cost += delay_cost; - av_timing_cost += timing_cost; - sum_of_squares += cost * cost; - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm - == PATH_TIMING_DRIVEN_PLACE) { - - if (inner_crit_iter_count >= inner_recompute_limit - && inner_iter != move_lim - 1) { - - inner_crit_iter_count = 0; -#ifdef VERBOSE - vpr_printf(TIO_MESSAGE_TRACE, "Inner loop recompute criticalities\n"); -#endif - if (placer_opts.place_algorithm - == NET_TIMING_DRIVEN_PLACE) { - place_delay_value = delay_cost / num_connections; - load_constant_net_delay(net_delay, place_delay_value, - clb_net, num_nets); - } - - load_timing_graph_net_delays(net_delay); - do_timing_analysis(slacks, FALSE, FALSE, FALSE); - load_criticalities(slacks, crit_exponent); - comp_td_costs(&timing_cost, &delay_cost); - } - inner_crit_iter_count++; - } - num_swap_accepted++; - } else if (swap_result == ABORTED) { - num_swap_aborted++; - } else { - num_swap_rejected++; - } - -#ifdef VERBOSE - vpr_printf(TIO_MESSAGE_INFO, "t = %g, cost = %g, move = %d\n", t, cost, tot_iter); -#endif - } - tot_iter += move_lim; - success_rat = ((float) success_sum) / move_lim; - if (success_sum == 0) { - av_cost = cost; - av_bb_cost = bb_cost; - av_delay_cost = delay_cost; - av_timing_cost = timing_cost; - } else { - av_cost /= success_sum; - av_bb_cost /= success_sum; - av_delay_cost /= success_sum; - av_timing_cost /= success_sum; - } - - std_dev = get_std_dev(success_sum, sum_of_squares, av_cost); - -#ifndef SPEC - vpr_printf(TIO_MESSAGE_INFO, "%9.5f %9.5g %11.6g %11.6g %11.6g %11.6g %8s %8.4f %7.4f %7.4f %7.4f %9d\n", - t, av_cost, av_bb_cost, av_timing_cost, av_delay_cost, place_delay_value, - " ", success_rat, std_dev, rlim, crit_exponent, tot_iter); -#endif - - // TODO: - // 1. print a message about number of aborted moves. - // 2. add some subroutine hierarchy! Too big! - // 3. put statistics counters (av_cost, success_sum, etc.) in a struct so a - // pointer to it can be passed around. - -#ifdef VERBOSE - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_END_CLB_PLACEMENT)) { - print_clb_placement(getEchoFileName(E_ECHO_END_CLB_PLACEMENT)); - } -#endif - - check_place(bb_cost, timing_cost, - placer_opts.place_algorithm, delay_cost); - - if (placer_opts.enable_timing_computations - && placer_opts.place_algorithm == BOUNDING_BOX_PLACE) { - /*need this done since the timing data has not been kept up to date* - *in bounding_box mode */ - for (inet = 0; inet < num_nets; inet++) - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) - timing_place_crit[inet][ipin] = 0; /*dummy crit values */ - comp_td_costs(&timing_cost, &delay_cost); /*computes point_to_point_delay_cost */ - } - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE - || placer_opts.enable_timing_computations) { - net_delay = point_to_point_delay_cost; /*this makes net_delay up to date with * - *the same values that the placer is using*/ - load_timing_graph_net_delays(net_delay); - - do_timing_analysis(slacks, FALSE, FALSE, FALSE); - - if (getEchoEnabled()) { - if(isEchoFileEnabled(E_ECHO_PLACEMENT_SINK_DELAYS)) - print_sink_delays(getEchoFileName(E_ECHO_PLACEMENT_SINK_DELAYS)); - if(isEchoFileEnabled(E_ECHO_FINAL_PLACEMENT_SLACK)) - print_slack(slacks->slack, FALSE, getEchoFileName(E_ECHO_FINAL_PLACEMENT_SLACK)); - if(isEchoFileEnabled(E_ECHO_FINAL_PLACEMENT_CRITICALITY)) - print_criticality(slacks, FALSE, getEchoFileName(E_ECHO_FINAL_PLACEMENT_CRITICALITY)); - if(isEchoFileEnabled(E_ECHO_FINAL_PLACEMENT_TIMING_GRAPH)) - print_timing_graph(getEchoFileName(E_ECHO_FINAL_PLACEMENT_TIMING_GRAPH)); - if(isEchoFileEnabled(E_ECHO_PLACEMENT_CRIT_PATH)) - print_critical_path(getEchoFileName(E_ECHO_PLACEMENT_CRIT_PATH)); - } - - /* Print critical path delay. */ - critical_path_delay = get_critical_path_delay(); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Placement estimated critical path delay: %g ns\n", critical_path_delay); - } - - sprintf(msg, "Placement. Cost: %g bb_cost: %g td_cost: %g Channel Factor: %d", - cost, bb_cost, timing_cost, width_fac); - vpr_printf(TIO_MESSAGE_INFO, "Placement cost: %g, bb_cost: %g, td_cost: %g, delay_cost: %g\n", - cost, bb_cost, timing_cost, delay_cost); - update_screen(MAJOR, msg, PLACEMENT, FALSE); - - // Print out swap statistics - total_swap_attempts = num_swap_rejected + num_swap_accepted + num_swap_aborted; - reject_rate = num_swap_rejected / total_swap_attempts; - accept_rate = num_swap_accepted / total_swap_attempts; - abort_rate = num_swap_aborted / total_swap_attempts; - vpr_printf(TIO_MESSAGE_INFO, "Placement total # of swap attempts: %d\n", total_swap_attempts); - vpr_printf(TIO_MESSAGE_INFO, "\tSwap reject rate: %g\n", reject_rate); - vpr_printf(TIO_MESSAGE_INFO, "\tSwap accept rate: %g\n", accept_rate); - vpr_printf(TIO_MESSAGE_INFO, "\tSwap abort rate: %g\n", abort_rate); - - -#ifdef SPEC - vpr_printf(TIO_MESSAGE_INFO, "Total moves attempted: %d.0\n", tot_iter); -#endif - - free_placement_structs( - old_region_occ_x, old_region_occ_y, - placer_opts); - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE - || placer_opts.enable_timing_computations) { - - net_delay = remember_net_delay_original_ptr; - free_lookups_and_criticalities(&net_delay, slacks); - } - - free_try_swap_arrays(); -} - -static int count_connections() { - /*only count non-global connections */ - - int count, inet; - - count = 0; - - for (inet = 0; inet < num_nets; inet++) { - - if (clb_net[inet].is_global) - continue; - - count += clb_net[inet].num_sinks; - } - return (count); -} - -static double get_std_dev(int n, double sum_x_squared, double av_x) { - - /* Returns the standard deviation of data set x. There are n sample points, * - * sum_x_squared is the summation over n of x^2 and av_x is the average x. * - * All operations are done in double precision, since round off error can be * - * a problem in the initial temp. std_dev calculation for big circuits. */ - - double std_dev; - - if (n <= 1) - std_dev = 0.; - else - std_dev = (sum_x_squared - n * av_x * av_x) / (double) (n - 1); - - if (std_dev > 0.) /* Very small variances sometimes round negative */ - std_dev = sqrt(std_dev); - else - std_dev = 0.; - - return (std_dev); -} - -static void update_rlim(float *rlim, float success_rat) { - - /* Update the range limited to keep acceptance prob. near 0.44. Use * - * a floating point rlim to allow gradual transitions at low temps. */ - - float upper_lim; - - *rlim = (*rlim) * (1. - 0.44 + success_rat); - upper_lim = std::max(nx + 1, ny + 1); - *rlim = std::min(*rlim, upper_lim); - *rlim = std::max(*rlim, (float)1.); -} - -/* Update the temperature according to the annealing schedule selected. */ -static void update_t(float *t, float std_dev, float rlim, float success_rat, - struct s_annealing_sched annealing_sched) { - - /* float fac; */ - - if (annealing_sched.type == USER_SCHED) { - *t = annealing_sched.alpha_t * (*t); - } - - /* Old standard deviation based stuff is below. This bogs down horribly - * for big circuits (alu4 and especially bigkey_mod). */ - /* #define LAMBDA .7 */ - /* ------------------------------------ */ -#if 0 - else if (std_dev == 0.) - { - *t = 0.; - } - else - { - fac = exp(-LAMBDA * (*t) / std_dev); - fac = max(0.5, fac); - *t = (*t) * fac; - } -#endif - /* ------------------------------------- */ - - else { /* AUTO_SCHED */ - if (success_rat > 0.96) { - *t = (*t) * 0.5; - } else if (success_rat > 0.8) { - *t = (*t) * 0.9; - } else if (success_rat > 0.15 || rlim > 1.) { - *t = (*t) * 0.95; - } else { - *t = (*t) * 0.8; - } - } -} - -static int exit_crit(float t, float cost, - struct s_annealing_sched annealing_sched) { - - /* Return 1 when the exit criterion is met. */ - - if (annealing_sched.type == USER_SCHED) { - if (t < annealing_sched.exit_t) { - return (1); - } else { - return (0); - } - } - - /* Automatic annealing schedule */ - - if (t < 0.005 * cost / num_nets) { - return (1); - } else { - return (0); - } -} - -static float starting_t(float *cost_ptr, float *bb_cost_ptr, - float *timing_cost_ptr, float **old_region_occ_x, - float **old_region_occ_y, - struct s_annealing_sched annealing_sched, int max_moves, float rlim, - enum e_place_algorithm place_algorithm, float timing_tradeoff, - float inverse_prev_bb_cost, float inverse_prev_timing_cost, - float *delay_cost_ptr) { - - /* Finds the starting temperature (hot condition). */ - - int i, num_accepted, move_lim, swap_result; - double std_dev, av, sum_of_squares; /* Double important to avoid round off */ - - if (annealing_sched.type == USER_SCHED) - return (annealing_sched.init_t); - - move_lim = std::min(max_moves, num_blocks); - - num_accepted = 0; - av = 0.; - sum_of_squares = 0.; - - /* Try one move per block. Set t high so essentially all accepted. */ - - for (i = 0; i < move_lim; i++) { - swap_result = try_swap(HUGE_POSITIVE_FLOAT, cost_ptr, bb_cost_ptr, timing_cost_ptr, rlim, - old_region_occ_x, old_region_occ_y, - place_algorithm, timing_tradeoff, - inverse_prev_bb_cost, inverse_prev_timing_cost, delay_cost_ptr); - - if (swap_result == ACCEPTED) { - num_accepted++; - av += *cost_ptr; - sum_of_squares += *cost_ptr * (*cost_ptr); - num_swap_accepted++; - } else if (swap_result == ABORTED) { - num_swap_aborted++; - } else { - num_swap_rejected++; - } - } - - if (num_accepted != 0) - av /= num_accepted; - else - av = 0.; - - std_dev = get_std_dev(num_accepted, sum_of_squares, av); - -#ifdef DEBUG - if (num_accepted != move_lim) { - vpr_printf(TIO_MESSAGE_WARNING, "Starting t: %d of %d configurations accepted.\n", num_accepted, move_lim); - } -#endif - -#ifdef VERBOSE - vpr_printf(TIO_MESSAGE_INFO, "std_dev: %g, average cost: %g, starting temp: %g\n", std_dev, av, 20. * std_dev); -#endif - - /* Set the initial temperature to 20 times the standard of deviation */ - /* so that the initial temperature adjusts according to the circuit */ - return (20. * std_dev); -} - - -static int setup_blocks_affected(int b_from, int x_to, int y_to, int z_to) { - - /* Find all the blocks affected when b_from is swapped with b_to. - * Returns abort_swap. */ - - int imoved_blk, imacro; - int x_from, y_from, z_from, b_to; - int abort_swap = FALSE; - - /* Xifan TANG: support swap between macros */ - /* int from_macro; */ - - x_from = block[b_from].x; - y_from = block[b_from].y; - z_from = block[b_from].z; - - b_to = grid[x_to][y_to].blocks[z_to]; - - // Check whether the to_location is empty - if (b_to == EMPTY) { - - // Swap the block, dont swap the nets yet - block[b_from].x = x_to; - block[b_from].y = y_to; - block[b_from].z = z_to; - - // Sets up the blocks moved - imoved_blk = blocks_affected.num_moved_blocks; - blocks_affected.moved_blocks[imoved_blk].block_num = b_from; - blocks_affected.moved_blocks[imoved_blk].xold = x_from; - blocks_affected.moved_blocks[imoved_blk].xnew = x_to; - blocks_affected.moved_blocks[imoved_blk].yold = y_from; - blocks_affected.moved_blocks[imoved_blk].ynew = y_to; - blocks_affected.moved_blocks[imoved_blk].zold = z_from; - blocks_affected.moved_blocks[imoved_blk].znew = z_to; - blocks_affected.moved_blocks[imoved_blk].swapped_to_empty = TRUE; - blocks_affected.num_moved_blocks ++; - - } else { - - // Does not allow a swap with a macro yet - /* Xifan TANG: allow macro swapping...*/ - get_imacro_from_iblk(&imacro, b_to, pl_macros, num_pl_macros); - /* get_imacro_from_iblk(&from_macro, b_from, pl_macros, num_pl_macros); - if (((-1 != from_macro)||(imacro != -1)) - &&(!((-1 != from_macro)&&(imacro != -1)))) { - */ - if (imacro != -1) { - abort_swap = TRUE; - return (abort_swap); - } - - // Swap the block, dont swap the nets yet - block[b_to].x = x_from; - block[b_to].y = y_from; - block[b_to].z = z_from; - - block[b_from].x = x_to; - block[b_from].y = y_to; - block[b_from].z = z_to; - - // Sets up the blocks moved - imoved_blk = blocks_affected.num_moved_blocks; - blocks_affected.moved_blocks[imoved_blk].block_num = b_from; - blocks_affected.moved_blocks[imoved_blk].xold = x_from; - blocks_affected.moved_blocks[imoved_blk].xnew = x_to; - blocks_affected.moved_blocks[imoved_blk].yold = y_from; - blocks_affected.moved_blocks[imoved_blk].ynew = y_to; - blocks_affected.moved_blocks[imoved_blk].zold = z_from; - blocks_affected.moved_blocks[imoved_blk].znew = z_to; - blocks_affected.moved_blocks[imoved_blk].swapped_to_empty = FALSE; - blocks_affected.num_moved_blocks ++; - - imoved_blk = blocks_affected.num_moved_blocks; - blocks_affected.moved_blocks[imoved_blk].block_num = b_to; - blocks_affected.moved_blocks[imoved_blk].xold = x_to; - blocks_affected.moved_blocks[imoved_blk].xnew = x_from; - blocks_affected.moved_blocks[imoved_blk].yold = y_to; - blocks_affected.moved_blocks[imoved_blk].ynew = y_from; - blocks_affected.moved_blocks[imoved_blk].zold = z_to; - blocks_affected.moved_blocks[imoved_blk].znew = z_from; - blocks_affected.moved_blocks[imoved_blk].swapped_to_empty = FALSE; - blocks_affected.num_moved_blocks ++; - - } // Finish swapping the blocks and setting up blocks_affected - - return (abort_swap); - -} - -static int find_affected_blocks(int b_from, int x_to, int y_to, int z_to) { - - /* Finds and set ups the affected_blocks array. - * Returns abort_swap. */ - - int imacro, imember; - int x_swap_offset, y_swap_offset, z_swap_offset, x_from, y_from, z_from; - int curr_b_from, curr_x_from, curr_y_from, curr_z_from, curr_x_to, curr_y_to, curr_z_to; - int abort_swap = FALSE; - - /* int to_imacro;*/ /* Xifan TANG: for more checking */ - - x_from = block[b_from].x; - y_from = block[b_from].y; - z_from = block[b_from].z; - - get_imacro_from_iblk(&imacro, b_from, pl_macros, num_pl_macros); - if ( imacro != -1) { - // b_from is part of a macro, I need to swap the whole macro - - // Record down the relative position of the swap - x_swap_offset = x_to - x_from; - y_swap_offset = y_to - y_from; - z_swap_offset = z_to - z_from; - - for (imember = 0; imember < pl_macros[imacro].num_blocks && abort_swap == FALSE; imember++) { - - // Gets the new from and to info for every block in the macro - // cannot use the old from and to info - curr_b_from = pl_macros[imacro].members[imember].blk_index; - - curr_x_from = block[curr_b_from].x; - curr_y_from = block[curr_b_from].y; - curr_z_from = block[curr_b_from].z; - - curr_x_to = curr_x_from + x_swap_offset; - curr_y_to = curr_y_from + y_swap_offset; - curr_z_to = curr_z_from + z_swap_offset; - - /* Xifan TANG: double check*/ - assert(block[curr_b_from].type == grid[curr_x_from][curr_y_from].type); - - // Make sure that the swap_to location is still on the chip - if (curr_x_to < 1 || curr_x_to > nx || curr_y_to < 1 || curr_y_to > ny || curr_z_to < 0) { - abort_swap = TRUE; - /* Xifan TANG: We need to check if the swap_to location has the same type! */ - /* - } else if (grid[curr_x_from][curr_y_from].type != grid[curr_x_to][curr_y_to].type) { - abort_swap = TRUE; - */ - } else { - /* Xifan TANG: Check if the to_x, to_y is also a marco... - * If the follow cases are true then we should abort the swap - * 1. length of to_macro is larger than this macro - * 2. length of to_macro is the same as this macro, but its starting point is not align with this macro. - * 2. length of to_macro is less this macro, but its starting/ending point is out of the range of this macro. - */ - /* - curr_b_to = grid[curr_x_to][curr_y_to].blocks[curr_z_to]; - if (OPEN != curr_b_to) { - get_imacro_from_iblk(&to_imacro, curr_b_to, pl_macros, num_pl_macros); - } - if (OPEN != to_imacro) { - if (pl_macros[imacro].num_blocks < pl_macros[to_imacro].num_blocks) { - abort_swap = TRUE; - } else if ((pl_macros[imacro].num_blocks == pl_macros[to_imacro].num_blocks) - && (imember != spot_blk_position_in_a_macro(pl_macros[to_imacro],curr_b_to))) { - abort_swap = TRUE; - } else if ((pl_macros[imacro].num_blocks > pl_macros[to_imacro].num_blocks) - && (0 == check_macros_contained(pl_macros[imacro], pl_macros[to_imacro]))) { - abort_swap = TRUE; - } - } - } - } - */ - /* Xifan TANG: Only all the memebers in the macro pass the check, we can proceed to setup swap */ - /* - if (FALSE == abort_swap) { - for (imember = 0; imember < pl_macros[imacro].num_blocks && abort_swap == FALSE; imember++) { - // Gets the new from and to info for every block in the macro - // cannot use the old from and to info - curr_b_from = pl_macros[imacro].members[imember].blk_index; - - curr_x_from = block[curr_b_from].x; - curr_y_from = block[curr_b_from].y; - curr_z_from = block[curr_b_from].z; - - curr_x_to = curr_x_from + x_swap_offset; - curr_y_to = curr_y_from + y_swap_offset; - curr_z_to = curr_z_from + z_swap_offset; - */ - abort_swap = setup_blocks_affected(curr_b_from, curr_x_to, curr_y_to, curr_z_to); - } // Finish going through all the blocks in the macro - } - } else { - - // This is not a macro - I could use the from and to info from before - abort_swap = setup_blocks_affected(b_from, x_to, y_to, z_to); - - } // Finish handling cases for blocks in macro and otherwise - - return (abort_swap); - -} - -static enum swap_result try_swap(float t, float *cost, float *bb_cost, float *timing_cost, - float rlim, float **old_region_occ_x, - float **old_region_occ_y, - enum e_place_algorithm place_algorithm, float timing_tradeoff, - float inverse_prev_bb_cost, float inverse_prev_timing_cost, - float *delay_cost) { - - /* Picks some block and moves it to another spot. If this spot is * - * occupied, switch the blocks. Assess the change in cost function * - * and accept or reject the move. If rejected, return 0. If * - * accepted return 1. Pass back the new value of the cost function. * - * rlim is the range limiter. */ - - enum swap_result keep_switch; - int b_from, x_from, y_from, z_from, x_to, y_to, z_to; - int num_nets_affected; - float delta_c, bb_delta_c, timing_delta_c, delay_delta_c; - int inet, iblk, bnum, iblk_pin, inet_affected; - int abort_swap = FALSE; - - num_ts_called ++; - - /* I'm using negative values of temp_net_cost as a flag, so DO NOT * - * use cost functions that can go negative. */ - - delta_c = 0; /* Change in cost due to this swap. */ - bb_delta_c = 0; - timing_delta_c = 0; - delay_delta_c = 0.0; - - /* Pick a random block to be swapped with another random block */ - b_from = my_irand(num_blocks - 1); - - /* If the pins are fixed we never move them from their initial * - * random locations. The code below could be made more efficient * - * by using the fact that pins appear first in the block list, * - * but this shouldn't cause any significant slowdown and won't be * - * broken if I ever change the parser so that the pins aren't * - * necessarily at the start of the block list. */ - while (block[b_from].isFixed == TRUE) { - b_from = my_irand(num_blocks - 1); - } - - x_from = block[b_from].x; - y_from = block[b_from].y; - z_from = block[b_from].z; - - if (!find_to(x_from, y_from, block[b_from].type, rlim, &x_to, - &y_to)) { - return REJECTED; - } - - z_to = 0; - if (grid[x_to][y_to].type->capacity > 1) { - z_to = my_irand(grid[x_to][y_to].type->capacity - 1); - } - - /* Make the switch in order to make computing the new bounding * - * box simpler. If the cost increase is too high, switch them * - * back. (block data structures switched, clbs not switched * - * until success of move is determined.) * - * Also check that whether those are the only 2 blocks * - * to be moved - check for carry chains and other placement * - * macros. */ - - /* Check whether the from_block is part of a macro first. * - * If it is, the whole macro has to be moved. Calculate the * - * x, y, z offsets of the swap to maintain relative placements * - * of the blocks. Abort the swap if the to_block is part of a * - * macro (not supported yet). */ - - abort_swap = find_affected_blocks(b_from, x_to, y_to, z_to); - - if (abort_swap == FALSE) { - - // Find all the nets affected by this swap - num_nets_affected = find_affected_nets(ts_nets_to_update); - - /* Go through all the pins in all the blocks moved and update the bounding boxes. * - * Do not update the net cost here since it should only be updated once per net, * - * not once per pin */ - for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) - { - bnum = blocks_affected.moved_blocks[iblk].block_num; - - /* Go through all the pins in the moved block */ - for (iblk_pin = 0; iblk_pin < block[bnum].type->num_pins; iblk_pin++) - { - inet = block[bnum].nets[iblk_pin]; - if (inet == OPEN) - continue; - if (clb_net[inet].is_global) - continue; - - if (clb_net[inet].num_sinks < SMALL_NET) { - if(bb_updated_before[inet] == NOT_UPDATED_YET) - /* Brute force bounding box recomputation, once only for speed. */ - get_non_updateable_bb(inet, &ts_bb_coord_new[inet]); - } else { - update_bb(inet, &ts_bb_coord_new[inet], - &ts_bb_edge_new[inet], - blocks_affected.moved_blocks[iblk].xold, - blocks_affected.moved_blocks[iblk].yold + block[bnum].type->pin_height[iblk_pin], - blocks_affected.moved_blocks[iblk].xnew, - blocks_affected.moved_blocks[iblk].ynew + block[bnum].type->pin_height[iblk_pin]); - } - } - } - - /* Now update the cost function. The cost is only updated once for every net * - * May have to do major optimizations here later. */ - for (inet_affected = 0; inet_affected < num_nets_affected; inet_affected++) { - inet = ts_nets_to_update[inet_affected]; - - temp_net_cost[inet] = get_net_cost(inet, &ts_bb_coord_new[inet]); - bb_delta_c += temp_net_cost[inet] - net_cost[inet]; - } - - if (place_algorithm == NET_TIMING_DRIVEN_PLACE - || place_algorithm == PATH_TIMING_DRIVEN_PLACE) { - /*in this case we redefine delta_c as a combination of timing and bb. * - *additionally, we normalize all values, therefore delta_c is in * - *relation to 1*/ - - comp_delta_td_cost(&timing_delta_c, &delay_delta_c); - - delta_c = (1 - timing_tradeoff) * bb_delta_c * inverse_prev_bb_cost - + timing_tradeoff * timing_delta_c * inverse_prev_timing_cost; - } else { - delta_c = bb_delta_c; - } - - /* 1 -> move accepted, 0 -> rejected. */ - keep_switch = assess_swap(delta_c, t); - - if (keep_switch == ACCEPTED) { - *cost = *cost + delta_c; - *bb_cost = *bb_cost + bb_delta_c; - - if (place_algorithm == NET_TIMING_DRIVEN_PLACE - || place_algorithm == PATH_TIMING_DRIVEN_PLACE) { - /*update the point_to_point_timing_cost and point_to_point_delay_cost - * values from the temporary values */ - *timing_cost = *timing_cost + timing_delta_c; - *delay_cost = *delay_cost + delay_delta_c; - - update_td_cost(); - } - - /* update net cost functions and reset flags. */ - for (inet_affected = 0; inet_affected < num_nets_affected; inet_affected++) { - inet = ts_nets_to_update[inet_affected]; - - bb_coords[inet] = ts_bb_coord_new[inet]; - if (clb_net[inet].num_sinks >= SMALL_NET) - bb_num_on_edges[inet] = ts_bb_edge_new[inet]; - - net_cost[inet] = temp_net_cost[inet]; - - /* negative temp_net_cost value is acting as a flag. */ - temp_net_cost[inet] = -1; - bb_updated_before[inet] = NOT_UPDATED_YET; - } - - /* Update clb data structures since we kept the move. */ - /* Swap physical location */ - for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) { - - x_to = blocks_affected.moved_blocks[iblk].xnew; - y_to = blocks_affected.moved_blocks[iblk].ynew; - z_to = blocks_affected.moved_blocks[iblk].znew; - /* Xifan TANG: not sure if this is needed */ - //b_to = grid[x_to][y_to].blocks[z_to]; - - x_from = blocks_affected.moved_blocks[iblk].xold; - y_from = blocks_affected.moved_blocks[iblk].yold; - z_from = blocks_affected.moved_blocks[iblk].zold; - - b_from = blocks_affected.moved_blocks[iblk].block_num; - - grid[x_to][y_to].blocks[z_to] = b_from; - /* Xifan TANG: not sure if this is needed */ - //grid[x_from][y_from].blocks[z_from] = b_to; - - if (blocks_affected.moved_blocks[iblk].swapped_to_empty == TRUE) { - grid[x_to][y_to].usage++; - grid[x_from][y_from].usage--; - grid[x_from][y_from].blocks[z_from] = -1; - } - - } // Finish updating clb for all blocks - - } else { /* Move was rejected. */ - - /* Reset the net cost function flags first. */ - for (inet_affected = 0; inet_affected < num_nets_affected; inet_affected++) { - inet = ts_nets_to_update[inet_affected]; - temp_net_cost[inet] = -1; - bb_updated_before[inet] = NOT_UPDATED_YET; - } - - /* Restore the block data structures to their state before the move. */ - for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) { - b_from = blocks_affected.moved_blocks[iblk].block_num; - - block[b_from].x = blocks_affected.moved_blocks[iblk].xold; - block[b_from].y = blocks_affected.moved_blocks[iblk].yold; - block[b_from].z = blocks_affected.moved_blocks[iblk].zold; - } - } - - /* Resets the num_moved_blocks, but do not free blocks_moved array. Defensive Coding */ - blocks_affected.num_moved_blocks = 0; - - //check_place(*bb_cost, *timing_cost, place_algorithm, *delay_cost); - - return (keep_switch); - } else { - - /* Restore the block data structures to their state before the move. */ - for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) { - b_from = blocks_affected.moved_blocks[iblk].block_num; - - block[b_from].x = blocks_affected.moved_blocks[iblk].xold; - block[b_from].y = blocks_affected.moved_blocks[iblk].yold; - block[b_from].z = blocks_affected.moved_blocks[iblk].zold; - } - - /* Resets the num_moved_blocks, but do not free blocks_moved array. Defensive Coding */ - blocks_affected.num_moved_blocks = 0; - - return ABORTED; - } -} - -static int find_affected_nets(int *nets_to_update) { - - /* Puts a list of all the nets that are changed by the swap into * - * nets_to_update. Returns the number of affected nets. */ - - int iblk, iblk_pin, inet, bnum, num_affected_nets; - - num_affected_nets = 0; - /* Go through all the blocks moved */ - for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) - { - bnum = blocks_affected.moved_blocks[iblk].block_num; - - /* Go through all the pins in the moved block */ - for (iblk_pin = 0; iblk_pin < block[bnum].type->num_pins; iblk_pin++) - { - /* Updates the pins_to_nets array, set to -1 if * - * that pin is not connected to any net or it is a * - * global pin that does not need to be updated */ - inet = block[bnum].nets[iblk_pin]; - if (inet == OPEN) - continue; - if (clb_net[inet].is_global) - continue; - - if (temp_net_cost[inet] < 0.) { - /* Net not marked yet. */ - nets_to_update[num_affected_nets] = inet; - num_affected_nets++; - - /* Flag to say we've marked this net. */ - temp_net_cost[inet] = 1.; - } - } - } - return num_affected_nets; -} - -static boolean find_to(int x_from, int y_from, t_type_ptr type, float rlim, int *x_to, int *y_to) { - - /* Returns the point to which I want to swap, properly range limited. - * rlim must always be between 1 and nx (inclusive) for this routine - * to work. Assumes that a column only contains blocks of the same type. - */ - - int x_rel, y_rel, rlx, rly, min_x, max_x, min_y, max_y; - int num_tries; - int active_area; - boolean is_legal; - int block_index, ipos; - - if (type != grid[x_from][y_from].type) { - assert(type == grid[x_from][y_from].type); - } - - rlx = (int)std::min((float)nx + 1, rlim); - rly = (int)std::min((float)ny + 1, rlim); /* Added rly for aspect_ratio != 1 case. */ - active_area = 4 * rlx * rly; - - min_x = std::max(0, x_from - rlx); - max_x = std::min(nx + 1, x_from + rlx); - min_y = std::max(0, y_from - rly); - max_y = std::min(ny + 1, y_from + rly); - -#ifdef DEBUG - if (rlx < 1 || rlx > nx + 1) { - vpr_printf(TIO_MESSAGE_ERROR, "in find_to: rlx = %d\n", rlx); - exit(1); - } -#endif - - num_tries = 0; - block_index = type->index; - - do { /* Until legal */ - is_legal = TRUE; - - /* Limit the number of tries when searching for an alternative position */ - if(num_tries >= 2 * std::min(active_area / type->height, num_legal_pos[block_index]) + 10) { - /* Tried randomly searching for a suitable position */ - return FALSE; - } else { - num_tries++; - } - if(nx / 4 < rlx || - ny / 4 < rly || - num_legal_pos[block_index] < active_area) { - ipos = my_irand(num_legal_pos[block_index] - 1); - *x_to = legal_pos[block_index][ipos].x; - *y_to = legal_pos[block_index][ipos].y; - } else { - x_rel = my_irand(std::max(0, max_x - min_x)); - *x_to = min_x + x_rel; - y_rel = my_irand(std::max(0, max_y - min_y)); - *y_to = min_y + y_rel; - *y_to = (*y_to) - grid[*x_to][*y_to].offset; /* align it */ - } - - if((x_from == *x_to) && (y_from == *y_to)) { - is_legal = FALSE; - } else if(*x_to > max_x || *x_to < min_x || *y_to > max_y || *y_to < min_y) { - is_legal = FALSE; - } else if(grid[*x_to][*y_to].type != grid[x_from][y_from].type) { - is_legal = FALSE; - } - - assert(*x_to >= 0 && *x_to <= nx + 1); - assert(*y_to >= 0 && *y_to <= ny + 1); - } while (is_legal == FALSE); - -#ifdef DEBUG - if (*x_to < 0 || *x_to > nx + 1 || *y_to < 0 || *y_to > ny + 1) { - vpr_printf(TIO_MESSAGE_ERROR, "in routine find_to: (x_to,y_to) = (%d,%d)\n", *x_to, *y_to); - exit(1); - } -#endif - assert(type == grid[*x_to][*y_to].type); - return TRUE; -} - -static enum swap_result assess_swap(float delta_c, float t) { - - /* Returns: 1 -> move accepted, 0 -> rejected. */ - - enum swap_result accept; - float prob_fac, fnum; - - if (delta_c <= 0) { - -#ifdef SPEC /* Reduce variation in final solution due to round off */ - fnum = my_frand(); -#endif - - accept = ACCEPTED; - return (accept); - } - - if (t == 0.) - return (REJECTED); - - fnum = my_frand(); - prob_fac = exp(-delta_c / t); - if (prob_fac > fnum) { - accept = ACCEPTED; - } else { - accept = REJECTED; - } - return (accept); -} - -static float recompute_bb_cost(void) { - - /* Recomputes the cost to eliminate roundoff that may have accrued. * - * This routine does as little work as possible to compute this new * - * cost. */ - - int inet; - float cost; - - cost = 0; - - for (inet = 0; inet < num_nets; inet++) { /* for each net ... */ - if (clb_net[inet].is_global == FALSE) { /* Do only if not global. */ - - /* Bounding boxes don't have to be recomputed; they're correct. */ - cost += net_cost[inet]; - } - } - - return (cost); -} - -static float comp_td_point_to_point_delay(int inet, int ipin) { - - /*returns the delay of one point to point connection */ - - int source_block, sink_block; - int delta_x, delta_y; - t_type_ptr source_type, sink_type; - float delay_source_to_sink; - - delay_source_to_sink = 0.; - - source_block = clb_net[inet].node_block[0]; - source_type = block[source_block].type; - - sink_block = clb_net[inet].node_block[ipin]; - sink_type = block[sink_block].type; - - assert(source_type != NULL); - assert(sink_type != NULL); - - delta_x = abs(block[sink_block].x - block[source_block].x); - delta_y = abs(block[sink_block].y - block[source_block].y); - - /* TODO low priority: Could be merged into one look-up table */ - /* Note: This heuristic is terrible on Quality of Results. - * A much better heuristic is to create a more comprehensive lookup table but - * it's too late in the release cycle to do this. Pushing until the next release */ - if (source_type == IO_TYPE) { - if (sink_type == IO_TYPE) - delay_source_to_sink = delta_io_to_io[delta_x][delta_y]; - else - delay_source_to_sink = delta_io_to_clb[delta_x][delta_y]; - } else { - if (sink_type == IO_TYPE) - delay_source_to_sink = delta_clb_to_io[delta_x][delta_y]; - else - delay_source_to_sink = delta_clb_to_clb[delta_x][delta_y]; - } - if (delay_source_to_sink < 0) { - vpr_printf(TIO_MESSAGE_ERROR, "in comp_td_point_to_point_delay: Bad delay_source_to_sink value delta(%d, %d) delay of %g\n", delta_x, delta_y, delay_source_to_sink); - vpr_printf(TIO_MESSAGE_ERROR, "in comp_td_point_to_point_delay: Delay is less than 0\n"); - exit(1); - } - - return (delay_source_to_sink); -} - -static void update_td_cost(void) { - /* Update the point_to_point_timing_cost values from the temporary * - * values for all connections that have changed. */ - - int iblk_pin, net_pin, inet, ipin; - int iblk, iblk2, bnum, driven_by_moved_block; - - /* Go through all the blocks moved. */ - for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) - { - bnum = blocks_affected.moved_blocks[iblk].block_num; - for (iblk_pin = 0; iblk_pin < block[bnum].type->num_pins; iblk_pin++) { - - inet = block[bnum].nets[iblk_pin]; - - if (inet == OPEN) - continue; - - if (clb_net[inet].is_global) - continue; - - net_pin = net_pin_index[bnum][iblk_pin]; - - if (net_pin != 0) { - - driven_by_moved_block = FALSE; - for (iblk2 = 0; iblk2 < blocks_affected.num_moved_blocks; iblk2++) - { if (clb_net[inet].node_block[0] == blocks_affected.moved_blocks[iblk2].block_num) - driven_by_moved_block = TRUE; - } - - /* The following "if" prevents the value from being updated twice. */ - if (driven_by_moved_block == FALSE) { - point_to_point_delay_cost[inet][net_pin] = - temp_point_to_point_delay_cost[inet][net_pin]; - temp_point_to_point_delay_cost[inet][net_pin] = -1; - point_to_point_timing_cost[inet][net_pin] = - temp_point_to_point_timing_cost[inet][net_pin]; - temp_point_to_point_timing_cost[inet][net_pin] = -1; - } - } else { /* This net is being driven by a moved block, recompute */ - /* All point to point connections on this net. */ - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { - point_to_point_delay_cost[inet][ipin] = - temp_point_to_point_delay_cost[inet][ipin]; - temp_point_to_point_delay_cost[inet][ipin] = -1; - point_to_point_timing_cost[inet][ipin] = - temp_point_to_point_timing_cost[inet][ipin]; - temp_point_to_point_timing_cost[inet][ipin] = -1; - } /* Finished updating the pin */ - } - } /* Finished going through all the pins in the moved block */ - } /* Finished going through all the blocks moved */ -} - -static void comp_delta_td_cost(float *delta_timing, float *delta_delay) { - - /*a net that is being driven by a moved block must have all of its */ - /*sink timing costs recomputed. A net that is driving a moved block */ - /*must only have the timing cost on the connection driving the input */ - /*pin computed */ - - int inet, net_pin, ipin; - float delta_timing_cost, delta_delay_cost, temp_delay; - int iblk, iblk2, bnum, iblk_pin, driven_by_moved_block; - - delta_timing_cost = 0.; - delta_delay_cost = 0.; - - /* Go through all the blocks moved */ - for (iblk = 0; iblk < blocks_affected.num_moved_blocks; iblk++) - { - bnum = blocks_affected.moved_blocks[iblk].block_num; - /* Go through all the pins in the moved block */ - for (iblk_pin = 0; iblk_pin < block[bnum].type->num_pins; iblk_pin++) { - inet = block[bnum].nets[iblk_pin]; - - if (inet == OPEN) - continue; - - if (clb_net[inet].is_global) - continue; - - net_pin = net_pin_index[bnum][iblk_pin]; - - if (net_pin != 0) { - /* If this net is being driven by a block that has moved, we do not * - * need to compute the change in the timing cost (here) since it will * - * be computed in the fanout of the net on the driving block, also * - * computing it here would double count the change, and mess up the * - * delta_timing_cost value. */ - driven_by_moved_block = FALSE; - for (iblk2 = 0; iblk2 < blocks_affected.num_moved_blocks; iblk2++) - { if (clb_net[inet].node_block[0] == blocks_affected.moved_blocks[iblk2].block_num) - driven_by_moved_block = TRUE; - } - - if (driven_by_moved_block == FALSE) { - temp_delay = comp_td_point_to_point_delay(inet, net_pin); - temp_point_to_point_delay_cost[inet][net_pin] = temp_delay; - - temp_point_to_point_timing_cost[inet][net_pin] = - timing_place_crit[inet][net_pin] * temp_delay; - delta_timing_cost += temp_point_to_point_timing_cost[inet][net_pin] - - point_to_point_timing_cost[inet][net_pin]; - delta_delay_cost += temp_point_to_point_delay_cost[inet][net_pin] - - point_to_point_delay_cost[inet][net_pin]; - } - } else { /* This net is being driven by a moved block, recompute */ - /* All point to point connections on this net. */ - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { - temp_delay = comp_td_point_to_point_delay(inet, ipin); - temp_point_to_point_delay_cost[inet][ipin] = temp_delay; - - temp_point_to_point_timing_cost[inet][ipin] = - timing_place_crit[inet][ipin] * temp_delay; - delta_timing_cost += temp_point_to_point_timing_cost[inet][ipin] - - point_to_point_timing_cost[inet][ipin]; - delta_delay_cost += temp_point_to_point_delay_cost[inet][ipin] - - point_to_point_delay_cost[inet][ipin]; - - } /* Finished updating the pin */ - } - } /* Finished going through all the pins in the moved block */ - } /* Finished going through all the blocks moved */ - - *delta_timing = delta_timing_cost; - *delta_delay = delta_delay_cost; -} - -static void comp_td_costs(float *timing_cost, float *connection_delay_sum) { - /* Computes the cost (from scratch) due to the delays and criticalities * - * on all point to point connections, we define the timing cost of * - * each connection as criticality*delay. */ - - int inet, ipin; - float loc_timing_cost, loc_connection_delay_sum, temp_delay_cost, - temp_timing_cost; - - loc_timing_cost = 0.; - loc_connection_delay_sum = 0.; - - for (inet = 0; inet < num_nets; inet++) { /* For each net ... */ - if (clb_net[inet].is_global == FALSE) { /* Do only if not global. */ - - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { - - temp_delay_cost = comp_td_point_to_point_delay(inet, ipin); - temp_timing_cost = temp_delay_cost * timing_place_crit[inet][ipin]; - - loc_connection_delay_sum += temp_delay_cost; - point_to_point_delay_cost[inet][ipin] = temp_delay_cost; - temp_point_to_point_delay_cost[inet][ipin] = -1; /* Undefined */ - - point_to_point_timing_cost[inet][ipin] = temp_timing_cost; - temp_point_to_point_timing_cost[inet][ipin] = -1; /* Undefined */ - loc_timing_cost += temp_timing_cost; - } - } - } - - /* Make sure timing cost does not go above MIN_TIMING_COST. */ - *timing_cost = loc_timing_cost; - - *connection_delay_sum = loc_connection_delay_sum; -} - -static float comp_bb_cost(enum cost_methods method) { - - /* Finds the cost from scratch. Done only when the placement * - * has been radically changed (i.e. after initial placement). * - * Otherwise find the cost change incrementally. If method * - * check is NORMAL, we find bounding boxes that are updateable * - * for the larger nets. If method is CHECK, all bounding boxes * - * are found via the non_updateable_bb routine, to provide a * - * cost which can be used to check the correctness of the * - * other routine. */ - - int inet; - float cost; - double expected_wirelength; - - cost = 0; - expected_wirelength = 0.0; - - for (inet = 0; inet < num_nets; inet++) { /* for each net ... */ - - if (clb_net[inet].is_global == FALSE) { /* Do only if not global. */ - - /* Small nets don't use incremental updating on their bounding boxes, * - * so they can use a fast bounding box calculator. */ - - if (clb_net[inet].num_sinks >= SMALL_NET && method == NORMAL) { - get_bb_from_scratch(inet, &bb_coords[inet], - &bb_num_on_edges[inet]); - } else { - get_non_updateable_bb(inet, &bb_coords[inet]); - } - - net_cost[inet] = get_net_cost(inet, &bb_coords[inet]); - cost += net_cost[inet]; - if (method == CHECK) - expected_wirelength += get_net_wirelength_estimate(inet, - &bb_coords[inet]); - } - } - - if (method == CHECK) { - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "BB estimate of min-dist (placement) wirelength: %.0f\n", expected_wirelength); - } - return (cost); -} - -static void free_placement_structs( - float **old_region_occ_x, float **old_region_occ_y, - struct s_placer_opts placer_opts) { - - /* Frees the major structures needed by the placer (and not needed * - * elsewhere). */ - - int inet, imacro; - - free_legal_placements(); - free_fast_cost_update(); - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE - || placer_opts.enable_timing_computations) { - for (inet = 0; inet < num_nets; inet++) { - /*add one to the address since it is indexed from 1 not 0 */ - - point_to_point_delay_cost[inet]++; - free(point_to_point_delay_cost[inet]); - - point_to_point_timing_cost[inet]++; - free(point_to_point_timing_cost[inet]); - - temp_point_to_point_delay_cost[inet]++; - free(temp_point_to_point_delay_cost[inet]); - - temp_point_to_point_timing_cost[inet]++; - free(temp_point_to_point_timing_cost[inet]); - } - free(point_to_point_delay_cost); - free(temp_point_to_point_delay_cost); - - free(point_to_point_timing_cost); - free(temp_point_to_point_timing_cost); - - free_matrix(net_pin_index, 0, num_blocks - 1, 0, sizeof(int)); - } - - free(net_cost); - free(temp_net_cost); - free(bb_num_on_edges); - free(bb_coords); - - free_placement_macros_structs(); - - for (imacro = 0; imacro < num_pl_macros; imacro ++) - free(pl_macros[imacro].members); - free(pl_macros); - - net_cost = NULL; /* Defensive coding. */ - temp_net_cost = NULL; - bb_num_on_edges = NULL; - bb_coords = NULL; - pl_macros = NULL; - - /* Frees up all the data structure used in vpr_utils. */ - free_port_pin_from_blk_pin(); - free_blk_pin_from_port_pin(); - -} - -static void alloc_and_load_placement_structs( - float place_cost_exp, float ***old_region_occ_x, - float ***old_region_occ_y, struct s_placer_opts placer_opts, - t_direct_inf *directs, int num_directs) { - - /* Allocates the major structures needed only by the placer, primarily for * - * computing costs quickly and such. */ - - int inet, ipin, max_pins_per_clb, i; - - alloc_legal_placements(); - load_legal_placements(); - - max_pins_per_clb = 0; - for (i = 0; i < num_types; i++) { - max_pins_per_clb = std::max(max_pins_per_clb, type_descriptors[i].num_pins); - } - - if (placer_opts.place_algorithm == NET_TIMING_DRIVEN_PLACE - || placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE - || placer_opts.enable_timing_computations) { - /* Allocate structures associated with timing driven placement */ - /* [0..num_nets-1][1..num_pins-1] */ - point_to_point_delay_cost = (float **) my_malloc( - num_nets * sizeof(float *)); - temp_point_to_point_delay_cost = (float **) my_malloc( - num_nets * sizeof(float *)); - - point_to_point_timing_cost = (float **) my_malloc( - num_nets * sizeof(float *)); - temp_point_to_point_timing_cost = (float **) my_malloc( - num_nets * sizeof(float *)); - - for (inet = 0; inet < num_nets; inet++) { - - /* In the following, subract one so index starts at * - * 1 instead of 0 */ - point_to_point_delay_cost[inet] = (float *) my_malloc( - clb_net[inet].num_sinks * sizeof(float)); - point_to_point_delay_cost[inet]--; - - temp_point_to_point_delay_cost[inet] = (float *) my_malloc( - clb_net[inet].num_sinks * sizeof(float)); - temp_point_to_point_delay_cost[inet]--; - - point_to_point_timing_cost[inet] = (float *) my_malloc( - clb_net[inet].num_sinks * sizeof(float)); - point_to_point_timing_cost[inet]--; - - temp_point_to_point_timing_cost[inet] = (float *) my_malloc( - clb_net[inet].num_sinks * sizeof(float)); - temp_point_to_point_timing_cost[inet]--; - } - for (inet = 0; inet < num_nets; inet++) { - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { - point_to_point_delay_cost[inet][ipin] = 0; - temp_point_to_point_delay_cost[inet][ipin] = 0; - } - } - } - - net_cost = (float *) my_malloc(num_nets * sizeof(float)); - temp_net_cost = (float *) my_malloc(num_nets * sizeof(float)); - bb_updated_before = (char*)my_calloc(num_nets, sizeof(char)); - - /* Used to store costs for moves not yet made and to indicate when a net's * - * cost has been recomputed. temp_net_cost[inet] < 0 means net's cost hasn't * - * been recomputed. */ - - for (inet = 0; inet < num_nets; inet++){ - bb_updated_before[inet] = NOT_UPDATED_YET; - temp_net_cost[inet] = -1.; - } - - bb_coords = (struct s_bb *) my_malloc(num_nets * sizeof(struct s_bb)); - bb_num_on_edges = (struct s_bb *) my_malloc(num_nets * sizeof(struct s_bb)); - - /* Shouldn't use them; crash hard if I do! */ - *old_region_occ_x = NULL; - *old_region_occ_y = NULL; - - alloc_and_load_for_fast_cost_update(place_cost_exp); - - net_pin_index = alloc_and_load_net_pin_index(); - - alloc_and_load_try_swap_structs(); - - num_pl_macros = alloc_and_load_placement_macros(directs, num_directs, &pl_macros); -} - -static void alloc_and_load_try_swap_structs() { - /* Allocate the local bb_coordinate storage, etc. only once. */ - /* Allocate with size num_nets for any number of nets affected. */ - ts_bb_coord_new = (struct s_bb *) my_calloc( - num_nets, sizeof(struct s_bb)); - ts_bb_edge_new = (struct s_bb *) my_calloc( - num_nets, sizeof(struct s_bb)); - ts_nets_to_update = (int *) my_calloc(num_nets, sizeof(int)); - - /* Allocate with size num_blocks for any number of moved block. */ - blocks_affected.moved_blocks = (t_pl_moved_block*)my_calloc( - num_blocks, sizeof(t_pl_moved_block) ); - blocks_affected.num_moved_blocks = 0; - -} - -static void get_bb_from_scratch(int inet, struct s_bb *coords, - struct s_bb *num_on_edges) { - - /* This routine finds the bounding box of each net from scratch (i.e. * - * from only the block location information). It updates both the * - * coordinate and number of pins on each edge information. It * - * should only be called when the bounding box information is not valid. */ - - int ipin, bnum, pnum, x, y, xmin, xmax, ymin, ymax; - int xmin_edge, xmax_edge, ymin_edge, ymax_edge; - int n_pins; - - n_pins = clb_net[inet].num_sinks + 1; - - bnum = clb_net[inet].node_block[0]; - pnum = clb_net[inet].node_block_pin[0]; - - x = block[bnum].x; - y = block[bnum].y + block[bnum].type->pin_height[pnum]; - - x = std::max(std::min(x, nx), 1); - y = std::max(std::min(y, ny), 1); - - xmin = x; - ymin = y; - xmax = x; - ymax = y; - xmin_edge = 1; - ymin_edge = 1; - xmax_edge = 1; - ymax_edge = 1; - - for (ipin = 1; ipin < n_pins; ipin++) { - bnum = clb_net[inet].node_block[ipin]; - pnum = clb_net[inet].node_block_pin[ipin]; - x = block[bnum].x; - y = block[bnum].y + block[bnum].type->pin_height[pnum]; - - /* Code below counts IO blocks as being within the 1..nx, 1..ny clb array. * - * This is because channels do not go out of the 0..nx, 0..ny range, and * - * I always take all channels impinging on the bounding box to be within * - * that bounding box. Hence, this "movement" of IO blocks does not affect * - * the which channels are included within the bounding box, and it * - * simplifies the code a lot. */ - - x = std::max(std::min(x, nx), 1); - y = std::max(std::min(y, ny), 1); - - if (x == xmin) { - xmin_edge++; - } - if (x == xmax) { /* Recall that xmin could equal xmax -- don't use else */ - xmax_edge++; - } else if (x < xmin) { - xmin = x; - xmin_edge = 1; - } else if (x > xmax) { - xmax = x; - xmax_edge = 1; - } - - if (y == ymin) { - ymin_edge++; - } - if (y == ymax) { - ymax_edge++; - } else if (y < ymin) { - ymin = y; - ymin_edge = 1; - } else if (y > ymax) { - ymax = y; - ymax_edge = 1; - } - } - - /* Copy the coordinates and number on edges information into the proper * - * structures. */ - coords->xmin = xmin; - coords->xmax = xmax; - coords->ymin = ymin; - coords->ymax = ymax; - - num_on_edges->xmin = xmin_edge; - num_on_edges->xmax = xmax_edge; - num_on_edges->ymin = ymin_edge; - num_on_edges->ymax = ymax_edge; -} - -static double get_net_wirelength_estimate(int inet, struct s_bb *bbptr) { - - /* WMF: Finds the estimate of wirelength due to one net by looking at * - * its coordinate bounding box. */ - - double ncost, crossing; - - /* Get the expected "crossing count" of a net, based on its number * - * of pins. Extrapolate for very large nets. */ - - if (((clb_net[inet].num_sinks + 1) > 50) - && ((clb_net[inet].num_sinks + 1) < 85)) { - crossing = 2.7933 + 0.02616 * ((clb_net[inet].num_sinks + 1) - 50); - } else if ((clb_net[inet].num_sinks + 1) >= 85) { - crossing = 2.7933 + 0.011 * (clb_net[inet].num_sinks + 1) - - 0.0000018 * (clb_net[inet].num_sinks + 1) - * (clb_net[inet].num_sinks + 1); - } else { - crossing = cross_count[(clb_net[inet].num_sinks + 1) - 1]; - } - - /* Could insert a check for xmin == xmax. In that case, assume * - * connection will be made with no bends and hence no x-cost. * - * Same thing for y-cost. */ - - /* Cost = wire length along channel * cross_count / average * - * channel capacity. Do this for x, then y direction and add. */ - - ncost = (bbptr->xmax - bbptr->xmin + 1) * crossing; - - ncost += (bbptr->ymax - bbptr->ymin + 1) * crossing; - - return (ncost); -} - -static float get_net_cost(int inet, struct s_bb *bbptr) { - - /* Finds the cost due to one net by looking at its coordinate bounding * - * box. */ - - float ncost, crossing; - - /* Get the expected "crossing count" of a net, based on its number * - * of pins. Extrapolate for very large nets. */ - - if ((clb_net[inet].num_sinks + 1) > 50) { - crossing = 2.7933 + 0.02616 * ((clb_net[inet].num_sinks + 1) - 50); - /* crossing = 3.0; Old value */ - } else { - crossing = cross_count[(clb_net[inet].num_sinks + 1) - 1]; - } - - /* Could insert a check for xmin == xmax. In that case, assume * - * connection will be made with no bends and hence no x-cost. * - * Same thing for y-cost. */ - - /* Cost = wire length along channel * cross_count / average * - * channel capacity. Do this for x, then y direction and add. */ - - ncost = (bbptr->xmax - bbptr->xmin + 1) * crossing - * chanx_place_cost_fac[bbptr->ymax][bbptr->ymin - 1]; - - ncost += (bbptr->ymax - bbptr->ymin + 1) * crossing - * chany_place_cost_fac[bbptr->xmax][bbptr->xmin - 1]; - - return (ncost); -} - -static void get_non_updateable_bb(int inet, struct s_bb *bb_coord_new) { - - /* Finds the bounding box of a net and stores its coordinates in the * - * bb_coord_new data structure. This routine should only be called * - * for small nets, since it does not determine enough information for * - * the bounding box to be updated incrementally later. * - * Currently assumes channels on both sides of the CLBs forming the * - * edges of the bounding box can be used. Essentially, I am assuming * - * the pins always lie on the outside of the bounding box. */ - - int k, xmax, ymax, xmin, ymin, x, y; - int bnum, pnum; - - bnum = clb_net[inet].node_block[0]; - pnum = clb_net[inet].node_block_pin[0]; - x = block[bnum].x; - y = block[bnum].y + block[bnum].type->pin_height[pnum]; - - xmin = x; - ymin = y; - xmax = x; - ymax = y; - - for (k = 1; k < (clb_net[inet].num_sinks + 1); k++) { - bnum = clb_net[inet].node_block[k]; - pnum = clb_net[inet].node_block_pin[k]; - x = block[bnum].x; - y = block[bnum].y + block[bnum].type->pin_height[pnum]; - - if (x < xmin) { - xmin = x; - } else if (x > xmax) { - xmax = x; - } - - if (y < ymin) { - ymin = y; - } else if (y > ymax) { - ymax = y; - } - } - - /* Now I've found the coordinates of the bounding box. There are no * - * channels beyond nx and ny, so I want to clip to that. As well, * - * since I'll always include the channel immediately below and the * - * channel immediately to the left of the bounding box, I want to * - * clip to 1 in both directions as well (since minimum channel index * - * is 0). See route.c for a channel diagram. */ - - bb_coord_new->xmin = std::max(std::min(xmin, nx), 1); - bb_coord_new->ymin = std::max(std::min(ymin, ny), 1); - bb_coord_new->xmax = std::max(std::min(xmax, nx), 1); - bb_coord_new->ymax = std::max(std::min(ymax, ny), 1); -} - -static void update_bb(int inet, struct s_bb *bb_coord_new, - struct s_bb *bb_edge_new, int xold, int yold, int xnew, int ynew) { - - /* Updates the bounding box of a net by storing its coordinates in * - * the bb_coord_new data structure and the number of blocks on each * - * edge in the bb_edge_new data structure. This routine should only * - * be called for large nets, since it has some overhead relative to * - * just doing a brute force bounding box calculation. The bounding * - * box coordinate and edge information for inet must be valid before * - * this routine is called. * - * Currently assumes channels on both sides of the CLBs forming the * - * edges of the bounding box can be used. Essentially, I am assuming * - * the pins always lie on the outside of the bounding box. * - * The x and y coordinates are the pin's x and y coordinates. */ - /* IO blocks are considered to be one cell in for simplicity. */ - - struct s_bb *curr_bb_edge, *curr_bb_coord; - - xnew = std::max(std::min(xnew, nx), 1); - ynew = std::max(std::min(ynew, ny), 1); - xold = std::max(std::min(xold, nx), 1); - yold = std::max(std::min(yold, ny), 1); - - /* Check if the net had been updated before. */ - if (bb_updated_before[inet] == GOT_FROM_SCRATCH) - { /* The net had been updated from scratch, DO NOT update again! */ - return; - } - else if (bb_updated_before[inet] == NOT_UPDATED_YET) - { /* The net had NOT been updated before, could use the old values */ - curr_bb_coord = &bb_coords[inet]; - curr_bb_edge = &bb_num_on_edges[inet]; - bb_updated_before[inet] = UPDATED_ONCE; - } - else - { /* The net had been updated before, must use the new values */ - curr_bb_coord = bb_coord_new; - curr_bb_edge = bb_edge_new; - } - - /* Check if I can update the bounding box incrementally. */ - - if (xnew < xold) { /* Move to left. */ - - /* Update the xmax fields for coordinates and number of edges first. */ - - if (xold == curr_bb_coord->xmax) { /* Old position at xmax. */ - if (curr_bb_edge->xmax == 1) { - get_bb_from_scratch(inet, bb_coord_new, bb_edge_new); - bb_updated_before[inet] = GOT_FROM_SCRATCH; - return; - } else { - bb_edge_new->xmax = curr_bb_edge->xmax - 1; - bb_coord_new->xmax = curr_bb_coord->xmax; - } - } - - else { /* Move to left, old postion was not at xmax. */ - bb_coord_new->xmax = curr_bb_coord->xmax; - bb_edge_new->xmax = curr_bb_edge->xmax; - } - - /* Now do the xmin fields for coordinates and number of edges. */ - - if (xnew < curr_bb_coord->xmin) { /* Moved past xmin */ - bb_coord_new->xmin = xnew; - bb_edge_new->xmin = 1; - } - - else if (xnew == curr_bb_coord->xmin) { /* Moved to xmin */ - bb_coord_new->xmin = xnew; - bb_edge_new->xmin = curr_bb_edge->xmin + 1; - } - - else { /* Xmin unchanged. */ - bb_coord_new->xmin = curr_bb_coord->xmin; - bb_edge_new->xmin = curr_bb_edge->xmin; - } - } - - /* End of move to left case. */ - else if (xnew > xold) { /* Move to right. */ - - /* Update the xmin fields for coordinates and number of edges first. */ - - if (xold == curr_bb_coord->xmin) { /* Old position at xmin. */ - if (curr_bb_edge->xmin == 1) { - get_bb_from_scratch(inet, bb_coord_new, bb_edge_new); - bb_updated_before[inet] = GOT_FROM_SCRATCH; - return; - } else { - bb_edge_new->xmin = curr_bb_edge->xmin - 1; - bb_coord_new->xmin = curr_bb_coord->xmin; - } - } - - else { /* Move to right, old position was not at xmin. */ - bb_coord_new->xmin = curr_bb_coord->xmin; - bb_edge_new->xmin = curr_bb_edge->xmin; - } - - /* Now do the xmax fields for coordinates and number of edges. */ - - if (xnew > curr_bb_coord->xmax) { /* Moved past xmax. */ - bb_coord_new->xmax = xnew; - bb_edge_new->xmax = 1; - } - - else if (xnew == curr_bb_coord->xmax) { /* Moved to xmax */ - bb_coord_new->xmax = xnew; - bb_edge_new->xmax = curr_bb_edge->xmax + 1; - } - - else { /* Xmax unchanged. */ - bb_coord_new->xmax = curr_bb_coord->xmax; - bb_edge_new->xmax = curr_bb_edge->xmax; - } - } - /* End of move to right case. */ - else { /* xnew == xold -- no x motion. */ - bb_coord_new->xmin = curr_bb_coord->xmin; - bb_coord_new->xmax = curr_bb_coord->xmax; - bb_edge_new->xmin = curr_bb_edge->xmin; - bb_edge_new->xmax = curr_bb_edge->xmax; - } - - /* Now account for the y-direction motion. */ - - if (ynew < yold) { /* Move down. */ - - /* Update the ymax fields for coordinates and number of edges first. */ - - if (yold == curr_bb_coord->ymax) { /* Old position at ymax. */ - if (curr_bb_edge->ymax == 1) { - get_bb_from_scratch(inet, bb_coord_new, bb_edge_new); - bb_updated_before[inet] = GOT_FROM_SCRATCH; - return; - } else { - bb_edge_new->ymax = curr_bb_edge->ymax - 1; - bb_coord_new->ymax = curr_bb_coord->ymax; - } - } - - else { /* Move down, old postion was not at ymax. */ - bb_coord_new->ymax = curr_bb_coord->ymax; - bb_edge_new->ymax = curr_bb_edge->ymax; - } - - /* Now do the ymin fields for coordinates and number of edges. */ - - if (ynew < curr_bb_coord->ymin) { /* Moved past ymin */ - bb_coord_new->ymin = ynew; - bb_edge_new->ymin = 1; - } - - else if (ynew == curr_bb_coord->ymin) { /* Moved to ymin */ - bb_coord_new->ymin = ynew; - bb_edge_new->ymin = curr_bb_edge->ymin + 1; - } - - else { /* ymin unchanged. */ - bb_coord_new->ymin = curr_bb_coord->ymin; - bb_edge_new->ymin = curr_bb_edge->ymin; - } - } - /* End of move down case. */ - else if (ynew > yold) { /* Moved up. */ - - /* Update the ymin fields for coordinates and number of edges first. */ - - if (yold == curr_bb_coord->ymin) { /* Old position at ymin. */ - if (curr_bb_edge->ymin == 1) { - get_bb_from_scratch(inet, bb_coord_new, bb_edge_new); - bb_updated_before[inet] = GOT_FROM_SCRATCH; - return; - } else { - bb_edge_new->ymin = curr_bb_edge->ymin - 1; - bb_coord_new->ymin = curr_bb_coord->ymin; - } - } - - else { /* Moved up, old position was not at ymin. */ - bb_coord_new->ymin = curr_bb_coord->ymin; - bb_edge_new->ymin = curr_bb_edge->ymin; - } - - /* Now do the ymax fields for coordinates and number of edges. */ - - if (ynew > curr_bb_coord->ymax) { /* Moved past ymax. */ - bb_coord_new->ymax = ynew; - bb_edge_new->ymax = 1; - } - - else if (ynew == curr_bb_coord->ymax) { /* Moved to ymax */ - bb_coord_new->ymax = ynew; - bb_edge_new->ymax = curr_bb_edge->ymax + 1; - } - - else { /* ymax unchanged. */ - bb_coord_new->ymax = curr_bb_coord->ymax; - bb_edge_new->ymax = curr_bb_edge->ymax; - } - } - /* End of move up case. */ - else { /* ynew == yold -- no y motion. */ - bb_coord_new->ymin = curr_bb_coord->ymin; - bb_coord_new->ymax = curr_bb_coord->ymax; - bb_edge_new->ymin = curr_bb_edge->ymin; - bb_edge_new->ymax = curr_bb_edge->ymax; - } - - if (bb_updated_before[inet] == NOT_UPDATED_YET) - bb_updated_before[inet] = UPDATED_ONCE; -} - -static void alloc_legal_placements() { - int i, j, k; - - legal_pos = (t_legal_pos **) my_malloc(num_types * sizeof(t_legal_pos *)); - num_legal_pos = (int *) my_calloc(num_types, sizeof(int)); - - /* Initialize all occupancy to zero. */ - - for (i = 0; i <= nx + 1; i++) { - for (j = 0; j <= ny + 1; j++) { - grid[i][j].usage = 0; - for (k = 0; k < grid[i][j].type->capacity; k++) { - grid[i][j].blocks[k] = EMPTY; - if (grid[i][j].offset == 0) { - num_legal_pos[grid[i][j].type->index]++; - } - } - } - } - - for (i = 0; i < num_types; i++) { - legal_pos[i] = (t_legal_pos *) my_malloc(num_legal_pos[i] * sizeof(t_legal_pos)); - } -} - -static void load_legal_placements() { - int i, j, k, itype; - int *index; - - index = (int *) my_calloc(num_types, sizeof(int)); - - for (i = 0; i <= nx + 1; i++) { - for (j = 0; j <= ny + 1; j++) { - for (k = 0; k < grid[i][j].type->capacity; k++) { - if (grid[i][j].offset == 0) { - itype = grid[i][j].type->index; - legal_pos[itype][index[itype]].x = i; - legal_pos[itype][index[itype]].y = j; - legal_pos[itype][index[itype]].z = k; - index[itype]++; - } - } - } - } - free(index); -} - -static void free_legal_placements() { - int i; - for (i = 0; i < num_types; i++) { - free(legal_pos[i]); - } - free(legal_pos); /* Free the mapping list */ - free(num_legal_pos); -} - - - -static int check_macro_can_be_placed(int imacro, int itype, int x, int y, int z) { - - int imember; - int member_x, member_y, member_z; - - // Every macro can be placed until proven otherwise - int macro_can_be_placed = TRUE; - - // Check whether all the members can be placed - for (imember = 0; imember < pl_macros[imacro].num_blocks; imember++) { - member_x = x + pl_macros[imacro].members[imember].x_offset; - member_y = y + pl_macros[imacro].members[imember].y_offset; - member_z = z + pl_macros[imacro].members[imember].z_offset; - - // Check whether the location could accept block of this type - // Then check whether the location could still accomodate more blocks - // Also check whether the member position is valid, that is the member's location - // still within the chip's dimemsion and the member_z is allowed at that location on the grid - if (member_x <= nx+1 && member_y <= ny+1 - && grid[member_x][member_y].type->index == itype - && grid[member_x][member_y].blocks[member_z] == OPEN) { - // Can still accomodate blocks here, check the next position - continue; - } else { - // Cant be placed here - skip to the next try - macro_can_be_placed = FALSE; - break; - } - } - - return (macro_can_be_placed); -} - - -static int try_place_macro(int itype, int ichoice, int imacro, int * free_locations){ - - int x, y, z, member_x, member_y, member_z, imember; - - int macro_placed = FALSE; - - // Choose a random position for the head - x = legal_pos[itype][ichoice].x; - y = legal_pos[itype][ichoice].y; - z = legal_pos[itype][ichoice].z; - - // If that location is occupied, do nothing. - if (grid[x][y].blocks[z] != OPEN) { - return (macro_placed); - } - - int macro_can_be_placed = check_macro_can_be_placed(imacro, itype, x, y, z); - - if (macro_can_be_placed == TRUE) { - - // Place down the macro - macro_placed = TRUE; - for (imember = 0; imember < pl_macros[imacro].num_blocks; imember++) { - - member_x = x + pl_macros[imacro].members[imember].x_offset; - member_y = y + pl_macros[imacro].members[imember].y_offset; - member_z = z + pl_macros[imacro].members[imember].z_offset; - - block[pl_macros[imacro].members[imember].blk_index].x = member_x; - block[pl_macros[imacro].members[imember].blk_index].y = member_y; - block[pl_macros[imacro].members[imember].blk_index].z = member_z; - - grid[member_x][member_y].blocks[member_z] = pl_macros[imacro].members[imember].blk_index; - grid[member_x][member_y].usage++; - - // Could not ensure that the randomiser would not pick this location again - // So, would have to do a lazy removal - whenever I come across a block that could not be placed, - // go ahead and remove it from the legal_pos[][] array - - } // Finish placing all the members in the macro - - } // End of this choice of legal_pos - - return (macro_placed); - -} - - -static void initial_placement_pl_macros(int macros_max_num_tries, int * free_locations) { - - int macro_placed; - int imacro, iblk, itype, itry, ichoice; - - /* Macros are harder to place. Do them first */ - for (imacro = 0; imacro < num_pl_macros; imacro++) { - - // Every macro are not placed in the beginnning - macro_placed = FALSE; - - // Assume that all the blocks in the macro are of the same type - iblk = pl_macros[imacro].members[0].blk_index; - itype = block[iblk].type->index; - if (free_locations[itype] < pl_macros[imacro].num_blocks) { - vpr_printf (TIO_MESSAGE_ERROR, "Initial placement failed.\n"); - vpr_printf (TIO_MESSAGE_ERROR, "Could not place macro length %d with head block %s (#%d); not enough free locations of type %s (#%d).\n", - pl_macros[imacro].num_blocks, block[iblk].name, iblk, type_descriptors[itype].name, itype); - vpr_printf (TIO_MESSAGE_INFO, "VPR cannot auto-size for your circuit, please resize the FPGA manually.\n"); - exit(1); - } - - // Try to place the macro first, if can be placed - place them, otherwise try again - for (itry = 0; itry < macros_max_num_tries && macro_placed == FALSE; itry++) { - - // Choose a random position for the head - ichoice = my_irand(free_locations[itype] - 1); - - // Try to place the macro - macro_placed = try_place_macro(itype, ichoice, imacro, free_locations); - - } // Finished all tries - - - if (macro_placed == FALSE){ - // if a macro still could not be placed after macros_max_num_tries times, - // go through the chip exhaustively to find a legal placement for the macro - // place the macro on the first location that is legal - // then set macro_placed = TRUE; - // if there are no legal positions, error out - - // Exhaustive placement of carry macros - for (ichoice = 0; ichoice < free_locations[itype] && macro_placed == FALSE; ichoice++) { - - // Try to place the macro - macro_placed = try_place_macro(itype, ichoice, imacro, free_locations); - - } // Exhausted all the legal placement position for this macro - - // If macro could not be placed after exhaustive placement, error out - if (macro_placed == FALSE) { - // Error out - vpr_printf (TIO_MESSAGE_ERROR, "Initial placement failed.\n"); - vpr_printf (TIO_MESSAGE_ERROR, "Could not place macro length %d with head block %s (#%d); not enough free locations of type %s (#%d).\n", - pl_macros[imacro].num_blocks, block[iblk].name, iblk, type_descriptors[itype].name, itype); - vpr_printf (TIO_MESSAGE_INFO, "Please manually size the FPGA because VPR can't do this yet.\n"); - exit(1); - } - - } else { - // This macro has been placed successfully, proceed to place the next macro - continue; - } - } // Finish placing all the pl_macros successfully -} - -static void initial_placement_blocks(int * free_locations, enum e_pad_loc_type pad_loc_type) { - - /* Place blocks that are NOT a part of any macro. - * We'll randomly place each block in the clustered netlist, one by one. - */ - - int iblk, itype; - int ichoice, x, y, z; - - for (iblk = 0; iblk < num_blocks; iblk++) { - - if (block[iblk].x != -1) { - // block placed. - continue; - } - /* Don't do IOs if the user specifies IOs; we'll read those locations later. */ - if (!(block[iblk].type == IO_TYPE && pad_loc_type == USER)) { - - /* Randomly select a free location of the appropriate type - * for iblk. We have a linearized list of all the free locations - * that can accomodate a block of that type in free_locations[itype]. - * Choose one randomly and put iblk there. Then we don't want to pick that - * location again, so remove it from the free_locations array. - */ - itype = block[iblk].type->index; - if (free_locations[itype] <= 0) { - vpr_printf (TIO_MESSAGE_ERROR, "Initial placement failed.\n"); - vpr_printf (TIO_MESSAGE_ERROR, "Could not place block %s (#%d); no free locations of type %s (#%d).\n", - block[iblk].name, iblk, type_descriptors[itype].name, itype); - exit(1); - } - - ichoice = my_irand(free_locations[itype] - 1); - x = legal_pos[itype][ichoice].x; - y = legal_pos[itype][ichoice].y; - z = legal_pos[itype][ichoice].z; - - // Make sure that the position is OPEN before placing the block down - assert (grid[x][y].blocks[z] == OPEN); - - grid[x][y].blocks[z] = iblk; - grid[x][y].usage++; - - block[iblk].x = x; - block[iblk].y = y; - block[iblk].z = z; - - /* Ensure randomizer doesn't pick this location again, since it's occupied. Could shift all the - * legal positions in legal_pos to remove the entry (choice) we just used, but faster to - * just move the last entry in legal_pos to the spot we just used and decrement the - * count of free_locations. - */ - legal_pos[itype][ichoice] = legal_pos[itype][free_locations[itype] - 1]; /* overwrite used block position */ - free_locations[itype]--; - - } - } -} - -static void initial_placement(enum e_pad_loc_type pad_loc_type, - char *pad_loc_file) { - - /* Randomly places the blocks to create an initial placement. We rely on - * the legal_pos array already being loaded. That legal_pos[itype] is an - * array that gives every legal value of (x,y,z) that can accomodate a block. - * The number of such locations is given by num_legal_pos[itype]. - */ - int i, j, k, iblk, itype, x, y, z, ichoice; - int *free_locations; /* [0..num_types-1]. - * Stores how many locations there are for this type that *might* still be free. - * That is, this stores the number of entries in legal_pos[itype] that are worth considering - * as you look for a free location. - */ - - free_locations = (int *) my_malloc(num_types * sizeof(int)); - for (itype = 0; itype < num_types; itype++) { - free_locations[itype] = num_legal_pos[itype]; - } - - /* We'll use the grid to record where everything goes. Initialize to the grid has no - * blocks placed anywhere. - */ - for (i = 0; i <= nx + 1; i++) { - for (j = 0; j <= ny + 1; j++) { - grid[i][j].usage = 0; - itype = grid[i][j].type->index; - for (k = 0; k < type_descriptors[itype].capacity; k++) { - grid[i][j].blocks[k] = OPEN; - } - } - } - - /* Similarly, mark all blocks as not being placed yet. */ - for (iblk = 0; iblk < num_blocks; iblk++) { - block[iblk].x = -1; - block[iblk].y = -1; - block[iblk].z = -1; - } - - initial_placement_pl_macros(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, free_locations); - - // All the macros are placed, update the legal_pos[][] array - for (itype = 0; itype < num_types; itype++) { - assert (free_locations[itype] >= 0); - for (ichoice = 0; ichoice < free_locations[itype]; ichoice++) { - x = legal_pos[itype][ichoice].x; - y = legal_pos[itype][ichoice].y; - z = legal_pos[itype][ichoice].z; - - // Check if that location is occupied. If it is, remove from legal_pos - if (grid[x][y].blocks[z] != OPEN) { - legal_pos[itype][ichoice] = legal_pos[itype][free_locations[itype] - 1]; - free_locations[itype]--; - - // After the move, I need to check this particular entry again - ichoice--; - continue; - } - } - } // Finish updating the legal_pos[][] and free_locations[] array - - initial_placement_blocks(free_locations, pad_loc_type); - - if (pad_loc_type == USER) { - read_user_pad_loc(pad_loc_file); - } - - /* Restore legal_pos */ - load_legal_placements(); - -#ifdef VERBOSE - vpr_printf(TIO_MESSAGE_INFO, "At end of initial_placement.\n"); - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_INITIAL_CLB_PLACEMENT)) { - print_clb_placement(getEchoFileName(E_ECHO_INITIAL_CLB_PLACEMENT)); - } -#endif - free(free_locations); -} - -static void free_fast_cost_update(void) { - int i; - - for (i = 0; i <= ny; i++) - free(chanx_place_cost_fac[i]); - free(chanx_place_cost_fac); - chanx_place_cost_fac = NULL; - - for (i = 0; i <= nx; i++) - free(chany_place_cost_fac[i]); - free(chany_place_cost_fac); - chany_place_cost_fac = NULL; -} - -static void alloc_and_load_for_fast_cost_update(float place_cost_exp) { - - /* Allocates and loads the chanx_place_cost_fac and chany_place_cost_fac * - * arrays with the inverse of the average number of tracks per channel * - * between [subhigh] and [sublow]. This is only useful for the cost * - * function that takes the length of the net bounding box in each * - * dimension divided by the average number of tracks in that direction. * - * For other cost functions, you don't have to bother calling this * - * routine; when using the cost function described above, however, you * - * must always call this routine after you call init_chan and before * - * you do any placement cost determination. The place_cost_exp factor * - * specifies to what power the width of the channel should be taken -- * - * larger numbers make narrower channels more expensive. */ - - int low, high, i; - - /* Access arrays below as chan?_place_cost_fac[subhigh][sublow]. Since * - * subhigh must be greater than or equal to sublow, we only need to * - * allocate storage for the lower half of a matrix. */ - - chanx_place_cost_fac = (float **) my_malloc((ny + 1) * sizeof(float *)); - for (i = 0; i <= ny; i++) - chanx_place_cost_fac[i] = (float *) my_malloc((i + 1) * sizeof(float)); - - chany_place_cost_fac = (float **) my_malloc((nx + 1) * sizeof(float *)); - for (i = 0; i <= nx; i++) - chany_place_cost_fac[i] = (float *) my_malloc((i + 1) * sizeof(float)); - - /* First compute the number of tracks between channel high and channel * - * low, inclusive, in an efficient manner. */ - - chanx_place_cost_fac[0][0] = chan_width_x[0]; - - for (high = 1; high <= ny; high++) { - chanx_place_cost_fac[high][high] = chan_width_x[high]; - for (low = 0; low < high; low++) { - chanx_place_cost_fac[high][low] = - chanx_place_cost_fac[high - 1][low] + chan_width_x[high]; - } - } - - /* Now compute the inverse of the average number of tracks per channel * - * between high and low. The cost function divides by the average * - * number of tracks per channel, so by storing the inverse I convert * - * this to a faster multiplication. Take this final number to the * - * place_cost_exp power -- numbers other than one mean this is no * - * longer a simple "average number of tracks"; it is some power of * - * that, allowing greater penalization of narrow channels. */ - - for (high = 0; high <= ny; high++) - for (low = 0; low <= high; low++) { - chanx_place_cost_fac[high][low] = (high - low + 1.) - / chanx_place_cost_fac[high][low]; - chanx_place_cost_fac[high][low] = pow( - (double) chanx_place_cost_fac[high][low], - (double) place_cost_exp); - } - - /* Now do the same thing for the y-directed channels. First get the * - * number of tracks between channel high and channel low, inclusive. */ - - chany_place_cost_fac[0][0] = chan_width_y[0]; - - for (high = 1; high <= nx; high++) { - chany_place_cost_fac[high][high] = chan_width_y[high]; - for (low = 0; low < high; low++) { - chany_place_cost_fac[high][low] = - chany_place_cost_fac[high - 1][low] + chan_width_y[high]; - } - } - - /* Now compute the inverse of the average number of tracks per channel * - * between high and low. Take to specified power. */ - - for (high = 0; high <= nx; high++) - for (low = 0; low <= high; low++) { - chany_place_cost_fac[high][low] = (high - low + 1.) - / chany_place_cost_fac[high][low]; - chany_place_cost_fac[high][low] = pow( - (double) chany_place_cost_fac[high][low], - (double) place_cost_exp); - } -} - -static void check_place(float bb_cost, float timing_cost, - enum e_place_algorithm place_algorithm, - float delay_cost) { - - /* Checks that the placement has not confused our data structures. * - * i.e. the clb and block structures agree about the locations of * - * every block, blocks are in legal spots, etc. Also recomputes * - * the final placement cost from scratch and makes sure it is * - * within roundoff of what we think the cost is. */ - - static int *bdone; - int i, j, k, error = 0, bnum; - float bb_cost_check; - int usage_check; - float timing_cost_check, delay_cost_check; - int imacro, imember, head_iblk, member_iblk, member_x, member_y, member_z; - - bb_cost_check = comp_bb_cost(CHECK); - vpr_printf(TIO_MESSAGE_INFO, "bb_cost recomputed from scratch: %g\n", bb_cost_check); - if (fabs(bb_cost_check - bb_cost) > bb_cost * ERROR_TOL) { - vpr_printf(TIO_MESSAGE_ERROR, "bb_cost_check: %g and bb_cost: %g differ in check_place.\n", bb_cost_check, bb_cost); - error++; - } - - if (place_algorithm == NET_TIMING_DRIVEN_PLACE - || place_algorithm == PATH_TIMING_DRIVEN_PLACE) { - comp_td_costs(&timing_cost_check, &delay_cost_check); - vpr_printf(TIO_MESSAGE_INFO, "timing_cost recomputed from scratch: %g\n", timing_cost_check); - if (fabs(timing_cost_check - timing_cost) > timing_cost * ERROR_TOL) { - vpr_printf(TIO_MESSAGE_ERROR, "timing_cost_check: %g and timing_cost: %g differ in check_place.\n", - timing_cost_check, timing_cost); - error++; - } - vpr_printf(TIO_MESSAGE_INFO, "delay_cost recomputed from scratch: %g\n", delay_cost_check); - if (fabs(delay_cost_check - delay_cost) > delay_cost * ERROR_TOL) { - vpr_printf(TIO_MESSAGE_ERROR, "delay_cost_check: %g and delay_cost: %g differ in check_place.\n", - delay_cost_check, delay_cost); - error++; - } - } - - bdone = (int *) my_malloc(num_blocks * sizeof(int)); - for (i = 0; i < num_blocks; i++) - bdone[i] = 0; - - /* Step through grid array. Check it against block array. */ - for (i = 0; i <= (nx + 1); i++) - for (j = 0; j <= (ny + 1); j++) { - if (grid[i][j].usage > grid[i][j].type->capacity) { - vpr_printf(TIO_MESSAGE_ERROR, "Block at grid location (%d,%d) overused. Usage is %d.\n", - i, j, grid[i][j].usage); - error++; - } - usage_check = 0; - for (k = 0; k < grid[i][j].type->capacity; k++) { - bnum = grid[i][j].blocks[k]; - if (EMPTY == bnum) - continue; - - if (block[bnum].type != grid[i][j].type) { - vpr_printf(TIO_MESSAGE_ERROR, "Block %d type does not match grid location (%d,%d) type.\n", - bnum, i, j); - error++; - } - if ((block[bnum].x != i) || (block[bnum].y != j)) { - vpr_printf(TIO_MESSAGE_ERROR, "Block %d location conflicts with grid(%d,%d) data.\n", - bnum, i, j); - error++; - } - ++usage_check; - bdone[bnum]++; - } - if (usage_check != grid[i][j].usage) { - vpr_printf(TIO_MESSAGE_ERROR, "Location (%d,%d) usage is %d, but has actual usage %d.\n", - i, j, grid[i][j].usage, usage_check); - error++; - } - } - - /* Check that every block exists in the grid and block arrays somewhere. */ - for (i = 0; i < num_blocks; i++) - if (bdone[i] != 1) { - vpr_printf(TIO_MESSAGE_ERROR, "Block %d listed %d times in data structures.\n", - i, bdone[i]); - error++; - } - free(bdone); - - /* Check the pl_macro placement are legal - blocks are in the proper relative position. */ - for (imacro = 0; imacro < num_pl_macros; imacro++) { - - head_iblk = pl_macros[imacro].members[0].blk_index; - - for (imember = 0; imember < pl_macros[imacro].num_blocks; imember++) { - - member_iblk = pl_macros[imacro].members[imember].blk_index; - - // Compute the suppossed member's x,y,z location - member_x = block[head_iblk].x + pl_macros[imacro].members[imember].x_offset; - member_y = block[head_iblk].y + pl_macros[imacro].members[imember].y_offset; - member_z = block[head_iblk].z + pl_macros[imacro].members[imember].z_offset; - - // Check the block data structure first - if (block[member_iblk].x != member_x - || block[member_iblk].y != member_y - || block[member_iblk].z != member_z) { - vpr_printf(TIO_MESSAGE_ERROR, "Block %d in pl_macro #%d is not placed in the proper orientation.\n", - member_iblk, imacro); - error++; - } - - // Then check the grid data structure - if (grid[member_x][member_y].blocks[member_z] != member_iblk) { - vpr_printf(TIO_MESSAGE_ERROR, "Block %d in pl_macro #%d is not placed in the proper orientation.\n", - member_iblk, imacro); - error++; - } - } // Finish going through all the members - } // Finish going through all the macros - - if (error == 0) { - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Completed placement consistency check successfully.\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Swaps called: %d\n", num_ts_called); - -#ifdef PRINT_REL_POS_DISTR - print_relative_pos_distr(void); -#endif - } else { - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_ERROR, "Completed placement consistency check, %d errors found.\n", error); - vpr_printf(TIO_MESSAGE_INFO, "Aborting program.\n"); - exit(1); - } - -} - -#ifdef VERBOSE -static void print_clb_placement(const char *fname) { - - /* Prints out the clb placements to a file. */ - - FILE *fp; - int i; - - fp = my_fopen(fname, "w", 0); - fprintf(fp, "Complex block placements:\n\n"); - - fprintf(fp, "Block #\tName\t(X, Y, Z).\n"); - for(i = 0; i < num_blocks; i++) { - fprintf(fp, "#%d\t%s\t(%d, %d, %d).\n", i, block[i].name, block[i].x, block[i].y, block[i].z); - } - - fclose(fp); -} -#endif - -static void free_try_swap_arrays(void) { - if(ts_bb_coord_new != NULL) { - free(ts_bb_coord_new); - free(ts_bb_edge_new); - free(ts_nets_to_update); - free(blocks_affected.moved_blocks); - free(bb_updated_before); - - ts_bb_coord_new = NULL; - ts_bb_edge_new = NULL; - ts_nets_to_update = NULL; - blocks_affected.moved_blocks = NULL; - blocks_affected.num_moved_blocks = 0; - bb_updated_before = NULL; - } -} - diff --git a/vpr7_x2p/vpr/SRC/place/place.h b/vpr7_x2p/vpr/SRC/place/place.h deleted file mode 100755 index 2d9d2c8cd..000000000 --- a/vpr7_x2p/vpr/SRC/place/place.h +++ /dev/null @@ -1,5 +0,0 @@ -void try_place(struct s_placer_opts placer_opts, - struct s_annealing_sched annealing_sched, - t_chan_width_dist chan_width_dist, struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, t_direct_inf *directs, int num_directs); diff --git a/vpr7_x2p/vpr/SRC/place/place_macro.c b/vpr7_x2p/vpr/SRC/place/place_macro.c deleted file mode 100644 index e9463e8ae..000000000 --- a/vpr7_x2p/vpr/SRC/place/place_macro.c +++ /dev/null @@ -1,552 +0,0 @@ -/**************************************************************************************** - Y.G.THIEN - 29 AUG 2012 - - This file contains functions related to placement macros. The term "placement macros" - refers to a structure that contains information on blocks that need special treatment - during placement and possibly routing. - - An example of placement macros is a carry chain. Blocks in a carry chain have to be - placed in a specific orientation or relative placement so that the carry_in's and the - carry_out's are properly aligned. With that, the carry chains would be able to use the - direct connections specified in the arch file. Direct connections with the pin's - fc_value 0 would be treated specially in routing where the whole carry chain would be - treated as a unit and regular routing would not be used to connect the carry_in's and - carry_out's. Floorplanning constraints may also be an example of placement macros. - - The function alloc_and_load_placement_macros allocates and loads the placement - macros in the following steps: - (1) First, go through all the block types and mark down the pins that could possibly - be part of a placement macros. - (2) Then, go through the netlist of all the pins marked in (1) to find out all the - heads of the placement macros using criteria depending on the type of placement - macros. For carry chains, the heads of the placement macros are blocks with - carry_in's not connected to any nets (OPEN) while the carry_out's connected to the - netlist with only 1 SINK. - (3) Traverse from the heads to the tails of the placement macros and load the - information in the t_pl_macro data structure. Similar to (2), tails are identified - with criteria depending on the type of placement macros. For carry chains, the - tails are blocks with carry_out's not connected to any nets (OPEN) while the - carry_in's is connected to the netlist which has only 1 SINK. - - The only placement macros supported at the moment are the carry chains with limited - functionality. - - Current support for placement macros are: - (1) The arch parser for direct connections is working. The specifications of the direct - connections are specified in sample_adder_arch.xml and also in the - VPR_User_Manual.doc - (2) The placement macros allocator and loader is working. - (3) The initial placement of placement macros that respects the restrictions of the - placement macros is working. - (4) The post-placement legality check for placement macros is working. - - Current limitations on placement macros are: - (1) One block could only be a part of a carry chain. In the future, if a block is part - of multiple placement macros, we should load 1 huge placement macro instead of - multiple placement macros that contain the same block. - (2) Bus direct connections (direct connections with multiple bits) are supported. - However, a 2-bit carry chain when loaded would become 2 1-bit carry chains. - And because of (1), only 1 1-bit carry chain would be loaded. In the future, - placement macros with multiple-bit connections or multiple 1-bit connections - should be allowed. - (3) Placement macros that span longer or wider than the chip would cause an error. - In the future, we *might* expand the size of the chip to accommodate such - placement macros that are crucial. - - In order for the carry chain support to work, two changes are required in the - arch file. - (1) For carry chain support, added in a new child in called . - specifies a list of available direct connections on the FPGA chip - that are necessary for direct carry chain connections. These direct connections - would be treated specially in routing if the fc_value for the pins is specified - as 0. Note that only direct connections that has fc_value 0 could be used as a - carry chain. - - A may have 0 or more children called . For each , - there are the following fields: - 1) name: This specifies the name given to this particular direct connection. - 2) from_pin: This specifies the SOURCEs for this direct connection. The format - could be as following: - a) type_name.port_name, for all the pins in this port. - b) type_name.port_name [end_pin_index:start_pin_index], for a - single pin, the end_pin_index and start_pin_index could be - the same. - 3) to_pin: This specifies the SINKs for this direct connection. The format is - the same as from_pin. - Note that the width of the from_pin and to_pin has to match. - 4) x_offset: This specifies the x direction that this connection is going from - SOURCEs to SINKs. - 5) y_offset: This specifies the y direction that this connection is going from - SOURCEs to SINKs. - Note that the x_offset and y_offset could not both be 0. - 6) z_offset: This specifies the z sublocations that all the blocks in this - direct connection to be at. - - The example of a direct connection specification below shows a possible carry chain - connection going north on the FPGA chip: - _______________________________________________________________________________ - | | - | | - | | - |_______________________________________________________________________________| - A corresponding arch file that has this direct connection is sample_adder_arch.xml - A corresponding blif file that uses this direct connection is adder.blif - - (2) As mentioned in (1), carry chain connections using the directs would only be - recognized if the pin's fc_value is 0. In order to achieve this, pin-based fc_value - is required. Hence, the new tag replaces both and tags. - - A tag may have 0 or more children called . For each , there are the - following fields: - 1) default_in_type: This specifies the default fc_type for input pins. They could - be "frac", "abs" or "full". - 2) default_in_val: This specifies the default fc_value for input pins. - 3) default_out_type: This specifies the default fc_type for output pins. They could - be "frac", "abs" or "full". - 4) default_out_val: This specifies the default fc_value for output pins. - - As for the children, there are the following fields: - 1) name: This specifies the name of the port/pin that the fc_type and fc_value - apply to. The name have to be in the format "port_name" or - "port_name [end_pin_index:start_pin_index]" where port_name is the name - of the port it apply to while end_pin_index and start_pin_index could - be specified to apply the fc_type and fc_value that follows to part of - a bus (multi-pin) port. - 2) fc_type: This specifies the fc_type that would be applied to the specified pins. - 3) fc_val: This specifies the fc_value that would be applied to the specified pins. - - The example of a pin-based fc_value specification below shows that the fc_values for - the cout and the cin ports are 0: - _______________________________________________________________________________ - | | - | | - | | - | | - |_______________________________________________________________________________| - A corresponding arch file that has this direct connection is sample_adder_arch.xml - A corresponding blif file that uses this direct connection is adder.blif - -****************************************************************************************/ - - -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "physical_types.h" -#include "globals.h" -#include "place.h" -#include "read_xml_arch_file.h" -#include "ReadOptions.h" -#include "place_macro.h" -#include "vpr_utils.h" - - -/******************** File-scope variables delcarations **********************/ - -/* f_idirect_from_blk_pin array allow us to quickly find pins that could be in a * - * direct connection. Values stored is the index of the possible direct connection * - * as specified in the arch file, OPEN (-1) is stored for pins that could not be * - * part of a direct chain conneciton. * - * [0...num_types-1][0...num_pins-1] */ -static int ** f_idirect_from_blk_pin = NULL; - -/* f_direct_type_from_blk_pin array stores the value SOURCE if the pin is the * - * from_pin, SINK if the pin is the to_pin in the direct connection as specified in * - * the arch file, OPEN (-1) is stored for pins that could not be part of a direct * - * chain conneciton. * - * [0...num_types-1][0...num_pins-1] */ -static int ** f_direct_type_from_blk_pin = NULL; - -/* f_imacro_from_blk_pin maps a blk_num to the corresponding macro index. * - * If the block is not part of a macro, the value OPEN (-1) is stored. * - * [0...num_blocks-1] */ -static int * f_imacro_from_iblk = NULL; - - -/******************** Subroutine declarations ********************************/ - -static void find_all_the_macro (int * num_of_macro, int * pl_macro_member_blk_num_of_this_blk, - int * pl_macro_idirect, int * pl_macro_num_members, int ** pl_macro_member_blk_num); - -static void free_imacro_from_iblk(void); - -static void alloc_and_load_imacro_from_iblk(t_pl_macro * macros, int num_macros); - -/******************** Subroutine definitions *********************************/ - -static void find_all_the_macro (int * num_of_macro, int * pl_macro_member_blk_num_of_this_blk, - int * pl_macro_idirect, int * pl_macro_num_members, int ** pl_macro_member_blk_num) { - - /* Compute required size: * - * Go through all the pins with possible direct connections in * - * f_idirect_from_blk_pin. Count the number of heads (which is the same * - * as the number macros) and also the length of each macro * - * Head - blocks with to_pin OPEN and from_pin connected * - * Tail - blocks with to_pin connected and from_pin OPEN */ - - int iblk, from_iblk_pin, to_iblk_pin, from_inet, to_inet, from_idirect, to_idirect, - from_src_or_sink, to_src_or_sink; - int next_iblk, next_inet, curr_inet; - int num_blk_pins, num_macro; - int imember; - - num_macro = 0; - for (iblk = 0; iblk < num_blocks; iblk++) { - - num_blk_pins = block[iblk].type->num_pins; - for (to_iblk_pin = 0; to_iblk_pin < num_blk_pins; to_iblk_pin++) { - - to_inet = block[iblk].nets[to_iblk_pin]; - to_idirect = f_idirect_from_blk_pin[block[iblk].type->index][to_iblk_pin]; - to_src_or_sink = f_direct_type_from_blk_pin[block[iblk].type->index][to_iblk_pin]; - - // Find to_pins (SINKs) with possible direct connection but are not - // connected to any net (Possible head of macro) - if ( to_src_or_sink == SINK && to_idirect != OPEN && to_inet == OPEN ) { - - for (from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) { - from_inet = block[iblk].nets[from_iblk_pin]; - from_idirect = f_idirect_from_blk_pin[block[iblk].type->index][from_iblk_pin]; - from_src_or_sink = f_direct_type_from_blk_pin[block[iblk].type->index][from_iblk_pin]; - - // Find from_pins with the same possible direct connection that are connected. - // Confirmed head of macro - if ( from_src_or_sink == SOURCE && to_idirect == from_idirect && from_inet != OPEN) { - - // Mark down that this is the first block in the macro - pl_macro_member_blk_num_of_this_blk[0] = iblk; - pl_macro_idirect[num_macro] = to_idirect; - - // Increment the num_member count. - pl_macro_num_members[num_macro]++; - - // Also find out how many members are in the macros, - // there are at least 2 members - 1 head and 1 tail. - - // Initialize the variables - next_inet = from_inet; - next_iblk = iblk; - - // Start finding the other members - while (next_inet != OPEN) { - - curr_inet = next_inet; - - // Assume that carry chains only has 1 sink - direct connection - if (clb_net[curr_inet].num_sinks != 1) { - assert(clb_net[curr_inet].num_sinks == 1); - } - next_iblk = clb_net[curr_inet].node_block[1]; - - // Assume that the from_iblk_pin index is the same for the next block - assert (f_idirect_from_blk_pin[block[next_iblk].type->index][from_iblk_pin] == from_idirect - && f_direct_type_from_blk_pin[block[next_iblk].type->index][from_iblk_pin] == SOURCE); - next_inet = block[next_iblk].nets[from_iblk_pin]; - - // Mark down this block as a member of the macro - imember = pl_macro_num_members[num_macro]; - pl_macro_member_blk_num_of_this_blk[imember] = next_iblk; - /* Xifan TANG: Should detect if there is a combinational loop inside */ - if (1 == spot_int_in_array(imember, pl_macro_member_blk_num_of_this_blk, next_iblk )) { - vpr_printf(TIO_MESSAGE_INFO, "Find a combinational loop in macro placement! More info:\n"); - vpr_printf(TIO_MESSAGE_ERROR,"next_inet: %d, num_macro: %d, imember: %d, next_iblk: %d.\n", - next_inet, num_macro, imember, next_iblk); - exit(1); - } - // Increment the num_member count. - pl_macro_num_members[num_macro]++; - - } // Found all the members of this macro at this point - - // Allocate the second dimension of the blk_num array since I now know the size - pl_macro_member_blk_num[num_macro] = - (int *) my_calloc (pl_macro_num_members[num_macro] , sizeof(int)); - // Copy the data from the temporary array to the newly allocated array. - for (imember = 0; imember < pl_macro_num_members[num_macro]; imember ++) - pl_macro_member_blk_num[num_macro][imember] = pl_macro_member_blk_num_of_this_blk[imember]; - - // Increment the macro count - num_macro ++; - - } // Do nothing if the from_pins does not have same possible direct connection. - } // Finish going through all the pins for from_pins. - } // Do nothing if the to_pins does not have same possible direct connection. - } // Finish going through all the pins for to_pins. - } // Finish going through all blocks. - - // Now, all the data is readily stored in the temporary data structures. - *num_of_macro = num_macro; -} - - -int alloc_and_load_placement_macros(t_direct_inf* directs, int num_directs, t_pl_macro ** macros){ - - /* This function allocates and loads the macros placement macros * - * and returns the total number of macros in 2 steps. * - * 1) Allocate temporary data structure for maximum possible * - * size and loops through all the blocks storing the data * - * relevant to the carry chains. At the same time, also count * - * the amount of memory required for the actual variables. * - * 2) Allocate the actual variables with the exact amount of * - * memory. Then loads the data from the temporary data * - * structures before freeing them. * - * * - * For pl_macro_member_blk_num, allocate for the first dimension * - * only at first. Allocate for the second dimemsion when I know * - * the size. Otherwise, the array is going to be of size * - * num_blocks^2 (There are big benckmarks VPR that have num_blocks * - * in the 100k's range). * - * * - * The placement macro array is freed by the caller(s). */ - - /* Declaration of local variables */ - int imacro, imember, num_macro; - int *pl_macro_idirect, *pl_macro_num_members, **pl_macro_member_blk_num, - *pl_macro_member_blk_num_of_this_blk; - - t_pl_macro * macro = NULL; - - /* Sets up the required variables. */ - alloc_and_load_idirect_from_blk_pin(directs, num_directs, - &f_idirect_from_blk_pin, &f_direct_type_from_blk_pin); - - /* Allocate maximum memory for temporary variables. */ - pl_macro_num_members = (int *) my_calloc (num_blocks , sizeof(int)); - pl_macro_idirect = (int *) my_calloc (num_blocks , sizeof(int)); - pl_macro_member_blk_num = (int **) my_calloc (num_blocks , sizeof(int*)); - pl_macro_member_blk_num_of_this_blk = (int *) my_calloc (num_blocks , sizeof(int)); - - /* Compute required size: * - * Go through all the pins with possible direct connections in * - * f_idirect_from_blk_pin. Count the number of heads (which is the same * - * as the number macros) and also the length of each macro * - * Head - blocks with to_pin OPEN and from_pin connected * - * Tail - blocks with to_pin connected and from_pin OPEN */ - num_macro = 0; - find_all_the_macro (&num_macro, pl_macro_member_blk_num_of_this_blk, - pl_macro_idirect, pl_macro_num_members, pl_macro_member_blk_num); - - /* Allocate the memories for the macro. */ - macro = (t_pl_macro *) my_malloc (num_macro * sizeof(t_pl_macro)); - - /* Allocate the memories for the chaim members. * - * Load the values from the temporary data structures. */ - for (imacro = 0; imacro < num_macro; imacro++) { - macro[imacro].num_blocks = pl_macro_num_members[imacro]; - macro[imacro].members = (t_pl_macro_member *) my_malloc - (macro[imacro].num_blocks * sizeof(t_pl_macro_member)); - - /* Load the values for each member of the macro */ - for (imember = 0; imember < macro[imacro].num_blocks; imember++) { - macro[imacro].members[imember].x_offset = imember * directs[pl_macro_idirect[imacro]].x_offset; - macro[imacro].members[imember].y_offset = imember * directs[pl_macro_idirect[imacro]].y_offset; - macro[imacro].members[imember].z_offset = directs[pl_macro_idirect[imacro]].z_offset; - macro[imacro].members[imember].blk_index = pl_macro_member_blk_num[imacro][imember]; - } - } - - /* Frees up the temporary data structures. */ - free(pl_macro_num_members); - free(pl_macro_idirect); - for(imacro=0; imacro < num_macro; imacro++) { - free(pl_macro_member_blk_num[imacro]); - } - free(pl_macro_member_blk_num); - free(pl_macro_member_blk_num_of_this_blk); - - /* Returns the pointer to the macro by reference. */ - *macros = macro; - return (num_macro); - -} - -void get_imacro_from_iblk(int * imacro, int iblk, t_pl_macro * macros, int num_macros) { - - /* This mapping is needed for fast lookup's whether the block with index * - * iblk belongs to a placement macro or not. * - * * - * The array f_imacro_from_iblk is used for the mapping for speed reason * - * [0...num_blocks-1] */ - - /* If the array is not allocated and loaded, allocate it. */ - if (f_imacro_from_iblk == NULL) { - alloc_and_load_imacro_from_iblk(macros, num_macros); - } - - /* Return the imacro for the block. */ - *imacro = f_imacro_from_iblk[iblk]; - -} - -static void free_imacro_from_iblk(void) { - - /* Frees the f_imacro_from_iblk array. * - * * - * This function is called when the arrays are freed in * - * free_placement_structs() */ - - if (f_imacro_from_iblk != NULL) { - free(f_imacro_from_iblk); - f_imacro_from_iblk = NULL; - } - -} - -static void alloc_and_load_imacro_from_iblk(t_pl_macro * macros, int num_macros) { - - /* Allocates and loads imacro_from_iblk array. * - * * - * The array is freed in free_placement_structs() */ - - int * temp_imacro_from_iblk = NULL; - int imacro, imember, iblk; - - /* Allocate and initialize the values to OPEN (-1). */ - temp_imacro_from_iblk = (int *)my_malloc(num_blocks * sizeof(int)); - for(iblk = 0; iblk < num_blocks; iblk ++) { - temp_imacro_from_iblk[iblk] = OPEN; - } - - /* Load the values */ - for (imacro = 0; imacro < num_macros; imacro++) { - for (imember = 0; imember < macros[imacro].num_blocks; imember++) { - iblk = macros[imacro].members[imember].blk_index; - temp_imacro_from_iblk[iblk] = imacro; - } - } - - /* Sets the file_scope variables to point at the arrays. */ - f_imacro_from_iblk = temp_imacro_from_iblk; -} - -void free_placement_macros_structs(void) { - - /* This function frees up all the static data structures used. */ - - // This frees up the two arrays and set the pointers to NULL - int itype; - if ( f_idirect_from_blk_pin != NULL ) { - for (itype = 1; itype < num_types; itype++) { - free(f_idirect_from_blk_pin[itype]); - } - free(f_idirect_from_blk_pin); - f_idirect_from_blk_pin = NULL; - } - - if ( f_direct_type_from_blk_pin != NULL ) { - for (itype = 1; itype < num_types; itype++) { - free(f_direct_type_from_blk_pin[itype]); - } - free(f_direct_type_from_blk_pin); - f_direct_type_from_blk_pin = NULL; - } - - // This frees up the imacro from iblk mapping array. - free_imacro_from_iblk(); - -} - -/* Xifan TANG: Find the position of a blk in a macro */ -int spot_blk_position_in_a_macro(t_pl_macro pl_macros, - int blk_idx) { - int imember; - - for (imember = 0; imember < pl_macros.num_blocks; imember++) { - if (blk_idx == pl_macros.members[imember].blk_index) { - return imember; - } - } - - return -1; -} - -/* Xifan TANG: Check if 1st macro contains the 2nd macro */ -void get_start_end_points_one_macro(t_pl_macro pl_macro, - int* upper_x, int* lower_x, - int* upper_y, int* lower_y) { - int imemb, iblk; - - /* Initialize */ - (*upper_x) = -1; - (*lower_x) = -1; - (*upper_y) = -1; - (*lower_y) = -1; - - /* Determine the upper/lower bound of x,y of macros*/ - for (imemb = 0; imemb < pl_macro.num_blocks; imemb++) { - iblk = pl_macro.members[imemb].blk_index; - if (0 == imemb) { - (*upper_x) = block[iblk].x; - (*upper_y) = block[iblk].y; - (*lower_x) = block[iblk].x; - (*lower_y) = block[iblk].y; - /* macro_a_upper_z = block[iblk_a].z; */ - } else { - if (block[iblk].x > (*upper_x)) { - (*upper_x) = block[iblk].x; - } - if (block[iblk].y > (*upper_y)) { - (*upper_y) = block[iblk].y; - } - if (block[iblk].x < (*lower_x)) { - (*lower_x) = block[iblk].x; - } - if (block[iblk].y < (*lower_y)) { - (*lower_y) = block[iblk].y; - } - } - } - /* check: this is currently true, as carry chain is vertical - * maybe changed if a new carry chain style is applied */ - if (!(((*upper_x) == (*lower_x))&&(((*upper_y) - (*lower_y) + 1) == (pl_macro.num_blocks)))) { - assert (((*upper_x) == (*lower_x))&&(((*upper_y) - (*lower_y) + 1) == (pl_macro.num_blocks))); - } -} - -/* Xifan TANG: Check if 1st macro contains the 2nd macro */ -int check_macros_contained(t_pl_macro pl_macro_a, - t_pl_macro pl_macro_b) { - int macro_a_upper_x, macro_a_upper_y; - int macro_a_lower_x, macro_a_lower_y; - int macro_b_upper_x, macro_b_upper_y; - int macro_b_lower_x, macro_b_lower_y; - - get_start_end_points_one_macro(pl_macro_a, ¯o_a_upper_x, ¯o_a_lower_x, - ¯o_a_upper_y, ¯o_a_lower_y); - - get_start_end_points_one_macro(pl_macro_b, ¯o_b_upper_x, ¯o_b_lower_x, - ¯o_b_upper_y, ¯o_b_lower_y); - - if ((macro_a_upper_y < macro_b_upper_y)||(macro_a_lower_y > macro_b_lower_y)) { - return 0; - } - - return 1; -} - -/* Xifan TANG: get the maximum length of macros */ -int max_len_pl_macros(int num_pl_macros, - t_pl_macro* pl_macros) { - int imacro; - int max_len = 0; - - if (0 == num_pl_macros) { - return max_len; - } - - assert(NULL != pl_macros); - - for (imacro = 0; imacro < num_pl_macros; imacro++) { - if (max_len < pl_macros[imacro].num_blocks) { - max_len = pl_macros[imacro].num_blocks; - } - } - - return max_len; -} diff --git a/vpr7_x2p/vpr/SRC/place/place_macro.h b/vpr7_x2p/vpr/SRC/place/place_macro.h deleted file mode 100644 index c1914f277..000000000 --- a/vpr7_x2p/vpr/SRC/place/place_macro.h +++ /dev/null @@ -1,176 +0,0 @@ -/**************************************************************************************** - Y.G.THIEN - 29 AUG 2012 - - This file contains functions related to placement macros. The term "placement macros" - refers to a structure that contains information on blocks that need special treatment - during placement and possibly routing. - - An example of placement macros is a carry chain. Blocks in a carry chain have to be - placed in a specific orientation or relative placement so that the carry_in's and the - carry_out's are properly aligned. With that, the carry chains would be able to use the - direct connections specified in the arch file. Direct connections with the pin's - fc_value 0 would be treated specially in routing where the whole carry chain would be - treated as a unit and regular routing would not be used to connect the carry_in's and - carry_out's. Floorplanning constraints may also be an example of placement macros. - - The function alloc_and_load_placement_macros allocates and loads the placement - macros in the following steps: - (1) First, go through all the block types and mark down the pins that could possibly - be part of a placement macros. - (2) Then, go through the netlist of all the pins marked in (1) to find out all the - heads of the placement macros using criteria depending on the type of placement - macros. For carry chains, the heads of the placement macros are blocks with - carry_in's not connected to any nets (OPEN) while the carry_out's connected to the - netlist with only 1 SINK. - (3) Traverse from the heads to the tails of the placement macros and load the - information in the t_pl_macro data structure. Similar to (2), tails are identified - with criteria depending on the type of placement macros. For carry chains, the - tails are blocks with carry_out's not connected to any nets (OPEN) while the - carry_in's is connected to the netlist which has only 1 SINK. - - The only placement macros supported at the moment are the carry chains with limited - functionality. - - Current support for placement macros are: - (1) The arch parser for direct connections is working. The specifications of the direct - connections are specified in sample_adder_arch.xml and also in the - VPR_User_Manual.doc - (2) The placement macros allocator and loader is working. - (3) The initial placement of placement macros that respects the restrictions of the - placement macros is working. - (4) The post-placement legality check for placement macros is working. - - Current limitations on placement macros are: - (1) One block could only be a part of a carry chain. In the future, if a block is part - of multiple placement macros, we should load 1 huge placement macro instead of - multiple placement macros that contain the same block. - (2) Bus direct connections (direct connections with multiple bits) are supported. - However, a 2-bit carry chain when loaded would become 2 1-bit carry chains. - And because of (1), only 1 1-bit carry chain would be loaded. In the future, - placement macros with multiple-bit connections or multiple 1-bit connections - should be allowed. - (3) Placement macros that span longer or wider than the chip would cause an error. - In the future, we *might* expand the size of the chip to accommodate such - placement macros that are crucial. - - In order for the carry chain support to work, two changes are required in the - arch file. - (1) For carry chain support, added in a new child in called . - specifies a list of available direct connections on the FPGA chip - that are necessary for direct carry chain connections. These direct connections - would be treated specially in routing if the fc_value for the pins is specified - as 0. Note that only direct connections that has fc_value 0 could be used as a - carry chain. - - A may have 0 or more children called . For each , - there are the following fields: - 1) name: This specifies the name given to this particular direct connection. - 2) from_pin: This specifies the SOURCEs for this direct connection. The format - could be as following: - a) type_name.port_name, for all the pins in this port. - b) type_name.port_name [end_pin_index:start_pin_index], for a - single pin, the end_pin_index and start_pin_index could be - the same. - 3) to_pin: This specifies the SINKs for this direct connection. The format is - the same as from_pin. - Note that the width of the from_pin and to_pin has to match. - 4) x_offset: This specifies the x direction that this connection is going from - SOURCEs to SINKs. - 5) y_offset: This specifies the y direction that this connection is going from - SOURCEs to SINKs. - Note that the x_offset and y_offset could not both be 0. - 6) z_offset: This specifies the z sublocations that all the blocks in this - direct connection to be at. - - The example of a direct connection specification below shows a possible carry chain - connection going north on the FPGA chip: - _______________________________________________________________________________ - | | - | | - | | - |_______________________________________________________________________________| - A corresponding arch file that has this direct connection is sample_adder_arch.xml - A corresponding blif file that uses this direct connection is adder.blif - - (2) As mentioned in (1), carry chain connections using the directs would only be - recognized if the pin's fc_value is 0. In order to achieve this, pin-based fc_value - is required. Hence, the new tag replaces both and tags. - - A tag may have 0 or more children called . For each , there are the - following fields: - 1) default_in_type: This specifies the default fc_type for input pins. They could - be "frac", "abs" or "full". - 2) default_in_val: This specifies the default fc_value for input pins. - 3) default_out_type: This specifies the default fc_type for output pins. They could - be "frac", "abs" or "full". - 4) default_out_val: This specifies the default fc_value for output pins. - - As for the children, there are the following fields: - 1) name: This specifies the name of the port/pin that the fc_type and fc_value - apply to. The name have to be in the format "port_name" or - "port_name [end_pin_index:start_pin_index]" where port_name is the name - of the port it apply to while end_pin_index and start_pin_index could - be specified to apply the fc_type and fc_value that follows to part of - a bus (multi-pin) port. - 2) fc_type: This specifies the fc_type that would be applied to the specified pins. - 3) fc_val: This specifies the fc_value that would be applied to the specified pins. - - The example of a pin-based fc_value specification below shows that the fc_values for - the cout and the cin ports are 0: - _______________________________________________________________________________ - | | - | | - | | - | | - |_______________________________________________________________________________| - A corresponding arch file that has this direct connection is sample_adder_arch.xml - A corresponding blif file that uses this direct connection is adder.blif - -****************************************************************************************/ - - -#ifndef PLACE_MACRO_H -#define PALCE_MACRO_H - -/* These are the placement macro structure. - * It is in the form of array of structs instead of - * structs of arrays for cache efficiency. - * Could have more data members for other macro type. - * blk_index: The block index of this block. - * x_offset: The x_offset of the previous block to this block. - * y_offset: The y_offset of the previous block to this block. - */ -typedef struct s_pl_macro_member{ - int blk_index; - int x_offset; - int y_offset; - int z_offset; -} t_pl_macro_member; - -/* num_blocks: The number of blocks this macro contains. - * members: An array of blocks in this macro [0¡­num_macro-1]. - * idirect: The direct index as specified in the arch file - */ -typedef struct s_pl_macro{ - int num_blocks; - t_pl_macro_member* members; -} t_pl_macro; - -/* These are the function declarations. */ -int alloc_and_load_placement_macros(t_direct_inf* directs, int num_directs, t_pl_macro ** chains); -void get_imacro_from_iblk(int * imacro, int iblk, t_pl_macro * macros, int num_macros); -void free_placement_macros_structs(void); - -/* Xifan TANG: spot the position of a block in a macro*/ -int spot_blk_position_in_a_macro(t_pl_macro pl_macros, int blk_idx); - -int check_macros_contained(t_pl_macro pl_macro_a, - t_pl_macro pl_macro_b); - -int max_len_pl_macros(int num_pl_macros, - t_pl_macro* pl_macros); - -#endif diff --git a/vpr7_x2p/vpr/SRC/place/place_stats.c b/vpr7_x2p/vpr/SRC/place/place_stats.c deleted file mode 100755 index d7d1d3f26..000000000 --- a/vpr7_x2p/vpr/SRC/place/place_stats.c +++ /dev/null @@ -1,152 +0,0 @@ -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" - -#define ABS_DIFF(X, Y) (((X) > (Y))? ((X) - (Y)):((Y) - (X))) -#define MAX_X 50 -#define MAX_LEN MAX_X*2 - -typedef struct relapos_rec_s { - int num_rp[MAX_LEN]; -} relapos_rec_t; - -#ifdef PRINT_REL_POS_DISTR -void -print_relative_pos_distr(void) -{ - - /* Prints out the probability distribution of the relative locations of * - * input pins on a net -- i.e. simulates 2-point net distance probability * - * distribution. */ -#ifdef PRINT_REL_POS_DISTR - FILE *out_bin_file; - relapos_rec_t rp_rec; -#endif /* PRINT_REL_POS_DISTR */ - - int inet, len, rp, src_x, src_y, dst_x, dst_y, del_x, del_y, min_del, - sink_pin, sum; - int *total_conn; - int **relapos; - double **relapos_distr; - - total_conn = (int *)my_malloc((nx + ny + 1) * sizeof(int)); - relapos = (int **)my_malloc((nx + ny + 1) * sizeof(int *)); - relapos_distr = (double **)my_malloc((nx + ny + 1) * sizeof(double *)); - for (len = 0; len <= nx + ny; len++) - { - relapos[len] = (int *)my_calloc(len / 2 + 1, sizeof(int)); - relapos_distr[len] = - (double *)my_calloc((len / 2 + 1), sizeof(double)); - } - - for (inet = 0; inet < num_nets; inet++) - { - if (clb_net[inet].is_global == FALSE) - { - - src_x = block[clb_net[inet].node_block[0]].x; - src_y = block[clb_net[inet].node_block[0]].y; - - for (sink_pin = 1; sink_pin <= clb_net[inet].num_sinks; - sink_pin++) - { - dst_x = block[clb_net[inet].node_block[sink_pin]].x; - dst_y = block[clb_net[inet].node_block[sink_pin]].y; - - del_x = ABS_DIFF(dst_x, src_x); - del_y = ABS_DIFF(dst_y, src_y); - - len = del_x + del_y; - - min_del = (del_x < del_y) ? del_x : del_y; - - if (!(min_del <= (len / 2))) - { - vpr_printf(TIO_MESSAGE_ERROR, "Error calculating relative location min_del = %d, len = %d\n", - min_del, len); - exit(1); - } - else - { - relapos[len][min_del]++; - } - } - } - } - -#ifdef PRINT_REL_POS_DISTR - out_bin_file = - fopen("/jayar/b/b5/fang/vpr_test/wirelength/relapos2.bin", "rb+"); -#endif /* PRINT_REL_POS_DISTR */ - - for (len = 0; len <= nx + ny; len++) - { - sum = 0; - for (rp = 0; rp <= len / 2; rp++) - { - sum += relapos[len][rp]; - } - if (sum != 0) - { -#ifdef PRINT_REL_POS_DISTR - fseek(out_bin_file, sizeof(relapos_rec_t) * len, - SEEK_SET); - fread(&rp_rec, sizeof(relapos_rec_t), 1, out_bin_file); -#endif /* PRINT_REL_POS_DISTR */ - - for (rp = 0; rp <= len / 2; rp++) - { - - relapos_distr[len][rp] = - (double)relapos[len][rp] / (double)sum; - - /* updating the binary record at "len" */ -#ifdef PRINT_REL_POS_DISTR - vpr_printf(TIO_MESSAGE_ERROR, "old %d increased by %d\n", rp_rec.num_rp[rp], relapos[len][rp]); - rp_rec.num_rp[rp] += relapos[len][rp]; - vpr_printf(TIO_MESSAGE_ERROR, "becomes %d\n", rp_rec.num_rp[rp]); -#endif /* PRINT_REL_POS_DISTR */ - } -#ifdef PRINT_REL_POS_DISTR - /* write back the updated record at "len" */ - fseek(out_bin_file, sizeof(relapos_rec_t) * len, - SEEK_SET); - fwrite(&rp_rec, sizeof(relapos_rec_t), 1, out_bin_file); -#endif /* PRINT_REL_POS_DISTR */ - - } - total_conn[len] = sum; - } - - fprintf(stdout, "Source to sink relative positions:\n"); - for (len = 1; len <= nx + ny; len++) - { - if (total_conn[len] != 0) - { - fprintf(stdout, "Of 2-pin distance %d exists %d\n\n", len, - total_conn[len]); - for (rp = 0; rp <= len / 2; rp++) - { - fprintf(stdout, "\trp%d\t%d\t\t(%.5f)\n", rp, - relapos[len][rp], relapos_distr[len][rp]); - } - fprintf(stdout, "----------------\n"); - } - } - - free((void *)total_conn); - for (len = 0; len <= nx + ny; len++) - { - free((void *)relapos[len]); - free((void *)relapos_distr[len]); - } - free((void *)relapos); - free((void *)relapos_distr); - -#ifdef PRINT_REL_POS_DISTR - fclose(out_bin_file); -#endif /* PRINT_REL_POS_DISTR */ -} -#endif diff --git a/vpr7_x2p/vpr/SRC/place/place_stats.h b/vpr7_x2p/vpr/SRC/place/place_stats.h deleted file mode 100755 index 67b451b18..000000000 --- a/vpr7_x2p/vpr/SRC/place/place_stats.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifdef PRINT_REL_POS_DISTR -void print_relative_pos_distr(void); - -/* Prints out the probability distribution of the relative locations of * - * input pins on a net -- i.e. simulates 2-point net length probability * - * distribution. */ -#endif diff --git a/vpr7_x2p/vpr/SRC/place/timing_place.c b/vpr7_x2p/vpr/SRC/place/timing_place.c deleted file mode 100755 index c6805ae3d..000000000 --- a/vpr7_x2p/vpr/SRC/place/timing_place.c +++ /dev/null @@ -1,152 +0,0 @@ -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "path_delay.h" -#include "path_delay2.h" -#include "net_delay.h" -#include "timing_place_lookup.h" -#include "timing_place.h" - -float **timing_place_crit; /*available externally */ - -static t_chunk timing_place_crit_ch = {NULL, 0, NULL}; -static t_chunk net_delay_ch = {NULL, 0, NULL}; - -/*static struct s_linked_vptr *timing_place_crit_chunk_list_head; -static struct s_linked_vptr *net_delay_chunk_list_head;*/ - -/******** prototypes ******************/ -/*static float **alloc_crit(struct s_linked_vptr **chunk_list_head_ptr); - -static void free_crit(struct s_linked_vptr **chunk_list_head_ptr);*/ - -static float **alloc_crit(t_chunk *chunk_list_ptr); - -static void free_crit(t_chunk *chunk_list_ptr); - -/**************************************/ - -static float ** alloc_crit(t_chunk *chunk_list_ptr) { - - /* Allocates space for the timing_place_crit data structure * - * [0..num_nets-1][1..num_pins-1]. I chunk the data to save space on large * - * problems. */ - - float **local_crit; /* [0..num_nets-1][1..num_pins-1] */ - float *tmp_ptr; - int inet; - - local_crit = (float **) my_malloc(num_nets * sizeof(float *)); - - for (inet = 0; inet < num_nets; inet++) { - tmp_ptr = (float *) my_chunk_malloc( - (clb_net[inet].num_sinks) * sizeof(float), chunk_list_ptr); - local_crit[inet] = tmp_ptr - 1; /* [1..num_sinks] */ - } - - return (local_crit); -} - -/**************************************/ -static void free_crit(t_chunk *chunk_list_ptr){ - free_chunk_memory(chunk_list_ptr); -} - -/**************************************/ -void print_sink_delays(const char *fname) { - - int num_at_level, num_edges, inode, ilevel, i; - FILE *fp; - - fp = my_fopen(fname, "w", 0); - - for (ilevel = num_tnode_levels - 1; ilevel >= 0; ilevel--) { - num_at_level = tnodes_at_level[ilevel].nelem; - - for (i = 0; i < num_at_level; i++) { - inode = tnodes_at_level[ilevel].list[i]; - num_edges = tnode[inode].num_edges; - - if (num_edges == 0) { /* sink */ - fprintf(fp, "%g\n", tnode[inode].T_arr); - } - } - } - fclose(fp); -} - -/**************************************/ -void load_criticalities(t_slack * slacks, float crit_exponent) { - /* Performs a 1-to-1 mapping from criticality to timing_place_crit. - For every pin on every net (or, equivalently, for every tedge ending - in that pin), timing_place_crit = criticality^(criticality exponent) */ - - int inet, ipin; -#ifdef PATH_COUNTING - float timing_criticality, path_criticality; -#endif - - for (inet = 0; inet < num_nets; inet++) { - if (inet == OPEN) - continue; - if (clb_net[inet].is_global) - continue; - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { - if (slacks->timing_criticality[inet][ipin] < HUGE_NEGATIVE_FLOAT + 1) { - /* We didn't analyze this connection, so give it a timing_place_crit of 0. */ - timing_place_crit[inet][ipin] = 0.; - } else { -#ifdef PATH_COUNTING - /* Calculate criticality as a weighted sum of timing criticality and path - criticality. The placer likes a great deal of contrast between criticalities. - Since path criticality varies much more than timing, we "sharpen" timing - criticality by taking it to some power, crit_exponent (between 1 and 8 by default). */ - path_criticality = slacks->path_criticality[inet][ipin]; - timing_criticality = pow(slacks->timing_criticality[inet][ipin], crit_exponent); - - timing_place_crit[inet][ipin] = PLACE_PATH_WEIGHT * path_criticality - + (1 - PLACE_PATH_WEIGHT) * timing_criticality; -#else - /* Just take timing criticality to some power (crit_exponent). */ - timing_place_crit[inet][ipin] = pow(slacks->timing_criticality[inet][ipin], crit_exponent); -#endif - } - } - } -} - -/**************************************/ -t_slack * alloc_lookups_and_criticalities(t_chan_width_dist chan_width_dist, - struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, float ***net_delay, INP t_direct_inf *directs, - INP int num_directs) { - - t_slack * slacks = alloc_and_load_timing_graph(timing_inf); - - (*net_delay) = alloc_net_delay(&net_delay_ch, clb_net, - num_nets); - - compute_delay_lookup_tables(router_opts, det_routing_arch, segment_inf, - timing_inf, chan_width_dist, directs, num_directs); - - timing_place_crit = alloc_crit(&timing_place_crit_ch); - - return slacks; -} - -/**************************************/ -void free_lookups_and_criticalities(float ***net_delay, t_slack * slacks) { - - free(timing_place_crit); - free_crit(&timing_place_crit_ch); - - free_timing_graph(slacks); - free_net_delay(*net_delay, &net_delay_ch); - - free_place_lookup_structs(); -} - -/**************************************/ diff --git a/vpr7_x2p/vpr/SRC/place/timing_place.h b/vpr7_x2p/vpr/SRC/place/timing_place.h deleted file mode 100755 index c53dccaf9..000000000 --- a/vpr7_x2p/vpr/SRC/place/timing_place.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef TIMING_PLACE -#define TIMING_PLACE - -t_slack * alloc_lookups_and_criticalities(t_chan_width_dist chan_width_dist, - struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, float ***net_delay, INP t_direct_inf *directs, - INP int num_directs); - -void free_lookups_and_criticalities(float ***net_delay, t_slack * slacks); - -void print_sink_delays(const char *fname); - -void load_criticalities(t_slack * slacks, float crit_exponent); - -extern float **timing_place_crit; - -#endif diff --git a/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c b/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c deleted file mode 100755 index 371825e90..000000000 --- a/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c +++ /dev/null @@ -1,1068 +0,0 @@ -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "route_common.h" -#include "place_and_route.h" -#include "route_tree_timing.h" -#include "route_timing.h" -#include "timing_place_lookup.h" -#include "rr_graph.h" -#include "route_export.h" -#include -#include "read_xml_arch_file.h" - -/* mrFPGA : Xifan TANG */ -#include "mrfpga_globals.h" -#include "net_delay_types.h" -#include "net_delay_local_void.h" -/* end */ - -/*this file contains routines that generate the array containing*/ -/*the delays between blocks, this is used in the timing driven */ -/*placement routines */ - -/*To compute delay between blocks we place temporary blocks at */ -/*different locations in the FPGA and route nets between */ -/*the blocks. From this procedure we generate a lookup table */ -/*which tells us the delay between different locations in */ -/*the FPGA */ - -/*Note: these routines assume that there is a uniform and even */ -/*distribution of the different wire segments. If this is not */ -/*the case, then this lookup table will be off */ - -/*Note: This code removes all heterogeneous types and creates an - artificial 1x1 tile. A good lookup for heterogeniety - requires more research */ - -#define NET_COUNT 1 /*we only use one net in these routines, */ -/*it is repeatedly routed and ripped up */ -/*to compute delays between different */ -/*locations, this value should not change */ -#define NET_USED 0 /*we use net at location zero of the net */ -/*structure */ -#define NET_USED_SOURCE_BLOCK 0 /*net.block[0] is source block */ -#define NET_USED_SINK_BLOCK 1 /*net.block[1] is sink block */ -#define SOURCE_BLOCK 0 /*block[0] is source */ -#define SINK_BLOCK 1 /*block[1] is sink */ - -#define BLOCK_COUNT 2 /*use 2 blocks to compute delay between */ -/*the various FPGA locations */ -/*do not change this number unless you */ -/*really know what you are doing, it is */ -/*assumed that the net only connects to */ -/*two blocks */ - -#define NUM_TYPES_USED 3 /* number of types used in look up */ - -#define DEBUG_TIMING_PLACE_LOOKUP /*initialize arrays to known state */ - -#define DUMPFILE "lookup_dump.echo" -/* #define PRINT_ARRAYS *//*only used during debugging, calls routine to */ -/*print out the various lookup arrays */ - -/***variables that are exported to other modules***/ - -/*the delta arrays are used to contain the best case routing delay */ -/*between different locations on the FPGA. */ - -float **delta_io_to_clb; -float **delta_clb_to_clb; -float **delta_clb_to_io; -float **delta_io_to_io; - -/*** Other Global Arrays ******/ -/* I could have allocated these as local variables, and passed them all */ -/* around, but was too lazy, since this is a small file, it should not */ -/* be a big problem */ - -static float **net_delay; -static float *pin_criticality; -static int *sink_order; -static t_rt_node **rt_node_of_sink; -static t_type_ptr IO_TYPE_BACKUP; -static t_type_ptr EMPTY_TYPE_BACKUP; -static t_type_ptr FILL_TYPE_BACKUP; -static t_type_descriptor dummy_type_descriptors[NUM_TYPES_USED]; -static t_type_descriptor *type_descriptors_backup; -static struct s_grid_tile **grid_backup; -static int num_types_backup; - -static t_ivec **clb_opins_used_locally; - -#ifdef PRINT_ARRAYS -static FILE *lookup_dump; /* If debugging mode is on, print out to - * the file defined in DUMPFILE */ -#endif /* PRINT_ARRAYS */ - -/*** Function Prototypes *****/ - -static void alloc_net(void); - -static void alloc_block(void); - -static void load_simplified_device(void); -static void restore_original_device(void); - -static void alloc_and_assign_internal_structures(struct s_net **original_net, - struct s_block **original_block, int *original_num_nets, - int *original_num_blocks); - -static void free_and_reset_internal_structures(struct s_net *original_net, - struct s_block *original_block, int original_num_nets, - int original_num_blocks); - -static void setup_chan_width(struct s_router_opts router_opts, - t_chan_width_dist chan_width_dist); - -static void alloc_routing_structs(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, INP t_direct_inf *directs, - INP int num_directs); - -static void free_routing_structs(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf); - -static void assign_locations(t_type_ptr source_type, int source_x_loc, - int source_y_loc, int source_z_loc, t_type_ptr sink_type, - int sink_x_loc, int sink_y_loc, int sink_z_loc); - -static float assign_blocks_and_route_net(t_type_ptr source_type, - int source_x_loc, int source_y_loc, t_type_ptr sink_type, - int sink_x_loc, int sink_y_loc, struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf); - -static void alloc_delta_arrays(void); - -static void free_delta_arrays(void); - -static void generic_compute_matrix(float ***matrix_ptr, t_type_ptr source_type, - t_type_ptr sink_type, int source_x, int source_y, int start_x, - int end_x, int start_y, int end_y, struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf); - -static void compute_delta_clb_to_clb(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, int longest_length); - -static void compute_delta_io_to_clb(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf); - -static void compute_delta_clb_to_io(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf); - -static void compute_delta_io_to_io(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf); - -static void compute_delta_arrays(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, int longest_length); - -static int get_first_pin(enum e_pin_type pintype, t_type_ptr type); - -static int get_longest_segment_length( - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf); -static void reset_placement(void); - -/* mrFPGA: Xifan TANG */ -void try_buffer_for_net( int inet, t_rc_node** rc_node_free_list, t_linked_rc_edge** rc_edge_free_list, t_linked_rc_ptr* rr_node_to_rc_node, float* net_delay ); - -static void buffer_net(float* cur_net_delay); -/* end */ - -#ifdef PRINT_ARRAYS -static void print_array(float **array_to_print, - int x1, - int x2, - int y1, - int y2); -#endif -/**************************************/ -static int get_first_pin(enum e_pin_type pintype, t_type_ptr type) { - - /*this code assumes logical equivilance between all driving pins */ - /*global pins are not hooked up to the temporary net */ - - int i, currpin; - - currpin = 0; - for (i = 0; i < type->num_class; i++) { - if (type->class_inf[i].type == pintype && !type->is_global_pin[currpin]) - return (type->class_inf[i].pinlist[0]); - else - currpin += type->class_inf[i].num_pins; - } - assert(0); - exit(0); /*should never hit this line */ -} - -/**************************************/ -static int get_longest_segment_length( - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf) { - - int i, length; - - length = 0; - for (i = 0; i < det_routing_arch.num_segment; i++) { - if (segment_inf[i].length > length) - length = segment_inf[i].length; - } - return (length); -} - -/**************************************/ -static void alloc_net(void) { - - int i, len; - - clb_net = (struct s_net *) my_malloc(num_nets * sizeof(struct s_net)); - for (i = 0; i < NET_COUNT; i++) { - /* FIXME: We *really* shouldn't be allocating write-once copies */ - len = strlen("TEMP_NET"); - clb_net[i].name = (char *) my_malloc((len + 1) * sizeof(char)); - clb_net[i].is_global = FALSE; - strcpy(clb_net[NET_USED].name, "TEMP_NET"); - - clb_net[i].num_sinks = (BLOCK_COUNT - 1); - clb_net[i].node_block = (int *) my_malloc(BLOCK_COUNT * sizeof(int)); - clb_net[i].node_block[NET_USED_SOURCE_BLOCK] = NET_USED_SOURCE_BLOCK; /*driving block */ - clb_net[i].node_block[NET_USED_SINK_BLOCK] = NET_USED_SINK_BLOCK; /*target block */ - - clb_net[i].node_block_pin = (int *) my_malloc( - BLOCK_COUNT * sizeof(int)); - /*the values for this are allocated in assign_blocks_and_route_net */ - - } -} - -/**************************************/ -static void alloc_block(void) { - - /*allocates block structure, and assigns values to known parameters */ - /*type and x,y fields are left undefined at this stage since they */ - /*are not known until we start moving blocks through the clb array */ - - int ix_b, ix_p, len, i; - int max_pins; - - max_pins = 0; - for (i = 0; i < NUM_TYPES_USED; i++) { - max_pins = std::max(max_pins, type_descriptors[i].num_pins); - } - - block = (struct s_block *) my_malloc(num_blocks * sizeof(struct s_block)); - - for (ix_b = 0; ix_b < BLOCK_COUNT; ix_b++) { - len = strlen("TEMP_BLOCK"); - block[ix_b].name = (char *) my_malloc((len + 1) * sizeof(char)); - strcpy(block[ix_b].name, "TEMP_BLOCK"); - - block[ix_b].nets = (int *) my_malloc(max_pins * sizeof(int)); - block[ix_b].nets[0] = 0; - for (ix_p = 1; ix_p < max_pins; ix_p++) - block[ix_b].nets[ix_p] = OPEN; - } -} - -/**************************************/ -static void load_simplified_device(void) { - int i, j; - - /* Backup original globals */ - EMPTY_TYPE_BACKUP = EMPTY_TYPE; - IO_TYPE_BACKUP = IO_TYPE; - FILL_TYPE_BACKUP = FILL_TYPE; - type_descriptors_backup = type_descriptors; - num_types_backup = num_types; - num_types = NUM_TYPES_USED; - - /* Fill in homogeneous core type info */ - dummy_type_descriptors[0] = *EMPTY_TYPE; - dummy_type_descriptors[0].index = 0; - dummy_type_descriptors[1] = *IO_TYPE; - dummy_type_descriptors[1].index = 1; - dummy_type_descriptors[2] = *FILL_TYPE; - dummy_type_descriptors[2].index = 2; - type_descriptors = dummy_type_descriptors; - EMPTY_TYPE = &dummy_type_descriptors[0]; - IO_TYPE = &dummy_type_descriptors[1]; - FILL_TYPE = &dummy_type_descriptors[2]; - - /* Fill in homogeneous core grid info */ - grid_backup = grid; - grid = (struct s_grid_tile **) alloc_matrix(0, nx + 1, 0, ny + 1, - sizeof(struct s_grid_tile)); - for (i = 0; i < nx + 2; i++) { - for (j = 0; j < ny + 2; j++) { - if ((i == 0 && j == 0) || (i == nx + 1 && j == 0) - || (i == 0 && j == ny + 1) - || (i == nx + 1 && j == ny + 1)) { - grid[i][j].type = EMPTY_TYPE; - } else if (i == 0 || i == nx + 1 || j == 0 || j == ny + 1) { - grid[i][j].type = IO_TYPE; - } else { - grid[i][j].type = FILL_TYPE; - } - grid[i][j].blocks = (int*)my_malloc( - grid[i][j].type->capacity * sizeof(int)); - grid[i][j].offset = 0; - } - } -} -static void restore_original_device(void) { - int i, j; - - /* restore previous globals */ - IO_TYPE = IO_TYPE_BACKUP; - EMPTY_TYPE = EMPTY_TYPE_BACKUP; - FILL_TYPE = FILL_TYPE_BACKUP; - type_descriptors = type_descriptors_backup; - num_types = num_types_backup; - - /* free allocatd data */ - for (i = 0; i < nx + 2; i++) { - for (j = 0; j < ny + 2; j++) { - free(grid[i][j].blocks); - } - } - free_matrix(grid, 0, nx + 1, 0, sizeof(struct s_grid_tile)); - grid = grid_backup; -} - -/**************************************/ -static void reset_placement(void) { - int i, j, k; - - for (i = 0; i <= nx + 1; i++) { - for (j = 0; j <= ny + 1; j++) { - grid[i][j].usage = 0; - for (k = 0; k < grid[i][j].type->capacity; k++) { - grid[i][j].blocks[k] = EMPTY; - } - } - } -} - -/**************************************/ -static void alloc_and_assign_internal_structures(struct s_net **original_net, - struct s_block **original_block, int *original_num_nets, - int *original_num_blocks) { - /*allocate new data structures to hold net, and block info */ - - *original_net = clb_net; - *original_num_nets = num_nets; - num_nets = NET_COUNT; - alloc_net(); - - *original_block = block; - *original_num_blocks = num_blocks; - num_blocks = BLOCK_COUNT; - alloc_block(); - - /* [0..num_nets-1][1..num_pins-1] */ - net_delay = (float **) alloc_matrix(0, NET_COUNT - 1, 1, BLOCK_COUNT - 1, - sizeof(float)); - - reset_placement(); -} - -/**************************************/ -static void free_and_reset_internal_structures(struct s_net *original_net, - struct s_block *original_block, int original_num_nets, - int original_num_blocks) { - /*reset gloabal data structures to the state that they were in before these */ - /*lookup computation routines were called */ - - int i; - - /*there should be only one net to free, but this is safer */ - for (i = 0; i < NET_COUNT; i++) { - free(clb_net[i].name); - free(clb_net[i].node_block); - free(clb_net[i].node_block_pin); - } - free(clb_net); - clb_net = original_net; - - for (i = 0; i < BLOCK_COUNT; i++) { - free(block[i].name); - free(block[i].nets); - } - free(block); - block = original_block; - - num_nets = original_num_nets; - num_blocks = original_num_blocks; - - free_matrix(net_delay, 0, NET_COUNT - 1, 1, sizeof(float)); - -} - -/**************************************/ -static void setup_chan_width(struct s_router_opts router_opts, - t_chan_width_dist chan_width_dist) { - /*we give plenty of tracks, this increases routability for the */ - /*lookup table generation */ - - int width_fac, i, max_pins_per_clb; - - max_pins_per_clb = 0; - for (i = 0; i < num_types; i++) { - max_pins_per_clb = std::max(max_pins_per_clb, type_descriptors[i].num_pins); - } - - if (router_opts.fixed_channel_width == NO_FIXED_CHANNEL_WIDTH) - width_fac = 4 * max_pins_per_clb; /*this is 2x the value that binary search starts */ - /*this should be enough to allow most pins to */ - /*connect to tracks in the architecture */ - else - width_fac = router_opts.fixed_channel_width; - - init_chan(width_fac, chan_width_dist); -} - -/**************************************/ -static void alloc_routing_structs(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, INP t_direct_inf *directs, - INP int num_directs) { - - int bb_factor; - int warnings; - t_graph_type graph_type; - - /*calls routines that set up routing resource graph and associated structures */ - - /*must set up dummy blocks for the first pass through to setup locally used opins */ - /* Only one block per tile */ - assign_locations(FILL_TYPE, 1, 1, 0, FILL_TYPE, nx, ny, 0); - - clb_opins_used_locally = alloc_route_structs(); - - free_rr_graph(); - - if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; - } else { - graph_type = ( - det_routing_arch.directionality == BI_DIRECTIONAL ? - GRAPH_BIDIR : GRAPH_UNIDIR); - } - - build_rr_graph(graph_type, num_types, dummy_type_descriptors, nx, ny, grid, - chan_width_x[0], NULL, - det_routing_arch.switch_block_type, det_routing_arch.Fs, - det_routing_arch.switch_block_sub_type, det_routing_arch.sub_Fs, - det_routing_arch.wire_opposite_side, - det_routing_arch.num_segment, - det_routing_arch.num_switch, segment_inf, - det_routing_arch.global_route_switch, - det_routing_arch.delayless_switch, timing_inf, - det_routing_arch.wire_to_ipin_switch, router_opts.base_cost_type, - NULL, 0, TRUE, /* do not send in direct connections because we care about general placement timing instead of special pin placement timing */ - &warnings, 0, NULL, FALSE, FALSE); - - alloc_and_load_rr_node_route_structs(); - - alloc_timing_driven_route_structs(&pin_criticality, &sink_order, - &rt_node_of_sink); - - bb_factor = nx + ny; /*set it to a huge value */ - init_route_structs(bb_factor); -} - -/**************************************/ -static void free_routing_structs(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf) { - int i; - free_rr_graph(); - - free_rr_node_route_structs(); - free_route_structs(); - free_trace_structs(); - - free_timing_driven_route_structs(pin_criticality, sink_order, - rt_node_of_sink); - - if (clb_opins_used_locally != NULL) { - for (i = 0; i < num_blocks; i++) { - free_ivec_vector(clb_opins_used_locally[i], 0, - block[i].type->num_class - 1); - } - free(clb_opins_used_locally); - clb_opins_used_locally = NULL; - } -} - -/**************************************/ -static void assign_locations(t_type_ptr source_type, int source_x_loc, - int source_y_loc, int source_z_loc, t_type_ptr sink_type, - int sink_x_loc, int sink_y_loc, int sink_z_loc) { - /*all routing occurs between block 0 (source) and block 1 (sink) */ - block[SOURCE_BLOCK].type = source_type; - block[SOURCE_BLOCK].x = source_x_loc; - block[SOURCE_BLOCK].y = source_y_loc; - block[SOURCE_BLOCK].z = source_z_loc; - - block[SINK_BLOCK].type = sink_type; - block[SINK_BLOCK].x = sink_x_loc; - block[SINK_BLOCK].y = sink_y_loc; - block[SINK_BLOCK].z = sink_z_loc; - - grid[source_x_loc][source_y_loc].blocks[source_z_loc] = SOURCE_BLOCK; - grid[sink_x_loc][sink_y_loc].blocks[sink_z_loc] = SINK_BLOCK; - - clb_net[NET_USED].node_block_pin[NET_USED_SOURCE_BLOCK] = get_first_pin( - DRIVER, block[SOURCE_BLOCK].type); - clb_net[NET_USED].node_block_pin[NET_USED_SINK_BLOCK] = get_first_pin( - RECEIVER, block[SINK_BLOCK].type); - - grid[source_x_loc][source_y_loc].usage += 1; - grid[sink_x_loc][sink_y_loc].usage += 1; - -} - -/**************************************/ -static float assign_blocks_and_route_net(t_type_ptr source_type, - int source_x_loc, int source_y_loc, t_type_ptr sink_type, - int sink_x_loc, int sink_y_loc, struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf) { - /*places blocks at the specified locations, and routes a net between them */ - /*returns the delay of this net */ - - float pres_fac, net_delay_value; - - int source_z_loc, sink_z_loc; - - /* Only one block per tile */ - source_z_loc = 0; - sink_z_loc = 0; - - net_delay_value = IMPOSSIBLE; /*set to known value for debug purposes */ - - assign_locations(source_type, source_x_loc, source_y_loc, source_z_loc, - sink_type, sink_x_loc, sink_y_loc, sink_z_loc); - - load_net_rr_terminals(rr_node_indices); - - pres_fac = 0; /* ignore congestion */ - - /* Route this net with a dummy criticality of 0 by calling - timing_driven_route_net with slacks set to NULL. */ - timing_driven_route_net(NET_USED, pres_fac, - router_opts.max_criticality, router_opts.criticality_exp, - router_opts.astar_fac, router_opts.bend_cost, - pin_criticality, sink_order, rt_node_of_sink, - net_delay[NET_USED], NULL); - - /* mrFPGA */ - if (is_mrFPGA && is_wire_buffer) { - buffer_net(net_delay[NET_USED]); - } - /* end */ - - net_delay_value = net_delay[NET_USED][NET_USED_SINK_BLOCK]; - - grid[source_x_loc][source_y_loc].usage = 0; - grid[source_x_loc][source_y_loc].blocks[source_z_loc] = EMPTY; - grid[sink_x_loc][sink_y_loc].usage = 0; - grid[sink_x_loc][sink_y_loc].blocks[sink_z_loc] = EMPTY; - - return (net_delay_value); -} - -/**************************************/ -static void alloc_delta_arrays(void) { - int id_x, id_y; - - delta_clb_to_clb = (float **) alloc_matrix(0, nx - 1, 0, ny - 1, - sizeof(float)); - delta_io_to_clb = (float **) alloc_matrix(0, nx, 0, ny, sizeof(float)); - delta_clb_to_io = (float **) alloc_matrix(0, nx, 0, ny, sizeof(float)); - delta_io_to_io = (float **) alloc_matrix(0, nx + 1, 0, ny + 1, - sizeof(float)); - - /*initialize all of the array locations to -1 */ - - for (id_x = 0; id_x <= nx; id_x++) { - for (id_y = 0; id_y <= ny; id_y++) { - delta_io_to_clb[id_x][id_y] = IMPOSSIBLE; - } - } - for (id_x = 0; id_x <= nx - 1; id_x++) { - for (id_y = 0; id_y <= ny - 1; id_y++) { - delta_clb_to_clb[id_x][id_y] = IMPOSSIBLE; - } - } - for (id_x = 0; id_x <= nx; id_x++) { - for (id_y = 0; id_y <= ny; id_y++) { - delta_clb_to_io[id_x][id_y] = IMPOSSIBLE; - } - } - for (id_x = 0; id_x <= nx + 1; id_x++) { - for (id_y = 0; id_y <= ny + 1; id_y++) { - delta_io_to_io[id_x][id_y] = IMPOSSIBLE; - } - } -} - -/**************************************/ -static void free_delta_arrays(void) { - - free_matrix(delta_io_to_clb, 0, nx, 0, sizeof(float)); - free_matrix(delta_clb_to_clb, 0, nx - 1, 0, sizeof(float)); - free_matrix(delta_clb_to_io, 0, nx, 0, sizeof(float)); - free_matrix(delta_io_to_io, 0, nx + 1, 0, sizeof(float)); - -} - -/**************************************/ -static void generic_compute_matrix(float ***matrix_ptr, t_type_ptr source_type, - t_type_ptr sink_type, int source_x, int source_y, int start_x, - int end_x, int start_y, int end_y, struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf) { - - int delta_x, delta_y; - int sink_x, sink_y; - - for (sink_x = start_x; sink_x <= end_x; sink_x++) { - for (sink_y = start_y; sink_y <= end_y; sink_y++) { - delta_x = abs(sink_x - source_x); - delta_y = abs(sink_y - source_y); - - if (delta_x == 0 && delta_y == 0) - continue; /*do not compute distance from a block to itself */ - /*if a value is desired, pre-assign it somewhere else */ - - (*matrix_ptr)[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - } - } -} - -/**************************************/ -static void compute_delta_clb_to_clb(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, int longest_length) { - - /*this routine must compute delay values in a slightly different way than the */ - /*other compute routines. We cannot use a location close to the edge as the */ - /*source location for the majority of the delay computations because this */ - /*would give gradually increasing delay values. To avoid this from happening */ - /*a clb that is at least longest_length away from an edge should be chosen */ - /*as a source , if longest_length is more than 0.5 of the total size then */ - /*choose a CLB at the center as the source CLB */ - - int source_x, source_y, sink_x, sink_y; - int start_x, start_y, end_x, end_y; - int delta_x, delta_y; - t_type_ptr source_type, sink_type; - - source_type = FILL_TYPE; - sink_type = FILL_TYPE; - - if (longest_length < 0.5 * (nx)) { - start_x = longest_length; - } else { - start_x = (int) (0.5 * nx); - } - end_x = nx; - source_x = start_x; - - if (longest_length < 0.5 * (ny)) { - start_y = longest_length; - } else { - start_y = (int) (0.5 * ny); - } - end_y = ny; - source_y = start_y; - - /*don't put the sink all the way to the corner, until it is necessary */ - for (sink_x = start_x; sink_x <= end_x - 1; sink_x++) { - for (sink_y = start_y; sink_y <= end_y - 1; sink_y++) { - delta_x = abs(sink_x - source_x); - delta_y = abs(sink_y - source_y); - - if (delta_x == 0 && delta_y == 0) { - delta_clb_to_clb[delta_x][delta_y] = 0.0; - continue; - } - delta_clb_to_clb[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - } - - } - - sink_x = end_x - 1; - sink_y = end_y - 1; - - for (source_x = start_x - 1; source_x >= 1; source_x--) { - for (source_y = start_y; source_y <= end_y - 1; source_y++) { - delta_x = abs(sink_x - source_x); - delta_y = abs(sink_y - source_y); - - delta_clb_to_clb[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - } - } - - for (source_x = 1; source_x <= end_x - 1; source_x++) { - for (source_y = 1; source_y < start_y; source_y++) { - delta_x = abs(sink_x - source_x); - delta_y = abs(sink_y - source_y); - - delta_clb_to_clb[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - } - } - - /*now move sink into the top right corner */ - sink_x = end_x; - sink_y = end_y; - source_x = 1; - for (source_y = 1; source_y <= end_y; source_y++) { - delta_x = abs(sink_x - source_x); - delta_y = abs(sink_y - source_y); - - delta_clb_to_clb[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - - } - - sink_x = end_x; - sink_y = end_y; - source_y = 1; - for (source_x = 1; source_x <= end_x; source_x++) { - delta_x = abs(sink_x - source_x); - delta_y = abs(sink_y - source_y); - - delta_clb_to_clb[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - } -} - -/**************************************/ -static void compute_delta_io_to_clb(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf) { - int source_x, source_y; - int start_x, start_y, end_x, end_y; - t_type_ptr source_type, sink_type; - - source_type = IO_TYPE; - sink_type = FILL_TYPE; - - delta_io_to_clb[0][0] = IMPOSSIBLE; - delta_io_to_clb[nx][ny] = IMPOSSIBLE; - - source_x = 0; - source_y = 1; - - start_x = 1; - end_x = nx; - start_y = 1; - end_y = ny; - generic_compute_matrix(&delta_io_to_clb, source_type, sink_type, source_x, - source_y, start_x, end_x, start_y, end_y, router_opts, - det_routing_arch, segment_inf, timing_inf); - - source_x = 1; - source_y = 0; - - start_x = 1; - end_x = 1; - start_y = 1; - end_y = ny; - generic_compute_matrix(&delta_io_to_clb, source_type, sink_type, source_x, - source_y, start_x, end_x, start_y, end_y, router_opts, - det_routing_arch, segment_inf, timing_inf); - - start_x = 1; - end_x = nx; - start_y = ny; - end_y = ny; - generic_compute_matrix(&delta_io_to_clb, source_type, sink_type, source_x, - source_y, start_x, end_x, start_y, end_y, router_opts, - det_routing_arch, segment_inf, timing_inf); -} - -/**************************************/ -static void compute_delta_clb_to_io(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf) { - int source_x, source_y, sink_x, sink_y; - int delta_x, delta_y; - t_type_ptr source_type, sink_type; - - source_type = FILL_TYPE; - sink_type = IO_TYPE; - - delta_clb_to_io[0][0] = IMPOSSIBLE; - delta_clb_to_io[nx][ny] = IMPOSSIBLE; - - sink_x = 0; - sink_y = 1; - for (source_x = 1; source_x <= nx; source_x++) { - for (source_y = 1; source_y <= ny; source_y++) { - delta_x = abs(source_x - sink_x); - delta_y = abs(source_y - sink_y); - - delta_clb_to_io[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - } - } - - sink_x = 1; - sink_y = 0; - source_x = 1; - delta_x = abs(source_x - sink_x); - for (source_y = 1; source_y <= ny; source_y++) { - delta_y = abs(source_y - sink_y); - delta_clb_to_io[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - } - - sink_x = 1; - sink_y = 0; - source_y = ny; - delta_y = abs(source_y - sink_y); - for (source_x = 2; source_x <= nx; source_x++) { - delta_x = abs(source_x - sink_x); - delta_clb_to_io[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - } -} - -/**************************************/ -static void compute_delta_io_to_io(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf) { - int source_x, source_y, sink_x, sink_y; - int delta_x, delta_y; - t_type_ptr source_type, sink_type; - - source_type = IO_TYPE; - sink_type = IO_TYPE; - - delta_io_to_io[0][0] = 0; /*delay to itself is 0 (this can happen) */ - delta_io_to_io[nx + 1][ny + 1] = IMPOSSIBLE; - delta_io_to_io[0][ny] = IMPOSSIBLE; - delta_io_to_io[nx][0] = IMPOSSIBLE; - delta_io_to_io[nx][ny + 1] = IMPOSSIBLE; - delta_io_to_io[nx + 1][ny] = IMPOSSIBLE; - - source_x = 0; - source_y = 1; - sink_x = 0; - delta_x = abs(sink_x - source_x); - - for (sink_y = 2; sink_y <= ny; sink_y++) { - delta_y = abs(sink_y - source_y); - delta_io_to_io[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - - } - - source_x = 0; - source_y = 1; - sink_x = nx + 1; - delta_x = abs(sink_x - source_x); - - for (sink_y = 1; sink_y <= ny; sink_y++) { - delta_y = abs(sink_y - source_y); - delta_io_to_io[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - - } - - source_x = 1; - source_y = 0; - sink_y = 0; - delta_y = abs(sink_y - source_y); - - for (sink_x = 2; sink_x <= nx; sink_x++) { - delta_x = abs(sink_x - source_x); - delta_io_to_io[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - - } - - source_x = 1; - source_y = 0; - sink_y = ny + 1; - delta_y = abs(sink_y - source_y); - - for (sink_x = 1; sink_x <= nx; sink_x++) { - delta_x = abs(sink_x - source_x); - delta_io_to_io[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - - } - - source_x = 0; - sink_y = ny + 1; - for (source_y = 1; source_y <= ny; source_y++) { - for (sink_x = 1; sink_x <= nx; sink_x++) { - delta_y = abs(source_y - sink_y); - delta_x = abs(source_x - sink_x); - delta_io_to_io[delta_x][delta_y] = assign_blocks_and_route_net( - source_type, source_x, source_y, sink_type, sink_x, sink_y, - router_opts, det_routing_arch, segment_inf, timing_inf); - - } - } -} - -/**************************************/ -#ifdef PRINT_ARRAYS -static void -print_array(float **array_to_print, - int x1, - int x2, - int y1, - int y2) -{ - - int idx_x, idx_y; - - fprintf(lookup_dump, "\nPrinting Array \n\n"); - - for (idx_y = y2; idx_y >= y1; idx_y--) - { - for (idx_x = x1; idx_x <= x2; idx_x++) - { - fprintf(lookup_dump, " %9.2e", - array_to_print[idx_x][idx_y]); - } - fprintf(lookup_dump, "\n"); - } - fprintf(lookup_dump, "\n\n"); -} -#endif -/**************************************/ -static void compute_delta_arrays(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, int longest_length) { - - vpr_printf(TIO_MESSAGE_INFO, "Computing delta_io_to_io lookup matrix, may take a few seconds, please wait...\n"); - compute_delta_io_to_io(router_opts, det_routing_arch, segment_inf, timing_inf); - vpr_printf(TIO_MESSAGE_INFO, "Computing delta_io_to_clb lookup matrix, may take a few seconds, please wait...\n"); - compute_delta_io_to_clb(router_opts, det_routing_arch, segment_inf, timing_inf); - vpr_printf(TIO_MESSAGE_INFO, "Computing delta_clb_to_io lookup matrix, may take a few seconds, please wait...\n"); - compute_delta_clb_to_io(router_opts, det_routing_arch, segment_inf, timing_inf); - vpr_printf(TIO_MESSAGE_INFO, "Computing delta_clb_to_clb lookup matrix, may take a few seconds, please wait...\n"); - compute_delta_clb_to_clb(router_opts, det_routing_arch, segment_inf, timing_inf, longest_length); - -#ifdef PRINT_ARRAYS - lookup_dump = my_fopen(DUMPFILE, "w", 0); - fprintf(lookup_dump, "\n\nprinting delta_clb_to_clb\n"); - print_array(delta_clb_to_clb, 0, nx - 1, 0, ny - 1); - fprintf(lookup_dump, "\n\nprinting delta_io_to_clb\n"); - print_array(delta_io_to_clb, 0, nx, 0, ny); - fprintf(lookup_dump, "\n\nprinting delta_clb_to_io\n"); - print_array(delta_clb_to_io, 0, nx, 0, ny); - fprintf(lookup_dump, "\n\nprinting delta_io_to_io\n"); - print_array(delta_io_to_io, 0, nx + 1, 0, ny + 1); - fclose(lookup_dump); -#endif - -} - -/******* Globally Accessable Functions **********/ - -/**************************************/ -void compute_delay_lookup_tables(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, t_chan_width_dist chan_width_dist, INP t_direct_inf *directs, - INP int num_directs) { - - static struct s_net *original_net; /*this will be used as a pointer to remember what */ - - /*the "real" nets in the circuit are. This is */ - /*required because we are using the net structure */ - /*in these routines to find delays between blocks */ - static struct s_block *original_block; /*same def as original_nets, but for block */ - - static int original_num_nets; - static int original_num_blocks; - static int longest_length; - - load_simplified_device(); - - alloc_and_assign_internal_structures(&original_net, &original_block, - &original_num_nets, &original_num_blocks); - setup_chan_width(router_opts, chan_width_dist); - - alloc_routing_structs(router_opts, det_routing_arch, segment_inf, - timing_inf, directs, num_directs); - - longest_length = get_longest_segment_length(det_routing_arch, segment_inf); - - /*now setup and compute the actual arrays */ - alloc_delta_arrays(); - compute_delta_arrays(router_opts, det_routing_arch, segment_inf, timing_inf, - longest_length); - - /*free all data structures that are no longer needed */ - free_routing_structs(router_opts, det_routing_arch, segment_inf, - timing_inf); - - restore_original_device(); - - free_and_reset_internal_structures(original_net, original_block, - original_num_nets, original_num_blocks); -} - -/**************************************/ -void free_place_lookup_structs(void) { - - free_delta_arrays(); - -} - -/* mrFPGA */ -static void buffer_net( float* cur_net_delay ) -{ - t_rc_node *rc_node_free_list; - t_linked_rc_edge *rc_edge_free_list; - //int inet; - t_linked_rc_ptr *rr_node_to_rc_node; /* [0..num_rr_nodes-1] */ - - vpr_printf(TIO_MESSAGE_INFO, "mrFPGA: net delay before buffer: %g\n", cur_net_delay[NET_USED_SINK_BLOCK] ); - rr_node_to_rc_node = (t_linked_rc_ptr *) my_calloc (num_rr_nodes, - sizeof (t_linked_rc_ptr)); - - rc_node_free_list = NULL; - rc_edge_free_list = NULL; - try_buffer_for_net( NET_USED, &rc_node_free_list, &rc_edge_free_list, rr_node_to_rc_node, cur_net_delay ); - free_rc_node_free_list (rc_node_free_list); - free_rc_edge_free_list (rc_edge_free_list); - free (rr_node_to_rc_node); - vpr_printf(TIO_MESSAGE_INFO, "mrFPGA: net delay after buffer: %g\n", cur_net_delay[NET_USED_SINK_BLOCK] ); -} -/* end */ diff --git a/vpr7_x2p/vpr/SRC/place/timing_place_lookup.h b/vpr7_x2p/vpr/SRC/place/timing_place_lookup.h deleted file mode 100755 index fd2406233..000000000 --- a/vpr7_x2p/vpr/SRC/place/timing_place_lookup.h +++ /dev/null @@ -1,13 +0,0 @@ -#define IMPOSSIBLE -1 /*indicator of an array location that */ -/*should never be accessed */ - -void compute_delay_lookup_tables(struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, t_chan_width_dist chan_width_dist, INP t_direct_inf *directs, - INP int num_directs); -void free_place_lookup_structs(void); - -extern float **delta_io_to_clb; -extern float **delta_clb_to_clb; -extern float **delta_clb_to_io; -extern float **delta_io_to_io; diff --git a/vpr7_x2p/vpr/SRC/power/PowerSpicedComponent.c b/vpr7_x2p/vpr/SRC/power/PowerSpicedComponent.c deleted file mode 100644 index cc8acc8e1..000000000 --- a/vpr7_x2p/vpr/SRC/power/PowerSpicedComponent.c +++ /dev/null @@ -1,230 +0,0 @@ -/************************* INCLUDES *********************************/ -#include -#include -#include -#include - -using namespace std; - -#include - -#include "util.h" -#include "PowerSpicedComponent.h" - -PowerCallibInputs::PowerCallibInputs(PowerSpicedComponent * parent_, - float inputs) : - parent(parent_), num_inputs(inputs), sorted(false), done_callibration( - false) { - - /* Add min/max bounding entries */ - add_size(0); - add_size(std::numeric_limits::max()); -} - -void PowerCallibInputs::add_size(float transistor_size, float power) { - PowerCallibSize * entry = new PowerCallibSize(transistor_size, power); - entries.push_back(entry); - sorted = false; -} - -bool sorter_PowerCallibSize(PowerCallibSize * a, PowerCallibSize * b) { - return a->transistor_size < b->transistor_size; -} - -void PowerCallibInputs::sort_me() { - sort(entries.begin(), entries.end(), sorter_PowerCallibSize); - sorted = true; -} - -void PowerCallibInputs::callibrate() { - assert(entries.size() >= 2); - - for (vector::iterator it = entries.begin() + 1; - it != entries.end() - 1; it++) { - float est_power = parent->component_usage(num_inputs, - (*it)->transistor_size); - (*it)->factor = (*it)->power / est_power; - } - - /* Set min-value placeholder */ - entries[0]->factor = entries[1]->factor; - - /* Set max-value placeholder */ - entries[entries.size() - 1]->factor = entries[entries.size() - 2]->factor; - - done_callibration = true; -} - -PowerCallibSize * PowerCallibInputs::get_entry_bound(bool lower, - float transistor_size) { - PowerCallibSize * prev = entries[0]; - - assert(sorted); - for (vector::iterator it = entries.begin() + 1; - it != entries.end(); it++) { - if ((*it)->transistor_size > transistor_size) { - if (lower) - return prev; - else - return *it; - } - prev = *it; - } - return NULL; -} - -PowerSpicedComponent::PowerSpicedComponent( - float (*usage_fn)(int num_inputs, float transistor_size)) { - component_usage = usage_fn; - - /* Always pad with a high and low entry */ - add_entry(0); -// add_entry(std::numeric_limits::max()); - add_entry(1000000000); - - done_callibration = false; - sorted = true; -} - -PowerCallibInputs * PowerSpicedComponent::add_entry(int num_inputs) { - PowerCallibInputs * entry = new PowerCallibInputs(this, num_inputs); - entries.push_back(entry); - return entry; -} - -PowerCallibInputs * PowerSpicedComponent::get_entry(int num_inputs) { - vector::iterator it; - - for (it = entries.begin(); it != entries.end(); it++) { - if ((*it)->num_inputs == num_inputs) { - break; - } - } - - if (it == entries.end()) { - return add_entry(num_inputs); - } else { - return *it; - } -} - -PowerCallibInputs * PowerSpicedComponent::get_entry_bound(bool lower, - int num_inputs) { - PowerCallibInputs * prev = entries[0]; - - assert(sorted); - for (vector::iterator it = entries.begin() + 1; - it != entries.end(); it++) { - if ((*it)->num_inputs > num_inputs) { - if (lower) { - if (prev == entries[0]) - return NULL; - else - return prev; - } else { - if (*it == entries[entries.size() - 1]) - return NULL; - else - return *it; - } - } - prev = *it; - } - return NULL; -} - -void PowerSpicedComponent::add_data_point(int num_inputs, float transistor_size, - float power) { - assert(!done_callibration); - PowerCallibInputs * inputs_entry = get_entry(num_inputs); - inputs_entry->add_size(transistor_size, power); - sorted = false; -} - -float PowerSpicedComponent::scale_factor(int num_inputs, - float transistor_size) { - - PowerCallibInputs * inputs_lower; - PowerCallibInputs * inputs_upper; - - PowerCallibSize * size_lower; - PowerCallibSize * size_upper; - - float factor_lower = 0.; - float factor_upper = 0.; - float factor; - - float perc_upper; - - assert(done_callibration); - - inputs_lower = get_entry_bound(true, num_inputs); - inputs_upper = get_entry_bound(false, num_inputs); - - if (inputs_lower) { - /* Interpolation of factor between sizes for lower # inputs */ - assert(inputs_lower->done_callibration); - size_lower = inputs_lower->get_entry_bound(true, transistor_size); - size_upper = inputs_lower->get_entry_bound(false, transistor_size); - - perc_upper = (transistor_size - size_lower->transistor_size) - / (size_upper->transistor_size - size_lower->transistor_size); - factor_lower = perc_upper * size_upper->factor - + (1 - perc_upper) * size_lower->factor; - } - - if (inputs_upper) { - /* Interpolation of factor between sizes for upper # inputs */ - assert(inputs_upper->done_callibration); - size_lower = inputs_upper->get_entry_bound(true, transistor_size); - size_upper = inputs_upper->get_entry_bound(false, transistor_size); - - perc_upper = (transistor_size - size_lower->transistor_size) - / (size_upper->transistor_size - size_lower->transistor_size); - factor_upper = perc_upper * size_upper->factor - + (1 - perc_upper) * size_lower->factor; - } - - if (!inputs_lower) { - factor = factor_upper; - } else if (!inputs_upper) { - factor = factor_lower; - } else { - /* Interpolation of factor between inputs */ - perc_upper = - ((float) (num_inputs - inputs_lower->num_inputs)) - / ((float) (inputs_upper->num_inputs - - inputs_lower->num_inputs)); - factor = perc_upper * factor_upper + (1 - perc_upper) * factor_lower; - } - return factor; - -} - -bool sorter_PowerCallibInputs(PowerCallibInputs * a, PowerCallibInputs * b) { - return a->num_inputs < b->num_inputs; -} - -void PowerSpicedComponent::sort_me(void) { - sort(entries.begin(), entries.end(), sorter_PowerCallibInputs); - - for (vector::iterator it = entries.begin(); - it != entries.end(); it++) { - (*it)->sort_me(); - } - sorted = true; -} - -void PowerSpicedComponent::callibrate(void) { - sort_me(); - - for (vector::iterator it = entries.begin(); - it != entries.end(); it++) { - (*it)->callibrate(); - } - done_callibration = true; -} - -bool PowerSpicedComponent::is_done_callibration(void) { - return done_callibration; -} diff --git a/vpr7_x2p/vpr/SRC/power/PowerSpicedComponent.h b/vpr7_x2p/vpr/SRC/power/PowerSpicedComponent.h deleted file mode 100644 index 45c4c6516..000000000 --- a/vpr7_x2p/vpr/SRC/power/PowerSpicedComponent.h +++ /dev/null @@ -1,82 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -#ifndef __POWER_POWERSPICEDCOMPONENT_NMOS_H__ -#define __POWER_POWERSPICEDCOMPONENT_NMOS_H__ - -#include - -/************************* STRUCTS **********************************/ -class PowerSpicedComponent; - -class PowerCallibSize { -public: - float transistor_size; - float power; - float factor; - - PowerCallibSize(float size, float power_) : - transistor_size(size), power(power_), factor(0.) { - } - const bool operator<(const PowerCallibSize & rhs) { - return transistor_size < rhs.transistor_size; - } -}; - -class PowerCallibInputs { -public: - PowerSpicedComponent * parent; - int num_inputs; - std::vector entries; - bool sorted; - - PowerCallibInputs(PowerSpicedComponent * parent, float num_inputs); - - void add_size(float transistor_size, float power = 0.); - PowerCallibSize * get_entry_bound(bool lower, float transistor_size); - void sort_me(); - bool done_callibration; - void callibrate(); -}; - -class PowerSpicedComponent { -public: - std::vector entries; - - /* Estimation function for this component */ - float (*component_usage)(int num_inputs, float transistor_size); - - bool sorted; - bool done_callibration; - - PowerCallibInputs * add_entry(int num_inputs); - PowerCallibInputs* get_entry(int num_inputs); - PowerCallibInputs * get_entry_bound(bool lower, int num_inputs); - - PowerSpicedComponent( - float (*usage_fn)(int num_inputs, float transistor_size)); - - void add_data_point(int num_inputs, float transistor_size, float power); - float scale_factor(int num_inputs, float transistor_size); - void sort_me(); - -// void update_scale_factor(float (*fn)(float size)); - void callibrate(void); - bool is_done_callibration(void); -}; - -#endif diff --git a/vpr7_x2p/vpr/SRC/power/power.c b/vpr7_x2p/vpr/SRC/power/power.c deleted file mode 100644 index d185ffa9d..000000000 --- a/vpr7_x2p/vpr/SRC/power/power.c +++ /dev/null @@ -1,1924 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/** - * This is the top-level file for power estimation in VTR - */ - -/************************* INCLUDES *********************************/ -#include -#include -#include -#include -#include -#include -using namespace std; - -#include -#include - -#include "power.h" -#include "power_components.h" -#include "power_util.h" -#include "power_lowlevel.h" -#include "power_sizing.h" -#include "power_callibrate.h" -#include "power_cmos_tech.h" - -#include "physical_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "vpr_utils.h" -#include "ezxml.h" -#include "read_xml_util.h" - -/************************* DEFINES **********************************/ -#define CONVERT_NM_PER_M 1000000000 -#define CONVERT_UM_PER_M 1000000 - -/************************* ENUMS ************************************/ -typedef enum { - POWER_BREAKDOWN_ENTRY_TYPE_TITLE = 0, - POWER_BREAKDOWN_ENTRY_TYPE_MODE, - POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT, - POWER_BREAKDOWN_ENTRY_TYPE_PB, - POWER_BREAKDOWN_ENTRY_TYPE_INTERC, - POWER_BREAKDOWN_ENTRY_TYPE_BUFS_WIRES -} e_power_breakdown_entry_type; - -/************************* GLOBALS **********************************/ -t_solution_inf g_solution_inf; -t_power_output * g_power_output; -t_power_commonly_used * g_power_commonly_used; -t_power_tech * g_power_tech; -t_power_arch * g_power_arch; -static t_rr_node_power * rr_node_power; - -/************************* Function Declarations ********************/ -/* Routing */ -static void power_usage_routing(t_power_usage * power_usage, - t_det_routing_arch * routing_arch, t_segment_inf * segment_inf); - -/* Tiles */ -static void power_usage_blocks(t_power_usage * power_usage); -static void power_usage_pb(t_power_usage * power_usage, t_pb * pb, - t_pb_graph_node * pb_node); -static void power_usage_primitive(t_power_usage * power_usage, t_pb * pb, - t_pb_graph_node * pb_graph_node); -static void power_reset_tile_usage(void); -static void power_reset_pb_type(t_pb_type * pb_type); -static void power_usage_local_buffers_and_wires(t_power_usage * power_usage, - t_pb * pb, t_pb_graph_node * pb_node); - -/* Clock */ -static void power_usage_clock(t_power_usage * power_usage, - t_clock_arch * clock_arch); -static void power_usage_clock_single(t_power_usage * power_usage, - t_clock_network * clock_inf); - -/* Init/Uninit */ -static void dealloc_mux_graph(t_mux_node * node); -static void dealloc_mux_graph_rec(t_mux_node * node); - -/* Printing */ -static void power_print_breakdown_pb_rec(FILE * fp, t_pb_type * pb_type, - int indent); -static void power_print_summary(FILE * fp, t_vpr_setup vpr_setup); -//static void power_print_stats(FILE * fp); -static void power_print_breakdown_summary(FILE * fp); -static void power_print_breakdown_entry(FILE * fp, int indent, - e_power_breakdown_entry_type type, char * name, float power, - float total_power, float perc_dyn, char * method); -static void power_print_breakdown_component(FILE * fp, char * name, - e_power_component_type type, int indent_level); -static void power_print_breakdown_pb(FILE * fp); - -static char * power_estimation_method_name( - e_power_estimation_method power_method); - -/************************* FUNCTION DEFINITIONS *********************/ -/** - * This function calculates the power of primitives (ff, lut, etc), - * by calling the appropriate primitive function. - * - power_usage: (Return value) - * - pb: The pysical block - * - pb_graph_node: The physical block graph node - * - calc_dynamic: Calculate dynamic power? Otherwise ignore - * - calc_static: Calculate static power? Otherwise ignore - */ -static void power_usage_primitive(t_power_usage * power_usage, t_pb * pb, - t_pb_graph_node * pb_graph_node) { - t_power_usage sub_power_usage; - - power_zero_usage(power_usage); - power_zero_usage(&sub_power_usage); - - if (strcmp(pb_graph_node->pb_type->blif_model, ".names") == 0) { - /* LUT */ - - char * SRAM_values; - float * input_probabilities; - float * input_densities; - int LUT_size; - int pin_idx; - - assert(pb_graph_node->num_input_ports == 1); - - LUT_size = pb_graph_node->num_input_pins[0]; - - input_probabilities = (float*) my_calloc(LUT_size, sizeof(float)); - input_densities = (float*) my_calloc(LUT_size, sizeof(float)); - - for (pin_idx = 0; pin_idx < LUT_size; pin_idx++) { - t_pb_graph_pin * pin = &pb_graph_node->input_pins[0][pin_idx]; - - input_probabilities[pin_idx] = pin_prob(pb, pin); - input_densities[pin_idx] = pin_dens(pb, pin); - } - - if (pb) { - SRAM_values = alloc_SRAM_values_from_truth_table(LUT_size, - logical_block[pb->logical_block].truth_table); - } else { - SRAM_values = alloc_SRAM_values_from_truth_table(LUT_size, NULL); - } - power_usage_lut(&sub_power_usage, LUT_size, - g_power_arch->LUT_transistor_size, SRAM_values, - input_probabilities, input_densities, g_solution_inf.T_crit); - power_add_usage(power_usage, &sub_power_usage); - free(SRAM_values); - free(input_probabilities); - free(input_densities); - } else if (strcmp(pb_graph_node->pb_type->blif_model, ".latch") == 0) { - /* Flip-Flop */ - - t_pb_graph_pin * D_pin = &pb_graph_node->input_pins[0][0]; - t_pb_graph_pin * Q_pin = &pb_graph_node->output_pins[0][0]; - - float D_dens = 0.; - float D_prob = 0.; - float Q_prob = 0.; - float Q_dens = 0.; - float clk_dens = 0.; - float clk_prob = 0.; - - D_dens = pin_dens(pb, D_pin); - D_prob = pin_prob(pb, D_pin); - Q_dens = pin_dens(pb, Q_pin); - Q_prob = pin_prob(pb, Q_pin); - - clk_prob = g_clock_arch->clock_inf[0].prob; - clk_dens = g_clock_arch->clock_inf[0].dens; - - power_usage_ff(&sub_power_usage, g_power_arch->FF_size, D_prob, D_dens, - Q_prob, Q_dens, clk_prob, clk_dens, g_solution_inf.T_crit); - power_add_usage(power_usage, &sub_power_usage); - - } else { - char msg[BUFSIZE]; - sprintf(msg, "No dynamic power defined for BLIF model: %s", - pb_graph_node->pb_type->blif_model); - power_log_msg(POWER_LOG_WARNING, msg); - - sprintf(msg, "No leakage power defined for BLIF model: %s", - pb_graph_node->pb_type->blif_model); - power_log_msg(POWER_LOG_WARNING, msg); - - } -} - -static -void power_usage_local_pin_toggle(t_power_usage * power_usage, t_pb * pb, - t_pb_graph_pin * pin) { - float scale_factor; - - power_zero_usage(power_usage); - - if (pin->pin_power->scaled_by_pin) { - scale_factor = pin_prob(pb, pin->pin_power->scaled_by_pin); - if (pin->port->port_power->reverse_scaled) { - scale_factor = 1 - scale_factor; - } - } else { - scale_factor = 1.0; - } - - /* Divide by 2 because density is switches/cycle, but a toggle is 2 switches */ - power_usage->dynamic += scale_factor - * pin->port->port_power->energy_per_toggle * pin_dens(pb, pin) / 2.0 - / g_solution_inf.T_crit; -} - -static -void power_usage_local_pin_buffer_and_wire(t_power_usage * power_usage, - t_pb * pb, t_pb_graph_pin * pin) { - t_power_usage sub_power_usage; - float buffer_size = 0.; - double C_wire; - - power_zero_usage(power_usage); - - /* Wire switching */ - C_wire = pin->pin_power->C_wire; - power_usage_wire(&sub_power_usage, C_wire, pin_dens(pb, pin), - g_solution_inf.T_crit); - power_add_usage(power_usage, &sub_power_usage); - - /* Buffer power */ - buffer_size = pin->pin_power->buffer_size; - if (buffer_size) { - power_usage_buffer(&sub_power_usage, buffer_size, pin_prob(pb, pin), - pin_dens(pb, pin), FALSE, g_solution_inf.T_crit); - power_add_usage(power_usage, &sub_power_usage); - } -} - -static void power_usage_local_buffers_and_wires(t_power_usage * power_usage, - t_pb * pb, t_pb_graph_node * pb_node) { - int port_idx; - int pin_idx; - t_power_usage pin_power; - - power_zero_usage(power_usage); - - /* Input pins */ - for (port_idx = 0; port_idx < pb_node->num_input_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_input_pins[port_idx]; - pin_idx++) { - power_usage_local_pin_buffer_and_wire(&pin_power, pb, - &pb_node->input_pins[port_idx][pin_idx]); - power_add_usage(power_usage, &pin_power); - } - } - - /* Output pins */ - for (port_idx = 0; port_idx < pb_node->num_output_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_output_pins[port_idx]; - pin_idx++) { - power_usage_local_pin_buffer_and_wire(&pin_power, pb, - &pb_node->output_pins[port_idx][pin_idx]); - power_add_usage(power_usage, &pin_power); - } - } - - /* Clock pins */ - for (port_idx = 0; port_idx < pb_node->num_clock_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_clock_pins[port_idx]; - pin_idx++) { - power_usage_local_pin_buffer_and_wire(&pin_power, pb, - &pb_node->clock_pins[port_idx][pin_idx]); - power_add_usage(power_usage, &pin_power); - } - } -} - -/** Calculates the power of a pb: - * First checks if dynamic/static power is provided by user in arch file. If not: - * - Calculate power of all interconnect - * - Call recursively for children - * - If no children, must be a primitive. Call primitive hander. - */ -static void power_usage_pb(t_power_usage * power_usage, t_pb * pb, - t_pb_graph_node * pb_node) { - - t_power_usage power_usage_bufs_wires; - t_power_usage power_usage_local_muxes; - t_power_usage power_usage_children; - t_power_usage power_usage_pin_toggle; - t_power_usage power_usage_sub; - - int pb_type_idx; - int pb_idx; - int interc_idx; - int pb_mode; - int port_idx; - int pin_idx; - float dens_avg; - int num_pins; - - power_zero_usage(power_usage); - - t_pb_type * pb_type = pb_node->pb_type; - t_pb_type_power * pb_power = pb_node->pb_type->pb_type_power; - - boolean estimate_buffers_and_wire = FALSE; - boolean estimate_multiplexers = FALSE; - boolean estimate_primitives = FALSE; - boolean recursive_children; - - /* Get mode */ - if (pb) { - pb_mode = pb->mode; - } else { - /* Default mode if not initialized (will only affect leakage power) */ - pb_mode = pb_type->pb_type_power->leakage_default_mode; - } - - recursive_children = power_method_is_recursive( - pb_node->pb_type->pb_type_power->estimation_method); - - power_zero_usage(&power_usage_sub); - - switch (pb_node->pb_type->pb_type_power->estimation_method) { - case POWER_METHOD_IGNORE: - case POWER_METHOD_SUM_OF_CHILDREN: - break; - - case POWER_METHOD_ABSOLUTE: - power_add_usage(power_usage, &pb_power->absolute_power_per_instance); - power_component_add_usage(&pb_power->absolute_power_per_instance, - POWER_COMPONENT_PB_OTHER); - break; - - case POWER_METHOD_C_INTERNAL: - power_zero_usage(&power_usage_sub); - - /* Just take the average density of inputs pins and use - * that with user-defined block capacitance and leakage */ - - /* Average the activity of all pins */ - num_pins = 0; - dens_avg = 0.; - for (port_idx = 0; port_idx < pb_node->num_input_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_input_pins[port_idx]; - pin_idx++) { - dens_avg += pin_dens(pb, - &pb_node->input_pins[port_idx][pin_idx]); - num_pins++; - } - } - if (num_pins != 0) { - dens_avg = dens_avg / num_pins; - } - power_usage_sub.dynamic += power_calc_node_switching( - pb_power->C_internal, dens_avg, g_solution_inf.T_crit); - - /* Leakage is an absolute */ - power_usage_sub.leakage += - pb_power->absolute_power_per_instance.leakage; - - /* Add to power of this PB */ - power_add_usage(power_usage, &power_usage_sub); - - // Add to component type - power_component_add_usage(&power_usage_sub, POWER_COMPONENT_PB_OTHER); - break; - - case POWER_METHOD_TOGGLE_PINS: - power_zero_usage(&power_usage_pin_toggle); - - /* Add toggle power of each input pin */ - for (port_idx = 0; port_idx < pb_node->num_input_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_input_pins[port_idx]; - pin_idx++) { - t_power_usage pin_power; - power_usage_local_pin_toggle(&pin_power, pb, - &pb_node->input_pins[port_idx][pin_idx]); - power_add_usage(&power_usage_pin_toggle, &pin_power); - } - } - - /* Add toggle power of each output pin */ - for (port_idx = 0; port_idx < pb_node->num_output_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_output_pins[port_idx]; - pin_idx++) { - t_power_usage pin_power; - power_usage_local_pin_toggle(&pin_power, pb, - &pb_node->output_pins[port_idx][pin_idx]); - power_add_usage(&power_usage_pin_toggle, &pin_power); - } - } - - /* Add toggle power of each clock pin */ - for (port_idx = 0; port_idx < pb_node->num_clock_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_clock_pins[port_idx]; - pin_idx++) { - t_power_usage pin_power; - power_usage_local_pin_toggle(&pin_power, pb, - &pb_node->clock_pins[port_idx][pin_idx]); - power_add_usage(&power_usage_pin_toggle, &pin_power); - } - } - - /* Static is supplied as an absolute */ - power_usage_pin_toggle.leakage += - pb_power->absolute_power_per_instance.leakage; - - // Add to this PB power - power_add_usage(power_usage, &power_usage_pin_toggle); - - // Add to component type power - power_component_add_usage(&power_usage_pin_toggle, - POWER_COMPONENT_PB_OTHER); - break; - case POWER_METHOD_SPECIFY_SIZES: - estimate_buffers_and_wire = TRUE; - estimate_multiplexers = TRUE; - estimate_primitives = TRUE; - break; - case POWER_METHOD_AUTO_SIZES: - estimate_buffers_and_wire = TRUE; - estimate_multiplexers = TRUE; - estimate_primitives = TRUE; - break; - case POWER_METHOD_UNDEFINED: - default: - assert(0); - break; - } - - if (pb_node->pb_type->class_type == LUT_CLASS) { - /* LUTs will have a child node that is used to indicate pin - * equivalence for routing purposes. - * There is a crossbar to the child node; however, - * this interconnect does not exist in FPGA hardware and should - * be ignored for power calculations. */ - estimate_buffers_and_wire = FALSE; - estimate_multiplexers = FALSE; - } - - if (pb_node->pb_type->num_modes == 0) { - /* This is a leaf node, which is a primitive (lut, ff, etc) */ - if (estimate_primitives) { - assert(pb_node->pb_type->blif_model); - power_usage_primitive(&power_usage_sub, pb, pb_node); - - // Add to power of this PB - power_add_usage(power_usage, &power_usage_sub); - - // Add to power of component type - power_component_add_usage(&power_usage_sub, - POWER_COMPONENT_PB_PRIMITIVES); - - } - - } else { - /* This node had children. The power of this node is the sum of: - * - Buffers/Wires in Interconnect from Parent to children - * - Multiplexers in Interconnect from Parent to children - * - Child nodes - */ - - if (estimate_buffers_and_wire) { - /* Check pins of all interconnect */ - power_usage_local_buffers_and_wires(&power_usage_bufs_wires, pb, - pb_node); - power_component_add_usage(&power_usage_bufs_wires, - POWER_COMPONENT_PB_BUFS_WIRE); - power_add_usage( - &pb_node->pb_type->pb_type_power->power_usage_bufs_wires, - &power_usage_bufs_wires); - power_add_usage(power_usage, &power_usage_bufs_wires); - } - - /* Interconnect Structures (multiplexers) */ - if (estimate_multiplexers) { - power_zero_usage(&power_usage_local_muxes); - for (interc_idx = 0; - interc_idx < pb_type->modes[pb_mode].num_interconnect; - interc_idx++) { - power_usage_local_interc_mux(&power_usage_sub, pb, - &pb_node->interconnect_pins[pb_mode][interc_idx]); - power_add_usage(&power_usage_local_muxes, &power_usage_sub); - - } - // Add to power of this PB - power_add_usage(power_usage, &power_usage_local_muxes); - - // Add to component type power - power_component_add_usage(&power_usage_local_muxes, - POWER_COMPONENT_PB_INTERC_MUXES); - - // Add to power of this mode - power_add_usage( - &pb_node->pb_type->modes[pb_mode].mode_power->power_usage, - &power_usage_local_muxes); - } - - /* Add power for children */ - if (recursive_children) { - power_zero_usage(&power_usage_children); - for (pb_type_idx = 0; - pb_type_idx - < pb_node->pb_type->modes[pb_mode].num_pb_type_children; - pb_type_idx++) { - for (pb_idx = 0; - pb_idx - < pb_node->pb_type->modes[pb_mode].pb_type_children[pb_type_idx].num_pb; - pb_idx++) { - t_pb * child_pb = NULL; - t_pb_graph_node * child_pb_graph_node; - - if (pb && pb->child_pbs[pb_type_idx][pb_idx].name) { - /* Child is initialized */ - child_pb = &pb->child_pbs[pb_type_idx][pb_idx]; - } - child_pb_graph_node = - &pb_node->child_pb_graph_nodes[pb_mode][pb_type_idx][pb_idx]; - - power_usage_pb(&power_usage_sub, child_pb, - child_pb_graph_node); - power_add_usage(&power_usage_children, &power_usage_sub); - } - } - // Add to power of this PB - power_add_usage(power_usage, &power_usage_children); - - // Add to power of this mode - power_add_usage( - &pb_node->pb_type->modes[pb_mode].mode_power->power_usage, - &power_usage_children); - } - } - - power_add_usage(&pb_node->pb_type->pb_type_power->power_usage, power_usage); -} - -/* Resets the power stats for all physical blocks */ -static void power_reset_pb_type(t_pb_type * pb_type) { - int mode_idx; - int child_idx; - int interc_idx; - - power_zero_usage(&pb_type->pb_type_power->power_usage); - power_zero_usage(&pb_type->pb_type_power->power_usage_bufs_wires); - - for (mode_idx = 0; mode_idx < pb_type->num_modes; mode_idx++) { - power_zero_usage(&pb_type->modes[mode_idx].mode_power->power_usage); - - for (child_idx = 0; - child_idx < pb_type->modes[mode_idx].num_pb_type_children; - child_idx++) { - power_reset_pb_type( - &pb_type->modes[mode_idx].pb_type_children[child_idx]); - } - for (interc_idx = 0; - interc_idx < pb_type->modes[mode_idx].num_interconnect; - interc_idx++) { - power_zero_usage( - &pb_type->modes[mode_idx].interconnect[interc_idx].interconnect_power->power_usage); - } - } -} - -/** - * Resets the power usage for all tile types - */ -static void power_reset_tile_usage(void) { - int type_idx; - - for (type_idx = 0; type_idx < num_types; type_idx++) { - if (type_descriptors[type_idx].pb_type) { - power_reset_pb_type(type_descriptors[type_idx].pb_type); - } - } -} - -/* - * Calcultes the power usage of all tiles in the FPGA - */ -static void power_usage_blocks(t_power_usage * power_usage) { - int x, y, z; - - power_zero_usage(power_usage); - - power_reset_tile_usage(); - - /* Loop through all grid locations */ - for (x = 0; x < nx + 2; x++) { - for (y = 0; y < ny + 2; y++) { - - if ((grid[x][y].offset != 0) || (grid[x][y].type == EMPTY_TYPE)) { - continue; - } - - for (z = 0; z < grid[x][y].type->capacity; z++) { - t_pb * pb = NULL; - t_power_usage pb_power; - - if (grid[x][y].blocks[z] != OPEN) { - pb = block[grid[x][y].blocks[z]].pb; - } - - /* Calculate power of this CLB */ - power_usage_pb(&pb_power, pb, grid[x][y].type->pb_graph_head); - power_add_usage(power_usage, &pb_power); - } - } - } - return; -} - -/** - * Calculates the total power usage from the clock network - */ -static void power_usage_clock(t_power_usage * power_usage, - t_clock_arch * clock_arch) { - int clock_idx; - - /* Initialization */ - power_usage->dynamic = 0.; - power_usage->leakage = 0.; - - /* if no global clock, then return */ - if (clock_arch->num_global_clocks == 0) { - return; - } - - for (clock_idx = 0; clock_idx < clock_arch->num_global_clocks; - clock_idx++) { - t_power_usage clock_power; - - /* Assume the global clock is active even for combinational circuits */ - if (clock_arch->num_global_clocks == 1) { - if (clock_arch->clock_inf[clock_idx].dens == 0) { - clock_arch->clock_inf[clock_idx].dens = 2; - clock_arch->clock_inf[clock_idx].prob = 0.5; - - // This will need to change for multi-clock - clock_arch->clock_inf[clock_idx].period = g_solution_inf.T_crit; - } - } - /* find the power dissipated by each clock network */ - power_usage_clock_single(&clock_power, - &clock_arch->clock_inf[clock_idx]); - power_add_usage(power_usage, &clock_power); - } - - return; -} - -/** - * Calculates the power from a single spine-and-rib global clock - */ -static void power_usage_clock_single(t_power_usage * power_usage, - t_clock_network * single_clock) { - - /* - * - * The following code assumes a spine-and-rib clock network as shown below. - * This is comprised of 3 main combonents: - * 1. A single wire from the io pad to the center of the chip - * 2. A H-structure which provides a 'spine' to all 4 quadrants - * 3. Ribs connect each spine with an entire column of blocks - - ___________________ - | | - | |_|_|_2__|_|_|_ | - | | | | | | | | | - | |3| | | | | | | - | | | - | | | | | | | | | - | |_|_|__|_|_|_|_ | - | | | | | | | | | - |_______1|________| - * It is assumed that there are a single-inverter buffers placed along each wire, - * with spacing equal to the FPGA block size (1 buffer/block) */ - t_power_usage clock_buffer_power; - int length; - t_power_usage buffer_power; - t_power_usage wire_power; - float C_segment; - float buffer_size; - - power_usage->dynamic = 0.; - power_usage->leakage = 0.; - - /* Check if this clock is active - this is used for calculating leakage */ - if (single_clock->dens) { - } else { - assert(0); - } - - C_segment = g_power_commonly_used->tile_length * single_clock->C_wire; - if (single_clock->autosize_buffer) { - buffer_size = 1 + C_segment / g_power_commonly_used->INV_1X_C_in; - } else { - buffer_size = single_clock->buffer_size; - } - - /* Calculate the capacitance and leakage power for the clock buffer */ - power_usage_inverter(&clock_buffer_power, single_clock->dens, - single_clock->prob, buffer_size, single_clock->period); - - length = 0; - - /* 1. IO to chip center */ - length += (ny + 2) / 2; - - /* 2. H-Tree to 4 quadrants */ - length += ny / 2 + 2 * nx; - - /* 3. Ribs - to */ - length += nx / 2 * ny; - - buffer_power.dynamic = length * clock_buffer_power.dynamic; - buffer_power.leakage = length * clock_buffer_power.leakage; - - power_add_usage(power_usage, &buffer_power); - power_component_add_usage(&buffer_power, POWER_COMPONENT_CLOCK_BUFFER); - - power_usage_wire(&wire_power, length * C_segment, single_clock->dens, - single_clock->period); - power_add_usage(power_usage, &wire_power); - power_component_add_usage(&wire_power, POWER_COMPONENT_CLOCK_WIRE); - - return; -} - -/* Frees a multiplexer graph */ -static void dealloc_mux_graph(t_mux_node * node) { - dealloc_mux_graph_rec(node); - free(node); -} - -static void dealloc_mux_graph_rec(t_mux_node * node) { - int child_idx; - - /* Dealloc Children */ - if (node->level != 0) { - for (child_idx = 0; child_idx < node->num_inputs; child_idx++) { - dealloc_mux_graph_rec(&node->children[child_idx]); - } - free(node->children); - } -} - -/** - * Calculates the power of the entire routing fabric (not local routing - */ -static void power_usage_routing(t_power_usage * power_usage, - t_det_routing_arch * routing_arch, t_segment_inf * segment_inf) { - int rr_node_idx; - int net_idx; - int edge_idx; - - power_zero_usage(power_usage); - - /* Reset routing statistics */ - g_power_commonly_used->num_sb_buffers = 0; - g_power_commonly_used->total_sb_buffer_size = 0.; - g_power_commonly_used->num_cb_buffers = 0; - g_power_commonly_used->total_cb_buffer_size = 0.; - - /* Reset rr graph net indices */ - for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { - rr_node[rr_node_idx].net_num = OPEN; - rr_node_power[rr_node_idx].num_inputs = 0; - rr_node_power[rr_node_idx].selected_input = 0; - } - - /* Populate net indices into rr graph */ - for (net_idx = 0; net_idx < num_nets; net_idx++) { - struct s_trace * trace; - - for (trace = trace_head[net_idx]; trace != NULL; trace = trace->next) { - rr_node_power[trace->index].visited = FALSE; - } - } - - /* Populate net indices into rr graph */ - for (net_idx = 0; net_idx < num_nets; net_idx++) { - /* Xifan TANG: Skip the global nets and dangling nets*/ - if ((FALSE == clb_net[net_idx].is_global)||(FALSE == clb_net[net_idx].num_sinks)) { - continue; - } - struct s_trace * trace; - - for (trace = trace_head[net_idx]; trace != NULL; trace = trace->next) { - t_rr_node * node = &rr_node[trace->index]; - t_rr_node_power * node_power = &rr_node_power[trace->index]; - - if (node_power->visited) { - continue; - } - - node->net_num = net_idx; - - for (edge_idx = 0; edge_idx < node->num_edges; edge_idx++) { - if (node->edges[edge_idx] != OPEN) { - t_rr_node * next_node = &rr_node[node->edges[edge_idx]]; - t_rr_node_power * next_node_power = - &rr_node_power[node->edges[edge_idx]]; - - switch (next_node->type) { - case CHANX: - case CHANY: - case IPIN: - if (next_node->net_num == node->net_num) { - next_node_power->selected_input = - next_node_power->num_inputs; - } - next_node_power->in_dens[next_node_power->num_inputs] = - clb_net_density(node->net_num); - next_node_power->in_prob[next_node_power->num_inputs] = - clb_net_prob(node->net_num); - next_node_power->num_inputs++; - if (next_node_power->num_inputs > next_node->fan_in) { - printf("%d %d\n", next_node_power->num_inputs, - next_node->fan_in); - fflush(0); - assert(0); - } - break; - default: - /* Do nothing */ - break; - } - } - } - node_power->visited = TRUE; - } - } - - /* Calculate power of all routing entities */ - for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { - t_power_usage sub_power_usage; - t_rr_node * node = &rr_node[rr_node_idx]; - t_rr_node_power * node_power = &rr_node_power[rr_node_idx]; - float C_wire; - float buffer_size; - int switch_idx; - int connectionbox_fanout; - int switchbox_fanout; - //float C_per_seg_split; - int wire_length; - - switch (node->type) { - case SOURCE: - case SINK: - case OPIN: - /* No power usage for these types */ - break; - case IPIN: - /* This is part of the connectionbox. The connection box is comprised of: - * - Driver (accounted for at end of CHANX/Y - see below) - * - Multiplexor */ - - if (node->fan_in) { - assert(node_power->in_dens); - assert(node_power->in_prob); - - /* Multiplexor */ - power_usage_mux_multilevel(&sub_power_usage, - power_get_mux_arch(node->fan_in, - g_power_arch->mux_transistor_size), - node_power->in_prob, node_power->in_dens, - node_power->selected_input, TRUE, - g_solution_inf.T_crit); - power_add_usage(power_usage, &sub_power_usage); - power_component_add_usage(&sub_power_usage, - POWER_COMPONENT_ROUTE_CB); - } - break; - case CHANX: - case CHANY: - /* This is a wire driven by a switchbox, which includes: - * - The Multiplexor at the beginning of the wire - * - A buffer, after the mux to drive the wire - * - The wire itself - * - A buffer at the end of the wire, going to switchbox/connectionbox */ - assert(node_power->in_dens); - assert(node_power->in_prob); - - wire_length = 0; - if (node->type == CHANX) { - wire_length = node->xhigh - node->xlow + 1; - } else if (node->type == CHANY) { - wire_length = node->yhigh - node->ylow + 1; - } - C_wire = - wire_length - * segment_inf[rr_indexed_data[node->cost_index].seg_index].Cmetal; - //(double)g_power_commonly_used->tile_length); - assert(node_power->selected_input < node->fan_in); - - /* Multiplexor */ - power_usage_mux_multilevel(&sub_power_usage, - power_get_mux_arch(node->fan_in, - g_power_arch->mux_transistor_size), - node_power->in_prob, node_power->in_dens, - node_power->selected_input, TRUE, g_solution_inf.T_crit); - power_add_usage(power_usage, &sub_power_usage); - power_component_add_usage(&sub_power_usage, - POWER_COMPONENT_ROUTE_SB); - - /* Buffer Size */ - switch (switch_inf[node_power->driver_switch_type].power_buffer_type) { - case POWER_BUFFER_TYPE_AUTO: - /* - C_per_seg_split = ((float) node->num_edges - * g_power_commonly_used->INV_1X_C_in + C_wire); - // / (float) g_power_arch->seg_buffer_split; - buffer_size = power_buffer_size_from_logical_effort( - C_per_seg_split); - buffer_size = max(buffer_size, 1.0F); - */ - buffer_size = power_calc_buffer_size_from_Cout( - switch_inf[node_power->driver_switch_type].Cout); - break; - case POWER_BUFFER_TYPE_ABSOLUTE_SIZE: - buffer_size = - switch_inf[node_power->driver_switch_type].power_buffer_size; - buffer_size = max(buffer_size, 1.0F); - break; - case POWER_BUFFER_TYPE_NONE: - buffer_size = 0.; - break; - default: - buffer_size = 0.; - assert(0); - break; - } - - g_power_commonly_used->num_sb_buffers++; - g_power_commonly_used->total_sb_buffer_size += buffer_size; - - /* - g_power_commonly_used->num_sb_buffers += - g_power_arch->seg_buffer_split; - g_power_commonly_used->total_sb_buffer_size += buffer_size - * g_power_arch->seg_buffer_split; - */ - - /* Buffer */ - power_usage_buffer(&sub_power_usage, buffer_size, - node_power->in_prob[node_power->selected_input], - node_power->in_dens[node_power->selected_input], TRUE, - g_solution_inf.T_crit); - power_add_usage(power_usage, &sub_power_usage); - power_component_add_usage(&sub_power_usage, - POWER_COMPONENT_ROUTE_SB); - - /* Wire Capacitance */ - power_usage_wire(&sub_power_usage, C_wire, - clb_net_density(node->net_num), g_solution_inf.T_crit); - power_add_usage(power_usage, &sub_power_usage); - power_component_add_usage(&sub_power_usage, - POWER_COMPONENT_ROUTE_GLB_WIRE); - - /* Determine types of switches that this wire drives */ - connectionbox_fanout = 0; - switchbox_fanout = 0; - for (switch_idx = 0; switch_idx < node->num_edges; switch_idx++) { - if (node->switches[switch_idx] - == routing_arch->wire_to_ipin_switch) { - connectionbox_fanout++; - } else if (node->switches[switch_idx] - == routing_arch->delayless_switch) { - /* Do nothing */ - } else { - switchbox_fanout++; - } - } - - /* Buffer to next Switchbox */ - if (switchbox_fanout) { - buffer_size = power_buffer_size_from_logical_effort( - switchbox_fanout * g_power_commonly_used->NMOS_1X_C_d); - power_usage_buffer(&sub_power_usage, buffer_size, - 1 - node_power->in_prob[node_power->selected_input], - node_power->in_dens[node_power->selected_input], FALSE, - g_solution_inf.T_crit); - power_add_usage(power_usage, &sub_power_usage); - power_component_add_usage(&sub_power_usage, - POWER_COMPONENT_ROUTE_SB); - } - - /* Driver for ConnectionBox */ - if (connectionbox_fanout) { - - buffer_size = power_buffer_size_from_logical_effort( - connectionbox_fanout - * g_power_commonly_used->NMOS_1X_C_d); - - power_usage_buffer(&sub_power_usage, buffer_size, - node_power->in_dens[node_power->selected_input], - 1 - node_power->in_prob[node_power->selected_input], - FALSE, g_solution_inf.T_crit); - power_add_usage(power_usage, &sub_power_usage); - power_component_add_usage(&sub_power_usage, - POWER_COMPONENT_ROUTE_CB); - - g_power_commonly_used->num_cb_buffers++; - g_power_commonly_used->total_cb_buffer_size += buffer_size; - } - break; - case INTRA_CLUSTER_EDGE: - assert(0); - break; - default: - power_log_msg(POWER_LOG_WARNING, - "The global routing-resource graph contains an unknown node type."); - break; - } - } -} - -static -void power_alloc_and_init_pb_pin(t_pb_graph_pin * pin) { - int port_idx; - t_port * port_to_find; - t_pb_graph_node * node = pin->parent_node; - boolean found; - - pin->pin_power = (t_pb_graph_pin_power*) malloc( - sizeof(t_pb_graph_pin_power)); - pin->pin_power->C_wire = 0.; - pin->pin_power->buffer_size = 0.; - pin->pin_power->scaled_by_pin = NULL; - - if (pin->port->port_power->scaled_by_port) { - - port_to_find = pin->port->port_power->scaled_by_port; - - /*pin->pin_power->scaled_by_pin = - get_pb_graph_node_pin_from_model_port_pin( - port_to_find->model_port, - pin->port->port_power->scaled_by_port_pin_idx, - pin->parent_node);*/ - /* Search input, output, clock ports */ - - found = FALSE; - for (port_idx = 0; port_idx < node->num_input_ports; port_idx++) { - if (node->input_pins[port_idx][0].port == port_to_find) { - pin->pin_power->scaled_by_pin = - &node->input_pins[port_idx][pin->port->port_power->scaled_by_port_pin_idx]; - found = TRUE; - break; - } - } - if (!found) { - for (port_idx = 0; port_idx < node->num_output_ports; port_idx++) { - if (node->output_pins[port_idx][0].port == port_to_find) { - pin->pin_power->scaled_by_pin = - &node->output_pins[port_idx][pin->port->port_power->scaled_by_port_pin_idx]; - found = TRUE; - break; - } - } - } - if (!found) { - for (port_idx = 0; port_idx < node->num_clock_ports; port_idx++) { - if (node->clock_pins[port_idx][0].port == port_to_find) { - pin->pin_power->scaled_by_pin = - &node->clock_pins[port_idx][pin->port->port_power->scaled_by_port_pin_idx]; - found = TRUE; - break; - } - } - } - assert(found); - - assert(pin->pin_power->scaled_by_pin); - } -} - -static -void power_init_pb_pins_rec(t_pb_graph_node * pb_node) { - int mode; - int type; - int pb; - int port_idx; - int pin_idx; - - for (port_idx = 0; port_idx < pb_node->num_input_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_input_pins[port_idx]; - pin_idx++) { - power_alloc_and_init_pb_pin( - &pb_node->input_pins[port_idx][pin_idx]); - } - } - - for (port_idx = 0; port_idx < pb_node->num_output_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_output_pins[port_idx]; - pin_idx++) { - power_alloc_and_init_pb_pin( - &pb_node->output_pins[port_idx][pin_idx]); - } - } - - for (port_idx = 0; port_idx < pb_node->num_clock_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_clock_pins[port_idx]; - pin_idx++) { - power_alloc_and_init_pb_pin( - &pb_node->clock_pins[port_idx][pin_idx]); - } - } - - for (mode = 0; mode < pb_node->pb_type->num_modes; mode++) { - for (type = 0; - type < pb_node->pb_type->modes[mode].num_pb_type_children; - type++) { - for (pb = 0; - pb - < pb_node->pb_type->modes[mode].pb_type_children[type].num_pb; - pb++) { - power_init_pb_pins_rec( - &pb_node->child_pb_graph_nodes[mode][type][pb]); - } - } - } -} - -static -void power_pb_pins_init() { - int type_idx; - - for (type_idx = 0; type_idx < num_types; type_idx++) { - if (type_descriptors[type_idx].pb_graph_head) { - power_init_pb_pins_rec(type_descriptors[type_idx].pb_graph_head); - } - } -} - -static -void power_routing_init(t_det_routing_arch * routing_arch) { - int net_idx; - int rr_node_idx; - int max_fanin; - int max_IPIN_fanin; - int max_seg_to_IPIN_fanout; - int max_seg_to_seg_fanout; - int max_seg_fanout; - - /* Copy probability/density values to new netlist */ - for (net_idx = 0; net_idx < num_nets; net_idx++) { - if (!clb_net[net_idx].net_power) { - clb_net[net_idx].net_power = new t_net_power; - } - clb_net[net_idx].net_power->probability = - vpack_net[clb_to_vpack_net_mapping[net_idx]].net_power->probability; - clb_net[net_idx].net_power->density = - vpack_net[clb_to_vpack_net_mapping[net_idx]].net_power->density; - } - - /* Initialize RR Graph Structures */ - rr_node_power = (t_rr_node_power*) my_calloc(num_rr_nodes, - sizeof(t_rr_node_power)); - for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { - rr_node_power[rr_node_idx].driver_switch_type = OPEN; - - } - - /* Initialize Mux Architectures */ - max_fanin = 0; - max_IPIN_fanin = 0; - max_seg_to_seg_fanout = 0; - max_seg_to_IPIN_fanout = 0; - for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { - int switch_idx; - int fanout_to_IPIN = 0; - int fanout_to_seg = 0; - t_rr_node * node = &rr_node[rr_node_idx]; - t_rr_node_power * node_power = &rr_node_power[rr_node_idx]; - - switch (node->type) { - case IPIN: - max_IPIN_fanin = max(max_IPIN_fanin, - static_cast(node->fan_in)); - max_fanin = max(max_fanin, static_cast(node->fan_in)); - - node_power->in_dens = (float*) my_calloc(node->fan_in, - sizeof(float)); - node_power->in_prob = (float*) my_calloc(node->fan_in, - sizeof(float)); - break; - case CHANX: - case CHANY: - for (switch_idx = 0; switch_idx < node->num_edges; switch_idx++) { - if (node->switches[switch_idx] - == routing_arch->wire_to_ipin_switch) { - fanout_to_IPIN++; - } else if (node->switches[switch_idx] - != routing_arch->delayless_switch) { - fanout_to_seg++; - } - } - max_seg_to_IPIN_fanout = max(max_seg_to_IPIN_fanout, - fanout_to_IPIN); - max_seg_to_seg_fanout = max(max_seg_to_seg_fanout, fanout_to_seg); - max_fanin = max(max_fanin, static_cast(node->fan_in)); - - node_power->in_dens = (float*) my_calloc(node->fan_in, - sizeof(float)); - node_power->in_prob = (float*) my_calloc(node->fan_in, - sizeof(float)); - break; - default: - /* Do nothing */ - break; - } - } - g_power_commonly_used->max_routing_mux_size = max_fanin; - g_power_commonly_used->max_IPIN_fanin = max_IPIN_fanin; - g_power_commonly_used->max_seg_to_seg_fanout = max_seg_to_seg_fanout; - g_power_commonly_used->max_seg_to_IPIN_fanout = max_seg_to_IPIN_fanout; - -#if (PRINT_SPICE_COMPARISON) - g_power_commonly_used->max_routing_mux_size = - max(g_power_commonly_used->max_routing_mux_size, 26); -#endif - - /* Populate driver switch type */ - for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { - t_rr_node * node = &rr_node[rr_node_idx]; - int edge_idx; - - for (edge_idx = 0; edge_idx < node->num_edges; edge_idx++) { - if (node->edges[edge_idx] != OPEN) { - if (rr_node_power[node->edges[edge_idx]].driver_switch_type - == OPEN) { - rr_node_power[node->edges[edge_idx]].driver_switch_type = - node->switches[edge_idx]; - /* Xifan TANG: Switch Segment Pattern Support */ - } else if (rr_node[node->edges[edge_idx]].unbuf_switched) { - rr_node_power[node->edges[edge_idx]].driver_switch_type = rr_node[node->edges[edge_idx]].driver_switch; - /* END */ - } else { - assert(rr_node_power[node->edges[edge_idx]].driver_switch_type == node->switches[edge_idx]); - } - } - } - } - - /* Find Max Fanout of Routing Buffer */ - max_seg_fanout = 0; - for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { - t_rr_node * node = &rr_node[rr_node_idx]; - - switch (node->type) { - case CHANX: - case CHANY: - if (node->num_edges > max_seg_fanout) { - max_seg_fanout = node->num_edges; - } - break; - default: - /* Do nothing */ - break; - } - } - g_power_commonly_used->max_seg_fanout = max_seg_fanout; -} - -/** - * Initialization for all power-related functions - */ -boolean power_init(char * power_out_filepath, - char * cmos_tech_behavior_filepath, t_arch * arch, - t_det_routing_arch * routing_arch) { - boolean error = FALSE; - - /* Set global power architecture & options */ - g_power_arch = arch->power; - g_power_commonly_used = new t_power_commonly_used; - g_power_tech = (t_power_tech*) my_malloc(sizeof(t_power_tech)); - g_power_output = (t_power_output*) my_malloc(sizeof(t_power_output)); - - /* Set up Logs */ - g_power_output->num_logs = POWER_LOG_NUM_TYPES; - g_power_output->logs = (t_log*) my_calloc(g_power_output->num_logs, - sizeof(t_log)); - g_power_output->logs[POWER_LOG_ERROR].name = my_strdup("Errors"); - g_power_output->logs[POWER_LOG_WARNING].name = my_strdup("Warnings"); - - /* Initialize output file */ - if (!error) { - g_power_output->out = NULL; - g_power_output->out = my_fopen(power_out_filepath, "w", 0); - if (!g_power_output->out) { - error = TRUE; - } - } - - /* Load technology properties */ - power_tech_init(cmos_tech_behavior_filepath); - - /* Low-Level Initialization */ - power_lowlevel_init(); - - /* Initialize sub-modules */ - power_components_init(); - - /* Perform callibration */ - power_callibrate(); - - /* Initialize routing information */ - power_routing_init(routing_arch); - -// Allocates power structures for each pb pin - power_pb_pins_init(); - - /* Size all components */ - power_sizing_init(arch); - - //power_print_spice_comparison(); - - return error; -} - -/** - * Uninitialize power module - */ -boolean power_uninit(void) { - int mux_size; - int log_idx; - int rr_node_idx; - int msg_idx; - boolean error = FALSE; - - for (rr_node_idx = 0; rr_node_idx < num_rr_nodes; rr_node_idx++) { - t_rr_node * node = &rr_node[rr_node_idx]; - t_rr_node_power * node_power = &rr_node_power[rr_node_idx]; - - switch (node->type) { - case CHANX: - case CHANY: - case IPIN: - if (node->fan_in) { - free(node_power->in_dens); - free(node_power->in_prob); - } - break; - default: - /* Do nothing */ - break; - } - } - free(rr_node_power); - - /* Free mux architectures */ - for (std::map::iterator it = - g_power_commonly_used->mux_info.begin(); - it != g_power_commonly_used->mux_info.end(); it++) { - t_power_mux_info * mux_info = it->second; - for (mux_size = 1; mux_size <= mux_info->mux_arch_max_size; - mux_size++) { - dealloc_mux_graph(mux_info->mux_arch[mux_size].mux_graph_head); - } - delete mux_info; - } - delete g_power_commonly_used; - - if (g_power_output->out) { - fclose(g_power_output->out); - } - - /* Free logs */ - for (log_idx = 0; log_idx < g_power_output->num_logs; log_idx++) { - for (msg_idx = 0; msg_idx < g_power_output->logs[log_idx].num_messages; - msg_idx++) { - free(g_power_output->logs[log_idx].messages[msg_idx]); - } - free(g_power_output->logs[log_idx].messages); - free(g_power_output->logs[log_idx].name); - } - free(g_power_output->logs); - free(g_power_output); - - return error; -} - -#if 0 -/** - * Prints the power of all pb structures, in an xml format that matches the archicture file - */ -static void power_print_pb_usage_recursive(FILE * fp, t_pb_type * type, - int indent_level, float parent_power, float total_power) { - int mode_idx; - int mode_indent; - int child_idx; - int interc_idx; - float pb_type_power; - - pb_type_power = type->pb_type_power->power_usage.dynamic - + type->pb_type_power->power_usage.leakage; - - print_tabs(fp, indent_level); - fprintf(fp, - "\n", - type->name, pb_type_power, pb_type_power / parent_power * 100, - pb_type_power / total_power * 100, - type->pb_type_power->power_usage.dynamic / pb_type_power); - - mode_indent = 0; - if (type->num_modes > 1) { - mode_indent = 1; - } - - for (mode_idx = 0; mode_idx < type->num_modes; mode_idx++) { - float mode_power; - mode_power = type->modes[mode_idx].mode_power->power_usage.dynamic - + type->modes[mode_idx].mode_power->power_usage.leakage; - - if (type->num_modes > 1) { - print_tabs(fp, indent_level + mode_indent); - fprintf(fp, - "\n", - type->modes[mode_idx].name, mode_power, - mode_power / pb_type_power * 100, - mode_power / total_power * 100, - type->modes[mode_idx].mode_power->power_usage.dynamic - / mode_power); - } - - if (type->modes[mode_idx].num_interconnect) { - /* Sum the interconnect power */ - t_power_usage interc_power_usage; - float interc_total_power; - - power_zero_usage(&interc_power_usage); - for (interc_idx = 0; - interc_idx < type->modes[mode_idx].num_interconnect; - interc_idx++) { - power_add_usage(&interc_power_usage, - &type->modes[mode_idx].interconnect[interc_idx].interconnect_power->power_usage); - } - interc_total_power = interc_power_usage.dynamic - + interc_power_usage.leakage; - - /* All interconnect */ - print_tabs(fp, indent_level + mode_indent + 1); - fprintf(fp, - "\n", - interc_total_power, interc_total_power / mode_power * 100, - interc_total_power / total_power * 100, - interc_power_usage.dynamic / interc_total_power); - for (interc_idx = 0; - interc_idx < type->modes[mode_idx].num_interconnect; - interc_idx++) { - float interc_power = - type->modes[mode_idx].interconnect[interc_idx].interconnect_power->power_usage.dynamic - + type->modes[mode_idx].interconnect[interc_idx].interconnect_power->power_usage.leakage; - /* Each interconnect */ - print_tabs(fp, indent_level + mode_indent + 2); - fprintf(fp, - "<%s name=\"%s\" P=\"%.4g\" P_parent=\"%.3g\" P_total=\"%.3g\" P_dyn=\"%.3g\"/>\n", - interconnect_type_name( - type->modes[mode_idx].interconnect[interc_idx].type), - type->modes[mode_idx].interconnect[interc_idx].name, - interc_power, interc_power / interc_total_power * 100, - interc_power / total_power * 100, - type->modes[mode_idx].interconnect[interc_idx].interconnect_power->power_usage.dynamic - / interc_power); - } - print_tabs(fp, indent_level + mode_indent + 1); - fprintf(fp, "\n"); - } - - for (child_idx = 0; - child_idx < type->modes[mode_idx].num_pb_type_children; - child_idx++) { - power_print_pb_usage_recursive(fp, - &type->modes[mode_idx].pb_type_children[child_idx], - indent_level + mode_indent + 1, - type->modes[mode_idx].mode_power->power_usage.dynamic - + type->modes[mode_idx].mode_power->power_usage.leakage, - total_power); - } - - if (type->num_modes > 1) { - print_tabs(fp, indent_level + mode_indent); - fprintf(fp, "\n"); - } - } - - print_tabs(fp, indent_level); - fprintf(fp, "\n"); -} - -static void power_print_clb_detailed(FILE * fp) { - int type_idx; - - float clb_power_total = power_component_get_usage_sum( - POWER_COMPONENT_PB); - for (type_idx = 0; type_idx < num_types; type_idx++) { - if (!type_descriptors[type_idx].pb_type) { - continue; - } - - power_print_pb_usage_recursive(fp, type_descriptors[type_idx].pb_type, - 0, clb_power_total, clb_power_total); - } -} -#endif - -/* - static void power_print_stats(FILE * fp) { - fprintf(fp, "Max Segment Fanout: %d\n", - g_power_commonly_used->max_seg_fanout); - fprintf(fp, "Max Segment->Segment Fanout: %d\n", - g_power_commonly_used->max_seg_to_seg_fanout); - fprintf(fp, "Max Segment->IPIN Fanout: %d\n", - g_power_commonly_used->max_seg_to_IPIN_fanout); - fprintf(fp, "Max IPIN fanin: %d\n", g_power_commonly_used->max_IPIN_fanin); - fprintf(fp, "Average SB Buffer Size: %.1f\n", - g_power_commonly_used->total_sb_buffer_size - / (float) g_power_commonly_used->num_sb_buffers); - fprintf(fp, "SB Buffer Transistors: %g\n", - power_count_transistors_buffer( - g_power_commonly_used->total_sb_buffer_size - / (float) g_power_commonly_used->num_sb_buffers)); - fprintf(fp, "Average CB Buffer Size: %.1f\n", - g_power_commonly_used->total_cb_buffer_size - / (float) g_power_commonly_used->num_cb_buffers); - fprintf(fp, "Tile length (um): %.2f\n", - g_power_commonly_used->tile_length * CONVERT_UM_PER_M); - fprintf(fp, "1X Inverter C_in: %g\n", g_power_commonly_used->INV_1X_C_in); - fprintf(fp, "\n"); - } - */ - -static char * power_estimation_method_name( - e_power_estimation_method power_method) { - switch (power_method) { - case POWER_METHOD_UNDEFINED: - return "Undefined"; - case POWER_METHOD_IGNORE: - return "Ignore"; - case POWER_METHOD_AUTO_SIZES: - return "Transistor Auto-Size"; - case POWER_METHOD_SPECIFY_SIZES: - return "Transistor Specify-Size"; - case POWER_METHOD_TOGGLE_PINS: - return "Pin-Toggle"; - case POWER_METHOD_C_INTERNAL: - return "C-Internal"; - case POWER_METHOD_ABSOLUTE: - return "Absolute"; - case POWER_METHOD_SUM_OF_CHILDREN: - return "Sum of Children"; - default: - return "Unkown"; - } -} - -static void power_print_breakdown_pb_rec(FILE * fp, t_pb_type * pb_type, - int indent) { - int mode_idx; - int child_idx; - int i; - char buf[51]; - int child_indent; - int interc_idx; - t_mode * mode; - t_power_usage interc_usage; - e_power_estimation_method est_method = - pb_type->pb_type_power->estimation_method; - float total_power = power_component_get_usage_sum(POWER_COMPONENT_TOTAL); - t_pb_type_power * pb_power = pb_type->pb_type_power; - - for (i = 0; i < indent; i++) { - buf[i] = ' '; - } - strncpy(buf + indent, pb_type->name, 50 - indent); - buf[50] = '\0'; - buf[strlen((pb_type->name)) + indent] = '\0'; - power_print_breakdown_entry(fp, indent, POWER_BREAKDOWN_ENTRY_TYPE_PB, - pb_type->name, power_sum_usage(&pb_power->power_usage), total_power, - power_perc_dynamic(&pb_power->power_usage), - power_estimation_method_name( - pb_type->pb_type_power->estimation_method)); - - if (power_method_is_transistor_level( - pb_type->pb_type_power->estimation_method)) { - /* Local bufs and wires */ - power_print_breakdown_entry(fp, indent + 1, - POWER_BREAKDOWN_ENTRY_TYPE_BUFS_WIRES, "Bufs/Wires", - power_sum_usage(&pb_power->power_usage_bufs_wires), total_power, - power_perc_dynamic(&pb_power->power_usage_bufs_wires), NULL); - } - - if (power_method_is_recursive(est_method)) { - if (pb_type->num_modes > 1) { - child_indent = indent + 2; - } else { - child_indent = indent + 1; - } - - for (mode_idx = 0; mode_idx < pb_type->num_modes; mode_idx++) { - mode = &pb_type->modes[mode_idx]; - - if (pb_type->num_modes > 1) { - power_print_breakdown_entry(fp, indent + 1, - POWER_BREAKDOWN_ENTRY_TYPE_MODE, mode->name, - power_sum_usage(&mode->mode_power->power_usage), - total_power, - power_perc_dynamic(&mode->mode_power->power_usage), - NULL); - } - - /* Interconnect Power */ - power_zero_usage(&interc_usage); - - /* Sum the interconnect */ - if (power_method_is_transistor_level(est_method)) { - for (interc_idx = 0; interc_idx < mode->num_interconnect; - interc_idx++) { - power_add_usage(&interc_usage, - &mode->interconnect[interc_idx].interconnect_power->power_usage); - } - if (mode->num_interconnect) { - power_print_breakdown_entry(fp, child_indent, - POWER_BREAKDOWN_ENTRY_TYPE_INTERC, "Interc:", - power_sum_usage(&interc_usage), total_power, - power_perc_dynamic(&interc_usage), NULL); - } - - /* Print Interconnect Breakdown */ - for (interc_idx = 0; interc_idx < mode->num_interconnect; - interc_idx++) { - t_interconnect * interc = &mode->interconnect[interc_idx]; - if (interc->type == DIRECT_INTERC) { - // no power - skip - } else { - power_print_breakdown_entry(fp, child_indent + 1, - POWER_BREAKDOWN_ENTRY_TYPE_INTERC, interc->name, - power_sum_usage( - &interc->interconnect_power->power_usage), - total_power, - power_perc_dynamic( - &interc->interconnect_power->power_usage), - NULL); - } - } - } - - for (child_idx = 0; - child_idx < pb_type->modes[mode_idx].num_pb_type_children; - child_idx++) { - power_print_breakdown_pb_rec(fp, - &pb_type->modes[mode_idx].pb_type_children[child_idx], - child_indent); - } - } - } -} - -static void power_print_summary(FILE * fp, t_vpr_setup vpr_setup) { - char * arch; - char * arch_new; - - /* Extract filename from full path */ - arch = vpr_setup.FileNameOpts.ArchFile; - - arch_new = strrchr(vpr_setup.FileNameOpts.ArchFile, '/'); - if (arch_new) - arch = arch_new + 1; - - arch_new = strrchr(vpr_setup.FileNameOpts.ArchFile, '\\'); - if (arch_new) - arch = arch_new + 1; - - fprintf(g_power_output->out, "Circuit: %s\n", - vpr_setup.FileNameOpts.CircuitName); - fprintf(g_power_output->out, "Architecture: %s\n", arch); - fprintf(fp, "Technology (nm): %.0f\n", - g_power_tech->tech_size * CONVERT_NM_PER_M); - fprintf(fp, "Voltage: %.2f\n", g_power_tech->Vdd); - fprintf(fp, "Temperature: %g\n", g_power_tech->temperature); - fprintf(fp, "Critical Path: %g\n", g_solution_inf.T_crit); - fprintf(fp, "Size of FPGA: %d x %d\n", nx, ny); - fprintf(fp, "Channel Width: %d\n", g_solution_inf.channel_width); - fprintf(fp, "\n"); -} - -/* - * Top-level function for the power module. - * Calculates the average power of the entire FPGA (watts), - * and prints it to the output file - * - run_time_s: (Return value) The total runtime in seconds (us accuracy) - */ -e_power_ret_code power_total(float * run_time_s, t_vpr_setup vpr_setup, - t_arch * arch, t_det_routing_arch * routing_arch) { - t_power_usage total_power; - t_power_usage sub_power_usage; - clock_t t_start; - clock_t t_end; - t_power_usage clb_power_usage; - - t_start = clock(); - - power_zero_usage(&total_power); - - if (routing_arch->directionality == BI_DIRECTIONAL) { - power_log_msg(POWER_LOG_ERROR, - "Cannot calculate routing power for bi-directional architectures"); - return POWER_RET_CODE_ERRORS; - } - - /* Calculate Power */ - /* Routing */ - power_usage_routing(&sub_power_usage, routing_arch, arch->Segments); - power_add_usage(&total_power, &sub_power_usage); - power_component_add_usage(&sub_power_usage, POWER_COMPONENT_ROUTING); - - /* Clock */ - power_usage_clock(&sub_power_usage, arch->clocks); - power_add_usage(&total_power, &sub_power_usage); - power_component_add_usage(&sub_power_usage, POWER_COMPONENT_CLOCK); - - /* CLBs */ - power_usage_blocks(&clb_power_usage); - power_add_usage(&total_power, &clb_power_usage); - power_component_add_usage(&clb_power_usage, POWER_COMPONENT_PB); - - power_component_add_usage(&total_power, POWER_COMPONENT_TOTAL); - - power_print_title(g_power_output->out, "Summary"); - power_print_summary(g_power_output->out, vpr_setup); - - /* Print Error & Warning Logs */ - output_logs(g_power_output->out, g_power_output->logs, - g_power_output->num_logs); - - //power_print_title(g_power_output->out, "Statistics"); - //power_print_stats(g_power_output->out); - - power_print_title(g_power_output->out, "Power Breakdown"); - power_print_breakdown_summary(g_power_output->out); - - power_print_title(g_power_output->out, "Power Breakdown by PB"); - power_print_breakdown_pb(g_power_output->out); - - //power_print_title(g_power_output->out, "Spice Comparison"); - //power_print_spice_comparison(); - - t_end = clock(); - - *run_time_s = (float) (t_end - t_start) / CLOCKS_PER_SEC; - - /* Return code */ - if (g_power_output->logs[POWER_LOG_ERROR].num_messages) { - return POWER_RET_CODE_ERRORS; - } else if (g_power_output->logs[POWER_LOG_WARNING].num_messages) { - return POWER_RET_CODE_WARNINGS; - } else { - return POWER_RET_CODE_SUCCESS; - } -} - -/** - * Prints the power usage for all components - * - fp: File descripter to print out to - */ -static void power_print_breakdown_summary(FILE * fp) { - power_print_breakdown_entry(fp, 0, POWER_BREAKDOWN_ENTRY_TYPE_TITLE, NULL, - 0., 0., 0., NULL); - power_print_breakdown_component(fp, "Total", POWER_COMPONENT_TOTAL, 0); - fprintf(fp, "\n"); -} - -static void power_print_breakdown_pb(FILE * fp) { - fprintf(fp, - "This sections provides a detailed breakdown of power usage by PB (physical\n" - "block). For each PB, the power is listed, which is the sum power of all\n" - "instances of the block. It also indicates its percentage of total power (entire\n" - "FPGA), as well as the percentage of its power that is dynamic (vs. static). It\n" - "also indicates the method used for power estimation.\n\n" - "The data includes:\n" - "\tModes:\t\tWhen a pb contains multiple modes, each mode is " - "listed, with\n\t\t\t\tits power statistics.\n" - "\tBufs/Wires:\tPower of all local " - "buffers and local wire switching\n" - "\t\t\t\t(transistor-level estimation only).\n" - "\tInterc:\t\tPower of local interconnect multiplexers (transistor-\n" - "\t\t\t\tlevel estimation only)\n\n" - "Description of Estimation Methods:\n" - "\tTransistor Auto-Size: Transistor-level power estimation. Local buffers and\n" - "\t\twire lengths are automatically sized. This is the default estimation\n" - "\t\tmethod.\n" - "\tTransistor Specify-Size: Transistor-level power estimation. Local buffers\n" - "\t\tand wire lengths are only inserted where specified by the user in the\n" - "\t\tarchitecture file.\n" - "\tPin-Toggle: Dynamic power is calculated using enery-per-toggle of the PB\n" - "\t\tinput pins. Static power is absolute.\n" - "\tC-Internal: Dynamic power is calculated using an internal equivalent\n" - "\t\tcapacitance for PB type. Static power is absolute.\n" - "\tAbsolute: Dynamic and static power are absolutes from the architecture file.\n" - "\tSum of Children: Power of PB is only the sum of all child PBs; interconnect\n" - "\t\tbetween the PB and its children is ignored.\n" - "\tIgnore: Power of PB is ignored.\n\n\n"); - - power_print_breakdown_entry(fp, 0, POWER_BREAKDOWN_ENTRY_TYPE_TITLE, NULL, - 0., 0., 0., NULL); - - for (int type_idx = 0; type_idx < num_types; type_idx++) { - if (type_descriptors[type_idx].pb_type) { - power_print_breakdown_pb_rec(g_power_output->out, - type_descriptors[type_idx].pb_type, 0); - } - } - fprintf(fp, "\n"); -} - -/** - * Internal recurseive function, used by power_component_print_usage - */ -static void power_print_breakdown_component(FILE * fp, char * name, - e_power_component_type type, int indent_level) { - power_print_breakdown_entry(fp, indent_level, - POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT, name, - power_sum_usage(&g_power_by_component.components[type]), - power_sum_usage( - &g_power_by_component.components[POWER_COMPONENT_TOTAL]), - power_perc_dynamic(&g_power_by_component.components[type]), NULL); - - switch (type) { - case (POWER_COMPONENT_TOTAL): - power_print_breakdown_component(fp, "Routing", POWER_COMPONENT_ROUTING, - indent_level + 1); - power_print_breakdown_component(fp, "PB Types", POWER_COMPONENT_PB, - indent_level + 1); - power_print_breakdown_component(fp, "Clock", POWER_COMPONENT_CLOCK, - indent_level + 1); - break; - case (POWER_COMPONENT_ROUTING): - power_print_breakdown_component(fp, "Switch Box", - POWER_COMPONENT_ROUTE_SB, indent_level + 1); - power_print_breakdown_component(fp, "Connection Box", - POWER_COMPONENT_ROUTE_CB, indent_level + 1); - power_print_breakdown_component(fp, "Global Wires", - POWER_COMPONENT_ROUTE_GLB_WIRE, indent_level + 1); - break; - case (POWER_COMPONENT_CLOCK): - /* - power_print_breakdown_component(fp, "Clock Buffers", - POWER_COMPONENT_CLOCK_BUFFER, indent_level + 1); - power_print_breakdown_component(fp, "Clock Wires", - POWER_COMPONENT_CLOCK_WIRE, indent_level + 1); - */ - break; - case (POWER_COMPONENT_PB): - power_print_breakdown_component(fp, "Primitives", - POWER_COMPONENT_PB_PRIMITIVES, indent_level + 1); - power_print_breakdown_component(fp, "Interc Structures", - POWER_COMPONENT_PB_INTERC_MUXES, indent_level + 1); - power_print_breakdown_component(fp, "Buffers and Wires", - POWER_COMPONENT_PB_BUFS_WIRE, indent_level + 1); - power_print_breakdown_component(fp, "Other Estimation Methods", - POWER_COMPONENT_PB_OTHER, indent_level + 1); - break; - default: - break; - } -} - -static void power_print_breakdown_entry(FILE * fp, int indent, - e_power_breakdown_entry_type type, char * name, float power, - float total_power, float perc_dyn, char * method) { - const int buf_size = 32; - char buf[buf_size]; - - switch (type) { - case POWER_BREAKDOWN_ENTRY_TYPE_TITLE: - fprintf(fp, "%-*s%-12s%-12s%-12s%-12s\n\n", buf_size, "Component", - "Power (W)", "%-Total", "%-Dynamic", "Method"); - break; - case POWER_BREAKDOWN_ENTRY_TYPE_MODE: - for (int i = 0; i < indent; i++) - buf[i] = ' '; - strcpy(buf + indent, "Mode:"); - strncpy(buf + indent + 5, name, buf_size - indent - 6); - fprintf(fp, "%-*s%-12.4g%-12.4g%-12.4g\n", buf_size, buf, power, - power / total_power, perc_dyn); - break; - case POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT: - case POWER_BREAKDOWN_ENTRY_TYPE_INTERC: - case POWER_BREAKDOWN_ENTRY_TYPE_BUFS_WIRES: - for (int i = 0; i < indent; i++) - buf[i] = ' '; - strncpy(buf + indent, name, buf_size - indent - 1); - buf[buf_size - 1] = '\0'; - - fprintf(fp, "%-*s%-12.4g%-12.4g%-12.4g\n", buf_size, buf, power, - power / total_power, perc_dyn); - break; - case POWER_BREAKDOWN_ENTRY_TYPE_PB: - for (int i = 0; i < indent; i++) - buf[i] = ' '; - strncpy(buf + indent, name, buf_size - indent - 1); - buf[buf_size - 1] = '\0'; - - fprintf(fp, "%-*s%-12.4g%-12.4g%-12.4g%-12s\n", buf_size, buf, power, - power / total_power, perc_dyn, method); - break; - default: - break; - } -} diff --git a/vpr7_x2p/vpr/SRC/power/power.h b/vpr7_x2p/vpr/SRC/power/power.h deleted file mode 100644 index 331db2eed..000000000 --- a/vpr7_x2p/vpr/SRC/power/power.h +++ /dev/null @@ -1,319 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/** - * This is the top-level file for power estimation in VTR - */ - -#ifndef __POWER_H__ -#define __POWER_H__ - -/************************* INCLUDES *********************************/ -#include - -#include "vpr_types.h" -#include "PowerSpicedComponent.h" - -/************************* DEFINES ***********************************/ -/* Maximum size of logs */ -#define MAX_LOGS 10000 - -/* Default clock behaviour */ -#define CLOCK_PROB 0.5 -#define CLOCK_DENS 2 - -/************************* ENUMS ************************************/ - -/* Return code used by power functions */ -typedef enum { - POWER_RET_CODE_SUCCESS = 0, POWER_RET_CODE_ERRORS, POWER_RET_CODE_WARNINGS -} e_power_ret_code; - -/* Power log types */ -typedef enum { - POWER_LOG_ERROR, POWER_LOG_WARNING, POWER_LOG_NUM_TYPES -} e_power_log_type; - -/* Multiplexer select encoding types */ -#if 0 -typedef enum { - ENCODING_ONE_HOT, /* One SRAM bit per mux input */ - ENCODING_DECODER /* Log2(mux_inputs) SRAM bits */ -}e_encoding_type; -#endif - -/************************* STRUCTS **********************************/ -typedef struct s_power_output t_power_output; -typedef struct s_log t_log; -typedef struct s_power_commonly_used t_power_commonly_used; -typedef struct s_power_mux_volt_inf t_power_mux_volt_inf; -typedef struct s_power_mux_volt_pair t_power_mux_volt_pair; -typedef struct s_power_nmos_leakages t_power_nmos_leakages; -typedef struct s_power_nmos_leakage_pair t_power_nmos_leakage_pair; -typedef struct s_power_buffer_sc_levr_inf t_power_buffer_sc_levr_inf; -typedef struct s_power_tech t_power_tech; -typedef struct s_transistor_inf t_transistor_inf; -typedef struct s_transistor_size_inf t_transistor_size_inf; -typedef struct s_rr_node_power t_rr_node_power; -typedef struct s_power_buffer_size_inf t_power_buffer_size_inf; -typedef struct s_power_buffer_strength_inf t_power_buffer_strength_inf; -typedef struct s_mux_node t_mux_node; -typedef struct s_mux_arch t_mux_arch; -typedef struct s_solution_inf t_solution_inf; -typedef struct s_power_nmos_mux_inf t_power_nmos_mux_inf; -typedef struct s_power_nmos_leakage_inf t_power_nmos_leakage_inf; -typedef struct s_power_mux_info t_power_mux_info; - -/* Information on the solution obtained by VPR */ -struct s_solution_inf { - float T_crit; - int channel_width; -}; - -/* two types of transisters */ -typedef enum { - NMOS, PMOS -} e_tx_type; - -/* Information for a given transistor size */ -struct s_transistor_size_inf { - float size; - - /* Subthreshold leakage, for Vds = Vdd */ - float leakage_subthreshold; - - /* Gate leakage for Vgd/Vgs = Vdd */ - float leakage_gate; - - /* Gate, Source, Drain capacitance */ - float C_g; - float C_s; - float C_d; -}; - -/** - * Transistor information - */ -struct s_transistor_inf { - int num_size_entries; - t_transistor_size_inf * size_inf; /* Array of transistor sizes */ - t_transistor_size_inf * long_trans_inf; /* Long transistor (W=1,L=2) */ -}; - -struct s_power_nmos_mux_inf { - float nmos_size; - int max_mux_sl_size; - t_power_mux_volt_inf * mux_voltage_inf; -}; - -struct s_power_nmos_leakage_inf { - float nmos_size; - int num_leakage_pairs; - t_power_nmos_leakage_pair * leakage_pairs; -}; - -/* CMOS technology properties, populated from data in xml file */ -struct s_power_tech { - float PN_ratio; /* Ratio of PMOS to NMOS in inverter */ - float Vdd; - - float tech_size; /* Tech size in nm, for example 90e-9 for 90nm */ - float temperature; /* Temp in C */ - - t_transistor_inf NMOS_inf; - t_transistor_inf PMOS_inf; - - /* Pass Multiplexor Voltage Information */ - int num_nmos_mux_info; - t_power_nmos_mux_inf * nmos_mux_info; - - /* NMOS Leakage by Vds */ - int num_nmos_leakage_info; - t_power_nmos_leakage_inf * nmos_leakage_info; - - /* Buffer Info */ - int max_buffer_size; - t_power_buffer_size_inf * buffer_size_inf; -}; - -/* Buffer information for a given size (# of stages) */ -struct s_power_buffer_size_inf { - int num_strengths; - t_power_buffer_strength_inf * strength_inf; -}; - -/* Set of I/O Voltages for a single-level multiplexer */ -struct s_power_mux_volt_inf { - int num_voltage_pairs; - t_power_mux_volt_pair * mux_voltage_pairs; -}; - -/* Single I/O voltage for a single-level multiplexer */ -struct s_power_mux_volt_pair { - float v_in; - float v_out_min; - float v_out_max; -}; - -/* Buffer information for a given buffer stength */ -struct s_power_buffer_strength_inf { - float stage_gain; - - /* Short circuit factor - no level restorer */ - float sc_no_levr; - - /* Short circuit factors - level restorers */ - int num_levr_entries; - t_power_buffer_sc_levr_inf * sc_levr_inf; -}; - -/* Buffer short-circuit information for a given input mux size */ -struct s_power_buffer_sc_levr_inf { - int mux_size; - - /* Short circuit factor */ - float sc_levr; -}; - -/* Vds/Ids subthreshold leakage pair */ -struct s_power_nmos_leakage_pair { - float v_ds; - float i_ds; -}; - -/* Output details of the power estimation */ -struct s_power_output { - FILE * out; - t_log * logs; - int num_logs; -}; - -struct s_log { - char * name; - char ** messages; - int num_messages; -}; - -struct s_power_mux_info { - /* Mux architecture information for 0..mux_arch_max_size */ - int mux_arch_max_size; - t_mux_arch * mux_arch; -}; - -/** - * Commonly used values that are cached here instead of recalculting each time, - * also includes statistics. - */ -struct s_power_commonly_used { - - /* Capacitances */ - float NMOS_1X_C_g; - float NMOS_1X_C_d; - float NMOS_1X_C_s; - - float PMOS_1X_C_g; - float PMOS_1X_C_d; - float PMOS_1X_C_s; - - float INV_1X_C_in; - float INV_1X_C; - float INV_2X_C; - - /* Component Callibrations Array [0..POWER_CALLIB_COMPONENT_MAX-1] */ - PowerSpicedComponent ** component_callibration; - - /* Subthreshold leakages */ - float NMOS_1X_st_leakage; - float NMOS_2X_st_leakage; - float PMOS_1X_st_leakage; - float PMOS_2X_st_leakage; - - std::map mux_info; - - /* Routing stats */ - int max_routing_mux_size; - int max_IPIN_fanin; - int max_seg_fanout; - int max_seg_to_IPIN_fanout; - int max_seg_to_seg_fanout; - - /* Physical length of a tile (meters) */ - float tile_length; - - /* Size of switch and connection box buffers */ - int num_sb_buffers; - float total_sb_buffer_size; - - int num_cb_buffers; - float total_cb_buffer_size; -}; - -/* 1-to-1 data structure with t_rr_node - */ -struct s_rr_node_power { - boolean visited; /* When traversing netlist, need to track whether the node has been processed */ - float * in_dens; /* Switching density of inputs */ - float * in_prob; /* Static probability of inputs */ - short num_inputs; /* Number of inputs */ - short selected_input; /* Input index that is selected */ - short driver_switch_type; /* Switch type that drives this resource */ -}; - -/* Architecture information for a multiplexer. - * This is used to specify transistor sizes, encoding, etc. - */ -struct s_mux_arch { - int levels; - int num_inputs; - float transistor_size; - //enum e_encoding_type * encoding_types; - t_mux_node * mux_graph_head; -}; - -/* A single-level multiplexer data structure. - * These are combined in a hierarchy to represent - * multi-level multiplexers - */ -struct s_mux_node { - int num_inputs; /* Number of inputs */ - t_mux_node * children; /* Multiplexers that drive the inputs [0..num_inputs-1] */ - int starting_pin_idx; /* Applicable to level 0 only, the overall mux primary input index */ - int level; /* Level in the full multilevel mux - 0 = primary inputs to mux */ - boolean level_restorer; /* Whether the output of this mux is level restored */ -}; - -/************************* GLOBALS **********************************/ -extern t_solution_inf g_solution_inf; -extern t_power_output * g_power_output; -extern t_power_commonly_used * g_power_commonly_used; -extern t_power_tech * g_power_tech; -extern t_power_arch * g_power_arch; - -/************************* FUNCTION DECLARATIONS ********************/ - -/* Call before using power module */ -boolean power_init(char * power_out_filepath, - char * cmos_tech_behavior_filepath, t_arch * arch, - t_det_routing_arch * routing_arch); - -boolean power_uninit(void); - -/* Top-Level Function */ -e_power_ret_code power_total(float * run_time_s, t_vpr_setup vpr_setup, - t_arch * arch, t_det_routing_arch * routing_arch); - -#endif /* __POWER_H__ */ diff --git a/vpr7_x2p/vpr/SRC/power/power_callibrate.c b/vpr7_x2p/vpr/SRC/power/power_callibrate.c deleted file mode 100644 index 471b6cd47..000000000 --- a/vpr7_x2p/vpr/SRC/power/power_callibrate.c +++ /dev/null @@ -1,402 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/* This file provides functions used to verify the power estimations - * againt SPICE. - */ - -/************************* INCLUDES *********************************/ -#include - -#include "power_callibrate.h" -#include "power_components.h" -#include "power_lowlevel.h" -#include "power_util.h" -#include "power_cmos_tech.h" -#include "globals.h" - -/************************* FUNCTION DECLARATIONS ********************/ -static char binary_not(char c); - -/************************* FUNCTION DEFINITIONS *********************/ - -/* This function prints high-activitiy and zero-activity single-cycle - * energy estimations for a variety of components and sizes. - */ -void power_print_spice_comparison(void) { -// - t_power_usage sub_power_usage; -// -// float inv_sizes[5] = { 1, 8, 16, 32, 64 }; -// -// float buffer_sizes[3] = { 16, 25, 64 }; -// - unsigned int LUT_sizes[3] = { 6 }; -// -// float sb_buffer_sizes[6] = { 9, 9, 16, 16, 25, 25 }; -// unsigned int sb_mux_sizes[6] = { 4, 8, 12, 16, 20, 25 }; -// -// unsigned int mux_sizes[5] = { 4, 8, 12, 16, 20 }; -// - unsigned int i, j; - float * dens = NULL; - float * prob = NULL; - char * SRAM_bits = NULL; - int sram_idx; -// - g_solution_inf.T_crit = 1.0e-8; -// -// -// fprintf(g_power_output->out, "Energy of INV (High Activity)\n"); -// for (i = 0; i < (sizeof(inv_sizes) / sizeof(float)); i++) { -// power_usage_inverter(&sub_power_usage, 2, 0.5, inv_sizes[i], -// power_callib_period); -// fprintf(g_power_output->out, "%g\t%g\n", inv_sizes[i], -// (sub_power_usage.dynamic + sub_power_usage.leakage) -// * g_solution_inf.T_crit); -// } -// -// fprintf(g_power_output->out, "Energy of INV (No Activity)\n"); -// for (i = 0; i < (sizeof(inv_sizes) / sizeof(float)); i++) { -// power_usage_inverter(&sub_power_usage, 0, 1, inv_sizes[i], -// power_callib_period); -// fprintf(g_power_output->out, "%g\t%g\n", inv_sizes[i], -// (sub_power_usage.dynamic + sub_power_usage.leakage) -// * g_solution_inf.T_crit); -// } -// } -// -// fprintf(g_power_output->out, "Energy of Mux (High Activity)\n"); -// for (i = 0; i < (sizeof(mux_sizes) / sizeof(int)); i++) { -// t_power_usage mux_power_usage; -// -// power_zero_usage(&mux_power_usage); -// -// dens = (float*) my_realloc(dens, mux_sizes[i] * sizeof(float)); -// prob = (float*) my_realloc(prob, mux_sizes[i] * sizeof(float)); -// for (j = 0; j < mux_sizes[i]; j++) { -// dens[j] = 2; -// prob[j] = 0.5; -// } -// power_usage_mux_multilevel(&mux_power_usage, -// power_get_mux_arch(mux_sizes[i]), prob, dens, 0, FALSE, -// power_callib_period); -// fprintf(g_power_output->out, "%d\t%g\n", mux_sizes[i], -// (mux_power_usage.dynamic + mux_power_usage.leakage) -// * g_solution_inf.T_crit); -// } -// -// fprintf(g_power_output->out, "Energy of Mux (No Activity)\n"); -// for (i = 0; i < (sizeof(mux_sizes) / sizeof(int)); i++) { -// t_power_usage mux_power_usage; -// -// power_zero_usage(&mux_power_usage); -// -// dens = (float*) my_realloc(dens, mux_sizes[i] * sizeof(float)); -// prob = (float*) my_realloc(prob, mux_sizes[i] * sizeof(float)); -// for (j = 0; j < mux_sizes[i]; j++) { -// if (j == 0) { -// dens[j] = 0; -// prob[j] = 1; -// } else { -// dens[j] = 0; -// prob[j] = 0; -// } -// } -// power_usage_mux_multilevel(&mux_power_usage, -// power_get_mux_arch(mux_sizes[i]), prob, dens, 0, FALSE, -// power_callib_period); -// fprintf(g_power_output->out, "%d\t%g\n", mux_sizes[i], -// (mux_power_usage.dynamic + mux_power_usage.leakage) -// * g_solution_inf.T_crit); -// } -// -// fprintf(g_power_output->out, "Energy of Buffer (High Activity)\n"); -// for (i = 0; i < (sizeof(buffer_sizes) / sizeof(float)); i++) { -// power_usage_buffer(&sub_power_usage, buffer_sizes[i], 0.5, 2, FALSE, -// power_callib_period); -// fprintf(g_power_output->out, "%g\t%g\n", buffer_sizes[i], -// (sub_power_usage.dynamic + sub_power_usage.leakage) -// * g_solution_inf.T_crit); -// } -// -// fprintf(g_power_output->out, "Energy of Buffer (No Activity)\n"); -// for (i = 0; i < (sizeof(buffer_sizes) / sizeof(float)); i++) { -// power_usage_buffer(&sub_power_usage, buffer_sizes[i], 1, 0, FALSE, -// power_callib_period); -// fprintf(g_power_output->out, "%g\t%g\n", buffer_sizes[i], -// (sub_power_usage.dynamic + sub_power_usage.leakage) -// * g_solution_inf.T_crit); -// } -// - fprintf(g_power_output->out, "Energy of LUT (High Activity)\n"); - for (i = 0; i < (sizeof(LUT_sizes) / sizeof(int)); i++) { - for (j = 1; j <= LUT_sizes[i]; j++) { - SRAM_bits = (char*) my_realloc(SRAM_bits, - ((1 << j) + 1) * sizeof(char)); - if (j == 1) { - SRAM_bits[0] = '1'; - SRAM_bits[1] = '0'; - } else { - for (sram_idx = 0; sram_idx < (1 << (j - 1)); sram_idx++) { - SRAM_bits[sram_idx + (1 << (j - 1))] = binary_not( - SRAM_bits[sram_idx]); - } - } - SRAM_bits[1 << j] = '\0'; - } - - dens = (float*) my_realloc(dens, LUT_sizes[i] * sizeof(float)); - prob = (float*) my_realloc(prob, LUT_sizes[i] * sizeof(float)); - for (j = 0; j < LUT_sizes[i]; j++) { - dens[j] = 1.0 / (float) LUT_sizes[i]; - prob[j] = 0.5; - } - power_usage_lut(&sub_power_usage, LUT_sizes[i], 1.0, SRAM_bits, prob, - dens, power_callib_period); - - t_power_usage power_usage_mux; - - float p[6] = { 0.5, 0.5, 0.5, 0.5, 0.5, 0.5 }; - float d[6] = { 1, 1, 1, 1, 1, 1 }; - power_usage_mux_multilevel(&power_usage_mux, power_get_mux_arch(6, 1.0), - p, d, 0, TRUE, g_solution_inf.T_crit); - - power_add_usage(&sub_power_usage, &power_usage_mux); - - fprintf(g_power_output->out, "%d\t%g\n", LUT_sizes[i], - power_sum_usage(&sub_power_usage)); - } -// -// fprintf(g_power_output->out, "Energy of LUT (No Activity)\n"); -// for (i = 0; i < (sizeof(LUT_sizes) / sizeof(int)); i++) { -// for (j = 1; j <= LUT_sizes[i]; j++) { -// SRAM_bits = (char*) my_realloc(SRAM_bits, -// ((1 << j) + 1) * sizeof(char)); -// if (j == 1) { -// SRAM_bits[0] = '1'; -// SRAM_bits[1] = '0'; -// } else { -// for (sram_idx = 0; sram_idx < (1 << (j - 1)); sram_idx++) { -// SRAM_bits[sram_idx + (1 << (j - 1))] = binary_not( -// SRAM_bits[sram_idx]); -// } -// } -// SRAM_bits[1 << j] = '\0'; -// } -// -// dens = (float*) my_realloc(dens, LUT_sizes[i] * sizeof(float)); -// prob = (float*) my_realloc(prob, LUT_sizes[i] * sizeof(float)); -// for (j = 0; j < LUT_sizes[i]; j++) { -// dens[j] = 0; -// prob[j] = 1; -// } -// power_usage_lut(&sub_power_usage, LUT_sizes[i], SRAM_bits, prob, dens, -// power_callib_period); -// fprintf(g_power_output->out, "%d\t%g\n", LUT_sizes[i], -// (sub_power_usage.dynamic + sub_power_usage.leakage) -// * g_solution_inf.T_crit * 2); -// } -// - fprintf(g_power_output->out, "Energy of FF (High Activity)\n"); - power_usage_ff(&sub_power_usage, 1.0, 0.5, 3, 0.5, 1, 0.5, 2, - power_callib_period); - fprintf(g_power_output->out, "%g\n", - (sub_power_usage.dynamic + sub_power_usage.leakage)); -// -// fprintf(g_power_output->out, "Energy of FF (No Activity)\n"); -// power_usage_ff(&sub_power_usage, 1, 0, 1, 0, 1, 0, power_callib_period); -// fprintf(g_power_output->out, "%g\n", -// (sub_power_usage.dynamic + sub_power_usage.leakage) -// * g_solution_inf.T_crit * 2); -// -// fprintf(g_power_output->out, "Energy of SB (High Activity)\n"); -// for (i = 0; i < (sizeof(sb_buffer_sizes) / sizeof(float)); i++) { -// t_power_usage sb_power_usage; -// -// power_zero_usage(&sb_power_usage); -// -// dens = (float*) my_realloc(dens, sb_mux_sizes[i] * sizeof(float)); -// prob = (float*) my_realloc(prob, sb_mux_sizes[i] * sizeof(float)); -// for (j = 0; j < sb_mux_sizes[i]; j++) { -// dens[j] = 2; -// prob[j] = 0.5; -// } -// -// power_usage_mux_multilevel(&sub_power_usage, -// power_get_mux_arch(sb_mux_sizes[i]), prob, dens, 0, TRUE, -// power_callib_period); -// power_add_usage(&sb_power_usage, &sub_power_usage); -// -// power_usage_buffer(&sub_power_usage, sb_buffer_sizes[i], 0.5, 2, TRUE, -// power_callib_period); -// power_add_usage(&sb_power_usage, &sub_power_usage); -// -// fprintf(g_power_output->out, "%d\t%.0f\t%g\n", sb_mux_sizes[i], -// sb_buffer_sizes[i], -// (sb_power_usage.dynamic + sb_power_usage.leakage) -// * g_solution_inf.T_crit); -// } -// -// fprintf(g_power_output->out, "Energy of SB (No Activity)\n"); -// for (i = 0; i < (sizeof(sb_buffer_sizes) / sizeof(float)); i++) { -// t_power_usage sb_power_usage; -// -// power_zero_usage(&sb_power_usage); -// -// dens = (float*) my_realloc(dens, sb_mux_sizes[i] * sizeof(float)); -// prob = (float*) my_realloc(prob, sb_mux_sizes[i] * sizeof(float)); -// for (j = 0; j < sb_mux_sizes[i]; j++) { -// if (j == 0) { -// dens[j] = 0; -// prob[j] = 1; -// } else { -// dens[j] = 0; -// prob[j] = 0; -// } -// } -// -// power_usage_mux_multilevel(&sub_power_usage, -// power_get_mux_arch(sb_mux_sizes[i]), prob, dens, 0, TRUE, -// power_callib_period); -// power_add_usage(&sb_power_usage, &sub_power_usage); -// -// power_usage_buffer(&sub_power_usage, sb_buffer_sizes[i], 1, 0, TRUE, -// power_callib_period); -// power_add_usage(&sb_power_usage, &sub_power_usage); -// -// fprintf(g_power_output->out, "%d\t%.0f\t%g\n", sb_mux_sizes[i], -// sb_buffer_sizes[i], -// (sb_power_usage.dynamic + sb_power_usage.leakage) -// * g_solution_inf.T_crit); -//} - -} - -static char binary_not(char c) { - if (c == '1') { - return '0'; - } else { - return '1'; - } -} - -float power_usage_buf_for_callibration(int num_inputs, float transistor_size) { - t_power_usage power_usage; - - assert(num_inputs == 1); - - power_usage_buffer(&power_usage, transistor_size, 0.5, 2.0, FALSE, - power_callib_period); - - return power_sum_usage(&power_usage); -} - -float power_usage_buf_levr_for_callibration(int num_inputs, - float transistor_size) { - t_power_usage power_usage; - - assert(num_inputs == 1); - - power_usage_buffer(&power_usage, transistor_size, 0.5, 2.0, TRUE, - power_callib_period); - - return power_sum_usage(&power_usage); -} - -float power_usage_mux_for_callibration(int num_inputs, float transistor_size) { - t_power_usage power_usage; - float * dens; - float * prob; - - dens = (float*) my_malloc(num_inputs * sizeof(float)); - prob = (float*) my_malloc(num_inputs * sizeof(float)); - for (int i = 0; i < num_inputs; i++) { - dens[i] = 2; - prob[i] = 0.5; - } - - power_usage_mux_multilevel(&power_usage, - power_get_mux_arch(num_inputs, transistor_size), prob, dens, 0, - FALSE, power_callib_period); /* Xifan: turn output_restore to be true */ - - free(dens); - free(prob); - - return power_sum_usage(&power_usage); -} - -float power_usage_lut_for_callibration(int num_inputs, float transistor_size) { - t_power_usage power_usage; - char * SRAM_bits; - float * dens; - float * prob; - int lut_size = num_inputs; - - /* Initialize an SRAM pattern that guarantees the outputs toggle with - * every input toggle. - */ - SRAM_bits = (char*) my_malloc(((1 << lut_size) + 1) * sizeof(char)); - for (int i = 1; i <= lut_size; i++) { - if (i == 1) { - SRAM_bits[0] = '1'; - SRAM_bits[1] = '0'; - } else { - for (int sram_idx = 0; sram_idx < (1 << (i - 1)); sram_idx++) { - SRAM_bits[sram_idx + (1 << (i - 1))] = binary_not( - SRAM_bits[sram_idx]); - } - } - SRAM_bits[1 << i] = '\0'; - } - - dens = (float*) my_malloc(lut_size * sizeof(float)); - prob = (float*) my_malloc(lut_size * sizeof(float)); - for (int i = 0; i < lut_size; i++) { - dens[i] = 1; - prob[i] = 0.5; - } - power_usage_lut(&power_usage, lut_size, transistor_size, SRAM_bits, prob, - dens, power_callib_period); - - free(SRAM_bits); - free(dens); - free(prob); - - return power_sum_usage(&power_usage); -} - -float power_usage_ff_for_callibration(int num_inputs, float transistor_size) { - t_power_usage power_usage; - - assert(num_inputs == 1); - - power_usage_ff(&power_usage, transistor_size, 0.5, 3, 0.5, 1, 0.5, 2, - power_callib_period); - - return power_sum_usage(&power_usage); -} - -void power_callibrate(void) { - /* Buffers and Mux must be done before LUT/FF */ - - g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_BUFFER]->callibrate(); - g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR]->callibrate(); - g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_MUX]->callibrate(); - g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_LUT]->callibrate(); - g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_FF]->callibrate(); -} diff --git a/vpr7_x2p/vpr/SRC/power/power_callibrate.h b/vpr7_x2p/vpr/SRC/power/power_callibrate.h deleted file mode 100644 index 3e6a5d1db..000000000 --- a/vpr7_x2p/vpr/SRC/power/power_callibrate.h +++ /dev/null @@ -1,52 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/* This file provides functions used to verify the power estimations - * againt SPICE. - */ - -#ifndef __POWER_MISC_H__ -#define __POWER_MISC_H__ - -/************************* INCLUDES *********************************/ -#include "power.h" - -/************************* DEFINES **********************************/ -const float power_callib_period = 5e-9; - -/************************* STRUCTS **********************************/ -/************************* ENUMS ************************************/ -typedef enum { - POWER_CALLIB_COMPONENT_BUFFER = 0, - POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR, - POWER_CALLIB_COMPONENT_FF, - POWER_CALLIB_COMPONENT_MUX, - POWER_CALLIB_COMPONENT_LUT, - POWER_CALLIB_COMPONENT_MAX -} e_power_callib_component; - -/************************* FUNCTION DECLARATIONS ********************/ -void power_print_spice_comparison(void); -void power_callibrate(void); -float power_usage_buf_for_callibration(int num_inputs, float transistor_size); -float power_usage_buf_levr_for_callibration(int num_inputs, - float transistor_size); -float power_usage_mux_for_callibration(int num_inputs, float transistor_size); -float power_usage_lut_for_callibration(int num_inputs, float transistor_size); -float power_usage_ff_for_callibration(int num_inputs, float transistor_size); - -#endif diff --git a/vpr7_x2p/vpr/SRC/power/power_cmos_tech.c b/vpr7_x2p/vpr/SRC/power/power_cmos_tech.c deleted file mode 100644 index 62bb73ec3..000000000 --- a/vpr7_x2p/vpr/SRC/power/power_cmos_tech.c +++ /dev/null @@ -1,901 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/** - * This file provides functions relating to the cmos technology. It - * includes functions to read the transistor characteristics from the - * xml file into data structures, and functions to search within - * these data structures. - */ - -/************************* INCLUDES *********************************/ -#include -using namespace std; - -#include - -#include "power_cmos_tech.h" -#include "power.h" -#include "power_util.h" -#include "ezxml.h" -#include "util.h" -#include "read_xml_util.h" -#include "PowerSpicedComponent.h" -#include "power_callibrate.h" - -/************************* GLOBALS **********************************/ -static t_transistor_inf * g_transistor_last_searched; -static t_power_buffer_strength_inf * g_buffer_strength_last_searched; -static t_power_mux_volt_inf * g_mux_volt_last_searched; - -/************************* FUNCTION DECLARATIONS ********************/ - -static void power_tech_load_xml_file(char * cmos_tech_behavior_filepath); -static void process_tech_xml_load_transistor_info(ezxml_t parent); -static void power_tech_xml_load_multiplexer_info(ezxml_t parent); -static void power_tech_xml_load_nmos_st_leakages(ezxml_t parent); -static int power_compare_transistor_size(const void * key_void, - const void * elem_void); -static int power_compare_voltage_pair(const void * key_void, - const void * elem_void); -static int power_compare_leakage_pair(const void * key_void, - const void * elem_void); -//static void power_tech_xml_load_sc(ezxml_t parent); -static int power_compare_buffer_strength(const void * key_void, - const void * elem_void); -static int power_compare_buffer_sc_levr(const void * key_void, - const void * elem_void); -static void power_tech_xml_load_components(ezxml_t parent); -static void power_tech_xml_load_component(ezxml_t parent, - PowerSpicedComponent ** component, char * name, - float (*usage_fn)(int num_inputs, float transistor_size)); -/************************* FUNCTION DEFINITIONS *********************/ - -void power_tech_init(char * cmos_tech_behavior_filepath) { - power_tech_load_xml_file(cmos_tech_behavior_filepath); -} - -/** - * Reads the transistor properties from the .xml file - */ -void power_tech_load_xml_file(char * cmos_tech_behavior_filepath) { - ezxml_t cur, child, prev; - const char * prop; - char msg[BUFSIZE]; - - if (!file_exists(cmos_tech_behavior_filepath)) { - /* .xml transistor characteristics is missing */ - sprintf(msg, - "The CMOS technology behavior file ('%s') does not exist. No power information will be calculated.", - cmos_tech_behavior_filepath); - power_log_msg(POWER_LOG_ERROR, msg); - - g_power_tech->NMOS_inf.num_size_entries = 0; - g_power_tech->NMOS_inf.long_trans_inf = NULL; - g_power_tech->NMOS_inf.size_inf = NULL; - - g_power_tech->PMOS_inf.num_size_entries = 0; - g_power_tech->PMOS_inf.long_trans_inf = NULL; - g_power_tech->PMOS_inf.size_inf = NULL; - - g_power_tech->Vdd = 0.; - g_power_tech->temperature = 85; - g_power_tech->PN_ratio = 1.; - return; - } - cur = ezxml_parse_file(cmos_tech_behavior_filepath); - - prop = FindProperty(cur, "file", TRUE); - ezxml_set_attr(cur, "file", NULL); - - prop = FindProperty(cur, "size", TRUE); - g_power_tech->tech_size = atof(prop); - ezxml_set_attr(cur, "size", NULL); - - child = FindElement(cur, "operating_point", TRUE); - g_power_tech->temperature = GetFloatProperty(child, "temperature", TRUE, 0); - g_power_tech->Vdd = GetFloatProperty(child, "Vdd", TRUE, 0); - FreeNode(child); - - child = FindElement(cur, "p_to_n", TRUE); - g_power_tech->PN_ratio = GetFloatProperty(child, "ratio", TRUE, 0); - FreeNode(child); - - /* Transistor Information */ - child = FindFirstElement(cur, "transistor", TRUE); - process_tech_xml_load_transistor_info(child); - - prev = child; - child = child->next; - FreeNode(prev); - - process_tech_xml_load_transistor_info(child); - FreeNode(child); - - /* Multiplexer Voltage Information */ - child = FindElement(cur, "multiplexers", TRUE); - power_tech_xml_load_multiplexer_info(child); - FreeNode(child); - - /* Vds Leakage Information */ - child = FindElement(cur, "nmos_leakages", TRUE); - power_tech_xml_load_nmos_st_leakages(child); - FreeNode(child); - - /* Buffer SC Info */ - /* - child = FindElement(cur, "buffer_sc", TRUE); - power_tech_xml_load_sc(child); - FreeNode(child); - */ - - /* Components */ - child = FindElement(cur, "components", TRUE); - power_tech_xml_load_components(child); - FreeNode(child); - - FreeNode(cur); -} - -static void power_tech_xml_load_component(ezxml_t parent, - PowerSpicedComponent ** component, char * name, - float (*usage_fn)(int num_inputs, float transistor_size)) { - ezxml_t cur, child, gc, prev; - - *component = new PowerSpicedComponent(usage_fn); - - cur = FindElement(parent, name, TRUE); - - child = FindFirstElement(cur, "inputs", TRUE); - while (child) { - int num_inputs = GetIntProperty(child, "num_inputs", TRUE, 0); - - gc = FindFirstElement(child, "size", TRUE); - while (gc) { - float transistor_size = GetFloatProperty(gc, "transistor_size", - TRUE, 0.); - float power = GetFloatProperty(gc, "power", TRUE, 0.); - (*component)->add_data_point(num_inputs, transistor_size, power); - - prev = gc; - gc = gc->next; - FreeNode(prev); - } - prev = child; - child = child->next; - FreeNode(prev); - } - FreeNode(cur); -} - -static void power_tech_xml_load_components(ezxml_t parent) { - - g_power_commonly_used->component_callibration = - (PowerSpicedComponent**) my_calloc(POWER_CALLIB_COMPONENT_MAX, - sizeof(PowerSpicedComponent*)); - - power_tech_xml_load_component(parent, - &g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_BUFFER], - "buf", power_usage_buf_for_callibration); - - power_tech_xml_load_component(parent, - &g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR], - "buf_levr", power_usage_buf_levr_for_callibration); - - power_tech_xml_load_component(parent, - &g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_FF], - "dff", power_usage_ff_for_callibration); - - power_tech_xml_load_component(parent, - &g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_MUX], - "mux", power_usage_mux_for_callibration); - - power_tech_xml_load_component(parent, - &g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_LUT], - "lut", power_usage_lut_for_callibration); - -} - -/** - * Read short-circuit buffer information from the transistor .xml file. - * This contains values for buffers of various 1) # Stages 2) Stage strength 3) Input type & capacitance - */ -#if 0 -static void power_tech_xml_load_sc(ezxml_t parent) { - ezxml_t child, prev, gc, ggc; - int i, j, k; - int num_buffer_sizes; - - /* Information for buffers, based on # of stages in buffer */ - num_buffer_sizes = CountChildren(parent, "stages", 1); - g_power_tech->max_buffer_size = num_buffer_sizes; /* buffer size starts at 1, not 0 */ - g_power_tech->buffer_size_inf = (t_power_buffer_size_inf*) my_calloc( - g_power_tech->max_buffer_size + 1, sizeof(t_power_buffer_size_inf)); - - child = FindFirstElement(parent, "stages", TRUE); - i = 1; - while (child) { - t_power_buffer_size_inf * size_inf = &g_power_tech->buffer_size_inf[i]; - - GetIntProperty(child, "num_stages", TRUE, 1); - - /* For the given # of stages, find the records for the strength of each stage */ - size_inf->num_strengths = CountChildren(child, "strength", 1); - size_inf->strength_inf = (t_power_buffer_strength_inf*) my_calloc( - size_inf->num_strengths, sizeof(t_power_buffer_strength_inf)); - - gc = FindFirstElement(child, "strength", TRUE); - j = 0; - while (gc) { - t_power_buffer_strength_inf * strength_inf = - &size_inf->strength_inf[j]; - - /* Get the short circuit factor for a buffer with no level restorer at the input */ - strength_inf->stage_gain = GetFloatProperty(gc, "gain", TRUE, 0.0); - strength_inf->sc_no_levr = GetFloatProperty(gc, "sc_nolevr", TRUE, - 0.0); - - /* Get the short circuit factor for buffers with level restorers at the input */ - strength_inf->num_levr_entries = CountChildren(gc, "input_cap", 1); - strength_inf->sc_levr_inf = (t_power_buffer_sc_levr_inf*) my_calloc( - strength_inf->num_levr_entries, - sizeof(t_power_buffer_sc_levr_inf)); - - ggc = FindFirstElement(gc, "input_cap", TRUE); - k = 0; - while (ggc) { - t_power_buffer_sc_levr_inf * levr_inf = - &strength_inf->sc_levr_inf[k]; - - /* Short circuit factor is depdent on size of mux that drives the buffer */ - levr_inf->mux_size = GetIntProperty(ggc, "mux_size", TRUE, 0); - levr_inf->sc_levr = GetFloatProperty(ggc, "sc_levr", TRUE, 0.0); - - prev = ggc; - ggc = ggc->next; - FreeNode(prev); - k++; - } - - prev = gc; - gc = gc->next; - FreeNode(prev); - j++; - } - - prev = child; - child = child->next; - FreeNode(prev); - i++; - } -} -#endif - -/** - * Read NMOS subthreshold leakage currents from the .xml transistor characteristics - * This builds a table of (Vds,Ids) value pairs - * */ -static void power_tech_xml_load_nmos_st_leakages(ezxml_t parent) { - ezxml_t me, child, prev; - int num_nmos_sizes; - int num_leakage_pairs; - int i; - int nmos_idx; - - num_nmos_sizes = CountChildren(parent, "nmos", 1); - g_power_tech->num_nmos_leakage_info = num_nmos_sizes; - g_power_tech->nmos_leakage_info = (t_power_nmos_leakage_inf*) my_calloc( - num_nmos_sizes, sizeof(t_power_nmos_leakage_inf)); - - me = FindFirstElement(parent, "nmos", TRUE); - nmos_idx = 0; - while (me) { - t_power_nmos_leakage_inf * nmos_info = - &g_power_tech->nmos_leakage_info[nmos_idx]; - nmos_info->nmos_size = GetFloatProperty(me, "size", TRUE, 0.); - - num_leakage_pairs = CountChildren(me, "nmos_leakage", 1); - nmos_info->num_leakage_pairs = num_leakage_pairs; - nmos_info->leakage_pairs = (t_power_nmos_leakage_pair*) my_calloc( - num_leakage_pairs, sizeof(t_power_nmos_leakage_pair)); - - child = FindFirstElement(me, "nmos_leakage", TRUE); - i = 0; - while (child) { - nmos_info->leakage_pairs[i].v_ds = GetFloatProperty(child, "Vds", - TRUE, 0.0); - nmos_info->leakage_pairs[i].i_ds = GetFloatProperty(child, "Ids", - TRUE, 0.0); - - prev = child; - child = child->next; - FreeNode(prev); - i++; - } - - prev = me; - me = me->next; - FreeNode(prev); - nmos_idx++; - } - -} - -/** - * Read multiplexer information from the .xml transistor characteristics. - * This contains the estimates of mux output voltages, depending on 1) Mux Size 2) Mux Vin - * */ -static void power_tech_xml_load_multiplexer_info(ezxml_t parent) { - ezxml_t me, child, prev, gc; - int num_nmos_sizes; - int num_mux_sizes; - int i, j, nmos_idx; - - /* Process all nmos sizes */ - num_nmos_sizes = CountChildren(parent, "nmos", 1); - g_power_tech->num_nmos_mux_info = num_nmos_sizes; - g_power_tech->nmos_mux_info = (t_power_nmos_mux_inf*) my_calloc( - num_nmos_sizes, sizeof(t_power_nmos_mux_inf)); - - me = FindFirstElement(parent, "nmos", TRUE); - nmos_idx = 0; - while (me) { - t_power_nmos_mux_inf * nmos_inf = &g_power_tech->nmos_mux_info[nmos_idx]; - nmos_inf->nmos_size = GetFloatProperty(me, "size", TRUE, 0.0); -// ezxml_set_attr(me, "size", NULL); - - /* Process all multiplexer sizes */ - num_mux_sizes = CountChildren(me, "multiplexer", 1); - - /* Add entries for 0 and 1, for convenience, although - * they will never be used - */ - nmos_inf->max_mux_sl_size = 1 + num_mux_sizes; - nmos_inf->mux_voltage_inf = (t_power_mux_volt_inf*) my_calloc( - nmos_inf->max_mux_sl_size + 1, sizeof(t_power_mux_volt_inf)); - - child = FindFirstElement(me, "multiplexer", TRUE); - i = 1; - while (child) { - int num_voltages; - - assert(i == GetFloatProperty(child, "size", TRUE, 0)); - - /* For each mux size, process all of the Vin levels */ - num_voltages = CountChildren(child, "voltages", 1); - - nmos_inf->mux_voltage_inf[i].num_voltage_pairs = num_voltages; - nmos_inf->mux_voltage_inf[i].mux_voltage_pairs = - (t_power_mux_volt_pair*) my_calloc(num_voltages, - sizeof(t_power_mux_volt_pair)); - - gc = FindFirstElement(child, "voltages", TRUE); - j = 0; - while (gc) { - /* For each mux size, and Vin level, get the min/max V_out */ - nmos_inf->mux_voltage_inf[i].mux_voltage_pairs[j].v_in = - GetFloatProperty(gc, "in", TRUE, 0.0); - nmos_inf->mux_voltage_inf[i].mux_voltage_pairs[j].v_out_min = - GetFloatProperty(gc, "out_min", TRUE, 0.0); - nmos_inf->mux_voltage_inf[i].mux_voltage_pairs[j].v_out_max = - GetFloatProperty(gc, "out_max", TRUE, 0.0); - - prev = gc; - gc = gc->next; - FreeNode(prev); - j++; - } - - prev = child; - child = child->next; - FreeNode(prev); - i++; - } - - prev = me; - me = me->next; - FreeNode(prev); - nmos_idx++; - } - -} - -/** - * Read the transistor information from the .xml transistor characteristics. - * For each transistor size, it extracts the: - * - transistor node capacitances - * - subthreshold leakage - * - gate leakage - */ -static void process_tech_xml_load_transistor_info(ezxml_t parent) { - t_transistor_inf * trans_inf; - const char * prop; - ezxml_t child, prev, grandchild; - int i; - - /* Get transistor type: NMOS or PMOS */ - prop = FindProperty(parent, "type", TRUE); - trans_inf = NULL; - if (strcmp(prop, "nmos") == 0) { - trans_inf = &g_power_tech->NMOS_inf; - } else if (strcmp(prop, "pmos") == 0) { - trans_inf = &g_power_tech->PMOS_inf; - } else { - assert(0); - } - ezxml_set_attr(parent, "type", NULL); - - /* Get long transistor information (W=1,L=2) */ - trans_inf->long_trans_inf = (t_transistor_size_inf*) my_malloc( - sizeof(t_transistor_size_inf)); - - child = FindElement(parent, "long_size", TRUE); - assert(GetIntProperty(child, "L", TRUE, 0) == 2); - trans_inf->long_trans_inf->size = GetFloatProperty(child, "W", TRUE, 0); - - grandchild = FindElement(child, "leakage_current", TRUE); - trans_inf->long_trans_inf->leakage_subthreshold = GetFloatProperty( - grandchild, "subthreshold", TRUE, 0); - FreeNode(grandchild); - - grandchild = FindElement(child, "capacitance", TRUE); - trans_inf->long_trans_inf->C_g = GetFloatProperty(grandchild, "C_g", TRUE, - 0); - trans_inf->long_trans_inf->C_d = GetFloatProperty(grandchild, "C_d", TRUE, - 0); - trans_inf->long_trans_inf->C_s = GetFloatProperty(grandchild, "C_s", TRUE, - 0); - FreeNode(grandchild); - - /* Process all transistor sizes */ - trans_inf->num_size_entries = CountChildren(parent, "size", 1); - trans_inf->size_inf = (t_transistor_size_inf*) my_calloc( - trans_inf->num_size_entries, sizeof(t_transistor_size_inf)); - FreeNode(child); - - child = FindFirstElement(parent, "size", TRUE); - i = 0; - while (child) { - assert(GetIntProperty(child, "L", TRUE, 0) == 1); - - trans_inf->size_inf[i].size = GetFloatProperty(child, "W", TRUE, 0); - - /* Get leakage currents */ - grandchild = FindElement(child, "leakage_current", TRUE); - trans_inf->size_inf[i].leakage_subthreshold = GetFloatProperty( - grandchild, "subthreshold", TRUE, 0); - trans_inf->size_inf[i].leakage_gate = GetFloatProperty(grandchild, - "gate", TRUE, 0); - FreeNode(grandchild); - - /* Get node capacitances */ - grandchild = FindElement(child, "capacitance", TRUE); - trans_inf->size_inf[i].C_g = GetFloatProperty(grandchild, "C_g", TRUE, - 0); - trans_inf->size_inf[i].C_s = GetFloatProperty(grandchild, "C_s", TRUE, - 0); - trans_inf->size_inf[i].C_d = GetFloatProperty(grandchild, "C_d", TRUE, - 0); - FreeNode(grandchild); - - prev = child; - child = child->next; - FreeNode(prev); - i++; - } -} - -/** - * This function searches for a transistor by size - * - lower: (Return value) The lower-bound matching transistor - * - upper: (Return value) The upper-bound matching transistor - * - type: The transistor type to search for - * - size: The transistor size to search for (size = W/L) - */ -boolean power_find_transistor_info(t_transistor_size_inf ** lower, - t_transistor_size_inf ** upper, e_tx_type type, float size) { - char msg[1024]; - t_transistor_size_inf key; - t_transistor_size_inf * found; - t_transistor_inf * trans_info; - float min_size, max_size; - boolean error = FALSE; - - key.size = size; - - /* Find the appropriate global transistor records */ - trans_info = NULL; - if (type == NMOS) { - trans_info = &g_power_tech->NMOS_inf; - } else if (type == PMOS) { - trans_info = &g_power_tech->PMOS_inf; - } else { - assert(0); - } - - /* No transistor data exists */ - if (trans_info->size_inf == NULL) { - power_log_msg(POWER_LOG_ERROR, - "No transistor information exists. Cannot determine transistor properties."); - error = TRUE; - return error; - } - - /* Make note of the transistor record we are searching in, and the bounds */ - g_transistor_last_searched = trans_info; - min_size = trans_info->size_inf[0].size; - max_size = trans_info->size_inf[trans_info->num_size_entries - 1].size; - - found = (t_transistor_size_inf*) bsearch(&key, trans_info->size_inf, - trans_info->num_size_entries, sizeof(t_transistor_size_inf), - &power_compare_transistor_size); - assert(found); - - if (size < min_size) { - /* Too small */ - assert(found == &trans_info->size_inf[0]); - sprintf(msg, - "Using %s transistor of size '%f', which is smaller than the smallest modeled transistor (%f) in the technology behavior file.", - transistor_type_name(type), size, min_size); - power_log_msg(POWER_LOG_WARNING, msg); - *lower = NULL; - *upper = found; - } else if (size > max_size) { - /* Too large */ - assert( - found - == &trans_info->size_inf[trans_info->num_size_entries - - 1]); - sprintf(msg, - "Using %s transistor of size '%f', which is larger than the largest modeled transistor (%f) in the technology behavior file.", - transistor_type_name(type), size, max_size); - power_log_msg(POWER_LOG_WARNING, msg); - *lower = found; - *upper = NULL; - } else { - *lower = found; - *upper = found + 1; - } - - return error; -} - -/** - * This function searches for the Ids leakage current, based on a given Vds. - * This function is used for minimum-sized NMOS transistors (used in muxs). - * - lower: (Return value) The lower-bound matching V/I pair - * - upper: (Return value) The upper-bound matching V/I pair - * - v_ds: The drain/source voltage to search for - */ -t_power_nmos_leakage_inf * g_power_searching_nmos_leakage_info; -void power_find_nmos_leakage(t_power_nmos_leakage_inf * nmos_leakage_info, - t_power_nmos_leakage_pair ** lower, t_power_nmos_leakage_pair ** upper, - float v_ds) { - t_power_nmos_leakage_pair key; - t_power_nmos_leakage_pair * found; - - key.v_ds = v_ds; - - g_power_searching_nmos_leakage_info = nmos_leakage_info; - - found = (t_power_nmos_leakage_pair*) bsearch(&key, - nmos_leakage_info->leakage_pairs, - nmos_leakage_info->num_leakage_pairs, - sizeof(t_power_nmos_leakage_pair), power_compare_leakage_pair); - if (!found) { - assert(found); - } - - if (found - == &nmos_leakage_info->leakage_pairs[nmos_leakage_info->num_leakage_pairs - - 1]) { - /* The results equal to the max voltage (Vdd) */ - *lower = found; - *upper = NULL; - } else { - *lower = found; - *upper = found + 1; - } -} - -/** - * This function searches for the information for a given buffer strength. - * - lower: (Return value) The lower-bound matching record - * - upper: (Return value) The upper-bound matching record - * - stage_gain: The buffer strength to search for - */ -void power_find_buffer_strength_inf(t_power_buffer_strength_inf ** lower, - t_power_buffer_strength_inf ** upper, - t_power_buffer_size_inf * size_inf, float stage_gain) { - t_power_buffer_strength_inf key; - t_power_buffer_strength_inf * found; - - float min_size; - float max_size; - - min_size = size_inf->strength_inf[0].stage_gain; - max_size = size_inf->strength_inf[size_inf->num_strengths - 1].stage_gain; - - assert(stage_gain >= min_size && stage_gain <= max_size); - - key.stage_gain = stage_gain; - - found = (t_power_buffer_strength_inf*) bsearch(&key, size_inf->strength_inf, - size_inf->num_strengths, sizeof(t_power_buffer_strength_inf), - power_compare_buffer_strength); - - if (stage_gain == max_size) { - *lower = found; - *upper = NULL; - } else { - *lower = found; - *upper = found + 1; - } -} - -/** - * This function searches for short-circuit current information for a level-restoring buffer, - * based on the size of the multiplexer driving the input - * - lower: (Return value) The lower-bound matching record - * - upper: (Return value) The upper-bound matching record - * - buffer_strength: The set of records to search withing, which are for a specific buffer size/strength - * - input_mux_size: The input mux size to search for - */ -void power_find_buffer_sc_levr(t_power_buffer_sc_levr_inf ** lower, - t_power_buffer_sc_levr_inf ** upper, - t_power_buffer_strength_inf * buffer_strength, int input_mux_size) { - t_power_buffer_sc_levr_inf key; - t_power_buffer_sc_levr_inf * found; - char msg[1024]; - int max_size; - - assert(input_mux_size >= 1); - - key.mux_size = input_mux_size; - - g_buffer_strength_last_searched = buffer_strength; - found = (t_power_buffer_sc_levr_inf*) bsearch(&key, - buffer_strength->sc_levr_inf, buffer_strength->num_levr_entries, - sizeof(t_power_buffer_sc_levr_inf), power_compare_buffer_sc_levr); - - max_size = buffer_strength->sc_levr_inf[buffer_strength->num_levr_entries - - 1].mux_size; - if (input_mux_size > max_size) { - /* Input mux too large */ - assert( - found - == &buffer_strength->sc_levr_inf[buffer_strength->num_levr_entries - - 1]); - sprintf(msg, - "Using buffer driven by mux of size '%d', which is larger than the largest modeled size (%d) in the technology behavior file.", - input_mux_size, max_size); - power_log_msg(POWER_LOG_WARNING, msg); - *lower = found; - *upper = NULL; - } else { - *lower = found; - *upper = found + 1; - } -} - -/** - * Comparison function, used by power_find_nmos_leakage - */ -static int power_compare_leakage_pair(const void * key_void, - const void * elem_void) { - const t_power_nmos_leakage_pair * key = - (const t_power_nmos_leakage_pair*) key_void; - const t_power_nmos_leakage_pair * elem = - (const t_power_nmos_leakage_pair*) elem_void; - const t_power_nmos_leakage_pair * next = - (const t_power_nmos_leakage_pair*) elem + 1; - - /* Compare against last? */ - if (elem - == &g_power_searching_nmos_leakage_info->leakage_pairs[g_power_searching_nmos_leakage_info->num_leakage_pairs - - 1]) { - if (key->v_ds >= elem->v_ds) { - return 0; - } else { - return -1; - } - } - - /* Check for exact match to Vdd (upper end) */ - if (key->v_ds == elem->v_ds) { - return 0; - } else if (key->v_ds < elem->v_ds) { - return -1; - } else if (key->v_ds > next->v_ds) { - return 1; - } else { - return 0; - } -} - -/** - * This function searches for multiplexer output voltage information, based on input voltage - * - lower: (Return value) The lower-bound matching record - * - upper: (Return value) The upper-bound matching record - * - volt_inf: The set of records to search within, which are for a specific mux size - * - v_in: The input voltage to search for - */ -void power_find_mux_volt_inf(t_power_mux_volt_pair ** lower, - t_power_mux_volt_pair ** upper, t_power_mux_volt_inf * volt_inf, - float v_in) { - t_power_mux_volt_pair key; - t_power_mux_volt_pair * found; - - key.v_in = v_in; - - g_mux_volt_last_searched = volt_inf; - found = (t_power_mux_volt_pair*) bsearch(&key, volt_inf->mux_voltage_pairs, - volt_inf->num_voltage_pairs, sizeof(t_power_mux_volt_pair), - power_compare_voltage_pair); - assert(found); - - if (found - == &volt_inf->mux_voltage_pairs[volt_inf->num_voltage_pairs - 1]) { - *lower = found; - *upper = NULL; - } else { - *lower = found; - *upper = found + 1; - } -} - -/** - * Comparison function, used by power_find_buffer_sc_levr - */ -static int power_compare_buffer_sc_levr(const void * key_void, - const void * elem_void) { - const t_power_buffer_sc_levr_inf * key = - (const t_power_buffer_sc_levr_inf*) key_void; - const t_power_buffer_sc_levr_inf * elem = - (const t_power_buffer_sc_levr_inf*) elem_void; - const t_power_buffer_sc_levr_inf * next; - - /* Compare against last? */ - if (elem - == &g_buffer_strength_last_searched->sc_levr_inf[g_buffer_strength_last_searched->num_levr_entries - - 1]) { - if (key->mux_size >= elem->mux_size) { - return 0; - } else { - return -1; - } - } - - /* Compare against first? */ - if (elem == &g_buffer_strength_last_searched->sc_levr_inf[0]) { - if (key->mux_size < elem->mux_size) { - return 0; - } - } - - /* Check if the key is between elem and the next element */ - next = elem + 1; - if (key->mux_size > next->mux_size) { - return 1; - } else if (key->mux_size < elem->mux_size) { - return -1; - } else { - return 0; - } -} - -/** - * Comparison function, used by power_find_buffer_strength_inf - */ -static int power_compare_buffer_strength(const void * key_void, - const void * elem_void) { - const t_power_buffer_strength_inf * key = - (const t_power_buffer_strength_inf*) key_void; - const t_power_buffer_strength_inf * elem = - (const t_power_buffer_strength_inf*) elem_void; - const t_power_buffer_strength_inf * next = - (const t_power_buffer_strength_inf*) elem + 1; - - /* Check for exact match */ - if (key->stage_gain == elem->stage_gain) { - return 0; - } else if (key->stage_gain < elem->stage_gain) { - return -1; - } else if (key->stage_gain > next->stage_gain) { - return 1; - } else { - return 0; - } -} - -/** - * Comparison function, used by power_find_transistor_info - */ -static int power_compare_transistor_size(const void * key_void, - const void * elem_void) { - const t_transistor_size_inf * key = (const t_transistor_size_inf*) key_void; - const t_transistor_size_inf * elem = - (const t_transistor_size_inf*) elem_void; - const t_transistor_size_inf * next; - - /* Check if we are comparing against the last element */ - if (elem - == &g_transistor_last_searched->size_inf[g_transistor_last_searched->num_size_entries - - 1]) { - /* Match if the desired value is larger than the largest item in the list */ - if (key->size >= elem->size) { - return 0; - } else { - return -1; - } - } - - /* Check if we are comparing against the first element */ - if (elem == &g_transistor_last_searched->size_inf[0]) { - /* Match the smallest if it is smaller than the smallest */ - if (key->size < elem->size) { - return 0; - } - } - - /* Check if the key is between elem and the next element */ - next = elem + 1; - if (key->size > next->size) { - return 1; - } else if (key->size < elem->size) { - return -1; - } else { - return 0; - } - -} - -/** - * Comparison function, used by power_find_mux_volt_inf - */ -static int power_compare_voltage_pair(const void * key_void, - const void * elem_void) { - const t_power_mux_volt_pair * key = (const t_power_mux_volt_pair *) key_void; - const t_power_mux_volt_pair * elem = - (const t_power_mux_volt_pair *) elem_void; - const t_power_mux_volt_pair * next = (const t_power_mux_volt_pair *) elem - + 1; - - /* Check if we are comparing against the last element */ - if (elem - == &g_mux_volt_last_searched->mux_voltage_pairs[g_mux_volt_last_searched->num_voltage_pairs - - 1]) { - /* Match if the desired value is larger than the largest item in the list */ - if (key->v_in >= elem->v_in) { - return 0; - } else { - return -1; - } - } - - /* Check for exact match to Vdd (upper end) */ - if (key->v_in == elem->v_in) { - return 0; - } else if (key->v_in < elem->v_in) { - return -1; - } else if (key->v_in > next->v_in) { - return 1; - } else { - return 0; - } -} - diff --git a/vpr7_x2p/vpr/SRC/power/power_cmos_tech.h b/vpr7_x2p/vpr/SRC/power/power_cmos_tech.h deleted file mode 100644 index 383d52e5c..000000000 --- a/vpr7_x2p/vpr/SRC/power/power_cmos_tech.h +++ /dev/null @@ -1,47 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/** - * This file provides functions relating to the cmos technology. It - * includes functions to read the transistor characteristics from the - * xml file into data structures, and functions to search within - * these data structures. - */ - -#ifndef __POWER_CMOS_TECH_H__ -#define __POWER_CMOS_TECH_H__ - -/************************* INCLUDES *********************************/ -#include "power.h" - -/************************* FUNCTION DECLARATIONS ********************/ -void power_tech_init(char * cmos_tech_behavior_filepath); -boolean power_find_transistor_info(t_transistor_size_inf ** lower, - t_transistor_size_inf ** upper, e_tx_type type, float size); -void power_find_mux_volt_inf(t_power_mux_volt_pair ** lower, - t_power_mux_volt_pair ** upper, t_power_mux_volt_inf * volt_inf, - float v_in); -void power_find_nmos_leakage(t_power_nmos_leakage_inf * nmos_leakage_info, - t_power_nmos_leakage_pair ** lower, t_power_nmos_leakage_pair ** upper, - float v_ds); -void power_find_buffer_strength_inf(t_power_buffer_strength_inf ** lower, - t_power_buffer_strength_inf ** upper, - t_power_buffer_size_inf * size_inf, float stage_gain); -void power_find_buffer_sc_levr(t_power_buffer_sc_levr_inf ** lower, - t_power_buffer_sc_levr_inf ** upper, - t_power_buffer_strength_inf * buffer_sc, int input_mux_size); -#endif diff --git a/vpr7_x2p/vpr/SRC/power/power_components.c b/vpr7_x2p/vpr/SRC/power/power_components.c deleted file mode 100644 index 06f44b1e7..000000000 --- a/vpr7_x2p/vpr/SRC/power/power_components.c +++ /dev/null @@ -1,697 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/** - * This file offers functions to estimate power of major components - * within the FPGA (flip-flops, LUTs, interconnect structures, etc). - */ - -/************************* INCLUDES *********************************/ -#include -using namespace std; - -#include - -#include "power_components.h" -#include "power_lowlevel.h" -#include "power_util.h" -#include "power_callibrate.h" -#include "globals.h" - -/************************* STRUCTS **********************************/ - -/************************* GLOBALS **********************************/ -t_power_components g_power_by_component; - -/************************* FUNCTION DECLARATIONS ********************/ -static void power_usage_mux_rec(t_power_usage * power_usage, float * out_prob, - float * out_dens, float * v_out, t_mux_node * mux_node, - t_mux_arch * mux_arch, int * selector_values, - float * primary_input_prob, float * primary_input_dens, - boolean v_out_restored, float period); - -/************************* FUNCTION DEFINITIONS *********************/ - -/** - * Module initializer function, called by power_init - */ -void power_components_init(void) { - int i; - - g_power_by_component.components = (t_power_usage*) my_calloc( - POWER_COMPONENT_MAX_NUM, sizeof(t_power_usage)); - for (i = 0; i < POWER_COMPONENT_MAX_NUM; i++) { - power_zero_usage(&g_power_by_component.components[i]); - } -} - -/** - * Module un-initializer function, called by power_uninit - */ -void power_components_uninit(void) { - free(g_power_by_component.components); -} - -/** - * Adds power usage for a component to the global component tracker - * - power_usage: Power usage to add - * - component_idx: Type of component - */ -void power_component_add_usage(t_power_usage * power_usage, - e_power_component_type component_idx) { - power_add_usage(&g_power_by_component.components[component_idx], - power_usage); -} - -/** - * Gets power usage for a component - * - power_usage: (Return value) Power usage for the given component - * - component_idx: Type of component - */ -void power_component_get_usage(t_power_usage * power_usage, - e_power_component_type component_idx) { - memcpy(power_usage, &g_power_by_component.components[component_idx], - sizeof(t_power_usage)); -} - -/** - * Returns total power for a given component - * - component_idx: Type of component - */ -float power_component_get_usage_sum(e_power_component_type component_idx) { - return power_sum_usage(&g_power_by_component.components[component_idx]); -} - -/** - * Calculates power of a D flip-flop - * - power_usage: (Return value) power usage of the flip-flop - * - D_prob: Signal probability of the input - * - D_dens: Transition density of the input - * - Q_prob: Signal probability of the output - * - Q_dens: Transition density of the output - * - clk_prob: Signal probability of the clock - * - clk_dens: Transition density of the clock - */ -void power_usage_ff(t_power_usage * power_usage, float size, float D_prob, - float D_dens, float Q_prob, float Q_dens, float clk_prob, - float clk_dens, float period) { - t_power_usage sub_power_usage; - float mux_in_dens[2]; - float mux_in_prob[2]; - PowerSpicedComponent * callibration; - float scale_factor; - - power_zero_usage(power_usage); - - /* DFF is build using a master loop and slave loop. - * Each loop begins with a MUX and contains 2 inverters - * in a feedback loop to the mux. - * Each mux is built using two transmission gates. - */ - - /* Master */ - mux_in_dens[0] = D_dens; - mux_in_dens[1] = (1 - clk_prob) * D_dens; - mux_in_prob[0] = D_prob; - mux_in_prob[1] = D_prob; - power_usage_MUX2_transmission(&sub_power_usage, size, mux_in_dens, - mux_in_prob, clk_dens, (1 - clk_prob) * D_dens, period); - power_add_usage(power_usage, &sub_power_usage); - - power_usage_inverter(&sub_power_usage, (1 - clk_prob) * D_dens, D_prob, - size, period); - power_add_usage(power_usage, &sub_power_usage); - - power_usage_inverter(&sub_power_usage, (1 - clk_prob) * D_dens, 1 - D_prob, - size, period); - power_add_usage(power_usage, &sub_power_usage); - - /* Slave */ - mux_in_dens[0] = Q_dens; - mux_in_dens[1] = (1 - clk_prob) * D_dens; - mux_in_prob[0] = (1 - Q_prob); - mux_in_prob[1] = (1 - D_prob); - power_usage_MUX2_transmission(&sub_power_usage, size, mux_in_dens, - mux_in_prob, clk_dens, Q_dens, period); - power_add_usage(power_usage, &sub_power_usage); - - power_usage_inverter(&sub_power_usage, Q_dens, 1 - Q_prob, size, period); - power_add_usage(power_usage, &sub_power_usage); - - power_usage_inverter(&sub_power_usage, Q_dens, Q_prob, size, period); - power_add_usage(power_usage, &sub_power_usage); - - /* Callibration */ - callibration = - g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_FF]; - if (callibration->is_done_callibration()) { - scale_factor = callibration->scale_factor(1, size); - power_scale_usage(power_usage, scale_factor); - } - - return; -} - -/** - * Calculated power of a look-up table (LUT) - * - power_usage: (Return value) The power usage of the LUT - * - LUT_size: Number of LUT inputs - * - SRAM_values: The 2^(LUT_size) truth table values. String of '0' and '1' characters. - * First characters is for all inputs = 0 and last characters is for all inputs = 1. - * - input_prob: Array of input signal probabilities - * - input_dens: Array of input transition densities - * - * NOTE: The following provides a diagram of a 3-LUT, the sram bit ordering, and - * the input array ordering. - * - * X - NMOS gate controlled by complement of input - * Z - NMOS gate controlled by input - * - * S - * R I I I - * A N N N - * M 2 1 0 - * | | | | - * v v | | - * v | - * 0 _X_ | - * |_X_ v - * 1 _Z_| | - * |_X_ - * 2 _X_ | | - * |_Z_| | - * 3 _Z_| | - * |------ out - * 4 _X_ | - * |_X_ | - * 5 _Z_| | | - * |_Z_| - * 6 _X_ | - * |_Z_| - * 7 _Z_| - * - */ -void power_usage_lut(t_power_usage * power_usage, int lut_size, - float transistor_size, char * SRAM_values, float * input_prob, - float * input_dens, float period) { - float **internal_prob; - float **internal_dens; - float **internal_v; - int i; - int level_idx; - PowerSpicedComponent * callibration; - float scale_factor; - - int num_SRAM_bits; - - boolean level_restorer_this_level = FALSE; - - power_zero_usage(power_usage); - - num_SRAM_bits = 1 << lut_size; - - /* Initialize internal node data */ - internal_prob = (float**) my_calloc(lut_size + 1, sizeof(float*)); - internal_dens = (float**) my_calloc(lut_size + 1, sizeof(float*)); - internal_v = (float**) my_calloc(lut_size + 1, sizeof(float*)); - for (i = 0; i <= lut_size; i++) { - internal_prob[i] = (float*) my_calloc(1 << (lut_size - i), - sizeof(float)); - internal_dens[i] = (float*) my_calloc(1 << (lut_size - i), - sizeof(float)); - internal_v[i] = (float*) my_calloc(1 << (lut_size - i), sizeof(float)); - } - - /* Initialize internal probabilities/densities from SRAM bits */ - for (i = 0; i < num_SRAM_bits; i++) { - if (SRAM_values[i] == '0') { - internal_prob[0][i] = 0.; - } else { - internal_prob[0][i] = 1.; - } - internal_dens[0][i] = 0.; - internal_v[0][i] = g_power_tech->Vdd; - } - - for (level_idx = 0; level_idx < lut_size; level_idx++) { - t_power_usage driver_power_usage; - int MUXs_this_level; - int MUX_idx; - int reverse_idx = lut_size - level_idx - 1; - - MUXs_this_level = 1 << (reverse_idx); - - /* Power of input drivers */ - power_usage_inverter(&driver_power_usage, input_dens[reverse_idx], - input_prob[reverse_idx], 1.0, period); - power_add_usage(power_usage, &driver_power_usage); - - power_usage_inverter(&driver_power_usage, input_dens[reverse_idx], - input_prob[reverse_idx], 2.0, period); - power_add_usage(power_usage, &driver_power_usage); - - power_usage_inverter(&driver_power_usage, input_dens[reverse_idx], - 1 - input_prob[reverse_idx], 2.0, period); - power_add_usage(power_usage, &driver_power_usage); - - /* Add level restorer after every 2 stages (level_idx %2 == 1) - * But if there is an odd # of stages, just put one at the last - * stage (level_idx == LUT_size - 1) and not at the stage just before - * the last stage (level_idx != LUT_size - 2) - */ - if (((level_idx % 2 == 1) && (level_idx != lut_size - 2)) - || (level_idx == lut_size - 1)) { - level_restorer_this_level = TRUE; - } else { - level_restorer_this_level = FALSE; - } - - /* Loop through the 2-muxs at each level */ - for (MUX_idx = 0; MUX_idx < MUXs_this_level; MUX_idx++) { - t_power_usage sub_power; - float out_prob; - float out_dens; - float sum_prob = 0; - int sram_offset = MUX_idx * ipow(2, level_idx + 1); - int sram_per_branch = ipow(2, level_idx); - int branch_lvl_idx; - int sram_idx; - float v_out; - - /* Calculate output probability of multiplexer */ - out_prob = internal_prob[level_idx][MUX_idx * 2] - * (1 - input_prob[reverse_idx]) - + internal_prob[level_idx][MUX_idx * 2 + 1] - * input_prob[reverse_idx]; - - /* Calculate output density of multiplexer */ - out_dens = internal_dens[level_idx][MUX_idx * 2] - * (1 - input_prob[reverse_idx]) - + internal_dens[level_idx][MUX_idx * 2 + 1] - * input_prob[reverse_idx]; - -#ifdef POWER_LUT_FAST - out_dens += ((1 - internal_prob[level_idx][MUX_idx * 2]) * internal_prob[level_idx][MUX_idx * 2 + 1] - + internal_prob[level_idx][MUX_idx * 2] * (1 - internal_prob[level_idx][MUX_idx * 2 + 1])) - * input_dens[reverse_idx]; -#elif defined(POWER_LUT_SLOW) - for (sram_idx = sram_offset; - sram_idx < sram_offset + sram_per_branch; sram_idx++) { - float branch_prob = 1.; - if (SRAM_values[sram_idx] - == SRAM_values[sram_idx + sram_per_branch]) { - continue; - } - for (branch_lvl_idx = 0; branch_lvl_idx < level_idx; - branch_lvl_idx++) { - int branch_lvl_reverse_idx = lut_size - branch_lvl_idx - 1; - int even_odd = sram_idx / ipow(2, branch_lvl_idx); - if (even_odd % 2 == 0) { - branch_prob *= (1 - input_prob[branch_lvl_reverse_idx]); - } else { - branch_prob *= input_prob[branch_lvl_reverse_idx]; - } - } - sum_prob += branch_prob; - } - out_dens += sum_prob * input_dens[reverse_idx]; -#endif - - /* Calculate output voltage of multiplexer */ - if (level_restorer_this_level) { - v_out = g_power_tech->Vdd; - } else { - v_out = (1 - input_prob[reverse_idx]) - * power_calc_mux_v_out(2, 1.0, - internal_v[level_idx][MUX_idx * 2], - internal_prob[level_idx][MUX_idx * 2 + 1]) - + input_prob[reverse_idx] - * power_calc_mux_v_out(2, 1.0, - internal_v[level_idx][MUX_idx * 2 + 1], - internal_prob[level_idx][MUX_idx * 2]); - } - - /* Save internal node info */ - internal_dens[level_idx + 1][MUX_idx] = out_dens; - internal_prob[level_idx + 1][MUX_idx] = out_prob; - internal_v[level_idx + 1][MUX_idx] = v_out; - - /* Calculate power of the 2-mux */ - power_usage_mux_singlelevel_dynamic(&sub_power, 2, - internal_dens[level_idx + 1][MUX_idx], - internal_v[level_idx + 1][MUX_idx], - &internal_prob[level_idx][MUX_idx * 2], - &internal_dens[level_idx][MUX_idx * 2], - &internal_v[level_idx][MUX_idx * 2], - input_dens[reverse_idx], input_prob[reverse_idx], - transistor_size, period); - power_add_usage(power_usage, &sub_power); - - /* Add the level-restoring buffer if necessary */ - if (level_restorer_this_level) { - /* Level restorer */ - power_usage_buffer(&sub_power, 1, - internal_prob[level_idx + 1][MUX_idx], - internal_dens[level_idx + 1][MUX_idx], TRUE, period); - power_add_usage(power_usage, &sub_power); - } - } - - } - - /* Free allocated memory */ - for (i = 0; i <= lut_size; i++) { - free(internal_prob[i]); - free(internal_dens[i]); - free(internal_v[i]); - } - free(internal_prob); - free(internal_dens); - free(internal_v); - - /* Callibration */ - callibration = - g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_LUT]; - if (callibration->is_done_callibration()) { - scale_factor = callibration->scale_factor(lut_size, transistor_size); - power_scale_usage(power_usage, scale_factor); - } - - return; -} - -/** - * This function calculates power of a local interconnect structure - * - power_usage: (Return value) Power usage of the structure - * - pb: The physical block to which this interconnect belongs - * - interc_pins: The interconnect input/ouput pin information - * - interc_length: The physical length spanned by the interconnect (meters) - */ -void power_usage_local_interc_mux(t_power_usage * power_usage, t_pb * pb, - t_interconnect_pins * interc_pins) { - int pin_idx; - int out_port_idx; - int in_port_idx; - float * in_dens; - float * in_prob; - t_power_usage MUX_power; - t_interconnect * interc = interc_pins->interconnect; - t_interconnect_power * interc_power = interc->interconnect_power; - - power_zero_usage(power_usage); - - /* Ensure port/pins are structured as expected */ - switch (interc_pins->interconnect->type) { - case DIRECT_INTERC: - assert(interc_power->num_input_ports == 1); - assert(interc_power->num_output_ports == 1); - break; - case MUX_INTERC: - assert(interc_power->num_output_ports == 1); - break; - case COMPLETE_INTERC: - break; - } - - /* Power of transistors to build interconnect structure */ - switch (interc_pins->interconnect->type) { - case DIRECT_INTERC: - /* Direct connections require no transistors */ - break; - case MUX_INTERC: - case COMPLETE_INTERC: - /* Many-to-1, or Many-to-Many - * Implemented as a multiplexer for each output - * */ - in_dens = (float*) my_calloc( - interc->interconnect_power->num_input_ports, sizeof(float)); - in_prob = (float*) my_calloc( - interc->interconnect_power->num_input_ports, sizeof(float)); - - for (out_port_idx = 0; - out_port_idx < interc->interconnect_power->num_output_ports; - out_port_idx++) { - for (pin_idx = 0; - pin_idx < interc->interconnect_power->num_pins_per_port; - pin_idx++) { - - int selected_input = OPEN; - - /* Clear input densities */ - for (in_port_idx = 0; - in_port_idx - < interc->interconnect_power->num_input_ports; - in_port_idx++) { - in_dens[in_port_idx] = 0.; - in_prob[in_port_idx] = 0.; - } - - /* Get probability/density of input signals */ - if (pb) { - int output_pin_net = - pb->rr_graph[interc_pins->output_pins[out_port_idx][pin_idx]->pin_count_in_cluster].net_num; - - if (output_pin_net == OPEN) { - selected_input = 0; - } else { - for (in_port_idx = 0; - in_port_idx - < interc->interconnect_power->num_input_ports; - in_port_idx++) { - t_pb_graph_pin * input_pin = - interc_pins->input_pins[in_port_idx][pin_idx]; - int input_pin_net = - pb->rr_graph[input_pin->pin_count_in_cluster].net_num; - - /* Find input pin that connects through the mux to the output pin */ - if (output_pin_net == input_pin_net) { - selected_input = in_port_idx; - } - - /* Initialize input densities */ - if (input_pin_net != OPEN) { - in_dens[in_port_idx] = pin_dens(pb, input_pin); - in_prob[in_port_idx] = pin_prob(pb, input_pin); - } - } - - /* Check that the input pin was found with a matching net to the output pin */ - assert(selected_input != OPEN); - } - } else { - selected_input = 0; - } - - /* Calculate power of the multiplexer */ - power_usage_mux_multilevel(&MUX_power, - power_get_mux_arch( - interc_pins->interconnect->interconnect_power->num_input_ports, - g_power_arch->mux_transistor_size), in_prob, - in_dens, selected_input, TRUE, g_solution_inf.T_crit); - - power_add_usage(power_usage, &MUX_power); - } - } - - free(in_dens); - free(in_prob); - break; - default: - assert(0); - } - - power_add_usage(&interc_pins->interconnect->interconnect_power->power_usage, - power_usage); -} - -/** - * This calculates the power of a multilevel multiplexer, with static inputs - * - power_usage: (Return value) The power usage of the multiplexer - * - mux_arch: The information on the multiplexer architecture - * - in_prob: Array of input signal probabilities - * - in_dens: Array of input transition densitites - * - selected_input: The index of the input that has been statically selected - * - output_level_restored: Whether the output is level restored to Vdd. - */ -void power_usage_mux_multilevel(t_power_usage * power_usage, - t_mux_arch * mux_arch, float * in_prob, float * in_dens, - int selected_input, boolean output_level_restored, float period) { - float output_density; - float output_prob; - float V_out; - boolean found; - PowerSpicedComponent * callibration; - float scale_factor; - int * selector_values = (int*) my_calloc(mux_arch->levels, sizeof(int)); - - assert(selected_input != OPEN); - - power_zero_usage(power_usage); - - /* Find selection index at each level */ - found = mux_find_selector_values(selector_values, mux_arch->mux_graph_head, - selected_input); - - assert(found); - - /* Calculate power of the multiplexor stages, from final stage, to first stages */ - power_usage_mux_rec(power_usage, &output_density, &output_prob, &V_out, - mux_arch->mux_graph_head, mux_arch, selector_values, in_prob, - in_dens, output_level_restored, period); - - free(selector_values); - - callibration = - g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_MUX]; - if (callibration->is_done_callibration()) { - scale_factor = callibration->scale_factor(mux_arch->num_inputs, - mux_arch->transistor_size); - power_scale_usage(power_usage, scale_factor); - } - -} - -/** - * Internal function, used recursively by power_calc_mux - */ -static void power_usage_mux_rec(t_power_usage * power_usage, float * out_prob, - float * out_dens, float * v_out, t_mux_node * mux_node, - t_mux_arch * mux_arch, int * selector_values, - float * primary_input_prob, float * primary_input_dens, - boolean v_out_restored, float period) { - int input_idx; - float * in_prob; - float * in_dens; - float * v_in; - t_power_usage sub_power_usage; - - /* Single input mux is really just a wire, and has no power. - * Ensure that it has no children before returning. */ - if (mux_node->num_inputs == 1) { - assert(mux_node->level == 0); - return; - } - - v_in = (float*) my_calloc(mux_node->num_inputs, sizeof(float)); - if (mux_node->level == 0) { - /* First level of mux - inputs are primar inputs */ - in_prob = &primary_input_prob[mux_node->starting_pin_idx]; - in_dens = &primary_input_dens[mux_node->starting_pin_idx]; - - for (input_idx = 0; input_idx < mux_node->num_inputs; input_idx++) { - v_in[input_idx] = g_power_tech->Vdd; - } - } else { - /* Higher level of mux - inputs recursive from lower levels */ - in_prob = (float*) my_calloc(mux_node->num_inputs, sizeof(float)); - in_dens = (float*) my_calloc(mux_node->num_inputs, sizeof(float)); - - for (input_idx = 0; input_idx < mux_node->num_inputs; input_idx++) { - /* Call recursively for multiplexer driving the input */ - power_usage_mux_rec(power_usage, &in_prob[input_idx], - &in_dens[input_idx], &v_in[input_idx], - &mux_node->children[input_idx], mux_arch, selector_values, - primary_input_prob, primary_input_dens, FALSE, period); - } - } - - power_usage_mux_singlelevel_static(&sub_power_usage, out_prob, out_dens, - v_out, mux_node->num_inputs, selector_values[mux_node->level], - in_prob, in_dens, v_in, mux_arch->transistor_size, v_out_restored, - period); - power_add_usage(power_usage, &sub_power_usage); - - if (mux_node->level != 0) { - free(in_prob); - free(in_dens); - } -} - -/** - * This function calculates the power of a multistage buffer - * - power_usage: (Return value) Power usage of buffer - * - size: The size of the final buffer stage, relative to min-sized inverter - * - in_prob: The signal probability of the input - * - in_dens: The transition density of the input - * - level_restored: Whether this buffer must level restore the input - * - input_mux_size: If fed by a mux, the size of this mutliplexer - */ -void power_usage_buffer(t_power_usage * power_usage, float size, float in_prob, - float in_dens, boolean level_restorer, float period) { - t_power_usage sub_power_usage; - int i, num_stages; - float stage_effort; - float stage_inv_size; - float stage_in_prob; - float input_dyn_power; - float scale_factor; - PowerSpicedComponent * callibration; - - power_zero_usage(power_usage); - - if (size == 0.) { - return; - } - - num_stages = power_calc_buffer_num_stages(size, - g_power_arch->logical_effort_factor); - stage_effort = calc_buffer_stage_effort(num_stages, size); - - stage_in_prob = in_prob; - for (i = 0; i < num_stages; i++) { - stage_inv_size = pow(stage_effort, i); - - if (i == 0) { - if (level_restorer) { - /* Sense Buffer */ - power_usage_level_restorer(&sub_power_usage, &input_dyn_power, - in_dens, stage_in_prob, period); - } else { - power_usage_inverter(&sub_power_usage, in_dens, stage_in_prob, - stage_inv_size, period); - } - } else { - power_usage_inverter(&sub_power_usage, in_dens, stage_in_prob, - stage_inv_size, period); - } - power_add_usage(power_usage, &sub_power_usage); - - stage_in_prob = 1 - stage_in_prob; - } - - /* Callibration */ - if (level_restorer) { - callibration = - g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_BUFFER_WITH_LEVR]; - } else { - callibration = - g_power_commonly_used->component_callibration[POWER_CALLIB_COMPONENT_BUFFER]; - } - - if (callibration->is_done_callibration()) { - scale_factor = callibration->scale_factor(1, size); - power_scale_usage(power_usage, scale_factor); - } - - /* Short-circuit: add a factor to dynamic power, but the factor is not in addition to the input power - * Need to subtract input before adding factor - this matters for small buffers - */ - /*power_usage->dynamic += (power_usage->dynamic - input_dyn_power) - * power_calc_buffer_sc(num_stages, stage_effort, level_restorer, - input_mux_size); */ -} - diff --git a/vpr7_x2p/vpr/SRC/power/power_components.h b/vpr7_x2p/vpr/SRC/power/power_components.h deleted file mode 100644 index 6d36f72fc..000000000 --- a/vpr7_x2p/vpr/SRC/power/power_components.h +++ /dev/null @@ -1,100 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/** - * This file offers functions to estimate power of major components - * within the FPGA (flip-flops, LUTs, interconnect structures, etc). - */ - -#ifndef __POWER_COMPONENTS_H__ -#define __POWER_COMPONENTS_H__ - -/************************* INCLUDES *********************************/ -#include "power.h" - -/************************* Defines **********************************/ - -/* This controlls the level of accuracy used for transition density - * calculations of internal LUT nodes. The more detailed model - * looks at SRAM values in deciding if toggles on the inputs will - * toggle the internal nets. The fast method uses only signal - * probabilities. - */ -#define POWER_LUT_SLOW -#if (!(defined(POWER_LUT_SLOW) || defined(POWER_LUT_FAST))) -#define POWER_LUT_SLOW -#endif - -/************************* ENUMS ************************************/ -typedef enum { - POWER_COMPONENT_IGNORE = 0, /* */ - POWER_COMPONENT_TOTAL, /* Total power for entire FPGA */ - - POWER_COMPONENT_ROUTING, /* Power for routing fabric (not local routing) */ - POWER_COMPONENT_ROUTE_SB, /* Switch-box */ - POWER_COMPONENT_ROUTE_CB, /* Connection box*/ - POWER_COMPONENT_ROUTE_GLB_WIRE, /* Wires */ - - POWER_COMPONENT_CLOCK, /* Clock network */ - POWER_COMPONENT_CLOCK_BUFFER, /* Buffers in clock network */ - POWER_COMPONENT_CLOCK_WIRE, /* Wires in clock network */ - - POWER_COMPONENT_PB, /* Logic Blocks, and other hard blocks */ - POWER_COMPONENT_PB_PRIMITIVES, /* Primitives (LUTs, FF, etc) */ - POWER_COMPONENT_PB_INTERC_MUXES, /* Local interconnect structures (muxes) */ - POWER_COMPONENT_PB_BUFS_WIRE, /* Local buffers and wire capacitance */ - - POWER_COMPONENT_PB_OTHER, /* Power from other estimation methods - not transistor-level */ - - POWER_COMPONENT_MAX_NUM -} e_power_component_type; - -/************************* STRUCTS **********************************/ -typedef struct s_power_breakdown t_power_components; - -struct s_power_breakdown { - t_power_usage * components; -}; - -/************************* FUNCTION DECLARATIONS ********************/ -extern t_power_components g_power_by_component; - -/************************* FUNCTION DECLARATIONS ********************/ - -void power_components_init(void); -void power_components_uninit(void); -void power_component_get_usage(t_power_usage * power_usage, - e_power_component_type component_idx); -void power_component_add_usage(t_power_usage * power_usage, - e_power_component_type component_idx); -float power_component_get_usage_sum(e_power_component_type component_idx); - -void power_usage_ff(t_power_usage * power_usage, float size, float D_prob, - float D_dens, float Q_prob, float Q_dens, float clk_prob, - float clk_dens, float period); -void power_usage_lut(t_power_usage * power_usage, int LUT_size, - float transistor_size, char * SRAM_values, float * input_densities, - float * input_probabilities, float period); -void power_usage_local_interc_mux(t_power_usage * power_usage, t_pb * pb, - t_interconnect_pins * interc_pins); -void power_usage_mux_multilevel(t_power_usage * power_usage, - t_mux_arch * mux_arch, float * in_prob, float * in_dens, - int selected_input, boolean output_level_restored, float period); -void power_usage_buffer(t_power_usage * power_usage, float size, float in_prob, - float in_dens, boolean level_restored, float period); - -#endif diff --git a/vpr7_x2p/vpr/SRC/power/power_lowlevel.c b/vpr7_x2p/vpr/SRC/power/power_lowlevel.c deleted file mode 100644 index 794a8fa4c..000000000 --- a/vpr7_x2p/vpr/SRC/power/power_lowlevel.c +++ /dev/null @@ -1,893 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/** - * This file provides functions that calculate the power of low-level - * components (inverters, simple multiplexers, etc) - */ - -/************************* INCLUDES *********************************/ -#include - -#include "power_lowlevel.h" -#include "power_util.h" -#include "power_cmos_tech.h" -#include "globals.h" - -/************************* FUNCTION DELCARATIONS ********************/ -static float power_calc_node_switching_v(float capacitance, float density, - float period, float voltage); -static void power_calc_transistor_capacitance(float *C_d, float *C_s, - float *C_g, e_tx_type transistor_type, float size); -static float power_calc_leakage_st(e_tx_type transistor_type, float size); -static float power_calc_leakage_st_pass_transistor(float size, float v_ds); -static float power_calc_leakage_gate(e_tx_type transistor_type, float size); -/*static float power_calc_buffer_sc_levr( - t_power_buffer_strength_inf * buffer_strength, int input_mux_size);*/ - -/************************* FUNCTION DEFINITIONS *********************/ - -/** - * Initializer function for this module, called by power_init - */ -void power_lowlevel_init() { - float C_d, C_s, C_g; - - power_calc_transistor_capacitance(&C_d, &C_s, &C_g, NMOS, 1.0); - g_power_commonly_used->NMOS_1X_C_d = C_d; - g_power_commonly_used->NMOS_1X_C_g = C_g; - g_power_commonly_used->NMOS_1X_C_s = C_s; - - power_calc_transistor_capacitance(&C_d, &C_s, &C_g, PMOS, - g_power_tech->PN_ratio); - g_power_commonly_used->PMOS_1X_C_d = C_d; - g_power_commonly_used->PMOS_1X_C_g = C_g; - g_power_commonly_used->PMOS_1X_C_s = C_s; - - g_power_commonly_used->NMOS_1X_st_leakage = power_calc_leakage_st(NMOS, - 1.0); - g_power_commonly_used->PMOS_1X_st_leakage = power_calc_leakage_st(PMOS, - 1.0 * g_power_tech->PN_ratio); - - g_power_commonly_used->INV_1X_C_in = g_power_commonly_used->NMOS_1X_C_g - + g_power_commonly_used->PMOS_1X_C_g; - g_power_commonly_used->INV_1X_C = g_power_commonly_used->NMOS_1X_C_g - + g_power_commonly_used->PMOS_1X_C_g - + g_power_commonly_used->NMOS_1X_C_d - + g_power_commonly_used->PMOS_1X_C_d; - - power_calc_transistor_capacitance(&C_d, &C_s, &C_g, NMOS, 2.0); - g_power_commonly_used->INV_2X_C = C_g + C_d; - power_calc_transistor_capacitance(&C_d, &C_s, &C_g, PMOS, - 2.0 * g_power_tech->PN_ratio); - g_power_commonly_used->INV_2X_C += C_g + C_d; - -} - -/** - * Calculates the switching power of a node - * - capacitance: The capacitance of the nodoe - * - density: The transition density of the node - */ -float power_calc_node_switching(float capacitance, float density, - float period) { - return 0.5 * g_power_tech->Vdd * g_power_tech->Vdd * capacitance * density - / period; -} - -/** - * Calculates the switching power of a node, with non-Vdd voltage - * - capacitance: The capacitance of the nodoe - * - density: The transition density of the node - * - voltage: The voltage when the node is charged - */ -static float power_calc_node_switching_v(float capacitance, float density, - float period, float voltage) { - return 0.5 * voltage * g_power_tech->Vdd * capacitance * density / period; -} - -/** - * Calculates the power of an inverter - * - power_usage: (Return value) The power usage of the inverter - * - in_dens: The transition density of the input - * - in_prob: The signal probability of the input - * - size: The inverter size, relative to a min-size inverter - */ -void power_usage_inverter(t_power_usage * power_usage, float in_dens, - float in_prob, float size, float period) { - float C_drain, C_gate, C_source; - float C_inv; - - float PMOS_size = g_power_tech->PN_ratio * size; - float NMOS_size = size; - - power_usage->dynamic = 0.; - power_usage->leakage = 0.; - - C_inv = 0.; - - power_calc_transistor_capacitance(&C_drain, &C_source, &C_gate, NMOS, - NMOS_size); - C_inv += C_gate + C_drain; - - power_calc_transistor_capacitance(&C_drain, &C_source, &C_gate, PMOS, - PMOS_size); - C_inv += C_gate + C_drain; - - power_usage->dynamic = power_calc_node_switching(C_inv, in_dens, period); - - power_usage->leakage = in_prob * power_calc_leakage_st(PMOS, PMOS_size) - + (1 - in_prob) * power_calc_leakage_st(NMOS, NMOS_size); - - power_usage->leakage += in_prob * power_calc_leakage_gate(NMOS, NMOS_size) - + (1 - in_prob) * power_calc_leakage_gate(PMOS, PMOS_size); -} - -/** - * Calculates the power of an inverter, with irregular P/N ratio - * - power_usage: (Return value) The power usage of the inverter - * - dy_power_input: (Return value) The dynamic power of the input node - * - in_dens: The transition density of the input - * - in_prob: The signal probability of the input - * - PMOS_size: (W/L) of the PMOS - * - NMOS_size: (W/L) of the NMOS - */ -void power_usage_inverter_irregular(t_power_usage * power_usage, - float * dyn_power_input, float in_density, float in_probability, - float PMOS_size, float NMOS_size, float period) { - float C_drain, C_gate, C_source; - float C_inv; - float C_in; - - power_usage->dynamic = 0.; - power_usage->leakage = 0.; - - C_inv = 0.; - C_in = 0.; - - power_calc_transistor_capacitance(&C_drain, &C_source, &C_gate, NMOS, - NMOS_size); - C_inv += C_gate + C_drain; - C_in += C_gate; - - power_calc_transistor_capacitance(&C_drain, &C_source, &C_gate, PMOS, - PMOS_size); - C_inv += C_gate + C_drain; - C_in += C_gate; - - power_usage->dynamic = power_calc_node_switching(C_inv, in_density, period); - *dyn_power_input = power_calc_node_switching(C_in, in_density, period); - - power_usage->leakage = in_probability - * power_calc_leakage_st(PMOS, PMOS_size) - + (1 - in_probability) * power_calc_leakage_st(NMOS, NMOS_size); -} - -/** - * Calculates the power of an inverter, also returning dynamic power of the input - * - power_usage: (Return value) The power usage of the inverter - * - input_dynamic_power: (Return value) The dynamic power of the input node - * - in_dens: The transition density of the input - * - in_prob: The signal probability of the input - * - size: The inverter size, relative to a min-size inverter - */ -#if 0 -void power_calc_inverter_with_input(t_power_usage * power_usage, - float * input_dynamic_power, float in_density, float in_prob, - float size) { - float C_drain, C_gate, C_source; - float C_inv; - float C_in; - - float PMOS_size = g_power_tech->PN_ratio * size; - float NMOS_size = size; - - power_usage->dynamic = 0.; - power_usage->leakage = 0.; - - C_inv = 0.; - C_in = 0.; - - power_calc_transistor_capacitance(&C_drain, &C_source, &C_gate, NMOS, - NMOS_size); - C_inv += C_gate + C_drain; - C_in += C_gate; - - power_calc_transistor_capacitance(&C_drain, &C_source, &C_gate, PMOS, - PMOS_size); - C_inv += C_gate + C_drain; - C_in += C_gate; - - power_usage->dynamic = power_calc_node_switching(C_inv, in_density); - *input_dynamic_power = power_calc_node_switching(C_in, in_density); - - power_usage->leakage = in_prob * power_calc_leakage_st(PMOS, PMOS_size) - + (1 - in_prob) * power_calc_leakage_st(NMOS, NMOS_size); - - power_usage->leakage += in_prob * power_calc_leakage_gate(NMOS, NMOS_size) - + (1 - in_prob) * power_calc_leakage_gate(PMOS, PMOS_size); -} -#endif - -/** - * Calculate the capacitance for a transistor - * - C_d: (Return value) Drain capacitance - * - C_s: (Return value) Source capacitance - * - C_g: (Return value) Gate capacitance - * - transistor_type: NMOS or PMOS - * - size: (W/L) size of the transistor - */ -static void power_calc_transistor_capacitance(float *C_d, float *C_s, - float *C_g, e_tx_type transistor_type, float size) { - t_transistor_size_inf * tx_info_lower; - t_transistor_size_inf * tx_info_upper; - boolean error; - - /* Initialize to 0 */ - *C_d = 0.; - *C_s = 0.; - *C_g = 0.; - - error = power_find_transistor_info(&tx_info_lower, &tx_info_upper, - transistor_type, size); - if (error) { - return; - } - - if (tx_info_lower == NULL) { - /* No lower bound */ - *C_d = tx_info_upper->C_d; - *C_s = tx_info_upper->C_s; - *C_g = tx_info_upper->C_g; - } else if (tx_info_upper == NULL) { - /* No upper bound */ - *C_d = tx_info_lower->C_d; - *C_s = tx_info_lower->C_s; - *C_g = tx_info_lower->C_g; - } else { - /* Linear approximation between sizes */ - float percent_upper = (size - tx_info_lower->size) - / (tx_info_upper->size - tx_info_lower->size); - *C_d = (1 - percent_upper) * tx_info_lower->C_d - + percent_upper * tx_info_upper->C_d; - *C_s = (1 - percent_upper) * tx_info_lower->C_s - + percent_upper * tx_info_upper->C_s; - *C_g = (1 - percent_upper) * tx_info_lower->C_g - + percent_upper * tx_info_upper->C_g; - } - - return; -} - -/** - * Returns the subthreshold leakage power of a transistor, - * for V_ds = V_dd - * - transistor_type: NMOS or PMOS - * - size: (W/L) of transistor - */ -static float power_calc_leakage_st(e_tx_type transistor_type, float size) { - t_transistor_size_inf * tx_info_lower; - t_transistor_size_inf * tx_info_upper; - boolean error; - float current; - - error = power_find_transistor_info(&tx_info_lower, &tx_info_upper, - transistor_type, size); - if (error) { - return 0; - } - - if (tx_info_lower == NULL) { - /* No lower bound */ - current = tx_info_upper->leakage_subthreshold; - - } else if (tx_info_upper == NULL) { - /* No upper bound */ - current = tx_info_lower->leakage_subthreshold; - } else { - /* Linear approximation between sizes */ - float percent_upper = (size - tx_info_lower->size) - / (tx_info_upper->size - tx_info_lower->size); - current = (1 - percent_upper) * tx_info_lower->leakage_subthreshold - + percent_upper * tx_info_upper->leakage_subthreshold; - } - - return current * g_power_tech->Vdd; -} - -/** - * Returns the gate gate leakage power of a transistor - * - transistor_type: NMOS or PMOS - * - size: (W/L) of transistor - */ -static float power_calc_leakage_gate(e_tx_type transistor_type, float size) { - t_transistor_size_inf * tx_info_lower; - t_transistor_size_inf * tx_info_upper; - boolean error; - float current; - - error = power_find_transistor_info(&tx_info_lower, &tx_info_upper, - transistor_type, size); - if (error) { - return 0; - } - - if (tx_info_lower == NULL) { - /* No lower bound */ - current = tx_info_upper->leakage_gate; - - } else if (tx_info_upper == NULL) { - /* No upper bound */ - current = tx_info_lower->leakage_gate; - } else { - /* Linear approximation between sizes */ - float percent_upper = (size - tx_info_lower->size) - / (tx_info_upper->size - tx_info_lower->size); - current = (1 - percent_upper) * tx_info_lower->leakage_gate - + percent_upper * tx_info_upper->leakage_gate; - } - - return current * g_power_tech->Vdd; -} - -/** - * Returns the subthreshold leakage power of a pass-transistor, - * assumed to be a minimum-sized NMOS - * - size: (W/L) size of transistor (Must be 1.0) - * - v_ds: Drain-source voltage - */ -static float power_calc_leakage_st_pass_transistor(float size, float v_ds) { - t_power_nmos_leakage_inf * nmos_low = NULL; - t_power_nmos_leakage_inf * nmos_high = NULL; - - t_power_nmos_leakage_pair * lower; - t_power_nmos_leakage_pair * upper; - float i_ds; - float power_low; - float power_high; - bool over_range = false; - - assert(size >= 1.0); - - // Check if nmos size is beyond range - if (size - >= g_power_tech->nmos_leakage_info[g_power_tech->num_nmos_leakage_info - - 1].nmos_size) { - nmos_low = - &g_power_tech->nmos_leakage_info[g_power_tech->num_nmos_leakage_info - - 1]; - over_range = true; - } else { - for (int i = 1; i < g_power_tech->num_nmos_leakage_info; i++) { - if (size < g_power_tech->nmos_leakage_info[i].nmos_size) { - nmos_low = &g_power_tech->nmos_leakage_info[i - 1]; - nmos_high = &g_power_tech->nmos_leakage_info[i]; - break; - } - } - } - - if (size - > g_power_tech->nmos_leakage_info[g_power_tech->num_nmos_leakage_info - - 1].nmos_size) { - power_log_msg(POWER_LOG_ERROR, - "The architectures uses multiplexers with \ - transistors sizes larger than what is defined in the \ - section of the technology file."); - } - - power_find_nmos_leakage(nmos_low, &lower, &upper, v_ds); - if (lower->v_ds == v_ds || !upper) { - i_ds = lower->i_ds; - } else { - float perc_upper = (v_ds - lower->v_ds) / (upper->v_ds - lower->v_ds); - i_ds = (1 - perc_upper) * lower->i_ds + perc_upper * upper->i_ds; - } - power_low = i_ds * g_power_tech->Vdd; - - if (!over_range) { - power_find_nmos_leakage(nmos_high, &lower, &upper, v_ds); - if (lower->v_ds == v_ds || !upper) { - i_ds = lower->i_ds; - } else { - float perc_upper = (v_ds - lower->v_ds) - / (upper->v_ds - lower->v_ds); - i_ds = (1 - perc_upper) * lower->i_ds + perc_upper * upper->i_ds; - } - power_high = i_ds * g_power_tech->Vdd; - } - - if (over_range) { - return power_low; - } else { - float perc_upper = (size - nmos_low->nmos_size) - / (nmos_high->nmos_size - nmos_low->nmos_size); - return power_high * perc_upper + power_low * (1 - perc_upper); - } -} - -/** - * Calculates the power of a wire - * - power_usage: (Return value) Power usage of the wire - * - capacitance: Capacitance of the wire (F) - * - density: Transition density of the wire - */ -void power_usage_wire(t_power_usage * power_usage, float capacitance, - float density, float period) { - power_usage->leakage = 0.; - power_usage->dynamic = power_calc_node_switching(capacitance, density, - period); -} - -/** - * Calculates the power of a 2-input multiplexer, comprised of transmission gates - * - power_usage: (Return value) Power usage of the mux - * - in_dens: Array of input transition densities - * - in_prob: Array of input signal probabilities - * - sel_desn: Transition density of select line - * - sel_prob: Signal probability of select line - * - out_dens: Transition density of the output - */ -void power_usage_MUX2_transmission(t_power_usage * power_usage, float size, - float * in_dens, float * in_prob, float sel_dens, float out_dens, - float period) { - - power_zero_usage(power_usage); - - float leakage_n, leakage_p; - leakage_n = power_calc_leakage_st(NMOS, size); - leakage_p = power_calc_leakage_st(PMOS, size * g_power_tech->PN_ratio); - - float C_g_n, C_d_n, C_s_n; - power_calc_transistor_capacitance(&C_d_n, &C_s_n, &C_g_n, NMOS, size); - - float C_g_p, C_d_p, C_s_p; - power_calc_transistor_capacitance(&C_d_p, &C_s_p, &C_g_p, PMOS, - size * g_power_tech->PN_ratio); - - /* A transmission gate leaks if the selected input != other input */ - power_usage->leakage += (in_prob[0] * (1 - in_prob[1]) - + (1 - in_prob[0]) * in_prob[1]) * (leakage_n + leakage_p); - - /* Gate switching */ - power_usage->dynamic += 2 - * power_calc_node_switching(C_g_n + C_g_p, sel_dens, period); - - /* Input switching */ - power_usage->dynamic += power_calc_node_switching(C_d_n + C_s_p, in_dens[0], - period); - power_usage->dynamic += power_calc_node_switching(C_d_n + C_s_p, in_dens[1], - period); - - /* Output switching */ - power_usage->dynamic += power_calc_node_switching(2 * (C_s_n + C_d_p), - out_dens, period); -} - -/** - * Calucates the power of a static, single-level multiplexer - * - power_usage: (Return value) power usage of the mux - * - out_prob: (Return value) Signal probability of the output - * - out_dens: (Return value) Transition density of the output - * - num_inputs: Number of inputs of the mux - * - selected_idx: The input index that is selected by the select lines - * - in_prob: Array of input signal probabilities - * - in_dens: Array of input tranistion densities - * - v_in: Array of input max voltages - * - transistor_size: Size of the NMOS transistors (must be 1.0) - * - v_out_restored: Whether the output will be level restored to Vdd - */ -void power_usage_mux_singlelevel_static(t_power_usage * power_usage, - float * out_prob, float * out_dens, float * v_out, int num_inputs, - int selected_idx, float * in_prob, float * in_dens, float * v_in, - float transistor_size, boolean v_out_restored, float period) { - int input_idx; - float v_in_selected; - float in_prob_avg; - - power_zero_usage(power_usage); - - assert(transistor_size >= 1.0); - - if (selected_idx < num_inputs) { - *out_prob = in_prob[selected_idx]; - *out_dens = in_dens[selected_idx]; - v_in_selected = v_in[selected_idx]; - - } else { - /* In this case, the multiplexer is not symetrical. The - * other branch of the mux has more inputs than this one, - * and the selected input index is not a valid index for - * this portion of the mux. If the mux was actually built - * this way, there would likely be a weak pull-up to ensure - * that the node does not float. - */ - *out_prob = 1.0; - *out_dens = 0.0; - - v_in_selected = 0.; - for (input_idx = 0; input_idx < num_inputs; input_idx++) { - v_in_selected += v_in[input_idx]; - } - v_in_selected /= num_inputs; - } - - in_prob_avg = 0.; - - float C_d, C_g, C_s; - power_calc_transistor_capacitance(&C_d, &C_s, &C_g, NMOS, transistor_size); - - for (input_idx = 0; input_idx < num_inputs; input_idx++) { - /* Dynamic Power at Inputs */ - power_usage->dynamic += power_calc_node_switching_v(C_d, - in_dens[input_idx], period, v_in[input_idx]); - - if (input_idx != selected_idx) { - in_prob_avg += in_prob[input_idx]; - } - } - in_prob_avg /= (num_inputs - 1); - - if (v_out_restored) { - *v_out = g_power_tech->Vdd; - } else { - *v_out = power_calc_mux_v_out(num_inputs, transistor_size, - v_in_selected, in_prob_avg); - } - - for (input_idx = 0; input_idx < num_inputs; input_idx++) { - /* Leakage */ - /* The selected input will never leak */ - if (input_idx == selected_idx) { - continue; - } - - /* Output is high and this input is low */ - power_usage->leakage += (*out_prob) * (1 - in_prob[input_idx]) - * power_calc_leakage_st_pass_transistor(transistor_size, - *v_out); - - /* Output is low and this input is high */ - power_usage->leakage += (1 - *out_prob) * in_prob[input_idx] - * power_calc_leakage_st_pass_transistor(transistor_size, - v_in[input_idx]); - } - - /* Dynamic Power at Output */ - power_usage->dynamic += power_calc_node_switching_v(C_s * num_inputs, - *out_dens, period, *v_out); - -} - -/** - * This function calcualtes the output voltage of a single-level multiplexer - * - num_inputs: Number of inputs of the multiplexer - * - transistor_size: The size of the NMOS transistors (must be 1.0) - * - v_in: The input voltage of the selcted input - * - in_prob_avg: The average signal probabilities of the non-selected inputs - */ -float power_calc_mux_v_out(int num_inputs, float transistor_size, float v_in, - float in_prob_avg) { - t_power_mux_volt_inf * mux_volt_inf_low; - t_power_mux_volt_inf * mux_volt_inf_high; - t_power_mux_volt_pair * lower; - t_power_mux_volt_pair * upper; - float v_out_min, v_out_max; - float v_out_low; - float v_out_high; - bool over_range = false; - - assert(transistor_size >= 1.0); - - t_power_nmos_mux_inf * mux_nmos_inf_lower = NULL; - t_power_nmos_mux_inf * mux_nmos_inf_upper = NULL; - -// Check if nmos size is beyond range - if (transistor_size - >= g_power_tech->nmos_mux_info[g_power_tech->num_nmos_mux_info - 1].nmos_size) { - mux_nmos_inf_lower = - &g_power_tech->nmos_mux_info[g_power_tech->num_nmos_mux_info - 1]; - over_range = true; - } else { - for (int i = 1; i < g_power_tech->num_nmos_mux_info; i++) { - if (transistor_size < g_power_tech->nmos_mux_info[i].nmos_size) { - mux_nmos_inf_lower = &g_power_tech->nmos_mux_info[i - 1]; - mux_nmos_inf_upper = &g_power_tech->nmos_mux_info[i]; - break; - } - } - } - - if (transistor_size - > g_power_tech->nmos_mux_info[g_power_tech->num_nmos_mux_info - 1].nmos_size) { - power_log_msg(POWER_LOG_ERROR, - "The architectures uses multiplexers with \ - transistors sizes larger than what is defined in the \ - section of the technology file."); - } - - if (num_inputs > mux_nmos_inf_lower->max_mux_sl_size - || (!over_range && num_inputs > mux_nmos_inf_upper->max_mux_sl_size)) { - power_log_msg(POWER_LOG_ERROR, - "The circuit contains a single-level mux larger than \ - what is defined in the section of the \ - technology file."); - } - - mux_volt_inf_low = &mux_nmos_inf_lower->mux_voltage_inf[num_inputs]; - - power_find_mux_volt_inf(&lower, &upper, mux_volt_inf_low, v_in); - if (lower->v_in == v_in || !upper) { - v_out_min = lower->v_out_min; - v_out_max = lower->v_out_max; - } else { - float perc_upper = (v_in - lower->v_in) / (upper->v_in - lower->v_in); - v_out_min = (1 - perc_upper) * lower->v_out_min - + perc_upper * upper->v_out_min; - v_out_max = (1 - perc_upper) * lower->v_out_max - + perc_upper * upper->v_out_max; - } - v_out_low = in_prob_avg * v_out_max + (1 - in_prob_avg) * v_out_min; - - if (!over_range) { - mux_volt_inf_high = &mux_nmos_inf_upper->mux_voltage_inf[num_inputs]; - power_find_mux_volt_inf(&lower, &upper, mux_volt_inf_high, v_in); - if (lower->v_in == v_in || !upper) { - v_out_min = lower->v_out_min; - v_out_max = lower->v_out_max; - } else { - float perc_upper = (v_in - lower->v_in) - / (upper->v_in - lower->v_in); - v_out_min = (1 - perc_upper) * lower->v_out_min - + perc_upper * upper->v_out_min; - v_out_max = (1 - perc_upper) * lower->v_out_max - + perc_upper * upper->v_out_max; - } - v_out_high = in_prob_avg * v_out_max + (1 - in_prob_avg) * v_out_min; - } - - if (over_range) { - return v_out_low; - } else { - float perc_upper = - (transistor_size - mux_nmos_inf_lower->nmos_size) - / (mux_nmos_inf_upper->nmos_size - - mux_nmos_inf_lower->nmos_size); - return v_out_high * perc_upper + (1 - perc_upper) * v_out_low; - } -} - -/** This function calculates the power of a single-level multiplexer, where the - * select lines are dynamic - * - power_usage: (Return value) The power usage of the mux - * - num_inputs: Number of multiplexer inputs (must be 2) - * - out_density: The transition density of the output - * - out_prob: The signal probability of the output - * - v_out: The output max voltage - * - in_prob: Array of input signal probabilities - * - in_dens: Array of input tranistion densities - * - v_in: Array of input voltages - * - sel_dens: Transition density of the select line - * - sel_prob: Signal probability of the select line - * - tranisistor_size: NMOS transistor sizes (must be 1.0) - */ -void power_usage_mux_singlelevel_dynamic(t_power_usage * power_usage, - int num_inputs, float out_density, float v_out, float * in_prob, - float * in_dens, float * v_in, float sel_dens, float sel_prob, - float transistor_size, float period) { - - assert(num_inputs == 2); - - power_zero_usage(power_usage); - - /* Leakage occurs when input1 != input2. - * If the selected input is low, the other transistor leaks input->output - * If the selected input is high, the other transistor leaks output->input*/ - - /* 1st selected, 1st Low, 2nd High - Leakage from 2nd in->out */ - power_usage->leakage += (1 - sel_prob) * (1 - in_prob[0]) * in_prob[1] - * power_calc_leakage_st_pass_transistor(transistor_size, v_in[1]); - - /* 1st selected, 1st High, 2nd Low - Leakage from 2nd out->in */ - /* 2nd selected, 1st Low, 2nd High - Leakage from 1st out->in */ - power_usage->leakage += ((1 - sel_prob) * in_prob[0] * (1 - in_prob[1]) - + sel_prob * (1 - in_prob[0]) * in_prob[1]) - * power_calc_leakage_st_pass_transistor(transistor_size, v_out); - - /* 2nd selected, 1st High, 2nd Low - Leakage from 1st in->out */ - power_usage->leakage += sel_prob * in_prob[0] * (1 - in_prob[1]) - * power_calc_leakage_st_pass_transistor(transistor_size, v_in[0]); - - /* Gate switching */ - float C_d, C_s, C_g; - power_calc_transistor_capacitance(&C_d, &C_s, &C_g, NMOS, transistor_size); - power_usage->dynamic += 2 - * power_calc_node_switching(C_g, sel_dens, period); - - /* Input switching */ - power_usage->dynamic += power_calc_node_switching_v(C_d, in_dens[0], period, - v_in[0]); - power_usage->dynamic += power_calc_node_switching_v(C_d, in_dens[1], period, - v_in[1]); - - /* Output switching */ - power_usage->dynamic += power_calc_node_switching_v(2 * C_s, out_density, - period, v_out); -} - -/** - * This function calculates the power of a level restorer, which is a biased - * inverter with a pull-up PMOS transistor in feedback. - * - power_usage: (Return value) Power usage of the level restorer - * - dyn_power_in: (Return value) Dynamic power at the input - * - in_density: Transition density of the input - * - in_prob: Signal probability of the input - */ -void power_usage_level_restorer(t_power_usage * power_usage, - float * dyn_power_in, float in_dens, float in_prob, float period) { - t_power_usage sub_power_usage; - float C; - float C_in; - float input_dyn_power = 0.; - - power_zero_usage(power_usage); - - /* Inverter */ - power_usage_inverter_irregular(&sub_power_usage, &input_dyn_power, in_dens, - in_prob, 1.0, 2.0, period); - power_add_usage(power_usage, &sub_power_usage); - - /* Pull-up PMOS */ - if (g_power_tech->PMOS_inf.long_trans_inf == NULL) { - power_log_msg(POWER_LOG_ERROR, - "No long transistor information exists. Cannot determine transistor properties."); - return; - } - C = g_power_tech->PMOS_inf.long_trans_inf->C_d - + g_power_tech->PMOS_inf.long_trans_inf->C_g; - C_in = g_power_tech->PMOS_inf.long_trans_inf->C_d; - - input_dyn_power += power_calc_node_switching(C_in, in_dens, period); - power_usage->dynamic += power_calc_node_switching(C, in_dens, period); - power_usage->leakage += (1 - in_prob) - * g_power_tech->PMOS_inf.long_trans_inf->leakage_subthreshold; - - *dyn_power_in = input_dyn_power; -} - -/** - * This function calculates the short-circuit factor for a buffer. This factor - * represents the short-circuit power of a buffer, as a factor of switching power. - * - stages: Number of stages of the buffer - * - gain: The gain at each stage - * - level_restorer: Whether this buffer must level-restore the input to Vdd - * - input_mux_size: For level-restoring buffers, what is the size of the mux driving it - */ -// Not used anymore -#if 0 -float power_calc_buffer_sc(int stages, float gain, boolean level_restorer, - int input_mux_size) { - - t_power_buffer_size_inf * size_inf; - t_power_buffer_strength_inf * strength_lower; - t_power_buffer_strength_inf * strength_upper; - float sc; - - /* Find information for given buffer size */ - size_inf = &g_power_tech->buffer_size_inf[stages]; - - /* Find information for a given size/strength */ - power_find_buffer_strength_inf(&strength_lower, &strength_upper, size_inf, - gain); - - if (!level_restorer) { - if (strength_upper == NULL) { - sc = strength_lower->sc_no_levr; - } else { - float percent_upper = (gain - strength_lower->stage_gain) - / (strength_upper->stage_gain - strength_lower->stage_gain); - sc = (1 - percent_upper) * strength_lower->sc_no_levr - + percent_upper * strength_upper->sc_no_levr; - } - } else { - /* Level Restored - Short Circuit depends on input mux size */ - - if (strength_upper == NULL) { - sc = power_calc_buffer_sc_levr(strength_lower, input_mux_size); - } else { - float sc_buf_low; - float sc_buf_high; - - sc_buf_low = power_calc_buffer_sc_levr(strength_lower, - input_mux_size); - sc_buf_high = power_calc_buffer_sc_levr(strength_upper, - input_mux_size); - - float percent_upper = (gain - strength_lower->stage_gain) - / (strength_upper->stage_gain - strength_lower->stage_gain); - sc = (1 - percent_upper) * sc_buf_low + percent_upper * sc_buf_high; - } - } - return sc; -} - -/** - * This function calculates the short-circuit factor for a level-restoring buffer, - * used by power_calc_buffer_sc - * - buffer_strength: The buffer information, for a given size/strength - * - input_mux_size: The size of the mux driving this buffer - */ -static float power_calc_buffer_sc_levr( - t_power_buffer_strength_inf * buffer_strength, int input_mux_size) { - t_power_buffer_sc_levr_inf * mux_lower; - t_power_buffer_sc_levr_inf * mux_upper; - - power_find_buffer_sc_levr(&mux_lower, &mux_upper, buffer_strength, - input_mux_size); - if (mux_upper == NULL) { - return mux_lower->sc_levr; - } else { - float percent_upper = (input_mux_size - mux_lower->mux_size) - / (mux_upper->mux_size - mux_lower->mux_size); - return (1 - percent_upper) * mux_lower->sc_levr - + percent_upper * mux_upper->sc_levr; - } -} -#endif - -float power_calc_buffer_size_from_Cout(float C_out) { - int i; - float C_found; - - t_transistor_inf * nmos_info = &g_power_tech->NMOS_inf; - t_transistor_inf * pmos_info = &g_power_tech->PMOS_inf; - - assert(nmos_info->num_size_entries == pmos_info->num_size_entries); - - for (i = 0; i < nmos_info->num_size_entries; i++) { - C_found = nmos_info->size_inf[i].C_d + pmos_info->size_inf[i].C_d; - - /* Not likely, since floating point */ - if (C_out == C_found) { - return nmos_info->size_inf[i].size; - } - - /* Gone past */ - if (C_found > C_out) { - if (i == 0) { - power_log_msg(POWER_LOG_WARNING, - "Attempted to search for a transistor with a capacitance smaller than the smallest in the technology file.\n"); - return nmos_info->size_inf[i].size; - } else { - float C_prev = nmos_info->size_inf[i - 1].C_d - + pmos_info->size_inf[i - 1].C_d; - float percent_upper = (C_out - C_prev) / (C_found - C_prev); - return percent_upper * nmos_info->size_inf[i].size - + (1 - percent_upper) * nmos_info->size_inf[i - 1].size; - } - } - - /* Reached the End */ - if (i == nmos_info->num_size_entries - 1) { - power_log_msg(POWER_LOG_WARNING, - "Attempted to search for a transistor with a capacitance greater than the largest in the technology file.\n"); - return nmos_info->size_inf[i].size; - } - } - - return 0; -} diff --git a/vpr7_x2p/vpr/SRC/power/power_lowlevel.h b/vpr7_x2p/vpr/SRC/power/power_lowlevel.h deleted file mode 100644 index 7047194d1..000000000 --- a/vpr7_x2p/vpr/SRC/power/power_lowlevel.h +++ /dev/null @@ -1,77 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/** - * This file provides functions that calculate the power of low-level - * components (inverters, simple multiplexers, etc) - */ - -#ifndef __POWER_LOW_LEVEL_H__ -#define __POWER_LOW_LEVEL_H__ - -/************************* INCLUDES *********************************/ -#include "power.h" - -/************************* GLOBALS **********************************/ - -/************************* FUNCTION DECLARATION *********************/ -void power_lowlevel_init(); - -void power_usage_inverter(t_power_usage * power_usage, float in_dens, - float in_prob, float size, float period); -/*void power_calc_inverter_with_input(t_power_usage * power_usage, - float * input_dynamic_power, float in_density, float in_prob, - float size);*/ -void power_usage_inverter_irregular(t_power_usage * power_usage, - float * dyn_power_input, float in_density, float in_probability, - float PMOS_size, float NMOS_size, float period); - -void power_usage_wire(t_power_usage * power_usage, float capacitance, - float density, float period); - -void power_usage_mux_singlelevel_static(t_power_usage * power_usage, - float * out_prob, float * out_dens, float * V_out, int num_inputs, - int selected_idx, float * in_prob, float * in_dens, float * v_in, - float transistor_size, boolean v_out_restored, float period); - -void power_usage_MUX2_transmission(t_power_usage * power_usage, float size, - float * in_dens, float * in_prob, float sel_dens, float out_dens, - float period); - -void power_usage_mux_singlelevel_dynamic(t_power_usage * power_usage, - int num_inputs, float out_density, float v_out, float * in_prob, - float * in_density, float * v_in, float sel_dens, float sel_prob, - float transistor_size, float period); - -void power_usage_level_restorer(t_power_usage * power_usage, - float * dyn_power_in, float in_density, float in_probability, - float period); - -float power_calc_pb_switching_from_c_internal(t_pb * pb, - t_pb_graph_node * pb_graph_node); - -float power_calc_mux_v_out(int num_inputs, float transistor_size, float v_in, - float in_prob_avg); - -/*float power_calc_buffer_sc(int stages, float gain, boolean level_restored, - int input_mux_size);*/ - -float power_calc_node_switching(float capacitance, float density, float period); - -float power_calc_buffer_size_from_Cout(float C_out); - -#endif diff --git a/vpr7_x2p/vpr/SRC/power/power_sizing.c b/vpr7_x2p/vpr/SRC/power/power_sizing.c deleted file mode 100644 index 920c4eacb..000000000 --- a/vpr7_x2p/vpr/SRC/power/power_sizing.c +++ /dev/null @@ -1,860 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/** - * The functions in this file are used to count the transistors in the - * FPGA, for physical size estimations - */ - -/************************* INCLUDES *********************************/ -#include -using namespace std; - -#include - -#include "power_sizing.h" -#include "power.h" -#include "globals.h" -#include "power_util.h" -/************************* GLOBALS **********************************/ -static double g_MTA_area; - -/************************* FUNCTION DELCARATIONS ********************/ -static double power_count_transistors_connectionbox(void); -static double power_count_transistors_mux(t_mux_arch * mux_arch); -static double power_count_transistors_mux_node(t_mux_node * mux_node, - float transistor_size); -static void power_mux_node_max_inputs(t_mux_node * mux_node, - float * max_inputs); -static double power_count_transistors_interc(t_interconnect * interc); -static double power_count_transistors_pb_node(t_pb_graph_node * pb_node); -static double power_count_transistors_switchbox(t_arch * arch); -static double power_count_transistors_primitive(t_pb_type * pb_type); -static double power_count_transistors_LUT(int LUT_inputs, - float transistor_size); -static double power_count_transistors_FF(float size); -static double power_count_transistor_SRAM_bit(void); -static double power_count_transistors_inv(float size); -static double power_count_transistors_trans_gate(float size); -static double power_count_transistors_levr(); -static double power_MTAs(float size); -static void power_size_pin_buffers_and_wires(t_pb_graph_pin * pin, - boolean pin_is_an_input); -static double power_transistors_for_pb_node(t_pb_graph_node * pb_node); -static double power_transistors_per_tile(t_arch * arch); -static void power_size_pb(void); -static void power_size_pb_rec(t_pb_graph_node * pb_node); -static void power_size_pin_to_interconnect(t_interconnect * interc, - int * fanout, float * wirelength); -static double power_MTAs(float W_size); -static double power_MTAs_L(float L_size); -/************************* FUNCTION DEFINITIONS *********************/ - -/** - * Counts the number of transistors in the largest connection box - */ -static double power_count_transistors_connectionbox(void) { - double transistor_cnt = 0.; - int CLB_inputs; - float buffer_size; - - //assert(FILL_TYPE->pb_graph_head->num_input_ports == 1); - CLB_inputs = FILL_TYPE->pb_graph_head->num_input_pins[0]; - - /* Buffers from Tracks */ - buffer_size = g_power_commonly_used->max_seg_to_IPIN_fanout - * (g_power_commonly_used->NMOS_1X_C_d - / g_power_commonly_used->INV_1X_C_in) - / g_power_arch->logical_effort_factor; - buffer_size = max(1.0F, buffer_size); - transistor_cnt += g_solution_inf.channel_width - * power_count_transistors_buffer(buffer_size); - - /* Muxes to IPINs */ - transistor_cnt += CLB_inputs - * power_count_transistors_mux( - power_get_mux_arch(g_power_commonly_used->max_IPIN_fanin, - g_power_arch->mux_transistor_size)); - - return transistor_cnt; -} - -/** - * Counts the number of transistors in a buffer. - * - buffer_size: The final stage size of the buffer, relative to a minimum sized inverter - */ -double power_count_transistors_buffer(float buffer_size) { - int stages; - float effort; - float stage_size; - int stage_idx; - double transistor_cnt = 0.; - - stages = power_calc_buffer_num_stages(buffer_size, - g_power_arch->logical_effort_factor); - effort = calc_buffer_stage_effort(stages, buffer_size); - - stage_size = 1; - for (stage_idx = 0; stage_idx < stages; stage_idx++) { - transistor_cnt += power_count_transistors_inv(stage_size); - stage_size *= effort; - } - - return transistor_cnt; -} - -/** - * Counts the number of transistors in a multiplexer - * - mux_arch: The architecture of the multiplexer - */ -static double power_count_transistors_mux(t_mux_arch * mux_arch) { - double transistor_cnt = 0.; - int lvl_idx; - float * max_inputs; - - /* SRAM bits */ - max_inputs = (float*) my_calloc(mux_arch->levels, sizeof(float)); - for (lvl_idx = 0; lvl_idx < mux_arch->levels; lvl_idx++) { - max_inputs[lvl_idx] = 0.; - } - power_mux_node_max_inputs(mux_arch->mux_graph_head, max_inputs); - - for (lvl_idx = 0; lvl_idx < mux_arch->levels; lvl_idx++) { - /* Assume there is decoder logic */ - transistor_cnt += ceil(log(max_inputs[lvl_idx]) / log((double) 2.0)) - * power_count_transistor_SRAM_bit(); - - /* - if (mux_arch->encoding_types[lvl_idx] == ENCODING_DECODER) { - transistor_cnt += ceil(log2((float)max_inputs[lvl_idx])) - * power_cnt_transistor_SRAM_bit(); - // TODO - Size of decoder - } else if (mux_arch->encoding_types[lvl_idx] == ENCODING_ONE_HOT) { - transistor_cnt += max_inputs[lvl_idx] - * power_cnt_transistor_SRAM_bit(); - } else { - assert(0); - } - */ - } - - transistor_cnt += power_count_transistors_mux_node(mux_arch->mux_graph_head, - mux_arch->transistor_size); - free(max_inputs); - return transistor_cnt; -} - -/** - * This function is used recursively to determine the largest single-level - * multiplexer at each level of a multi-level multiplexer - */ -static void power_mux_node_max_inputs(t_mux_node * mux_node, - float * max_inputs) { - - max_inputs[mux_node->level] = max(max_inputs[mux_node->level], - static_cast(mux_node->num_inputs)); - - if (mux_node->level != 0) { - int child_idx; - - for (child_idx = 0; child_idx < mux_node->num_inputs; child_idx++) { - power_mux_node_max_inputs(&mux_node->children[child_idx], - max_inputs); - } - } -} - -/** - * This function is used recursively to count the number of transistors in a multiplexer - */ -static double power_count_transistors_mux_node(t_mux_node * mux_node, - float transistor_size) { - int input_idx; - double transistor_cnt = 0.; - - if (mux_node->num_inputs != 1) { - for (input_idx = 0; input_idx < mux_node->num_inputs; input_idx++) { - /* Single Pass transistor */ - transistor_cnt += power_MTAs(transistor_size); - - /* Child MUX */ - if (mux_node->level != 0) { - transistor_cnt += power_count_transistors_mux_node( - &mux_node->children[input_idx], transistor_size); - } - } - } - - return transistor_cnt; -} - -/** - * This function returns the number of transistors in an interconnect structure - */ -static double power_count_transistors_interc(t_interconnect * interc) { - double transistor_cnt = 0.; - - switch (interc->type) { - case DIRECT_INTERC: - /* No transistors */ - break; - case MUX_INTERC: - case COMPLETE_INTERC: - /* Bus based interconnect: - * - Each output port requires a (num_input_ports:1) bus-based multiplexor. - * - The number of muxes required for bus based multiplexors is equivalent to - * the width of the bus (num_pins_per_port). - */ - transistor_cnt += interc->interconnect_power->num_output_ports - * interc->interconnect_power->num_pins_per_port - * power_count_transistors_mux( - power_get_mux_arch( - interc->interconnect_power->num_input_ports, - g_power_arch->mux_transistor_size)); - break; - default: - assert(0); - } - - interc->interconnect_power->transistor_cnt = transistor_cnt; - return transistor_cnt; -} - -void power_sizing_init(t_arch * arch) { - float transistors_per_tile; - - // tech size = 2 lambda, so lambda^2/4.0 = tech^2 - g_MTA_area = ((POWER_MTA_L * POWER_MTA_W)/ 4.0)*pow(g_power_tech->tech_size, - (float) 2.0); - - // Determines physical size of different PBs - power_size_pb(); - - /* Find # of transistors in each tile type */ - transistors_per_tile = power_transistors_per_tile(arch); - - /* Calculate CLB tile size - * - Assume a square tile - * - Assume min transistor size is Wx6L - * - Assume an overhead to space transistors - */ - g_power_commonly_used->tile_length = sqrt( - power_transistor_area(transistors_per_tile)); -} - -/** - * This functions counts the number of transistors in all structures in the FPGA. - * It returns the number of transistors in a grid of the FPGA (logic block, - * switch box, 2 connection boxes) - */ -static double power_transistors_per_tile(t_arch * arch) { - double transistor_cnt = 0.; - - transistor_cnt += power_transistors_for_pb_node(FILL_TYPE->pb_graph_head); - - transistor_cnt += 2 * power_count_transistors_switchbox(arch); - - transistor_cnt += 2 * power_count_transistors_connectionbox(); - - return transistor_cnt; -} - -static double power_transistors_for_pb_node(t_pb_graph_node * pb_node) { - return pb_node->pb_node_power->transistor_cnt_interc - + pb_node->pb_node_power->transistor_cnt_pb_children - + pb_node->pb_node_power->transistor_cnt_buffers; -} - -/** - * This function counts the number of transistors for a given physical block type - */ -static double power_count_transistors_pb_node(t_pb_graph_node * pb_node) { - int mode_idx; - int interc; - int child; - int pb_idx; - - double tc_children_max = 0; - double tc_interc_max = 0; - boolean ignore_interc = FALSE; - - t_pb_type * pb_type = pb_node->pb_type; - - /* Check if this is a leaf node, or whether it has children */ - if (pb_type->num_modes == 0) { - /* Leaf node */ - tc_interc_max = 0; - tc_children_max = power_count_transistors_primitive(pb_type); - } else { - /* Find max transistor count between all modes */ - for (mode_idx = 0; mode_idx < pb_type->num_modes; mode_idx++) { - - double tc_children = 0; - double tc_interc = 0; - - t_mode * mode = &pb_type->modes[mode_idx]; - - if (pb_type->class_type == LUT_CLASS) { - /* LUTs will have a child node that is used for routing purposes - * For the routing algorithms it is completely connected; however, - * this interconnect does not exist in FPGA hardware and should - * be ignored for power calculations. */ - ignore_interc = TRUE; - } - - /* Count Interconnect Transistors */ - if (!ignore_interc) { - for (interc = 0; interc < mode->num_interconnect; interc++) { - tc_interc += power_count_transistors_interc( - &mode->interconnect[interc]); - } - } - tc_interc_max = max(tc_interc_max, tc_interc); - - /* Count Child PB Types */ - for (child = 0; child < mode->num_pb_type_children; child++) { - t_pb_type * child_type = &mode->pb_type_children[child]; - - for (pb_idx = 0; pb_idx < child_type->num_pb; pb_idx++) { - tc_children += - power_transistors_for_pb_node( - &pb_node->child_pb_graph_nodes[mode_idx][child][pb_idx]); - } - } - - tc_children_max = max(tc_children_max, tc_children); - } - } - - pb_node->pb_node_power->transistor_cnt_interc = tc_interc_max; - pb_node->pb_node_power->transistor_cnt_pb_children = tc_children_max; - - return (tc_interc_max + tc_children_max); -} - -/** - * This function counts the maximum number of transistors in a switch box - */ -static double power_count_transistors_switchbox(t_arch * arch) { - double transistor_cnt = 0.; - double transistors_per_buf_mux = 0.; - int seg_idx; - - /* Buffer */ - transistors_per_buf_mux += power_count_transistors_buffer( - (float) g_power_commonly_used->max_seg_fanout - / g_power_arch->logical_effort_factor); - - /* Multiplexor */ - transistors_per_buf_mux += power_count_transistors_mux( - power_get_mux_arch(g_power_commonly_used->max_routing_mux_size, - g_power_arch->mux_transistor_size)); - - for (seg_idx = 0; seg_idx < arch->num_segments; seg_idx++) { - /* In each switchbox, the different types of segments occur with relative freqencies. - * Thus the total number of wires of each segment type is (#tracks * freq * 2). - * The (x2) factor accounts for vertical and horizontal tracks. - * Of the wires of each segment type only (1/seglength) will have a mux&buffer. - */ - float freq_frac = (float) arch->Segments[seg_idx].frequency - / (float) MAX_CHANNEL_WIDTH; - - transistor_cnt += transistors_per_buf_mux * 2 * freq_frac - * g_solution_inf.channel_width - * (1 / (float) arch->Segments[seg_idx].length); - } - - return transistor_cnt; -} - -/** - * This function calculates the number of transistors for a primitive physical block - */ -static double power_count_transistors_primitive(t_pb_type * pb_type) { - double transistor_cnt; - - if (strcmp(pb_type->blif_model, ".names") == 0) { - /* LUT */ - transistor_cnt = power_count_transistors_LUT(pb_type->num_input_pins, - g_power_arch->LUT_transistor_size); - } else if (strcmp(pb_type->blif_model, ".latch") == 0) { - /* Latch */ - transistor_cnt = power_count_transistors_FF(g_power_arch->FF_size); - } else { - /* Other */ - char msg[BUFSIZE]; - - sprintf(msg, "No transistor counter function for BLIF model: %s", - pb_type->blif_model); - power_log_msg(POWER_LOG_WARNING, msg); - transistor_cnt = 0; - } - - return transistor_cnt; -} - -/** - * Returns the transistor count of an SRAM cell - */ -static double power_count_transistor_SRAM_bit(void) { - return g_power_arch->transistors_per_SRAM_bit; -} - -static double power_count_transistors_levr() { - double transistor_cnt = 0.; - - /* Each level restorer has a P/N=1/2 inverter and a W/L=1/2 PMOS */ - - /* Inverter */ - transistor_cnt += power_MTAs(2); // NMOS - transistor_cnt += 1.0; // PMOS - - /* Pull-up */ - transistor_cnt += power_MTAs_L(2.0); // Double length - - return transistor_cnt; -} - -/** - * Returns the transistor count for a LUT - */ -static double power_count_transistors_LUT(int LUT_inputs, - float transistor_size) { - double transistor_cnt = 0.; - int level_idx; - - /* Each input driver has 1-1X and 2-2X inverters */ - transistor_cnt += (double) LUT_inputs - * (power_count_transistors_inv(1.0) - + 2 * power_count_transistors_inv(2.0)); - - /* SRAM bits */ - transistor_cnt += power_count_transistor_SRAM_bit() * (1 << LUT_inputs); - - for (level_idx = 0; level_idx < LUT_inputs; level_idx++) { - - /* Pass transistors */ - transistor_cnt += (1 << (LUT_inputs - level_idx)) - * power_MTAs(transistor_size); - - /* Add level restorer after every 2 stages (level_idx %2 == 1) - * But if there is an odd # of stages, just put one at the last - * stage (level_idx == LUT_size - 1) and not at the stage just before - * the last stage (level_idx != LUT_size - 2) - */ - if (((level_idx % 2 == 1) && (level_idx != LUT_inputs - 2)) - || (level_idx == LUT_inputs - 1)) { - transistor_cnt += power_count_transistors_levr(); - } - } - - return transistor_cnt; -} - -static double power_count_transistors_trans_gate(float size) { - double transistor_cnt = 0.; - - transistor_cnt += power_MTAs(size); - transistor_cnt += power_MTAs(size * g_power_tech->PN_ratio); - - return transistor_cnt; -} - -static double power_count_transistors_inv(float size) { - double transistor_cnt = 0.; - - /* NMOS */ - transistor_cnt += power_MTAs(size); - - /* PMOS */ - transistor_cnt += power_MTAs(g_power_tech->PN_ratio * size); - - return transistor_cnt; -} - -/** - * Returns the transistor count for a flip-flop - */ -static double power_count_transistors_FF(float size) { - double transistor_cnt = 0.; - - /* 4 1X Inverters */ - transistor_cnt += 4 * power_count_transistors_inv(size); - - /* 2 Muxes = 4 transmission gates */ - transistor_cnt += 4 * power_count_transistors_trans_gate(size); - - return transistor_cnt; -} - -double power_transistor_area(double num_MTAs) { - return num_MTAs * g_MTA_area; -} - -static double power_MTAs(float W_size) { - return 1 + (W_size - 1) * (POWER_DRC_MIN_W / POWER_MTA_W); -} - -static double power_MTAs_L(float L_size) { - return 1 + (L_size - 1) * (POWER_DRC_MIN_L / POWER_MTA_L); -} - -static void power_size_pb(void) { - int type_idx; - - for (type_idx = 0; type_idx < num_types; type_idx++) { - if (type_descriptors[type_idx].pb_graph_head) { - power_size_pb_rec(type_descriptors[type_idx].pb_graph_head); - } - } -} - -static void power_size_pb_rec(t_pb_graph_node * pb_node) { - int port_idx, pin_idx; - int mode_idx, type_idx, pb_idx; - boolean size_buffers_and_wires = TRUE; - - if (!power_method_is_transistor_level( - pb_node->pb_type->pb_type_power->estimation_method) - && pb_node != FILL_TYPE->pb_graph_head) { - /* Area information is only needed for: - * 1. Transistor-level estimation methods - * 2. the FILL_TYPE for tile size calculations - */ - return; - } - - /* Recursive call for all child pb nodes */ - for (mode_idx = 0; mode_idx < pb_node->pb_type->num_modes; mode_idx++) { - t_mode * mode = &pb_node->pb_type->modes[mode_idx]; - - for (type_idx = 0; type_idx < mode->num_pb_type_children; type_idx++) { - int num_pb = mode->pb_type_children[type_idx].num_pb; - - for (pb_idx = 0; pb_idx < num_pb; pb_idx++) { - - power_size_pb_rec( - &pb_node->child_pb_graph_nodes[mode_idx][type_idx][pb_idx]); - } - } - } - - /* Determine # of transistors for this node */ - power_count_transistors_pb_node(pb_node); - - if (pb_node->pb_type->class_type == LUT_CLASS) { - /* LUTs will have a child node that is used for routing purposes - * For the routing algorithms it is completely connected; however, - * this interconnect does not exist in FPGA hardware and should - * be ignored for power calculations. */ - size_buffers_and_wires = FALSE; - } - - if (!power_method_is_transistor_level( - pb_node->pb_type->pb_type_power->estimation_method)) { - size_buffers_and_wires = FALSE; - } - - /* Size all local buffers and wires */ - if (size_buffers_and_wires) { - for (port_idx = 0; port_idx < pb_node->num_input_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_input_pins[port_idx]; - pin_idx++) { - power_size_pin_buffers_and_wires( - &pb_node->input_pins[port_idx][pin_idx], TRUE); - } - } - - for (port_idx = 0; port_idx < pb_node->num_output_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_output_pins[port_idx]; - pin_idx++) { - power_size_pin_buffers_and_wires( - &pb_node->output_pins[port_idx][pin_idx], FALSE); - } - } - - for (port_idx = 0; port_idx < pb_node->num_clock_ports; port_idx++) { - for (pin_idx = 0; pin_idx < pb_node->num_clock_pins[port_idx]; - pin_idx++) { - power_size_pin_buffers_and_wires( - &pb_node->clock_pins[port_idx][pin_idx], TRUE); - } - } - } - -} - -/* Provides statistics about the connection between the pin and interconnect */ -static void power_size_pin_to_interconnect(t_interconnect * interc, - int * fanout, float * wirelength) { - - float this_interc_sidelength; - - /* Pin to interconnect wirelength */ - switch (interc->type) { - case DIRECT_INTERC: - *wirelength = 0; - *fanout = 1; - break; - case MUX_INTERC: - - case COMPLETE_INTERC: - /* The sidelength of this crossbar */ - this_interc_sidelength = sqrt( - power_transistor_area( - interc->interconnect_power->transistor_cnt)); - - /* Assume that inputs to the crossbar have a structure like this: - * - * A B|----- - * -----|---C- - * |----- - * - * A - wire from pin to point of fanout (grows pb interconnect area) - * B - fanout wire (sidelength of this crossbar) - * C - fanouts to crossbar muxes (grows with pb interconnect area) - */ - - *fanout = interc->interconnect_power->num_output_ports; - *wirelength = this_interc_sidelength; - //*wirelength = ((1 + *fanout) / 2.0) * g_power_arch->local_interc_factor - // * pb_interc_sidelength + this_interc_sidelength; - break; - default: - assert(0); - break; - } - -} - -static void power_size_pin_buffers_and_wires(t_pb_graph_pin * pin, - boolean pin_is_an_input) { - int edge_idx; - int list_cnt; - t_interconnect ** list; - boolean found; - int i; - - float C_load; - float this_pb_length; - - int fanout; - float wirelength_out = 0; - float wirelength_in = 0; - - int fanout_tmp; - float wirelength_tmp; - - float this_pb_interc_sidelength = 0; - float parent_pb_interc_sidelength = 0; - boolean top_level_pb; - - t_pb_type * this_pb_type = pin->parent_node->pb_type; - - /* - if (strcmp(pin->parent_node->pb_type->name, "clb") == 0) { - //printf("here\n"); - }*/ - - this_pb_interc_sidelength = sqrt( - power_transistor_area( - pin->parent_node->pb_node_power->transistor_cnt_interc)); - if (pin->parent_node->parent_pb_graph_node == NULL) { - top_level_pb = TRUE; - parent_pb_interc_sidelength = 0.; - } else { - top_level_pb = FALSE; - parent_pb_interc_sidelength = - sqrt( - power_transistor_area( - pin->parent_node->parent_pb_graph_node->pb_node_power->transistor_cnt_interc)); - } - - /* Pins are connected to a wire that is connected to: - * 1. Interconnect structures belonging its pb_node, and/or - * - The pb_node may have one or more modes, each with a set of - * interconnect. The capacitance is the worst-case capacitance - * between the different modes. - * - * 2. Interconnect structures belonging to its parent pb_node - */ - - /* We want to estimate the physical pin fan-out, unfortunately it is not defined in the architecture file. - * Instead, we know the modes of operation, and the fanout may differ depending on the mode. We assume - * that the physical fanout is the max of the connections to the various modes (although in reality it could - * be higher)*/ - - /* Loop through all edges, building a list of interconnect that this pin drives */ - list = NULL; - list_cnt = 0; - for (edge_idx = 0; edge_idx < pin->num_output_edges; edge_idx++) { - /* Check if its already in the list */ - found = FALSE; - for (i = 0; i < list_cnt; i++) { - if (list[i] == pin->output_edges[edge_idx]->interconnect) { - found = TRUE; - break; - } - } - - if (!found) { - list_cnt++; - list = (t_interconnect**) my_realloc(list, - list_cnt * sizeof(t_interconnect*)); - list[list_cnt - 1] = pin->output_edges[edge_idx]->interconnect; - } - } - - /* Determine the: - * 1. Wirelength connected to the pin - * 2. Fanout of the pin - */ - if (pin_is_an_input) { - /* Pin is an input to the PB. - * Thus, all interconnect it drives belong to the modes of the PB. - */ - int * fanout_per_mode; - float * wirelength_out_per_mode; - - fanout_per_mode = (int*) my_calloc(this_pb_type->num_modes, - sizeof(int)); - wirelength_out_per_mode = (float *) my_calloc(this_pb_type->num_modes, - sizeof(float)); - - for (i = 0; i < list_cnt; i++) { - int mode_idx = list[i]->parent_mode_index; - - power_size_pin_to_interconnect(list[i], &fanout_tmp, - &wirelength_tmp); - - fanout_per_mode[mode_idx] += fanout_tmp; - wirelength_out_per_mode[mode_idx] += wirelength_tmp; - } - - fanout = 0; - wirelength_out = 0.; - - /* Find worst-case between modes*/ - for (i = 0; i < this_pb_type->num_modes; i++) { - fanout = max(fanout, fanout_per_mode[i]); - wirelength_out = max(wirelength_out, wirelength_out_per_mode[i]); - } - if (wirelength_out != 0) { - wirelength_out += g_power_arch->local_interc_factor - * this_pb_interc_sidelength; - } - - free(fanout_per_mode); - free(wirelength_out_per_mode); - - /* Input wirelength - from parent PB */ - if (!top_level_pb) { - wirelength_in = g_power_arch->local_interc_factor - * parent_pb_interc_sidelength; - } - - } else { - /* Pin is an output of the PB. - * Thus, all interconnect it drives belong to the parent PB. - */ - fanout = 0; - wirelength_out = 0.; - - if (top_level_pb) { - /* Outputs of top-level pb should not drive interconnect */ - assert(list_cnt == 0); - } - - /* Loop through all interconnect that this pin drives */ - - for (i = 0; i < list_cnt; i++) { - power_size_pin_to_interconnect(list[i], &fanout_tmp, - &wirelength_tmp); - fanout += fanout_tmp; - wirelength_out += wirelength_tmp; - } - if (wirelength_out != 0) { - wirelength_out += g_power_arch->local_interc_factor - * parent_pb_interc_sidelength; - } - - /* Input wirelength - from this PB */ - wirelength_in = g_power_arch->local_interc_factor - * this_pb_interc_sidelength; - - } - free(list); - - /* Wirelength */ - switch (pin->port->port_power->wire_type) { - case POWER_WIRE_TYPE_IGNORED: - /* User is ignoring this wirelength */ - pin->pin_power->C_wire = 0.; - break; - case POWER_WIRE_TYPE_C: - pin->pin_power->C_wire = pin->port->port_power->wire.C; - break; - case POWER_WIRE_TYPE_ABSOLUTE_LENGTH: - pin->pin_power->C_wire = pin->port->port_power->wire.absolute_length - * g_power_arch->C_wire_local; - break; - case POWER_WIRE_TYPE_RELATIVE_LENGTH: - this_pb_length = sqrt( - power_transistor_area( - power_transistors_for_pb_node(pin->parent_node))); - pin->pin_power->C_wire = pin->port->port_power->wire.relative_length - * this_pb_length * g_power_arch->C_wire_local; - break; - - case POWER_WIRE_TYPE_AUTO: - pin->pin_power->C_wire += g_power_arch->C_wire_local - * (wirelength_in + wirelength_out); - break; - case POWER_WIRE_TYPE_UNDEFINED: - default: - assert(0); - break; - } - - /* Buffer */ - switch (pin->port->port_power->buffer_type) { - case POWER_BUFFER_TYPE_NONE: - /* User assumes no buffer */ - pin->pin_power->buffer_size = 0.; - break; - case POWER_BUFFER_TYPE_ABSOLUTE_SIZE: - pin->pin_power->buffer_size = pin->port->port_power->buffer_size; - break; - case POWER_BUFFER_TYPE_AUTO: - /* Asume the buffer drives the wire & fanout muxes */ - C_load = pin->pin_power->C_wire - + (fanout) * g_power_commonly_used->INV_1X_C_in; //g_power_commonly_used->NMOS_1X_C_d; - if (C_load > g_power_commonly_used->INV_1X_C_in) { - pin->pin_power->buffer_size = power_buffer_size_from_logical_effort( - C_load); - } else { - pin->pin_power->buffer_size = 0.; - } - break; - case POWER_BUFFER_TYPE_UNDEFINED: - default: - assert(0); - } - - pin->parent_node->pb_node_power->transistor_cnt_buffers += - power_count_transistors_buffer(pin->pin_power->buffer_size); -} diff --git a/vpr7_x2p/vpr/SRC/power/power_sizing.h b/vpr7_x2p/vpr/SRC/power/power_sizing.h deleted file mode 100644 index 4135c30bc..000000000 --- a/vpr7_x2p/vpr/SRC/power/power_sizing.h +++ /dev/null @@ -1,45 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/** - * The functions in this file are used to count the transistors in the - * FPGA, for physical size estimations - */ - -#ifndef __POWER_TRANSISTOR_CNT_H__ -#define __POWER_TRANSISTOR_CNT_H__ - -/************************* INCLUDES *********************************/ -#include "physical_types.h" - -/************************* DEFINES **********************************/ - -/* Design rules, values in LAMBDA, where tech size = 2 LAMBDA */ -#define POWER_DRC_MIN_L 2.0 -#define POWER_DRC_MIN_W 5.0 -#define POWER_DRC_MIN_DIFF_L 5.5 -#define POWER_DRC_SPACING 3.0 -#define POWER_DRC_POLY_OVERHANG 2.5 - -#define POWER_MTA_W (POWER_DRC_MIN_W + POWER_DRC_POLY_OVERHANG + POWER_DRC_SPACING) -#define POWER_MTA_L (POWER_DRC_MIN_L + 2 * POWER_DRC_MIN_DIFF_L + POWER_DRC_SPACING) - -/************************* FUNCTION DECLARATION *********************/ -void power_sizing_init(t_arch * arch); -double power_count_transistors_buffer(float buffer_size); -double power_transistor_area(double num_transistors); -#endif diff --git a/vpr7_x2p/vpr/SRC/power/power_util.c b/vpr7_x2p/vpr/SRC/power/power_util.c deleted file mode 100644 index a7d1264e3..000000000 --- a/vpr7_x2p/vpr/SRC/power/power_util.c +++ /dev/null @@ -1,606 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/** - * This file provides utility functions used by power estimation. - */ - -/************************* INCLUDES *********************************/ -#include -#include -using namespace std; - -#include - -#include "power_util.h" -#include "globals.h" - -/************************* GLOBALS **********************************/ - -/************************* FUNCTION DECLARATIONS*********************/ -static void log_msg(t_log * log_ptr, char * msg); -static void int_2_binary_str(char * binary_str, int value, int str_length); -static void init_mux_arch_default(t_mux_arch * mux_arch, int levels, - int num_inputs, float transistor_size); -static void alloc_and_load_mux_graph_recursive(t_mux_node * node, - int num_primary_inputs, int level, int starting_pin_idx); -static t_mux_node * alloc_and_load_mux_graph(int num_inputs, int levels); - -/************************* FUNCTION DEFINITIONS *********************/ -void power_zero_usage(t_power_usage * power_usage) { - power_usage->dynamic = 0.; - power_usage->leakage = 0.; -} - -void power_add_usage(t_power_usage * dest, const t_power_usage * src) { - dest->dynamic += src->dynamic; - dest->leakage += src->leakage; -} - -void power_scale_usage(t_power_usage * power_usage, float scale_factor) { - power_usage->dynamic *= scale_factor; - power_usage->leakage *= scale_factor; -} - -float power_sum_usage(t_power_usage * power_usage) { - return power_usage->dynamic + power_usage->leakage; -} - -float power_perc_dynamic(t_power_usage * power_usage) { - return power_usage->dynamic / power_sum_usage(power_usage); -} - -void power_log_msg(e_power_log_type log_type, char * msg) { - log_msg(&g_power_output->logs[log_type], msg); -} - -char * transistor_type_name(e_tx_type type) { - if (type == NMOS) { - return "NMOS"; - } else if (type == PMOS) { - return "PMOS"; - } else { - return "Unknown"; - } -} - -float pin_dens(t_pb * pb, t_pb_graph_pin * pin) { - float density = 0.; - - if (pb) { - int net_num; - net_num = pb->rr_graph[pin->pin_count_in_cluster].net_num; - - if (net_num != OPEN) { - density = vpack_net[net_num].net_power->density; - } - } - - return density; -} - -float pin_prob(t_pb * pb, t_pb_graph_pin * pin) { - /* Assumed pull-up on unused interconnect */ - float prob = 1.; - - if (pb) { - int net_num; - net_num = pb->rr_graph[pin->pin_count_in_cluster].net_num; - - if (net_num != OPEN) { - prob = vpack_net[net_num].net_power->probability; - } - } - - return prob; -} - -/** - * This function determines the values of the selectors in a static mux, based - * on the routing information. - * - selector_values: (Return values) selected index at each mux level - * - mux_node: - * - selected_input_pin: The input index to the multi-level mux that is chosen - */ -boolean mux_find_selector_values(int * selector_values, t_mux_node * mux_node, - int selected_input_pin) { - if (mux_node->level == 0) { - if ((selected_input_pin >= mux_node->starting_pin_idx) - && (selected_input_pin - <= (mux_node->starting_pin_idx + mux_node->num_inputs))) { - selector_values[mux_node->level] = selected_input_pin - - mux_node->starting_pin_idx; - return TRUE; - } - } else { - int input_idx; - for (input_idx = 0; input_idx < mux_node->num_inputs; input_idx++) { - if (mux_find_selector_values(selector_values, - &mux_node->children[input_idx], selected_input_pin)) { - selector_values[mux_node->level] = input_idx; - return TRUE; - } - } - } - return FALSE; -} - -static void log_msg(t_log * log_ptr, char * msg) { - int msg_idx; - - /* Check if this message is already in the log */ - for (msg_idx = 0; msg_idx < log_ptr->num_messages; msg_idx++) { - if (strcmp(log_ptr->messages[msg_idx], msg) == 0) { - return; - } - } - - if (log_ptr->num_messages <= MAX_LOGS) { - log_ptr->num_messages++; - log_ptr->messages = (char**) my_realloc(log_ptr->messages, - log_ptr->num_messages * sizeof(char*)); - } else { - /* Can't add any more messages */ - return; - } - - if (log_ptr->num_messages == (MAX_LOGS + 1)) { - const char * full_msg = "\n***LOG IS FULL***\n"; - log_ptr->messages[log_ptr->num_messages - 1] = (char*) my_calloc( - strlen(full_msg) + 1, sizeof(char)); - strncpy(log_ptr->messages[log_ptr->num_messages - 1], full_msg, - strlen(full_msg)); - } else { - log_ptr->messages[log_ptr->num_messages - 1] = (char*) my_calloc( - strlen(msg) + 1, sizeof(char)); - strncpy(log_ptr->messages[log_ptr->num_messages - 1], msg, strlen(msg)); - } -} - -/** - * Calculates the number of buffer stages required, to achieve a given buffer fanout - * final_stage_size: Size of the final inverter in the buffer, relative to a min size - * desired_stage_effort: The desired gain between stages, typically 4 - */ -int power_calc_buffer_num_stages(float final_stage_size, - float desired_stage_effort) { - int N = 1; - - if (final_stage_size <= 1.0) { - N = 1; - } else if (final_stage_size < desired_stage_effort) - N = 2; - else { - N = (int) (log(final_stage_size) / log(desired_stage_effort) + 1); - - /* We always round down. - * Perhaps N+1 would be closer to the desired stage effort, but the delay savings - * would likely not be worth the extra power/area - */ - } - - return N; -} - -/** - * Calculates the required effort of each stage of a buffer - * - N: The number of stages of the buffer - * - final_stage_size: Size of the final inverter in the buffer, relative to a min size - */ -float calc_buffer_stage_effort(int N, float final_stage_size) { - if (N > 1) - return pow((double) final_stage_size, (1.0 / ((double) N - 1))); - else - return 1.0; -} - -#if 0 -void integer_to_SRAMvalues(int SRAM_num, int input_integer, char SRAM_values[]) { - char binary_str[20]; - int binary_str_counter; - int local_integer; - int i; - - binary_str_counter = 0; - - local_integer = input_integer; - - while (local_integer > 0) { - if (local_integer % 2 == 0) { - SRAM_values[binary_str_counter++] = '0'; - } else { - SRAM_values[binary_str_counter++] = '1'; - } - local_integer = local_integer / 2; - } - - while (binary_str_counter < SRAM_num) { - SRAM_values[binary_str_counter++] = '0'; - } - - SRAM_values[binary_str_counter] = '\0'; - - for (i = 0; i < binary_str_counter; i++) { - binary_str[i] = SRAM_values[binary_str_counter - 1 - i]; - } - - binary_str[binary_str_counter] = '\0'; - -} -#endif - -/** - * This function converts an integer to a binary string - * - binary_str: (Return value) The created binary string - * - value: The integer value to convert - * - str_length: The length of the binary string - */ -static void int_2_binary_str(char * binary_str, int value, int str_length) { - int i; - int odd; - - binary_str[str_length] = '\0'; - - for (i = str_length - 1; i >= 0; i--, value >>= 1) { - odd = value % 2; - if (odd == 0) { - binary_str[i] = '0'; - } else { - binary_str[i] = '1'; - } - } -} - -/** - * This functions returns the LUT SRAM values from the given logic terms - * - LUT_size: The number of LUT inputs - * - truth_table: The logic terms saved from the BLIF file, in a linked list format - */ -char * alloc_SRAM_values_from_truth_table(int LUT_size, - t_linked_vptr * truth_table) { - char * SRAM_values; - int i; - int num_SRAM_bits; - char * binary_str; - char ** terms; - char * buffer; - char * str_loc; - boolean on_set; - t_linked_vptr * list_ptr; - int num_terms; - int term_idx; - int bit_idx; - int dont_care_start_pos; - - num_SRAM_bits = 1 << LUT_size; - SRAM_values = (char*) my_calloc(num_SRAM_bits + 1, sizeof(char)); - SRAM_values[num_SRAM_bits] = '\0'; - - if (!truth_table) { - for (i = 0; i < num_SRAM_bits; i++) { - SRAM_values[i] = '1'; - } - return SRAM_values; - } - - binary_str = (char*) my_calloc(LUT_size + 1, sizeof(char)); - buffer = (char*) my_calloc(LUT_size + 10, sizeof(char)); - - strcpy(buffer, (char*) truth_table->data_vptr); - - /* Check if this is an unconnected node - hopefully these will be - * ignored by VPR in the future - */ - if (strcmp(buffer, " 0") == 0) { - free(binary_str); - free(buffer); - return SRAM_values; - } else if (strcmp(buffer, " 1") == 0) { - for (i = 0; i < num_SRAM_bits; i++) { - SRAM_values[i] = '1'; - } - free(binary_str); - free(buffer); - return SRAM_values; - } - - /* If the LUT is larger than the terms, the lower significant bits will be don't cares */ - str_loc = strtok(buffer, " \t"); - dont_care_start_pos = strlen(str_loc); - - /* Find out if the truth table provides the ON-set or OFF-set */ - str_loc = strtok(NULL, " \t"); - on_set = TRUE; - if (str_loc[0] == '1') { - } else if (str_loc[0] == '0') { - on_set = FALSE; - } else { - assert(0); - } - - /* Count truth table terms */ - num_terms = 0; - for (list_ptr = truth_table; list_ptr != NULL; list_ptr = list_ptr->next) { - num_terms++; - } - terms = (char**) my_calloc(num_terms, sizeof(char *)); - - /* Extract truth table terms */ - for (list_ptr = truth_table, term_idx = 0; list_ptr != NULL; list_ptr = - list_ptr->next, term_idx++) { - terms[term_idx] = (char*) my_calloc(LUT_size + 1, sizeof(char)); - - strcpy(buffer, (char*) list_ptr->data_vptr); - str_loc = strtok(buffer, " \t"); - strcpy(terms[term_idx], str_loc); - - /* Fill don't cares for lower bits (when LUT is larger than term size) */ - for (bit_idx = dont_care_start_pos; bit_idx < LUT_size; bit_idx++) { - terms[term_idx][bit_idx] = '-'; - } - - /* Verify on/off consistency */ - str_loc = strtok(NULL, " \t"); - if (on_set) { - assert(str_loc[0] == '1'); - } else { - assert(str_loc[0] == '0'); - } - } - - /* Loop through all SRAM bits */ - for (i = 0; i < num_SRAM_bits; i++) { - /* Set default value */ - if (on_set) { - SRAM_values[i] = '0'; - } else { - SRAM_values[i] = '1'; - } - - /* Get binary number representing this SRAM index */ - int_2_binary_str(binary_str, i, LUT_size); - - /* Loop through truth table terms */ - for (term_idx = 0; term_idx < num_terms; term_idx++) { - boolean match = TRUE; - - for (bit_idx = 0; bit_idx < LUT_size; bit_idx++) { - if ((terms[term_idx][bit_idx] != '-') - && (terms[term_idx][bit_idx] != binary_str[bit_idx])) { - match = FALSE; - break; - } - } - - if (match) { - if (on_set) { - SRAM_values[i] = '1'; - } else { - SRAM_values[i] = '0'; - } - - /* No need to check the other terms, already matched */ - break; - } - } - - } - free(binary_str); - free(buffer); - for (term_idx = 0; term_idx < num_terms; term_idx++) { - free(terms[term_idx]); - } - free(terms); - - return SRAM_values; -} - -/* Reduce mux levels for multiplexers that are too small for the preset number of levels */ -void mux_arch_fix_levels(t_mux_arch * mux_arch) { - while (((1 << mux_arch->levels) > mux_arch->num_inputs) - && (mux_arch->levels > 1)) { - mux_arch->levels--; - } -} - -float clb_net_density(int net_idx) { - if (net_idx == OPEN) { - return 0.; - } else { - return clb_net[net_idx].net_power->density; - } -} - -float clb_net_prob(int net_idx) { - if (net_idx == OPEN) { - return 0.; - } else { - return clb_net[net_idx].net_power->probability; - } -} - -char * interconnect_type_name(enum e_interconnect type) { - switch (type) { - case COMPLETE_INTERC: - return "complete"; - case MUX_INTERC: - return "mux"; - case DIRECT_INTERC: - return "direct"; - default: - return ""; - } -} - -void output_log(t_log * log_ptr, FILE * fp) { - int msg_idx; - - for (msg_idx = 0; msg_idx < log_ptr->num_messages; msg_idx++) { - fprintf(fp, "%s\n", log_ptr->messages[msg_idx]); - } -} - -void output_logs(FILE * fp, t_log * logs, int num_logs) { - int log_idx; - - for (log_idx = 0; log_idx < num_logs; log_idx++) { - if (logs[log_idx].num_messages) { - power_print_title(fp, logs[log_idx].name); - output_log(&logs[log_idx], fp); - fprintf(fp, "\n"); - } - } -} - -float power_buffer_size_from_logical_effort(float C_load) { - return max(1.0f, - C_load / g_power_commonly_used->INV_1X_C_in - / (2 * g_power_arch->logical_effort_factor)); -} - -void power_print_title(FILE * fp, char * title) { - int i; - const int width = 80; - - int firsthalf = (width - strlen(title) - 2) / 2; - int secondhalf = width - strlen(title) - 2 - firsthalf; - - for (i = 1; i <= firsthalf; i++) - fprintf(fp, "-"); - fprintf(fp, " %s ", title); - for (i = 1; i <= secondhalf; i++) - fprintf(fp, "-"); - fprintf(fp, "\n"); -} - -t_mux_arch * power_get_mux_arch(int num_mux_inputs, float transistor_size) { - int i; - - t_power_mux_info * mux_info = NULL; - - /* Find the mux archs for the given transistor size */ - std::map::iterator it; - - it = g_power_commonly_used->mux_info.find(transistor_size); - - if (it == g_power_commonly_used->mux_info.end()) { - mux_info = new t_power_mux_info; - mux_info->mux_arch = NULL; - mux_info->mux_arch_max_size = 0; - g_power_commonly_used->mux_info[transistor_size] = mux_info; - } else { - mux_info = it->second; - } - - if (num_mux_inputs > mux_info->mux_arch_max_size) { - mux_info->mux_arch = (t_mux_arch*) my_realloc(mux_info->mux_arch, - (num_mux_inputs + 1) * sizeof(t_mux_arch)); - - for (i = mux_info->mux_arch_max_size + 1; i <= num_mux_inputs; i++) { - init_mux_arch_default(&mux_info->mux_arch[i], 2, i, - transistor_size); - } - mux_info->mux_arch_max_size = num_mux_inputs; - } - return &mux_info->mux_arch[num_mux_inputs]; -} - -/** - * Generates a default multiplexer architecture of given size and number of levels - */ -static void init_mux_arch_default(t_mux_arch * mux_arch, int levels, - int num_inputs, float transistor_size) { - - mux_arch->levels = levels; - mux_arch->num_inputs = num_inputs; - - mux_arch_fix_levels(mux_arch); - - mux_arch->transistor_size = transistor_size; - - mux_arch->mux_graph_head = alloc_and_load_mux_graph(num_inputs, - mux_arch->levels); -} - -/** - * Allocates a builds a multiplexer graph with given # inputs and levels - */ -static t_mux_node * alloc_and_load_mux_graph(int num_inputs, int levels) { - t_mux_node * node; - - node = (t_mux_node*) my_malloc(sizeof(t_mux_node)); - alloc_and_load_mux_graph_recursive(node, num_inputs, levels - 1, 0); - - return node; -} - -static void alloc_and_load_mux_graph_recursive(t_mux_node * node, - int num_primary_inputs, int level, int starting_pin_idx) { - int child_idx; - int pin_idx = starting_pin_idx; - - node->num_inputs = (int) (pow(num_primary_inputs, 1 / ((float) level + 1)) - + 0.5); - node->level = level; - node->starting_pin_idx = starting_pin_idx; - - if (level != 0) { - node->children = (t_mux_node*) my_calloc(node->num_inputs, - sizeof(t_mux_node)); - for (child_idx = 0; child_idx < node->num_inputs; child_idx++) { - int num_child_pi = num_primary_inputs / node->num_inputs; - if (child_idx < (num_primary_inputs % node->num_inputs)) { - num_child_pi++; - } - alloc_and_load_mux_graph_recursive(&node->children[child_idx], - num_child_pi, level - 1, pin_idx); - pin_idx += num_child_pi; - } - } -} - -boolean power_method_is_transistor_level( - e_power_estimation_method estimation_method) { - switch (estimation_method) { - case POWER_METHOD_AUTO_SIZES: - case POWER_METHOD_SPECIFY_SIZES: - return TRUE; - default: - return FALSE; - } -} - -boolean power_method_is_recursive(e_power_estimation_method method) { - switch (method) { - case POWER_METHOD_IGNORE: - case POWER_METHOD_TOGGLE_PINS: - case POWER_METHOD_C_INTERNAL: - case POWER_METHOD_ABSOLUTE: - return FALSE; - case POWER_METHOD_AUTO_SIZES: - case POWER_METHOD_SPECIFY_SIZES: - case POWER_METHOD_SUM_OF_CHILDREN: - return TRUE; - case POWER_METHOD_UNDEFINED: - default: - assert(0); - } - -// to get rid of warning - return FALSE; -} - diff --git a/vpr7_x2p/vpr/SRC/power/power_util.h b/vpr7_x2p/vpr/SRC/power/power_util.h deleted file mode 100644 index 80a5d124b..000000000 --- a/vpr7_x2p/vpr/SRC/power/power_util.h +++ /dev/null @@ -1,78 +0,0 @@ -/********************************************************************* - * The following code is part of the power modelling feature of VTR. - * - * For support: - * http://code.google.com/p/vtr-verilog-to-routing/wiki/Power - * - * or email: - * vtr.power.estimation@gmail.com - * - * If you are using power estimation for your researach please cite: - * - * Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation - * for Diverse FPGA Architectures. In International Conference on - * Field Programmable Technology, 2012. - * - ********************************************************************/ - -/** - * This file provides utility functions used by power estimation. - */ - -#ifndef __POWER_UTIL_H__ -#define __POWER_UTIL_H__ - -/************************* INCLUDES *********************************/ -#include "power.h" -#include "power_components.h" - -/************************* FUNCTION DECLARATIONS ********************/ - -/* Pins */ -float pin_dens(t_pb * pb, t_pb_graph_pin * pin); -float pin_prob(t_pb * pb, t_pb_graph_pin * pin); -int power_calc_pin_fanout(t_pb_graph_pin * pin, int mode_idx); -void pb_foreach_pin(t_pb_graph_node * pb_node, - void (*fn)(t_pb_graph_pin *, void *), void * context); - -/* Power Usage */ -void power_zero_usage(t_power_usage * power_usage); -void power_add_usage(t_power_usage * dest, const t_power_usage * src); -void power_scale_usage(t_power_usage * power_usage, float scale_factor); -float power_sum_usage(t_power_usage * power_usage); -float power_perc_dynamic(t_power_usage * power_usage); - -/* Message Logger */ -void power_log_msg(e_power_log_type log_type, char * msg); - -/* Buffers */ -int power_calc_buffer_num_stages(float final_stage_size, float desired_stage_effort); -float calc_buffer_stage_effort(int N, float final_stage_size); -float power_buffer_size_from_logical_effort(float C_load); - -/* Multiplexers */ -boolean mux_find_selector_values(int * selector_values, t_mux_node * mux_node, - int selected_input_pin); -t_mux_arch * power_get_mux_arch(int num_mux_inputs, float transistor_size); -void mux_arch_fix_levels(t_mux_arch * mux_arch); - -/* Power Methods */ -boolean power_method_is_transistor_level( - e_power_estimation_method estimation_method); -boolean power_method_is_recursive( - e_power_estimation_method method); - -char * transistor_type_name(e_tx_type type); -char * alloc_SRAM_values_from_truth_table(int LUT_size, - t_linked_vptr * truth_table); -float clb_net_density(int net_idx); -char * interconnect_type_name(enum e_interconnect type); -float clb_net_prob(int net_idx); - -void output_log(t_log * log_ptr, FILE * fp); - -void output_logs(FILE * fp, t_log * logs, int num_logs); - -void power_print_title(FILE * fp, char * title); - -#endif diff --git a/vpr7_x2p/vpr/SRC/route/check_route.c b/vpr7_x2p/vpr/SRC/route/check_route.c deleted file mode 100755 index 58c2a3646..000000000 --- a/vpr7_x2p/vpr/SRC/route/check_route.c +++ /dev/null @@ -1,759 +0,0 @@ -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "route_export.h" -#include "check_route.h" -#include "rr_graph.h" -#include "check_rr_graph.h" -#include "read_xml_arch_file.h" - -/* mrFPGA: Xifan TANG */ -#include "mrfpga_globals.h" -/* end */ - -/******************** Subroutines local to this module **********************/ -static void check_node_and_range(int inode, enum e_route_type route_type); -static void check_source(int inode, int inet); -static void check_sink(int inode, int inet, boolean * pin_done); -static void check_switch(struct s_trace *tptr, int num_switch); -static boolean check_adjacent(int from_node, int to_node); -static int pin_and_chan_adjacent(int pin_node, int chan_node); -static int chanx_chany_adjacent(int chanx_node, int chany_node); -static void reset_flags(int inet, boolean * connected_to_route); -static void recompute_occupancy_from_scratch(t_ivec ** clb_opins_used_locally); -static void check_locally_used_clb_opins(t_ivec ** clb_opins_used_locally, - enum e_route_type route_type); - -/************************ Subroutine definitions ****************************/ - -void check_route(enum e_route_type route_type, int num_switch, - t_ivec ** clb_opins_used_locally) { - - /* This routine checks that a routing: (1) Describes a properly * - * connected path for each net, (2) this path connects all the * - * pins spanned by that net, and (3) that no routing resources are * - * oversubscribed (the occupancy of everything is recomputed from * - * scratch). */ - - int inet, ipin, max_pins, inode, prev_node; - boolean valid, connects; - boolean * connected_to_route; /* [0 .. num_rr_nodes-1] */ - struct s_trace *tptr; - boolean * pin_done; - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Checking to ensure routing is legal...\n"); - - /* Recompute the occupancy from scratch and check for overuse of routing * - * resources. This was already checked in order to determine that this * - * is a successful routing, but I want to double check it here. */ - - recompute_occupancy_from_scratch(clb_opins_used_locally); - valid = feasible_routing(); - if (valid == FALSE) { - vpr_printf(TIO_MESSAGE_ERROR, "Error in check_route -- routing resources are overused.\n"); - exit(1); - } - - check_locally_used_clb_opins(clb_opins_used_locally, route_type); - - connected_to_route = (boolean *) my_calloc(num_rr_nodes, sizeof(boolean)); - - max_pins = 0; - for (inet = 0; inet < num_nets; inet++) - max_pins = std::max(max_pins, (clb_net[inet].num_sinks + 1)); - - pin_done = (boolean *) my_malloc(max_pins * sizeof(boolean)); - - /* Now check that all nets are indeed connected. */ - - for (inet = 0; inet < num_nets; inet++) { - - if (clb_net[inet].is_global || clb_net[inet].num_sinks == 0) /* Skip global nets. */ - continue; - - for (ipin = 0; ipin < (clb_net[inet].num_sinks + 1); ipin++) - pin_done[ipin] = FALSE; - - /* Check the SOURCE of the net. */ - - tptr = trace_head[inet]; - if (tptr == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_route: net %d has no routing.\n", inet); - exit(1); - } - - inode = tptr->index; - check_node_and_range(inode, route_type); - check_switch(tptr, num_switch); - connected_to_route[inode] = TRUE; /* Mark as in path. */ - - check_source(inode, inet); - pin_done[0] = TRUE; - - prev_node = inode; - tptr = tptr->next; - - /* Check the rest of the net */ - - while (tptr != NULL) { - inode = tptr->index; - check_node_and_range(inode, route_type); - check_switch(tptr, num_switch); - - if (rr_node[prev_node].type == SINK) { - if (connected_to_route[inode] == FALSE) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_route: node %d does not link into existing routing for net %d.\n", inode, inet); - exit(1); - } - } - - else { - connects = check_adjacent(prev_node, inode); - if (!connects) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_route: found non-adjacent segments in traceback while checking net %d.\n", inet); - exit(1); - } - - if (connected_to_route[inode] && rr_node[inode].type != SINK) { - - /* Note: Can get multiple connections to the same logically-equivalent * - * SINK in some logic blocks. */ - - vpr_printf(TIO_MESSAGE_ERROR, "in check_route: net %d routing is not a tree.\n", inet); - exit(1); - } - - connected_to_route[inode] = TRUE; /* Mark as in path. */ - - if (rr_node[inode].type == SINK) - check_sink(inode, inet, pin_done); - - } /* End of prev_node type != SINK */ - prev_node = inode; - tptr = tptr->next; - } /* End while */ - - if (rr_node[prev_node].type != SINK) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_route: net %d does not end with a SINK.\n", inet); - exit(1); - } - - for (ipin = 0; ipin < (clb_net[inet].num_sinks + 1); ipin++) { - if (pin_done[ipin] == FALSE) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_route: net %d does not connect to pin %d.\n", inet, ipin); - exit(1); - } - } - - reset_flags(inet, connected_to_route); - - } /* End for each net */ - - free(pin_done); - free(connected_to_route); - vpr_printf(TIO_MESSAGE_INFO, "Completed routing consistency check successfully.\n"); - vpr_printf(TIO_MESSAGE_INFO, "\n"); -} - -static void check_sink(int inode, int inet, boolean * pin_done) { - - /* Checks that this SINK node is one of the terminals of inet, and marks * - * the appropriate pin as being reached. */ - - int i, j, ipin, ifound, ptc_num, bnum, iclass, node_block_pin, iblk; - t_type_ptr type; - - assert(rr_node[inode].type == SINK); - i = rr_node[inode].xlow; - j = rr_node[inode].ylow; - type = grid[i][j].type; - ptc_num = rr_node[inode].ptc_num; /* For sinks, ptc_num is the class */ - ifound = 0; - - for (iblk = 0; iblk < type->capacity; iblk++) { - bnum = grid[i][j].blocks[iblk]; /* Hardcoded to one block */ - for (ipin = 1; ipin < (clb_net[inet].num_sinks + 1); ipin++) { /* All net SINKs */ - if (clb_net[inet].node_block[ipin] == bnum) { - node_block_pin = clb_net[inet].node_block_pin[ipin]; - iclass = type->pin_class[node_block_pin]; - if (iclass == ptc_num) { - /* Could connect to same pin class on the same clb more than once. Only * - * update pin_done for a pin that hasn't been reached yet. */ - - if (pin_done[ipin] == FALSE) { - ifound++; - pin_done[ipin] = TRUE; - } - } - } - } - } - - if (ifound > 1 && type == IO_TYPE) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_sink: found %d terminals of net %d of pad %d at location (%d, %d).\n", ifound, inet, ptc_num, i, j); - exit(1); - } - - if (ifound < 1) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_sink: node %d does not connect to any terminal of net %s #%d.\n" - "This error is usually caused by incorrectly specified logical equivalence in your architecture file.\n" - "You should try to respecify what pins are equivalent or turn logical equivalence off.\n", inode, clb_net[inet].name, inet); - exit(1); - } -} - -static void check_source(int inode, int inet) { - - /* Checks that the node passed in is a valid source for this net. */ - - t_rr_type rr_type; - t_type_ptr type; - int i, j, ptc_num, bnum, node_block_pin, iclass; - - rr_type = rr_node[inode].type; - if (rr_type != SOURCE) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_source: net %d begins with a node of type %d.\n", inet, rr_type); - exit(1); - } - - i = rr_node[inode].xlow; - j = rr_node[inode].ylow; - ptc_num = rr_node[inode].ptc_num; /* for sinks and sources, ptc_num is class */ - bnum = clb_net[inet].node_block[0]; /* First node_block for net is the source */ - type = grid[i][j].type; - - if (block[bnum].x != i || block[bnum].y != j) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_source: net SOURCE is in wrong location (%d,%d).\n", i, j); - exit(1); - } - - node_block_pin = clb_net[inet].node_block_pin[0]; - iclass = type->pin_class[node_block_pin]; - - if (ptc_num != iclass) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_source: net SOURCE is of wrong class (%d).\n", ptc_num); - exit(1); - } -} - -static void check_switch(struct s_trace *tptr, int num_switch) { - - /* Checks that the switch leading from this traceback element to the next * - * one is a legal switch type. */ - - int inode; - short switch_type; - - inode = tptr->index; - switch_type = tptr->iswitch; - - if (rr_node[inode].type != SINK) { - if (switch_type < 0 || switch_type >= num_switch) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_switch: rr_node %d left via switch type %d.\n", inode, switch_type); - vpr_printf(TIO_MESSAGE_ERROR, "\tSwitch type is out of range.\n"); - exit(1); - } - } - - else { /* Is a SINK */ - - /* Without feedthroughs, there should be no switch. If feedthroughs are * - * allowed, change to treat a SINK like any other node (as above). */ - - if (switch_type != OPEN) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_switch: rr_node %d is a SINK, but attempts to use a switch of type %d.\n", - inode, switch_type); - exit(1); - } - } -} - -static void reset_flags(int inet, boolean * connected_to_route) { - - /* This routine resets the flags of all the channel segments contained * - * in the traceback of net inet to 0. This allows us to check the * - * next net for connectivity (and the default state of the flags * - * should always be zero after they have been used). */ - - struct s_trace *tptr; - int inode; - - tptr = trace_head[inet]; - - while (tptr != NULL) { - inode = tptr->index; - connected_to_route[inode] = FALSE; /* Not in routed path now. */ - tptr = tptr->next; - } -} - -static boolean check_adjacent(int from_node, int to_node) { - - /* This routine checks if the rr_node to_node is reachable from from_node. * - * It returns TRUE if is reachable and FALSE if it is not. Check_node has * - * already been used to verify that both nodes are valid rr_nodes, so only * - * adjacency is checked here. - * Special case: direct OPIN to IPIN connections need not be adjacent. These - * represent specially-crafted connections such as carry-chains or more advanced - * blocks where adjacency is overridden by the architect */ - - - int from_xlow, from_ylow, to_xlow, to_ylow, from_ptc, to_ptc, iclass; - int num_adj, to_xhigh, to_yhigh, from_xhigh, from_yhigh, iconn; - boolean reached; - t_rr_type from_type, to_type; - t_type_ptr from_grid_type, to_grid_type; - - reached = FALSE; - - for (iconn = 0; iconn < rr_node[from_node].num_edges; iconn++) { - if (rr_node[from_node].edges[iconn] == to_node) { - reached = TRUE; - break; - } - } - - if (!reached) - return (FALSE); - - /* Now we know the rr graph says these two nodes are adjacent. Double * - * check that this makes sense, to verify the rr graph. */ - - num_adj = 0; - - from_type = rr_node[from_node].type; - from_xlow = rr_node[from_node].xlow; - from_ylow = rr_node[from_node].ylow; - from_xhigh = rr_node[from_node].xhigh; - from_yhigh = rr_node[from_node].yhigh; - from_ptc = rr_node[from_node].ptc_num; - to_type = rr_node[to_node].type; - to_xlow = rr_node[to_node].xlow; - to_ylow = rr_node[to_node].ylow; - to_xhigh = rr_node[to_node].xhigh; - to_yhigh = rr_node[to_node].yhigh; - to_ptc = rr_node[to_node].ptc_num; - - switch (from_type) { - - case SOURCE: - assert(to_type == OPIN); - if (from_xlow == to_xlow && from_ylow == to_ylow - && from_xhigh == to_xhigh && from_yhigh == to_yhigh) { - - from_grid_type = grid[from_xlow][from_ylow].type; - to_grid_type = grid[to_xlow][to_ylow].type; - assert(from_grid_type == to_grid_type); - - iclass = to_grid_type->pin_class[to_ptc]; - if (iclass == from_ptc) { - num_adj++; - /* Xifan TANG: fully_capable network dirty hack: - * more rules, if they belong to the same port, we think they are adjacent - */ - } else if (OPEN != rr_node[from_node].net_num) { - num_adj++; - } - } - break; - - case SINK: - /* SINKS are adjacent to not connected */ - break; - - case OPIN: - if(to_type == CHANX || to_type == CHANY) { - /* Xifan TANG: a dirty hack for pin_equivalence auto detect */ - from_grid_type = grid[from_xlow][from_ylow].type; - if (TRUE == from_grid_type->output_ports_eq_auto_detect) { - num_adj = 1; - break; - } - /* END */ - /* Original VPR */ - num_adj += pin_and_chan_adjacent(from_node, to_node); - } else { - assert(to_type == IPIN); /* direct OPIN to IPIN connections not necessarily adjacent */ - return TRUE; /* Special case, direct OPIN to IPIN connections need not be adjacent */ - } - - break; - - case IPIN: - assert(to_type == SINK); - if (from_xlow == to_xlow && from_ylow == to_ylow - && from_xhigh == to_xhigh && from_yhigh == to_yhigh) { - - from_grid_type = grid[from_xlow][from_ylow].type; - to_grid_type = grid[to_xlow][to_ylow].type; - assert(from_grid_type == to_grid_type); - - iclass = from_grid_type->pin_class[from_ptc]; - if (iclass == to_ptc) - num_adj++; - } - break; - - case CHANX: - if (to_type == IPIN) { - num_adj += pin_and_chan_adjacent(to_node, from_node); - } else if (to_type == CHANX) { - /* mrFPGA: Xifan TANG */ - if (is_stack) { - if (from_xlow == to_xlow) { - if (to_yhigh == from_ylow-1 || from_yhigh == to_ylow-1) { - num_adj++; - } - } - } else { - /* end */ - /* Original VPR */ - from_xhigh = rr_node[from_node].xhigh; - to_xhigh = rr_node[to_node].xhigh; - if (from_ylow == to_ylow) { - /* UDSD Modification by WMF Begin */ - /*For Fs > 3, can connect to overlapping wire segment */ - if (to_xhigh == from_xlow - 1 || from_xhigh == to_xlow - 1) { - num_adj++; - } - /* Overlapping */ - else { - int i; - - for (i = from_xlow; i <= from_xhigh; i++) { - if (i >= to_xlow && i <= to_xhigh) { - num_adj++; - break; - } - } - } - /* UDSD Modification by WMF End */ - } - /* end */ - } - } else if (to_type == CHANY) { - num_adj += chanx_chany_adjacent(from_node, to_node); - } else { - assert(0); - } - break; - - case CHANY: - if (to_type == IPIN) { - num_adj += pin_and_chan_adjacent(to_node, from_node); - } else if (to_type == CHANY) { - /* mrFPGA: Xifan TANG */ - if (is_stack) { - if (from_ylow == to_ylow) { - if (to_xhigh == from_xlow-1 || from_xhigh == to_xlow-1) { - num_adj++; - } - } - } else { - /* end */ - /* Original VPR */ - from_yhigh = rr_node[from_node].yhigh; - to_yhigh = rr_node[to_node].yhigh; - if (from_xlow == to_xlow) { - /* UDSD Modification by WMF Begin */ - if (to_yhigh == from_ylow - 1 || from_yhigh == to_ylow - 1) { - num_adj++; - } - /* Overlapping */ - else { - int j; - - for (j = from_ylow; j <= from_yhigh; j++) { - if (j >= to_ylow && j <= to_yhigh) { - num_adj++; - break; - } - } - } - /* UDSD Modification by WMF End */ - } - /* end */ - } - } else if (to_type == CHANX) { - num_adj += chanx_chany_adjacent(to_node, from_node); - } else { - assert(0); - } - break; - - default: - break; - - } - - if (num_adj == 1) - return (TRUE); - else if (num_adj == 0) - return (FALSE); - - vpr_printf(TIO_MESSAGE_ERROR, "in check_adjacent: num_adj = %d. Expected 0 or 1.\n", num_adj); - exit(1); -} - -static int chanx_chany_adjacent(int chanx_node, int chany_node) { - - /* Returns 1 if the specified CHANX and CHANY nodes are adjacent, 0 * - * otherwise. */ - - int chanx_y, chanx_xlow, chanx_xhigh; - int chany_x, chany_ylow, chany_yhigh; - - /* mrFPGA: Xifan TANG */ - if (is_stack) { - if (rr_node[chanx_node].xlow > rr_node[chany_node].xhigh + 1 - || rr_node[chanx_node].xhigh < rr_node[chany_node].xlow) { - return 0; - } - if (rr_node[chany_node].ylow > rr_node[chanx_node].yhigh + 1 - || rr_node[chany_node].yhigh < rr_node[chanx_node].ylow) { - return 0; - } - return 1; - } - /* end */ - /* Original VPR */ - chanx_y = rr_node[chanx_node].ylow; - chanx_xlow = rr_node[chanx_node].xlow; - chanx_xhigh = rr_node[chanx_node].xhigh; - - chany_x = rr_node[chany_node].xlow; - chany_ylow = rr_node[chany_node].ylow; - chany_yhigh = rr_node[chany_node].yhigh; - - if (chany_ylow > chanx_y + 1 || chany_yhigh < chanx_y) - return (0); - - if (chanx_xlow > chany_x + 1 || chanx_xhigh < chany_x) - return (0); - - return (1); - /* end */ -} - -static int pin_and_chan_adjacent(int pin_node, int chan_node) { - - /* Checks if pin_node is adjacent to chan_node. It returns 1 if the two * - * nodes are adjacent and 0 if they are not (any other value means there's * - * a bug in this routine). */ - - int num_adj, pin_xlow, pin_ylow, pin_xhigh, pin_yhigh, chan_xlow, chan_ylow, - chan_xhigh, chan_yhigh; - int pin_ptc, i; - t_rr_type chan_type; - t_type_ptr pin_grid_type; - - num_adj = 0; - pin_xlow = rr_node[pin_node].xlow; - pin_ylow = rr_node[pin_node].ylow; - pin_xhigh = rr_node[pin_node].xhigh; - pin_yhigh = rr_node[pin_node].yhigh; - pin_grid_type = grid[pin_xlow][pin_ylow].type; - pin_ptc = rr_node[pin_node].ptc_num; - chan_type = rr_node[chan_node].type; - chan_xlow = rr_node[chan_node].xlow; - chan_ylow = rr_node[chan_node].ylow; - chan_xhigh = rr_node[chan_node].xhigh; - chan_yhigh = rr_node[chan_node].yhigh; - - if (chan_type == CHANX) { - /* mrFPGA: Xifan TANG */ - if (is_stack) { - for (i = 0; i < pin_grid_type->height; i++) { - /* CHANX below CLB */ - if (pin_grid_type->pinloc[i][BOTTOM][pin_ptc] == 1 - && pin_yhigh > chan_ylow - && pin_ylow <= chan_yhigh + 1 - && pin_xlow == chan_xlow - && pin_xlow == chan_xhigh) { - num_adj++; - } - /* CHANX above CLB */ - if (pin_grid_type->pinloc[i][TOP][pin_ptc] == 1 - && pin_yhigh >= chan_ylow - && pin_ylow <= chan_yhigh - && pin_xlow == chan_xlow - && pin_xlow == chan_xhigh) { - num_adj++; - } - } - } else { - /* end */ - if (chan_ylow == pin_yhigh) { /* CHANX above CLB */ - if (pin_grid_type->pinloc[pin_grid_type->height - 1][TOP][pin_ptc] - == 1 && pin_xlow <= chan_xhigh && pin_xhigh >= chan_xlow) - num_adj++; - } else if (chan_ylow == pin_ylow - 1) { /* CHANX below CLB */ - if (pin_grid_type->pinloc[0][BOTTOM][pin_ptc] == 1 - && pin_xlow <= chan_xhigh && pin_xhigh >= chan_xlow) - num_adj++; - } - } - } else if (chan_type == CHANY) { - /* mrFPGA: Xifan TANG */ - if (is_stack) { - for (i = 0; i < pin_grid_type->height; i++) { - /* CHANY to right of CLB */ - if (pin_grid_type->pinloc[i][RIGHT][pin_ptc] == 1 - && pin_ylow <= chan_yhigh - && pin_yhigh >= chan_ylow - && pin_xlow >= chan_xlow - && pin_xlow <= chan_xhigh) { - num_adj++; - } - /* CHANY to left of CLB */ - if (pin_grid_type->pinloc[i][LEFT][pin_ptc] == 1 - && pin_ylow <= chan_yhigh - && pin_yhigh >= chan_ylow - && pin_xlow > chan_xlow - && pin_xlow <= chan_xhigh + 1) { - num_adj++; - } - } - } else { - /* end */ - for (i = 0; i < pin_grid_type->height; i++) { - if (chan_xlow == pin_xhigh) { /* CHANY to right of CLB */ - if (pin_grid_type->pinloc[i][RIGHT][pin_ptc] == 1 - && pin_ylow <= chan_yhigh && pin_yhigh >= chan_ylow) - num_adj++; - } else if (chan_xlow == pin_xlow - 1) { /* CHANY to left of CLB */ - if (pin_grid_type->pinloc[i][LEFT][pin_ptc] == 1 - && pin_ylow <= chan_yhigh && pin_yhigh >= chan_ylow) - num_adj++; - } - } - } - } - return (num_adj); -} - -static void recompute_occupancy_from_scratch(t_ivec ** clb_opins_used_locally) { - - /* This routine updates the occ field in the rr_node structure according to * - * the resource usage of the current routing. It does a brute force * - * recompute from scratch that is useful for sanity checking. */ - - int inode, inet, iblk, iclass, ipin, num_local_opins; - struct s_trace *tptr; - - /* First set the occupancy of everything to zero. */ - - for (inode = 0; inode < num_rr_nodes; inode++) - rr_node[inode].occ = 0; - - /* Now go through each net and count the tracks and pins used everywhere */ - - for (inet = 0; inet < num_nets; inet++) { - - if (clb_net[inet].is_global) /* Skip global nets. */ - continue; - - tptr = trace_head[inet]; - if (tptr == NULL) - continue; - - for (;;) { - inode = tptr->index; - rr_node[inode].occ++; - - if (rr_node[inode].type == SINK) { - tptr = tptr->next; /* Skip next segment. */ - if (tptr == NULL) - break; - } - - tptr = tptr->next; - } - } - - /* Now update the occupancy of each of the "locally used" OPINs on each CLB * - * (CLB outputs used up by being directly wired to subblocks used only * - * locally). */ - - for (iblk = 0; iblk < num_blocks; iblk++) { - /* Xifan TANG: Bypass pin equivalence auto detect block */ - if (TRUE == block[iblk].type->output_ports_eq_auto_detect) { - continue; - } - /* Original VPR */ - for (iclass = 0; iclass < block[iblk].type->num_class; iclass++) { - num_local_opins = clb_opins_used_locally[iblk][iclass].nelem; - /* Will always be 0 for pads or SINK classes. */ - for (ipin = 0; ipin < num_local_opins; ipin++) { - inode = clb_opins_used_locally[iblk][iclass].list[ipin]; - rr_node[inode].occ++; - } - } - } -} - -static void check_locally_used_clb_opins(t_ivec ** clb_opins_used_locally, - enum e_route_type route_type) { - - /* Checks that enough OPINs on CLBs have been set aside (used up) to make a * - * legal routing if subblocks connect to OPINs directly. */ - - int iclass, iblk, num_local_opins, inode, ipin; - t_rr_type rr_type; - - for (iblk = 0; iblk < num_blocks; iblk++) { - /* Xifan TANG: do not check the class when pin equivalence auto-detect is turned on */ - if (TRUE == block[iblk].type->output_ports_eq_auto_detect) { - continue; - } - - for (iclass = 0; iclass < block[iblk].type->num_class; iclass++) { - num_local_opins = clb_opins_used_locally[iblk][iclass].nelem; - /* Always 0 for pads and for SINK classes */ - - for (ipin = 0; ipin < num_local_opins; ipin++) { - inode = clb_opins_used_locally[iblk][iclass].list[ipin]; - check_node_and_range(inode, route_type); /* Node makes sense? */ - - /* Now check that node is an OPIN of the right type. */ - - rr_type = rr_node[inode].type; - if (rr_type != OPIN) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_locally_used_opins: block #%d (%s)\n", - iblk, block[iblk].name); - vpr_printf(TIO_MESSAGE_ERROR, "\tClass %d local OPIN is wrong rr_type -- rr_node #%d of type %d.\n", - iclass, inode, rr_type); - exit(1); - } - - ipin = rr_node[inode].ptc_num; - if (block[iblk].type->pin_class[ipin] != iclass) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_locally_used_opins: block #%d (%s):\n", - iblk, block[iblk].name); - vpr_printf(TIO_MESSAGE_ERROR, "\tExpected class %d local OPIN has class %d -- rr_node #: %d.\n", - iclass, block[iblk].type->pin_class[ipin], inode); - /* Xifan TANG: reduce this error to warning when multi- fan_in is found */ - //if (1 == rr_node[inode].fan_in) { - exit(1); - //} - } - } - } - } -} - -static void check_node_and_range(int inode, enum e_route_type route_type) { - - /* Checks that inode is within the legal range, then calls check_node to * - * check that everything else about the node is OK. */ - - if (inode < 0 || inode >= num_rr_nodes) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node_and_range: rr_node #%d is out of legal, range (0 to %d).\n", - inode, num_rr_nodes - 1); - exit(1); - } - check_node(inode, route_type); -} diff --git a/vpr7_x2p/vpr/SRC/route/check_route.h b/vpr7_x2p/vpr/SRC/route/check_route.h deleted file mode 100755 index 106b22d78..000000000 --- a/vpr7_x2p/vpr/SRC/route/check_route.h +++ /dev/null @@ -1,2 +0,0 @@ -void check_route(enum e_route_type route_type, int num_switch, - t_ivec ** clb_opins_used_locally); diff --git a/vpr7_x2p/vpr/SRC/route/check_rr_graph.c b/vpr7_x2p/vpr/SRC/route/check_rr_graph.c deleted file mode 100755 index b3fb098a9..000000000 --- a/vpr7_x2p/vpr/SRC/route/check_rr_graph.c +++ /dev/null @@ -1,589 +0,0 @@ -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "check_rr_graph.h" - -/* mrFPGA: Xifan TANG */ -#include "mrfpga_globals.h" -/* end */ - -/********************** Local defines and types *****************************/ - -#define BUF_FLAG 1 -#define PTRANS_FLAG 2 -#define BUF_AND_PTRANS_FLAG 3 - -/*********************** Subroutines local to this module *******************/ - -static boolean rr_node_is_global_clb_ipin(int inode); - -static void check_pass_transistors(int from_node); - -/************************ Subroutine definitions ****************************/ -/**************************************************************************** - * Print detailed information of a node to ease debugging - ****************************************************************************/ -static -void print_rr_node_details(t_rr_node* cur_rr_node) { - vpr_printf(TIO_MESSAGE_INFO, - "\tNode %d details: type=%s, (xlow,ylow)=(%d,%d)->(xhigh,yhigh)=(%d,%d), ptc_num=%d\n", - cur_rr_node - rr_node, - rr_node_typename[cur_rr_node->type], - cur_rr_node->xlow, cur_rr_node->ylow, - cur_rr_node->xhigh, cur_rr_node->yhigh, - cur_rr_node->ptc_num); - return; -} - - -void check_rr_graph(INP const t_graph_type graph_type, - INP const int L_nx, INP const int L_ny, - INP const int num_switches, - int **Fc_in) { - - int *num_edges_from_current_to_node; /* [0..num_rr_nodes-1] */ - int *total_edges_to_node; /* [0..num_rr_nodes-1] */ - char *switch_types_from_current_to_node; /* [0..num_rr_nodes-1] */ - int inode, iedge, to_node, num_edges; - short switch_type; - t_rr_type rr_type, to_rr_type; - enum e_route_type route_type; - boolean is_fringe_warning_sent; - t_type_ptr type; - - route_type = DETAILED; - if (graph_type == GRAPH_GLOBAL) { - route_type = GLOBAL; - } - - total_edges_to_node = (int *) my_calloc(num_rr_nodes, sizeof(int)); - num_edges_from_current_to_node = (int *) my_calloc(num_rr_nodes, - sizeof(int)); - switch_types_from_current_to_node = (char *) my_calloc(num_rr_nodes, - sizeof(char)); - - for (inode = 0; inode < num_rr_nodes; inode++) { - rr_type = rr_node[inode].type; - num_edges = rr_node[inode].num_edges; - - check_node(inode, route_type); - - /* Check all the connectivity (edges, etc.) information. */ - - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = rr_node[inode].edges[iedge]; - - if (to_node < 0 || to_node >= num_rr_nodes) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_rr_graph: node %d has an edge %d.\n", inode, to_node); - print_rr_node_details(&rr_node[inode]); - - vpr_printf(TIO_MESSAGE_ERROR, "\tEdge is out of range.\n"); - exit(1); - } - - num_edges_from_current_to_node[to_node]++; - total_edges_to_node[to_node]++; - - switch_type = rr_node[inode].switches[iedge]; - - if (switch_type < 0 || switch_type >= num_switches) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_rr_graph: node %d has a switch type %d.\n", inode, switch_type); - print_rr_node_details(&rr_node[inode]); - vpr_printf(TIO_MESSAGE_ERROR, "\tSwitch type is out of range.\n"); - exit(1); - } - - if (switch_inf[switch_type].buffered) - switch_types_from_current_to_node[to_node] |= BUF_FLAG; - else - switch_types_from_current_to_node[to_node] |= PTRANS_FLAG; - - } /* End for all edges of node. */ - - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = rr_node[inode].edges[iedge]; - - if (num_edges_from_current_to_node[to_node] > 1) { - to_rr_type = rr_node[to_node].type; - - if ((to_rr_type != CHANX && to_rr_type != CHANY) - || (rr_type != CHANX && rr_type != CHANY)) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_rr_graph: node %d connects to node %d %d times.\n", - inode, to_node, num_edges_from_current_to_node[to_node]); - print_rr_node_details(&rr_node[inode]); - print_rr_node_details(&rr_node[to_node]); - exit(1); - } - - /* Between two wire segments. Two connections are legal only if * - * one connection is a buffer and the other is a pass transistor. */ - - else if (num_edges_from_current_to_node[to_node] != 2 - || switch_types_from_current_to_node[to_node] != BUF_AND_PTRANS_FLAG) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_rr_graph: node %d connects to node %d %d times.\n", - inode, to_node, num_edges_from_current_to_node[to_node]); - print_rr_node_details(&rr_node[inode]); - print_rr_node_details(&rr_node[to_node]); - exit(1); - } - } - - num_edges_from_current_to_node[to_node] = 0; - switch_types_from_current_to_node[to_node] = 0; - } - - /* Slow test below. Leave commented out most of the time. */ - -#ifdef DEBUG - check_pass_transistors(inode); -#endif - - } /* End for all rr_nodes */ - - /* I built a list of how many edges went to everything in the code above -- * - * now I check that everything is reachable. */ - is_fringe_warning_sent = FALSE; - - for (inode = 0; inode < num_rr_nodes; inode++) { - rr_type = rr_node[inode].type; - - if (rr_type != SOURCE) { - if (total_edges_to_node[inode] < 1 - && !rr_node_is_global_clb_ipin(inode)) { - boolean is_fringe; - boolean is_wire; - boolean is_chain = FALSE; - - /* A global CLB input pin will not have any edges, and neither will * - * a SOURCE or the start of a carry-chain. Anything else is an error. - * For simplicity, carry-chain input pin are entirely ignored in this test - */ - - if(rr_type == IPIN) { - type = grid[rr_node[inode].xlow][rr_node[inode].ylow].type; - if(Fc_in[type->index][rr_node[inode].ptc_num] == 0) { - is_chain = TRUE; - } - } - - is_fringe = (boolean)((rr_node[inode].xlow == 1) - || (rr_node[inode].ylow == 1) - || (rr_node[inode].xhigh == L_nx) - || (rr_node[inode].yhigh == L_ny)); - is_wire = (boolean)(rr_node[inode].type == CHANX - || rr_node[inode].type == CHANY); - - if (!is_chain && !is_fringe && !is_wire) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_rr_graph: node %d has no fanin.\n", inode); - print_rr_node_details(&rr_node[inode]); - exit(1); - } else if (!is_chain && !is_fringe_warning_sent) { - vpr_printf(TIO_MESSAGE_WARNING, "in check_rr_graph: fringe node %d has no fanin.\n", inode); - vpr_printf(TIO_MESSAGE_WARNING, "\tThis is possible on the fringe for low Fc_out, N, and certain Lengths\n"); - print_rr_node_details(&rr_node[inode]); - is_fringe_warning_sent = TRUE; - } - } - } - - else { /* SOURCE. No fanin for now; change if feedthroughs allowed. */ - if (total_edges_to_node[inode] != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_rr_graph: SOURCE node %d has a fanin of %d, expected 0.\n", - inode, total_edges_to_node[inode]); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - } - } - - free(num_edges_from_current_to_node); - free(total_edges_to_node); - free(switch_types_from_current_to_node); -} - -static boolean rr_node_is_global_clb_ipin(int inode) { - - /* Returns TRUE if inode refers to a global CLB input pin node. */ - - int ipin; - t_type_ptr type; - - type = grid[rr_node[inode].xlow][rr_node[inode].ylow].type; - - if (rr_node[inode].type != IPIN) - return (FALSE); - - ipin = rr_node[inode].ptc_num; - - return (type->is_global_pin[ipin]); -} - -void check_node(int inode, enum e_route_type route_type) { - - /* This routine checks that the rr_node is inside the grid and has a valid - * pin number, etc. - */ - - int xlow, ylow, xhigh, yhigh, ptc_num, capacity; - t_rr_type rr_type; - t_type_ptr type; - int nodes_per_chan, tracks_per_node, num_edges, cost_index; - float C, R; - - rr_type = rr_node[inode].type; - xlow = rr_node[inode].xlow; - xhigh = rr_node[inode].xhigh; - ylow = rr_node[inode].ylow; - yhigh = rr_node[inode].yhigh; - ptc_num = rr_node[inode].ptc_num; - capacity = rr_node[inode].capacity; - type = NULL; - - /* mrFPGA: Xifan TANG, check flag*/ - int check_flag; - - if (xlow > xhigh || ylow > yhigh) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: rr endpoints are (%d,%d) and (%d,%d).\n", - xlow, ylow, xhigh, yhigh); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - - if (xlow < 0 || xhigh > nx + 1 || ylow < 0 || yhigh > ny + 1) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: rr endpoints (%d,%d) and (%d,%d) are out of range.\n", - xlow, ylow, xhigh, yhigh); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - - if (ptc_num < 0) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) had a ptc_num of %d.\n", - inode, rr_type, ptc_num); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - - /* Check that the segment is within the array and such. */ - - switch (rr_type) { - - case SOURCE: - case SINK: - case IPIN: - case OPIN: - /* This is used later as well */ - type = grid[xlow][ylow].type; - - if (type == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", - inode, rr_type, xlow, ylow); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - if (xlow != xhigh || ylow != (yhigh - type->height + 1)) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d (type %d) has endpoints (%d,%d) and (%d,%d)\n", - inode, rr_type, xlow, ylow, xhigh, yhigh); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - break; - - case CHANX: - /* Original VPR */ - /* if (xlow < 1 || xhigh > nx || yhigh > ny || yhigh != ylow) { */ - /* end */ - /* mrFPGA : Xifan TANG */ - if (is_stack) { - check_flag = (xlow < 1 || xhigh > nx || yhigh > ny || ylow < 0 || xhigh != xlow); - } else { - check_flag = (xlow < 1 || xhigh > nx || yhigh > ny || yhigh != ylow); - } - if (check_flag) { - /* end */ - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: CHANX out of range for endpoints (%d,%d) and (%d,%d)\n", - xlow, ylow, xhigh, yhigh); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - if (route_type == GLOBAL && xlow != xhigh) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d spans multiple channel segments (not allowed for global routing).\n", - inode); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - break; - - case CHANY: - /* Original VPR */ - /*if (xhigh > nx || ylow < 1 || yhigh > ny || xlow != xhigh) { */ - /* end */ - /* mrFPGA : Xifan TANG */ - if (is_stack) { - check_flag = (xhigh > nx || xlow < 0 || ylow < 1 || yhigh > ny || yhigh != ylow); - } else { - check_flag = (xhigh > nx || ylow < 1 || yhigh > ny || xlow != xhigh); - } - if (check_flag) { - /* end */ - vpr_printf(TIO_MESSAGE_ERROR, "Error in check_node: CHANY out of range for endpoints (%d,%d) and (%d,%d)\n", - xlow, ylow, xhigh, yhigh); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - if (route_type == GLOBAL && ylow != yhigh) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d spans multiple channel segments (not allowed for global routing).\n", - inode); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: Unexpected segment type: %d\n", rr_type); - exit(1); - } - - /* Check that it's capacities and such make sense. */ - - switch (rr_type) { - - case SOURCE: - - if (ptc_num >= type->num_class - || type->class_inf[ptc_num].type != DRIVER) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) had a ptc_num of %d.\n", - inode, rr_type, ptc_num); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - if (type->class_inf[ptc_num].num_pins != capacity) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) had a capacity of %d.\n", - inode, rr_type, capacity); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - break; - - case SINK: - - if (ptc_num >= type->num_class - || type->class_inf[ptc_num].type != RECEIVER) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) had a ptc_num of %d.\n", - inode, rr_type, ptc_num); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - if (type->class_inf[ptc_num].num_pins != capacity) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a capacity of %d.\n", - inode, rr_type, capacity); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - break; - - case OPIN: - - if (ptc_num >= type->num_pins - || type->class_inf[type->pin_class[ptc_num]].type != DRIVER) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) had a ptc_num of %d.\n", - inode, rr_type, ptc_num); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - - if (capacity != 1) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a capacity of %d.\n", - inode, rr_type, capacity); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - break; - - case IPIN: - if (ptc_num >= type->num_pins - || type->class_inf[type->pin_class[ptc_num]].type != RECEIVER) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) had a ptc_num of %d.\n", - inode, rr_type, ptc_num); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - if (capacity != 1) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a capacity of %d.\n", - inode, rr_type, capacity); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - break; - - case CHANX: - if (route_type == DETAILED) { - nodes_per_chan = chan_width_x[ylow]; - tracks_per_node = 1; - } else { - nodes_per_chan = 1; - tracks_per_node = chan_width_x[ylow]; - } - - if (ptc_num >= nodes_per_chan) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a ptc_num of %d.\n", - inode, rr_type, ptc_num); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - - if (capacity != tracks_per_node) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a capacity of %d.\n", - inode, rr_type, capacity); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - break; - - case CHANY: - if (route_type == DETAILED) { - nodes_per_chan = chan_width_y[xlow]; - tracks_per_node = 1; - } else { - nodes_per_chan = 1; - tracks_per_node = chan_width_y[xlow]; - } - - if (ptc_num >= nodes_per_chan) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a ptc_num of %d.\n", - inode, rr_type, ptc_num); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - - if (capacity != tracks_per_node) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: inode %d (type %d) has a capacity of %d.\n", - inode, rr_type, capacity); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: Unexpected segment type: %d\n", rr_type); - exit(1); - - } - - /* Check that the number of (out) edges is reasonable. */ - num_edges = rr_node[inode].num_edges; - - if (rr_type != SINK && rr_type != IPIN) { - if (num_edges <= 0) { - /* Just a warning, since a very poorly routable rr-graph could have nodes with no edges. * - * If such a node was ever used in a final routing (not just in an rr_graph), other * - * error checks in check_routing will catch it. */ - vpr_printf(TIO_MESSAGE_WARNING, "in check_node: node %d has no edges.\n", inode); - print_rr_node_details(&rr_node[inode]); - } - } - - else if (rr_type == SINK) { /* SINK -- remove this check if feedthroughs allowed */ - if (num_edges != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d is a sink, but has %d edges.\n", - inode, num_edges); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - } - - /* Check that the capacitance, resistance and cost_index are reasonable. */ - - C = rr_node[inode].C; - R = rr_node[inode].R; - - if (rr_type == CHANX || rr_type == CHANY) { - if (C < 0. || R < 0.) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d of type %d has R = %g and C = %g.\n", - inode, rr_type, R, C); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - } - - else { - if (C != 0. || R != 0.) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d of type %d has R = %g and C = %g.\n", - inode, rr_type, R, C); - print_rr_node_details(&rr_node[inode]); - exit(1); - } - } - - cost_index = rr_node[inode].cost_index; - if (cost_index < 0 || cost_index >= num_rr_indexed_data) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_node: node %d cost index (%d) is out of range.\n", - inode, cost_index); - print_rr_node_details(&rr_node[inode]); - exit(1); - } -} - -static void check_pass_transistors(int from_node) { - - /* This routine checks that all pass transistors in the routing truly are * - * bidirectional. It may be a slow check, so don't use it all the time. */ - - int from_edge, to_node, to_edge, from_num_edges, to_num_edges; - t_rr_type from_rr_type, to_rr_type; - short from_switch_type; - boolean trans_matched; - - from_rr_type = rr_node[from_node].type; - if (from_rr_type != CHANX && from_rr_type != CHANY) - return; - - from_num_edges = rr_node[from_node].num_edges; - - for (from_edge = 0; from_edge < from_num_edges; from_edge++) { - to_node = rr_node[from_node].edges[from_edge]; - to_rr_type = rr_node[to_node].type; - - if (to_rr_type != CHANX && to_rr_type != CHANY) - continue; - - from_switch_type = rr_node[from_node].switches[from_edge]; - - if (switch_inf[from_switch_type].buffered) - continue; - /* Xifan TANG: Switch Segment Support - * Skip the unbuffer mux as well - */ - if ((FALSE == switch_inf[from_switch_type].buffered)&&(0 == strcmp("unbuf_mux",switch_inf[from_switch_type].type))) { - continue; - } - - - /* We know that we have a pass transitor from from_node to to_node. Now * - * check that there is a corresponding edge from to_node back to * - * from_node. */ - - to_num_edges = rr_node[to_node].num_edges; - trans_matched = FALSE; - - for (to_edge = 0; to_edge < to_num_edges; to_edge++) { - if (rr_node[to_node].edges[to_edge] == from_node - && rr_node[to_node].switches[to_edge] == from_switch_type) { - trans_matched = TRUE; - break; - } - } - - if (trans_matched == FALSE) { - vpr_printf(TIO_MESSAGE_ERROR, "in check_pass_transistors:\n"); - vpr_printf(TIO_MESSAGE_ERROR, "connection from node %d to node %d uses a pass transistor (switch type %d)\n", - from_node, to_node, from_switch_type); - vpr_printf(TIO_MESSAGE_ERROR, "but there is no corresponding pass transistor edge in the other direction.\n"); - print_rr_node_details(&rr_node[from_node]); - print_rr_node_details(&rr_node[to_node]); - exit(1); - } - - } /* End for all from_node edges */ -} diff --git a/vpr7_x2p/vpr/SRC/route/check_rr_graph.h b/vpr7_x2p/vpr/SRC/route/check_rr_graph.h deleted file mode 100755 index eb7a9e971..000000000 --- a/vpr7_x2p/vpr/SRC/route/check_rr_graph.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef CHECK_RR_GRAPH_H -#define CHECK_RR_GRAPH_H - -void check_rr_graph(INP const t_graph_type graph_type, - INP const int L_nx, INP const int L_ny, - INP const int num_switches, - int **Fc_in); - -void check_node(int inode, enum e_route_type route_type); - -#endif - diff --git a/vpr7_x2p/vpr/SRC/route/pb_pin_eq_auto_detect.c b/vpr7_x2p/vpr/SRC/route/pb_pin_eq_auto_detect.c deleted file mode 100644 index b82961704..000000000 --- a/vpr7_x2p/vpr/SRC/route/pb_pin_eq_auto_detect.c +++ /dev/null @@ -1,793 +0,0 @@ -/* Xifan TANG: Auto detect the pin equivalence of type_descriptor - * by re-construct the class of pins in type_descriptor - */ -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "physical_types.h" -#include "globals.h" -#include "vpr_utils.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "linkedlist.h" - -/* -typedef struct s_clb_to_clb_directs { - t_type_descriptor *from_clb_type; - int from_clb_pin_start_index; - int from_clb_pin_end_index; - t_type_descriptor *to_clb_type; - int to_clb_pin_start_index; - int to_clb_pin_end_index; -} t_clb_to_clb_directs; -*/ - -typedef struct s_num_mapped_opins_stats t_num_mapped_opins_stats; -struct s_num_mapped_opins_stats{ - int num_mapped_opins; - int net_cnt; -}; - - -/***** Subroutines *****/ - -boolean is_opin_in_direct_list(t_type_ptr cur_type_descriptor, - int opin_index, - int num_directs, - t_clb_to_clb_directs *clb_to_clb_directs) { - int idirect = 0; - - /* Corner case 1: no directs, return false */ - if (0 == num_directs) { - assert(NULL == clb_to_clb_directs); - return FALSE; - } - - for (idirect = 0; idirect < num_directs; idirect++) { - if ((cur_type_descriptor == clb_to_clb_directs[idirect].from_clb_type) - && ((clb_to_clb_directs[idirect].from_clb_pin_start_index < opin_index)||(clb_to_clb_directs[idirect].from_clb_pin_start_index == opin_index)) - && ((opin_index < clb_to_clb_directs[idirect].from_clb_pin_end_index)||(opin_index == clb_to_clb_directs[idirect].from_clb_pin_end_index))) { - return TRUE; - } - } - - return FALSE; -} - - -boolean is_des_rr_node_in_src_rr_node_edges(t_rr_node* src_rr_node, - t_rr_node* des_rr_node) { - int iedge; - boolean found = FALSE; - - for (iedge = 0; iedge < src_rr_node->num_edges; iedge++) { - if (des_rr_node == &(rr_node[src_rr_node->edges[iedge]])) { - found = TRUE; - break; - } - } - - return found; -} - -int alloc_and_add_fully_capacity_rr_edges_to_source_opin(t_type_ptr cur_type_descriptor, - int num_source_rr_node, - t_rr_node** source_rr_node, - t_rr_node** opin_rr_node) { - int ret = 0; - int isrc, iopin, offset; - - for (isrc = 0; isrc < num_source_rr_node; isrc++) { - source_rr_node[isrc]->capacity = 1; - source_rr_node[isrc]->num_edges = 0; - } - - /* We only do for two parts, first 0... num/2 and num/2 + 1 ... end */ - /* First part */ - for (iopin = 0; iopin < num_source_rr_node / 2; iopin++) { - offset = iopin; - /* Increase fan_in for opin_rr_node[iopin] */ - opin_rr_node[iopin]->fan_in = num_source_rr_node / 2 + 1; - /* Add rr_edges one by one */ - for (isrc = offset; isrc < offset + num_source_rr_node / 2 + 1; isrc++) { - /* Add rr_edges from source_rr_node[isrc] to opin_rr_node[iopin] */ - /* Make sure the to_node is not already in the child edges */ - if (TRUE == is_des_rr_node_in_src_rr_node_edges(source_rr_node[isrc], opin_rr_node[iopin])) { - continue; - } - /* Update fan_in for all the child rr_nodes */ - /* Increase num_edges for source_rr_node[isrc] */ - source_rr_node[isrc]->num_edges++; - source_rr_node[isrc]->edges = (int*)my_realloc(source_rr_node[isrc]->edges, source_rr_node[isrc]->num_edges * sizeof(int)); - source_rr_node[isrc]->switches = (short*)my_realloc(source_rr_node[isrc]->switches, source_rr_node[isrc]->num_edges * sizeof(short)); - source_rr_node[isrc]->edges[source_rr_node[isrc]->num_edges - 1] = opin_rr_node[iopin] - rr_node; - /* Add switches for src_rr_node */ - /* TODO: to be smarter */ - source_rr_node[isrc]->switches[source_rr_node[isrc]->num_edges - 1] = source_rr_node[isrc]->switches[0]; - /* Update capacity for src_rr_node */ - //source_rr_node[isrc]->capacity++; - /* Update counter */ - ret++; - } - } - - /* Second part */ - for (iopin = num_source_rr_node/2; iopin < num_source_rr_node; iopin++) { - offset = iopin - num_source_rr_node / 2; - /* Increase fan_in for opin_rr_node[iopin] */ - opin_rr_node[iopin]->fan_in = num_source_rr_node / 2 + 1; - /* Add rr_edges one by one */ - for (isrc = offset; isrc < offset + num_source_rr_node / 2 + 1; isrc++) { - /* Add rr_edges from source_rr_node[isrc] to opin_rr_node[iopin] */ - /* Make sure the to_node is not already in the child edges */ - if (TRUE == is_des_rr_node_in_src_rr_node_edges(source_rr_node[isrc], opin_rr_node[iopin])) { - continue; - } - /* Update fan_in for all the child rr_nodes */ - /* Increase num_edges for source_rr_node[isrc] */ - source_rr_node[isrc]->num_edges++; - source_rr_node[isrc]->edges = (int*)my_realloc(source_rr_node[isrc]->edges, source_rr_node[isrc]->num_edges * sizeof(int)); - source_rr_node[isrc]->switches = (short*)my_realloc(source_rr_node[isrc]->switches, source_rr_node[isrc]->num_edges * sizeof(short)); - source_rr_node[isrc]->edges[source_rr_node[isrc]->num_edges - 1] = opin_rr_node[iopin] - rr_node; - /* Add switches for src_rr_node */ - /* TODO: to be smarter */ - source_rr_node[isrc]->switches[source_rr_node[isrc]->num_edges - 1] = source_rr_node[isrc]->switches[0]; - /* Update capacity for src_rr_node */ - //source_rr_node[isrc]->capacity++; - /* Update counter */ - ret++; - } - } - - /* Print debug information */ - /* - vpr_printf(TIO_MESSAGE_INFO, "OPIN node:"); - for (iopin = 0; iopin < num_source_rr_node; iopin++) { - vpr_printf(TIO_MESSAGE_INFO, "%d,", opin_rr_node[iopin] - rr_node); - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - for (isrc = 0; isrc < num_source_rr_node; isrc++) { - vpr_printf(TIO_MESSAGE_INFO, "Source node: index=%d, num_edges=%d.\n", source_rr_node[isrc] - rr_node, source_rr_node[isrc]->num_edges); - vpr_printf(TIO_MESSAGE_INFO, "Edges:"); - for (iedge = 0; iedge < source_rr_node[isrc]->num_edges; iedge++) { - vpr_printf(TIO_MESSAGE_INFO, "%d,", source_rr_node[isrc]->edges[iedge]); - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - } - */ - - return ret; -} - -/* Build arrays for all the SOURCE rr_nodes, OPIN rr_nodes of a grid - * Also build arrays for all the OUT_PORT pb_graph_pins corresponding to SINK and OPIN - */ -int alloc_and_add_fully_capacity_rr_edges_to_one_grid(int grid_x, int grid_y, int grid_z, - t_block* cur_block, - t_ivec*** LL_rr_node_indices, - int num_directs, - t_clb_to_clb_directs *clb_to_clb_directs) { - int ret = 0; - int ipin, iclass, offset, inode; - t_type_ptr grid_type_descriptor = NULL; - t_pb_graph_node* top_pb_graph_node = NULL; - int num_opin_rr_nodes = 0; - int num_source_rr_nodes = 0; - t_rr_node** opin_rr_node = NULL; - t_rr_node** source_rr_node = NULL; - - /* Check */ - assert((!(0 > grid_x))&&(!(grid_x > (nx + 1)))); - assert((!(0 > grid_y))&&(!(grid_y > (ny + 1)))); - - /* Get grid type descriptor */ - grid_type_descriptor = grid[grid_x][grid_y].type; - top_pb_graph_node = grid[grid_x][grid_y].type->pb_graph_head; - - /* Check */ - assert(NULL != grid_type_descriptor); - assert(NULL != top_pb_graph_node); - - /* Search all the OPIN rr_nodes */ - for (ipin = 0; ipin < grid_type_descriptor->num_pins; ipin++) { - iclass = grid_type_descriptor->pin_class[ipin]; - /* Skip IPINs */ - if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { - continue; - } - /* Skip direct pins */ - if (TRUE == is_opin_in_direct_list(grid_type_descriptor, ipin, num_directs, clb_to_clb_directs)) { - continue; - } - /* Get SOURCE rr_nodes */ - inode = get_rr_node_index(grid_x, grid_y, OPIN, - ipin, LL_rr_node_indices); - /* Check */ - assert((-1 < inode)&&(inode < num_rr_nodes)); - /* Update counter */ - num_opin_rr_nodes++; - } - - for (iclass = 0; iclass < grid_type_descriptor->num_class; iclass++) { - /* Skip IPINs */ - if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { - continue; - } - /* Get SOURCE rr_node */ - inode = get_rr_node_index(grid_x, grid_y, SOURCE, - iclass, LL_rr_node_indices); - /* Check */ - assert((-1 < inode)&&(inode < num_rr_nodes)); - if (1 < rr_node[inode].num_edges) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])When output pin logic equivalence auto-detect is turned on.\nLogic equivalence of outputs should not be defined in arch. XML (type name: %s).\n", - __FILE__, __LINE__, grid_type_descriptor->name); - exit(1); - } - /* Skip direct pins */ - if (TRUE == is_opin_in_direct_list(grid_type_descriptor, rr_node[rr_node[inode].edges[0]].ptc_num, num_directs, clb_to_clb_directs)) { - continue; - } - /* Update counter */ - num_source_rr_nodes++; - } - - /* Check ? num_opin_rr_nodes == num_source_rr_nodes */ - if (num_opin_rr_nodes != num_source_rr_nodes) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])When output pin logic equivalence auto-detect is turned on.\nLogic equivalence of outputs should not be defined in arch. XML (type name: %s).\n", - __FILE__, __LINE__, grid_type_descriptor->name); - exit(1); - } - - /* Allocate */ - opin_rr_node = (t_rr_node**)my_malloc(num_opin_rr_nodes * sizeof(t_rr_node*)); - source_rr_node = (t_rr_node**)my_malloc(num_source_rr_nodes * sizeof(t_rr_node*)); - - /* Fill the array */ - offset = 0; - for (ipin = 0; ipin < grid_type_descriptor->num_pins; ipin++) { - iclass = grid_type_descriptor->pin_class[ipin]; - if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { - continue; - } - /* Skip direct pins */ - if (TRUE == is_opin_in_direct_list(grid_type_descriptor, ipin, num_directs, clb_to_clb_directs)) { - continue; - } - /* Get SOURCE rr_nodes */ - inode = get_rr_node_index(grid_x, grid_y, OPIN, - ipin, LL_rr_node_indices); - /* Check */ - assert((-1 < inode)&&(inode < num_rr_nodes)); - assert(1 == rr_node[inode].fan_in); - /* Fill opin_rr_node array */ - opin_rr_node[offset] = &(rr_node[inode]); - offset++; - } - assert(offset == num_opin_rr_nodes); - - /* Fill the array */ - offset = 0; - for (iclass = 0; iclass < grid_type_descriptor->num_class; iclass++) { - if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { - continue; - } - /* Get SOURCE rr_node */ - inode = get_rr_node_index(grid_x, grid_y, SOURCE, - iclass, LL_rr_node_indices); - /* Check */ - assert((-1 < inode)&&(inode < num_rr_nodes)); - if (1 < rr_node[inode].num_edges) { - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])When output pin logic equivalence auto-detect is turned on.\nLogic equivalence of outputs should not be defined in arch. XML (type name: %s).\n", - __FILE__, __LINE__, grid_type_descriptor->name); - exit(1); - } - /* Skip direct pins */ - if (TRUE == is_opin_in_direct_list(grid_type_descriptor, rr_node[rr_node[inode].edges[0]].ptc_num, num_directs, clb_to_clb_directs)) { - continue; - } - /* Fill opin_rr_node array */ - source_rr_node[offset] = &(rr_node[inode]); - offset++; - } - assert(offset == num_source_rr_nodes); - - /* Add full-capacity network between the two arrays */ - ret += alloc_and_add_fully_capacity_rr_edges_to_source_opin(grid_type_descriptor, num_source_rr_nodes, source_rr_node, opin_rr_node); - - /* Update num_pins in the class */ - for (inode = 0; inode < num_source_rr_nodes; inode++) { - iclass = source_rr_node[inode]->ptc_num; - if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { - continue; - } - /* Skip direct pins */ - if (TRUE == is_opin_in_direct_list(grid_type_descriptor, opin_rr_node[inode]->ptc_num, num_directs, clb_to_clb_directs)) { - continue; - } - grid_type_descriptor->class_inf[iclass].num_pins = source_rr_node[inode]->capacity; - } - - /* Free */ - if (NULL != opin_rr_node) { - free(opin_rr_node); - } - if (NULL != source_rr_node) { - free(source_rr_node); - } - - return ret; -} - -/* Find the corresponding pb_graph_pin in a CLB with a net_num */ - -/* Top-level function - * Add additional edges for all the SOURCE rr_nodes with a net num - */ -int alloc_and_add_grids_fully_capacity_rr_edges(t_ivec*** LL_rr_node_indices, - int num_directs, - t_clb_to_clb_directs *clb_to_clb_directs) { - int ix, iy, iz, iblk, used_blk_id; - t_block* mapped_block = NULL; - int ret = 0; - - /* Go by grid to grid */ - for (ix = 0; ix < (nx + 2); ix++) { - for (iy = 0; iy < (ny + 2); iy++) { - /* Skip EMPTY_TYPE */ - if (EMPTY_TYPE == grid[ix][iy].type) { - continue; - } - /* Skip IO_TYPE */ - if (IO_TYPE == grid[ix][iy].type) { - continue; - } - /* We only care core grids */ - /* If not specified, we do not modify anything */ - if (FALSE == grid[ix][iy].type->output_ports_eq_auto_detect) { - continue; - } - for (iz = 0; iz < grid[ix][iy].type->capacity; iz++) { - /* Try to identify if this z block is used or not */ - mapped_block = NULL; - for (iblk = 0; iblk < grid[ix][iy].usage; iblk++) { - used_blk_id = grid[ix][iy].blocks[iblk]; - if (iz == block[used_blk_id].z) { - mapped_block = &(block[used_blk_id]); - break; - } - } - /* Allocate the add edges to this source node */ - ret += alloc_and_add_fully_capacity_rr_edges_to_one_grid(ix, iy, iz, mapped_block, LL_rr_node_indices, num_directs, clb_to_clb_directs); - } - } - } - - return ret; -} - -/* Detect which OPINs are used and update routing cost */ -void auto_detect_and_reserve_used_opins(float pres_fac) { - return; -} - -/* Search the linked list first, - * 1. If we find a matched element, increase the counter - * 2. if we cannot find, allocate a new element and initialize the counter - */ -t_llist* search_and_add_num_mapped_opin_llist(t_llist* head, - int cand_num_mapped_opins) { - - t_llist* new_head = NULL; - t_llist* temp = NULL; - t_num_mapped_opins_stats* cur_stats = NULL; - boolean found = FALSE; - - /* Search the linked list, try to find a matched element */ - temp = head; - while (temp) { - assert(NULL != temp->dptr); - cur_stats = (t_num_mapped_opins_stats*)(temp->dptr); - /* Find what we want! */ - if (cand_num_mapped_opins == cur_stats->num_mapped_opins) { - found = TRUE; - /* update counter */ - cur_stats->net_cnt++; - } - /* go to next */ - temp = temp->next; - } - - /* decide the next step */ - if (TRUE == found) { - /* We do not allocate anything, return the old head */ - return head; - } - - /* Initialize the data */ - cur_stats = (t_num_mapped_opins_stats*)my_malloc(sizeof(t_num_mapped_opins_stats)); - cur_stats->num_mapped_opins = cand_num_mapped_opins; - cur_stats->net_cnt = 1; - - /* Reach here. We need to allocate a new node */ - if (NULL == head) { - /* Empty llist, create a new llist, containing 1 node */ - new_head = create_llist(1); - new_head->dptr = (void*)(cur_stats); - } else { - /* Creata a new node */ - insert_llist_node(head); - head->next->dptr = (void*)(cur_stats); - new_head = head; - } - - return new_head; -} - -/* Print the stats, and once we print one node, we remove and free it */ -void print_net_opin_llist(t_llist* head) { - t_llist* cur_head = head; - t_llist* temp = NULL; - t_llist* min_node = NULL; - t_num_mapped_opins_stats* cur_stats = NULL; - - vpr_printf(TIO_MESSAGE_INFO, "Stats for OPIN occupancy: (number of nets = %d)\n", num_nets); - - /* Loop until the llist is empty */ - while (1) { - temp = cur_head; - /* Initialize min_node */ - min_node = NULL; - cur_stats = NULL; - /* each time, we find the lowest num_mapped_opins and print the node*/ - while (temp) { - assert(NULL != temp->dptr); - cur_stats = (t_num_mapped_opins_stats*)(temp->dptr); - if ((NULL == min_node)||(((t_num_mapped_opins_stats*)(min_node->dptr))->num_mapped_opins > cur_stats->num_mapped_opins)) { - min_node = temp; - } - /* go to next */ - temp = temp->next; - } - /* No min_node, the llist is empty */ - if (NULL == min_node) { - break; - } - /* Print */ - cur_stats = (t_num_mapped_opins_stats*)(min_node->dptr); - vpr_printf(TIO_MESSAGE_INFO, "\t%d (%g%) Nets is mapped to %d OPINs.\n", - cur_stats->net_cnt, - (float)(100 * cur_stats->net_cnt / num_nets), - cur_stats->num_mapped_opins); - /* Remove the node we find */ - /* If this is the head */ - if (min_node == cur_head) { - cur_head = cur_head->next; - free(min_node->dptr); - free(min_node); - continue; - } - /* Otherwise, we need a traversal */ - temp = cur_head; - while (temp) { - if (min_node == temp->next) { - free(min_node->dptr); - remove_llist_node(temp); - break; - } - /* go to next */ - temp = temp->next; - } - } - - return; -} - -/* Reset all the net_num of rr_nodes and update them according to routing results */ -void reassign_rr_node_net_num_from_scratch() { - - /* This routine updates the occ field in the rr_node structure according to * - * the resource usage of the current routing. It does a brute force * - * recompute from scratch that is useful for sanity checking. */ - - int inode, inet; - struct s_trace *tptr; - - /* First set the occupancy of everything to zero. */ - - for (inode = 0; inode < num_rr_nodes; inode++) - rr_node[inode].net_num = OPEN; - - /* Now go through each net and count the tracks and pins used everywhere */ - - for (inet = 0; inet < num_nets; inet++) { - - if (clb_net[inet].is_global) /* Skip global nets. */ - continue; - - tptr = trace_head[inet]; - if (tptr == NULL) - continue; - - for (;;) { - inode = tptr->index; - rr_node[inode].net_num = inet; - - if (rr_node[inode].type == SINK) { - tptr = tptr->next; /* Skip next segment. */ - if (tptr == NULL) - break; - } - - tptr = tptr->next; - } - } - - return; -} - - -/* Xifan TANG: Statisitcs for each net which has occupied more than 1 OPIN */ -void print_net_opin_occupancy() { - int inode, inet; - t_llist* head = NULL; - - reassign_rr_node_net_num_from_scratch(); - - /* Initialize counters */ - for (inet = 0; inet < num_nets; inet++) { - clb_net[inet].num_mapped_opins = 0; - } - - /* Search each OPIN in the rr_graph */ - for (inode = 0; inode < num_rr_nodes; inode++) { - if (OPIN != rr_node[inode].type) { - continue; - } - /* Find the net_num */ - inet = rr_node[inode].net_num; - if (OPEN == inet) { - continue; - } - /* Update the counter in clb_net */ - assert((-1 < inet)&&(inet < num_nets)); - clb_net[inet].num_mapped_opins++; - } - - /* Print stats */ - for (inet = 0; inet < num_nets; inet++) { - /* Global nets is not routed, set to 0 */ - if (TRUE == clb_net[inet].is_global) { - clb_net[inet].num_mapped_opins = 0; - } - /* Search in the linked list if there exists an element witht the same num_mapped_opins */ - head = search_and_add_num_mapped_opin_llist(head, clb_net[inet].num_mapped_opins); - } - - /* Print */ - print_net_opin_llist(head); - - /* Free */ - - return; -} - - -/* Functions to add fully-capable routing network to a SB connections */ -/* Add edges to a CHANX|CHANY node, establishing connections to a OPIN node list */ -int add_opin_rr_edges_to_chan_rr_node(t_rr_node* chan_rr_node, - int num_opin_rr_nodes, - t_rr_node** opin_rr_node) { - int inode; - int ret = 0; - - /* Check */ - assert((CHANX == chan_rr_node->type)||(CHANY == chan_rr_node->type)); - for (inode = 0; inode < num_opin_rr_nodes; inode++) { - assert(OPIN == opin_rr_node[inode]->type); - } - - for (inode = 0; inode < num_opin_rr_nodes; inode++) { - /* 1. For each OPIN_rr_node, check if the chan_rr_node is already connected ! */ - if (TRUE == is_des_rr_node_in_src_rr_node_edges(opin_rr_node[inode], chan_rr_node)) { - continue; /* Bypass this opin_rr_node then */ - } - /* 2. Reach here implying a new edge is needed */ - /* Update fan-in */ - chan_rr_node->fan_in++; - /* Reallocate the edges */ - /* Increase num_edges for source_rr_node[isrc] */ - opin_rr_node[inode]->num_edges++; - opin_rr_node[inode]->edges = (int*)my_realloc(opin_rr_node[inode]->edges, opin_rr_node[inode]->num_edges * sizeof(int)); - opin_rr_node[inode]->switches = (short*)my_realloc(opin_rr_node[inode]->switches, opin_rr_node[inode]->num_edges * sizeof(short)); - opin_rr_node[inode]->edges[opin_rr_node[inode]->num_edges - 1] = chan_rr_node - rr_node; - /* Add switches for src_rr_node */ - /* TODO: to be smarter */ - opin_rr_node[inode]->switches[opin_rr_node[inode]->num_edges - 1] = opin_rr_node[inode]->switches[0]; - /* Update counter */ - ret++; - } - - return ret; -} - -/* For the OPINs in each block that turns on output_ports_eq_auto_detect - * 1. Gather OPIN rr_nodes - * 2. Find the CHANX or CHANY that is driven by OPINs - * 3. For each CHANX|CHANY, create a opin_rr_node list - * 4. Add rr_edges - */ -int alloc_and_add_fully_capacity_sb_rr_edges_to_one_grid(int grid_x, int grid_y, int grid_z, - t_block* cur_block, - t_ivec*** LL_rr_node_indices, - int num_directs, - t_clb_to_clb_directs *clb_to_clb_directs) { - int ret = 0; - int ipin, offset, from_node, to_node, inode, iedge, iclass; - t_type_ptr grid_type_descriptor = NULL; - t_pb_graph_node* top_pb_graph_node = NULL; - int num_opin_rr_nodes = 0; - int num_chan_rr_nodes = 0; - t_rr_node** opin_rr_node = NULL; - t_rr_node** chan_rr_node = NULL; - boolean is_in_list = FALSE; - - /* Check */ - assert((!(0 > grid_x))&&(!(grid_x > (nx + 1)))); - assert((!(0 > grid_y))&&(!(grid_y > (ny + 1)))); - - /* Get grid type descriptor */ - grid_type_descriptor = grid[grid_x][grid_y].type; - top_pb_graph_node = grid[grid_x][grid_y].type->pb_graph_head; - - /* Check */ - assert(NULL != grid_type_descriptor); - assert(NULL != top_pb_graph_node); - - /* 1. Gather OPIN rr_nodes */ - num_opin_rr_nodes = 0; - /* Search all the OPIN rr_nodes */ - for (ipin = 0; ipin < grid_type_descriptor->num_pins; ipin++) { - iclass = grid_type_descriptor->pin_class[ipin]; - /* Skip IPINs */ - if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { - continue; - } - /* Skip direct pins */ - if (TRUE == is_opin_in_direct_list(grid_type_descriptor, ipin, num_directs, clb_to_clb_directs)) { - continue; - } - /* Get SOURCE rr_nodes */ - inode = get_rr_node_index(grid_x, grid_y, OPIN, - ipin, LL_rr_node_indices); - /* Check */ - assert((-1 < inode)&&(inode < num_rr_nodes)); - /* Update counter */ - num_opin_rr_nodes++; - } - /* Allocate */ - opin_rr_node = (t_rr_node**)my_malloc(num_opin_rr_nodes * sizeof(t_rr_node*)); - - /* Fill the array */ - offset = 0; - for (ipin = 0; ipin < grid_type_descriptor->num_pins; ipin++) { - iclass = grid_type_descriptor->pin_class[ipin]; - /* Skip IPINs */ - if (DRIVER != grid_type_descriptor->class_inf[iclass].type) { - continue; - } - /* Skip direct pins */ - if (TRUE == is_opin_in_direct_list(grid_type_descriptor, ipin, num_directs, clb_to_clb_directs)) { - continue; - } - /* Get SOURCE rr_nodes */ - inode = get_rr_node_index(grid_x, grid_y, OPIN, - ipin, LL_rr_node_indices); - /* Check */ - assert((-1 < inode)&&(inode < num_rr_nodes)); - /* Update counter */ - /* Fill opin_rr_node array */ - opin_rr_node[offset] = &(rr_node[inode]); - offset++; - } - assert(offset == num_opin_rr_nodes); - - /* 2. Get chan_rr_nodes */ - /* Get the CHANX or CHANY that each OPIN rr_node is driving */ - for (from_node = 0; from_node < num_opin_rr_nodes; from_node++) { - /* Initialize chan_rr_node */ - num_chan_rr_nodes = 0; - chan_rr_node = NULL; - for (iedge = 0; iedge < opin_rr_node[from_node]->num_edges; iedge++) { - /* if CHANX or CHANY, increase the counter */ - to_node = opin_rr_node[from_node]->edges[iedge]; - if ((CHANX != rr_node[to_node].type) - &&(CHANY != rr_node[to_node].type)) { - continue; - } - /* Check */ - assert((CHANX == rr_node[to_node].type)||(CHANY == rr_node[to_node].type)); - /* Check if this node is already inside the list */ - is_in_list = FALSE; - for (inode = 0; inode < num_chan_rr_nodes; inode++) { - if (&(rr_node[to_node]) == chan_rr_node[inode]) { - is_in_list = TRUE; - break; - } - } - if (TRUE == is_in_list) { - continue; - } - /* Increase the counter and reallocate */ - num_chan_rr_nodes++; - /* Allocate */ - chan_rr_node = (t_rr_node**)my_realloc(chan_rr_node, num_chan_rr_nodes * sizeof(t_rr_node*)); - /* Update the array */ - chan_rr_node[num_chan_rr_nodes - 1] = &(rr_node[to_node]); - } - /* Add edges */ - /* generate offset */ - if (from_node < num_opin_rr_nodes / 2) { - offset = from_node; - } else { - offset = from_node - num_opin_rr_nodes / 2; - } - for (inode = 0; inode < num_chan_rr_nodes; inode++) { - ret += add_opin_rr_edges_to_chan_rr_node(chan_rr_node[inode], num_opin_rr_nodes / 2 + 1, opin_rr_node + offset); - } - /* Free */ - if (NULL != chan_rr_node) { - free(chan_rr_node); - } - } - - /* Free */ - if (NULL != opin_rr_node) { - free(opin_rr_node); - } - - return ret; -} - - -int alloc_and_add_grids_fully_capacity_sb_rr_edges(t_ivec*** LL_rr_node_indices, - int num_directs, - t_clb_to_clb_directs *clb_to_clb_directs) { - int ix, iy, iz, iblk, used_blk_id; - t_block* mapped_block = NULL; - int ret = 0; - - /* Go by grid to grid */ - for (ix = 0; ix < (nx + 2); ix++) { - for (iy = 0; iy < (ny + 2); iy++) { - /* Skip IO_TYPE */ - if (IO_TYPE == grid[ix][iy].type) { - continue; - } - /* We only care core grids */ - /* If not specified, we do not modify anything */ - if (FALSE == grid[ix][iy].type->output_ports_eq_auto_detect) { - continue; - } - for (iz = 0; iz < grid[ix][iy].type->capacity; iz++) { - /* Try to identify if this z block is used or not */ - mapped_block = NULL; - for (iblk = 0; iblk < grid[ix][iy].usage; iblk++) { - used_blk_id = grid[ix][iy].blocks[iblk]; - if (iz == block[used_blk_id].z) { - mapped_block = &(block[used_blk_id]); - break; - } - } - /* Allocate the add edges to this source node */ - ret += alloc_and_add_fully_capacity_sb_rr_edges_to_one_grid(ix, iy, iz, mapped_block, LL_rr_node_indices, num_directs, clb_to_clb_directs); - } - } - } - - return ret; -} - diff --git a/vpr7_x2p/vpr/SRC/route/pb_pin_eq_auto_detect.h b/vpr7_x2p/vpr/SRC/route/pb_pin_eq_auto_detect.h deleted file mode 100644 index 14656fbd5..000000000 --- a/vpr7_x2p/vpr/SRC/route/pb_pin_eq_auto_detect.h +++ /dev/null @@ -1,15 +0,0 @@ - -#ifndef PB_PIN_EQ_AUTO_DETECT_H -#define PB_PIN_EQ_AUTO_DETECT_H -int alloc_and_add_grids_fully_capacity_rr_edges(t_ivec*** LL_rr_node_indices, - int num_directs, - t_clb_to_clb_directs *clb_to_clb_directs); - -void print_net_opin_occupancy(); - -void auto_detect_and_reserve_used_opins(float pres_fac); - -int alloc_and_add_grids_fully_capacity_sb_rr_edges(t_ivec*** LL_rr_node_indices, - int num_directs, - t_clb_to_clb_directs *clb_to_clb_directs); -#endif diff --git a/vpr7_x2p/vpr/SRC/route/route_breadth_first.c b/vpr7_x2p/vpr/SRC/route/route_breadth_first.c deleted file mode 100755 index c4c750c0c..000000000 --- a/vpr7_x2p/vpr/SRC/route/route_breadth_first.c +++ /dev/null @@ -1,305 +0,0 @@ -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "route_export.h" -#include "route_common.h" -#include "route_breadth_first.h" - -/********************* Subroutines local to this module *********************/ - -static boolean breadth_first_route_net(int inet, float bend_cost); - -static void breadth_first_expand_trace_segment(struct s_trace *start_ptr, - int remaining_connections_to_sink); - -static void breadth_first_expand_neighbours(int inode, float pcost, int inet, - float bend_cost); - -static void breadth_first_add_source_to_heap(int inet); - -/************************ Subroutine definitions ****************************/ - -boolean try_breadth_first_route(struct s_router_opts router_opts, - t_ivec ** clb_opins_used_locally, int width_fac) { - - /* Iterated maze router ala Pathfinder Negotiated Congestion algorithm, * - * (FPGA 95 p. 111). Returns TRUE if it can route this FPGA, FALSE if * - * it can't. */ - - float pres_fac; - boolean success, is_routable, rip_up_local_opins; - int itry, inet; - - /* Usually the first iteration uses a very small (or 0) pres_fac to find * - * the shortest path and get a congestion map. For fast compiles, I set * - * pres_fac high even for the first iteration. */ - - pres_fac = router_opts.first_iter_pres_fac; - - for (itry = 1; itry <= router_opts.max_router_iterations; itry++) { - - for (inet = 0; inet < num_nets; inet++) { - if (clb_net[inet].is_global == FALSE) { /* Skip global nets. */ - - pathfinder_update_one_cost(trace_head[inet], -1, pres_fac); - - is_routable = breadth_first_route_net(inet, - router_opts.bend_cost); - - /* Impossible to route? (disconnected rr_graph) */ - - if (!is_routable) { - vpr_printf(TIO_MESSAGE_INFO, "Routing failed.\n"); - return (FALSE); - } - - pathfinder_update_one_cost(trace_head[inet], 1, pres_fac); - - } - } - - /* Make sure any CLB OPINs used up by subblocks being hooked directly * - * to them are reserved for that purpose. */ - - if (itry == 1) - rip_up_local_opins = FALSE; - else - rip_up_local_opins = TRUE; - - reserve_locally_used_opins(pres_fac, rip_up_local_opins, - clb_opins_used_locally); - - success = feasible_routing(); - if (success) { - vpr_printf(TIO_MESSAGE_INFO, "Successfully routed after %d routing iterations.\n", itry); - return (TRUE); - } - - if (itry == 1) - pres_fac = router_opts.initial_pres_fac; - else - pres_fac *= router_opts.pres_fac_mult; - - pres_fac = std::min(pres_fac, static_cast(HUGE_POSITIVE_FLOAT / 1e5)); - - pathfinder_update_cost(pres_fac, router_opts.acc_fac); - } - - vpr_printf(TIO_MESSAGE_INFO, "Routing failed.\n"); - return (FALSE); -} - -static boolean breadth_first_route_net(int inet, float bend_cost) { - - /* Uses a maze routing (Dijkstra's) algorithm to route a net. The net * - * begins at the net output, and expands outward until it hits a target * - * pin. The algorithm is then restarted with the entire first wire segment * - * included as part of the source this time. For an n-pin net, the maze * - * router is invoked n-1 times to complete all the connections. Inet is * - * the index of the net to be routed. Bends are penalized by bend_cost * - * (which is typically zero for detailed routing and nonzero only for global * - * routing), since global routes with lots of bends are tougher to detailed * - * route (using a detailed router like SEGA). * - * If this routine finds that a net *cannot* be connected (due to a complete * - * lack of potential paths, rather than congestion), it returns FALSE, as * - * routing is impossible on this architecture. Otherwise it returns TRUE. */ - - int i, inode, prev_node, remaining_connections_to_sink; - float pcost, new_pcost; - struct s_heap *current; - struct s_trace *tptr; - - free_traceback(inet); - breadth_first_add_source_to_heap(inet); - mark_ends(inet); - - tptr = NULL; - remaining_connections_to_sink = 0; - - for (i = 1; i <= clb_net[inet].num_sinks; i++) { /* Need n-1 wires to connect n pins */ - breadth_first_expand_trace_segment(tptr, remaining_connections_to_sink); - current = get_heap_head(); - - if (current == NULL) { /* Infeasible routing. No possible path for net. */ - vpr_printf (TIO_MESSAGE_INFO, "Cannot route net #%d (%s) to sink #%d -- no possible path.\n", - inet, clb_net[inet].name, i); - reset_path_costs(); /* Clean up before leaving. */ - return (FALSE); - } - - inode = current->index; - - while (rr_node_route_inf[inode].target_flag == 0) { - pcost = rr_node_route_inf[inode].path_cost; - new_pcost = current->cost; - if (pcost > new_pcost) { /* New path is lowest cost. */ - rr_node_route_inf[inode].path_cost = new_pcost; - prev_node = current->u.prev_node; - rr_node_route_inf[inode].prev_node = prev_node; - rr_node_route_inf[inode].prev_edge = current->prev_edge; - - if (pcost > 0.99 * HUGE_POSITIVE_FLOAT) /* First time touched. */ - add_to_mod_list(&rr_node_route_inf[inode].path_cost); - - breadth_first_expand_neighbours(inode, new_pcost, inet, - bend_cost); - } - - free_heap_data(current); - current = get_heap_head(); - - if (current == NULL) { /* Impossible routing. No path for net. */ - vpr_printf (TIO_MESSAGE_INFO, "Cannot route net #%d (%s) to sink #%d -- no possible path.\n", - inet, clb_net[inet].name, i); - reset_path_costs(); - return (FALSE); - } - - inode = current->index; - } - - rr_node_route_inf[inode].target_flag--; /* Connected to this SINK. */ - remaining_connections_to_sink = rr_node_route_inf[inode].target_flag; - tptr = update_traceback(current, inet); - free_heap_data(current); - } - - empty_heap(); - reset_path_costs(); - return (TRUE); -} - -static void breadth_first_expand_trace_segment(struct s_trace *start_ptr, - int remaining_connections_to_sink) { - - /* Adds all the rr_nodes in the traceback segment starting at tptr (and * - * continuing to the end of the traceback) to the heap with a cost of zero. * - * This allows expansion to begin from the existing wiring. The * - * remaining_connections_to_sink value is 0 if the route segment ending * - * at this location is the last one to connect to the SINK ending the route * - * segment. This is the usual case. If it is not the last connection this * - * net must make to this SINK, I have a hack to ensure the next connection * - * to this SINK goes through a different IPIN. Without this hack, the * - * router would always put all the connections from this net to this SINK * - * through the same IPIN. With LUTs or cluster-based logic blocks, you * - * should never have a net connecting to two logically-equivalent pins on * - * the same logic block, so the hack will never execute. If your logic * - * block is an and-gate, however, nets might connect to two and-inputs on * - * the same logic block, and since the and-inputs are logically-equivalent, * - * this means two connections to the same SINK. */ - - struct s_trace *tptr, *next_ptr; - int inode, sink_node, last_ipin_node; - - tptr = start_ptr; - if(tptr != NULL && rr_node[tptr->index].type == SINK) { - /* During logical equivalence case, only use one opin */ - tptr = tptr->next; - } - - if (remaining_connections_to_sink == 0) { /* Usual case. */ - while (tptr != NULL) { - node_to_heap(tptr->index, 0., NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); - tptr = tptr->next; - } - } - - else { /* This case never executes for most logic blocks. */ - - /* Weird case. Lots of hacks. The cleanest way to do this would be to empty * - * the heap, update the congestion due to the partially-completed route, put * - * the whole route so far (excluding IPINs and SINKs) on the heap with cost * - * 0., and expand till you hit the next SINK. That would be slow, so I * - * do some hacks to enable incremental wavefront expansion instead. */ - - if (tptr == NULL) - return; /* No route yet */ - - next_ptr = tptr->next; - last_ipin_node = OPEN; /* Stops compiler from complaining. */ - - /* Can't put last SINK on heap with NO_PREVIOUS, etc, since that won't let * - * us reach it again. Instead, leave the last traceback element (SINK) off * - * the heap. */ - - while (next_ptr != NULL) { - inode = tptr->index; - node_to_heap(inode, 0., NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); - - if (rr_node[inode].type == IPIN) - last_ipin_node = inode; - - tptr = next_ptr; - next_ptr = tptr->next; - } - - /* This will stop the IPIN node used to get to this SINK from being * - * reexpanded for the remainder of this net's routing. This will make us * - * hook up more IPINs to this SINK (which is what we want). If IPIN * - * doglegs are allowed in the graph, we won't be able to use this IPIN to * - * do a dogleg, since it won't be re-expanded. Shouldn't be a big problem. */ - - rr_node_route_inf[last_ipin_node].path_cost = -HUGE_POSITIVE_FLOAT; - - /* Also need to mark the SINK as having high cost, so another connection can * - * be made to it. */ - - sink_node = tptr->index; - rr_node_route_inf[sink_node].path_cost = HUGE_POSITIVE_FLOAT; - - /* Finally, I need to remove any pending connections to this SINK via the * - * IPIN I just used (since they would result in congestion). Scan through * - * the heap to do this. */ - - invalidate_heap_entries(sink_node, last_ipin_node); - } -} - -static void breadth_first_expand_neighbours(int inode, float pcost, int inet, - float bend_cost) { - - /* Puts all the rr_nodes adjacent to inode on the heap. rr_nodes outside * - * the expanded bounding box specified in route_bb are not added to the * - * heap. pcost is the path_cost to get to inode. */ - - int iconn, to_node, num_edges; - t_rr_type from_type, to_type; - float tot_cost; - - num_edges = rr_node[inode].num_edges; - for (iconn = 0; iconn < num_edges; iconn++) { - to_node = rr_node[inode].edges[iconn]; - - if (rr_node[to_node].xhigh < route_bb[inet].xmin - || rr_node[to_node].xlow > route_bb[inet].xmax - || rr_node[to_node].yhigh < route_bb[inet].ymin - || rr_node[to_node].ylow > route_bb[inet].ymax) - continue; /* Node is outside (expanded) bounding box. */ - - tot_cost = pcost + get_rr_cong_cost(to_node); - - if (bend_cost != 0.) { - from_type = rr_node[inode].type; - to_type = rr_node[to_node].type; - if ((from_type == CHANX && to_type == CHANY) - || (from_type == CHANY && to_type == CHANX)) - tot_cost += bend_cost; - } - - node_to_heap(to_node, tot_cost, inode, iconn, OPEN, OPEN); - } -} - -static void breadth_first_add_source_to_heap(int inet) { - - /* Adds the SOURCE of this net to the heap. Used to start a net's routing. */ - - int inode; - float cost; - - inode = net_rr_terminals[inet][0]; /* SOURCE */ - cost = get_rr_cong_cost(inode); - - node_to_heap(inode, cost, NO_PREVIOUS, NO_PREVIOUS, OPEN, OPEN); -} diff --git a/vpr7_x2p/vpr/SRC/route/route_breadth_first.h b/vpr7_x2p/vpr/SRC/route/route_breadth_first.h deleted file mode 100755 index b69219962..000000000 --- a/vpr7_x2p/vpr/SRC/route/route_breadth_first.h +++ /dev/null @@ -1,2 +0,0 @@ -boolean try_breadth_first_route(struct s_router_opts router_opts, - t_ivec ** clb_opins_used_locally, int width_fac); diff --git a/vpr7_x2p/vpr/SRC/route/route_common.c b/vpr7_x2p/vpr/SRC/route/route_common.c deleted file mode 100755 index 83b7c8070..000000000 --- a/vpr7_x2p/vpr/SRC/route/route_common.c +++ /dev/null @@ -1,1493 +0,0 @@ -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "vpr_utils.h" -#include "globals.h" -#include "route_export.h" -#include "route_common.h" -#include "route_tree_timing.h" -#include "route_timing.h" -#include "route_breadth_first.h" -#include "place_and_route.h" -#include "rr_graph.h" -#include "read_xml_arch_file.h" -#include "ReadOptions.h" -/* mrFPGA */ -#include "mrfpga_globals.h" -#include "buffer_insertion.h" -/* end */ - -#include "rr_graph_builder_utils.h" - -/* Xifan TANG: useful functions for pb_pin_eq_auto_detect */ -void reassign_rr_node_net_num_from_scratch(); - -/***************** Variables shared only by route modules *******************/ - -t_rr_node_route_inf *rr_node_route_inf = NULL; /* [0..num_rr_nodes-1] */ - -struct s_bb *route_bb = NULL; /* [0..num_nets-1]. Limits area in which each */ - -/* net must be routed. */ - -/**************** Static variables local to route_common.c ******************/ - -static struct s_heap **heap; /* Indexed from [1..heap_size] */ -static int heap_size; /* Number of slots in the heap array */ -static int heap_tail; /* Index of first unused slot in the heap array */ - -/* For managing my own list of currently free heap data structures. */ -static struct s_heap *heap_free_head = NULL; -/* For keeping track of the sudo malloc memory for the heap*/ -static t_chunk heap_ch = {NULL, 0, NULL}; - -/* For managing my own list of currently free trace data structures. */ -static struct s_trace *trace_free_head = NULL; -/* For keeping track of the sudo malloc memory for the trace*/ -static t_chunk trace_ch = {NULL, 0, NULL}; - -#ifdef DEBUG -static int num_trace_allocated = 0; /* To watch for memory leaks. */ -static int num_heap_allocated = 0; -static int num_linked_f_pointer_allocated = 0; -#endif - -static struct s_linked_f_pointer *rr_modified_head = NULL; -static struct s_linked_f_pointer *linked_f_pointer_free_head = NULL; - -static t_chunk linked_f_pointer_ch = {NULL, 0, NULL}; - -/* The numbering relation between the channels and clbs is: * - * * - * | IO | chan_ | CLB | chan_ | CLB | * - * |grid[0][2] | y[0][2] |grid[1][2] | y[1][2] | grid[2][2]| * - * +-----------+ +-----------+ +-----------+ * - * } capacity in * - * No channel chan_x[1][1] chan_x[2][1] } chan_width * - * } _x[1] * - * +-----------+ +-----------+ +-----------+ * - * | | chan_ | | chan_ | | * - * | IO | y[0][1] | CLB | y[1][1] | CLB | * - * |grid[0][1] | |grid[1][1] | |grid[2][1] | * - * | | | | | | * - * +-----------+ +-----------+ +-----------+ * - * } capacity in * - * chan_x[1][0] chan_x[2][0] } chan_width * - * } _x[0] * - * +-----------+ +-----------+ * - * No | | No | | * - * Channel | IO | Channel | IO | * - * |grid[1][0] | |grid[2][0] | * - * | | | | * - * +-----------+ +-----------+ * - * * - * {=======} {=======} * - * Capacity in Capacity in * - * chan_width_y[0] chan_width_y[1] * - * */ - -/******************** Subroutines local to route_common.c *******************/ - -static void free_trace_data(struct s_trace *tptr); -static void load_route_bb(int bb_factor); - -static struct s_trace *alloc_trace_data(void); -static void add_to_heap(struct s_heap *hptr); -static struct s_heap *alloc_heap_data(void); -static struct s_linked_f_pointer *alloc_linked_f_pointer(void); - -static t_ivec **alloc_and_load_clb_opins_used_locally(void); -static void adjust_one_rr_occ_and_pcost(int inode, int add_or_sub, - float pres_fac); - -/************************** Subroutine definitions ***************************/ - -void save_routing(struct s_trace **best_routing, - t_ivec ** clb_opins_used_locally, - t_ivec ** saved_clb_opins_used_locally) { - - /* This routing frees any routing currently held in best routing, * - * then copies over the current routing (held in trace_head), and * - * finally sets trace_head and trace_tail to all NULLs so that the * - * connection to the saved routing is broken. This is necessary so * - * that the next iteration of the router does not free the saved * - * routing elements. Also saves any data about locally used clb_opins, * - * since this is also part of the routing. */ - - int inet, iblk, iclass, ipin, num_local_opins; - struct s_trace *tptr, *tempptr; - t_type_ptr type; - - for (inet = 0; inet < num_nets; inet++) { - - /* Free any previously saved routing. It is no longer best. */ - tptr = best_routing[inet]; - while (tptr != NULL) { - tempptr = tptr->next; - free_trace_data(tptr); - tptr = tempptr; - } - - /* Save a pointer to the current routing in best_routing. */ - best_routing[inet] = trace_head[inet]; - - /* Set the current (working) routing to NULL so the current trace * - * elements won't be reused by the memory allocator. */ - - trace_head[inet] = NULL; - trace_tail[inet] = NULL; - } - - /* Save which OPINs are locally used. */ - - for (iblk = 0; iblk < num_blocks; iblk++) { - type = block[iblk].type; - /* Xifan TANG: Bypass those with pin_equivalence auto-detect */ - if (TRUE == type->output_ports_eq_auto_detect) { - continue; - } - /* Xifan TANG: By pass IO */ - if (IO_TYPE == type) { - continue; - } - for (iclass = 0; iclass < type->num_class; iclass++) { - num_local_opins = clb_opins_used_locally[iblk][iclass].nelem; - /* clb_opins_used_locally may be changed. - * Reallocate saved_clb_opins_used_locally if needed - */ - if (0 == num_local_opins) { - if (NULL != saved_clb_opins_used_locally[iblk][iclass].list) { - free(saved_clb_opins_used_locally[iblk][iclass].list); - } - saved_clb_opins_used_locally[iblk][iclass].list = NULL; - } else { - saved_clb_opins_used_locally[iblk][iclass].list = (int*)my_realloc(saved_clb_opins_used_locally[iblk][iclass].list, - clb_opins_used_locally[iblk][iclass].nelem * sizeof(int)); - } - /* Fill the list of saved_clb_opins_used_locally */ - for (ipin = 0; ipin < num_local_opins; ipin++) { - saved_clb_opins_used_locally[iblk][iclass].list[ipin] = - clb_opins_used_locally[iblk][iclass].list[ipin]; - } - } - } -} - -void restore_routing(struct s_trace **best_routing, - t_ivec ** clb_opins_used_locally, - t_ivec ** saved_clb_opins_used_locally) { - - /* Deallocates any current routing in trace_head, and replaces it with * - * the routing in best_routing. Best_routing is set to NULL to show that * - * it no longer points to a valid routing. NOTE: trace_tail is not * - * restored -- it is set to all NULLs since it is only used in * - * update_traceback. If you need trace_tail restored, modify this * - * routine. Also restores the locally used opin data. */ - - int inet, iblk, ipin, iclass, num_local_opins; - t_type_ptr type; - - /* mrFPGA : Xifan TANG*/ - if (is_mrFPGA && is_wire_buffer) { - load_best_buffer_list(); - } - /* end */ - - for (inet = 0; inet < num_nets; inet++) { - - /* Free any current routing. */ - free_traceback(inet); - - /* Set the current routing to the saved one. */ - trace_head[inet] = best_routing[inet]; - best_routing[inet] = NULL; /* No stored routing. */ - } - - /* Save which OPINs are locally used. */ - - for (iblk = 0; iblk < num_blocks; iblk++) { - type = block[iblk].type; - for (iclass = 0; iclass < type->num_class; iclass++) { - num_local_opins = clb_opins_used_locally[iblk][iclass].nelem; - for (ipin = 0; ipin < num_local_opins; ipin++) { - clb_opins_used_locally[iblk][iclass].list[ipin] = - saved_clb_opins_used_locally[iblk][iclass].list[ipin]; - } - } - - } -} - -void get_serial_num(void) { - - /* This routine finds a "magic cookie" for the routing and prints it. * - * Use this number as a routing serial number to ensure that programming * - * changes do not break the router. */ - - int inet, serial_num, inode; - struct s_trace *tptr; - - serial_num = 0; - - for (inet = 0; inet < num_nets; inet++) { - - /* Global nets will have null trace_heads (never routed) so they * - * are not included in the serial number calculation. */ - - tptr = trace_head[inet]; - while (tptr != NULL) { - inode = tptr->index; - serial_num += (inet + 1) - * (rr_node[inode].xlow * (nx + 1) - rr_node[inode].yhigh); - - serial_num -= rr_node[inode].ptc_num * (inet + 1) * 10; - - serial_num -= rr_node[inode].type * (inet + 1) * 100; - serial_num %= 2000000000; /* Prevent overflow */ - tptr = tptr->next; - } - } - vpr_printf(TIO_MESSAGE_INFO, "Serial number (magic cookie) for the routing is: %d\n", serial_num); -} - -boolean try_route(int width_fac, struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, float **net_delay, t_slack * slacks, - t_chan_width_dist chan_width_dist, t_ivec ** clb_opins_used_locally, - boolean * Fc_clipped, t_direct_inf *directs, int num_directs, - /*Xifan TANG: Switch Segment Pattern Support*/ - t_swseg_pattern_inf* swseg_patterns) { - - /* Attempts a routing via an iterated maze router algorithm. Width_fac * - * specifies the relative width of the channels, while the members of * - * router_opts determine the value of the costs assigned to routing * - * resource node, etc. det_routing_arch describes the detailed routing * - * architecture (connection and switch boxes) of the FPGA; it is used * - * only if a DETAILED routing has been selected. */ - - int tmp; - clock_t begin, end; - boolean success; - t_graph_type graph_type; - - if (router_opts.route_type == GLOBAL) { - graph_type = GRAPH_GLOBAL; - /* Xifan Tang: tileable undirectional rr_graph support */ - } else if (BI_DIRECTIONAL == det_routing_arch.directionality) { - graph_type = GRAPH_BIDIR; - } else if (UNI_DIRECTIONAL == det_routing_arch.directionality) { - if (true == det_routing_arch.tileable) { - graph_type = GRAPH_UNIDIR_TILEABLE; - } else { - graph_type = GRAPH_UNIDIR; - } - } - - /* Set the channel widths */ - - init_chan(width_fac, chan_width_dist); - - /* Free any old routing graph, if one exists. */ - - free_rr_graph(); - - begin = clock(); - - /* Set up the routing resource graph defined by this FPGA architecture. */ - - build_rr_graph(graph_type, num_types, type_descriptors, nx, ny, grid, - chan_width_x[0], NULL, - det_routing_arch.switch_block_type, det_routing_arch.Fs, - det_routing_arch.switch_block_sub_type, det_routing_arch.sub_Fs, - det_routing_arch.wire_opposite_side, - det_routing_arch.num_segment, - det_routing_arch.num_switch, segment_inf, - det_routing_arch.global_route_switch, - det_routing_arch.delayless_switch, timing_inf, - det_routing_arch.wire_to_ipin_switch, router_opts.base_cost_type, - directs, num_directs, FALSE, - &tmp, - // Xifan TANG: Add Switch Segment Pattern Support - det_routing_arch.num_swseg_pattern, swseg_patterns, FALSE, TRUE); - - end = clock(); -#ifdef CLOCKS_PER_SEC - vpr_printf(TIO_MESSAGE_INFO, "Build rr_graph took %g seconds.\n", (float)(end - begin) / CLOCKS_PER_SEC); -#else - vpr_printf(TIO_MESSAGE_INFO, "Build rr_graph took %g seconds.\n", (float)(end - begin) / CLK_PER_SEC); -#endif - - /* Allocate and load some additional rr_graph information needed only by * - * the router. */ - - alloc_and_load_rr_node_route_structs(); - - init_route_structs(router_opts.bb_factor); - - if (router_opts.router_algorithm == BREADTH_FIRST) { - vpr_printf(TIO_MESSAGE_INFO, "Confirming Router Algorithm: BREADTH_FIRST.\n"); - success = try_breadth_first_route(router_opts, clb_opins_used_locally, - width_fac); - } else { /* TIMING_DRIVEN route */ - vpr_printf(TIO_MESSAGE_INFO, "Confirming Router Algorithm: TIMING_DRIVEN.\n"); - assert(router_opts.route_type != GLOBAL); - success = try_timing_driven_route(router_opts, net_delay, slacks, - clb_opins_used_locally,timing_inf.timing_analysis_enabled); - } - - free_rr_node_route_structs(); - - return (success); -} - -boolean feasible_routing(void) { - - /* This routine checks to see if this is a resource-feasible routing. * - * That is, are all rr_node capacity limitations respected? It assumes * - * that the occupancy arrays are up to date when it is called. */ - - int inode; - - for (inode = 0; inode < num_rr_nodes; inode++) { - if (rr_node[inode].occ > rr_node[inode].capacity) { - /* - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]rr_node[%d] occupancy(%d) exceeds its capacity(%d)!\n", - __FILE__, __LINE__, inode, rr_node[inode].occ, rr_node[inode].capacity); - */ - return (FALSE); - } - } - - return (TRUE); -} - -void pathfinder_update_one_cost(struct s_trace *route_segment_start, - int add_or_sub, float pres_fac) { - - /* This routine updates the occupancy and pres_cost of the rr_nodes that are * - * affected by the portion of the routing of one net that starts at * - * route_segment_start. If route_segment_start is trace_head[inet], the * - * cost of all the nodes in the routing of net inet are updated. If * - * add_or_sub is -1 the net (or net portion) is ripped up, if it is 1 the * - * net is added to the routing. The size of pres_fac determines how severly * - * oversubscribed rr_nodes are penalized. */ - - struct s_trace *tptr; - int inode, occ, capacity; - - tptr = route_segment_start; - if (tptr == NULL) /* No routing yet. */ - return; - - for (;;) { - inode = tptr->index; - - occ = rr_node[inode].occ + add_or_sub; - capacity = rr_node[inode].capacity; - - rr_node[inode].occ = occ; - - /* pres_cost is Pn in the Pathfinder paper. I set my pres_cost according to * - * the overuse that would result from having ONE MORE net use this routing * - * node. */ - - if (occ < capacity) { - rr_node_route_inf[inode].pres_cost = 1.; - } else { - rr_node_route_inf[inode].pres_cost = 1. - + (occ + 1 - capacity) * pres_fac; - } - - if (rr_node[inode].type == SINK) { - tptr = tptr->next; /* Skip next segment. */ - if (tptr == NULL) - break; - } - - tptr = tptr->next; - - } /* End while loop -- did an entire traceback. */ -} - -void pathfinder_update_cost(float pres_fac, float acc_fac) { - - /* This routine recomputes the pres_cost and acc_cost of each routing * - * resource for the pathfinder algorithm after all nets have been routed. * - * It updates the accumulated cost to by adding in the number of extra * - * signals sharing a resource right now (i.e. after each complete iteration) * - * times acc_fac. It also updates pres_cost, since pres_fac may have * - * changed. THIS ROUTINE ASSUMES THE OCCUPANCY VALUES IN RR_NODE ARE UP TO * - * DATE. */ - - int inode, occ, capacity; - - for (inode = 0; inode < num_rr_nodes; inode++) { - occ = rr_node[inode].occ; - capacity = rr_node[inode].capacity; - - if (occ > capacity) { - rr_node_route_inf[inode].acc_cost += (occ - capacity) * acc_fac; - rr_node_route_inf[inode].pres_cost = 1. - + (occ + 1 - capacity) * pres_fac; - } - - /* If occ == capacity, we don't need to increase acc_cost, but a change * - * in pres_fac could have made it necessary to recompute the cost anyway. */ - - else if (occ == capacity) { - rr_node_route_inf[inode].pres_cost = 1. + pres_fac; - } - } -} - -void init_route_structs(int bb_factor) { - - /* Call this before you route any nets. It frees any old traceback and * - * sets the list of rr_nodes touched to empty. */ - - int i; - - for (i = 0; i < num_nets; i++) - free_traceback(i); - - load_route_bb(bb_factor); - - /* Check that things that should have been emptied after the last routing * - * really were. */ - - if (rr_modified_head != NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "in init_route_structs. List of modified rr nodes is not empty.\n"); - exit(1); - } - - if (heap_tail != 1) { - vpr_printf(TIO_MESSAGE_ERROR, "in init_route_structs. Heap is not empty.\n"); - exit(1); - } -} - -struct s_trace * -update_traceback(struct s_heap *hptr, int inet) { - - /* This routine adds the most recently finished wire segment to the * - * traceback linked list. The first connection starts with the net SOURCE * - * and begins at the structure pointed to by trace_head[inet]. Each * - * connection ends with a SINK. After each SINK, the next connection * - * begins (if the net has more than 2 pins). The first element after the * - * SINK gives the routing node on a previous piece of the routing, which is * - * the link from the existing net to this new piece of the net. * - * In each traceback I start at the end of a path and trace back through * - * its predecessors to the beginning. I have stored information on the * - * predecesser of each node to make traceback easy -- this sacrificies some * - * memory for easier code maintenance. This routine returns a pointer to * - * the first "new" node in the traceback (node not previously in trace). */ - - struct s_trace *tptr, *prevptr, *temptail, *ret_ptr; - int inode; - short iedge; - -#ifdef DEBUG - t_rr_type rr_type; -#endif - - inode = hptr->index; - -#ifdef DEBUG - rr_type = rr_node[inode].type; - if (rr_type != SINK) { - vpr_printf(TIO_MESSAGE_ERROR, "in update_traceback. Expected type = SINK (%d).\n", SINK); - vpr_printf(TIO_MESSAGE_ERROR, "\tGot type = %d while tracing back net %d.\n", rr_type, inet); - exit(1); - } -#endif - - tptr = alloc_trace_data(); /* SINK on the end of the connection */ - tptr->index = inode; - tptr->iswitch = OPEN; - tptr->next = NULL; - temptail = tptr; /* This will become the new tail at the end */ - /* of the routine. */ - - /* Now do it's predecessor. */ - - inode = hptr->u.prev_node; - iedge = hptr->prev_edge; - - while (inode != NO_PREVIOUS) { - prevptr = alloc_trace_data(); - prevptr->index = inode; - prevptr->iswitch = rr_node[inode].switches[iedge]; - prevptr->next = tptr; - tptr = prevptr; - - iedge = rr_node_route_inf[inode].prev_edge; - inode = rr_node_route_inf[inode].prev_node; - } - - if (trace_tail[inet] != NULL) { - trace_tail[inet]->next = tptr; /* Traceback ends with tptr */ - ret_ptr = tptr->next; /* First new segment. */ - } else { /* This was the first "chunk" of the net's routing */ - trace_head[inet] = tptr; - ret_ptr = tptr; /* Whole traceback is new. */ - } - - trace_tail[inet] = temptail; - return (ret_ptr); -} - -void reset_path_costs(void) { - - /* The routine sets the path_cost to HUGE_POSITIVE_FLOAT for all channel segments * - * touched by previous routing phases. */ - - struct s_linked_f_pointer *mod_ptr; - -#ifdef DEBUG - int num_mod_ptrs; -#endif - - /* The traversal method below is slightly painful to make it faster. */ - - if (rr_modified_head != NULL) { - mod_ptr = rr_modified_head; - -#ifdef DEBUG - num_mod_ptrs = 1; -#endif - - while (mod_ptr->next != NULL) { - *(mod_ptr->fptr) = HUGE_POSITIVE_FLOAT; - mod_ptr = mod_ptr->next; -#ifdef DEBUG - num_mod_ptrs++; -#endif - } - *(mod_ptr->fptr) = HUGE_POSITIVE_FLOAT; /* Do last one. */ - - /* Reset the modified list and put all the elements back in the free * - * list. */ - - mod_ptr->next = linked_f_pointer_free_head; - linked_f_pointer_free_head = rr_modified_head; - rr_modified_head = NULL; - -#ifdef DEBUG - num_linked_f_pointer_allocated -= num_mod_ptrs; -#endif - } -} - -float get_rr_cong_cost(int inode) { - - /* Returns the *congestion* cost of using this rr_node. */ - - short cost_index; - float cost; - - cost_index = rr_node[inode].cost_index; - cost = rr_indexed_data[cost_index].base_cost - * rr_node_route_inf[inode].acc_cost - * rr_node_route_inf[inode].pres_cost; - return (cost); -} - -void mark_ends(int inet) { - - /* Mark all the SINKs of this net as targets by setting their target flags * - * to the number of times the net must connect to each SINK. Note that * - * this number can occassionally be greater than 1 -- think of connecting * - * the same net to two inputs of an and-gate (and-gate inputs are logically * - * equivalent, so both will connect to the same SINK). */ - - int ipin, inode; - - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { - inode = net_rr_terminals[inet][ipin]; - rr_node_route_inf[inode].target_flag++; - } -} - -void node_to_heap(int inode, float cost, int prev_node, int prev_edge, - float backward_path_cost, float R_upstream) { - - /* Puts an rr_node on the heap, if the new cost given is lower than the * - * current path_cost to this channel segment. The index of its predecessor * - * is stored to make traceback easy. The index of the edge used to get * - * from its predecessor to it is also stored to make timing analysis, etc. * - * easy. The backward_path_cost and R_upstream values are used only by the * - * timing-driven router -- the breadth-first router ignores them. */ - - struct s_heap *hptr; - - if (cost >= rr_node_route_inf[inode].path_cost) - return; - - hptr = alloc_heap_data(); - hptr->index = inode; - hptr->cost = cost; - hptr->u.prev_node = prev_node; - hptr->prev_edge = prev_edge; - hptr->backward_path_cost = backward_path_cost; - hptr->R_upstream = R_upstream; - add_to_heap(hptr); -} - -void free_traceback(int inet) { - - /* Puts the entire traceback (old routing) for this net on the free list * - * and sets the trace_head pointers etc. for the net to NULL. */ - - struct s_trace *tptr, *tempptr; - - if(trace_head == NULL) { - return; - } - - tptr = trace_head[inet]; - - while (tptr != NULL) { - tempptr = tptr->next; - free_trace_data(tptr); - tptr = tempptr; - } - - trace_head[inet] = NULL; - trace_tail[inet] = NULL; -} - -t_ivec ** -alloc_route_structs(void) { - - /* Allocates the data structures needed for routing. */ - - t_ivec **clb_opins_used_locally; - - alloc_route_static_structs(); - clb_opins_used_locally = alloc_and_load_clb_opins_used_locally(); - - return (clb_opins_used_locally); -} - -void alloc_route_static_structs(void) { - trace_head = (struct s_trace **) my_calloc(num_nets, - sizeof(struct s_trace *)); - trace_tail = (struct s_trace **) my_malloc( - num_nets * sizeof(struct s_trace *)); - - heap_size = nx * ny; - heap = (struct s_heap **) my_malloc(heap_size * sizeof(struct s_heap *)); - heap--; /* heap stores from [1..heap_size] */ - heap_tail = 1; - - route_bb = (struct s_bb *) my_malloc(num_nets * sizeof(struct s_bb)); -} - -struct s_trace ** -alloc_saved_routing(t_ivec ** clb_opins_used_locally, - t_ivec *** saved_clb_opins_used_locally_ptr) { - - /* Allocates data structures into which the key routing data can be saved, * - * allowing the routing to be recovered later (e.g. after a another routing * - * is attempted). */ - - struct s_trace **best_routing; - t_ivec **saved_clb_opins_used_locally; - int iblk, iclass, num_local_opins; - t_type_ptr type; - - best_routing = (struct s_trace **) my_calloc(num_nets, - sizeof(struct s_trace *)); - - saved_clb_opins_used_locally = (t_ivec **) my_malloc( - num_blocks * sizeof(t_ivec *)); - - for (iblk = 0; iblk < num_blocks; iblk++) { - type = block[iblk].type; - saved_clb_opins_used_locally[iblk] = (t_ivec *) my_malloc( - type->num_class * sizeof(t_ivec)); - for (iclass = 0; iclass < type->num_class; iclass++) { - num_local_opins = clb_opins_used_locally[iblk][iclass].nelem; - saved_clb_opins_used_locally[iblk][iclass].nelem = num_local_opins; - - if (num_local_opins == 0) { - saved_clb_opins_used_locally[iblk][iclass].list = NULL; - } else { - saved_clb_opins_used_locally[iblk][iclass].list = - (int *) my_malloc(num_local_opins * sizeof(int)); - } - } - } - - *saved_clb_opins_used_locally_ptr = saved_clb_opins_used_locally; - return (best_routing); -} - -/* TODO: super hacky, jluu comment, I need to rethink this whole function, without it, logically equivalent output pins incorrectly use more pins than needed. I force that CLB output pin uses at most one output pin */ -static t_ivec ** -alloc_and_load_clb_opins_used_locally(void) { - - /* Allocates and loads the data needed to make the router reserve some CLB * - * output pins for connections made locally within a CLB (if the netlist * - * specifies that this is necessary). */ - - t_ivec **clb_opins_used_locally; - int iblk, clb_pin, iclass, num_local_opins; - int class_low, class_high; - t_type_ptr type; - - clb_opins_used_locally = (t_ivec **) my_malloc( - num_blocks * sizeof(t_ivec *)); - - for (iblk = 0; iblk < num_blocks; iblk++) { - type = block[iblk].type; - get_class_range_for_block(iblk, &class_low, &class_high); - clb_opins_used_locally[iblk] = (t_ivec *) my_malloc( - type->num_class * sizeof(t_ivec)); - for (iclass = 0; iclass < type->num_class; iclass++) - clb_opins_used_locally[iblk][iclass].nelem = 0; - - for (clb_pin = 0; clb_pin < type->num_pins; clb_pin++) { - // another hack to avoid I/Os, whole function needs a rethink - if(type == IO_TYPE) { - continue; - } - /* Comment by Xifan TANG: count the number of unused clb OPINs ? Those pins may be used locally... - * It seems that jluu wants to force all these pins are used, even though there is no net mapped! - * Then router will not route with these unused clb_pins!!! - */ - if ((block[iblk].nets[clb_pin] != OPEN - && clb_net[block[iblk].nets[clb_pin]].num_sinks == 0) || block[iblk].nets[clb_pin] == OPEN - ) { - iclass = type->pin_class[clb_pin]; - if(type->class_inf[iclass].type == DRIVER) { - /* Check to make sure class is in same range as that assigned to block */ - assert(iclass >= class_low && iclass <= class_high); - clb_opins_used_locally[iblk][iclass].nelem++; - } - } - } - - for (iclass = 0; iclass < type->num_class; iclass++) { - num_local_opins = clb_opins_used_locally[iblk][iclass].nelem; - - if (num_local_opins == 0) - clb_opins_used_locally[iblk][iclass].list = NULL; - else - clb_opins_used_locally[iblk][iclass].list = (int *) my_malloc( - num_local_opins * sizeof(int)); - } - } - - return (clb_opins_used_locally); -} - -void free_trace_structs(void) { - /*the trace lists are only freed after use by the timing-driven placer */ - /*Do not free them after use by the router, since stats, and draw */ - /*routines use the trace values */ - int i; - - for (i = 0; i < num_nets; i++) - free_traceback(i); - - if(trace_head) { - free(trace_head); - free(trace_tail); - } - trace_head = NULL; - trace_tail = NULL; -} - -void free_route_structs() { - - /* Frees the temporary storage needed only during the routing. The * - * final routing result is not freed. */ - if(heap != NULL) { - free(heap + 1); - } - if(route_bb != NULL) { - free(route_bb); - } - - heap = NULL; /* Defensive coding: crash hard if I use these. */ - route_bb = NULL; - - /*free the memory chunks that were used by heap and linked f pointer */ - free_chunk_memory(&heap_ch); - free_chunk_memory(&linked_f_pointer_ch); - heap_free_head = NULL; - linked_f_pointer_free_head = NULL; -} - -void free_saved_routing(struct s_trace **best_routing, - t_ivec ** saved_clb_opins_used_locally) { - - /* Frees the data structures needed to save a routing. */ - int i; - - free(best_routing); - for (i = 0; i < num_blocks; i++) { - free_ivec_vector(saved_clb_opins_used_locally[i], 0, - block[i].type->num_class - 1); - } - free(saved_clb_opins_used_locally); -} - -void alloc_and_load_rr_node_route_structs(void) { - - /* Allocates some extra information about each rr_node that is used only * - * during routing. */ - - int inode; - - if (rr_node_route_inf != NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_rr_node_route_structs: old rr_node_route_inf array exists.\n"); - exit(1); - } - - rr_node_route_inf = (t_rr_node_route_inf *) my_malloc(num_rr_nodes * sizeof(t_rr_node_route_inf)); - - for (inode = 0; inode < num_rr_nodes; inode++) { - rr_node_route_inf[inode].prev_node = NO_PREVIOUS; - rr_node_route_inf[inode].prev_edge = NO_PREVIOUS; - rr_node_route_inf[inode].pres_cost = 1.; - rr_node_route_inf[inode].acc_cost = 1.; - rr_node_route_inf[inode].path_cost = HUGE_POSITIVE_FLOAT; - rr_node_route_inf[inode].target_flag = 0; - } -} - -void reset_rr_node_route_structs(void) { - - /* Allocates some extra information about each rr_node that is used only * - * during routing. */ - - int inode; - - assert(rr_node_route_inf != NULL); - - for (inode = 0; inode < num_rr_nodes; inode++) { - rr_node_route_inf[inode].prev_node = NO_PREVIOUS; - rr_node_route_inf[inode].prev_edge = NO_PREVIOUS; - rr_node_route_inf[inode].pres_cost = 1.; - rr_node_route_inf[inode].acc_cost = 1.; - rr_node_route_inf[inode].path_cost = HUGE_POSITIVE_FLOAT; - rr_node_route_inf[inode].target_flag = 0; - } -} - -void free_rr_node_route_structs(void) { - - /* Frees the extra information about each rr_node that is needed only * - * during routing. */ - - free(rr_node_route_inf); - rr_node_route_inf = NULL; /* Mark as free */ -} - -/* RESEARCH TODO: Bounding box heuristic needs to be redone for heterogeneous blocks */ -static void load_route_bb(int bb_factor) { - - /* This routine loads the bounding box arrays used to limit the space * - * searched by the maze router when routing each net. The search is * - * limited to channels contained with the net bounding box expanded * - * by bb_factor channels on each side. For example, if bb_factor is * - * 0, the maze router must route each net within its bounding box. * - * If bb_factor = nx, the maze router will search every channel in * - * the FPGA if necessary. The bounding boxes returned by this routine * - * are different from the ones used by the placer in that they are * - * clipped to lie within (0,0) and (nx+1,ny+1) rather than (1,1) and * - * (nx,ny). */ - - int k, xmax, ymax, xmin, ymin, x, y, inet; - - for (inet = 0; inet < num_nets; inet++) { - x = block[clb_net[inet].node_block[0]].x; - y = - block[clb_net[inet].node_block[0]].y - + block[clb_net[inet].node_block[0]].type->pin_height[clb_net[inet].node_block_pin[0]]; - - xmin = x; - ymin = y; - xmax = x; - ymax = y; - - for (k = 1; k <= clb_net[inet].num_sinks; k++) { - x = block[clb_net[inet].node_block[k]].x; - y = - block[clb_net[inet].node_block[k]].y - + block[clb_net[inet].node_block[k]].type->pin_height[clb_net[inet].node_block_pin[k]]; - - if (x < xmin) { - xmin = x; - } else if (x > xmax) { - xmax = x; - } - - if (y < ymin) { - ymin = y; - } else if (y > ymax) { - ymax = y; - } - } - - /* Want the channels on all 4 sides to be usuable, even if bb_factor = 0. */ - - xmin -= 1; - ymin -= 1; - - /* Expand the net bounding box by bb_factor, then clip to the physical * - * chip area. */ - - route_bb[inet].xmin = std::max(xmin - bb_factor, 0); - route_bb[inet].xmax = std::min(xmax + bb_factor, nx + 1); - route_bb[inet].ymin = std::max(ymin - bb_factor, 0); - route_bb[inet].ymax = std::min(ymax + bb_factor, ny + 1); - } -} - -void add_to_mod_list(float *fptr) { - - /* This routine adds the floating point pointer (fptr) into a * - * linked list that indicates all the pathcosts that have been * - * modified thus far. */ - - struct s_linked_f_pointer *mod_ptr; - - mod_ptr = alloc_linked_f_pointer(); - - /* Add this element to the start of the modified list. */ - - mod_ptr->next = rr_modified_head; - mod_ptr->fptr = fptr; - rr_modified_head = mod_ptr; -} - -static void add_to_heap(struct s_heap *hptr) { - - /* Adds an item to the heap, expanding the heap if necessary. */ - - int ito, ifrom; - struct s_heap *temp_ptr; - - if (heap_tail > heap_size) { /* Heap is full */ - heap_size *= 2; - heap = (struct s_heap **) my_realloc((void *) (heap + 1), - heap_size * sizeof(struct s_heap *)); - heap--; /* heap goes from [1..heap_size] */ - } - - heap[heap_tail] = hptr; - ifrom = heap_tail; - ito = ifrom / 2; - heap_tail++; - - while ((ito >= 1) && (heap[ifrom]->cost < heap[ito]->cost)) { - temp_ptr = heap[ito]; - heap[ito] = heap[ifrom]; - heap[ifrom] = temp_ptr; - ifrom = ito; - ito = ifrom / 2; - } -} - -/*WMF: peeking accessor :) */ -boolean is_empty_heap(void) { - return (boolean)(heap_tail == 1); -} - -struct s_heap * -get_heap_head(void) { - - /* Returns a pointer to the smallest element on the heap, or NULL if the * - * heap is empty. Invalid (index == OPEN) entries on the heap are never * - * returned -- they are just skipped over. */ - - int ito, ifrom; - struct s_heap *heap_head, *temp_ptr; - - do { - if (heap_tail == 1) { /* Empty heap. */ - vpr_printf(TIO_MESSAGE_WARNING, "Empty heap occurred in get_heap_head.\n"); - vpr_printf(TIO_MESSAGE_WARNING, "Some blocks are impossible to connect in this architecture.\n"); - return (NULL); - } - - heap_head = heap[1]; /* Smallest element. */ - - /* Now fix up the heap */ - - heap_tail--; - heap[1] = heap[heap_tail]; - ifrom = 1; - ito = 2 * ifrom; - - while (ito < heap_tail) { - if (heap[ito + 1]->cost < heap[ito]->cost) - ito++; - if (heap[ito]->cost > heap[ifrom]->cost) - break; - temp_ptr = heap[ito]; - heap[ito] = heap[ifrom]; - heap[ifrom] = temp_ptr; - ifrom = ito; - ito = 2 * ifrom; - } - - } while (heap_head->index == OPEN); /* Get another one if invalid entry. */ - - return (heap_head); -} - -void empty_heap(void) { - - int i; - - for (i = 1; i < heap_tail; i++) - free_heap_data(heap[i]); - - heap_tail = 1; -} - -static struct s_heap * -alloc_heap_data(void) { - - struct s_heap *temp_ptr; - - if (heap_free_head == NULL) { /* No elements on the free list */ - heap_free_head = (struct s_heap *) my_chunk_malloc(sizeof(struct s_heap),&heap_ch); - heap_free_head->u.next = NULL; - } - - temp_ptr = heap_free_head; - heap_free_head = heap_free_head->u.next; -#ifdef DEBUG - num_heap_allocated++; -#endif - return (temp_ptr); -} - -void free_heap_data(struct s_heap *hptr) { - - hptr->u.next = heap_free_head; - heap_free_head = hptr; -#ifdef DEBUG - num_heap_allocated--; -#endif -} - -void invalidate_heap_entries(int sink_node, int ipin_node) { - - /* Marks all the heap entries consisting of sink_node, where it was reached * - * via ipin_node, as invalid (OPEN). Used only by the breadth_first router * - * and even then only in rare circumstances. */ - - int i; - - for (i = 1; i < heap_tail; i++) { - if (heap[i]->index == sink_node && heap[i]->u.prev_node == ipin_node) - heap[i]->index = OPEN; /* Invalid. */ - } -} - -static struct s_trace * -alloc_trace_data(void) { - - struct s_trace *temp_ptr; - - if (trace_free_head == NULL) { /* No elements on the free list */ - trace_free_head = (struct s_trace *) my_chunk_malloc(sizeof(struct s_trace),&trace_ch); - trace_free_head->next = NULL; - } - temp_ptr = trace_free_head; - trace_free_head = trace_free_head->next; -#ifdef DEBUG - num_trace_allocated++; -#endif - return (temp_ptr); -} - -static void free_trace_data(struct s_trace *tptr) { - - /* Puts the traceback structure pointed to by tptr on the free list. */ - - tptr->next = trace_free_head; - trace_free_head = tptr; -#ifdef DEBUG - num_trace_allocated--; -#endif -} - -static struct s_linked_f_pointer * -alloc_linked_f_pointer(void) { - - /* This routine returns a linked list element with a float pointer as * - * the node data. */ - - /*int i;*/ - struct s_linked_f_pointer *temp_ptr; - - if (linked_f_pointer_free_head == NULL) { - /* No elements on the free list */ - linked_f_pointer_free_head = (struct s_linked_f_pointer *) my_chunk_malloc(sizeof(struct s_linked_f_pointer),&linked_f_pointer_ch); - linked_f_pointer_free_head->next = NULL; - } - - temp_ptr = linked_f_pointer_free_head; - linked_f_pointer_free_head = linked_f_pointer_free_head->next; - -#ifdef DEBUG - num_linked_f_pointer_allocated++; -#endif - - return (temp_ptr); -} - -void print_route(char *route_file) { - - /* Prints out the routing to file route_file. */ - - int inet, inode, ipin, bnum, ilow, jlow, node_block_pin, iclass; - t_rr_type rr_type; - struct s_trace *tptr; - const char *name_type[] = { "SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY", - "INTRA_CLUSTER_EDGE" }; - FILE *fp; - - fp = fopen(route_file, "w"); - - fprintf(fp, "Array size: %d x %d logic blocks.\n", nx, ny); - fprintf(fp, "\nRouting:"); - for (inet = 0; inet < num_nets; inet++) { - if (clb_net[inet].is_global == FALSE) { - if (clb_net[inet].num_sinks == FALSE) { - fprintf(fp, "\n\nNet %d (%s)\n\n", inet, clb_net[inet].name); - fprintf(fp, "\n\nUsed in local cluster only, reserved one CLB pin\n\n"); - } else { - fprintf(fp, "\n\nNet %d (%s)\n\n", inet, clb_net[inet].name); - tptr = trace_head[inet]; - - while (tptr != NULL) { - inode = tptr->index; - rr_type = rr_node[inode].type; - ilow = rr_node[inode].xlow; - jlow = rr_node[inode].ylow; - - fprintf(fp, "Node:\t%d\t%6s (%d,%d) ", inode, name_type[rr_type], ilow, jlow); - - if ((ilow != rr_node[inode].xhigh) - || (jlow != rr_node[inode].yhigh)) - fprintf(fp, "to (%d,%d) ", rr_node[inode].xhigh, - rr_node[inode].yhigh); - - switch (rr_type) { - - case IPIN: - case OPIN: - if (grid[ilow][jlow].type == IO_TYPE) { - fprintf(fp, " Pad: "); - } else { /* IO Pad. */ - fprintf(fp, " Pin: "); - } - break; - - case CHANX: - case CHANY: - fprintf(fp, " Track: "); - break; - - case SOURCE: - case SINK: - if (grid[ilow][jlow].type == IO_TYPE) { - fprintf(fp, " Pad: "); - } else { /* IO Pad. */ - fprintf(fp, " Class: "); - } - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in print_route: Unexpected traceback element type: %d (%s).\n", - rr_type, name_type[rr_type]); - exit(1); - break; - } - - /* A kind of dirty fix for tileable routing, - * the track_ids is allocated by tileable routing. - * If the vector is not empty, it means tileable routing is enabled - * we need another function to get the track_id rather than ptc_num - */ - if (0 == rr_node[inode].track_ids.size()) { - fprintf(fp, "%d ", rr_node[inode].ptc_num); - } else { - /* Xifan Tang: for routing tracks, get the actual track ids */ - DeviceCoordinator cur_coord(ilow, jlow); - fprintf(fp, "%d ", get_rr_node_actual_track_id(&(rr_node[inode]), cur_coord)); - } - - /* Uncomment line below if you're debugging and want to see the switch types * - * used in the routing. */ - /* fprintf (fp, "Switch: %d", tptr->iswitch); */ - - fprintf(fp, "\n"); - - tptr = tptr->next; - } - } - } - - else { /* Global net. Never routed. */ - fprintf(fp, "\n\nNet %d (%s): global net connecting:\n\n", inet, - clb_net[inet].name); - - for (ipin = 0; ipin <= clb_net[inet].num_sinks; ipin++) { - bnum = clb_net[inet].node_block[ipin]; - - node_block_pin = clb_net[inet].node_block_pin[ipin]; - iclass = block[bnum].type->pin_class[node_block_pin]; - - fprintf(fp, "Block %s (#%d) at (%d, %d), Pin class %d.\n", - block[bnum].name, bnum, block[bnum].x, block[bnum].y, - iclass); - } - } - } - - fclose(fp); - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_MEM)) { - fp = my_fopen(getEchoFileName(E_ECHO_MEM), "w", 0); - fprintf(fp, "\nNum_heap_allocated: %d Num_trace_allocated: %d\n", - num_heap_allocated, num_trace_allocated); - fprintf(fp, "Num_linked_f_pointer_allocated: %d\n", - num_linked_f_pointer_allocated); - fclose(fp); - } - -} - -/* TODO: check if this is still necessary for speed */ -void reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins, - t_ivec ** clb_opins_used_locally) { - - /* In the past, this function implicitly allowed LUT duplication when there are free LUTs. - This was especially important for logical equivalence; however, now that we have a very general - logic cluster, it does not make sense to allow LUT duplication implicitly. we'll need to look into how we want to handle this case - - */ - - int iblk, num_local_opin, inode, from_node, iconn, num_edges, to_node; - int iclass, ipin; - float cost; - struct s_heap *heap_head_ptr; - t_type_ptr type; - - if (rip_up_local_opins) { - for (iblk = 0; iblk < num_blocks; iblk++) { - type = block[iblk].type; - for (iclass = 0; iclass < type->num_class; iclass++) { - num_local_opin = clb_opins_used_locally[iblk][iclass].nelem; - /* Always 0 for pads and for RECEIVER (IPIN) classes */ - for (ipin = 0; ipin < num_local_opin; ipin++) { - inode = clb_opins_used_locally[iblk][iclass].list[ipin]; - adjust_one_rr_occ_and_pcost(inode, -1, pres_fac); - } - } - } - } - - for (iblk = 0; iblk < num_blocks; iblk++) { - type = block[iblk].type; - /* By pass type_descriptors that turns on pin equivalence auto_detect */ - //if (TRUE == type->output_ports_eq_auto_detect) { - // continue; - //} - for (iclass = 0; iclass < type->num_class; iclass++) { - num_local_opin = clb_opins_used_locally[iblk][iclass].nelem; - /* Always 0 for pads and for RECEIVER (IPIN) classes */ - - if (num_local_opin != 0) { /* Have to reserve (use) some OPINs */ - from_node = rr_blk_source[iblk][iclass]; - num_edges = rr_node[from_node].num_edges; - for (iconn = 0; iconn < num_edges; iconn++) { - to_node = rr_node[from_node].edges[iconn]; - /* Xifan TANG: the to_node may not be the one should be reserved - * Need double check if the ptc_num of this node matches class_id - */ - //if (type->pin_class[rr_node[to_node].ptc_num] != iclass) { - // continue; - //} - /* Original VPR */ - cost = get_rr_cong_cost(to_node); - /* Push nodes to heap: - * Xifan TANG: - * Need to check we do not push a node twice into the heap! - */ - node_to_heap(to_node, cost, OPEN, OPEN, 0., 0.); - } - - for (ipin = 0; ipin < num_local_opin; ipin++) { - heap_head_ptr = get_heap_head(); - inode = heap_head_ptr->index; - /* Xifan TANG: we only modify occ for single driver OPIN ! */ - //if (1 == rr_node[inode].fan_in) { - adjust_one_rr_occ_and_pcost(inode, 1, pres_fac); - //} - clb_opins_used_locally[iblk][iclass].list[ipin] = inode; - free_heap_data(heap_head_ptr); - } - - empty_heap(); - } - } - } -} - -/* Xifan TANG: new function to auto detect and reserved locally used opins */ -void auto_detect_and_reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins, - t_ivec ** clb_opins_used_locally) { - - /* In the past, this function implicitly allowed LUT duplication when there are free LUTs. - This was especially important for logical equivalence; however, now that we have a very general - logic cluster, it does not make sense to allow LUT duplication implicitly. we'll need to look into how we want to handle this case - */ - - int iblk, num_local_opin, inode, from_node, iconn, num_edges, to_node; - int iclass, ipin; - float cost; - struct s_heap *heap_head_ptr; - t_type_ptr type; - - /* Xifan TANG: Update net_num for all the rr_nodes */ - reassign_rr_node_net_num_from_scratch(); - - /* VPR original method */ - if (rip_up_local_opins) { - for (iblk = 0; iblk < num_blocks; iblk++) { - type = block[iblk].type; - /* Bypass those with pin_equivalence auto-detect */ - if (TRUE == type->output_ports_eq_auto_detect) { - continue; - } - /* By pass IO */ - if (IO_TYPE == type) { - continue; - } - for (iclass = 0; iclass < type->num_class; iclass++) { - num_local_opin = clb_opins_used_locally[iblk][iclass].nelem; - /* Always 0 for pads and for RECEIVER (IPIN) classes */ - for (ipin = 0; ipin < num_local_opin; ipin++) { - inode = clb_opins_used_locally[iblk][iclass].list[ipin]; - adjust_one_rr_occ_and_pcost(inode, -1, pres_fac); - } - } - } - } - - for (iblk = 0; iblk < num_blocks; iblk++) { - type = block[iblk].type; - /* Bypass those with pin_equivalence auto-detect */ - if (TRUE == type->output_ports_eq_auto_detect) { - continue; - } - /* By pass IO */ - if (IO_TYPE == type) { - continue; - } - for (iclass = 0; iclass < type->num_class; iclass++) { - /* Bypass non driver class */ - if (DRIVER != type->class_inf[iclass].type) { - continue; - } - - /* Always 0 for pads and for RECEIVER (IPIN) classes */ - num_local_opin = clb_opins_used_locally[iblk][iclass].nelem; - /* Have to reserve (use) some OPINs */ - ipin = 0; - /* We push nodes into heap and then we can pop-up with a sort by cost */ - from_node = rr_blk_source[iblk][iclass]; - num_edges = rr_node[from_node].num_edges; - /* initialize rr_node element: is_in_heap */ - for (iconn = 0; iconn < num_edges; iconn++) { - to_node = rr_node[from_node].edges[iconn]; - rr_node[to_node].is_in_heap = FALSE; - } - /* Find unmapped pins and add to heap */ - for (iconn = 0; iconn < num_edges; iconn++) { - to_node = rr_node[from_node].edges[iconn]; - if (OPEN != rr_node[to_node].net_num) { - continue; - } - /* we search by net_num if this inode is used or not */ - if (FALSE == rr_node[to_node].is_in_heap) { - rr_node[to_node].is_in_heap = TRUE; - /* Original VPR */ - cost = get_rr_cong_cost(to_node); - /* Push nodes to heap: - * Xifan TANG: - * Need to check we do not push a node twice into the heap! - */ - node_to_heap(to_node, cost, OPEN, OPEN, 0., 0.); - ipin++; - } - } - /* Re-allocate the look-up table if needed */ - if (num_local_opin != ipin) { - clb_opins_used_locally[iblk][iclass].nelem = ipin; - if (0 == clb_opins_used_locally[iblk][iclass].nelem) { - clb_opins_used_locally[iblk][iclass].list = NULL; - } else { - clb_opins_used_locally[iblk][iclass].list = (int *) my_realloc(clb_opins_used_locally[iblk][iclass].list, - clb_opins_used_locally[iblk][iclass].nelem * sizeof(int)); - } - } - /* We want to re-build the list of locally used opins from lowest cost to highest */ - for (iconn = 0; iconn < clb_opins_used_locally[iblk][iclass].nelem; iconn++) { - heap_head_ptr = get_heap_head(); - inode = heap_head_ptr->index; - /* Only update used pins */ - assert(OPEN == rr_node[inode].net_num); - adjust_one_rr_occ_and_pcost(inode, 1, pres_fac); /* Reserve the pin ? */ - clb_opins_used_locally[iblk][iclass].list[iconn] = inode; - rr_node[inode].is_in_heap = FALSE; /* reset the flag */ - free_heap_data(heap_head_ptr); - } - - empty_heap(); - } - } -} - - -static void adjust_one_rr_occ_and_pcost(int inode, int add_or_sub, - float pres_fac) { - - /* Increments or decrements (depending on add_or_sub) the occupancy of * - * one rr_node, and adjusts the present cost of that node appropriately. */ - - int occ, capacity; - - occ = rr_node[inode].occ + add_or_sub; - capacity = rr_node[inode].capacity; - rr_node[inode].occ = occ; - - if (occ < capacity) { - rr_node_route_inf[inode].pres_cost = 1.; - } else { - rr_node_route_inf[inode].pres_cost = 1. - + (occ + 1 - capacity) * pres_fac; - } -} - - -void free_chunk_memory_trace(void) { - if (trace_ch.chunk_ptr_head != NULL) { - free_chunk_memory(&trace_ch); - } -} - - diff --git a/vpr7_x2p/vpr/SRC/route/route_common.h b/vpr7_x2p/vpr/SRC/route/route_common.h deleted file mode 100755 index 272791041..000000000 --- a/vpr7_x2p/vpr/SRC/route/route_common.h +++ /dev/null @@ -1,124 +0,0 @@ -#ifndef ROUTE_COMMON_H -#define ROUTE_COMMON_H - -/************ Defines and types shared by all route files ********************/ - -typedef struct s_heap t_heap; -struct s_heap { - int index; - float cost; - union { - int prev_node; - struct s_heap *next; - } u; - int prev_edge; - float backward_path_cost; - float R_upstream; -}; - -/* Used by the heap as its fundamental data structure. * - * index: Index (ID) of this routing resource node. * - * cost: Cost up to and including this node. * - * u.prev_node: Index (ID) of the predecessor to this node for * - * use in traceback. NO_PREVIOUS if none. * - * u.next: pointer to the next s_heap structure in the free * - * linked list. Not used when on the heap. * - * prev_edge: Index of the edge (between 0 and num_edges-1) used to * - * connect the previous node to this one. NO_PREVIOUS if * - * there is no previous node. * - * backward_path_cost: Used only by the timing-driven router. The "known" * - * cost of the path up to and including this node. * - * In this case, the .cost member contains not only * - * the known backward cost but also an expected cost * - * to the target. * - * R_upstream: Used only by the timing-driven router. Stores the upstream * - * resistance to ground from this node, including the * - * resistance of the node itself (rr_node[index].R). */ - -typedef struct { - int prev_node; - float pres_cost; - float acc_cost; - float path_cost; - float backward_path_cost; - short prev_edge; - short target_flag; -} t_rr_node_route_inf; - -/* Extra information about each rr_node needed only during routing (i.e. * - * during the maze expansion). * - * * - * prev_node: Index of the previous node used to reach this one; * - * used to generate the traceback. If there is no * - * predecessor, prev_node = NO_PREVIOUS. * - * pres_cost: Present congestion cost term for this node. * - * acc_cost: Accumulated cost term from previous Pathfinder iterations. * - * path_cost: Total cost of the path up to and including this node + * - * the expected cost to the target if the timing_driven router * - * is being used. * - * backward_path_cost: Total cost of the path up to and including this * - * node. Not used by breadth-first router. * - * prev_edge: Index of the edge (from 0 to num_edges-1) that was used * - * to reach this node from the previous node. If there is * - * no predecessor, prev_edge = NO_PREVIOUS. * - * target_flag: Is this node a target (sink) for the current routing? * - * Number of times this node must be reached to fully route. */ - -/**************** Variables shared by all route_files ***********************/ - -extern t_rr_node_route_inf *rr_node_route_inf; /* [0..num_rr_nodes-1] */ -extern struct s_bb *route_bb; /* [0..num_nets-1] */ - -/******* Subroutines in route_common used only by other router modules ******/ - -void pathfinder_update_one_cost(struct s_trace *route_segment_start, - int add_or_sub, float pres_fac); - -void pathfinder_update_cost(float pres_fac, float acc_fac); - -struct s_trace *update_traceback(struct s_heap *hptr, int inet); - -void reset_path_costs(void); - -float get_rr_cong_cost(int inode); - -void mark_ends(int inet); - -void node_to_heap(int inode, float cost, int prev_node, int prev_edge, - float backward_path_cost, float R_upstream); - -boolean is_empty_heap(void); - -void free_traceback(int inet); - -void add_to_mod_list(float *fptr); - -struct s_heap *get_heap_head(void); - -void empty_heap(void); - -void free_heap_data(struct s_heap *hptr); - -void invalidate_heap_entries(int sink_node, int ipin_node); - -void init_route_structs(int bb_factor); - -void free_rr_node_route_structs(void); - -void alloc_and_load_rr_node_route_structs(void); - -void reset_rr_node_route_structs(void); - -void alloc_route_static_structs(void); - -void free_trace_structs(void); - -void reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins, - t_ivec ** clb_opins_used_locally); - -void auto_detect_and_reserve_locally_used_opins(float pres_fac, boolean rip_up_local_opins, - t_ivec ** clb_opins_used_locally); - -void free_chunk_memory_trace(void); - -#endif diff --git a/vpr7_x2p/vpr/SRC/route/route_export.h b/vpr7_x2p/vpr/SRC/route/route_export.h deleted file mode 100755 index 4bb2135c7..000000000 --- a/vpr7_x2p/vpr/SRC/route/route_export.h +++ /dev/null @@ -1,34 +0,0 @@ -/******** Function prototypes for functions in route_common.c that *********** - ******** are used outside the router modules. ***********/ - -boolean try_route(int width_fac, struct s_router_opts router_opts, - struct s_det_routing_arch det_routing_arch, t_segment_inf * segment_inf, - t_timing_inf timing_inf, float **net_delay, t_slack * slacks, - t_chan_width_dist chan_width_dist, t_ivec ** clb_opins_used_locally, - boolean * Fc_clipped, t_direct_inf *directs, int num_directs, - /*Xifan TANG: Switch Segment Pattern Support*/ - t_swseg_pattern_inf* swseg_patterns); - -boolean feasible_routing(void); - -t_ivec **alloc_route_structs(void); - -void free_route_structs(); - -struct s_trace **alloc_saved_routing(t_ivec ** clb_opins_used_locally, - t_ivec *** saved_clb_opins_used_locally_ptr); - -void free_saved_routing(struct s_trace **best_routing, - t_ivec ** saved_clb_opins_used_locally); - -void save_routing(struct s_trace **best_routing, - t_ivec ** clb_opins_used_locally, - t_ivec ** saved_clb_opins_used_locally); - -void restore_routing(struct s_trace **best_routing, - t_ivec ** clb_opins_used_locally, - t_ivec ** saved_clb_opins_used_locally); - -void get_serial_num(void); - -void print_route(char *name); diff --git a/vpr7_x2p/vpr/SRC/route/route_timing.c b/vpr7_x2p/vpr/SRC/route/route_timing.c deleted file mode 100755 index c5d4764f5..000000000 --- a/vpr7_x2p/vpr/SRC/route/route_timing.c +++ /dev/null @@ -1,926 +0,0 @@ -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "route_export.h" -#include "route_common.h" -#include "route_tree_timing.h" -#include "route_timing.h" -#include "heapsort.h" -#include "path_delay.h" -#include "net_delay.h" -#include "stats.h" -#include "ReadOptions.h" - -/*mrFPGA: Xifan TANG*/ -#include "mrfpga_globals.h" -#include "buffer_insertion.h" -/* end */ - -/******************** Subroutines local to route_timing.c ********************/ - -static int get_max_pins_per_net(void); - -static void add_route_tree_to_heap(t_rt_node * rt_node, int target_node, - float target_criticality, float astar_fac); - -static void timing_driven_expand_neighbours(struct s_heap *current, int inet, - float bend_cost, float criticality_fac, int target_node, - float astar_fac, int highfanout_rlim); - -static float get_timing_driven_expected_cost(int inode, int target_node, - float criticality_fac, float R_upstream); - -static int get_expected_segs_to_target(int inode, int target_node, - int *num_segs_ortho_dir_ptr); - -static void update_rr_base_costs(int inet, float largest_criticality); - -static void timing_driven_check_net_delays(float **net_delay); - -static int mark_node_expansion_by_bin(int inet, int target_node, - t_rt_node * rt_node); - -/************************ Subroutine definitions *****************************/ - -boolean try_timing_driven_route(struct s_router_opts router_opts, - float **net_delay, t_slack * slacks, t_ivec ** clb_opins_used_locally, boolean timing_analysis_enabled) { - - /* Timing-driven routing algorithm. The timing graph (includes slack) * - * must have already been allocated, and net_delay must have been allocated. * - * Returns TRUE if the routing succeeds, FALSE otherwise. */ - - int itry, inet, ipin, i, bends, wirelength, total_wirelength, available_wirelength, - segments, *net_index, *sink_order /* [1..max_pins_per_net-1] */; - boolean success, is_routable, rip_up_local_opins; - float *pin_criticality /* [1..max_pins_per_net-1] */, pres_fac, *sinks, - critical_path_delay, init_timing_criticality_val; - t_rt_node **rt_node_of_sink; /* [1..max_pins_per_net-1] */ - clock_t begin,end; - sinks = (float*)my_malloc(sizeof(float) * num_nets); - net_index = (int*)my_malloc(sizeof(int) * num_nets); - - for (i = 0; i < num_nets; i++) { - sinks[i] = clb_net[i].num_sinks; - net_index[i] = i; - } - heapsort(net_index, sinks, num_nets, 1); - - alloc_timing_driven_route_structs(&pin_criticality, &sink_order, - &rt_node_of_sink); - - /* First do one routing iteration ignoring congestion to - get reasonable net delay estimates. Set criticalities to 1 - when timing analysis is on to optimize timing, and to 0 - when timing analysis is off to optimize routability. */ - - if (timing_analysis_enabled) { - init_timing_criticality_val = 1.; - } else { - init_timing_criticality_val = 0.; - } - - for (inet = 0; inet < num_nets; inet++) { - if (clb_net[inet].is_global == FALSE) { - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) - slacks->timing_criticality[inet][ipin] = init_timing_criticality_val; -#ifdef PATH_COUNTING - slacks->path_criticality[inet][ipin] = init_timing_criticality_val; -#endif - } else { - /* Set delay of global signals to zero. Non-global net - delays are set by update_net_delays_from_route_tree() - inside timing_driven_route_net(), which is only called - for non-global nets. */ - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { - net_delay[inet][ipin] = 0.; - } - } - } - - pres_fac = router_opts.first_iter_pres_fac; /* Typically 0 -> ignore cong. */ - - for (itry = 1; itry <= router_opts.max_router_iterations; itry++) { - begin = clock(); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Routing iteration: %d\n", itry); - - for (i = 0; i < num_nets; i++) { - inet = net_index[i]; - if (clb_net[inet].is_global == FALSE) { /* Skip global nets. */ - //vpr_printf(TIO_MESSAGE_INFO, "try routing net(%s)...\n", clb_net[inet].name); - - is_routable = timing_driven_route_net(inet, pres_fac, - router_opts.max_criticality, - router_opts.criticality_exp, router_opts.astar_fac, - router_opts.bend_cost, pin_criticality, - sink_order, rt_node_of_sink, net_delay[inet], slacks); - - /* Impossible to route? (disconnected rr_graph) */ - - if (!is_routable) { - vpr_printf(TIO_MESSAGE_INFO, "Routing failed for net (%s).\n", clb_net[inet].name); - free_timing_driven_route_structs(pin_criticality, - sink_order, rt_node_of_sink); - free(net_index); - free(sinks); - return (FALSE); - } - } - } - - if (itry == 1) { - /* Early exit code for cases where it is obvious that a successful route will not be found - Heuristic: If total wirelength used in first routing iteration is X% of total available wirelength, exit - */ - total_wirelength = 0; - available_wirelength = 0; - - for (i = 0; i < num_rr_nodes; i++) { - if (rr_node[i].type == CHANX || rr_node[i].type == CHANY) { - available_wirelength += 1 + rr_node[i].xhigh - - rr_node[i].xlow + rr_node[i].yhigh - - rr_node[i].ylow; - } - } - - for (inet = 0; inet < num_nets; inet++) { - if (clb_net[inet].is_global == FALSE - && clb_net[inet].num_sinks != 0) { /* Globals don't count. */ - get_num_bends_and_length(inet, &bends, &wirelength, - &segments); - - total_wirelength += wirelength; - } - } - vpr_printf(TIO_MESSAGE_INFO, "Wire length after first iteration %d, total available wire length %d, ratio %g\n", - total_wirelength, available_wirelength, - (float) (total_wirelength) / (float) (available_wirelength)); - if ((float) (total_wirelength) / (float) (available_wirelength)> FIRST_ITER_WIRELENTH_LIMIT) { - vpr_printf(TIO_MESSAGE_INFO, "Wire length usage ratio exceeds limit of %g, fail routing.\n", - FIRST_ITER_WIRELENTH_LIMIT); - free_timing_driven_route_structs(pin_criticality, sink_order, - rt_node_of_sink); - free(net_index); - free(sinks); - return FALSE; - } - } - - /* Make sure any CLB OPINs used up by subblocks being hooked directly * - * to them are reserved for that purpose. */ - - if (itry == 1) - rip_up_local_opins = FALSE; - else - rip_up_local_opins = TRUE; - - /* Xifan TANG: may need a new function - * OPINs should only be reserved when it directly connected to a subblock! - */ - /* - reserve_locally_used_opins(pres_fac, rip_up_local_opins, - clb_opins_used_locally); - */ - /* Xifan TANG: a smart function to detect which OPINs are used and update routing cost */ - auto_detect_and_reserve_locally_used_opins(pres_fac, rip_up_local_opins, clb_opins_used_locally); - - /* Pathfinder guys quit after finding a feasible route. I may want to keep * - * going longer, trying to improve timing. Think about this some. */ - - success = feasible_routing(); - if (success) { - vpr_printf(TIO_MESSAGE_INFO, "Successfully routed after %d routing iterations.\n", itry); - free_timing_driven_route_structs(pin_criticality, sink_order, rt_node_of_sink); - /* mrFPGA: Xifan TANG*/ - clear_buffer(); - /* END */ -#ifdef DEBUG - timing_driven_check_net_delays(net_delay); -#endif - /* mrFPGA: Xifan TANG*/ - if (is_wire_buffer) { - try_buffer_for_routing(net_delay); - load_timing_graph_net_delays(net_delay); - /* Print critical path delay - convert to nanoseconds. */ - critical_path_delay = get_critical_path_delay(); - vpr_printf(TIO_MESSAGE_INFO, "After buffer insertion, Critical path: %g ns\n", critical_path_delay); - load_best_buffer_list(); -#ifdef DEBUG - timing_driven_check_net_delays(net_delay); -#endif - } - /* END */ - free(net_index); - free(sinks); - return (TRUE); - } - - if (itry == 1) { - pres_fac = router_opts.initial_pres_fac; - pathfinder_update_cost(pres_fac, 0.); /* Acc_fac=0 for first iter. */ - } else { - pres_fac *= router_opts.pres_fac_mult; - - /* Avoid overflow for high iteration counts, even if acc_cost is big */ - pres_fac = std::min(pres_fac, static_cast(HUGE_POSITIVE_FLOAT / 1e5)); - - pathfinder_update_cost(pres_fac, router_opts.acc_fac); - } - - if (timing_analysis_enabled) { - /* Update slack values by doing another timing analysis. * - * Timing_driven_route_net updated the net delay values. */ - - load_timing_graph_net_delays(net_delay); - - #ifdef HACK_LUT_PIN_SWAPPING - do_timing_analysis(slacks, FALSE, TRUE, FALSE); - #else - do_timing_analysis(slacks, FALSE, FALSE, FALSE); - #endif - - /* Print critical path delay - convert to nanoseconds. */ - critical_path_delay = get_critical_path_delay(); - vpr_printf(TIO_MESSAGE_INFO, "Critical path: %g ns\n", critical_path_delay); - } else { - /* If timing analysis is not enabled, make sure that the criticalities and the * - * net_delays stay as 0 so that wirelength can be optimized. */ - - for (inet = 0; inet < num_nets; inet++) { - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { - slacks->timing_criticality[inet][ipin] = 0.; -#ifdef PATH_COUNTING - slacks->path_criticality[inet][ipin] = 0.; -#endif - net_delay[inet][ipin] = 0.; - } - } - } - - end = clock(); - #ifdef CLOCKS_PER_SEC - vpr_printf(TIO_MESSAGE_INFO, "Routing iteration took %g seconds.\n", (float)(end - begin) / CLOCKS_PER_SEC); - #else - vpr_printf(TIO_MESSAGE_INFO, "Routing iteration took %g seconds.\n", (float)(end - begin) / CLK_PER_SEC); - #endif - - fflush(stdout); - } - - vpr_printf(TIO_MESSAGE_INFO, "Routing failed.\n"); - free_timing_driven_route_structs(pin_criticality, sink_order, - rt_node_of_sink); - free(net_index); - free(sinks); - return (FALSE); -} - -void alloc_timing_driven_route_structs(float **pin_criticality_ptr, - int **sink_order_ptr, t_rt_node *** rt_node_of_sink_ptr) { - - /* Allocates all the structures needed only by the timing-driven router. */ - - int max_pins_per_net; - float *pin_criticality; - int *sink_order; - t_rt_node **rt_node_of_sink; - - max_pins_per_net = get_max_pins_per_net(); - - pin_criticality = (float *) my_malloc( - (max_pins_per_net - 1) * sizeof(float)); - *pin_criticality_ptr = pin_criticality - 1; /* First sink is pin #1. */ - - sink_order = (int *) my_malloc((max_pins_per_net - 1) * sizeof(int)); - *sink_order_ptr = sink_order - 1; - - rt_node_of_sink = (t_rt_node **) my_malloc( - (max_pins_per_net - 1) * sizeof(t_rt_node *)); - *rt_node_of_sink_ptr = rt_node_of_sink - 1; - - alloc_route_tree_timing_structs(); -} - -void free_timing_driven_route_structs(float *pin_criticality, int *sink_order, - t_rt_node ** rt_node_of_sink) { - - /* Frees all the stuctures needed only by the timing-driven router. */ - - free(pin_criticality + 1); /* Starts at index 1. */ - free(sink_order + 1); - free(rt_node_of_sink + 1); - free_route_tree_timing_structs(); -} - -static int get_max_pins_per_net(void) { - - /* Returns the largest number of pins on any non-global net. */ - - int inet, max_pins_per_net; - - max_pins_per_net = 0; - for (inet = 0; inet < num_nets; inet++) { - if (clb_net[inet].is_global == FALSE) { - max_pins_per_net = std::max(max_pins_per_net, - (clb_net[inet].num_sinks + 1)); - } - } - - return (max_pins_per_net); -} - -boolean timing_driven_route_net(int inet, float pres_fac, float max_criticality, - float criticality_exp, float astar_fac, float bend_cost, - float *pin_criticality, int *sink_order, - t_rt_node ** rt_node_of_sink, float *net_delay, t_slack * slacks) { - - /* Returns TRUE as long is found some way to hook up this net, even if that * - * way resulted in overuse of resources (congestion). If there is no way * - * to route this net, even ignoring congestion, it returns FALSE. In this * - * case the rr_graph is disconnected and you can give up. If slacks = NULL, * - * give each net a dummy criticality of 0. */ - - int ipin, num_sinks, itarget, target_pin, target_node, inode; - float target_criticality, old_tcost, new_tcost, largest_criticality, - old_back_cost, new_back_cost; - t_rt_node *rt_root; - struct s_heap *current; - struct s_trace *new_route_start_tptr; - int highfanout_rlim; - - /* Rip-up any old routing. */ - - pathfinder_update_one_cost(trace_head[inet], -1, pres_fac); - free_traceback(inet); - - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { - if (!slacks) { - /* Use criticality of 1. This makes all nets critical. Note: There is a big difference between setting pin criticality to 0 - compared to 1. If pin criticality is set to 0, then the current path delay is completely ignored during routing. By setting - pin criticality to 1, the current path delay to the pin will always be considered and optimized for */ - pin_criticality[ipin] = 1.0; - } else { -#ifdef PATH_COUNTING - /* Pin criticality is based on a weighted sum of timing and path criticalities. */ - pin_criticality[ipin] = ROUTE_PATH_WEIGHT * slacks->path_criticality[inet][ipin] - + (1 - ROUTE_PATH_WEIGHT) * slacks->timing_criticality[inet][ipin]; -#else - /* Pin criticality is based on only timing criticality. */ - pin_criticality[ipin] = slacks->timing_criticality[inet][ipin]; -#endif - /* Currently, pin criticality is between 0 and 1. Now shift it downwards - by 1 - max_criticality (max_criticality is 0.99 by default, so shift down - by 0.01) and cut off at 0. This means that all pins with small criticalities - (<0.01) get criticality 0 and are ignored entirely, and everything - else becomes a bit less critical. This effect becomes more pronounced if - max_criticality is set lower. */ - assert(pin_criticality[ipin] > -0.01 && pin_criticality[ipin] < 1.01); - pin_criticality[ipin] = std::max(pin_criticality[ipin] - (1.0 - max_criticality), 0.0); - - /* Take pin criticality to some power (1 by default). */ - pin_criticality[ipin] = pow(pin_criticality[ipin], criticality_exp); - - /* Cut off pin criticality at max_criticality. */ - pin_criticality[ipin] = std::min(pin_criticality[ipin], max_criticality); - } - } - - num_sinks = clb_net[inet].num_sinks; - heapsort(sink_order, pin_criticality, num_sinks, 0); - - /* Update base costs according to fanout and criticality rules */ - - largest_criticality = pin_criticality[sink_order[1]]; - update_rr_base_costs(inet, largest_criticality); - - mark_ends(inet); /* Only needed to check for multiply-connected SINKs */ - - rt_root = init_route_tree_to_source(inet); - - for (itarget = 1; itarget <= num_sinks; itarget++) { - target_pin = sink_order[itarget]; - target_node = net_rr_terminals[inet][target_pin]; - - target_criticality = pin_criticality[target_pin]; - - highfanout_rlim = mark_node_expansion_by_bin(inet, target_node, - rt_root); - - add_route_tree_to_heap(rt_root, target_node, target_criticality, - astar_fac); - - current = get_heap_head(); - - if (current == NULL) { /* Infeasible routing. No possible path for net. */ - vpr_printf(TIO_MESSAGE_INFO, "Cannot route net #%d (%s) to sink #%d -- no possible path.\n", - inet, clb_net[inet].name, itarget); - reset_path_costs(); - free_route_tree(rt_root); - return (FALSE); - } - - inode = current->index; - - while (inode != target_node) { - old_tcost = rr_node_route_inf[inode].path_cost; - new_tcost = current->cost; - - if (old_tcost > 0.99 * HUGE_POSITIVE_FLOAT) /* First time touched. */ - old_back_cost = HUGE_POSITIVE_FLOAT; - else - old_back_cost = rr_node_route_inf[inode].backward_path_cost; - - new_back_cost = current->backward_path_cost; - - /* I only re-expand a node if both the "known" backward cost is lower * - * in the new expansion (this is necessary to prevent loops from * - * forming in the routing and causing havoc) *and* the expected total * - * cost to the sink is lower than the old value. Different R_upstream * - * values could make a path with lower back_path_cost less desirable * - * than one with higher cost. Test whether or not I should disallow * - * re-expansion based on a higher total cost. */ - - if (old_tcost > new_tcost && old_back_cost > new_back_cost) { - rr_node_route_inf[inode].prev_node = current->u.prev_node; - rr_node_route_inf[inode].prev_edge = current->prev_edge; - rr_node_route_inf[inode].path_cost = new_tcost; - rr_node_route_inf[inode].backward_path_cost = new_back_cost; - - if (old_tcost > 0.99 * HUGE_POSITIVE_FLOAT) /* First time touched. */ - add_to_mod_list(&rr_node_route_inf[inode].path_cost); - - timing_driven_expand_neighbours(current, inet, bend_cost, - target_criticality, target_node, astar_fac, - highfanout_rlim); - } - - free_heap_data(current); - current = get_heap_head(); - - if (current == NULL) { /* Impossible routing. No path for net. */ - vpr_printf(TIO_MESSAGE_INFO, "Cannot route net #%d (%s) to sink #%d -- no possible path.\n", - inet, clb_net[inet].name, itarget); - reset_path_costs(); - free_route_tree(rt_root); - return (FALSE); - } - - inode = current->index; - } - - /* NB: In the code below I keep two records of the partial routing: the * - * traceback and the route_tree. The route_tree enables fast recomputation * - * of the Elmore delay to each node in the partial routing. The traceback * - * lets me reuse all the routines written for breadth-first routing, which * - * all take a traceback structure as input. Before this routine exits the * - * route_tree structure is destroyed; only the traceback is needed at that * - * point. */ - - rr_node_route_inf[inode].target_flag--; /* Connected to this SINK. */ - new_route_start_tptr = update_traceback(current, inet); - rt_node_of_sink[target_pin] = update_route_tree(current); - free_heap_data(current); - pathfinder_update_one_cost(new_route_start_tptr, 1, pres_fac); - - empty_heap(); - reset_path_costs(); - } - - /* For later timing analysis. */ - - update_net_delays_from_route_tree(net_delay, rt_node_of_sink, inet); - free_route_tree(rt_root); - return (TRUE); -} - -static void add_route_tree_to_heap(t_rt_node * rt_node, int target_node, - float target_criticality, float astar_fac) { - - /* Puts the entire partial routing below and including rt_node onto the heap * - * (except for those parts marked as not to be expanded) by calling itself * - * recursively. */ - - int inode; - t_rt_node *child_node; - t_linked_rt_edge *linked_rt_edge; - float tot_cost, backward_path_cost, R_upstream; - - /* Pre-order depth-first traversal */ - - if (rt_node->re_expand) { - inode = rt_node->inode; - backward_path_cost = target_criticality * rt_node->Tdel; - R_upstream = rt_node->R_upstream; - tot_cost = backward_path_cost - + astar_fac - * get_timing_driven_expected_cost(inode, target_node, - target_criticality, R_upstream); - node_to_heap(inode, tot_cost, NO_PREVIOUS, NO_PREVIOUS, - backward_path_cost, R_upstream); - } - - linked_rt_edge = rt_node->u.child_list; - - while (linked_rt_edge != NULL) { - child_node = linked_rt_edge->child; - add_route_tree_to_heap(child_node, target_node, target_criticality, - astar_fac); - linked_rt_edge = linked_rt_edge->next; - } -} - -static void timing_driven_expand_neighbours(struct s_heap *current, int inet, - float bend_cost, float criticality_fac, int target_node, - float astar_fac, int highfanout_rlim) { - - /* Puts all the rr_nodes adjacent to current on the heap. rr_nodes outside * - * the expanded bounding box specified in route_bb are not added to the * - * heap. */ - - int iconn, to_node, num_edges, inode, iswitch, target_x, target_y; - t_rr_type from_type, to_type; - float new_tot_cost, old_back_pcost, new_back_pcost, R_upstream; - float new_R_upstream, Tdel; - - inode = current->index; - old_back_pcost = current->backward_path_cost; - R_upstream = current->R_upstream; - num_edges = rr_node[inode].num_edges; - - target_x = rr_node[target_node].xhigh; - target_y = rr_node[target_node].yhigh; - - for (iconn = 0; iconn < num_edges; iconn++) { - to_node = rr_node[inode].edges[iconn]; - - if (rr_node[to_node].xhigh < route_bb[inet].xmin - || rr_node[to_node].xlow > route_bb[inet].xmax - || rr_node[to_node].yhigh < route_bb[inet].ymin - || rr_node[to_node].ylow > route_bb[inet].ymax) - continue; /* Node is outside (expanded) bounding box. */ - - if (clb_net[inet].num_sinks >= HIGH_FANOUT_NET_LIM) { - if (rr_node[to_node].xhigh < target_x - highfanout_rlim - || rr_node[to_node].xlow > target_x + highfanout_rlim - || rr_node[to_node].yhigh < target_y - highfanout_rlim - || rr_node[to_node].ylow > target_y + highfanout_rlim) - continue; /* Node is outside high fanout bin. */ - } - - /* Prune away IPINs that lead to blocks other than the target one. Avoids * - * the issue of how to cost them properly so they don't get expanded before * - * more promising routes, but makes route-throughs (via CLBs) impossible. * - * Change this if you want to investigate route-throughs. */ - - to_type = rr_node[to_node].type; - if (to_type == IPIN - && (rr_node[to_node].xhigh != target_x - || rr_node[to_node].yhigh != target_y)) - continue; - - /* new_back_pcost stores the "known" part of the cost to this node -- the * - * congestion cost of all the routing resources back to the existing route * - * plus the known delay of the total path back to the source. new_tot_cost * - * is this "known" backward cost + an expected cost to get to the target. */ - - new_back_pcost = old_back_pcost - + (1. - criticality_fac) * get_rr_cong_cost(to_node); - - iswitch = rr_node[inode].switches[iconn]; - if (switch_inf[iswitch].buffered) { - new_R_upstream = switch_inf[iswitch].R; - } else { - new_R_upstream = R_upstream + switch_inf[iswitch].R; - } - - Tdel = rr_node[to_node].C * (new_R_upstream + 0.5 * rr_node[to_node].R); - Tdel += switch_inf[iswitch].Tdel; - new_R_upstream += rr_node[to_node].R; - new_back_pcost += criticality_fac * Tdel; - - if (bend_cost != 0.) { - from_type = rr_node[inode].type; - to_type = rr_node[to_node].type; - if ((from_type == CHANX && to_type == CHANY) - || (from_type == CHANY && to_type == CHANX)) - new_back_pcost += bend_cost; - } - - new_tot_cost = new_back_pcost - + astar_fac - * get_timing_driven_expected_cost(to_node, target_node, - criticality_fac, new_R_upstream); - - node_to_heap(to_node, new_tot_cost, inode, iconn, new_back_pcost, - new_R_upstream); - - } /* End for all neighbours */ -} - -static float get_timing_driven_expected_cost(int inode, int target_node, - float criticality_fac, float R_upstream) { - - /* Determines the expected cost (due to both delay and resouce cost) to reach * - * the target node from inode. It doesn't include the cost of inode -- * - * that's already in the "known" path_cost. */ - - t_rr_type rr_type; - int cost_index, ortho_cost_index, num_segs_same_dir, num_segs_ortho_dir; - float expected_cost, cong_cost, Tdel; - - rr_type = rr_node[inode].type; - - if (rr_type == CHANX || rr_type == CHANY) { - num_segs_same_dir = get_expected_segs_to_target(inode, target_node, - &num_segs_ortho_dir); - cost_index = rr_node[inode].cost_index; - ortho_cost_index = rr_indexed_data[cost_index].ortho_cost_index; - - cong_cost = num_segs_same_dir * rr_indexed_data[cost_index].base_cost - + num_segs_ortho_dir - * rr_indexed_data[ortho_cost_index].base_cost; - cong_cost += rr_indexed_data[IPIN_COST_INDEX].base_cost - + rr_indexed_data[SINK_COST_INDEX].base_cost; - - Tdel = - num_segs_same_dir * rr_indexed_data[cost_index].T_linear - + num_segs_ortho_dir - * rr_indexed_data[ortho_cost_index].T_linear - + num_segs_same_dir * num_segs_same_dir - * rr_indexed_data[cost_index].T_quadratic - + num_segs_ortho_dir * num_segs_ortho_dir - * rr_indexed_data[ortho_cost_index].T_quadratic - + R_upstream - * (num_segs_same_dir - * rr_indexed_data[cost_index].C_load - + num_segs_ortho_dir - * rr_indexed_data[ortho_cost_index].C_load); - - Tdel += rr_indexed_data[IPIN_COST_INDEX].T_linear; - - expected_cost = criticality_fac * Tdel - + (1. - criticality_fac) * cong_cost; - return (expected_cost); - } - - else if (rr_type == IPIN) { /* Change if you're allowing route-throughs */ - return (rr_indexed_data[SINK_COST_INDEX].base_cost); - } - - else { /* Change this if you want to investigate route-throughs */ - return (0.); - } -} - -/* Macro used below to ensure that fractions are rounded up, but floating * - * point values very close to an integer are rounded to that integer. */ - -#define ROUND_UP(x) (ceil (x - 0.001)) - -static int get_expected_segs_to_target(int inode, int target_node, - int *num_segs_ortho_dir_ptr) { - - /* Returns the number of segments the same type as inode that will be needed * - * to reach target_node (not including inode) in each direction (the same * - * direction (horizontal or vertical) as inode and the orthogonal direction).*/ - - t_rr_type rr_type; - int target_x, target_y, num_segs_same_dir, cost_index, ortho_cost_index; - int no_need_to_pass_by_clb; - float inv_length, ortho_inv_length, ylow, yhigh, xlow, xhigh; - - target_x = rr_node[target_node].xlow; - target_y = rr_node[target_node].ylow; - cost_index = rr_node[inode].cost_index; - inv_length = rr_indexed_data[cost_index].inv_length; - ortho_cost_index = rr_indexed_data[cost_index].ortho_cost_index; - ortho_inv_length = rr_indexed_data[ortho_cost_index].inv_length; - rr_type = rr_node[inode].type; - - if (rr_type == CHANX) { - ylow = rr_node[inode].ylow; - xhigh = rr_node[inode].xhigh; - xlow = rr_node[inode].xlow; - - /* Count vertical (orthogonal to inode) segs first. */ - - if (ylow > target_y) { /* Coming from a row above target? */ - *num_segs_ortho_dir_ptr = - (int)(ROUND_UP((ylow - target_y + 1.) * ortho_inv_length)); - no_need_to_pass_by_clb = 1; - } else if (ylow < target_y - 1) { /* Below the CLB bottom? */ - *num_segs_ortho_dir_ptr = (int)(ROUND_UP((target_y - ylow) * - ortho_inv_length)); - no_need_to_pass_by_clb = 1; - } else { /* In a row that passes by target CLB */ - *num_segs_ortho_dir_ptr = 0; - no_need_to_pass_by_clb = 0; - } - - /* Now count horizontal (same dir. as inode) segs. */ - - if (xlow > target_x + no_need_to_pass_by_clb) { - num_segs_same_dir = (int)(ROUND_UP((xlow - no_need_to_pass_by_clb - - target_x) * inv_length)); - } else if (xhigh < target_x - no_need_to_pass_by_clb) { - num_segs_same_dir = (int)(ROUND_UP((target_x - no_need_to_pass_by_clb - - xhigh) * inv_length)); - } else { - num_segs_same_dir = 0; - } - } - - else { /* inode is a CHANY */ - ylow = rr_node[inode].ylow; - yhigh = rr_node[inode].yhigh; - xlow = rr_node[inode].xlow; - - /* Count horizontal (orthogonal to inode) segs first. */ - - if (xlow > target_x) { /* Coming from a column right of target? */ - *num_segs_ortho_dir_ptr = (int)( - ROUND_UP((xlow - target_x + 1.) * ortho_inv_length)); - no_need_to_pass_by_clb = 1; - } else if (xlow < target_x - 1) { /* Left of and not adjacent to the CLB? */ - *num_segs_ortho_dir_ptr = (int)(ROUND_UP((target_x - xlow) * - ortho_inv_length)); - no_need_to_pass_by_clb = 1; - } else { /* In a column that passes by target CLB */ - *num_segs_ortho_dir_ptr = 0; - no_need_to_pass_by_clb = 0; - } - - /* Now count vertical (same dir. as inode) segs. */ - - if (ylow > target_y + no_need_to_pass_by_clb) { - num_segs_same_dir = (int)(ROUND_UP((ylow - no_need_to_pass_by_clb - - target_y) * inv_length)); - } else if (yhigh < target_y - no_need_to_pass_by_clb) { - num_segs_same_dir = (int)(ROUND_UP((target_y - no_need_to_pass_by_clb - - yhigh) * inv_length)); - } else { - num_segs_same_dir = 0; - } - } - - return (num_segs_same_dir); -} - -static void update_rr_base_costs(int inet, float largest_criticality) { - - /* Changes the base costs of different types of rr_nodes according to the * - * criticality, fanout, etc. of the current net being routed (inet). */ - - float fanout, factor; - int index; - - fanout = clb_net[inet].num_sinks; - - /* Other reasonable values for factor include fanout and 1 */ - factor = sqrt(fanout); - - for (index = CHANX_COST_INDEX_START; index < num_rr_indexed_data; index++) { - if (rr_indexed_data[index].T_quadratic > 0.) { /* pass transistor */ - rr_indexed_data[index].base_cost = - rr_indexed_data[index].saved_base_cost * factor; - } else { - rr_indexed_data[index].base_cost = - rr_indexed_data[index].saved_base_cost; - } - } -} - -/* Nets that have high fanout can take a very long time to route. Each sink should be routed contained within a bin instead of the entire bounding box to speed things up */ -static int mark_node_expansion_by_bin(int inet, int target_node, - t_rt_node * rt_node) { - int target_x, target_y; - int rlim = 1; - int inode; - float area; - boolean success; - t_linked_rt_edge *linked_rt_edge; - t_rt_node * child_node; - - target_x = rr_node[target_node].xlow; - target_y = rr_node[target_node].ylow; - - if (clb_net[inet].num_sinks < HIGH_FANOUT_NET_LIM) { - /* This algorithm only applies to high fanout nets */ - return 1; - } - - area = (route_bb[inet].xmax - route_bb[inet].xmin) - * (route_bb[inet].ymax - route_bb[inet].ymin); - if (area <= 0) { - area = 1; - } - - rlim = (int)(ceil(sqrt((float) area / (float) clb_net[inet].num_sinks))); - if (rt_node == NULL || rt_node->u.child_list == NULL) { - /* If unknown traceback, set radius of bin to be size of chip */ - rlim = std::max(nx + 2, ny + 2); - return rlim; - } - - success = FALSE; - /* determine quickly a feasible bin radius to route sink for high fanout nets - this is necessary to prevent super long runtimes for high fanout nets; in best case, a reduction in complexity from O(N^2logN) to O(NlogN) (Swartz fast router) - */ - linked_rt_edge = rt_node->u.child_list; - while (success == FALSE && linked_rt_edge != NULL) { - while (linked_rt_edge != NULL && success == FALSE) { - child_node = linked_rt_edge->child; - inode = child_node->inode; - if (!(rr_node[inode].type == IPIN || rr_node[inode].type == SINK)) { - if (rr_node[inode].xlow <= target_x + rlim - && rr_node[inode].xhigh >= target_x - rlim - && rr_node[inode].ylow <= target_y + rlim - && rr_node[inode].yhigh >= target_y - rlim) { - success = TRUE; - } - } - linked_rt_edge = linked_rt_edge->next; - } - - if (success == FALSE) { - if (rlim > std::max(nx + 2, ny + 2)) { - vpr_printf(TIO_MESSAGE_ERROR, "VPR internal error, net %s has paths that are not found in traceback.\n", - clb_net[inet].name); - exit(1); - } - /* if sink not in bin, increase bin size until fit */ - rlim *= 2; - } else { - /* Sometimes might just catch a wire in the end segment, need to give it some channel space to explore */ - rlim += 4; - } - linked_rt_edge = rt_node->u.child_list; - } - - /* redetermine expansion based on rlim */ - linked_rt_edge = rt_node->u.child_list; - while (linked_rt_edge != NULL) { - child_node = linked_rt_edge->child; - inode = child_node->inode; - if (!(rr_node[inode].type == IPIN || rr_node[inode].type == SINK)) { - if (rr_node[inode].xlow <= target_x + rlim - && rr_node[inode].xhigh >= target_x - rlim - && rr_node[inode].ylow <= target_y + rlim - && rr_node[inode].yhigh >= target_y - rlim) { - child_node->re_expand = TRUE; - } else { - child_node->re_expand = FALSE; - } - } - linked_rt_edge = linked_rt_edge->next; - } - return rlim; -} - -#define ERROR_TOL 0.0001 - -static void timing_driven_check_net_delays(float **net_delay) { - - /* Checks that the net delays computed incrementally during timing driven * - * routing match those computed from scratch by the net_delay.c module. */ - - int inet, ipin; - float **net_delay_check; - - t_chunk list_head_net_delay_check_ch = {NULL, 0, NULL}; - - /*struct s_linked_vptr *ch_list_head_net_delay_check;*/ - - net_delay_check = alloc_net_delay(&list_head_net_delay_check_ch, clb_net, - num_nets); - load_net_delay_from_routing(net_delay_check, clb_net, num_nets); - - for (inet = 0; inet < num_nets; inet++) { - for (ipin = 1; ipin <= clb_net[inet].num_sinks; ipin++) { - if (net_delay_check[inet][ipin] == 0.) { /* Should be only GLOBAL nets */ - if (fabs(net_delay[inet][ipin]) > ERROR_TOL) { - vpr_printf(TIO_MESSAGE_ERROR, "in timing_driven_check_net_delays: net %d pin %d.\n", - inet, ipin); - vpr_printf(TIO_MESSAGE_ERROR, "\tIncremental calc. net_delay is %g, but from scratch net delay is %g.\n", - net_delay[inet][ipin], net_delay_check[inet][ipin]); - exit(1); - } - } else { - if (fabs(1.0 - net_delay[inet][ipin] / net_delay_check[inet][ipin]) > ERROR_TOL) { - vpr_printf(TIO_MESSAGE_ERROR, "in timing_driven_check_net_delays: net %d pin %d.\n", - inet, ipin); - vpr_printf(TIO_MESSAGE_ERROR, "\tIncremental calc. net_delay is %g, but from scratch net delay is %g.\n", - net_delay[inet][ipin], net_delay_check[inet][ipin]); - exit(1); - } - } - } - } - - free_net_delay(net_delay_check, &list_head_net_delay_check_ch); - vpr_printf(TIO_MESSAGE_INFO, "Completed net delay value cross check successfully.\n"); -} diff --git a/vpr7_x2p/vpr/SRC/route/route_timing.h b/vpr7_x2p/vpr/SRC/route/route_timing.h deleted file mode 100755 index d6f6192bc..000000000 --- a/vpr7_x2p/vpr/SRC/route/route_timing.h +++ /dev/null @@ -1,11 +0,0 @@ -boolean try_timing_driven_route(struct s_router_opts router_opts, - float **net_delay, t_slack * slacks, t_ivec ** clb_opins_used_locally, - boolean timing_analysis_enabled); -boolean timing_driven_route_net(int inet, float pres_fac, float max_criticality, - float criticality_exp, float astar_fac, float bend_cost, - float *pin_criticality, int *sink_order, t_rt_node ** rt_node_of_sink, - float *net_delay, t_slack * slacks); -void alloc_timing_driven_route_structs(float **pin_criticality_ptr, - int **sink_order_ptr, t_rt_node *** rt_node_of_sink_ptr); -void free_timing_driven_route_structs(float *pin_criticality, int *sink_order, - t_rt_node ** rt_node_of_sink); diff --git a/vpr7_x2p/vpr/SRC/route/route_tree_timing.c b/vpr7_x2p/vpr/SRC/route/route_tree_timing.c deleted file mode 100755 index 409dac801..000000000 --- a/vpr7_x2p/vpr/SRC/route/route_tree_timing.c +++ /dev/null @@ -1,519 +0,0 @@ -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "route_common.h" -#include "route_tree_timing.h" - -/* mrFPGA: Xifan TANG */ -#include "mrfpga_globals.h" -/* end */ - -/* This module keeps track of the partial routing tree for timing-driven * - * routing. The normal traceback structure doesn't provide enough info * - * about the partial routing during timing-driven routing, so the routines * - * in this module are used to keep a tree representation of the partial * - * routing during timing-driven routing. This allows rapid incremental * - * timing analysis. The net_delay module does timing analysis in one step * - * (not incrementally as pieces of the routing are added). I could probably * - * one day remove a lot of net_delay.c and call the corresponding routines * - * here, but it's useful to have a from-scratch delay calculator to check * - * the results of this one. */ - -/********************** Variables local to this module ***********************/ - -/* Array below allows mapping from any rr_node to any rt_node currently in * - * the rt_tree. */ - -static t_rt_node **rr_node_to_rt_node = NULL; /* [0..num_rr_nodes-1] */ - -/* Frees lists for fast addition and deletion of nodes and edges. */ - -static t_rt_node *rt_node_free_list = NULL; -static t_linked_rt_edge *rt_edge_free_list = NULL; - -/********************** Subroutines local to this module *********************/ - -static t_rt_node *alloc_rt_node(void); - -static void free_rt_node(t_rt_node * rt_node); - -static t_linked_rt_edge *alloc_linked_rt_edge(void); - -static void free_linked_rt_edge(t_linked_rt_edge * rt_edge); - -static t_rt_node *add_path_to_route_tree(struct s_heap *hptr, - t_rt_node ** sink_rt_node_ptr); - -static void load_new_path_R_upstream(t_rt_node * start_of_new_path_rt_node); - -static t_rt_node *update_unbuffered_ancestors_C_downstream( - t_rt_node * start_of_new_path_rt_node); - -static void load_rt_subtree_Tdel(t_rt_node * subtree_rt_root, float Tarrival); - -/************************** Subroutine definitions ***************************/ - -void alloc_route_tree_timing_structs(void) { - - /* Allocates any structures needed to build the routing trees. */ - - if (rr_node_to_rt_node != NULL || rt_node_free_list != NULL - || rt_node_free_list != NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "in alloc_route_tree_timing_structs: old structures already exist.\n"); - exit(1); - } - - rr_node_to_rt_node = (t_rt_node **) my_malloc( - num_rr_nodes * sizeof(t_rt_node *)); -} - -void free_route_tree_timing_structs(void) { - - /* Frees the structures needed to build routing trees, and really frees * - * (i.e. calls free) all the data on the free lists. */ - - t_rt_node *rt_node, *next_node; - t_linked_rt_edge *rt_edge, *next_edge; - - free(rr_node_to_rt_node); - rr_node_to_rt_node = NULL; - - rt_node = rt_node_free_list; - - while (rt_node != NULL) { - next_node = rt_node->u.next; - free(rt_node); - rt_node = next_node; - } - - rt_node_free_list = NULL; - - rt_edge = rt_edge_free_list; - - while (rt_edge != NULL) { - next_edge = rt_edge->next; - free(rt_edge); - rt_edge = next_edge; - } - - rt_edge_free_list = NULL; -} - -static t_rt_node * -alloc_rt_node(void) { - - /* Allocates a new rt_node, from the free list if possible, from the free * - * store otherwise. */ - - t_rt_node *rt_node; - - rt_node = rt_node_free_list; - - if (rt_node != NULL) { - rt_node_free_list = rt_node->u.next; - } else { - rt_node = (t_rt_node *) my_malloc(sizeof(t_rt_node)); - } - - return (rt_node); -} - -static void free_rt_node(t_rt_node * rt_node) { - - /* Adds rt_node to the proper free list. */ - - rt_node->u.next = rt_node_free_list; - rt_node_free_list = rt_node; -} - -static t_linked_rt_edge * -alloc_linked_rt_edge(void) { - - /* Allocates a new linked_rt_edge, from the free list if possible, from the * - * free store otherwise. */ - - t_linked_rt_edge *linked_rt_edge; - - linked_rt_edge = rt_edge_free_list; - - if (linked_rt_edge != NULL) { - rt_edge_free_list = linked_rt_edge->next; - } else { - linked_rt_edge = (t_linked_rt_edge *) my_malloc( - sizeof(t_linked_rt_edge)); - } - - return (linked_rt_edge); -} - -static void free_linked_rt_edge(t_linked_rt_edge * rt_edge) { - - /* Adds the rt_edge to the rt_edge free list. */ - - rt_edge->next = rt_edge_free_list; - rt_edge_free_list = rt_edge; -} - -t_rt_node * -init_route_tree_to_source(int inet) { - - /* Initializes the routing tree to just the net source, and returns the root * - * node of the rt_tree (which is just the net source). */ - - t_rt_node *rt_root; - int inode; - - rt_root = alloc_rt_node(); - rt_root->u.child_list = NULL; - rt_root->parent_node = NULL; - rt_root->parent_switch = OPEN; - rt_root->re_expand = TRUE; - - inode = net_rr_terminals[inet][0]; /* Net source */ - - rt_root->inode = inode; - rt_root->C_downstream = rr_node[inode].C; - rt_root->R_upstream = rr_node[inode].R; - rt_root->Tdel = 0.5 * rr_node[inode].R * rr_node[inode].C; - rr_node_to_rt_node[inode] = rt_root; - - return (rt_root); -} - -t_rt_node * -update_route_tree(struct s_heap * hptr) { - - /* Adds the most recently finished wire segment to the routing tree, and * - * updates the Tdel, etc. numbers for the rest of the routing tree. hptr * - * is the heap pointer of the SINK that was reached. This routine returns * - * a pointer to the rt_node of the SINK that it adds to the routing. */ - - t_rt_node *start_of_new_path_rt_node, *sink_rt_node; - t_rt_node *unbuffered_subtree_rt_root, *subtree_parent_rt_node; - float Tdel_start; - short iswitch; - - start_of_new_path_rt_node = add_path_to_route_tree(hptr, &sink_rt_node); - load_new_path_R_upstream(start_of_new_path_rt_node); - unbuffered_subtree_rt_root = update_unbuffered_ancestors_C_downstream( - start_of_new_path_rt_node); - - subtree_parent_rt_node = unbuffered_subtree_rt_root->parent_node; - - if (subtree_parent_rt_node != NULL) { /* Parent exists. */ - Tdel_start = subtree_parent_rt_node->Tdel; - iswitch = unbuffered_subtree_rt_root->parent_switch; - Tdel_start += switch_inf[iswitch].R - * unbuffered_subtree_rt_root->C_downstream; - Tdel_start += switch_inf[iswitch].Tdel; - } else { /* Subtree starts at SOURCE */ - Tdel_start = 0.; - } - - load_rt_subtree_Tdel(unbuffered_subtree_rt_root, Tdel_start); - - return (sink_rt_node); -} - -static t_rt_node * -add_path_to_route_tree(struct s_heap *hptr, t_rt_node ** sink_rt_node_ptr) { - - /* Adds the most recent wire segment, ending at the SINK indicated by hptr, * - * to the routing tree. It returns the first (most upstream) new rt_node, * - * and (via a pointer) the rt_node of the new SINK. */ - - int inode, remaining_connections_to_sink, no_route_throughs; - short iedge, iswitch; - float C_downstream; - t_rt_node *rt_node, *downstream_rt_node, *sink_rt_node; - t_linked_rt_edge *linked_rt_edge; - - inode = hptr->index; - -#ifdef DEBUG - if (rr_node[inode].type != SINK) { - vpr_printf(TIO_MESSAGE_ERROR, "in add_path_to_route_tree. Expected type = SINK (%d).\n", SINK); - vpr_printf(TIO_MESSAGE_INFO, "Got type = %d.", rr_node[inode].type); - exit(1); - } -#endif - - remaining_connections_to_sink = rr_node_route_inf[inode].target_flag; - sink_rt_node = alloc_rt_node(); - sink_rt_node->u.child_list = NULL; - sink_rt_node->inode = inode; - C_downstream = rr_node[inode].C; - sink_rt_node->C_downstream = C_downstream; - rr_node_to_rt_node[inode] = sink_rt_node; - - /* In the code below I'm marking SINKs and IPINs as not to be re-expanded. * - * Undefine NO_ROUTE_THROUGHS if you want route-throughs or ipin doglegs. * - * It makes the code more efficient (though not vastly) to prune this way * - * when there aren't route-throughs or ipin doglegs. */ - -#define NO_ROUTE_THROUGHS 1 /* Can't route through unused CLB outputs */ - no_route_throughs = 1; - if (no_route_throughs == 1) - sink_rt_node->re_expand = FALSE; - else { - if (remaining_connections_to_sink == 0) { /* Usual case */ - sink_rt_node->re_expand = TRUE; - } - - /* Weird case. This net connects several times to the same SINK. Thus I * - * can't re_expand this node as part of the partial routing for subsequent * - * connections, since I need to reach it again via another path. */ - - else { - sink_rt_node->re_expand = FALSE; - } - } - - /* Now do it's predecessor. */ - - downstream_rt_node = sink_rt_node; - inode = hptr->u.prev_node; - iedge = hptr->prev_edge; - iswitch = rr_node[inode].switches[iedge]; - - /* For all "new" nodes in the path */ - - while (rr_node_route_inf[inode].prev_node != NO_PREVIOUS) { - linked_rt_edge = alloc_linked_rt_edge(); - linked_rt_edge->child = downstream_rt_node; - linked_rt_edge->iswitch = iswitch; - linked_rt_edge->next = NULL; - - rt_node = alloc_rt_node(); - downstream_rt_node->parent_node = rt_node; - downstream_rt_node->parent_switch = iswitch; - - rt_node->u.child_list = linked_rt_edge; - rt_node->inode = inode; - - if (switch_inf[iswitch].buffered == FALSE) - C_downstream += rr_node[inode].C; - else - C_downstream = rr_node[inode].C; - - /* mrFPGA : Xifan TANG*/ - if (is_isolation) { - C_downstream += switch_inf[iswitch].Cin; - if (FALSE == switch_inf[iswitch].buffered) { - C_downstream += switch_inf[iswitch].Cout; - } - } - /* end */ - - rt_node->C_downstream = C_downstream; - rr_node_to_rt_node[inode] = rt_node; - - if (no_route_throughs == 1) - if (rr_node[inode].type == IPIN) - rt_node->re_expand = FALSE; - else - rt_node->re_expand = TRUE; - - else { - if (remaining_connections_to_sink == 0) { /* Normal case */ - rt_node->re_expand = TRUE; - } else { /* This is the IPIN before a multiply-connected SINK */ - rt_node->re_expand = FALSE; - - /* Reset flag so wire segments get reused */ - - remaining_connections_to_sink = 0; - } - } - - downstream_rt_node = rt_node; - iedge = rr_node_route_inf[inode].prev_edge; - inode = rr_node_route_inf[inode].prev_node; - iswitch = rr_node[inode].switches[iedge]; - } - - /* Inode is the join point to the old routing */ - - rt_node = rr_node_to_rt_node[inode]; - - linked_rt_edge = alloc_linked_rt_edge(); - linked_rt_edge->child = downstream_rt_node; - linked_rt_edge->iswitch = iswitch; - linked_rt_edge->next = rt_node->u.child_list; - rt_node->u.child_list = linked_rt_edge; - - downstream_rt_node->parent_node = rt_node; - downstream_rt_node->parent_switch = iswitch; - - *sink_rt_node_ptr = sink_rt_node; - return (downstream_rt_node); -} - -static void load_new_path_R_upstream(t_rt_node * start_of_new_path_rt_node) { - - /* Sets the R_upstream values of all the nodes in the new path to the * - * correct value. */ - - float R_upstream; - int inode; - short iswitch; - t_rt_node *rt_node, *parent_rt_node; - t_linked_rt_edge *linked_rt_edge; - - rt_node = start_of_new_path_rt_node; - iswitch = rt_node->parent_switch; - inode = rt_node->inode; - parent_rt_node = rt_node->parent_node; - - R_upstream = switch_inf[iswitch].R + rr_node[inode].R; - - if (switch_inf[iswitch].buffered == FALSE) - R_upstream += parent_rt_node->R_upstream; - - rt_node->R_upstream = R_upstream; - - /* Note: the traversal below makes use of the fact that this new path * - * really is a path (not a tree with branches) to do a traversal without * - * recursion, etc. */ - - linked_rt_edge = rt_node->u.child_list; - - while (linked_rt_edge != NULL) { /* While SINK not reached. */ - -#ifdef DEBUG - if (linked_rt_edge->next != NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "in load_new_path_R_upstream: new routing addition is a tree (not a path).\n"); - exit(1); - } -#endif - - rt_node = linked_rt_edge->child; - iswitch = linked_rt_edge->iswitch; - inode = rt_node->inode; - - if (switch_inf[iswitch].buffered) - R_upstream = switch_inf[iswitch].R + rr_node[inode].R; - else - R_upstream += switch_inf[iswitch].R + rr_node[inode].R; - - rt_node->R_upstream = R_upstream; - linked_rt_edge = rt_node->u.child_list; - } -} - -static t_rt_node * -update_unbuffered_ancestors_C_downstream(t_rt_node * start_of_new_path_rt_node) { - - /* Updates the C_downstream values for the ancestors of the new path. Once * - * a buffered switch is found amongst the ancestors, no more ancestors are * - * affected. Returns the root of the "unbuffered subtree" whose Tdel * - * values are affected by the new path's addition. */ - - t_rt_node *rt_node, *parent_rt_node; - short iswitch; - float C_downstream_addition; - - rt_node = start_of_new_path_rt_node; - C_downstream_addition = rt_node->C_downstream; - parent_rt_node = rt_node->parent_node; - iswitch = rt_node->parent_switch; - - /* mrFPGA: Xifan TANG */ - if (is_isolation) { - if (parent_rt_node != NULL && switch_inf[iswitch].buffered) { - rt_node = parent_rt_node; - C_downstream_addition = switch_inf[iswitch].Cin; - rt_node->C_downstream += C_downstream_addition; - parent_rt_node = rt_node->parent_node; - iswitch = rt_node->parent_switch; - } else { - C_downstream_addition += switch_inf[iswitch].Cin + switch_inf[iswitch].Cout; - } - } - /* end */ - - while (parent_rt_node != NULL && switch_inf[iswitch].buffered == FALSE) { - rt_node = parent_rt_node; - rt_node->C_downstream += C_downstream_addition; - parent_rt_node = rt_node->parent_node; - iswitch = rt_node->parent_switch; - } - - return (rt_node); -} - -static void load_rt_subtree_Tdel(t_rt_node * subtree_rt_root, float Tarrival) { - - /* Updates the Tdel values of the subtree rooted at subtree_rt_root by * - * by calling itself recursively. The C_downstream values of all the nodes * - * must be correct before this routine is called. Tarrival is the time at * - * at which the signal arrives at this node's *input*. */ - - int inode; - short iswitch; - t_rt_node *child_node; - t_linked_rt_edge *linked_rt_edge; - float Tdel, Tchild; - - inode = subtree_rt_root->inode; - - /* Assuming the downstream connections are, on average, connected halfway * - * along a wire segment's length. See discussion in net_delay.c if you want * - * to change this. */ - - Tdel = Tarrival + 0.5 * subtree_rt_root->C_downstream * rr_node[inode].R; - subtree_rt_root->Tdel = Tdel; - - /* Now expand the children of this node to load their Tdel values (depth- * - * first pre-order traversal). */ - - linked_rt_edge = subtree_rt_root->u.child_list; - - while (linked_rt_edge != NULL) { - iswitch = linked_rt_edge->iswitch; - child_node = linked_rt_edge->child; - - Tchild = Tdel + switch_inf[iswitch].R * child_node->C_downstream; - Tchild += switch_inf[iswitch].Tdel; /* Intrinsic switch delay. */ - load_rt_subtree_Tdel(child_node, Tchild); - - linked_rt_edge = linked_rt_edge->next; - } -} - -void free_route_tree(t_rt_node * rt_node) { - - /* Puts the rt_nodes and edges in the tree rooted at rt_node back on the * - * free lists. Recursive, depth-first post-order traversal. */ - - t_rt_node *child_node; - t_linked_rt_edge *rt_edge, *next_edge; - - rt_edge = rt_node->u.child_list; - - while (rt_edge != NULL) { /* For all children */ - child_node = rt_edge->child; - free_route_tree(child_node); - next_edge = rt_edge->next; - free_linked_rt_edge(rt_edge); - rt_edge = next_edge; - } - - free_rt_node(rt_node); -} - -void update_net_delays_from_route_tree(float *net_delay, - t_rt_node ** rt_node_of_sink, int inet) { - - /* Goes through all the sinks of this net and copies their delay values from * - * the route_tree to the net_delay array. */ - - int isink; - t_rt_node *sink_rt_node; - - for (isink = 1; isink <= clb_net[inet].num_sinks; isink++) { - sink_rt_node = rt_node_of_sink[isink]; - net_delay[isink] = sink_rt_node->Tdel; - } -} diff --git a/vpr7_x2p/vpr/SRC/route/route_tree_timing.h b/vpr7_x2p/vpr/SRC/route/route_tree_timing.h deleted file mode 100755 index 50d9d7c18..000000000 --- a/vpr7_x2p/vpr/SRC/route/route_tree_timing.h +++ /dev/null @@ -1,68 +0,0 @@ -/************** Types and defines exported by route_tree_timing.c ************/ - -struct s_linked_rt_edge { - struct s_rt_node *child; - short iswitch; - struct s_linked_rt_edge *next; -}; - -typedef struct s_linked_rt_edge t_linked_rt_edge; - -/* Linked list listing the children of an rt_node. * - * child: Pointer to an rt_node (child of the current node). * - * iswitch: Index of the switch type used to connect to the child node. * - * next: Pointer to the next linked_rt_edge in the linked list (allows * - * you to get the next child of the current rt_node). */ - -struct s_rt_node { - union { - t_linked_rt_edge *child_list; - struct s_rt_node *next; - } u; - struct s_rt_node *parent_node; - short parent_switch; - short re_expand; - int inode; - float C_downstream; - float R_upstream; - float Tdel; -}; - -typedef struct s_rt_node t_rt_node; - -/* Structure describing one node in a routing tree (used to get net delays * - * incrementally during routing, as pieces are being added). * - * u.child_list: Pointer to a linked list of linked_rt_edge. Each one of * - * the linked list entries gives a child of this node. * - * u.next: Used only when this node is on the free list. Gives the next * - * node on the free list. * - * parent_node: Pointer to the rt_node that is this node's parent (used to * - * make bottom to top traversals). * - * re_expand: (really boolean). Should this node be put on the heap as * - * part of the partial routing to act as a source for subsequent * - * connections? TRUE->yes, FALSE-> no. * - * parent_switch: Index of the switch type driving this node (by its * - * parent). * - * inode: index (ID) of the rr_node that corresponds to this rt_node. * - * C_downstream: Total downstream capacitance from this rt_node. That is, * - * the total C of the subtree rooted at the current node, * - * including the C of the current node. * - * R_upstream: Total upstream resistance from this rt_node to the net * - * source, including any rr_node[].R of this node. * - * Tdel: Time delay for the signal to get from the net source to this node. * - * Includes the time to go through this node. */ - -/**************** Subroutines exported by route_tree_timing.c ***************/ - -void alloc_route_tree_timing_structs(void); - -void free_route_tree_timing_structs(void); - -t_rt_node *init_route_tree_to_source(int inet); - -void free_route_tree(t_rt_node * rt_node); - -t_rt_node *update_route_tree(struct s_heap *hptr); - -void update_net_delays_from_route_tree(float *net_delay, - t_rt_node ** rt_node_of_sink, int inet); diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph.c b/vpr7_x2p/vpr/SRC/route/rr_graph.c deleted file mode 100755 index c637473a4..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph.c +++ /dev/null @@ -1,2978 +0,0 @@ -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "rr_graph_sbox.h" -#include "check_rr_graph.h" -#include "rr_graph_timing_params.h" -#include "rr_graph_indexed_data.h" -#include "vpr_utils.h" -#include "read_xml_arch_file.h" -#include "ReadOptions.h" - -#include "tileable_rr_graph_builder.h" -#include "rr_graph_builder_utils.h" - -/* Xifan TANG: SWSEG SUPPORT */ -#include "rr_graph_swseg.h" -/* end */ -/* Xifan TANG: opin_to_cb support */ -#include "rr_graph_opincb.h" -/* end */ - -/* mrFPGA: Xifan TANG */ -#include "mrfpga_globals.h" -/* end */ - -/* #define ENABLE_DUMP */ -/* #define MUX_SIZE_DIST_DISPLAY */ - -/* mux size statistic data structures */ - -typedef struct s_mux { - int size; - struct s_mux *next; -} t_mux; - -typedef struct s_mux_size_distribution { - int mux_count; - int max_index; - int *distr; - struct s_mux_size_distribution *next; -} t_mux_size_distribution; - -/* -typedef struct s_clb_to_clb_directs { - t_type_descriptor *from_clb_type; - int from_clb_pin_start_index; - int from_clb_pin_end_index; - t_type_descriptor *to_clb_type; - int to_clb_pin_start_index; - int to_clb_pin_end_index; -} t_clb_to_clb_directs; -*/ - -/* Xifan TANG: opin_to_cb support */ -#include "pb_pin_eq_auto_detect.h" -/* end */ - -/* UDSD Modifications by WMF End */ - -/******************* Variables local to this module. ***********************/ - -/* Used to free "chunked" memory. If NULL, no rr_graph exists right now. */ -static t_chunk rr_mem_ch = {NULL, 0, NULL}; - -/* Status of current chunk being dished out by calls to my_chunk_malloc. */ - -/********************* Subroutines local to this module. *******************/ - -static void build_bidir_rr_opins(INP int i, INP int j, - INOUTP t_rr_node * L_rr_node, INP t_ivec *** L_rr_node_indices, - INP int *****opin_to_track_map, INP int **Fc_out, - INP boolean * L_rr_edge_done, INP t_seg_details * seg_details, - INP struct s_grid_tile **L_grid, INP int delayless_switch, - INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs); - -static void build_unidir_rr_opins(INP int i, INP int j, - INP struct s_grid_tile **L_grid, INP int **Fc_out, - INP int nodes_per_chan, INP t_seg_details * seg_details, - INOUTP int **Fc_xofs, INOUTP int **Fc_yofs, - INOUTP t_rr_node * L_rr_node, INOUTP boolean * L_rr_edge_done, - OUTP boolean * Fc_clipped, INP t_ivec *** L_rr_node_indices, INP int delayless_switch, - INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs); - -static int get_opin_direct_connecions(int x, int y, int opin, INOUTP t_linked_edge ** edge_list_ptr, INP t_ivec *** L_rr_node_indices, - INP int delayless_switch, INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs); - -static void alloc_and_load_rr_graph(INP int num_nodes, - INP t_rr_node * L_rr_node, INP int num_seg_types, - INP t_seg_details * seg_details, INP boolean * L_rr_edge_done, - INP struct s_ivec ****track_to_ipin_lookup, - INP int *****opin_to_track_map, INP struct s_ivec ***switch_block_conn, - INP struct s_grid_tile **L_grid, INP int L_nx, INP int L_ny, INP int Fs, - INP short *****sblock_pattern, INP int **Fc_out, INP int **Fc_xofs, - INP int **Fc_yofs, INP t_ivec *** L_rr_node_indices, - INP int nodes_per_chan, INP enum e_switch_block_type sb_type, - INP int delayless_switch, INP enum e_directionality directionality, - INP int wire_to_ipin_switch, OUTP boolean * Fc_clipped, INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs); - -static void load_uniform_switch_pattern(INP t_type_ptr type, - INOUTP int ****tracks_connected_to_pin, INP int num_phys_pins, - INP int *pin_num_ordering, INP int *side_ordering, - INP int *offset_ordering, INP int nodes_per_chan, INP int Fc, - INP enum e_directionality directionality); - -static void load_perturbed_switch_pattern(INP t_type_ptr type, - INOUTP int ****tracks_connected_to_pin, INP int num_phys_pins, - INP int *pin_num_ordering, INP int *side_ordering, - INP int *offset_ordering, INP int nodes_per_chan, INP int Fc, - INP enum e_directionality directionality); - -static void check_all_tracks_reach_pins(t_type_ptr type, - int ****tracks_connected_to_pin, int nodes_per_chan, int Fc, - enum e_pin_type ipin_or_opin); - -static void build_rr_sinks_sources(INP int i, INP int j, - INP t_rr_node * L_rr_node, INP t_ivec *** L_rr_node_indices, - INP int delayless_switch, INP struct s_grid_tile **L_grid); - -static void build_rr_xchan(INP int i, INP int j, - INP struct s_ivec ****track_to_ipin_lookup, - INP struct s_ivec ***switch_block_conn, INP int cost_index_offset, - INP int nodes_per_chan, INP int *opin_mux_size, - INP short *****sblock_pattern, INP int Fs_per_side, - INP t_seg_details * seg_details, INP t_ivec *** L_rr_node_indices, - INP boolean * L_rr_edge_done, INOUTP t_rr_node * L_rr_node, - INP int wire_to_ipin_switch, INP enum e_directionality directionality); - -static void build_rr_ychan(INP int i, INP int j, - INP struct s_ivec ****track_to_ipin_lookup, - INP struct s_ivec ***switch_block_conn, INP int cost_index_offset, - INP int nodes_per_chan, INP int *opin_mux_size, - INP short *****sblock_pattern, INP int Fs_per_side, - INP t_seg_details * seg_details, INP t_ivec *** L_rr_node_indices, - INP boolean * L_rr_edge_done, INOUTP t_rr_node * L_rr_node, - INP int wire_to_ipin_switch, INP enum e_directionality directionality); - - -void alloc_and_load_edges_and_switches(INP t_rr_node * L_rr_node, INP int inode, - INP int num_edges, INP boolean * L_rr_edge_done, - INP t_linked_edge * edge_list_head); - -static void alloc_net_rr_terminals(void); - -static void alloc_and_load_rr_clb_source(t_ivec *** L_rr_node_indices); - -/* -static t_clb_to_clb_directs *alloc_and_load_clb_to_clb_directs(INP t_direct_inf *directs, INP int num_directs); -*/ - -#if 0 -static void load_uniform_opin_switch_pattern_paired(INP int *Fc_out, - INP int num_pins, - INP int *pins_in_chan_seg, - INP int num_wire_inc_muxes, - INP int num_wire_dec_muxes, - INP int *wire_inc_muxes, - INP int *wire_dec_muxes, - INOUTP t_rr_node * L_rr_node, - INOUTP boolean * - L_rr_edge_done, - INP t_seg_details * - seg_details, - OUTP boolean * Fc_clipped); -#endif -void watch_edges(int inode, t_linked_edge * edge_list_head); -#if MUX_SIZE_DIST_DISPLAY -static void view_mux_size_distribution(t_ivec *** L_rr_node_indices, - int nodes_per_chan, - t_seg_details * seg_details_x, - t_seg_details * seg_details_y); -static void print_distribution(FILE * fptr, - t_mux_size_distribution * distr_struct); -#endif - - -static t_seg_details *alloc_and_load_global_route_seg_details( - INP int nodes_per_chan, INP int global_route_switch); - -static -void build_classic_rr_graph(INP t_graph_type graph_type, INP int L_num_types, - INP t_type_ptr types, INP int L_nx, INP int L_ny, - INP struct s_grid_tile **L_grid, INP int chan_width, - INP struct s_chan_width_dist *chan_capacity_inf, - INP enum e_switch_block_type sb_type, INP int Fs, INP int num_seg_types, - INP int num_switches, INP t_segment_inf * segment_inf, - INP int global_route_switch, INP int delayless_switch, - INP t_timing_inf timing_inf, INP int wire_to_ipin_switch, - INP enum e_base_cost_type base_cost_type, INP t_direct_inf *directs, - INP int num_directs, INP boolean ignore_Fc_0, OUTP int *Warnings, - /*Xifan TANG: Switch Segment Pattern Support*/ - INP int num_swseg_pattern, INP t_swseg_pattern_inf* swseg_patterns, - INP boolean opin_to_cb_fast_edges, INP boolean opin_logic_eq_edges); - - -/* UDSD Modifications by WMF End */ - -/******************* Subroutine definitions *******************************/ - -/************************************************************************* - * Top-level function of rr_graph builder - * Xifan TANG: this top function can branch between tileable rr_graph generator - * and the classical rr_graph generator - ************************************************************************/ -void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types, - INP t_type_ptr types, INP int L_nx, INP int L_ny, - INP struct s_grid_tile **L_grid, INP int chan_width, - INP struct s_chan_width_dist *chan_capacity_inf, - INP enum e_switch_block_type sb_type, INP int Fs, - INP enum e_switch_block_type sb_sub_type, INP int sub_Fs, INP boolean wire_opposite_side, - INP int num_seg_types, - INP int num_switches, INP t_segment_inf * segment_inf, - INP int global_route_switch, INP int delayless_switch, - INP t_timing_inf timing_inf, INP int wire_to_ipin_switch, - INP enum e_base_cost_type base_cost_type, INP t_direct_inf *directs, - INP int num_directs, INP boolean ignore_Fc_0, OUTP int *Warnings, - /*Xifan TANG: Switch Segment Pattern Support*/ - INP int num_swseg_pattern, INP t_swseg_pattern_inf* swseg_patterns, - INP boolean opin_to_cb_fast_edges, INP boolean opin_logic_eq_edges) { - /* Branch here */ - if (GRAPH_UNIDIR_TILEABLE == graph_type) { - build_tileable_unidir_rr_graph(L_num_types, types, - L_nx, L_ny, L_grid, - chan_width, - sb_type, Fs, - sb_sub_type, sub_Fs, wire_opposite_side, - num_seg_types, segment_inf, - num_switches, delayless_switch, - timing_inf, wire_to_ipin_switch, - base_cost_type, directs, num_directs, ignore_Fc_0, Warnings); - } else { - build_classic_rr_graph(graph_type, L_num_types, types, - L_nx, L_ny, L_grid, - chan_width, chan_capacity_inf, - sb_type, Fs, num_seg_types, num_switches, segment_inf, - global_route_switch, delayless_switch, - timing_inf, wire_to_ipin_switch, - base_cost_type, directs, num_directs, ignore_Fc_0, Warnings, - num_swseg_pattern, swseg_patterns, - opin_to_cb_fast_edges, opin_logic_eq_edges); - - } - - /* Print statistics of RR graph */ - print_rr_graph_stats(); - - return; -} - - -/* Xifan TANG: I rename the classical rr_graph builder here. - * We can have a clean build_rr_graph top function, - * where we branch for tileable routing and classical */ -static -void build_classic_rr_graph(INP t_graph_type graph_type, INP int L_num_types, - INP t_type_ptr types, INP int L_nx, INP int L_ny, - INP struct s_grid_tile **L_grid, INP int chan_width, - INP struct s_chan_width_dist *chan_capacity_inf, - INP enum e_switch_block_type sb_type, INP int Fs, INP int num_seg_types, - INP int num_switches, INP t_segment_inf * segment_inf, - INP int global_route_switch, INP int delayless_switch, - INP t_timing_inf timing_inf, INP int wire_to_ipin_switch, - INP enum e_base_cost_type base_cost_type, INP t_direct_inf *directs, - INP int num_directs, INP boolean ignore_Fc_0, OUTP int *Warnings, - /*Xifan TANG: Switch Segment Pattern Support*/ - INP int num_swseg_pattern, INP t_swseg_pattern_inf* swseg_patterns, - INP boolean opin_to_cb_fast_edges, INP boolean opin_logic_eq_edges) { - - /* Temp structures used to build graph */ - int nodes_per_chan, i, j; - t_seg_details *seg_details = NULL; - int **Fc_in = NULL; /* [0..num_types-1][0..num_pins-1] */ - int **Fc_out = NULL; /* [0..num_types-1][0..num_pins-1] */ - - int *****opin_to_track_map = NULL; /* [0..num_types-1][0..num_pins-1][0..height][0..3][0..Fc-1] */ - int *****ipin_to_track_map = NULL; /* [0..num_types-1][0..num_pins-1][0..height][0..3][0..Fc-1] */ - t_ivec ****track_to_ipin_lookup = NULL; /* [0..num_types-1][0..nodes_per_chan-1][0..height][0..3] */ - t_ivec ***switch_block_conn = NULL; - short *****unidir_sb_pattern = NULL; - boolean *L_rr_edge_done = NULL; - boolean is_global_graph; - boolean Fc_clipped; - boolean use_full_seg_groups; - boolean *perturb_ipins = NULL; - enum e_directionality directionality; - int **Fc_xofs = NULL; /* [0..ny-1][0..nx-1] */ - int **Fc_yofs = NULL; /* [0..nx-1][0..ny-1] */ - t_clb_to_clb_directs *clb_to_clb_directs; - - rr_node_indices = NULL; - rr_node = NULL; - num_rr_nodes = 0; - - /* Reset warning flag */ - *Warnings = RR_GRAPH_NO_WARN; - - /* Decode the graph_type */ - is_global_graph = FALSE; - if (GRAPH_GLOBAL == graph_type) { - is_global_graph = TRUE; - } - use_full_seg_groups = FALSE; - if (GRAPH_UNIDIR_TILEABLE == graph_type) { - use_full_seg_groups = TRUE; - } - directionality = UNI_DIRECTIONAL; - if (GRAPH_BIDIR == graph_type) { - directionality = BI_DIRECTIONAL; - } - if (is_global_graph) { - directionality = BI_DIRECTIONAL; - } - - /* Global routing uses a single longwire track */ - nodes_per_chan = (is_global_graph ? 1 : chan_width); - assert(nodes_per_chan > 0); - - clb_to_clb_directs = NULL; - if(num_directs > 0) { - clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, num_directs); - } - - /* START SEG_DETAILS */ - if (is_global_graph) { - /* Sets up a single unit length segment type for global routing. */ - seg_details = alloc_and_load_global_route_seg_details(nodes_per_chan, - global_route_switch); - } else { - /* Setup segments including distrubuting tracks and staggering. - * If use_full_seg_groups is specified, nodes_per_chan may be - * changed. Warning should be singled to caller if this happens. */ - seg_details = alloc_and_load_seg_details(&nodes_per_chan, - /* std::max(L_nx, L_ny), */ /* Original VPR */ - std::max(L_nx, L_ny) + ( is_stack ? 1 : 0 ), /* mrFPGA: Xifan TANG */ - num_seg_types, segment_inf, - use_full_seg_groups, is_global_graph, directionality); - if ((is_global_graph ? 1 : chan_width) != nodes_per_chan) { - *Warnings |= RR_GRAPH_WARN_CHAN_WIDTH_CHANGED; - } - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_SEG_DETAILS)) { - dump_seg_details(seg_details, nodes_per_chan, - getEchoFileName(E_ECHO_SEG_DETAILS)); - } - } - /* END SEG_DETAILS */ - - /* START FC */ - /* Determine the actual value of Fc */ - if (is_global_graph) { - Fc_in = (int **) my_malloc(sizeof(int) * L_num_types); - Fc_out = (int **) my_malloc(sizeof(int) * L_num_types); - for (i = 0; i < L_num_types; ++i) { - for (j = 0; j < types[i].num_pins; ++j) { - Fc_in[i][j] = 1; - Fc_out[i][j] = 1; - } - } - } else { - Fc_clipped = FALSE; - Fc_in = alloc_and_load_actual_fc(L_num_types, types, nodes_per_chan, - FALSE, directionality, &Fc_clipped, ignore_Fc_0); - if (Fc_clipped) { - *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; - } - Fc_clipped = FALSE; - Fc_out = alloc_and_load_actual_fc(L_num_types, types, nodes_per_chan, - TRUE, directionality, &Fc_clipped, ignore_Fc_0); - if (Fc_clipped) { - *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; - } - -#ifdef VERBOSE - for (i = 1; i < L_num_types; ++i) { /* Skip "" */ - for (j = 0; j < type_descriptors[i].num_pins; ++j) { - if (type_descriptors[i].is_Fc_full_flex[j]) { - vpr_printf(TIO_MESSAGE_INFO, "Fc Actual Values: type = %s, Fc_out = full, Fc_in = %d.\n", - type_descriptors[i].name, Fc_in[i][j]); - } - else { - vpr_printf(TIO_MESSAGE_INFO, "Fc Actual Values: type = %s, Fc_out = %d, Fc_in = %d.\n", - type_descriptors[i].name, Fc_out[i][j], Fc_in[i][j]); - } - } - } -#endif /* VERBOSE */ - } - - perturb_ipins = alloc_and_load_perturb_ipins(nodes_per_chan, L_num_types, - Fc_in, Fc_out, directionality); - /* END FC */ - - /* Alloc node lookups, count nodes, alloc rr nodes */ - num_rr_nodes = 0; - rr_node_indices = alloc_and_load_rr_node_indices(nodes_per_chan, L_nx, L_ny, - &num_rr_nodes, seg_details); - rr_node = (t_rr_node *) my_malloc(sizeof(t_rr_node) * num_rr_nodes); - memset(rr_node, 0, sizeof(t_rr_node) * num_rr_nodes); - L_rr_edge_done = (boolean *) my_malloc(sizeof(boolean) * num_rr_nodes); - memset(L_rr_edge_done, 0, sizeof(boolean) * num_rr_nodes); - - /* These are data structures used by the the unidir opin mapping. */ - if (UNI_DIRECTIONAL == directionality) { - Fc_xofs = (int **) alloc_matrix(0, L_ny, 0, L_nx, sizeof(int)); - Fc_yofs = (int **) alloc_matrix(0, L_nx, 0, L_ny, sizeof(int)); - for (i = 0; i <= L_nx; ++i) { - for (j = 0; j <= L_ny; ++j) { - Fc_xofs[j][i] = 0; - Fc_yofs[i][j] = 0; - } - } - } - - /* START SB LOOKUP */ - /* Alloc and load the switch block lookup */ - if (is_global_graph) { - assert(nodes_per_chan == 1); - switch_block_conn = alloc_and_load_switch_block_conn(1, SUBSET, 3); - } else if (BI_DIRECTIONAL == directionality) { - switch_block_conn = alloc_and_load_switch_block_conn(nodes_per_chan, - sb_type, Fs); - } else { - assert(UNI_DIRECTIONAL == directionality); - - unidir_sb_pattern = alloc_sblock_pattern_lookup(L_nx, L_ny, - nodes_per_chan); - for (i = 0; i <= L_nx; i++) { - for (j = 0; j <= L_ny; j++) { - load_sblock_pattern_lookup(i, j, nodes_per_chan, seg_details, - Fs, sb_type, unidir_sb_pattern); - } - } - } - /* END SB LOOKUP */ - - /* START IPINP MAP */ - /* Create ipin map lookups */ - ipin_to_track_map = (int *****) my_malloc(sizeof(int ****) * L_num_types); - track_to_ipin_lookup = (struct s_ivec ****) my_malloc( - sizeof(struct s_ivec ***) * L_num_types); - for (i = 0; i < L_num_types; ++i) { - ipin_to_track_map[i] = alloc_and_load_pin_to_track_map(RECEIVER, - nodes_per_chan, Fc_in[i], &types[i], perturb_ipins[i], - directionality); - track_to_ipin_lookup[i] = alloc_and_load_track_to_pin_lookup( - ipin_to_track_map[i], Fc_in[i], types[i].height, - types[i].num_pins, nodes_per_chan); - } - /* END IPINP MAP */ - - /* START OPINP MAP */ - /* Create opin map lookups */ - if (BI_DIRECTIONAL == directionality) { - opin_to_track_map = (int *****) my_malloc( - sizeof(int ****) * L_num_types); - for (i = 0; i < L_num_types; ++i) { - opin_to_track_map[i] = alloc_and_load_pin_to_track_map(DRIVER, - nodes_per_chan, Fc_out[i], &types[i], FALSE, directionality); - } - } - /* END OPINP MAP */ - - /* UDSD Modifications by WMF begin */ - /* I'm adding 2 new fields to t_rr_node, and I want them initialized to 0. */ - for (i = 0; i < num_rr_nodes; i++) { - rr_node[i].num_wire_drivers = 0; - rr_node[i].num_opin_drivers = 0; - } - - alloc_and_load_rr_graph(num_rr_nodes, rr_node, num_seg_types, seg_details, - L_rr_edge_done, track_to_ipin_lookup, opin_to_track_map, - switch_block_conn, L_grid, L_nx, L_ny, Fs, unidir_sb_pattern, - Fc_out, Fc_xofs, Fc_yofs, rr_node_indices, nodes_per_chan, sb_type, - delayless_switch, directionality, wire_to_ipin_switch, &Fc_clipped, directs, num_directs, clb_to_clb_directs); - -#ifdef MUX_SIZE_DIST_DISPLAY - if (UNI_DIRECTIONAL == directionality) - { - view_mux_size_distribution(rr_node_indices, nodes_per_chan, - seg_details, seg_details); - } -#endif - - /* Update rr_nodes capacities if global routing */ - if (graph_type == GRAPH_GLOBAL) { - for (i = 0; i < num_rr_nodes; i++) { - if (rr_node[i].type == CHANX || rr_node[i].type == CHANY) { - rr_node[i].capacity = chan_width; - } - } - } - - /* Xifan TANG: Add Fast Interconnection from LB OPINs to adjacent LB IPINs*/ - if (TRUE == opin_to_cb_fast_edges) { // Do only detailed rr_graph is needed - vpr_printf(TIO_MESSAGE_INFO,"Adding %d fast edges from logic block OPIN to logic block IPIN ...\n", - add_rr_graph_fast_edge_opin_to_cb(rr_node_indices)); - } - /*END*/ - - /*Xifan TANG: Switch Segment Pattern Support*/ - if (NULL != swseg_patterns) { // Do only the pointer is not NULL - vpr_printf(TIO_MESSAGE_INFO,"Applying Switch Segment Pattern...\n"); - if (UNI_DIRECTIONAL == directionality) { - add_rr_graph_switch_segment_pattern(directionality,nodes_per_chan, num_swseg_pattern, swseg_patterns, rr_node_indices, seg_details, seg_details); - } else { - vpr_printf(TIO_MESSAGE_ERROR,"Switch Segment Pattern is only applicable to uni-directional routing architecture!\n"); - exit(1); - } - } - /*END*/ - - /* Xifan TANG: Check logic equivalence of LB OPINs and IPINs. Then modify the associated rr_graph */ - /* use net_rr_terminal array to find SOURCE rr_node for each net*/ - if (TRUE == opin_logic_eq_edges) { // Do only detailed rr_graph is needed - vpr_printf(TIO_MESSAGE_INFO,"Adding %d logic equivalent edges for logic block OPIN ...\n", - // alloc_and_add_grids_fully_capacity_sb_rr_edges(rr_node_indices, num_directs, clb_to_clb_directs)); - alloc_and_add_grids_fully_capacity_rr_edges(rr_node_indices, num_directs, clb_to_clb_directs)); - } - /*END*/ - - rr_graph_externals(timing_inf, segment_inf, num_seg_types, nodes_per_chan, - wire_to_ipin_switch, base_cost_type); - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_RR_GRAPH)) { - dump_rr_graph(getEchoFileName(E_ECHO_RR_GRAPH)); - } else - ; - - check_rr_graph(graph_type, L_nx, L_ny, - num_switches, Fc_in); - - /* Free all temp structs */ - if (seg_details) { - free_seg_details(seg_details, nodes_per_chan); - seg_details = NULL; - } - if (Fc_in) { - free_matrix(Fc_in,0, L_num_types, 0, sizeof(int)); - Fc_in = NULL; - } - if (Fc_out) { - free_matrix(Fc_out,0, L_num_types, 0, sizeof(int)); - Fc_out = NULL; - } - if (perturb_ipins) { - free(perturb_ipins); - perturb_ipins = NULL; - } - if (switch_block_conn) { - free_switch_block_conn(switch_block_conn, nodes_per_chan); - switch_block_conn = NULL; - } - if (L_rr_edge_done) { - free(L_rr_edge_done); - L_rr_edge_done = NULL; - } - if (Fc_xofs) { - free_matrix(Fc_xofs, 0, L_ny, 0, sizeof(int)); - Fc_xofs = NULL; - } - if (Fc_yofs) { - free_matrix(Fc_yofs, 0, L_nx, 0, sizeof(int)); - Fc_yofs = NULL; - } - if (unidir_sb_pattern) { - free_sblock_pattern_lookup(unidir_sb_pattern); - unidir_sb_pattern = NULL; - } - if (opin_to_track_map) { - for (i = 0; i < L_num_types; ++i) { - free_matrix4(opin_to_track_map[i], 0, types[i].num_pins - 1, 0, - types[i].height - 1, 0, 3, 0, sizeof(int)); - } - free(opin_to_track_map); - } - - free_type_pin_to_track_map(ipin_to_track_map, types); - free_type_track_to_ipin_map(track_to_ipin_lookup, types, nodes_per_chan); - if(clb_to_clb_directs != NULL) { - free(clb_to_clb_directs); - } -} - -void rr_graph_externals(const t_timing_inf timing_inf, - const t_segment_inf * segment_inf, const int num_seg_types, const int nodes_per_chan, - const int wire_to_ipin_switch, const enum e_base_cost_type base_cost_type) { - add_rr_graph_C_from_switches(timing_inf.C_ipin_cblock); - alloc_and_load_rr_indexed_data(segment_inf, num_seg_types, rr_node_indices, - nodes_per_chan, wire_to_ipin_switch, base_cost_type); - - alloc_net_rr_terminals(); - load_net_rr_terminals(rr_node_indices); - alloc_and_load_rr_clb_source(rr_node_indices); -} - -boolean * -alloc_and_load_perturb_ipins(INP int nodes_per_chan, INP int L_num_types, - INP int **Fc_in, INP int **Fc_out, INP enum e_directionality directionality) { - int i; - float Fc_ratio; - boolean *result = NULL; - - result = (boolean *) my_malloc(L_num_types * sizeof(boolean)); - - if (BI_DIRECTIONAL == directionality) { - result[0] = FALSE; - for (i = 1; i < L_num_types; ++i) { - result[i] = FALSE; - - if (Fc_in[i][0] > Fc_out[i][0]) { - Fc_ratio = (float) Fc_in[i][0] / (float) Fc_out[i][0]; - } else { - Fc_ratio = (float) Fc_out[i][0] / (float) Fc_in[i][0]; - } - - if ((Fc_in[i][0] <= nodes_per_chan - 2) - && (fabs(Fc_ratio - nint(Fc_ratio)) - < (0.5 / (float) nodes_per_chan))) { - result[i] = TRUE; - } - } - } else { - /* Unidirectional routing uses mux balancing patterns and - * thus shouldn't need perturbation. */ - assert(UNI_DIRECTIONAL == directionality); - for (i = 0; i < L_num_types; ++i) { - result[i] = FALSE; - } - } - - return result; -} - -static t_seg_details * -alloc_and_load_global_route_seg_details(INP int nodes_per_chan, - INP int global_route_switch) { - t_seg_details *result = NULL; - - assert(nodes_per_chan == 1); - result = (t_seg_details *) my_malloc(sizeof(t_seg_details)); - - result->index = 0; - result->length = 1; - result->wire_switch = global_route_switch; - result->opin_switch = global_route_switch; - result->longline = FALSE; - result->direction = BI_DIRECTION; - result->Cmetal = 0.0; - result->Rmetal = 0.0; - result->start = 1; - result->drivers = MULTI_BUFFERED; - result->cb = (boolean *) my_malloc(sizeof(boolean) * 1); - result->cb[0] = TRUE; - result->sb = (boolean *) my_malloc(sizeof(boolean) * 2); - result->sb[0] = TRUE; - result->sb[1] = TRUE; - result->group_size = 1; - result->group_start = 0; - - return result; -} - -/* Calculates the actual Fc values for the given nodes_per_chan value */ -int ** -alloc_and_load_actual_fc(INP int L_num_types, INP t_type_ptr types, - INP int nodes_per_chan, INP boolean is_Fc_out, - INP enum e_directionality directionality, OUTP boolean * Fc_clipped, INP boolean ignore_Fc_0) { - - int i, j; - int **Result = NULL; - int fac, num_sets; - - *Fc_clipped = FALSE; - - /* Unidir tracks formed in pairs, otherwise no effect. */ - fac = 1; - if (UNI_DIRECTIONAL == directionality) { - fac = 2; - } - - assert((nodes_per_chan % fac) == 0); - num_sets = nodes_per_chan / fac; - - int max_pins = types[0].num_pins; - for (i = 1; i < L_num_types; ++i) { - if (types[i].num_pins > max_pins) { - max_pins = types[i].num_pins; - } - } - - Result = (int **) alloc_matrix(0, L_num_types, 0, max_pins, sizeof(int)); - - for (i = 1; i < L_num_types; ++i) { - float *Fc = (float *) my_malloc(sizeof(float) * types[i].num_pins); /* [0..num_pins-1] */ - for (j = 0; j < types[i].num_pins; ++j) { - Fc[j] = types[i].Fc[j]; - - /* Xifan Tang: give an initial value! */ - Result[i][j] = -1; - - if(Fc[j] == 0 && ignore_Fc_0 == FALSE) { - /* Special case indicating that this pin does not connect to general-purpose routing */ - Result[i][j] = 0; - } else { - /* General case indicating that this pin connects to general-purpose routing */ - if (types[i].is_Fc_frac[j]) { - Result[i][j] = fac * nint(num_sets * Fc[j]); - } else { - Result[i][j] = (int)Fc[j]; - } - - if (is_Fc_out && types[i].is_Fc_full_flex[j]) { - Result[i][j] = nodes_per_chan; - } - - Result[i][j] = std::max(Result[i][j], fac); - if (Result[i][j] > nodes_per_chan) { - *Fc_clipped = TRUE; - Result[i][j] = nodes_per_chan; - } - } - assert(Result[i][j] % fac == 0); - } - free(Fc); - } - - return Result; -} - -/* frees the track to ipin mapping for each physical grid type */ -void free_type_track_to_ipin_map(struct s_ivec**** track_to_pin_map, - t_type_ptr types, int nodes_per_chan) { - int i, itrack, ioff, iside; - for (i = 0; i < num_types; i++) { - if (track_to_pin_map[i] != NULL) { - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - for (ioff = 0; ioff < types[i].height; ioff++) { - for (iside = 0; iside < 4; iside++) { - if (track_to_pin_map[i][itrack][ioff][iside].list - != NULL) { - free(track_to_pin_map[i][itrack][ioff][iside].list); - } - } - } - } - free_matrix3(track_to_pin_map[i], 0, nodes_per_chan - 1, 0, - types[i].height - 1, 0, sizeof(struct s_ivec)); - } - } - free(track_to_pin_map); -} - -/* frees the ipin to track mapping for each physical grid type */ -void free_type_pin_to_track_map(int***** ipin_to_track_map, - t_type_ptr types) { - int i; - for (i = 0; i < num_types; i++) { - free_matrix4(ipin_to_track_map[i], 0, types[i].num_pins - 1, 0, - types[i].height - 1, 0, 3, 0, sizeof(int)); - } - free(ipin_to_track_map); -} - -/* Does the actual work of allocating the rr_graph and filling all the * - * appropriate values. Everything up to this was just a prelude! */ -static void alloc_and_load_rr_graph(INP int num_nodes, - INP t_rr_node * L_rr_node, INP int num_seg_types, - INP t_seg_details * seg_details, INP boolean * L_rr_edge_done, - INP struct s_ivec ****track_to_ipin_lookup, - INP int *****opin_to_track_map, INP struct s_ivec ***switch_block_conn, - INP struct s_grid_tile **L_grid, INP int L_nx, INP int L_ny, INP int Fs, - INP short *****sblock_pattern, INP int **Fc_out, INP int **Fc_xofs, - INP int **Fc_yofs, INP t_ivec *** L_rr_node_indices, - INP int nodes_per_chan, INP enum e_switch_block_type sb_type, - INP int delayless_switch, INP enum e_directionality directionality, - INP int wire_to_ipin_switch, OUTP boolean * Fc_clipped, - INP t_direct_inf *directs, INP int num_directs, - INP t_clb_to_clb_directs *clb_to_clb_directs) { - - int i, j; - boolean clipped; - int *opin_mux_size = NULL; - - /* If Fc gets clipped, this will be flagged to true */ - *Fc_clipped = FALSE; - - /* Connection SINKS and SOURCES to their pins. */ - for (i = 0; i <= (L_nx + 1); i++) { - for (j = 0; j <= (L_ny + 1); j++) { - build_rr_sinks_sources(i, j, L_rr_node, L_rr_node_indices, - delayless_switch, L_grid); - } - } - - /* Build opins */ - for (i = 0; i <= (L_nx + 1); ++i) { - for (j = 0; j <= (L_ny + 1); ++j) { - if (BI_DIRECTIONAL == directionality) { - build_bidir_rr_opins(i, j, L_rr_node, L_rr_node_indices, - opin_to_track_map, Fc_out, L_rr_edge_done, seg_details, - L_grid, delayless_switch, - directs, num_directs, clb_to_clb_directs); - } else { - assert(UNI_DIRECTIONAL == directionality); - build_unidir_rr_opins(i, j, L_grid, Fc_out, nodes_per_chan, - seg_details, Fc_xofs, Fc_yofs, L_rr_node, - L_rr_edge_done, &clipped, L_rr_node_indices, delayless_switch, - directs, num_directs, clb_to_clb_directs); - if (clipped) { - *Fc_clipped = TRUE; - } - } - } - } - - /* We make a copy of the current fanin values for the nodes to - * know the number of OPINs driving each mux presently */ - opin_mux_size = (int *) my_malloc(sizeof(int) * num_nodes); - for (i = 0; i < num_nodes; ++i) { - opin_mux_size[i] = L_rr_node[i].fan_in; - } - - /* Build channels */ - assert(Fs % 3 == 0); - for (i = 0; i <= L_nx; i++) { - for (j = 0; j <= L_ny; j++) { - if (i > 0) { - build_rr_xchan(i, j, track_to_ipin_lookup, switch_block_conn, - CHANX_COST_INDEX_START, nodes_per_chan, opin_mux_size, - sblock_pattern, Fs / 3, seg_details, L_rr_node_indices, - L_rr_edge_done, L_rr_node, wire_to_ipin_switch, - directionality); - } - if (j > 0) { - build_rr_ychan(i, j, track_to_ipin_lookup, switch_block_conn, - CHANX_COST_INDEX_START + num_seg_types, nodes_per_chan, - opin_mux_size, sblock_pattern, Fs / 3, seg_details, - L_rr_node_indices, L_rr_edge_done, L_rr_node, - wire_to_ipin_switch, directionality); - } - } - } - free(opin_mux_size); -} - -static void build_bidir_rr_opins(INP int i, INP int j, - INOUTP t_rr_node * L_rr_node, INP t_ivec *** L_rr_node_indices, - INP int *****opin_to_track_map, INP int **Fc_out, - INP boolean * L_rr_edge_done, INP t_seg_details * seg_details, - INP struct s_grid_tile **L_grid, INP int delayless_switch, - INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs) { - - int ipin, inode, num_edges, *Fc, ofs; - t_type_ptr type; - struct s_linked_edge *edge_list, *next; - - /* OPINP edges need to be done at once so let the offset 0 - * block do the work. */ - if (L_grid[i][j].offset > 0) { - return; - } - - type = L_grid[i][j].type; - Fc = Fc_out[type->index]; - - for (ipin = 0; ipin < type->num_pins; ++ipin) { - /* We only are working with opins so skip non-drivers */ - if (type->class_inf[type->pin_class[ipin]].type != DRIVER) { - continue; - } - - num_edges = 0; - edge_list = NULL; - if(Fc[ipin] != 0) { - for (ofs = 0; ofs < type->height; ++ofs) { - num_edges += get_bidir_opin_connections(i, j + ofs, ipin, - &edge_list, opin_to_track_map, Fc[ipin], L_rr_edge_done, - L_rr_node_indices, seg_details); - } - } - - /* Add in direct connections */ - num_edges += get_opin_direct_connecions(i, j, ipin, &edge_list, L_rr_node_indices, delayless_switch, directs, num_directs, clb_to_clb_directs); - - inode = get_rr_node_index(i, j, OPIN, ipin, L_rr_node_indices); - alloc_and_load_edges_and_switches(L_rr_node, inode, num_edges, - L_rr_edge_done, edge_list); - while (edge_list != NULL) { - next = edge_list->next; - free(edge_list); - edge_list = next; - } - } -} - -void free_rr_graph(void) { - int i; - - /* Frees all the routing graph data structures, if they have been * - * allocated. I use rr_mem_chunk_list_head as a flag to indicate * - * whether or not the graph has been allocated -- if it is not NULL, * - * a routing graph exists and can be freed. Hence, you can call this * - * routine even if you're not sure of whether a rr_graph exists or not. */ - - if (rr_mem_ch.chunk_ptr_head == NULL) /* Nothing to free. */ - return; - - free_chunk_memory(&rr_mem_ch); /* Frees ALL "chunked" data */ - - /* Before adding any more free calls here, be sure the data is NOT chunk * - * allocated, as ALL the chunk allocated data is already free! */ - - if(net_rr_terminals != NULL) { - free(net_rr_terminals); - } - for (i = 0; i < num_rr_nodes; i++) { - if (rr_node[i].edges != NULL) { - free(rr_node[i].edges); - } - if (rr_node[i].switches != NULL) { - free(rr_node[i].switches); - } - } - - assert(rr_node_indices); - free_rr_node_indices(rr_node_indices); - free(rr_node); - free(rr_indexed_data); - for (i = 0; i < num_blocks; i++) { - free(rr_blk_source[i]); - } - free(rr_blk_source); - rr_blk_source = NULL; - net_rr_terminals = NULL; - rr_node = NULL; - rr_node_indices = NULL; - rr_indexed_data = NULL; - num_rr_nodes = 0; -} - -static void alloc_net_rr_terminals(void) { - int inet; - - net_rr_terminals = (int **) my_malloc(num_nets * sizeof(int *)); - - for (inet = 0; inet < num_nets; inet++) { - net_rr_terminals[inet] = (int *) my_chunk_malloc( - (clb_net[inet].num_sinks + 1) * sizeof(int), - &rr_mem_ch); - } -} - -void load_net_rr_terminals(t_ivec *** L_rr_node_indices) { - - /* Allocates and loads the net_rr_terminals data structure. For each net * - * it stores the rr_node index of the SOURCE of the net and all the SINKs * - * of the net. [0..num_nets-1][0..num_pins-1]. Entry [inet][pnum] stores * - * the rr index corresponding to the SOURCE (opin) or SINK (ipin) of pnum. */ - - int inet, ipin, inode, iblk, i, j, node_block_pin, iclass; - t_type_ptr type; - - for (inet = 0; inet < num_nets; inet++) { - for (ipin = 0; ipin <= clb_net[inet].num_sinks; ipin++) { - iblk = clb_net[inet].node_block[ipin]; - i = block[iblk].x; - j = block[iblk].y; - type = block[iblk].type; - - /* In the routing graph, each (x, y) location has unique pins on it - * so when there is capacity, blocks are packed and their pin numbers - * are offset to get their actual rr_node */ - node_block_pin = clb_net[inet].node_block_pin[ipin]; - - iclass = type->pin_class[node_block_pin]; - - inode = get_rr_node_index(i, j, (ipin == 0 ? SOURCE : SINK), /* First pin is driver */ - iclass, L_rr_node_indices); - net_rr_terminals[inet][ipin] = inode; - } - } -} - -static void alloc_and_load_rr_clb_source(t_ivec *** L_rr_node_indices) { - - /* Saves the rr_node corresponding to each SOURCE and SINK in each CLB * - * in the FPGA. Currently only the SOURCE rr_node values are used, and * - * they are used only to reserve pins for locally used OPINs in the router. * - * [0..num_blocks-1][0..num_class-1]. The values for blocks that are pads * - * are NOT valid. */ - - int iblk, i, j, iclass, inode; - int class_low, class_high; - t_rr_type rr_type; - t_type_ptr type; - - rr_blk_source = (int **) my_malloc(num_blocks * sizeof(int *)); - - for (iblk = 0; iblk < num_blocks; iblk++) { - type = block[iblk].type; - get_class_range_for_block(iblk, &class_low, &class_high); - rr_blk_source[iblk] = (int *) my_malloc(type->num_class * sizeof(int)); - for (iclass = 0; iclass < type->num_class; iclass++) { - if (iclass >= class_low && iclass <= class_high) { - i = block[iblk].x; - j = block[iblk].y; - - if (type->class_inf[iclass].type == DRIVER) - rr_type = SOURCE; - else - rr_type = SINK; - - inode = get_rr_node_index(i, j, rr_type, iclass, - L_rr_node_indices); - rr_blk_source[iblk][iclass] = inode; - } else { - rr_blk_source[iblk][iclass] = OPEN; - } - } - } -} - -static void build_rr_sinks_sources(INP int i, INP int j, - INP t_rr_node * L_rr_node, INP t_ivec *** L_rr_node_indices, - INP int delayless_switch, INP struct s_grid_tile **L_grid) { - - /* Loads IPIN, SINK, SOURCE, and OPIN. - * Loads IPINP to SINK edges, and SOURCE to OPINP edges */ - - int ipin, iclass, inode, pin_num, to_node, num_edges; - int num_class, num_pins; - t_type_ptr type; - struct s_class *class_inf; - int *pin_class; - const t_pb_graph_node *pb_graph_node; - int iport, ipb_pin, iporttype, z; - - /* Since we share nodes within a large block, only - * start tile can initialize sinks, sources, and pins */ - if (L_grid[i][j].offset > 0) - return; - - type = L_grid[i][j].type; - num_class = type->num_class; - class_inf = type->class_inf; - num_pins = type->num_pins; - pin_class = type->pin_class; - z = 0; - - /* SINKS and SOURCE to OPINP edges */ - for (iclass = 0; iclass < num_class; iclass++) { - if (class_inf[iclass].type == DRIVER) { /* SOURCE */ - inode = get_rr_node_index(i, j, SOURCE, iclass, L_rr_node_indices); - - num_edges = class_inf[iclass].num_pins; - L_rr_node[inode].num_edges = num_edges; - L_rr_node[inode].edges = (int *) my_malloc(num_edges * sizeof(int)); - L_rr_node[inode].switches = (short *) my_malloc( - num_edges * sizeof(short)); - - for (ipin = 0; ipin < class_inf[iclass].num_pins; ipin++) { - pin_num = class_inf[iclass].pinlist[ipin]; - to_node = get_rr_node_index(i, j, OPIN, pin_num, - L_rr_node_indices); - L_rr_node[inode].edges[ipin] = to_node; - L_rr_node[inode].switches[ipin] = delayless_switch; - - ++L_rr_node[to_node].fan_in; - } - - L_rr_node[inode].cost_index = SOURCE_COST_INDEX; - L_rr_node[inode].type = SOURCE; - } else { /* SINK */ - assert(class_inf[iclass].type == RECEIVER); - inode = get_rr_node_index(i, j, SINK, iclass, L_rr_node_indices); - - /* NOTE: To allow route throughs through clbs, change the lines below to * - * make an edge from the input SINK to the output SOURCE. Do for just the * - * special case of INPUTS = class 0 and OUTPUTS = class 1 and see what it * - * leads to. If route throughs are allowed, you may want to increase the * - * base cost of OPINs and/or SOURCES so they aren't used excessively. */ - - /* Initialize to unconnected to fix values */ - L_rr_node[inode].num_edges = 0; - L_rr_node[inode].edges = NULL; - L_rr_node[inode].switches = NULL; - - L_rr_node[inode].cost_index = SINK_COST_INDEX; - L_rr_node[inode].type = SINK; - } - - /* Things common to both SOURCEs and SINKs. */ - L_rr_node[inode].capacity = class_inf[iclass].num_pins; - L_rr_node[inode].occ = 0; - L_rr_node[inode].xlow = i; - L_rr_node[inode].xhigh = i; - L_rr_node[inode].ylow = j; - L_rr_node[inode].yhigh = j + type->height - 1; - L_rr_node[inode].R = 0; - L_rr_node[inode].C = 0; - L_rr_node[inode].ptc_num = iclass; - L_rr_node[inode].direction = (enum e_direction)OPEN; - L_rr_node[inode].drivers = (enum e_drivers)OPEN; - } - - iporttype = iport = ipb_pin = 0; - - pb_graph_node = type->pb_graph_head; - if(pb_graph_node != NULL && pb_graph_node->num_input_ports == 0) { - iporttype = 1; - } - /* Connect IPINS to SINKS and dummy for OPINS */ - for (ipin = 0; ipin < num_pins; ipin++) { - iclass = pin_class[ipin]; - z = ipin / (type->pb_type->num_clock_pins + type->pb_type->num_output_pins + type->pb_type->num_input_pins); - - if (class_inf[iclass].type == RECEIVER) { - inode = get_rr_node_index(i, j, IPIN, ipin, L_rr_node_indices); - to_node = get_rr_node_index(i, j, SINK, iclass, L_rr_node_indices); - - L_rr_node[inode].num_edges = 1; - L_rr_node[inode].edges = (int *) my_malloc(sizeof(int)); - L_rr_node[inode].switches = (short *) my_malloc(sizeof(short)); - - L_rr_node[inode].edges[0] = to_node; - L_rr_node[inode].switches[0] = delayless_switch; - - ++L_rr_node[to_node].fan_in; - - L_rr_node[inode].cost_index = IPIN_COST_INDEX; - L_rr_node[inode].type = IPIN; - - /* Add in information so that I can identify which cluster pin this rr_node connects to later */ - L_rr_node[inode].z = z; - if(iporttype == 0) { - L_rr_node[inode].pb_graph_pin = &pb_graph_node->input_pins[iport][ipb_pin]; - ipb_pin++; - if(ipb_pin >= pb_graph_node->num_input_pins[iport]) { - iport++; - ipb_pin = 0; - if(iport >= pb_graph_node->num_input_ports) { - iporttype++; - iport = 0; - if(pb_graph_node->num_clock_ports == 0) { - iporttype = 0; - } - } - } - } else { - assert(iporttype == 1); - L_rr_node[inode].pb_graph_pin = &pb_graph_node->clock_pins[iport][ipb_pin]; - ipb_pin++; /* Xifan TANG: Original VPR does not have this incremental!!! */ - if(ipb_pin >= pb_graph_node->num_clock_pins[iport]) { - iport++; - ipb_pin = 0; - if(iport >= pb_graph_node->num_clock_ports) { - iporttype = 0; - iport = 0; - if(pb_graph_node->num_input_ports == 0) { - iporttype = 1; - } - } - } - } - } else { - assert(class_inf[iclass].type == DRIVER); - - inode = get_rr_node_index(i, j, OPIN, ipin, L_rr_node_indices); - - /* Add in information so that I can identify which cluster pin this rr_node connects to later */ - L_rr_node[inode].z = z; - - L_rr_node[inode].num_edges = 0; - L_rr_node[inode].edges = NULL; - - L_rr_node[inode].switches = NULL; - - L_rr_node[inode].cost_index = OPIN_COST_INDEX; - L_rr_node[inode].type = OPIN; - - L_rr_node[inode].pb_graph_pin = &pb_graph_node->output_pins[iport][ipb_pin]; - ipb_pin++; /* Xifan TANG: Original VPR does not have this incremental!!! */ - if(ipb_pin >= pb_graph_node->num_output_pins[iport]) { - iport++; - ipb_pin = 0; - if(iport >= pb_graph_node->num_output_ports) { - iport = 0; - if(pb_graph_node->num_input_ports == 0) { - iporttype = 1; - } else { - iporttype = 0; - } - } - } - } - - /* Common to both DRIVERs and RECEIVERs */ - L_rr_node[inode].capacity = 1; - L_rr_node[inode].occ = 0; - L_rr_node[inode].xlow = i; - L_rr_node[inode].xhigh = i; - L_rr_node[inode].ylow = j; - L_rr_node[inode].yhigh = j + type->height - 1; - L_rr_node[inode].C = 0; - L_rr_node[inode].R = 0; - L_rr_node[inode].ptc_num = ipin; - L_rr_node[inode].direction = (enum e_direction)OPEN; - L_rr_node[inode].drivers = (enum e_drivers)OPEN; - } -} - -static void build_rr_xchan(INP int i, INP int j, - INP struct s_ivec ****track_to_ipin_lookup, - INP struct s_ivec ***switch_block_conn, INP int cost_index_offset, - INP int nodes_per_chan, INP int *opin_mux_size, - INP short *****sblock_pattern, INP int Fs_per_side, - INP t_seg_details * seg_details, INP t_ivec *** L_rr_node_indices, - INOUTP boolean * L_rr_edge_done, INOUTP t_rr_node * L_rr_node, - INP int wire_to_ipin_switch, INP enum e_directionality directionality) { - - /* Loads up all the routing resource nodes in the x-directed channel * - * segments starting at (i,j). */ - - int itrack, istart, iend, num_edges, inode, length; - struct s_linked_edge *edge_list, *next; - /* mrFPGA: Xifan TANG */ - int jstart, jend; - /* END */ - - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - /* First count number of edges and put the edges in a linked list. */ - num_edges = 0; - edge_list = NULL; - - /* mrFPGA : Xifan TANG*/ - if ( is_stack ) { - jstart = get_seg_start (seg_details, itrack, i, j); - if ( jstart != j ) - continue; - jend = get_seg_end (seg_details, itrack, jstart, i, ny); - - istart = i; - iend = i; - - num_edges += get_track_to_ipins(jstart, i, itrack, &edge_list, L_rr_node_indices, - track_to_ipin_lookup, seg_details, CHANX, nx, wire_to_ipin_switch, - directionality); - - num_edges += get_track_to_tracks(i, jstart, itrack, CHANX, i-1, CHANY, ny, - nodes_per_chan, opin_mux_size, Fs_per_side, sblock_pattern, - &edge_list, seg_details, directionality, L_rr_node_indices, - L_rr_edge_done, switch_block_conn); - - num_edges += get_track_to_tracks(i, jstart, itrack, CHANX, i, CHANY, ny, - nodes_per_chan, opin_mux_size, Fs_per_side, sblock_pattern, - &edge_list, seg_details, directionality, L_rr_node_indices, - L_rr_edge_done, switch_block_conn); - - if( jstart > 0 ) { - num_edges += get_track_to_tracks(i, jstart, itrack, CHANX, jstart - 1, CHANX, ny, - nodes_per_chan, opin_mux_size, Fs_per_side,sblock_pattern, &edge_list, - seg_details, directionality, L_rr_node_indices, L_rr_edge_done, switch_block_conn); - } - if( jend < ny ) { - num_edges += get_track_to_tracks(i, jstart, itrack, CHANX, jend + 1, CHANX, ny, - nodes_per_chan, opin_mux_size, Fs_per_side, sblock_pattern, &edge_list, - seg_details, directionality, L_rr_node_indices, L_rr_edge_done, switch_block_conn); - } - } else { /* end */ - /* Xifan TANG: I remove the accurate part for Original VPR*/ - /* Original VPR part*/ - istart = get_seg_start(seg_details, itrack, j, i); - iend = get_seg_end(seg_details, itrack, istart, j, nx); - if (i > istart) - continue; /* Not the start of this segment. */ - jstart = j; - jend = j; - /* end */ - - /* First count number of edges and put the edges in a linked list. */ - num_edges = 0; - edge_list = NULL; - - num_edges += get_track_to_ipins(istart, j, itrack, &edge_list, - L_rr_node_indices, track_to_ipin_lookup, seg_details, CHANX, nx, - wire_to_ipin_switch, directionality); - - if (j > 0) { - num_edges += get_track_to_tracks(j, istart, itrack, CHANX, j, CHANY, - nx, nodes_per_chan, opin_mux_size, Fs_per_side, - sblock_pattern, &edge_list, seg_details, directionality, - L_rr_node_indices, L_rr_edge_done, switch_block_conn); - } - - if (j < ny) { - num_edges += get_track_to_tracks(j, istart, itrack, CHANX, j + 1, - CHANY, nx, nodes_per_chan, opin_mux_size, Fs_per_side, - sblock_pattern, &edge_list, seg_details, directionality, - L_rr_node_indices, L_rr_edge_done, switch_block_conn); - } - - if (istart > 1) { - num_edges += get_track_to_tracks(j, istart, itrack, CHANX, - istart - 1, CHANX, nx, nodes_per_chan, opin_mux_size, - Fs_per_side, sblock_pattern, &edge_list, seg_details, - directionality, L_rr_node_indices, L_rr_edge_done, - switch_block_conn); - } - - if (iend < nx) { - num_edges += get_track_to_tracks(j, istart, itrack, CHANX, iend + 1, - CHANX, nx, nodes_per_chan, opin_mux_size, Fs_per_side, - sblock_pattern, &edge_list, seg_details, directionality, - L_rr_node_indices, L_rr_edge_done, switch_block_conn); - } - } - /* END */ - - inode = get_rr_node_index(i, j, CHANX, itrack, L_rr_node_indices); - alloc_and_load_edges_and_switches(L_rr_node, inode, num_edges, - L_rr_edge_done, edge_list); - - while (edge_list != NULL) { - next = edge_list->next; - free(edge_list); - edge_list = next; - } - - /* Edge arrays have now been built up. Do everything else. */ - L_rr_node[inode].cost_index = cost_index_offset - + seg_details[itrack].index; - L_rr_node[inode].occ = 0; - - L_rr_node[inode].capacity = 1; /* GLOBAL routing handled elsewhere */ - - if (is_stack) { - /* mrFPGA: Xifan TANG */ - L_rr_node[inode].xlow = istart; - L_rr_node[inode].xhigh = iend; - L_rr_node[inode].ylow = jstart; - L_rr_node[inode].yhigh = jend; - } else { - /* Original VPR */ - L_rr_node[inode].xlow = istart; - L_rr_node[inode].xhigh = iend; - L_rr_node[inode].ylow = j; - L_rr_node[inode].yhigh = j; - } - - /* mrFPGA: Xifan TANG */ - length = is_stack ? (jend - jstart) : (iend - istart + 1); - //length = (iend - istart + 1); - /* END */ - - L_rr_node[inode].R = length * seg_details[itrack].Rmetal; - L_rr_node[inode].C = length * seg_details[itrack].Cmetal; - - L_rr_node[inode].ptc_num = itrack; - L_rr_node[inode].type = CHANX; - L_rr_node[inode].direction = seg_details[itrack].direction; - L_rr_node[inode].drivers = seg_details[itrack].drivers; - /* Xifan TANG:(For SPICE Modeling) Fill the segment inf */ - //LL_rr_node[inode].seg_index = seg_details[itrack].index; - } -} - -static void build_rr_ychan(INP int i, INP int j, - INP struct s_ivec ****track_to_ipin_lookup, - INP struct s_ivec ***switch_block_conn, INP int cost_index_offset, - INP int nodes_per_chan, INP int *opin_mux_size, - INP short *****sblock_pattern, INP int Fs_per_side, - INP t_seg_details * seg_details, INP t_ivec *** L_rr_node_indices, - INP boolean * L_rr_edge_done, INOUTP t_rr_node * L_rr_node, - INP int wire_to_ipin_switch, INP enum e_directionality directionality) { - - /* Loads up all the routing resource nodes in the y-directed channel * - * segments starting at (i,j). */ - - int itrack, istart, iend, num_edges, inode, length; - struct s_linked_edge *edge_list, *next; - - /* mrFPGA: Xifan TANG*/ - int jstart, jend; - /* END */ - - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - /* First count number of edges and put the edges in a linked list. */ - num_edges = 0; - edge_list = NULL; - - /* mrFPGA */ - if ( is_stack ) { - istart = get_seg_start (seg_details, itrack, j, i); - if ( istart != i ) - continue; - iend = get_seg_end (seg_details, itrack, istart, j, nx); - /* mrFPGA: Xifan TANG */ - jstart = j; - jend = j; - /* end */ - - num_edges += get_track_to_ipins(istart, j, itrack, &edge_list, L_rr_node_indices, - track_to_ipin_lookup, seg_details, CHANY, nx, wire_to_ipin_switch, - directionality); - - num_edges += get_track_to_tracks(j, istart, itrack, CHANY, j-1, CHANX, nx, - nodes_per_chan, opin_mux_size, Fs_per_side, sblock_pattern, - &edge_list, seg_details, directionality, L_rr_node_indices, - L_rr_edge_done, switch_block_conn); - - num_edges += get_track_to_tracks(j, istart, itrack, CHANY, j, CHANX, nx, - nodes_per_chan, opin_mux_size, Fs_per_side, sblock_pattern, - &edge_list, seg_details, directionality, L_rr_node_indices, - L_rr_edge_done, switch_block_conn); - - if (istart > 0) { - num_edges += get_track_to_tracks(j, istart, itrack, CHANY, istart - 1, CHANY, nx, - nodes_per_chan, opin_mux_size, Fs_per_side, sblock_pattern, &edge_list, - seg_details, directionality, L_rr_node_indices, L_rr_edge_done, - switch_block_conn); - } - - if (iend < nx) { - num_edges += get_track_to_tracks(j, istart, itrack, CHANY, iend + 1, - CHANY, nx, nodes_per_chan, opin_mux_size, Fs_per_side, - sblock_pattern, &edge_list, seg_details, directionality, - L_rr_node_indices, L_rr_edge_done, switch_block_conn); - - } - } else { /* end */ - istart = get_seg_start(seg_details, itrack, i, j); - iend = get_seg_end(seg_details, itrack, istart, i, ny); - - if (j > istart) - continue; /* Not the start of this segment. */ - /* mrFPGA: Xifan TANG*/ - jstart = i; - jend = i; - /* END */ - - /* Original VPR */ - /* First count number of edges and put the edges in a linked list. */ - num_edges = 0; - edge_list = NULL; - - num_edges += get_track_to_ipins(istart, i, itrack, &edge_list, - L_rr_node_indices, track_to_ipin_lookup, seg_details, CHANY, ny, - wire_to_ipin_switch, directionality); - - if (i > 0) { - num_edges += get_track_to_tracks(i, istart, itrack, CHANY, i, CHANX, - ny, nodes_per_chan, opin_mux_size, Fs_per_side, - sblock_pattern, &edge_list, seg_details, directionality, - L_rr_node_indices, L_rr_edge_done, switch_block_conn); - } - - if (i < nx) { - num_edges += get_track_to_tracks(i, istart, itrack, CHANY, i + 1, - CHANX, ny, nodes_per_chan, opin_mux_size, Fs_per_side, - sblock_pattern, &edge_list, seg_details, directionality, - L_rr_node_indices, L_rr_edge_done, switch_block_conn); - } - - if (istart > 1) { - num_edges += get_track_to_tracks(i, istart, itrack, CHANY, - istart - 1, CHANY, ny, nodes_per_chan, opin_mux_size, - Fs_per_side, sblock_pattern, &edge_list, seg_details, - directionality, L_rr_node_indices, L_rr_edge_done, - switch_block_conn); - } - - if (iend < ny) { - num_edges += get_track_to_tracks(i, istart, itrack, CHANY, iend + 1, - CHANY, ny, nodes_per_chan, opin_mux_size, Fs_per_side, - sblock_pattern, &edge_list, seg_details, directionality, - L_rr_node_indices, L_rr_edge_done, switch_block_conn); - } - } - /* END */ - - inode = get_rr_node_index(i, j, CHANY, itrack, L_rr_node_indices); - alloc_and_load_edges_and_switches(L_rr_node, inode, num_edges, - L_rr_edge_done, edge_list); - - while (edge_list != NULL) { - next = edge_list->next; - free(edge_list); - edge_list = next; - } - - /* Edge arrays have now been built up. Do everything else. */ - L_rr_node[inode].cost_index = cost_index_offset - + seg_details[itrack].index; - L_rr_node[inode].occ = 0; - - L_rr_node[inode].capacity = 1; /* GLOBAL routing handled elsewhere */ - - if (is_stack) { - /* mrFPGA: Xifan TANG */ - L_rr_node[inode].xlow = istart; - L_rr_node[inode].xhigh = iend; - L_rr_node[inode].ylow = jstart; - L_rr_node[inode].yhigh = jend; - } else { - /* Original VPR */ - L_rr_node[inode].xlow = i; - L_rr_node[inode].xhigh = i; - L_rr_node[inode].ylow = istart; - L_rr_node[inode].yhigh = iend; - } - - /* mrFPGA : Xifan TANG*/ - length = is_stack ? (iend - istart) : (iend - istart + 1); - //length = (iend - istart + 1); - /* END */ - - L_rr_node[inode].R = length * seg_details[itrack].Rmetal; - L_rr_node[inode].C = length * seg_details[itrack].Cmetal; - - L_rr_node[inode].ptc_num = itrack; - L_rr_node[inode].type = CHANY; - L_rr_node[inode].direction = seg_details[itrack].direction; - L_rr_node[inode].drivers = seg_details[itrack].drivers; - /* Xifan TANG:(For SPICE Modeling) Fill the segment inf */ - //LL_rr_node[inode].seg_index = seg_details[itrack].index; - } -} - -void watch_edges(int inode, t_linked_edge * edge_list_head) { - t_linked_edge *list_ptr; - int i, to_node; - - list_ptr = edge_list_head; - i = 0; - - vpr_printf(TIO_MESSAGE_TRACE, "!!! Watching Node %d !!!!\n", inode); - print_rr_node(stdout, rr_node, inode); - vpr_printf(TIO_MESSAGE_TRACE, "Currently connects to:\n"); - while (list_ptr != NULL) { - to_node = list_ptr->edge; - print_rr_node(stdout, rr_node, to_node); - list_ptr = list_ptr->next; - i++; - } -} - -void alloc_and_load_edges_and_switches(INP t_rr_node * L_rr_node, INP int inode, - INP int num_edges, INOUTP boolean * L_rr_edge_done, - INP t_linked_edge * edge_list_head) { - - /* Sets up all the edge related information for rr_node inode (num_edges, * - * the edges array and the switches array). The edge_list_head points to * - * a list of the num_edges edges and switches to put in the arrays. This * - * linked list is freed by this routine. This routine also resets the * - * rr_edge_done array for the next rr_node (i.e. set it so that no edges * - * are marked as having been seen before). */ - - t_linked_edge *list_ptr; - int i; - - /* Check we aren't overwriting edges */ - assert(L_rr_node[inode].num_edges < 1); - assert(NULL == L_rr_node[inode].edges); - assert(NULL == L_rr_node[inode].switches); - - L_rr_node[inode].num_edges = num_edges; - L_rr_node[inode].edges = (int *) my_malloc(num_edges * sizeof(int)); - L_rr_node[inode].switches = (short *) my_malloc(num_edges * sizeof(short)); - - i = 0; - list_ptr = edge_list_head; - while (list_ptr && (i < num_edges)) { - L_rr_node[inode].edges[i] = list_ptr->edge; - L_rr_node[inode].switches[i] = list_ptr->iswitch; - - ++L_rr_node[list_ptr->edge].fan_in; - - /* Unmark the edge since we are done considering fanout from node. */ - L_rr_edge_done[list_ptr->edge] = FALSE; - - list_ptr = list_ptr->next; - ++i; - } - assert(list_ptr == NULL); - assert(i == num_edges); -} - -int **** -alloc_and_load_pin_to_track_map(INP enum e_pin_type pin_type, - INP int nodes_per_chan, INP int *Fc, INP t_type_ptr Type, - INP boolean perturb_switch_pattern, - INP enum e_directionality directionality) { - - int **num_dir; /* [0..height][0..3] Number of *physical* pins on each side. */ - int ***dir_list; /* [0..height][0..3][0..num_pins-1] list of pins of correct type * - * * on each side. Max possible space alloced for simplicity */ - - int i, j, k, iside, ipin, iclass, num_phys_pins, pindex, ioff; - int *pin_num_ordering, *side_ordering, *offset_ordering; - int **num_done_per_dir; /* [0..height][0..3] */ - int ****tracks_connected_to_pin; /* [0..num_pins-1][0..height][0..3][0..Fc-1] */ - - /* NB: This wastes some space. Could set tracks_..._pin[ipin][ioff][iside] = - * NULL if there is no pin on that side, or that pin is of the wrong type. - * Probably not enough memory to worry about, esp. as it's temporary. - * If pin ipin on side iside does not exist or is of the wrong type, - * tracks_connected_to_pin[ipin][iside][0] = OPEN. */ - - if (Type->num_pins < 1) { - return NULL; - } - - /* Currently, only two possible Fc values exist: 0 or default. - * Finding the max. value of Fc in block will result in the - * default value, which works for now. In the future, when - * the Fc values of all pins can vary, the max value will continue - * to work for matrix (de)allocation purposes. However, all looping - * will have to be modified to account for pin-based Fc values. */ - int max_Fc = 0; - for (i = 0; i < Type->num_pins; ++i) { - iclass = Type->pin_class[i]; - if (Fc[i] > max_Fc && Type->class_inf[iclass].type == pin_type) { - max_Fc = Fc[i]; - } - } - - tracks_connected_to_pin = (int ****) alloc_matrix4(0, Type->num_pins - 1, 0, - Type->height - 1, 0, 3, 0, max_Fc, sizeof(int)); - - for (ipin = 0; ipin < Type->num_pins; ipin++) { - for (ioff = 0; ioff < Type->height; ioff++) { - for (iside = 0; iside < 4; iside++) { - for (i = 0; i < max_Fc; ++i) { - tracks_connected_to_pin[ipin][ioff][iside][i] = OPEN; /* Unconnected. */ - } - } - } - } - - num_dir = (int **) alloc_matrix(0, Type->height - 1, 0, 3, sizeof(int)); - dir_list = (int ***) alloc_matrix3(0, Type->height - 1, 0, 3, 0, - Type->num_pins - 1, sizeof(int)); - - /* Defensive coding. Try to crash hard if I use an unset entry. */ - for (i = 0; i < Type->height; i++) - for (j = 0; j < 4; j++) - for (k = 0; k < Type->num_pins; k++) - dir_list[i][j][k] = (-1); - - for (i = 0; i < Type->height; i++) - for (j = 0; j < 4; j++) - num_dir[i][j] = 0; - - for (ipin = 0; ipin < Type->num_pins; ipin++) { - iclass = Type->pin_class[ipin]; - if (Type->class_inf[iclass].type != pin_type) /* Doing either ipins OR opins */ - continue; - - /* Pins connecting only to global resources get no switches -> keeps the * - * area model accurate. */ - - if (Type->is_global_pin[ipin]) - continue; - for (ioff = 0; ioff < Type->height; ioff++) { - for (iside = 0; iside < 4; iside++) { - if (Type->pinloc[ioff][iside][ipin] == 1) { - dir_list[ioff][iside][num_dir[ioff][iside]] = ipin; - num_dir[ioff][iside]++; - } - } - } - } - - num_phys_pins = 0; - for (ioff = 0; ioff < Type->height; ioff++) { - for (iside = 0; iside < 4; iside++) - num_phys_pins += num_dir[ioff][iside]; /* Num. physical pins per type */ - } - num_done_per_dir = (int **) alloc_matrix(0, Type->height - 1, 0, 3, - sizeof(int)); - for (ioff = 0; ioff < Type->height; ioff++) { - for (iside = 0; iside < 4; iside++) { - num_done_per_dir[ioff][iside] = 0; - } - } - pin_num_ordering = (int *) my_malloc(num_phys_pins * sizeof(int)); - side_ordering = (int *) my_malloc(num_phys_pins * sizeof(int)); - offset_ordering = (int *) my_malloc(num_phys_pins * sizeof(int)); - - /* Connection block I use distributes pins evenly across the tracks * - * of ALL sides of the clb at once. Ensures that each pin connects * - * to spaced out tracks in its connection block, and that the other * - * pins (potentially in other C blocks) connect to the remaining tracks * - * first. Doesn't matter for large Fc, but should make a fairly * - * good low Fc block that leverages the fact that usually lots of pins * - * are logically equivalent. */ - - iside = LEFT; - ioff = Type->height - 1; - ipin = 0; - pindex = -1; - - while (ipin < num_phys_pins) { - if (iside == TOP) { - iside = RIGHT; - } else if (iside == RIGHT) { - if (ioff <= 0) { - iside = BOTTOM; - } else { - ioff--; - } - } else if (iside == BOTTOM) { - iside = LEFT; - } else { - assert(iside == LEFT); - if (ioff >= Type->height - 1) { - pindex++; - iside = TOP; - } else { - ioff++; - } - } - - assert(pindex < num_phys_pins); - /* Number of physical pins bounds number of logical pins */ - - if (num_done_per_dir[ioff][iside] >= num_dir[ioff][iside]) - continue; - pin_num_ordering[ipin] = dir_list[ioff][iside][pindex]; - side_ordering[ipin] = iside; - offset_ordering[ipin] = ioff; - assert(Type->pinloc[ioff][iside][dir_list[ioff][iside][pindex]]); - num_done_per_dir[ioff][iside]++; - ipin++; - } - - if (perturb_switch_pattern) { - load_perturbed_switch_pattern(Type, tracks_connected_to_pin, - num_phys_pins, pin_num_ordering, side_ordering, offset_ordering, - nodes_per_chan, max_Fc, directionality); - } else { - load_uniform_switch_pattern(Type, tracks_connected_to_pin, - num_phys_pins, pin_num_ordering, side_ordering, offset_ordering, - nodes_per_chan, max_Fc, directionality); - } - check_all_tracks_reach_pins(Type, tracks_connected_to_pin, nodes_per_chan, - max_Fc, pin_type); - - /* Free all temporary storage. */ - free_matrix(num_dir, 0, Type->height - 1, 0, sizeof(int)); - free_matrix3(dir_list, 0, Type->height - 1, 0, 3, 0, sizeof(int)); - free_matrix(num_done_per_dir, 0, Type->height - 1, 0, sizeof(int)); - free(pin_num_ordering); - free(side_ordering); - free(offset_ordering); - - return tracks_connected_to_pin; -} - -static void load_uniform_switch_pattern(INP t_type_ptr type, - INOUTP int ****tracks_connected_to_pin, INP int num_phys_pins, - INP int *pin_num_ordering, INP int *side_ordering, - INP int *offset_ordering, INP int nodes_per_chan, INP int Fc, - enum e_directionality directionality) { - - /* Loads the tracks_connected_to_pin array with an even distribution of * - * switches across the tracks for each pin. For example, each pin connects * - * to every 4.3rd track in a channel, with exactly which tracks a pin * - * connects to staggered from pin to pin. */ - - int i, j, ipin, iside, ioff, itrack, k; - float f_track, fc_step; - int group_size; - float step_size; - - /* Uni-directional drive is implemented to ensure no directional bias and this means - * two important comments noted below */ - /* 1. Spacing should be (W/2)/(Fc/2), and step_size should be spacing/(num_phys_pins), - * and lay down 2 switches on an adjacent pair of tracks at a time to ensure - * no directional bias. Basically, treat W (even) as W/2 pairs of tracks, and - * assign switches to a pair at a time. Can do this because W is guaranteed to - * be even-numbered; however same approach cannot be applied to Fc_out pattern - * when L > 1 and W <> 2L multiple. - * - * 2. This generic pattern should be considered the tileable physical layout, - * meaning all track # here are physical #'s, - * so later must use vpr_to_phy conversion to find actual logical #'s to connect. - * This also means I will not use get_output_block_companion_track to ensure - * no bias, since that describes a logical # -> that would confuse people. */ - - step_size = (float) nodes_per_chan / (float) (Fc * num_phys_pins); - - if (directionality == BI_DIRECTIONAL) { - group_size = 1; - } else { - assert(directionality == UNI_DIRECTIONAL); - group_size = 2; - } - - assert((nodes_per_chan % group_size == 0) && (Fc % group_size == 0)); - - fc_step = (float) nodes_per_chan / (float) Fc; - - for (i = 0; i < num_phys_pins; i++) { - ipin = pin_num_ordering[i]; - iside = side_ordering[i]; - ioff = offset_ordering[i]; - - /* Bi-directional treats each track separately, uni-directional works with pairs of tracks */ - for (j = 0; j < (Fc / group_size); j++) { - f_track = (i * step_size) + (j * fc_step); - itrack = ((int) f_track) * group_size; - - /* Catch possible floating point round error */ - itrack = std::min(itrack, nodes_per_chan - group_size); - - /* Assign the group of tracks for the Fc pattern */ - for (k = 0; k < group_size; ++k) { - tracks_connected_to_pin[ipin][ioff][iside][group_size * j + k] = - itrack + k; - } - } - } -} - -static void load_perturbed_switch_pattern(INP t_type_ptr type, - INOUTP int ****tracks_connected_to_pin, INP int num_phys_pins, - INP int *pin_num_ordering, INP int *side_ordering, - INP int *offset_ordering, INP int nodes_per_chan, INP int Fc, - enum e_directionality directionality) { - - /* Loads the tracks_connected_to_pin array with an unevenly distributed * - * set of switches across the channel. This is done for inputs when * - * Fc_input = Fc_output to avoid creating "pin domains" -- certain output * - * pins being able to talk only to certain input pins because their switch * - * patterns exactly line up. Distribute Fc/2 + 1 switches over half the * - * channel and Fc/2 - 1 switches over the other half to make the switch * - * pattern different from the uniform one of the outputs. Also, have half * - * the pins put the "dense" part of their connections in the first half of * - * the channel and the other half put the "dense" part in the second half, * - * to make sure each track can connect to about the same number of ipins. */ - - int i, j, ipin, iside, itrack, ihalf, iconn, ioff; - int Fc_dense, Fc_sparse, Fc_half[2]; - float f_track, spacing_dense, spacing_sparse, spacing[2]; - float step_size; - - assert(directionality == BI_DIRECTIONAL); - - step_size = (float) nodes_per_chan / (float) (Fc * num_phys_pins); - - Fc_dense = (Fc / 2) + 1; - Fc_sparse = Fc - Fc_dense; /* Works for even or odd Fc */ - - spacing_dense = (float) nodes_per_chan / (float) (2 * Fc_dense); - spacing_sparse = (float) nodes_per_chan / (float) (2 * Fc_sparse); - - for (i = 0; i < num_phys_pins; i++) { - ipin = pin_num_ordering[i]; - iside = side_ordering[i]; - ioff = offset_ordering[i]; - - /* Flip every pin to balance switch density */ - spacing[i % 2] = spacing_dense; - Fc_half[i % 2] = Fc_dense; - spacing[(i + 1) % 2] = spacing_sparse; - Fc_half[(i + 1) % 2] = Fc_sparse; - - f_track = i * step_size; /* Start point. Staggered from pin to pin */ - iconn = 0; - - for (ihalf = 0; ihalf < 2; ihalf++) { /* For both dense and sparse halves. */ - for (j = 0; j < Fc_half[ihalf]; ++j) { - itrack = (int) f_track; - - /* Can occasionally get wraparound due to floating point rounding. - This is okay because the starting position > 0 when this occurs - so connection is valid and fine */ - itrack = itrack % nodes_per_chan; - tracks_connected_to_pin[ipin][ioff][iside][iconn] = itrack; - - f_track += spacing[ihalf]; - iconn++; - } - } - } /* End for all physical pins. */ -} - -static void check_all_tracks_reach_pins(t_type_ptr type, - int ****tracks_connected_to_pin, int nodes_per_chan, int Fc, - enum e_pin_type ipin_or_opin) { - - /* Checks that all tracks can be reached by some pin. */ - - int iconn, iside, itrack, ipin, ioff; - int *num_conns_to_track; /* [0..nodes_per_chan-1] */ - - assert(nodes_per_chan > 0); - - num_conns_to_track = (int *) my_calloc(nodes_per_chan, sizeof(int)); - - for (ipin = 0; ipin < type->num_pins; ipin++) { - for (ioff = 0; ioff < type->height; ioff++) { - for (iside = 0; iside < 4; iside++) { - if (tracks_connected_to_pin[ipin][ioff][iside][0] != OPEN) { /* Pin exists */ - for (iconn = 0; iconn < Fc; iconn++) { - itrack = - tracks_connected_to_pin[ipin][ioff][iside][iconn]; - num_conns_to_track[itrack]++; - } - } - } - } - } - - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - if (num_conns_to_track[itrack] <= 0) { - vpr_printf(TIO_MESSAGE_WARNING, "check_all_tracks_reach_pins: Track %d does not connect to any CLB %ss.\n", - itrack, (ipin_or_opin == DRIVER ? "OPIN" : "IPIN")); - } - } - - free(num_conns_to_track); -} - -/* Allocates and loads the track to ipin lookup for each physical grid type. This - * is the same information as the ipin_to_track map but accessed in a different way. */ - -struct s_ivec *** -alloc_and_load_track_to_pin_lookup(INP int ****pin_to_track_map, INP int *Fc, - INP int height, INP int num_pins, INP int nodes_per_chan) { - int ipin, iside, itrack, iconn, ioff, pin_counter; - struct s_ivec ***track_to_pin_lookup; - - /* [0..nodes_per_chan-1][0..height][0..3]. For each track number it stores a vector - * for each of the four sides. x-directed channels will use the TOP and - * BOTTOM vectors to figure out what clb input pins they connect to above - * and below them, respectively, while y-directed channels use the LEFT - * and RIGHT vectors. Each vector contains an nelem field saying how many - * ipins it connects to. The list[0..nelem-1] array then gives the pin - * numbers. */ - - /* Note that a clb pin that connects to a channel on its RIGHT means that * - * that channel connects to a clb pin on its LEFT. The convention used * - * here is always in the perspective of the CLB */ - - if (num_pins < 1) { - return NULL; - } - - /* Alloc and zero the the lookup table */ - track_to_pin_lookup = (struct s_ivec ***) alloc_matrix3(0, - nodes_per_chan - 1, 0, height - 1, 0, 3, sizeof(struct s_ivec)); - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - for (ioff = 0; ioff < height; ioff++) { - for (iside = 0; iside < 4; iside++) { - track_to_pin_lookup[itrack][ioff][iside].nelem = 0; - track_to_pin_lookup[itrack][ioff][iside].list = NULL; - } - } - } - - /* Counting pass. */ - for (ipin = 0; ipin < num_pins; ipin++) { - for (ioff = 0; ioff < height; ioff++) { - for (iside = 0; iside < 4; iside++) { - if (pin_to_track_map[ipin][ioff][iside][0] == OPEN) - continue; - - for (iconn = 0; iconn < Fc[ipin]; iconn++) { - itrack = pin_to_track_map[ipin][ioff][iside][iconn]; - track_to_pin_lookup[itrack][ioff][iside].nelem++; - } - } - } - } - - /* Allocate space. */ - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - for (ioff = 0; ioff < height; ioff++) { - for (iside = 0; iside < 4; iside++) { - track_to_pin_lookup[itrack][ioff][iside].list = NULL; /* Defensive code */ - if (track_to_pin_lookup[itrack][ioff][iside].nelem != 0) { - track_to_pin_lookup[itrack][ioff][iside].list = - (int *) my_malloc( - track_to_pin_lookup[itrack][ioff][iside].nelem - * sizeof(int)); - track_to_pin_lookup[itrack][ioff][iside].nelem = 0; - } - } - } - } - - /* Loading pass. */ - for (ipin = 0; ipin < num_pins; ipin++) { - for (ioff = 0; ioff < height; ioff++) { - for (iside = 0; iside < 4; iside++) { - if (pin_to_track_map[ipin][ioff][iside][0] == OPEN) - continue; - - for (iconn = 0; iconn < Fc[ipin]; iconn++) { - itrack = pin_to_track_map[ipin][ioff][iside][iconn]; - pin_counter = - track_to_pin_lookup[itrack][ioff][iside].nelem; - track_to_pin_lookup[itrack][ioff][iside].list[pin_counter] = - ipin; - track_to_pin_lookup[itrack][ioff][iside].nelem++; - } - } - } - } - - return track_to_pin_lookup; -} - -/* A utility routine to dump the contents of the routing resource graph * - * (everything -- connectivity, occupancy, cost, etc.) into a file. Used * - * only for debugging. */ -void dump_rr_graph(INP const char *file_name) { - - int inode; - FILE *fp; - - fp = my_fopen(file_name, "w", 0); - - for (inode = 0; inode < num_rr_nodes; inode++) { - print_rr_node(fp, rr_node, inode); - fprintf(fp, "\n"); - } - -#if 0 - fprintf(fp, "\n\n%d rr_indexed_data entries.\n\n", num_rr_indexed_data); - - for (index = 0; index < num_rr_indexed_data; index++) - { - print_rr_indexed_data(fp, index); - fprintf(fp, "\n"); - } -#endif - - fclose(fp); -} - -/* Prints all the data about node inode to file fp. */ -void print_rr_node(FILE * fp, t_rr_node * L_rr_node, int inode) { - - static const char *name_type[] = { "SOURCE", "SINK", "IPIN", "OPIN", - "CHANX", "CHANY", "INTRA_CLUSTER_EDGE" }; - static const char *direction_name[] = { "OPEN", "INC_DIRECTION", - "DEC_DIRECTION", "BI_DIRECTION" }; - static const char *drivers_name[] = { "OPEN", "MULTI_BUFFER", "SINGLE" }; - - t_rr_type rr_type; - int iconn; - - rr_type = L_rr_node[inode].type; - - /* Make sure we don't overrun const arrays */ - assert((int)rr_type < (int)(sizeof(name_type) / sizeof(char *))); - assert( - (L_rr_node[inode].direction + 1) < (int)(sizeof(direction_name) / sizeof(char *))); - assert( - (L_rr_node[inode].drivers + 1) < (int)(sizeof(drivers_name) / sizeof(char *))); - - fprintf(fp, "Node: %d %s ", inode, name_type[rr_type]); - if ((L_rr_node[inode].xlow == L_rr_node[inode].xhigh) - && (L_rr_node[inode].ylow == L_rr_node[inode].yhigh)) { - fprintf(fp, "(%d, %d) ", L_rr_node[inode].xlow, L_rr_node[inode].ylow); - } else { - fprintf(fp, "(%d, %d) to (%d, %d) ", L_rr_node[inode].xlow, - L_rr_node[inode].ylow, L_rr_node[inode].xhigh, - L_rr_node[inode].yhigh); - } - fprintf(fp, "Ptc_num: %d ", L_rr_node[inode].ptc_num); - fprintf(fp, "Direction: %s ", - direction_name[L_rr_node[inode].direction + 1]); - fprintf(fp, "Drivers: %s ", drivers_name[L_rr_node[inode].drivers + 1]); - fprintf(fp, "\n"); - - fprintf(fp, "%d edge(s):", L_rr_node[inode].num_edges); - for (iconn = 0; iconn < L_rr_node[inode].num_edges; iconn++) - fprintf(fp, " %d", L_rr_node[inode].edges[iconn]); - fprintf(fp, "\n"); - - fprintf(fp, "Switch types:"); - for (iconn = 0; iconn < L_rr_node[inode].num_edges; iconn++) - fprintf(fp, " %d", L_rr_node[inode].switches[iconn]); - fprintf(fp, "\n"); - - fprintf(fp, "Occ: %d Capacity: %d\n", L_rr_node[inode].occ, - L_rr_node[inode].capacity); - if (rr_type != INTRA_CLUSTER_EDGE) { - fprintf(fp, "R: %g C: %g\n", L_rr_node[inode].R, L_rr_node[inode].C); - } - fprintf(fp, "Cost_index: %d\n", L_rr_node[inode].cost_index); -} - -/* Prints all the rr_indexed_data of index to file fp. */ -void print_rr_indexed_data(FILE * fp, int index) { - - fprintf(fp, "Index: %d\n", index); - - fprintf(fp, "ortho_cost_index: %d ", - rr_indexed_data[index].ortho_cost_index); - fprintf(fp, "base_cost: %g ", rr_indexed_data[index].saved_base_cost); - fprintf(fp, "saved_base_cost: %g\n", - rr_indexed_data[index].saved_base_cost); - - fprintf(fp, "Seg_index: %d ", rr_indexed_data[index].seg_index); - fprintf(fp, "inv_length: %g\n", rr_indexed_data[index].inv_length); - - fprintf(fp, "T_linear: %g ", rr_indexed_data[index].T_linear); - fprintf(fp, "T_quadratic: %g ", rr_indexed_data[index].T_quadratic); - fprintf(fp, "C_load: %g\n", rr_indexed_data[index].C_load); -} - -static void build_unidir_rr_opins(INP int i, INP int j, - INP struct s_grid_tile **L_grid, INP int **Fc_out, - INP int nodes_per_chan, INP t_seg_details * seg_details, - INOUTP int **Fc_xofs, INOUTP int **Fc_yofs, - INOUTP t_rr_node * L_rr_node, INOUTP boolean * L_rr_edge_done, - OUTP boolean * Fc_clipped, INP t_ivec *** L_rr_node_indices, INP int delayless_switch, - INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs) { - /* This routine returns a list of the opins rr_nodes on each - * side/offset of the block. You must free the result with - * free_matrix. */ - - t_type_ptr type; - int ipin, iclass, ofs, chan, seg, max_len, inode, max_Fc = -1; - enum e_side side; - t_rr_type chan_type; - t_linked_edge *edge_list = NULL, *next; - boolean clipped, vert, pos_dir; - int num_edges; - int **Fc_ofs; - - *Fc_clipped = FALSE; - - /* Only the base block of a set should use this function */ - if (L_grid[i][j].offset > 0) { - return; - } - - type = L_grid[i][j].type; - - /* Currently, only two possible Fc values exist: 0 or default. - * Finding the max. value of Fc in block will result in the - * default value, which works for now. In the future, when - * the Fc values of all pins can vary, the max value will continue - * to work for matrix allocation purposes. However, all looping - * will have to be modified to account for pin-based Fc values. */ - if (type->index > 0) { - max_Fc = 0; - for (ipin = 0; ipin < type->num_pins; ++ipin) { - iclass = type->pin_class[ipin]; - if (Fc_out[type->index][ipin] > max_Fc && type->class_inf[iclass].type == DRIVER) { - max_Fc = Fc_out[type->index][ipin]; - } - } - } - - /* Go through each pin and find its fanout. */ - for (ipin = 0; ipin < type->num_pins; ++ipin) { - /* Skip global pins and ipins */ - iclass = type->pin_class[ipin]; - if (type->class_inf[iclass].type != DRIVER) { - continue; - } - if (type->is_global_pin[ipin]) { - continue; - } - - num_edges = 0; - edge_list = NULL; - if(Fc_out[type->index][ipin] != 0) { - for (ofs = 0; ofs < type->height; ++ofs) { - for (side = (enum e_side)0; side < 4; side = (enum e_side)(side + 1)) { - /* Can't do anything if pin isn't at this location */ - if (0 == type->pinloc[ofs][side][ipin]) { - continue; - } - - /* Figure out the chan seg at that side. - * side is the side of the logic or io block. */ - vert = (boolean) ((side == TOP) || (side == BOTTOM)); - /* mrFPGA */ - if (is_stack) { - vert = (boolean)(!vert); - } - /* END */ - pos_dir = (boolean) ((side == TOP) || (side == RIGHT)); - /* mrFPGA */ - //chan_type = (vert ? CHANX : CHANY); - chan_type = ((is_stack ? !vert : vert) ? CHANX : CHANY); - /* END */ - chan = (vert ? (j + ofs) : i); - seg = (vert ? i : (j + ofs)); - max_len = (vert ? nx : ny); - Fc_ofs = (vert ? Fc_xofs : Fc_yofs); - if (FALSE == pos_dir) { - /* mrFPGA */ - if (is_stack) { - --seg; - /* END */ - } else { - --chan; - } - } - - /* mrFPGA */ - /* Skip the location if there is no channel. */ - if (chan < (is_stack ? 1:0)) { - continue; - } - if (seg < (is_stack ? 0:1)) { - continue; - } - /* END */ - if (seg > (vert ? nx : ny)) { - continue; - } - if (chan > (vert ? ny : nx)) { - continue; - } - - /* Get the list of opin to mux connections for that chan seg. */ - num_edges += get_unidir_opin_connections(chan, seg, - max_Fc, chan_type, seg_details, &edge_list, - Fc_ofs, L_rr_edge_done, max_len, nodes_per_chan, - L_rr_node_indices, &clipped); - if (clipped) { - *Fc_clipped = TRUE; - } - } - } - } - - /* Add in direct connections */ - num_edges += get_opin_direct_connecions(i, j, ipin, &edge_list, L_rr_node_indices, delayless_switch, directs, num_directs, clb_to_clb_directs); - - /* Add the edges */ - inode = get_rr_node_index(i, j, OPIN, ipin, L_rr_node_indices); - alloc_and_load_edges_and_switches(rr_node, inode, num_edges, - L_rr_edge_done, edge_list); - while (edge_list != NULL) { - next = edge_list->next; - free(edge_list); - edge_list = next; - } - } -} -#if 0 -static void -load_uniform_opin_switch_pattern_paired(INP int *Fc_out, - INP int num_pins, - INP int *pins_in_chan_seg, - INP int num_wire_inc_muxes, - INP int num_wire_dec_muxes, - INP int *wire_inc_muxes, - INP int *wire_dec_muxes, - INOUTP t_rr_node * L_rr_node, - INOUTP boolean * L_rr_edge_done, - INP t_seg_details * seg_details, - OUTP boolean * Fc_clipped) -{ - - /* Directionality is assumed to be uni-directional */ - - /* Make turn-based assignment to avoid overlap when Fc_ouput is low. This is a bipartite - * matching problem. Out of "num_wire_muxes" muxes "Fc_output" of them is assigned - * to each outpin (total "num_pins" of them); assignment is uniform (spacing - spreadout) - * and staggered to avoid overlap when Fc_output is low. */ - - /* The natural order wires muxes are stored in wire_muxes is alternating in directionality - * already (by my implementation), so no need to do anything extra to avoid directional bias */ - - /* TODO: Due to spacing, it's possible to have directional bias: all Fc_out wires connected - * to one opin goes in either INC or DEC -> whereas I want a mix of both. - * SOLUTION: Use quantization of 2 to ensure that if an opin connects to one wire, it - * must also connect to its companion wire, which runs in the opposite direction. This - * means instead of having num_wire_muxes as the matching set, pick out the INC wires - * in num_wires_muxes as the matching set (the DEC wires are their companions) April 17, 2007 - * NEWS: That solution does not work, as treating wires in groups will lead to serious - * abnormal patterns (conns crossing multiple blocks) for W nonquantized to multiples of 2L. - * So, I'm chaning that approach to a new one that avoids directional bias: I will separate - * the INC muxes and DEC muxes into two sets. Each set is uniformly assigned to opins with - * Fc_output/2; this should be identical as before for normal cases and contains all conns - * in the same chan segment for the nonquantized cases. */ - - /* Finally, separated the two approaches: 1. Take all wire muxes and assign them to opins - * one at a time (load_uniform_opin_switch_pattern) 2. Take pairs (by companion) - * of wire muxes and assign them to opins a pair at a time (load_uniform_opin_switch_pattern_paired). - * The first is used for fringe channel segments (ends of channels, where - * there are lots of muxes due to partial wire segments) and the second is used in core */ - - /* float spacing, step_size, f_mux; */ - int ipin, iconn, num_edges, init_mux; - int from_node, to_node, to_track; - int xlow, ylow; - t_linked_edge *edge_list; - int *wire_muxes; - int k, num_wire_muxes, Fc_output_per_side, CurFc; - int count_inc, count_dec; - t_type_ptr type; - - *Fc_clipped = FALSE; - - count_inc = count_dec = 0; - - for (ipin = 0; ipin < num_pins; ipin++) - { - from_node = pins_in_chan_seg[ipin]; - xlow = L_rr_node[from_node].xlow; - ylow = L_rr_node[from_node].ylow; - type = grid[xlow][ylow].type; - edge_list = NULL; - num_edges = 0; - - /* Assigning the INC muxes first, then DEC muxes */ - for (k = 0; k < 2; ++k) - { - if (k == 0) - { - num_wire_muxes = num_wire_inc_muxes; - wire_muxes = wire_inc_muxes; - } - else - { - num_wire_muxes = num_wire_dec_muxes; - wire_muxes = wire_dec_muxes; - } - - /* Half the Fc will be assigned for each direction. */ - assert(Fc_out[type->index] % 2 == 0); - Fc_output_per_side = Fc_out[type->index] / 2; - - /* Clip the demand. Make sure to use a new variable so - * on the second pass it is not clipped. */ - CurFc = Fc_output_per_side; - if (Fc_output_per_side > num_wire_muxes) - { - *Fc_clipped = TRUE; - CurFc = num_wire_muxes; - } - - if (k == 0) - { - init_mux = (count_inc) % num_wire_muxes; - count_inc += CurFc; - } - else - { - init_mux = (count_dec) % num_wire_muxes; - count_dec += CurFc; - } - - for (iconn = 0; iconn < CurFc; iconn++) - { - /* FINALLY, make the outpin to mux connection */ - /* Latest update: I'm not using Uniform Pattern, but a similarly staggered pattern */ - to_node = - wire_muxes[(init_mux + - iconn) % num_wire_muxes]; - - L_rr_node[to_node].num_opin_drivers++; /* keep track of mux size */ - to_track = L_rr_node[to_node].ptc_num; - - if (FALSE == L_rr_edge_done[to_node]) - { - /* Use of alloc_and_load_edges_and_switches - * must be accompanied by rr_edge_done check. */ - L_rr_edge_done[to_node] = TRUE; - edge_list = - insert_in_edge_list(edge_list, - to_node, - seg_details - [to_track]. - wire_switch); - num_edges++; - } - } - } - - if (num_edges < 1) - { - vpr_printf(TIO_MESSAGE_ERROR, "opin %d at (%d,%d) does not connect to any tracks.\n", - L_rr_node[from_node].ptc_num, L_rr_node[from_node].xlow, L_rr_node[from_node].ylow); - exit(1); - } - - alloc_and_load_edges_and_switches(L_rr_node, from_node, num_edges, - L_rr_edge_done, edge_list); - } -} -#endif - -#if MUX_SIZE_DIST_DISPLAY -/* This routine prints and dumps statistics on the mux sizes on a sblock - * per sblock basis, over the entire chip. Mux sizes should be balanced (off by - * at most 1) for all muxes in the same sblock in the core, and corner sblocks. - * Fringe sblocks will have imbalance due to missing one side and constrains on - * where wires must connect. Comparing two core sblock sblocks, muxes need not - * be balanced if W is not quantized to 2L multiples, again for reasons that - * there could be sblocks with different number of muxes but same number of incoming - * wires that need to make connections to these muxes (we don't want to under-connect - * user-specified Fc and Fs). */ -static void -view_mux_size_distribution(t_ivec *** L_rr_node_indices, - int nodes_per_chan, - t_seg_details * seg_details_x, - t_seg_details * seg_details_y) -{ - - int i, j, itrack, seg_num, chan_num, max_len; - int start, end, inode, max_value, min_value; - int array_count, k, num_muxes; - short direction, side; - float *percent_range_array; - float percent_range, percent_range_sum, avg_percent_range; - float std_dev_percent_range, deviation_f; - int range, *range_array, global_max_range; - float avg_range, range_sum, std_dev_range; - t_seg_details *seg_details; - t_mux *new_mux, *sblock_mux_list_head, *current, *next; - -#ifdef ENABLE_DUMP - FILE *dump_file_per_sblock, *dump_file; -#endif /* ENABLE_DUMP */ - t_mux_size_distribution *distr_list, *distr_current, *new_distribution, - *distr_next; - -#ifdef ENABLE_DUMP - dump_file = my_fopen("mux_size_dump.txt", "w", 0); - dump_file_per_sblock = my_fopen("mux_size_per_sblock_dump.txt", "w", 0); -#endif /* ENABLE_DUMP */ - - sblock_mux_list_head = NULL; - percent_range_array = - (float *)my_malloc((nx - 1) * (ny - 1) * sizeof(float)); - range_array = (int *)my_malloc((nx - 1) * (ny - 1) * sizeof(int)); - array_count = 0; - percent_range_sum = 0.0; - range_sum = 0.0; - global_max_range = 0; - min_value = 0; - max_value = 0; - seg_num = 0; - chan_num = 0; - direction = 0; - seg_details = 0; - max_len = 0; - distr_list = NULL; - - /* With the specified range, I'm only looking at core sblocks */ - for (j = (ny - 1); j > 0; j--) - { - for (i = 1; i < nx; i++) - { - num_muxes = 0; - for (side = 0; side < 4; side++) - { - switch (side) - { - case LEFT: - seg_num = i; - chan_num = j; - direction = DEC_DIRECTION; /* only DEC have muxes in that sblock */ - seg_details = seg_details_x; - max_len = nx; - break; - - case RIGHT: - seg_num = i + 1; - chan_num = j; - direction = INC_DIRECTION; - seg_details = seg_details_x; - max_len = nx; - break; - - case TOP: - seg_num = j + 1; - chan_num = i; - direction = INC_DIRECTION; - seg_details = seg_details_y; - max_len = ny; - break; - - case BOTTOM: - seg_num = j; - chan_num = i; - direction = DEC_DIRECTION; - seg_details = seg_details_y; - max_len = ny; - break; - - default: - assert(FALSE); - } - - assert(nodes_per_chan > 0); - for (itrack = 0; itrack < nodes_per_chan; itrack++) - { - start = - get_seg_start(seg_details, itrack, - seg_num, chan_num); - end = - get_seg_end(seg_details, itrack, - start, chan_num, max_len); - - if ((seg_details[itrack].direction == - direction) && (((start == seg_num) - && (direction == - INC_DIRECTION)) - || ((end == seg_num) - && (direction == - DEC_DIRECTION)))) - { /* mux found */ - num_muxes++; - if (side == LEFT || side == RIGHT) - { /* CHANX */ - inode = - get_rr_node_index - (seg_num, chan_num, - CHANX, itrack, - L_rr_node_indices); - } - else - { - assert((side == TOP) || (side == BOTTOM)); /* CHANY */ - inode = - get_rr_node_index - (chan_num, seg_num, - CHANY, itrack, - L_rr_node_indices); - } - - new_mux = (t_mux *) - my_malloc(sizeof(t_mux)); - new_mux->size = - rr_node[inode]. - num_wire_drivers + - rr_node[inode]. - num_opin_drivers; - new_mux->next = NULL; - - /* insert in linked list, descending */ - if (sblock_mux_list_head == NULL) - { - /* first entry */ - sblock_mux_list_head = - new_mux; - } - else if (sblock_mux_list_head-> - size < new_mux->size) - { - /* insert before head */ - new_mux->next = - sblock_mux_list_head; - sblock_mux_list_head = - new_mux; - } - else - { - /* insert after head */ - current = - sblock_mux_list_head; - next = current->next; - - while ((next != NULL) - && (next->size > - new_mux->size)) - { - current = next; - next = - current->next; - } - - if (next == NULL) - { - current->next = - new_mux; - } - else - { - new_mux->next = - current->next; - current->next = - new_mux; - } - } - /* end of insert in linked list */ - } - } - } /* end of mux searching over all four sides of sblock */ - /* now sblock_mux_list_head holds a linked list of all muxes in this sblock */ - - current = sblock_mux_list_head; - -#ifdef ENABLE_DUMP - fprintf(dump_file_per_sblock, - "sblock at (%d, %d) has mux sizes: {", i, j); -#endif /* ENABLE_DUMP */ - - if (current != NULL) - { - max_value = min_value = current->size; - } - while (current != NULL) - { - if (max_value < current->size) - max_value = current->size; - if (min_value > current->size) - min_value = current->size; - -#ifdef ENABLE_DUMP - fprintf(dump_file_per_sblock, "%d ", - current->size); - fprintf(dump_file, "%d\n", current->size); -#endif /* ENABLE_DUMP */ - - current = current->next; - } - -#ifdef ENABLE_DUMP - fprintf(dump_file_per_sblock, "}\n\tmax: %d\tmin:%d", - max_value, min_value); -#endif /* ENABLE_DUMP */ - - range = max_value - min_value; - percent_range = ((float)range) / ((float)min_value); - - if (global_max_range < range) - global_max_range = range; - -#ifdef ENABLE_DUMP - fprintf(dump_file_per_sblock, - "\t\trange: %d\t\tpercent range:%.2f\n", - range, percent_range); -#endif /* ENABLE_DUMP */ - - percent_range_array[array_count] = percent_range; - range_array[array_count] = range; - - percent_range_sum += percent_range; - range_sum += range; - - array_count++; - - /* I will use a distribution for each (core) sblock type. - * There are more than 1 type of sblocks, - * when quantization of W to 2L multiples is not observed. */ - - distr_current = distr_list; - while (distr_current != NULL - && distr_current->mux_count != num_muxes) - { - distr_current = distr_current->next; - } - - if (distr_current == NULL) - { - /* Create a distribution for the new sblock type, - * and put it as head of linked list by convention */ - - new_distribution = (t_mux_size_distribution *) - my_malloc(sizeof(t_mux_size_distribution)); - new_distribution->mux_count = num_muxes; - new_distribution->max_index = max_value; - new_distribution->distr = - (int *)my_calloc(max_value + 1, sizeof(int)); - - /* filling in the distribution */ - current = sblock_mux_list_head; - while (current != NULL) - { - assert(current->size <= - new_distribution->max_index); - new_distribution->distr[current->size]++; - current = current->next; - } - - /* add it to head */ - new_distribution->next = distr_list; - distr_list = new_distribution; - } - else - { - /* distr_current->mux_count == num_muxes so add this sblock's mux sizes in this distribution */ - current = sblock_mux_list_head; - - while (current != NULL) - { - if (current->size > - distr_current->max_index) - { - /* needs to realloc to expand the distribution array to hold the new large-valued data */ - distr_current->distr = - my_realloc(distr_current-> - distr, - (current->size + - 1) * sizeof(int)); - - /* initializing the newly allocated elements */ - for (k = - (distr_current->max_index + - 1); k <= current->size; k++) - distr_current->distr[k] = 0; - - distr_current->max_index = - current->size; - distr_current->distr[current-> - size]++; - } - else - { - distr_current->distr[current-> - size]++; - } - current = current->next; - } - } - - /* done - now free memory */ - current = sblock_mux_list_head; - while (current != NULL) - { - next = current->next; - free(current); - current = next; - } - sblock_mux_list_head = NULL; - } - } - - avg_percent_range = (float)percent_range_sum / array_count; - avg_range = (float)range_sum / array_count; - - percent_range_sum = 0.0; - range_sum = 0.0; - for (k = 0; k < array_count; k++) - { - deviation_f = (percent_range_array[k] - avg_percent_range); - percent_range_sum += deviation_f * deviation_f; - - deviation_f = ((float)range_array[k] - avg_range); - range_sum += deviation_f * deviation_f; - } - std_dev_percent_range = - sqrt(percent_range_sum / ((float)array_count - 1.0)); - std_dev_range = sqrt(range_sum / ((float)array_count - 1.0)); - vpr_printf(TIO_MESSAGE_INFO, "==== MUX size statistics ====\n"); - vpr_printf(TIO_MESSAGE_INFO, "Max range of mux size within a sblock: %d\n", global_max_range); - vpr_printf(TIO_MESSAGE_INFO, "Average range of mux size within a sblock: %.2f\n", avg_range); - vpr_printf(TIO_MESSAGE_INFO, "Std dev of range of mux size within a sblock: %.2f\n", std_dev_range); - vpr_printf(TIO_MESSAGE_INFO, "Average percent range of mux size within a sblock: %.2f%%\n", avg_percent_range * 100.0); - vpr_printf(TIO_MESSAGE_INFO, "Std dev of percent range of mux size within a sblock: %.2f%%\n", std_dev_percent_range * 100.0); - - vpr_printf(TIO_MESSAGE_INFO, " -- Detailed MUX size distribution by sblock type -- \n"); - distr_current = distr_list; - while (distr_current != NULL) - { - print_distribution(stdout, distr_current); - - /* free */ - distr_next = distr_current->next; - - free(distr_current->distr); - free(distr_current); - - distr_current = distr_next; - } - - free(percent_range_array); - free(range_array); -#ifdef ENABLE_DUMP - fclose(dump_file_per_sblock); - fclose(dump_file); -#endif /* ENABLE_DUMP */ -} - -static void -print_distribution(FILE * fptr, - t_mux_size_distribution * distr_struct) -{ - int *distr; - int k; - float sum; - boolean zeros; - - distr = distr_struct->distr; - fprintf(fptr, - "For Sblocks containing %d MUXes, the MUX size distribution is:\n", - distr_struct->mux_count); - fprintf(fptr, "\t\t\tSize\t\t\tFrequency (percent)\n"); - - sum = 0.0; - for (k = 0; k <= distr_struct->max_index; k++) - sum += distr[k]; - - zeros = TRUE; - for (k = 0; k <= distr_struct->max_index; k++) - { - if (zeros && (distr[k] == 0)) - { - /* do nothing for leading string of zeros */ - } - else - { - zeros = FALSE; /* leading string of zeros ended */ - fprintf(fptr, "\t\t\t%d\t\t\t%d (%.2f%%)\n", k, distr[k], - (float)distr[k] / sum * 100.0); - } - } - fprintf(fptr, "\nEnd of this Sblock MUX size distribution.\n"); - -} -#endif - -/** - * Parse out which CLB pins should connect directly to which other CLB pins then store that in a clb_to_clb_directs data structure - * This data structure supplements the the info in the "directs" data structure - * TODO: The function that does this parsing in placement is poorly done because it lacks generality on heterogeniety, should replace with this one -static t_clb_to_clb_directs * alloc_and_load_clb_to_clb_directs(INP t_direct_inf *directs, INP int num_directs) { - int i, j; - t_clb_to_clb_directs *clb_to_clb_directs; - char *pb_type_name, *port_name; - int start_pin_index, end_pin_index; - t_pb_type *pb_type; - - clb_to_clb_directs = (t_clb_to_clb_directs*)my_calloc(num_directs, sizeof(t_clb_to_clb_directs)); - - pb_type_name = NULL; - port_name = NULL; - - for(i = 0; i < num_directs; i++) { - pb_type_name = (char*)my_malloc((strlen(directs[i].from_pin) + strlen(directs[i].to_pin)) * sizeof(char)); - port_name = (char*)my_malloc((strlen(directs[i].from_pin) + strlen(directs[i].to_pin)) * sizeof(char)); - - // Load from pins - // Parse out the pb_type name, port name, and pin range - parse_direct_pin_name(directs[i].from_pin, directs[i].line, &start_pin_index, &end_pin_index, pb_type_name, port_name); - - // Figure out which type, port, and pin is used - for(j = 0; j < num_types; j++) { - if(strcmp(type_descriptors[j].name, pb_type_name) == 0) { - break; - } - } - assert(j < num_types); - clb_to_clb_directs[i].from_clb_type = &type_descriptors[j]; - pb_type = clb_to_clb_directs[i].from_clb_type->pb_type; - - for(j = 0; j < pb_type->num_ports; j++) { - if(strcmp(pb_type->ports[j].name, port_name) == 0) { - break; - } - } - assert(j < pb_type->num_ports); - - if(start_pin_index == OPEN) { - assert(start_pin_index == end_pin_index); - start_pin_index = 0; - end_pin_index = pb_type->ports[j].num_pins - 1; - } - get_blk_pin_from_port_pin(clb_to_clb_directs[i].from_clb_type->index, j, start_pin_index, &clb_to_clb_directs[i].from_clb_pin_start_index); - get_blk_pin_from_port_pin(clb_to_clb_directs[i].from_clb_type->index, j, end_pin_index, &clb_to_clb_directs[i].from_clb_pin_end_index); - - // Load to pins - // Parse out the pb_type name, port name, and pin range - parse_direct_pin_name(directs[i].to_pin, directs[i].line, &start_pin_index, &end_pin_index, pb_type_name, port_name); - - // Figure out which type, port, and pin is used - for(j = 0; j < num_types; j++) { - if(strcmp(type_descriptors[j].name, pb_type_name) == 0) { - break; - } - } - assert(j < num_types); - clb_to_clb_directs[i].to_clb_type = &type_descriptors[j]; - pb_type = clb_to_clb_directs[i].to_clb_type->pb_type; - - for(j = 0; j < pb_type->num_ports; j++) { - if(strcmp(pb_type->ports[j].name, port_name) == 0) { - break; - } - } - assert(j < pb_type->num_ports); - - if(start_pin_index == OPEN) { - assert(start_pin_index == end_pin_index); - start_pin_index = 0; - end_pin_index = pb_type->ports[j].num_pins - 1; - } - - get_blk_pin_from_port_pin(clb_to_clb_directs[i].to_clb_type->index, j, start_pin_index, &clb_to_clb_directs[i].to_clb_pin_start_index); - get_blk_pin_from_port_pin(clb_to_clb_directs[i].to_clb_type->index, j, end_pin_index, &clb_to_clb_directs[i].to_clb_pin_end_index); - - if(abs(clb_to_clb_directs[i].from_clb_pin_start_index - clb_to_clb_directs[i].from_clb_pin_end_index) != abs(clb_to_clb_directs[i].to_clb_pin_start_index - clb_to_clb_directs[i].to_clb_pin_end_index)) { - vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Range mismatch from %s to %s.\n", directs[i].line, directs[i].from_pin, directs[i].to_pin); - exit(1); - } - - free(pb_type_name); - free(port_name); - } - return clb_to_clb_directs; -} - */ - -/* Add all direct clb-pin-to-clb-pin edges to given opin */ -static int get_opin_direct_connecions(int x, int y, int opin, INOUTP t_linked_edge ** edge_list_ptr, INP t_ivec *** L_rr_node_indices, - INP int delayless_switch, INP t_direct_inf *directs, INP int num_directs, INP t_clb_to_clb_directs *clb_to_clb_directs) { - t_type_ptr type; - int grid_ofs; - int i, ipin, inode; - t_linked_edge *edge_list_head; - int max_index, min_index, offset, swap; - int new_edges; - - type = grid[x][y].type; - edge_list_head = *edge_list_ptr; - new_edges = 0; - - /* Iterate through all direct connections */ - for(i = 0; i < num_directs; i++) { - /* Find matching direct clb-to-clb connections with the same type as current grid location */ - if(clb_to_clb_directs[i].from_clb_type == type) { - /* Compute index of opin with regards to given pins */ - if(clb_to_clb_directs[i].from_clb_pin_start_index > clb_to_clb_directs[i].from_clb_pin_end_index) { - swap = TRUE; - max_index = clb_to_clb_directs[i].from_clb_pin_start_index; - min_index = clb_to_clb_directs[i].from_clb_pin_end_index; - } else { - swap = FALSE; - min_index = clb_to_clb_directs[i].from_clb_pin_start_index; - max_index = clb_to_clb_directs[i].from_clb_pin_end_index; - } - if(max_index >= opin && min_index <= opin) { - offset = opin - min_index; - /* This opin is specified to connect directly to an ipin, now compute which ipin to connect to */ - if(x + directs[i].x_offset < nx + 1 && - x + directs[i].x_offset > 0 && - y + directs[i].y_offset < ny + 1 && - y + directs[i].y_offset > 0) { - ipin = OPEN; - if(clb_to_clb_directs[i].to_clb_pin_start_index > clb_to_clb_directs[i].to_clb_pin_end_index) { - if(swap == TRUE) { - ipin = clb_to_clb_directs[i].to_clb_pin_end_index + offset; - } else { - ipin = clb_to_clb_directs[i].to_clb_pin_start_index - offset; - } - } else { - if(swap == TRUE) { - ipin = clb_to_clb_directs[i].to_clb_pin_end_index - offset; - } else { - ipin = clb_to_clb_directs[i].to_clb_pin_start_index + offset; - } - } - /* Add new ipin edge to list of edges */ - grid_ofs = grid[x + directs[i].x_offset][y + directs[i].y_offset].offset; - inode = get_rr_node_index(x + directs[i].x_offset, y + directs[i].y_offset - grid_ofs, IPIN, ipin, L_rr_node_indices); - edge_list_head = insert_in_edge_list(edge_list_head, inode, delayless_switch); - new_edges++; - } - } - } - } - *edge_list_ptr = edge_list_head; - return new_edges; -} - - - diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph.h b/vpr7_x2p/vpr/SRC/route/rr_graph.h deleted file mode 100755 index a0dd91644..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph.h +++ /dev/null @@ -1,90 +0,0 @@ -#ifndef RR_GRAPH_H -#define RR_GRAPH_H - -enum e_graph_type { - GRAPH_GLOBAL, /* One node per channel with wire capacity > 1 and full connectivity */ - GRAPH_BIDIR, /* Detailed bidirectional graph */ - GRAPH_UNIDIR, /* Detailed unidir graph, untilable */ - /* RESEARCH TODO: Get this option debugged */ - GRAPH_UNIDIR_TILEABLE /* Detail unidir graph with wire groups multiples of 2*L */ -}; -typedef enum e_graph_type t_graph_type; - -/* Warnings about the routing graph that can be returned. - * This is to avoid output messages during a value sweep */ -enum { - RR_GRAPH_NO_WARN = 0x00, - RR_GRAPH_WARN_FC_CLIPPED = 0x01, - RR_GRAPH_WARN_CHAN_WIDTH_CHANGED = 0x02 -}; - -void build_rr_graph(INP t_graph_type graph_type, - INP int L_num_types, - INP t_type_ptr types, - INP int L_nx, - INP int L_ny, - INP struct s_grid_tile **L_grid, - INP int chan_width, - INP struct s_chan_width_dist *chan_capacity_inf, - INP enum e_switch_block_type sb_type, - INP int Fs, - INP enum e_switch_block_type sb_sub_type, INP int sub_Fs, INP boolean wire_opposite_side, - INP int num_seg_types, - INP int num_switches, - INP t_segment_inf * segment_inf, - INP int global_route_switch, - INP int delayless_switch, - INP t_timing_inf timing_inf, - INP int wire_to_ipin_switch, - INP enum e_base_cost_type base_cost_type, - INP t_direct_inf *directs, - INP int num_directs, - INP boolean ignore_Fc_0, - OUTP int *Warnings, - /* Xifan TANG: Switch Segment Pattern Support*/ - int num_swseg_pattern, - t_swseg_pattern_inf* swseg_patterns, - boolean opin_to_cb_fast_edges, - boolean opin_logic_eq_edges); - -void free_rr_graph(void); - -void dump_rr_graph(INP const char *file_name); -void print_rr_indexed_data(FILE * fp, int index); /* For debugging only */ -void load_net_rr_terminals(t_ivec *** L_rr_node_indices); - -void print_rr_node(FILE *fp, t_rr_node *L_rr_node, int inode); - -int ** -alloc_and_load_actual_fc(INP int L_num_types, INP t_type_ptr types, - INP int nodes_per_chan, INP boolean is_Fc_out, - INP enum e_directionality directionality, OUTP boolean * Fc_clipped, INP boolean ignore_Fc_0); - -void rr_graph_externals(const t_timing_inf timing_inf, - const t_segment_inf * segment_inf, const int num_seg_types, const int nodes_per_chan, - const int wire_to_ipin_switch, const enum e_base_cost_type base_cost_type); - -/* Xifan Tang: Functions shared by tileable rr_graph generator */ - -int ****alloc_and_load_pin_to_track_map(INP enum e_pin_type pin_type, - INP int nodes_per_chan, INP int *Fc, INP t_type_ptr Type, - INP boolean perturb_switch_pattern, - INP enum e_directionality directionality); - -struct s_ivec ***alloc_and_load_track_to_pin_lookup( - INP int ****pin_to_track_map, INP int *Fc, INP int height, - INP int num_pins, INP int nodes_per_chan); - -boolean * -alloc_and_load_perturb_ipins(INP int nodes_per_chan, INP int L_num_types, - INP int **Fc_in, INP int **Fc_out, INP enum e_directionality directionality); - -void free_type_pin_to_track_map(int***** ipin_to_track_map, - t_type_ptr types); - -void free_type_track_to_ipin_map(struct s_ivec**** track_to_pin_map, - t_type_ptr types, int nodes_per_chan); - - -#endif - diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph2.c b/vpr7_x2p/vpr/SRC/route/rr_graph2.c deleted file mode 100755 index 3e9d8a037..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph2.c +++ /dev/null @@ -1,2362 +0,0 @@ -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph2.h" -#include "rr_graph_sbox.h" -#include "read_xml_arch_file.h" - -/*mrFPGA: Xifan TANG */ -#include "mrfpga_globals.h" -#include "mrfpga_api.h" -/* end */ - -#define ALLOW_SWITCH_OFF - -/* WMF: May 07 I put this feature in, but on May 09 in my testing phase - * I found that for Wilton, this feature is bad, since Wilton is already doing - * a reverse. */ -#define ENABLE_REVERSE 0 - -#define SAME_TRACK -5 -#define UN_SET -1 -/* Variables below are the global variables shared only amongst the rr_graph * - ************************************ routines. ******************************/ - -/* Used to keep my own list of free linked integers, for speed reasons. */ - -t_linked_edge *free_edge_list_head = NULL; - -/*************************** Variables local to this module *****************/ - -/* Two arrays below give the rr_node_index of the channel segment at * - * (i,j,track) for fast index lookup. */ - -/* UDSD Modifications by WMF Begin */ - -/* The sblock_pattern_init_mux_lookup contains the assignment of incoming - * wires to muxes. More specifically, it only contains the assignment of - * M-to-N cases. WMF_BETTER_COMMENTS */ - -/* UDSD MOdifications by WMF End */ - -/************************** Subroutines local to this module ****************/ - -static void get_switch_type(boolean is_from_sbox, boolean is_to_sbox, - short from_node_switch, short to_node_switch, short switch_types[2]); - -static void load_chan_rr_indices(INP int nodes_per_chan, INP int chan_len, - INP int num_chans, INP t_rr_type type, INP t_seg_details * seg_details, - INOUTP int *index, INOUTP t_ivec *** indices); - -static int get_bidir_track_to_chan_seg(INP struct s_ivec conn_tracks, - INP t_ivec *** L_rr_node_indices, INP int to_chan, INP int to_seg, - INP int to_sb, INP t_rr_type to_type, INP t_seg_details * seg_details, - INP boolean from_is_sbox, INP int from_switch, - INOUTP boolean * L_rr_edge_done, - INP enum e_directionality directionality, - INOUTP struct s_linked_edge **edge_list); - -static int get_unidir_track_to_chan_seg(INP boolean is_end_sb, - INP int from_track, INP int to_chan, INP int to_seg, INP int to_sb, - INP t_rr_type to_type, INP int nodes_per_chan, INP int L_nx, - INP int L_ny, INP enum e_side from_side, INP enum e_side to_side, - INP int Fs_per_side, INP int *opin_mux_size, - INP short *****sblock_pattern, INP t_ivec *** L_rr_node_indices, - INP t_seg_details * seg_details, INOUTP boolean * L_rr_edge_done, - OUTP boolean * Fs_clipped, INOUTP struct s_linked_edge **edge_list); - -static int vpr_to_phy_track(INP int itrack, INP int chan_num, INP int seg_num, - INP t_seg_details * seg_details, - INP enum e_directionality directionality); - -static int *get_seg_track_counts(INP int num_sets, INP int num_seg_types, - INP t_segment_inf * segment_inf, INP boolean use_full_seg_groups); - -static int *label_wire_muxes(INP int chan_num, INP int seg_num, - INP t_seg_details * seg_details, INP int max_len, - INP enum e_direction dir, INP int nodes_per_chan, - OUTP int *num_wire_muxes); - -static int *label_wire_muxes_for_balance(INP int chan_num, INP int seg_num, - INP t_seg_details * seg_details, INP int max_len, - INP enum e_direction direction, INP int nodes_per_chan, - INP int *num_wire_muxes, INP t_rr_type chan_type, - INP int *opin_mux_size, INP t_ivec *** L_rr_node_indices); - -static int *label_incoming_wires(INP int chan_num, INP int seg_num, - INP int sb_seg, INP t_seg_details * seg_details, INP int max_len, - INP enum e_direction dir, INP int nodes_per_chan, - OUTP int *num_incoming_wires, OUTP int *num_ending_wires); - -static int find_label_of_track(int *wire_mux_on_track, int num_wire_muxes, - int from_track); - -/* mrFPGA : Xifan TANG*/ -/* -static int get_seg_to_seg(INP t_ivec*** L_rr_node_indices, - INP int to_chan, - INP int to_seg, - INP int track, - INP t_rr_type type, - INP t_seg_details* seg_details, - INOUTP struct s_linked_edge** edge_list); -*/ -/* end */ - -/******************** Subroutine definitions *******************************/ - -/* This assigns tracks (individually or pairs) to segment types. - * It tries to match requested ratio. If use_full_seg_groups is - * true, then segments are assigned only in multiples of their - * length. This is primarily used for making a tileable unidir - * layout. The effect of using this is that the number of tracks - * requested will not always be met and the result will sometimes - * be over and sometimes under. - * The pattern when using use_full_seg_groups is to keep adding - * one group of the track type that wants the largest number of - * groups of tracks. Each time a group is assigned, the types - * demand is reduced by 1 unit. The process stops when we are - * no longer less than the requested number of tracks. As a final - * step, if we were closer to target before last more, undo it - * and end up with a result that uses fewer tracks than given. */ -static int * -get_seg_track_counts(INP int num_sets, INP int num_seg_types, - INP t_segment_inf * segment_inf, INP boolean use_full_seg_groups) { - int *result; - double *demand; - int i, imax, freq_sum, assigned, size; - double scale, max, reduce; - - result = (int *) my_malloc(sizeof(int) * num_seg_types); - demand = (double *) my_malloc(sizeof(double) * num_seg_types); - - /* Scale factor so we can divide by any length - * and still use integers */ - scale = 1; - freq_sum = 0; - for (i = 0; i < num_seg_types; ++i) { - scale *= segment_inf[i].length; - freq_sum += segment_inf[i].frequency; - } - reduce = scale * freq_sum; - - /* Init assignments to 0 and set the demand values */ - for (i = 0; i < num_seg_types; ++i) { - result[i] = 0; - demand[i] = scale * num_sets * segment_inf[i].frequency; - if (use_full_seg_groups) { - demand[i] /= segment_inf[i].length; - } - } - - /* Keep assigning tracks until we use them up */ - assigned = 0; - size = 0; - imax = 0; - while (assigned < num_sets) { - /* Find current maximum demand */ - max = 0; - for (i = 0; i < num_seg_types; ++i) { - if (demand[i] > max) { - imax = i; - max = demand[i]; - } - } - - /* Assign tracks to the type and reduce the types demand */ - size = (use_full_seg_groups ? segment_inf[imax].length : 1); - demand[imax] -= reduce; - result[imax] += size; - assigned += size; - } - - /* Undo last assignment if we were closer to goal without it */ - if ((assigned - num_sets) > (size / 2)) { - result[imax] -= size; - } - - /* Free temps */ - if (demand) { - free(demand); - demand = NULL; - } - - /* This must be freed by caller */ - return result; -} - -t_seg_details * -alloc_and_load_seg_details(INOUTP int *nodes_per_chan, INP int max_len, - INP int num_seg_types, INP t_segment_inf * segment_inf, - INP boolean use_full_seg_groups, INP boolean is_global_graph, - INP enum e_directionality directionality) { - - /* Allocates and loads the seg_details data structure. Max_len gives the * - * maximum length of a segment (dimension of array). The code below tries * - * to: * - * (1) stagger the start points of segments of the same type evenly; * - * (2) spread out the limited number of connection boxes or switch boxes * - * evenly along the length of a segment, starting at the segment ends; * - * (3) stagger the connection and switch boxes on different long lines, * - * as they will not be staggered by different segment start points. */ - - int i, cur_track, ntracks, itrack, length, j, index; - int wire_switch, opin_switch, fac, num_sets, tmp; - int group_start, first_track; - int *sets_per_seg_type = NULL; - t_seg_details *seg_details = NULL; - boolean longline; - - /* Unidir tracks are assigned in pairs, and bidir tracks individually */ - if (directionality == BI_DIRECTIONAL) { - fac = 1; - } else { - assert(directionality == UNI_DIRECTIONAL); - fac = 2; - } - assert(*nodes_per_chan % fac == 0); - - /* Map segment type fractions and groupings to counts of tracks */ - sets_per_seg_type = get_seg_track_counts((*nodes_per_chan / fac), - num_seg_types, segment_inf, use_full_seg_groups); - - /* Count the number tracks actually assigned. */ - tmp = 0; - for (i = 0; i < num_seg_types; ++i) { - tmp += sets_per_seg_type[i] * fac; - } - assert(use_full_seg_groups || (tmp == *nodes_per_chan)); - *nodes_per_chan = tmp; - // Xifan TANG Note: Alloc segments - seg_details = (t_seg_details *) my_malloc( - *nodes_per_chan * sizeof(t_seg_details)); - - /* Setup the seg_details data */ - cur_track = 0; - for (i = 0; i < num_seg_types; ++i) { - first_track = cur_track; - - num_sets = sets_per_seg_type[i]; - ntracks = fac * num_sets; - if (ntracks < 1) { - continue; - } - /* Avoid divide by 0 if ntracks */ - longline = segment_inf[i].longline; - length = segment_inf[i].length; - if (longline) { - length = max_len; - } - // Xifan TANG Note: Set the input and output switches - wire_switch = segment_inf[i].wire_switch; - opin_switch = segment_inf[i].opin_switch; - /* Xifan TANG Note: I think it should be && not || in this assert, - * Uni-direcitonal routing architecture, wire_switch and opin_switch should be the same... - */ - //assert( - // (wire_switch == opin_switch) || (directionality != UNI_DIRECTIONAL)); - /* END */ - - /* mrFPGA: Xifan TANG */ - assert((wire_switch == opin_switch) - || (directionality != UNI_DIRECTIONAL) || (is_mrFPGA) ); - /* END */ - - /* Set up the tracks of same type */ - group_start = 0; - for (itrack = 0; itrack < ntracks; itrack++) { - - /* Remember the start track of the current wire group */ - if ((itrack / fac) % length == 0 && (itrack % fac) == 0) { - group_start = cur_track; - } - - seg_details[cur_track].length = length; - seg_details[cur_track].longline = longline; - - /* Stagger the start points in for each track set. The - * pin mappings should be aware of this when chosing an - * intelligent way of connecting pins and tracks. - * cur_track is used as an offset so that extra tracks - * from different segment types are hopefully better - * balanced. */ - /* Original VPR */ - /* seg_details[cur_track].start = (cur_track / fac) % length + 1; */ - /* end */ - /* mrFPGA: Xifan TANG */ - seg_details[cur_track].start = (cur_track / fac) % length + (is_stack ? 0 : 1); - /* end */ - - /* These properties are used for vpr_to_phy_track to determine - * * twisting of wires. */ - seg_details[cur_track].group_start = group_start; - seg_details[cur_track].group_size = - std::min(ntracks + first_track - group_start, - length * fac); - assert(0 == seg_details[cur_track].group_size % fac); - if (0 == seg_details[cur_track].group_size) { - seg_details[cur_track].group_size = length * fac; - } - - /* Setup the cb and sb patterns. Global route graphs can't depopulate cb and sb - * since this is a property of a detailed route. */ - seg_details[cur_track].cb = (boolean *) my_malloc( - length * sizeof(boolean)); - seg_details[cur_track].sb = (boolean *) my_malloc( - (length + 1) * sizeof(boolean)); - for (j = 0; j < length; ++j) { /* apply connection block existence */ - if (is_global_graph) { - seg_details[cur_track].cb[j] = TRUE; - } else { - index = j; - - /* Rotate longline's so they vary across the FPGA */ - if (longline) { - index = (index + itrack) % length; - } - - /* Reverse the order for tracks going in DEC_DIRECTION */ - if (itrack % fac == 1) { - index = (length - 1) - j; - } - - /* Use the segment's pattern. */ - index = j % segment_inf[i].cb_len; - seg_details[cur_track].cb[j] = segment_inf[i].cb[index]; - } - } - for (j = 0; j < (length + 1); ++j) { /* apply switch block existence */ - if (is_global_graph) { - seg_details[cur_track].sb[j] = TRUE; - } else { - index = j; - - /* Rotate longline's so they vary across the FPGA */ - if (longline) { - index = (index + itrack) % (length + 1); - } - - /* Reverse the order for tracks going in DEC_DIRECTION */ - if (itrack % fac == 1) { - index = ((length + 1) - 1) - j; - } - - /* Use the segment's pattern. */ - index = j % segment_inf[i].sb_len; - seg_details[cur_track].sb[j] = segment_inf[i].sb[index]; - } - } - - seg_details[cur_track].Rmetal = segment_inf[i].Rmetal; - seg_details[cur_track].Cmetal = segment_inf[i].Cmetal; - //seg_details[cur_track].Cmetal_per_m = segment_inf[i].Cmetal_per_m; - - seg_details[cur_track].wire_switch = wire_switch; - seg_details[cur_track].opin_switch = opin_switch; - - if (BI_DIRECTIONAL == directionality) { - seg_details[cur_track].direction = BI_DIRECTION; - } else { - assert(UNI_DIRECTIONAL == directionality); - seg_details[cur_track].direction = - (itrack % 2) ? DEC_DIRECTION : INC_DIRECTION; - } - - switch (segment_inf[i].directionality) { - case UNI_DIRECTIONAL: - seg_details[cur_track].drivers = SINGLE; - break; - case BI_DIRECTIONAL: - seg_details[cur_track].drivers = MULTI_BUFFERED; - break; - } - - seg_details[cur_track].index = i; - - ++cur_track; - } - } /* End for each segment type. */ - - /* free variables */ - free(sets_per_seg_type); - - return seg_details; -} - -void free_seg_details(t_seg_details * seg_details, int nodes_per_chan) { - - /* Frees all the memory allocated to an array of seg_details structures. */ - - int i; - - for (i = 0; i < nodes_per_chan; i++) { - free(seg_details[i].cb); - free(seg_details[i].sb); - } - free(seg_details); -} - -/* Dumps out an array of seg_details structures to file fname. Used only * - * for debugging. */ -void dump_seg_details(t_seg_details * seg_details, int nodes_per_chan, - const char *fname) { - - FILE *fp; - int i, j; - const char *drivers_names[] = { "multi_buffered", "single" }; - const char *direction_names[] = { "inc_direction", "dec_direction", - "bi_direction" }; - - fp = my_fopen(fname, "w", 0); - - for (i = 0; i < nodes_per_chan; i++) { - fprintf(fp, "Track: %d.\n", i); - fprintf(fp, "Length: %d, Start: %d, Long line: %d " - "wire_switch: %d opin_switch: %d.\n", seg_details[i].length, - seg_details[i].start, seg_details[i].longline, - seg_details[i].wire_switch, seg_details[i].opin_switch); - - fprintf(fp, "Rmetal: %g Cmetal: %g\n", seg_details[i].Rmetal, - seg_details[i].Cmetal); - - fprintf(fp, "Direction: %s Drivers: %s\n", - direction_names[seg_details[i].direction], - drivers_names[seg_details[i].drivers]); - - fprintf(fp, "cb list: "); - for (j = 0; j < seg_details[i].length; j++) - fprintf(fp, "%d ", seg_details[i].cb[j]); - fprintf(fp, "\n"); - - fprintf(fp, "sb list: "); - for (j = 0; j <= seg_details[i].length; j++) - fprintf(fp, "%d ", seg_details[i].sb[j]); - fprintf(fp, "\n"); - - fprintf(fp, "\n"); - } - - fclose(fp); -} - -/* Returns the segment number at which the segment this track lies on * - * started. */ -int get_seg_start(INP t_seg_details * seg_details, INP int itrack, - INP int chan_num, INP int seg_num) { - - int seg_start, length, start; - - seg_start = 1; - if (FALSE == seg_details[itrack].longline) { - - length = seg_details[itrack].length; - start = seg_details[itrack].start; - - /* Start is guaranteed to be between 1 and length. Hence adding length to * - * the quantity in brackets below guarantees it will be nonnegative. */ - /* Original VPR */ - /* assert(start > 0); */ - /* end */ - /* mrFPGA: Xifan TANG */ - assert(is_stack ? start >= 0: start > 0); - /* end */ - assert(start <= length); - - /* NOTE: Start points are staggered between different channels. - * The start point must stagger backwards as chan_num increases. - * Unidirectional routing expects this to allow the N-to-N - * assumption to be made with respect to ending wires in the core. */ - /* mrFPGA: Xifan TANG */ - seg_start = seg_num - (seg_num - (is_stack ? 1 : 0) + length + chan_num - start) % length; - seg_start = std::max(seg_start, is_stack ? 0 : 1); - /* end */ - /* Original VPR */ - /* - seg_start = seg_num - (seg_num + length + chan_num - start) % length; - if (seg_start < 1) { - seg_start = 1; - } - */ - /* end */ - } - - return seg_start; -} - -int get_seg_end(INP t_seg_details * seg_details, INP int itrack, INP int istart, - INP int chan_num, INP int seg_max) { - int len, ofs, end, first_full; - - len = seg_details[itrack].length; - ofs = seg_details[itrack].start; - - /* Normal endpoint */ - end = istart + len - 1; - - /* If start is against edge it may have been clipped */ - /* Original VPR*/ - /* if (1 == istart) { */ - /* end */ - /* mrFPGA: Xifan TANG */ - if ((is_stack ? 0 : 1) == istart) { - /* end */ - /* If the (staggered) startpoint of first full wire wasn't - * also 1, we must be the clipped wire */ - /* Original VPR*/ - /* first_full = (len - (chan_num % len) + ofs - 1) % len + 1; */ - /* end */ - /* mrFPGA: Xifan TANG */ - first_full = (len - (chan_num - (is_stack ? 1 : 0)) % len + ofs + (is_stack ? 1: 0) - 1) % len - + (is_stack ? 0 : 1); - /* end */ - /* Original VPR*/ - /* if (first_full > 1) { */ - /* end */ - /* mrFPGA: Xifan TANG */ - if (first_full > (is_stack ? 0 : 1)) { - /* end */ - /* then we stop just before the first full seg */ - end = first_full - 1; - } - } - - /* Clip against far edge */ - if (end > seg_max) { - end = seg_max; - } - - return end; -} - -/* Returns the number of tracks to which clb opin #ipin at (i,j) connects. * - * Also stores the nodes to which this pin connects in the linked list * - * pointed to by *edge_list_ptr. */ -int get_bidir_opin_connections(INP int i, INP int j, INP int ipin, - INP struct s_linked_edge **edge_list, INP int *****opin_to_track_map, - INP int Fc, INP boolean * L_rr_edge_done, - INP t_ivec *** L_rr_node_indices, INP t_seg_details * seg_details) { - - int iside, num_conn, ofs, tr_i, tr_j, chan, seg; - int to_track, to_switch, to_node, iconn; - int is_connected_track; - t_type_ptr type; - t_rr_type to_type; - - type = grid[i][j].type; - ofs = grid[i][j].offset; - - num_conn = 0; - - /* [0..num_types-1][0..num_pins-1][0..height][0..3][0..Fc-1] */ - for (iside = 0; iside < 4; iside++) { - - /* Figure out coords of channel segment based on side */ - tr_i = ((iside == LEFT) ? (i - 1) : i); - tr_j = ((iside == BOTTOM) ? (j - 1) : j); - - to_type = ((iside == LEFT) || (iside == RIGHT)) ? CHANY : CHANX; - - chan = ((to_type == CHANX) ? tr_j : tr_i); - seg = ((to_type == CHANX) ? tr_i : tr_j); - - /* Don't connect where no tracks on fringes */ - if ((tr_i < 0) || (tr_i > nx)) { - continue; - } - if ((tr_j < 0) || (tr_j > ny)) { - continue; - } - if ((CHANX == to_type) && (tr_i < 1)) { - continue; - } - if ((CHANY == to_type) && (tr_j < 1)) { - continue; - } - - is_connected_track = FALSE; - - /* Itterate of the opin to track connections */ - for (iconn = 0; iconn < Fc; ++iconn) { - to_track = opin_to_track_map[type->index][ipin][ofs][iside][iconn]; - - /* Skip unconnected connections */ - if (OPEN == to_track || is_connected_track) { - is_connected_track = TRUE; - assert( - OPEN == opin_to_track_map[type-> index][ipin][ofs][iside] [0]); - continue; - } - - /* Only connect to wire if there is a CB */ - if (is_cbox(chan, seg, to_track, seg_details, BI_DIRECTIONAL)) { - to_switch = seg_details[to_track].wire_switch; - to_node = get_rr_node_index(tr_i, tr_j, to_type, to_track, - L_rr_node_indices); - - *edge_list = insert_in_edge_list(*edge_list, to_node, - to_switch); - L_rr_edge_done[to_node] = TRUE; - ++num_conn; - } - } - } - - return num_conn; -} - -int get_unidir_opin_connections(INP int chan, INP int seg, INP int Fc, - INP t_rr_type chan_type, INP t_seg_details * seg_details, - INOUTP t_linked_edge ** edge_list_ptr, INOUTP int **Fc_ofs, - INOUTP boolean * L_rr_edge_done, INP int max_len, - INP int nodes_per_chan, INP t_ivec *** L_rr_node_indices, - OUTP boolean * Fc_clipped) { - /* Gets a linked list of Fc nodes to connect to in given - * chan seg. Fc_ofs is used for the for the opin staggering - * pattern. */ - - int *inc_muxes = NULL; - int *dec_muxes = NULL; - int num_inc_muxes, num_dec_muxes, iconn; - int inc_inode, dec_inode; - int inc_mux, dec_mux; - int inc_track, dec_track; - int x, y; - int num_edges; - - *Fc_clipped = FALSE; - - /* Fc is assigned in pairs so check it is even. */ - assert(Fc % 2 == 0); - - /* get_rr_node_indices needs x and y coords. */ - /* Original VPR */ - //x = ((CHANX == chan_type) ? seg : chan); - //y = ((CHANX == chan_type) ? chan : seg); - /* end */ - /* mrFPGA : Xifan TANG */ - x = (((is_stack ? CHANY : CHANX) == chan_type) ? seg : chan); - y = (((is_stack ? CHANY : CHANX) == chan_type) ? chan : seg); - /* end */ - - /* Get the lists of possible muxes. */ - inc_muxes = label_wire_muxes(chan, seg, seg_details, max_len, INC_DIRECTION, - nodes_per_chan, &num_inc_muxes); - dec_muxes = label_wire_muxes(chan, seg, seg_details, max_len, DEC_DIRECTION, - nodes_per_chan, &num_dec_muxes); - - /* Clip Fc to the number of muxes. */ - if (((Fc / 2) > num_inc_muxes) || ((Fc / 2) > num_dec_muxes)) { - *Fc_clipped = TRUE; - Fc = 2 * std::min(num_inc_muxes, num_dec_muxes); - } - - /* Assign tracks to meet Fc demand */ - num_edges = 0; - for (iconn = 0; iconn < (Fc / 2); ++iconn) { - /* Figure of the next mux to use */ - inc_mux = Fc_ofs[chan][seg] % num_inc_muxes; - dec_mux = Fc_ofs[chan][seg] % num_dec_muxes; - ++Fc_ofs[chan][seg]; - - /* Figure out the track it corresponds to. */ - inc_track = inc_muxes[inc_mux]; - dec_track = dec_muxes[dec_mux]; - - /* Figure the inodes of those muxes */ - inc_inode = get_rr_node_index(x, y, chan_type, inc_track, - L_rr_node_indices); - dec_inode = get_rr_node_index(x, y, chan_type, dec_track, - L_rr_node_indices); - - /* Add to the list. */ - if (FALSE == L_rr_edge_done[inc_inode]) { - L_rr_edge_done[inc_inode] = TRUE; - *edge_list_ptr = insert_in_edge_list(*edge_list_ptr, inc_inode, - seg_details[inc_track].opin_switch); - ++num_edges; - } - if (FALSE == L_rr_edge_done[dec_inode]) { - L_rr_edge_done[dec_inode] = TRUE; - *edge_list_ptr = insert_in_edge_list(*edge_list_ptr, dec_inode, - seg_details[dec_track].opin_switch); - ++num_edges; - } - } - - if (inc_muxes) { - free(inc_muxes); - inc_muxes = NULL; - } - if (dec_muxes) { - free(dec_muxes); - dec_muxes = NULL; - } - - return num_edges; -} - -boolean is_cbox(INP int chan, INP int seg, INP int track, - INP t_seg_details * seg_details, - INP enum e_directionality directionality) { - - int length, ofs, start_seg; - - length = seg_details[track].length; - - /* Make sure they gave us correct start */ - start_seg = get_seg_start(seg_details, track, chan, seg); - - ofs = seg - start_seg; - - assert(ofs >= 0); - assert(ofs < length); - - /* If unidir segment that is going backwards, we need to flip the ofs */ - if (DEC_DIRECTION == seg_details[track].direction) { - ofs = (length - 1) - ofs; - } - - return seg_details[track].cb[ofs]; -} - -static void load_chan_rr_indices(INP int nodes_per_chan, INP int chan_len, - INP int num_chans, INP t_rr_type type, INP t_seg_details * seg_details, - INOUTP int *index, INOUTP t_ivec *** indices) { - int chan, seg, track, start, inode; - - indices[type] = (t_ivec **) my_malloc(sizeof(t_ivec *) * num_chans); - for (chan = 0; chan < num_chans; ++chan) { - indices[type][chan] = (t_ivec *) my_malloc(sizeof(t_ivec) * chan_len); - - indices[type][chan][0].nelem = 0; - indices[type][chan][0].list = NULL; - - /* Original VPR */ - /* for (seg = 1; seg < chan_len; ++seg) { */ - /* end */ - /* mrFPGA: Xifan TANG */ - for (seg = (is_stack ? 0 : 1); seg < chan_len; ++seg) { - /* end */ - /* Alloc the track inode lookup list */ - indices[type][chan][seg].nelem = nodes_per_chan; - indices[type][chan][seg].list = (int *) my_malloc( - sizeof(int) * nodes_per_chan); - for (track = 0; track < nodes_per_chan; ++track) { - indices[type][chan][seg].list[track] = OPEN; - } - } - } - - /* Original VPR */ - /* - for (chan = 0; chan < num_chans; ++chan) { - for (seg = 1; seg < chan_len; ++seg) { - */ - /* end */ - /* mrFPGA: Xifan TANG */ - for (chan = (is_stack ? 1 : 0); chan < num_chans; ++chan) { - for (seg = (is_stack ? 0 : 1); seg < chan_len; ++seg) { - /* end */ - /* Assign an inode to the starts of tracks */ - for (track = 0; track < indices[type][chan][seg].nelem; ++track) { - start = get_seg_start(seg_details, track, chan, seg); - /* Original VPR */ - /* If the start of the wire doesn't have a inode, - * assign one to it. */ - inode = indices[type][chan][start].list[track]; - if (OPEN == inode) { - inode = *index; - ++(*index); - - indices[type][chan][start].list[track] = inode; - } - /* end */ - /* Assign inode of start of wire to current position */ - indices[type][chan][seg].list[track] = inode; - } - } - } -} - -struct s_ivec *** -alloc_and_load_rr_node_indices(INP int nodes_per_chan, INP int L_nx, - INP int L_ny, INOUTP int *index, INP t_seg_details * seg_details) { - - /* Allocates and loads all the structures needed for fast lookups of the * - * index of an rr_node. rr_node_indices is a matrix containing the index * - * of the *first* rr_node at a given (i,j) location. */ - - int i, j, k, ofs; - t_ivec ***indices; - t_ivec tmp; - t_type_ptr type; - - /* Alloc the lookup table */ - indices = (t_ivec ***) my_malloc(sizeof(t_ivec **) * NUM_RR_TYPES); - indices[IPIN] = (t_ivec **) my_malloc(sizeof(t_ivec *) * (L_nx + 2)); - indices[SINK] = (t_ivec **) my_malloc(sizeof(t_ivec *) * (L_nx + 2)); - for (i = 0; i <= (L_nx + 1); ++i) { - indices[IPIN][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * (L_ny + 2)); - indices[SINK][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * (L_ny + 2)); - for (j = 0; j <= (L_ny + 1); ++j) { - indices[IPIN][i][j].nelem = 0; - indices[IPIN][i][j].list = NULL; - - indices[SINK][i][j].nelem = 0; - indices[SINK][i][j].list = NULL; - } - } - - /* Count indices for block nodes */ - for (i = 0; i <= (L_nx + 1); i++) { - for (j = 0; j <= (L_ny + 1); j++) { - ofs = grid[i][j].offset; - if (0 == ofs) { - type = grid[i][j].type; - - /* Load the pin class lookups. The ptc nums for SINK and SOURCE - * are disjoint so they can share the list. */ - tmp.nelem = type->num_class; - tmp.list = NULL; - if (tmp.nelem > 0) { - tmp.list = (int *) my_malloc(sizeof(int) * tmp.nelem); - for (k = 0; k < tmp.nelem; ++k) { - tmp.list[k] = *index; - ++(*index); - } - } - indices[SINK][i][j] = tmp; - - /* Load the pin lookups. The ptc nums for IPIN and OPIN - * are disjoint so they can share the list. */ - tmp.nelem = type->num_pins; - tmp.list = NULL; - if (tmp.nelem > 0) { - tmp.list = (int *) my_malloc(sizeof(int) * tmp.nelem); - for (k = 0; k < tmp.nelem; ++k) { - tmp.list[k] = *index; - ++(*index); - } - } - indices[IPIN][i][j] = tmp; - } - } - } - - /* Point offset blocks of a large block to base block */ - for (i = 0; i <= (L_nx + 1); i++) { - for (j = 0; j <= (L_ny + 1); j++) { - ofs = grid[i][j].offset; - if (ofs > 0) { - /* NOTE: this only supports vertical large blocks */ - indices[SINK][i][j] = indices[SINK][i][j - ofs]; - indices[IPIN][i][j] = indices[IPIN][i][j - ofs]; - } - } - } - - /* SOURCE and SINK have unique ptc values so their data can be shared. - * IPIN and OPIN have unique ptc values so their data can be shared. */ - indices[SOURCE] = indices[SINK]; - indices[OPIN] = indices[IPIN]; - - /* Original VPR */ - /* Load the data for x and y channels */ - /* - load_chan_rr_indices(nodes_per_chan, L_nx + 1, L_ny + 1, CHANX, seg_details, - index, indices); - load_chan_rr_indices(nodes_per_chan, L_ny + 1, L_nx + 1, CHANY, seg_details, - index, indices); - */ - /* end */ - /* mrFPGA : Xifan TANG */ - load_chan_rr_indices(nodes_per_chan, (is_stack ? L_ny + 1 : L_nx + 1), (is_stack ? L_nx + 1 : L_ny + 1), - CHANX, seg_details, index, indices); - load_chan_rr_indices(nodes_per_chan, (is_stack ? L_nx + 1 : L_ny + 1), (is_stack ? L_ny + 1 : L_nx + 1), - CHANY, seg_details, index, indices); - /* end */ - - return indices; -} - -void free_rr_node_indices(INP t_ivec *** L_rr_node_indices) { - int i, j, ofs; - /* This function must unallocate the structure allocated in - * alloc_and_load_rr_node_indices. */ - for (i = 0; i <= (nx + 1); ++i) { - for (j = 0; j <= (ny + 1); ++j) { - ofs = grid[i][j].offset; - if (ofs > 0) { - /* Vertical large blocks reference is same as offset 0 */ - L_rr_node_indices[SINK][i][j].list = NULL; - L_rr_node_indices[IPIN][i][j].list = NULL; - continue; - } - if (L_rr_node_indices[SINK][i][j].list != NULL) { - free(L_rr_node_indices[SINK][i][j].list); - } - if (L_rr_node_indices[IPIN][i][j].list != NULL) { - free(L_rr_node_indices[IPIN][i][j].list); - } - } - free(L_rr_node_indices[SINK][i]); - free(L_rr_node_indices[IPIN][i]); - } - free(L_rr_node_indices[SINK]); - free(L_rr_node_indices[IPIN]); - - for (i = 0; i < (nx + 1); ++i) { - for (j = 0; j < (ny + 1); ++j) { - if (L_rr_node_indices[CHANY][i][j].list != NULL) { - free(L_rr_node_indices[CHANY][i][j].list); - } - } - free(L_rr_node_indices[CHANY][i]); - } - free(L_rr_node_indices[CHANY]); - - for (i = 0; i < (ny + 1); ++i) { - for (j = 0; j < (nx + 1); ++j) { - if (L_rr_node_indices[CHANX][i][j].list != NULL) { - free(L_rr_node_indices[CHANX][i][j].list); - } - } - free(L_rr_node_indices[CHANX][i]); - } - free(L_rr_node_indices[CHANX]); - - free(L_rr_node_indices); -} - -int get_rr_node_index(int x, int y, t_rr_type rr_type, int ptc, - t_ivec *** L_rr_node_indices) { - /* Returns the index of the specified routing resource node. (x,y) are * - * the location within the FPGA, rr_type specifies the type of resource, * - * and ptc gives the number of this resource. ptc is the class number, * - * pin number or track number, depending on what type of resource this * - * is. All ptcs start at 0 and go up to pins_per_clb-1 or the equivalent. * - * The order within a clb is: SOURCEs + SINKs (type->num_class of them); IPINs, * - * and OPINs (pins_per_clb of them); CHANX; and CHANY (nodes_per_chan of * - * each). For (x,y) locations that point at pads the order is: type->capacity * - * occurances of SOURCE, SINK, OPIN, IPIN (one for each pad), then one * - * associated channel (if there is a channel at (x,y)). All IO pads are * - * bidirectional, so while each will be used only as an INPAD or as an * - * OUTPAD, all the switches necessary to do both must be in each pad. * - * * - * Note that for segments (CHANX and CHANY) of length > 1, the segment is * - * given an rr_index based on the (x,y) location at which it starts (i.e. * - * lowest (x,y) location at which this segment exists). * - * This routine also performs error checking to make sure the node in * - * question exists. */ - - int iclass, tmp; - t_type_ptr type; - t_ivec lookup; - - assert(ptc >= 0); - assert(x >= 0 && x <= (nx + 1)); - assert(y >= 0 && y <= (ny + 1)); - - type = grid[x][y].type; - - /* Currently need to swap x and y for CHANX because of chan, seg convention */ - /* Original VPR */ - /* - if (CHANX == rr_type) { - tmp = x; - x = y; - y = tmp; - } - */ - /* end */ - /* mrFPGA: Xifan TANG*/ - if ((is_stack ? CHANY : CHANX) == rr_type) { - tmp = x; - x = y; - y = tmp; - } - /* end */ - - /* Start of that block. */ - lookup = L_rr_node_indices[rr_type][x][y]; - - /* Check valid ptc num */ - assert(ptc >= 0); - assert(ptc < lookup.nelem); - -#ifdef DEBUG - switch (rr_type) { - case SOURCE: - assert(ptc < type->num_class); - assert(type->class_inf[ptc].type == DRIVER); - break; - - case SINK: - assert(ptc < type->num_class); - assert(type->class_inf[ptc].type == RECEIVER); - break; - - case OPIN: - assert(ptc < type->num_pins); - iclass = type->pin_class[ptc]; - assert(type->class_inf[iclass].type == DRIVER); - break; - - case IPIN: - assert(ptc < type->num_pins); - iclass = type->pin_class[ptc]; - assert(type->class_inf[iclass].type == RECEIVER); - break; - - case CHANX: - case CHANY: - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "Bad rr_node passed to get_rr_node_index.\n"); - vpr_printf(TIO_MESSAGE_ERROR, "Request for type=%d ptc=%d at (%d, %d).\n", rr_type, ptc, x, y); - exit(1); - } -#endif - - return lookup.list[ptc]; -} - -int get_track_to_ipins(int seg, int chan, int track, - t_linked_edge ** edge_list_ptr, t_ivec *** L_rr_node_indices, - struct s_ivec ****track_to_ipin_lookup, t_seg_details * seg_details, - enum e_rr_type chan_type, int chan_length, int wire_to_ipin_switch, - enum e_directionality directionality) { - - /* This counts the fan-out from wire segment (chan, seg, track) to blocks on either side */ - - t_linked_edge *edge_list_head; - int j, pass, iconn, phy_track, end, to_node, max_conn, ipin, side, x, y, - num_conn; - t_type_ptr type; - int off; - - /* End of this wire */ - /* Original VPR */ - /* end = get_seg_end(seg_details, track, seg, chan, chan_length); */ - /* end */ - /* mrFPGA: Xifan TANG */ - end = get_seg_end(seg_details, track, seg, chan, chan_length); - /* end */ - - edge_list_head = *edge_list_ptr; - num_conn = 0; - - for (j = seg; j <= end; j++) { - if (is_cbox(chan, j, track, seg_details, directionality)) { - for (pass = 0; pass < 2; ++pass) { - /* mrFPGA: Xifan TANG */ - if (is_stack) { - if (CHANX == chan_type) { - x = chan; - y = j + pass; - side = (0 == pass ? TOP : BOTTOM); - } else { - assert(CHANY == chan_type); - x = j + pass; - y = chan; - side = (0 == pass ? RIGHT : LEFT); - } - /* end */ - } else { - /* Original VPR */ - if (CHANX == chan_type) { - x = j; - y = chan + pass; - side = (0 == pass ? TOP : BOTTOM); - } else { - assert(CHANY == chan_type); - x = chan + pass; - y = j; - side = (0 == pass ? RIGHT : LEFT); - } - /* end */ - } - /* PAJ - if the pointed to is an EMPTY then shouldn't look for ipins */ - if (grid[x][y].type == EMPTY_TYPE) - continue; - - /* Move from logical (straight) to physical (twisted) track index - * - algorithm assigns ipin connections to same physical track index - * so that the logical track gets distributed uniformly */ - phy_track = vpr_to_phy_track(track, chan, j, seg_details, - directionality); - - /* We need the type to find the ipin map for this type */ - type = grid[x][y].type; - off = grid[x][y].offset; - - max_conn = - track_to_ipin_lookup[type->index][phy_track][off][side].nelem; - for (iconn = 0; iconn < max_conn; iconn++) { - ipin = - track_to_ipin_lookup[type->index][phy_track][off][side].list[iconn]; - - /* Check there is a connection and Fc map isn't wrong */ - assert(type->pinloc[off][side][ipin]); - assert(type->is_global_pin[ipin] == FALSE); - - to_node = get_rr_node_index(x, y, IPIN, ipin, - L_rr_node_indices); - edge_list_head = insert_in_edge_list(edge_list_head, - to_node, wire_to_ipin_switch); - } - num_conn += max_conn; - } - } - } - - *edge_list_ptr = edge_list_head; - return (num_conn); -} - -/* Counts how many connections should be made from this segment to the y- * - * segments in the adjacent channels at to_j. It returns the number of * - * connections, and updates edge_list_ptr to point at the head of the * - * (extended) linked list giving the nodes to which this segment connects * - * and the switch type used to connect to each. * - * * - * An edge is added from this segment to a y-segment if: * - * (1) this segment should have a switch box at that location, or * - * (2) the y-segment to which it would connect has a switch box, and the * - * switch type of that y-segment is unbuffered (bidirectional pass * - * transistor). * - * * - * For bidirectional: * - * If the switch in each direction is a pass transistor (unbuffered), both * - * switches are marked as being of the types of the larger (lower R) pass * - * transistor. */ -int get_track_to_tracks(INP int from_chan, INP int from_seg, INP int from_track, - INP t_rr_type from_type, INP int to_seg, INP t_rr_type to_type, - INP int chan_len, INP int nodes_per_chan, INP int *opin_mux_size, - INP int Fs_per_side, INP short *****sblock_pattern, - INOUTP struct s_linked_edge **edge_list, - INP t_seg_details * seg_details, - INP enum e_directionality directionality, - INP t_ivec *** L_rr_node_indices, INOUTP boolean * L_rr_edge_done, - INP struct s_ivec ***switch_block_conn) { - int num_conn; - int from_switch, from_end, from_sb, from_first; - int to_chan, to_sb; - int start, end; - struct s_ivec conn_tracks; - boolean from_is_sbox, is_behind, Fs_clipped; - enum e_side from_side_a, from_side_b, to_side; - - /* mrFPGA: Xifan TANG */ - //int true_from_start, true_from_end; - - /* Original VPR */ - assert( - from_seg == get_seg_start(seg_details, from_track, from_chan, from_seg)); - - from_switch = seg_details[from_track].wire_switch; - from_end = get_seg_end(seg_details, from_track, from_seg, from_chan, - chan_len); - /* end */ - - /* mrFPGA : Xifan TANG*/ - if (is_stack) { - from_end = from_end + 1; - from_first = from_seg; - /* end */ - } else { - /* Original VPR */ - from_first = from_seg - 1; - } - /* end */ - - /* mrFPGA : Xifan TANG*/ - if (is_stack ? (CHANY == from_type) : (CHANX == from_type)) { - from_side_a = RIGHT; - from_side_b = LEFT; - } else { - assert(is_stack ? (CHANX == from_type) : (CHANY == from_type)); - from_side_a = TOP; - from_side_b = BOTTOM; - } - /* end */ - - /* Original VPR */ - /* Figure out the sides of SB the from_wire will use */ - /* - if (CHANX == from_type) { - from_side_a = RIGHT; - from_side_b = LEFT; - } else { - assert(CHANY == from_type); - from_side_a = TOP; - from_side_b = BOTTOM; - } - */ - /* end */ - - /* Figure out if the to_wire is connecting to a SB - * that is behind it. */ - is_behind = FALSE; - if (to_type == from_type) { - /* Original VPR */ - /* If inline, check that they only are trying - * to connect at endpoints. */ - /* - assert((to_seg == (from_end + 1)) || (to_seg == (from_seg - 1))); - if (to_seg > from_end) { - is_behind = TRUE; - } - */ - /* end */ - /* mrFPGA: Xifan TANG */ - assert((to_seg == (from_end + (is_stack ? 0 : 1))) || (to_seg == (from_seg - 1))); - if (is_stack ? to_seg >= from_end : to_seg > from_end) { - is_behind = TRUE; - } - /* end */ - } else { - /* Original VPR */ - /* If bending, check that they are adjacent to - * our channel. */ - /* - assert((to_seg == from_chan) || (to_seg == (from_chan + 1))); - if (to_seg > from_chan) { - is_behind = TRUE; - } - */ - /* end */ - /* mrFPGA: Xifan TANG */ - if (is_stack) { - assert((to_seg == (from_chan - 1)) || (to_seg == from_chan)); - } else { - assert((to_seg == from_chan) || (to_seg == (from_chan + 1))); - } - if (is_stack ? (to_seg >= from_chan) : (to_seg > from_chan)) { - is_behind = TRUE; - } - /* end */ - } - - /* Original VPR */ - /* Figure out the side of SB the to_wires will use. - * The to_seg and from_chan are in same direction. */ - /* - if (CHANX == to_type) { - to_side = (is_behind ? RIGHT : LEFT); - } else { - assert(CHANY == to_type); - to_side = (is_behind ? TOP : BOTTOM); - } - */ - /* end */ - - /* mrFPGA: Xifan TANG */ - if (is_stack ? (CHANY == to_type) : (CHANX == to_type)) { - to_side = (is_behind ? RIGHT : LEFT); - } else { - assert(is_stack ? (CHANX == to_type) : (CHANY == to_type)); - to_side = (is_behind ? TOP : BOTTOM); - } - /* end */ - - /* Set the loop bounds */ - start = from_first; - end = from_end; - - /* If we are connecting in same direction the connection is - * on one of the two sides so clip the bounds to the SB of - * interest and proceed normally. */ - if (to_type == from_type) { - start = (is_behind ? end : start); - end = start; - } - - /* Iterate over the SBs */ - num_conn = 0; - for (from_sb = start; from_sb <= end; ++from_sb) { - /* mrFPGA: Xifan TANG */ - if (is_stack) { - if (CHANX == from_type) { - if ((0 == from_sb)||((ny + 1) == from_sb)) { - continue; - } - } else { - assert(CHANY == from_type); - if ((0 == from_sb)||((nx + 1) == from_sb)) { - continue; - } - } - } - /* end */ - - /* Figure out if we are at a sbox */ - from_is_sbox = is_sbox(from_chan, from_seg, from_sb, from_track, - seg_details, directionality); - /* end of wire must be an sbox */ - if (from_sb == from_end || from_sb == from_first) { - from_is_sbox = TRUE; /* Endpoints always default to true */ - } - - /* to_chan is the current segment if different directions, - * otherwise to_chan is the from_chan */ - to_chan = from_sb; - to_sb = from_chan; - if (from_type == to_type) { - to_chan = from_chan; - to_sb = from_sb; - } - - /* Do the edges going to the left or down */ - if (from_sb < from_end) { - if (BI_DIRECTIONAL == directionality) { - conn_tracks = - switch_block_conn[from_side_a][to_side][from_track]; - num_conn += get_bidir_track_to_chan_seg(conn_tracks, - L_rr_node_indices, to_chan, to_seg, to_sb, to_type, - seg_details, from_is_sbox, from_switch, L_rr_edge_done, - directionality, edge_list); - } - if (UNI_DIRECTIONAL == directionality) { - /* No fanout if no SB. */ - /* We are connecting from the top or right of SB so it - * makes the most sense to only there from DEC_DIRECTION wires. */ - if ((from_is_sbox) - && (DEC_DIRECTION == seg_details[from_track].direction)) { - num_conn += get_unidir_track_to_chan_seg( - (boolean)(from_sb == from_first), from_track, to_chan, - to_seg, to_sb, to_type, nodes_per_chan, nx, ny, - from_side_a, to_side, Fs_per_side, opin_mux_size, - sblock_pattern, L_rr_node_indices, seg_details, - L_rr_edge_done, &Fs_clipped, edge_list); - } - } - } - - /* Do the edges going to the right or up */ - if (from_sb > from_first) { - if (BI_DIRECTIONAL == directionality) { - conn_tracks = - switch_block_conn[from_side_b][to_side][from_track]; - num_conn += get_bidir_track_to_chan_seg(conn_tracks, - L_rr_node_indices, to_chan, to_seg, to_sb, to_type, - seg_details, from_is_sbox, from_switch, L_rr_edge_done, - directionality, edge_list); - } - if (UNI_DIRECTIONAL == directionality) { - /* No fanout if no SB. */ - /* We are connecting from the bottom or left of SB so it - * makes the most sense to only there from INC_DIRECTION wires. */ - if ((from_is_sbox) - && (INC_DIRECTION == seg_details[from_track].direction)) { - num_conn += get_unidir_track_to_chan_seg( - (boolean)(from_sb == from_end), from_track, to_chan, to_seg, - to_sb, to_type, nodes_per_chan, nx, ny, from_side_b, - to_side, Fs_per_side, opin_mux_size, sblock_pattern, - L_rr_node_indices, seg_details, L_rr_edge_done, - &Fs_clipped, edge_list); - } - } - } - } - - return num_conn; -} - -/* mrFPGA : Xifan TANG, Abolish */ -/* -static int get_seg_to_seg(INP t_ivec*** L_rr_node_indices, - INP int to_chan, - INP int to_seg, - INP int track, - INP t_rr_type type, - INP t_seg_details* seg_details, - INOUTP struct s_linked_edge** edge_list) { - int to_x, to_y, to_node; - - if ((is_stack ? CHANY : CHANX) == type) { - to_x = to_seg; - to_y = to_chan; - } else { - assert((is_stack ? CHANX : CHANY) == type); - to_x = to_chan; - to_y = to_seg; - } - to_node = get_rr_node_index(to_x, to_y, type, track, L_rr_node_indices); - *edge_list = insert_in_edge_list(*edge_list, to_node, seg_details[track].seg_switch); - - return 1; -} -*/ -/* END */ - - -static int get_bidir_track_to_chan_seg(INP struct s_ivec conn_tracks, - INP t_ivec *** L_rr_node_indices, INP int to_chan, INP int to_seg, - INP int to_sb, INP t_rr_type to_type, INP t_seg_details * seg_details, - INP boolean from_is_sbox, INP int from_switch, - INOUTP boolean * L_rr_edge_done, - INP enum e_directionality directionality, - INOUTP struct s_linked_edge **edge_list) { - int iconn, to_track, to_node, to_switch, num_conn, to_x, to_y, i; - boolean to_is_sbox; - short switch_types[2]; - - /* Original VPR */ - /* x, y coords for get_rr_node lookups */ - /* - if (CHANX == to_type) { - to_x = to_seg; - to_y = to_chan; - } else { - assert(CHANY == to_type); - to_x = to_chan; - to_y = to_seg; - } - */ - /* END */ - /* mrFPGA : Xifan TANG*/ - if ((is_stack ? CHANY : CHANX) == to_type) { - to_x = to_seg; - to_y = to_chan; - } else { - assert((is_stack ? CHANX : CHANY) == to_type); - to_x = to_chan; - to_y = to_seg; - } - /* END */ - - /* Go through the list of tracks we can connect to */ - num_conn = 0; - for (iconn = 0; iconn < conn_tracks.nelem; ++iconn) { - to_track = conn_tracks.list[iconn]; - to_node = get_rr_node_index(to_x, to_y, to_type, to_track, - L_rr_node_indices); - - /* Skip edge if already done */ - if (L_rr_edge_done[to_node]) { - continue; - } - - /* Get the switches for any edges between the two tracks */ - to_switch = seg_details[to_track].wire_switch; - - to_is_sbox = is_sbox(to_chan, to_seg, to_sb, to_track, seg_details, - directionality); - get_switch_type(from_is_sbox, to_is_sbox, from_switch, to_switch, - switch_types); - - /* There are up to two switch edges allowed from track to track */ - for (i = 0; i < 2; ++i) { - /* If the switch_type entry is empty, skip it */ - if (OPEN == switch_types[i]) { - continue; - } - - /* Add the edge to the list */ - *edge_list = insert_in_edge_list(*edge_list, to_node, - switch_types[i]); - /* Mark the edge as now done */ - L_rr_edge_done[to_node] = TRUE; - ++num_conn; - } - } - - return num_conn; -} - -static int get_unidir_track_to_chan_seg(INP boolean is_end_sb, - INP int from_track, INP int to_chan, INP int to_seg, INP int to_sb, - INP t_rr_type to_type, INP int nodes_per_chan, INP int L_nx, - INP int L_ny, INP enum e_side from_side, INP enum e_side to_side, - INP int Fs_per_side, INP int *opin_mux_size, - INP short *****sblock_pattern, INP t_ivec *** L_rr_node_indices, - INP t_seg_details * seg_details, INOUTP boolean * L_rr_edge_done, - OUTP boolean * Fs_clipped, INOUTP struct s_linked_edge **edge_list) { - int to_track, to_mux, to_node, to_x, to_y, i, max_len, num_labels; - int sb_x, sb_y, count; - int *mux_labels = NULL; - enum e_direction to_dir; - boolean is_fringe, is_core, is_corner, is_straight; - - /* x, y coords for get_rr_node lookups */ - /* Original VPR */ - /* - if (CHANX == to_type) { - to_x = to_seg; - to_y = to_chan; - sb_x = to_sb; - sb_y = to_chan; - max_len = L_nx; - } else { - assert(CHANY == to_type); - to_x = to_chan; - to_y = to_seg; - sb_x = to_chan; - sb_y = to_sb; - max_len = L_ny; - } - */ - /* end */ - /* mrFPGA: Xifan TANG*/ - if ((is_stack ? CHANY : CHANX) == to_type) { - to_x = to_seg; - to_y = to_chan; - sb_x = to_sb; - sb_y = to_chan; - max_len = L_nx; - } else { - assert((is_stack ? CHANX : CHANY) == to_type); - to_x = to_chan; - to_y = to_seg; - sb_x = to_chan; - sb_y = to_sb; - max_len = L_ny; - } - /* end */ - - to_dir = DEC_DIRECTION; - if (to_sb < to_seg) { - to_dir = INC_DIRECTION; - } - - *Fs_clipped = FALSE; - - /* SBs go from (0, 0) to (nx, ny) */ - is_corner = (boolean)(((sb_x < 1) || (sb_x >= L_nx)) - && ((sb_y < 1) || (sb_y >= L_ny))); - is_fringe = (boolean)((FALSE == is_corner) - && ((sb_x < 1) || (sb_y < 1) || (sb_x >= L_nx) || (sb_y >= L_ny))); - is_core = (boolean)((FALSE == is_corner) && (FALSE == is_fringe)); - is_straight = (boolean)((from_side == RIGHT && to_side == LEFT) - || (from_side == LEFT && to_side == RIGHT) - || (from_side == TOP && to_side == BOTTOM) - || (from_side == BOTTOM && to_side == TOP)); - - /* Ending wires use N-to-N mapping if not fringe or if goes straight */ - if (is_end_sb && (is_core || is_corner || is_straight)) { - /* Get the list of possible muxes for the N-to-N mapping. */ - mux_labels = label_wire_muxes(to_chan, to_seg, seg_details, max_len, - to_dir, nodes_per_chan, &num_labels); - } else { - assert(is_fringe || !is_end_sb); - - mux_labels = label_wire_muxes_for_balance(to_chan, to_seg, seg_details, - max_len, to_dir, nodes_per_chan, &num_labels, to_type, - opin_mux_size, L_rr_node_indices); - } - - /* Can't connect if no muxes. */ - if (num_labels < 1) { - if (mux_labels) { - free(mux_labels); - mux_labels = NULL; - } - return 0; - } - - /* Check if Fs demand was too high. */ - if (Fs_per_side > num_labels) { - *Fs_clipped = TRUE; - } - - /* Get the target label */ - to_mux = sblock_pattern[sb_x][sb_y][from_side][to_side][from_track]; - assert(to_mux != UN_SET); - - /* Handle Fs > 3 but assigning consecutive muxes. */ - count = 0; - for (i = 0; i < Fs_per_side; ++i) { - /* Use the balanced labeling for passing and fringe wires */ - to_track = mux_labels[(to_mux + i) % num_labels]; - to_node = get_rr_node_index(to_x, to_y, to_type, to_track, - L_rr_node_indices); - - /* Add edge to list. */ - if (FALSE == L_rr_edge_done[to_node]) { - L_rr_edge_done[to_node] = TRUE; - *edge_list = insert_in_edge_list(*edge_list, to_node, - seg_details[to_track].wire_switch); - ++count; - } - } - - if (mux_labels) { - free(mux_labels); - mux_labels = NULL; - } - - return count; -} - -boolean is_sbox(INP int chan, INP int wire_seg, INP int sb_seg, INP int track, - INP t_seg_details * seg_details, - INP enum e_directionality directionality) { - - int length, ofs, fac; - - fac = 1; - if (UNI_DIRECTIONAL == directionality) { - fac = 2; - } - - length = seg_details[track].length; - - /* Make sure they gave us correct start */ - wire_seg = get_seg_start(seg_details, track, chan, wire_seg); - - /* original VPR */ - /* Ofset 0 is behind us, so add 1 */ - /* ofs = sb_seg - wire_seg + 1; */ - /* end */ - - /* mrFPGA: Xifan TANG */ - ofs = sb_seg - wire_seg + (is_stack ? 0 : 1); - /* end */ - - assert(ofs >= 0); - assert(ofs < (length + 1)); - - /* If unidir segment that is going backwards, we need to flip the ofs */ - if ((ofs % fac) > 0) { - ofs = length - ofs; - } - - return seg_details[track].sb[ofs]; -} - -static void get_switch_type(boolean is_from_sbox, boolean is_to_sbox, - short from_node_switch, short to_node_switch, short switch_types[2]) { - /* This routine looks at whether the from_node and to_node want a switch, * - * and what type of switch is used to connect *to* each type of node * - * (from_node_switch and to_node_switch). It decides what type of switch, * - * if any, should be used to go from from_node to to_node. If no switch * - * should be inserted (i.e. no connection), it returns OPEN. Its returned * - * values are in the switch_types array. It needs to return an array * - * because one topology (a buffer in the forward direction and a pass * - * transistor in the backward direction) results in *two* switches. */ - - boolean forward_pass_trans; - boolean backward_pass_trans; - int used, min_switch, max_switch; - - /* mrFPGA: Xifan TANG */ - if (is_mrFPGA) { - get_mrfpga_switch_type(is_from_sbox, is_to_sbox, from_node_switch, - to_node_switch, switch_types); - return; - } - /* end */ - - switch_types[0] = OPEN; /* No switch */ - switch_types[1] = OPEN; - used = 0; - forward_pass_trans = FALSE; - backward_pass_trans = FALSE; - - /* Connect forward if we are a sbox */ - if (is_from_sbox) { - switch_types[used] = to_node_switch; - if (FALSE == switch_inf[to_node_switch].buffered) { - forward_pass_trans = TRUE; - } - ++used; - } - - /* Check for pass_trans coming backwards */ - if (is_to_sbox) { - if (FALSE == switch_inf[from_node_switch].buffered) { - switch_types[used] = from_node_switch; - backward_pass_trans = TRUE; - ++used; - } - } - - /* Take the larger pass trans if there are two */ - if (forward_pass_trans && backward_pass_trans) { - min_switch = std::min(to_node_switch, from_node_switch); - max_switch = std::max(to_node_switch, from_node_switch); - - /* Take the smaller index unless the other - * pass_trans is bigger (smaller R). */ - switch_types[used] = min_switch; - if (switch_inf[max_switch].R < switch_inf[min_switch].R) { - switch_types[used] = max_switch; - } - ++used; - } -} - -static int vpr_to_phy_track(INP int itrack, INP int chan_num, INP int seg_num, - INP t_seg_details * seg_details, - INP enum e_directionality directionality) { - int group_start, group_size; - int vpr_offset_for_first_phy_track; - int vpr_offset, phy_offset; - int phy_track; - int fac; - - /* Assign in pairs if unidir. */ - fac = 1; - if (UNI_DIRECTIONAL == directionality) { - fac = 2; - } - - group_start = seg_details[itrack].group_start; - group_size = seg_details[itrack].group_size; - - vpr_offset_for_first_phy_track = (chan_num + seg_num - 1) - % (group_size / fac); - vpr_offset = (itrack - group_start) / fac; - phy_offset = (vpr_offset_for_first_phy_track + vpr_offset) - % (group_size / fac); - phy_track = group_start + (fac * phy_offset) + (itrack - group_start) % fac; - - return phy_track; -} - -short ***** -alloc_sblock_pattern_lookup(INP int L_nx, INP int L_ny, INP int nodes_per_chan) { - int i, j, from_side, to_side, itrack, items; - short *****result; - short *****i_list; - short ****j_list; - short ***from_list; - short **to_list; - short *track_list; - - /* loading up the sblock connection pattern matrix. It's a huge matrix because - * for nonquantized W, it's impossible to make simple permutations to figure out - * where muxes are and how to connect to them such that their sizes are balanced */ - - /* Do chunked allocations to make freeing easier, speed up malloc and free, and - * reduce some of the memory overhead. Could use fewer malloc's but this way - * avoids all considerations of pointer sizes and allignment. */ - - /* Alloc each list of pointers in one go. items is a running product that increases - * with each new dimension of the matrix. */ - items = 1; - items *= (L_nx + 1); - i_list = (short *****) my_malloc(sizeof(short ****) * items); - items *= (L_ny + 1); - j_list = (short ****) my_malloc(sizeof(short ***) * items); - items *= (4); - from_list = (short ***) my_malloc(sizeof(short **) * items); - items *= (4); - to_list = (short **) my_malloc(sizeof(short *) * items); - items *= (nodes_per_chan); - track_list = (short *) my_malloc(sizeof(short) * items); - - /* Build the pointer lists to form the multidimensional array */ - result = i_list; - i_list += (L_nx + 1); /* Skip forward nx+1 items */ - for (i = 0; i < (L_nx + 1); ++i) { - - result[i] = j_list; - j_list += (L_ny + 1); /* Skip forward ny+1 items */ - for (j = 0; j < (L_ny + 1); ++j) { - - result[i][j] = from_list; - from_list += (4); /* Skip forward 4 items */ - for (from_side = 0; from_side < 4; ++from_side) { - - result[i][j][from_side] = to_list; - to_list += (4); /* Skip forward 4 items */ - for (to_side = 0; to_side < 4; ++to_side) { - - result[i][j][from_side][to_side] = track_list; - track_list += (nodes_per_chan); /* Skip forward nodes_per_chan items */ - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - - /* Set initial value to be unset */ - result[i][j][from_side][to_side][itrack] = UN_SET; - } - } - } - } - } - - /* This is the outer pointer to the full matrix */ - return result; -} - -void free_sblock_pattern_lookup(INOUTP short *****sblock_pattern) { - /* This free function corresponds to the chunked matrix - * allocation above and there should only be one free - * call for each dimension. */ - - /* Free dimensions from the inner one, outwards so - * we can still access them. The comments beside - * each one indicate the corresponding name used when - * allocating them. */ - free(****sblock_pattern); /* track_list */ - free(***sblock_pattern); /* to_list */ - free(**sblock_pattern); /* from_list */ - free(*sblock_pattern); /* j_list */ - free(sblock_pattern); /* i_list */ -} - -void load_sblock_pattern_lookup(INP int i, INP int j, INP int nodes_per_chan, - INP t_seg_details * seg_details, INP int Fs, - INP enum e_switch_block_type switch_block_type, - INOUTP short *****sblock_pattern) { - - /* This routine loads a lookup table for sblock topology. The lookup table is huge - * because the sblock varies from location to location. The i, j means the owning - * location of the sblock under investigation. */ - - int side_cw_incoming_wire_count, side_ccw_incoming_wire_count, - opp_incoming_wire_count; - int to_side, side, side_cw, side_ccw, side_opp, itrack; - int Fs_per_side, chan, seg, chan_len, sb_seg; - boolean is_core_sblock, is_corner_sblock, x_edge, y_edge; - int *incoming_wire_label[4]; - int *wire_mux_on_track[4]; - int num_incoming_wires[4]; - int num_ending_wires[4]; - int num_wire_muxes[4]; - boolean skip, vert, pos_dir; - enum e_direction dir; - - Fs_per_side = 1; - if (Fs != -1) { - Fs_per_side = Fs / 3; - } - - /* SB's have coords from (0, 0) to (nx, ny) */ - assert(i >= 0); - assert(i <= nx); - assert(j >= 0); - assert(j <= ny); - - /* May 12 - 15, 2007 - * - * I identify three types of sblocks in the chip: 1) The core sblock, whose special - * property is that the number of muxes (and ending wires) on each side is the same (very useful - * property, since it leads to a N-to-N assignment problem with ending wires). 2) The corner sblock - * which is same as a L=1 core sblock with 2 sides only (again N-to-N assignment problem). 3) The - * fringe / chip edge sblock which is most troublesome, as balance in each side of muxes is - * attainable but balance in the entire sblock is not. The following code first identifies the - * incoming wires, which can be classified into incoming passing wires with sbox and incoming - * ending wires (the word "incoming" is sometimes dropped for ease of discussion). It appropriately - * labels all the wires on each side by the following order: By the call to label_incoming_wires, - * which labels for one side, the order is such that the incoming ending wires (always with sbox) - * are labelled first 0,1,2,... p-1, then the incoming passing wires with sbox are labelled - * p,p+1,p+2,... k-1 (for total of k). By this convention, one can easily distinguish the ending - * wires from the passing wires by checking a label against num_ending_wires variable. - * - * After labelling all the incoming wires, this routine labels the muxes on the side we're currently - * connecting to (iterated for four sides of the sblock), called the to_side. The label scheme is - * the natural order of the muxes by their track #. Also we find the number of muxes. - * - * For each to_side, the total incoming wires that connect to the muxes on to_side - * come from three sides: side_1 (to_side's right), side_2 (to_side's left) and opp_side. - * The problem of balancing mux size is then: considering all incoming passing wires - * with sbox on side_1, side_2 and opp_side, how to assign them to the muxes on to_side - * (with specified Fs) in a way that mux size is imbalanced by at most 1. I solve this - * problem by this approach: the first incoming passing wire will connect to 0, 1, 2, - * ..., Fs_per_side - 1, then the next incoming passing wire will connect to - * Fs_per_side, Fs_per_side+1, ..., Fs_per_side*2-1, and so on. This consistent STAGGERING - * ensures N-to-N assignment is perfectly balanced and M-to-N assignment is imbalanced by no - * more than 1. - * - * For the sblock_pattern_init_mux_lookup lookup table, I will only need the lookup - * table to remember the first/init mux to connect, since the convention is Fs_per_side consecutive - * muxes to connect. Then how do I determine the order of the incoming wires? I use the labels - * on side_1, then labels on side_2, then labels on opp_side. Effectively I listed all - * incoming passing wires from the three sides, and order them to each make Fs_per_side - * consecutive connections to muxes, and use % to rotate to keep imbalance at most 1. - */ - - /* SB's range from (0, 0) to (nx, ny) */ - /* First find all four sides' incoming wires */ - x_edge = (boolean)((i < 1) || (i >= nx)); - y_edge = (boolean)((j < 1) || (j >= ny)); - - is_corner_sblock = (boolean)(x_edge && y_edge); - is_core_sblock = (boolean)(!x_edge && !y_edge); - - /* "Label" the wires around the switch block by connectivity. */ - for (side = 0; side < 4; ++side) { - /* Assume the channel segment doesn't exist. */ - wire_mux_on_track[side] = NULL; - incoming_wire_label[side] = NULL; - num_incoming_wires[side] = 0; - num_ending_wires[side] = 0; - num_wire_muxes[side] = 0; - - /* Skip the side and leave the zero'd value if the - * channel segment doesn't exist. */ - skip = TRUE; - switch (side) { - /* Original VPR */ - /* - case TOP: - if (j < ny) { - skip = FALSE; - } - ; - break; - case RIGHT: - if (i < nx) { - skip = FALSE; - } - break; - case BOTTOM: - if (j > 0) { - skip = FALSE; - } - break; - case LEFT: - if (i > 0) { - skip = FALSE; - } - break; - } - */ - /* end */ - /* mrFPGA : Xifan TANG*/ - case TOP: - if (j < (is_stack ? ny+1 : ny)) { - skip = FALSE; - } - ; - break; - case RIGHT: - if (i < (is_stack ? nx+1 : nx)) { - skip = FALSE; - } - break; - case BOTTOM: - if (j > 0) { - skip = FALSE; - } - break; - case LEFT: - if (i > 0) { - skip = FALSE; - } - break; - } - /* end */ - if (skip) { - continue; - } - - /* Figure out the channel and segment for a certain direction */ - vert = (boolean) ((side == TOP) || (side == BOTTOM)); - pos_dir = (boolean) ((side == TOP) || (side == RIGHT)); - chan = (vert ? i : j); - sb_seg = (vert ? j : i); - /* Original VPR */ - /* seg = (pos_dir ? (sb_seg + 1) : sb_seg); */ - /* end */ - /* mrFPGA : Xifan TANG*/ - seg = (pos_dir ? (sb_seg + 1) : sb_seg) - (is_stack ? 1 : 0); - /* end */ - chan_len = (vert ? ny : nx); - - /* Figure out all the tracks on a side that are ending and the - * ones that are passing through and have a SB. */ - dir = (pos_dir ? DEC_DIRECTION : INC_DIRECTION); - incoming_wire_label[side] = label_incoming_wires(chan, seg, sb_seg, - seg_details, chan_len, dir, nodes_per_chan, - &num_incoming_wires[side], &num_ending_wires[side]); - - /* Figure out all the tracks on a side that are starting. */ - dir = (pos_dir ? INC_DIRECTION : DEC_DIRECTION); - wire_mux_on_track[side] = label_wire_muxes(chan, seg, seg_details, - chan_len, dir, nodes_per_chan, &num_wire_muxes[side]); - } - - for (to_side = 0; to_side < 4; to_side++) { - /* Can't do anything if no muxes on this side. */ - if (0 == num_wire_muxes[to_side]) { - continue; - } - - /* Figure out side rotations */ - assert((TOP == 0) && (RIGHT == 1) && (BOTTOM == 2) && (LEFT == 3)); - side_cw = (to_side + 1) % 4; - side_opp = (to_side + 2) % 4; - side_ccw = (to_side + 3) % 4; - - /* For the core sblock: - * The new order for passing wires should appear as - * 0,1,2..,scw-1, for passing wires with sbox on side_cw - * scw,scw+1,...,sccw-1, for passing wires with sbox on side_ccw - * sccw,sccw+1,... for passing wires with sbox on side_opp. - * This way, I can keep the imbalance to at most 1. - * - * For the fringe sblocks, I don't distinguish between - * passing and ending wires so the above statement still holds - * if you replace "passing" by "incoming" */ - - side_cw_incoming_wire_count = 0; - if (incoming_wire_label[side_cw]) { - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - /* Ending wire, or passing wire with sbox. */ - if (incoming_wire_label[side_cw][itrack] != UN_SET) { - - if ((is_corner_sblock || is_core_sblock) - && (incoming_wire_label[side_cw][itrack] - < num_ending_wires[side_cw])) { - /* The ending wires in core sblocks form N-to-N assignment - * problem, so can use any pattern such as Wilton. This N-to-N - * mapping depends on the fact that start points stagger across - * channels. */ - assert( - num_ending_wires[side_cw] == num_wire_muxes[to_side]); - sblock_pattern[i][j][side_cw][to_side][itrack] = - get_simple_switch_block_track((enum e_side)side_cw, (enum e_side)to_side, - incoming_wire_label[side_cw][itrack], - switch_block_type, - num_wire_muxes[to_side]); - - } else { - - /* These are passing wires with sbox only for core sblocks - * or passing and ending wires (for fringe cases). */ - sblock_pattern[i][j][side_cw][to_side][itrack] = - (side_cw_incoming_wire_count * Fs_per_side) - % num_wire_muxes[to_side]; - side_cw_incoming_wire_count++; - } - } - } - } - - side_ccw_incoming_wire_count = 0; - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - - /* if that side has no channel segment skip it */ - if (incoming_wire_label[side_ccw] == NULL) - break; - - /* not ending wire nor passing wire with sbox */ - if (incoming_wire_label[side_ccw][itrack] != UN_SET) { - - if ((is_corner_sblock || is_core_sblock) - && (incoming_wire_label[side_ccw][itrack] - < num_ending_wires[side_ccw])) { - /* The ending wires in core sblocks form N-to-N assignment problem, so can - * use any pattern such as Wilton */ - assert( - incoming_wire_label[side_ccw] [itrack] < num_wire_muxes[to_side]); - sblock_pattern[i][j][side_ccw][to_side][itrack] = - get_simple_switch_block_track((enum e_side)side_ccw, (enum e_side)to_side, - incoming_wire_label[side_ccw][itrack], - switch_block_type, num_wire_muxes[to_side]); - } else { - - /* These are passing wires with sbox only for core sblocks - * or passing and ending wires (for fringe cases). */ - sblock_pattern[i][j][side_ccw][to_side][itrack] = - ((side_ccw_incoming_wire_count - + side_cw_incoming_wire_count) * Fs_per_side) - % num_wire_muxes[to_side]; - side_ccw_incoming_wire_count++; - } - } - } - - opp_incoming_wire_count = 0; - if (incoming_wire_label[side_opp]) { - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - /* not ending wire nor passing wire with sbox */ - if (incoming_wire_label[side_opp][itrack] != UN_SET) { - - /* corner sblocks for sure have no opposite channel segments so don't care about them */ - if (is_core_sblock) { - if (incoming_wire_label[side_opp][itrack] - < num_ending_wires[side_opp]) { - /* The ending wires in core sblocks form N-to-N assignment problem, so can - * use any pattern such as Wilton */ - /* In the direct connect case, I know for sure the init mux is at the same track # - * as this ending wire, but still need to find the init mux label for Fs > 3 */ - sblock_pattern[i][j][side_opp][to_side][itrack] = - find_label_of_track( - wire_mux_on_track[to_side], - num_wire_muxes[to_side], itrack); - } else { - /* These are passing wires with sbox for core sblocks */ - sblock_pattern[i][j][side_opp][to_side][itrack] = - ((side_ccw_incoming_wire_count - + side_cw_incoming_wire_count) - * Fs_per_side - + opp_incoming_wire_count - * (Fs_per_side - 1)) - % num_wire_muxes[to_side]; - opp_incoming_wire_count++; - } - } else { - if (incoming_wire_label[side_opp][itrack] - < num_ending_wires[side_opp]) { - sblock_pattern[i][j][side_opp][to_side][itrack] = - find_label_of_track( - wire_mux_on_track[to_side], - num_wire_muxes[to_side], itrack); - } else { - /* These are passing wires with sbox for fringe sblocks */ - sblock_pattern[i][j][side_opp][to_side][itrack] = - ((side_ccw_incoming_wire_count - + side_cw_incoming_wire_count) - * Fs_per_side - + opp_incoming_wire_count - * (Fs_per_side - 1)) - % num_wire_muxes[to_side]; - opp_incoming_wire_count++; - } - } - } - } - } - } - - for (side = 0; side < 4; ++side) { - if (incoming_wire_label[side]) { - free(incoming_wire_label[side]); - } - if (wire_mux_on_track[side]) { - free(wire_mux_on_track[side]); - } - } -} - -static int * -label_wire_muxes_for_balance(INP int chan_num, INP int seg_num, - INP t_seg_details * seg_details, INP int max_len, - INP enum e_direction direction, INP int nodes_per_chan, - INP int *num_wire_muxes, INP t_rr_type chan_type, - INP int *opin_mux_size, INP t_ivec *** L_rr_node_indices) { - - /* Labels the muxes on that side (seg_num, chan_num, direction). The returned array - * maps a label to the actual track #: array[0] = */ - - /* Sblock (aka wire2mux) pattern generation occurs after opin2mux connections have been - * made. Since opin2muxes are done with a pattern with which I guarantee imbalance of at most 1 due - * to them, we will observe that, for each side of an sblock some muxes have one fewer size - * than the others, considering only the contribution from opins. I refer to these muxes as "holes" - * as they have one fewer opin connection going to them than the rest (like missing one electron)*/ - - /* Before May 14, I was labelling wire muxes in the natural order of their track # (lowest first). - * Now I want to label wire muxes like this: first label the holes in order of their track #, - * then label the non-holes in order of their track #. This way the wire2mux generation will - * not overlap its own "holes" with the opin "holes", thus creating imbalance greater than 1. */ - - /* The best approach in sblock generation is do one assignment of all incoming wires from 3 other - * sides to the muxes on the fourth side, connecting the "opin hole" muxes first (i.e. filling - * the holes) then the rest -> this means after all opin2mux and wire2mux connections the - * mux size imbalance on one side is at most 1. The mux size imbalance in one sblock is thus - * also one, since the number of muxes per side is identical for all four sides, and they number - * of incoming wires per side is identical for full pop, and almost the same for depop (due to - * staggering) within +1 or -1. For different tiles (different sblocks) the imbalance is irrelevant, - * since if the tiles are different in mux count then they have to be designed with a different - * physical tile. */ - - int num_labels, max_opin_mux_size, min_opin_mux_size; - int inode, i, j, x, y; - int *pre_labels, *final_labels; - - if (chan_type == CHANX) { - x = seg_num; - y = chan_num; - } else if (chan_type == CHANY) { - x = chan_num; - y = seg_num; - } else { - vpr_printf(TIO_MESSAGE_ERROR, "Bad channel type (%d).\n", chan_type); - exit(1); - } - - /* Generate the normal labels list as the baseline. */ - pre_labels = label_wire_muxes(chan_num, seg_num, seg_details, max_len, - direction, nodes_per_chan, &num_labels); - - /* Find the min and max mux size. */ - min_opin_mux_size = MAX_SHORT; - max_opin_mux_size = 0; - for (i = 0; i < num_labels; ++i) { - inode = get_rr_node_index(x, y, chan_type, pre_labels[i], - L_rr_node_indices); - if (opin_mux_size[inode] < min_opin_mux_size) { - min_opin_mux_size = opin_mux_size[inode]; - } - if (opin_mux_size[inode] > max_opin_mux_size) { - max_opin_mux_size = opin_mux_size[inode]; - } - } - if (max_opin_mux_size > (min_opin_mux_size + 1)) { - vpr_printf(TIO_MESSAGE_ERROR, "opin muxes are not balanced!\n"); - vpr_printf(TIO_MESSAGE_ERROR, "max_opin_mux_size %d min_opin_mux_size %d chan_type %d x %d y %d\n", - max_opin_mux_size, min_opin_mux_size, chan_type, x, y); - exit(1); - } - - /* Create a new list that we will move the muxes with 'holes' to the start of list. */ - final_labels = (int *) my_malloc(sizeof(int) * num_labels); - j = 0; - for (i = 0; i < num_labels; ++i) { - inode = pre_labels[i]; - if (opin_mux_size[inode] < max_opin_mux_size) { - final_labels[j] = inode; - ++j; - } - } - for (i = 0; i < num_labels; ++i) { - inode = pre_labels[i]; - if (opin_mux_size[inode] >= max_opin_mux_size) { - final_labels[j] = inode; - ++j; - } - } - - /* Free the baseline labelling. */ - if (pre_labels) { - free(pre_labels); - pre_labels = NULL; - } - - *num_wire_muxes = num_labels; - return final_labels; -} - -static int * -label_wire_muxes(INP int chan_num, INP int seg_num, - INP t_seg_details * seg_details, INP int max_len, - INP enum e_direction dir, INP int nodes_per_chan, - OUTP int *num_wire_muxes) { - - /* Labels the muxes on that side (seg_num, chan_num, direction). The returned array - * maps a label to the actual track #: array[0] = - * This routine orders wire muxes by their natural order, i.e. track # */ - - int itrack, start, end, num_labels, pass; - int *labels = NULL; - boolean is_endpoint; - - /* COUNT pass then a LOAD pass */ - num_labels = 0; - for (pass = 0; pass < 2; ++pass) { - /* Alloc the list on LOAD pass */ - if (pass > 0) { - labels = (int *) my_malloc(sizeof(int) * num_labels); - num_labels = 0; - } - - /* Find the tracks that are starting. */ - for (itrack = 0; itrack < nodes_per_chan; ++itrack) { - start = get_seg_start(seg_details, itrack, chan_num, seg_num); - end = get_seg_end(seg_details, itrack, start, chan_num, max_len); - - /* Skip tracks going the wrong way */ - if (seg_details[itrack].direction != dir) { - continue; - } - - /* Determine if we are a wire startpoint */ - is_endpoint = (boolean)(seg_num == start); - if (DEC_DIRECTION == seg_details[itrack].direction) { - is_endpoint = (boolean)(seg_num == end); - } - - /* Count the labels and load if LOAD pass */ - if (is_endpoint) { - if (pass > 0) { - labels[num_labels] = itrack; - } - ++num_labels; - } - } - } - - *num_wire_muxes = num_labels; - return labels; -} - -static int * -label_incoming_wires(INP int chan_num, INP int seg_num, INP int sb_seg, - INP t_seg_details * seg_details, INP int max_len, - INP enum e_direction dir, INP int nodes_per_chan, - OUTP int *num_incoming_wires, OUTP int *num_ending_wires) { - - /* Labels the incoming wires on that side (seg_num, chan_num, direction). - * The returned array maps a track # to a label: array[0] = , - * the labels 0,1,2,.. identify consecutive incoming wires that have sbox (passing wires with sbox and ending wires) */ - - int itrack, start, end, i, num_passing, num_ending, pass; - int *labels; - boolean sbox_exists, is_endpoint; - - /* Alloc the list of labels for the tracks */ - labels = (int *) my_malloc(nodes_per_chan * sizeof(int)); - for (i = 0; i < nodes_per_chan; ++i) { - labels[i] = UN_SET; /* crash hard if unset */ - } - - num_ending = 0; - num_passing = 0; - for (pass = 0; pass < 2; ++pass) { - for (itrack = 0; itrack < nodes_per_chan; ++itrack) { - if (seg_details[itrack].direction == dir) { - start = get_seg_start(seg_details, itrack, chan_num, seg_num); - end = get_seg_end(seg_details, itrack, start, chan_num, - max_len); - - /* Determine if we are a wire endpoint */ - is_endpoint = (boolean)(seg_num == end); - if (DEC_DIRECTION == seg_details[itrack].direction) { - is_endpoint = (boolean)(seg_num == start); - } - - /* Determine if we have a sbox on the wire */ - sbox_exists = is_sbox(chan_num, seg_num, sb_seg, itrack, - seg_details, UNI_DIRECTIONAL); - - switch (pass) { - /* On first pass, only load ending wire labels. */ - case 0: - if (is_endpoint) { - labels[itrack] = num_ending; - ++num_ending; - } - break; - - /* On second pass, load the passing wire labels. They - * will follow after the ending wire labels. */ - case 1: - if ((FALSE == is_endpoint) && sbox_exists) { - labels[itrack] = num_ending + num_passing; - ++num_passing; - } - break; - } - } - } - } - - *num_incoming_wires = num_passing + num_ending; - *num_ending_wires = num_ending; - return labels; -} - -static int find_label_of_track(int *wire_mux_on_track, int num_wire_muxes, - int from_track) { - int i; - - /* Returns the index/label in array wire_mux_on_track whose entry equals from_track. If none are - * found, then returns the index of the entry whose value is the largest */ - - for (i = 0; i < num_wire_muxes; i++) { - if (wire_mux_on_track[i] == from_track) { - return i; /* matched, return now */ - } - } - - vpr_printf(TIO_MESSAGE_ERROR, "Expected mux not found.\n"); - exit(1); -} diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph2.h b/vpr7_x2p/vpr/SRC/route/rr_graph2.h deleted file mode 100755 index 132c0dea4..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph2.h +++ /dev/null @@ -1,122 +0,0 @@ -#ifndef RR_GRAPH2_H -#define RR_GRAPH2_H - -/************** Global variables shared only by the rr_* modules. ************/ - -extern boolean *rr_edge_done; /* [0..num_rr_nodes-1]. Used to keep track * - * of whether or not a node has been put in * - * an edge list yet. TRUE if a node is already listed in the edges array * - * that's being constructed. Ensure that there are no duplicate edges. */ - -/******************* Subroutines exported by rr_graph2.c *********************/ - -struct s_ivec ***alloc_and_load_rr_node_indices(INP int nodes_per_chan, - INP int L_nx, - INP int L_ny, - INOUTP int *index, - INP t_seg_details * seg_details) ; - -void free_rr_node_indices(INP t_ivec *** L_rr_node_indices); - -int get_rr_node_index(int x, int y, t_rr_type rr_type, int ptc, - t_ivec *** L_rr_node_indices); - -void free_seg_details(t_seg_details * seg_details, int nodes_per_chan); - -t_seg_details *alloc_and_load_seg_details(INOUTP int *nodes_per_chan, - INP int max_len, - INP int num_seg_types, - INP t_segment_inf * segment_inf, - INP boolean use_full_seg_groups, - INP boolean is_global_graph, - INP enum e_directionality - directionality); - -void dump_seg_details(t_seg_details * seg_details, int nodes_per_chan, - const char *fname); - -int get_seg_start(INP t_seg_details * seg_details, - INP int itrack, - INP int chan_num, - INP int seg_num); - -int get_seg_end(INP t_seg_details * seg_details, - INP int itrack, - INP int istart, - INP int chan_num, - INP int seg_max); - -boolean is_cbox(INP int chan, - INP int seg, - INP int track, - INP t_seg_details * seg_details, - INP enum e_directionality directionality); - -boolean is_sbox(INP int chan, - INP int wire_seg, - INP int sb_seg, - INP int track, - INP t_seg_details * seg_details, - INP enum e_directionality directionality); - -int get_bidir_opin_connections(INP int i, - INP int j, - INP int ipin, - INP struct s_linked_edge **edge_list, - INP int *****opin_to_track_map, - INP int Fc, - INP boolean * L_rr_edge_done, - INP t_ivec *** L_rr_node_indices, - INP t_seg_details * seg_details); - -int get_unidir_opin_connections(INP int chan, - INP int seg, - INP int Fc, - INP t_rr_type chan_type, - INP t_seg_details * seg_details, - INOUTP t_linked_edge ** edge_list_ptr, - INOUTP int **Fc_ofs, - INOUTP boolean * L_rr_edge_done, - INP int max_len, - INP int nodes_per_chan, - INP t_ivec *** L_rr_node_indices, - OUTP boolean * Fc_clipped); - -int get_track_to_ipins(int seg, int chan, int track, - t_linked_edge ** edge_list_ptr, t_ivec *** L_rr_node_indices, - struct s_ivec ****track_to_ipin_lookup, t_seg_details * seg_details, - enum e_rr_type chan_type, int chan_length, int wire_to_ipin_switch, - enum e_directionality directionality); - -int get_track_to_tracks(INP int from_chan, - INP int from_seg, - INP int from_track, - INP t_rr_type from_type, - INP int to_seg, - INP t_rr_type to_type, - INP int chan_len, - INP int nodes_per_chan, - INP int *opin_mux_size, - INP int Fs_per_side, - INP short *****sblock_pattern, - INOUTP struct s_linked_edge **edge_list, - INP t_seg_details * seg_details, - INP enum e_directionality directionality, - INP t_ivec *** L_rr_node_indices, - INOUTP boolean * L_rr_edge_done, - INP struct s_ivec ***switch_block_conn); - -short *****alloc_sblock_pattern_lookup(INP int L_nx, - INP int L_ny, - INP int nodes_per_chan); -void free_sblock_pattern_lookup(INOUTP short *****sblock_pattern); -void load_sblock_pattern_lookup(INP int i, - INP int j, - INP int nodes_per_chan, - INP t_seg_details * seg_details, - INP int Fs, - INP enum e_switch_block_type switch_block_type, - INOUTP short *****sblock_pattern); - -#endif - diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_area.c b/vpr7_x2p/vpr/SRC/route/rr_graph_area.c deleted file mode 100755 index 7790d57af..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_area.c +++ /dev/null @@ -1,733 +0,0 @@ -#include -#include -#include "util.h" -#include "vpr_types.h" -#include -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph_area.h" - -/* Some useful subroutines in Spice utils*/ -int determine_tree_mux_level(int mux_size); -int determine_num_input_basis_multilevel_mux(int mux_size, int mux_level); - -/************************ Subroutines local to this module *******************/ - -static void count_bidir_routing_transistors(int num_switch, float R_minW_nmos, - float R_minW_pmos, float sram_area); - -static void count_unidir_routing_transistors(t_segment_inf * segment_inf, - float R_minW_nmos, float R_minW_pmos, float sram_area); - -static float get_cblock_trans(int *num_inputs_to_cblock, int* switches_to_cblock, - int max_inputs_to_cblock, float trans_cblock_to_lblock_buf, - float trans_sram_bit); - -static float *alloc_and_load_unsharable_switch_trans(int num_switch, - float trans_sram_bit, float R_minW_nmos); - -static float *alloc_and_load_sharable_switch_trans(int num_switch, - float trans_sram_bit, float R_minW_nmos, float R_minW_pmos); - -/* mrFPGA: Xifan TANG*/ -//static -//float trans_per_buf(float Rbuf, float R_minW_nmos, float R_minW_pmos); -/*end */ - -static float trans_per_mux(int num_inputs, float trans_sram_bit, - float pass_trans_area, t_switch_inf target_switch); - -static float trans_per_R(float Rtrans, float R_minW_trans); - -/*************************** Subroutine definitions **************************/ - -void count_routing_transistors(enum e_directionality directionality, - int num_switch, t_segment_inf * segment_inf, float R_minW_nmos, - float R_minW_pmos, float sram_area) { - - /* Counts how many transistors are needed to implement the FPGA routing * - * resources. Call this only when an rr_graph exists. It does not count * - * the transistors used in logic blocks, but it counts the transistors in * - * the input connection block multiplexers and in the output pin drivers and * - * pass transistors. NB: this routine assumes pass transistors always * - * generate two edges (one forward, one backward) between two nodes. * - * Physically, this is what happens -- make sure your rr_graph does it. * - * * - * I assume a minimum width transistor takes 1 unit of area. A double-width * - * transistor takes the twice the diffusion width, but the same spacing, so * - * I assume it takes 1.5x the area of a minimum-width transitor. */ - if (directionality == BI_DIRECTIONAL) { - count_bidir_routing_transistors(num_switch, R_minW_nmos, R_minW_pmos, sram_area); - } else { - assert(directionality == UNI_DIRECTIONAL); - count_unidir_routing_transistors(segment_inf, R_minW_nmos, R_minW_pmos, sram_area); - } -} - -void count_bidir_routing_transistors(int num_switch, float R_minW_nmos, - float R_minW_pmos, float sram_area) { - - /* Tri-state buffers are designed as a buffer followed by a pass transistor. * - * I make Rbuffer = Rpass_transitor = 1/2 Rtri-state_buffer. * - * I make the pull-up and pull-down sides of the buffer the same strength -- * - * i.e. I make the p transistor R_minW_pmos / R_minW_nmos wider than the n * - * transistor. * - * * - * I generate two area numbers in this routine: ntrans_sharing and * - * ntrans_no_sharing. ntrans_sharing exactly reflects what the timing * - * analyzer, etc. works with -- each switch is a completely self contained * - * pass transistor or tri-state buffer. In the case of tri-state buffers * - * this is rather pessimisitic. The inverter chain part of the buffer (as * - * opposed to the pass transistor + SRAM output part) can be shared by * - * several switches in the same location. Obviously all the switches from * - * an OPIN can share one buffer. Also, CHANX and CHANY switches at the same * - * spot (i,j) on a single segment can share a buffer. For a more realistic * - * area number I assume all buffered switches from a node that are at the * - * *same (i,j) location* can share one buffer. Only the lowest resistance * - * (largest) buffer is implemented. In practice, you might want to build * - * something that is 1.5x or 2x the largest buffer, so this may be a bit * - * optimistic (but I still think it's pretty reasonable). */ - - int *num_inputs_to_cblock; /* [0..num_rr_nodes-1], but all entries not */ - /* Xifan TANG: cb switches*/ - int *switches_to_cblock; /* [0..num_rr_nodes-1], but all entries not */ - /* END */ - - /* corresponding to IPINs will be 0. */ - - boolean * cblock_counted; /* [0..max(nx,ny)] -- 0th element unused. */ - float *shared_buffer_trans; /* [0..max_nx,ny)] */ - float *unsharable_switch_trans, *sharable_switch_trans; /* [0..num_switch-1] */ - - t_rr_type from_rr_type, to_rr_type; - int from_node, to_node, iedge, num_edges, maxlen; - int iswitch, i, j, iseg, max_inputs_to_cblock; - float input_cblock_trans, shared_opin_buffer_trans; - const float trans_sram_bit = sram_area; - - /* Two variables below are the accumulator variables that add up all the * - * transistors in the routing. Make doubles so that they don't stop * - * incrementing once adding a switch makes a change of less than 1 part in * - * 10^7 to the total. If this still isn't good enough (adding 1 part in * - * 10^15 will still be thrown away), compute the transistor count in * - * "chunks", by adding up inodes 1 to 1000, 1001 to 2000 and then summing * - * the partial sums together. */ - - double ntrans_sharing, ntrans_no_sharing; - - /* Buffers from the routing to the ipin cblock inputs, and from the ipin * - * cblock outputs to the logic block, respectively. Assume minimum size n * - * transistors, and ptransistors sized to make the pull-up R = pull-down R. */ - - float trans_track_to_cblock_buf; - float trans_cblock_to_lblock_buf; - - ntrans_sharing = 0.; - ntrans_no_sharing = 0.; - max_inputs_to_cblock = 0; - - /* Assume the two buffers below are 4x minimum drive strength (enough to * - * drive a fanout of up to 16 pretty nicely -- should cover a reasonable * - * wiring C plus the fanout. */ - - trans_track_to_cblock_buf = trans_per_buf(R_minW_nmos / 4., R_minW_nmos, - R_minW_pmos); - - trans_cblock_to_lblock_buf = trans_per_buf(R_minW_nmos / 4., R_minW_nmos, - R_minW_pmos); - - num_inputs_to_cblock = (int *) my_calloc(num_rr_nodes, sizeof(int)); - - /* Xifan TANG: cb switches*/ - switches_to_cblock = (int *) my_calloc(num_rr_nodes, sizeof(int)); - for (i = 0; i < num_rr_nodes; i++) { - switches_to_cblock[i] = OPEN; - } - /* END */ - - maxlen = std::max(nx, ny) + 1; - cblock_counted = (boolean *) my_calloc(maxlen, sizeof(boolean)); - shared_buffer_trans = (float *) my_calloc(maxlen, sizeof(float)); - - unsharable_switch_trans = alloc_and_load_unsharable_switch_trans(num_switch, - trans_sram_bit, R_minW_nmos); - - sharable_switch_trans = alloc_and_load_sharable_switch_trans(num_switch, - trans_sram_bit, R_minW_nmos, R_minW_pmos); - - for (from_node = 0; from_node < num_rr_nodes; from_node++) { - - from_rr_type = rr_node[from_node].type; - - switch (from_rr_type) { - - case CHANX: - case CHANY: - num_edges = rr_node[from_node].num_edges; - - for (iedge = 0; iedge < num_edges; iedge++) { - - to_node = rr_node[from_node].edges[iedge]; - to_rr_type = rr_node[to_node].type; - - switch (to_rr_type) { - - case CHANX: - case CHANY: - iswitch = rr_node[from_node].switches[iedge]; - - if (switch_inf[iswitch].buffered) { - iseg = seg_index_of_sblock(from_node, to_node); - shared_buffer_trans[iseg] = std::max( - shared_buffer_trans[iseg], - sharable_switch_trans[iswitch]); - - ntrans_no_sharing += unsharable_switch_trans[iswitch] - + sharable_switch_trans[iswitch]; - ntrans_sharing += unsharable_switch_trans[iswitch]; - } else if (from_node < to_node) { - - /* Pass transistor shared by two edges -- only count once. * - * Also, no part of a pass transistor is sharable. */ - - ntrans_no_sharing += unsharable_switch_trans[iswitch]; - ntrans_sharing += unsharable_switch_trans[iswitch]; - } - break; - - case IPIN: - num_inputs_to_cblock[to_node]++; - max_inputs_to_cblock = std::max(max_inputs_to_cblock, - num_inputs_to_cblock[to_node]); - - iseg = seg_index_of_cblock(from_rr_type, to_node); - /* Xifan TANG: cb switches*/ - if (OPEN == switches_to_cblock[to_node]) { - switches_to_cblock[to_node] = rr_node[from_node].switches[iedge]; - } else { - assert(switches_to_cblock[to_node] == rr_node[from_node].switches[iedge]); - } - /* END */ - - if (cblock_counted[iseg] == FALSE) { - cblock_counted[iseg] = TRUE; - ntrans_sharing += trans_track_to_cblock_buf; - ntrans_no_sharing += trans_track_to_cblock_buf; - } - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in count_routing_transistors:\n"); - vpr_printf(TIO_MESSAGE_ERROR, "\tUnexpected connection from node %d (type %d) to node %d (type %d).\n", - from_node, from_rr_type, to_node, to_rr_type); - exit(1); - break; - - } /* End switch on to_rr_type. */ - - } /* End for each edge. */ - - /* Now add in the shared buffer transistors, and reset some flags. */ - - if (from_rr_type == CHANX) { - for (i = rr_node[from_node].xlow - 1; - i <= rr_node[from_node].xhigh; i++) { - ntrans_sharing += shared_buffer_trans[i]; - shared_buffer_trans[i] = 0.; - } - - for (i = rr_node[from_node].xlow; i <= rr_node[from_node].xhigh; - i++) - cblock_counted[i] = FALSE; - - } else { /* CHANY */ - for (j = rr_node[from_node].ylow - 1; - j <= rr_node[from_node].yhigh; j++) { - ntrans_sharing += shared_buffer_trans[j]; - shared_buffer_trans[j] = 0.; - } - - for (j = rr_node[from_node].ylow; j <= rr_node[from_node].yhigh; - j++) - cblock_counted[j] = FALSE; - - } - break; - - case OPIN: - num_edges = rr_node[from_node].num_edges; - shared_opin_buffer_trans = 0.; - - for (iedge = 0; iedge < num_edges; iedge++) { - iswitch = rr_node[from_node].switches[iedge]; - ntrans_no_sharing += unsharable_switch_trans[iswitch] - + sharable_switch_trans[iswitch]; - ntrans_sharing += unsharable_switch_trans[iswitch]; - - shared_opin_buffer_trans = std::max(shared_opin_buffer_trans, - sharable_switch_trans[iswitch]); - } - - ntrans_sharing += shared_opin_buffer_trans; - break; - - default: - break; - - } /* End switch on from_rr_type */ - } /* End for all nodes */ - - free(cblock_counted); - free(shared_buffer_trans); - free(unsharable_switch_trans); - free(sharable_switch_trans); - - /* Now add in the input connection block transistors. */ - - input_cblock_trans = get_cblock_trans(num_inputs_to_cblock, /*Xifan TANG:*/switches_to_cblock, - max_inputs_to_cblock, trans_cblock_to_lblock_buf, trans_sram_bit); - - free(num_inputs_to_cblock); - - /* Xifan TANG: cb switches */ - free(switches_to_cblock); - /* END */ - - ntrans_sharing += input_cblock_trans; - ntrans_no_sharing += input_cblock_trans; - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Routing area (in minimum width transistor areas)...\n"); - vpr_printf(TIO_MESSAGE_INFO, "\tAssuming no buffer sharing (pessimistic). Total: %#g, per logic tile: %#g\n", - ntrans_no_sharing, ntrans_no_sharing / (float) (nx * ny)); - vpr_printf(TIO_MESSAGE_INFO, "\tAssuming buffer sharing (slightly optimistic). Total: %#g, per logic tile: %#g\n", - ntrans_sharing, ntrans_sharing / (float) (nx * ny)); - vpr_printf(TIO_MESSAGE_INFO, "\n"); -} - -void count_unidir_routing_transistors(t_segment_inf * segment_inf, - float R_minW_nmos, float R_minW_pmos, float sram_area) { - boolean * cblock_counted; /* [0..max(nx,ny)] -- 0th element unused. */ - int *num_inputs_to_cblock; /* [0..num_rr_nodes-1], but all entries not */ - /* Xifan TANG: cb switches*/ - int *switches_to_cblock; /* [0..num_rr_nodes-1], but all entries not */ - /* END */ - - /* corresponding to IPINs will be 0. */ - - t_rr_type from_rr_type, to_rr_type; - int i, j, iseg, from_node, to_node, iedge, num_edges, maxlen; - int max_inputs_to_cblock, cost_index, seg_type, switch_type; - float input_cblock_trans; - const float trans_sram_bit = sram_area; - - /* Two variables below are the accumulator variables that add up all the * - * transistors in the routing. Make doubles so that they don't stop * - * incrementing once adding a switch makes a change of less than 1 part in * - * 10^7 to the total. If this still isn't good enough (adding 1 part in * - * 10^15 will still be thrown away), compute the transistor count in * - * "chunks", by adding up inodes 1 to 1000, 1001 to 2000 and then summing * - * the partial sums together. */ - - double ntrans; - - /* Buffers from the routing to the ipin cblock inputs, and from the ipin * - * cblock outputs to the logic block, respectively. Assume minimum size n * - * transistors, and ptransistors sized to make the pull-up R = pull-down R. */ - - float trans_track_to_cblock_buf; - float trans_cblock_to_lblock_buf; - - max_inputs_to_cblock = 0; - - /* Assume the two buffers below are 4x minimum drive strength (enough to * - * drive a fanout of up to 16 pretty nicely -- should cover a reasonable * - * wiring C plus the fanout. */ - - trans_track_to_cblock_buf = trans_per_buf(R_minW_nmos / 4., R_minW_nmos, - R_minW_pmos); - - trans_cblock_to_lblock_buf = trans_per_buf(R_minW_nmos / 4., R_minW_nmos, - R_minW_pmos); - - num_inputs_to_cblock = (int *) my_calloc(num_rr_nodes, sizeof(int)); - - /* Xifan TANG: cb switches*/ - switches_to_cblock = (int *) my_calloc(num_rr_nodes, sizeof(int)); - for (i = 0; i < num_rr_nodes; i++) { - switches_to_cblock[i] = OPEN; - } - /* END */ - - maxlen = std::max(nx, ny) + 1; - cblock_counted = (boolean *) my_calloc(maxlen, sizeof(boolean)); - - ntrans = 0; - for (from_node = 0; from_node < num_rr_nodes; from_node++) { - - from_rr_type = rr_node[from_node].type; - - switch (from_rr_type) { - - case CHANX: - case CHANY: - num_edges = rr_node[from_node].num_edges; - cost_index = rr_node[from_node].cost_index; - seg_type = rr_indexed_data[cost_index].seg_index; - /* Xifan TANG: Switch Segment Pattern Support - * we should consider the switch no in the segment but in the rr_node - */ - if (rr_node[from_node].unbuf_switched) { - switch_type = rr_node[from_node].driver_switch; - } else { - switch_type = segment_inf[seg_type].wire_switch; - assert( - segment_inf[seg_type].wire_switch == segment_inf[seg_type].opin_switch); - } - assert(switch_inf[switch_type].mux_trans_size >= 1); - /* can't be smaller than min sized transistor */ - - assert(rr_node[from_node].num_opin_drivers == 0); - /* undir has no opin or wire switches */ - assert(rr_node[from_node].num_wire_drivers == 0); - /* undir has no opin or wire switches */ - - /* Each wire segment begins with a multipexer followed by a driver for unidirectional */ - /* Each multiplexer contains all the fan-in to that routing node */ - /* Add up area of multiplexer */ - ntrans += trans_per_mux(rr_node[from_node].fan_in, trans_sram_bit, - switch_inf[switch_type].mux_trans_size, switch_inf[switch_type]); - - /* Add up area of buffer */ - /* Xifan TANG: Switch Segment Pattern Support*/ - if ((switch_inf[switch_type].buf_size == 0)&&(0 != strcmp("unbuf_mux",switch_inf[switch_type].type))) { - ntrans += trans_per_buf(switch_inf[switch_type].R, R_minW_nmos, - R_minW_pmos); - } else { - ntrans += switch_inf[switch_type].buf_size; - } - - for (iedge = 0; iedge < num_edges; iedge++) { - - to_node = rr_node[from_node].edges[iedge]; - to_rr_type = rr_node[to_node].type; - - switch (to_rr_type) { - - case CHANX: - case CHANY: - break; - - case IPIN: - num_inputs_to_cblock[to_node]++; - max_inputs_to_cblock = std::max(max_inputs_to_cblock, - num_inputs_to_cblock[to_node]); - iseg = seg_index_of_cblock(from_rr_type, to_node); - - /* Xifan TANG: cb switches*/ - if (OPEN == switches_to_cblock[to_node]) { - switches_to_cblock[to_node] = rr_node[from_node].switches[iedge]; - } else { - assert(switches_to_cblock[to_node] == rr_node[from_node].switches[iedge]); - } - /* END */ - - if (cblock_counted[iseg] == FALSE) { - cblock_counted[iseg] = TRUE; - ntrans += trans_track_to_cblock_buf; - } - break; - - default: - vpr_printf(TIO_MESSAGE_ERROR, "in count_routing_transistors:\n"); - vpr_printf(TIO_MESSAGE_ERROR, "\tUnexpected connection from node %d (type %d) to node %d (type %d).\n", - from_node, from_rr_type, to_node, to_rr_type); - exit(1); - break; - - } /* End switch on to_rr_type. */ - - } /* End for each edge. */ - - /* Reset some flags */ - if (from_rr_type == CHANX) { - for (i = rr_node[from_node].xlow; i <= rr_node[from_node].xhigh; - i++) - cblock_counted[i] = FALSE; - - } else { /* CHANY */ - for (j = rr_node[from_node].ylow; j <= rr_node[from_node].yhigh; - j++) - cblock_counted[j] = FALSE; - - } - break; - case OPIN: - break; - - default: - break; - - } /* End switch on from_rr_type */ - } /* End for all nodes */ - - /* Now add in the input connection block transistors. */ - - input_cblock_trans = get_cblock_trans(num_inputs_to_cblock, /*Xifan TANG*/switches_to_cblock, - max_inputs_to_cblock, trans_cblock_to_lblock_buf, trans_sram_bit); - - free(cblock_counted); - free(num_inputs_to_cblock); - - /* Xifan TANG: cb switches */ - free(switches_to_cblock); - /* END */ - - ntrans += input_cblock_trans; - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Routing area (in minimum width transistor areas)...\n"); - vpr_printf(TIO_MESSAGE_INFO, "\tTotal routing area: %#g, per logic tile: %#g\n", ntrans, ntrans / (float) (nx * ny)); -} - -static float get_cblock_trans(int *num_inputs_to_cblock, int* switches_to_cblock, - int max_inputs_to_cblock, float trans_cblock_to_lblock_buf, - float trans_sram_bit) { - - /* Computes the transistors in the input connection block multiplexers and * - * the buffers from connection block outputs to the logic block input pins. * - * For speed, I precompute the number of transistors in the multiplexers of * - * interest. */ - - float *trans_per_cblock; /* [0..max_inputs_to_cblock] */ - float trans_count; - int i, num_inputs; - - trans_per_cblock = (float *) my_malloc( - (max_inputs_to_cblock + 1) * sizeof(float)); - - trans_per_cblock[0] = 0.; /* i.e., not an IPIN or no inputs */ - - /* With one or more inputs, add the mux and output buffer. I add the output * - * buffer even when the number of inputs = 1 (i.e. no mux) because I assume * - * I need the drivability just for metal capacitance. */ - /* - for (i = 1; i <= max_inputs_to_cblock; i++) - trans_per_cblock[i] = trans_per_mux(i, trans_sram_bit, - ipin_mux_trans_size) + trans_cblock_to_lblock_buf; - */ - - trans_count = 0.; - - for (i = 0; i < num_rr_nodes; i++) { - num_inputs = num_inputs_to_cblock[i]; - /* Xifan TANG: consider cblock structure in area estimation */ - assert((0 < num_inputs)||(0 == num_inputs)); - if (0 < num_inputs) { - assert(OPEN != switches_to_cblock[i]); - trans_count += trans_per_mux(num_inputs, trans_sram_bit, - ipin_mux_trans_size, switch_inf[switches_to_cblock[i]]) + trans_cblock_to_lblock_buf; - } - /* END */ - /* trans_count += trans_per_cblock[num_inputs]; */ - } - - free(trans_per_cblock); - return (trans_count); -} - -static float * -alloc_and_load_unsharable_switch_trans(int num_switch, float trans_sram_bit, - float R_minW_nmos) { - - /* Loads up an array that says how many transistors are needed to implement * - * the unsharable portion of each switch type. The SRAM bit of a switch and * - * the pass transistor (forming either the entire switch or the output part * - * of a tri-state buffer) are both unsharable. */ - - float *unsharable_switch_trans, Rpass; - int i; - - unsharable_switch_trans = (float *) my_malloc(num_switch * sizeof(float)); - - for (i = 0; i < num_switch; i++) { - - if (switch_inf[i].buffered == FALSE) { - Rpass = switch_inf[i].R; - } else { /* Buffer. Set Rpass = Rbuf = 1/2 Rtotal. */ - Rpass = switch_inf[i].R / 2.; - } - - unsharable_switch_trans[i] = trans_per_R(Rpass, R_minW_nmos) - + trans_sram_bit; - } - - return (unsharable_switch_trans); -} - -static float * -alloc_and_load_sharable_switch_trans(int num_switch, float trans_sram_bit, - float R_minW_nmos, float R_minW_pmos) { - - /* Loads up an array that says how many transistor are needed to implement * - * the sharable portion of each switch type. The SRAM bit of a switch and * - * the pass transistor (forming either the entire switch or the output part * - * of a tri-state buffer) are both unsharable. Only the buffer part of a * - * buffer switch is sharable. */ - - float *sharable_switch_trans, Rbuf; - int i; - - sharable_switch_trans = (float *) my_malloc(num_switch * sizeof(float)); - - for (i = 0; i < num_switch; i++) { - - if (switch_inf[i].buffered == FALSE) { - sharable_switch_trans[i] = 0.; - } else { /* Buffer. Set Rbuf = Rpass = 1/2 Rtotal. */ - Rbuf = switch_inf[i].R / 2.; - sharable_switch_trans[i] = trans_per_buf(Rbuf, R_minW_nmos, - R_minW_pmos); - } - } - - return (sharable_switch_trans); -} - -/*mrFPGA: Xifan TANG, make this function accessible out of this source file*/ -//static -/*end */ -float trans_per_buf(float Rbuf, float R_minW_nmos, float R_minW_pmos) { - - /* Returns the number of minimum width transistor area equivalents needed to * - * implement this buffer. Assumes a stage ratio of 4, and equal strength * - * pull-up and pull-down paths. */ - - int num_stage, istage; - float trans_count, stage_ratio, Rstage; - - if (Rbuf > 0.6 * R_minW_nmos || Rbuf <= 0.) { /* Use a single-stage buffer */ - trans_count = trans_per_R(Rbuf, R_minW_nmos) - + trans_per_R(Rbuf, R_minW_pmos); - } else { /* Use a multi-stage buffer */ - - /* Target stage ratio = 4. 1 minimum width buffer, then num_stage bigger * - * ones. */ - - num_stage = nint(log10(R_minW_nmos / Rbuf) / log10(4.)); - num_stage = std::max(num_stage, 1); - stage_ratio = pow((float)(R_minW_nmos / Rbuf), (float)( 1. / (float) num_stage)); - - Rstage = R_minW_nmos; - trans_count = 0.; - - for (istage = 0; istage <= num_stage; istage++) { - trans_count += trans_per_R(Rstage, R_minW_nmos) - + trans_per_R(Rstage, R_minW_pmos); - Rstage /= stage_ratio; - } - } - - return (trans_count); -} - -static float trans_per_mux(int num_inputs, float trans_sram_bit, - float pass_trans_area, t_switch_inf target_switch) { - - /* Returns the number of transistors needed to build a pass transistor mux. * - * DOES NOT include input buffers or any output buffer. * - * Attempts to select smart multiplexer size depending on number of inputs * - * For multiplexers with inputs 4 or less, one level is used, more has two * - * levels. */ - float ntrans, sram_trans, pass_trans; - int num_second_stage_trans; - int mux_basis = 0; - - /* Xifan TANG: Original VPR area function is below, I replace them by considering more physical design parameters */ - /* - if (num_inputs <= 1) { - return (0); - } else if (num_inputs == 2) { - pass_trans = 2 * pass_trans_area; - sram_trans = 1 * trans_sram_bit; - } else if (num_inputs <= 4) { - */ - /* One-hot encoding */ - /* - pass_trans = num_inputs * pass_trans_area; - sram_trans = num_inputs * trans_sram_bit; - } else { - */ - /* This is a large multiplexer so design it using a two-level multiplexer * - * + 0.00001 is to make sure exact square roots two don't get rounded down * - * to one lower level. */ - /* - num_second_stage_trans = (int)floor((float)sqrt((float)num_inputs) + 0.00001); - pass_trans = (num_inputs + num_second_stage_trans) * pass_trans_area; - sram_trans = (ceil( - (float) num_inputs / num_second_stage_trans - 0.00001) - + num_second_stage_trans) * trans_sram_bit; - if (num_second_stage_trans == 2) { - */ - /* Can use one-bit instead of a two-bit one-hot encoding for the second stage */ - /* Eliminates one sram bit counted earlier */ - /* - sram_trans -= 1 * trans_sram_bit; - } - } - */ - /* Xifan TANG: new function starts */ - if (num_inputs <= 1) { - return 0; - } - /* Consider different structure */ - switch (target_switch.structure) { - case SPICE_MODEL_STRUCTURE_TREE: - sram_trans = trans_sram_bit * determine_tree_mux_level(num_inputs); - pass_trans = (num_inputs - 1)* 2 * pass_trans_area; - break; - case SPICE_MODEL_STRUCTURE_ONELEVEL: - sram_trans = trans_sram_bit * num_inputs; - pass_trans = (num_inputs * pass_trans_area); - break; - case SPICE_MODEL_STRUCTURE_MULTILEVEL: - assert(1 < target_switch.switch_num_level); - mux_basis = determine_num_input_basis_multilevel_mux(num_inputs, target_switch.switch_num_level); - sram_trans = trans_sram_bit * target_switch.switch_num_level * mux_basis; - num_second_stage_trans = (int)pow((double)mux_basis, (double)(target_switch.switch_num_level - 1)); - pass_trans = ((num_second_stage_trans - 1) * mux_basis/(mux_basis-1)) * pass_trans_area - + num_inputs * pass_trans_area; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid structure for switch(name=%s)!\n", - __FILE__, __LINE__, target_switch.name); - exit(1); - } - - ntrans = pass_trans + sram_trans; - return (ntrans); -} - -static float trans_per_R(float Rtrans, float R_minW_trans) { - - /* Returns the number of minimum width transistor area equivalents needed * - * to make a transistor with Rtrans, given that the resistance of a minimum * - * width transistor of this type is R_minW_trans. */ - - float trans_area; - - if (Rtrans <= 0.) /* Assume resistances are nonsense -- use min. width */ - return (1.); - - if (Rtrans >= R_minW_trans) - return (1.); - - /* Area = minimum width area (1) + 0.5 for each additional unit of width. * - * The 50% factor takes into account the "overlapping" that occurs in * - * horizontally-paralleled transistors, and the need for only one spacing, * - * not two (i.e. two min W transistors need two spaces; a 2W transistor * - * needs only 1). */ - - trans_area = 0.5 * R_minW_trans / Rtrans + 0.5; - return (trans_area); -} diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_area.h b/vpr7_x2p/vpr/SRC/route/rr_graph_area.h deleted file mode 100755 index c933648ef..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_area.h +++ /dev/null @@ -1,6 +0,0 @@ - -float trans_per_buf(float Rbuf, float R_minW_nmos, float R_minW_pmos); - -void count_routing_transistors(enum e_directionality directionality, - int num_switch, t_segment_inf * segment_inf, float R_minW_nmos, - float R_minW_pmos, float sram_area); diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_indexed_data.c b/vpr7_x2p/vpr/SRC/route/rr_graph_indexed_data.c deleted file mode 100755 index 476d093b9..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_indexed_data.c +++ /dev/null @@ -1,338 +0,0 @@ -#include /* Needed only for sqrt call (remove if sqrt removed) */ -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph2.h" -#include "rr_graph_indexed_data.h" -#include "read_xml_arch_file.h" - -/* mrFPGA: Xifan TANG */ -#include "mrfpga_globals.h" -/* end */ - -/******************* Subroutines local to this module ************************/ - -static void load_rr_indexed_data_base_costs(int nodes_per_chan, - t_ivec *** L_rr_node_indices, enum e_base_cost_type base_cost_type, - int wire_to_ipin_switch); - -static float get_delay_normalization_fac(int nodes_per_chan, - t_ivec *** L_rr_node_indices); - -static float get_average_opin_delay(t_ivec *** L_rr_node_indices, - int nodes_per_chan); - -static void load_rr_indexed_data_T_values(int index_start, - int num_indices_to_load, t_rr_type rr_type, int nodes_per_chan, - t_ivec *** L_rr_node_indices, const t_segment_inf * segment_inf); - -/******************** Subroutine definitions *********************************/ - -/* Allocates the rr_indexed_data array and loads it with appropriate values. * - * It currently stores the segment type (or OPEN if the index doesn't * - * correspond to an CHANX or CHANY type), the base cost of nodes of that * - * type, and some info to allow rapid estimates of time to get to a target * - * to be computed by the router. * - * - * Right now all SOURCES have the same base cost; and similarly there's only * - * one base cost for each of SINKs, OPINs, and IPINs (four total). This can * - * be changed just by allocating more space in the array below and changing * - * the cost_index values for these rr_nodes, if you want to make some pins * - * etc. more expensive than others. I give each segment type in an * - * x-channel its own cost_index, and each segment type in a y-channel its * - * own cost_index. */ -void alloc_and_load_rr_indexed_data(INP const t_segment_inf * segment_inf, - INP int num_segment, INP t_ivec *** L_rr_node_indices, - INP int nodes_per_chan, int wire_to_ipin_switch, - enum e_base_cost_type base_cost_type) { - - int iseg, length, i, index; - - num_rr_indexed_data = CHANX_COST_INDEX_START + (2 * num_segment); - rr_indexed_data = (t_rr_indexed_data *) my_malloc( - num_rr_indexed_data * sizeof(t_rr_indexed_data)); - - /* For rr_types that aren't CHANX or CHANY, base_cost is valid, but most * - * * other fields are invalid. For IPINs, the T_linear field is also valid; * - * * all other fields are invalid. For SOURCES, SINKs and OPINs, all fields * - * * other than base_cost are invalid. Mark invalid fields as OPEN for safety. */ - - for (i = SOURCE_COST_INDEX; i <= IPIN_COST_INDEX; i++) { - rr_indexed_data[i].ortho_cost_index = OPEN; - rr_indexed_data[i].seg_index = OPEN; - rr_indexed_data[i].inv_length = OPEN; - rr_indexed_data[i].T_linear = OPEN; - rr_indexed_data[i].T_quadratic = OPEN; - rr_indexed_data[i].C_load = OPEN; - } - - rr_indexed_data[IPIN_COST_INDEX].T_linear = - switch_inf[wire_to_ipin_switch].Tdel; - - /* X-directed segments. */ - - for (iseg = 0; iseg < num_segment; iseg++) { - index = CHANX_COST_INDEX_START + iseg; - - rr_indexed_data[index].ortho_cost_index = index + num_segment; - - if (segment_inf[iseg].longline) - length = nx; - else - length = std::min(segment_inf[iseg].length, nx); - - rr_indexed_data[index].inv_length = 1. / length; - rr_indexed_data[index].seg_index = iseg; - } - - load_rr_indexed_data_T_values(CHANX_COST_INDEX_START, num_segment, CHANX, - nodes_per_chan, L_rr_node_indices, segment_inf); - - /* Y-directed segments. */ - - for (iseg = 0; iseg < num_segment; iseg++) { - index = CHANX_COST_INDEX_START + num_segment + iseg; - - rr_indexed_data[index].ortho_cost_index = index - num_segment; - - if (segment_inf[iseg].longline) - length = ny; - else - length = std::min(segment_inf[iseg].length, ny); - - rr_indexed_data[index].inv_length = 1. / length; - rr_indexed_data[index].seg_index = iseg; - } - - load_rr_indexed_data_T_values((CHANX_COST_INDEX_START + num_segment), - num_segment, CHANY, nodes_per_chan, L_rr_node_indices, segment_inf); - - load_rr_indexed_data_base_costs(nodes_per_chan, L_rr_node_indices, - base_cost_type, wire_to_ipin_switch); - -} - -static void load_rr_indexed_data_base_costs(int nodes_per_chan, - t_ivec *** L_rr_node_indices, enum e_base_cost_type base_cost_type, - int wire_to_ipin_switch) { - - /* Loads the base_cost member of rr_indexed_data according to the specified * - * base_cost_type. */ - - float delay_normalization_fac; - int index; - - if (base_cost_type == DELAY_NORMALIZED) { - delay_normalization_fac = get_delay_normalization_fac(nodes_per_chan, - L_rr_node_indices); - } else { - delay_normalization_fac = 1.; - } - - if (base_cost_type == DEMAND_ONLY || base_cost_type == DELAY_NORMALIZED) { - rr_indexed_data[SOURCE_COST_INDEX].base_cost = delay_normalization_fac; - /* rr_indexed_data[SOURCE_COST_INDEX].base_cost = 0; Xifan TANG: TODO: Update routing cost to 1*/ - rr_indexed_data[SINK_COST_INDEX].base_cost = 0.; - rr_indexed_data[OPIN_COST_INDEX].base_cost = delay_normalization_fac; - /*rr_indexed_data[OPIN_COST_INDEX].base_cost = 0.95; Xifan TANG: TODO: Update routing cost to 1*/ - -#ifndef SPEC - rr_indexed_data[IPIN_COST_INDEX].base_cost = 0.95 - * delay_normalization_fac; -#else /* Avoid roundoff for SPEC */ - rr_indexed_data[IPIN_COST_INDEX].base_cost = - delay_normalization_fac; -#endif - } - - else if (base_cost_type == INTRINSIC_DELAY) { - rr_indexed_data[SOURCE_COST_INDEX].base_cost = 0.; - rr_indexed_data[SINK_COST_INDEX].base_cost = 0.; - rr_indexed_data[OPIN_COST_INDEX].base_cost = get_average_opin_delay( - L_rr_node_indices, nodes_per_chan); - rr_indexed_data[IPIN_COST_INDEX].base_cost = - switch_inf[wire_to_ipin_switch].Tdel; - } - - /* Load base costs for CHANX and CHANY segments */ - - for (index = CHANX_COST_INDEX_START; index < num_rr_indexed_data; index++) { - if (base_cost_type == INTRINSIC_DELAY) - rr_indexed_data[index].base_cost = rr_indexed_data[index].T_linear - + rr_indexed_data[index].T_quadratic; - else - /* rr_indexed_data[index].base_cost = delay_normalization_fac / - rr_indexed_data[index].inv_length; */ - - rr_indexed_data[index].base_cost = delay_normalization_fac; - /* rr_indexed_data[index].base_cost = delay_normalization_fac * - sqrt (1. / rr_indexed_data[index].inv_length); */ - /* rr_indexed_data[index].base_cost = delay_normalization_fac * - (1. + 1. / rr_indexed_data[index].inv_length); */ - } - - /* Save a copy of the base costs -- if dynamic costing is used by the * - * router, the base_cost values will get changed all the time and being * - * able to restore them from a saved version is useful. */ - - for (index = 0; index < num_rr_indexed_data; index++) { - rr_indexed_data[index].saved_base_cost = - rr_indexed_data[index].base_cost; - } -} - -static float get_delay_normalization_fac(int nodes_per_chan, - t_ivec *** L_rr_node_indices) { - - /* Returns the average delay to go 1 CLB distance along a wire. */ - - const int clb_dist = 3; /* Number of CLBs I think the average conn. goes. */ - - int inode, itrack, cost_index; - float Tdel, Tdel_sum, frac_num_seg; - - Tdel_sum = 0.; - - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - inode = get_rr_node_index((nx + 1) / 2, (ny + 1) / 2, CHANX, itrack, - L_rr_node_indices); - cost_index = rr_node[inode].cost_index; - frac_num_seg = clb_dist * rr_indexed_data[cost_index].inv_length; - Tdel = frac_num_seg * rr_indexed_data[cost_index].T_linear - + frac_num_seg * frac_num_seg - * rr_indexed_data[cost_index].T_quadratic; - Tdel_sum += Tdel / (float) clb_dist; - } - - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - inode = get_rr_node_index((nx + 1) / 2, (ny + 1) / 2, CHANY, itrack, - L_rr_node_indices); - cost_index = rr_node[inode].cost_index; - frac_num_seg = clb_dist * rr_indexed_data[cost_index].inv_length; - Tdel = frac_num_seg * rr_indexed_data[cost_index].T_linear - + frac_num_seg * frac_num_seg - * rr_indexed_data[cost_index].T_quadratic; - Tdel_sum += Tdel / (float) clb_dist; - } - - return (Tdel_sum / (2. * nodes_per_chan)); -} - -static float get_average_opin_delay(t_ivec *** L_rr_node_indices, - int nodes_per_chan) { - - /* Returns the average delay from an OPIN to a wire in an adjacent channel. */ - /* RESEARCH TODO: Got to think if this heuristic needs to change for hetero, right now, I'll calculate - * the average delay of non-IO blocks */ - int inode, ipin, iclass, iedge, itype, num_edges, to_switch, to_node, - num_conn; - float Cload, Tdel; - - Tdel = 0.; - num_conn = 0; - for (itype = 0; itype < num_types && &type_descriptors[itype] != IO_TYPE; - itype++) { - for (ipin = 0; ipin < type_descriptors[itype].num_pins; ipin++) { - iclass = type_descriptors[itype].pin_class[ipin]; - if (type_descriptors[itype].class_inf[iclass].type == DRIVER) { /* OPIN */ - inode = get_rr_node_index((nx + 1) / 2, (ny + 1) / 2, OPIN, - ipin, L_rr_node_indices); - num_edges = rr_node[inode].num_edges; - - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = rr_node[inode].edges[iedge]; - to_switch = rr_node[inode].switches[iedge]; - Cload = rr_node[to_node].C; - Tdel += Cload * switch_inf[to_switch].R - + switch_inf[to_switch].Tdel; - num_conn++; - } - } - } - } - - Tdel /= (float) num_conn; - return (Tdel); -} - -static void load_rr_indexed_data_T_values(int index_start, - int num_indices_to_load, t_rr_type rr_type, int nodes_per_chan, - t_ivec *** L_rr_node_indices, const t_segment_inf * segment_inf) { - - /* Loads the average propagation times through segments of each index type * - * for either all CHANX segment types or all CHANY segment types. It does * - * this by looking at all the segments in one channel in the middle of the * - * array and averaging the R and C values of all segments of the same type * - * and using them to compute average delay values for this type of segment. */ - - int itrack, iseg, inode, cost_index, iswitch; - float *C_total, *R_total; /* [0..num_rr_indexed_data - 1] */ - int *num_nodes_of_index; /* [0..num_rr_indexed_data - 1] */ - float Rnode, Cnode, Rsw, Tsw; - - num_nodes_of_index = (int *) my_calloc(num_rr_indexed_data, sizeof(int)); - C_total = (float *) my_calloc(num_rr_indexed_data, sizeof(float)); - R_total = (float *) my_calloc(num_rr_indexed_data, sizeof(float)); - - /* Get average C and R values for all the segments of this type in one * - * channel segment, near the middle of the array. */ - - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - inode = get_rr_node_index((nx + 1) / 2, (ny + 1) / 2, rr_type, itrack, - L_rr_node_indices); - cost_index = rr_node[inode].cost_index; - num_nodes_of_index[cost_index]++; - C_total[cost_index] += rr_node[inode].C; - R_total[cost_index] += rr_node[inode].R; - } - - for (cost_index = index_start; - cost_index < index_start + num_indices_to_load; cost_index++) { - - if (num_nodes_of_index[cost_index] == 0) { /* Segments don't exist. */ - rr_indexed_data[cost_index].T_linear = OPEN; - rr_indexed_data[cost_index].T_quadratic = OPEN; - rr_indexed_data[cost_index].C_load = OPEN; - } else { - Rnode = R_total[cost_index] / num_nodes_of_index[cost_index]; - Cnode = C_total[cost_index] / num_nodes_of_index[cost_index]; - /* mrFPGA: Xifan TANG */ - if (is_isolation) { - Cnode += switch_inf[iswitch].Cin + switch_inf[iswitch].Cout; - } - /* end */ - iseg = rr_indexed_data[cost_index].seg_index; - iswitch = segment_inf[iseg].wire_switch; - Rsw = switch_inf[iswitch].R; - Tsw = switch_inf[iswitch].Tdel; - - if (switch_inf[iswitch].buffered) { - rr_indexed_data[cost_index].T_linear = Tsw + Rsw * Cnode - + 0.5 * Rnode * Cnode; - rr_indexed_data[cost_index].T_quadratic = 0.; - rr_indexed_data[cost_index].C_load = 0.; - } else { /* Pass transistor */ - rr_indexed_data[cost_index].C_load = Cnode; - - /* See Dec. 23, 1997 notes for deriviation of formulae. */ - - rr_indexed_data[cost_index].T_linear = Tsw + 0.5 * Rsw * Cnode; - rr_indexed_data[cost_index].T_quadratic = (Rsw + Rnode) * 0.5 - * Cnode; - /* mrFPGA: Xifan TANG */ - if (is_mrFPGA && is_wire_buffer) { - rr_indexed_data[cost_index].T_linear += wire_buffer_inf.R * Cnode + wire_buffer_inf.C * (Rnode + Rsw) - + sqrt(rr_indexed_data[cost_index].T_quadratic * (wire_buffer_inf.Tdel - + wire_buffer_inf.R * wire_buffer_inf.C)); - rr_indexed_data[cost_index].T_quadratic = 0.; - } - /* end */ - } - } - } - - free(num_nodes_of_index); - free(C_total); - free(R_total); -} diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_indexed_data.h b/vpr7_x2p/vpr/SRC/route/rr_graph_indexed_data.h deleted file mode 100755 index e5c03aa9f..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_indexed_data.h +++ /dev/null @@ -1,3 +0,0 @@ -void alloc_and_load_rr_indexed_data(const t_segment_inf * segment_inf, - int num_segment, t_ivec *** L_rr_node_indices, int nodes_per_chan, - int wire_to_ipin_switch, enum e_base_cost_type base_cost_type); diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_opincb.c b/vpr7_x2p/vpr/SRC/route/rr_graph_opincb.c deleted file mode 100644 index c33b8a4a6..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_opincb.c +++ /dev/null @@ -1,625 +0,0 @@ -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "rr_graph_sbox.h" -#include "check_rr_graph.h" -#include "rr_graph_timing_params.h" -#include "rr_graph_indexed_data.h" -#include "vpr_utils.h" -#include "read_xml_arch_file.h" -#include "ReadOptions.h" -#include "rr_graph_opincb.h" - -/* Subroutines */ -static -int add_rr_graph_one_grid_fast_edge_opin_to_cb(int grid_x, - int grid_y, - t_ivec*** LL_rr_node_indices); - -static -void get_grid_side_pins(int grid_x, int grid_y, - int side, enum e_pin_type pin_type, - t_ivec*** LL_rr_node_indices, - int *num_pins, t_rr_node** *pin_list); - -static -int add_opin_list_ipin_list_fast_edge(int num_opins, t_rr_node** opin_list, - int num_ipins, t_rr_node** ipin_list); - -static -int add_opin_fast_edge_to_ipin(t_rr_node* opin, - t_rr_node* ipin); - -static -int get_ipin_switch_index(t_rr_node* ipin); - -static -void find_rr_nodes_ipin_driver_switch(); - -static -void recover_rr_nodes_ipin_driver_switch(); - -/* Xifan TANG: Create Fast Interconnection between LB OPIN and CB INPUT*/ -/* TOP function */ -int add_rr_graph_fast_edge_opin_to_cb(t_ivec*** LL_rr_node_indices) { - int ix, iy; - int add_edge_counter = 0; - int run_opintocb = 0; - - /* Decide if we run this part */ - - /* For each grid, include I/O*/ - for (ix = 1; ix < (nx+1); ix++) { - for (iy = 1; iy < (ny+1); iy++) { - if ((EMPTY_TYPE != grid[ix][iy].type)&&(TRUE == grid[ix][iy].type->opin_to_cb)) { - run_opintocb = 1; - break; - } - } - if (1 == run_opintocb) { - break; - } - } - - if (0 == run_opintocb) { - return add_edge_counter; - } - - find_rr_nodes_ipin_driver_switch(); - - /* For each grid, include I/O*/ - for (ix = 1; ix < (nx+1); ix++) { - for (iy = 1; iy < (ny+1); iy++) { - add_edge_counter += add_rr_graph_one_grid_fast_edge_opin_to_cb(ix, iy, LL_rr_node_indices); - } - } - - recover_rr_nodes_ipin_driver_switch(); - - return add_edge_counter; -} - -/* For one grid, add fast edge from a LB OPIN to CB*/ -static -int add_rr_graph_one_grid_fast_edge_opin_to_cb(int grid_x, - int grid_y, - t_ivec*** LL_rr_node_indices) { - int opin_side, ipin_side; - boolean early_stop = FALSE; - int num_opins = 0; - t_rr_node** opin_list = NULL; - int num_ipins = 0; - t_rr_node** ipin_list = NULL; - int add_edge_counter = 0; - t_type_ptr type_descriptor = NULL; - - /* Make sure this is a valid grid*/ - assert((-1 < grid_x) && (grid_x < (nx+1))); - assert((-1 < grid_y) && (grid_y < (ny+1))); - - /* Get the type_descriptor and determine if this grid should add edges */ - type_descriptor = grid[grid_x][grid_y].type; - if (NULL == type_descriptor) { - return add_edge_counter; - } else if (FALSE == type_descriptor->opin_to_cb) { - return add_edge_counter; - } - - /* Check each side of this grid, - * determine how many adjacent LB should be taken into account. - */ - for (opin_side = 0; opin_side < 4; opin_side++) { - early_stop = FALSE; - switch(opin_side) { - case TOP: - /* Only I/O on the bottom side of FPGA allows to continue */ - if ((0 == grid_x)||(ny + 1 == grid_y)||(nx + 1 == grid_x)) { - early_stop = TRUE; - } - break; - case RIGHT: - /* Only I/O on the left side of FPGA allows to continue */ - if ((0 == grid_y)||(ny + 1 == grid_y)||(nx + 1 == grid_x)) { - early_stop = TRUE; - } - break; - case BOTTOM: - /* Only I/O on the top side of FPGA allows to continue */ - if ((0 == grid_x)||(0 == grid_y)||(nx + 1 == grid_x)) { - early_stop = TRUE; - } - break; - case LEFT: - /* Only I/O on the right side of FPGA allows to continue */ - if ((0 == grid_x)||(ny + 1 == grid_y)||(0 == grid_y)) { - early_stop = TRUE; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s, [LINE%d]) Invalid opin_side(%d)!\n", - __FILE__, __LINE__, opin_side); - exit(1); - } - /* Decide if we should do something or not */ - if (TRUE == early_stop) { - continue; - } - - /* Find the opins on the opin_side of current grid */ - get_grid_side_pins(grid_x, grid_y, opin_side, DRIVER, LL_rr_node_indices, &num_opins, &opin_list); - if (0 == num_opins) { /* Do nothing if there is no OPIN available */ - continue; - } - - switch(opin_side) { - case TOP: - /* Create fast connection to the grid above*/ - for (ipin_side = 0; ipin_side < 4; ipin_side++) { - /* For the grid on the boundary, we only create connections to the bottom side */ - if (((grid_y + 1) == (ny + 1))&&(BOTTOM != ipin_side)) { - continue; - } - /* We also skip the top side because we believe a IPIN at the top side - * can be swapped to others by using logic equivalence. Which is faster. - */ - if (TOP == ipin_side) { - continue; - } - get_grid_side_pins(grid_x, grid_y+1, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); - /* Create fast edge from the OPINs to IPINs*/ - add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); - /* Free ipin_list */ - num_ipins = 0; - free(ipin_list); - } - /* If this is already the bottom side of FPGA, we skip */ - if (0 == grid_y) { - break; - } - /* Create fast connection to the grid below */ - for (ipin_side = 0; ipin_side < 4; ipin_side++) { - /* For the grid on the boundary, we only create connections to the top side */ - if (((grid_y - 1) == 0)&&(TOP != ipin_side)) { - continue; - } - /* We also skip the bottom side because we believe a IPIN at the bottom side - * can be swapped to others by using logic equivalence. Which is faster. - */ - if (BOTTOM == ipin_side) { - continue; - } - get_grid_side_pins(grid_x, grid_y-1, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); - /* Create fast edge from the OPINs to IPINs*/ - add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); - /* Free ipin_list */ - num_ipins = 0; - free(ipin_list); - } - break; - case RIGHT: - /* Create fast connection to the grid on the right side */ - for (ipin_side = 0; ipin_side < 4; ipin_side++) { - /* For the grid on the boundary, we only create connections to the left side */ - if (((grid_x + 1) == (nx + 1))&&(LEFT != ipin_side)) { - continue; - } - /* We also skip the top side because we believe a IPIN at the top side - * can be swapped to others by using logic equivalence. Which is faster. - */ - if (RIGHT == ipin_side) { - continue; - } - get_grid_side_pins(grid_x+1, grid_y, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); - /* Create fast edge from the OPINs to IPINs*/ - add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); - /* Free ipin_list */ - num_ipins = 0; - free(ipin_list); - } - /* If this is already the left side of FPGA, we skip */ - if (0 == grid_x) { - break; - } - /* Create fast connection to the grid on the left side */ - for (ipin_side = 0; ipin_side < 4; ipin_side++) { - /* For the grid on the boundary, we only create connections to the rigth side */ - if (((grid_x - 1) == 0)&&(RIGHT != ipin_side)) { - continue; - } - /* We also skip the bottom side because we believe a IPIN at the bottom side - * can be swapped to others by using logic equivalence. Which is faster. - */ - if (LEFT == ipin_side) { - continue; - } - get_grid_side_pins(grid_x-1, grid_y, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); - /* Create fast edge from the OPINs to IPINs*/ - add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); - /* Free ipin_list */ - num_ipins = 0; - free(ipin_list); - } - break; - case BOTTOM: - /* Create fast connection to the grid on the bottom side */ - for (ipin_side = 0; ipin_side < 4; ipin_side++) { - /* For the grid on the boundary, we only create connections to the left side */ - if (((grid_y - 1) == 0)&&(TOP != ipin_side)) { - continue; - } - /* We also skip the top side because we believe a IPIN at the bottom side - * can be swapped to others by using logic equivalence. Which is faster. - */ - if (BOTTOM == ipin_side) { - continue; - } - get_grid_side_pins(grid_x, grid_y-1, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); - /* Create fast edge from the OPINs to IPINs*/ - add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); - /* Free ipin_list */ - num_ipins = 0; - free(ipin_list); - } - /* If this is already the left side of FPGA, we skip */ - if ((ny + 1) == grid_y) { - break; - } - /* Create fast connection to the grid on the top side */ - for (ipin_side = 0; ipin_side < 4; ipin_side++) { - /* For the grid on the boundary, we only create connections to the rigth side */ - if (((grid_y + 1) == (ny + 1))&&(BOTTOM != ipin_side)) { - continue; - } - /* We also skip the bottom side because we believe a IPIN at the bottom side - * can be swapped to others by using logic equivalence. Which is faster. - */ - if (TOP == ipin_side) { - continue; - } - if (grid_y + 1 == ny + 1) { - assert(BOTTOM == ipin_side); - } - get_grid_side_pins(grid_x, grid_y+1, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); - /* Create fast edge from the OPINs to IPINs*/ - add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); - /* Free ipin_list */ - num_ipins = 0; - free(ipin_list); - } - break; - case LEFT: - /* Create fast connection to the grid on the left side */ - for (ipin_side = 0; ipin_side < 4; ipin_side++) { - /* For the grid on the boundary, we only create connections to the left side */ - if (((grid_x - 1) == 0)&&(RIGHT != ipin_side)) { - continue; - } - /* We also skip the top side because we believe a IPIN at the top side - * can be swapped to others by using logic equivalence. Which is faster. - */ - if (LEFT == ipin_side) { - continue; - } - get_grid_side_pins(grid_x-1, grid_y, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); - /* Create fast edge from the OPINs to IPINs*/ - add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); - /* Free ipin_list */ - num_ipins = 0; - free(ipin_list); - } - /* If this is already the right side of FPGA, we skip */ - if ((nx + 1) == grid_x) { - break; - } - /* Create fast connection to the grid on the right side */ - for (ipin_side = 0; ipin_side < 4; ipin_side++) { - /* For the grid on the boundary, we only create connections to the right side */ - if (((grid_x + 1) == (nx + 1))&&(LEFT != ipin_side)) { - continue; - } - /* We also skip the bottom side because we believe a IPIN at the bottom side - * can be swapped to others by using logic equivalence. Which is faster. - */ - if (RIGHT == ipin_side) { - continue; - } - get_grid_side_pins(grid_x+1, grid_y, ipin_side, RECEIVER, LL_rr_node_indices, &num_ipins, &ipin_list); - /* Create fast edge from the OPINs to IPINs*/ - add_edge_counter += add_opin_list_ipin_list_fast_edge(num_opins, opin_list, num_ipins, ipin_list); - /* Free ipin_list */ - num_ipins = 0; - free(ipin_list); - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s, [LINE%d]) Invalid opin_side(%d)!\n", - __FILE__, __LINE__, opin_side); - exit(1); - } - /* Free opin_list */ - num_opins = 0; - free(opin_list); - } - - return add_edge_counter; -} - -/* Find all the OPINs at a side of one grid. - * Return num_opins, and opin_list - */ -static -void get_grid_side_pins(int grid_x, int grid_y, - int side, enum e_pin_type pin_type, - t_ivec*** LL_rr_node_indices, - int *num_pins, t_rr_node** *pin_list) { - int ipin, iheight, class_idx, cur_pin, inode; - t_type_ptr type_descriptor = NULL; - t_rr_type pin_rr_type; - - switch (pin_type) { - case DRIVER: - pin_rr_type = OPIN; - break; - case RECEIVER: - pin_rr_type = IPIN; - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s, [LINE%d]) Invalid pin_type(%d)!\n", - __FILE__, __LINE__, pin_type); - exit(1); - } - - /* Initialization */ - (*num_pins) = 0; - (*pin_list) = NULL; - /* (*pin_class_list) = NULL; */ - - /* Make sure this is a valid grid*/ - assert((-1 < grid_x) && (grid_x < (nx+2))); - assert((-1 < grid_y) && (grid_y < (ny+2))); - - assert((-1 < side) && (side < 4)); - - type_descriptor = grid[grid_x][grid_y].type; - - /* Kick out corner cases */ - switch(side) { - case TOP: - /* If this is the most top grid, return*/ - if ((ny+1 == grid_y)||(0 == grid_x)||(nx + 1 == grid_x)) { - return; - } - break; - case RIGHT: - /* If this is the most right grid, return*/ - if ((nx + 1 == grid_x)||(ny + 1 == grid_y)||(0 == grid_y)) { - return; - } - break; - case BOTTOM: - /* If this is the most bottom grid, return*/ - if ((0 == grid_y)||(0 == grid_x)||(nx + 1 == grid_x)) { - return; - } - break; - case LEFT: - /* If this is the most left grid, return*/ - if ((0 == grid_x)||(0 == grid_y)||(ny + 1 == grid_y)) { - return; - } - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "(File: %s, [LINE%d]) Invalid side(%d)!\n", - __FILE__, __LINE__, side); - exit(1); - } - - /* Count num_opins */ - for (iheight = 0; iheight < type_descriptor->height; iheight++) { - for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { - /* Check if this is an OPIN at the side we want*/ - class_idx = type_descriptor->pin_class[ipin]; - assert((-1 < class_idx) && (class_idx < type_descriptor->num_class)); - if ((1 == type_descriptor->pinloc[iheight][side][ipin]) - &&(pin_type == type_descriptor->class_inf[class_idx].type) - &&(TRUE == type_descriptor->opin_to_cb)) { - (*num_pins)++; - } - } - } - - /* Alloc array */ - cur_pin = 0; - (*pin_list) = (t_rr_node**)my_malloc((*num_pins)*sizeof(t_rr_node*)); - /* (*pin_class_list) = (int*)my_malloc((*num_pins)*sizeof(int)); */ - - /* Fill array */ - for (iheight = 0; iheight < type_descriptor->height; iheight++) { - for (ipin = 0; ipin < type_descriptor->num_pins; ipin++) { - /* Check if this is an OPIN at the side we want*/ - class_idx = type_descriptor->pin_class[ipin]; - assert((-1 < class_idx) && (class_idx < type_descriptor->num_class)); - if ((1 == type_descriptor->pinloc[iheight][side][ipin]) - &&(pin_type == type_descriptor->class_inf[class_idx].type) - &&(TRUE == type_descriptor->opin_to_cb)) { - inode = get_rr_node_index(grid_x, grid_y, pin_rr_type, ipin, LL_rr_node_indices); - (*pin_list)[cur_pin] = &rr_node[inode]; - /* (*pin_class_list)[cur_pin] = class_idx; */ - cur_pin++; - } - } - } - assert(cur_pin == (*num_pins)); - - return; -} - -/* We have one list of OPIN, and one list of IPIN, - * decide which two rr_nodes should have a fast edge - */ -static -int add_opin_list_ipin_list_fast_edge(int num_opins, t_rr_node** opin_list, - int num_ipins, t_rr_node** ipin_list) { - int ipin, iedge, to_node, jpin; - int num_ipin_sink = 0; - t_linked_int* ipin_sink_head = NULL; - int* ipin_sink_index = (int*)my_malloc(sizeof(int)*num_ipins); - int add_edge_counter = 0; - - if (0 == num_opins) { - assert(NULL == opin_list); - return add_edge_counter; - } - - if (0 == num_ipins) { - assert(NULL == ipin_list); - return add_edge_counter; - } - - /* Count the number of common source of these ipin */ - for (ipin = 0; ipin < num_ipins; ipin++) { - ipin_sink_index[ipin] = OPEN; - assert(IPIN == ipin_list[ipin]->type); - for (iedge = 0; iedge < ipin_list[ipin]->num_edges; iedge++) { - to_node = ipin_list[ipin]->edges[iedge]; - if (SINK == rr_node[to_node].type) { - /* Search if the source exists in the list */ - if (NULL == search_in_int_list(ipin_sink_head, to_node)) { - /* Do not exist, add one */ - ipin_sink_head = insert_node_to_int_list(ipin_sink_head, to_node); - /* Update counter */ - num_ipin_sink++; - /* Update the index list */ - ipin_sink_index[ipin] = to_node; - } - } - } - } - - /* For each OPIN node, create a edge to each ipin whose ipin_src is different */ - for (ipin = 0; ipin < num_opins; ipin++) { - for (jpin = 0; jpin < num_ipins; jpin++) { - //if (OPEN != ipin_sink_index[jpin]) { - /* Find its ipin source node*/ - //ipin_sink_list_node = search_in_int_list(ipin_sink_head, ipin_sink_index[jpin]); - //if (NULL != ipin_sink_list_node) { - /* Add a fast edge */ - add_edge_counter += add_opin_fast_edge_to_ipin(opin_list[ipin], ipin_list[jpin]); - /* Make the sink list node invalid */ - // ipin_sink_list_node->data = OPEN; - // } - //} - } - } - - /* Free */ - free_int_list(&ipin_sink_head); - - return add_edge_counter; -} - -/* Add an edge from opin to ipin, use the switch of ipin*/ -static -int add_opin_fast_edge_to_ipin(t_rr_node* opin, - t_rr_node* ipin) { - int ipin_switch_index = OPEN; - int iedge, to_node; - - /* Make sure we have an OPIN and an IPIN*/ - assert(OPIN == opin->type); - assert(IPIN == ipin->type); - - /* Get the switch index of ipin, and check it is valid */ - ipin_switch_index = get_ipin_switch_index(ipin); - if (OPEN == ipin_switch_index) { - return 0; - } - - /* Check if OPIN has a fan-out to IPIN already*/ - for (iedge = 0; iedge < opin->num_edges; iedge++) { - to_node = opin->edges[iedge]; - if ((IPIN == rr_node[to_node].type)&&(ipin == &rr_node[to_node])) { - vpr_printf(TIO_MESSAGE_WARNING, "(File:%s,[LINE%d])OPIN rr_node[%d] has an fan-out to IPIN rr_node[%d]. Fast edge will not be created.\n", __FILE__, __LINE__, opin-rr_node, ipin-rr_node); - return 0; - } - } - - /* create a fast edge */ - /* 1. re-alloc a edge list switch list */ - opin->num_edges++; - opin->edges = (int*)my_realloc(opin->edges, opin->num_edges*sizeof(int)); - opin->switches = (short*)my_realloc(opin->switches, opin->num_edges*sizeof(short)); - /* 2. Update edge and switch info */ - opin->edges[opin->num_edges-1] = ipin - rr_node; - opin->switches[opin->num_edges-1] = ipin_switch_index; - /* 3. Increase the fan-in of IPIN */ - ipin->fan_in++; - /* Finish*/ - - return 1; -} - -/* This is not efficent, should be improved by using LL_rr_node_indices*/ -static -int get_ipin_switch_index(t_rr_node* ipin) { - return ipin->driver_switch; -} - -static -void find_rr_nodes_ipin_driver_switch() { - int inode, jnode, iedge, to_node, fan_in_counter; - int ipin_switch_index = OPEN; - - vpr_printf(TIO_MESSAGE_INFO, "Building rr_node driver switches...\n"); - - for (inode = 0; inode < num_rr_nodes; inode++) { - if (IPIN != rr_node[inode].type) { - continue; - } - /* Create a counter, check the correctness*/ - fan_in_counter = 0; - ipin_switch_index = OPEN; - for (jnode = 0; jnode < num_rr_nodes; jnode++) { - for (iedge = 0; iedge < rr_node[jnode].num_edges; iedge++) { - to_node = rr_node[jnode].edges[iedge]; - if (inode == to_node) { - fan_in_counter++; - if (OPEN == ipin_switch_index) { - ipin_switch_index = rr_node[jnode].switches[iedge]; - } else { - assert(ipin_switch_index == rr_node[jnode].switches[iedge]); - } - } - } - } - assert(fan_in_counter == rr_node[inode].fan_in); - if (0 != fan_in_counter) { - assert(OPEN != ipin_switch_index); - } - rr_node[inode].driver_switch = ipin_switch_index; - } - - return; -} - -static -void recover_rr_nodes_ipin_driver_switch() { - int inode; - - vpr_printf(TIO_MESSAGE_INFO, "Recovering rr_node driver switches...\n"); - - for (inode = 0; inode < num_rr_nodes; inode++) { - if (IPIN == rr_node[inode].type) { - rr_node[inode].driver_switch = OPEN; - } - } - return; -} - diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_opincb.h b/vpr7_x2p/vpr/SRC/route/rr_graph_opincb.h deleted file mode 100644 index df0dec4d6..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_opincb.h +++ /dev/null @@ -1,2 +0,0 @@ -/* Top function */ -int add_rr_graph_fast_edge_opin_to_cb(t_ivec*** LL_rr_node_indices); diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_sbox.c b/vpr7_x2p/vpr/SRC/route/rr_graph_sbox.c deleted file mode 100755 index 0b962a2d5..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_sbox.c +++ /dev/null @@ -1,228 +0,0 @@ -#include -#include "util.h" -#include "vpr_types.h" -#include "rr_graph_sbox.h" -#include "rr_graph_util.h" -#include "ReadOptions.h" - -/* Switch box: * - * TOP (CHANY) * - * | | | | | | * - * +-----------+ * - * --| |-- * - * --| |-- * - * LEFT --| |-- RIGHT * - * (CHANX)--| |--(CHANX) * - * --| |-- * - * --| |-- * - * +-----------+ * - * | | | | | | * - * BOTTOM (CHANY) */ - -/* [0..3][0..3][0..nodes_per_chan-1]. Structure below is indexed as: * - * [from_side][to_side][from_track]. That yields an integer vector (ivec) * - * of the tracks to which from_track connects in the proper to_location. * - * For simple switch boxes this is overkill, but it will allow complicated * - * switch boxes with Fs > 3, etc. without trouble. */ - -int get_simple_switch_block_track(INP enum e_side from_side, - INP enum e_side to_side, INP int from_track, - INP enum e_switch_block_type switch_block_type, INP int nodes_per_chan); - -/* Allocates and loads the switch_block_conn data structure. This structure * - * lists which tracks connect to which at each switch block. This is for - * bidir. */ -struct s_ivec *** -alloc_and_load_switch_block_conn(INP int nodes_per_chan, - INP enum e_switch_block_type switch_block_type, INP int Fs) { - enum e_side from_side, to_side; - int from_track; - struct s_ivec ***switch_block_conn = NULL; - - /* Currently Fs must be 3 since each track maps once to each other side */ - assert(3 == Fs); - - switch_block_conn = (struct s_ivec ***) alloc_matrix3(0, 3, 0, 3, 0, - (nodes_per_chan - 1), sizeof(struct s_ivec)); - - for (from_side = (enum e_side)0; from_side < 4; from_side = (enum e_side)(from_side + 1)) { - for (to_side = (enum e_side)0; to_side < 4; to_side = (enum e_side)(to_side + 1)) { - for (from_track = 0; from_track < nodes_per_chan; from_track++) { - if (from_side != to_side) { - switch_block_conn[from_side][to_side][from_track].nelem = 1; - switch_block_conn[from_side][to_side][from_track].list = - (int *) my_malloc(sizeof(int)); - - switch_block_conn[from_side][to_side][from_track].list[0] = - get_simple_switch_block_track(from_side, to_side, - from_track, switch_block_type, - nodes_per_chan); - } else { /* from_side == to_side -> no connection. */ - switch_block_conn[from_side][to_side][from_track].nelem = 0; - switch_block_conn[from_side][to_side][from_track].list = - NULL; - } - } - } - } - - if (getEchoEnabled()) { - int i, j, k, l; - FILE *out; - - out = my_fopen("switch_block_conn.echo", "w", 0); - for (l = 0; l < 4; ++l) { - for (k = 0; k < 4; ++k) { - fprintf(out, "Side %d to %d\n", l, k); - for (j = 0; j < nodes_per_chan; ++j) { - fprintf(out, "%d: ", j); - for (i = 0; i < switch_block_conn[l][k][j].nelem; ++i) { - fprintf(out, "%d ", switch_block_conn[l][k][j].list[i]); - } - fprintf(out, "\n"); - } - fprintf(out, "\n"); - } - } - fclose(out); - } - return switch_block_conn; -} - -void free_switch_block_conn(struct s_ivec ***switch_block_conn, - int nodes_per_chan) { - /* Frees the switch_block_conn data structure. */ - - free_ivec_matrix3(switch_block_conn, 0, 3, 0, 3, 0, nodes_per_chan - 1); -} - -#define SBOX_ERROR -1 - -/* This routine permutes the track number to connect for topologies - * SUBSET, UNIVERSAL, and WILTON. I added FULL (for fully flexible topology) - * but the returned value is simply a dummy, since we don't need to permute - * what connections to make for FULL (connect to EVERYTHING) */ -int get_simple_switch_block_track(INP enum e_side from_side, - INP enum e_side to_side, INP int from_track, - INP enum e_switch_block_type switch_block_type, INP int nodes_per_chan) { - - /* This routine returns the track number to which the from_track should * - * connect. It supports three simple, Fs = 3, switch blocks. */ - - int to_track; - - to_track = SBOX_ERROR; /* Can check to see if it's not set later. */ - - if (switch_block_type == SUBSET) { /* NB: Global routing uses SUBSET too */ - to_track = from_track; - } - - /* See S. Wilton Phd thesis, U of T, 1996 p. 103 for details on following. */ - - else if (switch_block_type == WILTON) { - - if (from_side == LEFT) { - - if (to_side == RIGHT) { /* CHANX to CHANX */ - to_track = from_track; - } else if (to_side == TOP) { /* from CHANX to CHANY */ - to_track = (nodes_per_chan - from_track) % nodes_per_chan; - } else if (to_side == BOTTOM) { - to_track = (nodes_per_chan + from_track - 1) % nodes_per_chan; - } - } - - else if (from_side == RIGHT) { - if (to_side == LEFT) { /* CHANX to CHANX */ - to_track = from_track; - } else if (to_side == TOP) { /* from CHANX to CHANY */ - to_track = (nodes_per_chan + from_track - 1) % nodes_per_chan; - } else if (to_side == BOTTOM) { - to_track = (2 * nodes_per_chan - 2 - from_track) - % nodes_per_chan; - } - } - - else if (from_side == BOTTOM) { - if (to_side == TOP) { /* CHANY to CHANY */ - to_track = from_track; - } else if (to_side == LEFT) { /* from CHANY to CHANX */ - to_track = (from_track + 1) % nodes_per_chan; - } else if (to_side == RIGHT) { - to_track = (2 * nodes_per_chan - 2 - from_track) - % nodes_per_chan; - } - } - - else if (from_side == TOP) { - if (to_side == BOTTOM) { /* CHANY to CHANY */ - to_track = from_track; - } else if (to_side == LEFT) { /* from CHANY to CHANX */ - to_track = (nodes_per_chan - from_track) % nodes_per_chan; - } else if (to_side == RIGHT) { - to_track = (from_track + 1) % nodes_per_chan; - } - } - - } - /* End switch_block_type == WILTON case. */ - else if (switch_block_type == UNIVERSAL) { - - if (from_side == LEFT) { - - if (to_side == RIGHT) { /* CHANX to CHANX */ - to_track = from_track; - } else if (to_side == TOP) { /* from CHANX to CHANY */ - to_track = nodes_per_chan - 1 - from_track; - } else if (to_side == BOTTOM) { - to_track = from_track; - } - } - - else if (from_side == RIGHT) { - if (to_side == LEFT) { /* CHANX to CHANX */ - to_track = from_track; - } else if (to_side == TOP) { /* from CHANX to CHANY */ - to_track = from_track; - } else if (to_side == BOTTOM) { - to_track = nodes_per_chan - 1 - from_track; - } - } - - else if (from_side == BOTTOM) { - if (to_side == TOP) { /* CHANY to CHANY */ - to_track = from_track; - } else if (to_side == LEFT) { /* from CHANY to CHANX */ - to_track = from_track; - } else if (to_side == RIGHT) { - to_track = nodes_per_chan - 1 - from_track; - } - } - - else if (from_side == TOP) { - if (to_side == BOTTOM) { /* CHANY to CHANY */ - to_track = from_track; - } else if (to_side == LEFT) { /* from CHANY to CHANX */ - to_track = nodes_per_chan - 1 - from_track; - } else if (to_side == RIGHT) { - to_track = from_track; - } - } - } - - /* End switch_block_type == UNIVERSAL case. */ - /* UDSD Modification by WMF Begin */ - if (switch_block_type == FULL) { /* Just a placeholder. No meaning in reality */ - to_track = from_track; - } - /* UDSD Modification by WMF End */ - - if (to_track == SBOX_ERROR) { - vpr_printf(TIO_MESSAGE_ERROR, "in get_simple_switch_block_track.\n"); - vpr_printf(TIO_MESSAGE_ERROR, "\tUnexpected connection from_side: %d to_side: %d switch_block_type: %d.\n", - from_side, to_side, switch_block_type); - exit(1); - } - - return (to_track); -} diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_sbox.h b/vpr7_x2p/vpr/SRC/route/rr_graph_sbox.h deleted file mode 100755 index 23b8d5964..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_sbox.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef RR_GRAPH_SBOX_H -#define RR_GRAPH_SBOX_H - -struct s_ivec get_switch_box_tracks(INP int from_i, - INP int from_j, - INP int from_track, - INP t_rr_type from_type, - INP int to_i, - INP int to_j, - INP t_rr_type to_type, - INP struct s_ivec ***switch_block_conn); - -void free_switch_block_conn(struct s_ivec ***switch_block_conn, - int nodes_per_chan); - -struct s_ivec ***alloc_and_load_switch_block_conn(int nodes_per_chan, - enum e_switch_block_type switch_block_type, int Fs); - -int get_simple_switch_block_track(enum e_side from_side, enum e_side to_side, - int from_track, enum e_switch_block_type switch_block_type, - int nodes_per_chan); - -#endif - diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_swseg.c b/vpr7_x2p/vpr/SRC/route/rr_graph_swseg.c deleted file mode 100644 index d923aa14b..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_swseg.c +++ /dev/null @@ -1,704 +0,0 @@ -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph_util.h" -#include "rr_graph.h" -#include "rr_graph2.h" -#include "rr_graph_sbox.h" -#include "check_rr_graph.h" -#include "rr_graph_timing_params.h" -#include "rr_graph_indexed_data.h" -#include "vpr_utils.h" -#include "read_xml_arch_file.h" -#include "ReadOptions.h" -#include "rr_graph_swseg.h" - -/* Switch Segment Pattern Support - * Xifan TANG, - * EPFL-IC-ISIM-LSI - * July 2014 - */ -enum ret_track_swseg_pattern { - RET_SWSEG_TRACK_DIR_UNMATCH, - RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN, - RET_SWSEG_TRACK_APPLIED -}; - -/** Basic idea: - * Add unbuffered multiplexers(switches) to the length-n segments - * For example: - * clb clb clb clb - * sb ------sb-------sb--------sb--------sb - * BUF BUF BUF BUF BUF - * The above is a length-1 wire. All the multiplexers in thes segments are buffered. - * In this work, we adapt the segments to the following story: - * clb clb clb clb - * sb ------sb-------sb--------sb--------sb - * BUF UNBUF BUF UNBUF BUF - * - * This is called a pattern. The length of the pattern is 2. - * Of cource, we can generalize it to length-n wire and define a pattern - * Pattern: 0 1 1 1 0, Segment length: 1, Pattern length 5 - * The results are as follows: - * clb clb clb clb - * sb ------sb-------sb--------sb--------sb - * BUF UNBUF UNBUF UNBUF BUF - */ - -/** We check the routing tracks one by one to apply the pattern. - * Start from the source of coordinate systems - */ - - -/* The numbering relation between the channels and clbs is: * - * * - * | IO | chan_ | CLB | chan_ | CLB | * - * |grid[0][2] | y[0][2] |grid[1][2] | y[1][2] | grid[2][2]| * - * +-----------+ +-----------+ +-----------+ * - * } capacity in * - * No channel chan_x[1][1] chan_x[2][1] } chan_width * - * } _x[1] * - * +-----------+ +-----------+ +-----------+ * - * | | chan_ | | chan_ | | * - * | IO | y[0][1] | CLB | y[1][1] | CLB | * - * |grid[0][1] | |grid[1][1] | |grid[2][1] | * - * | | | | | | * - * +-----------+ +-----------+ +-----------+ * - * } capacity in * - * chan_x[1][0] chan_x[2][0] } chan_width * - * } _x[0] * - * +-----------+ +-----------+ * - * No | | No | | * - * Channel | IO | Channel | IO | * - * |grid[1][0] | |grid[2][0] | * - * | | | | * - * +-----------+ +-----------+ * - * * - * {=======} {=======} * - * Capacity in Capacity in * - * chan_width_y[0] chan_width_y[1] * - * */ - -/**************************************************************************** - * =========chan_x [ix][iy]========= * - * || *---------------* || * - * || | | || * - * || | | || * - * chan_y | CLB | chan_y * - * [ix-1][iy] | [ix][iy] | [ix][iy] * - * || | | || * - * || | | || * - * || *---------------* || * - * ========chan_x [ix][iy-1]======== * - **************************************************************************** - * Directionality * - * /|\ * - * | INC * - * | * - * <--------- ----------> * - * DEC | INC * - * | * - * | DEC * - * \|/ * - **************************************************************************** - */ -/* We spot a routing track in channel (inx,iny). And start check its segment - * length. When we got the segment length, then apply the pattern to this routing track. - * And move on to the next. - * So, we would check the channels from [0][0] to [0][ny], [nx][0], [nx][ny] - */ - -/*****Subroutine Declaration*****/ -static -int init_chan_seg_detail_params(INP char* chan_type, - INP int curx, - INP int cury, - INP int nx, // Width of FPGA - INP int ny, // Height of FPGA - INP t_seg_details* seg_details_x, - INP t_seg_details* seg_details_y, - OUTP int* seg_num, - OUTP int* chan_num, - //OUTP short* direction, - OUTP t_seg_details* seg_details, - OUTP int* max_len); - -static t_swseg_pattern_inf* -search_swseg_pattern_seg_len(INP int num_swseg_pattern, - INP t_swseg_pattern_inf* swseg_patterns, - INP int seg_len); - -static enum ret_track_swseg_pattern - apply_swseg_pattern_chanx_track(INP int track_id, - INP int chanx_y, - INP int start_x, - INP int end_x, - INP int max_x, - INP int max_y, - INP short direction, - INP int num_swseg_pattern, - INP t_swseg_pattern_inf* swseg_patterns, - INP t_ivec*** L_rr_node_indices, - INP t_seg_details* seg_details_x, - INP t_seg_details* seg_details_y, - INP int* num_changed_chanx); - -static enum ret_track_swseg_pattern - apply_swseg_pattern_chany_track(INP int track_id, - INP int chany_x, - INP int start_y, - INP int end_y, - INP int max_x, - INP int max_y, - INP short direction, - INP int num_swseg_pattern, - INP t_swseg_pattern_inf* swseg_patterns, - INP t_ivec*** L_rr_node_indices, - INP t_seg_details* seg_details_x, - INP t_seg_details* seg_details_y, - INP int* num_changed_chany); - -static int swseg_pattern_change_switch_type(int inode, - t_rr_type chan_type, - t_swseg_pattern_inf swseg_pattern, - int* num_unbuf_mux); - -/*Update the driver_switch of all rr_nodes*/ -void update_rr_nodes_driver_switch(enum e_directionality directionality); - -static boolean* rotate_shift_swseg_pattern(int pattern_length, - boolean* pattern, - int rotate_shift_length); - -/*Start : The top function*/ -int add_rr_graph_switch_segment_pattern(enum e_directionality directionality, - INP int nodes_per_chan, - INP int num_swseg_pattern, - INP t_swseg_pattern_inf* swseg_patterns, - INP t_ivec*** L_rr_node_indices, - INP t_seg_details* seg_details_x, - INP t_seg_details* seg_details_y) { - int ix, iy, itrack; - int num_changed_chanx, num_changed_chany; - t_seg_details* seg_details; - - /*Initialization*/ - seg_details = NULL; - num_changed_chanx = 0; - num_changed_chany = 0; - - // Initialization - update_rr_nodes_driver_switch(directionality); - /* CHAN_X segments - * We start from chan_x [1...nx-1][0] to chan_x [1...nx-1][ny-1]. - * They are the start points of routing tracks in CHANX - */ - /* Ensure we have channel width > 0*/ - assert(nodes_per_chan > 0); - seg_details = seg_details_x; - for (iy = 0; iy < (ny + 1); iy++) { - /* Check each routing track in a channel*/ - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - if (INC_DIRECTION == seg_details[itrack].direction) { - apply_swseg_pattern_chanx_track(itrack, iy, 0, nx, nx, ny, INC_DIRECTION, - num_swseg_pattern, swseg_patterns, L_rr_node_indices, seg_details_x, seg_details_y, - &num_changed_chanx); - } else if (DEC_DIRECTION == seg_details[itrack].direction) { - apply_swseg_pattern_chanx_track(itrack, iy, nx, 0, nx, ny, DEC_DIRECTION, - num_swseg_pattern, swseg_patterns, L_rr_node_indices, seg_details_x, seg_details_y, - &num_changed_chanx); - } - } // Time to change another channel§ - } - /* CHAN_Y segments - * We start from chan_y [0][1...ny-1] to chan_y [nx-1][1...ny-1]. - * They are the start points of routing tracks in CHANX - */ - seg_details = seg_details_y; - for (ix = 0; ix < (nx + 1); ix++) { - /* Check each routing track in a channel*/ - for (itrack = 0; itrack < nodes_per_chan; itrack++) { - if (INC_DIRECTION == seg_details[itrack].direction) { - apply_swseg_pattern_chany_track(itrack, ix, 0, ny, nx, ny, INC_DIRECTION, - num_swseg_pattern, swseg_patterns, L_rr_node_indices, seg_details_x, seg_details_y, - &num_changed_chany); - } else if (DEC_DIRECTION == seg_details[itrack].direction) { - apply_swseg_pattern_chany_track(itrack, ix, ny, 0, nx, ny, DEC_DIRECTION, - num_swseg_pattern, swseg_patterns, L_rr_node_indices, seg_details_x, seg_details_y, - &num_changed_chany); - } - } // Time to change another channel§ - } - - // Show Statistics - vpr_printf(TIO_MESSAGE_INFO,"Switch Segment Pattern applied to %d Channel X.\n",num_changed_chanx); - vpr_printf(TIO_MESSAGE_INFO,"Switch Segment Pattern applied to %d Channel Y.\n",num_changed_chany); - - return 1; // Success -} - -// This part copied from function: view_mux_size_distribution -/* Determine seg_num, chan_num, direction, seg_details, max_len - * according to the side of FPGA - */ -static int init_chan_seg_detail_params(INP char* chan_type, - INP int curx, - INP int cury, - INP int max_x, // Width of FPGA - INP int max_y, // Height of FPGA - INP t_seg_details* seg_details_x, - INP t_seg_details* seg_details_y, - OUTP int* seg_num, - OUTP int* chan_num, - //OUTP short* direction, - OUTP t_seg_details* seg_details, - OUTP int* max_len) { - /*Initialization*/ - (*seg_num) = 0; - (*chan_num) = 0; - //(*direction) = 0; - seg_details = NULL; - (*max_len) = 0; - - if (0 == strcmp(chan_type,"chanx_inc")) { - (*seg_num) = curx; - (*chan_num) = cury; - //(*direction) = INC_DIRECTION; - seg_details = seg_details_x; - (*max_len) = max_x; - } else if (0 == strcmp(chan_type,"chanx_dec")) { - (*seg_num) = curx; - (*chan_num) = cury; - //(*direction) = DEC_DIRECTION; - seg_details = seg_details_x; - (*max_len) = max_x; - } else if (0 == strcmp(chan_type,"chany_inc")) { - (*seg_num) = cury; - (*chan_num) = curx; - //(*direction) = INC_DIRECTION; - seg_details = seg_details_y; - (*max_len) = max_y; - } else if (0 == strcmp(chan_type,"chany_dec")) { - (*seg_num) = cury; - (*chan_num) = curx; - //(*direction) = DEC_DIRECTION; - seg_details = seg_details_y; - (*max_len) = max_y; - } else { - vpr_printf(TIO_MESSAGE_ERROR, "Input channel type: %s. Expect [chanx_inc|chanx_dec|chany_inc|chany_dec].\n",chan_type); - exit(1); - } - return 1; -} - -/** Select a pattern according to the segment length. - * Return NULL if nothing found - */ -static -t_swseg_pattern_inf* search_swseg_pattern_seg_len(INP int num_swseg_pattern, - INP t_swseg_pattern_inf* swseg_patterns, - INP int seg_len) { - int ipattern; - t_swseg_pattern_inf* ret = NULL; - - for (ipattern = 0; ipattern < num_swseg_pattern; ipattern++) { - if (seg_len == swseg_patterns[ipattern].seg_length) { - ret = &swseg_patterns[ipattern]; - } - } - return ret; -} - -/** Apply patterns to all the segments of a track in a chanx - */ -static enum ret_track_swseg_pattern - apply_swseg_pattern_chanx_track(INP int track_id, - INP int chanx_y, - INP int start_x, - INP int end_x, - INP int max_x, - INP int max_y, - INP short direction, - INP int num_swseg_pattern, - INP t_swseg_pattern_inf* swseg_patterns, - INP t_ivec*** L_rr_node_indices, - INP t_seg_details* seg_details_x, - INP t_seg_details* seg_details_y, - INP int* num_changed_chanx) { - int ix, start, end, seg_len; - int seg_num, chan_num, max_len, inode; - t_seg_details* seg_details; - t_swseg_pattern_inf* select_swseg_pattern; - int swseg_offset; - boolean* rotated_pattern; - - /*Initialization*/ - seg_len = 0; - seg_details = seg_details_x; - seg_num = 0; - chan_num = 0; - max_len = 0; - select_swseg_pattern = NULL; - swseg_offset = 0; - rotated_pattern = NULL; - - /* Check directions and ranges*/ - assert((INC_DIRECTION == direction)||(DEC_DIRECTION == direction)); - if (INC_DIRECTION == direction) { - assert((!(start_x < 0))&&(!(end_x > max_x))&&(start_x < end_x)); - } else { - assert((!(end_x < 0))&&(!(start_x > max_x))&&(start_x > end_x)&&(DEC_DIRECTION == direction)); - } - - // Check if the track direction matches - if (direction != seg_details[track_id].direction) { - return RET_SWSEG_TRACK_DIR_UNMATCH; // Direction does not match. Ignore the track - } - // Direction match, try to apply the Switch Segment Pattern - if (INC_DIRECTION == direction) { - for (ix = start_x; ix < (end_x + 1); ix++) { - init_chan_seg_detail_params("chanx_inc", ix, chanx_y, max_x, max_y, seg_details_x, seg_details_y, /* INPUT list */ - &seg_num, &chan_num, seg_details, &max_len); /* OUTPUT list */ - /* Get the start point and end point of the segment*/ - start = get_seg_start(seg_details, track_id, chan_num, seg_num); - end = get_seg_end(seg_details, track_id, start, chan_num, max_len); - assert((start > 0)||(0 == start)); - assert((end > 0)||(0 == end)); - /* Get the segment length*/ - seg_len = end - start + 1; - /* Search a pattern*/ - select_swseg_pattern = search_swseg_pattern_seg_len(num_swseg_pattern, swseg_patterns, seg_len); - /* Nothing found, continue to the next track*/ - if (NULL == select_swseg_pattern) { - return RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN; // Do not need to apply any pattern - } - /* Rotate it*/ - rotated_pattern = rotate_shift_swseg_pattern(select_swseg_pattern->pattern_length,select_swseg_pattern->patterns,chanx_y); - /* Check it the segment starts here*/ - if ((start == seg_num)&&(direction == INC_DIRECTION)) { - /* Get the corresponding rr_node index of CHANX MUX*/ - inode = get_rr_node_index(seg_num, chan_num, CHANX, track_id, L_rr_node_indices); - /* Check if we need to change the switch to a unbuffered one*/ - if (TRUE == rotated_pattern[swseg_offset]) { - swseg_pattern_change_switch_type(inode,CHANX,(*select_swseg_pattern), num_changed_chanx); - } - /* Update the swseg_offset*/ - swseg_offset++; - if ((swseg_offset > select_swseg_pattern->pattern_length) - ||(swseg_offset == select_swseg_pattern->pattern_length)) { - swseg_offset = 0; - } - } - if ((rotated_pattern != NULL)&&(rotated_pattern != select_swseg_pattern->patterns)) { - free(rotated_pattern); - } - } - } else if (DEC_DIRECTION == direction) { - for (ix = start_x; ix > (end_x - 1); ix--) { - init_chan_seg_detail_params("chanx_dec", ix, chanx_y, max_x, max_y, seg_details_x, seg_details_y, /* INPUT list */ - &seg_num, &chan_num, seg_details, &max_len); /* OUTPUT list */ - /* Get the start point and end point of the segment*/ - start = get_seg_start(seg_details, track_id, chan_num, seg_num); - end = get_seg_end(seg_details, track_id, start, chan_num, max_len); - assert((start > 0)||(0 == start)); - assert((end > 0)||(0 == end)); - /* Get the segment length*/ - seg_len = end - start + 1; - /* Search a pattern*/ - select_swseg_pattern = search_swseg_pattern_seg_len(num_swseg_pattern, swseg_patterns, seg_len); - /* Nothing found, continue to the next track*/ - if (NULL == select_swseg_pattern) { - return RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN; // Do not need to apply any pattern - } - /* Rotate it*/ - rotated_pattern = rotate_shift_swseg_pattern(select_swseg_pattern->pattern_length,select_swseg_pattern->patterns,chanx_y); - /* Check it the segment starts here*/ - if ((end == seg_num)&&(direction == DEC_DIRECTION)) { - /* Get the corresponding rr_node index of CHANX MUX*/ - inode = get_rr_node_index(seg_num, chan_num, CHANX, track_id, L_rr_node_indices); - /* Check if we need to change the switch to a unbuffered one*/ - if (TRUE == rotated_pattern[swseg_offset]) { - swseg_pattern_change_switch_type(inode,CHANX,(*select_swseg_pattern), num_changed_chanx); - } - /* Update the swseg_offset*/ - swseg_offset++; - if ((swseg_offset > select_swseg_pattern->pattern_length) - ||(swseg_offset == select_swseg_pattern->pattern_length)) { - swseg_offset = 0; - } - } - if ((rotated_pattern != NULL)&&(rotated_pattern != select_swseg_pattern->patterns)) { - free(rotated_pattern); - } - } - } - - return RET_SWSEG_TRACK_APPLIED; -} - -/** Apply patterns to all the segments of a track in a chany - */ -static enum ret_track_swseg_pattern - apply_swseg_pattern_chany_track(INP int track_id, - INP int chany_x, - INP int start_y, - INP int end_y, - INP int max_x, - INP int max_y, - INP short direction, - INP int num_swseg_pattern, - INP t_swseg_pattern_inf* swseg_patterns, - INP t_ivec*** L_rr_node_indices, - INP t_seg_details* seg_details_x, - INP t_seg_details* seg_details_y, - INP int* num_changed_chany) { - int iy, start, end, seg_len; - int seg_num, chan_num, max_len, inode; - t_seg_details* seg_details; - t_swseg_pattern_inf* select_swseg_pattern; - int swseg_offset; - boolean* rotated_pattern= NULL; - - /*Initialization*/ - seg_len = 0; - seg_details = seg_details_y; - seg_num = 0; - chan_num = 0; - max_len = 0; - select_swseg_pattern = NULL; - swseg_offset = 0; - - /* Check directions and ranges*/ - assert((INC_DIRECTION == direction)||(DEC_DIRECTION == direction)); - if (INC_DIRECTION == direction) { - assert((!(start_y < 0))&&(!(end_y > max_y))&&(start_y < end_y)); - } else { - assert((!(end_y < 0))&&(!(start_y > max_y))&&(start_y > end_y)&&(DEC_DIRECTION == direction)); - } - - // Check if the track direction matches - if (direction != seg_details[track_id].direction) { - return RET_SWSEG_TRACK_DIR_UNMATCH; // Direction does not match. Ignore the track - } - // Direction match, try to apply the Switch Segment Pattern - if (INC_DIRECTION == direction) { - for (iy = start_y; iy < (end_y + 1); iy++) { - init_chan_seg_detail_params("chany_inc", chany_x, iy, max_x, max_y, seg_details_x, seg_details_y, /* INPUT list */ - &seg_num, &chan_num, seg_details, &max_len); /* OUTPUT list */ - /* Get the start point and end point of the segment*/ - start = get_seg_start(seg_details, track_id, chan_num, seg_num); - end = get_seg_end(seg_details, track_id, start, chan_num, max_len); - assert((start > 0)||(0 == start)); - assert((end > 0)||(0 == end)); - /* Get the segment length*/ - seg_len = end - start + 1; - /* Search a pattern*/ - select_swseg_pattern = search_swseg_pattern_seg_len(num_swseg_pattern, swseg_patterns, seg_len); - /* Nothing found, continue to the next track*/ - if (NULL == select_swseg_pattern) { - return RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN; // Do not need to apply any pattern - } - /* Rotate it*/ - rotated_pattern = rotate_shift_swseg_pattern(select_swseg_pattern->pattern_length,select_swseg_pattern->patterns,chany_x); - /* Check it the segment starts here*/ - if ((start == seg_num)&&(direction == INC_DIRECTION)) { - /* Get the corresponding rr_node index of CHANX MUX*/ - inode = get_rr_node_index(chan_num, seg_num, CHANY, track_id, L_rr_node_indices); - /* Check if we need to change the switch to a unbuffered one*/ - if (TRUE == rotated_pattern[swseg_offset]) { - swseg_pattern_change_switch_type(inode,CHANY,(*select_swseg_pattern), num_changed_chany); - } - /* Update the swseg_offset*/ - swseg_offset++; - if ((swseg_offset > select_swseg_pattern->pattern_length) - ||(swseg_offset == select_swseg_pattern->pattern_length)) { - swseg_offset = 0; - } - } - if ((rotated_pattern != NULL)&&(rotated_pattern != select_swseg_pattern->patterns)) { - free(rotated_pattern); - } - } - } else if (DEC_DIRECTION == direction) { - for (iy = start_y; iy > (end_y - 1); iy--) { - init_chan_seg_detail_params("chany_dec", chany_x, iy, max_x, max_y, seg_details_x, seg_details_y, /* INPUT list */ - &seg_num, &chan_num, seg_details, &max_len); /* OUTPUT list */ - /* Get the start point and end point of the segment*/ - start = get_seg_start(seg_details, track_id, chan_num, seg_num); - end = get_seg_end(seg_details, track_id, start, chan_num, max_len); - assert((start > 0)||(0 == start)); - assert((end > 0)||(0 == end)); - /* Get the segment length*/ - seg_len = end - start + 1; - /* Search a pattern*/ - select_swseg_pattern = search_swseg_pattern_seg_len(num_swseg_pattern, swseg_patterns, seg_len); - /* Nothing found, continue to the next track*/ - if (NULL == select_swseg_pattern) { - return RET_SWSEG_TRACK_NON_SEG_LEN_PATTERN; // Do not need to apply any pattern - } - /* Rotate it*/ - rotated_pattern = rotate_shift_swseg_pattern(select_swseg_pattern->pattern_length,select_swseg_pattern->patterns,chany_x); - /* Check it the segment starts here*/ - if ((end == seg_num)&&(direction == DEC_DIRECTION)) { - /* Get the corresponding rr_node index of CHANX MUX*/ - inode = get_rr_node_index(chan_num, seg_num, CHANY, track_id, L_rr_node_indices); - /* Check if we need to change the switch to a unbuffered one*/ - if (TRUE == rotated_pattern[swseg_offset]) { - swseg_pattern_change_switch_type(inode,CHANY,(*select_swseg_pattern), num_changed_chany); - } - /* Update the swseg_offset*/ - swseg_offset++; - if ((swseg_offset > select_swseg_pattern->pattern_length) - ||(swseg_offset == select_swseg_pattern->pattern_length)) { - swseg_offset = 0; - } - } - if ((rotated_pattern != NULL)&&(rotated_pattern != select_swseg_pattern->patterns)) { - free(rotated_pattern); - } - } - } - - return RET_SWSEG_TRACK_APPLIED; -} - - -/* Change the type of switch to a unbuffered one*/ -static -int swseg_pattern_change_switch_type(int cur_node, - t_rr_type chan_type, - t_swseg_pattern_inf swseg_pattern, - int* num_unbuf_mux) { - int iedge, jedge; - int inode, to_node; - - assert((CHANX == chan_type)||(CHANY == chan_type)); - /*Find the rr_node*/ - assert(rr_node+cur_node); - - for (iedge = 0; iedge < rr_node[cur_node].num_edges; iedge++) { - to_node = rr_node[cur_node].edges[iedge]; - if (chan_type == rr_node[to_node].type) { // Only apply to the matched type - rr_node[cur_node].switches[iedge] = swseg_pattern.unbuf_switch; - // Define the driver switch for routing stats - rr_node[to_node].unbuf_switched = 1; - rr_node[to_node].driver_switch = rr_node[cur_node].switches[iedge]; - (*num_unbuf_mux)++; - /* We should change the switches for other rr_nodes that drives this rr_node*/ - for(inode = 0; inode < num_rr_nodes; inode++) { - for (jedge = 0; jedge < rr_node[inode].num_edges; jedge++) { - if (to_node == rr_node[inode].edges[jedge]) { - rr_node[inode].switches[jedge] = rr_node[to_node].driver_switch; - } - } - } - } - } - - return 1; -} - -void update_rr_nodes_driver_switch(enum e_directionality directionality) { - int inode, iedge; - t_rr_type inode_rr_type; - int to_node; - - if (UNI_DIRECTIONAL != directionality) { - vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d])Update_rr_nodes_driver_switch is only valid for uni-directional routing architecture.\n", - __FILE__, __LINE__); - exit(1); - } - - /* Initial all the driver_switch to -1*/ - for (inode = 0; inode < num_rr_nodes; inode++) { - rr_node[inode].driver_switch = -1; - } - - for (inode = 0; inode < num_rr_nodes; inode++) { - inode_rr_type = rr_node[inode].type; - switch (inode_rr_type) { - // We care only switch boxes - case CHANX: - case CHANY: - for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { - to_node = rr_node[inode].edges[iedge]; - /* if to_node is a Channel, this is a switch box, - * if to_node is a IPIN, this is a connection box - */ - if ((CHANX == rr_node[to_node].type) - ||(CHANY == rr_node[to_node].type) - ||(IPIN == rr_node[to_node].type)) { - /* We should consider if driver_switch is the same or not*/ - if (-1 == rr_node[to_node].driver_switch) { - rr_node[to_node].driver_switch = rr_node[inode].switches[iedge]; - } else { - assert(rr_node[to_node].driver_switch == rr_node[inode].switches[iedge]); - } - } - } - break; - case OPIN: - for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { - to_node = rr_node[inode].edges[iedge]; - /* We care only to_node is a Channel - * Actually, in single driver routing, the switch is a delayless - * However, we have to update all switches - */ - if ((CHANX == rr_node[to_node].type) - ||(CHANY == rr_node[to_node].type)) { - /* We should consider if driver_switch is the same or not*/ - if (-1 == rr_node[to_node].driver_switch) { - rr_node[to_node].driver_switch = rr_node[inode].switches[iedge]; - } else { - assert(rr_node[to_node].driver_switch == rr_node[inode].switches[iedge]); - } - } - } - break; - case IPIN: - /* This is a sink... There is no to_node*/ - default: - break; - } - } -} - -/* Rotate the switch segmentpattern - * Original: 1 0 0 , rotated_shift = 2, return: 0 0 1 - */ -static -boolean* rotate_shift_swseg_pattern(int pattern_length, - boolean* pattern, - int rotate_shift_length) { - boolean* ret = NULL; - int shift_length; - - /* There is no need to do anything if input is NULL*/ - if ((pattern_length == 0)||(pattern_length < 0)) { - return NULL; - } - /* if rotate_shift_length exceeds the pattern lenght, we use mod */ - shift_length = rotate_shift_length % pattern_length; - /* Direct return the pattern */ - if (0 == shift_length) { - return pattern; - } - - /*Alloc*/ - ret = (boolean*)my_malloc(pattern_length*sizeof(boolean)); - /* Initialization*/ - memset(ret, 0, pattern_length*sizeof(boolean)); - - /*Rotate, rotated pattern: shifted part, orignal part*/ - /* Step 1: fill the shifted part*/ - memcpy(ret, pattern+pattern_length-shift_length, sizeof(boolean)*shift_length); - /* Step 2 : fill the rest*/ - memcpy(ret+shift_length, pattern, sizeof(boolean)*(pattern_length-shift_length)); - - /* Return*/ - return ret; -} diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_swseg.h b/vpr7_x2p/vpr/SRC/route/rr_graph_swseg.h deleted file mode 100644 index 0dea8a590..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_swseg.h +++ /dev/null @@ -1,12 +0,0 @@ -/*Declaration*/ -/*The top function*/ -int add_rr_graph_switch_segment_pattern(enum e_directionality directionality, - INP int nodes_per_chan, - INP int num_swseg_pattern, - INP t_swseg_pattern_inf* swseg_patterns, - INP t_ivec*** L_rr_node_indices, - INP t_seg_details* seg_details_x, - INP t_seg_details* seg_details_y); - -void update_rr_nodes_driver_switch(enum e_directionality directionality); - diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_timing_params.c b/vpr7_x2p/vpr/SRC/route/rr_graph_timing_params.c deleted file mode 100755 index c6f7ccc42..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_timing_params.c +++ /dev/null @@ -1,237 +0,0 @@ -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "rr_graph.h" -#include "rr_graph_util.h" -#include "rr_graph2.h" -#include "rr_graph_timing_params.h" - -/*mrFPGA: Xifan TANG*/ -#include "mrfpga_globals.h" -/*end */ - -/****************** Subroutine definitions *********************************/ - -void add_rr_graph_C_from_switches(float C_ipin_cblock) { - - /* This routine finishes loading the C elements of the rr_graph. It assumes * - * that when you call it the CHANX and CHANY nodes have had their C set to * - * their metal capacitance, and everything else has C set to 0. The graph * - * connectivity (edges, switch types etc.) must all be loaded too. This * - * routine will add in the capacitance on the CHANX and CHANY nodes due to: * - * * - * 1) The output capacitance of the switches coming from OPINs; * - * 2) The input and output capacitance of the switches between the various * - * wiring (CHANX and CHANY) segments; and * - * 3) The input capacitance of the buffers separating routing tracks from * - * the connection block inputs. */ - - int inode, iedge, switch_index, to_node, maxlen; - int icblock, isblock, iseg_low, iseg_high; - float Cin, Cout; - t_rr_type from_rr_type, to_rr_type; - boolean * cblock_counted; /* [0..max(nx,ny)] -- 0th element unused. */ - float *buffer_Cin; /* [0..max(nx,ny)] */ - boolean buffered; - float *Couts_to_add; /* UDSD */ - - maxlen = std::max(nx, ny) + 1; - cblock_counted = (boolean *) my_calloc(maxlen, sizeof(boolean)); - buffer_Cin = (float *) my_calloc(maxlen, sizeof(float)); - - for (inode = 0; inode < num_rr_nodes; inode++) { - - from_rr_type = rr_node[inode].type; - - if (from_rr_type == CHANX || from_rr_type == CHANY) { - - for (iedge = 0; iedge < rr_node[inode].num_edges; iedge++) { - - to_node = rr_node[inode].edges[iedge]; - to_rr_type = rr_node[to_node].type; - - if (to_rr_type == CHANX || to_rr_type == CHANY) { - - switch_index = rr_node[inode].switches[iedge]; - Cin = switch_inf[switch_index].Cin; - Cout = switch_inf[switch_index].Cout; - buffered = switch_inf[switch_index].buffered; - - /* If both the switch from inode to to_node and the switch from * - * to_node back to inode use bidirectional switches (i.e. pass * - * transistors), there will only be one physical switch for * - * both edges. Hence, I only want to count the capacitance of * - * that switch for one of the two edges. (Note: if there is * - * a pass transistor edge from x to y, I always build the graph * - * so that there is a corresponding edge using the same switch * - * type from y to x.) So, I arbitrarily choose to add in the * - * capacitance in that case of a pass transistor only when * - * processing the the lower inode number. * - * If an edge uses a buffer I always have to add in the output * - * capacitance. I assume that buffers are shared at the same * - * (i,j) location, so only one input capacitance needs to be * - * added for all the buffered switches at that location. If * - * the buffers at that location have different sizes, I use the * - * input capacitance of the largest one. */ - /* mrFPGA : Xifan TANG */ - if (is_junction) { - rr_node[inode].C += 2.0 * memristor_inf.C; - } - if (!is_isolation) { - /* end */ - /* Original VPR*/ - if (!buffered && inode < to_node) { /* Pass transistor. */ - rr_node[inode].C += Cin; - rr_node[to_node].C += Cout; - } - - else if (buffered) { - /* Prevent double counting of capacitance for UDSD */ - if (rr_node[to_node].drivers != SINGLE) { - /* For multiple-driver architectures the output capacitance can - * be added now since each edge is actually a driver */ - rr_node[to_node].C += Cout; - } - isblock = seg_index_of_sblock(inode, to_node); - buffer_Cin[isblock] = std::max(buffer_Cin[isblock], Cin); - } - /* end */ - } - - } - /* End edge to CHANX or CHANY node. */ - else if (to_rr_type == IPIN) { - - /* Code below implements sharing of the track to connection * - * box buffer. I assume there is one such buffer at every * - * segment of the wire at which at least one logic block input * - * connects. */ - - /* mrFPGA : Xifan TANG */ - if (is_junction) { - rr_node[inode].C += memristor_inf.C; - } - if (!is_isolation) { - /* end */ - /* Original VPR*/ - icblock = seg_index_of_cblock(from_rr_type, to_node); - if (cblock_counted[icblock] == FALSE) { - rr_node[inode].C += C_ipin_cblock; - cblock_counted[icblock] = TRUE; - } - } - /* end */ - } - } /* End loop over all edges of a node. */ - - /* Reset the cblock_counted and buffer_Cin arrays, and add buf Cin. */ - - /* Method below would be faster for very unpopulated segments, but I * - * think it would be slower overall for most FPGAs, so commented out. */ - - /* for (iedge=0;iedgeedge = edge; - linked_edge->iswitch = iswitch; - linked_edge->next = head; - - return linked_edge; -} - -#if 0 -void -free_linked_edge_soft(INOUT t_linked_edge * edge_ptr, - INOUT t_linked_edge ** free_list_head_ptr) -{ - - /* This routine does a soft free of the structure pointed to by edge_ptr by * - * adding it to the free list. You have to pass in the address of the * - * head of the free list. */ - - edge_ptr->next = *free_list_head_ptr; - *free_list_head_ptr = edge_ptr; -} -#endif - -int seg_index_of_cblock(t_rr_type from_rr_type, int to_node) { - - /* Returns the segment number (distance along the channel) of the connection * - * box from from_rr_type (CHANX or CHANY) to to_node (IPIN). */ - - if (from_rr_type == CHANX) - return (rr_node[to_node].xlow); - else - /* CHANY */ - return (rr_node[to_node].ylow); -} - -int seg_index_of_sblock(int from_node, int to_node) { - - /* Returns the segment number (distance along the channel) of the switch box * - * box from from_node (CHANX or CHANY) to to_node (CHANX or CHANY). The * - * switch box on the left side of a CHANX segment at (i,j) has seg_index = * - * i-1, while the switch box on the right side of that segment has seg_index * - * = i. CHANY stuff works similarly. Hence the range of values returned is * - * 0 to nx (if from_node is a CHANX) or 0 to ny (if from_node is a CHANY). */ - - t_rr_type from_rr_type, to_rr_type; - - from_rr_type = rr_node[from_node].type; - to_rr_type = rr_node[to_node].type; - - if (from_rr_type == CHANX) { - if (to_rr_type == CHANY) { - return (rr_node[to_node].xlow); - } else if (to_rr_type == CHANX) { - if (rr_node[to_node].xlow > rr_node[from_node].xlow) { /* Going right */ - return (rr_node[from_node].xhigh); - } else { /* Going left */ - return (rr_node[to_node].xhigh); - } - } else { - vpr_printf(TIO_MESSAGE_ERROR, "in seg_index_of_sblock: to_node %d is of type %d.\n", - to_node, to_rr_type); - exit(1); - } - } - /* End from_rr_type is CHANX */ - else if (from_rr_type == CHANY) { - if (to_rr_type == CHANX) { - return (rr_node[to_node].ylow); - } else if (to_rr_type == CHANY) { - if (rr_node[to_node].ylow > rr_node[from_node].ylow) { /* Going up */ - return (rr_node[from_node].yhigh); - } else { /* Going down */ - return (rr_node[to_node].yhigh); - } - } else { - vpr_printf(TIO_MESSAGE_ERROR, "in seg_index_of_sblock: to_node %d is of type %d.\n", - to_node, to_rr_type); - exit(1); - } - } - /* End from_rr_type is CHANY */ - else { - vpr_printf(TIO_MESSAGE_ERROR, "in seg_index_of_sblock: from_node %d is of type %d.\n", - from_node, from_rr_type); - exit(1); - } -} diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_util.h b/vpr7_x2p/vpr/SRC/route/rr_graph_util.h deleted file mode 100755 index 6db080324..000000000 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_util.h +++ /dev/null @@ -1,16 +0,0 @@ -struct s_linked_edge { - int edge; - short iswitch; - struct s_linked_edge *next; -}; -typedef struct s_linked_edge t_linked_edge; - -t_linked_edge *insert_in_edge_list(t_linked_edge * head, int edge, - short iswitch); - -void free_linked_edge_soft(t_linked_edge * edge_ptr, - t_linked_edge ** free_list_head_ptr); - -int seg_index_of_cblock(t_rr_type from_rr_type, int to_node); - -int seg_index_of_sblock(int from_node, int to_node); diff --git a/vpr7_x2p/vpr/SRC/route/segment_stats.c b/vpr7_x2p/vpr/SRC/route/segment_stats.c deleted file mode 100755 index 9c5895389..000000000 --- a/vpr7_x2p/vpr/SRC/route/segment_stats.c +++ /dev/null @@ -1,93 +0,0 @@ -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "segment_stats.h" - -/*************** Variables and defines local to this module ****************/ - -#define LONGLINE 0 - -/******************* Subroutine definitions ********************************/ - -void get_segment_usage_stats(int num_segment, t_segment_inf * segment_inf) { - - /* Computes statistics on the fractional utilization of segments by type * - * (index) and by length. This routine needs a valid rr_graph, and a * - * completed routing. Note that segments cut off by the end of the array * - * are counted as full-length segments (e.g. length 4 even if the last 2 * - * units of wire were chopped off by the chip edge). */ - - int inode, length, seg_type, max_segment_length, cost_index; - int *seg_occ_by_length, *seg_cap_by_length; /* [0..max_segment_length] */ - int *seg_occ_by_type, *seg_cap_by_type; /* [0..num_segment-1] */ - float utilization; - - max_segment_length = 0; - for (seg_type = 0; seg_type < num_segment; seg_type++) { - if (segment_inf[seg_type].longline == FALSE) - max_segment_length = std::max(max_segment_length, - segment_inf[seg_type].length); - } - - seg_occ_by_length = (int *) my_calloc((max_segment_length + 1), - sizeof(int)); - seg_cap_by_length = (int *) my_calloc((max_segment_length + 1), - sizeof(int)); - - seg_occ_by_type = (int *) my_calloc(num_segment, sizeof(int)); - seg_cap_by_type = (int *) my_calloc(num_segment, sizeof(int)); - - for (inode = 0; inode < num_rr_nodes; inode++) { - if (rr_node[inode].type == CHANX || rr_node[inode].type == CHANY) { - cost_index = rr_node[inode].cost_index; - seg_type = rr_indexed_data[cost_index].seg_index; - - if (!segment_inf[seg_type].longline) - length = segment_inf[seg_type].length; - else - length = LONGLINE; - - seg_occ_by_length[length] += rr_node[inode].occ; - seg_cap_by_length[length] += rr_node[inode].capacity; - seg_occ_by_type[seg_type] += rr_node[inode].occ; - seg_cap_by_type[seg_type] += rr_node[inode].capacity; - - } - } - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Segment usage by type (index):\n"); - vpr_printf(TIO_MESSAGE_INFO, "Segment type Fractional utilization\n"); - vpr_printf(TIO_MESSAGE_INFO, "------------ ----------------------\n"); - - for (seg_type = 0; seg_type < num_segment; seg_type++) { - if (seg_cap_by_type[seg_type] != 0) { - utilization = (float) seg_occ_by_type[seg_type] / (float) seg_cap_by_type[seg_type]; - vpr_printf(TIO_MESSAGE_INFO, "%8d %5.3g\n", seg_type, utilization); - } - } - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Segment usage by length:\n"); - vpr_printf(TIO_MESSAGE_INFO, "Segment length Fractional utilization\n"); - vpr_printf(TIO_MESSAGE_INFO, "-------------- ----------------------\n"); - - for (length = 1; length <= max_segment_length; length++) { - if (seg_cap_by_length[length] != 0) { - utilization = (float) seg_occ_by_length[length] / (float) seg_cap_by_length[length]; - vpr_printf(TIO_MESSAGE_INFO, "%9d %5.3g\n", length, utilization); - } - } - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - if (seg_cap_by_length[LONGLINE] != 0) { - utilization = (float) seg_occ_by_length[LONGLINE] / (float) seg_cap_by_length[LONGLINE]; - vpr_printf(TIO_MESSAGE_INFO, " longline %5.3g\n", utilization); - } - - free(seg_occ_by_length); - free(seg_cap_by_length); - free(seg_occ_by_type); - free(seg_cap_by_type); -} diff --git a/vpr7_x2p/vpr/SRC/route/segment_stats.h b/vpr7_x2p/vpr/SRC/route/segment_stats.h deleted file mode 100755 index 16f1c04f5..000000000 --- a/vpr7_x2p/vpr/SRC/route/segment_stats.h +++ /dev/null @@ -1 +0,0 @@ -void get_segment_usage_stats(int num_segment, t_segment_inf * segment_inf); diff --git a/vpr7_x2p/vpr/SRC/shell_main.c b/vpr7_x2p/vpr/SRC/shell_main.c deleted file mode 100644 index 1ea5290ea..000000000 --- a/vpr7_x2p/vpr/SRC/shell_main.c +++ /dev/null @@ -1,19 +0,0 @@ -/** - VPR is a CAD tool used to conduct FPGA architecture exploration. It takes, as input, a technology-mapped netlist and a description of the FPGA architecture being investigated. - VPR then generates a packed, placed, and routed FPGA (in .net, .place, and .route files respectively) that implements the input netlist. - - This file is where VPR starts execution. - - Key files in VPR: - 1. libarchfpga/physical_types.h - Data structures that define the properties of the FPGA architecture - 2. vpr_types.h - Very major file that defines the core data structures used in VPR. This includes detailed architecture information, user netlist data structures, and data structures that describe the mapping between those two. - 3. globals.h - Defines the global variables used by VPR. - */ - -#include - - -int main(int argc, char ** argv) { - - run_shell(argc, argv); -} diff --git a/vpr7_x2p/vpr/SRC/timing/net_delay.c b/vpr7_x2p/vpr/SRC/timing/net_delay.c deleted file mode 100755 index 441dc8cca..000000000 --- a/vpr7_x2p/vpr/SRC/timing/net_delay.c +++ /dev/null @@ -1,562 +0,0 @@ -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -/* Xifan TANG: move the data structures to another header file so that to share them*/ -#include "net_delay_types.h" -#include "net_delay_local_void.h" -/* END */ -#include "net_delay.h" - -/* mrFPGA: Xifan TANG */ -#include "mrfpga_globals.h" -#include "cal_capacitance.h" -/* end */ - -/*************************** Subroutine definitions **************************/ - -float ** -alloc_net_delay(t_chunk *chunk_list_ptr, struct s_net *nets, - int n_nets){ - - /* Allocates space for the net_delay data structure * - * [0..num_nets-1][1..num_pins-1]. I chunk the data to save space on large * - * problems. */ - - float **net_delay; /* [0..num_nets-1][1..num_pins-1] */ - float *tmp_ptr; - int inet; - - net_delay = (float **) my_malloc(n_nets * sizeof(float *)); - - for (inet = 0; inet < n_nets; inet++) { - tmp_ptr = (float *) my_chunk_malloc( - ((nets[inet].num_sinks + 1) - 1) * sizeof(float), - chunk_list_ptr); - - net_delay[inet] = tmp_ptr - 1; /* [1..num_pins-1] */ - } - - return (net_delay); -} - -void free_net_delay(float **net_delay, - t_chunk *chunk_list_ptr){ - - /* Frees the net_delay structure. Assumes it was chunk allocated. */ - - free(net_delay); - free_chunk_memory(chunk_list_ptr); -} - -void load_net_delay_from_routing(float **net_delay, struct s_net *nets, - int n_nets) { - - /* This routine loads net_delay[0..num_nets-1][1..num_pins-1]. Each entry * - * is the Elmore delay from the net source to the appropriate sink. Both * - * the rr_graph and the routing traceback must be completely constructed * - * before this routine is called, and the net_delay array must have been * - * allocated. */ - - t_rc_node *rc_node_free_list, *rc_root; - t_linked_rc_edge *rc_edge_free_list; - int inet; - t_linked_rc_ptr *rr_node_to_rc_node; /* [0..num_rr_nodes-1] */ - - rr_node_to_rc_node = (t_linked_rc_ptr *) my_calloc(num_rr_nodes, - sizeof(t_linked_rc_ptr)); - - rc_node_free_list = NULL; - rc_edge_free_list = NULL; - - for (inet = 0; inet < n_nets; inet++) { - if (nets[inet].is_global) { - load_one_constant_net_delay(net_delay, inet, nets, 0.); - } else { - rc_root = alloc_and_load_rc_tree(inet, &rc_node_free_list, - &rc_edge_free_list, rr_node_to_rc_node); - load_rc_tree_C(rc_root); - load_rc_tree_T(rc_root, 0.); - load_one_net_delay(net_delay, inet, nets, rr_node_to_rc_node); - free_rc_tree(rc_root, &rc_node_free_list, &rc_edge_free_list); - reset_rr_node_to_rc_node(rr_node_to_rc_node, inet); - } - } - - free_rc_node_free_list(rc_node_free_list); - free_rc_edge_free_list(rc_edge_free_list); - free(rr_node_to_rc_node); -} - -void load_constant_net_delay(float **net_delay, float delay_value, - struct s_net *nets, int n_nets) { - - /* Loads the net_delay array with delay_value for every source - sink * - * connection that is not on a global resource, and with 0. for every source * - * - sink connection on a global net. (This can be used to allow timing * - * analysis before routing is done with a constant net delay model). */ - - int inet; - - for (inet = 0; inet < n_nets; inet++) { - if (nets[inet].is_global) { - load_one_constant_net_delay(net_delay, inet, nets, 0.); - } else { - load_one_constant_net_delay(net_delay, inet, nets, delay_value); - } - } -} - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -t_rc_node * -alloc_and_load_rc_tree(int inet, t_rc_node ** rc_node_free_list_ptr, - t_linked_rc_edge ** rc_edge_free_list_ptr, - t_linked_rc_ptr * rr_node_to_rc_node) { - - /* Builds a tree describing the routing of net inet. Allocates all the data * - * and inserts all the connections in the tree. */ - - t_rc_node *curr_rc, *prev_rc, *root_rc; - struct s_trace *tptr; - int inode, prev_node; - short iswitch; - t_linked_rc_ptr *linked_rc_ptr; - - root_rc = alloc_rc_node(rc_node_free_list_ptr); - tptr = trace_head[inet]; - - if (tptr == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_rc_tree: Traceback for net %d does not exist.\n", inet); - exit(1); - } - - inode = tptr->index; - iswitch = tptr->iswitch; - root_rc->inode = inode; - root_rc->u.child_list = NULL; - rr_node_to_rc_node[inode].rc_node = root_rc; - - prev_rc = root_rc; - tptr = tptr->next; - - while (tptr != NULL) { - inode = tptr->index; - - /* Is this node a "stitch-in" point to part of the existing routing or a * - * new piece of routing along the current routing "arm?" */ - - if (rr_node_to_rc_node[inode].rc_node == NULL) { /* Part of current "arm" */ - curr_rc = alloc_rc_node(rc_node_free_list_ptr); - add_to_rc_tree(prev_rc, curr_rc, iswitch, inode, - rc_edge_free_list_ptr); - rr_node_to_rc_node[inode].rc_node = curr_rc; - prev_rc = curr_rc; - } - - else if (rr_node[inode].type != SINK) { /* Connection to old stuff. */ - -#ifdef DEBUG - prev_node = prev_rc->inode; - if (rr_node[prev_node].type != SINK) { - vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_rc_tree: Routing of net %d is not a tree.\n", inet); - exit(1); - } -#endif - - prev_rc = rr_node_to_rc_node[inode].rc_node; - } - - else { /* SINK that this net has connected to more than once. */ - - /* I can connect to a SINK node more than once in some weird architectures. * - * That means the routing isn't really a tree -- there is reconvergent * - * fanout from two or more IPINs into one SINK. I convert this structure * - * into a true RC tree on the fly by creating a new rc_node each time I hit * - * the same sink. This means I need to keep a linked list of the rc_nodes * - * associated with the rr_node (inode) associated with that SINK. */ - - curr_rc = alloc_rc_node(rc_node_free_list_ptr); - add_to_rc_tree(prev_rc, curr_rc, iswitch, inode, - rc_edge_free_list_ptr); - - linked_rc_ptr = (t_linked_rc_ptr *) my_malloc( - sizeof(t_linked_rc_ptr)); - linked_rc_ptr->next = rr_node_to_rc_node[inode].next; - rr_node_to_rc_node[inode].next = linked_rc_ptr; - linked_rc_ptr->rc_node = curr_rc; - - prev_rc = curr_rc; - } - iswitch = tptr->iswitch; - tptr = tptr->next; - } - - return (root_rc); -} - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -void add_to_rc_tree(t_rc_node * parent_rc, t_rc_node * child_rc, - short iswitch, int inode, t_linked_rc_edge ** rc_edge_free_list_ptr) { - - /* Adds child_rc to the child list of parent_rc, and sets the switch between * - * them to iswitch. This routine also intitializes the child_rc properly * - * and sets its node value to inode. */ - - t_linked_rc_edge *linked_rc_edge; - - linked_rc_edge = alloc_linked_rc_edge(rc_edge_free_list_ptr); - - linked_rc_edge->next = parent_rc->u.child_list; - parent_rc->u.child_list = linked_rc_edge; - - linked_rc_edge->child = child_rc; - linked_rc_edge->iswitch = iswitch; - - child_rc->u.child_list = NULL; - child_rc->inode = inode; -} - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -t_rc_node * -alloc_rc_node(t_rc_node ** rc_node_free_list_ptr) { - - /* Allocates a new rc_node, from the free list if possible, from the free * - * store otherwise. */ - - t_rc_node *rc_node; - - rc_node = *rc_node_free_list_ptr; - - if (rc_node != NULL) { - *rc_node_free_list_ptr = rc_node->u.next; - } else { - rc_node = (t_rc_node *) my_malloc(sizeof(t_rc_node)); - } - - return (rc_node); -} - - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -void free_rc_node(t_rc_node * rc_node, - t_rc_node ** rc_node_free_list_ptr) { - - /* Adds rc_node to the proper free list. */ - - rc_node->u.next = *rc_node_free_list_ptr; - *rc_node_free_list_ptr = rc_node; -} - - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -t_linked_rc_edge * -alloc_linked_rc_edge(t_linked_rc_edge ** rc_edge_free_list_ptr) { - - /* Allocates a new linked_rc_edge, from the free list if possible, from the * - * free store otherwise. */ - - t_linked_rc_edge *linked_rc_edge; - - linked_rc_edge = *rc_edge_free_list_ptr; - - if (linked_rc_edge != NULL) { - *rc_edge_free_list_ptr = linked_rc_edge->next; - } else { - linked_rc_edge = (t_linked_rc_edge *) my_malloc( - sizeof(t_linked_rc_edge)); - } - - return (linked_rc_edge); -} - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -void free_linked_rc_edge(t_linked_rc_edge * rc_edge, - t_linked_rc_edge ** rc_edge_free_list_ptr) { - - /* Adds the rc_edge to the rc_edge free list. */ - - rc_edge->next = *rc_edge_free_list_ptr; - *rc_edge_free_list_ptr = rc_edge; -} - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -float load_rc_tree_C(t_rc_node * rc_node) { - - /* Does a post-order traversal of the rc tree to load each node's * - * C_downstream with the proper sum of all the downstream capacitances. * - * This routine calls itself recursively to perform the traversal. */ - - t_linked_rc_edge *linked_rc_edge; - t_rc_node *child_node; - int inode; - short iswitch; - float C, C_downstream; - - linked_rc_edge = rc_node->u.child_list; - inode = rc_node->inode; - C = rr_node[inode].C; - - while (linked_rc_edge != NULL) { /* For all children */ - iswitch = linked_rc_edge->iswitch; - child_node = linked_rc_edge->child; - C_downstream = load_rc_tree_C(child_node); - - /* mrFPGA : Xifan TANG */ - if (is_isolation) { - C_downstream += switch_inf[iswitch].Cout; - C += switch_inf[iswitch].Cin; - } - /* end */ - - if (switch_inf[iswitch].buffered == FALSE) - C += C_downstream; - - linked_rc_edge = linked_rc_edge->next; - } - - /* mrFPGA : Xifan TANG */ - if (is_mrFPGA && rr_node[inode].buffered) { - rc_node->Tdel = (wire_buffer_inf.R + 0.5 * rr_node[inode].R) * C; - C = wire_buffer_inf.C; - if ((CHANX == rr_node[inode].type && rr_node[child_node->inode].yhigh <= rr_node[inode].ylow) - ||(rr_node[inode].type == CHANY && rr_node[child_node->inode].xhigh <= rr_node[inode].xlow)) { - rr_node[inode].buffered = -1; - } - } else { - rc_node->Tdel = 0.; - } - /* end */ - - rc_node->C_downstream = C; - return (C); -} - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -void load_rc_tree_T(t_rc_node * rc_node, float T_arrival) { - - /* This routine does a pre-order depth-first traversal of the rc tree to * - * compute the Tdel to each node in the rc tree. The T_arrival is the time * - * at which the signal hits the input to this node. This routine calls * - * itself recursively to perform the traversal. */ - - float Tdel, Rmetal, Tchild; - t_linked_rc_edge *linked_rc_edge; - t_rc_node *child_node; - short iswitch; - int inode; - - Tdel = T_arrival; - inode = rc_node->inode; - Rmetal = rr_node[inode].R; - - /* NB: rr_node[inode].C gives the capacitance of this node, while * - * rc_node->C_downstream gives the unbuffered downstream capacitance rooted * - * at this node, including the C of the node itself. I want to multiply * - * the C of this node by 0.5 Rmetal, since it's a distributed RC line. * - * Hence 0.5 Rmetal * Cnode is a pessimistic estimate of delay (i.e. end to * - * end). For the downstream capacitance rooted at this node (not including * - * the capacitance of the node itself), I assume it is, on average, * - * connected halfway along the line, so I also multiply by 0.5 Rmetal. To * - * be totally pessimistic I would multiply the downstream part of the * - * capacitance by Rmetal. Play with this equation if you like. */ - - /* Rmetal is distributed so x0.5 */ - /* mrFPGA : Xifan TANG */ - if (is_mrFPGA && rr_node[inode].buffered) { - Tdel += wire_buffer_inf.Tdel; - rc_node->Tdel += Tdel; - Tdel = rc_node->Tdel; - /* end */ - } else { - /* Original VPR */ - Tdel += 0.5 * rc_node->C_downstream * Rmetal; - rc_node->Tdel = Tdel; - /* end */ - } - - /* Now expand the children of this node to load their Tdel values. */ - - linked_rc_edge = rc_node->u.child_list; - - while (linked_rc_edge != NULL) { /* For all children */ - iswitch = linked_rc_edge->iswitch; - child_node = linked_rc_edge->child; - - Tchild = Tdel + switch_inf[iswitch].R * child_node->C_downstream; - Tchild += switch_inf[iswitch].Tdel; /* Intrinsic switch delay. */ - load_rc_tree_T(child_node, Tchild); - - linked_rc_edge = linked_rc_edge->next; - } -} - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -void load_one_net_delay(float **net_delay, int inet, struct s_net* nets, - t_linked_rc_ptr * rr_node_to_rc_node) { - - /* Loads the net delay array for net inet. The rc tree for that net must * - * have already been completely built and loaded. */ - - int ipin, inode; - float Tmax; - t_rc_node *rc_node; - t_linked_rc_ptr *linked_rc_ptr, *next_ptr; - - for (ipin = 1; ipin < (nets[inet].num_sinks + 1); ipin++) { - - inode = net_rr_terminals[inet][ipin]; - - linked_rc_ptr = rr_node_to_rc_node[inode].next; - rc_node = rr_node_to_rc_node[inode].rc_node; - Tmax = rc_node->Tdel; - - /* If below only executes when one net connects several times to the * - * same SINK. In this case, I can't tell which net pin each connection * - * to this SINK corresponds to (I can just choose arbitrarily). To make * - * sure the timing behaviour converges, I pessimistically set the delay * - * for all of the connections to this SINK by this net to be the max. of * - * the delays from this net to this SINK. NB: This code only occurs * - * when a net connect more than once to the same pin class on the same * - * logic block. Only a weird architecture would allow this. */ - - if (linked_rc_ptr != NULL) { - - /* The first time I hit a multiply-used SINK, I choose the largest delay * - * from this net to this SINK and use it for every connection to this * - * SINK by this net. */ - - do { - rc_node = linked_rc_ptr->rc_node; - if (rc_node->Tdel > Tmax) { - Tmax = rc_node->Tdel; - rr_node_to_rc_node[inode].rc_node = rc_node; - } - next_ptr = linked_rc_ptr->next; - free(linked_rc_ptr); - linked_rc_ptr = next_ptr; - } while (linked_rc_ptr != NULL); /* End do while */ - - rr_node_to_rc_node[inode].next = NULL; - } - /* End of if multiply-used SINK */ - net_delay[inet][ipin] = Tmax; - } -} - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -void load_one_constant_net_delay(float **net_delay, int inet, - struct s_net *nets, float delay_value) { - - /* Sets each entry of the net_delay array for net inet to delay_value. */ - - int ipin; - - for (ipin = 1; ipin < (nets[inet].num_sinks + 1); ipin++) - net_delay[inet][ipin] = delay_value; -} - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -void free_rc_tree(t_rc_node * rc_root, - t_rc_node ** rc_node_free_list_ptr, - t_linked_rc_edge ** rc_edge_free_list_ptr) { - - /* Puts the rc tree pointed to by rc_root back on the free list. Depth- * - * first post-order traversal via recursion. */ - - t_rc_node *rc_node, *child_node; - t_linked_rc_edge *rc_edge, *next_edge; - - rc_node = rc_root; - rc_edge = rc_node->u.child_list; - - while (rc_edge != NULL) { /* For all children */ - child_node = rc_edge->child; - free_rc_tree(child_node, rc_node_free_list_ptr, rc_edge_free_list_ptr); - next_edge = rc_edge->next; - free_linked_rc_edge(rc_edge, rc_edge_free_list_ptr); - rc_edge = next_edge; - } - - free_rc_node(rc_node, rc_node_free_list_ptr); -} - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -void reset_rr_node_to_rc_node(t_linked_rc_ptr * rr_node_to_rc_node, - int inet) { - - /* Resets the rr_node_to_rc_node mapping entries that were set during * - * construction of the RC tree for net inet. Any extra linked list entries * - * added to deal with a SINK being connected to multiple times have already * - * been freed by load_one_net_delay. */ - - struct s_trace *tptr; - int inode; - - tptr = trace_head[inet]; - - while (tptr != NULL) { - inode = tptr->index; - rr_node_to_rc_node[inode].rc_node = NULL; - tptr = tptr->next; - } -} - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -void free_rc_node_free_list(t_rc_node * rc_node_free_list) { - - /* Really frees (i.e. calls free()) all the rc_nodes on the free list. */ - - t_rc_node *rc_node, *next_node; - - rc_node = rc_node_free_list; - - while (rc_node != NULL) { - next_node = rc_node->u.next; - free(rc_node); - rc_node = next_node; - } -} - -/* mrFPGA: Xifan TANG, let's share these functions*/ -//static -/* END */ -void free_rc_edge_free_list(t_linked_rc_edge * rc_edge_free_list) { - - /* Really frees (i.e. calls free()) all the rc_edges on the free list. */ - - t_linked_rc_edge *rc_edge, *next_edge; - - rc_edge = rc_edge_free_list; - - while (rc_edge != NULL) { - next_edge = rc_edge->next; - free(rc_edge); - rc_edge = next_edge; - } -} diff --git a/vpr7_x2p/vpr/SRC/timing/net_delay.h b/vpr7_x2p/vpr/SRC/timing/net_delay.h deleted file mode 100755 index 1a879ff9b..000000000 --- a/vpr7_x2p/vpr/SRC/timing/net_delay.h +++ /dev/null @@ -1,19 +0,0 @@ -/*float **alloc_net_delay(struct s_linked_vptr **chunk_list_head_ptr, - struct s_net *nets, int n_nets);*/ - -float **alloc_net_delay(t_chunk *chunk_list_ptr, - struct s_net *nets, int n_nets); - -/*void free_net_delay(float **net_delay, - struct s_linked_vptr **chunk_list_head_ptr);*/ - -void free_net_delay(float **net_delay, - t_chunk *chunk_list_ptr); - -void load_net_delay_from_routing(float **net_delay, struct s_net *nets, - int n_nets); - -void load_constant_net_delay(float **net_delay, float delay_value, - struct s_net *nets, int n_nets); - - diff --git a/vpr7_x2p/vpr/SRC/timing/net_delay_local_void.h b/vpr7_x2p/vpr/SRC/timing/net_delay_local_void.h deleted file mode 100644 index 22de9e89f..000000000 --- a/vpr7_x2p/vpr/SRC/timing/net_delay_local_void.h +++ /dev/null @@ -1,57 +0,0 @@ - -/*********************** Subroutines local to this module ********************/ - -//static -t_rc_node *alloc_and_load_rc_tree(int inet, - t_rc_node ** rc_node_free_list_ptr, - t_linked_rc_edge ** rc_edge_free_list_ptr, - t_linked_rc_ptr * rr_node_to_rc_node); - -//static -void add_to_rc_tree(t_rc_node * parent_rc, t_rc_node * child_rc, - short iswitch, int inode, t_linked_rc_edge ** rc_edge_free_list_ptr); - -//static -t_rc_node *alloc_rc_node(t_rc_node ** rc_node_free_list_ptr); - -//static -void free_rc_node(t_rc_node * rc_node, - t_rc_node ** rc_node_free_list_ptr); - -//static -t_linked_rc_edge *alloc_linked_rc_edge( - t_linked_rc_edge ** rc_edge_free_list_ptr); - -//static -void free_linked_rc_edge(t_linked_rc_edge * rc_edge, - t_linked_rc_edge ** rc_edge_free_list_ptr); - -//static -float load_rc_tree_C(t_rc_node * rc_node); - -//static -void load_rc_tree_T(t_rc_node * rc_node, float T_arrival); - -//static -void load_one_net_delay(float **net_delay, int inet, struct s_net *nets, - t_linked_rc_ptr * rr_node_to_rc_node); - -//static -void load_one_constant_net_delay(float **net_delay, int inet, - struct s_net *nets, float delay_value); - -//static -void free_rc_tree(t_rc_node * rc_root, - t_rc_node ** rc_node_free_list_ptr, - t_linked_rc_edge ** rc_edge_free_list_ptr); - -//static -void reset_rr_node_to_rc_node(t_linked_rc_ptr * rr_node_to_rc_node, - int inet); - -//static -void free_rc_node_free_list(t_rc_node * rc_node_free_list); - -//static -void free_rc_edge_free_list(t_linked_rc_edge * rc_edge_free_list); - diff --git a/vpr7_x2p/vpr/SRC/timing/net_delay_types.h b/vpr7_x2p/vpr/SRC/timing/net_delay_types.h deleted file mode 100644 index cc7d7dcde..000000000 --- a/vpr7_x2p/vpr/SRC/timing/net_delay_types.h +++ /dev/null @@ -1,51 +0,0 @@ -/***************** Types and defines local to this module ********************/ - -struct s_linked_rc_edge { - struct s_rc_node *child; - short iswitch; - struct s_linked_rc_edge *next; -}; - -typedef struct s_linked_rc_edge t_linked_rc_edge; - -/* Linked list listing the children of an rc_node. * - * child: Pointer to an rc_node (child of the current node). * - * iswitch: Index of the switch type used to connect to the child node. * - * next: Pointer to the next linked_rc_edge in the linked list (allows * - * you to get the next child of the current rc_node). */ - -struct s_rc_node { - union { - t_linked_rc_edge *child_list; - struct s_rc_node *next; - } u; - int inode; - float C_downstream; - float Tdel; -}; - -typedef struct s_rc_node t_rc_node; - -/* Structure describing one node in an RC tree (used to get net delays). * - * u.child_list: Pointer to a linked list of linked_rc_edge. Each one of * - * the linked list entries gives a child of this node. * - * u.next: Used only when this node is on the free list. Gives the next * - * node on the free list. * - * inode: index (ID) of the rr_node that corresponds to this rc_node. * - * C_downstream: Total downstream capacitance from this rc_node. That is, * - * the total C of the subtree rooted at the current node, * - * including the C of the current node. * - * Tdel: Time delay for the signal to get from the net source to this node. * - * Includes the time to go through this node. */ - -struct s_linked_rc_ptr { - struct s_rc_node *rc_node; - struct s_linked_rc_ptr *next; -}; - -typedef struct s_linked_rc_ptr t_linked_rc_ptr; - -/* Linked list of pointers to rc_nodes. * - * rc_node: Pointer to an rc_node. * - * next: Next list element. */ - diff --git a/vpr7_x2p/vpr/SRC/timing/path_delay.c b/vpr7_x2p/vpr/SRC/timing/path_delay.c deleted file mode 100755 index 51b228555..000000000 --- a/vpr7_x2p/vpr/SRC/timing/path_delay.c +++ /dev/null @@ -1,3823 +0,0 @@ -#include -#include -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "path_delay.h" -#include "path_delay2.h" -#include "net_delay.h" -#include "vpr_utils.h" -#include -#include "read_xml_arch_file.h" -#include "ReadOptions.h" -#include "read_sdc.h" -#include "stats.h" - -/**************************** Top-level summary ****************************** - -Timing analysis by Vaughn Betz, Jason Luu, and Michael Wainberg. - -Timing analysis is a three-step process: -1. Interpret the constraints specified by the user in an SDC (Synopsys Design -Constraints) file or, if none is specified, use default constraints. -2. Convert the pre- or post-packed netlist (depending on the stage of the -flow) into a timing graph, where nodes represent pins and edges represent -dependencies and delays between pins (see "Timing graph structure", below). -3. Traverse the timing graph to obtain information about which connections -to optimize, as well as statistics for the user. - -Steps 1 and 2 are performed through one of two helper functions: -alloc_and_load_timing_graph and alloc_and_load_pre_packing_timing_graph. -The first step is to create the timing graph, which is stored in the array -tnode ("timing node"). This is done through alloc_and_load_tnodes (post- -packed) or alloc_and_load_tnodes_from_prepacked_netlist. Then, the timing -graph is topologically sorted ("levelized") in -alloc_and_load_timing_graph_levels, to allow for faster traversals later. - -read_sdc reads the SDC file, interprets its contents and stores them in -the data structure g_sdc. (This data structure does not need to remain -global but it is probably easier, since its information is used in both -netlists and only needs to be read in once.) - -load_clock_domain_and_clock_and_io_delay then gives each flip-flop and I/O -the index of a constrained clock from the SDC file in g_sdc->constrained_ -clocks, or -1 if an I/O is unconstrained. - -process_constraints does a pre-traversal through the timing graph and prunes -all constraints between domains that never intersect so they are not analysed. - -Step 3 is performed through do_timing_analysis. For each constraint between -a pair of clock domains we do a forward traversal from the "source" domain -to the "sink" domain to compute each tnode's arrival time, the time when the -latest signal would arrive at the node. We also do a backward traversal to -compute required time, the time when the earliest signal has to leave the -node to meet the constraint. The "slack" of each sink pin on each net is -basically the difference between the two times. - -If path counting is on, we calculate a forward and backward path weight in -do_path_counting. These represent the importance of paths fanning, -respectively, into and out of this pin, in such a way that paths with a -higher slack are discounted exponentially in importance. - -If path counting is off and we are using the pre-packed netlist, we also -calculate normalized costs for the clusterer (normalized arrival time, slack -and number of critical paths) in normalized_costs. The clusterer uses these -to calculate a criticality for each block. - -Finally, in update_slacks, we calculate the slack for each sink pin on each net -for printing, as well as a derived metric, timing criticality, which the -optimizers actually use. If path counting is on, we calculate a path criticality -from the forward and backward weights on each tnode. */ - -/************************* Timing graph structure **************************** - -Author: V. Betz - -We can build timing graphs that match either the primitive (logical_block) -netlist (of basic elements before clustering, like FFs and LUTs) or that -match the clustered netlist (block). You pass in the is_pre_packed flag to -say which kind of netlist and timing graph you are working with. - -Every used (not OPEN) block pin becomes a timing node, both on primitive -blocks and (if you’re building the timing graph that matches a clustered -netlist) on clustered blocks. For the clustered (not pre_packed) timing -graph, every used pin within a clustered (pb_type) block also becomes a timing -node. So a CLB that contains ALMs that contains LUTs will have nodes created -for the CLB pins, ALM pins and LUT pins, with edges that connect them as -specified in the clustered netlist. Unused (OPEN) pins don't create any -timing nodes. - -The primitive blocks have edges from the tnodes that represent input pins and -output pins that represent the timing dependencies within these lowest level -blocks (e.g. LUTs and FFs and IOs). The exact edges created come from reading -the architecture file. A LUT for example will have delays specified from all -its inputs to its output, and hence we will create a tedge from each tnode -corresponding to an input pin of the LUT to the tnode that represents the LUT -output pin. The delay marked on each edge is read from the architecture file. - -A FF has nodes representing its pins, but also two extra nodes, representing -the TN_FF_SINK and TN_FF_SOURCE. Those two nodes represent the internal storage -node of the FF. The TN_FF_SINK has edges going to it from the regular FF inputs -(but not the clock input), with appropriate delays. It has no outgoing edges, -since it terminates timing paths. The TN_FF_SOURCE has an edge going from it to -the FF output pin, with the appropriate delay. TN_FF_SOURCES have no edges; they -start timing paths. FF clock pins have no outgoing edges, but the delay to -them can be looked up, and is used in the timing traversals to compute clock -delay for slack computations. - -In the timing graph I create, input pads and constant generators have no -inputs (incoming edges), just like TN_FF_SOURCES. Every input pad and output -pad is represented by two tnodes -- an input pin/source and an output pin/ -sink. For an input pad the input source comes from off chip and has no fanin, -while the output pin drives signals within the chip. For output pads, the -input pin is driven by signal (net) within the chip, and the output sink node -goes off chip and has no fanout (out-edges). I need two nodes to respresent -things like pads because I mark all delay on tedges, not on tnodes. - -One other subblock that needs special attention is a constant generator. -This has no used inputs, but its output is used. I create an extra tnode, -a dummy input, in addition to the output pin tnode. The dummy tnode has -no fanin. Since constant generators really generate their outputs at T = --infinity, I set the delay from the input tnode to the output to a large- -magnitude negative number. This guarantees every block that needs the -output of a constant generator sees it available very early. - -The main structure of the timing graph is given by the nodes and the edges -that connect them. We also store some extra information on tnodes that -(1) lets us figure out how to map from a tnode back to the netlist pin (or -other item) it represents and (2) figure out what clock domain it is on, if -it is a timing path start point (no incoming edges) or end point (no outgoing -edges) and (3) lets us figure out the delay of the clock to that node, if it -is a timing path start or end point. - -To map efficiently from tedges back to the netlist pins, we create the tedge -array driven by a tnode the represents a netlist output pin *in the same order -as the netlist net pins*. That means the edge index for the tedge array from -such a tnode guarantees iedge = net_pin_index 1. The code to map slacks -from the timing graph back to the netlist relies on this. */ - -/*************************** Global variables *******************************/ - -t_tnode *tnode = NULL; /* [0..num_tnodes - 1] */ -int num_tnodes = 0; /* Number of nodes (pins) in the timing graph */ - -/******************** Variables local to this module ************************/ - -#define NUM_BUCKETS 5 /* Used when printing slack and criticality. */ - -/* Variables for "chunking" the tedge memory. If the head pointer in tedge_ch is NULL, * - * no timing graph exists now. */ - -static t_chunk tedge_ch = {NULL, 0, NULL}; - -static struct s_net *timing_nets = NULL; - -static int num_timing_nets = 0; - -static t_timing_stats * f_timing_stats = NULL; /* Critical path delay and worst-case slack per constraint. */ - -static int * f_net_to_driver_tnode; -/* [0..num_nets - 1]. Gives the index of the tnode that drives each net. -Used for both pre- and post-packed netlists. If you just want the number -of edges on the driver tnode, use: - num_edges = timing_nets[inet].num_sinks; -instead of the equivalent but more convoluted: - driver_tnode = f_net_to_driver_tnode[inet]; - num_edges = tnode[driver_tnode].num_edges; -Only use this array if you want the actual edges themselves or the index -of the driver tnode. */ - -/***************** Subroutines local to this module *************************/ - -static t_slack * alloc_slacks(void); - -static void update_slacks(t_slack * slacks, int source_clock_domain, int sink_clock_domain, float criticality_denom, - boolean update_slack); - -static void alloc_and_load_tnodes(t_timing_inf timing_inf); - -static void alloc_and_load_tnodes_from_prepacked_netlist(float block_delay, - float inter_cluster_net_delay); - -static void alloc_timing_stats(void); - -static float do_timing_analysis_for_constraint(int source_clock_domain, int sink_clock_domain, - boolean is_prepacked, boolean is_final_analysis, long * max_critical_input_paths_ptr, - long * max_critical_output_paths_ptr); - -#ifdef PATH_COUNTING -static void do_path_counting(float criticality_denom); -#endif - -static void do_lut_rebalancing(); -static void load_tnode(INP t_pb_graph_pin *pb_graph_pin, INP int iblock, - INOUTP int *inode, INP t_timing_inf timing_inf); - -#ifndef PATH_COUNTING -static void update_normalized_costs(float T_arr_max_this_domain, long max_critical_input_paths, - long max_critical_output_paths); -#endif - -static void print_primitive_as_blif (FILE *fpout, int iblk); - -static void set_and_balance_arrival_time(int to_node, int from_node, float Tdel, boolean do_lut_input_balancing); - -static void load_clock_domain_and_clock_and_io_delay(boolean is_prepacked); - -static char * find_tnode_net_name(int inode, boolean is_prepacked); - -static t_tnode * find_ff_clock_tnode(int inode, boolean is_prepacked); - -static inline int get_tnode_index(t_tnode * node); - -static inline boolean has_valid_T_arr(int inode); - -static inline boolean has_valid_T_req(int inode); - -static int find_clock(char * net_name); - -static int find_input(char * net_name); - -static int find_output(char * net_name); - -static int find_cf_constraint(char * source_clock_name, char * sink_ff_name); - -static void propagate_clock_domain_and_skew(int inode); - -static void process_constraints(void); - -static void print_global_criticality_stats(FILE * fp, float ** criticality, const char * singular_name, const char * capitalized_plural_name); - -static void print_timing_constraint_info(const char *fname); - -static void print_spaces(FILE * fp, int num_spaces); - -/********************* Subroutine definitions *******************************/ - -t_slack * alloc_and_load_timing_graph(t_timing_inf timing_inf) { - - /* This routine builds the graph used for timing analysis. Every cb pin is a - * timing node (tnode). The connectivity between pins is * - * represented by timing edges (tedges). All delay is marked on edges, not * - * on nodes. Returns two arrays that will store slack values: * - * slack and criticality ([0..num_nets-1][1..num_pins]). */ - - /* For pads, only the first two pin locations are used (input to pad is first, - * output of pad is second). For CLBs, all OPEN pins on the cb have their - * mapping set to OPEN so I won't use it by mistake. */ - - int num_sinks; - t_slack * slacks = NULL; - boolean do_process_constraints = FALSE; - - if (tedge_ch.chunk_ptr_head != NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_timing_graph: An old timing graph still exists.\n"); - exit(1); - } - num_timing_nets = num_nets; - timing_nets = clb_net; - - alloc_and_load_tnodes(timing_inf); - - num_sinks = alloc_and_load_timing_graph_levels(); - - check_timing_graph(num_sinks); - - slacks = alloc_slacks(); - - if (g_sdc == NULL) { - /* the SDC timing constraints only need to be read in once; * - * if they haven't been already, do it now */ - read_sdc(timing_inf); - do_process_constraints = TRUE; - } - - load_clock_domain_and_clock_and_io_delay(FALSE); - - if (do_process_constraints) - process_constraints(); - - if (f_timing_stats == NULL) - alloc_timing_stats(); - - return slacks; -} - -t_slack * alloc_and_load_pre_packing_timing_graph(float block_delay, - float inter_cluster_net_delay, t_model *models, t_timing_inf timing_inf) { - - /* This routine builds the graph used for timing analysis. Every technology- - * mapped netlist pin is a timing node (tnode). The connectivity between pins is * - * represented by timing edges (tedges). All delay is marked on edges, not * - * on nodes. Returns two arrays that will store slack values: * - * slack and criticality ([0..num_nets-1][1..num_pins]). */ - - /* For pads, only the first two pin locations are used (input to pad is first, - * output of pad is second). For CLBs, all OPEN pins on the cb have their - * mapping set to OPEN so I won't use it by mistake. */ - - int num_sinks; - t_slack * slacks = NULL; - boolean do_process_constraints = FALSE; - - if (tedge_ch.chunk_ptr_head != NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_timing_graph: An old timing graph still exists.\n"); - exit(1); - } - - num_timing_nets = num_logical_nets; - timing_nets = vpack_net; - - alloc_and_load_tnodes_from_prepacked_netlist(block_delay, - inter_cluster_net_delay); - - num_sinks = alloc_and_load_timing_graph_levels(); - - slacks = alloc_slacks(); - - check_timing_graph(num_sinks); - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_PRE_PACKING_TIMING_GRAPH_AS_BLIF)) { - print_timing_graph_as_blif(getEchoFileName(E_ECHO_PRE_PACKING_TIMING_GRAPH_AS_BLIF), models); - } - - if (g_sdc == NULL) { - /* the SDC timing constraints only need to be read in once; * - * if they haven't been already, do it now */ - read_sdc(timing_inf); - do_process_constraints = TRUE; - } - - load_clock_domain_and_clock_and_io_delay(TRUE); - - if (do_process_constraints) - process_constraints(); - - if (f_timing_stats == NULL) - alloc_timing_stats(); - - return slacks; -} - -static t_slack * alloc_slacks(void) { - - /* Allocates the slack, criticality and path_criticality structures - ([0..num_nets-1][1..num_pins-1]). Chunk allocated to save space. */ - - int inet; - t_slack * slacks = (t_slack *) my_malloc(sizeof(t_slack)); - - slacks->slack = (float **) my_malloc(num_timing_nets * sizeof(float *)); - slacks->timing_criticality = (float **) my_malloc(num_timing_nets * sizeof(float *)); -#ifdef PATH_COUNTING - slacks->path_criticality = (float **) my_malloc(num_timing_nets * sizeof(float *)); -#endif - for (inet = 0; inet < num_timing_nets; inet++) { - slacks->slack[inet] = (float *) my_chunk_malloc((timing_nets[inet].num_sinks + 1) * sizeof(float), &tedge_ch); - slacks->timing_criticality[inet] = (float *) my_chunk_malloc((timing_nets[inet].num_sinks + 1) * sizeof(float), &tedge_ch); -#ifdef PATH_COUNTING - slacks->path_criticality[inet] = (float *) my_chunk_malloc((timing_nets[inet].num_sinks + 1) * sizeof(float), &tedge_ch); -#endif - } - - return slacks; -} - -void load_timing_graph_net_delays(float **net_delay) { - - /* Sets the delays of the inter-CLB nets to the values specified by * - * net_delay[0..num_nets-1][1..num_pins-1]. These net delays should have * - * been allocated and loaded with the net_delay routines. This routine * - * marks the corresponding edges in the timing graph with the proper delay. */ - - int inet, ipin, inode; - t_tedge *tedge; - - for (inet = 0; inet < num_timing_nets; inet++) { - inode = f_net_to_driver_tnode[inet]; - tedge = tnode[inode].out_edges; - - /* Note that the edges of a tnode corresponding to a CLB or INPAD opin must * - * be in the same order as the pins of the net driven by the tnode. */ - - for (ipin = 1; ipin < (timing_nets[inet].num_sinks + 1); ipin++) - tedge[ipin - 1].Tdel = net_delay[inet][ipin]; - } -} - -void free_timing_graph(t_slack * slacks) { - - int inode; - - if (tedge_ch.chunk_ptr_head == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "in free_timing_graph: No timing graph to free.\n"); - exit(1); - } - - free_chunk_memory(&tedge_ch); - - if (tnode[0].prepacked_data) { - /* If we allocated prepacked_data for the first node, - it must be allocated for all other nodes too. */ - for (inode = 0; inode < num_tnodes; inode++) { - free(tnode[inode].prepacked_data); - } - } - free(tnode); - free(f_net_to_driver_tnode); - free_ivec_vector(tnodes_at_level, 0, num_tnode_levels - 1); - - free(slacks->slack); - free(slacks->timing_criticality); -#ifdef PATH_COUNTING - free(slacks->path_criticality); -#endif - free(slacks); - - tnode = NULL; - num_tnodes = 0; - f_net_to_driver_tnode = NULL; - tnodes_at_level = NULL; - num_tnode_levels = 0; - slacks = NULL; -} - -void free_timing_stats(void) { - int i; - if(f_timing_stats != NULL) { - for (i = 0; i < g_sdc->num_constrained_clocks; i++) { - free(f_timing_stats->cpd[i]); - free(f_timing_stats->least_slack[i]); - } - free(f_timing_stats->cpd); - free(f_timing_stats->least_slack); - free(f_timing_stats); - } - f_timing_stats = NULL; -} - -void print_slack(float ** slack, boolean slack_is_normalized, const char *fname) { - - /* Prints slacks into a file. */ - - int inet, iedge, ibucket, driver_tnode, num_edges, num_unused_slacks = 0; - t_tedge * tedge; - FILE *fp; - float max_slack = HUGE_NEGATIVE_FLOAT, min_slack = HUGE_POSITIVE_FLOAT, - total_slack = 0, total_negative_slack = 0, bucket_size, slk; - int slacks_in_bucket[NUM_BUCKETS]; - - fp = my_fopen(fname, "w", 0); - - if (slack_is_normalized) { - fprintf(fp, "The following slacks have been normalized to be non-negative by " - "relaxing the required times to the maximum arrival time.\n\n"); - } - - /* Go through slack once to get the largest and smallest slack, both for reporting and - so that we can delimit the buckets. Also calculate the total negative slack in the design. */ - for (inet = 0; inet < num_timing_nets; inet++) { - num_edges = timing_nets[inet].num_sinks; - for (iedge = 0; iedge < num_edges; iedge++) { - slk = slack[inet][iedge + 1]; - if (slk < HUGE_POSITIVE_FLOAT - 1) { /* if slack was analysed */ - max_slack = std::max(max_slack, slk); - min_slack = std::min(min_slack, slk); - total_slack += slk; - if (slk < NEGATIVE_EPSILON) { - total_negative_slack -= slk; /* By convention, we'll have total_negative_slack be a positive number. */ - } - } else { /* slack was never analysed */ - num_unused_slacks++; - } - } - } - - if (max_slack > HUGE_NEGATIVE_FLOAT + 1) { - fprintf(fp, "Largest slack in design: %g\n", max_slack); - } else { - fprintf(fp, "Largest slack in design: --\n"); - } - - if (min_slack < HUGE_POSITIVE_FLOAT - 1) { - fprintf(fp, "Smallest slack in design: %g\n", min_slack); - } else { - fprintf(fp, "Smallest slack in design: --\n"); - } - - fprintf(fp, "Total slack in design: %g\n", total_slack); - fprintf(fp, "Total negative slack: %g\n", total_negative_slack); - - if (max_slack - min_slack > EPSILON) { /* Only sort the slacks into buckets if not all slacks are the same (if they are identical, no need to sort). */ - /* Initialize slacks_in_bucket, an array counting how many slacks are within certain linearly-spaced ranges (buckets). */ - for (ibucket = 0; ibucket < NUM_BUCKETS; ibucket++) { - slacks_in_bucket[ibucket] = 0; - } - - /* The size of each bucket is the range of slacks, divided by the number of buckets. */ - bucket_size = (max_slack - min_slack)/NUM_BUCKETS; - - /* Now, pass through again, incrementing the number of slacks in the nth bucket - for each slack between (min_slack + n*bucket_size) and (min_slack + (n+1)*bucket_size). */ - - for (inet = 0; inet < num_timing_nets; inet++) { - num_edges = timing_nets[inet].num_sinks; - for (iedge = 0; iedge < num_edges; iedge++) { - slk = slack[inet][iedge + 1]; - if (slk < HUGE_POSITIVE_FLOAT - 1) { - /* We have to watch out for the special case where slack = max_slack, in which case ibucket = NUM_BUCKETS and we go out of bounds of the array. */ - ibucket = std::min(NUM_BUCKETS - 1, (int) ((slk - min_slack)/bucket_size)); - assert(ibucket >= 0 && ibucket < NUM_BUCKETS); - slacks_in_bucket[ibucket]++; - } - } - } - - /* Now print how many slacks are in each bucket. */ - fprintf(fp, "\n\nRange\t\t"); - for (ibucket = 0; ibucket < NUM_BUCKETS; ibucket++) { - fprintf(fp, "%.1e to ", min_slack); - min_slack += bucket_size; - fprintf(fp, "%.1e\t", min_slack); - } - fprintf(fp, "Not analysed"); - fprintf(fp, "\nSlacks in range\t\t"); - for (ibucket = 0; ibucket < NUM_BUCKETS; ibucket++) { - fprintf(fp, "%d\t\t\t", slacks_in_bucket[ibucket]); - } - fprintf(fp, "%d", num_unused_slacks); - } - - /* Finally, print all the slacks, organized by net. */ - fprintf(fp, "\n\nNet #\tDriver_tnode\tto_node\tSlack\n\n"); - - for (inet = 0; inet < num_timing_nets; inet++) { - driver_tnode = f_net_to_driver_tnode[inet]; - num_edges = tnode[driver_tnode].num_edges; - tedge = tnode[driver_tnode].out_edges; - slk = slack[inet][1]; - if (slk < HUGE_POSITIVE_FLOAT - 1) { - fprintf(fp, "%5d\t%5d\t\t%5d\t%g\n", inet, driver_tnode, tedge[0].to_node, slk); - } else { /* Slack is meaningless, so replace with --. */ - fprintf(fp, "%5d\t%5d\t\t%5d\t--\n", inet, driver_tnode, tedge[0].to_node); - } - for (iedge = 1; iedge < num_edges; iedge++) { /* newline and indent subsequent edges after the first */ - slk = slack[inet][iedge+1]; - if (slk < HUGE_POSITIVE_FLOAT - 1) { - fprintf(fp, "\t\t\t%5d\t%g\n", tedge[iedge].to_node, slk); - } else { /* Slack is meaningless, so replace with --. */ - fprintf(fp, "\t\t\t%5d\t--\n", tedge[iedge].to_node); - } - } - } - - fclose(fp); -} - -void print_criticality(t_slack * slacks, boolean criticality_is_normalized, const char *fname) { - - /* Prints timing criticalities (and path criticalities if enabled) into a file. */ - - int inet, iedge, driver_tnode, num_edges; - t_tedge * tedge; - FILE *fp; - - fp = my_fopen(fname, "w", 0); - - if (criticality_is_normalized) { - fprintf(fp, "Timing criticalities have been normalized to be non-negative by " - "relaxing the required times to the maximum arrival time.\n\n"); - } - - print_global_criticality_stats(fp, slacks->timing_criticality, "timing criticality", "Timing criticalities"); -#ifdef PATH_COUNTING - print_global_criticality_stats(fp, slacks->path_criticality, "path criticality", "Path criticalities"); -#endif - - /* Finally, print all the criticalities, organized by net. */ - fprintf(fp, "\n\nNet #\tDriver_tnode\t to_node\tTiming criticality" -#ifdef PATH_COUNTING - "\tPath criticality" -#endif - "\n"); - - for (inet = 0; inet < num_timing_nets; inet++) { - driver_tnode = f_net_to_driver_tnode[inet]; - num_edges = tnode[driver_tnode].num_edges; - tedge = tnode[driver_tnode].out_edges; - - fprintf(fp, "\n%5d\t%5d\t\t%5d\t\t%.6f", inet, driver_tnode, tedge[0].to_node, slacks->timing_criticality[inet][1]); -#ifdef PATH_COUNTING - fprintf(fp, "\t\t%g", slacks->path_criticality[inet][1]); -#endif - for (iedge = 1; iedge < num_edges; iedge++) { /* newline and indent subsequent edges after the first */ - fprintf(fp, "\n\t\t\t%5d\t\t%.6f", tedge[iedge].to_node, slacks->timing_criticality[inet][iedge+1]); -#ifdef PATH_COUNTING - fprintf(fp, "\t\t%g", slacks->path_criticality[inet][iedge+1]); -#endif - } - } - - fclose(fp); -} - -static void print_global_criticality_stats(FILE * fp, float ** criticality, const char * singular_name, const char * capitalized_plural_name) { - - /* Prints global stats for timing or path criticality to the file pointed to by fp, - including maximum criticality, minimum criticality, total criticality in the design, - and the number of criticalities within various ranges, or buckets. */ - - int inet, iedge, num_edges, ibucket, criticalities_in_bucket[NUM_BUCKETS]; - float crit, max_criticality = HUGE_NEGATIVE_FLOAT, min_criticality = HUGE_POSITIVE_FLOAT, - total_criticality = 0, bucket_size; - - /* Go through criticality once to get the largest and smallest timing criticality, - both for reporting and so that we can delimit the buckets. */ - for (inet = 0; inet < num_timing_nets; inet++) { - num_edges = timing_nets[inet].num_sinks; - for (iedge = 0; iedge < num_edges; iedge++) { - crit = criticality[inet][iedge + 1]; - max_criticality = std::max(max_criticality, crit); - min_criticality = std::min(min_criticality, crit); - total_criticality += crit; - } - } - - fprintf(fp, "Largest %s in design: %g\n", singular_name, max_criticality); - fprintf(fp, "Smallest %s in design: %g\n", singular_name, min_criticality); - fprintf(fp, "Total %s in design: %g\n", singular_name, total_criticality); - - if (max_criticality - min_criticality > EPSILON) { /* Only sort the criticalities into buckets if not all criticalities are the same (if they are identical, no need to sort). */ - /* Initialize criticalities_in_bucket, an array counting how many criticalities are within certain linearly-spaced ranges (buckets). */ - for (ibucket = 0; ibucket < NUM_BUCKETS; ibucket++) { - criticalities_in_bucket[ibucket] = 0; - } - - /* The size of each bucket is the range of criticalities, divided by the number of buckets. */ - bucket_size = (max_criticality - min_criticality)/NUM_BUCKETS; - - /* Now, pass through again, incrementing the number of criticalities in the nth bucket - for each criticality between (min_criticality + n*bucket_size) and (min_criticality + (n+1)*bucket_size). */ - - for (inet = 0; inet < num_timing_nets; inet++) { - num_edges = timing_nets[inet].num_sinks; - for (iedge = 0; iedge < num_edges; iedge++) { - crit = criticality[inet][iedge + 1]; - /* We have to watch out for the special case where criticality = max_criticality, in which case ibucket = NUM_BUCKETS and we go out of bounds of the array. */ - ibucket = std::min(NUM_BUCKETS - 1, (int) ((crit - min_criticality)/bucket_size)); - assert(ibucket >= 0 && ibucket < NUM_BUCKETS); - criticalities_in_bucket[ibucket]++; - } - } - - /* Now print how many criticalities are in each bucket. */ - fprintf(fp, "\nRange\t\t"); - for (ibucket = 0; ibucket < NUM_BUCKETS; ibucket++) { - fprintf(fp, "%.1e to ", min_criticality); - min_criticality += bucket_size; - fprintf(fp, "%.1e\t", min_criticality); - } - fprintf(fp, "\n%s in range\t\t", capitalized_plural_name); - for (ibucket = 0; ibucket < NUM_BUCKETS; ibucket++) { - fprintf(fp, "%d\t\t\t", criticalities_in_bucket[ibucket]); - } - } - fprintf(fp, "\n\n"); -} - -void print_net_delay(float **net_delay, const char *fname) { - - /* Prints the net delays into a file. */ - - int inet, iedge, driver_tnode, num_edges; - t_tedge * tedge; - FILE *fp; - - fp = my_fopen(fname, "w", 0); - - fprintf(fp, "Net #\tDriver_tnode\tto_node\tDelay\n\n"); - - for (inet = 0; inet < num_timing_nets; inet++) { - driver_tnode = f_net_to_driver_tnode[inet]; - num_edges = tnode[driver_tnode].num_edges; - tedge = tnode[driver_tnode].out_edges; - fprintf(fp, "%5d\t%5d\t\t%5d\t%g\n", inet, driver_tnode, tedge[0].to_node, net_delay[inet][1]); - for (iedge = 1; iedge < num_edges; iedge++) { /* newline and indent subsequent edges after the first */ - fprintf(fp, "\t\t\t%5d\t%g\n", tedge[iedge].to_node, net_delay[inet][iedge+1]); - } - } - - fclose(fp); -} - -#ifndef PATH_COUNTING -void print_clustering_timing_info(const char *fname) { - /* Print information from tnodes which is used by the clusterer. */ - int inode; - FILE *fp; - - fp = my_fopen(fname, "w", 0); - - fprintf(fp, "inode "); - if (g_sdc->num_constrained_clocks <= 1) { - /* These values are from the last constraint analysed, - so they're not meaningful unless there was only one constraint. */ - fprintf(fp, "Critical input paths Critical output paths "); - } - fprintf(fp, "Normalized slack Normalized Tarr Normalized total crit paths\n"); - for (inode = 0; inode < num_tnodes; inode++) { - fprintf(fp, "%d\t", inode); - /* Only print normalized values for tnodes which have valid normalized values. (If normalized_T_arr is valid, the others will be too.) */ - if (has_valid_normalized_T_arr(inode)) { - if (g_sdc->num_constrained_clocks <= 1) { - fprintf(fp, "%ld\t\t\t%ld\t\t\t", tnode[inode].prepacked_data->num_critical_input_paths, tnode[inode].prepacked_data->num_critical_output_paths); - } - fprintf(fp, "%f\t%f\t%f\n", tnode[inode].prepacked_data->normalized_slack, tnode[inode].prepacked_data->normalized_T_arr, tnode[inode].prepacked_data->normalized_total_critical_paths); - } else { - if (g_sdc->num_constrained_clocks <= 1) { - fprintf(fp, "--\t\t\t--\t\t\t"); - } - fprintf(fp, "--\t\t--\t\t--\n"); - } - } - - fclose(fp); -} -#endif -/* Count # of tnodes, allocates space, and loads the tnodes and its associated edges */ -static void alloc_and_load_tnodes(t_timing_inf timing_inf) { - int i, j, k; - int inode; - int num_nodes_in_block; - int count; - int iblock, irr_node; - int inet, dport, dpin, dblock, dnode; - int normalized_pin, normalization; - t_pb_graph_pin *ipb_graph_pin; - t_rr_node *local_rr_graph, *d_rr_graph; - int num_dangling_pins; - - f_net_to_driver_tnode = (int*)my_malloc(num_timing_nets * sizeof(int)); - - for (i = 0; i < num_timing_nets; i++) { - f_net_to_driver_tnode[i] = OPEN; - } - - /* allocate space for tnodes */ - num_tnodes = 0; - for (i = 0; i < num_blocks; i++) { - num_nodes_in_block = 0; - for (j = 0; j < block[i].pb->pb_graph_node->total_pb_pins; j++) { - if (block[i].pb->rr_graph[j].net_num != OPEN) { - if (block[i].pb->rr_graph[j].pb_graph_pin->type == PB_PIN_INPAD - || block[i].pb->rr_graph[j].pb_graph_pin->type - == PB_PIN_OUTPAD - || block[i].pb->rr_graph[j].pb_graph_pin->type - == PB_PIN_SEQUENTIAL) { - num_nodes_in_block += 2; - } else { - num_nodes_in_block++; - } - } - } - num_tnodes += num_nodes_in_block; - } - tnode = (t_tnode*)my_calloc(num_tnodes, sizeof(t_tnode)); - - /* load tnodes with all info except edge info */ - /* populate tnode lookups for edge info */ - inode = 0; - for (i = 0; i < num_blocks; i++) { - for (j = 0; j < block[i].pb->pb_graph_node->total_pb_pins; j++) { - if (block[i].pb->rr_graph[j].net_num != OPEN) { - assert(tnode[inode].pb_graph_pin == NULL); - load_tnode(block[i].pb->rr_graph[j].pb_graph_pin, i, &inode, - timing_inf); - } - } - } - assert(inode == num_tnodes); - num_dangling_pins = 0; - - /* load edge delays and initialize clock domains to OPEN - and prepacked_data (which is not used post-packing) to NULL. */ - for (i = 0; i < num_tnodes; i++) { - tnode[i].clock_domain = OPEN; - tnode[i].prepacked_data = NULL; - - /* 3 primary scenarios for edge delays - 1. Point-to-point delays inside block - 2. - */ - count = 0; - iblock = tnode[i].block; - switch (tnode[i].type) { - case TN_INPAD_OPIN: - case TN_INTERMEDIATE_NODE: - case TN_PRIMITIVE_OPIN: - case TN_FF_OPIN: - case TN_CB_IPIN: - /* fanout is determined by intra-cluster connections */ - /* Allocate space for edges */ - irr_node = tnode[i].pb_graph_pin->pin_count_in_cluster; - local_rr_graph = block[iblock].pb->rr_graph; - ipb_graph_pin = local_rr_graph[irr_node].pb_graph_pin; - - if (ipb_graph_pin->parent_node->pb_type->max_internal_delay - != UNDEFINED) { - if (pb_max_internal_delay == UNDEFINED) { - pb_max_internal_delay = - ipb_graph_pin->parent_node->pb_type->max_internal_delay; - pbtype_max_internal_delay = - ipb_graph_pin->parent_node->pb_type; - } else if (pb_max_internal_delay - < ipb_graph_pin->parent_node->pb_type->max_internal_delay) { - pb_max_internal_delay = - ipb_graph_pin->parent_node->pb_type->max_internal_delay; - pbtype_max_internal_delay = - ipb_graph_pin->parent_node->pb_type; - } - } - - for (j = 0; j < block[iblock].pb->rr_graph[irr_node].num_edges; - j++) { - dnode = local_rr_graph[irr_node].edges[j]; - if ((local_rr_graph[dnode].prev_node == irr_node) - && (j == local_rr_graph[dnode].prev_edge)) { - count++; - } - } - assert(count > 0); - tnode[i].num_edges = count; - tnode[i].out_edges = (t_tedge *) my_chunk_malloc( - count * sizeof(t_tedge), &tedge_ch); - - /* Load edges */ - count = 0; - for (j = 0; j < local_rr_graph[irr_node].num_edges; j++) { - dnode = local_rr_graph[irr_node].edges[j]; - if ((local_rr_graph[dnode].prev_node == irr_node) - && (j == local_rr_graph[dnode].prev_edge)) { - assert( - (ipb_graph_pin->output_edges[j]->num_output_pins == 1) && (local_rr_graph[ipb_graph_pin->output_edges[j]->output_pins[0]->pin_count_in_cluster].net_num == local_rr_graph[irr_node].net_num)); - - tnode[i].out_edges[count].Tdel = - ipb_graph_pin->output_edges[j]->delay_max; - tnode[i].out_edges[count].to_node = - get_tnode_index(local_rr_graph[dnode].tnode); - - if (vpack_net[local_rr_graph[irr_node].net_num].is_const_gen - == TRUE && tnode[i].type == TN_PRIMITIVE_OPIN) { - tnode[i].out_edges[count].Tdel = HUGE_NEGATIVE_FLOAT; - tnode[i].type = TN_CONSTANT_GEN_SOURCE; - } - - count++; - } - } - assert(count > 0); - - break; - case TN_PRIMITIVE_IPIN: - /* Pin info comes from pb_graph block delays - */ - /*there would be no slack information if timing analysis is off*/ - if (timing_inf.timing_analysis_enabled) - { - irr_node = tnode[i].pb_graph_pin->pin_count_in_cluster; - local_rr_graph = block[iblock].pb->rr_graph; - ipb_graph_pin = local_rr_graph[irr_node].pb_graph_pin; - tnode[i].num_edges = ipb_graph_pin->num_pin_timing; - tnode[i].out_edges = (t_tedge *) my_chunk_malloc( - ipb_graph_pin->num_pin_timing * sizeof(t_tedge), - &tedge_ch); - k = 0; - - for (j = 0; j < tnode[i].num_edges; j++) { - /* Some outpins aren't used, ignore these. Only consider output pins that are used */ - if (local_rr_graph[ipb_graph_pin->pin_timing[j]->pin_count_in_cluster].net_num - != OPEN) { - tnode[i].out_edges[k].Tdel = - ipb_graph_pin->pin_timing_del_max[j]; - tnode[i].out_edges[k].to_node = - get_tnode_index(local_rr_graph[ipb_graph_pin->pin_timing[j]->pin_count_in_cluster].tnode); - assert(tnode[i].out_edges[k].to_node != OPEN); - k++; - } - } - tnode[i].num_edges -= (j - k); /* remove unused edges */ - if (tnode[i].num_edges == 0) { - /* Dangling pin */ - num_dangling_pins++; - } - } - break; - case TN_CB_OPIN: - /* load up net info */ - irr_node = tnode[i].pb_graph_pin->pin_count_in_cluster; - local_rr_graph = block[iblock].pb->rr_graph; - ipb_graph_pin = local_rr_graph[irr_node].pb_graph_pin; - assert(local_rr_graph[irr_node].net_num != OPEN); - inet = vpack_to_clb_net_mapping[local_rr_graph[irr_node].net_num]; - assert(inet != OPEN); - f_net_to_driver_tnode[inet] = i; - tnode[i].num_edges = clb_net[inet].num_sinks; - tnode[i].out_edges = (t_tedge *) my_chunk_malloc( - clb_net[inet].num_sinks * sizeof(t_tedge), - &tedge_ch); - for (j = 1; j <= clb_net[inet].num_sinks; j++) { - dblock = clb_net[inet].node_block[j]; - normalization = block[dblock].type->num_pins - / block[dblock].type->capacity; - normalized_pin = clb_net[inet].node_block_pin[j] - % normalization; - d_rr_graph = block[dblock].pb->rr_graph; - dpin = OPEN; - dport = OPEN; - count = 0; - - for (k = 0; - k < block[dblock].pb->pb_graph_node->num_input_ports - && dpin == OPEN; k++) { - if (normalized_pin >= count - && (count - + block[dblock].pb->pb_graph_node->num_input_pins[k] - > normalized_pin)) { - dpin = normalized_pin - count; - dport = k; - break; - } - count += block[dblock].pb->pb_graph_node->num_input_pins[k]; - } - if (dpin == OPEN) { - for (k = 0; - k - < block[dblock].pb->pb_graph_node->num_output_ports - && dpin == OPEN; k++) { - count += - block[dblock].pb->pb_graph_node->num_output_pins[k]; - } - for (k = 0; - k < block[dblock].pb->pb_graph_node->num_clock_ports - && dpin == OPEN; k++) { - if (normalized_pin >= count - && (count - + block[dblock].pb->pb_graph_node->num_clock_pins[k] - > normalized_pin)) { - dpin = normalized_pin - count; - dport = k; - } - count += - block[dblock].pb->pb_graph_node->num_clock_pins[k]; - } - assert(dpin != OPEN); - assert( - inet == vpack_to_clb_net_mapping[d_rr_graph[block[dblock].pb->pb_graph_node->clock_pins[dport][dpin].pin_count_in_cluster].net_num]); - tnode[i].out_edges[j - 1].to_node = - get_tnode_index(d_rr_graph[block[dblock].pb->pb_graph_node->clock_pins[dport][dpin].pin_count_in_cluster].tnode); - } else { - assert(dpin != OPEN); - assert(inet == vpack_to_clb_net_mapping[d_rr_graph[block[dblock].pb->pb_graph_node->input_pins[dport][dpin].pin_count_in_cluster].net_num]); - /* delays are assigned post routing */ - tnode[i].out_edges[j - 1].to_node = - get_tnode_index(d_rr_graph[block[dblock].pb->pb_graph_node->input_pins[dport][dpin].pin_count_in_cluster].tnode); - } - tnode[i].out_edges[j - 1].Tdel = 0; - assert(inet != OPEN); - } - break; - case TN_OUTPAD_IPIN: - case TN_INPAD_SOURCE: - case TN_OUTPAD_SINK: - case TN_FF_SINK: - case TN_FF_SOURCE: - case TN_FF_IPIN: - case TN_FF_CLOCK: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "Consistency check failed: Unknown tnode type %d.\n", tnode[i].type); - assert(0); - break; - } - } - if(num_dangling_pins > 0) { - vpr_printf(TIO_MESSAGE_WARNING, "Unconnected logic in design, number of dangling tnodes = %d\n", num_dangling_pins); - } -} - -/* Allocate timing graph for pre packed netlist - Count number of tnodes first - Then connect up tnodes with edges - */ -static void alloc_and_load_tnodes_from_prepacked_netlist(float block_delay, - float inter_cluster_net_delay) { - int i, j, k; - t_model *model; - t_model_ports *model_port; - t_pb_graph_pin *from_pb_graph_pin, *to_pb_graph_pin; - int inode, inet; - int incr; - int count; - - f_net_to_driver_tnode = (int*)my_malloc(num_logical_nets * sizeof(int)); - - for (i = 0; i < num_logical_nets; i++) { - f_net_to_driver_tnode[i] = OPEN; - } - - /* allocate space for tnodes */ - num_tnodes = 0; - for (i = 0; i < num_logical_blocks; i++) { - model = logical_block[i].model; - logical_block[i].clock_net_tnode = NULL; - if (logical_block[i].type == VPACK_INPAD) { - logical_block[i].output_net_tnodes = (t_tnode***)my_calloc(1, - sizeof(t_tnode**)); - num_tnodes += 2; - } else if (logical_block[i].type == VPACK_OUTPAD) { - logical_block[i].input_net_tnodes = (t_tnode***)my_calloc(1, sizeof(t_tnode**)); - num_tnodes += 2; - } else { - if (logical_block[i].clock_net == OPEN) { - incr = 1; - } else { - incr = 2; - } - j = 0; - model_port = model->inputs; - while (model_port) { - if (model_port->is_clock == FALSE) { - for (k = 0; k < model_port->size; k++) { - if (logical_block[i].input_nets[j][k] != OPEN) { - num_tnodes += incr; - } - } - j++; - } else { - num_tnodes++; - } - model_port = model_port->next; - } - logical_block[i].input_net_tnodes = (t_tnode ***)my_calloc(j, sizeof(t_tnode**)); - - j = 0; - model_port = model->outputs; - while (model_port) { - for (k = 0; k < model_port->size; k++) { - if (logical_block[i].output_nets[j][k] != OPEN) { - num_tnodes += incr; - } - } - j++; - model_port = model_port->next; - } - logical_block[i].output_net_tnodes = (t_tnode ***)my_calloc(j, - sizeof(t_tnode**)); - } - } - tnode = (t_tnode *)my_calloc(num_tnodes, sizeof(t_tnode)); - - /* Allocate space for prepacked_data, which is only used pre-packing. */ - for (inode = 0; inode < num_tnodes; inode++) { - tnode[inode].prepacked_data = (t_prepacked_tnode_data *) my_malloc(sizeof(t_prepacked_tnode_data)); - } - - /* load tnodes, alloc edges for tnodes, load all known tnodes */ - inode = 0; - for (i = 0; i < num_logical_blocks; i++) { - model = logical_block[i].model; - if (logical_block[i].type == VPACK_INPAD) { - logical_block[i].output_net_tnodes[0] = (t_tnode **)my_calloc(1, - sizeof(t_tnode*)); - logical_block[i].output_net_tnodes[0][0] = &tnode[inode]; - f_net_to_driver_tnode[logical_block[i].output_nets[0][0]] = inode; - tnode[inode].prepacked_data->model_pin = 0; - tnode[inode].prepacked_data->model_port = 0; - tnode[inode].prepacked_data->model_port_ptr = model->outputs; - tnode[inode].block = i; - tnode[inode].type = TN_INPAD_OPIN; - - tnode[inode].num_edges = - vpack_net[logical_block[i].output_nets[0][0]].num_sinks; - tnode[inode].out_edges = (t_tedge *) my_chunk_malloc( - tnode[inode].num_edges * sizeof(t_tedge), - &tedge_ch); - tnode[inode + 1].num_edges = 1; - tnode[inode + 1].out_edges = (t_tedge *) my_chunk_malloc( - 1 * sizeof(t_tedge), &tedge_ch); - tnode[inode + 1].out_edges->Tdel = 0; - tnode[inode + 1].out_edges->to_node = inode; - tnode[inode + 1].type = TN_INPAD_SOURCE; - tnode[inode + 1].block = i; - inode += 2; - } else if (logical_block[i].type == VPACK_OUTPAD) { - logical_block[i].input_net_tnodes[0] = (t_tnode **)my_calloc(1, - sizeof(t_tnode*)); - logical_block[i].input_net_tnodes[0][0] = &tnode[inode]; - tnode[inode].prepacked_data->model_pin = 0; - tnode[inode].prepacked_data->model_port = 0; - tnode[inode].prepacked_data->model_port_ptr = model->inputs; - tnode[inode].block = i; - tnode[inode].type = TN_OUTPAD_IPIN; - tnode[inode].num_edges = 1; - tnode[inode].out_edges = (t_tedge *) my_chunk_malloc( - 1 * sizeof(t_tedge), &tedge_ch); - tnode[inode].out_edges->Tdel = 0; - tnode[inode].out_edges->to_node = inode + 1; - tnode[inode + 1].type = TN_OUTPAD_SINK; - tnode[inode + 1].block = i; - tnode[inode + 1].num_edges = 0; - tnode[inode + 1].out_edges = NULL; - inode += 2; - } else { - j = 0; - model_port = model->outputs; - while (model_port) { - logical_block[i].output_net_tnodes[j] = (t_tnode **)my_calloc( - model_port->size, sizeof(t_tnode*)); - for (k = 0; k < model_port->size; k++) { - if (logical_block[i].output_nets[j][k] != OPEN) { - tnode[inode].prepacked_data->model_pin = k; - tnode[inode].prepacked_data->model_port = j; - tnode[inode].prepacked_data->model_port_ptr = model_port; - tnode[inode].block = i; - f_net_to_driver_tnode[logical_block[i].output_nets[j][k]] = - inode; - logical_block[i].output_net_tnodes[j][k] = - &tnode[inode]; - - tnode[inode].num_edges = - vpack_net[logical_block[i].output_nets[j][k]].num_sinks; - tnode[inode].out_edges = (t_tedge *) my_chunk_malloc( - tnode[inode].num_edges * sizeof(t_tedge), - &tedge_ch); - - if (logical_block[i].clock_net == OPEN) { - tnode[inode].type = TN_PRIMITIVE_OPIN; - inode++; - } else { - /* load delays from predicted clock-to-Q time */ - from_pb_graph_pin = get_pb_graph_node_pin_from_model_port_pin(model_port, k, logical_block[i].expected_lowest_cost_primitive); - tnode[inode].type = TN_FF_OPIN; - tnode[inode + 1].num_edges = 1; - tnode[inode + 1].out_edges = - (t_tedge *) my_chunk_malloc( - 1 * sizeof(t_tedge), - &tedge_ch); - tnode[inode + 1].out_edges->to_node = inode; - tnode[inode + 1].out_edges->Tdel = from_pb_graph_pin->tsu_tco; - tnode[inode + 1].type = TN_FF_SOURCE; - tnode[inode + 1].block = i; - inode += 2; - } - } - } - j++; - model_port = model_port->next; - } - - j = 0; - model_port = model->inputs; - while (model_port) { - if (model_port->is_clock == FALSE) { - logical_block[i].input_net_tnodes[j] = (t_tnode **)my_calloc( - model_port->size, sizeof(t_tnode*)); - for (k = 0; k < model_port->size; k++) { - if (logical_block[i].input_nets[j][k] != OPEN) { - tnode[inode].prepacked_data->model_pin = k; - tnode[inode].prepacked_data->model_port = j; - tnode[inode].prepacked_data->model_port_ptr = model_port; - tnode[inode].block = i; - logical_block[i].input_net_tnodes[j][k] = - &tnode[inode]; - from_pb_graph_pin = get_pb_graph_node_pin_from_model_port_pin(model_port, k, logical_block[i].expected_lowest_cost_primitive); - if (logical_block[i].clock_net == OPEN) { - /* load predicted combinational delays to predicted edges */ - tnode[inode].type = TN_PRIMITIVE_IPIN; - tnode[inode].out_edges = - (t_tedge *) my_chunk_malloc( - from_pb_graph_pin->num_pin_timing * sizeof(t_tedge), - &tedge_ch); - count = 0; - for(int m = 0; m < from_pb_graph_pin->num_pin_timing; m++) { - to_pb_graph_pin = from_pb_graph_pin->pin_timing[m]; - if(logical_block[i].output_nets[to_pb_graph_pin->port->model_port->index][to_pb_graph_pin->pin_number] == OPEN) { - continue; - } - tnode[inode].out_edges[count].Tdel = from_pb_graph_pin->pin_timing_del_max[m]; - tnode[inode].out_edges[count].to_node = - get_tnode_index(logical_block[i].output_net_tnodes[to_pb_graph_pin->port->model_port->index][to_pb_graph_pin->pin_number]); - count++; - } - tnode[inode].num_edges = count; - inode++; - } else { - /* load predicted setup time */ - tnode[inode].type = TN_FF_IPIN; - tnode[inode].num_edges = 1; - tnode[inode].out_edges = - (t_tedge *) my_chunk_malloc( - 1 * sizeof(t_tedge), - &tedge_ch); - tnode[inode].out_edges->to_node = inode + 1; - tnode[inode].out_edges->Tdel = from_pb_graph_pin->tsu_tco; - tnode[inode + 1].type = TN_FF_SINK; - tnode[inode + 1].num_edges = 0; - tnode[inode + 1].out_edges = NULL; - tnode[inode + 1].block = i; - inode += 2; - } - } - } - j++; - } else { - if (logical_block[i].clock_net != OPEN) { - assert(logical_block[i].clock_net_tnode == NULL); - logical_block[i].clock_net_tnode = &tnode[inode]; - tnode[inode].block = i; - tnode[inode].prepacked_data->model_pin = 0; - tnode[inode].prepacked_data->model_port = 0; - tnode[inode].prepacked_data->model_port_ptr = model_port; - tnode[inode].num_edges = 0; - tnode[inode].out_edges = NULL; - tnode[inode].type = TN_FF_CLOCK; - inode++; - } - } - model_port = model_port->next; - } - } - } - assert(inode == num_tnodes); - - /* load edge delays and initialize clock domains to OPEN. */ - for (i = 0; i < num_tnodes; i++) { - tnode[i].clock_domain = OPEN; - - /* 3 primary scenarios for edge delays - 1. Point-to-point delays inside block - 2. - */ - count = 0; - switch (tnode[i].type) { - case TN_INPAD_OPIN: - case TN_PRIMITIVE_OPIN: - case TN_FF_OPIN: - /* fanout is determined by intra-cluster connections */ - /* Allocate space for edges */ - inet = - logical_block[tnode[i].block].output_nets[tnode[i].prepacked_data->model_port][tnode[i].prepacked_data->model_pin]; - assert(inet != OPEN); - - for (j = 1; j <= vpack_net[inet].num_sinks; j++) { - if (vpack_net[inet].is_const_gen) { - tnode[i].out_edges[j - 1].Tdel = HUGE_NEGATIVE_FLOAT; - tnode[i].type = TN_CONSTANT_GEN_SOURCE; - } else { - tnode[i].out_edges[j - 1].Tdel = inter_cluster_net_delay; - } - if (vpack_net[inet].is_global) { - assert( - logical_block[vpack_net[inet].node_block[j]].clock_net == inet); - tnode[i].out_edges[j - 1].to_node = - get_tnode_index(logical_block[vpack_net[inet].node_block[j]].clock_net_tnode); - } else { - assert( - logical_block[vpack_net[inet].node_block[j]].input_net_tnodes[vpack_net[inet].node_block_port[j]][vpack_net[inet].node_block_pin[j]] != NULL); - tnode[i].out_edges[j - 1].to_node = - get_tnode_index(logical_block[vpack_net[inet].node_block[j]].input_net_tnodes[vpack_net[inet].node_block_port[j]][vpack_net[inet].node_block_pin[j]]); - } - } - assert(tnode[i].num_edges == vpack_net[inet].num_sinks); - break; - case TN_PRIMITIVE_IPIN: - case TN_OUTPAD_IPIN: - case TN_INPAD_SOURCE: - case TN_OUTPAD_SINK: - case TN_FF_SINK: - case TN_FF_SOURCE: - case TN_FF_IPIN: - case TN_FF_CLOCK: - break; - default: - vpr_printf(TIO_MESSAGE_ERROR, "Consistency check failed: Unknown tnode type %d.\n", tnode[i].type); - assert(0); - break; - } - } - - for (i = 0; i < num_logical_nets; i++) { - assert(f_net_to_driver_tnode[i] != OPEN); - } -} - -static void load_tnode(INP t_pb_graph_pin *pb_graph_pin, INP int iblock, - INOUTP int *inode, INP t_timing_inf timing_inf) { - int i; - i = *inode; - tnode[i].pb_graph_pin = pb_graph_pin; - tnode[i].block = iblock; - block[iblock].pb->rr_graph[pb_graph_pin->pin_count_in_cluster].tnode = - &tnode[i]; - if (tnode[i].pb_graph_pin->parent_node->pb_type->blif_model == NULL) { - assert(tnode[i].pb_graph_pin->type == PB_PIN_NORMAL); - if (tnode[i].pb_graph_pin->parent_node->parent_pb_graph_node == NULL) { - if (tnode[i].pb_graph_pin->port->type == IN_PORT) { - tnode[i].type = TN_CB_IPIN; - } else { - assert(tnode[i].pb_graph_pin->port->type == OUT_PORT); - tnode[i].type = TN_CB_OPIN; - } - } else { - tnode[i].type = TN_INTERMEDIATE_NODE; - } - } else { - if (tnode[i].pb_graph_pin->type == PB_PIN_INPAD) { - assert(tnode[i].pb_graph_pin->port->type == OUT_PORT); - tnode[i].type = TN_INPAD_OPIN; - tnode[i + 1].num_edges = 1; - tnode[i + 1].out_edges = (t_tedge *) my_chunk_malloc( - 1 * sizeof(t_tedge), &tedge_ch); - tnode[i + 1].out_edges->Tdel = 0; - tnode[i + 1].out_edges->to_node = i; - tnode[i + 1].pb_graph_pin = pb_graph_pin; /* Necessary for propagate_clock_domain_and_skew(). */ - tnode[i + 1].type = TN_INPAD_SOURCE; - tnode[i + 1].block = iblock; - (*inode)++; - } else if (tnode[i].pb_graph_pin->type == PB_PIN_OUTPAD) { - assert(tnode[i].pb_graph_pin->port->type == IN_PORT); - tnode[i].type = TN_OUTPAD_IPIN; - tnode[i].num_edges = 1; - tnode[i].out_edges = (t_tedge *) my_chunk_malloc( - 1 * sizeof(t_tedge), &tedge_ch); - tnode[i].out_edges->Tdel = 0; - tnode[i].out_edges->to_node = i + 1; - tnode[i + 1].pb_graph_pin = pb_graph_pin; /* Necessary for find_tnode_net_name(). */ - tnode[i + 1].type = TN_OUTPAD_SINK; - tnode[i + 1].block = iblock; - tnode[i + 1].num_edges = 0; - tnode[i + 1].out_edges = NULL; - (*inode)++; - } else if (tnode[i].pb_graph_pin->type == PB_PIN_SEQUENTIAL) { - if (tnode[i].pb_graph_pin->port->type == IN_PORT) { - tnode[i].type = TN_FF_IPIN; - tnode[i].num_edges = 1; - tnode[i].out_edges = (t_tedge *) my_chunk_malloc( - 1 * sizeof(t_tedge), &tedge_ch); - tnode[i].out_edges->Tdel = pb_graph_pin->tsu_tco; - tnode[i].out_edges->to_node = i + 1; - tnode[i + 1].pb_graph_pin = pb_graph_pin; - tnode[i + 1].type = TN_FF_SINK; - tnode[i + 1].block = iblock; - tnode[i + 1].num_edges = 0; - tnode[i + 1].out_edges = NULL; - } else { - assert(tnode[i].pb_graph_pin->port->type == OUT_PORT); - tnode[i].type = TN_FF_OPIN; - tnode[i + 1].num_edges = 1; - tnode[i + 1].out_edges = (t_tedge *) my_chunk_malloc( - 1 * sizeof(t_tedge), &tedge_ch); - tnode[i + 1].out_edges->Tdel = pb_graph_pin->tsu_tco; - tnode[i + 1].out_edges->to_node = i; - tnode[i + 1].pb_graph_pin = pb_graph_pin; - tnode[i + 1].type = TN_FF_SOURCE; - tnode[i + 1].block = iblock; - } - (*inode)++; - } else if (tnode[i].pb_graph_pin->type == PB_PIN_CLOCK) { - tnode[i].type = TN_FF_CLOCK; - tnode[i].num_edges = 0; - tnode[i].out_edges = NULL; - } else { - if (tnode[i].pb_graph_pin->port->type == IN_PORT) { - assert(tnode[i].pb_graph_pin->type == PB_PIN_TERMINAL); - tnode[i].type = TN_PRIMITIVE_IPIN; - } else { - assert(tnode[i].pb_graph_pin->port->type == OUT_PORT); - assert(tnode[i].pb_graph_pin->type == PB_PIN_TERMINAL); - tnode[i].type = TN_PRIMITIVE_OPIN; - } - } - } - (*inode)++; -} - -void print_timing_graph(const char *fname) { - - /* Prints the timing graph into a file. */ - - FILE *fp; - int inode, iedge, ilevel, i; - t_tedge *tedge; - e_tnode_type itype; - const char *tnode_type_names[] = { "TN_INPAD_SOURCE", "TN_INPAD_OPIN", "TN_OUTPAD_IPIN", - - "TN_OUTPAD_SINK", "TN_CB_IPIN", "TN_CB_OPIN", "TN_INTERMEDIATE_NODE", - "TN_PRIMITIVE_IPIN", "TN_PRIMITIVE_OPIN", "TN_FF_IPIN", "TN_FF_OPIN", "TN_FF_SINK", - "TN_FF_SOURCE", "TN_FF_CLOCK", "TN_CONSTANT_GEN_SOURCE" }; - - fp = my_fopen(fname, "w", 0); - - fprintf(fp, "num_tnodes: %d\n", num_tnodes); - fprintf(fp, "Node #\tType\t\tipin\tiblk\tDomain\tSkew\tI/O Delay\t# edges\t" - "to_node Tdel\n\n"); - - for (inode = 0; inode < num_tnodes; inode++) { - fprintf(fp, "%d\t", inode); - - itype = tnode[inode].type; - fprintf(fp, "%-15.15s\t", tnode_type_names[itype]); - - if (tnode[inode].pb_graph_pin != NULL) { - fprintf(fp, "%d\t%d\t", - tnode[inode].pb_graph_pin->pin_count_in_cluster, - tnode[inode].block); - } else { - fprintf(fp, "\t%d\t", tnode[inode].block); - } - - if (itype == TN_FF_CLOCK || itype == TN_FF_SOURCE || itype == TN_FF_SINK) { - fprintf(fp, "%d\t%.3e\t\t", tnode[inode].clock_domain, tnode[inode].clock_delay); - } else if (itype == TN_INPAD_SOURCE) { - fprintf(fp, "%d\t\t%.3e\t", tnode[inode].clock_domain, tnode[inode].out_edges[0].Tdel); - } else if (itype == TN_OUTPAD_SINK) { - assert(tnode[inode-1].type == TN_OUTPAD_IPIN); /* Outpad ipins should be one prior in the tnode array */ - fprintf(fp, "%d\t\t%.3e\t", tnode[inode].clock_domain, tnode[inode-1].out_edges[0].Tdel); - } else { - fprintf(fp, "\t\t\t\t"); - } - - fprintf(fp, "%d", tnode[inode].num_edges); - - /* Print all edges after edge 0 on separate lines */ - tedge = tnode[inode].out_edges; - if (tnode[inode].num_edges > 0) { - fprintf(fp, "\t%4d\t%7.3g", tedge[0].to_node, tedge[0].Tdel); - for (iedge = 1; iedge < tnode[inode].num_edges; iedge++) { - fprintf(fp, "\n\t\t\t\t\t\t\t\t\t\t%4d\t%7.3g", tedge[iedge].to_node, tedge[iedge].Tdel); - } - } - fprintf(fp, "\n"); - } - - fprintf(fp, "\n\nnum_tnode_levels: %d\n", num_tnode_levels); - - for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) { - fprintf(fp, "\n\nLevel: %d Num_nodes: %d\nNodes:", ilevel, - tnodes_at_level[ilevel].nelem); - for (i = 0; i < tnodes_at_level[ilevel].nelem; i++) - fprintf(fp, "\t%d", tnodes_at_level[ilevel].list[i]); - } - - fprintf(fp, "\n"); - fprintf(fp, "\n\nNet #\tNet_to_driver_tnode\n"); - - for (i = 0; i < num_nets; i++) - fprintf(fp, "%4d\t%6d\n", i, f_net_to_driver_tnode[i]); - - if (g_sdc->num_constrained_clocks == 1) { - /* Arrival and required times, and forward and backward weights, will be meaningless for multiclock - designs, since the values currently on the graph will only correspond to the most recent traversal. */ - fprintf(fp, "\n\nNode #\t\tT_arr\t\tT_req" -#ifdef PATH_COUNTING - "\tForward weight\tBackward weight" -#endif - "\n\n"); - - for (inode = 0; inode < num_tnodes; inode++) { - if (tnode[inode].T_arr > HUGE_NEGATIVE_FLOAT + 1) { - fprintf(fp, "%d\t%12g", inode, tnode[inode].T_arr); - } else { - fprintf(fp, "%d\t\t -", inode); - } - if (tnode[inode].T_req < HUGE_POSITIVE_FLOAT - 1) { - fprintf(fp, "\t%12g", tnode[inode].T_req); - } else { - fprintf(fp, "\t\t -"); - } -#ifdef PATH_COUNTING - fprintf(fp, "\t%12g\t%12g\n", tnode[inode].forward_weight, tnode[inode].backward_weight); -#endif - } - } - - fclose(fp); -} -static void process_constraints(void) { - /* Removes all constraints between domains which never intersect. We need to do this - so that criticality_denom in do_timing_analysis is not affected by unused constraints. - BFS through the levelized graph once for each source domain. Whenever we get to a sink, - mark off that we've used that sink clock domain. After each traversal, set all unused - constraints to DO_NOT_ANALYSE. - - Also, print g_sdc->domain_constraints, constrained I/Os and override constraints, - and convert g_sdc->domain_constraints and flip-flop-level override constraints - to be in seconds rather than nanoseconds. We don't need to normalize g_sdc->cc_constraints - because they're already on the g_sdc->domain_constraints matrix, and we don't need - to normalize constrained_ios because we already did the normalization when - we put the delays onto the timing graph in load_clock_domain_and_clock_and_io_delay. */ - - int source_clock_domain, sink_clock_domain, inode, ilevel, num_at_level, i, - num_edges, iedge, to_node, icf, ifc, iff; - t_tedge * tedge; - float constraint; - boolean * constraint_used = (boolean *) my_malloc(g_sdc->num_constrained_clocks * sizeof(boolean)); - - for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { - /* We're going to use arrival time to flag which nodes we've reached, - even though the values we put in will not correspond to actual arrival times. - Nodes which are reached on this traversal will get an arrival time of 0. - Reset arrival times now to an invalid number. */ - for (inode = 0; inode < num_tnodes; inode++) { - tnode[inode].T_arr = HUGE_NEGATIVE_FLOAT; - } - - /* Reset all constraint_used entries. */ - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - constraint_used[sink_clock_domain] = FALSE; - } - - /* Set arrival times for each top-level tnode on this clock domain. */ - num_at_level = tnodes_at_level[0].nelem; - for (i = 0; i < num_at_level; i++) { - inode = tnodes_at_level[0].list[i]; - if (tnode[inode].clock_domain == source_clock_domain) { - tnode[inode].T_arr = 0.; - } - } - - for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) { /* Go down one level at a time. */ - num_at_level = tnodes_at_level[ilevel].nelem; - - for (i = 0; i < num_at_level; i++) { - inode = tnodes_at_level[ilevel].list[i]; /* Go through each of the tnodes at the level we're on. */ - if (has_valid_T_arr(inode)) { /* If this tnode has been used */ - num_edges = tnode[inode].num_edges; - if (num_edges == 0) { /* sink */ - /* We've reached the sink domain of this tnode, so set constraint_used - to true for this tnode's clock domain (if it has a valid one). */ - sink_clock_domain = tnode[inode].clock_domain; - if (sink_clock_domain != -1) { - constraint_used[sink_clock_domain] = TRUE; - } - } else { - /* Set arrival time to a valid value (0.) for each tnode in this tnode's fanout. */ - tedge = tnode[inode].out_edges; - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = tedge[iedge].to_node; - tnode[to_node].T_arr = 0.; - } - } - } - } - } - - /* At the end of the source domain traversal, see which sink domains haven't been hit, - and set the constraint for the pair of source and sink domains to DO_NOT_ANALYSE */ - - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - if (!constraint_used[sink_clock_domain]) { - g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = DO_NOT_ANALYSE; - } - } - } - - free(constraint_used); - - /* Print constraints */ - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_TIMING_CONSTRAINTS)) { - print_timing_constraint_info(getEchoFileName(E_ECHO_TIMING_CONSTRAINTS)); - } - - /* Convert g_sdc->domain_constraint and ff-level override constraints to be in seconds, not nanoseconds. */ - for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - constraint = g_sdc->domain_constraint[source_clock_domain][sink_clock_domain]; - if (constraint > NEGATIVE_EPSILON) { /* if constraint does not equal DO_NOT_ANALYSE */ - g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = constraint * 1e-9; - } - } - } - for (icf = 0; icf < g_sdc->num_cf_constraints; icf++) { - g_sdc->cf_constraints[icf].constraint *= 1e-9; - } - for (ifc = 0; ifc < g_sdc->num_fc_constraints; ifc++) { - g_sdc->fc_constraints[ifc].constraint *= 1e-9; - } - for (iff = 0; iff < g_sdc->num_ff_constraints; iff++) { - g_sdc->ff_constraints[iff].constraint *= 1e-9; - } - - /* Finally, free g_sdc->cc_constraints since all of its info is contained in g_sdc->domain_constraint. */ - free_override_constraint(g_sdc->cc_constraints, g_sdc->num_cc_constraints); -} - -static void alloc_timing_stats(void) { - - /* Allocate f_timing_stats data structure. */ - - int i; - - f_timing_stats = (t_timing_stats *) my_malloc(sizeof(t_timing_stats)); - f_timing_stats->cpd = (float **) my_malloc(g_sdc->num_constrained_clocks * sizeof(float *)); - f_timing_stats->least_slack = (float **) my_malloc(g_sdc->num_constrained_clocks * sizeof(float *)); - for (i = 0; i < g_sdc->num_constrained_clocks; i++) { - f_timing_stats->cpd[i] = (float *) my_malloc(g_sdc->num_constrained_clocks * sizeof(float)); - f_timing_stats->least_slack[i] = (float *) my_malloc(g_sdc->num_constrained_clocks * sizeof(float)); - } -} - -void do_timing_analysis(t_slack * slacks, boolean is_prepacked, boolean do_lut_input_balancing, boolean is_final_analysis) { - -/* Performs timing analysis on the circuit. Before this routine is called, t_slack * slacks - must have been allocated, and the circuit must have been converted into a timing graph. - The nodes of the timing graph represent pins and the edges between them represent delays - and m dependencies from one pin to another. Most elements are modeled as a pair of nodes so - that the delay through the element can be marked on the edge between them (e.g. - TN_INPAD_SOURCE->TN_INPAD_OPIN, TN_OUTPAD_IPIN->TN_OUTPAD_SINK, TN_PRIMITIVE_OPIN-> - TN_PRIMITIVE_OPIN, etc.). - - The timing graph nodes are stored as an array, tnode [0..num_tnodes - 1]. Each tnode - includes an array of all edges, tedge, which fan out from it. Each tedge includes the - index of the node on its far end (in the tnode array), and the delay to that node. - - The timing graph has sources at each TN_FF_SOURCE (Q output), TN_INPAD_SOURCE (input I/O pad) - and TN_CONSTANT_GEN_SOURCE (constant 1 or 0 generator) node and sinks at TN_FF_SINK (D input) - and TN_OUTPAD_SINK (output I/O pad) nodes. Two traversals, one forward (sources to sinks) - and one backward, are performed for each valid constraint (one which is not DO_NOT_ANALYSE) - between a source and a sink clock domain in the matrix g_sdc->domain_constraint - [0..g_sdc->num_constrained_clocks - 1][0..g_sdc->num_constrained_clocks - 1]. This matrix has been - pruned so that all domain pairs with no paths between them have been set to DO_NOT_ANALYSE. - - During the traversal pair for each constraint, all nodes in the fanout of sources on the - source clock domain are assigned a T_arr, the arrival time of the last input signal to the node. - All nodes in the fanin of sinks on the sink clock domain are assigned a T_req, the required - arrival time of the last input signal to the node if the critical path for this constraint is - not to be lengthened. Nodes which receive both a valid T_arr and T_req are flagged with - used_on_this_traversal, and nodes which are used on at least one traversal pair are flagged - with has_valid_slack so that later functions know the slack is valid. - - After each traversal pair, a slack is calculated for each sink pin on each net (or equivalently, - each connection or tedge fanning out from that net's driver tnode). Slack is calculated as: - T_req (dest node) - T_arr (source node) - Tdel (edge) - and represents the amount of delay which could be added to this connection before the critical - path delay for this constraint would worsen. Edges on the critical path have a slack of 0. - Slacks which are never used are set to HUGE_POSITIVE_FLOAT. - - The optimizers actually use a metric called timing_criticality. Timing criticality is defined - as 1 - slack / criticality_denom, where the normalization factor criticality_denom is the max - of all arrival times in the constraint and the constraint itself (T_req-relaxed slacks) or - all arrival times and constraints in the design (shifted slacks). See below for a further - discussion of these two regimes. Timing criticality is always between 0 (not critical) and 1 - (very critical). Unlike slack, which is set to HUGE_POSITIVE_FLOAT for unanalysed connections, - timing criticality is 0 for these, meaning no special check has to be made for which connections - have been analysed. - - If path counting is on (PATH_COUNTING is defined in vpr_types.h), the optimizers use a weighted - sum of timing_criticality and path_criticality, the latter of which is an estimate of the - importance of the number of paths using a particular connection. As a path's timing_criticality - decreases, it will become exponentially less important to the path_criticality of any connection - which this path uses. Path criticality also goes from 0 (not critical or unanalysed) to 1. - - Slack and criticalities are only calculated if both the driver of the net and the sink pin were - used_on_this_traversal, and are only overwritten if lower than previously-obtained values. - The optimizers actually use criticality rather than slack, but slack is useful for human - designers and so we calculate it only if we need to print it. - - This routine outputs slack and criticality to t_slack * slacks. It also stores least slack and - critical path delay per constraint [0..g_sdc->num_constrained_clocks - 1][0..g_sdc->num_constrained_clocks - 1] - in the file-scope variable f_timing_stats. - - Is_prepacked flags whether to calculate normalized costs for the clusterer (normalized_slack, - normalized_Tarr, normalized_total_critical_paths). Setting this to FALSE saves time in post- - packed timing analyses. - - Do_lut_input_balancing flags whether to rebalance LUT inputs. LUT rebalancing takes advantage of - the fact that different LUT inputs often have different delays. Since we can freely permute which - LUT inputs are used by just changing the logic in the LUT, these LUT permutations can be performed - late into the routing stage of the flow. - - Is_final_analysis flags whether this is the final, analysis pass. If it is, the analyser will - compute actual slacks instead of relaxed ones. We "relax" slacks by setting the required time to - the maximum arrival time for tight constraints so that no slacks are negative (which confuses - the optimizers). This is called "T_req-relaxed" slack. However, human designers want to see - actual slack values, so we report those in the final analysis. The alternative way of making - slacks positive is shifting them upwards by the value of the largest negative slack, after - all traversals are complete ("shifted slacks"), which can be enabled by changing SLACK_DEFINITION - from 'R' to 'S' in path_delay.h. - - To do: flip-flop to flip-flop and flip-flop to clock domain constraints (set_false_path, set_max_delay, - and especially set_multicycle_path). All the info for these constraints is contained in g_sdc->fc_constraints and - g_sdc->ff_constraints, but graph traversals are not included yet. Probably, an entire traversal will be needed for - each constraint. Clock domain to flip-flop constraints are coded but not tested, and are done within - existing traversals. */ - - int i, j, source_clock_domain, sink_clock_domain, inode, inet, ipin; - -#if defined PATH_COUNTING || SLACK_DEFINITION == 'S' - int iedge, num_edges; -#endif - -#ifdef PATH_COUNTING - float max_path_criticality = HUGE_NEGATIVE_FLOAT /* used to normalize path_criticalities */; -#endif - - boolean update_slack = (boolean) (is_final_analysis || getEchoEnabled()); - /* Only update slack values if we need to print it, i.e. - for the final output file (is_final_analysis) or echo files. */ - - float criticality_denom; /* (SLACK_DEFINITION == 'R' only) For a particular constraint, the maximum of - the constraint and all arrival times for the constraint's traversal. Used to - normalize the clusterer's normalized_slack and, more importantly, criticality. */ - - long max_critical_output_paths, max_critical_input_paths; - t_pb *pb; - -#if SLACK_DEFINITION == 'S' - float smallest_slack_in_design = HUGE_POSITIVE_FLOAT; - /* Shift all slacks upwards by this number if it is negative. */ - - float criticality_denom_global = HUGE_NEGATIVE_FLOAT; - /* Denominator of criticality for shifted - max of all arrival times and all constraints. */ -#endif - - /* Reset LUT input rebalancing. */ - for (inode = 0; inode < num_tnodes; inode++) { - if (tnode[inode].type == TN_PRIMITIVE_OPIN && tnode[inode].pb_graph_pin != NULL) { - pb = block[tnode[inode].block].pb->rr_node_to_pb_mapping[tnode[inode].pb_graph_pin->pin_count_in_cluster]; - if (pb != NULL && pb->lut_pin_remap != NULL) { - /* this is a LUT primitive, do pin swapping */ - assert(pb->pb_graph_node->pb_type->num_output_pins == 1 && pb->pb_graph_node->pb_type->num_clock_pins == 0); /* ensure LUT properties are valid */ - assert(pb->pb_graph_node->num_input_ports == 1); - /* If all input pins are known, perform LUT input delay rebalancing, do nothing otherwise */ - for (i = 0; i < pb->pb_graph_node->num_input_pins[0]; i++) { - pb->lut_pin_remap[i] = OPEN; - } - } - } - } - - /* Reset all values which need to be reset once per - timing analysis, rather than once per traversal pair. */ - - /* Reset slack and criticality */ - for (inet = 0; inet < num_timing_nets; inet++) { - for (ipin = 1; ipin <= timing_nets[inet].num_sinks; ipin++) { - slacks->slack[inet][ipin] = HUGE_POSITIVE_FLOAT; - slacks->timing_criticality[inet][ipin] = 0.; -#ifdef PATH_COUNTING - slacks->path_criticality[inet][ipin] = 0.; -#endif - } - } - - /* Reset f_timing_stats. */ - for (i = 0; i < g_sdc->num_constrained_clocks; i++) { - for (j = 0; j < g_sdc->num_constrained_clocks; j++) { - f_timing_stats->cpd[i][j] = HUGE_NEGATIVE_FLOAT; - f_timing_stats->least_slack[i][j] = HUGE_POSITIVE_FLOAT; - } - } - -#ifndef PATH_COUNTING - /* Reset normalized values for clusterer. */ - if (is_prepacked) { - for (inode = 0; inode < num_tnodes; inode++) { - tnode[inode].prepacked_data->normalized_slack = HUGE_POSITIVE_FLOAT; - tnode[inode].prepacked_data->normalized_T_arr = HUGE_NEGATIVE_FLOAT; - tnode[inode].prepacked_data->normalized_total_critical_paths = HUGE_NEGATIVE_FLOAT; - } - } -#endif - - if (do_lut_input_balancing) { - do_lut_rebalancing(); - } - - /* For each valid constraint (pair of source and sink clock domains), we do one - forward and one backward topological traversal to find arrival and required times, - in do_timing_analysis_for_constraint. If path counting is on, we then do another, - simpler traversal to find forward and backward weights, relying on the largest - required time we found from the first traversal. After each constraint's traversals, - we update the slacks, timing criticalities and (if necessary) path criticalities or - normalized costs used by the clusterer. */ - - for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - if (g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] > NEGATIVE_EPSILON) { /* i.e. != DO_NOT_ANALYSE */ - - /* Perform the forward and backward traversal for this constraint. */ - criticality_denom = do_timing_analysis_for_constraint(source_clock_domain, sink_clock_domain, - is_prepacked, is_final_analysis, &max_critical_input_paths, &max_critical_output_paths); -#ifdef PATH_COUNTING - /* Weight the importance of each net, used in slack calculation. */ - do_path_counting(criticality_denom); -#endif - - /* Update the slack and criticality for each edge of each net which was - analysed on the most recent traversal and has a lower (slack) or - higher (criticality) value than before. */ - update_slacks(slacks, source_clock_domain, sink_clock_domain, criticality_denom, update_slack); - -#ifndef PATH_COUNTING - /* Update the normalized costs used by the clusterer. */ - if (is_prepacked) { - update_normalized_costs(criticality_denom, max_critical_input_paths, max_critical_output_paths); - } -#endif - -#if SLACK_DEFINITION == 'S' - /* Set criticality_denom_global to the max of criticality_denom over all traversals. */ - criticality_denom_global = std::max(criticality_denom_global, criticality_denom); -#endif - } - } - } - -#ifdef PATH_COUNTING - /* Normalize path criticalities by the largest value in the - circuit. Otherwise, path criticalities would be unbounded. */ - - for (inet = 0; inet < num_timing_nets; inet++) { - num_edges = timing_nets[inet].num_sinks; - for (iedge = 0; iedge < num_edges; iedge++) { - max_path_criticality = std::max(max_path_criticality, slacks->path_criticality[inet][iedge + 1]); - } - } - - for (inet = 0; inet < num_timing_nets; inet++) { - num_edges = timing_nets[inet].num_sinks; - for (iedge = 0; iedge < num_edges; iedge++) { - slacks->path_criticality[inet][iedge + 1] /= max_path_criticality; - } - } - -#endif - -#if SLACK_DEFINITION == 'S' - if (!is_final_analysis) { - - /* Find the smallest slack in the design. */ - for (i = 0; i < g_sdc->num_constrained_clocks; i++) { - for (j = 0; j < g_sdc->num_constrained_clocks; j++) { - smallest_slack_in_design = std::min(smallest_slack_in_design, f_timing_stats->least_slack[i][j]); - } - } - - /* Increase all slacks by the value of the smallest slack in the design, if it's negative. */ - if (smallest_slack_in_design < 0) { - for (inet = 0; inet < num_timing_nets; inet++) { - num_edges = timing_nets[inet].num_sinks; - for (iedge = 0; iedge < num_edges; iedge++) { - slacks->slack[inet][iedge + 1] -= smallest_slack_in_design; - /* Remember, smallest_slack_in_design is negative, so we're INCREASING all the slacks. */ - /* Note that if slack was equal to HUGE_POSITIVE_FLOAT, it will still be equal to more than this, - so it will still be ignored when we calculate criticalities. */ - } - } - } - } - - /* We can now calculate criticalities, only after we normalize slacks. */ - for (inet = 0; inet < num_timing_nets; inet++) { - num_edges = timing_nets[inet].num_sinks; - for (iedge = 0; iedge < num_edges; iedge++) { - if (slacks->slack[inet][iedge + 1] < HUGE_POSITIVE_FLOAT - 1) { /* if the slack is valid */ - slacks->timing_criticality[inet][iedge + 1] = 1 - slacks->slack[inet][iedge + 1]/criticality_denom_global; - } - /* otherwise, criticality remains 0, as it was initialized */ - } - } -#endif -} - -static void do_lut_rebalancing() { - - int inode, num_at_level, i, ilevel, num_edges, iedge, to_node; - t_tedge * tedge; - - /* Reset all arrival times to a very large negative number. */ - for (inode = 0; inode < num_tnodes; inode++) { - tnode[inode].T_arr = HUGE_NEGATIVE_FLOAT; - } - - /* Set arrival times for each top-level tnode. */ - num_at_level = tnodes_at_level[0].nelem; - for (i = 0; i < num_at_level; i++) { - inode = tnodes_at_level[0].list[i]; - if (tnode[inode].type == TN_FF_SOURCE) { - /* Set the arrival time of this flip-flop tnode to its clock skew. */ - tnode[inode].T_arr = tnode[inode].clock_delay; - } else if (tnode[inode].type == TN_INPAD_SOURCE) { - /* There's no such thing as clock skew for external clocks. The closest equivalent, - input delay, is already marked on the edge coming out from this node. - As a result, the signal can be said to arrive at t = 0. */ - tnode[inode].T_arr = 0.; - } - } - - /* Now we actually start the forward topological traversal, to compute arrival times. */ - for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) { /* For each level of our levelized timing graph... */ - num_at_level = tnodes_at_level[ilevel].nelem; /* ...there are num_at_level tnodes at that level. */ - - for (i = 0; i < num_at_level; i++) { - inode = tnodes_at_level[ilevel].list[i]; /* Go through each of the tnodes at the level we're on. */ - - num_edges = tnode[inode].num_edges; /* Get the number of edges fanning out from the node we're visiting */ - tedge = tnode[inode].out_edges; /* Get the list of edges from the node we're visiting */ - - for (iedge = 0; iedge < num_edges; iedge++) { /* Now go through each edge coming out from this tnode */ - to_node = tedge[iedge].to_node; /* Get the index of the destination tnode of this edge. */ - - /* The arrival time T_arr at the destination node is set to the maximum of all the - possible arrival times from all edges fanning in to the node. - The arrival time represents the latest time that all inputs must arrive at a node. - LUT input rebalancing also occurs at this step. */ - set_and_balance_arrival_time(to_node, inode, tedge[iedge].Tdel, TRUE); - } - } - } -} - - -static float do_timing_analysis_for_constraint(int source_clock_domain, int sink_clock_domain, - boolean is_prepacked, boolean is_final_analysis, long * max_critical_input_paths_ptr, - long * max_critical_output_paths_ptr) { - - /* Performs a single forward and backward traversal for the domain pair - source_clock_domain and sink_clock_domain. Returns the denominator that - will be later used to normalize criticality - the maximum of all arrival - times from this traversal and the constraint for this pair of domains. - Also returns the maximum number of critical input and output paths of any - node analysed for this constraint, passed by reference from do_timing_analysis. */ - - int inode, num_at_level, i, total, ilevel, num_edges, iedge, to_node, icf; - float constraint, Tdel, T_req, max_Tarr = HUGE_NEGATIVE_FLOAT; - /* Max of all arrival times for this constraint - - used to relax required times. */ - t_tedge * tedge; - int num_dangling_nodes; - boolean found; - long max_critical_input_paths = 0, max_critical_output_paths = 0; - - /* Reset all values which need to be reset once per - traversal pair, rather than once per timing analysis. */ - - /* Reset all arrival and required times. */ - for (inode = 0; inode < num_tnodes; inode++) { - tnode[inode].T_arr = HUGE_NEGATIVE_FLOAT; - tnode[inode].T_req = HUGE_POSITIVE_FLOAT; - } - -#ifndef PATH_COUNTING - /* Reset num_critical_output_paths. */ - if (is_prepacked) { - for (inode = 0; inode < num_tnodes; inode++) { - tnode[inode].prepacked_data->num_critical_output_paths = 0; - } - } -#endif - - /* Set arrival times for each top-level tnode on this source domain. */ - num_at_level = tnodes_at_level[0].nelem; - for (i = 0; i < num_at_level; i++) { - inode = tnodes_at_level[0].list[i]; - - if (tnode[inode].clock_domain == source_clock_domain) { - - if (tnode[inode].type == TN_FF_SOURCE) { - /* Set the arrival time of this flip-flop tnode to its clock skew. */ - tnode[inode].T_arr = tnode[inode].clock_delay; - - } else if (tnode[inode].type == TN_INPAD_SOURCE) { - /* There's no such thing as clock skew for external clocks, and - input delay is already marked on the edge coming out from this node. - As a result, the signal can be said to arrive at t = 0. */ - tnode[inode].T_arr = 0.; - } - - } - } - - /* Compute arrival times with a forward topological traversal from sources - (TN_FF_SOURCE, TN_INPAD_SOURCE, TN_CONSTANT_GEN_SOURCE) to sinks (TN_FF_SINK, TN_OUTPAD_SINK). */ - - total = 0; /* We count up all tnodes to error-check at the end. */ - for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) { /* For each level of our levelized timing graph... */ - num_at_level = tnodes_at_level[ilevel].nelem; /* ...there are num_at_level tnodes at that level. */ - total += num_at_level; - - for (i = 0; i < num_at_level; i++) { - inode = tnodes_at_level[ilevel].list[i]; /* Go through each of the tnodes at the level we're on. */ - if (tnode[inode].T_arr < NEGATIVE_EPSILON) { /* If the arrival time is less than 0 (i.e. HUGE_NEGATIVE_FLOAT)... */ - continue; /* End this iteration of the num_at_level for loop since - this node is not part of the clock domain we're analyzing. - (If it were, it would have received an arrival time already.) */ - } - - num_edges = tnode[inode].num_edges; /* Get the number of edges fanning out from the node we're visiting */ - tedge = tnode[inode].out_edges; /* Get the list of edges from the node we're visiting */ -#ifndef PATH_COUNTING - if (is_prepacked && ilevel == 0) { - tnode[inode].prepacked_data->num_critical_input_paths = 1; /* Top-level tnodes have one locally-critical input path. */ - } - - /* Using a somewhat convoluted procedure inherited from T-VPack, - count how many locally-critical input paths fan into each tnode, - and also find the maximum number over all tnodes. */ - if (is_prepacked) { - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = tedge[iedge].to_node; - if (fabs(tnode[to_node].T_arr - (tnode[inode].T_arr + tedge[iedge].Tdel)) < EPSILON) { - /* If the "local forward slack" (T_arr(to_node) - T_arr(inode) - T_del) for this edge - is 0 (i.e. the path from inode to to_node is locally as critical as any other path to - to_node), add to_node's num critical input paths to inode's number. */ - tnode[to_node].prepacked_data->num_critical_input_paths += tnode[inode].prepacked_data->num_critical_input_paths; - } else if (tnode[to_node].T_arr < (tnode[inode].T_arr + tedge[iedge].Tdel)) { - /* If the "local forward slack" for this edge is negative, - reset to_node's num critical input paths to inode's number. */ - tnode[to_node].prepacked_data->num_critical_input_paths = tnode[inode].prepacked_data->num_critical_input_paths; - } - /* Set max_critical_input_paths to the maximum number of critical - input paths for all tnodes analysed on this traversal. */ - if (tnode[to_node].prepacked_data->num_critical_input_paths > max_critical_input_paths) { - max_critical_input_paths = tnode[to_node].prepacked_data->num_critical_input_paths; - } - } - } -#endif - for (iedge = 0; iedge < num_edges; iedge++) { /* Now go through each edge coming out from this tnode */ - to_node = tedge[iedge].to_node; /* Get the index of the destination tnode of this edge. */ - - /* The arrival time T_arr at the destination node is set to the maximum of all - the possible arrival times from all edges fanning in to the node. The arrival - time represents the latest time that all inputs must arrive at a node. LUT input - rebalancing also occurs at this step. */ - set_and_balance_arrival_time(to_node, inode, tedge[iedge].Tdel, FALSE); - - /* Since we updated the destination node (to_node), change the max arrival - time for the forward traversal if to_node's arrival time is greater than - the existing maximum. */ - max_Tarr = std::max(max_Tarr, tnode[to_node].T_arr); - } - } - } - - assert(total == num_tnodes); - num_dangling_nodes = 0; - /* Compute required times with a backward topological traversal from sinks to sources. */ - - for (ilevel = num_tnode_levels - 1; ilevel >= 0; ilevel--) { - num_at_level = tnodes_at_level[ilevel].nelem; - - for (i = 0; i < num_at_level; i++) { - inode = tnodes_at_level[ilevel].list[i]; - num_edges = tnode[inode].num_edges; - - if (ilevel == 0) { - if (!(tnode[inode].type == TN_INPAD_SOURCE || tnode[inode].type == TN_FF_SOURCE || tnode[inode].type == TN_CONSTANT_GEN_SOURCE)) { - vpr_printf(TIO_MESSAGE_ERROR, "Timing graph started on unexpected node %s.%s[%d].\n", - tnode[inode].pb_graph_pin->parent_node->pb_type->name, - tnode[inode].pb_graph_pin->port->name, - tnode[inode].pb_graph_pin->pin_number); - vpr_printf(TIO_MESSAGE_ERROR, "This is a VPR internal error, contact VPR development team.\n"); - exit(1); - } - } else { - if ((tnode[inode].type == TN_INPAD_SOURCE || tnode[inode].type == TN_FF_SOURCE || tnode[inode].type == TN_CONSTANT_GEN_SOURCE)) { - vpr_printf(TIO_MESSAGE_ERROR, "Timing graph discovered unexpected edge to node %s.%s[%d].\n", - tnode[inode].pb_graph_pin->parent_node->pb_type->name, - tnode[inode].pb_graph_pin->port->name, - tnode[inode].pb_graph_pin->pin_number); - vpr_printf(TIO_MESSAGE_ERROR, "This is a VPR internal error, contact VPR development team.\n"); - exit(1); - } - } - - /* Unlike the forward traversal, the sinks are all on different levels, so we always have to - check whether a node is a sink. We give every sink on the sink clock domain we're considering - a valid required time. Every non-sink node in the fanin of one of these sinks and the fanout of - some source from the forward traversal also gets a valid required time. */ - - if (num_edges == 0) { /* sink */ - - if (tnode[inode].type == TN_FF_CLOCK || tnode[inode].T_arr < HUGE_NEGATIVE_FLOAT + 1) { - continue; /* Skip nodes on the clock net itself, and nodes with unset arrival times. */ - } - - if (!(tnode[inode].type == TN_OUTPAD_SINK || tnode[inode].type == TN_FF_SINK)) { - if(is_prepacked) { - vpr_printf(TIO_MESSAGE_WARNING, "Pin on block %s.%s[%d] not used\n", - logical_block[tnode[inode].block].name, - tnode[inode].prepacked_data->model_port_ptr->name, - tnode[inode].prepacked_data->model_pin); - } - num_dangling_nodes++; - /* Note: Still need to do standard traversals with dangling pins so that algorithm runs properly, but T_arr and T_Req to values such that it dangling nodes do not affect actual timing values */ - } - - /* Skip nodes not on the sink clock domain of the - constraint we're currently considering */ - if (tnode[inode].clock_domain != sink_clock_domain) { - continue; - } - - /* See if there's an override constraint between the source clock domain (name is - g_sdc->constrained_clocks[source_clock_domain].name) and the flip-flop or outpad we're at - now (name is find_tnode_net_name(inode, is_prepacked)). We test if - g_sdc->num_cf_constraints > 0 first so that we can save time looking up names in the vast - majority of cases where there are no such constraints. */ - - if (g_sdc->num_cf_constraints > 0 && (icf = find_cf_constraint(g_sdc->constrained_clocks[source_clock_domain].name, find_tnode_net_name(inode, is_prepacked))) != -1) { - constraint = g_sdc->cf_constraints[icf].constraint; - if (constraint < NEGATIVE_EPSILON) { - /* Constraint is DO_NOT_ANALYSE (-1) for this particular sink. */ - continue; - } - } else { /* Use the default constraint from g_sdc->domain_constraint. */ - constraint = g_sdc->domain_constraint[source_clock_domain][sink_clock_domain]; - /* Constraint is guaranteed to be valid since we checked for it at the very beginning. */ - } - - /* Now we know we should analyse this tnode. */ - -#if SLACK_DEFINITION == 'R' - /* Assign the required time T_req for this leaf node, taking into account clock skew. T_req is the - time all inputs to a tnode must arrive by before it would degrade this constraint's critical path delay. - - Relax the required time at the sink node to be non-negative by taking the max of the "real" required - time (constraint + tnode[inode].clock_delay) and the max arrival time in this domain (max_Tarr), except - for the final analysis where we report actual slack. We do this to prevent any slacks from being - negative, since negative slacks are not used effectively by the optimizers. - - E.g. if we have a 10 ns constraint and it takes 14 ns to get here, we'll have a slack of at most -4 ns - for any edge along the path that got us here. If we say the required time is 14 ns (no less than the - arrival time), we don't have a negative slack anymore. However, in the final timing analysis, the real - slacks are computed (that's what human designers care about), not the relaxed ones. */ - - if (is_final_analysis) { - tnode[inode].T_req = constraint + tnode[inode].clock_delay; - } else { - tnode[inode].T_req = std::max(constraint + tnode[inode].clock_delay, max_Tarr); - } -#else - /* Don't do the relaxation and always set T_req equal to the "real" required time. */ - tnode[inode].T_req = constraint + tnode[inode].clock_delay; -#endif - - /* Store the largest critical path delay for this constraint (source domain AND sink domain) - in the matrix critical_path_delay. C.P.D. = T_arr at destination - clock skew at destination - = (datapath delay + clock delay to source) - clock delay to destination. - - Critical path delay is really telling us how fast we can run the source clock before we can no - longer meet this constraint. e.g. If the datapath delay is 10 ns, the clock delay at source is - 2 ns and the clock delay at destination is 5 ns, then C.P.D. is 7 ns by the above formula. We - can run the source clock at 7 ns because the clock skew gives us 3 ns extra to meet the 10 ns - datapath delay. */ - - f_timing_stats->cpd[source_clock_domain][sink_clock_domain] = - std::max(f_timing_stats->cpd[source_clock_domain][sink_clock_domain], - (tnode[inode].T_arr - tnode[inode].clock_delay)); - -#ifndef PATH_COUNTING - if (is_prepacked) { - tnode[inode].prepacked_data->num_critical_output_paths = 1; /* Bottom-level tnodes have one locally-critical input path. */ - } -#endif - } else { /* not a sink */ - - assert(!(tnode[inode].type == TN_OUTPAD_SINK || tnode[inode].type == TN_FF_SINK || tnode[inode].type == TN_FF_CLOCK)); - - /* We need to skip this node unless it is on a path from source_clock_domain to - sink_clock_domain. We need to skip all nodes which: - 1. Fan out to the sink domain but do not fan in from the source domain. - 2. Fan in from the source domain but do not fan out to the sink domain. - 3. Do not fan in or out to either domain. - If a node does not fan in from the source domain, it will not have a valid arrival time. - So cases 1 and 3 can be skipped by continuing if T_arr = HUGE_NEGATIVE_FLOAT. We cannot - treat case 2 as simply since the required time for this node has not yet been assigned, - so we have to look at the required time for every node in its immediate fanout instead. */ - - /* Cases 1 and 3 */ - if (tnode[inode].T_arr < HUGE_NEGATIVE_FLOAT + 1) { - continue; /* Skip nodes with unset arrival times. */ - } - - /* Case 2 */ - found = FALSE; - tedge = tnode[inode].out_edges; - for (iedge = 0; iedge < num_edges && !found; iedge++) { - to_node = tedge[iedge].to_node; - if (tnode[to_node].T_req < HUGE_POSITIVE_FLOAT) { - found = TRUE; - } - } - if (!found) { - continue; - } - - /* Now we know this node is on a path from source_clock_domain to - sink_clock_domain, and needs to be analyzed. */ - - /* Opposite to T_arr, set T_req to the MINIMUM of the - required times of all edges fanning OUT from this node. */ - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = tedge[iedge].to_node; - Tdel = tedge[iedge].Tdel; - T_req = tnode[to_node].T_req; - tnode[inode].T_req = std::min(tnode[inode].T_req, T_req - Tdel); - - /* Update least slack per constraint. This is NOT the same as the minimum slack we will - calculate on this traversal for post-packed netlists, which only count inter-cluster - slacks. We only look at edges adjacent to sink nodes on the sink clock domain since - all paths go through one of these edges. */ - if (tnode[to_node].num_edges == 0 && tnode[to_node].clock_domain == sink_clock_domain) { - f_timing_stats->least_slack[source_clock_domain][sink_clock_domain] = - std::min(f_timing_stats->least_slack[source_clock_domain][sink_clock_domain], - (T_req - Tdel - tnode[inode].T_arr)); - } - } -#ifndef PATH_COUNTING - - /* Similar to before, we count how many locally-critical output paths fan out from each tnode, - and also find the maximum number over all tnodes. Unlike for input paths, where we haven't set - the arrival time at to_node before analysing it, here the required time is set at both nodes, - so the "local backward slack" (T_req(to_node) - T_req(inode) - T_del) will never be negative. - Hence, we only have to test if the "local backward slack" is 0. */ - if (is_prepacked) { - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = tedge[iedge].to_node; - /* If the "local backward slack" (T_arr(to_node) - T_arr(inode) - T_del) for this edge - is 0 (i.e. the path from inode to to_node is locally as critical as any other path to - to_node), add to_node's num critical output paths to inode's number. */ - if (fabs(tnode[to_node].T_req - (tnode[inode].T_req + tedge[iedge].Tdel)) < EPSILON) { - tnode[inode].prepacked_data->num_critical_output_paths += tnode[to_node].prepacked_data->num_critical_output_paths; - } - /* Set max_critical_output_paths to the maximum number of critical - output paths for all tnodes analysed on this traversal. */ - if (tnode[to_node].prepacked_data->num_critical_output_paths > max_critical_output_paths) { - max_critical_output_paths = tnode[to_node].prepacked_data->num_critical_output_paths; - } - } - } -#endif - } - } - } - - /* Return max critical input/output paths for this constraint through - the pointers we passed in. */ - if (max_critical_input_paths_ptr && max_critical_output_paths_ptr) { - *max_critical_input_paths_ptr = max_critical_input_paths; - *max_critical_output_paths_ptr = max_critical_output_paths; - } - - if(num_dangling_nodes > 0 && (is_final_analysis || is_prepacked)) { - vpr_printf(TIO_MESSAGE_WARNING, "%d unused pins \n", num_dangling_nodes); - } - - /* The criticality denominator is the maximum of the max - arrival time and the constraint for this domain pair. */ - return std::max(max_Tarr, g_sdc->domain_constraint[source_clock_domain][sink_clock_domain]); -} -#ifdef PATH_COUNTING -static void do_path_counting(float criticality_denom) { - /* Count the importance of the number of paths going through each net - by giving each net a forward and backward path weight. This is the first step of - "A Novel Net Weighting Algorithm for Timing-Driven Placement" (Kong, 2002). - We only visit nodes with set arrival and required times, so this function - must be called after do_timing_analysis_for_constraints, which sets T_arr and T_req. */ - - int inode, num_at_level, i, ilevel, num_edges, iedge, to_node; - t_tedge * tedge; - float forward_local_slack, backward_local_slack, discount; - - /* Reset forward and backward weights for all tnodes. */ - for (inode = 0; inode < num_tnodes; inode++) { - tnode[inode].forward_weight = 0; - tnode[inode].backward_weight = 0; - } - - /* Set foward weights for each top-level tnode. */ - num_at_level = tnodes_at_level[0].nelem; - for (i = 0; i < num_at_level; i++) { - inode = tnodes_at_level[0].list[i]; - tnode[inode].forward_weight = 1.; - } - - /* Do a forward topological traversal to populate forward weights. */ - for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) { - num_at_level = tnodes_at_level[ilevel].nelem; - - for (i = 0; i < num_at_level; i++) { - inode = tnodes_at_level[ilevel].list[i]; - if (!(has_valid_T_arr(inode) && has_valid_T_req(inode))) { - continue; - } - tedge = tnode[inode].out_edges; - num_edges = tnode[inode].num_edges; - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = tedge[iedge].to_node; - if (!(has_valid_T_arr(to_node) && has_valid_T_req(to_node))) { - continue; - } - forward_local_slack = tnode[to_node].T_arr - tnode[inode].T_arr - tedge[iedge].Tdel; - discount = pow((float) DISCOUNT_FUNCTION_BASE, -1 * forward_local_slack / criticality_denom); - tnode[to_node].forward_weight += discount * tnode[inode].forward_weight; - } - } - } - - /* Do a backward topological traversal to populate backward weights. - Since the sinks are all on different levels, we have to check for them as we go. */ - for (ilevel = num_tnode_levels - 1; ilevel >= 0; ilevel--) { - num_at_level = tnodes_at_level[ilevel].nelem; - - for (i = 0; i < num_at_level; i++) { - inode = tnodes_at_level[ilevel].list[i]; - if (!(has_valid_T_arr(inode) && has_valid_T_req(inode))) { - continue; - } - num_edges = tnode[inode].num_edges; - if (num_edges == 0) { /* sink */ - tnode[inode].backward_weight = 1.; - } else { - tedge = tnode[inode].out_edges; - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = tedge[iedge].to_node; - if (!(has_valid_T_arr(to_node) && has_valid_T_req(to_node))) { - continue; - } - backward_local_slack = tnode[to_node].T_req - tnode[inode].T_req - tedge[iedge].Tdel; - discount = pow((float) DISCOUNT_FUNCTION_BASE, -1 * backward_local_slack / criticality_denom); - tnode[inode].backward_weight += discount * tnode[to_node].backward_weight; - } - } - } - } -} -#endif - -static void update_slacks(t_slack * slacks, int source_clock_domain, int sink_clock_domain, float criticality_denom, - boolean update_slack) { - - /* Updates the slack and criticality of each sink pin, or equivalently - each edge, of each net. Go through the list of nets. If the net's - driver tnode has been used, go through each tedge of that tnode and - take the minimum of the slack/criticality for this traversal and the - existing values. Since the criticality_denom can vary greatly between - traversals, we have to update slack and criticality separately. - Only update slack if we need to print it later (update_slack == TRUE). - - Note: there is a correspondence in indexing between out_edges and the - net data structure: out_edges[iedge] = net[inet].node_block[iedge + 1] - There is an offset of 1 because net[inet].node_block includes the driver - node at index 0, while out_edges is part of the driver node and does - not bother to refer to itself. */ - - int inet, iedge, inode, to_node, num_edges; - t_tedge *tedge; - float T_arr, Tdel, T_req, slk, timing_criticality; - - for (inet = 0; inet < num_timing_nets; inet++) { - inode = f_net_to_driver_tnode[inet]; - T_arr = tnode[inode].T_arr; - - if (!(has_valid_T_arr(inode) && has_valid_T_req(inode))) { - continue; /* Only update this net on this traversal if its - driver node has been updated on this traversal. */ - } - - num_edges = tnode[inode].num_edges; - tedge = tnode[inode].out_edges; - - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = tedge[iedge].to_node; - if (!(has_valid_T_arr(to_node) && has_valid_T_req(to_node))) { - continue; /* Only update this edge on this traversal if this - particular sink node has been updated on this traversal. */ - } - Tdel = tedge[iedge].Tdel; - T_req = tnode[to_node].T_req; - - if (update_slack) { - /* Update the slack for this edge. */ - slk = T_req - T_arr - Tdel; - if (slk < slacks->slack[inet][iedge + 1]) { - /* Only update on this traversal if this edge would have - lower slack from this traversal than its current value. */ - slacks->slack[inet][iedge + 1] = slk; - } - } - -#if SLACK_DEFINITION == 'R' - /* Since criticality_denom is not the same on each traversal, - we have to update criticality separately. */ - timing_criticality = 1 - (T_req - T_arr - Tdel)/criticality_denom; - if (timing_criticality > slacks->timing_criticality[inet][iedge + 1]) { - slacks->timing_criticality[inet][iedge + 1] = timing_criticality; - } - #ifdef PATH_COUNTING - /* Also update path criticality separately. Kong uses slack / T_crit for the exponent, - which is equivalent to criticality - 1. Depending on how PATH_COUNTING is defined, - different functional forms are used. */ - #if PATH_COUNTING == 'S' /* Use sum of forward and backward weights. */ - slacks->path_criticality[inet][iedge + 1] = max(slacks->path_criticality[inet][iedge + 1], - (tnode[inode].forward_weight + tnode[to_node].backward_weight) * - pow((float) FINAL_DISCOUNT_FUNCTION_BASE, timing_criticality - 1)); - #elif PATH_COUNTING == 'P' /* Use product of forward and backward weights. */ - slacks->path_criticality[inet][iedge + 1] = max(slacks->path_criticality[inet][iedge + 1], - tnode[inode].forward_weight * tnode[to_node].backward_weight * - pow((float) FINAL_DISCOUNT_FUNCTION_BASE, timing_criticality - 1)); - #elif PATH_COUNTING == 'L' /* Use natural log of product of forward and backward weights. */ - slacks->path_criticality[inet][iedge + 1] = max(slacks->path_criticality[inet][iedge + 1], - log(tnode[inode].forward_weight * tnode[to_node].backward_weight) * - pow((float) FINAL_DISCOUNT_FUNCTION_BASE, timing_criticality - 1)); - #elif PATH_COUNTING == 'R' /* Use product of natural logs of forward and backward weights. */ - slacks->path_criticality[inet][iedge + 1] = max(slacks->path_criticality[inet][iedge + 1], - log(tnode[inode].forward_weight) * log(tnode[to_node].backward_weight) * - pow((float) FINAL_DISCOUNT_FUNCTION_BASE, timing_criticality - 1)); - #endif - #endif -#endif - } - } -} - -void print_lut_remapping(const char *fname) { - FILE *fp; - int inode, i; - t_pb *pb; - - - fp = my_fopen(fname, "w", 0); - fprintf(fp, "# LUT_Name\tinput_pin_mapping\n"); - - for (inode = 0; inode < num_tnodes; inode++) { - /* Print LUT input rebalancing */ - if (tnode[inode].type == TN_PRIMITIVE_OPIN && tnode[inode].pb_graph_pin != NULL) { - pb = block[tnode[inode].block].pb->rr_node_to_pb_mapping[tnode[inode].pb_graph_pin->pin_count_in_cluster]; - if (pb != NULL && pb->lut_pin_remap != NULL) { - assert(pb->pb_graph_node->pb_type->num_output_pins == 1 && pb->pb_graph_node->pb_type->num_clock_pins == 0); /* ensure LUT properties are valid */ - assert(pb->pb_graph_node->num_input_ports == 1); - fprintf(fp, "%s", pb->name); - for (i = 0; i < pb->pb_graph_node->num_input_pins[0]; i++) { - fprintf(fp, "\t%d", pb->lut_pin_remap[i]); - } - fprintf(fp, "\n"); - } - } - } - - fclose(fp); -} - -void print_critical_path(const char *fname) { - - /* Prints the critical path to a file. */ - - t_linked_int *critical_path_head, *critical_path_node; - FILE *fp; - int non_global_nets_on_crit_path, global_nets_on_crit_path; - int tnodes_on_crit_path, inode, iblk, inet; - e_tnode_type type; - float total_net_delay, total_logic_delay, Tdel; - - critical_path_head = allocate_and_load_critical_path(); - critical_path_node = critical_path_head; - - fp = my_fopen(fname, "w", 0); - - non_global_nets_on_crit_path = 0; - global_nets_on_crit_path = 0; - tnodes_on_crit_path = 0; - total_net_delay = 0.; - total_logic_delay = 0.; - - while (critical_path_node != NULL) { - Tdel = print_critical_path_node(fp, critical_path_node); - inode = critical_path_node->data; - type = tnode[inode].type; - tnodes_on_crit_path++; - - if (type == TN_CB_OPIN) { - get_tnode_block_and_output_net(inode, &iblk, &inet); - - if (!timing_nets[inet].is_global) - non_global_nets_on_crit_path++; - else - global_nets_on_crit_path++; - - total_net_delay += Tdel; - } else { - total_logic_delay += Tdel; - } - - critical_path_node = critical_path_node->next; - } - - fprintf(fp, "\nTnodes on critical path: %d Non-global nets on critical path: %d." - "\n", tnodes_on_crit_path, non_global_nets_on_crit_path); - fprintf(fp, "Global nets on critical path: %d.\n", global_nets_on_crit_path); - fprintf(fp, "Total logic delay: %g (s) Total net delay: %g (s)\n", - total_logic_delay, total_net_delay); - - vpr_printf(TIO_MESSAGE_INFO, "Nets on critical path: %d normal, %d global.\n", - non_global_nets_on_crit_path, global_nets_on_crit_path); - - vpr_printf(TIO_MESSAGE_INFO, "Total logic delay: %g (s), total net delay: %g (s)\n", - total_logic_delay, total_net_delay); - - /* Make sure total_logic_delay and total_net_delay add - up to critical path delay,within 5 decimal places. */ - assert(total_logic_delay + total_net_delay - get_critical_path_delay()/1e9 < 1e-5); - - fclose(fp); - free_int_list(&critical_path_head); -} - -t_linked_int * allocate_and_load_critical_path(void) { - - /* Finds the critical path and returns a list of the tnodes on the critical * - * path in a linked list, from the path SOURCE to the path SINK. */ - - t_linked_int *critical_path_head, *curr_crit_node, *prev_crit_node; - int inode, iedge, to_node, num_at_level_zero, i, j, crit_node = OPEN, num_edges; - int source_clock_domain = UNDEFINED, sink_clock_domain = UNDEFINED; - float min_slack = HUGE_POSITIVE_FLOAT, slack; - t_tedge *tedge; - - /* If there's only one clock, we can use the arrival and required times - currently on the timing graph to find the critical path. If there are multiple - clocks, however, the values currently on the timing graph correspond to the - last constraint (pair of clock domains) analysed, which may not be the constraint - with the critical path. In this case, we have to find the constraint with the - least slack and redo the timing analysis for this constraint so we get the right - values onto the timing graph. */ - - if (g_sdc->num_constrained_clocks > 1) { - /* The critical path belongs to the source and sink clock domains - with the least slack. Find these clock domains now. */ - - for (i = 0; i < g_sdc->num_constrained_clocks; i++) { - for (j = 0; j < g_sdc->num_constrained_clocks; j++) { - if (min_slack > f_timing_stats->least_slack[i][j]) { - min_slack = f_timing_stats->least_slack[i][j]; - source_clock_domain = i; - sink_clock_domain = j; - } - } - } - - /* Do a timing analysis for this clock domain pair only. - Set is_prepacked to FALSE since we don't care about the clusterer's normalized values. - Set is_final_analysis to FALSE to get actual, rather than relaxed, slacks. - Set max critical input/output paths to NULL since they aren't used unless is_prepacked is TRUE. */ - do_timing_analysis_for_constraint(source_clock_domain, sink_clock_domain, FALSE, FALSE, (long*)NULL, (long*)NULL); - } - - /* Start at the source (level-0) tnode with the least slack (T_req-T_arr). - This will form the head of our linked list of tnodes on the critical path. */ - min_slack = HUGE_POSITIVE_FLOAT; - num_at_level_zero = tnodes_at_level[0].nelem; - for (i = 0; i < num_at_level_zero; i++) { - inode = tnodes_at_level[0].list[i]; - if (has_valid_T_arr(inode) && has_valid_T_req(inode)) { /* Valid arrival and required times */ - slack = tnode[inode].T_req - tnode[inode].T_arr; - if (slack < min_slack) { - crit_node = inode; - min_slack = slack; - } - } - } - critical_path_head = (t_linked_int *) my_malloc(sizeof(t_linked_int)); - critical_path_head->data = crit_node; - assert(crit_node != OPEN); - prev_crit_node = critical_path_head; - num_edges = tnode[crit_node].num_edges; - - /* Keep adding the tnode in this tnode's fanout which has the least slack - to our critical path linked list, then jump to that tnode and repeat, until - we hit a tnode with no edges, which is the sink of the critical path. */ - while (num_edges != 0) { - curr_crit_node = (t_linked_int *) my_malloc(sizeof(t_linked_int)); - prev_crit_node->next = curr_crit_node; - tedge = tnode[crit_node].out_edges; - min_slack = HUGE_POSITIVE_FLOAT; - - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = tedge[iedge].to_node; - if (has_valid_T_arr(to_node) && has_valid_T_req(to_node)) { /* Valid arrival and required times */ - slack = tnode[to_node].T_req - tnode[to_node].T_arr; - if (slack < min_slack) { - crit_node = to_node; - min_slack = slack; - } - } - } - - curr_crit_node->data = crit_node; - prev_crit_node = curr_crit_node; - num_edges = tnode[crit_node].num_edges; - } - - prev_crit_node->next = NULL; - return (critical_path_head); -} - -void get_tnode_block_and_output_net(int inode, int *iblk_ptr, int *inet_ptr) { - - /* Returns the index of the block that this tnode is part of. If the tnode * - * is a TN_CB_OPIN or TN_INPAD_OPIN (i.e. if it drives a net), the net index is * - * returned via inet_ptr. Otherwise inet_ptr points at OPEN. */ - - int inet, ipin, iblk; - e_tnode_type tnode_type; - - iblk = tnode[inode].block; - tnode_type = tnode[inode].type; - - if (tnode_type == TN_CB_OPIN) { - ipin = tnode[inode].pb_graph_pin->pin_count_in_cluster; - inet = block[iblk].pb->rr_graph[ipin].net_num; - assert(inet != OPEN); - inet = vpack_to_clb_net_mapping[inet]; - } else { - inet = OPEN; - } - - *iblk_ptr = iblk; - *inet_ptr = inet; -} - -void do_constant_net_delay_timing_analysis(t_timing_inf timing_inf, - float constant_net_delay_value) { - - /* Does a timing analysis (simple) where it assumes that each net has a * - * constant delay value. Used only when operation == TIMING_ANALYSIS_ONLY. */ - - /*struct s_linked_vptr *net_delay_chunk_list_head;*/ - - t_chunk net_delay_ch = {NULL, 0, NULL}; - t_slack * slacks = NULL; - float **net_delay = NULL; - - slacks = alloc_and_load_timing_graph(timing_inf); - net_delay = alloc_net_delay(&net_delay_ch, timing_nets, - num_timing_nets); - - load_constant_net_delay(net_delay, constant_net_delay_value, timing_nets, - num_timing_nets); - load_timing_graph_net_delays(net_delay); - - do_timing_analysis(slacks, FALSE, FALSE, TRUE); - - if (getEchoEnabled()) { - if(isEchoFileEnabled(E_ECHO_CRITICAL_PATH)) - print_critical_path("critical_path.echo"); - if(isEchoFileEnabled(E_ECHO_TIMING_GRAPH)) - print_timing_graph(getEchoFileName(E_ECHO_TIMING_GRAPH)); - if(isEchoFileEnabled(E_ECHO_SLACK)) - print_slack(slacks->slack, TRUE, getEchoFileName(E_ECHO_SLACK)); - if(isEchoFileEnabled(E_ECHO_CRITICALITY)) - print_criticality(slacks, TRUE, getEchoFileName(E_ECHO_CRITICALITY)); - if(isEchoFileEnabled(E_ECHO_NET_DELAY)) - print_net_delay(net_delay, getEchoFileName(E_ECHO_NET_DELAY)); - } - - print_timing_stats(); - - free_timing_graph(slacks); - free_net_delay(net_delay, &net_delay_ch); -} -#ifndef PATH_COUNTING -static void update_normalized_costs(float criticality_denom, long max_critical_input_paths, - long max_critical_output_paths) { - int inode; - - /* Update the normalized costs for the clusterer. On each traversal, each cost is - updated for tnodes analysed on this traversal if it would give this tnode a higher - criticality when calculating block criticality for the clusterer. */ - - assert(criticality_denom != 0); /* Possible if timing analysis is being run pre-packing - with all delays set to 0. This is not currently done, - but if you're going to do it, you need to decide how - best to normalize these values to suit your purposes. */ - - for (inode = 0; inode < num_tnodes; inode++) { - /* Only calculate for tnodes which have valid arrival and required times. */ - if (has_valid_T_arr(inode) && has_valid_T_req(inode)) { - tnode[inode].prepacked_data->normalized_slack = std::min(tnode[inode].prepacked_data->normalized_slack, - (tnode[inode].T_req - tnode[inode].T_arr)/criticality_denom); - tnode[inode].prepacked_data->normalized_T_arr = std::max(tnode[inode].prepacked_data->normalized_T_arr, - tnode[inode].T_arr/criticality_denom); - tnode[inode].prepacked_data->normalized_total_critical_paths = std::max(tnode[inode].prepacked_data->normalized_total_critical_paths, - ((float) tnode[inode].prepacked_data->num_critical_input_paths + tnode[inode].prepacked_data->num_critical_output_paths) / - ((float) max_critical_input_paths + max_critical_output_paths)); - } - } -} -#endif -/* Set new arrival time - Special code for LUTs to enable LUT input delay balancing -*/ -static void set_and_balance_arrival_time(int to_node, int from_node, float Tdel, boolean do_lut_input_balancing) { - int i, j; - t_pb *pb; - boolean rebalance; - t_tnode *input_tnode; - - boolean *assigned = NULL; - int fastest_unassigned_pin, most_crit_tnode, most_crit_pin; - float min_delay, highest_T_arr, balanced_T_arr; - - /* Normal case for determining arrival time */ - tnode[to_node].T_arr = std::max(tnode[to_node].T_arr, tnode[from_node].T_arr + Tdel); - - /* Do LUT input rebalancing for LUTs */ - if (do_lut_input_balancing && tnode[to_node].type == TN_PRIMITIVE_OPIN && tnode[to_node].pb_graph_pin != NULL) { - pb = block[tnode[to_node].block].pb->rr_node_to_pb_mapping[tnode[to_node].pb_graph_pin->pin_count_in_cluster]; - if (pb != NULL && pb->lut_pin_remap != NULL) { - /* this is a LUT primitive, do pin swapping */ - assert(pb->pb_graph_node->pb_type->num_output_pins == 1 && pb->pb_graph_node->pb_type->num_clock_pins == 0); /* ensure LUT properties are valid */ - assert(pb->pb_graph_node->num_input_ports == 1); - assert(tnode[from_node].block == tnode[to_node].block); - - /* assign from_node to default location */ - assert(pb->lut_pin_remap[tnode[from_node].pb_graph_pin->pin_number] == OPEN); - pb->lut_pin_remap[tnode[from_node].pb_graph_pin->pin_number] = tnode[from_node].pb_graph_pin->pin_number; - - /* If all input pins are known, perform LUT input delay rebalancing, do nothing otherwise */ - rebalance = TRUE; - for (i = 0; i < pb->pb_graph_node->num_input_pins[0]; i++) { - input_tnode = block[tnode[to_node].block].pb->rr_graph[pb->pb_graph_node->input_pins[0][i].pin_count_in_cluster].tnode; - if (input_tnode != NULL && pb->lut_pin_remap[i] == OPEN) { - rebalance = FALSE; - } - } - if (rebalance == TRUE) { - /* Rebalance LUT inputs so that the most critical paths get the fastest inputs */ - balanced_T_arr = OPEN; - assigned = (boolean*)my_calloc(pb->pb_graph_node->num_input_pins[0], sizeof(boolean)); - /* Clear pin remapping */ - for (i = 0; i < pb->pb_graph_node->num_input_pins[0]; i++) { - pb->lut_pin_remap[i] = OPEN; - } - /* load new T_arr and pin mapping */ - for (i = 0; i < pb->pb_graph_node->num_input_pins[0]; i++) { - /* Find fastest physical input pin of LUT */ - fastest_unassigned_pin = OPEN; - min_delay = OPEN; - for (j = 0; j < pb->pb_graph_node->num_input_pins[0]; j++) { - if (pb->lut_pin_remap[j] == OPEN) { - if (fastest_unassigned_pin == OPEN) { - fastest_unassigned_pin = j; - min_delay = pb->pb_graph_node->input_pins[0][j].pin_timing_del_max[0]; - } else if (min_delay > pb->pb_graph_node->input_pins[0][j].pin_timing_del_max[0]) { - fastest_unassigned_pin = j; - min_delay = pb->pb_graph_node->input_pins[0][j].pin_timing_del_max[0]; - } - } - } - assert(fastest_unassigned_pin != OPEN); - - /* Find most critical LUT input pin in user circuit */ - most_crit_tnode = OPEN; - highest_T_arr = OPEN; - most_crit_pin = OPEN; - for (j = 0; j < pb->pb_graph_node->num_input_pins[0]; j++) { - input_tnode = block[tnode[to_node].block].pb->rr_graph[pb->pb_graph_node->input_pins[0][j].pin_count_in_cluster].tnode; - if (input_tnode != NULL && assigned[j] == FALSE) { - if (most_crit_tnode == OPEN) { - most_crit_tnode = get_tnode_index(input_tnode); - highest_T_arr = input_tnode->T_arr; - most_crit_pin = j; - } else if (highest_T_arr < input_tnode->T_arr) { - most_crit_tnode = get_tnode_index(input_tnode); - highest_T_arr = input_tnode->T_arr; - most_crit_pin = j; - } - } - } - - if (most_crit_tnode == OPEN) { - break; - } else { - assert(tnode[most_crit_tnode].num_edges == 1); - tnode[most_crit_tnode].out_edges[0].Tdel = min_delay; - pb->lut_pin_remap[fastest_unassigned_pin] = most_crit_pin; - assigned[most_crit_pin] = TRUE; - if (balanced_T_arr < min_delay + highest_T_arr) { - balanced_T_arr = min_delay + highest_T_arr; - } - } - } - free(assigned); - if (balanced_T_arr != OPEN) { - tnode[to_node].T_arr = balanced_T_arr; - } - } - } - } -} - -static void load_clock_domain_and_clock_and_io_delay(boolean is_prepacked) { -/* Loads clock domain and clock delay onto TN_FF_SOURCE and TN_FF_SINK tnodes. -The clock domain of each clock is its index in g_sdc->constrained_clocks. -We do this by matching each clock input pad to a constrained clock name, then -propagating forward its domain index to all flip-flops fed by it (TN_FF_CLOCK -tnodes), then later looking up the TN_FF_CLOCK tnode corresponding to every -TN_FF_SOURCE and TN_FF_SINK tnode. We also add up the delays along the clock net -to each TN_FF_CLOCK tnode to give it (and the SOURCE/SINK nodes) a clock delay. - -Also loads input delay/output delay (from set_input_delay or set_output_delay SDC -constraints) onto the tedges between TN_INPAD_SOURCE/OPIN and TN_OUTPAD_IPIN/SINK -tnodes. Finds fanout of each clock domain, including virtual (external) clocks. -Marks unconstrained I/Os with a dummy clock domain (-1). */ - - int i, iclock, inode, num_at_level, clock_index, input_index, output_index; - char * net_name; - t_tnode * clock_node; - - /* Wipe fanout of each clock domain in g_sdc->constrained_clocks. */ - for (iclock = 0; iclock < g_sdc->num_constrained_clocks; iclock++) { - g_sdc->constrained_clocks[iclock].fanout = 0; - } - - /* First, visit all TN_INPAD_SOURCE tnodes */ - num_at_level = tnodes_at_level[0].nelem; /* There are num_at_level top-level tnodes. */ - for (i = 0; i < num_at_level; i++) { - inode = tnodes_at_level[0].list[i]; /* Iterate through each tnode. inode is the index of the tnode in the array tnode. */ - if (tnode[inode].type == TN_INPAD_SOURCE) { /* See if this node is the start of an I/O pad (as oppposed to a flip-flop source). */ - net_name = find_tnode_net_name(inode, is_prepacked); - if ((clock_index = find_clock(net_name)) != -1) { /* We have a clock inpad. */ - /* Set clock skew to 0 at the source and propagate skew - recursively to all connected nodes, adding delay as we go. - Set the clock domain to the index of the clock in the - g_sdc->constrained_clocks array and propagate unchanged. */ - tnode[inode].clock_delay = 0.; - tnode[inode].clock_domain = clock_index; - propagate_clock_domain_and_skew(inode); - - /* Set the clock domain of this clock inpad to -1, so that we do not analyse it. - If we did not do this, the clock net would be analysed on the same iteration of - the timing analyzer as the flip-flops it drives! */ - tnode[inode].clock_domain = -1; - - } else if ((input_index = find_input(net_name)) != -1) { - /* We have a constrained non-clock inpad - find the clock it's constrained on. */ - clock_index = find_clock(g_sdc->constrained_inputs[input_index].clock_name); - assert(clock_index != -1); - /* The clock domain for this input is that of its virtual clock */ - tnode[inode].clock_domain = clock_index; - /* Increment the fanout of this virtual clock domain. */ - g_sdc->constrained_clocks[clock_index].fanout++; - /* Mark input delay specified in SDC file on the timing graph edge leading out from the TN_INPAD_SOURCE node. */ - tnode[inode].out_edges[0].Tdel = g_sdc->constrained_inputs[input_index].delay * 1e-9; /* normalize to be in seconds not ns */ - } else { /* We have an unconstrained input - mark with dummy clock domain and do not analyze. */ - tnode[inode].clock_domain = -1; - } - } - } - - /* Second, visit all TN_OUTPAD_SINK tnodes. Unlike for TN_INPAD_SOURCE tnodes, - we have to search the entire tnode array since these are all on different levels. */ - for (inode = 0; inode < num_tnodes; inode++) { - if (tnode[inode].type == TN_OUTPAD_SINK) { - /* Since the pb_graph_pin of TN_OUTPAD_SINK tnodes points to NULL, we have to find the net - from the pb_graph_pin of the corresponding TN_OUTPAD_IPIN node. - Exploit the fact that the TN_OUTPAD_IPIN node will always be one prior in the tnode array. */ - assert(tnode[inode - 1].type == TN_OUTPAD_IPIN); - net_name = find_tnode_net_name(inode, is_prepacked); - output_index = find_output(net_name + 4); /* the + 4 removes the prefix "out:" automatically prepended to outputs */ - if (output_index != -1) { - /* We have a constrained outpad, find the clock it's constrained on. */ - clock_index = find_clock(g_sdc->constrained_outputs[output_index].clock_name); - assert(clock_index != -1); - /* The clock doain for this output is that of its virtual clock */ - tnode[inode].clock_domain = clock_index; - /* Increment the fanout of this virtual clock domain. */ - g_sdc->constrained_clocks[clock_index].fanout++; - /* Mark output delay specified in SDC file on the timing graph edge leading into the TN_OUTPAD_SINK node. - However, this edge is part of the corresponding TN_OUTPAD_IPIN node. - Exploit the fact that the TN_OUTPAD_IPIN node will always be one prior in the tnode array. */ - tnode[inode - 1].out_edges[0].Tdel = g_sdc->constrained_outputs[output_index].delay * 1e-9; /* normalize to be in seconds not ns */ - - } else { /* We have an unconstrained input - mark with dummy clock domain and do not analyze. */ - tnode[inode].clock_domain = -1; - } - } - } - - /* Third, visit all TN_FF_SOURCE and TN_FF_SINK tnodes, and transfer the clock domain and skew from their corresponding TN_FF_CLOCK tnodes*/ - for (inode = 0; inode < num_tnodes; inode++) { - if (tnode[inode].type == TN_FF_SOURCE || tnode[inode].type == TN_FF_SINK) { - clock_node = find_ff_clock_tnode(inode, is_prepacked); - tnode[inode].clock_domain = clock_node->clock_domain; - tnode[inode].clock_delay = clock_node->clock_delay; - } - } -} - -static void propagate_clock_domain_and_skew(int inode) { -/* Given a tnode indexed by inode (which is part of a clock net), - * propagate forward the clock domain (unchanged) and skew (adding the delay of edges) to all nodes in its fanout. - * We then call recursively on all children in a depth-first search. If num_edges is 0, we should be at an TN_FF_CLOCK tnode; we then set the - * TN_FF_SOURCE and TN_FF_SINK nodes to have the same clock domain and skew as the TN_FF_CLOCK node. We implicitly rely on a tnode not being - * part of two separate clock nets, since undefined behaviour would result if one DFS overwrote the results of another. This may - * be problematic in cases of multiplexed or locally-generated clocks. */ - - int iedge, to_node; - t_tedge * tedge; - - tedge = tnode[inode].out_edges; /* Get the list of edges from the node we're visiting. */ - - if (!tedge) { /* Leaf/sink node; base case of the recursion. */ - assert(tnode[inode].type == TN_FF_CLOCK); - assert(tnode[inode].clock_domain != -1); /* Make sure clock domain is valid. */ - g_sdc->constrained_clocks[tnode[inode].clock_domain].fanout++; - return; - } - - for (iedge = 0; iedge < tnode[inode].num_edges; iedge++) { /* Go through each edge coming out from this tnode */ - to_node = tedge[iedge].to_node; - /* Propagate clock skew forward along this clock net, adding the delay of the wires (edges) of the clock network. */ - tnode[to_node].clock_delay = tnode[inode].clock_delay + tedge[iedge].Tdel; - /* Propagate clock domain forward unchanged */ - tnode[to_node].clock_domain = tnode[inode].clock_domain; - /* Finally, call recursively on the destination tnode. */ - propagate_clock_domain_and_skew(to_node); - } -} - -static char * find_tnode_net_name(int inode, boolean is_prepacked) { - /* Finds the name of the net which a tnode (inode) is on (different for pre-/post-packed netlists). */ - - int logic_block; /* Name chosen not to conflict with the array logical_block */ - char * net_name; - t_pb * physical_block; - t_pb_graph_pin * pb_graph_pin; - - logic_block = tnode[inode].block; - if (is_prepacked) { - net_name = logical_block[logic_block].name; - } else { - physical_block = block[logic_block].pb; - pb_graph_pin = tnode[inode].pb_graph_pin; - net_name = physical_block->rr_node_to_pb_mapping[pb_graph_pin->pin_count_in_cluster]->name; - } - return net_name; -} - -static t_tnode * find_ff_clock_tnode(int inode, boolean is_prepacked) { - /* Finds the TN_FF_CLOCK tnode on the same flipflop as an TN_FF_SOURCE or TN_FF_SINK tnode. */ - - int logic_block; /* Name chosen not to conflict with the array logical_block */ - t_tnode * ff_clock_tnode; - t_rr_node * rr_graph; - t_pb_graph_node * parent_pb_graph_node; - t_pb_graph_pin * ff_source_or_sink_pb_graph_pin, * clock_pb_graph_pin; - - logic_block = tnode[inode].block; - if (is_prepacked) { - ff_clock_tnode = logical_block[logic_block].clock_net_tnode; - } else { - rr_graph = block[logic_block].pb->rr_graph; - ff_source_or_sink_pb_graph_pin = tnode[inode].pb_graph_pin; - parent_pb_graph_node = ff_source_or_sink_pb_graph_pin->parent_node; - /* Make sure there's only one clock port and only one clock pin in that port */ - assert(parent_pb_graph_node->num_clock_ports == 1); - assert(parent_pb_graph_node->num_clock_pins[0] == 1); - clock_pb_graph_pin = &parent_pb_graph_node->clock_pins[0][0]; - ff_clock_tnode = rr_graph[clock_pb_graph_pin->pin_count_in_cluster].tnode; - } - assert(ff_clock_tnode != NULL); - assert(ff_clock_tnode->type == TN_FF_CLOCK); - return ff_clock_tnode; -} - -static int find_clock(char * net_name) { -/* Given a string net_name, find whether it's the name of a clock in the array g_sdc->constrained_clocks. * - * if it is, return the clock's index in g_sdc->constrained_clocks; if it's not, return -1. */ - int index; - for (index = 0; index < g_sdc->num_constrained_clocks; index++) { - if (strcmp(net_name, g_sdc->constrained_clocks[index].name) == 0) { - return index; - } - } - return -1; -} - -static int find_input(char * net_name) { -/* Given a string net_name, find whether it's the name of a constrained input in the array g_sdc->constrained_inputs. * - * if it is, return its index in g_sdc->constrained_inputs; if it's not, return -1. */ - int index; - for (index = 0; index < g_sdc->num_constrained_inputs; index++) { - if (strcmp(net_name, g_sdc->constrained_inputs[index].name) == 0) { - return index; - } - } - return -1; -} - -static int find_output(char * net_name) { -/* Given a string net_name, find whether it's the name of a constrained output in the array g_sdc->constrained_outputs. * - * if it is, return its index in g_sdc->constrained_outputs; if it's not, return -1. */ - int index; - for (index = 0; index < g_sdc->num_constrained_outputs; index++) { - if (strcmp(net_name, g_sdc->constrained_outputs[index].name) == 0) { - return index; - } - } - return -1; -} - -static int find_cf_constraint(char * source_clock_name, char * sink_ff_name) { - /* Given a source clock domain and a sink flip-flop, find out if there's an override constraint between them. - If there is, return the index in g_sdc->cf_constraints; if there is not, return -1. */ - int icf, isource, isink; - - for (icf = 0; icf < g_sdc->num_cf_constraints; icf++) { - for (isource = 0; isource < g_sdc->cf_constraints[icf].num_source; isource++) { - if (strcmp(g_sdc->cf_constraints[icf].source_list[isource], source_clock_name) == 0) { - for (isink = 0; isink < g_sdc->cf_constraints[icf].num_sink; isink++) { - if (strcmp(g_sdc->cf_constraints[icf].sink_list[isink], sink_ff_name) == 0) { - return icf; - } - } - } - } - } - return -1; -} - -static inline int get_tnode_index(t_tnode * node) { - /* Returns the index of pointer_to_tnode in the array tnode [0..num_tnodes - 1] - using pointer arithmetic. */ - return node - tnode; -} - -static inline boolean has_valid_T_arr(int inode) { - /* Has this tnode's arrival time been changed from its original value of HUGE_NEGATIVE_FLOAT? */ - return (boolean) (tnode[inode].T_arr > HUGE_NEGATIVE_FLOAT + 1); -} - -static inline boolean has_valid_T_req(int inode) { - /* Has this tnode's required time been changed from its original value of HUGE_POSITIVE_FLOAT? */ - return (boolean) (tnode[inode].T_req < HUGE_POSITIVE_FLOAT - 1); -} - -#ifndef PATH_COUNTING -boolean has_valid_normalized_T_arr(int inode) { - /* Has this tnode's normalized_T_arr been changed from its original value of HUGE_NEGATIVE_FLOAT? */ - return (boolean) (tnode[inode].prepacked_data->normalized_T_arr > HUGE_NEGATIVE_FLOAT + 1); -} -#endif - -float get_critical_path_delay(void) { - /* Finds the critical path delay, which is the minimum clock period required to meet the constraint - corresponding to the pair of source and sink clock domains with the least slack in the design. */ - - int source_clock_domain, sink_clock_domain; - float least_slack_in_design = HUGE_POSITIVE_FLOAT, critical_path_delay = UNDEFINED; - - if (!g_sdc) return UNDEFINED; /* If timing analysis is off, for instance. */ - - for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - if (least_slack_in_design > f_timing_stats->least_slack[source_clock_domain][sink_clock_domain]) { - least_slack_in_design = f_timing_stats->least_slack[source_clock_domain][sink_clock_domain]; - critical_path_delay = f_timing_stats->cpd[source_clock_domain][sink_clock_domain]; - } - } - } - - return critical_path_delay * 1e9; /* Convert to nanoseconds */ -} - -void print_timing_stats(void) { - - /* Prints critical path delay/fmax, least slack in design, and, for multiple-clock designs, - minimum required clock period to meet each constraint, least slack per constraint, - geometric average clock frequency, and fanout-weighted geometric average clock frequency. */ - - int source_clock_domain, sink_clock_domain, clock_domain, fanout, total_fanout = 0, - num_netlist_clocks_with_intra_domain_paths = 0; - float geomean_period = 1., least_slack_in_design = HUGE_POSITIVE_FLOAT, critical_path_delay = UNDEFINED; - double fanout_weighted_geomean_period = 1.; - boolean found; - - /* Find critical path delay. If the pb_max_internal_delay is greater than this, it becomes - the limiting factor on critical path delay, so print that instead, with a special message. */ - - for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - if (least_slack_in_design > f_timing_stats->least_slack[source_clock_domain][sink_clock_domain]) { - least_slack_in_design = f_timing_stats->least_slack[source_clock_domain][sink_clock_domain]; - critical_path_delay = f_timing_stats->cpd[source_clock_domain][sink_clock_domain]; - } - } - } - - if (pb_max_internal_delay != UNDEFINED && pb_max_internal_delay > critical_path_delay) { - critical_path_delay = pb_max_internal_delay; - vpr_printf(TIO_MESSAGE_INFO, "Final critical path: %g ns\n", 1e9 * critical_path_delay); - vpr_printf(TIO_MESSAGE_INFO, "\t(capped by fmax of block type %s)\n", pbtype_max_internal_delay->name); - - } else { - vpr_printf(TIO_MESSAGE_INFO, "Final critical path: %g ns\n", 1e9 * critical_path_delay); - } - - if (g_sdc->num_constrained_clocks <= 1) { - /* Although critical path delay is always well-defined, it doesn't make sense to talk about fmax for multi-clock circuits */ - vpr_printf(TIO_MESSAGE_INFO, "f_max: %g MHz\n", 1e-6 / critical_path_delay); - } - - /* Also print the least slack in the design */ - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Least slack in design: %g ns\n", 1e9 * least_slack_in_design); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - if (g_sdc->num_constrained_clocks > 1) { /* Multiple-clock design */ - - /* Print minimum possible clock period to meet each constraint. Convert to nanoseconds. */ - - vpr_printf(TIO_MESSAGE_INFO, "Minimum possible clock period to meet each constraint (including skew effects):\n"); - for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { - /* Print the intra-domain constraint if it was analysed. */ - if (g_sdc->domain_constraint[source_clock_domain][source_clock_domain] > NEGATIVE_EPSILON) { - vpr_printf(TIO_MESSAGE_INFO, "%s to %s: %g ns (%g MHz)\n", - g_sdc->constrained_clocks[source_clock_domain].name, - g_sdc->constrained_clocks[source_clock_domain].name, - 1e9 * f_timing_stats->cpd[source_clock_domain][source_clock_domain], - 1e-6 / f_timing_stats->cpd[source_clock_domain][source_clock_domain]); - } else { - vpr_printf(TIO_MESSAGE_INFO, "%s to %s: --\n", - g_sdc->constrained_clocks[source_clock_domain].name, - g_sdc->constrained_clocks[source_clock_domain].name); - } - /* Then, print all other constraints on separate lines, indented. We re-print - the source clock domain's name so there's no ambiguity when parsing. */ - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - if (source_clock_domain == sink_clock_domain) continue; /* already done that */ - if (g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] > NEGATIVE_EPSILON) { - /* If this domain pair was analysed */ - vpr_printf(TIO_MESSAGE_INFO, "\t%s to %s: %g ns (%g MHz)\n", - g_sdc->constrained_clocks[source_clock_domain].name, - g_sdc->constrained_clocks[sink_clock_domain].name, - 1e9 * f_timing_stats->cpd[source_clock_domain][sink_clock_domain], - 1e-6 / f_timing_stats->cpd[source_clock_domain][sink_clock_domain]); - } else { - vpr_printf(TIO_MESSAGE_INFO, "\t%s to %s: --\n", - g_sdc->constrained_clocks[source_clock_domain].name, - g_sdc->constrained_clocks[sink_clock_domain].name); - } - } - } - - /* Print least slack per constraint. */ - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Least slack per constraint:\n"); - for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { - /* Print the intra-domain slack if valid. */ - if (f_timing_stats->least_slack[source_clock_domain][source_clock_domain] < HUGE_POSITIVE_FLOAT - 1) { - vpr_printf(TIO_MESSAGE_INFO, "%s to %s: %g ns\n", - g_sdc->constrained_clocks[source_clock_domain].name, - g_sdc->constrained_clocks[source_clock_domain].name, - 1e9 * f_timing_stats->least_slack[source_clock_domain][source_clock_domain]); - } else { - vpr_printf(TIO_MESSAGE_INFO, "%s to %s: --\n", - g_sdc->constrained_clocks[source_clock_domain].name, - g_sdc->constrained_clocks[source_clock_domain].name); - } - /* Then, print all other slacks on separate lines. */ - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - if (source_clock_domain == sink_clock_domain) continue; /* already done that */ - if (f_timing_stats->least_slack[source_clock_domain][sink_clock_domain] < HUGE_POSITIVE_FLOAT - 1) { - /* If this domain pair was analysed and has a valid slack */ - vpr_printf(TIO_MESSAGE_INFO, "\t%s to %s: %g ns\n", - g_sdc->constrained_clocks[source_clock_domain].name, - g_sdc->constrained_clocks[sink_clock_domain].name, - 1e9 * f_timing_stats->least_slack[source_clock_domain][sink_clock_domain]); - } else { - vpr_printf(TIO_MESSAGE_INFO, "\t%s to %s: --\n", - g_sdc->constrained_clocks[source_clock_domain].name, - g_sdc->constrained_clocks[sink_clock_domain].name); - } - } - } - - /* Calculate geometric mean f_max (fanout-weighted and unweighted) from the diagonal (intra-domain) entries of critical_path_delay, - excluding domains without intra-domain paths (for which the timing constraint is DO_NOT_ANALYSE) and virtual clocks. */ - found = FALSE; - for (clock_domain = 0; clock_domain < g_sdc->num_constrained_clocks; clock_domain++) { - if (g_sdc->domain_constraint[clock_domain][clock_domain] > NEGATIVE_EPSILON && g_sdc->constrained_clocks[clock_domain].is_netlist_clock) { - geomean_period *= f_timing_stats->cpd[clock_domain][clock_domain]; - fanout = g_sdc->constrained_clocks[clock_domain].fanout; - fanout_weighted_geomean_period *= pow((double) f_timing_stats->cpd[clock_domain][clock_domain], fanout); - total_fanout += fanout; - num_netlist_clocks_with_intra_domain_paths++; - found = TRUE; - } - } - if (found) { /* Only print these if we found at least one clock domain with intra-domain paths. */ - geomean_period = pow(geomean_period, (float) 1/num_netlist_clocks_with_intra_domain_paths); - fanout_weighted_geomean_period = pow(fanout_weighted_geomean_period, (double) 1/total_fanout); - /* Convert to MHz */ - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Geometric mean intra-domain period: %g ns (%g MHz)\n", - 1e9 * geomean_period, 1e-6 / geomean_period); - vpr_printf(TIO_MESSAGE_INFO, "Fanout-weighted geomean intra-domain period: %g ns (%g MHz)\n", - 1e9 * fanout_weighted_geomean_period, 1e-6 / fanout_weighted_geomean_period); - } - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - } -} - -static void print_timing_constraint_info(const char *fname) { - /* Prints the contents of g_sdc->domain_constraint, g_sdc->constrained_clocks, constrained_ios and g_sdc->cc_constraints to a file. */ - - FILE * fp; - int source_clock_domain, sink_clock_domain, i, j; - int * clock_name_length = (int *) my_malloc(g_sdc->num_constrained_clocks * sizeof(int)); /* Array of clock name lengths */ - int max_clock_name_length = INT_MIN; - char * clock_name; - - fp = my_fopen(fname, "w", 0); - - /* Get lengths of each clock name and max length so we can space the columns properly. */ - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - clock_name = g_sdc->constrained_clocks[sink_clock_domain].name; - clock_name_length[sink_clock_domain] = strlen(clock_name); - if (clock_name_length[sink_clock_domain] > max_clock_name_length) { - max_clock_name_length = clock_name_length[sink_clock_domain]; - } - } - - /* First, combine info from g_sdc->domain_constraint and g_sdc->constrained_clocks into a matrix - (they're indexed the same as each other). */ - - fprintf(fp, "Timing constraints in ns (source clock domains down left side, sink along top).\n" - "A value of -1.00 means the pair of source and sink domains will not be analysed.\n\n"); - - print_spaces(fp, max_clock_name_length + 4); - - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - fprintf(fp, "%s", g_sdc->constrained_clocks[sink_clock_domain].name); - /* Minimum column width of 8 */ - print_spaces(fp, std::max(8 - clock_name_length[sink_clock_domain], 4)); - } - fprintf(fp, "\n"); - - for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { - fprintf(fp, "%s", g_sdc->constrained_clocks[source_clock_domain].name); - print_spaces(fp, max_clock_name_length + 4 - clock_name_length[source_clock_domain]); - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - fprintf(fp, "%5.2f", g_sdc->domain_constraint[source_clock_domain][sink_clock_domain]); - /* Minimum column width of 8 */ - print_spaces(fp, std::max(clock_name_length[sink_clock_domain] - 1, 3)); - } - fprintf(fp, "\n"); - } - - free(clock_name_length); - - /* Second, print I/O constraints. */ - fprintf(fp, "\nList of constrained inputs (note: constraining a clock net input has no effect):\n"); - for (i = 0; i < g_sdc->num_constrained_inputs; i++) { - fprintf(fp, "Input name %s on clock %s with input delay %.2f ns\n", - g_sdc->constrained_inputs[i].name, g_sdc->constrained_inputs[i].clock_name, g_sdc->constrained_inputs[i].delay); - } - - fprintf(fp, "\nList of constrained outputs:\n"); - for (i = 0; i < g_sdc->num_constrained_outputs; i++) { - fprintf(fp, "Output name %s on clock %s with output delay %.2f ns\n", - g_sdc->constrained_outputs[i].name, g_sdc->constrained_outputs[i].clock_name, g_sdc->constrained_outputs[i].delay); - } - - /* Third, print override constraints. */ - fprintf(fp, "\nList of override constraints (non-default constraints created by set_false_path, set_clock_groups, \nset_max_delay, and set_multicycle_path):\n"); - - for (i = 0; i < g_sdc->num_cc_constraints; i++) { - fprintf(fp, "Clock domain"); - for (j = 0; j < g_sdc->cc_constraints[i].num_source; j++) { - fprintf(fp, " %s,", g_sdc->cc_constraints[i].source_list[j]); - } - fprintf(fp, " to clock domain"); - for (j = 0; j < g_sdc->cc_constraints[i].num_sink - 1; j++) { - fprintf(fp, " %s,", g_sdc->cc_constraints[i].sink_list[j]); - } /* We have to print the last one separately because we don't want a comma after it. */ - if (g_sdc->cc_constraints[i].num_multicycles == 0) { /* not a multicycle constraint */ - fprintf(fp, " %s: %.2f ns\n", g_sdc->cc_constraints[i].sink_list[j], g_sdc->cc_constraints[i].constraint); - } else { /* multicycle constraint */ - fprintf(fp, " %s: %d multicycles\n", g_sdc->cc_constraints[i].sink_list[j], g_sdc->cc_constraints[i].num_multicycles); - } - } - - for (i = 0; i < g_sdc->num_cf_constraints; i++) { - fprintf(fp, "Clock domain"); - for (j = 0; j < g_sdc->cf_constraints[i].num_source; j++) { - fprintf(fp, " %s,", g_sdc->cf_constraints[i].source_list[j]); - } - fprintf(fp, " to flip-flop"); - for (j = 0; j < g_sdc->cf_constraints[i].num_sink - 1; j++) { - fprintf(fp, " %s,", g_sdc->cf_constraints[i].sink_list[j]); - } /* We have to print the last one separately because we don't want a comma after it. */ - if (g_sdc->cf_constraints[i].num_multicycles == 0) { /* not a multicycle constraint */ - fprintf(fp, " %s: %.2f ns\n", g_sdc->cf_constraints[i].sink_list[j], g_sdc->cf_constraints[i].constraint); - } else { /* multicycle constraint */ - fprintf(fp, " %s: %d multicycles\n", g_sdc->cf_constraints[i].sink_list[j], g_sdc->cf_constraints[i].num_multicycles); - } - } - - for (i = 0; i < g_sdc->num_fc_constraints; i++) { - fprintf(fp, "Flip-flop"); - for (j = 0; j < g_sdc->fc_constraints[i].num_source; j++) { - fprintf(fp, " %s,", g_sdc->fc_constraints[i].source_list[j]); - } - fprintf(fp, " to clock domain"); - for (j = 0; j < g_sdc->fc_constraints[i].num_sink - 1; j++) { - fprintf(fp, " %s,", g_sdc->fc_constraints[i].sink_list[j]); - } /* We have to print the last one separately because we don't want a comma after it. */ - if (g_sdc->fc_constraints[i].num_multicycles == 0) { /* not a multicycle constraint */ - fprintf(fp, " %s: %.2f ns\n", g_sdc->fc_constraints[i].sink_list[j], g_sdc->fc_constraints[i].constraint); - } else { /* multicycle constraint */ - fprintf(fp, " %s: %d multicycles\n", g_sdc->fc_constraints[i].sink_list[j], g_sdc->fc_constraints[i].num_multicycles); - } - } - - for (i = 0; i < g_sdc->num_ff_constraints; i++) { - fprintf(fp, "Flip-flop"); - for (j = 0; j < g_sdc->ff_constraints[i].num_source; j++) { - fprintf(fp, " %s,", g_sdc->ff_constraints[i].source_list[j]); - } - fprintf(fp, " to flip-flop"); - for (j = 0; j < g_sdc->ff_constraints[i].num_sink - 1; j++) { - fprintf(fp, " %s,", g_sdc->ff_constraints[i].sink_list[j]); - } /* We have to print the last one separately because we don't want a comma after it. */ - if (g_sdc->ff_constraints[i].num_multicycles == 0) { /* not a multicycle constraint */ - fprintf(fp, " %s: %.2f ns\n", g_sdc->ff_constraints[i].sink_list[j], g_sdc->ff_constraints[i].constraint); - } else { /* multicycle constraint */ - fprintf(fp, " %s: %d multicycles\n", g_sdc->ff_constraints[i].sink_list[j], g_sdc->ff_constraints[i].num_multicycles); - } - } - - fclose(fp); -} - -static void print_spaces(FILE * fp, int num_spaces) { - /* Prints num_spaces spaces to file pointed to by fp. */ - for ( ; num_spaces > 0; num_spaces--) { - fprintf(fp, " "); - } -} - -void print_timing_graph_as_blif (const char *fname, t_model *models) { - struct s_model_ports *port; - struct s_linked_vptr *p_io_removed; - /* Prints out the critical path to a file. */ - - FILE *fp; - int i, j; - - fp = my_fopen(fname, "w", 0); - - fprintf(fp, ".model %s\n", blif_circuit_name); - - fprintf(fp, ".inputs "); - for (i = 0; i < num_logical_blocks; i++) { - if (logical_block[i].type == VPACK_INPAD) { - fprintf(fp, "\\\n%s ", logical_block[i].name); - } - } - p_io_removed = circuit_p_io_removed; - while (p_io_removed) { - fprintf(fp, "\\\n%s ", (char *) p_io_removed->data_vptr); - p_io_removed = p_io_removed->next; - } - - fprintf(fp, "\n"); - - fprintf(fp, ".outputs "); - for (i = 0; i < num_logical_blocks; i++) { - if (logical_block[i].type == VPACK_OUTPAD) { - /* Outputs have a "out:" prepended to them, must remove */ - fprintf(fp, "\\\n%s ", &logical_block[i].name[4]); - } - } - fprintf(fp, "\n"); - fprintf(fp, ".names unconn\n"); - fprintf(fp, " 0\n\n"); - - /* Print out primitives */ - for (i = 0; i < num_logical_blocks; i++) { - print_primitive_as_blif (fp, i); - } - - /* Print out tnode connections */ - for (i = 0; i < num_tnodes; i++) { - if (tnode[i].type != TN_PRIMITIVE_IPIN && tnode[i].type != TN_FF_SOURCE - && tnode[i].type != TN_INPAD_SOURCE - && tnode[i].type != TN_OUTPAD_IPIN) { - for (j = 0; j < tnode[i].num_edges; j++) { - fprintf(fp, ".names tnode_%d tnode_%d\n", i, - tnode[i].out_edges[j].to_node); - fprintf(fp, "1 1\n\n"); - } - } - } - - fprintf(fp, ".end\n\n"); - - /* Print out .subckt models */ - while (models) { - fprintf(fp, ".model %s\n", models->name); - fprintf(fp, ".inputs "); - port = models->inputs; - while (port) { - if (port->size > 1) { - for (j = 0; j < port->size; j++) { - fprintf(fp, "%s[%d] ", port->name, j); - } - } else { - fprintf(fp, "%s ", port->name); - } - port = port->next; - } - fprintf(fp, "\n"); - fprintf(fp, ".outputs "); - port = models->outputs; - while (port) { - if (port->size > 1) { - for (j = 0; j < port->size; j++) { - fprintf(fp, "%s[%d] ", port->name, j); - } - } else { - fprintf(fp, "%s ", port->name); - } - port = port->next; - } - fprintf(fp, "\n.blackbox\n.end\n\n"); - fprintf(fp, "\n\n"); - models = models->next; - } - fclose(fp); -} - -static void print_primitive_as_blif (FILE *fpout, int iblk) { - int i, j; - struct s_model_ports *port; - struct s_linked_vptr *truth_table; - t_rr_node *irr_graph; - t_pb_graph_node *pb_graph_node; - int node; - - /* Print primitives found in timing graph in blif format based on whether this is a logical primitive or a physical primitive */ - - if (logical_block[iblk].type == VPACK_INPAD) { - if (logical_block[iblk].pb == NULL) { - fprintf(fpout, ".names %s tnode_%d\n", logical_block[iblk].name, - get_tnode_index(logical_block[iblk].output_net_tnodes[0][0])); - } else { - fprintf(fpout, ".names %s tnode_%d\n", logical_block[iblk].name, - get_tnode_index(logical_block[iblk].pb->rr_graph[logical_block[iblk].pb->pb_graph_node->output_pins[0][0].pin_count_in_cluster].tnode)); - } - fprintf(fpout, "1 1\n\n"); - } else if (logical_block[iblk].type == VPACK_OUTPAD) { - /* outputs have the symbol out: automatically prepended to it, must remove */ - if (logical_block[iblk].pb == NULL) { - fprintf(fpout, ".names tnode_%d %s\n", - get_tnode_index(logical_block[iblk].input_net_tnodes[0][0]), - &logical_block[iblk].name[4]); - } else { - /* avoid the out: from output pad naming */ - fprintf(fpout, ".names tnode_%d %s\n", - get_tnode_index(logical_block[iblk].pb->rr_graph[logical_block[iblk].pb->pb_graph_node->input_pins[0][0].pin_count_in_cluster].tnode), - (logical_block[iblk].name + 4)); - } - fprintf(fpout, "1 1\n\n"); - } else if (strcmp(logical_block[iblk].model->name, "latch") == 0) { - fprintf(fpout, ".latch "); - node = OPEN; - - if (logical_block[iblk].pb == NULL) { - i = 0; - port = logical_block[iblk].model->inputs; - while (port) { - if (!port->is_clock) { - assert(port->size == 1); - for (j = 0; j < port->size; j++) { - if (logical_block[iblk].input_net_tnodes[i][j] != NULL) { - fprintf(fpout, "tnode_%d ", - get_tnode_index(logical_block[iblk].input_net_tnodes[i][j])); - } else { - assert(0); - } - } - i++; - } - port = port->next; - } - assert(i == 1); - - i = 0; - port = logical_block[iblk].model->outputs; - while (port) { - assert(port->size == 1); - for (j = 0; j < port->size; j++) { - if (logical_block[iblk].output_net_tnodes[i][j] != NULL) { - node = - get_tnode_index(logical_block[iblk].output_net_tnodes[i][j]); - fprintf(fpout, "latch_%s re ", - logical_block[iblk].name); - } else { - assert(0); - } - } - i++; - port = port->next; - } - assert(i == 1); - - i = 0; - port = logical_block[iblk].model->inputs; - while (port) { - if (port->is_clock) { - for (j = 0; j < port->size; j++) { - if (logical_block[iblk].clock_net_tnode != NULL) { - fprintf(fpout, "tnode_%d 0\n\n", - get_tnode_index(logical_block[iblk].clock_net_tnode)); - } else { - assert(0); - } - } - i++; - } - port = port->next; - } - assert(i == 1); - } else { - irr_graph = logical_block[iblk].pb->rr_graph; - assert( - irr_graph[logical_block[iblk].pb->pb_graph_node->input_pins[0][0].pin_count_in_cluster].net_num != OPEN); - fprintf(fpout, "tnode_%d ", - get_tnode_index(irr_graph[logical_block[iblk].pb->pb_graph_node->input_pins[0][0].pin_count_in_cluster].tnode)); - node = - get_tnode_index(irr_graph[logical_block[iblk].pb->pb_graph_node->output_pins[0][0].pin_count_in_cluster].tnode); - fprintf(fpout, "latch_%s re ", logical_block[iblk].name); - assert( - irr_graph[logical_block[iblk].pb->pb_graph_node->clock_pins[0][0].pin_count_in_cluster].net_num != OPEN); - fprintf(fpout, "tnode_%d 0\n\n", - get_tnode_index(irr_graph[logical_block[iblk].pb->pb_graph_node->clock_pins[0][0].pin_count_in_cluster].tnode)); - } - assert(node != OPEN); - fprintf(fpout, ".names latch_%s tnode_%d\n", logical_block[iblk].name, - node); - fprintf(fpout, "1 1\n\n"); - } else if (strcmp(logical_block[iblk].model->name, "names") == 0) { - fprintf(fpout, ".names "); - node = OPEN; - - if (logical_block[iblk].pb == NULL) { - i = 0; - port = logical_block[iblk].model->inputs; - while (port) { - assert(!port->is_clock); - for (j = 0; j < port->size; j++) { - if (logical_block[iblk].input_net_tnodes[i][j] != NULL) { - fprintf(fpout, "tnode_%d ", - get_tnode_index(logical_block[iblk].input_net_tnodes[i][j])); - } else { - break; - } - } - i++; - port = port->next; - } - assert(i == 1); - - i = 0; - port = logical_block[iblk].model->outputs; - while (port) { - assert(port->size == 1); - fprintf(fpout, "lut_%s\n", logical_block[iblk].name); - node = get_tnode_index(logical_block[iblk].output_net_tnodes[0][0]); - assert(node != OPEN); - i++; - port = port->next; - } - assert(i == 1); - } else { - irr_graph = logical_block[iblk].pb->rr_graph; - assert(logical_block[iblk].pb->pb_graph_node->num_input_ports == 1); - for (i = 0; - i < logical_block[iblk].pb->pb_graph_node->num_input_pins[0]; - i++) { - if(logical_block[iblk].input_nets[0][i] != OPEN) { - for (j = 0; j < logical_block[iblk].pb->pb_graph_node->num_input_pins[0]; j++) { - if (irr_graph[logical_block[iblk].pb->pb_graph_node->input_pins[0][j].pin_count_in_cluster].net_num - != OPEN) { - if (irr_graph[logical_block[iblk].pb->pb_graph_node->input_pins[0][j].pin_count_in_cluster].net_num == logical_block[iblk].input_nets[0][i]) { - fprintf(fpout, "tnode_%d ", - get_tnode_index(irr_graph[logical_block[iblk].pb->pb_graph_node->input_pins[0][j].pin_count_in_cluster].tnode)); - break; - } - } - } - assert(j < logical_block[iblk].pb->pb_graph_node->num_input_pins[0]); - } - } - assert( - logical_block[iblk].pb->pb_graph_node->num_output_ports == 1); - assert( - logical_block[iblk].pb->pb_graph_node->num_output_pins[0] == 1); - fprintf(fpout, "lut_%s\n", logical_block[iblk].name); - node = - get_tnode_index(irr_graph[logical_block[iblk].pb->pb_graph_node->output_pins[0][0].pin_count_in_cluster].tnode); - } - assert(node != OPEN); - truth_table = logical_block[iblk].truth_table; - while (truth_table) { - fprintf(fpout, "%s\n", (char*) truth_table->data_vptr); - truth_table = truth_table->next; - } - fprintf(fpout, "\n"); - fprintf(fpout, ".names lut_%s tnode_%d\n", logical_block[iblk].name, - node); - fprintf(fpout, "1 1\n\n"); - } else { - /* This is a standard .subckt blif structure */ - fprintf(fpout, ".subckt %s ", logical_block[iblk].model->name); - if (logical_block[iblk].pb == NULL) { - i = 0; - port = logical_block[iblk].model->inputs; - while (port) { - if (!port->is_clock) { - for (j = 0; j < port->size; j++) { - if (logical_block[iblk].input_net_tnodes[i][j] != NULL) { - if (port->size > 1) { - fprintf(fpout, "\\\n%s[%d]=tnode_%d ", - port->name, j, - get_tnode_index(logical_block[iblk].input_net_tnodes[i][j])); - } else { - fprintf(fpout, "\\\n%s=tnode_%d ", port->name, - get_tnode_index(logical_block[iblk].input_net_tnodes[i][j])); - } - } else { - if (port->size > 1) { - fprintf(fpout, "\\\n%s[%d]=unconn ", port->name, - j); - } else { - fprintf(fpout, "\\\n%s=unconn ", port->name); - } - } - } - i++; - } - port = port->next; - } - - i = 0; - port = logical_block[iblk].model->outputs; - while (port) { - for (j = 0; j < port->size; j++) { - if (logical_block[iblk].output_net_tnodes[i][j] != NULL) { - if (port->size > 1) { - fprintf(fpout, "\\\n%s[%d]=%s ", port->name, j, - vpack_net[logical_block[iblk].output_nets[i][j]].name); - } else { - fprintf(fpout, "\\\n%s=%s ", port->name, - vpack_net[logical_block[iblk].output_nets[i][j]].name); - } - } else { - if (port->size > 1) { - fprintf(fpout, "\\\n%s[%d]=unconn_%d_%s_%d ", - port->name, j, iblk, port->name, j); - } else { - fprintf(fpout, "\\\n%s=unconn_%d_%s ", port->name, - iblk, port->name); - } - } - } - i++; - port = port->next; - } - - i = 0; - port = logical_block[iblk].model->inputs; - while (port) { - if (port->is_clock) { - assert(port->size == 1); - if (logical_block[iblk].clock_net_tnode != NULL) { - fprintf(fpout, "\\\n%s=tnode_%d ", port->name, - get_tnode_index(logical_block[iblk].clock_net_tnode)); - } else { - fprintf(fpout, "\\\n%s=unconn ", port->name); - } - i++; - } - port = port->next; - } - - fprintf(fpout, "\n\n"); - - i = 0; - port = logical_block[iblk].model->outputs; - while (port) { - for (j = 0; j < port->size; j++) { - if (logical_block[iblk].output_net_tnodes[i][j] != NULL) { - fprintf(fpout, ".names %s tnode_%d\n", - vpack_net[logical_block[iblk].output_nets[i][j]].name, - get_tnode_index(logical_block[iblk].output_net_tnodes[i][j])); - fprintf(fpout, "1 1\n\n"); - } - } - i++; - port = port->next; - } - } else { - irr_graph = logical_block[iblk].pb->rr_graph; - pb_graph_node = logical_block[iblk].pb->pb_graph_node; - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - if (irr_graph[pb_graph_node->input_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - if (pb_graph_node->num_input_pins[i] > 1) { - fprintf(fpout, "\\\n%s[%d]=tnode_%d ", - pb_graph_node->input_pins[i][j].port->name, - j, - get_tnode_index(irr_graph[pb_graph_node->input_pins[i][j].pin_count_in_cluster].tnode)); - } else { - fprintf(fpout, "\\\n%s=tnode_%d ", - pb_graph_node->input_pins[i][j].port->name, - get_tnode_index(irr_graph[pb_graph_node->input_pins[i][j].pin_count_in_cluster].tnode)); - } - } else { - if (pb_graph_node->num_input_pins[i] > 1) { - fprintf(fpout, "\\\n%s[%d]=unconn ", - pb_graph_node->input_pins[i][j].port->name, - j); - } else { - fprintf(fpout, "\\\n%s=unconn ", - pb_graph_node->input_pins[i][j].port->name); - } - } - } - } - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - if (irr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - if (pb_graph_node->num_output_pins[i] > 1) { - fprintf(fpout, "\\\n%s[%d]=%s ", - pb_graph_node->output_pins[i][j].port->name, - j, - vpack_net[irr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster].net_num].name); - } else { - char* port_name = - pb_graph_node->output_pins[i][j].port->name; - int pin_count = - pb_graph_node->output_pins[i][j].pin_count_in_cluster; - int node_index = irr_graph[pin_count].net_num; - char* node_name = vpack_net[node_index].name; - fprintf(fpout, "\\\n%s=%s ", port_name, node_name); - } - } else { - if (pb_graph_node->num_output_pins[i] > 1) { - fprintf(fpout, "\\\n%s[%d]=unconn ", - pb_graph_node->output_pins[i][j].port->name, - j); - } else { - fprintf(fpout, "\\\n%s=unconn ", - pb_graph_node->output_pins[i][j].port->name); - } - } - } - } - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - if (irr_graph[pb_graph_node->clock_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - if (pb_graph_node->num_clock_pins[i] > 1) { - fprintf(fpout, "\\\n%s[%d]=tnode_%d ", - pb_graph_node->clock_pins[i][j].port->name, - j, - get_tnode_index(irr_graph[pb_graph_node->clock_pins[i][j].pin_count_in_cluster].tnode)); - } else { - fprintf(fpout, "\\\n%s=tnode_%d ", - pb_graph_node->clock_pins[i][j].port->name, - get_tnode_index(irr_graph[pb_graph_node->clock_pins[i][j].pin_count_in_cluster].tnode)); - } - } else { - if (pb_graph_node->num_clock_pins[i] > 1) { - fprintf(fpout, "\\\n%s[%d]=unconn ", - pb_graph_node->clock_pins[i][j].port->name, - j); - } else { - fprintf(fpout, "\\\n%s=unconn ", - pb_graph_node->clock_pins[i][j].port->name); - } - } - } - } - - fprintf(fpout, "\n\n"); - /* connect up output port names to output tnodes */ - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - if (irr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster].net_num - != OPEN) { - fprintf(fpout, ".names %s tnode_%d\n", - vpack_net[irr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster].net_num].name, - get_tnode_index(irr_graph[pb_graph_node->output_pins[i][j].pin_count_in_cluster].tnode)); - fprintf(fpout, "1 1\n\n"); - } - } - } - } - } -} diff --git a/vpr7_x2p/vpr/SRC/timing/path_delay.h b/vpr7_x2p/vpr/SRC/timing/path_delay.h deleted file mode 100755 index 2870b6f8e..000000000 --- a/vpr7_x2p/vpr/SRC/timing/path_delay.h +++ /dev/null @@ -1,96 +0,0 @@ -#ifndef PATH_DELAY -#define PATH_DELAY - -#define DO_NOT_ANALYSE -1 - -/*********************** Defines for timing options *******************************/ - -#define SLACK_DEFINITION 'R' -/* Choose how to normalize negative slacks for the optimizers (not in the final timing analysis for output statistics): - 'R' (T_req-relaxed): For each constraint, set the required time at sink nodes to the max of the true required time - (constraint + tnode[inode].clock_skew) and the max arrival time. This means that the required time is "relaxed" - to the max arrival time for tight constraints which would otherwise give negative slack. - Criticalities are computed once per constraint, using a criticality denominator unique to that constraint - (maximum of the constraint and the max arrival time). - 'S' (Shifted): After all slacks are computed, increase the value of all slacks by the largest negative slack, - if it exists. Equivalent to 'R' for single-clock cases. - Criticalities are computed once per timing analysis, using a single criticality denominator for all constraints - (maximum of all constraints and all required times). - This can give unusual results with multiple, very dissimilar constraints. -*/ - -#ifdef PATH_COUNTING /* Path counting options: */ - #define DISCOUNT_FUNCTION_BASE 100 - /* The base of the exponential discount function used to calculate - forward and backward path weights. Higher values discount paths - with higher slacks more greatly. */ - - #define FINAL_DISCOUNT_FUNCTION_BASE DISCOUNT_FUNCTION_BASE - /* The base of the exponential disount function used to calculate - path criticality from forward and backward weights. Higher values - discount paths with higher slacks more greatly. By default, this - is the same as the original discount function base. */ - - #define PACK_PATH_WEIGHT 1 - #define TIMING_GAIN_PATH_WEIGHT PACK_PATH_WEIGHT - #define PLACE_PATH_WEIGHT 0 - #define ROUTE_PATH_WEIGHT 0 - /* The percentage of total criticality taken from path criticality - as opposed to timing criticality. A value of 0 uses only timing - criticality; a value of 1 uses only path criticality. */ -#endif - -/*************************** Function declarations ********************************/ - -t_slack * alloc_and_load_timing_graph(t_timing_inf timing_inf); - -t_slack * alloc_and_load_pre_packing_timing_graph(float block_delay, - float inter_cluster_net_delay, t_model *models, t_timing_inf timing_inf); - -t_linked_int *allocate_and_load_critical_path(void); - -void load_timing_graph_net_delays(float **net_delay); - -void do_timing_analysis(t_slack * slacks, boolean is_prepacked, boolean do_lut_input_balancing, boolean is_final_analysis); - -void free_timing_graph(t_slack * slack); - -void free_timing_stats(void); - -void print_timing_graph(const char *fname); - -void print_lut_remapping(const char *fname); - -void print_slack(float ** slack, boolean slack_is_normalized, const char *fname); - -void print_criticality(t_slack * slacks, boolean criticality_is_normalized, const char *fname); - -void print_net_delay(float **net_delay, const char *fname); - -#ifdef PATH_COUNTING -void print_path_criticality(float ** path_criticality, const char *fname); -#else -void print_clustering_timing_info(const char *fname); - -boolean has_valid_normalized_T_arr(int inode); -#endif - -void print_timing_stats(void); - -float get_critical_path_delay(void); - -void print_critical_path(const char *fname); - -void get_tnode_block_and_output_net(int inode, int *iblk_ptr, int *inet_ptr); - -void do_constant_net_delay_timing_analysis(t_timing_inf timing_inf, - float constant_net_delay_value); - -void print_timing_graph_as_blif (const char *fname, t_model *models); - -/*************************** Variable declarations ********************************/ - -extern int num_tnodes; /* Number of nodes (pins) in the timing graph */ -extern t_tnode *tnode; /* [0..num_tnodes - 1] nodes in the timing graph */ - -#endif diff --git a/vpr7_x2p/vpr/SRC/timing/path_delay2.c b/vpr7_x2p/vpr/SRC/timing/path_delay2.c deleted file mode 100755 index ea7374b0b..000000000 --- a/vpr7_x2p/vpr/SRC/timing/path_delay2.c +++ /dev/null @@ -1,293 +0,0 @@ -#include -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "path_delay2.h" -#include "read_xml_arch_file.h" - -/************* Variables (globals) shared by all path_delay modules **********/ - -int num_tnode_levels; /* Number of levels in the timing graph. */ - -struct s_ivec *tnodes_at_level; -/* [0..num__tnode_levels - 1]. Count and list of tnodes at each level of - * the timing graph, to make topological searches easier. Level-0 nodes are - * sources to the timing graph (types TN_FF_SOURCE, TN_INPAD_SOURCE - * and TN_CONSTANT_GEN_SOURCE). Level-N nodes are in the immediate fanout of - * nodes with level at most N-1. */ - -/******************* Subroutines local to this module ************************/ - -static int *alloc_and_load_tnode_fanin_and_check_edges(int *num_sinks_ptr); -static void show_combinational_cycle_candidates(); - -/************************** Subroutine definitions ***************************/ - -static int * -alloc_and_load_tnode_fanin_and_check_edges(int *num_sinks_ptr) { - - /* Allocates an array and fills it with the number of in-edges (inputs) to * - * each tnode. While doing this it also checks that each edge in the timing * - * graph points to a valid tnode. Also counts the number of sinks. */ - - int inode, iedge, to_node, num_edges, error, num_sinks; - int *tnode_num_fanin; - t_tedge *tedge; - - tnode_num_fanin = (int *) my_calloc(num_tnodes, sizeof(int)); - error = 0; - num_sinks = 0; - - for (inode = 0; inode < num_tnodes; inode++) { - num_edges = tnode[inode].num_edges; - - if (num_edges > 0) { - tedge = tnode[inode].out_edges; - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = tedge[iedge].to_node; - if (to_node < 0 || to_node >= num_tnodes) { - vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_tnode_fanin_and_check_edges:\n"); - vpr_printf(TIO_MESSAGE_ERROR, "\ttnode #%d edge #%d goes to illegal node #%d.\n", - inode, iedge, to_node); - error++; - } - - tnode_num_fanin[to_node]++; - } - } - - else if (num_edges == 0) { - num_sinks++; - } - - else { - vpr_printf(TIO_MESSAGE_ERROR, "in alloc_and_load_tnode_fanin_and_check_edges:\n"); - vpr_printf(TIO_MESSAGE_ERROR, "\ttnode #%d has %d edges.\n", - inode, num_edges); - error++; - } - - } - - if (error != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "Found %d Errors in the timing graph. Aborting.\n", error); - exit(1); - } - - *num_sinks_ptr = num_sinks; - return (tnode_num_fanin); -} - -int alloc_and_load_timing_graph_levels(void) { - - /* Does a breadth-first search through the timing graph in order to levelize * - * it. This allows subsequent traversals to be done topologically for speed. * - * Also returns the number of sinks in the graph (nodes with no fanout). */ - - t_linked_int *free_list_head, *nodes_at_level_head; - int inode, num_at_level, iedge, to_node, num_edges, num_sinks, num_levels, - i; - t_tedge *tedge; - - /* [0..num_tnodes-1]. # of in-edges to each tnode that have not yet been * - * seen in this traversal. */ - - int *tnode_fanin_left; - - tnode_fanin_left = alloc_and_load_tnode_fanin_and_check_edges(&num_sinks); - - free_list_head = NULL; - nodes_at_level_head = NULL; - - /* Very conservative -> max number of levels = num_tnodes. Realloc later. * - * Temporarily need one extra level on the end because I look at the first * - * empty level. */ - - tnodes_at_level = (struct s_ivec *) my_malloc( - (num_tnodes + 1) * sizeof(struct s_ivec)); - - /* Scan through the timing graph, putting all the primary input nodes (no * - * fanin) into level 0 of the level structure. */ - - num_at_level = 0; - - for (inode = 0; inode < num_tnodes; inode++) { - if (tnode_fanin_left[inode] == 0) { - num_at_level++; - nodes_at_level_head = insert_in_int_list(nodes_at_level_head, inode, - &free_list_head); - } - } - - alloc_ivector_and_copy_int_list(&nodes_at_level_head, num_at_level, - &tnodes_at_level[0], &free_list_head); - - num_levels = 0; - - while (num_at_level != 0) { /* Until there's nothing in the queue. */ - num_levels++; - num_at_level = 0; - - for (i = 0; i < tnodes_at_level[num_levels - 1].nelem; i++) { - inode = tnodes_at_level[num_levels - 1].list[i]; - tedge = tnode[inode].out_edges; - num_edges = tnode[inode].num_edges; - - for (iedge = 0; iedge < num_edges; iedge++) { - to_node = tedge[iedge].to_node; - tnode_fanin_left[to_node]--; - - if (tnode_fanin_left[to_node] == 0) { - num_at_level++; - nodes_at_level_head = insert_in_int_list( - nodes_at_level_head, to_node, &free_list_head); - } - } - } - - alloc_ivector_and_copy_int_list(&nodes_at_level_head, num_at_level, - &tnodes_at_level[num_levels], &free_list_head); - } - - tnodes_at_level = (struct s_ivec *) my_realloc(tnodes_at_level, - num_levels * sizeof(struct s_ivec)); - num_tnode_levels = num_levels; - - free(tnode_fanin_left); - free_int_list(&free_list_head); - return (num_sinks); -} - -void check_timing_graph(int num_sinks) { - - /* Checks the timing graph to see that: (1) all the tnodes have been put * - * into some level of the timing graph; */ - - /* Addition error checks that need to be done but not yet implemented: (2) the number of primary inputs * - * to the timing graph is equal to the number of input pads + the number of * - * constant generators; and (3) the number of sinks (nodes with no fanout) * - * equals the number of output pads + the number of flip flops. */ - - int num_tnodes_check, ilevel, error; - - error = 0; - num_tnodes_check = 0; - - /* TODO: Rework error checks for I/Os*/ - - for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) - num_tnodes_check += tnodes_at_level[ilevel].nelem; - - if (num_tnodes_check != num_tnodes) { - vpr_printf(TIO_MESSAGE_ERROR, "Error in check_timing_graph: %d tnodes appear in the tnode level structure. Expected %d.\n", - num_tnodes_check, num_tnodes); - vpr_printf(TIO_MESSAGE_INFO, "Check the netlist for combinational cycles.\n"); - if (num_tnodes > num_tnodes_check) { - show_combinational_cycle_candidates(); - } - error++; - } - /* Todo: Add error checks that # of flip-flops, memories, and other - black boxes match # of sinks/sources*/ - - if (error != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "Found %d Errors in the timing graph. Aborting.\n", error); - exit(1); - } -} - -float print_critical_path_node(FILE * fp, t_linked_int * critical_path_node) { - - /* Prints one tnode on the critical path out to fp. Returns the delay to the next node. */ - - int inode, iblk, inet, downstream_node; - t_pb_graph_pin * pb_graph_pin; - e_tnode_type type; - static const char *tnode_type_names[] = { "TN_INPAD_SOURCE", "TN_INPAD_OPIN", - "TN_OUTPAD_IPIN", "TN_OUTPAD_SINK", "TN_CB_IPIN", "TN_CB_OPIN", - "TN_INTERMEDIATE_NODE", "TN_PRIMITIVE_IPIN", "TN_PRIMITIVE_OPIN", "TN_FF_IPIN", - "TN_FF_OPIN", "TN_FF_SINK", "TN_FF_SOURCE", "TN_FF_CLOCK", "TN_CONSTANT_GEN_SOURCE" }; - - t_linked_int *next_crit_node; - float Tdel; - - inode = critical_path_node->data; - type = tnode[inode].type; - iblk = tnode[inode].block; - pb_graph_pin = tnode[inode].pb_graph_pin; - - fprintf(fp, "Node: %d %s Block #%d (%s)\n", inode, tnode_type_names[type], - iblk, block[iblk].name); - - if (pb_graph_pin == NULL) { - assert( - type == TN_INPAD_SOURCE || type == TN_OUTPAD_SINK || type == TN_FF_SOURCE || type == TN_FF_SINK); - } - - if (pb_graph_pin != NULL) { - fprintf(fp, "Pin: %s.%s[%d] pb (%s)", pb_graph_pin->parent_node->pb_type->name, - pb_graph_pin->port->name, pb_graph_pin->pin_number, block[iblk].pb->rr_node_to_pb_mapping[pb_graph_pin->pin_count_in_cluster]->name); - } - if (type != TN_INPAD_SOURCE && type != TN_OUTPAD_SINK) { - fprintf(fp, "\n"); - } - - fprintf(fp, "T_arr: %g T_req: %g ", tnode[inode].T_arr, - tnode[inode].T_req); - - next_crit_node = critical_path_node->next; - if (next_crit_node != NULL) { - downstream_node = next_crit_node->data; - Tdel = tnode[downstream_node].T_arr - tnode[inode].T_arr; - fprintf(fp, "Tdel: %g\n", Tdel); - } else { /* last node, no Tdel. */ - Tdel = 0.; - fprintf(fp, "\n"); - } - - if (type == TN_CB_OPIN) { - inet = - block[iblk].pb->rr_graph[pb_graph_pin->pin_count_in_cluster].net_num; - inet = vpack_to_clb_net_mapping[inet]; - fprintf(fp, "External-to-Block Net: #%d (%s). Pins on net: %d.\n", - inet, clb_net[inet].name, (clb_net[inet].num_sinks + 1)); - } else if (pb_graph_pin != NULL) { - inet = - block[iblk].pb->rr_graph[pb_graph_pin->pin_count_in_cluster].net_num; - fprintf(fp, "Internal Net: #%d (%s). Pins on net: %d.\n", inet, - vpack_net[inet].name, (vpack_net[inet].num_sinks + 1)); - } - - fprintf(fp, "\n"); - return (Tdel); -} - -/* Display nodes that are likely in combinational cycles */ -static void show_combinational_cycle_candidates() { - boolean *found_tnode; - int ilevel, i, inode; - - found_tnode = (boolean*) my_calloc(num_tnodes, sizeof(boolean)); - - for (ilevel = 0; ilevel < num_tnode_levels; ilevel++) { - for (i = 0; i < tnodes_at_level[ilevel].nelem; i++) { - inode = tnodes_at_level[ilevel].list[i]; - found_tnode[inode] = TRUE; - } - } - - vpr_printf(TIO_MESSAGE_INFO, "\tProblematic nodes:\n"); - for (i = 0; i < num_tnodes; i++) { - if (found_tnode[i] == FALSE) { - vpr_printf(TIO_MESSAGE_INFO, "\t\ttnode %d ", i); - if (tnode[i].pb_graph_pin == NULL) { - vpr_printf(TIO_MESSAGE_INFO, "block %s port %d pin %d\n", logical_block[tnode[i].block].name, tnode[i].prepacked_data->model_port, tnode[i].prepacked_data->model_pin); - } else { - vpr_printf(TIO_MESSAGE_INFO, "\n"); - } - } - } - - free(found_tnode); -} - diff --git a/vpr7_x2p/vpr/SRC/timing/path_delay2.h b/vpr7_x2p/vpr/SRC/timing/path_delay2.h deleted file mode 100755 index 6e9459a1f..000000000 --- a/vpr7_x2p/vpr/SRC/timing/path_delay2.h +++ /dev/null @@ -1,21 +0,0 @@ -/*********** Types and defines used by all path_delay modules ****************/ - -extern t_tnode *tnode; /* [0..num_tnodes - 1] */ -extern int num_tnodes; /* Number of nodes in the timing graph */ - -extern int num_tnode_levels; /* Number of levels in the timing graph. */ - -extern struct s_ivec *tnodes_at_level; -/* [0..num__tnode_levels - 1]. Count and list of tnodes at each level of - * the timing graph, to make topological searches easier. Level-0 nodes are - * sources to the timing graph (types TN_FF_SOURCE, TN_INPAD_SOURCE - * and TN_CONSTANT_GEN_SOURCE). Level-N nodes are in the immediate fanout of - * nodes with level at most N-1. */ - -/***************** Subroutines exported by this module ***********************/ - -int alloc_and_load_timing_graph_levels(void); - -void check_timing_graph(int num_sinks); - -float print_critical_path_node(FILE * fp, t_linked_int * critical_path_node); diff --git a/vpr7_x2p/vpr/SRC/timing/read_sdc.c b/vpr7_x2p/vpr/SRC/timing/read_sdc.c deleted file mode 100644 index b55689f11..000000000 --- a/vpr7_x2p/vpr/SRC/timing/read_sdc.c +++ /dev/null @@ -1,1337 +0,0 @@ -#include -#include -#include -#include -#include "assert.h" -#include "util.h" -#include "vpr_types.h" -#include "globals.h" -#include "read_sdc.h" -#include "read_blif.h" -#include "path_delay.h" -#include "path_delay2.h" -#include "ReadOptions.h" -#include "slre.h" - -/***************************** Summary **********************************/ - -/* Author: Michael Wainberg - -Looks for an SDC (Synopsys Design Constraints) file called .sdc -(unless overridden with --sdc_file on the command-line, in which -case it looks for that filename), and parses the timing constraints in that file. -If it doesn't find a file with that name, it uses default timing constraints -(which differ depending on whether the circuit has 0, 1, or multiple clocks). - -The primary routine, read_sdc, populates a container structure, g_sdc. -One of the two key output data structures within is g_sdc->constrained_clocks, which -associates each clock given a timing constraint with a name, fanout and whether -it is a netlist or virtual (external) clock. From this point on, the only clocks -we care about are the ones in this array. During timing analysis and data output, -clocks are accessed using the indexing of this array. - -The other key data structure is the "constraint matrix" g_sdc->domain_constraint, which -has a timing constraint for each pair (source and sink) of clock domains. These -generally come from finding the smallest difference between the posedges of the -two clocks over the LCM clock period ("edge counting" - see calculate_constraint()). - -Alternatively, entries in g_sdc->domain_constraint can come from a special-case, "override -constraint" (so named because it overrides the default behaviour of edge counting). -Override constraints can cut paths (set_clock_groups, set_false_path commands), -create a multicycle (set_multicycle_path) or even override a constraint with a user- -specified one (set_max_delay). These entries are stored temporarily in g_sdc->cc_constraints -(cc = clock to clock), which is freed once the timing_constraints echo file is -created during process_constraints(). - -Flip-flop-level override constraints also exist and are stored in g_sdc->cf_constraints, -g_sdc->fc_constraints and g_sdc->ff_constraints (depending on whether the source, sink or neither -of the two is a clock domain).Unlike g_sdc->cc_constraints, they are placed on the timing -graph during timing analysis instead of going into g_sdc->domain_constraint, and are not -freed until the end of VPR's execution. - -I/O constraints from set_input_delay and set_output_delay are stored in constrained_ -inputs and g_sdc->constrained_outputs. These associate each I/O in the netlist given a -constraint with the clock (often virtual, but could be in the netlist) it was -constrained on, and the delay through the I/O in that constraint. - -The remaining data structures are temporary and local to this file: netlist_clocks, -netlist_inputs and netlist_outputs, which are used to match names of clocks and I/Os -in the SDC file to those in the netlist; sdc_clocks, which stores info on clock periods -and offsets from create_clock commands and is the raw info used in edge counting; and -exclusive_groups, used when parsing set_clock_groups commands into g_sdc->cc_constraints. */ - -/*********************** Externally-accessible variables **************************/ - -t_timing_constraints * g_sdc = NULL; - -/****************** Types local to this module **************************/ - -typedef struct s_sdc_clock { - char * name; - float period; - float rising_edge; - float falling_edge; -} t_sdc_clock; -/* Stores the name, period and offset of each constrained clock. */ - -typedef struct s_sdc_exclusive_group { - char ** clock_names; - int num_clock_names; -} t_sdc_exclusive_group; -/* Used to temporarily separate clock names into exclusive groups when parsing the -command set_clock_groups -exclusive. */ - -/****************** Variables local to this module **************************/ - -static FILE *sdc; -t_sdc_clock * sdc_clocks = NULL; /* List of clock periods and offsets from create_clock commands */ - -int num_netlist_clocks = 0; /* number of clocks in netlist */ -char ** netlist_clocks; /* [0..num_netlist_clocks - 1] array of names of clocks in netlist */ - -int num_netlist_ios = 0; /* number of clocks in netlist */ -char ** netlist_ios; /* [0..num_netlist_clocks - 1] array of names of ios in netlist */ - -/***************** Subroutines local to this module *************************/ - -static void alloc_and_load_netlist_clocks_and_ios(void); -static void use_default_timing_constraints(void); -static void count_netlist_clocks_as_constrained_clocks(void); -static boolean get_sdc_tok(char * buf); -static boolean is_number(char * ptr); -static int find_constrained_clock(char * ptr); -static float calculate_constraint(t_sdc_clock source_domain, t_sdc_clock sink_domain); -static void add_override_constraint(char ** from_list, int num_from, char ** to_list, int num_to, - float constraint, int num_multicycles, boolean domain_level_from, boolean domain_level_to, - boolean make_copies); -static int find_cc_constraint(char * source_clock_domain, char * sink_clock_domain); -static boolean regex_match (char *string, char *pattern); -static void count_netlist_ios_as_constrained_ios(char * clock_name, float io_delay); -static void free_io_constraint(t_io *& io_array, int num_ios); -static void free_clock_constraint(t_clock *& clock_array, int num_clocks); - -/********************* Subroutine definitions *******************************/ - -void read_sdc(t_timing_inf timing_inf) { - - char buf[BUFSIZE]; - int source_clock_domain, sink_clock_domain, iinput, ioutput, icc, isource, isink; - boolean found; - - /* Make sure we haven't called this subroutine before. */ - assert(!g_sdc); - - /* Allocate container structure for SDC constraints. */ - g_sdc = (t_timing_constraints *) my_calloc(1, sizeof(t_timing_constraints)); - - /* Reset file line number. */ - file_line_number = 0; - - /* If no SDC file is included or specified, or timing analysis is off, - use default behaviour of cutting paths between domains and optimizing each clock separately */ - - if (!timing_inf.timing_analysis_enabled) { - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Timing analysis off; using default timing constraints.\n"); - use_default_timing_constraints(); - return; - } - - if ((sdc = fopen(timing_inf.SDCFile, "r")) == NULL) { - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "SDC file '%s' blank or not found.\n", timing_inf.SDCFile); - use_default_timing_constraints(); - return; - } - - /* Now we have an SDC file. */ - - /* Count how many clocks and I/Os are in the netlist. - Store the names of each clock and each I/O in netlist_clocks and netlist_ios. - The only purpose of these two lists is to compare clock names in the SDC file against them. - As a result, they will be freed after the SDC file is parsed. */ - alloc_and_load_netlist_clocks_and_ios(); - - /* Parse the file line-by-line. */ - found = FALSE; - while (my_fgets(buf, BUFSIZE, sdc) != NULL) { - if (get_sdc_tok(buf)) { - found = TRUE; - } - } - if (!found) { /* blank file or only comments found */ - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "SDC file '%s' blank or not found.\n", timing_inf.SDCFile); - use_default_timing_constraints(); - free(netlist_clocks); - free(netlist_ios); - return; - } - - fclose(sdc); - - /* Make sure that all virtual clocks referenced in g_sdc->constrained_inputs and g_sdc->constrained_outputs have been constrained. */ - for (iinput = 0; iinput < g_sdc->num_constrained_inputs; iinput++) { - if ((find_constrained_clock(g_sdc->constrained_inputs[iinput].clock_name)) == -1) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Input %s is associated with an unconstrained clock %s.\n", - g_sdc->constrained_inputs[iinput].file_line_number, - g_sdc->constrained_inputs[iinput].name, - g_sdc->constrained_inputs[iinput].clock_name); - exit(1); - } - } - - for (ioutput = 0; ioutput < g_sdc->num_constrained_outputs; ioutput++) { - if ((find_constrained_clock(g_sdc->constrained_outputs[ioutput].clock_name)) == -1) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Output %s is associated with an unconstrained clock %s.\n", - g_sdc->constrained_inputs[iinput].file_line_number, - g_sdc->constrained_outputs[ioutput].name, - g_sdc->constrained_outputs[ioutput].clock_name); - exit(1); - } - } - - /* Make sure that all clocks referenced in g_sdc->cc_constraints have been constrained. */ - for (icc = 0; icc < g_sdc->num_cc_constraints; icc++) { - for (isource = 0; isource < g_sdc->cc_constraints[icc].num_source; isource++) { - if ((find_constrained_clock(g_sdc->cc_constraints[icc].source_list[isource])) == -1) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Token %s is not a constrained clock.\n", - g_sdc->cc_constraints[icc].file_line_number, - g_sdc->cc_constraints[icc].source_list[isource]); - exit(1); - } - } - for (isink = 0; isink < g_sdc->cc_constraints[icc].num_sink; isink++) { - if ((find_constrained_clock(g_sdc->cc_constraints[icc].sink_list[isink])) == -1) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Token %s is not a constrained clock.\n", - g_sdc->cc_constraints[icc].file_line_number, - g_sdc->cc_constraints[icc].sink_list[isink]); - exit(1); - } - } - } - - /* Allocate matrix of timing constraints [0..g_sdc->num_constrained_clocks-1][0..g_sdc->num_constrained_clocks-1] and initialize to 0 */ - g_sdc->domain_constraint = (float **) alloc_matrix(0, g_sdc->num_constrained_clocks-1, 0, g_sdc->num_constrained_clocks-1, sizeof(float)); - - /* Based on the information from sdc_clocks, calculate constraints for all paths except ones with an override constraint. */ - for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - if ((icc = find_cc_constraint(g_sdc->constrained_clocks[source_clock_domain].name, g_sdc->constrained_clocks[sink_clock_domain].name)) != -1) { - if (g_sdc->cc_constraints[icc].num_multicycles == 0) { - /* There's a special constraint from set_false_path, set_clock_groups - -exclusive or set_max_delay which overrides the default constraint. */ - g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = g_sdc->cc_constraints[icc].constraint; - } else { - /* There's a special constraint from set_multicycle_path which overrides the default constraint. - This constraint = default constraint (obtained via edge counting) + (num_multicycles - 1) * period of sink clock domain. */ - g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = - calculate_constraint(sdc_clocks[source_clock_domain], sdc_clocks[sink_clock_domain]) - + (g_sdc->cc_constraints[icc].num_multicycles - 1) * sdc_clocks[sink_clock_domain].period; - } - } else { - /* There's no special override constraint. */ - /* Calculate the constraint between clock domains by finding the smallest positive - difference between a posedge in the source domain and one in the sink domain. */ - g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = - calculate_constraint(sdc_clocks[source_clock_domain], sdc_clocks[sink_clock_domain]); - } - } - } - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "SDC file '%s' parsed successfully.\n", - timing_inf.SDCFile ); - vpr_printf(TIO_MESSAGE_INFO, "%d clocks (including virtual clocks), %d inputs and %d outputs were constrained.\n", - g_sdc->num_constrained_clocks, g_sdc->num_constrained_inputs, g_sdc->num_constrained_outputs); - vpr_printf(TIO_MESSAGE_INFO, "\n"); - - /* Since all the information we need is stored in g_sdc->domain_constraint, g_sdc->constrained_clocks, - and constrained_ios, free other data structures used in this routine */ - free(sdc_clocks); - free(netlist_clocks); - free(netlist_ios); - return; -} - -static void use_default_timing_constraints(void) { - - int source_clock_domain, sink_clock_domain; - - /* Find all netlist clocks and add them as constrained clocks. */ - count_netlist_clocks_as_constrained_clocks(); - - /* We'll use separate defaults for multi-clock and single-clock/combinational circuits. */ - - if (g_sdc->num_constrained_clocks <= 1) { - /* Create one constrained clock with period 0... */ - g_sdc->domain_constraint = (float **) alloc_matrix(0, 0, 0, 0, sizeof(float)); - g_sdc->domain_constraint[0][0] = 0.; - - if (g_sdc->num_constrained_clocks == 0) { - /* We need to create a virtual clock to constrain I/Os on. */ - g_sdc->num_constrained_clocks = 1; - g_sdc->constrained_clocks = (t_clock *) my_malloc(sizeof(t_clock)); - g_sdc->constrained_clocks[0].name = my_strdup("virtual_io_clock"); - g_sdc->constrained_clocks[0].is_netlist_clock = FALSE; - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Defaulting to: constrain all %d inputs and %d outputs on a virtual external clock.\n", - g_sdc->num_constrained_inputs, g_sdc->num_constrained_outputs); - vpr_printf(TIO_MESSAGE_INFO, "Optimize this virtual clock to run as fast as possible.\n"); - } else { - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Defaulting to: constrain all %d inputs and %d outputs on the netlist clock.\n", - g_sdc->num_constrained_inputs, g_sdc->num_constrained_outputs); - vpr_printf(TIO_MESSAGE_INFO, "Optimize this clock to run as fast as possible.\n"); - } - - /* Constrain all I/Os on the single constrained clock (whether real or virtual), with I/O delay 0. */ - count_netlist_ios_as_constrained_ios(g_sdc->constrained_clocks[0].name, 0.); - - } else { /* Multiclock circuit */ - - /* Constrain all I/Os on a separate virtual clock. Cut paths between all netlist - clocks, but analyse all paths between the virtual I/O clock and netlist clocks - and optimize all clocks to go as fast as possible. */ - - g_sdc->constrained_clocks = (t_clock *) my_realloc (g_sdc->constrained_clocks, ++g_sdc->num_constrained_clocks * sizeof(t_clock)); - g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].name = my_strdup("virtual_io_clock"); - g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].is_netlist_clock = FALSE; - count_netlist_ios_as_constrained_ios(g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].name, 0.); - - /* Allocate matrix of timing constraints [0..g_sdc->num_constrained_clocks-1][0..g_sdc->num_constrained_clocks-1] */ - g_sdc->domain_constraint = (float **) alloc_matrix(0, g_sdc->num_constrained_clocks-1, 0, g_sdc->num_constrained_clocks-1, sizeof(float)); - - for (source_clock_domain = 0; source_clock_domain < g_sdc->num_constrained_clocks; source_clock_domain++) { - for (sink_clock_domain = 0; sink_clock_domain < g_sdc->num_constrained_clocks; sink_clock_domain++) { - if (source_clock_domain == sink_clock_domain || source_clock_domain == g_sdc->num_constrained_clocks - 1 - || sink_clock_domain == g_sdc->num_constrained_clocks - 1) { - g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = 0.; - } else { - g_sdc->domain_constraint[source_clock_domain][sink_clock_domain] = DO_NOT_ANALYSE; - } - } - } - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "Defaulting to: constrain all %d inputs and %d outputs on a virtual external clock;\n", - g_sdc->num_constrained_inputs, g_sdc->num_constrained_outputs); - vpr_printf(TIO_MESSAGE_INFO, "\tcut paths between netlist clock domains; and\n"); - vpr_printf(TIO_MESSAGE_INFO, "\toptimize all clocks to run as fast as possible.\n"); - } -} - -static void alloc_and_load_netlist_clocks_and_ios(void) { - - /* Count how many clocks and I/Os are in the netlist. - Store the names of each clock and each I/O in netlist_clocks and netlist_ios. */ - - int iblock, i, clock_net; - char * name; - boolean found; - - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - if (logical_block[iblock].clock_net != OPEN) { - clock_net = logical_block[iblock].clock_net; - assert(clock_net != OPEN); - name = logical_block[clock_net].name; - /* Now that we've found a clock, let's see if we've counted it already */ - found = FALSE; - for (i = 0; !found && i < num_netlist_clocks; i++) { - if (strcmp(netlist_clocks[i], name) == 0) { - found = TRUE; - } - } - if (!found) { - /* If we get here, the clock is new and so we dynamically grow the array netlist_clocks by one. */ - netlist_clocks = (char **) my_realloc (netlist_clocks, ++num_netlist_clocks * sizeof(char *)); - netlist_clocks[num_netlist_clocks - 1] = name; - } - } else if (logical_block[iblock].type == VPACK_INPAD || logical_block[iblock].type == VPACK_OUTPAD) { - name = logical_block[iblock].name; - /* Now that we've found an I/O, let's see if we've counted it already */ - found = FALSE; - for (i = 0; !found && i < num_netlist_ios; i++) { - if (strcmp(netlist_ios[i], name) == 0) { - found = TRUE; - } - } - if (!found) { - /* If we get here, the I/O is new and so we dynamically grow the array netlist_ios by one. */ - netlist_ios = (char **) my_realloc (netlist_ios, ++num_netlist_ios * sizeof(char *)); - netlist_ios[num_netlist_ios - 1] = logical_block[iblock].type == VPACK_OUTPAD ? name + 4 : name; - /* the + 4 removes the prefix "out:" automatically prepended to outputs */ - } - } - } -} - -static void count_netlist_clocks_as_constrained_clocks(void) { - /* Counts how many clocks are in the netlist, and adds them to the array g_sdc->constrained_clocks. */ - - int iblock, i, clock_net; - char * name; - boolean found; - - g_sdc->num_constrained_clocks = 0; - - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - if (logical_block[iblock].clock_net != OPEN) { - clock_net = logical_block[iblock].clock_net; - assert(clock_net != OPEN); - name = logical_block[clock_net].name; - /* Now that we've found a clock, let's see if we've counted it already */ - found = FALSE; - for (i = 0; !found && i < g_sdc->num_constrained_clocks; i++) { - if (strcmp(g_sdc->constrained_clocks[i].name, name) == 0) { - found = TRUE; - } - } - if (!found) { - /* If we get here, the clock is new and so we dynamically grow the array g_sdc->constrained_clocks by one. */ - g_sdc->constrained_clocks = (t_clock *) my_realloc (g_sdc->constrained_clocks, ++g_sdc->num_constrained_clocks * sizeof(t_clock)); - g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].name = my_strdup(name); - g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].is_netlist_clock = TRUE; - /* Fanout will be filled out once the timing graph has been constructed. */ - } - } - } -} - -static void count_netlist_ios_as_constrained_ios(char * clock_name, float io_delay) { - /* Count how many I/Os are in the netlist, adds them to the arrays g_sdc->constrained_inputs/ - g_sdc->constrained_outputs with an I/O delay of 0 and constrains them to clock clock_name. */ - - int iblock, iinput, ioutput; - char * name; - boolean found; - - for (iblock = 0; iblock < num_logical_blocks; iblock++) { - if (logical_block[iblock].type == VPACK_INPAD) { - name = logical_block[iblock].name; - /* Now that we've found an I/O, let's see if we've counted it already */ - found = FALSE; - for (iinput = 0; !found && iinput < g_sdc->num_constrained_inputs; iinput++) { - if (strcmp(g_sdc->constrained_inputs[iinput].name, name) == 0) { - found = TRUE; - } - } - if (!found) { - /* If we get here, the input is new and so we add it to g_sdc->constrained_inputs. */ - g_sdc->constrained_inputs = (t_io *) my_realloc (g_sdc->constrained_inputs, ++g_sdc->num_constrained_inputs * sizeof(t_io)); - g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].name = my_strdup(name); - g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].clock_name = my_strdup(clock_name); - g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].delay = 0.; - } - } else if (logical_block[iblock].type == VPACK_OUTPAD) { - name = logical_block[iblock].name; - /* Now that we've found an I/O, let's see if we've counted it already */ - found = FALSE; - for (ioutput = 0; !found && ioutput < g_sdc->num_constrained_outputs; ioutput++) { - if (strcmp(g_sdc->constrained_outputs[ioutput].name, name) == 0) { - found = TRUE; - } - } - if (!found) { - /* If we get here, the output is new and so we add it to g_sdc->constrained_outputs. */ - g_sdc->constrained_outputs = (t_io *) my_realloc (g_sdc->constrained_outputs, ++g_sdc->num_constrained_outputs * sizeof(t_io)); - g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].name = my_strdup(name + 4); - /* the + 4 removes the prefix "out:" automatically prepended to outputs */ - g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].clock_name = my_strdup(clock_name); - g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].delay = 0.; - } - } - } -} - -static boolean get_sdc_tok(char * buf) { -/* Figures out which tokens are on this line and takes the appropriate actions. - Returns true if anything non-commented is found on this line. */ - -#define SDC_TOKENS " \t\n{}[]" /* We can ignore braces. */ - - char * ptr, ** from_list = NULL, ** to_list = NULL, * clock_name; - float clock_period, rising_edge, falling_edge, max_delay; - int iclock, iio, num_exclusive_groups = 0, - num_from = 0, num_to = 0, num_multicycles, i, j; - t_sdc_exclusive_group * exclusive_groups = NULL; - boolean found, domain_level_from = FALSE, domain_level_to = FALSE; - - /* my_strtok splits the string into tokens - little character arrays separated by the SDC_TOKENS - defined above. Throughout this code, ptr refers to the tokens we fetch, one at a time. The token - changes at each call of my_strtok. We call my_strtok with NULL as the first argument every time - AFTER the first, since this picks up tokenizing where we left off. We always wrap each call to - my_strtok with a check that ptr is non-null to avoid an exception from passing NULL into strcmp. */ - - - if ((ptr = my_strtok(buf, SDC_TOKENS, sdc, buf)) == NULL) {/* blank line */ - return FALSE; - } - - if (strcmp(ptr, "create_clock") == 0) { - /* Syntax: create_clock -period [-waveform {rising_edge falling_edge}] - or create_clock -period [-waveform {rising_edge falling_edge}] -name */ - - /* make sure clock has -period specified */ - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-period") != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Create_clock must be directly followed by '-period'.\n", - file_line_number); - exit(1); - } - - /* Check if the token following -period is actually a number. */ - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || !is_number(ptr)) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] A number must follow '-period'.\n", - file_line_number); - exit(1); - } - clock_period = (float) strtod(ptr, NULL); - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Clock(s) not specified.\n", - file_line_number); - exit(1); - } - if (strcmp(ptr, "-waveform") == 0) { - - /* Get the first float, which is the rising edge, and the second, which is the falling edge. */ - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || !is_number(ptr)) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] First token following '-waveform' should be rising edge, but is not a number.\n", - file_line_number); - } - rising_edge = (float) strtod(ptr, NULL); - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || !is_number(ptr)) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Second token following '-waveform' should be falling edge, but is not a number.\n", - file_line_number); - exit(1); - } - falling_edge = (float) strtod(ptr, NULL); - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Clock(s) not specified.\n", - file_line_number); - exit(1); - } /* We need this extra call to my_strtok to advance the ptr to the right spot. */ - - } else { - /* The clock's rising edge is by default at 0, and the falling edge is at the half-period. */ - rising_edge = 0.; - falling_edge = clock_period / 2.0; - } - - if (strcmp(ptr, "-name") == 0) { - /* For external virtual clocks only (used with I/O constraints). - Only one virtual clock can be specified per line, - so make sure there's only one token left on this line. */ - - /* Get the virtual clock name */ - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Virtual clock name not specified.\n", - file_line_number); - exit(1); - } /* We need this extra call to my_strtok to advance the ptr to the right spot. */ - - /* We've found a new clock! */ - - /* Store the clock's name, period and edges in the local array sdc_clocks. */ - sdc_clocks = (t_sdc_clock *) my_realloc(sdc_clocks, ++g_sdc->num_constrained_clocks * sizeof(t_sdc_clock)); - sdc_clocks[g_sdc->num_constrained_clocks - 1].name = ptr; - sdc_clocks[g_sdc->num_constrained_clocks - 1].period = clock_period; - sdc_clocks[g_sdc->num_constrained_clocks - 1].rising_edge = rising_edge; - sdc_clocks[g_sdc->num_constrained_clocks - 1].falling_edge = falling_edge; - - /* Also store the clock's name, and the fact that it is not a netlist clock, in g_sdc->constrained_clocks. */ - g_sdc->constrained_clocks = (t_clock *) my_realloc (g_sdc->constrained_clocks, g_sdc->num_constrained_clocks * sizeof(t_clock)); - g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].name = my_strdup(ptr); - g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].is_netlist_clock = FALSE; - /* Fanout will be filled out once the timing graph has been constructed. */ - - /* The next token should be NULL. If so, return; if not, print an error message and exit. */ - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) != NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] More than one virtual clock name is specified after '-name'.\n", - file_line_number); - exit(1); - } - - } else { - /* Parse through to the end of the line. All that should be left on this line are one or more - * regular expressions denoting netlist clocks to be associated with this clock period. An array sdc_clocks will - * store the period and offset of each clock at the same index which that clock has in netlist_clocks. Later, - * after everything has been parsed, we take the information from this array to calculate the actual timing constraints - * which these periods and offsets imply, and put them in the matrix g_sdc->domain_constraint. */ - - do { - /* See if the regular expression stored in ptr is legal and matches at least one clock net. - If it is not legal, it will fail during regex_match. We check for a match using boolean found. */ - found = FALSE; - for (iclock = 0; iclock < num_netlist_clocks; iclock++) { - if (regex_match(netlist_clocks[iclock], ptr)) { - /* We've found a new clock! (Note that we can't store ptr as the clock's - name since it could be a regex, unlike the virtual clock case).*/ - found = TRUE; - - /* Store the clock's name, period and edges in the local array sdc_clocks. */ - sdc_clocks = (t_sdc_clock *) my_realloc(sdc_clocks, ++g_sdc->num_constrained_clocks * sizeof(t_sdc_clock)); - sdc_clocks[g_sdc->num_constrained_clocks - 1].name = netlist_clocks[iclock]; - sdc_clocks[g_sdc->num_constrained_clocks - 1].period = clock_period; - sdc_clocks[g_sdc->num_constrained_clocks - 1].rising_edge = rising_edge; - sdc_clocks[g_sdc->num_constrained_clocks - 1].falling_edge = falling_edge; - - /* Also store the clock's name, and the fact that it is a netlist clock, in g_sdc->constrained_clocks. */ - g_sdc->constrained_clocks = (t_clock *) my_realloc (g_sdc->constrained_clocks, g_sdc->num_constrained_clocks * sizeof(t_clock)); - g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].name = my_strdup(netlist_clocks[iclock]); - g_sdc->constrained_clocks[g_sdc->num_constrained_clocks - 1].is_netlist_clock = TRUE; - /* Fanout will be filled out once the timing graph has been constructed. */ - } - } - - if (!found) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Clock name or regular expression does not correspond to any nets.\n", - file_line_number); - vpr_printf(TIO_MESSAGE_ERROR, "If you'd like to create a virtual clock, use the '-name' keyword.\n"); - exit(1); - } - } while ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) != NULL); /* Advance to the next token (or the end of the line). */ - } - - /* Warn if the clock has non-50% duty cycle. */ - if (fabs(rising_edge - falling_edge) - clock_period/2.0 > EPSILON) { - vpr_printf(TIO_MESSAGE_WARNING, "Clock %s does not have 50%% duty cycle.\n", - sdc_clocks[g_sdc->num_constrained_clocks - 1].name); - } - - return TRUE; - - } else if (strcmp(ptr, "set_clock_groups") == 0) { - /* Syntax: set_clock_groups -exclusive -group {} -group {} [-group {} ...] */ - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-exclusive") != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_clock_groups must be directly followed by '-exclusive'.\n", - file_line_number); - exit(1); - } - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-group") != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_clock_groups '-exclusive' must be followed by lists of clock names or regular expressions each starting with the '-group' command.\n", - file_line_number); - exit(1); - } - - /* Parse through to the end of the line. All that should be left on this line are a bunch of - -group commands, followed by groups of regexes. We need to ensure that paths are cut between - every clock matching a regex in one group and every clock matching a regex in any other group. */ - - do { - ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf); - - /* Create a new entry in exclusive groups */ - exclusive_groups = (t_sdc_exclusive_group *) my_realloc( - exclusive_groups, ++num_exclusive_groups * sizeof(t_sdc_exclusive_group)); - exclusive_groups[num_exclusive_groups - 1].clock_names = NULL; - exclusive_groups[num_exclusive_groups - 1].num_clock_names = 0; - do { - /* Check the regex ptr against each netlist clock and add it to the clock_names list if it matches. */ - found = FALSE; - for (iclock = 0; iclock < num_netlist_clocks; iclock++) { - if (regex_match(netlist_clocks[iclock], ptr)) { - found = TRUE; - exclusive_groups[num_exclusive_groups - 1].clock_names = (char **) my_realloc( - exclusive_groups[num_exclusive_groups - 1].clock_names, ++exclusive_groups[num_exclusive_groups - 1].num_clock_names * sizeof(char *)); - exclusive_groups[num_exclusive_groups - 1].clock_names - [exclusive_groups[num_exclusive_groups - 1].num_clock_names - 1] = - my_strdup(netlist_clocks[iclock]); - } - } - if (!found) { - /* If no clocks matched, assume ptr is the name of a virtual clock and add it to the list. - (If it's not a virtual clock, we'll catch it later when we check all override constraints.) */ - exclusive_groups[num_exclusive_groups - 1].clock_names = (char **) my_realloc( - exclusive_groups[num_exclusive_groups - 1].clock_names, ++exclusive_groups[num_exclusive_groups - 1].num_clock_names * sizeof(char *)); - exclusive_groups[num_exclusive_groups - 1].clock_names - [exclusive_groups[num_exclusive_groups - 1].num_clock_names - 1] = - my_strdup(ptr); - } - } while ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) != NULL && strcmp(ptr, "-group") != 0); - } while (ptr); - - if (num_exclusive_groups < 2) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] At least two '-group' commands required.", - file_line_number); - exit(1); - } - - /* Finally, create two DO_NOT_ANALYSE override constraints for each pair of entries - to cut paths bidirectionally between pairs of clock lists in different groups. - Set make_copies to TRUE because we have to use the lists of names in multiple - override constraints, and it's impossible to free them from multiple places at the - end without a whole lot of trouble. */ - - for (i = 0; i < num_exclusive_groups; i++) { - for (j = 0; j < num_exclusive_groups; j++) { - if (i != j) { - add_override_constraint(exclusive_groups[i].clock_names, exclusive_groups[i].num_clock_names, - exclusive_groups[j].clock_names, exclusive_groups[j].num_clock_names, DO_NOT_ANALYSE, 0, TRUE, TRUE, TRUE); - } - } - } - - /* Now that we've copied all the clock name lists - (2 * num_exlusive_groups - 1) times, free the original lists. */ - for (i = 0; i < num_exclusive_groups; i++) { - for (j = 0; j < exclusive_groups[i].num_clock_names; j++) { - free(exclusive_groups[i].clock_names[j]); - } - free(exclusive_groups[i].clock_names); - } - free (exclusive_groups); - - return TRUE; - - } else if (strcmp(ptr, "set_false_path") == 0) { - /* Syntax: set_false_path -from -to */ - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-from") != 0 || (ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_false_path must be directly followed by '-from '.\n", - file_line_number); - exit(1); - } - - if (strcmp(ptr, "get_clocks") == 0) { - domain_level_from = TRUE; - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_false_path must be directly followed by '-from '.\n", - file_line_number); - exit(1); - } - } - - do { - /* Keep adding clock names to from_list until we hit the -to command. */ - from_list = (char **) my_realloc(from_list, ++num_from * sizeof(char *)); - from_list[num_from - 1] = my_strdup(ptr); - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - /* We hit the end of the line before finding a -to. */ - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_false_path requires '-to ' after '-from '.\n", - file_line_number); - exit(1); - } - } while (strcmp(ptr, "-to") != 0); - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_false_path requires '-to ' after '-from '.\n", - file_line_number); - } - - if (strcmp(ptr, "get_clocks") == 0) { - domain_level_to = TRUE; - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_false_path must be directly followed by '-from '.\n", - file_line_number); - exit(1); - } - } - - do { - /* Keep adding clock names to to_list until we hit the end of the line. */ - to_list = (char **) my_realloc(to_list, ++num_to * sizeof(char *)); - to_list[num_to - 1] = my_strdup(ptr); - } while ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) != NULL); - - /* Create a constraint between each element in from_list and each element in to_list with value DO_NOT_ANALYSE. - Set make_copies to false since, as we only need to use from_list and to_list once, we can just have the - override constraint entry point to those lists. */ - add_override_constraint(from_list, num_from, to_list, num_to, DO_NOT_ANALYSE, 0, domain_level_from, domain_level_to, FALSE); - - /* Finally, set from_list and to_list to NULL since they're both - being pointed to by the override constraint entry we just created. */ - from_list = NULL, to_list = NULL; - - return TRUE; - - } else if (strcmp(ptr, "set_max_delay") == 0) { - /* Syntax: set_max_delay -from -to */ - - /* Basically the same as set_false_path above, except we get a specific delay value for the constraint. */ - - /* check if the token following set_max_delay is actually a number*/ - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || !is_number(ptr)) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Token following set_max_delay should be a delay value, but is not a number.\n", - file_line_number); - exit(1); - } - max_delay = (float) strtod(ptr, NULL); - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-from") != 0 || (ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_max_delay requires '-from ' after max_delay.\n", - file_line_number); - exit(1); - } - - if (strcmp(ptr, "get_clocks") == 0) { - domain_level_from = TRUE; - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_max_delay requires '-from ' after max_delay.\n", - file_line_number); - exit(1); - } - } - - do { - /* Keep adding clock names to from_list until we hit the -to command. */ - from_list = (char **) my_realloc(from_list, ++num_from * sizeof(char *)); - from_list[num_from - 1] = my_strdup(ptr); - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - /* We hit the end of the line before finding a -to. */ - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_max_delay requires '-to ' after '-from '.\n", - file_line_number); - exit(1); - } - } while (strcmp(ptr, "-to") != 0); - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_max_delay requires '-to ' after '-from '.\n", - file_line_number); - } - - if (strcmp(ptr, "get_clocks") == 0) { - domain_level_to = TRUE; - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_max_delay requires '-to ' after '-from '.\n", - file_line_number); - exit(1); - } - } - - do { - /* Keep adding clock names to to_list until we hit the end of the line. */ - to_list = (char **) my_realloc(to_list, ++num_to * sizeof(char *)); - to_list[num_to - 1] = my_strdup(ptr); - } while ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) != NULL); - - /* Create a constraint between each element in from_list and each element in to_list with value max_delay. */ - add_override_constraint(from_list, num_from, to_list, num_to, max_delay, 0, domain_level_from, domain_level_to, FALSE); - - /* Finally, set from_list and to_list to NULL since they're both - being pointed to by the override constraint entry we just created. */ - from_list = NULL, to_list = NULL; - - return TRUE; - - } else if (strcmp(ptr, "set_multicycle_path") == 0) { - /* Syntax: set_multicycle_path -setup -from -to */ - - /* Basically the same as set_false_path and set_max_delay above, except we have to calculate - the default value of the constraint (obtained via edge counting) first, and then set a - constraint equal to default constraint + (num_multicycles - 1) * period of sink clock domain. */ - - /* check if the token following set_max_delay is actually a number*/ - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-setup") != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path must be directly followed by '-setup'.\n", - file_line_number); - exit(1); - } - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-from") != 0 || (ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path requires '-from ' after '-setup'.\n", - file_line_number); - exit(1); - } - - if (strcmp(ptr, "get_clocks") == 0) { - domain_level_from = TRUE; - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path '-setup' must be followed by '-from '.\n", - file_line_number); - exit(1); - } - } - - do { - /* Keep adding clock names to from_list until we hit the -to command. */ - from_list = (char **) my_realloc(from_list, ++num_from * sizeof(char *)); - from_list[num_from - 1] = my_strdup(ptr); - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - /* We hit the end of the line before finding a -to. */ - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path requires '-to ' after '-from '.\n", - file_line_number); - exit(1); - } - } while (strcmp(ptr, "-to") != 0); - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path requires '-to ' after '-from '.\n", - file_line_number); - } - - if (strcmp(ptr, "get_clocks") == 0) { - domain_level_to = TRUE; - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path requires '-to ' after '-from '.\n", - file_line_number); - exit(1); - } - } - - do { - /* Keep adding clock names to to_list until we hit a number (i.e. num_multicycles). */ - to_list = (char **) my_realloc(to_list, ++num_to * sizeof(char *)); - to_list[num_to - 1] = my_strdup(ptr); - } while (((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) != NULL) && !is_number(ptr)); - - if (!ptr) { - /* We hit the end of the line before finding a number. */ - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_multicycle_path requires num_multicycles after '-to '.\n", - file_line_number); - exit(1); - } - - num_multicycles = (int) strtod(ptr, NULL); - - /* Create an override constraint between from and to. Unlike the previous two commands, set_multicycle_path requires - information about the periods and offsets of the clock domains which from and to, which we have to fill in at the end. */ - add_override_constraint(from_list, num_from, to_list, num_to, HUGE_NEGATIVE_FLOAT /* irrelevant - never used */, - num_multicycles, domain_level_from, domain_level_to, FALSE); - - /* Finally, set from_list and to_list to NULL since they're both - being pointed to by the override constraint entry we just created. */ - from_list = NULL, to_list = NULL; - - return TRUE; - - } else if (strcmp(ptr, "set_input_delay") == 0) { - /* Syntax: set_input_delay -clock -max [get_ports {}] */ - - /* We want to assign virtual_clock to all input ports in port_list, and - set the input delay (from the external device to the FPGA) to max_delay. */ - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-clock") != 0 || (ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_input_delay must be directly followed by '-clock '.\n", - file_line_number); - exit(1); - } - - if (num_netlist_clocks == 1 && strcmp(ptr, "*") == 0) { - /* Allow the user to wildcard the clock name if there's only one clock (not standard SDC but very convenient). */ - clock_name = netlist_clocks[0]; - } else { - /* We have no way of error-checking whether this is an actual virtual clock until we finish parsing. */ - clock_name = ptr; - } - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-max") != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_input_delay '-clock ' must be directly followed by '-max '.\n", - file_line_number); - exit(1); - } - - /* check if the token following -max is actually a number*/ - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || !is_number(ptr)) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Token following '-max' should be a delay value, but is not a number.\n", - file_line_number); - exit(1); - } - max_delay = (float) strtod(ptr, NULL); - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "get_ports") != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_input_delay requires a [get_ports {...}] command following '-max '.\n", - file_line_number); - exit(1); - } - - /* Parse through to the end of the line. Add each regular expression match we find to the list of - constrained inputs and give each entry the virtual clock name and max_delay we've just parsed. - We have no way of error-checking whether these tokens correspond to actual input ports until later. */ - - for (;;) { - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { /* end of line */ - return TRUE; - } - - found = FALSE; - - for (iio = 0; iio < num_netlist_ios; iio++) { - /* See if the regular expression stored in ptr is legal and matches at least one input port. - If it is not legal, it will fail during regex_match. We check for a match using boolean found. */ - if (regex_match(netlist_ios[iio], ptr)) { - /* We've found a new input! */ - g_sdc->num_constrained_inputs++; - found = TRUE; - - /* Fill in input information in the permanent array g_sdc->constrained_inputs. */ - g_sdc->constrained_inputs = (t_io *) my_realloc (g_sdc->constrained_inputs, g_sdc->num_constrained_inputs * sizeof(t_io)); - g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].name = my_strdup(netlist_ios[iio]); - g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].clock_name = my_strdup(clock_name); - g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].delay = max_delay; - g_sdc->constrained_inputs[g_sdc->num_constrained_inputs - 1].file_line_number = file_line_number; /* global var */ - } - } - - if (!found) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Output name or regular expression \"%s\" does not correspond to any nets.\n", - file_line_number, ptr); - exit(1); - } - } - - } else if (strcmp(ptr, "set_output_delay") == 0) { - /* Syntax: set_output_delay -clock -max [get_ports {}] */ - - /* We want to assign virtual_clock to all output ports in port_list, and - set the output delay (from the external device to the FPGA) to max_delay. */ - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-clock") != 0 || (ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_output_delay must be directly followed by '-clock '.\n", - file_line_number); - exit(1); - } - - if (num_netlist_clocks == 1 && strcmp(ptr, "*") == 0) { - /* Allow the user to wildcard the clock name if there's only one clock (not standard SDC but very convenient). */ - clock_name = netlist_clocks[0]; - } else { - /* We have no way of error-checking whether this is an actual virtual clock until we finish parsing. */ - clock_name = ptr; - } - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "-max") != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_output_delay -clock must be directly followed by '-max '.\n", - file_line_number); - exit(1); - } - - /* check if the token following -max is actually a number*/ - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || !is_number(ptr)) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Token following '-max' should be a delay value, but is not a number.\n", - file_line_number); - exit(1); - } - max_delay = (float) strtod(ptr, NULL); - - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL || strcmp(ptr, "get_ports") != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] set_output_delay requires a [get_ports {...}] command following '-max '.\n", - file_line_number); - exit(1); - } - - /* Parse through to the end of the line. Add each regular expression match we find to the list of - constrained outputs and give each entry the virtual clock name and max_delay we've just parsed. - We have no way of error-checking whether these tokens correspond to actual output ports until later. */ - - for (;;) { - if ((ptr = my_strtok(NULL, SDC_TOKENS, sdc, buf)) == NULL) { /* end of line */ - return TRUE; - } - - found = FALSE; - - for (iio = 0; iio < num_netlist_ios; iio++) { - /* See if the regular expression stored in ptr is legal and matches at least one output port. - If it is not legal, it will fail during regex_match. We check for a match using boolean found. */ - if (regex_match(netlist_ios[iio], ptr)) { - /* We've found a new output! */ - g_sdc->num_constrained_outputs++; - found = TRUE; - - /* Fill in output information in the permanent array g_sdc->constrained_outputs. */ - g_sdc->constrained_outputs = (t_io *) my_realloc (g_sdc->constrained_outputs, g_sdc->num_constrained_outputs * sizeof(t_io)); - g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].name = my_strdup(netlist_ios[iio]); - g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].clock_name = my_strdup(clock_name); - g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].delay = max_delay; - g_sdc->constrained_outputs[g_sdc->num_constrained_outputs - 1].file_line_number = file_line_number; /* global var */ - } - } - - if (!found) { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Output name or regular expression \"%s\" does not correspond to any nets.\n", - file_line_number, ptr); - exit(1); - } - } - - } else { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Incorrect or unsupported syntax near start of line.\n", - file_line_number); - exit(1); - } -} - -static boolean is_number(char * ptr) { -/* Checks if the character array ptr represents a valid floating-point number. * - * To return TRUE, all characters must be digits, although * - * there can also be no more than one decimal point. */ - int i, len, num_decimal_points = 0; - len = strlen(ptr); - for (i = 0; i < len; i++) { - if ((ptr[i] < '0' || ptr[i] > '9')) { - if (ptr[i] != '.') { - return FALSE; - } - num_decimal_points++; - if (num_decimal_points > 1) { - return FALSE; - } - } - } - return TRUE; -} - -static int find_constrained_clock(char * ptr) { -/* Given a string ptr, find whether it's the name of a clock in the array g_sdc->constrained_clocks. * - * if it is, return the clock's index in g_sdc->constrained_clocks; if it's not, return -1. */ - int index; - for (index = 0; index < g_sdc->num_constrained_clocks; index++) { - if (strcmp(ptr, g_sdc->constrained_clocks[index].name) == 0) { - return index; - } - } - return -1; -} - -static int find_cc_constraint(char * source_clock_name, char * sink_clock_name) { - /* Given a pair of source and sink clock domains, find out if there's an override constraint between them. - If there is, return the index in g_sdc->cc_constraints; if there is not, return -1. */ - int icc, isource, isink; - - for (icc = 0; icc < g_sdc->num_cc_constraints; icc++) { - for (isource = 0; isource < g_sdc->cc_constraints[icc].num_source; isource++) { - if (strcmp(g_sdc->cc_constraints[icc].source_list[isource], source_clock_name) == 0) { - for (isink = 0; isink < g_sdc->cc_constraints[icc].num_sink; isink++) { - if (strcmp(g_sdc->cc_constraints[icc].sink_list[isink], sink_clock_name) == 0) { - return icc; - } - } - } - } - } - return -1; -} - -static void add_override_constraint(char ** from_list, int num_from, char ** to_list, int num_to, - float constraint, int num_multicycles, boolean domain_level_from, boolean domain_level_to, - boolean make_copies) { - /* Add a special-case constraint to override the default, calculated timing constraint, - to one of four arrays depending on whether it's coming from/to a flip-flop or an entire clock domain. - - If make_copies is true, we make a copy of from_list and to_list for this override constraint entry; - if false, we just set the override constraint entry to point to the existing list. The latter is - more efficient, but it's almost impossible to free multiple identical pointers without freeing - the same thing twice and causing an error. */ - - t_override_constraint ** constraint_array; - /* Because we are reallocating the array and possibly changing - its address, we need to modify it through a reference. */ - - int num_constraints, i; - - if (domain_level_from) { - if (domain_level_to) { /* Clock-to-clock constraint */ - constraint_array = &g_sdc->cc_constraints; - num_constraints = ++g_sdc->num_cc_constraints; - } else { /* Clock-to-flipflop constraint */ - constraint_array = &g_sdc->cf_constraints; - num_constraints = ++g_sdc->num_cf_constraints; - } - } else { - if (domain_level_to) { /* Flipflop-to-clock constraint */ - constraint_array = &g_sdc->fc_constraints; - num_constraints = ++g_sdc->num_fc_constraints; - } else { /* Flipflop-to-flipflop constraint */ - constraint_array = &g_sdc->ff_constraints; - num_constraints = ++g_sdc->num_ff_constraints; - } - } - - *constraint_array = (t_override_constraint *) my_realloc(*constraint_array, num_constraints * sizeof(t_override_constraint)); - - if (make_copies) { - /* Copy from_list and to_list to constraint_array[num_constraints - 1].source_list and .sink_list. */ - (*constraint_array)[num_constraints - 1].source_list = (char **) my_malloc(num_from * sizeof(char *)); - (*constraint_array)[num_constraints - 1].sink_list = (char **) my_malloc(num_to * sizeof(char *)); - for (i = 0; i < num_from; i++) { - (*constraint_array)[num_constraints - 1].source_list[i] = my_strdup(from_list[i]); - } - for (i = 0; i < num_to; i++) { - (*constraint_array)[num_constraints - 1].sink_list[i] = my_strdup(to_list[i]); - } - } else { - /* Just set constraint array to point to from_list and to_list. */ - (*constraint_array)[num_constraints - 1].source_list = from_list; - (*constraint_array)[num_constraints - 1].sink_list = to_list; - } - (*constraint_array)[num_constraints - 1].num_source = num_from; - (*constraint_array)[num_constraints - 1].num_sink = num_to; - (*constraint_array)[num_constraints - 1].constraint = constraint; - (*constraint_array)[num_constraints - 1].num_multicycles = num_multicycles; - (*constraint_array)[num_constraints - 1].file_line_number = file_line_number; /* global var */ -} - -static float calculate_constraint(t_sdc_clock source_domain, t_sdc_clock sink_domain) { - /* Given information from the SDC file about the period and offset of two clocks, * - * determine the implied setup-time constraint between them via edge counting. */ - - int source_period, sink_period, source_rising_edge, sink_rising_edge, lcm_period, num_source_edges, num_sink_edges, - * source_edges, * sink_edges, i, j, time, constraint_as_int; - float constraint; - - /* If the source and sink domains have the same period and edges, the constraint is just the common clock period. */ - if (fabs(source_domain.period - sink_domain.period) < EPSILON && - fabs(source_domain.rising_edge - sink_domain.rising_edge) < EPSILON && - fabs(source_domain.falling_edge - sink_domain.falling_edge) < EPSILON) { - return source_domain.period; /* or, equivalently, sink_domain.period */ - } - - /* If either period is 0, the constraint is 0. */ - if (source_domain.period < EPSILON || sink_domain.period < EPSILON) { - return 0.; - } - - /* Multiply periods and edges by 1000 and round down * - * to the nearest integer, to avoid messy decimals. */ - - source_period = static_cast(source_domain.period * 1000); - sink_period = static_cast(sink_domain.period * 1000); - source_rising_edge = static_cast(source_domain.rising_edge * 1000); - sink_rising_edge = static_cast(sink_domain.rising_edge * 1000); - - /* If we get here, we have to use edge counting. Find the LCM of the two periods. * - * This determines how long it takes before the pattern of the two clocks starts repeating. */ - for (lcm_period = 1; lcm_period % source_period != 0 || lcm_period % sink_period != 0; lcm_period++) - ; - - /* Create an array of positive edges for each clock over one LCM clock period. */ - - num_source_edges = lcm_period/source_period + 1; - num_sink_edges = lcm_period/sink_period + 1; - - source_edges = (int *) my_malloc((num_source_edges + 1) * sizeof(int)); - sink_edges = (int *) my_malloc((num_sink_edges + 1) * sizeof(int)); - - for (i = 0, time = source_rising_edge; i < num_source_edges + 1; i++) { - source_edges[i] = time; - time += source_period; - } - - for (i = 0, time = sink_rising_edge; i < num_sink_edges + 1; i++) { - sink_edges[i] = time; - time += sink_period; - } - - /* Compare every edge in source_edges with every edge in sink_edges. * - * The lowest STRICTLY POSITIVE difference between a sink edge and a source edge * - * gives us the set-up time constraint. */ - - constraint_as_int = INT_MAX; /* constraint starts off at +ve infinity so that everything will be less than it */ - - for (i = 0; i < num_source_edges + 1; i++) { - for (j = 0; j < num_sink_edges + 1; j++) { - if (sink_edges[j] > source_edges[i]) { - constraint_as_int = std::min(constraint_as_int, sink_edges[j] - source_edges[i]); - } - } - } - - /* Divide by 1000 again and turn the constraint back into a float, and clean up memory. */ - - constraint = constraint_as_int / 1000.; - - free(source_edges); - free(sink_edges); - - return constraint; -} - -static boolean regex_match (char * string, char * regular_expression) { - /* Given a string and a regular expression, return TRUE if there's a match, - FALSE if not. Print an error and exit if regular_expression is invalid. */ - - const char * error; - - assert(string && regular_expression); - - /* The regex library reports a match if regular_expression is a substring of string - AND not equal to string. This is not appropriate for our purposes. For example, - we'd get both "clock" and "clock2" matching the regular expression "clock". - We have to manually return that there's no match in this special case. */ - if (strstr(string, regular_expression) && strcmp(string, regular_expression) != 0) - return FALSE; - - if (strcmp(regular_expression, "*") == 0) - return TRUE; /* The regex library hangs if it is fed "*" as a regular expression. */ - - error = slre_match((enum slre_option) 0, regular_expression, string, strlen(string)); - - if (!error) - return TRUE; - else if (strcmp(error, "No match") == 0) - return FALSE; - else { - vpr_printf(TIO_MESSAGE_ERROR, "[SDC line %d] Error matching regular expression \"%s\".\n", - file_line_number, regular_expression); - exit(1); - } -} - -void free_sdc_related_structs(void) { - if (!g_sdc) return; - - free_override_constraint(g_sdc->cc_constraints, g_sdc->num_cc_constraints); - /* Should already have been freed in process_constraints() */ - - free_override_constraint(g_sdc->cf_constraints, g_sdc->num_cf_constraints); - free_override_constraint(g_sdc->fc_constraints, g_sdc->num_fc_constraints); - free_override_constraint(g_sdc->ff_constraints, g_sdc->num_ff_constraints); - free_io_constraint(g_sdc->constrained_inputs, g_sdc->num_constrained_inputs); - free_io_constraint(g_sdc->constrained_outputs, g_sdc->num_constrained_outputs); - free_clock_constraint(g_sdc->constrained_clocks, g_sdc->num_constrained_clocks); - free_matrix(g_sdc->domain_constraint, 0, g_sdc->num_constrained_clocks - 1, 0, sizeof(float)); - free(g_sdc); - g_sdc = NULL; -} - -void free_override_constraint(t_override_constraint *& constraint_array, int num_constraints) { - int i, j; - - if (!constraint_array) return; - - for (i = 0; i < num_constraints; i++) { - for (j = 0; j < constraint_array[i].num_source; j++) { - free(constraint_array[i].source_list[j]); - constraint_array[i].source_list[j] = NULL; - } - for (j = 0; j < constraint_array[i].num_sink; j++) { - free(constraint_array[i].sink_list[j]); - constraint_array[i].sink_list[j] = NULL; - } - free(constraint_array[i].source_list); - free(constraint_array[i].sink_list); - } - free(constraint_array); - constraint_array = NULL; -} - -static void free_io_constraint(t_io *& io_array, int num_ios) { - int i; - - for (i = 0; i < num_ios; i++) { - free(io_array[i].name); - free(io_array[i].clock_name); - } - free(io_array); - io_array = NULL; -} - -static void free_clock_constraint(t_clock *& clock_array, int num_clocks) { - int i; - - for (i = 0; i < num_clocks; i++) { - free(clock_array[i].name); - } - free(clock_array); - clock_array = NULL; -} diff --git a/vpr7_x2p/vpr/SRC/timing/read_sdc.h b/vpr7_x2p/vpr/SRC/timing/read_sdc.h deleted file mode 100644 index 8ba93070e..000000000 --- a/vpr7_x2p/vpr/SRC/timing/read_sdc.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef READ_SDC_H -#define READ_SDC_H - -/*********************** Externally-accessible variables **************************/ - -extern t_timing_constraints * g_sdc; - -/*************************** Function declarations ********************************/ - -void read_sdc(t_timing_inf timing_inf); -void free_sdc_related_structs(void); -void free_override_constraint(t_override_constraint *& constraint_array, int num_constraints); - -#endif diff --git a/vpr7_x2p/vpr/SRC/timing/slre.c b/vpr7_x2p/vpr/SRC/timing/slre.c deleted file mode 100644 index 516b3d611..000000000 --- a/vpr7_x2p/vpr/SRC/timing/slre.c +++ /dev/null @@ -1,662 +0,0 @@ -// Copyright (c) 2004-2012 Sergey Lyubka -// All rights reserved -// -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. - -#include -#include -#include -#include -#include -#include -#include -#include "slre.h" - -// Compiled regular expression -struct slre { - unsigned char code[256]; - unsigned char data[256]; - int code_size; - int data_size; - int num_caps; // Number of bracket pairs - int anchored; // Must match from string start - enum slre_option options; - const char *error_string; // Error string -}; - -// Captured substring -struct cap { - const char *ptr; // Pointer to the substring - int len; // Substring length -}; - -enum { - END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL, STAR, PLUS, - STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT -}; - -// Commands and operands are all unsigned char (1 byte long). All code offsets -// are relative to current address, and positive (always point forward). Data -// offsets are absolute. Commands with operands: -// -// BRANCH offset1 offset2 -// Try to match the code block that follows the BRANCH instruction -// (code block ends with END). If no match, try to match code block that -// starts at offset1. If either of these match, jump to offset2. -// -// EXACT data_offset data_length -// Try to match exact string. String is recorded in data section from -// data_offset, and has length data_length. -// -// OPEN capture_number -// CLOSE capture_number -// If the user have passed 'struct cap' array for captures, OPEN -// records the beginning of the matched substring (cap->ptr), CLOSE -// sets the length (cap->len) for respective capture_number. -// -// STAR code_offset -// PLUS code_offset -// QUEST code_offset -// *, +, ?, respectively. Try to gobble as much as possible from the -// matched buffer while code block that follows these instructions -// matches. When the longest possible string is matched, -// jump to code_offset -// -// STARQ, PLUSQ are non-greedy versions of STAR and PLUS. - -static const char *meta_characters = "|.*+?()[\\"; -static const char *error_no_match = "No match"; - -static void set_jump_offset(struct slre *r, int pc, int offset) { - assert(offset < r->code_size); - if (r->code_size - offset > 0xff) { - r->error_string = "Jump offset is too big"; - } else { - r->code[pc] = (unsigned char) (r->code_size - offset); - } -} - -static void emit(struct slre *r, int code) { - if (r->code_size >= (int) (sizeof(r->code) / sizeof(r->code[0]))) { - r->error_string = "RE is too long (code overflow)"; - } else { - r->code[r->code_size++] = (unsigned char) code; - } -} - -static void store_char_in_data(struct slre *r, int ch) { - if (r->data_size >= (int) sizeof(r->data)) { - r->error_string = "RE is too long (data overflow)"; - } else { - r->data[r->data_size++] = ch; - } -} - -static void exact(struct slre *r, const char **re) { - int old_data_size = r->data_size; - - while (**re != '\0' && (strchr(meta_characters, **re)) == NULL) { - store_char_in_data(r, *(*re)++); - } - - emit(r, EXACT); - emit(r, old_data_size); - emit(r, r->data_size - old_data_size); -} - -static int get_escape_char(const char **re) { - int res; - - switch (*(*re)++) { - case 'n': res = '\n'; break; - case 'r': res = '\r'; break; - case 't': res = '\t'; break; - case '0': res = 0; break; - case 'S': res = NONSPACE << 8; break; - case 's': res = SPACE << 8; break; - case 'd': res = DIGIT << 8; break; - default: res = (*re)[-1]; break; - } - - return res; -} - -static void anyof(struct slre *r, const char **re) { - int esc, old_data_size = r->data_size, op = ANYOF; - - while (**re != '\0') - - switch (*(*re)++) { - case ']': - emit(r, op); - emit(r, old_data_size); - emit(r, r->data_size - old_data_size); - return; - // NOTREACHED - break; - case '\\': - esc = get_escape_char(re); - if ((esc & 0xff) == 0) { - store_char_in_data(r, 0); - store_char_in_data(r, esc >> 8); - } else { - store_char_in_data(r, esc); - } - break; - default: - store_char_in_data(r, (*re)[-1]); - break; - } - - r->error_string = "No closing ']' bracket"; -} - -static void relocate(struct slre *r, int begin, int shift) { - emit(r, END); - memmove(r->code + begin + shift, r->code + begin, r->code_size - begin); - r->code_size += shift; -} - -static void quantifier(struct slre *r, int prev, int op) { - if (r->code[prev] == EXACT && r->code[prev + 2] > 1) { - r->code[prev + 2]--; - emit(r, EXACT); - emit(r, r->code[prev + 1] + r->code[prev + 2]); - emit(r, 1); - prev = r->code_size - 3; - } - relocate(r, prev, 2); - r->code[prev] = op; - set_jump_offset(r, prev + 1, prev); -} - -static void exact_one_char(struct slre *r, int ch) { - emit(r, EXACT); - emit(r, r->data_size); - emit(r, 1); - store_char_in_data(r, ch); -} - -static void fixup_branch(struct slre *r, int fixup) { - if (fixup > 0) { - emit(r, END); - set_jump_offset(r, fixup, fixup - 2); - } -} - -static void compile(struct slre *r, const char **re) { - int op, esc, branch_start, last_op, fixup, cap_no, level; - - fixup = 0; - level = r->num_caps; - branch_start = last_op = r->code_size; - - for (;;) - switch (*(*re)++) { - - case '\0': - (*re)--; - return; - // NOTREACHED - break; - - case '.': - last_op = r->code_size; - emit(r, ANY); - break; - - case '[': - last_op = r->code_size; - anyof(r, re); - break; - - case '\\': - last_op = r->code_size; - esc = get_escape_char(re); - if (esc & 0xff00) { - emit(r, esc >> 8); - } else { - exact_one_char(r, esc); - } - break; - - case '(': - last_op = r->code_size; - cap_no = ++r->num_caps; - emit(r, OPEN); - emit(r, cap_no); - - compile(r, re); - if (*(*re)++ != ')') { - r->error_string = "No closing bracket"; - return; - } - - emit(r, CLOSE); - emit(r, cap_no); - break; - - case ')': - (*re)--; - fixup_branch(r, fixup); - if (level == 0) { - r->error_string = "Unbalanced brackets"; - return; - } - return; - // NOTREACHED - break; - - case '+': - case '*': - op = (*re)[-1] == '*' ? STAR: PLUS; - if (**re == '?') { - (*re)++; - op = op == STAR ? STARQ : PLUSQ; - } - quantifier(r, last_op, op); - break; - - case '?': - quantifier(r, last_op, QUEST); - break; - - case '|': - fixup_branch(r, fixup); - relocate(r, branch_start, 3); - r->code[branch_start] = BRANCH; - set_jump_offset(r, branch_start + 1, branch_start); - fixup = branch_start + 2; - r->code[fixup] = 0xff; - break; - - default: - (*re)--; - last_op = r->code_size; - exact(r, re); - break; - } -} - -// Compile regular expression. If success, 1 is returned. -// If error, 0 is returned and slre.error_string points to the error message. -static const char *compile2(struct slre *r, const char *re) { - r->error_string = NULL; - r->code_size = r->data_size = r->num_caps = r->anchored = 0; - - emit(r, OPEN); // This will capture what matches full RE - emit(r, 0); - - while (*re != '\0') { - compile(r, &re); - } - - if (r->code[2] == BRANCH) { - fixup_branch(r, 4); - } - - emit(r, CLOSE); - emit(r, 0); - emit(r, END); - -#if 0 - static void dump(const struct slre *, FILE *); - dump(r, stdout); -#endif - - return r->error_string; -} - -static const char *match(const struct slre *, int, const char *, int, int *, - struct cap *); - -static void loop_greedy(const struct slre *r, int pc, const char *s, int len, - int *ofs) { - int saved_offset, matched_offset; - - saved_offset = matched_offset = *ofs; - - while (!match(r, pc + 2, s, len, ofs, NULL)) { - saved_offset = *ofs; - if (!match(r, pc + r->code[pc + 1], s, len, ofs, NULL)) { - matched_offset = saved_offset; - } - *ofs = saved_offset; - } - - *ofs = matched_offset; -} - -static void loop_non_greedy(const struct slre *r, int pc, const char *s, - int len, int *ofs) { - int saved_offset = *ofs; - - while (!match(r, pc + 2, s, len, ofs, NULL)) { - saved_offset = *ofs; - if (!match(r, pc + r->code[pc + 1], s, len, ofs, NULL)) - break; - } - - *ofs = saved_offset; -} - -static int is_any_of(const unsigned char *p, int len, const char *s, int *ofs) { - int i, ch; - - ch = s[*ofs]; - - for (i = 0; i < len; i++) - if (p[i] == ch) { - (*ofs)++; - return 1; - } - - return 0; -} - -static int is_any_but(const unsigned char *p, int len, const char *s, - int *ofs) { - int i, ch; - - ch = s[*ofs]; - - for (i = 0; i < len; i++) - if (p[i] == ch) { - return 0; - } - - (*ofs)++; - return 1; -} - -static int lowercase(const char *s) { - return tolower(* (const unsigned char *) s); -} - -static int casecmp(const void *p1, const void *p2, size_t len) { - const char *s1 = (const char *) p1, *s2 = (const char *) p2; - int diff = 0; - - if (len > 0) - do { - diff = lowercase(s1++) - lowercase(s2++); - } while (diff == 0 && s1[-1] != '\0' && --len > 0); - - return diff; -} - -static const char *match(const struct slre *r, int pc, const char *s, int len, - int *ofs, struct cap *caps) { - int n, saved_offset; - const char *error_string = NULL; - int (*cmp)(const void *string1, const void *string2, size_t len); - - while (error_string == NULL && r->code[pc] != END) { - - assert(pc < r->code_size); - assert(pc < (int) (sizeof(r->code) / sizeof(r->code[0]))); - - switch (r->code[pc]) { - case BRANCH: - saved_offset = *ofs; - error_string = match(r, pc + 3, s, len, ofs, caps); - if (error_string != NULL) { - *ofs = saved_offset; - error_string = match(r, pc + r->code[pc + 1], s, len, ofs, caps); - } - pc += r->code[pc + 2]; - break; - - case EXACT: - error_string = error_no_match; - n = r->code[pc + 2]; // String length - cmp = r->options & SLRE_CASE_INSENSITIVE ? casecmp : memcmp; - if (n <= len - *ofs && !cmp(s + *ofs, r->data + r->code[pc + 1], n)) { - (*ofs) += n; - error_string = NULL; - } - pc += 3; - break; - - case QUEST: - error_string = NULL; - saved_offset = *ofs; - if (match(r, pc + 2, s, len, ofs, caps) != NULL) { - *ofs = saved_offset; - } - pc += r->code[pc + 1]; - break; - - case STAR: - error_string = NULL; - loop_greedy(r, pc, s, len, ofs); - pc += r->code[pc + 1]; - break; - - case STARQ: - error_string = NULL; - loop_non_greedy(r, pc, s, len, ofs); - pc += r->code[pc + 1]; - break; - - case PLUS: - if ((error_string = match(r, pc + 2, s, len, ofs, caps)) != NULL) - break; - - loop_greedy(r, pc, s, len, ofs); - pc += r->code[pc + 1]; - break; - - case PLUSQ: - if ((error_string = match(r, pc + 2, s, len, ofs, caps)) != NULL) - break; - - loop_non_greedy(r, pc, s, len, ofs); - pc += r->code[pc + 1]; - break; - - case SPACE: - error_string = error_no_match; - if (*ofs < len && isspace(((const unsigned char *)s)[*ofs])) { - (*ofs)++; - error_string = NULL; - } - pc++; - break; - - case NONSPACE: - error_string = error_no_match; - if (*ofs data + r->code[pc + 1], r->code[pc + 2], - s, ofs) ? NULL : error_no_match; - pc += 3; - break; - - case ANYBUT: - error_string = error_no_match; - if (*ofs < len) - error_string = is_any_but(r->data + r->code[pc + 1], r->code[pc + 2], - s, ofs) ? NULL : error_no_match; - pc += 3; - break; - - case BOL: - error_string = *ofs == 0 ? NULL : error_no_match; - pc++; - break; - - case EOL: - error_string = *ofs == len ? NULL : error_no_match; - pc++; - break; - - case OPEN: - if (caps != NULL) - caps[r->code[pc + 1]].ptr = s + *ofs; - pc += 2; - break; - - case CLOSE: - if (caps != NULL) - caps[r->code[pc + 1]].len = (s + *ofs) - - caps[r->code[pc + 1]].ptr; - pc += 2; - break; - - case END: - pc++; - break; - - default: - printf("unknown cmd (%d) at %d\n", r->code[pc], pc); - assert(0); - break; - } - } - - return error_string; -} - -// Return 1 if match, 0 if no match. -// If 'captured_substrings' array is not NULL, then it is filled with the -// values of captured substrings. captured_substrings[0] element is always -// a full matched substring. The round bracket captures start from -// captured_substrings[1]. -// It is assumed that the size of captured_substrings array is enough to -// hold all captures. The caller function must make sure it is! So, the -// array_size = number_of_round_bracket_pairs + 1 -static const char *match2(const struct slre *r, const char *buf, int len, - struct cap *caps) { - int i, ofs = 0; - const char *error_string = error_no_match; - - if (r->anchored) { - error_string = match(r, 0, buf, len, &ofs, caps); - } else { - for (i = 0; i < len && error_string != NULL; i++) { - ofs = i; - error_string = match(r, 0, buf, len, &ofs, caps); - } - } - - return error_string; -} - -static const char *capture_float(const struct cap *cap, void *p, size_t len) { - const char *fmt; - char buf[20]; - - switch (len) { - case sizeof(float): fmt = "f"; break; - case sizeof(double): fmt = "lf"; break; - default: return "SLRE_FLOAT: unsupported size"; - } - - sprintf(buf, "%%%d%s", cap->len, fmt); - return sscanf(cap->ptr, buf, p) == 1 ? NULL : "SLRE_FLOAT: capture failed"; -} - -static const char *capture_string(const struct cap *cap, void *p, size_t len) { - if ((int) len <= cap->len) { - return "SLRE_STRING: buffer size too small"; - } - memcpy(p, cap->ptr, cap->len); - ((char *) p)[cap->len] = '\0'; - return NULL; -} - -static const char *capture_int(const struct cap *cap, void *p, size_t len) { - const char *fmt; - char buf[20]; - - switch (len) { - case sizeof(char): fmt = "hh"; break; - case sizeof(short): fmt = "h"; break; - case sizeof(int): fmt = "d"; break; - default: return "SLRE_INT: unsupported size"; - } - - sprintf(buf, "%%%d%s", cap->len, fmt); - return sscanf(cap->ptr, buf, p) == 1 ? NULL : "SLRE_INT: capture failed"; -} - -static const char *capture(const struct cap *caps, int num_caps, va_list ap) { - int i, type; - size_t size; - void *p; - const char *err = NULL; - - for (i = 0; i < num_caps; i++) { - type = va_arg(ap, int); - size = va_arg(ap, size_t); - p = va_arg(ap, void *); - switch (type) { - case SLRE_INT: err = capture_int(&caps[i], p, size); break; - case SLRE_FLOAT: err = capture_float(&caps[i], p, size); break; - case SLRE_STRING: err = capture_string(&caps[i], p, size); break; - default: err = "Unknown type, expected SLRE_(INT|FLOAT|STRING)"; break; - } - } - return err; -} - -const char *slre_match(enum slre_option options, const char *re, - const char *buf, int buf_len, ...) { - struct slre slre; - struct cap caps[20]; - va_list ap; - const char *error_string = NULL; - - slre.options = options; - if ((error_string = compile2(&slre, re)) == NULL && - (error_string = match2(&slre, buf, buf_len, caps)) == NULL) { - va_start(ap, buf_len); - error_string = capture(caps + 1, slre.num_caps, ap); - va_end(ap); - } - - return error_string; -} diff --git a/vpr7_x2p/vpr/SRC/timing/slre.h b/vpr7_x2p/vpr/SRC/timing/slre.h deleted file mode 100644 index ece4452d3..000000000 --- a/vpr7_x2p/vpr/SRC/timing/slre.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Copyright (c) 2004-2012 Sergey Lyubka - All rights reserved - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - THE SOFTWARE. - - This is a regular expression library that implements a subset of Perl RE. - Please refer to http://slre.googlecode.com for detailed description. - - Supported syntax: - ^ Match beginning of a buffer - $ Match end of a buffer - () Grouping and substring capturing - [...] Match any character from set - [^...] Match any character but ones from set - \s Match whitespace - \S Match non-whitespace - \d Match decimal digit - \r Match carriage return - \n Match newline - + Match one or more times (greedy) - +? Match one or more times (non-greedy) - * Match zero or more times (greedy) - *? Match zero or more times (non-greedy) - ? Match zero or once - \xDD Match byte with hex value 0xDD - \meta Match one of the meta character: ^$().[*+\? - - Match string buffer "buf" of length "buf_len" against "regexp", which should - conform the syntax outlined above. "options" could be either 0 or - SLRE_CASE_INSENSITIVE for case-insensitive match. If regular expression - "regexp" contains brackets, slre_match() will capture the respective - substring into the passed placeholder. Thus, each opening parenthesis - should correspond to three arguments passed: - placeholder_type, placeholder_size, placeholder_address - - Usage example: parsing HTTP request line. - - char method[10], uri[100]; - int http_version_minor, http_version_major; - const char *error; - const char *request = " \tGET /index.html HTTP/1.0\r\n\r\n"; - - error = slre_match(0, "^\\s*(GET|POST)\\s+(\\S+)\\s+HTTP/(\\d)\\.(\\d)", - request, strlen(request), - SLRE_STRING, sizeof(method), method, - SLRE_STRING, sizeof(uri), uri, - SLRE_INT,sizeof(http_version_major),&http_version_major, - SLRE_INT,sizeof(http_version_minor),&http_version_minor); - - if (error != NULL) { - printf("Error parsing HTTP request: %s\n", error); - } else { - printf("Requested URI: %s\n", uri); - } - - - Return: - NULL: string matched and all captures successfully made - non-NULL: in this case, the return value is an error string */ - -#ifndef SLRE_H -#define SLRE_H - -enum slre_option {SLRE_CASE_INSENSITIVE = 1}; -enum slre_capture {SLRE_STRING, SLRE_INT, SLRE_FLOAT}; -const char *slre_match(enum slre_option options, const char *regexp, - const char *buf, int buf_len, ...); - -#endif /* SLRE_H */ diff --git a/vpr7_x2p/vpr/SRC/util/hash.c b/vpr7_x2p/vpr/SRC/util/hash.c deleted file mode 100755 index 8bcb81fcb..000000000 --- a/vpr7_x2p/vpr/SRC/util/hash.c +++ /dev/null @@ -1,200 +0,0 @@ -#include -#include -#include "hash.h" -#include "util.h" - -struct s_hash ** -alloc_hash_table(void) { - - /* Creates a hash table with HASHSIZE different locations (hash values). */ - - struct s_hash **hash_table; - - hash_table = (struct s_hash **) my_calloc(sizeof(struct s_hash *), - HASHSIZE); - return (hash_table); -} - -void free_hash_table(struct s_hash **hash_table) { - - /* Frees all the storage associated with a hash table. */ - - int i; - struct s_hash *h_ptr, *temp_ptr; - - for (i = 0; i < HASHSIZE; i++) { - h_ptr = hash_table[i]; - while (h_ptr != NULL) { - free(h_ptr->name); - temp_ptr = h_ptr->next; - free(h_ptr); - h_ptr = temp_ptr; - } - } - - free(hash_table); -} - -struct s_hash_iterator start_hash_table_iterator(void) { - - /* Call this routine before you start going through all the elements in * - * a hash table. It sets the internal indices to the start of the table. */ - - struct s_hash_iterator hash_iterator; - - hash_iterator.i = -1; - hash_iterator.h_ptr = NULL; - return (hash_iterator); -} - -struct s_hash * -get_next_hash(struct s_hash **hash_table, struct s_hash_iterator *hash_iterator) { - - /* Returns the next occupied hash entry, and moves the iterator structure * - * forward so the next call gets the next entry. */ - - int i; - struct s_hash *h_ptr; - - i = hash_iterator->i; - h_ptr = hash_iterator->h_ptr; - - while (h_ptr == NULL) { - i++; - if (i >= HASHSIZE) - return (NULL); /* End of table */ - - h_ptr = hash_table[i]; - } - - hash_iterator->h_ptr = h_ptr->next; - hash_iterator->i = i; - return (h_ptr); -} - -struct s_hash * -insert_in_hash_table(struct s_hash **hash_table, char *name, - int next_free_index) { - - /* Adds the string pointed to by name to the hash table, and returns the * - * hash structure created or updated. If name is already in the hash table * - * the count member of that hash element is incremented. Otherwise a new * - * hash entry with a count of zero and an index of next_free_index is * - * created. */ - - int i; - struct s_hash *h_ptr, *prev_ptr; - - i = hash_value(name); - prev_ptr = NULL; - h_ptr = hash_table[i]; - - while (h_ptr != NULL) { - if (strcmp(h_ptr->name, name) == 0) { - h_ptr->count++; - return (h_ptr); - } - - prev_ptr = h_ptr; - h_ptr = h_ptr->next; - } - - /* Name string wasn't in the hash table. Add it. */ - - h_ptr = (struct s_hash *) my_malloc(sizeof(struct s_hash)); - if (prev_ptr == NULL) { - hash_table[i] = h_ptr; - } else { - prev_ptr->next = h_ptr; - } - h_ptr->next = NULL; - h_ptr->index = next_free_index; - h_ptr->count = 1; - h_ptr->name = (char *) my_malloc((strlen(name) + 1) * sizeof(char)); - strcpy(h_ptr->name, name); - return (h_ptr); -} - -struct s_hash * -get_hash_entry(struct s_hash **hash_table, char *name) { - - /* Returns the hash entry with this name, or NULL if there is no * - * corresponding entry. */ - - int i; - struct s_hash *h_ptr; - - i = hash_value(name); - h_ptr = hash_table[i]; - - while (h_ptr != NULL) { - if (strcmp(h_ptr->name, name) == 0) - return (h_ptr); - - h_ptr = h_ptr->next; - } - - return (NULL); -} - -int hash_value(char *name) { - /* Creates a hash key from a character string. The absolute value is taken * - * for the final val to compensate for long strlen that cause val to * - * overflow. */ - - int i; - int val = 0, mult = 1; - - i = strlen(name); - for (i = strlen(name) - 1; i >= 0; i--) { - val += mult * ((int) name[i]); - mult *= 7; - } - val += (int) name[0]; - val %= HASHSIZE; - - val = abs(val); - return (val); -} - -void get_hash_stats(struct s_hash **hash_table, char *hash_table_name){ - - /* Checks to see how well elements are distributed within the hash table. * - * Will traverse through the hash_table and count the length of the linked * - * list. Will output the hash number, the number of array elements that are * - * NULL, the average number of linked lists and the maximum length of linked * - * lists. */ - - int num_NULL = 0, total_elements = 0, max_num = 0, curr_num; - double avg_num = 0; - int i; - struct s_hash *h_ptr; - - for (i = 0; inext; - } - } - - if (curr_num > max_num) - max_num = curr_num; - - total_elements = total_elements + curr_num; - } - - avg_num = (float) total_elements / ((float)HASHSIZE - (float)num_NULL); - - vpr_printf(TIO_MESSAGE_INFO, "\n"); - vpr_printf(TIO_MESSAGE_INFO, "The hash table '%s' is of size %d.\n", - hash_table_name, HASHSIZE); - vpr_printf(TIO_MESSAGE_INFO, "It has: %d keys that are never used; total of %d elements; an average linked-list length of %.1f; and a maximum linked-list length of %d.\n", - num_NULL, total_elements, avg_num, max_num); - vpr_printf(TIO_MESSAGE_INFO, "\n"); -} diff --git a/vpr7_x2p/vpr/SRC/util/hash.h b/vpr7_x2p/vpr/SRC/util/hash.h deleted file mode 100755 index f35157d14..000000000 --- a/vpr7_x2p/vpr/SRC/util/hash.h +++ /dev/null @@ -1,38 +0,0 @@ -#define HASHSIZE 5000001 - -struct s_hash { - char *name; - int index; - int count; - struct s_hash *next; -}; - -/* name: The string referred to by this hash entry. * - * index: The integer identifier for this entry. * - * count: Number of times an element with this name has been inserted into * - * the table. EXCEPTION: For the structure for blif parsing/reading, * - * blif_hash, value of count is the number of pins on this vpack_net * - * so far. * - * next: A pointer to the next (string,index) entry that mapped to the * - * same hash value, or NULL if there are no more entries. */ - -struct s_hash_iterator { - int i; - struct s_hash *h_ptr; -}; - -/* i: current "line" of the hash table. That is, hash_table[i] is the * - * start of the hash linked list for this hash value. * - * h_ptr: Pointer to the next hash structure to be examined in the * - * iteration. */ - -struct s_hash **alloc_hash_table(void); -void free_hash_table(struct s_hash **hash_table); -struct s_hash_iterator start_hash_table_iterator(void); -struct s_hash *get_next_hash(struct s_hash **hash_table, - struct s_hash_iterator *hash_iterator); -struct s_hash *insert_in_hash_table(struct s_hash **hash_table, char *name, - int next_free_index); -struct s_hash *get_hash_entry(struct s_hash **hash_table, char *name); -int hash_value(char *name); -void get_hash_stats(struct s_hash **hash_table, char *hash_table_name); diff --git a/vpr7_x2p/vpr/SRC/util/heapsort.c b/vpr7_x2p/vpr/SRC/util/heapsort.c deleted file mode 100755 index 75545dc02..000000000 --- a/vpr7_x2p/vpr/SRC/util/heapsort.c +++ /dev/null @@ -1,96 +0,0 @@ -#include "heapsort.h" - -/******************* Subroutines local to heapsort.c ************************/ - -static void add_to_sort_heap(int *heap, float *sort_values, int index, - int heap_tail); - -static int get_top_of_heap_index(int *heap, float *sort_values, int heap_tail, - int start_index); - -/********************* Subroutine definitions *******************************/ - -void heapsort(int *sort_index, float *sort_values, int nelem, int start_index) { - - /* This routine loads sort_index [1..nelem] with nelem values: the indices * - * of the sort_values [1..nelem] array that lead to sort_values[index] being * - * decreasing as one goes through sort_index. Sort_values is not changed. */ - - int i; - - sort_index -= start_index; - sort_values -= start_index; - - /* Build a heap with the *smallest* element at the top. */ - - for (i = 1; i <= nelem; i++) - add_to_sort_heap(sort_index, sort_values, i, i); - - /* Now pull items off the heap, smallest first. As the heap (in sort_index) * - * shrinks, I store the item pulled off (the smallest) in sort_index, * - * starting from the end. The heap and the stored smallest values never * - * overlap, so I get a nice sort-in-place. */ - - for (i = nelem; i >= 1; i--) - sort_index[i] = get_top_of_heap_index(sort_index, sort_values, i, - start_index); - - sort_index += start_index; - sort_values += start_index; -} - -static void add_to_sort_heap(int *heap, float *sort_values, int index, - int heap_tail) { - - /* Adds element index, with value = sort_values[index] to the heap. * - * Heap_tail is the number of elements in the heap *after* the insert. */ - - unsigned int ifrom, ito; /* Making these unsigned helps compiler opts. */ - int temp; - - heap[heap_tail] = index; - ifrom = heap_tail; - ito = ifrom / 2; - - while (ito >= 1 && sort_values[heap[ifrom]] < sort_values[heap[ito]]) { - temp = heap[ito]; - heap[ito] = heap[ifrom]; - heap[ifrom] = temp; - ifrom = ito; - ito = ifrom / 2; - } -} - -static int get_top_of_heap_index(int *heap, float *sort_values, int heap_tail, - int start_index) { - - /* Returns the index of the item at the top of the heap (the smallest one). * - * It then rebuilds the heap. Heap_tail is the number of items on the heap * - * before the top item is deleted. */ - - int index_of_smallest, temp; - unsigned int ifrom, ito, heap_end; - - index_of_smallest = heap[1]; - heap[1] = heap[heap_tail]; - heap_end = heap_tail - 1; /* One item deleted. */ - ifrom = 1; - ito = 2 * ifrom; - - while (ito <= heap_end) { - if (sort_values[heap[ito + 1]] < sort_values[heap[ito]]) - ito++; - - if (sort_values[heap[ito]] > sort_values[heap[ifrom]]) - break; - - temp = heap[ito]; - heap[ito] = heap[ifrom]; - heap[ifrom] = temp; - ifrom = ito; - ito = 2 * ifrom; - } - - /*index must have the start_index subracted to be consistent with the original array*/ - return (index_of_smallest - start_index); -} diff --git a/vpr7_x2p/vpr/SRC/util/heapsort.h b/vpr7_x2p/vpr/SRC/util/heapsort.h deleted file mode 100755 index 08daf2d05..000000000 --- a/vpr7_x2p/vpr/SRC/util/heapsort.h +++ /dev/null @@ -1 +0,0 @@ -void heapsort(int *sort_index, float *sort_values, int nelem, int start_index); diff --git a/vpr7_x2p/vpr/SRC/util/token.c b/vpr7_x2p/vpr/SRC/util/token.c deleted file mode 100755 index 2a7bdf4ef..000000000 --- a/vpr7_x2p/vpr/SRC/util/token.c +++ /dev/null @@ -1,173 +0,0 @@ -/** - * Jason Luu - * July 22, 2009 - * Tokenizer - */ - -#include -#include -#include "util.h" -#include "token.h" -#include "ezxml.h" -#include "read_xml_util.h" - -enum e_token_type GetTokenTypeFromChar(INP enum e_token_type cur_token_type, - INP char cur); - -/* Returns a token list of the text for a given string. */ -t_token *GetTokensFromString(INP const char* inString, OUTP int * num_tokens) { - const char *cur; - t_token * tokens; - int i, in_string_index, prev_in_string_index; - boolean has_null; - enum e_token_type cur_token_type, new_token_type; - - *num_tokens = i = 0; - cur_token_type = TOKEN_NULL; - - if (inString == NULL) { - return NULL; - }; - - cur = inString; - - /* Count number of tokens */ - while (*cur) { - new_token_type = GetTokenTypeFromChar(cur_token_type, *cur); - if (new_token_type != cur_token_type) { - cur_token_type = new_token_type; - if (new_token_type != TOKEN_NULL) { - i++; - } - } - ++cur; - } - *num_tokens = i; - - if (*num_tokens > 0) { - tokens = (t_token*)my_calloc(*num_tokens + 1, sizeof(t_token)); - } else { - return NULL; - } - - /* populate tokens */ - i = 0; - in_string_index = 0; - has_null = TRUE; - prev_in_string_index = 0; - cur_token_type = TOKEN_NULL; - - cur = inString; - - while (*cur) { - - new_token_type = GetTokenTypeFromChar(cur_token_type, *cur); - if (new_token_type != cur_token_type) { - if (!has_null) { - tokens[i - 1].data[in_string_index - prev_in_string_index] = - '\0'; /* NULL the end of the data string */ - has_null = TRUE; - } - if (new_token_type != TOKEN_NULL) { - tokens[i].type = new_token_type; - tokens[i].data = my_strdup(inString + in_string_index); - prev_in_string_index = in_string_index; - has_null = FALSE; - i++; - } - cur_token_type = new_token_type; - } - ++cur; - in_string_index++; - } - - assert(i == *num_tokens); - - tokens[*num_tokens].type = TOKEN_NULL; - tokens[*num_tokens].data = NULL; - - /* Return the list */ - return tokens; -} - -void freeTokens(INP t_token *tokens, INP int num_tokens) { - int i; - for (i = 0; i < num_tokens; i++) { - free(tokens[i].data); - } - free(tokens); -} - -enum e_token_type GetTokenTypeFromChar(INP enum e_token_type cur_token_type, - INP char cur) { - if (IsWhitespace(cur)) { - return TOKEN_NULL; - } else { - if (cur == '[') { - return TOKEN_OPEN_SQUARE_BRACKET; - } else if (cur == ']') { - return TOKEN_CLOSE_SQUARE_BRACKET; - } else if (cur == '{') { - return TOKEN_OPEN_SQUIG_BRACKET; - } else if (cur == '}') { - return TOKEN_CLOSE_SQUIG_BRACKET; - } else if (cur == ':') { - return TOKEN_COLON; - } else if (cur == '.') { - return TOKEN_DOT; - } else if (cur >= '0' && cur <= '9' && cur_token_type != TOKEN_STRING) { - return TOKEN_INT; - } else { - return TOKEN_STRING; - } - } -} - -boolean checkTokenType(INP t_token token, OUTP enum e_token_type token_type) { - if (token.type != token_type) { - return FALSE; - } - return TRUE; -} - -void my_atof_2D(INOUTP float **matrix, INP int max_i, INP int max_j, - INP char *instring) { - int i, j; - char *cur, *cur2, *copy, *final; - - copy = my_strdup(instring); - final = copy; - while (*final != '\0') { - final++; - } - - cur = copy; - i = j = 0; - while (cur != final) { - while (IsWhitespace(*cur) && cur != final) { - if (j == max_j) { - i++; - j = 0; - } - cur++; - } - if (cur == final) { - break; - } - cur2 = cur; - while (!IsWhitespace(*cur2) && cur2 != final) { - cur2++; - } - *cur2 = '\0'; - assert(i < max_i && j < max_j); - matrix[i][j] = atof(cur); - j++; - cur = cur2; - *cur = ' '; - } - - assert((i == max_i && j == 0) || (i == max_i - 1 && j == max_j)); - - free(copy); -} - diff --git a/vpr7_x2p/vpr/SRC/util/token.h b/vpr7_x2p/vpr/SRC/util/token.h deleted file mode 100755 index 8c9dd39eb..000000000 --- a/vpr7_x2p/vpr/SRC/util/token.h +++ /dev/null @@ -1,37 +0,0 @@ -/** - * Jason Luu - * July 22, 2009 - * Tokenizer - */ - -#ifndef TOKEN_H -#define TOKEN_H - -enum e_token_type { - TOKEN_NULL, - TOKEN_STRING, - TOKEN_INT, - TOKEN_OPEN_SQUARE_BRACKET, - TOKEN_CLOSE_SQUARE_BRACKET, - TOKEN_OPEN_SQUIG_BRACKET, - TOKEN_CLOSE_SQUIG_BRACKET, - TOKEN_COLON, - TOKEN_DOT -}; - -struct s_token { - enum e_token_type type; - char *data; -}; -typedef struct s_token t_token; - -t_token *GetTokensFromString(INP const char* inString, OUTP int * num_tokens); - -void freeTokens(INP t_token *tokens, INP int num_tokens); - -boolean checkTokenType(INP t_token token, OUTP enum e_token_type token_type); - -void my_atof_2D(INOUTP float **matrix, INP int max_i, INP int max_j, INP char *instring); - -#endif - diff --git a/vpr7_x2p/vpr/SRC/util/vpr_utils.c b/vpr7_x2p/vpr/SRC/util/vpr_utils.c deleted file mode 100755 index 049eef7c5..000000000 --- a/vpr7_x2p/vpr/SRC/util/vpr_utils.c +++ /dev/null @@ -1,1263 +0,0 @@ -#include -#include -#include "util.h" -#include "vpr_types.h" -#include "physical_types.h" -#include "globals.h" -#include "vpr_utils.h" -#include "cluster_placement.h" -#include "place_macro.h" -#include "string.h" - - -/* This module contains subroutines that are used in several unrelated parts * - * of VPR. They are VPR-specific utility routines. */ - -/* This defines the maximum string length that could be parsed by functions * - * in vpr_utils. */ -#define MAX_STRING_LEN 128 - -/******************** File-scope variables delcarations **********************/ - -/* These three mappings are needed since there are two different netlist * - * conventions - in the cluster level, ports and port pins are used * - * while in the post-pack level, block pins are used. The reason block * - * type is used instead of blocks is to save memories. */ - - /* f_port_from_blk_pin array allow us to quickly find what port a block * - * pin corresponds to. * - * [0...num_types-1][0...blk_pin_count-1] * - * */ -static int ** f_port_from_blk_pin = NULL; - -/* f_port_pin_from_blk_pin array allow us to quickly find what port pin a* - * block pin corresponds to. * - * [0...num_types-1][0...blk_pin_count-1] */ -static int ** f_port_pin_from_blk_pin = NULL; - -/* f_port_pin_to_block_pin array allows us to quickly find what block * - * pin a port pin corresponds to. * - * [0...num_types-1][0...num_ports-1][0...num_port_pins-1] */ -static int *** f_blk_pin_from_port_pin = NULL; - - -/******************** Subroutine declarations ********************************/ - -/* Allocates and loads f_port_from_blk_pin and f_port_pin_from_blk_pin * - * arrays. * - * The arrays are freed in free_placement_structs() */ -static void alloc_and_load_port_pin_from_blk_pin(void); - -/* Allocates and loads blk_pin_from_port_pin array. * - * The arrays are freed in free_placement_structs() */ -static void alloc_and_load_blk_pin_from_port_pin(void); - -/* Go through all the ports in all the blocks to find the port that has the same * - * name as port_name and belongs to the block type that has the name pb_type_name. * - * Then, check that whether start_pin_index and end_pin_index are specified. If * - * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * - * Otherwise, mark down all the pins in that port. */ -static void mark_direct_of_ports (int idirect, int direct_type, char * pb_type_name, - char * port_name, int end_pin_index, int start_pin_index, char * src_string, - int line, int ** idirect_from_blk_pin, int ** direct_type_from_blk_pin); - -/* Mark the pin entry in idirect_from_blk_pin with idirect and the pin entry in * - * direct_type_from_blk_pin with direct_type from start_pin_index to * - * end_pin_index. */ -static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int itype, - int iport, int ** idirect_from_blk_pin, int idirect, - int ** direct_type_from_blk_pin, int direct_type, int line, char * src_string); - -/******************** Subroutine definitions *********************************/ - -/** - * print tabs given number of tabs to file - */ -void print_tabs(FILE * fpout, int num_tab) { - int i; - for (i = 0; i < num_tab; i++) { - fprintf(fpout, "\t"); - } -} - -/* Points the grid structure back to the blocks list */ -void sync_grid_to_blocks(INP int L_num_blocks, - INP const struct s_block block_list[], INP int L_nx, INP int L_ny, - INOUTP struct s_grid_tile **L_grid) { - int i, j, k; - - /* Reset usage and allocate blocks list if needed */ - for (j = 0; j <= (L_ny + 1); ++j) { - for (i = 0; i <= (L_nx + 1); ++i) { - L_grid[i][j].usage = 0; - if (L_grid[i][j].type) { - /* If already allocated, leave it since size doesn't change */ - if (NULL == L_grid[i][j].blocks) { - L_grid[i][j].blocks = (int *) my_malloc( - sizeof(int) * L_grid[i][j].type->capacity); - - /* Set them as unconnected */ - for (k = 0; k < L_grid[i][j].type->capacity; ++k) { - L_grid[i][j].blocks[k] = OPEN; - } - } - } - } - } - - /* Go through each block */ - for (i = 0; i < L_num_blocks; ++i) { - /* Check range of block coords */ - if (block[i].x < 0 || block[i].x > (L_nx + 1) || block[i].y < 0 - || (block[i].y + block[i].type->height - 1) > (L_ny + 1) - || block[i].z < 0 || block[i].z > (block[i].type->capacity)) { - vpr_printf(TIO_MESSAGE_ERROR, "Block %d is at invalid location (%d, %d, %d).\n", - i, block[i].x, block[i].y, block[i].z); - exit(1); - } - - /* Check types match */ - if (block[i].type != L_grid[block[i].x][block[i].y].type) { - vpr_printf(TIO_MESSAGE_ERROR, "A block is in a grid location (%d x %d) with a conflicting type.\n", - block[i].x, block[i].y); - exit(1); - } - - /* Check already in use */ - if (OPEN != L_grid[block[i].x][block[i].y].blocks[block[i].z]) { - vpr_printf(TIO_MESSAGE_ERROR, "Location (%d, %d, %d) is used more than once.\n", - block[i].x, block[i].y, block[i].z); - exit(1); - } - - if (L_grid[block[i].x][block[i].y].offset != 0) { - vpr_printf(TIO_MESSAGE_ERROR, "Large block not aligned in placment for block %d at (%d, %d, %d).", - i, block[i].x, block[i].y, block[i].z); - exit(1); - } - - /* Set the block */ - for (j = 0; j < block[i].type->height; j++) { - L_grid[block[i].x][block[i].y + j].blocks[block[i].z] = i; - L_grid[block[i].x][block[i].y + j].usage++; - assert(L_grid[block[i].x][block[i].y + j].offset == j); - } - } -} - -boolean is_opin(int ipin, t_type_ptr type) { - - /* Returns TRUE if this clb pin is an output, FALSE otherwise. */ - - int iclass; - - iclass = type->pin_class[ipin]; - - if (type->class_inf[iclass].type == DRIVER) - return (TRUE); - else - return (FALSE); -} - -void get_class_range_for_block(INP int iblk, OUTP int *class_low, - OUTP int *class_high) { - /* Assumes that the placement has been done so each block has a set of pins allocated to it */ - t_type_ptr type; - - type = block[iblk].type; - assert(type->num_class % type->capacity == 0); - *class_low = block[iblk].z * (type->num_class / type->capacity); - *class_high = (block[iblk].z + 1) * (type->num_class / type->capacity) - 1; -} - -int get_max_primitives_in_pb_type(t_pb_type *pb_type) { - int i, j; - int max_size, temp_size; - if (pb_type->modes == 0) { - max_size = 1; - } else { - max_size = 0; - temp_size = 0; - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - temp_size += pb_type->modes[i].pb_type_children[j].num_pb - * get_max_primitives_in_pb_type( - &pb_type->modes[i].pb_type_children[j]); - } - if (temp_size > max_size) { - max_size = temp_size; - } - } - } - return max_size; -} - -/* finds maximum number of nets that can be contained in pb_type, this is bounded by the number of driving pins */ -int get_max_nets_in_pb_type(const t_pb_type *pb_type) { - int i, j; - int max_nets, temp_nets; - if (pb_type->modes == 0) { - max_nets = pb_type->num_output_pins; - } else { - max_nets = 0; - for (i = 0; i < pb_type->num_modes; i++) { - temp_nets = 0; - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - temp_nets += pb_type->modes[i].pb_type_children[j].num_pb - * get_max_nets_in_pb_type( - &pb_type->modes[i].pb_type_children[j]); - } - if (temp_nets > max_nets) { - max_nets = temp_nets; - } - } - } - if (pb_type->parent_mode == NULL) { - max_nets += pb_type->num_input_pins + pb_type->num_output_pins - + pb_type->num_clock_pins; - } - return max_nets; -} - -int get_max_depth_of_pb_type(t_pb_type *pb_type) { - int i, j; - int max_depth, temp_depth; - max_depth = pb_type->depth; - for (i = 0; i < pb_type->num_modes; i++) { - for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) { - temp_depth = get_max_depth_of_pb_type( - &pb_type->modes[i].pb_type_children[j]); - if (temp_depth > max_depth) { - max_depth = temp_depth; - } - } - } - return max_depth; -} - -/** - * given a primitive type and a logical block, is the mapping legal - */ -boolean primitive_type_feasible(int iblk, const t_pb_type *cur_pb_type) { - t_model_ports *port; - int i, j; - boolean second_pass; - - if (cur_pb_type == NULL) { - return FALSE; - } - - /* Xifan Tang: return false if this primitive is disabled in the packing */ - if (TRUE == cur_pb_type->parent_mode->disabled_in_packing) { - return FALSE; - } - /* END */ - - /* check if ports are big enough */ - port = logical_block[iblk].model->inputs; - second_pass = FALSE; - while (port || !second_pass) { - /* TODO: This is slow if the number of ports are large, fix if becomes a problem */ - if (!port) { - second_pass = TRUE; - port = logical_block[iblk].model->outputs; - } - for (i = 0; i < cur_pb_type->num_ports; i++) { - if (cur_pb_type->ports[i].model_port == port) { - for (j = cur_pb_type->ports[i].num_pins; j < port->size; j++) { - if (port->dir == IN_PORT && !port->is_clock) { - if (logical_block[iblk].input_nets[port->index][j] - != OPEN) { - return FALSE; - } - } else if (port->dir == OUT_PORT) { - if (logical_block[iblk].output_nets[port->index][j] - != OPEN) { - return FALSE; - } - } else { - assert(port->dir == IN_PORT && port->is_clock); - assert(j == 0); - if (logical_block[iblk].clock_net != OPEN) { - return FALSE; - } - } - } - break; - } - } - if (i == cur_pb_type->num_ports) { - if ((logical_block[iblk].model->inputs != NULL && !second_pass) - || (logical_block[iblk].model->outputs != NULL - && second_pass)) { - /* physical port not found */ - return FALSE; - } - } - if (port) { - port = port->next; - } - } - return TRUE; -} - - -/** - * Return pb_graph_node pin from model port and pin - * NULL if not found - */ -t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(t_model_ports *model_port, int model_pin, t_pb_graph_node *pb_graph_node) { - int i; - - if(model_port->dir == IN_PORT) { - if(model_port->is_clock == FALSE) { - for (i = 0; i < pb_graph_node->num_input_ports; i++) { - if (pb_graph_node->input_pins[i][0].port->model_port == model_port) { - if(pb_graph_node->num_input_pins[i] > model_pin) { - return &pb_graph_node->input_pins[i][model_pin]; - } else { - return NULL; - } - } - } - } else { - for (i = 0; i < pb_graph_node->num_clock_ports; i++) { - if (pb_graph_node->clock_pins[i][0].port->model_port == model_port) { - if(pb_graph_node->num_clock_pins[i] > model_pin) { - return &pb_graph_node->clock_pins[i][model_pin]; - } else { - return NULL; - } - } - } - } - } else { - assert(model_port->dir == OUT_PORT); - for (i = 0; i < pb_graph_node->num_output_ports; i++) { - if (pb_graph_node->output_pins[i][0].port->model_port == model_port) { - if(pb_graph_node->num_output_pins[i] > model_pin) { - return &pb_graph_node->output_pins[i][model_pin]; - } else { - return NULL; - } - } - } - } - return NULL; -} - -t_pb_graph_pin* get_pb_graph_node_pin_from_vpack_net(int inet, int ipin) { - int ilogical_block; - t_model_ports *port; - - ilogical_block = vpack_net[inet].node_block[ipin]; - - assert(ilogical_block != OPEN); - if(logical_block[ilogical_block].pb == NULL) { - /* This net has not been packed yet thus pb_graph_pin does not exist */ - return NULL; - } - - if(ipin > 0) { - port = logical_block[ilogical_block].model->inputs; - if(vpack_net[inet].is_global) { - while(port != NULL) { - if(port->is_clock) { - if(port->index == vpack_net[inet].node_block_port[ipin]) { - break; - } - } - port = port->next; - } - } else { - while(port != NULL) { - if(!port->is_clock) { - if(port->index == vpack_net[inet].node_block_port[ipin]) { - break; - } - } - port = port->next; - } - } - } else { - /* This is an output pin */ - port = logical_block[ilogical_block].model->outputs; - while(port != NULL) { - if(port->index == vpack_net[inet].node_block_port[ipin]) { - break; - } - port = port->next; - } - } - - assert(port != NULL); - return get_pb_graph_node_pin_from_model_port_pin(port, vpack_net[inet].node_block_pin[ipin], logical_block[ilogical_block].pb->pb_graph_node); -} - -t_pb_graph_pin* get_pb_graph_node_pin_from_clb_net(int inet, int ipin) { - int iblock, target_pin; - - iblock = clb_net[inet].node_block[ipin]; - - target_pin = clb_net[inet].node_block_pin[ipin]; - - return get_pb_graph_node_pin_from_block_pin(iblock, target_pin); -} - -t_pb_graph_pin* get_pb_graph_node_pin_from_block_pin(int iblock, int ipin) { - int i, count; - const t_pb_type *pb_type; - t_pb_graph_node *pb_graph_node; - - pb_graph_node = block[iblock].pb->pb_graph_node; - pb_type = pb_graph_node->pb_type; - - /* If this is post-placed, then the ipin may have been shuffled up by the z * num_pins, - bring it back down to 0..num_pins-1 range for easier analysis */ - ipin %= (pb_type->num_input_pins + pb_type->num_output_pins + pb_type->num_clock_pins); - - if(ipin < pb_type->num_input_pins) { - count = ipin; - for(i = 0; i < pb_graph_node->num_input_ports; i++) { - if(count - pb_graph_node->num_input_pins[i] >= 0) { - count -= pb_graph_node->num_input_pins[i]; - } else { - return &pb_graph_node->input_pins[i][count]; - } - } - } else if (ipin < pb_type->num_input_pins + pb_type->num_output_pins) { - count = ipin - pb_type->num_input_pins; - for(i = 0; i < pb_graph_node->num_output_ports; i++) { - if(count - pb_graph_node->num_output_pins[i] >= 0) { - count -= pb_graph_node->num_output_pins[i]; - } else { - return &pb_graph_node->output_pins[i][count]; - } - } - } else { - count = ipin - pb_type->num_input_pins - pb_type->num_output_pins; - for(i = 0; i < pb_graph_node->num_clock_ports; i++) { - if(count - pb_graph_node->num_clock_pins[i] >= 0) { - count -= pb_graph_node->num_clock_pins[i]; - } else { - return &pb_graph_node->clock_pins[i][count]; - } - } - } - assert(0); - return NULL; -} - - -/** - * Determine cost for using primitive within a complex block, should use primitives of low cost before selecting primitives of high cost - For now, assume primitives that have a lot of pins are scarcer than those without so use primitives with less pins before those with more - */ -float compute_primitive_base_cost(INP t_pb_graph_node *primitive) { - return (primitive->pb_type->num_input_pins - + primitive->pb_type->num_output_pins - + primitive->pb_type->num_clock_pins); -} - -int num_ext_inputs_logical_block(int iblk) { - - /* Returns the number of input pins on this logical_block that must be hooked * - * up through external interconnect. That is, the number of input * - * pins used - the number which connect (internally) to the outputs. */ - - int ext_inps, output_net, ipin, opin; - - t_model_ports *port, *out_port; - - /* TODO: process to get ext_inps is slow, should cache in lookup table */ - ext_inps = 0; - port = logical_block[iblk].model->inputs; - while (port) { - if (port->is_clock == FALSE) { - for (ipin = 0; ipin < port->size; ipin++) { - if (logical_block[iblk].input_nets[port->index][ipin] != OPEN) { - ext_inps++; - } - out_port = logical_block[iblk].model->outputs; - while (out_port) { - for (opin = 0; opin < out_port->size; opin++) { - output_net = - logical_block[iblk].output_nets[out_port->index][opin]; - if (output_net == OPEN) - continue; - /* TODO: I could speed things up a bit by computing the number of inputs * - * and number of external inputs for each logic logical_block at the start of * - * clustering and storing them in arrays. Look into if speed is a * - * problem. */ - - if (logical_block[iblk].input_nets[port->index][ipin] - == output_net) { - ext_inps--; - break; - } - } - out_port = out_port->next; - } - } - } - port = port->next; - } - - assert(ext_inps >= 0); - - return (ext_inps); -} - - -void free_cb(t_pb *pb) { - const t_pb_type * pb_type; - int i, total_nodes; - - pb_type = pb->pb_graph_node->pb_type; - - total_nodes = pb->pb_graph_node->total_pb_pins + pb_type->num_input_pins - + pb_type->num_output_pins + pb_type->num_clock_pins; - - for (i = 0; i < total_nodes; i++) { - if (pb->rr_graph[i].edges != NULL) { - free(pb->rr_graph[i].edges); - } - if (pb->rr_graph[i].switches != NULL) { - free(pb->rr_graph[i].switches); - } - } - free(pb->rr_graph); - free_pb(pb); -} - -void free_pb(t_pb *pb) { - const t_pb_type * pb_type; - int i, j, mode; - struct s_linked_vptr *revalid_molecule; - t_pack_molecule *cur_molecule; - - pb_type = pb->pb_graph_node->pb_type; - - if (pb_type->blif_model == NULL) { - mode = pb->mode; - for (i = 0; - i < pb_type->modes[mode].num_pb_type_children - && pb->child_pbs != NULL; i++) { - for (j = 0; - j < pb_type->modes[mode].pb_type_children[i].num_pb - && pb->child_pbs[i] != NULL; j++) { - if (pb->child_pbs[i][j].name != NULL || pb->child_pbs[i][j].child_pbs != NULL) { - free_pb(&pb->child_pbs[i][j]); - } - } - if (pb->child_pbs[i]) - free(pb->child_pbs[i]); - } - if (pb->child_pbs) - free(pb->child_pbs); - pb->child_pbs = NULL; - - if (pb->local_nets != NULL) { - for (i = 0; i < pb->num_local_nets; i++) { - free(pb->local_nets[i].node_block); - free(pb->local_nets[i].node_block_port); - free(pb->local_nets[i].node_block_pin); - if (pb->local_nets[i].name != NULL) { - free(pb->local_nets[i].name); - } - } - free(pb->local_nets); - pb->local_nets = NULL; - } - - if (pb->rr_node_to_pb_mapping != NULL) { - free(pb->rr_node_to_pb_mapping); - pb->rr_node_to_pb_mapping = NULL; - } - - if (pb->name) - free(pb->name); - pb->name = NULL; - } else { - /* Primitive */ - if (pb->name) - free(pb->name); - pb->name = NULL; - if (pb->lut_pin_remap) { - free(pb->lut_pin_remap); - } - pb->lut_pin_remap = NULL; - if (pb->logical_block != OPEN && logical_block != NULL) { - logical_block[pb->logical_block].clb_index = NO_CLUSTER; - logical_block[pb->logical_block].pb = NULL; - /* If any molecules were marked invalid because of this logic block getting packed, mark them valid */ - revalid_molecule = logical_block[pb->logical_block].packed_molecules; - while (revalid_molecule != NULL) { - cur_molecule = (t_pack_molecule*)revalid_molecule->data_vptr; - if (cur_molecule->valid == FALSE) { - for (i = 0; i < get_array_size_of_molecule(cur_molecule); i++) { - if (cur_molecule->logical_block_ptrs[i] != NULL) { - if (cur_molecule->logical_block_ptrs[i]->clb_index != OPEN) { - break; - } - } - } - /* All logical blocks are open for this molecule, place back in queue */ - if (i == get_array_size_of_molecule(cur_molecule)) { - cur_molecule->valid = TRUE; - } - } - revalid_molecule = revalid_molecule->next; - } - } - pb->logical_block = OPEN; - } - free_pb_stats(pb); -} - -void free_pb_stats(t_pb *pb) { - int i; - t_pb_graph_node *pb_graph_node = pb->pb_graph_node; - - if(pb->pb_stats == NULL) { - return; - } - - pb->pb_stats->gain.clear(); - pb->pb_stats->timinggain.clear(); - pb->pb_stats->sharinggain.clear(); - pb->pb_stats->hillgain.clear(); - pb->pb_stats->connectiongain.clear(); - pb->pb_stats->num_pins_of_net_in_pb.clear(); - - if(pb->pb_stats->marked_blocks != NULL) { - for (i = 0; i < pb_graph_node->num_input_pin_class; i++) { - free(pb->pb_stats->input_pins_used[i]); - free(pb->pb_stats->lookahead_input_pins_used[i]); - } - free(pb->pb_stats->input_pins_used); - free(pb->pb_stats->lookahead_input_pins_used); - for (i = 0; i < pb_graph_node->num_output_pin_class; i++) { - free(pb->pb_stats->output_pins_used[i]); - free(pb->pb_stats->lookahead_output_pins_used[i]); - } - free(pb->pb_stats->output_pins_used); - free(pb->pb_stats->lookahead_output_pins_used); - free(pb->pb_stats->feasible_blocks); - free(pb->pb_stats->marked_nets); - free(pb->pb_stats->marked_blocks); - } - pb->pb_stats->marked_blocks = NULL; - delete pb->pb_stats; - pb->pb_stats = NULL; -} - -int ** alloc_and_load_net_pin_index() { - - /* Allocates and loads net_pin_index array, this array allows us to quickly * - * find what pin on the net a block pin corresponds to. Returns the pointer * - * to the 2D net_pin_index array. */ - - int inet, netpin, blk, iblk, ipin, itype, **temp_net_pin_index, max_pins_per_clb = 0; - t_type_ptr type; - - /* Compute required size. */ - for (itype = 0; itype < num_types; itype++) - max_pins_per_clb = std::max(max_pins_per_clb, type_descriptors[itype].num_pins); - - /* Allocate for maximum size. */ - temp_net_pin_index = (int **) alloc_matrix(0, num_blocks - 1, 0, - max_pins_per_clb - 1, sizeof(int)); - - /* Initialize values to OPEN */ - for (iblk = 0; iblk < num_blocks; iblk++) { - type = block[iblk].type; - for (ipin = 0; ipin < type->num_pins; ipin++) { - temp_net_pin_index[iblk][ipin] = OPEN; - } - } - - /* Load the values */ - for (inet = 0; inet < num_nets; inet++) { - if (clb_net[inet].is_global) - continue; - for (netpin = 0; netpin <= clb_net[inet].num_sinks; netpin++) { - blk = clb_net[inet].node_block[netpin]; - temp_net_pin_index[blk][clb_net[inet].node_block_pin[netpin]] = netpin; - } - } - - /* Returns the pointers to the 2D array. */ - return temp_net_pin_index; -} - -/*************************************************************************************** - Y.G.THIEN - 29 AUG 2012 - - * The following functions maps the block pins indices for all block types to the * - * corresponding port indices and port_pin indices. This is necessary since there are * - * different netlist conventions - in the cluster level, ports and port pins are used * - * while in the post-pack level, block pins are used. * - * * - ***************************************************************************************/ - -void get_port_pin_from_blk_pin(int blk_type_index, int blk_pin, int * port, - int * port_pin) { - - /* These two mappings are needed since there are two different netlist * - * conventions - in the cluster level, ports and port pins are used * - * while in the post-pack level, block pins are used. The reason block * - * type is used instead of blocks is that the mapping is the same for * - * blocks belonging to the same block type. * - * * - * f_port_from_blk_pin array allow us to quickly find what port a * - * block pin corresponds to. * - * [0...num_types-1][0...blk_pin_count-1] * - * * - * f_port_pin_from_blk_pin array allow us to quickly find what port * - * pin a block pin corresponds to. * - * [0...num_types-1][0...blk_pin_count-1] */ - - /* If either one of the arrays is not allocated and loaded, it is * - * corrupted, so free both of them. */ - if ((f_port_from_blk_pin == NULL && f_port_pin_from_blk_pin != NULL) - || (f_port_from_blk_pin != NULL && f_port_pin_from_blk_pin == NULL)){ - free_port_pin_from_blk_pin(); - } - - /* If the arrays are not allocated and loaded, allocate it. */ - if (f_port_from_blk_pin == NULL && f_port_pin_from_blk_pin == NULL) { - alloc_and_load_port_pin_from_blk_pin(); - } - - /* Return the port and port_pin for the pin. */ - *port = f_port_from_blk_pin[blk_type_index][blk_pin]; - *port_pin = f_port_pin_from_blk_pin[blk_type_index][blk_pin]; - -} - -void free_port_pin_from_blk_pin(void) { - - /* Frees the f_port_from_blk_pin and f_port_pin_from_blk_pin arrays. * - * * - * This function is called when the file-scope arrays are corrupted. * - * Otherwise, the arrays are freed in free_placement_structs() */ - - int itype; - - if (f_port_from_blk_pin != NULL) { - for (itype = 1; itype < num_types; itype++) { - free(f_port_from_blk_pin[itype]); - } - free(f_port_from_blk_pin); - - f_port_from_blk_pin = NULL; - } - - if (f_port_pin_from_blk_pin != NULL) { - for (itype = 1; itype < num_types; itype++) { - free(f_port_pin_from_blk_pin[itype]); - } - free(f_port_pin_from_blk_pin); - - f_port_pin_from_blk_pin = NULL; - } - -} - -static void alloc_and_load_port_pin_from_blk_pin(void) { - - /* Allocates and loads f_port_from_blk_pin and f_port_pin_from_blk_pin * - * arrays. * - * * - * The arrays are freed in free_placement_structs() */ - - int ** temp_port_from_blk_pin = NULL; - int ** temp_port_pin_from_blk_pin = NULL; - int itype, iblk_pin, iport, iport_pin; - int blk_pin_count, num_port_pins, num_ports; - - /* Allocate and initialize the values to OPEN (-1). */ - temp_port_from_blk_pin = (int **) my_malloc(num_types* sizeof(int*)); - temp_port_pin_from_blk_pin = (int **) my_malloc(num_types* sizeof(int*)); - for (itype = 1; itype < num_types; itype++) { - - blk_pin_count = type_descriptors[itype].num_pins; - - temp_port_from_blk_pin[itype] = (int *) my_malloc(blk_pin_count* sizeof(int)); - temp_port_pin_from_blk_pin[itype] = (int *) my_malloc(blk_pin_count* sizeof(int)); - - for (iblk_pin = 0; iblk_pin < blk_pin_count; iblk_pin++) { - temp_port_from_blk_pin[itype][iblk_pin] = OPEN; - temp_port_pin_from_blk_pin[itype][iblk_pin] = OPEN; - } - } - - /* Load the values */ - /* itype starts from 1 since type_descriptors[0] is the EMPTY_TYPE. */ - for (itype = 1; itype < num_types; itype++) { - - blk_pin_count = 0; - num_ports = type_descriptors[itype].pb_type->num_ports; - - for (iport = 0; iport < num_ports; iport++) { - - num_port_pins = type_descriptors[itype].pb_type->ports[iport].num_pins; - - for (iport_pin = 0; iport_pin < num_port_pins; iport_pin++) { - - temp_port_from_blk_pin[itype][blk_pin_count] = iport; - temp_port_pin_from_blk_pin[itype][blk_pin_count] = iport_pin; - blk_pin_count++; - } - } - } - - /* Sets the file_scope variables to point at the arrays. */ - f_port_from_blk_pin = temp_port_from_blk_pin; - f_port_pin_from_blk_pin = temp_port_pin_from_blk_pin; -} - -void get_blk_pin_from_port_pin(int blk_type_index, int port,int port_pin, - int * blk_pin) { - - /* This mapping is needed since there are two different netlist * - * conventions - in the cluster level, ports and port pins are used * - * while in the post-pack level, block pins are used. The reason block * - * type is used instead of blocks is to save memories. * - * * - * f_port_pin_to_block_pin array allows us to quickly find what block * - * pin a port pin corresponds to. * - * [0...num_types-1][0...num_ports-1][0...num_port_pins-1] */ - - /* If the array is not allocated and loaded, allocate it. */ - if (f_blk_pin_from_port_pin == NULL) { - alloc_and_load_blk_pin_from_port_pin(); - } - - /* Return the port and port_pin for the pin. */ - *blk_pin = f_blk_pin_from_port_pin[blk_type_index][port][port_pin]; - -} - -void free_blk_pin_from_port_pin(void) { - - /* Frees the f_blk_pin_from_port_pin array. * - * * - * This function is called when the arrays are freed in * - * free_placement_structs() */ - - int itype, iport, num_ports; - - if (f_blk_pin_from_port_pin != NULL) { - - for (itype = 1; itype < num_types; itype++) { - num_ports = type_descriptors[itype].pb_type->num_ports; - for (iport = 0; iport < num_ports; iport++) { - free(f_blk_pin_from_port_pin[itype][iport]); - } - free(f_blk_pin_from_port_pin[itype]); - } - free(f_blk_pin_from_port_pin); - - f_blk_pin_from_port_pin = NULL; - } - -} - -static void alloc_and_load_blk_pin_from_port_pin(void) { - - /* Allocates and loads blk_pin_from_port_pin array. * - * * - * The arrays are freed in free_placement_structs() */ - - int *** temp_blk_pin_from_port_pin = NULL; - int itype, iport, iport_pin; - int blk_pin_count, num_port_pins, num_ports; - - /* Allocate and initialize the values to OPEN (-1). */ - temp_blk_pin_from_port_pin = (int ***) my_malloc(num_types * sizeof(int**)); - for (itype = 1; itype < num_types; itype++) { - num_ports = type_descriptors[itype].pb_type->num_ports; - temp_blk_pin_from_port_pin[itype] = (int **) my_malloc(num_ports * sizeof(int*)); - for (iport = 0; iport < num_ports; iport++) { - num_port_pins = type_descriptors[itype].pb_type->ports[iport].num_pins; - temp_blk_pin_from_port_pin[itype][iport] = (int *) my_malloc(num_port_pins * sizeof(int)); - - for(iport_pin = 0; iport_pin < num_port_pins; iport_pin ++) { - temp_blk_pin_from_port_pin[itype][iport][iport_pin] = OPEN; - } - } - } - - /* Load the values */ - /* itype starts from 1 since type_descriptors[0] is the EMPTY_TYPE. */ - for (itype = 1; itype < num_types; itype++) { - blk_pin_count = 0; - num_ports = type_descriptors[itype].pb_type->num_ports; - for (iport = 0; iport < num_ports; iport++) { - num_port_pins = type_descriptors[itype].pb_type->ports[iport].num_pins; - for (iport_pin = 0; iport_pin < num_port_pins; iport_pin++) { - temp_blk_pin_from_port_pin[itype][iport][iport_pin] = blk_pin_count; - blk_pin_count++; - } - } - } - - /* Sets the file_scope variables to point at the arrays. */ - f_blk_pin_from_port_pin = temp_blk_pin_from_port_pin; -} - - -/*************************************************************************************** - Y.G.THIEN - 30 AUG 2012 - - * The following functions parses the direct connections' information obtained from * - * the arch file. Then, the functions map the block pins indices for all block types * - * to the corresponding idirect (the index of the direct connection as specified in * - * the arch file) and direct type (whether this pin is a SOURCE or a SINK for the * - * direct connection). If a pin is not part of any direct connections, the value * - * OPEN (-1) is stored in both entries. * - * * - * The mapping arrays are freed by the caller. Currently, this mapping is only used to * - * load placement macros in place_macro.c * - * * - ***************************************************************************************/ - -void parse_direct_pin_name(char * src_string, int line, int * start_pin_index, - int * end_pin_index, char * pb_type_name, char * port_name){ - - /* Parses out the pb_type_name and port_name from the direct passed in. * - * If the start_pin_index and end_pin_index is specified, parse them too. * - * Return the values parsed by reference. */ - - char source_string[MAX_STRING_LEN+1]; - char * find_format = NULL; - int ichar, match_count; - - // parse out the pb_type and port name, possibly pin_indices - find_format = strstr(src_string,"["); - if (find_format == NULL) { - /* Format "pb_type_name.port_name" */ - *start_pin_index = *end_pin_index = -1; - - strcpy (source_string, src_string); - for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { - if (source_string[ichar] == '.') - source_string[ichar] = ' '; - } - - match_count = sscanf(source_string, "%s %s", pb_type_name, port_name); - if (match_count != 2){ - vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Invalid pin - %s, " - "name should be in the format \"pb_type_name\".\"port_name\" or " - "\"pb_type_name\".\"port_name [end_pin_index:start_pin_index]\". " - " The end_pin_index and start_pin_index can be the same.\n", line, - src_string); - exit(1); - } - } else { - /* Format "pb_type_name.port_name [end_pin_index:start_pin_index]" */ - strcpy (source_string, src_string); - for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { - if (source_string[ichar] == '.') - source_string[ichar] = ' '; - } - - match_count = sscanf(source_string, "%s %s [%d:%d]", - pb_type_name, port_name, - end_pin_index, start_pin_index); - if (match_count != 4){ - vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Invalid pin - %s, " - "name should be in the format \"pb_type_name\".\"port_name\" or " - "\"pb_type_name\".\"port_name [end_pin_index:start_pin_index]\". " - " The end_pin_index and start_pin_index can be the same.\n", line, - src_string); - exit(1); - } - if (*end_pin_index < 0 || *start_pin_index < 0) { - vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Invalid pin - %s, " - "the pin_index [end_pin_index:start_pin_index] should not " - "be a negative value.\n", line, src_string); - exit(1); - } - if ( *end_pin_index < *start_pin_index) { - vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Invalid from_pin - %s, " - "the end_pin_index in [end_pin_index:start_pin_index] should " - "not be less than start_pin_index.\n", line, src_string); - exit(1); - } - } -} - -static void mark_direct_of_pins(int start_pin_index, int end_pin_index, int itype, - int iport, int ** idirect_from_blk_pin, int idirect, - int ** direct_type_from_blk_pin, int direct_type, int line, char * src_string) { - - /* Mark the pin entry in idirect_from_blk_pin with idirect and the pin entry in * - * direct_type_from_blk_pin with direct_type from start_pin_index to * - * end_pin_index. */ - - int iport_pin, iblk_pin; - - // Mark pins with indices from start_pin_index to end_pin_index, inclusive - for (iport_pin = start_pin_index; iport_pin <= end_pin_index; iport_pin++) { - get_blk_pin_from_port_pin(itype, iport, iport_pin, &iblk_pin); - - // Check the fc for the pin, direct chain link only if fc == 0 - if (type_descriptors[itype].Fc[iblk_pin] == 0) { - idirect_from_blk_pin[itype][iblk_pin] = idirect; - - // Check whether the pins are marked, errors out if so - if (direct_type_from_blk_pin[itype][iblk_pin] != OPEN) { - vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Invalid pin - %s, " - "this pin is in more than one direct connection.\n", line, - src_string); - exit(1); - } else { - direct_type_from_blk_pin[itype][iblk_pin] = direct_type; - } - } - } // Finish marking all the pins - -} - -static void mark_direct_of_ports (int idirect, int direct_type, char * pb_type_name, - char * port_name, int end_pin_index, int start_pin_index, char * src_string, - int line, int ** idirect_from_blk_pin, int ** direct_type_from_blk_pin) { - - /* Go through all the ports in all the blocks to find the port that has the same * - * name as port_name and belongs to the block type that has the name pb_type_name. * - * Then, check that whether start_pin_index and end_pin_index are specified. If * - * they are, mark down the pins from start_pin_index to end_pin_index, inclusive. * - * Otherwise, mark down all the pins in that port. */ - - int num_ports, num_port_pins; - int itype, iport; - - // Go through all the block types - for (itype = 1; itype < num_types; itype++) { - - // Find blocks with the same pb_type_name - if (strcmp(type_descriptors[itype].pb_type->name, pb_type_name) == 0) { - num_ports = type_descriptors[itype].pb_type->num_ports; - for (iport = 0; iport < num_ports; iport++) { - // Find ports with the same port_name - if (strcmp(type_descriptors[itype].pb_type->ports[iport].name, port_name) == 0) { - num_port_pins = type_descriptors[itype].pb_type->ports[iport].num_pins; - - // Check whether the end_pin_index is valid - if (end_pin_index > num_port_pins) { - vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Invalid pin - %s, " - "the end_pin_index in [end_pin_index:start_pin_index] should " - "be less than the num_port_pins %d.\n", line, - src_string, num_port_pins); - exit(1); - } - - // Check whether the pin indices are specified - if (start_pin_index >= 0 || end_pin_index >= 0) { - mark_direct_of_pins(start_pin_index, end_pin_index, itype, - iport, idirect_from_blk_pin, idirect, - direct_type_from_blk_pin, direct_type, line, src_string); - } else { - mark_direct_of_pins(0, num_port_pins-1, itype, - iport, idirect_from_blk_pin, idirect, - direct_type_from_blk_pin, direct_type, line, src_string); - } - } // Do nothing if port_name does not match - } // Finish going through all the ports - } // Do nothing if pb_type_name does not match - } // Finish going through all the blocks - -} - -void alloc_and_load_idirect_from_blk_pin(t_direct_inf* directs, int num_directs, - int *** idirect_from_blk_pin, int *** direct_type_from_blk_pin) { - - /* Allocates and loads idirect_from_blk_pin and direct_type_from_blk_pin arrays. * - * * - * For a bus (multiple bits) direct connection, all the pins in the bus are marked. * - * * - * idirect_from_blk_pin array allow us to quickly find pins that could be in a * - * direct connection. Values stored is the index of the possible direct connection * - * as specified in the arch file, OPEN (-1) is stored for pins that could not be * - * part of a direct chain conneciton. * - * * - * direct_type_from_blk_pin array stores the value SOURCE if the pin is the * - * from_pin, SINK if the pin is the to_pin in the direct connection as specified in * - * the arch file, OPEN (-1) is stored for pins that could not be part of a direct * - * chain conneciton. * - * * - * Stores the pointers to the two 2D arrays in the addresses passed in. * - * * - * The two arrays are freed by the caller(s). */ - - int itype, iblk_pin, idirect, num_type_pins; - int ** temp_idirect_from_blk_pin, ** temp_direct_type_from_blk_pin; - - char to_pb_type_name[MAX_STRING_LEN+1], to_port_name[MAX_STRING_LEN+1], - from_pb_type_name[MAX_STRING_LEN+1], from_port_name[MAX_STRING_LEN+1]; - int to_start_pin_index = -1, to_end_pin_index = -1; - int from_start_pin_index = -1, from_end_pin_index = -1; - - /* Allocate and initialize the values to OPEN (-1). */ - temp_idirect_from_blk_pin = (int **) my_malloc(num_types * sizeof(int *)); - temp_direct_type_from_blk_pin = (int **) my_malloc(num_types * sizeof(int *)); - for (itype = 1; itype < num_types; itype++) { - - num_type_pins = type_descriptors[itype].num_pins; - - temp_idirect_from_blk_pin[itype] = (int *) my_malloc(num_type_pins * sizeof(int)); - temp_direct_type_from_blk_pin[itype] = (int *) my_malloc(num_type_pins * sizeof(int)); - - /* Initialize values to OPEN */ - for (iblk_pin = 0; iblk_pin < num_type_pins; iblk_pin++) { - temp_idirect_from_blk_pin[itype][iblk_pin] = OPEN; - temp_direct_type_from_blk_pin[itype][iblk_pin] = OPEN; - } - } - - /* Load the values */ - // Go through directs and find pins with possible direct connections - for (idirect = 0; idirect < num_directs; idirect++) { - - // Parse out the pb_type and port name, possibly pin_indices from from_pin - parse_direct_pin_name(directs[idirect].from_pin, directs[idirect].line, - &from_end_pin_index, &from_start_pin_index, from_pb_type_name, from_port_name); - - // Parse out the pb_type and port name, possibly pin_indices from to_pin - parse_direct_pin_name(directs[idirect].to_pin, directs[idirect].line, - &to_end_pin_index, &to_start_pin_index, to_pb_type_name, to_port_name); - - - /* Now I have all the data that I need, I could go through all the block pins * - * in all the blocks to find all the pins that could have possible direct * - * connections. Mark all down all those pins with the idirect the pins belong * - * to and whether it is a source or a sink of the direct connection. */ - - // Find blocks with the same name as from_pb_type_name and from_port_name - mark_direct_of_ports (idirect, SOURCE, from_pb_type_name, from_port_name, - from_end_pin_index, from_start_pin_index, directs[idirect].from_pin, - directs[idirect].line, - temp_idirect_from_blk_pin, temp_direct_type_from_blk_pin); - - // Then, find blocks with the same name as to_pb_type_name and from_port_name - mark_direct_of_ports (idirect, SINK, to_pb_type_name, to_port_name, - to_end_pin_index, to_start_pin_index, directs[idirect].to_pin, - directs[idirect].line, - temp_idirect_from_blk_pin, temp_direct_type_from_blk_pin); - - } // Finish going through all the directs - - /* Returns the pointer to the 2D arrays by reference. */ - *idirect_from_blk_pin = temp_idirect_from_blk_pin; - *direct_type_from_blk_pin = temp_direct_type_from_blk_pin; - -} - -/** - * Xifan Tang: Move this function from rr_graph.c - * since it is useful and general to parse clb to clb directs - * Parse out which CLB pins should connect directly to which other CLB pins then store that in a clb_to_clb_directs data structure - * This data structure supplements the the info in the "directs" data structure - * TODO: The function that does this parsing in placement is poorly done because it lacks generality on heterogeniety, should replace with this one - */ -t_clb_to_clb_directs * alloc_and_load_clb_to_clb_directs(INP const t_direct_inf *directs, - INP const int num_directs) { - int i, j; - t_clb_to_clb_directs *clb_to_clb_directs; - char *pb_type_name, *port_name; - int start_pin_index, end_pin_index; - t_pb_type *pb_type; - - clb_to_clb_directs = (t_clb_to_clb_directs*)my_calloc(num_directs, sizeof(t_clb_to_clb_directs)); - - pb_type_name = NULL; - port_name = NULL; - - for(i = 0; i < num_directs; i++) { - pb_type_name = (char*)my_malloc((strlen(directs[i].from_pin) + strlen(directs[i].to_pin)) * sizeof(char)); - port_name = (char*)my_malloc((strlen(directs[i].from_pin) + strlen(directs[i].to_pin)) * sizeof(char)); - - // Load from pins - // Parse out the pb_type name, port name, and pin range - parse_direct_pin_name(directs[i].from_pin, directs[i].line, &start_pin_index, &end_pin_index, pb_type_name, port_name); - - // Figure out which type, port, and pin is used - for(j = 0; j < num_types; j++) { - if(strcmp(type_descriptors[j].name, pb_type_name) == 0) { - break; - } - } - assert(j < num_types); - clb_to_clb_directs[i].from_clb_type = &type_descriptors[j]; - pb_type = clb_to_clb_directs[i].from_clb_type->pb_type; - - for(j = 0; j < pb_type->num_ports; j++) { - if(strcmp(pb_type->ports[j].name, port_name) == 0) { - break; - } - } - assert(j < pb_type->num_ports); - - if(start_pin_index == OPEN) { - assert(start_pin_index == end_pin_index); - start_pin_index = 0; - end_pin_index = pb_type->ports[j].num_pins - 1; - } - get_blk_pin_from_port_pin(clb_to_clb_directs[i].from_clb_type->index, j, start_pin_index, &clb_to_clb_directs[i].from_clb_pin_start_index); - get_blk_pin_from_port_pin(clb_to_clb_directs[i].from_clb_type->index, j, end_pin_index, &clb_to_clb_directs[i].from_clb_pin_end_index); - - // Load to pins - // Parse out the pb_type name, port name, and pin range - parse_direct_pin_name(directs[i].to_pin, directs[i].line, &start_pin_index, &end_pin_index, pb_type_name, port_name); - - // Figure out which type, port, and pin is used - for(j = 0; j < num_types; j++) { - if(strcmp(type_descriptors[j].name, pb_type_name) == 0) { - break; - } - } - assert(j < num_types); - clb_to_clb_directs[i].to_clb_type = &type_descriptors[j]; - pb_type = clb_to_clb_directs[i].to_clb_type->pb_type; - - for(j = 0; j < pb_type->num_ports; j++) { - if(strcmp(pb_type->ports[j].name, port_name) == 0) { - break; - } - } - assert(j < pb_type->num_ports); - - if(start_pin_index == OPEN) { - assert(start_pin_index == end_pin_index); - start_pin_index = 0; - end_pin_index = pb_type->ports[j].num_pins - 1; - } - - get_blk_pin_from_port_pin(clb_to_clb_directs[i].to_clb_type->index, j, start_pin_index, &clb_to_clb_directs[i].to_clb_pin_start_index); - get_blk_pin_from_port_pin(clb_to_clb_directs[i].to_clb_type->index, j, end_pin_index, &clb_to_clb_directs[i].to_clb_pin_end_index); - - if(abs(clb_to_clb_directs[i].from_clb_pin_start_index - clb_to_clb_directs[i].from_clb_pin_end_index) != abs(clb_to_clb_directs[i].to_clb_pin_start_index - clb_to_clb_directs[i].to_clb_pin_end_index)) { - vpr_printf(TIO_MESSAGE_ERROR, "[LINE %d] Range mismatch from %s to %s.\n", directs[i].line, directs[i].from_pin, directs[i].to_pin); - exit(1); - } - /* Aurelien: assign point to point parameters */ - clb_to_clb_directs[i].interconnection_type = directs[i].interconnection_type; - clb_to_clb_directs[i].x_dir = directs[i].x_dir; - clb_to_clb_directs[i].y_dir = directs[i].y_dir; - /* Xifan Tang: assign values to x,y,z_offset */ - clb_to_clb_directs[i].x_offset = directs[i].x_offset; - clb_to_clb_directs[i].y_offset = directs[i].y_offset; - clb_to_clb_directs[i].z_offset = directs[i].z_offset; - /* Xifan Tang: give the name */ - clb_to_clb_directs[i].name = my_strdup(directs[i].name); - - free(pb_type_name); - free(port_name); - } - return clb_to_clb_directs; -} diff --git a/vpr7_x2p/vpr/SRC/util/vpr_utils.h b/vpr7_x2p/vpr/SRC/util/vpr_utils.h deleted file mode 100755 index 721b7dec1..000000000 --- a/vpr7_x2p/vpr/SRC/util/vpr_utils.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef VPR_UTILS_H -#define VPR_UTILS_H - -#include "util.h" - -void print_tabs(FILE * fpout, int num_tab); - -boolean is_opin(int ipin, t_type_ptr type); - -void get_class_range_for_block(INP int iblk, OUTP int *class_low, - OUTP int *class_high); - -void sync_grid_to_blocks(INP int L_num_blocks, - INP const struct s_block block_list[], INP int L_nx, INP int L_ny, - INOUTP struct s_grid_tile **L_grid); - -int get_max_primitives_in_pb_type(t_pb_type *pb_type); -int get_max_depth_of_pb_type(t_pb_type *pb_type); -int get_max_nets_in_pb_type(const t_pb_type *pb_type); -boolean primitive_type_feasible(int iblk, const t_pb_type *cur_pb_type); -t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(t_model_ports *model_port, int model_pin, t_pb_graph_node *pb_graph_node); -t_pb_graph_pin* get_pb_graph_node_pin_from_vpack_net(int inet, int ipin); -t_pb_graph_pin* get_pb_graph_node_pin_from_clb_net(int inet, int ipin); -t_pb_graph_pin* get_pb_graph_node_pin_from_block_pin(int iblock, int ipin); -float compute_primitive_base_cost(INP t_pb_graph_node *primitive); -int num_ext_inputs_logical_block(int iblk); - -int ** alloc_and_load_net_pin_index(); - -void get_port_pin_from_blk_pin(int blk_type_index, int blk_pin, int * port, - int * port_pin); -void free_port_pin_from_blk_pin(void); - -void get_blk_pin_from_port_pin(int blk_type_index, int port,int port_pin, - int * blk_pin); -void free_blk_pin_from_port_pin(void); - -void alloc_and_load_idirect_from_blk_pin(t_direct_inf* directs, int num_directs, - int *** idirect_from_blk_pin, int *** direct_type_from_blk_pin); - -void parse_direct_pin_name(char * src_string, int line, int * start_pin_index, - int * end_pin_index, char * pb_type_name, char * port_name); - -t_clb_to_clb_directs *alloc_and_load_clb_to_clb_directs(INP const t_direct_inf *directs, INP const int num_directs); - - -void free_cb(t_pb *pb); -void free_pb_stats(t_pb *pb); -void free_pb(t_pb *pb); - - -#endif - diff --git a/vpr7_x2p/vpr/SpiceNetlists/adder.sp b/vpr7_x2p/vpr/SpiceNetlists/adder.sp deleted file mode 100644 index fd6799f76..000000000 --- a/vpr7_x2p/vpr/SpiceNetlists/adder.sp +++ /dev/null @@ -1,30 +0,0 @@ -* Sub Circuit -* 1-Bit Full-Adder circuit netlist -.subckt adder inA inB Cin Cout Sumout svdd sgnd size=1 -X01 nd1 inA svdd svdd vpr_pmos W='size*beta*wp' L='pl' -X02 nd1 inB svdd svdd vpr_pmos W='size*beta*wp' L='pl' -X03 nd2 inB nd1 svdd vpr_pmos W='size*beta*wp' L='pl' -X04 nco inA nd2 svdd vpr_pmos W='size*beta*wp' L='pl' -X05 nco Cin nd1 svdd vpr_pmos W='size*beta*wp' L='pl' -X06 nco Cin nd3 sgnd vpr_nmos W='size*wn' L='nl' -X07 nd3 inA sgnd sgnd vpr_nmos W='size*wn' L='nl' -X08 nd3 inB sgnd sgnd vpr_nmos W='size*wn' L='nl' -X09 nco inA nd4 sgnd vpr_nmos W='size*wn' L='nl' -X10 nd4 inB sgnd sgnd vpr_nmos W='size*wn' L='nl' -Xo1 nco Cout svdd sgnd inv size='size' -X11 nd5 inA svdd svdd vpr_pmos W='size*beta*wp' L='pl' -X12 nd5 inB svdd svdd vpr_pmos W='size*beta*wp' L='pl' -X13 nd5 Cin svdd svdd vpr_pmos W='size*beta*wp' L='pl' -X14 nd6 inA nd5 svdd vpr_pmos W='size*beta*wp' L='pl' -X15 nd7 inB nd6 svdd vpr_pmos W='size*beta*wp' L='pl' -X16 ndS Cin nd7 svdd vpr_pmos W='size*beta*wp' L='pl' -X23 nds nco nd5 svdd vpr_pmos W='size*beta*wp' L='pl' -X24 nds nco nd8 sgnd vpr_nmos W='size*wn' L='nl' -X17 nd8 inA sgnd sgnd vpr_nmos W='size*wn' L='nl' -X18 nd8 inB sgnd sgnd vpr_nmos W='size*wn' L='nl' -X19 nd8 Cin sgnd sgnd vpr_nmos W='size*wn' L='nl' -X20 ndS Cin nd9 sgnd vpr_nmos W='size*wn' L='nl' -X21 nd9 inA n10 sgnd vpr_nmos W='size*wn' L='nl' -X22 n10 inB sgnd sgnd vpr_nmos W='size*wn' L='nl' -Xo2 nds Sumout svdd sgnd inv size='size' -.eom diff --git a/vpr7_x2p/vpr/SpiceNetlists/ff.sp b/vpr7_x2p/vpr/SpiceNetlists/ff.sp deleted file mode 100644 index e7261a945..000000000 --- a/vpr7_x2p/vpr/SpiceNetlists/ff.sp +++ /dev/null @@ -1,25 +0,0 @@ -* Sub Circuits -* -* Static D Flip-flop -.subckt static_dff set rst clk D Q svdd sgnd size=1 -* Input inverter -Xinv_clk clk clk_b svdd sgnd inv size=size -Xinv_set set set_b svdd sgnd inv size=size -Xinv_rst rst rst_b svdd sgnd inv size=size -Xinv_d D s1_n1 svdd sgnd inv size=size -Xcpt0 s1_n1 s1_n2 clk_b clk svdd sgnd cpt nmos_size='size' pmos_size='size*beta' -Xset0 s1_n2 set_b svdd svdd vpr_pmos L=pl W='size*wp' -Xrst0 s1_n2 rst sgnd sgnd vpr_nmos L=nl W='size*wn' -Xinv1 s1_n2 s1_q svdd sgnd inv size=size -Xinv2 s1_q s1_n3 svdd sgnd inv size=size -Xcpt1 s1_n3 s1_n2 clk clk_b svdd sgnd cpt nmos_size='size' pmos_size='size*beta' -* Stage 2 -R3 s1_q s2_n1 0 -Xcpt2 s2_n1 s2_n2 clk clk_b svdd sgnd cpt nmos_size='size' pmos_size='size*beta' -Xrst1 s2_n2 rst_b svdd svdd vpr_pmos L=pl W='size*wp' -Xset1 s2_n2 set sgnd sgnd vpr_nmos L=nl W='size*wn' -Xinv4 s2_n2 Qb svdd sgnd inv size=size -Xinv5 Qb s2_n3 svdd sgnd inv size=size -Xcpt3 s2_n3 s2_n2 clk_b clk svdd sgnd cpt nmos_size='size' pmos_size='size*beta' -Xinv_out Qb Q svdd sgnd inv size=size -.eom static_dff diff --git a/vpr7_x2p/vpr/SpiceNetlists/ff_tb.sp b/vpr7_x2p/vpr/SpiceNetlists/ff_tb.sp deleted file mode 100644 index efea18da4..000000000 --- a/vpr7_x2p/vpr/SpiceNetlists/ff_tb.sp +++ /dev/null @@ -1,68 +0,0 @@ -Testbench for D-type Flip-flop with set and reset -********************************* -* HSPICE Netlist * -* Author: Xifan TANG * -* Organization: EPFL,LSI * -********************************* -* -* Use Standard CMOS Technology -****** Include Technology Library ****** -.lib '/home/xitang/tangxifan-eda-tools/branches/subvt_fpga/process/tsmc40nm/toplevel_crn45gs_2d5_v1d1_shrink0d9_embedded_usage.l' TOP_TT -****** Transistor Parameters ****** -.param beta=2 -.param nl=4e-08 -.param wn=1.4e-07 -.param pl=4e-08 -.param wp=1.4e-07 - -****** Include subckt netlists: NMOS and PMOS ***** -.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/spice_test/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/spice_test/subckt/inv_buf_trans_gate.sp' - -.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' - -.param clk_freq = 1e9 -*Temperature -.temp 25 -*Global nodes -.global vdd gnd -*Print node capacitance -.option captab -*Print waveforms -.option POST -* Parameters for measurements -.param clk2d=3e-09 -.param clk_pwl=3e-09 -.param clk_pwh=1.5e-08 -.param slew=1e-11 -.param thold=3e-09 -.param vsp=0.9 -* Parameters for Measuring Slew -.param slew_upper_threshold_pct_rise=0.9 -.param slew_lower_threshold_pct_rise=0.1 -.param slew_upper_threshold_pct_fall=0.1 -.param slew_lower_threshold_pct_fall=0.9 -* Parameters for Measuring Delay -.param input_threshold_pct_rise=0.5 -.param input_threshold_pct_fall=0.5 -.param output_threshold_pct_rise=0.5 -.param output_threshold_pct_fall=0.5 - -Xdff[0] set rst clk d q vdd gnd static_dff - -Vsupply vdd gnd 'vsp' -*Stimulates -vset set gnd 0 -vrst rst gnd 0 -vclk_in clk gnd pulse (0 vsp '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq' '0.4875/clk_freq' '1/clk_freq') -* Measuring Clk2Q, Setup Time and Hold Time -vdata D gnd pulse (0 vsp '0.25/clk_freq' '0.025/clk_freq' '0.025/clk_freq' '2*0.4875/clk_freq' '2/clk_freq') - -*Simulation -.tran 1e-15 '10/clk_freq' -.meas tran slew_q trig v(Q) val='slew_lower_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew' -+ targ v(Q) val='slew_upper_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew' -.meas tran clk2q trig v(CLK) val='input_threshold_pct_fall*vsp' rise=2 -+ targ v(Q) val='output_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew' -.end TSPC Flip-flop with set and reset diff --git a/vpr7_x2p/vpr/SpiceNetlists/gate.sp b/vpr7_x2p/vpr/SpiceNetlists/gate.sp deleted file mode 100644 index a97316d56..000000000 --- a/vpr7_x2p/vpr/SpiceNetlists/gate.sp +++ /dev/null @@ -1,16 +0,0 @@ -* Sub Circuit -* OR2 gate -.subckt or2 in0 in1 out svdd sgnd size=1 -Xp0 ntwk_n0 in0 svdd svdd vpr_pmos L=pl W='size*beta*wp' -Xp1 ntwk_n0 in1 ntwk_n1 svdd vpr_pmos L=pl W='size*beta*wp' -Xn0 ntwk_n1 in0 sgnd sgnd vpr_nmos L=nl W='wn*size' -Xn1 ntwk_n1 in1 sgnd sgnd vpr_nmos L=nl W='wn*size' -.eom - -* AND2 gate -.subckt and2 in0 in1 out svdd sgnd size=1 -Xp0 ntwk_n0 in0 svdd svdd vpr_pmos L=pl W='wp*size*beta' -Xp1 ntwk_n0 in1 svdd svdd vpr_pmos L=pl W='wp*size*beta' -Xn0 ntwk_n0 in0 ntwk_n1 sgnd vpr_nmos L=nl W='wn*size' -Xn1 ntwk_n1 in1 sgnd sgnd vpr_nmos L=nl W='wn*size' -.eom diff --git a/vpr7_x2p/vpr/SpiceNetlists/io.sp b/vpr7_x2p/vpr/SpiceNetlists/io.sp deleted file mode 100644 index e5d757b16..000000000 --- a/vpr7_x2p/vpr/SpiceNetlists/io.sp +++ /dev/null @@ -1,11 +0,0 @@ -* Sub Circuit -* IO pads -* When direction = 0, pad <= dout -* When direction = 1, pad => din -.subckt iopad zin dout din pad direction direction_inv svdd sgnd -Xbuf0 pad din_inter svdd sgnd buf size=2 -Xbuf1 dout pad_inter svdd sgnd buf size=2 -*Xinv0 direction direction_inv svdd sgnd inv size=1 -Xcpt0 din_inter din direction direction_inv svdd sgnd cpt -Xcpt1 pad_inter pad direction_inv direction svdd sgnd cpt -.eom iopad diff --git a/vpr7_x2p/vpr/SpiceNetlists/sram.sp b/vpr7_x2p/vpr/SpiceNetlists/sram.sp deleted file mode 100644 index 06d44db99..000000000 --- a/vpr7_x2p/vpr/SpiceNetlists/sram.sp +++ /dev/null @@ -1,10 +0,0 @@ -* Sub Circuit -* SRAM -* Input to force write the stored bit -.subckt sram6T in out outb svdd sgnd size=1 -Xinv0 loop_out loop_outb svdd sgnd inv size=size -Xinv1 loop_outb loop_out svdd sgnd inv size=size -Xout_pt loop_out out svdd sgnd svdd sgnd cpt nmos_size='size' pmos_size='size*beta' -Xoutb_pt loop_outb outb svdd sgnd svdd sgnd cpt -Rin in loop_out 0 -.eom sram6T diff --git a/vpr7_x2p/vpr/VerilogNetlists/adder.v b/vpr7_x2p/vpr/VerilogNetlists/adder.v deleted file mode 100644 index da288c9b9..000000000 --- a/vpr7_x2p/vpr/VerilogNetlists/adder.v +++ /dev/null @@ -1,19 +0,0 @@ -//------ Module: sram6T_blwl -----// -//------ Verilog file: sram.v -----// -//------ Author: Xifan TANG -----// -module adder( -input [0:0] a, // Input a -input [0:0] b, // Input b -input [0:0] cin, // Input cin -output [0:0] cout, // Output carry -output [0:0] sumout // Output sum -); -//wire[1:0] int_calc; - -//assign int_calc = a + b + cin; -//assign cout = int_calc[1]; -//assign sumout = int_calc[0]; - assign sumout = a ^ b ^ cin; - assign cout = (a & b) | (a & cin) | (b & cin); -endmodule - diff --git a/vpr7_x2p/vpr/VerilogNetlists/ff.v b/vpr7_x2p/vpr/VerilogNetlists/ff.v deleted file mode 100644 index cf15dc440..000000000 --- a/vpr7_x2p/vpr/VerilogNetlists/ff.v +++ /dev/null @@ -1,114 +0,0 @@ -//----------------------------------------------------- -// Design Name : static_dff -// File Name : ff.v -// Function : D flip-flop with asyn reset and set -// Coder : Xifan TANG -//----------------------------------------------------- -//------ Include defines: preproc flags ----- -`include "GENERATED_DIR_KEYWORD/SRC/fpga_defines.v" -module static_dff ( -/* Global ports go first */ -input set, // set input -input reset, // Reset input -input clk, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset or posedge set) -if (reset) begin - q_reg <= 1'b0; -end else if (set) begin - q_reg <= 1'b1; -end else begin - q_reg <= D; -end - -// Wire q_reg to Q -assign Q = q_reg; - -endmodule //End Of Module static_dff - -//----------------------------------------------------- -// Design Name : scan_chain_dff -// File Name : ff.v -// Function : D flip-flop with asyn reset and set -// Coder : Xifan TANG -//----------------------------------------------------- -module sc_dff ( -/* Global ports go first */ -input set, // set input -input reset, // Reset input -input clk, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q, // Q output -output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset or posedge set) -if (reset) begin - q_reg <= 1'b0; -end else if (set) begin - q_reg <= 1'b1; -end else begin - q_reg <= D; -end - -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~Q; - -endmodule //End Of Module static_dff - -//----------------------------------------------------- -// Design Name : scan_chain_dff compact -// File Name : ff.v -// Function : Scan-chain D flip-flop without reset and set //Modified to fit Edouards architecture -// Coder : Xifan TANG -//----------------------------------------------------- -module sc_dff_compact ( -/* Global ports go first */ -input reset, // Reset input -//input set, // set input -input clk, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q, // Q output -output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset /*or posedge set*/) -if (reset) begin - q_reg <= 1'b0; -//end else if (set) begin -// q_reg <= 1'b1; -end else begin - q_reg <= D; -end -/* -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~Q; -*/ - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule //End Of Module static_dff diff --git a/vpr7_x2p/vpr/VerilogNetlists/ff_tb.v b/vpr7_x2p/vpr/VerilogNetlists/ff_tb.v deleted file mode 100644 index 183953d95..000000000 --- a/vpr7_x2p/vpr/VerilogNetlists/ff_tb.v +++ /dev/null @@ -1,64 +0,0 @@ -//----------------------------------------------------- -// Design Name : testbench for static_dff -// File Name : ff_tb.v -// Function : D flip-flop with asyn reset and set -// Coder : Xifan TANG -//----------------------------------------------------- -//----- Time scale: simulation time step and accuracy ----- -`timescale 1ns / 1ps - -module static_dff_tb; -// voltage sources -wire set; -reg reset; -reg clk; -reg D; -wire Q; -// Parameters -parameter clk_period = 2; // [ns] a full clock period -parameter half_clk_period = clk_period / 2; // [ns] a half clock period -parameter d_period = 2 * clk_period; // [ns] two clock period -parameter reset_period = 8 * clk_period; // [ns] a full clock period - -// Unit Under Test -static_dff U0 (set, reset, clk, D, Q); - -// Voltage stimuli -// Reset : enable in the first clock cycle and then disabled -initial -begin - reset = 1'b1; - #clk_period reset = ~reset; -end -always -begin - #reset_period reset = ~reset; -end - -// set : alway disabled -assign set = 1'b0; - -// clk: clock generator -initial -begin - clk = 1'b0; -end -always -begin - #half_clk_period clk = ~clk; -end - -// D: input, flip every two clock cycles -initial -begin - D = 1'b0; -end -always -begin - #d_period D = ~D; -end - -// Q is an output -// - -endmodule diff --git a/vpr7_x2p/vpr/VerilogNetlists/io.v b/vpr7_x2p/vpr/VerilogNetlists/io.v deleted file mode 100644 index 9fccdd23d..000000000 --- a/vpr7_x2p/vpr/VerilogNetlists/io.v +++ /dev/null @@ -1,16 +0,0 @@ -//------ Module: iopad -----// -//------ Verilog file: io.v -----// -//------ Author: Xifan TANG -----// -module iopad( -//input zin, // Set output to be Z -input outpad, // Data output -output inpad, // Data input -inout pad, // bi-directional pad -input en // enable signal to control direction of iopad -//input direction_inv // enable signal to control direction of iopad -); - //----- when direction enabled, the signal is propagated from pad to din - assign inpad = en ? pad : 1'bz; - //----- when direction is disabled, the signal is propagated from dout to pad - assign pad = en ? 1'bz : outpad; -endmodule diff --git a/vpr7_x2p/vpr/VerilogNetlists/lb_tb.v b/vpr7_x2p/vpr/VerilogNetlists/lb_tb.v deleted file mode 100644 index 705970fd6..000000000 --- a/vpr7_x2p/vpr/VerilogNetlists/lb_tb.v +++ /dev/null @@ -1,199 +0,0 @@ -//----------------------------------------------------- -// Design Name : testbench for logic blocks -// File Name : lb_tb.v -// Function : Configurable logic block -// Coder : Xifan TANG -//----------------------------------------------------- -//----- Time scale: simulation time step and accuracy ----- -`timescale 1ns / 1ps - -module lb_tb; -// Parameters -parameter SIZE_IN = 40; //---- MUX input size -parameter SIZE_OUT = 10; //---- MUX input size -parameter SIZE_RESERV_BLWL = 49 + 1; //---- MUX input size -parameter SIZE_BLWL = 1019 - 310 + 1; //---- MUX input size -parameter prog_clk_period = 1; // [ns] half clock period -parameter op_clk_period = 1; // [ns] half clock period -parameter config_period = 2 * prog_clk_period; // [ns] One full clock period -parameter operating_period = SIZE_IN * 2 * op_clk_period; // [ns] One full clock period - -// Ports -wire [0:SIZE_IN-1] lb_in; -wire [0:SIZE_IN-1] lb_out; -wire lb_clk; -wire [0:SIZE_RESERV_BLWL-1] reserv_bl; -wire [0:SIZE_RESERV_BLWL-1] reserv_wl; -wire [0:SIZE_BLWL-1] bl; -wire [0:SIZE_BLWL-1] wl; -wire prog_EN; -wire prog_ENb; -wire zin; -wire nequalize; -wire read; -wire clk; -wire Reset; -wire Set; -// Clocks -wire prog_clock; -wire op_clock; - -// Registered port -reg [0:SIZE_IN-1] lb_in_reg; -reg [0:SIZE_RESERV_BLWL-1] reserv_bl_reg; -reg [0:SIZE_RESERV_BLWL-1] reserv_wl_reg; -reg [0:SIZE_BLWL-1] bl_reg; -reg [0:SIZE_BLWL-1] wl_reg; -reg prog_clock_reg; -reg op_clock_reg; - -// Config done signal; -reg config_done; -// Temp register for rotating shift -reg temp; - -// Unit under test -grid_1__1_ U0 ( -zin, -nequalize, -read, -clk, -Reset, -Set, -prog_ENb, -prog_EN, -// Top inputs -lb_in[0], lb_in[4], lb_in[8], lb_in[12], lb_in[16], -lb_in[20], lb_in[24], lb_in[28], lb_in[32], lb_in[36], -// Top outputs -lb_out[0], lb_out[4], lb_out[8], -// Right inputs -lb_in[1], lb_in[5], lb_in[9], lb_in[13], lb_in[17], -lb_in[21], lb_in[25], lb_in[29], lb_in[33], lb_in[37], -// Right outputs -lb_out[1], lb_out[5], lb_out[9], -// Bottom inputs -lb_in[2], lb_in[6], lb_in[10], lb_in[14], lb_in[18], -lb_in[22], lb_in[26], lb_in[30], lb_in[34], lb_in[38], -// Bottom outputs -lb_out[2], lb_out[6], -// Bottom inputs -lb_clk, -// left inputs -lb_in[3], lb_in[7], lb_in[11], lb_in[15], lb_in[19], -lb_in[23], lb_in[27], lb_in[31], lb_in[35], lb_in[39], -// left outputs -lb_out[3], lb_out[7], -reserv_bl, reserv_wl, -bl, wl -); - -// Task: assign BL and WL values -task prog_lb_blwl; - begin - @(posedge prog_clock); - // Rotate left shift - temp = reserv_bl_reg[SIZE_RESERV_BLWL-1]; - //bl_reg = bl_reg >> 1; - reserv_bl_reg[1:SIZE_RESERV_BLWL-1] = reserv_bl_reg[0:SIZE_RESERV_BLWL-2]; - reserv_bl_reg[0] = temp; - end -endtask - -// Task: assign inputs -task op_lb_in; - begin - @(posedge op_clock); - temp = lb_in_reg[SIZE_IN-1]; - lb_in_reg[1:SIZE_IN-1] = lb_in_reg[0:SIZE_IN-2]; - lb_in_reg[0] = temp; - end -endtask - -// Configuration done signal -initial -begin - config_done = 1'b0; -end -// Enabled during config_period, Disabled during op_period -always -begin - #config_period config_done = ~config_done; - #operating_period config_done = ~config_done; -end - -// Programming clocks -initial -begin - prog_clock_reg = 1'b0; -end -always -begin - #prog_clk_period prog_clock_reg = ~prog_clock_reg; -end - -// Operating clocks -initial -begin - op_clock_reg = 1'b0; -end -always -begin - #op_clk_period op_clock_reg = ~op_clock_reg; -end - -// Programming and Operating clocks -assign prog_clock = prog_clock_reg & (~config_done); -assign op_clock = op_clock_reg & config_done; - -// Programming Enable signals -assign prog_EN = prog_clock & (~config_done); -assign prog_ENb = ~prog_EN; - -// Programming phase: BL/WL -initial -begin - // Initialize BL/WL registers - reserv_bl_reg = {SIZE_RESERV_BLWL {1'b0}}; - reserv_bl_reg[0] = 1'b1; - reserv_wl_reg = {SIZE_RESERV_BLWL {1'b0}}; - // Reserved BL/WL - bl_reg = {SIZE_BLWL {1'b0}}; - wl_reg = {SIZE_BLWL {1'b1}}; - //wl_reg[SIZE_BLWL-1] = 1'b1; -end -always wait (~config_done) // Only invoked when config_done is 0 -begin - // Propagate input 1 to the output - // BL[0] = 1, WL[4] = 1 - prog_lb_blwl; -end - -// Operating Phase -initial -begin - lb_in_reg = {SIZE_IN {1'b0}}; - lb_in_reg[0] = 1'b1; // Last bit is 1 initially -end -always wait (config_done) // Only invoked when config_done is 1 -begin - /* Update inputs */ - op_lb_in; -end - -// Wire ports -assign lb_in = lb_in_reg; -assign reserv_bl = reserv_bl_reg; -assign reserv_wl = reserv_wl_reg; -assign bl = bl_reg; -assign wl = wl_reg; - -// Constant ports -assign zin = 1'b0; -assign nequalize = 1'b1; -assign read = 1'b0; -assign clk = op_clock; -assign Reset = ~config_done; -assign Set = 1'b0; - -endmodule diff --git a/vpr7_x2p/vpr/VerilogNetlists/lut6.v b/vpr7_x2p/vpr/VerilogNetlists/lut6.v deleted file mode 100644 index d214e56db..000000000 --- a/vpr7_x2p/vpr/VerilogNetlists/lut6.v +++ /dev/null @@ -1,15 +0,0 @@ -//----------------------------------------------------- -// Design Name : lut6 -// File Name : lut6.v -// Function : 6-input Look Up Table -// Coder : Xifan TANG -//----------------------------------------------------- -module lut6 ( -input [5:0] in, -output out, -input [63:0] sram, -input [63:0] sram_inv); - - assign out = sram[in]; - -endmodule diff --git a/vpr7_x2p/vpr/VerilogNetlists/mux_tb.v b/vpr7_x2p/vpr/VerilogNetlists/mux_tb.v deleted file mode 100644 index 752bab00b..000000000 --- a/vpr7_x2p/vpr/VerilogNetlists/mux_tb.v +++ /dev/null @@ -1,85 +0,0 @@ -//----------------------------------------------------- -// Design Name : testbench for 2-level SRAM MUX -// File Name : mux_tb.v -// Function : SRAM-based 2-level MUXes -// Coder : Xifan TANG -//----------------------------------------------------- -//----- Time scale: simulation time step and accuracy ----- -`timescale 1ns / 1ps - -module cmos_mux2level_tb; -// Parameters -parameter SIZE_OF_MUX = 50; //---- MUX input size -parameter SIZE_OF_SRAM = 16; //---- MUX input size -parameter op_clk_period = 1; // [ns] half clock period -parameter operating_period = SIZE_OF_MUX * 2 * op_clk_period; // [ns] One full clock period - -// voltage sources -wire [0:SIZE_OF_MUX-1] in; -wire out; -wire [0:SIZE_OF_SRAM-1] sram; -wire [0:SIZE_OF_SRAM-1] sram_inv; -// clocks -wire op_clock; -// registered ports -reg op_clock_reg; -reg [0:SIZE_OF_MUX-1] in_reg; -reg [0:SIZE_OF_SRAM-1] sram_reg; -reg [0:SIZE_OF_SRAM-1] sram_inv_reg; -// Config done signal; -reg config_done; -// Temp register for rotating shift -reg temp; - -// Unit Under Test -mux_2level_size50 U0 (in, out, sram, sram_inv); - -// Task: assign inputs -task op_mux_input; - begin - @(posedge op_clock); - temp = in_reg[SIZE_OF_MUX-1]; - in_reg[1:SIZE_OF_MUX-1] = in_reg[0:SIZE_OF_MUX-2]; - in_reg[0] = temp; - end -endtask - -// Configuration done signal -initial -begin - config_done = 1'b1; -end - -// Operating clocks -initial -begin - op_clock_reg = 1'b0; -end -always -begin - #op_clk_period op_clock_reg = ~op_clock_reg; -end - -// Programming and Operating clocks -assign op_clock = op_clock_reg & config_done; - -// Operating Phase -initial -begin - in_reg = {SIZE_OF_MUX {1'b0}}; - in_reg[0] = 1'b1; // Last bit is 1 initially -end -always wait (config_done) // Only invoked when config_done is 1 -begin - /* Update inputs */ - op_mux_input; -end - -// Wire ports -assign in = in_reg; -assign sram[0:7] = 8'b00010000; -assign sram[8:15] = 8'b00010000; -assign sram_inv = ~sram; - -endmodule - diff --git a/vpr7_x2p/vpr/VerilogNetlists/sram.v b/vpr7_x2p/vpr/VerilogNetlists/sram.v deleted file mode 100644 index 536c1012a..000000000 --- a/vpr7_x2p/vpr/VerilogNetlists/sram.v +++ /dev/null @@ -1,97 +0,0 @@ -//------ Module: sram6T_blwl -----// -//------ Verilog file: sram.v -----// -//------ Author: Xifan TANG -----// -module sram6T_blwl( -//input read, -//input nequalize, -input din, // Data input -output dout, // Data output -output doutb, // Data output -input bl, // Bit line control signal -input wl, // Word line control signal -input blb // Inverted Bit line control signal -); - //----- local variable need to be registered - reg a; - - //----- when wl is enabled, we can read in data from bl - always @(bl, wl) - begin - //----- Cases to program internal memory bit - //----- case 1: bl = 1, wl = 1, a -> 0 - if ((1'b1 == bl)&&(1'b1 == wl)) begin - a <= 1'b1; - end - //----- case 2: bl = 0, wl = 1, a -> 0 - if ((1'b0 == bl)&&(1'b1 == wl)) begin - a <= 1'b0; - end - end - - // dout is short-wired to din - assign dout = a; - //---- doutb is always opposite to dout - assign doutb = ~dout; -`ifdef ENABLE_SIGNAL_INITIALIZATION - initial begin - $deposit(a, $random); - end -`endif -endmodule - -module sram6T_rram( -input read, -input nequalize, -input din, // Data input -output dout, // Data output -output doutb, // Data output -// !!! Port bit position should start from LSB to MSB -// Follow this convention for BL/WLs in each module! -input [0:2] bl, // Bit line control signal -input [0:2] wl// Word line control signal -); - //----- local variable need to be registered - //----- Modeling two RRAMs - reg r0, r1; - - always @(bl[0], wl[2]) - begin - //----- Cases to program r0 - //----- case 1: bl[0] = 1, wl[2] = 1, r0 -> 0 - if ((1'b1 == bl[0])&&(1'b1 == wl[2])) begin - r0 <= 0; - end - end - - always @(bl[2], wl[0]) - begin - //----- case 2: bl[2] = 1, wl[0] = 1, r0 -> 1 - if ((1'b1 == bl[2])&&(1'b1 == wl[0])) begin - r0 <= 1; - end - end - - always @(bl[1], wl[2]) - begin - //----- Cases to program r1 - //----- case 1: bl[1] = 1, wl[2] = 1, r0 -> 0 - if ((1'b1 == bl[1])&&(1'b1 == wl[2])) begin - r1 <= 0; - end - end - - always @( bl[2], wl[1]) - begin - //----- case 2: bl[2] = 1, wl[1] = 1, r0 -> 1 - if ((1'b1 == bl[2])&&(1'b1 == wl[1])) begin - r1 <= 1; - end - end - - // dout is r0 AND r1 - assign dout = r0 | (~r1); - - //---- doutb is always opposite to dout - assign doutb = ~dout; - -endmodule diff --git a/vpr7_x2p/vpr/VerilogNetlists/sram_tb.v b/vpr7_x2p/vpr/VerilogNetlists/sram_tb.v deleted file mode 100644 index 611579f41..000000000 --- a/vpr7_x2p/vpr/VerilogNetlists/sram_tb.v +++ /dev/null @@ -1,88 +0,0 @@ -//----------------------------------------------------- -// Design Name : testbench for static_dff -// File Name : ff_tb.v -// Function : D flip-flop with asyn reset and set -// Coder : Xifan TANG -//----------------------------------------------------- -//----- Time scale: simulation time step and accuracy ----- -`timescale 1ns / 1ps - -module sram6T_rram_tb; -// voltage sources -wire read; -wire nequalize; -wire din; -wire dout; -wire doutb; -reg [0:2] bl; -reg [0:2] wl; -reg prog_clock; - -// Parameters -parameter prog_clk_period = 2; // [ns] a full clock period - -// Unit Under Test -sram6T_rram U0 (read, nequalize, din, dout, doutb, bl, wl); - -// Voltage stimuli -// read : alway disabled -assign read = 1'b0; - -// nequalize: always disabled -assign nequalize = 1'b1; - -// din: always disabled -assign din = 1'b0; - -// Programming clock -initial -begin - prog_clock = 1'b0; -end -always -begin - #prog_clk_period prog_clock = ~prog_clock; -end - -// Task: assign BL and WL values -task prog_blwl; - input [0:2] bl_val; - input [0:2] wl_val; - begin - @(posedge prog_clock); - bl = bl_val; - wl = wl_val; - end -endtask - -// Test two cases: -// 1. Program dout to 0 -// bl[0] = 1, wl[2] = 1 -// bl[2] = 1, wl[0] = 1 -// 2. Program dout to 1 -// bl[1] = 1, wl[2] = 1 -// bl[2] = 1, wl[1] = 1 -initial -begin - bl = 3'b000; - wl = 3'b000; -// 1. Program dout to 0 -// bl[0] = 1, wl[2] = 1 - prog_blwl(3'b100, 3'b001); -// bl[2] = 1, wl[0] = 1 - prog_blwl(3'b001, 3'b100); -// 2. Program dout to 1 -// bl[1] = 1, wl[2] = 1 - prog_blwl(3'b010, 3'b001); -// bl[2] = 1, wl[1] = 1 - prog_blwl(3'b100, 3'b010); -// 3. Program dout to 0 -// bl[0] = 1, wl[2] = 1 - prog_blwl(3'b100, 3'b001); -// bl[2] = 1, wl[0] = 1 - prog_blwl(3'b001, 3'b100); -end - -// Outputs are wired to dout and doutb - -endmodule diff --git a/vpr7_x2p/vpr/go_fpga_spice.sh b/vpr7_x2p/vpr/go_fpga_spice.sh deleted file mode 100755 index e4091f945..000000000 --- a/vpr7_x2p/vpr/go_fpga_spice.sh +++ /dev/null @@ -1,32 +0,0 @@ -#! /bin/csh -f -# Example of how to run vpr - -# Set variables -# For FPGA-Verilog ONLY -set spice_output_dirname = sram_fpga_hetero -set spice_output_dirpath = $PWD -# VPR critical inputs -#set arch_xml_file = ARCH/k6_N10_MD_tsmc40nm_chain_TT.xml -#set arch_xml_file = ARCH/ed_dev.xml -set arch_xml_file = ARCH/k6_N10_SC_tsmc40nm_chain_TT.xml -#set arch_xml_file = ARCH/k6_N10_SC_tsmc40nm_chain_TT_yosys.xml -#set arch_xml_file = ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml -set blif_file = Circuits/s298_prevpr.blif -set act_file = Circuits/s298_prevpr.act -#set blif_file = Circuits/simple_gates_prevpr.blif -#set act_file = Circuits/simple_gates_prevpr.act -set vpr_route_chan_width = 100 - -# Step A: Make sure a clean start -# Recompile if needed -#make clean -#make -j32 -# Remove previous designs -rm -rf $spice_output_dirpath/$spice_output_dirname - -# Run VPR -#valgrind -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_spice --fpga_spice_dir $spice_output_dirpath/$spice_output_dirname --fpga_x2p_rename_illegal_port --fpga_spice_print_top_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_io_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_grid_testbench - - - diff --git a/vpr7_x2p/vpr/go_fpga_verilog.sh b/vpr7_x2p/vpr/go_fpga_verilog.sh deleted file mode 100755 index cb2cb23dc..000000000 --- a/vpr7_x2p/vpr/go_fpga_verilog.sh +++ /dev/null @@ -1,46 +0,0 @@ -#! /bin/csh -f -# Example of how to run vpr - -# Set variables -# For FPGA-Verilog ONLY -set benchmark = s298_prevpr -set verilog_output_dirname = ${benchmark}_Verilog -set verilog_output_dirpath = $PWD -set modelsim_ini_file = /uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini -# VPR critical inputs -#set arch_xml_file = ARCH/k6_N10_MD_tsmc40nm_chain_TT.xml -#set arch_xml_file = ARCH/k8_N10_SC_tsmc40nm_chain_TT_stratixIV_lookalike.xml -#set arch_xml_file = ARCH/k6_N10_sram_chain_HC_template.xml -set arch_xml_file = ARCH/test_arch.xml -#set arch_xml_file = ARCH/ed_stdcell.xml -#set arch_xml_file = ARCH/k6_N10_sram_chain_FC_tsmc40.xml -#set arch_xml_file = ARCH/k6_N10_SC_tsmc40nm_chain_TT.xml -#set arch_xml_file = ARCH/k6_N10_SC_tsmc40nm_chain_TT_yosys.xml -#set arch_xml_file = ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml -#set verilog_reference = ${PWD}/Circuits/alu4_K6_N10_ace.v -#set blif_file = Circuits/shiftReg.blif -#set act_file = Circuits/shiftReg.act -set blif_file = Circuits/$benchmark.blif -set act_file = Circuits/$benchmark.act -set verilog_reference = ${PWD}/Circuits/$benchmark.v -#set blif_file = Circuits/frisc.blif -#set act_file = Circuits/frisc.act -#set blif_file = Circuits/elliptic.blif -#set act_file = Circuits/elliptic.act -set vpr_route_chan_width = 200 - -# Step A: Make sure a clean start -# Recompile if needed -#make clean -#make -j32 -# Remove previous designs -rm -rf $verilog_output_dirpath/$verilog_output_dirname -rm -rf $verilog_output_dirpath/$verilog_output_dirname\_compact - -# Run VPR -#valgrind -echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl" - -echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname\_compact --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl" - - diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh deleted file mode 100755 index 47608013f..000000000 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ /dev/null @@ -1,41 +0,0 @@ -#!/bin/bash -# Example of how to run vpr - -# Set variables -# For FPGA-Verilog ONLY -benchmark="test_modes" -OpenFPGA_path="OPENFPGAPATHKEYWORD" -verilog_output_dirname="${benchmark}_Verilog" -verilog_output_dirpath="$PWD" -tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" -# VPR critical inputs -template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml" -arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml" -blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif" -act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act " -verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v" -vpr_route_chan_width="300" -fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts" -ff_path="$vpr_path/VerilogNetlists/ff.v" -new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v" -ff_keyword="GENERATED_DIR_KEYWORD" -ff_include_path="$verilog_output_dirpath/$verilog_output_dirname" -arch_ff_keyword="FFPATHKEYWORD" - -# Remove previous designs -rm -rf $verilog_output_dirpath/$verilog_output_dirname - -mkdir -p ${OpenFPGA_path}/fpga_flow/arch/generated - -cd $fpga_flow_scripts -perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file -perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path -cd - - -# Run VPR -echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping" -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping - -cd $fpga_flow_scripts -perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path -cd -

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