[FPGA-Bitstream] Reworked the bitstream writer to dump BL/WL words separately

openfpga/src/fpga_bitstream/memory_bank_shift_register_fabric_bitstream.cpp

@@ -12,13 +12,20 @@ size_t MemoryBankShiftRegisterFabricBitstream::num_words() const {
   return bitstream_word_ids_.size();
 }
 
-size_t MemoryBankShiftRegisterFabricBitstream::word_size() const {
+size_t MemoryBankShiftRegisterFabricBitstream::bl_word_size() const {
   /* For a fast runtime, we just inspect the last element
    * It is the validator which should ensure all the words have a uniform size
    */
   return bitstream_word_bls_[bitstream_word_ids_.back()].size();
 }
 
+size_t MemoryBankShiftRegisterFabricBitstream::wl_word_size() const {
+  /* For a fast runtime, we just inspect the last element
+   * It is the validator which should ensure all the words have a uniform size
+   */
+  return bitstream_word_wls_[bitstream_word_ids_.back()].size();
+}
+
 size_t MemoryBankShiftRegisterFabricBitstream::bl_width() const {
   /* For a fast runtime, we just inspect the last element
    * It is the validator which should ensure all the words have a uniform size
@@ -43,16 +50,6 @@ std::vector<std::string> MemoryBankShiftRegisterFabricBitstream::wl_vectors(cons
   return bitstream_word_wls_[word_id];
 }
 
-std::vector<std::string> MemoryBankShiftRegisterFabricBitstream::blwl_vectors(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id) const {
-  VTR_ASSERT(valid_word_id(word_id));
-  std::vector<std::string> blwl_vec = bitstream_word_bls_[word_id];
-  VTR_ASSERT(blwl_vec.size() == bitstream_word_wls_[word_id].size());
-  for (size_t iwl = 0; iwl < bitstream_word_wls_[word_id].size(); ++iwl) {
-    blwl_vec[iwl] += bitstream_word_wls_[word_id][iwl]; 
-  }
-  return blwl_vec;
-}
-
 MemoryBankShiftRegisterFabricBitstreamWordId MemoryBankShiftRegisterFabricBitstream::create_word() {
   /* Create a new id*/
   MemoryBankShiftRegisterFabricBitstreamWordId word_id = MemoryBankShiftRegisterFabricBitstreamWordId(bitstream_word_ids_.size());

openfpga/src/fpga_bitstream/memory_bank_shift_register_fabric_bitstream.h

@@ -28,8 +28,11 @@ class MemoryBankShiftRegisterFabricBitstream {
     /* @brief Return the length of bitstream */
     size_t num_words() const;
 
-    /* @brief Return the length of each word. All the word should have a uniform size */
+    /* @brief Return the length of BL part of each word. All the word should have a uniform size */
-    size_t word_size() const;
+    size_t bl_word_size() const;
+
+    /* @brief Return the length of WL part of each word. All the word should have a uniform size */
+    size_t wl_word_size() const;
 
     /* @brief Return the width of each BL word, which is the number of heads through which a BL word can be loaded in parallel */
     size_t bl_width() const;
@@ -43,9 +46,6 @@ class MemoryBankShiftRegisterFabricBitstream {
     /* @brief Return the WL vectors in a given word id */
     std::vector<std::string> wl_vectors(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id) const;
 
-    /* @brief Return the pair of BL and WL vectors in a given word id */
-    std::vector<std::string> blwl_vectors(const MemoryBankShiftRegisterFabricBitstreamWordId& word_id) const;
-
   public: /* Mutators */
     /* @brief Create a new word */
     MemoryBankShiftRegisterFabricBitstreamWordId create_word();

openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp

@@ -242,7 +242,8 @@ int write_memory_bank_shift_register_fabric_bitstream_to_text_file(std::fstream&
 
   /* Output information about how to intepret the bitstream */
   fp << "// Bitstream word count: " << fabric_bits.num_words() << std::endl;
-  fp << "// Bitstream word size: " << fabric_bits.word_size() << std::endl;
+  fp << "// Bitstream bl word size: " << fabric_bits.bl_word_size() << std::endl;
+  fp << "// Bitstream wl word size: " << fabric_bits.wl_word_size() << std::endl;
   fp << "// Bitstream width (LSB -> MSB): ";
   fp << "<bl shift register heads " << fabric_bits.bl_width() << " bits>";
   fp << "<wl shift register heads " << fabric_bits.wl_width() << " bits>";
@@ -252,11 +253,21 @@ int write_memory_bank_shift_register_fabric_bitstream_to_text_file(std::fstream&
 
   for (const auto& word : fabric_bits.words()) {
     fp << "// Word " << word_cnt << std::endl;
-    /* Write BL/WL address code */
+
-    for (const auto& blwl_vec : fabric_bits.blwl_vectors(word)) {
+    /* Write BL address code */
-      fp << blwl_vec;
+    fp << "// BL part " << std::endl;
+    for (const auto& bl_vec : fabric_bits.bl_vectors(word)) {
+      fp << bl_vec;
       fp << std::endl;
     }
+
+    /* Write WL address code */
+    fp << "// WL part " << std::endl;
+    for (const auto& wl_vec : fabric_bits.wl_vectors(word)) {
+      fp << wl_vec;
+      fp << std::endl;
+    }
+
     word_cnt++;
   }
 

openfpga/src/utils/fabric_bitstream_utils.cpp

@@ -319,6 +319,60 @@ MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(cons
   return fabric_bits;
 }
 
+/********************************************************************
+ * Reshape a list of vectors by aligning all of them to the last element
+ * For example:
+ * - Align vectors to the last element
+ *
+ *   index ---------------------->
+ *   vector 0: 000000001111101010
+ *   vector 1:     00000011010101
+ *   vector 2:   0010101111000110
+ * 
+ * - Fill void in each vector with desired bits (Here assume fill 'x'
+ *   index ---------------------->
+ *   vector 0: 000000001111101010
+ *   vector 1: xxxx00000011010101
+ *   vector 2: xx0010101111000110
+ * 
+ * - Rotate the array by 90 degree
+ *   index ----------------------->
+ *   vector 0: 0xx
+ *   vector 1: 0xx
+ *   ...
+ *   vector N: 010
+ * 
+ *******************************************************************/
+static 
+std::vector<std::string> reshape_bitstream_vectors_to_last_element(const std::vector<std::string>& bitstream_vectors,
+                                                                   const char& default_bit_to_fill) {
+  /* Find the max sizes of BL bits, this determines the size of shift register chain */
+  size_t max_vec_size = 0;
+  for (const auto& vec : bitstream_vectors) {
+    max_vec_size = std::max(max_vec_size, vec.size());
+  }
+  /* Reshape the BL vectors */
+  std::vector<std::string> reshaped_vectors(bitstream_vectors.size(), std::string());
+  size_t col_cnt = 0;
+  for (const auto& vec : bitstream_vectors) {
+    reshaped_vectors[col_cnt].resize(max_vec_size - vec.size(), default_bit_to_fill);
+    reshaped_vectors[col_cnt] += vec;
+    col_cnt++;
+  }
+
+  /* Add the BL word to final bitstream */
+  std::vector<std::string> rotated_vectors;
+  for (size_t irow = 0; irow < max_vec_size; ++irow) {
+    std::string cur_vec;
+    for (size_t icol = 0; icol < reshaped_vectors.size(); ++icol) {
+      cur_vec.push_back(reshaped_vectors[icol][irow]);
+    }
+    rotated_vectors.push_back(cur_vec); 
+  }
+ 
+  return rotated_vectors;
+}
+
 MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_bitstream(const FabricBitstream& fabric_bitstream,
                                                                                          //const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
                                                                                          const bool& bit_value_to_skip) {
@@ -328,41 +382,19 @@ MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_b
   /* Iterate over each word */   
   for (const auto& wl_vec : raw_fabric_bits.wl_vectors()) {
     std::vector<std::string> bl_vec = raw_fabric_bits.bl_vector(wl_vec);
-    /* Find the max sizes of BL/WL bits, this determines the size of shift register chain */
-    size_t max_blwl_sizes = 0;
-    for (const auto& bl_bits : bl_vec) {
-      max_blwl_sizes = std::max(max_blwl_sizes, bl_bits.size());
-    }
-    for (const auto& wl_bits : wl_vec) {
-      max_blwl_sizes = std::max(max_blwl_sizes, wl_bits.size());
-    }
-    /* Reshape the BL and WL vectors */
-    std::vector<std::string> reshaped_blwls(bl_vec.size() + wl_vec.size(), std::string());
-    size_t blwl_col_cnt = 0;
-    for (const auto& bl_bits : bl_vec) {
-      reshaped_blwls[blwl_col_cnt].resize(max_blwl_sizes - bl_bits.size(), '0');
-      reshaped_blwls[blwl_col_cnt] += bl_bits;
-      blwl_col_cnt++;
-    }
-    for (const auto& wl_bits : wl_vec) {
-      reshaped_blwls[blwl_col_cnt].resize(max_blwl_sizes - wl_bits.size(), '0');
-      reshaped_blwls[blwl_col_cnt] += wl_bits;
-      blwl_col_cnt++;
-    }
-    /* Add the word to final bitstream */
-    MemoryBankShiftRegisterFabricBitstreamWordId word_id = fabric_bits.create_word();
-    for (size_t irow = 0; irow < max_blwl_sizes; ++irow) {
-      std::string cur_bl_vec;
-      for (size_t icol = 0; icol < bl_vec.size(); ++icol) {
-        cur_bl_vec.push_back(reshaped_blwls[icol][irow]);
-      }
-      fabric_bits.add_bl_vectors(word_id, cur_bl_vec); 
 
-      std::string cur_wl_vec;
+    MemoryBankShiftRegisterFabricBitstreamWordId word_id = fabric_bits.create_word();
-      for (size_t icol = bl_vec.size(); icol < bl_vec.size() + wl_vec.size(); ++icol) {
+
-        cur_wl_vec.push_back(reshaped_blwls[icol][irow]);
+    std::vector<std::string> reshaped_bl_vectors = reshape_bitstream_vectors_to_last_element(bl_vec, '0');
-      }
+    /* Add the BL word to final bitstream */
-      fabric_bits.add_wl_vectors(word_id, cur_wl_vec);
+    for (const auto& reshaped_bl_vec : reshaped_bl_vectors) {
+      fabric_bits.add_bl_vectors(word_id, reshaped_bl_vec); 
+    }
+
+    std::vector<std::string> reshaped_wl_vectors = reshape_bitstream_vectors_to_last_element(wl_vec, '0');
+    /* Add the BL word to final bitstream */
+    for (const auto& reshaped_wl_vec : reshaped_wl_vectors) {
+      fabric_bits.add_wl_vectors(word_id, reshaped_wl_vec); 
     }
   }