diff --git a/.travis/regression.sh b/.travis/regression.sh index 9ec6dbee1..2552488d6 100755 --- a/.travis/regression.sh +++ b/.travis/regression.sh @@ -13,6 +13,8 @@ cd fpga_flow/scripts perl rewrite_path_in_file.pl -i ../arch/template/k6_N10_sram_chain_HC_template.xml perl rewrite_path_in_file.pl -i ../../vpr7_x2p/vpr/regression_verilog.sh +perl rewrite_path_in_file.pl -i ../../vpr7_x2p/vpr/ +perl rewrite_path_in_file.pl -i ../../vpr7_x2p/vpr/VerilogNetlists/ff.v cd - diff --git a/.travis/script.sh b/.travis/script.sh index 43ec44d20..e0f3f9988 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -19,14 +19,14 @@ else cd build cmake --version cmake .. -DCMAKE_BUILD_TYPE=debug - make -j16 + make -j fi end_section "OpenFPGA.build" $SPACER cd - -source .travis/regression.sh +./.travis/regression.sh #cd fpga_flow #./regression_fpga_flow.sh diff --git a/vpr7_x2p/vpr/VerilogNetlists/ff.v b/vpr7_x2p/vpr/VerilogNetlists/ff.v index 61c1bad7e..b52ba4078 100644 --- a/vpr7_x2p/vpr/VerilogNetlists/ff.v +++ b/vpr7_x2p/vpr/VerilogNetlists/ff.v @@ -5,7 +5,7 @@ // Coder : Xifan TANG //----------------------------------------------------- //------ Include defines: preproc flags ----- -`include "/home/travis/build/LNIS-Projects/OpenFPGA/vpr7_x2p/vpr/test_modes_Verilog/SRC/fpga_defines.v" +`include "OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/test_modes_Verilog/SRC/fpga_defines.v" module static_dff ( /* Global ports go first */ input set, // set input diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index 8e777ebca..f57bfcbf5 100644 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -4,14 +4,15 @@ # Set variables # For FPGA-Verilog ONLY benchmark="test_modes" +OpenFPGA_path="OPENFPGAPATHKEYWORD" verilog_output_dirname="${benchmark}_Verilog" verilog_output_dirpath="$PWD" -modelsim_ini_file="/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini" +tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" # VPR critical inputs -arch_xml_file="OPENFPGAPATHKEYWORD/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml" -blif_file="OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif" -act_file="OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act " -verilog_reference="OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v" +arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml" +blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif" +act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act " +verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v" vpr_route_chan_width="200" # Step A: Make sure a clean start @@ -23,7 +24,5 @@ rm -rf $verilog_output_dirpath/$verilog_output_dirname # Run VPR #valgrind -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis - - +./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis #--fpga_x2p_compact_routing_hierarchy