From b213faaf81abd0a43078f337a39121803d32877f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 29 Oct 2021 13:54:15 -0700 Subject: [PATCH 01/31] [Git] Add YosysHQ as a submodule in the place of QuickLogic Yosys --- .gitmodules | 4 ---- yosys | 1 - 2 files changed, 5 deletions(-) delete mode 160000 yosys diff --git a/.gitmodules b/.gitmodules index 1fb1d4212..e69de29bb 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,4 +0,0 @@ -[submodule "yosys"] - path = yosys - url = https://github.com/QuickLogic-Corp/yosys.git - branch = quicklogic-rebased diff --git a/yosys b/yosys deleted file mode 160000 index f44a4f908..000000000 --- a/yosys +++ /dev/null @@ -1 +0,0 @@ -Subproject commit f44a4f90867b49837da048f9055fdcd8a13c335b From f2ce2e612601bd03b9a4c62d27a59cd5f26ae92f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 29 Oct 2021 14:11:45 -0700 Subject: [PATCH 02/31] [Github] debugging --- .gitmodules | 3 +++ yosys | 1 + 2 files changed, 4 insertions(+) create mode 160000 yosys diff --git a/.gitmodules b/.gitmodules index e69de29bb..5b2a14da5 100644 --- a/.gitmodules +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "yosys"] + path = yosys + url = https://github.com/YosysHQ/yosys diff --git a/yosys b/yosys new file mode 160000 index 000000000..f44a4f908 --- /dev/null +++ b/yosys @@ -0,0 +1 @@ +Subproject commit f44a4f90867b49837da048f9055fdcd8a13c335b From 39fa050b3b13115add5fabe18dd9932da8107925 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 29 Oct 2021 14:13:02 -0700 Subject: [PATCH 03/31] [Github] debugging --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index f44a4f908..c9555c9ad 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit f44a4f90867b49837da048f9055fdcd8a13c335b +Subproject commit c9555c9adeba886a308c60615ac794ec20d9276e From aece87b0c8cc5ed84e11a263e0ad71ccef08637e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 29 Oct 2021 14:15:16 -0700 Subject: [PATCH 04/31] [Github] debugging --- .gitmodules | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitmodules b/.gitmodules index 5b2a14da5..48686a8d6 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,4 @@ [submodule "yosys"] path = yosys url = https://github.com/YosysHQ/yosys + branch = master From 104e177e3714a50d05755134c8f107df90301bc3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 29 Oct 2021 14:17:42 -0700 Subject: [PATCH 05/31] [Git] Update yosys submodule: --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index c9555c9ad..c0edfa878 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit c9555c9adeba886a308c60615ac794ec20d9276e +Subproject commit c0edfa878833f8c6a2a90c3466448783eae3fa28 From e8b3c6856544cc34a32f581ec319c97f15cf6c79 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 29 Oct 2021 14:19:26 -0700 Subject: [PATCH 06/31] [Github] Now use YosysHQ v0.10 release as a submodule --- .gitmodules | 2 +- yosys | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 48686a8d6..6aab6298c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,4 +1,4 @@ [submodule "yosys"] path = yosys url = https://github.com/YosysHQ/yosys - branch = master + branch = release-branch-0.10 diff --git a/yosys b/yosys index c0edfa878..dca8fb54a 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit c0edfa878833f8c6a2a90c3466448783eae3fa28 +Subproject commit dca8fb54aa625f1600e2ccb16f9763c6abfa798f From 9c06041ce4a728ac82bff22beb7febe251848bd6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 11:27:40 -0700 Subject: [PATCH 07/31] [Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff` --- openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys | 2 +- openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys | 2 +- openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys index 7244532e5..a9aa234ee 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys @@ -83,7 +83,7 @@ opt_expr -mux_undef simplemap opt_expr opt_merge -opt_rmdff +opt_dff opt_clean opt diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys index a81474999..ea67a5918 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys @@ -83,7 +83,7 @@ opt_expr -mux_undef simplemap opt_expr opt_merge -opt_rmdff +opt_dff opt_clean opt diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys index 6a8bf372b..ea3037912 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys @@ -67,7 +67,7 @@ opt_expr -mux_undef simplemap opt_expr opt_merge -opt_rmdff +opt_dff opt_clean opt From 0a449cc24ccd74378d2c852d003ad48bb257e059 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 11:45:01 -0700 Subject: [PATCH 08/31] [HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected --- openfpga_flow/openfpga_cell_library/verilog/dff.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v index 2eb5765c9..ea43f113d 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dff.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v @@ -260,7 +260,7 @@ module MULTI_MODE_DFFSRQ ( ); wire post_set = mode[1] ? ~SET : SET; -wire post_reset = mode[0] ? ~RST : RST; +wire post_rst = mode[0] ? ~RST : RST; DFFSRQ FF_CORE (.SET(post_set), .RST(post_rst), @@ -284,7 +284,7 @@ module MULTI_MODE_DFFRQ ( input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity ); -wire post_reset = mode ? ~RST : RST; +wire post_rst = mode ? ~RST : RST; DFFRQ FF_CORE (.RST(post_rst), .CK(CK), From 91627abe12986b0dda6daf6f2452c8072c801d9c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 11:53:46 -0700 Subject: [PATCH 09/31] [FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided --- .../src/fpga_verilog/verilog_formal_random_top_testbench.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 47fc6a13d..3e620cec5 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -143,6 +143,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, const std::string& circuit_name, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); @@ -157,7 +158,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, std::vector(), std::string(FPGA_PORT_POSTFIX), atom_ctx, netlist_annotation, - PinConstraints(), + pin_constraints, explicit_port_mapping); print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------")); @@ -301,6 +302,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, /* Call defined top-level module */ print_verilog_random_testbench_fpga_instance(fp, circuit_name, atom_ctx, netlist_annotation, + pin_constraints, options.explicit_port_mapping()); /* Call defined benchmark */ From 94328351be1fd250fa754e60db1cf2978352a20f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 12:00:06 -0700 Subject: [PATCH 10/31] [Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts --- openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys index 849ea9811..09c4c27a2 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys @@ -74,7 +74,7 @@ opt_expr -mux_undef simplemap opt_expr opt_merge -opt_rmdff +opt_dff opt_clean opt @@ -93,4 +93,4 @@ stat # Output netlists ######################### opt_clean -purge -write_blif ${OUTPUT_BLIF} \ No newline at end of file +write_blif ${OUTPUT_BLIF} From 16de60e9439399b1b7b7e638f131162143472f18 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 12:31:14 -0700 Subject: [PATCH 11/31] [Test] Turn off ACE2 run in bitstream generation only flows --- .../generate_bitstream_fix_device_example_script.openfpga | 2 +- .../generate_bitstream/device_48x48/config/task.conf | 4 ++-- .../generate_bitstream/device_96x96/config/task.conf | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga index 9558a5944..e5c963ecf 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges +link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf index 22f2f94a4..a66a1a273 100644 --- a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf @@ -9,7 +9,7 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true # Runtime of this bitstream generation should not exceed 3 minutes as a QoR requirement @@ -19,7 +19,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_vpr_route_chan_width=50 openfpga_vpr_device_layout=48x48 diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf index 45903d9e6..e5708fba4 100644 --- a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf @@ -9,7 +9,7 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true # Runtime of this bitstream generation should not exceed 6 minutes as a QoR requirement @@ -19,7 +19,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_vpr_route_chan_width=100 openfpga_vpr_device_layout=96x96 From 18bab180328b8a2315f5e2da642c8008dc30f5e0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 13:20:58 -0700 Subject: [PATCH 12/31] [Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release --- .../quicklogic_reg_test.sh | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh index 2d3bd1202..84c76cc9f 100755 --- a/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh @@ -8,12 +8,14 @@ PYTHON_EXEC=python3.8 ############################################## echo -e "QuickLogic regression tests"; -echo -e "Testing yosys flow using custom ys script for running quicklogic device"; -run-task quicklogic_tests/flow_test --debug --show_thread_logs +# TODO: Disabled all the tests here because Quicklogic's synthesis script is not in Yosys v0.10 release. Will bring back once Quicklogic manages to merge their contribution to Yosys upstream -echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device"; -run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs -run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs - -echo -e "Testing yosys flow using custom ys script for adders in quicklogic device"; -run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs +##echo -e "Testing yosys flow using custom ys script for running quicklogic device"; +##run-task quicklogic_tests/flow_test --debug --show_thread_logs +## +##echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device"; +##run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs +##run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs +## +##echo -e "Testing yosys flow using custom ys script for adders in quicklogic device"; +##run-task quicklogic_tests/lut_adder_test --debug --show_thread_logs From 978c60e75bddcec8444c9adf2b9091f0d8f6ea4d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 13:29:38 -0700 Subject: [PATCH 13/31] [Flow] Disable DFFE and SDFF in no-ff Yosys scripts --- .../misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys index ea67a5918..8ecfe2cf0 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys @@ -25,12 +25,12 @@ opt_clean # demote inout ports to input or output port # with follow-up optimizations to clean up AST deminout -opt +opt -nodffe -nosdff opt_expr opt_clean check -opt +opt -nodffe -nosdff wreduce -keepdc peepopt pmuxtree @@ -58,10 +58,10 @@ chtype -set $mul t:$__soft_mul# Extract arithmetic functions techmap alumacc share -opt +opt -nodffe -nosdff fsm # Run a quick follow-up optimization to sweep out unused nets/signals -opt -fast +opt -fast -nodffe -nosdff # Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells memory -nomap opt_clean @@ -78,14 +78,15 @@ opt -undriven -fine ######################### # Map flip-flops ######################### +dfflegalize -cell $_DFF_P_ 0 techmap -map +/adff2dff.v opt_expr -mux_undef simplemap opt_expr opt_merge -opt_dff +opt_dff -nodffe -nosdff opt_clean -opt +opt -nodffe -nosdff ######################### # Map LUTs From 59a622a9108d162f21e83e36fdc77aee82b9cc63 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 14:34:37 -0700 Subject: [PATCH 14/31] [Flow] Disable DFFE and SDFF in no-ff Yosys scripts --- openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys index 09c4c27a2..2ee5138f3 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys @@ -25,12 +25,12 @@ opt_clean # demote inout ports to input or output port # with follow-up optimizations to clean up AST deminout -opt +opt -nodffe -nosdff opt_expr opt_clean check -opt +opt -nodffe -nosdff wreduce -keepdc peepopt pmuxtree @@ -58,10 +58,10 @@ chtype -set $mul t:$__soft_mul# Extract arithmetic functions techmap alumacc share -opt +opt -nodffe -nosdff fsm # Run a quick follow-up optimization to sweep out unused nets/signals -opt -fast +opt -fast -nodffe -nosdff # Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells memory -nomap opt_clean @@ -69,14 +69,15 @@ opt_clean ######################### # Map flip-flops ######################### +dfflegalize -cell $_DFF_P_ 0 techmap -map +/adff2dff.v opt_expr -mux_undef simplemap opt_expr opt_merge -opt_dff +opt_dff -nodffe -nosdff opt_clean -opt +opt -nodffe -nosdff ######################### # Map LUTs From 0b770f3330206b0d0d802bd00b60f9b4dadf4246 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 14:36:43 -0700 Subject: [PATCH 15/31] [Flow] Disable DFFE and SDFF in no-ff Yosys scripts --- .../misc/ys_tmpl_yosys_vpr_bram_flow.ys | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys index ea3037912..764991819 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys @@ -25,12 +25,12 @@ opt_clean # demote inout ports to input or output port # with follow-up optimizations to clean up AST deminout -opt +opt -nodffe -nosdff opt_expr opt_clean check -opt +opt -nodffe -nosdff wreduce -keepdc peepopt pmuxtree @@ -42,10 +42,10 @@ opt_clean # Extract arithmetic functions alumacc share -opt +opt -nodffe -nosdff fsm # Run a quick follow-up optimization to sweep out unused nets/signals -opt -fast +opt -fast -nodffe -nosdff # Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells memory -nomap opt_clean @@ -55,21 +55,22 @@ opt_clean ######################### memory_bram -rules ${YOSYS_BRAM_MAP_RULES} techmap -map ${YOSYS_BRAM_MAP_VERILOG} -opt -fast -mux_undef -undriven -fine +opt -fast -mux_undef -undriven -fine -nodffe -nosdff memory_map -opt -undriven -fine +opt -undriven -fine -nodffe -nosdff ######################### # Map flip-flops ######################### +dfflegalize -cell $_DFF_P_ 0 techmap -map +/adff2dff.v opt_expr -mux_undef simplemap opt_expr opt_merge -opt_dff +opt_dff -nodffe -nosdff opt_clean -opt +opt -nodffe -nosdff ######################### # Map LUTs From ec184ef5324f7e5b6ca7d0a1fd24e932d35544b9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 14:46:12 -0700 Subject: [PATCH 16/31] [Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF --- openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys index aeaded4b5..b4021a084 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys @@ -8,7 +8,23 @@ proc techmap -D NO_LUT -map +/adff2dff.v # Synthesis -synth -top ${TOP_MODULE} -flatten +opt_expr +opt_clean +check +opt -nodffe -nosdff +fsm +opt -nodffe -nosdff +wreduce +peepopt +opt_clean +opt -nodffe -nosdff +memory -nomap +opt_clean +opt -fast -full -nodffe -nosdff +memory_map +opt -full -nodffe -nosdff +techmap +opt -fast -nodffe -nosdff clean # LUT mapping From b7ad61227de9be1d9bbd52c48a9c9677bc6fecc1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 14:47:37 -0700 Subject: [PATCH 17/31] [Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF --- .../ys_tmpl_yosys_vpr_flow_with_rewrite.ys | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys index edcce4c23..f614760dc 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys @@ -8,7 +8,25 @@ proc techmap -D NO_LUT -map +/adff2dff.v # Synthesis -synth -top ${TOP_MODULE} -flatten +opt_expr +opt_clean +check +opt -nodffe -nosdff +fsm +opt -nodffe -nosdff +wreduce +peepopt +opt_clean +opt -nodffe -nosdff +memory -nomap +opt_clean +opt -fast -full -nodffe -nosdff +memory_map +opt -full -nodffe -nosdff +techmap +opt -fast -nodffe -nosdff +clean + clean # LUT mapping From 40d11a45d9edb20193475726fe694873eb5f25ff Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 14:49:56 -0700 Subject: [PATCH 18/31] [Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade --- .../implicit_verilog_example_script.openfpga | 2 +- .../verilog_netlist_formats/implicit_verilog/config/task.conf | 4 ++-- .../implicit_verilog_default_nettype_wire/config/task.conf | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga index 31296021f..6d623e138 100644 --- a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges +link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf index df4d8b854..c0fea17f7 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf @@ -9,7 +9,7 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true timeout_each_job = 20*60 @@ -18,7 +18,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_verilog_default_net_type=none [ARCHITECTURES] diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf index 568ded5e4..079c4f19a 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf @@ -9,7 +9,7 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true timeout_each_job = 20*60 @@ -18,7 +18,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_verilog_default_net_type=wire [ARCHITECTURES] From 8dea7e80e6ba734e5c9db33e0af9383cd8554eca Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 14:56:54 -0700 Subject: [PATCH 19/31] [Flow] Update yosys script to not use sdff and dffe --- .../ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys | 16 ++++++++-------- .../misc/ys_tmpl_yosys_vpr_dff_flow.ys | 18 +++++++++++++++++- 2 files changed, 25 insertions(+), 9 deletions(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys index a9aa234ee..e62587399 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys @@ -25,12 +25,12 @@ opt_clean # demote inout ports to input or output port # with follow-up optimizations to clean up AST deminout -opt +opt -nodffe -nosdff opt_expr opt_clean check -opt +opt -nodffe -nosdff wreduce -keepdc peepopt pmuxtree @@ -58,10 +58,10 @@ chtype -set $mul t:$__soft_mul# Extract arithmetic functions techmap alumacc share -opt +opt -nodffe -nosdff fsm # Run a quick follow-up optimization to sweep out unused nets/signals -opt -fast +opt -fast -nodffe -nosdff # Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells memory -nomap opt_clean @@ -71,9 +71,9 @@ opt_clean ######################### memory_bram -rules ${YOSYS_BRAM_MAP_RULES} techmap -map ${YOSYS_BRAM_MAP_VERILOG} -opt -fast -mux_undef -undriven -fine +opt -fast -mux_undef -undriven -fine -nodffe -nosdff memory_map -opt -undriven -fine +opt -undriven -fine -nodffe -nosdff ######################### # Map flip-flops @@ -83,9 +83,9 @@ opt_expr -mux_undef simplemap opt_expr opt_merge -opt_dff +opt_dff -nodffe -nosdff opt_clean -opt +opt -nodffe -nosdff ######################### # Map LUTs diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys index edd21c94c..cd27e97eb 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys @@ -10,7 +10,23 @@ proc techmap -D NO_LUT -map ${YOSYS_DFF_MAP_VERILOG} # Synthesis -synth -top ${TOP_MODULE} -flatten +opt_expr +opt_clean +check +opt -nodffe -nosdff +fsm +opt -nodffe -nosdff +wreduce +peepopt +opt_clean +opt -nodffe -nosdff +memory -nomap +opt_clean +opt -fast -full -nodffe -nosdff +memory_map +opt -full -nodffe -nosdff +techmap +opt -fast -nodffe -nosdff clean # LUT mapping From ad5cce0ae8c786d688714ff8c6fd448a363022eb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 15:11:07 -0700 Subject: [PATCH 20/31] [Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals --- .../generate_bitstream/device_48x48/config/task.conf | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf index a66a1a273..411380903 100644 --- a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf @@ -18,18 +18,23 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +# VPR parameters openfpga_vpr_route_chan_width=50 openfpga_vpr_device_layout=48x48 [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/* [SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys bench0_top = SAPone [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From e6cc3c494236e7f1e9ca891ed44dde79d356deed Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 15:12:34 -0700 Subject: [PATCH 21/31] [Flow] Enable flatten for dff-related yosys scripts --- openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys | 1 + openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys | 1 + openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys | 1 + 3 files changed, 3 insertions(+) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys index cd27e97eb..8c90e2c30 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys @@ -10,6 +10,7 @@ proc techmap -D NO_LUT -map ${YOSYS_DFF_MAP_VERILOG} # Synthesis +flatten opt_expr opt_clean check diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys index b4021a084..629211c88 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys @@ -8,6 +8,7 @@ proc techmap -D NO_LUT -map +/adff2dff.v # Synthesis +flatten opt_expr opt_clean check diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys index f614760dc..ad1549d25 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys @@ -8,6 +8,7 @@ proc techmap -D NO_LUT -map +/adff2dff.v # Synthesis +flatten opt_expr opt_clean check From be47e78289eb1cfc28ff2009853a84a02c0efa69 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 15:23:19 -0700 Subject: [PATCH 22/31] [Arch] Change arch for Sapone test --- .../device_48x48/config/task.conf | 14 +++++++++----- .../vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml | 7 +++++++ ...eable_adder_chain_dpram8K_dsp36_fracff_40nm.xml | 10 ++++++++++ 3 files changed, 26 insertions(+), 5 deletions(-) diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf index 411380903..959959d3b 100644 --- a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf @@ -18,23 +18,27 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml # Yosys script parameters -yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v -yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v +yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v +yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36 # VPR parameters openfpga_vpr_route_chan_width=50 openfpga_vpr_device_layout=48x48 [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/* [SYNTHESIS_PARAM] -bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys bench0_top = SAPone [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index 5351486bc..a0ff98e49 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -130,6 +130,13 @@ + + + + + + + + + + + + + + +