From 4e254a304d4288428210351fa6bd0072d43d7b6f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 20 Sep 2022 18:10:52 -0700 Subject: [PATCH] [test] now golden netlists have no relationship with OPENFPGA_PATH --- .../golden_outputs_no_time_stamp/fabric_netlists.v | 5 +++-- .../golden_outputs_no_time_stamp/fabric_netlists.v | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_netlists.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_netlists.v index b50cd2830..740b0d1ee 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_netlists.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_netlists.v @@ -11,8 +11,9 @@ `include "fpga_defines.v" // ------ Include user-defined netlists ----- -`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v" -`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/gpio.v" +`include "openfpga_flow/openfpga_cell_library/verilog/dff.v" +`include "/home/tangxifan/temp_to_remove/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v" +`include "openfpga_flow/openfpga_cell_library/verilog/gpio.v" // ------ Include primitive module netlists ----- `include "sub_module/inv_buf_passgate.v" `include "sub_module/arch_encoder.v" diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_netlists.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_netlists.v index a1a38685f..934a2ddc2 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_netlists.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_netlists.v @@ -11,8 +11,9 @@ `include "fpga_defines.v" // ------ Include user-defined netlists ----- -`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v" -`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/gpio.v" +`include "openfpga_flow/openfpga_cell_library/verilog/dff.v" +`include "/home/tangxifan/temp_to_remove/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v" +`include "openfpga_flow/openfpga_cell_library/verilog/gpio.v" // ------ Include primitive module netlists ----- `include "sub_module/inv_buf_passgate.v" `include "sub_module/arch_encoder.v"