From 4dedee4011f23b982fd8fd2f0ce589a170af4ce2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 11 Apr 2024 12:59:13 -0700 Subject: [PATCH] [test] add a new test case to basic reg test to validate write_fabric_pin_physical_location command --- ...reconfig_testbench_example_script.openfpga | 79 +++++++++++++++++++ .../regression_test_scripts/basic_reg_test.sh | 3 + .../config/task.conf | 42 ++++++++++ .../config/tile_config.xml | 1 + 4 files changed, 125 insertions(+) create mode 100644 openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga create mode 100644 openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/tile_config.xml diff --git a/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga new file mode 100644 index 000000000..aeb9572b5 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/group_tile_write_fabric_pin_phy_loc_preconfig_testbench_example_script.openfpga @@ -0,0 +1,79 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose + +# Write fabric phyiscal pin location to file +write_fabric_pin_physical_location --file ${OPENFPGA_FABRIC_PIN_PHY_LOC_FILE} --verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} + +# Write the SDC files for PnR backend +# - Turn on every options here +# FIXME: Not supported yet. +#write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +#write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +#write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 5de03cf86..9aa5b0d8e 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -252,6 +252,9 @@ run-task basic_tests/write_gsb/write_gsb_to_xml_compress_routing $@ run-task basic_tests/write_gsb/write_unique_gsb_to_xml $@ run-task basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing $@ +echo -e "Testing fabric pin physical location file" +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles $@ + echo -e "Testing bus group features"; run-task basic_tests/bus_group/preconfig_testbench_explicit_mapping $@ run-task basic_tests/bus_group/preconfig_testbench_implicit_mapping $@ diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/task.conf b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/task.conf new file mode 100644 index 000000000..25bc71b85 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=auto +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_fabric_pin_phy_loc_file=fabric_pin_phy_loc.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles/config/tile_config.xml @@ -0,0 +1 @@ +