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[doc] update for bottom-left tile organization

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tangxifan 2024-07-07 14:20:26 -07:00
parent 439de61fd0
commit 4da5150a26
2 changed files with 12 additions and 1 deletions
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docs/source/manual/file_formats/tile_config_file.rst
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@ -24,7 +24,7 @@ Detailed syntax are presented as follows.
Specify the style of tile organization. Can be [``top_left`` | ``top_right`` | ``bottom_left`` | ``bottom_right`` | ``custom``] Specify the style of tile organization. Can be [``top_left`` | ``top_right`` | ``bottom_left`` | ``bottom_right`` | ``custom``]
.. warning:: Currently, only ``top_left`` is supported! .. warning:: Currently, only ``top_left`` and ``bottom_left`` are supported!
The ``top_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_top_left` shows an example of tiles in the top-left sytle, where the programmable block locates in the top-left corner of all the tiles, surrounded by two connection blocks and one switch blocks. The ``top_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_top_left` shows an example of tiles in the top-left sytle, where the programmable block locates in the top-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.
@ -37,3 +37,14 @@ Detailed syntax are presented as follows.
An example of top-left style of a tile in FPGA fabric An example of top-left style of a tile in FPGA fabric
The ``bottom_left`` is a shortcut to define the organization for all the tiles. :numref:`fig_tile_style_bottom_left` shows an example of tiles in the bottom-left sytle, where the programmable block locates in the bottom-left corner of all the tiles, surrounded by two connection blocks and one switch blocks.
.. _fig_tile_style_bottom_left:
.. figure:: ./figures/tile_style_bottom_left.png
:width: 100%
:alt: An example of bottom-left style of tile
An example of bottom-left style of a tile in FPGA fabric