From 4cc875a5a5c8f61eb6301e5a83ae451e78c6f846 Mon Sep 17 00:00:00 2001 From: Aur??Lien ALACCHI Date: Thu, 6 Dec 2018 18:00:17 -0700 Subject: [PATCH] fix a bug in wired LUT --- vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c | 6 +++--- vpr7_x2p/vpr/go.sh | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c b/vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c index 31b42ff1f..374d86f5d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c @@ -5900,9 +5900,9 @@ int get_pb_graph_node_wired_lut_logical_block_index(t_pb_graph_node* cur_pb_grap } } /* Make sure we only have 1 used input pin */ - if (1 != num_used_lut_input_pins) { - assert (1 == num_used_lut_input_pins); - } + //if (1 != num_used_lut_input_pins) { + assert (0 < num_used_lut_input_pins); + //} /* vpr_printf(TIO_MESSAGE_INFO, "Wired LUT output vpack_net_num is %d\n", lut_output_vpack_net_num); */ diff --git a/vpr7_x2p/vpr/go.sh b/vpr7_x2p/vpr/go.sh index e9cbbd8de..1eec39a78 100755 --- a/vpr7_x2p/vpr/go.sh +++ b/vpr7_x2p/vpr/go.sh @@ -3,7 +3,7 @@ # Pack, place, and route a heterogeneous FPGA # Packing uses the AAPack algorithm -./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test --fpga_verilog_print_top_testbench +echo "./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test --fpga_verilog_print_top_testbench"