ahoy nice
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@ -60,6 +60,7 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --time_unit ns --flatten_names --file ./SDC
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write_pnr_sdc --time_unit ns --flatten_names --hierarchical --file ./SDC_leaf
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
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