From 4bfd0c0a02ef09962a0b05aaef246307117af922 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 22 Mar 2021 12:53:30 -0600 Subject: [PATCH] [Test] Enable more VTR benchmark in testing --- .../vtr_benchmarks/config/task.conf | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf index d0ba48694..6d22dd9f1 100644 --- a/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf @@ -42,20 +42,16 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v -# Comment out due to high runtime +# Require many different DPRAM modules to be added (each has a different address and data width) #bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU8PEEng.v -# Comment out due to high runtime +# Require many different DPRAM modules to be added (each has a different address and data width) #bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU32PEEng.v -# Comment out due to high runtime +# Require many different DPRAM modules to be added (each has a different address and data width) #bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mcml.v -# Need a custom dual port ram -#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v -# Need a custom dual port ram -#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v -# Synthesis error -#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter4B.v -# Require a custom dual port ram -#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/or1200.v +bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v +bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v +bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter4B.v +bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/or1200.v bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/sha.v bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v