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bug fixed for multiple io types defined in FPGA architectures

This commit is contained in:
tangxifan 2020-03-27 16:32:15 -06:00
parent 7c9c2451f2
commit 4bf0a63ae6
2 changed files with 17 additions and 6 deletions
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6
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -115,9 +115,10 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
/* Collect sink-related information */ /* Collect sink-related information */
vtr::Point<size_t> sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)), vtr::Point<size_t> sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)),
rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode))); rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode)));
size_t sink_grid_pin_index = rr_graph.node_pin_num(module_sb.get_opin_node(side_manager.get_side(), inode));
std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(), std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)), rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)),
src_grid_pin_index); sink_grid_pin_index);
ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id)); VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id));
BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id); BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id);
@ -259,9 +260,10 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
/* Collect sink-related information */ /* Collect sink-related information */
vtr::Point<size_t> sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)), vtr::Point<size_t> sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)),
rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode))); rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode)));
size_t sink_grid_pin_index = rr_graph.node_pin_num(module_sb.get_opin_node(side_manager.get_side(), inode));
std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(), std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)), rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)),
src_grid_pin_index); sink_grid_pin_index);
ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id)); VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id));
BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id); BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id);

17
openfpga/src/fpga_verilog/verilog_grid.cpp
View File

@ -23,6 +23,7 @@
#include "openfpga_reserved_words.h" #include "openfpga_reserved_words.h"
#include "openfpga_naming.h" #include "openfpga_naming.h"
#include "openfpga_physical_tile_utils.h"
#include "pb_type_utils.h" #include "pb_type_utils.h"
#include "circuit_library_utils.h" #include "circuit_library_utils.h"
#include "module_manager_utils.h" #include "module_manager_utils.h"
@ -375,13 +376,21 @@ void print_verilog_grids(const ModuleManager& module_manager,
if (true == is_empty_type(&physical_tile)) { if (true == is_empty_type(&physical_tile)) {
continue; continue;
} else if (true == is_io_type(&physical_tile)) { } else if (true == is_io_type(&physical_tile)) {
/* Special for I/O block, generate one module for each border side */ /* Special for I/O block:
for (int iside = 0; iside < NUM_SIDES; iside++) { * We will search the grids and see where the I/O blocks are located:
SideManager side_manager(iside); * - If a I/O block locates on border sides of FPGA fabric:
* i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT},
* we will generate one module for each border side
* - If a I/O block locates in the center of FPGA fabric:
* we will generate one module with NUM_SIDES (same treatment as regular grids)
*/
std::set<e_side> io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid,
&physical_tile);
for (const e_side& io_type_side : io_type_sides) {
print_verilog_physical_tile_netlist(module_manager, netlist_names, print_verilog_physical_tile_netlist(module_manager, netlist_names,
verilog_dir, subckt_dir, verilog_dir, subckt_dir,
&physical_tile, &physical_tile,
side_manager.get_side(), io_type_side,
use_explicit_mapping); use_explicit_mapping);
} }
continue; continue;