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skip rotating mirror detection which is too time-consuming

This commit is contained in:
tangxifan 2019-05-25 23:41:46 -06:00
parent 22e71f5847
commit 4b852afeac
4 changed files with 10 additions and 7 deletions
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4
vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_template.xml
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@ -150,8 +150,8 @@
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->
<!-- Physical descriptions begin --> <!-- Physical descriptions begin -->
<!--layout auto="1.0"/--> <layout auto="1.0"/>
<layout height="20" width="20"/> <!--layout height="20" width="20"/-->
<spice_settings> <spice_settings>
<parameters> <parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/> <options sim_temp="25" post="off" captab="off" fast="on"/>

3
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
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@ -1074,10 +1074,11 @@ DeviceRRSwitchBlock build_device_rr_switch_blocks(int LL_num_rr_nodes, t_rr_node
vpr_printf(TIO_MESSAGE_INFO, vpr_printf(TIO_MESSAGE_INFO,
"Detect %d independent switch blocks from %d switch blocks.\n", "Detect %d independent switch blocks from %d switch blocks.\n",
LL_device_rr_switch_block.get_num_unique_mirror(), (nx + 1) * (ny + 1) ); LL_device_rr_switch_block.get_num_unique_mirror(), (nx + 1) * (ny + 1) );
/* Skip rotating mirror searching
vpr_printf(TIO_MESSAGE_INFO, vpr_printf(TIO_MESSAGE_INFO,
"Detect %d rotatable unique switch blocks from %d switch blocks.\n", "Detect %d rotatable unique switch blocks from %d switch blocks.\n",
LL_device_rr_switch_block.get_num_rotatable_mirror(), (nx + 1) * (ny + 1) ); LL_device_rr_switch_block.get_num_rotatable_mirror(), (nx + 1) * (ny + 1) );
*/
return LL_device_rr_switch_block; return LL_device_rr_switch_block;
} }

8
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp
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@ -1434,6 +1434,8 @@ void DeviceRRSwitchBlock::add_rr_switch_block(DeviceCoordinator& coordinator,
rr_switch_block_mirror_id_[coordinator.get_x()][coordinator.get_y()] = unique_mirror_.size() - 1; rr_switch_block_mirror_id_[coordinator.get_x()][coordinator.get_y()] = unique_mirror_.size() - 1;
} }
return; /* skip rotable mirror searching...*/
/* add rotatable mirror support */ /* add rotatable mirror support */
for (size_t mirror_id = 0; mirror_id < get_num_rotatable_mirror(); ++mirror_id) { for (size_t mirror_id = 0; mirror_id < get_num_rotatable_mirror(); ++mirror_id) {
RRSwitchBlock rotate_mirror = rr_switch_block; RRSwitchBlock rotate_mirror = rr_switch_block;
@ -1476,8 +1478,8 @@ void DeviceRRSwitchBlock::add_rr_switch_block(DeviceCoordinator& coordinator,
/* Rotate TOP and BOTTOM only */ /* Rotate TOP and BOTTOM only */
RRSwitchBlock rotate_y_mirror = rotate_mirror; RRSwitchBlock rotate_y_mirror = rotate_mirror;
rotate_y_mirror.rotate_side(TOP, 1); rotate_y_mirror.rotate_side(TOP, 2);
rotate_y_mirror.rotate_side(BOTTOM, 1); rotate_y_mirror.rotate_side(BOTTOM, 2);
if (true == get_switch_block(rotatable_mirror_[mirror_id]).is_mirror(rotate_y_mirror)) { if (true == get_switch_block(rotatable_mirror_[mirror_id]).is_mirror(rotate_y_mirror)) {
/* This is a mirror, raise the flag and we finish */ /* This is a mirror, raise the flag and we finish */
@ -1488,7 +1490,7 @@ void DeviceRRSwitchBlock::add_rr_switch_block(DeviceCoordinator& coordinator,
} }
/* Rotate all sides */ /* Rotate all sides */
rotate_mirror.rotate(1); rotate_mirror.rotate(2);
} }
if (false == is_rotatable_mirror) { if (false == is_rotatable_mirror) {
break; break;

2
vpr7_x2p/vpr/go_fpga_verilog.sh
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@ -39,6 +39,6 @@ rm -rf $verilog_output_dirpath/$verilog_output_dirname
#valgrind #valgrind
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl ./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl
#./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname\_compact --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_x2p_compact_routing_hierarchy --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl ./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname\_compact --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_x2p_compact_routing_hierarchy --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl