From 4b77a3a57481af6014140aef4a7a23edab5ecd24 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 29 Jan 2021 11:33:40 -0700 Subject: [PATCH] [Tool] Now activity file is not a manadatory input of openfpga tools --- openfpga/src/annotation/annotate_simulation_setting.cpp | 6 ++++++ openfpga/src/base/openfpga_context.h | 5 ----- openfpga/src/base/openfpga_link_arch.cpp | 9 ++++++--- openfpga/src/base/openfpga_setup_command.cpp | 2 +- 4 files changed, 13 insertions(+), 9 deletions(-) diff --git a/openfpga/src/annotation/annotate_simulation_setting.cpp b/openfpga/src/annotation/annotate_simulation_setting.cpp index 960be6e68..1e27b1c8e 100644 --- a/openfpga/src/annotation/annotate_simulation_setting.cpp +++ b/openfpga/src/annotation/annotate_simulation_setting.cpp @@ -237,6 +237,12 @@ int annotate_simulation_setting(const AtomContext& atom_ctx, */ VTR_LOG("User specified the number of operating clock cycles to be inferred from signal activities\n"); + /* Error out if net activity is not defined */ + if (true == net_activity.empty()) { + VTR_LOG_ERROR("Signal activities are not defined!\nPlease check if activity file is given and properly generated!\n"); + return CMD_EXEC_FATAL_ERROR; + } + /* Use a fixed simulation window size now. TODO: this could be specified by users */ size_t num_clock_cycles = recommend_num_sim_clock_cycle(atom_ctx, net_activity, diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h index c59219ed2..a6ea28ace 100644 --- a/openfpga/src/base/openfpga_context.h +++ b/openfpga/src/base/openfpga_context.h @@ -67,7 +67,6 @@ class OpenfpgaContext : public Context { const openfpga::FabricBitstream& fabric_bitstream() const { return fabric_bitstream_; } const openfpga::IoLocationMap& io_location_map() const { return io_location_map_; } const openfpga::FabricGlobalPortInfo& fabric_global_port_info() const { return fabric_global_port_info_; } - const std::unordered_map& net_activity() const { return net_activity_; } const openfpga::NetlistManager& verilog_netlists() const { return verilog_netlists_; } const openfpga::NetlistManager& spice_netlists() const { return spice_netlists_; } public: /* Public mutators */ @@ -88,7 +87,6 @@ class OpenfpgaContext : public Context { openfpga::FabricBitstream& mutable_fabric_bitstream() { return fabric_bitstream_; } openfpga::IoLocationMap& mutable_io_location_map() { return io_location_map_; } openfpga::FabricGlobalPortInfo& mutable_fabric_global_port_info() { return fabric_global_port_info_; } - std::unordered_map& mutable_net_activity() { return net_activity_; } openfpga::NetlistManager& mutable_verilog_netlists() { return verilog_netlists_; } openfpga::NetlistManager& mutable_spice_netlists() { return spice_netlists_; } private: /* Internal data */ @@ -138,9 +136,6 @@ class OpenfpgaContext : public Context { openfpga::NetlistManager verilog_netlists_; openfpga::NetlistManager spice_netlists_; - /* Net activities of users' implementation */ - std::unordered_map net_activity_; - /* Flow status */ openfpga::FlowManager flow_manager_; }; diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp index 567a9a62c..efedf9584 100644 --- a/openfpga/src/base/openfpga_link_arch.cpp +++ b/openfpga/src/base/openfpga_link_arch.cpp @@ -148,8 +148,11 @@ int link_arch(OpenfpgaContext& openfpga_ctx, * should be inferred from FPGA implmentation * - When FPGA-SPICE is enabled */ - openfpga_ctx.mutable_net_activity() = read_activity(g_vpr_ctx.atom().nlist, - cmd_context.option_value(cmd, opt_activity_file).c_str()); + std::unordered_map net_activity; + if (true == cmd_context.option_enable(cmd, opt_activity_file)) { + net_activity = read_activity(g_vpr_ctx.atom().nlist, + cmd_context.option_value(cmd, opt_activity_file).c_str()); + } /* TODO: Annotate the number of clock cycles and clock frequency by following VPR results * We SHOULD create a new simulation setting for OpenFPGA use only @@ -160,7 +163,7 @@ int link_arch(OpenfpgaContext& openfpga_ctx, */ //openfpga_ctx.mutable_simulation_setting() = openfpga_ctx.mutable_arch().sim_setting; if (CMD_EXEC_FATAL_ERROR == annotate_simulation_setting(g_vpr_ctx.atom(), - openfpga_ctx.net_activity(), + net_activity, openfpga_ctx.mutable_simulation_setting())) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp index eb0e0430d..7e484731d 100644 --- a/openfpga/src/base/openfpga_setup_command.cpp +++ b/openfpga/src/base/openfpga_setup_command.cpp @@ -125,7 +125,7 @@ ShellCommandId add_openfpga_link_arch_command(openfpga::Shell& Command shell_cmd("link_openfpga_arch"); /* Add an option '--activity_file'*/ - CommandOptionId opt_act_file = shell_cmd.add_option("activity_file", true, "file path to the signal activity"); + CommandOptionId opt_act_file = shell_cmd.add_option("activity_file", false, "file path to the signal activity"); shell_cmd.set_option_require_value(opt_act_file, openfpga::OPT_STRING); /* Add an option '--sort_gsb_chan_node_in_edges'*/