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[core] now name indexing is applied to netlist names

This commit is contained in:
tangxifan 2023-10-19 23:03:48 -07:00
parent f680bdaec3
commit 4b00651a46
1 changed files with 11 additions and 3 deletions
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14
openfpga/src/fpga_verilog/verilog_routing.cpp
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@ -85,6 +85,11 @@ static void print_verilog_routing_connection_box_unique_module(
rr_gsb.get_cb_y(cb_type)); rr_gsb.get_cb_y(cb_type));
std::string verilog_fname(generate_connection_block_netlist_name( std::string verilog_fname(generate_connection_block_netlist_name(
cb_type, gsb_coordinate, std::string(VERILOG_NETLIST_FILE_POSTFIX))); cb_type, gsb_coordinate, std::string(VERILOG_NETLIST_FILE_POSTFIX)));
std::string orig_module_name = generate_connection_block_module_name(cb_type, gsb_coordinate);
if (module_name_map.name_exist(orig_module_name)) {
verilog_fname = generate_tile_module_netlist_name(module_name_map.name(orig_module_name), std::string(VERILOG_NETLIST_FILE_POSTFIX));
}
std::string verilog_fpath(subckt_dir + verilog_fname); std::string verilog_fpath(subckt_dir + verilog_fname);
/* Create the file stream */ /* Create the file stream */
@ -102,8 +107,7 @@ static void print_verilog_routing_connection_box_unique_module(
/* Create a Verilog Module based on the circuit model, and add to module /* Create a Verilog Module based on the circuit model, and add to module
* manager */ * manager */
std::string cb_module_name = module_name_map.name( std::string cb_module_name = module_name_map.name(orig_module_name);
generate_connection_block_module_name(cb_type, gsb_coordinate));
ModuleId cb_module = module_manager.find_module(cb_module_name); ModuleId cb_module = module_manager.find_module(cb_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
@ -200,6 +204,10 @@ static void print_verilog_routing_switch_box_unique_module(
std::string verilog_fname(generate_routing_block_netlist_name( std::string verilog_fname(generate_routing_block_netlist_name(
SB_VERILOG_FILE_NAME_PREFIX, gsb_coordinate, SB_VERILOG_FILE_NAME_PREFIX, gsb_coordinate,
std::string(VERILOG_NETLIST_FILE_POSTFIX))); std::string(VERILOG_NETLIST_FILE_POSTFIX)));
std::string orig_module_name = generate_switch_block_module_name(gsb_coordinate);
if (module_name_map.name_exist(orig_module_name)) {
verilog_fname = generate_tile_module_netlist_name(module_name_map.name(orig_module_name), std::string(VERILOG_NETLIST_FILE_POSTFIX));
}
std::string verilog_fpath(subckt_dir + verilog_fname); std::string verilog_fpath(subckt_dir + verilog_fname);
/* Create the file stream */ /* Create the file stream */
@ -218,7 +226,7 @@ static void print_verilog_routing_switch_box_unique_module(
/* Create a Verilog Module based on the circuit model, and add to module /* Create a Verilog Module based on the circuit model, and add to module
* manager */ * manager */
std::string sb_module_name = std::string sb_module_name =
module_name_map.name(generate_switch_block_module_name(gsb_coordinate)); module_name_map.name(orig_module_name);
ModuleId sb_module = module_manager.find_module(sb_module_name); ModuleId sb_module = module_manager.find_module(sb_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); VTR_ASSERT(true == module_manager.valid_module_id(sb_module));