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[Architecture] Adapt openfpga architecture to follow the renamed adder cell

This commit is contained in:
tangxifan 2020-09-24 20:09:29 -06:00
parent 53187044e6
commit 4ada793c84
13 changed files with 123 additions and 123 deletions
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18
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -183,15 +183,15 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -226,7 +226,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 --> <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

18
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -183,15 +183,15 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram1k.v"> <circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram1k.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -238,7 +238,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 --> <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

18
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -183,15 +183,15 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram1k.v"> <circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram1k.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -242,7 +242,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 --> <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

22
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -183,15 +183,15 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram1k.v"> <circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram1k.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -209,8 +209,8 @@
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="32"/> <port type="input" prefix="a" lib_name="A" size="32"/>
<port type="input" prefix="b" size="32"/> <port type="input" prefix="b" lib_name="B" size="32"/>
<port type="output" prefix="out" size="64"/> <port type="output" prefix="out" size="64"/>
<!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes --> <!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="LATCHR" default_val="1"/> <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
@ -248,7 +248,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 --> <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

18
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -184,15 +184,15 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -227,7 +227,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' --> <!-- Binding operating pb_types in mode 'n2_lut5' -->
<pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">

22
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -184,22 +184,22 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="mult_36x36" prefix="mult_36x36" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/mult_36x36.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/mult_36x36.v"> <circuit_model type="hard_logic" name="mult_36x36" prefix="mult_36x36" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/mult_36x36.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/mult_36x36.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="36"/> <port type="input" prefix="a" lib_name="A" size="36"/>
<port type="input" prefix="b" size="36"/> <port type="input" prefix="b" lib_name="B" size="36"/>
<port type="output" prefix="out" size="72"/> <port type="output" prefix="out" size="72"/>
<!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes --> <!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/> <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
@ -253,7 +253,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' --> <!-- Binding operating pb_types in mode 'n2_lut5' -->
<pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">

18
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -184,15 +184,15 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram16k.v"> <circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram16k.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -239,7 +239,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' --> <!-- Binding operating pb_types in mode 'n2_lut5' -->
<pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">

18
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -184,15 +184,15 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram16k.v"> <circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram16k.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
@ -251,7 +251,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' --> <!-- Binding operating pb_types in mode 'n2_lut5' -->
<pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">

18
openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -184,15 +184,15 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -227,7 +227,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' --> <!-- Binding operating pb_types in mode 'n2_lut5' -->
<pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">

18
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -184,15 +184,15 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -228,7 +228,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' --> <!-- Binding operating pb_types in mode 'n2_lut5' -->
<pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">

18
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -189,15 +189,15 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -234,7 +234,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/> <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="SDFFSRQ"/> <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="SDFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' --> <!-- Binding operating pb_types in mode 'n2_lut5' -->
<pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">

18
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -189,15 +189,15 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -229,7 +229,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/> <pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb.fle[physical].ff_phy" circuit_model_name="SDFFSRQ"/> <pb_type name="clb.fle[physical].ff_phy" circuit_model_name="SDFFSRQ"/>
<pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' --> <!-- Binding operating pb_types in mode 'n2_lut5' -->
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">

22
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12
@ -204,15 +204,15 @@
<port type="input" prefix="outpad" lib_name="A" size="1"/> <port type="input" prefix="outpad" lib_name="A" size="1"/>
<port type="output" prefix="inpad" lib_name="Y" size="1"/> <port type="output" prefix="inpad" lib_name="Y" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v"> <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="a" size="1"/> <port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" size="1"/> <port type="input" prefix="b" lib_name="B" size="1"/>
<port type="input" prefix="cin" size="1"/> <port type="input" prefix="cin" lib_name="CI" size="1"/>
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" lib_name="CO" size="1"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
@ -244,7 +244,7 @@
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/> <pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/>
<pb_type name="clb.fle[physical].ff_phy" circuit_model_name="SDFFSRQ"/> <pb_type name="clb.fle[physical].ff_phy" circuit_model_name="SDFFSRQ"/>
<pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/> <pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' --> <!-- Binding operating pb_types in mode 'n2_lut5' -->
<pb_type name="clb.fle[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5"> <pb_type name="clb.fle[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb.fle[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
@ -279,7 +279,7 @@
<!-- Binding regular FLEs --> <!-- Binding regular FLEs -->
<pb_type name="clb_spypad.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/> <pb_type name="clb_spypad.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/>
<pb_type name="clb_spypad.fle[physical].ff_phy" circuit_model_name="SDFFSRQ"/> <pb_type name="clb_spypad.fle[physical].ff_phy" circuit_model_name="SDFFSRQ"/>
<pb_type name="clb_spypad.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/> <pb_type name="clb_spypad.fle[physical].frac_logic.adder_phy" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' --> <!-- Binding operating pb_types in mode 'n2_lut5' -->
<pb_type name="clb_spypad.fle[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb_spypad.fle[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5"> <pb_type name="clb_spypad.fle[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb_spypad.fle[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
@ -312,7 +312,7 @@
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6_spypad" mode_bits="00"/> <pb_type name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6_spypad" mode_bits="00"/>
<pb_type name="clb_spypad.fle_spypad[physical].ff_phy" circuit_model_name="SDFFSRQ"/> <pb_type name="clb_spypad.fle_spypad[physical].ff_phy" circuit_model_name="SDFFSRQ"/>
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.adder_phy" circuit_model_name="adder"/> <pb_type name="clb_spypad.fle_spypad[physical].frac_logic.adder_phy" circuit_model_name="ADDF"/>
<!-- Binding operating pb_type to physical pb_type --> <!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' --> <!-- Binding operating pb_types in mode 'n2_lut5' -->
<pb_type name="clb_spypad.fle_spypad[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5"> <pb_type name="clb_spypad.fle_spypad[n2_lut5].lut5inter.ble5[blut5].flut5.lut5" physical_pb_type_name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">