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[Tool] Rework simulation time period to be sync with actual stimuli

This commit is contained in:
tangxifan 2020-12-02 22:58:13 -07:00
parent b661c39b04
commit 4aa6264b1c
6 changed files with 28 additions and 20 deletions
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8
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -250,10 +250,10 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
clock_port_names,
std::string(DEFAULT_CLOCK_NAME));
int simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME,
simulation_parameters.num_clock_cycles(),
1./simulation_parameters.operating_clock_frequency(),
VERILOG_SIM_TIMESCALE);
float simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME,
simulation_parameters.num_clock_cycles(),
1./simulation_parameters.operating_clock_frequency(),
VERILOG_SIM_TIMESCALE);
/* Add Icarus requirement */
print_verilog_timeout_and_vcd(fp,

4
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -299,7 +299,7 @@ void print_verilog_timeout_and_vcd(std::fstream& fp,
const std::string& vcd_fname,
const std::string& simulation_start_counter_name,
const std::string& error_counter_name,
const int& simulation_time) {
const float& simulation_time) {
/* Validate the file stream */
valid_file_stream(fp);
@ -328,7 +328,7 @@ void print_verilog_timeout_and_vcd(std::fstream& fp,
fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl;
fp << "\t$display(\"Simulation start\");" << std::endl;
print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------"));
fp << "\t#" << simulation_time << std::endl;
fp << "\t#" << std::setprecision(10) << simulation_time << std::endl;
fp << "\tif(" << error_counter_name << " == 0) begin" << std::endl;
fp << "\t\t$display(\"Simulation Succeed\");" << std::endl;
fp << "\tend else begin" << std::endl;

2
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -58,7 +58,7 @@ void print_verilog_timeout_and_vcd(std::fstream& fp,
const std::string& vcd_fname,
const std::string& simulation_start_counter_name,
const std::string& error_counter_name,
const int& simulation_time);
const float& simulation_time);
BasicPort generate_verilog_testbench_clock_port(const std::vector<std::string>& clock_port_names,
const std::string& default_clock_name);

6
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -1958,14 +1958,16 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
1./simulation_parameters.operating_clock_frequency());
/* Add Icarus requirement */
/* Add Icarus requirement:
* Always ceil the simulation time so that we test a sufficient length of period!!!
*/
print_verilog_timeout_and_vcd(fp,
std::string(ICARUS_SIMULATOR_FLAG),
std::string(circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX)),
std::string(circuit_name + std::string("_formal.vcd")),
std::string(TOP_TESTBENCH_SIM_START_PORT_NAME),
std::string(TOP_TESTBENCH_ERROR_COUNTER),
(int)simulation_time);
std::ceil(simulation_time));
/* Testbench ends*/

20
openfpga/src/utils/simulation_utils.cpp
View File

@ -14,14 +14,14 @@ namespace openfpga {
/********************************************************************
* Compute the time period for the simulation
*******************************************************************/
int find_operating_phase_simulation_time(const int& factor,
const int& num_op_clock_cycles,
const float& op_clock_period,
const float& timescale) {
float find_operating_phase_simulation_time(const int& factor,
const int& num_op_clock_cycles,
const float& op_clock_period,
const float& timescale) {
/* Take into account the prog_reset and reset cycles
* 1e9 is to change the unit to ns rather than second
*/
return (factor * num_op_clock_cycles * op_clock_period) / timescale;
return ((float)factor * (float)num_op_clock_cycles * op_clock_period) / timescale;
}
/********************************************************************
@ -37,8 +37,14 @@ float find_simulation_time_period(const float &time_unit,
const float &op_clock_period) {
float total_time_period = 0.;
/* Take into account the prog_reset and reset cycles */
total_time_period = (num_prog_clock_cycles + 2) * prog_clock_period + num_op_clock_cycles * op_clock_period;
/* Take into account
* - the prog_reset
* - the gap clock cycle between programming and operating phase
* - 2 reset cycles before operating phase starts
* This is why the magic number 2 and 2 are added
*/
total_time_period = ((float)num_prog_clock_cycles + 2) * prog_clock_period
+ ((float)num_op_clock_cycles + 2) * op_clock_period;
total_time_period = total_time_period / time_unit;
return total_time_period;

8
openfpga/src/utils/simulation_utils.h
View File

@ -12,10 +12,10 @@
/* begin namespace openfpga */
namespace openfpga {
int find_operating_phase_simulation_time(const int& factor,
const int& num_op_clock_cycles,
const float& op_clock_period,
const float& timescale);
float find_operating_phase_simulation_time(const int& factor,
const int& num_op_clock_cycles,
const float& op_clock_period,
const float& timescale);
float find_simulation_time_period(const float& time_unit,
const int& num_prog_clock_cycles,