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Flatten_hierarchy_doc

This commit is contained in:
Aurelien Alacchi 2018-10-18 16:28:12 -06:00
parent aa5449c37d
commit 4a950c6857
8 changed files with 121 additions and 117 deletions
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115
docs/source/arch_lang/circuit_modules.rst
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@ -12,8 +12,9 @@ Define circuit_models
.. code-block:: xml
<module_circuit_models>
<circuit_model type="string" name="string" prefix="string" is_default="int" [spice|verilog]_netlist="string" dump_structural_verilog="string">
<transistor-level circuit design features>
<circuit_model type="string" name="string" prefix="string" is_default="int"
spice_netlist="string" verilog_netlist="string" dump_structural_verilog="string">
<transistor-level circuit_design_features="developped_further" />
</circuit_model>
</module_circuit_models>
@ -47,12 +48,15 @@ Transistor level
.. code-block:: xml
<circuit_model type="string" name="string" prefix="string" is_default="int" netlist="string" dump_structural_verilog="string">
<circuit_model type="string" name="string" prefix="string" is_default="int" netlist="string"
dump_structural_verilog="string">
<design_technology type="string"/>
<input_buffer exist="string" circuit_model_name="string"/>
<output_buffer exist="string" circuit_model_name="string"/>
<pass_gate_logic type="string" circuit_model_name="string"/>
<port type="string" prefix="string" size="int" default_val="int" circuit_model_name="string" mode_select="boolean" is_global="boolean" is_set="boolean" is_reset="boolean" is_config_enable="boolean"/>
<port type="string" prefix="string" size="int" default_val="int" circuit_model_name="string"
mode_select="boolean" is_global="boolean" is_set="boolean" is_reset="boolean"
is_config_enable="boolean"/>
</circuit_model>
* design_technology :
@ -102,7 +106,7 @@ Inverters and Buffers
.. code-block:: xml
<circuit_model type="inv_buf" name="string" prefix="string" netlist="string" is_default="int"/>
<circuit_model type="inv_buf" name="string" prefix="string" netlist="string" is_default="int">
<design_technology type="cmos" topology="string" size="int" tapered="off"/>
<port type="input" prefix="string" size="int"/>
<port type="output" prefix="string" size="int"/>
@ -140,8 +144,8 @@ The XML code describing this inverter is:
<circuit_model type="inv_buf" name="inv1x" prefix="inv1x">
<design_technology type="cmos" topology="inverter" size="1"/>
<port_type="input" prefix="in" size="1"/>
<port_type="output" prefix="out" size="1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
This example shows:
@ -168,8 +172,8 @@ The XML code describing this buffer is:
<circuit_model type="inv_buf" name="buf2" prefix="buf2">
<design_technology type="cmos" topology="buffer" size="2"/>
<port_type="input" prefix="in" size="1"/>
<port_type="output" prefix="out" size="1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
This example shows:
@ -195,9 +199,10 @@ The XML code describing this inverter is:
.. code-block:: xml
<circuit_model type="inv_buf" name="tapdrive4" prefix="tapdrive4">
<design_technology type="cmos" topology=”inverter" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port_type="input" prefix="in" size="1"/>
<port_type="output" prefix="out" size="1"/>
<design_technology type="cmos" topology=”inverter" size="1" tapered="on" tap_drive_level="3"
f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
@ -206,7 +211,7 @@ This example shows:
* Size of 1 for the first stage output strength
* The tapered parameter is on. Then the required sub parameters are declared
* The number of stage is set to 3 by tap_drive_level
* f_per_stage is set to 4. Then 2nd stage output strength is 4* the 1st stage output strength (so 4*1 = 4) and the 3rd stage output strength is 4* the 2nd stage output strength (so 4*4 =
* f_per_stage is set to 4. Then 2nd stage output strength is 4* the 1st stage output strength (so 4*1 = 4) and the 3rd stage output strength is 4* the 2nd stage output strength (so 4*4 = 16).
Pass-gate Logic
@ -214,8 +219,8 @@ Pass-gate Logic
.. code-block:: xml
<circuit_model type="pass_gate" name="string" prefix="string" netlist="string" is_default="int"/>
<design_technology type="cmos" topology="string" nmos_size="int" pmos_size="int" tapered="off"/>
<circuit_model type="pass_gate" name="string" prefix="string" netlist="string" is_default="int">
<design_technology type="cmos" topology="string" nmos_size="int" pmos_size="int"/>
<input_buffer exist="string" circuit_model_name="string" />
<output_buffer exist="string" circuit_model_name="string" />
<port type="input" prefix="string" size="int"/>
@ -248,12 +253,12 @@ The XML code describing this pass-gate is:
.. code-block:: xml
<circuit_model_type="pass_gate" name="tgate" prefix="tgate">
<circuit_model type="pass_gate" name="tgate" prefix="tgate">
<design_technology type="cmos" topology="transmission_gate"/>
<port_type="input" prefix="in" size="1"/>
<port_type="input" prefix="sram" size="1"/>
<port_type="input" prefix="sramb" size="1"/>
<port_type="output" prefix="out" size="1"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sram" size="1"/>
<port type="input" prefix="sramb" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
This example shows:
@ -277,11 +282,11 @@ The XML code describing this pass-gate is:
.. code-block:: xml
<circuit_model_type="pass_gate" name="t_pass" prefix="t_pass">
<circuit_model type="pass_gate" name="t_pass" prefix="t_pass">
<design_technology type="cmos" topology="pass_transistor"/>
<port_type="input" prefix="in" size="1"/>
<port_type="input" prefix="sram" size="1"/>
<port_type="output" prefix="out" size="1"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sram" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
This example shows:
@ -315,8 +320,9 @@ Multiplexers
.. code-block:: xml
<circuit_model type="mux" name="string" prefix="string" is_default="int"/>
<design_technology type="string" structure="string" num_level="int" ron="float" roff="float" prog_transistor_size="float"/>
<circuit_model type="mux" name="string" prefix="string" is_default="int">
<design_technology type="string" structure="string" num_level="int" ron="float" roff="float"
prog_transistor_size="float"/>
<input_buffer exist="string" circuit_model_name="string"/>
<output_buffer exist="string" circuit_model_name="string"/>
<pass_gate_logic type="string" circuit_model_name="string"/>
@ -360,15 +366,15 @@ The code describing this Multiplexer is:
.. code-block:: xml
<circuit model type="mux" name="mux 1level" prefix="mux 1level">
<design technology type="cmos" structure="one-level"/>
<input buffer exist="on" circuit model name="inv1x"/>
<output buffer exist="on" circuit model name="tapbuf4"/>
<pass gate logic circuit model name="tgate"/>
<circuit_model type="mux" name="mux_1level" prefix="mux_1level">
<design_technology type="cmos" structure="one-level"/>
<input_buffer exist="on" circuit_model_name="inv1x"/>
<output_buffer exist="on" circuit_model_name="tapbuf4"/>
<pass_gate_logic circuit_model_name="tgate"/>
<port type="input" prefix="in" size="4"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="4"/>
</circuit model>
</circuit_model>
**This example shows:**
* Each circuit model composing the Multiplexer
@ -391,14 +397,14 @@ If we arbitrarily fix the number of Mux entries at 4, the following code could i
.. code-block:: xml
<circuit_model_type="mux" name="mux_tree" prefix="mux_tree">
<circuit_model type="mux" name="mux_tree" prefix="mux_tree">
<design_technology type="cmos" structure="tree"/>
<input_buffer exist="on" circuit_model_name="inv1x"/>
<output_buffer exist="on" circuit_model_name="tapdrive4"/>
<pass_gate_logic circuit_model_name="tgate"/>
<port_type="input" prefix="in" size="4"/>
<port_type="output" prefix="out" size="1"/>
<port_type="sram" prefix="sram" size="3"/>
<port type="input" prefix="in" size="4"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="3"/>
</circuit_model>
**This example shows:**
@ -459,9 +465,9 @@ The code describing this LUT is:
<output_buffer exist="on" circuit_model_name="inv1x"/>
<lut_input_buffer exist="on" circuit_model_name="buf2"/>
<pass_gate_logic circuit_model_name="tgate"/>
<port_type="input" prefix="in" size="6"/>
<port_type="output" prefix="out" size="1"/>
<port_type="sram" prefix="sram" size="64"/>
<port type="input" prefix="in" size="6"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="64"/>
</circuit_model>
**This example shows:**
@ -511,11 +517,11 @@ The code describing this FF is:
.. code-block:: xml
<circuit_model type="ff" name="dff" prefix="dff" verilog_netlist="ff.v">
<port_type="input" prefix="D" size="1"/>
<port_type="input" prefix="Set" size="1" is_global="true"/>
<port_type="input" prefix="Reset" size="1" is_global="true"/>
<port_type="output" prefix="Q" size="1"/>
<port_type="clock" prefix="clk" size="1" is_global="true"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1" is_global="true"/>
<port type="input" prefix="Reset" size="1" is_global="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true"/>
</circuit_model>
**This example shows:**
@ -540,9 +546,9 @@ The code describing this FF is:
.. code-block:: xml
<circuit_model type="scff" name="scff" prefix="scff" verilog_netlist="scff.v">
<port_type="input" prefix="D" size="1"/>
<port_type="output" prefix="Q" size="2"/>
<port_type="clock" prefix="clk" size="1" is_global="true"/>
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="2"/>
<port type="clock" prefix="clk" size="1" is_global="true"/>
</circuit_model>
**This example shows:**
@ -648,7 +654,8 @@ I/O pads
<output_buffer exist="string" circuit_model_name="string"/>
<port type="input" prefix="string" size="int"/>
<port type="output" prefix="string" size="int"/>
<port type="sram" prefix="string" size="int" mode_select="true|false" circuit_model_name="string" default_val="int"/>
<port type="sram" prefix="string" size="int" mode_select="true|false"
circuit_model_name="string" default_val="int"/>
</circuit_model>
.. note:: The circuit designs of I/O pads are highly dependent on the technology node and well optimized by engineers.
@ -677,11 +684,11 @@ The code describing this IO-Pad is:
.. code-block:: xml
<circuit_model type="iopad" name="iopad" prefix="iopad" verilog_netlist="io.v">
<port_type="inout" prefix="pad" size="1"/>
<port_type="sram" prefix="dir" size="1" circuit_model_name="scff"/>
<port_type="input" prefix="data_in" size="1"/>
<port_type="input" prefix="zin" size="1" is_global="true"/>
<port_type="output" prefix="data out" size="1"/>
<port type="inout" prefix="pad" size="1"/>
<port type="sram" prefix="dir" size="1" circuit_model_name="scff"/>
<port type="input" prefix="data_in" size="1"/>
<port type="input" prefix="zin" size="1" is_global="true"/>
<port type="output" prefix="data out" size="1"/>
</circuit_model>
**This example shows**
@ -689,5 +696,3 @@ The code describing this IO-Pad is:
* The association of the verilog netlist file *io.v*
* The inout pad port_type, which means as inout as output.
* The instantiation of a SCFF as sram

2
docs/source/arch_lang/index.rst
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@ -1,5 +1,5 @@
Extended Architecture Description Language
====================================
==========================================
.. _arch_lang:
Extended FPGA Architecture Description Language

5
docs/source/fpga_bitstream/index.rst
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@ -1,4 +1,7 @@
.. _fpga_bistream:
FPGA-Bitstream
=============
.. _fpga_bitstream:
User Manual for FPGA Bitstream Generator
.. toctree::

2
docs/source/fpga_spice/command_line_usage.rst
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@ -34,7 +34,7 @@ FPGA-SPICE Supported Options::
.. csv-table:: Commmand-line Options of FPGA-SPICE
:header: "Command Options", "Description"
:widths: 15, 30
:widths: 15, 20
"--fpga_spice", "Turn on the FPGA-SPICE."
"--fpga_spice_dir <dir_path>", "Specify the directory that all the SPICE netlists will be outputted to. <dir_path> is the destination directory."

3
docs/source/fpga_spice/index.rst
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@ -1,3 +1,6 @@
FPGA-SPICE: SPICE Auto-Generation
====================================
.. _fpga_spice:
User Manual for FPGA-SPICE support

2
docs/source/fpga_verilog/command_line_usage.rst
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@ -7,6 +7,7 @@ FPGA-Verilog Supported Options::
--fpga_verilog
--fpga_verilog_dir <directory_path_of_dumped_verilog_files>
--fpga_verilog_print_top_testbench
.. csv-table:: Commmand-line Options of FPGA-Verilog
:header: "Command Options", "Description"
@ -14,6 +15,7 @@ FPGA-Verilog Supported Options::
"--fpga_verilog", "Turn on the FPGA-Verilog."
"--fpga_verilog_dir <dir_path>", "Specify the directory that all the Verilog files will be outputted to. <dir_path> is the destination directory."
"--fpga_verilog_print_top_testbench", "Print the full-chip-level testbench for the FPGA."
.. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are:

4
docs/source/fpga_verilog/index.rst
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@ -1,5 +1,5 @@
FPGA-VERILOG: VERILOG AUTO-GENERATION
=====================================
FPGA-Verilog: Verilog Auto-Generation
-------------------------------------
.. _fpga_verilog:
User Manual for FPGA Verilog Generator

13
docs/source/index.rst
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@ -22,28 +22,19 @@ For more information on the original FPGA architecture description language see
.. toctree::
:maxdepth: 2
:caption: Extended Architecture Description Language
:caption: Tools Guide
arch_lang/index
.. toctree::
:caption: FPGA-SPICE: SPICE Auto-Generation
fpga_spice/index
.. toctree::
:caption: FPGA-Verilog: Verilog Auto-Generation
fpga_verilog/index
.. toctree::
:caption: FPGA-Bitstream: Bitstream Generator
fpga_bitstream/index
.. toctree::
:maxdepth: 2
:caption: Tutorial
:caption: User Guide
tutorials/index